From 02cf60fd25e0728d91f698d5114ea5c84b0ea61b Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 11:14:56 -0400 Subject: [PATCH 01/12] Hellen says DRV manual change pick --- firmware/integration/rusefi_config.txt | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/firmware/integration/rusefi_config.txt b/firmware/integration/rusefi_config.txt index 47fb83a0b1..2259b28dd8 100644 --- a/firmware/integration/rusefi_config.txt +++ b/firmware/integration/rusefi_config.txt @@ -738,7 +738,11 @@ custom maf_sensor_type_e 4 bits, S32, @OFFSET@, [0:7], @@maf_sensor_type_e_enum@ bit todoClutchDownPinInverted etb_io[ETB_COUNT iterate] etbIo ! our strategy is to get rid of "boardConfiguration" and make everything just "engineConfiguration". Please do not add new fields into legacy "bc" area. - int[119] unusedAtOldBoardConfigurationEnd; + int[118] unusedAtOldBoardConfigurationEnd; + spi_device_e drv8860spiDevice; + brain_pin_e drv8860_cs; + pin_output_mode_e drv8860_csPinMode; + brain_pin_e drv8860_miso; bit vvtDisplayInverted bit fuelClosedLoopCorrectionEnabled;+Enables lambda sensor closed loop feedback for fuelling. From 91a09425511137808e35b085bd4b2ad5c70b314e Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 11:28:51 -0400 Subject: [PATCH 02/12] Hellen says Cypress --- .../hellen/cypress/!compile-cypress.bat | 29 + .../os/common/ext/CMSIS/S6E2CxAH/base_types.h | 160 + .../ext/CMSIS/S6E2CxAH/chibios_pdl_vectors.h | 140 + .../OS/os/common/ext/CMSIS/S6E2CxAH/mcu.h | 54 + .../os/common/ext/CMSIS/S6E2CxAH/s6e2c5xh.h | 70654 +++++++++++++++ .../os/common/ext/CMSIS/S6E2CxAH/s6e2c5xl.h | 72329 ++++++++++++++++ .../common/ext/CMSIS/S6E2CxAH/system_s6e2c5.h | 753 + .../compilers/GCC/ld/cypress_S6E2CxAH.ld | 93 + .../compilers/GCC/mk/startup_S6E2CxAH.mk | 23 + .../ARMCMx/devices/S6E2CxAH/cmparams.h | 81 + .../os/hal/ports/Cypress/LLD/ADCv2/driver.mk | 6 + .../hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.c | 371 + .../hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.h | 445 + .../os/hal/ports/Cypress/LLD/CANv2/driver.mk | 9 + .../hal/ports/Cypress/LLD/CANv2/hal_can_lld.c | 424 + .../hal/ports/Cypress/LLD/CANv2/hal_can_lld.h | 369 + .../os/hal/ports/Cypress/LLD/GPIOv2/driver.mk | 13 + .../Cypress/LLD/GPIOv2/gpio_s6e2_common.h | 66 + .../ports/Cypress/LLD/GPIOv2/hal_pal_lld.c | 669 + .../ports/Cypress/LLD/GPIOv2/hal_pal_lld.h | 453 + .../os/hal/ports/Cypress/LLD/PITv2/driver.mk | 7 + .../hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.c | 337 + .../hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.h | 250 + .../hal/ports/Cypress/LLD/PITv2/hal_st_lld.c | 99 + .../hal/ports/Cypress/LLD/PITv2/hal_st_lld.h | 157 + .../os/hal/ports/Cypress/LLD/SPIv2/driver.mk | 6 + .../hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c | 467 + .../hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.h | 241 + .../os/hal/ports/Cypress/PDL/driver/adc/adc.c | 1607 + .../os/hal/ports/Cypress/PDL/driver/adc/adc.h | 576 + .../hal/ports/Cypress/PDL/driver/base_types.h | 103 + .../os/hal/ports/Cypress/PDL/driver/bt/bt.c | 2481 + .../os/hal/ports/Cypress/PDL/driver/bt/bt.h | 959 + .../os/hal/ports/Cypress/PDL/driver/can/can.c | 1396 + .../os/hal/ports/Cypress/PDL/driver/can/can.h | 478 + .../ports/Cypress/PDL/driver/can/can_pre.c | 117 + .../ports/Cypress/PDL/driver/can/can_pre.h | 98 + .../hal/ports/Cypress/PDL/driver/can/canfd.c | 1929 + .../hal/ports/Cypress/PDL/driver/can/canfd.h | 436 + .../os/hal/ports/Cypress/PDL/driver/clk/clk.c | 2031 + .../os/hal/ports/Cypress/PDL/driver/clk/clk.h | 557 + .../os/hal/ports/Cypress/PDL/driver/cr/cr.c | 197 + .../os/hal/ports/Cypress/PDL/driver/cr/cr.h | 147 + .../os/hal/ports/Cypress/PDL/driver/crc/crc.c | 231 + .../os/hal/ports/Cypress/PDL/driver/crc/crc.h | 176 + .../os/hal/ports/Cypress/PDL/driver/csv/csv.c | 296 + .../os/hal/ports/Cypress/PDL/driver/csv/csv.h | 183 + .../os/hal/ports/Cypress/PDL/driver/dac/dac.c | 218 + .../os/hal/ports/Cypress/PDL/driver/dac/dac.h | 197 + .../ports/Cypress/PDL/driver/description.h | 212 + .../os/hal/ports/Cypress/PDL/driver/dma/dma.c | 1144 + .../os/hal/ports/Cypress/PDL/driver/dma/dma.h | 490 + .../hal/ports/Cypress/PDL/driver/dstc/dstc.c | 2848 + .../hal/ports/Cypress/PDL/driver/dstc/dstc.h | 2516 + .../os/hal/ports/Cypress/PDL/driver/dt/dt.c | 986 + .../os/hal/ports/Cypress/PDL/driver/dt/dt.h | 287 + .../ports/Cypress/PDL/driver/exint/exint.c | 933 + .../ports/Cypress/PDL/driver/exint/exint.h | 390 + .../ports/Cypress/PDL/driver/extif/extif.c | 634 + .../ports/Cypress/PDL/driver/extif/extif.h | 494 + .../Cypress/PDL/driver/flash/dualflash.c | 378 + .../Cypress/PDL/driver/flash/dualflash.h | 132 + .../Cypress/PDL/driver/flash/mainflash.c | 850 + .../Cypress/PDL/driver/flash/mainflash.h | 248 + .../Cypress/PDL/driver/flash/workflash.c | 357 + .../Cypress/PDL/driver/flash/workflash.h | 123 + .../hal/ports/Cypress/PDL/driver/gpio/fgpio.h | 192 + .../hal/ports/Cypress/PDL/driver/gpio/gpio.h | 142 + .../Cypress/PDL/driver/gpio/gpio_s6e2c5xh.h | 7281 ++ .../Cypress/PDL/driver/gpio/gpio_s6e2c5xl.h | 11362 +++ .../hal/ports/Cypress/PDL/driver/hbif/hbif.c | 471 + .../hal/ports/Cypress/PDL/driver/hbif/hbif.h | 303 + .../ports/Cypress/PDL/driver/hsspi/hsspi.c | 1615 + .../ports/Cypress/PDL/driver/hsspi/hsspi.h | 805 + .../hal/ports/Cypress/PDL/driver/i2cs/i2cs.c | 760 + .../hal/ports/Cypress/PDL/driver/i2cs/i2cs.h | 338 + .../os/hal/ports/Cypress/PDL/driver/i2s/i2s.c | 1252 + .../os/hal/ports/Cypress/PDL/driver/i2s/i2s.h | 452 + .../os/hal/ports/Cypress/PDL/driver/icc/icc.c | 1398 + .../os/hal/ports/Cypress/PDL/driver/icc/icc.h | 433 + .../Cypress/PDL/driver/interrupts_fm0p.h | 356 + .../PDL/driver/interrupts_fm0p_type_1-a.c | 952 + .../PDL/driver/interrupts_fm0p_type_1-b.c | 2134 + .../PDL/driver/interrupts_fm0p_type_2-a.c | 2385 + .../PDL/driver/interrupts_fm0p_type_2-b.c | 2140 + .../PDL/driver/interrupts_fm0p_type_3.c | 1797 + .../ports/Cypress/PDL/driver/interrupts_fm3.h | 377 + .../PDL/driver/interrupts_fm3_type_a.c | 3962 + .../PDL/driver/interrupts_fm3_type_b.c | 1822 + .../PDL/driver/interrupts_fm3_type_c.c | 1655 + .../ports/Cypress/PDL/driver/interrupts_fm4.h | 454 + .../PDL/driver/interrupts_fm4_type_a.c | 4384 + .../PDL/driver/interrupts_fm4_type_b.c | 6389 ++ .../PDL/driver/interrupts_fm4_type_c.c | 3770 + .../os/hal/ports/Cypress/PDL/driver/lcd/lcd.c | 666 + .../os/hal/ports/Cypress/PDL/driver/lcd/lcd.h | 492 + .../os/hal/ports/Cypress/PDL/driver/lpm/lpm.c | 871 + .../os/hal/ports/Cypress/PDL/driver/lpm/lpm.h | 383 + .../os/hal/ports/Cypress/PDL/driver/lvd/lvd.c | 497 + .../os/hal/ports/Cypress/PDL/driver/lvd/lvd.h | 463 + .../os/hal/ports/Cypress/PDL/driver/mfs/mfs.c | 5097 ++ .../os/hal/ports/Cypress/PDL/driver/mfs/mfs.h | 1417 + .../ports/Cypress/PDL/driver/mft/mft_adcmp.c | 1061 + .../ports/Cypress/PDL/driver/mft/mft_adcmp.h | 375 + .../ports/Cypress/PDL/driver/mft/mft_frt.c | 1139 + .../ports/Cypress/PDL/driver/mft/mft_frt.h | 379 + .../ports/Cypress/PDL/driver/mft/mft_icu.c | 706 + .../ports/Cypress/PDL/driver/mft/mft_icu.h | 272 + .../ports/Cypress/PDL/driver/mft/mft_ocu.c | 1255 + .../ports/Cypress/PDL/driver/mft/mft_ocu.h | 478 + .../ports/Cypress/PDL/driver/mft/mft_wfg.c | 1099 + .../ports/Cypress/PDL/driver/mft/mft_wfg.h | 419 + .../hal/ports/Cypress/PDL/driver/pcrc/pcrc.c | 394 + .../hal/ports/Cypress/PDL/driver/pcrc/pcrc.h | 208 + .../OS/os/hal/ports/Cypress/PDL/driver/pdl.c | 81 + .../OS/os/hal/ports/Cypress/PDL/driver/pdl.h | 285 + .../hal/ports/Cypress/PDL/driver/pdl_header.h | 319 + .../os/hal/ports/Cypress/PDL/driver/ppg/ppg.c | 1055 + .../os/hal/ports/Cypress/PDL/driver/ppg/ppg.h | 503 + .../hal/ports/Cypress/PDL/driver/qprc/qprc.c | 1363 + .../hal/ports/Cypress/PDL/driver/qprc/qprc.h | 443 + .../os/hal/ports/Cypress/PDL/driver/rc/rc.c | 2223 + .../os/hal/ports/Cypress/PDL/driver/rc/rc.h | 625 + .../ports/Cypress/PDL/driver/reset/reset.c | 193 + .../ports/Cypress/PDL/driver/reset/reset.h | 149 + .../os/hal/ports/Cypress/PDL/driver/rtc/rtc.c | 2836 + .../os/hal/ports/Cypress/PDL/driver/rtc/rtc.h | 580 + .../hal/ports/Cypress/PDL/driver/sd/debug.h | 70 + .../os/hal/ports/Cypress/PDL/driver/sd/sd.c | 973 + .../os/hal/ports/Cypress/PDL/driver/sd/sd.h | 310 + .../hal/ports/Cypress/PDL/driver/sd/sd_cfg.h | 108 + .../hal/ports/Cypress/PDL/driver/sdif/sdif.c | 1587 + .../hal/ports/Cypress/PDL/driver/sdif/sdif.h | 560 + .../os/hal/ports/Cypress/PDL/driver/uid/uid.c | 129 + .../os/hal/ports/Cypress/PDL/driver/uid/uid.h | 139 + .../os/hal/ports/Cypress/PDL/driver/usb/usb.c | 2969 + .../os/hal/ports/Cypress/PDL/driver/usb/usb.h | 1863 + .../ports/Cypress/PDL/driver/usb/usbdevice.c | 999 + .../ports/Cypress/PDL/driver/usb/usbdevice.h | 408 + .../Cypress/PDL/driver/usb/usbethernetclock.c | 368 + .../Cypress/PDL/driver/usb/usbethernetclock.h | 1279 + .../PDL/driver/usb/usbethernetclocklegacy.h | 1712 + .../ports/Cypress/PDL/driver/usb/usbhost.c | 1698 + .../ports/Cypress/PDL/driver/usb/usbhost.h | 554 + .../ports/Cypress/PDL/driver/usb/usblegacy.h | 906 + .../hal/ports/Cypress/PDL/driver/vbat/vbat.c | 689 + .../hal/ports/Cypress/PDL/driver/vbat/vbat.h | 243 + .../os/hal/ports/Cypress/PDL/driver/wc/wc.c | 601 + .../os/hal/ports/Cypress/PDL/driver/wc/wc.h | 245 + .../hal/ports/Cypress/PDL/driver/wdg/hwwdg.c | 301 + .../hal/ports/Cypress/PDL/driver/wdg/hwwdg.h | 205 + .../hal/ports/Cypress/PDL/driver/wdg/swwdg.c | 332 + .../hal/ports/Cypress/PDL/driver/wdg/swwdg.h | 224 + .../os/hal/ports/Cypress/PDL/driver/wdg/wdg.h | 33 + .../ports/Cypress/PDL/highlevel/mfs/mfs_hl.c | 4687 + .../ports/Cypress/PDL/highlevel/mfs/mfs_hl.h | 563 + .../ports/Cypress/PDL/highlevel/sd/sdcard.c | 424 + .../ports/Cypress/PDL/highlevel/sd/sdcard.h | 272 + .../ports/Cypress/PDL/highlevel/sd/sdcmd.c | 260 + .../ports/Cypress/PDL/highlevel/sd/sdcmd.h | 142 + .../PDL/midware/usb/device/UsbDeviceCdcCom.c | 1176 + .../PDL/midware/usb/device/UsbDeviceCdcCom.h | 416 + .../midware/usb/device/UsbDeviceCmsisDap.c | 393 + .../midware/usb/device/UsbDeviceCmsisDap.h | 85 + .../PDL/midware/usb/device/UsbDeviceHidCom.c | 268 + .../PDL/midware/usb/device/UsbDeviceHidCom.h | 126 + .../midware/usb/device/UsbDeviceHidJoystick.c | 389 + .../midware/usb/device/UsbDeviceHidJoystick.h | 258 + .../midware/usb/device/UsbDeviceHidKeyboard.c | 537 + .../midware/usb/device/UsbDeviceHidKeyboard.h | 168 + .../midware/usb/device/UsbDeviceHidMouse.c | 342 + .../midware/usb/device/UsbDeviceHidMouse.h | 141 + .../PDL/midware/usb/device/UsbDeviceLibUsb.c | 244 + .../PDL/midware/usb/device/UsbDeviceLibUsb.h | 126 + .../midware/usb/device/UsbDeviceMassStorage.c | 941 + .../midware/usb/device/UsbDeviceMassStorage.h | 859 + .../PDL/midware/usb/device/UsbDevicePrinter.c | 300 + .../PDL/midware/usb/device/UsbDevicePrinter.h | 138 + .../ports/Cypress/S6E2CxAH/cypress_stm32.h | 104 + .../os/hal/ports/Cypress/S6E2CxAH/hal_lld.c | 67 + .../os/hal/ports/Cypress/S6E2CxAH/hal_lld.h | 104 + .../os/hal/ports/Cypress/S6E2CxAH/platform.mk | 45 + .../ports/Cypress/S6E2CxAH/system_s6e2c5.c | 259 + firmware/config/boards/hellen/cypress/board.c | 47 + firmware/config/boards/hellen/cypress/board.h | 47 + .../config/boards/hellen/cypress/board.mk | 27 + .../hellen/cypress/board_configuration.cpp | 161 + .../config/boards/hellen/cypress/chconf.h | 830 + .../config/boards/hellen/cypress/config.mk | 17 + .../hellen/cypress/config/!gen_config.bat | 36 + .../cypress/config/!gen_enum_to_string.bat | 12 + .../controllers/algo/auto_generated_enums.cpp | 1296 + .../controllers/algo/auto_generated_enums.h | 53 + ...ngine_configuration_generated_structures.h | 3136 + .../controllers/algo/rusefi_generated.h | 2221 + .../models/src/com/rusefi/config/Fields.java | 1970 + .../cypress/config/java_console/rusefi.xml | 240 + .../cypress/config/rusefi_config_cypress.txt | 16 + .../config/tunerstudio/cypress_prefix.txt | 0 .../boards/hellen/cypress/efifeatures.h | 436 + .../config/boards/hellen/cypress/halconf.h | 416 + .../boards/hellen/cypress/halconf_community.h | 0 .../config/boards/hellen/cypress/mapping.yaml | 7 + .../config/boards/hellen/cypress/mcuconf.h | 86 + .../config/boards/hellen/cypress/pdl_user.h | 1436 + .../config/boards/hellen/cypress/readme.md | 7 + .../boards/hellen/cypress/rusefi_hw_enums.h | 304 + 207 files changed, 309987 insertions(+) create mode 100644 firmware/config/boards/hellen/cypress/!compile-cypress.bat create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/base_types.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/chibios_pdl_vectors.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/mcu.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xh.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xl.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/system_s6e2c5.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/ld/cypress_S6E2CxAH.ld create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/devices/S6E2CxAH/cmparams.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/driver.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/driver.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/driver.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/gpio_s6e2_common.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/driver.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/driver.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/base_types.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/description.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.c create mode 100644 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create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/debug.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd_cfg.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sdif/sdif.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sdif/sdif.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclocklegacy.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usblegacy.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/wdg.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcard.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcard.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcmd.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcmd.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCdcCom.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCdcCom.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/cypress_stm32.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/hal_lld.c create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/hal_lld.h create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/platform.mk create mode 100644 firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/system_s6e2c5.c create mode 100644 firmware/config/boards/hellen/cypress/board.c create mode 100644 firmware/config/boards/hellen/cypress/board.h create mode 100644 firmware/config/boards/hellen/cypress/board.mk create mode 100644 firmware/config/boards/hellen/cypress/board_configuration.cpp create mode 100644 firmware/config/boards/hellen/cypress/chconf.h create mode 100644 firmware/config/boards/hellen/cypress/config.mk create mode 100644 firmware/config/boards/hellen/cypress/config/!gen_config.bat create mode 100644 firmware/config/boards/hellen/cypress/config/!gen_enum_to_string.bat create mode 100644 firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.cpp create mode 100644 firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.h create mode 100644 firmware/config/boards/hellen/cypress/config/controllers/algo/engine_configuration_generated_structures.h create mode 100644 firmware/config/boards/hellen/cypress/config/controllers/algo/rusefi_generated.h create mode 100644 firmware/config/boards/hellen/cypress/config/java_console/models/src/com/rusefi/config/Fields.java create mode 100644 firmware/config/boards/hellen/cypress/config/java_console/rusefi.xml create mode 100644 firmware/config/boards/hellen/cypress/config/rusefi_config_cypress.txt create mode 100644 firmware/config/boards/hellen/cypress/config/tunerstudio/cypress_prefix.txt create mode 100644 firmware/config/boards/hellen/cypress/efifeatures.h create mode 100644 firmware/config/boards/hellen/cypress/halconf.h create mode 100644 firmware/config/boards/hellen/cypress/halconf_community.h create mode 100644 firmware/config/boards/hellen/cypress/mapping.yaml create mode 100644 firmware/config/boards/hellen/cypress/mcuconf.h create mode 100644 firmware/config/boards/hellen/cypress/pdl_user.h create mode 100644 firmware/config/boards/hellen/cypress/readme.md create mode 100644 firmware/config/boards/hellen/cypress/rusefi_hw_enums.h diff --git a/firmware/config/boards/hellen/cypress/!compile-cypress.bat b/firmware/config/boards/hellen/cypress/!compile-cypress.bat new file mode 100644 index 0000000000..aefb0e8df0 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/!compile-cypress.bat @@ -0,0 +1,29 @@ +@echo off +set PATH=G:\VStudio\arm-elf-gcc\bin;G:\VStudio\msys2\usr\bin;C:\Program Files\Java\jre\bin;G:\VStudio\Git\bin + +echo "Compiling for Cypress FM4 S6E2CxAH" +rem TODO: somehow this -DDUMMY is helping us to not mess up the parameters, why?! +rem https://github.com/rusefi/rusefi/issues/684 +set EXTRA_PARAMS=-DDUMMY -D__USE_CMSIS^ + -DEFI_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_CHECKS=FALSE -DCH_DBG_ENABLE_ASSERTS=FALSE -DCH_DBG_ENABLE_STACK_CHECK=FALSE -DCH_DBG_FILL_THREADS=FALSE -DCH_DBG_THREADS_PROFILING=FALSE^ + -DDEFAULT_ENGINE_TYPE=MINIMAL_PINS + +set BUILDDIR=build_cypress +set PROJECT_BOARD=hellen/cypress +set PROJECT_CPU=cypress +set USE_FATFS=no +set USE_BOOTLOADER=no +set DEBUG_LEVEL_OPT="-O2" + +rem make -r clean +rem make -r +rem 2> err.log +rem rm -f build/rusefi.dfu +rem dir build +rem ..\misc\hex2dfu\HEX2DFU.exe build/rusefi.hex -out build/rusefi.dfu + +cd ../../../.. + +rm -f build_cypress/rusefi.hex + +call config/boards/common_make.bat diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/base_types.h b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/base_types.h new file mode 100644 index 0000000000..3b1e2800ac --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/base_types.h @@ -0,0 +1,160 @@ +/******************************************************************************* +* Copyright (C) 2014 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ + +/*****************************************************************************/ +/** \file base_types.h + ** + ** Additional base type definitions to stddef.h and stdint.h + ** + ** History: + ** - 2013-03-21 1.0 MWi First version. + ** + *****************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include "stdint.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0) +#endif + +/** Returns the minimum value out of two values */ +#define MIN( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAX( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define DIM( X ) (sizeof(X) / sizeof(X[0])) + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCCI character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0, ///< No error + Error = 1, ///< Non-specific error code + ErrorAddressAlignment = 2, ///< Address alignment does not match + ErrorAccessRights = 3, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4, ///< Provided parameter is not valid + ErrorOperationInProgress = 5, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6, ///< Operation not allowed in current mode + ErrorUninitialized = 7, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10, ///< A requested final state is not reached + OperationInProgress = 11 ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + PDLLow = 0, ///< Low level '0' + PDLHigh = 1 ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + PdlClr = 0, ///< Flag clr '0' + PdlSet = 1 ///< Flag set '1' +} en_stat_flag_t, en_int_flag_t; + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/chibios_pdl_vectors.h b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/chibios_pdl_vectors.h new file mode 100644 index 0000000000..9343187409 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/chibios_pdl_vectors.h @@ -0,0 +1,140 @@ +/** + * @file chibios_pdl_vectors.h + * @brief Core IRQ vector mappings + * @author andreika + */ + +#ifndef __CHIBIOS_PDL_VECTORS_H__ +#define __CHIBIOS_PDL_VECTORS_H__ + +// generated from startup_s6e2c5.S + ChibiOS/os/common/startup/ARMCMx/compilers/GCC/vectors.S +#define CSV_IRQHandler Vector40 +#define SWDT_IRQHandler Vector44 +#define LVD_IRQHandler Vector48 +#define IRQ003SEL_IRQHandler Vector4C +#define IRQ004SEL_IRQHandler Vector50 +#define IRQ005SEL_IRQHandler Vector54 +#define IRQ006SEL_IRQHandler Vector58 +#define IRQ007SEL_IRQHandler Vector5C +#define IRQ008SEL_IRQHandler Vector60 +#define IRQ009SEL_IRQHandler Vector64 +#define IRQ010SEL_IRQHandler Vector68 +#define EXINT0_IRQHandler Vector6C +#define EXINT1_IRQHandler Vector70 +#define EXINT2_IRQHandler Vector74 +#define EXINT3_IRQHandler Vector78 +#define EXINT4_IRQHandler Vector7C +#define EXINT5_IRQHandler Vector80 +#define EXINT6_IRQHandler Vector84 +#define EXINT7_IRQHandler Vector88 +#define QPRC0_IRQHandler Vector8C +#define QPRC1_IRQHandler Vector90 +#define MFT0_WFG_DTIF_IRQHandler Vector94 +#define MFT1_WFG_DTIF_IRQHandler Vector98 +#define MFT2_WFG_DTIF_IRQHandler Vector9C +#define MFT0_FRT_PEAK_IRQHandler VectorA0 +#define MFT0_FRT_ZERO_IRQHandler VectorA4 +#define MFT0_ICU_IRQHandler VectorA8 +#define MFT0_OCU_IRQHandler VectorAC +#define MFT1_FRT_PEAK_IRQHandler VectorB0 +#define MFT1_FRT_ZERO_IRQHandler VectorB4 +#define MFT1_ICU_IRQHandler VectorB8 +#define MFT1_OCU_IRQHandler VectorBC +#define MFT2_FRT_PEAK_IRQHandler VectorC0 +#define MFT2_FRT_ZERO_IRQHandler VectorC4 +#define MFT2_ICU_IRQHandler VectorC8 +#define MFT2_OCU_IRQHandler VectorCC +#define PPG00_02_04_IRQHandler VectorD0 +#define PPG08_10_12_IRQHandler VectorD4 +#define PPG16_18_20_IRQHandler VectorD8 +#define BT0_IRQHandler VectorDC +#define BT1_IRQHandler VectorE0 +#define BT2_IRQHandler VectorE4 +#define BT3_IRQHandler VectorE8 +#define BT4_IRQHandler VectorEC +#define BT5_IRQHandler VectorF0 +#define BT6_IRQHandler VectorF4 +#define BT7_IRQHandler VectorF8 +#define DT_IRQHandler VectorFC +#define WC_IRQHandler Vector100 +#define EXTBUS_ERR_IRQHandler Vector104 +#define RTC_IRQHandler Vector108 +#define EXINT8_IRQHandler Vector10C +#define EXINT9_IRQHandler Vector110 +#define EXINT10_IRQHandler Vector114 +#define EXINT11_IRQHandler Vector118 +#define EXINT12_IRQHandler Vector11C +#define EXINT13_IRQHandler Vector120 +#define EXINT14_IRQHandler Vector124 +#define EXINT15_IRQHandler Vector128 +#define TIM_IRQHandler Vector12C +#define MFS0_RX_IRQHandler Vector130 +#define MFS0_TX_IRQHandler Vector134 +#define MFS1_RX_IRQHandler Vector138 +#define MFS1_TX_IRQHandler Vector13C +#define MFS2_RX_IRQHandler Vector140 +#define MFS2_TX_IRQHandler Vector144 +#define MFS3_RX_IRQHandler Vector148 +#define MFS3_TX_IRQHandler Vector14C +#define MFS4_RX_IRQHandler Vector150 +#define MFS4_TX_IRQHandler Vector154 +#define MFS5_RX_IRQHandler Vector158 +#define MFS5_TX_IRQHandler Vector15C +#define MFS6_RX_IRQHandler Vector160 +#define MFS6_TX_IRQHandler Vector164 +#define MFS7_RX_IRQHandler Vector168 +#define MFS7_TX_IRQHandler Vector16C +#define ADC0_IRQHandler Vector170 +#define ADC1_IRQHandler Vector174 +#define USB0_F_IRQHandler Vector178 +#define USB0_H_F_IRQHandler Vector17C +#define CAN0_IRQHandler Vector180 +#define CAN1_CANFD0_IRQHandler Vector184 +//#define Default_Handler Vector188 +#define DMAC0_IRQHandler Vector18C +#define DMAC1_IRQHandler Vector190 +#define DMAC2_IRQHandler Vector194 +#define DMAC3_IRQHandler Vector198 +#define DMAC4_IRQHandler Vector19C +#define DMAC5_IRQHandler Vector1A0 +#define DMAC6_IRQHandler Vector1A4 +#define DMAC7_IRQHandler Vector1A8 +#define DSTC_IRQHandler Vector1AC +#define EXINT16_19_IRQHandler Vector1B0 +#define EXINT20_23_IRQHandler Vector1B4 +#define EXINT24_27_IRQHandler Vector1B8 +#define EXINT28_31_IRQHandler Vector1BC +#define QPRC2_IRQHandler Vector1C0 +#define QPRC3_IRQHandler Vector1C4 +#define BT8_IRQHandler Vector1C8 +#define BT9_IRQHandler Vector1CC +#define BT10_IRQHandler Vector1D0 +#define BT11_IRQHandler Vector1D4 +#define BT12_15_IRQHandler Vector1D8 +#define MFS8_RX_IRQHandler Vector1DC +#define MFS8_TX_IRQHandler Vector1E0 +#define MFS9_RX_IRQHandler Vector1E4 +#define MFS9_TX_IRQHandler Vector1E8 +#define MFS10_RX_IRQHandler Vector1EC +#define MFS10_TX_IRQHandler Vector1F0 +#define MFS11_RX_IRQHandler Vector1F4 +#define MFS11_TX_IRQHandler Vector1F8 +#define ADC2_IRQHandler Vector1FC +#define DSTC_HW_IRQHandler Vector200 +#define USB1_F_IRQHandler Vector204 +#define USB1_H_F_IRQHandler Vector208 +#define HSSPI_IRQHandler Vector20C +//#define Default_Handler Vector210 +#define PCRC_I2S0_1_IRQHandler Vector214 +#define SD_IRQHandler Vector218 +#define FLASHIF_IRQHandler Vector21C +#define MFS12_RX_IRQHandler Vector220 +#define MFS12_TX_IRQHandler Vector224 +#define MFS13_RX_IRQHandler Vector228 +#define MFS13_TX_IRQHandler Vector22C +#define MFS14_RX_IRQHandler Vector230 +#define MFS14_TX_IRQHandler Vector234 +#define MFS15_RX_IRQHandler Vector238 +#define MFS15_TX_IRQHandler Vector23C + +#endif // of __CHIBIOS_PDL_VECTORS_H__ diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/mcu.h b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/mcu.h new file mode 100644 index 0000000000..e7e8eb9374 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/mcu.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* \file mcu.h +* +* \version 1.0 +* +* \date 7/29/2016 +* +* \brief Contains references to all device-specific header files. +* +******************************************************************************** +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MCU_H__ +#define __MCU_H__ + +/******************************************************************************* +* Device-specific include file +*******************************************************************************/ +#ifndef _S6E2C5XH_H_ + #include "s6e2c5xh.h" +#endif + +//#ifndef _S6E2C5XL_H_ +// #include "s6e2c5xl.h" +//#endif + +/******************************************************************************* +* System device-specific configuration include file +*******************************************************************************/ +#ifndef _SYSTEM_S6E2C5_H_ + #include "system_s6e2c5.h" +#endif + +/******************************************************************************* +* Device-specific GPIO macro include file +*******************************************************************************/ +#ifndef __GPIO_S6E2C5XH_H__ + #include "gpio_s6e2c5xh.h" +#endif + +//#ifndef __GPIO_S6E2C5XL_H__ +// #include "gpio_s6e2c5xl.h" +//#endif + +#endif /* __MCU_H__ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xh.h b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xh.h new file mode 100644 index 0000000000..1e281276dc --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xh.h @@ -0,0 +1,70654 @@ +/******************************************************************************* +* \file s6e2c5xh.h +* +* \version 1.0 +* +* \date 7/29/2016 +* +* \brief CMSIS Core Peripheral Access Layer Header File for s6e2c5xh Device +* +******************************************************************************** +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef _S6E2C5XH_H_ +#define _S6E2C5XH_H_ +#define __S6E2C5XH_H__ +#define __S6E2C5_H__ + +#if defined __cplusplus +extern "C" { +#endif + +#define FM_GENERAL_MCUHEADER_VERSION 0201 + + +#ifndef FM_DEVICE_PACKAGE_S6E_H +#define FM_DEVICE_PACKAGE_S6E_H +#endif + +/******************************************************************************* +* Configuration of the Cortex-M4 Processor and Core Peripherals +*******************************************************************************/ +#define FM4_DEVICE_TYPE 3 +#define FM_DEVICE_TYPE 4003u +#define FM_CORE_TYPE_FM4 1 +#define __CM4_REV 0x0001 +#define __MPU_PRESENT 1 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 +#define __FPU_PRESENT 1 +#define __FPU_DP 0 +#define __ICACHE_PRESENT 0 +#define __DCACHE_PRESENT 0 +#define __DTCM_PRESENT 0 + +/******************************************************************************* +* Peripheral Types +*******************************************************************************/ +#define FM4_ADC_TYPE_A 1 +#define FM4_BT_TYPE_A 1 +#define FM4_BTIOSEL03_TYPE_A 1 +#define FM4_BTIOSEL47_TYPE_A 1 +#define FM4_BTIOSEL8B_TYPE_A 1 +#define FM4_BTIOSELCF_TYPE_A 1 +#define FM4_CAN_TYPE_A 1 +#define FM4_CANFD_TYPE_A 1 +#define FM4_CANPRES_TYPE_A 1 +#define FM4_CLK_GATING_TYPE_B 1 +#define FM4_CRC_TYPE_A 1 +#define FM4_CRG_TYPE_B 1 +#define FM4_CRTRIM_TYPE_A 1 +#define FM4_DAC_TYPE_A 1 +#define FM4_DMAC_TYPE_A 1 +#define FM4_DS_TYPE_A 1 +#define FM4_DSTC_TYPE_A 1 +#define FM4_DT_TYPE_A 1 +#define FM4_DUALFLASH_IF_TYPE_A 1 +#define FM4_ECC_CAPTURE_TYPE_A 1 +#define FM4_EXBUS_TYPE_B 1 +#define FM4_EXTI_TYPE_A 1 +#define FM4_FLASH_IF_TYPE_B 1 +#define FM4_GPIO_TYPE_B 1 +#define FM4_HSSPI_TYPE_A 1 +#define FM4_HWWDT_TYPE_A 1 +#define FM4_I2S_TYPE_A 1 +#define FM4_I2SPRE_TYPE_A 1 +#define FM4_INTREQ_TYPE_B 1 +#define FM4_LSCRP_TYPE_A 1 +#define FM4_LVD_TYPE_A 1 +#define FM4_MFS_TYPE_B 1 +#define FM4_MFT_TYPE_B 1 +#define FM4_MFT_PPG_TYPE_A 1 +#define FM4_PCRC_TYPE_A 1 +#define FM4_QPRC_TYPE_B 1 +#define FM4_QPRC_NF_TYPE_A 1 +#define FM4_RTC_TYPE_A 1 +#define FM4_SBSSR_TYPE_A 1 +#define FM4_SDIF_TYPE_A 1 +#define FM4_SWWDT_TYPE_A 1 +#define FM4_UNIQUE_ID_TYPE_A 1 +#define FM4_USB_TYPE_A 1 +#define FM4_USBCLK_TYPE_A 1 +#define FM4_WC_TYPE_A 1 + +/******************************************************************************* +* Available Peripherals +*******************************************************************************/ +#define FM4_ADC_AVAILABLE 1 +#define FM_ADC_AVAILABLE 1 +#define FM4_BT_AVAILABLE 1 +#define FM_BT_AVAILABLE 1 +#define FM4_BT_PPG_AVAILABLE 1 +#define FM_BT_PPG_AVAILABLE 1 +#define FM4_BT_PWC_AVAILABLE 1 +#define FM_BT_PWC_AVAILABLE 1 +#define FM4_BT_PWM_AVAILABLE 1 +#define FM_BT_PWM_AVAILABLE 1 +#define FM4_BT_RT_AVAILABLE 1 +#define FM_BT_RT_AVAILABLE 1 +#define FM4_BTIOSEL03_AVAILABLE 1 +#define FM_BTIOSEL03_AVAILABLE 1 +#define FM4_BTIOSEL47_AVAILABLE 1 +#define FM_BTIOSEL47_AVAILABLE 1 +#define FM4_BTIOSEL8B_AVAILABLE 1 +#define FM_BTIOSEL8B_AVAILABLE 1 +#define FM4_BTIOSELCF_AVAILABLE 1 +#define FM_BTIOSELCF_AVAILABLE 1 +#define FM4_CAN_AVAILABLE 1 +#define FM_CAN_AVAILABLE 1 +#define FM4_CANFD_AVAILABLE 1 +#define FM_CANFD_AVAILABLE 1 +#define FM4_CANPRES_AVAILABLE 1 +#define FM_CANPRES_AVAILABLE 1 +#define FM4_CLK_GATING_AVAILABLE 1 +#define FM_CLK_GATING_AVAILABLE 1 +#define FM4_CRC_AVAILABLE 1 +#define FM_CRC_AVAILABLE 1 +#define FM4_CRG_AVAILABLE 1 +#define FM_CRG_AVAILABLE 1 +#define FM4_CRTRIM_AVAILABLE 1 +#define FM_CRTRIM_AVAILABLE 1 +#define FM4_DAC_AVAILABLE 1 +#define FM_DAC_AVAILABLE 1 +#define FM4_DMAC_AVAILABLE 1 +#define FM_DMAC_AVAILABLE 1 +#define FM4_DS_AVAILABLE 1 +#define FM_DS_AVAILABLE 1 +#define FM4_DSTC_AVAILABLE 1 +#define FM_DSTC_AVAILABLE 1 +#define FM4_DT_AVAILABLE 1 +#define FM_DT_AVAILABLE 1 +#define FM4_DUALFLASH_IF_AVAILABLE 1 +#define FM_DUALFLASH_IF_AVAILABLE 1 +#define FM4_ECC_CAPTURE_AVAILABLE 1 +#define FM_ECC_CAPTURE_AVAILABLE 1 +#define FM4_EXBUS_AVAILABLE 1 +#define FM_EXBUS_AVAILABLE 1 +#define FM4_EXTI_AVAILABLE 1 +#define FM_EXTI_AVAILABLE 1 +#define FM4_FLASH_IF_AVAILABLE 1 +#define FM_FLASH_IF_AVAILABLE 1 +#define FM4_GPIO_AVAILABLE 1 +#define FM_GPIO_AVAILABLE 1 +#define FM4_HSSPI_AVAILABLE 1 +#define FM_HSSPI_AVAILABLE 1 +#define FM4_HWWDT_AVAILABLE 1 +#define FM_HWWDT_AVAILABLE 1 +#define FM4_I2S_AVAILABLE 1 +#define FM_I2S_AVAILABLE 1 +#define FM4_I2SPRE_AVAILABLE 1 +#define FM_I2SPRE_AVAILABLE 1 +#define FM4_INTREQ_AVAILABLE 1 +#define FM_INTREQ_AVAILABLE 1 +#define FM4_LSCRP_AVAILABLE 1 +#define FM_LSCRP_AVAILABLE 1 +#define FM4_LVD_AVAILABLE 1 +#define FM_LVD_AVAILABLE 1 +#define FM4_MFS_AVAILABLE 1 +#define FM_MFS_AVAILABLE 1 +#define FM4_MFS_CSIO_AVAILABLE 1 +#define FM_MFS_CSIO_AVAILABLE 1 +#define FM4_MFS_I2C_AVAILABLE 1 +#define FM_MFS_I2C_AVAILABLE 1 +#define FM4_MFS_LIN_AVAILABLE 1 +#define FM_MFS_LIN_AVAILABLE 1 +#define FM4_MFS_UART_AVAILABLE 1 +#define FM_MFS_UART_AVAILABLE 1 +#define FM4_MFT_AVAILABLE 1 +#define FM_MFT_AVAILABLE 1 +#define FM4_MFT_ADCMP_AVAILABLE 1 +#define FM_MFT_ADCMP_AVAILABLE 1 +#define FM4_MFT_FRT_AVAILABLE 1 +#define FM_MFT_FRT_AVAILABLE 1 +#define FM4_MFT_ICU_AVAILABLE 1 +#define FM_MFT_ICU_AVAILABLE 1 +#define FM4_MFT_OCU_AVAILABLE 1 +#define FM_MFT_OCU_AVAILABLE 1 +#define FM4_MFT_PPG_AVAILABLE 1 +#define FM_MFT_PPG_AVAILABLE 1 +#define FM4_MFT_WFG_AVAILABLE 1 +#define FM_MFT_WFG_AVAILABLE 1 +#define FM4_PCRC_AVAILABLE 1 +#define FM_PCRC_AVAILABLE 1 +#define FM4_QPRC_AVAILABLE 1 +#define FM_QPRC_AVAILABLE 1 +#define FM4_QPRC_NF_AVAILABLE 1 +#define FM_QPRC_NF_AVAILABLE 1 +#define FM4_RTC_AVAILABLE 1 +#define FM_RTC_AVAILABLE 1 +#define FM4_SBSSR_AVAILABLE 1 +#define FM_SBSSR_AVAILABLE 1 +#define FM4_SDIF_AVAILABLE 1 +#define FM_SDIF_AVAILABLE 1 +#define FM4_SWWDT_AVAILABLE 1 +#define FM_SWWDT_AVAILABLE 1 +#define FM4_UNIQUE_ID_AVAILABLE 1 +#define FM_UNIQUE_ID_AVAILABLE 1 +#define FM4_USB_AVAILABLE 1 +#define FM_USB_AVAILABLE 1 +#define FM4_USBCLK_AVAILABLE 1 +#define FM_USBCLK_AVAILABLE 1 +#define FM4_WC_AVAILABLE 1 +#define FM_WC_AVAILABLE 1 + +/******************************************************************************* +* \brief Interrupt number definition for all type MCUs +*******************************************************************************/ +#define FM_INTERRUPT_TYPE 0x400Bu + +#define IRQ_NMI_AVAILABLE 1 +#define IRQ_HARDFAULT_AVAILABLE 1 +#define IRQ_MEMMANAGE_AVAILABLE 1 +#define IRQ_BUSFAULT_AVAILABLE 1 +#define IRQ_USAGEFAULT_AVAILABLE 1 +#define IRQ_SVC_AVAILABLE 1 +#define IRQ_DEBUGMONITOR_AVAILABLE 1 +#define IRQ_PENDSV_AVAILABLE 1 +#define IRQ_SYSTICK_AVAILABLE 1 + +#define IRQ_CSV_AVAILABLE 1 +#define IRQ_SWDT_AVAILABLE 1 +#define IRQ_LVD_AVAILABLE 1 +#define IRQ_IRQ003SEL_AVAILABLE 1 +#define IRQ_IRQ004SEL_AVAILABLE 1 +#define IRQ_IRQ005SEL_AVAILABLE 1 +#define IRQ_IRQ006SEL_AVAILABLE 1 +#define IRQ_IRQ007SEL_AVAILABLE 1 +#define IRQ_IRQ008SEL_AVAILABLE 1 +#define IRQ_IRQ009SEL_AVAILABLE 1 +#define IRQ_IRQ010SEL_AVAILABLE 1 +#define IRQ_EXINT0_AVAILABLE 1 +#define IRQ_EXINT1_AVAILABLE 1 +#define IRQ_EXINT2_AVAILABLE 1 +#define IRQ_EXINT3_AVAILABLE 1 +#define IRQ_EXINT4_AVAILABLE 1 +#define IRQ_EXINT5_AVAILABLE 1 +#define IRQ_EXINT6_AVAILABLE 1 +#define IRQ_EXINT7_AVAILABLE 1 +#define IRQ_QPRC0_AVAILABLE 1 +#define IRQ_QPRC1_AVAILABLE 1 +#define IRQ_MFT0_WFG_DTIF_AVAILABLE 1 +#define IRQ_MFT1_WFG_DTIF_AVAILABLE 1 +#define IRQ_MFT2_WFG_DTIF_AVAILABLE 1 +#define IRQ_MFT0_FRT_PEAK_AVAILABLE 1 +#define IRQ_MFT0_FRT_ZERO_AVAILABLE 1 +#define IRQ_MFT0_ICU_AVAILABLE 1 +#define IRQ_MFT0_OCU_AVAILABLE 1 +#define IRQ_MFT1_FRT_PEAK_AVAILABLE 1 +#define IRQ_MFT1_FRT_ZERO_AVAILABLE 1 +#define IRQ_MFT1_ICU_AVAILABLE 1 +#define IRQ_MFT1_OCU_AVAILABLE 1 +#define IRQ_MFT2_FRT_PEAK_AVAILABLE 1 +#define IRQ_MFT2_FRT_ZERO_AVAILABLE 1 +#define IRQ_MFT2_ICU_AVAILABLE 1 +#define IRQ_MFT2_OCU_AVAILABLE 1 +#define IRQ_PPG00_02_04_AVAILABLE 1 +#define IRQ_PPG08_10_12_AVAILABLE 1 +#define IRQ_PPG16_18_20_AVAILABLE 1 +#define IRQ_BT0_AVAILABLE 1 +#define IRQ_BT1_AVAILABLE 1 +#define IRQ_BT2_AVAILABLE 1 +#define IRQ_BT3_AVAILABLE 1 +#define IRQ_BT4_AVAILABLE 1 +#define IRQ_BT5_AVAILABLE 1 +#define IRQ_BT6_AVAILABLE 1 +#define IRQ_BT7_AVAILABLE 1 +#define IRQ_DT_AVAILABLE 1 +#define IRQ_WC_AVAILABLE 1 +#define IRQ_EXTBUS_ERR_AVAILABLE 1 +#define IRQ_RTC_AVAILABLE 1 +#define IRQ_EXINT8_AVAILABLE 1 +#define IRQ_EXINT9_AVAILABLE 1 +#define IRQ_EXINT10_AVAILABLE 1 +#define IRQ_EXINT11_AVAILABLE 1 +#define IRQ_EXINT12_AVAILABLE 1 +#define IRQ_EXINT13_AVAILABLE 1 +#define IRQ_EXINT14_AVAILABLE 1 +#define IRQ_EXINT15_AVAILABLE 1 +#define IRQ_TIM_AVAILABLE 1 +#define IRQ_MFS0_RX_AVAILABLE 1 +#define IRQ_MFS0_TX_AVAILABLE 1 +#define IRQ_MFS1_RX_AVAILABLE 1 +#define IRQ_MFS1_TX_AVAILABLE 1 +#define IRQ_MFS2_RX_AVAILABLE 1 +#define IRQ_MFS2_TX_AVAILABLE 1 +#define IRQ_MFS3_RX_AVAILABLE 1 +#define IRQ_MFS3_TX_AVAILABLE 1 +#define IRQ_MFS4_RX_AVAILABLE 1 +#define IRQ_MFS4_TX_AVAILABLE 1 +#define IRQ_MFS5_RX_AVAILABLE 1 +#define IRQ_MFS5_TX_AVAILABLE 1 +#define IRQ_MFS6_RX_AVAILABLE 1 +#define IRQ_MFS6_TX_AVAILABLE 1 +#define IRQ_MFS7_RX_AVAILABLE 1 +#define IRQ_MFS7_TX_AVAILABLE 1 +#define IRQ_ADC0_AVAILABLE 1 +#define IRQ_ADC1_AVAILABLE 1 +#define IRQ_USB0_F_AVAILABLE 1 +#define IRQ_USB0_H_F_AVAILABLE 1 +#define IRQ_CAN0_AVAILABLE 1 +#define IRQ_CAN1_CANFD0_AVAILABLE 1 +#define IRQ_DMAC0_AVAILABLE 1 +#define IRQ_DMAC1_AVAILABLE 1 +#define IRQ_DMAC2_AVAILABLE 1 +#define IRQ_DMAC3_AVAILABLE 1 +#define IRQ_DMAC4_AVAILABLE 1 +#define IRQ_DMAC5_AVAILABLE 1 +#define IRQ_DMAC6_AVAILABLE 1 +#define IRQ_DMAC7_AVAILABLE 1 +#define IRQ_DSTC_AVAILABLE 1 +#define IRQ_EXINT16_19_AVAILABLE 1 +#define IRQ_EXINT20_23_AVAILABLE 1 +#define IRQ_EXINT24_27_AVAILABLE 1 +#define IRQ_EXINT28_31_AVAILABLE 1 +#define IRQ_QPRC2_AVAILABLE 1 +#define IRQ_QPRC3_AVAILABLE 1 +#define IRQ_BT8_AVAILABLE 1 +#define IRQ_BT9_AVAILABLE 1 +#define IRQ_BT10_AVAILABLE 1 +#define IRQ_BT11_AVAILABLE 1 +#define IRQ_BT12_15_AVAILABLE 1 +#define IRQ_MFS8_RX_AVAILABLE 1 +#define IRQ_MFS8_TX_AVAILABLE 1 +#define IRQ_MFS9_RX_AVAILABLE 1 +#define IRQ_MFS9_TX_AVAILABLE 1 +#define IRQ_MFS10_RX_AVAILABLE 1 +#define IRQ_MFS10_TX_AVAILABLE 1 +#define IRQ_MFS11_RX_AVAILABLE 1 +#define IRQ_MFS11_TX_AVAILABLE 1 +#define IRQ_ADC2_AVAILABLE 1 +#define IRQ_DSTC_HW_AVAILABLE 1 +#define IRQ_USB1_F_AVAILABLE 1 +#define IRQ_USB1_H_F_AVAILABLE 1 +#define IRQ_HSSPI_AVAILABLE 1 +#define IRQ_PCRC_I2S0_1_AVAILABLE 1 +#define IRQ_SD_AVAILABLE 1 +#define IRQ_FLASHIF_AVAILABLE 1 +#define IRQ_MFS12_RX_AVAILABLE 1 +#define IRQ_MFS12_TX_AVAILABLE 1 +#define IRQ_MFS13_RX_AVAILABLE 1 +#define IRQ_MFS13_TX_AVAILABLE 1 +#define IRQ_MFS14_RX_AVAILABLE 1 +#define IRQ_MFS14_TX_AVAILABLE 1 +#define IRQ_MFS15_RX_AVAILABLE 1 +#define IRQ_MFS15_TX_AVAILABLE 1 + + +typedef enum IRQn +{ + NMI_IRQn = -14, /* Non Maskable Interrupt NMI */ + HardFault_IRQn = -13, /* HardFault HardFault */ + MemManage_IRQn = -12, /* Memory Management MemManage */ + BusFault_IRQn = -11, /* Bus Fault BusFault */ + UsageFault_IRQn = -10, /* Usage Fault UsageFault */ + SVC_IRQn = -5, /* SV Call SVC */ + DebugMonitor_IRQn = -4, /* Debug Monitor DebugMonitor */ + PendSV_IRQn = -2, /* Pend SV PendSV */ + SysTick_IRQn = -1, /* System Tick SysTick */ + + CSV_IRQn = 0, /* CSV_IRQ */ + SWDT_IRQn = 1, /* SWDT_IRQ */ + LVD_IRQn = 2, /* LVD_IRQ */ + IRQ003SEL_IRQn = 3, /* IRQ003SEL_IRQ */ + IRQ004SEL_IRQn = 4, /* IRQ004SEL_IRQ */ + IRQ005SEL_IRQn = 5, /* IRQ005SEL_IRQ */ + IRQ006SEL_IRQn = 6, /* IRQ006SEL_IRQ */ + IRQ007SEL_IRQn = 7, /* IRQ007SEL_IRQ */ + IRQ008SEL_IRQn = 8, /* IRQ008SEL_IRQ */ + IRQ009SEL_IRQn = 9, /* IRQ009SEL_IRQ */ + IRQ010SEL_IRQn = 10, /* IRQ010SEL_IRQ */ + EXINT0_IRQn = 11, /* EXINT0_IRQ */ + EXINT1_IRQn = 12, /* EXINT1_IRQ */ + EXINT2_IRQn = 13, /* EXINT2_IRQ */ + EXINT3_IRQn = 14, /* EXINT3_IRQ */ + EXINT4_IRQn = 15, /* EXINT4_IRQ */ + EXINT5_IRQn = 16, /* EXINT5_IRQ */ + EXINT6_IRQn = 17, /* EXINT6_IRQ */ + EXINT7_IRQn = 18, /* EXINT7_IRQ */ + QPRC0_IRQn = 19, /* QPRC0_IRQ */ + QPRC1_IRQn = 20, /* QPRC1_IRQ */ + MFT0_WFG_DTIF_IRQn = 21, /* MFT0_WFG_DTIF_IRQ */ + MFT1_WFG_DTIF_IRQn = 22, /* MFT1_WFG_DTIF_IRQ */ + MFT2_WFG_DTIF_IRQn = 23, /* MFT2_WFG_DTIF_IRQ */ + MFT0_FRT_PEAK_IRQn = 24, /* MFT0_FRT_PEAK_IRQ */ + MFT0_FRT_ZERO_IRQn = 25, /* MFT0_FRT_ZERO_IRQ */ + MFT0_ICU_IRQn = 26, /* MFT0_ICU_IRQ */ + MFT0_OCU_IRQn = 27, /* MFT0_OCU_IRQ */ + MFT1_FRT_PEAK_IRQn = 28, /* MFT1_FRT_PEAK_IRQ */ + MFT1_FRT_ZERO_IRQn = 29, /* MFT1_FRT_ZERO_IRQ */ + MFT1_ICU_IRQn = 30, /* MFT1_ICU_IRQ */ + MFT1_OCU_IRQn = 31, /* MFT1_OCU_IRQ */ + MFT2_FRT_PEAK_IRQn = 32, /* MFT2_FRT_PEAK_IRQ */ + MFT2_FRT_ZERO_IRQn = 33, /* MFT2_FRT_ZERO_IRQ */ + MFT2_ICU_IRQn = 34, /* MFT2_ICU_IRQ */ + MFT2_OCU_IRQn = 35, /* MFT2_OCU_IRQ */ + PPG00_02_04_IRQn = 36, /* PPG00_02_04_IRQ */ + PPG08_10_12_IRQn = 37, /* PPG08_10_12_IRQ */ + PPG16_18_20_IRQn = 38, /* PPG16_18_20_IRQ */ + BT0_IRQn = 39, /* BT0_IRQ */ + BT1_IRQn = 40, /* BT1_IRQ */ + BT2_IRQn = 41, /* BT2_IRQ */ + BT3_IRQn = 42, /* BT3_IRQ */ + BT4_IRQn = 43, /* BT4_IRQ */ + BT5_IRQn = 44, /* BT5_IRQ */ + BT6_IRQn = 45, /* BT6_IRQ */ + BT7_IRQn = 46, /* BT7_IRQ */ + DT_IRQn = 47, /* DT_IRQ */ + WC_IRQn = 48, /* WC_IRQ */ + EXTBUS_ERR_IRQn = 49, /* EXTBUS_ERR_IRQ */ + RTC_IRQn = 50, /* RTC_IRQ */ + EXINT8_IRQn = 51, /* EXINT8_IRQ */ + EXINT9_IRQn = 52, /* EXINT9_IRQ */ + EXINT10_IRQn = 53, /* EXINT10_IRQ */ + EXINT11_IRQn = 54, /* EXINT11_IRQ */ + EXINT12_IRQn = 55, /* EXINT12_IRQ */ + EXINT13_IRQn = 56, /* EXINT13_IRQ */ + EXINT14_IRQn = 57, /* EXINT14_IRQ */ + EXINT15_IRQn = 58, /* EXINT15_IRQ */ + TIM_IRQn = 59, /* TIM_IRQ */ + MFS0_RX_IRQn = 60, /* MFS0_RX_IRQ */ + MFS0_TX_IRQn = 61, /* MFS0_TX_IRQ */ + MFS1_RX_IRQn = 62, /* MFS1_RX_IRQ */ + MFS1_TX_IRQn = 63, /* MFS1_TX_IRQ */ + MFS2_RX_IRQn = 64, /* MFS2_RX_IRQ */ + MFS2_TX_IRQn = 65, /* MFS2_TX_IRQ */ + MFS3_RX_IRQn = 66, /* MFS3_RX_IRQ */ + MFS3_TX_IRQn = 67, /* MFS3_TX_IRQ */ + MFS4_RX_IRQn = 68, /* MFS4_RX_IRQ */ + MFS4_TX_IRQn = 69, /* MFS4_TX_IRQ */ + MFS5_RX_IRQn = 70, /* MFS5_RX_IRQ */ + MFS5_TX_IRQn = 71, /* MFS5_TX_IRQ */ + MFS6_RX_IRQn = 72, /* MFS6_RX_IRQ */ + MFS6_TX_IRQn = 73, /* MFS6_TX_IRQ */ + MFS7_RX_IRQn = 74, /* MFS7_RX_IRQ */ + MFS7_TX_IRQn = 75, /* MFS7_TX_IRQ */ + ADC0_IRQn = 76, /* ADC0_IRQ */ + ADC1_IRQn = 77, /* ADC1_IRQ */ + USB0_F_IRQn = 78, /* USB0_F_IRQ */ + USB0_H_F_IRQn = 79, /* USB0_H_F_IRQ */ + CAN0_IRQn = 80, /* CAN0_IRQ */ + CAN1_CANFD0_IRQn = 81, /* CAN1_CANFD0_IRQ */ + DMAC0_IRQn = 83, /* DMAC0_IRQ */ + DMAC1_IRQn = 84, /* DMAC1_IRQ */ + DMAC2_IRQn = 85, /* DMAC2_IRQ */ + DMAC3_IRQn = 86, /* DMAC3_IRQ */ + DMAC4_IRQn = 87, /* DMAC4_IRQ */ + DMAC5_IRQn = 88, /* DMAC5_IRQ */ + DMAC6_IRQn = 89, /* DMAC6_IRQ */ + DMAC7_IRQn = 90, /* DMAC7_IRQ */ + DSTC_IRQn = 91, /* DSTC_IRQ */ + EXINT16_19_IRQn = 92, /* EXINT16_19_IRQ */ + EXINT20_23_IRQn = 93, /* EXINT20_23_IRQ */ + EXINT24_27_IRQn = 94, /* EXINT24_27_IRQ */ + EXINT28_31_IRQn = 95, /* EXINT28_31_IRQ */ + QPRC2_IRQn = 96, /* QPRC2_IRQ */ + QPRC3_IRQn = 97, /* QPRC3_IRQ */ + BT8_IRQn = 98, /* BT8_IRQ */ + BT9_IRQn = 99, /* BT9_IRQ */ + BT10_IRQn = 100, /* BT10_IRQ */ + BT11_IRQn = 101, /* BT11_IRQ */ + BT12_15_IRQn = 102, /* BT12_15_IRQ */ + MFS8_RX_IRQn = 103, /* MFS8_RX_IRQ */ + MFS8_TX_IRQn = 104, /* MFS8_TX_IRQ */ + MFS9_RX_IRQn = 105, /* MFS9_RX_IRQ */ + MFS9_TX_IRQn = 106, /* MFS9_TX_IRQ */ + MFS10_RX_IRQn = 107, /* MFS10_RX_IRQ */ + MFS10_TX_IRQn = 108, /* MFS10_TX_IRQ */ + MFS11_RX_IRQn = 109, /* MFS11_RX_IRQ */ + MFS11_TX_IRQn = 110, /* MFS11_TX_IRQ */ + ADC2_IRQn = 111, /* ADC2_IRQ */ + DSTC_HW_IRQn = 112, /* DSTC_HW_IRQ */ + USB1_F_IRQn = 113, /* USB1_F_IRQ */ + USB1_H_F_IRQn = 114, /* USB1_H_F_IRQ */ + HSSPI_IRQn = 115, /* HSSPI_IRQ */ + PCRC_I2S0_1_IRQn = 117, /* PCRC_I2S0_1_IRQ */ + SD_IRQn = 118, /* SD_IRQ */ + FLASHIF_IRQn = 119, /* FLASHIF_IRQ */ + MFS12_RX_IRQn = 120, /* MFS12_RX_IRQ */ + MFS12_TX_IRQn = 121, /* MFS12_TX_IRQ */ + MFS13_RX_IRQn = 122, /* MFS13_RX_IRQ */ + MFS13_TX_IRQn = 123, /* MFS13_TX_IRQ */ + MFS14_RX_IRQn = 124, /* MFS14_RX_IRQ */ + MFS14_TX_IRQn = 125, /* MFS14_TX_IRQ */ + MFS15_RX_IRQn = 126, /* MFS15_RX_IRQ */ + MFS15_TX_IRQn = 127, /* MFS15_TX_IRQ */ +} IRQn_Type; + +#include "core_cm4.h" +#include + +/******************************************************************************* +* Device Specific Peripheral Registers structures +*******************************************************************************/ +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************* +* ADC_MODULE +*******************************************************************************/ +typedef struct stc_adc_adsr_field +{ + __IO uint8_t SCS :1; + __IO uint8_t PCS :1; + __IO uint8_t PCNS :1; + __IO uint8_t RESERVED0 :3; + __IO uint8_t FDAS :1; + __IO uint8_t ADSTP :1; +} stc_adc_adsr_field_t; + +typedef struct stc_adc_adcr_field +{ + __IO uint8_t OVRIE :1; + __IO uint8_t CMPIE :1; + __IO uint8_t PCIE :1; + __IO uint8_t SCIE :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t CMPIF :1; + __IO uint8_t PCIF :1; + __IO uint8_t SCIF :1; +} stc_adc_adcr_field_t; + +typedef struct stc_adc_sfns_field +{ + union { + struct { + __IO uint8_t SFS :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t SFS0 :1; + __IO uint8_t SFS1 :1; + __IO uint8_t SFS2 :1; + __IO uint8_t SFS3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_adc_sfns_field_t; + +typedef struct stc_adc_sccr_field +{ + __IO uint8_t SSTR :1; + __IO uint8_t SHEN :1; + __IO uint8_t RPT :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t SFCLR :1; + __IO uint8_t SOVR :1; + __IO uint8_t SFUL :1; + __IO uint8_t SEMP :1; +} stc_adc_sccr_field_t; + +typedef struct stc_adc_scfd_fdas1_field +{ + union { + struct { + __IO uint32_t SC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t SD :12; + __IO uint32_t RESERVED5 :4; + }; + struct { + __IO uint32_t SC0 :1; + __IO uint32_t SC1 :1; + __IO uint32_t SC2 :1; + __IO uint32_t SC3 :1; + __IO uint32_t SC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RESERVED4 :6; + __IO uint32_t SD0 :1; + __IO uint32_t SD1 :1; + __IO uint32_t SD2 :1; + __IO uint32_t SD3 :1; + __IO uint32_t SD4 :1; + __IO uint32_t SD5 :1; + __IO uint32_t SD6 :1; + __IO uint32_t SD7 :1; + __IO uint32_t SD8 :1; + __IO uint32_t SD9 :1; + __IO uint32_t SD10 :1; + __IO uint32_t SD11 :1; + __IO uint32_t RESERVED6 :4; + }; + }; +} stc_adc_scfd_fdas1_field_t; + +typedef struct stc_adc_scfd_field +{ + union { + struct { + __IO uint32_t SC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :7; + __IO uint32_t SD :12; + }; + struct { + __IO uint32_t SC0 :1; + __IO uint32_t SC1 :1; + __IO uint32_t SC2 :1; + __IO uint32_t SC3 :1; + __IO uint32_t SC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RESERVED4 :10; + __IO uint32_t SD0 :1; + __IO uint32_t SD1 :1; + __IO uint32_t SD2 :1; + __IO uint32_t SD3 :1; + __IO uint32_t SD4 :1; + __IO uint32_t SD5 :1; + __IO uint32_t SD6 :1; + __IO uint32_t SD7 :1; + __IO uint32_t SD8 :1; + __IO uint32_t SD9 :1; + __IO uint32_t SD10 :1; + __IO uint32_t SD11 :1; + }; + }; +} stc_adc_scfd_field_t; + +typedef struct stc_adc_scis23_field +{ + __IO uint16_t AN16 :1; + __IO uint16_t AN17 :1; + __IO uint16_t AN18 :1; + __IO uint16_t AN19 :1; + __IO uint16_t AN20 :1; + __IO uint16_t AN21 :1; + __IO uint16_t AN22 :1; + __IO uint16_t AN23 :1; + __IO uint16_t AN24 :1; + __IO uint16_t AN25 :1; + __IO uint16_t AN26 :1; + __IO uint16_t AN27 :1; + __IO uint16_t AN28 :1; + __IO uint16_t AN29 :1; + __IO uint16_t AN30 :1; + __IO uint16_t AN31 :1; +} stc_adc_scis23_field_t; + +typedef struct stc_adc_scis01_field +{ + __IO uint16_t AN0 :1; + __IO uint16_t AN1 :1; + __IO uint16_t AN2 :1; + __IO uint16_t AN3 :1; + __IO uint16_t AN4 :1; + __IO uint16_t AN5 :1; + __IO uint16_t AN6 :1; + __IO uint16_t AN7 :1; + __IO uint16_t AN8 :1; + __IO uint16_t AN9 :1; + __IO uint16_t AN10 :1; + __IO uint16_t AN11 :1; + __IO uint16_t AN12 :1; + __IO uint16_t AN13 :1; + __IO uint16_t AN14 :1; + __IO uint16_t AN15 :1; +} stc_adc_scis01_field_t; + +typedef struct stc_adc_pfns_field +{ + union { + struct { + __IO uint8_t PFS :2; + __IO uint8_t RESERVED0 :2; + __IO uint8_t TEST :2; + __IO uint8_t RESERVED2 :2; + }; + struct { + __IO uint8_t PFS0 :1; + __IO uint8_t PFS1 :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t TEST0 :1; + __IO uint8_t TEST1 :1; + __IO uint8_t RESERVED3 :2; + }; + }; +} stc_adc_pfns_field_t; + +typedef struct stc_adc_pccr_field +{ + __IO uint8_t PSTR :1; + __IO uint8_t PHEN :1; + __IO uint8_t PEEN :1; + __IO uint8_t ESCE :1; + __IO uint8_t PFCLR :1; + __IO uint8_t POVR :1; + __IO uint8_t PFUL :1; + __IO uint8_t PEMP :1; +} stc_adc_pccr_field_t; + +typedef struct stc_adc_pcfd_fdas1_field +{ + union { + struct { + __IO uint32_t PC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t PD :12; + __IO uint32_t RESERVED5 :4; + }; + struct { + __IO uint32_t PC0 :1; + __IO uint32_t PC1 :1; + __IO uint32_t PC2 :1; + __IO uint32_t PC3 :1; + __IO uint32_t PC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RS2 :1; + __IO uint32_t RESERVED4 :5; + __IO uint32_t PD0 :1; + __IO uint32_t PD1 :1; + __IO uint32_t PD2 :1; + __IO uint32_t PD3 :1; + __IO uint32_t PD4 :1; + __IO uint32_t PD5 :1; + __IO uint32_t PD6 :1; + __IO uint32_t PD7 :1; + __IO uint32_t PD8 :1; + __IO uint32_t PD9 :1; + __IO uint32_t PD10 :1; + __IO uint32_t PD11 :1; + __IO uint32_t RESERVED6 :4; + }; + }; +} stc_adc_pcfd_fdas1_field_t; + +typedef struct stc_adc_pcfd_field +{ + union { + struct { + __IO uint32_t PC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :7; + __IO uint32_t PD :12; + }; + struct { + __IO uint32_t PC0 :1; + __IO uint32_t PC1 :1; + __IO uint32_t PC2 :1; + __IO uint32_t PC3 :1; + __IO uint32_t PC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RS2 :1; + __IO uint32_t RESERVED4 :9; + __IO uint32_t PD0 :1; + __IO uint32_t PD1 :1; + __IO uint32_t PD2 :1; + __IO uint32_t PD3 :1; + __IO uint32_t PD4 :1; + __IO uint32_t PD5 :1; + __IO uint32_t PD6 :1; + __IO uint32_t PD7 :1; + __IO uint32_t PD8 :1; + __IO uint32_t PD9 :1; + __IO uint32_t PD10 :1; + __IO uint32_t PD11 :1; + }; + }; +} stc_adc_pcfd_field_t; + +typedef struct stc_adc_pcis_field +{ + union { + struct { + __IO uint8_t P1A :3; + __IO uint8_t P2A :5; + }; + struct { + __IO uint8_t P1A0 :1; + __IO uint8_t P1A1 :1; + __IO uint8_t P1A2 :1; + __IO uint8_t P2A0 :1; + __IO uint8_t P2A1 :1; + __IO uint8_t P2A2 :1; + __IO uint8_t P2A3 :1; + __IO uint8_t P2A4 :1; + }; + }; +} stc_adc_pcis_field_t; + +typedef struct stc_adc_cmpcr_field +{ + union { + struct { + __IO uint8_t CCH :5; + __IO uint8_t CMD0 :1; + __IO uint8_t CMD1 :1; + __IO uint8_t CMPEN :1; + }; + struct { + __IO uint8_t CCH0 :1; + __IO uint8_t CCH1 :1; + __IO uint8_t CCH2 :1; + __IO uint8_t CCH3 :1; + __IO uint8_t CCH4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_adc_cmpcr_field_t; + +typedef struct stc_adc_cmpd_field +{ + union { + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CMAD :10; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t CMAD0 :1; + __IO uint16_t CMAD1 :1; + __IO uint16_t CMAD2 :1; + __IO uint16_t CMAD3 :1; + __IO uint16_t CMAD4 :1; + __IO uint16_t CMAD5 :1; + __IO uint16_t CMAD6 :1; + __IO uint16_t CMAD7 :1; + __IO uint16_t CMAD8 :1; + __IO uint16_t CMAD9 :1; + }; + }; +} stc_adc_cmpd_field_t; + +typedef struct stc_adc_adss23_field +{ + __IO uint16_t TS16 :1; + __IO uint16_t TS17 :1; + __IO uint16_t TS18 :1; + __IO uint16_t TS19 :1; + __IO uint16_t TS20 :1; + __IO uint16_t TS21 :1; + __IO uint16_t TS22 :1; + __IO uint16_t TS23 :1; + __IO uint16_t TS24 :1; + __IO uint16_t TS25 :1; + __IO uint16_t TS26 :1; + __IO uint16_t TS27 :1; + __IO uint16_t TS28 :1; + __IO uint16_t TS29 :1; + __IO uint16_t TS30 :1; + __IO uint16_t TS31 :1; +} stc_adc_adss23_field_t; + +typedef struct stc_adc_adss01_field +{ + __IO uint16_t TS0 :1; + __IO uint16_t TS1 :1; + __IO uint16_t TS2 :1; + __IO uint16_t TS3 :1; + __IO uint16_t TS4 :1; + __IO uint16_t TS5 :1; + __IO uint16_t TS6 :1; + __IO uint16_t TS7 :1; + __IO uint16_t TS8 :1; + __IO uint16_t TS9 :1; + __IO uint16_t TS10 :1; + __IO uint16_t TS11 :1; + __IO uint16_t TS12 :1; + __IO uint16_t TS13 :1; + __IO uint16_t TS14 :1; + __IO uint16_t TS15 :1; +} stc_adc_adss01_field_t; + +typedef struct stc_adc_adst01_field +{ + union { + struct { + __IO uint16_t ST1 :5; + __IO uint16_t STX1 :3; + __IO uint16_t ST0 :5; + __IO uint16_t STX0 :3; + }; + struct { + __IO uint16_t ST10 :1; + __IO uint16_t ST11 :1; + __IO uint16_t ST12 :1; + __IO uint16_t ST13 :1; + __IO uint16_t ST14 :1; + __IO uint16_t STX10 :1; + __IO uint16_t STX11 :1; + __IO uint16_t STX12 :1; + __IO uint16_t ST00 :1; + __IO uint16_t ST01 :1; + __IO uint16_t ST02 :1; + __IO uint16_t ST03 :1; + __IO uint16_t ST04 :1; + __IO uint16_t STX00 :1; + __IO uint16_t STX01 :1; + __IO uint16_t STX02 :1; + }; + }; +} stc_adc_adst01_field_t; + +typedef struct stc_adc_adct_field +{ + union { + struct { + __IO uint8_t CT :8; + }; + struct { + __IO uint8_t CT0 :1; + __IO uint8_t CT1 :1; + __IO uint8_t CT2 :1; + __IO uint8_t CT3 :1; + __IO uint8_t CT4 :1; + __IO uint8_t CT5 :1; + __IO uint8_t CT6 :1; + __IO uint8_t CT7 :1; + }; + }; +} stc_adc_adct_field_t; + +typedef struct stc_adc_prtsl_field +{ + union { + struct { + __IO uint8_t PRTSL :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t PRTSL0 :1; + __IO uint8_t PRTSL1 :1; + __IO uint8_t PRTSL2 :1; + __IO uint8_t PRTSL3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_adc_prtsl_field_t; + +typedef struct stc_adc_sctsl_field +{ + union { + struct { + __IO uint8_t SCTSL :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t SCTSL0 :1; + __IO uint8_t SCTSL1 :1; + __IO uint8_t SCTSL2 :1; + __IO uint8_t SCTSL3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_adc_sctsl_field_t; + +typedef struct stc_adc_adcen_field +{ + union { + struct { + __IO uint16_t ENBL :1; + __IO uint16_t READY :1; + __IO uint16_t RESERVED0 :6; + __IO uint16_t ENBLTIME :8; + }; + struct { + __IO uint16_t RESERVED1 :8; + __IO uint16_t ENBLTIME0 :1; + __IO uint16_t ENBLTIME1 :1; + __IO uint16_t ENBLTIME2 :1; + __IO uint16_t ENBLTIME3 :1; + __IO uint16_t ENBLTIME4 :1; + __IO uint16_t ENBLTIME5 :1; + __IO uint16_t ENBLTIME6 :1; + __IO uint16_t ENBLTIME7 :1; + }; + }; +} stc_adc_adcen_field_t; + +typedef struct stc_adc_calsr_field +{ + union { + struct { + __IO uint32_t OFST :8; + __IO uint32_t CLBEN :1; + __IO uint32_t RESERVED0 :23; + }; + struct { + __IO uint32_t OFST0 :1; + __IO uint32_t OFST1 :1; + __IO uint32_t OFST2 :1; + __IO uint32_t OFST3 :1; + __IO uint32_t OFST4 :1; + __IO uint32_t OFST5 :1; + __IO uint32_t OFST6 :1; + __IO uint32_t OFST7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_adc_calsr_field_t; + +typedef struct stc_adc_wcmrcot_field +{ + __IO uint8_t RCOOF :1; + __IO uint8_t RESERVED0 :7; +} stc_adc_wcmrcot_field_t; + +typedef struct stc_adc_wcmrcif_field +{ + __IO uint8_t RCINT :1; + __IO uint8_t RESERVED0 :7; +} stc_adc_wcmrcif_field_t; + +typedef struct stc_adc_wcmpcr_field +{ + union { + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t RCOE :1; + __IO uint8_t RCOIE :1; + __IO uint8_t RCOIRS :1; + __IO uint8_t RCOCD :3; + }; + struct { + __IO uint8_t RESERVED1 :5; + __IO uint8_t RCOCD0 :1; + __IO uint8_t RCOCD1 :1; + __IO uint8_t RCOCD2 :1; + }; + }; +} stc_adc_wcmpcr_field_t; + +typedef struct stc_adc_wcmpsr_field +{ + union { + struct { + __IO uint8_t WCCH :5; + __IO uint8_t WCMD :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t WCCH0 :1; + __IO uint8_t WCCH1 :1; + __IO uint8_t WCCH2 :1; + __IO uint8_t WCCH3 :1; + __IO uint8_t WCCH4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_adc_wcmpsr_field_t; + +typedef struct stc_adc_wcmpdl_field +{ + union { + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CMLD :10; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t CMLD0 :1; + __IO uint16_t CMLD1 :1; + __IO uint16_t CMLD2 :1; + __IO uint16_t CMLD3 :1; + __IO uint16_t CMLD4 :1; + __IO uint16_t CMLD5 :1; + __IO uint16_t CMLD6 :1; + __IO uint16_t CMLD7 :1; + __IO uint16_t CMLD8 :1; + __IO uint16_t CMLD9 :1; + }; + }; +} stc_adc_wcmpdl_field_t; + +typedef struct stc_adc_wcmpdh_field +{ + union { + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CMHD :10; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t CMHD0 :1; + __IO uint16_t CMHD1 :1; + __IO uint16_t CMHD2 :1; + __IO uint16_t CMHD3 :1; + __IO uint16_t CMHD4 :1; + __IO uint16_t CMHD5 :1; + __IO uint16_t CMHD6 :1; + __IO uint16_t CMHD7 :1; + __IO uint16_t CMHD8 :1; + __IO uint16_t CMHD9 :1; + }; + }; +} stc_adc_wcmpdh_field_t; + +/******************************************************************************* +* BT_MODULE +*******************************************************************************/ +typedef struct stc_bt_tmcr_field +{ + union { + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t RESERVED1 :1; + __IO uint16_t EGS :2; + __IO uint16_t PMSK :1; + __IO uint16_t RTGEN :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t RESERVED0 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED2 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED3 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED5 :1; + }; + }; + union { + struct { + __IO uint16_t RESERVED6 :7; + __IO uint16_t T32 :1; + __IO uint16_t RESERVED7 :8; + }; + struct { + __IO uint16_t RESERVED8 :16; + }; + }; + }; +} stc_bt_tmcr_field_t; + +typedef struct stc_bt_stc_field +{ + union { + struct { + __IO uint8_t UDIR :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED1 :1; + __IO uint8_t UDIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t OVIR :1; + __IO uint8_t RESERVED5 :1; + __IO uint8_t EDIR :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t OVIE :1; + __IO uint8_t RESERVED7 :1; + __IO uint8_t EDIE :1; + __IO uint8_t ERR :1; + }; + struct { + __IO uint8_t RESERVED9 :1; + __IO uint8_t DTIR :1; + __IO uint8_t RESERVED10 :3; + __IO uint8_t DTIE :1; + __IO uint8_t RESERVED11 :2; + }; + }; +} stc_bt_stc_field_t; + +typedef struct stc_bt_tmcr2_field +{ + union { + struct { + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED0 :7; + }; + struct { + __IO uint8_t RESERVED6 :7; + __IO uint8_t GATE :1; + }; + }; +} stc_bt_tmcr2_field_t; + +typedef struct stc_bt_ppg_tmcr_field +{ + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t RESERVED1 :1; + __IO uint16_t EGS :2; + __IO uint16_t PMSK :1; + __IO uint16_t RTGEN :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t RESERVED0 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED2 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED3 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_bt_ppg_tmcr_field_t; + +typedef struct stc_bt_pwc_tmcr_field +{ + union { + struct { + __IO uint16_t RESERVED6 :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t RESERVED7 :1; + __IO uint16_t FMD :3; + __IO uint16_t T32 :1; + __IO uint16_t EGS :3; + __IO uint16_t RESERVED10 :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED12 :1; + }; + struct { + __IO uint16_t RESERVED8 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED9 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t EGS2 :1; + __IO uint16_t RESERVED11 :1; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED13 :1; + }; + }; +} stc_bt_pwc_tmcr_field_t; + +typedef struct stc_bt_pwm_tmcr_field +{ + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t RESERVED15 :1; + __IO uint16_t EGS :2; + __IO uint16_t PMSK :1; + __IO uint16_t RTGEN :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED18 :1; + }; + struct { + __IO uint16_t RESERVED14 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED16 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED17 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED19 :1; + }; + }; +} stc_bt_pwm_tmcr_field_t; + +typedef struct stc_bt_rt_tmcr_field +{ + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t T32 :1; + __IO uint16_t EGS :2; + __IO uint16_t RESERVED22 :2; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED24 :1; + }; + struct { + __IO uint16_t RESERVED20 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED21 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED23 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED25 :1; + }; + }; +} stc_bt_rt_tmcr_field_t; + +typedef struct stc_bt_ppg_stc_field +{ + __IO uint8_t UDIR :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED1 :1; + __IO uint8_t UDIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED3 :1; +} stc_bt_ppg_stc_field_t; + +typedef struct stc_bt_pwc_stc_field +{ + __IO uint8_t OVIR :1; + __IO uint8_t RESERVED5 :1; + __IO uint8_t EDIR :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t OVIE :1; + __IO uint8_t RESERVED7 :1; + __IO uint8_t EDIE :1; + __IO uint8_t ERR :1; +} stc_bt_pwc_stc_field_t; + +typedef struct stc_bt_pwm_stc_field +{ + __IO uint8_t UDIR :1; + __IO uint8_t DTIR :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED9 :1; + __IO uint8_t UDIE :1; + __IO uint8_t DTIE :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED10 :1; +} stc_bt_pwm_stc_field_t; + +typedef struct stc_bt_rt_stc_field +{ + __IO uint8_t UDIR :1; + __IO uint8_t RESERVED12 :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED13 :1; + __IO uint8_t UDIE :1; + __IO uint8_t RESERVED14 :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED15 :1; +} stc_bt_rt_stc_field_t; + +typedef struct stc_bt_ppg_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED0 :7; +} stc_bt_ppg_tmcr2_field_t; + +typedef struct stc_bt_pwc_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED2 :7; +} stc_bt_pwc_tmcr2_field_t; + +typedef struct stc_bt_pwm_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED4 :7; +} stc_bt_pwm_tmcr2_field_t; + +typedef struct stc_bt_rt_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED6 :6; + __IO uint8_t GATE :1; +} stc_bt_rt_tmcr2_field_t; + +/******************************************************************************* +* BTIOSEL03_MODULE +*******************************************************************************/ +typedef struct stc_btiosel03_btsel0123_field +{ + union { + struct { + __IO uint8_t SEL01 :4; + __IO uint8_t SEL23 :4; + }; + struct { + __IO uint8_t SEL010 :1; + __IO uint8_t SEL011 :1; + __IO uint8_t SEL012 :1; + __IO uint8_t SEL013 :1; + __IO uint8_t SEL230 :1; + __IO uint8_t SEL231 :1; + __IO uint8_t SEL232 :1; + __IO uint8_t SEL233 :1; + }; + }; +} stc_btiosel03_btsel0123_field_t; + +/******************************************************************************* +* BTIOSEL47_MODULE +*******************************************************************************/ +typedef struct stc_btiosel47_btsel4567_field +{ + union { + struct { + __IO uint8_t SEL45 :4; + __IO uint8_t SEL67 :4; + }; + struct { + __IO uint8_t SEL450 :1; + __IO uint8_t SEL451 :1; + __IO uint8_t SEL452 :1; + __IO uint8_t SEL453 :1; + __IO uint8_t SEL670 :1; + __IO uint8_t SEL671 :1; + __IO uint8_t SEL672 :1; + __IO uint8_t SEL673 :1; + }; + }; +} stc_btiosel47_btsel4567_field_t; + +/******************************************************************************* +* BTIOSEL8B_MODULE +*******************************************************************************/ +typedef struct stc_btiosel8b_btsel89ab_field +{ + union { + struct { + __IO uint8_t SEL89 :4; + __IO uint8_t SELAB :4; + }; + struct { + __IO uint8_t SEL890 :1; + __IO uint8_t SEL891 :1; + __IO uint8_t SEL892 :1; + __IO uint8_t SEL893 :1; + __IO uint8_t SELAB0 :1; + __IO uint8_t SELAB1 :1; + __IO uint8_t SELAB2 :1; + __IO uint8_t SELAB3 :1; + }; + }; +} stc_btiosel8b_btsel89ab_field_t; + +/******************************************************************************* +* BTIOSELCF_MODULE +*******************************************************************************/ +typedef struct stc_btioselcf_btselcdef_field +{ + union { + struct { + __IO uint8_t SELCD :4; + __IO uint8_t SELEF :4; + }; + struct { + __IO uint8_t SELCD0 :1; + __IO uint8_t SELCD1 :1; + __IO uint8_t SELCD2 :1; + __IO uint8_t SELCD3 :1; + __IO uint8_t SELEF0 :1; + __IO uint8_t SELEF1 :1; + __IO uint8_t SELEF2 :1; + __IO uint8_t SELEF3 :1; + }; + }; +} stc_btioselcf_btselcdef_field_t; + +/******************************************************************************* +* CAN_MODULE +*******************************************************************************/ +typedef struct stc_can_ctrlr_field +{ + __IO uint16_t INIT :1; + __IO uint16_t IE :1; + __IO uint16_t SIE :1; + __IO uint16_t EIE :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t DAR :1; + __IO uint16_t CCE :1; + __IO uint16_t TEST :1; + __IO uint16_t RESERVED1 :8; +} stc_can_ctrlr_field_t; + +typedef struct stc_can_statr_field +{ + union { + struct { + __IO uint16_t LEC :3; + __IO uint16_t TXOK :1; + __IO uint16_t RXOK :1; + __IO uint16_t EPASS :1; + __IO uint16_t EWARN :1; + __IO uint16_t BOFF :1; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t LEC0 :1; + __IO uint16_t LEC1 :1; + __IO uint16_t LEC2 :1; + __IO uint16_t RESERVED1 :13; + }; + }; +} stc_can_statr_field_t; + +typedef struct stc_can_errcnt_field +{ + union { + struct { + __IO uint16_t TEC :8; + __IO uint16_t REC :7; + __IO uint16_t RP :1; + }; + struct { + __IO uint16_t TEC0 :1; + __IO uint16_t TEC1 :1; + __IO uint16_t TEC2 :1; + __IO uint16_t TEC3 :1; + __IO uint16_t TEC4 :1; + __IO uint16_t TEC5 :1; + __IO uint16_t TEC6 :1; + __IO uint16_t TEC7 :1; + __IO uint16_t REC0 :1; + __IO uint16_t REC1 :1; + __IO uint16_t REC2 :1; + __IO uint16_t REC3 :1; + __IO uint16_t REC4 :1; + __IO uint16_t REC5 :1; + __IO uint16_t REC6 :1; + __IO uint16_t RESERVED0 :1; + }; + }; +} stc_can_errcnt_field_t; + +typedef struct stc_can_btr_field +{ + union { + struct { + __IO uint16_t BRP :6; + __IO uint16_t SJW :2; + __IO uint16_t TSEG1 :4; + __IO uint16_t TSEG2 :3; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t BRP0 :1; + __IO uint16_t BRP1 :1; + __IO uint16_t BRP2 :1; + __IO uint16_t BRP3 :1; + __IO uint16_t BRP4 :1; + __IO uint16_t BRP5 :1; + __IO uint16_t SJW0 :1; + __IO uint16_t SJW1 :1; + __IO uint16_t TSEG10 :1; + __IO uint16_t TSEG11 :1; + __IO uint16_t TSEG12 :1; + __IO uint16_t TSEG13 :1; + __IO uint16_t TSEG20 :1; + __IO uint16_t TSEG21 :1; + __IO uint16_t TSEG22 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_can_btr_field_t; + +typedef struct stc_can_intr_field +{ + union { + struct { + __IO uint16_t INTID :16; + }; + struct { + __IO uint16_t INTID0 :1; + __IO uint16_t INTID1 :1; + __IO uint16_t INTID2 :1; + __IO uint16_t INTID3 :1; + __IO uint16_t INTID4 :1; + __IO uint16_t INTID5 :1; + __IO uint16_t INTID6 :1; + __IO uint16_t INTID7 :1; + __IO uint16_t INTID8 :1; + __IO uint16_t INTID9 :1; + __IO uint16_t INTID10 :1; + __IO uint16_t INTID11 :1; + __IO uint16_t INTID12 :1; + __IO uint16_t INTID13 :1; + __IO uint16_t INTID14 :1; + __IO uint16_t INTID15 :1; + }; + }; +} stc_can_intr_field_t; + +typedef struct stc_can_testr_field +{ + union { + struct { + __IO uint16_t RESERVED0 :2; + __IO uint16_t BASIC :1; + __IO uint16_t SILENT :1; + __IO uint16_t LBACK :1; + __IO uint16_t TX :2; + __IO uint16_t RX :1; + __IO uint16_t RESERVED2 :8; + }; + struct { + __IO uint16_t RESERVED1 :5; + __IO uint16_t TX0 :1; + __IO uint16_t TX1 :1; + __IO uint16_t RESERVED3 :9; + }; + }; +} stc_can_testr_field_t; + +typedef struct stc_can_brper_field +{ + union { + struct { + __IO uint16_t BRPE :4; + __IO uint16_t RESERVED0 :12; + }; + struct { + __IO uint16_t BRPE0 :1; + __IO uint16_t BRPE1 :1; + __IO uint16_t BRPE2 :1; + __IO uint16_t BRPE3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_can_brper_field_t; + +typedef struct stc_can_if1creq_field +{ + union { + struct { + __IO uint16_t MESSAGENUMBER :8; + __IO uint16_t RESERVED0 :7; + __IO uint16_t BUSY :1; + }; + struct { + __IO uint16_t MESSAGENUMBER0 :1; + __IO uint16_t MESSAGENUMBER1 :1; + __IO uint16_t MESSAGENUMBER2 :1; + __IO uint16_t MESSAGENUMBER3 :1; + __IO uint16_t MESSAGENUMBER4 :1; + __IO uint16_t MESSAGENUMBER5 :1; + __IO uint16_t MESSAGENUMBER6 :1; + __IO uint16_t MESSAGENUMBER7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_can_if1creq_field_t; + +typedef struct stc_can_if1cmsk_field +{ + __IO uint16_t DATAB :1; + __IO uint16_t DATAA :1; + __IO uint16_t NEWDAT :1; + __IO uint16_t CIP :1; + __IO uint16_t CONTROL :1; + __IO uint16_t ARB :1; + __IO uint16_t MASK :1; + __IO uint16_t WR_RD :1; + __IO uint16_t RESERVED0 :8; +} stc_can_if1cmsk_field_t; + +typedef struct stc_can_if1msk_field +{ + union { + struct { + __IO uint32_t MSK :29; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MDIR :1; + __IO uint32_t MXTD :1; + }; + struct { + __IO uint32_t MSK0 :1; + __IO uint32_t MSK1 :1; + __IO uint32_t MSK2 :1; + __IO uint32_t MSK3 :1; + __IO uint32_t MSK4 :1; + __IO uint32_t MSK5 :1; + __IO uint32_t MSK6 :1; + __IO uint32_t MSK7 :1; + __IO uint32_t MSK8 :1; + __IO uint32_t MSK9 :1; + __IO uint32_t MSK10 :1; + __IO uint32_t MSK11 :1; + __IO uint32_t MSK12 :1; + __IO uint32_t MSK13 :1; + __IO uint32_t MSK14 :1; + __IO uint32_t MSK15 :1; + __IO uint32_t MSK16 :1; + __IO uint32_t MSK17 :1; + __IO uint32_t MSK18 :1; + __IO uint32_t MSK19 :1; + __IO uint32_t MSK20 :1; + __IO uint32_t MSK21 :1; + __IO uint32_t MSK22 :1; + __IO uint32_t MSK23 :1; + __IO uint32_t MSK24 :1; + __IO uint32_t MSK25 :1; + __IO uint32_t MSK26 :1; + __IO uint32_t MSK27 :1; + __IO uint32_t MSK28 :1; + __IO uint32_t RESERVED1 :3; + }; + }; +} stc_can_if1msk_field_t; + +typedef struct stc_can_if1arb_field +{ + union { + struct { + __IO uint32_t ID :29; + __IO uint32_t DIR :1; + __IO uint32_t XTD :1; + __IO uint32_t MSGVAL :1; + }; + struct { + __IO uint32_t ID0 :1; + __IO uint32_t ID1 :1; + __IO uint32_t ID2 :1; + __IO uint32_t ID3 :1; + __IO uint32_t ID4 :1; + __IO uint32_t ID5 :1; + __IO uint32_t ID6 :1; + __IO uint32_t ID7 :1; + __IO uint32_t ID8 :1; + __IO uint32_t ID9 :1; + __IO uint32_t ID10 :1; + __IO uint32_t ID11 :1; + __IO uint32_t ID12 :1; + __IO uint32_t ID13 :1; + __IO uint32_t ID14 :1; + __IO uint32_t ID15 :1; + __IO uint32_t ID16 :1; + __IO uint32_t ID17 :1; + __IO uint32_t ID18 :1; + __IO uint32_t ID19 :1; + __IO uint32_t ID20 :1; + __IO uint32_t ID21 :1; + __IO uint32_t ID22 :1; + __IO uint32_t ID23 :1; + __IO uint32_t ID24 :1; + __IO uint32_t ID25 :1; + __IO uint32_t ID26 :1; + __IO uint32_t ID27 :1; + __IO uint32_t ID28 :1; + __IO uint32_t RESERVED0 :3; + }; + }; +} stc_can_if1arb_field_t; + +typedef struct stc_can_if1mctr_field +{ + union { + struct { + __IO uint16_t DLC :4; + __IO uint16_t RESERVED0 :3; + __IO uint16_t EOB :1; + __IO uint16_t TXRQST :1; + __IO uint16_t RMTEN :1; + __IO uint16_t RXIE :1; + __IO uint16_t TXIE :1; + __IO uint16_t UMASK :1; + __IO uint16_t INTPND :1; + __IO uint16_t MSGLST :1; + __IO uint16_t NEWDAT :1; + }; + struct { + __IO uint16_t DLC0 :1; + __IO uint16_t DLC1 :1; + __IO uint16_t DLC2 :1; + __IO uint16_t DLC3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_can_if1mctr_field_t; + +typedef struct stc_can_if1dta_l_field +{ + union { + struct { + __IO uint32_t DATA0 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA3 :8; + }; + struct { + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + }; + }; +} stc_can_if1dta_l_field_t; + +typedef struct stc_can_if1dtb_l_field +{ + union { + struct { + __IO uint32_t DATA4 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA7 :8; + }; + struct { + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + }; + }; +} stc_can_if1dtb_l_field_t; + +typedef struct stc_can_if1dta_b_field +{ + union { + struct { + __IO uint32_t DATA3 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA0 :8; + }; + struct { + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + }; + }; +} stc_can_if1dta_b_field_t; + +typedef struct stc_can_if1dtb_b_field +{ + union { + struct { + __IO uint32_t DATA7 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA4 :8; + }; + struct { + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + }; + }; +} stc_can_if1dtb_b_field_t; + +typedef struct stc_can_if2creq_field +{ + union { + struct { + __IO uint16_t MESSAGENUMBER :8; + __IO uint16_t RESERVED0 :7; + __IO uint16_t BUSY :1; + }; + struct { + __IO uint16_t MESSAGENUMBER0 :1; + __IO uint16_t MESSAGENUMBER1 :1; + __IO uint16_t MESSAGENUMBER2 :1; + __IO uint16_t MESSAGENUMBER3 :1; + __IO uint16_t MESSAGENUMBER4 :1; + __IO uint16_t MESSAGENUMBER5 :1; + __IO uint16_t MESSAGENUMBER6 :1; + __IO uint16_t MESSAGENUMBER7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_can_if2creq_field_t; + +typedef struct stc_can_if2cmsk_field +{ + __IO uint16_t DATAB :1; + __IO uint16_t DATAA :1; + __IO uint16_t NEWDAT :1; + __IO uint16_t CIP :1; + __IO uint16_t CONTROL :1; + __IO uint16_t ARB :1; + __IO uint16_t MASK :1; + __IO uint16_t WR_RD :1; + __IO uint16_t RESERVED0 :8; +} stc_can_if2cmsk_field_t; + +typedef struct stc_can_if2msk_field +{ + union { + struct { + __IO uint32_t MSK :29; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MDIR :1; + __IO uint32_t MXTD :1; + }; + struct { + __IO uint32_t MSK0 :1; + __IO uint32_t MSK1 :1; + __IO uint32_t MSK2 :1; + __IO uint32_t MSK3 :1; + __IO uint32_t MSK4 :1; + __IO uint32_t MSK5 :1; + __IO uint32_t MSK6 :1; + __IO uint32_t MSK7 :1; + __IO uint32_t MSK8 :1; + __IO uint32_t MSK9 :1; + __IO uint32_t MSK10 :1; + __IO uint32_t MSK11 :1; + __IO uint32_t MSK12 :1; + __IO uint32_t MSK13 :1; + __IO uint32_t MSK14 :1; + __IO uint32_t MSK15 :1; + __IO uint32_t MSK16 :1; + __IO uint32_t MSK17 :1; + __IO uint32_t MSK18 :1; + __IO uint32_t MSK19 :1; + __IO uint32_t MSK20 :1; + __IO uint32_t MSK21 :1; + __IO uint32_t MSK22 :1; + __IO uint32_t MSK23 :1; + __IO uint32_t MSK24 :1; + __IO uint32_t MSK25 :1; + __IO uint32_t MSK26 :1; + __IO uint32_t MSK27 :1; + __IO uint32_t MSK28 :1; + __IO uint32_t RESERVED1 :3; + }; + }; +} stc_can_if2msk_field_t; + +typedef struct stc_can_if2arb_field +{ + union { + struct { + __IO uint32_t ID :29; + __IO uint32_t DIR :1; + __IO uint32_t XTD :1; + __IO uint32_t MSGVAL :1; + }; + struct { + __IO uint32_t ID0 :1; + __IO uint32_t ID1 :1; + __IO uint32_t ID2 :1; + __IO uint32_t ID3 :1; + __IO uint32_t ID4 :1; + __IO uint32_t ID5 :1; + __IO uint32_t ID6 :1; + __IO uint32_t ID7 :1; + __IO uint32_t ID8 :1; + __IO uint32_t ID9 :1; + __IO uint32_t ID10 :1; + __IO uint32_t ID11 :1; + __IO uint32_t ID12 :1; + __IO uint32_t ID13 :1; + __IO uint32_t ID14 :1; + __IO uint32_t ID15 :1; + __IO uint32_t ID16 :1; + __IO uint32_t ID17 :1; + __IO uint32_t ID18 :1; + __IO uint32_t ID19 :1; + __IO uint32_t ID20 :1; + __IO uint32_t ID21 :1; + __IO uint32_t ID22 :1; + __IO uint32_t ID23 :1; + __IO uint32_t ID24 :1; + __IO uint32_t ID25 :1; + __IO uint32_t ID26 :1; + __IO uint32_t ID27 :1; + __IO uint32_t ID28 :1; + __IO uint32_t RESERVED0 :3; + }; + }; +} stc_can_if2arb_field_t; + +typedef struct stc_can_if2mctr_field +{ + union { + struct { + __IO uint16_t DLC :4; + __IO uint16_t RESERVED0 :3; + __IO uint16_t EOB :1; + __IO uint16_t TXRQST :1; + __IO uint16_t RMTEN :1; + __IO uint16_t RXIE :1; + __IO uint16_t TXIE :1; + __IO uint16_t UMASK :1; + __IO uint16_t INTPND :1; + __IO uint16_t MSGLST :1; + __IO uint16_t NEWDAT :1; + }; + struct { + __IO uint16_t DLC0 :1; + __IO uint16_t DLC1 :1; + __IO uint16_t DLC2 :1; + __IO uint16_t DLC3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_can_if2mctr_field_t; + +typedef struct stc_can_if2dta_l_field +{ + union { + struct { + __IO uint32_t DATA0 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA3 :8; + }; + struct { + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + }; + }; +} stc_can_if2dta_l_field_t; + +typedef struct stc_can_if2dtb_l_field +{ + union { + struct { + __IO uint32_t DATA4 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA7 :8; + }; + struct { + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + }; + }; +} stc_can_if2dtb_l_field_t; + +typedef struct stc_can_if2dta_b_field +{ + union { + struct { + __IO uint32_t DATA3 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA0 :8; + }; + struct { + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + }; + }; +} stc_can_if2dta_b_field_t; + +typedef struct stc_can_if2dtb_b_field +{ + union { + struct { + __IO uint32_t DATA7 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA4 :8; + }; + struct { + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + }; + }; +} stc_can_if2dtb_b_field_t; + +typedef struct stc_can_treqr_field +{ + __IO uint32_t TXRQST1 :1; + __IO uint32_t TXRQST2 :1; + __IO uint32_t TXRQST3 :1; + __IO uint32_t TXRQST4 :1; + __IO uint32_t TXRQST5 :1; + __IO uint32_t TXRQST6 :1; + __IO uint32_t TXRQST7 :1; + __IO uint32_t TXRQST8 :1; + __IO uint32_t TXRQST9 :1; + __IO uint32_t TXRQST10 :1; + __IO uint32_t TXRQST11 :1; + __IO uint32_t TXRQST12 :1; + __IO uint32_t TXRQST13 :1; + __IO uint32_t TXRQST14 :1; + __IO uint32_t TXRQST15 :1; + __IO uint32_t TXRQST16 :1; + __IO uint32_t TXRQST17 :1; + __IO uint32_t TXRQST18 :1; + __IO uint32_t TXRQST19 :1; + __IO uint32_t TXRQST20 :1; + __IO uint32_t TXRQST21 :1; + __IO uint32_t TXRQST22 :1; + __IO uint32_t TXRQST23 :1; + __IO uint32_t TXRQST24 :1; + __IO uint32_t TXRQST25 :1; + __IO uint32_t TXRQST26 :1; + __IO uint32_t TXRQST27 :1; + __IO uint32_t TXRQST28 :1; + __IO uint32_t TXRQST29 :1; + __IO uint32_t TXRQST30 :1; + __IO uint32_t TXRQST31 :1; + __IO uint32_t TXRQST32 :1; +} stc_can_treqr_field_t; + +typedef struct stc_can_newdt_field +{ + __IO uint32_t NEWDAT1 :1; + __IO uint32_t NEWDAT2 :1; + __IO uint32_t NEWDAT3 :1; + __IO uint32_t NEWDAT4 :1; + __IO uint32_t NEWDAT5 :1; + __IO uint32_t NEWDAT6 :1; + __IO uint32_t NEWDAT7 :1; + __IO uint32_t NEWDAT8 :1; + __IO uint32_t NEWDAT9 :1; + __IO uint32_t NEWDAT10 :1; + __IO uint32_t NEWDAT11 :1; + __IO uint32_t NEWDAT12 :1; + __IO uint32_t NEWDAT13 :1; + __IO uint32_t NEWDAT14 :1; + __IO uint32_t NEWDAT15 :1; + __IO uint32_t NEWDAT16 :1; + __IO uint32_t NEWDAT17 :1; + __IO uint32_t NEWDAT18 :1; + __IO uint32_t NEWDAT19 :1; + __IO uint32_t NEWDAT20 :1; + __IO uint32_t NEWDAT21 :1; + __IO uint32_t NEWDAT22 :1; + __IO uint32_t NEWDAT23 :1; + __IO uint32_t NEWDAT24 :1; + __IO uint32_t NEWDAT25 :1; + __IO uint32_t NEWDAT26 :1; + __IO uint32_t NEWDAT27 :1; + __IO uint32_t NEWDAT28 :1; + __IO uint32_t NEWDAT29 :1; + __IO uint32_t NEWDAT30 :1; + __IO uint32_t NEWDAT31 :1; + __IO uint32_t NEWDAT32 :1; +} stc_can_newdt_field_t; + +typedef struct stc_can_intpnd_field +{ + __IO uint32_t INTPND1 :1; + __IO uint32_t INTPND2 :1; + __IO uint32_t INTPND3 :1; + __IO uint32_t INTPND4 :1; + __IO uint32_t INTPND5 :1; + __IO uint32_t INTPND6 :1; + __IO uint32_t INTPND7 :1; + __IO uint32_t INTPND8 :1; + __IO uint32_t INTPND9 :1; + __IO uint32_t INTPND10 :1; + __IO uint32_t INTPND11 :1; + __IO uint32_t INTPND12 :1; + __IO uint32_t INTPND13 :1; + __IO uint32_t INTPND14 :1; + __IO uint32_t INTPND15 :1; + __IO uint32_t INTPND16 :1; + __IO uint32_t INTPND17 :1; + __IO uint32_t INTPND18 :1; + __IO uint32_t INTPND19 :1; + __IO uint32_t INTPND20 :1; + __IO uint32_t INTPND21 :1; + __IO uint32_t INTPND22 :1; + __IO uint32_t INTPND23 :1; + __IO uint32_t INTPND24 :1; + __IO uint32_t INTPND25 :1; + __IO uint32_t INTPND26 :1; + __IO uint32_t INTPND27 :1; + __IO uint32_t INTPND28 :1; + __IO uint32_t INTPND29 :1; + __IO uint32_t INTPND30 :1; + __IO uint32_t INTPND31 :1; + __IO uint32_t INTPND32 :1; +} stc_can_intpnd_field_t; + +typedef struct stc_can_msgval_field +{ + __IO uint32_t MSGVAL1 :1; + __IO uint32_t MSGVAL2 :1; + __IO uint32_t MSGVAL3 :1; + __IO uint32_t MSGVAL4 :1; + __IO uint32_t MSGVAL5 :1; + __IO uint32_t MSGVAL6 :1; + __IO uint32_t MSGVAL7 :1; + __IO uint32_t MSGVAL8 :1; + __IO uint32_t MSGVAL9 :1; + __IO uint32_t MSGVAL10 :1; + __IO uint32_t MSGVAL11 :1; + __IO uint32_t MSGVAL12 :1; + __IO uint32_t MSGVAL13 :1; + __IO uint32_t MSGVAL14 :1; + __IO uint32_t MSGVAL15 :1; + __IO uint32_t MSGVAL16 :1; + __IO uint32_t MSGVAL17 :1; + __IO uint32_t MSGVAL18 :1; + __IO uint32_t MSGVAL19 :1; + __IO uint32_t MSGVAL20 :1; + __IO uint32_t MSGVAL21 :1; + __IO uint32_t MSGVAL22 :1; + __IO uint32_t MSGVAL23 :1; + __IO uint32_t MSGVAL24 :1; + __IO uint32_t MSGVAL25 :1; + __IO uint32_t MSGVAL26 :1; + __IO uint32_t MSGVAL27 :1; + __IO uint32_t MSGVAL28 :1; + __IO uint32_t MSGVAL29 :1; + __IO uint32_t MSGVAL30 :1; + __IO uint32_t MSGVAL31 :1; + __IO uint32_t MSGVAL32 :1; +} stc_can_msgval_field_t; + +/******************************************************************************* +* CANFD_MODULE +*******************************************************************************/ +typedef struct stc_canfd_crel_field +{ + union { + struct { + __IO uint32_t DAY :8; + __IO uint32_t MON :8; + __IO uint32_t YEAR :4; + __IO uint32_t SUBSTEP :4; + __IO uint32_t STEP :4; + __IO uint32_t REL :4; + }; + struct { + __IO uint32_t DAY0 :1; + __IO uint32_t DAY1 :1; + __IO uint32_t DAY2 :1; + __IO uint32_t DAY3 :1; + __IO uint32_t DAY4 :1; + __IO uint32_t DAY5 :1; + __IO uint32_t DAY6 :1; + __IO uint32_t DAY7 :1; + __IO uint32_t MON0 :1; + __IO uint32_t MON1 :1; + __IO uint32_t MON2 :1; + __IO uint32_t MON3 :1; + __IO uint32_t MON4 :1; + __IO uint32_t MON5 :1; + __IO uint32_t MON6 :1; + __IO uint32_t MON7 :1; + __IO uint32_t YEAR0 :1; + __IO uint32_t YEAR1 :1; + __IO uint32_t YEAR2 :1; + __IO uint32_t YEAR3 :1; + __IO uint32_t SUBSTEP0 :1; + __IO uint32_t SUBSTEP1 :1; + __IO uint32_t SUBSTEP2 :1; + __IO uint32_t SUBSTEP3 :1; + __IO uint32_t STEP0 :1; + __IO uint32_t STEP1 :1; + __IO uint32_t STEP2 :1; + __IO uint32_t STEP3 :1; + __IO uint32_t REL0 :1; + __IO uint32_t REL1 :1; + __IO uint32_t REL2 :1; + __IO uint32_t REL3 :1; + }; + }; +} stc_canfd_crel_field_t; + +typedef struct stc_canfd_endn_field +{ + union { + struct { + __IO uint32_t ETV :32; + }; + struct { + __IO uint32_t ETV0 :1; + __IO uint32_t ETV1 :1; + __IO uint32_t ETV2 :1; + __IO uint32_t ETV3 :1; + __IO uint32_t ETV4 :1; + __IO uint32_t ETV5 :1; + __IO uint32_t ETV6 :1; + __IO uint32_t ETV7 :1; + __IO uint32_t ETV8 :1; + __IO uint32_t ETV9 :1; + __IO uint32_t ETV10 :1; + __IO uint32_t ETV11 :1; + __IO uint32_t ETV12 :1; + __IO uint32_t ETV13 :1; + __IO uint32_t ETV14 :1; + __IO uint32_t ETV15 :1; + __IO uint32_t ETV16 :1; + __IO uint32_t ETV17 :1; + __IO uint32_t ETV18 :1; + __IO uint32_t ETV19 :1; + __IO uint32_t ETV20 :1; + __IO uint32_t ETV21 :1; + __IO uint32_t ETV22 :1; + __IO uint32_t ETV23 :1; + __IO uint32_t ETV24 :1; + __IO uint32_t ETV25 :1; + __IO uint32_t ETV26 :1; + __IO uint32_t ETV27 :1; + __IO uint32_t ETV28 :1; + __IO uint32_t ETV29 :1; + __IO uint32_t ETV30 :1; + __IO uint32_t ETV31 :1; + }; + }; +} stc_canfd_endn_field_t; + +typedef struct stc_canfd_fbtp_field +{ + union { + struct { + __IO uint32_t FSJW :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FTSEG2 :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t FTSEG1 :4; + __IO uint32_t RESERVED4 :4; + __IO uint32_t FBRP :5; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TDC :1; + __IO uint32_t TDCO :5; + __IO uint32_t RESERVED8 :3; + }; + struct { + __IO uint32_t FSJW0 :1; + __IO uint32_t FSJW1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t FTSEG20 :1; + __IO uint32_t FTSEG21 :1; + __IO uint32_t FTSEG22 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t FTSEG10 :1; + __IO uint32_t FTSEG11 :1; + __IO uint32_t FTSEG12 :1; + __IO uint32_t FTSEG13 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t FBRP0 :1; + __IO uint32_t FBRP1 :1; + __IO uint32_t FBRP2 :1; + __IO uint32_t FBRP3 :1; + __IO uint32_t FBRP4 :1; + __IO uint32_t RESERVED7 :3; + __IO uint32_t TDCO0 :1; + __IO uint32_t TDCO1 :1; + __IO uint32_t TDCO2 :1; + __IO uint32_t TDCO3 :1; + __IO uint32_t TDCO4 :1; + __IO uint32_t RESERVED9 :3; + }; + }; +} stc_canfd_fbtp_field_t; + +typedef struct stc_canfd_test_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t LBCK :1; + __IO uint32_t TX :2; + __IO uint32_t RX :1; + __IO uint32_t TDCV :6; + __IO uint32_t RESERVED3 :18; + }; + struct { + __IO uint32_t RESERVED1 :5; + __IO uint32_t TX0 :1; + __IO uint32_t TX1 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t TDCV0 :1; + __IO uint32_t TDCV1 :1; + __IO uint32_t TDCV2 :1; + __IO uint32_t TDCV3 :1; + __IO uint32_t TDCV4 :1; + __IO uint32_t TDCV5 :1; + __IO uint32_t RESERVED4 :18; + }; + }; +} stc_canfd_test_field_t; + +typedef struct stc_canfd_rwd_field +{ + union { + struct { + __IO uint32_t WDC :8; + __IO uint32_t WDV :8; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t WDC0 :1; + __IO uint32_t WDC1 :1; + __IO uint32_t WDC2 :1; + __IO uint32_t WDC3 :1; + __IO uint32_t WDC4 :1; + __IO uint32_t WDC5 :1; + __IO uint32_t WDC6 :1; + __IO uint32_t WDC7 :1; + __IO uint32_t WDV0 :1; + __IO uint32_t WDV1 :1; + __IO uint32_t WDV2 :1; + __IO uint32_t WDV3 :1; + __IO uint32_t WDV4 :1; + __IO uint32_t WDV5 :1; + __IO uint32_t WDV6 :1; + __IO uint32_t WDV7 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_rwd_field_t; + +typedef struct stc_canfd_cccr_field +{ + union { + struct { + __IO uint32_t INIT :1; + __IO uint32_t CCE :1; + __IO uint32_t ASM :1; + __IO uint32_t CSA :1; + __IO uint32_t CSR :1; + __IO uint32_t MON :1; + __IO uint32_t DAR :1; + __IO uint32_t TEST :1; + __IO uint32_t CME :2; + __IO uint32_t CMR :2; + __IO uint32_t FDO :1; + __IO uint32_t FDBS :1; + __IO uint32_t TXP :1; + __IO uint32_t RESERVED1 :17; + }; + struct { + __IO uint32_t RESERVED0 :8; + __IO uint32_t CME0 :1; + __IO uint32_t CME1 :1; + __IO uint32_t CMR0 :1; + __IO uint32_t CMR1 :1; + __IO uint32_t RESERVED2 :20; + }; + }; +} stc_canfd_cccr_field_t; + +typedef struct stc_canfd_btp_field +{ + union { + struct { + __IO uint32_t SJW :4; + __IO uint32_t TSEG2 :4; + __IO uint32_t TSEG1 :6; + __IO uint32_t RESERVED0 :2; + __IO uint32_t BRP :10; + __IO uint32_t RESERVED2 :6; + }; + struct { + __IO uint32_t SJW0 :1; + __IO uint32_t SJW1 :1; + __IO uint32_t SJW2 :1; + __IO uint32_t SJW3 :1; + __IO uint32_t TSEG20 :1; + __IO uint32_t TSEG21 :1; + __IO uint32_t TSEG22 :1; + __IO uint32_t TSEG23 :1; + __IO uint32_t TSEG10 :1; + __IO uint32_t TSEG11 :1; + __IO uint32_t TSEG12 :1; + __IO uint32_t TSEG13 :1; + __IO uint32_t TSEG14 :1; + __IO uint32_t TSEG15 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t BRP0 :1; + __IO uint32_t BRP1 :1; + __IO uint32_t BRP2 :1; + __IO uint32_t BRP3 :1; + __IO uint32_t BRP4 :1; + __IO uint32_t BRP5 :1; + __IO uint32_t BRP6 :1; + __IO uint32_t BRP7 :1; + __IO uint32_t BRP8 :1; + __IO uint32_t BRP9 :1; + __IO uint32_t RESERVED3 :6; + }; + }; +} stc_canfd_btp_field_t; + +typedef struct stc_canfd_tscc_field +{ + union { + struct { + __IO uint32_t TSS :2; + __IO uint32_t RESERVED0 :14; + __IO uint32_t TCP :4; + __IO uint32_t RESERVED2 :12; + }; + struct { + __IO uint32_t TSS0 :1; + __IO uint32_t TSS1 :1; + __IO uint32_t RESERVED1 :14; + __IO uint32_t TCP0 :1; + __IO uint32_t TCP1 :1; + __IO uint32_t TCP2 :1; + __IO uint32_t TCP3 :1; + __IO uint32_t RESERVED3 :12; + }; + }; +} stc_canfd_tscc_field_t; + +typedef struct stc_canfd_tscv_field +{ + union { + struct { + __IO uint32_t TSC :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t TSC0 :1; + __IO uint32_t TSC1 :1; + __IO uint32_t TSC2 :1; + __IO uint32_t TSC3 :1; + __IO uint32_t TSC4 :1; + __IO uint32_t TSC5 :1; + __IO uint32_t TSC6 :1; + __IO uint32_t TSC7 :1; + __IO uint32_t TSC8 :1; + __IO uint32_t TSC9 :1; + __IO uint32_t TSC10 :1; + __IO uint32_t TSC11 :1; + __IO uint32_t TSC12 :1; + __IO uint32_t TSC13 :1; + __IO uint32_t TSC14 :1; + __IO uint32_t TSC15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_tscv_field_t; + +typedef struct stc_canfd_tocc_field +{ + union { + struct { + __IO uint32_t ETOC :1; + __IO uint32_t TOS :2; + __IO uint32_t RESERVED1 :13; + __IO uint32_t TOP :16; + }; + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t TOS0 :1; + __IO uint32_t TOS1 :1; + __IO uint32_t RESERVED2 :13; + __IO uint32_t TOP0 :1; + __IO uint32_t TOP1 :1; + __IO uint32_t TOP2 :1; + __IO uint32_t TOP3 :1; + __IO uint32_t TOP4 :1; + __IO uint32_t TOP5 :1; + __IO uint32_t TOP6 :1; + __IO uint32_t TOP7 :1; + __IO uint32_t TOP8 :1; + __IO uint32_t TOP9 :1; + __IO uint32_t TOP10 :1; + __IO uint32_t TOP11 :1; + __IO uint32_t TOP12 :1; + __IO uint32_t TOP13 :1; + __IO uint32_t TOP14 :1; + __IO uint32_t TOP15 :1; + }; + }; +} stc_canfd_tocc_field_t; + +typedef struct stc_canfd_tocv_field +{ + union { + struct { + __IO uint32_t TOC :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t TOC0 :1; + __IO uint32_t TOC1 :1; + __IO uint32_t TOC2 :1; + __IO uint32_t TOC3 :1; + __IO uint32_t TOC4 :1; + __IO uint32_t TOC5 :1; + __IO uint32_t TOC6 :1; + __IO uint32_t TOC7 :1; + __IO uint32_t TOC8 :1; + __IO uint32_t TOC9 :1; + __IO uint32_t TOC10 :1; + __IO uint32_t TOC11 :1; + __IO uint32_t TOC12 :1; + __IO uint32_t TOC13 :1; + __IO uint32_t TOC14 :1; + __IO uint32_t TOC15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_tocv_field_t; + +typedef struct stc_canfd_ecr_field +{ + union { + struct { + __IO uint32_t TEC :8; + __IO uint32_t REC :7; + __IO uint32_t RP :1; + __IO uint32_t CEL :8; + __IO uint32_t RESERVED1 :8; + }; + struct { + __IO uint32_t TEC0 :1; + __IO uint32_t TEC1 :1; + __IO uint32_t TEC2 :1; + __IO uint32_t TEC3 :1; + __IO uint32_t TEC4 :1; + __IO uint32_t TEC5 :1; + __IO uint32_t TEC6 :1; + __IO uint32_t TEC7 :1; + __IO uint32_t REC0 :1; + __IO uint32_t REC1 :1; + __IO uint32_t REC2 :1; + __IO uint32_t REC3 :1; + __IO uint32_t REC4 :1; + __IO uint32_t REC5 :1; + __IO uint32_t REC6 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t CEL0 :1; + __IO uint32_t CEL1 :1; + __IO uint32_t CEL2 :1; + __IO uint32_t CEL3 :1; + __IO uint32_t CEL4 :1; + __IO uint32_t CEL5 :1; + __IO uint32_t CEL6 :1; + __IO uint32_t CEL7 :1; + __IO uint32_t RESERVED2 :8; + }; + }; +} stc_canfd_ecr_field_t; + +typedef struct stc_canfd_psr_field +{ + union { + struct { + __IO uint32_t LEC :3; + __IO uint32_t ACT :2; + __IO uint32_t EP :1; + __IO uint32_t EW :1; + __IO uint32_t BO :1; + __IO uint32_t FLEC :3; + __IO uint32_t RESI :1; + __IO uint32_t RBRS :1; + __IO uint32_t REDL :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t LEC0 :1; + __IO uint32_t LEC1 :1; + __IO uint32_t LEC2 :1; + __IO uint32_t ACT0 :1; + __IO uint32_t ACT1 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t FLEC0 :1; + __IO uint32_t FLEC1 :1; + __IO uint32_t FLEC2 :1; + __IO uint32_t RESERVED2 :21; + }; + }; +} stc_canfd_psr_field_t; + +typedef struct stc_canfd_ir_field +{ + __IO uint32_t RF0N :1; + __IO uint32_t RF0W :1; + __IO uint32_t RF0F :1; + __IO uint32_t RF0L :1; + __IO uint32_t RF1N :1; + __IO uint32_t RF1W :1; + __IO uint32_t RF1F :1; + __IO uint32_t RF1L :1; + __IO uint32_t HPM :1; + __IO uint32_t TC :1; + __IO uint32_t TCF :1; + __IO uint32_t TFE :1; + __IO uint32_t TEFN :1; + __IO uint32_t TEFW :1; + __IO uint32_t TEFF :1; + __IO uint32_t TEFL :1; + __IO uint32_t TSW :1; + __IO uint32_t MRAF :1; + __IO uint32_t TOO :1; + __IO uint32_t DRX :1; + __IO uint32_t BEC :1; + __IO uint32_t BEU :1; + __IO uint32_t ELO :1; + __IO uint32_t EP :1; + __IO uint32_t EW :1; + __IO uint32_t BO :1; + __IO uint32_t WDI :1; + __IO uint32_t CRCE :1; + __IO uint32_t BE :1; + __IO uint32_t ACKE :1; + __IO uint32_t FOE :1; + __IO uint32_t STE :1; +} stc_canfd_ir_field_t; + +typedef struct stc_canfd_ie_field +{ + __IO uint32_t RF0NE :1; + __IO uint32_t RF0WE :1; + __IO uint32_t RF0FE :1; + __IO uint32_t RF0LE :1; + __IO uint32_t RF1NE :1; + __IO uint32_t RF1WE :1; + __IO uint32_t RF1FE :1; + __IO uint32_t RF1LE :1; + __IO uint32_t HPME :1; + __IO uint32_t TCE :1; + __IO uint32_t TCFE :1; + __IO uint32_t TFEE :1; + __IO uint32_t TEFNE :1; + __IO uint32_t TEFWE :1; + __IO uint32_t TEFFE :1; + __IO uint32_t TEFLE :1; + __IO uint32_t TSWE :1; + __IO uint32_t MRAFE :1; + __IO uint32_t TOOE :1; + __IO uint32_t DRXE :1; + __IO uint32_t BECE :1; + __IO uint32_t BEUE :1; + __IO uint32_t ELOE :1; + __IO uint32_t EPE :1; + __IO uint32_t EWE :1; + __IO uint32_t BOE :1; + __IO uint32_t WDIE :1; + __IO uint32_t CRCEE :1; + __IO uint32_t BEE :1; + __IO uint32_t ACKEE :1; + __IO uint32_t FOEE :1; + __IO uint32_t STEE :1; +} stc_canfd_ie_field_t; + +typedef struct stc_canfd_ils_field +{ + __IO uint32_t RF0NL :1; + __IO uint32_t RF0WL :1; + __IO uint32_t RF0FL :1; + __IO uint32_t RF0LL :1; + __IO uint32_t RF1NL :1; + __IO uint32_t RF1WL :1; + __IO uint32_t RF1FL :1; + __IO uint32_t RF1LL :1; + __IO uint32_t HPML :1; + __IO uint32_t TCL :1; + __IO uint32_t TCFL :1; + __IO uint32_t TFEL :1; + __IO uint32_t TEFNL :1; + __IO uint32_t TEFWL :1; + __IO uint32_t TEFFL :1; + __IO uint32_t TEFLL :1; + __IO uint32_t TSWL :1; + __IO uint32_t MRAFL :1; + __IO uint32_t TOOL :1; + __IO uint32_t DRXL :1; + __IO uint32_t BECL :1; + __IO uint32_t BEUL :1; + __IO uint32_t ELOL :1; + __IO uint32_t EPL :1; + __IO uint32_t EWL :1; + __IO uint32_t BOL :1; + __IO uint32_t WDIL :1; + __IO uint32_t CRCEL :1; + __IO uint32_t BEL :1; + __IO uint32_t ACKEL :1; + __IO uint32_t FOEL :1; + __IO uint32_t STEL :1; +} stc_canfd_ils_field_t; + +typedef struct stc_canfd_ile_field +{ + __IO uint32_t EINT0 :1; + __IO uint32_t EINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_canfd_ile_field_t; + +typedef struct stc_canfd_gfc_field +{ + union { + struct { + __IO uint32_t RRFE :1; + __IO uint32_t RRFS :1; + __IO uint32_t ANFE :2; + __IO uint32_t ANFS :2; + __IO uint32_t RESERVED1 :26; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t ANFE0 :1; + __IO uint32_t ANFE1 :1; + __IO uint32_t ANFS0 :1; + __IO uint32_t ANFS1 :1; + __IO uint32_t RESERVED2 :26; + }; + }; +} stc_canfd_gfc_field_t; + +typedef struct stc_canfd_sidfc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t FLSSA :14; + __IO uint32_t LSS :8; + __IO uint32_t RESERVED2 :8; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t FLSSA0 :1; + __IO uint32_t FLSSA1 :1; + __IO uint32_t FLSSA2 :1; + __IO uint32_t FLSSA3 :1; + __IO uint32_t FLSSA4 :1; + __IO uint32_t FLSSA5 :1; + __IO uint32_t FLSSA6 :1; + __IO uint32_t FLSSA7 :1; + __IO uint32_t FLSSA8 :1; + __IO uint32_t FLSSA9 :1; + __IO uint32_t FLSSA10 :1; + __IO uint32_t FLSSA11 :1; + __IO uint32_t FLSSA12 :1; + __IO uint32_t FLSSA13 :1; + __IO uint32_t LSS0 :1; + __IO uint32_t LSS1 :1; + __IO uint32_t LSS2 :1; + __IO uint32_t LSS3 :1; + __IO uint32_t LSS4 :1; + __IO uint32_t LSS5 :1; + __IO uint32_t LSS6 :1; + __IO uint32_t LSS7 :1; + __IO uint32_t RESERVED3 :8; + }; + }; +} stc_canfd_sidfc_field_t; + +typedef struct stc_canfd_xidfc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t FLESA :14; + __IO uint32_t LSE :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t FLESA0 :1; + __IO uint32_t FLESA1 :1; + __IO uint32_t FLESA2 :1; + __IO uint32_t FLESA3 :1; + __IO uint32_t FLESA4 :1; + __IO uint32_t FLESA5 :1; + __IO uint32_t FLESA6 :1; + __IO uint32_t FLESA7 :1; + __IO uint32_t FLESA8 :1; + __IO uint32_t FLESA9 :1; + __IO uint32_t FLESA10 :1; + __IO uint32_t FLESA11 :1; + __IO uint32_t FLESA12 :1; + __IO uint32_t FLESA13 :1; + __IO uint32_t LSE0 :1; + __IO uint32_t LSE1 :1; + __IO uint32_t LSE2 :1; + __IO uint32_t LSE3 :1; + __IO uint32_t LSE4 :1; + __IO uint32_t LSE5 :1; + __IO uint32_t LSE6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_canfd_xidfc_field_t; + +typedef struct stc_canfd_xidam_field +{ + union { + struct { + __IO uint32_t EIDM :29; + __IO uint32_t RESERVED0 :3; + }; + struct { + __IO uint32_t EIDM0 :1; + __IO uint32_t EIDM1 :1; + __IO uint32_t EIDM2 :1; + __IO uint32_t EIDM3 :1; + __IO uint32_t EIDM4 :1; + __IO uint32_t EIDM5 :1; + __IO uint32_t EIDM6 :1; + __IO uint32_t EIDM7 :1; + __IO uint32_t EIDM8 :1; + __IO uint32_t EIDM9 :1; + __IO uint32_t EIDM10 :1; + __IO uint32_t EIDM11 :1; + __IO uint32_t EIDM12 :1; + __IO uint32_t EIDM13 :1; + __IO uint32_t EIDM14 :1; + __IO uint32_t EIDM15 :1; + __IO uint32_t EIDM16 :1; + __IO uint32_t EIDM17 :1; + __IO uint32_t EIDM18 :1; + __IO uint32_t EIDM19 :1; + __IO uint32_t EIDM20 :1; + __IO uint32_t EIDM21 :1; + __IO uint32_t EIDM22 :1; + __IO uint32_t EIDM23 :1; + __IO uint32_t EIDM24 :1; + __IO uint32_t EIDM25 :1; + __IO uint32_t EIDM26 :1; + __IO uint32_t EIDM27 :1; + __IO uint32_t EIDM28 :1; + __IO uint32_t RESERVED1 :3; + }; + }; +} stc_canfd_xidam_field_t; + +typedef struct stc_canfd_hpms_field +{ + union { + struct { + __IO uint32_t BIDX :6; + __IO uint32_t MSI :2; + __IO uint32_t FIDX :7; + __IO uint32_t FLST :1; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t BIDX0 :1; + __IO uint32_t BIDX1 :1; + __IO uint32_t BIDX2 :1; + __IO uint32_t BIDX3 :1; + __IO uint32_t BIDX4 :1; + __IO uint32_t BIDX5 :1; + __IO uint32_t MSI0 :1; + __IO uint32_t MSI1 :1; + __IO uint32_t FIDX0 :1; + __IO uint32_t FIDX1 :1; + __IO uint32_t FIDX2 :1; + __IO uint32_t FIDX3 :1; + __IO uint32_t FIDX4 :1; + __IO uint32_t FIDX5 :1; + __IO uint32_t FIDX6 :1; + __IO uint32_t RESERVED1 :17; + }; + }; +} stc_canfd_hpms_field_t; + +typedef struct stc_canfd_ndat1_field +{ + __IO uint32_t ND0 :1; + __IO uint32_t ND1 :1; + __IO uint32_t ND2 :1; + __IO uint32_t ND3 :1; + __IO uint32_t ND4 :1; + __IO uint32_t ND5 :1; + __IO uint32_t ND6 :1; + __IO uint32_t ND7 :1; + __IO uint32_t ND8 :1; + __IO uint32_t ND9 :1; + __IO uint32_t ND10 :1; + __IO uint32_t ND11 :1; + __IO uint32_t ND12 :1; + __IO uint32_t ND13 :1; + __IO uint32_t ND14 :1; + __IO uint32_t ND15 :1; + __IO uint32_t ND16 :1; + __IO uint32_t ND17 :1; + __IO uint32_t ND18 :1; + __IO uint32_t ND19 :1; + __IO uint32_t ND20 :1; + __IO uint32_t ND21 :1; + __IO uint32_t ND22 :1; + __IO uint32_t ND23 :1; + __IO uint32_t ND24 :1; + __IO uint32_t ND25 :1; + __IO uint32_t ND26 :1; + __IO uint32_t ND27 :1; + __IO uint32_t ND28 :1; + __IO uint32_t ND29 :1; + __IO uint32_t ND30 :1; + __IO uint32_t ND31 :1; +} stc_canfd_ndat1_field_t; + +typedef struct stc_canfd_ndat2_field +{ + __IO uint32_t ND32 :1; + __IO uint32_t ND33 :1; + __IO uint32_t ND34 :1; + __IO uint32_t ND35 :1; + __IO uint32_t ND36 :1; + __IO uint32_t ND37 :1; + __IO uint32_t ND38 :1; + __IO uint32_t ND39 :1; + __IO uint32_t ND40 :1; + __IO uint32_t ND41 :1; + __IO uint32_t ND42 :1; + __IO uint32_t ND43 :1; + __IO uint32_t ND44 :1; + __IO uint32_t ND45 :1; + __IO uint32_t ND46 :1; + __IO uint32_t ND47 :1; + __IO uint32_t ND48 :1; + __IO uint32_t ND49 :1; + __IO uint32_t ND50 :1; + __IO uint32_t ND51 :1; + __IO uint32_t ND52 :1; + __IO uint32_t ND53 :1; + __IO uint32_t ND54 :1; + __IO uint32_t ND55 :1; + __IO uint32_t ND56 :1; + __IO uint32_t ND57 :1; + __IO uint32_t ND58 :1; + __IO uint32_t ND59 :1; + __IO uint32_t ND60 :1; + __IO uint32_t ND61 :1; + __IO uint32_t ND62 :1; + __IO uint32_t ND63 :1; +} stc_canfd_ndat2_field_t; + +typedef struct stc_canfd_rxf0c_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t F0SA :14; + __IO uint32_t F0S :7; + __IO uint32_t RESERVED2 :1; + __IO uint32_t F0WM :7; + __IO uint32_t F0OM :1; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t F0SA0 :1; + __IO uint32_t F0SA1 :1; + __IO uint32_t F0SA2 :1; + __IO uint32_t F0SA3 :1; + __IO uint32_t F0SA4 :1; + __IO uint32_t F0SA5 :1; + __IO uint32_t F0SA6 :1; + __IO uint32_t F0SA7 :1; + __IO uint32_t F0SA8 :1; + __IO uint32_t F0SA9 :1; + __IO uint32_t F0SA10 :1; + __IO uint32_t F0SA11 :1; + __IO uint32_t F0SA12 :1; + __IO uint32_t F0SA13 :1; + __IO uint32_t F0S0 :1; + __IO uint32_t F0S1 :1; + __IO uint32_t F0S2 :1; + __IO uint32_t F0S3 :1; + __IO uint32_t F0S4 :1; + __IO uint32_t F0S5 :1; + __IO uint32_t F0S6 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t F0WM0 :1; + __IO uint32_t F0WM1 :1; + __IO uint32_t F0WM2 :1; + __IO uint32_t F0WM3 :1; + __IO uint32_t F0WM4 :1; + __IO uint32_t F0WM5 :1; + __IO uint32_t F0WM6 :1; + __IO uint32_t RESERVED4 :1; + }; + }; +} stc_canfd_rxf0c_field_t; + +typedef struct stc_canfd_rxf0s_field +{ + union { + struct { + __IO uint32_t F0FL :7; + __IO uint32_t RESERVED0 :1; + __IO uint32_t F0GI :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t F0PI :6; + __IO uint32_t RESERVED4 :2; + __IO uint32_t F0F :1; + __IO uint32_t RF0L :1; + __IO uint32_t RESERVED5 :6; + }; + struct { + __IO uint32_t F0FL0 :1; + __IO uint32_t F0FL1 :1; + __IO uint32_t F0FL2 :1; + __IO uint32_t F0FL3 :1; + __IO uint32_t F0FL4 :1; + __IO uint32_t F0FL5 :1; + __IO uint32_t F0FL6 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t F0GI0 :1; + __IO uint32_t F0GI1 :1; + __IO uint32_t F0GI2 :1; + __IO uint32_t F0GI3 :1; + __IO uint32_t F0GI4 :1; + __IO uint32_t F0GI5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t F0PI0 :1; + __IO uint32_t F0PI1 :1; + __IO uint32_t F0PI2 :1; + __IO uint32_t F0PI3 :1; + __IO uint32_t F0PI4 :1; + __IO uint32_t F0PI5 :1; + __IO uint32_t RESERVED6 :10; + }; + }; +} stc_canfd_rxf0s_field_t; + +typedef struct stc_canfd_rxf0a_field +{ + union { + struct { + __IO uint32_t F0AI :6; + __IO uint32_t RESERVED0 :26; + }; + struct { + __IO uint32_t F0AI0 :1; + __IO uint32_t F0AI1 :1; + __IO uint32_t F0AI2 :1; + __IO uint32_t F0AI3 :1; + __IO uint32_t F0AI4 :1; + __IO uint32_t F0AI5 :1; + __IO uint32_t RESERVED1 :26; + }; + }; +} stc_canfd_rxf0a_field_t; + +typedef struct stc_canfd_rxbc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t RBSA :14; + __IO uint32_t RESERVED2 :16; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t RBSA0 :1; + __IO uint32_t RBSA1 :1; + __IO uint32_t RBSA2 :1; + __IO uint32_t RBSA3 :1; + __IO uint32_t RBSA4 :1; + __IO uint32_t RBSA5 :1; + __IO uint32_t RBSA6 :1; + __IO uint32_t RBSA7 :1; + __IO uint32_t RBSA8 :1; + __IO uint32_t RBSA9 :1; + __IO uint32_t RBSA10 :1; + __IO uint32_t RBSA11 :1; + __IO uint32_t RBSA12 :1; + __IO uint32_t RBSA13 :1; + __IO uint32_t RESERVED3 :16; + }; + }; +} stc_canfd_rxbc_field_t; + +typedef struct stc_canfd_rxf1c_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t F1SA :14; + __IO uint32_t F1S :7; + __IO uint32_t RESERVED2 :1; + __IO uint32_t F1WM :7; + __IO uint32_t F1OM :1; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t F1SA0 :1; + __IO uint32_t F1SA1 :1; + __IO uint32_t F1SA2 :1; + __IO uint32_t F1SA3 :1; + __IO uint32_t F1SA4 :1; + __IO uint32_t F1SA5 :1; + __IO uint32_t F1SA6 :1; + __IO uint32_t F1SA7 :1; + __IO uint32_t F1SA8 :1; + __IO uint32_t F1SA9 :1; + __IO uint32_t F1SA10 :1; + __IO uint32_t F1SA11 :1; + __IO uint32_t F1SA12 :1; + __IO uint32_t F1SA13 :1; + __IO uint32_t F1S0 :1; + __IO uint32_t F1S1 :1; + __IO uint32_t F1S2 :1; + __IO uint32_t F1S3 :1; + __IO uint32_t F1S4 :1; + __IO uint32_t F1S5 :1; + __IO uint32_t F1S6 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t F1WM0 :1; + __IO uint32_t F1WM1 :1; + __IO uint32_t F1WM2 :1; + __IO uint32_t F1WM3 :1; + __IO uint32_t F1WM4 :1; + __IO uint32_t F1WM5 :1; + __IO uint32_t F1WM6 :1; + __IO uint32_t RESERVED4 :1; + }; + }; +} stc_canfd_rxf1c_field_t; + +typedef struct stc_canfd_rxf1s_field +{ + union { + struct { + __IO uint32_t F1FL :7; + __IO uint32_t RESERVED0 :1; + __IO uint32_t F1GI :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t F1PI :6; + __IO uint32_t RESERVED4 :2; + __IO uint32_t F1F :1; + __IO uint32_t RF1L :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t DMS :2; + }; + struct { + __IO uint32_t F1FL0 :1; + __IO uint32_t F1FL1 :1; + __IO uint32_t F1FL2 :1; + __IO uint32_t F1FL3 :1; + __IO uint32_t F1FL4 :1; + __IO uint32_t F1FL5 :1; + __IO uint32_t F1FL6 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t F1GI0 :1; + __IO uint32_t F1GI1 :1; + __IO uint32_t F1GI2 :1; + __IO uint32_t F1GI3 :1; + __IO uint32_t F1GI4 :1; + __IO uint32_t F1GI5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t F1PI0 :1; + __IO uint32_t F1PI1 :1; + __IO uint32_t F1PI2 :1; + __IO uint32_t F1PI3 :1; + __IO uint32_t F1PI4 :1; + __IO uint32_t F1PI5 :1; + __IO uint32_t RESERVED6 :8; + __IO uint32_t DMS0 :1; + __IO uint32_t DMS1 :1; + }; + }; +} stc_canfd_rxf1s_field_t; + +typedef struct stc_canfd_rxf1a_field +{ + union { + struct { + __IO uint32_t F1AI :6; + __IO uint32_t RESERVED0 :26; + }; + struct { + __IO uint32_t F1AI0 :1; + __IO uint32_t F1AI1 :1; + __IO uint32_t F1AI2 :1; + __IO uint32_t F1AI3 :1; + __IO uint32_t F1AI4 :1; + __IO uint32_t F1AI5 :1; + __IO uint32_t RESERVED1 :26; + }; + }; +} stc_canfd_rxf1a_field_t; + +typedef struct stc_canfd_rxesc_field +{ + union { + struct { + __IO uint32_t F0DS :3; + __IO uint32_t RESERVED0 :1; + __IO uint32_t F1DS :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t RBDS :3; + __IO uint32_t RESERVED4 :21; + }; + struct { + __IO uint32_t F0DS0 :1; + __IO uint32_t F0DS1 :1; + __IO uint32_t F0DS2 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t F1DS0 :1; + __IO uint32_t F1DS1 :1; + __IO uint32_t F1DS2 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t RBDS0 :1; + __IO uint32_t RBDS1 :1; + __IO uint32_t RBDS2 :1; + __IO uint32_t RESERVED5 :21; + }; + }; +} stc_canfd_rxesc_field_t; + +typedef struct stc_canfd_txbc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TBSA :14; + __IO uint32_t NDTB :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TFQS :6; + __IO uint32_t TFQM :1; + __IO uint32_t RESERVED4 :1; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TBSA0 :1; + __IO uint32_t TBSA1 :1; + __IO uint32_t TBSA2 :1; + __IO uint32_t TBSA3 :1; + __IO uint32_t TBSA4 :1; + __IO uint32_t TBSA5 :1; + __IO uint32_t TBSA6 :1; + __IO uint32_t TBSA7 :1; + __IO uint32_t TBSA8 :1; + __IO uint32_t TBSA9 :1; + __IO uint32_t TBSA10 :1; + __IO uint32_t TBSA11 :1; + __IO uint32_t TBSA12 :1; + __IO uint32_t TBSA13 :1; + __IO uint32_t NDTB0 :1; + __IO uint32_t NDTB1 :1; + __IO uint32_t NDTB2 :1; + __IO uint32_t NDTB3 :1; + __IO uint32_t NDTB4 :1; + __IO uint32_t NDTB5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TFQS0 :1; + __IO uint32_t TFQS1 :1; + __IO uint32_t TFQS2 :1; + __IO uint32_t TFQS3 :1; + __IO uint32_t TFQS4 :1; + __IO uint32_t TFQS5 :1; + __IO uint32_t RESERVED5 :2; + }; + }; +} stc_canfd_txbc_field_t; + +typedef struct stc_canfd_txfqs_field +{ + union { + struct { + __IO uint32_t TFFL :6; + __IO uint32_t RESERVED0 :2; + __IO uint32_t TFGI :5; + __IO uint32_t RESERVED2 :3; + __IO uint32_t TFQPI :5; + __IO uint32_t TFQF :1; + __IO uint32_t RESERVED4 :10; + }; + struct { + __IO uint32_t TFFL0 :1; + __IO uint32_t TFFL1 :1; + __IO uint32_t TFFL2 :1; + __IO uint32_t TFFL3 :1; + __IO uint32_t TFFL4 :1; + __IO uint32_t TFFL5 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t TFGI0 :1; + __IO uint32_t TFGI1 :1; + __IO uint32_t TFGI2 :1; + __IO uint32_t TFGI3 :1; + __IO uint32_t TFGI4 :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t TFQPI0 :1; + __IO uint32_t TFQPI1 :1; + __IO uint32_t TFQPI2 :1; + __IO uint32_t TFQPI3 :1; + __IO uint32_t TFQPI4 :1; + __IO uint32_t RESERVED5 :11; + }; + }; +} stc_canfd_txfqs_field_t; + +typedef struct stc_canfd_txesc_field +{ + union { + struct { + __IO uint32_t TBDS :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t TBDS0 :1; + __IO uint32_t TBDS1 :1; + __IO uint32_t TBDS2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_canfd_txesc_field_t; + +typedef struct stc_canfd_txbrp_field +{ + __IO uint32_t TRP0 :1; + __IO uint32_t TRP1 :1; + __IO uint32_t TRP2 :1; + __IO uint32_t TRP3 :1; + __IO uint32_t TRP4 :1; + __IO uint32_t TRP5 :1; + __IO uint32_t TRP6 :1; + __IO uint32_t TRP7 :1; + __IO uint32_t TRP8 :1; + __IO uint32_t TRP9 :1; + __IO uint32_t TRP10 :1; + __IO uint32_t TRP11 :1; + __IO uint32_t TRP12 :1; + __IO uint32_t TRP13 :1; + __IO uint32_t TRP14 :1; + __IO uint32_t TRP15 :1; + __IO uint32_t TRP16 :1; + __IO uint32_t TRP17 :1; + __IO uint32_t TRP18 :1; + __IO uint32_t TRP19 :1; + __IO uint32_t TRP20 :1; + __IO uint32_t TRP21 :1; + __IO uint32_t TRP22 :1; + __IO uint32_t TRP23 :1; + __IO uint32_t TRP24 :1; + __IO uint32_t TRP25 :1; + __IO uint32_t TRP26 :1; + __IO uint32_t TRP27 :1; + __IO uint32_t TRP28 :1; + __IO uint32_t TRP29 :1; + __IO uint32_t TRP30 :1; + __IO uint32_t TRP31 :1; +} stc_canfd_txbrp_field_t; + +typedef struct stc_canfd_txbar_field +{ + __IO uint32_t AR0 :1; + __IO uint32_t AR1 :1; + __IO uint32_t AR2 :1; + __IO uint32_t AR3 :1; + __IO uint32_t AR4 :1; + __IO uint32_t AR5 :1; + __IO uint32_t AR6 :1; + __IO uint32_t AR7 :1; + __IO uint32_t AR8 :1; + __IO uint32_t AR9 :1; + __IO uint32_t AR10 :1; + __IO uint32_t AR11 :1; + __IO uint32_t AR12 :1; + __IO uint32_t AR13 :1; + __IO uint32_t AR14 :1; + __IO uint32_t AR15 :1; + __IO uint32_t AR16 :1; + __IO uint32_t AR17 :1; + __IO uint32_t AR18 :1; + __IO uint32_t AR19 :1; + __IO uint32_t AR20 :1; + __IO uint32_t AR21 :1; + __IO uint32_t AR22 :1; + __IO uint32_t AR23 :1; + __IO uint32_t AR24 :1; + __IO uint32_t AR25 :1; + __IO uint32_t AR26 :1; + __IO uint32_t AR27 :1; + __IO uint32_t AR28 :1; + __IO uint32_t AR29 :1; + __IO uint32_t AR30 :1; + __IO uint32_t AR31 :1; +} stc_canfd_txbar_field_t; + +typedef struct stc_canfd_txbcr_field +{ + __IO uint32_t CR0 :1; + __IO uint32_t CR1 :1; + __IO uint32_t CR2 :1; + __IO uint32_t CR3 :1; + __IO uint32_t CR4 :1; + __IO uint32_t CR5 :1; + __IO uint32_t CR6 :1; + __IO uint32_t CR7 :1; + __IO uint32_t CR8 :1; + __IO uint32_t CR9 :1; + __IO uint32_t CR10 :1; + __IO uint32_t CR11 :1; + __IO uint32_t CR12 :1; + __IO uint32_t CR13 :1; + __IO uint32_t CR14 :1; + __IO uint32_t CR15 :1; + __IO uint32_t CR16 :1; + __IO uint32_t CR17 :1; + __IO uint32_t CR18 :1; + __IO uint32_t CR19 :1; + __IO uint32_t CR20 :1; + __IO uint32_t CR21 :1; + __IO uint32_t CR22 :1; + __IO uint32_t CR23 :1; + __IO uint32_t CR24 :1; + __IO uint32_t CR25 :1; + __IO uint32_t CR26 :1; + __IO uint32_t CR27 :1; + __IO uint32_t CR28 :1; + __IO uint32_t CR29 :1; + __IO uint32_t CR30 :1; + __IO uint32_t CR31 :1; +} stc_canfd_txbcr_field_t; + +typedef struct stc_canfd_txbto_field +{ + __IO uint32_t TO0 :1; + __IO uint32_t TO1 :1; + __IO uint32_t TO2 :1; + __IO uint32_t TO3 :1; + __IO uint32_t TO4 :1; + __IO uint32_t TO5 :1; + __IO uint32_t TO6 :1; + __IO uint32_t TO7 :1; + __IO uint32_t TO8 :1; + __IO uint32_t TO9 :1; + __IO uint32_t TO10 :1; + __IO uint32_t TO11 :1; + __IO uint32_t TO12 :1; + __IO uint32_t TO13 :1; + __IO uint32_t TO14 :1; + __IO uint32_t TO15 :1; + __IO uint32_t TO16 :1; + __IO uint32_t TO17 :1; + __IO uint32_t TO18 :1; + __IO uint32_t TO19 :1; + __IO uint32_t TO20 :1; + __IO uint32_t TO21 :1; + __IO uint32_t TO22 :1; + __IO uint32_t TO23 :1; + __IO uint32_t TO24 :1; + __IO uint32_t TO25 :1; + __IO uint32_t TO26 :1; + __IO uint32_t TO27 :1; + __IO uint32_t TO28 :1; + __IO uint32_t TO29 :1; + __IO uint32_t TO30 :1; + __IO uint32_t TO31 :1; +} stc_canfd_txbto_field_t; + +typedef struct stc_canfd_txbcf_field +{ + __IO uint32_t CF0 :1; + __IO uint32_t CF1 :1; + __IO uint32_t CF2 :1; + __IO uint32_t CF3 :1; + __IO uint32_t CF4 :1; + __IO uint32_t CF5 :1; + __IO uint32_t CF6 :1; + __IO uint32_t CF7 :1; + __IO uint32_t CF8 :1; + __IO uint32_t CF9 :1; + __IO uint32_t CF10 :1; + __IO uint32_t CF11 :1; + __IO uint32_t CF12 :1; + __IO uint32_t CF13 :1; + __IO uint32_t CF14 :1; + __IO uint32_t CF15 :1; + __IO uint32_t CF16 :1; + __IO uint32_t CF17 :1; + __IO uint32_t CF18 :1; + __IO uint32_t CF19 :1; + __IO uint32_t CF20 :1; + __IO uint32_t CF21 :1; + __IO uint32_t CF22 :1; + __IO uint32_t CF23 :1; + __IO uint32_t CF24 :1; + __IO uint32_t CF25 :1; + __IO uint32_t CF26 :1; + __IO uint32_t CF27 :1; + __IO uint32_t CF28 :1; + __IO uint32_t CF29 :1; + __IO uint32_t CF30 :1; + __IO uint32_t CF31 :1; +} stc_canfd_txbcf_field_t; + +typedef struct stc_canfd_txbtie_field +{ + __IO uint32_t TIE0 :1; + __IO uint32_t TIE1 :1; + __IO uint32_t TIE2 :1; + __IO uint32_t TIE3 :1; + __IO uint32_t TIE4 :1; + __IO uint32_t TIE5 :1; + __IO uint32_t TIE6 :1; + __IO uint32_t TIE7 :1; + __IO uint32_t TIE8 :1; + __IO uint32_t TIE9 :1; + __IO uint32_t TIE10 :1; + __IO uint32_t TIE11 :1; + __IO uint32_t TIE12 :1; + __IO uint32_t TIE13 :1; + __IO uint32_t TIE14 :1; + __IO uint32_t TIE15 :1; + __IO uint32_t TIE16 :1; + __IO uint32_t TIE17 :1; + __IO uint32_t TIE18 :1; + __IO uint32_t TIE19 :1; + __IO uint32_t TIE20 :1; + __IO uint32_t TIE21 :1; + __IO uint32_t TIE22 :1; + __IO uint32_t TIE23 :1; + __IO uint32_t TIE24 :1; + __IO uint32_t TIE25 :1; + __IO uint32_t TIE26 :1; + __IO uint32_t TIE27 :1; + __IO uint32_t TIE28 :1; + __IO uint32_t TIE29 :1; + __IO uint32_t TIE30 :1; + __IO uint32_t TIE31 :1; +} stc_canfd_txbtie_field_t; + +typedef struct stc_canfd_txbcie_field +{ + __IO uint32_t CFIE0 :1; + __IO uint32_t CFIE1 :1; + __IO uint32_t CFIE2 :1; + __IO uint32_t CFIE3 :1; + __IO uint32_t CFIE4 :1; + __IO uint32_t CFIE5 :1; + __IO uint32_t CFIE6 :1; + __IO uint32_t CFIE7 :1; + __IO uint32_t CFIE8 :1; + __IO uint32_t CFIE9 :1; + __IO uint32_t CFIE10 :1; + __IO uint32_t CFIE11 :1; + __IO uint32_t CFIE12 :1; + __IO uint32_t CFIE13 :1; + __IO uint32_t CFIE14 :1; + __IO uint32_t CFIE15 :1; + __IO uint32_t CFIE16 :1; + __IO uint32_t CFIE17 :1; + __IO uint32_t CFIE18 :1; + __IO uint32_t CFIE19 :1; + __IO uint32_t CFIE20 :1; + __IO uint32_t CFIE21 :1; + __IO uint32_t CFIE22 :1; + __IO uint32_t CFIE23 :1; + __IO uint32_t CFIE24 :1; + __IO uint32_t CFIE25 :1; + __IO uint32_t CFIE26 :1; + __IO uint32_t CFIE27 :1; + __IO uint32_t CFIE28 :1; + __IO uint32_t CFIE29 :1; + __IO uint32_t CFIE30 :1; + __IO uint32_t CFIE31 :1; +} stc_canfd_txbcie_field_t; + +typedef struct stc_canfd_txefc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t EFSA :14; + __IO uint32_t EFS :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t EFWM :6; + __IO uint32_t RESERVED4 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t EFSA0 :1; + __IO uint32_t EFSA1 :1; + __IO uint32_t EFSA2 :1; + __IO uint32_t EFSA3 :1; + __IO uint32_t EFSA4 :1; + __IO uint32_t EFSA5 :1; + __IO uint32_t EFSA6 :1; + __IO uint32_t EFSA7 :1; + __IO uint32_t EFSA8 :1; + __IO uint32_t EFSA9 :1; + __IO uint32_t EFSA10 :1; + __IO uint32_t EFSA11 :1; + __IO uint32_t EFSA12 :1; + __IO uint32_t EFSA13 :1; + __IO uint32_t EFS0 :1; + __IO uint32_t EFS1 :1; + __IO uint32_t EFS2 :1; + __IO uint32_t EFS3 :1; + __IO uint32_t EFS4 :1; + __IO uint32_t EFS5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t EFWM0 :1; + __IO uint32_t EFWM1 :1; + __IO uint32_t EFWM2 :1; + __IO uint32_t EFWM3 :1; + __IO uint32_t EFWM4 :1; + __IO uint32_t EFWM5 :1; + __IO uint32_t RESERVED5 :2; + }; + }; +} stc_canfd_txefc_field_t; + +typedef struct stc_canfd_txfs_field +{ + union { + struct { + __IO uint32_t EFFL :6; + __IO uint32_t RESERVED0 :2; + __IO uint32_t EFGI :5; + __IO uint32_t RESERVED2 :3; + __IO uint32_t EFPI :5; + __IO uint32_t RESERVED4 :3; + __IO uint32_t EFF :1; + __IO uint32_t TEFL :1; + __IO uint32_t RESERVED5 :6; + }; + struct { + __IO uint32_t EFFL0 :1; + __IO uint32_t EFFL1 :1; + __IO uint32_t EFFL2 :1; + __IO uint32_t EFFL3 :1; + __IO uint32_t EFFL4 :1; + __IO uint32_t EFFL5 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t EFGI0 :1; + __IO uint32_t EFGI1 :1; + __IO uint32_t EFGI2 :1; + __IO uint32_t EFGI3 :1; + __IO uint32_t EFGI4 :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t EFPI0 :1; + __IO uint32_t EFPI1 :1; + __IO uint32_t EFPI2 :1; + __IO uint32_t EFPI3 :1; + __IO uint32_t EFPI4 :1; + __IO uint32_t RESERVED6 :11; + }; + }; +} stc_canfd_txfs_field_t; + +typedef struct stc_canfd_txfa_field +{ + union { + struct { + __IO uint32_t EFAI :5; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t EFAI0 :1; + __IO uint32_t EFAI1 :1; + __IO uint32_t EFAI2 :1; + __IO uint32_t EFAI3 :1; + __IO uint32_t EFAI4 :1; + __IO uint32_t RESERVED1 :27; + }; + }; +} stc_canfd_txfa_field_t; + +typedef struct stc_canfd_fdecr_field +{ + __IO uint8_t SEIE :1; + __IO uint8_t DEIE :1; + __IO uint8_t CEREN :1; + __IO uint8_t CEIV :1; + __IO uint8_t RESERVED0 :4; +} stc_canfd_fdecr_field_t; + +typedef struct stc_canfd_fdesr_field +{ + __IO uint8_t SEI :1; + __IO uint8_t DEI :1; + __IO uint8_t RESERVED0 :6; +} stc_canfd_fdesr_field_t; + +typedef struct stc_canfd_fdsear_field +{ + union { + struct { + __IO uint16_t SRA :16; + }; + struct { + __IO uint16_t SRA0 :1; + __IO uint16_t SRA1 :1; + __IO uint16_t SRA2 :1; + __IO uint16_t SRA3 :1; + __IO uint16_t SRA4 :1; + __IO uint16_t SRA5 :1; + __IO uint16_t SRA6 :1; + __IO uint16_t SRA7 :1; + __IO uint16_t SRA8 :1; + __IO uint16_t SRA9 :1; + __IO uint16_t SRA10 :1; + __IO uint16_t SRA11 :1; + __IO uint16_t SRA12 :1; + __IO uint16_t SRA13 :1; + __IO uint16_t SRA14 :1; + __IO uint16_t SRA15 :1; + }; + }; +} stc_canfd_fdsear_field_t; + +typedef struct stc_canfd_fdescr_field +{ + __IO uint8_t SEIC :1; + __IO uint8_t DEIC :1; + __IO uint8_t RESERVED0 :6; +} stc_canfd_fdescr_field_t; + +typedef struct stc_canfd_fddear_field +{ + union { + struct { + __IO uint16_t DRA :16; + }; + struct { + __IO uint16_t DRA0 :1; + __IO uint16_t DRA1 :1; + __IO uint16_t DRA2 :1; + __IO uint16_t DRA3 :1; + __IO uint16_t DRA4 :1; + __IO uint16_t DRA5 :1; + __IO uint16_t DRA6 :1; + __IO uint16_t DRA7 :1; + __IO uint16_t DRA8 :1; + __IO uint16_t DRA9 :1; + __IO uint16_t DRA10 :1; + __IO uint16_t DRA11 :1; + __IO uint16_t DRA12 :1; + __IO uint16_t DRA13 :1; + __IO uint16_t DRA14 :1; + __IO uint16_t DRA15 :1; + }; + }; +} stc_canfd_fddear_field_t; + +typedef struct stc_canfd_tscntr_field +{ + __IO uint16_t CCLR :1; + __IO uint16_t RESERVED0 :15; +} stc_canfd_tscntr_field_t; + +typedef struct stc_canfd_tsmdr_field +{ + __IO uint16_t CNTEN :1; + __IO uint16_t RESERVED0 :15; +} stc_canfd_tsmdr_field_t; + +typedef struct stc_canfd_tsdivr_field +{ + union { + struct { + __IO uint32_t CDIV :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t CDIV0 :1; + __IO uint32_t CDIV1 :1; + __IO uint32_t CDIV2 :1; + __IO uint32_t CDIV3 :1; + __IO uint32_t CDIV4 :1; + __IO uint32_t CDIV5 :1; + __IO uint32_t CDIV6 :1; + __IO uint32_t CDIV7 :1; + __IO uint32_t CDIV8 :1; + __IO uint32_t CDIV9 :1; + __IO uint32_t CDIV10 :1; + __IO uint32_t CDIV11 :1; + __IO uint32_t CDIV12 :1; + __IO uint32_t CDIV13 :1; + __IO uint32_t CDIV14 :1; + __IO uint32_t CDIV15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_tsdivr_field_t; + +typedef struct stc_canfd_tscdtr_field +{ + union { + struct { + __IO uint16_t CNT :16; + }; + struct { + __IO uint16_t CNT0 :1; + __IO uint16_t CNT1 :1; + __IO uint16_t CNT2 :1; + __IO uint16_t CNT3 :1; + __IO uint16_t CNT4 :1; + __IO uint16_t CNT5 :1; + __IO uint16_t CNT6 :1; + __IO uint16_t CNT7 :1; + __IO uint16_t CNT8 :1; + __IO uint16_t CNT9 :1; + __IO uint16_t CNT10 :1; + __IO uint16_t CNT11 :1; + __IO uint16_t CNT12 :1; + __IO uint16_t CNT13 :1; + __IO uint16_t CNT14 :1; + __IO uint16_t CNT15 :1; + }; + }; +} stc_canfd_tscdtr_field_t; + +typedef struct stc_canfd_tscpclr_field +{ + union { + struct { + __IO uint16_t CMP :16; + }; + struct { + __IO uint16_t CMP0 :1; + __IO uint16_t CMP1 :1; + __IO uint16_t CMP2 :1; + __IO uint16_t CMP3 :1; + __IO uint16_t CMP4 :1; + __IO uint16_t CMP5 :1; + __IO uint16_t CMP6 :1; + __IO uint16_t CMP7 :1; + __IO uint16_t CMP8 :1; + __IO uint16_t CMP9 :1; + __IO uint16_t CMP10 :1; + __IO uint16_t CMP11 :1; + __IO uint16_t CMP12 :1; + __IO uint16_t CMP13 :1; + __IO uint16_t CMP14 :1; + __IO uint16_t CMP15 :1; + }; + }; +} stc_canfd_tscpclr_field_t; + +/******************************************************************************* +* CANPRES_MODULE +*******************************************************************************/ +typedef struct stc_canpres_canpre_field +{ + union { + struct { + __IO uint8_t CANPRE :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t CANPRE0 :1; + __IO uint8_t CANPRE1 :1; + __IO uint8_t CANPRE2 :1; + __IO uint8_t CANPRE3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_canpres_canpre_field_t; + +/******************************************************************************* +* CLK_GATING_MODULE +*******************************************************************************/ +typedef struct stc_clk_gating_cken0_field +{ + __IO uint32_t MFSCK0 :1; + __IO uint32_t MFSCK1 :1; + __IO uint32_t MFSCK2 :1; + __IO uint32_t MFSCK3 :1; + __IO uint32_t MFSCK4 :1; + __IO uint32_t MFSCK5 :1; + __IO uint32_t MFSCK6 :1; + __IO uint32_t MFSCK7 :1; + __IO uint32_t MFSCK8 :1; + __IO uint32_t MFSCK9 :1; + __IO uint32_t MFSCK10 :1; + __IO uint32_t MFSCK11 :1; + __IO uint32_t MFSCK12 :1; + __IO uint32_t MFSCK13 :1; + __IO uint32_t MFSCK14 :1; + __IO uint32_t MFSCK15 :1; + __IO uint32_t ADCCK0 :1; + __IO uint32_t ADCCK1 :1; + __IO uint32_t ADCCK2 :1; + __IO uint32_t ADCCK3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t DMACK :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t EXBCK :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t GIOCK :1; + __IO uint32_t RESERVED3 :3; +} stc_clk_gating_cken0_field_t; + +typedef struct stc_clk_gating_mrst0_field +{ + __IO uint32_t MFSRST0 :1; + __IO uint32_t MFSRST1 :1; + __IO uint32_t MFSRST2 :1; + __IO uint32_t MFSRST3 :1; + __IO uint32_t MFSRST4 :1; + __IO uint32_t MFSRST5 :1; + __IO uint32_t MFSRST6 :1; + __IO uint32_t MFSRST7 :1; + __IO uint32_t MFSRST8 :1; + __IO uint32_t MFSRST9 :1; + __IO uint32_t MFSRST10 :1; + __IO uint32_t MFSRST11 :1; + __IO uint32_t MFSRST12 :1; + __IO uint32_t MFSRST13 :1; + __IO uint32_t MFSRST14 :1; + __IO uint32_t MFSRST15 :1; + __IO uint32_t ADCRST0 :1; + __IO uint32_t ADCRST1 :1; + __IO uint32_t ADCRST2 :1; + __IO uint32_t ADCRST3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t DMARST :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t EXBRST :1; + __IO uint32_t RESERVED2 :5; +} stc_clk_gating_mrst0_field_t; + +typedef struct stc_clk_gating_cken1_field +{ + __IO uint32_t BTMCK0 :1; + __IO uint32_t BTMCK1 :1; + __IO uint32_t BTMCK2 :1; + __IO uint32_t BTMCK3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t MFTCK0 :1; + __IO uint32_t MFTCK1 :1; + __IO uint32_t MFTCK2 :1; + __IO uint32_t MFTCK3 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t QDUCK0 :1; + __IO uint32_t QDUCK1 :1; + __IO uint32_t QDUCK2 :1; + __IO uint32_t QDUCK3 :1; + __IO uint32_t RESERVED2 :12; +} stc_clk_gating_cken1_field_t; + +typedef struct stc_clk_gating_mrst1_field +{ + __IO uint32_t BTMRST0 :1; + __IO uint32_t BTMRST1 :1; + __IO uint32_t BTMRST2 :1; + __IO uint32_t BTMRST3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t MFTRST0 :1; + __IO uint32_t MFTRST1 :1; + __IO uint32_t MFTRST2 :1; + __IO uint32_t MFTRST3 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t QDURST0 :1; + __IO uint32_t QDURST1 :1; + __IO uint32_t QDURST2 :1; + __IO uint32_t QDURST3 :1; + __IO uint32_t RESERVED2 :12; +} stc_clk_gating_mrst1_field_t; + +typedef struct stc_clk_gating_cken2_field +{ + __IO uint32_t USBCK0 :1; + __IO uint32_t USBCK1 :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t CANCK0 :1; + __IO uint32_t CANCK1 :1; + __IO uint32_t CANCK2 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SDCCK :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t I2SCK0 :1; + __IO uint32_t I2SCK1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t PCRCCK :1; + __IO uint32_t RESERVED4 :3; + __IO uint32_t CECCK0 :1; + __IO uint32_t CECCK1 :1; + __IO uint32_t RESERVED5 :2; + __IO uint32_t HSSPICK :1; + __IO uint32_t RESERVED6 :3; +} stc_clk_gating_cken2_field_t; + +typedef struct stc_clk_gating_mrst2_field +{ + __IO uint32_t USBRST0 :1; + __IO uint32_t USBRST1 :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t CANRST0 :1; + __IO uint32_t CANRST1 :1; + __IO uint32_t CANRST2 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SDCRST :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t I2SRST0 :1; + __IO uint32_t I2SRST1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t PCRCRST :1; + __IO uint32_t RESERVED4 :3; + __IO uint32_t CECRST0 :1; + __IO uint32_t CECRST1 :1; + __IO uint32_t RESERVED5 :2; + __IO uint32_t HSSPIRST :1; + __IO uint32_t RESERVED6 :3; +} stc_clk_gating_mrst2_field_t; + +/******************************************************************************* +* CRC_MODULE +*******************************************************************************/ +typedef struct stc_crc_crccr_field +{ + __IO uint8_t INIT :1; + __IO uint8_t CRC32 :1; + __IO uint8_t LTLEND :1; + __IO uint8_t LSBFST :1; + __IO uint8_t CRCLTE :1; + __IO uint8_t CRCLSF :1; + __IO uint8_t FXOR :1; + __IO uint8_t RESERVED0 :1; +} stc_crc_crccr_field_t; + +typedef struct stc_crc_crcinit_field +{ + union { + struct { + __IO uint32_t D :32; + }; + struct { + __IO uint32_t D0 :1; + __IO uint32_t D1 :1; + __IO uint32_t D2 :1; + __IO uint32_t D3 :1; + __IO uint32_t D4 :1; + __IO uint32_t D5 :1; + __IO uint32_t D6 :1; + __IO uint32_t D7 :1; + __IO uint32_t D8 :1; + __IO uint32_t D9 :1; + __IO uint32_t D10 :1; + __IO uint32_t D11 :1; + __IO uint32_t D12 :1; + __IO uint32_t D13 :1; + __IO uint32_t D14 :1; + __IO uint32_t D15 :1; + __IO uint32_t D16 :1; + __IO uint32_t D17 :1; + __IO uint32_t D18 :1; + __IO uint32_t D19 :1; + __IO uint32_t D20 :1; + __IO uint32_t D21 :1; + __IO uint32_t D22 :1; + __IO uint32_t D23 :1; + __IO uint32_t D24 :1; + __IO uint32_t D25 :1; + __IO uint32_t D26 :1; + __IO uint32_t D27 :1; + __IO uint32_t D28 :1; + __IO uint32_t D29 :1; + __IO uint32_t D30 :1; + __IO uint32_t D31 :1; + }; + }; +} stc_crc_crcinit_field_t; + +typedef struct stc_crc_crcin_field +{ + union { + struct { + __IO uint32_t D :32; + }; + struct { + __IO uint32_t D0 :1; + __IO uint32_t D1 :1; + __IO uint32_t D2 :1; + __IO uint32_t D3 :1; + __IO uint32_t D4 :1; + __IO uint32_t D5 :1; + __IO uint32_t D6 :1; + __IO uint32_t D7 :1; + __IO uint32_t D8 :1; + __IO uint32_t D9 :1; + __IO uint32_t D10 :1; + __IO uint32_t D11 :1; + __IO uint32_t D12 :1; + __IO uint32_t D13 :1; + __IO uint32_t D14 :1; + __IO uint32_t D15 :1; + __IO uint32_t D16 :1; + __IO uint32_t D17 :1; + __IO uint32_t D18 :1; + __IO uint32_t D19 :1; + __IO uint32_t D20 :1; + __IO uint32_t D21 :1; + __IO uint32_t D22 :1; + __IO uint32_t D23 :1; + __IO uint32_t D24 :1; + __IO uint32_t D25 :1; + __IO uint32_t D26 :1; + __IO uint32_t D27 :1; + __IO uint32_t D28 :1; + __IO uint32_t D29 :1; + __IO uint32_t D30 :1; + __IO uint32_t D31 :1; + }; + }; +} stc_crc_crcin_field_t; + +typedef struct stc_crc_crcr_field +{ + union { + struct { + __IO uint32_t D :32; + }; + struct { + __IO uint32_t D0 :1; + __IO uint32_t D1 :1; + __IO uint32_t D2 :1; + __IO uint32_t D3 :1; + __IO uint32_t D4 :1; + __IO uint32_t D5 :1; + __IO uint32_t D6 :1; + __IO uint32_t D7 :1; + __IO uint32_t D8 :1; + __IO uint32_t D9 :1; + __IO uint32_t D10 :1; + __IO uint32_t D11 :1; + __IO uint32_t D12 :1; + __IO uint32_t D13 :1; + __IO uint32_t D14 :1; + __IO uint32_t D15 :1; + __IO uint32_t D16 :1; + __IO uint32_t D17 :1; + __IO uint32_t D18 :1; + __IO uint32_t D19 :1; + __IO uint32_t D20 :1; + __IO uint32_t D21 :1; + __IO uint32_t D22 :1; + __IO uint32_t D23 :1; + __IO uint32_t D24 :1; + __IO uint32_t D25 :1; + __IO uint32_t D26 :1; + __IO uint32_t D27 :1; + __IO uint32_t D28 :1; + __IO uint32_t D29 :1; + __IO uint32_t D30 :1; + __IO uint32_t D31 :1; + }; + }; +} stc_crc_crcr_field_t; + +/******************************************************************************* +* CRG_MODULE +*******************************************************************************/ +typedef struct stc_crg_scm_ctl_field +{ + union { + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t MOSCE :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SOSCE :1; + __IO uint32_t PLLE :1; + __IO uint32_t RCS :3; + __IO uint32_t RESERVED3 :24; + }; + struct { + __IO uint32_t RESERVED2 :5; + __IO uint32_t RCS0 :1; + __IO uint32_t RCS1 :1; + __IO uint32_t RCS2 :1; + __IO uint32_t RESERVED4 :24; + }; + }; +} stc_crg_scm_ctl_field_t; + +typedef struct stc_crg_scm_str_field +{ + union { + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t MORDY :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SORDY :1; + __IO uint32_t PLRDY :1; + __IO uint32_t RCM :3; + __IO uint32_t RESERVED3 :24; + }; + struct { + __IO uint32_t RESERVED2 :5; + __IO uint32_t RCM0 :1; + __IO uint32_t RCM1 :1; + __IO uint32_t RCM2 :1; + __IO uint32_t RESERVED4 :24; + }; + }; +} stc_crg_scm_str_field_t; + +typedef struct stc_crg_stb_ctl_field +{ + union { + struct { + __IO uint32_t STM :2; + __IO uint32_t DSTM :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t SPL :1; + __IO uint32_t RESERVED1 :11; + __IO uint32_t KEY :16; + }; + struct { + __IO uint32_t STM0 :1; + __IO uint32_t STM1 :1; + __IO uint32_t RESERVED2 :14; + __IO uint32_t KEY0 :1; + __IO uint32_t KEY1 :1; + __IO uint32_t KEY2 :1; + __IO uint32_t KEY3 :1; + __IO uint32_t KEY4 :1; + __IO uint32_t KEY5 :1; + __IO uint32_t KEY6 :1; + __IO uint32_t KEY7 :1; + __IO uint32_t KEY8 :1; + __IO uint32_t KEY9 :1; + __IO uint32_t KEY10 :1; + __IO uint32_t KEY11 :1; + __IO uint32_t KEY12 :1; + __IO uint32_t KEY13 :1; + __IO uint32_t KEY14 :1; + __IO uint32_t KEY15 :1; + }; + }; +} stc_crg_stb_ctl_field_t; + +typedef struct stc_crg_rst_str_field +{ + __IO uint32_t PONR :1; + __IO uint32_t INITX :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t SWDT :1; + __IO uint32_t HWDT :1; + __IO uint32_t CSVR :1; + __IO uint32_t FCSR :1; + __IO uint32_t SRST :1; + __IO uint32_t RESERVED1 :23; +} stc_crg_rst_str_field_t; + +typedef struct stc_crg_bsc_psr_field +{ + union { + struct { + __IO uint32_t BSR :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t BSR0 :1; + __IO uint32_t BSR1 :1; + __IO uint32_t BSR2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_crg_bsc_psr_field_t; + +typedef struct stc_crg_apbc0_psr_field +{ + union { + struct { + __IO uint32_t APBC0 :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t APBC00 :1; + __IO uint32_t APBC01 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_crg_apbc0_psr_field_t; + +typedef struct stc_crg_apbc1_psr_field +{ + union { + struct { + __IO uint32_t APBC1 :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t APBC1RST :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t APBC1EN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t APBC10 :1; + __IO uint32_t APBC11 :1; + __IO uint32_t RESERVED3 :30; + }; + }; +} stc_crg_apbc1_psr_field_t; + +typedef struct stc_crg_apbc2_psr_field +{ + union { + struct { + __IO uint32_t APBC2 :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t APBC2RST :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t APBC2EN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t APBC20 :1; + __IO uint32_t APBC21 :1; + __IO uint32_t RESERVED3 :30; + }; + }; +} stc_crg_apbc2_psr_field_t; + +typedef struct stc_crg_swc_psr_field +{ + union { + struct { + __IO uint32_t SWDS :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t SWDS0 :1; + __IO uint32_t SWDS1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_crg_swc_psr_field_t; + +typedef struct stc_crg_ttc_psr_field +{ + union { + struct { + __IO uint32_t TTC :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t TTC0 :1; + __IO uint32_t TTC1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_crg_ttc_psr_field_t; + +typedef struct stc_crg_csw_tmr_field +{ + union { + struct { + __IO uint32_t MOWT :4; + __IO uint32_t SOWT :4; + __IO uint32_t RESERVED0 :24; + }; + struct { + __IO uint32_t MOWT0 :1; + __IO uint32_t MOWT1 :1; + __IO uint32_t MOWT2 :1; + __IO uint32_t MOWT3 :1; + __IO uint32_t SOWT0 :1; + __IO uint32_t SOWT1 :1; + __IO uint32_t SOWT2 :1; + __IO uint32_t SOWT3 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_crg_csw_tmr_field_t; + +typedef struct stc_crg_psw_tmr_field +{ + union { + struct { + __IO uint32_t POWT :3; + __IO uint32_t RESERVED0 :1; + __IO uint32_t PINC :1; + __IO uint32_t RESERVED1 :27; + }; + struct { + __IO uint32_t POWT0 :1; + __IO uint32_t POWT1 :1; + __IO uint32_t POWT2 :1; + __IO uint32_t RESERVED2 :29; + }; + }; +} stc_crg_psw_tmr_field_t; + +typedef struct stc_crg_pll_ctl1_field +{ + union { + struct { + __IO uint32_t PLLM :4; + __IO uint32_t PLLK :4; + __IO uint32_t RESERVED0 :24; + }; + struct { + __IO uint32_t PLLM0 :1; + __IO uint32_t PLLM1 :1; + __IO uint32_t PLLM2 :1; + __IO uint32_t PLLM3 :1; + __IO uint32_t PLLK0 :1; + __IO uint32_t PLLK1 :1; + __IO uint32_t PLLK2 :1; + __IO uint32_t PLLK3 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_crg_pll_ctl1_field_t; + +typedef struct stc_crg_pll_ctl2_field +{ + union { + struct { + __IO uint32_t PLLN :6; + __IO uint32_t RESERVED0 :26; + }; + struct { + __IO uint32_t PLLN0 :1; + __IO uint32_t PLLN1 :1; + __IO uint32_t PLLN2 :1; + __IO uint32_t PLLN3 :1; + __IO uint32_t PLLN4 :1; + __IO uint32_t PLLN5 :1; + __IO uint32_t RESERVED1 :26; + }; + }; +} stc_crg_pll_ctl2_field_t; + +typedef struct stc_crg_csv_ctl_field +{ + union { + struct { + __IO uint32_t MCSVE :1; + __IO uint32_t SCSVE :1; + __IO uint32_t RESERVED0 :6; + __IO uint32_t FCSDE :1; + __IO uint32_t FCSRE :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t FCD :3; + __IO uint32_t RESERVED3 :17; + }; + struct { + __IO uint32_t RESERVED2 :12; + __IO uint32_t FCD0 :1; + __IO uint32_t FCD1 :1; + __IO uint32_t FCD2 :1; + __IO uint32_t RESERVED4 :17; + }; + }; +} stc_crg_csv_ctl_field_t; + +typedef struct stc_crg_csv_str_field +{ + __IO uint32_t MCMF :1; + __IO uint32_t SCMF :1; + __IO uint32_t RESERVED0 :30; +} stc_crg_csv_str_field_t; + +typedef struct stc_crg_fcswh_ctl_field +{ + union { + struct { + __IO uint32_t FWH :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t FWH0 :1; + __IO uint32_t FWH1 :1; + __IO uint32_t FWH2 :1; + __IO uint32_t FWH3 :1; + __IO uint32_t FWH4 :1; + __IO uint32_t FWH5 :1; + __IO uint32_t FWH6 :1; + __IO uint32_t FWH7 :1; + __IO uint32_t FWH8 :1; + __IO uint32_t FWH9 :1; + __IO uint32_t FWH10 :1; + __IO uint32_t FWH11 :1; + __IO uint32_t FWH12 :1; + __IO uint32_t FWH13 :1; + __IO uint32_t FWH14 :1; + __IO uint32_t FWH15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_crg_fcswh_ctl_field_t; + +typedef struct stc_crg_fcswl_ctl_field +{ + union { + struct { + __IO uint32_t FWL :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t FWL0 :1; + __IO uint32_t FWL1 :1; + __IO uint32_t FWL2 :1; + __IO uint32_t FWL3 :1; + __IO uint32_t FWL4 :1; + __IO uint32_t FWL5 :1; + __IO uint32_t FWL6 :1; + __IO uint32_t FWL7 :1; + __IO uint32_t FWL8 :1; + __IO uint32_t FWL9 :1; + __IO uint32_t FWL10 :1; + __IO uint32_t FWL11 :1; + __IO uint32_t FWL12 :1; + __IO uint32_t FWL13 :1; + __IO uint32_t FWL14 :1; + __IO uint32_t FWL15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_crg_fcswl_ctl_field_t; + +typedef struct stc_crg_fcswd_ctl_field +{ + union { + struct { + __IO uint32_t FWD :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t FWD0 :1; + __IO uint32_t FWD1 :1; + __IO uint32_t FWD2 :1; + __IO uint32_t FWD3 :1; + __IO uint32_t FWD4 :1; + __IO uint32_t FWD5 :1; + __IO uint32_t FWD6 :1; + __IO uint32_t FWD7 :1; + __IO uint32_t FWD8 :1; + __IO uint32_t FWD9 :1; + __IO uint32_t FWD10 :1; + __IO uint32_t FWD11 :1; + __IO uint32_t FWD12 :1; + __IO uint32_t FWD13 :1; + __IO uint32_t FWD14 :1; + __IO uint32_t FWD15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_crg_fcswd_ctl_field_t; + +typedef struct stc_crg_dbwdt_ctl_field +{ + __IO uint32_t RESERVED0 :5; + __IO uint32_t DPSWBE :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t DPHWBE :1; + __IO uint32_t RESERVED2 :24; +} stc_crg_dbwdt_ctl_field_t; + +typedef struct stc_crg_int_enr_field +{ + __IO uint32_t MCSE :1; + __IO uint32_t SCSE :1; + __IO uint32_t PCSE :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FCSE :1; + __IO uint32_t RESERVED1 :26; +} stc_crg_int_enr_field_t; + +typedef struct stc_crg_int_str_field +{ + __IO uint32_t MCSI :1; + __IO uint32_t SCSI :1; + __IO uint32_t PCSI :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FCSI :1; + __IO uint32_t RESERVED1 :26; +} stc_crg_int_str_field_t; + +typedef struct stc_crg_int_clr_field +{ + __IO uint32_t MCSC :1; + __IO uint32_t SCSC :1; + __IO uint32_t PCSC :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FCSC :1; + __IO uint32_t RESERVED1 :26; +} stc_crg_int_clr_field_t; + +typedef struct stc_crg_pllcg_ctl_field +{ + union { + struct { + __IO uint32_t PLLCGEN :1; + __IO uint32_t PLLCGSTR :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t PLLCGSTS :2; + __IO uint32_t PLLCGSSN :6; + __IO uint32_t PLLCGSTP :2; + __IO uint32_t PLLCGLP :8; + __IO uint32_t RESERVED2 :8; + }; + struct { + __IO uint32_t RESERVED1 :6; + __IO uint32_t PLLCGSTS0 :1; + __IO uint32_t PLLCGSTS1 :1; + __IO uint32_t PLLCGSSN0 :1; + __IO uint32_t PLLCGSSN1 :1; + __IO uint32_t PLLCGSSN2 :1; + __IO uint32_t PLLCGSSN3 :1; + __IO uint32_t PLLCGSSN4 :1; + __IO uint32_t PLLCGSSN5 :1; + __IO uint32_t PLLCGSTP0 :1; + __IO uint32_t PLLCGSTP1 :1; + __IO uint32_t PLLCGLP0 :1; + __IO uint32_t PLLCGLP1 :1; + __IO uint32_t PLLCGLP2 :1; + __IO uint32_t PLLCGLP3 :1; + __IO uint32_t PLLCGLP4 :1; + __IO uint32_t PLLCGLP5 :1; + __IO uint32_t PLLCGLP6 :1; + __IO uint32_t PLLCGLP7 :1; + __IO uint32_t RESERVED3 :8; + }; + }; +} stc_crg_pllcg_ctl_field_t; + +/******************************************************************************* +* CRTRIM_MODULE +*******************************************************************************/ +typedef struct stc_crtrim_mcr_psr_field +{ + union { + struct { + __IO uint8_t CSR :3; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t CSR0 :1; + __IO uint8_t CSR1 :1; + __IO uint8_t CSR2 :1; + __IO uint8_t RESERVED1 :5; + }; + }; +} stc_crtrim_mcr_psr_field_t; + +typedef struct stc_crtrim_mcr_ftrm_field +{ + union { + struct { + __IO uint32_t TRD :10; + __IO uint32_t RESERVED0 :22; + }; + struct { + __IO uint32_t TRD0 :1; + __IO uint32_t TRD1 :1; + __IO uint32_t TRD2 :1; + __IO uint32_t TRD3 :1; + __IO uint32_t TRD4 :1; + __IO uint32_t TRD5 :1; + __IO uint32_t TRD6 :1; + __IO uint32_t TRD7 :1; + __IO uint32_t TRD8 :1; + __IO uint32_t TRD9 :1; + __IO uint32_t RESERVED1 :22; + }; + }; +} stc_crtrim_mcr_ftrm_field_t; + +typedef struct stc_crtrim_mcr_ttrm_field +{ + union { + struct { + __IO uint32_t TRT :5; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t TRT0 :1; + __IO uint32_t TRT1 :1; + __IO uint32_t TRT2 :1; + __IO uint32_t TRT3 :1; + __IO uint32_t TRT4 :1; + __IO uint32_t RESERVED1 :27; + }; + }; +} stc_crtrim_mcr_ttrm_field_t; + +typedef struct stc_crtrim_mcr_rlr_field +{ + union { + struct { + __IO uint32_t TRMLCK :32; + }; + struct { + __IO uint32_t TRMLCK0 :1; + __IO uint32_t TRMLCK1 :1; + __IO uint32_t TRMLCK2 :1; + __IO uint32_t TRMLCK3 :1; + __IO uint32_t TRMLCK4 :1; + __IO uint32_t TRMLCK5 :1; + __IO uint32_t TRMLCK6 :1; + __IO uint32_t TRMLCK7 :1; + __IO uint32_t TRMLCK8 :1; + __IO uint32_t TRMLCK9 :1; + __IO uint32_t TRMLCK10 :1; + __IO uint32_t TRMLCK11 :1; + __IO uint32_t TRMLCK12 :1; + __IO uint32_t TRMLCK13 :1; + __IO uint32_t TRMLCK14 :1; + __IO uint32_t TRMLCK15 :1; + __IO uint32_t TRMLCK16 :1; + __IO uint32_t TRMLCK17 :1; + __IO uint32_t TRMLCK18 :1; + __IO uint32_t TRMLCK19 :1; + __IO uint32_t TRMLCK20 :1; + __IO uint32_t TRMLCK21 :1; + __IO uint32_t TRMLCK22 :1; + __IO uint32_t TRMLCK23 :1; + __IO uint32_t TRMLCK24 :1; + __IO uint32_t TRMLCK25 :1; + __IO uint32_t TRMLCK26 :1; + __IO uint32_t TRMLCK27 :1; + __IO uint32_t TRMLCK28 :1; + __IO uint32_t TRMLCK29 :1; + __IO uint32_t TRMLCK30 :1; + __IO uint32_t TRMLCK31 :1; + }; + }; +} stc_crtrim_mcr_rlr_field_t; + +/******************************************************************************* +* DAC_MODULE +*******************************************************************************/ +typedef struct stc_dac_dacr_field +{ + __IO uint8_t DAE :1; + __IO uint8_t DRDY :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DAC10 :1; + __IO uint8_t DDAS :1; + __IO uint8_t RESERVED1 :2; +} stc_dac_dacr_field_t; + +typedef struct stc_dac_dadr_field +{ + union { + struct { + __IO uint16_t DA :12; + __IO uint16_t RESERVED0 :4; + }; + struct { + __IO uint16_t DA0 :1; + __IO uint16_t DA1 :1; + __IO uint16_t DA2 :1; + __IO uint16_t DA3 :1; + __IO uint16_t DA4 :1; + __IO uint16_t DA5 :1; + __IO uint16_t DA6 :1; + __IO uint16_t DA7 :1; + __IO uint16_t DA8 :1; + __IO uint16_t DA9 :1; + __IO uint16_t DA10 :1; + __IO uint16_t DA11 :1; + __IO uint16_t RESERVED1 :4; + }; + }; +} stc_dac_dadr_field_t; + +/******************************************************************************* +* DMAC_MODULE +*******************************************************************************/ +typedef struct stc_dmac_dmacr_field +{ + union { + struct { + __IO uint32_t RESERVED0 :24; + __IO uint32_t DH :4; + __IO uint32_t PR :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t DS :1; + __IO uint32_t DE :1; + }; + struct { + __IO uint32_t RESERVED1 :24; + __IO uint32_t DH0 :1; + __IO uint32_t DH1 :1; + __IO uint32_t DH2 :1; + __IO uint32_t DH3 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_dmac_dmacr_field_t; + +typedef struct stc_dmac_dmaca0_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca0_field_t; + +typedef struct stc_dmac_dmacb0_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb0_field_t; + +typedef struct stc_dmac_dmaca1_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca1_field_t; + +typedef struct stc_dmac_dmacb1_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb1_field_t; + +typedef struct stc_dmac_dmaca2_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca2_field_t; + +typedef struct stc_dmac_dmacb2_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb2_field_t; + +typedef struct stc_dmac_dmaca3_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca3_field_t; + +typedef struct stc_dmac_dmacb3_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb3_field_t; + +typedef struct stc_dmac_dmaca4_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca4_field_t; + +typedef struct stc_dmac_dmacb4_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb4_field_t; + +typedef struct stc_dmac_dmaca5_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca5_field_t; + +typedef struct stc_dmac_dmacb5_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb5_field_t; + +typedef struct stc_dmac_dmaca6_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca6_field_t; + +typedef struct stc_dmac_dmacb6_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb6_field_t; + +typedef struct stc_dmac_dmaca7_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca7_field_t; + +typedef struct stc_dmac_dmacb7_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb7_field_t; + +/******************************************************************************* +* DS_MODULE +*******************************************************************************/ +typedef struct stc_ds_rck_ctl_field +{ + __IO uint8_t RTCCKE :1; + __IO uint8_t CECCKE :1; + __IO uint8_t RESERVED0 :6; +} stc_ds_rck_ctl_field_t; + +typedef struct stc_ds_pmd_ctl_field +{ + __IO uint8_t RTCE :1; + __IO uint8_t RESERVED0 :7; +} stc_ds_pmd_ctl_field_t; + +typedef struct stc_ds_wrfsr_field +{ + __IO uint8_t WINITX :1; + __IO uint8_t WLVDH :1; + __IO uint8_t RESERVED0 :6; +} stc_ds_wrfsr_field_t; + +typedef struct stc_ds_wifsr_field +{ + __IO uint16_t WRTCI :1; + __IO uint16_t WLVDI :1; + __IO uint16_t WUI0 :1; + __IO uint16_t WUI1 :1; + __IO uint16_t WUI2 :1; + __IO uint16_t WUI3 :1; + __IO uint16_t WUI4 :1; + __IO uint16_t WUI5 :1; + __IO uint16_t RESERVED0 :8; +} stc_ds_wifsr_field_t; + +typedef struct stc_ds_wier_field +{ + __IO uint16_t WRTCE :1; + __IO uint16_t WLVDE :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t WUI1E :1; + __IO uint16_t WUI2E :1; + __IO uint16_t WUI3E :1; + __IO uint16_t WUI4E :1; + __IO uint16_t WUI5E :1; + __IO uint16_t RESERVED1 :8; +} stc_ds_wier_field_t; + +typedef struct stc_ds_wilvr_field +{ + __IO uint8_t WUI1LV :1; + __IO uint8_t WUI2LV :1; + __IO uint8_t WUI3LV :1; + __IO uint8_t WUI4LV :1; + __IO uint8_t WUI5LV :1; + __IO uint8_t RESERVED0 :3; +} stc_ds_wilvr_field_t; + +typedef struct stc_ds_dsramr_field +{ + union { + struct { + __IO uint8_t SRAMR :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t SRAMR0 :1; + __IO uint8_t SRAMR1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_ds_dsramr_field_t; + +/******************************************************************************* +* DSTC_MODULE +*******************************************************************************/ +typedef struct stc_dstc_hwdesp_field +{ + union { + struct { + __IO uint32_t CHANNEL :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t HWDESP :14; + __IO uint32_t RESERVED2 :2; + }; + struct { + __IO uint32_t CHANNEL0 :1; + __IO uint32_t CHANNEL1 :1; + __IO uint32_t CHANNEL2 :1; + __IO uint32_t CHANNEL3 :1; + __IO uint32_t CHANNEL4 :1; + __IO uint32_t CHANNEL5 :1; + __IO uint32_t CHANNEL6 :1; + __IO uint32_t CHANNEL7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t HWDESP0 :1; + __IO uint32_t HWDESP1 :1; + __IO uint32_t HWDESP2 :1; + __IO uint32_t HWDESP3 :1; + __IO uint32_t HWDESP4 :1; + __IO uint32_t HWDESP5 :1; + __IO uint32_t HWDESP6 :1; + __IO uint32_t HWDESP7 :1; + __IO uint32_t HWDESP8 :1; + __IO uint32_t HWDESP9 :1; + __IO uint32_t HWDESP10 :1; + __IO uint32_t HWDESP11 :1; + __IO uint32_t HWDESP12 :1; + __IO uint32_t HWDESP13 :1; + __IO uint32_t RESERVED3 :2; + }; + }; +} stc_dstc_hwdesp_field_t; + +typedef struct stc_dstc_cfg_field +{ + union { + struct { + __IO uint8_t SWINTE :1; + __IO uint8_t ERINTE :1; + __IO uint8_t RBDIS :1; + __IO uint8_t ESTE :1; + __IO uint8_t SWPR :3; + __IO uint8_t RESERVED1 :1; + }; + struct { + __IO uint8_t RESERVED0 :4; + __IO uint8_t SWPR0 :1; + __IO uint8_t SWPR1 :1; + __IO uint8_t SWPR2 :1; + __IO uint8_t RESERVED2 :1; + }; + }; +} stc_dstc_cfg_field_t; + +typedef struct stc_dstc_swtr_field +{ + union { + struct { + __IO uint16_t SWDESP :14; + __IO uint16_t SWREQ :1; + __IO uint16_t SWST :1; + }; + struct { + __IO uint16_t SWDESP0 :1; + __IO uint16_t SWDESP1 :1; + __IO uint16_t SWDESP2 :1; + __IO uint16_t SWDESP3 :1; + __IO uint16_t SWDESP4 :1; + __IO uint16_t SWDESP5 :1; + __IO uint16_t SWDESP6 :1; + __IO uint16_t SWDESP7 :1; + __IO uint16_t SWDESP8 :1; + __IO uint16_t SWDESP9 :1; + __IO uint16_t SWDESP10 :1; + __IO uint16_t SWDESP11 :1; + __IO uint16_t SWDESP12 :1; + __IO uint16_t SWDESP13 :1; + __IO uint16_t RESERVED0 :2; + }; + }; +} stc_dstc_swtr_field_t; + +typedef struct stc_dstc_moners_field +{ + union { + struct { + __IO uint32_t EST :3; + __IO uint32_t DER :1; + __IO uint32_t ESTOP :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t EHS :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t ECH :8; + __IO uint32_t EDESP :14; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t EST0 :1; + __IO uint32_t EST1 :1; + __IO uint32_t EST2 :1; + __IO uint32_t RESERVED2 :5; + __IO uint32_t ECH0 :1; + __IO uint32_t ECH1 :1; + __IO uint32_t ECH2 :1; + __IO uint32_t ECH3 :1; + __IO uint32_t ECH4 :1; + __IO uint32_t ECH5 :1; + __IO uint32_t ECH6 :1; + __IO uint32_t ECH7 :1; + __IO uint32_t EDESP0 :1; + __IO uint32_t EDESP1 :1; + __IO uint32_t EDESP2 :1; + __IO uint32_t EDESP3 :1; + __IO uint32_t EDESP4 :1; + __IO uint32_t EDESP5 :1; + __IO uint32_t EDESP6 :1; + __IO uint32_t EDESP7 :1; + __IO uint32_t EDESP8 :1; + __IO uint32_t EDESP9 :1; + __IO uint32_t EDESP10 :1; + __IO uint32_t EDESP11 :1; + __IO uint32_t EDESP12 :1; + __IO uint32_t EDESP13 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dstc_moners_field_t; + +/******************************************************************************* +* DT_MODULE +*******************************************************************************/ +typedef struct stc_dt_timer1control_field +{ + union { + struct { + __IO uint32_t ONESHOT :1; + __IO uint32_t TIMERSIZE :1; + __IO uint32_t TIMERPRE :2; + __IO uint32_t RESERVED1 :1; + __IO uint32_t INTENABLE :1; + __IO uint32_t TIMERMODE :1; + __IO uint32_t TIMEREN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIMERPRE0 :1; + __IO uint32_t TIMERPRE1 :1; + __IO uint32_t RESERVED3 :28; + }; + }; +} stc_dt_timer1control_field_t; + +typedef struct stc_dt_timer1ris_field +{ + __IO uint32_t TIMER1RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer1ris_field_t; + +typedef struct stc_dt_timer1mis_field +{ + __IO uint32_t TIMER1MIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer1mis_field_t; + +typedef struct stc_dt_timer2control_field +{ + union { + struct { + __IO uint32_t ONESHOT :1; + __IO uint32_t TIMERSIZE :1; + __IO uint32_t TIMERPRE :2; + __IO uint32_t RESERVED1 :1; + __IO uint32_t INTENABLE :1; + __IO uint32_t TIMERMODE :1; + __IO uint32_t TIMEREN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIMERPRE0 :1; + __IO uint32_t TIMERPRE1 :1; + __IO uint32_t RESERVED3 :28; + }; + }; +} stc_dt_timer2control_field_t; + +typedef struct stc_dt_timer2ris_field +{ + __IO uint32_t TIMER2RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer2ris_field_t; + +typedef struct stc_dt_timer2mis_field +{ + __IO uint32_t TIMER2MIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer2mis_field_t; + +/******************************************************************************* +* DUALFLASH_IF_MODULE +*******************************************************************************/ +typedef struct stc_dualflash_if_dfaszr_field +{ + union { + struct { + __IO uint32_t DASZ :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t DASZ0 :1; + __IO uint32_t DASZ1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_dualflash_if_dfaszr_field_t; + +typedef struct stc_dualflash_if_dfrwtr_field +{ + union { + struct { + __IO uint32_t DRWT :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t DRWT0 :1; + __IO uint32_t DRWT1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_dualflash_if_dfrwtr_field_t; + +typedef struct stc_dualflash_if_dfstr_field +{ + __IO uint32_t DFRDY :1; + __IO uint32_t DFHNG :1; + __IO uint32_t DFERR :1; + __IO uint32_t RESERVED0 :29; +} stc_dualflash_if_dfstr_field_t; + +/******************************************************************************* +* ECC_CAPTURE_MODULE +*******************************************************************************/ +typedef struct stc_ecc_capture_ferrad_field +{ + union { + struct { + __IO uint32_t ERRAD :23; + __IO uint32_t RESERVED0 :9; + }; + struct { + __IO uint32_t ERRAD0 :1; + __IO uint32_t ERRAD1 :1; + __IO uint32_t ERRAD2 :1; + __IO uint32_t ERRAD3 :1; + __IO uint32_t ERRAD4 :1; + __IO uint32_t ERRAD5 :1; + __IO uint32_t ERRAD6 :1; + __IO uint32_t ERRAD7 :1; + __IO uint32_t ERRAD8 :1; + __IO uint32_t ERRAD9 :1; + __IO uint32_t ERRAD10 :1; + __IO uint32_t ERRAD11 :1; + __IO uint32_t ERRAD12 :1; + __IO uint32_t ERRAD13 :1; + __IO uint32_t ERRAD14 :1; + __IO uint32_t ERRAD15 :1; + __IO uint32_t ERRAD16 :1; + __IO uint32_t ERRAD17 :1; + __IO uint32_t ERRAD18 :1; + __IO uint32_t ERRAD19 :1; + __IO uint32_t ERRAD20 :1; + __IO uint32_t ERRAD21 :1; + __IO uint32_t ERRAD22 :1; + __IO uint32_t RESERVED1 :9; + }; + }; +} stc_ecc_capture_ferrad_field_t; + +/******************************************************************************* +* EXBUS_MODULE +*******************************************************************************/ +typedef struct stc_exbus_mode0_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode0_field_t; + +typedef struct stc_exbus_mode1_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode1_field_t; + +typedef struct stc_exbus_mode2_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode2_field_t; + +typedef struct stc_exbus_mode3_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode3_field_t; + +typedef struct stc_exbus_mode4_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode4_field_t; + +typedef struct stc_exbus_mode5_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode5_field_t; + +typedef struct stc_exbus_mode6_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode6_field_t; + +typedef struct stc_exbus_mode7_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode7_field_t; + +typedef struct stc_exbus_tim0_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim0_field_t; + +typedef struct stc_exbus_tim1_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim1_field_t; + +typedef struct stc_exbus_tim2_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim2_field_t; + +typedef struct stc_exbus_tim3_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim3_field_t; + +typedef struct stc_exbus_tim4_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim4_field_t; + +typedef struct stc_exbus_tim5_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim5_field_t; + +typedef struct stc_exbus_tim6_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim6_field_t; + +typedef struct stc_exbus_tim7_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim7_field_t; + +typedef struct stc_exbus_area0_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area0_field_t; + +typedef struct stc_exbus_area1_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area1_field_t; + +typedef struct stc_exbus_area2_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area2_field_t; + +typedef struct stc_exbus_area3_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area3_field_t; + +typedef struct stc_exbus_area4_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area4_field_t; + +typedef struct stc_exbus_area5_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area5_field_t; + +typedef struct stc_exbus_area6_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area6_field_t; + +typedef struct stc_exbus_area7_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area7_field_t; + +typedef struct stc_exbus_atim0_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim0_field_t; + +typedef struct stc_exbus_atim1_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim1_field_t; + +typedef struct stc_exbus_atim2_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim2_field_t; + +typedef struct stc_exbus_atim3_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim3_field_t; + +typedef struct stc_exbus_atim4_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim4_field_t; + +typedef struct stc_exbus_atim5_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim5_field_t; + +typedef struct stc_exbus_atim6_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim6_field_t; + +typedef struct stc_exbus_atim7_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim7_field_t; + +typedef struct stc_exbus_sdmode_field +{ + union { + struct { + __IO uint32_t SDON :1; + __IO uint32_t PDON :1; + __IO uint32_t ROFF :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t CASEL :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t RASEL :4; + __IO uint32_t BASEL :4; + __IO uint32_t MSDCLKOFF :1; + __IO uint32_t RESERVED4 :15; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t CASEL0 :1; + __IO uint32_t CASEL1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t RASEL0 :1; + __IO uint32_t RASEL1 :1; + __IO uint32_t RASEL2 :1; + __IO uint32_t RASEL3 :1; + __IO uint32_t BASEL0 :1; + __IO uint32_t BASEL1 :1; + __IO uint32_t BASEL2 :1; + __IO uint32_t BASEL3 :1; + __IO uint32_t RESERVED5 :16; + }; + }; +} stc_exbus_sdmode_field_t; + +typedef struct stc_exbus_reftim_field +{ + union { + struct { + __IO uint32_t REFC :16; + __IO uint32_t NREF :8; + __IO uint32_t PREF :1; + __IO uint32_t RESERVED0 :7; + }; + struct { + __IO uint32_t REFC0 :1; + __IO uint32_t REFC1 :1; + __IO uint32_t REFC2 :1; + __IO uint32_t REFC3 :1; + __IO uint32_t REFC4 :1; + __IO uint32_t REFC5 :1; + __IO uint32_t REFC6 :1; + __IO uint32_t REFC7 :1; + __IO uint32_t REFC8 :1; + __IO uint32_t REFC9 :1; + __IO uint32_t REFC10 :1; + __IO uint32_t REFC11 :1; + __IO uint32_t REFC12 :1; + __IO uint32_t REFC13 :1; + __IO uint32_t REFC14 :1; + __IO uint32_t REFC15 :1; + __IO uint32_t NREF0 :1; + __IO uint32_t NREF1 :1; + __IO uint32_t NREF2 :1; + __IO uint32_t NREF3 :1; + __IO uint32_t NREF4 :1; + __IO uint32_t NREF5 :1; + __IO uint32_t NREF6 :1; + __IO uint32_t NREF7 :1; + __IO uint32_t RESERVED1 :8; + }; + }; +} stc_exbus_reftim_field_t; + +typedef struct stc_exbus_pwrdwn_field +{ + union { + struct { + __IO uint32_t PDC :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t PDC0 :1; + __IO uint32_t PDC1 :1; + __IO uint32_t PDC2 :1; + __IO uint32_t PDC3 :1; + __IO uint32_t PDC4 :1; + __IO uint32_t PDC5 :1; + __IO uint32_t PDC6 :1; + __IO uint32_t PDC7 :1; + __IO uint32_t PDC8 :1; + __IO uint32_t PDC9 :1; + __IO uint32_t PDC10 :1; + __IO uint32_t PDC11 :1; + __IO uint32_t PDC12 :1; + __IO uint32_t PDC13 :1; + __IO uint32_t PDC14 :1; + __IO uint32_t PDC15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_exbus_pwrdwn_field_t; + +typedef struct stc_exbus_sdtim_field +{ + union { + struct { + __IO uint32_t CL :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t TRC :4; + __IO uint32_t TRP :4; + __IO uint32_t TRCD :4; + __IO uint32_t TRAS :4; + __IO uint32_t TREFC :4; + __IO uint32_t TDPL :2; + __IO uint32_t RESERVED2 :5; + __IO uint32_t BOFF :1; + }; + struct { + __IO uint32_t CL0 :1; + __IO uint32_t CL1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t TRC0 :1; + __IO uint32_t TRC1 :1; + __IO uint32_t TRC2 :1; + __IO uint32_t TRC3 :1; + __IO uint32_t TRP0 :1; + __IO uint32_t TRP1 :1; + __IO uint32_t TRP2 :1; + __IO uint32_t TRP3 :1; + __IO uint32_t TRCD0 :1; + __IO uint32_t TRCD1 :1; + __IO uint32_t TRCD2 :1; + __IO uint32_t TRCD3 :1; + __IO uint32_t TRAS0 :1; + __IO uint32_t TRAS1 :1; + __IO uint32_t TRAS2 :1; + __IO uint32_t TRAS3 :1; + __IO uint32_t TREFC0 :1; + __IO uint32_t TREFC1 :1; + __IO uint32_t TREFC2 :1; + __IO uint32_t TREFC3 :1; + __IO uint32_t TDPL0 :1; + __IO uint32_t TDPL1 :1; + __IO uint32_t RESERVED3 :6; + }; + }; +} stc_exbus_sdtim_field_t; + +typedef struct stc_exbus_sdcmd_field +{ + union { + struct { + __IO uint32_t SDAD :16; + __IO uint32_t SDWE :1; + __IO uint32_t SDCAS :1; + __IO uint32_t SDRAS :1; + __IO uint32_t SDCS :1; + __IO uint32_t SDCKE :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PEND :1; + }; + struct { + __IO uint32_t SDAD0 :1; + __IO uint32_t SDAD1 :1; + __IO uint32_t SDAD2 :1; + __IO uint32_t SDAD3 :1; + __IO uint32_t SDAD4 :1; + __IO uint32_t SDAD5 :1; + __IO uint32_t SDAD6 :1; + __IO uint32_t SDAD7 :1; + __IO uint32_t SDAD8 :1; + __IO uint32_t SDAD9 :1; + __IO uint32_t SDAD10 :1; + __IO uint32_t SDAD11 :1; + __IO uint32_t SDAD12 :1; + __IO uint32_t SDAD13 :1; + __IO uint32_t SDAD14 :1; + __IO uint32_t SDAD15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_exbus_sdcmd_field_t; + +typedef struct stc_exbus_memcerr_field +{ + __IO uint32_t SFER :1; + __IO uint32_t SDER :1; + __IO uint32_t SFION :1; + __IO uint32_t SDION :1; + __IO uint32_t RESERVED0 :28; +} stc_exbus_memcerr_field_t; + +typedef struct stc_exbus_dclkr_field +{ + union { + struct { + __IO uint32_t MDIV :4; + __IO uint32_t MCLKON :1; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t MDIV0 :1; + __IO uint32_t MDIV1 :1; + __IO uint32_t MDIV2 :1; + __IO uint32_t MDIV3 :1; + __IO uint32_t RESERVED1 :28; + }; + }; +} stc_exbus_dclkr_field_t; + +typedef struct stc_exbus_est_field +{ + __IO uint32_t WERR :1; + __IO uint32_t RESERVED0 :31; +} stc_exbus_est_field_t; + +typedef struct stc_exbus_wead_field +{ + union { + struct { + __IO uint32_t ADDR :32; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t ADDR8 :1; + __IO uint32_t ADDR9 :1; + __IO uint32_t ADDR10 :1; + __IO uint32_t ADDR11 :1; + __IO uint32_t ADDR12 :1; + __IO uint32_t ADDR13 :1; + __IO uint32_t ADDR14 :1; + __IO uint32_t ADDR15 :1; + __IO uint32_t ADDR16 :1; + __IO uint32_t ADDR17 :1; + __IO uint32_t ADDR18 :1; + __IO uint32_t ADDR19 :1; + __IO uint32_t ADDR20 :1; + __IO uint32_t ADDR21 :1; + __IO uint32_t ADDR22 :1; + __IO uint32_t ADDR23 :1; + __IO uint32_t ADDR24 :1; + __IO uint32_t ADDR25 :1; + __IO uint32_t ADDR26 :1; + __IO uint32_t ADDR27 :1; + __IO uint32_t ADDR28 :1; + __IO uint32_t ADDR29 :1; + __IO uint32_t ADDR30 :1; + __IO uint32_t ADDR31 :1; + }; + }; +} stc_exbus_wead_field_t; + +typedef struct stc_exbus_esclr_field +{ + __IO uint32_t WERRCLR :1; + __IO uint32_t RESERVED0 :31; +} stc_exbus_esclr_field_t; + +typedef struct stc_exbus_amode_field +{ + __IO uint32_t WAEN :1; + __IO uint32_t RESERVED0 :31; +} stc_exbus_amode_field_t; + +/******************************************************************************* +* EXTI_MODULE +*******************************************************************************/ +typedef struct stc_exti_enir_field +{ + __IO uint32_t EN0 :1; + __IO uint32_t EN1 :1; + __IO uint32_t EN2 :1; + __IO uint32_t EN3 :1; + __IO uint32_t EN4 :1; + __IO uint32_t EN5 :1; + __IO uint32_t EN6 :1; + __IO uint32_t EN7 :1; + __IO uint32_t EN8 :1; + __IO uint32_t EN9 :1; + __IO uint32_t EN10 :1; + __IO uint32_t EN11 :1; + __IO uint32_t EN12 :1; + __IO uint32_t EN13 :1; + __IO uint32_t EN14 :1; + __IO uint32_t EN15 :1; + __IO uint32_t EN16 :1; + __IO uint32_t EN17 :1; + __IO uint32_t EN18 :1; + __IO uint32_t EN19 :1; + __IO uint32_t EN20 :1; + __IO uint32_t EN21 :1; + __IO uint32_t EN22 :1; + __IO uint32_t EN23 :1; + __IO uint32_t EN24 :1; + __IO uint32_t EN25 :1; + __IO uint32_t EN26 :1; + __IO uint32_t EN27 :1; + __IO uint32_t EN28 :1; + __IO uint32_t EN29 :1; + __IO uint32_t EN30 :1; + __IO uint32_t EN31 :1; +} stc_exti_enir_field_t; + +typedef struct stc_exti_eirr_field +{ + __IO uint32_t ER0 :1; + __IO uint32_t ER1 :1; + __IO uint32_t ER2 :1; + __IO uint32_t ER3 :1; + __IO uint32_t ER4 :1; + __IO uint32_t ER5 :1; + __IO uint32_t ER6 :1; + __IO uint32_t ER7 :1; + __IO uint32_t ER8 :1; + __IO uint32_t ER9 :1; + __IO uint32_t ER10 :1; + __IO uint32_t ER11 :1; + __IO uint32_t ER12 :1; + __IO uint32_t ER13 :1; + __IO uint32_t ER14 :1; + __IO uint32_t ER15 :1; + __IO uint32_t ER16 :1; + __IO uint32_t ER17 :1; + __IO uint32_t ER18 :1; + __IO uint32_t ER19 :1; + __IO uint32_t ER20 :1; + __IO uint32_t ER21 :1; + __IO uint32_t ER22 :1; + __IO uint32_t ER23 :1; + __IO uint32_t ER24 :1; + __IO uint32_t ER25 :1; + __IO uint32_t ER26 :1; + __IO uint32_t ER27 :1; + __IO uint32_t ER28 :1; + __IO uint32_t ER29 :1; + __IO uint32_t ER30 :1; + __IO uint32_t ER31 :1; +} stc_exti_eirr_field_t; + +typedef struct stc_exti_eicl_field +{ + __IO uint32_t ECL0 :1; + __IO uint32_t ECL1 :1; + __IO uint32_t ECL2 :1; + __IO uint32_t ECL3 :1; + __IO uint32_t ECL4 :1; + __IO uint32_t ECL5 :1; + __IO uint32_t ECL6 :1; + __IO uint32_t ECL7 :1; + __IO uint32_t ECL8 :1; + __IO uint32_t ECL9 :1; + __IO uint32_t ECL10 :1; + __IO uint32_t ECL11 :1; + __IO uint32_t ECL12 :1; + __IO uint32_t ECL13 :1; + __IO uint32_t ECL14 :1; + __IO uint32_t ECL15 :1; + __IO uint32_t ECL16 :1; + __IO uint32_t ECL17 :1; + __IO uint32_t ECL18 :1; + __IO uint32_t ECL19 :1; + __IO uint32_t ECL20 :1; + __IO uint32_t ECL21 :1; + __IO uint32_t ECL22 :1; + __IO uint32_t ECL23 :1; + __IO uint32_t ECL24 :1; + __IO uint32_t ECL25 :1; + __IO uint32_t ECL26 :1; + __IO uint32_t ECL27 :1; + __IO uint32_t ECL28 :1; + __IO uint32_t ECL29 :1; + __IO uint32_t ECL30 :1; + __IO uint32_t ECL31 :1; +} stc_exti_eicl_field_t; + +typedef struct stc_exti_elvr_field +{ + __IO uint32_t LA0 :1; + __IO uint32_t LB0 :1; + __IO uint32_t LA1 :1; + __IO uint32_t LB1 :1; + __IO uint32_t LA2 :1; + __IO uint32_t LB2 :1; + __IO uint32_t LA3 :1; + __IO uint32_t LB3 :1; + __IO uint32_t LA4 :1; + __IO uint32_t LB4 :1; + __IO uint32_t LA5 :1; + __IO uint32_t LB5 :1; + __IO uint32_t LA6 :1; + __IO uint32_t LB6 :1; + __IO uint32_t LA7 :1; + __IO uint32_t LB7 :1; + __IO uint32_t LA8 :1; + __IO uint32_t LB8 :1; + __IO uint32_t LA9 :1; + __IO uint32_t LB9 :1; + __IO uint32_t LA10 :1; + __IO uint32_t LB10 :1; + __IO uint32_t LA11 :1; + __IO uint32_t LB11 :1; + __IO uint32_t LA12 :1; + __IO uint32_t LB12 :1; + __IO uint32_t LA13 :1; + __IO uint32_t LB13 :1; + __IO uint32_t LA14 :1; + __IO uint32_t LB14 :1; + __IO uint32_t LA15 :1; + __IO uint32_t LB15 :1; +} stc_exti_elvr_field_t; + +typedef struct stc_exti_elvr1_field +{ + __IO uint32_t LA16 :1; + __IO uint32_t LB16 :1; + __IO uint32_t LA17 :1; + __IO uint32_t LB17 :1; + __IO uint32_t LA18 :1; + __IO uint32_t LB18 :1; + __IO uint32_t LA19 :1; + __IO uint32_t LB19 :1; + __IO uint32_t LA20 :1; + __IO uint32_t LB20 :1; + __IO uint32_t LA21 :1; + __IO uint32_t LB21 :1; + __IO uint32_t LA22 :1; + __IO uint32_t LB22 :1; + __IO uint32_t LA23 :1; + __IO uint32_t LB23 :1; + __IO uint32_t LA24 :1; + __IO uint32_t LB24 :1; + __IO uint32_t LA25 :1; + __IO uint32_t LB25 :1; + __IO uint32_t LA26 :1; + __IO uint32_t LB26 :1; + __IO uint32_t LA27 :1; + __IO uint32_t LB27 :1; + __IO uint32_t LA28 :1; + __IO uint32_t LB28 :1; + __IO uint32_t LA29 :1; + __IO uint32_t LB29 :1; + __IO uint32_t LA30 :1; + __IO uint32_t LB30 :1; + __IO uint32_t LA31 :1; + __IO uint32_t LB31 :1; +} stc_exti_elvr1_field_t; + +typedef struct stc_exti_nmirr_field +{ + __IO uint16_t NR :1; + __IO uint16_t RESERVED0 :15; +} stc_exti_nmirr_field_t; + +typedef struct stc_exti_nmicl_field +{ + __IO uint16_t NCL :1; + __IO uint16_t RESERVED0 :15; +} stc_exti_nmicl_field_t; + +/******************************************************************************* +* FLASH_IF_MODULE +*******************************************************************************/ +typedef struct stc_flash_if_faszr_field +{ + union { + struct { + __IO uint32_t ASZ :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t ASZ0 :1; + __IO uint32_t ASZ1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_flash_if_faszr_field_t; + +typedef struct stc_flash_if_frwtr_field +{ + union { + struct { + __IO uint32_t RWT :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t RWT0 :1; + __IO uint32_t RWT1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_flash_if_frwtr_field_t; + +typedef struct stc_flash_if_fstr_field +{ + __IO uint32_t RDY :1; + __IO uint32_t HNG :1; + __IO uint32_t ERR :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_fstr_field_t; + +typedef struct stc_flash_if_fsyndn_field +{ + union { + struct { + __IO uint32_t SD :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t SD0 :1; + __IO uint32_t SD1 :1; + __IO uint32_t SD2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_flash_if_fsyndn_field_t; + +typedef struct stc_flash_if_fbfcr_field +{ + __IO uint32_t BE :1; + __IO uint32_t BS :1; + __IO uint32_t RESERVED0 :30; +} stc_flash_if_fbfcr_field_t; + +typedef struct stc_flash_if_ficr_field +{ + __IO uint32_t RDYIE :1; + __IO uint32_t HNGIE :1; + __IO uint32_t ERRIE :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_ficr_field_t; + +typedef struct stc_flash_if_fisr_field +{ + __IO uint32_t RDYIF :1; + __IO uint32_t HNGIF :1; + __IO uint32_t ERRIF :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_fisr_field_t; + +typedef struct stc_flash_if_ficlr_field +{ + __IO uint32_t RDYIC :1; + __IO uint32_t HNGIC :1; + __IO uint32_t ERRIC :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_ficlr_field_t; + +typedef struct stc_flash_if_dfctrlr_field +{ + union { + struct { + __IO uint32_t DFE :1; + __IO uint32_t RME :1; + __IO uint32_t RESERVED0 :14; + __IO uint32_t WKEY :16; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t WKEY0 :1; + __IO uint32_t WKEY1 :1; + __IO uint32_t WKEY2 :1; + __IO uint32_t WKEY3 :1; + __IO uint32_t WKEY4 :1; + __IO uint32_t WKEY5 :1; + __IO uint32_t WKEY6 :1; + __IO uint32_t WKEY7 :1; + __IO uint32_t WKEY8 :1; + __IO uint32_t WKEY9 :1; + __IO uint32_t WKEY10 :1; + __IO uint32_t WKEY11 :1; + __IO uint32_t WKEY12 :1; + __IO uint32_t WKEY13 :1; + __IO uint32_t WKEY14 :1; + __IO uint32_t WKEY15 :1; + }; + }; +} stc_flash_if_dfctrlr_field_t; + +typedef struct stc_flash_if_crtrmm_field +{ + union { + struct { + __IO uint32_t TRMM :10; + __IO uint32_t RESERVED0 :6; + __IO uint32_t TTRMM :5; + __IO uint32_t RESERVED2 :11; + }; + struct { + __IO uint32_t TRMM0 :1; + __IO uint32_t TRMM1 :1; + __IO uint32_t TRMM2 :1; + __IO uint32_t TRMM3 :1; + __IO uint32_t TRMM4 :1; + __IO uint32_t TRMM5 :1; + __IO uint32_t TRMM6 :1; + __IO uint32_t TRMM7 :1; + __IO uint32_t TRMM8 :1; + __IO uint32_t TRMM9 :1; + __IO uint32_t RESERVED1 :6; + __IO uint32_t TTRMM0 :1; + __IO uint32_t TTRMM1 :1; + __IO uint32_t TTRMM2 :1; + __IO uint32_t TTRMM3 :1; + __IO uint32_t TTRMM4 :1; + __IO uint32_t RESERVED3 :11; + }; + }; +} stc_flash_if_crtrmm_field_t; + +typedef struct stc_flash_if_fgpdm1_field +{ + union { + struct { + __IO uint32_t GPD1 :32; + }; + struct { + __IO uint32_t GPD10 :1; + __IO uint32_t GPD11 :1; + __IO uint32_t GPD12 :1; + __IO uint32_t GPD13 :1; + __IO uint32_t GPD14 :1; + __IO uint32_t GPD15 :1; + __IO uint32_t GPD16 :1; + __IO uint32_t GPD17 :1; + __IO uint32_t GPD18 :1; + __IO uint32_t GPD19 :1; + __IO uint32_t GPD110 :1; + __IO uint32_t GPD111 :1; + __IO uint32_t GPD112 :1; + __IO uint32_t GPD113 :1; + __IO uint32_t GPD114 :1; + __IO uint32_t GPD115 :1; + __IO uint32_t GPD116 :1; + __IO uint32_t GPD117 :1; + __IO uint32_t GPD118 :1; + __IO uint32_t GPD119 :1; + __IO uint32_t GPD120 :1; + __IO uint32_t GPD121 :1; + __IO uint32_t GPD122 :1; + __IO uint32_t GPD123 :1; + __IO uint32_t GPD124 :1; + __IO uint32_t GPD125 :1; + __IO uint32_t GPD126 :1; + __IO uint32_t GPD127 :1; + __IO uint32_t GPD128 :1; + __IO uint32_t GPD129 :1; + __IO uint32_t GPD130 :1; + __IO uint32_t GPD131 :1; + }; + }; +} stc_flash_if_fgpdm1_field_t; + +typedef struct stc_flash_if_fgpdm2_field +{ + union { + struct { + __IO uint32_t GPD2 :32; + }; + struct { + __IO uint32_t GPD20 :1; + __IO uint32_t GPD21 :1; + __IO uint32_t GPD22 :1; + __IO uint32_t GPD23 :1; + __IO uint32_t GPD24 :1; + __IO uint32_t GPD25 :1; + __IO uint32_t GPD26 :1; + __IO uint32_t GPD27 :1; + __IO uint32_t GPD28 :1; + __IO uint32_t GPD29 :1; + __IO uint32_t GPD210 :1; + __IO uint32_t GPD211 :1; + __IO uint32_t GPD212 :1; + __IO uint32_t GPD213 :1; + __IO uint32_t GPD214 :1; + __IO uint32_t GPD215 :1; + __IO uint32_t GPD216 :1; + __IO uint32_t GPD217 :1; + __IO uint32_t GPD218 :1; + __IO uint32_t GPD219 :1; + __IO uint32_t GPD220 :1; + __IO uint32_t GPD221 :1; + __IO uint32_t GPD222 :1; + __IO uint32_t GPD223 :1; + __IO uint32_t GPD224 :1; + __IO uint32_t GPD225 :1; + __IO uint32_t GPD226 :1; + __IO uint32_t GPD227 :1; + __IO uint32_t GPD228 :1; + __IO uint32_t GPD229 :1; + __IO uint32_t GPD230 :1; + __IO uint32_t GPD231 :1; + }; + }; +} stc_flash_if_fgpdm2_field_t; + +typedef struct stc_flash_if_fgpdm3_field +{ + union { + struct { + __IO uint32_t GPD3 :32; + }; + struct { + __IO uint32_t GPD30 :1; + __IO uint32_t GPD31 :1; + __IO uint32_t GPD32 :1; + __IO uint32_t GPD33 :1; + __IO uint32_t GPD34 :1; + __IO uint32_t GPD35 :1; + __IO uint32_t GPD36 :1; + __IO uint32_t GPD37 :1; + __IO uint32_t GPD38 :1; + __IO uint32_t GPD39 :1; + __IO uint32_t GPD310 :1; + __IO uint32_t GPD311 :1; + __IO uint32_t GPD312 :1; + __IO uint32_t GPD313 :1; + __IO uint32_t GPD314 :1; + __IO uint32_t GPD315 :1; + __IO uint32_t GPD316 :1; + __IO uint32_t GPD317 :1; + __IO uint32_t GPD318 :1; + __IO uint32_t GPD319 :1; + __IO uint32_t GPD320 :1; + __IO uint32_t GPD321 :1; + __IO uint32_t GPD322 :1; + __IO uint32_t GPD323 :1; + __IO uint32_t GPD324 :1; + __IO uint32_t GPD325 :1; + __IO uint32_t GPD326 :1; + __IO uint32_t GPD327 :1; + __IO uint32_t GPD328 :1; + __IO uint32_t GPD329 :1; + __IO uint32_t GPD330 :1; + __IO uint32_t GPD331 :1; + }; + }; +} stc_flash_if_fgpdm3_field_t; + +typedef struct stc_flash_if_fgpdm4_field +{ + union { + struct { + __IO uint32_t GPD4 :32; + }; + struct { + __IO uint32_t GPD40 :1; + __IO uint32_t GPD41 :1; + __IO uint32_t GPD42 :1; + __IO uint32_t GPD43 :1; + __IO uint32_t GPD44 :1; + __IO uint32_t GPD45 :1; + __IO uint32_t GPD46 :1; + __IO uint32_t GPD47 :1; + __IO uint32_t GPD48 :1; + __IO uint32_t GPD49 :1; + __IO uint32_t GPD410 :1; + __IO uint32_t GPD411 :1; + __IO uint32_t GPD412 :1; + __IO uint32_t GPD413 :1; + __IO uint32_t GPD414 :1; + __IO uint32_t GPD415 :1; + __IO uint32_t GPD416 :1; + __IO uint32_t GPD417 :1; + __IO uint32_t GPD418 :1; + __IO uint32_t GPD419 :1; + __IO uint32_t GPD420 :1; + __IO uint32_t GPD421 :1; + __IO uint32_t GPD422 :1; + __IO uint32_t GPD423 :1; + __IO uint32_t GPD424 :1; + __IO uint32_t GPD425 :1; + __IO uint32_t GPD426 :1; + __IO uint32_t GPD427 :1; + __IO uint32_t GPD428 :1; + __IO uint32_t GPD429 :1; + __IO uint32_t GPD430 :1; + __IO uint32_t GPD431 :1; + }; + }; +} stc_flash_if_fgpdm4_field_t; + +/******************************************************************************* +* GPIO_MODULE +*******************************************************************************/ +typedef struct stc_gpio_pfr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pfr0_field_t; + +typedef struct stc_gpio_pfr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfr1_field_t; + +typedef struct stc_gpio_pfr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pfr2_field_t; + +typedef struct stc_gpio_pfr3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pfr3_field_t; + +typedef struct stc_gpio_pfr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_pfr4_field_t; + +typedef struct stc_gpio_pfr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pfr6_field_t; + +typedef struct stc_gpio_pfr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pfr7_field_t; + +typedef struct stc_gpio_pfr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pfr8_field_t; + +typedef struct stc_gpio_pfra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfra_field_t; + +typedef struct stc_gpio_pfrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfrc_field_t; + +typedef struct stc_gpio_pfrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pfrd_field_t; + +typedef struct stc_gpio_pfre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pfre_field_t; + +typedef struct stc_gpio_pcr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pcr0_field_t; + +typedef struct stc_gpio_pcr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcr1_field_t; + +typedef struct stc_gpio_pcr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pcr2_field_t; + +typedef struct stc_gpio_pcr3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pcr3_field_t; + +typedef struct stc_gpio_pcr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_pcr4_field_t; + +typedef struct stc_gpio_pcr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pcr6_field_t; + +typedef struct stc_gpio_pcr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pcr7_field_t; + +typedef struct stc_gpio_pcra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcra_field_t; + +typedef struct stc_gpio_pcrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcrc_field_t; + +typedef struct stc_gpio_pcrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pcrd_field_t; + +typedef struct stc_gpio_pcre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pcre_field_t; + +typedef struct stc_gpio_ddr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_ddr0_field_t; + +typedef struct stc_gpio_ddr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddr1_field_t; + +typedef struct stc_gpio_ddr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_ddr2_field_t; + +typedef struct stc_gpio_ddr3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_ddr3_field_t; + +typedef struct stc_gpio_ddr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_ddr4_field_t; + +typedef struct stc_gpio_ddr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_ddr6_field_t; + +typedef struct stc_gpio_ddr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_ddr7_field_t; + +typedef struct stc_gpio_ddr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_ddr8_field_t; + +typedef struct stc_gpio_ddra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddra_field_t; + +typedef struct stc_gpio_ddrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddrc_field_t; + +typedef struct stc_gpio_ddrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_ddrd_field_t; + +typedef struct stc_gpio_ddre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_ddre_field_t; + +typedef struct stc_gpio_pdir0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pdir0_field_t; + +typedef struct stc_gpio_pdir1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdir1_field_t; + +typedef struct stc_gpio_pdir2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pdir2_field_t; + +typedef struct stc_gpio_pdir3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pdir3_field_t; + +typedef struct stc_gpio_pdir4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_pdir4_field_t; + +typedef struct stc_gpio_pdir6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pdir6_field_t; + +typedef struct stc_gpio_pdir7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdir7_field_t; + +typedef struct stc_gpio_pdir8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pdir8_field_t; + +typedef struct stc_gpio_pdira_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdira_field_t; + +typedef struct stc_gpio_pdirc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdirc_field_t; + +typedef struct stc_gpio_pdird_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pdird_field_t; + +typedef struct stc_gpio_pdire_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pdire_field_t; + +typedef struct stc_gpio_pdor0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pdor0_field_t; + +typedef struct stc_gpio_pdor1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdor1_field_t; + +typedef struct stc_gpio_pdor2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pdor2_field_t; + +typedef struct stc_gpio_pdor3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pdor3_field_t; + +typedef struct stc_gpio_pdor4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_pdor4_field_t; + +typedef struct stc_gpio_pdor6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pdor6_field_t; + +typedef struct stc_gpio_pdor7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdor7_field_t; + +typedef struct stc_gpio_pdor8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pdor8_field_t; + +typedef struct stc_gpio_pdora_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdora_field_t; + +typedef struct stc_gpio_pdorc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdorc_field_t; + +typedef struct stc_gpio_pdord_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pdord_field_t; + +typedef struct stc_gpio_pdore_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pdore_field_t; + +typedef struct stc_gpio_ade_field +{ + __IO uint32_t AN00 :1; + __IO uint32_t AN01 :1; + __IO uint32_t AN02 :1; + __IO uint32_t AN03 :1; + __IO uint32_t AN04 :1; + __IO uint32_t AN05 :1; + __IO uint32_t AN06 :1; + __IO uint32_t AN07 :1; + __IO uint32_t AN08 :1; + __IO uint32_t AN09 :1; + __IO uint32_t AN10 :1; + __IO uint32_t AN11 :1; + __IO uint32_t AN12 :1; + __IO uint32_t AN13 :1; + __IO uint32_t AN14 :1; + __IO uint32_t AN15 :1; + __IO uint32_t RESERVED0 :8; + __IO uint32_t AN24 :1; + __IO uint32_t AN25 :1; + __IO uint32_t AN26 :1; + __IO uint32_t AN27 :1; + __IO uint32_t AN28 :1; + __IO uint32_t AN29 :1; + __IO uint32_t AN30 :1; + __IO uint32_t AN31 :1; +} stc_gpio_ade_field_t; + +typedef struct stc_gpio_spsr_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t MAINXC :2; + __IO uint32_t USB0C :1; + __IO uint32_t USB1C :1; + __IO uint32_t RESERVED2 :26; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t MAINXC0 :1; + __IO uint32_t MAINXC1 :1; + __IO uint32_t RESERVED3 :28; + }; + }; +} stc_gpio_spsr_field_t; + +typedef struct stc_gpio_epfr00_field +{ + union { + struct { + __IO uint32_t NMIS :1; + __IO uint32_t CROUTE :2; + __IO uint32_t RESERVED1 :1; + __IO uint32_t RTCCOE :2; + __IO uint32_t SUBOUTE :2; + __IO uint32_t RESERVED3 :1; + __IO uint32_t USBP0E :1; + __IO uint32_t RESERVED4 :3; + __IO uint32_t USBP1E :1; + __IO uint32_t RESERVED5 :2; + __IO uint32_t JTAGEN0B :1; + __IO uint32_t JTAGEN1S :1; + __IO uint32_t RESERVED6 :6; + __IO uint32_t TRC0E :1; + __IO uint32_t TRC1E :1; + __IO uint32_t TRC2E :1; + __IO uint32_t TRC3E :1; + __IO uint32_t RESERVED7 :4; + }; + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t CROUTE0 :1; + __IO uint32_t CROUTE1 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t RTCCOE0 :1; + __IO uint32_t RTCCOE1 :1; + __IO uint32_t SUBOUTE0 :1; + __IO uint32_t SUBOUTE1 :1; + __IO uint32_t RESERVED8 :24; + }; + }; +} stc_gpio_epfr00_field_t; + +typedef struct stc_gpio_epfr01_field +{ + union { + struct { + __IO uint32_t RTO00E :2; + __IO uint32_t RTO01E :2; + __IO uint32_t RTO02E :2; + __IO uint32_t RTO03E :2; + __IO uint32_t RTO04E :2; + __IO uint32_t RTO05E :2; + __IO uint32_t DTTI0C :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t DTTI0S :2; + __IO uint32_t FRCK0S :2; + __IO uint32_t IC00S :3; + __IO uint32_t IC01S :3; + __IO uint32_t IC02S :3; + __IO uint32_t IC03S :3; + }; + struct { + __IO uint32_t RTO00E0 :1; + __IO uint32_t RTO00E1 :1; + __IO uint32_t RTO01E0 :1; + __IO uint32_t RTO01E1 :1; + __IO uint32_t RTO02E0 :1; + __IO uint32_t RTO02E1 :1; + __IO uint32_t RTO03E0 :1; + __IO uint32_t RTO03E1 :1; + __IO uint32_t RTO04E0 :1; + __IO uint32_t RTO04E1 :1; + __IO uint32_t RTO05E0 :1; + __IO uint32_t RTO05E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t DTTI0S0 :1; + __IO uint32_t DTTI0S1 :1; + __IO uint32_t FRCK0S0 :1; + __IO uint32_t FRCK0S1 :1; + __IO uint32_t IC00S0 :1; + __IO uint32_t IC00S1 :1; + __IO uint32_t IC00S2 :1; + __IO uint32_t IC01S0 :1; + __IO uint32_t IC01S1 :1; + __IO uint32_t IC01S2 :1; + __IO uint32_t IC02S0 :1; + __IO uint32_t IC02S1 :1; + __IO uint32_t IC02S2 :1; + __IO uint32_t IC03S0 :1; + __IO uint32_t IC03S1 :1; + __IO uint32_t IC03S2 :1; + }; + }; +} stc_gpio_epfr01_field_t; + +typedef struct stc_gpio_epfr02_field +{ + union { + struct { + __IO uint32_t RTO10E :2; + __IO uint32_t RTO11E :2; + __IO uint32_t RTO12E :2; + __IO uint32_t RTO13E :2; + __IO uint32_t RTO14E :2; + __IO uint32_t RTO15E :2; + __IO uint32_t DTTI1C :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t DTTI1S :2; + __IO uint32_t FRCK1S :2; + __IO uint32_t IC10S :3; + __IO uint32_t IC11S :3; + __IO uint32_t IC12S :3; + __IO uint32_t IC13S :3; + }; + struct { + __IO uint32_t RTO10E0 :1; + __IO uint32_t RTO10E1 :1; + __IO uint32_t RTO11E0 :1; + __IO uint32_t RTO11E1 :1; + __IO uint32_t RTO12E0 :1; + __IO uint32_t RTO12E1 :1; + __IO uint32_t RTO13E0 :1; + __IO uint32_t RTO13E1 :1; + __IO uint32_t RTO14E0 :1; + __IO uint32_t RTO14E1 :1; + __IO uint32_t RTO15E0 :1; + __IO uint32_t RTO15E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t DTTI1S0 :1; + __IO uint32_t DTTI1S1 :1; + __IO uint32_t FRCK1S0 :1; + __IO uint32_t FRCK1S1 :1; + __IO uint32_t IC10S0 :1; + __IO uint32_t IC10S1 :1; + __IO uint32_t IC10S2 :1; + __IO uint32_t IC11S0 :1; + __IO uint32_t IC11S1 :1; + __IO uint32_t IC11S2 :1; + __IO uint32_t IC12S0 :1; + __IO uint32_t IC12S1 :1; + __IO uint32_t IC12S2 :1; + __IO uint32_t IC13S0 :1; + __IO uint32_t IC13S1 :1; + __IO uint32_t IC13S2 :1; + }; + }; +} stc_gpio_epfr02_field_t; + +typedef struct stc_gpio_epfr03_field +{ + union { + struct { + __IO uint32_t RTO20E :2; + __IO uint32_t RTO21E :2; + __IO uint32_t RTO22E :2; + __IO uint32_t RTO23E :2; + __IO uint32_t RTO24E :2; + __IO uint32_t RTO25E :2; + __IO uint32_t DTTI2C :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t DTTI2S :2; + __IO uint32_t FRCK2S :2; + __IO uint32_t IC20S :3; + __IO uint32_t IC21S :3; + __IO uint32_t IC22S :3; + __IO uint32_t IC23S :3; + }; + struct { + __IO uint32_t RTO20E0 :1; + __IO uint32_t RTO20E1 :1; + __IO uint32_t RTO21E0 :1; + __IO uint32_t RTO21E1 :1; + __IO uint32_t RTO22E0 :1; + __IO uint32_t RTO22E1 :1; + __IO uint32_t RTO23E0 :1; + __IO uint32_t RTO23E1 :1; + __IO uint32_t RTO24E0 :1; + __IO uint32_t RTO24E1 :1; + __IO uint32_t RTO25E0 :1; + __IO uint32_t RTO25E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t DTTI2S0 :1; + __IO uint32_t DTTI2S1 :1; + __IO uint32_t FRCK2S0 :1; + __IO uint32_t FRCK2S1 :1; + __IO uint32_t IC20S0 :1; + __IO uint32_t IC20S1 :1; + __IO uint32_t IC20S2 :1; + __IO uint32_t IC21S0 :1; + __IO uint32_t IC21S1 :1; + __IO uint32_t IC21S2 :1; + __IO uint32_t IC22S0 :1; + __IO uint32_t IC22S1 :1; + __IO uint32_t IC22S2 :1; + __IO uint32_t IC23S0 :1; + __IO uint32_t IC23S1 :1; + __IO uint32_t IC23S2 :1; + }; + }; +} stc_gpio_epfr03_field_t; + +typedef struct stc_gpio_epfr04_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA0E :2; + __IO uint32_t TIOB0S :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t TIOA1S :2; + __IO uint32_t TIOA1E :2; + __IO uint32_t TIOB1S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA2E :2; + __IO uint32_t TIOB2S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA3S :2; + __IO uint32_t TIOA3E :2; + __IO uint32_t TIOB3S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA0E0 :1; + __IO uint32_t TIOA0E1 :1; + __IO uint32_t TIOB0S0 :1; + __IO uint32_t TIOB0S1 :1; + __IO uint32_t TIOB0S2 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t TIOA1S0 :1; + __IO uint32_t TIOA1S1 :1; + __IO uint32_t TIOA1E0 :1; + __IO uint32_t TIOA1E1 :1; + __IO uint32_t TIOB1S0 :1; + __IO uint32_t TIOB1S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA2E0 :1; + __IO uint32_t TIOA2E1 :1; + __IO uint32_t TIOB2S0 :1; + __IO uint32_t TIOB2S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA3S0 :1; + __IO uint32_t TIOA3S1 :1; + __IO uint32_t TIOA3E0 :1; + __IO uint32_t TIOA3E1 :1; + __IO uint32_t TIOB3S0 :1; + __IO uint32_t TIOB3S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr04_field_t; + +typedef struct stc_gpio_epfr05_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA4E :2; + __IO uint32_t TIOB4S :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TIOA5S :2; + __IO uint32_t TIOA5E :2; + __IO uint32_t TIOB5S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA6E :2; + __IO uint32_t TIOB6S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA7S :2; + __IO uint32_t TIOA7E :2; + __IO uint32_t TIOB7S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA4E0 :1; + __IO uint32_t TIOA4E1 :1; + __IO uint32_t TIOB4S0 :1; + __IO uint32_t TIOB4S1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TIOA5S0 :1; + __IO uint32_t TIOA5S1 :1; + __IO uint32_t TIOA5E0 :1; + __IO uint32_t TIOA5E1 :1; + __IO uint32_t TIOB5S0 :1; + __IO uint32_t TIOB5S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA6E0 :1; + __IO uint32_t TIOA6E1 :1; + __IO uint32_t TIOB6S0 :1; + __IO uint32_t TIOB6S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA7S0 :1; + __IO uint32_t TIOA7S1 :1; + __IO uint32_t TIOA7E0 :1; + __IO uint32_t TIOA7E1 :1; + __IO uint32_t TIOB7S0 :1; + __IO uint32_t TIOB7S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr05_field_t; + +typedef struct stc_gpio_epfr06_field +{ + union { + struct { + __IO uint32_t EINT00S :2; + __IO uint32_t EINT01S :2; + __IO uint32_t EINT02S :2; + __IO uint32_t EINT03S :2; + __IO uint32_t EINT04S :2; + __IO uint32_t EINT05S :2; + __IO uint32_t EINT06S :2; + __IO uint32_t EINT07S :2; + __IO uint32_t EINT08S :2; + __IO uint32_t EINT09S :2; + __IO uint32_t EINT10S :2; + __IO uint32_t EINT11S :2; + __IO uint32_t EINT12S :2; + __IO uint32_t EINT13S :2; + __IO uint32_t EINT14S :2; + __IO uint32_t EINT15S :2; + }; + struct { + __IO uint32_t EINT00S0 :1; + __IO uint32_t EINT00S1 :1; + __IO uint32_t EINT01S0 :1; + __IO uint32_t EINT01S1 :1; + __IO uint32_t EINT02S0 :1; + __IO uint32_t EINT02S1 :1; + __IO uint32_t EINT03S0 :1; + __IO uint32_t EINT03S1 :1; + __IO uint32_t EINT04S0 :1; + __IO uint32_t EINT04S1 :1; + __IO uint32_t EINT05S0 :1; + __IO uint32_t EINT05S1 :1; + __IO uint32_t EINT06S0 :1; + __IO uint32_t EINT06S1 :1; + __IO uint32_t EINT07S0 :1; + __IO uint32_t EINT07S1 :1; + __IO uint32_t EINT08S0 :1; + __IO uint32_t EINT08S1 :1; + __IO uint32_t EINT09S0 :1; + __IO uint32_t EINT09S1 :1; + __IO uint32_t EINT10S0 :1; + __IO uint32_t EINT10S1 :1; + __IO uint32_t EINT11S0 :1; + __IO uint32_t EINT11S1 :1; + __IO uint32_t EINT12S0 :1; + __IO uint32_t EINT12S1 :1; + __IO uint32_t EINT13S0 :1; + __IO uint32_t EINT13S1 :1; + __IO uint32_t EINT14S0 :1; + __IO uint32_t EINT14S1 :1; + __IO uint32_t EINT15S0 :1; + __IO uint32_t EINT15S1 :1; + }; + }; +} stc_gpio_epfr06_field_t; + +typedef struct stc_gpio_epfr07_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t SIN0S :2; + __IO uint32_t SOT0B :2; + __IO uint32_t SCK0B :2; + __IO uint32_t SIN1S :2; + __IO uint32_t SOT1B :2; + __IO uint32_t SCK1B :2; + __IO uint32_t SIN2S :2; + __IO uint32_t SOT2B :2; + __IO uint32_t SCK2B :2; + __IO uint32_t SIN3S :2; + __IO uint32_t SOT3B :2; + __IO uint32_t SCK3B :2; + __IO uint32_t RESERVED2 :4; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t SIN0S0 :1; + __IO uint32_t SIN0S1 :1; + __IO uint32_t SOT0B0 :1; + __IO uint32_t SOT0B1 :1; + __IO uint32_t SCK0B0 :1; + __IO uint32_t SCK0B1 :1; + __IO uint32_t SIN1S0 :1; + __IO uint32_t SIN1S1 :1; + __IO uint32_t SOT1B0 :1; + __IO uint32_t SOT1B1 :1; + __IO uint32_t SCK1B0 :1; + __IO uint32_t SCK1B1 :1; + __IO uint32_t SIN2S0 :1; + __IO uint32_t SIN2S1 :1; + __IO uint32_t SOT2B0 :1; + __IO uint32_t SOT2B1 :1; + __IO uint32_t SCK2B0 :1; + __IO uint32_t SCK2B1 :1; + __IO uint32_t SIN3S0 :1; + __IO uint32_t SIN3S1 :1; + __IO uint32_t SOT3B0 :1; + __IO uint32_t SOT3B1 :1; + __IO uint32_t SCK3B0 :1; + __IO uint32_t SCK3B1 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_gpio_epfr07_field_t; + +typedef struct stc_gpio_epfr08_field +{ + union { + struct { + __IO uint32_t RTS4E :2; + __IO uint32_t CTS4S :2; + __IO uint32_t SIN4S :2; + __IO uint32_t SOT4B :2; + __IO uint32_t SCK4B :2; + __IO uint32_t SIN5S :2; + __IO uint32_t SOT5B :2; + __IO uint32_t SCK5B :2; + __IO uint32_t SIN6S :2; + __IO uint32_t SOT6B :2; + __IO uint32_t SCK6B :2; + __IO uint32_t SIN7S :2; + __IO uint32_t SOT7B :2; + __IO uint32_t SCK7B :2; + __IO uint32_t RTS5E :2; + __IO uint32_t CTS5S :2; + }; + struct { + __IO uint32_t RTS4E0 :1; + __IO uint32_t RTS4E1 :1; + __IO uint32_t CTS4S0 :1; + __IO uint32_t CTS4S1 :1; + __IO uint32_t SIN4S0 :1; + __IO uint32_t SIN4S1 :1; + __IO uint32_t SOT4B0 :1; + __IO uint32_t SOT4B1 :1; + __IO uint32_t SCK4B0 :1; + __IO uint32_t SCK4B1 :1; + __IO uint32_t SIN5S0 :1; + __IO uint32_t SIN5S1 :1; + __IO uint32_t SOT5B0 :1; + __IO uint32_t SOT5B1 :1; + __IO uint32_t SCK5B0 :1; + __IO uint32_t SCK5B1 :1; + __IO uint32_t SIN6S0 :1; + __IO uint32_t SIN6S1 :1; + __IO uint32_t SOT6B0 :1; + __IO uint32_t SOT6B1 :1; + __IO uint32_t SCK6B0 :1; + __IO uint32_t SCK6B1 :1; + __IO uint32_t SIN7S0 :1; + __IO uint32_t SIN7S1 :1; + __IO uint32_t SOT7B0 :1; + __IO uint32_t SOT7B1 :1; + __IO uint32_t SCK7B0 :1; + __IO uint32_t SCK7B1 :1; + __IO uint32_t RTS5E0 :1; + __IO uint32_t RTS5E1 :1; + __IO uint32_t CTS5S0 :1; + __IO uint32_t CTS5S1 :1; + }; + }; +} stc_gpio_epfr08_field_t; + +typedef struct stc_gpio_epfr09_field +{ + union { + struct { + __IO uint32_t QAIN0S :2; + __IO uint32_t QBIN0S :2; + __IO uint32_t QZIN0S :2; + __IO uint32_t QAIN1S :2; + __IO uint32_t QBIN1S :2; + __IO uint32_t QZIN1S :2; + __IO uint32_t ADTRG0S :4; + __IO uint32_t ADTRG1S :4; + __IO uint32_t ADTRG2S :4; + __IO uint32_t CRX0S :2; + __IO uint32_t CTX0E :2; + __IO uint32_t CRX1S :2; + __IO uint32_t CTX1E :2; + }; + struct { + __IO uint32_t QAIN0S0 :1; + __IO uint32_t QAIN0S1 :1; + __IO uint32_t QBIN0S0 :1; + __IO uint32_t QBIN0S1 :1; + __IO uint32_t QZIN0S0 :1; + __IO uint32_t QZIN0S1 :1; + __IO uint32_t QAIN1S0 :1; + __IO uint32_t QAIN1S1 :1; + __IO uint32_t QBIN1S0 :1; + __IO uint32_t QBIN1S1 :1; + __IO uint32_t QZIN1S0 :1; + __IO uint32_t QZIN1S1 :1; + __IO uint32_t ADTRG0S0 :1; + __IO uint32_t ADTRG0S1 :1; + __IO uint32_t ADTRG0S2 :1; + __IO uint32_t ADTRG0S3 :1; + __IO uint32_t ADTRG1S0 :1; + __IO uint32_t ADTRG1S1 :1; + __IO uint32_t ADTRG1S2 :1; + __IO uint32_t ADTRG1S3 :1; + __IO uint32_t ADTRG2S0 :1; + __IO uint32_t ADTRG2S1 :1; + __IO uint32_t ADTRG2S2 :1; + __IO uint32_t ADTRG2S3 :1; + __IO uint32_t CRX0S0 :1; + __IO uint32_t CRX0S1 :1; + __IO uint32_t CTX0E0 :1; + __IO uint32_t CTX0E1 :1; + __IO uint32_t CRX1S0 :1; + __IO uint32_t CRX1S1 :1; + __IO uint32_t CTX1E0 :1; + __IO uint32_t CTX1E1 :1; + }; + }; +} stc_gpio_epfr09_field_t; + +typedef struct stc_gpio_epfr10_field +{ + __IO uint32_t UEDEFB :1; + __IO uint32_t UEDTHB :1; + __IO uint32_t UECLKE :1; + __IO uint32_t UEWEXE :1; + __IO uint32_t UEDQME :1; + __IO uint32_t UEOEXE :1; + __IO uint32_t UEFLSE :1; + __IO uint32_t UECS1E :1; + __IO uint32_t UECS2E :1; + __IO uint32_t UECS3E :1; + __IO uint32_t UECS4E :1; + __IO uint32_t UECS5E :1; + __IO uint32_t UECS6E :1; + __IO uint32_t UECS7E :1; + __IO uint32_t UEAOOE :1; + __IO uint32_t UEA08E :1; + __IO uint32_t UEA09E :1; + __IO uint32_t UEA10E :1; + __IO uint32_t UEA11E :1; + __IO uint32_t UEA12E :1; + __IO uint32_t UEA13E :1; + __IO uint32_t UEA14E :1; + __IO uint32_t UEA15E :1; + __IO uint32_t UEA16E :1; + __IO uint32_t UEA17E :1; + __IO uint32_t UEA18E :1; + __IO uint32_t UEA19E :1; + __IO uint32_t UEA20E :1; + __IO uint32_t UEA21E :1; + __IO uint32_t UEA22E :1; + __IO uint32_t UEA23E :1; + __IO uint32_t UEA24E :1; +} stc_gpio_epfr10_field_t; + +typedef struct stc_gpio_epfr11_field +{ + __IO uint32_t UEALEE :1; + __IO uint32_t UECS0E :1; + __IO uint32_t UEA01E :1; + __IO uint32_t UEA02E :1; + __IO uint32_t UEA03E :1; + __IO uint32_t UEA04E :1; + __IO uint32_t UEA05E :1; + __IO uint32_t UEA06E :1; + __IO uint32_t UEA07E :1; + __IO uint32_t UED00B :1; + __IO uint32_t UED01B :1; + __IO uint32_t UED02B :1; + __IO uint32_t UED03B :1; + __IO uint32_t UED04B :1; + __IO uint32_t UED05B :1; + __IO uint32_t UED06B :1; + __IO uint32_t UED07B :1; + __IO uint32_t UED08B :1; + __IO uint32_t UED09B :1; + __IO uint32_t UED10B :1; + __IO uint32_t UED11B :1; + __IO uint32_t UED12B :1; + __IO uint32_t UED13B :1; + __IO uint32_t UED14B :1; + __IO uint32_t UED15B :1; + __IO uint32_t UERLC :1; + __IO uint32_t RESERVED0 :6; +} stc_gpio_epfr11_field_t; + +typedef struct stc_gpio_epfr12_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA8E :2; + __IO uint32_t TIOB8S :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TIOA9S :2; + __IO uint32_t TIOA9E :2; + __IO uint32_t TIOB9S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA10E :2; + __IO uint32_t TIOB10S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA11S :2; + __IO uint32_t TIOA11E :2; + __IO uint32_t TIOB11S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA8E0 :1; + __IO uint32_t TIOA8E1 :1; + __IO uint32_t TIOB8S0 :1; + __IO uint32_t TIOB8S1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TIOA9S0 :1; + __IO uint32_t TIOA9S1 :1; + __IO uint32_t TIOA9E0 :1; + __IO uint32_t TIOA9E1 :1; + __IO uint32_t TIOB9S0 :1; + __IO uint32_t TIOB9S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA10E0 :1; + __IO uint32_t TIOA10E1 :1; + __IO uint32_t TIOB10S0 :1; + __IO uint32_t TIOB10S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA11S0 :1; + __IO uint32_t TIOA11S1 :1; + __IO uint32_t TIOA11E0 :1; + __IO uint32_t TIOA11E1 :1; + __IO uint32_t TIOB11S0 :1; + __IO uint32_t TIOB11S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr12_field_t; + +typedef struct stc_gpio_epfr13_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA12E :2; + __IO uint32_t TIOB12S :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TIOA13S :2; + __IO uint32_t TIOA13E :2; + __IO uint32_t TIOB13S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA14E :2; + __IO uint32_t TIOB14S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA15S :2; + __IO uint32_t TIOA15E :2; + __IO uint32_t TIOB15S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA12E0 :1; + __IO uint32_t TIOA12E1 :1; + __IO uint32_t TIOB12S0 :1; + __IO uint32_t TIOB12S1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TIOA13S0 :1; + __IO uint32_t TIOA13S1 :1; + __IO uint32_t TIOA13E0 :1; + __IO uint32_t TIOA13E1 :1; + __IO uint32_t TIOB13S0 :1; + __IO uint32_t TIOB13S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA14E0 :1; + __IO uint32_t TIOA14E1 :1; + __IO uint32_t TIOB14S0 :1; + __IO uint32_t TIOB14S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA15S0 :1; + __IO uint32_t TIOA15S1 :1; + __IO uint32_t TIOA15E0 :1; + __IO uint32_t TIOA15E1 :1; + __IO uint32_t TIOB15S0 :1; + __IO uint32_t TIOB15S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr13_field_t; + +typedef struct stc_gpio_epfr14_field +{ + union { + struct { + __IO uint32_t QAIN2S :2; + __IO uint32_t QBIN2S :2; + __IO uint32_t QZIN2S :2; + __IO uint32_t RESERVED0 :12; + __IO uint32_t E_TD0E :1; + __IO uint32_t E_TD1E :1; + __IO uint32_t E_TE0E :1; + __IO uint32_t E_TE1E :1; + __IO uint32_t E_MC0E :1; + __IO uint32_t E_MC1B :1; + __IO uint32_t E_MD0B :1; + __IO uint32_t E_MD1B :1; + __IO uint32_t E_CKE :1; + __IO uint32_t E_PSE :1; + __IO uint32_t E_SPLC :2; + __IO uint32_t RESERVED2 :2; + }; + struct { + __IO uint32_t QAIN2S0 :1; + __IO uint32_t QAIN2S1 :1; + __IO uint32_t QBIN2S0 :1; + __IO uint32_t QBIN2S1 :1; + __IO uint32_t QZIN2S0 :1; + __IO uint32_t QZIN2S1 :1; + __IO uint32_t RESERVED1 :22; + __IO uint32_t E_SPLC0 :1; + __IO uint32_t E_SPLC1 :1; + __IO uint32_t RESERVED3 :2; + }; + }; +} stc_gpio_epfr14_field_t; + +typedef struct stc_gpio_epfr15_field +{ + union { + struct { + __IO uint32_t EINT16S :2; + __IO uint32_t EINT17S :2; + __IO uint32_t EINT18S :2; + __IO uint32_t EINT19S :2; + __IO uint32_t EINT20S :2; + __IO uint32_t EINT21S :2; + __IO uint32_t EINT22S :2; + __IO uint32_t EINT23S :2; + __IO uint32_t EINT24S :2; + __IO uint32_t EINT25S :2; + __IO uint32_t EINT26S :2; + __IO uint32_t EINT27S :2; + __IO uint32_t EINT28S :2; + __IO uint32_t EINT29S :2; + __IO uint32_t EINT30S :2; + __IO uint32_t EINT31S :2; + }; + struct { + __IO uint32_t EINT16S0 :1; + __IO uint32_t EINT16S1 :1; + __IO uint32_t EINT17S0 :1; + __IO uint32_t EINT17S1 :1; + __IO uint32_t EINT18S0 :1; + __IO uint32_t EINT18S1 :1; + __IO uint32_t EINT19S0 :1; + __IO uint32_t EINT19S1 :1; + __IO uint32_t EINT20S0 :1; + __IO uint32_t EINT20S1 :1; + __IO uint32_t EINT21S0 :1; + __IO uint32_t EINT21S1 :1; + __IO uint32_t EINT22S0 :1; + __IO uint32_t EINT22S1 :1; + __IO uint32_t EINT23S0 :1; + __IO uint32_t EINT23S1 :1; + __IO uint32_t EINT24S0 :1; + __IO uint32_t EINT24S1 :1; + __IO uint32_t EINT25S0 :1; + __IO uint32_t EINT25S1 :1; + __IO uint32_t EINT26S0 :1; + __IO uint32_t EINT26S1 :1; + __IO uint32_t EINT27S0 :1; + __IO uint32_t EINT27S1 :1; + __IO uint32_t EINT28S0 :1; + __IO uint32_t EINT28S1 :1; + __IO uint32_t EINT29S0 :1; + __IO uint32_t EINT29S1 :1; + __IO uint32_t EINT30S0 :1; + __IO uint32_t EINT30S1 :1; + __IO uint32_t EINT31S0 :1; + __IO uint32_t EINT31S1 :1; + }; + }; +} stc_gpio_epfr15_field_t; + +typedef struct stc_gpio_epfr16_field +{ + union { + struct { + __IO uint32_t SCS6B :2; + __IO uint32_t SCS7B :2; + __IO uint32_t SIN8S :2; + __IO uint32_t SOT8B :2; + __IO uint32_t SCK8B :2; + __IO uint32_t SIN9S :2; + __IO uint32_t SOT9B :2; + __IO uint32_t SCK9B :2; + __IO uint32_t SIN10S :2; + __IO uint32_t SOT10B :2; + __IO uint32_t SCK10B :2; + __IO uint32_t SIN11S :2; + __IO uint32_t SOT11B :2; + __IO uint32_t SCK11B :2; + __IO uint32_t SFMPAC :1; + __IO uint32_t SFMPBC :1; + __IO uint32_t RESERVED0 :2; + }; + struct { + __IO uint32_t SCS6B0 :1; + __IO uint32_t SCS6B1 :1; + __IO uint32_t SCS7B0 :1; + __IO uint32_t SCS7B1 :1; + __IO uint32_t SIN8S0 :1; + __IO uint32_t SIN8S1 :1; + __IO uint32_t SOT8B0 :1; + __IO uint32_t SOT8B1 :1; + __IO uint32_t SCK8B0 :1; + __IO uint32_t SCK8B1 :1; + __IO uint32_t SIN9S0 :1; + __IO uint32_t SIN9S1 :1; + __IO uint32_t SOT9B0 :1; + __IO uint32_t SOT9B1 :1; + __IO uint32_t SCK9B0 :1; + __IO uint32_t SCK9B1 :1; + __IO uint32_t SIN10S0 :1; + __IO uint32_t SIN10S1 :1; + __IO uint32_t SOT10B0 :1; + __IO uint32_t SOT10B1 :1; + __IO uint32_t SCK10B0 :1; + __IO uint32_t SCK10B1 :1; + __IO uint32_t SIN11S0 :1; + __IO uint32_t SIN11S1 :1; + __IO uint32_t SOT11B0 :1; + __IO uint32_t SOT11B1 :1; + __IO uint32_t SCK11B0 :1; + __IO uint32_t SCK11B1 :1; + __IO uint32_t RESERVED1 :4; + }; + }; +} stc_gpio_epfr16_field_t; + +typedef struct stc_gpio_epfr17_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t SIN12S :2; + __IO uint32_t SOT12B :2; + __IO uint32_t SCK12B :2; + __IO uint32_t SIN13S :2; + __IO uint32_t SOT13B :2; + __IO uint32_t SCK13B :2; + __IO uint32_t SIN14S :2; + __IO uint32_t SOT14B :2; + __IO uint32_t SCK14B :2; + __IO uint32_t SIN15S :2; + __IO uint32_t SOT15B :2; + __IO uint32_t SCK15B :2; + __IO uint32_t RESERVED2 :4; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t SIN12S0 :1; + __IO uint32_t SIN12S1 :1; + __IO uint32_t SOT12B0 :1; + __IO uint32_t SOT12B1 :1; + __IO uint32_t SCK12B0 :1; + __IO uint32_t SCK12B1 :1; + __IO uint32_t SIN13S0 :1; + __IO uint32_t SIN13S1 :1; + __IO uint32_t SOT13B0 :1; + __IO uint32_t SOT13B1 :1; + __IO uint32_t SCK13B0 :1; + __IO uint32_t SCK13B1 :1; + __IO uint32_t SIN14S0 :1; + __IO uint32_t SIN14S1 :1; + __IO uint32_t SOT14B0 :1; + __IO uint32_t SOT14B1 :1; + __IO uint32_t SCK14B0 :1; + __IO uint32_t SCK14B1 :1; + __IO uint32_t SIN15S0 :1; + __IO uint32_t SIN15S1 :1; + __IO uint32_t SOT15B0 :1; + __IO uint32_t SOT15B1 :1; + __IO uint32_t SCK15B0 :1; + __IO uint32_t SCK15B1 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_gpio_epfr17_field_t; + +typedef struct stc_gpio_epfr18_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t QAIN3S :2; + __IO uint32_t QBIN3S :2; + __IO uint32_t QZIN3S :2; + __IO uint32_t RESERVED2 :4; + __IO uint32_t SDCLKE :2; + __IO uint32_t SDCMDB :2; + __IO uint32_t SDDATA0B :2; + __IO uint32_t SDDATA1B :2; + __IO uint32_t SDDATA2B :2; + __IO uint32_t SDDATA3B :2; + __IO uint32_t SDCDS :2; + __IO uint32_t SDWPS :2; + __IO uint32_t RESERVED4 :2; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t QAIN3S0 :1; + __IO uint32_t QAIN3S1 :1; + __IO uint32_t QBIN3S0 :1; + __IO uint32_t QBIN3S1 :1; + __IO uint32_t QZIN3S0 :1; + __IO uint32_t QZIN3S1 :1; + __IO uint32_t RESERVED3 :4; + __IO uint32_t SDCLKE0 :1; + __IO uint32_t SDCLKE1 :1; + __IO uint32_t SDCMDB0 :1; + __IO uint32_t SDCMDB1 :1; + __IO uint32_t SDDATA0B0 :1; + __IO uint32_t SDDATA0B1 :1; + __IO uint32_t SDDATA1B0 :1; + __IO uint32_t SDDATA1B1 :1; + __IO uint32_t SDDATA2B0 :1; + __IO uint32_t SDDATA2B1 :1; + __IO uint32_t SDDATA3B0 :1; + __IO uint32_t SDDATA3B1 :1; + __IO uint32_t SDCDS0 :1; + __IO uint32_t SDCDS1 :1; + __IO uint32_t SDWPS0 :1; + __IO uint32_t SDWPS1 :1; + __IO uint32_t RESERVED5 :2; + }; + }; +} stc_gpio_epfr18_field_t; + +typedef struct stc_gpio_epfr20_field +{ + __IO uint32_t UESMCKE :1; + __IO uint32_t UESMCEE :1; + __IO uint32_t UERASE :1; + __IO uint32_t UECASE :1; + __IO uint32_t UEDWEXE :1; + __IO uint32_t UECSXE :1; + __IO uint32_t UEDQM2E :1; + __IO uint32_t UEDQM3E :1; + __IO uint32_t UEDTHHB :1; + __IO uint32_t UED16B :1; + __IO uint32_t UED17B :1; + __IO uint32_t UED18B :1; + __IO uint32_t UED19B :1; + __IO uint32_t UED20B :1; + __IO uint32_t UED21B :1; + __IO uint32_t UED22B :1; + __IO uint32_t UED23B :1; + __IO uint32_t UED24B :1; + __IO uint32_t UED25B :1; + __IO uint32_t UED26B :1; + __IO uint32_t UED27B :1; + __IO uint32_t UED28B :1; + __IO uint32_t UED29B :1; + __IO uint32_t UED30B :1; + __IO uint32_t UED31B :1; + __IO uint32_t RESERVED0 :7; +} stc_gpio_epfr20_field_t; + +typedef struct stc_gpio_epfr23_field +{ + union { + struct { + __IO uint32_t SCS60E :2; + __IO uint32_t SCS61E :2; + __IO uint32_t SCS62E :2; + __IO uint32_t SCS63E :2; + __IO uint32_t SCS70E :2; + __IO uint32_t SCS71E :2; + __IO uint32_t SCS72E :2; + __IO uint32_t SCS73E :2; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t SCS60E0 :1; + __IO uint32_t SCS60E1 :1; + __IO uint32_t SCS61E0 :1; + __IO uint32_t SCS61E1 :1; + __IO uint32_t SCS62E0 :1; + __IO uint32_t SCS62E1 :1; + __IO uint32_t SCS63E0 :1; + __IO uint32_t SCS63E1 :1; + __IO uint32_t SCS70E0 :1; + __IO uint32_t SCS70E1 :1; + __IO uint32_t SCS71E0 :1; + __IO uint32_t SCS71E1 :1; + __IO uint32_t SCS72E0 :1; + __IO uint32_t SCS72E1 :1; + __IO uint32_t SCS73E0 :1; + __IO uint32_t SCS73E1 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_gpio_epfr23_field_t; + +typedef struct stc_gpio_epfr24_field +{ + union { + struct { + __IO uint32_t I2SM4_MCLK0S :2; + __IO uint32_t I2SM4_MCLK0E :2; + __IO uint32_t I2SM4_SCK0B :2; + __IO uint32_t I2SM4_WS0B :2; + __IO uint32_t I2SM4_SDI0S :2; + __IO uint32_t I2SM4_SDO0E :2; + __IO uint32_t RESERVED0 :4; + __IO uint32_t I2SM4_MCLK1S :2; + __IO uint32_t I2SM4_MCLK1E :2; + __IO uint32_t I2SM4_SCK1B :2; + __IO uint32_t I2SM4_WS1B :2; + __IO uint32_t I2SM4_SDI1S :2; + __IO uint32_t I2SM4_SDO1E :2; + __IO uint32_t RESERVED2 :4; + }; + struct { + __IO uint32_t I2SM4_MCLK0S0 :1; + __IO uint32_t I2SM4_MCLK0S1 :1; + __IO uint32_t I2SM4_MCLK0E0 :1; + __IO uint32_t I2SM4_MCLK0E1 :1; + __IO uint32_t I2SM4_SCK0B0 :1; + __IO uint32_t I2SM4_SCK0B1 :1; + __IO uint32_t I2SM4_WS0B0 :1; + __IO uint32_t I2SM4_WS0B1 :1; + __IO uint32_t I2SM4_SDI0S0 :1; + __IO uint32_t I2SM4_SDI0S1 :1; + __IO uint32_t I2SM4_SDO0E0 :1; + __IO uint32_t I2SM4_SDO0E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t I2SM4_MCLK1S0 :1; + __IO uint32_t I2SM4_MCLK1S1 :1; + __IO uint32_t I2SM4_MCLK1E0 :1; + __IO uint32_t I2SM4_MCLK1E1 :1; + __IO uint32_t I2SM4_SCK1B0 :1; + __IO uint32_t I2SM4_SCK1B1 :1; + __IO uint32_t I2SM4_WS1B0 :1; + __IO uint32_t I2SM4_WS1B1 :1; + __IO uint32_t I2SM4_SDI1S0 :1; + __IO uint32_t I2SM4_SDI1S1 :1; + __IO uint32_t I2SM4_SDO1E0 :1; + __IO uint32_t I2SM4_SDO1E1 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_gpio_epfr24_field_t; + +typedef struct stc_gpio_epfr25_field +{ + union { + struct { + __IO uint32_t MCRX2S :2; + __IO uint32_t MCTX2E :2; + __IO uint32_t RESERVED0 :28; + }; + struct { + __IO uint32_t MCRX2S0 :1; + __IO uint32_t MCRX2S1 :1; + __IO uint32_t MCTX2E0 :1; + __IO uint32_t MCTX2E1 :1; + __IO uint32_t RESERVED1 :28; + }; + }; +} stc_gpio_epfr25_field_t; + +typedef struct stc_gpio_epfr26_field +{ + union { + struct { + __IO uint32_t Q_SCKB :2; + __IO uint32_t Q_CS0E :2; + __IO uint32_t Q_CS1E :2; + __IO uint32_t Q_CS2E :2; + __IO uint32_t Q_CS3E :2; + __IO uint32_t Q_IO0B :2; + __IO uint32_t Q_IO1B :2; + __IO uint32_t Q_IO2B :2; + __IO uint32_t Q_IO3B :2; + __IO uint32_t RESERVED0 :14; + }; + struct { + __IO uint32_t Q_SCKB0 :1; + __IO uint32_t Q_SCKB1 :1; + __IO uint32_t Q_CS0E0 :1; + __IO uint32_t Q_CS0E1 :1; + __IO uint32_t Q_CS1E0 :1; + __IO uint32_t Q_CS1E1 :1; + __IO uint32_t Q_CS2E0 :1; + __IO uint32_t Q_CS2E1 :1; + __IO uint32_t Q_CS3E0 :1; + __IO uint32_t Q_CS3E1 :1; + __IO uint32_t Q_IO0B0 :1; + __IO uint32_t Q_IO0B1 :1; + __IO uint32_t Q_IO1B0 :1; + __IO uint32_t Q_IO1B1 :1; + __IO uint32_t Q_IO2B0 :1; + __IO uint32_t Q_IO2B1 :1; + __IO uint32_t Q_IO3B0 :1; + __IO uint32_t Q_IO3B1 :1; + __IO uint32_t RESERVED1 :14; + }; + }; +} stc_gpio_epfr26_field_t; + +typedef struct stc_gpio_pzr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pzr0_field_t; + +typedef struct stc_gpio_pzr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzr1_field_t; + +typedef struct stc_gpio_pzr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pzr2_field_t; + +typedef struct stc_gpio_pzr3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pzr3_field_t; + +typedef struct stc_gpio_pzr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_pzr4_field_t; + +typedef struct stc_gpio_pzr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pzr6_field_t; + +typedef struct stc_gpio_pzr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pzr7_field_t; + +typedef struct stc_gpio_pzr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pzr8_field_t; + +typedef struct stc_gpio_pzra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzra_field_t; + +typedef struct stc_gpio_pzrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzrc_field_t; + +typedef struct stc_gpio_pzrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pzrd_field_t; + +typedef struct stc_gpio_pzre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pzre_field_t; + +typedef struct stc_gpio_pdsr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pdsr0_field_t; + +typedef struct stc_gpio_pdsr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsr1_field_t; + +typedef struct stc_gpio_pdsr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pdsr2_field_t; + +typedef struct stc_gpio_pdsr3_field +{ + __IO uint32_t RESERVED0 :2; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pdsr3_field_t; + +typedef struct stc_gpio_pdsr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t RESERVED0 :22; +} stc_gpio_pdsr4_field_t; + +typedef struct stc_gpio_pdsr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PE :1; + __IO uint32_t RESERVED1 :17; +} stc_gpio_pdsr6_field_t; + +typedef struct stc_gpio_pdsr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdsr7_field_t; + +typedef struct stc_gpio_pdsr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pdsr8_field_t; + +typedef struct stc_gpio_pdsra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsra_field_t; + +typedef struct stc_gpio_pdsrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsrc_field_t; + +typedef struct stc_gpio_pdsrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pdsrd_field_t; + +typedef struct stc_gpio_pdsre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pdsre_field_t; + +/******************************************************************************* +* HSSPI_MODULE +*******************************************************************************/ +typedef struct stc_hsspi_mctrl_field +{ + __IO uint32_t MEN :1; + __IO uint32_t CSEN :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t MES :1; + __IO uint32_t SYNCON :1; + __IO uint32_t RESERVED1 :26; +} stc_hsspi_mctrl_field_t; + +typedef struct stc_hsspi_pcc0_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc0_field_t; + +typedef struct stc_hsspi_pcc1_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc1_field_t; + +typedef struct stc_hsspi_pcc2_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc2_field_t; + +typedef struct stc_hsspi_pcc3_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc3_field_t; + +typedef struct stc_hsspi_txf_field +{ + __IO uint32_t TFFS :1; + __IO uint32_t TFES :1; + __IO uint32_t TFOS :1; + __IO uint32_t TFUS :1; + __IO uint32_t TFLETS :1; + __IO uint32_t TFMTS :1; + __IO uint32_t TSSRS :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_txf_field_t; + +typedef struct stc_hsspi_txe_field +{ + __IO uint32_t TFFE :1; + __IO uint32_t TFEE :1; + __IO uint32_t TFOE :1; + __IO uint32_t TFUE :1; + __IO uint32_t TFLETE :1; + __IO uint32_t TFMTE :1; + __IO uint32_t TSSRE :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_txe_field_t; + +typedef struct stc_hsspi_txc_field +{ + __IO uint32_t TFFC :1; + __IO uint32_t TFEC :1; + __IO uint32_t TFOC :1; + __IO uint32_t TFUC :1; + __IO uint32_t TFLETC :1; + __IO uint32_t TFMTC :1; + __IO uint32_t TSSRC :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_txc_field_t; + +typedef struct stc_hsspi_rxf_field +{ + __IO uint32_t RFFS :1; + __IO uint32_t RFES :1; + __IO uint32_t RFOS :1; + __IO uint32_t RFUS :1; + __IO uint32_t RFLETS :1; + __IO uint32_t RFMTS :1; + __IO uint32_t RSSRS :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_rxf_field_t; + +typedef struct stc_hsspi_rxe_field +{ + __IO uint32_t RFFE :1; + __IO uint32_t RFEE :1; + __IO uint32_t RFOE :1; + __IO uint32_t RFUE :1; + __IO uint32_t RFLETE :1; + __IO uint32_t RFMTE :1; + __IO uint32_t RSSRE :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_rxe_field_t; + +typedef struct stc_hsspi_rxc_field +{ + __IO uint32_t RFFC :1; + __IO uint32_t RFEC :1; + __IO uint32_t RFOC :1; + __IO uint32_t RFUC :1; + __IO uint32_t RFLETC :1; + __IO uint32_t RFMTC :1; + __IO uint32_t RSSRC :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_rxc_field_t; + +typedef struct stc_hsspi_faultf_field +{ + __IO uint32_t UMAFS :1; + __IO uint32_t WAFS :1; + __IO uint32_t PVFS :1; + __IO uint32_t DWCBSFS :1; + __IO uint32_t DRCBSFS :1; + __IO uint32_t RESERVED0 :27; +} stc_hsspi_faultf_field_t; + +typedef struct stc_hsspi_faultc_field +{ + __IO uint32_t UMAFC :1; + __IO uint32_t WAFC :1; + __IO uint32_t PVFC :1; + __IO uint32_t DWCBSFC :1; + __IO uint32_t DRCBSFC :1; + __IO uint32_t RESERVED0 :27; +} stc_hsspi_faultc_field_t; + +typedef struct stc_hsspi_dmcfg_field +{ + __IO uint8_t RESERVED0 :1; + __IO uint8_t SSDC :1; + __IO uint8_t RESERVED1 :6; +} stc_hsspi_dmcfg_field_t; + +typedef struct stc_hsspi_dmdmaen_field +{ + __IO uint8_t RXDMAEN :1; + __IO uint8_t TXDMAEN :1; + __IO uint8_t RESERVED0 :6; +} stc_hsspi_dmdmaen_field_t; + +typedef struct stc_hsspi_dmstart_field +{ + __IO uint8_t START :1; + __IO uint8_t RESERVED0 :7; +} stc_hsspi_dmstart_field_t; + +typedef struct stc_hsspi_dmstop_field +{ + __IO uint8_t STOP :1; + __IO uint8_t RESERVED0 :7; +} stc_hsspi_dmstop_field_t; + +typedef struct stc_hsspi_dmpsel_field +{ + union { + struct { + __IO uint8_t PSEL :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t PSEL0 :1; + __IO uint8_t PSEL1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_hsspi_dmpsel_field_t; + +typedef struct stc_hsspi_dmtrp_field +{ + union { + struct { + __IO uint8_t TRP :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t TRP0 :1; + __IO uint8_t TRP1 :1; + __IO uint8_t TRP2 :1; + __IO uint8_t TRP3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_hsspi_dmtrp_field_t; + +typedef struct stc_hsspi_dmbcc_field +{ + union { + struct { + __IO uint16_t BCC :16; + }; + struct { + __IO uint16_t BCC0 :1; + __IO uint16_t BCC1 :1; + __IO uint16_t BCC2 :1; + __IO uint16_t BCC3 :1; + __IO uint16_t BCC4 :1; + __IO uint16_t BCC5 :1; + __IO uint16_t BCC6 :1; + __IO uint16_t BCC7 :1; + __IO uint16_t BCC8 :1; + __IO uint16_t BCC9 :1; + __IO uint16_t BCC10 :1; + __IO uint16_t BCC11 :1; + __IO uint16_t BCC12 :1; + __IO uint16_t BCC13 :1; + __IO uint16_t BCC14 :1; + __IO uint16_t BCC15 :1; + }; + }; +} stc_hsspi_dmbcc_field_t; + +typedef struct stc_hsspi_dmbcs_field +{ + union { + struct { + __IO uint16_t BCS :16; + }; + struct { + __IO uint16_t BCS0 :1; + __IO uint16_t BCS1 :1; + __IO uint16_t BCS2 :1; + __IO uint16_t BCS3 :1; + __IO uint16_t BCS4 :1; + __IO uint16_t BCS5 :1; + __IO uint16_t BCS6 :1; + __IO uint16_t BCS7 :1; + __IO uint16_t BCS8 :1; + __IO uint16_t BCS9 :1; + __IO uint16_t BCS10 :1; + __IO uint16_t BCS11 :1; + __IO uint16_t BCS12 :1; + __IO uint16_t BCS13 :1; + __IO uint16_t BCS14 :1; + __IO uint16_t BCS15 :1; + }; + }; +} stc_hsspi_dmbcs_field_t; + +typedef struct stc_hsspi_dmstatus_field +{ + union { + struct { + __IO uint32_t RXACTIVE :1; + __IO uint32_t TXACTIVE :1; + __IO uint32_t RESERVED0 :6; + __IO uint32_t RXFLEVEL :5; + __IO uint32_t RESERVED2 :3; + __IO uint32_t TXFLEVEL :5; + __IO uint32_t RESERVED4 :11; + }; + struct { + __IO uint32_t RESERVED1 :8; + __IO uint32_t RXFLEVEL0 :1; + __IO uint32_t RXFLEVEL1 :1; + __IO uint32_t RXFLEVEL2 :1; + __IO uint32_t RXFLEVEL3 :1; + __IO uint32_t RXFLEVEL4 :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t TXFLEVEL0 :1; + __IO uint32_t TXFLEVEL1 :1; + __IO uint32_t TXFLEVEL2 :1; + __IO uint32_t TXFLEVEL3 :1; + __IO uint32_t TXFLEVEL4 :1; + __IO uint32_t RESERVED5 :11; + }; + }; +} stc_hsspi_dmstatus_field_t; + +typedef struct stc_hsspi_fifocfg_field +{ + union { + struct { + __IO uint32_t RXFTH :4; + __IO uint32_t TXFTH :4; + __IO uint32_t FWIDTH :2; + __IO uint32_t TXCTRL :1; + __IO uint32_t RXFLSH :1; + __IO uint32_t TXFLSH :1; + __IO uint32_t RESERVED0 :19; + }; + struct { + __IO uint32_t RXFTH0 :1; + __IO uint32_t RXFTH1 :1; + __IO uint32_t RXFTH2 :1; + __IO uint32_t RXFTH3 :1; + __IO uint32_t TXFTH0 :1; + __IO uint32_t TXFTH1 :1; + __IO uint32_t TXFTH2 :1; + __IO uint32_t TXFTH3 :1; + __IO uint32_t FWIDTH0 :1; + __IO uint32_t FWIDTH1 :1; + __IO uint32_t RESERVED1 :22; + }; + }; +} stc_hsspi_fifocfg_field_t; + +typedef struct stc_hsspi_txfifo0_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo0_field_t; + +typedef struct stc_hsspi_txfifo1_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo1_field_t; + +typedef struct stc_hsspi_txfifo2_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo2_field_t; + +typedef struct stc_hsspi_txfifo3_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo3_field_t; + +typedef struct stc_hsspi_txfifo4_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo4_field_t; + +typedef struct stc_hsspi_txfifo5_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo5_field_t; + +typedef struct stc_hsspi_txfifo6_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo6_field_t; + +typedef struct stc_hsspi_txfifo7_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo7_field_t; + +typedef struct stc_hsspi_txfifo8_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo8_field_t; + +typedef struct stc_hsspi_txfifo9_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo9_field_t; + +typedef struct stc_hsspi_txfifo10_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo10_field_t; + +typedef struct stc_hsspi_txfifo11_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo11_field_t; + +typedef struct stc_hsspi_txfifo12_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo12_field_t; + +typedef struct stc_hsspi_txfifo13_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo13_field_t; + +typedef struct stc_hsspi_txfifo14_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo14_field_t; + +typedef struct stc_hsspi_txfifo15_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo15_field_t; + +typedef struct stc_hsspi_rxfifo0_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo0_field_t; + +typedef struct stc_hsspi_rxfifo1_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo1_field_t; + +typedef struct stc_hsspi_rxfifo2_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo2_field_t; + +typedef struct stc_hsspi_rxfifo3_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo3_field_t; + +typedef struct stc_hsspi_rxfifo4_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo4_field_t; + +typedef struct stc_hsspi_rxfifo5_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo5_field_t; + +typedef struct stc_hsspi_rxfifo6_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo6_field_t; + +typedef struct stc_hsspi_rxfifo7_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo7_field_t; + +typedef struct stc_hsspi_rxfifo8_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo8_field_t; + +typedef struct stc_hsspi_rxfifo9_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo9_field_t; + +typedef struct stc_hsspi_rxfifo10_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo10_field_t; + +typedef struct stc_hsspi_rxfifo11_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo11_field_t; + +typedef struct stc_hsspi_rxfifo12_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo12_field_t; + +typedef struct stc_hsspi_rxfifo13_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo13_field_t; + +typedef struct stc_hsspi_rxfifo14_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo14_field_t; + +typedef struct stc_hsspi_rxfifo15_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo15_field_t; + +typedef struct stc_hsspi_cscfg_field +{ + union { + struct { + __IO uint32_t SRAM :1; + __IO uint32_t MBM :2; + __IO uint32_t RESERVED1 :5; + __IO uint32_t SSEL0EN :1; + __IO uint32_t SSEL1EN :1; + __IO uint32_t SSEL2EN :1; + __IO uint32_t SSEL3EN :1; + __IO uint32_t RESERVED2 :4; + __IO uint32_t MSEL :4; + __IO uint32_t RESERVED4 :12; + }; + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t MBM0 :1; + __IO uint32_t MBM1 :1; + __IO uint32_t RESERVED3 :13; + __IO uint32_t MSEL0 :1; + __IO uint32_t MSEL1 :1; + __IO uint32_t MSEL2 :1; + __IO uint32_t MSEL3 :1; + __IO uint32_t RESERVED5 :12; + }; + }; +} stc_hsspi_cscfg_field_t; + +typedef struct stc_hsspi_csitime_field +{ + union { + struct { + __IO uint32_t ITIME :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t ITIME0 :1; + __IO uint32_t ITIME1 :1; + __IO uint32_t ITIME2 :1; + __IO uint32_t ITIME3 :1; + __IO uint32_t ITIME4 :1; + __IO uint32_t ITIME5 :1; + __IO uint32_t ITIME6 :1; + __IO uint32_t ITIME7 :1; + __IO uint32_t ITIME8 :1; + __IO uint32_t ITIME9 :1; + __IO uint32_t ITIME10 :1; + __IO uint32_t ITIME11 :1; + __IO uint32_t ITIME12 :1; + __IO uint32_t ITIME13 :1; + __IO uint32_t ITIME14 :1; + __IO uint32_t ITIME15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_hsspi_csitime_field_t; + +typedef struct stc_hsspi_csaext_field +{ + union { + struct { + __IO uint32_t RESERVED0 :13; + __IO uint32_t AEXT :19; + }; + struct { + __IO uint32_t RESERVED1 :13; + __IO uint32_t AEXT0 :1; + __IO uint32_t AEXT1 :1; + __IO uint32_t AEXT2 :1; + __IO uint32_t AEXT3 :1; + __IO uint32_t AEXT4 :1; + __IO uint32_t AEXT5 :1; + __IO uint32_t AEXT6 :1; + __IO uint32_t AEXT7 :1; + __IO uint32_t AEXT8 :1; + __IO uint32_t AEXT9 :1; + __IO uint32_t AEXT10 :1; + __IO uint32_t AEXT11 :1; + __IO uint32_t AEXT12 :1; + __IO uint32_t AEXT13 :1; + __IO uint32_t AEXT14 :1; + __IO uint32_t AEXT15 :1; + __IO uint32_t AEXT16 :1; + __IO uint32_t AEXT17 :1; + __IO uint32_t AEXT18 :1; + }; + }; +} stc_hsspi_csaext_field_t; + +typedef struct stc_hsspi_rdcsdc0_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc0_field_t; + +typedef struct stc_hsspi_rdcsdc1_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc1_field_t; + +typedef struct stc_hsspi_rdcsdc2_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc2_field_t; + +typedef struct stc_hsspi_rdcsdc3_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc3_field_t; + +typedef struct stc_hsspi_rdcsdc4_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc4_field_t; + +typedef struct stc_hsspi_rdcsdc5_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc5_field_t; + +typedef struct stc_hsspi_rdcsdc6_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc6_field_t; + +typedef struct stc_hsspi_rdcsdc7_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc7_field_t; + +typedef struct stc_hsspi_wrcsdc0_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc0_field_t; + +typedef struct stc_hsspi_wrcsdc1_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc1_field_t; + +typedef struct stc_hsspi_wrcsdc2_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc2_field_t; + +typedef struct stc_hsspi_wrcsdc3_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc3_field_t; + +typedef struct stc_hsspi_wrcsdc4_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc4_field_t; + +typedef struct stc_hsspi_wrcsdc5_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc5_field_t; + +typedef struct stc_hsspi_wrcsdc6_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc6_field_t; + +typedef struct stc_hsspi_wrcsdc7_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc7_field_t; + +typedef struct stc_hsspi_mid_field +{ + union { + struct { + __IO uint32_t MID :32; + }; + struct { + __IO uint32_t MID0 :1; + __IO uint32_t MID1 :1; + __IO uint32_t MID2 :1; + __IO uint32_t MID3 :1; + __IO uint32_t MID4 :1; + __IO uint32_t MID5 :1; + __IO uint32_t MID6 :1; + __IO uint32_t MID7 :1; + __IO uint32_t MID8 :1; + __IO uint32_t MID9 :1; + __IO uint32_t MID10 :1; + __IO uint32_t MID11 :1; + __IO uint32_t MID12 :1; + __IO uint32_t MID13 :1; + __IO uint32_t MID14 :1; + __IO uint32_t MID15 :1; + __IO uint32_t MID16 :1; + __IO uint32_t MID17 :1; + __IO uint32_t MID18 :1; + __IO uint32_t MID19 :1; + __IO uint32_t MID20 :1; + __IO uint32_t MID21 :1; + __IO uint32_t MID22 :1; + __IO uint32_t MID23 :1; + __IO uint32_t MID24 :1; + __IO uint32_t MID25 :1; + __IO uint32_t MID26 :1; + __IO uint32_t MID27 :1; + __IO uint32_t MID28 :1; + __IO uint32_t MID29 :1; + __IO uint32_t MID30 :1; + __IO uint32_t MID31 :1; + }; + }; +} stc_hsspi_mid_field_t; + +typedef struct stc_hsspi_qdclkr_field +{ + union { + struct { + __IO uint8_t QHDIV :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t QHDIV0 :1; + __IO uint8_t QHDIV1 :1; + __IO uint8_t QHDIV2 :1; + __IO uint8_t QHDIV3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_hsspi_qdclkr_field_t; + +typedef struct stc_hsspi_dbcnt_field +{ + __IO uint8_t RXDBEN :1; + __IO uint8_t TXDBEN :1; + __IO uint8_t RESERVED0 :6; +} stc_hsspi_dbcnt_field_t; + +/******************************************************************************* +* HWWDT_MODULE +*******************************************************************************/ +typedef struct stc_hwwdt_wdg_ctl_field +{ + __IO uint32_t INTEN :1; + __IO uint32_t RESEN :1; + __IO uint32_t RESERVED0 :30; +} stc_hwwdt_wdg_ctl_field_t; + +typedef struct stc_hwwdt_wdg_ris_field +{ + __IO uint32_t RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_hwwdt_wdg_ris_field_t; + +/******************************************************************************* +* I2S_MODULE +*******************************************************************************/ +typedef struct stc_i2s_rxfdat_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_i2s_rxfdat_field_t; + +typedef struct stc_i2s_txfdat_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_i2s_txfdat_field_t; + +typedef struct stc_i2s_cntreg_field +{ + union { + struct { + __IO uint32_t FSPL :1; + __IO uint32_t FSLN :1; + __IO uint32_t FSPH :1; + __IO uint32_t CPOL :1; + __IO uint32_t SMPL :1; + __IO uint32_t RXDIS :1; + __IO uint32_t TXDIS :1; + __IO uint32_t MLSB :1; + __IO uint32_t FRUN :1; + __IO uint32_t BEXT :1; + __IO uint32_t ECKM :1; + __IO uint32_t RHLL :1; + __IO uint32_t SBFN :1; + __IO uint32_t MSMD :1; + __IO uint32_t MSKB :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t OVHD :10; + __IO uint32_t CKRT :6; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t OVHD0 :1; + __IO uint32_t OVHD1 :1; + __IO uint32_t OVHD2 :1; + __IO uint32_t OVHD3 :1; + __IO uint32_t OVHD4 :1; + __IO uint32_t OVHD5 :1; + __IO uint32_t OVHD6 :1; + __IO uint32_t OVHD7 :1; + __IO uint32_t OVHD8 :1; + __IO uint32_t OVHD9 :1; + __IO uint32_t CKRT0 :1; + __IO uint32_t CKRT1 :1; + __IO uint32_t CKRT2 :1; + __IO uint32_t CKRT3 :1; + __IO uint32_t CKRT4 :1; + __IO uint32_t CKRT5 :1; + }; + }; +} stc_i2s_cntreg_field_t; + +typedef struct stc_i2s_mcr0reg_field +{ + union { + struct { + __IO uint32_t S0WDL :5; + __IO uint32_t S0CHL :5; + __IO uint32_t S0CHN :5; + __IO uint32_t RESERVED0 :1; + __IO uint32_t S1WDL :5; + __IO uint32_t S1CHL :5; + __IO uint32_t S1CHN :5; + __IO uint32_t RESERVED2 :1; + }; + struct { + __IO uint32_t S0WDL0 :1; + __IO uint32_t S0WDL1 :1; + __IO uint32_t S0WDL2 :1; + __IO uint32_t S0WDL3 :1; + __IO uint32_t S0WDL4 :1; + __IO uint32_t S0CHL0 :1; + __IO uint32_t S0CHL1 :1; + __IO uint32_t S0CHL2 :1; + __IO uint32_t S0CHL3 :1; + __IO uint32_t S0CHL4 :1; + __IO uint32_t S0CHN0 :1; + __IO uint32_t S0CHN1 :1; + __IO uint32_t S0CHN2 :1; + __IO uint32_t S0CHN3 :1; + __IO uint32_t S0CHN4 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t S1WDL0 :1; + __IO uint32_t S1WDL1 :1; + __IO uint32_t S1WDL2 :1; + __IO uint32_t S1WDL3 :1; + __IO uint32_t S1WDL4 :1; + __IO uint32_t S1CHL0 :1; + __IO uint32_t S1CHL1 :1; + __IO uint32_t S1CHL2 :1; + __IO uint32_t S1CHL3 :1; + __IO uint32_t S1CHL4 :1; + __IO uint32_t S1CHN0 :1; + __IO uint32_t S1CHN1 :1; + __IO uint32_t S1CHN2 :1; + __IO uint32_t S1CHN3 :1; + __IO uint32_t S1CHN4 :1; + __IO uint32_t RESERVED3 :1; + }; + }; +} stc_i2s_mcr0reg_field_t; + +typedef struct stc_i2s_mcr1reg_field +{ + __IO uint32_t S0CH00 :1; + __IO uint32_t S0CH01 :1; + __IO uint32_t S0CH02 :1; + __IO uint32_t S0CH03 :1; + __IO uint32_t S0CH04 :1; + __IO uint32_t S0CH05 :1; + __IO uint32_t S0CH06 :1; + __IO uint32_t S0CH07 :1; + __IO uint32_t S0CH08 :1; + __IO uint32_t S0CH09 :1; + __IO uint32_t S0CH10 :1; + __IO uint32_t S0CH11 :1; + __IO uint32_t S0CH12 :1; + __IO uint32_t S0CH13 :1; + __IO uint32_t S0CH14 :1; + __IO uint32_t S0CH15 :1; + __IO uint32_t S0CH16 :1; + __IO uint32_t S0CH17 :1; + __IO uint32_t S0CH18 :1; + __IO uint32_t S0CH19 :1; + __IO uint32_t S0CH20 :1; + __IO uint32_t S0CH21 :1; + __IO uint32_t S0CH22 :1; + __IO uint32_t S0CH23 :1; + __IO uint32_t S0CH24 :1; + __IO uint32_t S0CH25 :1; + __IO uint32_t S0CH26 :1; + __IO uint32_t S0CH27 :1; + __IO uint32_t S0CH28 :1; + __IO uint32_t S0CH29 :1; + __IO uint32_t S0CH30 :1; + __IO uint32_t S0CH31 :1; +} stc_i2s_mcr1reg_field_t; + +typedef struct stc_i2s_mcr2reg_field +{ + __IO uint32_t S1CH00 :1; + __IO uint32_t S1CH01 :1; + __IO uint32_t S1CH02 :1; + __IO uint32_t S1CH03 :1; + __IO uint32_t S1CH04 :1; + __IO uint32_t S1CH05 :1; + __IO uint32_t S1CH06 :1; + __IO uint32_t S1CH07 :1; + __IO uint32_t S1CH08 :1; + __IO uint32_t S1CH09 :1; + __IO uint32_t S1CH10 :1; + __IO uint32_t S1CH11 :1; + __IO uint32_t S1CH12 :1; + __IO uint32_t S1CH13 :1; + __IO uint32_t S1CH14 :1; + __IO uint32_t S1CH15 :1; + __IO uint32_t S1CH16 :1; + __IO uint32_t S1CH17 :1; + __IO uint32_t S1CH18 :1; + __IO uint32_t S1CH19 :1; + __IO uint32_t S1CH20 :1; + __IO uint32_t S1CH21 :1; + __IO uint32_t S1CH22 :1; + __IO uint32_t S1CH23 :1; + __IO uint32_t S1CH24 :1; + __IO uint32_t S1CH25 :1; + __IO uint32_t S1CH26 :1; + __IO uint32_t S1CH27 :1; + __IO uint32_t S1CH28 :1; + __IO uint32_t S1CH29 :1; + __IO uint32_t S1CH30 :1; + __IO uint32_t S1CH31 :1; +} stc_i2s_mcr2reg_field_t; + +typedef struct stc_i2s_oprreg_field +{ + __IO uint32_t START :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t TXENB :1; + __IO uint32_t RESERVED1 :7; + __IO uint32_t RXENB :1; + __IO uint32_t RESERVED2 :7; +} stc_i2s_oprreg_field_t; + +typedef struct stc_i2s_srst_field +{ + __IO uint32_t SRST :1; + __IO uint32_t RESERVED0 :31; +} stc_i2s_srst_field_t; + +typedef struct stc_i2s_intcnt_field +{ + union { + struct { + __IO uint32_t RFTH :4; + __IO uint32_t RPTMR :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t TFTH :4; + __IO uint32_t RESERVED2 :4; + __IO uint32_t RXFIM :1; + __IO uint32_t RXFDM :1; + __IO uint32_t EOPM :1; + __IO uint32_t RXOVM :1; + __IO uint32_t RXUDM :1; + __IO uint32_t RBERM :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TXFIM :1; + __IO uint32_t TXFDM :1; + __IO uint32_t TXOVM :1; + __IO uint32_t TXUD0M :1; + __IO uint32_t FERRM :1; + __IO uint32_t TBERM :1; + __IO uint32_t TXUD1M :1; + __IO uint32_t RESERVED4 :1; + }; + struct { + __IO uint32_t RFTH0 :1; + __IO uint32_t RFTH1 :1; + __IO uint32_t RFTH2 :1; + __IO uint32_t RFTH3 :1; + __IO uint32_t RPTMR0 :1; + __IO uint32_t RPTMR1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t TFTH0 :1; + __IO uint32_t TFTH1 :1; + __IO uint32_t TFTH2 :1; + __IO uint32_t TFTH3 :1; + __IO uint32_t RESERVED5 :20; + }; + }; +} stc_i2s_intcnt_field_t; + +typedef struct stc_i2s_status_field +{ + union { + struct { + __IO uint32_t RXNUM :8; + __IO uint32_t TXNUM :8; + __IO uint32_t RXFI :1; + __IO uint32_t TXFI :1; + __IO uint32_t BSY :1; + __IO uint32_t EOPI :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t RXOVR :1; + __IO uint32_t RXUDR :1; + __IO uint32_t TXOVR :1; + __IO uint32_t TXUDR0 :1; + __IO uint32_t TXUDR1 :1; + __IO uint32_t FERR :1; + __IO uint32_t RBERR :1; + __IO uint32_t TBERR :1; + }; + struct { + __IO uint32_t RXNUM0 :1; + __IO uint32_t RXNUM1 :1; + __IO uint32_t RXNUM2 :1; + __IO uint32_t RXNUM3 :1; + __IO uint32_t RXNUM4 :1; + __IO uint32_t RXNUM5 :1; + __IO uint32_t RXNUM6 :1; + __IO uint32_t RXNUM7 :1; + __IO uint32_t TXNUM0 :1; + __IO uint32_t TXNUM1 :1; + __IO uint32_t TXNUM2 :1; + __IO uint32_t TXNUM3 :1; + __IO uint32_t TXNUM4 :1; + __IO uint32_t TXNUM5 :1; + __IO uint32_t TXNUM6 :1; + __IO uint32_t TXNUM7 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_i2s_status_field_t; + +typedef struct stc_i2s_dmaact_field +{ + __IO uint32_t RDMACT :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t RL1E0 :1; + __IO uint32_t RESERVED1 :7; + __IO uint32_t TDMACT :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TL1E0 :1; + __IO uint32_t RESERVED3 :7; +} stc_i2s_dmaact_field_t; + +typedef struct stc_i2s_tstreg_field +{ + __IO uint32_t LBMD :1; + __IO uint32_t RESERVED0 :31; +} stc_i2s_tstreg_field_t; + +/******************************************************************************* +* I2SPRE_MODULE +*******************************************************************************/ +typedef struct stc_i2spre_iccr_field +{ + __IO uint32_t I2SEN :1; + __IO uint32_t ICSEL :1; + __IO uint32_t RESERVED0 :30; +} stc_i2spre_iccr_field_t; + +typedef struct stc_i2spre_ipcr1_field +{ + __IO uint32_t IPLLEN :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipcr1_field_t; + +typedef struct stc_i2spre_ipcr2_field +{ + union { + struct { + __IO uint32_t IPOWT :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t IPOWT0 :1; + __IO uint32_t IPOWT1 :1; + __IO uint32_t IPOWT2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_i2spre_ipcr2_field_t; + +typedef struct stc_i2spre_ipcr3_field +{ + union { + struct { + __IO uint32_t IPLLK :5; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t IPLLK0 :1; + __IO uint32_t IPLLK1 :1; + __IO uint32_t IPLLK2 :1; + __IO uint32_t IPLLK3 :1; + __IO uint32_t IPLLK4 :1; + __IO uint32_t RESERVED1 :27; + }; + }; +} stc_i2spre_ipcr3_field_t; + +typedef struct stc_i2spre_ipcr4_field +{ + union { + struct { + __IO uint32_t IPLLN :7; + __IO uint32_t RESERVED0 :25; + }; + struct { + __IO uint32_t IPLLN0 :1; + __IO uint32_t IPLLN1 :1; + __IO uint32_t IPLLN2 :1; + __IO uint32_t IPLLN3 :1; + __IO uint32_t IPLLN4 :1; + __IO uint32_t IPLLN5 :1; + __IO uint32_t IPLLN6 :1; + __IO uint32_t RESERVED1 :25; + }; + }; +} stc_i2spre_ipcr4_field_t; + +typedef struct stc_i2spre_ip_str_field +{ + __IO uint32_t IPRDY :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ip_str_field_t; + +typedef struct stc_i2spre_ipint_enr_field +{ + __IO uint32_t IPCSE :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipint_enr_field_t; + +typedef struct stc_i2spre_ipint_clr_field +{ + __IO uint32_t IPCSC :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipint_clr_field_t; + +typedef struct stc_i2spre_ipint_str_field +{ + __IO uint32_t IPCSI :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipint_str_field_t; + +typedef struct stc_i2spre_ipcr5_field +{ + union { + struct { + __IO uint32_t IPLLM :7; + __IO uint32_t RESERVED0 :25; + }; + struct { + __IO uint32_t IPLLM0 :1; + __IO uint32_t IPLLM1 :1; + __IO uint32_t IPLLM2 :1; + __IO uint32_t IPLLM3 :1; + __IO uint32_t IPLLM4 :1; + __IO uint32_t IPLLM5 :1; + __IO uint32_t IPLLM6 :1; + __IO uint32_t RESERVED1 :25; + }; + }; +} stc_i2spre_ipcr5_field_t; + +/******************************************************************************* +* INTREQ_MODULE +*******************************************************************************/ +typedef struct stc_intreq_drqsel_field +{ + __IO uint32_t USBEP1 :1; + __IO uint32_t USBEP2 :1; + __IO uint32_t USBEP3 :1; + __IO uint32_t USBEP4 :1; + __IO uint32_t USBEP5 :1; + __IO uint32_t ADCSCAN0 :1; + __IO uint32_t ADCSCAN1 :1; + __IO uint32_t ADCSCAN2 :1; + __IO uint32_t IRQ0BT0 :1; + __IO uint32_t IRQ0BT2 :1; + __IO uint32_t IRQ0BT4 :1; + __IO uint32_t IRQ0BT6 :1; + __IO uint32_t MFS0RX :1; + __IO uint32_t MFS0TX :1; + __IO uint32_t MFS1RX :1; + __IO uint32_t MFS1TX :1; + __IO uint32_t MFS2RX :1; + __IO uint32_t MFS2TX :1; + __IO uint32_t MFS3RX :1; + __IO uint32_t MFS3TX :1; + __IO uint32_t MFS4RX :1; + __IO uint32_t MFS4TX :1; + __IO uint32_t MFS5RX :1; + __IO uint32_t MFS5TX :1; + __IO uint32_t MFS6RX :1; + __IO uint32_t MFS6TX :1; + __IO uint32_t MFS7RX :1; + __IO uint32_t MFS7TX :1; + __IO uint32_t EXINT0 :1; + __IO uint32_t EXINT1 :1; + __IO uint32_t EXINT2 :1; + __IO uint32_t EXINT3 :1; +} stc_intreq_drqsel_field_t; + +typedef struct stc_intreq_oddpks_field +{ + __IO uint8_t ODDPKS0 :1; + __IO uint8_t ODDPKS1 :1; + __IO uint8_t ODDPKS2 :1; + __IO uint8_t ODDPKS3 :1; + __IO uint8_t ODDPKS4 :1; + __IO uint8_t RESERVED0 :3; +} stc_intreq_oddpks_field_t; + +typedef struct stc_intreq_oddpks1_field +{ + __IO uint8_t ODDPKS10 :1; + __IO uint8_t ODDPKS11 :1; + __IO uint8_t ODDPKS12 :1; + __IO uint8_t ODDPKS13 :1; + __IO uint8_t ODDPKS14 :1; + __IO uint8_t RESERVED0 :3; +} stc_intreq_oddpks1_field_t; + +typedef struct stc_intreq_irq003sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq003sel_field_t; + +typedef struct stc_intreq_irq004sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq004sel_field_t; + +typedef struct stc_intreq_irq005sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq005sel_field_t; + +typedef struct stc_intreq_irq006sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq006sel_field_t; + +typedef struct stc_intreq_irq007sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq007sel_field_t; + +typedef struct stc_intreq_irq008sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq008sel_field_t; + +typedef struct stc_intreq_irq009sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq009sel_field_t; + +typedef struct stc_intreq_irq010sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq010sel_field_t; + +typedef struct stc_intreq_exc02mon_field +{ + __IO uint32_t NMI :1; + __IO uint32_t HWINT :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_exc02mon_field_t; + +typedef struct stc_intreq_irq000mon_field +{ + __IO uint32_t FCSINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq000mon_field_t; + +typedef struct stc_intreq_irq001mon_field +{ + __IO uint32_t SWWDTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq001mon_field_t; + +typedef struct stc_intreq_irq002mon_field +{ + __IO uint32_t LVDINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq002mon_field_t; + +typedef struct stc_intreq_irq003mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq003mon_field_t; + +typedef struct stc_intreq_irq004mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq004mon_field_t; + +typedef struct stc_intreq_irq005mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq005mon_field_t; + +typedef struct stc_intreq_irq006mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq006mon_field_t; + +typedef struct stc_intreq_irq007mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq007mon_field_t; + +typedef struct stc_intreq_irq008mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq008mon_field_t; + +typedef struct stc_intreq_irq009mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq009mon_field_t; + +typedef struct stc_intreq_irq010mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq010mon_field_t; + +typedef struct stc_intreq_irq011mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq011mon_field_t; + +typedef struct stc_intreq_irq012mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq012mon_field_t; + +typedef struct stc_intreq_irq013mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq013mon_field_t; + +typedef struct stc_intreq_irq014mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq014mon_field_t; + +typedef struct stc_intreq_irq015mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq015mon_field_t; + +typedef struct stc_intreq_irq016mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq016mon_field_t; + +typedef struct stc_intreq_irq017mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq017mon_field_t; + +typedef struct stc_intreq_irq018mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq018mon_field_t; + +typedef struct stc_intreq_irq019mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq019mon_field_t; + +typedef struct stc_intreq_irq020mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq020mon_field_t; + +typedef struct stc_intreq_irq021mon_field +{ + __IO uint32_t WAVEINT0 :1; + __IO uint32_t WAVEINT1 :1; + __IO uint32_t WAVEINT2 :1; + __IO uint32_t WAVEINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq021mon_field_t; + +typedef struct stc_intreq_irq022mon_field +{ + __IO uint32_t WAVEINT0 :1; + __IO uint32_t WAVEINT1 :1; + __IO uint32_t WAVEINT2 :1; + __IO uint32_t WAVEINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq022mon_field_t; + +typedef struct stc_intreq_irq023mon_field +{ + __IO uint32_t WAVEINT0 :1; + __IO uint32_t WAVEINT1 :1; + __IO uint32_t WAVEINT2 :1; + __IO uint32_t WAVEINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq023mon_field_t; + +typedef struct stc_intreq_irq024mon_field +{ + __IO uint32_t FRT_PEAK_INT0 :1; + __IO uint32_t FRT_PEAK_INT1 :1; + __IO uint32_t FRT_PEAK_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq024mon_field_t; + +typedef struct stc_intreq_irq025mon_field +{ + __IO uint32_t FRT_ZERO_INT0 :1; + __IO uint32_t FRT_ZERO_INT1 :1; + __IO uint32_t FRT_ZERO_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq025mon_field_t; + +typedef struct stc_intreq_irq026mon_field +{ + __IO uint32_t ICUINT0 :1; + __IO uint32_t ICUINT1 :1; + __IO uint32_t ICUINT2 :1; + __IO uint32_t ICUINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq026mon_field_t; + +typedef struct stc_intreq_irq027mon_field +{ + __IO uint32_t OCUINT0 :1; + __IO uint32_t OCUINT1 :1; + __IO uint32_t OCUINT2 :1; + __IO uint32_t OCUINT3 :1; + __IO uint32_t OCUINT4 :1; + __IO uint32_t OCUINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq027mon_field_t; + +typedef struct stc_intreq_irq028mon_field +{ + __IO uint32_t FRT_PEAK_INT0 :1; + __IO uint32_t FRT_PEAK_INT1 :1; + __IO uint32_t FRT_PEAK_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq028mon_field_t; + +typedef struct stc_intreq_irq029mon_field +{ + __IO uint32_t FRT_ZERO_INT0 :1; + __IO uint32_t FRT_ZERO_INT1 :1; + __IO uint32_t FRT_ZERO_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq029mon_field_t; + +typedef struct stc_intreq_irq030mon_field +{ + __IO uint32_t ICUINT0 :1; + __IO uint32_t ICUINT1 :1; + __IO uint32_t ICUINT2 :1; + __IO uint32_t ICUINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq030mon_field_t; + +typedef struct stc_intreq_irq031mon_field +{ + __IO uint32_t OCUINT0 :1; + __IO uint32_t OCUINT1 :1; + __IO uint32_t OCUINT2 :1; + __IO uint32_t OCUINT3 :1; + __IO uint32_t OCUINT4 :1; + __IO uint32_t OCUINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq031mon_field_t; + +typedef struct stc_intreq_irq032mon_field +{ + __IO uint32_t FRT_PEAK_INT0 :1; + __IO uint32_t FRT_PEAK_INT1 :1; + __IO uint32_t FRT_PEAK_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq032mon_field_t; + +typedef struct stc_intreq_irq033mon_field +{ + __IO uint32_t FRT_ZERO_INT0 :1; + __IO uint32_t FRT_ZERO_INT1 :1; + __IO uint32_t FRT_ZERO_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq033mon_field_t; + +typedef struct stc_intreq_irq034mon_field +{ + __IO uint32_t ICUINT0 :1; + __IO uint32_t ICUINT1 :1; + __IO uint32_t ICUINT2 :1; + __IO uint32_t ICUINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq034mon_field_t; + +typedef struct stc_intreq_irq035mon_field +{ + __IO uint32_t OCUINT0 :1; + __IO uint32_t OCUINT1 :1; + __IO uint32_t OCUINT2 :1; + __IO uint32_t OCUINT3 :1; + __IO uint32_t OCUINT4 :1; + __IO uint32_t OCUINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq035mon_field_t; + +typedef struct stc_intreq_irq036mon_field +{ + __IO uint32_t PPGINT0 :1; + __IO uint32_t PPGINT1 :1; + __IO uint32_t PPGINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq036mon_field_t; + +typedef struct stc_intreq_irq037mon_field +{ + __IO uint32_t PPGINT0 :1; + __IO uint32_t PPGINT1 :1; + __IO uint32_t PPGINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq037mon_field_t; + +typedef struct stc_intreq_irq038mon_field +{ + __IO uint32_t PPGINT0 :1; + __IO uint32_t PPGINT1 :1; + __IO uint32_t PPGINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq038mon_field_t; + +typedef struct stc_intreq_irq039mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq039mon_field_t; + +typedef struct stc_intreq_irq040mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq040mon_field_t; + +typedef struct stc_intreq_irq041mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq041mon_field_t; + +typedef struct stc_intreq_irq042mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq042mon_field_t; + +typedef struct stc_intreq_irq043mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq043mon_field_t; + +typedef struct stc_intreq_irq044mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq044mon_field_t; + +typedef struct stc_intreq_irq045mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq045mon_field_t; + +typedef struct stc_intreq_irq046mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq046mon_field_t; + +typedef struct stc_intreq_irq047mon_field +{ + __IO uint32_t TIMINT1 :1; + __IO uint32_t TIMINT2 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq047mon_field_t; + +typedef struct stc_intreq_irq048mon_field +{ + __IO uint32_t WCINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq048mon_field_t; + +typedef struct stc_intreq_irq049mon_field +{ + __IO uint32_t BMEMCS :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq049mon_field_t; + +typedef struct stc_intreq_irq050mon_field +{ + __IO uint32_t RTCINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq050mon_field_t; + +typedef struct stc_intreq_irq051mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq051mon_field_t; + +typedef struct stc_intreq_irq052mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq052mon_field_t; + +typedef struct stc_intreq_irq053mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq053mon_field_t; + +typedef struct stc_intreq_irq054mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq054mon_field_t; + +typedef struct stc_intreq_irq055mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq055mon_field_t; + +typedef struct stc_intreq_irq056mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq056mon_field_t; + +typedef struct stc_intreq_irq057mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq057mon_field_t; + +typedef struct stc_intreq_irq058mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq058mon_field_t; + +typedef struct stc_intreq_irq059mon_field +{ + __IO uint32_t MOSCINT :1; + __IO uint32_t SOSCINT :1; + __IO uint32_t MPLLINT :1; + __IO uint32_t UPLLINT :1; + __IO uint32_t IPLLINT :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq059mon_field_t; + +typedef struct stc_intreq_irq060mon_field +{ + __IO uint32_t MFSINT0_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq060mon_field_t; + +typedef struct stc_intreq_irq061mon_field +{ + __IO uint32_t MFSINT0_TX :1; + __IO uint32_t MFSINT0_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq061mon_field_t; + +typedef struct stc_intreq_irq062mon_field +{ + __IO uint32_t MFSINT1_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq062mon_field_t; + +typedef struct stc_intreq_irq063mon_field +{ + __IO uint32_t MFSINT1_TX :1; + __IO uint32_t MFSINT1_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq063mon_field_t; + +typedef struct stc_intreq_irq064mon_field +{ + __IO uint32_t MFSINT2_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq064mon_field_t; + +typedef struct stc_intreq_irq065mon_field +{ + __IO uint32_t MFSINT2_TX :1; + __IO uint32_t MFSINT2_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq065mon_field_t; + +typedef struct stc_intreq_irq066mon_field +{ + __IO uint32_t MFSINT3_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq066mon_field_t; + +typedef struct stc_intreq_irq067mon_field +{ + __IO uint32_t MFSINT3_TX :1; + __IO uint32_t MFSINT3_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq067mon_field_t; + +typedef struct stc_intreq_irq068mon_field +{ + __IO uint32_t MFSINT4_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq068mon_field_t; + +typedef struct stc_intreq_irq069mon_field +{ + __IO uint32_t MFSINT4_TX :1; + __IO uint32_t MFSINT4_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq069mon_field_t; + +typedef struct stc_intreq_irq070mon_field +{ + __IO uint32_t MFSINT5_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq070mon_field_t; + +typedef struct stc_intreq_irq071mon_field +{ + __IO uint32_t MFSINT5_TX :1; + __IO uint32_t MFSINT5_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq071mon_field_t; + +typedef struct stc_intreq_irq072mon_field +{ + __IO uint32_t MFSINT6_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq072mon_field_t; + +typedef struct stc_intreq_irq073mon_field +{ + __IO uint32_t MFSINT6_TX :1; + __IO uint32_t MFSINT6_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq073mon_field_t; + +typedef struct stc_intreq_irq074mon_field +{ + __IO uint32_t MFSINT7_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq074mon_field_t; + +typedef struct stc_intreq_irq075mon_field +{ + __IO uint32_t MFSINT7_TX :1; + __IO uint32_t MFSINT7_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq075mon_field_t; + +typedef struct stc_intreq_irq076mon_field +{ + __IO uint32_t ADCINT0 :1; + __IO uint32_t ADCINT1 :1; + __IO uint32_t ADCINT2 :1; + __IO uint32_t ADCINT3 :1; + __IO uint32_t ADCINT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq076mon_field_t; + +typedef struct stc_intreq_irq077mon_field +{ + __IO uint32_t ADCINT0 :1; + __IO uint32_t ADCINT1 :1; + __IO uint32_t ADCINT2 :1; + __IO uint32_t ADCINT3 :1; + __IO uint32_t ADCINT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq077mon_field_t; + +typedef struct stc_intreq_irq078mon_field +{ + __IO uint32_t USB_DRQ_INT0 :1; + __IO uint32_t USB_DRQ_INT1 :1; + __IO uint32_t USB_DRQ_INT2 :1; + __IO uint32_t USB_DRQ_INT3 :1; + __IO uint32_t USB_DRQ_INT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq078mon_field_t; + +typedef struct stc_intreq_irq079mon_field +{ + __IO uint32_t USB_INT0 :1; + __IO uint32_t USB_INT1 :1; + __IO uint32_t USB_INT2 :1; + __IO uint32_t USB_INT3 :1; + __IO uint32_t USB_INT4 :1; + __IO uint32_t USB_INT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq079mon_field_t; + +typedef struct stc_intreq_irq080mon_field +{ + __IO uint32_t CANINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq080mon_field_t; + +typedef struct stc_intreq_irq081mon_field +{ + __IO uint32_t CANINT :1; + __IO uint32_t CANDEINT :1; + __IO uint32_t CANSEINT :1; + __IO uint32_t CAN0INT :1; + __IO uint32_t CAN1INT :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq081mon_field_t; + +typedef struct stc_intreq_irq082mon_field +{ + __IO uint32_t MACSBD :1; + __IO uint32_t MACPMT :1; + __IO uint32_t MACLPI :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq082mon_field_t; + +typedef struct stc_intreq_irq083mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq083mon_field_t; + +typedef struct stc_intreq_irq084mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq084mon_field_t; + +typedef struct stc_intreq_irq085mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq085mon_field_t; + +typedef struct stc_intreq_irq086mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq086mon_field_t; + +typedef struct stc_intreq_irq087mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq087mon_field_t; + +typedef struct stc_intreq_irq088mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq088mon_field_t; + +typedef struct stc_intreq_irq089mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq089mon_field_t; + +typedef struct stc_intreq_irq090mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq090mon_field_t; + +typedef struct stc_intreq_irq091mon_field +{ + __IO uint32_t DSTCINT0 :1; + __IO uint32_t DSTCINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq091mon_field_t; + +typedef struct stc_intreq_irq092mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq092mon_field_t; + +typedef struct stc_intreq_irq093mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq093mon_field_t; + +typedef struct stc_intreq_irq094mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq094mon_field_t; + +typedef struct stc_intreq_irq095mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq095mon_field_t; + +typedef struct stc_intreq_irq096mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq096mon_field_t; + +typedef struct stc_intreq_irq097mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq097mon_field_t; + +typedef struct stc_intreq_irq098mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq098mon_field_t; + +typedef struct stc_intreq_irq099mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq099mon_field_t; + +typedef struct stc_intreq_irq100mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq100mon_field_t; + +typedef struct stc_intreq_irq101mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq101mon_field_t; + +typedef struct stc_intreq_irq102mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t BTINT2 :1; + __IO uint32_t BTINT3 :1; + __IO uint32_t BTINT4 :1; + __IO uint32_t BTINT5 :1; + __IO uint32_t BTINT6 :1; + __IO uint32_t BTINT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq102mon_field_t; + +typedef struct stc_intreq_irq103mon_field +{ + __IO uint32_t MFSINT8_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq103mon_field_t; + +typedef struct stc_intreq_irq104mon_field +{ + __IO uint32_t MFSINT8_TX :1; + __IO uint32_t MFSINT8_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq104mon_field_t; + +typedef struct stc_intreq_irq105mon_field +{ + __IO uint32_t MFSINT9_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq105mon_field_t; + +typedef struct stc_intreq_irq106mon_field +{ + __IO uint32_t MFSINT9_TX :1; + __IO uint32_t MFSINT9_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq106mon_field_t; + +typedef struct stc_intreq_irq107mon_field +{ + __IO uint32_t MFSINT10_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq107mon_field_t; + +typedef struct stc_intreq_irq108mon_field +{ + __IO uint32_t MFSINT10_TX :1; + __IO uint32_t MFSINT10_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq108mon_field_t; + +typedef struct stc_intreq_irq109mon_field +{ + __IO uint32_t MFSINT11_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq109mon_field_t; + +typedef struct stc_intreq_irq110mon_field +{ + __IO uint32_t MFSINT11_TX :1; + __IO uint32_t MFSINT11_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq110mon_field_t; + +typedef struct stc_intreq_irq111mon_field +{ + __IO uint32_t ADCINT0 :1; + __IO uint32_t ADCINT1 :1; + __IO uint32_t ADCINT2 :1; + __IO uint32_t ADCINT3 :1; + __IO uint32_t ADCINT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq111mon_field_t; + +typedef struct stc_intreq_irq112mon_field +{ + __IO uint32_t I2SDINT0 :1; + __IO uint32_t I2SDINT1 :1; + __IO uint32_t HSSPIDINT0 :1; + __IO uint32_t HSSPIDINT1 :1; + __IO uint32_t PCRCDINT :1; + __IO uint32_t CANDINT :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq112mon_field_t; + +typedef struct stc_intreq_irq113mon_field +{ + __IO uint32_t USB_DRQ_INT0 :1; + __IO uint32_t USB_DRQ_INT1 :1; + __IO uint32_t USB_DRQ_INT2 :1; + __IO uint32_t USB_DRQ_INT3 :1; + __IO uint32_t USB_DRQ_INT4 :1; + __IO uint32_t RCEC0INT :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq113mon_field_t; + +typedef struct stc_intreq_irq114mon_field +{ + __IO uint32_t USB_INT0 :1; + __IO uint32_t USB_INT1 :1; + __IO uint32_t USB_INT2 :1; + __IO uint32_t USB_INT3 :1; + __IO uint32_t USB_INT4 :1; + __IO uint32_t USB_INT5 :1; + __IO uint32_t RCEC1INT :1; + __IO uint32_t RESERVED0 :25; +} stc_intreq_irq114mon_field_t; + +typedef struct stc_intreq_irq115mon_field +{ + __IO uint32_t HSSPIINT0 :1; + __IO uint32_t HSSPIINT1 :1; + __IO uint32_t HSSPIINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq115mon_field_t; + +typedef struct stc_intreq_irq117mon_field +{ + __IO uint32_t I2SINT :1; + __IO uint32_t PCRC :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq117mon_field_t; + +typedef struct stc_intreq_irq118mon_field +{ + __IO uint32_t SDINT0 :1; + __IO uint32_t SDINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq118mon_field_t; + +typedef struct stc_intreq_irq119mon_field +{ + __IO uint32_t FLINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq119mon_field_t; + +typedef struct stc_intreq_irq120mon_field +{ + __IO uint32_t MFSINT12_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq120mon_field_t; + +typedef struct stc_intreq_irq121mon_field +{ + __IO uint32_t MFSINT12_TX :1; + __IO uint32_t MFSINT12_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq121mon_field_t; + +typedef struct stc_intreq_irq122mon_field +{ + __IO uint32_t MFSINT13_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq122mon_field_t; + +typedef struct stc_intreq_irq123mon_field +{ + __IO uint32_t MFSINT13_TX :1; + __IO uint32_t MFSINT13_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq123mon_field_t; + +typedef struct stc_intreq_irq124mon_field +{ + __IO uint32_t MFSINT14_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq124mon_field_t; + +typedef struct stc_intreq_irq125mon_field +{ + __IO uint32_t MFSINT14_TX :1; + __IO uint32_t MFSINT14_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq125mon_field_t; + +typedef struct stc_intreq_irq126mon_field +{ + __IO uint32_t MFSINT15_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq126mon_field_t; + +typedef struct stc_intreq_irq127mon_field +{ + __IO uint32_t MFSINT15_TX :1; + __IO uint32_t MFSINT15_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq127mon_field_t; + +/******************************************************************************* +* LSCRP_MODULE +*******************************************************************************/ +typedef struct stc_lscrp_lcr_prsld_field +{ + union { + struct { + __IO uint8_t LCR_PRSLD :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t LCR_PRSLD0 :1; + __IO uint8_t LCR_PRSLD1 :1; + __IO uint8_t LCR_PRSLD2 :1; + __IO uint8_t LCR_PRSLD3 :1; + __IO uint8_t LCR_PRSLD4 :1; + __IO uint8_t LCR_PRSLD5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_lscrp_lcr_prsld_field_t; + +/******************************************************************************* +* LVD_MODULE +*******************************************************************************/ +typedef struct stc_lvd_lvd_ctl_field +{ + union { + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t SVHI :5; + __IO uint8_t LVDIE :1; + }; + struct { + __IO uint8_t RESERVED1 :2; + __IO uint8_t SVHI0 :1; + __IO uint8_t SVHI1 :1; + __IO uint8_t SVHI2 :1; + __IO uint8_t SVHI3 :1; + __IO uint8_t SVHI4 :1; + __IO uint8_t RESERVED2 :1; + }; + }; +} stc_lvd_lvd_ctl_field_t; + +typedef struct stc_lvd_lvd_str_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t LVDIR :1; +} stc_lvd_lvd_str_field_t; + +typedef struct stc_lvd_lvd_clr_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t LVDCL :1; +} stc_lvd_lvd_clr_field_t; + +typedef struct stc_lvd_lvd_rlr_field +{ + union { + struct { + __IO uint32_t LVDLCK :32; + }; + struct { + __IO uint32_t LVDLCK0 :1; + __IO uint32_t LVDLCK1 :1; + __IO uint32_t LVDLCK2 :1; + __IO uint32_t LVDLCK3 :1; + __IO uint32_t LVDLCK4 :1; + __IO uint32_t LVDLCK5 :1; + __IO uint32_t LVDLCK6 :1; + __IO uint32_t LVDLCK7 :1; + __IO uint32_t LVDLCK8 :1; + __IO uint32_t LVDLCK9 :1; + __IO uint32_t LVDLCK10 :1; + __IO uint32_t LVDLCK11 :1; + __IO uint32_t LVDLCK12 :1; + __IO uint32_t LVDLCK13 :1; + __IO uint32_t LVDLCK14 :1; + __IO uint32_t LVDLCK15 :1; + __IO uint32_t LVDLCK16 :1; + __IO uint32_t LVDLCK17 :1; + __IO uint32_t LVDLCK18 :1; + __IO uint32_t LVDLCK19 :1; + __IO uint32_t LVDLCK20 :1; + __IO uint32_t LVDLCK21 :1; + __IO uint32_t LVDLCK22 :1; + __IO uint32_t LVDLCK23 :1; + __IO uint32_t LVDLCK24 :1; + __IO uint32_t LVDLCK25 :1; + __IO uint32_t LVDLCK26 :1; + __IO uint32_t LVDLCK27 :1; + __IO uint32_t LVDLCK28 :1; + __IO uint32_t LVDLCK29 :1; + __IO uint32_t LVDLCK30 :1; + __IO uint32_t LVDLCK31 :1; + }; + }; +} stc_lvd_lvd_rlr_field_t; + +typedef struct stc_lvd_lvd_str2_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t LVDIRDY :1; +} stc_lvd_lvd_str2_field_t; + +/******************************************************************************* +* MFS_MODULE +*******************************************************************************/ +typedef struct stc_mfs_smr_field +{ + union { + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t SCKE :1; + __IO uint8_t BDS :1; + __IO uint8_t SCINV :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED1 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; + union { + struct { + __IO uint8_t RESERVED2 :2; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t RESERVED3 :4; + }; + struct { + __IO uint8_t RESERVED4 :8; + }; + }; + union { + struct { + __IO uint8_t RESERVED5 :3; + __IO uint8_t SBL :1; + __IO uint8_t WUCR :1; + __IO uint8_t RESERVED6 :3; + }; + struct { + __IO uint8_t RESERVED7 :8; + }; + }; + }; +} stc_mfs_smr_field_t; + +typedef struct stc_mfs_ibcr_field +{ + union { + struct { + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t SPI :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; + }; + struct { + __IO uint8_t INT :1; + __IO uint8_t BER :1; + __IO uint8_t INTE :1; + __IO uint8_t CNDE :1; + __IO uint8_t WSEL :1; + __IO uint8_t ACKE :1; + __IO uint8_t ACT_SCC :1; + __IO uint8_t MSS :1; + }; + struct { + __IO uint8_t RESERVED2 :5; + __IO uint8_t LBR :1; + __IO uint8_t RESERVED3 :2; + }; + }; +} stc_mfs_ibcr_field_t; + +typedef struct stc_mfs_scr_field +{ + union { + struct { + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t SPI :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; + }; + struct { + __IO uint8_t INT :1; + __IO uint8_t BER :1; + __IO uint8_t INTE :1; + __IO uint8_t CNDE :1; + __IO uint8_t WSEL :1; + __IO uint8_t ACKE :1; + __IO uint8_t ACT_SCC :1; + __IO uint8_t MSS :1; + }; + struct { + __IO uint8_t RESERVED2 :5; + __IO uint8_t LBR :1; + __IO uint8_t RESERVED3 :2; + }; + }; +} stc_mfs_scr_field_t; + +typedef struct stc_mfs_escr_field +{ + union { + union { + struct { + __IO uint8_t L :3; + __IO uint8_t WT :2; + __IO uint8_t CSFE :1; + __IO uint8_t L3 :1; + __IO uint8_t SOP :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t WT0 :1; + __IO uint8_t WT1 :1; + __IO uint8_t RESERVED0 :3; + }; + }; + struct { + __IO uint8_t BB :1; + __IO uint8_t SPC :1; + __IO uint8_t RSC :1; + __IO uint8_t AL :1; + __IO uint8_t TRX :1; + __IO uint8_t RSA :1; + __IO uint8_t RACK :1; + __IO uint8_t FBT :1; + }; + union { + struct { + __IO uint8_t DEL :2; + __IO uint8_t LBL :2; + __IO uint8_t LBIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t ESBL :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t DEL0 :1; + __IO uint8_t DEL1 :1; + __IO uint8_t LBL0 :1; + __IO uint8_t LBL1 :1; + __IO uint8_t RESERVED4 :4; + }; + }; + union { + struct { + __IO uint8_t RESERVED5 :3; + __IO uint8_t P :1; + __IO uint8_t PEN :1; + __IO uint8_t INV :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t FLWEN :1; + }; + struct { + __IO uint8_t RESERVED7 :8; + }; + }; + }; +} stc_mfs_escr_field_t; + +typedef struct stc_mfs_ibsr_field +{ + union { + union { + struct { + __IO uint8_t L :3; + __IO uint8_t WT :2; + __IO uint8_t CSFE :1; + __IO uint8_t L3 :1; + __IO uint8_t SOP :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t WT0 :1; + __IO uint8_t WT1 :1; + __IO uint8_t RESERVED0 :3; + }; + }; + struct { + __IO uint8_t BB :1; + __IO uint8_t SPC :1; + __IO uint8_t RSC :1; + __IO uint8_t AL :1; + __IO uint8_t TRX :1; + __IO uint8_t RSA :1; + __IO uint8_t RACK :1; + __IO uint8_t FBT :1; + }; + union { + struct { + __IO uint8_t DEL :2; + __IO uint8_t LBL :2; + __IO uint8_t LBIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t ESBL :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t DEL0 :1; + __IO uint8_t DEL1 :1; + __IO uint8_t LBL0 :1; + __IO uint8_t LBL1 :1; + __IO uint8_t RESERVED4 :4; + }; + }; + union { + struct { + __IO uint8_t RESERVED5 :3; + __IO uint8_t P :1; + __IO uint8_t PEN :1; + __IO uint8_t INV :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t FLWEN :1; + }; + struct { + __IO uint8_t RESERVED7 :8; + }; + }; + }; +} stc_mfs_ibsr_field_t; + +typedef struct stc_mfs_ssr_field +{ + union { + struct { + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t AWC :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t REC :1; + }; + struct { + __IO uint8_t RESERVED2 :4; + __IO uint8_t TBIE :1; + __IO uint8_t DMA :1; + __IO uint8_t TSET :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t RESERVED5 :4; + __IO uint8_t FRE :1; + __IO uint8_t LBD :1; + __IO uint8_t RESERVED6 :2; + }; + struct { + __IO uint8_t RESERVED8 :5; + __IO uint8_t PE :1; + __IO uint8_t RESERVED9 :2; + }; + }; +} stc_mfs_ssr_field_t; + +typedef struct stc_mfs_rdr_field +{ + union { + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; + }; +} stc_mfs_rdr_field_t; + +typedef struct stc_mfs_tdr_field +{ + union { + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; + }; +} stc_mfs_tdr_field_t; + +typedef struct stc_mfs_bgr_field +{ + union { + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED1 :1; + }; + }; + union { + struct { + __IO uint16_t RESERVED4 :15; + __IO uint16_t EXT :1; + }; + struct { + __IO uint16_t RESERVED5 :16; + }; + }; + }; +} stc_mfs_bgr_field_t; + +typedef struct stc_mfs_isba_field +{ + union { + struct { + __IO uint8_t SA :7; + __IO uint8_t SAEN :1; + }; + struct { + __IO uint8_t SA0 :1; + __IO uint8_t SA1 :1; + __IO uint8_t SA2 :1; + __IO uint8_t SA3 :1; + __IO uint8_t SA4 :1; + __IO uint8_t SA5 :1; + __IO uint8_t SA6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_isba_field_t; + +typedef struct stc_mfs_ismk_field +{ + union { + struct { + __IO uint8_t SM :7; + __IO uint8_t EN :1; + }; + struct { + __IO uint8_t SM0 :1; + __IO uint8_t SM1 :1; + __IO uint8_t SM2 :1; + __IO uint8_t SM3 :1; + __IO uint8_t SM4 :1; + __IO uint8_t SM5 :1; + __IO uint8_t SM6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_ismk_field_t; + +typedef struct stc_mfs_fcr_field +{ + union { + struct { + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED1 :3; + }; + }; +} stc_mfs_fcr_field_t; + +typedef struct stc_mfs_fbyte1_field +{ + union { + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; + }; +} stc_mfs_fbyte1_field_t; + +typedef struct stc_mfs_fbyte2_field +{ + union { + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; + }; +} stc_mfs_fbyte2_field_t; + +typedef struct stc_mfs_nfcr_field +{ + union { + union { + struct { + __IO uint8_t CSHD :8; + }; + struct { + __IO uint8_t CSHD0 :1; + __IO uint8_t CSHD1 :1; + __IO uint8_t CSHD2 :1; + __IO uint8_t CSHD3 :1; + __IO uint8_t CSHD4 :1; + __IO uint8_t CSHD5 :1; + __IO uint8_t CSHD6 :1; + __IO uint8_t CSHD7 :1; + }; + }; + union { + struct { + __IO uint8_t NFT :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t NFT0 :1; + __IO uint8_t NFT1 :1; + __IO uint8_t NFT2 :1; + __IO uint8_t NFT3 :1; + __IO uint8_t NFT4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; + }; +} stc_mfs_nfcr_field_t; + +typedef struct stc_mfs_scstr0_field +{ + union { + union { + struct { + __IO uint8_t CSHD :8; + }; + struct { + __IO uint8_t CSHD0 :1; + __IO uint8_t CSHD1 :1; + __IO uint8_t CSHD2 :1; + __IO uint8_t CSHD3 :1; + __IO uint8_t CSHD4 :1; + __IO uint8_t CSHD5 :1; + __IO uint8_t CSHD6 :1; + __IO uint8_t CSHD7 :1; + }; + }; + union { + struct { + __IO uint8_t NFT :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t NFT0 :1; + __IO uint8_t NFT1 :1; + __IO uint8_t NFT2 :1; + __IO uint8_t NFT3 :1; + __IO uint8_t NFT4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; + }; +} stc_mfs_scstr0_field_t; + +typedef struct stc_mfs_eibcr_field +{ + union { + union { + struct { + __IO uint8_t CSSU :8; + }; + struct { + __IO uint8_t CSSU0 :1; + __IO uint8_t CSSU1 :1; + __IO uint8_t CSSU2 :1; + __IO uint8_t CSSU3 :1; + __IO uint8_t CSSU4 :1; + __IO uint8_t CSSU5 :1; + __IO uint8_t CSSU6 :1; + __IO uint8_t CSSU7 :1; + }; + }; + struct { + __IO uint8_t BEC :1; + __IO uint8_t SOCE :1; + __IO uint8_t SCLC :1; + __IO uint8_t SDAC :1; + __IO uint8_t SCLS :1; + __IO uint8_t SDAS :1; + __IO uint8_t RESERVED0 :2; + }; + }; +} stc_mfs_eibcr_field_t; + +typedef struct stc_mfs_scstr1_field +{ + union { + union { + struct { + __IO uint8_t CSSU :8; + }; + struct { + __IO uint8_t CSSU0 :1; + __IO uint8_t CSSU1 :1; + __IO uint8_t CSSU2 :1; + __IO uint8_t CSSU3 :1; + __IO uint8_t CSSU4 :1; + __IO uint8_t CSSU5 :1; + __IO uint8_t CSSU6 :1; + __IO uint8_t CSSU7 :1; + }; + }; + struct { + __IO uint8_t BEC :1; + __IO uint8_t SOCE :1; + __IO uint8_t SCLC :1; + __IO uint8_t SDAC :1; + __IO uint8_t SCLS :1; + __IO uint8_t SDAS :1; + __IO uint8_t RESERVED0 :2; + }; + }; +} stc_mfs_scstr1_field_t; + +typedef struct stc_mfs_scstr32_field +{ + union { + struct { + __IO uint16_t CSDS :16; + }; + struct { + __IO uint16_t CSDS0 :1; + __IO uint16_t CSDS1 :1; + __IO uint16_t CSDS2 :1; + __IO uint16_t CSDS3 :1; + __IO uint16_t CSDS4 :1; + __IO uint16_t CSDS5 :1; + __IO uint16_t CSDS6 :1; + __IO uint16_t CSDS7 :1; + __IO uint16_t CSDS8 :1; + __IO uint16_t CSDS9 :1; + __IO uint16_t CSDS10 :1; + __IO uint16_t CSDS11 :1; + __IO uint16_t CSDS12 :1; + __IO uint16_t CSDS13 :1; + __IO uint16_t CSDS14 :1; + __IO uint16_t CSDS15 :1; + }; + }; +} stc_mfs_scstr32_field_t; + +typedef struct stc_mfs_sacsr_field +{ + union { + struct { + __IO uint16_t TMRE :1; + __IO uint16_t TDIV :4; + __IO uint16_t RESERVED1 :1; + __IO uint16_t TSYNE :1; + __IO uint16_t TINTE :1; + __IO uint16_t TINT :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t CSE :1; + __IO uint16_t CSEIE :1; + __IO uint16_t TBEEN :1; + __IO uint16_t RESERVED3 :2; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TDIV0 :1; + __IO uint16_t TDIV1 :1; + __IO uint16_t TDIV2 :1; + __IO uint16_t TDIV3 :1; + __IO uint16_t RESERVED4 :11; + }; + }; +} stc_mfs_sacsr_field_t; + +typedef struct stc_mfs_stmr_field +{ + union { + struct { + __IO uint16_t TM :16; + }; + struct { + __IO uint16_t TM0 :1; + __IO uint16_t TM1 :1; + __IO uint16_t TM2 :1; + __IO uint16_t TM3 :1; + __IO uint16_t TM4 :1; + __IO uint16_t TM5 :1; + __IO uint16_t TM6 :1; + __IO uint16_t TM7 :1; + __IO uint16_t TM8 :1; + __IO uint16_t TM9 :1; + __IO uint16_t TM10 :1; + __IO uint16_t TM11 :1; + __IO uint16_t TM12 :1; + __IO uint16_t TM13 :1; + __IO uint16_t TM14 :1; + __IO uint16_t TM15 :1; + }; + }; +} stc_mfs_stmr_field_t; + +typedef struct stc_mfs_stmcr_field +{ + union { + struct { + __IO uint16_t TC :16; + }; + struct { + __IO uint16_t TC0 :1; + __IO uint16_t TC1 :1; + __IO uint16_t TC2 :1; + __IO uint16_t TC3 :1; + __IO uint16_t TC4 :1; + __IO uint16_t TC5 :1; + __IO uint16_t TC6 :1; + __IO uint16_t TC7 :1; + __IO uint16_t TC8 :1; + __IO uint16_t TC9 :1; + __IO uint16_t TC10 :1; + __IO uint16_t TC11 :1; + __IO uint16_t TC12 :1; + __IO uint16_t TC13 :1; + __IO uint16_t TC14 :1; + __IO uint16_t TC15 :1; + }; + }; +} stc_mfs_stmcr_field_t; + +typedef struct stc_mfs_scscr_field +{ + union { + struct { + __IO uint16_t CSOE :1; + __IO uint16_t CSEN0 :1; + __IO uint16_t CSEN1 :1; + __IO uint16_t CSEN2 :1; + __IO uint16_t CSEN3 :1; + __IO uint16_t CSLVL :1; + __IO uint16_t CDIV :3; + __IO uint16_t SCAM :1; + __IO uint16_t SCD :2; + __IO uint16_t SED :2; + __IO uint16_t SST :2; + }; + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CDIV0 :1; + __IO uint16_t CDIV1 :1; + __IO uint16_t CDIV2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SCD0 :1; + __IO uint16_t SCD1 :1; + __IO uint16_t SED0 :1; + __IO uint16_t SED1 :1; + __IO uint16_t SST0 :1; + __IO uint16_t SST1 :1; + }; + }; +} stc_mfs_scscr_field_t; + +typedef struct stc_mfs_scsfr0_field +{ + union { + struct { + __IO uint8_t CS1L :5; + __IO uint8_t CS1SPI :1; + __IO uint8_t CS1SCINV :1; + __IO uint8_t CS1CSLVL :1; + }; + struct { + __IO uint8_t CS1L0 :1; + __IO uint8_t CS1L1 :1; + __IO uint8_t CS1L2 :1; + __IO uint8_t CS1L3 :1; + __IO uint8_t CS1L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_scsfr0_field_t; + +typedef struct stc_mfs_scsfr1_field +{ + union { + struct { + __IO uint8_t CS2L :5; + __IO uint8_t CS2SPI :1; + __IO uint8_t CS2SCINV :1; + __IO uint8_t CS2CSLVL :1; + }; + struct { + __IO uint8_t CS2L0 :1; + __IO uint8_t CS2L1 :1; + __IO uint8_t CS2L2 :1; + __IO uint8_t CS2L3 :1; + __IO uint8_t CS2L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_scsfr1_field_t; + +typedef struct stc_mfs_scsfr2_field +{ + union { + struct { + __IO uint8_t CS3L :5; + __IO uint8_t CS3SPI :1; + __IO uint8_t CS3SCINV :1; + __IO uint8_t CS3CSLVL :1; + }; + struct { + __IO uint8_t CS3L0 :1; + __IO uint8_t CS3L1 :1; + __IO uint8_t CS3L2 :1; + __IO uint8_t CS3L3 :1; + __IO uint8_t CS3L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_scsfr2_field_t; + +typedef struct stc_mfs_csio_smr_field +{ + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t SCKE :1; + __IO uint8_t BDS :1; + __IO uint8_t SCINV :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED1 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_csio_smr_field_t; + +typedef struct stc_mfs_i2c_smr_field +{ + union { + struct { + __IO uint8_t RESERVED2 :2; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t RESERVED3 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED4 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_i2c_smr_field_t; + +typedef struct stc_mfs_lin_smr_field +{ + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t RESERVED5 :2; + __IO uint8_t SBL :1; + __IO uint8_t WUCR :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED6 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_lin_smr_field_t; + +typedef struct stc_mfs_uart_smr_field +{ + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t RESERVED7 :1; + __IO uint8_t BDS :1; + __IO uint8_t SBL :1; + __IO uint8_t RESERVED8 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED9 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_uart_smr_field_t; + +typedef struct stc_mfs_csio_scr_field +{ + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t SPI :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; +} stc_mfs_csio_scr_field_t; + +typedef struct stc_mfs_i2c_ibcr_field +{ + __IO uint8_t INT :1; + __IO uint8_t BER :1; + __IO uint8_t INTE :1; + __IO uint8_t CNDE :1; + __IO uint8_t WSEL :1; + __IO uint8_t ACKE :1; + __IO uint8_t ACT_SCC :1; + __IO uint8_t MSS :1; +} stc_mfs_i2c_ibcr_field_t; + +typedef struct stc_mfs_lin_scr_field +{ + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t LBR :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; +} stc_mfs_lin_scr_field_t; + +typedef struct stc_mfs_uart_scr_field +{ + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t RESERVED3 :2; + __IO uint8_t UPCL :1; +} stc_mfs_uart_scr_field_t; + +typedef struct stc_mfs_csio_escr_field +{ + union { + struct { + __IO uint8_t L :3; + __IO uint8_t WT :2; + __IO uint8_t CSFE :1; + __IO uint8_t L3 :1; + __IO uint8_t SOP :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t WT0 :1; + __IO uint8_t WT1 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_escr_field_t; + +typedef struct stc_mfs_i2c_ibsr_field +{ + __IO uint8_t BB :1; + __IO uint8_t SPC :1; + __IO uint8_t RSC :1; + __IO uint8_t AL :1; + __IO uint8_t TRX :1; + __IO uint8_t RSA :1; + __IO uint8_t RACK :1; + __IO uint8_t FBT :1; +} stc_mfs_i2c_ibsr_field_t; + +typedef struct stc_mfs_lin_escr_field +{ + union { + struct { + __IO uint8_t DEL :2; + __IO uint8_t LBL :2; + __IO uint8_t LBIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t ESBL :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t DEL0 :1; + __IO uint8_t DEL1 :1; + __IO uint8_t LBL0 :1; + __IO uint8_t LBL1 :1; + __IO uint8_t RESERVED4 :4; + }; + }; +} stc_mfs_lin_escr_field_t; + +typedef struct stc_mfs_uart_escr_field +{ + union { + struct { + __IO uint8_t L :3; + __IO uint8_t P :1; + __IO uint8_t PEN :1; + __IO uint8_t INV :1; + __IO uint8_t ESBL :1; + __IO uint8_t FLWEN :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t RESERVED5 :5; + }; + }; +} stc_mfs_uart_escr_field_t; + +typedef struct stc_mfs_csio_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t AWC :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t REC :1; +} stc_mfs_csio_ssr_field_t; + +typedef struct stc_mfs_i2c_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t TBIE :1; + __IO uint8_t DMA :1; + __IO uint8_t TSET :1; + __IO uint8_t REC :1; +} stc_mfs_i2c_ssr_field_t; + +typedef struct stc_mfs_lin_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t FRE :1; + __IO uint8_t LBD :1; + __IO uint8_t RESERVED3 :1; + __IO uint8_t REC :1; +} stc_mfs_lin_ssr_field_t; + +typedef struct stc_mfs_uart_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t FRE :1; + __IO uint8_t PE :1; + __IO uint8_t RESERVED5 :1; + __IO uint8_t REC :1; +} stc_mfs_uart_ssr_field_t; + +typedef struct stc_mfs_csio_rdr_field +{ + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; +} stc_mfs_csio_rdr_field_t; + +typedef struct stc_mfs_csio_tdr_field +{ + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; +} stc_mfs_csio_tdr_field_t; + +typedef struct stc_mfs_i2c_rdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mfs_i2c_rdr_field_t; + +typedef struct stc_mfs_i2c_tdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED2 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED3 :8; + }; + }; +} stc_mfs_i2c_tdr_field_t; + +typedef struct stc_mfs_lin_rdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED4 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED5 :8; + }; + }; +} stc_mfs_lin_rdr_field_t; + +typedef struct stc_mfs_lin_tdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED6 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED7 :8; + }; + }; +} stc_mfs_lin_tdr_field_t; + +typedef struct stc_mfs_uart_rdr_field +{ + union { + struct { + __IO uint16_t D :9; + __IO uint16_t RESERVED8 :7; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t RESERVED9 :7; + }; + }; +} stc_mfs_uart_rdr_field_t; + +typedef struct stc_mfs_uart_tdr_field +{ + union { + struct { + __IO uint16_t D :9; + __IO uint16_t RESERVED10 :7; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t RESERVED11 :7; + }; + }; +} stc_mfs_uart_tdr_field_t; + +typedef struct stc_mfs_csio_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_mfs_csio_bgr_field_t; + +typedef struct stc_mfs_i2c_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t RESERVED2 :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED3 :1; + }; + }; +} stc_mfs_i2c_bgr_field_t; + +typedef struct stc_mfs_lin_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t EXT :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED4 :1; + }; + }; +} stc_mfs_lin_bgr_field_t; + +typedef struct stc_mfs_uart_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t EXT :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_mfs_uart_bgr_field_t; + +typedef struct stc_mfs_i2c_isba_field +{ + union { + struct { + __IO uint8_t SA :7; + __IO uint8_t SAEN :1; + }; + struct { + __IO uint8_t SA0 :1; + __IO uint8_t SA1 :1; + __IO uint8_t SA2 :1; + __IO uint8_t SA3 :1; + __IO uint8_t SA4 :1; + __IO uint8_t SA5 :1; + __IO uint8_t SA6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_i2c_isba_field_t; + +typedef struct stc_mfs_i2c_ismk_field +{ + union { + struct { + __IO uint8_t SM :7; + __IO uint8_t EN :1; + }; + struct { + __IO uint8_t SM0 :1; + __IO uint8_t SM1 :1; + __IO uint8_t SM2 :1; + __IO uint8_t SM3 :1; + __IO uint8_t SM4 :1; + __IO uint8_t SM5 :1; + __IO uint8_t SM6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_i2c_ismk_field_t; + +typedef struct stc_mfs_csio_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED1 :3; +} stc_mfs_csio_fcr_field_t; + +typedef struct stc_mfs_i2c_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED3 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED4 :3; +} stc_mfs_i2c_fcr_field_t; + +typedef struct stc_mfs_lin_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED6 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED7 :3; +} stc_mfs_lin_fcr_field_t; + +typedef struct stc_mfs_uart_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED9 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED10 :3; +} stc_mfs_uart_fcr_field_t; + +typedef struct stc_mfs_csio_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_csio_fbyte1_field_t; + +typedef struct stc_mfs_i2c_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_i2c_fbyte1_field_t; + +typedef struct stc_mfs_lin_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_lin_fbyte1_field_t; + +typedef struct stc_mfs_uart_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_uart_fbyte1_field_t; + +typedef struct stc_mfs_csio_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_csio_fbyte2_field_t; + +typedef struct stc_mfs_i2c_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_i2c_fbyte2_field_t; + +typedef struct stc_mfs_lin_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_lin_fbyte2_field_t; + +typedef struct stc_mfs_uart_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_uart_fbyte2_field_t; + +typedef struct stc_mfs_csio_scstr0_field +{ + union { + struct { + __IO uint8_t CSHD :8; + }; + struct { + __IO uint8_t CSHD0 :1; + __IO uint8_t CSHD1 :1; + __IO uint8_t CSHD2 :1; + __IO uint8_t CSHD3 :1; + __IO uint8_t CSHD4 :1; + __IO uint8_t CSHD5 :1; + __IO uint8_t CSHD6 :1; + __IO uint8_t CSHD7 :1; + }; + }; +} stc_mfs_csio_scstr0_field_t; + +typedef struct stc_mfs_i2c_nfcr_field +{ + union { + struct { + __IO uint8_t NFT :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t NFT0 :1; + __IO uint8_t NFT1 :1; + __IO uint8_t NFT2 :1; + __IO uint8_t NFT3 :1; + __IO uint8_t NFT4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mfs_i2c_nfcr_field_t; + +typedef struct stc_mfs_csio_scstr1_field +{ + union { + struct { + __IO uint8_t CSSU :8; + }; + struct { + __IO uint8_t CSSU0 :1; + __IO uint8_t CSSU1 :1; + __IO uint8_t CSSU2 :1; + __IO uint8_t CSSU3 :1; + __IO uint8_t CSSU4 :1; + __IO uint8_t CSSU5 :1; + __IO uint8_t CSSU6 :1; + __IO uint8_t CSSU7 :1; + }; + }; +} stc_mfs_csio_scstr1_field_t; + +typedef struct stc_mfs_i2c_eibcr_field +{ + __IO uint8_t BEC :1; + __IO uint8_t SOCE :1; + __IO uint8_t SCLC :1; + __IO uint8_t SDAC :1; + __IO uint8_t SCLS :1; + __IO uint8_t SDAS :1; + __IO uint8_t RESERVED0 :2; +} stc_mfs_i2c_eibcr_field_t; + +typedef struct stc_mfs_csio_scstr32_field +{ + union { + struct { + __IO uint16_t CSDS :16; + }; + struct { + __IO uint16_t CSDS0 :1; + __IO uint16_t CSDS1 :1; + __IO uint16_t CSDS2 :1; + __IO uint16_t CSDS3 :1; + __IO uint16_t CSDS4 :1; + __IO uint16_t CSDS5 :1; + __IO uint16_t CSDS6 :1; + __IO uint16_t CSDS7 :1; + __IO uint16_t CSDS8 :1; + __IO uint16_t CSDS9 :1; + __IO uint16_t CSDS10 :1; + __IO uint16_t CSDS11 :1; + __IO uint16_t CSDS12 :1; + __IO uint16_t CSDS13 :1; + __IO uint16_t CSDS14 :1; + __IO uint16_t CSDS15 :1; + }; + }; +} stc_mfs_csio_scstr32_field_t; + +typedef struct stc_mfs_csio_sacsr_field +{ + union { + struct { + __IO uint16_t TMRE :1; + __IO uint16_t TDIV :4; + __IO uint16_t RESERVED1 :1; + __IO uint16_t TSYNE :1; + __IO uint16_t TINTE :1; + __IO uint16_t TINT :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t CSE :1; + __IO uint16_t CSEIE :1; + __IO uint16_t TBEEN :1; + __IO uint16_t RESERVED3 :2; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TDIV0 :1; + __IO uint16_t TDIV1 :1; + __IO uint16_t TDIV2 :1; + __IO uint16_t TDIV3 :1; + __IO uint16_t RESERVED4 :11; + }; + }; +} stc_mfs_csio_sacsr_field_t; + +typedef struct stc_mfs_csio_stmr_field +{ + union { + struct { + __IO uint16_t TM :16; + }; + struct { + __IO uint16_t TM0 :1; + __IO uint16_t TM1 :1; + __IO uint16_t TM2 :1; + __IO uint16_t TM3 :1; + __IO uint16_t TM4 :1; + __IO uint16_t TM5 :1; + __IO uint16_t TM6 :1; + __IO uint16_t TM7 :1; + __IO uint16_t TM8 :1; + __IO uint16_t TM9 :1; + __IO uint16_t TM10 :1; + __IO uint16_t TM11 :1; + __IO uint16_t TM12 :1; + __IO uint16_t TM13 :1; + __IO uint16_t TM14 :1; + __IO uint16_t TM15 :1; + }; + }; +} stc_mfs_csio_stmr_field_t; + +typedef struct stc_mfs_csio_stmcr_field +{ + union { + struct { + __IO uint16_t TC :16; + }; + struct { + __IO uint16_t TC0 :1; + __IO uint16_t TC1 :1; + __IO uint16_t TC2 :1; + __IO uint16_t TC3 :1; + __IO uint16_t TC4 :1; + __IO uint16_t TC5 :1; + __IO uint16_t TC6 :1; + __IO uint16_t TC7 :1; + __IO uint16_t TC8 :1; + __IO uint16_t TC9 :1; + __IO uint16_t TC10 :1; + __IO uint16_t TC11 :1; + __IO uint16_t TC12 :1; + __IO uint16_t TC13 :1; + __IO uint16_t TC14 :1; + __IO uint16_t TC15 :1; + }; + }; +} stc_mfs_csio_stmcr_field_t; + +typedef struct stc_mfs_csio_scscr_field +{ + union { + struct { + __IO uint16_t CSOE :1; + __IO uint16_t CSEN0 :1; + __IO uint16_t CSEN1 :1; + __IO uint16_t CSEN2 :1; + __IO uint16_t CSEN3 :1; + __IO uint16_t CSLVL :1; + __IO uint16_t CDIV :3; + __IO uint16_t SCAM :1; + __IO uint16_t SCD :2; + __IO uint16_t SED :2; + __IO uint16_t SST :2; + }; + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CDIV0 :1; + __IO uint16_t CDIV1 :1; + __IO uint16_t CDIV2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SCD0 :1; + __IO uint16_t SCD1 :1; + __IO uint16_t SED0 :1; + __IO uint16_t SED1 :1; + __IO uint16_t SST0 :1; + __IO uint16_t SST1 :1; + }; + }; +} stc_mfs_csio_scscr_field_t; + +typedef struct stc_mfs_csio_scsfr0_field +{ + union { + struct { + __IO uint8_t CS1L :5; + __IO uint8_t CS1SPI :1; + __IO uint8_t CS1SCINV :1; + __IO uint8_t CS1CSLVL :1; + }; + struct { + __IO uint8_t CS1L0 :1; + __IO uint8_t CS1L1 :1; + __IO uint8_t CS1L2 :1; + __IO uint8_t CS1L3 :1; + __IO uint8_t CS1L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_scsfr0_field_t; + +typedef struct stc_mfs_csio_scsfr1_field +{ + union { + struct { + __IO uint8_t CS2L :5; + __IO uint8_t CS2SPI :1; + __IO uint8_t CS2SCINV :1; + __IO uint8_t CS2CSLVL :1; + }; + struct { + __IO uint8_t CS2L0 :1; + __IO uint8_t CS2L1 :1; + __IO uint8_t CS2L2 :1; + __IO uint8_t CS2L3 :1; + __IO uint8_t CS2L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_scsfr1_field_t; + +typedef struct stc_mfs_csio_scsfr2_field +{ + union { + struct { + __IO uint8_t CS3L :5; + __IO uint8_t CS3SPI :1; + __IO uint8_t CS3SCINV :1; + __IO uint8_t CS3CSLVL :1; + }; + struct { + __IO uint8_t CS3L0 :1; + __IO uint8_t CS3L1 :1; + __IO uint8_t CS3L2 :1; + __IO uint8_t CS3L3 :1; + __IO uint8_t CS3L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_scsfr2_field_t; + +/******************************************************************************* +* MFT_MODULE +*******************************************************************************/ +typedef struct stc_mft_ocsa10_field +{ + __IO uint8_t CST0 :1; + __IO uint8_t CST1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE0 :1; + __IO uint8_t IOE1 :1; + __IO uint8_t IOP0 :1; + __IO uint8_t IOP1 :1; +} stc_mft_ocsa10_field_t; + +typedef struct stc_mft_ocsb10_field +{ + __IO uint8_t OTD0 :1; + __IO uint8_t OTD1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocsb10_field_t; + +typedef struct stc_mft_ocsd10_field +{ + union { + struct { + __IO uint16_t OCCP0BUFE :2; + __IO uint16_t OCCP1BUFE :2; + __IO uint16_t OCSE0BUFE :2; + __IO uint16_t OCSE1BUFE :2; + __IO uint16_t OPBM0 :1; + __IO uint16_t OPBM1 :1; + __IO uint16_t OEBM0 :1; + __IO uint16_t OEBM1 :1; + __IO uint16_t OFEX0 :1; + __IO uint16_t OFEX1 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP0BUFE0 :1; + __IO uint16_t OCCP0BUFE1 :1; + __IO uint16_t OCCP1BUFE0 :1; + __IO uint16_t OCCP1BUFE1 :1; + __IO uint16_t OCSE0BUFE0 :1; + __IO uint16_t OCSE0BUFE1 :1; + __IO uint16_t OCSE1BUFE0 :1; + __IO uint16_t OCSE1BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocsd10_field_t; + +typedef struct stc_mft_ocsa32_field +{ + __IO uint8_t CST2 :1; + __IO uint8_t CST3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE2 :1; + __IO uint8_t IOE3 :1; + __IO uint8_t IOP2 :1; + __IO uint8_t IOP3 :1; +} stc_mft_ocsa32_field_t; + +typedef struct stc_mft_ocsb32_field +{ + __IO uint8_t OTD2 :1; + __IO uint8_t OTD3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocsb32_field_t; + +typedef struct stc_mft_ocsd32_field +{ + union { + struct { + __IO uint16_t OCCP2BUFE :2; + __IO uint16_t OCCP3BUFE :2; + __IO uint16_t OCSE2BUFE :2; + __IO uint16_t OCSE3BUFE :2; + __IO uint16_t OPBM2 :1; + __IO uint16_t OPBM3 :1; + __IO uint16_t OEBM2 :1; + __IO uint16_t OEBM3 :1; + __IO uint16_t OFEX2 :1; + __IO uint16_t OFEX3 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP2BUFE0 :1; + __IO uint16_t OCCP2BUFE1 :1; + __IO uint16_t OCCP3BUFE0 :1; + __IO uint16_t OCCP3BUFE1 :1; + __IO uint16_t OCSE2BUFE0 :1; + __IO uint16_t OCSE2BUFE1 :1; + __IO uint16_t OCSE3BUFE0 :1; + __IO uint16_t OCSE3BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocsd32_field_t; + +typedef struct stc_mft_ocsa54_field +{ + __IO uint8_t CST4 :1; + __IO uint8_t CST5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE4 :1; + __IO uint8_t IOE5 :1; + __IO uint8_t IOP4 :1; + __IO uint8_t IOP5 :1; +} stc_mft_ocsa54_field_t; + +typedef struct stc_mft_ocsb54_field +{ + __IO uint8_t OTD4 :1; + __IO uint8_t OTD5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocsb54_field_t; + +typedef struct stc_mft_ocsd54_field +{ + union { + struct { + __IO uint16_t OCCP4BUFE :2; + __IO uint16_t OCCP5BUFE :2; + __IO uint16_t OCSE4BUFE :2; + __IO uint16_t OCSE5BUFE :2; + __IO uint16_t OPBM4 :1; + __IO uint16_t OPBM5 :1; + __IO uint16_t OEBM4 :1; + __IO uint16_t OEBM5 :1; + __IO uint16_t OFEX4 :1; + __IO uint16_t OFEX5 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP4BUFE0 :1; + __IO uint16_t OCCP4BUFE1 :1; + __IO uint16_t OCCP5BUFE0 :1; + __IO uint16_t OCCP5BUFE1 :1; + __IO uint16_t OCSE4BUFE0 :1; + __IO uint16_t OCSE4BUFE1 :1; + __IO uint16_t OCSE5BUFE0 :1; + __IO uint16_t OCSE5BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocsd54_field_t; + +typedef struct stc_mft_ocsc_field +{ + __IO uint8_t MOD0 :1; + __IO uint8_t MOD1 :1; + __IO uint8_t MOD2 :1; + __IO uint8_t MOD3 :1; + __IO uint8_t MOD4 :1; + __IO uint8_t MOD5 :1; + __IO uint8_t RESERVED0 :2; +} stc_mft_ocsc_field_t; + +typedef struct stc_mft_ocse0_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocse0_field_t; + +typedef struct stc_mft_ocse1_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocse1_field_t; + +typedef struct stc_mft_ocse2_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocse2_field_t; + +typedef struct stc_mft_ocse3_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocse3_field_t; + +typedef struct stc_mft_ocse4_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocse4_field_t; + +typedef struct stc_mft_ocse5_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocse5_field_t; + +typedef struct stc_mft_tccp0_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_tccp0_field_t; + +typedef struct stc_mft_tcsa0_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_tcsa0_field_t; + +typedef struct stc_mft_tcsc0_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_tcsc0_field_t; + +typedef struct stc_mft_tccp1_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_tccp1_field_t; + +typedef struct stc_mft_tcsa1_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_tcsa1_field_t; + +typedef struct stc_mft_tcsc1_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_tcsc1_field_t; + +typedef struct stc_mft_tccp2_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_tccp2_field_t; + +typedef struct stc_mft_tcsa2_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_tcsa2_field_t; + +typedef struct stc_mft_tcsc2_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_tcsc2_field_t; + +typedef struct stc_mft_tcal_field +{ + __IO uint32_t STOP00 :1; + __IO uint32_t STOP01 :1; + __IO uint32_t STOP02 :1; + __IO uint32_t STOP10 :1; + __IO uint32_t STOP11 :1; + __IO uint32_t STOP12 :1; + __IO uint32_t STOP20 :1; + __IO uint32_t STOP21 :1; + __IO uint32_t STOP22 :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t SCLR00 :1; + __IO uint32_t SCLR01 :1; + __IO uint32_t SCLR02 :1; + __IO uint32_t SCLR10 :1; + __IO uint32_t SCLR11 :1; + __IO uint32_t SCLR12 :1; + __IO uint32_t SCLR20 :1; + __IO uint32_t SCLR21 :1; + __IO uint32_t SCLR22 :1; + __IO uint32_t RESERVED1 :7; +} stc_mft_tcal_field_t; + +typedef struct stc_mft_ocfs10_field +{ + union { + struct { + __IO uint8_t FSO0 :4; + __IO uint8_t FSO1 :4; + }; + struct { + __IO uint8_t FSO00 :1; + __IO uint8_t FSO01 :1; + __IO uint8_t FSO02 :1; + __IO uint8_t FSO03 :1; + __IO uint8_t FSO10 :1; + __IO uint8_t FSO11 :1; + __IO uint8_t FSO12 :1; + __IO uint8_t FSO13 :1; + }; + }; +} stc_mft_ocfs10_field_t; + +typedef struct stc_mft_ocfs32_field +{ + union { + struct { + __IO uint8_t FSO2 :4; + __IO uint8_t FSO3 :4; + }; + struct { + __IO uint8_t FSO20 :1; + __IO uint8_t FSO21 :1; + __IO uint8_t FSO22 :1; + __IO uint8_t FSO23 :1; + __IO uint8_t FSO30 :1; + __IO uint8_t FSO31 :1; + __IO uint8_t FSO32 :1; + __IO uint8_t FSO33 :1; + }; + }; +} stc_mft_ocfs32_field_t; + +typedef struct stc_mft_ocfs54_field +{ + union { + struct { + __IO uint8_t FSO4 :4; + __IO uint8_t FSO5 :4; + }; + struct { + __IO uint8_t FSO40 :1; + __IO uint8_t FSO41 :1; + __IO uint8_t FSO42 :1; + __IO uint8_t FSO43 :1; + __IO uint8_t FSO50 :1; + __IO uint8_t FSO51 :1; + __IO uint8_t FSO52 :1; + __IO uint8_t FSO53 :1; + }; + }; +} stc_mft_ocfs54_field_t; + +typedef struct stc_mft_icfs10_field +{ + union { + struct { + __IO uint8_t FSI0 :4; + __IO uint8_t FSI1 :4; + }; + struct { + __IO uint8_t FSI00 :1; + __IO uint8_t FSI01 :1; + __IO uint8_t FSI02 :1; + __IO uint8_t FSI03 :1; + __IO uint8_t FSI10 :1; + __IO uint8_t FSI11 :1; + __IO uint8_t FSI12 :1; + __IO uint8_t FSI13 :1; + }; + }; +} stc_mft_icfs10_field_t; + +typedef struct stc_mft_icfs32_field +{ + union { + struct { + __IO uint8_t FSI2 :4; + __IO uint8_t FSI3 :4; + }; + struct { + __IO uint8_t FSI20 :1; + __IO uint8_t FSI21 :1; + __IO uint8_t FSI22 :1; + __IO uint8_t FSI23 :1; + __IO uint8_t FSI30 :1; + __IO uint8_t FSI31 :1; + __IO uint8_t FSI32 :1; + __IO uint8_t FSI33 :1; + }; + }; +} stc_mft_icfs32_field_t; + +typedef struct stc_mft_acfs10_field +{ + union { + struct { + __IO uint8_t FSA0 :4; + __IO uint8_t FSA1 :4; + }; + struct { + __IO uint8_t FSA00 :1; + __IO uint8_t FSA01 :1; + __IO uint8_t FSA02 :1; + __IO uint8_t FSA03 :1; + __IO uint8_t FSA10 :1; + __IO uint8_t FSA11 :1; + __IO uint8_t FSA12 :1; + __IO uint8_t FSA13 :1; + }; + }; +} stc_mft_acfs10_field_t; + +typedef struct stc_mft_acfs32_field +{ + union { + struct { + __IO uint8_t FSA2 :4; + __IO uint8_t FSA3 :4; + }; + struct { + __IO uint8_t FSA20 :1; + __IO uint8_t FSA21 :1; + __IO uint8_t FSA22 :1; + __IO uint8_t FSA23 :1; + __IO uint8_t FSA30 :1; + __IO uint8_t FSA31 :1; + __IO uint8_t FSA32 :1; + __IO uint8_t FSA33 :1; + }; + }; +} stc_mft_acfs32_field_t; + +typedef struct stc_mft_acfs54_field +{ + union { + struct { + __IO uint8_t FSA4 :4; + __IO uint8_t FSA5 :4; + }; + struct { + __IO uint8_t FSA40 :1; + __IO uint8_t FSA41 :1; + __IO uint8_t FSA42 :1; + __IO uint8_t FSA43 :1; + __IO uint8_t FSA50 :1; + __IO uint8_t FSA51 :1; + __IO uint8_t FSA52 :1; + __IO uint8_t FSA53 :1; + }; + }; +} stc_mft_acfs54_field_t; + +typedef struct stc_mft_icsa10_field +{ + union { + struct { + __IO uint8_t EG0 :2; + __IO uint8_t EG1 :2; + __IO uint8_t ICE0 :1; + __IO uint8_t ICE1 :1; + __IO uint8_t ICP0 :1; + __IO uint8_t ICP1 :1; + }; + struct { + __IO uint8_t EG00 :1; + __IO uint8_t EG01 :1; + __IO uint8_t EG10 :1; + __IO uint8_t EG11 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icsa10_field_t; + +typedef struct stc_mft_icsb10_field +{ + __IO uint8_t IEI0 :1; + __IO uint8_t IEI1 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icsb10_field_t; + +typedef struct stc_mft_icsa32_field +{ + union { + struct { + __IO uint8_t EG2 :2; + __IO uint8_t EG3 :2; + __IO uint8_t ICE2 :1; + __IO uint8_t ICE3 :1; + __IO uint8_t ICP2 :1; + __IO uint8_t ICP3 :1; + }; + struct { + __IO uint8_t EG20 :1; + __IO uint8_t EG21 :1; + __IO uint8_t EG30 :1; + __IO uint8_t EG31 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icsa32_field_t; + +typedef struct stc_mft_icsb32_field +{ + __IO uint8_t IEI2 :1; + __IO uint8_t IEI3 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icsb32_field_t; + +typedef struct stc_mft_wfsa10_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfsa10_field_t; + +typedef struct stc_mft_wfsa32_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfsa32_field_t; + +typedef struct stc_mft_wfsa54_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfsa54_field_t; + +typedef struct stc_mft_wfir_field +{ + __IO uint16_t DTIFA :1; + __IO uint16_t DTICA :1; + __IO uint16_t DTIFB :1; + __IO uint16_t DTICB :1; + __IO uint16_t TMIF10 :1; + __IO uint16_t TMIC10 :1; + __IO uint16_t TMIE10 :1; + __IO uint16_t TMIS10 :1; + __IO uint16_t TMIF32 :1; + __IO uint16_t TMIC32 :1; + __IO uint16_t TMIE32 :1; + __IO uint16_t TMIS32 :1; + __IO uint16_t TMIF54 :1; + __IO uint16_t TMIC54 :1; + __IO uint16_t TMIE54 :1; + __IO uint16_t TMIS54 :1; +} stc_mft_wfir_field_t; + +typedef struct stc_mft_nzcl_field +{ + union { + struct { + __IO uint16_t DTIEA :1; + __IO uint16_t NWS :3; + __IO uint16_t SDTI :1; + __IO uint16_t DTIEB :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t DHOLD :1; + __IO uint16_t DIMA :1; + __IO uint16_t DIMB :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t WIM10 :1; + __IO uint16_t WIM32 :1; + __IO uint16_t WIM54 :1; + __IO uint16_t RESERVED3 :1; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t NWS0 :1; + __IO uint16_t NWS1 :1; + __IO uint16_t NWS2 :1; + __IO uint16_t RESERVED4 :12; + }; + }; +} stc_mft_nzcl_field_t; + +typedef struct stc_mft_acmp0_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp0_field_t; + +typedef struct stc_mft_acmp1_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp1_field_t; + +typedef struct stc_mft_acmp2_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp2_field_t; + +typedef struct stc_mft_acmp3_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp3_field_t; + +typedef struct stc_mft_acmp4_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp4_field_t; + +typedef struct stc_mft_acmp5_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp5_field_t; + +typedef struct stc_mft_acsa_field +{ + union { + struct { + __IO uint16_t CE10 :2; + __IO uint16_t CE32 :2; + __IO uint16_t CE54 :2; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SEL10 :2; + __IO uint16_t SEL32 :2; + __IO uint16_t SEL54 :2; + __IO uint16_t RESERVED2 :2; + }; + struct { + __IO uint16_t CE100 :1; + __IO uint16_t CE101 :1; + __IO uint16_t CE320 :1; + __IO uint16_t CE321 :1; + __IO uint16_t CE540 :1; + __IO uint16_t CE541 :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SEL100 :1; + __IO uint16_t SEL101 :1; + __IO uint16_t SEL320 :1; + __IO uint16_t SEL321 :1; + __IO uint16_t SEL540 :1; + __IO uint16_t SEL541 :1; + __IO uint16_t RESERVED3 :2; + }; + }; +} stc_mft_acsa_field_t; + +typedef struct stc_mft_acsc0_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc0_field_t; + +typedef struct stc_mft_acsd0_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd0_field_t; + +typedef struct stc_mft_acmc0_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc0_field_t; + +typedef struct stc_mft_acsc1_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc1_field_t; + +typedef struct stc_mft_acsd1_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd1_field_t; + +typedef struct stc_mft_acmc1_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc1_field_t; + +typedef struct stc_mft_acsc2_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc2_field_t; + +typedef struct stc_mft_acsd2_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd2_field_t; + +typedef struct stc_mft_acmc2_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc2_field_t; + +typedef struct stc_mft_acsc3_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc3_field_t; + +typedef struct stc_mft_acsd3_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd3_field_t; + +typedef struct stc_mft_acmc3_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc3_field_t; + +typedef struct stc_mft_acsc4_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc4_field_t; + +typedef struct stc_mft_acsd4_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd4_field_t; + +typedef struct stc_mft_acmc4_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc4_field_t; + +typedef struct stc_mft_acsc5_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc5_field_t; + +typedef struct stc_mft_acsd5_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd5_field_t; + +typedef struct stc_mft_acmc5_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc5_field_t; + +typedef struct stc_mft_tcsd_field +{ + __IO uint8_t OFMD1 :1; + __IO uint8_t OFMD2 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_tcsd_field_t; + +typedef struct stc_mft_ocu_ocsa10_field +{ + __IO uint8_t CST0 :1; + __IO uint8_t CST1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE0 :1; + __IO uint8_t IOE1 :1; + __IO uint8_t IOP0 :1; + __IO uint8_t IOP1 :1; +} stc_mft_ocu_ocsa10_field_t; + +typedef struct stc_mft_ocu_ocsb10_field +{ + __IO uint8_t OTD0 :1; + __IO uint8_t OTD1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocu_ocsb10_field_t; + +typedef struct stc_mft_ocu_ocsd10_field +{ + union { + struct { + __IO uint16_t OCCP0BUFE :2; + __IO uint16_t OCCP1BUFE :2; + __IO uint16_t OCSE0BUFE :2; + __IO uint16_t OCSE1BUFE :2; + __IO uint16_t OPBM0 :1; + __IO uint16_t OPBM1 :1; + __IO uint16_t OEBM0 :1; + __IO uint16_t OEBM1 :1; + __IO uint16_t OFEX0 :1; + __IO uint16_t OFEX1 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP0BUFE0 :1; + __IO uint16_t OCCP0BUFE1 :1; + __IO uint16_t OCCP1BUFE0 :1; + __IO uint16_t OCCP1BUFE1 :1; + __IO uint16_t OCSE0BUFE0 :1; + __IO uint16_t OCSE0BUFE1 :1; + __IO uint16_t OCSE1BUFE0 :1; + __IO uint16_t OCSE1BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocu_ocsd10_field_t; + +typedef struct stc_mft_ocu_ocsa32_field +{ + __IO uint8_t CST2 :1; + __IO uint8_t CST3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE2 :1; + __IO uint8_t IOE3 :1; + __IO uint8_t IOP2 :1; + __IO uint8_t IOP3 :1; +} stc_mft_ocu_ocsa32_field_t; + +typedef struct stc_mft_ocu_ocsb32_field +{ + __IO uint8_t OTD2 :1; + __IO uint8_t OTD3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocu_ocsb32_field_t; + +typedef struct stc_mft_ocu_ocsd32_field +{ + union { + struct { + __IO uint16_t OCCP2BUFE :2; + __IO uint16_t OCCP3BUFE :2; + __IO uint16_t OCSE2BUFE :2; + __IO uint16_t OCSE3BUFE :2; + __IO uint16_t OPBM2 :1; + __IO uint16_t OPBM3 :1; + __IO uint16_t OEBM2 :1; + __IO uint16_t OEBM3 :1; + __IO uint16_t OFEX2 :1; + __IO uint16_t OFEX3 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP2BUFE0 :1; + __IO uint16_t OCCP2BUFE1 :1; + __IO uint16_t OCCP3BUFE0 :1; + __IO uint16_t OCCP3BUFE1 :1; + __IO uint16_t OCSE2BUFE0 :1; + __IO uint16_t OCSE2BUFE1 :1; + __IO uint16_t OCSE3BUFE0 :1; + __IO uint16_t OCSE3BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocu_ocsd32_field_t; + +typedef struct stc_mft_ocu_ocsa54_field +{ + __IO uint8_t CST4 :1; + __IO uint8_t CST5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE4 :1; + __IO uint8_t IOE5 :1; + __IO uint8_t IOP4 :1; + __IO uint8_t IOP5 :1; +} stc_mft_ocu_ocsa54_field_t; + +typedef struct stc_mft_ocu_ocsb54_field +{ + __IO uint8_t OTD4 :1; + __IO uint8_t OTD5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocu_ocsb54_field_t; + +typedef struct stc_mft_ocu_ocsd54_field +{ + union { + struct { + __IO uint16_t OCCP4BUFE :2; + __IO uint16_t OCCP5BUFE :2; + __IO uint16_t OCSE4BUFE :2; + __IO uint16_t OCSE5BUFE :2; + __IO uint16_t OPBM4 :1; + __IO uint16_t OPBM5 :1; + __IO uint16_t OEBM4 :1; + __IO uint16_t OEBM5 :1; + __IO uint16_t OFEX4 :1; + __IO uint16_t OFEX5 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP4BUFE0 :1; + __IO uint16_t OCCP4BUFE1 :1; + __IO uint16_t OCCP5BUFE0 :1; + __IO uint16_t OCCP5BUFE1 :1; + __IO uint16_t OCSE4BUFE0 :1; + __IO uint16_t OCSE4BUFE1 :1; + __IO uint16_t OCSE5BUFE0 :1; + __IO uint16_t OCSE5BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocu_ocsd54_field_t; + +typedef struct stc_mft_ocu_ocsc_field +{ + __IO uint8_t MOD0 :1; + __IO uint8_t MOD1 :1; + __IO uint8_t MOD2 :1; + __IO uint8_t MOD3 :1; + __IO uint8_t MOD4 :1; + __IO uint8_t MOD5 :1; + __IO uint8_t RESERVED0 :2; +} stc_mft_ocu_ocsc_field_t; + +typedef struct stc_mft_ocu_ocse0_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocu_ocse0_field_t; + +typedef struct stc_mft_ocu_ocse1_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocu_ocse1_field_t; + +typedef struct stc_mft_ocu_ocse2_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocu_ocse2_field_t; + +typedef struct stc_mft_ocu_ocse3_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocu_ocse3_field_t; + +typedef struct stc_mft_ocu_ocse4_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocu_ocse4_field_t; + +typedef struct stc_mft_ocu_ocse5_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocu_ocse5_field_t; + +typedef struct stc_mft_frt_tccp0_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_frt_tccp0_field_t; + +typedef struct stc_mft_frt_tcsa0_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_frt_tcsa0_field_t; + +typedef struct stc_mft_frt_tcsc0_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_frt_tcsc0_field_t; + +typedef struct stc_mft_frt_tccp1_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_frt_tccp1_field_t; + +typedef struct stc_mft_frt_tcsa1_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_frt_tcsa1_field_t; + +typedef struct stc_mft_frt_tcsc1_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_frt_tcsc1_field_t; + +typedef struct stc_mft_frt_tccp2_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_frt_tccp2_field_t; + +typedef struct stc_mft_frt_tcsa2_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_frt_tcsa2_field_t; + +typedef struct stc_mft_frt_tcsc2_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_frt_tcsc2_field_t; + +typedef struct stc_mft_frt_tcal_field +{ + __IO uint32_t STOP00 :1; + __IO uint32_t STOP01 :1; + __IO uint32_t STOP02 :1; + __IO uint32_t STOP10 :1; + __IO uint32_t STOP11 :1; + __IO uint32_t STOP12 :1; + __IO uint32_t STOP20 :1; + __IO uint32_t STOP21 :1; + __IO uint32_t STOP22 :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t SCLR00 :1; + __IO uint32_t SCLR01 :1; + __IO uint32_t SCLR02 :1; + __IO uint32_t SCLR10 :1; + __IO uint32_t SCLR11 :1; + __IO uint32_t SCLR12 :1; + __IO uint32_t SCLR20 :1; + __IO uint32_t SCLR21 :1; + __IO uint32_t SCLR22 :1; + __IO uint32_t RESERVED1 :7; +} stc_mft_frt_tcal_field_t; + +typedef struct stc_mft_ocu_ocfs10_field +{ + union { + struct { + __IO uint8_t FSO0 :4; + __IO uint8_t FSO1 :4; + }; + struct { + __IO uint8_t FSO00 :1; + __IO uint8_t FSO01 :1; + __IO uint8_t FSO02 :1; + __IO uint8_t FSO03 :1; + __IO uint8_t FSO10 :1; + __IO uint8_t FSO11 :1; + __IO uint8_t FSO12 :1; + __IO uint8_t FSO13 :1; + }; + }; +} stc_mft_ocu_ocfs10_field_t; + +typedef struct stc_mft_ocu_ocfs32_field +{ + union { + struct { + __IO uint8_t FSO2 :4; + __IO uint8_t FSO3 :4; + }; + struct { + __IO uint8_t FSO20 :1; + __IO uint8_t FSO21 :1; + __IO uint8_t FSO22 :1; + __IO uint8_t FSO23 :1; + __IO uint8_t FSO30 :1; + __IO uint8_t FSO31 :1; + __IO uint8_t FSO32 :1; + __IO uint8_t FSO33 :1; + }; + }; +} stc_mft_ocu_ocfs32_field_t; + +typedef struct stc_mft_ocu_ocfs54_field +{ + union { + struct { + __IO uint8_t FSO4 :4; + __IO uint8_t FSO5 :4; + }; + struct { + __IO uint8_t FSO40 :1; + __IO uint8_t FSO41 :1; + __IO uint8_t FSO42 :1; + __IO uint8_t FSO43 :1; + __IO uint8_t FSO50 :1; + __IO uint8_t FSO51 :1; + __IO uint8_t FSO52 :1; + __IO uint8_t FSO53 :1; + }; + }; +} stc_mft_ocu_ocfs54_field_t; + +typedef struct stc_mft_icu_icfs10_field +{ + union { + struct { + __IO uint8_t FSI0 :4; + __IO uint8_t FSI1 :4; + }; + struct { + __IO uint8_t FSI00 :1; + __IO uint8_t FSI01 :1; + __IO uint8_t FSI02 :1; + __IO uint8_t FSI03 :1; + __IO uint8_t FSI10 :1; + __IO uint8_t FSI11 :1; + __IO uint8_t FSI12 :1; + __IO uint8_t FSI13 :1; + }; + }; +} stc_mft_icu_icfs10_field_t; + +typedef struct stc_mft_icu_icfs32_field +{ + union { + struct { + __IO uint8_t FSI2 :4; + __IO uint8_t FSI3 :4; + }; + struct { + __IO uint8_t FSI20 :1; + __IO uint8_t FSI21 :1; + __IO uint8_t FSI22 :1; + __IO uint8_t FSI23 :1; + __IO uint8_t FSI30 :1; + __IO uint8_t FSI31 :1; + __IO uint8_t FSI32 :1; + __IO uint8_t FSI33 :1; + }; + }; +} stc_mft_icu_icfs32_field_t; + +typedef struct stc_mft_adcmp_acfs10_field +{ + union { + struct { + __IO uint8_t FSA0 :4; + __IO uint8_t FSA1 :4; + }; + struct { + __IO uint8_t FSA00 :1; + __IO uint8_t FSA01 :1; + __IO uint8_t FSA02 :1; + __IO uint8_t FSA03 :1; + __IO uint8_t FSA10 :1; + __IO uint8_t FSA11 :1; + __IO uint8_t FSA12 :1; + __IO uint8_t FSA13 :1; + }; + }; +} stc_mft_adcmp_acfs10_field_t; + +typedef struct stc_mft_adcmp_acfs32_field +{ + union { + struct { + __IO uint8_t FSA2 :4; + __IO uint8_t FSA3 :4; + }; + struct { + __IO uint8_t FSA20 :1; + __IO uint8_t FSA21 :1; + __IO uint8_t FSA22 :1; + __IO uint8_t FSA23 :1; + __IO uint8_t FSA30 :1; + __IO uint8_t FSA31 :1; + __IO uint8_t FSA32 :1; + __IO uint8_t FSA33 :1; + }; + }; +} stc_mft_adcmp_acfs32_field_t; + +typedef struct stc_mft_adcmp_acfs54_field +{ + union { + struct { + __IO uint8_t FSA4 :4; + __IO uint8_t FSA5 :4; + }; + struct { + __IO uint8_t FSA40 :1; + __IO uint8_t FSA41 :1; + __IO uint8_t FSA42 :1; + __IO uint8_t FSA43 :1; + __IO uint8_t FSA50 :1; + __IO uint8_t FSA51 :1; + __IO uint8_t FSA52 :1; + __IO uint8_t FSA53 :1; + }; + }; +} stc_mft_adcmp_acfs54_field_t; + +typedef struct stc_mft_icu_icsa10_field +{ + union { + struct { + __IO uint8_t EG0 :2; + __IO uint8_t EG1 :2; + __IO uint8_t ICE0 :1; + __IO uint8_t ICE1 :1; + __IO uint8_t ICP0 :1; + __IO uint8_t ICP1 :1; + }; + struct { + __IO uint8_t EG00 :1; + __IO uint8_t EG01 :1; + __IO uint8_t EG10 :1; + __IO uint8_t EG11 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icu_icsa10_field_t; + +typedef struct stc_mft_icu_icsb10_field +{ + __IO uint8_t IEI0 :1; + __IO uint8_t IEI1 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icu_icsb10_field_t; + +typedef struct stc_mft_icu_icsa32_field +{ + union { + struct { + __IO uint8_t EG2 :2; + __IO uint8_t EG3 :2; + __IO uint8_t ICE2 :1; + __IO uint8_t ICE3 :1; + __IO uint8_t ICP2 :1; + __IO uint8_t ICP3 :1; + }; + struct { + __IO uint8_t EG20 :1; + __IO uint8_t EG21 :1; + __IO uint8_t EG30 :1; + __IO uint8_t EG31 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icu_icsa32_field_t; + +typedef struct stc_mft_icu_icsb32_field +{ + __IO uint8_t IEI2 :1; + __IO uint8_t IEI3 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icu_icsb32_field_t; + +typedef struct stc_mft_wfg_wfsa10_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfg_wfsa10_field_t; + +typedef struct stc_mft_wfg_wfsa32_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfg_wfsa32_field_t; + +typedef struct stc_mft_wfg_wfsa54_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfg_wfsa54_field_t; + +typedef struct stc_mft_wfg_wfir_field +{ + __IO uint16_t DTIFA :1; + __IO uint16_t DTICA :1; + __IO uint16_t DTIFB :1; + __IO uint16_t DTICB :1; + __IO uint16_t TMIF10 :1; + __IO uint16_t TMIC10 :1; + __IO uint16_t TMIE10 :1; + __IO uint16_t TMIS10 :1; + __IO uint16_t TMIF32 :1; + __IO uint16_t TMIC32 :1; + __IO uint16_t TMIE32 :1; + __IO uint16_t TMIS32 :1; + __IO uint16_t TMIF54 :1; + __IO uint16_t TMIC54 :1; + __IO uint16_t TMIE54 :1; + __IO uint16_t TMIS54 :1; +} stc_mft_wfg_wfir_field_t; + +typedef struct stc_mft_wfg_nzcl_field +{ + union { + struct { + __IO uint16_t DTIEA :1; + __IO uint16_t NWS :3; + __IO uint16_t SDTI :1; + __IO uint16_t DTIEB :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t DHOLD :1; + __IO uint16_t DIMA :1; + __IO uint16_t DIMB :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t WIM10 :1; + __IO uint16_t WIM32 :1; + __IO uint16_t WIM54 :1; + __IO uint16_t RESERVED3 :1; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t NWS0 :1; + __IO uint16_t NWS1 :1; + __IO uint16_t NWS2 :1; + __IO uint16_t RESERVED4 :12; + }; + }; +} stc_mft_wfg_nzcl_field_t; + +typedef struct stc_mft_adcmp_acmp0_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp0_field_t; + +typedef struct stc_mft_adcmp_acmp1_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp1_field_t; + +typedef struct stc_mft_adcmp_acmp2_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp2_field_t; + +typedef struct stc_mft_adcmp_acmp3_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp3_field_t; + +typedef struct stc_mft_adcmp_acmp4_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp4_field_t; + +typedef struct stc_mft_adcmp_acmp5_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp5_field_t; + +typedef struct stc_mft_adcmp_acsa_field +{ + union { + struct { + __IO uint16_t CE10 :2; + __IO uint16_t CE32 :2; + __IO uint16_t CE54 :2; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SEL10 :2; + __IO uint16_t SEL32 :2; + __IO uint16_t SEL54 :2; + __IO uint16_t RESERVED2 :2; + }; + struct { + __IO uint16_t CE100 :1; + __IO uint16_t CE101 :1; + __IO uint16_t CE320 :1; + __IO uint16_t CE321 :1; + __IO uint16_t CE540 :1; + __IO uint16_t CE541 :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SEL100 :1; + __IO uint16_t SEL101 :1; + __IO uint16_t SEL320 :1; + __IO uint16_t SEL321 :1; + __IO uint16_t SEL540 :1; + __IO uint16_t SEL541 :1; + __IO uint16_t RESERVED3 :2; + }; + }; +} stc_mft_adcmp_acsa_field_t; + +typedef struct stc_mft_adcmp_acsc0_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc0_field_t; + +typedef struct stc_mft_adcmp_acsd0_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd0_field_t; + +typedef struct stc_mft_adcmp_acmc0_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc0_field_t; + +typedef struct stc_mft_adcmp_acsc1_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc1_field_t; + +typedef struct stc_mft_adcmp_acsd1_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd1_field_t; + +typedef struct stc_mft_adcmp_acmc1_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc1_field_t; + +typedef struct stc_mft_adcmp_acsc2_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc2_field_t; + +typedef struct stc_mft_adcmp_acsd2_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd2_field_t; + +typedef struct stc_mft_adcmp_acmc2_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc2_field_t; + +typedef struct stc_mft_adcmp_acsc3_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc3_field_t; + +typedef struct stc_mft_adcmp_acsd3_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd3_field_t; + +typedef struct stc_mft_adcmp_acmc3_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc3_field_t; + +typedef struct stc_mft_adcmp_acsc4_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc4_field_t; + +typedef struct stc_mft_adcmp_acsd4_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd4_field_t; + +typedef struct stc_mft_adcmp_acmc4_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc4_field_t; + +typedef struct stc_mft_adcmp_acsc5_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc5_field_t; + +typedef struct stc_mft_adcmp_acsd5_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd5_field_t; + +typedef struct stc_mft_adcmp_acmc5_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc5_field_t; + +typedef struct stc_mft_frt_tcsd_field +{ + __IO uint8_t OFMD1 :1; + __IO uint8_t OFMD2 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_frt_tcsd_field_t; + +/******************************************************************************* +* MFT_PPG_MODULE +*******************************************************************************/ +typedef struct stc_mft_ppg_ttcr0_field +{ + union { + struct { + __IO uint8_t STR0 :1; + __IO uint8_t MONI0 :1; + __IO uint8_t CS0 :2; + __IO uint8_t TRG0O :1; + __IO uint8_t TRG2O :1; + __IO uint8_t TRG4O :1; + __IO uint8_t TRG6O :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS00 :1; + __IO uint8_t CS01 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_ppg_ttcr0_field_t; + +typedef struct stc_mft_ppg_ttcr1_field +{ + union { + struct { + __IO uint8_t STR1 :1; + __IO uint8_t MONI1 :1; + __IO uint8_t CS1 :2; + __IO uint8_t TRG1O :1; + __IO uint8_t TRG3O :1; + __IO uint8_t TRG5O :1; + __IO uint8_t TRG7O :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS10 :1; + __IO uint8_t CS11 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_ppg_ttcr1_field_t; + +typedef struct stc_mft_ppg_ttcr2_field +{ + union { + struct { + __IO uint8_t STR2 :1; + __IO uint8_t MONI2 :1; + __IO uint8_t CS2 :2; + __IO uint8_t TRG16O :1; + __IO uint8_t TRG18O :1; + __IO uint8_t TRG20O :1; + __IO uint8_t TRG22O :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS20 :1; + __IO uint8_t CS21 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_ppg_ttcr2_field_t; + +typedef struct stc_mft_ppg_trg0_field +{ + __IO uint16_t PEN00 :1; + __IO uint16_t PEN01 :1; + __IO uint16_t PEN02 :1; + __IO uint16_t PEN03 :1; + __IO uint16_t PEN04 :1; + __IO uint16_t PEN05 :1; + __IO uint16_t PEN06 :1; + __IO uint16_t PEN07 :1; + __IO uint16_t PEN08 :1; + __IO uint16_t PEN09 :1; + __IO uint16_t PEN10 :1; + __IO uint16_t PEN11 :1; + __IO uint16_t PEN12 :1; + __IO uint16_t PEN13 :1; + __IO uint16_t PEN14 :1; + __IO uint16_t PEN15 :1; +} stc_mft_ppg_trg0_field_t; + +typedef struct stc_mft_ppg_revc0_field +{ + __IO uint16_t REV00 :1; + __IO uint16_t REV01 :1; + __IO uint16_t REV02 :1; + __IO uint16_t REV03 :1; + __IO uint16_t REV04 :1; + __IO uint16_t REV05 :1; + __IO uint16_t REV06 :1; + __IO uint16_t REV07 :1; + __IO uint16_t REV08 :1; + __IO uint16_t REV09 :1; + __IO uint16_t REV10 :1; + __IO uint16_t REV11 :1; + __IO uint16_t REV12 :1; + __IO uint16_t REV13 :1; + __IO uint16_t REV14 :1; + __IO uint16_t REV15 :1; +} stc_mft_ppg_revc0_field_t; + +typedef struct stc_mft_ppg_trg1_field +{ + __IO uint16_t PEN16 :1; + __IO uint16_t PEN17 :1; + __IO uint16_t PEN18 :1; + __IO uint16_t PEN19 :1; + __IO uint16_t PEN20 :1; + __IO uint16_t PEN21 :1; + __IO uint16_t PEN22 :1; + __IO uint16_t PEN23 :1; + __IO uint16_t RESERVED0 :8; +} stc_mft_ppg_trg1_field_t; + +typedef struct stc_mft_ppg_revc1_field +{ + __IO uint16_t REV16 :1; + __IO uint16_t REV17 :1; + __IO uint16_t REV18 :1; + __IO uint16_t REV19 :1; + __IO uint16_t REV20 :1; + __IO uint16_t REV21 :1; + __IO uint16_t REV22 :1; + __IO uint16_t REV23 :1; + __IO uint16_t RESERVED0 :8; +} stc_mft_ppg_revc1_field_t; + +typedef struct stc_mft_ppg_ppgc1_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc1_field_t; + +typedef struct stc_mft_ppg_ppgc0_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc0_field_t; + +typedef struct stc_mft_ppg_ppgc3_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc3_field_t; + +typedef struct stc_mft_ppg_ppgc2_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc2_field_t; + +typedef struct stc_mft_ppg_prll0_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll0_field_t; + +typedef struct stc_mft_ppg_prlh0_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh0_field_t; + +typedef struct stc_mft_ppg_prll1_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll1_field_t; + +typedef struct stc_mft_ppg_prlh1_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh1_field_t; + +typedef struct stc_mft_ppg_prll2_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll2_field_t; + +typedef struct stc_mft_ppg_prlh2_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh2_field_t; + +typedef struct stc_mft_ppg_prll3_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll3_field_t; + +typedef struct stc_mft_ppg_prlh3_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh3_field_t; + +typedef struct stc_mft_ppg_gatec0_field +{ + __IO uint8_t EDGE0 :1; + __IO uint8_t STRG0 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE2 :1; + __IO uint8_t STRG2 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec0_field_t; + +typedef struct stc_mft_ppg_ppgc5_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc5_field_t; + +typedef struct stc_mft_ppg_ppgc4_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc4_field_t; + +typedef struct stc_mft_ppg_ppgc7_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc7_field_t; + +typedef struct stc_mft_ppg_ppgc6_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc6_field_t; + +typedef struct stc_mft_ppg_prll4_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll4_field_t; + +typedef struct stc_mft_ppg_prlh4_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh4_field_t; + +typedef struct stc_mft_ppg_prll5_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll5_field_t; + +typedef struct stc_mft_ppg_prlh5_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh5_field_t; + +typedef struct stc_mft_ppg_prll6_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll6_field_t; + +typedef struct stc_mft_ppg_prlh6_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh6_field_t; + +typedef struct stc_mft_ppg_prll7_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll7_field_t; + +typedef struct stc_mft_ppg_prlh7_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh7_field_t; + +typedef struct stc_mft_ppg_gatec4_field +{ + __IO uint8_t EDGE4 :1; + __IO uint8_t STRG4 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE6 :1; + __IO uint8_t STRG6 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec4_field_t; + +typedef struct stc_mft_ppg_ppgc9_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc9_field_t; + +typedef struct stc_mft_ppg_ppgc8_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc8_field_t; + +typedef struct stc_mft_ppg_ppgc11_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc11_field_t; + +typedef struct stc_mft_ppg_ppgc10_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc10_field_t; + +typedef struct stc_mft_ppg_prll8_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll8_field_t; + +typedef struct stc_mft_ppg_prlh8_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh8_field_t; + +typedef struct stc_mft_ppg_prll9_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll9_field_t; + +typedef struct stc_mft_ppg_prlh9_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh9_field_t; + +typedef struct stc_mft_ppg_prll10_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll10_field_t; + +typedef struct stc_mft_ppg_prlh10_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh10_field_t; + +typedef struct stc_mft_ppg_prll11_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll11_field_t; + +typedef struct stc_mft_ppg_prlh11_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh11_field_t; + +typedef struct stc_mft_ppg_gatec8_field +{ + __IO uint8_t EDGE8 :1; + __IO uint8_t STRG8 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE10 :1; + __IO uint8_t STRG10 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec8_field_t; + +typedef struct stc_mft_ppg_ppgc13_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc13_field_t; + +typedef struct stc_mft_ppg_ppgc12_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc12_field_t; + +typedef struct stc_mft_ppg_ppgc15_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc15_field_t; + +typedef struct stc_mft_ppg_ppgc14_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc14_field_t; + +typedef struct stc_mft_ppg_prll12_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll12_field_t; + +typedef struct stc_mft_ppg_prlh12_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh12_field_t; + +typedef struct stc_mft_ppg_prll13_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll13_field_t; + +typedef struct stc_mft_ppg_prlh13_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh13_field_t; + +typedef struct stc_mft_ppg_prll14_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll14_field_t; + +typedef struct stc_mft_ppg_prlh14_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh14_field_t; + +typedef struct stc_mft_ppg_prll15_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll15_field_t; + +typedef struct stc_mft_ppg_prlh15_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh15_field_t; + +typedef struct stc_mft_ppg_gatec12_field +{ + __IO uint8_t EDGE12 :1; + __IO uint8_t STRG12 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE14 :1; + __IO uint8_t STRG14 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec12_field_t; + +typedef struct stc_mft_ppg_ppgc17_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc17_field_t; + +typedef struct stc_mft_ppg_ppgc16_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc16_field_t; + +typedef struct stc_mft_ppg_ppgc19_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc19_field_t; + +typedef struct stc_mft_ppg_ppgc18_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc18_field_t; + +typedef struct stc_mft_ppg_prll16_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll16_field_t; + +typedef struct stc_mft_ppg_prlh16_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh16_field_t; + +typedef struct stc_mft_ppg_prll17_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll17_field_t; + +typedef struct stc_mft_ppg_prlh17_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh17_field_t; + +typedef struct stc_mft_ppg_prll18_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll18_field_t; + +typedef struct stc_mft_ppg_prlh18_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh18_field_t; + +typedef struct stc_mft_ppg_prll19_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll19_field_t; + +typedef struct stc_mft_ppg_prlh19_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh19_field_t; + +typedef struct stc_mft_ppg_gatec16_field +{ + __IO uint8_t EDGE16 :1; + __IO uint8_t STRG16 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE18 :1; + __IO uint8_t STRG18 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec16_field_t; + +typedef struct stc_mft_ppg_ppgc21_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc21_field_t; + +typedef struct stc_mft_ppg_ppgc20_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc20_field_t; + +typedef struct stc_mft_ppg_ppgc23_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc23_field_t; + +typedef struct stc_mft_ppg_ppgc22_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc22_field_t; + +typedef struct stc_mft_ppg_prll20_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll20_field_t; + +typedef struct stc_mft_ppg_prlh20_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh20_field_t; + +typedef struct stc_mft_ppg_prll21_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll21_field_t; + +typedef struct stc_mft_ppg_prlh21_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh21_field_t; + +typedef struct stc_mft_ppg_prll22_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll22_field_t; + +typedef struct stc_mft_ppg_prlh22_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh22_field_t; + +typedef struct stc_mft_ppg_prll23_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll23_field_t; + +typedef struct stc_mft_ppg_prlh23_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh23_field_t; + +typedef struct stc_mft_ppg_gatec20_field +{ + __IO uint8_t EDGE20 :1; + __IO uint8_t STRG20 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE22 :1; + __IO uint8_t STRG22 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec20_field_t; + +/******************************************************************************* +* PCRC_MODULE +*******************************************************************************/ +typedef struct stc_pcrc_pcrc_cfg_field +{ + union { + struct { + __IO uint32_t CIRQCLR :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t FO :2; + __IO uint32_t FI :2; + __IO uint32_t RESERVED2 :4; + __IO uint32_t TEST :6; + __IO uint32_t SZ :2; + __IO uint32_t CIRQ :1; + __IO uint32_t CIEN :1; + __IO uint32_t CDEN :1; + __IO uint32_t RESERVED4 :1; + __IO uint32_t LOCK :1; + __IO uint32_t RESERVED5 :3; + }; + struct { + __IO uint32_t RESERVED1 :8; + __IO uint32_t FO0 :1; + __IO uint32_t FO1 :1; + __IO uint32_t FI0 :1; + __IO uint32_t FI1 :1; + __IO uint32_t RESERVED3 :4; + __IO uint32_t TEST0 :1; + __IO uint32_t TEST1 :1; + __IO uint32_t TEST2 :1; + __IO uint32_t TEST3 :1; + __IO uint32_t TEST4 :1; + __IO uint32_t TEST5 :1; + __IO uint32_t SZ0 :1; + __IO uint32_t SZ1 :1; + __IO uint32_t RESERVED6 :8; + }; + }; +} stc_pcrc_pcrc_cfg_field_t; + +/******************************************************************************* +* QPRC_MODULE +*******************************************************************************/ +typedef struct stc_qprc_qicrl_field +{ + __IO uint8_t QPCMIE :1; + __IO uint8_t QPCMF :1; + __IO uint8_t QPRCMIE :1; + __IO uint8_t QPRCMF :1; + __IO uint8_t OUZIE :1; + __IO uint8_t UFDF :1; + __IO uint8_t OFDF :1; + __IO uint8_t ZIIF :1; +} stc_qprc_qicrl_field_t; + +typedef struct stc_qprc_qicrh_field +{ + __IO uint8_t CDCIE :1; + __IO uint8_t CDCF :1; + __IO uint8_t DIRPC :1; + __IO uint8_t DIROU :1; + __IO uint8_t QPCNRCMIE :1; + __IO uint8_t QPCNRCMF :1; + __IO uint8_t RESERVED0 :2; +} stc_qprc_qicrh_field_t; + +typedef struct stc_qprc_qcr_field +{ + union { + struct { + __IO uint16_t PCM :2; + __IO uint16_t RCM :2; + __IO uint16_t PSTP :1; + __IO uint16_t CGSC :1; + __IO uint16_t RSEL :1; + __IO uint16_t SWAP :1; + __IO uint16_t PCRM :2; + __IO uint16_t AES :2; + __IO uint16_t BES :2; + __IO uint16_t CGE :2; + }; + struct { + __IO uint16_t PCM0 :1; + __IO uint16_t PCM1 :1; + __IO uint16_t RCM0 :1; + __IO uint16_t RCM1 :1; + __IO uint16_t RESERVED0 :4; + __IO uint16_t PCRM0 :1; + __IO uint16_t PCRM1 :1; + __IO uint16_t AES0 :1; + __IO uint16_t AES1 :1; + __IO uint16_t BES0 :1; + __IO uint16_t BES1 :1; + __IO uint16_t CGE0 :1; + __IO uint16_t CGE1 :1; + }; + }; +} stc_qprc_qcr_field_t; + +typedef struct stc_qprc_qecr_field +{ + __IO uint16_t ORNGMD :1; + __IO uint16_t ORNGF :1; + __IO uint16_t ORNGIE :1; + __IO uint16_t PEC :1; + __IO uint16_t RESERVED0 :12; +} stc_qprc_qecr_field_t; + +typedef struct stc_qprc_qprcrr_field +{ + union { + struct { + __IO uint32_t QPCRR :16; + __IO uint32_t QRCRR :16; + }; + struct { + __IO uint32_t QPCRR0 :1; + __IO uint32_t QPCRR1 :1; + __IO uint32_t QPCRR2 :1; + __IO uint32_t QPCRR3 :1; + __IO uint32_t QPCRR4 :1; + __IO uint32_t QPCRR5 :1; + __IO uint32_t QPCRR6 :1; + __IO uint32_t QPCRR7 :1; + __IO uint32_t QPCRR8 :1; + __IO uint32_t QPCRR9 :1; + __IO uint32_t QPCRR10 :1; + __IO uint32_t QPCRR11 :1; + __IO uint32_t QPCRR12 :1; + __IO uint32_t QPCRR13 :1; + __IO uint32_t QPCRR14 :1; + __IO uint32_t QPCRR15 :1; + __IO uint32_t QRCRR0 :1; + __IO uint32_t QRCRR1 :1; + __IO uint32_t QRCRR2 :1; + __IO uint32_t QRCRR3 :1; + __IO uint32_t QRCRR4 :1; + __IO uint32_t QRCRR5 :1; + __IO uint32_t QRCRR6 :1; + __IO uint32_t QRCRR7 :1; + __IO uint32_t QRCRR8 :1; + __IO uint32_t QRCRR9 :1; + __IO uint32_t QRCRR10 :1; + __IO uint32_t QRCRR11 :1; + __IO uint32_t QRCRR12 :1; + __IO uint32_t QRCRR13 :1; + __IO uint32_t QRCRR14 :1; + __IO uint32_t QRCRR15 :1; + }; + }; +} stc_qprc_qprcrr_field_t; + +/******************************************************************************* +* QPRC_NF_MODULE +*******************************************************************************/ +typedef struct stc_qprc_nf_nfctla_field +{ + union { + struct { + __IO uint8_t AINNWS :3; + __IO uint8_t RESERVED0 :1; + __IO uint8_t AINLV :1; + __IO uint8_t AINMD :1; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t AINNWS0 :1; + __IO uint8_t AINNWS1 :1; + __IO uint8_t AINNWS2 :1; + __IO uint8_t RESERVED2 :5; + }; + }; +} stc_qprc_nf_nfctla_field_t; + +typedef struct stc_qprc_nf_nfctlb_field +{ + union { + struct { + __IO uint8_t BINNWS :3; + __IO uint8_t RESERVED0 :1; + __IO uint8_t BINLV :1; + __IO uint8_t BINMD :1; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t BINNWS0 :1; + __IO uint8_t BINNWS1 :1; + __IO uint8_t BINNWS2 :1; + __IO uint8_t RESERVED2 :5; + }; + }; +} stc_qprc_nf_nfctlb_field_t; + +typedef struct stc_qprc_nf_nfctlz_field +{ + union { + struct { + __IO uint8_t ZINNWS :3; + __IO uint8_t RESERVED0 :1; + __IO uint8_t ZINLV :1; + __IO uint8_t ZINMD :1; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t ZINNWS0 :1; + __IO uint8_t ZINNWS1 :1; + __IO uint8_t ZINNWS2 :1; + __IO uint8_t RESERVED2 :5; + }; + }; +} stc_qprc_nf_nfctlz_field_t; + +/******************************************************************************* +* RTC_MODULE +*******************************************************************************/ +typedef struct stc_rtc_wtcr10_field +{ + __IO uint8_t ST :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t RUN :1; + __IO uint8_t SRST :1; + __IO uint8_t SCST :1; + __IO uint8_t SCRST :1; + __IO uint8_t BUSY :1; + __IO uint8_t TRANS :1; +} stc_rtc_wtcr10_field_t; + +typedef struct stc_rtc_wtcr11_field +{ + __IO uint8_t MIEN :1; + __IO uint8_t HEN :1; + __IO uint8_t DEN :1; + __IO uint8_t MOEN :1; + __IO uint8_t YEN :1; + __IO uint8_t RESERVED0 :3; +} stc_rtc_wtcr11_field_t; + +typedef struct stc_rtc_wtcr12_field +{ + __IO uint8_t INTSSI :1; + __IO uint8_t INTSI :1; + __IO uint8_t INTMI :1; + __IO uint8_t INTHI :1; + __IO uint8_t INTTMI :1; + __IO uint8_t INTALI :1; + __IO uint8_t INTERI :1; + __IO uint8_t INTCRI :1; +} stc_rtc_wtcr12_field_t; + +typedef struct stc_rtc_wtcr13_field +{ + __IO uint8_t INTSSIE :1; + __IO uint8_t INTSIE :1; + __IO uint8_t INTMIE :1; + __IO uint8_t INTHIE :1; + __IO uint8_t INTTMIE :1; + __IO uint8_t INTALIE :1; + __IO uint8_t INTERIE :1; + __IO uint8_t INTCRIE :1; +} stc_rtc_wtcr13_field_t; + +typedef struct stc_rtc_wtcr20_field +{ + __IO uint8_t CREAD :1; + __IO uint8_t CWRITE :1; + __IO uint8_t BREAD :1; + __IO uint8_t BWRITE :1; + __IO uint8_t PREAD :1; + __IO uint8_t PWRITE :1; + __IO uint8_t RESERVED0 :2; +} stc_rtc_wtcr20_field_t; + +typedef struct stc_rtc_wtcr21_field +{ + __IO uint8_t TMST :1; + __IO uint8_t TMEN :1; + __IO uint8_t TMRUN :1; + __IO uint8_t RESERVED0 :5; +} stc_rtc_wtcr21_field_t; + +typedef struct stc_rtc_wtsr_field +{ + union { + struct { + __IO uint8_t S :4; + __IO uint8_t TS :3; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t S0 :1; + __IO uint8_t S1 :1; + __IO uint8_t S2 :1; + __IO uint8_t S3 :1; + __IO uint8_t TS0 :1; + __IO uint8_t TS1 :1; + __IO uint8_t TS2 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_rtc_wtsr_field_t; + +typedef struct stc_rtc_wtmir_field +{ + union { + struct { + __IO uint8_t MI :4; + __IO uint8_t TMI :3; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t MI0 :1; + __IO uint8_t MI1 :1; + __IO uint8_t MI2 :1; + __IO uint8_t MI3 :1; + __IO uint8_t TMI0 :1; + __IO uint8_t TMI1 :1; + __IO uint8_t TMI2 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_rtc_wtmir_field_t; + +typedef struct stc_rtc_wthr_field +{ + union { + struct { + __IO uint8_t H :4; + __IO uint8_t TH :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t H0 :1; + __IO uint8_t H1 :1; + __IO uint8_t H2 :1; + __IO uint8_t H3 :1; + __IO uint8_t TH0 :1; + __IO uint8_t TH1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_wthr_field_t; + +typedef struct stc_rtc_wtdr_field +{ + union { + struct { + __IO uint8_t D :4; + __IO uint8_t TD :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t D0 :1; + __IO uint8_t D1 :1; + __IO uint8_t D2 :1; + __IO uint8_t D3 :1; + __IO uint8_t TD0 :1; + __IO uint8_t TD1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_wtdr_field_t; + +typedef struct stc_rtc_wtdw_field +{ + union { + struct { + __IO uint8_t DW :3; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t DW0 :1; + __IO uint8_t DW1 :1; + __IO uint8_t DW2 :1; + __IO uint8_t RESERVED1 :5; + }; + }; +} stc_rtc_wtdw_field_t; + +typedef struct stc_rtc_wtmor_field +{ + union { + struct { + __IO uint8_t MO :4; + __IO uint8_t TMO :1; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t MO0 :1; + __IO uint8_t MO1 :1; + __IO uint8_t MO2 :1; + __IO uint8_t MO3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_rtc_wtmor_field_t; + +typedef struct stc_rtc_wtyr_field +{ + union { + struct { + __IO uint8_t Y :4; + __IO uint8_t TY :4; + }; + struct { + __IO uint8_t Y0 :1; + __IO uint8_t Y1 :1; + __IO uint8_t Y2 :1; + __IO uint8_t Y3 :1; + __IO uint8_t TY0 :1; + __IO uint8_t TY1 :1; + __IO uint8_t TY2 :1; + __IO uint8_t TY3 :1; + }; + }; +} stc_rtc_wtyr_field_t; + +typedef struct stc_rtc_almir_field +{ + union { + struct { + __IO uint8_t AMI :4; + __IO uint8_t TAMI :3; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t AMI0 :1; + __IO uint8_t AMI1 :1; + __IO uint8_t AMI2 :1; + __IO uint8_t AMI3 :1; + __IO uint8_t TAMI0 :1; + __IO uint8_t TAMI1 :1; + __IO uint8_t TAMI2 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_rtc_almir_field_t; + +typedef struct stc_rtc_alhr_field +{ + union { + struct { + __IO uint8_t AH :4; + __IO uint8_t TAH :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t AH0 :1; + __IO uint8_t AH1 :1; + __IO uint8_t AH2 :1; + __IO uint8_t AH3 :1; + __IO uint8_t TAH0 :1; + __IO uint8_t TAH1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_alhr_field_t; + +typedef struct stc_rtc_aldr_field +{ + union { + struct { + __IO uint8_t AD :4; + __IO uint8_t TAD :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t AD0 :1; + __IO uint8_t AD1 :1; + __IO uint8_t AD2 :1; + __IO uint8_t AD3 :1; + __IO uint8_t TAD0 :1; + __IO uint8_t TAD1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_aldr_field_t; + +typedef struct stc_rtc_almor_field +{ + union { + struct { + __IO uint8_t AMO :4; + __IO uint8_t TAMO :1; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t AMO0 :1; + __IO uint8_t AMO1 :1; + __IO uint8_t AMO2 :1; + __IO uint8_t AMO3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_rtc_almor_field_t; + +typedef struct stc_rtc_alyr_field +{ + union { + struct { + __IO uint8_t AY :4; + __IO uint8_t TAY :4; + }; + struct { + __IO uint8_t AY0 :1; + __IO uint8_t AY1 :1; + __IO uint8_t AY2 :1; + __IO uint8_t AY3 :1; + __IO uint8_t TAY0 :1; + __IO uint8_t TAY1 :1; + __IO uint8_t TAY2 :1; + __IO uint8_t TAY3 :1; + }; + }; +} stc_rtc_alyr_field_t; + +typedef struct stc_rtc_wttr0_field +{ + union { + struct { + __IO uint8_t TM :8; + }; + struct { + __IO uint8_t TM0 :1; + __IO uint8_t TM1 :1; + __IO uint8_t TM2 :1; + __IO uint8_t TM3 :1; + __IO uint8_t TM4 :1; + __IO uint8_t TM5 :1; + __IO uint8_t TM6 :1; + __IO uint8_t TM7 :1; + }; + }; +} stc_rtc_wttr0_field_t; + +typedef struct stc_rtc_wttr1_field +{ + union { + struct { + __IO uint8_t TM :8; + }; + struct { + __IO uint8_t TM0 :1; + __IO uint8_t TM1 :1; + __IO uint8_t TM2 :1; + __IO uint8_t TM3 :1; + __IO uint8_t TM4 :1; + __IO uint8_t TM5 :1; + __IO uint8_t TM6 :1; + __IO uint8_t TM7 :1; + }; + }; +} stc_rtc_wttr1_field_t; + +typedef struct stc_rtc_wttr2_field +{ + union { + struct { + __IO uint8_t TM :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t TM0 :1; + __IO uint8_t TM1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_rtc_wttr2_field_t; + +typedef struct stc_rtc_wtcal0_field +{ + union { + struct { + __IO uint8_t WTCAL0 :8; + }; + struct { + __IO uint8_t WTCAL00 :1; + __IO uint8_t WTCAL01 :1; + __IO uint8_t WTCAL02 :1; + __IO uint8_t WTCAL03 :1; + __IO uint8_t WTCAL04 :1; + __IO uint8_t WTCAL05 :1; + __IO uint8_t WTCAL06 :1; + __IO uint8_t WTCAL07 :1; + }; + }; +} stc_rtc_wtcal0_field_t; + +typedef struct stc_rtc_wtcal1_field +{ + union { + struct { + __IO uint8_t WTCAL1 :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t WTCAL10 :1; + __IO uint8_t WTCAL11 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_rtc_wtcal1_field_t; + +typedef struct stc_rtc_wtcalen_field +{ + __IO uint8_t WTCALEN :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_wtcalen_field_t; + +typedef struct stc_rtc_wtdiv_field +{ + union { + struct { + __IO uint8_t WTDIV :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t WTDIV0 :1; + __IO uint8_t WTDIV1 :1; + __IO uint8_t WTDIV2 :1; + __IO uint8_t WTDIV3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_rtc_wtdiv_field_t; + +typedef struct stc_rtc_wtdiven_field +{ + __IO uint8_t WTDIVEN :1; + __IO uint8_t WTDIVRDY :1; + __IO uint8_t RESERVED0 :6; +} stc_rtc_wtdiven_field_t; + +typedef struct stc_rtc_wtcalprd_field +{ + union { + struct { + __IO uint8_t WTCALPRD :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t WTCALPRD0 :1; + __IO uint8_t WTCALPRD1 :1; + __IO uint8_t WTCALPRD2 :1; + __IO uint8_t WTCALPRD3 :1; + __IO uint8_t WTCALPRD4 :1; + __IO uint8_t WTCALPRD5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_wtcalprd_field_t; + +typedef struct stc_rtc_wtcosel_field +{ + __IO uint8_t WTCOSEL :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_wtcosel_field_t; + +typedef struct stc_rtc_vb_clkdiv_field +{ + union { + struct { + __IO uint8_t DIV :8; + }; + struct { + __IO uint8_t DIV0 :1; + __IO uint8_t DIV1 :1; + __IO uint8_t DIV2 :1; + __IO uint8_t DIV3 :1; + __IO uint8_t DIV4 :1; + __IO uint8_t DIV5 :1; + __IO uint8_t DIV6 :1; + __IO uint8_t DIV7 :1; + }; + }; +} stc_rtc_vb_clkdiv_field_t; + +typedef struct stc_rtc_wtosccnt_field +{ + __IO uint8_t SOSCEX :1; + __IO uint8_t SOSCNTL :1; + __IO uint8_t RESERVED0 :6; +} stc_rtc_wtosccnt_field_t; + +typedef struct stc_rtc_ccs_field +{ + union { + struct { + __IO uint8_t CCS :8; + }; + struct { + __IO uint8_t CCS0 :1; + __IO uint8_t CCS1 :1; + __IO uint8_t CCS2 :1; + __IO uint8_t CCS3 :1; + __IO uint8_t CCS4 :1; + __IO uint8_t CCS5 :1; + __IO uint8_t CCS6 :1; + __IO uint8_t CCS7 :1; + }; + }; +} stc_rtc_ccs_field_t; + +typedef struct stc_rtc_ccb_field +{ + union { + struct { + __IO uint8_t CCB :8; + }; + struct { + __IO uint8_t CCB0 :1; + __IO uint8_t CCB1 :1; + __IO uint8_t CCB2 :1; + __IO uint8_t CCB3 :1; + __IO uint8_t CCB4 :1; + __IO uint8_t CCB5 :1; + __IO uint8_t CCB6 :1; + __IO uint8_t CCB7 :1; + }; + }; +} stc_rtc_ccb_field_t; + +typedef struct stc_rtc_boost_field +{ + union { + struct { + __IO uint8_t BOOST :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t BOOST0 :1; + __IO uint8_t BOOST1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_rtc_boost_field_t; + +typedef struct stc_rtc_ewkup_field +{ + __IO uint8_t WUP0 :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_ewkup_field_t; + +typedef struct stc_rtc_vdet_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t PON :1; +} stc_rtc_vdet_field_t; + +typedef struct stc_rtc_hibrst_field +{ + __IO uint8_t HIBRST :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_hibrst_field_t; + +typedef struct stc_rtc_vbpfr_field +{ + union { + struct { + __IO uint8_t VPFR0 :1; + __IO uint8_t VPFR1 :1; + __IO uint8_t VPFR2 :1; + __IO uint8_t VPFR3 :1; + __IO uint8_t SPSR :2; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t RESERVED0 :4; + __IO uint8_t SPSR0 :1; + __IO uint8_t SPSR1 :1; + __IO uint8_t RESERVED2 :2; + }; + }; +} stc_rtc_vbpfr_field_t; + +typedef struct stc_rtc_vbpcr_field +{ + __IO uint8_t VPCR0 :1; + __IO uint8_t VPCR1 :1; + __IO uint8_t VPCR2 :1; + __IO uint8_t VPCR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbpcr_field_t; + +typedef struct stc_rtc_vbddr_field +{ + __IO uint8_t VDDR0 :1; + __IO uint8_t VDDR1 :1; + __IO uint8_t VDDR2 :1; + __IO uint8_t VDDR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbddr_field_t; + +typedef struct stc_rtc_vbdir_field +{ + __IO uint8_t VDIR0 :1; + __IO uint8_t VDIR1 :1; + __IO uint8_t VDIR2 :1; + __IO uint8_t VDIR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbdir_field_t; + +typedef struct stc_rtc_vbdor_field +{ + __IO uint8_t VDOR0 :1; + __IO uint8_t VDOR1 :1; + __IO uint8_t VDOR2 :1; + __IO uint8_t VDOR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbdor_field_t; + +typedef struct stc_rtc_vbpzr_field +{ + __IO uint8_t VPZR0 :1; + __IO uint8_t VPZR1 :1; + __IO uint8_t RESERVED0 :6; +} stc_rtc_vbpzr_field_t; + +/******************************************************************************* +* SBSSR_MODULE +*******************************************************************************/ +typedef struct stc_sbssr_btsssr_field +{ + __IO uint16_t SSSR0 :1; + __IO uint16_t SSSR1 :1; + __IO uint16_t SSSR2 :1; + __IO uint16_t SSSR3 :1; + __IO uint16_t SSSR4 :1; + __IO uint16_t SSSR5 :1; + __IO uint16_t SSSR6 :1; + __IO uint16_t SSSR7 :1; + __IO uint16_t SSSR8 :1; + __IO uint16_t SSSR9 :1; + __IO uint16_t SSSR10 :1; + __IO uint16_t SSSR11 :1; + __IO uint16_t SSSR12 :1; + __IO uint16_t SSSR13 :1; + __IO uint16_t SSSR14 :1; + __IO uint16_t SSSR15 :1; +} stc_sbssr_btsssr_field_t; + +/******************************************************************************* +* SDIF_MODULE +*******************************************************************************/ +typedef struct stc_sdif_sbsize_field +{ + union { + struct { + __IO uint16_t TRSFBLCKSZ :12; + __IO uint16_t HSDMABUFBD :3; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t TRSFBLCKSZ0 :1; + __IO uint16_t TRSFBLCKSZ1 :1; + __IO uint16_t TRSFBLCKSZ2 :1; + __IO uint16_t TRSFBLCKSZ3 :1; + __IO uint16_t TRSFBLCKSZ4 :1; + __IO uint16_t TRSFBLCKSZ5 :1; + __IO uint16_t TRSFBLCKSZ6 :1; + __IO uint16_t TRSFBLCKSZ7 :1; + __IO uint16_t TRSFBLCKSZ8 :1; + __IO uint16_t TRSFBLCKSZ9 :1; + __IO uint16_t TRSFBLCKSZ10 :1; + __IO uint16_t TRSFBLCKSZ11 :1; + __IO uint16_t HSDMABUFBD0 :1; + __IO uint16_t HSDMABUFBD1 :1; + __IO uint16_t HSDMABUFBD2 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_sdif_sbsize_field_t; + +typedef struct stc_sdif_strsfmd_field +{ + union { + struct { + __IO uint16_t DMAEN :1; + __IO uint16_t BLCKCNTEN :1; + __IO uint16_t AUTOCMDEN :2; + __IO uint16_t DTTRSFDIR :1; + __IO uint16_t BLCKCNTSEL :1; + __IO uint16_t RESERVED1 :10; + }; + struct { + __IO uint16_t RESERVED0 :2; + __IO uint16_t AUTOCMDEN0 :1; + __IO uint16_t AUTOCMDEN1 :1; + __IO uint16_t RESERVED2 :12; + }; + }; +} stc_sdif_strsfmd_field_t; + +typedef struct stc_sdif_scmmd_field +{ + union { + struct { + __IO uint16_t RESPTYPE :2; + __IO uint16_t RESERVED0 :1; + __IO uint16_t CMDCRCCHKE :1; + __IO uint16_t CMDIDXCHKE :1; + __IO uint16_t DATPRESSEL :1; + __IO uint16_t CMDTYPE :2; + __IO uint16_t CMDINDEX :6; + __IO uint16_t RESERVED2 :2; + }; + struct { + __IO uint16_t RESPTYPE0 :1; + __IO uint16_t RESPTYPE1 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t CMDTYPE0 :1; + __IO uint16_t CMDTYPE1 :1; + __IO uint16_t CMDINDEX0 :1; + __IO uint16_t CMDINDEX1 :1; + __IO uint16_t CMDINDEX2 :1; + __IO uint16_t CMDINDEX3 :1; + __IO uint16_t CMDINDEX4 :1; + __IO uint16_t CMDINDEX5 :1; + __IO uint16_t RESERVED3 :2; + }; + }; +} stc_sdif_scmmd_field_t; + +typedef struct stc_sdif_sprstat_field +{ + union { + struct { + __IO uint32_t CMDINH :1; + __IO uint32_t CMDDATINH :1; + __IO uint32_t DATLNACT :1; + __IO uint32_t RETUNEREQ :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t WRTRSFACT :1; + __IO uint32_t RDTRSFACT :1; + __IO uint32_t BUFWREN :1; + __IO uint32_t BUFRDEN :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t CARDINS :1; + __IO uint32_t CARDSTB :1; + __IO uint32_t CARDDET :1; + __IO uint32_t WPPINLVL :1; + __IO uint32_t LNSGNLVL :4; + __IO uint32_t CMDLNSGN :1; + __IO uint32_t RESERVED3 :7; + }; + struct { + __IO uint32_t RESERVED2 :20; + __IO uint32_t LNSGNLVL0 :1; + __IO uint32_t LNSGNLVL1 :1; + __IO uint32_t LNSGNLVL2 :1; + __IO uint32_t LNSGNLVL3 :1; + __IO uint32_t RESERVED4 :8; + }; + }; +} stc_sdif_sprstat_field_t; + +typedef struct stc_sdif_shctl1_field +{ + union { + struct { + __IO uint8_t LEDCTRL :1; + __IO uint8_t DATAWIDTH :1; + __IO uint8_t HIGHSPDEN :1; + __IO uint8_t DMASEL :2; + __IO uint8_t EXTDTWIDTH :1; + __IO uint8_t CDTSTLVL :1; + __IO uint8_t CDSGNSEL :1; + }; + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t DMASEL0 :1; + __IO uint8_t DMASEL1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_sdif_shctl1_field_t; + +typedef struct stc_sdif_spwrctl_field +{ + union { + struct { + __IO uint8_t SDBUSPWR :1; + __IO uint8_t SDBUSVLSEL :3; + __IO uint8_t RESERVED1 :4; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t SDBUSVLSEL0 :1; + __IO uint8_t SDBUSVLSEL1 :1; + __IO uint8_t SDBUSVLSEL2 :1; + __IO uint8_t RESERVED2 :4; + }; + }; +} stc_sdif_spwrctl_field_t; + +typedef struct stc_sdif_sblkgpctl_field +{ + __IO uint8_t BLCKGSTPREQ :1; + __IO uint8_t CONTREQ :1; + __IO uint8_t RDWAITCTL :1; + __IO uint8_t BLCKGAPINT :1; + __IO uint8_t RESERVED0 :4; +} stc_sdif_sblkgpctl_field_t; + +typedef struct stc_sdif_swkupctl_field +{ + __IO uint8_t WKUPEVNTEN0 :1; + __IO uint8_t WKUPEVNTEN1 :1; + __IO uint8_t WKUPEVNTEN2 :1; + __IO uint8_t RESERVED0 :5; +} stc_sdif_swkupctl_field_t; + +typedef struct stc_sdif_sclkctl_field +{ + union { + struct { + __IO uint16_t INTLCLCKEN :1; + __IO uint16_t INTLCLCKST :1; + __IO uint16_t SDCLCKEN :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t CLCKGENSEL :1; + __IO uint16_t UPSDCLKSEL :2; + __IO uint16_t SDCLKSEL :8; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t UPSDCLKSEL0 :1; + __IO uint16_t UPSDCLKSEL1 :1; + __IO uint16_t SDCLKSEL0 :1; + __IO uint16_t SDCLKSEL1 :1; + __IO uint16_t SDCLKSEL2 :1; + __IO uint16_t SDCLKSEL3 :1; + __IO uint16_t SDCLKSEL4 :1; + __IO uint16_t SDCLKSEL5 :1; + __IO uint16_t SDCLKSEL6 :1; + __IO uint16_t SDCLKSEL7 :1; + }; + }; +} stc_sdif_sclkctl_field_t; + +typedef struct stc_sdif_stoctl_field +{ + union { + struct { + __IO uint8_t DTTMOUTVAL :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t DTTMOUTVAL0 :1; + __IO uint8_t DTTMOUTVAL1 :1; + __IO uint8_t DTTMOUTVAL2 :1; + __IO uint8_t DTTMOUTVAL3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_sdif_stoctl_field_t; + +typedef struct stc_sdif_ssrst_field +{ + __IO uint8_t SWRSTALL :1; + __IO uint8_t SWRSTCMDLN :1; + __IO uint8_t SWRSTDATLN :1; + __IO uint8_t RESERVED0 :5; +} stc_sdif_ssrst_field_t; + +typedef struct stc_sdif_snintst_field +{ + __IO uint16_t CMDCMPLT :1; + __IO uint16_t TRSFCMPLT :1; + __IO uint16_t BLCKGEVNT :1; + __IO uint16_t DMAINT :1; + __IO uint16_t BUFWRRDY :1; + __IO uint16_t BUFRDRDY :1; + __IO uint16_t CARDINS :1; + __IO uint16_t CARDRMV :1; + __IO uint16_t CARDINT :1; + __IO uint16_t INT_A :1; + __IO uint16_t INT_B :1; + __IO uint16_t INT_C :1; + __IO uint16_t RETUNEEVT :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t ERRORINT :1; +} stc_sdif_snintst_field_t; + +typedef struct stc_sdif_seintst_field +{ + __IO uint16_t CMDTOERR :1; + __IO uint16_t CMDCRCERR :1; + __IO uint16_t CMDEBERR :1; + __IO uint16_t CMDIDXERR :1; + __IO uint16_t DTTOERR :1; + __IO uint16_t DTCRCERR :1; + __IO uint16_t DTEBERR :1; + __IO uint16_t CRTLMTERR :1; + __IO uint16_t ACMD12ERR :1; + __IO uint16_t ADMAERR :1; + __IO uint16_t TUNINGERR :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t BTACKERR :1; + __IO uint16_t ACMD19ERR :1; + __IO uint16_t AHBMSTERR :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_seintst_field_t; + +typedef struct stc_sdif_snintste_field +{ + __IO uint16_t CMDCMPLTS :1; + __IO uint16_t TRSFCMPLTS :1; + __IO uint16_t BLCKGEVNTS :1; + __IO uint16_t DMAINTS :1; + __IO uint16_t BUFWRRDYS :1; + __IO uint16_t BUFRDRDYS :1; + __IO uint16_t CARDINSS :1; + __IO uint16_t CARDRMVS :1; + __IO uint16_t CARDINTS :1; + __IO uint16_t INT_AS :1; + __IO uint16_t INT_BS :1; + __IO uint16_t INT_CS :1; + __IO uint16_t RETUNEEVTS :1; + __IO uint16_t RESERVED0 :3; +} stc_sdif_snintste_field_t; + +typedef struct stc_sdif_seintste_field +{ + __IO uint16_t CMDTOERRS :1; + __IO uint16_t CMDCRCERRS :1; + __IO uint16_t CMDEBERRS :1; + __IO uint16_t CMDIDXERRS :1; + __IO uint16_t DTTOERRS :1; + __IO uint16_t DTCRCERRS :1; + __IO uint16_t DTEBERRS :1; + __IO uint16_t CRTLMTERRS :1; + __IO uint16_t ACMD12ERRS :1; + __IO uint16_t ADMAERRS :1; + __IO uint16_t TUNINGERRS :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t BTACKERRS :1; + __IO uint16_t ACMD19ERRS :1; + __IO uint16_t AHBMSTERRS :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_seintste_field_t; + +typedef struct stc_sdif_snintsge_field +{ + __IO uint16_t CMDCMPLTG :1; + __IO uint16_t TRSFCMPLTG :1; + __IO uint16_t BLCKGEVNTG :1; + __IO uint16_t DMAINTG :1; + __IO uint16_t BUFWRRDYG :1; + __IO uint16_t BUFRDRDYG :1; + __IO uint16_t CARDINSG :1; + __IO uint16_t CARDRMVG :1; + __IO uint16_t CARDINTG :1; + __IO uint16_t INT_AG :1; + __IO uint16_t INT_BG :1; + __IO uint16_t INT_CG :1; + __IO uint16_t RETUNEEVTG :1; + __IO uint16_t RESERVED0 :3; +} stc_sdif_snintsge_field_t; + +typedef struct stc_sdif_seintsge_field +{ + __IO uint16_t CMDTOERRG :1; + __IO uint16_t CMDCRCERRG :1; + __IO uint16_t CMDEBERRG :1; + __IO uint16_t CMDIDXERRG :1; + __IO uint16_t DTTOERRG :1; + __IO uint16_t DTCRCERRG :1; + __IO uint16_t DTEBERRG :1; + __IO uint16_t CRTLMTERRG :1; + __IO uint16_t ACMD12ERRG :1; + __IO uint16_t ADMAERRG :1; + __IO uint16_t TUNINGERRG :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t BTACKERRG :1; + __IO uint16_t ACMD19ERRG :1; + __IO uint16_t AHBMSTERRG :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_seintsge_field_t; + +typedef struct stc_sdif_sacmdest_field +{ + __IO uint16_t ACMD12NOEX :1; + __IO uint16_t ACMDTOERR :1; + __IO uint16_t ACMDCRCERR :1; + __IO uint16_t ACMDEBERR :1; + __IO uint16_t ACMDIDXERR :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t CMDND12ERR :1; + __IO uint16_t RESERVED1 :8; +} stc_sdif_sacmdest_field_t; + +typedef struct stc_sdif_shctl2_field +{ + union { + struct { + __IO uint16_t UHSMDSEL :3; + __IO uint16_t V18SGNEN :1; + __IO uint16_t DRVSEL :2; + __IO uint16_t DOTUING :1; + __IO uint16_t SMPCLKSEL :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t ASYINTEN :1; + __IO uint16_t PREVALEN :1; + }; + struct { + __IO uint16_t UHSMDSEL0 :1; + __IO uint16_t UHSMDSEL1 :1; + __IO uint16_t UHSMDSEL2 :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t DRVSEL0 :1; + __IO uint16_t DRVSEL1 :1; + __IO uint16_t RESERVED2 :10; + }; + }; +} stc_sdif_shctl2_field_t; + +typedef struct stc_sdif_capblty0_field +{ + union { + struct { + __IO uint16_t TOCLKFREQ :6; + __IO uint16_t RESERVED0 :1; + __IO uint16_t TOCLKUNIT :1; + __IO uint16_t SDBASECLK :8; + }; + struct { + __IO uint16_t TOCLKFREQ0 :1; + __IO uint16_t TOCLKFREQ1 :1; + __IO uint16_t TOCLKFREQ2 :1; + __IO uint16_t TOCLKFREQ3 :1; + __IO uint16_t TOCLKFREQ4 :1; + __IO uint16_t TOCLKFREQ5 :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SDBASECLK0 :1; + __IO uint16_t SDBASECLK1 :1; + __IO uint16_t SDBASECLK2 :1; + __IO uint16_t SDBASECLK3 :1; + __IO uint16_t SDBASECLK4 :1; + __IO uint16_t SDBASECLK5 :1; + __IO uint16_t SDBASECLK6 :1; + __IO uint16_t SDBASECLK7 :1; + }; + }; +} stc_sdif_capblty0_field_t; + +typedef struct stc_sdif_capblty1_field +{ + union { + struct { + __IO uint16_t MAXBLCKLEN :2; + __IO uint16_t EMBD8BIT :1; + __IO uint16_t ADMA2SPT :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t HGHSPDSPT :1; + __IO uint16_t SDMASPT :1; + __IO uint16_t LWPWRSPT :1; + __IO uint16_t V33SPT :1; + __IO uint16_t V30SPT :1; + __IO uint16_t V18SPT :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t BUS64SPT :1; + __IO uint16_t ASYINTSPT :1; + __IO uint16_t STOPTYPE :2; + }; + struct { + __IO uint16_t MAXBLCKLEN0 :1; + __IO uint16_t MAXBLCKLEN1 :1; + __IO uint16_t RESERVED2 :12; + __IO uint16_t STOPTYPE0 :1; + __IO uint16_t STOPTYPE1 :1; + }; + }; +} stc_sdif_capblty1_field_t; + +typedef struct stc_sdif_capblty2_field +{ + union { + struct { + __IO uint16_t SDR50SPT :1; + __IO uint16_t SDR104SPT :1; + __IO uint16_t DDR50SPT :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t DRVTPASPT :1; + __IO uint16_t DRVTPCSPT :1; + __IO uint16_t DRVTPDSPT :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t TMCNTRETN :4; + __IO uint16_t RESERVED3 :1; + __IO uint16_t USETNSDR50 :1; + __IO uint16_t RETNMODE :2; + }; + struct { + __IO uint16_t RESERVED2 :8; + __IO uint16_t TMCNTRETN0 :1; + __IO uint16_t TMCNTRETN1 :1; + __IO uint16_t TMCNTRETN2 :1; + __IO uint16_t TMCNTRETN3 :1; + __IO uint16_t RESERVED4 :2; + __IO uint16_t RETNMODE0 :1; + __IO uint16_t RETNMODE1 :1; + }; + }; +} stc_sdif_capblty2_field_t; + +typedef struct stc_sdif_capblty3_field +{ + union { + struct { + __IO uint16_t CLKMULTPL :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t CLKMULTPL0 :1; + __IO uint16_t CLKMULTPL1 :1; + __IO uint16_t CLKMULTPL2 :1; + __IO uint16_t CLKMULTPL3 :1; + __IO uint16_t CLKMULTPL4 :1; + __IO uint16_t CLKMULTPL5 :1; + __IO uint16_t CLKMULTPL6 :1; + __IO uint16_t CLKMULTPL7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_capblty3_field_t; + +typedef struct stc_sdif_mxccapy0_field +{ + union { + struct { + __IO uint16_t V33MAXCUR :8; + __IO uint16_t V30MAXCUR :8; + }; + struct { + __IO uint16_t V33MAXCUR0 :1; + __IO uint16_t V33MAXCUR1 :1; + __IO uint16_t V33MAXCUR2 :1; + __IO uint16_t V33MAXCUR3 :1; + __IO uint16_t V33MAXCUR4 :1; + __IO uint16_t V33MAXCUR5 :1; + __IO uint16_t V33MAXCUR6 :1; + __IO uint16_t V33MAXCUR7 :1; + __IO uint16_t V30MAXCUR0 :1; + __IO uint16_t V30MAXCUR1 :1; + __IO uint16_t V30MAXCUR2 :1; + __IO uint16_t V30MAXCUR3 :1; + __IO uint16_t V30MAXCUR4 :1; + __IO uint16_t V30MAXCUR5 :1; + __IO uint16_t V30MAXCUR6 :1; + __IO uint16_t V30MAXCUR7 :1; + }; + }; +} stc_sdif_mxccapy0_field_t; + +typedef struct stc_sdif_mxccapy1_field +{ + union { + struct { + __IO uint16_t V18MAXCUR :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t V18MAXCUR0 :1; + __IO uint16_t V18MAXCUR1 :1; + __IO uint16_t V18MAXCUR2 :1; + __IO uint16_t V18MAXCUR3 :1; + __IO uint16_t V18MAXCUR4 :1; + __IO uint16_t V18MAXCUR5 :1; + __IO uint16_t V18MAXCUR6 :1; + __IO uint16_t V18MAXCUR7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_mxccapy1_field_t; + +typedef struct stc_sdif_feacest_field +{ + __IO uint16_t FEVNT12ND :1; + __IO uint16_t FEVNTTO :1; + __IO uint16_t FEVNTCRC :1; + __IO uint16_t FEVNTEB :1; + __IO uint16_t FEVNTIDX :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t FEVNTCMD12 :1; + __IO uint16_t RESERVED1 :8; +} stc_sdif_feacest_field_t; + +typedef struct stc_sdif_sfeeist_field +{ + __IO uint16_t FETOERR :1; + __IO uint16_t FECRCERR :1; + __IO uint16_t FEEBERR :1; + __IO uint16_t FEIDXERR :1; + __IO uint16_t FEDTOTERR :1; + __IO uint16_t FEDTCRCERR :1; + __IO uint16_t FEDTEBERR :1; + __IO uint16_t FECRLTERR :1; + __IO uint16_t FEA12ERR :1; + __IO uint16_t FEADMAERR :1; + __IO uint16_t FETUNEERR :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t FEACKERR :1; + __IO uint16_t FEA19ERR :1; + __IO uint16_t FEAHBMSERR :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_sfeeist_field_t; + +typedef struct stc_sdif_admaest_field +{ + union { + struct { + __IO uint8_t ADMAERRS :2; + __IO uint8_t ADMALENME :1; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t ADMAERRS0 :1; + __IO uint8_t ADMAERRS1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_sdif_admaest_field_t; + +typedef struct stc_sdif_sadsa0_field +{ + union { + struct { + __IO uint16_t ADR1500 :16; + }; + struct { + __IO uint16_t ADR15000 :1; + __IO uint16_t ADR15001 :1; + __IO uint16_t ADR15002 :1; + __IO uint16_t ADR15003 :1; + __IO uint16_t ADR15004 :1; + __IO uint16_t ADR15005 :1; + __IO uint16_t ADR15006 :1; + __IO uint16_t ADR15007 :1; + __IO uint16_t ADR15008 :1; + __IO uint16_t ADR15009 :1; + __IO uint16_t ADR150010 :1; + __IO uint16_t ADR150011 :1; + __IO uint16_t ADR150012 :1; + __IO uint16_t ADR150013 :1; + __IO uint16_t ADR150014 :1; + __IO uint16_t ADR150015 :1; + }; + }; +} stc_sdif_sadsa0_field_t; + +typedef struct stc_sdif_sadsa1_field +{ + union { + struct { + __IO uint16_t ADR3116 :16; + }; + struct { + __IO uint16_t ADR31160 :1; + __IO uint16_t ADR31161 :1; + __IO uint16_t ADR31162 :1; + __IO uint16_t ADR31163 :1; + __IO uint16_t ADR31164 :1; + __IO uint16_t ADR31165 :1; + __IO uint16_t ADR31166 :1; + __IO uint16_t ADR31167 :1; + __IO uint16_t ADR31168 :1; + __IO uint16_t ADR31169 :1; + __IO uint16_t ADR311610 :1; + __IO uint16_t ADR311611 :1; + __IO uint16_t ADR311612 :1; + __IO uint16_t ADR311613 :1; + __IO uint16_t ADR311614 :1; + __IO uint16_t ADR311615 :1; + }; + }; +} stc_sdif_sadsa1_field_t; + +typedef struct stc_sdif_sadsa2_field +{ + union { + struct { + __IO uint16_t ADR4732 :16; + }; + struct { + __IO uint16_t ADR47320 :1; + __IO uint16_t ADR47321 :1; + __IO uint16_t ADR47322 :1; + __IO uint16_t ADR47323 :1; + __IO uint16_t ADR47324 :1; + __IO uint16_t ADR47325 :1; + __IO uint16_t ADR47326 :1; + __IO uint16_t ADR47327 :1; + __IO uint16_t ADR47328 :1; + __IO uint16_t ADR47329 :1; + __IO uint16_t ADR473210 :1; + __IO uint16_t ADR473211 :1; + __IO uint16_t ADR473212 :1; + __IO uint16_t ADR473213 :1; + __IO uint16_t ADR473214 :1; + __IO uint16_t ADR473215 :1; + }; + }; +} stc_sdif_sadsa2_field_t; + +typedef struct stc_sdif_sadsa3_field +{ + union { + struct { + __IO uint16_t ADR6348 :16; + }; + struct { + __IO uint16_t ADR63480 :1; + __IO uint16_t ADR63481 :1; + __IO uint16_t ADR63482 :1; + __IO uint16_t ADR63483 :1; + __IO uint16_t ADR63484 :1; + __IO uint16_t ADR63485 :1; + __IO uint16_t ADR63486 :1; + __IO uint16_t ADR63487 :1; + __IO uint16_t ADR63488 :1; + __IO uint16_t ADR63489 :1; + __IO uint16_t ADR634810 :1; + __IO uint16_t ADR634811 :1; + __IO uint16_t ADR634812 :1; + __IO uint16_t ADR634813 :1; + __IO uint16_t ADR634814 :1; + __IO uint16_t ADR634815 :1; + }; + }; +} stc_sdif_sadsa3_field_t; + +typedef struct stc_sdif_sprval0_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval0_field_t; + +typedef struct stc_sdif_sprval1_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval1_field_t; + +typedef struct stc_sdif_sprval2_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval2_field_t; + +typedef struct stc_sdif_sprval3_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval3_field_t; + +typedef struct stc_sdif_sprval4_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval4_field_t; + +typedef struct stc_sdif_sprval5_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval5_field_t; + +typedef struct stc_sdif_sprval6_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval6_field_t; + +typedef struct stc_sdif_sprval7_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval7_field_t; + +typedef struct stc_sdif_sshbctll_field +{ + union { + struct { + __IO uint16_t CLCKPIN :3; + __IO uint16_t RESERVED0 :1; + __IO uint16_t INTINPIN :2; + __IO uint16_t RESERVED2 :2; + __IO uint16_t BUSWDPRST :7; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t CLCKPIN0 :1; + __IO uint16_t CLCKPIN1 :1; + __IO uint16_t CLCKPIN2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t INTINPIN0 :1; + __IO uint16_t INTINPIN1 :1; + __IO uint16_t RESERVED3 :2; + __IO uint16_t BUSWDPRST0 :1; + __IO uint16_t BUSWDPRST1 :1; + __IO uint16_t BUSWDPRST2 :1; + __IO uint16_t BUSWDPRST3 :1; + __IO uint16_t BUSWDPRST4 :1; + __IO uint16_t BUSWDPRST5 :1; + __IO uint16_t BUSWDPRST6 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_sdif_sshbctll_field_t; + +typedef struct stc_sdif_sshbctlh_field +{ + union { + struct { + __IO uint16_t CLCKPINSEL :3; + __IO uint16_t RESERVED0 :1; + __IO uint16_t INTPINSEL :3; + __IO uint16_t RESERVED2 :1; + __IO uint16_t BEPWRCTL :7; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t CLCKPINSEL0 :1; + __IO uint16_t CLCKPINSEL1 :1; + __IO uint16_t CLCKPINSEL2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t INTPINSEL0 :1; + __IO uint16_t INTPINSEL1 :1; + __IO uint16_t INTPINSEL2 :1; + __IO uint16_t RESERVED3 :1; + __IO uint16_t BEPWRCTL0 :1; + __IO uint16_t BEPWRCTL1 :1; + __IO uint16_t BEPWRCTL2 :1; + __IO uint16_t BEPWRCTL3 :1; + __IO uint16_t BEPWRCTL4 :1; + __IO uint16_t BEPWRCTL5 :1; + __IO uint16_t BEPWRCTL6 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_sdif_sshbctlh_field_t; + +typedef struct stc_sdif_sslist_field +{ + union { + struct { + __IO uint16_t SLOTINTSGN :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t SLOTINTSGN0 :1; + __IO uint16_t SLOTINTSGN1 :1; + __IO uint16_t SLOTINTSGN2 :1; + __IO uint16_t SLOTINTSGN3 :1; + __IO uint16_t SLOTINTSGN4 :1; + __IO uint16_t SLOTINTSGN5 :1; + __IO uint16_t SLOTINTSGN6 :1; + __IO uint16_t SLOTINTSGN7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_sslist_field_t; + +typedef struct stc_sdif_shctlv_field +{ + union { + struct { + __IO uint16_t SPECVERNUM :8; + __IO uint16_t VNDVERNUM :8; + }; + struct { + __IO uint16_t SPECVERNUM0 :1; + __IO uint16_t SPECVERNUM1 :1; + __IO uint16_t SPECVERNUM2 :1; + __IO uint16_t SPECVERNUM3 :1; + __IO uint16_t SPECVERNUM4 :1; + __IO uint16_t SPECVERNUM5 :1; + __IO uint16_t SPECVERNUM6 :1; + __IO uint16_t SPECVERNUM7 :1; + __IO uint16_t VNDVERNUM0 :1; + __IO uint16_t VNDVERNUM1 :1; + __IO uint16_t VNDVERNUM2 :1; + __IO uint16_t VNDVERNUM3 :1; + __IO uint16_t VNDVERNUM4 :1; + __IO uint16_t VNDVERNUM5 :1; + __IO uint16_t VNDVERNUM6 :1; + __IO uint16_t VNDVERNUM7 :1; + }; + }; +} stc_sdif_shctlv_field_t; + +typedef struct stc_sdif_ahbcfgl_field +{ + union { + struct { + __IO uint16_t INCRSEL :3; + __IO uint16_t SINEN :1; + __IO uint16_t BSLOCK :1; + __IO uint16_t BSLOCKSEL :1; + __IO uint16_t ENDIANSEL :1; + __IO uint16_t RESERVED0 :9; + }; + struct { + __IO uint16_t INCRSEL0 :1; + __IO uint16_t INCRSEL1 :1; + __IO uint16_t INCRSEL2 :1; + __IO uint16_t RESERVED1 :13; + }; + }; +} stc_sdif_ahbcfgl_field_t; + +typedef struct stc_sdif_spwswcl_field +{ + __IO uint16_t ATPWRSWEN :1; + __IO uint16_t IOREGSEL :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_spwswcl_field_t; + +typedef struct stc_sdif_stunsetl_field +{ + union { + struct { + __IO uint16_t TNPTSEL :8; + __IO uint16_t TNPHSELEN :1; + __IO uint16_t TNERRBDSEL :1; + __IO uint16_t RETNTAPSEL :1; + __IO uint16_t RETNRNGSEL :2; + __IO uint16_t RESERVED1 :3; + }; + struct { + __IO uint16_t TNPTSEL0 :1; + __IO uint16_t TNPTSEL1 :1; + __IO uint16_t TNPTSEL2 :1; + __IO uint16_t TNPTSEL3 :1; + __IO uint16_t TNPTSEL4 :1; + __IO uint16_t TNPTSEL5 :1; + __IO uint16_t TNPTSEL6 :1; + __IO uint16_t TNPTSEL7 :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t RETNRNGSEL0 :1; + __IO uint16_t RETNRNGSEL1 :1; + __IO uint16_t RESERVED2 :3; + }; + }; +} stc_sdif_stunsetl_field_t; + +typedef struct stc_sdif_stunseth_field +{ + union { + struct { + __IO uint16_t CMDCFCHKDS :1; + __IO uint16_t RESERVED0 :7; + __IO uint16_t DTOTCNTVAL :4; + __IO uint16_t RESERVED2 :4; + }; + struct { + __IO uint16_t RESERVED1 :8; + __IO uint16_t DTOTCNTVAL0 :1; + __IO uint16_t DTOTCNTVAL1 :1; + __IO uint16_t DTOTCNTVAL2 :1; + __IO uint16_t DTOTCNTVAL3 :1; + __IO uint16_t RESERVED3 :4; + }; + }; +} stc_sdif_stunseth_field_t; + +typedef struct stc_sdif_stunstl_field +{ + union { + struct { + __IO uint16_t REP8TNRSLT :8; + __IO uint16_t REP3TNRSLT :3; + __IO uint16_t RESERVED0 :5; + }; + struct { + __IO uint16_t REP8TNRSLT0 :1; + __IO uint16_t REP8TNRSLT1 :1; + __IO uint16_t REP8TNRSLT2 :1; + __IO uint16_t REP8TNRSLT3 :1; + __IO uint16_t REP8TNRSLT4 :1; + __IO uint16_t REP8TNRSLT5 :1; + __IO uint16_t REP8TNRSLT6 :1; + __IO uint16_t REP8TNRSLT7 :1; + __IO uint16_t REP3TNRSLT0 :1; + __IO uint16_t REP3TNRSLT1 :1; + __IO uint16_t REP3TNRSLT2 :1; + __IO uint16_t RESERVED1 :5; + }; + }; +} stc_sdif_stunstl_field_t; + +typedef struct stc_sdif_stunsth_field +{ + union { + struct { + __IO uint16_t PRSTTNPNT :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t PRSTTNPNT0 :1; + __IO uint16_t PRSTTNPNT1 :1; + __IO uint16_t PRSTTNPNT2 :1; + __IO uint16_t PRSTTNPNT3 :1; + __IO uint16_t PRSTTNPNT4 :1; + __IO uint16_t PRSTTNPNT5 :1; + __IO uint16_t PRSTTNPNT6 :1; + __IO uint16_t PRSTTNPNT7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_stunsth_field_t; + +typedef struct stc_sdif_pswistl_field +{ + __IO uint16_t INT5MS :1; + __IO uint16_t INT1MS :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_pswistl_field_t; + +typedef struct stc_sdif_pswistel_field +{ + __IO uint16_t INT5MSSTS :1; + __IO uint16_t INT1MSSTS :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_pswistel_field_t; + +typedef struct stc_sdif_pswisgel_field +{ + __IO uint16_t INT5MSSGEN :1; + __IO uint16_t INT1MSSGEN :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_pswisgel_field_t; + +typedef struct stc_sdif_mmcsdcl_field +{ + __IO uint16_t LCKRSTESD :1; + __IO uint16_t RSTMMC :1; + __IO uint16_t VCCCTLMMC :1; + __IO uint16_t VCCQCTLMMC :1; + __IO uint16_t RESERVED0 :4; + __IO uint16_t MMCDDRSEL :1; + __IO uint16_t CMDDATDLY :1; + __IO uint16_t RESERVED1 :6; +} stc_sdif_mmcsdcl_field_t; + +typedef struct stc_sdif_mmcsdch_field +{ + __IO uint16_t BTACKENMMC :1; + __IO uint16_t BTABTENMMC :1; + __IO uint16_t BTMDENMMC :1; + __IO uint16_t RESERVED0 :13; +} stc_sdif_mmcsdch_field_t; + +typedef struct stc_sdif_mcwirqc0_field +{ + __IO uint16_t WTIRQEN :1; + __IO uint16_t WTIRQST :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_mcwirqc0_field_t; + +typedef struct stc_sdif_mcwirqc1_field +{ + union { + struct { + __IO uint16_t WTIRQCNCLR :16; + }; + struct { + __IO uint16_t WTIRQCNCLR0 :1; + __IO uint16_t WTIRQCNCLR1 :1; + __IO uint16_t WTIRQCNCLR2 :1; + __IO uint16_t WTIRQCNCLR3 :1; + __IO uint16_t WTIRQCNCLR4 :1; + __IO uint16_t WTIRQCNCLR5 :1; + __IO uint16_t WTIRQCNCLR6 :1; + __IO uint16_t WTIRQCNCLR7 :1; + __IO uint16_t WTIRQCNCLR8 :1; + __IO uint16_t WTIRQCNCLR9 :1; + __IO uint16_t WTIRQCNCLR10 :1; + __IO uint16_t WTIRQCNCLR11 :1; + __IO uint16_t WTIRQCNCLR12 :1; + __IO uint16_t WTIRQCNCLR13 :1; + __IO uint16_t WTIRQCNCLR14 :1; + __IO uint16_t WTIRQCNCLR15 :1; + }; + }; +} stc_sdif_mcwirqc1_field_t; + +typedef struct stc_sdif_mcwirqc2_field +{ + union { + struct { + __IO uint16_t WTIRQCNCLR :16; + }; + struct { + __IO uint16_t WTIRQCNCLR0 :1; + __IO uint16_t WTIRQCNCLR1 :1; + __IO uint16_t WTIRQCNCLR2 :1; + __IO uint16_t WTIRQCNCLR3 :1; + __IO uint16_t WTIRQCNCLR4 :1; + __IO uint16_t WTIRQCNCLR5 :1; + __IO uint16_t WTIRQCNCLR6 :1; + __IO uint16_t WTIRQCNCLR7 :1; + __IO uint16_t WTIRQCNCLR8 :1; + __IO uint16_t WTIRQCNCLR9 :1; + __IO uint16_t WTIRQCNCLR10 :1; + __IO uint16_t WTIRQCNCLR11 :1; + __IO uint16_t WTIRQCNCLR12 :1; + __IO uint16_t WTIRQCNCLR13 :1; + __IO uint16_t WTIRQCNCLR14 :1; + __IO uint16_t WTIRQCNCLR15 :1; + }; + }; +} stc_sdif_mcwirqc2_field_t; + +typedef struct stc_sdif_mcwirqc3_field +{ + union { + struct { + __IO uint16_t WTIRQCNCLR :16; + }; + struct { + __IO uint16_t WTIRQCNCLR0 :1; + __IO uint16_t WTIRQCNCLR1 :1; + __IO uint16_t WTIRQCNCLR2 :1; + __IO uint16_t WTIRQCNCLR3 :1; + __IO uint16_t WTIRQCNCLR4 :1; + __IO uint16_t WTIRQCNCLR5 :1; + __IO uint16_t WTIRQCNCLR6 :1; + __IO uint16_t WTIRQCNCLR7 :1; + __IO uint16_t WTIRQCNCLR8 :1; + __IO uint16_t WTIRQCNCLR9 :1; + __IO uint16_t WTIRQCNCLR10 :1; + __IO uint16_t WTIRQCNCLR11 :1; + __IO uint16_t WTIRQCNCLR12 :1; + __IO uint16_t WTIRQCNCLR13 :1; + __IO uint16_t WTIRQCNCLR14 :1; + __IO uint16_t WTIRQCNCLR15 :1; + }; + }; +} stc_sdif_mcwirqc3_field_t; + +typedef struct stc_sdif_mcrpckbl_field +{ + union { + struct { + __IO uint16_t CHECKBIT1 :7; + __IO uint16_t CHECKBIT2 :6; + __IO uint16_t RESERVED0 :3; + }; + struct { + __IO uint16_t CHECKBIT10 :1; + __IO uint16_t CHECKBIT11 :1; + __IO uint16_t CHECKBIT12 :1; + __IO uint16_t CHECKBIT13 :1; + __IO uint16_t CHECKBIT14 :1; + __IO uint16_t CHECKBIT15 :1; + __IO uint16_t CHECKBIT16 :1; + __IO uint16_t CHECKBIT20 :1; + __IO uint16_t CHECKBIT21 :1; + __IO uint16_t CHECKBIT22 :1; + __IO uint16_t CHECKBIT23 :1; + __IO uint16_t CHECKBIT24 :1; + __IO uint16_t CHECKBIT25 :1; + __IO uint16_t RESERVED1 :3; + }; + }; +} stc_sdif_mcrpckbl_field_t; + +typedef struct stc_sdif_scdetecs_field +{ + union { + struct { + __IO uint16_t RESERVED0 :8; + __IO uint16_t CDDEBTCVAL :4; + __IO uint16_t RESERVED2 :4; + }; + struct { + __IO uint16_t RESERVED1 :8; + __IO uint16_t CDDEBTCVAL0 :1; + __IO uint16_t CDDEBTCVAL1 :1; + __IO uint16_t CDDEBTCVAL2 :1; + __IO uint16_t CDDEBTCVAL3 :1; + __IO uint16_t RESERVED3 :4; + }; + }; +} stc_sdif_scdetecs_field_t; + +/******************************************************************************* +* SWWDT_MODULE +*******************************************************************************/ +typedef struct stc_swwdt_wdogcontrol_field +{ + union { + struct { + __IO uint32_t INTEN :1; + __IO uint32_t RESEN :1; + __IO uint32_t TWD :2; + __IO uint32_t SPM :1; + __IO uint32_t RESERVED1 :27; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TWD0 :1; + __IO uint32_t TWD1 :1; + __IO uint32_t RESERVED2 :28; + }; + }; +} stc_swwdt_wdogcontrol_field_t; + +typedef struct stc_swwdt_wdogris_field +{ + __IO uint32_t RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_swwdt_wdogris_field_t; + +typedef struct stc_swwdt_wdogspmc_field +{ + __IO uint32_t TGR :1; + __IO uint32_t RESERVED0 :31; +} stc_swwdt_wdogspmc_field_t; + +/******************************************************************************* +* UNIQUE_ID_MODULE +*******************************************************************************/ +typedef struct stc_unique_id_uidr0_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t UID :28; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t UID0 :1; + __IO uint32_t UID1 :1; + __IO uint32_t UID2 :1; + __IO uint32_t UID3 :1; + __IO uint32_t UID4 :1; + __IO uint32_t UID5 :1; + __IO uint32_t UID6 :1; + __IO uint32_t UID7 :1; + __IO uint32_t UID8 :1; + __IO uint32_t UID9 :1; + __IO uint32_t UID10 :1; + __IO uint32_t UID11 :1; + __IO uint32_t UID12 :1; + __IO uint32_t UID13 :1; + __IO uint32_t UID14 :1; + __IO uint32_t UID15 :1; + __IO uint32_t UID16 :1; + __IO uint32_t UID17 :1; + __IO uint32_t UID18 :1; + __IO uint32_t UID19 :1; + __IO uint32_t UID20 :1; + __IO uint32_t UID21 :1; + __IO uint32_t UID22 :1; + __IO uint32_t UID23 :1; + __IO uint32_t UID24 :1; + __IO uint32_t UID25 :1; + __IO uint32_t UID26 :1; + __IO uint32_t UID27 :1; + }; + }; +} stc_unique_id_uidr0_field_t; + +typedef struct stc_unique_id_uidr1_field +{ + union { + struct { + __IO uint32_t UID :13; + __IO uint32_t RESERVED0 :19; + }; + struct { + __IO uint32_t UID0 :1; + __IO uint32_t UID1 :1; + __IO uint32_t UID2 :1; + __IO uint32_t UID3 :1; + __IO uint32_t UID4 :1; + __IO uint32_t UID5 :1; + __IO uint32_t UID6 :1; + __IO uint32_t UID7 :1; + __IO uint32_t UID8 :1; + __IO uint32_t UID9 :1; + __IO uint32_t UID10 :1; + __IO uint32_t UID11 :1; + __IO uint32_t UID12 :1; + __IO uint32_t RESERVED1 :19; + }; + }; +} stc_unique_id_uidr1_field_t; + +/******************************************************************************* +* USB_MODULE +*******************************************************************************/ +typedef struct stc_usb_hcnt_field +{ + __IO uint16_t HOST :1; + __IO uint16_t URST :1; + __IO uint16_t SOFIRE :1; + __IO uint16_t DIRE :1; + __IO uint16_t CNNIRE :1; + __IO uint16_t CMPIRE :1; + __IO uint16_t URIRE :1; + __IO uint16_t RWKIRE :1; + __IO uint16_t RETRY :1; + __IO uint16_t CANCEL :1; + __IO uint16_t SOFSTEP :1; + __IO uint16_t RESERVED0 :5; +} stc_usb_hcnt_field_t; + +typedef struct stc_usb_hirq_field +{ + __IO uint8_t SOFIRQ :1; + __IO uint8_t DIRQ :1; + __IO uint8_t CNNIRQ :1; + __IO uint8_t CMPIRQ :1; + __IO uint8_t URIRQ :1; + __IO uint8_t RWKIRQ :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t TCAN :1; +} stc_usb_hirq_field_t; + +typedef struct stc_usb_herr_field +{ + union { + struct { + __IO uint8_t HS :2; + __IO uint8_t STUFF :1; + __IO uint8_t TGERR :1; + __IO uint8_t CRC :1; + __IO uint8_t TOUT :1; + __IO uint8_t RERR :1; + __IO uint8_t LSTSOF :1; + }; + struct { + __IO uint8_t HS0 :1; + __IO uint8_t HS1 :1; + __IO uint8_t RESERVED0 :6; + }; + }; +} stc_usb_herr_field_t; + +typedef struct stc_usb_hstate_field +{ + __IO uint8_t CSTAT :1; + __IO uint8_t TMODE :1; + __IO uint8_t SUSP :1; + __IO uint8_t SOFBUSY :1; + __IO uint8_t CLKSEL :1; + __IO uint8_t ALIVE :1; + __IO uint8_t RESERVED0 :2; +} stc_usb_hstate_field_t; + +typedef struct stc_usb_hfcomp_field +{ + union { + struct { + __IO uint8_t FRAMECOMP :8; + }; + struct { + __IO uint8_t FRAMECOMP0 :1; + __IO uint8_t FRAMECOMP1 :1; + __IO uint8_t FRAMECOMP2 :1; + __IO uint8_t FRAMECOMP3 :1; + __IO uint8_t FRAMECOMP4 :1; + __IO uint8_t FRAMECOMP5 :1; + __IO uint8_t FRAMECOMP6 :1; + __IO uint8_t FRAMECOMP7 :1; + }; + }; +} stc_usb_hfcomp_field_t; + +typedef struct stc_usb_hrtimer_field +{ + union { + struct { + __IO uint16_t RTIMER :16; + }; + struct { + __IO uint16_t RTIMER0 :1; + __IO uint16_t RTIMER1 :1; + __IO uint16_t RTIMER2 :1; + __IO uint16_t RTIMER3 :1; + __IO uint16_t RTIMER4 :1; + __IO uint16_t RTIMER5 :1; + __IO uint16_t RTIMER6 :1; + __IO uint16_t RTIMER7 :1; + __IO uint16_t RTIMER8 :1; + __IO uint16_t RTIMER9 :1; + __IO uint16_t RTIMER10 :1; + __IO uint16_t RTIMER11 :1; + __IO uint16_t RTIMER12 :1; + __IO uint16_t RTIMER13 :1; + __IO uint16_t RTIMER14 :1; + __IO uint16_t RTIMER15 :1; + }; + }; +} stc_usb_hrtimer_field_t; + +typedef struct stc_usb_hrtimer2_field +{ + union { + struct { + __IO uint8_t RTIMER2 :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t RTIMER20 :1; + __IO uint8_t RTIMER21 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_usb_hrtimer2_field_t; + +typedef struct stc_usb_hadr_field +{ + union { + struct { + __IO uint8_t ADDRESS :7; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t ADDRESS0 :1; + __IO uint8_t ADDRESS1 :1; + __IO uint8_t ADDRESS2 :1; + __IO uint8_t ADDRESS3 :1; + __IO uint8_t ADDRESS4 :1; + __IO uint8_t ADDRESS5 :1; + __IO uint8_t ADDRESS6 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_usb_hadr_field_t; + +typedef struct stc_usb_heof_field +{ + union { + struct { + __IO uint16_t HEOF :14; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t HEOF0 :1; + __IO uint16_t HEOF1 :1; + __IO uint16_t HEOF2 :1; + __IO uint16_t HEOF3 :1; + __IO uint16_t HEOF4 :1; + __IO uint16_t HEOF5 :1; + __IO uint16_t HEOF6 :1; + __IO uint16_t HEOF7 :1; + __IO uint16_t HEOF8 :1; + __IO uint16_t HEOF9 :1; + __IO uint16_t HEOF10 :1; + __IO uint16_t HEOF11 :1; + __IO uint16_t HEOF12 :1; + __IO uint16_t HEOF13 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_usb_heof_field_t; + +typedef struct stc_usb_hframe_field +{ + union { + struct { + __IO uint16_t FRAME :11; + __IO uint16_t RESERVED0 :5; + }; + struct { + __IO uint16_t FRAME0 :1; + __IO uint16_t FRAME1 :1; + __IO uint16_t FRAME2 :1; + __IO uint16_t FRAME3 :1; + __IO uint16_t FRAME4 :1; + __IO uint16_t FRAME5 :1; + __IO uint16_t FRAME6 :1; + __IO uint16_t FRAME7 :1; + __IO uint16_t FRAME8 :1; + __IO uint16_t FRAME9 :1; + __IO uint16_t FRAME10 :1; + __IO uint16_t RESERVED1 :5; + }; + }; +} stc_usb_hframe_field_t; + +typedef struct stc_usb_htoken_field +{ + union { + struct { + __IO uint8_t ENDPT :4; + __IO uint8_t TKNEN :3; + __IO uint8_t TGGL :1; + }; + struct { + __IO uint8_t ENDPT0 :1; + __IO uint8_t ENDPT1 :1; + __IO uint8_t ENDPT2 :1; + __IO uint8_t ENDPT3 :1; + __IO uint8_t TKNEN0 :1; + __IO uint8_t TKNEN1 :1; + __IO uint8_t TKNEN2 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_usb_htoken_field_t; + +typedef struct stc_usb_udcc_field +{ + __IO uint16_t PWC :1; + __IO uint16_t RFBK :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t STALCLREN :1; + __IO uint16_t USTP :1; + __IO uint16_t HCONX :1; + __IO uint16_t RESUM :1; + __IO uint16_t RST :1; + __IO uint16_t RESERVED1 :8; +} stc_usb_udcc_field_t; + +typedef struct stc_usb_ep0c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t RESERVED1 :6; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep0c_field_t; + +typedef struct stc_usb_ep1c_field +{ + union { + struct { + __IO uint16_t PKS :9; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t PKS7 :1; + __IO uint16_t PKS8 :1; + __IO uint16_t RESERVED0 :4; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_usb_ep1c_field_t; + +typedef struct stc_usb_ep2c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep2c_field_t; + +typedef struct stc_usb_ep3c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep3c_field_t; + +typedef struct stc_usb_ep4c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep4c_field_t; + +typedef struct stc_usb_ep5c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep5c_field_t; + +typedef struct stc_usb_tmsp_field +{ + union { + struct { + __IO uint16_t TMSP :11; + __IO uint16_t RESERVED0 :5; + }; + struct { + __IO uint16_t TMSP0 :1; + __IO uint16_t TMSP1 :1; + __IO uint16_t TMSP2 :1; + __IO uint16_t TMSP3 :1; + __IO uint16_t TMSP4 :1; + __IO uint16_t TMSP5 :1; + __IO uint16_t TMSP6 :1; + __IO uint16_t TMSP7 :1; + __IO uint16_t TMSP8 :1; + __IO uint16_t TMSP9 :1; + __IO uint16_t TMSP10 :1; + __IO uint16_t RESERVED1 :5; + }; + }; +} stc_usb_tmsp_field_t; + +typedef struct stc_usb_udcs_field +{ + __IO uint8_t CONF :1; + __IO uint8_t SETP :1; + __IO uint8_t WKUP :1; + __IO uint8_t BRST :1; + __IO uint8_t SOF :1; + __IO uint8_t SUSP :1; + __IO uint8_t RESERVED0 :2; +} stc_usb_udcs_field_t; + +typedef struct stc_usb_udcie_field +{ + __IO uint8_t CONFIE :1; + __IO uint8_t CONFN :1; + __IO uint8_t WKUPIE :1; + __IO uint8_t BRSTIE :1; + __IO uint8_t SOFIE :1; + __IO uint8_t SUSPIE :1; + __IO uint8_t RESERVED0 :2; +} stc_usb_udcie_field_t; + +typedef struct stc_usb_ep0is_field +{ + __IO uint16_t RESERVED0 :10; + __IO uint16_t DRQI :1; + __IO uint16_t RESERVED1 :3; + __IO uint16_t DRQIIE :1; + __IO uint16_t BFINI :1; +} stc_usb_ep0is_field_t; + +typedef struct stc_usb_ep0os_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQO :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQOIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep0os_field_t; + +typedef struct stc_usb_ep1s_field +{ + union { + struct { + __IO uint16_t SIZE :9; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t SIZE7 :1; + __IO uint16_t SIZE8 :1; + __IO uint16_t RESERVED1 :7; + }; + }; +} stc_usb_ep1s_field_t; + +typedef struct stc_usb_ep2s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep2s_field_t; + +typedef struct stc_usb_ep3s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep3s_field_t; + +typedef struct stc_usb_ep4s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep4s_field_t; + +typedef struct stc_usb_ep5s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep5s_field_t; + +typedef struct stc_usb_ep0dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep0dt_field_t; + +typedef struct stc_usb_ep1dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep1dt_field_t; + +typedef struct stc_usb_ep2dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep2dt_field_t; + +typedef struct stc_usb_ep3dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep3dt_field_t; + +typedef struct stc_usb_ep4dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep4dt_field_t; + +typedef struct stc_usb_ep5dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep5dt_field_t; + +/******************************************************************************* +* USBCLK_MODULE +*******************************************************************************/ +typedef struct stc_usbclk_uccr_field +{ + __IO uint8_t UCEN0 :1; + __IO uint8_t UCSEL :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t UCEN1 :1; + __IO uint8_t RESERVED1 :4; +} stc_usbclk_uccr_field_t; + +typedef struct stc_usbclk_upcr1_field +{ + __IO uint8_t UPLLEN :1; + __IO uint8_t UPINC :1; + __IO uint8_t RESERVED0 :6; +} stc_usbclk_upcr1_field_t; + +typedef struct stc_usbclk_upcr2_field +{ + union { + struct { + __IO uint8_t UPOWT :3; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t UPOWT0 :1; + __IO uint8_t UPOWT1 :1; + __IO uint8_t UPOWT2 :1; + __IO uint8_t RESERVED1 :5; + }; + }; +} stc_usbclk_upcr2_field_t; + +typedef struct stc_usbclk_upcr3_field +{ + union { + struct { + __IO uint8_t UPLLK :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t UPLLK0 :1; + __IO uint8_t UPLLK1 :1; + __IO uint8_t UPLLK2 :1; + __IO uint8_t UPLLK3 :1; + __IO uint8_t UPLLK4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_usbclk_upcr3_field_t; + +typedef struct stc_usbclk_upcr4_field +{ + union { + struct { + __IO uint8_t UPLLN :7; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t UPLLN0 :1; + __IO uint8_t UPLLN1 :1; + __IO uint8_t UPLLN2 :1; + __IO uint8_t UPLLN3 :1; + __IO uint8_t UPLLN4 :1; + __IO uint8_t UPLLN5 :1; + __IO uint8_t UPLLN6 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_usbclk_upcr4_field_t; + +typedef struct stc_usbclk_up_str_field +{ + __IO uint8_t UPRDY :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_up_str_field_t; + +typedef struct stc_usbclk_upint_enr_field +{ + __IO uint8_t UPCSE :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_upint_enr_field_t; + +typedef struct stc_usbclk_upint_clr_field +{ + __IO uint8_t UPCSC :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_upint_clr_field_t; + +typedef struct stc_usbclk_upint_str_field +{ + __IO uint8_t UPCSI :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_upint_str_field_t; + +typedef struct stc_usbclk_upcr5_field +{ + union { + struct { + __IO uint8_t UPLLM :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t UPLLM0 :1; + __IO uint8_t UPLLM1 :1; + __IO uint8_t UPLLM2 :1; + __IO uint8_t UPLLM3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_usbclk_upcr5_field_t; + +typedef struct stc_usbclk_usben0_field +{ + __IO uint8_t USBEN0 :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_usben0_field_t; + +typedef struct stc_usbclk_usben1_field +{ + __IO uint8_t USBEN1 :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_usben1_field_t; + +/******************************************************************************* +* WC_MODULE +*******************************************************************************/ +typedef struct stc_wc_wcrd_field +{ + union { + struct { + __IO uint8_t CTR :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t CTR0 :1; + __IO uint8_t CTR1 :1; + __IO uint8_t CTR2 :1; + __IO uint8_t CTR3 :1; + __IO uint8_t CTR4 :1; + __IO uint8_t CTR5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_wc_wcrd_field_t; + +typedef struct stc_wc_wcrl_field +{ + union { + struct { + __IO uint8_t RLC :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t RLC0 :1; + __IO uint8_t RLC1 :1; + __IO uint8_t RLC2 :1; + __IO uint8_t RLC3 :1; + __IO uint8_t RLC4 :1; + __IO uint8_t RLC5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_wc_wcrl_field_t; + +typedef struct stc_wc_wccr_field +{ + union { + struct { + __IO uint8_t WCIF :1; + __IO uint8_t WCIE :1; + __IO uint8_t CS :2; + __IO uint8_t RESERVED1 :2; + __IO uint8_t WCOP :1; + __IO uint8_t WCEN :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS0 :1; + __IO uint8_t CS1 :1; + __IO uint8_t RESERVED2 :4; + }; + }; +} stc_wc_wccr_field_t; + +typedef struct stc_wc_clk_sel_field +{ + union { + struct { + __IO uint16_t SEL_IN :2; + __IO uint16_t RESERVED0 :6; + __IO uint16_t SEL_OUT :3; + __IO uint16_t RESERVED2 :5; + }; + struct { + __IO uint16_t SEL_IN0 :1; + __IO uint16_t SEL_IN1 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t SEL_OUT0 :1; + __IO uint16_t SEL_OUT1 :1; + __IO uint16_t SEL_OUT2 :1; + __IO uint16_t RESERVED3 :5; + }; + }; +} stc_wc_clk_sel_field_t; + +typedef struct stc_wc_clk_en_field +{ + __IO uint8_t CLK_EN :1; + __IO uint8_t CLK_EN_R :1; + __IO uint8_t RESERVED0 :6; +} stc_wc_clk_en_field_t; + +/******************************************************************************* +* Peripheral register structures +*******************************************************************************/ + +/******************************************************************************* +* ADC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t ADSR; + stc_adc_adsr_field_t ADSR_f; + }; + union { + __IO uint8_t ADCR; + stc_adc_adcr_field_t ADCR_f; + }; + __IO uint8_t RESERVED0[6]; + union { + __IO uint8_t SFNS; + stc_adc_sfns_field_t SFNS_f; + }; + union { + __IO uint8_t SCCR; + stc_adc_sccr_field_t SCCR_f; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint32_t SCFD; + stc_adc_scfd_field_t SCFD_f; + struct { + union { + __IO uint16_t SCFDL; + struct { + __IO uint8_t SCFDLL; + __IO uint8_t SCFDLH; + }; + }; + union { + __IO uint16_t SCFDH; + struct { + __IO uint8_t SCFDHL; + __IO uint8_t SCFDHH; + }; + }; + }; + __IO uint32_t SCFD_FDAS1; + stc_adc_scfd_fdas1_field_t SCFD_FDAS1_f; + struct { + union { + __IO uint16_t SCFD_FDAS1L; + struct { + __IO uint8_t SCFD_FDAS1LL; + __IO uint8_t SCFD_FDAS1LH; + }; + }; + union { + __IO uint16_t SCFD_FDAS1H; + struct { + __IO uint8_t SCFD_FDAS1HL; + __IO uint8_t SCFD_FDAS1HH; + }; + }; + }; + }; + union { + __IO uint16_t SCIS23; + stc_adc_scis23_field_t SCIS23_f; + struct { + __IO uint8_t SCIS23L; + __IO uint8_t SCIS23H; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t SCIS01; + stc_adc_scis01_field_t SCIS01_f; + struct { + __IO uint8_t SCIS01L; + __IO uint8_t SCIS01H; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint8_t PFNS; + stc_adc_pfns_field_t PFNS_f; + }; + union { + __IO uint8_t PCCR; + stc_adc_pccr_field_t PCCR_f; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint32_t PCFD; + stc_adc_pcfd_field_t PCFD_f; + struct { + union { + __IO uint16_t PCFDL; + struct { + __IO uint8_t PCFDLL; + __IO uint8_t PCFDLH; + }; + }; + union { + __IO uint16_t PCFDH; + struct { + __IO uint8_t PCFDHL; + __IO uint8_t PCFDHH; + }; + }; + }; + __IO uint32_t PCFD_FDAS1; + stc_adc_pcfd_fdas1_field_t PCFD_FDAS1_f; + struct { + union { + __IO uint16_t PCFD_FDAS1L; + struct { + __IO uint8_t PCFD_FDAS1LL; + __IO uint8_t PCFD_FDAS1LH; + }; + }; + union { + __IO uint16_t PCFD_FDAS1H; + struct { + __IO uint8_t PCFD_FDAS1HL; + __IO uint8_t PCFD_FDAS1HH; + }; + }; + }; + }; + union { + __IO uint8_t PCIS; + stc_adc_pcis_field_t PCIS_f; + }; + __IO uint8_t RESERVED5[3]; + union { + __IO uint8_t CMPCR; + stc_adc_cmpcr_field_t CMPCR_f; + }; + __IO uint8_t RESERVED6[1]; + union { + __IO uint16_t CMPD; + stc_adc_cmpd_field_t CMPD_f; + struct { + __IO uint8_t CMPDL; + __IO uint8_t CMPDH; + }; + }; + union { + __IO uint16_t ADSS23; + stc_adc_adss23_field_t ADSS23_f; + struct { + __IO uint8_t ADSS23L; + __IO uint8_t ADSS23H; + }; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint16_t ADSS01; + stc_adc_adss01_field_t ADSS01_f; + struct { + __IO uint8_t ADSS01L; + __IO uint8_t ADSS01H; + }; + }; + __IO uint8_t RESERVED8[2]; + union { + __IO uint16_t ADST01; + stc_adc_adst01_field_t ADST01_f; + struct { + __IO uint8_t ADST01L; + __IO uint8_t ADST01H; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint8_t ADCT; + stc_adc_adct_field_t ADCT_f; + }; + __IO uint8_t RESERVED10[3]; + union { + __IO uint8_t PRTSL; + stc_adc_prtsl_field_t PRTSL_f; + }; + union { + __IO uint8_t SCTSL; + stc_adc_sctsl_field_t SCTSL_f; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t ADCEN; + stc_adc_adcen_field_t ADCEN_f; + struct { + __IO uint8_t ADCENL; + __IO uint8_t ADCENH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint32_t CALSR; + stc_adc_calsr_field_t CALSR_f; + struct { + union { + __IO uint16_t CALSRL; + struct { + __IO uint8_t CALSRLL; + __IO uint8_t CALSRLH; + }; + }; + union { + __IO uint16_t CALSRH; + struct { + __IO uint8_t CALSRHL; + __IO uint8_t CALSRHH; + }; + }; + }; + }; + union { + __IO uint8_t WCMRCOT; + stc_adc_wcmrcot_field_t WCMRCOT_f; + }; + __IO uint8_t RESERVED13[3]; + union { + __IO uint8_t WCMRCIF; + stc_adc_wcmrcif_field_t WCMRCIF_f; + }; + __IO uint8_t RESERVED14[3]; + union { + __IO uint8_t WCMPCR; + stc_adc_wcmpcr_field_t WCMPCR_f; + }; + union { + __IO uint8_t WCMPSR; + stc_adc_wcmpsr_field_t WCMPSR_f; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint16_t WCMPDL; + stc_adc_wcmpdl_field_t WCMPDL_f; + struct { + __IO uint8_t WCMPDLL; + __IO uint8_t WCMPDLH; + }; + }; + union { + __IO uint16_t WCMPDH; + stc_adc_wcmpdh_field_t WCMPDH_f; + struct { + __IO uint8_t WCMPDHL; + __IO uint8_t WCMPDHH; + }; + }; +} FM_ADC_TypeDef, FM4_ADC_TypeDef; + +/******************************************************************************* +* BT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PRLL; + struct { + __IO uint8_t PRLLL; + __IO uint8_t PRLLH; + }; + __IO uint16_t PPG_PRLL; + struct { + __IO uint8_t PPG_PRLLL; + __IO uint8_t PPG_PRLLH; + }; + __IO uint16_t PCSR; + struct { + __IO uint8_t PCSRL; + __IO uint8_t PCSRH; + }; + __IO uint16_t PWM_PCSR; + struct { + __IO uint8_t PWM_PCSRL; + __IO uint8_t PWM_PCSRH; + }; + __IO uint16_t RT_PCSR; + struct { + __IO uint8_t RT_PCSRL; + __IO uint8_t RT_PCSRH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t PRLH; + struct { + __IO uint8_t PRLHL; + __IO uint8_t PRLHH; + }; + __IO uint16_t PPG_PRLH; + struct { + __IO uint8_t PPG_PRLHL; + __IO uint8_t PPG_PRLHH; + }; + __IO uint16_t DTBF; + struct { + __IO uint8_t DTBFL; + __IO uint8_t DTBFH; + }; + __IO uint16_t PWC_DTBF; + struct { + __IO uint8_t PWC_DTBFL; + __IO uint8_t PWC_DTBFH; + }; + __IO uint16_t PDUT; + struct { + __IO uint8_t PDUTL; + __IO uint8_t PDUTH; + }; + __IO uint16_t PWM_PDUT; + struct { + __IO uint8_t PWM_PDUTL; + __IO uint8_t PWM_PDUTH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + __IO uint16_t PPG_TMR; + struct { + __IO uint8_t PPG_TMRL; + __IO uint8_t PPG_TMRH; + }; + __IO uint16_t PWM_TMR; + struct { + __IO uint8_t PWM_TMRL; + __IO uint8_t PWM_TMRH; + }; + __IO uint16_t RT_TMR; + struct { + __IO uint8_t RT_TMRL; + __IO uint8_t RT_TMRH; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + __IO uint16_t PPG_TMCR; + stc_bt_ppg_tmcr_field_t PPG_TMCR_f; + struct { + __IO uint8_t PPG_TMCRL; + __IO uint8_t PPG_TMCRH; + }; + __IO uint16_t PWC_TMCR; + stc_bt_pwc_tmcr_field_t PWC_TMCR_f; + struct { + __IO uint8_t PWC_TMCRL; + __IO uint8_t PWC_TMCRH; + }; + __IO uint16_t PWM_TMCR; + stc_bt_pwm_tmcr_field_t PWM_TMCR_f; + struct { + __IO uint8_t PWM_TMCRL; + __IO uint8_t PWM_TMCRH; + }; + __IO uint16_t RT_TMCR; + stc_bt_rt_tmcr_field_t RT_TMCR_f; + struct { + __IO uint8_t RT_TMCRL; + __IO uint8_t RT_TMCRH; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_stc_field_t STC_f; + __IO uint8_t PPG_STC; + stc_bt_ppg_stc_field_t PPG_STC_f; + __IO uint8_t PWC_STC; + stc_bt_pwc_stc_field_t PWC_STC_f; + __IO uint8_t PWM_STC; + stc_bt_pwm_stc_field_t PWM_STC_f; + __IO uint8_t RT_STC; + stc_bt_rt_stc_field_t RT_STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_tmcr2_field_t TMCR2_f; + __IO uint8_t PPG_TMCR2; + stc_bt_ppg_tmcr2_field_t PPG_TMCR2_f; + __IO uint8_t PWC_TMCR2; + stc_bt_pwc_tmcr2_field_t PWC_TMCR2_f; + __IO uint8_t PWM_TMCR2; + stc_bt_pwm_tmcr2_field_t PWM_TMCR2_f; + __IO uint8_t RT_TMCR2; + stc_bt_rt_tmcr2_field_t RT_TMCR2_f; + }; +} FM_BT_TypeDef, FM4_BT_TypeDef; + +/******************************************************************************* +* BT_PPG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PRLL; + struct { + __IO uint8_t PRLLL; + __IO uint8_t PRLLH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t PRLH; + struct { + __IO uint8_t PRLHL; + __IO uint8_t PRLHH; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint16_t TMCR; + stc_bt_ppg_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint8_t STC; + stc_bt_ppg_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_ppg_tmcr2_field_t TMCR2_f; + }; +} FM_BT_PPG_TypeDef, FM4_BT_PPG_TypeDef; + +/******************************************************************************* +* BT_PWC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED8[4]; + union { + __IO uint16_t DTBF; + struct { + __IO uint8_t DTBFL; + __IO uint8_t DTBFH; + }; + }; + __IO uint8_t RESERVED9[6]; + union { + __IO uint16_t TMCR; + stc_bt_pwc_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint8_t STC; + stc_bt_pwc_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwc_tmcr2_field_t TMCR2_f; + }; +} FM_BT_PWC_TypeDef, FM4_BT_PWC_TypeDef; + +/******************************************************************************* +* BT_PWM_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PCSR; + struct { + __IO uint8_t PCSRL; + __IO uint8_t PCSRH; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t PDUT; + struct { + __IO uint8_t PDUTL; + __IO uint8_t PDUTH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint16_t TMCR; + stc_bt_pwm_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED14[2]; + union { + __IO uint8_t STC; + stc_bt_pwm_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwm_tmcr2_field_t TMCR2_f; + }; +} FM_BT_PWM_TypeDef, FM4_BT_PWM_TypeDef; + +/******************************************************************************* +* BT_RT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PCSR; + struct { + __IO uint8_t PCSRL; + __IO uint8_t PCSRH; + }; + }; + __IO uint8_t RESERVED15[6]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint16_t TMCR; + stc_bt_rt_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED17[2]; + union { + __IO uint8_t STC; + stc_bt_rt_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_rt_tmcr2_field_t TMCR2_f; + }; +} FM_BT_RT_TypeDef, FM4_BT_RT_TypeDef; + +/******************************************************************************* +* BTIOSEL03_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSEL0123; + stc_btiosel03_btsel0123_field_t BTSEL0123_f; + }; +} FM_BTIOSEL03_TypeDef, FM4_BTIOSEL03_TypeDef; + +/******************************************************************************* +* BTIOSEL47_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSEL4567; + stc_btiosel47_btsel4567_field_t BTSEL4567_f; + }; +} FM_BTIOSEL47_TypeDef, FM4_BTIOSEL47_TypeDef; + +/******************************************************************************* +* BTIOSEL8B_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSEL89AB; + stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; + }; +} FM_BTIOSEL8B_TypeDef, FM4_BTIOSEL8B_TypeDef; + +/******************************************************************************* +* BTIOSELCF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSELCDEF; + stc_btioselcf_btselcdef_field_t BTSELCDEF_f; + }; +} FM_BTIOSELCF_TypeDef, FM4_BTIOSELCF_TypeDef; + +/******************************************************************************* +* CAN_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t CTRLR; + stc_can_ctrlr_field_t CTRLR_f; + struct { + __IO uint8_t CTRLRL; + __IO uint8_t CTRLRH; + }; + }; + union { + __IO uint16_t STATR; + stc_can_statr_field_t STATR_f; + struct { + __IO uint8_t STATRL; + __IO uint8_t STATRH; + }; + }; + union { + __IO uint16_t ERRCNT; + stc_can_errcnt_field_t ERRCNT_f; + struct { + __IO uint8_t ERRCNTL; + __IO uint8_t ERRCNTH; + }; + }; + union { + __IO uint16_t BTR; + stc_can_btr_field_t BTR_f; + struct { + __IO uint8_t BTRL; + __IO uint8_t BTRH; + }; + }; + union { + __IO uint16_t INTR; + stc_can_intr_field_t INTR_f; + struct { + __IO uint8_t INTRL; + __IO uint8_t INTRH; + }; + }; + union { + __IO uint16_t TESTR; + stc_can_testr_field_t TESTR_f; + struct { + __IO uint8_t TESTRL; + __IO uint8_t TESTRH; + }; + }; + union { + __IO uint16_t BRPER; + stc_can_brper_field_t BRPER_f; + struct { + __IO uint8_t BRPERL; + __IO uint8_t BRPERH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t IF1CREQ; + stc_can_if1creq_field_t IF1CREQ_f; + struct { + __IO uint8_t IF1CREQL; + __IO uint8_t IF1CREQH; + }; + }; + union { + __IO uint16_t IF1CMSK; + stc_can_if1cmsk_field_t IF1CMSK_f; + struct { + __IO uint8_t IF1CMSKL; + __IO uint8_t IF1CMSKH; + }; + }; + union { + __IO uint32_t IF1MSK; + stc_can_if1msk_field_t IF1MSK_f; + struct { + union { + __IO uint16_t IF1MSKL; + struct { + __IO uint8_t IF1MSKLL; + __IO uint8_t IF1MSKLH; + }; + }; + union { + __IO uint16_t IF1MSKH; + struct { + __IO uint8_t IF1MSKHL; + __IO uint8_t IF1MSKHH; + }; + }; + }; + }; + union { + __IO uint32_t IF1ARB; + stc_can_if1arb_field_t IF1ARB_f; + struct { + union { + __IO uint16_t IF1ARBL; + struct { + __IO uint8_t IF1ARBLL; + __IO uint8_t IF1ARBLH; + }; + }; + union { + __IO uint16_t IF1ARBH; + struct { + __IO uint8_t IF1ARBHL; + __IO uint8_t IF1ARBHH; + }; + }; + }; + }; + union { + __IO uint16_t IF1MCTR; + stc_can_if1mctr_field_t IF1MCTR_f; + struct { + __IO uint8_t IF1MCTRL; + __IO uint8_t IF1MCTRH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + stc_can_if1dta_l_field_t IF1DTA_L_f; + struct { + union { + __IO uint16_t IF1DTA_LL; + struct { + __IO uint8_t IF1DTA_LLL; + __IO uint8_t IF1DTA_LLH; + }; + }; + union { + __IO uint16_t IF1DTA_LH; + struct { + __IO uint8_t IF1DTA_LHL; + __IO uint8_t IF1DTA_LHH; + }; + }; + }; + }; + union { + __IO uint32_t IF1DTB_L; + stc_can_if1dtb_l_field_t IF1DTB_L_f; + struct { + union { + __IO uint16_t IF1DTB_LL; + struct { + __IO uint8_t IF1DTB_LLL; + __IO uint8_t IF1DTB_LLH; + }; + }; + union { + __IO uint16_t IF1DTB_LH; + struct { + __IO uint8_t IF1DTB_LHL; + __IO uint8_t IF1DTB_LHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + stc_can_if1dta_b_field_t IF1DTA_B_f; + struct { + union { + __IO uint16_t IF1DTA_BL; + struct { + __IO uint8_t IF1DTA_BLL; + __IO uint8_t IF1DTA_BLH; + }; + }; + union { + __IO uint16_t IF1DTA_BH; + struct { + __IO uint8_t IF1DTA_BHL; + __IO uint8_t IF1DTA_BHH; + }; + }; + }; + }; + union { + __IO uint32_t IF1DTB_B; + stc_can_if1dtb_b_field_t IF1DTB_B_f; + struct { + union { + __IO uint16_t IF1DTB_BL; + struct { + __IO uint8_t IF1DTB_BLL; + __IO uint8_t IF1DTB_BLH; + }; + }; + union { + __IO uint16_t IF1DTB_BH; + struct { + __IO uint8_t IF1DTB_BHL; + __IO uint8_t IF1DTB_BHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[8]; + union { + __IO uint16_t IF2CREQ; + stc_can_if2creq_field_t IF2CREQ_f; + struct { + __IO uint8_t IF2CREQL; + __IO uint8_t IF2CREQH; + }; + }; + union { + __IO uint16_t IF2CMSK; + stc_can_if2cmsk_field_t IF2CMSK_f; + struct { + __IO uint8_t IF2CMSKL; + __IO uint8_t IF2CMSKH; + }; + }; + union { + __IO uint32_t IF2MSK; + stc_can_if2msk_field_t IF2MSK_f; + struct { + union { + __IO uint16_t IF2MSKL; + struct { + __IO uint8_t IF2MSKLL; + __IO uint8_t IF2MSKLH; + }; + }; + union { + __IO uint16_t IF2MSKH; + struct { + __IO uint8_t IF2MSKHL; + __IO uint8_t IF2MSKHH; + }; + }; + }; + }; + union { + __IO uint32_t IF2ARB; + stc_can_if2arb_field_t IF2ARB_f; + struct { + union { + __IO uint16_t IF2ARBL; + struct { + __IO uint8_t IF2ARBLL; + __IO uint8_t IF2ARBLH; + }; + }; + union { + __IO uint16_t IF2ARBH; + struct { + __IO uint8_t IF2ARBHL; + __IO uint8_t IF2ARBHH; + }; + }; + }; + }; + union { + __IO uint16_t IF2MCTR; + stc_can_if2mctr_field_t IF2MCTR_f; + struct { + __IO uint8_t IF2MCTRL; + __IO uint8_t IF2MCTRH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + stc_can_if2dta_l_field_t IF2DTA_L_f; + struct { + union { + __IO uint16_t IF2DTA_LL; + struct { + __IO uint8_t IF2DTA_LLL; + __IO uint8_t IF2DTA_LLH; + }; + }; + union { + __IO uint16_t IF2DTA_LH; + struct { + __IO uint8_t IF2DTA_LHL; + __IO uint8_t IF2DTA_LHH; + }; + }; + }; + }; + union { + __IO uint32_t IF2DTB_L; + stc_can_if2dtb_l_field_t IF2DTB_L_f; + struct { + union { + __IO uint16_t IF2DTB_LL; + struct { + __IO uint8_t IF2DTB_LLL; + __IO uint8_t IF2DTB_LLH; + }; + }; + union { + __IO uint16_t IF2DTB_LH; + struct { + __IO uint8_t IF2DTB_LHL; + __IO uint8_t IF2DTB_LHH; + }; + }; + }; + }; + __IO uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + stc_can_if2dta_b_field_t IF2DTA_B_f; + struct { + union { + __IO uint16_t IF2DTA_BL; + struct { + __IO uint8_t IF2DTA_BLL; + __IO uint8_t IF2DTA_BLH; + }; + }; + union { + __IO uint16_t IF2DTA_BH; + struct { + __IO uint8_t IF2DTA_BHL; + __IO uint8_t IF2DTA_BHH; + }; + }; + }; + }; + union { + __IO uint32_t IF2DTB_B; + stc_can_if2dtb_b_field_t IF2DTB_B_f; + struct { + union { + __IO uint16_t IF2DTB_BL; + struct { + __IO uint8_t IF2DTB_BLL; + __IO uint8_t IF2DTB_BLH; + }; + }; + union { + __IO uint16_t IF2DTB_BH; + struct { + __IO uint8_t IF2DTB_BHL; + __IO uint8_t IF2DTB_BHH; + }; + }; + }; + }; + __IO uint8_t RESERVED6[24]; + union { + __IO uint32_t TREQR; + stc_can_treqr_field_t TREQR_f; + struct { + union { + __IO uint16_t TREQRL; + struct { + __IO uint8_t TREQRLL; + __IO uint8_t TREQRLH; + }; + }; + union { + __IO uint16_t TREQRH; + struct { + __IO uint8_t TREQRHL; + __IO uint8_t TREQRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED7[12]; + union { + __IO uint32_t NEWDT; + stc_can_newdt_field_t NEWDT_f; + struct { + union { + __IO uint16_t NEWDTL; + struct { + __IO uint8_t NEWDTLL; + __IO uint8_t NEWDTLH; + }; + }; + union { + __IO uint16_t NEWDTH; + struct { + __IO uint8_t NEWDTHL; + __IO uint8_t NEWDTHH; + }; + }; + }; + }; + __IO uint8_t RESERVED8[12]; + union { + __IO uint32_t INTPND; + stc_can_intpnd_field_t INTPND_f; + struct { + union { + __IO uint16_t INTPNDL; + struct { + __IO uint8_t INTPNDLL; + __IO uint8_t INTPNDLH; + }; + }; + union { + __IO uint16_t INTPNDH; + struct { + __IO uint8_t INTPNDHL; + __IO uint8_t INTPNDHH; + }; + }; + }; + }; + __IO uint8_t RESERVED9[12]; + union { + __IO uint32_t MSGVAL; + stc_can_msgval_field_t MSGVAL_f; + struct { + union { + __IO uint16_t MSGVALL; + struct { + __IO uint8_t MSGVALLL; + __IO uint8_t MSGVALLH; + }; + }; + union { + __IO uint16_t MSGVALH; + struct { + __IO uint8_t MSGVALHL; + __IO uint8_t MSGVALHH; + }; + }; + }; + }; +} FM_CAN_TypeDef, FM4_CAN_TypeDef; + +/******************************************************************************* +* CANFD_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t CREL; + stc_canfd_crel_field_t CREL_f; + struct { + union { + __IO uint16_t CRELL; + struct { + __IO uint8_t CRELLL; + __IO uint8_t CRELLH; + }; + }; + union { + __IO uint16_t CRELH; + struct { + __IO uint8_t CRELHL; + __IO uint8_t CRELHH; + }; + }; + }; + }; + union { + __IO uint32_t ENDN; + stc_canfd_endn_field_t ENDN_f; + struct { + union { + __IO uint16_t ENDNL; + struct { + __IO uint8_t ENDNLL; + __IO uint8_t ENDNLH; + }; + }; + union { + __IO uint16_t ENDNH; + struct { + __IO uint8_t ENDNHL; + __IO uint8_t ENDNHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t FBTP; + stc_canfd_fbtp_field_t FBTP_f; + struct { + union { + __IO uint16_t FBTPL; + struct { + __IO uint8_t FBTPLL; + __IO uint8_t FBTPLH; + }; + }; + union { + __IO uint16_t FBTPH; + struct { + __IO uint8_t FBTPHL; + __IO uint8_t FBTPHH; + }; + }; + }; + }; + union { + __IO uint32_t TEST; + stc_canfd_test_field_t TEST_f; + struct { + union { + __IO uint16_t TESTL; + struct { + __IO uint8_t TESTLL; + __IO uint8_t TESTLH; + }; + }; + union { + __IO uint16_t TESTH; + struct { + __IO uint8_t TESTHL; + __IO uint8_t TESTHH; + }; + }; + }; + }; + union { + __IO uint32_t RWD; + stc_canfd_rwd_field_t RWD_f; + struct { + union { + __IO uint16_t RWDL; + struct { + __IO uint8_t RWDLL; + __IO uint8_t RWDLH; + }; + }; + union { + __IO uint16_t RWDH; + struct { + __IO uint8_t RWDHL; + __IO uint8_t RWDHH; + }; + }; + }; + }; + union { + __IO uint32_t CCCR; + stc_canfd_cccr_field_t CCCR_f; + struct { + union { + __IO uint16_t CCCRL; + struct { + __IO uint8_t CCCRLL; + __IO uint8_t CCCRLH; + }; + }; + union { + __IO uint16_t CCCRH; + struct { + __IO uint8_t CCCRHL; + __IO uint8_t CCCRHH; + }; + }; + }; + }; + union { + __IO uint32_t BTP; + stc_canfd_btp_field_t BTP_f; + struct { + union { + __IO uint16_t BTPL; + struct { + __IO uint8_t BTPLL; + __IO uint8_t BTPLH; + }; + }; + union { + __IO uint16_t BTPH; + struct { + __IO uint8_t BTPHL; + __IO uint8_t BTPHH; + }; + }; + }; + }; + union { + __IO uint32_t TSCC; + stc_canfd_tscc_field_t TSCC_f; + struct { + union { + __IO uint16_t TSCCL; + struct { + __IO uint8_t TSCCLL; + __IO uint8_t TSCCLH; + }; + }; + union { + __IO uint16_t TSCCH; + struct { + __IO uint8_t TSCCHL; + __IO uint8_t TSCCHH; + }; + }; + }; + }; + union { + __IO uint32_t TSCV; + stc_canfd_tscv_field_t TSCV_f; + struct { + union { + __IO uint16_t TSCVL; + struct { + __IO uint8_t TSCVLL; + __IO uint8_t TSCVLH; + }; + }; + union { + __IO uint16_t TSCVH; + struct { + __IO uint8_t TSCVHL; + __IO uint8_t TSCVHH; + }; + }; + }; + }; + union { + __IO uint32_t TOCC; + stc_canfd_tocc_field_t TOCC_f; + struct { + union { + __IO uint16_t TOCCL; + struct { + __IO uint8_t TOCCLL; + __IO uint8_t TOCCLH; + }; + }; + union { + __IO uint16_t TOCCH; + struct { + __IO uint8_t TOCCHL; + __IO uint8_t TOCCHH; + }; + }; + }; + }; + union { + __IO uint32_t TOCV; + stc_canfd_tocv_field_t TOCV_f; + struct { + union { + __IO uint16_t TOCVL; + struct { + __IO uint8_t TOCVLL; + __IO uint8_t TOCVLH; + }; + }; + union { + __IO uint16_t TOCVH; + struct { + __IO uint8_t TOCVHL; + __IO uint8_t TOCVHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[16]; + union { + __IO uint32_t ECR; + stc_canfd_ecr_field_t ECR_f; + struct { + union { + __IO uint16_t ECRL; + struct { + __IO uint8_t ECRLL; + __IO uint8_t ECRLH; + }; + }; + union { + __IO uint16_t ECRH; + struct { + __IO uint8_t ECRHL; + __IO uint8_t ECRHH; + }; + }; + }; + }; + union { + __IO uint32_t PSR; + stc_canfd_psr_field_t PSR_f; + struct { + union { + __IO uint16_t PSRL; + struct { + __IO uint8_t PSRLL; + __IO uint8_t PSRLH; + }; + }; + union { + __IO uint16_t PSRH; + struct { + __IO uint8_t PSRHL; + __IO uint8_t PSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[8]; + union { + __IO uint32_t IR; + stc_canfd_ir_field_t IR_f; + struct { + union { + __IO uint16_t IRL; + struct { + __IO uint8_t IRLL; + __IO uint8_t IRLH; + }; + }; + union { + __IO uint16_t IRH; + struct { + __IO uint8_t IRHL; + __IO uint8_t IRHH; + }; + }; + }; + }; + union { + __IO uint32_t IE; + stc_canfd_ie_field_t IE_f; + struct { + union { + __IO uint16_t IEL; + struct { + __IO uint8_t IELL; + __IO uint8_t IELH; + }; + }; + union { + __IO uint16_t IEH; + struct { + __IO uint8_t IEHL; + __IO uint8_t IEHH; + }; + }; + }; + }; + union { + __IO uint32_t ILS; + stc_canfd_ils_field_t ILS_f; + struct { + union { + __IO uint16_t ILSL; + struct { + __IO uint8_t ILSLL; + __IO uint8_t ILSLH; + }; + }; + union { + __IO uint16_t ILSH; + struct { + __IO uint8_t ILSHL; + __IO uint8_t ILSHH; + }; + }; + }; + }; + union { + __IO uint32_t ILE; + stc_canfd_ile_field_t ILE_f; + struct { + union { + __IO uint16_t ILEL; + struct { + __IO uint8_t ILELL; + __IO uint8_t ILELH; + }; + }; + union { + __IO uint16_t ILEH; + struct { + __IO uint8_t ILEHL; + __IO uint8_t ILEHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[32]; + union { + __IO uint32_t GFC; + stc_canfd_gfc_field_t GFC_f; + struct { + union { + __IO uint16_t GFCL; + struct { + __IO uint8_t GFCLL; + __IO uint8_t GFCLH; + }; + }; + union { + __IO uint16_t GFCH; + struct { + __IO uint8_t GFCHL; + __IO uint8_t GFCHH; + }; + }; + }; + }; + union { + __IO uint32_t SIDFC; + stc_canfd_sidfc_field_t SIDFC_f; + struct { + union { + __IO uint16_t SIDFCL; + struct { + __IO uint8_t SIDFCLL; + __IO uint8_t SIDFCLH; + }; + }; + union { + __IO uint16_t SIDFCH; + struct { + __IO uint8_t SIDFCHL; + __IO uint8_t SIDFCHH; + }; + }; + }; + }; + union { + __IO uint32_t XIDFC; + stc_canfd_xidfc_field_t XIDFC_f; + struct { + union { + __IO uint16_t XIDFCL; + struct { + __IO uint8_t XIDFCLL; + __IO uint8_t XIDFCLH; + }; + }; + union { + __IO uint16_t XIDFCH; + struct { + __IO uint8_t XIDFCHL; + __IO uint8_t XIDFCHH; + }; + }; + }; + }; + __IO uint8_t RESERVED4[4]; + union { + __IO uint32_t XIDAM; + stc_canfd_xidam_field_t XIDAM_f; + struct { + union { + __IO uint16_t XIDAML; + struct { + __IO uint8_t XIDAMLL; + __IO uint8_t XIDAMLH; + }; + }; + union { + __IO uint16_t XIDAMH; + struct { + __IO uint8_t XIDAMHL; + __IO uint8_t XIDAMHH; + }; + }; + }; + }; + union { + __IO uint32_t HPMS; + stc_canfd_hpms_field_t HPMS_f; + struct { + union { + __IO uint16_t HPMSL; + struct { + __IO uint8_t HPMSLL; + __IO uint8_t HPMSLH; + }; + }; + union { + __IO uint16_t HPMSH; + struct { + __IO uint8_t HPMSHL; + __IO uint8_t HPMSHH; + }; + }; + }; + }; + union { + __IO uint32_t NDAT1; + stc_canfd_ndat1_field_t NDAT1_f; + struct { + union { + __IO uint16_t NDAT1L; + struct { + __IO uint8_t NDAT1LL; + __IO uint8_t NDAT1LH; + }; + }; + union { + __IO uint16_t NDAT1H; + struct { + __IO uint8_t NDAT1HL; + __IO uint8_t NDAT1HH; + }; + }; + }; + }; + union { + __IO uint32_t NDAT2; + stc_canfd_ndat2_field_t NDAT2_f; + struct { + union { + __IO uint16_t NDAT2L; + struct { + __IO uint8_t NDAT2LL; + __IO uint8_t NDAT2LH; + }; + }; + union { + __IO uint16_t NDAT2H; + struct { + __IO uint8_t NDAT2HL; + __IO uint8_t NDAT2HH; + }; + }; + }; + }; + union { + __IO uint32_t RXF0C; + stc_canfd_rxf0c_field_t RXF0C_f; + struct { + union { + __IO uint16_t RXF0CL; + struct { + __IO uint8_t RXF0CLL; + __IO uint8_t RXF0CLH; + }; + }; + union { + __IO uint16_t RXF0CH; + struct { + __IO uint8_t RXF0CHL; + __IO uint8_t RXF0CHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF0S; + stc_canfd_rxf0s_field_t RXF0S_f; + struct { + union { + __IO uint16_t RXF0SL; + struct { + __IO uint8_t RXF0SLL; + __IO uint8_t RXF0SLH; + }; + }; + union { + __IO uint16_t RXF0SH; + struct { + __IO uint8_t RXF0SHL; + __IO uint8_t RXF0SHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF0A; + stc_canfd_rxf0a_field_t RXF0A_f; + struct { + union { + __IO uint16_t RXF0AL; + struct { + __IO uint8_t RXF0ALL; + __IO uint8_t RXF0ALH; + }; + }; + union { + __IO uint16_t RXF0AH; + struct { + __IO uint8_t RXF0AHL; + __IO uint8_t RXF0AHH; + }; + }; + }; + }; + union { + __IO uint32_t RXBC; + stc_canfd_rxbc_field_t RXBC_f; + struct { + union { + __IO uint16_t RXBCL; + struct { + __IO uint8_t RXBCLL; + __IO uint8_t RXBCLH; + }; + }; + union { + __IO uint16_t RXBCH; + struct { + __IO uint8_t RXBCHL; + __IO uint8_t RXBCHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF1C; + stc_canfd_rxf1c_field_t RXF1C_f; + struct { + union { + __IO uint16_t RXF1CL; + struct { + __IO uint8_t RXF1CLL; + __IO uint8_t RXF1CLH; + }; + }; + union { + __IO uint16_t RXF1CH; + struct { + __IO uint8_t RXF1CHL; + __IO uint8_t RXF1CHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF1S; + stc_canfd_rxf1s_field_t RXF1S_f; + struct { + union { + __IO uint16_t RXF1SL; + struct { + __IO uint8_t RXF1SLL; + __IO uint8_t RXF1SLH; + }; + }; + union { + __IO uint16_t RXF1SH; + struct { + __IO uint8_t RXF1SHL; + __IO uint8_t RXF1SHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF1A; + stc_canfd_rxf1a_field_t RXF1A_f; + struct { + union { + __IO uint16_t RXF1AL; + struct { + __IO uint8_t RXF1ALL; + __IO uint8_t RXF1ALH; + }; + }; + union { + __IO uint16_t RXF1AH; + struct { + __IO uint8_t RXF1AHL; + __IO uint8_t RXF1AHH; + }; + }; + }; + }; + union { + __IO uint32_t RXESC; + stc_canfd_rxesc_field_t RXESC_f; + struct { + union { + __IO uint16_t RXESCL; + struct { + __IO uint8_t RXESCLL; + __IO uint8_t RXESCLH; + }; + }; + union { + __IO uint16_t RXESCH; + struct { + __IO uint8_t RXESCHL; + __IO uint8_t RXESCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBC; + stc_canfd_txbc_field_t TXBC_f; + struct { + union { + __IO uint16_t TXBCL; + struct { + __IO uint8_t TXBCLL; + __IO uint8_t TXBCLH; + }; + }; + union { + __IO uint16_t TXBCH; + struct { + __IO uint8_t TXBCHL; + __IO uint8_t TXBCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFQS; + stc_canfd_txfqs_field_t TXFQS_f; + struct { + union { + __IO uint16_t TXFQSL; + struct { + __IO uint8_t TXFQSLL; + __IO uint8_t TXFQSLH; + }; + }; + union { + __IO uint16_t TXFQSH; + struct { + __IO uint8_t TXFQSHL; + __IO uint8_t TXFQSHH; + }; + }; + }; + }; + union { + __IO uint32_t TXESC; + stc_canfd_txesc_field_t TXESC_f; + struct { + union { + __IO uint16_t TXESCL; + struct { + __IO uint8_t TXESCLL; + __IO uint8_t TXESCLH; + }; + }; + union { + __IO uint16_t TXESCH; + struct { + __IO uint8_t TXESCHL; + __IO uint8_t TXESCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBRP; + stc_canfd_txbrp_field_t TXBRP_f; + struct { + union { + __IO uint16_t TXBRPL; + struct { + __IO uint8_t TXBRPLL; + __IO uint8_t TXBRPLH; + }; + }; + union { + __IO uint16_t TXBRPH; + struct { + __IO uint8_t TXBRPHL; + __IO uint8_t TXBRPHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBAR; + stc_canfd_txbar_field_t TXBAR_f; + struct { + union { + __IO uint16_t TXBARL; + struct { + __IO uint8_t TXBARLL; + __IO uint8_t TXBARLH; + }; + }; + union { + __IO uint16_t TXBARH; + struct { + __IO uint8_t TXBARHL; + __IO uint8_t TXBARHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBCR; + stc_canfd_txbcr_field_t TXBCR_f; + struct { + union { + __IO uint16_t TXBCRL; + struct { + __IO uint8_t TXBCRLL; + __IO uint8_t TXBCRLH; + }; + }; + union { + __IO uint16_t TXBCRH; + struct { + __IO uint8_t TXBCRHL; + __IO uint8_t TXBCRHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBTO; + stc_canfd_txbto_field_t TXBTO_f; + struct { + union { + __IO uint16_t TXBTOL; + struct { + __IO uint8_t TXBTOLL; + __IO uint8_t TXBTOLH; + }; + }; + union { + __IO uint16_t TXBTOH; + struct { + __IO uint8_t TXBTOHL; + __IO uint8_t TXBTOHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBCF; + stc_canfd_txbcf_field_t TXBCF_f; + struct { + union { + __IO uint16_t TXBCFL; + struct { + __IO uint8_t TXBCFLL; + __IO uint8_t TXBCFLH; + }; + }; + union { + __IO uint16_t TXBCFH; + struct { + __IO uint8_t TXBCFHL; + __IO uint8_t TXBCFHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBTIE; + stc_canfd_txbtie_field_t TXBTIE_f; + struct { + union { + __IO uint16_t TXBTIEL; + struct { + __IO uint8_t TXBTIELL; + __IO uint8_t TXBTIELH; + }; + }; + union { + __IO uint16_t TXBTIEH; + struct { + __IO uint8_t TXBTIEHL; + __IO uint8_t TXBTIEHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBCIE; + stc_canfd_txbcie_field_t TXBCIE_f; + struct { + union { + __IO uint16_t TXBCIEL; + struct { + __IO uint8_t TXBCIELL; + __IO uint8_t TXBCIELH; + }; + }; + union { + __IO uint16_t TXBCIEH; + struct { + __IO uint8_t TXBCIEHL; + __IO uint8_t TXBCIEHH; + }; + }; + }; + }; + __IO uint8_t RESERVED5[8]; + union { + __IO uint32_t TXEFC; + stc_canfd_txefc_field_t TXEFC_f; + struct { + union { + __IO uint16_t TXEFCL; + struct { + __IO uint8_t TXEFCLL; + __IO uint8_t TXEFCLH; + }; + }; + union { + __IO uint16_t TXEFCH; + struct { + __IO uint8_t TXEFCHL; + __IO uint8_t TXEFCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFS; + stc_canfd_txfs_field_t TXFS_f; + struct { + union { + __IO uint16_t TXFSL; + struct { + __IO uint8_t TXFSLL; + __IO uint8_t TXFSLH; + }; + }; + union { + __IO uint16_t TXFSH; + struct { + __IO uint8_t TXFSHL; + __IO uint8_t TXFSHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFA; + stc_canfd_txfa_field_t TXFA_f; + struct { + union { + __IO uint16_t TXFAL; + struct { + __IO uint8_t TXFALL; + __IO uint8_t TXFALH; + }; + }; + union { + __IO uint16_t TXFAH; + struct { + __IO uint8_t TXFAHL; + __IO uint8_t TXFAHH; + }; + }; + }; + }; + __IO uint8_t RESERVED6[260]; + union { + __IO uint8_t FDECR; + stc_canfd_fdecr_field_t FDECR_f; + }; + union { + __IO uint8_t FDESR; + stc_canfd_fdesr_field_t FDESR_f; + }; + union { + __IO uint16_t FDSEAR; + stc_canfd_fdsear_field_t FDSEAR_f; + struct { + __IO uint8_t FDSEARL; + __IO uint8_t FDSEARH; + }; + }; + __IO uint8_t RESERVED7[1]; + union { + __IO uint8_t FDESCR; + stc_canfd_fdescr_field_t FDESCR_f; + }; + union { + __IO uint16_t FDDEAR; + stc_canfd_fddear_field_t FDDEAR_f; + struct { + __IO uint8_t FDDEARL; + __IO uint8_t FDDEARH; + }; + }; + __IO uint8_t RESERVED8[8]; + union { + __IO uint16_t TSCNTR; + stc_canfd_tscntr_field_t TSCNTR_f; + struct { + __IO uint8_t TSCNTRL; + __IO uint8_t TSCNTRH; + }; + }; + union { + __IO uint16_t TSMDR; + stc_canfd_tsmdr_field_t TSMDR_f; + struct { + __IO uint8_t TSMDRL; + __IO uint8_t TSMDRH; + }; + }; + union { + __IO uint32_t TSDIVR; + stc_canfd_tsdivr_field_t TSDIVR_f; + struct { + union { + __IO uint16_t TSDIVRL; + struct { + __IO uint8_t TSDIVRLL; + __IO uint8_t TSDIVRLH; + }; + }; + union { + __IO uint16_t TSDIVRH; + struct { + __IO uint8_t TSDIVRHL; + __IO uint8_t TSDIVRHH; + }; + }; + }; + }; + union { + __IO uint16_t TSCDTR; + stc_canfd_tscdtr_field_t TSCDTR_f; + struct { + __IO uint8_t TSCDTRL; + __IO uint8_t TSCDTRH; + }; + }; + union { + __IO uint16_t TSCPCLR; + stc_canfd_tscpclr_field_t TSCPCLR_f; + struct { + __IO uint8_t TSCPCLRL; + __IO uint8_t TSCPCLRH; + }; + }; +} FM_CANFD_TypeDef, FM4_CANFD_TypeDef; + +/******************************************************************************* +* CANPRES_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t CANPRE; + stc_canpres_canpre_field_t CANPRE_f; + }; +} FM_CANPRES_TypeDef, FM4_CANPRES_TypeDef; + +/******************************************************************************* +* CLK_GATING_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t CKEN0; + stc_clk_gating_cken0_field_t CKEN0_f; + struct { + union { + __IO uint16_t CKEN0L; + struct { + __IO uint8_t CKEN0LL; + __IO uint8_t CKEN0LH; + }; + }; + union { + __IO uint16_t CKEN0H; + struct { + __IO uint8_t CKEN0HL; + __IO uint8_t CKEN0HH; + }; + }; + }; + }; + union { + __IO uint32_t MRST0; + stc_clk_gating_mrst0_field_t MRST0_f; + struct { + union { + __IO uint16_t MRST0L; + struct { + __IO uint8_t MRST0LL; + __IO uint8_t MRST0LH; + }; + }; + union { + __IO uint16_t MRST0H; + struct { + __IO uint8_t MRST0HL; + __IO uint8_t MRST0HH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[8]; + union { + __IO uint32_t CKEN1; + stc_clk_gating_cken1_field_t CKEN1_f; + struct { + union { + __IO uint16_t CKEN1L; + struct { + __IO uint8_t CKEN1LL; + __IO uint8_t CKEN1LH; + }; + }; + union { + __IO uint16_t CKEN1H; + struct { + __IO uint8_t CKEN1HL; + __IO uint8_t CKEN1HH; + }; + }; + }; + }; + union { + __IO uint32_t MRST1; + stc_clk_gating_mrst1_field_t MRST1_f; + struct { + union { + __IO uint16_t MRST1L; + struct { + __IO uint8_t MRST1LL; + __IO uint8_t MRST1LH; + }; + }; + union { + __IO uint16_t MRST1H; + struct { + __IO uint8_t MRST1HL; + __IO uint8_t MRST1HH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[8]; + union { + __IO uint32_t CKEN2; + stc_clk_gating_cken2_field_t CKEN2_f; + struct { + union { + __IO uint16_t CKEN2L; + struct { + __IO uint8_t CKEN2LL; + __IO uint8_t CKEN2LH; + }; + }; + union { + __IO uint16_t CKEN2H; + struct { + __IO uint8_t CKEN2HL; + __IO uint8_t CKEN2HH; + }; + }; + }; + }; + union { + __IO uint32_t MRST2; + stc_clk_gating_mrst2_field_t MRST2_f; + struct { + union { + __IO uint16_t MRST2L; + struct { + __IO uint8_t MRST2LL; + __IO uint8_t MRST2LH; + }; + }; + union { + __IO uint16_t MRST2H; + struct { + __IO uint8_t MRST2HL; + __IO uint8_t MRST2HH; + }; + }; + }; + }; +} FM_CLK_GATING_TypeDef, FM4_CLK_GATING_TypeDef; + +/******************************************************************************* +* CRC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t CRCCR; + stc_crc_crccr_field_t CRCCR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint32_t CRCINIT; + stc_crc_crcinit_field_t CRCINIT_f; + struct { + union { + __IO uint16_t CRCINITL; + struct { + __IO uint8_t CRCINITLL; + __IO uint8_t CRCINITLH; + }; + }; + union { + __IO uint16_t CRCINITH; + struct { + __IO uint8_t CRCINITHL; + __IO uint8_t CRCINITHH; + }; + }; + }; + }; + union { + __IO uint32_t CRCIN; + stc_crc_crcin_field_t CRCIN_f; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + union { + __IO uint32_t CRCR; + stc_crc_crcr_field_t CRCR_f; + struct { + union { + __IO uint16_t CRCRL; + struct { + __IO uint8_t CRCRLL; + __IO uint8_t CRCRLH; + }; + }; + union { + __IO uint16_t CRCRH; + struct { + __IO uint8_t CRCRHL; + __IO uint8_t CRCRHH; + }; + }; + }; + }; +} FM_CRC_TypeDef, FM4_CRC_TypeDef; + +/******************************************************************************* +* CRG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t SCM_CTL; + stc_crg_scm_ctl_field_t SCM_CTL_f; + struct { + union { + __IO uint16_t SCM_CTLL; + struct { + __IO uint8_t SCM_CTLLL; + __IO uint8_t SCM_CTLLH; + }; + }; + union { + __IO uint16_t SCM_CTLH; + struct { + __IO uint8_t SCM_CTLHL; + __IO uint8_t SCM_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t SCM_STR; + stc_crg_scm_str_field_t SCM_STR_f; + struct { + union { + __IO uint16_t SCM_STRL; + struct { + __IO uint8_t SCM_STRLL; + __IO uint8_t SCM_STRLH; + }; + }; + union { + __IO uint16_t SCM_STRH; + struct { + __IO uint8_t SCM_STRHL; + __IO uint8_t SCM_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t STB_CTL; + stc_crg_stb_ctl_field_t STB_CTL_f; + struct { + union { + __IO uint16_t STB_CTLL; + struct { + __IO uint8_t STB_CTLLL; + __IO uint8_t STB_CTLLH; + }; + }; + union { + __IO uint16_t STB_CTLH; + struct { + __IO uint8_t STB_CTLHL; + __IO uint8_t STB_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t RST_STR; + stc_crg_rst_str_field_t RST_STR_f; + struct { + union { + __IO uint16_t RST_STRL; + struct { + __IO uint8_t RST_STRLL; + __IO uint8_t RST_STRLH; + }; + }; + union { + __IO uint16_t RST_STRH; + struct { + __IO uint8_t RST_STRHL; + __IO uint8_t RST_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t BSC_PSR; + stc_crg_bsc_psr_field_t BSC_PSR_f; + struct { + union { + __IO uint16_t BSC_PSRL; + struct { + __IO uint8_t BSC_PSRLL; + __IO uint8_t BSC_PSRLH; + }; + }; + union { + __IO uint16_t BSC_PSRH; + struct { + __IO uint8_t BSC_PSRHL; + __IO uint8_t BSC_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t APBC0_PSR; + stc_crg_apbc0_psr_field_t APBC0_PSR_f; + struct { + union { + __IO uint16_t APBC0_PSRL; + struct { + __IO uint8_t APBC0_PSRLL; + __IO uint8_t APBC0_PSRLH; + }; + }; + union { + __IO uint16_t APBC0_PSRH; + struct { + __IO uint8_t APBC0_PSRHL; + __IO uint8_t APBC0_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t APBC1_PSR; + stc_crg_apbc1_psr_field_t APBC1_PSR_f; + struct { + union { + __IO uint16_t APBC1_PSRL; + struct { + __IO uint8_t APBC1_PSRLL; + __IO uint8_t APBC1_PSRLH; + }; + }; + union { + __IO uint16_t APBC1_PSRH; + struct { + __IO uint8_t APBC1_PSRHL; + __IO uint8_t APBC1_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t APBC2_PSR; + stc_crg_apbc2_psr_field_t APBC2_PSR_f; + struct { + union { + __IO uint16_t APBC2_PSRL; + struct { + __IO uint8_t APBC2_PSRLL; + __IO uint8_t APBC2_PSRLH; + }; + }; + union { + __IO uint16_t APBC2_PSRH; + struct { + __IO uint8_t APBC2_PSRHL; + __IO uint8_t APBC2_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t SWC_PSR; + stc_crg_swc_psr_field_t SWC_PSR_f; + struct { + union { + __IO uint16_t SWC_PSRL; + struct { + __IO uint8_t SWC_PSRLL; + __IO uint8_t SWC_PSRLH; + }; + }; + union { + __IO uint16_t SWC_PSRH; + struct { + __IO uint8_t SWC_PSRHL; + __IO uint8_t SWC_PSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t TTC_PSR; + stc_crg_ttc_psr_field_t TTC_PSR_f; + struct { + union { + __IO uint16_t TTC_PSRL; + struct { + __IO uint8_t TTC_PSRLL; + __IO uint8_t TTC_PSRLH; + }; + }; + union { + __IO uint16_t TTC_PSRH; + struct { + __IO uint8_t TTC_PSRHL; + __IO uint8_t TTC_PSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[4]; + union { + __IO uint32_t CSW_TMR; + stc_crg_csw_tmr_field_t CSW_TMR_f; + struct { + union { + __IO uint16_t CSW_TMRL; + struct { + __IO uint8_t CSW_TMRLL; + __IO uint8_t CSW_TMRLH; + }; + }; + union { + __IO uint16_t CSW_TMRH; + struct { + __IO uint8_t CSW_TMRHL; + __IO uint8_t CSW_TMRHH; + }; + }; + }; + }; + union { + __IO uint32_t PSW_TMR; + stc_crg_psw_tmr_field_t PSW_TMR_f; + struct { + union { + __IO uint16_t PSW_TMRL; + struct { + __IO uint8_t PSW_TMRLL; + __IO uint8_t PSW_TMRLH; + }; + }; + union { + __IO uint16_t PSW_TMRH; + struct { + __IO uint8_t PSW_TMRHL; + __IO uint8_t PSW_TMRHH; + }; + }; + }; + }; + union { + __IO uint32_t PLL_CTL1; + stc_crg_pll_ctl1_field_t PLL_CTL1_f; + struct { + union { + __IO uint16_t PLL_CTL1L; + struct { + __IO uint8_t PLL_CTL1LL; + __IO uint8_t PLL_CTL1LH; + }; + }; + union { + __IO uint16_t PLL_CTL1H; + struct { + __IO uint8_t PLL_CTL1HL; + __IO uint8_t PLL_CTL1HH; + }; + }; + }; + }; + union { + __IO uint32_t PLL_CTL2; + stc_crg_pll_ctl2_field_t PLL_CTL2_f; + struct { + union { + __IO uint16_t PLL_CTL2L; + struct { + __IO uint8_t PLL_CTL2LL; + __IO uint8_t PLL_CTL2LH; + }; + }; + union { + __IO uint16_t PLL_CTL2H; + struct { + __IO uint8_t PLL_CTL2HL; + __IO uint8_t PLL_CTL2HH; + }; + }; + }; + }; + union { + __IO uint32_t CSV_CTL; + stc_crg_csv_ctl_field_t CSV_CTL_f; + struct { + union { + __IO uint16_t CSV_CTLL; + struct { + __IO uint8_t CSV_CTLLL; + __IO uint8_t CSV_CTLLH; + }; + }; + union { + __IO uint16_t CSV_CTLH; + struct { + __IO uint8_t CSV_CTLHL; + __IO uint8_t CSV_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t CSV_STR; + stc_crg_csv_str_field_t CSV_STR_f; + struct { + union { + __IO uint16_t CSV_STRL; + struct { + __IO uint8_t CSV_STRLL; + __IO uint8_t CSV_STRLH; + }; + }; + union { + __IO uint16_t CSV_STRH; + struct { + __IO uint8_t CSV_STRHL; + __IO uint8_t CSV_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t FCSWH_CTL; + stc_crg_fcswh_ctl_field_t FCSWH_CTL_f; + struct { + union { + __IO uint16_t FCSWH_CTLL; + struct { + __IO uint8_t FCSWH_CTLLL; + __IO uint8_t FCSWH_CTLLH; + }; + }; + union { + __IO uint16_t FCSWH_CTLH; + struct { + __IO uint8_t FCSWH_CTLHL; + __IO uint8_t FCSWH_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t FCSWL_CTL; + stc_crg_fcswl_ctl_field_t FCSWL_CTL_f; + struct { + union { + __IO uint16_t FCSWL_CTLL; + struct { + __IO uint8_t FCSWL_CTLLL; + __IO uint8_t FCSWL_CTLLH; + }; + }; + union { + __IO uint16_t FCSWL_CTLH; + struct { + __IO uint8_t FCSWL_CTLHL; + __IO uint8_t FCSWL_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t FCSWD_CTL; + stc_crg_fcswd_ctl_field_t FCSWD_CTL_f; + struct { + union { + __IO uint16_t FCSWD_CTLL; + struct { + __IO uint8_t FCSWD_CTLLL; + __IO uint8_t FCSWD_CTLLH; + }; + }; + union { + __IO uint16_t FCSWD_CTLH; + struct { + __IO uint8_t FCSWD_CTLHL; + __IO uint8_t FCSWD_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t DBWDT_CTL; + stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; + struct { + union { + __IO uint16_t DBWDT_CTLL; + struct { + __IO uint8_t DBWDT_CTLLL; + __IO uint8_t DBWDT_CTLLH; + }; + }; + union { + __IO uint16_t DBWDT_CTLH; + struct { + __IO uint8_t DBWDT_CTLHL; + __IO uint8_t DBWDT_CTLHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[8]; + union { + __IO uint32_t INT_ENR; + stc_crg_int_enr_field_t INT_ENR_f; + struct { + union { + __IO uint16_t INT_ENRL; + struct { + __IO uint8_t INT_ENRLL; + __IO uint8_t INT_ENRLH; + }; + }; + union { + __IO uint16_t INT_ENRH; + struct { + __IO uint8_t INT_ENRHL; + __IO uint8_t INT_ENRHH; + }; + }; + }; + }; + union { + __IO uint32_t INT_STR; + stc_crg_int_str_field_t INT_STR_f; + struct { + union { + __IO uint16_t INT_STRL; + struct { + __IO uint8_t INT_STRLL; + __IO uint8_t INT_STRLH; + }; + }; + union { + __IO uint16_t INT_STRH; + struct { + __IO uint8_t INT_STRHL; + __IO uint8_t INT_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t INT_CLR; + stc_crg_int_clr_field_t INT_CLR_f; + struct { + union { + __IO uint16_t INT_CLRL; + struct { + __IO uint8_t INT_CLRLL; + __IO uint8_t INT_CLRLH; + }; + }; + union { + __IO uint16_t INT_CLRH; + struct { + __IO uint8_t INT_CLRHL; + __IO uint8_t INT_CLRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[8]; + union { + __IO uint32_t PLLCG_CTL; + stc_crg_pllcg_ctl_field_t PLLCG_CTL_f; + struct { + union { + __IO uint16_t PLLCG_CTLL; + struct { + __IO uint8_t PLLCG_CTLLL; + __IO uint8_t PLLCG_CTLLH; + }; + }; + union { + __IO uint16_t PLLCG_CTLH; + struct { + __IO uint8_t PLLCG_CTLHL; + __IO uint8_t PLLCG_CTLHH; + }; + }; + }; + }; +} FM_CRG_TypeDef, FM4_CRG_TypeDef; + +/******************************************************************************* +* CRTRIM_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t MCR_PSR; + stc_crtrim_mcr_psr_field_t MCR_PSR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint32_t MCR_FTRM; + stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; + struct { + union { + __IO uint16_t MCR_FTRML; + struct { + __IO uint8_t MCR_FTRMLL; + __IO uint8_t MCR_FTRMLH; + }; + }; + union { + __IO uint16_t MCR_FTRMH; + struct { + __IO uint8_t MCR_FTRMHL; + __IO uint8_t MCR_FTRMHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR_TTRM; + stc_crtrim_mcr_ttrm_field_t MCR_TTRM_f; + struct { + union { + __IO uint16_t MCR_TTRML; + struct { + __IO uint8_t MCR_TTRMLL; + __IO uint8_t MCR_TTRMLH; + }; + }; + union { + __IO uint16_t MCR_TTRMH; + struct { + __IO uint8_t MCR_TTRMHL; + __IO uint8_t MCR_TTRMHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR_RLR; + stc_crtrim_mcr_rlr_field_t MCR_RLR_f; + struct { + union { + __IO uint16_t MCR_RLRL; + struct { + __IO uint8_t MCR_RLRLL; + __IO uint8_t MCR_RLRLH; + }; + }; + union { + __IO uint16_t MCR_RLRH; + struct { + __IO uint8_t MCR_RLRHL; + __IO uint8_t MCR_RLRHH; + }; + }; + }; + }; +} FM_CRTRIM_TypeDef, FM4_CRTRIM_TypeDef; + +/******************************************************************************* +* DAC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t DACR; + stc_dac_dacr_field_t DACR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint16_t DADR; + stc_dac_dadr_field_t DADR_f; + struct { + __IO uint8_t DADRL; + __IO uint8_t DADRH; + }; + }; +} FM_DAC_TypeDef, FM4_DAC_TypeDef; + +/******************************************************************************* +* DMAC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DMACR; + stc_dmac_dmacr_field_t DMACR_f; + struct { + union { + __IO uint16_t DMACRL; + struct { + __IO uint8_t DMACRLL; + __IO uint8_t DMACRLH; + }; + }; + union { + __IO uint16_t DMACRH; + struct { + __IO uint8_t DMACRHL; + __IO uint8_t DMACRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[12]; + union { + __IO uint32_t DMACA0; + stc_dmac_dmaca0_field_t DMACA0_f; + struct { + union { + __IO uint16_t DMACA0L; + struct { + __IO uint8_t DMACA0LL; + __IO uint8_t DMACA0LH; + }; + }; + union { + __IO uint16_t DMACA0H; + struct { + __IO uint8_t DMACA0HL; + __IO uint8_t DMACA0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB0; + stc_dmac_dmacb0_field_t DMACB0_f; + struct { + union { + __IO uint16_t DMACB0L; + struct { + __IO uint8_t DMACB0LL; + __IO uint8_t DMACB0LH; + }; + }; + union { + __IO uint16_t DMACB0H; + struct { + __IO uint8_t DMACB0HL; + __IO uint8_t DMACB0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA0; + struct { + union { + __IO uint16_t DMACSA0L; + struct { + __IO uint8_t DMACSA0LL; + __IO uint8_t DMACSA0LH; + }; + }; + union { + __IO uint16_t DMACSA0H; + struct { + __IO uint8_t DMACSA0HL; + __IO uint8_t DMACSA0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA0; + struct { + union { + __IO uint16_t DMACDA0L; + struct { + __IO uint8_t DMACDA0LL; + __IO uint8_t DMACDA0LH; + }; + }; + union { + __IO uint16_t DMACDA0H; + struct { + __IO uint8_t DMACDA0HL; + __IO uint8_t DMACDA0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA1; + stc_dmac_dmaca1_field_t DMACA1_f; + struct { + union { + __IO uint16_t DMACA1L; + struct { + __IO uint8_t DMACA1LL; + __IO uint8_t DMACA1LH; + }; + }; + union { + __IO uint16_t DMACA1H; + struct { + __IO uint8_t DMACA1HL; + __IO uint8_t DMACA1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB1; + stc_dmac_dmacb1_field_t DMACB1_f; + struct { + union { + __IO uint16_t DMACB1L; + struct { + __IO uint8_t DMACB1LL; + __IO uint8_t DMACB1LH; + }; + }; + union { + __IO uint16_t DMACB1H; + struct { + __IO uint8_t DMACB1HL; + __IO uint8_t DMACB1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA1; + struct { + union { + __IO uint16_t DMACSA1L; + struct { + __IO uint8_t DMACSA1LL; + __IO uint8_t DMACSA1LH; + }; + }; + union { + __IO uint16_t DMACSA1H; + struct { + __IO uint8_t DMACSA1HL; + __IO uint8_t DMACSA1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA1; + struct { + union { + __IO uint16_t DMACDA1L; + struct { + __IO uint8_t DMACDA1LL; + __IO uint8_t DMACDA1LH; + }; + }; + union { + __IO uint16_t DMACDA1H; + struct { + __IO uint8_t DMACDA1HL; + __IO uint8_t DMACDA1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA2; + stc_dmac_dmaca2_field_t DMACA2_f; + struct { + union { + __IO uint16_t DMACA2L; + struct { + __IO uint8_t DMACA2LL; + __IO uint8_t DMACA2LH; + }; + }; + union { + __IO uint16_t DMACA2H; + struct { + __IO uint8_t DMACA2HL; + __IO uint8_t DMACA2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB2; + stc_dmac_dmacb2_field_t DMACB2_f; + struct { + union { + __IO uint16_t DMACB2L; + struct { + __IO uint8_t DMACB2LL; + __IO uint8_t DMACB2LH; + }; + }; + union { + __IO uint16_t DMACB2H; + struct { + __IO uint8_t DMACB2HL; + __IO uint8_t DMACB2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA2; + struct { + union { + __IO uint16_t DMACSA2L; + struct { + __IO uint8_t DMACSA2LL; + __IO uint8_t DMACSA2LH; + }; + }; + union { + __IO uint16_t DMACSA2H; + struct { + __IO uint8_t DMACSA2HL; + __IO uint8_t DMACSA2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA2; + struct { + union { + __IO uint16_t DMACDA2L; + struct { + __IO uint8_t DMACDA2LL; + __IO uint8_t DMACDA2LH; + }; + }; + union { + __IO uint16_t DMACDA2H; + struct { + __IO uint8_t DMACDA2HL; + __IO uint8_t DMACDA2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA3; + stc_dmac_dmaca3_field_t DMACA3_f; + struct { + union { + __IO uint16_t DMACA3L; + struct { + __IO uint8_t DMACA3LL; + __IO uint8_t DMACA3LH; + }; + }; + union { + __IO uint16_t DMACA3H; + struct { + __IO uint8_t DMACA3HL; + __IO uint8_t DMACA3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB3; + stc_dmac_dmacb3_field_t DMACB3_f; + struct { + union { + __IO uint16_t DMACB3L; + struct { + __IO uint8_t DMACB3LL; + __IO uint8_t DMACB3LH; + }; + }; + union { + __IO uint16_t DMACB3H; + struct { + __IO uint8_t DMACB3HL; + __IO uint8_t DMACB3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA3; + struct { + union { + __IO uint16_t DMACSA3L; + struct { + __IO uint8_t DMACSA3LL; + __IO uint8_t DMACSA3LH; + }; + }; + union { + __IO uint16_t DMACSA3H; + struct { + __IO uint8_t DMACSA3HL; + __IO uint8_t DMACSA3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA3; + struct { + union { + __IO uint16_t DMACDA3L; + struct { + __IO uint8_t DMACDA3LL; + __IO uint8_t DMACDA3LH; + }; + }; + union { + __IO uint16_t DMACDA3H; + struct { + __IO uint8_t DMACDA3HL; + __IO uint8_t DMACDA3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA4; + stc_dmac_dmaca4_field_t DMACA4_f; + struct { + union { + __IO uint16_t DMACA4L; + struct { + __IO uint8_t DMACA4LL; + __IO uint8_t DMACA4LH; + }; + }; + union { + __IO uint16_t DMACA4H; + struct { + __IO uint8_t DMACA4HL; + __IO uint8_t DMACA4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB4; + stc_dmac_dmacb4_field_t DMACB4_f; + struct { + union { + __IO uint16_t DMACB4L; + struct { + __IO uint8_t DMACB4LL; + __IO uint8_t DMACB4LH; + }; + }; + union { + __IO uint16_t DMACB4H; + struct { + __IO uint8_t DMACB4HL; + __IO uint8_t DMACB4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA4; + struct { + union { + __IO uint16_t DMACSA4L; + struct { + __IO uint8_t DMACSA4LL; + __IO uint8_t DMACSA4LH; + }; + }; + union { + __IO uint16_t DMACSA4H; + struct { + __IO uint8_t DMACSA4HL; + __IO uint8_t DMACSA4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA4; + struct { + union { + __IO uint16_t DMACDA4L; + struct { + __IO uint8_t DMACDA4LL; + __IO uint8_t DMACDA4LH; + }; + }; + union { + __IO uint16_t DMACDA4H; + struct { + __IO uint8_t DMACDA4HL; + __IO uint8_t DMACDA4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA5; + stc_dmac_dmaca5_field_t DMACA5_f; + struct { + union { + __IO uint16_t DMACA5L; + struct { + __IO uint8_t DMACA5LL; + __IO uint8_t DMACA5LH; + }; + }; + union { + __IO uint16_t DMACA5H; + struct { + __IO uint8_t DMACA5HL; + __IO uint8_t DMACA5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB5; + stc_dmac_dmacb5_field_t DMACB5_f; + struct { + union { + __IO uint16_t DMACB5L; + struct { + __IO uint8_t DMACB5LL; + __IO uint8_t DMACB5LH; + }; + }; + union { + __IO uint16_t DMACB5H; + struct { + __IO uint8_t DMACB5HL; + __IO uint8_t DMACB5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA5; + struct { + union { + __IO uint16_t DMACSA5L; + struct { + __IO uint8_t DMACSA5LL; + __IO uint8_t DMACSA5LH; + }; + }; + union { + __IO uint16_t DMACSA5H; + struct { + __IO uint8_t DMACSA5HL; + __IO uint8_t DMACSA5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA5; + struct { + union { + __IO uint16_t DMACDA5L; + struct { + __IO uint8_t DMACDA5LL; + __IO uint8_t DMACDA5LH; + }; + }; + union { + __IO uint16_t DMACDA5H; + struct { + __IO uint8_t DMACDA5HL; + __IO uint8_t DMACDA5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA6; + stc_dmac_dmaca6_field_t DMACA6_f; + struct { + union { + __IO uint16_t DMACA6L; + struct { + __IO uint8_t DMACA6LL; + __IO uint8_t DMACA6LH; + }; + }; + union { + __IO uint16_t DMACA6H; + struct { + __IO uint8_t DMACA6HL; + __IO uint8_t DMACA6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB6; + stc_dmac_dmacb6_field_t DMACB6_f; + struct { + union { + __IO uint16_t DMACB6L; + struct { + __IO uint8_t DMACB6LL; + __IO uint8_t DMACB6LH; + }; + }; + union { + __IO uint16_t DMACB6H; + struct { + __IO uint8_t DMACB6HL; + __IO uint8_t DMACB6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA6; + struct { + union { + __IO uint16_t DMACSA6L; + struct { + __IO uint8_t DMACSA6LL; + __IO uint8_t DMACSA6LH; + }; + }; + union { + __IO uint16_t DMACSA6H; + struct { + __IO uint8_t DMACSA6HL; + __IO uint8_t DMACSA6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA6; + struct { + union { + __IO uint16_t DMACDA6L; + struct { + __IO uint8_t DMACDA6LL; + __IO uint8_t DMACDA6LH; + }; + }; + union { + __IO uint16_t DMACDA6H; + struct { + __IO uint8_t DMACDA6HL; + __IO uint8_t DMACDA6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA7; + stc_dmac_dmaca7_field_t DMACA7_f; + struct { + union { + __IO uint16_t DMACA7L; + struct { + __IO uint8_t DMACA7LL; + __IO uint8_t DMACA7LH; + }; + }; + union { + __IO uint16_t DMACA7H; + struct { + __IO uint8_t DMACA7HL; + __IO uint8_t DMACA7HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB7; + stc_dmac_dmacb7_field_t DMACB7_f; + struct { + union { + __IO uint16_t DMACB7L; + struct { + __IO uint8_t DMACB7LL; + __IO uint8_t DMACB7LH; + }; + }; + union { + __IO uint16_t DMACB7H; + struct { + __IO uint8_t DMACB7HL; + __IO uint8_t DMACB7HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA7; + struct { + union { + __IO uint16_t DMACSA7L; + struct { + __IO uint8_t DMACSA7LL; + __IO uint8_t DMACSA7LH; + }; + }; + union { + __IO uint16_t DMACSA7H; + struct { + __IO uint8_t DMACSA7HL; + __IO uint8_t DMACSA7HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA7; + struct { + union { + __IO uint16_t DMACDA7L; + struct { + __IO uint8_t DMACDA7LL; + __IO uint8_t DMACDA7LH; + }; + }; + union { + __IO uint16_t DMACDA7H; + struct { + __IO uint8_t DMACDA7HL; + __IO uint8_t DMACDA7HH; + }; + }; + }; + }; +} FM_DMAC_TypeDef, FM4_DMAC_TypeDef; + +/******************************************************************************* +* DS_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[4]; + union { + __IO uint8_t RCK_CTL; + stc_ds_rck_ctl_field_t RCK_CTL_f; + }; + __IO uint8_t RESERVED1[1787]; + union { + __IO uint8_t PMD_CTL; + stc_ds_pmd_ctl_field_t PMD_CTL_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint8_t WRFSR; + stc_ds_wrfsr_field_t WRFSR_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint16_t WIFSR; + stc_ds_wifsr_field_t WIFSR_f; + struct { + __IO uint8_t WIFSRL; + __IO uint8_t WIFSRH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t WIER; + stc_ds_wier_field_t WIER_f; + struct { + __IO uint8_t WIERL; + __IO uint8_t WIERH; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint8_t WILVR; + stc_ds_wilvr_field_t WILVR_f; + }; + __IO uint8_t RESERVED6[3]; + union { + __IO uint8_t DSRAMR; + stc_ds_dsramr_field_t DSRAMR_f; + }; + __IO uint8_t RESERVED7[235]; + __IO uint8_t BUR01; + __IO uint8_t BUR02; + __IO uint8_t BUR03; + __IO uint8_t BUR04; + __IO uint8_t BUR05; + __IO uint8_t BUR06; + __IO uint8_t BUR07; + __IO uint8_t BUR08; + __IO uint8_t BUR09; + __IO uint8_t BUR10; + __IO uint8_t BUR11; + __IO uint8_t BUR12; + __IO uint8_t BUR13; + __IO uint8_t BUR14; + __IO uint8_t BUR15; + __IO uint8_t BUR16; +} FM_DS_TypeDef, FM4_DS_TypeDef; + +/******************************************************************************* +* DSTC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DESTP; + struct { + union { + __IO uint16_t DESTPL; + struct { + __IO uint8_t DESTPLL; + __IO uint8_t DESTPLH; + }; + }; + union { + __IO uint16_t DESTPH; + struct { + __IO uint8_t DESTPHL; + __IO uint8_t DESTPHH; + }; + }; + }; + }; + union { + __IO uint32_t HWDESP; + stc_dstc_hwdesp_field_t HWDESP_f; + struct { + union { + __IO uint16_t HWDESPL; + struct { + __IO uint8_t HWDESPLL; + __IO uint8_t HWDESPLH; + }; + }; + union { + __IO uint16_t HWDESPH; + struct { + __IO uint8_t HWDESPHL; + __IO uint8_t HWDESPHH; + }; + }; + }; + }; + __IO uint8_t CMD; + union { + __IO uint8_t CFG; + stc_dstc_cfg_field_t CFG_f; + }; + union { + __IO uint16_t SWTR; + stc_dstc_swtr_field_t SWTR_f; + struct { + __IO uint8_t SWTRL; + __IO uint8_t SWTRH; + }; + }; + union { + __IO uint32_t MONERS; + stc_dstc_moners_field_t MONERS_f; + struct { + union { + __IO uint16_t MONERSL; + struct { + __IO uint8_t MONERSLL; + __IO uint8_t MONERSLH; + }; + }; + union { + __IO uint16_t MONERSH; + struct { + __IO uint8_t MONERSHL; + __IO uint8_t MONERSHH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB0; + struct { + union { + __IO uint16_t DREQENB0L; + struct { + __IO uint8_t DREQENB0LL; + __IO uint8_t DREQENB0LH; + }; + }; + union { + __IO uint16_t DREQENB0H; + struct { + __IO uint8_t DREQENB0HL; + __IO uint8_t DREQENB0HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB1; + struct { + union { + __IO uint16_t DREQENB1L; + struct { + __IO uint8_t DREQENB1LL; + __IO uint8_t DREQENB1LH; + }; + }; + union { + __IO uint16_t DREQENB1H; + struct { + __IO uint8_t DREQENB1HL; + __IO uint8_t DREQENB1HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB2; + struct { + union { + __IO uint16_t DREQENB2L; + struct { + __IO uint8_t DREQENB2LL; + __IO uint8_t DREQENB2LH; + }; + }; + union { + __IO uint16_t DREQENB2H; + struct { + __IO uint8_t DREQENB2HL; + __IO uint8_t DREQENB2HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB3; + struct { + union { + __IO uint16_t DREQENB3L; + struct { + __IO uint8_t DREQENB3LL; + __IO uint8_t DREQENB3LH; + }; + }; + union { + __IO uint16_t DREQENB3H; + struct { + __IO uint8_t DREQENB3HL; + __IO uint8_t DREQENB3HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB4; + struct { + union { + __IO uint16_t DREQENB4L; + struct { + __IO uint8_t DREQENB4LL; + __IO uint8_t DREQENB4LH; + }; + }; + union { + __IO uint16_t DREQENB4H; + struct { + __IO uint8_t DREQENB4HL; + __IO uint8_t DREQENB4HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB5; + struct { + union { + __IO uint16_t DREQENB5L; + struct { + __IO uint8_t DREQENB5LL; + __IO uint8_t DREQENB5LH; + }; + }; + union { + __IO uint16_t DREQENB5H; + struct { + __IO uint8_t DREQENB5HL; + __IO uint8_t DREQENB5HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB6; + struct { + union { + __IO uint16_t DREQENB6L; + struct { + __IO uint8_t DREQENB6LL; + __IO uint8_t DREQENB6LH; + }; + }; + union { + __IO uint16_t DREQENB6H; + struct { + __IO uint8_t DREQENB6HL; + __IO uint8_t DREQENB6HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB7; + struct { + union { + __IO uint16_t DREQENB7L; + struct { + __IO uint8_t DREQENB7LL; + __IO uint8_t DREQENB7LH; + }; + }; + union { + __IO uint16_t DREQENB7H; + struct { + __IO uint8_t DREQENB7HL; + __IO uint8_t DREQENB7HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT0; + struct { + union { + __IO uint16_t HWINT0L; + struct { + __IO uint8_t HWINT0LL; + __IO uint8_t HWINT0LH; + }; + }; + union { + __IO uint16_t HWINT0H; + struct { + __IO uint8_t HWINT0HL; + __IO uint8_t HWINT0HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT1; + struct { + union { + __IO uint16_t HWINT1L; + struct { + __IO uint8_t HWINT1LL; + __IO uint8_t HWINT1LH; + }; + }; + union { + __IO uint16_t HWINT1H; + struct { + __IO uint8_t HWINT1HL; + __IO uint8_t HWINT1HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT2; + struct { + union { + __IO uint16_t HWINT2L; + struct { + __IO uint8_t HWINT2LL; + __IO uint8_t HWINT2LH; + }; + }; + union { + __IO uint16_t HWINT2H; + struct { + __IO uint8_t HWINT2HL; + __IO uint8_t HWINT2HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT3; + struct { + union { + __IO uint16_t HWINT3L; + struct { + __IO uint8_t HWINT3LL; + __IO uint8_t HWINT3LH; + }; + }; + union { + __IO uint16_t HWINT3H; + struct { + __IO uint8_t HWINT3HL; + __IO uint8_t HWINT3HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT4; + struct { + union { + __IO uint16_t HWINT4L; + struct { + __IO uint8_t HWINT4LL; + __IO uint8_t HWINT4LH; + }; + }; + union { + __IO uint16_t HWINT4H; + struct { + __IO uint8_t HWINT4HL; + __IO uint8_t HWINT4HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT5; + struct { + union { + __IO uint16_t HWINT5L; + struct { + __IO uint8_t HWINT5LL; + __IO uint8_t HWINT5LH; + }; + }; + union { + __IO uint16_t HWINT5H; + struct { + __IO uint8_t HWINT5HL; + __IO uint8_t HWINT5HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT6; + struct { + union { + __IO uint16_t HWINT6L; + struct { + __IO uint8_t HWINT6LL; + __IO uint8_t HWINT6LH; + }; + }; + union { + __IO uint16_t HWINT6H; + struct { + __IO uint8_t HWINT6HL; + __IO uint8_t HWINT6HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT7; + struct { + union { + __IO uint16_t HWINT7L; + struct { + __IO uint8_t HWINT7LL; + __IO uint8_t HWINT7LH; + }; + }; + union { + __IO uint16_t HWINT7H; + struct { + __IO uint8_t HWINT7HL; + __IO uint8_t HWINT7HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR0; + struct { + union { + __IO uint16_t HWINTCLR0L; + struct { + __IO uint8_t HWINTCLR0LL; + __IO uint8_t HWINTCLR0LH; + }; + }; + union { + __IO uint16_t HWINTCLR0H; + struct { + __IO uint8_t HWINTCLR0HL; + __IO uint8_t HWINTCLR0HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR1; + struct { + union { + __IO uint16_t HWINTCLR1L; + struct { + __IO uint8_t HWINTCLR1LL; + __IO uint8_t HWINTCLR1LH; + }; + }; + union { + __IO uint16_t HWINTCLR1H; + struct { + __IO uint8_t HWINTCLR1HL; + __IO uint8_t HWINTCLR1HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR2; + struct { + union { + __IO uint16_t HWINTCLR2L; + struct { + __IO uint8_t HWINTCLR2LL; + __IO uint8_t HWINTCLR2LH; + }; + }; + union { + __IO uint16_t HWINTCLR2H; + struct { + __IO uint8_t HWINTCLR2HL; + __IO uint8_t HWINTCLR2HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR3; + struct { + union { + __IO uint16_t HWINTCLR3L; + struct { + __IO uint8_t HWINTCLR3LL; + __IO uint8_t HWINTCLR3LH; + }; + }; + union { + __IO uint16_t HWINTCLR3H; + struct { + __IO uint8_t HWINTCLR3HL; + __IO uint8_t HWINTCLR3HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR4; + struct { + union { + __IO uint16_t HWINTCLR4L; + struct { + __IO uint8_t HWINTCLR4LL; + __IO uint8_t HWINTCLR4LH; + }; + }; + union { + __IO uint16_t HWINTCLR4H; + struct { + __IO uint8_t HWINTCLR4HL; + __IO uint8_t HWINTCLR4HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR5; + struct { + union { + __IO uint16_t HWINTCLR5L; + struct { + __IO uint8_t HWINTCLR5LL; + __IO uint8_t HWINTCLR5LH; + }; + }; + union { + __IO uint16_t HWINTCLR5H; + struct { + __IO uint8_t HWINTCLR5HL; + __IO uint8_t HWINTCLR5HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR6; + struct { + union { + __IO uint16_t HWINTCLR6L; + struct { + __IO uint8_t HWINTCLR6LL; + __IO uint8_t HWINTCLR6LH; + }; + }; + union { + __IO uint16_t HWINTCLR6H; + struct { + __IO uint8_t HWINTCLR6HL; + __IO uint8_t HWINTCLR6HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR7; + struct { + union { + __IO uint16_t HWINTCLR7L; + struct { + __IO uint8_t HWINTCLR7LL; + __IO uint8_t HWINTCLR7LH; + }; + }; + union { + __IO uint16_t HWINTCLR7H; + struct { + __IO uint8_t HWINTCLR7HL; + __IO uint8_t HWINTCLR7HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK0; + struct { + union { + __IO uint16_t DQMSK0L; + struct { + __IO uint8_t DQMSK0LL; + __IO uint8_t DQMSK0LH; + }; + }; + union { + __IO uint16_t DQMSK0H; + struct { + __IO uint8_t DQMSK0HL; + __IO uint8_t DQMSK0HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK1; + struct { + union { + __IO uint16_t DQMSK1L; + struct { + __IO uint8_t DQMSK1LL; + __IO uint8_t DQMSK1LH; + }; + }; + union { + __IO uint16_t DQMSK1H; + struct { + __IO uint8_t DQMSK1HL; + __IO uint8_t DQMSK1HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK2; + struct { + union { + __IO uint16_t DQMSK2L; + struct { + __IO uint8_t DQMSK2LL; + __IO uint8_t DQMSK2LH; + }; + }; + union { + __IO uint16_t DQMSK2H; + struct { + __IO uint8_t DQMSK2HL; + __IO uint8_t DQMSK2HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK3; + struct { + union { + __IO uint16_t DQMSK3L; + struct { + __IO uint8_t DQMSK3LL; + __IO uint8_t DQMSK3LH; + }; + }; + union { + __IO uint16_t DQMSK3H; + struct { + __IO uint8_t DQMSK3HL; + __IO uint8_t DQMSK3HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK4; + struct { + union { + __IO uint16_t DQMSK4L; + struct { + __IO uint8_t DQMSK4LL; + __IO uint8_t DQMSK4LH; + }; + }; + union { + __IO uint16_t DQMSK4H; + struct { + __IO uint8_t DQMSK4HL; + __IO uint8_t DQMSK4HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK5; + struct { + union { + __IO uint16_t DQMSK5L; + struct { + __IO uint8_t DQMSK5LL; + __IO uint8_t DQMSK5LH; + }; + }; + union { + __IO uint16_t DQMSK5H; + struct { + __IO uint8_t DQMSK5HL; + __IO uint8_t DQMSK5HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK6; + struct { + union { + __IO uint16_t DQMSK6L; + struct { + __IO uint8_t DQMSK6LL; + __IO uint8_t DQMSK6LH; + }; + }; + union { + __IO uint16_t DQMSK6H; + struct { + __IO uint8_t DQMSK6HL; + __IO uint8_t DQMSK6HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK7; + struct { + union { + __IO uint16_t DQMSK7L; + struct { + __IO uint8_t DQMSK7LL; + __IO uint8_t DQMSK7LH; + }; + }; + union { + __IO uint16_t DQMSK7H; + struct { + __IO uint8_t DQMSK7HL; + __IO uint8_t DQMSK7HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR0; + struct { + union { + __IO uint16_t DQMSKCLR0L; + struct { + __IO uint8_t DQMSKCLR0LL; + __IO uint8_t DQMSKCLR0LH; + }; + }; + union { + __IO uint16_t DQMSKCLR0H; + struct { + __IO uint8_t DQMSKCLR0HL; + __IO uint8_t DQMSKCLR0HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR1; + struct { + union { + __IO uint16_t DQMSKCLR1L; + struct { + __IO uint8_t DQMSKCLR1LL; + __IO uint8_t DQMSKCLR1LH; + }; + }; + union { + __IO uint16_t DQMSKCLR1H; + struct { + __IO uint8_t DQMSKCLR1HL; + __IO uint8_t DQMSKCLR1HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR2; + struct { + union { + __IO uint16_t DQMSKCLR2L; + struct { + __IO uint8_t DQMSKCLR2LL; + __IO uint8_t DQMSKCLR2LH; + }; + }; + union { + __IO uint16_t DQMSKCLR2H; + struct { + __IO uint8_t DQMSKCLR2HL; + __IO uint8_t DQMSKCLR2HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR3; + struct { + union { + __IO uint16_t DQMSKCLR3L; + struct { + __IO uint8_t DQMSKCLR3LL; + __IO uint8_t DQMSKCLR3LH; + }; + }; + union { + __IO uint16_t DQMSKCLR3H; + struct { + __IO uint8_t DQMSKCLR3HL; + __IO uint8_t DQMSKCLR3HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR4; + struct { + union { + __IO uint16_t DQMSKCLR4L; + struct { + __IO uint8_t DQMSKCLR4LL; + __IO uint8_t DQMSKCLR4LH; + }; + }; + union { + __IO uint16_t DQMSKCLR4H; + struct { + __IO uint8_t DQMSKCLR4HL; + __IO uint8_t DQMSKCLR4HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR5; + struct { + union { + __IO uint16_t DQMSKCLR5L; + struct { + __IO uint8_t DQMSKCLR5LL; + __IO uint8_t DQMSKCLR5LH; + }; + }; + union { + __IO uint16_t DQMSKCLR5H; + struct { + __IO uint8_t DQMSKCLR5HL; + __IO uint8_t DQMSKCLR5HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR6; + struct { + union { + __IO uint16_t DQMSKCLR6L; + struct { + __IO uint8_t DQMSKCLR6LL; + __IO uint8_t DQMSKCLR6LH; + }; + }; + union { + __IO uint16_t DQMSKCLR6H; + struct { + __IO uint8_t DQMSKCLR6HL; + __IO uint8_t DQMSKCLR6HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR7; + struct { + union { + __IO uint16_t DQMSKCLR7L; + struct { + __IO uint8_t DQMSKCLR7LL; + __IO uint8_t DQMSKCLR7LH; + }; + }; + union { + __IO uint16_t DQMSKCLR7H; + struct { + __IO uint8_t DQMSKCLR7HL; + __IO uint8_t DQMSKCLR7HH; + }; + }; + }; + }; +} FM_DSTC_TypeDef, FM4_DSTC_TypeDef; + +/******************************************************************************* +* DT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t TIMER1LOAD; + struct { + union { + __IO uint16_t TIMER1LOADL; + struct { + __IO uint8_t TIMER1LOADLL; + __IO uint8_t TIMER1LOADLH; + }; + }; + union { + __IO uint16_t TIMER1LOADH; + struct { + __IO uint8_t TIMER1LOADHL; + __IO uint8_t TIMER1LOADHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1VALUE; + struct { + union { + __IO uint16_t TIMER1VALUEL; + struct { + __IO uint8_t TIMER1VALUELL; + __IO uint8_t TIMER1VALUELH; + }; + }; + union { + __IO uint16_t TIMER1VALUEH; + struct { + __IO uint8_t TIMER1VALUEHL; + __IO uint8_t TIMER1VALUEHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1CONTROL; + stc_dt_timer1control_field_t TIMER1CONTROL_f; + struct { + union { + __IO uint16_t TIMER1CONTROLL; + struct { + __IO uint8_t TIMER1CONTROLLL; + __IO uint8_t TIMER1CONTROLLH; + }; + }; + union { + __IO uint16_t TIMER1CONTROLH; + struct { + __IO uint8_t TIMER1CONTROLHL; + __IO uint8_t TIMER1CONTROLHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1INTCLR; + struct { + union { + __IO uint16_t TIMER1INTCLRL; + struct { + __IO uint8_t TIMER1INTCLRLL; + __IO uint8_t TIMER1INTCLRLH; + }; + }; + union { + __IO uint16_t TIMER1INTCLRH; + struct { + __IO uint8_t TIMER1INTCLRHL; + __IO uint8_t TIMER1INTCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1RIS; + stc_dt_timer1ris_field_t TIMER1RIS_f; + struct { + union { + __IO uint16_t TIMER1RISL; + struct { + __IO uint8_t TIMER1RISLL; + __IO uint8_t TIMER1RISLH; + }; + }; + union { + __IO uint16_t TIMER1RISH; + struct { + __IO uint8_t TIMER1RISHL; + __IO uint8_t TIMER1RISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1MIS; + stc_dt_timer1mis_field_t TIMER1MIS_f; + struct { + union { + __IO uint16_t TIMER1MISL; + struct { + __IO uint8_t TIMER1MISLL; + __IO uint8_t TIMER1MISLH; + }; + }; + union { + __IO uint16_t TIMER1MISH; + struct { + __IO uint8_t TIMER1MISHL; + __IO uint8_t TIMER1MISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1BGLOAD; + struct { + union { + __IO uint16_t TIMER1BGLOADL; + struct { + __IO uint8_t TIMER1BGLOADLL; + __IO uint8_t TIMER1BGLOADLH; + }; + }; + union { + __IO uint16_t TIMER1BGLOADH; + struct { + __IO uint8_t TIMER1BGLOADHL; + __IO uint8_t TIMER1BGLOADHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t TIMER2LOAD; + struct { + union { + __IO uint16_t TIMER2LOADL; + struct { + __IO uint8_t TIMER2LOADLL; + __IO uint8_t TIMER2LOADLH; + }; + }; + union { + __IO uint16_t TIMER2LOADH; + struct { + __IO uint8_t TIMER2LOADHL; + __IO uint8_t TIMER2LOADHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2VALUE; + struct { + union { + __IO uint16_t TIMER2VALUEL; + struct { + __IO uint8_t TIMER2VALUELL; + __IO uint8_t TIMER2VALUELH; + }; + }; + union { + __IO uint16_t TIMER2VALUEH; + struct { + __IO uint8_t TIMER2VALUEHL; + __IO uint8_t TIMER2VALUEHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2CONTROL; + stc_dt_timer2control_field_t TIMER2CONTROL_f; + struct { + union { + __IO uint16_t TIMER2CONTROLL; + struct { + __IO uint8_t TIMER2CONTROLLL; + __IO uint8_t TIMER2CONTROLLH; + }; + }; + union { + __IO uint16_t TIMER2CONTROLH; + struct { + __IO uint8_t TIMER2CONTROLHL; + __IO uint8_t TIMER2CONTROLHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2INTCLR; + struct { + union { + __IO uint16_t TIMER2INTCLRL; + struct { + __IO uint8_t TIMER2INTCLRLL; + __IO uint8_t TIMER2INTCLRLH; + }; + }; + union { + __IO uint16_t TIMER2INTCLRH; + struct { + __IO uint8_t TIMER2INTCLRHL; + __IO uint8_t TIMER2INTCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2RIS; + stc_dt_timer2ris_field_t TIMER2RIS_f; + struct { + union { + __IO uint16_t TIMER2RISL; + struct { + __IO uint8_t TIMER2RISLL; + __IO uint8_t TIMER2RISLH; + }; + }; + union { + __IO uint16_t TIMER2RISH; + struct { + __IO uint8_t TIMER2RISHL; + __IO uint8_t TIMER2RISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2MIS; + stc_dt_timer2mis_field_t TIMER2MIS_f; + struct { + union { + __IO uint16_t TIMER2MISL; + struct { + __IO uint8_t TIMER2MISLL; + __IO uint8_t TIMER2MISLH; + }; + }; + union { + __IO uint16_t TIMER2MISH; + struct { + __IO uint8_t TIMER2MISHL; + __IO uint8_t TIMER2MISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2BGLOAD; + struct { + union { + __IO uint16_t TIMER2BGLOADL; + struct { + __IO uint8_t TIMER2BGLOADLL; + __IO uint8_t TIMER2BGLOADLH; + }; + }; + union { + __IO uint16_t TIMER2BGLOADH; + struct { + __IO uint8_t TIMER2BGLOADHL; + __IO uint8_t TIMER2BGLOADHH; + }; + }; + }; + }; +} FM_DT_TypeDef, FM4_DT_TypeDef; + +/******************************************************************************* +* DUALFLASH_IF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DFASZR; + stc_dualflash_if_dfaszr_field_t DFASZR_f; + struct { + union { + __IO uint16_t DFASZRL; + struct { + __IO uint8_t DFASZRLL; + __IO uint8_t DFASZRLH; + }; + }; + union { + __IO uint16_t DFASZRH; + struct { + __IO uint8_t DFASZRHL; + __IO uint8_t DFASZRHH; + }; + }; + }; + }; + union { + __IO uint32_t DFRWTR; + stc_dualflash_if_dfrwtr_field_t DFRWTR_f; + struct { + union { + __IO uint16_t DFRWTRL; + struct { + __IO uint8_t DFRWTRLL; + __IO uint8_t DFRWTRLH; + }; + }; + union { + __IO uint16_t DFRWTRH; + struct { + __IO uint8_t DFRWTRHL; + __IO uint8_t DFRWTRHH; + }; + }; + }; + }; + union { + __IO uint32_t DFSTR; + stc_dualflash_if_dfstr_field_t DFSTR_f; + struct { + union { + __IO uint16_t DFSTRL; + struct { + __IO uint8_t DFSTRLL; + __IO uint8_t DFSTRLH; + }; + }; + union { + __IO uint16_t DFSTRH; + struct { + __IO uint8_t DFSTRHL; + __IO uint8_t DFSTRHH; + }; + }; + }; + }; +} FM_DUALFLASH_IF_TypeDef, FM4_DUALFLASH_IF_TypeDef; + +/******************************************************************************* +* ECC_CAPTURE_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t FERRAD; + stc_ecc_capture_ferrad_field_t FERRAD_f; + struct { + union { + __IO uint16_t FERRADL; + struct { + __IO uint8_t FERRADLL; + __IO uint8_t FERRADLH; + }; + }; + union { + __IO uint16_t FERRADH; + struct { + __IO uint8_t FERRADHL; + __IO uint8_t FERRADHH; + }; + }; + }; + }; +} FM_ECC_CAPTURE_TypeDef, FM4_ECC_CAPTURE_TypeDef; + +/******************************************************************************* +* EXBUS_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t MODE0; + stc_exbus_mode0_field_t MODE0_f; + struct { + union { + __IO uint16_t MODE0L; + struct { + __IO uint8_t MODE0LL; + __IO uint8_t MODE0LH; + }; + }; + union { + __IO uint16_t MODE0H; + struct { + __IO uint8_t MODE0HL; + __IO uint8_t MODE0HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE1; + stc_exbus_mode1_field_t MODE1_f; + struct { + union { + __IO uint16_t MODE1L; + struct { + __IO uint8_t MODE1LL; + __IO uint8_t MODE1LH; + }; + }; + union { + __IO uint16_t MODE1H; + struct { + __IO uint8_t MODE1HL; + __IO uint8_t MODE1HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE2; + stc_exbus_mode2_field_t MODE2_f; + struct { + union { + __IO uint16_t MODE2L; + struct { + __IO uint8_t MODE2LL; + __IO uint8_t MODE2LH; + }; + }; + union { + __IO uint16_t MODE2H; + struct { + __IO uint8_t MODE2HL; + __IO uint8_t MODE2HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE3; + stc_exbus_mode3_field_t MODE3_f; + struct { + union { + __IO uint16_t MODE3L; + struct { + __IO uint8_t MODE3LL; + __IO uint8_t MODE3LH; + }; + }; + union { + __IO uint16_t MODE3H; + struct { + __IO uint8_t MODE3HL; + __IO uint8_t MODE3HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE4; + stc_exbus_mode4_field_t MODE4_f; + struct { + union { + __IO uint16_t MODE4L; + struct { + __IO uint8_t MODE4LL; + __IO uint8_t MODE4LH; + }; + }; + union { + __IO uint16_t MODE4H; + struct { + __IO uint8_t MODE4HL; + __IO uint8_t MODE4HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE5; + stc_exbus_mode5_field_t MODE5_f; + struct { + union { + __IO uint16_t MODE5L; + struct { + __IO uint8_t MODE5LL; + __IO uint8_t MODE5LH; + }; + }; + union { + __IO uint16_t MODE5H; + struct { + __IO uint8_t MODE5HL; + __IO uint8_t MODE5HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE6; + stc_exbus_mode6_field_t MODE6_f; + struct { + union { + __IO uint16_t MODE6L; + struct { + __IO uint8_t MODE6LL; + __IO uint8_t MODE6LH; + }; + }; + union { + __IO uint16_t MODE6H; + struct { + __IO uint8_t MODE6HL; + __IO uint8_t MODE6HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE7; + stc_exbus_mode7_field_t MODE7_f; + struct { + union { + __IO uint16_t MODE7L; + struct { + __IO uint8_t MODE7LL; + __IO uint8_t MODE7LH; + }; + }; + union { + __IO uint16_t MODE7H; + struct { + __IO uint8_t MODE7HL; + __IO uint8_t MODE7HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM0; + stc_exbus_tim0_field_t TIM0_f; + struct { + union { + __IO uint16_t TIM0L; + struct { + __IO uint8_t TIM0LL; + __IO uint8_t TIM0LH; + }; + }; + union { + __IO uint16_t TIM0H; + struct { + __IO uint8_t TIM0HL; + __IO uint8_t TIM0HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM1; + stc_exbus_tim1_field_t TIM1_f; + struct { + union { + __IO uint16_t TIM1L; + struct { + __IO uint8_t TIM1LL; + __IO uint8_t TIM1LH; + }; + }; + union { + __IO uint16_t TIM1H; + struct { + __IO uint8_t TIM1HL; + __IO uint8_t TIM1HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM2; + stc_exbus_tim2_field_t TIM2_f; + struct { + union { + __IO uint16_t TIM2L; + struct { + __IO uint8_t TIM2LL; + __IO uint8_t TIM2LH; + }; + }; + union { + __IO uint16_t TIM2H; + struct { + __IO uint8_t TIM2HL; + __IO uint8_t TIM2HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM3; + stc_exbus_tim3_field_t TIM3_f; + struct { + union { + __IO uint16_t TIM3L; + struct { + __IO uint8_t TIM3LL; + __IO uint8_t TIM3LH; + }; + }; + union { + __IO uint16_t TIM3H; + struct { + __IO uint8_t TIM3HL; + __IO uint8_t TIM3HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM4; + stc_exbus_tim4_field_t TIM4_f; + struct { + union { + __IO uint16_t TIM4L; + struct { + __IO uint8_t TIM4LL; + __IO uint8_t TIM4LH; + }; + }; + union { + __IO uint16_t TIM4H; + struct { + __IO uint8_t TIM4HL; + __IO uint8_t TIM4HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM5; + stc_exbus_tim5_field_t TIM5_f; + struct { + union { + __IO uint16_t TIM5L; + struct { + __IO uint8_t TIM5LL; + __IO uint8_t TIM5LH; + }; + }; + union { + __IO uint16_t TIM5H; + struct { + __IO uint8_t TIM5HL; + __IO uint8_t TIM5HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM6; + stc_exbus_tim6_field_t TIM6_f; + struct { + union { + __IO uint16_t TIM6L; + struct { + __IO uint8_t TIM6LL; + __IO uint8_t TIM6LH; + }; + }; + union { + __IO uint16_t TIM6H; + struct { + __IO uint8_t TIM6HL; + __IO uint8_t TIM6HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM7; + stc_exbus_tim7_field_t TIM7_f; + struct { + union { + __IO uint16_t TIM7L; + struct { + __IO uint8_t TIM7LL; + __IO uint8_t TIM7LH; + }; + }; + union { + __IO uint16_t TIM7H; + struct { + __IO uint8_t TIM7HL; + __IO uint8_t TIM7HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA0; + stc_exbus_area0_field_t AREA0_f; + struct { + union { + __IO uint16_t AREA0L; + struct { + __IO uint8_t AREA0LL; + __IO uint8_t AREA0LH; + }; + }; + union { + __IO uint16_t AREA0H; + struct { + __IO uint8_t AREA0HL; + __IO uint8_t AREA0HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA1; + stc_exbus_area1_field_t AREA1_f; + struct { + union { + __IO uint16_t AREA1L; + struct { + __IO uint8_t AREA1LL; + __IO uint8_t AREA1LH; + }; + }; + union { + __IO uint16_t AREA1H; + struct { + __IO uint8_t AREA1HL; + __IO uint8_t AREA1HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA2; + stc_exbus_area2_field_t AREA2_f; + struct { + union { + __IO uint16_t AREA2L; + struct { + __IO uint8_t AREA2LL; + __IO uint8_t AREA2LH; + }; + }; + union { + __IO uint16_t AREA2H; + struct { + __IO uint8_t AREA2HL; + __IO uint8_t AREA2HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA3; + stc_exbus_area3_field_t AREA3_f; + struct { + union { + __IO uint16_t AREA3L; + struct { + __IO uint8_t AREA3LL; + __IO uint8_t AREA3LH; + }; + }; + union { + __IO uint16_t AREA3H; + struct { + __IO uint8_t AREA3HL; + __IO uint8_t AREA3HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA4; + stc_exbus_area4_field_t AREA4_f; + struct { + union { + __IO uint16_t AREA4L; + struct { + __IO uint8_t AREA4LL; + __IO uint8_t AREA4LH; + }; + }; + union { + __IO uint16_t AREA4H; + struct { + __IO uint8_t AREA4HL; + __IO uint8_t AREA4HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA5; + stc_exbus_area5_field_t AREA5_f; + struct { + union { + __IO uint16_t AREA5L; + struct { + __IO uint8_t AREA5LL; + __IO uint8_t AREA5LH; + }; + }; + union { + __IO uint16_t AREA5H; + struct { + __IO uint8_t AREA5HL; + __IO uint8_t AREA5HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA6; + stc_exbus_area6_field_t AREA6_f; + struct { + union { + __IO uint16_t AREA6L; + struct { + __IO uint8_t AREA6LL; + __IO uint8_t AREA6LH; + }; + }; + union { + __IO uint16_t AREA6H; + struct { + __IO uint8_t AREA6HL; + __IO uint8_t AREA6HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA7; + stc_exbus_area7_field_t AREA7_f; + struct { + union { + __IO uint16_t AREA7L; + struct { + __IO uint8_t AREA7LL; + __IO uint8_t AREA7LH; + }; + }; + union { + __IO uint16_t AREA7H; + struct { + __IO uint8_t AREA7HL; + __IO uint8_t AREA7HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM0; + stc_exbus_atim0_field_t ATIM0_f; + struct { + union { + __IO uint16_t ATIM0L; + struct { + __IO uint8_t ATIM0LL; + __IO uint8_t ATIM0LH; + }; + }; + union { + __IO uint16_t ATIM0H; + struct { + __IO uint8_t ATIM0HL; + __IO uint8_t ATIM0HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM1; + stc_exbus_atim1_field_t ATIM1_f; + struct { + union { + __IO uint16_t ATIM1L; + struct { + __IO uint8_t ATIM1LL; + __IO uint8_t ATIM1LH; + }; + }; + union { + __IO uint16_t ATIM1H; + struct { + __IO uint8_t ATIM1HL; + __IO uint8_t ATIM1HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM2; + stc_exbus_atim2_field_t ATIM2_f; + struct { + union { + __IO uint16_t ATIM2L; + struct { + __IO uint8_t ATIM2LL; + __IO uint8_t ATIM2LH; + }; + }; + union { + __IO uint16_t ATIM2H; + struct { + __IO uint8_t ATIM2HL; + __IO uint8_t ATIM2HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM3; + stc_exbus_atim3_field_t ATIM3_f; + struct { + union { + __IO uint16_t ATIM3L; + struct { + __IO uint8_t ATIM3LL; + __IO uint8_t ATIM3LH; + }; + }; + union { + __IO uint16_t ATIM3H; + struct { + __IO uint8_t ATIM3HL; + __IO uint8_t ATIM3HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM4; + stc_exbus_atim4_field_t ATIM4_f; + struct { + union { + __IO uint16_t ATIM4L; + struct { + __IO uint8_t ATIM4LL; + __IO uint8_t ATIM4LH; + }; + }; + union { + __IO uint16_t ATIM4H; + struct { + __IO uint8_t ATIM4HL; + __IO uint8_t ATIM4HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM5; + stc_exbus_atim5_field_t ATIM5_f; + struct { + union { + __IO uint16_t ATIM5L; + struct { + __IO uint8_t ATIM5LL; + __IO uint8_t ATIM5LH; + }; + }; + union { + __IO uint16_t ATIM5H; + struct { + __IO uint8_t ATIM5HL; + __IO uint8_t ATIM5HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM6; + stc_exbus_atim6_field_t ATIM6_f; + struct { + union { + __IO uint16_t ATIM6L; + struct { + __IO uint8_t ATIM6LL; + __IO uint8_t ATIM6LH; + }; + }; + union { + __IO uint16_t ATIM6H; + struct { + __IO uint8_t ATIM6HL; + __IO uint8_t ATIM6HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM7; + stc_exbus_atim7_field_t ATIM7_f; + struct { + union { + __IO uint16_t ATIM7L; + struct { + __IO uint8_t ATIM7LL; + __IO uint8_t ATIM7LH; + }; + }; + union { + __IO uint16_t ATIM7H; + struct { + __IO uint8_t ATIM7HL; + __IO uint8_t ATIM7HH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[128]; + union { + __IO uint32_t SDMODE; + stc_exbus_sdmode_field_t SDMODE_f; + struct { + union { + __IO uint16_t SDMODEL; + struct { + __IO uint8_t SDMODELL; + __IO uint8_t SDMODELH; + }; + }; + union { + __IO uint16_t SDMODEH; + struct { + __IO uint8_t SDMODEHL; + __IO uint8_t SDMODEHH; + }; + }; + }; + }; + union { + __IO uint32_t REFTIM; + stc_exbus_reftim_field_t REFTIM_f; + struct { + union { + __IO uint16_t REFTIML; + struct { + __IO uint8_t REFTIMLL; + __IO uint8_t REFTIMLH; + }; + }; + union { + __IO uint16_t REFTIMH; + struct { + __IO uint8_t REFTIMHL; + __IO uint8_t REFTIMHH; + }; + }; + }; + }; + union { + __IO uint32_t PWRDWN; + stc_exbus_pwrdwn_field_t PWRDWN_f; + struct { + union { + __IO uint16_t PWRDWNL; + struct { + __IO uint8_t PWRDWNLL; + __IO uint8_t PWRDWNLH; + }; + }; + union { + __IO uint16_t PWRDWNH; + struct { + __IO uint8_t PWRDWNHL; + __IO uint8_t PWRDWNHH; + }; + }; + }; + }; + union { + __IO uint32_t SDTIM; + stc_exbus_sdtim_field_t SDTIM_f; + struct { + union { + __IO uint16_t SDTIML; + struct { + __IO uint8_t SDTIMLL; + __IO uint8_t SDTIMLH; + }; + }; + union { + __IO uint16_t SDTIMH; + struct { + __IO uint8_t SDTIMHL; + __IO uint8_t SDTIMHH; + }; + }; + }; + }; + union { + __IO uint32_t SDCMD; + stc_exbus_sdcmd_field_t SDCMD_f; + struct { + union { + __IO uint16_t SDCMDL; + struct { + __IO uint8_t SDCMDLL; + __IO uint8_t SDCMDLH; + }; + }; + union { + __IO uint16_t SDCMDH; + struct { + __IO uint8_t SDCMDHL; + __IO uint8_t SDCMDHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[236]; + union { + __IO uint32_t MEMCERR; + stc_exbus_memcerr_field_t MEMCERR_f; + struct { + union { + __IO uint16_t MEMCERRL; + struct { + __IO uint8_t MEMCERRLL; + __IO uint8_t MEMCERRLH; + }; + }; + union { + __IO uint16_t MEMCERRH; + struct { + __IO uint8_t MEMCERRHL; + __IO uint8_t MEMCERRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[252]; + union { + __IO uint32_t DCLKR; + stc_exbus_dclkr_field_t DCLKR_f; + struct { + union { + __IO uint16_t DCLKRL; + struct { + __IO uint8_t DCLKRLL; + __IO uint8_t DCLKRLH; + }; + }; + union { + __IO uint16_t DCLKRH; + struct { + __IO uint8_t DCLKRHL; + __IO uint8_t DCLKRHH; + }; + }; + }; + }; + union { + __IO uint32_t EST; + stc_exbus_est_field_t EST_f; + struct { + union { + __IO uint16_t ESTL; + struct { + __IO uint8_t ESTLL; + __IO uint8_t ESTLH; + }; + }; + union { + __IO uint16_t ESTH; + struct { + __IO uint8_t ESTHL; + __IO uint8_t ESTHH; + }; + }; + }; + }; + union { + __IO uint32_t WEAD; + stc_exbus_wead_field_t WEAD_f; + struct { + union { + __IO uint16_t WEADL; + struct { + __IO uint8_t WEADLL; + __IO uint8_t WEADLH; + }; + }; + union { + __IO uint16_t WEADH; + struct { + __IO uint8_t WEADHL; + __IO uint8_t WEADHH; + }; + }; + }; + }; + union { + __IO uint32_t ESCLR; + stc_exbus_esclr_field_t ESCLR_f; + struct { + union { + __IO uint16_t ESCLRL; + struct { + __IO uint8_t ESCLRLL; + __IO uint8_t ESCLRLH; + }; + }; + union { + __IO uint16_t ESCLRH; + struct { + __IO uint8_t ESCLRHL; + __IO uint8_t ESCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t AMODE; + stc_exbus_amode_field_t AMODE_f; + struct { + union { + __IO uint16_t AMODEL; + struct { + __IO uint8_t AMODELL; + __IO uint8_t AMODELH; + }; + }; + union { + __IO uint16_t AMODEH; + struct { + __IO uint8_t AMODEHL; + __IO uint8_t AMODEHH; + }; + }; + }; + }; +} FM_EXBUS_TypeDef, FM4_EXBUS_TypeDef; + +/******************************************************************************* +* EXTI_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t ENIR; + stc_exti_enir_field_t ENIR_f; + struct { + union { + __IO uint16_t ENIRL; + struct { + __IO uint8_t ENIRLL; + __IO uint8_t ENIRLH; + }; + }; + union { + __IO uint16_t ENIRH; + struct { + __IO uint8_t ENIRHL; + __IO uint8_t ENIRHH; + }; + }; + }; + }; + union { + __IO uint32_t EIRR; + stc_exti_eirr_field_t EIRR_f; + struct { + union { + __IO uint16_t EIRRL; + struct { + __IO uint8_t EIRRLL; + __IO uint8_t EIRRLH; + }; + }; + union { + __IO uint16_t EIRRH; + struct { + __IO uint8_t EIRRHL; + __IO uint8_t EIRRHH; + }; + }; + }; + }; + union { + __IO uint32_t EICL; + stc_exti_eicl_field_t EICL_f; + struct { + union { + __IO uint16_t EICLL; + struct { + __IO uint8_t EICLLL; + __IO uint8_t EICLLH; + }; + }; + union { + __IO uint16_t EICLH; + struct { + __IO uint8_t EICLHL; + __IO uint8_t EICLHH; + }; + }; + }; + }; + union { + __IO uint32_t ELVR; + stc_exti_elvr_field_t ELVR_f; + struct { + union { + __IO uint16_t ELVRL; + struct { + __IO uint8_t ELVRLL; + __IO uint8_t ELVRLH; + }; + }; + union { + __IO uint16_t ELVRH; + struct { + __IO uint8_t ELVRHL; + __IO uint8_t ELVRHH; + }; + }; + }; + }; + union { + __IO uint32_t ELVR1; + stc_exti_elvr1_field_t ELVR1_f; + struct { + union { + __IO uint16_t ELVR1L; + struct { + __IO uint8_t ELVR1LL; + __IO uint8_t ELVR1LH; + }; + }; + union { + __IO uint16_t ELVR1H; + struct { + __IO uint8_t ELVR1HL; + __IO uint8_t ELVR1HH; + }; + }; + }; + }; + union { + __IO uint16_t NMIRR; + stc_exti_nmirr_field_t NMIRR_f; + struct { + __IO uint8_t NMIRRL; + __IO uint8_t NMIRRH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t NMICL; + stc_exti_nmicl_field_t NMICL_f; + struct { + __IO uint8_t NMICLL; + __IO uint8_t NMICLH; + }; + }; +} FM_EXTI_TypeDef, FM4_EXTI_TypeDef; + +/******************************************************************************* +* FLASH_IF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t FASZR; + stc_flash_if_faszr_field_t FASZR_f; + struct { + union { + __IO uint16_t FASZRL; + struct { + __IO uint8_t FASZRLL; + __IO uint8_t FASZRLH; + }; + }; + union { + __IO uint16_t FASZRH; + struct { + __IO uint8_t FASZRHL; + __IO uint8_t FASZRHH; + }; + }; + }; + }; + union { + __IO uint32_t FRWTR; + stc_flash_if_frwtr_field_t FRWTR_f; + struct { + union { + __IO uint16_t FRWTRL; + struct { + __IO uint8_t FRWTRLL; + __IO uint8_t FRWTRLH; + }; + }; + union { + __IO uint16_t FRWTRH; + struct { + __IO uint8_t FRWTRHL; + __IO uint8_t FRWTRHH; + }; + }; + }; + }; + union { + __IO uint32_t FSTR; + stc_flash_if_fstr_field_t FSTR_f; + struct { + union { + __IO uint16_t FSTRL; + struct { + __IO uint8_t FSTRLL; + __IO uint8_t FSTRLH; + }; + }; + union { + __IO uint16_t FSTRH; + struct { + __IO uint8_t FSTRHL; + __IO uint8_t FSTRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t FSYNDN; + stc_flash_if_fsyndn_field_t FSYNDN_f; + struct { + union { + __IO uint16_t FSYNDNL; + struct { + __IO uint8_t FSYNDNLL; + __IO uint8_t FSYNDNLH; + }; + }; + union { + __IO uint16_t FSYNDNH; + struct { + __IO uint8_t FSYNDNHL; + __IO uint8_t FSYNDNHH; + }; + }; + }; + }; + union { + __IO uint32_t FBFCR; + stc_flash_if_fbfcr_field_t FBFCR_f; + struct { + union { + __IO uint16_t FBFCRL; + struct { + __IO uint8_t FBFCRLL; + __IO uint8_t FBFCRLH; + }; + }; + union { + __IO uint16_t FBFCRH; + struct { + __IO uint8_t FBFCRHL; + __IO uint8_t FBFCRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[8]; + union { + __IO uint32_t FICR; + stc_flash_if_ficr_field_t FICR_f; + struct { + union { + __IO uint16_t FICRL; + struct { + __IO uint8_t FICRLL; + __IO uint8_t FICRLH; + }; + }; + union { + __IO uint16_t FICRH; + struct { + __IO uint8_t FICRHL; + __IO uint8_t FICRHH; + }; + }; + }; + }; + union { + __IO uint32_t FISR; + stc_flash_if_fisr_field_t FISR_f; + struct { + union { + __IO uint16_t FISRL; + struct { + __IO uint8_t FISRLL; + __IO uint8_t FISRLH; + }; + }; + union { + __IO uint16_t FISRH; + struct { + __IO uint8_t FISRHL; + __IO uint8_t FISRHH; + }; + }; + }; + }; + union { + __IO uint32_t FICLR; + stc_flash_if_ficlr_field_t FICLR_f; + struct { + union { + __IO uint16_t FICLRL; + struct { + __IO uint8_t FICLRLL; + __IO uint8_t FICLRLH; + }; + }; + union { + __IO uint16_t FICLRH; + struct { + __IO uint8_t FICLRHL; + __IO uint8_t FICLRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[4]; + union { + __IO uint32_t DFCTRLR; + stc_flash_if_dfctrlr_field_t DFCTRLR_f; + struct { + union { + __IO uint16_t DFCTRLRL; + struct { + __IO uint8_t DFCTRLRLL; + __IO uint8_t DFCTRLRLH; + }; + }; + union { + __IO uint16_t DFCTRLRH; + struct { + __IO uint8_t DFCTRLRHL; + __IO uint8_t DFCTRLRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[204]; + union { + __IO uint32_t CRTRMM; + stc_flash_if_crtrmm_field_t CRTRMM_f; + struct { + union { + __IO uint16_t CRTRMML; + struct { + __IO uint8_t CRTRMMLL; + __IO uint8_t CRTRMMLH; + }; + }; + union { + __IO uint16_t CRTRMMH; + struct { + __IO uint8_t CRTRMMHL; + __IO uint8_t CRTRMMHH; + }; + }; + }; + }; + __IO uint8_t RESERVED4[12]; + union { + __IO uint32_t FGPDM1; + stc_flash_if_fgpdm1_field_t FGPDM1_f; + struct { + union { + __IO uint16_t FGPDM1L; + struct { + __IO uint8_t FGPDM1LL; + __IO uint8_t FGPDM1LH; + }; + }; + union { + __IO uint16_t FGPDM1H; + struct { + __IO uint8_t FGPDM1HL; + __IO uint8_t FGPDM1HH; + }; + }; + }; + }; + union { + __IO uint32_t FGPDM2; + stc_flash_if_fgpdm2_field_t FGPDM2_f; + struct { + union { + __IO uint16_t FGPDM2L; + struct { + __IO uint8_t FGPDM2LL; + __IO uint8_t FGPDM2LH; + }; + }; + union { + __IO uint16_t FGPDM2H; + struct { + __IO uint8_t FGPDM2HL; + __IO uint8_t FGPDM2HH; + }; + }; + }; + }; + union { + __IO uint32_t FGPDM3; + stc_flash_if_fgpdm3_field_t FGPDM3_f; + struct { + union { + __IO uint16_t FGPDM3L; + struct { + __IO uint8_t FGPDM3LL; + __IO uint8_t FGPDM3LH; + }; + }; + union { + __IO uint16_t FGPDM3H; + struct { + __IO uint8_t FGPDM3HL; + __IO uint8_t FGPDM3HH; + }; + }; + }; + }; + union { + __IO uint32_t FGPDM4; + stc_flash_if_fgpdm4_field_t FGPDM4_f; + struct { + union { + __IO uint16_t FGPDM4L; + struct { + __IO uint8_t FGPDM4LL; + __IO uint8_t FGPDM4LH; + }; + }; + union { + __IO uint16_t FGPDM4H; + struct { + __IO uint8_t FGPDM4HL; + __IO uint8_t FGPDM4HH; + }; + }; + }; + }; +} FM_FLASH_IF_TypeDef, FM4_FLASH_IF_TypeDef; + +/******************************************************************************* +* GPIO_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t PFR0; + stc_gpio_pfr0_field_t PFR0_f; + struct { + union { + __IO uint16_t PFR0L; + struct { + __IO uint8_t PFR0LL; + __IO uint8_t PFR0LH; + }; + }; + union { + __IO uint16_t PFR0H; + struct { + __IO uint8_t PFR0HL; + __IO uint8_t PFR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR1; + stc_gpio_pfr1_field_t PFR1_f; + struct { + union { + __IO uint16_t PFR1L; + struct { + __IO uint8_t PFR1LL; + __IO uint8_t PFR1LH; + }; + }; + union { + __IO uint16_t PFR1H; + struct { + __IO uint8_t PFR1HL; + __IO uint8_t PFR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR2; + stc_gpio_pfr2_field_t PFR2_f; + struct { + union { + __IO uint16_t PFR2L; + struct { + __IO uint8_t PFR2LL; + __IO uint8_t PFR2LH; + }; + }; + union { + __IO uint16_t PFR2H; + struct { + __IO uint8_t PFR2HL; + __IO uint8_t PFR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR3; + stc_gpio_pfr3_field_t PFR3_f; + struct { + union { + __IO uint16_t PFR3L; + struct { + __IO uint8_t PFR3LL; + __IO uint8_t PFR3LH; + }; + }; + union { + __IO uint16_t PFR3H; + struct { + __IO uint8_t PFR3HL; + __IO uint8_t PFR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR4; + stc_gpio_pfr4_field_t PFR4_f; + struct { + union { + __IO uint16_t PFR4L; + struct { + __IO uint8_t PFR4LL; + __IO uint8_t PFR4LH; + }; + }; + union { + __IO uint16_t PFR4H; + struct { + __IO uint8_t PFR4HL; + __IO uint8_t PFR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR5; + struct { + union { + __IO uint16_t PFR5L; + struct { + __IO uint8_t PFR5LL; + __IO uint8_t PFR5LH; + }; + }; + union { + __IO uint16_t PFR5H; + struct { + __IO uint8_t PFR5HL; + __IO uint8_t PFR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR6; + stc_gpio_pfr6_field_t PFR6_f; + struct { + union { + __IO uint16_t PFR6L; + struct { + __IO uint8_t PFR6LL; + __IO uint8_t PFR6LH; + }; + }; + union { + __IO uint16_t PFR6H; + struct { + __IO uint8_t PFR6HL; + __IO uint8_t PFR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR7; + stc_gpio_pfr7_field_t PFR7_f; + struct { + union { + __IO uint16_t PFR7L; + struct { + __IO uint8_t PFR7LL; + __IO uint8_t PFR7LH; + }; + }; + union { + __IO uint16_t PFR7H; + struct { + __IO uint8_t PFR7HL; + __IO uint8_t PFR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR8; + stc_gpio_pfr8_field_t PFR8_f; + struct { + union { + __IO uint16_t PFR8L; + struct { + __IO uint8_t PFR8LL; + __IO uint8_t PFR8LH; + }; + }; + union { + __IO uint16_t PFR8H; + struct { + __IO uint8_t PFR8HL; + __IO uint8_t PFR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR9; + struct { + union { + __IO uint16_t PFR9L; + struct { + __IO uint8_t PFR9LL; + __IO uint8_t PFR9LH; + }; + }; + union { + __IO uint16_t PFR9H; + struct { + __IO uint8_t PFR9HL; + __IO uint8_t PFR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PFRA; + stc_gpio_pfra_field_t PFRA_f; + struct { + union { + __IO uint16_t PFRAL; + struct { + __IO uint8_t PFRALL; + __IO uint8_t PFRALH; + }; + }; + union { + __IO uint16_t PFRAH; + struct { + __IO uint8_t PFRAHL; + __IO uint8_t PFRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRB; + struct { + union { + __IO uint16_t PFRBL; + struct { + __IO uint8_t PFRBLL; + __IO uint8_t PFRBLH; + }; + }; + union { + __IO uint16_t PFRBH; + struct { + __IO uint8_t PFRBHL; + __IO uint8_t PFRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRC; + stc_gpio_pfrc_field_t PFRC_f; + struct { + union { + __IO uint16_t PFRCL; + struct { + __IO uint8_t PFRCLL; + __IO uint8_t PFRCLH; + }; + }; + union { + __IO uint16_t PFRCH; + struct { + __IO uint8_t PFRCHL; + __IO uint8_t PFRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRD; + stc_gpio_pfrd_field_t PFRD_f; + struct { + union { + __IO uint16_t PFRDL; + struct { + __IO uint8_t PFRDLL; + __IO uint8_t PFRDLH; + }; + }; + union { + __IO uint16_t PFRDH; + struct { + __IO uint8_t PFRDHL; + __IO uint8_t PFRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRE; + stc_gpio_pfre_field_t PFRE_f; + struct { + union { + __IO uint16_t PFREL; + struct { + __IO uint8_t PFRELL; + __IO uint8_t PFRELH; + }; + }; + union { + __IO uint16_t PFREH; + struct { + __IO uint8_t PFREHL; + __IO uint8_t PFREHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRF; + struct { + union { + __IO uint16_t PFRFL; + struct { + __IO uint8_t PFRFLL; + __IO uint8_t PFRFLH; + }; + }; + union { + __IO uint16_t PFRFH; + struct { + __IO uint8_t PFRFHL; + __IO uint8_t PFRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[192]; + union { + __IO uint32_t PCR0; + stc_gpio_pcr0_field_t PCR0_f; + struct { + union { + __IO uint16_t PCR0L; + struct { + __IO uint8_t PCR0LL; + __IO uint8_t PCR0LH; + }; + }; + union { + __IO uint16_t PCR0H; + struct { + __IO uint8_t PCR0HL; + __IO uint8_t PCR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR1; + stc_gpio_pcr1_field_t PCR1_f; + struct { + union { + __IO uint16_t PCR1L; + struct { + __IO uint8_t PCR1LL; + __IO uint8_t PCR1LH; + }; + }; + union { + __IO uint16_t PCR1H; + struct { + __IO uint8_t PCR1HL; + __IO uint8_t PCR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR2; + stc_gpio_pcr2_field_t PCR2_f; + struct { + union { + __IO uint16_t PCR2L; + struct { + __IO uint8_t PCR2LL; + __IO uint8_t PCR2LH; + }; + }; + union { + __IO uint16_t PCR2H; + struct { + __IO uint8_t PCR2HL; + __IO uint8_t PCR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR3; + stc_gpio_pcr3_field_t PCR3_f; + struct { + union { + __IO uint16_t PCR3L; + struct { + __IO uint8_t PCR3LL; + __IO uint8_t PCR3LH; + }; + }; + union { + __IO uint16_t PCR3H; + struct { + __IO uint8_t PCR3HL; + __IO uint8_t PCR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR4; + stc_gpio_pcr4_field_t PCR4_f; + struct { + union { + __IO uint16_t PCR4L; + struct { + __IO uint8_t PCR4LL; + __IO uint8_t PCR4LH; + }; + }; + union { + __IO uint16_t PCR4H; + struct { + __IO uint8_t PCR4HL; + __IO uint8_t PCR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR5; + struct { + union { + __IO uint16_t PCR5L; + struct { + __IO uint8_t PCR5LL; + __IO uint8_t PCR5LH; + }; + }; + union { + __IO uint16_t PCR5H; + struct { + __IO uint8_t PCR5HL; + __IO uint8_t PCR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR6; + stc_gpio_pcr6_field_t PCR6_f; + struct { + union { + __IO uint16_t PCR6L; + struct { + __IO uint8_t PCR6LL; + __IO uint8_t PCR6LH; + }; + }; + union { + __IO uint16_t PCR6H; + struct { + __IO uint8_t PCR6HL; + __IO uint8_t PCR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR7; + stc_gpio_pcr7_field_t PCR7_f; + struct { + union { + __IO uint16_t PCR7L; + struct { + __IO uint8_t PCR7LL; + __IO uint8_t PCR7LH; + }; + }; + union { + __IO uint16_t PCR7H; + struct { + __IO uint8_t PCR7HL; + __IO uint8_t PCR7HH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[4]; + union { + __IO uint32_t PCR9; + struct { + union { + __IO uint16_t PCR9L; + struct { + __IO uint8_t PCR9LL; + __IO uint8_t PCR9LH; + }; + }; + union { + __IO uint16_t PCR9H; + struct { + __IO uint8_t PCR9HL; + __IO uint8_t PCR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PCRA; + stc_gpio_pcra_field_t PCRA_f; + struct { + union { + __IO uint16_t PCRAL; + struct { + __IO uint8_t PCRALL; + __IO uint8_t PCRALH; + }; + }; + union { + __IO uint16_t PCRAH; + struct { + __IO uint8_t PCRAHL; + __IO uint8_t PCRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRB; + struct { + union { + __IO uint16_t PCRBL; + struct { + __IO uint8_t PCRBLL; + __IO uint8_t PCRBLH; + }; + }; + union { + __IO uint16_t PCRBH; + struct { + __IO uint8_t PCRBHL; + __IO uint8_t PCRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC; + stc_gpio_pcrc_field_t PCRC_f; + struct { + union { + __IO uint16_t PCRCL; + struct { + __IO uint8_t PCRCLL; + __IO uint8_t PCRCLH; + }; + }; + union { + __IO uint16_t PCRCH; + struct { + __IO uint8_t PCRCHL; + __IO uint8_t PCRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRD; + stc_gpio_pcrd_field_t PCRD_f; + struct { + union { + __IO uint16_t PCRDL; + struct { + __IO uint8_t PCRDLL; + __IO uint8_t PCRDLH; + }; + }; + union { + __IO uint16_t PCRDH; + struct { + __IO uint8_t PCRDHL; + __IO uint8_t PCRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRE; + stc_gpio_pcre_field_t PCRE_f; + struct { + union { + __IO uint16_t PCREL; + struct { + __IO uint8_t PCRELL; + __IO uint8_t PCRELH; + }; + }; + union { + __IO uint16_t PCREH; + struct { + __IO uint8_t PCREHL; + __IO uint8_t PCREHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRF; + struct { + union { + __IO uint16_t PCRFL; + struct { + __IO uint8_t PCRFLL; + __IO uint8_t PCRFLH; + }; + }; + union { + __IO uint16_t PCRFH; + struct { + __IO uint8_t PCRFHL; + __IO uint8_t PCRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[192]; + union { + __IO uint32_t DDR0; + stc_gpio_ddr0_field_t DDR0_f; + struct { + union { + __IO uint16_t DDR0L; + struct { + __IO uint8_t DDR0LL; + __IO uint8_t DDR0LH; + }; + }; + union { + __IO uint16_t DDR0H; + struct { + __IO uint8_t DDR0HL; + __IO uint8_t DDR0HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR1; + stc_gpio_ddr1_field_t DDR1_f; + struct { + union { + __IO uint16_t DDR1L; + struct { + __IO uint8_t DDR1LL; + __IO uint8_t DDR1LH; + }; + }; + union { + __IO uint16_t DDR1H; + struct { + __IO uint8_t DDR1HL; + __IO uint8_t DDR1HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR2; + stc_gpio_ddr2_field_t DDR2_f; + struct { + union { + __IO uint16_t DDR2L; + struct { + __IO uint8_t DDR2LL; + __IO uint8_t DDR2LH; + }; + }; + union { + __IO uint16_t DDR2H; + struct { + __IO uint8_t DDR2HL; + __IO uint8_t DDR2HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR3; + stc_gpio_ddr3_field_t DDR3_f; + struct { + union { + __IO uint16_t DDR3L; + struct { + __IO uint8_t DDR3LL; + __IO uint8_t DDR3LH; + }; + }; + union { + __IO uint16_t DDR3H; + struct { + __IO uint8_t DDR3HL; + __IO uint8_t DDR3HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR4; + stc_gpio_ddr4_field_t DDR4_f; + struct { + union { + __IO uint16_t DDR4L; + struct { + __IO uint8_t DDR4LL; + __IO uint8_t DDR4LH; + }; + }; + union { + __IO uint16_t DDR4H; + struct { + __IO uint8_t DDR4HL; + __IO uint8_t DDR4HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR5; + struct { + union { + __IO uint16_t DDR5L; + struct { + __IO uint8_t DDR5LL; + __IO uint8_t DDR5LH; + }; + }; + union { + __IO uint16_t DDR5H; + struct { + __IO uint8_t DDR5HL; + __IO uint8_t DDR5HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR6; + stc_gpio_ddr6_field_t DDR6_f; + struct { + union { + __IO uint16_t DDR6L; + struct { + __IO uint8_t DDR6LL; + __IO uint8_t DDR6LH; + }; + }; + union { + __IO uint16_t DDR6H; + struct { + __IO uint8_t DDR6HL; + __IO uint8_t DDR6HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR7; + stc_gpio_ddr7_field_t DDR7_f; + struct { + union { + __IO uint16_t DDR7L; + struct { + __IO uint8_t DDR7LL; + __IO uint8_t DDR7LH; + }; + }; + union { + __IO uint16_t DDR7H; + struct { + __IO uint8_t DDR7HL; + __IO uint8_t DDR7HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR8; + stc_gpio_ddr8_field_t DDR8_f; + struct { + union { + __IO uint16_t DDR8L; + struct { + __IO uint8_t DDR8LL; + __IO uint8_t DDR8LH; + }; + }; + union { + __IO uint16_t DDR8H; + struct { + __IO uint8_t DDR8HL; + __IO uint8_t DDR8HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR9; + struct { + union { + __IO uint16_t DDR9L; + struct { + __IO uint8_t DDR9LL; + __IO uint8_t DDR9LH; + }; + }; + union { + __IO uint16_t DDR9H; + struct { + __IO uint8_t DDR9HL; + __IO uint8_t DDR9HH; + }; + }; + }; + }; + union { + __IO uint32_t DDRA; + stc_gpio_ddra_field_t DDRA_f; + struct { + union { + __IO uint16_t DDRAL; + struct { + __IO uint8_t DDRALL; + __IO uint8_t DDRALH; + }; + }; + union { + __IO uint16_t DDRAH; + struct { + __IO uint8_t DDRAHL; + __IO uint8_t DDRAHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRB; + struct { + union { + __IO uint16_t DDRBL; + struct { + __IO uint8_t DDRBLL; + __IO uint8_t DDRBLH; + }; + }; + union { + __IO uint16_t DDRBH; + struct { + __IO uint8_t DDRBHL; + __IO uint8_t DDRBHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRC; + stc_gpio_ddrc_field_t DDRC_f; + struct { + union { + __IO uint16_t DDRCL; + struct { + __IO uint8_t DDRCLL; + __IO uint8_t DDRCLH; + }; + }; + union { + __IO uint16_t DDRCH; + struct { + __IO uint8_t DDRCHL; + __IO uint8_t DDRCHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRD; + stc_gpio_ddrd_field_t DDRD_f; + struct { + union { + __IO uint16_t DDRDL; + struct { + __IO uint8_t DDRDLL; + __IO uint8_t DDRDLH; + }; + }; + union { + __IO uint16_t DDRDH; + struct { + __IO uint8_t DDRDHL; + __IO uint8_t DDRDHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRE; + stc_gpio_ddre_field_t DDRE_f; + struct { + union { + __IO uint16_t DDREL; + struct { + __IO uint8_t DDRELL; + __IO uint8_t DDRELH; + }; + }; + union { + __IO uint16_t DDREH; + struct { + __IO uint8_t DDREHL; + __IO uint8_t DDREHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRF; + struct { + union { + __IO uint16_t DDRFL; + struct { + __IO uint8_t DDRFLL; + __IO uint8_t DDRFLH; + }; + }; + union { + __IO uint16_t DDRFH; + struct { + __IO uint8_t DDRFHL; + __IO uint8_t DDRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[192]; + union { + __IO uint32_t PDIR0; + stc_gpio_pdir0_field_t PDIR0_f; + struct { + union { + __IO uint16_t PDIR0L; + struct { + __IO uint8_t PDIR0LL; + __IO uint8_t PDIR0LH; + }; + }; + union { + __IO uint16_t PDIR0H; + struct { + __IO uint8_t PDIR0HL; + __IO uint8_t PDIR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR1; + stc_gpio_pdir1_field_t PDIR1_f; + struct { + union { + __IO uint16_t PDIR1L; + struct { + __IO uint8_t PDIR1LL; + __IO uint8_t PDIR1LH; + }; + }; + union { + __IO uint16_t PDIR1H; + struct { + __IO uint8_t PDIR1HL; + __IO uint8_t PDIR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR2; + stc_gpio_pdir2_field_t PDIR2_f; + struct { + union { + __IO uint16_t PDIR2L; + struct { + __IO uint8_t PDIR2LL; + __IO uint8_t PDIR2LH; + }; + }; + union { + __IO uint16_t PDIR2H; + struct { + __IO uint8_t PDIR2HL; + __IO uint8_t PDIR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR3; + stc_gpio_pdir3_field_t PDIR3_f; + struct { + union { + __IO uint16_t PDIR3L; + struct { + __IO uint8_t PDIR3LL; + __IO uint8_t PDIR3LH; + }; + }; + union { + __IO uint16_t PDIR3H; + struct { + __IO uint8_t PDIR3HL; + __IO uint8_t PDIR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR4; + stc_gpio_pdir4_field_t PDIR4_f; + struct { + union { + __IO uint16_t PDIR4L; + struct { + __IO uint8_t PDIR4LL; + __IO uint8_t PDIR4LH; + }; + }; + union { + __IO uint16_t PDIR4H; + struct { + __IO uint8_t PDIR4HL; + __IO uint8_t PDIR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR5; + struct { + union { + __IO uint16_t PDIR5L; + struct { + __IO uint8_t PDIR5LL; + __IO uint8_t PDIR5LH; + }; + }; + union { + __IO uint16_t PDIR5H; + struct { + __IO uint8_t PDIR5HL; + __IO uint8_t PDIR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR6; + stc_gpio_pdir6_field_t PDIR6_f; + struct { + union { + __IO uint16_t PDIR6L; + struct { + __IO uint8_t PDIR6LL; + __IO uint8_t PDIR6LH; + }; + }; + union { + __IO uint16_t PDIR6H; + struct { + __IO uint8_t PDIR6HL; + __IO uint8_t PDIR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR7; + stc_gpio_pdir7_field_t PDIR7_f; + struct { + union { + __IO uint16_t PDIR7L; + struct { + __IO uint8_t PDIR7LL; + __IO uint8_t PDIR7LH; + }; + }; + union { + __IO uint16_t PDIR7H; + struct { + __IO uint8_t PDIR7HL; + __IO uint8_t PDIR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR8; + stc_gpio_pdir8_field_t PDIR8_f; + struct { + union { + __IO uint16_t PDIR8L; + struct { + __IO uint8_t PDIR8LL; + __IO uint8_t PDIR8LH; + }; + }; + union { + __IO uint16_t PDIR8H; + struct { + __IO uint8_t PDIR8HL; + __IO uint8_t PDIR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR9; + struct { + union { + __IO uint16_t PDIR9L; + struct { + __IO uint8_t PDIR9LL; + __IO uint8_t PDIR9LH; + }; + }; + union { + __IO uint16_t PDIR9H; + struct { + __IO uint8_t PDIR9HL; + __IO uint8_t PDIR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRA; + stc_gpio_pdira_field_t PDIRA_f; + struct { + union { + __IO uint16_t PDIRAL; + struct { + __IO uint8_t PDIRALL; + __IO uint8_t PDIRALH; + }; + }; + union { + __IO uint16_t PDIRAH; + struct { + __IO uint8_t PDIRAHL; + __IO uint8_t PDIRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRB; + struct { + union { + __IO uint16_t PDIRBL; + struct { + __IO uint8_t PDIRBLL; + __IO uint8_t PDIRBLH; + }; + }; + union { + __IO uint16_t PDIRBH; + struct { + __IO uint8_t PDIRBHL; + __IO uint8_t PDIRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRC; + stc_gpio_pdirc_field_t PDIRC_f; + struct { + union { + __IO uint16_t PDIRCL; + struct { + __IO uint8_t PDIRCLL; + __IO uint8_t PDIRCLH; + }; + }; + union { + __IO uint16_t PDIRCH; + struct { + __IO uint8_t PDIRCHL; + __IO uint8_t PDIRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRD; + stc_gpio_pdird_field_t PDIRD_f; + struct { + union { + __IO uint16_t PDIRDL; + struct { + __IO uint8_t PDIRDLL; + __IO uint8_t PDIRDLH; + }; + }; + union { + __IO uint16_t PDIRDH; + struct { + __IO uint8_t PDIRDHL; + __IO uint8_t PDIRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRE; + stc_gpio_pdire_field_t PDIRE_f; + struct { + union { + __IO uint16_t PDIREL; + struct { + __IO uint8_t PDIRELL; + __IO uint8_t PDIRELH; + }; + }; + union { + __IO uint16_t PDIREH; + struct { + __IO uint8_t PDIREHL; + __IO uint8_t PDIREHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRF; + struct { + union { + __IO uint16_t PDIRFL; + struct { + __IO uint8_t PDIRFLL; + __IO uint8_t PDIRFLH; + }; + }; + union { + __IO uint16_t PDIRFH; + struct { + __IO uint8_t PDIRFHL; + __IO uint8_t PDIRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED4[192]; + union { + __IO uint32_t PDOR0; + stc_gpio_pdor0_field_t PDOR0_f; + struct { + union { + __IO uint16_t PDOR0L; + struct { + __IO uint8_t PDOR0LL; + __IO uint8_t PDOR0LH; + }; + }; + union { + __IO uint16_t PDOR0H; + struct { + __IO uint8_t PDOR0HL; + __IO uint8_t PDOR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR1; + stc_gpio_pdor1_field_t PDOR1_f; + struct { + union { + __IO uint16_t PDOR1L; + struct { + __IO uint8_t PDOR1LL; + __IO uint8_t PDOR1LH; + }; + }; + union { + __IO uint16_t PDOR1H; + struct { + __IO uint8_t PDOR1HL; + __IO uint8_t PDOR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR2; + stc_gpio_pdor2_field_t PDOR2_f; + struct { + union { + __IO uint16_t PDOR2L; + struct { + __IO uint8_t PDOR2LL; + __IO uint8_t PDOR2LH; + }; + }; + union { + __IO uint16_t PDOR2H; + struct { + __IO uint8_t PDOR2HL; + __IO uint8_t PDOR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR3; + stc_gpio_pdor3_field_t PDOR3_f; + struct { + union { + __IO uint16_t PDOR3L; + struct { + __IO uint8_t PDOR3LL; + __IO uint8_t PDOR3LH; + }; + }; + union { + __IO uint16_t PDOR3H; + struct { + __IO uint8_t PDOR3HL; + __IO uint8_t PDOR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR4; + stc_gpio_pdor4_field_t PDOR4_f; + struct { + union { + __IO uint16_t PDOR4L; + struct { + __IO uint8_t PDOR4LL; + __IO uint8_t PDOR4LH; + }; + }; + union { + __IO uint16_t PDOR4H; + struct { + __IO uint8_t PDOR4HL; + __IO uint8_t PDOR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR5; + struct { + union { + __IO uint16_t PDOR5L; + struct { + __IO uint8_t PDOR5LL; + __IO uint8_t PDOR5LH; + }; + }; + union { + __IO uint16_t PDOR5H; + struct { + __IO uint8_t PDOR5HL; + __IO uint8_t PDOR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR6; + stc_gpio_pdor6_field_t PDOR6_f; + struct { + union { + __IO uint16_t PDOR6L; + struct { + __IO uint8_t PDOR6LL; + __IO uint8_t PDOR6LH; + }; + }; + union { + __IO uint16_t PDOR6H; + struct { + __IO uint8_t PDOR6HL; + __IO uint8_t PDOR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR7; + stc_gpio_pdor7_field_t PDOR7_f; + struct { + union { + __IO uint16_t PDOR7L; + struct { + __IO uint8_t PDOR7LL; + __IO uint8_t PDOR7LH; + }; + }; + union { + __IO uint16_t PDOR7H; + struct { + __IO uint8_t PDOR7HL; + __IO uint8_t PDOR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR8; + stc_gpio_pdor8_field_t PDOR8_f; + struct { + union { + __IO uint16_t PDOR8L; + struct { + __IO uint8_t PDOR8LL; + __IO uint8_t PDOR8LH; + }; + }; + union { + __IO uint16_t PDOR8H; + struct { + __IO uint8_t PDOR8HL; + __IO uint8_t PDOR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR9; + struct { + union { + __IO uint16_t PDOR9L; + struct { + __IO uint8_t PDOR9LL; + __IO uint8_t PDOR9LH; + }; + }; + union { + __IO uint16_t PDOR9H; + struct { + __IO uint8_t PDOR9HL; + __IO uint8_t PDOR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PDORA; + stc_gpio_pdora_field_t PDORA_f; + struct { + union { + __IO uint16_t PDORAL; + struct { + __IO uint8_t PDORALL; + __IO uint8_t PDORALH; + }; + }; + union { + __IO uint16_t PDORAH; + struct { + __IO uint8_t PDORAHL; + __IO uint8_t PDORAHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORB; + struct { + union { + __IO uint16_t PDORBL; + struct { + __IO uint8_t PDORBLL; + __IO uint8_t PDORBLH; + }; + }; + union { + __IO uint16_t PDORBH; + struct { + __IO uint8_t PDORBHL; + __IO uint8_t PDORBHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORC; + stc_gpio_pdorc_field_t PDORC_f; + struct { + union { + __IO uint16_t PDORCL; + struct { + __IO uint8_t PDORCLL; + __IO uint8_t PDORCLH; + }; + }; + union { + __IO uint16_t PDORCH; + struct { + __IO uint8_t PDORCHL; + __IO uint8_t PDORCHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORD; + stc_gpio_pdord_field_t PDORD_f; + struct { + union { + __IO uint16_t PDORDL; + struct { + __IO uint8_t PDORDLL; + __IO uint8_t PDORDLH; + }; + }; + union { + __IO uint16_t PDORDH; + struct { + __IO uint8_t PDORDHL; + __IO uint8_t PDORDHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORE; + stc_gpio_pdore_field_t PDORE_f; + struct { + union { + __IO uint16_t PDOREL; + struct { + __IO uint8_t PDORELL; + __IO uint8_t PDORELH; + }; + }; + union { + __IO uint16_t PDOREH; + struct { + __IO uint8_t PDOREHL; + __IO uint8_t PDOREHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORF; + struct { + union { + __IO uint16_t PDORFL; + struct { + __IO uint8_t PDORFLL; + __IO uint8_t PDORFLH; + }; + }; + union { + __IO uint16_t PDORFH; + struct { + __IO uint8_t PDORFHL; + __IO uint8_t PDORFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED5[192]; + union { + __IO uint32_t ADE; + stc_gpio_ade_field_t ADE_f; + struct { + union { + __IO uint16_t ADEL; + struct { + __IO uint8_t ADELL; + __IO uint8_t ADELH; + }; + }; + union { + __IO uint16_t ADEH; + struct { + __IO uint8_t ADEHL; + __IO uint8_t ADEHH; + }; + }; + }; + }; + __IO uint8_t RESERVED6[124]; + union { + __IO uint32_t SPSR; + stc_gpio_spsr_field_t SPSR_f; + struct { + union { + __IO uint16_t SPSRL; + struct { + __IO uint8_t SPSRLL; + __IO uint8_t SPSRLH; + }; + }; + union { + __IO uint16_t SPSRH; + struct { + __IO uint8_t SPSRHL; + __IO uint8_t SPSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED7[124]; + union { + __IO uint32_t EPFR00; + stc_gpio_epfr00_field_t EPFR00_f; + struct { + union { + __IO uint16_t EPFR00L; + struct { + __IO uint8_t EPFR00LL; + __IO uint8_t EPFR00LH; + }; + }; + union { + __IO uint16_t EPFR00H; + struct { + __IO uint8_t EPFR00HL; + __IO uint8_t EPFR00HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR01; + stc_gpio_epfr01_field_t EPFR01_f; + struct { + union { + __IO uint16_t EPFR01L; + struct { + __IO uint8_t EPFR01LL; + __IO uint8_t EPFR01LH; + }; + }; + union { + __IO uint16_t EPFR01H; + struct { + __IO uint8_t EPFR01HL; + __IO uint8_t EPFR01HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR02; + stc_gpio_epfr02_field_t EPFR02_f; + struct { + union { + __IO uint16_t EPFR02L; + struct { + __IO uint8_t EPFR02LL; + __IO uint8_t EPFR02LH; + }; + }; + union { + __IO uint16_t EPFR02H; + struct { + __IO uint8_t EPFR02HL; + __IO uint8_t EPFR02HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR03; + stc_gpio_epfr03_field_t EPFR03_f; + struct { + union { + __IO uint16_t EPFR03L; + struct { + __IO uint8_t EPFR03LL; + __IO uint8_t EPFR03LH; + }; + }; + union { + __IO uint16_t EPFR03H; + struct { + __IO uint8_t EPFR03HL; + __IO uint8_t EPFR03HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR04; + stc_gpio_epfr04_field_t EPFR04_f; + struct { + union { + __IO uint16_t EPFR04L; + struct { + __IO uint8_t EPFR04LL; + __IO uint8_t EPFR04LH; + }; + }; + union { + __IO uint16_t EPFR04H; + struct { + __IO uint8_t EPFR04HL; + __IO uint8_t EPFR04HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR05; + stc_gpio_epfr05_field_t EPFR05_f; + struct { + union { + __IO uint16_t EPFR05L; + struct { + __IO uint8_t EPFR05LL; + __IO uint8_t EPFR05LH; + }; + }; + union { + __IO uint16_t EPFR05H; + struct { + __IO uint8_t EPFR05HL; + __IO uint8_t EPFR05HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR06; + stc_gpio_epfr06_field_t EPFR06_f; + struct { + union { + __IO uint16_t EPFR06L; + struct { + __IO uint8_t EPFR06LL; + __IO uint8_t EPFR06LH; + }; + }; + union { + __IO uint16_t EPFR06H; + struct { + __IO uint8_t EPFR06HL; + __IO uint8_t EPFR06HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR07; + stc_gpio_epfr07_field_t EPFR07_f; + struct { + union { + __IO uint16_t EPFR07L; + struct { + __IO uint8_t EPFR07LL; + __IO uint8_t EPFR07LH; + }; + }; + union { + __IO uint16_t EPFR07H; + struct { + __IO uint8_t EPFR07HL; + __IO uint8_t EPFR07HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR08; + stc_gpio_epfr08_field_t EPFR08_f; + struct { + union { + __IO uint16_t EPFR08L; + struct { + __IO uint8_t EPFR08LL; + __IO uint8_t EPFR08LH; + }; + }; + union { + __IO uint16_t EPFR08H; + struct { + __IO uint8_t EPFR08HL; + __IO uint8_t EPFR08HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR09; + stc_gpio_epfr09_field_t EPFR09_f; + struct { + union { + __IO uint16_t EPFR09L; + struct { + __IO uint8_t EPFR09LL; + __IO uint8_t EPFR09LH; + }; + }; + union { + __IO uint16_t EPFR09H; + struct { + __IO uint8_t EPFR09HL; + __IO uint8_t EPFR09HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR10; + stc_gpio_epfr10_field_t EPFR10_f; + struct { + union { + __IO uint16_t EPFR10L; + struct { + __IO uint8_t EPFR10LL; + __IO uint8_t EPFR10LH; + }; + }; + union { + __IO uint16_t EPFR10H; + struct { + __IO uint8_t EPFR10HL; + __IO uint8_t EPFR10HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR11; + stc_gpio_epfr11_field_t EPFR11_f; + struct { + union { + __IO uint16_t EPFR11L; + struct { + __IO uint8_t EPFR11LL; + __IO uint8_t EPFR11LH; + }; + }; + union { + __IO uint16_t EPFR11H; + struct { + __IO uint8_t EPFR11HL; + __IO uint8_t EPFR11HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR12; + stc_gpio_epfr12_field_t EPFR12_f; + struct { + union { + __IO uint16_t EPFR12L; + struct { + __IO uint8_t EPFR12LL; + __IO uint8_t EPFR12LH; + }; + }; + union { + __IO uint16_t EPFR12H; + struct { + __IO uint8_t EPFR12HL; + __IO uint8_t EPFR12HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR13; + stc_gpio_epfr13_field_t EPFR13_f; + struct { + union { + __IO uint16_t EPFR13L; + struct { + __IO uint8_t EPFR13LL; + __IO uint8_t EPFR13LH; + }; + }; + union { + __IO uint16_t EPFR13H; + struct { + __IO uint8_t EPFR13HL; + __IO uint8_t EPFR13HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR14; + stc_gpio_epfr14_field_t EPFR14_f; + struct { + union { + __IO uint16_t EPFR14L; + struct { + __IO uint8_t EPFR14LL; + __IO uint8_t EPFR14LH; + }; + }; + union { + __IO uint16_t EPFR14H; + struct { + __IO uint8_t EPFR14HL; + __IO uint8_t EPFR14HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR15; + stc_gpio_epfr15_field_t EPFR15_f; + struct { + union { + __IO uint16_t EPFR15L; + struct { + __IO uint8_t EPFR15LL; + __IO uint8_t EPFR15LH; + }; + }; + union { + __IO uint16_t EPFR15H; + struct { + __IO uint8_t EPFR15HL; + __IO uint8_t EPFR15HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR16; + stc_gpio_epfr16_field_t EPFR16_f; + struct { + union { + __IO uint16_t EPFR16L; + struct { + __IO uint8_t EPFR16LL; + __IO uint8_t EPFR16LH; + }; + }; + union { + __IO uint16_t EPFR16H; + struct { + __IO uint8_t EPFR16HL; + __IO uint8_t EPFR16HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR17; + stc_gpio_epfr17_field_t EPFR17_f; + struct { + union { + __IO uint16_t EPFR17L; + struct { + __IO uint8_t EPFR17LL; + __IO uint8_t EPFR17LH; + }; + }; + union { + __IO uint16_t EPFR17H; + struct { + __IO uint8_t EPFR17HL; + __IO uint8_t EPFR17HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR18; + stc_gpio_epfr18_field_t EPFR18_f; + struct { + union { + __IO uint16_t EPFR18L; + struct { + __IO uint8_t EPFR18LL; + __IO uint8_t EPFR18LH; + }; + }; + union { + __IO uint16_t EPFR18H; + struct { + __IO uint8_t EPFR18HL; + __IO uint8_t EPFR18HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR19; + struct { + union { + __IO uint16_t EPFR19L; + struct { + __IO uint8_t EPFR19LL; + __IO uint8_t EPFR19LH; + }; + }; + union { + __IO uint16_t EPFR19H; + struct { + __IO uint8_t EPFR19HL; + __IO uint8_t EPFR19HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR20; + stc_gpio_epfr20_field_t EPFR20_f; + struct { + union { + __IO uint16_t EPFR20L; + struct { + __IO uint8_t EPFR20LL; + __IO uint8_t EPFR20LH; + }; + }; + union { + __IO uint16_t EPFR20H; + struct { + __IO uint8_t EPFR20HL; + __IO uint8_t EPFR20HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR21; + struct { + union { + __IO uint16_t EPFR21L; + struct { + __IO uint8_t EPFR21LL; + __IO uint8_t EPFR21LH; + }; + }; + union { + __IO uint16_t EPFR21H; + struct { + __IO uint8_t EPFR21HL; + __IO uint8_t EPFR21HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR22; + struct { + union { + __IO uint16_t EPFR22L; + struct { + __IO uint8_t EPFR22LL; + __IO uint8_t EPFR22LH; + }; + }; + union { + __IO uint16_t EPFR22H; + struct { + __IO uint8_t EPFR22HL; + __IO uint8_t EPFR22HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR23; + stc_gpio_epfr23_field_t EPFR23_f; + struct { + union { + __IO uint16_t EPFR23L; + struct { + __IO uint8_t EPFR23LL; + __IO uint8_t EPFR23LH; + }; + }; + union { + __IO uint16_t EPFR23H; + struct { + __IO uint8_t EPFR23HL; + __IO uint8_t EPFR23HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR24; + stc_gpio_epfr24_field_t EPFR24_f; + struct { + union { + __IO uint16_t EPFR24L; + struct { + __IO uint8_t EPFR24LL; + __IO uint8_t EPFR24LH; + }; + }; + union { + __IO uint16_t EPFR24H; + struct { + __IO uint8_t EPFR24HL; + __IO uint8_t EPFR24HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR25; + stc_gpio_epfr25_field_t EPFR25_f; + struct { + union { + __IO uint16_t EPFR25L; + struct { + __IO uint8_t EPFR25LL; + __IO uint8_t EPFR25LH; + }; + }; + union { + __IO uint16_t EPFR25H; + struct { + __IO uint8_t EPFR25HL; + __IO uint8_t EPFR25HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR26; + stc_gpio_epfr26_field_t EPFR26_f; + struct { + union { + __IO uint16_t EPFR26L; + struct { + __IO uint8_t EPFR26LL; + __IO uint8_t EPFR26LH; + }; + }; + union { + __IO uint16_t EPFR26H; + struct { + __IO uint8_t EPFR26HL; + __IO uint8_t EPFR26HH; + }; + }; + }; + }; + __IO uint8_t RESERVED8[148]; + union { + __IO uint32_t PZR0; + stc_gpio_pzr0_field_t PZR0_f; + struct { + union { + __IO uint16_t PZR0L; + struct { + __IO uint8_t PZR0LL; + __IO uint8_t PZR0LH; + }; + }; + union { + __IO uint16_t PZR0H; + struct { + __IO uint8_t PZR0HL; + __IO uint8_t PZR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR1; + stc_gpio_pzr1_field_t PZR1_f; + struct { + union { + __IO uint16_t PZR1L; + struct { + __IO uint8_t PZR1LL; + __IO uint8_t PZR1LH; + }; + }; + union { + __IO uint16_t PZR1H; + struct { + __IO uint8_t PZR1HL; + __IO uint8_t PZR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR2; + stc_gpio_pzr2_field_t PZR2_f; + struct { + union { + __IO uint16_t PZR2L; + struct { + __IO uint8_t PZR2LL; + __IO uint8_t PZR2LH; + }; + }; + union { + __IO uint16_t PZR2H; + struct { + __IO uint8_t PZR2HL; + __IO uint8_t PZR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR3; + stc_gpio_pzr3_field_t PZR3_f; + struct { + union { + __IO uint16_t PZR3L; + struct { + __IO uint8_t PZR3LL; + __IO uint8_t PZR3LH; + }; + }; + union { + __IO uint16_t PZR3H; + struct { + __IO uint8_t PZR3HL; + __IO uint8_t PZR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR4; + stc_gpio_pzr4_field_t PZR4_f; + struct { + union { + __IO uint16_t PZR4L; + struct { + __IO uint8_t PZR4LL; + __IO uint8_t PZR4LH; + }; + }; + union { + __IO uint16_t PZR4H; + struct { + __IO uint8_t PZR4HL; + __IO uint8_t PZR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR5; + struct { + union { + __IO uint16_t PZR5L; + struct { + __IO uint8_t PZR5LL; + __IO uint8_t PZR5LH; + }; + }; + union { + __IO uint16_t PZR5H; + struct { + __IO uint8_t PZR5HL; + __IO uint8_t PZR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR6; + stc_gpio_pzr6_field_t PZR6_f; + struct { + union { + __IO uint16_t PZR6L; + struct { + __IO uint8_t PZR6LL; + __IO uint8_t PZR6LH; + }; + }; + union { + __IO uint16_t PZR6H; + struct { + __IO uint8_t PZR6HL; + __IO uint8_t PZR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR7; + stc_gpio_pzr7_field_t PZR7_f; + struct { + union { + __IO uint16_t PZR7L; + struct { + __IO uint8_t PZR7LL; + __IO uint8_t PZR7LH; + }; + }; + union { + __IO uint16_t PZR7H; + struct { + __IO uint8_t PZR7HL; + __IO uint8_t PZR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR8; + stc_gpio_pzr8_field_t PZR8_f; + struct { + union { + __IO uint16_t PZR8L; + struct { + __IO uint8_t PZR8LL; + __IO uint8_t PZR8LH; + }; + }; + union { + __IO uint16_t PZR8H; + struct { + __IO uint8_t PZR8HL; + __IO uint8_t PZR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR9; + struct { + union { + __IO uint16_t PZR9L; + struct { + __IO uint8_t PZR9LL; + __IO uint8_t PZR9LH; + }; + }; + union { + __IO uint16_t PZR9H; + struct { + __IO uint8_t PZR9HL; + __IO uint8_t PZR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PZRA; + stc_gpio_pzra_field_t PZRA_f; + struct { + union { + __IO uint16_t PZRAL; + struct { + __IO uint8_t PZRALL; + __IO uint8_t PZRALH; + }; + }; + union { + __IO uint16_t PZRAH; + struct { + __IO uint8_t PZRAHL; + __IO uint8_t PZRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRB; + struct { + union { + __IO uint16_t PZRBL; + struct { + __IO uint8_t PZRBLL; + __IO uint8_t PZRBLH; + }; + }; + union { + __IO uint16_t PZRBH; + struct { + __IO uint8_t PZRBHL; + __IO uint8_t PZRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRC; + stc_gpio_pzrc_field_t PZRC_f; + struct { + union { + __IO uint16_t PZRCL; + struct { + __IO uint8_t PZRCLL; + __IO uint8_t PZRCLH; + }; + }; + union { + __IO uint16_t PZRCH; + struct { + __IO uint8_t PZRCHL; + __IO uint8_t PZRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRD; + stc_gpio_pzrd_field_t PZRD_f; + struct { + union { + __IO uint16_t PZRDL; + struct { + __IO uint8_t PZRDLL; + __IO uint8_t PZRDLH; + }; + }; + union { + __IO uint16_t PZRDH; + struct { + __IO uint8_t PZRDHL; + __IO uint8_t PZRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRE; + stc_gpio_pzre_field_t PZRE_f; + struct { + union { + __IO uint16_t PZREL; + struct { + __IO uint8_t PZRELL; + __IO uint8_t PZRELH; + }; + }; + union { + __IO uint16_t PZREH; + struct { + __IO uint8_t PZREHL; + __IO uint8_t PZREHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRF; + struct { + union { + __IO uint16_t PZRFL; + struct { + __IO uint8_t PZRFLL; + __IO uint8_t PZRFLH; + }; + }; + union { + __IO uint16_t PZRFH; + struct { + __IO uint8_t PZRFHL; + __IO uint8_t PZRFHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR0; + stc_gpio_pdsr0_field_t PDSR0_f; + struct { + union { + __IO uint16_t PDSR0L; + struct { + __IO uint8_t PDSR0LL; + __IO uint8_t PDSR0LH; + }; + }; + union { + __IO uint16_t PDSR0H; + struct { + __IO uint8_t PDSR0HL; + __IO uint8_t PDSR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR1; + stc_gpio_pdsr1_field_t PDSR1_f; + struct { + union { + __IO uint16_t PDSR1L; + struct { + __IO uint8_t PDSR1LL; + __IO uint8_t PDSR1LH; + }; + }; + union { + __IO uint16_t PDSR1H; + struct { + __IO uint8_t PDSR1HL; + __IO uint8_t PDSR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR2; + stc_gpio_pdsr2_field_t PDSR2_f; + struct { + union { + __IO uint16_t PDSR2L; + struct { + __IO uint8_t PDSR2LL; + __IO uint8_t PDSR2LH; + }; + }; + union { + __IO uint16_t PDSR2H; + struct { + __IO uint8_t PDSR2HL; + __IO uint8_t PDSR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR3; + stc_gpio_pdsr3_field_t PDSR3_f; + struct { + union { + __IO uint16_t PDSR3L; + struct { + __IO uint8_t PDSR3LL; + __IO uint8_t PDSR3LH; + }; + }; + union { + __IO uint16_t PDSR3H; + struct { + __IO uint8_t PDSR3HL; + __IO uint8_t PDSR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR4; + stc_gpio_pdsr4_field_t PDSR4_f; + struct { + union { + __IO uint16_t PDSR4L; + struct { + __IO uint8_t PDSR4LL; + __IO uint8_t PDSR4LH; + }; + }; + union { + __IO uint16_t PDSR4H; + struct { + __IO uint8_t PDSR4HL; + __IO uint8_t PDSR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR5; + struct { + union { + __IO uint16_t PDSR5L; + struct { + __IO uint8_t PDSR5LL; + __IO uint8_t PDSR5LH; + }; + }; + union { + __IO uint16_t PDSR5H; + struct { + __IO uint8_t PDSR5HL; + __IO uint8_t PDSR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR6; + stc_gpio_pdsr6_field_t PDSR6_f; + struct { + union { + __IO uint16_t PDSR6L; + struct { + __IO uint8_t PDSR6LL; + __IO uint8_t PDSR6LH; + }; + }; + union { + __IO uint16_t PDSR6H; + struct { + __IO uint8_t PDSR6HL; + __IO uint8_t PDSR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR7; + stc_gpio_pdsr7_field_t PDSR7_f; + struct { + union { + __IO uint16_t PDSR7L; + struct { + __IO uint8_t PDSR7LL; + __IO uint8_t PDSR7LH; + }; + }; + union { + __IO uint16_t PDSR7H; + struct { + __IO uint8_t PDSR7HL; + __IO uint8_t PDSR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR8; + stc_gpio_pdsr8_field_t PDSR8_f; + struct { + union { + __IO uint16_t PDSR8L; + struct { + __IO uint8_t PDSR8LL; + __IO uint8_t PDSR8LH; + }; + }; + union { + __IO uint16_t PDSR8H; + struct { + __IO uint8_t PDSR8HL; + __IO uint8_t PDSR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR9; + struct { + union { + __IO uint16_t PDSR9L; + struct { + __IO uint8_t PDSR9LL; + __IO uint8_t PDSR9LH; + }; + }; + union { + __IO uint16_t PDSR9H; + struct { + __IO uint8_t PDSR9HL; + __IO uint8_t PDSR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRA; + stc_gpio_pdsra_field_t PDSRA_f; + struct { + union { + __IO uint16_t PDSRAL; + struct { + __IO uint8_t PDSRALL; + __IO uint8_t PDSRALH; + }; + }; + union { + __IO uint16_t PDSRAH; + struct { + __IO uint8_t PDSRAHL; + __IO uint8_t PDSRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRB; + struct { + union { + __IO uint16_t PDSRBL; + struct { + __IO uint8_t PDSRBLL; + __IO uint8_t PDSRBLH; + }; + }; + union { + __IO uint16_t PDSRBH; + struct { + __IO uint8_t PDSRBHL; + __IO uint8_t PDSRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRC; + stc_gpio_pdsrc_field_t PDSRC_f; + struct { + union { + __IO uint16_t PDSRCL; + struct { + __IO uint8_t PDSRCLL; + __IO uint8_t PDSRCLH; + }; + }; + union { + __IO uint16_t PDSRCH; + struct { + __IO uint8_t PDSRCHL; + __IO uint8_t PDSRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRD; + stc_gpio_pdsrd_field_t PDSRD_f; + struct { + union { + __IO uint16_t PDSRDL; + struct { + __IO uint8_t PDSRDLL; + __IO uint8_t PDSRDLH; + }; + }; + union { + __IO uint16_t PDSRDH; + struct { + __IO uint8_t PDSRDHL; + __IO uint8_t PDSRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRE; + stc_gpio_pdsre_field_t PDSRE_f; + struct { + union { + __IO uint16_t PDSREL; + struct { + __IO uint8_t PDSRELL; + __IO uint8_t PDSRELH; + }; + }; + union { + __IO uint16_t PDSREH; + struct { + __IO uint8_t PDSREHL; + __IO uint8_t PDSREHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRF; + struct { + union { + __IO uint16_t PDSRFL; + struct { + __IO uint8_t PDSRFLL; + __IO uint8_t PDSRFLH; + }; + }; + union { + __IO uint16_t PDSRFH; + struct { + __IO uint8_t PDSRFHL; + __IO uint8_t PDSRFHH; + }; + }; + }; + }; +} FM_GPIO_TypeDef, FM4_GPIO_TypeDef; + +/******************************************************************************* +* HSSPI_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t MCTRL; + stc_hsspi_mctrl_field_t MCTRL_f; + struct { + union { + __IO uint16_t MCTRLL; + struct { + __IO uint8_t MCTRLLL; + __IO uint8_t MCTRLLH; + }; + }; + union { + __IO uint16_t MCTRLH; + struct { + __IO uint8_t MCTRLHL; + __IO uint8_t MCTRLHH; + }; + }; + }; + }; + union { + __IO uint32_t PCC0; + stc_hsspi_pcc0_field_t PCC0_f; + struct { + union { + __IO uint16_t PCC0L; + struct { + __IO uint8_t PCC0LL; + __IO uint8_t PCC0LH; + }; + }; + union { + __IO uint16_t PCC0H; + struct { + __IO uint8_t PCC0HL; + __IO uint8_t PCC0HH; + }; + }; + }; + }; + union { + __IO uint32_t PCC1; + stc_hsspi_pcc1_field_t PCC1_f; + struct { + union { + __IO uint16_t PCC1L; + struct { + __IO uint8_t PCC1LL; + __IO uint8_t PCC1LH; + }; + }; + union { + __IO uint16_t PCC1H; + struct { + __IO uint8_t PCC1HL; + __IO uint8_t PCC1HH; + }; + }; + }; + }; + union { + __IO uint32_t PCC2; + stc_hsspi_pcc2_field_t PCC2_f; + struct { + union { + __IO uint16_t PCC2L; + struct { + __IO uint8_t PCC2LL; + __IO uint8_t PCC2LH; + }; + }; + union { + __IO uint16_t PCC2H; + struct { + __IO uint8_t PCC2HL; + __IO uint8_t PCC2HH; + }; + }; + }; + }; + union { + __IO uint32_t PCC3; + stc_hsspi_pcc3_field_t PCC3_f; + struct { + union { + __IO uint16_t PCC3L; + struct { + __IO uint8_t PCC3LL; + __IO uint8_t PCC3LH; + }; + }; + union { + __IO uint16_t PCC3H; + struct { + __IO uint8_t PCC3HL; + __IO uint8_t PCC3HH; + }; + }; + }; + }; + union { + __IO uint32_t TXF; + stc_hsspi_txf_field_t TXF_f; + struct { + union { + __IO uint16_t TXFL; + struct { + __IO uint8_t TXFLL; + __IO uint8_t TXFLH; + }; + }; + union { + __IO uint16_t TXFH; + struct { + __IO uint8_t TXFHL; + __IO uint8_t TXFHH; + }; + }; + }; + }; + union { + __IO uint32_t TXE; + stc_hsspi_txe_field_t TXE_f; + struct { + union { + __IO uint16_t TXEL; + struct { + __IO uint8_t TXELL; + __IO uint8_t TXELH; + }; + }; + union { + __IO uint16_t TXEH; + struct { + __IO uint8_t TXEHL; + __IO uint8_t TXEHH; + }; + }; + }; + }; + union { + __IO uint32_t TXC; + stc_hsspi_txc_field_t TXC_f; + struct { + union { + __IO uint16_t TXCL; + struct { + __IO uint8_t TXCLL; + __IO uint8_t TXCLH; + }; + }; + union { + __IO uint16_t TXCH; + struct { + __IO uint8_t TXCHL; + __IO uint8_t TXCHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF; + stc_hsspi_rxf_field_t RXF_f; + struct { + union { + __IO uint16_t RXFL; + struct { + __IO uint8_t RXFLL; + __IO uint8_t RXFLH; + }; + }; + union { + __IO uint16_t RXFH; + struct { + __IO uint8_t RXFHL; + __IO uint8_t RXFHH; + }; + }; + }; + }; + union { + __IO uint32_t RXE; + stc_hsspi_rxe_field_t RXE_f; + struct { + union { + __IO uint16_t RXEL; + struct { + __IO uint8_t RXELL; + __IO uint8_t RXELH; + }; + }; + union { + __IO uint16_t RXEH; + struct { + __IO uint8_t RXEHL; + __IO uint8_t RXEHH; + }; + }; + }; + }; + union { + __IO uint32_t RXC; + stc_hsspi_rxc_field_t RXC_f; + struct { + union { + __IO uint16_t RXCL; + struct { + __IO uint8_t RXCLL; + __IO uint8_t RXCLH; + }; + }; + union { + __IO uint16_t RXCH; + struct { + __IO uint8_t RXCHL; + __IO uint8_t RXCHH; + }; + }; + }; + }; + union { + __IO uint32_t FAULTF; + stc_hsspi_faultf_field_t FAULTF_f; + struct { + union { + __IO uint16_t FAULTFL; + struct { + __IO uint8_t FAULTFLL; + __IO uint8_t FAULTFLH; + }; + }; + union { + __IO uint16_t FAULTFH; + struct { + __IO uint8_t FAULTFHL; + __IO uint8_t FAULTFHH; + }; + }; + }; + }; + union { + __IO uint32_t FAULTC; + stc_hsspi_faultc_field_t FAULTC_f; + struct { + union { + __IO uint16_t FAULTCL; + struct { + __IO uint8_t FAULTCLL; + __IO uint8_t FAULTCLH; + }; + }; + union { + __IO uint16_t FAULTCH; + struct { + __IO uint8_t FAULTCHL; + __IO uint8_t FAULTCHH; + }; + }; + }; + }; + union { + __IO uint8_t DMCFG; + stc_hsspi_dmcfg_field_t DMCFG_f; + }; + union { + __IO uint8_t DMDMAEN; + stc_hsspi_dmdmaen_field_t DMDMAEN_f; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint8_t DMSTART; + stc_hsspi_dmstart_field_t DMSTART_f; + }; + union { + __IO uint8_t DMSTOP; + stc_hsspi_dmstop_field_t DMSTOP_f; + }; + union { + __IO uint8_t DMPSEL; + stc_hsspi_dmpsel_field_t DMPSEL_f; + }; + union { + __IO uint8_t DMTRP; + stc_hsspi_dmtrp_field_t DMTRP_f; + }; + union { + __IO uint16_t DMBCC; + stc_hsspi_dmbcc_field_t DMBCC_f; + struct { + __IO uint8_t DMBCCL; + __IO uint8_t DMBCCH; + }; + }; + union { + __IO uint16_t DMBCS; + stc_hsspi_dmbcs_field_t DMBCS_f; + struct { + __IO uint8_t DMBCSL; + __IO uint8_t DMBCSH; + }; + }; + union { + __IO uint32_t DMSTATUS; + stc_hsspi_dmstatus_field_t DMSTATUS_f; + struct { + union { + __IO uint16_t DMSTATUSL; + struct { + __IO uint8_t DMSTATUSLL; + __IO uint8_t DMSTATUSLH; + }; + }; + union { + __IO uint16_t DMSTATUSH; + struct { + __IO uint8_t DMSTATUSHL; + __IO uint8_t DMSTATUSHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[8]; + union { + __IO uint32_t FIFOCFG; + stc_hsspi_fifocfg_field_t FIFOCFG_f; + struct { + union { + __IO uint16_t FIFOCFGL; + struct { + __IO uint8_t FIFOCFGLL; + __IO uint8_t FIFOCFGLH; + }; + }; + union { + __IO uint16_t FIFOCFGH; + struct { + __IO uint8_t FIFOCFGHL; + __IO uint8_t FIFOCFGHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO0; + stc_hsspi_txfifo0_field_t TXFIFO0_f; + struct { + union { + __IO uint16_t TXFIFO0L; + struct { + __IO uint8_t TXFIFO0LL; + __IO uint8_t TXFIFO0LH; + }; + }; + union { + __IO uint16_t TXFIFO0H; + struct { + __IO uint8_t TXFIFO0HL; + __IO uint8_t TXFIFO0HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO1; + stc_hsspi_txfifo1_field_t TXFIFO1_f; + struct { + union { + __IO uint16_t TXFIFO1L; + struct { + __IO uint8_t TXFIFO1LL; + __IO uint8_t TXFIFO1LH; + }; + }; + union { + __IO uint16_t TXFIFO1H; + struct { + __IO uint8_t TXFIFO1HL; + __IO uint8_t TXFIFO1HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO2; + stc_hsspi_txfifo2_field_t TXFIFO2_f; + struct { + union { + __IO uint16_t TXFIFO2L; + struct { + __IO uint8_t TXFIFO2LL; + __IO uint8_t TXFIFO2LH; + }; + }; + union { + __IO uint16_t TXFIFO2H; + struct { + __IO uint8_t TXFIFO2HL; + __IO uint8_t TXFIFO2HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO3; + stc_hsspi_txfifo3_field_t TXFIFO3_f; + struct { + union { + __IO uint16_t TXFIFO3L; + struct { + __IO uint8_t TXFIFO3LL; + __IO uint8_t TXFIFO3LH; + }; + }; + union { + __IO uint16_t TXFIFO3H; + struct { + __IO uint8_t TXFIFO3HL; + __IO uint8_t TXFIFO3HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO4; + stc_hsspi_txfifo4_field_t TXFIFO4_f; + struct { + union { + __IO uint16_t TXFIFO4L; + struct { + __IO uint8_t TXFIFO4LL; + __IO uint8_t TXFIFO4LH; + }; + }; + union { + __IO uint16_t TXFIFO4H; + struct { + __IO uint8_t TXFIFO4HL; + __IO uint8_t TXFIFO4HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO5; + stc_hsspi_txfifo5_field_t TXFIFO5_f; + struct { + union { + __IO uint16_t TXFIFO5L; + struct { + __IO uint8_t TXFIFO5LL; + __IO uint8_t TXFIFO5LH; + }; + }; + union { + __IO uint16_t TXFIFO5H; + struct { + __IO uint8_t TXFIFO5HL; + __IO uint8_t TXFIFO5HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO6; + stc_hsspi_txfifo6_field_t TXFIFO6_f; + struct { + union { + __IO uint16_t TXFIFO6L; + struct { + __IO uint8_t TXFIFO6LL; + __IO uint8_t TXFIFO6LH; + }; + }; + union { + __IO uint16_t TXFIFO6H; + struct { + __IO uint8_t TXFIFO6HL; + __IO uint8_t TXFIFO6HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO7; + stc_hsspi_txfifo7_field_t TXFIFO7_f; + struct { + union { + __IO uint16_t TXFIFO7L; + struct { + __IO uint8_t TXFIFO7LL; + __IO uint8_t TXFIFO7LH; + }; + }; + union { + __IO uint16_t TXFIFO7H; + struct { + __IO uint8_t TXFIFO7HL; + __IO uint8_t TXFIFO7HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO8; + stc_hsspi_txfifo8_field_t TXFIFO8_f; + struct { + union { + __IO uint16_t TXFIFO8L; + struct { + __IO uint8_t TXFIFO8LL; + __IO uint8_t TXFIFO8LH; + }; + }; + union { + __IO uint16_t TXFIFO8H; + struct { + __IO uint8_t TXFIFO8HL; + __IO uint8_t TXFIFO8HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO9; + stc_hsspi_txfifo9_field_t TXFIFO9_f; + struct { + union { + __IO uint16_t TXFIFO9L; + struct { + __IO uint8_t TXFIFO9LL; + __IO uint8_t TXFIFO9LH; + }; + }; + union { + __IO uint16_t TXFIFO9H; + struct { + __IO uint8_t TXFIFO9HL; + __IO uint8_t TXFIFO9HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO10; + stc_hsspi_txfifo10_field_t TXFIFO10_f; + struct { + union { + __IO uint16_t TXFIFO10L; + struct { + __IO uint8_t TXFIFO10LL; + __IO uint8_t TXFIFO10LH; + }; + }; + union { + __IO uint16_t TXFIFO10H; + struct { + __IO uint8_t TXFIFO10HL; + __IO uint8_t TXFIFO10HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO11; + stc_hsspi_txfifo11_field_t TXFIFO11_f; + struct { + union { + __IO uint16_t TXFIFO11L; + struct { + __IO uint8_t TXFIFO11LL; + __IO uint8_t TXFIFO11LH; + }; + }; + union { + __IO uint16_t TXFIFO11H; + struct { + __IO uint8_t TXFIFO11HL; + __IO uint8_t TXFIFO11HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO12; + stc_hsspi_txfifo12_field_t TXFIFO12_f; + struct { + union { + __IO uint16_t TXFIFO12L; + struct { + __IO uint8_t TXFIFO12LL; + __IO uint8_t TXFIFO12LH; + }; + }; + union { + __IO uint16_t TXFIFO12H; + struct { + __IO uint8_t TXFIFO12HL; + __IO uint8_t TXFIFO12HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO13; + stc_hsspi_txfifo13_field_t TXFIFO13_f; + struct { + union { + __IO uint16_t TXFIFO13L; + struct { + __IO uint8_t TXFIFO13LL; + __IO uint8_t TXFIFO13LH; + }; + }; + union { + __IO uint16_t TXFIFO13H; + struct { + __IO uint8_t TXFIFO13HL; + __IO uint8_t TXFIFO13HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO14; + stc_hsspi_txfifo14_field_t TXFIFO14_f; + struct { + union { + __IO uint16_t TXFIFO14L; + struct { + __IO uint8_t TXFIFO14LL; + __IO uint8_t TXFIFO14LH; + }; + }; + union { + __IO uint16_t TXFIFO14H; + struct { + __IO uint8_t TXFIFO14HL; + __IO uint8_t TXFIFO14HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO15; + stc_hsspi_txfifo15_field_t TXFIFO15_f; + struct { + union { + __IO uint16_t TXFIFO15L; + struct { + __IO uint8_t TXFIFO15LL; + __IO uint8_t TXFIFO15LH; + }; + }; + union { + __IO uint16_t TXFIFO15H; + struct { + __IO uint8_t TXFIFO15HL; + __IO uint8_t TXFIFO15HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO0; + stc_hsspi_rxfifo0_field_t RXFIFO0_f; + struct { + union { + __IO uint16_t RXFIFO0L; + struct { + __IO uint8_t RXFIFO0LL; + __IO uint8_t RXFIFO0LH; + }; + }; + union { + __IO uint16_t RXFIFO0H; + struct { + __IO uint8_t RXFIFO0HL; + __IO uint8_t RXFIFO0HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO1; + stc_hsspi_rxfifo1_field_t RXFIFO1_f; + struct { + union { + __IO uint16_t RXFIFO1L; + struct { + __IO uint8_t RXFIFO1LL; + __IO uint8_t RXFIFO1LH; + }; + }; + union { + __IO uint16_t RXFIFO1H; + struct { + __IO uint8_t RXFIFO1HL; + __IO uint8_t RXFIFO1HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO2; + stc_hsspi_rxfifo2_field_t RXFIFO2_f; + struct { + union { + __IO uint16_t RXFIFO2L; + struct { + __IO uint8_t RXFIFO2LL; + __IO uint8_t RXFIFO2LH; + }; + }; + union { + __IO uint16_t RXFIFO2H; + struct { + __IO uint8_t RXFIFO2HL; + __IO uint8_t RXFIFO2HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO3; + stc_hsspi_rxfifo3_field_t RXFIFO3_f; + struct { + union { + __IO uint16_t RXFIFO3L; + struct { + __IO uint8_t RXFIFO3LL; + __IO uint8_t RXFIFO3LH; + }; + }; + union { + __IO uint16_t RXFIFO3H; + struct { + __IO uint8_t RXFIFO3HL; + __IO uint8_t RXFIFO3HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO4; + stc_hsspi_rxfifo4_field_t RXFIFO4_f; + struct { + union { + __IO uint16_t RXFIFO4L; + struct { + __IO uint8_t RXFIFO4LL; + __IO uint8_t RXFIFO4LH; + }; + }; + union { + __IO uint16_t RXFIFO4H; + struct { + __IO uint8_t RXFIFO4HL; + __IO uint8_t RXFIFO4HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO5; + stc_hsspi_rxfifo5_field_t RXFIFO5_f; + struct { + union { + __IO uint16_t RXFIFO5L; + struct { + __IO uint8_t RXFIFO5LL; + __IO uint8_t RXFIFO5LH; + }; + }; + union { + __IO uint16_t RXFIFO5H; + struct { + __IO uint8_t RXFIFO5HL; + __IO uint8_t RXFIFO5HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO6; + stc_hsspi_rxfifo6_field_t RXFIFO6_f; + struct { + union { + __IO uint16_t RXFIFO6L; + struct { + __IO uint8_t RXFIFO6LL; + __IO uint8_t RXFIFO6LH; + }; + }; + union { + __IO uint16_t RXFIFO6H; + struct { + __IO uint8_t RXFIFO6HL; + __IO uint8_t RXFIFO6HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO7; + stc_hsspi_rxfifo7_field_t RXFIFO7_f; + struct { + union { + __IO uint16_t RXFIFO7L; + struct { + __IO uint8_t RXFIFO7LL; + __IO uint8_t RXFIFO7LH; + }; + }; + union { + __IO uint16_t RXFIFO7H; + struct { + __IO uint8_t RXFIFO7HL; + __IO uint8_t RXFIFO7HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO8; + stc_hsspi_rxfifo8_field_t RXFIFO8_f; + struct { + union { + __IO uint16_t RXFIFO8L; + struct { + __IO uint8_t RXFIFO8LL; + __IO uint8_t RXFIFO8LH; + }; + }; + union { + __IO uint16_t RXFIFO8H; + struct { + __IO uint8_t RXFIFO8HL; + __IO uint8_t RXFIFO8HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO9; + stc_hsspi_rxfifo9_field_t RXFIFO9_f; + struct { + union { + __IO uint16_t RXFIFO9L; + struct { + __IO uint8_t RXFIFO9LL; + __IO uint8_t RXFIFO9LH; + }; + }; + union { + __IO uint16_t RXFIFO9H; + struct { + __IO uint8_t RXFIFO9HL; + __IO uint8_t RXFIFO9HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO10; + stc_hsspi_rxfifo10_field_t RXFIFO10_f; + struct { + union { + __IO uint16_t RXFIFO10L; + struct { + __IO uint8_t RXFIFO10LL; + __IO uint8_t RXFIFO10LH; + }; + }; + union { + __IO uint16_t RXFIFO10H; + struct { + __IO uint8_t RXFIFO10HL; + __IO uint8_t RXFIFO10HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO11; + stc_hsspi_rxfifo11_field_t RXFIFO11_f; + struct { + union { + __IO uint16_t RXFIFO11L; + struct { + __IO uint8_t RXFIFO11LL; + __IO uint8_t RXFIFO11LH; + }; + }; + union { + __IO uint16_t RXFIFO11H; + struct { + __IO uint8_t RXFIFO11HL; + __IO uint8_t RXFIFO11HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO12; + stc_hsspi_rxfifo12_field_t RXFIFO12_f; + struct { + union { + __IO uint16_t RXFIFO12L; + struct { + __IO uint8_t RXFIFO12LL; + __IO uint8_t RXFIFO12LH; + }; + }; + union { + __IO uint16_t RXFIFO12H; + struct { + __IO uint8_t RXFIFO12HL; + __IO uint8_t RXFIFO12HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO13; + stc_hsspi_rxfifo13_field_t RXFIFO13_f; + struct { + union { + __IO uint16_t RXFIFO13L; + struct { + __IO uint8_t RXFIFO13LL; + __IO uint8_t RXFIFO13LH; + }; + }; + union { + __IO uint16_t RXFIFO13H; + struct { + __IO uint8_t RXFIFO13HL; + __IO uint8_t RXFIFO13HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO14; + stc_hsspi_rxfifo14_field_t RXFIFO14_f; + struct { + union { + __IO uint16_t RXFIFO14L; + struct { + __IO uint8_t RXFIFO14LL; + __IO uint8_t RXFIFO14LH; + }; + }; + union { + __IO uint16_t RXFIFO14H; + struct { + __IO uint8_t RXFIFO14HL; + __IO uint8_t RXFIFO14HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO15; + stc_hsspi_rxfifo15_field_t RXFIFO15_f; + struct { + union { + __IO uint16_t RXFIFO15L; + struct { + __IO uint8_t RXFIFO15LL; + __IO uint8_t RXFIFO15LH; + }; + }; + union { + __IO uint16_t RXFIFO15H; + struct { + __IO uint8_t RXFIFO15HL; + __IO uint8_t RXFIFO15HH; + }; + }; + }; + }; + union { + __IO uint32_t CSCFG; + stc_hsspi_cscfg_field_t CSCFG_f; + struct { + union { + __IO uint16_t CSCFGL; + struct { + __IO uint8_t CSCFGLL; + __IO uint8_t CSCFGLH; + }; + }; + union { + __IO uint16_t CSCFGH; + struct { + __IO uint8_t CSCFGHL; + __IO uint8_t CSCFGHH; + }; + }; + }; + }; + union { + __IO uint32_t CSITIME; + stc_hsspi_csitime_field_t CSITIME_f; + struct { + union { + __IO uint16_t CSITIMEL; + struct { + __IO uint8_t CSITIMELL; + __IO uint8_t CSITIMELH; + }; + }; + union { + __IO uint16_t CSITIMEH; + struct { + __IO uint8_t CSITIMEHL; + __IO uint8_t CSITIMEHH; + }; + }; + }; + }; + union { + __IO uint32_t CSAEXT; + stc_hsspi_csaext_field_t CSAEXT_f; + struct { + union { + __IO uint16_t CSAEXTL; + struct { + __IO uint8_t CSAEXTLL; + __IO uint8_t CSAEXTLH; + }; + }; + union { + __IO uint16_t CSAEXTH; + struct { + __IO uint8_t CSAEXTHL; + __IO uint8_t CSAEXTHH; + }; + }; + }; + }; + union { + __IO uint16_t RDCSDC0; + stc_hsspi_rdcsdc0_field_t RDCSDC0_f; + struct { + __IO uint8_t RDCSDC0L; + __IO uint8_t RDCSDC0H; + }; + }; + union { + __IO uint16_t RDCSDC1; + stc_hsspi_rdcsdc1_field_t RDCSDC1_f; + struct { + __IO uint8_t RDCSDC1L; + __IO uint8_t RDCSDC1H; + }; + }; + union { + __IO uint16_t RDCSDC2; + stc_hsspi_rdcsdc2_field_t RDCSDC2_f; + struct { + __IO uint8_t RDCSDC2L; + __IO uint8_t RDCSDC2H; + }; + }; + union { + __IO uint16_t RDCSDC3; + stc_hsspi_rdcsdc3_field_t RDCSDC3_f; + struct { + __IO uint8_t RDCSDC3L; + __IO uint8_t RDCSDC3H; + }; + }; + union { + __IO uint16_t RDCSDC4; + stc_hsspi_rdcsdc4_field_t RDCSDC4_f; + struct { + __IO uint8_t RDCSDC4L; + __IO uint8_t RDCSDC4H; + }; + }; + union { + __IO uint16_t RDCSDC5; + stc_hsspi_rdcsdc5_field_t RDCSDC5_f; + struct { + __IO uint8_t RDCSDC5L; + __IO uint8_t RDCSDC5H; + }; + }; + union { + __IO uint16_t RDCSDC6; + stc_hsspi_rdcsdc6_field_t RDCSDC6_f; + struct { + __IO uint8_t RDCSDC6L; + __IO uint8_t RDCSDC6H; + }; + }; + union { + __IO uint16_t RDCSDC7; + stc_hsspi_rdcsdc7_field_t RDCSDC7_f; + struct { + __IO uint8_t RDCSDC7L; + __IO uint8_t RDCSDC7H; + }; + }; + union { + __IO uint16_t WRCSDC0; + stc_hsspi_wrcsdc0_field_t WRCSDC0_f; + struct { + __IO uint8_t WRCSDC0L; + __IO uint8_t WRCSDC0H; + }; + }; + union { + __IO uint16_t WRCSDC1; + stc_hsspi_wrcsdc1_field_t WRCSDC1_f; + struct { + __IO uint8_t WRCSDC1L; + __IO uint8_t WRCSDC1H; + }; + }; + union { + __IO uint16_t WRCSDC2; + stc_hsspi_wrcsdc2_field_t WRCSDC2_f; + struct { + __IO uint8_t WRCSDC2L; + __IO uint8_t WRCSDC2H; + }; + }; + union { + __IO uint16_t WRCSDC3; + stc_hsspi_wrcsdc3_field_t WRCSDC3_f; + struct { + __IO uint8_t WRCSDC3L; + __IO uint8_t WRCSDC3H; + }; + }; + union { + __IO uint16_t WRCSDC4; + stc_hsspi_wrcsdc4_field_t WRCSDC4_f; + struct { + __IO uint8_t WRCSDC4L; + __IO uint8_t WRCSDC4H; + }; + }; + union { + __IO uint16_t WRCSDC5; + stc_hsspi_wrcsdc5_field_t WRCSDC5_f; + struct { + __IO uint8_t WRCSDC5L; + __IO uint8_t WRCSDC5H; + }; + }; + union { + __IO uint16_t WRCSDC6; + stc_hsspi_wrcsdc6_field_t WRCSDC6_f; + struct { + __IO uint8_t WRCSDC6L; + __IO uint8_t WRCSDC6H; + }; + }; + union { + __IO uint16_t WRCSDC7; + stc_hsspi_wrcsdc7_field_t WRCSDC7_f; + struct { + __IO uint8_t WRCSDC7L; + __IO uint8_t WRCSDC7H; + }; + }; + union { + __IO uint32_t MID; + stc_hsspi_mid_field_t MID_f; + struct { + union { + __IO uint16_t MIDL; + struct { + __IO uint8_t MIDLL; + __IO uint8_t MIDLH; + }; + }; + union { + __IO uint16_t MIDH; + struct { + __IO uint8_t MIDHL; + __IO uint8_t MIDHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[768]; + union { + __IO uint8_t QDCLKR; + stc_hsspi_qdclkr_field_t QDCLKR_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint8_t DBCNT; + stc_hsspi_dbcnt_field_t DBCNT_f; + }; +} FM_HSSPI_TypeDef, FM4_HSSPI_TypeDef; + +/******************************************************************************* +* HWWDT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t WDG_LDR; + struct { + union { + __IO uint16_t WDG_LDRL; + struct { + __IO uint8_t WDG_LDRLL; + __IO uint8_t WDG_LDRLH; + }; + }; + union { + __IO uint16_t WDG_LDRH; + struct { + __IO uint8_t WDG_LDRHL; + __IO uint8_t WDG_LDRHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_VLR; + struct { + union { + __IO uint16_t WDG_VLRL; + struct { + __IO uint8_t WDG_VLRLL; + __IO uint8_t WDG_VLRLH; + }; + }; + union { + __IO uint16_t WDG_VLRH; + struct { + __IO uint8_t WDG_VLRHL; + __IO uint8_t WDG_VLRHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_CTL; + stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; + struct { + union { + __IO uint16_t WDG_CTLL; + struct { + __IO uint8_t WDG_CTLLL; + __IO uint8_t WDG_CTLLH; + }; + }; + union { + __IO uint16_t WDG_CTLH; + struct { + __IO uint8_t WDG_CTLHL; + __IO uint8_t WDG_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_ICL; + struct { + union { + __IO uint16_t WDG_ICLL; + struct { + __IO uint8_t WDG_ICLLL; + __IO uint8_t WDG_ICLLH; + }; + }; + union { + __IO uint16_t WDG_ICLH; + struct { + __IO uint8_t WDG_ICLHL; + __IO uint8_t WDG_ICLHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_RIS; + stc_hwwdt_wdg_ris_field_t WDG_RIS_f; + struct { + union { + __IO uint16_t WDG_RISL; + struct { + __IO uint8_t WDG_RISLL; + __IO uint8_t WDG_RISLH; + }; + }; + union { + __IO uint16_t WDG_RISH; + struct { + __IO uint8_t WDG_RISHL; + __IO uint8_t WDG_RISHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[3052]; + union { + __IO uint32_t WDG_LCK; + struct { + union { + __IO uint16_t WDG_LCKL; + struct { + __IO uint8_t WDG_LCKLL; + __IO uint8_t WDG_LCKLH; + }; + }; + union { + __IO uint16_t WDG_LCKH; + struct { + __IO uint8_t WDG_LCKHL; + __IO uint8_t WDG_LCKHH; + }; + }; + }; + }; +} FM_HWWDT_TypeDef, FM4_HWWDT_TypeDef; + +/******************************************************************************* +* I2S_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t RXFDAT; + stc_i2s_rxfdat_field_t RXFDAT_f; + struct { + union { + __IO uint16_t RXFDATL; + struct { + __IO uint8_t RXFDATLL; + __IO uint8_t RXFDATLH; + }; + }; + union { + __IO uint16_t RXFDATH; + struct { + __IO uint8_t RXFDATHL; + __IO uint8_t RXFDATHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFDAT; + stc_i2s_txfdat_field_t TXFDAT_f; + struct { + union { + __IO uint16_t TXFDATL; + struct { + __IO uint8_t TXFDATLL; + __IO uint8_t TXFDATLH; + }; + }; + union { + __IO uint16_t TXFDATH; + struct { + __IO uint8_t TXFDATHL; + __IO uint8_t TXFDATHH; + }; + }; + }; + }; + union { + __IO uint32_t CNTREG; + stc_i2s_cntreg_field_t CNTREG_f; + struct { + union { + __IO uint16_t CNTREGL; + struct { + __IO uint8_t CNTREGLL; + __IO uint8_t CNTREGLH; + }; + }; + union { + __IO uint16_t CNTREGH; + struct { + __IO uint8_t CNTREGHL; + __IO uint8_t CNTREGHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR0REG; + stc_i2s_mcr0reg_field_t MCR0REG_f; + struct { + union { + __IO uint16_t MCR0REGL; + struct { + __IO uint8_t MCR0REGLL; + __IO uint8_t MCR0REGLH; + }; + }; + union { + __IO uint16_t MCR0REGH; + struct { + __IO uint8_t MCR0REGHL; + __IO uint8_t MCR0REGHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR1REG; + stc_i2s_mcr1reg_field_t MCR1REG_f; + struct { + union { + __IO uint16_t MCR1REGL; + struct { + __IO uint8_t MCR1REGLL; + __IO uint8_t MCR1REGLH; + }; + }; + union { + __IO uint16_t MCR1REGH; + struct { + __IO uint8_t MCR1REGHL; + __IO uint8_t MCR1REGHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR2REG; + stc_i2s_mcr2reg_field_t MCR2REG_f; + struct { + union { + __IO uint16_t MCR2REGL; + struct { + __IO uint8_t MCR2REGLL; + __IO uint8_t MCR2REGLH; + }; + }; + union { + __IO uint16_t MCR2REGH; + struct { + __IO uint8_t MCR2REGHL; + __IO uint8_t MCR2REGHH; + }; + }; + }; + }; + union { + __IO uint32_t OPRREG; + stc_i2s_oprreg_field_t OPRREG_f; + struct { + union { + __IO uint16_t OPRREGL; + struct { + __IO uint8_t OPRREGLL; + __IO uint8_t OPRREGLH; + }; + }; + union { + __IO uint16_t OPRREGH; + struct { + __IO uint8_t OPRREGHL; + __IO uint8_t OPRREGHH; + }; + }; + }; + }; + union { + __IO uint32_t SRST; + stc_i2s_srst_field_t SRST_f; + struct { + union { + __IO uint16_t SRSTL; + struct { + __IO uint8_t SRSTLL; + __IO uint8_t SRSTLH; + }; + }; + union { + __IO uint16_t SRSTH; + struct { + __IO uint8_t SRSTHL; + __IO uint8_t SRSTHH; + }; + }; + }; + }; + union { + __IO uint32_t INTCNT; + stc_i2s_intcnt_field_t INTCNT_f; + struct { + union { + __IO uint16_t INTCNTL; + struct { + __IO uint8_t INTCNTLL; + __IO uint8_t INTCNTLH; + }; + }; + union { + __IO uint16_t INTCNTH; + struct { + __IO uint8_t INTCNTHL; + __IO uint8_t INTCNTHH; + }; + }; + }; + }; + union { + __IO uint32_t STATUS; + stc_i2s_status_field_t STATUS_f; + struct { + union { + __IO uint16_t STATUSL; + struct { + __IO uint8_t STATUSLL; + __IO uint8_t STATUSLH; + }; + }; + union { + __IO uint16_t STATUSH; + struct { + __IO uint8_t STATUSHL; + __IO uint8_t STATUSHH; + }; + }; + }; + }; + union { + __IO uint32_t DMAACT; + stc_i2s_dmaact_field_t DMAACT_f; + struct { + union { + __IO uint16_t DMAACTL; + struct { + __IO uint8_t DMAACTLL; + __IO uint8_t DMAACTLH; + }; + }; + union { + __IO uint16_t DMAACTH; + struct { + __IO uint8_t DMAACTHL; + __IO uint8_t DMAACTHH; + }; + }; + }; + }; + union { + __IO uint32_t TSTREG; + stc_i2s_tstreg_field_t TSTREG_f; + struct { + union { + __IO uint16_t TSTREGL; + struct { + __IO uint8_t TSTREGLL; + __IO uint8_t TSTREGLH; + }; + }; + union { + __IO uint16_t TSTREGH; + struct { + __IO uint8_t TSTREGHL; + __IO uint8_t TSTREGHH; + }; + }; + }; + }; +} FM_I2S_TypeDef, FM4_I2S_TypeDef; + +/******************************************************************************* +* I2SPRE_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t ICCR; + stc_i2spre_iccr_field_t ICCR_f; + struct { + union { + __IO uint16_t ICCRL; + struct { + __IO uint8_t ICCRLL; + __IO uint8_t ICCRLH; + }; + }; + union { + __IO uint16_t ICCRH; + struct { + __IO uint8_t ICCRHL; + __IO uint8_t ICCRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR1; + stc_i2spre_ipcr1_field_t IPCR1_f; + struct { + union { + __IO uint16_t IPCR1L; + struct { + __IO uint8_t IPCR1LL; + __IO uint8_t IPCR1LH; + }; + }; + union { + __IO uint16_t IPCR1H; + struct { + __IO uint8_t IPCR1HL; + __IO uint8_t IPCR1HH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR2; + stc_i2spre_ipcr2_field_t IPCR2_f; + struct { + union { + __IO uint16_t IPCR2L; + struct { + __IO uint8_t IPCR2LL; + __IO uint8_t IPCR2LH; + }; + }; + union { + __IO uint16_t IPCR2H; + struct { + __IO uint8_t IPCR2HL; + __IO uint8_t IPCR2HH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR3; + stc_i2spre_ipcr3_field_t IPCR3_f; + struct { + union { + __IO uint16_t IPCR3L; + struct { + __IO uint8_t IPCR3LL; + __IO uint8_t IPCR3LH; + }; + }; + union { + __IO uint16_t IPCR3H; + struct { + __IO uint8_t IPCR3HL; + __IO uint8_t IPCR3HH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR4; + stc_i2spre_ipcr4_field_t IPCR4_f; + struct { + union { + __IO uint16_t IPCR4L; + struct { + __IO uint8_t IPCR4LL; + __IO uint8_t IPCR4LH; + }; + }; + union { + __IO uint16_t IPCR4H; + struct { + __IO uint8_t IPCR4HL; + __IO uint8_t IPCR4HH; + }; + }; + }; + }; + union { + __IO uint32_t IP_STR; + stc_i2spre_ip_str_field_t IP_STR_f; + struct { + union { + __IO uint16_t IP_STRL; + struct { + __IO uint8_t IP_STRLL; + __IO uint8_t IP_STRLH; + }; + }; + union { + __IO uint16_t IP_STRH; + struct { + __IO uint8_t IP_STRHL; + __IO uint8_t IP_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPINT_ENR; + stc_i2spre_ipint_enr_field_t IPINT_ENR_f; + struct { + union { + __IO uint16_t IPINT_ENRL; + struct { + __IO uint8_t IPINT_ENRLL; + __IO uint8_t IPINT_ENRLH; + }; + }; + union { + __IO uint16_t IPINT_ENRH; + struct { + __IO uint8_t IPINT_ENRHL; + __IO uint8_t IPINT_ENRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPINT_CLR; + stc_i2spre_ipint_clr_field_t IPINT_CLR_f; + struct { + union { + __IO uint16_t IPINT_CLRL; + struct { + __IO uint8_t IPINT_CLRLL; + __IO uint8_t IPINT_CLRLH; + }; + }; + union { + __IO uint16_t IPINT_CLRH; + struct { + __IO uint8_t IPINT_CLRHL; + __IO uint8_t IPINT_CLRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPINT_STR; + stc_i2spre_ipint_str_field_t IPINT_STR_f; + struct { + union { + __IO uint16_t IPINT_STRL; + struct { + __IO uint8_t IPINT_STRLL; + __IO uint8_t IPINT_STRLH; + }; + }; + union { + __IO uint16_t IPINT_STRH; + struct { + __IO uint8_t IPINT_STRHL; + __IO uint8_t IPINT_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR5; + stc_i2spre_ipcr5_field_t IPCR5_f; + struct { + union { + __IO uint16_t IPCR5L; + struct { + __IO uint8_t IPCR5LL; + __IO uint8_t IPCR5LH; + }; + }; + union { + __IO uint16_t IPCR5H; + struct { + __IO uint8_t IPCR5HL; + __IO uint8_t IPCR5HH; + }; + }; + }; + }; +} FM_I2SPRE_TypeDef, FM4_I2SPRE_TypeDef; + +/******************************************************************************* +* INTREQ_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DRQSEL; + stc_intreq_drqsel_field_t DRQSEL_f; + struct { + union { + __IO uint16_t DRQSELL; + struct { + __IO uint8_t DRQSELLL; + __IO uint8_t DRQSELLH; + }; + }; + union { + __IO uint16_t DRQSELH; + struct { + __IO uint8_t DRQSELHL; + __IO uint8_t DRQSELHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[12]; + union { + __IO uint8_t ODDPKS; + stc_intreq_oddpks_field_t ODDPKS_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t ODDPKS1; + stc_intreq_oddpks1_field_t ODDPKS1_f; + }; + __IO uint8_t RESERVED2[251]; + union { + __IO uint32_t IRQ003SEL; + stc_intreq_irq003sel_field_t IRQ003SEL_f; + struct { + union { + __IO uint16_t IRQ003SELL; + struct { + __IO uint8_t IRQ003SELLL; + __IO uint8_t IRQ003SELLH; + }; + }; + union { + __IO uint16_t IRQ003SELH; + struct { + __IO uint8_t IRQ003SELHL; + __IO uint8_t IRQ003SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ004SEL; + stc_intreq_irq004sel_field_t IRQ004SEL_f; + struct { + union { + __IO uint16_t IRQ004SELL; + struct { + __IO uint8_t IRQ004SELLL; + __IO uint8_t IRQ004SELLH; + }; + }; + union { + __IO uint16_t IRQ004SELH; + struct { + __IO uint8_t IRQ004SELHL; + __IO uint8_t IRQ004SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ005SEL; + stc_intreq_irq005sel_field_t IRQ005SEL_f; + struct { + union { + __IO uint16_t IRQ005SELL; + struct { + __IO uint8_t IRQ005SELLL; + __IO uint8_t IRQ005SELLH; + }; + }; + union { + __IO uint16_t IRQ005SELH; + struct { + __IO uint8_t IRQ005SELHL; + __IO uint8_t IRQ005SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ006SEL; + stc_intreq_irq006sel_field_t IRQ006SEL_f; + struct { + union { + __IO uint16_t IRQ006SELL; + struct { + __IO uint8_t IRQ006SELLL; + __IO uint8_t IRQ006SELLH; + }; + }; + union { + __IO uint16_t IRQ006SELH; + struct { + __IO uint8_t IRQ006SELHL; + __IO uint8_t IRQ006SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ007SEL; + stc_intreq_irq007sel_field_t IRQ007SEL_f; + struct { + union { + __IO uint16_t IRQ007SELL; + struct { + __IO uint8_t IRQ007SELLL; + __IO uint8_t IRQ007SELLH; + }; + }; + union { + __IO uint16_t IRQ007SELH; + struct { + __IO uint8_t IRQ007SELHL; + __IO uint8_t IRQ007SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ008SEL; + stc_intreq_irq008sel_field_t IRQ008SEL_f; + struct { + union { + __IO uint16_t IRQ008SELL; + struct { + __IO uint8_t IRQ008SELLL; + __IO uint8_t IRQ008SELLH; + }; + }; + union { + __IO uint16_t IRQ008SELH; + struct { + __IO uint8_t IRQ008SELHL; + __IO uint8_t IRQ008SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ009SEL; + stc_intreq_irq009sel_field_t IRQ009SEL_f; + struct { + union { + __IO uint16_t IRQ009SELL; + struct { + __IO uint8_t IRQ009SELLL; + __IO uint8_t IRQ009SELLH; + }; + }; + union { + __IO uint16_t IRQ009SELH; + struct { + __IO uint8_t IRQ009SELHL; + __IO uint8_t IRQ009SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ010SEL; + stc_intreq_irq010sel_field_t IRQ010SEL_f; + struct { + union { + __IO uint16_t IRQ010SELL; + struct { + __IO uint8_t IRQ010SELLL; + __IO uint8_t IRQ010SELLH; + }; + }; + union { + __IO uint16_t IRQ010SELH; + struct { + __IO uint8_t IRQ010SELHL; + __IO uint8_t IRQ010SELHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[208]; + union { + __IO uint32_t EXC02MON; + stc_intreq_exc02mon_field_t EXC02MON_f; + struct { + union { + __IO uint16_t EXC02MONL; + struct { + __IO uint8_t EXC02MONLL; + __IO uint8_t EXC02MONLH; + }; + }; + union { + __IO uint16_t EXC02MONH; + struct { + __IO uint8_t EXC02MONHL; + __IO uint8_t EXC02MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ000MON; + stc_intreq_irq000mon_field_t IRQ000MON_f; + struct { + union { + __IO uint16_t IRQ000MONL; + struct { + __IO uint8_t IRQ000MONLL; + __IO uint8_t IRQ000MONLH; + }; + }; + union { + __IO uint16_t IRQ000MONH; + struct { + __IO uint8_t IRQ000MONHL; + __IO uint8_t IRQ000MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ001MON; + stc_intreq_irq001mon_field_t IRQ001MON_f; + struct { + union { + __IO uint16_t IRQ001MONL; + struct { + __IO uint8_t IRQ001MONLL; + __IO uint8_t IRQ001MONLH; + }; + }; + union { + __IO uint16_t IRQ001MONH; + struct { + __IO uint8_t IRQ001MONHL; + __IO uint8_t IRQ001MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ002MON; + stc_intreq_irq002mon_field_t IRQ002MON_f; + struct { + union { + __IO uint16_t IRQ002MONL; + struct { + __IO uint8_t IRQ002MONLL; + __IO uint8_t IRQ002MONLH; + }; + }; + union { + __IO uint16_t IRQ002MONH; + struct { + __IO uint8_t IRQ002MONHL; + __IO uint8_t IRQ002MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ003MON; + stc_intreq_irq003mon_field_t IRQ003MON_f; + struct { + union { + __IO uint16_t IRQ003MONL; + struct { + __IO uint8_t IRQ003MONLL; + __IO uint8_t IRQ003MONLH; + }; + }; + union { + __IO uint16_t IRQ003MONH; + struct { + __IO uint8_t IRQ003MONHL; + __IO uint8_t IRQ003MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ004MON; + stc_intreq_irq004mon_field_t IRQ004MON_f; + struct { + union { + __IO uint16_t IRQ004MONL; + struct { + __IO uint8_t IRQ004MONLL; + __IO uint8_t IRQ004MONLH; + }; + }; + union { + __IO uint16_t IRQ004MONH; + struct { + __IO uint8_t IRQ004MONHL; + __IO uint8_t IRQ004MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ005MON; + stc_intreq_irq005mon_field_t IRQ005MON_f; + struct { + union { + __IO uint16_t IRQ005MONL; + struct { + __IO uint8_t IRQ005MONLL; + __IO uint8_t IRQ005MONLH; + }; + }; + union { + __IO uint16_t IRQ005MONH; + struct { + __IO uint8_t IRQ005MONHL; + __IO uint8_t IRQ005MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ006MON; + stc_intreq_irq006mon_field_t IRQ006MON_f; + struct { + union { + __IO uint16_t IRQ006MONL; + struct { + __IO uint8_t IRQ006MONLL; + __IO uint8_t IRQ006MONLH; + }; + }; + union { + __IO uint16_t IRQ006MONH; + struct { + __IO uint8_t IRQ006MONHL; + __IO uint8_t IRQ006MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ007MON; + stc_intreq_irq007mon_field_t IRQ007MON_f; + struct { + union { + __IO uint16_t IRQ007MONL; + struct { + __IO uint8_t IRQ007MONLL; + __IO uint8_t IRQ007MONLH; + }; + }; + union { + __IO uint16_t IRQ007MONH; + struct { + __IO uint8_t IRQ007MONHL; + __IO uint8_t IRQ007MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ008MON; + stc_intreq_irq008mon_field_t IRQ008MON_f; + struct { + union { + __IO uint16_t IRQ008MONL; + struct { + __IO uint8_t IRQ008MONLL; + __IO uint8_t IRQ008MONLH; + }; + }; + union { + __IO uint16_t IRQ008MONH; + struct { + __IO uint8_t IRQ008MONHL; + __IO uint8_t IRQ008MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ009MON; + stc_intreq_irq009mon_field_t IRQ009MON_f; + struct { + union { + __IO uint16_t IRQ009MONL; + struct { + __IO uint8_t IRQ009MONLL; + __IO uint8_t IRQ009MONLH; + }; + }; + union { + __IO uint16_t IRQ009MONH; + struct { + __IO uint8_t IRQ009MONHL; + __IO uint8_t IRQ009MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ010MON; + stc_intreq_irq010mon_field_t IRQ010MON_f; + struct { + union { + __IO uint16_t IRQ010MONL; + struct { + __IO uint8_t IRQ010MONLL; + __IO uint8_t IRQ010MONLH; + }; + }; + union { + __IO uint16_t IRQ010MONH; + struct { + __IO uint8_t IRQ010MONHL; + __IO uint8_t IRQ010MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ011MON; + stc_intreq_irq011mon_field_t IRQ011MON_f; + struct { + union { + __IO uint16_t IRQ011MONL; + struct { + __IO uint8_t IRQ011MONLL; + __IO uint8_t IRQ011MONLH; + }; + }; + union { + __IO uint16_t IRQ011MONH; + struct { + __IO uint8_t IRQ011MONHL; + __IO uint8_t IRQ011MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ012MON; + stc_intreq_irq012mon_field_t IRQ012MON_f; + struct { + union { + __IO uint16_t IRQ012MONL; + struct { + __IO uint8_t IRQ012MONLL; + __IO uint8_t IRQ012MONLH; + }; + }; + union { + __IO uint16_t IRQ012MONH; + struct { + __IO uint8_t IRQ012MONHL; + __IO uint8_t IRQ012MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ013MON; + stc_intreq_irq013mon_field_t IRQ013MON_f; + struct { + union { + __IO uint16_t IRQ013MONL; + struct { + __IO uint8_t IRQ013MONLL; + __IO uint8_t IRQ013MONLH; + }; + }; + union { + __IO uint16_t IRQ013MONH; + struct { + __IO uint8_t IRQ013MONHL; + __IO uint8_t IRQ013MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ014MON; + stc_intreq_irq014mon_field_t IRQ014MON_f; + struct { + union { + __IO uint16_t IRQ014MONL; + struct { + __IO uint8_t IRQ014MONLL; + __IO uint8_t IRQ014MONLH; + }; + }; + union { + __IO uint16_t IRQ014MONH; + struct { + __IO uint8_t IRQ014MONHL; + __IO uint8_t IRQ014MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ015MON; + stc_intreq_irq015mon_field_t IRQ015MON_f; + struct { + union { + __IO uint16_t IRQ015MONL; + struct { + __IO uint8_t IRQ015MONLL; + __IO uint8_t IRQ015MONLH; + }; + }; + union { + __IO uint16_t IRQ015MONH; + struct { + __IO uint8_t IRQ015MONHL; + __IO uint8_t IRQ015MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ016MON; + stc_intreq_irq016mon_field_t IRQ016MON_f; + struct { + union { + __IO uint16_t IRQ016MONL; + struct { + __IO uint8_t IRQ016MONLL; + __IO uint8_t IRQ016MONLH; + }; + }; + union { + __IO uint16_t IRQ016MONH; + struct { + __IO uint8_t IRQ016MONHL; + __IO uint8_t IRQ016MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ017MON; + stc_intreq_irq017mon_field_t IRQ017MON_f; + struct { + union { + __IO uint16_t IRQ017MONL; + struct { + __IO uint8_t IRQ017MONLL; + __IO uint8_t IRQ017MONLH; + }; + }; + union { + __IO uint16_t IRQ017MONH; + struct { + __IO uint8_t IRQ017MONHL; + __IO uint8_t IRQ017MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ018MON; + stc_intreq_irq018mon_field_t IRQ018MON_f; + struct { + union { + __IO uint16_t IRQ018MONL; + struct { + __IO uint8_t IRQ018MONLL; + __IO uint8_t IRQ018MONLH; + }; + }; + union { + __IO uint16_t IRQ018MONH; + struct { + __IO uint8_t IRQ018MONHL; + __IO uint8_t IRQ018MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ019MON; + stc_intreq_irq019mon_field_t IRQ019MON_f; + struct { + union { + __IO uint16_t IRQ019MONL; + struct { + __IO uint8_t IRQ019MONLL; + __IO uint8_t IRQ019MONLH; + }; + }; + union { + __IO uint16_t IRQ019MONH; + struct { + __IO uint8_t IRQ019MONHL; + __IO uint8_t IRQ019MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ020MON; + stc_intreq_irq020mon_field_t IRQ020MON_f; + struct { + union { + __IO uint16_t IRQ020MONL; + struct { + __IO uint8_t IRQ020MONLL; + __IO uint8_t IRQ020MONLH; + }; + }; + union { + __IO uint16_t IRQ020MONH; + struct { + __IO uint8_t IRQ020MONHL; + __IO uint8_t IRQ020MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ021MON; + stc_intreq_irq021mon_field_t IRQ021MON_f; + struct { + union { + __IO uint16_t IRQ021MONL; + struct { + __IO uint8_t IRQ021MONLL; + __IO uint8_t IRQ021MONLH; + }; + }; + union { + __IO uint16_t IRQ021MONH; + struct { + __IO uint8_t IRQ021MONHL; + __IO uint8_t IRQ021MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ022MON; + stc_intreq_irq022mon_field_t IRQ022MON_f; + struct { + union { + __IO uint16_t IRQ022MONL; + struct { + __IO uint8_t IRQ022MONLL; + __IO uint8_t IRQ022MONLH; + }; + }; + union { + __IO uint16_t IRQ022MONH; + struct { + __IO uint8_t IRQ022MONHL; + __IO uint8_t IRQ022MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ023MON; + stc_intreq_irq023mon_field_t IRQ023MON_f; + struct { + union { + __IO uint16_t IRQ023MONL; + struct { + __IO uint8_t IRQ023MONLL; + __IO uint8_t IRQ023MONLH; + }; + }; + union { + __IO uint16_t IRQ023MONH; + struct { + __IO uint8_t IRQ023MONHL; + __IO uint8_t IRQ023MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ024MON; + stc_intreq_irq024mon_field_t IRQ024MON_f; + struct { + union { + __IO uint16_t IRQ024MONL; + struct { + __IO uint8_t IRQ024MONLL; + __IO uint8_t IRQ024MONLH; + }; + }; + union { + __IO uint16_t IRQ024MONH; + struct { + __IO uint8_t IRQ024MONHL; + __IO uint8_t IRQ024MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ025MON; + stc_intreq_irq025mon_field_t IRQ025MON_f; + struct { + union { + __IO uint16_t IRQ025MONL; + struct { + __IO uint8_t IRQ025MONLL; + __IO uint8_t IRQ025MONLH; + }; + }; + union { + __IO uint16_t IRQ025MONH; + struct { + __IO uint8_t IRQ025MONHL; + __IO uint8_t IRQ025MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ026MON; + stc_intreq_irq026mon_field_t IRQ026MON_f; + struct { + union { + __IO uint16_t IRQ026MONL; + struct { + __IO uint8_t IRQ026MONLL; + __IO uint8_t IRQ026MONLH; + }; + }; + union { + __IO uint16_t IRQ026MONH; + struct { + __IO uint8_t IRQ026MONHL; + __IO uint8_t IRQ026MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ027MON; + stc_intreq_irq027mon_field_t IRQ027MON_f; + struct { + union { + __IO uint16_t IRQ027MONL; + struct { + __IO uint8_t IRQ027MONLL; + __IO uint8_t IRQ027MONLH; + }; + }; + union { + __IO uint16_t IRQ027MONH; + struct { + __IO uint8_t IRQ027MONHL; + __IO uint8_t IRQ027MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ028MON; + stc_intreq_irq028mon_field_t IRQ028MON_f; + struct { + union { + __IO uint16_t IRQ028MONL; + struct { + __IO uint8_t IRQ028MONLL; + __IO uint8_t IRQ028MONLH; + }; + }; + union { + __IO uint16_t IRQ028MONH; + struct { + __IO uint8_t IRQ028MONHL; + __IO uint8_t IRQ028MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ029MON; + stc_intreq_irq029mon_field_t IRQ029MON_f; + struct { + union { + __IO uint16_t IRQ029MONL; + struct { + __IO uint8_t IRQ029MONLL; + __IO uint8_t IRQ029MONLH; + }; + }; + union { + __IO uint16_t IRQ029MONH; + struct { + __IO uint8_t IRQ029MONHL; + __IO uint8_t IRQ029MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ030MON; + stc_intreq_irq030mon_field_t IRQ030MON_f; + struct { + union { + __IO uint16_t IRQ030MONL; + struct { + __IO uint8_t IRQ030MONLL; + __IO uint8_t IRQ030MONLH; + }; + }; + union { + __IO uint16_t IRQ030MONH; + struct { + __IO uint8_t IRQ030MONHL; + __IO uint8_t IRQ030MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ031MON; + stc_intreq_irq031mon_field_t IRQ031MON_f; + struct { + union { + __IO uint16_t IRQ031MONL; + struct { + __IO uint8_t IRQ031MONLL; + __IO uint8_t IRQ031MONLH; + }; + }; + union { + __IO uint16_t IRQ031MONH; + struct { + __IO uint8_t IRQ031MONHL; + __IO uint8_t IRQ031MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ032MON; + stc_intreq_irq032mon_field_t IRQ032MON_f; + struct { + union { + __IO uint16_t IRQ032MONL; + struct { + __IO uint8_t IRQ032MONLL; + __IO uint8_t IRQ032MONLH; + }; + }; + union { + __IO uint16_t IRQ032MONH; + struct { + __IO uint8_t IRQ032MONHL; + __IO uint8_t IRQ032MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ033MON; + stc_intreq_irq033mon_field_t IRQ033MON_f; + struct { + union { + __IO uint16_t IRQ033MONL; + struct { + __IO uint8_t IRQ033MONLL; + __IO uint8_t IRQ033MONLH; + }; + }; + union { + __IO uint16_t IRQ033MONH; + struct { + __IO uint8_t IRQ033MONHL; + __IO uint8_t IRQ033MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ034MON; + stc_intreq_irq034mon_field_t IRQ034MON_f; + struct { + union { + __IO uint16_t IRQ034MONL; + struct { + __IO uint8_t IRQ034MONLL; + __IO uint8_t IRQ034MONLH; + }; + }; + union { + __IO uint16_t IRQ034MONH; + struct { + __IO uint8_t IRQ034MONHL; + __IO uint8_t IRQ034MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ035MON; + stc_intreq_irq035mon_field_t IRQ035MON_f; + struct { + union { + __IO uint16_t IRQ035MONL; + struct { + __IO uint8_t IRQ035MONLL; + __IO uint8_t IRQ035MONLH; + }; + }; + union { + __IO uint16_t IRQ035MONH; + struct { + __IO uint8_t IRQ035MONHL; + __IO uint8_t IRQ035MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ036MON; + stc_intreq_irq036mon_field_t IRQ036MON_f; + struct { + union { + __IO uint16_t IRQ036MONL; + struct { + __IO uint8_t IRQ036MONLL; + __IO uint8_t IRQ036MONLH; + }; + }; + union { + __IO uint16_t IRQ036MONH; + struct { + __IO uint8_t IRQ036MONHL; + __IO uint8_t IRQ036MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ037MON; + stc_intreq_irq037mon_field_t IRQ037MON_f; + struct { + union { + __IO uint16_t IRQ037MONL; + struct { + __IO uint8_t IRQ037MONLL; + __IO uint8_t IRQ037MONLH; + }; + }; + union { + __IO uint16_t IRQ037MONH; + struct { + __IO uint8_t IRQ037MONHL; + __IO uint8_t IRQ037MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ038MON; + stc_intreq_irq038mon_field_t IRQ038MON_f; + struct { + union { + __IO uint16_t IRQ038MONL; + struct { + __IO uint8_t IRQ038MONLL; + __IO uint8_t IRQ038MONLH; + }; + }; + union { + __IO uint16_t IRQ038MONH; + struct { + __IO uint8_t IRQ038MONHL; + __IO uint8_t IRQ038MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ039MON; + stc_intreq_irq039mon_field_t IRQ039MON_f; + struct { + union { + __IO uint16_t IRQ039MONL; + struct { + __IO uint8_t IRQ039MONLL; + __IO uint8_t IRQ039MONLH; + }; + }; + union { + __IO uint16_t IRQ039MONH; + struct { + __IO uint8_t IRQ039MONHL; + __IO uint8_t IRQ039MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ040MON; + stc_intreq_irq040mon_field_t IRQ040MON_f; + struct { + union { + __IO uint16_t IRQ040MONL; + struct { + __IO uint8_t IRQ040MONLL; + __IO uint8_t IRQ040MONLH; + }; + }; + union { + __IO uint16_t IRQ040MONH; + struct { + __IO uint8_t IRQ040MONHL; + __IO uint8_t IRQ040MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ041MON; + stc_intreq_irq041mon_field_t IRQ041MON_f; + struct { + union { + __IO uint16_t IRQ041MONL; + struct { + __IO uint8_t IRQ041MONLL; + __IO uint8_t IRQ041MONLH; + }; + }; + union { + __IO uint16_t IRQ041MONH; + struct { + __IO uint8_t IRQ041MONHL; + __IO uint8_t IRQ041MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ042MON; + stc_intreq_irq042mon_field_t IRQ042MON_f; + struct { + union { + __IO uint16_t IRQ042MONL; + struct { + __IO uint8_t IRQ042MONLL; + __IO uint8_t IRQ042MONLH; + }; + }; + union { + __IO uint16_t IRQ042MONH; + struct { + __IO uint8_t IRQ042MONHL; + __IO uint8_t IRQ042MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ043MON; + stc_intreq_irq043mon_field_t IRQ043MON_f; + struct { + union { + __IO uint16_t IRQ043MONL; + struct { + __IO uint8_t IRQ043MONLL; + __IO uint8_t IRQ043MONLH; + }; + }; + union { + __IO uint16_t IRQ043MONH; + struct { + __IO uint8_t IRQ043MONHL; + __IO uint8_t IRQ043MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ044MON; + stc_intreq_irq044mon_field_t IRQ044MON_f; + struct { + union { + __IO uint16_t IRQ044MONL; + struct { + __IO uint8_t IRQ044MONLL; + __IO uint8_t IRQ044MONLH; + }; + }; + union { + __IO uint16_t IRQ044MONH; + struct { + __IO uint8_t IRQ044MONHL; + __IO uint8_t IRQ044MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ045MON; + stc_intreq_irq045mon_field_t IRQ045MON_f; + struct { + union { + __IO uint16_t IRQ045MONL; + struct { + __IO uint8_t IRQ045MONLL; + __IO uint8_t IRQ045MONLH; + }; + }; + union { + __IO uint16_t IRQ045MONH; + struct { + __IO uint8_t IRQ045MONHL; + __IO uint8_t IRQ045MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ046MON; + stc_intreq_irq046mon_field_t IRQ046MON_f; + struct { + union { + __IO uint16_t IRQ046MONL; + struct { + __IO uint8_t IRQ046MONLL; + __IO uint8_t IRQ046MONLH; + }; + }; + union { + __IO uint16_t IRQ046MONH; + struct { + __IO uint8_t IRQ046MONHL; + __IO uint8_t IRQ046MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ047MON; + stc_intreq_irq047mon_field_t IRQ047MON_f; + struct { + union { + __IO uint16_t IRQ047MONL; + struct { + __IO uint8_t IRQ047MONLL; + __IO uint8_t IRQ047MONLH; + }; + }; + union { + __IO uint16_t IRQ047MONH; + struct { + __IO uint8_t IRQ047MONHL; + __IO uint8_t IRQ047MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ048MON; + stc_intreq_irq048mon_field_t IRQ048MON_f; + struct { + union { + __IO uint16_t IRQ048MONL; + struct { + __IO uint8_t IRQ048MONLL; + __IO uint8_t IRQ048MONLH; + }; + }; + union { + __IO uint16_t IRQ048MONH; + struct { + __IO uint8_t IRQ048MONHL; + __IO uint8_t IRQ048MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ049MON; + stc_intreq_irq049mon_field_t IRQ049MON_f; + struct { + union { + __IO uint16_t IRQ049MONL; + struct { + __IO uint8_t IRQ049MONLL; + __IO uint8_t IRQ049MONLH; + }; + }; + union { + __IO uint16_t IRQ049MONH; + struct { + __IO uint8_t IRQ049MONHL; + __IO uint8_t IRQ049MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ050MON; + stc_intreq_irq050mon_field_t IRQ050MON_f; + struct { + union { + __IO uint16_t IRQ050MONL; + struct { + __IO uint8_t IRQ050MONLL; + __IO uint8_t IRQ050MONLH; + }; + }; + union { + __IO uint16_t IRQ050MONH; + struct { + __IO uint8_t IRQ050MONHL; + __IO uint8_t IRQ050MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ051MON; + stc_intreq_irq051mon_field_t IRQ051MON_f; + struct { + union { + __IO uint16_t IRQ051MONL; + struct { + __IO uint8_t IRQ051MONLL; + __IO uint8_t IRQ051MONLH; + }; + }; + union { + __IO uint16_t IRQ051MONH; + struct { + __IO uint8_t IRQ051MONHL; + __IO uint8_t IRQ051MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ052MON; + stc_intreq_irq052mon_field_t IRQ052MON_f; + struct { + union { + __IO uint16_t IRQ052MONL; + struct { + __IO uint8_t IRQ052MONLL; + __IO uint8_t IRQ052MONLH; + }; + }; + union { + __IO uint16_t IRQ052MONH; + struct { + __IO uint8_t IRQ052MONHL; + __IO uint8_t IRQ052MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ053MON; + stc_intreq_irq053mon_field_t IRQ053MON_f; + struct { + union { + __IO uint16_t IRQ053MONL; + struct { + __IO uint8_t IRQ053MONLL; + __IO uint8_t IRQ053MONLH; + }; + }; + union { + __IO uint16_t IRQ053MONH; + struct { + __IO uint8_t IRQ053MONHL; + __IO uint8_t IRQ053MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ054MON; + stc_intreq_irq054mon_field_t IRQ054MON_f; + struct { + union { + __IO uint16_t IRQ054MONL; + struct { + __IO uint8_t IRQ054MONLL; + __IO uint8_t IRQ054MONLH; + }; + }; + union { + __IO uint16_t IRQ054MONH; + struct { + __IO uint8_t IRQ054MONHL; + __IO uint8_t IRQ054MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ055MON; + stc_intreq_irq055mon_field_t IRQ055MON_f; + struct { + union { + __IO uint16_t IRQ055MONL; + struct { + __IO uint8_t IRQ055MONLL; + __IO uint8_t IRQ055MONLH; + }; + }; + union { + __IO uint16_t IRQ055MONH; + struct { + __IO uint8_t IRQ055MONHL; + __IO uint8_t IRQ055MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ056MON; + stc_intreq_irq056mon_field_t IRQ056MON_f; + struct { + union { + __IO uint16_t IRQ056MONL; + struct { + __IO uint8_t IRQ056MONLL; + __IO uint8_t IRQ056MONLH; + }; + }; + union { + __IO uint16_t IRQ056MONH; + struct { + __IO uint8_t IRQ056MONHL; + __IO uint8_t IRQ056MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ057MON; + stc_intreq_irq057mon_field_t IRQ057MON_f; + struct { + union { + __IO uint16_t IRQ057MONL; + struct { + __IO uint8_t IRQ057MONLL; + __IO uint8_t IRQ057MONLH; + }; + }; + union { + __IO uint16_t IRQ057MONH; + struct { + __IO uint8_t IRQ057MONHL; + __IO uint8_t IRQ057MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ058MON; + stc_intreq_irq058mon_field_t IRQ058MON_f; + struct { + union { + __IO uint16_t IRQ058MONL; + struct { + __IO uint8_t IRQ058MONLL; + __IO uint8_t IRQ058MONLH; + }; + }; + union { + __IO uint16_t IRQ058MONH; + struct { + __IO uint8_t IRQ058MONHL; + __IO uint8_t IRQ058MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ059MON; + stc_intreq_irq059mon_field_t IRQ059MON_f; + struct { + union { + __IO uint16_t IRQ059MONL; + struct { + __IO uint8_t IRQ059MONLL; + __IO uint8_t IRQ059MONLH; + }; + }; + union { + __IO uint16_t IRQ059MONH; + struct { + __IO uint8_t IRQ059MONHL; + __IO uint8_t IRQ059MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ060MON; + stc_intreq_irq060mon_field_t IRQ060MON_f; + struct { + union { + __IO uint16_t IRQ060MONL; + struct { + __IO uint8_t IRQ060MONLL; + __IO uint8_t IRQ060MONLH; + }; + }; + union { + __IO uint16_t IRQ060MONH; + struct { + __IO uint8_t IRQ060MONHL; + __IO uint8_t IRQ060MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ061MON; + stc_intreq_irq061mon_field_t IRQ061MON_f; + struct { + union { + __IO uint16_t IRQ061MONL; + struct { + __IO uint8_t IRQ061MONLL; + __IO uint8_t IRQ061MONLH; + }; + }; + union { + __IO uint16_t IRQ061MONH; + struct { + __IO uint8_t IRQ061MONHL; + __IO uint8_t IRQ061MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ062MON; + stc_intreq_irq062mon_field_t IRQ062MON_f; + struct { + union { + __IO uint16_t IRQ062MONL; + struct { + __IO uint8_t IRQ062MONLL; + __IO uint8_t IRQ062MONLH; + }; + }; + union { + __IO uint16_t IRQ062MONH; + struct { + __IO uint8_t IRQ062MONHL; + __IO uint8_t IRQ062MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ063MON; + stc_intreq_irq063mon_field_t IRQ063MON_f; + struct { + union { + __IO uint16_t IRQ063MONL; + struct { + __IO uint8_t IRQ063MONLL; + __IO uint8_t IRQ063MONLH; + }; + }; + union { + __IO uint16_t IRQ063MONH; + struct { + __IO uint8_t IRQ063MONHL; + __IO uint8_t IRQ063MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ064MON; + stc_intreq_irq064mon_field_t IRQ064MON_f; + struct { + union { + __IO uint16_t IRQ064MONL; + struct { + __IO uint8_t IRQ064MONLL; + __IO uint8_t IRQ064MONLH; + }; + }; + union { + __IO uint16_t IRQ064MONH; + struct { + __IO uint8_t IRQ064MONHL; + __IO uint8_t IRQ064MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ065MON; + stc_intreq_irq065mon_field_t IRQ065MON_f; + struct { + union { + __IO uint16_t IRQ065MONL; + struct { + __IO uint8_t IRQ065MONLL; + __IO uint8_t IRQ065MONLH; + }; + }; + union { + __IO uint16_t IRQ065MONH; + struct { + __IO uint8_t IRQ065MONHL; + __IO uint8_t IRQ065MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ066MON; + stc_intreq_irq066mon_field_t IRQ066MON_f; + struct { + union { + __IO uint16_t IRQ066MONL; + struct { + __IO uint8_t IRQ066MONLL; + __IO uint8_t IRQ066MONLH; + }; + }; + union { + __IO uint16_t IRQ066MONH; + struct { + __IO uint8_t IRQ066MONHL; + __IO uint8_t IRQ066MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ067MON; + stc_intreq_irq067mon_field_t IRQ067MON_f; + struct { + union { + __IO uint16_t IRQ067MONL; + struct { + __IO uint8_t IRQ067MONLL; + __IO uint8_t IRQ067MONLH; + }; + }; + union { + __IO uint16_t IRQ067MONH; + struct { + __IO uint8_t IRQ067MONHL; + __IO uint8_t IRQ067MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ068MON; + stc_intreq_irq068mon_field_t IRQ068MON_f; + struct { + union { + __IO uint16_t IRQ068MONL; + struct { + __IO uint8_t IRQ068MONLL; + __IO uint8_t IRQ068MONLH; + }; + }; + union { + __IO uint16_t IRQ068MONH; + struct { + __IO uint8_t IRQ068MONHL; + __IO uint8_t IRQ068MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ069MON; + stc_intreq_irq069mon_field_t IRQ069MON_f; + struct { + union { + __IO uint16_t IRQ069MONL; + struct { + __IO uint8_t IRQ069MONLL; + __IO uint8_t IRQ069MONLH; + }; + }; + union { + __IO uint16_t IRQ069MONH; + struct { + __IO uint8_t IRQ069MONHL; + __IO uint8_t IRQ069MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ070MON; + stc_intreq_irq070mon_field_t IRQ070MON_f; + struct { + union { + __IO uint16_t IRQ070MONL; + struct { + __IO uint8_t IRQ070MONLL; + __IO uint8_t IRQ070MONLH; + }; + }; + union { + __IO uint16_t IRQ070MONH; + struct { + __IO uint8_t IRQ070MONHL; + __IO uint8_t IRQ070MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ071MON; + stc_intreq_irq071mon_field_t IRQ071MON_f; + struct { + union { + __IO uint16_t IRQ071MONL; + struct { + __IO uint8_t IRQ071MONLL; + __IO uint8_t IRQ071MONLH; + }; + }; + union { + __IO uint16_t IRQ071MONH; + struct { + __IO uint8_t IRQ071MONHL; + __IO uint8_t IRQ071MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ072MON; + stc_intreq_irq072mon_field_t IRQ072MON_f; + struct { + union { + __IO uint16_t IRQ072MONL; + struct { + __IO uint8_t IRQ072MONLL; + __IO uint8_t IRQ072MONLH; + }; + }; + union { + __IO uint16_t IRQ072MONH; + struct { + __IO uint8_t IRQ072MONHL; + __IO uint8_t IRQ072MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ073MON; + stc_intreq_irq073mon_field_t IRQ073MON_f; + struct { + union { + __IO uint16_t IRQ073MONL; + struct { + __IO uint8_t IRQ073MONLL; + __IO uint8_t IRQ073MONLH; + }; + }; + union { + __IO uint16_t IRQ073MONH; + struct { + __IO uint8_t IRQ073MONHL; + __IO uint8_t IRQ073MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ074MON; + stc_intreq_irq074mon_field_t IRQ074MON_f; + struct { + union { + __IO uint16_t IRQ074MONL; + struct { + __IO uint8_t IRQ074MONLL; + __IO uint8_t IRQ074MONLH; + }; + }; + union { + __IO uint16_t IRQ074MONH; + struct { + __IO uint8_t IRQ074MONHL; + __IO uint8_t IRQ074MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ075MON; + stc_intreq_irq075mon_field_t IRQ075MON_f; + struct { + union { + __IO uint16_t IRQ075MONL; + struct { + __IO uint8_t IRQ075MONLL; + __IO uint8_t IRQ075MONLH; + }; + }; + union { + __IO uint16_t IRQ075MONH; + struct { + __IO uint8_t IRQ075MONHL; + __IO uint8_t IRQ075MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ076MON; + stc_intreq_irq076mon_field_t IRQ076MON_f; + struct { + union { + __IO uint16_t IRQ076MONL; + struct { + __IO uint8_t IRQ076MONLL; + __IO uint8_t IRQ076MONLH; + }; + }; + union { + __IO uint16_t IRQ076MONH; + struct { + __IO uint8_t IRQ076MONHL; + __IO uint8_t IRQ076MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ077MON; + stc_intreq_irq077mon_field_t IRQ077MON_f; + struct { + union { + __IO uint16_t IRQ077MONL; + struct { + __IO uint8_t IRQ077MONLL; + __IO uint8_t IRQ077MONLH; + }; + }; + union { + __IO uint16_t IRQ077MONH; + struct { + __IO uint8_t IRQ077MONHL; + __IO uint8_t IRQ077MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ078MON; + stc_intreq_irq078mon_field_t IRQ078MON_f; + struct { + union { + __IO uint16_t IRQ078MONL; + struct { + __IO uint8_t IRQ078MONLL; + __IO uint8_t IRQ078MONLH; + }; + }; + union { + __IO uint16_t IRQ078MONH; + struct { + __IO uint8_t IRQ078MONHL; + __IO uint8_t IRQ078MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ079MON; + stc_intreq_irq079mon_field_t IRQ079MON_f; + struct { + union { + __IO uint16_t IRQ079MONL; + struct { + __IO uint8_t IRQ079MONLL; + __IO uint8_t IRQ079MONLH; + }; + }; + union { + __IO uint16_t IRQ079MONH; + struct { + __IO uint8_t IRQ079MONHL; + __IO uint8_t IRQ079MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ080MON; + stc_intreq_irq080mon_field_t IRQ080MON_f; + struct { + union { + __IO uint16_t IRQ080MONL; + struct { + __IO uint8_t IRQ080MONLL; + __IO uint8_t IRQ080MONLH; + }; + }; + union { + __IO uint16_t IRQ080MONH; + struct { + __IO uint8_t IRQ080MONHL; + __IO uint8_t IRQ080MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ081MON; + stc_intreq_irq081mon_field_t IRQ081MON_f; + struct { + union { + __IO uint16_t IRQ081MONL; + struct { + __IO uint8_t IRQ081MONLL; + __IO uint8_t IRQ081MONLH; + }; + }; + union { + __IO uint16_t IRQ081MONH; + struct { + __IO uint8_t IRQ081MONHL; + __IO uint8_t IRQ081MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ082MON; + stc_intreq_irq082mon_field_t IRQ082MON_f; + struct { + union { + __IO uint16_t IRQ082MONL; + struct { + __IO uint8_t IRQ082MONLL; + __IO uint8_t IRQ082MONLH; + }; + }; + union { + __IO uint16_t IRQ082MONH; + struct { + __IO uint8_t IRQ082MONHL; + __IO uint8_t IRQ082MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ083MON; + stc_intreq_irq083mon_field_t IRQ083MON_f; + struct { + union { + __IO uint16_t IRQ083MONL; + struct { + __IO uint8_t IRQ083MONLL; + __IO uint8_t IRQ083MONLH; + }; + }; + union { + __IO uint16_t IRQ083MONH; + struct { + __IO uint8_t IRQ083MONHL; + __IO uint8_t IRQ083MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ084MON; + stc_intreq_irq084mon_field_t IRQ084MON_f; + struct { + union { + __IO uint16_t IRQ084MONL; + struct { + __IO uint8_t IRQ084MONLL; + __IO uint8_t IRQ084MONLH; + }; + }; + union { + __IO uint16_t IRQ084MONH; + struct { + __IO uint8_t IRQ084MONHL; + __IO uint8_t IRQ084MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ085MON; + stc_intreq_irq085mon_field_t IRQ085MON_f; + struct { + union { + __IO uint16_t IRQ085MONL; + struct { + __IO uint8_t IRQ085MONLL; + __IO uint8_t IRQ085MONLH; + }; + }; + union { + __IO uint16_t IRQ085MONH; + struct { + __IO uint8_t IRQ085MONHL; + __IO uint8_t IRQ085MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ086MON; + stc_intreq_irq086mon_field_t IRQ086MON_f; + struct { + union { + __IO uint16_t IRQ086MONL; + struct { + __IO uint8_t IRQ086MONLL; + __IO uint8_t IRQ086MONLH; + }; + }; + union { + __IO uint16_t IRQ086MONH; + struct { + __IO uint8_t IRQ086MONHL; + __IO uint8_t IRQ086MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ087MON; + stc_intreq_irq087mon_field_t IRQ087MON_f; + struct { + union { + __IO uint16_t IRQ087MONL; + struct { + __IO uint8_t IRQ087MONLL; + __IO uint8_t IRQ087MONLH; + }; + }; + union { + __IO uint16_t IRQ087MONH; + struct { + __IO uint8_t IRQ087MONHL; + __IO uint8_t IRQ087MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ088MON; + stc_intreq_irq088mon_field_t IRQ088MON_f; + struct { + union { + __IO uint16_t IRQ088MONL; + struct { + __IO uint8_t IRQ088MONLL; + __IO uint8_t IRQ088MONLH; + }; + }; + union { + __IO uint16_t IRQ088MONH; + struct { + __IO uint8_t IRQ088MONHL; + __IO uint8_t IRQ088MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ089MON; + stc_intreq_irq089mon_field_t IRQ089MON_f; + struct { + union { + __IO uint16_t IRQ089MONL; + struct { + __IO uint8_t IRQ089MONLL; + __IO uint8_t IRQ089MONLH; + }; + }; + union { + __IO uint16_t IRQ089MONH; + struct { + __IO uint8_t IRQ089MONHL; + __IO uint8_t IRQ089MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ090MON; + stc_intreq_irq090mon_field_t IRQ090MON_f; + struct { + union { + __IO uint16_t IRQ090MONL; + struct { + __IO uint8_t IRQ090MONLL; + __IO uint8_t IRQ090MONLH; + }; + }; + union { + __IO uint16_t IRQ090MONH; + struct { + __IO uint8_t IRQ090MONHL; + __IO uint8_t IRQ090MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ091MON; + stc_intreq_irq091mon_field_t IRQ091MON_f; + struct { + union { + __IO uint16_t IRQ091MONL; + struct { + __IO uint8_t IRQ091MONLL; + __IO uint8_t IRQ091MONLH; + }; + }; + union { + __IO uint16_t IRQ091MONH; + struct { + __IO uint8_t IRQ091MONHL; + __IO uint8_t IRQ091MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ092MON; + stc_intreq_irq092mon_field_t IRQ092MON_f; + struct { + union { + __IO uint16_t IRQ092MONL; + struct { + __IO uint8_t IRQ092MONLL; + __IO uint8_t IRQ092MONLH; + }; + }; + union { + __IO uint16_t IRQ092MONH; + struct { + __IO uint8_t IRQ092MONHL; + __IO uint8_t IRQ092MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ093MON; + stc_intreq_irq093mon_field_t IRQ093MON_f; + struct { + union { + __IO uint16_t IRQ093MONL; + struct { + __IO uint8_t IRQ093MONLL; + __IO uint8_t IRQ093MONLH; + }; + }; + union { + __IO uint16_t IRQ093MONH; + struct { + __IO uint8_t IRQ093MONHL; + __IO uint8_t IRQ093MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ094MON; + stc_intreq_irq094mon_field_t IRQ094MON_f; + struct { + union { + __IO uint16_t IRQ094MONL; + struct { + __IO uint8_t IRQ094MONLL; + __IO uint8_t IRQ094MONLH; + }; + }; + union { + __IO uint16_t IRQ094MONH; + struct { + __IO uint8_t IRQ094MONHL; + __IO uint8_t IRQ094MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ095MON; + stc_intreq_irq095mon_field_t IRQ095MON_f; + struct { + union { + __IO uint16_t IRQ095MONL; + struct { + __IO uint8_t IRQ095MONLL; + __IO uint8_t IRQ095MONLH; + }; + }; + union { + __IO uint16_t IRQ095MONH; + struct { + __IO uint8_t IRQ095MONHL; + __IO uint8_t IRQ095MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ096MON; + stc_intreq_irq096mon_field_t IRQ096MON_f; + struct { + union { + __IO uint16_t IRQ096MONL; + struct { + __IO uint8_t IRQ096MONLL; + __IO uint8_t IRQ096MONLH; + }; + }; + union { + __IO uint16_t IRQ096MONH; + struct { + __IO uint8_t IRQ096MONHL; + __IO uint8_t IRQ096MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ097MON; + stc_intreq_irq097mon_field_t IRQ097MON_f; + struct { + union { + __IO uint16_t IRQ097MONL; + struct { + __IO uint8_t IRQ097MONLL; + __IO uint8_t IRQ097MONLH; + }; + }; + union { + __IO uint16_t IRQ097MONH; + struct { + __IO uint8_t IRQ097MONHL; + __IO uint8_t IRQ097MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ098MON; + stc_intreq_irq098mon_field_t IRQ098MON_f; + struct { + union { + __IO uint16_t IRQ098MONL; + struct { + __IO uint8_t IRQ098MONLL; + __IO uint8_t IRQ098MONLH; + }; + }; + union { + __IO uint16_t IRQ098MONH; + struct { + __IO uint8_t IRQ098MONHL; + __IO uint8_t IRQ098MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ099MON; + stc_intreq_irq099mon_field_t IRQ099MON_f; + struct { + union { + __IO uint16_t IRQ099MONL; + struct { + __IO uint8_t IRQ099MONLL; + __IO uint8_t IRQ099MONLH; + }; + }; + union { + __IO uint16_t IRQ099MONH; + struct { + __IO uint8_t IRQ099MONHL; + __IO uint8_t IRQ099MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ100MON; + stc_intreq_irq100mon_field_t IRQ100MON_f; + struct { + union { + __IO uint16_t IRQ100MONL; + struct { + __IO uint8_t IRQ100MONLL; + __IO uint8_t IRQ100MONLH; + }; + }; + union { + __IO uint16_t IRQ100MONH; + struct { + __IO uint8_t IRQ100MONHL; + __IO uint8_t IRQ100MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ101MON; + stc_intreq_irq101mon_field_t IRQ101MON_f; + struct { + union { + __IO uint16_t IRQ101MONL; + struct { + __IO uint8_t IRQ101MONLL; + __IO uint8_t IRQ101MONLH; + }; + }; + union { + __IO uint16_t IRQ101MONH; + struct { + __IO uint8_t IRQ101MONHL; + __IO uint8_t IRQ101MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ102MON; + stc_intreq_irq102mon_field_t IRQ102MON_f; + struct { + union { + __IO uint16_t IRQ102MONL; + struct { + __IO uint8_t IRQ102MONLL; + __IO uint8_t IRQ102MONLH; + }; + }; + union { + __IO uint16_t IRQ102MONH; + struct { + __IO uint8_t IRQ102MONHL; + __IO uint8_t IRQ102MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ103MON; + stc_intreq_irq103mon_field_t IRQ103MON_f; + struct { + union { + __IO uint16_t IRQ103MONL; + struct { + __IO uint8_t IRQ103MONLL; + __IO uint8_t IRQ103MONLH; + }; + }; + union { + __IO uint16_t IRQ103MONH; + struct { + __IO uint8_t IRQ103MONHL; + __IO uint8_t IRQ103MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ104MON; + stc_intreq_irq104mon_field_t IRQ104MON_f; + struct { + union { + __IO uint16_t IRQ104MONL; + struct { + __IO uint8_t IRQ104MONLL; + __IO uint8_t IRQ104MONLH; + }; + }; + union { + __IO uint16_t IRQ104MONH; + struct { + __IO uint8_t IRQ104MONHL; + __IO uint8_t IRQ104MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ105MON; + stc_intreq_irq105mon_field_t IRQ105MON_f; + struct { + union { + __IO uint16_t IRQ105MONL; + struct { + __IO uint8_t IRQ105MONLL; + __IO uint8_t IRQ105MONLH; + }; + }; + union { + __IO uint16_t IRQ105MONH; + struct { + __IO uint8_t IRQ105MONHL; + __IO uint8_t IRQ105MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ106MON; + stc_intreq_irq106mon_field_t IRQ106MON_f; + struct { + union { + __IO uint16_t IRQ106MONL; + struct { + __IO uint8_t IRQ106MONLL; + __IO uint8_t IRQ106MONLH; + }; + }; + union { + __IO uint16_t IRQ106MONH; + struct { + __IO uint8_t IRQ106MONHL; + __IO uint8_t IRQ106MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ107MON; + stc_intreq_irq107mon_field_t IRQ107MON_f; + struct { + union { + __IO uint16_t IRQ107MONL; + struct { + __IO uint8_t IRQ107MONLL; + __IO uint8_t IRQ107MONLH; + }; + }; + union { + __IO uint16_t IRQ107MONH; + struct { + __IO uint8_t IRQ107MONHL; + __IO uint8_t IRQ107MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ108MON; + stc_intreq_irq108mon_field_t IRQ108MON_f; + struct { + union { + __IO uint16_t IRQ108MONL; + struct { + __IO uint8_t IRQ108MONLL; + __IO uint8_t IRQ108MONLH; + }; + }; + union { + __IO uint16_t IRQ108MONH; + struct { + __IO uint8_t IRQ108MONHL; + __IO uint8_t IRQ108MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ109MON; + stc_intreq_irq109mon_field_t IRQ109MON_f; + struct { + union { + __IO uint16_t IRQ109MONL; + struct { + __IO uint8_t IRQ109MONLL; + __IO uint8_t IRQ109MONLH; + }; + }; + union { + __IO uint16_t IRQ109MONH; + struct { + __IO uint8_t IRQ109MONHL; + __IO uint8_t IRQ109MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ110MON; + stc_intreq_irq110mon_field_t IRQ110MON_f; + struct { + union { + __IO uint16_t IRQ110MONL; + struct { + __IO uint8_t IRQ110MONLL; + __IO uint8_t IRQ110MONLH; + }; + }; + union { + __IO uint16_t IRQ110MONH; + struct { + __IO uint8_t IRQ110MONHL; + __IO uint8_t IRQ110MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ111MON; + stc_intreq_irq111mon_field_t IRQ111MON_f; + struct { + union { + __IO uint16_t IRQ111MONL; + struct { + __IO uint8_t IRQ111MONLL; + __IO uint8_t IRQ111MONLH; + }; + }; + union { + __IO uint16_t IRQ111MONH; + struct { + __IO uint8_t IRQ111MONHL; + __IO uint8_t IRQ111MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ112MON; + stc_intreq_irq112mon_field_t IRQ112MON_f; + struct { + union { + __IO uint16_t IRQ112MONL; + struct { + __IO uint8_t IRQ112MONLL; + __IO uint8_t IRQ112MONLH; + }; + }; + union { + __IO uint16_t IRQ112MONH; + struct { + __IO uint8_t IRQ112MONHL; + __IO uint8_t IRQ112MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ113MON; + stc_intreq_irq113mon_field_t IRQ113MON_f; + struct { + union { + __IO uint16_t IRQ113MONL; + struct { + __IO uint8_t IRQ113MONLL; + __IO uint8_t IRQ113MONLH; + }; + }; + union { + __IO uint16_t IRQ113MONH; + struct { + __IO uint8_t IRQ113MONHL; + __IO uint8_t IRQ113MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ114MON; + stc_intreq_irq114mon_field_t IRQ114MON_f; + struct { + union { + __IO uint16_t IRQ114MONL; + struct { + __IO uint8_t IRQ114MONLL; + __IO uint8_t IRQ114MONLH; + }; + }; + union { + __IO uint16_t IRQ114MONH; + struct { + __IO uint8_t IRQ114MONHL; + __IO uint8_t IRQ114MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ115MON; + stc_intreq_irq115mon_field_t IRQ115MON_f; + struct { + union { + __IO uint16_t IRQ115MONL; + struct { + __IO uint8_t IRQ115MONLL; + __IO uint8_t IRQ115MONLH; + }; + }; + union { + __IO uint16_t IRQ115MONH; + struct { + __IO uint8_t IRQ115MONHL; + __IO uint8_t IRQ115MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ116MON; + struct { + union { + __IO uint16_t IRQ116MONL; + struct { + __IO uint8_t IRQ116MONLL; + __IO uint8_t IRQ116MONLH; + }; + }; + union { + __IO uint16_t IRQ116MONH; + struct { + __IO uint8_t IRQ116MONHL; + __IO uint8_t IRQ116MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ117MON; + stc_intreq_irq117mon_field_t IRQ117MON_f; + struct { + union { + __IO uint16_t IRQ117MONL; + struct { + __IO uint8_t IRQ117MONLL; + __IO uint8_t IRQ117MONLH; + }; + }; + union { + __IO uint16_t IRQ117MONH; + struct { + __IO uint8_t IRQ117MONHL; + __IO uint8_t IRQ117MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ118MON; + stc_intreq_irq118mon_field_t IRQ118MON_f; + struct { + union { + __IO uint16_t IRQ118MONL; + struct { + __IO uint8_t IRQ118MONLL; + __IO uint8_t IRQ118MONLH; + }; + }; + union { + __IO uint16_t IRQ118MONH; + struct { + __IO uint8_t IRQ118MONHL; + __IO uint8_t IRQ118MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ119MON; + stc_intreq_irq119mon_field_t IRQ119MON_f; + struct { + union { + __IO uint16_t IRQ119MONL; + struct { + __IO uint8_t IRQ119MONLL; + __IO uint8_t IRQ119MONLH; + }; + }; + union { + __IO uint16_t IRQ119MONH; + struct { + __IO uint8_t IRQ119MONHL; + __IO uint8_t IRQ119MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ120MON; + stc_intreq_irq120mon_field_t IRQ120MON_f; + struct { + union { + __IO uint16_t IRQ120MONL; + struct { + __IO uint8_t IRQ120MONLL; + __IO uint8_t IRQ120MONLH; + }; + }; + union { + __IO uint16_t IRQ120MONH; + struct { + __IO uint8_t IRQ120MONHL; + __IO uint8_t IRQ120MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ121MON; + stc_intreq_irq121mon_field_t IRQ121MON_f; + struct { + union { + __IO uint16_t IRQ121MONL; + struct { + __IO uint8_t IRQ121MONLL; + __IO uint8_t IRQ121MONLH; + }; + }; + union { + __IO uint16_t IRQ121MONH; + struct { + __IO uint8_t IRQ121MONHL; + __IO uint8_t IRQ121MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ122MON; + stc_intreq_irq122mon_field_t IRQ122MON_f; + struct { + union { + __IO uint16_t IRQ122MONL; + struct { + __IO uint8_t IRQ122MONLL; + __IO uint8_t IRQ122MONLH; + }; + }; + union { + __IO uint16_t IRQ122MONH; + struct { + __IO uint8_t IRQ122MONHL; + __IO uint8_t IRQ122MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ123MON; + stc_intreq_irq123mon_field_t IRQ123MON_f; + struct { + union { + __IO uint16_t IRQ123MONL; + struct { + __IO uint8_t IRQ123MONLL; + __IO uint8_t IRQ123MONLH; + }; + }; + union { + __IO uint16_t IRQ123MONH; + struct { + __IO uint8_t IRQ123MONHL; + __IO uint8_t IRQ123MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ124MON; + stc_intreq_irq124mon_field_t IRQ124MON_f; + struct { + union { + __IO uint16_t IRQ124MONL; + struct { + __IO uint8_t IRQ124MONLL; + __IO uint8_t IRQ124MONLH; + }; + }; + union { + __IO uint16_t IRQ124MONH; + struct { + __IO uint8_t IRQ124MONHL; + __IO uint8_t IRQ124MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ125MON; + stc_intreq_irq125mon_field_t IRQ125MON_f; + struct { + union { + __IO uint16_t IRQ125MONL; + struct { + __IO uint8_t IRQ125MONLL; + __IO uint8_t IRQ125MONLH; + }; + }; + union { + __IO uint16_t IRQ125MONH; + struct { + __IO uint8_t IRQ125MONHL; + __IO uint8_t IRQ125MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ126MON; + stc_intreq_irq126mon_field_t IRQ126MON_f; + struct { + union { + __IO uint16_t IRQ126MONL; + struct { + __IO uint8_t IRQ126MONLL; + __IO uint8_t IRQ126MONLH; + }; + }; + union { + __IO uint16_t IRQ126MONH; + struct { + __IO uint8_t IRQ126MONHL; + __IO uint8_t IRQ126MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ127MON; + stc_intreq_irq127mon_field_t IRQ127MON_f; + struct { + union { + __IO uint16_t IRQ127MONL; + struct { + __IO uint8_t IRQ127MONLL; + __IO uint8_t IRQ127MONLH; + }; + }; + union { + __IO uint16_t IRQ127MONH; + struct { + __IO uint8_t IRQ127MONHL; + __IO uint8_t IRQ127MONHH; + }; + }; + }; + }; +} FM_INTREQ_TypeDef, FM4_INTREQ_TypeDef; + +/******************************************************************************* +* LSCRP_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t LCR_PRSLD; + stc_lscrp_lcr_prsld_field_t LCR_PRSLD_f; + }; +} FM_LSCRP_TypeDef, FM4_LSCRP_TypeDef; + +/******************************************************************************* +* LVD_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t LVD_CTL; + stc_lvd_lvd_ctl_field_t LVD_CTL_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t LVD_STR; + stc_lvd_lvd_str_field_t LVD_STR_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t LVD_CLR; + stc_lvd_lvd_clr_field_t LVD_CLR_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint32_t LVD_RLR; + stc_lvd_lvd_rlr_field_t LVD_RLR_f; + struct { + union { + __IO uint16_t LVD_RLRL; + struct { + __IO uint8_t LVD_RLRLL; + __IO uint8_t LVD_RLRLH; + }; + }; + union { + __IO uint16_t LVD_RLRH; + struct { + __IO uint8_t LVD_RLRHL; + __IO uint8_t LVD_RLRHH; + }; + }; + }; + }; + union { + __IO uint8_t LVD_STR2; + stc_lvd_lvd_str2_field_t LVD_STR2_f; + }; +} FM_LVD_TypeDef, FM4_LVD_TypeDef; + +/******************************************************************************* +* MFS_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_smr_field_t SMR_f; + __IO uint8_t CSIO_SMR; + stc_mfs_csio_smr_field_t CSIO_SMR_f; + __IO uint8_t I2C_SMR; + stc_mfs_i2c_smr_field_t I2C_SMR_f; + __IO uint8_t LIN_SMR; + stc_mfs_lin_smr_field_t LIN_SMR_f; + __IO uint8_t UART_SMR; + stc_mfs_uart_smr_field_t UART_SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_scr_field_t SCR_f; + __IO uint8_t CSIO_SCR; + stc_mfs_csio_scr_field_t CSIO_SCR_f; + __IO uint8_t IBCR; + stc_mfs_ibcr_field_t IBCR_f; + __IO uint8_t I2C_IBCR; + stc_mfs_i2c_ibcr_field_t I2C_IBCR_f; + __IO uint8_t LIN_SCR; + stc_mfs_lin_scr_field_t LIN_SCR_f; + __IO uint8_t UART_SCR; + stc_mfs_uart_scr_field_t UART_SCR_f; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs_escr_field_t ESCR_f; + __IO uint8_t CSIO_ESCR; + stc_mfs_csio_escr_field_t CSIO_ESCR_f; + __IO uint8_t IBSR; + stc_mfs_ibsr_field_t IBSR_f; + __IO uint8_t I2C_IBSR; + stc_mfs_i2c_ibsr_field_t I2C_IBSR_f; + __IO uint8_t LIN_ESCR; + stc_mfs_lin_escr_field_t LIN_ESCR_f; + __IO uint8_t UART_ESCR; + stc_mfs_uart_escr_field_t UART_ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_ssr_field_t SSR_f; + __IO uint8_t CSIO_SSR; + stc_mfs_csio_ssr_field_t CSIO_SSR_f; + __IO uint8_t I2C_SSR; + stc_mfs_i2c_ssr_field_t I2C_SSR_f; + __IO uint8_t LIN_SSR; + stc_mfs_lin_ssr_field_t LIN_SSR_f; + __IO uint8_t UART_SSR; + stc_mfs_uart_ssr_field_t UART_SSR_f; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + stc_mfs_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t CSIO_RDR; + stc_mfs_csio_rdr_field_t CSIO_RDR_f; + struct { + __IO uint8_t CSIO_RDRL; + __IO uint8_t CSIO_RDRH; + }; + __IO uint16_t TDR; + stc_mfs_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + __IO uint16_t CSIO_TDR; + stc_mfs_csio_tdr_field_t CSIO_TDR_f; + struct { + __IO uint8_t CSIO_TDRL; + __IO uint8_t CSIO_TDRH; + }; + __IO uint16_t I2C_RDR; + stc_mfs_i2c_rdr_field_t I2C_RDR_f; + struct { + __IO uint8_t I2C_RDRL; + __IO uint8_t I2C_RDRH; + }; + __IO uint16_t I2C_TDR; + stc_mfs_i2c_tdr_field_t I2C_TDR_f; + struct { + __IO uint8_t I2C_TDRL; + __IO uint8_t I2C_TDRH; + }; + __IO uint16_t LIN_RDR; + stc_mfs_lin_rdr_field_t LIN_RDR_f; + struct { + __IO uint8_t LIN_RDRL; + __IO uint8_t LIN_RDRH; + }; + __IO uint16_t LIN_TDR; + stc_mfs_lin_tdr_field_t LIN_TDR_f; + struct { + __IO uint8_t LIN_TDRL; + __IO uint8_t LIN_TDRH; + }; + __IO uint16_t UART_RDR; + stc_mfs_uart_rdr_field_t UART_RDR_f; + struct { + __IO uint8_t UART_RDRL; + __IO uint8_t UART_RDRH; + }; + __IO uint16_t UART_TDR; + stc_mfs_uart_tdr_field_t UART_TDR_f; + struct { + __IO uint8_t UART_TDRL; + __IO uint8_t UART_TDRH; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + stc_mfs_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + __IO uint16_t CSIO_BGR; + stc_mfs_csio_bgr_field_t CSIO_BGR_f; + struct { + __IO uint8_t CSIO_BGRL; + __IO uint8_t CSIO_BGRH; + }; + __IO uint16_t I2C_BGR; + stc_mfs_i2c_bgr_field_t I2C_BGR_f; + struct { + __IO uint8_t I2C_BGRL; + __IO uint8_t I2C_BGRH; + }; + __IO uint16_t LIN_BGR; + stc_mfs_lin_bgr_field_t LIN_BGR_f; + struct { + __IO uint8_t LIN_BGRL; + __IO uint8_t LIN_BGRH; + }; + __IO uint16_t UART_BGR; + stc_mfs_uart_bgr_field_t UART_BGR_f; + struct { + __IO uint8_t UART_BGRL; + __IO uint8_t UART_BGRH; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs_isba_field_t ISBA_f; + __IO uint8_t I2C_ISBA; + stc_mfs_i2c_isba_field_t I2C_ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs_ismk_field_t ISMK_f; + __IO uint8_t I2C_ISMK; + stc_mfs_i2c_ismk_field_t I2C_ISMK_f; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t FCR; + stc_mfs_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + __IO uint16_t CSIO_FCR; + stc_mfs_csio_fcr_field_t CSIO_FCR_f; + struct { + __IO uint8_t CSIO_FCRL; + __IO uint8_t CSIO_FCRH; + }; + __IO uint16_t I2C_FCR; + stc_mfs_i2c_fcr_field_t I2C_FCR_f; + struct { + __IO uint8_t I2C_FCRL; + __IO uint8_t I2C_FCRH; + }; + __IO uint16_t LIN_FCR; + stc_mfs_lin_fcr_field_t LIN_FCR_f; + struct { + __IO uint8_t LIN_FCRL; + __IO uint8_t LIN_FCRH; + }; + __IO uint16_t UART_FCR; + stc_mfs_uart_fcr_field_t UART_FCR_f; + struct { + __IO uint8_t UART_FCRL; + __IO uint8_t UART_FCRH; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_fbyte1_field_t FBYTE1_f; + __IO uint8_t CSIO_FBYTE1; + stc_mfs_csio_fbyte1_field_t CSIO_FBYTE1_f; + __IO uint8_t I2C_FBYTE1; + stc_mfs_i2c_fbyte1_field_t I2C_FBYTE1_f; + __IO uint8_t LIN_FBYTE1; + stc_mfs_lin_fbyte1_field_t LIN_FBYTE1_f; + __IO uint8_t UART_FBYTE1; + stc_mfs_uart_fbyte1_field_t UART_FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_fbyte2_field_t FBYTE2_f; + __IO uint8_t CSIO_FBYTE2; + stc_mfs_csio_fbyte2_field_t CSIO_FBYTE2_f; + __IO uint8_t I2C_FBYTE2; + stc_mfs_i2c_fbyte2_field_t I2C_FBYTE2_f; + __IO uint8_t LIN_FBYTE2; + stc_mfs_lin_fbyte2_field_t LIN_FBYTE2_f; + __IO uint8_t UART_FBYTE2; + stc_mfs_uart_fbyte2_field_t UART_FBYTE2_f; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint8_t SCSTR0; + stc_mfs_scstr0_field_t SCSTR0_f; + __IO uint8_t CSIO_SCSTR0; + stc_mfs_csio_scstr0_field_t CSIO_SCSTR0_f; + __IO uint8_t NFCR; + stc_mfs_nfcr_field_t NFCR_f; + __IO uint8_t I2C_NFCR; + stc_mfs_i2c_nfcr_field_t I2C_NFCR_f; + }; + union { + __IO uint8_t SCSTR1; + stc_mfs_scstr1_field_t SCSTR1_f; + __IO uint8_t CSIO_SCSTR1; + stc_mfs_csio_scstr1_field_t CSIO_SCSTR1_f; + __IO uint8_t EIBCR; + stc_mfs_eibcr_field_t EIBCR_f; + __IO uint8_t I2C_EIBCR; + stc_mfs_i2c_eibcr_field_t I2C_EIBCR_f; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint16_t SCSTR32; + stc_mfs_scstr32_field_t SCSTR32_f; + struct { + __IO uint8_t SCSTR32L; + __IO uint8_t SCSTR32H; + }; + __IO uint16_t CSIO_SCSTR32; + stc_mfs_csio_scstr32_field_t CSIO_SCSTR32_f; + struct { + __IO uint8_t CSIO_SCSTR32L; + __IO uint8_t CSIO_SCSTR32H; + }; + }; + __IO uint8_t RESERVED8[2]; + union { + __IO uint16_t SACSR; + stc_mfs_sacsr_field_t SACSR_f; + struct { + __IO uint8_t SACSRL; + __IO uint8_t SACSRH; + }; + __IO uint16_t CSIO_SACSR; + stc_mfs_csio_sacsr_field_t CSIO_SACSR_f; + struct { + __IO uint8_t CSIO_SACSRL; + __IO uint8_t CSIO_SACSRH; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint16_t STMR; + stc_mfs_stmr_field_t STMR_f; + struct { + __IO uint8_t STMRL; + __IO uint8_t STMRH; + }; + __IO uint16_t CSIO_STMR; + stc_mfs_csio_stmr_field_t CSIO_STMR_f; + struct { + __IO uint8_t CSIO_STMRL; + __IO uint8_t CSIO_STMRH; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint16_t STMCR; + stc_mfs_stmcr_field_t STMCR_f; + struct { + __IO uint8_t STMCRL; + __IO uint8_t STMCRH; + }; + __IO uint16_t CSIO_STMCR; + stc_mfs_csio_stmcr_field_t CSIO_STMCR_f; + struct { + __IO uint8_t CSIO_STMCRL; + __IO uint8_t CSIO_STMCRH; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t SCSCR; + stc_mfs_scscr_field_t SCSCR_f; + struct { + __IO uint8_t SCSCRL; + __IO uint8_t SCSCRH; + }; + __IO uint16_t CSIO_SCSCR; + stc_mfs_csio_scscr_field_t CSIO_SCSCR_f; + struct { + __IO uint8_t CSIO_SCSCRL; + __IO uint8_t CSIO_SCSCRH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint8_t SCSFR0; + stc_mfs_scsfr0_field_t SCSFR0_f; + __IO uint8_t CSIO_SCSFR0; + stc_mfs_csio_scsfr0_field_t CSIO_SCSFR0_f; + }; + union { + __IO uint8_t SCSFR1; + stc_mfs_scsfr1_field_t SCSFR1_f; + __IO uint8_t CSIO_SCSFR1; + stc_mfs_csio_scsfr1_field_t CSIO_SCSFR1_f; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint8_t SCSFR2; + stc_mfs_scsfr2_field_t SCSFR2_f; + __IO uint8_t CSIO_SCSFR2; + stc_mfs_csio_scsfr2_field_t CSIO_SCSFR2_f; + }; + __IO uint8_t RESERVED14[3]; + union { + __IO uint8_t TBYTE0; + __IO uint8_t CSIO_TBYTE0; + }; + union { + __IO uint8_t TBYTE1; + __IO uint8_t CSIO_TBYTE1; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint8_t TBYTE2; + __IO uint8_t CSIO_TBYTE2; + }; + union { + __IO uint8_t TBYTE3; + __IO uint8_t CSIO_TBYTE3; + }; +} FM_MFS_TypeDef, FM4_MFS_TypeDef; + +/******************************************************************************* +* MFS_CSIO_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_csio_scr_field_t SCR_f; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint8_t ESCR; + stc_mfs_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_csio_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED17[2]; + union { + __IO uint16_t RDR; + stc_mfs_csio_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_csio_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint16_t BGR; + stc_mfs_csio_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED19[6]; + union { + __IO uint16_t FCR; + stc_mfs_csio_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_csio_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_csio_fbyte2_field_t FBYTE2_f; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint8_t SCSTR0; + stc_mfs_csio_scstr0_field_t SCSTR0_f; + }; + union { + __IO uint8_t SCSTR1; + stc_mfs_csio_scstr1_field_t SCSTR1_f; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint16_t SCSTR32; + stc_mfs_csio_scstr32_field_t SCSTR32_f; + struct { + __IO uint8_t SCSTR32L; + __IO uint8_t SCSTR32H; + }; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint16_t SACSR; + stc_mfs_csio_sacsr_field_t SACSR_f; + struct { + __IO uint8_t SACSRL; + __IO uint8_t SACSRH; + }; + }; + __IO uint8_t RESERVED24[2]; + union { + __IO uint16_t STMR; + stc_mfs_csio_stmr_field_t STMR_f; + struct { + __IO uint8_t STMRL; + __IO uint8_t STMRH; + }; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint16_t STMCR; + stc_mfs_csio_stmcr_field_t STMCR_f; + struct { + __IO uint8_t STMCRL; + __IO uint8_t STMCRH; + }; + }; + __IO uint8_t RESERVED26[2]; + union { + __IO uint16_t SCSCR; + stc_mfs_csio_scscr_field_t SCSCR_f; + struct { + __IO uint8_t SCSCRL; + __IO uint8_t SCSCRH; + }; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint8_t SCSFR0; + stc_mfs_csio_scsfr0_field_t SCSFR0_f; + }; + union { + __IO uint8_t SCSFR1; + stc_mfs_csio_scsfr1_field_t SCSFR1_f; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint8_t SCSFR2; + stc_mfs_csio_scsfr2_field_t SCSFR2_f; + }; + __IO uint8_t RESERVED29[3]; + __IO uint8_t TBYTE0; + __IO uint8_t TBYTE1; + __IO uint8_t RESERVED30[2]; + __IO uint8_t TBYTE2; + __IO uint8_t TBYTE3; +} FM_MFS_CSIO_TypeDef, FM4_MFS_CSIO_TypeDef; + +/******************************************************************************* +* MFS_I2C_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs_i2c_ibcr_field_t IBCR_f; + }; + __IO uint8_t RESERVED31[2]; + union { + __IO uint8_t IBSR; + stc_mfs_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_i2c_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED32[2]; + union { + __IO uint16_t RDR; + stc_mfs_i2c_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_i2c_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED33[2]; + union { + __IO uint16_t BGR; + stc_mfs_i2c_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED34[2]; + union { + __IO uint8_t ISBA; + stc_mfs_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs_i2c_ismk_field_t ISMK_f; + }; + __IO uint8_t RESERVED35[2]; + union { + __IO uint16_t FCR; + stc_mfs_i2c_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED36[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_i2c_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_i2c_fbyte2_field_t FBYTE2_f; + }; + __IO uint8_t RESERVED37[2]; + union { + __IO uint8_t NFCR; + stc_mfs_i2c_nfcr_field_t NFCR_f; + }; + union { + __IO uint8_t EIBCR; + stc_mfs_i2c_eibcr_field_t EIBCR_f; + }; +} FM_MFS_I2C_TypeDef, FM4_MFS_I2C_TypeDef; + +/******************************************************************************* +* MFS_LIN_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_lin_scr_field_t SCR_f; + }; + __IO uint8_t RESERVED38[2]; + union { + __IO uint8_t ESCR; + stc_mfs_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_lin_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED39[2]; + union { + __IO uint16_t RDR; + stc_mfs_lin_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_lin_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED40[2]; + union { + __IO uint16_t BGR; + stc_mfs_lin_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED41[6]; + union { + __IO uint16_t FCR; + stc_mfs_lin_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED42[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_lin_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_lin_fbyte2_field_t FBYTE2_f; + }; +} FM_MFS_LIN_TypeDef, FM4_MFS_LIN_TypeDef; + +/******************************************************************************* +* MFS_UART_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_uart_scr_field_t SCR_f; + }; + __IO uint8_t RESERVED43[2]; + union { + __IO uint8_t ESCR; + stc_mfs_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_uart_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED44[2]; + union { + __IO uint16_t RDR; + stc_mfs_uart_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_uart_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED45[2]; + union { + __IO uint16_t BGR; + stc_mfs_uart_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED46[6]; + union { + __IO uint16_t FCR; + stc_mfs_uart_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED47[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_uart_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_uart_fbyte2_field_t FBYTE2_f; + }; +} FM_MFS_UART_TypeDef, FM4_MFS_UART_TypeDef; + +/******************************************************************************* +* MFT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[258]; + union { + __IO uint16_t OCCP0; + struct { + __IO uint8_t OCCP0L; + __IO uint8_t OCCP0H; + }; + __IO uint16_t OCU_OCCP0; + struct { + __IO uint8_t OCU_OCCP0L; + __IO uint8_t OCU_OCCP0H; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t OCCP1; + struct { + __IO uint8_t OCCP1L; + __IO uint8_t OCCP1H; + }; + __IO uint16_t OCU_OCCP1; + struct { + __IO uint8_t OCU_OCCP1L; + __IO uint8_t OCU_OCCP1H; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t OCCP2; + struct { + __IO uint8_t OCCP2L; + __IO uint8_t OCCP2H; + }; + __IO uint16_t OCU_OCCP2; + struct { + __IO uint8_t OCU_OCCP2L; + __IO uint8_t OCU_OCCP2H; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint16_t OCCP3; + struct { + __IO uint8_t OCCP3L; + __IO uint8_t OCCP3H; + }; + __IO uint16_t OCU_OCCP3; + struct { + __IO uint8_t OCU_OCCP3L; + __IO uint8_t OCU_OCCP3H; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t OCCP4; + struct { + __IO uint8_t OCCP4L; + __IO uint8_t OCCP4H; + }; + __IO uint16_t OCU_OCCP4; + struct { + __IO uint8_t OCU_OCCP4L; + __IO uint8_t OCU_OCCP4H; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t OCCP5; + struct { + __IO uint8_t OCCP5L; + __IO uint8_t OCCP5H; + }; + __IO uint16_t OCU_OCCP5; + struct { + __IO uint8_t OCU_OCCP5L; + __IO uint8_t OCU_OCCP5H; + }; + }; + union { + __IO uint8_t OCSA10; + stc_mft_ocsa10_field_t OCSA10_f; + __IO uint8_t OCU_OCSA10; + stc_mft_ocu_ocsa10_field_t OCU_OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocsb10_field_t OCSB10_f; + __IO uint8_t OCU_OCSB10; + stc_mft_ocu_ocsb10_field_t OCU_OCSB10_f; + }; + union { + __IO uint16_t OCSD10; + stc_mft_ocsd10_field_t OCSD10_f; + struct { + __IO uint8_t OCSD10L; + __IO uint8_t OCSD10H; + }; + __IO uint16_t OCU_OCSD10; + stc_mft_ocu_ocsd10_field_t OCU_OCSD10_f; + struct { + __IO uint8_t OCU_OCSD10L; + __IO uint8_t OCU_OCSD10H; + }; + }; + union { + __IO uint8_t OCSA32; + stc_mft_ocsa32_field_t OCSA32_f; + __IO uint8_t OCU_OCSA32; + stc_mft_ocu_ocsa32_field_t OCU_OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocsb32_field_t OCSB32_f; + __IO uint8_t OCU_OCSB32; + stc_mft_ocu_ocsb32_field_t OCU_OCSB32_f; + }; + union { + __IO uint16_t OCSD32; + stc_mft_ocsd32_field_t OCSD32_f; + struct { + __IO uint8_t OCSD32L; + __IO uint8_t OCSD32H; + }; + __IO uint16_t OCU_OCSD32; + stc_mft_ocu_ocsd32_field_t OCU_OCSD32_f; + struct { + __IO uint8_t OCU_OCSD32L; + __IO uint8_t OCU_OCSD32H; + }; + }; + union { + __IO uint8_t OCSA54; + stc_mft_ocsa54_field_t OCSA54_f; + __IO uint8_t OCU_OCSA54; + stc_mft_ocu_ocsa54_field_t OCU_OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocsb54_field_t OCSB54_f; + __IO uint8_t OCU_OCSB54; + stc_mft_ocu_ocsb54_field_t OCU_OCSB54_f; + }; + union { + __IO uint16_t OCSD54; + stc_mft_ocsd54_field_t OCSD54_f; + struct { + __IO uint8_t OCSD54L; + __IO uint8_t OCSD54H; + }; + __IO uint16_t OCU_OCSD54; + stc_mft_ocu_ocsd54_field_t OCU_OCSD54_f; + struct { + __IO uint8_t OCU_OCSD54L; + __IO uint8_t OCU_OCSD54H; + }; + }; + __IO uint8_t RESERVED6[1]; + union { + __IO uint8_t OCSC; + stc_mft_ocsc_field_t OCSC_f; + __IO uint8_t OCU_OCSC; + stc_mft_ocu_ocsc_field_t OCU_OCSC_f; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint16_t OCSE0; + stc_mft_ocse0_field_t OCSE0_f; + struct { + __IO uint8_t OCSE0L; + __IO uint8_t OCSE0H; + }; + __IO uint16_t OCU_OCSE0; + stc_mft_ocu_ocse0_field_t OCU_OCSE0_f; + struct { + __IO uint8_t OCU_OCSE0L; + __IO uint8_t OCU_OCSE0H; + }; + }; + __IO uint8_t RESERVED8[2]; + union { + __IO uint32_t OCSE1; + stc_mft_ocse1_field_t OCSE1_f; + struct { + union { + __IO uint16_t OCSE1L; + struct { + __IO uint8_t OCSE1LL; + __IO uint8_t OCSE1LH; + }; + }; + union { + __IO uint16_t OCSE1H; + struct { + __IO uint8_t OCSE1HL; + __IO uint8_t OCSE1HH; + }; + }; + }; + __IO uint32_t OCU_OCSE1; + stc_mft_ocu_ocse1_field_t OCU_OCSE1_f; + struct { + union { + __IO uint16_t OCU_OCSE1L; + struct { + __IO uint8_t OCU_OCSE1LL; + __IO uint8_t OCU_OCSE1LH; + }; + }; + union { + __IO uint16_t OCU_OCSE1H; + struct { + __IO uint8_t OCU_OCSE1HL; + __IO uint8_t OCU_OCSE1HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE2; + stc_mft_ocse2_field_t OCSE2_f; + struct { + __IO uint8_t OCSE2L; + __IO uint8_t OCSE2H; + }; + __IO uint16_t OCU_OCSE2; + stc_mft_ocu_ocse2_field_t OCU_OCSE2_f; + struct { + __IO uint8_t OCU_OCSE2L; + __IO uint8_t OCU_OCSE2H; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint32_t OCSE3; + stc_mft_ocse3_field_t OCSE3_f; + struct { + union { + __IO uint16_t OCSE3L; + struct { + __IO uint8_t OCSE3LL; + __IO uint8_t OCSE3LH; + }; + }; + union { + __IO uint16_t OCSE3H; + struct { + __IO uint8_t OCSE3HL; + __IO uint8_t OCSE3HH; + }; + }; + }; + __IO uint32_t OCU_OCSE3; + stc_mft_ocu_ocse3_field_t OCU_OCSE3_f; + struct { + union { + __IO uint16_t OCU_OCSE3L; + struct { + __IO uint8_t OCU_OCSE3LL; + __IO uint8_t OCU_OCSE3LH; + }; + }; + union { + __IO uint16_t OCU_OCSE3H; + struct { + __IO uint8_t OCU_OCSE3HL; + __IO uint8_t OCU_OCSE3HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE4; + stc_mft_ocse4_field_t OCSE4_f; + struct { + __IO uint8_t OCSE4L; + __IO uint8_t OCSE4H; + }; + __IO uint16_t OCU_OCSE4; + stc_mft_ocu_ocse4_field_t OCU_OCSE4_f; + struct { + __IO uint8_t OCU_OCSE4L; + __IO uint8_t OCU_OCSE4H; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint32_t OCSE5; + stc_mft_ocse5_field_t OCSE5_f; + struct { + union { + __IO uint16_t OCSE5L; + struct { + __IO uint8_t OCSE5LL; + __IO uint8_t OCSE5LH; + }; + }; + union { + __IO uint16_t OCSE5H; + struct { + __IO uint8_t OCSE5HL; + __IO uint8_t OCSE5HH; + }; + }; + }; + __IO uint32_t OCU_OCSE5; + stc_mft_ocu_ocse5_field_t OCU_OCSE5_f; + struct { + union { + __IO uint16_t OCU_OCSE5L; + struct { + __IO uint8_t OCU_OCSE5LL; + __IO uint8_t OCU_OCSE5LH; + }; + }; + union { + __IO uint16_t OCU_OCSE5H; + struct { + __IO uint8_t OCU_OCSE5HL; + __IO uint8_t OCU_OCSE5HH; + }; + }; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t TCCP0; + stc_mft_tccp0_field_t TCCP0_f; + struct { + __IO uint8_t TCCP0L; + __IO uint8_t TCCP0H; + }; + __IO uint16_t FRT_TCCP0; + stc_mft_frt_tccp0_field_t FRT_TCCP0_f; + struct { + __IO uint8_t FRT_TCCP0L; + __IO uint8_t FRT_TCCP0H; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint16_t TCDT0; + struct { + __IO uint8_t TCDT0L; + __IO uint8_t TCDT0H; + }; + __IO uint16_t FRT_TCDT0; + struct { + __IO uint8_t FRT_TCDT0L; + __IO uint8_t FRT_TCDT0H; + }; + }; + union { + __IO uint16_t TCSA0; + stc_mft_tcsa0_field_t TCSA0_f; + struct { + __IO uint8_t TCSA0L; + __IO uint8_t TCSA0H; + }; + __IO uint16_t FRT_TCSA0; + stc_mft_frt_tcsa0_field_t FRT_TCSA0_f; + struct { + __IO uint8_t FRT_TCSA0L; + __IO uint8_t FRT_TCSA0H; + }; + }; + union { + __IO uint16_t TCSC0; + stc_mft_tcsc0_field_t TCSC0_f; + struct { + __IO uint8_t TCSC0L; + __IO uint8_t TCSC0H; + }; + __IO uint16_t FRT_TCSC0; + stc_mft_frt_tcsc0_field_t FRT_TCSC0_f; + struct { + __IO uint8_t FRT_TCSC0L; + __IO uint8_t FRT_TCSC0H; + }; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint16_t TCCP1; + stc_mft_tccp1_field_t TCCP1_f; + struct { + __IO uint8_t TCCP1L; + __IO uint8_t TCCP1H; + }; + __IO uint16_t FRT_TCCP1; + stc_mft_frt_tccp1_field_t FRT_TCCP1_f; + struct { + __IO uint8_t FRT_TCCP1L; + __IO uint8_t FRT_TCCP1H; + }; + }; + __IO uint8_t RESERVED14[2]; + union { + __IO uint16_t TCDT1; + struct { + __IO uint8_t TCDT1L; + __IO uint8_t TCDT1H; + }; + __IO uint16_t FRT_TCDT1; + struct { + __IO uint8_t FRT_TCDT1L; + __IO uint8_t FRT_TCDT1H; + }; + }; + union { + __IO uint16_t TCSA1; + stc_mft_tcsa1_field_t TCSA1_f; + struct { + __IO uint8_t TCSA1L; + __IO uint8_t TCSA1H; + }; + __IO uint16_t FRT_TCSA1; + stc_mft_frt_tcsa1_field_t FRT_TCSA1_f; + struct { + __IO uint8_t FRT_TCSA1L; + __IO uint8_t FRT_TCSA1H; + }; + }; + union { + __IO uint16_t TCSC1; + stc_mft_tcsc1_field_t TCSC1_f; + struct { + __IO uint8_t TCSC1L; + __IO uint8_t TCSC1H; + }; + __IO uint16_t FRT_TCSC1; + stc_mft_frt_tcsc1_field_t FRT_TCSC1_f; + struct { + __IO uint8_t FRT_TCSC1L; + __IO uint8_t FRT_TCSC1H; + }; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint16_t TCCP2; + stc_mft_tccp2_field_t TCCP2_f; + struct { + __IO uint8_t TCCP2L; + __IO uint8_t TCCP2H; + }; + __IO uint16_t FRT_TCCP2; + stc_mft_frt_tccp2_field_t FRT_TCCP2_f; + struct { + __IO uint8_t FRT_TCCP2L; + __IO uint8_t FRT_TCCP2H; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint16_t TCDT2; + struct { + __IO uint8_t TCDT2L; + __IO uint8_t TCDT2H; + }; + __IO uint16_t FRT_TCDT2; + struct { + __IO uint8_t FRT_TCDT2L; + __IO uint8_t FRT_TCDT2H; + }; + }; + union { + __IO uint16_t TCSA2; + stc_mft_tcsa2_field_t TCSA2_f; + struct { + __IO uint8_t TCSA2L; + __IO uint8_t TCSA2H; + }; + __IO uint16_t FRT_TCSA2; + stc_mft_frt_tcsa2_field_t FRT_TCSA2_f; + struct { + __IO uint8_t FRT_TCSA2L; + __IO uint8_t FRT_TCSA2H; + }; + }; + union { + __IO uint16_t TCSC2; + stc_mft_tcsc2_field_t TCSC2_f; + struct { + __IO uint8_t TCSC2L; + __IO uint8_t TCSC2H; + }; + __IO uint16_t FRT_TCSC2; + stc_mft_frt_tcsc2_field_t FRT_TCSC2_f; + struct { + __IO uint8_t FRT_TCSC2L; + __IO uint8_t FRT_TCSC2H; + }; + }; + union { + __IO uint32_t TCAL; + stc_mft_tcal_field_t TCAL_f; + struct { + union { + __IO uint16_t TCALL; + struct { + __IO uint8_t TCALLL; + __IO uint8_t TCALLH; + }; + }; + union { + __IO uint16_t TCALH; + struct { + __IO uint8_t TCALHL; + __IO uint8_t TCALHH; + }; + }; + }; + __IO uint32_t FRT_TCAL; + stc_mft_frt_tcal_field_t FRT_TCAL_f; + struct { + union { + __IO uint16_t FRT_TCALL; + struct { + __IO uint8_t FRT_TCALLL; + __IO uint8_t FRT_TCALLH; + }; + }; + union { + __IO uint16_t FRT_TCALH; + struct { + __IO uint8_t FRT_TCALHL; + __IO uint8_t FRT_TCALHH; + }; + }; + }; + }; + union { + __IO uint8_t OCFS10; + stc_mft_ocfs10_field_t OCFS10_f; + __IO uint8_t OCU_OCFS10; + stc_mft_ocu_ocfs10_field_t OCU_OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocfs32_field_t OCFS32_f; + __IO uint8_t OCU_OCFS32; + stc_mft_ocu_ocfs32_field_t OCU_OCFS32_f; + }; + union { + __IO uint8_t OCFS54; + stc_mft_ocfs54_field_t OCFS54_f; + __IO uint8_t OCU_OCFS54; + stc_mft_ocu_ocfs54_field_t OCU_OCFS54_f; + }; + __IO uint8_t RESERVED17[1]; + union { + __IO uint8_t ICFS10; + stc_mft_icfs10_field_t ICFS10_f; + __IO uint8_t ICU_ICFS10; + stc_mft_icu_icfs10_field_t ICU_ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icfs32_field_t ICFS32_f; + __IO uint8_t ICU_ICFS32; + stc_mft_icu_icfs32_field_t ICU_ICFS32_f; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint8_t ACFS10; + stc_mft_acfs10_field_t ACFS10_f; + __IO uint8_t ADCMP_ACFS10; + stc_mft_adcmp_acfs10_field_t ADCMP_ACFS10_f; + }; + union { + __IO uint8_t ACFS32; + stc_mft_acfs32_field_t ACFS32_f; + __IO uint8_t ADCMP_ACFS32; + stc_mft_adcmp_acfs32_field_t ADCMP_ACFS32_f; + }; + union { + __IO uint8_t ACFS54; + stc_mft_acfs54_field_t ACFS54_f; + __IO uint8_t ADCMP_ACFS54; + stc_mft_adcmp_acfs54_field_t ADCMP_ACFS54_f; + }; + __IO uint8_t RESERVED19[3]; + union { + __IO uint16_t ICCP0; + struct { + __IO uint8_t ICCP0L; + __IO uint8_t ICCP0H; + }; + __IO uint16_t ICU_ICCP0; + struct { + __IO uint8_t ICU_ICCP0L; + __IO uint8_t ICU_ICCP0H; + }; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint16_t ICCP1; + struct { + __IO uint8_t ICCP1L; + __IO uint8_t ICCP1H; + }; + __IO uint16_t ICU_ICCP1; + struct { + __IO uint8_t ICU_ICCP1L; + __IO uint8_t ICU_ICCP1H; + }; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint16_t ICCP2; + struct { + __IO uint8_t ICCP2L; + __IO uint8_t ICCP2H; + }; + __IO uint16_t ICU_ICCP2; + struct { + __IO uint8_t ICU_ICCP2L; + __IO uint8_t ICU_ICCP2H; + }; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint16_t ICCP3; + struct { + __IO uint8_t ICCP3L; + __IO uint8_t ICCP3H; + }; + __IO uint16_t ICU_ICCP3; + struct { + __IO uint8_t ICU_ICCP3L; + __IO uint8_t ICU_ICCP3H; + }; + }; + union { + __IO uint8_t ICSA10; + stc_mft_icsa10_field_t ICSA10_f; + __IO uint8_t ICU_ICSA10; + stc_mft_icu_icsa10_field_t ICU_ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icsb10_field_t ICSB10_f; + __IO uint8_t ICU_ICSB10; + stc_mft_icu_icsb10_field_t ICU_ICSB10_f; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icsa32_field_t ICSA32_f; + __IO uint8_t ICU_ICSA32; + stc_mft_icu_icsa32_field_t ICU_ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icsb32_field_t ICSB32_f; + __IO uint8_t ICU_ICSB32; + stc_mft_icu_icsb32_field_t ICU_ICSB32_f; + }; + __IO uint8_t RESERVED24[4]; + union { + __IO uint16_t WFTF10; + struct { + __IO uint8_t WFTF10L; + __IO uint8_t WFTF10H; + }; + __IO uint16_t WFG_WFTF10; + struct { + __IO uint8_t WFG_WFTF10L; + __IO uint8_t WFG_WFTF10H; + }; + }; + union { + __IO uint16_t WFTA10; + struct { + __IO uint8_t WFTA10L; + __IO uint8_t WFTA10H; + }; + __IO uint16_t WFG_WFTA10; + struct { + __IO uint8_t WFG_WFTA10L; + __IO uint8_t WFG_WFTA10H; + }; + }; + union { + __IO uint16_t WFTB10; + struct { + __IO uint8_t WFTB10L; + __IO uint8_t WFTB10H; + }; + __IO uint16_t WFG_WFTB10; + struct { + __IO uint8_t WFG_WFTB10L; + __IO uint8_t WFG_WFTB10H; + }; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint16_t WFTF32; + struct { + __IO uint8_t WFTF32L; + __IO uint8_t WFTF32H; + }; + __IO uint16_t WFG_WFTF32; + struct { + __IO uint8_t WFG_WFTF32L; + __IO uint8_t WFG_WFTF32H; + }; + }; + union { + __IO uint16_t WFTA32; + struct { + __IO uint8_t WFTA32L; + __IO uint8_t WFTA32H; + }; + __IO uint16_t WFG_WFTA32; + struct { + __IO uint8_t WFG_WFTA32L; + __IO uint8_t WFG_WFTA32H; + }; + }; + union { + __IO uint16_t WFTB32; + struct { + __IO uint8_t WFTB32L; + __IO uint8_t WFTB32H; + }; + __IO uint16_t WFG_WFTB32; + struct { + __IO uint8_t WFG_WFTB32L; + __IO uint8_t WFG_WFTB32H; + }; + }; + __IO uint8_t RESERVED26[2]; + union { + __IO uint16_t WFTF54; + struct { + __IO uint8_t WFTF54L; + __IO uint8_t WFTF54H; + }; + __IO uint16_t WFG_WFTF54; + struct { + __IO uint8_t WFG_WFTF54L; + __IO uint8_t WFG_WFTF54H; + }; + }; + union { + __IO uint16_t WFTA54; + struct { + __IO uint8_t WFTA54L; + __IO uint8_t WFTA54H; + }; + __IO uint16_t WFG_WFTA54; + struct { + __IO uint8_t WFG_WFTA54L; + __IO uint8_t WFG_WFTA54H; + }; + }; + union { + __IO uint16_t WFTB54; + struct { + __IO uint8_t WFTB54L; + __IO uint8_t WFTB54H; + }; + __IO uint16_t WFG_WFTB54; + struct { + __IO uint8_t WFG_WFTB54L; + __IO uint8_t WFG_WFTB54H; + }; + }; + union { + __IO uint16_t WFSA10; + stc_mft_wfsa10_field_t WFSA10_f; + struct { + __IO uint8_t WFSA10L; + __IO uint8_t WFSA10H; + }; + __IO uint16_t WFG_WFSA10; + stc_mft_wfg_wfsa10_field_t WFG_WFSA10_f; + struct { + __IO uint8_t WFG_WFSA10L; + __IO uint8_t WFG_WFSA10H; + }; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfsa32_field_t WFSA32_f; + struct { + __IO uint8_t WFSA32L; + __IO uint8_t WFSA32H; + }; + __IO uint16_t WFG_WFSA32; + stc_mft_wfg_wfsa32_field_t WFG_WFSA32_f; + struct { + __IO uint8_t WFG_WFSA32L; + __IO uint8_t WFG_WFSA32H; + }; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfsa54_field_t WFSA54_f; + struct { + __IO uint8_t WFSA54L; + __IO uint8_t WFSA54H; + }; + __IO uint16_t WFG_WFSA54; + stc_mft_wfg_wfsa54_field_t WFG_WFSA54_f; + struct { + __IO uint8_t WFG_WFSA54L; + __IO uint8_t WFG_WFSA54H; + }; + }; + __IO uint8_t RESERVED29[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfir_field_t WFIR_f; + struct { + __IO uint8_t WFIRL; + __IO uint8_t WFIRH; + }; + __IO uint16_t WFG_WFIR; + stc_mft_wfg_wfir_field_t WFG_WFIR_f; + struct { + __IO uint8_t WFG_WFIRL; + __IO uint8_t WFG_WFIRH; + }; + }; + __IO uint8_t RESERVED30[2]; + union { + __IO uint16_t NZCL; + stc_mft_nzcl_field_t NZCL_f; + struct { + __IO uint8_t NZCLL; + __IO uint8_t NZCLH; + }; + __IO uint16_t WFG_NZCL; + stc_mft_wfg_nzcl_field_t WFG_NZCL_f; + struct { + __IO uint8_t WFG_NZCLL; + __IO uint8_t WFG_NZCLH; + }; + }; + __IO uint8_t RESERVED31[4]; + union { + __IO uint16_t ACMP0; + stc_mft_acmp0_field_t ACMP0_f; + struct { + __IO uint8_t ACMP0L; + __IO uint8_t ACMP0H; + }; + __IO uint16_t ADCMP_ACMP0; + stc_mft_adcmp_acmp0_field_t ADCMP_ACMP0_f; + struct { + __IO uint8_t ADCMP_ACMP0L; + __IO uint8_t ADCMP_ACMP0H; + }; + }; + __IO uint8_t RESERVED32[2]; + union { + __IO uint16_t ACMP1; + stc_mft_acmp1_field_t ACMP1_f; + struct { + __IO uint8_t ACMP1L; + __IO uint8_t ACMP1H; + }; + __IO uint16_t ADCMP_ACMP1; + stc_mft_adcmp_acmp1_field_t ADCMP_ACMP1_f; + struct { + __IO uint8_t ADCMP_ACMP1L; + __IO uint8_t ADCMP_ACMP1H; + }; + }; + __IO uint8_t RESERVED33[2]; + union { + __IO uint16_t ACMP2; + stc_mft_acmp2_field_t ACMP2_f; + struct { + __IO uint8_t ACMP2L; + __IO uint8_t ACMP2H; + }; + __IO uint16_t ADCMP_ACMP2; + stc_mft_adcmp_acmp2_field_t ADCMP_ACMP2_f; + struct { + __IO uint8_t ADCMP_ACMP2L; + __IO uint8_t ADCMP_ACMP2H; + }; + }; + __IO uint8_t RESERVED34[2]; + union { + __IO uint16_t ACMP3; + stc_mft_acmp3_field_t ACMP3_f; + struct { + __IO uint8_t ACMP3L; + __IO uint8_t ACMP3H; + }; + __IO uint16_t ADCMP_ACMP3; + stc_mft_adcmp_acmp3_field_t ADCMP_ACMP3_f; + struct { + __IO uint8_t ADCMP_ACMP3L; + __IO uint8_t ADCMP_ACMP3H; + }; + }; + __IO uint8_t RESERVED35[2]; + union { + __IO uint16_t ACMP4; + stc_mft_acmp4_field_t ACMP4_f; + struct { + __IO uint8_t ACMP4L; + __IO uint8_t ACMP4H; + }; + __IO uint16_t ADCMP_ACMP4; + stc_mft_adcmp_acmp4_field_t ADCMP_ACMP4_f; + struct { + __IO uint8_t ADCMP_ACMP4L; + __IO uint8_t ADCMP_ACMP4H; + }; + }; + __IO uint8_t RESERVED36[2]; + union { + __IO uint16_t ACMP5; + stc_mft_acmp5_field_t ACMP5_f; + struct { + __IO uint8_t ACMP5L; + __IO uint8_t ACMP5H; + }; + __IO uint16_t ADCMP_ACMP5; + stc_mft_adcmp_acmp5_field_t ADCMP_ACMP5_f; + struct { + __IO uint8_t ADCMP_ACMP5L; + __IO uint8_t ADCMP_ACMP5H; + }; + }; + union { + __IO uint16_t ACSA; + stc_mft_acsa_field_t ACSA_f; + struct { + __IO uint8_t ACSAL; + __IO uint8_t ACSAH; + }; + __IO uint16_t ADCMP_ACSA; + stc_mft_adcmp_acsa_field_t ADCMP_ACSA_f; + struct { + __IO uint8_t ADCMP_ACSAL; + __IO uint8_t ADCMP_ACSAH; + }; + }; + __IO uint8_t RESERVED37[2]; + union { + __IO uint8_t ACSC0; + stc_mft_acsc0_field_t ACSC0_f; + __IO uint8_t ADCMP_ACSC0; + stc_mft_adcmp_acsc0_field_t ADCMP_ACSC0_f; + }; + union { + __IO uint8_t ACSD0; + stc_mft_acsd0_field_t ACSD0_f; + __IO uint8_t ADCMP_ACSD0; + stc_mft_adcmp_acsd0_field_t ADCMP_ACSD0_f; + }; + union { + __IO uint8_t ACMC0; + stc_mft_acmc0_field_t ACMC0_f; + __IO uint8_t ADCMP_ACMC0; + stc_mft_adcmp_acmc0_field_t ADCMP_ACMC0_f; + }; + __IO uint8_t RESERVED38[1]; + union { + __IO uint8_t ACSC1; + stc_mft_acsc1_field_t ACSC1_f; + __IO uint8_t ADCMP_ACSC1; + stc_mft_adcmp_acsc1_field_t ADCMP_ACSC1_f; + }; + union { + __IO uint8_t ACSD1; + stc_mft_acsd1_field_t ACSD1_f; + __IO uint8_t ADCMP_ACSD1; + stc_mft_adcmp_acsd1_field_t ADCMP_ACSD1_f; + }; + union { + __IO uint8_t ACMC1; + stc_mft_acmc1_field_t ACMC1_f; + __IO uint8_t ADCMP_ACMC1; + stc_mft_adcmp_acmc1_field_t ADCMP_ACMC1_f; + }; + __IO uint8_t RESERVED39[1]; + union { + __IO uint8_t ACSC2; + stc_mft_acsc2_field_t ACSC2_f; + __IO uint8_t ADCMP_ACSC2; + stc_mft_adcmp_acsc2_field_t ADCMP_ACSC2_f; + }; + union { + __IO uint8_t ACSD2; + stc_mft_acsd2_field_t ACSD2_f; + __IO uint8_t ADCMP_ACSD2; + stc_mft_adcmp_acsd2_field_t ADCMP_ACSD2_f; + }; + union { + __IO uint8_t ACMC2; + stc_mft_acmc2_field_t ACMC2_f; + __IO uint8_t ADCMP_ACMC2; + stc_mft_adcmp_acmc2_field_t ADCMP_ACMC2_f; + }; + __IO uint8_t RESERVED40[1]; + union { + __IO uint8_t ACSC3; + stc_mft_acsc3_field_t ACSC3_f; + __IO uint8_t ADCMP_ACSC3; + stc_mft_adcmp_acsc3_field_t ADCMP_ACSC3_f; + }; + union { + __IO uint8_t ACSD3; + stc_mft_acsd3_field_t ACSD3_f; + __IO uint8_t ADCMP_ACSD3; + stc_mft_adcmp_acsd3_field_t ADCMP_ACSD3_f; + }; + union { + __IO uint8_t ACMC3; + stc_mft_acmc3_field_t ACMC3_f; + __IO uint8_t ADCMP_ACMC3; + stc_mft_adcmp_acmc3_field_t ADCMP_ACMC3_f; + }; + __IO uint8_t RESERVED41[1]; + union { + __IO uint8_t ACSC4; + stc_mft_acsc4_field_t ACSC4_f; + __IO uint8_t ADCMP_ACSC4; + stc_mft_adcmp_acsc4_field_t ADCMP_ACSC4_f; + }; + union { + __IO uint8_t ACSD4; + stc_mft_acsd4_field_t ACSD4_f; + __IO uint8_t ADCMP_ACSD4; + stc_mft_adcmp_acsd4_field_t ADCMP_ACSD4_f; + }; + union { + __IO uint8_t ACMC4; + stc_mft_acmc4_field_t ACMC4_f; + __IO uint8_t ADCMP_ACMC4; + stc_mft_adcmp_acmc4_field_t ADCMP_ACMC4_f; + }; + __IO uint8_t RESERVED42[1]; + union { + __IO uint8_t ACSC5; + stc_mft_acsc5_field_t ACSC5_f; + __IO uint8_t ADCMP_ACSC5; + stc_mft_adcmp_acsc5_field_t ADCMP_ACSC5_f; + }; + union { + __IO uint8_t ACSD5; + stc_mft_acsd5_field_t ACSD5_f; + __IO uint8_t ADCMP_ACSD5; + stc_mft_adcmp_acsd5_field_t ADCMP_ACSD5_f; + }; + union { + __IO uint8_t ACMC5; + stc_mft_acmc5_field_t ACMC5_f; + __IO uint8_t ADCMP_ACMC5; + stc_mft_adcmp_acmc5_field_t ADCMP_ACMC5_f; + }; + __IO uint8_t RESERVED43[1]; + union { + __IO uint8_t TCSD; + stc_mft_tcsd_field_t TCSD_f; + __IO uint8_t FRT_TCSD; + stc_mft_frt_tcsd_field_t FRT_TCSD_f; + }; +} FM_MFT_TypeDef, FM4_MFT_TypeDef; + +/******************************************************************************* +* MFT_ADCMP_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED44[368]; + union { + __IO uint8_t ACFS10; + stc_mft_adcmp_acfs10_field_t ACFS10_f; + }; + union { + __IO uint8_t ACFS32; + stc_mft_adcmp_acfs32_field_t ACFS32_f; + }; + union { + __IO uint8_t ACFS54; + stc_mft_adcmp_acfs54_field_t ACFS54_f; + }; + __IO uint8_t RESERVED45[71]; + union { + __IO uint16_t ACMP0; + stc_mft_adcmp_acmp0_field_t ACMP0_f; + struct { + __IO uint8_t ACMP0L; + __IO uint8_t ACMP0H; + }; + }; + __IO uint8_t RESERVED46[2]; + union { + __IO uint16_t ACMP1; + stc_mft_adcmp_acmp1_field_t ACMP1_f; + struct { + __IO uint8_t ACMP1L; + __IO uint8_t ACMP1H; + }; + }; + __IO uint8_t RESERVED47[2]; + union { + __IO uint16_t ACMP2; + stc_mft_adcmp_acmp2_field_t ACMP2_f; + struct { + __IO uint8_t ACMP2L; + __IO uint8_t ACMP2H; + }; + }; + __IO uint8_t RESERVED48[2]; + union { + __IO uint16_t ACMP3; + stc_mft_adcmp_acmp3_field_t ACMP3_f; + struct { + __IO uint8_t ACMP3L; + __IO uint8_t ACMP3H; + }; + }; + __IO uint8_t RESERVED49[2]; + union { + __IO uint16_t ACMP4; + stc_mft_adcmp_acmp4_field_t ACMP4_f; + struct { + __IO uint8_t ACMP4L; + __IO uint8_t ACMP4H; + }; + }; + __IO uint8_t RESERVED50[2]; + union { + __IO uint16_t ACMP5; + stc_mft_adcmp_acmp5_field_t ACMP5_f; + struct { + __IO uint8_t ACMP5L; + __IO uint8_t ACMP5H; + }; + }; + union { + __IO uint16_t ACSA; + stc_mft_adcmp_acsa_field_t ACSA_f; + struct { + __IO uint8_t ACSAL; + __IO uint8_t ACSAH; + }; + }; + __IO uint8_t RESERVED51[2]; + union { + __IO uint8_t ACSC0; + stc_mft_adcmp_acsc0_field_t ACSC0_f; + }; + union { + __IO uint8_t ACSD0; + stc_mft_adcmp_acsd0_field_t ACSD0_f; + }; + union { + __IO uint8_t ACMC0; + stc_mft_adcmp_acmc0_field_t ACMC0_f; + }; + __IO uint8_t RESERVED52[1]; + union { + __IO uint8_t ACSC1; + stc_mft_adcmp_acsc1_field_t ACSC1_f; + }; + union { + __IO uint8_t ACSD1; + stc_mft_adcmp_acsd1_field_t ACSD1_f; + }; + union { + __IO uint8_t ACMC1; + stc_mft_adcmp_acmc1_field_t ACMC1_f; + }; + __IO uint8_t RESERVED53[1]; + union { + __IO uint8_t ACSC2; + stc_mft_adcmp_acsc2_field_t ACSC2_f; + }; + union { + __IO uint8_t ACSD2; + stc_mft_adcmp_acsd2_field_t ACSD2_f; + }; + union { + __IO uint8_t ACMC2; + stc_mft_adcmp_acmc2_field_t ACMC2_f; + }; + __IO uint8_t RESERVED54[1]; + union { + __IO uint8_t ACSC3; + stc_mft_adcmp_acsc3_field_t ACSC3_f; + }; + union { + __IO uint8_t ACSD3; + stc_mft_adcmp_acsd3_field_t ACSD3_f; + }; + union { + __IO uint8_t ACMC3; + stc_mft_adcmp_acmc3_field_t ACMC3_f; + }; + __IO uint8_t RESERVED55[1]; + union { + __IO uint8_t ACSC4; + stc_mft_adcmp_acsc4_field_t ACSC4_f; + }; + union { + __IO uint8_t ACSD4; + stc_mft_adcmp_acsd4_field_t ACSD4_f; + }; + union { + __IO uint8_t ACMC4; + stc_mft_adcmp_acmc4_field_t ACMC4_f; + }; + __IO uint8_t RESERVED56[1]; + union { + __IO uint8_t ACSC5; + stc_mft_adcmp_acsc5_field_t ACSC5_f; + }; + union { + __IO uint8_t ACSD5; + stc_mft_adcmp_acsd5_field_t ACSD5_f; + }; + union { + __IO uint8_t ACMC5; + stc_mft_adcmp_acmc5_field_t ACMC5_f; + }; +} FM_MFT_ADCMP_TypeDef, FM4_MFT_ADCMP_TypeDef; + +/******************************************************************************* +* MFT_FRT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED57[322]; + union { + __IO uint16_t TCCP0; + stc_mft_frt_tccp0_field_t TCCP0_f; + struct { + __IO uint8_t TCCP0L; + __IO uint8_t TCCP0H; + }; + }; + __IO uint8_t RESERVED58[2]; + union { + __IO uint16_t TCDT0; + struct { + __IO uint8_t TCDT0L; + __IO uint8_t TCDT0H; + }; + }; + union { + __IO uint16_t TCSA0; + stc_mft_frt_tcsa0_field_t TCSA0_f; + struct { + __IO uint8_t TCSA0L; + __IO uint8_t TCSA0H; + }; + }; + union { + __IO uint16_t TCSC0; + stc_mft_frt_tcsc0_field_t TCSC0_f; + struct { + __IO uint8_t TCSC0L; + __IO uint8_t TCSC0H; + }; + }; + __IO uint8_t RESERVED59[2]; + union { + __IO uint16_t TCCP1; + stc_mft_frt_tccp1_field_t TCCP1_f; + struct { + __IO uint8_t TCCP1L; + __IO uint8_t TCCP1H; + }; + }; + __IO uint8_t RESERVED60[2]; + union { + __IO uint16_t TCDT1; + struct { + __IO uint8_t TCDT1L; + __IO uint8_t TCDT1H; + }; + }; + union { + __IO uint16_t TCSA1; + stc_mft_frt_tcsa1_field_t TCSA1_f; + struct { + __IO uint8_t TCSA1L; + __IO uint8_t TCSA1H; + }; + }; + union { + __IO uint16_t TCSC1; + stc_mft_frt_tcsc1_field_t TCSC1_f; + struct { + __IO uint8_t TCSC1L; + __IO uint8_t TCSC1H; + }; + }; + __IO uint8_t RESERVED61[2]; + union { + __IO uint16_t TCCP2; + stc_mft_frt_tccp2_field_t TCCP2_f; + struct { + __IO uint8_t TCCP2L; + __IO uint8_t TCCP2H; + }; + }; + __IO uint8_t RESERVED62[2]; + union { + __IO uint16_t TCDT2; + struct { + __IO uint8_t TCDT2L; + __IO uint8_t TCDT2H; + }; + }; + union { + __IO uint16_t TCSA2; + stc_mft_frt_tcsa2_field_t TCSA2_f; + struct { + __IO uint8_t TCSA2L; + __IO uint8_t TCSA2H; + }; + }; + union { + __IO uint16_t TCSC2; + stc_mft_frt_tcsc2_field_t TCSC2_f; + struct { + __IO uint8_t TCSC2L; + __IO uint8_t TCSC2H; + }; + }; + union { + __IO uint32_t TCAL; + stc_mft_frt_tcal_field_t TCAL_f; + struct { + union { + __IO uint16_t TCALL; + struct { + __IO uint8_t TCALLL; + __IO uint8_t TCALLH; + }; + }; + union { + __IO uint16_t TCALH; + struct { + __IO uint8_t TCALHL; + __IO uint8_t TCALHH; + }; + }; + }; + }; + __IO uint8_t RESERVED63[132]; + union { + __IO uint8_t TCSD; + stc_mft_frt_tcsd_field_t TCSD_f; + }; +} FM_MFT_FRT_TypeDef, FM4_MFT_FRT_TypeDef; + +/******************************************************************************* +* MFT_ICU_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED64[364]; + union { + __IO uint8_t ICFS10; + stc_mft_icu_icfs10_field_t ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icu_icfs32_field_t ICFS32_f; + }; + __IO uint8_t RESERVED65[8]; + union { + __IO uint16_t ICCP0; + struct { + __IO uint8_t ICCP0L; + __IO uint8_t ICCP0H; + }; + }; + __IO uint8_t RESERVED66[2]; + union { + __IO uint16_t ICCP1; + struct { + __IO uint8_t ICCP1L; + __IO uint8_t ICCP1H; + }; + }; + __IO uint8_t RESERVED67[2]; + union { + __IO uint16_t ICCP2; + struct { + __IO uint8_t ICCP2L; + __IO uint8_t ICCP2H; + }; + }; + __IO uint8_t RESERVED68[2]; + union { + __IO uint16_t ICCP3; + struct { + __IO uint8_t ICCP3L; + __IO uint8_t ICCP3H; + }; + }; + union { + __IO uint8_t ICSA10; + stc_mft_icu_icsa10_field_t ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icu_icsb10_field_t ICSB10_f; + }; + __IO uint8_t RESERVED69[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icu_icsa32_field_t ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icu_icsb32_field_t ICSB32_f; + }; +} FM_MFT_ICU_TypeDef, FM4_MFT_ICU_TypeDef; + +/******************************************************************************* +* MFT_OCU_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED70[258]; + union { + __IO uint16_t OCCP0; + struct { + __IO uint8_t OCCP0L; + __IO uint8_t OCCP0H; + }; + }; + __IO uint8_t RESERVED71[2]; + union { + __IO uint16_t OCCP1; + struct { + __IO uint8_t OCCP1L; + __IO uint8_t OCCP1H; + }; + }; + __IO uint8_t RESERVED72[2]; + union { + __IO uint16_t OCCP2; + struct { + __IO uint8_t OCCP2L; + __IO uint8_t OCCP2H; + }; + }; + __IO uint8_t RESERVED73[2]; + union { + __IO uint16_t OCCP3; + struct { + __IO uint8_t OCCP3L; + __IO uint8_t OCCP3H; + }; + }; + __IO uint8_t RESERVED74[2]; + union { + __IO uint16_t OCCP4; + struct { + __IO uint8_t OCCP4L; + __IO uint8_t OCCP4H; + }; + }; + __IO uint8_t RESERVED75[2]; + union { + __IO uint16_t OCCP5; + struct { + __IO uint8_t OCCP5L; + __IO uint8_t OCCP5H; + }; + }; + union { + __IO uint8_t OCSA10; + stc_mft_ocu_ocsa10_field_t OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocu_ocsb10_field_t OCSB10_f; + }; + union { + __IO uint16_t OCSD10; + stc_mft_ocu_ocsd10_field_t OCSD10_f; + struct { + __IO uint8_t OCSD10L; + __IO uint8_t OCSD10H; + }; + }; + union { + __IO uint8_t OCSA32; + stc_mft_ocu_ocsa32_field_t OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocu_ocsb32_field_t OCSB32_f; + }; + union { + __IO uint16_t OCSD32; + stc_mft_ocu_ocsd32_field_t OCSD32_f; + struct { + __IO uint8_t OCSD32L; + __IO uint8_t OCSD32H; + }; + }; + union { + __IO uint8_t OCSA54; + stc_mft_ocu_ocsa54_field_t OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocu_ocsb54_field_t OCSB54_f; + }; + union { + __IO uint16_t OCSD54; + stc_mft_ocu_ocsd54_field_t OCSD54_f; + struct { + __IO uint8_t OCSD54L; + __IO uint8_t OCSD54H; + }; + }; + __IO uint8_t RESERVED76[1]; + union { + __IO uint8_t OCSC; + stc_mft_ocu_ocsc_field_t OCSC_f; + }; + __IO uint8_t RESERVED77[2]; + union { + __IO uint16_t OCSE0; + stc_mft_ocu_ocse0_field_t OCSE0_f; + struct { + __IO uint8_t OCSE0L; + __IO uint8_t OCSE0H; + }; + }; + __IO uint8_t RESERVED78[2]; + union { + __IO uint32_t OCSE1; + stc_mft_ocu_ocse1_field_t OCSE1_f; + struct { + union { + __IO uint16_t OCSE1L; + struct { + __IO uint8_t OCSE1LL; + __IO uint8_t OCSE1LH; + }; + }; + union { + __IO uint16_t OCSE1H; + struct { + __IO uint8_t OCSE1HL; + __IO uint8_t OCSE1HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE2; + stc_mft_ocu_ocse2_field_t OCSE2_f; + struct { + __IO uint8_t OCSE2L; + __IO uint8_t OCSE2H; + }; + }; + __IO uint8_t RESERVED79[2]; + union { + __IO uint32_t OCSE3; + stc_mft_ocu_ocse3_field_t OCSE3_f; + struct { + union { + __IO uint16_t OCSE3L; + struct { + __IO uint8_t OCSE3LL; + __IO uint8_t OCSE3LH; + }; + }; + union { + __IO uint16_t OCSE3H; + struct { + __IO uint8_t OCSE3HL; + __IO uint8_t OCSE3HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE4; + stc_mft_ocu_ocse4_field_t OCSE4_f; + struct { + __IO uint8_t OCSE4L; + __IO uint8_t OCSE4H; + }; + }; + __IO uint8_t RESERVED80[2]; + union { + __IO uint32_t OCSE5; + stc_mft_ocu_ocse5_field_t OCSE5_f; + struct { + union { + __IO uint16_t OCSE5L; + struct { + __IO uint8_t OCSE5LL; + __IO uint8_t OCSE5LH; + }; + }; + union { + __IO uint16_t OCSE5H; + struct { + __IO uint8_t OCSE5HL; + __IO uint8_t OCSE5HH; + }; + }; + }; + }; + __IO uint8_t RESERVED81[40]; + union { + __IO uint8_t OCFS10; + stc_mft_ocu_ocfs10_field_t OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocu_ocfs32_field_t OCFS32_f; + }; + union { + __IO uint8_t OCFS54; + stc_mft_ocu_ocfs54_field_t OCFS54_f; + }; +} FM_MFT_OCU_TypeDef, FM4_MFT_OCU_TypeDef; + +/******************************************************************************* +* MFT_WFG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED82[398]; + union { + __IO uint16_t WFTF10; + struct { + __IO uint8_t WFTF10L; + __IO uint8_t WFTF10H; + }; + }; + union { + __IO uint16_t WFTA10; + struct { + __IO uint8_t WFTA10L; + __IO uint8_t WFTA10H; + }; + }; + union { + __IO uint16_t WFTB10; + struct { + __IO uint8_t WFTB10L; + __IO uint8_t WFTB10H; + }; + }; + __IO uint8_t RESERVED83[2]; + union { + __IO uint16_t WFTF32; + struct { + __IO uint8_t WFTF32L; + __IO uint8_t WFTF32H; + }; + }; + union { + __IO uint16_t WFTA32; + struct { + __IO uint8_t WFTA32L; + __IO uint8_t WFTA32H; + }; + }; + union { + __IO uint16_t WFTB32; + struct { + __IO uint8_t WFTB32L; + __IO uint8_t WFTB32H; + }; + }; + __IO uint8_t RESERVED84[2]; + union { + __IO uint16_t WFTF54; + struct { + __IO uint8_t WFTF54L; + __IO uint8_t WFTF54H; + }; + }; + union { + __IO uint16_t WFTA54; + struct { + __IO uint8_t WFTA54L; + __IO uint8_t WFTA54H; + }; + }; + union { + __IO uint16_t WFTB54; + struct { + __IO uint8_t WFTB54L; + __IO uint8_t WFTB54H; + }; + }; + union { + __IO uint16_t WFSA10; + stc_mft_wfg_wfsa10_field_t WFSA10_f; + struct { + __IO uint8_t WFSA10L; + __IO uint8_t WFSA10H; + }; + }; + __IO uint8_t RESERVED85[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfg_wfsa32_field_t WFSA32_f; + struct { + __IO uint8_t WFSA32L; + __IO uint8_t WFSA32H; + }; + }; + __IO uint8_t RESERVED86[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfg_wfsa54_field_t WFSA54_f; + struct { + __IO uint8_t WFSA54L; + __IO uint8_t WFSA54H; + }; + }; + __IO uint8_t RESERVED87[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfg_wfir_field_t WFIR_f; + struct { + __IO uint8_t WFIRL; + __IO uint8_t WFIRH; + }; + }; + __IO uint8_t RESERVED88[2]; + union { + __IO uint16_t NZCL; + stc_mft_wfg_nzcl_field_t NZCL_f; + struct { + __IO uint8_t NZCLL; + __IO uint8_t NZCLH; + }; + }; +} FM_MFT_WFG_TypeDef, FM4_MFT_WFG_TypeDef; + +/******************************************************************************* +* MFT_PPG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t TTCR0; + stc_mft_ppg_ttcr0_field_t TTCR0_f; + }; + __IO uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + __IO uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + __IO uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + __IO uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + __IO uint8_t RESERVED5[12]; + union { + __IO uint8_t TTCR1; + stc_mft_ppg_ttcr1_field_t TTCR1_f; + }; + __IO uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + __IO uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + __IO uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + __IO uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + __IO uint8_t RESERVED10[12]; + union { + __IO uint8_t TTCR2; + stc_mft_ppg_ttcr2_field_t TTCR2_f; + }; + __IO uint8_t RESERVED11[7]; + __IO uint8_t COMP8; + __IO uint8_t RESERVED12[2]; + __IO uint8_t COMP10; + __IO uint8_t RESERVED13[4]; + __IO uint8_t COMP12; + __IO uint8_t RESERVED14[2]; + __IO uint8_t COMP14; + __IO uint8_t RESERVED15[171]; + union { + __IO uint16_t TRG0; + stc_mft_ppg_trg0_field_t TRG0_f; + struct { + __IO uint8_t TRG0L; + __IO uint8_t TRG0H; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint16_t REVC0; + stc_mft_ppg_revc0_field_t REVC0_f; + struct { + __IO uint8_t REVC0L; + __IO uint8_t REVC0H; + }; + }; + __IO uint8_t RESERVED17[58]; + union { + __IO uint16_t TRG1; + stc_mft_ppg_trg1_field_t TRG1_f; + struct { + __IO uint8_t TRG1L; + __IO uint8_t TRG1H; + }; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint16_t REVC1; + stc_mft_ppg_revc1_field_t REVC1_f; + struct { + __IO uint8_t REVC1L; + __IO uint8_t REVC1H; + }; + }; + __IO uint8_t RESERVED19[186]; + union { + __IO uint8_t PPGC1; + stc_mft_ppg_ppgc1_field_t PPGC1_f; + }; + union { + __IO uint8_t PPGC0; + stc_mft_ppg_ppgc0_field_t PPGC0_f; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint8_t PPGC3; + stc_mft_ppg_ppgc3_field_t PPGC3_f; + }; + union { + __IO uint8_t PPGC2; + stc_mft_ppg_ppgc2_field_t PPGC2_f; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint8_t PRLL0; + stc_mft_ppg_prll0_field_t PRLL0_f; + }; + union { + __IO uint8_t PRLH0; + stc_mft_ppg_prlh0_field_t PRLH0_f; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint8_t PRLL1; + stc_mft_ppg_prll1_field_t PRLL1_f; + }; + union { + __IO uint8_t PRLH1; + stc_mft_ppg_prlh1_field_t PRLH1_f; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint8_t PRLL2; + stc_mft_ppg_prll2_field_t PRLL2_f; + }; + union { + __IO uint8_t PRLH2; + stc_mft_ppg_prlh2_field_t PRLH2_f; + }; + __IO uint8_t RESERVED24[2]; + union { + __IO uint8_t PRLL3; + stc_mft_ppg_prll3_field_t PRLL3_f; + }; + union { + __IO uint8_t PRLH3; + stc_mft_ppg_prlh3_field_t PRLH3_f; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint8_t GATEC0; + stc_mft_ppg_gatec0_field_t GATEC0_f; + }; + __IO uint8_t RESERVED26[39]; + union { + __IO uint8_t PPGC5; + stc_mft_ppg_ppgc5_field_t PPGC5_f; + }; + union { + __IO uint8_t PPGC4; + stc_mft_ppg_ppgc4_field_t PPGC4_f; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint8_t PPGC7; + stc_mft_ppg_ppgc7_field_t PPGC7_f; + }; + union { + __IO uint8_t PPGC6; + stc_mft_ppg_ppgc6_field_t PPGC6_f; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint8_t PRLL4; + stc_mft_ppg_prll4_field_t PRLL4_f; + }; + union { + __IO uint8_t PRLH4; + stc_mft_ppg_prlh4_field_t PRLH4_f; + }; + __IO uint8_t RESERVED29[2]; + union { + __IO uint8_t PRLL5; + stc_mft_ppg_prll5_field_t PRLL5_f; + }; + union { + __IO uint8_t PRLH5; + stc_mft_ppg_prlh5_field_t PRLH5_f; + }; + __IO uint8_t RESERVED30[2]; + union { + __IO uint8_t PRLL6; + stc_mft_ppg_prll6_field_t PRLL6_f; + }; + union { + __IO uint8_t PRLH6; + stc_mft_ppg_prlh6_field_t PRLH6_f; + }; + __IO uint8_t RESERVED31[2]; + union { + __IO uint8_t PRLL7; + stc_mft_ppg_prll7_field_t PRLL7_f; + }; + union { + __IO uint8_t PRLH7; + stc_mft_ppg_prlh7_field_t PRLH7_f; + }; + __IO uint8_t RESERVED32[2]; + union { + __IO uint8_t GATEC4; + stc_mft_ppg_gatec4_field_t GATEC4_f; + }; + __IO uint8_t RESERVED33[39]; + union { + __IO uint8_t PPGC9; + stc_mft_ppg_ppgc9_field_t PPGC9_f; + }; + union { + __IO uint8_t PPGC8; + stc_mft_ppg_ppgc8_field_t PPGC8_f; + }; + __IO uint8_t RESERVED34[2]; + union { + __IO uint8_t PPGC11; + stc_mft_ppg_ppgc11_field_t PPGC11_f; + }; + union { + __IO uint8_t PPGC10; + stc_mft_ppg_ppgc10_field_t PPGC10_f; + }; + __IO uint8_t RESERVED35[2]; + union { + __IO uint8_t PRLL8; + stc_mft_ppg_prll8_field_t PRLL8_f; + }; + union { + __IO uint8_t PRLH8; + stc_mft_ppg_prlh8_field_t PRLH8_f; + }; + __IO uint8_t RESERVED36[2]; + union { + __IO uint8_t PRLL9; + stc_mft_ppg_prll9_field_t PRLL9_f; + }; + union { + __IO uint8_t PRLH9; + stc_mft_ppg_prlh9_field_t PRLH9_f; + }; + __IO uint8_t RESERVED37[2]; + union { + __IO uint8_t PRLL10; + stc_mft_ppg_prll10_field_t PRLL10_f; + }; + union { + __IO uint8_t PRLH10; + stc_mft_ppg_prlh10_field_t PRLH10_f; + }; + __IO uint8_t RESERVED38[2]; + union { + __IO uint8_t PRLL11; + stc_mft_ppg_prll11_field_t PRLL11_f; + }; + union { + __IO uint8_t PRLH11; + stc_mft_ppg_prlh11_field_t PRLH11_f; + }; + __IO uint8_t RESERVED39[2]; + union { + __IO uint8_t GATEC8; + stc_mft_ppg_gatec8_field_t GATEC8_f; + }; + __IO uint8_t RESERVED40[39]; + union { + __IO uint8_t PPGC13; + stc_mft_ppg_ppgc13_field_t PPGC13_f; + }; + union { + __IO uint8_t PPGC12; + stc_mft_ppg_ppgc12_field_t PPGC12_f; + }; + __IO uint8_t RESERVED41[2]; + union { + __IO uint8_t PPGC15; + stc_mft_ppg_ppgc15_field_t PPGC15_f; + }; + union { + __IO uint8_t PPGC14; + stc_mft_ppg_ppgc14_field_t PPGC14_f; + }; + __IO uint8_t RESERVED42[2]; + union { + __IO uint8_t PRLL12; + stc_mft_ppg_prll12_field_t PRLL12_f; + }; + union { + __IO uint8_t PRLH12; + stc_mft_ppg_prlh12_field_t PRLH12_f; + }; + __IO uint8_t RESERVED43[2]; + union { + __IO uint8_t PRLL13; + stc_mft_ppg_prll13_field_t PRLL13_f; + }; + union { + __IO uint8_t PRLH13; + stc_mft_ppg_prlh13_field_t PRLH13_f; + }; + __IO uint8_t RESERVED44[2]; + union { + __IO uint8_t PRLL14; + stc_mft_ppg_prll14_field_t PRLL14_f; + }; + union { + __IO uint8_t PRLH14; + stc_mft_ppg_prlh14_field_t PRLH14_f; + }; + __IO uint8_t RESERVED45[2]; + union { + __IO uint8_t PRLL15; + stc_mft_ppg_prll15_field_t PRLL15_f; + }; + union { + __IO uint8_t PRLH15; + stc_mft_ppg_prlh15_field_t PRLH15_f; + }; + __IO uint8_t RESERVED46[2]; + union { + __IO uint8_t GATEC12; + stc_mft_ppg_gatec12_field_t GATEC12_f; + }; + __IO uint8_t RESERVED47[39]; + union { + __IO uint8_t PPGC17; + stc_mft_ppg_ppgc17_field_t PPGC17_f; + }; + union { + __IO uint8_t PPGC16; + stc_mft_ppg_ppgc16_field_t PPGC16_f; + }; + __IO uint8_t RESERVED48[2]; + union { + __IO uint8_t PPGC19; + stc_mft_ppg_ppgc19_field_t PPGC19_f; + }; + union { + __IO uint8_t PPGC18; + stc_mft_ppg_ppgc18_field_t PPGC18_f; + }; + __IO uint8_t RESERVED49[2]; + union { + __IO uint8_t PRLL16; + stc_mft_ppg_prll16_field_t PRLL16_f; + }; + union { + __IO uint8_t PRLH16; + stc_mft_ppg_prlh16_field_t PRLH16_f; + }; + __IO uint8_t RESERVED50[2]; + union { + __IO uint8_t PRLL17; + stc_mft_ppg_prll17_field_t PRLL17_f; + }; + union { + __IO uint8_t PRLH17; + stc_mft_ppg_prlh17_field_t PRLH17_f; + }; + __IO uint8_t RESERVED51[2]; + union { + __IO uint8_t PRLL18; + stc_mft_ppg_prll18_field_t PRLL18_f; + }; + union { + __IO uint8_t PRLH18; + stc_mft_ppg_prlh18_field_t PRLH18_f; + }; + __IO uint8_t RESERVED52[2]; + union { + __IO uint8_t PRLL19; + stc_mft_ppg_prll19_field_t PRLL19_f; + }; + union { + __IO uint8_t PRLH19; + stc_mft_ppg_prlh19_field_t PRLH19_f; + }; + __IO uint8_t RESERVED53[2]; + union { + __IO uint8_t GATEC16; + stc_mft_ppg_gatec16_field_t GATEC16_f; + }; + __IO uint8_t RESERVED54[39]; + union { + __IO uint8_t PPGC21; + stc_mft_ppg_ppgc21_field_t PPGC21_f; + }; + union { + __IO uint8_t PPGC20; + stc_mft_ppg_ppgc20_field_t PPGC20_f; + }; + __IO uint8_t RESERVED55[2]; + union { + __IO uint8_t PPGC23; + stc_mft_ppg_ppgc23_field_t PPGC23_f; + }; + union { + __IO uint8_t PPGC22; + stc_mft_ppg_ppgc22_field_t PPGC22_f; + }; + __IO uint8_t RESERVED56[2]; + union { + __IO uint8_t PRLL20; + stc_mft_ppg_prll20_field_t PRLL20_f; + }; + union { + __IO uint8_t PRLH20; + stc_mft_ppg_prlh20_field_t PRLH20_f; + }; + __IO uint8_t RESERVED57[2]; + union { + __IO uint8_t PRLL21; + stc_mft_ppg_prll21_field_t PRLL21_f; + }; + union { + __IO uint8_t PRLH21; + stc_mft_ppg_prlh21_field_t PRLH21_f; + }; + __IO uint8_t RESERVED58[2]; + union { + __IO uint8_t PRLL22; + stc_mft_ppg_prll22_field_t PRLL22_f; + }; + union { + __IO uint8_t PRLH22; + stc_mft_ppg_prlh22_field_t PRLH22_f; + }; + __IO uint8_t RESERVED59[2]; + union { + __IO uint8_t PRLL23; + stc_mft_ppg_prll23_field_t PRLL23_f; + }; + union { + __IO uint8_t PRLH23; + stc_mft_ppg_prlh23_field_t PRLH23_f; + }; + __IO uint8_t RESERVED60[2]; + union { + __IO uint8_t GATEC20; + stc_mft_ppg_gatec20_field_t GATEC20_f; + }; +} FM_MFT_PPG_TypeDef, FM4_MFT_PPG_TypeDef; + +/******************************************************************************* +* PCRC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t PCRC_POLY; + struct { + union { + __IO uint16_t PCRC_POLYL; + struct { + __IO uint8_t PCRC_POLYLL; + __IO uint8_t PCRC_POLYLH; + }; + }; + union { + __IO uint16_t PCRC_POLYH; + struct { + __IO uint8_t PCRC_POLYHL; + __IO uint8_t PCRC_POLYHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_SEED; + struct { + union { + __IO uint16_t PCRC_SEEDL; + struct { + __IO uint8_t PCRC_SEEDLL; + __IO uint8_t PCRC_SEEDLH; + }; + }; + union { + __IO uint16_t PCRC_SEEDH; + struct { + __IO uint8_t PCRC_SEEDHL; + __IO uint8_t PCRC_SEEDHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_FXOR; + struct { + union { + __IO uint16_t PCRC_FXORL; + struct { + __IO uint8_t PCRC_FXORLL; + __IO uint8_t PCRC_FXORLH; + }; + }; + union { + __IO uint16_t PCRC_FXORH; + struct { + __IO uint8_t PCRC_FXORHL; + __IO uint8_t PCRC_FXORHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_CFG; + stc_pcrc_pcrc_cfg_field_t PCRC_CFG_f; + struct { + union { + __IO uint16_t PCRC_CFGL; + struct { + __IO uint8_t PCRC_CFGLL; + __IO uint8_t PCRC_CFGLH; + }; + }; + union { + __IO uint16_t PCRC_CFGH; + struct { + __IO uint8_t PCRC_CFGHL; + __IO uint8_t PCRC_CFGHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_WR; + struct { + union { + __IO uint16_t PCRC_WRL; + struct { + __IO uint8_t PCRC_WRLL; + __IO uint8_t PCRC_WRLH; + }; + }; + union { + __IO uint16_t PCRC_WRH; + struct { + __IO uint8_t PCRC_WRHL; + __IO uint8_t PCRC_WRHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_RD; + struct { + union { + __IO uint16_t PCRC_RDL; + struct { + __IO uint8_t PCRC_RDLL; + __IO uint8_t PCRC_RDLH; + }; + }; + union { + __IO uint16_t PCRC_RDH; + struct { + __IO uint8_t PCRC_RDHL; + __IO uint8_t PCRC_RDHH; + }; + }; + }; + }; +} FM_PCRC_TypeDef, FM4_PCRC_TypeDef; + +/******************************************************************************* +* QPRC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t QPCR; + struct { + __IO uint8_t QPCRL; + __IO uint8_t QPCRH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t QRCR; + struct { + __IO uint8_t QRCRL; + __IO uint8_t QRCRH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t QPCCR; + struct { + __IO uint8_t QPCCRL; + __IO uint8_t QPCCRH; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t QPRCR; + struct { + __IO uint8_t QPRCRL; + __IO uint8_t QPRCRH; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint16_t QMPR; + struct { + __IO uint8_t QMPRL; + __IO uint8_t QMPRH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint8_t QICRL; + stc_qprc_qicrl_field_t QICRL_f; + }; + union { + __IO uint8_t QICRH; + stc_qprc_qicrh_field_t QICRH_f; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t QCR; + stc_qprc_qcr_field_t QCR_f; + struct { + __IO uint8_t QCRL; + __IO uint8_t QCRH; + }; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint16_t QECR; + stc_qprc_qecr_field_t QECR_f; + struct { + __IO uint8_t QECRL; + __IO uint8_t QECRH; + }; + }; + __IO uint8_t RESERVED7[30]; + union { + __IO uint32_t QPRCRR; + stc_qprc_qprcrr_field_t QPRCRR_f; + struct { + union { + __IO uint16_t QPRCRRL; + struct { + __IO uint8_t QPRCRRLL; + __IO uint8_t QPRCRRLH; + }; + }; + union { + __IO uint16_t QPRCRRH; + struct { + __IO uint8_t QPRCRRHL; + __IO uint8_t QPRCRRHH; + }; + }; + }; + }; +} FM_QPRC_TypeDef, FM4_QPRC_TypeDef; + +/******************************************************************************* +* QPRC_NF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t NFCTLA; + stc_qprc_nf_nfctla_field_t NFCTLA_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t NFCTLB; + stc_qprc_nf_nfctlb_field_t NFCTLB_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t NFCTLZ; + stc_qprc_nf_nfctlz_field_t NFCTLZ_f; + }; +} FM_QPRC_NF_TypeDef, FM4_QPRC_NF_TypeDef; + +/******************************************************************************* +* RTC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t WTCR10; + stc_rtc_wtcr10_field_t WTCR10_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t WTCR11; + stc_rtc_wtcr11_field_t WTCR11_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t WTCR12; + stc_rtc_wtcr12_field_t WTCR12_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint8_t WTCR13; + stc_rtc_wtcr13_field_t WTCR13_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint8_t WTCR20; + stc_rtc_wtcr20_field_t WTCR20_f; + }; + __IO uint8_t RESERVED4[3]; + union { + __IO uint8_t WTCR21; + stc_rtc_wtcr21_field_t WTCR21_f; + }; + __IO uint8_t RESERVED5[7]; + union { + __IO uint8_t WTSR; + stc_rtc_wtsr_field_t WTSR_f; + }; + __IO uint8_t RESERVED6[3]; + union { + __IO uint8_t WTMIR; + stc_rtc_wtmir_field_t WTMIR_f; + }; + __IO uint8_t RESERVED7[3]; + union { + __IO uint8_t WTHR; + stc_rtc_wthr_field_t WTHR_f; + }; + __IO uint8_t RESERVED8[3]; + union { + __IO uint8_t WTDR; + stc_rtc_wtdr_field_t WTDR_f; + }; + __IO uint8_t RESERVED9[3]; + union { + __IO uint8_t WTDW; + stc_rtc_wtdw_field_t WTDW_f; + }; + __IO uint8_t RESERVED10[3]; + union { + __IO uint8_t WTMOR; + stc_rtc_wtmor_field_t WTMOR_f; + }; + __IO uint8_t RESERVED11[3]; + union { + __IO uint8_t WTYR; + stc_rtc_wtyr_field_t WTYR_f; + }; + __IO uint8_t RESERVED12[3]; + union { + __IO uint8_t ALMIR; + stc_rtc_almir_field_t ALMIR_f; + }; + __IO uint8_t RESERVED13[3]; + union { + __IO uint8_t ALHR; + stc_rtc_alhr_field_t ALHR_f; + }; + __IO uint8_t RESERVED14[3]; + union { + __IO uint8_t ALDR; + stc_rtc_aldr_field_t ALDR_f; + }; + __IO uint8_t RESERVED15[3]; + union { + __IO uint8_t ALMOR; + stc_rtc_almor_field_t ALMOR_f; + }; + __IO uint8_t RESERVED16[3]; + union { + __IO uint8_t ALYR; + stc_rtc_alyr_field_t ALYR_f; + }; + __IO uint8_t RESERVED17[3]; + union { + __IO uint8_t WTTR0; + stc_rtc_wttr0_field_t WTTR0_f; + }; + __IO uint8_t RESERVED18[3]; + union { + __IO uint8_t WTTR1; + stc_rtc_wttr1_field_t WTTR1_f; + }; + __IO uint8_t RESERVED19[3]; + union { + __IO uint8_t WTTR2; + stc_rtc_wttr2_field_t WTTR2_f; + }; + __IO uint8_t RESERVED20[3]; + union { + __IO uint8_t WTCAL0; + stc_rtc_wtcal0_field_t WTCAL0_f; + }; + __IO uint8_t RESERVED21[3]; + union { + __IO uint8_t WTCAL1; + stc_rtc_wtcal1_field_t WTCAL1_f; + }; + __IO uint8_t RESERVED22[3]; + union { + __IO uint8_t WTCALEN; + stc_rtc_wtcalen_field_t WTCALEN_f; + }; + __IO uint8_t RESERVED23[3]; + union { + __IO uint8_t WTDIV; + stc_rtc_wtdiv_field_t WTDIV_f; + }; + __IO uint8_t RESERVED24[3]; + union { + __IO uint8_t WTDIVEN; + stc_rtc_wtdiven_field_t WTDIVEN_f; + }; + __IO uint8_t RESERVED25[3]; + union { + __IO uint8_t WTCALPRD; + stc_rtc_wtcalprd_field_t WTCALPRD_f; + }; + __IO uint8_t RESERVED26[3]; + union { + __IO uint8_t WTCOSEL; + stc_rtc_wtcosel_field_t WTCOSEL_f; + }; + __IO uint8_t RESERVED27[3]; + union { + __IO uint8_t VB_CLKDIV; + stc_rtc_vb_clkdiv_field_t VB_CLKDIV_f; + }; + __IO uint8_t RESERVED28[3]; + union { + __IO uint8_t WTOSCCNT; + stc_rtc_wtosccnt_field_t WTOSCCNT_f; + }; + __IO uint8_t RESERVED29[3]; + union { + __IO uint8_t CCS; + stc_rtc_ccs_field_t CCS_f; + }; + __IO uint8_t RESERVED30[3]; + union { + __IO uint8_t CCB; + stc_rtc_ccb_field_t CCB_f; + }; + __IO uint8_t RESERVED31[7]; + union { + __IO uint8_t BOOST; + stc_rtc_boost_field_t BOOST_f; + }; + __IO uint8_t RESERVED32[3]; + union { + __IO uint8_t EWKUP; + stc_rtc_ewkup_field_t EWKUP_f; + }; + __IO uint8_t RESERVED33[3]; + union { + __IO uint8_t VDET; + stc_rtc_vdet_field_t VDET_f; + }; + __IO uint8_t RESERVED34[7]; + union { + __IO uint8_t HIBRST; + stc_rtc_hibrst_field_t HIBRST_f; + }; + __IO uint8_t RESERVED35[3]; + union { + __IO uint8_t VBPFR; + stc_rtc_vbpfr_field_t VBPFR_f; + }; + __IO uint8_t RESERVED36[3]; + union { + __IO uint8_t VBPCR; + stc_rtc_vbpcr_field_t VBPCR_f; + }; + __IO uint8_t RESERVED37[3]; + union { + __IO uint8_t VBDDR; + stc_rtc_vbddr_field_t VBDDR_f; + }; + __IO uint8_t RESERVED38[3]; + union { + __IO uint8_t VBDIR; + stc_rtc_vbdir_field_t VBDIR_f; + }; + __IO uint8_t RESERVED39[3]; + union { + __IO uint8_t VBDOR; + stc_rtc_vbdor_field_t VBDOR_f; + }; + __IO uint8_t RESERVED40[3]; + union { + __IO uint8_t VBPZR; + stc_rtc_vbpzr_field_t VBPZR_f; + }; + __IO uint8_t RESERVED41[79]; + __IO uint8_t BREG00; + __IO uint8_t BREG01; + __IO uint8_t BREG02; + __IO uint8_t BREG03; + __IO uint8_t BREG04; + __IO uint8_t BREG05; + __IO uint8_t BREG06; + __IO uint8_t BREG07; + __IO uint8_t BREG08; + __IO uint8_t BREG09; + __IO uint8_t BREG0A; + __IO uint8_t BREG0B; + __IO uint8_t BREG0C; + __IO uint8_t BREG0D; + __IO uint8_t BREG0E; + __IO uint8_t BREG0F; + __IO uint8_t BREG10; + __IO uint8_t BREG11; + __IO uint8_t BREG12; + __IO uint8_t BREG13; + __IO uint8_t BREG14; + __IO uint8_t BREG15; + __IO uint8_t BREG16; + __IO uint8_t BREG17; + __IO uint8_t BREG18; + __IO uint8_t BREG19; + __IO uint8_t BREG1A; + __IO uint8_t BREG1B; + __IO uint8_t BREG1C; + __IO uint8_t BREG1D; + __IO uint8_t BREG1E; + __IO uint8_t BREG1F; + __IO uint8_t BREG20; + __IO uint8_t BREG21; + __IO uint8_t BREG22; + __IO uint8_t BREG23; + __IO uint8_t BREG24; + __IO uint8_t BREG25; + __IO uint8_t BREG26; + __IO uint8_t BREG27; + __IO uint8_t BREG28; + __IO uint8_t BREG29; + __IO uint8_t BREG2A; + __IO uint8_t BREG2B; + __IO uint8_t BREG2C; + __IO uint8_t BREG2D; + __IO uint8_t BREG2E; + __IO uint8_t BREG2F; + __IO uint8_t BREG30; + __IO uint8_t BREG31; + __IO uint8_t BREG32; + __IO uint8_t BREG33; + __IO uint8_t BREG34; + __IO uint8_t BREG35; + __IO uint8_t BREG36; + __IO uint8_t BREG37; + __IO uint8_t BREG38; + __IO uint8_t BREG39; + __IO uint8_t BREG3A; + __IO uint8_t BREG3B; + __IO uint8_t BREG3C; + __IO uint8_t BREG3D; + __IO uint8_t BREG3E; + __IO uint8_t BREG3F; + __IO uint8_t BREG40; + __IO uint8_t BREG41; + __IO uint8_t BREG42; + __IO uint8_t BREG43; + __IO uint8_t BREG44; + __IO uint8_t BREG45; + __IO uint8_t BREG46; + __IO uint8_t BREG47; + __IO uint8_t BREG48; + __IO uint8_t BREG49; + __IO uint8_t BREG4A; + __IO uint8_t BREG4B; + __IO uint8_t BREG4C; + __IO uint8_t BREG4D; + __IO uint8_t BREG4E; + __IO uint8_t BREG4F; + __IO uint8_t BREG50; + __IO uint8_t BREG51; + __IO uint8_t BREG52; + __IO uint8_t BREG53; + __IO uint8_t BREG54; + __IO uint8_t BREG55; + __IO uint8_t BREG56; + __IO uint8_t BREG57; + __IO uint8_t BREG58; + __IO uint8_t BREG59; + __IO uint8_t BREG5A; + __IO uint8_t BREG5B; + __IO uint8_t BREG5C; + __IO uint8_t BREG5D; + __IO uint8_t BREG5E; + __IO uint8_t BREG5F; + __IO uint8_t BREG60; + __IO uint8_t BREG61; + __IO uint8_t BREG62; + __IO uint8_t BREG63; + __IO uint8_t BREG64; + __IO uint8_t BREG65; + __IO uint8_t BREG66; + __IO uint8_t BREG67; + __IO uint8_t BREG68; + __IO uint8_t BREG69; + __IO uint8_t BREG6A; + __IO uint8_t BREG6B; + __IO uint8_t BREG6C; + __IO uint8_t BREG6D; + __IO uint8_t BREG6E; + __IO uint8_t BREG6F; + __IO uint8_t BREG70; + __IO uint8_t BREG71; + __IO uint8_t BREG72; + __IO uint8_t BREG73; + __IO uint8_t BREG74; + __IO uint8_t BREG75; + __IO uint8_t BREG76; + __IO uint8_t BREG77; + __IO uint8_t BREG78; + __IO uint8_t BREG79; + __IO uint8_t BREG7A; + __IO uint8_t BREG7B; + __IO uint8_t BREG7C; + __IO uint8_t BREG7D; + __IO uint8_t BREG7E; + __IO uint8_t BREG7F; +} FM_RTC_TypeDef, FM4_RTC_TypeDef; + +/******************************************************************************* +* SBSSR_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[252]; + union { + __IO uint16_t BTSSSR; + stc_sbssr_btsssr_field_t BTSSSR_f; + struct { + __IO uint8_t BTSSSRL; + __IO uint8_t BTSSSRH; + }; + }; +} FM_SBSSR_TypeDef, FM4_SBSSR_TypeDef; + +/******************************************************************************* +* SDIF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t SSA2; + struct { + union { + __IO uint16_t SSA2L; + struct { + __IO uint8_t SSA2LL; + __IO uint8_t SSA2LH; + }; + }; + union { + __IO uint16_t SSA2H; + struct { + __IO uint8_t SSA2HL; + __IO uint8_t SSA2HH; + }; + }; + }; + }; + union { + __IO uint16_t SBSIZE; + stc_sdif_sbsize_field_t SBSIZE_f; + struct { + __IO uint8_t SBSIZEL; + __IO uint8_t SBSIZEH; + }; + }; + union { + __IO uint16_t SBLCNT; + struct { + __IO uint8_t SBLCNTL; + __IO uint8_t SBLCNTH; + }; + }; + union { + __IO uint32_t SSA1; + struct { + union { + __IO uint16_t SSA1L; + struct { + __IO uint8_t SSA1LL; + __IO uint8_t SSA1LH; + }; + }; + union { + __IO uint16_t SSA1H; + struct { + __IO uint8_t SSA1HL; + __IO uint8_t SSA1HH; + }; + }; + }; + }; + union { + __IO uint16_t STRSFMD; + stc_sdif_strsfmd_field_t STRSFMD_f; + struct { + __IO uint8_t STRSFMDL; + __IO uint8_t STRSFMDH; + }; + }; + union { + __IO uint16_t SCMMD; + stc_sdif_scmmd_field_t SCMMD_f; + struct { + __IO uint8_t SCMMDL; + __IO uint8_t SCMMDH; + }; + }; + union { + __IO uint16_t SRESP0; + struct { + __IO uint8_t SRESP0L; + __IO uint8_t SRESP0H; + }; + }; + union { + __IO uint16_t SRESP1; + struct { + __IO uint8_t SRESP1L; + __IO uint8_t SRESP1H; + }; + }; + union { + __IO uint16_t SRESP2; + struct { + __IO uint8_t SRESP2L; + __IO uint8_t SRESP2H; + }; + }; + union { + __IO uint16_t SRESP3; + struct { + __IO uint8_t SRESP3L; + __IO uint8_t SRESP3H; + }; + }; + union { + __IO uint16_t SRESP4; + struct { + __IO uint8_t SRESP4L; + __IO uint8_t SRESP4H; + }; + }; + union { + __IO uint16_t SRESP5; + struct { + __IO uint8_t SRESP5L; + __IO uint8_t SRESP5H; + }; + }; + union { + __IO uint16_t SRESP6; + struct { + __IO uint8_t SRESP6L; + __IO uint8_t SRESP6H; + }; + }; + union { + __IO uint16_t SRESP7; + struct { + __IO uint8_t SRESP7L; + __IO uint8_t SRESP7H; + }; + }; + union { + __IO uint32_t SBUFDP; + struct { + union { + __IO uint16_t SBUFDPL; + struct { + __IO uint8_t SBUFDPLL; + __IO uint8_t SBUFDPLH; + }; + }; + union { + __IO uint16_t SBUFDPH; + struct { + __IO uint8_t SBUFDPHL; + __IO uint8_t SBUFDPHH; + }; + }; + }; + }; + union { + __IO uint32_t SPRSTAT; + stc_sdif_sprstat_field_t SPRSTAT_f; + struct { + union { + __IO uint16_t SPRSTATL; + struct { + __IO uint8_t SPRSTATLL; + __IO uint8_t SPRSTATLH; + }; + }; + union { + __IO uint16_t SPRSTATH; + struct { + __IO uint8_t SPRSTATHL; + __IO uint8_t SPRSTATHH; + }; + }; + }; + }; + union { + __IO uint8_t SHCTL1; + stc_sdif_shctl1_field_t SHCTL1_f; + }; + union { + __IO uint8_t SPWRCTL; + stc_sdif_spwrctl_field_t SPWRCTL_f; + }; + union { + __IO uint8_t SBLKGPCTL; + stc_sdif_sblkgpctl_field_t SBLKGPCTL_f; + }; + union { + __IO uint8_t SWKUPCTL; + stc_sdif_swkupctl_field_t SWKUPCTL_f; + }; + union { + __IO uint16_t SCLKCTL; + stc_sdif_sclkctl_field_t SCLKCTL_f; + struct { + __IO uint8_t SCLKCTLL; + __IO uint8_t SCLKCTLH; + }; + }; + union { + __IO uint8_t STOCTL; + stc_sdif_stoctl_field_t STOCTL_f; + }; + union { + __IO uint8_t SSRST; + stc_sdif_ssrst_field_t SSRST_f; + }; + union { + __IO uint16_t SNINTST; + stc_sdif_snintst_field_t SNINTST_f; + struct { + __IO uint8_t SNINTSTL; + __IO uint8_t SNINTSTH; + }; + }; + union { + __IO uint16_t SEINTST; + stc_sdif_seintst_field_t SEINTST_f; + struct { + __IO uint8_t SEINTSTL; + __IO uint8_t SEINTSTH; + }; + }; + union { + __IO uint16_t SNINTSTE; + stc_sdif_snintste_field_t SNINTSTE_f; + struct { + __IO uint8_t SNINTSTEL; + __IO uint8_t SNINTSTEH; + }; + }; + union { + __IO uint16_t SEINTSTE; + stc_sdif_seintste_field_t SEINTSTE_f; + struct { + __IO uint8_t SEINTSTEL; + __IO uint8_t SEINTSTEH; + }; + }; + union { + __IO uint16_t SNINTSGE; + stc_sdif_snintsge_field_t SNINTSGE_f; + struct { + __IO uint8_t SNINTSGEL; + __IO uint8_t SNINTSGEH; + }; + }; + union { + __IO uint16_t SEINTSGE; + stc_sdif_seintsge_field_t SEINTSGE_f; + struct { + __IO uint8_t SEINTSGEL; + __IO uint8_t SEINTSGEH; + }; + }; + union { + __IO uint16_t SACMDEST; + stc_sdif_sacmdest_field_t SACMDEST_f; + struct { + __IO uint8_t SACMDESTL; + __IO uint8_t SACMDESTH; + }; + }; + union { + __IO uint16_t SHCTL2; + stc_sdif_shctl2_field_t SHCTL2_f; + struct { + __IO uint8_t SHCTL2L; + __IO uint8_t SHCTL2H; + }; + }; + union { + __IO uint16_t CAPBLTY0; + stc_sdif_capblty0_field_t CAPBLTY0_f; + struct { + __IO uint8_t CAPBLTY0L; + __IO uint8_t CAPBLTY0H; + }; + }; + union { + __IO uint16_t CAPBLTY1; + stc_sdif_capblty1_field_t CAPBLTY1_f; + struct { + __IO uint8_t CAPBLTY1L; + __IO uint8_t CAPBLTY1H; + }; + }; + union { + __IO uint16_t CAPBLTY2; + stc_sdif_capblty2_field_t CAPBLTY2_f; + struct { + __IO uint8_t CAPBLTY2L; + __IO uint8_t CAPBLTY2H; + }; + }; + union { + __IO uint16_t CAPBLTY3; + stc_sdif_capblty3_field_t CAPBLTY3_f; + struct { + __IO uint8_t CAPBLTY3L; + __IO uint8_t CAPBLTY3H; + }; + }; + union { + __IO uint16_t MXCCAPY0; + stc_sdif_mxccapy0_field_t MXCCAPY0_f; + struct { + __IO uint8_t MXCCAPY0L; + __IO uint8_t MXCCAPY0H; + }; + }; + union { + __IO uint16_t MXCCAPY1; + stc_sdif_mxccapy1_field_t MXCCAPY1_f; + struct { + __IO uint8_t MXCCAPY1L; + __IO uint8_t MXCCAPY1H; + }; + }; + union { + __IO uint16_t MXCCAPY2; + struct { + __IO uint8_t MXCCAPY2L; + __IO uint8_t MXCCAPY2H; + }; + }; + union { + __IO uint16_t MXCCAPY3; + struct { + __IO uint8_t MXCCAPY3L; + __IO uint8_t MXCCAPY3H; + }; + }; + union { + __IO uint16_t FEACEST; + stc_sdif_feacest_field_t FEACEST_f; + struct { + __IO uint8_t FEACESTL; + __IO uint8_t FEACESTH; + }; + }; + union { + __IO uint16_t SFEEIST; + stc_sdif_sfeeist_field_t SFEEIST_f; + struct { + __IO uint8_t SFEEISTL; + __IO uint8_t SFEEISTH; + }; + }; + union { + __IO uint8_t ADMAEST; + stc_sdif_admaest_field_t ADMAEST_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint16_t SADSA0; + stc_sdif_sadsa0_field_t SADSA0_f; + struct { + __IO uint8_t SADSA0L; + __IO uint8_t SADSA0H; + }; + }; + union { + __IO uint16_t SADSA1; + stc_sdif_sadsa1_field_t SADSA1_f; + struct { + __IO uint8_t SADSA1L; + __IO uint8_t SADSA1H; + }; + }; + union { + __IO uint16_t SADSA2; + stc_sdif_sadsa2_field_t SADSA2_f; + struct { + __IO uint8_t SADSA2L; + __IO uint8_t SADSA2H; + }; + }; + union { + __IO uint16_t SADSA3; + stc_sdif_sadsa3_field_t SADSA3_f; + struct { + __IO uint8_t SADSA3L; + __IO uint8_t SADSA3H; + }; + }; + union { + __IO uint16_t SPRVAL0; + stc_sdif_sprval0_field_t SPRVAL0_f; + struct { + __IO uint8_t SPRVAL0L; + __IO uint8_t SPRVAL0H; + }; + }; + union { + __IO uint16_t SPRVAL1; + stc_sdif_sprval1_field_t SPRVAL1_f; + struct { + __IO uint8_t SPRVAL1L; + __IO uint8_t SPRVAL1H; + }; + }; + union { + __IO uint16_t SPRVAL2; + stc_sdif_sprval2_field_t SPRVAL2_f; + struct { + __IO uint8_t SPRVAL2L; + __IO uint8_t SPRVAL2H; + }; + }; + union { + __IO uint16_t SPRVAL3; + stc_sdif_sprval3_field_t SPRVAL3_f; + struct { + __IO uint8_t SPRVAL3L; + __IO uint8_t SPRVAL3H; + }; + }; + union { + __IO uint16_t SPRVAL4; + stc_sdif_sprval4_field_t SPRVAL4_f; + struct { + __IO uint8_t SPRVAL4L; + __IO uint8_t SPRVAL4H; + }; + }; + union { + __IO uint16_t SPRVAL5; + stc_sdif_sprval5_field_t SPRVAL5_f; + struct { + __IO uint8_t SPRVAL5L; + __IO uint8_t SPRVAL5H; + }; + }; + union { + __IO uint16_t SPRVAL6; + stc_sdif_sprval6_field_t SPRVAL6_f; + struct { + __IO uint8_t SPRVAL6L; + __IO uint8_t SPRVAL6H; + }; + }; + union { + __IO uint16_t SPRVAL7; + stc_sdif_sprval7_field_t SPRVAL7_f; + struct { + __IO uint8_t SPRVAL7L; + __IO uint8_t SPRVAL7H; + }; + }; + __IO uint8_t RESERVED1[112]; + union { + __IO uint16_t SSHBCTLL; + stc_sdif_sshbctll_field_t SSHBCTLL_f; + struct { + __IO uint8_t SSHBCTLLL; + __IO uint8_t SSHBCTLLH; + }; + }; + union { + __IO uint16_t SSHBCTLH; + stc_sdif_sshbctlh_field_t SSHBCTLH_f; + struct { + __IO uint8_t SSHBCTLHL; + __IO uint8_t SSHBCTLHH; + }; + }; + __IO uint8_t RESERVED2[24]; + union { + __IO uint16_t SSLIST; + stc_sdif_sslist_field_t SSLIST_f; + struct { + __IO uint8_t SSLISTL; + __IO uint8_t SSLISTH; + }; + }; + union { + __IO uint16_t SHCTLV; + stc_sdif_shctlv_field_t SHCTLV_f; + struct { + __IO uint8_t SHCTLVL; + __IO uint8_t SHCTLVH; + }; + }; + union { + __IO uint16_t AHBCFGL; + stc_sdif_ahbcfgl_field_t AHBCFGL_f; + struct { + __IO uint8_t AHBCFGLL; + __IO uint8_t AHBCFGLH; + }; + }; + union { + __IO uint16_t AHBCFGH; + struct { + __IO uint8_t AHBCFGHL; + __IO uint8_t AHBCFGHH; + }; + }; + union { + __IO uint16_t SPWSWCL; + stc_sdif_spwswcl_field_t SPWSWCL_f; + struct { + __IO uint8_t SPWSWCLL; + __IO uint8_t SPWSWCLH; + }; + }; + union { + __IO uint16_t SPWSWCH; + struct { + __IO uint8_t SPWSWCHL; + __IO uint8_t SPWSWCHH; + }; + }; + union { + __IO uint16_t STUNSETL; + stc_sdif_stunsetl_field_t STUNSETL_f; + struct { + __IO uint8_t STUNSETLL; + __IO uint8_t STUNSETLH; + }; + }; + union { + __IO uint16_t STUNSETH; + stc_sdif_stunseth_field_t STUNSETH_f; + struct { + __IO uint8_t STUNSETHL; + __IO uint8_t STUNSETHH; + }; + }; + union { + __IO uint16_t STUNSTL; + stc_sdif_stunstl_field_t STUNSTL_f; + struct { + __IO uint8_t STUNSTLL; + __IO uint8_t STUNSTLH; + }; + }; + union { + __IO uint16_t STUNSTH; + stc_sdif_stunsth_field_t STUNSTH_f; + struct { + __IO uint8_t STUNSTHL; + __IO uint8_t STUNSTHH; + }; + }; + __IO uint8_t RESERVED3[8]; + union { + __IO uint16_t PSWISTL; + stc_sdif_pswistl_field_t PSWISTL_f; + struct { + __IO uint8_t PSWISTLL; + __IO uint8_t PSWISTLH; + }; + }; + union { + __IO uint16_t PSWISTH; + struct { + __IO uint8_t PSWISTHL; + __IO uint8_t PSWISTHH; + }; + }; + union { + __IO uint16_t PSWISTEL; + stc_sdif_pswistel_field_t PSWISTEL_f; + struct { + __IO uint8_t PSWISTELL; + __IO uint8_t PSWISTELH; + }; + }; + union { + __IO uint16_t PSWISTEH; + struct { + __IO uint8_t PSWISTEHL; + __IO uint8_t PSWISTEHH; + }; + }; + union { + __IO uint16_t PSWISGEL; + stc_sdif_pswisgel_field_t PSWISGEL_f; + struct { + __IO uint8_t PSWISGELL; + __IO uint8_t PSWISGELH; + }; + }; + union { + __IO uint16_t PSWISGEH; + struct { + __IO uint8_t PSWISGEHL; + __IO uint8_t PSWISGEHH; + }; + }; + union { + __IO uint16_t MMCSDCL; + stc_sdif_mmcsdcl_field_t MMCSDCL_f; + struct { + __IO uint8_t MMCSDCLL; + __IO uint8_t MMCSDCLH; + }; + }; + union { + __IO uint16_t MMCSDCH; + stc_sdif_mmcsdch_field_t MMCSDCH_f; + struct { + __IO uint8_t MMCSDCHL; + __IO uint8_t MMCSDCHH; + }; + }; + union { + __IO uint16_t MCWIRQC0; + stc_sdif_mcwirqc0_field_t MCWIRQC0_f; + struct { + __IO uint8_t MCWIRQC0L; + __IO uint8_t MCWIRQC0H; + }; + }; + union { + __IO uint16_t MCWIRQC1; + stc_sdif_mcwirqc1_field_t MCWIRQC1_f; + struct { + __IO uint8_t MCWIRQC1L; + __IO uint8_t MCWIRQC1H; + }; + }; + union { + __IO uint16_t MCWIRQC2; + stc_sdif_mcwirqc2_field_t MCWIRQC2_f; + struct { + __IO uint8_t MCWIRQC2L; + __IO uint8_t MCWIRQC2H; + }; + }; + union { + __IO uint16_t MCWIRQC3; + stc_sdif_mcwirqc3_field_t MCWIRQC3_f; + struct { + __IO uint8_t MCWIRQC3L; + __IO uint8_t MCWIRQC3H; + }; + }; + union { + __IO uint16_t MCRPCKBL; + stc_sdif_mcrpckbl_field_t MCRPCKBL_f; + struct { + __IO uint8_t MCRPCKBLL; + __IO uint8_t MCRPCKBLH; + }; + }; + union { + __IO uint16_t MCRPCKBH; + struct { + __IO uint8_t MCRPCKBHL; + __IO uint8_t MCRPCKBHH; + }; + }; + __IO uint8_t RESERVED4[32]; + union { + __IO uint16_t SCDETECS; + stc_sdif_scdetecs_field_t SCDETECS_f; + struct { + __IO uint8_t SCDETECSL; + __IO uint8_t SCDETECSH; + }; + }; +} FM_SDIF_TypeDef, FM4_SDIF_TypeDef; + +/******************************************************************************* +* SWWDT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t WDOGLOAD; + struct { + union { + __IO uint16_t WDOGLOADL; + struct { + __IO uint8_t WDOGLOADLL; + __IO uint8_t WDOGLOADLH; + }; + }; + union { + __IO uint16_t WDOGLOADH; + struct { + __IO uint8_t WDOGLOADHL; + __IO uint8_t WDOGLOADHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGVALUE; + struct { + union { + __IO uint16_t WDOGVALUEL; + struct { + __IO uint8_t WDOGVALUELL; + __IO uint8_t WDOGVALUELH; + }; + }; + union { + __IO uint16_t WDOGVALUEH; + struct { + __IO uint8_t WDOGVALUEHL; + __IO uint8_t WDOGVALUEHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGCONTROL; + stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; + struct { + union { + __IO uint16_t WDOGCONTROLL; + struct { + __IO uint8_t WDOGCONTROLLL; + __IO uint8_t WDOGCONTROLLH; + }; + }; + union { + __IO uint16_t WDOGCONTROLH; + struct { + __IO uint8_t WDOGCONTROLHL; + __IO uint8_t WDOGCONTROLHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGINTCLR; + struct { + union { + __IO uint16_t WDOGINTCLRL; + struct { + __IO uint8_t WDOGINTCLRLL; + __IO uint8_t WDOGINTCLRLH; + }; + }; + union { + __IO uint16_t WDOGINTCLRH; + struct { + __IO uint8_t WDOGINTCLRHL; + __IO uint8_t WDOGINTCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGRIS; + stc_swwdt_wdogris_field_t WDOGRIS_f; + struct { + union { + __IO uint16_t WDOGRISL; + struct { + __IO uint8_t WDOGRISLL; + __IO uint8_t WDOGRISLH; + }; + }; + union { + __IO uint16_t WDOGRISH; + struct { + __IO uint8_t WDOGRISHL; + __IO uint8_t WDOGRISHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t WDOGSPMC; + stc_swwdt_wdogspmc_field_t WDOGSPMC_f; + struct { + union { + __IO uint16_t WDOGSPMCL; + struct { + __IO uint8_t WDOGSPMCLL; + __IO uint8_t WDOGSPMCLH; + }; + }; + union { + __IO uint16_t WDOGSPMCH; + struct { + __IO uint8_t WDOGSPMCHL; + __IO uint8_t WDOGSPMCHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[3044]; + union { + __IO uint32_t WDOGLOCK; + struct { + union { + __IO uint16_t WDOGLOCKL; + struct { + __IO uint8_t WDOGLOCKLL; + __IO uint8_t WDOGLOCKLH; + }; + }; + union { + __IO uint16_t WDOGLOCKH; + struct { + __IO uint8_t WDOGLOCKHL; + __IO uint8_t WDOGLOCKHH; + }; + }; + }; + }; +} FM_SWWDT_TypeDef, FM4_SWWDT_TypeDef; + +/******************************************************************************* +* UNIQUE_ID_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t UIDR0; + stc_unique_id_uidr0_field_t UIDR0_f; + struct { + union { + __IO uint16_t UIDR0L; + struct { + __IO uint8_t UIDR0LL; + __IO uint8_t UIDR0LH; + }; + }; + union { + __IO uint16_t UIDR0H; + struct { + __IO uint8_t UIDR0HL; + __IO uint8_t UIDR0HH; + }; + }; + }; + }; + union { + __IO uint32_t UIDR1; + stc_unique_id_uidr1_field_t UIDR1_f; + struct { + union { + __IO uint16_t UIDR1L; + struct { + __IO uint8_t UIDR1LL; + __IO uint8_t UIDR1LH; + }; + }; + union { + __IO uint16_t UIDR1H; + struct { + __IO uint8_t UIDR1HL; + __IO uint8_t UIDR1HH; + }; + }; + }; + }; +} FM_UNIQUE_ID_TypeDef, FM4_UNIQUE_ID_TypeDef; + +/******************************************************************************* +* USB_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[8448]; + union { + __IO uint16_t HCNT; + stc_usb_hcnt_field_t HCNT_f; + struct { + __IO uint8_t HCNTL; + __IO uint8_t HCNTH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint8_t HIRQ; + stc_usb_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usb_herr_field_t HERR_f; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint8_t HSTATE; + stc_usb_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usb_hfcomp_field_t HFCOMP_f; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint16_t HRTIMER; + stc_usb_hrtimer_field_t HRTIMER_f; + struct { + __IO uint8_t HRTIMERL; + __IO uint8_t HRTIMERH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint8_t HRTIMER2; + stc_usb_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usb_hadr_field_t HADR_f; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t HEOF; + stc_usb_heof_field_t HEOF_f; + struct { + __IO uint8_t HEOFL; + __IO uint8_t HEOFH; + }; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint16_t HFRAME; + stc_usb_hframe_field_t HFRAME_f; + struct { + __IO uint8_t HFRAMEL; + __IO uint8_t HFRAMEH; + }; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint8_t HTOKEN; + stc_usb_htoken_field_t HTOKEN_f; + }; + __IO uint8_t RESERVED8[3]; + union { + __IO uint16_t UDCC; + stc_usb_udcc_field_t UDCC_f; + struct { + __IO uint8_t UDCCL; + __IO uint8_t UDCCH; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint16_t EP0C; + stc_usb_ep0c_field_t EP0C_f; + struct { + __IO uint8_t EP0CL; + __IO uint8_t EP0CH; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint16_t EP1C; + stc_usb_ep1c_field_t EP1C_f; + struct { + __IO uint8_t EP1CL; + __IO uint8_t EP1CH; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t EP2C; + stc_usb_ep2c_field_t EP2C_f; + struct { + __IO uint8_t EP2CL; + __IO uint8_t EP2CH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint16_t EP3C; + stc_usb_ep3c_field_t EP3C_f; + struct { + __IO uint8_t EP3CL; + __IO uint8_t EP3CH; + }; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint16_t EP4C; + stc_usb_ep4c_field_t EP4C_f; + struct { + __IO uint8_t EP4CL; + __IO uint8_t EP4CH; + }; + }; + __IO uint8_t RESERVED14[2]; + union { + __IO uint16_t EP5C; + stc_usb_ep5c_field_t EP5C_f; + struct { + __IO uint8_t EP5CL; + __IO uint8_t EP5CH; + }; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint16_t TMSP; + stc_usb_tmsp_field_t TMSP_f; + struct { + __IO uint8_t TMSPL; + __IO uint8_t TMSPH; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint8_t UDCS; + stc_usb_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usb_udcie_field_t UDCIE_f; + }; + __IO uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0IS; + stc_usb_ep0is_field_t EP0IS_f; + struct { + __IO uint8_t EP0ISL; + __IO uint8_t EP0ISH; + }; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint16_t EP0OS; + stc_usb_ep0os_field_t EP0OS_f; + struct { + __IO uint8_t EP0OSL; + __IO uint8_t EP0OSH; + }; + }; + __IO uint8_t RESERVED19[2]; + union { + __IO uint16_t EP1S; + stc_usb_ep1s_field_t EP1S_f; + struct { + __IO uint8_t EP1SL; + __IO uint8_t EP1SH; + }; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint16_t EP2S; + stc_usb_ep2s_field_t EP2S_f; + struct { + __IO uint8_t EP2SL; + __IO uint8_t EP2SH; + }; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint16_t EP3S; + stc_usb_ep3s_field_t EP3S_f; + struct { + __IO uint8_t EP3SL; + __IO uint8_t EP3SH; + }; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint16_t EP4S; + stc_usb_ep4s_field_t EP4S_f; + struct { + __IO uint8_t EP4SL; + __IO uint8_t EP4SH; + }; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint16_t EP5S; + stc_usb_ep5s_field_t EP5S_f; + struct { + __IO uint8_t EP5SL; + __IO uint8_t EP5SH; + }; + }; + __IO uint8_t RESERVED24[2]; + union { + __IO uint16_t EP0DT; + stc_usb_ep0dt_field_t EP0DT_f; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint16_t EP1DT; + stc_usb_ep1dt_field_t EP1DT_f; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + __IO uint8_t RESERVED26[2]; + union { + __IO uint16_t EP2DT; + stc_usb_ep2dt_field_t EP2DT_f; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint16_t EP3DT; + stc_usb_ep3dt_field_t EP3DT_f; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint16_t EP4DT; + stc_usb_ep4dt_field_t EP4DT_f; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + __IO uint8_t RESERVED29[2]; + union { + __IO uint16_t EP5DT; + stc_usb_ep5dt_field_t EP5DT_f; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +} FM_USB_TypeDef, FM4_USB_TypeDef; + +/******************************************************************************* +* USBCLK_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbclk_uccr_field_t UCCR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclk_upcr1_field_t UPCR1_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclk_upcr2_field_t UPCR2_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclk_upcr3_field_t UPCR3_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclk_upcr4_field_t UPCR4_f; + }; + __IO uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclk_up_str_field_t UP_STR_f; + }; + __IO uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclk_upint_enr_field_t UPINT_ENR_f; + }; + __IO uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclk_upint_clr_field_t UPINT_CLR_f; + }; + __IO uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclk_upint_str_field_t UPINT_STR_f; + }; + __IO uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbclk_upcr5_field_t UPCR5_f; + }; + __IO uint8_t RESERVED9[11]; + union { + __IO uint8_t USBEN0; + stc_usbclk_usben0_field_t USBEN0_f; + }; + __IO uint8_t RESERVED10[3]; + union { + __IO uint8_t USBEN1; + stc_usbclk_usben1_field_t USBEN1_f; + }; +} FM_USBCLK_TypeDef, FM4_USBCLK_TypeDef; + +/******************************************************************************* +* WC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t WCRD; + stc_wc_wcrd_field_t WCRD_f; + }; + union { + __IO uint8_t WCRL; + stc_wc_wcrl_field_t WCRL_f; + }; + union { + __IO uint8_t WCCR; + stc_wc_wccr_field_t WCCR_f; + }; + __IO uint8_t RESERVED0[13]; + union { + __IO uint16_t CLK_SEL; + stc_wc_clk_sel_field_t CLK_SEL_f; + struct { + __IO uint8_t CLK_SELL; + __IO uint8_t CLK_SELH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint8_t CLK_EN; + stc_wc_clk_en_field_t CLK_EN_f; + }; +} FM_WC_TypeDef, FM4_WC_TypeDef; + +/******************************************************************************* +* Peripheral Memory Map +*******************************************************************************/ +#define FM_FLASH_BASE (0x00000000UL) /* Flash Base Address */ +#define FM4_FLASH_BASE (0x00000000UL) /* Flash Base Address */ +#define FM_PERIPH_BASE (0x40000000UL) /* Peripheral Base Address */ +#define FM4_PERIPH_BASE (0x40000000UL) /* Peripheral Base Address */ +#define FM_CM4_BASE (0xE0100000UL) /* CM4 Private */ +#define FM4_CM4_BASE (0xE0100000UL) /* CM4 Private */ + +#define FM_ADC0_BASE (0x40027000UL) /* ADC0 Base Address */ +#define FM4_ADC0_BASE (0x40027000UL) /* ADC0 Base Address */ +#define FM_ADC1_BASE (0x40027100UL) /* ADC1 Base Address */ +#define FM4_ADC1_BASE (0x40027100UL) /* ADC1 Base Address */ +#define FM_ADC2_BASE (0x40027200UL) /* ADC2 Base Address */ +#define FM4_ADC2_BASE (0x40027200UL) /* ADC2 Base Address */ +#define FM_BT0_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_PPG_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_PPG_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_PWC_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_PWC_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_PWM_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_PWM_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_RT_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_RT_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT1_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_PPG_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_PPG_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_PWC_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_PWC_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_PWM_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_PWM_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_RT_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_RT_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT10_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_PPG_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_PPG_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_PWC_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_PWC_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_PWM_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_PWM_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_RT_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_RT_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT11_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_PPG_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_PPG_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_PWC_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_PWC_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_PWM_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_PWM_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_RT_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_RT_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT12_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_PPG_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_PPG_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_PWC_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_PWC_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_PWM_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_PWM_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_RT_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_RT_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT13_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_PPG_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_PPG_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_PWC_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_PWC_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_PWM_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_PWM_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_RT_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_RT_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT14_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_PPG_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_PPG_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_PWC_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_PWC_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_PWM_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_PWM_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_RT_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_RT_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT15_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_PPG_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_PPG_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_PWC_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_PWC_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_PWM_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_PWM_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_RT_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_RT_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT2_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_PPG_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_PPG_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_PWC_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_PWC_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_PWM_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_PWM_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_RT_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_RT_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT3_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_PPG_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_PPG_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_PWC_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_PWC_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_PWM_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_PWM_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_RT_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_RT_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT4_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_PPG_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_PPG_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_PWC_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_PWC_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_PWM_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_PWM_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_RT_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_RT_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT5_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_PPG_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_PPG_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_PWC_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_PWC_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_PWM_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_PWM_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_RT_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_RT_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT6_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_PPG_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_PPG_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_PWC_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_PWC_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_PWM_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_PWM_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_RT_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_RT_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT7_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_PPG_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_PPG_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_PWC_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_PWC_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_PWM_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_PWM_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_RT_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_RT_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT8_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_PPG_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_PPG_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_PWC_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_PWC_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_PWM_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_PWM_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_RT_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_RT_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT9_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_PPG_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_PPG_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_PWC_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_PWC_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_PWM_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_PWM_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_RT_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_RT_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BTIOSEL03_BASE (0x40025100UL) /* BTIOSEL03 Base Address */ +#define FM4_BTIOSEL03_BASE (0x40025100UL) /* BTIOSEL03 Base Address */ +#define FM_BTIOSEL47_BASE (0x40025300UL) /* BTIOSEL47 Base Address */ +#define FM4_BTIOSEL47_BASE (0x40025300UL) /* BTIOSEL47 Base Address */ +#define FM_BTIOSEL8B_BASE (0x40025500UL) /* BTIOSEL8B Base Address */ +#define FM4_BTIOSEL8B_BASE (0x40025500UL) /* BTIOSEL8B Base Address */ +#define FM_BTIOSELCF_BASE (0x40025700UL) /* BTIOSELCF Base Address */ +#define FM4_BTIOSELCF_BASE (0x40025700UL) /* BTIOSELCF Base Address */ +#define FM_CAN0_BASE (0x40062000UL) /* CAN0 Base Address */ +#define FM4_CAN0_BASE (0x40062000UL) /* CAN0 Base Address */ +#define FM_CAN1_BASE (0x40063000UL) /* CAN1 Base Address */ +#define FM4_CAN1_BASE (0x40063000UL) /* CAN1 Base Address */ +#define FM_CANFD0_BASE (0x40070000UL) /* CANFD0 Base Address */ +#define FM4_CANFD0_BASE (0x40070000UL) /* CANFD0 Base Address */ +#define FM_CANPRES_BASE (0x40037000UL) /* CANPRES Base Address */ +#define FM4_CANPRES_BASE (0x40037000UL) /* CANPRES Base Address */ +#define FM_CLK_GATING_BASE (0x4003C100UL) /* CLK_GATING Base Address */ +#define FM4_CLK_GATING_BASE (0x4003C100UL) /* CLK_GATING Base Address */ +#define FM_CRC_BASE (0x40039000UL) /* CRC Base Address */ +#define FM4_CRC_BASE (0x40039000UL) /* CRC Base Address */ +#define FM_CRG_BASE (0x40010000UL) /* CRG Base Address */ +#define FM4_CRG_BASE (0x40010000UL) /* CRG Base Address */ +#define FM_CRTRIM_BASE (0x4002E000UL) /* CRTRIM Base Address */ +#define FM4_CRTRIM_BASE (0x4002E000UL) /* CRTRIM Base Address */ +#define FM_DAC0_BASE (0x40033000UL) /* DAC0 Base Address */ +#define FM4_DAC0_BASE (0x40033000UL) /* DAC0 Base Address */ +#define FM_DAC1_BASE (0x40033008UL) /* DAC1 Base Address */ +#define FM4_DAC1_BASE (0x40033008UL) /* DAC1 Base Address */ +#define FM_DMAC_BASE (0x40060000UL) /* DMAC Base Address */ +#define FM4_DMAC_BASE (0x40060000UL) /* DMAC Base Address */ +#define FM_DS_BASE (0x40035100UL) /* DS Base Address */ +#define FM4_DS_BASE (0x40035100UL) /* DS Base Address */ +#define FM_DSTC_BASE (0x40061000UL) /* DSTC Base Address */ +#define FM4_DSTC_BASE (0x40061000UL) /* DSTC Base Address */ +#define FM_DT_BASE (0x40015000UL) /* DT Base Address */ +#define FM4_DT_BASE (0x40015000UL) /* DT Base Address */ +#define FM_DUALFLASH_IF_BASE (0x40000400UL) /* DUALFLASH_IF Base Address */ +#define FM4_DUALFLASH_IF_BASE (0x40000400UL) /* DUALFLASH_IF Base Address */ +#define FM_ECC_CAPTURE_BASE (0x40000300UL) /* ECC_CAPTURE Base Address */ +#define FM4_ECC_CAPTURE_BASE (0x40000300UL) /* ECC_CAPTURE Base Address */ +#define FM_EXBUS_BASE (0x4003F000UL) /* EXBUS Base Address */ +#define FM4_EXBUS_BASE (0x4003F000UL) /* EXBUS Base Address */ +#define FM_EXTI_BASE (0x40030000UL) /* EXTI Base Address */ +#define FM4_EXTI_BASE (0x40030000UL) /* EXTI Base Address */ +#define FM_FLASH_IF_BASE (0x40000000UL) /* FLASH_IF Base Address */ +#define FM4_FLASH_IF_BASE (0x40000000UL) /* FLASH_IF Base Address */ +#define FM_GPIO_BASE (0x4006F000UL) /* GPIO Base Address */ +#define FM4_GPIO_BASE (0x4006F000UL) /* GPIO Base Address */ +#define FM_HSSPI_BASE (0xD0000000UL) /* HSSPI Base Address */ +#define FM4_HSSPI_BASE (0xD0000000UL) /* HSSPI Base Address */ +#define FM_HWWDT_BASE (0x40011000UL) /* HWWDT Base Address */ +#define FM4_HWWDT_BASE (0x40011000UL) /* HWWDT Base Address */ +#define FM_I2S0_BASE (0x4006C000UL) /* I2S0 Base Address */ +#define FM4_I2S0_BASE (0x4006C000UL) /* I2S0 Base Address */ +#define FM_I2SPRE_BASE (0x4003D000UL) /* I2SPRE Base Address */ +#define FM4_I2SPRE_BASE (0x4003D000UL) /* I2SPRE Base Address */ +#define FM_INTREQ_BASE (0x40031000UL) /* INTREQ Base Address */ +#define FM4_INTREQ_BASE (0x40031000UL) /* INTREQ Base Address */ +#define FM_LSCRP_BASE (0x4003C000UL) /* LSCRP Base Address */ +#define FM4_LSCRP_BASE (0x4003C000UL) /* LSCRP Base Address */ +#define FM_LVD_BASE (0x40035000UL) /* LVD Base Address */ +#define FM4_LVD_BASE (0x40035000UL) /* LVD Base Address */ +#define FM_MFS0_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_CSIO_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_CSIO_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_I2C_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_I2C_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_LIN_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_LIN_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_UART_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_UART_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS1_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_CSIO_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_CSIO_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_I2C_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_I2C_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_LIN_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_LIN_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_UART_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_UART_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS10_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_CSIO_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_CSIO_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_I2C_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_I2C_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_LIN_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_LIN_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_UART_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_UART_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS11_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_CSIO_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_CSIO_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_I2C_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_I2C_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_LIN_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_LIN_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_UART_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_UART_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS12_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_CSIO_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_CSIO_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_I2C_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_I2C_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_LIN_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_LIN_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_UART_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_UART_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS13_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_CSIO_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_CSIO_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_I2C_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_I2C_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_LIN_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_LIN_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_UART_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_UART_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS14_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_CSIO_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_CSIO_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_I2C_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_I2C_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_LIN_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_LIN_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_UART_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_UART_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS15_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_CSIO_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_CSIO_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_I2C_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_I2C_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_LIN_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_LIN_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_UART_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_UART_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS2_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_CSIO_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_CSIO_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_I2C_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_I2C_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_LIN_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_LIN_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_UART_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_UART_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS3_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_CSIO_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_CSIO_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_I2C_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_I2C_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_LIN_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_LIN_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_UART_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_UART_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS4_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_CSIO_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_CSIO_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_I2C_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_I2C_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_LIN_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_LIN_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_UART_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_UART_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS5_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_CSIO_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_CSIO_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_I2C_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_I2C_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_LIN_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_LIN_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_UART_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_UART_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS6_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_CSIO_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_CSIO_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_I2C_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_I2C_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_LIN_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_LIN_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_UART_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_UART_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS7_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_CSIO_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_CSIO_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_I2C_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_I2C_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_LIN_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_LIN_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_UART_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_UART_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS8_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_CSIO_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_CSIO_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_I2C_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_I2C_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_LIN_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_LIN_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_UART_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_UART_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS9_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_CSIO_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_CSIO_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_I2C_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_I2C_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_LIN_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_LIN_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_UART_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_UART_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFT_PPG_BASE (0x40024000UL) /* MFT_PPG Base Address */ +#define FM4_MFT_PPG_BASE (0x40024000UL) /* MFT_PPG Base Address */ +#define FM_MFT0_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_ADCMP_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_ADCMP_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_FRT_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_FRT_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_ICU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_ICU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_OCU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_OCU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_WFG_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_WFG_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT1_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_ADCMP_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_ADCMP_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_FRT_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_FRT_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_ICU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_ICU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_OCU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_OCU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_WFG_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_WFG_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT2_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_ADCMP_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_ADCMP_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_FRT_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_FRT_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_ICU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_ICU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_OCU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_OCU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_WFG_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_WFG_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_PCRC_BASE (0x40080000UL) /* PCRC Base Address */ +#define FM4_PCRC_BASE (0x40080000UL) /* PCRC Base Address */ +#define FM_QPRC0_BASE (0x40026000UL) /* QPRC0 Base Address */ +#define FM4_QPRC0_BASE (0x40026000UL) /* QPRC0 Base Address */ +#define FM_QPRC0_NF_BASE (0x40026100UL) /* QPRC0_NF Base Address */ +#define FM4_QPRC0_NF_BASE (0x40026100UL) /* QPRC0_NF Base Address */ +#define FM_QPRC1_BASE (0x40026040UL) /* QPRC1 Base Address */ +#define FM4_QPRC1_BASE (0x40026040UL) /* QPRC1 Base Address */ +#define FM_QPRC1_NF_BASE (0x40026110UL) /* QPRC1_NF Base Address */ +#define FM4_QPRC1_NF_BASE (0x40026110UL) /* QPRC1_NF Base Address */ +#define FM_QPRC2_BASE (0x40026080UL) /* QPRC2 Base Address */ +#define FM4_QPRC2_BASE (0x40026080UL) /* QPRC2 Base Address */ +#define FM_QPRC2_NF_BASE (0x40026120UL) /* QPRC2_NF Base Address */ +#define FM4_QPRC2_NF_BASE (0x40026120UL) /* QPRC2_NF Base Address */ +#define FM_QPRC3_BASE (0x400260C0UL) /* QPRC3 Base Address */ +#define FM4_QPRC3_BASE (0x400260C0UL) /* QPRC3 Base Address */ +#define FM_QPRC3_NF_BASE (0x40026130UL) /* QPRC3_NF Base Address */ +#define FM4_QPRC3_NF_BASE (0x40026130UL) /* QPRC3_NF Base Address */ +#define FM_RTC_BASE (0x4003B100UL) /* RTC Base Address */ +#define FM4_RTC_BASE (0x4003B100UL) /* RTC Base Address */ +#define FM_SBSSR_BASE (0x40025F00UL) /* SBSSR Base Address */ +#define FM4_SBSSR_BASE (0x40025F00UL) /* SBSSR Base Address */ +#define FM_SDIF_BASE (0x4006E000UL) /* SDIF Base Address */ +#define FM4_SDIF_BASE (0x4006E000UL) /* SDIF Base Address */ +#define FM_SWWDT_BASE (0x40012000UL) /* SWWDT Base Address */ +#define FM4_SWWDT_BASE (0x40012000UL) /* SWWDT Base Address */ +#define FM_UNIQUE_ID_BASE (0x40000200UL) /* UNIQUE_ID Base Address */ +#define FM4_UNIQUE_ID_BASE (0x40000200UL) /* UNIQUE_ID Base Address */ +#define FM_USB0_BASE (0x40040000UL) /* USB0 Base Address */ +#define FM4_USB0_BASE (0x40040000UL) /* USB0 Base Address */ +#define FM_USB1_BASE (0x40052100UL) /* USB1 Base Address */ +#define FM4_USB1_BASE (0x40052100UL) /* USB1 Base Address */ +#define FM_USBCLK_BASE (0x40036000UL) /* USBCLK Base Address */ +#define FM4_USBCLK_BASE (0x40036000UL) /* USBCLK Base Address */ +#define FM_WC_BASE (0x4003A000UL) /* WC Base Address */ +#define FM4_WC_BASE (0x4003A000UL) /* WC Base Address */ +/******************************************************************************* +* Peripheral declaration +*******************************************************************************/ +#define FM4_ADC0 ((FM_ADC_TypeDef *)FM4_ADC0_BASE) +#define FM_ADC0 ((FM_ADC_TypeDef *)FM4_ADC0_BASE) +#define FM4_ADC1 ((FM_ADC_TypeDef *)FM4_ADC1_BASE) +#define FM_ADC1 ((FM_ADC_TypeDef *)FM4_ADC1_BASE) +#define FM4_ADC2 ((FM_ADC_TypeDef *)FM4_ADC2_BASE) +#define FM_ADC2 ((FM_ADC_TypeDef *)FM4_ADC2_BASE) +#define FM4_BT0 ((FM_BT_TypeDef *)FM4_BT0_BASE) +#define FM_BT0 ((FM_BT_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_PPG ((FM_BT_PPG_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_PPG ((FM_BT_PPG_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_PWC ((FM_BT_PWC_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_PWC ((FM_BT_PWC_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_PWM ((FM_BT_PWM_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_PWM ((FM_BT_PWM_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_RT ((FM_BT_RT_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_RT ((FM_BT_RT_TypeDef *)FM4_BT0_BASE) +#define FM4_BT1 ((FM_BT_TypeDef *)FM4_BT1_BASE) +#define FM_BT1 ((FM_BT_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_PPG ((FM_BT_PPG_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_PPG ((FM_BT_PPG_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_PWC ((FM_BT_PWC_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_PWC ((FM_BT_PWC_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_PWM ((FM_BT_PWM_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_PWM ((FM_BT_PWM_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_RT ((FM_BT_RT_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_RT ((FM_BT_RT_TypeDef *)FM4_BT1_BASE) +#define FM4_BT10 ((FM_BT_TypeDef *)FM4_BT10_BASE) +#define FM_BT10 ((FM_BT_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_PPG ((FM_BT_PPG_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_PPG ((FM_BT_PPG_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_PWC ((FM_BT_PWC_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_PWC ((FM_BT_PWC_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_PWM ((FM_BT_PWM_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_PWM ((FM_BT_PWM_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_RT ((FM_BT_RT_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_RT ((FM_BT_RT_TypeDef *)FM4_BT10_BASE) +#define FM4_BT11 ((FM_BT_TypeDef *)FM4_BT11_BASE) +#define FM_BT11 ((FM_BT_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_PPG ((FM_BT_PPG_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_PPG ((FM_BT_PPG_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_PWC ((FM_BT_PWC_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_PWC ((FM_BT_PWC_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_PWM ((FM_BT_PWM_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_PWM ((FM_BT_PWM_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_RT ((FM_BT_RT_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_RT ((FM_BT_RT_TypeDef *)FM4_BT11_BASE) +#define FM4_BT12 ((FM_BT_TypeDef *)FM4_BT12_BASE) +#define FM_BT12 ((FM_BT_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_PPG ((FM_BT_PPG_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_PPG ((FM_BT_PPG_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_PWC ((FM_BT_PWC_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_PWC ((FM_BT_PWC_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_PWM ((FM_BT_PWM_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_PWM ((FM_BT_PWM_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_RT ((FM_BT_RT_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_RT ((FM_BT_RT_TypeDef *)FM4_BT12_BASE) +#define FM4_BT13 ((FM_BT_TypeDef *)FM4_BT13_BASE) +#define FM_BT13 ((FM_BT_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_PPG ((FM_BT_PPG_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_PPG ((FM_BT_PPG_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_PWC ((FM_BT_PWC_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_PWC ((FM_BT_PWC_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_PWM ((FM_BT_PWM_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_PWM ((FM_BT_PWM_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_RT ((FM_BT_RT_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_RT ((FM_BT_RT_TypeDef *)FM4_BT13_BASE) +#define FM4_BT14 ((FM_BT_TypeDef *)FM4_BT14_BASE) +#define FM_BT14 ((FM_BT_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_PPG ((FM_BT_PPG_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_PPG ((FM_BT_PPG_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_PWC ((FM_BT_PWC_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_PWC ((FM_BT_PWC_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_PWM ((FM_BT_PWM_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_PWM ((FM_BT_PWM_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_RT ((FM_BT_RT_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_RT ((FM_BT_RT_TypeDef *)FM4_BT14_BASE) +#define FM4_BT15 ((FM_BT_TypeDef *)FM4_BT15_BASE) +#define FM_BT15 ((FM_BT_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_PPG ((FM_BT_PPG_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_PPG ((FM_BT_PPG_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_PWC ((FM_BT_PWC_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_PWC ((FM_BT_PWC_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_PWM ((FM_BT_PWM_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_PWM ((FM_BT_PWM_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_RT ((FM_BT_RT_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_RT ((FM_BT_RT_TypeDef *)FM4_BT15_BASE) +#define FM4_BT2 ((FM_BT_TypeDef *)FM4_BT2_BASE) +#define FM_BT2 ((FM_BT_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_PPG ((FM_BT_PPG_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_PPG ((FM_BT_PPG_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_PWC ((FM_BT_PWC_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_PWC ((FM_BT_PWC_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_PWM ((FM_BT_PWM_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_PWM ((FM_BT_PWM_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_RT ((FM_BT_RT_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_RT ((FM_BT_RT_TypeDef *)FM4_BT2_BASE) +#define FM4_BT3 ((FM_BT_TypeDef *)FM4_BT3_BASE) +#define FM_BT3 ((FM_BT_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_PPG ((FM_BT_PPG_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_PPG ((FM_BT_PPG_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_PWC ((FM_BT_PWC_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_PWC ((FM_BT_PWC_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_PWM ((FM_BT_PWM_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_PWM ((FM_BT_PWM_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_RT ((FM_BT_RT_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_RT ((FM_BT_RT_TypeDef *)FM4_BT3_BASE) +#define FM4_BT4 ((FM_BT_TypeDef *)FM4_BT4_BASE) +#define FM_BT4 ((FM_BT_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_PPG ((FM_BT_PPG_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_PPG ((FM_BT_PPG_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_PWC ((FM_BT_PWC_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_PWC ((FM_BT_PWC_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_PWM ((FM_BT_PWM_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_PWM ((FM_BT_PWM_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_RT ((FM_BT_RT_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_RT ((FM_BT_RT_TypeDef *)FM4_BT4_BASE) +#define FM4_BT5 ((FM_BT_TypeDef *)FM4_BT5_BASE) +#define FM_BT5 ((FM_BT_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_PPG ((FM_BT_PPG_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_PPG ((FM_BT_PPG_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_PWC ((FM_BT_PWC_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_PWC ((FM_BT_PWC_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_PWM ((FM_BT_PWM_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_PWM ((FM_BT_PWM_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_RT ((FM_BT_RT_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_RT ((FM_BT_RT_TypeDef *)FM4_BT5_BASE) +#define FM4_BT6 ((FM_BT_TypeDef *)FM4_BT6_BASE) +#define FM_BT6 ((FM_BT_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_PPG ((FM_BT_PPG_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_PPG ((FM_BT_PPG_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_PWC ((FM_BT_PWC_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_PWC ((FM_BT_PWC_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_PWM ((FM_BT_PWM_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_PWM ((FM_BT_PWM_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_RT ((FM_BT_RT_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_RT ((FM_BT_RT_TypeDef *)FM4_BT6_BASE) +#define FM4_BT7 ((FM_BT_TypeDef *)FM4_BT7_BASE) +#define FM_BT7 ((FM_BT_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_PPG ((FM_BT_PPG_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_PPG ((FM_BT_PPG_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_PWC ((FM_BT_PWC_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_PWC ((FM_BT_PWC_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_PWM ((FM_BT_PWM_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_PWM ((FM_BT_PWM_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_RT ((FM_BT_RT_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_RT ((FM_BT_RT_TypeDef *)FM4_BT7_BASE) +#define FM4_BT8 ((FM_BT_TypeDef *)FM4_BT8_BASE) +#define FM_BT8 ((FM_BT_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_PPG ((FM_BT_PPG_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_PPG ((FM_BT_PPG_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_PWC ((FM_BT_PWC_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_PWC ((FM_BT_PWC_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_PWM ((FM_BT_PWM_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_PWM ((FM_BT_PWM_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_RT ((FM_BT_RT_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_RT ((FM_BT_RT_TypeDef *)FM4_BT8_BASE) +#define FM4_BT9 ((FM_BT_TypeDef *)FM4_BT9_BASE) +#define FM_BT9 ((FM_BT_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_PPG ((FM_BT_PPG_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_PPG ((FM_BT_PPG_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_PWC ((FM_BT_PWC_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_PWC ((FM_BT_PWC_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_PWM ((FM_BT_PWM_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_PWM ((FM_BT_PWM_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_RT ((FM_BT_RT_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_RT ((FM_BT_RT_TypeDef *)FM4_BT9_BASE) +#define FM4_BTIOSEL03 ((FM_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE) +#define FM_BTIOSEL03 ((FM_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE) +#define FM4_BTIOSEL47 ((FM_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE) +#define FM_BTIOSEL47 ((FM_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE) +#define FM4_BTIOSEL8B ((FM_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE) +#define FM_BTIOSEL8B ((FM_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE) +#define FM4_BTIOSELCF ((FM_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE) +#define FM_BTIOSELCF ((FM_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE) +#define FM4_CAN0 ((FM_CAN_TypeDef *)FM4_CAN0_BASE) +#define FM_CAN0 ((FM_CAN_TypeDef *)FM4_CAN0_BASE) +#define FM4_CAN1 ((FM_CAN_TypeDef *)FM4_CAN1_BASE) +#define FM_CAN1 ((FM_CAN_TypeDef *)FM4_CAN1_BASE) +#define FM4_CANFD0 ((FM_CANFD_TypeDef *)FM4_CANFD0_BASE) +#define FM_CANFD0 ((FM_CANFD_TypeDef *)FM4_CANFD0_BASE) +#define FM4_CANPRES ((FM_CANPRES_TypeDef *)FM4_CANPRES_BASE) +#define FM_CANPRES ((FM_CANPRES_TypeDef *)FM4_CANPRES_BASE) +#define FM4_CLK_GATING ((FM_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE) +#define FM_CLK_GATING ((FM_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE) +#define FM4_CRC ((FM_CRC_TypeDef *)FM4_CRC_BASE) +#define FM_CRC ((FM_CRC_TypeDef *)FM4_CRC_BASE) +#define FM4_CRG ((FM_CRG_TypeDef *)FM4_CRG_BASE) +#define FM_CRG ((FM_CRG_TypeDef *)FM4_CRG_BASE) +#define FM4_CRTRIM ((FM_CRTRIM_TypeDef *)FM4_CRTRIM_BASE) +#define FM_CRTRIM ((FM_CRTRIM_TypeDef *)FM4_CRTRIM_BASE) +#define FM4_DAC0 ((FM_DAC_TypeDef *)FM4_DAC0_BASE) +#define FM_DAC0 ((FM_DAC_TypeDef *)FM4_DAC0_BASE) +#define FM4_DAC1 ((FM_DAC_TypeDef *)FM4_DAC1_BASE) +#define FM_DAC1 ((FM_DAC_TypeDef *)FM4_DAC1_BASE) +#define FM4_DMAC ((FM_DMAC_TypeDef *)FM4_DMAC_BASE) +#define FM_DMAC ((FM_DMAC_TypeDef *)FM4_DMAC_BASE) +#define FM4_DS ((FM_DS_TypeDef *)FM4_DS_BASE) +#define FM_DS ((FM_DS_TypeDef *)FM4_DS_BASE) +#define FM4_DSTC ((FM_DSTC_TypeDef *)FM4_DSTC_BASE) +#define FM_DSTC ((FM_DSTC_TypeDef *)FM4_DSTC_BASE) +#define FM4_DT ((FM_DT_TypeDef *)FM4_DT_BASE) +#define FM_DT ((FM_DT_TypeDef *)FM4_DT_BASE) +#define FM4_DUALFLASH_IF ((FM_DUALFLASH_IF_TypeDef *)FM4_DUALFLASH_IF_BASE) +#define FM_DUALFLASH_IF ((FM_DUALFLASH_IF_TypeDef *)FM4_DUALFLASH_IF_BASE) +#define FM4_ECC_CAPTURE ((FM_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE) +#define FM_ECC_CAPTURE ((FM_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE) +#define FM4_EXBUS ((FM_EXBUS_TypeDef *)FM4_EXBUS_BASE) +#define FM_EXBUS ((FM_EXBUS_TypeDef *)FM4_EXBUS_BASE) +#define FM4_EXTI ((FM_EXTI_TypeDef *)FM4_EXTI_BASE) +#define FM_EXTI ((FM_EXTI_TypeDef *)FM4_EXTI_BASE) +#define FM4_FLASH_IF ((FM_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE) +#define FM_FLASH_IF ((FM_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE) +#define FM4_GPIO ((FM_GPIO_TypeDef *)FM4_GPIO_BASE) +#define FM_GPIO ((FM_GPIO_TypeDef *)FM4_GPIO_BASE) +#define FM4_HSSPI ((FM_HSSPI_TypeDef *)FM4_HSSPI_BASE) +#define FM_HSSPI ((FM_HSSPI_TypeDef *)FM4_HSSPI_BASE) +#define FM4_HWWDT ((FM_HWWDT_TypeDef *)FM4_HWWDT_BASE) +#define FM_HWWDT ((FM_HWWDT_TypeDef *)FM4_HWWDT_BASE) +#define FM4_I2S0 ((FM_I2S_TypeDef *)FM4_I2S0_BASE) +#define FM_I2S0 ((FM_I2S_TypeDef *)FM4_I2S0_BASE) +#define FM4_I2SPRE ((FM_I2SPRE_TypeDef *)FM4_I2SPRE_BASE) +#define FM_I2SPRE ((FM_I2SPRE_TypeDef *)FM4_I2SPRE_BASE) +#define FM4_INTREQ ((FM_INTREQ_TypeDef *)FM4_INTREQ_BASE) +#define FM_INTREQ ((FM_INTREQ_TypeDef *)FM4_INTREQ_BASE) +#define FM4_LSCRP ((FM_LSCRP_TypeDef *)FM4_LSCRP_BASE) +#define FM_LSCRP ((FM_LSCRP_TypeDef *)FM4_LSCRP_BASE) +#define FM4_LVD ((FM_LVD_TypeDef *)FM4_LVD_BASE) +#define FM_LVD ((FM_LVD_TypeDef *)FM4_LVD_BASE) +#define FM4_MFS0 ((FM_MFS_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0 ((FM_MFS_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_UART ((FM_MFS_UART_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_UART ((FM_MFS_UART_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS1 ((FM_MFS_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1 ((FM_MFS_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_UART ((FM_MFS_UART_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_UART ((FM_MFS_UART_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS10 ((FM_MFS_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10 ((FM_MFS_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_UART ((FM_MFS_UART_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_UART ((FM_MFS_UART_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS11 ((FM_MFS_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11 ((FM_MFS_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_UART ((FM_MFS_UART_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_UART ((FM_MFS_UART_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS12 ((FM_MFS_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12 ((FM_MFS_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_UART ((FM_MFS_UART_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_UART ((FM_MFS_UART_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS13 ((FM_MFS_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13 ((FM_MFS_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_UART ((FM_MFS_UART_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_UART ((FM_MFS_UART_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS14 ((FM_MFS_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14 ((FM_MFS_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_UART ((FM_MFS_UART_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_UART ((FM_MFS_UART_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS15 ((FM_MFS_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15 ((FM_MFS_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_UART ((FM_MFS_UART_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_UART ((FM_MFS_UART_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS2 ((FM_MFS_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2 ((FM_MFS_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_UART ((FM_MFS_UART_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_UART ((FM_MFS_UART_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS3 ((FM_MFS_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3 ((FM_MFS_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_UART ((FM_MFS_UART_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_UART ((FM_MFS_UART_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS4 ((FM_MFS_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4 ((FM_MFS_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_UART ((FM_MFS_UART_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_UART ((FM_MFS_UART_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS5 ((FM_MFS_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5 ((FM_MFS_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_UART ((FM_MFS_UART_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_UART ((FM_MFS_UART_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS6 ((FM_MFS_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6 ((FM_MFS_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_UART ((FM_MFS_UART_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_UART ((FM_MFS_UART_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS7 ((FM_MFS_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7 ((FM_MFS_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_UART ((FM_MFS_UART_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_UART ((FM_MFS_UART_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS8 ((FM_MFS_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8 ((FM_MFS_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_UART ((FM_MFS_UART_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_UART ((FM_MFS_UART_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS9 ((FM_MFS_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9 ((FM_MFS_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_UART ((FM_MFS_UART_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_UART ((FM_MFS_UART_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFT_PPG ((FM_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE) +#define FM_MFT_PPG ((FM_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE) +#define FM4_MFT0 ((FM_MFT_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0 ((FM_MFT_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT1 ((FM_MFT_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1 ((FM_MFT_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT2 ((FM_MFT_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2 ((FM_MFT_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT2_BASE) +#define FM4_PCRC ((FM_PCRC_TypeDef *)FM4_PCRC_BASE) +#define FM_PCRC ((FM_PCRC_TypeDef *)FM4_PCRC_BASE) +#define FM4_QPRC0 ((FM_QPRC_TypeDef *)FM4_QPRC0_BASE) +#define FM_QPRC0 ((FM_QPRC_TypeDef *)FM4_QPRC0_BASE) +#define FM4_QPRC0_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE) +#define FM_QPRC0_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE) +#define FM4_QPRC1 ((FM_QPRC_TypeDef *)FM4_QPRC1_BASE) +#define FM_QPRC1 ((FM_QPRC_TypeDef *)FM4_QPRC1_BASE) +#define FM4_QPRC1_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE) +#define FM_QPRC1_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE) +#define FM4_QPRC2 ((FM_QPRC_TypeDef *)FM4_QPRC2_BASE) +#define FM_QPRC2 ((FM_QPRC_TypeDef *)FM4_QPRC2_BASE) +#define FM4_QPRC2_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE) +#define FM_QPRC2_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE) +#define FM4_QPRC3 ((FM_QPRC_TypeDef *)FM4_QPRC3_BASE) +#define FM_QPRC3 ((FM_QPRC_TypeDef *)FM4_QPRC3_BASE) +#define FM4_QPRC3_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE) +#define FM_QPRC3_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE) +#define FM4_RTC ((FM_RTC_TypeDef *)FM4_RTC_BASE) +#define FM_RTC ((FM_RTC_TypeDef *)FM4_RTC_BASE) +#define FM4_SBSSR ((FM_SBSSR_TypeDef *)FM4_SBSSR_BASE) +#define FM_SBSSR ((FM_SBSSR_TypeDef *)FM4_SBSSR_BASE) +#define FM4_SDIF ((FM_SDIF_TypeDef *)FM4_SDIF_BASE) +#define FM_SDIF ((FM_SDIF_TypeDef *)FM4_SDIF_BASE) +#define FM4_SWWDT ((FM_SWWDT_TypeDef *)FM4_SWWDT_BASE) +#define FM_SWWDT ((FM_SWWDT_TypeDef *)FM4_SWWDT_BASE) +#define FM4_UNIQUE_ID ((FM_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE) +#define FM_UNIQUE_ID ((FM_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE) +#define FM4_USB0 ((FM_USB_TypeDef *)FM4_USB0_BASE) +#define FM_USB0 ((FM_USB_TypeDef *)FM4_USB0_BASE) +#define FM4_USB1 ((FM_USB_TypeDef *)FM4_USB1_BASE) +#define FM_USB1 ((FM_USB_TypeDef *)FM4_USB1_BASE) +#define FM4_USBCLK ((FM_USBCLK_TypeDef *)FM4_USBCLK_BASE) +#define FM_USBCLK ((FM_USBCLK_TypeDef *)FM4_USBCLK_BASE) +#define FM4_WC ((FM_WC_TypeDef *)FM4_WC_BASE) +#define FM_WC ((FM_WC_TypeDef *)FM4_WC_BASE) +/******************************************************************************* +* Register Definitions +*******************************************************************************/ +/******************************************************************************* +* ADC Registers ADC0 +* Register Definition +*******************************************************************************/ +#define FM_ADC0_ADSR *((volatile uint8_t*)(0x40027000UL)) +#define FM4_ADC0_ADSR *((volatile uint8_t*)(0x40027000UL)) +#define FM_ADC0_ADCR *((volatile uint8_t*)(0x40027001UL)) +#define FM4_ADC0_ADCR *((volatile uint8_t*)(0x40027001UL)) +#define FM_ADC0_SFNS *((volatile uint8_t*)(0x40027008UL)) +#define FM4_ADC0_SFNS *((volatile uint8_t*)(0x40027008UL)) +#define FM_ADC0_SCCR *((volatile uint8_t*)(0x40027009UL)) +#define FM4_ADC0_SCCR *((volatile uint8_t*)(0x40027009UL)) +#define FM_ADC0_SCFD *((volatile uint32_t*)(0x4002700CUL)) +#define FM4_ADC0_SCFD *((volatile uint32_t*)(0x4002700CUL)) +#define FM_ADC0_SCFD_FDAS1 *((volatile uint32_t*)(0x4002700CUL)) +#define FM4_ADC0_SCFD_FDAS1 *((volatile uint32_t*)(0x4002700CUL)) +#define FM_ADC0_SCIS23 *((volatile uint16_t*)(0x40027010UL)) +#define FM4_ADC0_SCIS23 *((volatile uint16_t*)(0x40027010UL)) +#define FM_ADC0_SCIS01 *((volatile uint16_t*)(0x40027014UL)) +#define FM4_ADC0_SCIS01 *((volatile uint16_t*)(0x40027014UL)) +#define FM_ADC0_PFNS *((volatile uint8_t*)(0x40027018UL)) +#define FM4_ADC0_PFNS *((volatile uint8_t*)(0x40027018UL)) +#define FM_ADC0_PCCR *((volatile uint8_t*)(0x40027019UL)) +#define FM4_ADC0_PCCR *((volatile uint8_t*)(0x40027019UL)) +#define FM_ADC0_PCFD *((volatile uint32_t*)(0x4002701CUL)) +#define FM4_ADC0_PCFD *((volatile uint32_t*)(0x4002701CUL)) +#define FM_ADC0_PCFD_FDAS1 *((volatile uint32_t*)(0x4002701CUL)) +#define FM4_ADC0_PCFD_FDAS1 *((volatile uint32_t*)(0x4002701CUL)) +#define FM_ADC0_PCIS *((volatile uint8_t*)(0x40027020UL)) +#define FM4_ADC0_PCIS *((volatile uint8_t*)(0x40027020UL)) +#define FM_ADC0_CMPCR *((volatile uint8_t*)(0x40027024UL)) +#define FM4_ADC0_CMPCR *((volatile uint8_t*)(0x40027024UL)) +#define FM_ADC0_CMPD *((volatile uint16_t*)(0x40027026UL)) +#define FM4_ADC0_CMPD *((volatile uint16_t*)(0x40027026UL)) +#define FM_ADC0_ADSS23 *((volatile uint16_t*)(0x40027028UL)) +#define FM4_ADC0_ADSS23 *((volatile uint16_t*)(0x40027028UL)) +#define FM_ADC0_ADSS01 *((volatile uint16_t*)(0x4002702CUL)) +#define FM4_ADC0_ADSS01 *((volatile uint16_t*)(0x4002702CUL)) +#define FM_ADC0_ADST01 *((volatile uint16_t*)(0x40027030UL)) +#define FM4_ADC0_ADST01 *((volatile uint16_t*)(0x40027030UL)) +#define FM_ADC0_ADCT *((volatile uint8_t*)(0x40027034UL)) +#define FM4_ADC0_ADCT *((volatile uint8_t*)(0x40027034UL)) +#define FM_ADC0_PRTSL *((volatile uint8_t*)(0x40027038UL)) +#define FM4_ADC0_PRTSL *((volatile uint8_t*)(0x40027038UL)) +#define FM_ADC0_SCTSL *((volatile uint8_t*)(0x40027039UL)) +#define FM4_ADC0_SCTSL *((volatile uint8_t*)(0x40027039UL)) +#define FM_ADC0_ADCEN *((volatile uint16_t*)(0x4002703CUL)) +#define FM4_ADC0_ADCEN *((volatile uint16_t*)(0x4002703CUL)) +#define FM_ADC0_CALSR *((volatile uint32_t*)(0x40027040UL)) +#define FM4_ADC0_CALSR *((volatile uint32_t*)(0x40027040UL)) +#define FM_ADC0_WCMRCOT *((volatile uint8_t*)(0x40027044UL)) +#define FM4_ADC0_WCMRCOT *((volatile uint8_t*)(0x40027044UL)) +#define FM_ADC0_WCMRCIF *((volatile uint8_t*)(0x40027048UL)) +#define FM4_ADC0_WCMRCIF *((volatile uint8_t*)(0x40027048UL)) +#define FM_ADC0_WCMPCR *((volatile uint8_t*)(0x4002704CUL)) +#define FM4_ADC0_WCMPCR *((volatile uint8_t*)(0x4002704CUL)) +#define FM_ADC0_WCMPSR *((volatile uint8_t*)(0x4002704DUL)) +#define FM4_ADC0_WCMPSR *((volatile uint8_t*)(0x4002704DUL)) +#define FM_ADC0_WCMPDL *((volatile uint16_t*)(0x40027050UL)) +#define FM4_ADC0_WCMPDL *((volatile uint16_t*)(0x40027050UL)) +#define FM_ADC0_WCMPDH *((volatile uint16_t*)(0x40027052UL)) +#define FM4_ADC0_WCMPDH *((volatile uint16_t*)(0x40027052UL)) + +/******************************************************************************* +* ADC Registers ADC1 +* Register Definition +*******************************************************************************/ +#define FM_ADC1_ADSR *((volatile uint8_t*)(0x40027100UL)) +#define FM4_ADC1_ADSR *((volatile uint8_t*)(0x40027100UL)) +#define FM_ADC1_ADCR *((volatile uint8_t*)(0x40027101UL)) +#define FM4_ADC1_ADCR *((volatile uint8_t*)(0x40027101UL)) +#define FM_ADC1_SFNS *((volatile uint8_t*)(0x40027108UL)) +#define FM4_ADC1_SFNS *((volatile uint8_t*)(0x40027108UL)) +#define FM_ADC1_SCCR *((volatile uint8_t*)(0x40027109UL)) +#define FM4_ADC1_SCCR *((volatile uint8_t*)(0x40027109UL)) +#define FM_ADC1_SCFD *((volatile uint32_t*)(0x4002710CUL)) +#define FM4_ADC1_SCFD *((volatile uint32_t*)(0x4002710CUL)) +#define FM_ADC1_SCFD_FDAS1 *((volatile uint32_t*)(0x4002710CUL)) +#define FM4_ADC1_SCFD_FDAS1 *((volatile uint32_t*)(0x4002710CUL)) +#define FM_ADC1_SCIS23 *((volatile uint16_t*)(0x40027110UL)) +#define FM4_ADC1_SCIS23 *((volatile uint16_t*)(0x40027110UL)) +#define FM_ADC1_SCIS01 *((volatile uint16_t*)(0x40027114UL)) +#define FM4_ADC1_SCIS01 *((volatile uint16_t*)(0x40027114UL)) +#define FM_ADC1_PFNS *((volatile uint8_t*)(0x40027118UL)) +#define FM4_ADC1_PFNS *((volatile uint8_t*)(0x40027118UL)) +#define FM_ADC1_PCCR *((volatile uint8_t*)(0x40027119UL)) +#define FM4_ADC1_PCCR *((volatile uint8_t*)(0x40027119UL)) +#define FM_ADC1_PCFD *((volatile uint32_t*)(0x4002711CUL)) +#define FM4_ADC1_PCFD *((volatile uint32_t*)(0x4002711CUL)) +#define FM_ADC1_PCFD_FDAS1 *((volatile uint32_t*)(0x4002711CUL)) +#define FM4_ADC1_PCFD_FDAS1 *((volatile uint32_t*)(0x4002711CUL)) +#define FM_ADC1_PCIS *((volatile uint8_t*)(0x40027120UL)) +#define FM4_ADC1_PCIS *((volatile uint8_t*)(0x40027120UL)) +#define FM_ADC1_CMPCR *((volatile uint8_t*)(0x40027124UL)) +#define FM4_ADC1_CMPCR *((volatile uint8_t*)(0x40027124UL)) +#define FM_ADC1_CMPD *((volatile uint16_t*)(0x40027126UL)) +#define FM4_ADC1_CMPD *((volatile uint16_t*)(0x40027126UL)) +#define FM_ADC1_ADSS23 *((volatile uint16_t*)(0x40027128UL)) +#define FM4_ADC1_ADSS23 *((volatile uint16_t*)(0x40027128UL)) +#define FM_ADC1_ADSS01 *((volatile uint16_t*)(0x4002712CUL)) +#define FM4_ADC1_ADSS01 *((volatile uint16_t*)(0x4002712CUL)) +#define FM_ADC1_ADST01 *((volatile uint16_t*)(0x40027130UL)) +#define FM4_ADC1_ADST01 *((volatile uint16_t*)(0x40027130UL)) +#define FM_ADC1_ADCT *((volatile uint8_t*)(0x40027134UL)) +#define FM4_ADC1_ADCT *((volatile uint8_t*)(0x40027134UL)) +#define FM_ADC1_PRTSL *((volatile uint8_t*)(0x40027138UL)) +#define FM4_ADC1_PRTSL *((volatile uint8_t*)(0x40027138UL)) +#define FM_ADC1_SCTSL *((volatile uint8_t*)(0x40027139UL)) +#define FM4_ADC1_SCTSL *((volatile uint8_t*)(0x40027139UL)) +#define FM_ADC1_ADCEN *((volatile uint16_t*)(0x4002713CUL)) +#define FM4_ADC1_ADCEN *((volatile uint16_t*)(0x4002713CUL)) +#define FM_ADC1_CALSR *((volatile uint32_t*)(0x40027140UL)) +#define FM4_ADC1_CALSR *((volatile uint32_t*)(0x40027140UL)) +#define FM_ADC1_WCMRCOT *((volatile uint8_t*)(0x40027144UL)) +#define FM4_ADC1_WCMRCOT *((volatile uint8_t*)(0x40027144UL)) +#define FM_ADC1_WCMRCIF *((volatile uint8_t*)(0x40027148UL)) +#define FM4_ADC1_WCMRCIF *((volatile uint8_t*)(0x40027148UL)) +#define FM_ADC1_WCMPCR *((volatile uint8_t*)(0x4002714CUL)) +#define FM4_ADC1_WCMPCR *((volatile uint8_t*)(0x4002714CUL)) +#define FM_ADC1_WCMPSR *((volatile uint8_t*)(0x4002714DUL)) +#define FM4_ADC1_WCMPSR *((volatile uint8_t*)(0x4002714DUL)) +#define FM_ADC1_WCMPDL *((volatile uint16_t*)(0x40027150UL)) +#define FM4_ADC1_WCMPDL *((volatile uint16_t*)(0x40027150UL)) +#define FM_ADC1_WCMPDH *((volatile uint16_t*)(0x40027152UL)) +#define FM4_ADC1_WCMPDH *((volatile uint16_t*)(0x40027152UL)) + +/******************************************************************************* +* ADC Registers ADC2 +* Register Definition +*******************************************************************************/ +#define FM_ADC2_ADSR *((volatile uint8_t*)(0x40027200UL)) +#define FM4_ADC2_ADSR *((volatile uint8_t*)(0x40027200UL)) +#define FM_ADC2_ADCR *((volatile uint8_t*)(0x40027201UL)) +#define FM4_ADC2_ADCR *((volatile uint8_t*)(0x40027201UL)) +#define FM_ADC2_SFNS *((volatile uint8_t*)(0x40027208UL)) +#define FM4_ADC2_SFNS *((volatile uint8_t*)(0x40027208UL)) +#define FM_ADC2_SCCR *((volatile uint8_t*)(0x40027209UL)) +#define FM4_ADC2_SCCR *((volatile uint8_t*)(0x40027209UL)) +#define FM_ADC2_SCFD *((volatile uint32_t*)(0x4002720CUL)) +#define FM4_ADC2_SCFD *((volatile uint32_t*)(0x4002720CUL)) +#define FM_ADC2_SCFD_FDAS1 *((volatile uint32_t*)(0x4002720CUL)) +#define FM4_ADC2_SCFD_FDAS1 *((volatile uint32_t*)(0x4002720CUL)) +#define FM_ADC2_SCIS23 *((volatile uint16_t*)(0x40027210UL)) +#define FM4_ADC2_SCIS23 *((volatile uint16_t*)(0x40027210UL)) +#define FM_ADC2_SCIS01 *((volatile uint16_t*)(0x40027214UL)) +#define FM4_ADC2_SCIS01 *((volatile uint16_t*)(0x40027214UL)) +#define FM_ADC2_PFNS *((volatile uint8_t*)(0x40027218UL)) +#define FM4_ADC2_PFNS *((volatile uint8_t*)(0x40027218UL)) +#define FM_ADC2_PCCR *((volatile uint8_t*)(0x40027219UL)) +#define FM4_ADC2_PCCR *((volatile uint8_t*)(0x40027219UL)) +#define FM_ADC2_PCFD *((volatile uint32_t*)(0x4002721CUL)) +#define FM4_ADC2_PCFD *((volatile uint32_t*)(0x4002721CUL)) +#define FM_ADC2_PCFD_FDAS1 *((volatile uint32_t*)(0x4002721CUL)) +#define FM4_ADC2_PCFD_FDAS1 *((volatile uint32_t*)(0x4002721CUL)) +#define FM_ADC2_PCIS *((volatile uint8_t*)(0x40027220UL)) +#define FM4_ADC2_PCIS *((volatile uint8_t*)(0x40027220UL)) +#define FM_ADC2_CMPCR *((volatile uint8_t*)(0x40027224UL)) +#define FM4_ADC2_CMPCR *((volatile uint8_t*)(0x40027224UL)) +#define FM_ADC2_CMPD *((volatile uint16_t*)(0x40027226UL)) +#define FM4_ADC2_CMPD *((volatile uint16_t*)(0x40027226UL)) +#define FM_ADC2_ADSS23 *((volatile uint16_t*)(0x40027228UL)) +#define FM4_ADC2_ADSS23 *((volatile uint16_t*)(0x40027228UL)) +#define FM_ADC2_ADSS01 *((volatile uint16_t*)(0x4002722CUL)) +#define FM4_ADC2_ADSS01 *((volatile uint16_t*)(0x4002722CUL)) +#define FM_ADC2_ADST01 *((volatile uint16_t*)(0x40027230UL)) +#define FM4_ADC2_ADST01 *((volatile uint16_t*)(0x40027230UL)) +#define FM_ADC2_ADCT *((volatile uint8_t*)(0x40027234UL)) +#define FM4_ADC2_ADCT *((volatile uint8_t*)(0x40027234UL)) +#define FM_ADC2_PRTSL *((volatile uint8_t*)(0x40027238UL)) +#define FM4_ADC2_PRTSL *((volatile uint8_t*)(0x40027238UL)) +#define FM_ADC2_SCTSL *((volatile uint8_t*)(0x40027239UL)) +#define FM4_ADC2_SCTSL *((volatile uint8_t*)(0x40027239UL)) +#define FM_ADC2_ADCEN *((volatile uint16_t*)(0x4002723CUL)) +#define FM4_ADC2_ADCEN *((volatile uint16_t*)(0x4002723CUL)) +#define FM_ADC2_CALSR *((volatile uint32_t*)(0x40027240UL)) +#define FM4_ADC2_CALSR *((volatile uint32_t*)(0x40027240UL)) +#define FM_ADC2_WCMRCOT *((volatile uint8_t*)(0x40027244UL)) +#define FM4_ADC2_WCMRCOT *((volatile uint8_t*)(0x40027244UL)) +#define FM_ADC2_WCMRCIF *((volatile uint8_t*)(0x40027248UL)) +#define FM4_ADC2_WCMRCIF *((volatile uint8_t*)(0x40027248UL)) +#define FM_ADC2_WCMPCR *((volatile uint8_t*)(0x4002724CUL)) +#define FM4_ADC2_WCMPCR *((volatile uint8_t*)(0x4002724CUL)) +#define FM_ADC2_WCMPSR *((volatile uint8_t*)(0x4002724DUL)) +#define FM4_ADC2_WCMPSR *((volatile uint8_t*)(0x4002724DUL)) +#define FM_ADC2_WCMPDL *((volatile uint16_t*)(0x40027250UL)) +#define FM4_ADC2_WCMPDL *((volatile uint16_t*)(0x40027250UL)) +#define FM_ADC2_WCMPDH *((volatile uint16_t*)(0x40027252UL)) +#define FM4_ADC2_WCMPDH *((volatile uint16_t*)(0x40027252UL)) + +/******************************************************************************* +* BT Registers BT0 +* Register Definition +*******************************************************************************/ +#define FM_BT0_PPG_PRLL *((volatile uint16_t*)(0x40025000UL)) +#define FM4_BT0_PPG_PRLL *((volatile uint16_t*)(0x40025000UL)) +#define FM_BT0_PWM_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM4_BT0_PWM_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM_BT0_RT_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM4_BT0_RT_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM_BT0_PPG_PRLH *((volatile uint16_t*)(0x40025004UL)) +#define FM4_BT0_PPG_PRLH *((volatile uint16_t*)(0x40025004UL)) +#define FM_BT0_PWC_DTBF *((volatile uint16_t*)(0x40025004UL)) +#define FM4_BT0_PWC_DTBF *((volatile uint16_t*)(0x40025004UL)) +#define FM_BT0_PWM_PDUT *((volatile uint16_t*)(0x40025004UL)) +#define FM4_BT0_PWM_PDUT *((volatile uint16_t*)(0x40025004UL)) +#define FM_BT0_PPG_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM4_BT0_PPG_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM_BT0_PWM_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM4_BT0_PWM_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM_BT0_RT_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM4_BT0_RT_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM_BT0_PPG_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_PPG_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_PWC_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_PWC_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_PWM_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_PWM_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_RT_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_RT_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_PPG_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_PPG_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_PWC_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_PWC_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_PWM_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_PWM_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_RT_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_RT_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_PPG_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_PPG_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM_BT0_PWC_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_PWC_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM_BT0_PWM_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_PWM_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM_BT0_RT_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_RT_TMCR2 *((volatile uint8_t*)(0x40025011UL)) + +/******************************************************************************* +* BT Registers BT1 +* Register Definition +*******************************************************************************/ +#define FM_BT1_PPG_PRLL *((volatile uint16_t*)(0x40025040UL)) +#define FM4_BT1_PPG_PRLL *((volatile uint16_t*)(0x40025040UL)) +#define FM_BT1_PWM_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM4_BT1_PWM_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM_BT1_RT_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM4_BT1_RT_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM_BT1_PPG_PRLH *((volatile uint16_t*)(0x40025044UL)) +#define FM4_BT1_PPG_PRLH *((volatile uint16_t*)(0x40025044UL)) +#define FM_BT1_PWC_DTBF *((volatile uint16_t*)(0x40025044UL)) +#define FM4_BT1_PWC_DTBF *((volatile uint16_t*)(0x40025044UL)) +#define FM_BT1_PWM_PDUT *((volatile uint16_t*)(0x40025044UL)) +#define FM4_BT1_PWM_PDUT *((volatile uint16_t*)(0x40025044UL)) +#define FM_BT1_PPG_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM4_BT1_PPG_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM_BT1_PWM_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM4_BT1_PWM_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM_BT1_RT_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM4_BT1_RT_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM_BT1_PPG_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_PPG_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_PWC_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_PWC_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_PWM_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_PWM_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_RT_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_RT_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_PPG_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_PPG_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_PWC_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_PWC_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_PWM_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_PWM_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_RT_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_RT_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_PPG_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_PPG_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM_BT1_PWC_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_PWC_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM_BT1_PWM_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_PWM_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM_BT1_RT_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_RT_TMCR2 *((volatile uint8_t*)(0x40025051UL)) + +/******************************************************************************* +* BT Registers BT10 +* Register Definition +*******************************************************************************/ +#define FM_BT10_PPG_PRLL *((volatile uint16_t*)(0x40025480UL)) +#define FM4_BT10_PPG_PRLL *((volatile uint16_t*)(0x40025480UL)) +#define FM_BT10_PWM_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM4_BT10_PWM_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM_BT10_RT_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM4_BT10_RT_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM_BT10_PPG_PRLH *((volatile uint16_t*)(0x40025484UL)) +#define FM4_BT10_PPG_PRLH *((volatile uint16_t*)(0x40025484UL)) +#define FM_BT10_PWC_DTBF *((volatile uint16_t*)(0x40025484UL)) +#define FM4_BT10_PWC_DTBF *((volatile uint16_t*)(0x40025484UL)) +#define FM_BT10_PWM_PDUT *((volatile uint16_t*)(0x40025484UL)) +#define FM4_BT10_PWM_PDUT *((volatile uint16_t*)(0x40025484UL)) +#define FM_BT10_PPG_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM4_BT10_PPG_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM_BT10_PWM_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM4_BT10_PWM_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM_BT10_RT_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM4_BT10_RT_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM_BT10_PPG_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_PPG_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_PWC_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_PWC_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_PWM_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_PWM_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_RT_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_RT_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_PPG_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_PPG_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_PWC_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_PWC_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_PWM_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_PWM_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_RT_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_RT_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_PPG_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_PPG_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM_BT10_PWC_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_PWC_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM_BT10_PWM_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_PWM_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM_BT10_RT_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_RT_TMCR2 *((volatile uint8_t*)(0x40025491UL)) + +/******************************************************************************* +* BT Registers BT11 +* Register Definition +*******************************************************************************/ +#define FM_BT11_PPG_PRLL *((volatile uint16_t*)(0x400254C0UL)) +#define FM4_BT11_PPG_PRLL *((volatile uint16_t*)(0x400254C0UL)) +#define FM_BT11_PWM_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM4_BT11_PWM_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM_BT11_RT_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM4_BT11_RT_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM_BT11_PPG_PRLH *((volatile uint16_t*)(0x400254C4UL)) +#define FM4_BT11_PPG_PRLH *((volatile uint16_t*)(0x400254C4UL)) +#define FM_BT11_PWC_DTBF *((volatile uint16_t*)(0x400254C4UL)) +#define FM4_BT11_PWC_DTBF *((volatile uint16_t*)(0x400254C4UL)) +#define FM_BT11_PWM_PDUT *((volatile uint16_t*)(0x400254C4UL)) +#define FM4_BT11_PWM_PDUT *((volatile uint16_t*)(0x400254C4UL)) +#define FM_BT11_PPG_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM4_BT11_PPG_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM_BT11_PWM_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM4_BT11_PWM_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM_BT11_RT_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM4_BT11_RT_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM_BT11_PPG_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_PPG_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_PWC_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_PWC_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_PWM_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_PWM_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_RT_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_RT_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_PPG_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_PPG_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_PWC_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_PWC_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_PWM_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_PWM_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_RT_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_RT_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_PPG_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_PPG_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM_BT11_PWC_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_PWC_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM_BT11_PWM_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_PWM_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM_BT11_RT_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_RT_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) + +/******************************************************************************* +* BT Registers BT12 +* Register Definition +*******************************************************************************/ +#define FM_BT12_PPG_PRLL *((volatile uint16_t*)(0x40025600UL)) +#define FM4_BT12_PPG_PRLL *((volatile uint16_t*)(0x40025600UL)) +#define FM_BT12_PWM_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM4_BT12_PWM_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM_BT12_RT_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM4_BT12_RT_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM_BT12_PPG_PRLH *((volatile uint16_t*)(0x40025604UL)) +#define FM4_BT12_PPG_PRLH *((volatile uint16_t*)(0x40025604UL)) +#define FM_BT12_PWC_DTBF *((volatile uint16_t*)(0x40025604UL)) +#define FM4_BT12_PWC_DTBF *((volatile uint16_t*)(0x40025604UL)) +#define FM_BT12_PWM_PDUT *((volatile uint16_t*)(0x40025604UL)) +#define FM4_BT12_PWM_PDUT *((volatile uint16_t*)(0x40025604UL)) +#define FM_BT12_PPG_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM4_BT12_PPG_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM_BT12_PWM_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM4_BT12_PWM_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM_BT12_RT_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM4_BT12_RT_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM_BT12_PPG_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_PPG_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_PWC_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_PWC_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_PWM_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_PWM_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_RT_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_RT_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_PPG_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_PPG_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_PWC_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_PWC_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_PWM_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_PWM_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_RT_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_RT_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_PPG_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_PPG_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM_BT12_PWC_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_PWC_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM_BT12_PWM_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_PWM_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM_BT12_RT_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_RT_TMCR2 *((volatile uint8_t*)(0x40025611UL)) + +/******************************************************************************* +* BT Registers BT13 +* Register Definition +*******************************************************************************/ +#define FM_BT13_PPG_PRLL *((volatile uint16_t*)(0x40025640UL)) +#define FM4_BT13_PPG_PRLL *((volatile uint16_t*)(0x40025640UL)) +#define FM_BT13_PWM_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM4_BT13_PWM_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM_BT13_RT_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM4_BT13_RT_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM_BT13_PPG_PRLH *((volatile uint16_t*)(0x40025644UL)) +#define FM4_BT13_PPG_PRLH *((volatile uint16_t*)(0x40025644UL)) +#define FM_BT13_PWC_DTBF *((volatile uint16_t*)(0x40025644UL)) +#define FM4_BT13_PWC_DTBF *((volatile uint16_t*)(0x40025644UL)) +#define FM_BT13_PWM_PDUT *((volatile uint16_t*)(0x40025644UL)) +#define FM4_BT13_PWM_PDUT *((volatile uint16_t*)(0x40025644UL)) +#define FM_BT13_PPG_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM4_BT13_PPG_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM_BT13_PWM_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM4_BT13_PWM_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM_BT13_RT_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM4_BT13_RT_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM_BT13_PPG_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_PPG_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_PWC_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_PWC_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_PWM_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_PWM_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_RT_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_RT_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_PPG_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_PPG_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_PWC_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_PWC_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_PWM_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_PWM_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_RT_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_RT_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_PPG_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_PPG_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM_BT13_PWC_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_PWC_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM_BT13_PWM_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_PWM_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM_BT13_RT_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_RT_TMCR2 *((volatile uint8_t*)(0x40025651UL)) + +/******************************************************************************* +* BT Registers BT14 +* Register Definition +*******************************************************************************/ +#define FM_BT14_PPG_PRLL *((volatile uint16_t*)(0x40025680UL)) +#define FM4_BT14_PPG_PRLL *((volatile uint16_t*)(0x40025680UL)) +#define FM_BT14_PWM_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM4_BT14_PWM_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM_BT14_RT_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM4_BT14_RT_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM_BT14_PPG_PRLH *((volatile uint16_t*)(0x40025684UL)) +#define FM4_BT14_PPG_PRLH *((volatile uint16_t*)(0x40025684UL)) +#define FM_BT14_PWC_DTBF *((volatile uint16_t*)(0x40025684UL)) +#define FM4_BT14_PWC_DTBF *((volatile uint16_t*)(0x40025684UL)) +#define FM_BT14_PWM_PDUT *((volatile uint16_t*)(0x40025684UL)) +#define FM4_BT14_PWM_PDUT *((volatile uint16_t*)(0x40025684UL)) +#define FM_BT14_PPG_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM4_BT14_PPG_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM_BT14_PWM_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM4_BT14_PWM_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM_BT14_RT_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM4_BT14_RT_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM_BT14_PPG_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_PPG_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_PWC_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_PWC_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_PWM_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_PWM_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_RT_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_RT_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_PPG_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_PPG_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_PWC_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_PWC_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_PWM_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_PWM_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_RT_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_RT_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_PPG_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_PPG_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM_BT14_PWC_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_PWC_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM_BT14_PWM_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_PWM_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM_BT14_RT_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_RT_TMCR2 *((volatile uint8_t*)(0x40025691UL)) + +/******************************************************************************* +* BT Registers BT15 +* Register Definition +*******************************************************************************/ +#define FM_BT15_PPG_PRLL *((volatile uint16_t*)(0x400256C0UL)) +#define FM4_BT15_PPG_PRLL *((volatile uint16_t*)(0x400256C0UL)) +#define FM_BT15_PWM_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM4_BT15_PWM_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM_BT15_RT_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM4_BT15_RT_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM_BT15_PPG_PRLH *((volatile uint16_t*)(0x400256C4UL)) +#define FM4_BT15_PPG_PRLH *((volatile uint16_t*)(0x400256C4UL)) +#define FM_BT15_PWC_DTBF *((volatile uint16_t*)(0x400256C4UL)) +#define FM4_BT15_PWC_DTBF *((volatile uint16_t*)(0x400256C4UL)) +#define FM_BT15_PWM_PDUT *((volatile uint16_t*)(0x400256C4UL)) +#define FM4_BT15_PWM_PDUT *((volatile uint16_t*)(0x400256C4UL)) +#define FM_BT15_PPG_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM4_BT15_PPG_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM_BT15_PWM_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM4_BT15_PWM_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM_BT15_RT_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM4_BT15_RT_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM_BT15_PPG_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_PPG_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_PWC_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_PWC_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_PWM_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_PWM_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_RT_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_RT_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_PPG_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_PPG_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_PWC_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_PWC_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_PWM_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_PWM_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_RT_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_RT_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_PPG_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_PPG_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM_BT15_PWC_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_PWC_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM_BT15_PWM_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_PWM_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM_BT15_RT_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_RT_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) + +/******************************************************************************* +* BT Registers BT2 +* Register Definition +*******************************************************************************/ +#define FM_BT2_PPG_PRLL *((volatile uint16_t*)(0x40025080UL)) +#define FM4_BT2_PPG_PRLL *((volatile uint16_t*)(0x40025080UL)) +#define FM_BT2_PWM_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM4_BT2_PWM_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM_BT2_RT_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM4_BT2_RT_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM_BT2_PPG_PRLH *((volatile uint16_t*)(0x40025084UL)) +#define FM4_BT2_PPG_PRLH *((volatile uint16_t*)(0x40025084UL)) +#define FM_BT2_PWC_DTBF *((volatile uint16_t*)(0x40025084UL)) +#define FM4_BT2_PWC_DTBF *((volatile uint16_t*)(0x40025084UL)) +#define FM_BT2_PWM_PDUT *((volatile uint16_t*)(0x40025084UL)) +#define FM4_BT2_PWM_PDUT *((volatile uint16_t*)(0x40025084UL)) +#define FM_BT2_PPG_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM4_BT2_PPG_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM_BT2_PWM_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM4_BT2_PWM_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM_BT2_RT_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM4_BT2_RT_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM_BT2_PPG_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_PPG_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_PWC_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_PWC_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_PWM_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_PWM_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_RT_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_RT_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_PPG_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_PPG_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_PWC_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_PWC_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_PWM_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_PWM_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_RT_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_RT_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_PPG_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_PPG_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM_BT2_PWC_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_PWC_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM_BT2_PWM_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_PWM_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM_BT2_RT_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_RT_TMCR2 *((volatile uint8_t*)(0x40025091UL)) + +/******************************************************************************* +* BT Registers BT3 +* Register Definition +*******************************************************************************/ +#define FM_BT3_PPG_PRLL *((volatile uint16_t*)(0x400250C0UL)) +#define FM4_BT3_PPG_PRLL *((volatile uint16_t*)(0x400250C0UL)) +#define FM_BT3_PWM_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM4_BT3_PWM_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM_BT3_RT_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM4_BT3_RT_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM_BT3_PPG_PRLH *((volatile uint16_t*)(0x400250C4UL)) +#define FM4_BT3_PPG_PRLH *((volatile uint16_t*)(0x400250C4UL)) +#define FM_BT3_PWC_DTBF *((volatile uint16_t*)(0x400250C4UL)) +#define FM4_BT3_PWC_DTBF *((volatile uint16_t*)(0x400250C4UL)) +#define FM_BT3_PWM_PDUT *((volatile uint16_t*)(0x400250C4UL)) +#define FM4_BT3_PWM_PDUT *((volatile uint16_t*)(0x400250C4UL)) +#define FM_BT3_PPG_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM4_BT3_PPG_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM_BT3_PWM_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM4_BT3_PWM_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM_BT3_RT_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM4_BT3_RT_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM_BT3_PPG_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_PPG_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_PWC_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_PWC_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_PWM_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_PWM_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_RT_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_RT_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_PPG_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_PPG_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_PWC_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_PWC_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_PWM_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_PWM_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_RT_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_RT_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_PPG_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_PPG_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM_BT3_PWC_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_PWC_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM_BT3_PWM_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_PWM_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM_BT3_RT_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_RT_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) + +/******************************************************************************* +* BT Registers BT4 +* Register Definition +*******************************************************************************/ +#define FM_BT4_PPG_PRLL *((volatile uint16_t*)(0x40025200UL)) +#define FM4_BT4_PPG_PRLL *((volatile uint16_t*)(0x40025200UL)) +#define FM_BT4_PWM_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM4_BT4_PWM_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM_BT4_RT_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM4_BT4_RT_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM_BT4_PPG_PRLH *((volatile uint16_t*)(0x40025204UL)) +#define FM4_BT4_PPG_PRLH *((volatile uint16_t*)(0x40025204UL)) +#define FM_BT4_PWC_DTBF *((volatile uint16_t*)(0x40025204UL)) +#define FM4_BT4_PWC_DTBF *((volatile uint16_t*)(0x40025204UL)) +#define FM_BT4_PWM_PDUT *((volatile uint16_t*)(0x40025204UL)) +#define FM4_BT4_PWM_PDUT *((volatile uint16_t*)(0x40025204UL)) +#define FM_BT4_PPG_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM4_BT4_PPG_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM_BT4_PWM_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM4_BT4_PWM_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM_BT4_RT_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM4_BT4_RT_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM_BT4_PPG_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_PPG_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_PWC_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_PWC_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_PWM_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_PWM_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_RT_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_RT_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_PPG_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_PPG_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_PWC_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_PWC_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_PWM_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_PWM_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_RT_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_RT_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_PPG_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_PPG_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM_BT4_PWC_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_PWC_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM_BT4_PWM_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_PWM_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM_BT4_RT_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_RT_TMCR2 *((volatile uint8_t*)(0x40025211UL)) + +/******************************************************************************* +* BT Registers BT5 +* Register Definition +*******************************************************************************/ +#define FM_BT5_PPG_PRLL *((volatile uint16_t*)(0x40025240UL)) +#define FM4_BT5_PPG_PRLL *((volatile uint16_t*)(0x40025240UL)) +#define FM_BT5_PWM_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM4_BT5_PWM_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM_BT5_RT_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM4_BT5_RT_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM_BT5_PPG_PRLH *((volatile uint16_t*)(0x40025244UL)) +#define FM4_BT5_PPG_PRLH *((volatile uint16_t*)(0x40025244UL)) +#define FM_BT5_PWC_DTBF *((volatile uint16_t*)(0x40025244UL)) +#define FM4_BT5_PWC_DTBF *((volatile uint16_t*)(0x40025244UL)) +#define FM_BT5_PWM_PDUT *((volatile uint16_t*)(0x40025244UL)) +#define FM4_BT5_PWM_PDUT *((volatile uint16_t*)(0x40025244UL)) +#define FM_BT5_PPG_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM4_BT5_PPG_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM_BT5_PWM_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM4_BT5_PWM_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM_BT5_RT_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM4_BT5_RT_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM_BT5_PPG_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_PPG_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_PWC_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_PWC_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_PWM_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_PWM_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_RT_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_RT_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_PPG_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_PPG_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_PWC_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_PWC_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_PWM_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_PWM_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_RT_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_RT_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_PPG_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_PPG_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM_BT5_PWC_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_PWC_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM_BT5_PWM_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_PWM_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM_BT5_RT_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_RT_TMCR2 *((volatile uint8_t*)(0x40025251UL)) + +/******************************************************************************* +* BT Registers BT6 +* Register Definition +*******************************************************************************/ +#define FM_BT6_PPG_PRLL *((volatile uint16_t*)(0x40025280UL)) +#define FM4_BT6_PPG_PRLL *((volatile uint16_t*)(0x40025280UL)) +#define FM_BT6_PWM_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM4_BT6_PWM_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM_BT6_RT_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM4_BT6_RT_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM_BT6_PPG_PRLH *((volatile uint16_t*)(0x40025284UL)) +#define FM4_BT6_PPG_PRLH *((volatile uint16_t*)(0x40025284UL)) +#define FM_BT6_PWC_DTBF *((volatile uint16_t*)(0x40025284UL)) +#define FM4_BT6_PWC_DTBF *((volatile uint16_t*)(0x40025284UL)) +#define FM_BT6_PWM_PDUT *((volatile uint16_t*)(0x40025284UL)) +#define FM4_BT6_PWM_PDUT *((volatile uint16_t*)(0x40025284UL)) +#define FM_BT6_PPG_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM4_BT6_PPG_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM_BT6_PWM_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM4_BT6_PWM_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM_BT6_RT_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM4_BT6_RT_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM_BT6_PPG_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_PPG_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_PWC_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_PWC_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_PWM_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_PWM_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_RT_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_RT_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_PPG_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_PPG_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_PWC_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_PWC_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_PWM_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_PWM_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_RT_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_RT_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_PPG_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_PPG_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM_BT6_PWC_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_PWC_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM_BT6_PWM_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_PWM_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM_BT6_RT_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_RT_TMCR2 *((volatile uint8_t*)(0x40025291UL)) + +/******************************************************************************* +* BT Registers BT7 +* Register Definition +*******************************************************************************/ +#define FM_BT7_PPG_PRLL *((volatile uint16_t*)(0x400252C0UL)) +#define FM4_BT7_PPG_PRLL *((volatile uint16_t*)(0x400252C0UL)) +#define FM_BT7_PWM_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM4_BT7_PWM_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM_BT7_RT_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM4_BT7_RT_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM_BT7_PPG_PRLH *((volatile uint16_t*)(0x400252C4UL)) +#define FM4_BT7_PPG_PRLH *((volatile uint16_t*)(0x400252C4UL)) +#define FM_BT7_PWC_DTBF *((volatile uint16_t*)(0x400252C4UL)) +#define FM4_BT7_PWC_DTBF *((volatile uint16_t*)(0x400252C4UL)) +#define FM_BT7_PWM_PDUT *((volatile uint16_t*)(0x400252C4UL)) +#define FM4_BT7_PWM_PDUT *((volatile uint16_t*)(0x400252C4UL)) +#define FM_BT7_PPG_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM4_BT7_PPG_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM_BT7_PWM_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM4_BT7_PWM_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM_BT7_RT_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM4_BT7_RT_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM_BT7_PPG_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_PPG_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_PWC_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_PWC_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_PWM_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_PWM_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_RT_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_RT_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_PPG_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_PPG_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_PWC_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_PWC_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_PWM_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_PWM_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_RT_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_RT_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_PPG_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_PPG_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM_BT7_PWC_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_PWC_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM_BT7_PWM_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_PWM_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM_BT7_RT_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_RT_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) + +/******************************************************************************* +* BT Registers BT8 +* Register Definition +*******************************************************************************/ +#define FM_BT8_PPG_PRLL *((volatile uint16_t*)(0x40025400UL)) +#define FM4_BT8_PPG_PRLL *((volatile uint16_t*)(0x40025400UL)) +#define FM_BT8_PWM_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM4_BT8_PWM_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM_BT8_RT_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM4_BT8_RT_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM_BT8_PPG_PRLH *((volatile uint16_t*)(0x40025404UL)) +#define FM4_BT8_PPG_PRLH *((volatile uint16_t*)(0x40025404UL)) +#define FM_BT8_PWC_DTBF *((volatile uint16_t*)(0x40025404UL)) +#define FM4_BT8_PWC_DTBF *((volatile uint16_t*)(0x40025404UL)) +#define FM_BT8_PWM_PDUT *((volatile uint16_t*)(0x40025404UL)) +#define FM4_BT8_PWM_PDUT *((volatile uint16_t*)(0x40025404UL)) +#define FM_BT8_PPG_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM4_BT8_PPG_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM_BT8_PWM_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM4_BT8_PWM_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM_BT8_RT_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM4_BT8_RT_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM_BT8_PPG_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_PPG_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_PWC_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_PWC_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_PWM_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_PWM_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_RT_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_RT_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_PPG_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_PPG_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_PWC_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_PWC_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_PWM_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_PWM_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_RT_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_RT_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_PPG_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_PPG_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM_BT8_PWC_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_PWC_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM_BT8_PWM_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_PWM_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM_BT8_RT_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_RT_TMCR2 *((volatile uint8_t*)(0x40025411UL)) + +/******************************************************************************* +* BT Registers BT9 +* Register Definition +*******************************************************************************/ +#define FM_BT9_PPG_PRLL *((volatile uint16_t*)(0x40025440UL)) +#define FM4_BT9_PPG_PRLL *((volatile uint16_t*)(0x40025440UL)) +#define FM_BT9_PWM_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM4_BT9_PWM_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM_BT9_RT_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM4_BT9_RT_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM_BT9_PPG_PRLH *((volatile uint16_t*)(0x40025444UL)) +#define FM4_BT9_PPG_PRLH *((volatile uint16_t*)(0x40025444UL)) +#define FM_BT9_PWC_DTBF *((volatile uint16_t*)(0x40025444UL)) +#define FM4_BT9_PWC_DTBF *((volatile uint16_t*)(0x40025444UL)) +#define FM_BT9_PWM_PDUT *((volatile uint16_t*)(0x40025444UL)) +#define FM4_BT9_PWM_PDUT *((volatile uint16_t*)(0x40025444UL)) +#define FM_BT9_PPG_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM4_BT9_PPG_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM_BT9_PWM_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM4_BT9_PWM_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM_BT9_RT_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM4_BT9_RT_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM_BT9_PPG_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_PPG_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_PWC_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_PWC_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_PWM_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_PWM_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_RT_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_RT_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_PPG_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_PPG_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_PWC_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_PWC_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_PWM_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_PWM_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_RT_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_RT_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_PPG_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_PPG_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM_BT9_PWC_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_PWC_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM_BT9_PWM_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_PWM_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM_BT9_RT_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_RT_TMCR2 *((volatile uint8_t*)(0x40025451UL)) + +/******************************************************************************* +* BTIOSEL03 Registers BTIOSEL03 +* Register Definition +*******************************************************************************/ +#define FM_BTIOSEL03_BTSEL0123 *((volatile uint8_t*)(0x40025101UL)) +#define FM4_BTIOSEL03_BTSEL0123 *((volatile uint8_t*)(0x40025101UL)) + +/******************************************************************************* +* BTIOSEL47 Registers BTIOSEL47 +* Register Definition +*******************************************************************************/ +#define FM_BTIOSEL47_BTSEL4567 *((volatile uint8_t*)(0x40025301UL)) +#define FM4_BTIOSEL47_BTSEL4567 *((volatile uint8_t*)(0x40025301UL)) + +/******************************************************************************* +* BTIOSEL8B Registers BTIOSEL8B +* Register Definition +*******************************************************************************/ +#define FM_BTIOSEL8B_BTSEL89AB *((volatile uint8_t*)(0x40025501UL)) +#define FM4_BTIOSEL8B_BTSEL89AB *((volatile uint8_t*)(0x40025501UL)) + +/******************************************************************************* +* BTIOSELCF Registers BTIOSELCF +* Register Definition +*******************************************************************************/ +#define FM_BTIOSELCF_BTSELCDEF *((volatile uint8_t*)(0x40025701UL)) +#define FM4_BTIOSELCF_BTSELCDEF *((volatile uint8_t*)(0x40025701UL)) + +/******************************************************************************* +* CAN Registers CAN0 +* Register Definition +*******************************************************************************/ +#define FM_CAN0_CTRLR *((volatile uint16_t*)(0x40062000UL)) +#define FM4_CAN0_CTRLR *((volatile uint16_t*)(0x40062000UL)) +#define FM_CAN0_STATR *((volatile uint16_t*)(0x40062002UL)) +#define FM4_CAN0_STATR *((volatile uint16_t*)(0x40062002UL)) +#define FM_CAN0_ERRCNT *((volatile uint16_t*)(0x40062004UL)) +#define FM4_CAN0_ERRCNT *((volatile uint16_t*)(0x40062004UL)) +#define FM_CAN0_BTR *((volatile uint16_t*)(0x40062006UL)) +#define FM4_CAN0_BTR *((volatile uint16_t*)(0x40062006UL)) +#define FM_CAN0_INTR *((volatile uint16_t*)(0x40062008UL)) +#define FM4_CAN0_INTR *((volatile uint16_t*)(0x40062008UL)) +#define FM_CAN0_TESTR *((volatile uint16_t*)(0x4006200AUL)) +#define FM4_CAN0_TESTR *((volatile uint16_t*)(0x4006200AUL)) +#define FM_CAN0_BRPER *((volatile uint16_t*)(0x4006200CUL)) +#define FM4_CAN0_BRPER *((volatile uint16_t*)(0x4006200CUL)) +#define FM_CAN0_IF1CREQ *((volatile uint16_t*)(0x40062010UL)) +#define FM4_CAN0_IF1CREQ *((volatile uint16_t*)(0x40062010UL)) +#define FM_CAN0_IF1CMSK *((volatile uint16_t*)(0x40062012UL)) +#define FM4_CAN0_IF1CMSK *((volatile uint16_t*)(0x40062012UL)) +#define FM_CAN0_IF1MSK *((volatile uint32_t*)(0x40062014UL)) +#define FM4_CAN0_IF1MSK *((volatile uint32_t*)(0x40062014UL)) +#define FM_CAN0_IF1ARB *((volatile uint32_t*)(0x40062018UL)) +#define FM4_CAN0_IF1ARB *((volatile uint32_t*)(0x40062018UL)) +#define FM_CAN0_IF1MCTR *((volatile uint16_t*)(0x4006201CUL)) +#define FM4_CAN0_IF1MCTR *((volatile uint16_t*)(0x4006201CUL)) +#define FM_CAN0_IF1DTA_L *((volatile uint32_t*)(0x40062020UL)) +#define FM4_CAN0_IF1DTA_L *((volatile uint32_t*)(0x40062020UL)) +#define FM_CAN0_IF1DTB_L *((volatile uint32_t*)(0x40062024UL)) +#define FM4_CAN0_IF1DTB_L *((volatile uint32_t*)(0x40062024UL)) +#define FM_CAN0_IF1DTA_B *((volatile uint32_t*)(0x40062030UL)) +#define FM4_CAN0_IF1DTA_B *((volatile uint32_t*)(0x40062030UL)) +#define FM_CAN0_IF1DTB_B *((volatile uint32_t*)(0x40062034UL)) +#define FM4_CAN0_IF1DTB_B *((volatile uint32_t*)(0x40062034UL)) +#define FM_CAN0_IF2CREQ *((volatile uint16_t*)(0x40062040UL)) +#define FM4_CAN0_IF2CREQ *((volatile uint16_t*)(0x40062040UL)) +#define FM_CAN0_IF2CMSK *((volatile uint16_t*)(0x40062042UL)) +#define FM4_CAN0_IF2CMSK *((volatile uint16_t*)(0x40062042UL)) +#define FM_CAN0_IF2MSK *((volatile uint32_t*)(0x40062044UL)) +#define FM4_CAN0_IF2MSK *((volatile uint32_t*)(0x40062044UL)) +#define FM_CAN0_IF2ARB *((volatile uint32_t*)(0x40062048UL)) +#define FM4_CAN0_IF2ARB *((volatile uint32_t*)(0x40062048UL)) +#define FM_CAN0_IF2MCTR *((volatile uint16_t*)(0x4006204CUL)) +#define FM4_CAN0_IF2MCTR *((volatile uint16_t*)(0x4006204CUL)) +#define FM_CAN0_IF2DTA_L *((volatile uint32_t*)(0x40062050UL)) +#define FM4_CAN0_IF2DTA_L *((volatile uint32_t*)(0x40062050UL)) +#define FM_CAN0_IF2DTB_L *((volatile uint32_t*)(0x40062054UL)) +#define FM4_CAN0_IF2DTB_L *((volatile uint32_t*)(0x40062054UL)) +#define FM_CAN0_IF2DTA_B *((volatile uint32_t*)(0x40062060UL)) +#define FM4_CAN0_IF2DTA_B *((volatile uint32_t*)(0x40062060UL)) +#define FM_CAN0_IF2DTB_B *((volatile uint32_t*)(0x40062064UL)) +#define FM4_CAN0_IF2DTB_B *((volatile uint32_t*)(0x40062064UL)) +#define FM_CAN0_TREQR *((volatile uint32_t*)(0x40062080UL)) +#define FM4_CAN0_TREQR *((volatile uint32_t*)(0x40062080UL)) +#define FM_CAN0_NEWDT *((volatile uint32_t*)(0x40062090UL)) +#define FM4_CAN0_NEWDT *((volatile uint32_t*)(0x40062090UL)) +#define FM_CAN0_INTPND *((volatile uint32_t*)(0x400620A0UL)) +#define FM4_CAN0_INTPND *((volatile uint32_t*)(0x400620A0UL)) +#define FM_CAN0_MSGVAL *((volatile uint32_t*)(0x400620B0UL)) +#define FM4_CAN0_MSGVAL *((volatile uint32_t*)(0x400620B0UL)) + +/******************************************************************************* +* CAN Registers CAN1 +* Register Definition +*******************************************************************************/ +#define FM_CAN1_CTRLR *((volatile uint16_t*)(0x40063000UL)) +#define FM4_CAN1_CTRLR *((volatile uint16_t*)(0x40063000UL)) +#define FM_CAN1_STATR *((volatile uint16_t*)(0x40063002UL)) +#define FM4_CAN1_STATR *((volatile uint16_t*)(0x40063002UL)) +#define FM_CAN1_ERRCNT *((volatile uint16_t*)(0x40063004UL)) +#define FM4_CAN1_ERRCNT *((volatile uint16_t*)(0x40063004UL)) +#define FM_CAN1_BTR *((volatile uint16_t*)(0x40063006UL)) +#define FM4_CAN1_BTR *((volatile uint16_t*)(0x40063006UL)) +#define FM_CAN1_INTR *((volatile uint16_t*)(0x40063008UL)) +#define FM4_CAN1_INTR *((volatile uint16_t*)(0x40063008UL)) +#define FM_CAN1_TESTR *((volatile uint16_t*)(0x4006300AUL)) +#define FM4_CAN1_TESTR *((volatile uint16_t*)(0x4006300AUL)) +#define FM_CAN1_BRPER *((volatile uint16_t*)(0x4006300CUL)) +#define FM4_CAN1_BRPER *((volatile uint16_t*)(0x4006300CUL)) +#define FM_CAN1_IF1CREQ *((volatile uint16_t*)(0x40063010UL)) +#define FM4_CAN1_IF1CREQ *((volatile uint16_t*)(0x40063010UL)) +#define FM_CAN1_IF1CMSK *((volatile uint16_t*)(0x40063012UL)) +#define FM4_CAN1_IF1CMSK *((volatile uint16_t*)(0x40063012UL)) +#define FM_CAN1_IF1MSK *((volatile uint32_t*)(0x40063014UL)) +#define FM4_CAN1_IF1MSK *((volatile uint32_t*)(0x40063014UL)) +#define FM_CAN1_IF1ARB *((volatile uint32_t*)(0x40063018UL)) +#define FM4_CAN1_IF1ARB *((volatile uint32_t*)(0x40063018UL)) +#define FM_CAN1_IF1MCTR *((volatile uint16_t*)(0x4006301CUL)) +#define FM4_CAN1_IF1MCTR *((volatile uint16_t*)(0x4006301CUL)) +#define FM_CAN1_IF1DTA_L *((volatile uint32_t*)(0x40063020UL)) +#define FM4_CAN1_IF1DTA_L *((volatile uint32_t*)(0x40063020UL)) +#define FM_CAN1_IF1DTB_L *((volatile uint32_t*)(0x40063024UL)) +#define FM4_CAN1_IF1DTB_L *((volatile uint32_t*)(0x40063024UL)) +#define FM_CAN1_IF1DTA_B *((volatile uint32_t*)(0x40063030UL)) +#define FM4_CAN1_IF1DTA_B *((volatile uint32_t*)(0x40063030UL)) +#define FM_CAN1_IF1DTB_B *((volatile uint32_t*)(0x40063034UL)) +#define FM4_CAN1_IF1DTB_B *((volatile uint32_t*)(0x40063034UL)) +#define FM_CAN1_IF2CREQ *((volatile uint16_t*)(0x40063040UL)) +#define FM4_CAN1_IF2CREQ *((volatile uint16_t*)(0x40063040UL)) +#define FM_CAN1_IF2CMSK *((volatile uint16_t*)(0x40063042UL)) +#define FM4_CAN1_IF2CMSK *((volatile uint16_t*)(0x40063042UL)) +#define FM_CAN1_IF2MSK *((volatile uint32_t*)(0x40063044UL)) +#define FM4_CAN1_IF2MSK *((volatile uint32_t*)(0x40063044UL)) +#define FM_CAN1_IF2ARB *((volatile uint32_t*)(0x40063048UL)) +#define FM4_CAN1_IF2ARB *((volatile uint32_t*)(0x40063048UL)) +#define FM_CAN1_IF2MCTR *((volatile uint16_t*)(0x4006304CUL)) +#define FM4_CAN1_IF2MCTR *((volatile uint16_t*)(0x4006304CUL)) +#define FM_CAN1_IF2DTA_L *((volatile uint32_t*)(0x40063050UL)) +#define FM4_CAN1_IF2DTA_L *((volatile uint32_t*)(0x40063050UL)) +#define FM_CAN1_IF2DTB_L *((volatile uint32_t*)(0x40063054UL)) +#define FM4_CAN1_IF2DTB_L *((volatile uint32_t*)(0x40063054UL)) +#define FM_CAN1_IF2DTA_B *((volatile uint32_t*)(0x40063060UL)) +#define FM4_CAN1_IF2DTA_B *((volatile uint32_t*)(0x40063060UL)) +#define FM_CAN1_IF2DTB_B *((volatile uint32_t*)(0x40063064UL)) +#define FM4_CAN1_IF2DTB_B *((volatile uint32_t*)(0x40063064UL)) +#define FM_CAN1_TREQR *((volatile uint32_t*)(0x40063080UL)) +#define FM4_CAN1_TREQR *((volatile uint32_t*)(0x40063080UL)) +#define FM_CAN1_NEWDT *((volatile uint32_t*)(0x40063090UL)) +#define FM4_CAN1_NEWDT *((volatile uint32_t*)(0x40063090UL)) +#define FM_CAN1_INTPND *((volatile uint32_t*)(0x400630A0UL)) +#define FM4_CAN1_INTPND *((volatile uint32_t*)(0x400630A0UL)) +#define FM_CAN1_MSGVAL *((volatile uint32_t*)(0x400630B0UL)) +#define FM4_CAN1_MSGVAL *((volatile uint32_t*)(0x400630B0UL)) + +/******************************************************************************* +* CANFD Registers CANFD0 +* Register Definition +*******************************************************************************/ +#define FM_CANFD0_CREL *((volatile uint32_t*)(0x40070000UL)) +#define FM4_CANFD0_CREL *((volatile uint32_t*)(0x40070000UL)) +#define FM_CANFD0_ENDN *((volatile uint32_t*)(0x40070004UL)) +#define FM4_CANFD0_ENDN *((volatile uint32_t*)(0x40070004UL)) +#define FM_CANFD0_FBTP *((volatile uint32_t*)(0x4007000CUL)) +#define FM4_CANFD0_FBTP *((volatile uint32_t*)(0x4007000CUL)) +#define FM_CANFD0_TEST *((volatile uint32_t*)(0x40070010UL)) +#define FM4_CANFD0_TEST *((volatile uint32_t*)(0x40070010UL)) +#define FM_CANFD0_RWD *((volatile uint32_t*)(0x40070014UL)) +#define FM4_CANFD0_RWD *((volatile uint32_t*)(0x40070014UL)) +#define FM_CANFD0_CCCR *((volatile uint32_t*)(0x40070018UL)) +#define FM4_CANFD0_CCCR *((volatile uint32_t*)(0x40070018UL)) +#define FM_CANFD0_BTP *((volatile uint32_t*)(0x4007001CUL)) +#define FM4_CANFD0_BTP *((volatile uint32_t*)(0x4007001CUL)) +#define FM_CANFD0_TSCC *((volatile uint32_t*)(0x40070020UL)) +#define FM4_CANFD0_TSCC *((volatile uint32_t*)(0x40070020UL)) +#define FM_CANFD0_TSCV *((volatile uint32_t*)(0x40070024UL)) +#define FM4_CANFD0_TSCV *((volatile uint32_t*)(0x40070024UL)) +#define FM_CANFD0_TOCC *((volatile uint32_t*)(0x40070028UL)) +#define FM4_CANFD0_TOCC *((volatile uint32_t*)(0x40070028UL)) +#define FM_CANFD0_TOCV *((volatile uint32_t*)(0x4007002CUL)) +#define FM4_CANFD0_TOCV *((volatile uint32_t*)(0x4007002CUL)) +#define FM_CANFD0_ECR *((volatile uint32_t*)(0x40070040UL)) +#define FM4_CANFD0_ECR *((volatile uint32_t*)(0x40070040UL)) +#define FM_CANFD0_PSR *((volatile uint32_t*)(0x40070044UL)) +#define FM4_CANFD0_PSR *((volatile uint32_t*)(0x40070044UL)) +#define FM_CANFD0_IR *((volatile uint32_t*)(0x40070050UL)) +#define FM4_CANFD0_IR *((volatile uint32_t*)(0x40070050UL)) +#define FM_CANFD0_IE *((volatile uint32_t*)(0x40070054UL)) +#define FM4_CANFD0_IE *((volatile uint32_t*)(0x40070054UL)) +#define FM_CANFD0_ILS *((volatile uint32_t*)(0x40070058UL)) +#define FM4_CANFD0_ILS *((volatile uint32_t*)(0x40070058UL)) +#define FM_CANFD0_ILE *((volatile uint32_t*)(0x4007005CUL)) +#define FM4_CANFD0_ILE *((volatile uint32_t*)(0x4007005CUL)) +#define FM_CANFD0_GFC *((volatile uint32_t*)(0x40070080UL)) +#define FM4_CANFD0_GFC *((volatile uint32_t*)(0x40070080UL)) +#define FM_CANFD0_SIDFC *((volatile uint32_t*)(0x40070084UL)) +#define FM4_CANFD0_SIDFC *((volatile uint32_t*)(0x40070084UL)) +#define FM_CANFD0_XIDFC *((volatile uint32_t*)(0x40070088UL)) +#define FM4_CANFD0_XIDFC *((volatile uint32_t*)(0x40070088UL)) +#define FM_CANFD0_XIDAM *((volatile uint32_t*)(0x40070090UL)) +#define FM4_CANFD0_XIDAM *((volatile uint32_t*)(0x40070090UL)) +#define FM_CANFD0_HPMS *((volatile uint32_t*)(0x40070094UL)) +#define FM4_CANFD0_HPMS *((volatile uint32_t*)(0x40070094UL)) +#define FM_CANFD0_NDAT1 *((volatile uint32_t*)(0x40070098UL)) +#define FM4_CANFD0_NDAT1 *((volatile uint32_t*)(0x40070098UL)) +#define FM_CANFD0_NDAT2 *((volatile uint32_t*)(0x4007009CUL)) +#define FM4_CANFD0_NDAT2 *((volatile uint32_t*)(0x4007009CUL)) +#define FM_CANFD0_RXF0C *((volatile uint32_t*)(0x400700A0UL)) +#define FM4_CANFD0_RXF0C *((volatile uint32_t*)(0x400700A0UL)) +#define FM_CANFD0_RXF0S *((volatile uint32_t*)(0x400700A4UL)) +#define FM4_CANFD0_RXF0S *((volatile uint32_t*)(0x400700A4UL)) +#define FM_CANFD0_RXF0A *((volatile uint32_t*)(0x400700A8UL)) +#define FM4_CANFD0_RXF0A *((volatile uint32_t*)(0x400700A8UL)) +#define FM_CANFD0_RXBC *((volatile uint32_t*)(0x400700ACUL)) +#define FM4_CANFD0_RXBC *((volatile uint32_t*)(0x400700ACUL)) +#define FM_CANFD0_RXF1C *((volatile uint32_t*)(0x400700B0UL)) +#define FM4_CANFD0_RXF1C *((volatile uint32_t*)(0x400700B0UL)) +#define FM_CANFD0_RXF1S *((volatile uint32_t*)(0x400700B4UL)) +#define FM4_CANFD0_RXF1S *((volatile uint32_t*)(0x400700B4UL)) +#define FM_CANFD0_RXF1A *((volatile uint32_t*)(0x400700B8UL)) +#define FM4_CANFD0_RXF1A *((volatile uint32_t*)(0x400700B8UL)) +#define FM_CANFD0_RXESC *((volatile uint32_t*)(0x400700BCUL)) +#define FM4_CANFD0_RXESC *((volatile uint32_t*)(0x400700BCUL)) +#define FM_CANFD0_TXBC *((volatile uint32_t*)(0x400700C0UL)) +#define FM4_CANFD0_TXBC *((volatile uint32_t*)(0x400700C0UL)) +#define FM_CANFD0_TXFQS *((volatile uint32_t*)(0x400700C4UL)) +#define FM4_CANFD0_TXFQS *((volatile uint32_t*)(0x400700C4UL)) +#define FM_CANFD0_TXESC *((volatile uint32_t*)(0x400700C8UL)) +#define FM4_CANFD0_TXESC *((volatile uint32_t*)(0x400700C8UL)) +#define FM_CANFD0_TXBRP *((volatile uint32_t*)(0x400700CCUL)) +#define FM4_CANFD0_TXBRP *((volatile uint32_t*)(0x400700CCUL)) +#define FM_CANFD0_TXBAR *((volatile uint32_t*)(0x400700D0UL)) +#define FM4_CANFD0_TXBAR *((volatile uint32_t*)(0x400700D0UL)) +#define FM_CANFD0_TXBCR *((volatile uint32_t*)(0x400700D4UL)) +#define FM4_CANFD0_TXBCR *((volatile uint32_t*)(0x400700D4UL)) +#define FM_CANFD0_TXBTO *((volatile uint32_t*)(0x400700D8UL)) +#define FM4_CANFD0_TXBTO *((volatile uint32_t*)(0x400700D8UL)) +#define FM_CANFD0_TXBCF *((volatile uint32_t*)(0x400700DCUL)) +#define FM4_CANFD0_TXBCF *((volatile uint32_t*)(0x400700DCUL)) +#define FM_CANFD0_TXBTIE *((volatile uint32_t*)(0x400700E0UL)) +#define FM4_CANFD0_TXBTIE *((volatile uint32_t*)(0x400700E0UL)) +#define FM_CANFD0_TXBCIE *((volatile uint32_t*)(0x400700E4UL)) +#define FM4_CANFD0_TXBCIE *((volatile uint32_t*)(0x400700E4UL)) +#define FM_CANFD0_TXEFC *((volatile uint32_t*)(0x400700F0UL)) +#define FM4_CANFD0_TXEFC *((volatile uint32_t*)(0x400700F0UL)) +#define FM_CANFD0_TXFS *((volatile uint32_t*)(0x400700F4UL)) +#define FM4_CANFD0_TXFS *((volatile uint32_t*)(0x400700F4UL)) +#define FM_CANFD0_TXFA *((volatile uint32_t*)(0x400700F8UL)) +#define FM4_CANFD0_TXFA *((volatile uint32_t*)(0x400700F8UL)) +#define FM_CANFD0_FDECR *((volatile uint8_t*)(0x40070200UL)) +#define FM4_CANFD0_FDECR *((volatile uint8_t*)(0x40070200UL)) +#define FM_CANFD0_FDESR *((volatile uint8_t*)(0x40070201UL)) +#define FM4_CANFD0_FDESR *((volatile uint8_t*)(0x40070201UL)) +#define FM_CANFD0_FDSEAR *((volatile uint16_t*)(0x40070202UL)) +#define FM4_CANFD0_FDSEAR *((volatile uint16_t*)(0x40070202UL)) +#define FM_CANFD0_FDESCR *((volatile uint8_t*)(0x40070205UL)) +#define FM4_CANFD0_FDESCR *((volatile uint8_t*)(0x40070205UL)) +#define FM_CANFD0_FDDEAR *((volatile uint16_t*)(0x40070206UL)) +#define FM4_CANFD0_FDDEAR *((volatile uint16_t*)(0x40070206UL)) +#define FM_CANFD0_TSCNTR *((volatile uint16_t*)(0x40070210UL)) +#define FM4_CANFD0_TSCNTR *((volatile uint16_t*)(0x40070210UL)) +#define FM_CANFD0_TSMDR *((volatile uint16_t*)(0x40070212UL)) +#define FM4_CANFD0_TSMDR *((volatile uint16_t*)(0x40070212UL)) +#define FM_CANFD0_TSDIVR *((volatile uint32_t*)(0x40070214UL)) +#define FM4_CANFD0_TSDIVR *((volatile uint32_t*)(0x40070214UL)) +#define FM_CANFD0_TSCDTR *((volatile uint16_t*)(0x40070218UL)) +#define FM4_CANFD0_TSCDTR *((volatile uint16_t*)(0x40070218UL)) +#define FM_CANFD0_TSCPCLR *((volatile uint16_t*)(0x4007021AUL)) +#define FM4_CANFD0_TSCPCLR *((volatile uint16_t*)(0x4007021AUL)) + +/******************************************************************************* +* CANPRES Registers CANPRES +* Register Definition +*******************************************************************************/ +#define FM_CANPRES_CANPRE *((volatile uint8_t*)(0x40037000UL)) +#define FM4_CANPRES_CANPRE *((volatile uint8_t*)(0x40037000UL)) + +/******************************************************************************* +* CLK_GATING Registers CLK_GATING +* Register Definition +*******************************************************************************/ +#define FM_CLK_GATING_CKEN0 *((volatile uint32_t*)(0x4003C100UL)) +#define FM4_CLK_GATING_CKEN0 *((volatile uint32_t*)(0x4003C100UL)) +#define FM_CLK_GATING_MRST0 *((volatile uint32_t*)(0x4003C104UL)) +#define FM4_CLK_GATING_MRST0 *((volatile uint32_t*)(0x4003C104UL)) +#define FM_CLK_GATING_CKEN1 *((volatile uint32_t*)(0x4003C110UL)) +#define FM4_CLK_GATING_CKEN1 *((volatile uint32_t*)(0x4003C110UL)) +#define FM_CLK_GATING_MRST1 *((volatile uint32_t*)(0x4003C114UL)) +#define FM4_CLK_GATING_MRST1 *((volatile uint32_t*)(0x4003C114UL)) +#define FM_CLK_GATING_CKEN2 *((volatile uint32_t*)(0x4003C120UL)) +#define FM4_CLK_GATING_CKEN2 *((volatile uint32_t*)(0x4003C120UL)) +#define FM_CLK_GATING_MRST2 *((volatile uint32_t*)(0x4003C124UL)) +#define FM4_CLK_GATING_MRST2 *((volatile uint32_t*)(0x4003C124UL)) + +/******************************************************************************* +* CRC Registers CRC +* Register Definition +*******************************************************************************/ +#define FM_CRC_CRCCR *((volatile uint8_t*)(0x40039000UL)) +#define FM4_CRC_CRCCR *((volatile uint8_t*)(0x40039000UL)) +#define FM_CRC_CRCINIT *((volatile uint32_t*)(0x40039004UL)) +#define FM4_CRC_CRCINIT *((volatile uint32_t*)(0x40039004UL)) +#define FM_CRC_CRCIN *((volatile uint32_t*)(0x40039008UL)) +#define FM4_CRC_CRCIN *((volatile uint32_t*)(0x40039008UL)) +#define FM_CRC_CRCR *((volatile uint32_t*)(0x4003900CUL)) +#define FM4_CRC_CRCR *((volatile uint32_t*)(0x4003900CUL)) + +/******************************************************************************* +* CRG Registers CRG +* Register Definition +*******************************************************************************/ +#define FM_CRG_SCM_CTL *((volatile uint32_t*)(0x40010000UL)) +#define FM4_CRG_SCM_CTL *((volatile uint32_t*)(0x40010000UL)) +#define FM_CRG_SCM_STR *((volatile uint32_t*)(0x40010004UL)) +#define FM4_CRG_SCM_STR *((volatile uint32_t*)(0x40010004UL)) +#define FM_CRG_STB_CTL *((volatile uint32_t*)(0x40010008UL)) +#define FM4_CRG_STB_CTL *((volatile uint32_t*)(0x40010008UL)) +#define FM_CRG_RST_STR *((volatile uint32_t*)(0x4001000CUL)) +#define FM4_CRG_RST_STR *((volatile uint32_t*)(0x4001000CUL)) +#define FM_CRG_BSC_PSR *((volatile uint32_t*)(0x40010010UL)) +#define FM4_CRG_BSC_PSR *((volatile uint32_t*)(0x40010010UL)) +#define FM_CRG_APBC0_PSR *((volatile uint32_t*)(0x40010014UL)) +#define FM4_CRG_APBC0_PSR *((volatile uint32_t*)(0x40010014UL)) +#define FM_CRG_APBC1_PSR *((volatile uint32_t*)(0x40010018UL)) +#define FM4_CRG_APBC1_PSR *((volatile uint32_t*)(0x40010018UL)) +#define FM_CRG_APBC2_PSR *((volatile uint32_t*)(0x4001001CUL)) +#define FM4_CRG_APBC2_PSR *((volatile uint32_t*)(0x4001001CUL)) +#define FM_CRG_SWC_PSR *((volatile uint32_t*)(0x40010020UL)) +#define FM4_CRG_SWC_PSR *((volatile uint32_t*)(0x40010020UL)) +#define FM_CRG_TTC_PSR *((volatile uint32_t*)(0x40010028UL)) +#define FM4_CRG_TTC_PSR *((volatile uint32_t*)(0x40010028UL)) +#define FM_CRG_CSW_TMR *((volatile uint32_t*)(0x40010030UL)) +#define FM4_CRG_CSW_TMR *((volatile uint32_t*)(0x40010030UL)) +#define FM_CRG_PSW_TMR *((volatile uint32_t*)(0x40010034UL)) +#define FM4_CRG_PSW_TMR *((volatile uint32_t*)(0x40010034UL)) +#define FM_CRG_PLL_CTL1 *((volatile uint32_t*)(0x40010038UL)) +#define FM4_CRG_PLL_CTL1 *((volatile uint32_t*)(0x40010038UL)) +#define FM_CRG_PLL_CTL2 *((volatile uint32_t*)(0x4001003CUL)) +#define FM4_CRG_PLL_CTL2 *((volatile uint32_t*)(0x4001003CUL)) +#define FM_CRG_CSV_CTL *((volatile uint32_t*)(0x40010040UL)) +#define FM4_CRG_CSV_CTL *((volatile uint32_t*)(0x40010040UL)) +#define FM_CRG_CSV_STR *((volatile uint32_t*)(0x40010044UL)) +#define FM4_CRG_CSV_STR *((volatile uint32_t*)(0x40010044UL)) +#define FM_CRG_FCSWH_CTL *((volatile uint32_t*)(0x40010048UL)) +#define FM4_CRG_FCSWH_CTL *((volatile uint32_t*)(0x40010048UL)) +#define FM_CRG_FCSWL_CTL *((volatile uint32_t*)(0x4001004CUL)) +#define FM4_CRG_FCSWL_CTL *((volatile uint32_t*)(0x4001004CUL)) +#define FM_CRG_FCSWD_CTL *((volatile uint32_t*)(0x40010050UL)) +#define FM4_CRG_FCSWD_CTL *((volatile uint32_t*)(0x40010050UL)) +#define FM_CRG_DBWDT_CTL *((volatile uint32_t*)(0x40010054UL)) +#define FM4_CRG_DBWDT_CTL *((volatile uint32_t*)(0x40010054UL)) +#define FM_CRG_INT_ENR *((volatile uint32_t*)(0x40010060UL)) +#define FM4_CRG_INT_ENR *((volatile uint32_t*)(0x40010060UL)) +#define FM_CRG_INT_STR *((volatile uint32_t*)(0x40010064UL)) +#define FM4_CRG_INT_STR *((volatile uint32_t*)(0x40010064UL)) +#define FM_CRG_INT_CLR *((volatile uint32_t*)(0x40010068UL)) +#define FM4_CRG_INT_CLR *((volatile uint32_t*)(0x40010068UL)) +#define FM_CRG_PLLCG_CTL *((volatile uint32_t*)(0x40010074UL)) +#define FM4_CRG_PLLCG_CTL *((volatile uint32_t*)(0x40010074UL)) + +/******************************************************************************* +* CRTRIM Registers CRTRIM +* Register Definition +*******************************************************************************/ +#define FM_CRTRIM_MCR_PSR *((volatile uint8_t*)(0x4002E000UL)) +#define FM4_CRTRIM_MCR_PSR *((volatile uint8_t*)(0x4002E000UL)) +#define FM_CRTRIM_MCR_FTRM *((volatile uint32_t*)(0x4002E004UL)) +#define FM4_CRTRIM_MCR_FTRM *((volatile uint32_t*)(0x4002E004UL)) +#define FM_CRTRIM_MCR_TTRM *((volatile uint32_t*)(0x4002E008UL)) +#define FM4_CRTRIM_MCR_TTRM *((volatile uint32_t*)(0x4002E008UL)) +#define FM_CRTRIM_MCR_RLR *((volatile uint32_t*)(0x4002E00CUL)) +#define FM4_CRTRIM_MCR_RLR *((volatile uint32_t*)(0x4002E00CUL)) + +/******************************************************************************* +* DAC Registers DAC0 +* Register Definition +*******************************************************************************/ +#define FM_DAC0_DACR *((volatile uint8_t*)(0x40033000UL)) +#define FM4_DAC0_DACR *((volatile uint8_t*)(0x40033000UL)) +#define FM_DAC0_DADR *((volatile uint16_t*)(0x40033004UL)) +#define FM4_DAC0_DADR *((volatile uint16_t*)(0x40033004UL)) + +/******************************************************************************* +* DAC Registers DAC1 +* Register Definition +*******************************************************************************/ +#define FM_DAC1_DACR *((volatile uint8_t*)(0x40033008UL)) +#define FM4_DAC1_DACR *((volatile uint8_t*)(0x40033008UL)) +#define FM_DAC1_DADR *((volatile uint16_t*)(0x4003300CUL)) +#define FM4_DAC1_DADR *((volatile uint16_t*)(0x4003300CUL)) + +/******************************************************************************* +* DMAC Registers DMAC +* Register Definition +*******************************************************************************/ +#define FM_DMAC_DMACR *((volatile uint32_t*)(0x40060000UL)) +#define FM4_DMAC_DMACR *((volatile uint32_t*)(0x40060000UL)) +#define FM_DMAC_DMACA0 *((volatile uint32_t*)(0x40060010UL)) +#define FM4_DMAC_DMACA0 *((volatile uint32_t*)(0x40060010UL)) +#define FM_DMAC_DMACB0 *((volatile uint32_t*)(0x40060014UL)) +#define FM4_DMAC_DMACB0 *((volatile uint32_t*)(0x40060014UL)) +#define FM_DMAC_DMACSA0 *((volatile uint32_t*)(0x40060018UL)) +#define FM4_DMAC_DMACSA0 *((volatile uint32_t*)(0x40060018UL)) +#define FM_DMAC_DMACDA0 *((volatile uint32_t*)(0x4006001CUL)) +#define FM4_DMAC_DMACDA0 *((volatile uint32_t*)(0x4006001CUL)) +#define FM_DMAC_DMACA1 *((volatile uint32_t*)(0x40060020UL)) +#define FM4_DMAC_DMACA1 *((volatile uint32_t*)(0x40060020UL)) +#define FM_DMAC_DMACB1 *((volatile uint32_t*)(0x40060024UL)) +#define FM4_DMAC_DMACB1 *((volatile uint32_t*)(0x40060024UL)) +#define FM_DMAC_DMACSA1 *((volatile uint32_t*)(0x40060028UL)) +#define FM4_DMAC_DMACSA1 *((volatile uint32_t*)(0x40060028UL)) +#define FM_DMAC_DMACDA1 *((volatile uint32_t*)(0x4006002CUL)) +#define FM4_DMAC_DMACDA1 *((volatile uint32_t*)(0x4006002CUL)) +#define FM_DMAC_DMACA2 *((volatile uint32_t*)(0x40060030UL)) +#define FM4_DMAC_DMACA2 *((volatile uint32_t*)(0x40060030UL)) +#define FM_DMAC_DMACB2 *((volatile uint32_t*)(0x40060034UL)) +#define FM4_DMAC_DMACB2 *((volatile uint32_t*)(0x40060034UL)) +#define FM_DMAC_DMACSA2 *((volatile uint32_t*)(0x40060038UL)) +#define FM4_DMAC_DMACSA2 *((volatile uint32_t*)(0x40060038UL)) +#define FM_DMAC_DMACDA2 *((volatile uint32_t*)(0x4006003CUL)) +#define FM4_DMAC_DMACDA2 *((volatile uint32_t*)(0x4006003CUL)) +#define FM_DMAC_DMACA3 *((volatile uint32_t*)(0x40060040UL)) +#define FM4_DMAC_DMACA3 *((volatile uint32_t*)(0x40060040UL)) +#define FM_DMAC_DMACB3 *((volatile uint32_t*)(0x40060044UL)) +#define FM4_DMAC_DMACB3 *((volatile uint32_t*)(0x40060044UL)) +#define FM_DMAC_DMACSA3 *((volatile uint32_t*)(0x40060048UL)) +#define FM4_DMAC_DMACSA3 *((volatile uint32_t*)(0x40060048UL)) +#define FM_DMAC_DMACDA3 *((volatile uint32_t*)(0x4006004CUL)) +#define FM4_DMAC_DMACDA3 *((volatile uint32_t*)(0x4006004CUL)) +#define FM_DMAC_DMACA4 *((volatile uint32_t*)(0x40060050UL)) +#define FM4_DMAC_DMACA4 *((volatile uint32_t*)(0x40060050UL)) +#define FM_DMAC_DMACB4 *((volatile uint32_t*)(0x40060054UL)) +#define FM4_DMAC_DMACB4 *((volatile uint32_t*)(0x40060054UL)) +#define FM_DMAC_DMACSA4 *((volatile uint32_t*)(0x40060058UL)) +#define FM4_DMAC_DMACSA4 *((volatile uint32_t*)(0x40060058UL)) +#define FM_DMAC_DMACDA4 *((volatile uint32_t*)(0x4006005CUL)) +#define FM4_DMAC_DMACDA4 *((volatile uint32_t*)(0x4006005CUL)) +#define FM_DMAC_DMACA5 *((volatile uint32_t*)(0x40060060UL)) +#define FM4_DMAC_DMACA5 *((volatile uint32_t*)(0x40060060UL)) +#define FM_DMAC_DMACB5 *((volatile uint32_t*)(0x40060064UL)) +#define FM4_DMAC_DMACB5 *((volatile uint32_t*)(0x40060064UL)) +#define FM_DMAC_DMACSA5 *((volatile uint32_t*)(0x40060068UL)) +#define FM4_DMAC_DMACSA5 *((volatile uint32_t*)(0x40060068UL)) +#define FM_DMAC_DMACDA5 *((volatile uint32_t*)(0x4006006CUL)) +#define FM4_DMAC_DMACDA5 *((volatile uint32_t*)(0x4006006CUL)) +#define FM_DMAC_DMACA6 *((volatile uint32_t*)(0x40060070UL)) +#define FM4_DMAC_DMACA6 *((volatile uint32_t*)(0x40060070UL)) +#define FM_DMAC_DMACB6 *((volatile uint32_t*)(0x40060074UL)) +#define FM4_DMAC_DMACB6 *((volatile uint32_t*)(0x40060074UL)) +#define FM_DMAC_DMACSA6 *((volatile uint32_t*)(0x40060078UL)) +#define FM4_DMAC_DMACSA6 *((volatile uint32_t*)(0x40060078UL)) +#define FM_DMAC_DMACDA6 *((volatile uint32_t*)(0x4006007CUL)) +#define FM4_DMAC_DMACDA6 *((volatile uint32_t*)(0x4006007CUL)) +#define FM_DMAC_DMACA7 *((volatile uint32_t*)(0x40060080UL)) +#define FM4_DMAC_DMACA7 *((volatile uint32_t*)(0x40060080UL)) +#define FM_DMAC_DMACB7 *((volatile uint32_t*)(0x40060084UL)) +#define FM4_DMAC_DMACB7 *((volatile uint32_t*)(0x40060084UL)) +#define FM_DMAC_DMACSA7 *((volatile uint32_t*)(0x40060088UL)) +#define FM4_DMAC_DMACSA7 *((volatile uint32_t*)(0x40060088UL)) +#define FM_DMAC_DMACDA7 *((volatile uint32_t*)(0x4006008CUL)) +#define FM4_DMAC_DMACDA7 *((volatile uint32_t*)(0x4006008CUL)) + +/******************************************************************************* +* DS Registers DS +* Register Definition +*******************************************************************************/ +#define FM_DS_RCK_CTL *((volatile uint8_t*)(0x40035104UL)) +#define FM4_DS_RCK_CTL *((volatile uint8_t*)(0x40035104UL)) +#define FM_DS_PMD_CTL *((volatile uint8_t*)(0x40035800UL)) +#define FM4_DS_PMD_CTL *((volatile uint8_t*)(0x40035800UL)) +#define FM_DS_WRFSR *((volatile uint8_t*)(0x40035804UL)) +#define FM4_DS_WRFSR *((volatile uint8_t*)(0x40035804UL)) +#define FM_DS_WIFSR *((volatile uint16_t*)(0x40035808UL)) +#define FM4_DS_WIFSR *((volatile uint16_t*)(0x40035808UL)) +#define FM_DS_WIER *((volatile uint16_t*)(0x4003580CUL)) +#define FM4_DS_WIER *((volatile uint16_t*)(0x4003580CUL)) +#define FM_DS_WILVR *((volatile uint8_t*)(0x40035810UL)) +#define FM4_DS_WILVR *((volatile uint8_t*)(0x40035810UL)) +#define FM_DS_DSRAMR *((volatile uint8_t*)(0x40035814UL)) +#define FM4_DS_DSRAMR *((volatile uint8_t*)(0x40035814UL)) +#define FM_DS_BUR01 *((volatile uint8_t*)(0x40035900UL)) +#define FM4_DS_BUR01 *((volatile uint8_t*)(0x40035900UL)) +#define FM_DS_BUR02 *((volatile uint8_t*)(0x40035901UL)) +#define FM4_DS_BUR02 *((volatile uint8_t*)(0x40035901UL)) +#define FM_DS_BUR03 *((volatile uint8_t*)(0x40035902UL)) +#define FM4_DS_BUR03 *((volatile uint8_t*)(0x40035902UL)) +#define FM_DS_BUR04 *((volatile uint8_t*)(0x40035903UL)) +#define FM4_DS_BUR04 *((volatile uint8_t*)(0x40035903UL)) +#define FM_DS_BUR05 *((volatile uint8_t*)(0x40035904UL)) +#define FM4_DS_BUR05 *((volatile uint8_t*)(0x40035904UL)) +#define FM_DS_BUR06 *((volatile uint8_t*)(0x40035905UL)) +#define FM4_DS_BUR06 *((volatile uint8_t*)(0x40035905UL)) +#define FM_DS_BUR07 *((volatile uint8_t*)(0x40035906UL)) +#define FM4_DS_BUR07 *((volatile uint8_t*)(0x40035906UL)) +#define FM_DS_BUR08 *((volatile uint8_t*)(0x40035907UL)) +#define FM4_DS_BUR08 *((volatile uint8_t*)(0x40035907UL)) +#define FM_DS_BUR09 *((volatile uint8_t*)(0x40035908UL)) +#define FM4_DS_BUR09 *((volatile uint8_t*)(0x40035908UL)) +#define FM_DS_BUR10 *((volatile uint8_t*)(0x40035909UL)) +#define FM4_DS_BUR10 *((volatile uint8_t*)(0x40035909UL)) +#define FM_DS_BUR11 *((volatile uint8_t*)(0x4003590AUL)) +#define FM4_DS_BUR11 *((volatile uint8_t*)(0x4003590AUL)) +#define FM_DS_BUR12 *((volatile uint8_t*)(0x4003590BUL)) +#define FM4_DS_BUR12 *((volatile uint8_t*)(0x4003590BUL)) +#define FM_DS_BUR13 *((volatile uint8_t*)(0x4003590CUL)) +#define FM4_DS_BUR13 *((volatile uint8_t*)(0x4003590CUL)) +#define FM_DS_BUR14 *((volatile uint8_t*)(0x4003590DUL)) +#define FM4_DS_BUR14 *((volatile uint8_t*)(0x4003590DUL)) +#define FM_DS_BUR15 *((volatile uint8_t*)(0x4003590EUL)) +#define FM4_DS_BUR15 *((volatile uint8_t*)(0x4003590EUL)) +#define FM_DS_BUR16 *((volatile uint8_t*)(0x4003590FUL)) +#define FM4_DS_BUR16 *((volatile uint8_t*)(0x4003590FUL)) + +/******************************************************************************* +* DSTC Registers DSTC +* Register Definition +*******************************************************************************/ +#define FM_DSTC_DESTP *((volatile uint32_t*)(0x40061000UL)) +#define FM4_DSTC_DESTP *((volatile uint32_t*)(0x40061000UL)) +#define FM_DSTC_HWDESP *((volatile uint32_t*)(0x40061004UL)) +#define FM4_DSTC_HWDESP *((volatile uint32_t*)(0x40061004UL)) +#define FM_DSTC_CMD *((volatile uint8_t*)(0x40061008UL)) +#define FM4_DSTC_CMD *((volatile uint8_t*)(0x40061008UL)) +#define FM_DSTC_CFG *((volatile uint8_t*)(0x40061009UL)) +#define FM4_DSTC_CFG *((volatile uint8_t*)(0x40061009UL)) +#define FM_DSTC_SWTR *((volatile uint16_t*)(0x4006100AUL)) +#define FM4_DSTC_SWTR *((volatile uint16_t*)(0x4006100AUL)) +#define FM_DSTC_MONERS *((volatile uint32_t*)(0x4006100CUL)) +#define FM4_DSTC_MONERS *((volatile uint32_t*)(0x4006100CUL)) +#define FM_DSTC_DREQENB0 *((volatile uint32_t*)(0x40061010UL)) +#define FM4_DSTC_DREQENB0 *((volatile uint32_t*)(0x40061010UL)) +#define FM_DSTC_DREQENB1 *((volatile uint32_t*)(0x40061014UL)) +#define FM4_DSTC_DREQENB1 *((volatile uint32_t*)(0x40061014UL)) +#define FM_DSTC_DREQENB2 *((volatile uint32_t*)(0x40061018UL)) +#define FM4_DSTC_DREQENB2 *((volatile uint32_t*)(0x40061018UL)) +#define FM_DSTC_DREQENB3 *((volatile uint32_t*)(0x4006101CUL)) +#define FM4_DSTC_DREQENB3 *((volatile uint32_t*)(0x4006101CUL)) +#define FM_DSTC_DREQENB4 *((volatile uint32_t*)(0x40061020UL)) +#define FM4_DSTC_DREQENB4 *((volatile uint32_t*)(0x40061020UL)) +#define FM_DSTC_DREQENB5 *((volatile uint32_t*)(0x40061024UL)) +#define FM4_DSTC_DREQENB5 *((volatile uint32_t*)(0x40061024UL)) +#define FM_DSTC_DREQENB6 *((volatile uint32_t*)(0x40061028UL)) +#define FM4_DSTC_DREQENB6 *((volatile uint32_t*)(0x40061028UL)) +#define FM_DSTC_DREQENB7 *((volatile uint32_t*)(0x4006102CUL)) +#define FM4_DSTC_DREQENB7 *((volatile uint32_t*)(0x4006102CUL)) +#define FM_DSTC_HWINT0 *((volatile uint32_t*)(0x40061030UL)) +#define FM4_DSTC_HWINT0 *((volatile uint32_t*)(0x40061030UL)) +#define FM_DSTC_HWINT1 *((volatile uint32_t*)(0x40061034UL)) +#define FM4_DSTC_HWINT1 *((volatile uint32_t*)(0x40061034UL)) +#define FM_DSTC_HWINT2 *((volatile uint32_t*)(0x40061038UL)) +#define FM4_DSTC_HWINT2 *((volatile uint32_t*)(0x40061038UL)) +#define FM_DSTC_HWINT3 *((volatile uint32_t*)(0x4006103CUL)) +#define FM4_DSTC_HWINT3 *((volatile uint32_t*)(0x4006103CUL)) +#define FM_DSTC_HWINT4 *((volatile uint32_t*)(0x40061040UL)) +#define FM4_DSTC_HWINT4 *((volatile uint32_t*)(0x40061040UL)) +#define FM_DSTC_HWINT5 *((volatile uint32_t*)(0x40061044UL)) +#define FM4_DSTC_HWINT5 *((volatile uint32_t*)(0x40061044UL)) +#define FM_DSTC_HWINT6 *((volatile uint32_t*)(0x40061048UL)) +#define FM4_DSTC_HWINT6 *((volatile uint32_t*)(0x40061048UL)) +#define FM_DSTC_HWINT7 *((volatile uint32_t*)(0x4006104CUL)) +#define FM4_DSTC_HWINT7 *((volatile uint32_t*)(0x4006104CUL)) +#define FM_DSTC_HWINTCLR0 *((volatile uint32_t*)(0x40061050UL)) +#define FM4_DSTC_HWINTCLR0 *((volatile uint32_t*)(0x40061050UL)) +#define FM_DSTC_HWINTCLR1 *((volatile uint32_t*)(0x40061054UL)) +#define FM4_DSTC_HWINTCLR1 *((volatile uint32_t*)(0x40061054UL)) +#define FM_DSTC_HWINTCLR2 *((volatile uint32_t*)(0x40061058UL)) +#define FM4_DSTC_HWINTCLR2 *((volatile uint32_t*)(0x40061058UL)) +#define FM_DSTC_HWINTCLR3 *((volatile uint32_t*)(0x4006105CUL)) +#define FM4_DSTC_HWINTCLR3 *((volatile uint32_t*)(0x4006105CUL)) +#define FM_DSTC_HWINTCLR4 *((volatile uint32_t*)(0x40061060UL)) +#define FM4_DSTC_HWINTCLR4 *((volatile uint32_t*)(0x40061060UL)) +#define FM_DSTC_HWINTCLR5 *((volatile uint32_t*)(0x40061064UL)) +#define FM4_DSTC_HWINTCLR5 *((volatile uint32_t*)(0x40061064UL)) +#define FM_DSTC_HWINTCLR6 *((volatile uint32_t*)(0x40061068UL)) +#define FM4_DSTC_HWINTCLR6 *((volatile uint32_t*)(0x40061068UL)) +#define FM_DSTC_HWINTCLR7 *((volatile uint32_t*)(0x4006106CUL)) +#define FM4_DSTC_HWINTCLR7 *((volatile uint32_t*)(0x4006106CUL)) +#define FM_DSTC_DQMSK0 *((volatile uint32_t*)(0x40061070UL)) +#define FM4_DSTC_DQMSK0 *((volatile uint32_t*)(0x40061070UL)) +#define FM_DSTC_DQMSK1 *((volatile uint32_t*)(0x40061074UL)) +#define FM4_DSTC_DQMSK1 *((volatile uint32_t*)(0x40061074UL)) +#define FM_DSTC_DQMSK2 *((volatile uint32_t*)(0x40061078UL)) +#define FM4_DSTC_DQMSK2 *((volatile uint32_t*)(0x40061078UL)) +#define FM_DSTC_DQMSK3 *((volatile uint32_t*)(0x4006107CUL)) +#define FM4_DSTC_DQMSK3 *((volatile uint32_t*)(0x4006107CUL)) +#define FM_DSTC_DQMSK4 *((volatile uint32_t*)(0x40061080UL)) +#define FM4_DSTC_DQMSK4 *((volatile uint32_t*)(0x40061080UL)) +#define FM_DSTC_DQMSK5 *((volatile uint32_t*)(0x40061084UL)) +#define FM4_DSTC_DQMSK5 *((volatile uint32_t*)(0x40061084UL)) +#define FM_DSTC_DQMSK6 *((volatile uint32_t*)(0x40061088UL)) +#define FM4_DSTC_DQMSK6 *((volatile uint32_t*)(0x40061088UL)) +#define FM_DSTC_DQMSK7 *((volatile uint32_t*)(0x4006108CUL)) +#define FM4_DSTC_DQMSK7 *((volatile uint32_t*)(0x4006108CUL)) +#define FM_DSTC_DQMSKCLR0 *((volatile uint32_t*)(0x40061090UL)) +#define FM4_DSTC_DQMSKCLR0 *((volatile uint32_t*)(0x40061090UL)) +#define FM_DSTC_DQMSKCLR1 *((volatile uint32_t*)(0x40061094UL)) +#define FM4_DSTC_DQMSKCLR1 *((volatile uint32_t*)(0x40061094UL)) +#define FM_DSTC_DQMSKCLR2 *((volatile uint32_t*)(0x40061098UL)) +#define FM4_DSTC_DQMSKCLR2 *((volatile uint32_t*)(0x40061098UL)) +#define FM_DSTC_DQMSKCLR3 *((volatile uint32_t*)(0x4006109CUL)) +#define FM4_DSTC_DQMSKCLR3 *((volatile uint32_t*)(0x4006109CUL)) +#define FM_DSTC_DQMSKCLR4 *((volatile uint32_t*)(0x400610A0UL)) +#define FM4_DSTC_DQMSKCLR4 *((volatile uint32_t*)(0x400610A0UL)) +#define FM_DSTC_DQMSKCLR5 *((volatile uint32_t*)(0x400610A4UL)) +#define FM4_DSTC_DQMSKCLR5 *((volatile uint32_t*)(0x400610A4UL)) +#define FM_DSTC_DQMSKCLR6 *((volatile uint32_t*)(0x400610A8UL)) +#define FM4_DSTC_DQMSKCLR6 *((volatile uint32_t*)(0x400610A8UL)) +#define FM_DSTC_DQMSKCLR7 *((volatile uint32_t*)(0x400610ACUL)) +#define FM4_DSTC_DQMSKCLR7 *((volatile uint32_t*)(0x400610ACUL)) + +/******************************************************************************* +* DT Registers DT +* Register Definition +*******************************************************************************/ +#define FM_DT_TIMER1LOAD *((volatile uint32_t*)(0x40015000UL)) +#define FM4_DT_TIMER1LOAD *((volatile uint32_t*)(0x40015000UL)) +#define FM_DT_TIMER1VALUE *((volatile uint32_t*)(0x40015004UL)) +#define FM4_DT_TIMER1VALUE *((volatile uint32_t*)(0x40015004UL)) +#define FM_DT_TIMER1CONTROL *((volatile uint32_t*)(0x40015008UL)) +#define FM4_DT_TIMER1CONTROL *((volatile uint32_t*)(0x40015008UL)) +#define FM_DT_TIMER1INTCLR *((volatile uint32_t*)(0x4001500CUL)) +#define FM4_DT_TIMER1INTCLR *((volatile uint32_t*)(0x4001500CUL)) +#define FM_DT_TIMER1RIS *((volatile uint32_t*)(0x40015010UL)) +#define FM4_DT_TIMER1RIS *((volatile uint32_t*)(0x40015010UL)) +#define FM_DT_TIMER1MIS *((volatile uint32_t*)(0x40015014UL)) +#define FM4_DT_TIMER1MIS *((volatile uint32_t*)(0x40015014UL)) +#define FM_DT_TIMER1BGLOAD *((volatile uint32_t*)(0x40015018UL)) +#define FM4_DT_TIMER1BGLOAD *((volatile uint32_t*)(0x40015018UL)) +#define FM_DT_TIMER2LOAD *((volatile uint32_t*)(0x40015020UL)) +#define FM4_DT_TIMER2LOAD *((volatile uint32_t*)(0x40015020UL)) +#define FM_DT_TIMER2VALUE *((volatile uint32_t*)(0x40015024UL)) +#define FM4_DT_TIMER2VALUE *((volatile uint32_t*)(0x40015024UL)) +#define FM_DT_TIMER2CONTROL *((volatile uint32_t*)(0x40015028UL)) +#define FM4_DT_TIMER2CONTROL *((volatile uint32_t*)(0x40015028UL)) +#define FM_DT_TIMER2INTCLR *((volatile uint32_t*)(0x4001502CUL)) +#define FM4_DT_TIMER2INTCLR *((volatile uint32_t*)(0x4001502CUL)) +#define FM_DT_TIMER2RIS *((volatile uint32_t*)(0x40015030UL)) +#define FM4_DT_TIMER2RIS *((volatile uint32_t*)(0x40015030UL)) +#define FM_DT_TIMER2MIS *((volatile uint32_t*)(0x40015034UL)) +#define FM4_DT_TIMER2MIS *((volatile uint32_t*)(0x40015034UL)) +#define FM_DT_TIMER2BGLOAD *((volatile uint32_t*)(0x40015038UL)) +#define FM4_DT_TIMER2BGLOAD *((volatile uint32_t*)(0x40015038UL)) + +/******************************************************************************* +* DUALFLASH_IF Registers DUALFLASH_IF +* Register Definition +*******************************************************************************/ +#define FM_DUALFLASH_IF_DFASZR *((volatile uint32_t*)(0x40000400UL)) +#define FM4_DUALFLASH_IF_DFASZR *((volatile uint32_t*)(0x40000400UL)) +#define FM_DUALFLASH_IF_DFRWTR *((volatile uint32_t*)(0x40000404UL)) +#define FM4_DUALFLASH_IF_DFRWTR *((volatile uint32_t*)(0x40000404UL)) +#define FM_DUALFLASH_IF_DFSTR *((volatile uint32_t*)(0x40000408UL)) +#define FM4_DUALFLASH_IF_DFSTR *((volatile uint32_t*)(0x40000408UL)) + +/******************************************************************************* +* ECC_CAPTURE Registers ECC_CAPTURE +* Register Definition +*******************************************************************************/ +#define FM_ECC_CAPTURE_FERRAD *((volatile uint32_t*)(0x40000300UL)) +#define FM4_ECC_CAPTURE_FERRAD *((volatile uint32_t*)(0x40000300UL)) + +/******************************************************************************* +* EXBUS Registers EXBUS +* Register Definition +*******************************************************************************/ +#define FM_EXBUS_MODE0 *((volatile uint32_t*)(0x4003F000UL)) +#define FM4_EXBUS_MODE0 *((volatile uint32_t*)(0x4003F000UL)) +#define FM_EXBUS_MODE1 *((volatile uint32_t*)(0x4003F004UL)) +#define FM4_EXBUS_MODE1 *((volatile uint32_t*)(0x4003F004UL)) +#define FM_EXBUS_MODE2 *((volatile uint32_t*)(0x4003F008UL)) +#define FM4_EXBUS_MODE2 *((volatile uint32_t*)(0x4003F008UL)) +#define FM_EXBUS_MODE3 *((volatile uint32_t*)(0x4003F00CUL)) +#define FM4_EXBUS_MODE3 *((volatile uint32_t*)(0x4003F00CUL)) +#define FM_EXBUS_MODE4 *((volatile uint32_t*)(0x4003F010UL)) +#define FM4_EXBUS_MODE4 *((volatile uint32_t*)(0x4003F010UL)) +#define FM_EXBUS_MODE5 *((volatile uint32_t*)(0x4003F014UL)) +#define FM4_EXBUS_MODE5 *((volatile uint32_t*)(0x4003F014UL)) +#define FM_EXBUS_MODE6 *((volatile uint32_t*)(0x4003F018UL)) +#define FM4_EXBUS_MODE6 *((volatile uint32_t*)(0x4003F018UL)) +#define FM_EXBUS_MODE7 *((volatile uint32_t*)(0x4003F01CUL)) +#define FM4_EXBUS_MODE7 *((volatile uint32_t*)(0x4003F01CUL)) +#define FM_EXBUS_TIM0 *((volatile uint32_t*)(0x4003F020UL)) +#define FM4_EXBUS_TIM0 *((volatile uint32_t*)(0x4003F020UL)) +#define FM_EXBUS_TIM1 *((volatile uint32_t*)(0x4003F024UL)) +#define FM4_EXBUS_TIM1 *((volatile uint32_t*)(0x4003F024UL)) +#define FM_EXBUS_TIM2 *((volatile uint32_t*)(0x4003F028UL)) +#define FM4_EXBUS_TIM2 *((volatile uint32_t*)(0x4003F028UL)) +#define FM_EXBUS_TIM3 *((volatile uint32_t*)(0x4003F02CUL)) +#define FM4_EXBUS_TIM3 *((volatile uint32_t*)(0x4003F02CUL)) +#define FM_EXBUS_TIM4 *((volatile uint32_t*)(0x4003F030UL)) +#define FM4_EXBUS_TIM4 *((volatile uint32_t*)(0x4003F030UL)) +#define FM_EXBUS_TIM5 *((volatile uint32_t*)(0x4003F034UL)) +#define FM4_EXBUS_TIM5 *((volatile uint32_t*)(0x4003F034UL)) +#define FM_EXBUS_TIM6 *((volatile uint32_t*)(0x4003F038UL)) +#define FM4_EXBUS_TIM6 *((volatile uint32_t*)(0x4003F038UL)) +#define FM_EXBUS_TIM7 *((volatile uint32_t*)(0x4003F03CUL)) +#define FM4_EXBUS_TIM7 *((volatile uint32_t*)(0x4003F03CUL)) +#define FM_EXBUS_AREA0 *((volatile uint32_t*)(0x4003F040UL)) +#define FM4_EXBUS_AREA0 *((volatile uint32_t*)(0x4003F040UL)) +#define FM_EXBUS_AREA1 *((volatile uint32_t*)(0x4003F044UL)) +#define FM4_EXBUS_AREA1 *((volatile uint32_t*)(0x4003F044UL)) +#define FM_EXBUS_AREA2 *((volatile uint32_t*)(0x4003F048UL)) +#define FM4_EXBUS_AREA2 *((volatile uint32_t*)(0x4003F048UL)) +#define FM_EXBUS_AREA3 *((volatile uint32_t*)(0x4003F04CUL)) +#define FM4_EXBUS_AREA3 *((volatile uint32_t*)(0x4003F04CUL)) +#define FM_EXBUS_AREA4 *((volatile uint32_t*)(0x4003F050UL)) +#define FM4_EXBUS_AREA4 *((volatile uint32_t*)(0x4003F050UL)) +#define FM_EXBUS_AREA5 *((volatile uint32_t*)(0x4003F054UL)) +#define FM4_EXBUS_AREA5 *((volatile uint32_t*)(0x4003F054UL)) +#define FM_EXBUS_AREA6 *((volatile uint32_t*)(0x4003F058UL)) +#define FM4_EXBUS_AREA6 *((volatile uint32_t*)(0x4003F058UL)) +#define FM_EXBUS_AREA7 *((volatile uint32_t*)(0x4003F05CUL)) +#define FM4_EXBUS_AREA7 *((volatile uint32_t*)(0x4003F05CUL)) +#define FM_EXBUS_ATIM0 *((volatile uint32_t*)(0x4003F060UL)) +#define FM4_EXBUS_ATIM0 *((volatile uint32_t*)(0x4003F060UL)) +#define FM_EXBUS_ATIM1 *((volatile uint32_t*)(0x4003F064UL)) +#define FM4_EXBUS_ATIM1 *((volatile uint32_t*)(0x4003F064UL)) +#define FM_EXBUS_ATIM2 *((volatile uint32_t*)(0x4003F068UL)) +#define FM4_EXBUS_ATIM2 *((volatile uint32_t*)(0x4003F068UL)) +#define FM_EXBUS_ATIM3 *((volatile uint32_t*)(0x4003F06CUL)) +#define FM4_EXBUS_ATIM3 *((volatile uint32_t*)(0x4003F06CUL)) +#define FM_EXBUS_ATIM4 *((volatile uint32_t*)(0x4003F070UL)) +#define FM4_EXBUS_ATIM4 *((volatile uint32_t*)(0x4003F070UL)) +#define FM_EXBUS_ATIM5 *((volatile uint32_t*)(0x4003F074UL)) +#define FM4_EXBUS_ATIM5 *((volatile uint32_t*)(0x4003F074UL)) +#define FM_EXBUS_ATIM6 *((volatile uint32_t*)(0x4003F078UL)) +#define FM4_EXBUS_ATIM6 *((volatile uint32_t*)(0x4003F078UL)) +#define FM_EXBUS_ATIM7 *((volatile uint32_t*)(0x4003F07CUL)) +#define FM4_EXBUS_ATIM7 *((volatile uint32_t*)(0x4003F07CUL)) +#define FM_EXBUS_SDMODE *((volatile uint32_t*)(0x4003F100UL)) +#define FM4_EXBUS_SDMODE *((volatile uint32_t*)(0x4003F100UL)) +#define FM_EXBUS_REFTIM *((volatile uint32_t*)(0x4003F104UL)) +#define FM4_EXBUS_REFTIM *((volatile uint32_t*)(0x4003F104UL)) +#define FM_EXBUS_PWRDWN *((volatile uint32_t*)(0x4003F108UL)) +#define FM4_EXBUS_PWRDWN *((volatile uint32_t*)(0x4003F108UL)) +#define FM_EXBUS_SDTIM *((volatile uint32_t*)(0x4003F10CUL)) +#define FM4_EXBUS_SDTIM *((volatile uint32_t*)(0x4003F10CUL)) +#define FM_EXBUS_SDCMD *((volatile uint32_t*)(0x4003F110UL)) +#define FM4_EXBUS_SDCMD *((volatile uint32_t*)(0x4003F110UL)) +#define FM_EXBUS_MEMCERR *((volatile uint32_t*)(0x4003F200UL)) +#define FM4_EXBUS_MEMCERR *((volatile uint32_t*)(0x4003F200UL)) +#define FM_EXBUS_DCLKR *((volatile uint32_t*)(0x4003F300UL)) +#define FM4_EXBUS_DCLKR *((volatile uint32_t*)(0x4003F300UL)) +#define FM_EXBUS_EST *((volatile uint32_t*)(0x4003F304UL)) +#define FM4_EXBUS_EST *((volatile uint32_t*)(0x4003F304UL)) +#define FM_EXBUS_WEAD *((volatile uint32_t*)(0x4003F308UL)) +#define FM4_EXBUS_WEAD *((volatile uint32_t*)(0x4003F308UL)) +#define FM_EXBUS_ESCLR *((volatile uint32_t*)(0x4003F30CUL)) +#define FM4_EXBUS_ESCLR *((volatile uint32_t*)(0x4003F30CUL)) +#define FM_EXBUS_AMODE *((volatile uint32_t*)(0x4003F310UL)) +#define FM4_EXBUS_AMODE *((volatile uint32_t*)(0x4003F310UL)) + +/******************************************************************************* +* EXTI Registers EXTI +* Register Definition +*******************************************************************************/ +#define FM_EXTI_ENIR *((volatile uint32_t*)(0x40030000UL)) +#define FM4_EXTI_ENIR *((volatile uint32_t*)(0x40030000UL)) +#define FM_EXTI_EIRR *((volatile uint32_t*)(0x40030004UL)) +#define FM4_EXTI_EIRR *((volatile uint32_t*)(0x40030004UL)) +#define FM_EXTI_EICL *((volatile uint32_t*)(0x40030008UL)) +#define FM4_EXTI_EICL *((volatile uint32_t*)(0x40030008UL)) +#define FM_EXTI_ELVR *((volatile uint32_t*)(0x4003000CUL)) +#define FM4_EXTI_ELVR *((volatile uint32_t*)(0x4003000CUL)) +#define FM_EXTI_ELVR1 *((volatile uint32_t*)(0x40030010UL)) +#define FM4_EXTI_ELVR1 *((volatile uint32_t*)(0x40030010UL)) +#define FM_EXTI_NMIRR *((volatile uint16_t*)(0x40030014UL)) +#define FM4_EXTI_NMIRR *((volatile uint16_t*)(0x40030014UL)) +#define FM_EXTI_NMICL *((volatile uint16_t*)(0x40030018UL)) +#define FM4_EXTI_NMICL *((volatile uint16_t*)(0x40030018UL)) + +/******************************************************************************* +* FLASH_IF Registers FLASH_IF +* Register Definition +*******************************************************************************/ +#define FM_FLASH_IF_FASZR *((volatile uint32_t*)(0x40000000UL)) +#define FM4_FLASH_IF_FASZR *((volatile uint32_t*)(0x40000000UL)) +#define FM_FLASH_IF_FRWTR *((volatile uint32_t*)(0x40000004UL)) +#define FM4_FLASH_IF_FRWTR *((volatile uint32_t*)(0x40000004UL)) +#define FM_FLASH_IF_FSTR *((volatile uint32_t*)(0x40000008UL)) +#define FM4_FLASH_IF_FSTR *((volatile uint32_t*)(0x40000008UL)) +#define FM_FLASH_IF_FSYNDN *((volatile uint32_t*)(0x40000010UL)) +#define FM4_FLASH_IF_FSYNDN *((volatile uint32_t*)(0x40000010UL)) +#define FM_FLASH_IF_FBFCR *((volatile uint32_t*)(0x40000014UL)) +#define FM4_FLASH_IF_FBFCR *((volatile uint32_t*)(0x40000014UL)) +#define FM_FLASH_IF_FICR *((volatile uint32_t*)(0x40000020UL)) +#define FM4_FLASH_IF_FICR *((volatile uint32_t*)(0x40000020UL)) +#define FM_FLASH_IF_FISR *((volatile uint32_t*)(0x40000024UL)) +#define FM4_FLASH_IF_FISR *((volatile uint32_t*)(0x40000024UL)) +#define FM_FLASH_IF_FICLR *((volatile uint32_t*)(0x40000028UL)) +#define FM4_FLASH_IF_FICLR *((volatile uint32_t*)(0x40000028UL)) +#define FM_FLASH_IF_DFCTRLR *((volatile uint32_t*)(0x40000030UL)) +#define FM4_FLASH_IF_DFCTRLR *((volatile uint32_t*)(0x40000030UL)) +#define FM_FLASH_IF_CRTRMM *((volatile uint32_t*)(0x40000100UL)) +#define FM4_FLASH_IF_CRTRMM *((volatile uint32_t*)(0x40000100UL)) +#define FM_FLASH_IF_FGPDM1 *((volatile uint32_t*)(0x40000110UL)) +#define FM4_FLASH_IF_FGPDM1 *((volatile uint32_t*)(0x40000110UL)) +#define FM_FLASH_IF_FGPDM2 *((volatile uint32_t*)(0x40000114UL)) +#define FM4_FLASH_IF_FGPDM2 *((volatile uint32_t*)(0x40000114UL)) +#define FM_FLASH_IF_FGPDM3 *((volatile uint32_t*)(0x40000118UL)) +#define FM4_FLASH_IF_FGPDM3 *((volatile uint32_t*)(0x40000118UL)) +#define FM_FLASH_IF_FGPDM4 *((volatile uint32_t*)(0x4000011CUL)) +#define FM4_FLASH_IF_FGPDM4 *((volatile uint32_t*)(0x4000011CUL)) + +/******************************************************************************* +* GPIO Registers GPIO +* Register Definition +*******************************************************************************/ +#define FM_GPIO_PFR0 *((volatile uint32_t*)(0x4006F000UL)) +#define FM4_GPIO_PFR0 *((volatile uint32_t*)(0x4006F000UL)) +#define FM_GPIO_PFR1 *((volatile uint32_t*)(0x4006F004UL)) +#define FM4_GPIO_PFR1 *((volatile uint32_t*)(0x4006F004UL)) +#define FM_GPIO_PFR2 *((volatile uint32_t*)(0x4006F008UL)) +#define FM4_GPIO_PFR2 *((volatile uint32_t*)(0x4006F008UL)) +#define FM_GPIO_PFR3 *((volatile uint32_t*)(0x4006F00CUL)) +#define FM4_GPIO_PFR3 *((volatile uint32_t*)(0x4006F00CUL)) +#define FM_GPIO_PFR4 *((volatile uint32_t*)(0x4006F010UL)) +#define FM4_GPIO_PFR4 *((volatile uint32_t*)(0x4006F010UL)) +#define FM_GPIO_PFR5 *((volatile uint32_t*)(0x4006F014UL)) +#define FM4_GPIO_PFR5 *((volatile uint32_t*)(0x4006F014UL)) +#define FM_GPIO_PFR6 *((volatile uint32_t*)(0x4006F018UL)) +#define FM4_GPIO_PFR6 *((volatile uint32_t*)(0x4006F018UL)) +#define FM_GPIO_PFR7 *((volatile uint32_t*)(0x4006F01CUL)) +#define FM4_GPIO_PFR7 *((volatile uint32_t*)(0x4006F01CUL)) +#define FM_GPIO_PFR8 *((volatile uint32_t*)(0x4006F020UL)) +#define FM4_GPIO_PFR8 *((volatile uint32_t*)(0x4006F020UL)) +#define FM_GPIO_PFR9 *((volatile uint32_t*)(0x4006F024UL)) +#define FM4_GPIO_PFR9 *((volatile uint32_t*)(0x4006F024UL)) +#define FM_GPIO_PFRA *((volatile uint32_t*)(0x4006F028UL)) +#define FM4_GPIO_PFRA *((volatile uint32_t*)(0x4006F028UL)) +#define FM_GPIO_PFRB *((volatile uint32_t*)(0x4006F02CUL)) +#define FM4_GPIO_PFRB *((volatile uint32_t*)(0x4006F02CUL)) +#define FM_GPIO_PFRC *((volatile uint32_t*)(0x4006F030UL)) +#define FM4_GPIO_PFRC *((volatile uint32_t*)(0x4006F030UL)) +#define FM_GPIO_PFRD *((volatile uint32_t*)(0x4006F034UL)) +#define FM4_GPIO_PFRD *((volatile uint32_t*)(0x4006F034UL)) +#define FM_GPIO_PFRE *((volatile uint32_t*)(0x4006F038UL)) +#define FM4_GPIO_PFRE *((volatile uint32_t*)(0x4006F038UL)) +#define FM_GPIO_PFRF *((volatile uint32_t*)(0x4006F03CUL)) +#define FM4_GPIO_PFRF *((volatile uint32_t*)(0x4006F03CUL)) +#define FM_GPIO_PCR0 *((volatile uint32_t*)(0x4006F100UL)) +#define FM4_GPIO_PCR0 *((volatile uint32_t*)(0x4006F100UL)) +#define FM_GPIO_PCR1 *((volatile uint32_t*)(0x4006F104UL)) +#define FM4_GPIO_PCR1 *((volatile uint32_t*)(0x4006F104UL)) +#define FM_GPIO_PCR2 *((volatile uint32_t*)(0x4006F108UL)) +#define FM4_GPIO_PCR2 *((volatile uint32_t*)(0x4006F108UL)) +#define FM_GPIO_PCR3 *((volatile uint32_t*)(0x4006F10CUL)) +#define FM4_GPIO_PCR3 *((volatile uint32_t*)(0x4006F10CUL)) +#define FM_GPIO_PCR4 *((volatile uint32_t*)(0x4006F110UL)) +#define FM4_GPIO_PCR4 *((volatile uint32_t*)(0x4006F110UL)) +#define FM_GPIO_PCR5 *((volatile uint32_t*)(0x4006F114UL)) +#define FM4_GPIO_PCR5 *((volatile uint32_t*)(0x4006F114UL)) +#define FM_GPIO_PCR6 *((volatile uint32_t*)(0x4006F118UL)) +#define FM4_GPIO_PCR6 *((volatile uint32_t*)(0x4006F118UL)) +#define FM_GPIO_PCR7 *((volatile uint32_t*)(0x4006F11CUL)) +#define FM4_GPIO_PCR7 *((volatile uint32_t*)(0x4006F11CUL)) +#define FM_GPIO_PCR9 *((volatile uint32_t*)(0x4006F124UL)) +#define FM4_GPIO_PCR9 *((volatile uint32_t*)(0x4006F124UL)) +#define FM_GPIO_PCRA *((volatile uint32_t*)(0x4006F128UL)) +#define FM4_GPIO_PCRA *((volatile uint32_t*)(0x4006F128UL)) +#define FM_GPIO_PCRB *((volatile uint32_t*)(0x4006F12CUL)) +#define FM4_GPIO_PCRB *((volatile uint32_t*)(0x4006F12CUL)) +#define FM_GPIO_PCRC *((volatile uint32_t*)(0x4006F130UL)) +#define FM4_GPIO_PCRC *((volatile uint32_t*)(0x4006F130UL)) +#define FM_GPIO_PCRD *((volatile uint32_t*)(0x4006F134UL)) +#define FM4_GPIO_PCRD *((volatile uint32_t*)(0x4006F134UL)) +#define FM_GPIO_PCRE *((volatile uint32_t*)(0x4006F138UL)) +#define FM4_GPIO_PCRE *((volatile uint32_t*)(0x4006F138UL)) +#define FM_GPIO_PCRF *((volatile uint32_t*)(0x4006F13CUL)) +#define FM4_GPIO_PCRF *((volatile uint32_t*)(0x4006F13CUL)) +#define FM_GPIO_DDR0 *((volatile uint32_t*)(0x4006F200UL)) +#define FM4_GPIO_DDR0 *((volatile uint32_t*)(0x4006F200UL)) +#define FM_GPIO_DDR1 *((volatile uint32_t*)(0x4006F204UL)) +#define FM4_GPIO_DDR1 *((volatile uint32_t*)(0x4006F204UL)) +#define FM_GPIO_DDR2 *((volatile uint32_t*)(0x4006F208UL)) +#define FM4_GPIO_DDR2 *((volatile uint32_t*)(0x4006F208UL)) +#define FM_GPIO_DDR3 *((volatile uint32_t*)(0x4006F20CUL)) +#define FM4_GPIO_DDR3 *((volatile uint32_t*)(0x4006F20CUL)) +#define FM_GPIO_DDR4 *((volatile uint32_t*)(0x4006F210UL)) +#define FM4_GPIO_DDR4 *((volatile uint32_t*)(0x4006F210UL)) +#define FM_GPIO_DDR5 *((volatile uint32_t*)(0x4006F214UL)) +#define FM4_GPIO_DDR5 *((volatile uint32_t*)(0x4006F214UL)) +#define FM_GPIO_DDR6 *((volatile uint32_t*)(0x4006F218UL)) +#define FM4_GPIO_DDR6 *((volatile uint32_t*)(0x4006F218UL)) +#define FM_GPIO_DDR7 *((volatile uint32_t*)(0x4006F21CUL)) +#define FM4_GPIO_DDR7 *((volatile uint32_t*)(0x4006F21CUL)) +#define FM_GPIO_DDR8 *((volatile uint32_t*)(0x4006F220UL)) +#define FM4_GPIO_DDR8 *((volatile uint32_t*)(0x4006F220UL)) +#define FM_GPIO_DDR9 *((volatile uint32_t*)(0x4006F224UL)) +#define FM4_GPIO_DDR9 *((volatile uint32_t*)(0x4006F224UL)) +#define FM_GPIO_DDRA *((volatile uint32_t*)(0x4006F228UL)) +#define FM4_GPIO_DDRA *((volatile uint32_t*)(0x4006F228UL)) +#define FM_GPIO_DDRB *((volatile uint32_t*)(0x4006F22CUL)) +#define FM4_GPIO_DDRB *((volatile uint32_t*)(0x4006F22CUL)) +#define FM_GPIO_DDRC *((volatile uint32_t*)(0x4006F230UL)) +#define FM4_GPIO_DDRC *((volatile uint32_t*)(0x4006F230UL)) +#define FM_GPIO_DDRD *((volatile uint32_t*)(0x4006F234UL)) +#define FM4_GPIO_DDRD *((volatile uint32_t*)(0x4006F234UL)) +#define FM_GPIO_DDRE *((volatile uint32_t*)(0x4006F238UL)) +#define FM4_GPIO_DDRE *((volatile uint32_t*)(0x4006F238UL)) +#define FM_GPIO_DDRF *((volatile uint32_t*)(0x4006F23CUL)) +#define FM4_GPIO_DDRF *((volatile uint32_t*)(0x4006F23CUL)) +#define FM_GPIO_PDIR0 *((volatile uint32_t*)(0x4006F300UL)) +#define FM4_GPIO_PDIR0 *((volatile uint32_t*)(0x4006F300UL)) +#define FM_GPIO_PDIR1 *((volatile uint32_t*)(0x4006F304UL)) +#define FM4_GPIO_PDIR1 *((volatile uint32_t*)(0x4006F304UL)) +#define FM_GPIO_PDIR2 *((volatile uint32_t*)(0x4006F308UL)) +#define FM4_GPIO_PDIR2 *((volatile uint32_t*)(0x4006F308UL)) +#define FM_GPIO_PDIR3 *((volatile uint32_t*)(0x4006F30CUL)) +#define FM4_GPIO_PDIR3 *((volatile uint32_t*)(0x4006F30CUL)) +#define FM_GPIO_PDIR4 *((volatile uint32_t*)(0x4006F310UL)) +#define FM4_GPIO_PDIR4 *((volatile uint32_t*)(0x4006F310UL)) +#define FM_GPIO_PDIR5 *((volatile uint32_t*)(0x4006F314UL)) +#define FM4_GPIO_PDIR5 *((volatile uint32_t*)(0x4006F314UL)) +#define FM_GPIO_PDIR6 *((volatile uint32_t*)(0x4006F318UL)) +#define FM4_GPIO_PDIR6 *((volatile uint32_t*)(0x4006F318UL)) +#define FM_GPIO_PDIR7 *((volatile uint32_t*)(0x4006F31CUL)) +#define FM4_GPIO_PDIR7 *((volatile uint32_t*)(0x4006F31CUL)) +#define FM_GPIO_PDIR8 *((volatile uint32_t*)(0x4006F320UL)) +#define FM4_GPIO_PDIR8 *((volatile uint32_t*)(0x4006F320UL)) +#define FM_GPIO_PDIR9 *((volatile uint32_t*)(0x4006F324UL)) +#define FM4_GPIO_PDIR9 *((volatile uint32_t*)(0x4006F324UL)) +#define FM_GPIO_PDIRA *((volatile uint32_t*)(0x4006F328UL)) +#define FM4_GPIO_PDIRA *((volatile uint32_t*)(0x4006F328UL)) +#define FM_GPIO_PDIRB *((volatile uint32_t*)(0x4006F32CUL)) +#define FM4_GPIO_PDIRB *((volatile uint32_t*)(0x4006F32CUL)) +#define FM_GPIO_PDIRC *((volatile uint32_t*)(0x4006F330UL)) +#define FM4_GPIO_PDIRC *((volatile uint32_t*)(0x4006F330UL)) +#define FM_GPIO_PDIRD *((volatile uint32_t*)(0x4006F334UL)) +#define FM4_GPIO_PDIRD *((volatile uint32_t*)(0x4006F334UL)) +#define FM_GPIO_PDIRE *((volatile uint32_t*)(0x4006F338UL)) +#define FM4_GPIO_PDIRE *((volatile uint32_t*)(0x4006F338UL)) +#define FM_GPIO_PDIRF *((volatile uint32_t*)(0x4006F33CUL)) +#define FM4_GPIO_PDIRF *((volatile uint32_t*)(0x4006F33CUL)) +#define FM_GPIO_PDOR0 *((volatile uint32_t*)(0x4006F400UL)) +#define FM4_GPIO_PDOR0 *((volatile uint32_t*)(0x4006F400UL)) +#define FM_GPIO_PDOR1 *((volatile uint32_t*)(0x4006F404UL)) +#define FM4_GPIO_PDOR1 *((volatile uint32_t*)(0x4006F404UL)) +#define FM_GPIO_PDOR2 *((volatile uint32_t*)(0x4006F408UL)) +#define FM4_GPIO_PDOR2 *((volatile uint32_t*)(0x4006F408UL)) +#define FM_GPIO_PDOR3 *((volatile uint32_t*)(0x4006F40CUL)) +#define FM4_GPIO_PDOR3 *((volatile uint32_t*)(0x4006F40CUL)) +#define FM_GPIO_PDOR4 *((volatile uint32_t*)(0x4006F410UL)) +#define FM4_GPIO_PDOR4 *((volatile uint32_t*)(0x4006F410UL)) +#define FM_GPIO_PDOR5 *((volatile uint32_t*)(0x4006F414UL)) +#define FM4_GPIO_PDOR5 *((volatile uint32_t*)(0x4006F414UL)) +#define FM_GPIO_PDOR6 *((volatile uint32_t*)(0x4006F418UL)) +#define FM4_GPIO_PDOR6 *((volatile uint32_t*)(0x4006F418UL)) +#define FM_GPIO_PDOR7 *((volatile uint32_t*)(0x4006F41CUL)) +#define FM4_GPIO_PDOR7 *((volatile uint32_t*)(0x4006F41CUL)) +#define FM_GPIO_PDOR8 *((volatile uint32_t*)(0x4006F420UL)) +#define FM4_GPIO_PDOR8 *((volatile uint32_t*)(0x4006F420UL)) +#define FM_GPIO_PDOR9 *((volatile uint32_t*)(0x4006F424UL)) +#define FM4_GPIO_PDOR9 *((volatile uint32_t*)(0x4006F424UL)) +#define FM_GPIO_PDORA *((volatile uint32_t*)(0x4006F428UL)) +#define FM4_GPIO_PDORA *((volatile uint32_t*)(0x4006F428UL)) +#define FM_GPIO_PDORB *((volatile uint32_t*)(0x4006F42CUL)) +#define FM4_GPIO_PDORB *((volatile uint32_t*)(0x4006F42CUL)) +#define FM_GPIO_PDORC *((volatile uint32_t*)(0x4006F430UL)) +#define FM4_GPIO_PDORC *((volatile uint32_t*)(0x4006F430UL)) +#define FM_GPIO_PDORD *((volatile uint32_t*)(0x4006F434UL)) +#define FM4_GPIO_PDORD *((volatile uint32_t*)(0x4006F434UL)) +#define FM_GPIO_PDORE *((volatile uint32_t*)(0x4006F438UL)) +#define FM4_GPIO_PDORE *((volatile uint32_t*)(0x4006F438UL)) +#define FM_GPIO_PDORF *((volatile uint32_t*)(0x4006F43CUL)) +#define FM4_GPIO_PDORF *((volatile uint32_t*)(0x4006F43CUL)) +#define FM_GPIO_ADE *((volatile uint32_t*)(0x4006F500UL)) +#define FM4_GPIO_ADE *((volatile uint32_t*)(0x4006F500UL)) +#define FM_GPIO_SPSR *((volatile uint32_t*)(0x4006F580UL)) +#define FM4_GPIO_SPSR *((volatile uint32_t*)(0x4006F580UL)) +#define FM_GPIO_EPFR00 *((volatile uint32_t*)(0x4006F600UL)) +#define FM4_GPIO_EPFR00 *((volatile uint32_t*)(0x4006F600UL)) +#define FM_GPIO_EPFR01 *((volatile uint32_t*)(0x4006F604UL)) +#define FM4_GPIO_EPFR01 *((volatile uint32_t*)(0x4006F604UL)) +#define FM_GPIO_EPFR02 *((volatile uint32_t*)(0x4006F608UL)) +#define FM4_GPIO_EPFR02 *((volatile uint32_t*)(0x4006F608UL)) +#define FM_GPIO_EPFR03 *((volatile uint32_t*)(0x4006F60CUL)) +#define FM4_GPIO_EPFR03 *((volatile uint32_t*)(0x4006F60CUL)) +#define FM_GPIO_EPFR04 *((volatile uint32_t*)(0x4006F610UL)) +#define FM4_GPIO_EPFR04 *((volatile uint32_t*)(0x4006F610UL)) +#define FM_GPIO_EPFR05 *((volatile uint32_t*)(0x4006F614UL)) +#define FM4_GPIO_EPFR05 *((volatile uint32_t*)(0x4006F614UL)) +#define FM_GPIO_EPFR06 *((volatile uint32_t*)(0x4006F618UL)) +#define FM4_GPIO_EPFR06 *((volatile uint32_t*)(0x4006F618UL)) +#define FM_GPIO_EPFR07 *((volatile uint32_t*)(0x4006F61CUL)) +#define FM4_GPIO_EPFR07 *((volatile uint32_t*)(0x4006F61CUL)) +#define FM_GPIO_EPFR08 *((volatile uint32_t*)(0x4006F620UL)) +#define FM4_GPIO_EPFR08 *((volatile uint32_t*)(0x4006F620UL)) +#define FM_GPIO_EPFR09 *((volatile uint32_t*)(0x4006F624UL)) +#define FM4_GPIO_EPFR09 *((volatile uint32_t*)(0x4006F624UL)) +#define FM_GPIO_EPFR10 *((volatile uint32_t*)(0x4006F628UL)) +#define FM4_GPIO_EPFR10 *((volatile uint32_t*)(0x4006F628UL)) +#define FM_GPIO_EPFR11 *((volatile uint32_t*)(0x4006F62CUL)) +#define FM4_GPIO_EPFR11 *((volatile uint32_t*)(0x4006F62CUL)) +#define FM_GPIO_EPFR12 *((volatile uint32_t*)(0x4006F630UL)) +#define FM4_GPIO_EPFR12 *((volatile uint32_t*)(0x4006F630UL)) +#define FM_GPIO_EPFR13 *((volatile uint32_t*)(0x4006F634UL)) +#define FM4_GPIO_EPFR13 *((volatile uint32_t*)(0x4006F634UL)) +#define FM_GPIO_EPFR14 *((volatile uint32_t*)(0x4006F638UL)) +#define FM4_GPIO_EPFR14 *((volatile uint32_t*)(0x4006F638UL)) +#define FM_GPIO_EPFR15 *((volatile uint32_t*)(0x4006F63CUL)) +#define FM4_GPIO_EPFR15 *((volatile uint32_t*)(0x4006F63CUL)) +#define FM_GPIO_EPFR16 *((volatile uint32_t*)(0x4006F640UL)) +#define FM4_GPIO_EPFR16 *((volatile uint32_t*)(0x4006F640UL)) +#define FM_GPIO_EPFR17 *((volatile uint32_t*)(0x4006F644UL)) +#define FM4_GPIO_EPFR17 *((volatile uint32_t*)(0x4006F644UL)) +#define FM_GPIO_EPFR18 *((volatile uint32_t*)(0x4006F648UL)) +#define FM4_GPIO_EPFR18 *((volatile uint32_t*)(0x4006F648UL)) +#define FM_GPIO_EPFR19 *((volatile uint32_t*)(0x4006F64CUL)) +#define FM4_GPIO_EPFR19 *((volatile uint32_t*)(0x4006F64CUL)) +#define FM_GPIO_EPFR20 *((volatile uint32_t*)(0x4006F650UL)) +#define FM4_GPIO_EPFR20 *((volatile uint32_t*)(0x4006F650UL)) +#define FM_GPIO_EPFR21 *((volatile uint32_t*)(0x4006F654UL)) +#define FM4_GPIO_EPFR21 *((volatile uint32_t*)(0x4006F654UL)) +#define FM_GPIO_EPFR22 *((volatile uint32_t*)(0x4006F658UL)) +#define FM4_GPIO_EPFR22 *((volatile uint32_t*)(0x4006F658UL)) +#define FM_GPIO_EPFR23 *((volatile uint32_t*)(0x4006F65CUL)) +#define FM4_GPIO_EPFR23 *((volatile uint32_t*)(0x4006F65CUL)) +#define FM_GPIO_EPFR24 *((volatile uint32_t*)(0x4006F660UL)) +#define FM4_GPIO_EPFR24 *((volatile uint32_t*)(0x4006F660UL)) +#define FM_GPIO_EPFR25 *((volatile uint32_t*)(0x4006F664UL)) +#define FM4_GPIO_EPFR25 *((volatile uint32_t*)(0x4006F664UL)) +#define FM_GPIO_EPFR26 *((volatile uint32_t*)(0x4006F668UL)) +#define FM4_GPIO_EPFR26 *((volatile uint32_t*)(0x4006F668UL)) +#define FM_GPIO_PZR0 *((volatile uint32_t*)(0x4006F700UL)) +#define FM4_GPIO_PZR0 *((volatile uint32_t*)(0x4006F700UL)) +#define FM_GPIO_PZR1 *((volatile uint32_t*)(0x4006F704UL)) +#define FM4_GPIO_PZR1 *((volatile uint32_t*)(0x4006F704UL)) +#define FM_GPIO_PZR2 *((volatile uint32_t*)(0x4006F708UL)) +#define FM4_GPIO_PZR2 *((volatile uint32_t*)(0x4006F708UL)) +#define FM_GPIO_PZR3 *((volatile uint32_t*)(0x4006F70CUL)) +#define FM4_GPIO_PZR3 *((volatile uint32_t*)(0x4006F70CUL)) +#define FM_GPIO_PZR4 *((volatile uint32_t*)(0x4006F710UL)) +#define FM4_GPIO_PZR4 *((volatile uint32_t*)(0x4006F710UL)) +#define FM_GPIO_PZR5 *((volatile uint32_t*)(0x4006F714UL)) +#define FM4_GPIO_PZR5 *((volatile uint32_t*)(0x4006F714UL)) +#define FM_GPIO_PZR6 *((volatile uint32_t*)(0x4006F718UL)) +#define FM4_GPIO_PZR6 *((volatile uint32_t*)(0x4006F718UL)) +#define FM_GPIO_PZR7 *((volatile uint32_t*)(0x4006F71CUL)) +#define FM4_GPIO_PZR7 *((volatile uint32_t*)(0x4006F71CUL)) +#define FM_GPIO_PZR8 *((volatile uint32_t*)(0x4006F720UL)) +#define FM4_GPIO_PZR8 *((volatile uint32_t*)(0x4006F720UL)) +#define FM_GPIO_PZR9 *((volatile uint32_t*)(0x4006F724UL)) +#define FM4_GPIO_PZR9 *((volatile uint32_t*)(0x4006F724UL)) +#define FM_GPIO_PZRA *((volatile uint32_t*)(0x4006F728UL)) +#define FM4_GPIO_PZRA *((volatile uint32_t*)(0x4006F728UL)) +#define FM_GPIO_PZRB *((volatile uint32_t*)(0x4006F72CUL)) +#define FM4_GPIO_PZRB *((volatile uint32_t*)(0x4006F72CUL)) +#define FM_GPIO_PZRC *((volatile uint32_t*)(0x4006F730UL)) +#define FM4_GPIO_PZRC *((volatile uint32_t*)(0x4006F730UL)) +#define FM_GPIO_PZRD *((volatile uint32_t*)(0x4006F734UL)) +#define FM4_GPIO_PZRD *((volatile uint32_t*)(0x4006F734UL)) +#define FM_GPIO_PZRE *((volatile uint32_t*)(0x4006F738UL)) +#define FM4_GPIO_PZRE *((volatile uint32_t*)(0x4006F738UL)) +#define FM_GPIO_PZRF *((volatile uint32_t*)(0x4006F73CUL)) +#define FM4_GPIO_PZRF *((volatile uint32_t*)(0x4006F73CUL)) +#define FM_GPIO_PDSR0 *((volatile uint32_t*)(0x4006F740UL)) +#define FM4_GPIO_PDSR0 *((volatile uint32_t*)(0x4006F740UL)) +#define FM_GPIO_PDSR1 *((volatile uint32_t*)(0x4006F744UL)) +#define FM4_GPIO_PDSR1 *((volatile uint32_t*)(0x4006F744UL)) +#define FM_GPIO_PDSR2 *((volatile uint32_t*)(0x4006F748UL)) +#define FM4_GPIO_PDSR2 *((volatile uint32_t*)(0x4006F748UL)) +#define FM_GPIO_PDSR3 *((volatile uint32_t*)(0x4006F74CUL)) +#define FM4_GPIO_PDSR3 *((volatile uint32_t*)(0x4006F74CUL)) +#define FM_GPIO_PDSR4 *((volatile uint32_t*)(0x4006F750UL)) +#define FM4_GPIO_PDSR4 *((volatile uint32_t*)(0x4006F750UL)) +#define FM_GPIO_PDSR5 *((volatile uint32_t*)(0x4006F754UL)) +#define FM4_GPIO_PDSR5 *((volatile uint32_t*)(0x4006F754UL)) +#define FM_GPIO_PDSR6 *((volatile uint32_t*)(0x4006F758UL)) +#define FM4_GPIO_PDSR6 *((volatile uint32_t*)(0x4006F758UL)) +#define FM_GPIO_PDSR7 *((volatile uint32_t*)(0x4006F75CUL)) +#define FM4_GPIO_PDSR7 *((volatile uint32_t*)(0x4006F75CUL)) +#define FM_GPIO_PDSR8 *((volatile uint32_t*)(0x4006F760UL)) +#define FM4_GPIO_PDSR8 *((volatile uint32_t*)(0x4006F760UL)) +#define FM_GPIO_PDSR9 *((volatile uint32_t*)(0x4006F764UL)) +#define FM4_GPIO_PDSR9 *((volatile uint32_t*)(0x4006F764UL)) +#define FM_GPIO_PDSRA *((volatile uint32_t*)(0x4006F768UL)) +#define FM4_GPIO_PDSRA *((volatile uint32_t*)(0x4006F768UL)) +#define FM_GPIO_PDSRB *((volatile uint32_t*)(0x4006F76CUL)) +#define FM4_GPIO_PDSRB *((volatile uint32_t*)(0x4006F76CUL)) +#define FM_GPIO_PDSRC *((volatile uint32_t*)(0x4006F770UL)) +#define FM4_GPIO_PDSRC *((volatile uint32_t*)(0x4006F770UL)) +#define FM_GPIO_PDSRD *((volatile uint32_t*)(0x4006F774UL)) +#define FM4_GPIO_PDSRD *((volatile uint32_t*)(0x4006F774UL)) +#define FM_GPIO_PDSRE *((volatile uint32_t*)(0x4006F778UL)) +#define FM4_GPIO_PDSRE *((volatile uint32_t*)(0x4006F778UL)) +#define FM_GPIO_PDSRF *((volatile uint32_t*)(0x4006F77CUL)) +#define FM4_GPIO_PDSRF *((volatile uint32_t*)(0x4006F77CUL)) + +/******************************************************************************* +* HSSPI Registers HSSPI +* Register Definition +*******************************************************************************/ +#define FM_HSSPI_MCTRL *((volatile uint32_t*)(0xD0000000UL)) +#define FM4_HSSPI_MCTRL *((volatile uint32_t*)(0xD0000000UL)) +#define FM_HSSPI_PCC0 *((volatile uint32_t*)(0xD0000004UL)) +#define FM4_HSSPI_PCC0 *((volatile uint32_t*)(0xD0000004UL)) +#define FM_HSSPI_PCC1 *((volatile uint32_t*)(0xD0000008UL)) +#define FM4_HSSPI_PCC1 *((volatile uint32_t*)(0xD0000008UL)) +#define FM_HSSPI_PCC2 *((volatile uint32_t*)(0xD000000CUL)) +#define FM4_HSSPI_PCC2 *((volatile uint32_t*)(0xD000000CUL)) +#define FM_HSSPI_PCC3 *((volatile uint32_t*)(0xD0000010UL)) +#define FM4_HSSPI_PCC3 *((volatile uint32_t*)(0xD0000010UL)) +#define FM_HSSPI_TXF *((volatile uint32_t*)(0xD0000014UL)) +#define FM4_HSSPI_TXF *((volatile uint32_t*)(0xD0000014UL)) +#define FM_HSSPI_TXE *((volatile uint32_t*)(0xD0000018UL)) +#define FM4_HSSPI_TXE *((volatile uint32_t*)(0xD0000018UL)) +#define FM_HSSPI_TXC *((volatile uint32_t*)(0xD000001CUL)) +#define FM4_HSSPI_TXC *((volatile uint32_t*)(0xD000001CUL)) +#define FM_HSSPI_RXF *((volatile uint32_t*)(0xD0000020UL)) +#define FM4_HSSPI_RXF *((volatile uint32_t*)(0xD0000020UL)) +#define FM_HSSPI_RXE *((volatile uint32_t*)(0xD0000024UL)) +#define FM4_HSSPI_RXE *((volatile uint32_t*)(0xD0000024UL)) +#define FM_HSSPI_RXC *((volatile uint32_t*)(0xD0000028UL)) +#define FM4_HSSPI_RXC *((volatile uint32_t*)(0xD0000028UL)) +#define FM_HSSPI_FAULTF *((volatile uint32_t*)(0xD000002CUL)) +#define FM4_HSSPI_FAULTF *((volatile uint32_t*)(0xD000002CUL)) +#define FM_HSSPI_FAULTC *((volatile uint32_t*)(0xD0000030UL)) +#define FM4_HSSPI_FAULTC *((volatile uint32_t*)(0xD0000030UL)) +#define FM_HSSPI_DMCFG *((volatile uint8_t*)(0xD0000034UL)) +#define FM4_HSSPI_DMCFG *((volatile uint8_t*)(0xD0000034UL)) +#define FM_HSSPI_DMDMAEN *((volatile uint8_t*)(0xD0000035UL)) +#define FM4_HSSPI_DMDMAEN *((volatile uint8_t*)(0xD0000035UL)) +#define FM_HSSPI_DMSTART *((volatile uint8_t*)(0xD0000038UL)) +#define FM4_HSSPI_DMSTART *((volatile uint8_t*)(0xD0000038UL)) +#define FM_HSSPI_DMSTOP *((volatile uint8_t*)(0xD0000039UL)) +#define FM4_HSSPI_DMSTOP *((volatile uint8_t*)(0xD0000039UL)) +#define FM_HSSPI_DMPSEL *((volatile uint8_t*)(0xD000003AUL)) +#define FM4_HSSPI_DMPSEL *((volatile uint8_t*)(0xD000003AUL)) +#define FM_HSSPI_DMTRP *((volatile uint8_t*)(0xD000003BUL)) +#define FM4_HSSPI_DMTRP *((volatile uint8_t*)(0xD000003BUL)) +#define FM_HSSPI_DMBCC *((volatile uint16_t*)(0xD000003CUL)) +#define FM4_HSSPI_DMBCC *((volatile uint16_t*)(0xD000003CUL)) +#define FM_HSSPI_DMBCS *((volatile uint16_t*)(0xD000003EUL)) +#define FM4_HSSPI_DMBCS *((volatile uint16_t*)(0xD000003EUL)) +#define FM_HSSPI_DMSTATUS *((volatile uint32_t*)(0xD0000040UL)) +#define FM4_HSSPI_DMSTATUS *((volatile uint32_t*)(0xD0000040UL)) +#define FM_HSSPI_FIFOCFG *((volatile uint32_t*)(0xD000004CUL)) +#define FM4_HSSPI_FIFOCFG *((volatile uint32_t*)(0xD000004CUL)) +#define FM_HSSPI_TXFIFO0 *((volatile uint32_t*)(0xD0000050UL)) +#define FM4_HSSPI_TXFIFO0 *((volatile uint32_t*)(0xD0000050UL)) +#define FM_HSSPI_TXFIFO1 *((volatile uint32_t*)(0xD0000054UL)) +#define FM4_HSSPI_TXFIFO1 *((volatile uint32_t*)(0xD0000054UL)) +#define FM_HSSPI_TXFIFO2 *((volatile uint32_t*)(0xD0000058UL)) +#define FM4_HSSPI_TXFIFO2 *((volatile uint32_t*)(0xD0000058UL)) +#define FM_HSSPI_TXFIFO3 *((volatile uint32_t*)(0xD000005CUL)) +#define FM4_HSSPI_TXFIFO3 *((volatile uint32_t*)(0xD000005CUL)) +#define FM_HSSPI_TXFIFO4 *((volatile uint32_t*)(0xD0000060UL)) +#define FM4_HSSPI_TXFIFO4 *((volatile uint32_t*)(0xD0000060UL)) +#define FM_HSSPI_TXFIFO5 *((volatile uint32_t*)(0xD0000064UL)) +#define FM4_HSSPI_TXFIFO5 *((volatile uint32_t*)(0xD0000064UL)) +#define FM_HSSPI_TXFIFO6 *((volatile uint32_t*)(0xD0000068UL)) +#define FM4_HSSPI_TXFIFO6 *((volatile uint32_t*)(0xD0000068UL)) +#define FM_HSSPI_TXFIFO7 *((volatile uint32_t*)(0xD000006CUL)) +#define FM4_HSSPI_TXFIFO7 *((volatile uint32_t*)(0xD000006CUL)) +#define FM_HSSPI_TXFIFO8 *((volatile uint32_t*)(0xD0000070UL)) +#define FM4_HSSPI_TXFIFO8 *((volatile uint32_t*)(0xD0000070UL)) +#define FM_HSSPI_TXFIFO9 *((volatile uint32_t*)(0xD0000074UL)) +#define FM4_HSSPI_TXFIFO9 *((volatile uint32_t*)(0xD0000074UL)) +#define FM_HSSPI_TXFIFO10 *((volatile uint32_t*)(0xD0000078UL)) +#define FM4_HSSPI_TXFIFO10 *((volatile uint32_t*)(0xD0000078UL)) +#define FM_HSSPI_TXFIFO11 *((volatile uint32_t*)(0xD000007CUL)) +#define FM4_HSSPI_TXFIFO11 *((volatile uint32_t*)(0xD000007CUL)) +#define FM_HSSPI_TXFIFO12 *((volatile uint32_t*)(0xD0000080UL)) +#define FM4_HSSPI_TXFIFO12 *((volatile uint32_t*)(0xD0000080UL)) +#define FM_HSSPI_TXFIFO13 *((volatile uint32_t*)(0xD0000084UL)) +#define FM4_HSSPI_TXFIFO13 *((volatile uint32_t*)(0xD0000084UL)) +#define FM_HSSPI_TXFIFO14 *((volatile uint32_t*)(0xD0000088UL)) +#define FM4_HSSPI_TXFIFO14 *((volatile uint32_t*)(0xD0000088UL)) +#define FM_HSSPI_TXFIFO15 *((volatile uint32_t*)(0xD000008CUL)) +#define FM4_HSSPI_TXFIFO15 *((volatile uint32_t*)(0xD000008CUL)) +#define FM_HSSPI_RXFIFO0 *((volatile uint32_t*)(0xD0000090UL)) +#define FM4_HSSPI_RXFIFO0 *((volatile uint32_t*)(0xD0000090UL)) +#define FM_HSSPI_RXFIFO1 *((volatile uint32_t*)(0xD0000094UL)) +#define FM4_HSSPI_RXFIFO1 *((volatile uint32_t*)(0xD0000094UL)) +#define FM_HSSPI_RXFIFO2 *((volatile uint32_t*)(0xD0000098UL)) +#define FM4_HSSPI_RXFIFO2 *((volatile uint32_t*)(0xD0000098UL)) +#define FM_HSSPI_RXFIFO3 *((volatile uint32_t*)(0xD000009CUL)) +#define FM4_HSSPI_RXFIFO3 *((volatile uint32_t*)(0xD000009CUL)) +#define FM_HSSPI_RXFIFO4 *((volatile uint32_t*)(0xD00000A0UL)) +#define FM4_HSSPI_RXFIFO4 *((volatile uint32_t*)(0xD00000A0UL)) +#define FM_HSSPI_RXFIFO5 *((volatile uint32_t*)(0xD00000A4UL)) +#define FM4_HSSPI_RXFIFO5 *((volatile uint32_t*)(0xD00000A4UL)) +#define FM_HSSPI_RXFIFO6 *((volatile uint32_t*)(0xD00000A8UL)) +#define FM4_HSSPI_RXFIFO6 *((volatile uint32_t*)(0xD00000A8UL)) +#define FM_HSSPI_RXFIFO7 *((volatile uint32_t*)(0xD00000ACUL)) +#define FM4_HSSPI_RXFIFO7 *((volatile uint32_t*)(0xD00000ACUL)) +#define FM_HSSPI_RXFIFO8 *((volatile uint32_t*)(0xD00000B0UL)) +#define FM4_HSSPI_RXFIFO8 *((volatile uint32_t*)(0xD00000B0UL)) +#define FM_HSSPI_RXFIFO9 *((volatile uint32_t*)(0xD00000B4UL)) +#define FM4_HSSPI_RXFIFO9 *((volatile uint32_t*)(0xD00000B4UL)) +#define FM_HSSPI_RXFIFO10 *((volatile uint32_t*)(0xD00000B8UL)) +#define FM4_HSSPI_RXFIFO10 *((volatile uint32_t*)(0xD00000B8UL)) +#define FM_HSSPI_RXFIFO11 *((volatile uint32_t*)(0xD00000BCUL)) +#define FM4_HSSPI_RXFIFO11 *((volatile uint32_t*)(0xD00000BCUL)) +#define FM_HSSPI_RXFIFO12 *((volatile uint32_t*)(0xD00000C0UL)) +#define FM4_HSSPI_RXFIFO12 *((volatile uint32_t*)(0xD00000C0UL)) +#define FM_HSSPI_RXFIFO13 *((volatile uint32_t*)(0xD00000C4UL)) +#define FM4_HSSPI_RXFIFO13 *((volatile uint32_t*)(0xD00000C4UL)) +#define FM_HSSPI_RXFIFO14 *((volatile uint32_t*)(0xD00000C8UL)) +#define FM4_HSSPI_RXFIFO14 *((volatile uint32_t*)(0xD00000C8UL)) +#define FM_HSSPI_RXFIFO15 *((volatile uint32_t*)(0xD00000CCUL)) +#define FM4_HSSPI_RXFIFO15 *((volatile uint32_t*)(0xD00000CCUL)) +#define FM_HSSPI_CSCFG *((volatile uint32_t*)(0xD00000D0UL)) +#define FM4_HSSPI_CSCFG *((volatile uint32_t*)(0xD00000D0UL)) +#define FM_HSSPI_CSITIME *((volatile uint32_t*)(0xD00000D4UL)) +#define FM4_HSSPI_CSITIME *((volatile uint32_t*)(0xD00000D4UL)) +#define FM_HSSPI_CSAEXT *((volatile uint32_t*)(0xD00000D8UL)) +#define FM4_HSSPI_CSAEXT *((volatile uint32_t*)(0xD00000D8UL)) +#define FM_HSSPI_RDCSDC0 *((volatile uint16_t*)(0xD00000DCUL)) +#define FM4_HSSPI_RDCSDC0 *((volatile uint16_t*)(0xD00000DCUL)) +#define FM_HSSPI_RDCSDC1 *((volatile uint16_t*)(0xD00000DEUL)) +#define FM4_HSSPI_RDCSDC1 *((volatile uint16_t*)(0xD00000DEUL)) +#define FM_HSSPI_RDCSDC2 *((volatile uint16_t*)(0xD00000E0UL)) +#define FM4_HSSPI_RDCSDC2 *((volatile uint16_t*)(0xD00000E0UL)) +#define FM_HSSPI_RDCSDC3 *((volatile uint16_t*)(0xD00000E2UL)) +#define FM4_HSSPI_RDCSDC3 *((volatile uint16_t*)(0xD00000E2UL)) +#define FM_HSSPI_RDCSDC4 *((volatile uint16_t*)(0xD00000E4UL)) +#define FM4_HSSPI_RDCSDC4 *((volatile uint16_t*)(0xD00000E4UL)) +#define FM_HSSPI_RDCSDC5 *((volatile uint16_t*)(0xD00000E6UL)) +#define FM4_HSSPI_RDCSDC5 *((volatile uint16_t*)(0xD00000E6UL)) +#define FM_HSSPI_RDCSDC6 *((volatile uint16_t*)(0xD00000E8UL)) +#define FM4_HSSPI_RDCSDC6 *((volatile uint16_t*)(0xD00000E8UL)) +#define FM_HSSPI_RDCSDC7 *((volatile uint16_t*)(0xD00000EAUL)) +#define FM4_HSSPI_RDCSDC7 *((volatile uint16_t*)(0xD00000EAUL)) +#define FM_HSSPI_WRCSDC0 *((volatile uint16_t*)(0xD00000ECUL)) +#define FM4_HSSPI_WRCSDC0 *((volatile uint16_t*)(0xD00000ECUL)) +#define FM_HSSPI_WRCSDC1 *((volatile uint16_t*)(0xD00000EEUL)) +#define FM4_HSSPI_WRCSDC1 *((volatile uint16_t*)(0xD00000EEUL)) +#define FM_HSSPI_WRCSDC2 *((volatile uint16_t*)(0xD00000F0UL)) +#define FM4_HSSPI_WRCSDC2 *((volatile uint16_t*)(0xD00000F0UL)) +#define FM_HSSPI_WRCSDC3 *((volatile uint16_t*)(0xD00000F2UL)) +#define FM4_HSSPI_WRCSDC3 *((volatile uint16_t*)(0xD00000F2UL)) +#define FM_HSSPI_WRCSDC4 *((volatile uint16_t*)(0xD00000F4UL)) +#define FM4_HSSPI_WRCSDC4 *((volatile uint16_t*)(0xD00000F4UL)) +#define FM_HSSPI_WRCSDC5 *((volatile uint16_t*)(0xD00000F6UL)) +#define FM4_HSSPI_WRCSDC5 *((volatile uint16_t*)(0xD00000F6UL)) +#define FM_HSSPI_WRCSDC6 *((volatile uint16_t*)(0xD00000F8UL)) +#define FM4_HSSPI_WRCSDC6 *((volatile uint16_t*)(0xD00000F8UL)) +#define FM_HSSPI_WRCSDC7 *((volatile uint16_t*)(0xD00000FAUL)) +#define FM4_HSSPI_WRCSDC7 *((volatile uint16_t*)(0xD00000FAUL)) +#define FM_HSSPI_MID *((volatile uint32_t*)(0xD00000FCUL)) +#define FM4_HSSPI_MID *((volatile uint32_t*)(0xD00000FCUL)) +#define FM_HSSPI_QDCLKR *((volatile uint8_t*)(0xD0000400UL)) +#define FM4_HSSPI_QDCLKR *((volatile uint8_t*)(0xD0000400UL)) +#define FM_HSSPI_DBCNT *((volatile uint8_t*)(0xD0000404UL)) +#define FM4_HSSPI_DBCNT *((volatile uint8_t*)(0xD0000404UL)) + +/******************************************************************************* +* HWWDT Registers HWWDT +* Register Definition +*******************************************************************************/ +#define FM_HWWDT_WDG_LDR *((volatile uint32_t*)(0x40011000UL)) +#define FM4_HWWDT_WDG_LDR *((volatile uint32_t*)(0x40011000UL)) +#define FM_HWWDT_WDG_VLR *((volatile uint32_t*)(0x40011004UL)) +#define FM4_HWWDT_WDG_VLR *((volatile uint32_t*)(0x40011004UL)) +#define FM_HWWDT_WDG_CTL *((volatile uint32_t*)(0x40011008UL)) +#define FM4_HWWDT_WDG_CTL *((volatile uint32_t*)(0x40011008UL)) +#define FM_HWWDT_WDG_ICL *((volatile uint32_t*)(0x4001100CUL)) +#define FM4_HWWDT_WDG_ICL *((volatile uint32_t*)(0x4001100CUL)) +#define FM_HWWDT_WDG_RIS *((volatile uint32_t*)(0x40011010UL)) +#define FM4_HWWDT_WDG_RIS *((volatile uint32_t*)(0x40011010UL)) +#define FM_HWWDT_WDG_LCK *((volatile uint32_t*)(0x40011C00UL)) +#define FM4_HWWDT_WDG_LCK *((volatile uint32_t*)(0x40011C00UL)) + +/******************************************************************************* +* I2S Registers I2S0 +* Register Definition +*******************************************************************************/ +#define FM_I2S0_RXFDAT *((volatile uint32_t*)(0x4006C000UL)) +#define FM4_I2S0_RXFDAT *((volatile uint32_t*)(0x4006C000UL)) +#define FM_I2S0_TXFDAT *((volatile uint32_t*)(0x4006C004UL)) +#define FM4_I2S0_TXFDAT *((volatile uint32_t*)(0x4006C004UL)) +#define FM_I2S0_CNTREG *((volatile uint32_t*)(0x4006C008UL)) +#define FM4_I2S0_CNTREG *((volatile uint32_t*)(0x4006C008UL)) +#define FM_I2S0_MCR0REG *((volatile uint32_t*)(0x4006C00CUL)) +#define FM4_I2S0_MCR0REG *((volatile uint32_t*)(0x4006C00CUL)) +#define FM_I2S0_MCR1REG *((volatile uint32_t*)(0x4006C010UL)) +#define FM4_I2S0_MCR1REG *((volatile uint32_t*)(0x4006C010UL)) +#define FM_I2S0_MCR2REG *((volatile uint32_t*)(0x4006C014UL)) +#define FM4_I2S0_MCR2REG *((volatile uint32_t*)(0x4006C014UL)) +#define FM_I2S0_OPRREG *((volatile uint32_t*)(0x4006C018UL)) +#define FM4_I2S0_OPRREG *((volatile uint32_t*)(0x4006C018UL)) +#define FM_I2S0_SRST *((volatile uint32_t*)(0x4006C01CUL)) +#define FM4_I2S0_SRST *((volatile uint32_t*)(0x4006C01CUL)) +#define FM_I2S0_INTCNT *((volatile uint32_t*)(0x4006C020UL)) +#define FM4_I2S0_INTCNT *((volatile uint32_t*)(0x4006C020UL)) +#define FM_I2S0_STATUS *((volatile uint32_t*)(0x4006C024UL)) +#define FM4_I2S0_STATUS *((volatile uint32_t*)(0x4006C024UL)) +#define FM_I2S0_DMAACT *((volatile uint32_t*)(0x4006C028UL)) +#define FM4_I2S0_DMAACT *((volatile uint32_t*)(0x4006C028UL)) +#define FM_I2S0_TSTREG *((volatile uint32_t*)(0x4006C02CUL)) +#define FM4_I2S0_TSTREG *((volatile uint32_t*)(0x4006C02CUL)) + +/******************************************************************************* +* I2SPRE Registers I2SPRE +* Register Definition +*******************************************************************************/ +#define FM_I2SPRE_ICCR *((volatile uint32_t*)(0x4003D000UL)) +#define FM4_I2SPRE_ICCR *((volatile uint32_t*)(0x4003D000UL)) +#define FM_I2SPRE_IPCR1 *((volatile uint32_t*)(0x4003D004UL)) +#define FM4_I2SPRE_IPCR1 *((volatile uint32_t*)(0x4003D004UL)) +#define FM_I2SPRE_IPCR2 *((volatile uint32_t*)(0x4003D008UL)) +#define FM4_I2SPRE_IPCR2 *((volatile uint32_t*)(0x4003D008UL)) +#define FM_I2SPRE_IPCR3 *((volatile uint32_t*)(0x4003D00CUL)) +#define FM4_I2SPRE_IPCR3 *((volatile uint32_t*)(0x4003D00CUL)) +#define FM_I2SPRE_IPCR4 *((volatile uint32_t*)(0x4003D010UL)) +#define FM4_I2SPRE_IPCR4 *((volatile uint32_t*)(0x4003D010UL)) +#define FM_I2SPRE_IP_STR *((volatile uint32_t*)(0x4003D014UL)) +#define FM4_I2SPRE_IP_STR *((volatile uint32_t*)(0x4003D014UL)) +#define FM_I2SPRE_IPINT_ENR *((volatile uint32_t*)(0x4003D018UL)) +#define FM4_I2SPRE_IPINT_ENR *((volatile uint32_t*)(0x4003D018UL)) +#define FM_I2SPRE_IPINT_CLR *((volatile uint32_t*)(0x4003D01CUL)) +#define FM4_I2SPRE_IPINT_CLR *((volatile uint32_t*)(0x4003D01CUL)) +#define FM_I2SPRE_IPINT_STR *((volatile uint32_t*)(0x4003D020UL)) +#define FM4_I2SPRE_IPINT_STR *((volatile uint32_t*)(0x4003D020UL)) +#define FM_I2SPRE_IPCR5 *((volatile uint32_t*)(0x4003D024UL)) +#define FM4_I2SPRE_IPCR5 *((volatile uint32_t*)(0x4003D024UL)) + +/******************************************************************************* +* INTREQ Registers INTREQ +* Register Definition +*******************************************************************************/ +#define FM_INTREQ_DRQSEL *((volatile uint32_t*)(0x40031000UL)) +#define FM4_INTREQ_DRQSEL *((volatile uint32_t*)(0x40031000UL)) +#define FM_INTREQ_ODDPKS *((volatile uint8_t*)(0x40031010UL)) +#define FM4_INTREQ_ODDPKS *((volatile uint8_t*)(0x40031010UL)) +#define FM_INTREQ_ODDPKS1 *((volatile uint8_t*)(0x40031014UL)) +#define FM4_INTREQ_ODDPKS1 *((volatile uint8_t*)(0x40031014UL)) +#define FM_INTREQ_IRQ003SEL *((volatile uint32_t*)(0x40031110UL)) +#define FM4_INTREQ_IRQ003SEL *((volatile uint32_t*)(0x40031110UL)) +#define FM_INTREQ_IRQ004SEL *((volatile uint32_t*)(0x40031114UL)) +#define FM4_INTREQ_IRQ004SEL *((volatile uint32_t*)(0x40031114UL)) +#define FM_INTREQ_IRQ005SEL *((volatile uint32_t*)(0x40031118UL)) +#define FM4_INTREQ_IRQ005SEL *((volatile uint32_t*)(0x40031118UL)) +#define FM_INTREQ_IRQ006SEL *((volatile uint32_t*)(0x4003111CUL)) +#define FM4_INTREQ_IRQ006SEL *((volatile uint32_t*)(0x4003111CUL)) +#define FM_INTREQ_IRQ007SEL *((volatile uint32_t*)(0x40031120UL)) +#define FM4_INTREQ_IRQ007SEL *((volatile uint32_t*)(0x40031120UL)) +#define FM_INTREQ_IRQ008SEL *((volatile uint32_t*)(0x40031124UL)) +#define FM4_INTREQ_IRQ008SEL *((volatile uint32_t*)(0x40031124UL)) +#define FM_INTREQ_IRQ009SEL *((volatile uint32_t*)(0x40031128UL)) +#define FM4_INTREQ_IRQ009SEL *((volatile uint32_t*)(0x40031128UL)) +#define FM_INTREQ_IRQ010SEL *((volatile uint32_t*)(0x4003112CUL)) +#define FM4_INTREQ_IRQ010SEL *((volatile uint32_t*)(0x4003112CUL)) +#define FM_INTREQ_EXC02MON *((volatile uint32_t*)(0x40031200UL)) +#define FM4_INTREQ_EXC02MON *((volatile uint32_t*)(0x40031200UL)) +#define FM_INTREQ_IRQ000MON *((volatile uint32_t*)(0x40031204UL)) +#define FM4_INTREQ_IRQ000MON *((volatile uint32_t*)(0x40031204UL)) +#define FM_INTREQ_IRQ001MON *((volatile uint32_t*)(0x40031208UL)) +#define FM4_INTREQ_IRQ001MON *((volatile uint32_t*)(0x40031208UL)) +#define FM_INTREQ_IRQ002MON *((volatile uint32_t*)(0x4003120CUL)) +#define FM4_INTREQ_IRQ002MON *((volatile uint32_t*)(0x4003120CUL)) +#define FM_INTREQ_IRQ003MON *((volatile uint32_t*)(0x40031210UL)) +#define FM4_INTREQ_IRQ003MON *((volatile uint32_t*)(0x40031210UL)) +#define FM_INTREQ_IRQ004MON *((volatile uint32_t*)(0x40031214UL)) +#define FM4_INTREQ_IRQ004MON *((volatile uint32_t*)(0x40031214UL)) +#define FM_INTREQ_IRQ005MON *((volatile uint32_t*)(0x40031218UL)) +#define FM4_INTREQ_IRQ005MON *((volatile uint32_t*)(0x40031218UL)) +#define FM_INTREQ_IRQ006MON *((volatile uint32_t*)(0x4003121CUL)) +#define FM4_INTREQ_IRQ006MON *((volatile uint32_t*)(0x4003121CUL)) +#define FM_INTREQ_IRQ007MON *((volatile uint32_t*)(0x40031220UL)) +#define FM4_INTREQ_IRQ007MON *((volatile uint32_t*)(0x40031220UL)) +#define FM_INTREQ_IRQ008MON *((volatile uint32_t*)(0x40031224UL)) +#define FM4_INTREQ_IRQ008MON *((volatile uint32_t*)(0x40031224UL)) +#define FM_INTREQ_IRQ009MON *((volatile uint32_t*)(0x40031228UL)) +#define FM4_INTREQ_IRQ009MON *((volatile uint32_t*)(0x40031228UL)) +#define FM_INTREQ_IRQ010MON *((volatile uint32_t*)(0x4003122CUL)) +#define FM4_INTREQ_IRQ010MON *((volatile uint32_t*)(0x4003122CUL)) +#define FM_INTREQ_IRQ011MON *((volatile uint32_t*)(0x40031230UL)) +#define FM4_INTREQ_IRQ011MON *((volatile uint32_t*)(0x40031230UL)) +#define FM_INTREQ_IRQ012MON *((volatile uint32_t*)(0x40031234UL)) +#define FM4_INTREQ_IRQ012MON *((volatile uint32_t*)(0x40031234UL)) +#define FM_INTREQ_IRQ013MON *((volatile uint32_t*)(0x40031238UL)) +#define FM4_INTREQ_IRQ013MON *((volatile uint32_t*)(0x40031238UL)) +#define FM_INTREQ_IRQ014MON *((volatile uint32_t*)(0x4003123CUL)) +#define FM4_INTREQ_IRQ014MON *((volatile uint32_t*)(0x4003123CUL)) +#define FM_INTREQ_IRQ015MON *((volatile uint32_t*)(0x40031240UL)) +#define FM4_INTREQ_IRQ015MON *((volatile uint32_t*)(0x40031240UL)) +#define FM_INTREQ_IRQ016MON *((volatile uint32_t*)(0x40031244UL)) +#define FM4_INTREQ_IRQ016MON *((volatile uint32_t*)(0x40031244UL)) +#define FM_INTREQ_IRQ017MON *((volatile uint32_t*)(0x40031248UL)) +#define FM4_INTREQ_IRQ017MON *((volatile uint32_t*)(0x40031248UL)) +#define FM_INTREQ_IRQ018MON *((volatile uint32_t*)(0x4003124CUL)) +#define FM4_INTREQ_IRQ018MON *((volatile uint32_t*)(0x4003124CUL)) +#define FM_INTREQ_IRQ019MON *((volatile uint32_t*)(0x40031250UL)) +#define FM4_INTREQ_IRQ019MON *((volatile uint32_t*)(0x40031250UL)) +#define FM_INTREQ_IRQ020MON *((volatile uint32_t*)(0x40031254UL)) +#define FM4_INTREQ_IRQ020MON *((volatile uint32_t*)(0x40031254UL)) +#define FM_INTREQ_IRQ021MON *((volatile uint32_t*)(0x40031258UL)) +#define FM4_INTREQ_IRQ021MON *((volatile uint32_t*)(0x40031258UL)) +#define FM_INTREQ_IRQ022MON *((volatile uint32_t*)(0x4003125CUL)) +#define FM4_INTREQ_IRQ022MON *((volatile uint32_t*)(0x4003125CUL)) +#define FM_INTREQ_IRQ023MON *((volatile uint32_t*)(0x40031260UL)) +#define FM4_INTREQ_IRQ023MON *((volatile uint32_t*)(0x40031260UL)) +#define FM_INTREQ_IRQ024MON *((volatile uint32_t*)(0x40031264UL)) +#define FM4_INTREQ_IRQ024MON *((volatile uint32_t*)(0x40031264UL)) +#define FM_INTREQ_IRQ025MON *((volatile uint32_t*)(0x40031268UL)) +#define FM4_INTREQ_IRQ025MON *((volatile uint32_t*)(0x40031268UL)) +#define FM_INTREQ_IRQ026MON *((volatile uint32_t*)(0x4003126CUL)) +#define FM4_INTREQ_IRQ026MON *((volatile uint32_t*)(0x4003126CUL)) +#define FM_INTREQ_IRQ027MON *((volatile uint32_t*)(0x40031270UL)) +#define FM4_INTREQ_IRQ027MON *((volatile uint32_t*)(0x40031270UL)) +#define FM_INTREQ_IRQ028MON *((volatile uint32_t*)(0x40031274UL)) +#define FM4_INTREQ_IRQ028MON *((volatile uint32_t*)(0x40031274UL)) +#define FM_INTREQ_IRQ029MON *((volatile uint32_t*)(0x40031278UL)) +#define FM4_INTREQ_IRQ029MON *((volatile uint32_t*)(0x40031278UL)) +#define FM_INTREQ_IRQ030MON *((volatile uint32_t*)(0x4003127CUL)) +#define FM4_INTREQ_IRQ030MON *((volatile uint32_t*)(0x4003127CUL)) +#define FM_INTREQ_IRQ031MON *((volatile uint32_t*)(0x40031280UL)) +#define FM4_INTREQ_IRQ031MON *((volatile uint32_t*)(0x40031280UL)) +#define FM_INTREQ_IRQ032MON *((volatile uint32_t*)(0x40031284UL)) +#define FM4_INTREQ_IRQ032MON *((volatile uint32_t*)(0x40031284UL)) +#define FM_INTREQ_IRQ033MON *((volatile uint32_t*)(0x40031288UL)) +#define FM4_INTREQ_IRQ033MON *((volatile uint32_t*)(0x40031288UL)) +#define FM_INTREQ_IRQ034MON *((volatile uint32_t*)(0x4003128CUL)) +#define FM4_INTREQ_IRQ034MON *((volatile uint32_t*)(0x4003128CUL)) +#define FM_INTREQ_IRQ035MON *((volatile uint32_t*)(0x40031290UL)) +#define FM4_INTREQ_IRQ035MON *((volatile uint32_t*)(0x40031290UL)) +#define FM_INTREQ_IRQ036MON *((volatile uint32_t*)(0x40031294UL)) +#define FM4_INTREQ_IRQ036MON *((volatile uint32_t*)(0x40031294UL)) +#define FM_INTREQ_IRQ037MON *((volatile uint32_t*)(0x40031298UL)) +#define FM4_INTREQ_IRQ037MON *((volatile uint32_t*)(0x40031298UL)) +#define FM_INTREQ_IRQ038MON *((volatile uint32_t*)(0x4003129CUL)) +#define FM4_INTREQ_IRQ038MON *((volatile uint32_t*)(0x4003129CUL)) +#define FM_INTREQ_IRQ039MON *((volatile uint32_t*)(0x400312A0UL)) +#define FM4_INTREQ_IRQ039MON *((volatile uint32_t*)(0x400312A0UL)) +#define FM_INTREQ_IRQ040MON *((volatile uint32_t*)(0x400312A4UL)) +#define FM4_INTREQ_IRQ040MON *((volatile uint32_t*)(0x400312A4UL)) +#define FM_INTREQ_IRQ041MON *((volatile uint32_t*)(0x400312A8UL)) +#define FM4_INTREQ_IRQ041MON *((volatile uint32_t*)(0x400312A8UL)) +#define FM_INTREQ_IRQ042MON *((volatile uint32_t*)(0x400312ACUL)) +#define FM4_INTREQ_IRQ042MON *((volatile uint32_t*)(0x400312ACUL)) +#define FM_INTREQ_IRQ043MON *((volatile uint32_t*)(0x400312B0UL)) +#define FM4_INTREQ_IRQ043MON *((volatile uint32_t*)(0x400312B0UL)) +#define FM_INTREQ_IRQ044MON *((volatile uint32_t*)(0x400312B4UL)) +#define FM4_INTREQ_IRQ044MON *((volatile uint32_t*)(0x400312B4UL)) +#define FM_INTREQ_IRQ045MON *((volatile uint32_t*)(0x400312B8UL)) +#define FM4_INTREQ_IRQ045MON *((volatile uint32_t*)(0x400312B8UL)) +#define FM_INTREQ_IRQ046MON *((volatile uint32_t*)(0x400312BCUL)) +#define FM4_INTREQ_IRQ046MON *((volatile uint32_t*)(0x400312BCUL)) +#define FM_INTREQ_IRQ047MON *((volatile uint32_t*)(0x400312C0UL)) +#define FM4_INTREQ_IRQ047MON *((volatile uint32_t*)(0x400312C0UL)) +#define FM_INTREQ_IRQ048MON *((volatile uint32_t*)(0x400312C4UL)) +#define FM4_INTREQ_IRQ048MON *((volatile uint32_t*)(0x400312C4UL)) +#define FM_INTREQ_IRQ049MON *((volatile uint32_t*)(0x400312C8UL)) +#define FM4_INTREQ_IRQ049MON *((volatile uint32_t*)(0x400312C8UL)) +#define FM_INTREQ_IRQ050MON *((volatile uint32_t*)(0x400312CCUL)) +#define FM4_INTREQ_IRQ050MON *((volatile uint32_t*)(0x400312CCUL)) +#define FM_INTREQ_IRQ051MON *((volatile uint32_t*)(0x400312D0UL)) +#define FM4_INTREQ_IRQ051MON *((volatile uint32_t*)(0x400312D0UL)) +#define FM_INTREQ_IRQ052MON *((volatile uint32_t*)(0x400312D4UL)) +#define FM4_INTREQ_IRQ052MON *((volatile uint32_t*)(0x400312D4UL)) +#define FM_INTREQ_IRQ053MON *((volatile uint32_t*)(0x400312D8UL)) +#define FM4_INTREQ_IRQ053MON *((volatile uint32_t*)(0x400312D8UL)) +#define FM_INTREQ_IRQ054MON *((volatile uint32_t*)(0x400312DCUL)) +#define FM4_INTREQ_IRQ054MON *((volatile uint32_t*)(0x400312DCUL)) +#define FM_INTREQ_IRQ055MON *((volatile uint32_t*)(0x400312E0UL)) +#define FM4_INTREQ_IRQ055MON *((volatile uint32_t*)(0x400312E0UL)) +#define FM_INTREQ_IRQ056MON *((volatile uint32_t*)(0x400312E4UL)) +#define FM4_INTREQ_IRQ056MON *((volatile uint32_t*)(0x400312E4UL)) +#define FM_INTREQ_IRQ057MON *((volatile uint32_t*)(0x400312E8UL)) +#define FM4_INTREQ_IRQ057MON *((volatile uint32_t*)(0x400312E8UL)) +#define FM_INTREQ_IRQ058MON *((volatile uint32_t*)(0x400312ECUL)) +#define FM4_INTREQ_IRQ058MON *((volatile uint32_t*)(0x400312ECUL)) +#define FM_INTREQ_IRQ059MON *((volatile uint32_t*)(0x400312F0UL)) +#define FM4_INTREQ_IRQ059MON *((volatile uint32_t*)(0x400312F0UL)) +#define FM_INTREQ_IRQ060MON *((volatile uint32_t*)(0x400312F4UL)) +#define FM4_INTREQ_IRQ060MON *((volatile uint32_t*)(0x400312F4UL)) +#define FM_INTREQ_IRQ061MON *((volatile uint32_t*)(0x400312F8UL)) +#define FM4_INTREQ_IRQ061MON *((volatile uint32_t*)(0x400312F8UL)) +#define FM_INTREQ_IRQ062MON *((volatile uint32_t*)(0x400312FCUL)) +#define FM4_INTREQ_IRQ062MON *((volatile uint32_t*)(0x400312FCUL)) +#define FM_INTREQ_IRQ063MON *((volatile uint32_t*)(0x40031300UL)) +#define FM4_INTREQ_IRQ063MON *((volatile uint32_t*)(0x40031300UL)) +#define FM_INTREQ_IRQ064MON *((volatile uint32_t*)(0x40031304UL)) +#define FM4_INTREQ_IRQ064MON *((volatile uint32_t*)(0x40031304UL)) +#define FM_INTREQ_IRQ065MON *((volatile uint32_t*)(0x40031308UL)) +#define FM4_INTREQ_IRQ065MON *((volatile uint32_t*)(0x40031308UL)) +#define FM_INTREQ_IRQ066MON *((volatile uint32_t*)(0x4003130CUL)) +#define FM4_INTREQ_IRQ066MON *((volatile uint32_t*)(0x4003130CUL)) +#define FM_INTREQ_IRQ067MON *((volatile uint32_t*)(0x40031310UL)) +#define FM4_INTREQ_IRQ067MON *((volatile uint32_t*)(0x40031310UL)) +#define FM_INTREQ_IRQ068MON *((volatile uint32_t*)(0x40031314UL)) +#define FM4_INTREQ_IRQ068MON *((volatile uint32_t*)(0x40031314UL)) +#define FM_INTREQ_IRQ069MON *((volatile uint32_t*)(0x40031318UL)) +#define FM4_INTREQ_IRQ069MON *((volatile uint32_t*)(0x40031318UL)) +#define FM_INTREQ_IRQ070MON *((volatile uint32_t*)(0x4003131CUL)) +#define FM4_INTREQ_IRQ070MON *((volatile uint32_t*)(0x4003131CUL)) +#define FM_INTREQ_IRQ071MON *((volatile uint32_t*)(0x40031320UL)) +#define FM4_INTREQ_IRQ071MON *((volatile uint32_t*)(0x40031320UL)) +#define FM_INTREQ_IRQ072MON *((volatile uint32_t*)(0x40031324UL)) +#define FM4_INTREQ_IRQ072MON *((volatile uint32_t*)(0x40031324UL)) +#define FM_INTREQ_IRQ073MON *((volatile uint32_t*)(0x40031328UL)) +#define FM4_INTREQ_IRQ073MON *((volatile uint32_t*)(0x40031328UL)) +#define FM_INTREQ_IRQ074MON *((volatile uint32_t*)(0x4003132CUL)) +#define FM4_INTREQ_IRQ074MON *((volatile uint32_t*)(0x4003132CUL)) +#define FM_INTREQ_IRQ075MON *((volatile uint32_t*)(0x40031330UL)) +#define FM4_INTREQ_IRQ075MON *((volatile uint32_t*)(0x40031330UL)) +#define FM_INTREQ_IRQ076MON *((volatile uint32_t*)(0x40031334UL)) +#define FM4_INTREQ_IRQ076MON *((volatile uint32_t*)(0x40031334UL)) +#define FM_INTREQ_IRQ077MON *((volatile uint32_t*)(0x40031338UL)) +#define FM4_INTREQ_IRQ077MON *((volatile uint32_t*)(0x40031338UL)) +#define FM_INTREQ_IRQ078MON *((volatile uint32_t*)(0x4003133CUL)) +#define FM4_INTREQ_IRQ078MON *((volatile uint32_t*)(0x4003133CUL)) +#define FM_INTREQ_IRQ079MON *((volatile uint32_t*)(0x40031340UL)) +#define FM4_INTREQ_IRQ079MON *((volatile uint32_t*)(0x40031340UL)) +#define FM_INTREQ_IRQ080MON *((volatile uint32_t*)(0x40031344UL)) +#define FM4_INTREQ_IRQ080MON *((volatile uint32_t*)(0x40031344UL)) +#define FM_INTREQ_IRQ081MON *((volatile uint32_t*)(0x40031348UL)) +#define FM4_INTREQ_IRQ081MON *((volatile uint32_t*)(0x40031348UL)) +#define FM_INTREQ_IRQ082MON *((volatile uint32_t*)(0x4003134CUL)) +#define FM4_INTREQ_IRQ082MON *((volatile uint32_t*)(0x4003134CUL)) +#define FM_INTREQ_IRQ083MON *((volatile uint32_t*)(0x40031350UL)) +#define FM4_INTREQ_IRQ083MON *((volatile uint32_t*)(0x40031350UL)) +#define FM_INTREQ_IRQ084MON *((volatile uint32_t*)(0x40031354UL)) +#define FM4_INTREQ_IRQ084MON *((volatile uint32_t*)(0x40031354UL)) +#define FM_INTREQ_IRQ085MON *((volatile uint32_t*)(0x40031358UL)) +#define FM4_INTREQ_IRQ085MON *((volatile uint32_t*)(0x40031358UL)) +#define FM_INTREQ_IRQ086MON *((volatile uint32_t*)(0x4003135CUL)) +#define FM4_INTREQ_IRQ086MON *((volatile uint32_t*)(0x4003135CUL)) +#define FM_INTREQ_IRQ087MON *((volatile uint32_t*)(0x40031360UL)) +#define FM4_INTREQ_IRQ087MON *((volatile uint32_t*)(0x40031360UL)) +#define FM_INTREQ_IRQ088MON *((volatile uint32_t*)(0x40031364UL)) +#define FM4_INTREQ_IRQ088MON *((volatile uint32_t*)(0x40031364UL)) +#define FM_INTREQ_IRQ089MON *((volatile uint32_t*)(0x40031368UL)) +#define FM4_INTREQ_IRQ089MON *((volatile uint32_t*)(0x40031368UL)) +#define FM_INTREQ_IRQ090MON *((volatile uint32_t*)(0x4003136CUL)) +#define FM4_INTREQ_IRQ090MON *((volatile uint32_t*)(0x4003136CUL)) +#define FM_INTREQ_IRQ091MON *((volatile uint32_t*)(0x40031370UL)) +#define FM4_INTREQ_IRQ091MON *((volatile uint32_t*)(0x40031370UL)) +#define FM_INTREQ_IRQ092MON *((volatile uint32_t*)(0x40031374UL)) +#define FM4_INTREQ_IRQ092MON *((volatile uint32_t*)(0x40031374UL)) +#define FM_INTREQ_IRQ093MON *((volatile uint32_t*)(0x40031378UL)) +#define FM4_INTREQ_IRQ093MON *((volatile uint32_t*)(0x40031378UL)) +#define FM_INTREQ_IRQ094MON *((volatile uint32_t*)(0x4003137CUL)) +#define FM4_INTREQ_IRQ094MON *((volatile uint32_t*)(0x4003137CUL)) +#define FM_INTREQ_IRQ095MON *((volatile uint32_t*)(0x40031380UL)) +#define FM4_INTREQ_IRQ095MON *((volatile uint32_t*)(0x40031380UL)) +#define FM_INTREQ_IRQ096MON *((volatile uint32_t*)(0x40031384UL)) +#define FM4_INTREQ_IRQ096MON *((volatile uint32_t*)(0x40031384UL)) +#define FM_INTREQ_IRQ097MON *((volatile uint32_t*)(0x40031388UL)) +#define FM4_INTREQ_IRQ097MON *((volatile uint32_t*)(0x40031388UL)) +#define FM_INTREQ_IRQ098MON *((volatile uint32_t*)(0x4003138CUL)) +#define FM4_INTREQ_IRQ098MON *((volatile uint32_t*)(0x4003138CUL)) +#define FM_INTREQ_IRQ099MON *((volatile uint32_t*)(0x40031390UL)) +#define FM4_INTREQ_IRQ099MON *((volatile uint32_t*)(0x40031390UL)) +#define FM_INTREQ_IRQ100MON *((volatile uint32_t*)(0x40031394UL)) +#define FM4_INTREQ_IRQ100MON *((volatile uint32_t*)(0x40031394UL)) +#define FM_INTREQ_IRQ101MON *((volatile uint32_t*)(0x40031398UL)) +#define FM4_INTREQ_IRQ101MON *((volatile uint32_t*)(0x40031398UL)) +#define FM_INTREQ_IRQ102MON *((volatile uint32_t*)(0x4003139CUL)) +#define FM4_INTREQ_IRQ102MON *((volatile uint32_t*)(0x4003139CUL)) +#define FM_INTREQ_IRQ103MON *((volatile uint32_t*)(0x400313A0UL)) +#define FM4_INTREQ_IRQ103MON *((volatile uint32_t*)(0x400313A0UL)) +#define FM_INTREQ_IRQ104MON *((volatile uint32_t*)(0x400313A4UL)) +#define FM4_INTREQ_IRQ104MON *((volatile uint32_t*)(0x400313A4UL)) +#define FM_INTREQ_IRQ105MON *((volatile uint32_t*)(0x400313A8UL)) +#define FM4_INTREQ_IRQ105MON *((volatile uint32_t*)(0x400313A8UL)) +#define FM_INTREQ_IRQ106MON *((volatile uint32_t*)(0x400313ACUL)) +#define FM4_INTREQ_IRQ106MON *((volatile uint32_t*)(0x400313ACUL)) +#define FM_INTREQ_IRQ107MON *((volatile uint32_t*)(0x400313B0UL)) +#define FM4_INTREQ_IRQ107MON *((volatile uint32_t*)(0x400313B0UL)) +#define FM_INTREQ_IRQ108MON *((volatile uint32_t*)(0x400313B4UL)) +#define FM4_INTREQ_IRQ108MON *((volatile uint32_t*)(0x400313B4UL)) +#define FM_INTREQ_IRQ109MON *((volatile uint32_t*)(0x400313B8UL)) +#define FM4_INTREQ_IRQ109MON *((volatile uint32_t*)(0x400313B8UL)) +#define FM_INTREQ_IRQ110MON *((volatile uint32_t*)(0x400313BCUL)) +#define FM4_INTREQ_IRQ110MON *((volatile uint32_t*)(0x400313BCUL)) +#define FM_INTREQ_IRQ111MON *((volatile uint32_t*)(0x400313C0UL)) +#define FM4_INTREQ_IRQ111MON *((volatile uint32_t*)(0x400313C0UL)) +#define FM_INTREQ_IRQ112MON *((volatile uint32_t*)(0x400313C4UL)) +#define FM4_INTREQ_IRQ112MON *((volatile uint32_t*)(0x400313C4UL)) +#define FM_INTREQ_IRQ113MON *((volatile uint32_t*)(0x400313C8UL)) +#define FM4_INTREQ_IRQ113MON *((volatile uint32_t*)(0x400313C8UL)) +#define FM_INTREQ_IRQ114MON *((volatile uint32_t*)(0x400313CCUL)) +#define FM4_INTREQ_IRQ114MON *((volatile uint32_t*)(0x400313CCUL)) +#define FM_INTREQ_IRQ115MON *((volatile uint32_t*)(0x400313D0UL)) +#define FM4_INTREQ_IRQ115MON *((volatile uint32_t*)(0x400313D0UL)) +#define FM_INTREQ_IRQ116MON *((volatile uint32_t*)(0x400313D4UL)) +#define FM4_INTREQ_IRQ116MON *((volatile uint32_t*)(0x400313D4UL)) +#define FM_INTREQ_IRQ117MON *((volatile uint32_t*)(0x400313D8UL)) +#define FM4_INTREQ_IRQ117MON *((volatile uint32_t*)(0x400313D8UL)) +#define FM_INTREQ_IRQ118MON *((volatile uint32_t*)(0x400313DCUL)) +#define FM4_INTREQ_IRQ118MON *((volatile uint32_t*)(0x400313DCUL)) +#define FM_INTREQ_IRQ119MON *((volatile uint32_t*)(0x400313E0UL)) +#define FM4_INTREQ_IRQ119MON *((volatile uint32_t*)(0x400313E0UL)) +#define FM_INTREQ_IRQ120MON *((volatile uint32_t*)(0x400313E4UL)) +#define FM4_INTREQ_IRQ120MON *((volatile uint32_t*)(0x400313E4UL)) +#define FM_INTREQ_IRQ121MON *((volatile uint32_t*)(0x400313E8UL)) +#define FM4_INTREQ_IRQ121MON *((volatile uint32_t*)(0x400313E8UL)) +#define FM_INTREQ_IRQ122MON *((volatile uint32_t*)(0x400313ECUL)) +#define FM4_INTREQ_IRQ122MON *((volatile uint32_t*)(0x400313ECUL)) +#define FM_INTREQ_IRQ123MON *((volatile uint32_t*)(0x400313F0UL)) +#define FM4_INTREQ_IRQ123MON *((volatile uint32_t*)(0x400313F0UL)) +#define FM_INTREQ_IRQ124MON *((volatile uint32_t*)(0x400313F4UL)) +#define FM4_INTREQ_IRQ124MON *((volatile uint32_t*)(0x400313F4UL)) +#define FM_INTREQ_IRQ125MON *((volatile uint32_t*)(0x400313F8UL)) +#define FM4_INTREQ_IRQ125MON *((volatile uint32_t*)(0x400313F8UL)) +#define FM_INTREQ_IRQ126MON *((volatile uint32_t*)(0x400313FCUL)) +#define FM4_INTREQ_IRQ126MON *((volatile uint32_t*)(0x400313FCUL)) +#define FM_INTREQ_IRQ127MON *((volatile uint32_t*)(0x40031400UL)) +#define FM4_INTREQ_IRQ127MON *((volatile uint32_t*)(0x40031400UL)) + +/******************************************************************************* +* LSCRP Registers LSCRP +* Register Definition +*******************************************************************************/ +#define FM_LSCRP_LCR_PRSLD *((volatile uint8_t*)(0x4003C000UL)) +#define FM4_LSCRP_LCR_PRSLD *((volatile uint8_t*)(0x4003C000UL)) + +/******************************************************************************* +* LVD Registers LVD +* Register Definition +*******************************************************************************/ +#define FM_LVD_LVD_CTL *((volatile uint8_t*)(0x40035000UL)) +#define FM4_LVD_LVD_CTL *((volatile uint8_t*)(0x40035000UL)) +#define FM_LVD_LVD_STR *((volatile uint8_t*)(0x40035004UL)) +#define FM4_LVD_LVD_STR *((volatile uint8_t*)(0x40035004UL)) +#define FM_LVD_LVD_CLR *((volatile uint8_t*)(0x40035008UL)) +#define FM4_LVD_LVD_CLR *((volatile uint8_t*)(0x40035008UL)) +#define FM_LVD_LVD_RLR *((volatile uint32_t*)(0x4003500CUL)) +#define FM4_LVD_LVD_RLR *((volatile uint32_t*)(0x4003500CUL)) +#define FM_LVD_LVD_STR2 *((volatile uint8_t*)(0x40035010UL)) +#define FM4_LVD_LVD_STR2 *((volatile uint8_t*)(0x40035010UL)) + +/******************************************************************************* +* MFS Registers MFS0 +* Register Definition +*******************************************************************************/ +#define FM_MFS0_CSIO_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_CSIO_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_I2C_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_I2C_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_LIN_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_LIN_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_UART_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_UART_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_CSIO_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_CSIO_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_I2C_IBCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_I2C_IBCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_LIN_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_LIN_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_UART_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_UART_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_CSIO_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_CSIO_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_I2C_IBSR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_I2C_IBSR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_LIN_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_LIN_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_UART_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_UART_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_CSIO_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_CSIO_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_I2C_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_I2C_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_LIN_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_LIN_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_UART_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_UART_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_CSIO_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_CSIO_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_CSIO_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_CSIO_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_I2C_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_I2C_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_I2C_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_I2C_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_LIN_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_LIN_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_LIN_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_LIN_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_UART_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_UART_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_UART_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_UART_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_CSIO_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_CSIO_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_I2C_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_I2C_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_LIN_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_LIN_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_UART_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_UART_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_I2C_ISBA *((volatile uint8_t*)(0x40038010UL)) +#define FM4_MFS0_I2C_ISBA *((volatile uint8_t*)(0x40038010UL)) +#define FM_MFS0_I2C_ISMK *((volatile uint8_t*)(0x40038011UL)) +#define FM4_MFS0_I2C_ISMK *((volatile uint8_t*)(0x40038011UL)) +#define FM_MFS0_CSIO_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_CSIO_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_I2C_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_I2C_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_LIN_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_LIN_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_UART_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_UART_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_I2C_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_I2C_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_LIN_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_LIN_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_UART_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_UART_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_I2C_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_I2C_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_LIN_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_LIN_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_UART_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_UART_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003801CUL)) +#define FM4_MFS0_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003801CUL)) +#define FM_MFS0_I2C_NFCR *((volatile uint8_t*)(0x4003801CUL)) +#define FM4_MFS0_I2C_NFCR *((volatile uint8_t*)(0x4003801CUL)) +#define FM_MFS0_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003801DUL)) +#define FM4_MFS0_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003801DUL)) +#define FM_MFS0_I2C_EIBCR *((volatile uint8_t*)(0x4003801DUL)) +#define FM4_MFS0_I2C_EIBCR *((volatile uint8_t*)(0x4003801DUL)) +#define FM_MFS0_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038020UL)) +#define FM4_MFS0_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038020UL)) +#define FM_MFS0_CSIO_SACSR *((volatile uint16_t*)(0x40038024UL)) +#define FM4_MFS0_CSIO_SACSR *((volatile uint16_t*)(0x40038024UL)) +#define FM_MFS0_CSIO_STMR *((volatile uint16_t*)(0x40038028UL)) +#define FM4_MFS0_CSIO_STMR *((volatile uint16_t*)(0x40038028UL)) +#define FM_MFS0_CSIO_STMCR *((volatile uint16_t*)(0x4003802CUL)) +#define FM4_MFS0_CSIO_STMCR *((volatile uint16_t*)(0x4003802CUL)) +#define FM_MFS0_CSIO_SCSCR *((volatile uint16_t*)(0x40038030UL)) +#define FM4_MFS0_CSIO_SCSCR *((volatile uint16_t*)(0x40038030UL)) +#define FM_MFS0_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038034UL)) +#define FM4_MFS0_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038034UL)) +#define FM_MFS0_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038035UL)) +#define FM4_MFS0_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038035UL)) +#define FM_MFS0_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038038UL)) +#define FM4_MFS0_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038038UL)) +#define FM_MFS0_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003803CUL)) +#define FM4_MFS0_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003803CUL)) +#define FM_MFS0_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003803DUL)) +#define FM4_MFS0_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003803DUL)) +#define FM_MFS0_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038040UL)) +#define FM4_MFS0_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038040UL)) +#define FM_MFS0_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038041UL)) +#define FM4_MFS0_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038041UL)) + +/******************************************************************************* +* MFS Registers MFS1 +* Register Definition +*******************************************************************************/ +#define FM_MFS1_CSIO_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_CSIO_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_I2C_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_I2C_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_LIN_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_LIN_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_UART_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_UART_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_CSIO_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_CSIO_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_I2C_IBCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_I2C_IBCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_LIN_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_LIN_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_UART_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_UART_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_CSIO_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_CSIO_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_I2C_IBSR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_I2C_IBSR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_LIN_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_LIN_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_UART_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_UART_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_CSIO_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_CSIO_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_I2C_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_I2C_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_LIN_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_LIN_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_UART_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_UART_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_CSIO_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_CSIO_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_CSIO_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_CSIO_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_I2C_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_I2C_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_I2C_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_I2C_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_LIN_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_LIN_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_LIN_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_LIN_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_UART_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_UART_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_UART_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_UART_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_CSIO_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_CSIO_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_I2C_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_I2C_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_LIN_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_LIN_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_UART_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_UART_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_I2C_ISBA *((volatile uint8_t*)(0x40038110UL)) +#define FM4_MFS1_I2C_ISBA *((volatile uint8_t*)(0x40038110UL)) +#define FM_MFS1_I2C_ISMK *((volatile uint8_t*)(0x40038111UL)) +#define FM4_MFS1_I2C_ISMK *((volatile uint8_t*)(0x40038111UL)) +#define FM_MFS1_CSIO_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_CSIO_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_I2C_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_I2C_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_LIN_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_LIN_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_UART_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_UART_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_I2C_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_I2C_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_LIN_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_LIN_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_UART_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_UART_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_I2C_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_I2C_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_LIN_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_LIN_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_UART_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_UART_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003811CUL)) +#define FM4_MFS1_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003811CUL)) +#define FM_MFS1_I2C_NFCR *((volatile uint8_t*)(0x4003811CUL)) +#define FM4_MFS1_I2C_NFCR *((volatile uint8_t*)(0x4003811CUL)) +#define FM_MFS1_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003811DUL)) +#define FM4_MFS1_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003811DUL)) +#define FM_MFS1_I2C_EIBCR *((volatile uint8_t*)(0x4003811DUL)) +#define FM4_MFS1_I2C_EIBCR *((volatile uint8_t*)(0x4003811DUL)) +#define FM_MFS1_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038120UL)) +#define FM4_MFS1_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038120UL)) +#define FM_MFS1_CSIO_SACSR *((volatile uint16_t*)(0x40038124UL)) +#define FM4_MFS1_CSIO_SACSR *((volatile uint16_t*)(0x40038124UL)) +#define FM_MFS1_CSIO_STMR *((volatile uint16_t*)(0x40038128UL)) +#define FM4_MFS1_CSIO_STMR *((volatile uint16_t*)(0x40038128UL)) +#define FM_MFS1_CSIO_STMCR *((volatile uint16_t*)(0x4003812CUL)) +#define FM4_MFS1_CSIO_STMCR *((volatile uint16_t*)(0x4003812CUL)) +#define FM_MFS1_CSIO_SCSCR *((volatile uint16_t*)(0x40038130UL)) +#define FM4_MFS1_CSIO_SCSCR *((volatile uint16_t*)(0x40038130UL)) +#define FM_MFS1_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038134UL)) +#define FM4_MFS1_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038134UL)) +#define FM_MFS1_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038135UL)) +#define FM4_MFS1_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038135UL)) +#define FM_MFS1_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038138UL)) +#define FM4_MFS1_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038138UL)) +#define FM_MFS1_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003813CUL)) +#define FM4_MFS1_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003813CUL)) +#define FM_MFS1_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003813DUL)) +#define FM4_MFS1_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003813DUL)) +#define FM_MFS1_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038140UL)) +#define FM4_MFS1_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038140UL)) +#define FM_MFS1_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038141UL)) +#define FM4_MFS1_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038141UL)) + +/******************************************************************************* +* MFS Registers MFS10 +* Register Definition +*******************************************************************************/ +#define FM_MFS10_CSIO_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_CSIO_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_I2C_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_I2C_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_LIN_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_LIN_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_UART_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_UART_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_CSIO_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_CSIO_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_I2C_IBCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_I2C_IBCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_LIN_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_LIN_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_UART_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_UART_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_CSIO_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_CSIO_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_I2C_IBSR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_I2C_IBSR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_LIN_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_LIN_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_UART_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_UART_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_CSIO_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_CSIO_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_I2C_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_I2C_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_LIN_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_LIN_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_UART_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_UART_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_CSIO_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_CSIO_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_CSIO_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_CSIO_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_I2C_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_I2C_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_I2C_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_I2C_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_LIN_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_LIN_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_LIN_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_LIN_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_UART_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_UART_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_UART_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_UART_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_CSIO_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_CSIO_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_I2C_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_I2C_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_LIN_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_LIN_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_UART_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_UART_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_I2C_ISBA *((volatile uint8_t*)(0x40038A10UL)) +#define FM4_MFS10_I2C_ISBA *((volatile uint8_t*)(0x40038A10UL)) +#define FM_MFS10_I2C_ISMK *((volatile uint8_t*)(0x40038A11UL)) +#define FM4_MFS10_I2C_ISMK *((volatile uint8_t*)(0x40038A11UL)) +#define FM_MFS10_CSIO_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_CSIO_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_I2C_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_I2C_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_LIN_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_LIN_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_UART_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_UART_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_I2C_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_I2C_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_LIN_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_LIN_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_UART_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_UART_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_I2C_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_I2C_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_LIN_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_LIN_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_UART_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_UART_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038A1CUL)) +#define FM4_MFS10_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038A1CUL)) +#define FM_MFS10_I2C_NFCR *((volatile uint8_t*)(0x40038A1CUL)) +#define FM4_MFS10_I2C_NFCR *((volatile uint8_t*)(0x40038A1CUL)) +#define FM_MFS10_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038A1DUL)) +#define FM4_MFS10_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038A1DUL)) +#define FM_MFS10_I2C_EIBCR *((volatile uint8_t*)(0x40038A1DUL)) +#define FM4_MFS10_I2C_EIBCR *((volatile uint8_t*)(0x40038A1DUL)) +#define FM_MFS10_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038A20UL)) +#define FM4_MFS10_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038A20UL)) +#define FM_MFS10_CSIO_SACSR *((volatile uint16_t*)(0x40038A24UL)) +#define FM4_MFS10_CSIO_SACSR *((volatile uint16_t*)(0x40038A24UL)) +#define FM_MFS10_CSIO_STMR *((volatile uint16_t*)(0x40038A28UL)) +#define FM4_MFS10_CSIO_STMR *((volatile uint16_t*)(0x40038A28UL)) +#define FM_MFS10_CSIO_STMCR *((volatile uint16_t*)(0x40038A2CUL)) +#define FM4_MFS10_CSIO_STMCR *((volatile uint16_t*)(0x40038A2CUL)) +#define FM_MFS10_CSIO_SCSCR *((volatile uint16_t*)(0x40038A30UL)) +#define FM4_MFS10_CSIO_SCSCR *((volatile uint16_t*)(0x40038A30UL)) +#define FM_MFS10_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038A34UL)) +#define FM4_MFS10_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038A34UL)) +#define FM_MFS10_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038A35UL)) +#define FM4_MFS10_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038A35UL)) +#define FM_MFS10_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038A38UL)) +#define FM4_MFS10_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038A38UL)) +#define FM_MFS10_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038A3CUL)) +#define FM4_MFS10_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038A3CUL)) +#define FM_MFS10_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038A3DUL)) +#define FM4_MFS10_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038A3DUL)) +#define FM_MFS10_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038A40UL)) +#define FM4_MFS10_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038A40UL)) +#define FM_MFS10_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038A41UL)) +#define FM4_MFS10_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038A41UL)) + +/******************************************************************************* +* MFS Registers MFS11 +* Register Definition +*******************************************************************************/ +#define FM_MFS11_CSIO_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_CSIO_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_I2C_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_I2C_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_LIN_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_LIN_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_UART_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_UART_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_CSIO_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_CSIO_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_I2C_IBCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_I2C_IBCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_LIN_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_LIN_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_UART_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_UART_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_CSIO_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_CSIO_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_I2C_IBSR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_I2C_IBSR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_LIN_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_LIN_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_UART_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_UART_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_CSIO_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_CSIO_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_I2C_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_I2C_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_LIN_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_LIN_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_UART_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_UART_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_CSIO_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_CSIO_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_CSIO_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_CSIO_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_I2C_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_I2C_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_I2C_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_I2C_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_LIN_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_LIN_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_LIN_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_LIN_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_UART_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_UART_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_UART_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_UART_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_CSIO_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_CSIO_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_I2C_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_I2C_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_LIN_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_LIN_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_UART_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_UART_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_I2C_ISBA *((volatile uint8_t*)(0x40038B10UL)) +#define FM4_MFS11_I2C_ISBA *((volatile uint8_t*)(0x40038B10UL)) +#define FM_MFS11_I2C_ISMK *((volatile uint8_t*)(0x40038B11UL)) +#define FM4_MFS11_I2C_ISMK *((volatile uint8_t*)(0x40038B11UL)) +#define FM_MFS11_CSIO_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_CSIO_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_I2C_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_I2C_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_LIN_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_LIN_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_UART_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_UART_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_I2C_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_I2C_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_LIN_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_LIN_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_UART_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_UART_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_I2C_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_I2C_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_LIN_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_LIN_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_UART_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_UART_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038B1CUL)) +#define FM4_MFS11_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038B1CUL)) +#define FM_MFS11_I2C_NFCR *((volatile uint8_t*)(0x40038B1CUL)) +#define FM4_MFS11_I2C_NFCR *((volatile uint8_t*)(0x40038B1CUL)) +#define FM_MFS11_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038B1DUL)) +#define FM4_MFS11_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038B1DUL)) +#define FM_MFS11_I2C_EIBCR *((volatile uint8_t*)(0x40038B1DUL)) +#define FM4_MFS11_I2C_EIBCR *((volatile uint8_t*)(0x40038B1DUL)) +#define FM_MFS11_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038B20UL)) +#define FM4_MFS11_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038B20UL)) +#define FM_MFS11_CSIO_SACSR *((volatile uint16_t*)(0x40038B24UL)) +#define FM4_MFS11_CSIO_SACSR *((volatile uint16_t*)(0x40038B24UL)) +#define FM_MFS11_CSIO_STMR *((volatile uint16_t*)(0x40038B28UL)) +#define FM4_MFS11_CSIO_STMR *((volatile uint16_t*)(0x40038B28UL)) +#define FM_MFS11_CSIO_STMCR *((volatile uint16_t*)(0x40038B2CUL)) +#define FM4_MFS11_CSIO_STMCR *((volatile uint16_t*)(0x40038B2CUL)) +#define FM_MFS11_CSIO_SCSCR *((volatile uint16_t*)(0x40038B30UL)) +#define FM4_MFS11_CSIO_SCSCR *((volatile uint16_t*)(0x40038B30UL)) +#define FM_MFS11_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038B34UL)) +#define FM4_MFS11_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038B34UL)) +#define FM_MFS11_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038B35UL)) +#define FM4_MFS11_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038B35UL)) +#define FM_MFS11_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038B38UL)) +#define FM4_MFS11_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038B38UL)) +#define FM_MFS11_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038B3CUL)) +#define FM4_MFS11_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038B3CUL)) +#define FM_MFS11_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038B3DUL)) +#define FM4_MFS11_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038B3DUL)) +#define FM_MFS11_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038B40UL)) +#define FM4_MFS11_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038B40UL)) +#define FM_MFS11_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038B41UL)) +#define FM4_MFS11_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038B41UL)) + +/******************************************************************************* +* MFS Registers MFS12 +* Register Definition +*******************************************************************************/ +#define FM_MFS12_CSIO_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_CSIO_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_I2C_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_I2C_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_LIN_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_LIN_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_UART_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_UART_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_CSIO_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_CSIO_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_I2C_IBCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_I2C_IBCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_LIN_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_LIN_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_UART_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_UART_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_CSIO_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_CSIO_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_I2C_IBSR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_I2C_IBSR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_LIN_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_LIN_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_UART_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_UART_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_CSIO_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_CSIO_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_I2C_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_I2C_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_LIN_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_LIN_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_UART_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_UART_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_CSIO_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_CSIO_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_CSIO_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_CSIO_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_I2C_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_I2C_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_I2C_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_I2C_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_LIN_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_LIN_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_LIN_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_LIN_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_UART_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_UART_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_UART_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_UART_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_CSIO_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_CSIO_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_I2C_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_I2C_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_LIN_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_LIN_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_UART_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_UART_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_I2C_ISBA *((volatile uint8_t*)(0x40038C10UL)) +#define FM4_MFS12_I2C_ISBA *((volatile uint8_t*)(0x40038C10UL)) +#define FM_MFS12_I2C_ISMK *((volatile uint8_t*)(0x40038C11UL)) +#define FM4_MFS12_I2C_ISMK *((volatile uint8_t*)(0x40038C11UL)) +#define FM_MFS12_CSIO_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_CSIO_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_I2C_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_I2C_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_LIN_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_LIN_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_UART_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_UART_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_I2C_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_I2C_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_LIN_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_LIN_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_UART_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_UART_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_I2C_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_I2C_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_LIN_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_LIN_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_UART_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_UART_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038C1CUL)) +#define FM4_MFS12_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038C1CUL)) +#define FM_MFS12_I2C_NFCR *((volatile uint8_t*)(0x40038C1CUL)) +#define FM4_MFS12_I2C_NFCR *((volatile uint8_t*)(0x40038C1CUL)) +#define FM_MFS12_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038C1DUL)) +#define FM4_MFS12_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038C1DUL)) +#define FM_MFS12_I2C_EIBCR *((volatile uint8_t*)(0x40038C1DUL)) +#define FM4_MFS12_I2C_EIBCR *((volatile uint8_t*)(0x40038C1DUL)) +#define FM_MFS12_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038C20UL)) +#define FM4_MFS12_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038C20UL)) +#define FM_MFS12_CSIO_SACSR *((volatile uint16_t*)(0x40038C24UL)) +#define FM4_MFS12_CSIO_SACSR *((volatile uint16_t*)(0x40038C24UL)) +#define FM_MFS12_CSIO_STMR *((volatile uint16_t*)(0x40038C28UL)) +#define FM4_MFS12_CSIO_STMR *((volatile uint16_t*)(0x40038C28UL)) +#define FM_MFS12_CSIO_STMCR *((volatile uint16_t*)(0x40038C2CUL)) +#define FM4_MFS12_CSIO_STMCR *((volatile uint16_t*)(0x40038C2CUL)) +#define FM_MFS12_CSIO_SCSCR *((volatile uint16_t*)(0x40038C30UL)) +#define FM4_MFS12_CSIO_SCSCR *((volatile uint16_t*)(0x40038C30UL)) +#define FM_MFS12_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038C34UL)) +#define FM4_MFS12_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038C34UL)) +#define FM_MFS12_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038C35UL)) +#define FM4_MFS12_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038C35UL)) +#define FM_MFS12_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038C38UL)) +#define FM4_MFS12_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038C38UL)) +#define FM_MFS12_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038C3CUL)) +#define FM4_MFS12_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038C3CUL)) +#define FM_MFS12_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038C3DUL)) +#define FM4_MFS12_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038C3DUL)) +#define FM_MFS12_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038C40UL)) +#define FM4_MFS12_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038C40UL)) +#define FM_MFS12_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038C41UL)) +#define FM4_MFS12_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038C41UL)) + +/******************************************************************************* +* MFS Registers MFS13 +* Register Definition +*******************************************************************************/ +#define FM_MFS13_CSIO_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_CSIO_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_I2C_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_I2C_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_LIN_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_LIN_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_UART_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_UART_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_CSIO_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_CSIO_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_I2C_IBCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_I2C_IBCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_LIN_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_LIN_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_UART_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_UART_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_CSIO_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_CSIO_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_I2C_IBSR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_I2C_IBSR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_LIN_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_LIN_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_UART_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_UART_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_CSIO_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_CSIO_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_I2C_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_I2C_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_LIN_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_LIN_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_UART_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_UART_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_CSIO_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_CSIO_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_CSIO_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_CSIO_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_I2C_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_I2C_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_I2C_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_I2C_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_LIN_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_LIN_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_LIN_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_LIN_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_UART_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_UART_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_UART_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_UART_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_CSIO_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_CSIO_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_I2C_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_I2C_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_LIN_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_LIN_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_UART_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_UART_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_I2C_ISBA *((volatile uint8_t*)(0x40038D10UL)) +#define FM4_MFS13_I2C_ISBA *((volatile uint8_t*)(0x40038D10UL)) +#define FM_MFS13_I2C_ISMK *((volatile uint8_t*)(0x40038D11UL)) +#define FM4_MFS13_I2C_ISMK *((volatile uint8_t*)(0x40038D11UL)) +#define FM_MFS13_CSIO_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_CSIO_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_I2C_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_I2C_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_LIN_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_LIN_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_UART_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_UART_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_I2C_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_I2C_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_LIN_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_LIN_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_UART_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_UART_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_I2C_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_I2C_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_LIN_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_LIN_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_UART_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_UART_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038D1CUL)) +#define FM4_MFS13_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038D1CUL)) +#define FM_MFS13_I2C_NFCR *((volatile uint8_t*)(0x40038D1CUL)) +#define FM4_MFS13_I2C_NFCR *((volatile uint8_t*)(0x40038D1CUL)) +#define FM_MFS13_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038D1DUL)) +#define FM4_MFS13_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038D1DUL)) +#define FM_MFS13_I2C_EIBCR *((volatile uint8_t*)(0x40038D1DUL)) +#define FM4_MFS13_I2C_EIBCR *((volatile uint8_t*)(0x40038D1DUL)) +#define FM_MFS13_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038D20UL)) +#define FM4_MFS13_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038D20UL)) +#define FM_MFS13_CSIO_SACSR *((volatile uint16_t*)(0x40038D24UL)) +#define FM4_MFS13_CSIO_SACSR *((volatile uint16_t*)(0x40038D24UL)) +#define FM_MFS13_CSIO_STMR *((volatile uint16_t*)(0x40038D28UL)) +#define FM4_MFS13_CSIO_STMR *((volatile uint16_t*)(0x40038D28UL)) +#define FM_MFS13_CSIO_STMCR *((volatile uint16_t*)(0x40038D2CUL)) +#define FM4_MFS13_CSIO_STMCR *((volatile uint16_t*)(0x40038D2CUL)) +#define FM_MFS13_CSIO_SCSCR *((volatile uint16_t*)(0x40038D30UL)) +#define FM4_MFS13_CSIO_SCSCR *((volatile uint16_t*)(0x40038D30UL)) +#define FM_MFS13_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038D34UL)) +#define FM4_MFS13_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038D34UL)) +#define FM_MFS13_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038D35UL)) +#define FM4_MFS13_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038D35UL)) +#define FM_MFS13_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038D38UL)) +#define FM4_MFS13_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038D38UL)) +#define FM_MFS13_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038D3CUL)) +#define FM4_MFS13_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038D3CUL)) +#define FM_MFS13_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038D3DUL)) +#define FM4_MFS13_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038D3DUL)) +#define FM_MFS13_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038D40UL)) +#define FM4_MFS13_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038D40UL)) +#define FM_MFS13_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038D41UL)) +#define FM4_MFS13_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038D41UL)) + +/******************************************************************************* +* MFS Registers MFS14 +* Register Definition +*******************************************************************************/ +#define FM_MFS14_CSIO_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_CSIO_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_I2C_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_I2C_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_LIN_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_LIN_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_UART_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_UART_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_CSIO_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_CSIO_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_I2C_IBCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_I2C_IBCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_LIN_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_LIN_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_UART_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_UART_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_CSIO_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_CSIO_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_I2C_IBSR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_I2C_IBSR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_LIN_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_LIN_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_UART_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_UART_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_CSIO_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_CSIO_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_I2C_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_I2C_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_LIN_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_LIN_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_UART_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_UART_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_CSIO_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_CSIO_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_CSIO_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_CSIO_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_I2C_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_I2C_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_I2C_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_I2C_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_LIN_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_LIN_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_LIN_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_LIN_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_UART_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_UART_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_UART_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_UART_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_CSIO_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_CSIO_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_I2C_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_I2C_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_LIN_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_LIN_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_UART_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_UART_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_I2C_ISBA *((volatile uint8_t*)(0x40038E10UL)) +#define FM4_MFS14_I2C_ISBA *((volatile uint8_t*)(0x40038E10UL)) +#define FM_MFS14_I2C_ISMK *((volatile uint8_t*)(0x40038E11UL)) +#define FM4_MFS14_I2C_ISMK *((volatile uint8_t*)(0x40038E11UL)) +#define FM_MFS14_CSIO_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_CSIO_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_I2C_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_I2C_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_LIN_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_LIN_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_UART_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_UART_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_I2C_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_I2C_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_LIN_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_LIN_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_UART_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_UART_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_I2C_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_I2C_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_LIN_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_LIN_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_UART_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_UART_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038E1CUL)) +#define FM4_MFS14_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038E1CUL)) +#define FM_MFS14_I2C_NFCR *((volatile uint8_t*)(0x40038E1CUL)) +#define FM4_MFS14_I2C_NFCR *((volatile uint8_t*)(0x40038E1CUL)) +#define FM_MFS14_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038E1DUL)) +#define FM4_MFS14_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038E1DUL)) +#define FM_MFS14_I2C_EIBCR *((volatile uint8_t*)(0x40038E1DUL)) +#define FM4_MFS14_I2C_EIBCR *((volatile uint8_t*)(0x40038E1DUL)) +#define FM_MFS14_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038E20UL)) +#define FM4_MFS14_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038E20UL)) +#define FM_MFS14_CSIO_SACSR *((volatile uint16_t*)(0x40038E24UL)) +#define FM4_MFS14_CSIO_SACSR *((volatile uint16_t*)(0x40038E24UL)) +#define FM_MFS14_CSIO_STMR *((volatile uint16_t*)(0x40038E28UL)) +#define FM4_MFS14_CSIO_STMR *((volatile uint16_t*)(0x40038E28UL)) +#define FM_MFS14_CSIO_STMCR *((volatile uint16_t*)(0x40038E2CUL)) +#define FM4_MFS14_CSIO_STMCR *((volatile uint16_t*)(0x40038E2CUL)) +#define FM_MFS14_CSIO_SCSCR *((volatile uint16_t*)(0x40038E30UL)) +#define FM4_MFS14_CSIO_SCSCR *((volatile uint16_t*)(0x40038E30UL)) +#define FM_MFS14_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038E34UL)) +#define FM4_MFS14_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038E34UL)) +#define FM_MFS14_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038E35UL)) +#define FM4_MFS14_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038E35UL)) +#define FM_MFS14_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038E38UL)) +#define FM4_MFS14_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038E38UL)) +#define FM_MFS14_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038E3CUL)) +#define FM4_MFS14_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038E3CUL)) +#define FM_MFS14_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038E3DUL)) +#define FM4_MFS14_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038E3DUL)) +#define FM_MFS14_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038E40UL)) +#define FM4_MFS14_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038E40UL)) +#define FM_MFS14_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038E41UL)) +#define FM4_MFS14_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038E41UL)) + +/******************************************************************************* +* MFS Registers MFS15 +* Register Definition +*******************************************************************************/ +#define FM_MFS15_CSIO_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_CSIO_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_I2C_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_I2C_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_LIN_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_LIN_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_UART_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_UART_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_CSIO_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_CSIO_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_I2C_IBCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_I2C_IBCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_LIN_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_LIN_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_UART_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_UART_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_CSIO_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_CSIO_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_I2C_IBSR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_I2C_IBSR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_LIN_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_LIN_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_UART_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_UART_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_CSIO_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_CSIO_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_I2C_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_I2C_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_LIN_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_LIN_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_UART_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_UART_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_CSIO_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_CSIO_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_CSIO_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_CSIO_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_I2C_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_I2C_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_I2C_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_I2C_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_LIN_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_LIN_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_LIN_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_LIN_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_UART_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_UART_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_UART_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_UART_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_CSIO_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_CSIO_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_I2C_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_I2C_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_LIN_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_LIN_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_UART_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_UART_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_I2C_ISBA *((volatile uint8_t*)(0x40038F10UL)) +#define FM4_MFS15_I2C_ISBA *((volatile uint8_t*)(0x40038F10UL)) +#define FM_MFS15_I2C_ISMK *((volatile uint8_t*)(0x40038F11UL)) +#define FM4_MFS15_I2C_ISMK *((volatile uint8_t*)(0x40038F11UL)) +#define FM_MFS15_CSIO_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_CSIO_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_I2C_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_I2C_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_LIN_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_LIN_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_UART_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_UART_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_I2C_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_I2C_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_LIN_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_LIN_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_UART_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_UART_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_I2C_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_I2C_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_LIN_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_LIN_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_UART_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_UART_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038F1CUL)) +#define FM4_MFS15_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038F1CUL)) +#define FM_MFS15_I2C_NFCR *((volatile uint8_t*)(0x40038F1CUL)) +#define FM4_MFS15_I2C_NFCR *((volatile uint8_t*)(0x40038F1CUL)) +#define FM_MFS15_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038F1DUL)) +#define FM4_MFS15_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038F1DUL)) +#define FM_MFS15_I2C_EIBCR *((volatile uint8_t*)(0x40038F1DUL)) +#define FM4_MFS15_I2C_EIBCR *((volatile uint8_t*)(0x40038F1DUL)) +#define FM_MFS15_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038F20UL)) +#define FM4_MFS15_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038F20UL)) +#define FM_MFS15_CSIO_SACSR *((volatile uint16_t*)(0x40038F24UL)) +#define FM4_MFS15_CSIO_SACSR *((volatile uint16_t*)(0x40038F24UL)) +#define FM_MFS15_CSIO_STMR *((volatile uint16_t*)(0x40038F28UL)) +#define FM4_MFS15_CSIO_STMR *((volatile uint16_t*)(0x40038F28UL)) +#define FM_MFS15_CSIO_STMCR *((volatile uint16_t*)(0x40038F2CUL)) +#define FM4_MFS15_CSIO_STMCR *((volatile uint16_t*)(0x40038F2CUL)) +#define FM_MFS15_CSIO_SCSCR *((volatile uint16_t*)(0x40038F30UL)) +#define FM4_MFS15_CSIO_SCSCR *((volatile uint16_t*)(0x40038F30UL)) +#define FM_MFS15_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038F34UL)) +#define FM4_MFS15_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038F34UL)) +#define FM_MFS15_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038F35UL)) +#define FM4_MFS15_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038F35UL)) +#define FM_MFS15_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038F38UL)) +#define FM4_MFS15_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038F38UL)) +#define FM_MFS15_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038F3CUL)) +#define FM4_MFS15_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038F3CUL)) +#define FM_MFS15_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038F3DUL)) +#define FM4_MFS15_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038F3DUL)) +#define FM_MFS15_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038F40UL)) +#define FM4_MFS15_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038F40UL)) +#define FM_MFS15_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038F41UL)) +#define FM4_MFS15_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038F41UL)) + +/******************************************************************************* +* MFS Registers MFS2 +* Register Definition +*******************************************************************************/ +#define FM_MFS2_CSIO_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_CSIO_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_I2C_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_I2C_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_LIN_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_LIN_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_UART_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_UART_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_CSIO_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_CSIO_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_I2C_IBCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_I2C_IBCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_LIN_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_LIN_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_UART_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_UART_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_CSIO_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_CSIO_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_I2C_IBSR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_I2C_IBSR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_LIN_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_LIN_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_UART_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_UART_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_CSIO_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_CSIO_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_I2C_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_I2C_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_LIN_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_LIN_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_UART_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_UART_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_CSIO_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_CSIO_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_CSIO_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_CSIO_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_I2C_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_I2C_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_I2C_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_I2C_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_LIN_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_LIN_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_LIN_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_LIN_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_UART_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_UART_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_UART_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_UART_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_CSIO_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_CSIO_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_I2C_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_I2C_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_LIN_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_LIN_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_UART_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_UART_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_I2C_ISBA *((volatile uint8_t*)(0x40038210UL)) +#define FM4_MFS2_I2C_ISBA *((volatile uint8_t*)(0x40038210UL)) +#define FM_MFS2_I2C_ISMK *((volatile uint8_t*)(0x40038211UL)) +#define FM4_MFS2_I2C_ISMK *((volatile uint8_t*)(0x40038211UL)) +#define FM_MFS2_CSIO_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_CSIO_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_I2C_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_I2C_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_LIN_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_LIN_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_UART_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_UART_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_I2C_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_I2C_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_LIN_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_LIN_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_UART_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_UART_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_I2C_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_I2C_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_LIN_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_LIN_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_UART_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_UART_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003821CUL)) +#define FM4_MFS2_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003821CUL)) +#define FM_MFS2_I2C_NFCR *((volatile uint8_t*)(0x4003821CUL)) +#define FM4_MFS2_I2C_NFCR *((volatile uint8_t*)(0x4003821CUL)) +#define FM_MFS2_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003821DUL)) +#define FM4_MFS2_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003821DUL)) +#define FM_MFS2_I2C_EIBCR *((volatile uint8_t*)(0x4003821DUL)) +#define FM4_MFS2_I2C_EIBCR *((volatile uint8_t*)(0x4003821DUL)) +#define FM_MFS2_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038220UL)) +#define FM4_MFS2_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038220UL)) +#define FM_MFS2_CSIO_SACSR *((volatile uint16_t*)(0x40038224UL)) +#define FM4_MFS2_CSIO_SACSR *((volatile uint16_t*)(0x40038224UL)) +#define FM_MFS2_CSIO_STMR *((volatile uint16_t*)(0x40038228UL)) +#define FM4_MFS2_CSIO_STMR *((volatile uint16_t*)(0x40038228UL)) +#define FM_MFS2_CSIO_STMCR *((volatile uint16_t*)(0x4003822CUL)) +#define FM4_MFS2_CSIO_STMCR *((volatile uint16_t*)(0x4003822CUL)) +#define FM_MFS2_CSIO_SCSCR *((volatile uint16_t*)(0x40038230UL)) +#define FM4_MFS2_CSIO_SCSCR *((volatile uint16_t*)(0x40038230UL)) +#define FM_MFS2_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038234UL)) +#define FM4_MFS2_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038234UL)) +#define FM_MFS2_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038235UL)) +#define FM4_MFS2_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038235UL)) +#define FM_MFS2_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038238UL)) +#define FM4_MFS2_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038238UL)) +#define FM_MFS2_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003823CUL)) +#define FM4_MFS2_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003823CUL)) +#define FM_MFS2_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003823DUL)) +#define FM4_MFS2_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003823DUL)) +#define FM_MFS2_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038240UL)) +#define FM4_MFS2_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038240UL)) +#define FM_MFS2_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038241UL)) +#define FM4_MFS2_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038241UL)) + +/******************************************************************************* +* MFS Registers MFS3 +* Register Definition +*******************************************************************************/ +#define FM_MFS3_CSIO_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_CSIO_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_I2C_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_I2C_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_LIN_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_LIN_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_UART_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_UART_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_CSIO_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_CSIO_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_I2C_IBCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_I2C_IBCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_LIN_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_LIN_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_UART_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_UART_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_CSIO_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_CSIO_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_I2C_IBSR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_I2C_IBSR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_LIN_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_LIN_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_UART_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_UART_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_CSIO_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_CSIO_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_I2C_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_I2C_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_LIN_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_LIN_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_UART_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_UART_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_CSIO_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_CSIO_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_CSIO_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_CSIO_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_I2C_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_I2C_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_I2C_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_I2C_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_LIN_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_LIN_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_LIN_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_LIN_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_UART_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_UART_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_UART_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_UART_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_CSIO_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_CSIO_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_I2C_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_I2C_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_LIN_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_LIN_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_UART_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_UART_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_I2C_ISBA *((volatile uint8_t*)(0x40038310UL)) +#define FM4_MFS3_I2C_ISBA *((volatile uint8_t*)(0x40038310UL)) +#define FM_MFS3_I2C_ISMK *((volatile uint8_t*)(0x40038311UL)) +#define FM4_MFS3_I2C_ISMK *((volatile uint8_t*)(0x40038311UL)) +#define FM_MFS3_CSIO_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_CSIO_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_I2C_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_I2C_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_LIN_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_LIN_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_UART_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_UART_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_I2C_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_I2C_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_LIN_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_LIN_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_UART_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_UART_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_I2C_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_I2C_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_LIN_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_LIN_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_UART_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_UART_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003831CUL)) +#define FM4_MFS3_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003831CUL)) +#define FM_MFS3_I2C_NFCR *((volatile uint8_t*)(0x4003831CUL)) +#define FM4_MFS3_I2C_NFCR *((volatile uint8_t*)(0x4003831CUL)) +#define FM_MFS3_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003831DUL)) +#define FM4_MFS3_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003831DUL)) +#define FM_MFS3_I2C_EIBCR *((volatile uint8_t*)(0x4003831DUL)) +#define FM4_MFS3_I2C_EIBCR *((volatile uint8_t*)(0x4003831DUL)) +#define FM_MFS3_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038320UL)) +#define FM4_MFS3_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038320UL)) +#define FM_MFS3_CSIO_SACSR *((volatile uint16_t*)(0x40038324UL)) +#define FM4_MFS3_CSIO_SACSR *((volatile uint16_t*)(0x40038324UL)) +#define FM_MFS3_CSIO_STMR *((volatile uint16_t*)(0x40038328UL)) +#define FM4_MFS3_CSIO_STMR *((volatile uint16_t*)(0x40038328UL)) +#define FM_MFS3_CSIO_STMCR *((volatile uint16_t*)(0x4003832CUL)) +#define FM4_MFS3_CSIO_STMCR *((volatile uint16_t*)(0x4003832CUL)) +#define FM_MFS3_CSIO_SCSCR *((volatile uint16_t*)(0x40038330UL)) +#define FM4_MFS3_CSIO_SCSCR *((volatile uint16_t*)(0x40038330UL)) +#define FM_MFS3_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038334UL)) +#define FM4_MFS3_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038334UL)) +#define FM_MFS3_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038335UL)) +#define FM4_MFS3_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038335UL)) +#define FM_MFS3_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038338UL)) +#define FM4_MFS3_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038338UL)) +#define FM_MFS3_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003833CUL)) +#define FM4_MFS3_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003833CUL)) +#define FM_MFS3_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003833DUL)) +#define FM4_MFS3_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003833DUL)) +#define FM_MFS3_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038340UL)) +#define FM4_MFS3_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038340UL)) +#define FM_MFS3_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038341UL)) +#define FM4_MFS3_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038341UL)) + +/******************************************************************************* +* MFS Registers MFS4 +* Register Definition +*******************************************************************************/ +#define FM_MFS4_CSIO_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_CSIO_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_I2C_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_I2C_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_LIN_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_LIN_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_UART_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_UART_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_CSIO_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_CSIO_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_I2C_IBCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_I2C_IBCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_LIN_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_LIN_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_UART_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_UART_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_CSIO_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_CSIO_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_I2C_IBSR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_I2C_IBSR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_LIN_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_LIN_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_UART_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_UART_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_CSIO_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_CSIO_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_I2C_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_I2C_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_LIN_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_LIN_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_UART_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_UART_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_CSIO_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_CSIO_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_CSIO_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_CSIO_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_I2C_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_I2C_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_I2C_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_I2C_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_LIN_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_LIN_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_LIN_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_LIN_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_UART_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_UART_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_UART_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_UART_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_CSIO_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_CSIO_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_I2C_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_I2C_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_LIN_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_LIN_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_UART_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_UART_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_I2C_ISBA *((volatile uint8_t*)(0x40038410UL)) +#define FM4_MFS4_I2C_ISBA *((volatile uint8_t*)(0x40038410UL)) +#define FM_MFS4_I2C_ISMK *((volatile uint8_t*)(0x40038411UL)) +#define FM4_MFS4_I2C_ISMK *((volatile uint8_t*)(0x40038411UL)) +#define FM_MFS4_CSIO_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_CSIO_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_I2C_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_I2C_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_LIN_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_LIN_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_UART_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_UART_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_I2C_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_I2C_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_LIN_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_LIN_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_UART_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_UART_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_I2C_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_I2C_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_LIN_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_LIN_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_UART_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_UART_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003841CUL)) +#define FM4_MFS4_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003841CUL)) +#define FM_MFS4_I2C_NFCR *((volatile uint8_t*)(0x4003841CUL)) +#define FM4_MFS4_I2C_NFCR *((volatile uint8_t*)(0x4003841CUL)) +#define FM_MFS4_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003841DUL)) +#define FM4_MFS4_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003841DUL)) +#define FM_MFS4_I2C_EIBCR *((volatile uint8_t*)(0x4003841DUL)) +#define FM4_MFS4_I2C_EIBCR *((volatile uint8_t*)(0x4003841DUL)) +#define FM_MFS4_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038420UL)) +#define FM4_MFS4_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038420UL)) +#define FM_MFS4_CSIO_SACSR *((volatile uint16_t*)(0x40038424UL)) +#define FM4_MFS4_CSIO_SACSR *((volatile uint16_t*)(0x40038424UL)) +#define FM_MFS4_CSIO_STMR *((volatile uint16_t*)(0x40038428UL)) +#define FM4_MFS4_CSIO_STMR *((volatile uint16_t*)(0x40038428UL)) +#define FM_MFS4_CSIO_STMCR *((volatile uint16_t*)(0x4003842CUL)) +#define FM4_MFS4_CSIO_STMCR *((volatile uint16_t*)(0x4003842CUL)) +#define FM_MFS4_CSIO_SCSCR *((volatile uint16_t*)(0x40038430UL)) +#define FM4_MFS4_CSIO_SCSCR *((volatile uint16_t*)(0x40038430UL)) +#define FM_MFS4_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038434UL)) +#define FM4_MFS4_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038434UL)) +#define FM_MFS4_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038435UL)) +#define FM4_MFS4_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038435UL)) +#define FM_MFS4_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038438UL)) +#define FM4_MFS4_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038438UL)) +#define FM_MFS4_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003843CUL)) +#define FM4_MFS4_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003843CUL)) +#define FM_MFS4_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003843DUL)) +#define FM4_MFS4_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003843DUL)) +#define FM_MFS4_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038440UL)) +#define FM4_MFS4_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038440UL)) +#define FM_MFS4_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038441UL)) +#define FM4_MFS4_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038441UL)) + +/******************************************************************************* +* MFS Registers MFS5 +* Register Definition +*******************************************************************************/ +#define FM_MFS5_CSIO_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_CSIO_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_I2C_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_I2C_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_LIN_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_LIN_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_UART_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_UART_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_CSIO_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_CSIO_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_I2C_IBCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_I2C_IBCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_LIN_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_LIN_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_UART_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_UART_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_CSIO_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_CSIO_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_I2C_IBSR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_I2C_IBSR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_LIN_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_LIN_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_UART_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_UART_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_CSIO_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_CSIO_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_I2C_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_I2C_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_LIN_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_LIN_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_UART_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_UART_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_CSIO_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_CSIO_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_CSIO_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_CSIO_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_I2C_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_I2C_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_I2C_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_I2C_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_LIN_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_LIN_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_LIN_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_LIN_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_UART_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_UART_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_UART_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_UART_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_CSIO_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_CSIO_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_I2C_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_I2C_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_LIN_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_LIN_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_UART_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_UART_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_I2C_ISBA *((volatile uint8_t*)(0x40038510UL)) +#define FM4_MFS5_I2C_ISBA *((volatile uint8_t*)(0x40038510UL)) +#define FM_MFS5_I2C_ISMK *((volatile uint8_t*)(0x40038511UL)) +#define FM4_MFS5_I2C_ISMK *((volatile uint8_t*)(0x40038511UL)) +#define FM_MFS5_CSIO_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_CSIO_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_I2C_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_I2C_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_LIN_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_LIN_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_UART_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_UART_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_I2C_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_I2C_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_LIN_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_LIN_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_UART_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_UART_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_I2C_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_I2C_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_LIN_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_LIN_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_UART_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_UART_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003851CUL)) +#define FM4_MFS5_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003851CUL)) +#define FM_MFS5_I2C_NFCR *((volatile uint8_t*)(0x4003851CUL)) +#define FM4_MFS5_I2C_NFCR *((volatile uint8_t*)(0x4003851CUL)) +#define FM_MFS5_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003851DUL)) +#define FM4_MFS5_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003851DUL)) +#define FM_MFS5_I2C_EIBCR *((volatile uint8_t*)(0x4003851DUL)) +#define FM4_MFS5_I2C_EIBCR *((volatile uint8_t*)(0x4003851DUL)) +#define FM_MFS5_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038520UL)) +#define FM4_MFS5_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038520UL)) +#define FM_MFS5_CSIO_SACSR *((volatile uint16_t*)(0x40038524UL)) +#define FM4_MFS5_CSIO_SACSR *((volatile uint16_t*)(0x40038524UL)) +#define FM_MFS5_CSIO_STMR *((volatile uint16_t*)(0x40038528UL)) +#define FM4_MFS5_CSIO_STMR *((volatile uint16_t*)(0x40038528UL)) +#define FM_MFS5_CSIO_STMCR *((volatile uint16_t*)(0x4003852CUL)) +#define FM4_MFS5_CSIO_STMCR *((volatile uint16_t*)(0x4003852CUL)) +#define FM_MFS5_CSIO_SCSCR *((volatile uint16_t*)(0x40038530UL)) +#define FM4_MFS5_CSIO_SCSCR *((volatile uint16_t*)(0x40038530UL)) +#define FM_MFS5_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038534UL)) +#define FM4_MFS5_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038534UL)) +#define FM_MFS5_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038535UL)) +#define FM4_MFS5_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038535UL)) +#define FM_MFS5_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038538UL)) +#define FM4_MFS5_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038538UL)) +#define FM_MFS5_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003853CUL)) +#define FM4_MFS5_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003853CUL)) +#define FM_MFS5_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003853DUL)) +#define FM4_MFS5_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003853DUL)) +#define FM_MFS5_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038540UL)) +#define FM4_MFS5_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038540UL)) +#define FM_MFS5_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038541UL)) +#define FM4_MFS5_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038541UL)) + +/******************************************************************************* +* MFS Registers MFS6 +* Register Definition +*******************************************************************************/ +#define FM_MFS6_CSIO_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_CSIO_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_I2C_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_I2C_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_LIN_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_LIN_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_UART_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_UART_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_CSIO_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_CSIO_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_I2C_IBCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_I2C_IBCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_LIN_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_LIN_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_UART_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_UART_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_CSIO_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_CSIO_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_I2C_IBSR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_I2C_IBSR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_LIN_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_LIN_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_UART_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_UART_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_CSIO_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_CSIO_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_I2C_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_I2C_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_LIN_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_LIN_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_UART_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_UART_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_CSIO_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_CSIO_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_CSIO_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_CSIO_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_I2C_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_I2C_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_I2C_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_I2C_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_LIN_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_LIN_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_LIN_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_LIN_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_UART_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_UART_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_UART_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_UART_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_CSIO_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_CSIO_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_I2C_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_I2C_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_LIN_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_LIN_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_UART_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_UART_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_I2C_ISBA *((volatile uint8_t*)(0x40038610UL)) +#define FM4_MFS6_I2C_ISBA *((volatile uint8_t*)(0x40038610UL)) +#define FM_MFS6_I2C_ISMK *((volatile uint8_t*)(0x40038611UL)) +#define FM4_MFS6_I2C_ISMK *((volatile uint8_t*)(0x40038611UL)) +#define FM_MFS6_CSIO_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_CSIO_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_I2C_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_I2C_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_LIN_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_LIN_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_UART_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_UART_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_I2C_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_I2C_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_LIN_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_LIN_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_UART_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_UART_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_I2C_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_I2C_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_LIN_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_LIN_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_UART_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_UART_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003861CUL)) +#define FM4_MFS6_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003861CUL)) +#define FM_MFS6_I2C_NFCR *((volatile uint8_t*)(0x4003861CUL)) +#define FM4_MFS6_I2C_NFCR *((volatile uint8_t*)(0x4003861CUL)) +#define FM_MFS6_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003861DUL)) +#define FM4_MFS6_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003861DUL)) +#define FM_MFS6_I2C_EIBCR *((volatile uint8_t*)(0x4003861DUL)) +#define FM4_MFS6_I2C_EIBCR *((volatile uint8_t*)(0x4003861DUL)) +#define FM_MFS6_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038620UL)) +#define FM4_MFS6_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038620UL)) +#define FM_MFS6_CSIO_SACSR *((volatile uint16_t*)(0x40038624UL)) +#define FM4_MFS6_CSIO_SACSR *((volatile uint16_t*)(0x40038624UL)) +#define FM_MFS6_CSIO_STMR *((volatile uint16_t*)(0x40038628UL)) +#define FM4_MFS6_CSIO_STMR *((volatile uint16_t*)(0x40038628UL)) +#define FM_MFS6_CSIO_STMCR *((volatile uint16_t*)(0x4003862CUL)) +#define FM4_MFS6_CSIO_STMCR *((volatile uint16_t*)(0x4003862CUL)) +#define FM_MFS6_CSIO_SCSCR *((volatile uint16_t*)(0x40038630UL)) +#define FM4_MFS6_CSIO_SCSCR *((volatile uint16_t*)(0x40038630UL)) +#define FM_MFS6_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038634UL)) +#define FM4_MFS6_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038634UL)) +#define FM_MFS6_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038635UL)) +#define FM4_MFS6_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038635UL)) +#define FM_MFS6_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038638UL)) +#define FM4_MFS6_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038638UL)) +#define FM_MFS6_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003863CUL)) +#define FM4_MFS6_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003863CUL)) +#define FM_MFS6_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003863DUL)) +#define FM4_MFS6_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003863DUL)) +#define FM_MFS6_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038640UL)) +#define FM4_MFS6_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038640UL)) +#define FM_MFS6_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038641UL)) +#define FM4_MFS6_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038641UL)) + +/******************************************************************************* +* MFS Registers MFS7 +* Register Definition +*******************************************************************************/ +#define FM_MFS7_CSIO_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_CSIO_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_I2C_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_I2C_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_LIN_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_LIN_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_UART_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_UART_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_CSIO_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_CSIO_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_I2C_IBCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_I2C_IBCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_LIN_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_LIN_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_UART_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_UART_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_CSIO_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_CSIO_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_I2C_IBSR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_I2C_IBSR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_LIN_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_LIN_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_UART_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_UART_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_CSIO_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_CSIO_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_I2C_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_I2C_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_LIN_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_LIN_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_UART_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_UART_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_CSIO_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_CSIO_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_CSIO_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_CSIO_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_I2C_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_I2C_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_I2C_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_I2C_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_LIN_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_LIN_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_LIN_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_LIN_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_UART_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_UART_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_UART_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_UART_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_CSIO_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_CSIO_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_I2C_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_I2C_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_LIN_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_LIN_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_UART_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_UART_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_I2C_ISBA *((volatile uint8_t*)(0x40038710UL)) +#define FM4_MFS7_I2C_ISBA *((volatile uint8_t*)(0x40038710UL)) +#define FM_MFS7_I2C_ISMK *((volatile uint8_t*)(0x40038711UL)) +#define FM4_MFS7_I2C_ISMK *((volatile uint8_t*)(0x40038711UL)) +#define FM_MFS7_CSIO_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_CSIO_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_I2C_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_I2C_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_LIN_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_LIN_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_UART_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_UART_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_I2C_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_I2C_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_LIN_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_LIN_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_UART_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_UART_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_I2C_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_I2C_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_LIN_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_LIN_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_UART_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_UART_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003871CUL)) +#define FM4_MFS7_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003871CUL)) +#define FM_MFS7_I2C_NFCR *((volatile uint8_t*)(0x4003871CUL)) +#define FM4_MFS7_I2C_NFCR *((volatile uint8_t*)(0x4003871CUL)) +#define FM_MFS7_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003871DUL)) +#define FM4_MFS7_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003871DUL)) +#define FM_MFS7_I2C_EIBCR *((volatile uint8_t*)(0x4003871DUL)) +#define FM4_MFS7_I2C_EIBCR *((volatile uint8_t*)(0x4003871DUL)) +#define FM_MFS7_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038720UL)) +#define FM4_MFS7_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038720UL)) +#define FM_MFS7_CSIO_SACSR *((volatile uint16_t*)(0x40038724UL)) +#define FM4_MFS7_CSIO_SACSR *((volatile uint16_t*)(0x40038724UL)) +#define FM_MFS7_CSIO_STMR *((volatile uint16_t*)(0x40038728UL)) +#define FM4_MFS7_CSIO_STMR *((volatile uint16_t*)(0x40038728UL)) +#define FM_MFS7_CSIO_STMCR *((volatile uint16_t*)(0x4003872CUL)) +#define FM4_MFS7_CSIO_STMCR *((volatile uint16_t*)(0x4003872CUL)) +#define FM_MFS7_CSIO_SCSCR *((volatile uint16_t*)(0x40038730UL)) +#define FM4_MFS7_CSIO_SCSCR *((volatile uint16_t*)(0x40038730UL)) +#define FM_MFS7_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038734UL)) +#define FM4_MFS7_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038734UL)) +#define FM_MFS7_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038735UL)) +#define FM4_MFS7_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038735UL)) +#define FM_MFS7_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038738UL)) +#define FM4_MFS7_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038738UL)) +#define FM_MFS7_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003873CUL)) +#define FM4_MFS7_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003873CUL)) +#define FM_MFS7_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003873DUL)) +#define FM4_MFS7_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003873DUL)) +#define FM_MFS7_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038740UL)) +#define FM4_MFS7_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038740UL)) +#define FM_MFS7_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038741UL)) +#define FM4_MFS7_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038741UL)) + +/******************************************************************************* +* MFS Registers MFS8 +* Register Definition +*******************************************************************************/ +#define FM_MFS8_CSIO_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_CSIO_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_I2C_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_I2C_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_LIN_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_LIN_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_UART_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_UART_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_CSIO_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_CSIO_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_I2C_IBCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_I2C_IBCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_LIN_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_LIN_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_UART_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_UART_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_CSIO_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_CSIO_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_I2C_IBSR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_I2C_IBSR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_LIN_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_LIN_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_UART_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_UART_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_CSIO_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_CSIO_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_I2C_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_I2C_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_LIN_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_LIN_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_UART_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_UART_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_CSIO_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_CSIO_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_CSIO_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_CSIO_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_I2C_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_I2C_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_I2C_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_I2C_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_LIN_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_LIN_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_LIN_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_LIN_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_UART_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_UART_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_UART_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_UART_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_CSIO_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_CSIO_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_I2C_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_I2C_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_LIN_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_LIN_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_UART_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_UART_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_I2C_ISBA *((volatile uint8_t*)(0x40038810UL)) +#define FM4_MFS8_I2C_ISBA *((volatile uint8_t*)(0x40038810UL)) +#define FM_MFS8_I2C_ISMK *((volatile uint8_t*)(0x40038811UL)) +#define FM4_MFS8_I2C_ISMK *((volatile uint8_t*)(0x40038811UL)) +#define FM_MFS8_CSIO_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_CSIO_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_I2C_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_I2C_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_LIN_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_LIN_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_UART_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_UART_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_I2C_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_I2C_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_LIN_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_LIN_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_UART_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_UART_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_I2C_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_I2C_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_LIN_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_LIN_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_UART_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_UART_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003881CUL)) +#define FM4_MFS8_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003881CUL)) +#define FM_MFS8_I2C_NFCR *((volatile uint8_t*)(0x4003881CUL)) +#define FM4_MFS8_I2C_NFCR *((volatile uint8_t*)(0x4003881CUL)) +#define FM_MFS8_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003881DUL)) +#define FM4_MFS8_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003881DUL)) +#define FM_MFS8_I2C_EIBCR *((volatile uint8_t*)(0x4003881DUL)) +#define FM4_MFS8_I2C_EIBCR *((volatile uint8_t*)(0x4003881DUL)) +#define FM_MFS8_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038820UL)) +#define FM4_MFS8_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038820UL)) +#define FM_MFS8_CSIO_SACSR *((volatile uint16_t*)(0x40038824UL)) +#define FM4_MFS8_CSIO_SACSR *((volatile uint16_t*)(0x40038824UL)) +#define FM_MFS8_CSIO_STMR *((volatile uint16_t*)(0x40038828UL)) +#define FM4_MFS8_CSIO_STMR *((volatile uint16_t*)(0x40038828UL)) +#define FM_MFS8_CSIO_STMCR *((volatile uint16_t*)(0x4003882CUL)) +#define FM4_MFS8_CSIO_STMCR *((volatile uint16_t*)(0x4003882CUL)) +#define FM_MFS8_CSIO_SCSCR *((volatile uint16_t*)(0x40038830UL)) +#define FM4_MFS8_CSIO_SCSCR *((volatile uint16_t*)(0x40038830UL)) +#define FM_MFS8_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038834UL)) +#define FM4_MFS8_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038834UL)) +#define FM_MFS8_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038835UL)) +#define FM4_MFS8_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038835UL)) +#define FM_MFS8_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038838UL)) +#define FM4_MFS8_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038838UL)) +#define FM_MFS8_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003883CUL)) +#define FM4_MFS8_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003883CUL)) +#define FM_MFS8_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003883DUL)) +#define FM4_MFS8_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003883DUL)) +#define FM_MFS8_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038840UL)) +#define FM4_MFS8_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038840UL)) +#define FM_MFS8_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038841UL)) +#define FM4_MFS8_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038841UL)) + +/******************************************************************************* +* MFS Registers MFS9 +* Register Definition +*******************************************************************************/ +#define FM_MFS9_CSIO_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_CSIO_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_I2C_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_I2C_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_LIN_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_LIN_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_UART_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_UART_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_CSIO_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_CSIO_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_I2C_IBCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_I2C_IBCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_LIN_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_LIN_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_UART_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_UART_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_CSIO_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_CSIO_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_I2C_IBSR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_I2C_IBSR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_LIN_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_LIN_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_UART_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_UART_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_CSIO_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_CSIO_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_I2C_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_I2C_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_LIN_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_LIN_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_UART_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_UART_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_CSIO_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_CSIO_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_CSIO_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_CSIO_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_I2C_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_I2C_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_I2C_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_I2C_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_LIN_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_LIN_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_LIN_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_LIN_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_UART_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_UART_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_UART_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_UART_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_CSIO_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_CSIO_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_I2C_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_I2C_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_LIN_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_LIN_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_UART_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_UART_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_I2C_ISBA *((volatile uint8_t*)(0x40038910UL)) +#define FM4_MFS9_I2C_ISBA *((volatile uint8_t*)(0x40038910UL)) +#define FM_MFS9_I2C_ISMK *((volatile uint8_t*)(0x40038911UL)) +#define FM4_MFS9_I2C_ISMK *((volatile uint8_t*)(0x40038911UL)) +#define FM_MFS9_CSIO_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_CSIO_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_I2C_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_I2C_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_LIN_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_LIN_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_UART_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_UART_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_I2C_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_I2C_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_LIN_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_LIN_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_UART_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_UART_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_I2C_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_I2C_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_LIN_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_LIN_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_UART_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_UART_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003891CUL)) +#define FM4_MFS9_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003891CUL)) +#define FM_MFS9_I2C_NFCR *((volatile uint8_t*)(0x4003891CUL)) +#define FM4_MFS9_I2C_NFCR *((volatile uint8_t*)(0x4003891CUL)) +#define FM_MFS9_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003891DUL)) +#define FM4_MFS9_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003891DUL)) +#define FM_MFS9_I2C_EIBCR *((volatile uint8_t*)(0x4003891DUL)) +#define FM4_MFS9_I2C_EIBCR *((volatile uint8_t*)(0x4003891DUL)) +#define FM_MFS9_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038920UL)) +#define FM4_MFS9_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038920UL)) +#define FM_MFS9_CSIO_SACSR *((volatile uint16_t*)(0x40038924UL)) +#define FM4_MFS9_CSIO_SACSR *((volatile uint16_t*)(0x40038924UL)) +#define FM_MFS9_CSIO_STMR *((volatile uint16_t*)(0x40038928UL)) +#define FM4_MFS9_CSIO_STMR *((volatile uint16_t*)(0x40038928UL)) +#define FM_MFS9_CSIO_STMCR *((volatile uint16_t*)(0x4003892CUL)) +#define FM4_MFS9_CSIO_STMCR *((volatile uint16_t*)(0x4003892CUL)) +#define FM_MFS9_CSIO_SCSCR *((volatile uint16_t*)(0x40038930UL)) +#define FM4_MFS9_CSIO_SCSCR *((volatile uint16_t*)(0x40038930UL)) +#define FM_MFS9_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038934UL)) +#define FM4_MFS9_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038934UL)) +#define FM_MFS9_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038935UL)) +#define FM4_MFS9_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038935UL)) +#define FM_MFS9_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038938UL)) +#define FM4_MFS9_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038938UL)) +#define FM_MFS9_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003893CUL)) +#define FM4_MFS9_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003893CUL)) +#define FM_MFS9_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003893DUL)) +#define FM4_MFS9_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003893DUL)) +#define FM_MFS9_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038940UL)) +#define FM4_MFS9_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038940UL)) +#define FM_MFS9_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038941UL)) +#define FM4_MFS9_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038941UL)) + +/******************************************************************************* +* MFT_PPG Registers MFT_PPG +* Register Definition +*******************************************************************************/ +#define FM_MFT_PPG_TTCR0 *((volatile uint8_t*)(0x40024001UL)) +#define FM4_MFT_PPG_TTCR0 *((volatile uint8_t*)(0x40024001UL)) +#define FM_MFT_PPG_COMP0 *((volatile uint8_t*)(0x40024009UL)) +#define FM4_MFT_PPG_COMP0 *((volatile uint8_t*)(0x40024009UL)) +#define FM_MFT_PPG_COMP2 *((volatile uint8_t*)(0x4002400CUL)) +#define FM4_MFT_PPG_COMP2 *((volatile uint8_t*)(0x4002400CUL)) +#define FM_MFT_PPG_COMP4 *((volatile uint8_t*)(0x40024011UL)) +#define FM4_MFT_PPG_COMP4 *((volatile uint8_t*)(0x40024011UL)) +#define FM_MFT_PPG_COMP6 *((volatile uint8_t*)(0x40024014UL)) +#define FM4_MFT_PPG_COMP6 *((volatile uint8_t*)(0x40024014UL)) +#define FM_MFT_PPG_TTCR1 *((volatile uint8_t*)(0x40024021UL)) +#define FM4_MFT_PPG_TTCR1 *((volatile uint8_t*)(0x40024021UL)) +#define FM_MFT_PPG_COMP1 *((volatile uint8_t*)(0x40024029UL)) +#define FM4_MFT_PPG_COMP1 *((volatile uint8_t*)(0x40024029UL)) +#define FM_MFT_PPG_COMP3 *((volatile uint8_t*)(0x4002402CUL)) +#define FM4_MFT_PPG_COMP3 *((volatile uint8_t*)(0x4002402CUL)) +#define FM_MFT_PPG_COMP5 *((volatile uint8_t*)(0x40024031UL)) +#define FM4_MFT_PPG_COMP5 *((volatile uint8_t*)(0x40024031UL)) +#define FM_MFT_PPG_COMP7 *((volatile uint8_t*)(0x40024034UL)) +#define FM4_MFT_PPG_COMP7 *((volatile uint8_t*)(0x40024034UL)) +#define FM_MFT_PPG_TTCR2 *((volatile uint8_t*)(0x40024041UL)) +#define FM4_MFT_PPG_TTCR2 *((volatile uint8_t*)(0x40024041UL)) +#define FM_MFT_PPG_COMP8 *((volatile uint8_t*)(0x40024049UL)) +#define FM4_MFT_PPG_COMP8 *((volatile uint8_t*)(0x40024049UL)) +#define FM_MFT_PPG_COMP10 *((volatile uint8_t*)(0x4002404CUL)) +#define FM4_MFT_PPG_COMP10 *((volatile uint8_t*)(0x4002404CUL)) +#define FM_MFT_PPG_COMP12 *((volatile uint8_t*)(0x40024051UL)) +#define FM4_MFT_PPG_COMP12 *((volatile uint8_t*)(0x40024051UL)) +#define FM_MFT_PPG_COMP14 *((volatile uint8_t*)(0x40024054UL)) +#define FM4_MFT_PPG_COMP14 *((volatile uint8_t*)(0x40024054UL)) +#define FM_MFT_PPG_TRG0 *((volatile uint16_t*)(0x40024100UL)) +#define FM4_MFT_PPG_TRG0 *((volatile uint16_t*)(0x40024100UL)) +#define FM_MFT_PPG_REVC0 *((volatile uint16_t*)(0x40024104UL)) +#define FM4_MFT_PPG_REVC0 *((volatile uint16_t*)(0x40024104UL)) +#define FM_MFT_PPG_TRG1 *((volatile uint16_t*)(0x40024140UL)) +#define FM4_MFT_PPG_TRG1 *((volatile uint16_t*)(0x40024140UL)) +#define FM_MFT_PPG_REVC1 *((volatile uint16_t*)(0x40024144UL)) +#define FM4_MFT_PPG_REVC1 *((volatile uint16_t*)(0x40024144UL)) +#define FM_MFT_PPG_PPGC1 *((volatile uint8_t*)(0x40024200UL)) +#define FM4_MFT_PPG_PPGC1 *((volatile uint8_t*)(0x40024200UL)) +#define FM_MFT_PPG_PPGC0 *((volatile uint8_t*)(0x40024201UL)) +#define FM4_MFT_PPG_PPGC0 *((volatile uint8_t*)(0x40024201UL)) +#define FM_MFT_PPG_PPGC3 *((volatile uint8_t*)(0x40024204UL)) +#define FM4_MFT_PPG_PPGC3 *((volatile uint8_t*)(0x40024204UL)) +#define FM_MFT_PPG_PPGC2 *((volatile uint8_t*)(0x40024205UL)) +#define FM4_MFT_PPG_PPGC2 *((volatile uint8_t*)(0x40024205UL)) +#define FM_MFT_PPG_PRLL0 *((volatile uint8_t*)(0x40024208UL)) +#define FM4_MFT_PPG_PRLL0 *((volatile uint8_t*)(0x40024208UL)) +#define FM_MFT_PPG_PRLH0 *((volatile uint8_t*)(0x40024209UL)) +#define FM4_MFT_PPG_PRLH0 *((volatile uint8_t*)(0x40024209UL)) +#define FM_MFT_PPG_PRLL1 *((volatile uint8_t*)(0x4002420CUL)) +#define FM4_MFT_PPG_PRLL1 *((volatile uint8_t*)(0x4002420CUL)) +#define FM_MFT_PPG_PRLH1 *((volatile uint8_t*)(0x4002420DUL)) +#define FM4_MFT_PPG_PRLH1 *((volatile uint8_t*)(0x4002420DUL)) +#define FM_MFT_PPG_PRLL2 *((volatile uint8_t*)(0x40024210UL)) +#define FM4_MFT_PPG_PRLL2 *((volatile uint8_t*)(0x40024210UL)) +#define FM_MFT_PPG_PRLH2 *((volatile uint8_t*)(0x40024211UL)) +#define FM4_MFT_PPG_PRLH2 *((volatile uint8_t*)(0x40024211UL)) +#define FM_MFT_PPG_PRLL3 *((volatile uint8_t*)(0x40024214UL)) +#define FM4_MFT_PPG_PRLL3 *((volatile uint8_t*)(0x40024214UL)) +#define FM_MFT_PPG_PRLH3 *((volatile uint8_t*)(0x40024215UL)) +#define FM4_MFT_PPG_PRLH3 *((volatile uint8_t*)(0x40024215UL)) +#define FM_MFT_PPG_GATEC0 *((volatile uint8_t*)(0x40024218UL)) +#define FM4_MFT_PPG_GATEC0 *((volatile uint8_t*)(0x40024218UL)) +#define FM_MFT_PPG_PPGC5 *((volatile uint8_t*)(0x40024240UL)) +#define FM4_MFT_PPG_PPGC5 *((volatile uint8_t*)(0x40024240UL)) +#define FM_MFT_PPG_PPGC4 *((volatile uint8_t*)(0x40024241UL)) +#define FM4_MFT_PPG_PPGC4 *((volatile uint8_t*)(0x40024241UL)) +#define FM_MFT_PPG_PPGC7 *((volatile uint8_t*)(0x40024244UL)) +#define FM4_MFT_PPG_PPGC7 *((volatile uint8_t*)(0x40024244UL)) +#define FM_MFT_PPG_PPGC6 *((volatile uint8_t*)(0x40024245UL)) +#define FM4_MFT_PPG_PPGC6 *((volatile uint8_t*)(0x40024245UL)) +#define FM_MFT_PPG_PRLL4 *((volatile uint8_t*)(0x40024248UL)) +#define FM4_MFT_PPG_PRLL4 *((volatile uint8_t*)(0x40024248UL)) +#define FM_MFT_PPG_PRLH4 *((volatile uint8_t*)(0x40024249UL)) +#define FM4_MFT_PPG_PRLH4 *((volatile uint8_t*)(0x40024249UL)) +#define FM_MFT_PPG_PRLL5 *((volatile uint8_t*)(0x4002424CUL)) +#define FM4_MFT_PPG_PRLL5 *((volatile uint8_t*)(0x4002424CUL)) +#define FM_MFT_PPG_PRLH5 *((volatile uint8_t*)(0x4002424DUL)) +#define FM4_MFT_PPG_PRLH5 *((volatile uint8_t*)(0x4002424DUL)) +#define FM_MFT_PPG_PRLL6 *((volatile uint8_t*)(0x40024250UL)) +#define FM4_MFT_PPG_PRLL6 *((volatile uint8_t*)(0x40024250UL)) +#define FM_MFT_PPG_PRLH6 *((volatile uint8_t*)(0x40024251UL)) +#define FM4_MFT_PPG_PRLH6 *((volatile uint8_t*)(0x40024251UL)) +#define FM_MFT_PPG_PRLL7 *((volatile uint8_t*)(0x40024254UL)) +#define FM4_MFT_PPG_PRLL7 *((volatile uint8_t*)(0x40024254UL)) +#define FM_MFT_PPG_PRLH7 *((volatile uint8_t*)(0x40024255UL)) +#define FM4_MFT_PPG_PRLH7 *((volatile uint8_t*)(0x40024255UL)) +#define FM_MFT_PPG_GATEC4 *((volatile uint8_t*)(0x40024258UL)) +#define FM4_MFT_PPG_GATEC4 *((volatile uint8_t*)(0x40024258UL)) +#define FM_MFT_PPG_PPGC9 *((volatile uint8_t*)(0x40024280UL)) +#define FM4_MFT_PPG_PPGC9 *((volatile uint8_t*)(0x40024280UL)) +#define FM_MFT_PPG_PPGC8 *((volatile uint8_t*)(0x40024281UL)) +#define FM4_MFT_PPG_PPGC8 *((volatile uint8_t*)(0x40024281UL)) +#define FM_MFT_PPG_PPGC11 *((volatile uint8_t*)(0x40024284UL)) +#define FM4_MFT_PPG_PPGC11 *((volatile uint8_t*)(0x40024284UL)) +#define FM_MFT_PPG_PPGC10 *((volatile uint8_t*)(0x40024285UL)) +#define FM4_MFT_PPG_PPGC10 *((volatile uint8_t*)(0x40024285UL)) +#define FM_MFT_PPG_PRLL8 *((volatile uint8_t*)(0x40024288UL)) +#define FM4_MFT_PPG_PRLL8 *((volatile uint8_t*)(0x40024288UL)) +#define FM_MFT_PPG_PRLH8 *((volatile uint8_t*)(0x40024289UL)) +#define FM4_MFT_PPG_PRLH8 *((volatile uint8_t*)(0x40024289UL)) +#define FM_MFT_PPG_PRLL9 *((volatile uint8_t*)(0x4002428CUL)) +#define FM4_MFT_PPG_PRLL9 *((volatile uint8_t*)(0x4002428CUL)) +#define FM_MFT_PPG_PRLH9 *((volatile uint8_t*)(0x4002428DUL)) +#define FM4_MFT_PPG_PRLH9 *((volatile uint8_t*)(0x4002428DUL)) +#define FM_MFT_PPG_PRLL10 *((volatile uint8_t*)(0x40024290UL)) +#define FM4_MFT_PPG_PRLL10 *((volatile uint8_t*)(0x40024290UL)) +#define FM_MFT_PPG_PRLH10 *((volatile uint8_t*)(0x40024291UL)) +#define FM4_MFT_PPG_PRLH10 *((volatile uint8_t*)(0x40024291UL)) +#define FM_MFT_PPG_PRLL11 *((volatile uint8_t*)(0x40024294UL)) +#define FM4_MFT_PPG_PRLL11 *((volatile uint8_t*)(0x40024294UL)) +#define FM_MFT_PPG_PRLH11 *((volatile uint8_t*)(0x40024295UL)) +#define FM4_MFT_PPG_PRLH11 *((volatile uint8_t*)(0x40024295UL)) +#define FM_MFT_PPG_GATEC8 *((volatile uint8_t*)(0x40024298UL)) +#define FM4_MFT_PPG_GATEC8 *((volatile uint8_t*)(0x40024298UL)) +#define FM_MFT_PPG_PPGC13 *((volatile uint8_t*)(0x400242C0UL)) +#define FM4_MFT_PPG_PPGC13 *((volatile uint8_t*)(0x400242C0UL)) +#define FM_MFT_PPG_PPGC12 *((volatile uint8_t*)(0x400242C1UL)) +#define FM4_MFT_PPG_PPGC12 *((volatile uint8_t*)(0x400242C1UL)) +#define FM_MFT_PPG_PPGC15 *((volatile uint8_t*)(0x400242C4UL)) +#define FM4_MFT_PPG_PPGC15 *((volatile uint8_t*)(0x400242C4UL)) +#define FM_MFT_PPG_PPGC14 *((volatile uint8_t*)(0x400242C5UL)) +#define FM4_MFT_PPG_PPGC14 *((volatile uint8_t*)(0x400242C5UL)) +#define FM_MFT_PPG_PRLL12 *((volatile uint8_t*)(0x400242C8UL)) +#define FM4_MFT_PPG_PRLL12 *((volatile uint8_t*)(0x400242C8UL)) +#define FM_MFT_PPG_PRLH12 *((volatile uint8_t*)(0x400242C9UL)) +#define FM4_MFT_PPG_PRLH12 *((volatile uint8_t*)(0x400242C9UL)) +#define FM_MFT_PPG_PRLL13 *((volatile uint8_t*)(0x400242CCUL)) +#define FM4_MFT_PPG_PRLL13 *((volatile uint8_t*)(0x400242CCUL)) +#define FM_MFT_PPG_PRLH13 *((volatile uint8_t*)(0x400242CDUL)) +#define FM4_MFT_PPG_PRLH13 *((volatile uint8_t*)(0x400242CDUL)) +#define FM_MFT_PPG_PRLL14 *((volatile uint8_t*)(0x400242D0UL)) +#define FM4_MFT_PPG_PRLL14 *((volatile uint8_t*)(0x400242D0UL)) +#define FM_MFT_PPG_PRLH14 *((volatile uint8_t*)(0x400242D1UL)) +#define FM4_MFT_PPG_PRLH14 *((volatile uint8_t*)(0x400242D1UL)) +#define FM_MFT_PPG_PRLL15 *((volatile uint8_t*)(0x400242D4UL)) +#define FM4_MFT_PPG_PRLL15 *((volatile uint8_t*)(0x400242D4UL)) +#define FM_MFT_PPG_PRLH15 *((volatile uint8_t*)(0x400242D5UL)) +#define FM4_MFT_PPG_PRLH15 *((volatile uint8_t*)(0x400242D5UL)) +#define FM_MFT_PPG_GATEC12 *((volatile uint8_t*)(0x400242D8UL)) +#define FM4_MFT_PPG_GATEC12 *((volatile uint8_t*)(0x400242D8UL)) +#define FM_MFT_PPG_PPGC17 *((volatile uint8_t*)(0x40024300UL)) +#define FM4_MFT_PPG_PPGC17 *((volatile uint8_t*)(0x40024300UL)) +#define FM_MFT_PPG_PPGC16 *((volatile uint8_t*)(0x40024301UL)) +#define FM4_MFT_PPG_PPGC16 *((volatile uint8_t*)(0x40024301UL)) +#define FM_MFT_PPG_PPGC19 *((volatile uint8_t*)(0x40024304UL)) +#define FM4_MFT_PPG_PPGC19 *((volatile uint8_t*)(0x40024304UL)) +#define FM_MFT_PPG_PPGC18 *((volatile uint8_t*)(0x40024305UL)) +#define FM4_MFT_PPG_PPGC18 *((volatile uint8_t*)(0x40024305UL)) +#define FM_MFT_PPG_PRLL16 *((volatile uint8_t*)(0x40024308UL)) +#define FM4_MFT_PPG_PRLL16 *((volatile uint8_t*)(0x40024308UL)) +#define FM_MFT_PPG_PRLH16 *((volatile uint8_t*)(0x40024309UL)) +#define FM4_MFT_PPG_PRLH16 *((volatile uint8_t*)(0x40024309UL)) +#define FM_MFT_PPG_PRLL17 *((volatile uint8_t*)(0x4002430CUL)) +#define FM4_MFT_PPG_PRLL17 *((volatile uint8_t*)(0x4002430CUL)) +#define FM_MFT_PPG_PRLH17 *((volatile uint8_t*)(0x4002430DUL)) +#define FM4_MFT_PPG_PRLH17 *((volatile uint8_t*)(0x4002430DUL)) +#define FM_MFT_PPG_PRLL18 *((volatile uint8_t*)(0x40024310UL)) +#define FM4_MFT_PPG_PRLL18 *((volatile uint8_t*)(0x40024310UL)) +#define FM_MFT_PPG_PRLH18 *((volatile uint8_t*)(0x40024311UL)) +#define FM4_MFT_PPG_PRLH18 *((volatile uint8_t*)(0x40024311UL)) +#define FM_MFT_PPG_PRLL19 *((volatile uint8_t*)(0x40024314UL)) +#define FM4_MFT_PPG_PRLL19 *((volatile uint8_t*)(0x40024314UL)) +#define FM_MFT_PPG_PRLH19 *((volatile uint8_t*)(0x40024315UL)) +#define FM4_MFT_PPG_PRLH19 *((volatile uint8_t*)(0x40024315UL)) +#define FM_MFT_PPG_GATEC16 *((volatile uint8_t*)(0x40024318UL)) +#define FM4_MFT_PPG_GATEC16 *((volatile uint8_t*)(0x40024318UL)) +#define FM_MFT_PPG_PPGC21 *((volatile uint8_t*)(0x40024340UL)) +#define FM4_MFT_PPG_PPGC21 *((volatile uint8_t*)(0x40024340UL)) +#define FM_MFT_PPG_PPGC20 *((volatile uint8_t*)(0x40024341UL)) +#define FM4_MFT_PPG_PPGC20 *((volatile uint8_t*)(0x40024341UL)) +#define FM_MFT_PPG_PPGC23 *((volatile uint8_t*)(0x40024344UL)) +#define FM4_MFT_PPG_PPGC23 *((volatile uint8_t*)(0x40024344UL)) +#define FM_MFT_PPG_PPGC22 *((volatile uint8_t*)(0x40024345UL)) +#define FM4_MFT_PPG_PPGC22 *((volatile uint8_t*)(0x40024345UL)) +#define FM_MFT_PPG_PRLL20 *((volatile uint8_t*)(0x40024348UL)) +#define FM4_MFT_PPG_PRLL20 *((volatile uint8_t*)(0x40024348UL)) +#define FM_MFT_PPG_PRLH20 *((volatile uint8_t*)(0x40024349UL)) +#define FM4_MFT_PPG_PRLH20 *((volatile uint8_t*)(0x40024349UL)) +#define FM_MFT_PPG_PRLL21 *((volatile uint8_t*)(0x4002434CUL)) +#define FM4_MFT_PPG_PRLL21 *((volatile uint8_t*)(0x4002434CUL)) +#define FM_MFT_PPG_PRLH21 *((volatile uint8_t*)(0x4002434DUL)) +#define FM4_MFT_PPG_PRLH21 *((volatile uint8_t*)(0x4002434DUL)) +#define FM_MFT_PPG_PRLL22 *((volatile uint8_t*)(0x40024350UL)) +#define FM4_MFT_PPG_PRLL22 *((volatile uint8_t*)(0x40024350UL)) +#define FM_MFT_PPG_PRLH22 *((volatile uint8_t*)(0x40024351UL)) +#define FM4_MFT_PPG_PRLH22 *((volatile uint8_t*)(0x40024351UL)) +#define FM_MFT_PPG_PRLL23 *((volatile uint8_t*)(0x40024354UL)) +#define FM4_MFT_PPG_PRLL23 *((volatile uint8_t*)(0x40024354UL)) +#define FM_MFT_PPG_PRLH23 *((volatile uint8_t*)(0x40024355UL)) +#define FM4_MFT_PPG_PRLH23 *((volatile uint8_t*)(0x40024355UL)) +#define FM_MFT_PPG_GATEC20 *((volatile uint8_t*)(0x40024358UL)) +#define FM4_MFT_PPG_GATEC20 *((volatile uint8_t*)(0x40024358UL)) + +/******************************************************************************* +* MFT Registers MFT0 +* Register Definition +*******************************************************************************/ +#define FM_MFT0_OCU_OCCP0 *((volatile uint16_t*)(0x40020102UL)) +#define FM4_MFT0_OCU_OCCP0 *((volatile uint16_t*)(0x40020102UL)) +#define FM_MFT0_OCU_OCCP1 *((volatile uint16_t*)(0x40020106UL)) +#define FM4_MFT0_OCU_OCCP1 *((volatile uint16_t*)(0x40020106UL)) +#define FM_MFT0_OCU_OCCP2 *((volatile uint16_t*)(0x4002010AUL)) +#define FM4_MFT0_OCU_OCCP2 *((volatile uint16_t*)(0x4002010AUL)) +#define FM_MFT0_OCU_OCCP3 *((volatile uint16_t*)(0x4002010EUL)) +#define FM4_MFT0_OCU_OCCP3 *((volatile uint16_t*)(0x4002010EUL)) +#define FM_MFT0_OCU_OCCP4 *((volatile uint16_t*)(0x40020112UL)) +#define FM4_MFT0_OCU_OCCP4 *((volatile uint16_t*)(0x40020112UL)) +#define FM_MFT0_OCU_OCCP5 *((volatile uint16_t*)(0x40020116UL)) +#define FM4_MFT0_OCU_OCCP5 *((volatile uint16_t*)(0x40020116UL)) +#define FM_MFT0_OCU_OCSA10 *((volatile uint8_t*)(0x40020118UL)) +#define FM4_MFT0_OCU_OCSA10 *((volatile uint8_t*)(0x40020118UL)) +#define FM_MFT0_OCU_OCSB10 *((volatile uint8_t*)(0x40020119UL)) +#define FM4_MFT0_OCU_OCSB10 *((volatile uint8_t*)(0x40020119UL)) +#define FM_MFT0_OCU_OCSD10 *((volatile uint16_t*)(0x4002011AUL)) +#define FM4_MFT0_OCU_OCSD10 *((volatile uint16_t*)(0x4002011AUL)) +#define FM_MFT0_OCU_OCSA32 *((volatile uint8_t*)(0x4002011CUL)) +#define FM4_MFT0_OCU_OCSA32 *((volatile uint8_t*)(0x4002011CUL)) +#define FM_MFT0_OCU_OCSB32 *((volatile uint8_t*)(0x4002011DUL)) +#define FM4_MFT0_OCU_OCSB32 *((volatile uint8_t*)(0x4002011DUL)) +#define FM_MFT0_OCU_OCSD32 *((volatile uint16_t*)(0x4002011EUL)) +#define FM4_MFT0_OCU_OCSD32 *((volatile uint16_t*)(0x4002011EUL)) +#define FM_MFT0_OCU_OCSA54 *((volatile uint8_t*)(0x40020120UL)) +#define FM4_MFT0_OCU_OCSA54 *((volatile uint8_t*)(0x40020120UL)) +#define FM_MFT0_OCU_OCSB54 *((volatile uint8_t*)(0x40020121UL)) +#define FM4_MFT0_OCU_OCSB54 *((volatile uint8_t*)(0x40020121UL)) +#define FM_MFT0_OCU_OCSD54 *((volatile uint16_t*)(0x40020122UL)) +#define FM4_MFT0_OCU_OCSD54 *((volatile uint16_t*)(0x40020122UL)) +#define FM_MFT0_OCU_OCSC *((volatile uint8_t*)(0x40020125UL)) +#define FM4_MFT0_OCU_OCSC *((volatile uint8_t*)(0x40020125UL)) +#define FM_MFT0_OCU_OCSE0 *((volatile uint16_t*)(0x40020128UL)) +#define FM4_MFT0_OCU_OCSE0 *((volatile uint16_t*)(0x40020128UL)) +#define FM_MFT0_OCU_OCSE1 *((volatile uint32_t*)(0x4002012CUL)) +#define FM4_MFT0_OCU_OCSE1 *((volatile uint32_t*)(0x4002012CUL)) +#define FM_MFT0_OCU_OCSE2 *((volatile uint16_t*)(0x40020130UL)) +#define FM4_MFT0_OCU_OCSE2 *((volatile uint16_t*)(0x40020130UL)) +#define FM_MFT0_OCU_OCSE3 *((volatile uint32_t*)(0x40020134UL)) +#define FM4_MFT0_OCU_OCSE3 *((volatile uint32_t*)(0x40020134UL)) +#define FM_MFT0_OCU_OCSE4 *((volatile uint16_t*)(0x40020138UL)) +#define FM4_MFT0_OCU_OCSE4 *((volatile uint16_t*)(0x40020138UL)) +#define FM_MFT0_OCU_OCSE5 *((volatile uint32_t*)(0x4002013CUL)) +#define FM4_MFT0_OCU_OCSE5 *((volatile uint32_t*)(0x4002013CUL)) +#define FM_MFT0_FRT_TCCP0 *((volatile uint16_t*)(0x40020142UL)) +#define FM4_MFT0_FRT_TCCP0 *((volatile uint16_t*)(0x40020142UL)) +#define FM_MFT0_FRT_TCDT0 *((volatile uint16_t*)(0x40020146UL)) +#define FM4_MFT0_FRT_TCDT0 *((volatile uint16_t*)(0x40020146UL)) +#define FM_MFT0_FRT_TCSA0 *((volatile uint16_t*)(0x40020148UL)) +#define FM4_MFT0_FRT_TCSA0 *((volatile uint16_t*)(0x40020148UL)) +#define FM_MFT0_FRT_TCSC0 *((volatile uint16_t*)(0x4002014AUL)) +#define FM4_MFT0_FRT_TCSC0 *((volatile uint16_t*)(0x4002014AUL)) +#define FM_MFT0_FRT_TCCP1 *((volatile uint16_t*)(0x4002014EUL)) +#define FM4_MFT0_FRT_TCCP1 *((volatile uint16_t*)(0x4002014EUL)) +#define FM_MFT0_FRT_TCDT1 *((volatile uint16_t*)(0x40020152UL)) +#define FM4_MFT0_FRT_TCDT1 *((volatile uint16_t*)(0x40020152UL)) +#define FM_MFT0_FRT_TCSA1 *((volatile uint16_t*)(0x40020154UL)) +#define FM4_MFT0_FRT_TCSA1 *((volatile uint16_t*)(0x40020154UL)) +#define FM_MFT0_FRT_TCSC1 *((volatile uint16_t*)(0x40020156UL)) +#define FM4_MFT0_FRT_TCSC1 *((volatile uint16_t*)(0x40020156UL)) +#define FM_MFT0_FRT_TCCP2 *((volatile uint16_t*)(0x4002015AUL)) +#define FM4_MFT0_FRT_TCCP2 *((volatile uint16_t*)(0x4002015AUL)) +#define FM_MFT0_FRT_TCDT2 *((volatile uint16_t*)(0x4002015EUL)) +#define FM4_MFT0_FRT_TCDT2 *((volatile uint16_t*)(0x4002015EUL)) +#define FM_MFT0_FRT_TCSA2 *((volatile uint16_t*)(0x40020160UL)) +#define FM4_MFT0_FRT_TCSA2 *((volatile uint16_t*)(0x40020160UL)) +#define FM_MFT0_FRT_TCSC2 *((volatile uint16_t*)(0x40020162UL)) +#define FM4_MFT0_FRT_TCSC2 *((volatile uint16_t*)(0x40020162UL)) +#define FM_MFT0_FRT_TCAL *((volatile uint32_t*)(0x40020164UL)) +#define FM4_MFT0_FRT_TCAL *((volatile uint32_t*)(0x40020164UL)) +#define FM_MFT0_OCU_OCFS10 *((volatile uint8_t*)(0x40020168UL)) +#define FM4_MFT0_OCU_OCFS10 *((volatile uint8_t*)(0x40020168UL)) +#define FM_MFT0_OCU_OCFS32 *((volatile uint8_t*)(0x40020169UL)) +#define FM4_MFT0_OCU_OCFS32 *((volatile uint8_t*)(0x40020169UL)) +#define FM_MFT0_OCU_OCFS54 *((volatile uint8_t*)(0x4002016AUL)) +#define FM4_MFT0_OCU_OCFS54 *((volatile uint8_t*)(0x4002016AUL)) +#define FM_MFT0_ICU_ICFS10 *((volatile uint8_t*)(0x4002016CUL)) +#define FM4_MFT0_ICU_ICFS10 *((volatile uint8_t*)(0x4002016CUL)) +#define FM_MFT0_ICU_ICFS32 *((volatile uint8_t*)(0x4002016DUL)) +#define FM4_MFT0_ICU_ICFS32 *((volatile uint8_t*)(0x4002016DUL)) +#define FM_MFT0_ADCMP_ACFS10 *((volatile uint8_t*)(0x40020170UL)) +#define FM4_MFT0_ADCMP_ACFS10 *((volatile uint8_t*)(0x40020170UL)) +#define FM_MFT0_ADCMP_ACFS32 *((volatile uint8_t*)(0x40020171UL)) +#define FM4_MFT0_ADCMP_ACFS32 *((volatile uint8_t*)(0x40020171UL)) +#define FM_MFT0_ADCMP_ACFS54 *((volatile uint8_t*)(0x40020172UL)) +#define FM4_MFT0_ADCMP_ACFS54 *((volatile uint8_t*)(0x40020172UL)) +#define FM_MFT0_ICU_ICCP0 *((volatile uint16_t*)(0x40020176UL)) +#define FM4_MFT0_ICU_ICCP0 *((volatile uint16_t*)(0x40020176UL)) +#define FM_MFT0_ICU_ICCP1 *((volatile uint16_t*)(0x4002017AUL)) +#define FM4_MFT0_ICU_ICCP1 *((volatile uint16_t*)(0x4002017AUL)) +#define FM_MFT0_ICU_ICCP2 *((volatile uint16_t*)(0x4002017EUL)) +#define FM4_MFT0_ICU_ICCP2 *((volatile uint16_t*)(0x4002017EUL)) +#define FM_MFT0_ICU_ICCP3 *((volatile uint16_t*)(0x40020182UL)) +#define FM4_MFT0_ICU_ICCP3 *((volatile uint16_t*)(0x40020182UL)) +#define FM_MFT0_ICU_ICSA10 *((volatile uint8_t*)(0x40020184UL)) +#define FM4_MFT0_ICU_ICSA10 *((volatile uint8_t*)(0x40020184UL)) +#define FM_MFT0_ICU_ICSB10 *((volatile uint8_t*)(0x40020185UL)) +#define FM4_MFT0_ICU_ICSB10 *((volatile uint8_t*)(0x40020185UL)) +#define FM_MFT0_ICU_ICSA32 *((volatile uint8_t*)(0x40020188UL)) +#define FM4_MFT0_ICU_ICSA32 *((volatile uint8_t*)(0x40020188UL)) +#define FM_MFT0_ICU_ICSB32 *((volatile uint8_t*)(0x40020189UL)) +#define FM4_MFT0_ICU_ICSB32 *((volatile uint8_t*)(0x40020189UL)) +#define FM_MFT0_WFG_WFTF10 *((volatile uint16_t*)(0x4002018EUL)) +#define FM4_MFT0_WFG_WFTF10 *((volatile uint16_t*)(0x4002018EUL)) +#define FM_MFT0_WFG_WFTA10 *((volatile uint16_t*)(0x40020190UL)) +#define FM4_MFT0_WFG_WFTA10 *((volatile uint16_t*)(0x40020190UL)) +#define FM_MFT0_WFG_WFTB10 *((volatile uint16_t*)(0x40020192UL)) +#define FM4_MFT0_WFG_WFTB10 *((volatile uint16_t*)(0x40020192UL)) +#define FM_MFT0_WFG_WFTF32 *((volatile uint16_t*)(0x40020196UL)) +#define FM4_MFT0_WFG_WFTF32 *((volatile uint16_t*)(0x40020196UL)) +#define FM_MFT0_WFG_WFTA32 *((volatile uint16_t*)(0x40020198UL)) +#define FM4_MFT0_WFG_WFTA32 *((volatile uint16_t*)(0x40020198UL)) +#define FM_MFT0_WFG_WFTB32 *((volatile uint16_t*)(0x4002019AUL)) +#define FM4_MFT0_WFG_WFTB32 *((volatile uint16_t*)(0x4002019AUL)) +#define FM_MFT0_WFG_WFTF54 *((volatile uint16_t*)(0x4002019EUL)) +#define FM4_MFT0_WFG_WFTF54 *((volatile uint16_t*)(0x4002019EUL)) +#define FM_MFT0_WFG_WFTA54 *((volatile uint16_t*)(0x400201A0UL)) +#define FM4_MFT0_WFG_WFTA54 *((volatile uint16_t*)(0x400201A0UL)) +#define FM_MFT0_WFG_WFTB54 *((volatile uint16_t*)(0x400201A2UL)) +#define FM4_MFT0_WFG_WFTB54 *((volatile uint16_t*)(0x400201A2UL)) +#define FM_MFT0_WFG_WFSA10 *((volatile uint16_t*)(0x400201A4UL)) +#define FM4_MFT0_WFG_WFSA10 *((volatile uint16_t*)(0x400201A4UL)) +#define FM_MFT0_WFG_WFSA32 *((volatile uint16_t*)(0x400201A8UL)) +#define FM4_MFT0_WFG_WFSA32 *((volatile uint16_t*)(0x400201A8UL)) +#define FM_MFT0_WFG_WFSA54 *((volatile uint16_t*)(0x400201ACUL)) +#define FM4_MFT0_WFG_WFSA54 *((volatile uint16_t*)(0x400201ACUL)) +#define FM_MFT0_WFG_WFIR *((volatile uint16_t*)(0x400201B0UL)) +#define FM4_MFT0_WFG_WFIR *((volatile uint16_t*)(0x400201B0UL)) +#define FM_MFT0_WFG_NZCL *((volatile uint16_t*)(0x400201B4UL)) +#define FM4_MFT0_WFG_NZCL *((volatile uint16_t*)(0x400201B4UL)) +#define FM_MFT0_ADCMP_ACMP0 *((volatile uint16_t*)(0x400201BAUL)) +#define FM4_MFT0_ADCMP_ACMP0 *((volatile uint16_t*)(0x400201BAUL)) +#define FM_MFT0_ADCMP_ACMP1 *((volatile uint16_t*)(0x400201BEUL)) +#define FM4_MFT0_ADCMP_ACMP1 *((volatile uint16_t*)(0x400201BEUL)) +#define FM_MFT0_ADCMP_ACMP2 *((volatile uint16_t*)(0x400201C2UL)) +#define FM4_MFT0_ADCMP_ACMP2 *((volatile uint16_t*)(0x400201C2UL)) +#define FM_MFT0_ADCMP_ACMP3 *((volatile uint16_t*)(0x400201C6UL)) +#define FM4_MFT0_ADCMP_ACMP3 *((volatile uint16_t*)(0x400201C6UL)) +#define FM_MFT0_ADCMP_ACMP4 *((volatile uint16_t*)(0x400201CAUL)) +#define FM4_MFT0_ADCMP_ACMP4 *((volatile uint16_t*)(0x400201CAUL)) +#define FM_MFT0_ADCMP_ACMP5 *((volatile uint16_t*)(0x400201CEUL)) +#define FM4_MFT0_ADCMP_ACMP5 *((volatile uint16_t*)(0x400201CEUL)) +#define FM_MFT0_ADCMP_ACSA *((volatile uint16_t*)(0x400201D0UL)) +#define FM4_MFT0_ADCMP_ACSA *((volatile uint16_t*)(0x400201D0UL)) +#define FM_MFT0_ADCMP_ACSC0 *((volatile uint8_t*)(0x400201D4UL)) +#define FM4_MFT0_ADCMP_ACSC0 *((volatile uint8_t*)(0x400201D4UL)) +#define FM_MFT0_ADCMP_ACSD0 *((volatile uint8_t*)(0x400201D5UL)) +#define FM4_MFT0_ADCMP_ACSD0 *((volatile uint8_t*)(0x400201D5UL)) +#define FM_MFT0_ADCMP_ACMC0 *((volatile uint8_t*)(0x400201D6UL)) +#define FM4_MFT0_ADCMP_ACMC0 *((volatile uint8_t*)(0x400201D6UL)) +#define FM_MFT0_ADCMP_ACSC1 *((volatile uint8_t*)(0x400201D8UL)) +#define FM4_MFT0_ADCMP_ACSC1 *((volatile uint8_t*)(0x400201D8UL)) +#define FM_MFT0_ADCMP_ACSD1 *((volatile uint8_t*)(0x400201D9UL)) +#define FM4_MFT0_ADCMP_ACSD1 *((volatile uint8_t*)(0x400201D9UL)) +#define FM_MFT0_ADCMP_ACMC1 *((volatile uint8_t*)(0x400201DAUL)) +#define FM4_MFT0_ADCMP_ACMC1 *((volatile uint8_t*)(0x400201DAUL)) +#define FM_MFT0_ADCMP_ACSC2 *((volatile uint8_t*)(0x400201DCUL)) +#define FM4_MFT0_ADCMP_ACSC2 *((volatile uint8_t*)(0x400201DCUL)) +#define FM_MFT0_ADCMP_ACSD2 *((volatile uint8_t*)(0x400201DDUL)) +#define FM4_MFT0_ADCMP_ACSD2 *((volatile uint8_t*)(0x400201DDUL)) +#define FM_MFT0_ADCMP_ACMC2 *((volatile uint8_t*)(0x400201DEUL)) +#define FM4_MFT0_ADCMP_ACMC2 *((volatile uint8_t*)(0x400201DEUL)) +#define FM_MFT0_ADCMP_ACSC3 *((volatile uint8_t*)(0x400201E0UL)) +#define FM4_MFT0_ADCMP_ACSC3 *((volatile uint8_t*)(0x400201E0UL)) +#define FM_MFT0_ADCMP_ACSD3 *((volatile uint8_t*)(0x400201E1UL)) +#define FM4_MFT0_ADCMP_ACSD3 *((volatile uint8_t*)(0x400201E1UL)) +#define FM_MFT0_ADCMP_ACMC3 *((volatile uint8_t*)(0x400201E2UL)) +#define FM4_MFT0_ADCMP_ACMC3 *((volatile uint8_t*)(0x400201E2UL)) +#define FM_MFT0_ADCMP_ACSC4 *((volatile uint8_t*)(0x400201E4UL)) +#define FM4_MFT0_ADCMP_ACSC4 *((volatile uint8_t*)(0x400201E4UL)) +#define FM_MFT0_ADCMP_ACSD4 *((volatile uint8_t*)(0x400201E5UL)) +#define FM4_MFT0_ADCMP_ACSD4 *((volatile uint8_t*)(0x400201E5UL)) +#define FM_MFT0_ADCMP_ACMC4 *((volatile uint8_t*)(0x400201E6UL)) +#define FM4_MFT0_ADCMP_ACMC4 *((volatile uint8_t*)(0x400201E6UL)) +#define FM_MFT0_ADCMP_ACSC5 *((volatile uint8_t*)(0x400201E8UL)) +#define FM4_MFT0_ADCMP_ACSC5 *((volatile uint8_t*)(0x400201E8UL)) +#define FM_MFT0_ADCMP_ACSD5 *((volatile uint8_t*)(0x400201E9UL)) +#define FM4_MFT0_ADCMP_ACSD5 *((volatile uint8_t*)(0x400201E9UL)) +#define FM_MFT0_ADCMP_ACMC5 *((volatile uint8_t*)(0x400201EAUL)) +#define FM4_MFT0_ADCMP_ACMC5 *((volatile uint8_t*)(0x400201EAUL)) +#define FM_MFT0_FRT_TCSD *((volatile uint8_t*)(0x400201ECUL)) +#define FM4_MFT0_FRT_TCSD *((volatile uint8_t*)(0x400201ECUL)) + +/******************************************************************************* +* MFT Registers MFT1 +* Register Definition +*******************************************************************************/ +#define FM_MFT1_OCU_OCCP0 *((volatile uint16_t*)(0x40021102UL)) +#define FM4_MFT1_OCU_OCCP0 *((volatile uint16_t*)(0x40021102UL)) +#define FM_MFT1_OCU_OCCP1 *((volatile uint16_t*)(0x40021106UL)) +#define FM4_MFT1_OCU_OCCP1 *((volatile uint16_t*)(0x40021106UL)) +#define FM_MFT1_OCU_OCCP2 *((volatile uint16_t*)(0x4002110AUL)) +#define FM4_MFT1_OCU_OCCP2 *((volatile uint16_t*)(0x4002110AUL)) +#define FM_MFT1_OCU_OCCP3 *((volatile uint16_t*)(0x4002110EUL)) +#define FM4_MFT1_OCU_OCCP3 *((volatile uint16_t*)(0x4002110EUL)) +#define FM_MFT1_OCU_OCCP4 *((volatile uint16_t*)(0x40021112UL)) +#define FM4_MFT1_OCU_OCCP4 *((volatile uint16_t*)(0x40021112UL)) +#define FM_MFT1_OCU_OCCP5 *((volatile uint16_t*)(0x40021116UL)) +#define FM4_MFT1_OCU_OCCP5 *((volatile uint16_t*)(0x40021116UL)) +#define FM_MFT1_OCU_OCSA10 *((volatile uint8_t*)(0x40021118UL)) +#define FM4_MFT1_OCU_OCSA10 *((volatile uint8_t*)(0x40021118UL)) +#define FM_MFT1_OCU_OCSB10 *((volatile uint8_t*)(0x40021119UL)) +#define FM4_MFT1_OCU_OCSB10 *((volatile uint8_t*)(0x40021119UL)) +#define FM_MFT1_OCU_OCSD10 *((volatile uint16_t*)(0x4002111AUL)) +#define FM4_MFT1_OCU_OCSD10 *((volatile uint16_t*)(0x4002111AUL)) +#define FM_MFT1_OCU_OCSA32 *((volatile uint8_t*)(0x4002111CUL)) +#define FM4_MFT1_OCU_OCSA32 *((volatile uint8_t*)(0x4002111CUL)) +#define FM_MFT1_OCU_OCSB32 *((volatile uint8_t*)(0x4002111DUL)) +#define FM4_MFT1_OCU_OCSB32 *((volatile uint8_t*)(0x4002111DUL)) +#define FM_MFT1_OCU_OCSD32 *((volatile uint16_t*)(0x4002111EUL)) +#define FM4_MFT1_OCU_OCSD32 *((volatile uint16_t*)(0x4002111EUL)) +#define FM_MFT1_OCU_OCSA54 *((volatile uint8_t*)(0x40021120UL)) +#define FM4_MFT1_OCU_OCSA54 *((volatile uint8_t*)(0x40021120UL)) +#define FM_MFT1_OCU_OCSB54 *((volatile uint8_t*)(0x40021121UL)) +#define FM4_MFT1_OCU_OCSB54 *((volatile uint8_t*)(0x40021121UL)) +#define FM_MFT1_OCU_OCSD54 *((volatile uint16_t*)(0x40021122UL)) +#define FM4_MFT1_OCU_OCSD54 *((volatile uint16_t*)(0x40021122UL)) +#define FM_MFT1_OCU_OCSC *((volatile uint8_t*)(0x40021125UL)) +#define FM4_MFT1_OCU_OCSC *((volatile uint8_t*)(0x40021125UL)) +#define FM_MFT1_OCU_OCSE0 *((volatile uint16_t*)(0x40021128UL)) +#define FM4_MFT1_OCU_OCSE0 *((volatile uint16_t*)(0x40021128UL)) +#define FM_MFT1_OCU_OCSE1 *((volatile uint32_t*)(0x4002112CUL)) +#define FM4_MFT1_OCU_OCSE1 *((volatile uint32_t*)(0x4002112CUL)) +#define FM_MFT1_OCU_OCSE2 *((volatile uint16_t*)(0x40021130UL)) +#define FM4_MFT1_OCU_OCSE2 *((volatile uint16_t*)(0x40021130UL)) +#define FM_MFT1_OCU_OCSE3 *((volatile uint32_t*)(0x40021134UL)) +#define FM4_MFT1_OCU_OCSE3 *((volatile uint32_t*)(0x40021134UL)) +#define FM_MFT1_OCU_OCSE4 *((volatile uint16_t*)(0x40021138UL)) +#define FM4_MFT1_OCU_OCSE4 *((volatile uint16_t*)(0x40021138UL)) +#define FM_MFT1_OCU_OCSE5 *((volatile uint32_t*)(0x4002113CUL)) +#define FM4_MFT1_OCU_OCSE5 *((volatile uint32_t*)(0x4002113CUL)) +#define FM_MFT1_FRT_TCCP0 *((volatile uint16_t*)(0x40021142UL)) +#define FM4_MFT1_FRT_TCCP0 *((volatile uint16_t*)(0x40021142UL)) +#define FM_MFT1_FRT_TCDT0 *((volatile uint16_t*)(0x40021146UL)) +#define FM4_MFT1_FRT_TCDT0 *((volatile uint16_t*)(0x40021146UL)) +#define FM_MFT1_FRT_TCSA0 *((volatile uint16_t*)(0x40021148UL)) +#define FM4_MFT1_FRT_TCSA0 *((volatile uint16_t*)(0x40021148UL)) +#define FM_MFT1_FRT_TCSC0 *((volatile uint16_t*)(0x4002114AUL)) +#define FM4_MFT1_FRT_TCSC0 *((volatile uint16_t*)(0x4002114AUL)) +#define FM_MFT1_FRT_TCCP1 *((volatile uint16_t*)(0x4002114EUL)) +#define FM4_MFT1_FRT_TCCP1 *((volatile uint16_t*)(0x4002114EUL)) +#define FM_MFT1_FRT_TCDT1 *((volatile uint16_t*)(0x40021152UL)) +#define FM4_MFT1_FRT_TCDT1 *((volatile uint16_t*)(0x40021152UL)) +#define FM_MFT1_FRT_TCSA1 *((volatile uint16_t*)(0x40021154UL)) +#define FM4_MFT1_FRT_TCSA1 *((volatile uint16_t*)(0x40021154UL)) +#define FM_MFT1_FRT_TCSC1 *((volatile uint16_t*)(0x40021156UL)) +#define FM4_MFT1_FRT_TCSC1 *((volatile uint16_t*)(0x40021156UL)) +#define FM_MFT1_FRT_TCCP2 *((volatile uint16_t*)(0x4002115AUL)) +#define FM4_MFT1_FRT_TCCP2 *((volatile uint16_t*)(0x4002115AUL)) +#define FM_MFT1_FRT_TCDT2 *((volatile uint16_t*)(0x4002115EUL)) +#define FM4_MFT1_FRT_TCDT2 *((volatile uint16_t*)(0x4002115EUL)) +#define FM_MFT1_FRT_TCSA2 *((volatile uint16_t*)(0x40021160UL)) +#define FM4_MFT1_FRT_TCSA2 *((volatile uint16_t*)(0x40021160UL)) +#define FM_MFT1_FRT_TCSC2 *((volatile uint16_t*)(0x40021162UL)) +#define FM4_MFT1_FRT_TCSC2 *((volatile uint16_t*)(0x40021162UL)) +#define FM_MFT1_FRT_TCAL *((volatile uint32_t*)(0x40021164UL)) +#define FM4_MFT1_FRT_TCAL *((volatile uint32_t*)(0x40021164UL)) +#define FM_MFT1_OCU_OCFS10 *((volatile uint8_t*)(0x40021168UL)) +#define FM4_MFT1_OCU_OCFS10 *((volatile uint8_t*)(0x40021168UL)) +#define FM_MFT1_OCU_OCFS32 *((volatile uint8_t*)(0x40021169UL)) +#define FM4_MFT1_OCU_OCFS32 *((volatile uint8_t*)(0x40021169UL)) +#define FM_MFT1_OCU_OCFS54 *((volatile uint8_t*)(0x4002116AUL)) +#define FM4_MFT1_OCU_OCFS54 *((volatile uint8_t*)(0x4002116AUL)) +#define FM_MFT1_ICU_ICFS10 *((volatile uint8_t*)(0x4002116CUL)) +#define FM4_MFT1_ICU_ICFS10 *((volatile uint8_t*)(0x4002116CUL)) +#define FM_MFT1_ICU_ICFS32 *((volatile uint8_t*)(0x4002116DUL)) +#define FM4_MFT1_ICU_ICFS32 *((volatile uint8_t*)(0x4002116DUL)) +#define FM_MFT1_ADCMP_ACFS10 *((volatile uint8_t*)(0x40021170UL)) +#define FM4_MFT1_ADCMP_ACFS10 *((volatile uint8_t*)(0x40021170UL)) +#define FM_MFT1_ADCMP_ACFS32 *((volatile uint8_t*)(0x40021171UL)) +#define FM4_MFT1_ADCMP_ACFS32 *((volatile uint8_t*)(0x40021171UL)) +#define FM_MFT1_ADCMP_ACFS54 *((volatile uint8_t*)(0x40021172UL)) +#define FM4_MFT1_ADCMP_ACFS54 *((volatile uint8_t*)(0x40021172UL)) +#define FM_MFT1_ICU_ICCP0 *((volatile uint16_t*)(0x40021176UL)) +#define FM4_MFT1_ICU_ICCP0 *((volatile uint16_t*)(0x40021176UL)) +#define FM_MFT1_ICU_ICCP1 *((volatile uint16_t*)(0x4002117AUL)) +#define FM4_MFT1_ICU_ICCP1 *((volatile uint16_t*)(0x4002117AUL)) +#define FM_MFT1_ICU_ICCP2 *((volatile uint16_t*)(0x4002117EUL)) +#define FM4_MFT1_ICU_ICCP2 *((volatile uint16_t*)(0x4002117EUL)) +#define FM_MFT1_ICU_ICCP3 *((volatile uint16_t*)(0x40021182UL)) +#define FM4_MFT1_ICU_ICCP3 *((volatile uint16_t*)(0x40021182UL)) +#define FM_MFT1_ICU_ICSA10 *((volatile uint8_t*)(0x40021184UL)) +#define FM4_MFT1_ICU_ICSA10 *((volatile uint8_t*)(0x40021184UL)) +#define FM_MFT1_ICU_ICSB10 *((volatile uint8_t*)(0x40021185UL)) +#define FM4_MFT1_ICU_ICSB10 *((volatile uint8_t*)(0x40021185UL)) +#define FM_MFT1_ICU_ICSA32 *((volatile uint8_t*)(0x40021188UL)) +#define FM4_MFT1_ICU_ICSA32 *((volatile uint8_t*)(0x40021188UL)) +#define FM_MFT1_ICU_ICSB32 *((volatile uint8_t*)(0x40021189UL)) +#define FM4_MFT1_ICU_ICSB32 *((volatile uint8_t*)(0x40021189UL)) +#define FM_MFT1_WFG_WFTF10 *((volatile uint16_t*)(0x4002118EUL)) +#define FM4_MFT1_WFG_WFTF10 *((volatile uint16_t*)(0x4002118EUL)) +#define FM_MFT1_WFG_WFTA10 *((volatile uint16_t*)(0x40021190UL)) +#define FM4_MFT1_WFG_WFTA10 *((volatile uint16_t*)(0x40021190UL)) +#define FM_MFT1_WFG_WFTB10 *((volatile uint16_t*)(0x40021192UL)) +#define FM4_MFT1_WFG_WFTB10 *((volatile uint16_t*)(0x40021192UL)) +#define FM_MFT1_WFG_WFTF32 *((volatile uint16_t*)(0x40021196UL)) +#define FM4_MFT1_WFG_WFTF32 *((volatile uint16_t*)(0x40021196UL)) +#define FM_MFT1_WFG_WFTA32 *((volatile uint16_t*)(0x40021198UL)) +#define FM4_MFT1_WFG_WFTA32 *((volatile uint16_t*)(0x40021198UL)) +#define FM_MFT1_WFG_WFTB32 *((volatile uint16_t*)(0x4002119AUL)) +#define FM4_MFT1_WFG_WFTB32 *((volatile uint16_t*)(0x4002119AUL)) +#define FM_MFT1_WFG_WFTF54 *((volatile uint16_t*)(0x4002119EUL)) +#define FM4_MFT1_WFG_WFTF54 *((volatile uint16_t*)(0x4002119EUL)) +#define FM_MFT1_WFG_WFTA54 *((volatile uint16_t*)(0x400211A0UL)) +#define FM4_MFT1_WFG_WFTA54 *((volatile uint16_t*)(0x400211A0UL)) +#define FM_MFT1_WFG_WFTB54 *((volatile uint16_t*)(0x400211A2UL)) +#define FM4_MFT1_WFG_WFTB54 *((volatile uint16_t*)(0x400211A2UL)) +#define FM_MFT1_WFG_WFSA10 *((volatile uint16_t*)(0x400211A4UL)) +#define FM4_MFT1_WFG_WFSA10 *((volatile uint16_t*)(0x400211A4UL)) +#define FM_MFT1_WFG_WFSA32 *((volatile uint16_t*)(0x400211A8UL)) +#define FM4_MFT1_WFG_WFSA32 *((volatile uint16_t*)(0x400211A8UL)) +#define FM_MFT1_WFG_WFSA54 *((volatile uint16_t*)(0x400211ACUL)) +#define FM4_MFT1_WFG_WFSA54 *((volatile uint16_t*)(0x400211ACUL)) +#define FM_MFT1_WFG_WFIR *((volatile uint16_t*)(0x400211B0UL)) +#define FM4_MFT1_WFG_WFIR *((volatile uint16_t*)(0x400211B0UL)) +#define FM_MFT1_WFG_NZCL *((volatile uint16_t*)(0x400211B4UL)) +#define FM4_MFT1_WFG_NZCL *((volatile uint16_t*)(0x400211B4UL)) +#define FM_MFT1_ADCMP_ACMP0 *((volatile uint16_t*)(0x400211BAUL)) +#define FM4_MFT1_ADCMP_ACMP0 *((volatile uint16_t*)(0x400211BAUL)) +#define FM_MFT1_ADCMP_ACMP1 *((volatile uint16_t*)(0x400211BEUL)) +#define FM4_MFT1_ADCMP_ACMP1 *((volatile uint16_t*)(0x400211BEUL)) +#define FM_MFT1_ADCMP_ACMP2 *((volatile uint16_t*)(0x400211C2UL)) +#define FM4_MFT1_ADCMP_ACMP2 *((volatile uint16_t*)(0x400211C2UL)) +#define FM_MFT1_ADCMP_ACMP3 *((volatile uint16_t*)(0x400211C6UL)) +#define FM4_MFT1_ADCMP_ACMP3 *((volatile uint16_t*)(0x400211C6UL)) +#define FM_MFT1_ADCMP_ACMP4 *((volatile uint16_t*)(0x400211CAUL)) +#define FM4_MFT1_ADCMP_ACMP4 *((volatile uint16_t*)(0x400211CAUL)) +#define FM_MFT1_ADCMP_ACMP5 *((volatile uint16_t*)(0x400211CEUL)) +#define FM4_MFT1_ADCMP_ACMP5 *((volatile uint16_t*)(0x400211CEUL)) +#define FM_MFT1_ADCMP_ACSA *((volatile uint16_t*)(0x400211D0UL)) +#define FM4_MFT1_ADCMP_ACSA *((volatile uint16_t*)(0x400211D0UL)) +#define FM_MFT1_ADCMP_ACSC0 *((volatile uint8_t*)(0x400211D4UL)) +#define FM4_MFT1_ADCMP_ACSC0 *((volatile uint8_t*)(0x400211D4UL)) +#define FM_MFT1_ADCMP_ACSD0 *((volatile uint8_t*)(0x400211D5UL)) +#define FM4_MFT1_ADCMP_ACSD0 *((volatile uint8_t*)(0x400211D5UL)) +#define FM_MFT1_ADCMP_ACMC0 *((volatile uint8_t*)(0x400211D6UL)) +#define FM4_MFT1_ADCMP_ACMC0 *((volatile uint8_t*)(0x400211D6UL)) +#define FM_MFT1_ADCMP_ACSC1 *((volatile uint8_t*)(0x400211D8UL)) +#define FM4_MFT1_ADCMP_ACSC1 *((volatile uint8_t*)(0x400211D8UL)) +#define FM_MFT1_ADCMP_ACSD1 *((volatile uint8_t*)(0x400211D9UL)) +#define FM4_MFT1_ADCMP_ACSD1 *((volatile uint8_t*)(0x400211D9UL)) +#define FM_MFT1_ADCMP_ACMC1 *((volatile uint8_t*)(0x400211DAUL)) +#define FM4_MFT1_ADCMP_ACMC1 *((volatile uint8_t*)(0x400211DAUL)) +#define FM_MFT1_ADCMP_ACSC2 *((volatile uint8_t*)(0x400211DCUL)) +#define FM4_MFT1_ADCMP_ACSC2 *((volatile uint8_t*)(0x400211DCUL)) +#define FM_MFT1_ADCMP_ACSD2 *((volatile uint8_t*)(0x400211DDUL)) +#define FM4_MFT1_ADCMP_ACSD2 *((volatile uint8_t*)(0x400211DDUL)) +#define FM_MFT1_ADCMP_ACMC2 *((volatile uint8_t*)(0x400211DEUL)) +#define FM4_MFT1_ADCMP_ACMC2 *((volatile uint8_t*)(0x400211DEUL)) +#define FM_MFT1_ADCMP_ACSC3 *((volatile uint8_t*)(0x400211E0UL)) +#define FM4_MFT1_ADCMP_ACSC3 *((volatile uint8_t*)(0x400211E0UL)) +#define FM_MFT1_ADCMP_ACSD3 *((volatile uint8_t*)(0x400211E1UL)) +#define FM4_MFT1_ADCMP_ACSD3 *((volatile uint8_t*)(0x400211E1UL)) +#define FM_MFT1_ADCMP_ACMC3 *((volatile uint8_t*)(0x400211E2UL)) +#define FM4_MFT1_ADCMP_ACMC3 *((volatile uint8_t*)(0x400211E2UL)) +#define FM_MFT1_ADCMP_ACSC4 *((volatile uint8_t*)(0x400211E4UL)) +#define FM4_MFT1_ADCMP_ACSC4 *((volatile uint8_t*)(0x400211E4UL)) +#define FM_MFT1_ADCMP_ACSD4 *((volatile uint8_t*)(0x400211E5UL)) +#define FM4_MFT1_ADCMP_ACSD4 *((volatile uint8_t*)(0x400211E5UL)) +#define FM_MFT1_ADCMP_ACMC4 *((volatile uint8_t*)(0x400211E6UL)) +#define FM4_MFT1_ADCMP_ACMC4 *((volatile uint8_t*)(0x400211E6UL)) +#define FM_MFT1_ADCMP_ACSC5 *((volatile uint8_t*)(0x400211E8UL)) +#define FM4_MFT1_ADCMP_ACSC5 *((volatile uint8_t*)(0x400211E8UL)) +#define FM_MFT1_ADCMP_ACSD5 *((volatile uint8_t*)(0x400211E9UL)) +#define FM4_MFT1_ADCMP_ACSD5 *((volatile uint8_t*)(0x400211E9UL)) +#define FM_MFT1_ADCMP_ACMC5 *((volatile uint8_t*)(0x400211EAUL)) +#define FM4_MFT1_ADCMP_ACMC5 *((volatile uint8_t*)(0x400211EAUL)) +#define FM_MFT1_FRT_TCSD *((volatile uint8_t*)(0x400211ECUL)) +#define FM4_MFT1_FRT_TCSD *((volatile uint8_t*)(0x400211ECUL)) + +/******************************************************************************* +* MFT Registers MFT2 +* Register Definition +*******************************************************************************/ +#define FM_MFT2_OCU_OCCP0 *((volatile uint16_t*)(0x40022102UL)) +#define FM4_MFT2_OCU_OCCP0 *((volatile uint16_t*)(0x40022102UL)) +#define FM_MFT2_OCU_OCCP1 *((volatile uint16_t*)(0x40022106UL)) +#define FM4_MFT2_OCU_OCCP1 *((volatile uint16_t*)(0x40022106UL)) +#define FM_MFT2_OCU_OCCP2 *((volatile uint16_t*)(0x4002210AUL)) +#define FM4_MFT2_OCU_OCCP2 *((volatile uint16_t*)(0x4002210AUL)) +#define FM_MFT2_OCU_OCCP3 *((volatile uint16_t*)(0x4002210EUL)) +#define FM4_MFT2_OCU_OCCP3 *((volatile uint16_t*)(0x4002210EUL)) +#define FM_MFT2_OCU_OCCP4 *((volatile uint16_t*)(0x40022112UL)) +#define FM4_MFT2_OCU_OCCP4 *((volatile uint16_t*)(0x40022112UL)) +#define FM_MFT2_OCU_OCCP5 *((volatile uint16_t*)(0x40022116UL)) +#define FM4_MFT2_OCU_OCCP5 *((volatile uint16_t*)(0x40022116UL)) +#define FM_MFT2_OCU_OCSA10 *((volatile uint8_t*)(0x40022118UL)) +#define FM4_MFT2_OCU_OCSA10 *((volatile uint8_t*)(0x40022118UL)) +#define FM_MFT2_OCU_OCSB10 *((volatile uint8_t*)(0x40022119UL)) +#define FM4_MFT2_OCU_OCSB10 *((volatile uint8_t*)(0x40022119UL)) +#define FM_MFT2_OCU_OCSD10 *((volatile uint16_t*)(0x4002211AUL)) +#define FM4_MFT2_OCU_OCSD10 *((volatile uint16_t*)(0x4002211AUL)) +#define FM_MFT2_OCU_OCSA32 *((volatile uint8_t*)(0x4002211CUL)) +#define FM4_MFT2_OCU_OCSA32 *((volatile uint8_t*)(0x4002211CUL)) +#define FM_MFT2_OCU_OCSB32 *((volatile uint8_t*)(0x4002211DUL)) +#define FM4_MFT2_OCU_OCSB32 *((volatile uint8_t*)(0x4002211DUL)) +#define FM_MFT2_OCU_OCSD32 *((volatile uint16_t*)(0x4002211EUL)) +#define FM4_MFT2_OCU_OCSD32 *((volatile uint16_t*)(0x4002211EUL)) +#define FM_MFT2_OCU_OCSA54 *((volatile uint8_t*)(0x40022120UL)) +#define FM4_MFT2_OCU_OCSA54 *((volatile uint8_t*)(0x40022120UL)) +#define FM_MFT2_OCU_OCSB54 *((volatile uint8_t*)(0x40022121UL)) +#define FM4_MFT2_OCU_OCSB54 *((volatile uint8_t*)(0x40022121UL)) +#define FM_MFT2_OCU_OCSD54 *((volatile uint16_t*)(0x40022122UL)) +#define FM4_MFT2_OCU_OCSD54 *((volatile uint16_t*)(0x40022122UL)) +#define FM_MFT2_OCU_OCSC *((volatile uint8_t*)(0x40022125UL)) +#define FM4_MFT2_OCU_OCSC *((volatile uint8_t*)(0x40022125UL)) +#define FM_MFT2_OCU_OCSE0 *((volatile uint16_t*)(0x40022128UL)) +#define FM4_MFT2_OCU_OCSE0 *((volatile uint16_t*)(0x40022128UL)) +#define FM_MFT2_OCU_OCSE1 *((volatile uint32_t*)(0x4002212CUL)) +#define FM4_MFT2_OCU_OCSE1 *((volatile uint32_t*)(0x4002212CUL)) +#define FM_MFT2_OCU_OCSE2 *((volatile uint16_t*)(0x40022130UL)) +#define FM4_MFT2_OCU_OCSE2 *((volatile uint16_t*)(0x40022130UL)) +#define FM_MFT2_OCU_OCSE3 *((volatile uint32_t*)(0x40022134UL)) +#define FM4_MFT2_OCU_OCSE3 *((volatile uint32_t*)(0x40022134UL)) +#define FM_MFT2_OCU_OCSE4 *((volatile uint16_t*)(0x40022138UL)) +#define FM4_MFT2_OCU_OCSE4 *((volatile uint16_t*)(0x40022138UL)) +#define FM_MFT2_OCU_OCSE5 *((volatile uint32_t*)(0x4002213CUL)) +#define FM4_MFT2_OCU_OCSE5 *((volatile uint32_t*)(0x4002213CUL)) +#define FM_MFT2_FRT_TCCP0 *((volatile uint16_t*)(0x40022142UL)) +#define FM4_MFT2_FRT_TCCP0 *((volatile uint16_t*)(0x40022142UL)) +#define FM_MFT2_FRT_TCDT0 *((volatile uint16_t*)(0x40022146UL)) +#define FM4_MFT2_FRT_TCDT0 *((volatile uint16_t*)(0x40022146UL)) +#define FM_MFT2_FRT_TCSA0 *((volatile uint16_t*)(0x40022148UL)) +#define FM4_MFT2_FRT_TCSA0 *((volatile uint16_t*)(0x40022148UL)) +#define FM_MFT2_FRT_TCSC0 *((volatile uint16_t*)(0x4002214AUL)) +#define FM4_MFT2_FRT_TCSC0 *((volatile uint16_t*)(0x4002214AUL)) +#define FM_MFT2_FRT_TCCP1 *((volatile uint16_t*)(0x4002214EUL)) +#define FM4_MFT2_FRT_TCCP1 *((volatile uint16_t*)(0x4002214EUL)) +#define FM_MFT2_FRT_TCDT1 *((volatile uint16_t*)(0x40022152UL)) +#define FM4_MFT2_FRT_TCDT1 *((volatile uint16_t*)(0x40022152UL)) +#define FM_MFT2_FRT_TCSA1 *((volatile uint16_t*)(0x40022154UL)) +#define FM4_MFT2_FRT_TCSA1 *((volatile uint16_t*)(0x40022154UL)) +#define FM_MFT2_FRT_TCSC1 *((volatile uint16_t*)(0x40022156UL)) +#define FM4_MFT2_FRT_TCSC1 *((volatile uint16_t*)(0x40022156UL)) +#define FM_MFT2_FRT_TCCP2 *((volatile uint16_t*)(0x4002215AUL)) +#define FM4_MFT2_FRT_TCCP2 *((volatile uint16_t*)(0x4002215AUL)) +#define FM_MFT2_FRT_TCDT2 *((volatile uint16_t*)(0x4002215EUL)) +#define FM4_MFT2_FRT_TCDT2 *((volatile uint16_t*)(0x4002215EUL)) +#define FM_MFT2_FRT_TCSA2 *((volatile uint16_t*)(0x40022160UL)) +#define FM4_MFT2_FRT_TCSA2 *((volatile uint16_t*)(0x40022160UL)) +#define FM_MFT2_FRT_TCSC2 *((volatile uint16_t*)(0x40022162UL)) +#define FM4_MFT2_FRT_TCSC2 *((volatile uint16_t*)(0x40022162UL)) +#define FM_MFT2_FRT_TCAL *((volatile uint32_t*)(0x40022164UL)) +#define FM4_MFT2_FRT_TCAL *((volatile uint32_t*)(0x40022164UL)) +#define FM_MFT2_OCU_OCFS10 *((volatile uint8_t*)(0x40022168UL)) +#define FM4_MFT2_OCU_OCFS10 *((volatile uint8_t*)(0x40022168UL)) +#define FM_MFT2_OCU_OCFS32 *((volatile uint8_t*)(0x40022169UL)) +#define FM4_MFT2_OCU_OCFS32 *((volatile uint8_t*)(0x40022169UL)) +#define FM_MFT2_OCU_OCFS54 *((volatile uint8_t*)(0x4002216AUL)) +#define FM4_MFT2_OCU_OCFS54 *((volatile uint8_t*)(0x4002216AUL)) +#define FM_MFT2_ICU_ICFS10 *((volatile uint8_t*)(0x4002216CUL)) +#define FM4_MFT2_ICU_ICFS10 *((volatile uint8_t*)(0x4002216CUL)) +#define FM_MFT2_ICU_ICFS32 *((volatile uint8_t*)(0x4002216DUL)) +#define FM4_MFT2_ICU_ICFS32 *((volatile uint8_t*)(0x4002216DUL)) +#define FM_MFT2_ADCMP_ACFS10 *((volatile uint8_t*)(0x40022170UL)) +#define FM4_MFT2_ADCMP_ACFS10 *((volatile uint8_t*)(0x40022170UL)) +#define FM_MFT2_ADCMP_ACFS32 *((volatile uint8_t*)(0x40022171UL)) +#define FM4_MFT2_ADCMP_ACFS32 *((volatile uint8_t*)(0x40022171UL)) +#define FM_MFT2_ADCMP_ACFS54 *((volatile uint8_t*)(0x40022172UL)) +#define FM4_MFT2_ADCMP_ACFS54 *((volatile uint8_t*)(0x40022172UL)) +#define FM_MFT2_ICU_ICCP0 *((volatile uint16_t*)(0x40022176UL)) +#define FM4_MFT2_ICU_ICCP0 *((volatile uint16_t*)(0x40022176UL)) +#define FM_MFT2_ICU_ICCP1 *((volatile uint16_t*)(0x4002217AUL)) +#define FM4_MFT2_ICU_ICCP1 *((volatile uint16_t*)(0x4002217AUL)) +#define FM_MFT2_ICU_ICCP2 *((volatile uint16_t*)(0x4002217EUL)) +#define FM4_MFT2_ICU_ICCP2 *((volatile uint16_t*)(0x4002217EUL)) +#define FM_MFT2_ICU_ICCP3 *((volatile uint16_t*)(0x40022182UL)) +#define FM4_MFT2_ICU_ICCP3 *((volatile uint16_t*)(0x40022182UL)) +#define FM_MFT2_ICU_ICSA10 *((volatile uint8_t*)(0x40022184UL)) +#define FM4_MFT2_ICU_ICSA10 *((volatile uint8_t*)(0x40022184UL)) +#define FM_MFT2_ICU_ICSB10 *((volatile uint8_t*)(0x40022185UL)) +#define FM4_MFT2_ICU_ICSB10 *((volatile uint8_t*)(0x40022185UL)) +#define FM_MFT2_ICU_ICSA32 *((volatile uint8_t*)(0x40022188UL)) +#define FM4_MFT2_ICU_ICSA32 *((volatile uint8_t*)(0x40022188UL)) +#define FM_MFT2_ICU_ICSB32 *((volatile uint8_t*)(0x40022189UL)) +#define FM4_MFT2_ICU_ICSB32 *((volatile uint8_t*)(0x40022189UL)) +#define FM_MFT2_WFG_WFTF10 *((volatile uint16_t*)(0x4002218EUL)) +#define FM4_MFT2_WFG_WFTF10 *((volatile uint16_t*)(0x4002218EUL)) +#define FM_MFT2_WFG_WFTA10 *((volatile uint16_t*)(0x40022190UL)) +#define FM4_MFT2_WFG_WFTA10 *((volatile uint16_t*)(0x40022190UL)) +#define FM_MFT2_WFG_WFTB10 *((volatile uint16_t*)(0x40022192UL)) +#define FM4_MFT2_WFG_WFTB10 *((volatile uint16_t*)(0x40022192UL)) +#define FM_MFT2_WFG_WFTF32 *((volatile uint16_t*)(0x40022196UL)) +#define FM4_MFT2_WFG_WFTF32 *((volatile uint16_t*)(0x40022196UL)) +#define FM_MFT2_WFG_WFTA32 *((volatile uint16_t*)(0x40022198UL)) +#define FM4_MFT2_WFG_WFTA32 *((volatile uint16_t*)(0x40022198UL)) +#define FM_MFT2_WFG_WFTB32 *((volatile uint16_t*)(0x4002219AUL)) +#define FM4_MFT2_WFG_WFTB32 *((volatile uint16_t*)(0x4002219AUL)) +#define FM_MFT2_WFG_WFTF54 *((volatile uint16_t*)(0x4002219EUL)) +#define FM4_MFT2_WFG_WFTF54 *((volatile uint16_t*)(0x4002219EUL)) +#define FM_MFT2_WFG_WFTA54 *((volatile uint16_t*)(0x400221A0UL)) +#define FM4_MFT2_WFG_WFTA54 *((volatile uint16_t*)(0x400221A0UL)) +#define FM_MFT2_WFG_WFTB54 *((volatile uint16_t*)(0x400221A2UL)) +#define FM4_MFT2_WFG_WFTB54 *((volatile uint16_t*)(0x400221A2UL)) +#define FM_MFT2_WFG_WFSA10 *((volatile uint16_t*)(0x400221A4UL)) +#define FM4_MFT2_WFG_WFSA10 *((volatile uint16_t*)(0x400221A4UL)) +#define FM_MFT2_WFG_WFSA32 *((volatile uint16_t*)(0x400221A8UL)) +#define FM4_MFT2_WFG_WFSA32 *((volatile uint16_t*)(0x400221A8UL)) +#define FM_MFT2_WFG_WFSA54 *((volatile uint16_t*)(0x400221ACUL)) +#define FM4_MFT2_WFG_WFSA54 *((volatile uint16_t*)(0x400221ACUL)) +#define FM_MFT2_WFG_WFIR *((volatile uint16_t*)(0x400221B0UL)) +#define FM4_MFT2_WFG_WFIR *((volatile uint16_t*)(0x400221B0UL)) +#define FM_MFT2_WFG_NZCL *((volatile uint16_t*)(0x400221B4UL)) +#define FM4_MFT2_WFG_NZCL *((volatile uint16_t*)(0x400221B4UL)) +#define FM_MFT2_ADCMP_ACMP0 *((volatile uint16_t*)(0x400221BAUL)) +#define FM4_MFT2_ADCMP_ACMP0 *((volatile uint16_t*)(0x400221BAUL)) +#define FM_MFT2_ADCMP_ACMP1 *((volatile uint16_t*)(0x400221BEUL)) +#define FM4_MFT2_ADCMP_ACMP1 *((volatile uint16_t*)(0x400221BEUL)) +#define FM_MFT2_ADCMP_ACMP2 *((volatile uint16_t*)(0x400221C2UL)) +#define FM4_MFT2_ADCMP_ACMP2 *((volatile uint16_t*)(0x400221C2UL)) +#define FM_MFT2_ADCMP_ACMP3 *((volatile uint16_t*)(0x400221C6UL)) +#define FM4_MFT2_ADCMP_ACMP3 *((volatile uint16_t*)(0x400221C6UL)) +#define FM_MFT2_ADCMP_ACMP4 *((volatile uint16_t*)(0x400221CAUL)) +#define FM4_MFT2_ADCMP_ACMP4 *((volatile uint16_t*)(0x400221CAUL)) +#define FM_MFT2_ADCMP_ACMP5 *((volatile uint16_t*)(0x400221CEUL)) +#define FM4_MFT2_ADCMP_ACMP5 *((volatile uint16_t*)(0x400221CEUL)) +#define FM_MFT2_ADCMP_ACSA *((volatile uint16_t*)(0x400221D0UL)) +#define FM4_MFT2_ADCMP_ACSA *((volatile uint16_t*)(0x400221D0UL)) +#define FM_MFT2_ADCMP_ACSC0 *((volatile uint8_t*)(0x400221D4UL)) +#define FM4_MFT2_ADCMP_ACSC0 *((volatile uint8_t*)(0x400221D4UL)) +#define FM_MFT2_ADCMP_ACSD0 *((volatile uint8_t*)(0x400221D5UL)) +#define FM4_MFT2_ADCMP_ACSD0 *((volatile uint8_t*)(0x400221D5UL)) +#define FM_MFT2_ADCMP_ACMC0 *((volatile uint8_t*)(0x400221D6UL)) +#define FM4_MFT2_ADCMP_ACMC0 *((volatile uint8_t*)(0x400221D6UL)) +#define FM_MFT2_ADCMP_ACSC1 *((volatile uint8_t*)(0x400221D8UL)) +#define FM4_MFT2_ADCMP_ACSC1 *((volatile uint8_t*)(0x400221D8UL)) +#define FM_MFT2_ADCMP_ACSD1 *((volatile uint8_t*)(0x400221D9UL)) +#define FM4_MFT2_ADCMP_ACSD1 *((volatile uint8_t*)(0x400221D9UL)) +#define FM_MFT2_ADCMP_ACMC1 *((volatile uint8_t*)(0x400221DAUL)) +#define FM4_MFT2_ADCMP_ACMC1 *((volatile uint8_t*)(0x400221DAUL)) +#define FM_MFT2_ADCMP_ACSC2 *((volatile uint8_t*)(0x400221DCUL)) +#define FM4_MFT2_ADCMP_ACSC2 *((volatile uint8_t*)(0x400221DCUL)) +#define FM_MFT2_ADCMP_ACSD2 *((volatile uint8_t*)(0x400221DDUL)) +#define FM4_MFT2_ADCMP_ACSD2 *((volatile uint8_t*)(0x400221DDUL)) +#define FM_MFT2_ADCMP_ACMC2 *((volatile uint8_t*)(0x400221DEUL)) +#define FM4_MFT2_ADCMP_ACMC2 *((volatile uint8_t*)(0x400221DEUL)) +#define FM_MFT2_ADCMP_ACSC3 *((volatile uint8_t*)(0x400221E0UL)) +#define FM4_MFT2_ADCMP_ACSC3 *((volatile uint8_t*)(0x400221E0UL)) +#define FM_MFT2_ADCMP_ACSD3 *((volatile uint8_t*)(0x400221E1UL)) +#define FM4_MFT2_ADCMP_ACSD3 *((volatile uint8_t*)(0x400221E1UL)) +#define FM_MFT2_ADCMP_ACMC3 *((volatile uint8_t*)(0x400221E2UL)) +#define FM4_MFT2_ADCMP_ACMC3 *((volatile uint8_t*)(0x400221E2UL)) +#define FM_MFT2_ADCMP_ACSC4 *((volatile uint8_t*)(0x400221E4UL)) +#define FM4_MFT2_ADCMP_ACSC4 *((volatile uint8_t*)(0x400221E4UL)) +#define FM_MFT2_ADCMP_ACSD4 *((volatile uint8_t*)(0x400221E5UL)) +#define FM4_MFT2_ADCMP_ACSD4 *((volatile uint8_t*)(0x400221E5UL)) +#define FM_MFT2_ADCMP_ACMC4 *((volatile uint8_t*)(0x400221E6UL)) +#define FM4_MFT2_ADCMP_ACMC4 *((volatile uint8_t*)(0x400221E6UL)) +#define FM_MFT2_ADCMP_ACSC5 *((volatile uint8_t*)(0x400221E8UL)) +#define FM4_MFT2_ADCMP_ACSC5 *((volatile uint8_t*)(0x400221E8UL)) +#define FM_MFT2_ADCMP_ACSD5 *((volatile uint8_t*)(0x400221E9UL)) +#define FM4_MFT2_ADCMP_ACSD5 *((volatile uint8_t*)(0x400221E9UL)) +#define FM_MFT2_ADCMP_ACMC5 *((volatile uint8_t*)(0x400221EAUL)) +#define FM4_MFT2_ADCMP_ACMC5 *((volatile uint8_t*)(0x400221EAUL)) +#define FM_MFT2_FRT_TCSD *((volatile uint8_t*)(0x400221ECUL)) +#define FM4_MFT2_FRT_TCSD *((volatile uint8_t*)(0x400221ECUL)) + +/******************************************************************************* +* PCRC Registers PCRC +* Register Definition +*******************************************************************************/ +#define FM_PCRC_PCRC_POLY *((volatile uint32_t*)(0x40080000UL)) +#define FM4_PCRC_PCRC_POLY *((volatile uint32_t*)(0x40080000UL)) +#define FM_PCRC_PCRC_SEED *((volatile uint32_t*)(0x40080004UL)) +#define FM4_PCRC_PCRC_SEED *((volatile uint32_t*)(0x40080004UL)) +#define FM_PCRC_PCRC_FXOR *((volatile uint32_t*)(0x40080008UL)) +#define FM4_PCRC_PCRC_FXOR *((volatile uint32_t*)(0x40080008UL)) +#define FM_PCRC_PCRC_CFG *((volatile uint32_t*)(0x4008000CUL)) +#define FM4_PCRC_PCRC_CFG *((volatile uint32_t*)(0x4008000CUL)) +#define FM_PCRC_PCRC_WR *((volatile uint32_t*)(0x40080010UL)) +#define FM4_PCRC_PCRC_WR *((volatile uint32_t*)(0x40080010UL)) +#define FM_PCRC_PCRC_RD *((volatile uint32_t*)(0x40080014UL)) +#define FM4_PCRC_PCRC_RD *((volatile uint32_t*)(0x40080014UL)) + +/******************************************************************************* +* QPRC Registers QPRC0 +* Register Definition +*******************************************************************************/ +#define FM_QPRC0_QPCR *((volatile uint16_t*)(0x40026000UL)) +#define FM4_QPRC0_QPCR *((volatile uint16_t*)(0x40026000UL)) +#define FM_QPRC0_QRCR *((volatile uint16_t*)(0x40026004UL)) +#define FM4_QPRC0_QRCR *((volatile uint16_t*)(0x40026004UL)) +#define FM_QPRC0_QPCCR *((volatile uint16_t*)(0x40026008UL)) +#define FM4_QPRC0_QPCCR *((volatile uint16_t*)(0x40026008UL)) +#define FM_QPRC0_QPRCR *((volatile uint16_t*)(0x4002600CUL)) +#define FM4_QPRC0_QPRCR *((volatile uint16_t*)(0x4002600CUL)) +#define FM_QPRC0_QMPR *((volatile uint16_t*)(0x40026010UL)) +#define FM4_QPRC0_QMPR *((volatile uint16_t*)(0x40026010UL)) +#define FM_QPRC0_QICRL *((volatile uint8_t*)(0x40026014UL)) +#define FM4_QPRC0_QICRL *((volatile uint8_t*)(0x40026014UL)) +#define FM_QPRC0_QICRH *((volatile uint8_t*)(0x40026015UL)) +#define FM4_QPRC0_QICRH *((volatile uint8_t*)(0x40026015UL)) +#define FM_QPRC0_QCR *((volatile uint16_t*)(0x40026018UL)) +#define FM4_QPRC0_QCR *((volatile uint16_t*)(0x40026018UL)) +#define FM_QPRC0_QECR *((volatile uint16_t*)(0x4002601CUL)) +#define FM4_QPRC0_QECR *((volatile uint16_t*)(0x4002601CUL)) +#define FM_QPRC0_QPRCRR *((volatile uint32_t*)(0x4002603CUL)) +#define FM4_QPRC0_QPRCRR *((volatile uint32_t*)(0x4002603CUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC0_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC0_NF_NFCTLA *((volatile uint8_t*)(0x40026100UL)) +#define FM4_QPRC0_NF_NFCTLA *((volatile uint8_t*)(0x40026100UL)) +#define FM_QPRC0_NF_NFCTLB *((volatile uint8_t*)(0x40026104UL)) +#define FM4_QPRC0_NF_NFCTLB *((volatile uint8_t*)(0x40026104UL)) +#define FM_QPRC0_NF_NFCTLZ *((volatile uint8_t*)(0x40026108UL)) +#define FM4_QPRC0_NF_NFCTLZ *((volatile uint8_t*)(0x40026108UL)) + +/******************************************************************************* +* QPRC Registers QPRC1 +* Register Definition +*******************************************************************************/ +#define FM_QPRC1_QPCR *((volatile uint16_t*)(0x40026040UL)) +#define FM4_QPRC1_QPCR *((volatile uint16_t*)(0x40026040UL)) +#define FM_QPRC1_QRCR *((volatile uint16_t*)(0x40026044UL)) +#define FM4_QPRC1_QRCR *((volatile uint16_t*)(0x40026044UL)) +#define FM_QPRC1_QPCCR *((volatile uint16_t*)(0x40026048UL)) +#define FM4_QPRC1_QPCCR *((volatile uint16_t*)(0x40026048UL)) +#define FM_QPRC1_QPRCR *((volatile uint16_t*)(0x4002604CUL)) +#define FM4_QPRC1_QPRCR *((volatile uint16_t*)(0x4002604CUL)) +#define FM_QPRC1_QMPR *((volatile uint16_t*)(0x40026050UL)) +#define FM4_QPRC1_QMPR *((volatile uint16_t*)(0x40026050UL)) +#define FM_QPRC1_QICRL *((volatile uint8_t*)(0x40026054UL)) +#define FM4_QPRC1_QICRL *((volatile uint8_t*)(0x40026054UL)) +#define FM_QPRC1_QICRH *((volatile uint8_t*)(0x40026055UL)) +#define FM4_QPRC1_QICRH *((volatile uint8_t*)(0x40026055UL)) +#define FM_QPRC1_QCR *((volatile uint16_t*)(0x40026058UL)) +#define FM4_QPRC1_QCR *((volatile uint16_t*)(0x40026058UL)) +#define FM_QPRC1_QECR *((volatile uint16_t*)(0x4002605CUL)) +#define FM4_QPRC1_QECR *((volatile uint16_t*)(0x4002605CUL)) +#define FM_QPRC1_QPRCRR *((volatile uint32_t*)(0x4002607CUL)) +#define FM4_QPRC1_QPRCRR *((volatile uint32_t*)(0x4002607CUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC1_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC1_NF_NFCTLA *((volatile uint8_t*)(0x40026110UL)) +#define FM4_QPRC1_NF_NFCTLA *((volatile uint8_t*)(0x40026110UL)) +#define FM_QPRC1_NF_NFCTLB *((volatile uint8_t*)(0x40026114UL)) +#define FM4_QPRC1_NF_NFCTLB *((volatile uint8_t*)(0x40026114UL)) +#define FM_QPRC1_NF_NFCTLZ *((volatile uint8_t*)(0x40026118UL)) +#define FM4_QPRC1_NF_NFCTLZ *((volatile uint8_t*)(0x40026118UL)) + +/******************************************************************************* +* QPRC Registers QPRC2 +* Register Definition +*******************************************************************************/ +#define FM_QPRC2_QPCR *((volatile uint16_t*)(0x40026080UL)) +#define FM4_QPRC2_QPCR *((volatile uint16_t*)(0x40026080UL)) +#define FM_QPRC2_QRCR *((volatile uint16_t*)(0x40026084UL)) +#define FM4_QPRC2_QRCR *((volatile uint16_t*)(0x40026084UL)) +#define FM_QPRC2_QPCCR *((volatile uint16_t*)(0x40026088UL)) +#define FM4_QPRC2_QPCCR *((volatile uint16_t*)(0x40026088UL)) +#define FM_QPRC2_QPRCR *((volatile uint16_t*)(0x4002608CUL)) +#define FM4_QPRC2_QPRCR *((volatile uint16_t*)(0x4002608CUL)) +#define FM_QPRC2_QMPR *((volatile uint16_t*)(0x40026090UL)) +#define FM4_QPRC2_QMPR *((volatile uint16_t*)(0x40026090UL)) +#define FM_QPRC2_QICRL *((volatile uint8_t*)(0x40026094UL)) +#define FM4_QPRC2_QICRL *((volatile uint8_t*)(0x40026094UL)) +#define FM_QPRC2_QICRH *((volatile uint8_t*)(0x40026095UL)) +#define FM4_QPRC2_QICRH *((volatile uint8_t*)(0x40026095UL)) +#define FM_QPRC2_QCR *((volatile uint16_t*)(0x40026098UL)) +#define FM4_QPRC2_QCR *((volatile uint16_t*)(0x40026098UL)) +#define FM_QPRC2_QECR *((volatile uint16_t*)(0x4002609CUL)) +#define FM4_QPRC2_QECR *((volatile uint16_t*)(0x4002609CUL)) +#define FM_QPRC2_QPRCRR *((volatile uint32_t*)(0x400260BCUL)) +#define FM4_QPRC2_QPRCRR *((volatile uint32_t*)(0x400260BCUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC2_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC2_NF_NFCTLA *((volatile uint8_t*)(0x40026120UL)) +#define FM4_QPRC2_NF_NFCTLA *((volatile uint8_t*)(0x40026120UL)) +#define FM_QPRC2_NF_NFCTLB *((volatile uint8_t*)(0x40026124UL)) +#define FM4_QPRC2_NF_NFCTLB *((volatile uint8_t*)(0x40026124UL)) +#define FM_QPRC2_NF_NFCTLZ *((volatile uint8_t*)(0x40026128UL)) +#define FM4_QPRC2_NF_NFCTLZ *((volatile uint8_t*)(0x40026128UL)) + +/******************************************************************************* +* QPRC Registers QPRC3 +* Register Definition +*******************************************************************************/ +#define FM_QPRC3_QPCR *((volatile uint16_t*)(0x400260C0UL)) +#define FM4_QPRC3_QPCR *((volatile uint16_t*)(0x400260C0UL)) +#define FM_QPRC3_QRCR *((volatile uint16_t*)(0x400260C4UL)) +#define FM4_QPRC3_QRCR *((volatile uint16_t*)(0x400260C4UL)) +#define FM_QPRC3_QPCCR *((volatile uint16_t*)(0x400260C8UL)) +#define FM4_QPRC3_QPCCR *((volatile uint16_t*)(0x400260C8UL)) +#define FM_QPRC3_QPRCR *((volatile uint16_t*)(0x400260CCUL)) +#define FM4_QPRC3_QPRCR *((volatile uint16_t*)(0x400260CCUL)) +#define FM_QPRC3_QMPR *((volatile uint16_t*)(0x400260D0UL)) +#define FM4_QPRC3_QMPR *((volatile uint16_t*)(0x400260D0UL)) +#define FM_QPRC3_QICRL *((volatile uint8_t*)(0x400260D4UL)) +#define FM4_QPRC3_QICRL *((volatile uint8_t*)(0x400260D4UL)) +#define FM_QPRC3_QICRH *((volatile uint8_t*)(0x400260D5UL)) +#define FM4_QPRC3_QICRH *((volatile uint8_t*)(0x400260D5UL)) +#define FM_QPRC3_QCR *((volatile uint16_t*)(0x400260D8UL)) +#define FM4_QPRC3_QCR *((volatile uint16_t*)(0x400260D8UL)) +#define FM_QPRC3_QECR *((volatile uint16_t*)(0x400260DCUL)) +#define FM4_QPRC3_QECR *((volatile uint16_t*)(0x400260DCUL)) +#define FM_QPRC3_QPRCRR *((volatile uint32_t*)(0x400260FCUL)) +#define FM4_QPRC3_QPRCRR *((volatile uint32_t*)(0x400260FCUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC3_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC3_NF_NFCTLA *((volatile uint8_t*)(0x40026130UL)) +#define FM4_QPRC3_NF_NFCTLA *((volatile uint8_t*)(0x40026130UL)) +#define FM_QPRC3_NF_NFCTLB *((volatile uint8_t*)(0x40026134UL)) +#define FM4_QPRC3_NF_NFCTLB *((volatile uint8_t*)(0x40026134UL)) +#define FM_QPRC3_NF_NFCTLZ *((volatile uint8_t*)(0x40026138UL)) +#define FM4_QPRC3_NF_NFCTLZ *((volatile uint8_t*)(0x40026138UL)) + +/******************************************************************************* +* RTC Registers RTC +* Register Definition +*******************************************************************************/ +#define FM_RTC_WTCR10 *((volatile uint8_t*)(0x4003B100UL)) +#define FM4_RTC_WTCR10 *((volatile uint8_t*)(0x4003B100UL)) +#define FM_RTC_WTCR11 *((volatile uint8_t*)(0x4003B104UL)) +#define FM4_RTC_WTCR11 *((volatile uint8_t*)(0x4003B104UL)) +#define FM_RTC_WTCR12 *((volatile uint8_t*)(0x4003B108UL)) +#define FM4_RTC_WTCR12 *((volatile uint8_t*)(0x4003B108UL)) +#define FM_RTC_WTCR13 *((volatile uint8_t*)(0x4003B10CUL)) +#define FM4_RTC_WTCR13 *((volatile uint8_t*)(0x4003B10CUL)) +#define FM_RTC_WTCR20 *((volatile uint8_t*)(0x4003B110UL)) +#define FM4_RTC_WTCR20 *((volatile uint8_t*)(0x4003B110UL)) +#define FM_RTC_WTCR21 *((volatile uint8_t*)(0x4003B114UL)) +#define FM4_RTC_WTCR21 *((volatile uint8_t*)(0x4003B114UL)) +#define FM_RTC_WTSR *((volatile uint8_t*)(0x4003B11CUL)) +#define FM4_RTC_WTSR *((volatile uint8_t*)(0x4003B11CUL)) +#define FM_RTC_WTMIR *((volatile uint8_t*)(0x4003B120UL)) +#define FM4_RTC_WTMIR *((volatile uint8_t*)(0x4003B120UL)) +#define FM_RTC_WTHR *((volatile uint8_t*)(0x4003B124UL)) +#define FM4_RTC_WTHR *((volatile uint8_t*)(0x4003B124UL)) +#define FM_RTC_WTDR *((volatile uint8_t*)(0x4003B128UL)) +#define FM4_RTC_WTDR *((volatile uint8_t*)(0x4003B128UL)) +#define FM_RTC_WTDW *((volatile uint8_t*)(0x4003B12CUL)) +#define FM4_RTC_WTDW *((volatile uint8_t*)(0x4003B12CUL)) +#define FM_RTC_WTMOR *((volatile uint8_t*)(0x4003B130UL)) +#define FM4_RTC_WTMOR *((volatile uint8_t*)(0x4003B130UL)) +#define FM_RTC_WTYR *((volatile uint8_t*)(0x4003B134UL)) +#define FM4_RTC_WTYR *((volatile uint8_t*)(0x4003B134UL)) +#define FM_RTC_ALMIR *((volatile uint8_t*)(0x4003B138UL)) +#define FM4_RTC_ALMIR *((volatile uint8_t*)(0x4003B138UL)) +#define FM_RTC_ALHR *((volatile uint8_t*)(0x4003B13CUL)) +#define FM4_RTC_ALHR *((volatile uint8_t*)(0x4003B13CUL)) +#define FM_RTC_ALDR *((volatile uint8_t*)(0x4003B140UL)) +#define FM4_RTC_ALDR *((volatile uint8_t*)(0x4003B140UL)) +#define FM_RTC_ALMOR *((volatile uint8_t*)(0x4003B144UL)) +#define FM4_RTC_ALMOR *((volatile uint8_t*)(0x4003B144UL)) +#define FM_RTC_ALYR *((volatile uint8_t*)(0x4003B148UL)) +#define FM4_RTC_ALYR *((volatile uint8_t*)(0x4003B148UL)) +#define FM_RTC_WTTR0 *((volatile uint8_t*)(0x4003B14CUL)) +#define FM4_RTC_WTTR0 *((volatile uint8_t*)(0x4003B14CUL)) +#define FM_RTC_WTTR1 *((volatile uint8_t*)(0x4003B150UL)) +#define FM4_RTC_WTTR1 *((volatile uint8_t*)(0x4003B150UL)) +#define FM_RTC_WTTR2 *((volatile uint8_t*)(0x4003B154UL)) +#define FM4_RTC_WTTR2 *((volatile uint8_t*)(0x4003B154UL)) +#define FM_RTC_WTCAL0 *((volatile uint8_t*)(0x4003B158UL)) +#define FM4_RTC_WTCAL0 *((volatile uint8_t*)(0x4003B158UL)) +#define FM_RTC_WTCAL1 *((volatile uint8_t*)(0x4003B15CUL)) +#define FM4_RTC_WTCAL1 *((volatile uint8_t*)(0x4003B15CUL)) +#define FM_RTC_WTCALEN *((volatile uint8_t*)(0x4003B160UL)) +#define FM4_RTC_WTCALEN *((volatile uint8_t*)(0x4003B160UL)) +#define FM_RTC_WTDIV *((volatile uint8_t*)(0x4003B164UL)) +#define FM4_RTC_WTDIV *((volatile uint8_t*)(0x4003B164UL)) +#define FM_RTC_WTDIVEN *((volatile uint8_t*)(0x4003B168UL)) +#define FM4_RTC_WTDIVEN *((volatile uint8_t*)(0x4003B168UL)) +#define FM_RTC_WTCALPRD *((volatile uint8_t*)(0x4003B16CUL)) +#define FM4_RTC_WTCALPRD *((volatile uint8_t*)(0x4003B16CUL)) +#define FM_RTC_WTCOSEL *((volatile uint8_t*)(0x4003B170UL)) +#define FM4_RTC_WTCOSEL *((volatile uint8_t*)(0x4003B170UL)) +#define FM_RTC_VB_CLKDIV *((volatile uint8_t*)(0x4003B174UL)) +#define FM4_RTC_VB_CLKDIV *((volatile uint8_t*)(0x4003B174UL)) +#define FM_RTC_WTOSCCNT *((volatile uint8_t*)(0x4003B178UL)) +#define FM4_RTC_WTOSCCNT *((volatile uint8_t*)(0x4003B178UL)) +#define FM_RTC_CCS *((volatile uint8_t*)(0x4003B17CUL)) +#define FM4_RTC_CCS *((volatile uint8_t*)(0x4003B17CUL)) +#define FM_RTC_CCB *((volatile uint8_t*)(0x4003B180UL)) +#define FM4_RTC_CCB *((volatile uint8_t*)(0x4003B180UL)) +#define FM_RTC_BOOST *((volatile uint8_t*)(0x4003B188UL)) +#define FM4_RTC_BOOST *((volatile uint8_t*)(0x4003B188UL)) +#define FM_RTC_EWKUP *((volatile uint8_t*)(0x4003B18CUL)) +#define FM4_RTC_EWKUP *((volatile uint8_t*)(0x4003B18CUL)) +#define FM_RTC_VDET *((volatile uint8_t*)(0x4003B190UL)) +#define FM4_RTC_VDET *((volatile uint8_t*)(0x4003B190UL)) +#define FM_RTC_HIBRST *((volatile uint8_t*)(0x4003B198UL)) +#define FM4_RTC_HIBRST *((volatile uint8_t*)(0x4003B198UL)) +#define FM_RTC_VBPFR *((volatile uint8_t*)(0x4003B19CUL)) +#define FM4_RTC_VBPFR *((volatile uint8_t*)(0x4003B19CUL)) +#define FM_RTC_VBPCR *((volatile uint8_t*)(0x4003B1A0UL)) +#define FM4_RTC_VBPCR *((volatile uint8_t*)(0x4003B1A0UL)) +#define FM_RTC_VBDDR *((volatile uint8_t*)(0x4003B1A4UL)) +#define FM4_RTC_VBDDR *((volatile uint8_t*)(0x4003B1A4UL)) +#define FM_RTC_VBDIR *((volatile uint8_t*)(0x4003B1A8UL)) +#define FM4_RTC_VBDIR *((volatile uint8_t*)(0x4003B1A8UL)) +#define FM_RTC_VBDOR *((volatile uint8_t*)(0x4003B1ACUL)) +#define FM4_RTC_VBDOR *((volatile uint8_t*)(0x4003B1ACUL)) +#define FM_RTC_VBPZR *((volatile uint8_t*)(0x4003B1B0UL)) +#define FM4_RTC_VBPZR *((volatile uint8_t*)(0x4003B1B0UL)) +#define FM_RTC_BREG00 *((volatile uint8_t*)(0x4003B200UL)) +#define FM4_RTC_BREG00 *((volatile uint8_t*)(0x4003B200UL)) +#define FM_RTC_BREG01 *((volatile uint8_t*)(0x4003B201UL)) +#define FM4_RTC_BREG01 *((volatile uint8_t*)(0x4003B201UL)) +#define FM_RTC_BREG02 *((volatile uint8_t*)(0x4003B202UL)) +#define FM4_RTC_BREG02 *((volatile uint8_t*)(0x4003B202UL)) +#define FM_RTC_BREG03 *((volatile uint8_t*)(0x4003B203UL)) +#define FM4_RTC_BREG03 *((volatile uint8_t*)(0x4003B203UL)) +#define FM_RTC_BREG04 *((volatile uint8_t*)(0x4003B204UL)) +#define FM4_RTC_BREG04 *((volatile uint8_t*)(0x4003B204UL)) +#define FM_RTC_BREG05 *((volatile uint8_t*)(0x4003B205UL)) +#define FM4_RTC_BREG05 *((volatile uint8_t*)(0x4003B205UL)) +#define FM_RTC_BREG06 *((volatile uint8_t*)(0x4003B206UL)) +#define FM4_RTC_BREG06 *((volatile uint8_t*)(0x4003B206UL)) +#define FM_RTC_BREG07 *((volatile uint8_t*)(0x4003B207UL)) +#define FM4_RTC_BREG07 *((volatile uint8_t*)(0x4003B207UL)) +#define FM_RTC_BREG08 *((volatile uint8_t*)(0x4003B208UL)) +#define FM4_RTC_BREG08 *((volatile uint8_t*)(0x4003B208UL)) +#define FM_RTC_BREG09 *((volatile uint8_t*)(0x4003B209UL)) +#define FM4_RTC_BREG09 *((volatile uint8_t*)(0x4003B209UL)) +#define FM_RTC_BREG0A *((volatile uint8_t*)(0x4003B20AUL)) +#define FM4_RTC_BREG0A *((volatile uint8_t*)(0x4003B20AUL)) +#define FM_RTC_BREG0B *((volatile uint8_t*)(0x4003B20BUL)) +#define FM4_RTC_BREG0B *((volatile uint8_t*)(0x4003B20BUL)) +#define FM_RTC_BREG0C *((volatile uint8_t*)(0x4003B20CUL)) +#define FM4_RTC_BREG0C *((volatile uint8_t*)(0x4003B20CUL)) +#define FM_RTC_BREG0D *((volatile uint8_t*)(0x4003B20DUL)) +#define FM4_RTC_BREG0D *((volatile uint8_t*)(0x4003B20DUL)) +#define FM_RTC_BREG0E *((volatile uint8_t*)(0x4003B20EUL)) +#define FM4_RTC_BREG0E *((volatile uint8_t*)(0x4003B20EUL)) +#define FM_RTC_BREG0F *((volatile uint8_t*)(0x4003B20FUL)) +#define FM4_RTC_BREG0F *((volatile uint8_t*)(0x4003B20FUL)) +#define FM_RTC_BREG10 *((volatile uint8_t*)(0x4003B210UL)) +#define FM4_RTC_BREG10 *((volatile uint8_t*)(0x4003B210UL)) +#define FM_RTC_BREG11 *((volatile uint8_t*)(0x4003B211UL)) +#define FM4_RTC_BREG11 *((volatile uint8_t*)(0x4003B211UL)) +#define FM_RTC_BREG12 *((volatile uint8_t*)(0x4003B212UL)) +#define FM4_RTC_BREG12 *((volatile uint8_t*)(0x4003B212UL)) +#define FM_RTC_BREG13 *((volatile uint8_t*)(0x4003B213UL)) +#define FM4_RTC_BREG13 *((volatile uint8_t*)(0x4003B213UL)) +#define FM_RTC_BREG14 *((volatile uint8_t*)(0x4003B214UL)) +#define FM4_RTC_BREG14 *((volatile uint8_t*)(0x4003B214UL)) +#define FM_RTC_BREG15 *((volatile uint8_t*)(0x4003B215UL)) +#define FM4_RTC_BREG15 *((volatile uint8_t*)(0x4003B215UL)) +#define FM_RTC_BREG16 *((volatile uint8_t*)(0x4003B216UL)) +#define FM4_RTC_BREG16 *((volatile uint8_t*)(0x4003B216UL)) +#define FM_RTC_BREG17 *((volatile uint8_t*)(0x4003B217UL)) +#define FM4_RTC_BREG17 *((volatile uint8_t*)(0x4003B217UL)) +#define FM_RTC_BREG18 *((volatile uint8_t*)(0x4003B218UL)) +#define FM4_RTC_BREG18 *((volatile uint8_t*)(0x4003B218UL)) +#define FM_RTC_BREG19 *((volatile uint8_t*)(0x4003B219UL)) +#define FM4_RTC_BREG19 *((volatile uint8_t*)(0x4003B219UL)) +#define FM_RTC_BREG1A *((volatile uint8_t*)(0x4003B21AUL)) +#define FM4_RTC_BREG1A *((volatile uint8_t*)(0x4003B21AUL)) +#define FM_RTC_BREG1B *((volatile uint8_t*)(0x4003B21BUL)) +#define FM4_RTC_BREG1B *((volatile uint8_t*)(0x4003B21BUL)) +#define FM_RTC_BREG1C *((volatile uint8_t*)(0x4003B21CUL)) +#define FM4_RTC_BREG1C *((volatile uint8_t*)(0x4003B21CUL)) +#define FM_RTC_BREG1D *((volatile uint8_t*)(0x4003B21DUL)) +#define FM4_RTC_BREG1D *((volatile uint8_t*)(0x4003B21DUL)) +#define FM_RTC_BREG1E *((volatile uint8_t*)(0x4003B21EUL)) +#define FM4_RTC_BREG1E *((volatile uint8_t*)(0x4003B21EUL)) +#define FM_RTC_BREG1F *((volatile uint8_t*)(0x4003B21FUL)) +#define FM4_RTC_BREG1F *((volatile uint8_t*)(0x4003B21FUL)) +#define FM_RTC_BREG20 *((volatile uint8_t*)(0x4003B220UL)) +#define FM4_RTC_BREG20 *((volatile uint8_t*)(0x4003B220UL)) +#define FM_RTC_BREG21 *((volatile uint8_t*)(0x4003B221UL)) +#define FM4_RTC_BREG21 *((volatile uint8_t*)(0x4003B221UL)) +#define FM_RTC_BREG22 *((volatile uint8_t*)(0x4003B222UL)) +#define FM4_RTC_BREG22 *((volatile uint8_t*)(0x4003B222UL)) +#define FM_RTC_BREG23 *((volatile uint8_t*)(0x4003B223UL)) +#define FM4_RTC_BREG23 *((volatile uint8_t*)(0x4003B223UL)) +#define FM_RTC_BREG24 *((volatile uint8_t*)(0x4003B224UL)) +#define FM4_RTC_BREG24 *((volatile uint8_t*)(0x4003B224UL)) +#define FM_RTC_BREG25 *((volatile uint8_t*)(0x4003B225UL)) +#define FM4_RTC_BREG25 *((volatile uint8_t*)(0x4003B225UL)) +#define FM_RTC_BREG26 *((volatile uint8_t*)(0x4003B226UL)) +#define FM4_RTC_BREG26 *((volatile uint8_t*)(0x4003B226UL)) +#define FM_RTC_BREG27 *((volatile uint8_t*)(0x4003B227UL)) +#define FM4_RTC_BREG27 *((volatile uint8_t*)(0x4003B227UL)) +#define FM_RTC_BREG28 *((volatile uint8_t*)(0x4003B228UL)) +#define FM4_RTC_BREG28 *((volatile uint8_t*)(0x4003B228UL)) +#define FM_RTC_BREG29 *((volatile uint8_t*)(0x4003B229UL)) +#define FM4_RTC_BREG29 *((volatile uint8_t*)(0x4003B229UL)) +#define FM_RTC_BREG2A *((volatile uint8_t*)(0x4003B22AUL)) +#define FM4_RTC_BREG2A *((volatile uint8_t*)(0x4003B22AUL)) +#define FM_RTC_BREG2B *((volatile uint8_t*)(0x4003B22BUL)) +#define FM4_RTC_BREG2B *((volatile uint8_t*)(0x4003B22BUL)) +#define FM_RTC_BREG2C *((volatile uint8_t*)(0x4003B22CUL)) +#define FM4_RTC_BREG2C *((volatile uint8_t*)(0x4003B22CUL)) +#define FM_RTC_BREG2D *((volatile uint8_t*)(0x4003B22DUL)) +#define FM4_RTC_BREG2D *((volatile uint8_t*)(0x4003B22DUL)) +#define FM_RTC_BREG2E *((volatile uint8_t*)(0x4003B22EUL)) +#define FM4_RTC_BREG2E *((volatile uint8_t*)(0x4003B22EUL)) +#define FM_RTC_BREG2F *((volatile uint8_t*)(0x4003B22FUL)) +#define FM4_RTC_BREG2F *((volatile uint8_t*)(0x4003B22FUL)) +#define FM_RTC_BREG30 *((volatile uint8_t*)(0x4003B230UL)) +#define FM4_RTC_BREG30 *((volatile uint8_t*)(0x4003B230UL)) +#define FM_RTC_BREG31 *((volatile uint8_t*)(0x4003B231UL)) +#define FM4_RTC_BREG31 *((volatile uint8_t*)(0x4003B231UL)) +#define FM_RTC_BREG32 *((volatile uint8_t*)(0x4003B232UL)) +#define FM4_RTC_BREG32 *((volatile uint8_t*)(0x4003B232UL)) +#define FM_RTC_BREG33 *((volatile uint8_t*)(0x4003B233UL)) +#define FM4_RTC_BREG33 *((volatile uint8_t*)(0x4003B233UL)) +#define FM_RTC_BREG34 *((volatile uint8_t*)(0x4003B234UL)) +#define FM4_RTC_BREG34 *((volatile uint8_t*)(0x4003B234UL)) +#define FM_RTC_BREG35 *((volatile uint8_t*)(0x4003B235UL)) +#define FM4_RTC_BREG35 *((volatile uint8_t*)(0x4003B235UL)) +#define FM_RTC_BREG36 *((volatile uint8_t*)(0x4003B236UL)) +#define FM4_RTC_BREG36 *((volatile uint8_t*)(0x4003B236UL)) +#define FM_RTC_BREG37 *((volatile uint8_t*)(0x4003B237UL)) +#define FM4_RTC_BREG37 *((volatile uint8_t*)(0x4003B237UL)) +#define FM_RTC_BREG38 *((volatile uint8_t*)(0x4003B238UL)) +#define FM4_RTC_BREG38 *((volatile uint8_t*)(0x4003B238UL)) +#define FM_RTC_BREG39 *((volatile uint8_t*)(0x4003B239UL)) +#define FM4_RTC_BREG39 *((volatile uint8_t*)(0x4003B239UL)) +#define FM_RTC_BREG3A *((volatile uint8_t*)(0x4003B23AUL)) +#define FM4_RTC_BREG3A *((volatile uint8_t*)(0x4003B23AUL)) +#define FM_RTC_BREG3B *((volatile uint8_t*)(0x4003B23BUL)) +#define FM4_RTC_BREG3B *((volatile uint8_t*)(0x4003B23BUL)) +#define FM_RTC_BREG3C *((volatile uint8_t*)(0x4003B23CUL)) +#define FM4_RTC_BREG3C *((volatile uint8_t*)(0x4003B23CUL)) +#define FM_RTC_BREG3D *((volatile uint8_t*)(0x4003B23DUL)) +#define FM4_RTC_BREG3D *((volatile uint8_t*)(0x4003B23DUL)) +#define FM_RTC_BREG3E *((volatile uint8_t*)(0x4003B23EUL)) +#define FM4_RTC_BREG3E *((volatile uint8_t*)(0x4003B23EUL)) +#define FM_RTC_BREG3F *((volatile uint8_t*)(0x4003B23FUL)) +#define FM4_RTC_BREG3F *((volatile uint8_t*)(0x4003B23FUL)) +#define FM_RTC_BREG40 *((volatile uint8_t*)(0x4003B240UL)) +#define FM4_RTC_BREG40 *((volatile uint8_t*)(0x4003B240UL)) +#define FM_RTC_BREG41 *((volatile uint8_t*)(0x4003B241UL)) +#define FM4_RTC_BREG41 *((volatile uint8_t*)(0x4003B241UL)) +#define FM_RTC_BREG42 *((volatile uint8_t*)(0x4003B242UL)) +#define FM4_RTC_BREG42 *((volatile uint8_t*)(0x4003B242UL)) +#define FM_RTC_BREG43 *((volatile uint8_t*)(0x4003B243UL)) +#define FM4_RTC_BREG43 *((volatile uint8_t*)(0x4003B243UL)) +#define FM_RTC_BREG44 *((volatile uint8_t*)(0x4003B244UL)) +#define FM4_RTC_BREG44 *((volatile uint8_t*)(0x4003B244UL)) +#define FM_RTC_BREG45 *((volatile uint8_t*)(0x4003B245UL)) +#define FM4_RTC_BREG45 *((volatile uint8_t*)(0x4003B245UL)) +#define FM_RTC_BREG46 *((volatile uint8_t*)(0x4003B246UL)) +#define FM4_RTC_BREG46 *((volatile uint8_t*)(0x4003B246UL)) +#define FM_RTC_BREG47 *((volatile uint8_t*)(0x4003B247UL)) +#define FM4_RTC_BREG47 *((volatile uint8_t*)(0x4003B247UL)) +#define FM_RTC_BREG48 *((volatile uint8_t*)(0x4003B248UL)) +#define FM4_RTC_BREG48 *((volatile uint8_t*)(0x4003B248UL)) +#define FM_RTC_BREG49 *((volatile uint8_t*)(0x4003B249UL)) +#define FM4_RTC_BREG49 *((volatile uint8_t*)(0x4003B249UL)) +#define FM_RTC_BREG4A *((volatile uint8_t*)(0x4003B24AUL)) +#define FM4_RTC_BREG4A *((volatile uint8_t*)(0x4003B24AUL)) +#define FM_RTC_BREG4B *((volatile uint8_t*)(0x4003B24BUL)) +#define FM4_RTC_BREG4B *((volatile uint8_t*)(0x4003B24BUL)) +#define FM_RTC_BREG4C *((volatile uint8_t*)(0x4003B24CUL)) +#define FM4_RTC_BREG4C *((volatile uint8_t*)(0x4003B24CUL)) +#define FM_RTC_BREG4D *((volatile uint8_t*)(0x4003B24DUL)) +#define FM4_RTC_BREG4D *((volatile uint8_t*)(0x4003B24DUL)) +#define FM_RTC_BREG4E *((volatile uint8_t*)(0x4003B24EUL)) +#define FM4_RTC_BREG4E *((volatile uint8_t*)(0x4003B24EUL)) +#define FM_RTC_BREG4F *((volatile uint8_t*)(0x4003B24FUL)) +#define FM4_RTC_BREG4F *((volatile uint8_t*)(0x4003B24FUL)) +#define FM_RTC_BREG50 *((volatile uint8_t*)(0x4003B250UL)) +#define FM4_RTC_BREG50 *((volatile uint8_t*)(0x4003B250UL)) +#define FM_RTC_BREG51 *((volatile uint8_t*)(0x4003B251UL)) +#define FM4_RTC_BREG51 *((volatile uint8_t*)(0x4003B251UL)) +#define FM_RTC_BREG52 *((volatile uint8_t*)(0x4003B252UL)) +#define FM4_RTC_BREG52 *((volatile uint8_t*)(0x4003B252UL)) +#define FM_RTC_BREG53 *((volatile uint8_t*)(0x4003B253UL)) +#define FM4_RTC_BREG53 *((volatile uint8_t*)(0x4003B253UL)) +#define FM_RTC_BREG54 *((volatile uint8_t*)(0x4003B254UL)) +#define FM4_RTC_BREG54 *((volatile uint8_t*)(0x4003B254UL)) +#define FM_RTC_BREG55 *((volatile uint8_t*)(0x4003B255UL)) +#define FM4_RTC_BREG55 *((volatile uint8_t*)(0x4003B255UL)) +#define FM_RTC_BREG56 *((volatile uint8_t*)(0x4003B256UL)) +#define FM4_RTC_BREG56 *((volatile uint8_t*)(0x4003B256UL)) +#define FM_RTC_BREG57 *((volatile uint8_t*)(0x4003B257UL)) +#define FM4_RTC_BREG57 *((volatile uint8_t*)(0x4003B257UL)) +#define FM_RTC_BREG58 *((volatile uint8_t*)(0x4003B258UL)) +#define FM4_RTC_BREG58 *((volatile uint8_t*)(0x4003B258UL)) +#define FM_RTC_BREG59 *((volatile uint8_t*)(0x4003B259UL)) +#define FM4_RTC_BREG59 *((volatile uint8_t*)(0x4003B259UL)) +#define FM_RTC_BREG5A *((volatile uint8_t*)(0x4003B25AUL)) +#define FM4_RTC_BREG5A *((volatile uint8_t*)(0x4003B25AUL)) +#define FM_RTC_BREG5B *((volatile uint8_t*)(0x4003B25BUL)) +#define FM4_RTC_BREG5B *((volatile uint8_t*)(0x4003B25BUL)) +#define FM_RTC_BREG5C *((volatile uint8_t*)(0x4003B25CUL)) +#define FM4_RTC_BREG5C *((volatile uint8_t*)(0x4003B25CUL)) +#define FM_RTC_BREG5D *((volatile uint8_t*)(0x4003B25DUL)) +#define FM4_RTC_BREG5D *((volatile uint8_t*)(0x4003B25DUL)) +#define FM_RTC_BREG5E *((volatile uint8_t*)(0x4003B25EUL)) +#define FM4_RTC_BREG5E *((volatile uint8_t*)(0x4003B25EUL)) +#define FM_RTC_BREG5F *((volatile uint8_t*)(0x4003B25FUL)) +#define FM4_RTC_BREG5F *((volatile uint8_t*)(0x4003B25FUL)) +#define FM_RTC_BREG60 *((volatile uint8_t*)(0x4003B260UL)) +#define FM4_RTC_BREG60 *((volatile uint8_t*)(0x4003B260UL)) +#define FM_RTC_BREG61 *((volatile uint8_t*)(0x4003B261UL)) +#define FM4_RTC_BREG61 *((volatile uint8_t*)(0x4003B261UL)) +#define FM_RTC_BREG62 *((volatile uint8_t*)(0x4003B262UL)) +#define FM4_RTC_BREG62 *((volatile uint8_t*)(0x4003B262UL)) +#define FM_RTC_BREG63 *((volatile uint8_t*)(0x4003B263UL)) +#define FM4_RTC_BREG63 *((volatile uint8_t*)(0x4003B263UL)) +#define FM_RTC_BREG64 *((volatile uint8_t*)(0x4003B264UL)) +#define FM4_RTC_BREG64 *((volatile uint8_t*)(0x4003B264UL)) +#define FM_RTC_BREG65 *((volatile uint8_t*)(0x4003B265UL)) +#define FM4_RTC_BREG65 *((volatile uint8_t*)(0x4003B265UL)) +#define FM_RTC_BREG66 *((volatile uint8_t*)(0x4003B266UL)) +#define FM4_RTC_BREG66 *((volatile uint8_t*)(0x4003B266UL)) +#define FM_RTC_BREG67 *((volatile uint8_t*)(0x4003B267UL)) +#define FM4_RTC_BREG67 *((volatile uint8_t*)(0x4003B267UL)) +#define FM_RTC_BREG68 *((volatile uint8_t*)(0x4003B268UL)) +#define FM4_RTC_BREG68 *((volatile uint8_t*)(0x4003B268UL)) +#define FM_RTC_BREG69 *((volatile uint8_t*)(0x4003B269UL)) +#define FM4_RTC_BREG69 *((volatile uint8_t*)(0x4003B269UL)) +#define FM_RTC_BREG6A *((volatile uint8_t*)(0x4003B26AUL)) +#define FM4_RTC_BREG6A *((volatile uint8_t*)(0x4003B26AUL)) +#define FM_RTC_BREG6B *((volatile uint8_t*)(0x4003B26BUL)) +#define FM4_RTC_BREG6B *((volatile uint8_t*)(0x4003B26BUL)) +#define FM_RTC_BREG6C *((volatile uint8_t*)(0x4003B26CUL)) +#define FM4_RTC_BREG6C *((volatile uint8_t*)(0x4003B26CUL)) +#define FM_RTC_BREG6D *((volatile uint8_t*)(0x4003B26DUL)) +#define FM4_RTC_BREG6D *((volatile uint8_t*)(0x4003B26DUL)) +#define FM_RTC_BREG6E *((volatile uint8_t*)(0x4003B26EUL)) +#define FM4_RTC_BREG6E *((volatile uint8_t*)(0x4003B26EUL)) +#define FM_RTC_BREG6F *((volatile uint8_t*)(0x4003B26FUL)) +#define FM4_RTC_BREG6F *((volatile uint8_t*)(0x4003B26FUL)) +#define FM_RTC_BREG70 *((volatile uint8_t*)(0x4003B270UL)) +#define FM4_RTC_BREG70 *((volatile uint8_t*)(0x4003B270UL)) +#define FM_RTC_BREG71 *((volatile uint8_t*)(0x4003B271UL)) +#define FM4_RTC_BREG71 *((volatile uint8_t*)(0x4003B271UL)) +#define FM_RTC_BREG72 *((volatile uint8_t*)(0x4003B272UL)) +#define FM4_RTC_BREG72 *((volatile uint8_t*)(0x4003B272UL)) +#define FM_RTC_BREG73 *((volatile uint8_t*)(0x4003B273UL)) +#define FM4_RTC_BREG73 *((volatile uint8_t*)(0x4003B273UL)) +#define FM_RTC_BREG74 *((volatile uint8_t*)(0x4003B274UL)) +#define FM4_RTC_BREG74 *((volatile uint8_t*)(0x4003B274UL)) +#define FM_RTC_BREG75 *((volatile uint8_t*)(0x4003B275UL)) +#define FM4_RTC_BREG75 *((volatile uint8_t*)(0x4003B275UL)) +#define FM_RTC_BREG76 *((volatile uint8_t*)(0x4003B276UL)) +#define FM4_RTC_BREG76 *((volatile uint8_t*)(0x4003B276UL)) +#define FM_RTC_BREG77 *((volatile uint8_t*)(0x4003B277UL)) +#define FM4_RTC_BREG77 *((volatile uint8_t*)(0x4003B277UL)) +#define FM_RTC_BREG78 *((volatile uint8_t*)(0x4003B278UL)) +#define FM4_RTC_BREG78 *((volatile uint8_t*)(0x4003B278UL)) +#define FM_RTC_BREG79 *((volatile uint8_t*)(0x4003B279UL)) +#define FM4_RTC_BREG79 *((volatile uint8_t*)(0x4003B279UL)) +#define FM_RTC_BREG7A *((volatile uint8_t*)(0x4003B27AUL)) +#define FM4_RTC_BREG7A *((volatile uint8_t*)(0x4003B27AUL)) +#define FM_RTC_BREG7B *((volatile uint8_t*)(0x4003B27BUL)) +#define FM4_RTC_BREG7B *((volatile uint8_t*)(0x4003B27BUL)) +#define FM_RTC_BREG7C *((volatile uint8_t*)(0x4003B27CUL)) +#define FM4_RTC_BREG7C *((volatile uint8_t*)(0x4003B27CUL)) +#define FM_RTC_BREG7D *((volatile uint8_t*)(0x4003B27DUL)) +#define FM4_RTC_BREG7D *((volatile uint8_t*)(0x4003B27DUL)) +#define FM_RTC_BREG7E *((volatile uint8_t*)(0x4003B27EUL)) +#define FM4_RTC_BREG7E *((volatile uint8_t*)(0x4003B27EUL)) +#define FM_RTC_BREG7F *((volatile uint8_t*)(0x4003B27FUL)) +#define FM4_RTC_BREG7F *((volatile uint8_t*)(0x4003B27FUL)) + +/******************************************************************************* +* SBSSR Registers SBSSR +* Register Definition +*******************************************************************************/ +#define FM_SBSSR_BTSSSR *((volatile uint16_t*)(0x40025FFCUL)) +#define FM4_SBSSR_BTSSSR *((volatile uint16_t*)(0x40025FFCUL)) + +/******************************************************************************* +* SDIF Registers SDIF +* Register Definition +*******************************************************************************/ +#define FM_SDIF_SSA2 *((volatile uint32_t*)(0x4006E000UL)) +#define FM4_SDIF_SSA2 *((volatile uint32_t*)(0x4006E000UL)) +#define FM_SDIF_SBSIZE *((volatile uint16_t*)(0x4006E004UL)) +#define FM4_SDIF_SBSIZE *((volatile uint16_t*)(0x4006E004UL)) +#define FM_SDIF_SBLCNT *((volatile uint16_t*)(0x4006E006UL)) +#define FM4_SDIF_SBLCNT *((volatile uint16_t*)(0x4006E006UL)) +#define FM_SDIF_SSA1 *((volatile uint32_t*)(0x4006E008UL)) +#define FM4_SDIF_SSA1 *((volatile uint32_t*)(0x4006E008UL)) +#define FM_SDIF_STRSFMD *((volatile uint16_t*)(0x4006E00CUL)) +#define FM4_SDIF_STRSFMD *((volatile uint16_t*)(0x4006E00CUL)) +#define FM_SDIF_SCMMD *((volatile uint16_t*)(0x4006E00EUL)) +#define FM4_SDIF_SCMMD *((volatile uint16_t*)(0x4006E00EUL)) +#define FM_SDIF_SRESP0 *((volatile uint16_t*)(0x4006E010UL)) +#define FM4_SDIF_SRESP0 *((volatile uint16_t*)(0x4006E010UL)) +#define FM_SDIF_SRESP1 *((volatile uint16_t*)(0x4006E012UL)) +#define FM4_SDIF_SRESP1 *((volatile uint16_t*)(0x4006E012UL)) +#define FM_SDIF_SRESP2 *((volatile uint16_t*)(0x4006E014UL)) +#define FM4_SDIF_SRESP2 *((volatile uint16_t*)(0x4006E014UL)) +#define FM_SDIF_SRESP3 *((volatile uint16_t*)(0x4006E016UL)) +#define FM4_SDIF_SRESP3 *((volatile uint16_t*)(0x4006E016UL)) +#define FM_SDIF_SRESP4 *((volatile uint16_t*)(0x4006E018UL)) +#define FM4_SDIF_SRESP4 *((volatile uint16_t*)(0x4006E018UL)) +#define FM_SDIF_SRESP5 *((volatile uint16_t*)(0x4006E01AUL)) +#define FM4_SDIF_SRESP5 *((volatile uint16_t*)(0x4006E01AUL)) +#define FM_SDIF_SRESP6 *((volatile uint16_t*)(0x4006E01CUL)) +#define FM4_SDIF_SRESP6 *((volatile uint16_t*)(0x4006E01CUL)) +#define FM_SDIF_SRESP7 *((volatile uint16_t*)(0x4006E01EUL)) +#define FM4_SDIF_SRESP7 *((volatile uint16_t*)(0x4006E01EUL)) +#define FM_SDIF_SBUFDP *((volatile uint32_t*)(0x4006E020UL)) +#define FM4_SDIF_SBUFDP *((volatile uint32_t*)(0x4006E020UL)) +#define FM_SDIF_SPRSTAT *((volatile uint32_t*)(0x4006E024UL)) +#define FM4_SDIF_SPRSTAT *((volatile uint32_t*)(0x4006E024UL)) +#define FM_SDIF_SHCTL1 *((volatile uint8_t*)(0x4006E028UL)) +#define FM4_SDIF_SHCTL1 *((volatile uint8_t*)(0x4006E028UL)) +#define FM_SDIF_SPWRCTL *((volatile uint8_t*)(0x4006E029UL)) +#define FM4_SDIF_SPWRCTL *((volatile uint8_t*)(0x4006E029UL)) +#define FM_SDIF_SBLKGPCTL *((volatile uint8_t*)(0x4006E02AUL)) +#define FM4_SDIF_SBLKGPCTL *((volatile uint8_t*)(0x4006E02AUL)) +#define FM_SDIF_SWKUPCTL *((volatile uint8_t*)(0x4006E02BUL)) +#define FM4_SDIF_SWKUPCTL *((volatile uint8_t*)(0x4006E02BUL)) +#define FM_SDIF_SCLKCTL *((volatile uint16_t*)(0x4006E02CUL)) +#define FM4_SDIF_SCLKCTL *((volatile uint16_t*)(0x4006E02CUL)) +#define FM_SDIF_STOCTL *((volatile uint8_t*)(0x4006E02EUL)) +#define FM4_SDIF_STOCTL *((volatile uint8_t*)(0x4006E02EUL)) +#define FM_SDIF_SSRST *((volatile uint8_t*)(0x4006E02FUL)) +#define FM4_SDIF_SSRST *((volatile uint8_t*)(0x4006E02FUL)) +#define FM_SDIF_SNINTST *((volatile uint16_t*)(0x4006E030UL)) +#define FM4_SDIF_SNINTST *((volatile uint16_t*)(0x4006E030UL)) +#define FM_SDIF_SEINTST *((volatile uint16_t*)(0x4006E032UL)) +#define FM4_SDIF_SEINTST *((volatile uint16_t*)(0x4006E032UL)) +#define FM_SDIF_SNINTSTE *((volatile uint16_t*)(0x4006E034UL)) +#define FM4_SDIF_SNINTSTE *((volatile uint16_t*)(0x4006E034UL)) +#define FM_SDIF_SEINTSTE *((volatile uint16_t*)(0x4006E036UL)) +#define FM4_SDIF_SEINTSTE *((volatile uint16_t*)(0x4006E036UL)) +#define FM_SDIF_SNINTSGE *((volatile uint16_t*)(0x4006E038UL)) +#define FM4_SDIF_SNINTSGE *((volatile uint16_t*)(0x4006E038UL)) +#define FM_SDIF_SEINTSGE *((volatile uint16_t*)(0x4006E03AUL)) +#define FM4_SDIF_SEINTSGE *((volatile uint16_t*)(0x4006E03AUL)) +#define FM_SDIF_SACMDEST *((volatile uint16_t*)(0x4006E03CUL)) +#define FM4_SDIF_SACMDEST *((volatile uint16_t*)(0x4006E03CUL)) +#define FM_SDIF_SHCTL2 *((volatile uint16_t*)(0x4006E03EUL)) +#define FM4_SDIF_SHCTL2 *((volatile uint16_t*)(0x4006E03EUL)) +#define FM_SDIF_CAPBLTY0 *((volatile uint16_t*)(0x4006E040UL)) +#define FM4_SDIF_CAPBLTY0 *((volatile uint16_t*)(0x4006E040UL)) +#define FM_SDIF_CAPBLTY1 *((volatile uint16_t*)(0x4006E042UL)) +#define FM4_SDIF_CAPBLTY1 *((volatile uint16_t*)(0x4006E042UL)) +#define FM_SDIF_CAPBLTY2 *((volatile uint16_t*)(0x4006E044UL)) +#define FM4_SDIF_CAPBLTY2 *((volatile uint16_t*)(0x4006E044UL)) +#define FM_SDIF_CAPBLTY3 *((volatile uint16_t*)(0x4006E046UL)) +#define FM4_SDIF_CAPBLTY3 *((volatile uint16_t*)(0x4006E046UL)) +#define FM_SDIF_MXCCAPY0 *((volatile uint16_t*)(0x4006E048UL)) +#define FM4_SDIF_MXCCAPY0 *((volatile uint16_t*)(0x4006E048UL)) +#define FM_SDIF_MXCCAPY1 *((volatile uint16_t*)(0x4006E04AUL)) +#define FM4_SDIF_MXCCAPY1 *((volatile uint16_t*)(0x4006E04AUL)) +#define FM_SDIF_MXCCAPY2 *((volatile uint16_t*)(0x4006E04CUL)) +#define FM4_SDIF_MXCCAPY2 *((volatile uint16_t*)(0x4006E04CUL)) +#define FM_SDIF_MXCCAPY3 *((volatile uint16_t*)(0x4006E04EUL)) +#define FM4_SDIF_MXCCAPY3 *((volatile uint16_t*)(0x4006E04EUL)) +#define FM_SDIF_FEACEST *((volatile uint16_t*)(0x4006E050UL)) +#define FM4_SDIF_FEACEST *((volatile uint16_t*)(0x4006E050UL)) +#define FM_SDIF_SFEEIST *((volatile uint16_t*)(0x4006E052UL)) +#define FM4_SDIF_SFEEIST *((volatile uint16_t*)(0x4006E052UL)) +#define FM_SDIF_ADMAEST *((volatile uint8_t*)(0x4006E054UL)) +#define FM4_SDIF_ADMAEST *((volatile uint8_t*)(0x4006E054UL)) +#define FM_SDIF_SADSA0 *((volatile uint16_t*)(0x4006E058UL)) +#define FM4_SDIF_SADSA0 *((volatile uint16_t*)(0x4006E058UL)) +#define FM_SDIF_SADSA1 *((volatile uint16_t*)(0x4006E05AUL)) +#define FM4_SDIF_SADSA1 *((volatile uint16_t*)(0x4006E05AUL)) +#define FM_SDIF_SADSA2 *((volatile uint16_t*)(0x4006E05CUL)) +#define FM4_SDIF_SADSA2 *((volatile uint16_t*)(0x4006E05CUL)) +#define FM_SDIF_SADSA3 *((volatile uint16_t*)(0x4006E05EUL)) +#define FM4_SDIF_SADSA3 *((volatile uint16_t*)(0x4006E05EUL)) +#define FM_SDIF_SPRVAL0 *((volatile uint16_t*)(0x4006E060UL)) +#define FM4_SDIF_SPRVAL0 *((volatile uint16_t*)(0x4006E060UL)) +#define FM_SDIF_SPRVAL1 *((volatile uint16_t*)(0x4006E062UL)) +#define FM4_SDIF_SPRVAL1 *((volatile uint16_t*)(0x4006E062UL)) +#define FM_SDIF_SPRVAL2 *((volatile uint16_t*)(0x4006E064UL)) +#define FM4_SDIF_SPRVAL2 *((volatile uint16_t*)(0x4006E064UL)) +#define FM_SDIF_SPRVAL3 *((volatile uint16_t*)(0x4006E066UL)) +#define FM4_SDIF_SPRVAL3 *((volatile uint16_t*)(0x4006E066UL)) +#define FM_SDIF_SPRVAL4 *((volatile uint16_t*)(0x4006E068UL)) +#define FM4_SDIF_SPRVAL4 *((volatile uint16_t*)(0x4006E068UL)) +#define FM_SDIF_SPRVAL5 *((volatile uint16_t*)(0x4006E06AUL)) +#define FM4_SDIF_SPRVAL5 *((volatile uint16_t*)(0x4006E06AUL)) +#define FM_SDIF_SPRVAL6 *((volatile uint16_t*)(0x4006E06CUL)) +#define FM4_SDIF_SPRVAL6 *((volatile uint16_t*)(0x4006E06CUL)) +#define FM_SDIF_SPRVAL7 *((volatile uint16_t*)(0x4006E06EUL)) +#define FM4_SDIF_SPRVAL7 *((volatile uint16_t*)(0x4006E06EUL)) +#define FM_SDIF_SSHBCTLL *((volatile uint16_t*)(0x4006E0E0UL)) +#define FM4_SDIF_SSHBCTLL *((volatile uint16_t*)(0x4006E0E0UL)) +#define FM_SDIF_SSHBCTLH *((volatile uint16_t*)(0x4006E0E2UL)) +#define FM4_SDIF_SSHBCTLH *((volatile uint16_t*)(0x4006E0E2UL)) +#define FM_SDIF_SSLIST *((volatile uint16_t*)(0x4006E0FCUL)) +#define FM4_SDIF_SSLIST *((volatile uint16_t*)(0x4006E0FCUL)) +#define FM_SDIF_SHCTLV *((volatile uint16_t*)(0x4006E0FEUL)) +#define FM4_SDIF_SHCTLV *((volatile uint16_t*)(0x4006E0FEUL)) +#define FM_SDIF_AHBCFGL *((volatile uint16_t*)(0x4006E100UL)) +#define FM4_SDIF_AHBCFGL *((volatile uint16_t*)(0x4006E100UL)) +#define FM_SDIF_AHBCFGH *((volatile uint16_t*)(0x4006E102UL)) +#define FM4_SDIF_AHBCFGH *((volatile uint16_t*)(0x4006E102UL)) +#define FM_SDIF_SPWSWCL *((volatile uint16_t*)(0x4006E104UL)) +#define FM4_SDIF_SPWSWCL *((volatile uint16_t*)(0x4006E104UL)) +#define FM_SDIF_SPWSWCH *((volatile uint16_t*)(0x4006E106UL)) +#define FM4_SDIF_SPWSWCH *((volatile uint16_t*)(0x4006E106UL)) +#define FM_SDIF_STUNSETL *((volatile uint16_t*)(0x4006E108UL)) +#define FM4_SDIF_STUNSETL *((volatile uint16_t*)(0x4006E108UL)) +#define FM_SDIF_STUNSETH *((volatile uint16_t*)(0x4006E10AUL)) +#define FM4_SDIF_STUNSETH *((volatile uint16_t*)(0x4006E10AUL)) +#define FM_SDIF_STUNSTL *((volatile uint16_t*)(0x4006E10CUL)) +#define FM4_SDIF_STUNSTL *((volatile uint16_t*)(0x4006E10CUL)) +#define FM_SDIF_STUNSTH *((volatile uint16_t*)(0x4006E10EUL)) +#define FM4_SDIF_STUNSTH *((volatile uint16_t*)(0x4006E10EUL)) +#define FM_SDIF_PSWISTL *((volatile uint16_t*)(0x4006E118UL)) +#define FM4_SDIF_PSWISTL *((volatile uint16_t*)(0x4006E118UL)) +#define FM_SDIF_PSWISTH *((volatile uint16_t*)(0x4006E11AUL)) +#define FM4_SDIF_PSWISTH *((volatile uint16_t*)(0x4006E11AUL)) +#define FM_SDIF_PSWISTEL *((volatile uint16_t*)(0x4006E11CUL)) +#define FM4_SDIF_PSWISTEL *((volatile uint16_t*)(0x4006E11CUL)) +#define FM_SDIF_PSWISTEH *((volatile uint16_t*)(0x4006E11EUL)) +#define FM4_SDIF_PSWISTEH *((volatile uint16_t*)(0x4006E11EUL)) +#define FM_SDIF_PSWISGEL *((volatile uint16_t*)(0x4006E120UL)) +#define FM4_SDIF_PSWISGEL *((volatile uint16_t*)(0x4006E120UL)) +#define FM_SDIF_PSWISGEH *((volatile uint16_t*)(0x4006E122UL)) +#define FM4_SDIF_PSWISGEH *((volatile uint16_t*)(0x4006E122UL)) +#define FM_SDIF_MMCSDCL *((volatile uint16_t*)(0x4006E124UL)) +#define FM4_SDIF_MMCSDCL *((volatile uint16_t*)(0x4006E124UL)) +#define FM_SDIF_MMCSDCH *((volatile uint16_t*)(0x4006E126UL)) +#define FM4_SDIF_MMCSDCH *((volatile uint16_t*)(0x4006E126UL)) +#define FM_SDIF_MCWIRQC0 *((volatile uint16_t*)(0x4006E128UL)) +#define FM4_SDIF_MCWIRQC0 *((volatile uint16_t*)(0x4006E128UL)) +#define FM_SDIF_MCWIRQC1 *((volatile uint16_t*)(0x4006E12AUL)) +#define FM4_SDIF_MCWIRQC1 *((volatile uint16_t*)(0x4006E12AUL)) +#define FM_SDIF_MCWIRQC2 *((volatile uint16_t*)(0x4006E12CUL)) +#define FM4_SDIF_MCWIRQC2 *((volatile uint16_t*)(0x4006E12CUL)) +#define FM_SDIF_MCWIRQC3 *((volatile uint16_t*)(0x4006E12EUL)) +#define FM4_SDIF_MCWIRQC3 *((volatile uint16_t*)(0x4006E12EUL)) +#define FM_SDIF_MCRPCKBL *((volatile uint16_t*)(0x4006E130UL)) +#define FM4_SDIF_MCRPCKBL *((volatile uint16_t*)(0x4006E130UL)) +#define FM_SDIF_MCRPCKBH *((volatile uint16_t*)(0x4006E132UL)) +#define FM4_SDIF_MCRPCKBH *((volatile uint16_t*)(0x4006E132UL)) +#define FM_SDIF_SCDETECS *((volatile uint16_t*)(0x4006E154UL)) +#define FM4_SDIF_SCDETECS *((volatile uint16_t*)(0x4006E154UL)) + +/******************************************************************************* +* SWWDT Registers SWWDT +* Register Definition +*******************************************************************************/ +#define FM_SWWDT_WDOGLOAD *((volatile uint32_t*)(0x40012000UL)) +#define FM4_SWWDT_WDOGLOAD *((volatile uint32_t*)(0x40012000UL)) +#define FM_SWWDT_WDOGVALUE *((volatile uint32_t*)(0x40012004UL)) +#define FM4_SWWDT_WDOGVALUE *((volatile uint32_t*)(0x40012004UL)) +#define FM_SWWDT_WDOGCONTROL *((volatile uint32_t*)(0x40012008UL)) +#define FM4_SWWDT_WDOGCONTROL *((volatile uint32_t*)(0x40012008UL)) +#define FM_SWWDT_WDOGINTCLR *((volatile uint32_t*)(0x4001200CUL)) +#define FM4_SWWDT_WDOGINTCLR *((volatile uint32_t*)(0x4001200CUL)) +#define FM_SWWDT_WDOGRIS *((volatile uint32_t*)(0x40012010UL)) +#define FM4_SWWDT_WDOGRIS *((volatile uint32_t*)(0x40012010UL)) +#define FM_SWWDT_WDOGSPMC *((volatile uint32_t*)(0x40012018UL)) +#define FM4_SWWDT_WDOGSPMC *((volatile uint32_t*)(0x40012018UL)) +#define FM_SWWDT_WDOGLOCK *((volatile uint32_t*)(0x40012C00UL)) +#define FM4_SWWDT_WDOGLOCK *((volatile uint32_t*)(0x40012C00UL)) + +/******************************************************************************* +* UNIQUE_ID Registers UNIQUE_ID +* Register Definition +*******************************************************************************/ +#define FM_UNIQUE_ID_UIDR0 *((volatile uint32_t*)(0x40000200UL)) +#define FM4_UNIQUE_ID_UIDR0 *((volatile uint32_t*)(0x40000200UL)) +#define FM_UNIQUE_ID_UIDR1 *((volatile uint32_t*)(0x40000204UL)) +#define FM4_UNIQUE_ID_UIDR1 *((volatile uint32_t*)(0x40000204UL)) + +/******************************************************************************* +* USB Registers USB0 +* Register Definition +*******************************************************************************/ +#define FM_USB0_HCNT *((volatile uint16_t*)(0x40042100UL)) +#define FM4_USB0_HCNT *((volatile uint16_t*)(0x40042100UL)) +#define FM_USB0_HIRQ *((volatile uint8_t*)(0x40042104UL)) +#define FM4_USB0_HIRQ *((volatile uint8_t*)(0x40042104UL)) +#define FM_USB0_HERR *((volatile uint8_t*)(0x40042105UL)) +#define FM4_USB0_HERR *((volatile uint8_t*)(0x40042105UL)) +#define FM_USB0_HSTATE *((volatile uint8_t*)(0x40042108UL)) +#define FM4_USB0_HSTATE *((volatile uint8_t*)(0x40042108UL)) +#define FM_USB0_HFCOMP *((volatile uint8_t*)(0x40042109UL)) +#define FM4_USB0_HFCOMP *((volatile uint8_t*)(0x40042109UL)) +#define FM_USB0_HRTIMER *((volatile uint16_t*)(0x4004210CUL)) +#define FM4_USB0_HRTIMER *((volatile uint16_t*)(0x4004210CUL)) +#define FM_USB0_HRTIMER2 *((volatile uint8_t*)(0x40042110UL)) +#define FM4_USB0_HRTIMER2 *((volatile uint8_t*)(0x40042110UL)) +#define FM_USB0_HADR *((volatile uint8_t*)(0x40042111UL)) +#define FM4_USB0_HADR *((volatile uint8_t*)(0x40042111UL)) +#define FM_USB0_HEOF *((volatile uint16_t*)(0x40042114UL)) +#define FM4_USB0_HEOF *((volatile uint16_t*)(0x40042114UL)) +#define FM_USB0_HFRAME *((volatile uint16_t*)(0x40042118UL)) +#define FM4_USB0_HFRAME *((volatile uint16_t*)(0x40042118UL)) +#define FM_USB0_HTOKEN *((volatile uint8_t*)(0x4004211CUL)) +#define FM4_USB0_HTOKEN *((volatile uint8_t*)(0x4004211CUL)) +#define FM_USB0_UDCC *((volatile uint16_t*)(0x40042120UL)) +#define FM4_USB0_UDCC *((volatile uint16_t*)(0x40042120UL)) +#define FM_USB0_EP0C *((volatile uint16_t*)(0x40042124UL)) +#define FM4_USB0_EP0C *((volatile uint16_t*)(0x40042124UL)) +#define FM_USB0_EP1C *((volatile uint16_t*)(0x40042128UL)) +#define FM4_USB0_EP1C *((volatile uint16_t*)(0x40042128UL)) +#define FM_USB0_EP2C *((volatile uint16_t*)(0x4004212CUL)) +#define FM4_USB0_EP2C *((volatile uint16_t*)(0x4004212CUL)) +#define FM_USB0_EP3C *((volatile uint16_t*)(0x40042130UL)) +#define FM4_USB0_EP3C *((volatile uint16_t*)(0x40042130UL)) +#define FM_USB0_EP4C *((volatile uint16_t*)(0x40042134UL)) +#define FM4_USB0_EP4C *((volatile uint16_t*)(0x40042134UL)) +#define FM_USB0_EP5C *((volatile uint16_t*)(0x40042138UL)) +#define FM4_USB0_EP5C *((volatile uint16_t*)(0x40042138UL)) +#define FM_USB0_TMSP *((volatile uint16_t*)(0x4004213CUL)) +#define FM4_USB0_TMSP *((volatile uint16_t*)(0x4004213CUL)) +#define FM_USB0_UDCS *((volatile uint8_t*)(0x40042140UL)) +#define FM4_USB0_UDCS *((volatile uint8_t*)(0x40042140UL)) +#define FM_USB0_UDCIE *((volatile uint8_t*)(0x40042141UL)) +#define FM4_USB0_UDCIE *((volatile uint8_t*)(0x40042141UL)) +#define FM_USB0_EP0IS *((volatile uint16_t*)(0x40042144UL)) +#define FM4_USB0_EP0IS *((volatile uint16_t*)(0x40042144UL)) +#define FM_USB0_EP0OS *((volatile uint16_t*)(0x40042148UL)) +#define FM4_USB0_EP0OS *((volatile uint16_t*)(0x40042148UL)) +#define FM_USB0_EP1S *((volatile uint16_t*)(0x4004214CUL)) +#define FM4_USB0_EP1S *((volatile uint16_t*)(0x4004214CUL)) +#define FM_USB0_EP2S *((volatile uint16_t*)(0x40042150UL)) +#define FM4_USB0_EP2S *((volatile uint16_t*)(0x40042150UL)) +#define FM_USB0_EP3S *((volatile uint16_t*)(0x40042154UL)) +#define FM4_USB0_EP3S *((volatile uint16_t*)(0x40042154UL)) +#define FM_USB0_EP4S *((volatile uint16_t*)(0x40042158UL)) +#define FM4_USB0_EP4S *((volatile uint16_t*)(0x40042158UL)) +#define FM_USB0_EP5S *((volatile uint16_t*)(0x4004215CUL)) +#define FM4_USB0_EP5S *((volatile uint16_t*)(0x4004215CUL)) +#define FM_USB0_EP0DT *((volatile uint16_t*)(0x40042160UL)) +#define FM4_USB0_EP0DT *((volatile uint16_t*)(0x40042160UL)) +#define FM_USB0_EP1DT *((volatile uint16_t*)(0x40042164UL)) +#define FM4_USB0_EP1DT *((volatile uint16_t*)(0x40042164UL)) +#define FM_USB0_EP2DT *((volatile uint16_t*)(0x40042168UL)) +#define FM4_USB0_EP2DT *((volatile uint16_t*)(0x40042168UL)) +#define FM_USB0_EP3DT *((volatile uint16_t*)(0x4004216CUL)) +#define FM4_USB0_EP3DT *((volatile uint16_t*)(0x4004216CUL)) +#define FM_USB0_EP4DT *((volatile uint16_t*)(0x40042170UL)) +#define FM4_USB0_EP4DT *((volatile uint16_t*)(0x40042170UL)) +#define FM_USB0_EP5DT *((volatile uint16_t*)(0x40042174UL)) +#define FM4_USB0_EP5DT *((volatile uint16_t*)(0x40042174UL)) + +/******************************************************************************* +* USB Registers USB1 +* Register Definition +*******************************************************************************/ +#define FM_USB1_HCNT *((volatile uint16_t*)(0x40054200UL)) +#define FM4_USB1_HCNT *((volatile uint16_t*)(0x40054200UL)) +#define FM_USB1_HIRQ *((volatile uint8_t*)(0x40054204UL)) +#define FM4_USB1_HIRQ *((volatile uint8_t*)(0x40054204UL)) +#define FM_USB1_HERR *((volatile uint8_t*)(0x40054205UL)) +#define FM4_USB1_HERR *((volatile uint8_t*)(0x40054205UL)) +#define FM_USB1_HSTATE *((volatile uint8_t*)(0x40054208UL)) +#define FM4_USB1_HSTATE *((volatile uint8_t*)(0x40054208UL)) +#define FM_USB1_HFCOMP *((volatile uint8_t*)(0x40054209UL)) +#define FM4_USB1_HFCOMP *((volatile uint8_t*)(0x40054209UL)) +#define FM_USB1_HRTIMER *((volatile uint16_t*)(0x4005420CUL)) +#define FM4_USB1_HRTIMER *((volatile uint16_t*)(0x4005420CUL)) +#define FM_USB1_HRTIMER2 *((volatile uint8_t*)(0x40054210UL)) +#define FM4_USB1_HRTIMER2 *((volatile uint8_t*)(0x40054210UL)) +#define FM_USB1_HADR *((volatile uint8_t*)(0x40054211UL)) +#define FM4_USB1_HADR *((volatile uint8_t*)(0x40054211UL)) +#define FM_USB1_HEOF *((volatile uint16_t*)(0x40054214UL)) +#define FM4_USB1_HEOF *((volatile uint16_t*)(0x40054214UL)) +#define FM_USB1_HFRAME *((volatile uint16_t*)(0x40054218UL)) +#define FM4_USB1_HFRAME *((volatile uint16_t*)(0x40054218UL)) +#define FM_USB1_HTOKEN *((volatile uint8_t*)(0x4005421CUL)) +#define FM4_USB1_HTOKEN *((volatile uint8_t*)(0x4005421CUL)) +#define FM_USB1_UDCC *((volatile uint16_t*)(0x40054220UL)) +#define FM4_USB1_UDCC *((volatile uint16_t*)(0x40054220UL)) +#define FM_USB1_EP0C *((volatile uint16_t*)(0x40054224UL)) +#define FM4_USB1_EP0C *((volatile uint16_t*)(0x40054224UL)) +#define FM_USB1_EP1C *((volatile uint16_t*)(0x40054228UL)) +#define FM4_USB1_EP1C *((volatile uint16_t*)(0x40054228UL)) +#define FM_USB1_EP2C *((volatile uint16_t*)(0x4005422CUL)) +#define FM4_USB1_EP2C *((volatile uint16_t*)(0x4005422CUL)) +#define FM_USB1_EP3C *((volatile uint16_t*)(0x40054230UL)) +#define FM4_USB1_EP3C *((volatile uint16_t*)(0x40054230UL)) +#define FM_USB1_EP4C *((volatile uint16_t*)(0x40054234UL)) +#define FM4_USB1_EP4C *((volatile uint16_t*)(0x40054234UL)) +#define FM_USB1_EP5C *((volatile uint16_t*)(0x40054238UL)) +#define FM4_USB1_EP5C *((volatile uint16_t*)(0x40054238UL)) +#define FM_USB1_TMSP *((volatile uint16_t*)(0x4005423CUL)) +#define FM4_USB1_TMSP *((volatile uint16_t*)(0x4005423CUL)) +#define FM_USB1_UDCS *((volatile uint8_t*)(0x40054240UL)) +#define FM4_USB1_UDCS *((volatile uint8_t*)(0x40054240UL)) +#define FM_USB1_UDCIE *((volatile uint8_t*)(0x40054241UL)) +#define FM4_USB1_UDCIE *((volatile uint8_t*)(0x40054241UL)) +#define FM_USB1_EP0IS *((volatile uint16_t*)(0x40054244UL)) +#define FM4_USB1_EP0IS *((volatile uint16_t*)(0x40054244UL)) +#define FM_USB1_EP0OS *((volatile uint16_t*)(0x40054248UL)) +#define FM4_USB1_EP0OS *((volatile uint16_t*)(0x40054248UL)) +#define FM_USB1_EP1S *((volatile uint16_t*)(0x4005424CUL)) +#define FM4_USB1_EP1S *((volatile uint16_t*)(0x4005424CUL)) +#define FM_USB1_EP2S *((volatile uint16_t*)(0x40054250UL)) +#define FM4_USB1_EP2S *((volatile uint16_t*)(0x40054250UL)) +#define FM_USB1_EP3S *((volatile uint16_t*)(0x40054254UL)) +#define FM4_USB1_EP3S *((volatile uint16_t*)(0x40054254UL)) +#define FM_USB1_EP4S *((volatile uint16_t*)(0x40054258UL)) +#define FM4_USB1_EP4S *((volatile uint16_t*)(0x40054258UL)) +#define FM_USB1_EP5S *((volatile uint16_t*)(0x4005425CUL)) +#define FM4_USB1_EP5S *((volatile uint16_t*)(0x4005425CUL)) +#define FM_USB1_EP0DT *((volatile uint16_t*)(0x40054260UL)) +#define FM4_USB1_EP0DT *((volatile uint16_t*)(0x40054260UL)) +#define FM_USB1_EP1DT *((volatile uint16_t*)(0x40054264UL)) +#define FM4_USB1_EP1DT *((volatile uint16_t*)(0x40054264UL)) +#define FM_USB1_EP2DT *((volatile uint16_t*)(0x40054268UL)) +#define FM4_USB1_EP2DT *((volatile uint16_t*)(0x40054268UL)) +#define FM_USB1_EP3DT *((volatile uint16_t*)(0x4005426CUL)) +#define FM4_USB1_EP3DT *((volatile uint16_t*)(0x4005426CUL)) +#define FM_USB1_EP4DT *((volatile uint16_t*)(0x40054270UL)) +#define FM4_USB1_EP4DT *((volatile uint16_t*)(0x40054270UL)) +#define FM_USB1_EP5DT *((volatile uint16_t*)(0x40054274UL)) +#define FM4_USB1_EP5DT *((volatile uint16_t*)(0x40054274UL)) + +/******************************************************************************* +* USBCLK Registers USBCLK +* Register Definition +*******************************************************************************/ +#define FM_USBCLK_UCCR *((volatile uint8_t*)(0x40036000UL)) +#define FM4_USBCLK_UCCR *((volatile uint8_t*)(0x40036000UL)) +#define FM_USBCLK_UPCR1 *((volatile uint8_t*)(0x40036004UL)) +#define FM4_USBCLK_UPCR1 *((volatile uint8_t*)(0x40036004UL)) +#define FM_USBCLK_UPCR2 *((volatile uint8_t*)(0x40036008UL)) +#define FM4_USBCLK_UPCR2 *((volatile uint8_t*)(0x40036008UL)) +#define FM_USBCLK_UPCR3 *((volatile uint8_t*)(0x4003600CUL)) +#define FM4_USBCLK_UPCR3 *((volatile uint8_t*)(0x4003600CUL)) +#define FM_USBCLK_UPCR4 *((volatile uint8_t*)(0x40036010UL)) +#define FM4_USBCLK_UPCR4 *((volatile uint8_t*)(0x40036010UL)) +#define FM_USBCLK_UP_STR *((volatile uint8_t*)(0x40036014UL)) +#define FM4_USBCLK_UP_STR *((volatile uint8_t*)(0x40036014UL)) +#define FM_USBCLK_UPINT_ENR *((volatile uint8_t*)(0x40036018UL)) +#define FM4_USBCLK_UPINT_ENR *((volatile uint8_t*)(0x40036018UL)) +#define FM_USBCLK_UPINT_CLR *((volatile uint8_t*)(0x4003601CUL)) +#define FM4_USBCLK_UPINT_CLR *((volatile uint8_t*)(0x4003601CUL)) +#define FM_USBCLK_UPINT_STR *((volatile uint8_t*)(0x40036020UL)) +#define FM4_USBCLK_UPINT_STR *((volatile uint8_t*)(0x40036020UL)) +#define FM_USBCLK_UPCR5 *((volatile uint8_t*)(0x40036024UL)) +#define FM4_USBCLK_UPCR5 *((volatile uint8_t*)(0x40036024UL)) +#define FM_USBCLK_USBEN0 *((volatile uint8_t*)(0x40036030UL)) +#define FM4_USBCLK_USBEN0 *((volatile uint8_t*)(0x40036030UL)) +#define FM_USBCLK_USBEN1 *((volatile uint8_t*)(0x40036034UL)) +#define FM4_USBCLK_USBEN1 *((volatile uint8_t*)(0x40036034UL)) + +/******************************************************************************* +* WC Registers WC +* Register Definition +*******************************************************************************/ +#define FM_WC_WCRD *((volatile uint8_t*)(0x4003A000UL)) +#define FM4_WC_WCRD *((volatile uint8_t*)(0x4003A000UL)) +#define FM_WC_WCRL *((volatile uint8_t*)(0x4003A001UL)) +#define FM4_WC_WCRL *((volatile uint8_t*)(0x4003A001UL)) +#define FM_WC_WCCR *((volatile uint8_t*)(0x4003A002UL)) +#define FM4_WC_WCCR *((volatile uint8_t*)(0x4003A002UL)) +#define FM_WC_CLK_SEL *((volatile uint16_t*)(0x4003A010UL)) +#define FM4_WC_CLK_SEL *((volatile uint16_t*)(0x4003A010UL)) +#define FM_WC_CLK_EN *((volatile uint8_t*)(0x4003A014UL)) +#define FM4_WC_CLK_EN *((volatile uint8_t*)(0x4003A014UL)) + +/******************************************************************************* +* Available Registers +*******************************************************************************/ +/******************************************************************************* +* ADC0 +*******************************************************************************/ +#define FM4_ADC_ADCEN_AVAILABLE 1 +#define FM_ADC_ADCEN_AVAILABLE 1 +#define FM4_ADC_ADCR_AVAILABLE 1 +#define FM_ADC_ADCR_AVAILABLE 1 +#define FM4_ADC_ADCT_AVAILABLE 1 +#define FM_ADC_ADCT_AVAILABLE 1 +#define FM4_ADC_ADSR_AVAILABLE 1 +#define FM_ADC_ADSR_AVAILABLE 1 +#define FM4_ADC_ADSS01_AVAILABLE 1 +#define FM_ADC_ADSS01_AVAILABLE 1 +#define FM4_ADC_ADSS23_AVAILABLE 1 +#define FM_ADC_ADSS23_AVAILABLE 1 +#define FM4_ADC_ADST01_AVAILABLE 1 +#define FM_ADC_ADST01_AVAILABLE 1 +#define FM4_ADC_CALSR_AVAILABLE 1 +#define FM_ADC_CALSR_AVAILABLE 1 +#define FM4_ADC_CMPCR_AVAILABLE 1 +#define FM_ADC_CMPCR_AVAILABLE 1 +#define FM4_ADC_CMPD_AVAILABLE 1 +#define FM_ADC_CMPD_AVAILABLE 1 +#define FM4_ADC_PCCR_AVAILABLE 1 +#define FM_ADC_PCCR_AVAILABLE 1 +#define FM4_ADC_PCFD_AVAILABLE 1 +#define FM_ADC_PCFD_AVAILABLE 1 +#define FM4_ADC_PCFD_FDAS1_AVAILABLE 1 +#define FM_ADC_PCFD_FDAS1_AVAILABLE 1 +#define FM4_ADC_PCIS_AVAILABLE 1 +#define FM_ADC_PCIS_AVAILABLE 1 +#define FM4_ADC_PFNS_AVAILABLE 1 +#define FM_ADC_PFNS_AVAILABLE 1 +#define FM4_ADC_PRTSL_AVAILABLE 1 +#define FM_ADC_PRTSL_AVAILABLE 1 +#define FM4_ADC_SCCR_AVAILABLE 1 +#define FM_ADC_SCCR_AVAILABLE 1 +#define FM4_ADC_SCFD_AVAILABLE 1 +#define FM_ADC_SCFD_AVAILABLE 1 +#define FM4_ADC_SCFD_FDAS1_AVAILABLE 1 +#define FM_ADC_SCFD_FDAS1_AVAILABLE 1 +#define FM4_ADC_SCIS01_AVAILABLE 1 +#define FM_ADC_SCIS01_AVAILABLE 1 +#define FM4_ADC_SCIS23_AVAILABLE 1 +#define FM_ADC_SCIS23_AVAILABLE 1 +#define FM4_ADC_SCTSL_AVAILABLE 1 +#define FM_ADC_SCTSL_AVAILABLE 1 +#define FM4_ADC_SFNS_AVAILABLE 1 +#define FM_ADC_SFNS_AVAILABLE 1 +#define FM4_ADC_WCMPCR_AVAILABLE 1 +#define FM_ADC_WCMPCR_AVAILABLE 1 +#define FM4_ADC_WCMPDH_AVAILABLE 1 +#define FM_ADC_WCMPDH_AVAILABLE 1 +#define FM4_ADC_WCMPDL_AVAILABLE 1 +#define FM_ADC_WCMPDL_AVAILABLE 1 +#define FM4_ADC_WCMPSR_AVAILABLE 1 +#define FM_ADC_WCMPSR_AVAILABLE 1 +#define FM4_ADC_WCMRCIF_AVAILABLE 1 +#define FM_ADC_WCMRCIF_AVAILABLE 1 +#define FM4_ADC_WCMRCOT_AVAILABLE 1 +#define FM_ADC_WCMRCOT_AVAILABLE 1 +/******************************************************************************* +* BT0 +*******************************************************************************/ +#define FM4_BT_PPG_PRLH_AVAILABLE 1 +#define FM_BT_PPG_PRLH_AVAILABLE 1 +#define FM4_BT_PPG_PRLL_AVAILABLE 1 +#define FM_BT_PPG_PRLL_AVAILABLE 1 +#define FM4_BT_PPG_STC_AVAILABLE 1 +#define FM_BT_PPG_STC_AVAILABLE 1 +#define FM4_BT_PPG_TMCR_AVAILABLE 1 +#define FM_BT_PPG_TMCR_AVAILABLE 1 +#define FM4_BT_PPG_TMCR2_AVAILABLE 1 +#define FM_BT_PPG_TMCR2_AVAILABLE 1 +#define FM4_BT_PPG_TMR_AVAILABLE 1 +#define FM_BT_PPG_TMR_AVAILABLE 1 +#define FM4_BT_PWC_DTBF_AVAILABLE 1 +#define FM_BT_PWC_DTBF_AVAILABLE 1 +#define FM4_BT_PWC_STC_AVAILABLE 1 +#define FM_BT_PWC_STC_AVAILABLE 1 +#define FM4_BT_PWC_TMCR_AVAILABLE 1 +#define FM_BT_PWC_TMCR_AVAILABLE 1 +#define FM4_BT_PWC_TMCR2_AVAILABLE 1 +#define FM_BT_PWC_TMCR2_AVAILABLE 1 +#define FM4_BT_PWM_PCSR_AVAILABLE 1 +#define FM_BT_PWM_PCSR_AVAILABLE 1 +#define FM4_BT_PWM_PDUT_AVAILABLE 1 +#define FM_BT_PWM_PDUT_AVAILABLE 1 +#define FM4_BT_PWM_STC_AVAILABLE 1 +#define FM_BT_PWM_STC_AVAILABLE 1 +#define FM4_BT_PWM_TMCR_AVAILABLE 1 +#define FM_BT_PWM_TMCR_AVAILABLE 1 +#define FM4_BT_PWM_TMCR2_AVAILABLE 1 +#define FM_BT_PWM_TMCR2_AVAILABLE 1 +#define FM4_BT_PWM_TMR_AVAILABLE 1 +#define FM_BT_PWM_TMR_AVAILABLE 1 +#define FM4_BT_RT_PCSR_AVAILABLE 1 +#define FM_BT_RT_PCSR_AVAILABLE 1 +#define FM4_BT_RT_STC_AVAILABLE 1 +#define FM_BT_RT_STC_AVAILABLE 1 +#define FM4_BT_RT_TMCR_AVAILABLE 1 +#define FM_BT_RT_TMCR_AVAILABLE 1 +#define FM4_BT_RT_TMCR2_AVAILABLE 1 +#define FM_BT_RT_TMCR2_AVAILABLE 1 +#define FM4_BT_RT_TMR_AVAILABLE 1 +#define FM_BT_RT_TMR_AVAILABLE 1 +/******************************************************************************* +* BTIOSEL03 +*******************************************************************************/ +#define FM4_BTIOSEL03_BTSEL0123_AVAILABLE 1 +#define FM_BTIOSEL03_BTSEL0123_AVAILABLE 1 +/******************************************************************************* +* BTIOSEL47 +*******************************************************************************/ +#define FM4_BTIOSEL47_BTSEL4567_AVAILABLE 1 +#define FM_BTIOSEL47_BTSEL4567_AVAILABLE 1 +/******************************************************************************* +* BTIOSEL8B +*******************************************************************************/ +#define FM4_BTIOSEL8B_BTSEL89AB_AVAILABLE 1 +#define FM_BTIOSEL8B_BTSEL89AB_AVAILABLE 1 +/******************************************************************************* +* BTIOSELCF +*******************************************************************************/ +#define FM4_BTIOSELCF_BTSELCDEF_AVAILABLE 1 +#define FM_BTIOSELCF_BTSELCDEF_AVAILABLE 1 +/******************************************************************************* +* CAN0 +*******************************************************************************/ +#define FM4_CAN_BRPER_AVAILABLE 1 +#define FM_CAN_BRPER_AVAILABLE 1 +#define FM4_CAN_BTR_AVAILABLE 1 +#define FM_CAN_BTR_AVAILABLE 1 +#define FM4_CAN_CTRLR_AVAILABLE 1 +#define FM_CAN_CTRLR_AVAILABLE 1 +#define FM4_CAN_ERRCNT_AVAILABLE 1 +#define FM_CAN_ERRCNT_AVAILABLE 1 +#define FM4_CAN_IF1ARB_AVAILABLE 1 +#define FM_CAN_IF1ARB_AVAILABLE 1 +#define FM4_CAN_IF1CMSK_AVAILABLE 1 +#define FM_CAN_IF1CMSK_AVAILABLE 1 +#define FM4_CAN_IF1CREQ_AVAILABLE 1 +#define FM_CAN_IF1CREQ_AVAILABLE 1 +#define FM4_CAN_IF1DTA_B_AVAILABLE 1 +#define FM_CAN_IF1DTA_B_AVAILABLE 1 +#define FM4_CAN_IF1DTA_L_AVAILABLE 1 +#define FM_CAN_IF1DTA_L_AVAILABLE 1 +#define FM4_CAN_IF1DTB_B_AVAILABLE 1 +#define FM_CAN_IF1DTB_B_AVAILABLE 1 +#define FM4_CAN_IF1DTB_L_AVAILABLE 1 +#define FM_CAN_IF1DTB_L_AVAILABLE 1 +#define FM4_CAN_IF1MCTR_AVAILABLE 1 +#define FM_CAN_IF1MCTR_AVAILABLE 1 +#define FM4_CAN_IF1MSK_AVAILABLE 1 +#define FM_CAN_IF1MSK_AVAILABLE 1 +#define FM4_CAN_IF2ARB_AVAILABLE 1 +#define FM_CAN_IF2ARB_AVAILABLE 1 +#define FM4_CAN_IF2CMSK_AVAILABLE 1 +#define FM_CAN_IF2CMSK_AVAILABLE 1 +#define FM4_CAN_IF2CREQ_AVAILABLE 1 +#define FM_CAN_IF2CREQ_AVAILABLE 1 +#define FM4_CAN_IF2DTA_B_AVAILABLE 1 +#define FM_CAN_IF2DTA_B_AVAILABLE 1 +#define FM4_CAN_IF2DTA_L_AVAILABLE 1 +#define FM_CAN_IF2DTA_L_AVAILABLE 1 +#define FM4_CAN_IF2DTB_B_AVAILABLE 1 +#define FM_CAN_IF2DTB_B_AVAILABLE 1 +#define FM4_CAN_IF2DTB_L_AVAILABLE 1 +#define FM_CAN_IF2DTB_L_AVAILABLE 1 +#define FM4_CAN_IF2MCTR_AVAILABLE 1 +#define FM_CAN_IF2MCTR_AVAILABLE 1 +#define FM4_CAN_IF2MSK_AVAILABLE 1 +#define FM_CAN_IF2MSK_AVAILABLE 1 +#define FM4_CAN_INTPND_AVAILABLE 1 +#define FM_CAN_INTPND_AVAILABLE 1 +#define FM4_CAN_INTR_AVAILABLE 1 +#define FM_CAN_INTR_AVAILABLE 1 +#define FM4_CAN_MSGVAL_AVAILABLE 1 +#define FM_CAN_MSGVAL_AVAILABLE 1 +#define FM4_CAN_NEWDT_AVAILABLE 1 +#define FM_CAN_NEWDT_AVAILABLE 1 +#define FM4_CAN_STATR_AVAILABLE 1 +#define FM_CAN_STATR_AVAILABLE 1 +#define FM4_CAN_TESTR_AVAILABLE 1 +#define FM_CAN_TESTR_AVAILABLE 1 +#define FM4_CAN_TREQR_AVAILABLE 1 +#define FM_CAN_TREQR_AVAILABLE 1 +/******************************************************************************* +* CANFD0 +*******************************************************************************/ +#define FM4_CANFD_BTP_AVAILABLE 1 +#define FM_CANFD_BTP_AVAILABLE 1 +#define FM4_CANFD_CCCR_AVAILABLE 1 +#define FM_CANFD_CCCR_AVAILABLE 1 +#define FM4_CANFD_CREL_AVAILABLE 1 +#define FM_CANFD_CREL_AVAILABLE 1 +#define FM4_CANFD_ECR_AVAILABLE 1 +#define FM_CANFD_ECR_AVAILABLE 1 +#define FM4_CANFD_ENDN_AVAILABLE 1 +#define FM_CANFD_ENDN_AVAILABLE 1 +#define FM4_CANFD_FBTP_AVAILABLE 1 +#define FM_CANFD_FBTP_AVAILABLE 1 +#define FM4_CANFD_FDDEAR_AVAILABLE 1 +#define FM_CANFD_FDDEAR_AVAILABLE 1 +#define FM4_CANFD_FDECR_AVAILABLE 1 +#define FM_CANFD_FDECR_AVAILABLE 1 +#define FM4_CANFD_FDESCR_AVAILABLE 1 +#define FM_CANFD_FDESCR_AVAILABLE 1 +#define FM4_CANFD_FDESR_AVAILABLE 1 +#define FM_CANFD_FDESR_AVAILABLE 1 +#define FM4_CANFD_FDSEAR_AVAILABLE 1 +#define FM_CANFD_FDSEAR_AVAILABLE 1 +#define FM4_CANFD_GFC_AVAILABLE 1 +#define FM_CANFD_GFC_AVAILABLE 1 +#define FM4_CANFD_HPMS_AVAILABLE 1 +#define FM_CANFD_HPMS_AVAILABLE 1 +#define FM4_CANFD_IE_AVAILABLE 1 +#define FM_CANFD_IE_AVAILABLE 1 +#define FM4_CANFD_ILE_AVAILABLE 1 +#define FM_CANFD_ILE_AVAILABLE 1 +#define FM4_CANFD_ILS_AVAILABLE 1 +#define FM_CANFD_ILS_AVAILABLE 1 +#define FM4_CANFD_IR_AVAILABLE 1 +#define FM_CANFD_IR_AVAILABLE 1 +#define FM4_CANFD_NDAT1_AVAILABLE 1 +#define FM_CANFD_NDAT1_AVAILABLE 1 +#define FM4_CANFD_NDAT2_AVAILABLE 1 +#define FM_CANFD_NDAT2_AVAILABLE 1 +#define FM4_CANFD_PSR_AVAILABLE 1 +#define FM_CANFD_PSR_AVAILABLE 1 +#define FM4_CANFD_RWD_AVAILABLE 1 +#define FM_CANFD_RWD_AVAILABLE 1 +#define FM4_CANFD_RXBC_AVAILABLE 1 +#define FM_CANFD_RXBC_AVAILABLE 1 +#define FM4_CANFD_RXESC_AVAILABLE 1 +#define FM_CANFD_RXESC_AVAILABLE 1 +#define FM4_CANFD_RXF0A_AVAILABLE 1 +#define FM_CANFD_RXF0A_AVAILABLE 1 +#define FM4_CANFD_RXF0C_AVAILABLE 1 +#define FM_CANFD_RXF0C_AVAILABLE 1 +#define FM4_CANFD_RXF0S_AVAILABLE 1 +#define FM_CANFD_RXF0S_AVAILABLE 1 +#define FM4_CANFD_RXF1A_AVAILABLE 1 +#define FM_CANFD_RXF1A_AVAILABLE 1 +#define FM4_CANFD_RXF1C_AVAILABLE 1 +#define FM_CANFD_RXF1C_AVAILABLE 1 +#define FM4_CANFD_RXF1S_AVAILABLE 1 +#define FM_CANFD_RXF1S_AVAILABLE 1 +#define FM4_CANFD_SIDFC_AVAILABLE 1 +#define FM_CANFD_SIDFC_AVAILABLE 1 +#define FM4_CANFD_TEST_AVAILABLE 1 +#define FM_CANFD_TEST_AVAILABLE 1 +#define FM4_CANFD_TOCC_AVAILABLE 1 +#define FM_CANFD_TOCC_AVAILABLE 1 +#define FM4_CANFD_TOCV_AVAILABLE 1 +#define FM_CANFD_TOCV_AVAILABLE 1 +#define FM4_CANFD_TSCC_AVAILABLE 1 +#define FM_CANFD_TSCC_AVAILABLE 1 +#define FM4_CANFD_TSCDTR_AVAILABLE 1 +#define FM_CANFD_TSCDTR_AVAILABLE 1 +#define FM4_CANFD_TSCNTR_AVAILABLE 1 +#define FM_CANFD_TSCNTR_AVAILABLE 1 +#define FM4_CANFD_TSCPCLR_AVAILABLE 1 +#define FM_CANFD_TSCPCLR_AVAILABLE 1 +#define FM4_CANFD_TSCV_AVAILABLE 1 +#define FM_CANFD_TSCV_AVAILABLE 1 +#define FM4_CANFD_TSDIVR_AVAILABLE 1 +#define FM_CANFD_TSDIVR_AVAILABLE 1 +#define FM4_CANFD_TSMDR_AVAILABLE 1 +#define FM_CANFD_TSMDR_AVAILABLE 1 +#define FM4_CANFD_TXBAR_AVAILABLE 1 +#define FM_CANFD_TXBAR_AVAILABLE 1 +#define FM4_CANFD_TXBC_AVAILABLE 1 +#define FM_CANFD_TXBC_AVAILABLE 1 +#define FM4_CANFD_TXBCF_AVAILABLE 1 +#define FM_CANFD_TXBCF_AVAILABLE 1 +#define FM4_CANFD_TXBCIE_AVAILABLE 1 +#define FM_CANFD_TXBCIE_AVAILABLE 1 +#define FM4_CANFD_TXBCR_AVAILABLE 1 +#define FM_CANFD_TXBCR_AVAILABLE 1 +#define FM4_CANFD_TXBRP_AVAILABLE 1 +#define FM_CANFD_TXBRP_AVAILABLE 1 +#define FM4_CANFD_TXBTIE_AVAILABLE 1 +#define FM_CANFD_TXBTIE_AVAILABLE 1 +#define FM4_CANFD_TXBTO_AVAILABLE 1 +#define FM_CANFD_TXBTO_AVAILABLE 1 +#define FM4_CANFD_TXEFC_AVAILABLE 1 +#define FM_CANFD_TXEFC_AVAILABLE 1 +#define FM4_CANFD_TXESC_AVAILABLE 1 +#define FM_CANFD_TXESC_AVAILABLE 1 +#define FM4_CANFD_TXFA_AVAILABLE 1 +#define FM_CANFD_TXFA_AVAILABLE 1 +#define FM4_CANFD_TXFQS_AVAILABLE 1 +#define FM_CANFD_TXFQS_AVAILABLE 1 +#define FM4_CANFD_TXFS_AVAILABLE 1 +#define FM_CANFD_TXFS_AVAILABLE 1 +#define FM4_CANFD_XIDAM_AVAILABLE 1 +#define FM_CANFD_XIDAM_AVAILABLE 1 +#define FM4_CANFD_XIDFC_AVAILABLE 1 +#define FM_CANFD_XIDFC_AVAILABLE 1 +/******************************************************************************* +* CANPRES +*******************************************************************************/ +#define FM4_CANPRES_CANPRE_AVAILABLE 1 +#define FM_CANPRES_CANPRE_AVAILABLE 1 +/******************************************************************************* +* CLK_GATING +*******************************************************************************/ +#define FM4_CLK_GATING_CKEN0_AVAILABLE 1 +#define FM_CLK_GATING_CKEN0_AVAILABLE 1 +#define FM4_CLK_GATING_CKEN1_AVAILABLE 1 +#define FM_CLK_GATING_CKEN1_AVAILABLE 1 +#define FM4_CLK_GATING_CKEN2_AVAILABLE 1 +#define FM_CLK_GATING_CKEN2_AVAILABLE 1 +#define FM4_CLK_GATING_MRST0_AVAILABLE 1 +#define FM_CLK_GATING_MRST0_AVAILABLE 1 +#define FM4_CLK_GATING_MRST1_AVAILABLE 1 +#define FM_CLK_GATING_MRST1_AVAILABLE 1 +#define FM4_CLK_GATING_MRST2_AVAILABLE 1 +#define FM_CLK_GATING_MRST2_AVAILABLE 1 +/******************************************************************************* +* CRC +*******************************************************************************/ +#define FM4_CRC_CRCCR_AVAILABLE 1 +#define FM_CRC_CRCCR_AVAILABLE 1 +#define FM4_CRC_CRCIN_AVAILABLE 1 +#define FM_CRC_CRCIN_AVAILABLE 1 +#define FM4_CRC_CRCINIT_AVAILABLE 1 +#define FM_CRC_CRCINIT_AVAILABLE 1 +#define FM4_CRC_CRCR_AVAILABLE 1 +#define FM_CRC_CRCR_AVAILABLE 1 +/******************************************************************************* +* CRG +*******************************************************************************/ +#define FM4_CRG_APBC0_PSR_AVAILABLE 1 +#define FM_CRG_APBC0_PSR_AVAILABLE 1 +#define FM4_CRG_APBC1_PSR_AVAILABLE 1 +#define FM_CRG_APBC1_PSR_AVAILABLE 1 +#define FM4_CRG_APBC2_PSR_AVAILABLE 1 +#define FM_CRG_APBC2_PSR_AVAILABLE 1 +#define FM4_CRG_BSC_PSR_AVAILABLE 1 +#define FM_CRG_BSC_PSR_AVAILABLE 1 +#define FM4_CRG_CSV_CTL_AVAILABLE 1 +#define FM_CRG_CSV_CTL_AVAILABLE 1 +#define FM4_CRG_CSV_STR_AVAILABLE 1 +#define FM_CRG_CSV_STR_AVAILABLE 1 +#define FM4_CRG_CSW_TMR_AVAILABLE 1 +#define FM_CRG_CSW_TMR_AVAILABLE 1 +#define FM4_CRG_DBWDT_CTL_AVAILABLE 1 +#define FM_CRG_DBWDT_CTL_AVAILABLE 1 +#define FM4_CRG_FCSWD_CTL_AVAILABLE 1 +#define FM_CRG_FCSWD_CTL_AVAILABLE 1 +#define FM4_CRG_FCSWH_CTL_AVAILABLE 1 +#define FM_CRG_FCSWH_CTL_AVAILABLE 1 +#define FM4_CRG_FCSWL_CTL_AVAILABLE 1 +#define FM_CRG_FCSWL_CTL_AVAILABLE 1 +#define FM4_CRG_INT_CLR_AVAILABLE 1 +#define FM_CRG_INT_CLR_AVAILABLE 1 +#define FM4_CRG_INT_ENR_AVAILABLE 1 +#define FM_CRG_INT_ENR_AVAILABLE 1 +#define FM4_CRG_INT_STR_AVAILABLE 1 +#define FM_CRG_INT_STR_AVAILABLE 1 +#define FM4_CRG_PLL_CTL1_AVAILABLE 1 +#define FM_CRG_PLL_CTL1_AVAILABLE 1 +#define FM4_CRG_PLL_CTL2_AVAILABLE 1 +#define FM_CRG_PLL_CTL2_AVAILABLE 1 +#define FM4_CRG_PLLCG_CTL_AVAILABLE 1 +#define FM_CRG_PLLCG_CTL_AVAILABLE 1 +#define FM4_CRG_PSW_TMR_AVAILABLE 1 +#define FM_CRG_PSW_TMR_AVAILABLE 1 +#define FM4_CRG_RST_STR_AVAILABLE 1 +#define FM_CRG_RST_STR_AVAILABLE 1 +#define FM4_CRG_SCM_CTL_AVAILABLE 1 +#define FM_CRG_SCM_CTL_AVAILABLE 1 +#define FM4_CRG_SCM_STR_AVAILABLE 1 +#define FM_CRG_SCM_STR_AVAILABLE 1 +#define FM4_CRG_STB_CTL_AVAILABLE 1 +#define FM_CRG_STB_CTL_AVAILABLE 1 +#define FM4_CRG_SWC_PSR_AVAILABLE 1 +#define FM_CRG_SWC_PSR_AVAILABLE 1 +#define FM4_CRG_TTC_PSR_AVAILABLE 1 +#define FM_CRG_TTC_PSR_AVAILABLE 1 +/******************************************************************************* +* CRTRIM +*******************************************************************************/ +#define FM4_CRTRIM_MCR_FTRM_AVAILABLE 1 +#define FM_CRTRIM_MCR_FTRM_AVAILABLE 1 +#define FM4_CRTRIM_MCR_PSR_AVAILABLE 1 +#define FM_CRTRIM_MCR_PSR_AVAILABLE 1 +#define FM4_CRTRIM_MCR_RLR_AVAILABLE 1 +#define FM_CRTRIM_MCR_RLR_AVAILABLE 1 +#define FM4_CRTRIM_MCR_TTRM_AVAILABLE 1 +#define FM_CRTRIM_MCR_TTRM_AVAILABLE 1 +/******************************************************************************* +* DAC0 +*******************************************************************************/ +#define FM4_DAC_DACR_AVAILABLE 1 +#define FM_DAC_DACR_AVAILABLE 1 +#define FM4_DAC_DADR_AVAILABLE 1 +#define FM_DAC_DADR_AVAILABLE 1 +/******************************************************************************* +* DMAC +*******************************************************************************/ +#define FM4_DMAC_DMACA0_AVAILABLE 1 +#define FM_DMAC_DMACA0_AVAILABLE 1 +#define FM4_DMAC_DMACA1_AVAILABLE 1 +#define FM_DMAC_DMACA1_AVAILABLE 1 +#define FM4_DMAC_DMACA2_AVAILABLE 1 +#define FM_DMAC_DMACA2_AVAILABLE 1 +#define FM4_DMAC_DMACA3_AVAILABLE 1 +#define FM_DMAC_DMACA3_AVAILABLE 1 +#define FM4_DMAC_DMACA4_AVAILABLE 1 +#define FM_DMAC_DMACA4_AVAILABLE 1 +#define FM4_DMAC_DMACA5_AVAILABLE 1 +#define FM_DMAC_DMACA5_AVAILABLE 1 +#define FM4_DMAC_DMACA6_AVAILABLE 1 +#define FM_DMAC_DMACA6_AVAILABLE 1 +#define FM4_DMAC_DMACA7_AVAILABLE 1 +#define FM_DMAC_DMACA7_AVAILABLE 1 +#define FM4_DMAC_DMACB0_AVAILABLE 1 +#define FM_DMAC_DMACB0_AVAILABLE 1 +#define FM4_DMAC_DMACB1_AVAILABLE 1 +#define FM_DMAC_DMACB1_AVAILABLE 1 +#define FM4_DMAC_DMACB2_AVAILABLE 1 +#define FM_DMAC_DMACB2_AVAILABLE 1 +#define FM4_DMAC_DMACB3_AVAILABLE 1 +#define FM_DMAC_DMACB3_AVAILABLE 1 +#define FM4_DMAC_DMACB4_AVAILABLE 1 +#define FM_DMAC_DMACB4_AVAILABLE 1 +#define FM4_DMAC_DMACB5_AVAILABLE 1 +#define FM_DMAC_DMACB5_AVAILABLE 1 +#define FM4_DMAC_DMACB6_AVAILABLE 1 +#define FM_DMAC_DMACB6_AVAILABLE 1 +#define FM4_DMAC_DMACB7_AVAILABLE 1 +#define FM_DMAC_DMACB7_AVAILABLE 1 +#define FM4_DMAC_DMACDA0_AVAILABLE 1 +#define FM_DMAC_DMACDA0_AVAILABLE 1 +#define FM4_DMAC_DMACDA1_AVAILABLE 1 +#define FM_DMAC_DMACDA1_AVAILABLE 1 +#define FM4_DMAC_DMACDA2_AVAILABLE 1 +#define FM_DMAC_DMACDA2_AVAILABLE 1 +#define FM4_DMAC_DMACDA3_AVAILABLE 1 +#define FM_DMAC_DMACDA3_AVAILABLE 1 +#define FM4_DMAC_DMACDA4_AVAILABLE 1 +#define FM_DMAC_DMACDA4_AVAILABLE 1 +#define FM4_DMAC_DMACDA5_AVAILABLE 1 +#define FM_DMAC_DMACDA5_AVAILABLE 1 +#define FM4_DMAC_DMACDA6_AVAILABLE 1 +#define FM_DMAC_DMACDA6_AVAILABLE 1 +#define FM4_DMAC_DMACDA7_AVAILABLE 1 +#define FM_DMAC_DMACDA7_AVAILABLE 1 +#define FM4_DMAC_DMACR_AVAILABLE 1 +#define FM_DMAC_DMACR_AVAILABLE 1 +#define FM4_DMAC_DMACSA0_AVAILABLE 1 +#define FM_DMAC_DMACSA0_AVAILABLE 1 +#define FM4_DMAC_DMACSA1_AVAILABLE 1 +#define FM_DMAC_DMACSA1_AVAILABLE 1 +#define FM4_DMAC_DMACSA2_AVAILABLE 1 +#define FM_DMAC_DMACSA2_AVAILABLE 1 +#define FM4_DMAC_DMACSA3_AVAILABLE 1 +#define FM_DMAC_DMACSA3_AVAILABLE 1 +#define FM4_DMAC_DMACSA4_AVAILABLE 1 +#define FM_DMAC_DMACSA4_AVAILABLE 1 +#define FM4_DMAC_DMACSA5_AVAILABLE 1 +#define FM_DMAC_DMACSA5_AVAILABLE 1 +#define FM4_DMAC_DMACSA6_AVAILABLE 1 +#define FM_DMAC_DMACSA6_AVAILABLE 1 +#define FM4_DMAC_DMACSA7_AVAILABLE 1 +#define FM_DMAC_DMACSA7_AVAILABLE 1 +/******************************************************************************* +* DS +*******************************************************************************/ +#define FM4_DS_BUR01_AVAILABLE 1 +#define FM_DS_BUR01_AVAILABLE 1 +#define FM4_DS_BUR02_AVAILABLE 1 +#define FM_DS_BUR02_AVAILABLE 1 +#define FM4_DS_BUR03_AVAILABLE 1 +#define FM_DS_BUR03_AVAILABLE 1 +#define FM4_DS_BUR04_AVAILABLE 1 +#define FM_DS_BUR04_AVAILABLE 1 +#define FM4_DS_BUR05_AVAILABLE 1 +#define FM_DS_BUR05_AVAILABLE 1 +#define FM4_DS_BUR06_AVAILABLE 1 +#define FM_DS_BUR06_AVAILABLE 1 +#define FM4_DS_BUR07_AVAILABLE 1 +#define FM_DS_BUR07_AVAILABLE 1 +#define FM4_DS_BUR08_AVAILABLE 1 +#define FM_DS_BUR08_AVAILABLE 1 +#define FM4_DS_BUR09_AVAILABLE 1 +#define FM_DS_BUR09_AVAILABLE 1 +#define FM4_DS_BUR10_AVAILABLE 1 +#define FM_DS_BUR10_AVAILABLE 1 +#define FM4_DS_BUR11_AVAILABLE 1 +#define FM_DS_BUR11_AVAILABLE 1 +#define FM4_DS_BUR12_AVAILABLE 1 +#define FM_DS_BUR12_AVAILABLE 1 +#define FM4_DS_BUR13_AVAILABLE 1 +#define FM_DS_BUR13_AVAILABLE 1 +#define FM4_DS_BUR14_AVAILABLE 1 +#define FM_DS_BUR14_AVAILABLE 1 +#define FM4_DS_BUR15_AVAILABLE 1 +#define FM_DS_BUR15_AVAILABLE 1 +#define FM4_DS_BUR16_AVAILABLE 1 +#define FM_DS_BUR16_AVAILABLE 1 +#define FM4_DS_DSRAMR_AVAILABLE 1 +#define FM_DS_DSRAMR_AVAILABLE 1 +#define FM4_DS_PMD_CTL_AVAILABLE 1 +#define FM_DS_PMD_CTL_AVAILABLE 1 +#define FM4_DS_RCK_CTL_AVAILABLE 1 +#define FM_DS_RCK_CTL_AVAILABLE 1 +#define FM4_DS_WIER_AVAILABLE 1 +#define FM_DS_WIER_AVAILABLE 1 +#define FM4_DS_WIFSR_AVAILABLE 1 +#define FM_DS_WIFSR_AVAILABLE 1 +#define FM4_DS_WILVR_AVAILABLE 1 +#define FM_DS_WILVR_AVAILABLE 1 +#define FM4_DS_WRFSR_AVAILABLE 1 +#define FM_DS_WRFSR_AVAILABLE 1 +/******************************************************************************* +* DSTC +*******************************************************************************/ +#define FM4_DSTC_CFG_AVAILABLE 1 +#define FM_DSTC_CFG_AVAILABLE 1 +#define FM4_DSTC_CMD_AVAILABLE 1 +#define FM_DSTC_CMD_AVAILABLE 1 +#define FM4_DSTC_DESTP_AVAILABLE 1 +#define FM_DSTC_DESTP_AVAILABLE 1 +#define FM4_DSTC_DQMSK0_AVAILABLE 1 +#define FM_DSTC_DQMSK0_AVAILABLE 1 +#define FM4_DSTC_DQMSK1_AVAILABLE 1 +#define FM_DSTC_DQMSK1_AVAILABLE 1 +#define FM4_DSTC_DQMSK2_AVAILABLE 1 +#define FM_DSTC_DQMSK2_AVAILABLE 1 +#define FM4_DSTC_DQMSK3_AVAILABLE 1 +#define FM_DSTC_DQMSK3_AVAILABLE 1 +#define FM4_DSTC_DQMSK4_AVAILABLE 1 +#define FM_DSTC_DQMSK4_AVAILABLE 1 +#define FM4_DSTC_DQMSK5_AVAILABLE 1 +#define FM_DSTC_DQMSK5_AVAILABLE 1 +#define FM4_DSTC_DQMSK6_AVAILABLE 1 +#define FM_DSTC_DQMSK6_AVAILABLE 1 +#define FM4_DSTC_DQMSK7_AVAILABLE 1 +#define FM_DSTC_DQMSK7_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR0_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR0_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR1_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR1_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR2_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR2_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR3_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR3_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR4_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR4_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR5_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR5_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR6_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR6_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR7_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR7_AVAILABLE 1 +#define FM4_DSTC_DREQENB0_AVAILABLE 1 +#define FM_DSTC_DREQENB0_AVAILABLE 1 +#define FM4_DSTC_DREQENB1_AVAILABLE 1 +#define FM_DSTC_DREQENB1_AVAILABLE 1 +#define FM4_DSTC_DREQENB2_AVAILABLE 1 +#define FM_DSTC_DREQENB2_AVAILABLE 1 +#define FM4_DSTC_DREQENB3_AVAILABLE 1 +#define FM_DSTC_DREQENB3_AVAILABLE 1 +#define FM4_DSTC_DREQENB4_AVAILABLE 1 +#define FM_DSTC_DREQENB4_AVAILABLE 1 +#define FM4_DSTC_DREQENB5_AVAILABLE 1 +#define FM_DSTC_DREQENB5_AVAILABLE 1 +#define FM4_DSTC_DREQENB6_AVAILABLE 1 +#define FM_DSTC_DREQENB6_AVAILABLE 1 +#define FM4_DSTC_DREQENB7_AVAILABLE 1 +#define FM_DSTC_DREQENB7_AVAILABLE 1 +#define FM4_DSTC_HWDESP_AVAILABLE 1 +#define FM_DSTC_HWDESP_AVAILABLE 1 +#define FM4_DSTC_HWINT0_AVAILABLE 1 +#define FM_DSTC_HWINT0_AVAILABLE 1 +#define FM4_DSTC_HWINT1_AVAILABLE 1 +#define FM_DSTC_HWINT1_AVAILABLE 1 +#define FM4_DSTC_HWINT2_AVAILABLE 1 +#define FM_DSTC_HWINT2_AVAILABLE 1 +#define FM4_DSTC_HWINT3_AVAILABLE 1 +#define FM_DSTC_HWINT3_AVAILABLE 1 +#define FM4_DSTC_HWINT4_AVAILABLE 1 +#define FM_DSTC_HWINT4_AVAILABLE 1 +#define FM4_DSTC_HWINT5_AVAILABLE 1 +#define FM_DSTC_HWINT5_AVAILABLE 1 +#define FM4_DSTC_HWINT6_AVAILABLE 1 +#define FM_DSTC_HWINT6_AVAILABLE 1 +#define FM4_DSTC_HWINT7_AVAILABLE 1 +#define FM_DSTC_HWINT7_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR0_AVAILABLE 1 +#define FM_DSTC_HWINTCLR0_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR1_AVAILABLE 1 +#define FM_DSTC_HWINTCLR1_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR2_AVAILABLE 1 +#define FM_DSTC_HWINTCLR2_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR3_AVAILABLE 1 +#define FM_DSTC_HWINTCLR3_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR4_AVAILABLE 1 +#define FM_DSTC_HWINTCLR4_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR5_AVAILABLE 1 +#define FM_DSTC_HWINTCLR5_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR6_AVAILABLE 1 +#define FM_DSTC_HWINTCLR6_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR7_AVAILABLE 1 +#define FM_DSTC_HWINTCLR7_AVAILABLE 1 +#define FM4_DSTC_MONERS_AVAILABLE 1 +#define FM_DSTC_MONERS_AVAILABLE 1 +#define FM4_DSTC_SWTR_AVAILABLE 1 +#define FM_DSTC_SWTR_AVAILABLE 1 +/******************************************************************************* +* DT +*******************************************************************************/ +#define FM4_DT_TIMER1BGLOAD_AVAILABLE 1 +#define FM_DT_TIMER1BGLOAD_AVAILABLE 1 +#define FM4_DT_TIMER1CONTROL_AVAILABLE 1 +#define FM_DT_TIMER1CONTROL_AVAILABLE 1 +#define FM4_DT_TIMER1INTCLR_AVAILABLE 1 +#define FM_DT_TIMER1INTCLR_AVAILABLE 1 +#define FM4_DT_TIMER1LOAD_AVAILABLE 1 +#define FM_DT_TIMER1LOAD_AVAILABLE 1 +#define FM4_DT_TIMER1MIS_AVAILABLE 1 +#define FM_DT_TIMER1MIS_AVAILABLE 1 +#define FM4_DT_TIMER1RIS_AVAILABLE 1 +#define FM_DT_TIMER1RIS_AVAILABLE 1 +#define FM4_DT_TIMER1VALUE_AVAILABLE 1 +#define FM_DT_TIMER1VALUE_AVAILABLE 1 +#define FM4_DT_TIMER2BGLOAD_AVAILABLE 1 +#define FM_DT_TIMER2BGLOAD_AVAILABLE 1 +#define FM4_DT_TIMER2CONTROL_AVAILABLE 1 +#define FM_DT_TIMER2CONTROL_AVAILABLE 1 +#define FM4_DT_TIMER2INTCLR_AVAILABLE 1 +#define FM_DT_TIMER2INTCLR_AVAILABLE 1 +#define FM4_DT_TIMER2LOAD_AVAILABLE 1 +#define FM_DT_TIMER2LOAD_AVAILABLE 1 +#define FM4_DT_TIMER2MIS_AVAILABLE 1 +#define FM_DT_TIMER2MIS_AVAILABLE 1 +#define FM4_DT_TIMER2RIS_AVAILABLE 1 +#define FM_DT_TIMER2RIS_AVAILABLE 1 +#define FM4_DT_TIMER2VALUE_AVAILABLE 1 +#define FM_DT_TIMER2VALUE_AVAILABLE 1 +/******************************************************************************* +* DUALFLASH_IF +*******************************************************************************/ +#define FM4_DUALFLASH_IF_DFASZR_AVAILABLE 1 +#define FM_DUALFLASH_IF_DFASZR_AVAILABLE 1 +#define FM4_DUALFLASH_IF_DFRWTR_AVAILABLE 1 +#define FM_DUALFLASH_IF_DFRWTR_AVAILABLE 1 +#define FM4_DUALFLASH_IF_DFSTR_AVAILABLE 1 +#define FM_DUALFLASH_IF_DFSTR_AVAILABLE 1 +/******************************************************************************* +* ECC_CAPTURE +*******************************************************************************/ +#define FM4_ECC_CAPTURE_FERRAD_AVAILABLE 1 +#define FM_ECC_CAPTURE_FERRAD_AVAILABLE 1 +/******************************************************************************* +* EXBUS +*******************************************************************************/ +#define FM4_EXBUS_AMODE_AVAILABLE 1 +#define FM_EXBUS_AMODE_AVAILABLE 1 +#define FM4_EXBUS_AREA0_AVAILABLE 1 +#define FM_EXBUS_AREA0_AVAILABLE 1 +#define FM4_EXBUS_AREA1_AVAILABLE 1 +#define FM_EXBUS_AREA1_AVAILABLE 1 +#define FM4_EXBUS_AREA2_AVAILABLE 1 +#define FM_EXBUS_AREA2_AVAILABLE 1 +#define FM4_EXBUS_AREA3_AVAILABLE 1 +#define FM_EXBUS_AREA3_AVAILABLE 1 +#define FM4_EXBUS_AREA4_AVAILABLE 1 +#define FM_EXBUS_AREA4_AVAILABLE 1 +#define FM4_EXBUS_AREA5_AVAILABLE 1 +#define FM_EXBUS_AREA5_AVAILABLE 1 +#define FM4_EXBUS_AREA6_AVAILABLE 1 +#define FM_EXBUS_AREA6_AVAILABLE 1 +#define FM4_EXBUS_AREA7_AVAILABLE 1 +#define FM_EXBUS_AREA7_AVAILABLE 1 +#define FM4_EXBUS_ATIM0_AVAILABLE 1 +#define FM_EXBUS_ATIM0_AVAILABLE 1 +#define FM4_EXBUS_ATIM1_AVAILABLE 1 +#define FM_EXBUS_ATIM1_AVAILABLE 1 +#define FM4_EXBUS_ATIM2_AVAILABLE 1 +#define FM_EXBUS_ATIM2_AVAILABLE 1 +#define FM4_EXBUS_ATIM3_AVAILABLE 1 +#define FM_EXBUS_ATIM3_AVAILABLE 1 +#define FM4_EXBUS_ATIM4_AVAILABLE 1 +#define FM_EXBUS_ATIM4_AVAILABLE 1 +#define FM4_EXBUS_ATIM5_AVAILABLE 1 +#define FM_EXBUS_ATIM5_AVAILABLE 1 +#define FM4_EXBUS_ATIM6_AVAILABLE 1 +#define FM_EXBUS_ATIM6_AVAILABLE 1 +#define FM4_EXBUS_ATIM7_AVAILABLE 1 +#define FM_EXBUS_ATIM7_AVAILABLE 1 +#define FM4_EXBUS_DCLKR_AVAILABLE 1 +#define FM_EXBUS_DCLKR_AVAILABLE 1 +#define FM4_EXBUS_ESCLR_AVAILABLE 1 +#define FM_EXBUS_ESCLR_AVAILABLE 1 +#define FM4_EXBUS_EST_AVAILABLE 1 +#define FM_EXBUS_EST_AVAILABLE 1 +#define FM4_EXBUS_MEMCERR_AVAILABLE 1 +#define FM_EXBUS_MEMCERR_AVAILABLE 1 +#define FM4_EXBUS_MODE0_AVAILABLE 1 +#define FM_EXBUS_MODE0_AVAILABLE 1 +#define FM4_EXBUS_MODE1_AVAILABLE 1 +#define FM_EXBUS_MODE1_AVAILABLE 1 +#define FM4_EXBUS_MODE2_AVAILABLE 1 +#define FM_EXBUS_MODE2_AVAILABLE 1 +#define FM4_EXBUS_MODE3_AVAILABLE 1 +#define FM_EXBUS_MODE3_AVAILABLE 1 +#define FM4_EXBUS_MODE4_AVAILABLE 1 +#define FM_EXBUS_MODE4_AVAILABLE 1 +#define FM4_EXBUS_MODE5_AVAILABLE 1 +#define FM_EXBUS_MODE5_AVAILABLE 1 +#define FM4_EXBUS_MODE6_AVAILABLE 1 +#define FM_EXBUS_MODE6_AVAILABLE 1 +#define FM4_EXBUS_MODE7_AVAILABLE 1 +#define FM_EXBUS_MODE7_AVAILABLE 1 +#define FM4_EXBUS_PWRDWN_AVAILABLE 1 +#define FM_EXBUS_PWRDWN_AVAILABLE 1 +#define FM4_EXBUS_REFTIM_AVAILABLE 1 +#define FM_EXBUS_REFTIM_AVAILABLE 1 +#define FM4_EXBUS_SDCMD_AVAILABLE 1 +#define FM_EXBUS_SDCMD_AVAILABLE 1 +#define FM4_EXBUS_SDMODE_AVAILABLE 1 +#define FM_EXBUS_SDMODE_AVAILABLE 1 +#define FM4_EXBUS_SDTIM_AVAILABLE 1 +#define FM_EXBUS_SDTIM_AVAILABLE 1 +#define FM4_EXBUS_TIM0_AVAILABLE 1 +#define FM_EXBUS_TIM0_AVAILABLE 1 +#define FM4_EXBUS_TIM1_AVAILABLE 1 +#define FM_EXBUS_TIM1_AVAILABLE 1 +#define FM4_EXBUS_TIM2_AVAILABLE 1 +#define FM_EXBUS_TIM2_AVAILABLE 1 +#define FM4_EXBUS_TIM3_AVAILABLE 1 +#define FM_EXBUS_TIM3_AVAILABLE 1 +#define FM4_EXBUS_TIM4_AVAILABLE 1 +#define FM_EXBUS_TIM4_AVAILABLE 1 +#define FM4_EXBUS_TIM5_AVAILABLE 1 +#define FM_EXBUS_TIM5_AVAILABLE 1 +#define FM4_EXBUS_TIM6_AVAILABLE 1 +#define FM_EXBUS_TIM6_AVAILABLE 1 +#define FM4_EXBUS_TIM7_AVAILABLE 1 +#define FM_EXBUS_TIM7_AVAILABLE 1 +#define FM4_EXBUS_WEAD_AVAILABLE 1 +#define FM_EXBUS_WEAD_AVAILABLE 1 +/******************************************************************************* +* EXTI +*******************************************************************************/ +#define FM4_EXTI_EICL_AVAILABLE 1 +#define FM_EXTI_EICL_AVAILABLE 1 +#define FM4_EXTI_EIRR_AVAILABLE 1 +#define FM_EXTI_EIRR_AVAILABLE 1 +#define FM4_EXTI_ELVR_AVAILABLE 1 +#define FM_EXTI_ELVR_AVAILABLE 1 +#define FM4_EXTI_ELVR1_AVAILABLE 1 +#define FM_EXTI_ELVR1_AVAILABLE 1 +#define FM4_EXTI_ENIR_AVAILABLE 1 +#define FM_EXTI_ENIR_AVAILABLE 1 +#define FM4_EXTI_NMICL_AVAILABLE 1 +#define FM_EXTI_NMICL_AVAILABLE 1 +#define FM4_EXTI_NMIRR_AVAILABLE 1 +#define FM_EXTI_NMIRR_AVAILABLE 1 +/******************************************************************************* +* FLASH_IF +*******************************************************************************/ +#define FM4_FLASH_IF_CRTRMM_AVAILABLE 1 +#define FM_FLASH_IF_CRTRMM_AVAILABLE 1 +#define FM4_FLASH_IF_DFCTRLR_AVAILABLE 1 +#define FM_FLASH_IF_DFCTRLR_AVAILABLE 1 +#define FM4_FLASH_IF_FASZR_AVAILABLE 1 +#define FM_FLASH_IF_FASZR_AVAILABLE 1 +#define FM4_FLASH_IF_FBFCR_AVAILABLE 1 +#define FM_FLASH_IF_FBFCR_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM1_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM1_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM2_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM2_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM3_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM3_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM4_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM4_AVAILABLE 1 +#define FM4_FLASH_IF_FICLR_AVAILABLE 1 +#define FM_FLASH_IF_FICLR_AVAILABLE 1 +#define FM4_FLASH_IF_FICR_AVAILABLE 1 +#define FM_FLASH_IF_FICR_AVAILABLE 1 +#define FM4_FLASH_IF_FISR_AVAILABLE 1 +#define FM_FLASH_IF_FISR_AVAILABLE 1 +#define FM4_FLASH_IF_FRWTR_AVAILABLE 1 +#define FM_FLASH_IF_FRWTR_AVAILABLE 1 +#define FM4_FLASH_IF_FSTR_AVAILABLE 1 +#define FM_FLASH_IF_FSTR_AVAILABLE 1 +#define FM4_FLASH_IF_FSYNDN_AVAILABLE 1 +#define FM_FLASH_IF_FSYNDN_AVAILABLE 1 +/******************************************************************************* +* GPIO +*******************************************************************************/ +#define FM4_GPIO_ADE_AVAILABLE 1 +#define FM_GPIO_ADE_AVAILABLE 1 +#define FM4_GPIO_DDR0_AVAILABLE 1 +#define FM_GPIO_DDR0_AVAILABLE 1 +#define FM4_GPIO_DDR1_AVAILABLE 1 +#define FM_GPIO_DDR1_AVAILABLE 1 +#define FM4_GPIO_DDR2_AVAILABLE 1 +#define FM_GPIO_DDR2_AVAILABLE 1 +#define FM4_GPIO_DDR3_AVAILABLE 1 +#define FM_GPIO_DDR3_AVAILABLE 1 +#define FM4_GPIO_DDR4_AVAILABLE 1 +#define FM_GPIO_DDR4_AVAILABLE 1 +#define FM4_GPIO_DDR5_AVAILABLE 1 +#define FM_GPIO_DDR5_AVAILABLE 1 +#define FM4_GPIO_DDR6_AVAILABLE 1 +#define FM_GPIO_DDR6_AVAILABLE 1 +#define FM4_GPIO_DDR7_AVAILABLE 1 +#define FM_GPIO_DDR7_AVAILABLE 1 +#define FM4_GPIO_DDR8_AVAILABLE 1 +#define FM_GPIO_DDR8_AVAILABLE 1 +#define FM4_GPIO_DDR9_AVAILABLE 1 +#define FM_GPIO_DDR9_AVAILABLE 1 +#define FM4_GPIO_DDRA_AVAILABLE 1 +#define FM_GPIO_DDRA_AVAILABLE 1 +#define FM4_GPIO_DDRB_AVAILABLE 1 +#define FM_GPIO_DDRB_AVAILABLE 1 +#define FM4_GPIO_DDRC_AVAILABLE 1 +#define FM_GPIO_DDRC_AVAILABLE 1 +#define FM4_GPIO_DDRD_AVAILABLE 1 +#define FM_GPIO_DDRD_AVAILABLE 1 +#define FM4_GPIO_DDRE_AVAILABLE 1 +#define FM_GPIO_DDRE_AVAILABLE 1 +#define FM4_GPIO_DDRF_AVAILABLE 1 +#define FM_GPIO_DDRF_AVAILABLE 1 +#define FM4_GPIO_EPFR00_AVAILABLE 1 +#define FM_GPIO_EPFR00_AVAILABLE 1 +#define FM4_GPIO_EPFR01_AVAILABLE 1 +#define FM_GPIO_EPFR01_AVAILABLE 1 +#define FM4_GPIO_EPFR02_AVAILABLE 1 +#define FM_GPIO_EPFR02_AVAILABLE 1 +#define FM4_GPIO_EPFR03_AVAILABLE 1 +#define FM_GPIO_EPFR03_AVAILABLE 1 +#define FM4_GPIO_EPFR04_AVAILABLE 1 +#define FM_GPIO_EPFR04_AVAILABLE 1 +#define FM4_GPIO_EPFR05_AVAILABLE 1 +#define FM_GPIO_EPFR05_AVAILABLE 1 +#define FM4_GPIO_EPFR06_AVAILABLE 1 +#define FM_GPIO_EPFR06_AVAILABLE 1 +#define FM4_GPIO_EPFR07_AVAILABLE 1 +#define FM_GPIO_EPFR07_AVAILABLE 1 +#define FM4_GPIO_EPFR08_AVAILABLE 1 +#define FM_GPIO_EPFR08_AVAILABLE 1 +#define FM4_GPIO_EPFR09_AVAILABLE 1 +#define FM_GPIO_EPFR09_AVAILABLE 1 +#define FM4_GPIO_EPFR10_AVAILABLE 1 +#define FM_GPIO_EPFR10_AVAILABLE 1 +#define FM4_GPIO_EPFR11_AVAILABLE 1 +#define FM_GPIO_EPFR11_AVAILABLE 1 +#define FM4_GPIO_EPFR12_AVAILABLE 1 +#define FM_GPIO_EPFR12_AVAILABLE 1 +#define FM4_GPIO_EPFR13_AVAILABLE 1 +#define FM_GPIO_EPFR13_AVAILABLE 1 +#define FM4_GPIO_EPFR14_AVAILABLE 1 +#define FM_GPIO_EPFR14_AVAILABLE 1 +#define FM4_GPIO_EPFR15_AVAILABLE 1 +#define FM_GPIO_EPFR15_AVAILABLE 1 +#define FM4_GPIO_EPFR16_AVAILABLE 1 +#define FM_GPIO_EPFR16_AVAILABLE 1 +#define FM4_GPIO_EPFR17_AVAILABLE 1 +#define FM_GPIO_EPFR17_AVAILABLE 1 +#define FM4_GPIO_EPFR18_AVAILABLE 1 +#define FM_GPIO_EPFR18_AVAILABLE 1 +#define FM4_GPIO_EPFR19_AVAILABLE 1 +#define FM_GPIO_EPFR19_AVAILABLE 1 +#define FM4_GPIO_EPFR20_AVAILABLE 1 +#define FM_GPIO_EPFR20_AVAILABLE 1 +#define FM4_GPIO_EPFR21_AVAILABLE 1 +#define FM_GPIO_EPFR21_AVAILABLE 1 +#define FM4_GPIO_EPFR22_AVAILABLE 1 +#define FM_GPIO_EPFR22_AVAILABLE 1 +#define FM4_GPIO_EPFR23_AVAILABLE 1 +#define FM_GPIO_EPFR23_AVAILABLE 1 +#define FM4_GPIO_EPFR24_AVAILABLE 1 +#define FM_GPIO_EPFR24_AVAILABLE 1 +#define FM4_GPIO_EPFR25_AVAILABLE 1 +#define FM_GPIO_EPFR25_AVAILABLE 1 +#define FM4_GPIO_EPFR26_AVAILABLE 1 +#define FM_GPIO_EPFR26_AVAILABLE 1 +#define FM4_GPIO_PCR0_AVAILABLE 1 +#define FM_GPIO_PCR0_AVAILABLE 1 +#define FM4_GPIO_PCR1_AVAILABLE 1 +#define FM_GPIO_PCR1_AVAILABLE 1 +#define FM4_GPIO_PCR2_AVAILABLE 1 +#define FM_GPIO_PCR2_AVAILABLE 1 +#define FM4_GPIO_PCR3_AVAILABLE 1 +#define FM_GPIO_PCR3_AVAILABLE 1 +#define FM4_GPIO_PCR4_AVAILABLE 1 +#define FM_GPIO_PCR4_AVAILABLE 1 +#define FM4_GPIO_PCR5_AVAILABLE 1 +#define FM_GPIO_PCR5_AVAILABLE 1 +#define FM4_GPIO_PCR6_AVAILABLE 1 +#define FM_GPIO_PCR6_AVAILABLE 1 +#define FM4_GPIO_PCR7_AVAILABLE 1 +#define FM_GPIO_PCR7_AVAILABLE 1 +#define FM4_GPIO_PCR9_AVAILABLE 1 +#define FM_GPIO_PCR9_AVAILABLE 1 +#define FM4_GPIO_PCRA_AVAILABLE 1 +#define FM_GPIO_PCRA_AVAILABLE 1 +#define FM4_GPIO_PCRB_AVAILABLE 1 +#define FM_GPIO_PCRB_AVAILABLE 1 +#define FM4_GPIO_PCRC_AVAILABLE 1 +#define FM_GPIO_PCRC_AVAILABLE 1 +#define FM4_GPIO_PCRD_AVAILABLE 1 +#define FM_GPIO_PCRD_AVAILABLE 1 +#define FM4_GPIO_PCRE_AVAILABLE 1 +#define FM_GPIO_PCRE_AVAILABLE 1 +#define FM4_GPIO_PCRF_AVAILABLE 1 +#define FM_GPIO_PCRF_AVAILABLE 1 +#define FM4_GPIO_PDIR0_AVAILABLE 1 +#define FM_GPIO_PDIR0_AVAILABLE 1 +#define FM4_GPIO_PDIR1_AVAILABLE 1 +#define FM_GPIO_PDIR1_AVAILABLE 1 +#define FM4_GPIO_PDIR2_AVAILABLE 1 +#define FM_GPIO_PDIR2_AVAILABLE 1 +#define FM4_GPIO_PDIR3_AVAILABLE 1 +#define FM_GPIO_PDIR3_AVAILABLE 1 +#define FM4_GPIO_PDIR4_AVAILABLE 1 +#define FM_GPIO_PDIR4_AVAILABLE 1 +#define FM4_GPIO_PDIR5_AVAILABLE 1 +#define FM_GPIO_PDIR5_AVAILABLE 1 +#define FM4_GPIO_PDIR6_AVAILABLE 1 +#define FM_GPIO_PDIR6_AVAILABLE 1 +#define FM4_GPIO_PDIR7_AVAILABLE 1 +#define FM_GPIO_PDIR7_AVAILABLE 1 +#define FM4_GPIO_PDIR8_AVAILABLE 1 +#define FM_GPIO_PDIR8_AVAILABLE 1 +#define FM4_GPIO_PDIR9_AVAILABLE 1 +#define FM_GPIO_PDIR9_AVAILABLE 1 +#define FM4_GPIO_PDIRA_AVAILABLE 1 +#define FM_GPIO_PDIRA_AVAILABLE 1 +#define FM4_GPIO_PDIRB_AVAILABLE 1 +#define FM_GPIO_PDIRB_AVAILABLE 1 +#define FM4_GPIO_PDIRC_AVAILABLE 1 +#define FM_GPIO_PDIRC_AVAILABLE 1 +#define FM4_GPIO_PDIRD_AVAILABLE 1 +#define FM_GPIO_PDIRD_AVAILABLE 1 +#define FM4_GPIO_PDIRE_AVAILABLE 1 +#define FM_GPIO_PDIRE_AVAILABLE 1 +#define FM4_GPIO_PDIRF_AVAILABLE 1 +#define FM_GPIO_PDIRF_AVAILABLE 1 +#define FM4_GPIO_PDOR0_AVAILABLE 1 +#define FM_GPIO_PDOR0_AVAILABLE 1 +#define FM4_GPIO_PDOR1_AVAILABLE 1 +#define FM_GPIO_PDOR1_AVAILABLE 1 +#define FM4_GPIO_PDOR2_AVAILABLE 1 +#define FM_GPIO_PDOR2_AVAILABLE 1 +#define FM4_GPIO_PDOR3_AVAILABLE 1 +#define FM_GPIO_PDOR3_AVAILABLE 1 +#define FM4_GPIO_PDOR4_AVAILABLE 1 +#define FM_GPIO_PDOR4_AVAILABLE 1 +#define FM4_GPIO_PDOR5_AVAILABLE 1 +#define FM_GPIO_PDOR5_AVAILABLE 1 +#define FM4_GPIO_PDOR6_AVAILABLE 1 +#define FM_GPIO_PDOR6_AVAILABLE 1 +#define FM4_GPIO_PDOR7_AVAILABLE 1 +#define FM_GPIO_PDOR7_AVAILABLE 1 +#define FM4_GPIO_PDOR8_AVAILABLE 1 +#define FM_GPIO_PDOR8_AVAILABLE 1 +#define FM4_GPIO_PDOR9_AVAILABLE 1 +#define FM_GPIO_PDOR9_AVAILABLE 1 +#define FM4_GPIO_PDORA_AVAILABLE 1 +#define FM_GPIO_PDORA_AVAILABLE 1 +#define FM4_GPIO_PDORB_AVAILABLE 1 +#define FM_GPIO_PDORB_AVAILABLE 1 +#define FM4_GPIO_PDORC_AVAILABLE 1 +#define FM_GPIO_PDORC_AVAILABLE 1 +#define FM4_GPIO_PDORD_AVAILABLE 1 +#define FM_GPIO_PDORD_AVAILABLE 1 +#define FM4_GPIO_PDORE_AVAILABLE 1 +#define FM_GPIO_PDORE_AVAILABLE 1 +#define FM4_GPIO_PDORF_AVAILABLE 1 +#define FM_GPIO_PDORF_AVAILABLE 1 +#define FM4_GPIO_PDSR0_AVAILABLE 1 +#define FM_GPIO_PDSR0_AVAILABLE 1 +#define FM4_GPIO_PDSR1_AVAILABLE 1 +#define FM_GPIO_PDSR1_AVAILABLE 1 +#define FM4_GPIO_PDSR2_AVAILABLE 1 +#define FM_GPIO_PDSR2_AVAILABLE 1 +#define FM4_GPIO_PDSR3_AVAILABLE 1 +#define FM_GPIO_PDSR3_AVAILABLE 1 +#define FM4_GPIO_PDSR4_AVAILABLE 1 +#define FM_GPIO_PDSR4_AVAILABLE 1 +#define FM4_GPIO_PDSR5_AVAILABLE 1 +#define FM_GPIO_PDSR5_AVAILABLE 1 +#define FM4_GPIO_PDSR6_AVAILABLE 1 +#define FM_GPIO_PDSR6_AVAILABLE 1 +#define FM4_GPIO_PDSR7_AVAILABLE 1 +#define FM_GPIO_PDSR7_AVAILABLE 1 +#define FM4_GPIO_PDSR8_AVAILABLE 1 +#define FM_GPIO_PDSR8_AVAILABLE 1 +#define FM4_GPIO_PDSR9_AVAILABLE 1 +#define FM_GPIO_PDSR9_AVAILABLE 1 +#define FM4_GPIO_PDSRA_AVAILABLE 1 +#define FM_GPIO_PDSRA_AVAILABLE 1 +#define FM4_GPIO_PDSRB_AVAILABLE 1 +#define FM_GPIO_PDSRB_AVAILABLE 1 +#define FM4_GPIO_PDSRC_AVAILABLE 1 +#define FM_GPIO_PDSRC_AVAILABLE 1 +#define FM4_GPIO_PDSRD_AVAILABLE 1 +#define FM_GPIO_PDSRD_AVAILABLE 1 +#define FM4_GPIO_PDSRE_AVAILABLE 1 +#define FM_GPIO_PDSRE_AVAILABLE 1 +#define FM4_GPIO_PDSRF_AVAILABLE 1 +#define FM_GPIO_PDSRF_AVAILABLE 1 +#define FM4_GPIO_PFR0_AVAILABLE 1 +#define FM_GPIO_PFR0_AVAILABLE 1 +#define FM4_GPIO_PFR1_AVAILABLE 1 +#define FM_GPIO_PFR1_AVAILABLE 1 +#define FM4_GPIO_PFR2_AVAILABLE 1 +#define FM_GPIO_PFR2_AVAILABLE 1 +#define FM4_GPIO_PFR3_AVAILABLE 1 +#define FM_GPIO_PFR3_AVAILABLE 1 +#define FM4_GPIO_PFR4_AVAILABLE 1 +#define FM_GPIO_PFR4_AVAILABLE 1 +#define FM4_GPIO_PFR5_AVAILABLE 1 +#define FM_GPIO_PFR5_AVAILABLE 1 +#define FM4_GPIO_PFR6_AVAILABLE 1 +#define FM_GPIO_PFR6_AVAILABLE 1 +#define FM4_GPIO_PFR7_AVAILABLE 1 +#define FM_GPIO_PFR7_AVAILABLE 1 +#define FM4_GPIO_PFR8_AVAILABLE 1 +#define FM_GPIO_PFR8_AVAILABLE 1 +#define FM4_GPIO_PFR9_AVAILABLE 1 +#define FM_GPIO_PFR9_AVAILABLE 1 +#define FM4_GPIO_PFRA_AVAILABLE 1 +#define FM_GPIO_PFRA_AVAILABLE 1 +#define FM4_GPIO_PFRB_AVAILABLE 1 +#define FM_GPIO_PFRB_AVAILABLE 1 +#define FM4_GPIO_PFRC_AVAILABLE 1 +#define FM_GPIO_PFRC_AVAILABLE 1 +#define FM4_GPIO_PFRD_AVAILABLE 1 +#define FM_GPIO_PFRD_AVAILABLE 1 +#define FM4_GPIO_PFRE_AVAILABLE 1 +#define FM_GPIO_PFRE_AVAILABLE 1 +#define FM4_GPIO_PFRF_AVAILABLE 1 +#define FM_GPIO_PFRF_AVAILABLE 1 +#define FM4_GPIO_PZR0_AVAILABLE 1 +#define FM_GPIO_PZR0_AVAILABLE 1 +#define FM4_GPIO_PZR1_AVAILABLE 1 +#define FM_GPIO_PZR1_AVAILABLE 1 +#define FM4_GPIO_PZR2_AVAILABLE 1 +#define FM_GPIO_PZR2_AVAILABLE 1 +#define FM4_GPIO_PZR3_AVAILABLE 1 +#define FM_GPIO_PZR3_AVAILABLE 1 +#define FM4_GPIO_PZR4_AVAILABLE 1 +#define FM_GPIO_PZR4_AVAILABLE 1 +#define FM4_GPIO_PZR5_AVAILABLE 1 +#define FM_GPIO_PZR5_AVAILABLE 1 +#define FM4_GPIO_PZR6_AVAILABLE 1 +#define FM_GPIO_PZR6_AVAILABLE 1 +#define FM4_GPIO_PZR7_AVAILABLE 1 +#define FM_GPIO_PZR7_AVAILABLE 1 +#define FM4_GPIO_PZR8_AVAILABLE 1 +#define FM_GPIO_PZR8_AVAILABLE 1 +#define FM4_GPIO_PZR9_AVAILABLE 1 +#define FM_GPIO_PZR9_AVAILABLE 1 +#define FM4_GPIO_PZRA_AVAILABLE 1 +#define FM_GPIO_PZRA_AVAILABLE 1 +#define FM4_GPIO_PZRB_AVAILABLE 1 +#define FM_GPIO_PZRB_AVAILABLE 1 +#define FM4_GPIO_PZRC_AVAILABLE 1 +#define FM_GPIO_PZRC_AVAILABLE 1 +#define FM4_GPIO_PZRD_AVAILABLE 1 +#define FM_GPIO_PZRD_AVAILABLE 1 +#define FM4_GPIO_PZRE_AVAILABLE 1 +#define FM_GPIO_PZRE_AVAILABLE 1 +#define FM4_GPIO_PZRF_AVAILABLE 1 +#define FM_GPIO_PZRF_AVAILABLE 1 +#define FM4_GPIO_SPSR_AVAILABLE 1 +#define FM_GPIO_SPSR_AVAILABLE 1 +/******************************************************************************* +* HSSPI +*******************************************************************************/ +#define FM4_HSSPI_CSAEXT_AVAILABLE 1 +#define FM_HSSPI_CSAEXT_AVAILABLE 1 +#define FM4_HSSPI_CSCFG_AVAILABLE 1 +#define FM_HSSPI_CSCFG_AVAILABLE 1 +#define FM4_HSSPI_CSITIME_AVAILABLE 1 +#define FM_HSSPI_CSITIME_AVAILABLE 1 +#define FM4_HSSPI_DBCNT_AVAILABLE 1 +#define FM_HSSPI_DBCNT_AVAILABLE 1 +#define FM4_HSSPI_DMBCC_AVAILABLE 1 +#define FM_HSSPI_DMBCC_AVAILABLE 1 +#define FM4_HSSPI_DMBCS_AVAILABLE 1 +#define FM_HSSPI_DMBCS_AVAILABLE 1 +#define FM4_HSSPI_DMCFG_AVAILABLE 1 +#define FM_HSSPI_DMCFG_AVAILABLE 1 +#define FM4_HSSPI_DMDMAEN_AVAILABLE 1 +#define FM_HSSPI_DMDMAEN_AVAILABLE 1 +#define FM4_HSSPI_DMPSEL_AVAILABLE 1 +#define FM_HSSPI_DMPSEL_AVAILABLE 1 +#define FM4_HSSPI_DMSTART_AVAILABLE 1 +#define FM_HSSPI_DMSTART_AVAILABLE 1 +#define FM4_HSSPI_DMSTATUS_AVAILABLE 1 +#define FM_HSSPI_DMSTATUS_AVAILABLE 1 +#define FM4_HSSPI_DMSTOP_AVAILABLE 1 +#define FM_HSSPI_DMSTOP_AVAILABLE 1 +#define FM4_HSSPI_DMTRP_AVAILABLE 1 +#define FM_HSSPI_DMTRP_AVAILABLE 1 +#define FM4_HSSPI_FAULTC_AVAILABLE 1 +#define FM_HSSPI_FAULTC_AVAILABLE 1 +#define FM4_HSSPI_FAULTF_AVAILABLE 1 +#define FM_HSSPI_FAULTF_AVAILABLE 1 +#define FM4_HSSPI_FIFOCFG_AVAILABLE 1 +#define FM_HSSPI_FIFOCFG_AVAILABLE 1 +#define FM4_HSSPI_MCTRL_AVAILABLE 1 +#define FM_HSSPI_MCTRL_AVAILABLE 1 +#define FM4_HSSPI_MID_AVAILABLE 1 +#define FM_HSSPI_MID_AVAILABLE 1 +#define FM4_HSSPI_PCC0_AVAILABLE 1 +#define FM_HSSPI_PCC0_AVAILABLE 1 +#define FM4_HSSPI_PCC1_AVAILABLE 1 +#define FM_HSSPI_PCC1_AVAILABLE 1 +#define FM4_HSSPI_PCC2_AVAILABLE 1 +#define FM_HSSPI_PCC2_AVAILABLE 1 +#define FM4_HSSPI_PCC3_AVAILABLE 1 +#define FM_HSSPI_PCC3_AVAILABLE 1 +#define FM4_HSSPI_QDCLKR_AVAILABLE 1 +#define FM_HSSPI_QDCLKR_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC0_AVAILABLE 1 +#define FM_HSSPI_RDCSDC0_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC1_AVAILABLE 1 +#define FM_HSSPI_RDCSDC1_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC2_AVAILABLE 1 +#define FM_HSSPI_RDCSDC2_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC3_AVAILABLE 1 +#define FM_HSSPI_RDCSDC3_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC4_AVAILABLE 1 +#define FM_HSSPI_RDCSDC4_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC5_AVAILABLE 1 +#define FM_HSSPI_RDCSDC5_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC6_AVAILABLE 1 +#define FM_HSSPI_RDCSDC6_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC7_AVAILABLE 1 +#define FM_HSSPI_RDCSDC7_AVAILABLE 1 +#define FM4_HSSPI_RXC_AVAILABLE 1 +#define FM_HSSPI_RXC_AVAILABLE 1 +#define FM4_HSSPI_RXE_AVAILABLE 1 +#define FM_HSSPI_RXE_AVAILABLE 1 +#define FM4_HSSPI_RXF_AVAILABLE 1 +#define FM_HSSPI_RXF_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO0_AVAILABLE 1 +#define FM_HSSPI_RXFIFO0_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO1_AVAILABLE 1 +#define FM_HSSPI_RXFIFO1_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO10_AVAILABLE 1 +#define FM_HSSPI_RXFIFO10_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO11_AVAILABLE 1 +#define FM_HSSPI_RXFIFO11_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO12_AVAILABLE 1 +#define FM_HSSPI_RXFIFO12_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO13_AVAILABLE 1 +#define FM_HSSPI_RXFIFO13_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO14_AVAILABLE 1 +#define FM_HSSPI_RXFIFO14_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO15_AVAILABLE 1 +#define FM_HSSPI_RXFIFO15_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO2_AVAILABLE 1 +#define FM_HSSPI_RXFIFO2_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO3_AVAILABLE 1 +#define FM_HSSPI_RXFIFO3_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO4_AVAILABLE 1 +#define FM_HSSPI_RXFIFO4_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO5_AVAILABLE 1 +#define FM_HSSPI_RXFIFO5_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO6_AVAILABLE 1 +#define FM_HSSPI_RXFIFO6_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO7_AVAILABLE 1 +#define FM_HSSPI_RXFIFO7_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO8_AVAILABLE 1 +#define FM_HSSPI_RXFIFO8_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO9_AVAILABLE 1 +#define FM_HSSPI_RXFIFO9_AVAILABLE 1 +#define FM4_HSSPI_TXC_AVAILABLE 1 +#define FM_HSSPI_TXC_AVAILABLE 1 +#define FM4_HSSPI_TXE_AVAILABLE 1 +#define FM_HSSPI_TXE_AVAILABLE 1 +#define FM4_HSSPI_TXF_AVAILABLE 1 +#define FM_HSSPI_TXF_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO0_AVAILABLE 1 +#define FM_HSSPI_TXFIFO0_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO1_AVAILABLE 1 +#define FM_HSSPI_TXFIFO1_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO10_AVAILABLE 1 +#define FM_HSSPI_TXFIFO10_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO11_AVAILABLE 1 +#define FM_HSSPI_TXFIFO11_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO12_AVAILABLE 1 +#define FM_HSSPI_TXFIFO12_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO13_AVAILABLE 1 +#define FM_HSSPI_TXFIFO13_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO14_AVAILABLE 1 +#define FM_HSSPI_TXFIFO14_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO15_AVAILABLE 1 +#define FM_HSSPI_TXFIFO15_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO2_AVAILABLE 1 +#define FM_HSSPI_TXFIFO2_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO3_AVAILABLE 1 +#define FM_HSSPI_TXFIFO3_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO4_AVAILABLE 1 +#define FM_HSSPI_TXFIFO4_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO5_AVAILABLE 1 +#define FM_HSSPI_TXFIFO5_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO6_AVAILABLE 1 +#define FM_HSSPI_TXFIFO6_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO7_AVAILABLE 1 +#define FM_HSSPI_TXFIFO7_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO8_AVAILABLE 1 +#define FM_HSSPI_TXFIFO8_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO9_AVAILABLE 1 +#define FM_HSSPI_TXFIFO9_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC0_AVAILABLE 1 +#define FM_HSSPI_WRCSDC0_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC1_AVAILABLE 1 +#define FM_HSSPI_WRCSDC1_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC2_AVAILABLE 1 +#define FM_HSSPI_WRCSDC2_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC3_AVAILABLE 1 +#define FM_HSSPI_WRCSDC3_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC4_AVAILABLE 1 +#define FM_HSSPI_WRCSDC4_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC5_AVAILABLE 1 +#define FM_HSSPI_WRCSDC5_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC6_AVAILABLE 1 +#define FM_HSSPI_WRCSDC6_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC7_AVAILABLE 1 +#define FM_HSSPI_WRCSDC7_AVAILABLE 1 +/******************************************************************************* +* HWWDT +*******************************************************************************/ +#define FM4_HWWDT_WDG_CTL_AVAILABLE 1 +#define FM_HWWDT_WDG_CTL_AVAILABLE 1 +#define FM4_HWWDT_WDG_ICL_AVAILABLE 1 +#define FM_HWWDT_WDG_ICL_AVAILABLE 1 +#define FM4_HWWDT_WDG_LCK_AVAILABLE 1 +#define FM_HWWDT_WDG_LCK_AVAILABLE 1 +#define FM4_HWWDT_WDG_LDR_AVAILABLE 1 +#define FM_HWWDT_WDG_LDR_AVAILABLE 1 +#define FM4_HWWDT_WDG_RIS_AVAILABLE 1 +#define FM_HWWDT_WDG_RIS_AVAILABLE 1 +#define FM4_HWWDT_WDG_VLR_AVAILABLE 1 +#define FM_HWWDT_WDG_VLR_AVAILABLE 1 +/******************************************************************************* +* I2S0 +*******************************************************************************/ +#define FM4_I2S_CNTREG_AVAILABLE 1 +#define FM_I2S_CNTREG_AVAILABLE 1 +#define FM4_I2S_DMAACT_AVAILABLE 1 +#define FM_I2S_DMAACT_AVAILABLE 1 +#define FM4_I2S_INTCNT_AVAILABLE 1 +#define FM_I2S_INTCNT_AVAILABLE 1 +#define FM4_I2S_MCR0REG_AVAILABLE 1 +#define FM_I2S_MCR0REG_AVAILABLE 1 +#define FM4_I2S_MCR1REG_AVAILABLE 1 +#define FM_I2S_MCR1REG_AVAILABLE 1 +#define FM4_I2S_MCR2REG_AVAILABLE 1 +#define FM_I2S_MCR2REG_AVAILABLE 1 +#define FM4_I2S_OPRREG_AVAILABLE 1 +#define FM_I2S_OPRREG_AVAILABLE 1 +#define FM4_I2S_RXFDAT_AVAILABLE 1 +#define FM_I2S_RXFDAT_AVAILABLE 1 +#define FM4_I2S_SRST_AVAILABLE 1 +#define FM_I2S_SRST_AVAILABLE 1 +#define FM4_I2S_STATUS_AVAILABLE 1 +#define FM_I2S_STATUS_AVAILABLE 1 +#define FM4_I2S_TSTREG_AVAILABLE 1 +#define FM_I2S_TSTREG_AVAILABLE 1 +#define FM4_I2S_TXFDAT_AVAILABLE 1 +#define FM_I2S_TXFDAT_AVAILABLE 1 +/******************************************************************************* +* I2SPRE +*******************************************************************************/ +#define FM4_I2SPRE_ICCR_AVAILABLE 1 +#define FM_I2SPRE_ICCR_AVAILABLE 1 +#define FM4_I2SPRE_IP_STR_AVAILABLE 1 +#define FM_I2SPRE_IP_STR_AVAILABLE 1 +#define FM4_I2SPRE_IPCR1_AVAILABLE 1 +#define FM_I2SPRE_IPCR1_AVAILABLE 1 +#define FM4_I2SPRE_IPCR2_AVAILABLE 1 +#define FM_I2SPRE_IPCR2_AVAILABLE 1 +#define FM4_I2SPRE_IPCR3_AVAILABLE 1 +#define FM_I2SPRE_IPCR3_AVAILABLE 1 +#define FM4_I2SPRE_IPCR4_AVAILABLE 1 +#define FM_I2SPRE_IPCR4_AVAILABLE 1 +#define FM4_I2SPRE_IPCR5_AVAILABLE 1 +#define FM_I2SPRE_IPCR5_AVAILABLE 1 +#define FM4_I2SPRE_IPINT_CLR_AVAILABLE 1 +#define FM_I2SPRE_IPINT_CLR_AVAILABLE 1 +#define FM4_I2SPRE_IPINT_ENR_AVAILABLE 1 +#define FM_I2SPRE_IPINT_ENR_AVAILABLE 1 +#define FM4_I2SPRE_IPINT_STR_AVAILABLE 1 +#define FM_I2SPRE_IPINT_STR_AVAILABLE 1 +/******************************************************************************* +* INTREQ +*******************************************************************************/ +#define FM4_INTREQ_DRQSEL_AVAILABLE 1 +#define FM_INTREQ_DRQSEL_AVAILABLE 1 +#define FM4_INTREQ_EXC02MON_AVAILABLE 1 +#define FM_INTREQ_EXC02MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ000MON_AVAILABLE 1 +#define FM_INTREQ_IRQ000MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ001MON_AVAILABLE 1 +#define FM_INTREQ_IRQ001MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ002MON_AVAILABLE 1 +#define FM_INTREQ_IRQ002MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ003MON_AVAILABLE 1 +#define FM_INTREQ_IRQ003MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ003SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ003SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ004MON_AVAILABLE 1 +#define FM_INTREQ_IRQ004MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ004SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ004SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ005MON_AVAILABLE 1 +#define FM_INTREQ_IRQ005MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ005SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ005SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ006MON_AVAILABLE 1 +#define FM_INTREQ_IRQ006MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ006SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ006SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ007MON_AVAILABLE 1 +#define FM_INTREQ_IRQ007MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ007SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ007SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ008MON_AVAILABLE 1 +#define FM_INTREQ_IRQ008MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ008SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ008SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ009MON_AVAILABLE 1 +#define FM_INTREQ_IRQ009MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ009SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ009SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ010MON_AVAILABLE 1 +#define FM_INTREQ_IRQ010MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ010SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ010SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ011MON_AVAILABLE 1 +#define FM_INTREQ_IRQ011MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ012MON_AVAILABLE 1 +#define FM_INTREQ_IRQ012MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ013MON_AVAILABLE 1 +#define FM_INTREQ_IRQ013MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ014MON_AVAILABLE 1 +#define FM_INTREQ_IRQ014MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ015MON_AVAILABLE 1 +#define FM_INTREQ_IRQ015MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ016MON_AVAILABLE 1 +#define FM_INTREQ_IRQ016MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ017MON_AVAILABLE 1 +#define FM_INTREQ_IRQ017MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ018MON_AVAILABLE 1 +#define FM_INTREQ_IRQ018MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ019MON_AVAILABLE 1 +#define FM_INTREQ_IRQ019MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ020MON_AVAILABLE 1 +#define FM_INTREQ_IRQ020MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ021MON_AVAILABLE 1 +#define FM_INTREQ_IRQ021MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ022MON_AVAILABLE 1 +#define FM_INTREQ_IRQ022MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ023MON_AVAILABLE 1 +#define FM_INTREQ_IRQ023MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ024MON_AVAILABLE 1 +#define FM_INTREQ_IRQ024MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ025MON_AVAILABLE 1 +#define FM_INTREQ_IRQ025MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ026MON_AVAILABLE 1 +#define FM_INTREQ_IRQ026MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ027MON_AVAILABLE 1 +#define FM_INTREQ_IRQ027MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ028MON_AVAILABLE 1 +#define FM_INTREQ_IRQ028MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ029MON_AVAILABLE 1 +#define FM_INTREQ_IRQ029MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ030MON_AVAILABLE 1 +#define FM_INTREQ_IRQ030MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ031MON_AVAILABLE 1 +#define FM_INTREQ_IRQ031MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ032MON_AVAILABLE 1 +#define FM_INTREQ_IRQ032MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ033MON_AVAILABLE 1 +#define FM_INTREQ_IRQ033MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ034MON_AVAILABLE 1 +#define FM_INTREQ_IRQ034MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ035MON_AVAILABLE 1 +#define FM_INTREQ_IRQ035MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ036MON_AVAILABLE 1 +#define FM_INTREQ_IRQ036MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ037MON_AVAILABLE 1 +#define FM_INTREQ_IRQ037MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ038MON_AVAILABLE 1 +#define FM_INTREQ_IRQ038MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ039MON_AVAILABLE 1 +#define FM_INTREQ_IRQ039MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ040MON_AVAILABLE 1 +#define FM_INTREQ_IRQ040MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ041MON_AVAILABLE 1 +#define FM_INTREQ_IRQ041MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ042MON_AVAILABLE 1 +#define FM_INTREQ_IRQ042MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ043MON_AVAILABLE 1 +#define FM_INTREQ_IRQ043MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ044MON_AVAILABLE 1 +#define FM_INTREQ_IRQ044MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ045MON_AVAILABLE 1 +#define FM_INTREQ_IRQ045MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ046MON_AVAILABLE 1 +#define FM_INTREQ_IRQ046MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ047MON_AVAILABLE 1 +#define FM_INTREQ_IRQ047MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ048MON_AVAILABLE 1 +#define FM_INTREQ_IRQ048MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ049MON_AVAILABLE 1 +#define FM_INTREQ_IRQ049MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ050MON_AVAILABLE 1 +#define FM_INTREQ_IRQ050MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ051MON_AVAILABLE 1 +#define FM_INTREQ_IRQ051MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ052MON_AVAILABLE 1 +#define FM_INTREQ_IRQ052MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ053MON_AVAILABLE 1 +#define FM_INTREQ_IRQ053MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ054MON_AVAILABLE 1 +#define FM_INTREQ_IRQ054MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ055MON_AVAILABLE 1 +#define FM_INTREQ_IRQ055MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ056MON_AVAILABLE 1 +#define FM_INTREQ_IRQ056MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ057MON_AVAILABLE 1 +#define FM_INTREQ_IRQ057MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ058MON_AVAILABLE 1 +#define FM_INTREQ_IRQ058MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ059MON_AVAILABLE 1 +#define FM_INTREQ_IRQ059MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ060MON_AVAILABLE 1 +#define FM_INTREQ_IRQ060MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ061MON_AVAILABLE 1 +#define FM_INTREQ_IRQ061MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ062MON_AVAILABLE 1 +#define FM_INTREQ_IRQ062MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ063MON_AVAILABLE 1 +#define FM_INTREQ_IRQ063MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ064MON_AVAILABLE 1 +#define FM_INTREQ_IRQ064MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ065MON_AVAILABLE 1 +#define FM_INTREQ_IRQ065MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ066MON_AVAILABLE 1 +#define FM_INTREQ_IRQ066MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ067MON_AVAILABLE 1 +#define FM_INTREQ_IRQ067MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ068MON_AVAILABLE 1 +#define FM_INTREQ_IRQ068MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ069MON_AVAILABLE 1 +#define FM_INTREQ_IRQ069MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ070MON_AVAILABLE 1 +#define FM_INTREQ_IRQ070MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ071MON_AVAILABLE 1 +#define FM_INTREQ_IRQ071MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ072MON_AVAILABLE 1 +#define FM_INTREQ_IRQ072MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ073MON_AVAILABLE 1 +#define FM_INTREQ_IRQ073MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ074MON_AVAILABLE 1 +#define FM_INTREQ_IRQ074MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ075MON_AVAILABLE 1 +#define FM_INTREQ_IRQ075MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ076MON_AVAILABLE 1 +#define FM_INTREQ_IRQ076MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ077MON_AVAILABLE 1 +#define FM_INTREQ_IRQ077MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ078MON_AVAILABLE 1 +#define FM_INTREQ_IRQ078MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ079MON_AVAILABLE 1 +#define FM_INTREQ_IRQ079MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ080MON_AVAILABLE 1 +#define FM_INTREQ_IRQ080MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ081MON_AVAILABLE 1 +#define FM_INTREQ_IRQ081MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ082MON_AVAILABLE 1 +#define FM_INTREQ_IRQ082MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ083MON_AVAILABLE 1 +#define FM_INTREQ_IRQ083MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ084MON_AVAILABLE 1 +#define FM_INTREQ_IRQ084MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ085MON_AVAILABLE 1 +#define FM_INTREQ_IRQ085MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ086MON_AVAILABLE 1 +#define FM_INTREQ_IRQ086MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ087MON_AVAILABLE 1 +#define FM_INTREQ_IRQ087MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ088MON_AVAILABLE 1 +#define FM_INTREQ_IRQ088MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ089MON_AVAILABLE 1 +#define FM_INTREQ_IRQ089MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ090MON_AVAILABLE 1 +#define FM_INTREQ_IRQ090MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ091MON_AVAILABLE 1 +#define FM_INTREQ_IRQ091MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ092MON_AVAILABLE 1 +#define FM_INTREQ_IRQ092MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ093MON_AVAILABLE 1 +#define FM_INTREQ_IRQ093MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ094MON_AVAILABLE 1 +#define FM_INTREQ_IRQ094MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ095MON_AVAILABLE 1 +#define FM_INTREQ_IRQ095MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ096MON_AVAILABLE 1 +#define FM_INTREQ_IRQ096MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ097MON_AVAILABLE 1 +#define FM_INTREQ_IRQ097MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ098MON_AVAILABLE 1 +#define FM_INTREQ_IRQ098MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ099MON_AVAILABLE 1 +#define FM_INTREQ_IRQ099MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ100MON_AVAILABLE 1 +#define FM_INTREQ_IRQ100MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ101MON_AVAILABLE 1 +#define FM_INTREQ_IRQ101MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ102MON_AVAILABLE 1 +#define FM_INTREQ_IRQ102MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ103MON_AVAILABLE 1 +#define FM_INTREQ_IRQ103MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ104MON_AVAILABLE 1 +#define FM_INTREQ_IRQ104MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ105MON_AVAILABLE 1 +#define FM_INTREQ_IRQ105MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ106MON_AVAILABLE 1 +#define FM_INTREQ_IRQ106MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ107MON_AVAILABLE 1 +#define FM_INTREQ_IRQ107MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ108MON_AVAILABLE 1 +#define FM_INTREQ_IRQ108MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ109MON_AVAILABLE 1 +#define FM_INTREQ_IRQ109MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ110MON_AVAILABLE 1 +#define FM_INTREQ_IRQ110MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ111MON_AVAILABLE 1 +#define FM_INTREQ_IRQ111MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ112MON_AVAILABLE 1 +#define FM_INTREQ_IRQ112MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ113MON_AVAILABLE 1 +#define FM_INTREQ_IRQ113MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ114MON_AVAILABLE 1 +#define FM_INTREQ_IRQ114MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ115MON_AVAILABLE 1 +#define FM_INTREQ_IRQ115MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ116MON_AVAILABLE 1 +#define FM_INTREQ_IRQ116MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ117MON_AVAILABLE 1 +#define FM_INTREQ_IRQ117MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ118MON_AVAILABLE 1 +#define FM_INTREQ_IRQ118MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ119MON_AVAILABLE 1 +#define FM_INTREQ_IRQ119MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ120MON_AVAILABLE 1 +#define FM_INTREQ_IRQ120MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ121MON_AVAILABLE 1 +#define FM_INTREQ_IRQ121MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ122MON_AVAILABLE 1 +#define FM_INTREQ_IRQ122MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ123MON_AVAILABLE 1 +#define FM_INTREQ_IRQ123MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ124MON_AVAILABLE 1 +#define FM_INTREQ_IRQ124MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ125MON_AVAILABLE 1 +#define FM_INTREQ_IRQ125MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ126MON_AVAILABLE 1 +#define FM_INTREQ_IRQ126MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ127MON_AVAILABLE 1 +#define FM_INTREQ_IRQ127MON_AVAILABLE 1 +#define FM4_INTREQ_ODDPKS_AVAILABLE 1 +#define FM_INTREQ_ODDPKS_AVAILABLE 1 +#define FM4_INTREQ_ODDPKS1_AVAILABLE 1 +#define FM_INTREQ_ODDPKS1_AVAILABLE 1 +/******************************************************************************* +* LSCRP +*******************************************************************************/ +#define FM4_LSCRP_LCR_PRSLD_AVAILABLE 1 +#define FM_LSCRP_LCR_PRSLD_AVAILABLE 1 +/******************************************************************************* +* LVD +*******************************************************************************/ +#define FM4_LVD_LVD_CLR_AVAILABLE 1 +#define FM_LVD_LVD_CLR_AVAILABLE 1 +#define FM4_LVD_LVD_CTL_AVAILABLE 1 +#define FM_LVD_LVD_CTL_AVAILABLE 1 +#define FM4_LVD_LVD_RLR_AVAILABLE 1 +#define FM_LVD_LVD_RLR_AVAILABLE 1 +#define FM4_LVD_LVD_STR_AVAILABLE 1 +#define FM_LVD_LVD_STR_AVAILABLE 1 +#define FM4_LVD_LVD_STR2_AVAILABLE 1 +#define FM_LVD_LVD_STR2_AVAILABLE 1 +/******************************************************************************* +* MFS0 +*******************************************************************************/ +#define FM4_MFS_CSIO_BGR_AVAILABLE 1 +#define FM_MFS_CSIO_BGR_AVAILABLE 1 +#define FM4_MFS_CSIO_ESCR_AVAILABLE 1 +#define FM_MFS_CSIO_ESCR_AVAILABLE 1 +#define FM4_MFS_CSIO_FBYTE1_AVAILABLE 1 +#define FM_MFS_CSIO_FBYTE1_AVAILABLE 1 +#define FM4_MFS_CSIO_FBYTE2_AVAILABLE 1 +#define FM_MFS_CSIO_FBYTE2_AVAILABLE 1 +#define FM4_MFS_CSIO_FCR_AVAILABLE 1 +#define FM_MFS_CSIO_FCR_AVAILABLE 1 +#define FM4_MFS_CSIO_RDR_AVAILABLE 1 +#define FM_MFS_CSIO_RDR_AVAILABLE 1 +#define FM4_MFS_CSIO_SACSR_AVAILABLE 1 +#define FM_MFS_CSIO_SACSR_AVAILABLE 1 +#define FM4_MFS_CSIO_SCR_AVAILABLE 1 +#define FM_MFS_CSIO_SCR_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSCR_AVAILABLE 1 +#define FM_MFS_CSIO_SCSCR_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSFR0_AVAILABLE 1 +#define FM_MFS_CSIO_SCSFR0_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSFR1_AVAILABLE 1 +#define FM_MFS_CSIO_SCSFR1_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSFR2_AVAILABLE 1 +#define FM_MFS_CSIO_SCSFR2_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSTR0_AVAILABLE 1 +#define FM_MFS_CSIO_SCSTR0_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSTR1_AVAILABLE 1 +#define FM_MFS_CSIO_SCSTR1_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSTR32_AVAILABLE 1 +#define FM_MFS_CSIO_SCSTR32_AVAILABLE 1 +#define FM4_MFS_CSIO_SMR_AVAILABLE 1 +#define FM_MFS_CSIO_SMR_AVAILABLE 1 +#define FM4_MFS_CSIO_SSR_AVAILABLE 1 +#define FM_MFS_CSIO_SSR_AVAILABLE 1 +#define FM4_MFS_CSIO_STMCR_AVAILABLE 1 +#define FM_MFS_CSIO_STMCR_AVAILABLE 1 +#define FM4_MFS_CSIO_STMR_AVAILABLE 1 +#define FM_MFS_CSIO_STMR_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE0_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE0_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE1_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE1_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE2_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE2_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE3_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE3_AVAILABLE 1 +#define FM4_MFS_CSIO_TDR_AVAILABLE 1 +#define FM_MFS_CSIO_TDR_AVAILABLE 1 +#define FM4_MFS_I2C_BGR_AVAILABLE 1 +#define FM_MFS_I2C_BGR_AVAILABLE 1 +#define FM4_MFS_I2C_EIBCR_AVAILABLE 1 +#define FM_MFS_I2C_EIBCR_AVAILABLE 1 +#define FM4_MFS_I2C_FBYTE1_AVAILABLE 1 +#define FM_MFS_I2C_FBYTE1_AVAILABLE 1 +#define FM4_MFS_I2C_FBYTE2_AVAILABLE 1 +#define FM_MFS_I2C_FBYTE2_AVAILABLE 1 +#define FM4_MFS_I2C_FCR_AVAILABLE 1 +#define FM_MFS_I2C_FCR_AVAILABLE 1 +#define FM4_MFS_I2C_IBCR_AVAILABLE 1 +#define FM_MFS_I2C_IBCR_AVAILABLE 1 +#define FM4_MFS_I2C_IBSR_AVAILABLE 1 +#define FM_MFS_I2C_IBSR_AVAILABLE 1 +#define FM4_MFS_I2C_ISBA_AVAILABLE 1 +#define FM_MFS_I2C_ISBA_AVAILABLE 1 +#define FM4_MFS_I2C_ISMK_AVAILABLE 1 +#define FM_MFS_I2C_ISMK_AVAILABLE 1 +#define FM4_MFS_I2C_NFCR_AVAILABLE 1 +#define FM_MFS_I2C_NFCR_AVAILABLE 1 +#define FM4_MFS_I2C_RDR_AVAILABLE 1 +#define FM_MFS_I2C_RDR_AVAILABLE 1 +#define FM4_MFS_I2C_SMR_AVAILABLE 1 +#define FM_MFS_I2C_SMR_AVAILABLE 1 +#define FM4_MFS_I2C_SSR_AVAILABLE 1 +#define FM_MFS_I2C_SSR_AVAILABLE 1 +#define FM4_MFS_I2C_TDR_AVAILABLE 1 +#define FM_MFS_I2C_TDR_AVAILABLE 1 +#define FM4_MFS_LIN_BGR_AVAILABLE 1 +#define FM_MFS_LIN_BGR_AVAILABLE 1 +#define FM4_MFS_LIN_ESCR_AVAILABLE 1 +#define FM_MFS_LIN_ESCR_AVAILABLE 1 +#define FM4_MFS_LIN_FBYTE1_AVAILABLE 1 +#define FM_MFS_LIN_FBYTE1_AVAILABLE 1 +#define FM4_MFS_LIN_FBYTE2_AVAILABLE 1 +#define FM_MFS_LIN_FBYTE2_AVAILABLE 1 +#define FM4_MFS_LIN_FCR_AVAILABLE 1 +#define FM_MFS_LIN_FCR_AVAILABLE 1 +#define FM4_MFS_LIN_RDR_AVAILABLE 1 +#define FM_MFS_LIN_RDR_AVAILABLE 1 +#define FM4_MFS_LIN_SCR_AVAILABLE 1 +#define FM_MFS_LIN_SCR_AVAILABLE 1 +#define FM4_MFS_LIN_SMR_AVAILABLE 1 +#define FM_MFS_LIN_SMR_AVAILABLE 1 +#define FM4_MFS_LIN_SSR_AVAILABLE 1 +#define FM_MFS_LIN_SSR_AVAILABLE 1 +#define FM4_MFS_LIN_TDR_AVAILABLE 1 +#define FM_MFS_LIN_TDR_AVAILABLE 1 +#define FM4_MFS_UART_BGR_AVAILABLE 1 +#define FM_MFS_UART_BGR_AVAILABLE 1 +#define FM4_MFS_UART_ESCR_AVAILABLE 1 +#define FM_MFS_UART_ESCR_AVAILABLE 1 +#define FM4_MFS_UART_FBYTE1_AVAILABLE 1 +#define FM_MFS_UART_FBYTE1_AVAILABLE 1 +#define FM4_MFS_UART_FBYTE2_AVAILABLE 1 +#define FM_MFS_UART_FBYTE2_AVAILABLE 1 +#define FM4_MFS_UART_FCR_AVAILABLE 1 +#define FM_MFS_UART_FCR_AVAILABLE 1 +#define FM4_MFS_UART_RDR_AVAILABLE 1 +#define FM_MFS_UART_RDR_AVAILABLE 1 +#define FM4_MFS_UART_SCR_AVAILABLE 1 +#define FM_MFS_UART_SCR_AVAILABLE 1 +#define FM4_MFS_UART_SMR_AVAILABLE 1 +#define FM_MFS_UART_SMR_AVAILABLE 1 +#define FM4_MFS_UART_SSR_AVAILABLE 1 +#define FM_MFS_UART_SSR_AVAILABLE 1 +#define FM4_MFS_UART_TDR_AVAILABLE 1 +#define FM_MFS_UART_TDR_AVAILABLE 1 +/******************************************************************************* +* MFT0 +*******************************************************************************/ +#define FM4_MFT_ADCMP_ACFS10_AVAILABLE 1 +#define FM_MFT_ADCMP_ACFS10_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACFS32_AVAILABLE 1 +#define FM_MFT_ADCMP_ACFS32_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACFS54_AVAILABLE 1 +#define FM_MFT_ADCMP_ACFS54_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC5_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP5_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSA_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSA_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC5_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD5_AVAILABLE 1 +#define FM4_MFT_FRT_TCAL_AVAILABLE 1 +#define FM_MFT_FRT_TCAL_AVAILABLE 1 +#define FM4_MFT_FRT_TCCP0_AVAILABLE 1 +#define FM_MFT_FRT_TCCP0_AVAILABLE 1 +#define FM4_MFT_FRT_TCCP1_AVAILABLE 1 +#define FM_MFT_FRT_TCCP1_AVAILABLE 1 +#define FM4_MFT_FRT_TCCP2_AVAILABLE 1 +#define FM_MFT_FRT_TCCP2_AVAILABLE 1 +#define FM4_MFT_FRT_TCDT0_AVAILABLE 1 +#define FM_MFT_FRT_TCDT0_AVAILABLE 1 +#define FM4_MFT_FRT_TCDT1_AVAILABLE 1 +#define FM_MFT_FRT_TCDT1_AVAILABLE 1 +#define FM4_MFT_FRT_TCDT2_AVAILABLE 1 +#define FM_MFT_FRT_TCDT2_AVAILABLE 1 +#define FM4_MFT_FRT_TCSA0_AVAILABLE 1 +#define FM_MFT_FRT_TCSA0_AVAILABLE 1 +#define FM4_MFT_FRT_TCSA1_AVAILABLE 1 +#define FM_MFT_FRT_TCSA1_AVAILABLE 1 +#define FM4_MFT_FRT_TCSA2_AVAILABLE 1 +#define FM_MFT_FRT_TCSA2_AVAILABLE 1 +#define FM4_MFT_FRT_TCSC0_AVAILABLE 1 +#define FM_MFT_FRT_TCSC0_AVAILABLE 1 +#define FM4_MFT_FRT_TCSC1_AVAILABLE 1 +#define FM_MFT_FRT_TCSC1_AVAILABLE 1 +#define FM4_MFT_FRT_TCSC2_AVAILABLE 1 +#define FM_MFT_FRT_TCSC2_AVAILABLE 1 +#define FM4_MFT_FRT_TCSD_AVAILABLE 1 +#define FM_MFT_FRT_TCSD_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP0_AVAILABLE 1 +#define FM_MFT_ICU_ICCP0_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP1_AVAILABLE 1 +#define FM_MFT_ICU_ICCP1_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP2_AVAILABLE 1 +#define FM_MFT_ICU_ICCP2_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP3_AVAILABLE 1 +#define FM_MFT_ICU_ICCP3_AVAILABLE 1 +#define FM4_MFT_ICU_ICFS10_AVAILABLE 1 +#define FM_MFT_ICU_ICFS10_AVAILABLE 1 +#define FM4_MFT_ICU_ICFS32_AVAILABLE 1 +#define FM_MFT_ICU_ICFS32_AVAILABLE 1 +#define FM4_MFT_ICU_ICSA10_AVAILABLE 1 +#define FM_MFT_ICU_ICSA10_AVAILABLE 1 +#define FM4_MFT_ICU_ICSA32_AVAILABLE 1 +#define FM_MFT_ICU_ICSA32_AVAILABLE 1 +#define FM4_MFT_ICU_ICSB10_AVAILABLE 1 +#define FM_MFT_ICU_ICSB10_AVAILABLE 1 +#define FM4_MFT_ICU_ICSB32_AVAILABLE 1 +#define FM_MFT_ICU_ICSB32_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP0_AVAILABLE 1 +#define FM_MFT_OCU_OCCP0_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP1_AVAILABLE 1 +#define FM_MFT_OCU_OCCP1_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP2_AVAILABLE 1 +#define FM_MFT_OCU_OCCP2_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP3_AVAILABLE 1 +#define FM_MFT_OCU_OCCP3_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP4_AVAILABLE 1 +#define FM_MFT_OCU_OCCP4_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP5_AVAILABLE 1 +#define FM_MFT_OCU_OCCP5_AVAILABLE 1 +#define FM4_MFT_OCU_OCFS10_AVAILABLE 1 +#define FM_MFT_OCU_OCFS10_AVAILABLE 1 +#define FM4_MFT_OCU_OCFS32_AVAILABLE 1 +#define FM_MFT_OCU_OCFS32_AVAILABLE 1 +#define FM4_MFT_OCU_OCFS54_AVAILABLE 1 +#define FM_MFT_OCU_OCFS54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSA10_AVAILABLE 1 +#define FM_MFT_OCU_OCSA10_AVAILABLE 1 +#define FM4_MFT_OCU_OCSA32_AVAILABLE 1 +#define FM_MFT_OCU_OCSA32_AVAILABLE 1 +#define FM4_MFT_OCU_OCSA54_AVAILABLE 1 +#define FM_MFT_OCU_OCSA54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSB10_AVAILABLE 1 +#define FM_MFT_OCU_OCSB10_AVAILABLE 1 +#define FM4_MFT_OCU_OCSB32_AVAILABLE 1 +#define FM_MFT_OCU_OCSB32_AVAILABLE 1 +#define FM4_MFT_OCU_OCSB54_AVAILABLE 1 +#define FM_MFT_OCU_OCSB54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSC_AVAILABLE 1 +#define FM_MFT_OCU_OCSC_AVAILABLE 1 +#define FM4_MFT_OCU_OCSD10_AVAILABLE 1 +#define FM_MFT_OCU_OCSD10_AVAILABLE 1 +#define FM4_MFT_OCU_OCSD32_AVAILABLE 1 +#define FM_MFT_OCU_OCSD32_AVAILABLE 1 +#define FM4_MFT_OCU_OCSD54_AVAILABLE 1 +#define FM_MFT_OCU_OCSD54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE0_AVAILABLE 1 +#define FM_MFT_OCU_OCSE0_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE1_AVAILABLE 1 +#define FM_MFT_OCU_OCSE1_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE2_AVAILABLE 1 +#define FM_MFT_OCU_OCSE2_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE3_AVAILABLE 1 +#define FM_MFT_OCU_OCSE3_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE4_AVAILABLE 1 +#define FM_MFT_OCU_OCSE4_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE5_AVAILABLE 1 +#define FM_MFT_OCU_OCSE5_AVAILABLE 1 +#define FM4_MFT_WFG_NZCL_AVAILABLE 1 +#define FM_MFT_WFG_NZCL_AVAILABLE 1 +#define FM4_MFT_WFG_WFIR_AVAILABLE 1 +#define FM_MFT_WFG_WFIR_AVAILABLE 1 +#define FM4_MFT_WFG_WFSA10_AVAILABLE 1 +#define FM_MFT_WFG_WFSA10_AVAILABLE 1 +#define FM4_MFT_WFG_WFSA32_AVAILABLE 1 +#define FM_MFT_WFG_WFSA32_AVAILABLE 1 +#define FM4_MFT_WFG_WFSA54_AVAILABLE 1 +#define FM_MFT_WFG_WFSA54_AVAILABLE 1 +#define FM4_MFT_WFG_WFTA10_AVAILABLE 1 +#define FM_MFT_WFG_WFTA10_AVAILABLE 1 +#define FM4_MFT_WFG_WFTA32_AVAILABLE 1 +#define FM_MFT_WFG_WFTA32_AVAILABLE 1 +#define FM4_MFT_WFG_WFTA54_AVAILABLE 1 +#define FM_MFT_WFG_WFTA54_AVAILABLE 1 +#define FM4_MFT_WFG_WFTB10_AVAILABLE 1 +#define FM_MFT_WFG_WFTB10_AVAILABLE 1 +#define FM4_MFT_WFG_WFTB32_AVAILABLE 1 +#define FM_MFT_WFG_WFTB32_AVAILABLE 1 +#define FM4_MFT_WFG_WFTB54_AVAILABLE 1 +#define FM_MFT_WFG_WFTB54_AVAILABLE 1 +#define FM4_MFT_WFG_WFTF10_AVAILABLE 1 +#define FM_MFT_WFG_WFTF10_AVAILABLE 1 +#define FM4_MFT_WFG_WFTF32_AVAILABLE 1 +#define FM_MFT_WFG_WFTF32_AVAILABLE 1 +#define FM4_MFT_WFG_WFTF54_AVAILABLE 1 +#define FM_MFT_WFG_WFTF54_AVAILABLE 1 +/******************************************************************************* +* MFT_PPG +*******************************************************************************/ +#define FM4_MFT_PPG_COMP0_AVAILABLE 1 +#define FM_MFT_PPG_COMP0_AVAILABLE 1 +#define FM4_MFT_PPG_COMP1_AVAILABLE 1 +#define FM_MFT_PPG_COMP1_AVAILABLE 1 +#define FM4_MFT_PPG_COMP10_AVAILABLE 1 +#define FM_MFT_PPG_COMP10_AVAILABLE 1 +#define FM4_MFT_PPG_COMP12_AVAILABLE 1 +#define FM_MFT_PPG_COMP12_AVAILABLE 1 +#define FM4_MFT_PPG_COMP14_AVAILABLE 1 +#define FM_MFT_PPG_COMP14_AVAILABLE 1 +#define FM4_MFT_PPG_COMP2_AVAILABLE 1 +#define FM_MFT_PPG_COMP2_AVAILABLE 1 +#define FM4_MFT_PPG_COMP3_AVAILABLE 1 +#define FM_MFT_PPG_COMP3_AVAILABLE 1 +#define FM4_MFT_PPG_COMP4_AVAILABLE 1 +#define FM_MFT_PPG_COMP4_AVAILABLE 1 +#define FM4_MFT_PPG_COMP5_AVAILABLE 1 +#define FM_MFT_PPG_COMP5_AVAILABLE 1 +#define FM4_MFT_PPG_COMP6_AVAILABLE 1 +#define FM_MFT_PPG_COMP6_AVAILABLE 1 +#define FM4_MFT_PPG_COMP7_AVAILABLE 1 +#define FM_MFT_PPG_COMP7_AVAILABLE 1 +#define FM4_MFT_PPG_COMP8_AVAILABLE 1 +#define FM_MFT_PPG_COMP8_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC0_AVAILABLE 1 +#define FM_MFT_PPG_GATEC0_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC12_AVAILABLE 1 +#define FM_MFT_PPG_GATEC12_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC16_AVAILABLE 1 +#define FM_MFT_PPG_GATEC16_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC20_AVAILABLE 1 +#define FM_MFT_PPG_GATEC20_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC4_AVAILABLE 1 +#define FM_MFT_PPG_GATEC4_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC8_AVAILABLE 1 +#define FM_MFT_PPG_GATEC8_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC0_AVAILABLE 1 +#define FM_MFT_PPG_PPGC0_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC1_AVAILABLE 1 +#define FM_MFT_PPG_PPGC1_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC10_AVAILABLE 1 +#define FM_MFT_PPG_PPGC10_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC11_AVAILABLE 1 +#define FM_MFT_PPG_PPGC11_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC12_AVAILABLE 1 +#define FM_MFT_PPG_PPGC12_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC13_AVAILABLE 1 +#define FM_MFT_PPG_PPGC13_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC14_AVAILABLE 1 +#define FM_MFT_PPG_PPGC14_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC15_AVAILABLE 1 +#define FM_MFT_PPG_PPGC15_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC16_AVAILABLE 1 +#define FM_MFT_PPG_PPGC16_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC17_AVAILABLE 1 +#define FM_MFT_PPG_PPGC17_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC18_AVAILABLE 1 +#define FM_MFT_PPG_PPGC18_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC19_AVAILABLE 1 +#define FM_MFT_PPG_PPGC19_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC2_AVAILABLE 1 +#define FM_MFT_PPG_PPGC2_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC20_AVAILABLE 1 +#define FM_MFT_PPG_PPGC20_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC21_AVAILABLE 1 +#define FM_MFT_PPG_PPGC21_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC22_AVAILABLE 1 +#define FM_MFT_PPG_PPGC22_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC23_AVAILABLE 1 +#define FM_MFT_PPG_PPGC23_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC3_AVAILABLE 1 +#define FM_MFT_PPG_PPGC3_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC4_AVAILABLE 1 +#define FM_MFT_PPG_PPGC4_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC5_AVAILABLE 1 +#define FM_MFT_PPG_PPGC5_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC6_AVAILABLE 1 +#define FM_MFT_PPG_PPGC6_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC7_AVAILABLE 1 +#define FM_MFT_PPG_PPGC7_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC8_AVAILABLE 1 +#define FM_MFT_PPG_PPGC8_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC9_AVAILABLE 1 +#define FM_MFT_PPG_PPGC9_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH0_AVAILABLE 1 +#define FM_MFT_PPG_PRLH0_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH1_AVAILABLE 1 +#define FM_MFT_PPG_PRLH1_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH10_AVAILABLE 1 +#define FM_MFT_PPG_PRLH10_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH11_AVAILABLE 1 +#define FM_MFT_PPG_PRLH11_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH12_AVAILABLE 1 +#define FM_MFT_PPG_PRLH12_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH13_AVAILABLE 1 +#define FM_MFT_PPG_PRLH13_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH14_AVAILABLE 1 +#define FM_MFT_PPG_PRLH14_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH15_AVAILABLE 1 +#define FM_MFT_PPG_PRLH15_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH16_AVAILABLE 1 +#define FM_MFT_PPG_PRLH16_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH17_AVAILABLE 1 +#define FM_MFT_PPG_PRLH17_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH18_AVAILABLE 1 +#define FM_MFT_PPG_PRLH18_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH19_AVAILABLE 1 +#define FM_MFT_PPG_PRLH19_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH2_AVAILABLE 1 +#define FM_MFT_PPG_PRLH2_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH20_AVAILABLE 1 +#define FM_MFT_PPG_PRLH20_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH21_AVAILABLE 1 +#define FM_MFT_PPG_PRLH21_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH22_AVAILABLE 1 +#define FM_MFT_PPG_PRLH22_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH23_AVAILABLE 1 +#define FM_MFT_PPG_PRLH23_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH3_AVAILABLE 1 +#define FM_MFT_PPG_PRLH3_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH4_AVAILABLE 1 +#define FM_MFT_PPG_PRLH4_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH5_AVAILABLE 1 +#define FM_MFT_PPG_PRLH5_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH6_AVAILABLE 1 +#define FM_MFT_PPG_PRLH6_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH7_AVAILABLE 1 +#define FM_MFT_PPG_PRLH7_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH8_AVAILABLE 1 +#define FM_MFT_PPG_PRLH8_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH9_AVAILABLE 1 +#define FM_MFT_PPG_PRLH9_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL0_AVAILABLE 1 +#define FM_MFT_PPG_PRLL0_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL1_AVAILABLE 1 +#define FM_MFT_PPG_PRLL1_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL10_AVAILABLE 1 +#define FM_MFT_PPG_PRLL10_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL11_AVAILABLE 1 +#define FM_MFT_PPG_PRLL11_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL12_AVAILABLE 1 +#define FM_MFT_PPG_PRLL12_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL13_AVAILABLE 1 +#define FM_MFT_PPG_PRLL13_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL14_AVAILABLE 1 +#define FM_MFT_PPG_PRLL14_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL15_AVAILABLE 1 +#define FM_MFT_PPG_PRLL15_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL16_AVAILABLE 1 +#define FM_MFT_PPG_PRLL16_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL17_AVAILABLE 1 +#define FM_MFT_PPG_PRLL17_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL18_AVAILABLE 1 +#define FM_MFT_PPG_PRLL18_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL19_AVAILABLE 1 +#define FM_MFT_PPG_PRLL19_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL2_AVAILABLE 1 +#define FM_MFT_PPG_PRLL2_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL20_AVAILABLE 1 +#define FM_MFT_PPG_PRLL20_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL21_AVAILABLE 1 +#define FM_MFT_PPG_PRLL21_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL22_AVAILABLE 1 +#define FM_MFT_PPG_PRLL22_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL23_AVAILABLE 1 +#define FM_MFT_PPG_PRLL23_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL3_AVAILABLE 1 +#define FM_MFT_PPG_PRLL3_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL4_AVAILABLE 1 +#define FM_MFT_PPG_PRLL4_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL5_AVAILABLE 1 +#define FM_MFT_PPG_PRLL5_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL6_AVAILABLE 1 +#define FM_MFT_PPG_PRLL6_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL7_AVAILABLE 1 +#define FM_MFT_PPG_PRLL7_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL8_AVAILABLE 1 +#define FM_MFT_PPG_PRLL8_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL9_AVAILABLE 1 +#define FM_MFT_PPG_PRLL9_AVAILABLE 1 +#define FM4_MFT_PPG_REVC0_AVAILABLE 1 +#define FM_MFT_PPG_REVC0_AVAILABLE 1 +#define FM4_MFT_PPG_REVC1_AVAILABLE 1 +#define FM_MFT_PPG_REVC1_AVAILABLE 1 +#define FM4_MFT_PPG_TRG0_AVAILABLE 1 +#define FM_MFT_PPG_TRG0_AVAILABLE 1 +#define FM4_MFT_PPG_TRG1_AVAILABLE 1 +#define FM_MFT_PPG_TRG1_AVAILABLE 1 +#define FM4_MFT_PPG_TTCR0_AVAILABLE 1 +#define FM_MFT_PPG_TTCR0_AVAILABLE 1 +#define FM4_MFT_PPG_TTCR1_AVAILABLE 1 +#define FM_MFT_PPG_TTCR1_AVAILABLE 1 +#define FM4_MFT_PPG_TTCR2_AVAILABLE 1 +#define FM_MFT_PPG_TTCR2_AVAILABLE 1 +/******************************************************************************* +* PCRC +*******************************************************************************/ +#define FM4_PCRC_PCRC_CFG_AVAILABLE 1 +#define FM_PCRC_PCRC_CFG_AVAILABLE 1 +#define FM4_PCRC_PCRC_FXOR_AVAILABLE 1 +#define FM_PCRC_PCRC_FXOR_AVAILABLE 1 +#define FM4_PCRC_PCRC_POLY_AVAILABLE 1 +#define FM_PCRC_PCRC_POLY_AVAILABLE 1 +#define FM4_PCRC_PCRC_RD_AVAILABLE 1 +#define FM_PCRC_PCRC_RD_AVAILABLE 1 +#define FM4_PCRC_PCRC_SEED_AVAILABLE 1 +#define FM_PCRC_PCRC_SEED_AVAILABLE 1 +#define FM4_PCRC_PCRC_WR_AVAILABLE 1 +#define FM_PCRC_PCRC_WR_AVAILABLE 1 +/******************************************************************************* +* QPRC0 +*******************************************************************************/ +#define FM4_QPRC_QCR_AVAILABLE 1 +#define FM_QPRC_QCR_AVAILABLE 1 +#define FM4_QPRC_QECR_AVAILABLE 1 +#define FM_QPRC_QECR_AVAILABLE 1 +#define FM4_QPRC_QICRH_AVAILABLE 1 +#define FM_QPRC_QICRH_AVAILABLE 1 +#define FM4_QPRC_QICRL_AVAILABLE 1 +#define FM_QPRC_QICRL_AVAILABLE 1 +#define FM4_QPRC_QMPR_AVAILABLE 1 +#define FM_QPRC_QMPR_AVAILABLE 1 +#define FM4_QPRC_QPCCR_AVAILABLE 1 +#define FM_QPRC_QPCCR_AVAILABLE 1 +#define FM4_QPRC_QPCR_AVAILABLE 1 +#define FM_QPRC_QPCR_AVAILABLE 1 +#define FM4_QPRC_QPRCR_AVAILABLE 1 +#define FM_QPRC_QPRCR_AVAILABLE 1 +#define FM4_QPRC_QPRCRR_AVAILABLE 1 +#define FM_QPRC_QPRCRR_AVAILABLE 1 +#define FM4_QPRC_QRCR_AVAILABLE 1 +#define FM_QPRC_QRCR_AVAILABLE 1 +/******************************************************************************* +* QPRC0_NF +*******************************************************************************/ +#define FM4_QPRC_NF_NFCTLA_AVAILABLE 1 +#define FM_QPRC_NF_NFCTLA_AVAILABLE 1 +#define FM4_QPRC_NF_NFCTLB_AVAILABLE 1 +#define FM_QPRC_NF_NFCTLB_AVAILABLE 1 +#define FM4_QPRC_NF_NFCTLZ_AVAILABLE 1 +#define FM_QPRC_NF_NFCTLZ_AVAILABLE 1 +/******************************************************************************* +* RTC +*******************************************************************************/ +#define FM4_RTC_ALDR_AVAILABLE 1 +#define FM_RTC_ALDR_AVAILABLE 1 +#define FM4_RTC_ALHR_AVAILABLE 1 +#define FM_RTC_ALHR_AVAILABLE 1 +#define FM4_RTC_ALMIR_AVAILABLE 1 +#define FM_RTC_ALMIR_AVAILABLE 1 +#define FM4_RTC_ALMOR_AVAILABLE 1 +#define FM_RTC_ALMOR_AVAILABLE 1 +#define FM4_RTC_ALYR_AVAILABLE 1 +#define FM_RTC_ALYR_AVAILABLE 1 +#define FM4_RTC_BOOST_AVAILABLE 1 +#define FM_RTC_BOOST_AVAILABLE 1 +#define FM4_RTC_BREG00_AVAILABLE 1 +#define FM_RTC_BREG00_AVAILABLE 1 +#define FM4_RTC_BREG01_AVAILABLE 1 +#define FM_RTC_BREG01_AVAILABLE 1 +#define FM4_RTC_BREG02_AVAILABLE 1 +#define FM_RTC_BREG02_AVAILABLE 1 +#define FM4_RTC_BREG03_AVAILABLE 1 +#define FM_RTC_BREG03_AVAILABLE 1 +#define FM4_RTC_BREG04_AVAILABLE 1 +#define FM_RTC_BREG04_AVAILABLE 1 +#define FM4_RTC_BREG05_AVAILABLE 1 +#define FM_RTC_BREG05_AVAILABLE 1 +#define FM4_RTC_BREG06_AVAILABLE 1 +#define FM_RTC_BREG06_AVAILABLE 1 +#define FM4_RTC_BREG07_AVAILABLE 1 +#define FM_RTC_BREG07_AVAILABLE 1 +#define FM4_RTC_BREG08_AVAILABLE 1 +#define FM_RTC_BREG08_AVAILABLE 1 +#define FM4_RTC_BREG09_AVAILABLE 1 +#define FM_RTC_BREG09_AVAILABLE 1 +#define FM4_RTC_BREG0A_AVAILABLE 1 +#define FM_RTC_BREG0A_AVAILABLE 1 +#define FM4_RTC_BREG0B_AVAILABLE 1 +#define FM_RTC_BREG0B_AVAILABLE 1 +#define FM4_RTC_BREG0C_AVAILABLE 1 +#define FM_RTC_BREG0C_AVAILABLE 1 +#define FM4_RTC_BREG0D_AVAILABLE 1 +#define FM_RTC_BREG0D_AVAILABLE 1 +#define FM4_RTC_BREG0E_AVAILABLE 1 +#define FM_RTC_BREG0E_AVAILABLE 1 +#define FM4_RTC_BREG0F_AVAILABLE 1 +#define FM_RTC_BREG0F_AVAILABLE 1 +#define FM4_RTC_BREG10_AVAILABLE 1 +#define FM_RTC_BREG10_AVAILABLE 1 +#define FM4_RTC_BREG11_AVAILABLE 1 +#define FM_RTC_BREG11_AVAILABLE 1 +#define FM4_RTC_BREG12_AVAILABLE 1 +#define FM_RTC_BREG12_AVAILABLE 1 +#define FM4_RTC_BREG13_AVAILABLE 1 +#define FM_RTC_BREG13_AVAILABLE 1 +#define FM4_RTC_BREG14_AVAILABLE 1 +#define FM_RTC_BREG14_AVAILABLE 1 +#define FM4_RTC_BREG15_AVAILABLE 1 +#define FM_RTC_BREG15_AVAILABLE 1 +#define FM4_RTC_BREG16_AVAILABLE 1 +#define FM_RTC_BREG16_AVAILABLE 1 +#define FM4_RTC_BREG17_AVAILABLE 1 +#define FM_RTC_BREG17_AVAILABLE 1 +#define FM4_RTC_BREG18_AVAILABLE 1 +#define FM_RTC_BREG18_AVAILABLE 1 +#define FM4_RTC_BREG19_AVAILABLE 1 +#define FM_RTC_BREG19_AVAILABLE 1 +#define FM4_RTC_BREG1A_AVAILABLE 1 +#define FM_RTC_BREG1A_AVAILABLE 1 +#define FM4_RTC_BREG1B_AVAILABLE 1 +#define FM_RTC_BREG1B_AVAILABLE 1 +#define FM4_RTC_BREG1C_AVAILABLE 1 +#define FM_RTC_BREG1C_AVAILABLE 1 +#define FM4_RTC_BREG1D_AVAILABLE 1 +#define FM_RTC_BREG1D_AVAILABLE 1 +#define FM4_RTC_BREG1E_AVAILABLE 1 +#define FM_RTC_BREG1E_AVAILABLE 1 +#define FM4_RTC_BREG1F_AVAILABLE 1 +#define FM_RTC_BREG1F_AVAILABLE 1 +#define FM4_RTC_BREG20_AVAILABLE 1 +#define FM_RTC_BREG20_AVAILABLE 1 +#define FM4_RTC_BREG21_AVAILABLE 1 +#define FM_RTC_BREG21_AVAILABLE 1 +#define FM4_RTC_BREG22_AVAILABLE 1 +#define FM_RTC_BREG22_AVAILABLE 1 +#define FM4_RTC_BREG23_AVAILABLE 1 +#define FM_RTC_BREG23_AVAILABLE 1 +#define FM4_RTC_BREG24_AVAILABLE 1 +#define FM_RTC_BREG24_AVAILABLE 1 +#define FM4_RTC_BREG25_AVAILABLE 1 +#define FM_RTC_BREG25_AVAILABLE 1 +#define FM4_RTC_BREG26_AVAILABLE 1 +#define FM_RTC_BREG26_AVAILABLE 1 +#define FM4_RTC_BREG27_AVAILABLE 1 +#define FM_RTC_BREG27_AVAILABLE 1 +#define FM4_RTC_BREG28_AVAILABLE 1 +#define FM_RTC_BREG28_AVAILABLE 1 +#define FM4_RTC_BREG29_AVAILABLE 1 +#define FM_RTC_BREG29_AVAILABLE 1 +#define FM4_RTC_BREG2A_AVAILABLE 1 +#define FM_RTC_BREG2A_AVAILABLE 1 +#define FM4_RTC_BREG2B_AVAILABLE 1 +#define FM_RTC_BREG2B_AVAILABLE 1 +#define FM4_RTC_BREG2C_AVAILABLE 1 +#define FM_RTC_BREG2C_AVAILABLE 1 +#define FM4_RTC_BREG2D_AVAILABLE 1 +#define FM_RTC_BREG2D_AVAILABLE 1 +#define FM4_RTC_BREG2E_AVAILABLE 1 +#define FM_RTC_BREG2E_AVAILABLE 1 +#define FM4_RTC_BREG2F_AVAILABLE 1 +#define FM_RTC_BREG2F_AVAILABLE 1 +#define FM4_RTC_BREG30_AVAILABLE 1 +#define FM_RTC_BREG30_AVAILABLE 1 +#define FM4_RTC_BREG31_AVAILABLE 1 +#define FM_RTC_BREG31_AVAILABLE 1 +#define FM4_RTC_BREG32_AVAILABLE 1 +#define FM_RTC_BREG32_AVAILABLE 1 +#define FM4_RTC_BREG33_AVAILABLE 1 +#define FM_RTC_BREG33_AVAILABLE 1 +#define FM4_RTC_BREG34_AVAILABLE 1 +#define FM_RTC_BREG34_AVAILABLE 1 +#define FM4_RTC_BREG35_AVAILABLE 1 +#define FM_RTC_BREG35_AVAILABLE 1 +#define FM4_RTC_BREG36_AVAILABLE 1 +#define FM_RTC_BREG36_AVAILABLE 1 +#define FM4_RTC_BREG37_AVAILABLE 1 +#define FM_RTC_BREG37_AVAILABLE 1 +#define FM4_RTC_BREG38_AVAILABLE 1 +#define FM_RTC_BREG38_AVAILABLE 1 +#define FM4_RTC_BREG39_AVAILABLE 1 +#define FM_RTC_BREG39_AVAILABLE 1 +#define FM4_RTC_BREG3A_AVAILABLE 1 +#define FM_RTC_BREG3A_AVAILABLE 1 +#define FM4_RTC_BREG3B_AVAILABLE 1 +#define FM_RTC_BREG3B_AVAILABLE 1 +#define FM4_RTC_BREG3C_AVAILABLE 1 +#define FM_RTC_BREG3C_AVAILABLE 1 +#define FM4_RTC_BREG3D_AVAILABLE 1 +#define FM_RTC_BREG3D_AVAILABLE 1 +#define FM4_RTC_BREG3E_AVAILABLE 1 +#define FM_RTC_BREG3E_AVAILABLE 1 +#define FM4_RTC_BREG3F_AVAILABLE 1 +#define FM_RTC_BREG3F_AVAILABLE 1 +#define FM4_RTC_BREG40_AVAILABLE 1 +#define FM_RTC_BREG40_AVAILABLE 1 +#define FM4_RTC_BREG41_AVAILABLE 1 +#define FM_RTC_BREG41_AVAILABLE 1 +#define FM4_RTC_BREG42_AVAILABLE 1 +#define FM_RTC_BREG42_AVAILABLE 1 +#define FM4_RTC_BREG43_AVAILABLE 1 +#define FM_RTC_BREG43_AVAILABLE 1 +#define FM4_RTC_BREG44_AVAILABLE 1 +#define FM_RTC_BREG44_AVAILABLE 1 +#define FM4_RTC_BREG45_AVAILABLE 1 +#define FM_RTC_BREG45_AVAILABLE 1 +#define FM4_RTC_BREG46_AVAILABLE 1 +#define FM_RTC_BREG46_AVAILABLE 1 +#define FM4_RTC_BREG47_AVAILABLE 1 +#define FM_RTC_BREG47_AVAILABLE 1 +#define FM4_RTC_BREG48_AVAILABLE 1 +#define FM_RTC_BREG48_AVAILABLE 1 +#define FM4_RTC_BREG49_AVAILABLE 1 +#define FM_RTC_BREG49_AVAILABLE 1 +#define FM4_RTC_BREG4A_AVAILABLE 1 +#define FM_RTC_BREG4A_AVAILABLE 1 +#define FM4_RTC_BREG4B_AVAILABLE 1 +#define FM_RTC_BREG4B_AVAILABLE 1 +#define FM4_RTC_BREG4C_AVAILABLE 1 +#define FM_RTC_BREG4C_AVAILABLE 1 +#define FM4_RTC_BREG4D_AVAILABLE 1 +#define FM_RTC_BREG4D_AVAILABLE 1 +#define FM4_RTC_BREG4E_AVAILABLE 1 +#define FM_RTC_BREG4E_AVAILABLE 1 +#define FM4_RTC_BREG4F_AVAILABLE 1 +#define FM_RTC_BREG4F_AVAILABLE 1 +#define FM4_RTC_BREG50_AVAILABLE 1 +#define FM_RTC_BREG50_AVAILABLE 1 +#define FM4_RTC_BREG51_AVAILABLE 1 +#define FM_RTC_BREG51_AVAILABLE 1 +#define FM4_RTC_BREG52_AVAILABLE 1 +#define FM_RTC_BREG52_AVAILABLE 1 +#define FM4_RTC_BREG53_AVAILABLE 1 +#define FM_RTC_BREG53_AVAILABLE 1 +#define FM4_RTC_BREG54_AVAILABLE 1 +#define FM_RTC_BREG54_AVAILABLE 1 +#define FM4_RTC_BREG55_AVAILABLE 1 +#define FM_RTC_BREG55_AVAILABLE 1 +#define FM4_RTC_BREG56_AVAILABLE 1 +#define FM_RTC_BREG56_AVAILABLE 1 +#define FM4_RTC_BREG57_AVAILABLE 1 +#define FM_RTC_BREG57_AVAILABLE 1 +#define FM4_RTC_BREG58_AVAILABLE 1 +#define FM_RTC_BREG58_AVAILABLE 1 +#define FM4_RTC_BREG59_AVAILABLE 1 +#define FM_RTC_BREG59_AVAILABLE 1 +#define FM4_RTC_BREG5A_AVAILABLE 1 +#define FM_RTC_BREG5A_AVAILABLE 1 +#define FM4_RTC_BREG5B_AVAILABLE 1 +#define FM_RTC_BREG5B_AVAILABLE 1 +#define FM4_RTC_BREG5C_AVAILABLE 1 +#define FM_RTC_BREG5C_AVAILABLE 1 +#define FM4_RTC_BREG5D_AVAILABLE 1 +#define FM_RTC_BREG5D_AVAILABLE 1 +#define FM4_RTC_BREG5E_AVAILABLE 1 +#define FM_RTC_BREG5E_AVAILABLE 1 +#define FM4_RTC_BREG5F_AVAILABLE 1 +#define FM_RTC_BREG5F_AVAILABLE 1 +#define FM4_RTC_BREG60_AVAILABLE 1 +#define FM_RTC_BREG60_AVAILABLE 1 +#define FM4_RTC_BREG61_AVAILABLE 1 +#define FM_RTC_BREG61_AVAILABLE 1 +#define FM4_RTC_BREG62_AVAILABLE 1 +#define FM_RTC_BREG62_AVAILABLE 1 +#define FM4_RTC_BREG63_AVAILABLE 1 +#define FM_RTC_BREG63_AVAILABLE 1 +#define FM4_RTC_BREG64_AVAILABLE 1 +#define FM_RTC_BREG64_AVAILABLE 1 +#define FM4_RTC_BREG65_AVAILABLE 1 +#define FM_RTC_BREG65_AVAILABLE 1 +#define FM4_RTC_BREG66_AVAILABLE 1 +#define FM_RTC_BREG66_AVAILABLE 1 +#define FM4_RTC_BREG67_AVAILABLE 1 +#define FM_RTC_BREG67_AVAILABLE 1 +#define FM4_RTC_BREG68_AVAILABLE 1 +#define FM_RTC_BREG68_AVAILABLE 1 +#define FM4_RTC_BREG69_AVAILABLE 1 +#define FM_RTC_BREG69_AVAILABLE 1 +#define FM4_RTC_BREG6A_AVAILABLE 1 +#define FM_RTC_BREG6A_AVAILABLE 1 +#define FM4_RTC_BREG6B_AVAILABLE 1 +#define FM_RTC_BREG6B_AVAILABLE 1 +#define FM4_RTC_BREG6C_AVAILABLE 1 +#define FM_RTC_BREG6C_AVAILABLE 1 +#define FM4_RTC_BREG6D_AVAILABLE 1 +#define FM_RTC_BREG6D_AVAILABLE 1 +#define FM4_RTC_BREG6E_AVAILABLE 1 +#define FM_RTC_BREG6E_AVAILABLE 1 +#define FM4_RTC_BREG6F_AVAILABLE 1 +#define FM_RTC_BREG6F_AVAILABLE 1 +#define FM4_RTC_BREG70_AVAILABLE 1 +#define FM_RTC_BREG70_AVAILABLE 1 +#define FM4_RTC_BREG71_AVAILABLE 1 +#define FM_RTC_BREG71_AVAILABLE 1 +#define FM4_RTC_BREG72_AVAILABLE 1 +#define FM_RTC_BREG72_AVAILABLE 1 +#define FM4_RTC_BREG73_AVAILABLE 1 +#define FM_RTC_BREG73_AVAILABLE 1 +#define FM4_RTC_BREG74_AVAILABLE 1 +#define FM_RTC_BREG74_AVAILABLE 1 +#define FM4_RTC_BREG75_AVAILABLE 1 +#define FM_RTC_BREG75_AVAILABLE 1 +#define FM4_RTC_BREG76_AVAILABLE 1 +#define FM_RTC_BREG76_AVAILABLE 1 +#define FM4_RTC_BREG77_AVAILABLE 1 +#define FM_RTC_BREG77_AVAILABLE 1 +#define FM4_RTC_BREG78_AVAILABLE 1 +#define FM_RTC_BREG78_AVAILABLE 1 +#define FM4_RTC_BREG79_AVAILABLE 1 +#define FM_RTC_BREG79_AVAILABLE 1 +#define FM4_RTC_BREG7A_AVAILABLE 1 +#define FM_RTC_BREG7A_AVAILABLE 1 +#define FM4_RTC_BREG7B_AVAILABLE 1 +#define FM_RTC_BREG7B_AVAILABLE 1 +#define FM4_RTC_BREG7C_AVAILABLE 1 +#define FM_RTC_BREG7C_AVAILABLE 1 +#define FM4_RTC_BREG7D_AVAILABLE 1 +#define FM_RTC_BREG7D_AVAILABLE 1 +#define FM4_RTC_BREG7E_AVAILABLE 1 +#define FM_RTC_BREG7E_AVAILABLE 1 +#define FM4_RTC_BREG7F_AVAILABLE 1 +#define FM_RTC_BREG7F_AVAILABLE 1 +#define FM4_RTC_CCB_AVAILABLE 1 +#define FM_RTC_CCB_AVAILABLE 1 +#define FM4_RTC_CCS_AVAILABLE 1 +#define FM_RTC_CCS_AVAILABLE 1 +#define FM4_RTC_EWKUP_AVAILABLE 1 +#define FM_RTC_EWKUP_AVAILABLE 1 +#define FM4_RTC_HIBRST_AVAILABLE 1 +#define FM_RTC_HIBRST_AVAILABLE 1 +#define FM4_RTC_VB_CLKDIV_AVAILABLE 1 +#define FM_RTC_VB_CLKDIV_AVAILABLE 1 +#define FM4_RTC_VBDDR_AVAILABLE 1 +#define FM_RTC_VBDDR_AVAILABLE 1 +#define FM4_RTC_VBDIR_AVAILABLE 1 +#define FM_RTC_VBDIR_AVAILABLE 1 +#define FM4_RTC_VBDOR_AVAILABLE 1 +#define FM_RTC_VBDOR_AVAILABLE 1 +#define FM4_RTC_VBPCR_AVAILABLE 1 +#define FM_RTC_VBPCR_AVAILABLE 1 +#define FM4_RTC_VBPFR_AVAILABLE 1 +#define FM_RTC_VBPFR_AVAILABLE 1 +#define FM4_RTC_VBPZR_AVAILABLE 1 +#define FM_RTC_VBPZR_AVAILABLE 1 +#define FM4_RTC_VDET_AVAILABLE 1 +#define FM_RTC_VDET_AVAILABLE 1 +#define FM4_RTC_WTCAL0_AVAILABLE 1 +#define FM_RTC_WTCAL0_AVAILABLE 1 +#define FM4_RTC_WTCAL1_AVAILABLE 1 +#define FM_RTC_WTCAL1_AVAILABLE 1 +#define FM4_RTC_WTCALEN_AVAILABLE 1 +#define FM_RTC_WTCALEN_AVAILABLE 1 +#define FM4_RTC_WTCALPRD_AVAILABLE 1 +#define FM_RTC_WTCALPRD_AVAILABLE 1 +#define FM4_RTC_WTCOSEL_AVAILABLE 1 +#define FM_RTC_WTCOSEL_AVAILABLE 1 +#define FM4_RTC_WTCR10_AVAILABLE 1 +#define FM_RTC_WTCR10_AVAILABLE 1 +#define FM4_RTC_WTCR11_AVAILABLE 1 +#define FM_RTC_WTCR11_AVAILABLE 1 +#define FM4_RTC_WTCR12_AVAILABLE 1 +#define FM_RTC_WTCR12_AVAILABLE 1 +#define FM4_RTC_WTCR13_AVAILABLE 1 +#define FM_RTC_WTCR13_AVAILABLE 1 +#define FM4_RTC_WTCR20_AVAILABLE 1 +#define FM_RTC_WTCR20_AVAILABLE 1 +#define FM4_RTC_WTCR21_AVAILABLE 1 +#define FM_RTC_WTCR21_AVAILABLE 1 +#define FM4_RTC_WTDIV_AVAILABLE 1 +#define FM_RTC_WTDIV_AVAILABLE 1 +#define FM4_RTC_WTDIVEN_AVAILABLE 1 +#define FM_RTC_WTDIVEN_AVAILABLE 1 +#define FM4_RTC_WTDR_AVAILABLE 1 +#define FM_RTC_WTDR_AVAILABLE 1 +#define FM4_RTC_WTDW_AVAILABLE 1 +#define FM_RTC_WTDW_AVAILABLE 1 +#define FM4_RTC_WTHR_AVAILABLE 1 +#define FM_RTC_WTHR_AVAILABLE 1 +#define FM4_RTC_WTMIR_AVAILABLE 1 +#define FM_RTC_WTMIR_AVAILABLE 1 +#define FM4_RTC_WTMOR_AVAILABLE 1 +#define FM_RTC_WTMOR_AVAILABLE 1 +#define FM4_RTC_WTOSCCNT_AVAILABLE 1 +#define FM_RTC_WTOSCCNT_AVAILABLE 1 +#define FM4_RTC_WTSR_AVAILABLE 1 +#define FM_RTC_WTSR_AVAILABLE 1 +#define FM4_RTC_WTTR0_AVAILABLE 1 +#define FM_RTC_WTTR0_AVAILABLE 1 +#define FM4_RTC_WTTR1_AVAILABLE 1 +#define FM_RTC_WTTR1_AVAILABLE 1 +#define FM4_RTC_WTTR2_AVAILABLE 1 +#define FM_RTC_WTTR2_AVAILABLE 1 +#define FM4_RTC_WTYR_AVAILABLE 1 +#define FM_RTC_WTYR_AVAILABLE 1 +/******************************************************************************* +* SBSSR +*******************************************************************************/ +#define FM4_SBSSR_BTSSSR_AVAILABLE 1 +#define FM_SBSSR_BTSSSR_AVAILABLE 1 +/******************************************************************************* +* SDIF +*******************************************************************************/ +#define FM4_SDIF_ADMAEST_AVAILABLE 1 +#define FM_SDIF_ADMAEST_AVAILABLE 1 +#define FM4_SDIF_AHBCFGH_AVAILABLE 1 +#define FM_SDIF_AHBCFGH_AVAILABLE 1 +#define FM4_SDIF_AHBCFGL_AVAILABLE 1 +#define FM_SDIF_AHBCFGL_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY0_AVAILABLE 1 +#define FM_SDIF_CAPBLTY0_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY1_AVAILABLE 1 +#define FM_SDIF_CAPBLTY1_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY2_AVAILABLE 1 +#define FM_SDIF_CAPBLTY2_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY3_AVAILABLE 1 +#define FM_SDIF_CAPBLTY3_AVAILABLE 1 +#define FM4_SDIF_FEACEST_AVAILABLE 1 +#define FM_SDIF_FEACEST_AVAILABLE 1 +#define FM4_SDIF_MCRPCKBH_AVAILABLE 1 +#define FM_SDIF_MCRPCKBH_AVAILABLE 1 +#define FM4_SDIF_MCRPCKBL_AVAILABLE 1 +#define FM_SDIF_MCRPCKBL_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC0_AVAILABLE 1 +#define FM_SDIF_MCWIRQC0_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC1_AVAILABLE 1 +#define FM_SDIF_MCWIRQC1_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC2_AVAILABLE 1 +#define FM_SDIF_MCWIRQC2_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC3_AVAILABLE 1 +#define FM_SDIF_MCWIRQC3_AVAILABLE 1 +#define FM4_SDIF_MMCSDCH_AVAILABLE 1 +#define FM_SDIF_MMCSDCH_AVAILABLE 1 +#define FM4_SDIF_MMCSDCL_AVAILABLE 1 +#define FM_SDIF_MMCSDCL_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY0_AVAILABLE 1 +#define FM_SDIF_MXCCAPY0_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY1_AVAILABLE 1 +#define FM_SDIF_MXCCAPY1_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY2_AVAILABLE 1 +#define FM_SDIF_MXCCAPY2_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY3_AVAILABLE 1 +#define FM_SDIF_MXCCAPY3_AVAILABLE 1 +#define FM4_SDIF_PSWISGEH_AVAILABLE 1 +#define FM_SDIF_PSWISGEH_AVAILABLE 1 +#define FM4_SDIF_PSWISGEL_AVAILABLE 1 +#define FM_SDIF_PSWISGEL_AVAILABLE 1 +#define FM4_SDIF_PSWISTEH_AVAILABLE 1 +#define FM_SDIF_PSWISTEH_AVAILABLE 1 +#define FM4_SDIF_PSWISTEL_AVAILABLE 1 +#define FM_SDIF_PSWISTEL_AVAILABLE 1 +#define FM4_SDIF_PSWISTH_AVAILABLE 1 +#define FM_SDIF_PSWISTH_AVAILABLE 1 +#define FM4_SDIF_PSWISTL_AVAILABLE 1 +#define FM_SDIF_PSWISTL_AVAILABLE 1 +#define FM4_SDIF_SACMDEST_AVAILABLE 1 +#define FM_SDIF_SACMDEST_AVAILABLE 1 +#define FM4_SDIF_SADSA0_AVAILABLE 1 +#define FM_SDIF_SADSA0_AVAILABLE 1 +#define FM4_SDIF_SADSA1_AVAILABLE 1 +#define FM_SDIF_SADSA1_AVAILABLE 1 +#define FM4_SDIF_SADSA2_AVAILABLE 1 +#define FM_SDIF_SADSA2_AVAILABLE 1 +#define FM4_SDIF_SADSA3_AVAILABLE 1 +#define FM_SDIF_SADSA3_AVAILABLE 1 +#define FM4_SDIF_SBLCNT_AVAILABLE 1 +#define FM_SDIF_SBLCNT_AVAILABLE 1 +#define FM4_SDIF_SBLKGPCTL_AVAILABLE 1 +#define FM_SDIF_SBLKGPCTL_AVAILABLE 1 +#define FM4_SDIF_SBSIZE_AVAILABLE 1 +#define FM_SDIF_SBSIZE_AVAILABLE 1 +#define FM4_SDIF_SBUFDP_AVAILABLE 1 +#define FM_SDIF_SBUFDP_AVAILABLE 1 +#define FM4_SDIF_SCDETECS_AVAILABLE 1 +#define FM_SDIF_SCDETECS_AVAILABLE 1 +#define FM4_SDIF_SCLKCTL_AVAILABLE 1 +#define FM_SDIF_SCLKCTL_AVAILABLE 1 +#define FM4_SDIF_SCMMD_AVAILABLE 1 +#define FM_SDIF_SCMMD_AVAILABLE 1 +#define FM4_SDIF_SEINTSGE_AVAILABLE 1 +#define FM_SDIF_SEINTSGE_AVAILABLE 1 +#define FM4_SDIF_SEINTST_AVAILABLE 1 +#define FM_SDIF_SEINTST_AVAILABLE 1 +#define FM4_SDIF_SEINTSTE_AVAILABLE 1 +#define FM_SDIF_SEINTSTE_AVAILABLE 1 +#define FM4_SDIF_SFEEIST_AVAILABLE 1 +#define FM_SDIF_SFEEIST_AVAILABLE 1 +#define FM4_SDIF_SHCTL1_AVAILABLE 1 +#define FM_SDIF_SHCTL1_AVAILABLE 1 +#define FM4_SDIF_SHCTL2_AVAILABLE 1 +#define FM_SDIF_SHCTL2_AVAILABLE 1 +#define FM4_SDIF_SHCTLV_AVAILABLE 1 +#define FM_SDIF_SHCTLV_AVAILABLE 1 +#define FM4_SDIF_SNINTSGE_AVAILABLE 1 +#define FM_SDIF_SNINTSGE_AVAILABLE 1 +#define FM4_SDIF_SNINTST_AVAILABLE 1 +#define FM_SDIF_SNINTST_AVAILABLE 1 +#define FM4_SDIF_SNINTSTE_AVAILABLE 1 +#define FM_SDIF_SNINTSTE_AVAILABLE 1 +#define FM4_SDIF_SPRSTAT_AVAILABLE 1 +#define FM_SDIF_SPRSTAT_AVAILABLE 1 +#define FM4_SDIF_SPRVAL0_AVAILABLE 1 +#define FM_SDIF_SPRVAL0_AVAILABLE 1 +#define FM4_SDIF_SPRVAL1_AVAILABLE 1 +#define FM_SDIF_SPRVAL1_AVAILABLE 1 +#define FM4_SDIF_SPRVAL2_AVAILABLE 1 +#define FM_SDIF_SPRVAL2_AVAILABLE 1 +#define FM4_SDIF_SPRVAL3_AVAILABLE 1 +#define FM_SDIF_SPRVAL3_AVAILABLE 1 +#define FM4_SDIF_SPRVAL4_AVAILABLE 1 +#define FM_SDIF_SPRVAL4_AVAILABLE 1 +#define FM4_SDIF_SPRVAL5_AVAILABLE 1 +#define FM_SDIF_SPRVAL5_AVAILABLE 1 +#define FM4_SDIF_SPRVAL6_AVAILABLE 1 +#define FM_SDIF_SPRVAL6_AVAILABLE 1 +#define FM4_SDIF_SPRVAL7_AVAILABLE 1 +#define FM_SDIF_SPRVAL7_AVAILABLE 1 +#define FM4_SDIF_SPWRCTL_AVAILABLE 1 +#define FM_SDIF_SPWRCTL_AVAILABLE 1 +#define FM4_SDIF_SPWSWCH_AVAILABLE 1 +#define FM_SDIF_SPWSWCH_AVAILABLE 1 +#define FM4_SDIF_SPWSWCL_AVAILABLE 1 +#define FM_SDIF_SPWSWCL_AVAILABLE 1 +#define FM4_SDIF_SRESP0_AVAILABLE 1 +#define FM_SDIF_SRESP0_AVAILABLE 1 +#define FM4_SDIF_SRESP1_AVAILABLE 1 +#define FM_SDIF_SRESP1_AVAILABLE 1 +#define FM4_SDIF_SRESP2_AVAILABLE 1 +#define FM_SDIF_SRESP2_AVAILABLE 1 +#define FM4_SDIF_SRESP3_AVAILABLE 1 +#define FM_SDIF_SRESP3_AVAILABLE 1 +#define FM4_SDIF_SRESP4_AVAILABLE 1 +#define FM_SDIF_SRESP4_AVAILABLE 1 +#define FM4_SDIF_SRESP5_AVAILABLE 1 +#define FM_SDIF_SRESP5_AVAILABLE 1 +#define FM4_SDIF_SRESP6_AVAILABLE 1 +#define FM_SDIF_SRESP6_AVAILABLE 1 +#define FM4_SDIF_SRESP7_AVAILABLE 1 +#define FM_SDIF_SRESP7_AVAILABLE 1 +#define FM4_SDIF_SSA1_AVAILABLE 1 +#define FM_SDIF_SSA1_AVAILABLE 1 +#define FM4_SDIF_SSA2_AVAILABLE 1 +#define FM_SDIF_SSA2_AVAILABLE 1 +#define FM4_SDIF_SSHBCTLH_AVAILABLE 1 +#define FM_SDIF_SSHBCTLH_AVAILABLE 1 +#define FM4_SDIF_SSHBCTLL_AVAILABLE 1 +#define FM_SDIF_SSHBCTLL_AVAILABLE 1 +#define FM4_SDIF_SSLIST_AVAILABLE 1 +#define FM_SDIF_SSLIST_AVAILABLE 1 +#define FM4_SDIF_SSRST_AVAILABLE 1 +#define FM_SDIF_SSRST_AVAILABLE 1 +#define FM4_SDIF_STOCTL_AVAILABLE 1 +#define FM_SDIF_STOCTL_AVAILABLE 1 +#define FM4_SDIF_STRSFMD_AVAILABLE 1 +#define FM_SDIF_STRSFMD_AVAILABLE 1 +#define FM4_SDIF_STUNSETH_AVAILABLE 1 +#define FM_SDIF_STUNSETH_AVAILABLE 1 +#define FM4_SDIF_STUNSETL_AVAILABLE 1 +#define FM_SDIF_STUNSETL_AVAILABLE 1 +#define FM4_SDIF_STUNSTH_AVAILABLE 1 +#define FM_SDIF_STUNSTH_AVAILABLE 1 +#define FM4_SDIF_STUNSTL_AVAILABLE 1 +#define FM_SDIF_STUNSTL_AVAILABLE 1 +#define FM4_SDIF_SWKUPCTL_AVAILABLE 1 +#define FM_SDIF_SWKUPCTL_AVAILABLE 1 +/******************************************************************************* +* SWWDT +*******************************************************************************/ +#define FM4_SWWDT_WDOGCONTROL_AVAILABLE 1 +#define FM_SWWDT_WDOGCONTROL_AVAILABLE 1 +#define FM4_SWWDT_WDOGINTCLR_AVAILABLE 1 +#define FM_SWWDT_WDOGINTCLR_AVAILABLE 1 +#define FM4_SWWDT_WDOGLOAD_AVAILABLE 1 +#define FM_SWWDT_WDOGLOAD_AVAILABLE 1 +#define FM4_SWWDT_WDOGLOCK_AVAILABLE 1 +#define FM_SWWDT_WDOGLOCK_AVAILABLE 1 +#define FM4_SWWDT_WDOGRIS_AVAILABLE 1 +#define FM_SWWDT_WDOGRIS_AVAILABLE 1 +#define FM4_SWWDT_WDOGSPMC_AVAILABLE 1 +#define FM_SWWDT_WDOGSPMC_AVAILABLE 1 +#define FM4_SWWDT_WDOGVALUE_AVAILABLE 1 +#define FM_SWWDT_WDOGVALUE_AVAILABLE 1 +/******************************************************************************* +* UNIQUE_ID +*******************************************************************************/ +#define FM4_UNIQUE_ID_UIDR0_AVAILABLE 1 +#define FM_UNIQUE_ID_UIDR0_AVAILABLE 1 +#define FM4_UNIQUE_ID_UIDR1_AVAILABLE 1 +#define FM_UNIQUE_ID_UIDR1_AVAILABLE 1 +/******************************************************************************* +* USB0 +*******************************************************************************/ +#define FM4_USB_EP0C_AVAILABLE 1 +#define FM_USB_EP0C_AVAILABLE 1 +#define FM4_USB_EP0DT_AVAILABLE 1 +#define FM_USB_EP0DT_AVAILABLE 1 +#define FM4_USB_EP0IS_AVAILABLE 1 +#define FM_USB_EP0IS_AVAILABLE 1 +#define FM4_USB_EP0OS_AVAILABLE 1 +#define FM_USB_EP0OS_AVAILABLE 1 +#define FM4_USB_EP1C_AVAILABLE 1 +#define FM_USB_EP1C_AVAILABLE 1 +#define FM4_USB_EP1DT_AVAILABLE 1 +#define FM_USB_EP1DT_AVAILABLE 1 +#define FM4_USB_EP1S_AVAILABLE 1 +#define FM_USB_EP1S_AVAILABLE 1 +#define FM4_USB_EP2C_AVAILABLE 1 +#define FM_USB_EP2C_AVAILABLE 1 +#define FM4_USB_EP2DT_AVAILABLE 1 +#define FM_USB_EP2DT_AVAILABLE 1 +#define FM4_USB_EP2S_AVAILABLE 1 +#define FM_USB_EP2S_AVAILABLE 1 +#define FM4_USB_EP3C_AVAILABLE 1 +#define FM_USB_EP3C_AVAILABLE 1 +#define FM4_USB_EP3DT_AVAILABLE 1 +#define FM_USB_EP3DT_AVAILABLE 1 +#define FM4_USB_EP3S_AVAILABLE 1 +#define FM_USB_EP3S_AVAILABLE 1 +#define FM4_USB_EP4C_AVAILABLE 1 +#define FM_USB_EP4C_AVAILABLE 1 +#define FM4_USB_EP4DT_AVAILABLE 1 +#define FM_USB_EP4DT_AVAILABLE 1 +#define FM4_USB_EP4S_AVAILABLE 1 +#define FM_USB_EP4S_AVAILABLE 1 +#define FM4_USB_EP5C_AVAILABLE 1 +#define FM_USB_EP5C_AVAILABLE 1 +#define FM4_USB_EP5DT_AVAILABLE 1 +#define FM_USB_EP5DT_AVAILABLE 1 +#define FM4_USB_EP5S_AVAILABLE 1 +#define FM_USB_EP5S_AVAILABLE 1 +#define FM4_USB_HADR_AVAILABLE 1 +#define FM_USB_HADR_AVAILABLE 1 +#define FM4_USB_HCNT_AVAILABLE 1 +#define FM_USB_HCNT_AVAILABLE 1 +#define FM4_USB_HEOF_AVAILABLE 1 +#define FM_USB_HEOF_AVAILABLE 1 +#define FM4_USB_HERR_AVAILABLE 1 +#define FM_USB_HERR_AVAILABLE 1 +#define FM4_USB_HFCOMP_AVAILABLE 1 +#define FM_USB_HFCOMP_AVAILABLE 1 +#define FM4_USB_HFRAME_AVAILABLE 1 +#define FM_USB_HFRAME_AVAILABLE 1 +#define FM4_USB_HIRQ_AVAILABLE 1 +#define FM_USB_HIRQ_AVAILABLE 1 +#define FM4_USB_HRTIMER_AVAILABLE 1 +#define FM_USB_HRTIMER_AVAILABLE 1 +#define FM4_USB_HRTIMER2_AVAILABLE 1 +#define FM_USB_HRTIMER2_AVAILABLE 1 +#define FM4_USB_HSTATE_AVAILABLE 1 +#define FM_USB_HSTATE_AVAILABLE 1 +#define FM4_USB_HTOKEN_AVAILABLE 1 +#define FM_USB_HTOKEN_AVAILABLE 1 +#define FM4_USB_TMSP_AVAILABLE 1 +#define FM_USB_TMSP_AVAILABLE 1 +#define FM4_USB_UDCC_AVAILABLE 1 +#define FM_USB_UDCC_AVAILABLE 1 +#define FM4_USB_UDCIE_AVAILABLE 1 +#define FM_USB_UDCIE_AVAILABLE 1 +#define FM4_USB_UDCS_AVAILABLE 1 +#define FM_USB_UDCS_AVAILABLE 1 +/******************************************************************************* +* USBCLK +*******************************************************************************/ +#define FM4_USBCLK_UCCR_AVAILABLE 1 +#define FM_USBCLK_UCCR_AVAILABLE 1 +#define FM4_USBCLK_UP_STR_AVAILABLE 1 +#define FM_USBCLK_UP_STR_AVAILABLE 1 +#define FM4_USBCLK_UPCR1_AVAILABLE 1 +#define FM_USBCLK_UPCR1_AVAILABLE 1 +#define FM4_USBCLK_UPCR2_AVAILABLE 1 +#define FM_USBCLK_UPCR2_AVAILABLE 1 +#define FM4_USBCLK_UPCR3_AVAILABLE 1 +#define FM_USBCLK_UPCR3_AVAILABLE 1 +#define FM4_USBCLK_UPCR4_AVAILABLE 1 +#define FM_USBCLK_UPCR4_AVAILABLE 1 +#define FM4_USBCLK_UPCR5_AVAILABLE 1 +#define FM_USBCLK_UPCR5_AVAILABLE 1 +#define FM4_USBCLK_UPINT_CLR_AVAILABLE 1 +#define FM_USBCLK_UPINT_CLR_AVAILABLE 1 +#define FM4_USBCLK_UPINT_ENR_AVAILABLE 1 +#define FM_USBCLK_UPINT_ENR_AVAILABLE 1 +#define FM4_USBCLK_UPINT_STR_AVAILABLE 1 +#define FM_USBCLK_UPINT_STR_AVAILABLE 1 +#define FM4_USBCLK_USBEN0_AVAILABLE 1 +#define FM_USBCLK_USBEN0_AVAILABLE 1 +#define FM4_USBCLK_USBEN1_AVAILABLE 1 +#define FM_USBCLK_USBEN1_AVAILABLE 1 +/******************************************************************************* +* WC +*******************************************************************************/ +#define FM4_WC_CLK_EN_AVAILABLE 1 +#define FM_WC_CLK_EN_AVAILABLE 1 +#define FM4_WC_CLK_SEL_AVAILABLE 1 +#define FM_WC_CLK_SEL_AVAILABLE 1 +#define FM4_WC_WCCR_AVAILABLE 1 +#define FM_WC_WCCR_AVAILABLE 1 +#define FM4_WC_WCRD_AVAILABLE 1 +#define FM_WC_WCRD_AVAILABLE 1 +#define FM4_WC_WCRL_AVAILABLE 1 +#define FM_WC_WCRL_AVAILABLE 1 + +/******************************************************************************* +* Peripheral Bit Band Alias declaration +*******************************************************************************/ +/******************************************************************************* +* ADC Registers ADC0 +* Bitband Section +*******************************************************************************/ +#define bFM_ADC0_ADCEN_ENBL *((volatile uint8_t *)(0x424E0780UL)) +#define bFM4_ADC0_ADCEN_ENBL *((volatile uint8_t *)(0x424E0780UL)) +#define bFM_ADC0_ADCEN_READY *((volatile uint8_t *)(0x424E0784UL)) +#define bFM4_ADC0_ADCEN_READY *((volatile uint8_t *)(0x424E0784UL)) + +#define bFM_ADC0_ADCR_OVRIE *((volatile uint8_t *)(0x424E0020UL)) +#define bFM4_ADC0_ADCR_OVRIE *((volatile uint8_t *)(0x424E0020UL)) +#define bFM_ADC0_ADCR_CMPIE *((volatile uint8_t *)(0x424E0024UL)) +#define bFM4_ADC0_ADCR_CMPIE *((volatile uint8_t *)(0x424E0024UL)) +#define bFM_ADC0_ADCR_PCIE *((volatile uint8_t *)(0x424E0028UL)) +#define bFM4_ADC0_ADCR_PCIE *((volatile uint8_t *)(0x424E0028UL)) +#define bFM_ADC0_ADCR_SCIE *((volatile uint8_t *)(0x424E002CUL)) +#define bFM4_ADC0_ADCR_SCIE *((volatile uint8_t *)(0x424E002CUL)) +#define bFM_ADC0_ADCR_CMPIF *((volatile uint8_t *)(0x424E0034UL)) +#define bFM4_ADC0_ADCR_CMPIF *((volatile uint8_t *)(0x424E0034UL)) +#define bFM_ADC0_ADCR_PCIF *((volatile uint8_t *)(0x424E0038UL)) +#define bFM4_ADC0_ADCR_PCIF *((volatile uint8_t *)(0x424E0038UL)) +#define bFM_ADC0_ADCR_SCIF *((volatile uint8_t *)(0x424E003CUL)) +#define bFM4_ADC0_ADCR_SCIF *((volatile uint8_t *)(0x424E003CUL)) + +#define bFM_ADC0_ADSR_SCS *((volatile uint8_t *)(0x424E0000UL)) +#define bFM4_ADC0_ADSR_SCS *((volatile uint8_t *)(0x424E0000UL)) +#define bFM_ADC0_ADSR_PCS *((volatile uint8_t *)(0x424E0004UL)) +#define bFM4_ADC0_ADSR_PCS *((volatile uint8_t *)(0x424E0004UL)) +#define bFM_ADC0_ADSR_PCNS *((volatile uint8_t *)(0x424E0008UL)) +#define bFM4_ADC0_ADSR_PCNS *((volatile uint8_t *)(0x424E0008UL)) +#define bFM_ADC0_ADSR_FDAS *((volatile uint8_t *)(0x424E0018UL)) +#define bFM4_ADC0_ADSR_FDAS *((volatile uint8_t *)(0x424E0018UL)) +#define bFM_ADC0_ADSR_ADSTP *((volatile uint8_t *)(0x424E001CUL)) +#define bFM4_ADC0_ADSR_ADSTP *((volatile uint8_t *)(0x424E001CUL)) + +#define bFM_ADC0_ADSS01_TS0 *((volatile uint8_t *)(0x424E0580UL)) +#define bFM4_ADC0_ADSS01_TS0 *((volatile uint8_t *)(0x424E0580UL)) +#define bFM_ADC0_ADSS01_TS1 *((volatile uint8_t *)(0x424E0584UL)) +#define bFM4_ADC0_ADSS01_TS1 *((volatile uint8_t *)(0x424E0584UL)) +#define bFM_ADC0_ADSS01_TS2 *((volatile uint8_t *)(0x424E0588UL)) +#define bFM4_ADC0_ADSS01_TS2 *((volatile uint8_t *)(0x424E0588UL)) +#define bFM_ADC0_ADSS01_TS3 *((volatile uint8_t *)(0x424E058CUL)) +#define bFM4_ADC0_ADSS01_TS3 *((volatile uint8_t *)(0x424E058CUL)) +#define bFM_ADC0_ADSS01_TS4 *((volatile uint8_t *)(0x424E0590UL)) +#define bFM4_ADC0_ADSS01_TS4 *((volatile uint8_t *)(0x424E0590UL)) +#define bFM_ADC0_ADSS01_TS5 *((volatile uint8_t *)(0x424E0594UL)) +#define bFM4_ADC0_ADSS01_TS5 *((volatile uint8_t *)(0x424E0594UL)) +#define bFM_ADC0_ADSS01_TS6 *((volatile uint8_t *)(0x424E0598UL)) +#define bFM4_ADC0_ADSS01_TS6 *((volatile uint8_t *)(0x424E0598UL)) +#define bFM_ADC0_ADSS01_TS7 *((volatile uint8_t *)(0x424E059CUL)) +#define bFM4_ADC0_ADSS01_TS7 *((volatile uint8_t *)(0x424E059CUL)) +#define bFM_ADC0_ADSS01_TS8 *((volatile uint8_t *)(0x424E05A0UL)) +#define bFM4_ADC0_ADSS01_TS8 *((volatile uint8_t *)(0x424E05A0UL)) +#define bFM_ADC0_ADSS01_TS9 *((volatile uint8_t *)(0x424E05A4UL)) +#define bFM4_ADC0_ADSS01_TS9 *((volatile uint8_t *)(0x424E05A4UL)) +#define bFM_ADC0_ADSS01_TS10 *((volatile uint8_t *)(0x424E05A8UL)) +#define bFM4_ADC0_ADSS01_TS10 *((volatile uint8_t *)(0x424E05A8UL)) +#define bFM_ADC0_ADSS01_TS11 *((volatile uint8_t *)(0x424E05ACUL)) +#define bFM4_ADC0_ADSS01_TS11 *((volatile uint8_t *)(0x424E05ACUL)) +#define bFM_ADC0_ADSS01_TS12 *((volatile uint8_t *)(0x424E05B0UL)) +#define bFM4_ADC0_ADSS01_TS12 *((volatile uint8_t *)(0x424E05B0UL)) +#define bFM_ADC0_ADSS01_TS13 *((volatile uint8_t *)(0x424E05B4UL)) +#define bFM4_ADC0_ADSS01_TS13 *((volatile uint8_t *)(0x424E05B4UL)) +#define bFM_ADC0_ADSS01_TS14 *((volatile uint8_t *)(0x424E05B8UL)) +#define bFM4_ADC0_ADSS01_TS14 *((volatile uint8_t *)(0x424E05B8UL)) +#define bFM_ADC0_ADSS01_TS15 *((volatile uint8_t *)(0x424E05BCUL)) +#define bFM4_ADC0_ADSS01_TS15 *((volatile uint8_t *)(0x424E05BCUL)) + +#define bFM_ADC0_ADSS23_TS16 *((volatile uint8_t *)(0x424E0500UL)) +#define bFM4_ADC0_ADSS23_TS16 *((volatile uint8_t *)(0x424E0500UL)) +#define bFM_ADC0_ADSS23_TS17 *((volatile uint8_t *)(0x424E0504UL)) +#define bFM4_ADC0_ADSS23_TS17 *((volatile uint8_t *)(0x424E0504UL)) +#define bFM_ADC0_ADSS23_TS18 *((volatile uint8_t *)(0x424E0508UL)) +#define bFM4_ADC0_ADSS23_TS18 *((volatile uint8_t *)(0x424E0508UL)) +#define bFM_ADC0_ADSS23_TS19 *((volatile uint8_t *)(0x424E050CUL)) +#define bFM4_ADC0_ADSS23_TS19 *((volatile uint8_t *)(0x424E050CUL)) +#define bFM_ADC0_ADSS23_TS20 *((volatile uint8_t *)(0x424E0510UL)) +#define bFM4_ADC0_ADSS23_TS20 *((volatile uint8_t *)(0x424E0510UL)) +#define bFM_ADC0_ADSS23_TS21 *((volatile uint8_t *)(0x424E0514UL)) +#define bFM4_ADC0_ADSS23_TS21 *((volatile uint8_t *)(0x424E0514UL)) +#define bFM_ADC0_ADSS23_TS22 *((volatile uint8_t *)(0x424E0518UL)) +#define bFM4_ADC0_ADSS23_TS22 *((volatile uint8_t *)(0x424E0518UL)) +#define bFM_ADC0_ADSS23_TS23 *((volatile uint8_t *)(0x424E051CUL)) +#define bFM4_ADC0_ADSS23_TS23 *((volatile uint8_t *)(0x424E051CUL)) +#define bFM_ADC0_ADSS23_TS24 *((volatile uint8_t *)(0x424E0520UL)) +#define bFM4_ADC0_ADSS23_TS24 *((volatile uint8_t *)(0x424E0520UL)) +#define bFM_ADC0_ADSS23_TS25 *((volatile uint8_t *)(0x424E0524UL)) +#define bFM4_ADC0_ADSS23_TS25 *((volatile uint8_t *)(0x424E0524UL)) +#define bFM_ADC0_ADSS23_TS26 *((volatile uint8_t *)(0x424E0528UL)) +#define bFM4_ADC0_ADSS23_TS26 *((volatile uint8_t *)(0x424E0528UL)) +#define bFM_ADC0_ADSS23_TS27 *((volatile uint8_t *)(0x424E052CUL)) +#define bFM4_ADC0_ADSS23_TS27 *((volatile uint8_t *)(0x424E052CUL)) +#define bFM_ADC0_ADSS23_TS28 *((volatile uint8_t *)(0x424E0530UL)) +#define bFM4_ADC0_ADSS23_TS28 *((volatile uint8_t *)(0x424E0530UL)) +#define bFM_ADC0_ADSS23_TS29 *((volatile uint8_t *)(0x424E0534UL)) +#define bFM4_ADC0_ADSS23_TS29 *((volatile uint8_t *)(0x424E0534UL)) +#define bFM_ADC0_ADSS23_TS30 *((volatile uint8_t *)(0x424E0538UL)) +#define bFM4_ADC0_ADSS23_TS30 *((volatile uint8_t *)(0x424E0538UL)) +#define bFM_ADC0_ADSS23_TS31 *((volatile uint8_t *)(0x424E053CUL)) +#define bFM4_ADC0_ADSS23_TS31 *((volatile uint8_t *)(0x424E053CUL)) + +#define bFM_ADC0_CALSR_CLBEN *((volatile uint8_t *)(0x424E0820UL)) +#define bFM4_ADC0_CALSR_CLBEN *((volatile uint8_t *)(0x424E0820UL)) + +#define bFM_ADC0_CMPCR_CMD0 *((volatile uint8_t *)(0x424E0494UL)) +#define bFM4_ADC0_CMPCR_CMD0 *((volatile uint8_t *)(0x424E0494UL)) +#define bFM_ADC0_CMPCR_CMD1 *((volatile uint8_t *)(0x424E0498UL)) +#define bFM4_ADC0_CMPCR_CMD1 *((volatile uint8_t *)(0x424E0498UL)) +#define bFM_ADC0_CMPCR_CMPEN *((volatile uint8_t *)(0x424E049CUL)) +#define bFM4_ADC0_CMPCR_CMPEN *((volatile uint8_t *)(0x424E049CUL)) + +#define bFM_ADC0_PCCR_PSTR *((volatile uint8_t *)(0x424E0320UL)) +#define bFM4_ADC0_PCCR_PSTR *((volatile uint8_t *)(0x424E0320UL)) +#define bFM_ADC0_PCCR_PHEN *((volatile uint8_t *)(0x424E0324UL)) +#define bFM4_ADC0_PCCR_PHEN *((volatile uint8_t *)(0x424E0324UL)) +#define bFM_ADC0_PCCR_PEEN *((volatile uint8_t *)(0x424E0328UL)) +#define bFM4_ADC0_PCCR_PEEN *((volatile uint8_t *)(0x424E0328UL)) +#define bFM_ADC0_PCCR_ESCE *((volatile uint8_t *)(0x424E032CUL)) +#define bFM4_ADC0_PCCR_ESCE *((volatile uint8_t *)(0x424E032CUL)) +#define bFM_ADC0_PCCR_PFCLR *((volatile uint8_t *)(0x424E0330UL)) +#define bFM4_ADC0_PCCR_PFCLR *((volatile uint8_t *)(0x424E0330UL)) +#define bFM_ADC0_PCCR_POVR *((volatile uint8_t *)(0x424E0334UL)) +#define bFM4_ADC0_PCCR_POVR *((volatile uint8_t *)(0x424E0334UL)) +#define bFM_ADC0_PCCR_PFUL *((volatile uint8_t *)(0x424E0338UL)) +#define bFM4_ADC0_PCCR_PFUL *((volatile uint8_t *)(0x424E0338UL)) +#define bFM_ADC0_PCCR_PEMP *((volatile uint8_t *)(0x424E033CUL)) +#define bFM4_ADC0_PCCR_PEMP *((volatile uint8_t *)(0x424E033CUL)) + +#define bFM_ADC0_PCFD_INVL *((volatile uint8_t *)(0x424E03B0UL)) +#define bFM4_ADC0_PCFD_INVL *((volatile uint8_t *)(0x424E03B0UL)) + +#define bFM_ADC0_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E03B0UL)) +#define bFM4_ADC0_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E03B0UL)) + +#define bFM_ADC0_SCCR_SSTR *((volatile uint8_t *)(0x424E0120UL)) +#define bFM4_ADC0_SCCR_SSTR *((volatile uint8_t *)(0x424E0120UL)) +#define bFM_ADC0_SCCR_SHEN *((volatile uint8_t *)(0x424E0124UL)) +#define bFM4_ADC0_SCCR_SHEN *((volatile uint8_t *)(0x424E0124UL)) +#define bFM_ADC0_SCCR_RPT *((volatile uint8_t *)(0x424E0128UL)) +#define bFM4_ADC0_SCCR_RPT *((volatile uint8_t *)(0x424E0128UL)) +#define bFM_ADC0_SCCR_SFCLR *((volatile uint8_t *)(0x424E0130UL)) +#define bFM4_ADC0_SCCR_SFCLR *((volatile uint8_t *)(0x424E0130UL)) +#define bFM_ADC0_SCCR_SOVR *((volatile uint8_t *)(0x424E0134UL)) +#define bFM4_ADC0_SCCR_SOVR *((volatile uint8_t *)(0x424E0134UL)) +#define bFM_ADC0_SCCR_SFUL *((volatile uint8_t *)(0x424E0138UL)) +#define bFM4_ADC0_SCCR_SFUL *((volatile uint8_t *)(0x424E0138UL)) +#define bFM_ADC0_SCCR_SEMP *((volatile uint8_t *)(0x424E013CUL)) +#define bFM4_ADC0_SCCR_SEMP *((volatile uint8_t *)(0x424E013CUL)) + +#define bFM_ADC0_SCFD_INVL *((volatile uint8_t *)(0x424E01B0UL)) +#define bFM4_ADC0_SCFD_INVL *((volatile uint8_t *)(0x424E01B0UL)) + +#define bFM_ADC0_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E01B0UL)) +#define bFM4_ADC0_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E01B0UL)) + +#define bFM_ADC0_SCIS01_AN0 *((volatile uint8_t *)(0x424E0280UL)) +#define bFM4_ADC0_SCIS01_AN0 *((volatile uint8_t *)(0x424E0280UL)) +#define bFM_ADC0_SCIS01_AN1 *((volatile uint8_t *)(0x424E0284UL)) +#define bFM4_ADC0_SCIS01_AN1 *((volatile uint8_t *)(0x424E0284UL)) +#define bFM_ADC0_SCIS01_AN2 *((volatile uint8_t *)(0x424E0288UL)) +#define bFM4_ADC0_SCIS01_AN2 *((volatile uint8_t *)(0x424E0288UL)) +#define bFM_ADC0_SCIS01_AN3 *((volatile uint8_t *)(0x424E028CUL)) +#define bFM4_ADC0_SCIS01_AN3 *((volatile uint8_t *)(0x424E028CUL)) +#define bFM_ADC0_SCIS01_AN4 *((volatile uint8_t *)(0x424E0290UL)) +#define bFM4_ADC0_SCIS01_AN4 *((volatile uint8_t *)(0x424E0290UL)) +#define bFM_ADC0_SCIS01_AN5 *((volatile uint8_t *)(0x424E0294UL)) +#define bFM4_ADC0_SCIS01_AN5 *((volatile uint8_t *)(0x424E0294UL)) +#define bFM_ADC0_SCIS01_AN6 *((volatile uint8_t *)(0x424E0298UL)) +#define bFM4_ADC0_SCIS01_AN6 *((volatile uint8_t *)(0x424E0298UL)) +#define bFM_ADC0_SCIS01_AN7 *((volatile uint8_t *)(0x424E029CUL)) +#define bFM4_ADC0_SCIS01_AN7 *((volatile uint8_t *)(0x424E029CUL)) +#define bFM_ADC0_SCIS01_AN8 *((volatile uint8_t *)(0x424E02A0UL)) +#define bFM4_ADC0_SCIS01_AN8 *((volatile uint8_t *)(0x424E02A0UL)) +#define bFM_ADC0_SCIS01_AN9 *((volatile uint8_t *)(0x424E02A4UL)) +#define bFM4_ADC0_SCIS01_AN9 *((volatile uint8_t *)(0x424E02A4UL)) +#define bFM_ADC0_SCIS01_AN10 *((volatile uint8_t *)(0x424E02A8UL)) +#define bFM4_ADC0_SCIS01_AN10 *((volatile uint8_t *)(0x424E02A8UL)) +#define bFM_ADC0_SCIS01_AN11 *((volatile uint8_t *)(0x424E02ACUL)) +#define bFM4_ADC0_SCIS01_AN11 *((volatile uint8_t *)(0x424E02ACUL)) +#define bFM_ADC0_SCIS01_AN12 *((volatile uint8_t *)(0x424E02B0UL)) +#define bFM4_ADC0_SCIS01_AN12 *((volatile uint8_t *)(0x424E02B0UL)) +#define bFM_ADC0_SCIS01_AN13 *((volatile uint8_t *)(0x424E02B4UL)) +#define bFM4_ADC0_SCIS01_AN13 *((volatile uint8_t *)(0x424E02B4UL)) +#define bFM_ADC0_SCIS01_AN14 *((volatile uint8_t *)(0x424E02B8UL)) +#define bFM4_ADC0_SCIS01_AN14 *((volatile uint8_t *)(0x424E02B8UL)) +#define bFM_ADC0_SCIS01_AN15 *((volatile uint8_t *)(0x424E02BCUL)) +#define bFM4_ADC0_SCIS01_AN15 *((volatile uint8_t *)(0x424E02BCUL)) + +#define bFM_ADC0_SCIS23_AN16 *((volatile uint8_t *)(0x424E0200UL)) +#define bFM4_ADC0_SCIS23_AN16 *((volatile uint8_t *)(0x424E0200UL)) +#define bFM_ADC0_SCIS23_AN17 *((volatile uint8_t *)(0x424E0204UL)) +#define bFM4_ADC0_SCIS23_AN17 *((volatile uint8_t *)(0x424E0204UL)) +#define bFM_ADC0_SCIS23_AN18 *((volatile uint8_t *)(0x424E0208UL)) +#define bFM4_ADC0_SCIS23_AN18 *((volatile uint8_t *)(0x424E0208UL)) +#define bFM_ADC0_SCIS23_AN19 *((volatile uint8_t *)(0x424E020CUL)) +#define bFM4_ADC0_SCIS23_AN19 *((volatile uint8_t *)(0x424E020CUL)) +#define bFM_ADC0_SCIS23_AN20 *((volatile uint8_t *)(0x424E0210UL)) +#define bFM4_ADC0_SCIS23_AN20 *((volatile uint8_t *)(0x424E0210UL)) +#define bFM_ADC0_SCIS23_AN21 *((volatile uint8_t *)(0x424E0214UL)) +#define bFM4_ADC0_SCIS23_AN21 *((volatile uint8_t *)(0x424E0214UL)) +#define bFM_ADC0_SCIS23_AN22 *((volatile uint8_t *)(0x424E0218UL)) +#define bFM4_ADC0_SCIS23_AN22 *((volatile uint8_t *)(0x424E0218UL)) +#define bFM_ADC0_SCIS23_AN23 *((volatile uint8_t *)(0x424E021CUL)) +#define bFM4_ADC0_SCIS23_AN23 *((volatile uint8_t *)(0x424E021CUL)) +#define bFM_ADC0_SCIS23_AN24 *((volatile uint8_t *)(0x424E0220UL)) +#define bFM4_ADC0_SCIS23_AN24 *((volatile uint8_t *)(0x424E0220UL)) +#define bFM_ADC0_SCIS23_AN25 *((volatile uint8_t *)(0x424E0224UL)) +#define bFM4_ADC0_SCIS23_AN25 *((volatile uint8_t *)(0x424E0224UL)) +#define bFM_ADC0_SCIS23_AN26 *((volatile uint8_t *)(0x424E0228UL)) +#define bFM4_ADC0_SCIS23_AN26 *((volatile uint8_t *)(0x424E0228UL)) +#define bFM_ADC0_SCIS23_AN27 *((volatile uint8_t *)(0x424E022CUL)) +#define bFM4_ADC0_SCIS23_AN27 *((volatile uint8_t *)(0x424E022CUL)) +#define bFM_ADC0_SCIS23_AN28 *((volatile uint8_t *)(0x424E0230UL)) +#define bFM4_ADC0_SCIS23_AN28 *((volatile uint8_t *)(0x424E0230UL)) +#define bFM_ADC0_SCIS23_AN29 *((volatile uint8_t *)(0x424E0234UL)) +#define bFM4_ADC0_SCIS23_AN29 *((volatile uint8_t *)(0x424E0234UL)) +#define bFM_ADC0_SCIS23_AN30 *((volatile uint8_t *)(0x424E0238UL)) +#define bFM4_ADC0_SCIS23_AN30 *((volatile uint8_t *)(0x424E0238UL)) +#define bFM_ADC0_SCIS23_AN31 *((volatile uint8_t *)(0x424E023CUL)) +#define bFM4_ADC0_SCIS23_AN31 *((volatile uint8_t *)(0x424E023CUL)) + +#define bFM_ADC0_WCMPCR_RCOE *((volatile uint8_t *)(0x424E0988UL)) +#define bFM4_ADC0_WCMPCR_RCOE *((volatile uint8_t *)(0x424E0988UL)) +#define bFM_ADC0_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E098CUL)) +#define bFM4_ADC0_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E098CUL)) +#define bFM_ADC0_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E0990UL)) +#define bFM4_ADC0_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E0990UL)) + +#define bFM_ADC0_WCMPSR_WCMD *((volatile uint8_t *)(0x424E09B4UL)) +#define bFM4_ADC0_WCMPSR_WCMD *((volatile uint8_t *)(0x424E09B4UL)) + +#define bFM_ADC0_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E0900UL)) +#define bFM4_ADC0_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E0900UL)) + +#define bFM_ADC0_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E0880UL)) +#define bFM4_ADC0_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E0880UL)) + + +/******************************************************************************* +* ADC Registers ADC1 +* Bitband Section +*******************************************************************************/ +#define bFM_ADC1_ADCEN_ENBL *((volatile uint8_t *)(0x424E2780UL)) +#define bFM4_ADC1_ADCEN_ENBL *((volatile uint8_t *)(0x424E2780UL)) +#define bFM_ADC1_ADCEN_READY *((volatile uint8_t *)(0x424E2784UL)) +#define bFM4_ADC1_ADCEN_READY *((volatile uint8_t *)(0x424E2784UL)) + +#define bFM_ADC1_ADCR_OVRIE *((volatile uint8_t *)(0x424E2020UL)) +#define bFM4_ADC1_ADCR_OVRIE *((volatile uint8_t *)(0x424E2020UL)) +#define bFM_ADC1_ADCR_CMPIE *((volatile uint8_t *)(0x424E2024UL)) +#define bFM4_ADC1_ADCR_CMPIE *((volatile uint8_t *)(0x424E2024UL)) +#define bFM_ADC1_ADCR_PCIE *((volatile uint8_t *)(0x424E2028UL)) +#define bFM4_ADC1_ADCR_PCIE *((volatile uint8_t *)(0x424E2028UL)) +#define bFM_ADC1_ADCR_SCIE *((volatile uint8_t *)(0x424E202CUL)) +#define bFM4_ADC1_ADCR_SCIE *((volatile uint8_t *)(0x424E202CUL)) +#define bFM_ADC1_ADCR_CMPIF *((volatile uint8_t *)(0x424E2034UL)) +#define bFM4_ADC1_ADCR_CMPIF *((volatile uint8_t *)(0x424E2034UL)) +#define bFM_ADC1_ADCR_PCIF *((volatile uint8_t *)(0x424E2038UL)) +#define bFM4_ADC1_ADCR_PCIF *((volatile uint8_t *)(0x424E2038UL)) +#define bFM_ADC1_ADCR_SCIF *((volatile uint8_t *)(0x424E203CUL)) +#define bFM4_ADC1_ADCR_SCIF *((volatile uint8_t *)(0x424E203CUL)) + +#define bFM_ADC1_ADSR_SCS *((volatile uint8_t *)(0x424E2000UL)) +#define bFM4_ADC1_ADSR_SCS *((volatile uint8_t *)(0x424E2000UL)) +#define bFM_ADC1_ADSR_PCS *((volatile uint8_t *)(0x424E2004UL)) +#define bFM4_ADC1_ADSR_PCS *((volatile uint8_t *)(0x424E2004UL)) +#define bFM_ADC1_ADSR_PCNS *((volatile uint8_t *)(0x424E2008UL)) +#define bFM4_ADC1_ADSR_PCNS *((volatile uint8_t *)(0x424E2008UL)) +#define bFM_ADC1_ADSR_FDAS *((volatile uint8_t *)(0x424E2018UL)) +#define bFM4_ADC1_ADSR_FDAS *((volatile uint8_t *)(0x424E2018UL)) +#define bFM_ADC1_ADSR_ADSTP *((volatile uint8_t *)(0x424E201CUL)) +#define bFM4_ADC1_ADSR_ADSTP *((volatile uint8_t *)(0x424E201CUL)) + +#define bFM_ADC1_ADSS01_TS0 *((volatile uint8_t *)(0x424E2580UL)) +#define bFM4_ADC1_ADSS01_TS0 *((volatile uint8_t *)(0x424E2580UL)) +#define bFM_ADC1_ADSS01_TS1 *((volatile uint8_t *)(0x424E2584UL)) +#define bFM4_ADC1_ADSS01_TS1 *((volatile uint8_t *)(0x424E2584UL)) +#define bFM_ADC1_ADSS01_TS2 *((volatile uint8_t *)(0x424E2588UL)) +#define bFM4_ADC1_ADSS01_TS2 *((volatile uint8_t *)(0x424E2588UL)) +#define bFM_ADC1_ADSS01_TS3 *((volatile uint8_t *)(0x424E258CUL)) +#define bFM4_ADC1_ADSS01_TS3 *((volatile uint8_t *)(0x424E258CUL)) +#define bFM_ADC1_ADSS01_TS4 *((volatile uint8_t *)(0x424E2590UL)) +#define bFM4_ADC1_ADSS01_TS4 *((volatile uint8_t *)(0x424E2590UL)) +#define bFM_ADC1_ADSS01_TS5 *((volatile uint8_t *)(0x424E2594UL)) +#define bFM4_ADC1_ADSS01_TS5 *((volatile uint8_t *)(0x424E2594UL)) +#define bFM_ADC1_ADSS01_TS6 *((volatile uint8_t *)(0x424E2598UL)) +#define bFM4_ADC1_ADSS01_TS6 *((volatile uint8_t *)(0x424E2598UL)) +#define bFM_ADC1_ADSS01_TS7 *((volatile uint8_t *)(0x424E259CUL)) +#define bFM4_ADC1_ADSS01_TS7 *((volatile uint8_t *)(0x424E259CUL)) +#define bFM_ADC1_ADSS01_TS8 *((volatile uint8_t *)(0x424E25A0UL)) +#define bFM4_ADC1_ADSS01_TS8 *((volatile uint8_t *)(0x424E25A0UL)) +#define bFM_ADC1_ADSS01_TS9 *((volatile uint8_t *)(0x424E25A4UL)) +#define bFM4_ADC1_ADSS01_TS9 *((volatile uint8_t *)(0x424E25A4UL)) +#define bFM_ADC1_ADSS01_TS10 *((volatile uint8_t *)(0x424E25A8UL)) +#define bFM4_ADC1_ADSS01_TS10 *((volatile uint8_t *)(0x424E25A8UL)) +#define bFM_ADC1_ADSS01_TS11 *((volatile uint8_t *)(0x424E25ACUL)) +#define bFM4_ADC1_ADSS01_TS11 *((volatile uint8_t *)(0x424E25ACUL)) +#define bFM_ADC1_ADSS01_TS12 *((volatile uint8_t *)(0x424E25B0UL)) +#define bFM4_ADC1_ADSS01_TS12 *((volatile uint8_t *)(0x424E25B0UL)) +#define bFM_ADC1_ADSS01_TS13 *((volatile uint8_t *)(0x424E25B4UL)) +#define bFM4_ADC1_ADSS01_TS13 *((volatile uint8_t *)(0x424E25B4UL)) +#define bFM_ADC1_ADSS01_TS14 *((volatile uint8_t *)(0x424E25B8UL)) +#define bFM4_ADC1_ADSS01_TS14 *((volatile uint8_t *)(0x424E25B8UL)) +#define bFM_ADC1_ADSS01_TS15 *((volatile uint8_t *)(0x424E25BCUL)) +#define bFM4_ADC1_ADSS01_TS15 *((volatile uint8_t *)(0x424E25BCUL)) + +#define bFM_ADC1_ADSS23_TS16 *((volatile uint8_t *)(0x424E2500UL)) +#define bFM4_ADC1_ADSS23_TS16 *((volatile uint8_t *)(0x424E2500UL)) +#define bFM_ADC1_ADSS23_TS17 *((volatile uint8_t *)(0x424E2504UL)) +#define bFM4_ADC1_ADSS23_TS17 *((volatile uint8_t *)(0x424E2504UL)) +#define bFM_ADC1_ADSS23_TS18 *((volatile uint8_t *)(0x424E2508UL)) +#define bFM4_ADC1_ADSS23_TS18 *((volatile uint8_t *)(0x424E2508UL)) +#define bFM_ADC1_ADSS23_TS19 *((volatile uint8_t *)(0x424E250CUL)) +#define bFM4_ADC1_ADSS23_TS19 *((volatile uint8_t *)(0x424E250CUL)) +#define bFM_ADC1_ADSS23_TS20 *((volatile uint8_t *)(0x424E2510UL)) +#define bFM4_ADC1_ADSS23_TS20 *((volatile uint8_t *)(0x424E2510UL)) +#define bFM_ADC1_ADSS23_TS21 *((volatile uint8_t *)(0x424E2514UL)) +#define bFM4_ADC1_ADSS23_TS21 *((volatile uint8_t *)(0x424E2514UL)) +#define bFM_ADC1_ADSS23_TS22 *((volatile uint8_t *)(0x424E2518UL)) +#define bFM4_ADC1_ADSS23_TS22 *((volatile uint8_t *)(0x424E2518UL)) +#define bFM_ADC1_ADSS23_TS23 *((volatile uint8_t *)(0x424E251CUL)) +#define bFM4_ADC1_ADSS23_TS23 *((volatile uint8_t *)(0x424E251CUL)) +#define bFM_ADC1_ADSS23_TS24 *((volatile uint8_t *)(0x424E2520UL)) +#define bFM4_ADC1_ADSS23_TS24 *((volatile uint8_t *)(0x424E2520UL)) +#define bFM_ADC1_ADSS23_TS25 *((volatile uint8_t *)(0x424E2524UL)) +#define bFM4_ADC1_ADSS23_TS25 *((volatile uint8_t *)(0x424E2524UL)) +#define bFM_ADC1_ADSS23_TS26 *((volatile uint8_t *)(0x424E2528UL)) +#define bFM4_ADC1_ADSS23_TS26 *((volatile uint8_t *)(0x424E2528UL)) +#define bFM_ADC1_ADSS23_TS27 *((volatile uint8_t *)(0x424E252CUL)) +#define bFM4_ADC1_ADSS23_TS27 *((volatile uint8_t *)(0x424E252CUL)) +#define bFM_ADC1_ADSS23_TS28 *((volatile uint8_t *)(0x424E2530UL)) +#define bFM4_ADC1_ADSS23_TS28 *((volatile uint8_t *)(0x424E2530UL)) +#define bFM_ADC1_ADSS23_TS29 *((volatile uint8_t *)(0x424E2534UL)) +#define bFM4_ADC1_ADSS23_TS29 *((volatile uint8_t *)(0x424E2534UL)) +#define bFM_ADC1_ADSS23_TS30 *((volatile uint8_t *)(0x424E2538UL)) +#define bFM4_ADC1_ADSS23_TS30 *((volatile uint8_t *)(0x424E2538UL)) +#define bFM_ADC1_ADSS23_TS31 *((volatile uint8_t *)(0x424E253CUL)) +#define bFM4_ADC1_ADSS23_TS31 *((volatile uint8_t *)(0x424E253CUL)) + +#define bFM_ADC1_CALSR_CLBEN *((volatile uint8_t *)(0x424E2820UL)) +#define bFM4_ADC1_CALSR_CLBEN *((volatile uint8_t *)(0x424E2820UL)) + +#define bFM_ADC1_CMPCR_CMD0 *((volatile uint8_t *)(0x424E2494UL)) +#define bFM4_ADC1_CMPCR_CMD0 *((volatile uint8_t *)(0x424E2494UL)) +#define bFM_ADC1_CMPCR_CMD1 *((volatile uint8_t *)(0x424E2498UL)) +#define bFM4_ADC1_CMPCR_CMD1 *((volatile uint8_t *)(0x424E2498UL)) +#define bFM_ADC1_CMPCR_CMPEN *((volatile uint8_t *)(0x424E249CUL)) +#define bFM4_ADC1_CMPCR_CMPEN *((volatile uint8_t *)(0x424E249CUL)) + +#define bFM_ADC1_PCCR_PSTR *((volatile uint8_t *)(0x424E2320UL)) +#define bFM4_ADC1_PCCR_PSTR *((volatile uint8_t *)(0x424E2320UL)) +#define bFM_ADC1_PCCR_PHEN *((volatile uint8_t *)(0x424E2324UL)) +#define bFM4_ADC1_PCCR_PHEN *((volatile uint8_t *)(0x424E2324UL)) +#define bFM_ADC1_PCCR_PEEN *((volatile uint8_t *)(0x424E2328UL)) +#define bFM4_ADC1_PCCR_PEEN *((volatile uint8_t *)(0x424E2328UL)) +#define bFM_ADC1_PCCR_ESCE *((volatile uint8_t *)(0x424E232CUL)) +#define bFM4_ADC1_PCCR_ESCE *((volatile uint8_t *)(0x424E232CUL)) +#define bFM_ADC1_PCCR_PFCLR *((volatile uint8_t *)(0x424E2330UL)) +#define bFM4_ADC1_PCCR_PFCLR *((volatile uint8_t *)(0x424E2330UL)) +#define bFM_ADC1_PCCR_POVR *((volatile uint8_t *)(0x424E2334UL)) +#define bFM4_ADC1_PCCR_POVR *((volatile uint8_t *)(0x424E2334UL)) +#define bFM_ADC1_PCCR_PFUL *((volatile uint8_t *)(0x424E2338UL)) +#define bFM4_ADC1_PCCR_PFUL *((volatile uint8_t *)(0x424E2338UL)) +#define bFM_ADC1_PCCR_PEMP *((volatile uint8_t *)(0x424E233CUL)) +#define bFM4_ADC1_PCCR_PEMP *((volatile uint8_t *)(0x424E233CUL)) + +#define bFM_ADC1_PCFD_INVL *((volatile uint8_t *)(0x424E23B0UL)) +#define bFM4_ADC1_PCFD_INVL *((volatile uint8_t *)(0x424E23B0UL)) + +#define bFM_ADC1_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E23B0UL)) +#define bFM4_ADC1_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E23B0UL)) + +#define bFM_ADC1_SCCR_SSTR *((volatile uint8_t *)(0x424E2120UL)) +#define bFM4_ADC1_SCCR_SSTR *((volatile uint8_t *)(0x424E2120UL)) +#define bFM_ADC1_SCCR_SHEN *((volatile uint8_t *)(0x424E2124UL)) +#define bFM4_ADC1_SCCR_SHEN *((volatile uint8_t *)(0x424E2124UL)) +#define bFM_ADC1_SCCR_RPT *((volatile uint8_t *)(0x424E2128UL)) +#define bFM4_ADC1_SCCR_RPT *((volatile uint8_t *)(0x424E2128UL)) +#define bFM_ADC1_SCCR_SFCLR *((volatile uint8_t *)(0x424E2130UL)) +#define bFM4_ADC1_SCCR_SFCLR *((volatile uint8_t *)(0x424E2130UL)) +#define bFM_ADC1_SCCR_SOVR *((volatile uint8_t *)(0x424E2134UL)) +#define bFM4_ADC1_SCCR_SOVR *((volatile uint8_t *)(0x424E2134UL)) +#define bFM_ADC1_SCCR_SFUL *((volatile uint8_t *)(0x424E2138UL)) +#define bFM4_ADC1_SCCR_SFUL *((volatile uint8_t *)(0x424E2138UL)) +#define bFM_ADC1_SCCR_SEMP *((volatile uint8_t *)(0x424E213CUL)) +#define bFM4_ADC1_SCCR_SEMP *((volatile uint8_t *)(0x424E213CUL)) + +#define bFM_ADC1_SCFD_INVL *((volatile uint8_t *)(0x424E21B0UL)) +#define bFM4_ADC1_SCFD_INVL *((volatile uint8_t *)(0x424E21B0UL)) + +#define bFM_ADC1_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E21B0UL)) +#define bFM4_ADC1_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E21B0UL)) + +#define bFM_ADC1_SCIS01_AN0 *((volatile uint8_t *)(0x424E2280UL)) +#define bFM4_ADC1_SCIS01_AN0 *((volatile uint8_t *)(0x424E2280UL)) +#define bFM_ADC1_SCIS01_AN1 *((volatile uint8_t *)(0x424E2284UL)) +#define bFM4_ADC1_SCIS01_AN1 *((volatile uint8_t *)(0x424E2284UL)) +#define bFM_ADC1_SCIS01_AN2 *((volatile uint8_t *)(0x424E2288UL)) +#define bFM4_ADC1_SCIS01_AN2 *((volatile uint8_t *)(0x424E2288UL)) +#define bFM_ADC1_SCIS01_AN3 *((volatile uint8_t *)(0x424E228CUL)) +#define bFM4_ADC1_SCIS01_AN3 *((volatile uint8_t *)(0x424E228CUL)) +#define bFM_ADC1_SCIS01_AN4 *((volatile uint8_t *)(0x424E2290UL)) +#define bFM4_ADC1_SCIS01_AN4 *((volatile uint8_t *)(0x424E2290UL)) +#define bFM_ADC1_SCIS01_AN5 *((volatile uint8_t *)(0x424E2294UL)) +#define bFM4_ADC1_SCIS01_AN5 *((volatile uint8_t *)(0x424E2294UL)) +#define bFM_ADC1_SCIS01_AN6 *((volatile uint8_t *)(0x424E2298UL)) +#define bFM4_ADC1_SCIS01_AN6 *((volatile uint8_t *)(0x424E2298UL)) +#define bFM_ADC1_SCIS01_AN7 *((volatile uint8_t *)(0x424E229CUL)) +#define bFM4_ADC1_SCIS01_AN7 *((volatile uint8_t *)(0x424E229CUL)) +#define bFM_ADC1_SCIS01_AN8 *((volatile uint8_t *)(0x424E22A0UL)) +#define bFM4_ADC1_SCIS01_AN8 *((volatile uint8_t *)(0x424E22A0UL)) +#define bFM_ADC1_SCIS01_AN9 *((volatile uint8_t *)(0x424E22A4UL)) +#define bFM4_ADC1_SCIS01_AN9 *((volatile uint8_t *)(0x424E22A4UL)) +#define bFM_ADC1_SCIS01_AN10 *((volatile uint8_t *)(0x424E22A8UL)) +#define bFM4_ADC1_SCIS01_AN10 *((volatile uint8_t *)(0x424E22A8UL)) +#define bFM_ADC1_SCIS01_AN11 *((volatile uint8_t *)(0x424E22ACUL)) +#define bFM4_ADC1_SCIS01_AN11 *((volatile uint8_t *)(0x424E22ACUL)) +#define bFM_ADC1_SCIS01_AN12 *((volatile uint8_t *)(0x424E22B0UL)) +#define bFM4_ADC1_SCIS01_AN12 *((volatile uint8_t *)(0x424E22B0UL)) +#define bFM_ADC1_SCIS01_AN13 *((volatile uint8_t *)(0x424E22B4UL)) +#define bFM4_ADC1_SCIS01_AN13 *((volatile uint8_t *)(0x424E22B4UL)) +#define bFM_ADC1_SCIS01_AN14 *((volatile uint8_t *)(0x424E22B8UL)) +#define bFM4_ADC1_SCIS01_AN14 *((volatile uint8_t *)(0x424E22B8UL)) +#define bFM_ADC1_SCIS01_AN15 *((volatile uint8_t *)(0x424E22BCUL)) +#define bFM4_ADC1_SCIS01_AN15 *((volatile uint8_t *)(0x424E22BCUL)) + +#define bFM_ADC1_SCIS23_AN16 *((volatile uint8_t *)(0x424E2200UL)) +#define bFM4_ADC1_SCIS23_AN16 *((volatile uint8_t *)(0x424E2200UL)) +#define bFM_ADC1_SCIS23_AN17 *((volatile uint8_t *)(0x424E2204UL)) +#define bFM4_ADC1_SCIS23_AN17 *((volatile uint8_t *)(0x424E2204UL)) +#define bFM_ADC1_SCIS23_AN18 *((volatile uint8_t *)(0x424E2208UL)) +#define bFM4_ADC1_SCIS23_AN18 *((volatile uint8_t *)(0x424E2208UL)) +#define bFM_ADC1_SCIS23_AN19 *((volatile uint8_t *)(0x424E220CUL)) +#define bFM4_ADC1_SCIS23_AN19 *((volatile uint8_t *)(0x424E220CUL)) +#define bFM_ADC1_SCIS23_AN20 *((volatile uint8_t *)(0x424E2210UL)) +#define bFM4_ADC1_SCIS23_AN20 *((volatile uint8_t *)(0x424E2210UL)) +#define bFM_ADC1_SCIS23_AN21 *((volatile uint8_t *)(0x424E2214UL)) +#define bFM4_ADC1_SCIS23_AN21 *((volatile uint8_t *)(0x424E2214UL)) +#define bFM_ADC1_SCIS23_AN22 *((volatile uint8_t *)(0x424E2218UL)) +#define bFM4_ADC1_SCIS23_AN22 *((volatile uint8_t *)(0x424E2218UL)) +#define bFM_ADC1_SCIS23_AN23 *((volatile uint8_t *)(0x424E221CUL)) +#define bFM4_ADC1_SCIS23_AN23 *((volatile uint8_t *)(0x424E221CUL)) +#define bFM_ADC1_SCIS23_AN24 *((volatile uint8_t *)(0x424E2220UL)) +#define bFM4_ADC1_SCIS23_AN24 *((volatile uint8_t *)(0x424E2220UL)) +#define bFM_ADC1_SCIS23_AN25 *((volatile uint8_t *)(0x424E2224UL)) +#define bFM4_ADC1_SCIS23_AN25 *((volatile uint8_t *)(0x424E2224UL)) +#define bFM_ADC1_SCIS23_AN26 *((volatile uint8_t *)(0x424E2228UL)) +#define bFM4_ADC1_SCIS23_AN26 *((volatile uint8_t *)(0x424E2228UL)) +#define bFM_ADC1_SCIS23_AN27 *((volatile uint8_t *)(0x424E222CUL)) +#define bFM4_ADC1_SCIS23_AN27 *((volatile uint8_t *)(0x424E222CUL)) +#define bFM_ADC1_SCIS23_AN28 *((volatile uint8_t *)(0x424E2230UL)) +#define bFM4_ADC1_SCIS23_AN28 *((volatile uint8_t *)(0x424E2230UL)) +#define bFM_ADC1_SCIS23_AN29 *((volatile uint8_t *)(0x424E2234UL)) +#define bFM4_ADC1_SCIS23_AN29 *((volatile uint8_t *)(0x424E2234UL)) +#define bFM_ADC1_SCIS23_AN30 *((volatile uint8_t *)(0x424E2238UL)) +#define bFM4_ADC1_SCIS23_AN30 *((volatile uint8_t *)(0x424E2238UL)) +#define bFM_ADC1_SCIS23_AN31 *((volatile uint8_t *)(0x424E223CUL)) +#define bFM4_ADC1_SCIS23_AN31 *((volatile uint8_t *)(0x424E223CUL)) + +#define bFM_ADC1_WCMPCR_RCOE *((volatile uint8_t *)(0x424E2988UL)) +#define bFM4_ADC1_WCMPCR_RCOE *((volatile uint8_t *)(0x424E2988UL)) +#define bFM_ADC1_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E298CUL)) +#define bFM4_ADC1_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E298CUL)) +#define bFM_ADC1_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E2990UL)) +#define bFM4_ADC1_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E2990UL)) + +#define bFM_ADC1_WCMPSR_WCMD *((volatile uint8_t *)(0x424E29B4UL)) +#define bFM4_ADC1_WCMPSR_WCMD *((volatile uint8_t *)(0x424E29B4UL)) + +#define bFM_ADC1_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E2900UL)) +#define bFM4_ADC1_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E2900UL)) + +#define bFM_ADC1_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E2880UL)) +#define bFM4_ADC1_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E2880UL)) + + +/******************************************************************************* +* ADC Registers ADC2 +* Bitband Section +*******************************************************************************/ +#define bFM_ADC2_ADCEN_ENBL *((volatile uint8_t *)(0x424E4780UL)) +#define bFM4_ADC2_ADCEN_ENBL *((volatile uint8_t *)(0x424E4780UL)) +#define bFM_ADC2_ADCEN_READY *((volatile uint8_t *)(0x424E4784UL)) +#define bFM4_ADC2_ADCEN_READY *((volatile uint8_t *)(0x424E4784UL)) + +#define bFM_ADC2_ADCR_OVRIE *((volatile uint8_t *)(0x424E4020UL)) +#define bFM4_ADC2_ADCR_OVRIE *((volatile uint8_t *)(0x424E4020UL)) +#define bFM_ADC2_ADCR_CMPIE *((volatile uint8_t *)(0x424E4024UL)) +#define bFM4_ADC2_ADCR_CMPIE *((volatile uint8_t *)(0x424E4024UL)) +#define bFM_ADC2_ADCR_PCIE *((volatile uint8_t *)(0x424E4028UL)) +#define bFM4_ADC2_ADCR_PCIE *((volatile uint8_t *)(0x424E4028UL)) +#define bFM_ADC2_ADCR_SCIE *((volatile uint8_t *)(0x424E402CUL)) +#define bFM4_ADC2_ADCR_SCIE *((volatile uint8_t *)(0x424E402CUL)) +#define bFM_ADC2_ADCR_CMPIF *((volatile uint8_t *)(0x424E4034UL)) +#define bFM4_ADC2_ADCR_CMPIF *((volatile uint8_t *)(0x424E4034UL)) +#define bFM_ADC2_ADCR_PCIF *((volatile uint8_t *)(0x424E4038UL)) +#define bFM4_ADC2_ADCR_PCIF *((volatile uint8_t *)(0x424E4038UL)) +#define bFM_ADC2_ADCR_SCIF *((volatile uint8_t *)(0x424E403CUL)) +#define bFM4_ADC2_ADCR_SCIF *((volatile uint8_t *)(0x424E403CUL)) + +#define bFM_ADC2_ADSR_SCS *((volatile uint8_t *)(0x424E4000UL)) +#define bFM4_ADC2_ADSR_SCS *((volatile uint8_t *)(0x424E4000UL)) +#define bFM_ADC2_ADSR_PCS *((volatile uint8_t *)(0x424E4004UL)) +#define bFM4_ADC2_ADSR_PCS *((volatile uint8_t *)(0x424E4004UL)) +#define bFM_ADC2_ADSR_PCNS *((volatile uint8_t *)(0x424E4008UL)) +#define bFM4_ADC2_ADSR_PCNS *((volatile uint8_t *)(0x424E4008UL)) +#define bFM_ADC2_ADSR_FDAS *((volatile uint8_t *)(0x424E4018UL)) +#define bFM4_ADC2_ADSR_FDAS *((volatile uint8_t *)(0x424E4018UL)) +#define bFM_ADC2_ADSR_ADSTP *((volatile uint8_t *)(0x424E401CUL)) +#define bFM4_ADC2_ADSR_ADSTP *((volatile uint8_t *)(0x424E401CUL)) + +#define bFM_ADC2_ADSS01_TS0 *((volatile uint8_t *)(0x424E4580UL)) +#define bFM4_ADC2_ADSS01_TS0 *((volatile uint8_t *)(0x424E4580UL)) +#define bFM_ADC2_ADSS01_TS1 *((volatile uint8_t *)(0x424E4584UL)) +#define bFM4_ADC2_ADSS01_TS1 *((volatile uint8_t *)(0x424E4584UL)) +#define bFM_ADC2_ADSS01_TS2 *((volatile uint8_t *)(0x424E4588UL)) +#define bFM4_ADC2_ADSS01_TS2 *((volatile uint8_t *)(0x424E4588UL)) +#define bFM_ADC2_ADSS01_TS3 *((volatile uint8_t *)(0x424E458CUL)) +#define bFM4_ADC2_ADSS01_TS3 *((volatile uint8_t *)(0x424E458CUL)) +#define bFM_ADC2_ADSS01_TS4 *((volatile uint8_t *)(0x424E4590UL)) +#define bFM4_ADC2_ADSS01_TS4 *((volatile uint8_t *)(0x424E4590UL)) +#define bFM_ADC2_ADSS01_TS5 *((volatile uint8_t *)(0x424E4594UL)) +#define bFM4_ADC2_ADSS01_TS5 *((volatile uint8_t *)(0x424E4594UL)) +#define bFM_ADC2_ADSS01_TS6 *((volatile uint8_t *)(0x424E4598UL)) +#define bFM4_ADC2_ADSS01_TS6 *((volatile uint8_t *)(0x424E4598UL)) +#define bFM_ADC2_ADSS01_TS7 *((volatile uint8_t *)(0x424E459CUL)) +#define bFM4_ADC2_ADSS01_TS7 *((volatile uint8_t *)(0x424E459CUL)) +#define bFM_ADC2_ADSS01_TS8 *((volatile uint8_t *)(0x424E45A0UL)) +#define bFM4_ADC2_ADSS01_TS8 *((volatile uint8_t *)(0x424E45A0UL)) +#define bFM_ADC2_ADSS01_TS9 *((volatile uint8_t *)(0x424E45A4UL)) +#define bFM4_ADC2_ADSS01_TS9 *((volatile uint8_t *)(0x424E45A4UL)) +#define bFM_ADC2_ADSS01_TS10 *((volatile uint8_t *)(0x424E45A8UL)) +#define bFM4_ADC2_ADSS01_TS10 *((volatile uint8_t *)(0x424E45A8UL)) +#define bFM_ADC2_ADSS01_TS11 *((volatile uint8_t *)(0x424E45ACUL)) +#define bFM4_ADC2_ADSS01_TS11 *((volatile uint8_t *)(0x424E45ACUL)) +#define bFM_ADC2_ADSS01_TS12 *((volatile uint8_t *)(0x424E45B0UL)) +#define bFM4_ADC2_ADSS01_TS12 *((volatile uint8_t *)(0x424E45B0UL)) +#define bFM_ADC2_ADSS01_TS13 *((volatile uint8_t *)(0x424E45B4UL)) +#define bFM4_ADC2_ADSS01_TS13 *((volatile uint8_t *)(0x424E45B4UL)) +#define bFM_ADC2_ADSS01_TS14 *((volatile uint8_t *)(0x424E45B8UL)) +#define bFM4_ADC2_ADSS01_TS14 *((volatile uint8_t *)(0x424E45B8UL)) +#define bFM_ADC2_ADSS01_TS15 *((volatile uint8_t *)(0x424E45BCUL)) +#define bFM4_ADC2_ADSS01_TS15 *((volatile uint8_t *)(0x424E45BCUL)) + +#define bFM_ADC2_ADSS23_TS16 *((volatile uint8_t *)(0x424E4500UL)) +#define bFM4_ADC2_ADSS23_TS16 *((volatile uint8_t *)(0x424E4500UL)) +#define bFM_ADC2_ADSS23_TS17 *((volatile uint8_t *)(0x424E4504UL)) +#define bFM4_ADC2_ADSS23_TS17 *((volatile uint8_t *)(0x424E4504UL)) +#define bFM_ADC2_ADSS23_TS18 *((volatile uint8_t *)(0x424E4508UL)) +#define bFM4_ADC2_ADSS23_TS18 *((volatile uint8_t *)(0x424E4508UL)) +#define bFM_ADC2_ADSS23_TS19 *((volatile uint8_t *)(0x424E450CUL)) +#define bFM4_ADC2_ADSS23_TS19 *((volatile uint8_t *)(0x424E450CUL)) +#define bFM_ADC2_ADSS23_TS20 *((volatile uint8_t *)(0x424E4510UL)) +#define bFM4_ADC2_ADSS23_TS20 *((volatile uint8_t *)(0x424E4510UL)) +#define bFM_ADC2_ADSS23_TS21 *((volatile uint8_t *)(0x424E4514UL)) +#define bFM4_ADC2_ADSS23_TS21 *((volatile uint8_t *)(0x424E4514UL)) +#define bFM_ADC2_ADSS23_TS22 *((volatile uint8_t *)(0x424E4518UL)) +#define bFM4_ADC2_ADSS23_TS22 *((volatile uint8_t *)(0x424E4518UL)) +#define bFM_ADC2_ADSS23_TS23 *((volatile uint8_t *)(0x424E451CUL)) +#define bFM4_ADC2_ADSS23_TS23 *((volatile uint8_t *)(0x424E451CUL)) +#define bFM_ADC2_ADSS23_TS24 *((volatile uint8_t *)(0x424E4520UL)) +#define bFM4_ADC2_ADSS23_TS24 *((volatile uint8_t *)(0x424E4520UL)) +#define bFM_ADC2_ADSS23_TS25 *((volatile uint8_t *)(0x424E4524UL)) +#define bFM4_ADC2_ADSS23_TS25 *((volatile uint8_t *)(0x424E4524UL)) +#define bFM_ADC2_ADSS23_TS26 *((volatile uint8_t *)(0x424E4528UL)) +#define bFM4_ADC2_ADSS23_TS26 *((volatile uint8_t *)(0x424E4528UL)) +#define bFM_ADC2_ADSS23_TS27 *((volatile uint8_t *)(0x424E452CUL)) +#define bFM4_ADC2_ADSS23_TS27 *((volatile uint8_t *)(0x424E452CUL)) +#define bFM_ADC2_ADSS23_TS28 *((volatile uint8_t *)(0x424E4530UL)) +#define bFM4_ADC2_ADSS23_TS28 *((volatile uint8_t *)(0x424E4530UL)) +#define bFM_ADC2_ADSS23_TS29 *((volatile uint8_t *)(0x424E4534UL)) +#define bFM4_ADC2_ADSS23_TS29 *((volatile uint8_t *)(0x424E4534UL)) +#define bFM_ADC2_ADSS23_TS30 *((volatile uint8_t *)(0x424E4538UL)) +#define bFM4_ADC2_ADSS23_TS30 *((volatile uint8_t *)(0x424E4538UL)) +#define bFM_ADC2_ADSS23_TS31 *((volatile uint8_t *)(0x424E453CUL)) +#define bFM4_ADC2_ADSS23_TS31 *((volatile uint8_t *)(0x424E453CUL)) + +#define bFM_ADC2_CALSR_CLBEN *((volatile uint8_t *)(0x424E4820UL)) +#define bFM4_ADC2_CALSR_CLBEN *((volatile uint8_t *)(0x424E4820UL)) + +#define bFM_ADC2_CMPCR_CMD0 *((volatile uint8_t *)(0x424E4494UL)) +#define bFM4_ADC2_CMPCR_CMD0 *((volatile uint8_t *)(0x424E4494UL)) +#define bFM_ADC2_CMPCR_CMD1 *((volatile uint8_t *)(0x424E4498UL)) +#define bFM4_ADC2_CMPCR_CMD1 *((volatile uint8_t *)(0x424E4498UL)) +#define bFM_ADC2_CMPCR_CMPEN *((volatile uint8_t *)(0x424E449CUL)) +#define bFM4_ADC2_CMPCR_CMPEN *((volatile uint8_t *)(0x424E449CUL)) + +#define bFM_ADC2_PCCR_PSTR *((volatile uint8_t *)(0x424E4320UL)) +#define bFM4_ADC2_PCCR_PSTR *((volatile uint8_t *)(0x424E4320UL)) +#define bFM_ADC2_PCCR_PHEN *((volatile uint8_t *)(0x424E4324UL)) +#define bFM4_ADC2_PCCR_PHEN *((volatile uint8_t *)(0x424E4324UL)) +#define bFM_ADC2_PCCR_PEEN *((volatile uint8_t *)(0x424E4328UL)) +#define bFM4_ADC2_PCCR_PEEN *((volatile uint8_t *)(0x424E4328UL)) +#define bFM_ADC2_PCCR_ESCE *((volatile uint8_t *)(0x424E432CUL)) +#define bFM4_ADC2_PCCR_ESCE *((volatile uint8_t *)(0x424E432CUL)) +#define bFM_ADC2_PCCR_PFCLR *((volatile uint8_t *)(0x424E4330UL)) +#define bFM4_ADC2_PCCR_PFCLR *((volatile uint8_t *)(0x424E4330UL)) +#define bFM_ADC2_PCCR_POVR *((volatile uint8_t *)(0x424E4334UL)) +#define bFM4_ADC2_PCCR_POVR *((volatile uint8_t *)(0x424E4334UL)) +#define bFM_ADC2_PCCR_PFUL *((volatile uint8_t *)(0x424E4338UL)) +#define bFM4_ADC2_PCCR_PFUL *((volatile uint8_t *)(0x424E4338UL)) +#define bFM_ADC2_PCCR_PEMP *((volatile uint8_t *)(0x424E433CUL)) +#define bFM4_ADC2_PCCR_PEMP *((volatile uint8_t *)(0x424E433CUL)) + +#define bFM_ADC2_PCFD_INVL *((volatile uint8_t *)(0x424E43B0UL)) +#define bFM4_ADC2_PCFD_INVL *((volatile uint8_t *)(0x424E43B0UL)) + +#define bFM_ADC2_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E43B0UL)) +#define bFM4_ADC2_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E43B0UL)) + +#define bFM_ADC2_SCCR_SSTR *((volatile uint8_t *)(0x424E4120UL)) +#define bFM4_ADC2_SCCR_SSTR *((volatile uint8_t *)(0x424E4120UL)) +#define bFM_ADC2_SCCR_SHEN *((volatile uint8_t *)(0x424E4124UL)) +#define bFM4_ADC2_SCCR_SHEN *((volatile uint8_t *)(0x424E4124UL)) +#define bFM_ADC2_SCCR_RPT *((volatile uint8_t *)(0x424E4128UL)) +#define bFM4_ADC2_SCCR_RPT *((volatile uint8_t *)(0x424E4128UL)) +#define bFM_ADC2_SCCR_SFCLR *((volatile uint8_t *)(0x424E4130UL)) +#define bFM4_ADC2_SCCR_SFCLR *((volatile uint8_t *)(0x424E4130UL)) +#define bFM_ADC2_SCCR_SOVR *((volatile uint8_t *)(0x424E4134UL)) +#define bFM4_ADC2_SCCR_SOVR *((volatile uint8_t *)(0x424E4134UL)) +#define bFM_ADC2_SCCR_SFUL *((volatile uint8_t *)(0x424E4138UL)) +#define bFM4_ADC2_SCCR_SFUL *((volatile uint8_t *)(0x424E4138UL)) +#define bFM_ADC2_SCCR_SEMP *((volatile uint8_t *)(0x424E413CUL)) +#define bFM4_ADC2_SCCR_SEMP *((volatile uint8_t *)(0x424E413CUL)) + +#define bFM_ADC2_SCFD_INVL *((volatile uint8_t *)(0x424E41B0UL)) +#define bFM4_ADC2_SCFD_INVL *((volatile uint8_t *)(0x424E41B0UL)) + +#define bFM_ADC2_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E41B0UL)) +#define bFM4_ADC2_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E41B0UL)) + +#define bFM_ADC2_SCIS01_AN0 *((volatile uint8_t *)(0x424E4280UL)) +#define bFM4_ADC2_SCIS01_AN0 *((volatile uint8_t *)(0x424E4280UL)) +#define bFM_ADC2_SCIS01_AN1 *((volatile uint8_t *)(0x424E4284UL)) +#define bFM4_ADC2_SCIS01_AN1 *((volatile uint8_t *)(0x424E4284UL)) +#define bFM_ADC2_SCIS01_AN2 *((volatile uint8_t *)(0x424E4288UL)) +#define bFM4_ADC2_SCIS01_AN2 *((volatile uint8_t *)(0x424E4288UL)) +#define bFM_ADC2_SCIS01_AN3 *((volatile uint8_t *)(0x424E428CUL)) +#define bFM4_ADC2_SCIS01_AN3 *((volatile uint8_t *)(0x424E428CUL)) +#define bFM_ADC2_SCIS01_AN4 *((volatile uint8_t *)(0x424E4290UL)) +#define bFM4_ADC2_SCIS01_AN4 *((volatile uint8_t *)(0x424E4290UL)) +#define bFM_ADC2_SCIS01_AN5 *((volatile uint8_t *)(0x424E4294UL)) +#define bFM4_ADC2_SCIS01_AN5 *((volatile uint8_t *)(0x424E4294UL)) +#define bFM_ADC2_SCIS01_AN6 *((volatile uint8_t *)(0x424E4298UL)) +#define bFM4_ADC2_SCIS01_AN6 *((volatile uint8_t *)(0x424E4298UL)) +#define bFM_ADC2_SCIS01_AN7 *((volatile uint8_t *)(0x424E429CUL)) +#define bFM4_ADC2_SCIS01_AN7 *((volatile uint8_t *)(0x424E429CUL)) +#define bFM_ADC2_SCIS01_AN8 *((volatile uint8_t *)(0x424E42A0UL)) +#define bFM4_ADC2_SCIS01_AN8 *((volatile uint8_t *)(0x424E42A0UL)) +#define bFM_ADC2_SCIS01_AN9 *((volatile uint8_t *)(0x424E42A4UL)) +#define bFM4_ADC2_SCIS01_AN9 *((volatile uint8_t *)(0x424E42A4UL)) +#define bFM_ADC2_SCIS01_AN10 *((volatile uint8_t *)(0x424E42A8UL)) +#define bFM4_ADC2_SCIS01_AN10 *((volatile uint8_t *)(0x424E42A8UL)) +#define bFM_ADC2_SCIS01_AN11 *((volatile uint8_t *)(0x424E42ACUL)) +#define bFM4_ADC2_SCIS01_AN11 *((volatile uint8_t *)(0x424E42ACUL)) +#define bFM_ADC2_SCIS01_AN12 *((volatile uint8_t *)(0x424E42B0UL)) +#define bFM4_ADC2_SCIS01_AN12 *((volatile uint8_t *)(0x424E42B0UL)) +#define bFM_ADC2_SCIS01_AN13 *((volatile uint8_t *)(0x424E42B4UL)) +#define bFM4_ADC2_SCIS01_AN13 *((volatile uint8_t *)(0x424E42B4UL)) +#define bFM_ADC2_SCIS01_AN14 *((volatile uint8_t *)(0x424E42B8UL)) +#define bFM4_ADC2_SCIS01_AN14 *((volatile uint8_t *)(0x424E42B8UL)) +#define bFM_ADC2_SCIS01_AN15 *((volatile uint8_t *)(0x424E42BCUL)) +#define bFM4_ADC2_SCIS01_AN15 *((volatile uint8_t *)(0x424E42BCUL)) + +#define bFM_ADC2_SCIS23_AN16 *((volatile uint8_t *)(0x424E4200UL)) +#define bFM4_ADC2_SCIS23_AN16 *((volatile uint8_t *)(0x424E4200UL)) +#define bFM_ADC2_SCIS23_AN17 *((volatile uint8_t *)(0x424E4204UL)) +#define bFM4_ADC2_SCIS23_AN17 *((volatile uint8_t *)(0x424E4204UL)) +#define bFM_ADC2_SCIS23_AN18 *((volatile uint8_t *)(0x424E4208UL)) +#define bFM4_ADC2_SCIS23_AN18 *((volatile uint8_t *)(0x424E4208UL)) +#define bFM_ADC2_SCIS23_AN19 *((volatile uint8_t *)(0x424E420CUL)) +#define bFM4_ADC2_SCIS23_AN19 *((volatile uint8_t *)(0x424E420CUL)) +#define bFM_ADC2_SCIS23_AN20 *((volatile uint8_t *)(0x424E4210UL)) +#define bFM4_ADC2_SCIS23_AN20 *((volatile uint8_t *)(0x424E4210UL)) +#define bFM_ADC2_SCIS23_AN21 *((volatile uint8_t *)(0x424E4214UL)) +#define bFM4_ADC2_SCIS23_AN21 *((volatile uint8_t *)(0x424E4214UL)) +#define bFM_ADC2_SCIS23_AN22 *((volatile uint8_t *)(0x424E4218UL)) +#define bFM4_ADC2_SCIS23_AN22 *((volatile uint8_t *)(0x424E4218UL)) +#define bFM_ADC2_SCIS23_AN23 *((volatile uint8_t *)(0x424E421CUL)) +#define bFM4_ADC2_SCIS23_AN23 *((volatile uint8_t *)(0x424E421CUL)) +#define bFM_ADC2_SCIS23_AN24 *((volatile uint8_t *)(0x424E4220UL)) +#define bFM4_ADC2_SCIS23_AN24 *((volatile uint8_t *)(0x424E4220UL)) +#define bFM_ADC2_SCIS23_AN25 *((volatile uint8_t *)(0x424E4224UL)) +#define bFM4_ADC2_SCIS23_AN25 *((volatile uint8_t *)(0x424E4224UL)) +#define bFM_ADC2_SCIS23_AN26 *((volatile uint8_t *)(0x424E4228UL)) +#define bFM4_ADC2_SCIS23_AN26 *((volatile uint8_t *)(0x424E4228UL)) +#define bFM_ADC2_SCIS23_AN27 *((volatile uint8_t *)(0x424E422CUL)) +#define bFM4_ADC2_SCIS23_AN27 *((volatile uint8_t *)(0x424E422CUL)) +#define bFM_ADC2_SCIS23_AN28 *((volatile uint8_t *)(0x424E4230UL)) +#define bFM4_ADC2_SCIS23_AN28 *((volatile uint8_t *)(0x424E4230UL)) +#define bFM_ADC2_SCIS23_AN29 *((volatile uint8_t *)(0x424E4234UL)) +#define bFM4_ADC2_SCIS23_AN29 *((volatile uint8_t *)(0x424E4234UL)) +#define bFM_ADC2_SCIS23_AN30 *((volatile uint8_t *)(0x424E4238UL)) +#define bFM4_ADC2_SCIS23_AN30 *((volatile uint8_t *)(0x424E4238UL)) +#define bFM_ADC2_SCIS23_AN31 *((volatile uint8_t *)(0x424E423CUL)) +#define bFM4_ADC2_SCIS23_AN31 *((volatile uint8_t *)(0x424E423CUL)) + +#define bFM_ADC2_WCMPCR_RCOE *((volatile uint8_t *)(0x424E4988UL)) +#define bFM4_ADC2_WCMPCR_RCOE *((volatile uint8_t *)(0x424E4988UL)) +#define bFM_ADC2_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E498CUL)) +#define bFM4_ADC2_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E498CUL)) +#define bFM_ADC2_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E4990UL)) +#define bFM4_ADC2_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E4990UL)) + +#define bFM_ADC2_WCMPSR_WCMD *((volatile uint8_t *)(0x424E49B4UL)) +#define bFM4_ADC2_WCMPSR_WCMD *((volatile uint8_t *)(0x424E49B4UL)) + +#define bFM_ADC2_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E4900UL)) +#define bFM4_ADC2_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E4900UL)) + +#define bFM_ADC2_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E4880UL)) +#define bFM4_ADC2_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E4880UL)) + + +/******************************************************************************* +* BT Registers BT0 +* Bitband Section +*******************************************************************************/ +#define bFM_BT0_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) + +#define bFM_BT0_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM4_BT0_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM_BT0_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM4_BT0_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM_BT0_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM4_BT0_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM_BT0_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) +#define bFM4_BT0_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) + +#define bFM_BT0_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) + +#define bFM_BT0_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM_BT0_PWC_STC_ERR *((volatile uint8_t *)(0x424A021CUL)) +#define bFM4_BT0_PWC_STC_ERR *((volatile uint8_t *)(0x424A021CUL)) + +#define bFM_BT0_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) +#define bFM4_BT0_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) + +#define bFM_BT0_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) + +#define bFM_BT0_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0204UL)) +#define bFM4_BT0_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0204UL)) +#define bFM_BT0_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0214UL)) +#define bFM4_BT0_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0214UL)) +#define bFM_BT0_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) + +#define bFM_BT0_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM4_BT0_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM_BT0_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM4_BT0_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM_BT0_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM4_BT0_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM_BT0_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) +#define bFM4_BT0_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) + +#define bFM_BT0_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) + +#define bFM_BT0_RT_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_RT_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_RT_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_RT_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_RT_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_RT_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_RT_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_RT_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) + +#define bFM_BT0_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM4_BT0_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM_BT0_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM4_BT0_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM_BT0_RT_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) +#define bFM4_BT0_RT_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) + +#define bFM_BT0_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM_BT0_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A023CUL)) +#define bFM4_BT0_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A023CUL)) + + +/******************************************************************************* +* BT Registers BT1 +* Bitband Section +*******************************************************************************/ +#define bFM_BT1_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) + +#define bFM_BT1_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM4_BT1_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM_BT1_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM4_BT1_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM_BT1_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM4_BT1_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM_BT1_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) +#define bFM4_BT1_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) + +#define bFM_BT1_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) + +#define bFM_BT1_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM_BT1_PWC_STC_ERR *((volatile uint8_t *)(0x424A0A1CUL)) +#define bFM4_BT1_PWC_STC_ERR *((volatile uint8_t *)(0x424A0A1CUL)) + +#define bFM_BT1_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) +#define bFM4_BT1_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) + +#define bFM_BT1_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) + +#define bFM_BT1_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0A04UL)) +#define bFM4_BT1_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0A04UL)) +#define bFM_BT1_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0A14UL)) +#define bFM4_BT1_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0A14UL)) +#define bFM_BT1_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) + +#define bFM_BT1_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM4_BT1_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM_BT1_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM4_BT1_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM_BT1_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM4_BT1_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM_BT1_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) +#define bFM4_BT1_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) + +#define bFM_BT1_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) + +#define bFM_BT1_RT_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_RT_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_RT_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_RT_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_RT_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_RT_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_RT_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_RT_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) + +#define bFM_BT1_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM4_BT1_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM_BT1_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM4_BT1_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM_BT1_RT_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) +#define bFM4_BT1_RT_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) + +#define bFM_BT1_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM_BT1_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A0A3CUL)) +#define bFM4_BT1_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A0A3CUL)) + + +/******************************************************************************* +* BT Registers BT10 +* Bitband Section +*******************************************************************************/ +#define bFM_BT10_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) + +#define bFM_BT10_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM4_BT10_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM_BT10_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM4_BT10_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM_BT10_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM4_BT10_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM_BT10_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) +#define bFM4_BT10_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) + +#define bFM_BT10_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) + +#define bFM_BT10_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM_BT10_PWC_STC_ERR *((volatile uint8_t *)(0x424A921CUL)) +#define bFM4_BT10_PWC_STC_ERR *((volatile uint8_t *)(0x424A921CUL)) + +#define bFM_BT10_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) +#define bFM4_BT10_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) + +#define bFM_BT10_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) + +#define bFM_BT10_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9204UL)) +#define bFM4_BT10_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9204UL)) +#define bFM_BT10_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9214UL)) +#define bFM4_BT10_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9214UL)) +#define bFM_BT10_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) + +#define bFM_BT10_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM4_BT10_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM_BT10_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM4_BT10_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM_BT10_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM4_BT10_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM_BT10_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) +#define bFM4_BT10_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) + +#define bFM_BT10_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) + +#define bFM_BT10_RT_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_RT_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_RT_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_RT_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_RT_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_RT_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_RT_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_RT_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) + +#define bFM_BT10_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM4_BT10_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM_BT10_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM4_BT10_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM_BT10_RT_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) +#define bFM4_BT10_RT_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) + +#define bFM_BT10_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM_BT10_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A923CUL)) +#define bFM4_BT10_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A923CUL)) + + +/******************************************************************************* +* BT Registers BT11 +* Bitband Section +*******************************************************************************/ +#define bFM_BT11_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) + +#define bFM_BT11_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM4_BT11_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM_BT11_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM4_BT11_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM_BT11_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM4_BT11_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM_BT11_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) +#define bFM4_BT11_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) + +#define bFM_BT11_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) + +#define bFM_BT11_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM_BT11_PWC_STC_ERR *((volatile uint8_t *)(0x424A9A1CUL)) +#define bFM4_BT11_PWC_STC_ERR *((volatile uint8_t *)(0x424A9A1CUL)) + +#define bFM_BT11_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) +#define bFM4_BT11_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) + +#define bFM_BT11_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) + +#define bFM_BT11_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9A04UL)) +#define bFM4_BT11_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9A04UL)) +#define bFM_BT11_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9A14UL)) +#define bFM4_BT11_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9A14UL)) +#define bFM_BT11_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) + +#define bFM_BT11_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM4_BT11_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM_BT11_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM4_BT11_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM_BT11_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM4_BT11_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM_BT11_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) +#define bFM4_BT11_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) + +#define bFM_BT11_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) + +#define bFM_BT11_RT_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_RT_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_RT_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_RT_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_RT_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_RT_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_RT_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_RT_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) + +#define bFM_BT11_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM4_BT11_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM_BT11_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM4_BT11_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM_BT11_RT_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) +#define bFM4_BT11_RT_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) + +#define bFM_BT11_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM_BT11_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A9A3CUL)) +#define bFM4_BT11_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A9A3CUL)) + + +/******************************************************************************* +* BT Registers BT12 +* Bitband Section +*******************************************************************************/ +#define bFM_BT12_PPG_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_PPG_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_PPG_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_PPG_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_PPG_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_PPG_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_PPG_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_PPG_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) + +#define bFM_BT12_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM4_BT12_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM_BT12_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM4_BT12_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM_BT12_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM4_BT12_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM_BT12_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) +#define bFM4_BT12_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) + +#define bFM_BT12_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) + +#define bFM_BT12_PWC_STC_OVIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_PWC_STC_OVIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_PWC_STC_EDIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_PWC_STC_EDIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_PWC_STC_OVIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_PWC_STC_OVIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_PWC_STC_EDIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_PWC_STC_EDIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM_BT12_PWC_STC_ERR *((volatile uint8_t *)(0x424AC21CUL)) +#define bFM4_BT12_PWC_STC_ERR *((volatile uint8_t *)(0x424AC21CUL)) + +#define bFM_BT12_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) +#define bFM4_BT12_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) + +#define bFM_BT12_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) + +#define bFM_BT12_PWM_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_PWM_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_PWM_STC_DTIR *((volatile uint8_t *)(0x424AC204UL)) +#define bFM4_BT12_PWM_STC_DTIR *((volatile uint8_t *)(0x424AC204UL)) +#define bFM_BT12_PWM_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_PWM_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_PWM_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_PWM_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_PWM_STC_DTIE *((volatile uint8_t *)(0x424AC214UL)) +#define bFM4_BT12_PWM_STC_DTIE *((volatile uint8_t *)(0x424AC214UL)) +#define bFM_BT12_PWM_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_PWM_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) + +#define bFM_BT12_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM4_BT12_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM_BT12_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM4_BT12_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM_BT12_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM4_BT12_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM_BT12_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) +#define bFM4_BT12_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) + +#define bFM_BT12_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) + +#define bFM_BT12_RT_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_RT_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_RT_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_RT_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_RT_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_RT_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_RT_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_RT_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) + +#define bFM_BT12_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM4_BT12_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM_BT12_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM4_BT12_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM_BT12_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) +#define bFM4_BT12_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) + +#define bFM_BT12_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM_BT12_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AC23CUL)) +#define bFM4_BT12_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AC23CUL)) + + +/******************************************************************************* +* BT Registers BT13 +* Bitband Section +*******************************************************************************/ +#define bFM_BT13_PPG_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_PPG_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_PPG_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_PPG_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_PPG_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_PPG_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_PPG_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_PPG_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) + +#define bFM_BT13_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM4_BT13_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM_BT13_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM4_BT13_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM_BT13_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM4_BT13_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM_BT13_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) +#define bFM4_BT13_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) + +#define bFM_BT13_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) + +#define bFM_BT13_PWC_STC_OVIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_PWC_STC_OVIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_PWC_STC_EDIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_PWC_STC_EDIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_PWC_STC_OVIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_PWC_STC_OVIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_PWC_STC_EDIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_PWC_STC_EDIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM_BT13_PWC_STC_ERR *((volatile uint8_t *)(0x424ACA1CUL)) +#define bFM4_BT13_PWC_STC_ERR *((volatile uint8_t *)(0x424ACA1CUL)) + +#define bFM_BT13_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) +#define bFM4_BT13_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) + +#define bFM_BT13_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) + +#define bFM_BT13_PWM_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_PWM_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_PWM_STC_DTIR *((volatile uint8_t *)(0x424ACA04UL)) +#define bFM4_BT13_PWM_STC_DTIR *((volatile uint8_t *)(0x424ACA04UL)) +#define bFM_BT13_PWM_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_PWM_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_PWM_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_PWM_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_PWM_STC_DTIE *((volatile uint8_t *)(0x424ACA14UL)) +#define bFM4_BT13_PWM_STC_DTIE *((volatile uint8_t *)(0x424ACA14UL)) +#define bFM_BT13_PWM_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_PWM_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) + +#define bFM_BT13_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM4_BT13_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM_BT13_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM4_BT13_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM_BT13_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM4_BT13_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM_BT13_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) +#define bFM4_BT13_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) + +#define bFM_BT13_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) + +#define bFM_BT13_RT_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_RT_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_RT_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_RT_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_RT_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_RT_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_RT_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_RT_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) + +#define bFM_BT13_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM4_BT13_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM_BT13_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM4_BT13_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM_BT13_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) +#define bFM4_BT13_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) + +#define bFM_BT13_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM_BT13_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ACA3CUL)) +#define bFM4_BT13_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ACA3CUL)) + + +/******************************************************************************* +* BT Registers BT14 +* Bitband Section +*******************************************************************************/ +#define bFM_BT14_PPG_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_PPG_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_PPG_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_PPG_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_PPG_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_PPG_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_PPG_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_PPG_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) + +#define bFM_BT14_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM4_BT14_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM_BT14_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM4_BT14_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM_BT14_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM4_BT14_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM_BT14_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) +#define bFM4_BT14_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) + +#define bFM_BT14_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) + +#define bFM_BT14_PWC_STC_OVIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_PWC_STC_OVIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_PWC_STC_EDIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_PWC_STC_EDIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_PWC_STC_OVIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_PWC_STC_OVIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_PWC_STC_EDIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_PWC_STC_EDIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM_BT14_PWC_STC_ERR *((volatile uint8_t *)(0x424AD21CUL)) +#define bFM4_BT14_PWC_STC_ERR *((volatile uint8_t *)(0x424AD21CUL)) + +#define bFM_BT14_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) +#define bFM4_BT14_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) + +#define bFM_BT14_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) + +#define bFM_BT14_PWM_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_PWM_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_PWM_STC_DTIR *((volatile uint8_t *)(0x424AD204UL)) +#define bFM4_BT14_PWM_STC_DTIR *((volatile uint8_t *)(0x424AD204UL)) +#define bFM_BT14_PWM_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_PWM_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_PWM_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_PWM_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_PWM_STC_DTIE *((volatile uint8_t *)(0x424AD214UL)) +#define bFM4_BT14_PWM_STC_DTIE *((volatile uint8_t *)(0x424AD214UL)) +#define bFM_BT14_PWM_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_PWM_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) + +#define bFM_BT14_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM4_BT14_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM_BT14_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM4_BT14_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM_BT14_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM4_BT14_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM_BT14_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) +#define bFM4_BT14_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) + +#define bFM_BT14_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) + +#define bFM_BT14_RT_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_RT_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_RT_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_RT_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_RT_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_RT_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_RT_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_RT_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) + +#define bFM_BT14_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM4_BT14_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM_BT14_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM4_BT14_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM_BT14_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) +#define bFM4_BT14_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) + +#define bFM_BT14_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM_BT14_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AD23CUL)) +#define bFM4_BT14_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AD23CUL)) + + +/******************************************************************************* +* BT Registers BT15 +* Bitband Section +*******************************************************************************/ +#define bFM_BT15_PPG_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_PPG_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_PPG_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_PPG_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_PPG_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_PPG_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_PPG_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_PPG_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) + +#define bFM_BT15_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM4_BT15_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM_BT15_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM4_BT15_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM_BT15_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM4_BT15_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM_BT15_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) +#define bFM4_BT15_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) + +#define bFM_BT15_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) + +#define bFM_BT15_PWC_STC_OVIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_PWC_STC_OVIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_PWC_STC_EDIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_PWC_STC_EDIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_PWC_STC_OVIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_PWC_STC_OVIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_PWC_STC_EDIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_PWC_STC_EDIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM_BT15_PWC_STC_ERR *((volatile uint8_t *)(0x424ADA1CUL)) +#define bFM4_BT15_PWC_STC_ERR *((volatile uint8_t *)(0x424ADA1CUL)) + +#define bFM_BT15_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) +#define bFM4_BT15_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) + +#define bFM_BT15_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) + +#define bFM_BT15_PWM_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_PWM_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_PWM_STC_DTIR *((volatile uint8_t *)(0x424ADA04UL)) +#define bFM4_BT15_PWM_STC_DTIR *((volatile uint8_t *)(0x424ADA04UL)) +#define bFM_BT15_PWM_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_PWM_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_PWM_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_PWM_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_PWM_STC_DTIE *((volatile uint8_t *)(0x424ADA14UL)) +#define bFM4_BT15_PWM_STC_DTIE *((volatile uint8_t *)(0x424ADA14UL)) +#define bFM_BT15_PWM_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_PWM_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) + +#define bFM_BT15_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM4_BT15_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM_BT15_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM4_BT15_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM_BT15_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM4_BT15_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM_BT15_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) +#define bFM4_BT15_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) + +#define bFM_BT15_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) + +#define bFM_BT15_RT_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_RT_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_RT_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_RT_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_RT_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_RT_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_RT_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_RT_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) + +#define bFM_BT15_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM4_BT15_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM_BT15_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM4_BT15_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM_BT15_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) +#define bFM4_BT15_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) + +#define bFM_BT15_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM_BT15_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ADA3CUL)) +#define bFM4_BT15_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ADA3CUL)) + + +/******************************************************************************* +* BT Registers BT2 +* Bitband Section +*******************************************************************************/ +#define bFM_BT2_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) + +#define bFM_BT2_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM4_BT2_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM_BT2_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM4_BT2_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM_BT2_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM4_BT2_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM_BT2_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) +#define bFM4_BT2_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) + +#define bFM_BT2_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) + +#define bFM_BT2_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM_BT2_PWC_STC_ERR *((volatile uint8_t *)(0x424A121CUL)) +#define bFM4_BT2_PWC_STC_ERR *((volatile uint8_t *)(0x424A121CUL)) + +#define bFM_BT2_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) +#define bFM4_BT2_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) + +#define bFM_BT2_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) + +#define bFM_BT2_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1204UL)) +#define bFM4_BT2_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1204UL)) +#define bFM_BT2_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1214UL)) +#define bFM4_BT2_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1214UL)) +#define bFM_BT2_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) + +#define bFM_BT2_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM4_BT2_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM_BT2_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM4_BT2_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM_BT2_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM4_BT2_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM_BT2_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) +#define bFM4_BT2_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) + +#define bFM_BT2_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) + +#define bFM_BT2_RT_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_RT_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_RT_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_RT_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_RT_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_RT_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_RT_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_RT_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) + +#define bFM_BT2_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM4_BT2_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM_BT2_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM4_BT2_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM_BT2_RT_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) +#define bFM4_BT2_RT_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) + +#define bFM_BT2_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM_BT2_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A123CUL)) +#define bFM4_BT2_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A123CUL)) + + +/******************************************************************************* +* BT Registers BT3 +* Bitband Section +*******************************************************************************/ +#define bFM_BT3_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) + +#define bFM_BT3_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM4_BT3_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM_BT3_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM4_BT3_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM_BT3_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM4_BT3_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM_BT3_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) +#define bFM4_BT3_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) + +#define bFM_BT3_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) + +#define bFM_BT3_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM_BT3_PWC_STC_ERR *((volatile uint8_t *)(0x424A1A1CUL)) +#define bFM4_BT3_PWC_STC_ERR *((volatile uint8_t *)(0x424A1A1CUL)) + +#define bFM_BT3_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) +#define bFM4_BT3_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) + +#define bFM_BT3_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) + +#define bFM_BT3_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1A04UL)) +#define bFM4_BT3_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1A04UL)) +#define bFM_BT3_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1A14UL)) +#define bFM4_BT3_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1A14UL)) +#define bFM_BT3_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) + +#define bFM_BT3_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM4_BT3_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM_BT3_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM4_BT3_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM_BT3_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM4_BT3_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM_BT3_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) +#define bFM4_BT3_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) + +#define bFM_BT3_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) + +#define bFM_BT3_RT_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_RT_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_RT_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_RT_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_RT_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_RT_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_RT_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_RT_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) + +#define bFM_BT3_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM4_BT3_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM_BT3_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM4_BT3_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM_BT3_RT_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) +#define bFM4_BT3_RT_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) + +#define bFM_BT3_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM_BT3_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A1A3CUL)) +#define bFM4_BT3_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A1A3CUL)) + + +/******************************************************************************* +* BT Registers BT4 +* Bitband Section +*******************************************************************************/ +#define bFM_BT4_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) + +#define bFM_BT4_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM4_BT4_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM_BT4_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM4_BT4_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM_BT4_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM4_BT4_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM_BT4_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) +#define bFM4_BT4_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) + +#define bFM_BT4_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) + +#define bFM_BT4_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM_BT4_PWC_STC_ERR *((volatile uint8_t *)(0x424A421CUL)) +#define bFM4_BT4_PWC_STC_ERR *((volatile uint8_t *)(0x424A421CUL)) + +#define bFM_BT4_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) +#define bFM4_BT4_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) + +#define bFM_BT4_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) + +#define bFM_BT4_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4204UL)) +#define bFM4_BT4_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4204UL)) +#define bFM_BT4_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4214UL)) +#define bFM4_BT4_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4214UL)) +#define bFM_BT4_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) + +#define bFM_BT4_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM4_BT4_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM_BT4_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM4_BT4_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM_BT4_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM4_BT4_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM_BT4_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) +#define bFM4_BT4_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) + +#define bFM_BT4_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) + +#define bFM_BT4_RT_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_RT_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_RT_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_RT_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_RT_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_RT_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_RT_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_RT_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) + +#define bFM_BT4_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM4_BT4_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM_BT4_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM4_BT4_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM_BT4_RT_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) +#define bFM4_BT4_RT_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) + +#define bFM_BT4_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM_BT4_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A423CUL)) +#define bFM4_BT4_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A423CUL)) + + +/******************************************************************************* +* BT Registers BT5 +* Bitband Section +*******************************************************************************/ +#define bFM_BT5_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) + +#define bFM_BT5_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM4_BT5_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM_BT5_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM4_BT5_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM_BT5_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM4_BT5_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM_BT5_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) +#define bFM4_BT5_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) + +#define bFM_BT5_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) + +#define bFM_BT5_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM_BT5_PWC_STC_ERR *((volatile uint8_t *)(0x424A4A1CUL)) +#define bFM4_BT5_PWC_STC_ERR *((volatile uint8_t *)(0x424A4A1CUL)) + +#define bFM_BT5_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) +#define bFM4_BT5_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) + +#define bFM_BT5_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) + +#define bFM_BT5_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4A04UL)) +#define bFM4_BT5_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4A04UL)) +#define bFM_BT5_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4A14UL)) +#define bFM4_BT5_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4A14UL)) +#define bFM_BT5_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) + +#define bFM_BT5_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM4_BT5_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM_BT5_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM4_BT5_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM_BT5_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM4_BT5_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM_BT5_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) +#define bFM4_BT5_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) + +#define bFM_BT5_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) + +#define bFM_BT5_RT_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_RT_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_RT_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_RT_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_RT_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_RT_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_RT_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_RT_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) + +#define bFM_BT5_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM4_BT5_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM_BT5_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM4_BT5_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM_BT5_RT_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) +#define bFM4_BT5_RT_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) + +#define bFM_BT5_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM_BT5_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A4A3CUL)) +#define bFM4_BT5_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A4A3CUL)) + + +/******************************************************************************* +* BT Registers BT6 +* Bitband Section +*******************************************************************************/ +#define bFM_BT6_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) + +#define bFM_BT6_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM4_BT6_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM_BT6_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM4_BT6_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM_BT6_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM4_BT6_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM_BT6_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) +#define bFM4_BT6_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) + +#define bFM_BT6_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) + +#define bFM_BT6_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM_BT6_PWC_STC_ERR *((volatile uint8_t *)(0x424A521CUL)) +#define bFM4_BT6_PWC_STC_ERR *((volatile uint8_t *)(0x424A521CUL)) + +#define bFM_BT6_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) +#define bFM4_BT6_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) + +#define bFM_BT6_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) + +#define bFM_BT6_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5204UL)) +#define bFM4_BT6_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5204UL)) +#define bFM_BT6_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5214UL)) +#define bFM4_BT6_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5214UL)) +#define bFM_BT6_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) + +#define bFM_BT6_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM4_BT6_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM_BT6_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM4_BT6_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM_BT6_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM4_BT6_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM_BT6_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) +#define bFM4_BT6_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) + +#define bFM_BT6_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) + +#define bFM_BT6_RT_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_RT_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_RT_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_RT_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_RT_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_RT_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_RT_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_RT_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) + +#define bFM_BT6_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM4_BT6_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM_BT6_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM4_BT6_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM_BT6_RT_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) +#define bFM4_BT6_RT_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) + +#define bFM_BT6_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM_BT6_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A523CUL)) +#define bFM4_BT6_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A523CUL)) + + +/******************************************************************************* +* BT Registers BT7 +* Bitband Section +*******************************************************************************/ +#define bFM_BT7_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) + +#define bFM_BT7_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM4_BT7_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM_BT7_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM4_BT7_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM_BT7_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM4_BT7_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM_BT7_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) +#define bFM4_BT7_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) + +#define bFM_BT7_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) + +#define bFM_BT7_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM_BT7_PWC_STC_ERR *((volatile uint8_t *)(0x424A5A1CUL)) +#define bFM4_BT7_PWC_STC_ERR *((volatile uint8_t *)(0x424A5A1CUL)) + +#define bFM_BT7_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) +#define bFM4_BT7_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) + +#define bFM_BT7_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) + +#define bFM_BT7_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5A04UL)) +#define bFM4_BT7_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5A04UL)) +#define bFM_BT7_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5A14UL)) +#define bFM4_BT7_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5A14UL)) +#define bFM_BT7_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) + +#define bFM_BT7_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM4_BT7_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM_BT7_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM4_BT7_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM_BT7_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM4_BT7_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM_BT7_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) +#define bFM4_BT7_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) + +#define bFM_BT7_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) + +#define bFM_BT7_RT_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_RT_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_RT_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_RT_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_RT_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_RT_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_RT_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_RT_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) + +#define bFM_BT7_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM4_BT7_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM_BT7_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM4_BT7_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM_BT7_RT_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) +#define bFM4_BT7_RT_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) + +#define bFM_BT7_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM_BT7_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A5A3CUL)) +#define bFM4_BT7_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A5A3CUL)) + + +/******************************************************************************* +* BT Registers BT8 +* Bitband Section +*******************************************************************************/ +#define bFM_BT8_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) + +#define bFM_BT8_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM4_BT8_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM_BT8_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM4_BT8_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM_BT8_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM4_BT8_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM_BT8_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) +#define bFM4_BT8_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) + +#define bFM_BT8_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) + +#define bFM_BT8_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM_BT8_PWC_STC_ERR *((volatile uint8_t *)(0x424A821CUL)) +#define bFM4_BT8_PWC_STC_ERR *((volatile uint8_t *)(0x424A821CUL)) + +#define bFM_BT8_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) +#define bFM4_BT8_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) + +#define bFM_BT8_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) + +#define bFM_BT8_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8204UL)) +#define bFM4_BT8_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8204UL)) +#define bFM_BT8_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8214UL)) +#define bFM4_BT8_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8214UL)) +#define bFM_BT8_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) + +#define bFM_BT8_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM4_BT8_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM_BT8_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM4_BT8_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM_BT8_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM4_BT8_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM_BT8_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) +#define bFM4_BT8_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) + +#define bFM_BT8_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) + +#define bFM_BT8_RT_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_RT_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_RT_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_RT_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_RT_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_RT_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_RT_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_RT_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) + +#define bFM_BT8_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM4_BT8_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM_BT8_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM4_BT8_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM_BT8_RT_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) +#define bFM4_BT8_RT_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) + +#define bFM_BT8_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM_BT8_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A823CUL)) +#define bFM4_BT8_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A823CUL)) + + +/******************************************************************************* +* BT Registers BT9 +* Bitband Section +*******************************************************************************/ +#define bFM_BT9_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) + +#define bFM_BT9_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM4_BT9_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM_BT9_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM4_BT9_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM_BT9_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM4_BT9_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM_BT9_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) +#define bFM4_BT9_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) + +#define bFM_BT9_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) + +#define bFM_BT9_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM_BT9_PWC_STC_ERR *((volatile uint8_t *)(0x424A8A1CUL)) +#define bFM4_BT9_PWC_STC_ERR *((volatile uint8_t *)(0x424A8A1CUL)) + +#define bFM_BT9_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) +#define bFM4_BT9_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) + +#define bFM_BT9_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) + +#define bFM_BT9_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8A04UL)) +#define bFM4_BT9_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8A04UL)) +#define bFM_BT9_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8A14UL)) +#define bFM4_BT9_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8A14UL)) +#define bFM_BT9_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) + +#define bFM_BT9_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM4_BT9_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM_BT9_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM4_BT9_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM_BT9_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM4_BT9_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM_BT9_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) +#define bFM4_BT9_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) + +#define bFM_BT9_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) + +#define bFM_BT9_RT_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_RT_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_RT_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_RT_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_RT_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_RT_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_RT_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_RT_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) + +#define bFM_BT9_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM4_BT9_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM_BT9_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM4_BT9_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM_BT9_RT_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) +#define bFM4_BT9_RT_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) + +#define bFM_BT9_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM_BT9_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A8A3CUL)) +#define bFM4_BT9_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A8A3CUL)) + + +/******************************************************************************* +* BTIOSEL03 Registers BTIOSEL03 +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* BTIOSEL47 Registers BTIOSEL47 +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* BTIOSEL8B Registers BTIOSEL8B +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* BTIOSELCF Registers BTIOSELCF +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* CAN Registers CAN0 +* Bitband Section +*******************************************************************************/ +#define bFM_CAN0_CTRLR_INIT *((volatile uint8_t *)(0x42C40000UL)) +#define bFM4_CAN0_CTRLR_INIT *((volatile uint8_t *)(0x42C40000UL)) +#define bFM_CAN0_CTRLR_IE *((volatile uint8_t *)(0x42C40004UL)) +#define bFM4_CAN0_CTRLR_IE *((volatile uint8_t *)(0x42C40004UL)) +#define bFM_CAN0_CTRLR_SIE *((volatile uint8_t *)(0x42C40008UL)) +#define bFM4_CAN0_CTRLR_SIE *((volatile uint8_t *)(0x42C40008UL)) +#define bFM_CAN0_CTRLR_EIE *((volatile uint8_t *)(0x42C4000CUL)) +#define bFM4_CAN0_CTRLR_EIE *((volatile uint8_t *)(0x42C4000CUL)) +#define bFM_CAN0_CTRLR_DAR *((volatile uint8_t *)(0x42C40014UL)) +#define bFM4_CAN0_CTRLR_DAR *((volatile uint8_t *)(0x42C40014UL)) +#define bFM_CAN0_CTRLR_CCE *((volatile uint8_t *)(0x42C40018UL)) +#define bFM4_CAN0_CTRLR_CCE *((volatile uint8_t *)(0x42C40018UL)) +#define bFM_CAN0_CTRLR_TEST *((volatile uint8_t *)(0x42C4001CUL)) +#define bFM4_CAN0_CTRLR_TEST *((volatile uint8_t *)(0x42C4001CUL)) + +#define bFM_CAN0_ERRCNT_RP *((volatile uint8_t *)(0x42C400BCUL)) +#define bFM4_CAN0_ERRCNT_RP *((volatile uint8_t *)(0x42C400BCUL)) + +#define bFM_CAN0_IF1ARB_DIR *((volatile uint8_t *)(0x42C40374UL)) +#define bFM4_CAN0_IF1ARB_DIR *((volatile uint8_t *)(0x42C40374UL)) +#define bFM_CAN0_IF1ARB_XTD *((volatile uint8_t *)(0x42C40378UL)) +#define bFM4_CAN0_IF1ARB_XTD *((volatile uint8_t *)(0x42C40378UL)) +#define bFM_CAN0_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C4037CUL)) +#define bFM4_CAN0_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C4037CUL)) + +#define bFM_CAN0_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C40240UL)) +#define bFM4_CAN0_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C40240UL)) +#define bFM_CAN0_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C40244UL)) +#define bFM4_CAN0_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C40244UL)) +#define bFM_CAN0_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C40248UL)) +#define bFM4_CAN0_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C40248UL)) +#define bFM_CAN0_IF1CMSK_CIP *((volatile uint8_t *)(0x42C4024CUL)) +#define bFM4_CAN0_IF1CMSK_CIP *((volatile uint8_t *)(0x42C4024CUL)) +#define bFM_CAN0_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C40250UL)) +#define bFM4_CAN0_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C40250UL)) +#define bFM_CAN0_IF1CMSK_ARB *((volatile uint8_t *)(0x42C40254UL)) +#define bFM4_CAN0_IF1CMSK_ARB *((volatile uint8_t *)(0x42C40254UL)) +#define bFM_CAN0_IF1CMSK_MASK *((volatile uint8_t *)(0x42C40258UL)) +#define bFM4_CAN0_IF1CMSK_MASK *((volatile uint8_t *)(0x42C40258UL)) +#define bFM_CAN0_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C4025CUL)) +#define bFM4_CAN0_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C4025CUL)) + +#define bFM_CAN0_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C4023CUL)) +#define bFM4_CAN0_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C4023CUL)) + +#define bFM_CAN0_IF1MCTR_EOB *((volatile uint8_t *)(0x42C4039CUL)) +#define bFM4_CAN0_IF1MCTR_EOB *((volatile uint8_t *)(0x42C4039CUL)) +#define bFM_CAN0_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C403A0UL)) +#define bFM4_CAN0_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C403A0UL)) +#define bFM_CAN0_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C403A4UL)) +#define bFM4_CAN0_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C403A4UL)) +#define bFM_CAN0_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C403A8UL)) +#define bFM4_CAN0_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C403A8UL)) +#define bFM_CAN0_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C403ACUL)) +#define bFM4_CAN0_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C403ACUL)) +#define bFM_CAN0_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C403B0UL)) +#define bFM4_CAN0_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C403B0UL)) +#define bFM_CAN0_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C403B4UL)) +#define bFM4_CAN0_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C403B4UL)) +#define bFM_CAN0_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C403B8UL)) +#define bFM4_CAN0_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C403B8UL)) +#define bFM_CAN0_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C403BCUL)) +#define bFM4_CAN0_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C403BCUL)) + +#define bFM_CAN0_IF1MSK_MDIR *((volatile uint8_t *)(0x42C402F8UL)) +#define bFM4_CAN0_IF1MSK_MDIR *((volatile uint8_t *)(0x42C402F8UL)) +#define bFM_CAN0_IF1MSK_MXTD *((volatile uint8_t *)(0x42C402FCUL)) +#define bFM4_CAN0_IF1MSK_MXTD *((volatile uint8_t *)(0x42C402FCUL)) + +#define bFM_CAN0_IF2ARB_DIR *((volatile uint8_t *)(0x42C40974UL)) +#define bFM4_CAN0_IF2ARB_DIR *((volatile uint8_t *)(0x42C40974UL)) +#define bFM_CAN0_IF2ARB_XTD *((volatile uint8_t *)(0x42C40978UL)) +#define bFM4_CAN0_IF2ARB_XTD *((volatile uint8_t *)(0x42C40978UL)) +#define bFM_CAN0_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C4097CUL)) +#define bFM4_CAN0_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C4097CUL)) + +#define bFM_CAN0_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C40840UL)) +#define bFM4_CAN0_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C40840UL)) +#define bFM_CAN0_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C40844UL)) +#define bFM4_CAN0_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C40844UL)) +#define bFM_CAN0_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C40848UL)) +#define bFM4_CAN0_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C40848UL)) +#define bFM_CAN0_IF2CMSK_CIP *((volatile uint8_t *)(0x42C4084CUL)) +#define bFM4_CAN0_IF2CMSK_CIP *((volatile uint8_t *)(0x42C4084CUL)) +#define bFM_CAN0_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C40850UL)) +#define bFM4_CAN0_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C40850UL)) +#define bFM_CAN0_IF2CMSK_ARB *((volatile uint8_t *)(0x42C40854UL)) +#define bFM4_CAN0_IF2CMSK_ARB *((volatile uint8_t *)(0x42C40854UL)) +#define bFM_CAN0_IF2CMSK_MASK *((volatile uint8_t *)(0x42C40858UL)) +#define bFM4_CAN0_IF2CMSK_MASK *((volatile uint8_t *)(0x42C40858UL)) +#define bFM_CAN0_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C4085CUL)) +#define bFM4_CAN0_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C4085CUL)) + +#define bFM_CAN0_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C4083CUL)) +#define bFM4_CAN0_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C4083CUL)) + +#define bFM_CAN0_IF2MCTR_EOB *((volatile uint8_t *)(0x42C4099CUL)) +#define bFM4_CAN0_IF2MCTR_EOB *((volatile uint8_t *)(0x42C4099CUL)) +#define bFM_CAN0_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C409A0UL)) +#define bFM4_CAN0_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C409A0UL)) +#define bFM_CAN0_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C409A4UL)) +#define bFM4_CAN0_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C409A4UL)) +#define bFM_CAN0_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C409A8UL)) +#define bFM4_CAN0_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C409A8UL)) +#define bFM_CAN0_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C409ACUL)) +#define bFM4_CAN0_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C409ACUL)) +#define bFM_CAN0_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C409B0UL)) +#define bFM4_CAN0_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C409B0UL)) +#define bFM_CAN0_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C409B4UL)) +#define bFM4_CAN0_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C409B4UL)) +#define bFM_CAN0_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C409B8UL)) +#define bFM4_CAN0_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C409B8UL)) +#define bFM_CAN0_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C409BCUL)) +#define bFM4_CAN0_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C409BCUL)) + +#define bFM_CAN0_IF2MSK_MDIR *((volatile uint8_t *)(0x42C408F8UL)) +#define bFM4_CAN0_IF2MSK_MDIR *((volatile uint8_t *)(0x42C408F8UL)) +#define bFM_CAN0_IF2MSK_MXTD *((volatile uint8_t *)(0x42C408FCUL)) +#define bFM4_CAN0_IF2MSK_MXTD *((volatile uint8_t *)(0x42C408FCUL)) + +#define bFM_CAN0_INTPND_INTPND1 *((volatile uint8_t *)(0x42C41400UL)) +#define bFM4_CAN0_INTPND_INTPND1 *((volatile uint8_t *)(0x42C41400UL)) +#define bFM_CAN0_INTPND_INTPND2 *((volatile uint8_t *)(0x42C41404UL)) +#define bFM4_CAN0_INTPND_INTPND2 *((volatile uint8_t *)(0x42C41404UL)) +#define bFM_CAN0_INTPND_INTPND3 *((volatile uint8_t *)(0x42C41408UL)) +#define bFM4_CAN0_INTPND_INTPND3 *((volatile uint8_t *)(0x42C41408UL)) +#define bFM_CAN0_INTPND_INTPND4 *((volatile uint8_t *)(0x42C4140CUL)) +#define bFM4_CAN0_INTPND_INTPND4 *((volatile uint8_t *)(0x42C4140CUL)) +#define bFM_CAN0_INTPND_INTPND5 *((volatile uint8_t *)(0x42C41410UL)) +#define bFM4_CAN0_INTPND_INTPND5 *((volatile uint8_t *)(0x42C41410UL)) +#define bFM_CAN0_INTPND_INTPND6 *((volatile uint8_t *)(0x42C41414UL)) +#define bFM4_CAN0_INTPND_INTPND6 *((volatile uint8_t *)(0x42C41414UL)) +#define bFM_CAN0_INTPND_INTPND7 *((volatile uint8_t *)(0x42C41418UL)) +#define bFM4_CAN0_INTPND_INTPND7 *((volatile uint8_t *)(0x42C41418UL)) +#define bFM_CAN0_INTPND_INTPND8 *((volatile uint8_t *)(0x42C4141CUL)) +#define bFM4_CAN0_INTPND_INTPND8 *((volatile uint8_t *)(0x42C4141CUL)) +#define bFM_CAN0_INTPND_INTPND9 *((volatile uint8_t *)(0x42C41420UL)) +#define bFM4_CAN0_INTPND_INTPND9 *((volatile uint8_t *)(0x42C41420UL)) +#define bFM_CAN0_INTPND_INTPND10 *((volatile uint8_t *)(0x42C41424UL)) +#define bFM4_CAN0_INTPND_INTPND10 *((volatile uint8_t *)(0x42C41424UL)) +#define bFM_CAN0_INTPND_INTPND11 *((volatile uint8_t *)(0x42C41428UL)) +#define bFM4_CAN0_INTPND_INTPND11 *((volatile uint8_t *)(0x42C41428UL)) +#define bFM_CAN0_INTPND_INTPND12 *((volatile uint8_t *)(0x42C4142CUL)) +#define bFM4_CAN0_INTPND_INTPND12 *((volatile uint8_t *)(0x42C4142CUL)) +#define bFM_CAN0_INTPND_INTPND13 *((volatile uint8_t *)(0x42C41430UL)) +#define bFM4_CAN0_INTPND_INTPND13 *((volatile uint8_t *)(0x42C41430UL)) +#define bFM_CAN0_INTPND_INTPND14 *((volatile uint8_t *)(0x42C41434UL)) +#define bFM4_CAN0_INTPND_INTPND14 *((volatile uint8_t *)(0x42C41434UL)) +#define bFM_CAN0_INTPND_INTPND15 *((volatile uint8_t *)(0x42C41438UL)) +#define bFM4_CAN0_INTPND_INTPND15 *((volatile uint8_t *)(0x42C41438UL)) +#define bFM_CAN0_INTPND_INTPND16 *((volatile uint8_t *)(0x42C4143CUL)) +#define bFM4_CAN0_INTPND_INTPND16 *((volatile uint8_t *)(0x42C4143CUL)) +#define bFM_CAN0_INTPND_INTPND17 *((volatile uint8_t *)(0x42C41440UL)) +#define bFM4_CAN0_INTPND_INTPND17 *((volatile uint8_t *)(0x42C41440UL)) +#define bFM_CAN0_INTPND_INTPND18 *((volatile uint8_t *)(0x42C41444UL)) +#define bFM4_CAN0_INTPND_INTPND18 *((volatile uint8_t *)(0x42C41444UL)) +#define bFM_CAN0_INTPND_INTPND19 *((volatile uint8_t *)(0x42C41448UL)) +#define bFM4_CAN0_INTPND_INTPND19 *((volatile uint8_t *)(0x42C41448UL)) +#define bFM_CAN0_INTPND_INTPND20 *((volatile uint8_t *)(0x42C4144CUL)) +#define bFM4_CAN0_INTPND_INTPND20 *((volatile uint8_t *)(0x42C4144CUL)) +#define bFM_CAN0_INTPND_INTPND21 *((volatile uint8_t *)(0x42C41450UL)) +#define bFM4_CAN0_INTPND_INTPND21 *((volatile uint8_t *)(0x42C41450UL)) +#define bFM_CAN0_INTPND_INTPND22 *((volatile uint8_t *)(0x42C41454UL)) +#define bFM4_CAN0_INTPND_INTPND22 *((volatile uint8_t *)(0x42C41454UL)) +#define bFM_CAN0_INTPND_INTPND23 *((volatile uint8_t *)(0x42C41458UL)) +#define bFM4_CAN0_INTPND_INTPND23 *((volatile uint8_t *)(0x42C41458UL)) +#define bFM_CAN0_INTPND_INTPND24 *((volatile uint8_t *)(0x42C4145CUL)) +#define bFM4_CAN0_INTPND_INTPND24 *((volatile uint8_t *)(0x42C4145CUL)) +#define bFM_CAN0_INTPND_INTPND25 *((volatile uint8_t *)(0x42C41460UL)) +#define bFM4_CAN0_INTPND_INTPND25 *((volatile uint8_t *)(0x42C41460UL)) +#define bFM_CAN0_INTPND_INTPND26 *((volatile uint8_t *)(0x42C41464UL)) +#define bFM4_CAN0_INTPND_INTPND26 *((volatile uint8_t *)(0x42C41464UL)) +#define bFM_CAN0_INTPND_INTPND27 *((volatile uint8_t *)(0x42C41468UL)) +#define bFM4_CAN0_INTPND_INTPND27 *((volatile uint8_t *)(0x42C41468UL)) +#define bFM_CAN0_INTPND_INTPND28 *((volatile uint8_t *)(0x42C4146CUL)) +#define bFM4_CAN0_INTPND_INTPND28 *((volatile uint8_t *)(0x42C4146CUL)) +#define bFM_CAN0_INTPND_INTPND29 *((volatile uint8_t *)(0x42C41470UL)) +#define bFM4_CAN0_INTPND_INTPND29 *((volatile uint8_t *)(0x42C41470UL)) +#define bFM_CAN0_INTPND_INTPND30 *((volatile uint8_t *)(0x42C41474UL)) +#define bFM4_CAN0_INTPND_INTPND30 *((volatile uint8_t *)(0x42C41474UL)) +#define bFM_CAN0_INTPND_INTPND31 *((volatile uint8_t *)(0x42C41478UL)) +#define bFM4_CAN0_INTPND_INTPND31 *((volatile uint8_t *)(0x42C41478UL)) +#define bFM_CAN0_INTPND_INTPND32 *((volatile uint8_t *)(0x42C4147CUL)) +#define bFM4_CAN0_INTPND_INTPND32 *((volatile uint8_t *)(0x42C4147CUL)) + +#define bFM_CAN0_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C41600UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C41600UL)) +#define bFM_CAN0_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C41604UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C41604UL)) +#define bFM_CAN0_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C41608UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C41608UL)) +#define bFM_CAN0_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C4160CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C4160CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C41610UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C41610UL)) +#define bFM_CAN0_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C41614UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C41614UL)) +#define bFM_CAN0_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C41618UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C41618UL)) +#define bFM_CAN0_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C4161CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C4161CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C41620UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C41620UL)) +#define bFM_CAN0_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C41624UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C41624UL)) +#define bFM_CAN0_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C41628UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C41628UL)) +#define bFM_CAN0_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C4162CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C4162CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C41630UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C41630UL)) +#define bFM_CAN0_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C41634UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C41634UL)) +#define bFM_CAN0_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C41638UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C41638UL)) +#define bFM_CAN0_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C4163CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C4163CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C41640UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C41640UL)) +#define bFM_CAN0_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C41644UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C41644UL)) +#define bFM_CAN0_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C41648UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C41648UL)) +#define bFM_CAN0_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C4164CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C4164CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C41650UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C41650UL)) +#define bFM_CAN0_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C41654UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C41654UL)) +#define bFM_CAN0_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C41658UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C41658UL)) +#define bFM_CAN0_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C4165CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C4165CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C41660UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C41660UL)) +#define bFM_CAN0_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C41664UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C41664UL)) +#define bFM_CAN0_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C41668UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C41668UL)) +#define bFM_CAN0_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C4166CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C4166CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C41670UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C41670UL)) +#define bFM_CAN0_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C41674UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C41674UL)) +#define bFM_CAN0_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C41678UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C41678UL)) +#define bFM_CAN0_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C4167CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C4167CUL)) + +#define bFM_CAN0_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C41200UL)) +#define bFM4_CAN0_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C41200UL)) +#define bFM_CAN0_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C41204UL)) +#define bFM4_CAN0_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C41204UL)) +#define bFM_CAN0_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C41208UL)) +#define bFM4_CAN0_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C41208UL)) +#define bFM_CAN0_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C4120CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C4120CUL)) +#define bFM_CAN0_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C41210UL)) +#define bFM4_CAN0_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C41210UL)) +#define bFM_CAN0_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C41214UL)) +#define bFM4_CAN0_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C41214UL)) +#define bFM_CAN0_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C41218UL)) +#define bFM4_CAN0_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C41218UL)) +#define bFM_CAN0_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C4121CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C4121CUL)) +#define bFM_CAN0_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C41220UL)) +#define bFM4_CAN0_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C41220UL)) +#define bFM_CAN0_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C41224UL)) +#define bFM4_CAN0_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C41224UL)) +#define bFM_CAN0_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C41228UL)) +#define bFM4_CAN0_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C41228UL)) +#define bFM_CAN0_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C4122CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C4122CUL)) +#define bFM_CAN0_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C41230UL)) +#define bFM4_CAN0_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C41230UL)) +#define bFM_CAN0_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C41234UL)) +#define bFM4_CAN0_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C41234UL)) +#define bFM_CAN0_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C41238UL)) +#define bFM4_CAN0_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C41238UL)) +#define bFM_CAN0_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C4123CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C4123CUL)) +#define bFM_CAN0_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C41240UL)) +#define bFM4_CAN0_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C41240UL)) +#define bFM_CAN0_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C41244UL)) +#define bFM4_CAN0_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C41244UL)) +#define bFM_CAN0_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C41248UL)) +#define bFM4_CAN0_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C41248UL)) +#define bFM_CAN0_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C4124CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C4124CUL)) +#define bFM_CAN0_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C41250UL)) +#define bFM4_CAN0_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C41250UL)) +#define bFM_CAN0_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C41254UL)) +#define bFM4_CAN0_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C41254UL)) +#define bFM_CAN0_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C41258UL)) +#define bFM4_CAN0_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C41258UL)) +#define bFM_CAN0_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C4125CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C4125CUL)) +#define bFM_CAN0_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C41260UL)) +#define bFM4_CAN0_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C41260UL)) +#define bFM_CAN0_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C41264UL)) +#define bFM4_CAN0_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C41264UL)) +#define bFM_CAN0_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C41268UL)) +#define bFM4_CAN0_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C41268UL)) +#define bFM_CAN0_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C4126CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C4126CUL)) +#define bFM_CAN0_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C41270UL)) +#define bFM4_CAN0_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C41270UL)) +#define bFM_CAN0_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C41274UL)) +#define bFM4_CAN0_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C41274UL)) +#define bFM_CAN0_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C41278UL)) +#define bFM4_CAN0_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C41278UL)) +#define bFM_CAN0_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C4127CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C4127CUL)) + +#define bFM_CAN0_STATR_TXOK *((volatile uint8_t *)(0x42C4004CUL)) +#define bFM4_CAN0_STATR_TXOK *((volatile uint8_t *)(0x42C4004CUL)) +#define bFM_CAN0_STATR_RXOK *((volatile uint8_t *)(0x42C40050UL)) +#define bFM4_CAN0_STATR_RXOK *((volatile uint8_t *)(0x42C40050UL)) +#define bFM_CAN0_STATR_EPASS *((volatile uint8_t *)(0x42C40054UL)) +#define bFM4_CAN0_STATR_EPASS *((volatile uint8_t *)(0x42C40054UL)) +#define bFM_CAN0_STATR_EWARN *((volatile uint8_t *)(0x42C40058UL)) +#define bFM4_CAN0_STATR_EWARN *((volatile uint8_t *)(0x42C40058UL)) +#define bFM_CAN0_STATR_BOFF *((volatile uint8_t *)(0x42C4005CUL)) +#define bFM4_CAN0_STATR_BOFF *((volatile uint8_t *)(0x42C4005CUL)) + +#define bFM_CAN0_TESTR_BASIC *((volatile uint8_t *)(0x42C40148UL)) +#define bFM4_CAN0_TESTR_BASIC *((volatile uint8_t *)(0x42C40148UL)) +#define bFM_CAN0_TESTR_SILENT *((volatile uint8_t *)(0x42C4014CUL)) +#define bFM4_CAN0_TESTR_SILENT *((volatile uint8_t *)(0x42C4014CUL)) +#define bFM_CAN0_TESTR_LBACK *((volatile uint8_t *)(0x42C40150UL)) +#define bFM4_CAN0_TESTR_LBACK *((volatile uint8_t *)(0x42C40150UL)) +#define bFM_CAN0_TESTR_RX *((volatile uint8_t *)(0x42C4015CUL)) +#define bFM4_CAN0_TESTR_RX *((volatile uint8_t *)(0x42C4015CUL)) + +#define bFM_CAN0_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C41000UL)) +#define bFM4_CAN0_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C41000UL)) +#define bFM_CAN0_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C41004UL)) +#define bFM4_CAN0_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C41004UL)) +#define bFM_CAN0_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C41008UL)) +#define bFM4_CAN0_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C41008UL)) +#define bFM_CAN0_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C4100CUL)) +#define bFM4_CAN0_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C4100CUL)) +#define bFM_CAN0_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C41010UL)) +#define bFM4_CAN0_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C41010UL)) +#define bFM_CAN0_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C41014UL)) +#define bFM4_CAN0_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C41014UL)) +#define bFM_CAN0_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C41018UL)) +#define bFM4_CAN0_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C41018UL)) +#define bFM_CAN0_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C4101CUL)) +#define bFM4_CAN0_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C4101CUL)) +#define bFM_CAN0_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C41020UL)) +#define bFM4_CAN0_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C41020UL)) +#define bFM_CAN0_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C41024UL)) +#define bFM4_CAN0_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C41024UL)) +#define bFM_CAN0_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C41028UL)) +#define bFM4_CAN0_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C41028UL)) +#define bFM_CAN0_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C4102CUL)) +#define bFM4_CAN0_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C4102CUL)) +#define bFM_CAN0_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C41030UL)) +#define bFM4_CAN0_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C41030UL)) +#define bFM_CAN0_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C41034UL)) +#define bFM4_CAN0_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C41034UL)) +#define bFM_CAN0_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C41038UL)) +#define bFM4_CAN0_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C41038UL)) +#define bFM_CAN0_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C4103CUL)) +#define bFM4_CAN0_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C4103CUL)) +#define bFM_CAN0_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C41040UL)) +#define bFM4_CAN0_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C41040UL)) +#define bFM_CAN0_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C41044UL)) +#define bFM4_CAN0_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C41044UL)) +#define bFM_CAN0_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C41048UL)) +#define bFM4_CAN0_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C41048UL)) +#define bFM_CAN0_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C4104CUL)) +#define bFM4_CAN0_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C4104CUL)) +#define bFM_CAN0_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C41050UL)) +#define bFM4_CAN0_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C41050UL)) +#define bFM_CAN0_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C41054UL)) +#define bFM4_CAN0_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C41054UL)) +#define bFM_CAN0_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C41058UL)) +#define bFM4_CAN0_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C41058UL)) +#define bFM_CAN0_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C4105CUL)) +#define bFM4_CAN0_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C4105CUL)) +#define bFM_CAN0_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C41060UL)) +#define bFM4_CAN0_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C41060UL)) +#define bFM_CAN0_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C41064UL)) +#define bFM4_CAN0_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C41064UL)) +#define bFM_CAN0_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C41068UL)) +#define bFM4_CAN0_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C41068UL)) +#define bFM_CAN0_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C4106CUL)) +#define bFM4_CAN0_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C4106CUL)) +#define bFM_CAN0_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C41070UL)) +#define bFM4_CAN0_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C41070UL)) +#define bFM_CAN0_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C41074UL)) +#define bFM4_CAN0_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C41074UL)) +#define bFM_CAN0_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C41078UL)) +#define bFM4_CAN0_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C41078UL)) +#define bFM_CAN0_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C4107CUL)) +#define bFM4_CAN0_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C4107CUL)) + + +/******************************************************************************* +* CAN Registers CAN1 +* Bitband Section +*******************************************************************************/ +#define bFM_CAN1_CTRLR_INIT *((volatile uint8_t *)(0x42C60000UL)) +#define bFM4_CAN1_CTRLR_INIT *((volatile uint8_t *)(0x42C60000UL)) +#define bFM_CAN1_CTRLR_IE *((volatile uint8_t *)(0x42C60004UL)) +#define bFM4_CAN1_CTRLR_IE *((volatile uint8_t *)(0x42C60004UL)) +#define bFM_CAN1_CTRLR_SIE *((volatile uint8_t *)(0x42C60008UL)) +#define bFM4_CAN1_CTRLR_SIE *((volatile uint8_t *)(0x42C60008UL)) +#define bFM_CAN1_CTRLR_EIE *((volatile uint8_t *)(0x42C6000CUL)) +#define bFM4_CAN1_CTRLR_EIE *((volatile uint8_t *)(0x42C6000CUL)) +#define bFM_CAN1_CTRLR_DAR *((volatile uint8_t *)(0x42C60014UL)) +#define bFM4_CAN1_CTRLR_DAR *((volatile uint8_t *)(0x42C60014UL)) +#define bFM_CAN1_CTRLR_CCE *((volatile uint8_t *)(0x42C60018UL)) +#define bFM4_CAN1_CTRLR_CCE *((volatile uint8_t *)(0x42C60018UL)) +#define bFM_CAN1_CTRLR_TEST *((volatile uint8_t *)(0x42C6001CUL)) +#define bFM4_CAN1_CTRLR_TEST *((volatile uint8_t *)(0x42C6001CUL)) + +#define bFM_CAN1_ERRCNT_RP *((volatile uint8_t *)(0x42C600BCUL)) +#define bFM4_CAN1_ERRCNT_RP *((volatile uint8_t *)(0x42C600BCUL)) + +#define bFM_CAN1_IF1ARB_DIR *((volatile uint8_t *)(0x42C60374UL)) +#define bFM4_CAN1_IF1ARB_DIR *((volatile uint8_t *)(0x42C60374UL)) +#define bFM_CAN1_IF1ARB_XTD *((volatile uint8_t *)(0x42C60378UL)) +#define bFM4_CAN1_IF1ARB_XTD *((volatile uint8_t *)(0x42C60378UL)) +#define bFM_CAN1_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C6037CUL)) +#define bFM4_CAN1_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C6037CUL)) + +#define bFM_CAN1_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C60240UL)) +#define bFM4_CAN1_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C60240UL)) +#define bFM_CAN1_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C60244UL)) +#define bFM4_CAN1_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C60244UL)) +#define bFM_CAN1_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C60248UL)) +#define bFM4_CAN1_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C60248UL)) +#define bFM_CAN1_IF1CMSK_CIP *((volatile uint8_t *)(0x42C6024CUL)) +#define bFM4_CAN1_IF1CMSK_CIP *((volatile uint8_t *)(0x42C6024CUL)) +#define bFM_CAN1_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C60250UL)) +#define bFM4_CAN1_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C60250UL)) +#define bFM_CAN1_IF1CMSK_ARB *((volatile uint8_t *)(0x42C60254UL)) +#define bFM4_CAN1_IF1CMSK_ARB *((volatile uint8_t *)(0x42C60254UL)) +#define bFM_CAN1_IF1CMSK_MASK *((volatile uint8_t *)(0x42C60258UL)) +#define bFM4_CAN1_IF1CMSK_MASK *((volatile uint8_t *)(0x42C60258UL)) +#define bFM_CAN1_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C6025CUL)) +#define bFM4_CAN1_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C6025CUL)) + +#define bFM_CAN1_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C6023CUL)) +#define bFM4_CAN1_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C6023CUL)) + +#define bFM_CAN1_IF1MCTR_EOB *((volatile uint8_t *)(0x42C6039CUL)) +#define bFM4_CAN1_IF1MCTR_EOB *((volatile uint8_t *)(0x42C6039CUL)) +#define bFM_CAN1_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C603A0UL)) +#define bFM4_CAN1_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C603A0UL)) +#define bFM_CAN1_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C603A4UL)) +#define bFM4_CAN1_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C603A4UL)) +#define bFM_CAN1_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C603A8UL)) +#define bFM4_CAN1_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C603A8UL)) +#define bFM_CAN1_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C603ACUL)) +#define bFM4_CAN1_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C603ACUL)) +#define bFM_CAN1_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C603B0UL)) +#define bFM4_CAN1_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C603B0UL)) +#define bFM_CAN1_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C603B4UL)) +#define bFM4_CAN1_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C603B4UL)) +#define bFM_CAN1_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C603B8UL)) +#define bFM4_CAN1_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C603B8UL)) +#define bFM_CAN1_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C603BCUL)) +#define bFM4_CAN1_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C603BCUL)) + +#define bFM_CAN1_IF1MSK_MDIR *((volatile uint8_t *)(0x42C602F8UL)) +#define bFM4_CAN1_IF1MSK_MDIR *((volatile uint8_t *)(0x42C602F8UL)) +#define bFM_CAN1_IF1MSK_MXTD *((volatile uint8_t *)(0x42C602FCUL)) +#define bFM4_CAN1_IF1MSK_MXTD *((volatile uint8_t *)(0x42C602FCUL)) + +#define bFM_CAN1_IF2ARB_DIR *((volatile uint8_t *)(0x42C60974UL)) +#define bFM4_CAN1_IF2ARB_DIR *((volatile uint8_t *)(0x42C60974UL)) +#define bFM_CAN1_IF2ARB_XTD *((volatile uint8_t *)(0x42C60978UL)) +#define bFM4_CAN1_IF2ARB_XTD *((volatile uint8_t *)(0x42C60978UL)) +#define bFM_CAN1_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C6097CUL)) +#define bFM4_CAN1_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C6097CUL)) + +#define bFM_CAN1_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C60840UL)) +#define bFM4_CAN1_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C60840UL)) +#define bFM_CAN1_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C60844UL)) +#define bFM4_CAN1_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C60844UL)) +#define bFM_CAN1_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C60848UL)) +#define bFM4_CAN1_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C60848UL)) +#define bFM_CAN1_IF2CMSK_CIP *((volatile uint8_t *)(0x42C6084CUL)) +#define bFM4_CAN1_IF2CMSK_CIP *((volatile uint8_t *)(0x42C6084CUL)) +#define bFM_CAN1_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C60850UL)) +#define bFM4_CAN1_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C60850UL)) +#define bFM_CAN1_IF2CMSK_ARB *((volatile uint8_t *)(0x42C60854UL)) +#define bFM4_CAN1_IF2CMSK_ARB *((volatile uint8_t *)(0x42C60854UL)) +#define bFM_CAN1_IF2CMSK_MASK *((volatile uint8_t *)(0x42C60858UL)) +#define bFM4_CAN1_IF2CMSK_MASK *((volatile uint8_t *)(0x42C60858UL)) +#define bFM_CAN1_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C6085CUL)) +#define bFM4_CAN1_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C6085CUL)) + +#define bFM_CAN1_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C6083CUL)) +#define bFM4_CAN1_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C6083CUL)) + +#define bFM_CAN1_IF2MCTR_EOB *((volatile uint8_t *)(0x42C6099CUL)) +#define bFM4_CAN1_IF2MCTR_EOB *((volatile uint8_t *)(0x42C6099CUL)) +#define bFM_CAN1_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C609A0UL)) +#define bFM4_CAN1_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C609A0UL)) +#define bFM_CAN1_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C609A4UL)) +#define bFM4_CAN1_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C609A4UL)) +#define bFM_CAN1_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C609A8UL)) +#define bFM4_CAN1_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C609A8UL)) +#define bFM_CAN1_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C609ACUL)) +#define bFM4_CAN1_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C609ACUL)) +#define bFM_CAN1_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C609B0UL)) +#define bFM4_CAN1_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C609B0UL)) +#define bFM_CAN1_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C609B4UL)) +#define bFM4_CAN1_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C609B4UL)) +#define bFM_CAN1_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C609B8UL)) +#define bFM4_CAN1_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C609B8UL)) +#define bFM_CAN1_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C609BCUL)) +#define bFM4_CAN1_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C609BCUL)) + +#define bFM_CAN1_IF2MSK_MDIR *((volatile uint8_t *)(0x42C608F8UL)) +#define bFM4_CAN1_IF2MSK_MDIR *((volatile uint8_t *)(0x42C608F8UL)) +#define bFM_CAN1_IF2MSK_MXTD *((volatile uint8_t *)(0x42C608FCUL)) +#define bFM4_CAN1_IF2MSK_MXTD *((volatile uint8_t *)(0x42C608FCUL)) + +#define bFM_CAN1_INTPND_INTPND1 *((volatile uint8_t *)(0x42C61400UL)) +#define bFM4_CAN1_INTPND_INTPND1 *((volatile uint8_t *)(0x42C61400UL)) +#define bFM_CAN1_INTPND_INTPND2 *((volatile uint8_t *)(0x42C61404UL)) +#define bFM4_CAN1_INTPND_INTPND2 *((volatile uint8_t *)(0x42C61404UL)) +#define bFM_CAN1_INTPND_INTPND3 *((volatile uint8_t *)(0x42C61408UL)) +#define bFM4_CAN1_INTPND_INTPND3 *((volatile uint8_t *)(0x42C61408UL)) +#define bFM_CAN1_INTPND_INTPND4 *((volatile uint8_t *)(0x42C6140CUL)) +#define bFM4_CAN1_INTPND_INTPND4 *((volatile uint8_t *)(0x42C6140CUL)) +#define bFM_CAN1_INTPND_INTPND5 *((volatile uint8_t *)(0x42C61410UL)) +#define bFM4_CAN1_INTPND_INTPND5 *((volatile uint8_t *)(0x42C61410UL)) +#define bFM_CAN1_INTPND_INTPND6 *((volatile uint8_t *)(0x42C61414UL)) +#define bFM4_CAN1_INTPND_INTPND6 *((volatile uint8_t *)(0x42C61414UL)) +#define bFM_CAN1_INTPND_INTPND7 *((volatile uint8_t *)(0x42C61418UL)) +#define bFM4_CAN1_INTPND_INTPND7 *((volatile uint8_t *)(0x42C61418UL)) +#define bFM_CAN1_INTPND_INTPND8 *((volatile uint8_t *)(0x42C6141CUL)) +#define bFM4_CAN1_INTPND_INTPND8 *((volatile uint8_t *)(0x42C6141CUL)) +#define bFM_CAN1_INTPND_INTPND9 *((volatile uint8_t *)(0x42C61420UL)) +#define bFM4_CAN1_INTPND_INTPND9 *((volatile uint8_t *)(0x42C61420UL)) +#define bFM_CAN1_INTPND_INTPND10 *((volatile uint8_t *)(0x42C61424UL)) +#define bFM4_CAN1_INTPND_INTPND10 *((volatile uint8_t *)(0x42C61424UL)) +#define bFM_CAN1_INTPND_INTPND11 *((volatile uint8_t *)(0x42C61428UL)) +#define bFM4_CAN1_INTPND_INTPND11 *((volatile uint8_t *)(0x42C61428UL)) +#define bFM_CAN1_INTPND_INTPND12 *((volatile uint8_t *)(0x42C6142CUL)) +#define bFM4_CAN1_INTPND_INTPND12 *((volatile uint8_t *)(0x42C6142CUL)) +#define bFM_CAN1_INTPND_INTPND13 *((volatile uint8_t *)(0x42C61430UL)) +#define bFM4_CAN1_INTPND_INTPND13 *((volatile uint8_t *)(0x42C61430UL)) +#define bFM_CAN1_INTPND_INTPND14 *((volatile uint8_t *)(0x42C61434UL)) +#define bFM4_CAN1_INTPND_INTPND14 *((volatile uint8_t *)(0x42C61434UL)) +#define bFM_CAN1_INTPND_INTPND15 *((volatile uint8_t *)(0x42C61438UL)) +#define bFM4_CAN1_INTPND_INTPND15 *((volatile uint8_t *)(0x42C61438UL)) +#define bFM_CAN1_INTPND_INTPND16 *((volatile uint8_t *)(0x42C6143CUL)) +#define bFM4_CAN1_INTPND_INTPND16 *((volatile uint8_t *)(0x42C6143CUL)) +#define bFM_CAN1_INTPND_INTPND17 *((volatile uint8_t *)(0x42C61440UL)) +#define bFM4_CAN1_INTPND_INTPND17 *((volatile uint8_t *)(0x42C61440UL)) +#define bFM_CAN1_INTPND_INTPND18 *((volatile uint8_t *)(0x42C61444UL)) +#define bFM4_CAN1_INTPND_INTPND18 *((volatile uint8_t *)(0x42C61444UL)) +#define bFM_CAN1_INTPND_INTPND19 *((volatile uint8_t *)(0x42C61448UL)) +#define bFM4_CAN1_INTPND_INTPND19 *((volatile uint8_t *)(0x42C61448UL)) +#define bFM_CAN1_INTPND_INTPND20 *((volatile uint8_t *)(0x42C6144CUL)) +#define bFM4_CAN1_INTPND_INTPND20 *((volatile uint8_t *)(0x42C6144CUL)) +#define bFM_CAN1_INTPND_INTPND21 *((volatile uint8_t *)(0x42C61450UL)) +#define bFM4_CAN1_INTPND_INTPND21 *((volatile uint8_t *)(0x42C61450UL)) +#define bFM_CAN1_INTPND_INTPND22 *((volatile uint8_t *)(0x42C61454UL)) +#define bFM4_CAN1_INTPND_INTPND22 *((volatile uint8_t *)(0x42C61454UL)) +#define bFM_CAN1_INTPND_INTPND23 *((volatile uint8_t *)(0x42C61458UL)) +#define bFM4_CAN1_INTPND_INTPND23 *((volatile uint8_t *)(0x42C61458UL)) +#define bFM_CAN1_INTPND_INTPND24 *((volatile uint8_t *)(0x42C6145CUL)) +#define bFM4_CAN1_INTPND_INTPND24 *((volatile uint8_t *)(0x42C6145CUL)) +#define bFM_CAN1_INTPND_INTPND25 *((volatile uint8_t *)(0x42C61460UL)) +#define bFM4_CAN1_INTPND_INTPND25 *((volatile uint8_t *)(0x42C61460UL)) +#define bFM_CAN1_INTPND_INTPND26 *((volatile uint8_t *)(0x42C61464UL)) +#define bFM4_CAN1_INTPND_INTPND26 *((volatile uint8_t *)(0x42C61464UL)) +#define bFM_CAN1_INTPND_INTPND27 *((volatile uint8_t *)(0x42C61468UL)) +#define bFM4_CAN1_INTPND_INTPND27 *((volatile uint8_t *)(0x42C61468UL)) +#define bFM_CAN1_INTPND_INTPND28 *((volatile uint8_t *)(0x42C6146CUL)) +#define bFM4_CAN1_INTPND_INTPND28 *((volatile uint8_t *)(0x42C6146CUL)) +#define bFM_CAN1_INTPND_INTPND29 *((volatile uint8_t *)(0x42C61470UL)) +#define bFM4_CAN1_INTPND_INTPND29 *((volatile uint8_t *)(0x42C61470UL)) +#define bFM_CAN1_INTPND_INTPND30 *((volatile uint8_t *)(0x42C61474UL)) +#define bFM4_CAN1_INTPND_INTPND30 *((volatile uint8_t *)(0x42C61474UL)) +#define bFM_CAN1_INTPND_INTPND31 *((volatile uint8_t *)(0x42C61478UL)) +#define bFM4_CAN1_INTPND_INTPND31 *((volatile uint8_t *)(0x42C61478UL)) +#define bFM_CAN1_INTPND_INTPND32 *((volatile uint8_t *)(0x42C6147CUL)) +#define bFM4_CAN1_INTPND_INTPND32 *((volatile uint8_t *)(0x42C6147CUL)) + +#define bFM_CAN1_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C61600UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C61600UL)) +#define bFM_CAN1_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C61604UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C61604UL)) +#define bFM_CAN1_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C61608UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C61608UL)) +#define bFM_CAN1_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C6160CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C6160CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C61610UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C61610UL)) +#define bFM_CAN1_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C61614UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C61614UL)) +#define bFM_CAN1_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C61618UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C61618UL)) +#define bFM_CAN1_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C6161CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C6161CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C61620UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C61620UL)) +#define bFM_CAN1_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C61624UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C61624UL)) +#define bFM_CAN1_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C61628UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C61628UL)) +#define bFM_CAN1_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C6162CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C6162CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C61630UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C61630UL)) +#define bFM_CAN1_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C61634UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C61634UL)) +#define bFM_CAN1_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C61638UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C61638UL)) +#define bFM_CAN1_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C6163CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C6163CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C61640UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C61640UL)) +#define bFM_CAN1_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C61644UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C61644UL)) +#define bFM_CAN1_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C61648UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C61648UL)) +#define bFM_CAN1_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C6164CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C6164CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C61650UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C61650UL)) +#define bFM_CAN1_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C61654UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C61654UL)) +#define bFM_CAN1_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C61658UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C61658UL)) +#define bFM_CAN1_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C6165CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C6165CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C61660UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C61660UL)) +#define bFM_CAN1_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C61664UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C61664UL)) +#define bFM_CAN1_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C61668UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C61668UL)) +#define bFM_CAN1_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C6166CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C6166CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C61670UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C61670UL)) +#define bFM_CAN1_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C61674UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C61674UL)) +#define bFM_CAN1_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C61678UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C61678UL)) +#define bFM_CAN1_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C6167CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C6167CUL)) + +#define bFM_CAN1_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C61200UL)) +#define bFM4_CAN1_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C61200UL)) +#define bFM_CAN1_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C61204UL)) +#define bFM4_CAN1_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C61204UL)) +#define bFM_CAN1_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C61208UL)) +#define bFM4_CAN1_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C61208UL)) +#define bFM_CAN1_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C6120CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C6120CUL)) +#define bFM_CAN1_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C61210UL)) +#define bFM4_CAN1_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C61210UL)) +#define bFM_CAN1_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C61214UL)) +#define bFM4_CAN1_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C61214UL)) +#define bFM_CAN1_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C61218UL)) +#define bFM4_CAN1_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C61218UL)) +#define bFM_CAN1_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C6121CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C6121CUL)) +#define bFM_CAN1_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C61220UL)) +#define bFM4_CAN1_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C61220UL)) +#define bFM_CAN1_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C61224UL)) +#define bFM4_CAN1_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C61224UL)) +#define bFM_CAN1_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C61228UL)) +#define bFM4_CAN1_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C61228UL)) +#define bFM_CAN1_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C6122CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C6122CUL)) +#define bFM_CAN1_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C61230UL)) +#define bFM4_CAN1_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C61230UL)) +#define bFM_CAN1_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C61234UL)) +#define bFM4_CAN1_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C61234UL)) +#define bFM_CAN1_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C61238UL)) +#define bFM4_CAN1_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C61238UL)) +#define bFM_CAN1_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C6123CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C6123CUL)) +#define bFM_CAN1_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C61240UL)) +#define bFM4_CAN1_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C61240UL)) +#define bFM_CAN1_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C61244UL)) +#define bFM4_CAN1_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C61244UL)) +#define bFM_CAN1_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C61248UL)) +#define bFM4_CAN1_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C61248UL)) +#define bFM_CAN1_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C6124CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C6124CUL)) +#define bFM_CAN1_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C61250UL)) +#define bFM4_CAN1_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C61250UL)) +#define bFM_CAN1_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C61254UL)) +#define bFM4_CAN1_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C61254UL)) +#define bFM_CAN1_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C61258UL)) +#define bFM4_CAN1_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C61258UL)) +#define bFM_CAN1_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C6125CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C6125CUL)) +#define bFM_CAN1_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C61260UL)) +#define bFM4_CAN1_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C61260UL)) +#define bFM_CAN1_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C61264UL)) +#define bFM4_CAN1_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C61264UL)) +#define bFM_CAN1_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C61268UL)) +#define bFM4_CAN1_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C61268UL)) +#define bFM_CAN1_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C6126CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C6126CUL)) +#define bFM_CAN1_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C61270UL)) +#define bFM4_CAN1_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C61270UL)) +#define bFM_CAN1_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C61274UL)) +#define bFM4_CAN1_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C61274UL)) +#define bFM_CAN1_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C61278UL)) +#define bFM4_CAN1_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C61278UL)) +#define bFM_CAN1_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C6127CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C6127CUL)) + +#define bFM_CAN1_STATR_TXOK *((volatile uint8_t *)(0x42C6004CUL)) +#define bFM4_CAN1_STATR_TXOK *((volatile uint8_t *)(0x42C6004CUL)) +#define bFM_CAN1_STATR_RXOK *((volatile uint8_t *)(0x42C60050UL)) +#define bFM4_CAN1_STATR_RXOK *((volatile uint8_t *)(0x42C60050UL)) +#define bFM_CAN1_STATR_EPASS *((volatile uint8_t *)(0x42C60054UL)) +#define bFM4_CAN1_STATR_EPASS *((volatile uint8_t *)(0x42C60054UL)) +#define bFM_CAN1_STATR_EWARN *((volatile uint8_t *)(0x42C60058UL)) +#define bFM4_CAN1_STATR_EWARN *((volatile uint8_t *)(0x42C60058UL)) +#define bFM_CAN1_STATR_BOFF *((volatile uint8_t *)(0x42C6005CUL)) +#define bFM4_CAN1_STATR_BOFF *((volatile uint8_t *)(0x42C6005CUL)) + +#define bFM_CAN1_TESTR_BASIC *((volatile uint8_t *)(0x42C60148UL)) +#define bFM4_CAN1_TESTR_BASIC *((volatile uint8_t *)(0x42C60148UL)) +#define bFM_CAN1_TESTR_SILENT *((volatile uint8_t *)(0x42C6014CUL)) +#define bFM4_CAN1_TESTR_SILENT *((volatile uint8_t *)(0x42C6014CUL)) +#define bFM_CAN1_TESTR_LBACK *((volatile uint8_t *)(0x42C60150UL)) +#define bFM4_CAN1_TESTR_LBACK *((volatile uint8_t *)(0x42C60150UL)) +#define bFM_CAN1_TESTR_RX *((volatile uint8_t *)(0x42C6015CUL)) +#define bFM4_CAN1_TESTR_RX *((volatile uint8_t *)(0x42C6015CUL)) + +#define bFM_CAN1_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C61000UL)) +#define bFM4_CAN1_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C61000UL)) +#define bFM_CAN1_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C61004UL)) +#define bFM4_CAN1_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C61004UL)) +#define bFM_CAN1_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C61008UL)) +#define bFM4_CAN1_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C61008UL)) +#define bFM_CAN1_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C6100CUL)) +#define bFM4_CAN1_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C6100CUL)) +#define bFM_CAN1_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C61010UL)) +#define bFM4_CAN1_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C61010UL)) +#define bFM_CAN1_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C61014UL)) +#define bFM4_CAN1_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C61014UL)) +#define bFM_CAN1_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C61018UL)) +#define bFM4_CAN1_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C61018UL)) +#define bFM_CAN1_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C6101CUL)) +#define bFM4_CAN1_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C6101CUL)) +#define bFM_CAN1_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C61020UL)) +#define bFM4_CAN1_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C61020UL)) +#define bFM_CAN1_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C61024UL)) +#define bFM4_CAN1_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C61024UL)) +#define bFM_CAN1_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C61028UL)) +#define bFM4_CAN1_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C61028UL)) +#define bFM_CAN1_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C6102CUL)) +#define bFM4_CAN1_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C6102CUL)) +#define bFM_CAN1_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C61030UL)) +#define bFM4_CAN1_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C61030UL)) +#define bFM_CAN1_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C61034UL)) +#define bFM4_CAN1_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C61034UL)) +#define bFM_CAN1_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C61038UL)) +#define bFM4_CAN1_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C61038UL)) +#define bFM_CAN1_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C6103CUL)) +#define bFM4_CAN1_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C6103CUL)) +#define bFM_CAN1_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C61040UL)) +#define bFM4_CAN1_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C61040UL)) +#define bFM_CAN1_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C61044UL)) +#define bFM4_CAN1_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C61044UL)) +#define bFM_CAN1_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C61048UL)) +#define bFM4_CAN1_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C61048UL)) +#define bFM_CAN1_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C6104CUL)) +#define bFM4_CAN1_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C6104CUL)) +#define bFM_CAN1_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C61050UL)) +#define bFM4_CAN1_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C61050UL)) +#define bFM_CAN1_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C61054UL)) +#define bFM4_CAN1_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C61054UL)) +#define bFM_CAN1_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C61058UL)) +#define bFM4_CAN1_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C61058UL)) +#define bFM_CAN1_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C6105CUL)) +#define bFM4_CAN1_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C6105CUL)) +#define bFM_CAN1_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C61060UL)) +#define bFM4_CAN1_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C61060UL)) +#define bFM_CAN1_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C61064UL)) +#define bFM4_CAN1_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C61064UL)) +#define bFM_CAN1_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C61068UL)) +#define bFM4_CAN1_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C61068UL)) +#define bFM_CAN1_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C6106CUL)) +#define bFM4_CAN1_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C6106CUL)) +#define bFM_CAN1_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C61070UL)) +#define bFM4_CAN1_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C61070UL)) +#define bFM_CAN1_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C61074UL)) +#define bFM4_CAN1_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C61074UL)) +#define bFM_CAN1_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C61078UL)) +#define bFM4_CAN1_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C61078UL)) +#define bFM_CAN1_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C6107CUL)) +#define bFM4_CAN1_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C6107CUL)) + + +/******************************************************************************* +* CANFD Registers CANFD0 +* Bitband Section +*******************************************************************************/ +#define bFM_CANFD0_CCCR_INIT *((volatile uint8_t *)(0x42E00300UL)) +#define bFM4_CANFD0_CCCR_INIT *((volatile uint8_t *)(0x42E00300UL)) +#define bFM_CANFD0_CCCR_CCE *((volatile uint8_t *)(0x42E00304UL)) +#define bFM4_CANFD0_CCCR_CCE *((volatile uint8_t *)(0x42E00304UL)) +#define bFM_CANFD0_CCCR_ASM *((volatile uint8_t *)(0x42E00308UL)) +#define bFM4_CANFD0_CCCR_ASM *((volatile uint8_t *)(0x42E00308UL)) +#define bFM_CANFD0_CCCR_CSA *((volatile uint8_t *)(0x42E0030CUL)) +#define bFM4_CANFD0_CCCR_CSA *((volatile uint8_t *)(0x42E0030CUL)) +#define bFM_CANFD0_CCCR_CSR *((volatile uint8_t *)(0x42E00310UL)) +#define bFM4_CANFD0_CCCR_CSR *((volatile uint8_t *)(0x42E00310UL)) +#define bFM_CANFD0_CCCR_MON *((volatile uint8_t *)(0x42E00314UL)) +#define bFM4_CANFD0_CCCR_MON *((volatile uint8_t *)(0x42E00314UL)) +#define bFM_CANFD0_CCCR_DAR *((volatile uint8_t *)(0x42E00318UL)) +#define bFM4_CANFD0_CCCR_DAR *((volatile uint8_t *)(0x42E00318UL)) +#define bFM_CANFD0_CCCR_TEST *((volatile uint8_t *)(0x42E0031CUL)) +#define bFM4_CANFD0_CCCR_TEST *((volatile uint8_t *)(0x42E0031CUL)) +#define bFM_CANFD0_CCCR_FDO *((volatile uint8_t *)(0x42E00330UL)) +#define bFM4_CANFD0_CCCR_FDO *((volatile uint8_t *)(0x42E00330UL)) +#define bFM_CANFD0_CCCR_FDBS *((volatile uint8_t *)(0x42E00334UL)) +#define bFM4_CANFD0_CCCR_FDBS *((volatile uint8_t *)(0x42E00334UL)) +#define bFM_CANFD0_CCCR_TXP *((volatile uint8_t *)(0x42E00338UL)) +#define bFM4_CANFD0_CCCR_TXP *((volatile uint8_t *)(0x42E00338UL)) + +#define bFM_CANFD0_ECR_RP *((volatile uint8_t *)(0x42E0083CUL)) +#define bFM4_CANFD0_ECR_RP *((volatile uint8_t *)(0x42E0083CUL)) + +#define bFM_CANFD0_FBTP_TDC *((volatile uint8_t *)(0x42E001DCUL)) +#define bFM4_CANFD0_FBTP_TDC *((volatile uint8_t *)(0x42E001DCUL)) + +#define bFM_CANFD0_FDECR_SEIE *((volatile uint8_t *)(0x42E04000UL)) +#define bFM4_CANFD0_FDECR_SEIE *((volatile uint8_t *)(0x42E04000UL)) +#define bFM_CANFD0_FDECR_DEIE *((volatile uint8_t *)(0x42E04004UL)) +#define bFM4_CANFD0_FDECR_DEIE *((volatile uint8_t *)(0x42E04004UL)) +#define bFM_CANFD0_FDECR_CEREN *((volatile uint8_t *)(0x42E04008UL)) +#define bFM4_CANFD0_FDECR_CEREN *((volatile uint8_t *)(0x42E04008UL)) +#define bFM_CANFD0_FDECR_CEIV *((volatile uint8_t *)(0x42E0400CUL)) +#define bFM4_CANFD0_FDECR_CEIV *((volatile uint8_t *)(0x42E0400CUL)) + +#define bFM_CANFD0_FDESCR_SEIC *((volatile uint8_t *)(0x42E040A0UL)) +#define bFM4_CANFD0_FDESCR_SEIC *((volatile uint8_t *)(0x42E040A0UL)) +#define bFM_CANFD0_FDESCR_DEIC *((volatile uint8_t *)(0x42E040A4UL)) +#define bFM4_CANFD0_FDESCR_DEIC *((volatile uint8_t *)(0x42E040A4UL)) + +#define bFM_CANFD0_FDESR_SEI *((volatile uint8_t *)(0x42E04020UL)) +#define bFM4_CANFD0_FDESR_SEI *((volatile uint8_t *)(0x42E04020UL)) +#define bFM_CANFD0_FDESR_DEI *((volatile uint8_t *)(0x42E04024UL)) +#define bFM4_CANFD0_FDESR_DEI *((volatile uint8_t *)(0x42E04024UL)) + +#define bFM_CANFD0_GFC_RRFE *((volatile uint8_t *)(0x42E01000UL)) +#define bFM4_CANFD0_GFC_RRFE *((volatile uint8_t *)(0x42E01000UL)) +#define bFM_CANFD0_GFC_RRFS *((volatile uint8_t *)(0x42E01004UL)) +#define bFM4_CANFD0_GFC_RRFS *((volatile uint8_t *)(0x42E01004UL)) + +#define bFM_CANFD0_HPMS_FLST *((volatile uint8_t *)(0x42E012BCUL)) +#define bFM4_CANFD0_HPMS_FLST *((volatile uint8_t *)(0x42E012BCUL)) + +#define bFM_CANFD0_IE_RF0NE *((volatile uint8_t *)(0x42E00A80UL)) +#define bFM4_CANFD0_IE_RF0NE *((volatile uint8_t *)(0x42E00A80UL)) +#define bFM_CANFD0_IE_RF0WE *((volatile uint8_t *)(0x42E00A84UL)) +#define bFM4_CANFD0_IE_RF0WE *((volatile uint8_t *)(0x42E00A84UL)) +#define bFM_CANFD0_IE_RF0FE *((volatile uint8_t *)(0x42E00A88UL)) +#define bFM4_CANFD0_IE_RF0FE *((volatile uint8_t *)(0x42E00A88UL)) +#define bFM_CANFD0_IE_RF0LE *((volatile uint8_t *)(0x42E00A8CUL)) +#define bFM4_CANFD0_IE_RF0LE *((volatile uint8_t *)(0x42E00A8CUL)) +#define bFM_CANFD0_IE_RF1NE *((volatile uint8_t *)(0x42E00A90UL)) +#define bFM4_CANFD0_IE_RF1NE *((volatile uint8_t *)(0x42E00A90UL)) +#define bFM_CANFD0_IE_RF1WE *((volatile uint8_t *)(0x42E00A94UL)) +#define bFM4_CANFD0_IE_RF1WE *((volatile uint8_t *)(0x42E00A94UL)) +#define bFM_CANFD0_IE_RF1FE *((volatile uint8_t *)(0x42E00A98UL)) +#define bFM4_CANFD0_IE_RF1FE *((volatile uint8_t *)(0x42E00A98UL)) +#define bFM_CANFD0_IE_RF1LE *((volatile uint8_t *)(0x42E00A9CUL)) +#define bFM4_CANFD0_IE_RF1LE *((volatile uint8_t *)(0x42E00A9CUL)) +#define bFM_CANFD0_IE_HPME *((volatile uint8_t *)(0x42E00AA0UL)) +#define bFM4_CANFD0_IE_HPME *((volatile uint8_t *)(0x42E00AA0UL)) +#define bFM_CANFD0_IE_TCE *((volatile uint8_t *)(0x42E00AA4UL)) +#define bFM4_CANFD0_IE_TCE *((volatile uint8_t *)(0x42E00AA4UL)) +#define bFM_CANFD0_IE_TCFE *((volatile uint8_t *)(0x42E00AA8UL)) +#define bFM4_CANFD0_IE_TCFE *((volatile uint8_t *)(0x42E00AA8UL)) +#define bFM_CANFD0_IE_TFEE *((volatile uint8_t *)(0x42E00AACUL)) +#define bFM4_CANFD0_IE_TFEE *((volatile uint8_t *)(0x42E00AACUL)) +#define bFM_CANFD0_IE_TEFNE *((volatile uint8_t *)(0x42E00AB0UL)) +#define bFM4_CANFD0_IE_TEFNE *((volatile uint8_t *)(0x42E00AB0UL)) +#define bFM_CANFD0_IE_TEFWE *((volatile uint8_t *)(0x42E00AB4UL)) +#define bFM4_CANFD0_IE_TEFWE *((volatile uint8_t *)(0x42E00AB4UL)) +#define bFM_CANFD0_IE_TEFFE *((volatile uint8_t *)(0x42E00AB8UL)) +#define bFM4_CANFD0_IE_TEFFE *((volatile uint8_t *)(0x42E00AB8UL)) +#define bFM_CANFD0_IE_TEFLE *((volatile uint8_t *)(0x42E00ABCUL)) +#define bFM4_CANFD0_IE_TEFLE *((volatile uint8_t *)(0x42E00ABCUL)) +#define bFM_CANFD0_IE_TSWE *((volatile uint8_t *)(0x42E00AC0UL)) +#define bFM4_CANFD0_IE_TSWE *((volatile uint8_t *)(0x42E00AC0UL)) +#define bFM_CANFD0_IE_MRAFE *((volatile uint8_t *)(0x42E00AC4UL)) +#define bFM4_CANFD0_IE_MRAFE *((volatile uint8_t *)(0x42E00AC4UL)) +#define bFM_CANFD0_IE_TOOE *((volatile uint8_t *)(0x42E00AC8UL)) +#define bFM4_CANFD0_IE_TOOE *((volatile uint8_t *)(0x42E00AC8UL)) +#define bFM_CANFD0_IE_DRXE *((volatile uint8_t *)(0x42E00ACCUL)) +#define bFM4_CANFD0_IE_DRXE *((volatile uint8_t *)(0x42E00ACCUL)) +#define bFM_CANFD0_IE_BECE *((volatile uint8_t *)(0x42E00AD0UL)) +#define bFM4_CANFD0_IE_BECE *((volatile uint8_t *)(0x42E00AD0UL)) +#define bFM_CANFD0_IE_BEUE *((volatile uint8_t *)(0x42E00AD4UL)) +#define bFM4_CANFD0_IE_BEUE *((volatile uint8_t *)(0x42E00AD4UL)) +#define bFM_CANFD0_IE_ELOE *((volatile uint8_t *)(0x42E00AD8UL)) +#define bFM4_CANFD0_IE_ELOE *((volatile uint8_t *)(0x42E00AD8UL)) +#define bFM_CANFD0_IE_EPE *((volatile uint8_t *)(0x42E00ADCUL)) +#define bFM4_CANFD0_IE_EPE *((volatile uint8_t *)(0x42E00ADCUL)) +#define bFM_CANFD0_IE_EWE *((volatile uint8_t *)(0x42E00AE0UL)) +#define bFM4_CANFD0_IE_EWE *((volatile uint8_t *)(0x42E00AE0UL)) +#define bFM_CANFD0_IE_BOE *((volatile uint8_t *)(0x42E00AE4UL)) +#define bFM4_CANFD0_IE_BOE *((volatile uint8_t *)(0x42E00AE4UL)) +#define bFM_CANFD0_IE_WDIE *((volatile uint8_t *)(0x42E00AE8UL)) +#define bFM4_CANFD0_IE_WDIE *((volatile uint8_t *)(0x42E00AE8UL)) +#define bFM_CANFD0_IE_CRCEE *((volatile uint8_t *)(0x42E00AECUL)) +#define bFM4_CANFD0_IE_CRCEE *((volatile uint8_t *)(0x42E00AECUL)) +#define bFM_CANFD0_IE_BEE *((volatile uint8_t *)(0x42E00AF0UL)) +#define bFM4_CANFD0_IE_BEE *((volatile uint8_t *)(0x42E00AF0UL)) +#define bFM_CANFD0_IE_ACKEE *((volatile uint8_t *)(0x42E00AF4UL)) +#define bFM4_CANFD0_IE_ACKEE *((volatile uint8_t *)(0x42E00AF4UL)) +#define bFM_CANFD0_IE_FOEE *((volatile uint8_t *)(0x42E00AF8UL)) +#define bFM4_CANFD0_IE_FOEE *((volatile uint8_t *)(0x42E00AF8UL)) +#define bFM_CANFD0_IE_STEE *((volatile uint8_t *)(0x42E00AFCUL)) +#define bFM4_CANFD0_IE_STEE *((volatile uint8_t *)(0x42E00AFCUL)) + +#define bFM_CANFD0_ILE_EINT0 *((volatile uint8_t *)(0x42E00B80UL)) +#define bFM4_CANFD0_ILE_EINT0 *((volatile uint8_t *)(0x42E00B80UL)) +#define bFM_CANFD0_ILE_EINT1 *((volatile uint8_t *)(0x42E00B84UL)) +#define bFM4_CANFD0_ILE_EINT1 *((volatile uint8_t *)(0x42E00B84UL)) + +#define bFM_CANFD0_ILS_RF0NL *((volatile uint8_t *)(0x42E00B00UL)) +#define bFM4_CANFD0_ILS_RF0NL *((volatile uint8_t *)(0x42E00B00UL)) +#define bFM_CANFD0_ILS_RF0WL *((volatile uint8_t *)(0x42E00B04UL)) +#define bFM4_CANFD0_ILS_RF0WL *((volatile uint8_t *)(0x42E00B04UL)) +#define bFM_CANFD0_ILS_RF0FL *((volatile uint8_t *)(0x42E00B08UL)) +#define bFM4_CANFD0_ILS_RF0FL *((volatile uint8_t *)(0x42E00B08UL)) +#define bFM_CANFD0_ILS_RF0LL *((volatile uint8_t *)(0x42E00B0CUL)) +#define bFM4_CANFD0_ILS_RF0LL *((volatile uint8_t *)(0x42E00B0CUL)) +#define bFM_CANFD0_ILS_RF1NL *((volatile uint8_t *)(0x42E00B10UL)) +#define bFM4_CANFD0_ILS_RF1NL *((volatile uint8_t *)(0x42E00B10UL)) +#define bFM_CANFD0_ILS_RF1WL *((volatile uint8_t *)(0x42E00B14UL)) +#define bFM4_CANFD0_ILS_RF1WL *((volatile uint8_t *)(0x42E00B14UL)) +#define bFM_CANFD0_ILS_RF1FL *((volatile uint8_t *)(0x42E00B18UL)) +#define bFM4_CANFD0_ILS_RF1FL *((volatile uint8_t *)(0x42E00B18UL)) +#define bFM_CANFD0_ILS_RF1LL *((volatile uint8_t *)(0x42E00B1CUL)) +#define bFM4_CANFD0_ILS_RF1LL *((volatile uint8_t *)(0x42E00B1CUL)) +#define bFM_CANFD0_ILS_HPML *((volatile uint8_t *)(0x42E00B20UL)) +#define bFM4_CANFD0_ILS_HPML *((volatile uint8_t *)(0x42E00B20UL)) +#define bFM_CANFD0_ILS_TCL *((volatile uint8_t *)(0x42E00B24UL)) +#define bFM4_CANFD0_ILS_TCL *((volatile uint8_t *)(0x42E00B24UL)) +#define bFM_CANFD0_ILS_TCFL *((volatile uint8_t *)(0x42E00B28UL)) +#define bFM4_CANFD0_ILS_TCFL *((volatile uint8_t *)(0x42E00B28UL)) +#define bFM_CANFD0_ILS_TFEL *((volatile uint8_t *)(0x42E00B2CUL)) +#define bFM4_CANFD0_ILS_TFEL *((volatile uint8_t *)(0x42E00B2CUL)) +#define bFM_CANFD0_ILS_TEFNL *((volatile uint8_t *)(0x42E00B30UL)) +#define bFM4_CANFD0_ILS_TEFNL *((volatile uint8_t *)(0x42E00B30UL)) +#define bFM_CANFD0_ILS_TEFWL *((volatile uint8_t *)(0x42E00B34UL)) +#define bFM4_CANFD0_ILS_TEFWL *((volatile uint8_t *)(0x42E00B34UL)) +#define bFM_CANFD0_ILS_TEFFL *((volatile uint8_t *)(0x42E00B38UL)) +#define bFM4_CANFD0_ILS_TEFFL *((volatile uint8_t *)(0x42E00B38UL)) +#define bFM_CANFD0_ILS_TEFLL *((volatile uint8_t *)(0x42E00B3CUL)) +#define bFM4_CANFD0_ILS_TEFLL *((volatile uint8_t *)(0x42E00B3CUL)) +#define bFM_CANFD0_ILS_TSWL *((volatile uint8_t *)(0x42E00B40UL)) +#define bFM4_CANFD0_ILS_TSWL *((volatile uint8_t *)(0x42E00B40UL)) +#define bFM_CANFD0_ILS_MRAFL *((volatile uint8_t *)(0x42E00B44UL)) +#define bFM4_CANFD0_ILS_MRAFL *((volatile uint8_t *)(0x42E00B44UL)) +#define bFM_CANFD0_ILS_TOOL *((volatile uint8_t *)(0x42E00B48UL)) +#define bFM4_CANFD0_ILS_TOOL *((volatile uint8_t *)(0x42E00B48UL)) +#define bFM_CANFD0_ILS_DRXL *((volatile uint8_t *)(0x42E00B4CUL)) +#define bFM4_CANFD0_ILS_DRXL *((volatile uint8_t *)(0x42E00B4CUL)) +#define bFM_CANFD0_ILS_BECL *((volatile uint8_t *)(0x42E00B50UL)) +#define bFM4_CANFD0_ILS_BECL *((volatile uint8_t *)(0x42E00B50UL)) +#define bFM_CANFD0_ILS_BEUL *((volatile uint8_t *)(0x42E00B54UL)) +#define bFM4_CANFD0_ILS_BEUL *((volatile uint8_t *)(0x42E00B54UL)) +#define bFM_CANFD0_ILS_ELOL *((volatile uint8_t *)(0x42E00B58UL)) +#define bFM4_CANFD0_ILS_ELOL *((volatile uint8_t *)(0x42E00B58UL)) +#define bFM_CANFD0_ILS_EPL *((volatile uint8_t *)(0x42E00B5CUL)) +#define bFM4_CANFD0_ILS_EPL *((volatile uint8_t *)(0x42E00B5CUL)) +#define bFM_CANFD0_ILS_EWL *((volatile uint8_t *)(0x42E00B60UL)) +#define bFM4_CANFD0_ILS_EWL *((volatile uint8_t *)(0x42E00B60UL)) +#define bFM_CANFD0_ILS_BOL *((volatile uint8_t *)(0x42E00B64UL)) +#define bFM4_CANFD0_ILS_BOL *((volatile uint8_t *)(0x42E00B64UL)) +#define bFM_CANFD0_ILS_WDIL *((volatile uint8_t *)(0x42E00B68UL)) +#define bFM4_CANFD0_ILS_WDIL *((volatile uint8_t *)(0x42E00B68UL)) +#define bFM_CANFD0_ILS_CRCEL *((volatile uint8_t *)(0x42E00B6CUL)) +#define bFM4_CANFD0_ILS_CRCEL *((volatile uint8_t *)(0x42E00B6CUL)) +#define bFM_CANFD0_ILS_BEL *((volatile uint8_t *)(0x42E00B70UL)) +#define bFM4_CANFD0_ILS_BEL *((volatile uint8_t *)(0x42E00B70UL)) +#define bFM_CANFD0_ILS_ACKEL *((volatile uint8_t *)(0x42E00B74UL)) +#define bFM4_CANFD0_ILS_ACKEL *((volatile uint8_t *)(0x42E00B74UL)) +#define bFM_CANFD0_ILS_FOEL *((volatile uint8_t *)(0x42E00B78UL)) +#define bFM4_CANFD0_ILS_FOEL *((volatile uint8_t *)(0x42E00B78UL)) +#define bFM_CANFD0_ILS_STEL *((volatile uint8_t *)(0x42E00B7CUL)) +#define bFM4_CANFD0_ILS_STEL *((volatile uint8_t *)(0x42E00B7CUL)) + +#define bFM_CANFD0_IR_RF0N *((volatile uint8_t *)(0x42E00A00UL)) +#define bFM4_CANFD0_IR_RF0N *((volatile uint8_t *)(0x42E00A00UL)) +#define bFM_CANFD0_IR_RF0W *((volatile uint8_t *)(0x42E00A04UL)) +#define bFM4_CANFD0_IR_RF0W *((volatile uint8_t *)(0x42E00A04UL)) +#define bFM_CANFD0_IR_RF0F *((volatile uint8_t *)(0x42E00A08UL)) +#define bFM4_CANFD0_IR_RF0F *((volatile uint8_t *)(0x42E00A08UL)) +#define bFM_CANFD0_IR_RF0L *((volatile uint8_t *)(0x42E00A0CUL)) +#define bFM4_CANFD0_IR_RF0L *((volatile uint8_t *)(0x42E00A0CUL)) +#define bFM_CANFD0_IR_RF1N *((volatile uint8_t *)(0x42E00A10UL)) +#define bFM4_CANFD0_IR_RF1N *((volatile uint8_t *)(0x42E00A10UL)) +#define bFM_CANFD0_IR_RF1W *((volatile uint8_t *)(0x42E00A14UL)) +#define bFM4_CANFD0_IR_RF1W *((volatile uint8_t *)(0x42E00A14UL)) +#define bFM_CANFD0_IR_RF1F *((volatile uint8_t *)(0x42E00A18UL)) +#define bFM4_CANFD0_IR_RF1F *((volatile uint8_t *)(0x42E00A18UL)) +#define bFM_CANFD0_IR_RF1L *((volatile uint8_t *)(0x42E00A1CUL)) +#define bFM4_CANFD0_IR_RF1L *((volatile uint8_t *)(0x42E00A1CUL)) +#define bFM_CANFD0_IR_HPM *((volatile uint8_t *)(0x42E00A20UL)) +#define bFM4_CANFD0_IR_HPM *((volatile uint8_t *)(0x42E00A20UL)) +#define bFM_CANFD0_IR_TC *((volatile uint8_t *)(0x42E00A24UL)) +#define bFM4_CANFD0_IR_TC *((volatile uint8_t *)(0x42E00A24UL)) +#define bFM_CANFD0_IR_TCF *((volatile uint8_t *)(0x42E00A28UL)) +#define bFM4_CANFD0_IR_TCF *((volatile uint8_t *)(0x42E00A28UL)) +#define bFM_CANFD0_IR_TFE *((volatile uint8_t *)(0x42E00A2CUL)) +#define bFM4_CANFD0_IR_TFE *((volatile uint8_t *)(0x42E00A2CUL)) +#define bFM_CANFD0_IR_TEFN *((volatile uint8_t *)(0x42E00A30UL)) +#define bFM4_CANFD0_IR_TEFN *((volatile uint8_t *)(0x42E00A30UL)) +#define bFM_CANFD0_IR_TEFW *((volatile uint8_t *)(0x42E00A34UL)) +#define bFM4_CANFD0_IR_TEFW *((volatile uint8_t *)(0x42E00A34UL)) +#define bFM_CANFD0_IR_TEFF *((volatile uint8_t *)(0x42E00A38UL)) +#define bFM4_CANFD0_IR_TEFF *((volatile uint8_t *)(0x42E00A38UL)) +#define bFM_CANFD0_IR_TEFL *((volatile uint8_t *)(0x42E00A3CUL)) +#define bFM4_CANFD0_IR_TEFL *((volatile uint8_t *)(0x42E00A3CUL)) +#define bFM_CANFD0_IR_TSW *((volatile uint8_t *)(0x42E00A40UL)) +#define bFM4_CANFD0_IR_TSW *((volatile uint8_t *)(0x42E00A40UL)) +#define bFM_CANFD0_IR_MRAF *((volatile uint8_t *)(0x42E00A44UL)) +#define bFM4_CANFD0_IR_MRAF *((volatile uint8_t *)(0x42E00A44UL)) +#define bFM_CANFD0_IR_TOO *((volatile uint8_t *)(0x42E00A48UL)) +#define bFM4_CANFD0_IR_TOO *((volatile uint8_t *)(0x42E00A48UL)) +#define bFM_CANFD0_IR_DRX *((volatile uint8_t *)(0x42E00A4CUL)) +#define bFM4_CANFD0_IR_DRX *((volatile uint8_t *)(0x42E00A4CUL)) +#define bFM_CANFD0_IR_BEC *((volatile uint8_t *)(0x42E00A50UL)) +#define bFM4_CANFD0_IR_BEC *((volatile uint8_t *)(0x42E00A50UL)) +#define bFM_CANFD0_IR_BEU *((volatile uint8_t *)(0x42E00A54UL)) +#define bFM4_CANFD0_IR_BEU *((volatile uint8_t *)(0x42E00A54UL)) +#define bFM_CANFD0_IR_ELO *((volatile uint8_t *)(0x42E00A58UL)) +#define bFM4_CANFD0_IR_ELO *((volatile uint8_t *)(0x42E00A58UL)) +#define bFM_CANFD0_IR_EP *((volatile uint8_t *)(0x42E00A5CUL)) +#define bFM4_CANFD0_IR_EP *((volatile uint8_t *)(0x42E00A5CUL)) +#define bFM_CANFD0_IR_EW *((volatile uint8_t *)(0x42E00A60UL)) +#define bFM4_CANFD0_IR_EW *((volatile uint8_t *)(0x42E00A60UL)) +#define bFM_CANFD0_IR_BO *((volatile uint8_t *)(0x42E00A64UL)) +#define bFM4_CANFD0_IR_BO *((volatile uint8_t *)(0x42E00A64UL)) +#define bFM_CANFD0_IR_WDI *((volatile uint8_t *)(0x42E00A68UL)) +#define bFM4_CANFD0_IR_WDI *((volatile uint8_t *)(0x42E00A68UL)) +#define bFM_CANFD0_IR_CRCE *((volatile uint8_t *)(0x42E00A6CUL)) +#define bFM4_CANFD0_IR_CRCE *((volatile uint8_t *)(0x42E00A6CUL)) +#define bFM_CANFD0_IR_BE *((volatile uint8_t *)(0x42E00A70UL)) +#define bFM4_CANFD0_IR_BE *((volatile uint8_t *)(0x42E00A70UL)) +#define bFM_CANFD0_IR_ACKE *((volatile uint8_t *)(0x42E00A74UL)) +#define bFM4_CANFD0_IR_ACKE *((volatile uint8_t *)(0x42E00A74UL)) +#define bFM_CANFD0_IR_FOE *((volatile uint8_t *)(0x42E00A78UL)) +#define bFM4_CANFD0_IR_FOE *((volatile uint8_t *)(0x42E00A78UL)) +#define bFM_CANFD0_IR_STE *((volatile uint8_t *)(0x42E00A7CUL)) +#define bFM4_CANFD0_IR_STE *((volatile uint8_t *)(0x42E00A7CUL)) + +#define bFM_CANFD0_NDAT1_ND0 *((volatile uint8_t *)(0x42E01300UL)) +#define bFM4_CANFD0_NDAT1_ND0 *((volatile uint8_t *)(0x42E01300UL)) +#define bFM_CANFD0_NDAT1_ND1 *((volatile uint8_t *)(0x42E01304UL)) +#define bFM4_CANFD0_NDAT1_ND1 *((volatile uint8_t *)(0x42E01304UL)) +#define bFM_CANFD0_NDAT1_ND2 *((volatile uint8_t *)(0x42E01308UL)) +#define bFM4_CANFD0_NDAT1_ND2 *((volatile uint8_t *)(0x42E01308UL)) +#define bFM_CANFD0_NDAT1_ND3 *((volatile uint8_t *)(0x42E0130CUL)) +#define bFM4_CANFD0_NDAT1_ND3 *((volatile uint8_t *)(0x42E0130CUL)) +#define bFM_CANFD0_NDAT1_ND4 *((volatile uint8_t *)(0x42E01310UL)) +#define bFM4_CANFD0_NDAT1_ND4 *((volatile uint8_t *)(0x42E01310UL)) +#define bFM_CANFD0_NDAT1_ND5 *((volatile uint8_t *)(0x42E01314UL)) +#define bFM4_CANFD0_NDAT1_ND5 *((volatile uint8_t *)(0x42E01314UL)) +#define bFM_CANFD0_NDAT1_ND6 *((volatile uint8_t *)(0x42E01318UL)) +#define bFM4_CANFD0_NDAT1_ND6 *((volatile uint8_t *)(0x42E01318UL)) +#define bFM_CANFD0_NDAT1_ND7 *((volatile uint8_t *)(0x42E0131CUL)) +#define bFM4_CANFD0_NDAT1_ND7 *((volatile uint8_t *)(0x42E0131CUL)) +#define bFM_CANFD0_NDAT1_ND8 *((volatile uint8_t *)(0x42E01320UL)) +#define bFM4_CANFD0_NDAT1_ND8 *((volatile uint8_t *)(0x42E01320UL)) +#define bFM_CANFD0_NDAT1_ND9 *((volatile uint8_t *)(0x42E01324UL)) +#define bFM4_CANFD0_NDAT1_ND9 *((volatile uint8_t *)(0x42E01324UL)) +#define bFM_CANFD0_NDAT1_ND10 *((volatile uint8_t *)(0x42E01328UL)) +#define bFM4_CANFD0_NDAT1_ND10 *((volatile uint8_t *)(0x42E01328UL)) +#define bFM_CANFD0_NDAT1_ND11 *((volatile uint8_t *)(0x42E0132CUL)) +#define bFM4_CANFD0_NDAT1_ND11 *((volatile uint8_t *)(0x42E0132CUL)) +#define bFM_CANFD0_NDAT1_ND12 *((volatile uint8_t *)(0x42E01330UL)) +#define bFM4_CANFD0_NDAT1_ND12 *((volatile uint8_t *)(0x42E01330UL)) +#define bFM_CANFD0_NDAT1_ND13 *((volatile uint8_t *)(0x42E01334UL)) +#define bFM4_CANFD0_NDAT1_ND13 *((volatile uint8_t *)(0x42E01334UL)) +#define bFM_CANFD0_NDAT1_ND14 *((volatile uint8_t *)(0x42E01338UL)) +#define bFM4_CANFD0_NDAT1_ND14 *((volatile uint8_t *)(0x42E01338UL)) +#define bFM_CANFD0_NDAT1_ND15 *((volatile uint8_t *)(0x42E0133CUL)) +#define bFM4_CANFD0_NDAT1_ND15 *((volatile uint8_t *)(0x42E0133CUL)) +#define bFM_CANFD0_NDAT1_ND16 *((volatile uint8_t *)(0x42E01340UL)) +#define bFM4_CANFD0_NDAT1_ND16 *((volatile uint8_t *)(0x42E01340UL)) +#define bFM_CANFD0_NDAT1_ND17 *((volatile uint8_t *)(0x42E01344UL)) +#define bFM4_CANFD0_NDAT1_ND17 *((volatile uint8_t *)(0x42E01344UL)) +#define bFM_CANFD0_NDAT1_ND18 *((volatile uint8_t *)(0x42E01348UL)) +#define bFM4_CANFD0_NDAT1_ND18 *((volatile uint8_t *)(0x42E01348UL)) +#define bFM_CANFD0_NDAT1_ND19 *((volatile uint8_t *)(0x42E0134CUL)) +#define bFM4_CANFD0_NDAT1_ND19 *((volatile uint8_t *)(0x42E0134CUL)) +#define bFM_CANFD0_NDAT1_ND20 *((volatile uint8_t *)(0x42E01350UL)) +#define bFM4_CANFD0_NDAT1_ND20 *((volatile uint8_t *)(0x42E01350UL)) +#define bFM_CANFD0_NDAT1_ND21 *((volatile uint8_t *)(0x42E01354UL)) +#define bFM4_CANFD0_NDAT1_ND21 *((volatile uint8_t *)(0x42E01354UL)) +#define bFM_CANFD0_NDAT1_ND22 *((volatile uint8_t *)(0x42E01358UL)) +#define bFM4_CANFD0_NDAT1_ND22 *((volatile uint8_t *)(0x42E01358UL)) +#define bFM_CANFD0_NDAT1_ND23 *((volatile uint8_t *)(0x42E0135CUL)) +#define bFM4_CANFD0_NDAT1_ND23 *((volatile uint8_t *)(0x42E0135CUL)) +#define bFM_CANFD0_NDAT1_ND24 *((volatile uint8_t *)(0x42E01360UL)) +#define bFM4_CANFD0_NDAT1_ND24 *((volatile uint8_t *)(0x42E01360UL)) +#define bFM_CANFD0_NDAT1_ND25 *((volatile uint8_t *)(0x42E01364UL)) +#define bFM4_CANFD0_NDAT1_ND25 *((volatile uint8_t *)(0x42E01364UL)) +#define bFM_CANFD0_NDAT1_ND26 *((volatile uint8_t *)(0x42E01368UL)) +#define bFM4_CANFD0_NDAT1_ND26 *((volatile uint8_t *)(0x42E01368UL)) +#define bFM_CANFD0_NDAT1_ND27 *((volatile uint8_t *)(0x42E0136CUL)) +#define bFM4_CANFD0_NDAT1_ND27 *((volatile uint8_t *)(0x42E0136CUL)) +#define bFM_CANFD0_NDAT1_ND28 *((volatile uint8_t *)(0x42E01370UL)) +#define bFM4_CANFD0_NDAT1_ND28 *((volatile uint8_t *)(0x42E01370UL)) +#define bFM_CANFD0_NDAT1_ND29 *((volatile uint8_t *)(0x42E01374UL)) +#define bFM4_CANFD0_NDAT1_ND29 *((volatile uint8_t *)(0x42E01374UL)) +#define bFM_CANFD0_NDAT1_ND30 *((volatile uint8_t *)(0x42E01378UL)) +#define bFM4_CANFD0_NDAT1_ND30 *((volatile uint8_t *)(0x42E01378UL)) +#define bFM_CANFD0_NDAT1_ND31 *((volatile uint8_t *)(0x42E0137CUL)) +#define bFM4_CANFD0_NDAT1_ND31 *((volatile uint8_t *)(0x42E0137CUL)) + +#define bFM_CANFD0_NDAT2_ND32 *((volatile uint8_t *)(0x42E01380UL)) +#define bFM4_CANFD0_NDAT2_ND32 *((volatile uint8_t *)(0x42E01380UL)) +#define bFM_CANFD0_NDAT2_ND33 *((volatile uint8_t *)(0x42E01384UL)) +#define bFM4_CANFD0_NDAT2_ND33 *((volatile uint8_t *)(0x42E01384UL)) +#define bFM_CANFD0_NDAT2_ND34 *((volatile uint8_t *)(0x42E01388UL)) +#define bFM4_CANFD0_NDAT2_ND34 *((volatile uint8_t *)(0x42E01388UL)) +#define bFM_CANFD0_NDAT2_ND35 *((volatile uint8_t *)(0x42E0138CUL)) +#define bFM4_CANFD0_NDAT2_ND35 *((volatile uint8_t *)(0x42E0138CUL)) +#define bFM_CANFD0_NDAT2_ND36 *((volatile uint8_t *)(0x42E01390UL)) +#define bFM4_CANFD0_NDAT2_ND36 *((volatile uint8_t *)(0x42E01390UL)) +#define bFM_CANFD0_NDAT2_ND37 *((volatile uint8_t *)(0x42E01394UL)) +#define bFM4_CANFD0_NDAT2_ND37 *((volatile uint8_t *)(0x42E01394UL)) +#define bFM_CANFD0_NDAT2_ND38 *((volatile uint8_t *)(0x42E01398UL)) +#define bFM4_CANFD0_NDAT2_ND38 *((volatile uint8_t *)(0x42E01398UL)) +#define bFM_CANFD0_NDAT2_ND39 *((volatile uint8_t *)(0x42E0139CUL)) +#define bFM4_CANFD0_NDAT2_ND39 *((volatile uint8_t *)(0x42E0139CUL)) +#define bFM_CANFD0_NDAT2_ND40 *((volatile uint8_t *)(0x42E013A0UL)) +#define bFM4_CANFD0_NDAT2_ND40 *((volatile uint8_t *)(0x42E013A0UL)) +#define bFM_CANFD0_NDAT2_ND41 *((volatile uint8_t *)(0x42E013A4UL)) +#define bFM4_CANFD0_NDAT2_ND41 *((volatile uint8_t *)(0x42E013A4UL)) +#define bFM_CANFD0_NDAT2_ND42 *((volatile uint8_t *)(0x42E013A8UL)) +#define bFM4_CANFD0_NDAT2_ND42 *((volatile uint8_t *)(0x42E013A8UL)) +#define bFM_CANFD0_NDAT2_ND43 *((volatile uint8_t *)(0x42E013ACUL)) +#define bFM4_CANFD0_NDAT2_ND43 *((volatile uint8_t *)(0x42E013ACUL)) +#define bFM_CANFD0_NDAT2_ND44 *((volatile uint8_t *)(0x42E013B0UL)) +#define bFM4_CANFD0_NDAT2_ND44 *((volatile uint8_t *)(0x42E013B0UL)) +#define bFM_CANFD0_NDAT2_ND45 *((volatile uint8_t *)(0x42E013B4UL)) +#define bFM4_CANFD0_NDAT2_ND45 *((volatile uint8_t *)(0x42E013B4UL)) +#define bFM_CANFD0_NDAT2_ND46 *((volatile uint8_t *)(0x42E013B8UL)) +#define bFM4_CANFD0_NDAT2_ND46 *((volatile uint8_t *)(0x42E013B8UL)) +#define bFM_CANFD0_NDAT2_ND47 *((volatile uint8_t *)(0x42E013BCUL)) +#define bFM4_CANFD0_NDAT2_ND47 *((volatile uint8_t *)(0x42E013BCUL)) +#define bFM_CANFD0_NDAT2_ND48 *((volatile uint8_t *)(0x42E013C0UL)) +#define bFM4_CANFD0_NDAT2_ND48 *((volatile uint8_t *)(0x42E013C0UL)) +#define bFM_CANFD0_NDAT2_ND49 *((volatile uint8_t *)(0x42E013C4UL)) +#define bFM4_CANFD0_NDAT2_ND49 *((volatile uint8_t *)(0x42E013C4UL)) +#define bFM_CANFD0_NDAT2_ND50 *((volatile uint8_t *)(0x42E013C8UL)) +#define bFM4_CANFD0_NDAT2_ND50 *((volatile uint8_t *)(0x42E013C8UL)) +#define bFM_CANFD0_NDAT2_ND51 *((volatile uint8_t *)(0x42E013CCUL)) +#define bFM4_CANFD0_NDAT2_ND51 *((volatile uint8_t *)(0x42E013CCUL)) +#define bFM_CANFD0_NDAT2_ND52 *((volatile uint8_t *)(0x42E013D0UL)) +#define bFM4_CANFD0_NDAT2_ND52 *((volatile uint8_t *)(0x42E013D0UL)) +#define bFM_CANFD0_NDAT2_ND53 *((volatile uint8_t *)(0x42E013D4UL)) +#define bFM4_CANFD0_NDAT2_ND53 *((volatile uint8_t *)(0x42E013D4UL)) +#define bFM_CANFD0_NDAT2_ND54 *((volatile uint8_t *)(0x42E013D8UL)) +#define bFM4_CANFD0_NDAT2_ND54 *((volatile uint8_t *)(0x42E013D8UL)) +#define bFM_CANFD0_NDAT2_ND55 *((volatile uint8_t *)(0x42E013DCUL)) +#define bFM4_CANFD0_NDAT2_ND55 *((volatile uint8_t *)(0x42E013DCUL)) +#define bFM_CANFD0_NDAT2_ND56 *((volatile uint8_t *)(0x42E013E0UL)) +#define bFM4_CANFD0_NDAT2_ND56 *((volatile uint8_t *)(0x42E013E0UL)) +#define bFM_CANFD0_NDAT2_ND57 *((volatile uint8_t *)(0x42E013E4UL)) +#define bFM4_CANFD0_NDAT2_ND57 *((volatile uint8_t *)(0x42E013E4UL)) +#define bFM_CANFD0_NDAT2_ND58 *((volatile uint8_t *)(0x42E013E8UL)) +#define bFM4_CANFD0_NDAT2_ND58 *((volatile uint8_t *)(0x42E013E8UL)) +#define bFM_CANFD0_NDAT2_ND59 *((volatile uint8_t *)(0x42E013ECUL)) +#define bFM4_CANFD0_NDAT2_ND59 *((volatile uint8_t *)(0x42E013ECUL)) +#define bFM_CANFD0_NDAT2_ND60 *((volatile uint8_t *)(0x42E013F0UL)) +#define bFM4_CANFD0_NDAT2_ND60 *((volatile uint8_t *)(0x42E013F0UL)) +#define bFM_CANFD0_NDAT2_ND61 *((volatile uint8_t *)(0x42E013F4UL)) +#define bFM4_CANFD0_NDAT2_ND61 *((volatile uint8_t *)(0x42E013F4UL)) +#define bFM_CANFD0_NDAT2_ND62 *((volatile uint8_t *)(0x42E013F8UL)) +#define bFM4_CANFD0_NDAT2_ND62 *((volatile uint8_t *)(0x42E013F8UL)) +#define bFM_CANFD0_NDAT2_ND63 *((volatile uint8_t *)(0x42E013FCUL)) +#define bFM4_CANFD0_NDAT2_ND63 *((volatile uint8_t *)(0x42E013FCUL)) + +#define bFM_CANFD0_PSR_EP *((volatile uint8_t *)(0x42E00894UL)) +#define bFM4_CANFD0_PSR_EP *((volatile uint8_t *)(0x42E00894UL)) +#define bFM_CANFD0_PSR_EW *((volatile uint8_t *)(0x42E00898UL)) +#define bFM4_CANFD0_PSR_EW *((volatile uint8_t *)(0x42E00898UL)) +#define bFM_CANFD0_PSR_BO *((volatile uint8_t *)(0x42E0089CUL)) +#define bFM4_CANFD0_PSR_BO *((volatile uint8_t *)(0x42E0089CUL)) +#define bFM_CANFD0_PSR_RESI *((volatile uint8_t *)(0x42E008ACUL)) +#define bFM4_CANFD0_PSR_RESI *((volatile uint8_t *)(0x42E008ACUL)) +#define bFM_CANFD0_PSR_RBRS *((volatile uint8_t *)(0x42E008B0UL)) +#define bFM4_CANFD0_PSR_RBRS *((volatile uint8_t *)(0x42E008B0UL)) +#define bFM_CANFD0_PSR_REDL *((volatile uint8_t *)(0x42E008B4UL)) +#define bFM4_CANFD0_PSR_REDL *((volatile uint8_t *)(0x42E008B4UL)) + +#define bFM_CANFD0_RXF0C_F0OM *((volatile uint8_t *)(0x42E0147CUL)) +#define bFM4_CANFD0_RXF0C_F0OM *((volatile uint8_t *)(0x42E0147CUL)) + +#define bFM_CANFD0_RXF0S_F0F *((volatile uint8_t *)(0x42E014E0UL)) +#define bFM4_CANFD0_RXF0S_F0F *((volatile uint8_t *)(0x42E014E0UL)) +#define bFM_CANFD0_RXF0S_RF0L *((volatile uint8_t *)(0x42E014E4UL)) +#define bFM4_CANFD0_RXF0S_RF0L *((volatile uint8_t *)(0x42E014E4UL)) + +#define bFM_CANFD0_RXF1C_F1OM *((volatile uint8_t *)(0x42E0167CUL)) +#define bFM4_CANFD0_RXF1C_F1OM *((volatile uint8_t *)(0x42E0167CUL)) + +#define bFM_CANFD0_RXF1S_F1F *((volatile uint8_t *)(0x42E016E0UL)) +#define bFM4_CANFD0_RXF1S_F1F *((volatile uint8_t *)(0x42E016E0UL)) +#define bFM_CANFD0_RXF1S_RF1L *((volatile uint8_t *)(0x42E016E4UL)) +#define bFM4_CANFD0_RXF1S_RF1L *((volatile uint8_t *)(0x42E016E4UL)) + +#define bFM_CANFD0_TEST_LBCK *((volatile uint8_t *)(0x42E00210UL)) +#define bFM4_CANFD0_TEST_LBCK *((volatile uint8_t *)(0x42E00210UL)) +#define bFM_CANFD0_TEST_RX *((volatile uint8_t *)(0x42E0021CUL)) +#define bFM4_CANFD0_TEST_RX *((volatile uint8_t *)(0x42E0021CUL)) + +#define bFM_CANFD0_TOCC_ETOC *((volatile uint8_t *)(0x42E00500UL)) +#define bFM4_CANFD0_TOCC_ETOC *((volatile uint8_t *)(0x42E00500UL)) + +#define bFM_CANFD0_TSCNTR_CCLR *((volatile uint8_t *)(0x42E04200UL)) +#define bFM4_CANFD0_TSCNTR_CCLR *((volatile uint8_t *)(0x42E04200UL)) + +#define bFM_CANFD0_TSMDR_CNTEN *((volatile uint8_t *)(0x42E04240UL)) +#define bFM4_CANFD0_TSMDR_CNTEN *((volatile uint8_t *)(0x42E04240UL)) + +#define bFM_CANFD0_TXBAR_AR0 *((volatile uint8_t *)(0x42E01A00UL)) +#define bFM4_CANFD0_TXBAR_AR0 *((volatile uint8_t *)(0x42E01A00UL)) +#define bFM_CANFD0_TXBAR_AR1 *((volatile uint8_t *)(0x42E01A04UL)) +#define bFM4_CANFD0_TXBAR_AR1 *((volatile uint8_t *)(0x42E01A04UL)) +#define bFM_CANFD0_TXBAR_AR2 *((volatile uint8_t *)(0x42E01A08UL)) +#define bFM4_CANFD0_TXBAR_AR2 *((volatile uint8_t *)(0x42E01A08UL)) +#define bFM_CANFD0_TXBAR_AR3 *((volatile uint8_t *)(0x42E01A0CUL)) +#define bFM4_CANFD0_TXBAR_AR3 *((volatile uint8_t *)(0x42E01A0CUL)) +#define bFM_CANFD0_TXBAR_AR4 *((volatile uint8_t *)(0x42E01A10UL)) +#define bFM4_CANFD0_TXBAR_AR4 *((volatile uint8_t *)(0x42E01A10UL)) +#define bFM_CANFD0_TXBAR_AR5 *((volatile uint8_t *)(0x42E01A14UL)) +#define bFM4_CANFD0_TXBAR_AR5 *((volatile uint8_t *)(0x42E01A14UL)) +#define bFM_CANFD0_TXBAR_AR6 *((volatile uint8_t *)(0x42E01A18UL)) +#define bFM4_CANFD0_TXBAR_AR6 *((volatile uint8_t *)(0x42E01A18UL)) +#define bFM_CANFD0_TXBAR_AR7 *((volatile uint8_t *)(0x42E01A1CUL)) +#define bFM4_CANFD0_TXBAR_AR7 *((volatile uint8_t *)(0x42E01A1CUL)) +#define bFM_CANFD0_TXBAR_AR8 *((volatile uint8_t *)(0x42E01A20UL)) +#define bFM4_CANFD0_TXBAR_AR8 *((volatile uint8_t *)(0x42E01A20UL)) +#define bFM_CANFD0_TXBAR_AR9 *((volatile uint8_t *)(0x42E01A24UL)) +#define bFM4_CANFD0_TXBAR_AR9 *((volatile uint8_t *)(0x42E01A24UL)) +#define bFM_CANFD0_TXBAR_AR10 *((volatile uint8_t *)(0x42E01A28UL)) +#define bFM4_CANFD0_TXBAR_AR10 *((volatile uint8_t *)(0x42E01A28UL)) +#define bFM_CANFD0_TXBAR_AR11 *((volatile uint8_t *)(0x42E01A2CUL)) +#define bFM4_CANFD0_TXBAR_AR11 *((volatile uint8_t *)(0x42E01A2CUL)) +#define bFM_CANFD0_TXBAR_AR12 *((volatile uint8_t *)(0x42E01A30UL)) +#define bFM4_CANFD0_TXBAR_AR12 *((volatile uint8_t *)(0x42E01A30UL)) +#define bFM_CANFD0_TXBAR_AR13 *((volatile uint8_t *)(0x42E01A34UL)) +#define bFM4_CANFD0_TXBAR_AR13 *((volatile uint8_t *)(0x42E01A34UL)) +#define bFM_CANFD0_TXBAR_AR14 *((volatile uint8_t *)(0x42E01A38UL)) +#define bFM4_CANFD0_TXBAR_AR14 *((volatile uint8_t *)(0x42E01A38UL)) +#define bFM_CANFD0_TXBAR_AR15 *((volatile uint8_t *)(0x42E01A3CUL)) +#define bFM4_CANFD0_TXBAR_AR15 *((volatile uint8_t *)(0x42E01A3CUL)) +#define bFM_CANFD0_TXBAR_AR16 *((volatile uint8_t *)(0x42E01A40UL)) +#define bFM4_CANFD0_TXBAR_AR16 *((volatile uint8_t *)(0x42E01A40UL)) +#define bFM_CANFD0_TXBAR_AR17 *((volatile uint8_t *)(0x42E01A44UL)) +#define bFM4_CANFD0_TXBAR_AR17 *((volatile uint8_t *)(0x42E01A44UL)) +#define bFM_CANFD0_TXBAR_AR18 *((volatile uint8_t *)(0x42E01A48UL)) +#define bFM4_CANFD0_TXBAR_AR18 *((volatile uint8_t *)(0x42E01A48UL)) +#define bFM_CANFD0_TXBAR_AR19 *((volatile uint8_t *)(0x42E01A4CUL)) +#define bFM4_CANFD0_TXBAR_AR19 *((volatile uint8_t *)(0x42E01A4CUL)) +#define bFM_CANFD0_TXBAR_AR20 *((volatile uint8_t *)(0x42E01A50UL)) +#define bFM4_CANFD0_TXBAR_AR20 *((volatile uint8_t *)(0x42E01A50UL)) +#define bFM_CANFD0_TXBAR_AR21 *((volatile uint8_t *)(0x42E01A54UL)) +#define bFM4_CANFD0_TXBAR_AR21 *((volatile uint8_t *)(0x42E01A54UL)) +#define bFM_CANFD0_TXBAR_AR22 *((volatile uint8_t *)(0x42E01A58UL)) +#define bFM4_CANFD0_TXBAR_AR22 *((volatile uint8_t *)(0x42E01A58UL)) +#define bFM_CANFD0_TXBAR_AR23 *((volatile uint8_t *)(0x42E01A5CUL)) +#define bFM4_CANFD0_TXBAR_AR23 *((volatile uint8_t *)(0x42E01A5CUL)) +#define bFM_CANFD0_TXBAR_AR24 *((volatile uint8_t *)(0x42E01A60UL)) +#define bFM4_CANFD0_TXBAR_AR24 *((volatile uint8_t *)(0x42E01A60UL)) +#define bFM_CANFD0_TXBAR_AR25 *((volatile uint8_t *)(0x42E01A64UL)) +#define bFM4_CANFD0_TXBAR_AR25 *((volatile uint8_t *)(0x42E01A64UL)) +#define bFM_CANFD0_TXBAR_AR26 *((volatile uint8_t *)(0x42E01A68UL)) +#define bFM4_CANFD0_TXBAR_AR26 *((volatile uint8_t *)(0x42E01A68UL)) +#define bFM_CANFD0_TXBAR_AR27 *((volatile uint8_t *)(0x42E01A6CUL)) +#define bFM4_CANFD0_TXBAR_AR27 *((volatile uint8_t *)(0x42E01A6CUL)) +#define bFM_CANFD0_TXBAR_AR28 *((volatile uint8_t *)(0x42E01A70UL)) +#define bFM4_CANFD0_TXBAR_AR28 *((volatile uint8_t *)(0x42E01A70UL)) +#define bFM_CANFD0_TXBAR_AR29 *((volatile uint8_t *)(0x42E01A74UL)) +#define bFM4_CANFD0_TXBAR_AR29 *((volatile uint8_t *)(0x42E01A74UL)) +#define bFM_CANFD0_TXBAR_AR30 *((volatile uint8_t *)(0x42E01A78UL)) +#define bFM4_CANFD0_TXBAR_AR30 *((volatile uint8_t *)(0x42E01A78UL)) +#define bFM_CANFD0_TXBAR_AR31 *((volatile uint8_t *)(0x42E01A7CUL)) +#define bFM4_CANFD0_TXBAR_AR31 *((volatile uint8_t *)(0x42E01A7CUL)) + +#define bFM_CANFD0_TXBC_TFQM *((volatile uint8_t *)(0x42E01878UL)) +#define bFM4_CANFD0_TXBC_TFQM *((volatile uint8_t *)(0x42E01878UL)) + +#define bFM_CANFD0_TXBCF_CF0 *((volatile uint8_t *)(0x42E01B80UL)) +#define bFM4_CANFD0_TXBCF_CF0 *((volatile uint8_t *)(0x42E01B80UL)) +#define bFM_CANFD0_TXBCF_CF1 *((volatile uint8_t *)(0x42E01B84UL)) +#define bFM4_CANFD0_TXBCF_CF1 *((volatile uint8_t *)(0x42E01B84UL)) +#define bFM_CANFD0_TXBCF_CF2 *((volatile uint8_t *)(0x42E01B88UL)) +#define bFM4_CANFD0_TXBCF_CF2 *((volatile uint8_t *)(0x42E01B88UL)) +#define bFM_CANFD0_TXBCF_CF3 *((volatile uint8_t *)(0x42E01B8CUL)) +#define bFM4_CANFD0_TXBCF_CF3 *((volatile uint8_t *)(0x42E01B8CUL)) +#define bFM_CANFD0_TXBCF_CF4 *((volatile uint8_t *)(0x42E01B90UL)) +#define bFM4_CANFD0_TXBCF_CF4 *((volatile uint8_t *)(0x42E01B90UL)) +#define bFM_CANFD0_TXBCF_CF5 *((volatile uint8_t *)(0x42E01B94UL)) +#define bFM4_CANFD0_TXBCF_CF5 *((volatile uint8_t *)(0x42E01B94UL)) +#define bFM_CANFD0_TXBCF_CF6 *((volatile uint8_t *)(0x42E01B98UL)) +#define bFM4_CANFD0_TXBCF_CF6 *((volatile uint8_t *)(0x42E01B98UL)) +#define bFM_CANFD0_TXBCF_CF7 *((volatile uint8_t *)(0x42E01B9CUL)) +#define bFM4_CANFD0_TXBCF_CF7 *((volatile uint8_t *)(0x42E01B9CUL)) +#define bFM_CANFD0_TXBCF_CF8 *((volatile uint8_t *)(0x42E01BA0UL)) +#define bFM4_CANFD0_TXBCF_CF8 *((volatile uint8_t *)(0x42E01BA0UL)) +#define bFM_CANFD0_TXBCF_CF9 *((volatile uint8_t *)(0x42E01BA4UL)) +#define bFM4_CANFD0_TXBCF_CF9 *((volatile uint8_t *)(0x42E01BA4UL)) +#define bFM_CANFD0_TXBCF_CF10 *((volatile uint8_t *)(0x42E01BA8UL)) +#define bFM4_CANFD0_TXBCF_CF10 *((volatile uint8_t *)(0x42E01BA8UL)) +#define bFM_CANFD0_TXBCF_CF11 *((volatile uint8_t *)(0x42E01BACUL)) +#define bFM4_CANFD0_TXBCF_CF11 *((volatile uint8_t *)(0x42E01BACUL)) +#define bFM_CANFD0_TXBCF_CF12 *((volatile uint8_t *)(0x42E01BB0UL)) +#define bFM4_CANFD0_TXBCF_CF12 *((volatile uint8_t *)(0x42E01BB0UL)) +#define bFM_CANFD0_TXBCF_CF13 *((volatile uint8_t *)(0x42E01BB4UL)) +#define bFM4_CANFD0_TXBCF_CF13 *((volatile uint8_t *)(0x42E01BB4UL)) +#define bFM_CANFD0_TXBCF_CF14 *((volatile uint8_t *)(0x42E01BB8UL)) +#define bFM4_CANFD0_TXBCF_CF14 *((volatile uint8_t *)(0x42E01BB8UL)) +#define bFM_CANFD0_TXBCF_CF15 *((volatile uint8_t *)(0x42E01BBCUL)) +#define bFM4_CANFD0_TXBCF_CF15 *((volatile uint8_t *)(0x42E01BBCUL)) +#define bFM_CANFD0_TXBCF_CF16 *((volatile uint8_t *)(0x42E01BC0UL)) +#define bFM4_CANFD0_TXBCF_CF16 *((volatile uint8_t *)(0x42E01BC0UL)) +#define bFM_CANFD0_TXBCF_CF17 *((volatile uint8_t *)(0x42E01BC4UL)) +#define bFM4_CANFD0_TXBCF_CF17 *((volatile uint8_t *)(0x42E01BC4UL)) +#define bFM_CANFD0_TXBCF_CF18 *((volatile uint8_t *)(0x42E01BC8UL)) +#define bFM4_CANFD0_TXBCF_CF18 *((volatile uint8_t *)(0x42E01BC8UL)) +#define bFM_CANFD0_TXBCF_CF19 *((volatile uint8_t *)(0x42E01BCCUL)) +#define bFM4_CANFD0_TXBCF_CF19 *((volatile uint8_t *)(0x42E01BCCUL)) +#define bFM_CANFD0_TXBCF_CF20 *((volatile uint8_t *)(0x42E01BD0UL)) +#define bFM4_CANFD0_TXBCF_CF20 *((volatile uint8_t *)(0x42E01BD0UL)) +#define bFM_CANFD0_TXBCF_CF21 *((volatile uint8_t *)(0x42E01BD4UL)) +#define bFM4_CANFD0_TXBCF_CF21 *((volatile uint8_t *)(0x42E01BD4UL)) +#define bFM_CANFD0_TXBCF_CF22 *((volatile uint8_t *)(0x42E01BD8UL)) +#define bFM4_CANFD0_TXBCF_CF22 *((volatile uint8_t *)(0x42E01BD8UL)) +#define bFM_CANFD0_TXBCF_CF23 *((volatile uint8_t *)(0x42E01BDCUL)) +#define bFM4_CANFD0_TXBCF_CF23 *((volatile uint8_t *)(0x42E01BDCUL)) +#define bFM_CANFD0_TXBCF_CF24 *((volatile uint8_t *)(0x42E01BE0UL)) +#define bFM4_CANFD0_TXBCF_CF24 *((volatile uint8_t *)(0x42E01BE0UL)) +#define bFM_CANFD0_TXBCF_CF25 *((volatile uint8_t *)(0x42E01BE4UL)) +#define bFM4_CANFD0_TXBCF_CF25 *((volatile uint8_t *)(0x42E01BE4UL)) +#define bFM_CANFD0_TXBCF_CF26 *((volatile uint8_t *)(0x42E01BE8UL)) +#define bFM4_CANFD0_TXBCF_CF26 *((volatile uint8_t *)(0x42E01BE8UL)) +#define bFM_CANFD0_TXBCF_CF27 *((volatile uint8_t *)(0x42E01BECUL)) +#define bFM4_CANFD0_TXBCF_CF27 *((volatile uint8_t *)(0x42E01BECUL)) +#define bFM_CANFD0_TXBCF_CF28 *((volatile uint8_t *)(0x42E01BF0UL)) +#define bFM4_CANFD0_TXBCF_CF28 *((volatile uint8_t *)(0x42E01BF0UL)) +#define bFM_CANFD0_TXBCF_CF29 *((volatile uint8_t *)(0x42E01BF4UL)) +#define bFM4_CANFD0_TXBCF_CF29 *((volatile uint8_t *)(0x42E01BF4UL)) +#define bFM_CANFD0_TXBCF_CF30 *((volatile uint8_t *)(0x42E01BF8UL)) +#define bFM4_CANFD0_TXBCF_CF30 *((volatile uint8_t *)(0x42E01BF8UL)) +#define bFM_CANFD0_TXBCF_CF31 *((volatile uint8_t *)(0x42E01BFCUL)) +#define bFM4_CANFD0_TXBCF_CF31 *((volatile uint8_t *)(0x42E01BFCUL)) + +#define bFM_CANFD0_TXBCIE_CFIE0 *((volatile uint8_t *)(0x42E01C80UL)) +#define bFM4_CANFD0_TXBCIE_CFIE0 *((volatile uint8_t *)(0x42E01C80UL)) +#define bFM_CANFD0_TXBCIE_CFIE1 *((volatile uint8_t *)(0x42E01C84UL)) +#define bFM4_CANFD0_TXBCIE_CFIE1 *((volatile uint8_t *)(0x42E01C84UL)) +#define bFM_CANFD0_TXBCIE_CFIE2 *((volatile uint8_t *)(0x42E01C88UL)) +#define bFM4_CANFD0_TXBCIE_CFIE2 *((volatile uint8_t *)(0x42E01C88UL)) +#define bFM_CANFD0_TXBCIE_CFIE3 *((volatile uint8_t *)(0x42E01C8CUL)) +#define bFM4_CANFD0_TXBCIE_CFIE3 *((volatile uint8_t *)(0x42E01C8CUL)) +#define bFM_CANFD0_TXBCIE_CFIE4 *((volatile uint8_t *)(0x42E01C90UL)) +#define bFM4_CANFD0_TXBCIE_CFIE4 *((volatile uint8_t *)(0x42E01C90UL)) +#define bFM_CANFD0_TXBCIE_CFIE5 *((volatile uint8_t *)(0x42E01C94UL)) +#define bFM4_CANFD0_TXBCIE_CFIE5 *((volatile uint8_t *)(0x42E01C94UL)) +#define bFM_CANFD0_TXBCIE_CFIE6 *((volatile uint8_t *)(0x42E01C98UL)) +#define bFM4_CANFD0_TXBCIE_CFIE6 *((volatile uint8_t *)(0x42E01C98UL)) +#define bFM_CANFD0_TXBCIE_CFIE7 *((volatile uint8_t *)(0x42E01C9CUL)) +#define bFM4_CANFD0_TXBCIE_CFIE7 *((volatile uint8_t *)(0x42E01C9CUL)) +#define bFM_CANFD0_TXBCIE_CFIE8 *((volatile uint8_t *)(0x42E01CA0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE8 *((volatile uint8_t *)(0x42E01CA0UL)) +#define bFM_CANFD0_TXBCIE_CFIE9 *((volatile uint8_t *)(0x42E01CA4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE9 *((volatile uint8_t *)(0x42E01CA4UL)) +#define bFM_CANFD0_TXBCIE_CFIE10 *((volatile uint8_t *)(0x42E01CA8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE10 *((volatile uint8_t *)(0x42E01CA8UL)) +#define bFM_CANFD0_TXBCIE_CFIE11 *((volatile uint8_t *)(0x42E01CACUL)) +#define bFM4_CANFD0_TXBCIE_CFIE11 *((volatile uint8_t *)(0x42E01CACUL)) +#define bFM_CANFD0_TXBCIE_CFIE12 *((volatile uint8_t *)(0x42E01CB0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE12 *((volatile uint8_t *)(0x42E01CB0UL)) +#define bFM_CANFD0_TXBCIE_CFIE13 *((volatile uint8_t *)(0x42E01CB4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE13 *((volatile uint8_t *)(0x42E01CB4UL)) +#define bFM_CANFD0_TXBCIE_CFIE14 *((volatile uint8_t *)(0x42E01CB8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE14 *((volatile uint8_t *)(0x42E01CB8UL)) +#define bFM_CANFD0_TXBCIE_CFIE15 *((volatile uint8_t *)(0x42E01CBCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE15 *((volatile uint8_t *)(0x42E01CBCUL)) +#define bFM_CANFD0_TXBCIE_CFIE16 *((volatile uint8_t *)(0x42E01CC0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE16 *((volatile uint8_t *)(0x42E01CC0UL)) +#define bFM_CANFD0_TXBCIE_CFIE17 *((volatile uint8_t *)(0x42E01CC4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE17 *((volatile uint8_t *)(0x42E01CC4UL)) +#define bFM_CANFD0_TXBCIE_CFIE18 *((volatile uint8_t *)(0x42E01CC8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE18 *((volatile uint8_t *)(0x42E01CC8UL)) +#define bFM_CANFD0_TXBCIE_CFIE19 *((volatile uint8_t *)(0x42E01CCCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE19 *((volatile uint8_t *)(0x42E01CCCUL)) +#define bFM_CANFD0_TXBCIE_CFIE20 *((volatile uint8_t *)(0x42E01CD0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE20 *((volatile uint8_t *)(0x42E01CD0UL)) +#define bFM_CANFD0_TXBCIE_CFIE21 *((volatile uint8_t *)(0x42E01CD4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE21 *((volatile uint8_t *)(0x42E01CD4UL)) +#define bFM_CANFD0_TXBCIE_CFIE22 *((volatile uint8_t *)(0x42E01CD8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE22 *((volatile uint8_t *)(0x42E01CD8UL)) +#define bFM_CANFD0_TXBCIE_CFIE23 *((volatile uint8_t *)(0x42E01CDCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE23 *((volatile uint8_t *)(0x42E01CDCUL)) +#define bFM_CANFD0_TXBCIE_CFIE24 *((volatile uint8_t *)(0x42E01CE0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE24 *((volatile uint8_t *)(0x42E01CE0UL)) +#define bFM_CANFD0_TXBCIE_CFIE25 *((volatile uint8_t *)(0x42E01CE4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE25 *((volatile uint8_t *)(0x42E01CE4UL)) +#define bFM_CANFD0_TXBCIE_CFIE26 *((volatile uint8_t *)(0x42E01CE8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE26 *((volatile uint8_t *)(0x42E01CE8UL)) +#define bFM_CANFD0_TXBCIE_CFIE27 *((volatile uint8_t *)(0x42E01CECUL)) +#define bFM4_CANFD0_TXBCIE_CFIE27 *((volatile uint8_t *)(0x42E01CECUL)) +#define bFM_CANFD0_TXBCIE_CFIE28 *((volatile uint8_t *)(0x42E01CF0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE28 *((volatile uint8_t *)(0x42E01CF0UL)) +#define bFM_CANFD0_TXBCIE_CFIE29 *((volatile uint8_t *)(0x42E01CF4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE29 *((volatile uint8_t *)(0x42E01CF4UL)) +#define bFM_CANFD0_TXBCIE_CFIE30 *((volatile uint8_t *)(0x42E01CF8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE30 *((volatile uint8_t *)(0x42E01CF8UL)) +#define bFM_CANFD0_TXBCIE_CFIE31 *((volatile uint8_t *)(0x42E01CFCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE31 *((volatile uint8_t *)(0x42E01CFCUL)) + +#define bFM_CANFD0_TXBCR_CR0 *((volatile uint8_t *)(0x42E01A80UL)) +#define bFM4_CANFD0_TXBCR_CR0 *((volatile uint8_t *)(0x42E01A80UL)) +#define bFM_CANFD0_TXBCR_CR1 *((volatile uint8_t *)(0x42E01A84UL)) +#define bFM4_CANFD0_TXBCR_CR1 *((volatile uint8_t *)(0x42E01A84UL)) +#define bFM_CANFD0_TXBCR_CR2 *((volatile uint8_t *)(0x42E01A88UL)) +#define bFM4_CANFD0_TXBCR_CR2 *((volatile uint8_t *)(0x42E01A88UL)) +#define bFM_CANFD0_TXBCR_CR3 *((volatile uint8_t *)(0x42E01A8CUL)) +#define bFM4_CANFD0_TXBCR_CR3 *((volatile uint8_t *)(0x42E01A8CUL)) +#define bFM_CANFD0_TXBCR_CR4 *((volatile uint8_t *)(0x42E01A90UL)) +#define bFM4_CANFD0_TXBCR_CR4 *((volatile uint8_t *)(0x42E01A90UL)) +#define bFM_CANFD0_TXBCR_CR5 *((volatile uint8_t *)(0x42E01A94UL)) +#define bFM4_CANFD0_TXBCR_CR5 *((volatile uint8_t *)(0x42E01A94UL)) +#define bFM_CANFD0_TXBCR_CR6 *((volatile uint8_t *)(0x42E01A98UL)) +#define bFM4_CANFD0_TXBCR_CR6 *((volatile uint8_t *)(0x42E01A98UL)) +#define bFM_CANFD0_TXBCR_CR7 *((volatile uint8_t *)(0x42E01A9CUL)) +#define bFM4_CANFD0_TXBCR_CR7 *((volatile uint8_t *)(0x42E01A9CUL)) +#define bFM_CANFD0_TXBCR_CR8 *((volatile uint8_t *)(0x42E01AA0UL)) +#define bFM4_CANFD0_TXBCR_CR8 *((volatile uint8_t *)(0x42E01AA0UL)) +#define bFM_CANFD0_TXBCR_CR9 *((volatile uint8_t *)(0x42E01AA4UL)) +#define bFM4_CANFD0_TXBCR_CR9 *((volatile uint8_t *)(0x42E01AA4UL)) +#define bFM_CANFD0_TXBCR_CR10 *((volatile uint8_t *)(0x42E01AA8UL)) +#define bFM4_CANFD0_TXBCR_CR10 *((volatile uint8_t *)(0x42E01AA8UL)) +#define bFM_CANFD0_TXBCR_CR11 *((volatile uint8_t *)(0x42E01AACUL)) +#define bFM4_CANFD0_TXBCR_CR11 *((volatile uint8_t *)(0x42E01AACUL)) +#define bFM_CANFD0_TXBCR_CR12 *((volatile uint8_t *)(0x42E01AB0UL)) +#define bFM4_CANFD0_TXBCR_CR12 *((volatile uint8_t *)(0x42E01AB0UL)) +#define bFM_CANFD0_TXBCR_CR13 *((volatile uint8_t *)(0x42E01AB4UL)) +#define bFM4_CANFD0_TXBCR_CR13 *((volatile uint8_t *)(0x42E01AB4UL)) +#define bFM_CANFD0_TXBCR_CR14 *((volatile uint8_t *)(0x42E01AB8UL)) +#define bFM4_CANFD0_TXBCR_CR14 *((volatile uint8_t *)(0x42E01AB8UL)) +#define bFM_CANFD0_TXBCR_CR15 *((volatile uint8_t *)(0x42E01ABCUL)) +#define bFM4_CANFD0_TXBCR_CR15 *((volatile uint8_t *)(0x42E01ABCUL)) +#define bFM_CANFD0_TXBCR_CR16 *((volatile uint8_t *)(0x42E01AC0UL)) +#define bFM4_CANFD0_TXBCR_CR16 *((volatile uint8_t *)(0x42E01AC0UL)) +#define bFM_CANFD0_TXBCR_CR17 *((volatile uint8_t *)(0x42E01AC4UL)) +#define bFM4_CANFD0_TXBCR_CR17 *((volatile uint8_t *)(0x42E01AC4UL)) +#define bFM_CANFD0_TXBCR_CR18 *((volatile uint8_t *)(0x42E01AC8UL)) +#define bFM4_CANFD0_TXBCR_CR18 *((volatile uint8_t *)(0x42E01AC8UL)) +#define bFM_CANFD0_TXBCR_CR19 *((volatile uint8_t *)(0x42E01ACCUL)) +#define bFM4_CANFD0_TXBCR_CR19 *((volatile uint8_t *)(0x42E01ACCUL)) +#define bFM_CANFD0_TXBCR_CR20 *((volatile uint8_t *)(0x42E01AD0UL)) +#define bFM4_CANFD0_TXBCR_CR20 *((volatile uint8_t *)(0x42E01AD0UL)) +#define bFM_CANFD0_TXBCR_CR21 *((volatile uint8_t *)(0x42E01AD4UL)) +#define bFM4_CANFD0_TXBCR_CR21 *((volatile uint8_t *)(0x42E01AD4UL)) +#define bFM_CANFD0_TXBCR_CR22 *((volatile uint8_t *)(0x42E01AD8UL)) +#define bFM4_CANFD0_TXBCR_CR22 *((volatile uint8_t *)(0x42E01AD8UL)) +#define bFM_CANFD0_TXBCR_CR23 *((volatile uint8_t *)(0x42E01ADCUL)) +#define bFM4_CANFD0_TXBCR_CR23 *((volatile uint8_t *)(0x42E01ADCUL)) +#define bFM_CANFD0_TXBCR_CR24 *((volatile uint8_t *)(0x42E01AE0UL)) +#define bFM4_CANFD0_TXBCR_CR24 *((volatile uint8_t *)(0x42E01AE0UL)) +#define bFM_CANFD0_TXBCR_CR25 *((volatile uint8_t *)(0x42E01AE4UL)) +#define bFM4_CANFD0_TXBCR_CR25 *((volatile uint8_t *)(0x42E01AE4UL)) +#define bFM_CANFD0_TXBCR_CR26 *((volatile uint8_t *)(0x42E01AE8UL)) +#define bFM4_CANFD0_TXBCR_CR26 *((volatile uint8_t *)(0x42E01AE8UL)) +#define bFM_CANFD0_TXBCR_CR27 *((volatile uint8_t *)(0x42E01AECUL)) +#define bFM4_CANFD0_TXBCR_CR27 *((volatile uint8_t *)(0x42E01AECUL)) +#define bFM_CANFD0_TXBCR_CR28 *((volatile uint8_t *)(0x42E01AF0UL)) +#define bFM4_CANFD0_TXBCR_CR28 *((volatile uint8_t *)(0x42E01AF0UL)) +#define bFM_CANFD0_TXBCR_CR29 *((volatile uint8_t *)(0x42E01AF4UL)) +#define bFM4_CANFD0_TXBCR_CR29 *((volatile uint8_t *)(0x42E01AF4UL)) +#define bFM_CANFD0_TXBCR_CR30 *((volatile uint8_t *)(0x42E01AF8UL)) +#define bFM4_CANFD0_TXBCR_CR30 *((volatile uint8_t *)(0x42E01AF8UL)) +#define bFM_CANFD0_TXBCR_CR31 *((volatile uint8_t *)(0x42E01AFCUL)) +#define bFM4_CANFD0_TXBCR_CR31 *((volatile uint8_t *)(0x42E01AFCUL)) + +#define bFM_CANFD0_TXBRP_TRP0 *((volatile uint8_t *)(0x42E01980UL)) +#define bFM4_CANFD0_TXBRP_TRP0 *((volatile uint8_t *)(0x42E01980UL)) +#define bFM_CANFD0_TXBRP_TRP1 *((volatile uint8_t *)(0x42E01984UL)) +#define bFM4_CANFD0_TXBRP_TRP1 *((volatile uint8_t *)(0x42E01984UL)) +#define bFM_CANFD0_TXBRP_TRP2 *((volatile uint8_t *)(0x42E01988UL)) +#define bFM4_CANFD0_TXBRP_TRP2 *((volatile uint8_t *)(0x42E01988UL)) +#define bFM_CANFD0_TXBRP_TRP3 *((volatile uint8_t *)(0x42E0198CUL)) +#define bFM4_CANFD0_TXBRP_TRP3 *((volatile uint8_t *)(0x42E0198CUL)) +#define bFM_CANFD0_TXBRP_TRP4 *((volatile uint8_t *)(0x42E01990UL)) +#define bFM4_CANFD0_TXBRP_TRP4 *((volatile uint8_t *)(0x42E01990UL)) +#define bFM_CANFD0_TXBRP_TRP5 *((volatile uint8_t *)(0x42E01994UL)) +#define bFM4_CANFD0_TXBRP_TRP5 *((volatile uint8_t *)(0x42E01994UL)) +#define bFM_CANFD0_TXBRP_TRP6 *((volatile uint8_t *)(0x42E01998UL)) +#define bFM4_CANFD0_TXBRP_TRP6 *((volatile uint8_t *)(0x42E01998UL)) +#define bFM_CANFD0_TXBRP_TRP7 *((volatile uint8_t *)(0x42E0199CUL)) +#define bFM4_CANFD0_TXBRP_TRP7 *((volatile uint8_t *)(0x42E0199CUL)) +#define bFM_CANFD0_TXBRP_TRP8 *((volatile uint8_t *)(0x42E019A0UL)) +#define bFM4_CANFD0_TXBRP_TRP8 *((volatile uint8_t *)(0x42E019A0UL)) +#define bFM_CANFD0_TXBRP_TRP9 *((volatile uint8_t *)(0x42E019A4UL)) +#define bFM4_CANFD0_TXBRP_TRP9 *((volatile uint8_t *)(0x42E019A4UL)) +#define bFM_CANFD0_TXBRP_TRP10 *((volatile uint8_t *)(0x42E019A8UL)) +#define bFM4_CANFD0_TXBRP_TRP10 *((volatile uint8_t *)(0x42E019A8UL)) +#define bFM_CANFD0_TXBRP_TRP11 *((volatile uint8_t *)(0x42E019ACUL)) +#define bFM4_CANFD0_TXBRP_TRP11 *((volatile uint8_t *)(0x42E019ACUL)) +#define bFM_CANFD0_TXBRP_TRP12 *((volatile uint8_t *)(0x42E019B0UL)) +#define bFM4_CANFD0_TXBRP_TRP12 *((volatile uint8_t *)(0x42E019B0UL)) +#define bFM_CANFD0_TXBRP_TRP13 *((volatile uint8_t *)(0x42E019B4UL)) +#define bFM4_CANFD0_TXBRP_TRP13 *((volatile uint8_t *)(0x42E019B4UL)) +#define bFM_CANFD0_TXBRP_TRP14 *((volatile uint8_t *)(0x42E019B8UL)) +#define bFM4_CANFD0_TXBRP_TRP14 *((volatile uint8_t *)(0x42E019B8UL)) +#define bFM_CANFD0_TXBRP_TRP15 *((volatile uint8_t *)(0x42E019BCUL)) +#define bFM4_CANFD0_TXBRP_TRP15 *((volatile uint8_t *)(0x42E019BCUL)) +#define bFM_CANFD0_TXBRP_TRP16 *((volatile uint8_t *)(0x42E019C0UL)) +#define bFM4_CANFD0_TXBRP_TRP16 *((volatile uint8_t *)(0x42E019C0UL)) +#define bFM_CANFD0_TXBRP_TRP17 *((volatile uint8_t *)(0x42E019C4UL)) +#define bFM4_CANFD0_TXBRP_TRP17 *((volatile uint8_t *)(0x42E019C4UL)) +#define bFM_CANFD0_TXBRP_TRP18 *((volatile uint8_t *)(0x42E019C8UL)) +#define bFM4_CANFD0_TXBRP_TRP18 *((volatile uint8_t *)(0x42E019C8UL)) +#define bFM_CANFD0_TXBRP_TRP19 *((volatile uint8_t *)(0x42E019CCUL)) +#define bFM4_CANFD0_TXBRP_TRP19 *((volatile uint8_t *)(0x42E019CCUL)) +#define bFM_CANFD0_TXBRP_TRP20 *((volatile uint8_t *)(0x42E019D0UL)) +#define bFM4_CANFD0_TXBRP_TRP20 *((volatile uint8_t *)(0x42E019D0UL)) +#define bFM_CANFD0_TXBRP_TRP21 *((volatile uint8_t *)(0x42E019D4UL)) +#define bFM4_CANFD0_TXBRP_TRP21 *((volatile uint8_t *)(0x42E019D4UL)) +#define bFM_CANFD0_TXBRP_TRP22 *((volatile uint8_t *)(0x42E019D8UL)) +#define bFM4_CANFD0_TXBRP_TRP22 *((volatile uint8_t *)(0x42E019D8UL)) +#define bFM_CANFD0_TXBRP_TRP23 *((volatile uint8_t *)(0x42E019DCUL)) +#define bFM4_CANFD0_TXBRP_TRP23 *((volatile uint8_t *)(0x42E019DCUL)) +#define bFM_CANFD0_TXBRP_TRP24 *((volatile uint8_t *)(0x42E019E0UL)) +#define bFM4_CANFD0_TXBRP_TRP24 *((volatile uint8_t *)(0x42E019E0UL)) +#define bFM_CANFD0_TXBRP_TRP25 *((volatile uint8_t *)(0x42E019E4UL)) +#define bFM4_CANFD0_TXBRP_TRP25 *((volatile uint8_t *)(0x42E019E4UL)) +#define bFM_CANFD0_TXBRP_TRP26 *((volatile uint8_t *)(0x42E019E8UL)) +#define bFM4_CANFD0_TXBRP_TRP26 *((volatile uint8_t *)(0x42E019E8UL)) +#define bFM_CANFD0_TXBRP_TRP27 *((volatile uint8_t *)(0x42E019ECUL)) +#define bFM4_CANFD0_TXBRP_TRP27 *((volatile uint8_t *)(0x42E019ECUL)) +#define bFM_CANFD0_TXBRP_TRP28 *((volatile uint8_t *)(0x42E019F0UL)) +#define bFM4_CANFD0_TXBRP_TRP28 *((volatile uint8_t *)(0x42E019F0UL)) +#define bFM_CANFD0_TXBRP_TRP29 *((volatile uint8_t *)(0x42E019F4UL)) +#define bFM4_CANFD0_TXBRP_TRP29 *((volatile uint8_t *)(0x42E019F4UL)) +#define bFM_CANFD0_TXBRP_TRP30 *((volatile uint8_t *)(0x42E019F8UL)) +#define bFM4_CANFD0_TXBRP_TRP30 *((volatile uint8_t *)(0x42E019F8UL)) +#define bFM_CANFD0_TXBRP_TRP31 *((volatile uint8_t *)(0x42E019FCUL)) +#define bFM4_CANFD0_TXBRP_TRP31 *((volatile uint8_t *)(0x42E019FCUL)) + +#define bFM_CANFD0_TXBTIE_TIE0 *((volatile uint8_t *)(0x42E01C00UL)) +#define bFM4_CANFD0_TXBTIE_TIE0 *((volatile uint8_t *)(0x42E01C00UL)) +#define bFM_CANFD0_TXBTIE_TIE1 *((volatile uint8_t *)(0x42E01C04UL)) +#define bFM4_CANFD0_TXBTIE_TIE1 *((volatile uint8_t *)(0x42E01C04UL)) +#define bFM_CANFD0_TXBTIE_TIE2 *((volatile uint8_t *)(0x42E01C08UL)) +#define bFM4_CANFD0_TXBTIE_TIE2 *((volatile uint8_t *)(0x42E01C08UL)) +#define bFM_CANFD0_TXBTIE_TIE3 *((volatile uint8_t *)(0x42E01C0CUL)) +#define bFM4_CANFD0_TXBTIE_TIE3 *((volatile uint8_t *)(0x42E01C0CUL)) +#define bFM_CANFD0_TXBTIE_TIE4 *((volatile uint8_t *)(0x42E01C10UL)) +#define bFM4_CANFD0_TXBTIE_TIE4 *((volatile uint8_t *)(0x42E01C10UL)) +#define bFM_CANFD0_TXBTIE_TIE5 *((volatile uint8_t *)(0x42E01C14UL)) +#define bFM4_CANFD0_TXBTIE_TIE5 *((volatile uint8_t *)(0x42E01C14UL)) +#define bFM_CANFD0_TXBTIE_TIE6 *((volatile uint8_t *)(0x42E01C18UL)) +#define bFM4_CANFD0_TXBTIE_TIE6 *((volatile uint8_t *)(0x42E01C18UL)) +#define bFM_CANFD0_TXBTIE_TIE7 *((volatile uint8_t *)(0x42E01C1CUL)) +#define bFM4_CANFD0_TXBTIE_TIE7 *((volatile uint8_t *)(0x42E01C1CUL)) +#define bFM_CANFD0_TXBTIE_TIE8 *((volatile uint8_t *)(0x42E01C20UL)) +#define bFM4_CANFD0_TXBTIE_TIE8 *((volatile uint8_t *)(0x42E01C20UL)) +#define bFM_CANFD0_TXBTIE_TIE9 *((volatile uint8_t *)(0x42E01C24UL)) +#define bFM4_CANFD0_TXBTIE_TIE9 *((volatile uint8_t *)(0x42E01C24UL)) +#define bFM_CANFD0_TXBTIE_TIE10 *((volatile uint8_t *)(0x42E01C28UL)) +#define bFM4_CANFD0_TXBTIE_TIE10 *((volatile uint8_t *)(0x42E01C28UL)) +#define bFM_CANFD0_TXBTIE_TIE11 *((volatile uint8_t *)(0x42E01C2CUL)) +#define bFM4_CANFD0_TXBTIE_TIE11 *((volatile uint8_t *)(0x42E01C2CUL)) +#define bFM_CANFD0_TXBTIE_TIE12 *((volatile uint8_t *)(0x42E01C30UL)) +#define bFM4_CANFD0_TXBTIE_TIE12 *((volatile uint8_t *)(0x42E01C30UL)) +#define bFM_CANFD0_TXBTIE_TIE13 *((volatile uint8_t *)(0x42E01C34UL)) +#define bFM4_CANFD0_TXBTIE_TIE13 *((volatile uint8_t *)(0x42E01C34UL)) +#define bFM_CANFD0_TXBTIE_TIE14 *((volatile uint8_t *)(0x42E01C38UL)) +#define bFM4_CANFD0_TXBTIE_TIE14 *((volatile uint8_t *)(0x42E01C38UL)) +#define bFM_CANFD0_TXBTIE_TIE15 *((volatile uint8_t *)(0x42E01C3CUL)) +#define bFM4_CANFD0_TXBTIE_TIE15 *((volatile uint8_t *)(0x42E01C3CUL)) +#define bFM_CANFD0_TXBTIE_TIE16 *((volatile uint8_t *)(0x42E01C40UL)) +#define bFM4_CANFD0_TXBTIE_TIE16 *((volatile uint8_t *)(0x42E01C40UL)) +#define bFM_CANFD0_TXBTIE_TIE17 *((volatile uint8_t *)(0x42E01C44UL)) +#define bFM4_CANFD0_TXBTIE_TIE17 *((volatile uint8_t *)(0x42E01C44UL)) +#define bFM_CANFD0_TXBTIE_TIE18 *((volatile uint8_t *)(0x42E01C48UL)) +#define bFM4_CANFD0_TXBTIE_TIE18 *((volatile uint8_t *)(0x42E01C48UL)) +#define bFM_CANFD0_TXBTIE_TIE19 *((volatile uint8_t *)(0x42E01C4CUL)) +#define bFM4_CANFD0_TXBTIE_TIE19 *((volatile uint8_t *)(0x42E01C4CUL)) +#define bFM_CANFD0_TXBTIE_TIE20 *((volatile uint8_t *)(0x42E01C50UL)) +#define bFM4_CANFD0_TXBTIE_TIE20 *((volatile uint8_t *)(0x42E01C50UL)) +#define bFM_CANFD0_TXBTIE_TIE21 *((volatile uint8_t *)(0x42E01C54UL)) +#define bFM4_CANFD0_TXBTIE_TIE21 *((volatile uint8_t *)(0x42E01C54UL)) +#define bFM_CANFD0_TXBTIE_TIE22 *((volatile uint8_t *)(0x42E01C58UL)) +#define bFM4_CANFD0_TXBTIE_TIE22 *((volatile uint8_t *)(0x42E01C58UL)) +#define bFM_CANFD0_TXBTIE_TIE23 *((volatile uint8_t *)(0x42E01C5CUL)) +#define bFM4_CANFD0_TXBTIE_TIE23 *((volatile uint8_t *)(0x42E01C5CUL)) +#define bFM_CANFD0_TXBTIE_TIE24 *((volatile uint8_t *)(0x42E01C60UL)) +#define bFM4_CANFD0_TXBTIE_TIE24 *((volatile uint8_t *)(0x42E01C60UL)) +#define bFM_CANFD0_TXBTIE_TIE25 *((volatile uint8_t *)(0x42E01C64UL)) +#define bFM4_CANFD0_TXBTIE_TIE25 *((volatile uint8_t *)(0x42E01C64UL)) +#define bFM_CANFD0_TXBTIE_TIE26 *((volatile uint8_t *)(0x42E01C68UL)) +#define bFM4_CANFD0_TXBTIE_TIE26 *((volatile uint8_t *)(0x42E01C68UL)) +#define bFM_CANFD0_TXBTIE_TIE27 *((volatile uint8_t *)(0x42E01C6CUL)) +#define bFM4_CANFD0_TXBTIE_TIE27 *((volatile uint8_t *)(0x42E01C6CUL)) +#define bFM_CANFD0_TXBTIE_TIE28 *((volatile uint8_t *)(0x42E01C70UL)) +#define bFM4_CANFD0_TXBTIE_TIE28 *((volatile uint8_t *)(0x42E01C70UL)) +#define bFM_CANFD0_TXBTIE_TIE29 *((volatile uint8_t *)(0x42E01C74UL)) +#define bFM4_CANFD0_TXBTIE_TIE29 *((volatile uint8_t *)(0x42E01C74UL)) +#define bFM_CANFD0_TXBTIE_TIE30 *((volatile uint8_t *)(0x42E01C78UL)) +#define bFM4_CANFD0_TXBTIE_TIE30 *((volatile uint8_t *)(0x42E01C78UL)) +#define bFM_CANFD0_TXBTIE_TIE31 *((volatile uint8_t *)(0x42E01C7CUL)) +#define bFM4_CANFD0_TXBTIE_TIE31 *((volatile uint8_t *)(0x42E01C7CUL)) + +#define bFM_CANFD0_TXBTO_TO0 *((volatile uint8_t *)(0x42E01B00UL)) +#define bFM4_CANFD0_TXBTO_TO0 *((volatile uint8_t *)(0x42E01B00UL)) +#define bFM_CANFD0_TXBTO_TO1 *((volatile uint8_t *)(0x42E01B04UL)) +#define bFM4_CANFD0_TXBTO_TO1 *((volatile uint8_t *)(0x42E01B04UL)) +#define bFM_CANFD0_TXBTO_TO2 *((volatile uint8_t *)(0x42E01B08UL)) +#define bFM4_CANFD0_TXBTO_TO2 *((volatile uint8_t *)(0x42E01B08UL)) +#define bFM_CANFD0_TXBTO_TO3 *((volatile uint8_t *)(0x42E01B0CUL)) +#define bFM4_CANFD0_TXBTO_TO3 *((volatile uint8_t *)(0x42E01B0CUL)) +#define bFM_CANFD0_TXBTO_TO4 *((volatile uint8_t *)(0x42E01B10UL)) +#define bFM4_CANFD0_TXBTO_TO4 *((volatile uint8_t *)(0x42E01B10UL)) +#define bFM_CANFD0_TXBTO_TO5 *((volatile uint8_t *)(0x42E01B14UL)) +#define bFM4_CANFD0_TXBTO_TO5 *((volatile uint8_t *)(0x42E01B14UL)) +#define bFM_CANFD0_TXBTO_TO6 *((volatile uint8_t *)(0x42E01B18UL)) +#define bFM4_CANFD0_TXBTO_TO6 *((volatile uint8_t *)(0x42E01B18UL)) +#define bFM_CANFD0_TXBTO_TO7 *((volatile uint8_t *)(0x42E01B1CUL)) +#define bFM4_CANFD0_TXBTO_TO7 *((volatile uint8_t *)(0x42E01B1CUL)) +#define bFM_CANFD0_TXBTO_TO8 *((volatile uint8_t *)(0x42E01B20UL)) +#define bFM4_CANFD0_TXBTO_TO8 *((volatile uint8_t *)(0x42E01B20UL)) +#define bFM_CANFD0_TXBTO_TO9 *((volatile uint8_t *)(0x42E01B24UL)) +#define bFM4_CANFD0_TXBTO_TO9 *((volatile uint8_t *)(0x42E01B24UL)) +#define bFM_CANFD0_TXBTO_TO10 *((volatile uint8_t *)(0x42E01B28UL)) +#define bFM4_CANFD0_TXBTO_TO10 *((volatile uint8_t *)(0x42E01B28UL)) +#define bFM_CANFD0_TXBTO_TO11 *((volatile uint8_t *)(0x42E01B2CUL)) +#define bFM4_CANFD0_TXBTO_TO11 *((volatile uint8_t *)(0x42E01B2CUL)) +#define bFM_CANFD0_TXBTO_TO12 *((volatile uint8_t *)(0x42E01B30UL)) +#define bFM4_CANFD0_TXBTO_TO12 *((volatile uint8_t *)(0x42E01B30UL)) +#define bFM_CANFD0_TXBTO_TO13 *((volatile uint8_t *)(0x42E01B34UL)) +#define bFM4_CANFD0_TXBTO_TO13 *((volatile uint8_t *)(0x42E01B34UL)) +#define bFM_CANFD0_TXBTO_TO14 *((volatile uint8_t *)(0x42E01B38UL)) +#define bFM4_CANFD0_TXBTO_TO14 *((volatile uint8_t *)(0x42E01B38UL)) +#define bFM_CANFD0_TXBTO_TO15 *((volatile uint8_t *)(0x42E01B3CUL)) +#define bFM4_CANFD0_TXBTO_TO15 *((volatile uint8_t *)(0x42E01B3CUL)) +#define bFM_CANFD0_TXBTO_TO16 *((volatile uint8_t *)(0x42E01B40UL)) +#define bFM4_CANFD0_TXBTO_TO16 *((volatile uint8_t *)(0x42E01B40UL)) +#define bFM_CANFD0_TXBTO_TO17 *((volatile uint8_t *)(0x42E01B44UL)) +#define bFM4_CANFD0_TXBTO_TO17 *((volatile uint8_t *)(0x42E01B44UL)) +#define bFM_CANFD0_TXBTO_TO18 *((volatile uint8_t *)(0x42E01B48UL)) +#define bFM4_CANFD0_TXBTO_TO18 *((volatile uint8_t *)(0x42E01B48UL)) +#define bFM_CANFD0_TXBTO_TO19 *((volatile uint8_t *)(0x42E01B4CUL)) +#define bFM4_CANFD0_TXBTO_TO19 *((volatile uint8_t *)(0x42E01B4CUL)) +#define bFM_CANFD0_TXBTO_TO20 *((volatile uint8_t *)(0x42E01B50UL)) +#define bFM4_CANFD0_TXBTO_TO20 *((volatile uint8_t *)(0x42E01B50UL)) +#define bFM_CANFD0_TXBTO_TO21 *((volatile uint8_t *)(0x42E01B54UL)) +#define bFM4_CANFD0_TXBTO_TO21 *((volatile uint8_t *)(0x42E01B54UL)) +#define bFM_CANFD0_TXBTO_TO22 *((volatile uint8_t *)(0x42E01B58UL)) +#define bFM4_CANFD0_TXBTO_TO22 *((volatile uint8_t *)(0x42E01B58UL)) +#define bFM_CANFD0_TXBTO_TO23 *((volatile uint8_t *)(0x42E01B5CUL)) +#define bFM4_CANFD0_TXBTO_TO23 *((volatile uint8_t *)(0x42E01B5CUL)) +#define bFM_CANFD0_TXBTO_TO24 *((volatile uint8_t *)(0x42E01B60UL)) +#define bFM4_CANFD0_TXBTO_TO24 *((volatile uint8_t *)(0x42E01B60UL)) +#define bFM_CANFD0_TXBTO_TO25 *((volatile uint8_t *)(0x42E01B64UL)) +#define bFM4_CANFD0_TXBTO_TO25 *((volatile uint8_t *)(0x42E01B64UL)) +#define bFM_CANFD0_TXBTO_TO26 *((volatile uint8_t *)(0x42E01B68UL)) +#define bFM4_CANFD0_TXBTO_TO26 *((volatile uint8_t *)(0x42E01B68UL)) +#define bFM_CANFD0_TXBTO_TO27 *((volatile uint8_t *)(0x42E01B6CUL)) +#define bFM4_CANFD0_TXBTO_TO27 *((volatile uint8_t *)(0x42E01B6CUL)) +#define bFM_CANFD0_TXBTO_TO28 *((volatile uint8_t *)(0x42E01B70UL)) +#define bFM4_CANFD0_TXBTO_TO28 *((volatile uint8_t *)(0x42E01B70UL)) +#define bFM_CANFD0_TXBTO_TO29 *((volatile uint8_t *)(0x42E01B74UL)) +#define bFM4_CANFD0_TXBTO_TO29 *((volatile uint8_t *)(0x42E01B74UL)) +#define bFM_CANFD0_TXBTO_TO30 *((volatile uint8_t *)(0x42E01B78UL)) +#define bFM4_CANFD0_TXBTO_TO30 *((volatile uint8_t *)(0x42E01B78UL)) +#define bFM_CANFD0_TXBTO_TO31 *((volatile uint8_t *)(0x42E01B7CUL)) +#define bFM4_CANFD0_TXBTO_TO31 *((volatile uint8_t *)(0x42E01B7CUL)) + +#define bFM_CANFD0_TXFQS_TFQF *((volatile uint8_t *)(0x42E018D4UL)) +#define bFM4_CANFD0_TXFQS_TFQF *((volatile uint8_t *)(0x42E018D4UL)) + +#define bFM_CANFD0_TXFS_EFF *((volatile uint8_t *)(0x42E01EE0UL)) +#define bFM4_CANFD0_TXFS_EFF *((volatile uint8_t *)(0x42E01EE0UL)) +#define bFM_CANFD0_TXFS_TEFL *((volatile uint8_t *)(0x42E01EE4UL)) +#define bFM4_CANFD0_TXFS_TEFL *((volatile uint8_t *)(0x42E01EE4UL)) + + +/******************************************************************************* +* CANPRES Registers CANPRES +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* CLK_GATING Registers CLK_GATING +* Bitband Section +*******************************************************************************/ +#define bFM_CLK_GATING_CKEN0_MFSCK0 *((volatile uint8_t *)(0x42782000UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK0 *((volatile uint8_t *)(0x42782000UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK1 *((volatile uint8_t *)(0x42782004UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK1 *((volatile uint8_t *)(0x42782004UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK2 *((volatile uint8_t *)(0x42782008UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK2 *((volatile uint8_t *)(0x42782008UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK3 *((volatile uint8_t *)(0x4278200CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK3 *((volatile uint8_t *)(0x4278200CUL)) +#define bFM_CLK_GATING_CKEN0_MFSCK4 *((volatile uint8_t *)(0x42782010UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK4 *((volatile uint8_t *)(0x42782010UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK5 *((volatile uint8_t *)(0x42782014UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK5 *((volatile uint8_t *)(0x42782014UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK6 *((volatile uint8_t *)(0x42782018UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK6 *((volatile uint8_t *)(0x42782018UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK7 *((volatile uint8_t *)(0x4278201CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK7 *((volatile uint8_t *)(0x4278201CUL)) +#define bFM_CLK_GATING_CKEN0_MFSCK8 *((volatile uint8_t *)(0x42782020UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK8 *((volatile uint8_t *)(0x42782020UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK9 *((volatile uint8_t *)(0x42782024UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK9 *((volatile uint8_t *)(0x42782024UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK10 *((volatile uint8_t *)(0x42782028UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK10 *((volatile uint8_t *)(0x42782028UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK11 *((volatile uint8_t *)(0x4278202CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK11 *((volatile uint8_t *)(0x4278202CUL)) +#define bFM_CLK_GATING_CKEN0_MFSCK12 *((volatile uint8_t *)(0x42782030UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK12 *((volatile uint8_t *)(0x42782030UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK13 *((volatile uint8_t *)(0x42782034UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK13 *((volatile uint8_t *)(0x42782034UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK14 *((volatile uint8_t *)(0x42782038UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK14 *((volatile uint8_t *)(0x42782038UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK15 *((volatile uint8_t *)(0x4278203CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK15 *((volatile uint8_t *)(0x4278203CUL)) +#define bFM_CLK_GATING_CKEN0_ADCCK0 *((volatile uint8_t *)(0x42782040UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK0 *((volatile uint8_t *)(0x42782040UL)) +#define bFM_CLK_GATING_CKEN0_ADCCK1 *((volatile uint8_t *)(0x42782044UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK1 *((volatile uint8_t *)(0x42782044UL)) +#define bFM_CLK_GATING_CKEN0_ADCCK2 *((volatile uint8_t *)(0x42782048UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK2 *((volatile uint8_t *)(0x42782048UL)) +#define bFM_CLK_GATING_CKEN0_ADCCK3 *((volatile uint8_t *)(0x4278204CUL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK3 *((volatile uint8_t *)(0x4278204CUL)) +#define bFM_CLK_GATING_CKEN0_DMACK *((volatile uint8_t *)(0x42782060UL)) +#define bFM4_CLK_GATING_CKEN0_DMACK *((volatile uint8_t *)(0x42782060UL)) +#define bFM_CLK_GATING_CKEN0_EXBCK *((volatile uint8_t *)(0x42782068UL)) +#define bFM4_CLK_GATING_CKEN0_EXBCK *((volatile uint8_t *)(0x42782068UL)) +#define bFM_CLK_GATING_CKEN0_GIOCK *((volatile uint8_t *)(0x42782070UL)) +#define bFM4_CLK_GATING_CKEN0_GIOCK *((volatile uint8_t *)(0x42782070UL)) + +#define bFM_CLK_GATING_CKEN1_BTMCK0 *((volatile uint8_t *)(0x42782200UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK0 *((volatile uint8_t *)(0x42782200UL)) +#define bFM_CLK_GATING_CKEN1_BTMCK1 *((volatile uint8_t *)(0x42782204UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK1 *((volatile uint8_t *)(0x42782204UL)) +#define bFM_CLK_GATING_CKEN1_BTMCK2 *((volatile uint8_t *)(0x42782208UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK2 *((volatile uint8_t *)(0x42782208UL)) +#define bFM_CLK_GATING_CKEN1_BTMCK3 *((volatile uint8_t *)(0x4278220CUL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK3 *((volatile uint8_t *)(0x4278220CUL)) +#define bFM_CLK_GATING_CKEN1_MFTCK0 *((volatile uint8_t *)(0x42782220UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK0 *((volatile uint8_t *)(0x42782220UL)) +#define bFM_CLK_GATING_CKEN1_MFTCK1 *((volatile uint8_t *)(0x42782224UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK1 *((volatile uint8_t *)(0x42782224UL)) +#define bFM_CLK_GATING_CKEN1_MFTCK2 *((volatile uint8_t *)(0x42782228UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK2 *((volatile uint8_t *)(0x42782228UL)) +#define bFM_CLK_GATING_CKEN1_MFTCK3 *((volatile uint8_t *)(0x4278222CUL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK3 *((volatile uint8_t *)(0x4278222CUL)) +#define bFM_CLK_GATING_CKEN1_QDUCK0 *((volatile uint8_t *)(0x42782240UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK0 *((volatile uint8_t *)(0x42782240UL)) +#define bFM_CLK_GATING_CKEN1_QDUCK1 *((volatile uint8_t *)(0x42782244UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK1 *((volatile uint8_t *)(0x42782244UL)) +#define bFM_CLK_GATING_CKEN1_QDUCK2 *((volatile uint8_t *)(0x42782248UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK2 *((volatile uint8_t *)(0x42782248UL)) +#define bFM_CLK_GATING_CKEN1_QDUCK3 *((volatile uint8_t *)(0x4278224CUL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK3 *((volatile uint8_t *)(0x4278224CUL)) + +#define bFM_CLK_GATING_CKEN2_USBCK0 *((volatile uint8_t *)(0x42782400UL)) +#define bFM4_CLK_GATING_CKEN2_USBCK0 *((volatile uint8_t *)(0x42782400UL)) +#define bFM_CLK_GATING_CKEN2_USBCK1 *((volatile uint8_t *)(0x42782404UL)) +#define bFM4_CLK_GATING_CKEN2_USBCK1 *((volatile uint8_t *)(0x42782404UL)) +#define bFM_CLK_GATING_CKEN2_CANCK0 *((volatile uint8_t *)(0x42782410UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK0 *((volatile uint8_t *)(0x42782410UL)) +#define bFM_CLK_GATING_CKEN2_CANCK1 *((volatile uint8_t *)(0x42782414UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK1 *((volatile uint8_t *)(0x42782414UL)) +#define bFM_CLK_GATING_CKEN2_CANCK2 *((volatile uint8_t *)(0x42782418UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK2 *((volatile uint8_t *)(0x42782418UL)) +#define bFM_CLK_GATING_CKEN2_SDCCK *((volatile uint8_t *)(0x42782420UL)) +#define bFM4_CLK_GATING_CKEN2_SDCCK *((volatile uint8_t *)(0x42782420UL)) +#define bFM_CLK_GATING_CKEN2_I2SCK0 *((volatile uint8_t *)(0x42782440UL)) +#define bFM4_CLK_GATING_CKEN2_I2SCK0 *((volatile uint8_t *)(0x42782440UL)) +#define bFM_CLK_GATING_CKEN2_I2SCK1 *((volatile uint8_t *)(0x42782444UL)) +#define bFM4_CLK_GATING_CKEN2_I2SCK1 *((volatile uint8_t *)(0x42782444UL)) +#define bFM_CLK_GATING_CKEN2_PCRCCK *((volatile uint8_t *)(0x42782450UL)) +#define bFM4_CLK_GATING_CKEN2_PCRCCK *((volatile uint8_t *)(0x42782450UL)) +#define bFM_CLK_GATING_CKEN2_CECCK0 *((volatile uint8_t *)(0x42782460UL)) +#define bFM4_CLK_GATING_CKEN2_CECCK0 *((volatile uint8_t *)(0x42782460UL)) +#define bFM_CLK_GATING_CKEN2_CECCK1 *((volatile uint8_t *)(0x42782464UL)) +#define bFM4_CLK_GATING_CKEN2_CECCK1 *((volatile uint8_t *)(0x42782464UL)) +#define bFM_CLK_GATING_CKEN2_HSSPICK *((volatile uint8_t *)(0x42782470UL)) +#define bFM4_CLK_GATING_CKEN2_HSSPICK *((volatile uint8_t *)(0x42782470UL)) + +#define bFM_CLK_GATING_MRST0_MFSRST0 *((volatile uint8_t *)(0x42782080UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST0 *((volatile uint8_t *)(0x42782080UL)) +#define bFM_CLK_GATING_MRST0_MFSRST1 *((volatile uint8_t *)(0x42782084UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST1 *((volatile uint8_t *)(0x42782084UL)) +#define bFM_CLK_GATING_MRST0_MFSRST2 *((volatile uint8_t *)(0x42782088UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST2 *((volatile uint8_t *)(0x42782088UL)) +#define bFM_CLK_GATING_MRST0_MFSRST3 *((volatile uint8_t *)(0x4278208CUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST3 *((volatile uint8_t *)(0x4278208CUL)) +#define bFM_CLK_GATING_MRST0_MFSRST4 *((volatile uint8_t *)(0x42782090UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST4 *((volatile uint8_t *)(0x42782090UL)) +#define bFM_CLK_GATING_MRST0_MFSRST5 *((volatile uint8_t *)(0x42782094UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST5 *((volatile uint8_t *)(0x42782094UL)) +#define bFM_CLK_GATING_MRST0_MFSRST6 *((volatile uint8_t *)(0x42782098UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST6 *((volatile uint8_t *)(0x42782098UL)) +#define bFM_CLK_GATING_MRST0_MFSRST7 *((volatile uint8_t *)(0x4278209CUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST7 *((volatile uint8_t *)(0x4278209CUL)) +#define bFM_CLK_GATING_MRST0_MFSRST8 *((volatile uint8_t *)(0x427820A0UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST8 *((volatile uint8_t *)(0x427820A0UL)) +#define bFM_CLK_GATING_MRST0_MFSRST9 *((volatile uint8_t *)(0x427820A4UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST9 *((volatile uint8_t *)(0x427820A4UL)) +#define bFM_CLK_GATING_MRST0_MFSRST10 *((volatile uint8_t *)(0x427820A8UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST10 *((volatile uint8_t *)(0x427820A8UL)) +#define bFM_CLK_GATING_MRST0_MFSRST11 *((volatile uint8_t *)(0x427820ACUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST11 *((volatile uint8_t *)(0x427820ACUL)) +#define bFM_CLK_GATING_MRST0_MFSRST12 *((volatile uint8_t *)(0x427820B0UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST12 *((volatile uint8_t *)(0x427820B0UL)) +#define bFM_CLK_GATING_MRST0_MFSRST13 *((volatile uint8_t *)(0x427820B4UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST13 *((volatile uint8_t *)(0x427820B4UL)) +#define bFM_CLK_GATING_MRST0_MFSRST14 *((volatile uint8_t *)(0x427820B8UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST14 *((volatile uint8_t *)(0x427820B8UL)) +#define bFM_CLK_GATING_MRST0_MFSRST15 *((volatile uint8_t *)(0x427820BCUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST15 *((volatile uint8_t *)(0x427820BCUL)) +#define bFM_CLK_GATING_MRST0_ADCRST0 *((volatile uint8_t *)(0x427820C0UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST0 *((volatile uint8_t *)(0x427820C0UL)) +#define bFM_CLK_GATING_MRST0_ADCRST1 *((volatile uint8_t *)(0x427820C4UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST1 *((volatile uint8_t *)(0x427820C4UL)) +#define bFM_CLK_GATING_MRST0_ADCRST2 *((volatile uint8_t *)(0x427820C8UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST2 *((volatile uint8_t *)(0x427820C8UL)) +#define bFM_CLK_GATING_MRST0_ADCRST3 *((volatile uint8_t *)(0x427820CCUL)) +#define bFM4_CLK_GATING_MRST0_ADCRST3 *((volatile uint8_t *)(0x427820CCUL)) +#define bFM_CLK_GATING_MRST0_DMARST *((volatile uint8_t *)(0x427820E0UL)) +#define bFM4_CLK_GATING_MRST0_DMARST *((volatile uint8_t *)(0x427820E0UL)) +#define bFM_CLK_GATING_MRST0_EXBRST *((volatile uint8_t *)(0x427820E8UL)) +#define bFM4_CLK_GATING_MRST0_EXBRST *((volatile uint8_t *)(0x427820E8UL)) + +#define bFM_CLK_GATING_MRST1_BTMRST0 *((volatile uint8_t *)(0x42782280UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST0 *((volatile uint8_t *)(0x42782280UL)) +#define bFM_CLK_GATING_MRST1_BTMRST1 *((volatile uint8_t *)(0x42782284UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST1 *((volatile uint8_t *)(0x42782284UL)) +#define bFM_CLK_GATING_MRST1_BTMRST2 *((volatile uint8_t *)(0x42782288UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST2 *((volatile uint8_t *)(0x42782288UL)) +#define bFM_CLK_GATING_MRST1_BTMRST3 *((volatile uint8_t *)(0x4278228CUL)) +#define bFM4_CLK_GATING_MRST1_BTMRST3 *((volatile uint8_t *)(0x4278228CUL)) +#define bFM_CLK_GATING_MRST1_MFTRST0 *((volatile uint8_t *)(0x427822A0UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST0 *((volatile uint8_t *)(0x427822A0UL)) +#define bFM_CLK_GATING_MRST1_MFTRST1 *((volatile uint8_t *)(0x427822A4UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST1 *((volatile uint8_t *)(0x427822A4UL)) +#define bFM_CLK_GATING_MRST1_MFTRST2 *((volatile uint8_t *)(0x427822A8UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST2 *((volatile uint8_t *)(0x427822A8UL)) +#define bFM_CLK_GATING_MRST1_MFTRST3 *((volatile uint8_t *)(0x427822ACUL)) +#define bFM4_CLK_GATING_MRST1_MFTRST3 *((volatile uint8_t *)(0x427822ACUL)) +#define bFM_CLK_GATING_MRST1_QDURST0 *((volatile uint8_t *)(0x427822C0UL)) +#define bFM4_CLK_GATING_MRST1_QDURST0 *((volatile uint8_t *)(0x427822C0UL)) +#define bFM_CLK_GATING_MRST1_QDURST1 *((volatile uint8_t *)(0x427822C4UL)) +#define bFM4_CLK_GATING_MRST1_QDURST1 *((volatile uint8_t *)(0x427822C4UL)) +#define bFM_CLK_GATING_MRST1_QDURST2 *((volatile uint8_t *)(0x427822C8UL)) +#define bFM4_CLK_GATING_MRST1_QDURST2 *((volatile uint8_t *)(0x427822C8UL)) +#define bFM_CLK_GATING_MRST1_QDURST3 *((volatile uint8_t *)(0x427822CCUL)) +#define bFM4_CLK_GATING_MRST1_QDURST3 *((volatile uint8_t *)(0x427822CCUL)) + +#define bFM_CLK_GATING_MRST2_USBRST0 *((volatile uint8_t *)(0x42782480UL)) +#define bFM4_CLK_GATING_MRST2_USBRST0 *((volatile uint8_t *)(0x42782480UL)) +#define bFM_CLK_GATING_MRST2_USBRST1 *((volatile uint8_t *)(0x42782484UL)) +#define bFM4_CLK_GATING_MRST2_USBRST1 *((volatile uint8_t *)(0x42782484UL)) +#define bFM_CLK_GATING_MRST2_CANRST0 *((volatile uint8_t *)(0x42782490UL)) +#define bFM4_CLK_GATING_MRST2_CANRST0 *((volatile uint8_t *)(0x42782490UL)) +#define bFM_CLK_GATING_MRST2_CANRST1 *((volatile uint8_t *)(0x42782494UL)) +#define bFM4_CLK_GATING_MRST2_CANRST1 *((volatile uint8_t *)(0x42782494UL)) +#define bFM_CLK_GATING_MRST2_CANRST2 *((volatile uint8_t *)(0x42782498UL)) +#define bFM4_CLK_GATING_MRST2_CANRST2 *((volatile uint8_t *)(0x42782498UL)) +#define bFM_CLK_GATING_MRST2_SDCRST *((volatile uint8_t *)(0x427824A0UL)) +#define bFM4_CLK_GATING_MRST2_SDCRST *((volatile uint8_t *)(0x427824A0UL)) +#define bFM_CLK_GATING_MRST2_I2SRST0 *((volatile uint8_t *)(0x427824C0UL)) +#define bFM4_CLK_GATING_MRST2_I2SRST0 *((volatile uint8_t *)(0x427824C0UL)) +#define bFM_CLK_GATING_MRST2_I2SRST1 *((volatile uint8_t *)(0x427824C4UL)) +#define bFM4_CLK_GATING_MRST2_I2SRST1 *((volatile uint8_t *)(0x427824C4UL)) +#define bFM_CLK_GATING_MRST2_PCRCRST *((volatile uint8_t *)(0x427824D0UL)) +#define bFM4_CLK_GATING_MRST2_PCRCRST *((volatile uint8_t *)(0x427824D0UL)) +#define bFM_CLK_GATING_MRST2_CECRST0 *((volatile uint8_t *)(0x427824E0UL)) +#define bFM4_CLK_GATING_MRST2_CECRST0 *((volatile uint8_t *)(0x427824E0UL)) +#define bFM_CLK_GATING_MRST2_CECRST1 *((volatile uint8_t *)(0x427824E4UL)) +#define bFM4_CLK_GATING_MRST2_CECRST1 *((volatile uint8_t *)(0x427824E4UL)) +#define bFM_CLK_GATING_MRST2_HSSPIRST *((volatile uint8_t *)(0x427824F0UL)) +#define bFM4_CLK_GATING_MRST2_HSSPIRST *((volatile uint8_t *)(0x427824F0UL)) + + +/******************************************************************************* +* CRC Registers CRC +* Bitband Section +*******************************************************************************/ +#define bFM_CRC_CRCCR_INIT *((volatile uint8_t *)(0x42720000UL)) +#define bFM4_CRC_CRCCR_INIT *((volatile uint8_t *)(0x42720000UL)) +#define bFM_CRC_CRCCR_CRC32 *((volatile uint8_t *)(0x42720004UL)) +#define bFM4_CRC_CRCCR_CRC32 *((volatile uint8_t *)(0x42720004UL)) +#define bFM_CRC_CRCCR_LTLEND *((volatile uint8_t *)(0x42720008UL)) +#define bFM4_CRC_CRCCR_LTLEND *((volatile uint8_t *)(0x42720008UL)) +#define bFM_CRC_CRCCR_LSBFST *((volatile uint8_t *)(0x4272000CUL)) +#define bFM4_CRC_CRCCR_LSBFST *((volatile uint8_t *)(0x4272000CUL)) +#define bFM_CRC_CRCCR_CRCLTE *((volatile uint8_t *)(0x42720010UL)) +#define bFM4_CRC_CRCCR_CRCLTE *((volatile uint8_t *)(0x42720010UL)) +#define bFM_CRC_CRCCR_CRCLSF *((volatile uint8_t *)(0x42720014UL)) +#define bFM4_CRC_CRCCR_CRCLSF *((volatile uint8_t *)(0x42720014UL)) +#define bFM_CRC_CRCCR_FXOR *((volatile uint8_t *)(0x42720018UL)) +#define bFM4_CRC_CRCCR_FXOR *((volatile uint8_t *)(0x42720018UL)) + + +/******************************************************************************* +* CRG Registers CRG +* Bitband Section +*******************************************************************************/ +#define bFM_CRG_APBC1_PSR_APBC1RST *((volatile uint32_t*)(0x42200310UL)) +#define bFM4_CRG_APBC1_PSR_APBC1RST *((volatile uint32_t*)(0x42200310UL)) +#define bFM_CRG_APBC1_PSR_APBC1EN *((volatile uint32_t*)(0x4220031CUL)) +#define bFM4_CRG_APBC1_PSR_APBC1EN *((volatile uint32_t*)(0x4220031CUL)) + +#define bFM_CRG_APBC2_PSR_APBC2RST *((volatile uint32_t*)(0x42200390UL)) +#define bFM4_CRG_APBC2_PSR_APBC2RST *((volatile uint32_t*)(0x42200390UL)) +#define bFM_CRG_APBC2_PSR_APBC2EN *((volatile uint32_t*)(0x4220039CUL)) +#define bFM4_CRG_APBC2_PSR_APBC2EN *((volatile uint32_t*)(0x4220039CUL)) + +#define bFM_CRG_CSV_CTL_MCSVE *((volatile uint32_t*)(0x42200800UL)) +#define bFM4_CRG_CSV_CTL_MCSVE *((volatile uint32_t*)(0x42200800UL)) +#define bFM_CRG_CSV_CTL_SCSVE *((volatile uint32_t*)(0x42200804UL)) +#define bFM4_CRG_CSV_CTL_SCSVE *((volatile uint32_t*)(0x42200804UL)) +#define bFM_CRG_CSV_CTL_FCSDE *((volatile uint32_t*)(0x42200820UL)) +#define bFM4_CRG_CSV_CTL_FCSDE *((volatile uint32_t*)(0x42200820UL)) +#define bFM_CRG_CSV_CTL_FCSRE *((volatile uint32_t*)(0x42200824UL)) +#define bFM4_CRG_CSV_CTL_FCSRE *((volatile uint32_t*)(0x42200824UL)) + +#define bFM_CRG_CSV_STR_MCMF *((volatile uint32_t*)(0x42200880UL)) +#define bFM4_CRG_CSV_STR_MCMF *((volatile uint32_t*)(0x42200880UL)) +#define bFM_CRG_CSV_STR_SCMF *((volatile uint32_t*)(0x42200884UL)) +#define bFM4_CRG_CSV_STR_SCMF *((volatile uint32_t*)(0x42200884UL)) + +#define bFM_CRG_DBWDT_CTL_DPSWBE *((volatile uint32_t*)(0x42200A94UL)) +#define bFM4_CRG_DBWDT_CTL_DPSWBE *((volatile uint32_t*)(0x42200A94UL)) +#define bFM_CRG_DBWDT_CTL_DPHWBE *((volatile uint32_t*)(0x42200A9CUL)) +#define bFM4_CRG_DBWDT_CTL_DPHWBE *((volatile uint32_t*)(0x42200A9CUL)) + +#define bFM_CRG_INT_CLR_MCSC *((volatile uint32_t*)(0x42200D00UL)) +#define bFM4_CRG_INT_CLR_MCSC *((volatile uint32_t*)(0x42200D00UL)) +#define bFM_CRG_INT_CLR_SCSC *((volatile uint32_t*)(0x42200D04UL)) +#define bFM4_CRG_INT_CLR_SCSC *((volatile uint32_t*)(0x42200D04UL)) +#define bFM_CRG_INT_CLR_PCSC *((volatile uint32_t*)(0x42200D08UL)) +#define bFM4_CRG_INT_CLR_PCSC *((volatile uint32_t*)(0x42200D08UL)) +#define bFM_CRG_INT_CLR_FCSC *((volatile uint32_t*)(0x42200D14UL)) +#define bFM4_CRG_INT_CLR_FCSC *((volatile uint32_t*)(0x42200D14UL)) + +#define bFM_CRG_INT_ENR_MCSE *((volatile uint32_t*)(0x42200C00UL)) +#define bFM4_CRG_INT_ENR_MCSE *((volatile uint32_t*)(0x42200C00UL)) +#define bFM_CRG_INT_ENR_SCSE *((volatile uint32_t*)(0x42200C04UL)) +#define bFM4_CRG_INT_ENR_SCSE *((volatile uint32_t*)(0x42200C04UL)) +#define bFM_CRG_INT_ENR_PCSE *((volatile uint32_t*)(0x42200C08UL)) +#define bFM4_CRG_INT_ENR_PCSE *((volatile uint32_t*)(0x42200C08UL)) +#define bFM_CRG_INT_ENR_FCSE *((volatile uint32_t*)(0x42200C14UL)) +#define bFM4_CRG_INT_ENR_FCSE *((volatile uint32_t*)(0x42200C14UL)) + +#define bFM_CRG_INT_STR_MCSI *((volatile uint32_t*)(0x42200C80UL)) +#define bFM4_CRG_INT_STR_MCSI *((volatile uint32_t*)(0x42200C80UL)) +#define bFM_CRG_INT_STR_SCSI *((volatile uint32_t*)(0x42200C84UL)) +#define bFM4_CRG_INT_STR_SCSI *((volatile uint32_t*)(0x42200C84UL)) +#define bFM_CRG_INT_STR_PCSI *((volatile uint32_t*)(0x42200C88UL)) +#define bFM4_CRG_INT_STR_PCSI *((volatile uint32_t*)(0x42200C88UL)) +#define bFM_CRG_INT_STR_FCSI *((volatile uint32_t*)(0x42200C94UL)) +#define bFM4_CRG_INT_STR_FCSI *((volatile uint32_t*)(0x42200C94UL)) + +#define bFM_CRG_PLLCG_CTL_PLLCGEN *((volatile uint32_t*)(0x42200E80UL)) +#define bFM4_CRG_PLLCG_CTL_PLLCGEN *((volatile uint32_t*)(0x42200E80UL)) +#define bFM_CRG_PLLCG_CTL_PLLCGSTR *((volatile uint32_t*)(0x42200E84UL)) +#define bFM4_CRG_PLLCG_CTL_PLLCGSTR *((volatile uint32_t*)(0x42200E84UL)) + +#define bFM_CRG_PSW_TMR_PINC *((volatile uint32_t*)(0x42200690UL)) +#define bFM4_CRG_PSW_TMR_PINC *((volatile uint32_t*)(0x42200690UL)) + +#define bFM_CRG_RST_STR_PONR *((volatile uint32_t*)(0x42200180UL)) +#define bFM4_CRG_RST_STR_PONR *((volatile uint32_t*)(0x42200180UL)) +#define bFM_CRG_RST_STR_INITX *((volatile uint32_t*)(0x42200184UL)) +#define bFM4_CRG_RST_STR_INITX *((volatile uint32_t*)(0x42200184UL)) +#define bFM_CRG_RST_STR_SWDT *((volatile uint32_t*)(0x42200190UL)) +#define bFM4_CRG_RST_STR_SWDT *((volatile uint32_t*)(0x42200190UL)) +#define bFM_CRG_RST_STR_HWDT *((volatile uint32_t*)(0x42200194UL)) +#define bFM4_CRG_RST_STR_HWDT *((volatile uint32_t*)(0x42200194UL)) +#define bFM_CRG_RST_STR_CSVR *((volatile uint32_t*)(0x42200198UL)) +#define bFM4_CRG_RST_STR_CSVR *((volatile uint32_t*)(0x42200198UL)) +#define bFM_CRG_RST_STR_FCSR *((volatile uint32_t*)(0x4220019CUL)) +#define bFM4_CRG_RST_STR_FCSR *((volatile uint32_t*)(0x4220019CUL)) +#define bFM_CRG_RST_STR_SRST *((volatile uint32_t*)(0x422001A0UL)) +#define bFM4_CRG_RST_STR_SRST *((volatile uint32_t*)(0x422001A0UL)) + +#define bFM_CRG_SCM_CTL_MOSCE *((volatile uint32_t*)(0x42200004UL)) +#define bFM4_CRG_SCM_CTL_MOSCE *((volatile uint32_t*)(0x42200004UL)) +#define bFM_CRG_SCM_CTL_SOSCE *((volatile uint32_t*)(0x4220000CUL)) +#define bFM4_CRG_SCM_CTL_SOSCE *((volatile uint32_t*)(0x4220000CUL)) +#define bFM_CRG_SCM_CTL_PLLE *((volatile uint32_t*)(0x42200010UL)) +#define bFM4_CRG_SCM_CTL_PLLE *((volatile uint32_t*)(0x42200010UL)) + +#define bFM_CRG_SCM_STR_MORDY *((volatile uint32_t*)(0x42200084UL)) +#define bFM4_CRG_SCM_STR_MORDY *((volatile uint32_t*)(0x42200084UL)) +#define bFM_CRG_SCM_STR_SORDY *((volatile uint32_t*)(0x4220008CUL)) +#define bFM4_CRG_SCM_STR_SORDY *((volatile uint32_t*)(0x4220008CUL)) +#define bFM_CRG_SCM_STR_PLRDY *((volatile uint32_t*)(0x42200090UL)) +#define bFM4_CRG_SCM_STR_PLRDY *((volatile uint32_t*)(0x42200090UL)) + +#define bFM_CRG_STB_CTL_DSTM *((volatile uint32_t*)(0x42200108UL)) +#define bFM4_CRG_STB_CTL_DSTM *((volatile uint32_t*)(0x42200108UL)) +#define bFM_CRG_STB_CTL_SPL *((volatile uint32_t*)(0x42200110UL)) +#define bFM4_CRG_STB_CTL_SPL *((volatile uint32_t*)(0x42200110UL)) + + +/******************************************************************************* +* CRTRIM Registers CRTRIM +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* DAC Registers DAC0 +* Bitband Section +*******************************************************************************/ +#define bFM_DAC0_DACR_DAE *((volatile uint8_t *)(0x42660000UL)) +#define bFM4_DAC0_DACR_DAE *((volatile uint8_t *)(0x42660000UL)) +#define bFM_DAC0_DACR_DRDY *((volatile uint8_t *)(0x42660004UL)) +#define bFM4_DAC0_DACR_DRDY *((volatile uint8_t *)(0x42660004UL)) +#define bFM_DAC0_DACR_DAC10 *((volatile uint8_t *)(0x42660010UL)) +#define bFM4_DAC0_DACR_DAC10 *((volatile uint8_t *)(0x42660010UL)) +#define bFM_DAC0_DACR_DDAS *((volatile uint8_t *)(0x42660014UL)) +#define bFM4_DAC0_DACR_DDAS *((volatile uint8_t *)(0x42660014UL)) + + +/******************************************************************************* +* DAC Registers DAC1 +* Bitband Section +*******************************************************************************/ +#define bFM_DAC1_DACR_DAE *((volatile uint8_t *)(0x42660100UL)) +#define bFM4_DAC1_DACR_DAE *((volatile uint8_t *)(0x42660100UL)) +#define bFM_DAC1_DACR_DRDY *((volatile uint8_t *)(0x42660104UL)) +#define bFM4_DAC1_DACR_DRDY *((volatile uint8_t *)(0x42660104UL)) +#define bFM_DAC1_DACR_DAC10 *((volatile uint8_t *)(0x42660110UL)) +#define bFM4_DAC1_DACR_DAC10 *((volatile uint8_t *)(0x42660110UL)) +#define bFM_DAC1_DACR_DDAS *((volatile uint8_t *)(0x42660114UL)) +#define bFM4_DAC1_DACR_DDAS *((volatile uint8_t *)(0x42660114UL)) + + +/******************************************************************************* +* DMAC Registers DMAC +* Bitband Section +*******************************************************************************/ +#define bFM_DMAC_DMACA0_ST *((volatile uint8_t *)(0x42C00274UL)) +#define bFM4_DMAC_DMACA0_ST *((volatile uint8_t *)(0x42C00274UL)) +#define bFM_DMAC_DMACA0_PB *((volatile uint8_t *)(0x42C00278UL)) +#define bFM4_DMAC_DMACA0_PB *((volatile uint8_t *)(0x42C00278UL)) +#define bFM_DMAC_DMACA0_EB *((volatile uint8_t *)(0x42C0027CUL)) +#define bFM4_DMAC_DMACA0_EB *((volatile uint8_t *)(0x42C0027CUL)) + +#define bFM_DMAC_DMACA1_ST *((volatile uint8_t *)(0x42C00474UL)) +#define bFM4_DMAC_DMACA1_ST *((volatile uint8_t *)(0x42C00474UL)) +#define bFM_DMAC_DMACA1_PB *((volatile uint8_t *)(0x42C00478UL)) +#define bFM4_DMAC_DMACA1_PB *((volatile uint8_t *)(0x42C00478UL)) +#define bFM_DMAC_DMACA1_EB *((volatile uint8_t *)(0x42C0047CUL)) +#define bFM4_DMAC_DMACA1_EB *((volatile uint8_t *)(0x42C0047CUL)) + +#define bFM_DMAC_DMACA2_ST *((volatile uint8_t *)(0x42C00674UL)) +#define bFM4_DMAC_DMACA2_ST *((volatile uint8_t *)(0x42C00674UL)) +#define bFM_DMAC_DMACA2_PB *((volatile uint8_t *)(0x42C00678UL)) +#define bFM4_DMAC_DMACA2_PB *((volatile uint8_t *)(0x42C00678UL)) +#define bFM_DMAC_DMACA2_EB *((volatile uint8_t *)(0x42C0067CUL)) +#define bFM4_DMAC_DMACA2_EB *((volatile uint8_t *)(0x42C0067CUL)) + +#define bFM_DMAC_DMACA3_ST *((volatile uint8_t *)(0x42C00874UL)) +#define bFM4_DMAC_DMACA3_ST *((volatile uint8_t *)(0x42C00874UL)) +#define bFM_DMAC_DMACA3_PB *((volatile uint8_t *)(0x42C00878UL)) +#define bFM4_DMAC_DMACA3_PB *((volatile uint8_t *)(0x42C00878UL)) +#define bFM_DMAC_DMACA3_EB *((volatile uint8_t *)(0x42C0087CUL)) +#define bFM4_DMAC_DMACA3_EB *((volatile uint8_t *)(0x42C0087CUL)) + +#define bFM_DMAC_DMACA4_ST *((volatile uint8_t *)(0x42C00A74UL)) +#define bFM4_DMAC_DMACA4_ST *((volatile uint8_t *)(0x42C00A74UL)) +#define bFM_DMAC_DMACA4_PB *((volatile uint8_t *)(0x42C00A78UL)) +#define bFM4_DMAC_DMACA4_PB *((volatile uint8_t *)(0x42C00A78UL)) +#define bFM_DMAC_DMACA4_EB *((volatile uint8_t *)(0x42C00A7CUL)) +#define bFM4_DMAC_DMACA4_EB *((volatile uint8_t *)(0x42C00A7CUL)) + +#define bFM_DMAC_DMACA5_ST *((volatile uint8_t *)(0x42C00C74UL)) +#define bFM4_DMAC_DMACA5_ST *((volatile uint8_t *)(0x42C00C74UL)) +#define bFM_DMAC_DMACA5_PB *((volatile uint8_t *)(0x42C00C78UL)) +#define bFM4_DMAC_DMACA5_PB *((volatile uint8_t *)(0x42C00C78UL)) +#define bFM_DMAC_DMACA5_EB *((volatile uint8_t *)(0x42C00C7CUL)) +#define bFM4_DMAC_DMACA5_EB *((volatile uint8_t *)(0x42C00C7CUL)) + +#define bFM_DMAC_DMACA6_ST *((volatile uint8_t *)(0x42C00E74UL)) +#define bFM4_DMAC_DMACA6_ST *((volatile uint8_t *)(0x42C00E74UL)) +#define bFM_DMAC_DMACA6_PB *((volatile uint8_t *)(0x42C00E78UL)) +#define bFM4_DMAC_DMACA6_PB *((volatile uint8_t *)(0x42C00E78UL)) +#define bFM_DMAC_DMACA6_EB *((volatile uint8_t *)(0x42C00E7CUL)) +#define bFM4_DMAC_DMACA6_EB *((volatile uint8_t *)(0x42C00E7CUL)) + +#define bFM_DMAC_DMACA7_ST *((volatile uint8_t *)(0x42C01074UL)) +#define bFM4_DMAC_DMACA7_ST *((volatile uint8_t *)(0x42C01074UL)) +#define bFM_DMAC_DMACA7_PB *((volatile uint8_t *)(0x42C01078UL)) +#define bFM4_DMAC_DMACA7_PB *((volatile uint8_t *)(0x42C01078UL)) +#define bFM_DMAC_DMACA7_EB *((volatile uint8_t *)(0x42C0107CUL)) +#define bFM4_DMAC_DMACA7_EB *((volatile uint8_t *)(0x42C0107CUL)) + +#define bFM_DMAC_DMACB0_EM *((volatile uint8_t *)(0x42C00280UL)) +#define bFM4_DMAC_DMACB0_EM *((volatile uint8_t *)(0x42C00280UL)) +#define bFM_DMAC_DMACB0_CI *((volatile uint8_t *)(0x42C002CCUL)) +#define bFM4_DMAC_DMACB0_CI *((volatile uint8_t *)(0x42C002CCUL)) +#define bFM_DMAC_DMACB0_EI *((volatile uint8_t *)(0x42C002D0UL)) +#define bFM4_DMAC_DMACB0_EI *((volatile uint8_t *)(0x42C002D0UL)) +#define bFM_DMAC_DMACB0_RD *((volatile uint8_t *)(0x42C002D4UL)) +#define bFM4_DMAC_DMACB0_RD *((volatile uint8_t *)(0x42C002D4UL)) +#define bFM_DMAC_DMACB0_RS *((volatile uint8_t *)(0x42C002D8UL)) +#define bFM4_DMAC_DMACB0_RS *((volatile uint8_t *)(0x42C002D8UL)) +#define bFM_DMAC_DMACB0_RC *((volatile uint8_t *)(0x42C002DCUL)) +#define bFM4_DMAC_DMACB0_RC *((volatile uint8_t *)(0x42C002DCUL)) +#define bFM_DMAC_DMACB0_FD *((volatile uint8_t *)(0x42C002E0UL)) +#define bFM4_DMAC_DMACB0_FD *((volatile uint8_t *)(0x42C002E0UL)) +#define bFM_DMAC_DMACB0_FS *((volatile uint8_t *)(0x42C002E4UL)) +#define bFM4_DMAC_DMACB0_FS *((volatile uint8_t *)(0x42C002E4UL)) + +#define bFM_DMAC_DMACB1_EM *((volatile uint8_t *)(0x42C00480UL)) +#define bFM4_DMAC_DMACB1_EM *((volatile uint8_t *)(0x42C00480UL)) +#define bFM_DMAC_DMACB1_CI *((volatile uint8_t *)(0x42C004CCUL)) +#define bFM4_DMAC_DMACB1_CI *((volatile uint8_t *)(0x42C004CCUL)) +#define bFM_DMAC_DMACB1_EI *((volatile uint8_t *)(0x42C004D0UL)) +#define bFM4_DMAC_DMACB1_EI *((volatile uint8_t *)(0x42C004D0UL)) +#define bFM_DMAC_DMACB1_RD *((volatile uint8_t *)(0x42C004D4UL)) +#define bFM4_DMAC_DMACB1_RD *((volatile uint8_t *)(0x42C004D4UL)) +#define bFM_DMAC_DMACB1_RS *((volatile uint8_t *)(0x42C004D8UL)) +#define bFM4_DMAC_DMACB1_RS *((volatile uint8_t *)(0x42C004D8UL)) +#define bFM_DMAC_DMACB1_RC *((volatile uint8_t *)(0x42C004DCUL)) +#define bFM4_DMAC_DMACB1_RC *((volatile uint8_t *)(0x42C004DCUL)) +#define bFM_DMAC_DMACB1_FD *((volatile uint8_t *)(0x42C004E0UL)) +#define bFM4_DMAC_DMACB1_FD *((volatile uint8_t *)(0x42C004E0UL)) +#define bFM_DMAC_DMACB1_FS *((volatile uint8_t *)(0x42C004E4UL)) +#define bFM4_DMAC_DMACB1_FS *((volatile uint8_t *)(0x42C004E4UL)) + +#define bFM_DMAC_DMACB2_EM *((volatile uint8_t *)(0x42C00680UL)) +#define bFM4_DMAC_DMACB2_EM *((volatile uint8_t *)(0x42C00680UL)) +#define bFM_DMAC_DMACB2_CI *((volatile uint8_t *)(0x42C006CCUL)) +#define bFM4_DMAC_DMACB2_CI *((volatile uint8_t *)(0x42C006CCUL)) +#define bFM_DMAC_DMACB2_EI *((volatile uint8_t *)(0x42C006D0UL)) +#define bFM4_DMAC_DMACB2_EI *((volatile uint8_t *)(0x42C006D0UL)) +#define bFM_DMAC_DMACB2_RD *((volatile uint8_t *)(0x42C006D4UL)) +#define bFM4_DMAC_DMACB2_RD *((volatile uint8_t *)(0x42C006D4UL)) +#define bFM_DMAC_DMACB2_RS *((volatile uint8_t *)(0x42C006D8UL)) +#define bFM4_DMAC_DMACB2_RS *((volatile uint8_t *)(0x42C006D8UL)) +#define bFM_DMAC_DMACB2_RC *((volatile uint8_t *)(0x42C006DCUL)) +#define bFM4_DMAC_DMACB2_RC *((volatile uint8_t *)(0x42C006DCUL)) +#define bFM_DMAC_DMACB2_FD *((volatile uint8_t *)(0x42C006E0UL)) +#define bFM4_DMAC_DMACB2_FD *((volatile uint8_t *)(0x42C006E0UL)) +#define bFM_DMAC_DMACB2_FS *((volatile uint8_t *)(0x42C006E4UL)) +#define bFM4_DMAC_DMACB2_FS *((volatile uint8_t *)(0x42C006E4UL)) + +#define bFM_DMAC_DMACB3_EM *((volatile uint8_t *)(0x42C00880UL)) +#define bFM4_DMAC_DMACB3_EM *((volatile uint8_t *)(0x42C00880UL)) +#define bFM_DMAC_DMACB3_CI *((volatile uint8_t *)(0x42C008CCUL)) +#define bFM4_DMAC_DMACB3_CI *((volatile uint8_t *)(0x42C008CCUL)) +#define bFM_DMAC_DMACB3_EI *((volatile uint8_t *)(0x42C008D0UL)) +#define bFM4_DMAC_DMACB3_EI *((volatile uint8_t *)(0x42C008D0UL)) +#define bFM_DMAC_DMACB3_RD *((volatile uint8_t *)(0x42C008D4UL)) +#define bFM4_DMAC_DMACB3_RD *((volatile uint8_t *)(0x42C008D4UL)) +#define bFM_DMAC_DMACB3_RS *((volatile uint8_t *)(0x42C008D8UL)) +#define bFM4_DMAC_DMACB3_RS *((volatile uint8_t *)(0x42C008D8UL)) +#define bFM_DMAC_DMACB3_RC *((volatile uint8_t *)(0x42C008DCUL)) +#define bFM4_DMAC_DMACB3_RC *((volatile uint8_t *)(0x42C008DCUL)) +#define bFM_DMAC_DMACB3_FD *((volatile uint8_t *)(0x42C008E0UL)) +#define bFM4_DMAC_DMACB3_FD *((volatile uint8_t *)(0x42C008E0UL)) +#define bFM_DMAC_DMACB3_FS *((volatile uint8_t *)(0x42C008E4UL)) +#define bFM4_DMAC_DMACB3_FS *((volatile uint8_t *)(0x42C008E4UL)) + +#define bFM_DMAC_DMACB4_EM *((volatile uint8_t *)(0x42C00A80UL)) +#define bFM4_DMAC_DMACB4_EM *((volatile uint8_t *)(0x42C00A80UL)) +#define bFM_DMAC_DMACB4_CI *((volatile uint8_t *)(0x42C00ACCUL)) +#define bFM4_DMAC_DMACB4_CI *((volatile uint8_t *)(0x42C00ACCUL)) +#define bFM_DMAC_DMACB4_EI *((volatile uint8_t *)(0x42C00AD0UL)) +#define bFM4_DMAC_DMACB4_EI *((volatile uint8_t *)(0x42C00AD0UL)) +#define bFM_DMAC_DMACB4_RD *((volatile uint8_t *)(0x42C00AD4UL)) +#define bFM4_DMAC_DMACB4_RD *((volatile uint8_t *)(0x42C00AD4UL)) +#define bFM_DMAC_DMACB4_RS *((volatile uint8_t *)(0x42C00AD8UL)) +#define bFM4_DMAC_DMACB4_RS *((volatile uint8_t *)(0x42C00AD8UL)) +#define bFM_DMAC_DMACB4_RC *((volatile uint8_t *)(0x42C00ADCUL)) +#define bFM4_DMAC_DMACB4_RC *((volatile uint8_t *)(0x42C00ADCUL)) +#define bFM_DMAC_DMACB4_FD *((volatile uint8_t *)(0x42C00AE0UL)) +#define bFM4_DMAC_DMACB4_FD *((volatile uint8_t *)(0x42C00AE0UL)) +#define bFM_DMAC_DMACB4_FS *((volatile uint8_t *)(0x42C00AE4UL)) +#define bFM4_DMAC_DMACB4_FS *((volatile uint8_t *)(0x42C00AE4UL)) + +#define bFM_DMAC_DMACB5_EM *((volatile uint8_t *)(0x42C00C80UL)) +#define bFM4_DMAC_DMACB5_EM *((volatile uint8_t *)(0x42C00C80UL)) +#define bFM_DMAC_DMACB5_CI *((volatile uint8_t *)(0x42C00CCCUL)) +#define bFM4_DMAC_DMACB5_CI *((volatile uint8_t *)(0x42C00CCCUL)) +#define bFM_DMAC_DMACB5_EI *((volatile uint8_t *)(0x42C00CD0UL)) +#define bFM4_DMAC_DMACB5_EI *((volatile uint8_t *)(0x42C00CD0UL)) +#define bFM_DMAC_DMACB5_RD *((volatile uint8_t *)(0x42C00CD4UL)) +#define bFM4_DMAC_DMACB5_RD *((volatile uint8_t *)(0x42C00CD4UL)) +#define bFM_DMAC_DMACB5_RS *((volatile uint8_t *)(0x42C00CD8UL)) +#define bFM4_DMAC_DMACB5_RS *((volatile uint8_t *)(0x42C00CD8UL)) +#define bFM_DMAC_DMACB5_RC *((volatile uint8_t *)(0x42C00CDCUL)) +#define bFM4_DMAC_DMACB5_RC *((volatile uint8_t *)(0x42C00CDCUL)) +#define bFM_DMAC_DMACB5_FD *((volatile uint8_t *)(0x42C00CE0UL)) +#define bFM4_DMAC_DMACB5_FD *((volatile uint8_t *)(0x42C00CE0UL)) +#define bFM_DMAC_DMACB5_FS *((volatile uint8_t *)(0x42C00CE4UL)) +#define bFM4_DMAC_DMACB5_FS *((volatile uint8_t *)(0x42C00CE4UL)) + +#define bFM_DMAC_DMACB6_EM *((volatile uint8_t *)(0x42C00E80UL)) +#define bFM4_DMAC_DMACB6_EM *((volatile uint8_t *)(0x42C00E80UL)) +#define bFM_DMAC_DMACB6_CI *((volatile uint8_t *)(0x42C00ECCUL)) +#define bFM4_DMAC_DMACB6_CI *((volatile uint8_t *)(0x42C00ECCUL)) +#define bFM_DMAC_DMACB6_EI *((volatile uint8_t *)(0x42C00ED0UL)) +#define bFM4_DMAC_DMACB6_EI *((volatile uint8_t *)(0x42C00ED0UL)) +#define bFM_DMAC_DMACB6_RD *((volatile uint8_t *)(0x42C00ED4UL)) +#define bFM4_DMAC_DMACB6_RD *((volatile uint8_t *)(0x42C00ED4UL)) +#define bFM_DMAC_DMACB6_RS *((volatile uint8_t *)(0x42C00ED8UL)) +#define bFM4_DMAC_DMACB6_RS *((volatile uint8_t *)(0x42C00ED8UL)) +#define bFM_DMAC_DMACB6_RC *((volatile uint8_t *)(0x42C00EDCUL)) +#define bFM4_DMAC_DMACB6_RC *((volatile uint8_t *)(0x42C00EDCUL)) +#define bFM_DMAC_DMACB6_FD *((volatile uint8_t *)(0x42C00EE0UL)) +#define bFM4_DMAC_DMACB6_FD *((volatile uint8_t *)(0x42C00EE0UL)) +#define bFM_DMAC_DMACB6_FS *((volatile uint8_t *)(0x42C00EE4UL)) +#define bFM4_DMAC_DMACB6_FS *((volatile uint8_t *)(0x42C00EE4UL)) + +#define bFM_DMAC_DMACB7_EM *((volatile uint8_t *)(0x42C01080UL)) +#define bFM4_DMAC_DMACB7_EM *((volatile uint8_t *)(0x42C01080UL)) +#define bFM_DMAC_DMACB7_CI *((volatile uint8_t *)(0x42C010CCUL)) +#define bFM4_DMAC_DMACB7_CI *((volatile uint8_t *)(0x42C010CCUL)) +#define bFM_DMAC_DMACB7_EI *((volatile uint8_t *)(0x42C010D0UL)) +#define bFM4_DMAC_DMACB7_EI *((volatile uint8_t *)(0x42C010D0UL)) +#define bFM_DMAC_DMACB7_RD *((volatile uint8_t *)(0x42C010D4UL)) +#define bFM4_DMAC_DMACB7_RD *((volatile uint8_t *)(0x42C010D4UL)) +#define bFM_DMAC_DMACB7_RS *((volatile uint8_t *)(0x42C010D8UL)) +#define bFM4_DMAC_DMACB7_RS *((volatile uint8_t *)(0x42C010D8UL)) +#define bFM_DMAC_DMACB7_RC *((volatile uint8_t *)(0x42C010DCUL)) +#define bFM4_DMAC_DMACB7_RC *((volatile uint8_t *)(0x42C010DCUL)) +#define bFM_DMAC_DMACB7_FD *((volatile uint8_t *)(0x42C010E0UL)) +#define bFM4_DMAC_DMACB7_FD *((volatile uint8_t *)(0x42C010E0UL)) +#define bFM_DMAC_DMACB7_FS *((volatile uint8_t *)(0x42C010E4UL)) +#define bFM4_DMAC_DMACB7_FS *((volatile uint8_t *)(0x42C010E4UL)) + +#define bFM_DMAC_DMACR_PR *((volatile uint8_t *)(0x42C00070UL)) +#define bFM4_DMAC_DMACR_PR *((volatile uint8_t *)(0x42C00070UL)) +#define bFM_DMAC_DMACR_DS *((volatile uint8_t *)(0x42C00078UL)) +#define bFM4_DMAC_DMACR_DS *((volatile uint8_t *)(0x42C00078UL)) +#define bFM_DMAC_DMACR_DE *((volatile uint8_t *)(0x42C0007CUL)) +#define bFM4_DMAC_DMACR_DE *((volatile uint8_t *)(0x42C0007CUL)) + + +/******************************************************************************* +* DS Registers DS +* Bitband Section +*******************************************************************************/ +#define bFM_DS_PMD_CTL_RTCE *((volatile uint8_t *)(0x426B0000UL)) +#define bFM4_DS_PMD_CTL_RTCE *((volatile uint8_t *)(0x426B0000UL)) + +#define bFM_DS_RCK_CTL_RTCCKE *((volatile uint8_t *)(0x426A2080UL)) +#define bFM4_DS_RCK_CTL_RTCCKE *((volatile uint8_t *)(0x426A2080UL)) +#define bFM_DS_RCK_CTL_CECCKE *((volatile uint8_t *)(0x426A2084UL)) +#define bFM4_DS_RCK_CTL_CECCKE *((volatile uint8_t *)(0x426A2084UL)) + +#define bFM_DS_WIER_WRTCE *((volatile uint8_t *)(0x426B0180UL)) +#define bFM4_DS_WIER_WRTCE *((volatile uint8_t *)(0x426B0180UL)) +#define bFM_DS_WIER_WLVDE *((volatile uint8_t *)(0x426B0184UL)) +#define bFM4_DS_WIER_WLVDE *((volatile uint8_t *)(0x426B0184UL)) +#define bFM_DS_WIER_WUI1E *((volatile uint8_t *)(0x426B018CUL)) +#define bFM4_DS_WIER_WUI1E *((volatile uint8_t *)(0x426B018CUL)) +#define bFM_DS_WIER_WUI2E *((volatile uint8_t *)(0x426B0190UL)) +#define bFM4_DS_WIER_WUI2E *((volatile uint8_t *)(0x426B0190UL)) +#define bFM_DS_WIER_WUI3E *((volatile uint8_t *)(0x426B0194UL)) +#define bFM4_DS_WIER_WUI3E *((volatile uint8_t *)(0x426B0194UL)) +#define bFM_DS_WIER_WUI4E *((volatile uint8_t *)(0x426B0198UL)) +#define bFM4_DS_WIER_WUI4E *((volatile uint8_t *)(0x426B0198UL)) +#define bFM_DS_WIER_WUI5E *((volatile uint8_t *)(0x426B019CUL)) +#define bFM4_DS_WIER_WUI5E *((volatile uint8_t *)(0x426B019CUL)) + +#define bFM_DS_WIFSR_WRTCI *((volatile uint8_t *)(0x426B0100UL)) +#define bFM4_DS_WIFSR_WRTCI *((volatile uint8_t *)(0x426B0100UL)) +#define bFM_DS_WIFSR_WLVDI *((volatile uint8_t *)(0x426B0104UL)) +#define bFM4_DS_WIFSR_WLVDI *((volatile uint8_t *)(0x426B0104UL)) +#define bFM_DS_WIFSR_WUI0 *((volatile uint8_t *)(0x426B0108UL)) +#define bFM4_DS_WIFSR_WUI0 *((volatile uint8_t *)(0x426B0108UL)) +#define bFM_DS_WIFSR_WUI1 *((volatile uint8_t *)(0x426B010CUL)) +#define bFM4_DS_WIFSR_WUI1 *((volatile uint8_t *)(0x426B010CUL)) +#define bFM_DS_WIFSR_WUI2 *((volatile uint8_t *)(0x426B0110UL)) +#define bFM4_DS_WIFSR_WUI2 *((volatile uint8_t *)(0x426B0110UL)) +#define bFM_DS_WIFSR_WUI3 *((volatile uint8_t *)(0x426B0114UL)) +#define bFM4_DS_WIFSR_WUI3 *((volatile uint8_t *)(0x426B0114UL)) +#define bFM_DS_WIFSR_WUI4 *((volatile uint8_t *)(0x426B0118UL)) +#define bFM4_DS_WIFSR_WUI4 *((volatile uint8_t *)(0x426B0118UL)) +#define bFM_DS_WIFSR_WUI5 *((volatile uint8_t *)(0x426B011CUL)) +#define bFM4_DS_WIFSR_WUI5 *((volatile uint8_t *)(0x426B011CUL)) + +#define bFM_DS_WILVR_WUI1LV *((volatile uint8_t *)(0x426B0200UL)) +#define bFM4_DS_WILVR_WUI1LV *((volatile uint8_t *)(0x426B0200UL)) +#define bFM_DS_WILVR_WUI2LV *((volatile uint8_t *)(0x426B0204UL)) +#define bFM4_DS_WILVR_WUI2LV *((volatile uint8_t *)(0x426B0204UL)) +#define bFM_DS_WILVR_WUI3LV *((volatile uint8_t *)(0x426B0208UL)) +#define bFM4_DS_WILVR_WUI3LV *((volatile uint8_t *)(0x426B0208UL)) +#define bFM_DS_WILVR_WUI4LV *((volatile uint8_t *)(0x426B020CUL)) +#define bFM4_DS_WILVR_WUI4LV *((volatile uint8_t *)(0x426B020CUL)) +#define bFM_DS_WILVR_WUI5LV *((volatile uint8_t *)(0x426B0210UL)) +#define bFM4_DS_WILVR_WUI5LV *((volatile uint8_t *)(0x426B0210UL)) + +#define bFM_DS_WRFSR_WINITX *((volatile uint8_t *)(0x426B0080UL)) +#define bFM4_DS_WRFSR_WINITX *((volatile uint8_t *)(0x426B0080UL)) +#define bFM_DS_WRFSR_WLVDH *((volatile uint8_t *)(0x426B0084UL)) +#define bFM4_DS_WRFSR_WLVDH *((volatile uint8_t *)(0x426B0084UL)) + + +/******************************************************************************* +* DSTC Registers DSTC +* Bitband Section +*******************************************************************************/ +#define bFM_DSTC_CFG_SWINTE *((volatile uint8_t *)(0x42C20120UL)) +#define bFM4_DSTC_CFG_SWINTE *((volatile uint8_t *)(0x42C20120UL)) +#define bFM_DSTC_CFG_ERINTE *((volatile uint8_t *)(0x42C20124UL)) +#define bFM4_DSTC_CFG_ERINTE *((volatile uint8_t *)(0x42C20124UL)) +#define bFM_DSTC_CFG_RBDIS *((volatile uint8_t *)(0x42C20128UL)) +#define bFM4_DSTC_CFG_RBDIS *((volatile uint8_t *)(0x42C20128UL)) +#define bFM_DSTC_CFG_ESTE *((volatile uint8_t *)(0x42C2012CUL)) +#define bFM4_DSTC_CFG_ESTE *((volatile uint8_t *)(0x42C2012CUL)) + +#define bFM_DSTC_MONERS_DER *((volatile uint8_t *)(0x42C2018CUL)) +#define bFM4_DSTC_MONERS_DER *((volatile uint8_t *)(0x42C2018CUL)) +#define bFM_DSTC_MONERS_ESTOP *((volatile uint8_t *)(0x42C20190UL)) +#define bFM4_DSTC_MONERS_ESTOP *((volatile uint8_t *)(0x42C20190UL)) +#define bFM_DSTC_MONERS_EHS *((volatile uint8_t *)(0x42C20198UL)) +#define bFM4_DSTC_MONERS_EHS *((volatile uint8_t *)(0x42C20198UL)) + +#define bFM_DSTC_SWTR_SWREQ *((volatile uint16_t*)(0x42C20178UL)) +#define bFM4_DSTC_SWTR_SWREQ *((volatile uint16_t*)(0x42C20178UL)) +#define bFM_DSTC_SWTR_SWST *((volatile uint16_t*)(0x42C2017CUL)) +#define bFM4_DSTC_SWTR_SWST *((volatile uint16_t*)(0x42C2017CUL)) + + +/******************************************************************************* +* DT Registers DT +* Bitband Section +*******************************************************************************/ +#define bFM_DT_TIMER1CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0100UL)) +#define bFM4_DT_TIMER1CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0100UL)) +#define bFM_DT_TIMER1CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0104UL)) +#define bFM4_DT_TIMER1CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0104UL)) +#define bFM_DT_TIMER1CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0114UL)) +#define bFM4_DT_TIMER1CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0114UL)) +#define bFM_DT_TIMER1CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0118UL)) +#define bFM4_DT_TIMER1CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0118UL)) +#define bFM_DT_TIMER1CONTROL_TIMEREN *((volatile uint32_t*)(0x422A011CUL)) +#define bFM4_DT_TIMER1CONTROL_TIMEREN *((volatile uint32_t*)(0x422A011CUL)) + +#define bFM_DT_TIMER1MIS_TIMER1MIS *((volatile uint32_t*)(0x422A0280UL)) +#define bFM4_DT_TIMER1MIS_TIMER1MIS *((volatile uint32_t*)(0x422A0280UL)) + +#define bFM_DT_TIMER1RIS_TIMER1RIS *((volatile uint32_t*)(0x422A0200UL)) +#define bFM4_DT_TIMER1RIS_TIMER1RIS *((volatile uint32_t*)(0x422A0200UL)) + +#define bFM_DT_TIMER2CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0500UL)) +#define bFM4_DT_TIMER2CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0500UL)) +#define bFM_DT_TIMER2CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0504UL)) +#define bFM4_DT_TIMER2CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0504UL)) +#define bFM_DT_TIMER2CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0514UL)) +#define bFM4_DT_TIMER2CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0514UL)) +#define bFM_DT_TIMER2CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0518UL)) +#define bFM4_DT_TIMER2CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0518UL)) +#define bFM_DT_TIMER2CONTROL_TIMEREN *((volatile uint32_t*)(0x422A051CUL)) +#define bFM4_DT_TIMER2CONTROL_TIMEREN *((volatile uint32_t*)(0x422A051CUL)) + +#define bFM_DT_TIMER2MIS_TIMER2MIS *((volatile uint32_t*)(0x422A0680UL)) +#define bFM4_DT_TIMER2MIS_TIMER2MIS *((volatile uint32_t*)(0x422A0680UL)) + +#define bFM_DT_TIMER2RIS_TIMER2RIS *((volatile uint32_t*)(0x422A0600UL)) +#define bFM4_DT_TIMER2RIS_TIMER2RIS *((volatile uint32_t*)(0x422A0600UL)) + + +/******************************************************************************* +* DUALFLASH_IF Registers DUALFLASH_IF +* Bitband Section +*******************************************************************************/ +#define bFM_DUALFLASH_IF_DFSTR_DFRDY *((volatile uint8_t *)(0x42008100UL)) +#define bFM4_DUALFLASH_IF_DFSTR_DFRDY *((volatile uint8_t *)(0x42008100UL)) +#define bFM_DUALFLASH_IF_DFSTR_DFHNG *((volatile uint8_t *)(0x42008104UL)) +#define bFM4_DUALFLASH_IF_DFSTR_DFHNG *((volatile uint8_t *)(0x42008104UL)) +#define bFM_DUALFLASH_IF_DFSTR_DFERR *((volatile uint8_t *)(0x42008108UL)) +#define bFM4_DUALFLASH_IF_DFSTR_DFERR *((volatile uint8_t *)(0x42008108UL)) + + +/******************************************************************************* +* ECC_CAPTURE Registers ECC_CAPTURE +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* EXTI Registers EXTI +* Bitband Section +*******************************************************************************/ +#define bFM_EXTI_EICL_ECL0 *((volatile uint8_t *)(0x42600100UL)) +#define bFM4_EXTI_EICL_ECL0 *((volatile uint8_t *)(0x42600100UL)) +#define bFM_EXTI_EICL_ECL1 *((volatile uint8_t *)(0x42600104UL)) +#define bFM4_EXTI_EICL_ECL1 *((volatile uint8_t *)(0x42600104UL)) +#define bFM_EXTI_EICL_ECL2 *((volatile uint8_t *)(0x42600108UL)) +#define bFM4_EXTI_EICL_ECL2 *((volatile uint8_t *)(0x42600108UL)) +#define bFM_EXTI_EICL_ECL3 *((volatile uint8_t *)(0x4260010CUL)) +#define bFM4_EXTI_EICL_ECL3 *((volatile uint8_t *)(0x4260010CUL)) +#define bFM_EXTI_EICL_ECL4 *((volatile uint8_t *)(0x42600110UL)) +#define bFM4_EXTI_EICL_ECL4 *((volatile uint8_t *)(0x42600110UL)) +#define bFM_EXTI_EICL_ECL5 *((volatile uint8_t *)(0x42600114UL)) +#define bFM4_EXTI_EICL_ECL5 *((volatile uint8_t *)(0x42600114UL)) +#define bFM_EXTI_EICL_ECL6 *((volatile uint8_t *)(0x42600118UL)) +#define bFM4_EXTI_EICL_ECL6 *((volatile uint8_t *)(0x42600118UL)) +#define bFM_EXTI_EICL_ECL7 *((volatile uint8_t *)(0x4260011CUL)) +#define bFM4_EXTI_EICL_ECL7 *((volatile uint8_t *)(0x4260011CUL)) +#define bFM_EXTI_EICL_ECL8 *((volatile uint8_t *)(0x42600120UL)) +#define bFM4_EXTI_EICL_ECL8 *((volatile uint8_t *)(0x42600120UL)) +#define bFM_EXTI_EICL_ECL9 *((volatile uint8_t *)(0x42600124UL)) +#define bFM4_EXTI_EICL_ECL9 *((volatile uint8_t *)(0x42600124UL)) +#define bFM_EXTI_EICL_ECL10 *((volatile uint8_t *)(0x42600128UL)) +#define bFM4_EXTI_EICL_ECL10 *((volatile uint8_t *)(0x42600128UL)) +#define bFM_EXTI_EICL_ECL11 *((volatile uint8_t *)(0x4260012CUL)) +#define bFM4_EXTI_EICL_ECL11 *((volatile uint8_t *)(0x4260012CUL)) +#define bFM_EXTI_EICL_ECL12 *((volatile uint8_t *)(0x42600130UL)) +#define bFM4_EXTI_EICL_ECL12 *((volatile uint8_t *)(0x42600130UL)) +#define bFM_EXTI_EICL_ECL13 *((volatile uint8_t *)(0x42600134UL)) +#define bFM4_EXTI_EICL_ECL13 *((volatile uint8_t *)(0x42600134UL)) +#define bFM_EXTI_EICL_ECL14 *((volatile uint8_t *)(0x42600138UL)) +#define bFM4_EXTI_EICL_ECL14 *((volatile uint8_t *)(0x42600138UL)) +#define bFM_EXTI_EICL_ECL15 *((volatile uint8_t *)(0x4260013CUL)) +#define bFM4_EXTI_EICL_ECL15 *((volatile uint8_t *)(0x4260013CUL)) +#define bFM_EXTI_EICL_ECL16 *((volatile uint8_t *)(0x42600140UL)) +#define bFM4_EXTI_EICL_ECL16 *((volatile uint8_t *)(0x42600140UL)) +#define bFM_EXTI_EICL_ECL17 *((volatile uint8_t *)(0x42600144UL)) +#define bFM4_EXTI_EICL_ECL17 *((volatile uint8_t *)(0x42600144UL)) +#define bFM_EXTI_EICL_ECL18 *((volatile uint8_t *)(0x42600148UL)) +#define bFM4_EXTI_EICL_ECL18 *((volatile uint8_t *)(0x42600148UL)) +#define bFM_EXTI_EICL_ECL19 *((volatile uint8_t *)(0x4260014CUL)) +#define bFM4_EXTI_EICL_ECL19 *((volatile uint8_t *)(0x4260014CUL)) +#define bFM_EXTI_EICL_ECL20 *((volatile uint8_t *)(0x42600150UL)) +#define bFM4_EXTI_EICL_ECL20 *((volatile uint8_t *)(0x42600150UL)) +#define bFM_EXTI_EICL_ECL21 *((volatile uint8_t *)(0x42600154UL)) +#define bFM4_EXTI_EICL_ECL21 *((volatile uint8_t *)(0x42600154UL)) +#define bFM_EXTI_EICL_ECL22 *((volatile uint8_t *)(0x42600158UL)) +#define bFM4_EXTI_EICL_ECL22 *((volatile uint8_t *)(0x42600158UL)) +#define bFM_EXTI_EICL_ECL23 *((volatile uint8_t *)(0x4260015CUL)) +#define bFM4_EXTI_EICL_ECL23 *((volatile uint8_t *)(0x4260015CUL)) +#define bFM_EXTI_EICL_ECL24 *((volatile uint8_t *)(0x42600160UL)) +#define bFM4_EXTI_EICL_ECL24 *((volatile uint8_t *)(0x42600160UL)) +#define bFM_EXTI_EICL_ECL25 *((volatile uint8_t *)(0x42600164UL)) +#define bFM4_EXTI_EICL_ECL25 *((volatile uint8_t *)(0x42600164UL)) +#define bFM_EXTI_EICL_ECL26 *((volatile uint8_t *)(0x42600168UL)) +#define bFM4_EXTI_EICL_ECL26 *((volatile uint8_t *)(0x42600168UL)) +#define bFM_EXTI_EICL_ECL27 *((volatile uint8_t *)(0x4260016CUL)) +#define bFM4_EXTI_EICL_ECL27 *((volatile uint8_t *)(0x4260016CUL)) +#define bFM_EXTI_EICL_ECL28 *((volatile uint8_t *)(0x42600170UL)) +#define bFM4_EXTI_EICL_ECL28 *((volatile uint8_t *)(0x42600170UL)) +#define bFM_EXTI_EICL_ECL29 *((volatile uint8_t *)(0x42600174UL)) +#define bFM4_EXTI_EICL_ECL29 *((volatile uint8_t *)(0x42600174UL)) +#define bFM_EXTI_EICL_ECL30 *((volatile uint8_t *)(0x42600178UL)) +#define bFM4_EXTI_EICL_ECL30 *((volatile uint8_t *)(0x42600178UL)) +#define bFM_EXTI_EICL_ECL31 *((volatile uint8_t *)(0x4260017CUL)) +#define bFM4_EXTI_EICL_ECL31 *((volatile uint8_t *)(0x4260017CUL)) + +#define bFM_EXTI_EIRR_ER0 *((volatile uint8_t *)(0x42600080UL)) +#define bFM4_EXTI_EIRR_ER0 *((volatile uint8_t *)(0x42600080UL)) +#define bFM_EXTI_EIRR_ER1 *((volatile uint8_t *)(0x42600084UL)) +#define bFM4_EXTI_EIRR_ER1 *((volatile uint8_t *)(0x42600084UL)) +#define bFM_EXTI_EIRR_ER2 *((volatile uint8_t *)(0x42600088UL)) +#define bFM4_EXTI_EIRR_ER2 *((volatile uint8_t *)(0x42600088UL)) +#define bFM_EXTI_EIRR_ER3 *((volatile uint8_t *)(0x4260008CUL)) +#define bFM4_EXTI_EIRR_ER3 *((volatile uint8_t *)(0x4260008CUL)) +#define bFM_EXTI_EIRR_ER4 *((volatile uint8_t *)(0x42600090UL)) +#define bFM4_EXTI_EIRR_ER4 *((volatile uint8_t *)(0x42600090UL)) +#define bFM_EXTI_EIRR_ER5 *((volatile uint8_t *)(0x42600094UL)) +#define bFM4_EXTI_EIRR_ER5 *((volatile uint8_t *)(0x42600094UL)) +#define bFM_EXTI_EIRR_ER6 *((volatile uint8_t *)(0x42600098UL)) +#define bFM4_EXTI_EIRR_ER6 *((volatile uint8_t *)(0x42600098UL)) +#define bFM_EXTI_EIRR_ER7 *((volatile uint8_t *)(0x4260009CUL)) +#define bFM4_EXTI_EIRR_ER7 *((volatile uint8_t *)(0x4260009CUL)) +#define bFM_EXTI_EIRR_ER8 *((volatile uint8_t *)(0x426000A0UL)) +#define bFM4_EXTI_EIRR_ER8 *((volatile uint8_t *)(0x426000A0UL)) +#define bFM_EXTI_EIRR_ER9 *((volatile uint8_t *)(0x426000A4UL)) +#define bFM4_EXTI_EIRR_ER9 *((volatile uint8_t *)(0x426000A4UL)) +#define bFM_EXTI_EIRR_ER10 *((volatile uint8_t *)(0x426000A8UL)) +#define bFM4_EXTI_EIRR_ER10 *((volatile uint8_t *)(0x426000A8UL)) +#define bFM_EXTI_EIRR_ER11 *((volatile uint8_t *)(0x426000ACUL)) +#define bFM4_EXTI_EIRR_ER11 *((volatile uint8_t *)(0x426000ACUL)) +#define bFM_EXTI_EIRR_ER12 *((volatile uint8_t *)(0x426000B0UL)) +#define bFM4_EXTI_EIRR_ER12 *((volatile uint8_t *)(0x426000B0UL)) +#define bFM_EXTI_EIRR_ER13 *((volatile uint8_t *)(0x426000B4UL)) +#define bFM4_EXTI_EIRR_ER13 *((volatile uint8_t *)(0x426000B4UL)) +#define bFM_EXTI_EIRR_ER14 *((volatile uint8_t *)(0x426000B8UL)) +#define bFM4_EXTI_EIRR_ER14 *((volatile uint8_t *)(0x426000B8UL)) +#define bFM_EXTI_EIRR_ER15 *((volatile uint8_t *)(0x426000BCUL)) +#define bFM4_EXTI_EIRR_ER15 *((volatile uint8_t *)(0x426000BCUL)) +#define bFM_EXTI_EIRR_ER16 *((volatile uint8_t *)(0x426000C0UL)) +#define bFM4_EXTI_EIRR_ER16 *((volatile uint8_t *)(0x426000C0UL)) +#define bFM_EXTI_EIRR_ER17 *((volatile uint8_t *)(0x426000C4UL)) +#define bFM4_EXTI_EIRR_ER17 *((volatile uint8_t *)(0x426000C4UL)) +#define bFM_EXTI_EIRR_ER18 *((volatile uint8_t *)(0x426000C8UL)) +#define bFM4_EXTI_EIRR_ER18 *((volatile uint8_t *)(0x426000C8UL)) +#define bFM_EXTI_EIRR_ER19 *((volatile uint8_t *)(0x426000CCUL)) +#define bFM4_EXTI_EIRR_ER19 *((volatile uint8_t *)(0x426000CCUL)) +#define bFM_EXTI_EIRR_ER20 *((volatile uint8_t *)(0x426000D0UL)) +#define bFM4_EXTI_EIRR_ER20 *((volatile uint8_t *)(0x426000D0UL)) +#define bFM_EXTI_EIRR_ER21 *((volatile uint8_t *)(0x426000D4UL)) +#define bFM4_EXTI_EIRR_ER21 *((volatile uint8_t *)(0x426000D4UL)) +#define bFM_EXTI_EIRR_ER22 *((volatile uint8_t *)(0x426000D8UL)) +#define bFM4_EXTI_EIRR_ER22 *((volatile uint8_t *)(0x426000D8UL)) +#define bFM_EXTI_EIRR_ER23 *((volatile uint8_t *)(0x426000DCUL)) +#define bFM4_EXTI_EIRR_ER23 *((volatile uint8_t *)(0x426000DCUL)) +#define bFM_EXTI_EIRR_ER24 *((volatile uint8_t *)(0x426000E0UL)) +#define bFM4_EXTI_EIRR_ER24 *((volatile uint8_t *)(0x426000E0UL)) +#define bFM_EXTI_EIRR_ER25 *((volatile uint8_t *)(0x426000E4UL)) +#define bFM4_EXTI_EIRR_ER25 *((volatile uint8_t *)(0x426000E4UL)) +#define bFM_EXTI_EIRR_ER26 *((volatile uint8_t *)(0x426000E8UL)) +#define bFM4_EXTI_EIRR_ER26 *((volatile uint8_t *)(0x426000E8UL)) +#define bFM_EXTI_EIRR_ER27 *((volatile uint8_t *)(0x426000ECUL)) +#define bFM4_EXTI_EIRR_ER27 *((volatile uint8_t *)(0x426000ECUL)) +#define bFM_EXTI_EIRR_ER28 *((volatile uint8_t *)(0x426000F0UL)) +#define bFM4_EXTI_EIRR_ER28 *((volatile uint8_t *)(0x426000F0UL)) +#define bFM_EXTI_EIRR_ER29 *((volatile uint8_t *)(0x426000F4UL)) +#define bFM4_EXTI_EIRR_ER29 *((volatile uint8_t *)(0x426000F4UL)) +#define bFM_EXTI_EIRR_ER30 *((volatile uint8_t *)(0x426000F8UL)) +#define bFM4_EXTI_EIRR_ER30 *((volatile uint8_t *)(0x426000F8UL)) +#define bFM_EXTI_EIRR_ER31 *((volatile uint8_t *)(0x426000FCUL)) +#define bFM4_EXTI_EIRR_ER31 *((volatile uint8_t *)(0x426000FCUL)) + +#define bFM_EXTI_ELVR_LA0 *((volatile uint8_t *)(0x42600180UL)) +#define bFM4_EXTI_ELVR_LA0 *((volatile uint8_t *)(0x42600180UL)) +#define bFM_EXTI_ELVR_LB0 *((volatile uint8_t *)(0x42600184UL)) +#define bFM4_EXTI_ELVR_LB0 *((volatile uint8_t *)(0x42600184UL)) +#define bFM_EXTI_ELVR_LA1 *((volatile uint8_t *)(0x42600188UL)) +#define bFM4_EXTI_ELVR_LA1 *((volatile uint8_t *)(0x42600188UL)) +#define bFM_EXTI_ELVR_LB1 *((volatile uint8_t *)(0x4260018CUL)) +#define bFM4_EXTI_ELVR_LB1 *((volatile uint8_t *)(0x4260018CUL)) +#define bFM_EXTI_ELVR_LA2 *((volatile uint8_t *)(0x42600190UL)) +#define bFM4_EXTI_ELVR_LA2 *((volatile uint8_t *)(0x42600190UL)) +#define bFM_EXTI_ELVR_LB2 *((volatile uint8_t *)(0x42600194UL)) +#define bFM4_EXTI_ELVR_LB2 *((volatile uint8_t *)(0x42600194UL)) +#define bFM_EXTI_ELVR_LA3 *((volatile uint8_t *)(0x42600198UL)) +#define bFM4_EXTI_ELVR_LA3 *((volatile uint8_t *)(0x42600198UL)) +#define bFM_EXTI_ELVR_LB3 *((volatile uint8_t *)(0x4260019CUL)) +#define bFM4_EXTI_ELVR_LB3 *((volatile uint8_t *)(0x4260019CUL)) +#define bFM_EXTI_ELVR_LA4 *((volatile uint8_t *)(0x426001A0UL)) +#define bFM4_EXTI_ELVR_LA4 *((volatile uint8_t *)(0x426001A0UL)) +#define bFM_EXTI_ELVR_LB4 *((volatile uint8_t *)(0x426001A4UL)) +#define bFM4_EXTI_ELVR_LB4 *((volatile uint8_t *)(0x426001A4UL)) +#define bFM_EXTI_ELVR_LA5 *((volatile uint8_t *)(0x426001A8UL)) +#define bFM4_EXTI_ELVR_LA5 *((volatile uint8_t *)(0x426001A8UL)) +#define bFM_EXTI_ELVR_LB5 *((volatile uint8_t *)(0x426001ACUL)) +#define bFM4_EXTI_ELVR_LB5 *((volatile uint8_t *)(0x426001ACUL)) +#define bFM_EXTI_ELVR_LA6 *((volatile uint8_t *)(0x426001B0UL)) +#define bFM4_EXTI_ELVR_LA6 *((volatile uint8_t *)(0x426001B0UL)) +#define bFM_EXTI_ELVR_LB6 *((volatile uint8_t *)(0x426001B4UL)) +#define bFM4_EXTI_ELVR_LB6 *((volatile uint8_t *)(0x426001B4UL)) +#define bFM_EXTI_ELVR_LA7 *((volatile uint8_t *)(0x426001B8UL)) +#define bFM4_EXTI_ELVR_LA7 *((volatile uint8_t *)(0x426001B8UL)) +#define bFM_EXTI_ELVR_LB7 *((volatile uint8_t *)(0x426001BCUL)) +#define bFM4_EXTI_ELVR_LB7 *((volatile uint8_t *)(0x426001BCUL)) +#define bFM_EXTI_ELVR_LA8 *((volatile uint8_t *)(0x426001C0UL)) +#define bFM4_EXTI_ELVR_LA8 *((volatile uint8_t *)(0x426001C0UL)) +#define bFM_EXTI_ELVR_LB8 *((volatile uint8_t *)(0x426001C4UL)) +#define bFM4_EXTI_ELVR_LB8 *((volatile uint8_t *)(0x426001C4UL)) +#define bFM_EXTI_ELVR_LA9 *((volatile uint8_t *)(0x426001C8UL)) +#define bFM4_EXTI_ELVR_LA9 *((volatile uint8_t *)(0x426001C8UL)) +#define bFM_EXTI_ELVR_LB9 *((volatile uint8_t *)(0x426001CCUL)) +#define bFM4_EXTI_ELVR_LB9 *((volatile uint8_t *)(0x426001CCUL)) +#define bFM_EXTI_ELVR_LA10 *((volatile uint8_t *)(0x426001D0UL)) +#define bFM4_EXTI_ELVR_LA10 *((volatile uint8_t *)(0x426001D0UL)) +#define bFM_EXTI_ELVR_LB10 *((volatile uint8_t *)(0x426001D4UL)) +#define bFM4_EXTI_ELVR_LB10 *((volatile uint8_t *)(0x426001D4UL)) +#define bFM_EXTI_ELVR_LA11 *((volatile uint8_t *)(0x426001D8UL)) +#define bFM4_EXTI_ELVR_LA11 *((volatile uint8_t *)(0x426001D8UL)) +#define bFM_EXTI_ELVR_LB11 *((volatile uint8_t *)(0x426001DCUL)) +#define bFM4_EXTI_ELVR_LB11 *((volatile uint8_t *)(0x426001DCUL)) +#define bFM_EXTI_ELVR_LA12 *((volatile uint8_t *)(0x426001E0UL)) +#define bFM4_EXTI_ELVR_LA12 *((volatile uint8_t *)(0x426001E0UL)) +#define bFM_EXTI_ELVR_LB12 *((volatile uint8_t *)(0x426001E4UL)) +#define bFM4_EXTI_ELVR_LB12 *((volatile uint8_t *)(0x426001E4UL)) +#define bFM_EXTI_ELVR_LA13 *((volatile uint8_t *)(0x426001E8UL)) +#define bFM4_EXTI_ELVR_LA13 *((volatile uint8_t *)(0x426001E8UL)) +#define bFM_EXTI_ELVR_LB13 *((volatile uint8_t *)(0x426001ECUL)) +#define bFM4_EXTI_ELVR_LB13 *((volatile uint8_t *)(0x426001ECUL)) +#define bFM_EXTI_ELVR_LA14 *((volatile uint8_t *)(0x426001F0UL)) +#define bFM4_EXTI_ELVR_LA14 *((volatile uint8_t *)(0x426001F0UL)) +#define bFM_EXTI_ELVR_LB14 *((volatile uint8_t *)(0x426001F4UL)) +#define bFM4_EXTI_ELVR_LB14 *((volatile uint8_t *)(0x426001F4UL)) +#define bFM_EXTI_ELVR_LA15 *((volatile uint8_t *)(0x426001F8UL)) +#define bFM4_EXTI_ELVR_LA15 *((volatile uint8_t *)(0x426001F8UL)) +#define bFM_EXTI_ELVR_LB15 *((volatile uint8_t *)(0x426001FCUL)) +#define bFM4_EXTI_ELVR_LB15 *((volatile uint8_t *)(0x426001FCUL)) + +#define bFM_EXTI_ELVR1_LA16 *((volatile uint8_t *)(0x42600200UL)) +#define bFM4_EXTI_ELVR1_LA16 *((volatile uint8_t *)(0x42600200UL)) +#define bFM_EXTI_ELVR1_LB16 *((volatile uint8_t *)(0x42600204UL)) +#define bFM4_EXTI_ELVR1_LB16 *((volatile uint8_t *)(0x42600204UL)) +#define bFM_EXTI_ELVR1_LA17 *((volatile uint8_t *)(0x42600208UL)) +#define bFM4_EXTI_ELVR1_LA17 *((volatile uint8_t *)(0x42600208UL)) +#define bFM_EXTI_ELVR1_LB17 *((volatile uint8_t *)(0x4260020CUL)) +#define bFM4_EXTI_ELVR1_LB17 *((volatile uint8_t *)(0x4260020CUL)) +#define bFM_EXTI_ELVR1_LA18 *((volatile uint8_t *)(0x42600210UL)) +#define bFM4_EXTI_ELVR1_LA18 *((volatile uint8_t *)(0x42600210UL)) +#define bFM_EXTI_ELVR1_LB18 *((volatile uint8_t *)(0x42600214UL)) +#define bFM4_EXTI_ELVR1_LB18 *((volatile uint8_t *)(0x42600214UL)) +#define bFM_EXTI_ELVR1_LA19 *((volatile uint8_t *)(0x42600218UL)) +#define bFM4_EXTI_ELVR1_LA19 *((volatile uint8_t *)(0x42600218UL)) +#define bFM_EXTI_ELVR1_LB19 *((volatile uint8_t *)(0x4260021CUL)) +#define bFM4_EXTI_ELVR1_LB19 *((volatile uint8_t *)(0x4260021CUL)) +#define bFM_EXTI_ELVR1_LA20 *((volatile uint8_t *)(0x42600220UL)) +#define bFM4_EXTI_ELVR1_LA20 *((volatile uint8_t *)(0x42600220UL)) +#define bFM_EXTI_ELVR1_LB20 *((volatile uint8_t *)(0x42600224UL)) +#define bFM4_EXTI_ELVR1_LB20 *((volatile uint8_t *)(0x42600224UL)) +#define bFM_EXTI_ELVR1_LA21 *((volatile uint8_t *)(0x42600228UL)) +#define bFM4_EXTI_ELVR1_LA21 *((volatile uint8_t *)(0x42600228UL)) +#define bFM_EXTI_ELVR1_LB21 *((volatile uint8_t *)(0x4260022CUL)) +#define bFM4_EXTI_ELVR1_LB21 *((volatile uint8_t *)(0x4260022CUL)) +#define bFM_EXTI_ELVR1_LA22 *((volatile uint8_t *)(0x42600230UL)) +#define bFM4_EXTI_ELVR1_LA22 *((volatile uint8_t *)(0x42600230UL)) +#define bFM_EXTI_ELVR1_LB22 *((volatile uint8_t *)(0x42600234UL)) +#define bFM4_EXTI_ELVR1_LB22 *((volatile uint8_t *)(0x42600234UL)) +#define bFM_EXTI_ELVR1_LA23 *((volatile uint8_t *)(0x42600238UL)) +#define bFM4_EXTI_ELVR1_LA23 *((volatile uint8_t *)(0x42600238UL)) +#define bFM_EXTI_ELVR1_LB23 *((volatile uint8_t *)(0x4260023CUL)) +#define bFM4_EXTI_ELVR1_LB23 *((volatile uint8_t *)(0x4260023CUL)) +#define bFM_EXTI_ELVR1_LA24 *((volatile uint8_t *)(0x42600240UL)) +#define bFM4_EXTI_ELVR1_LA24 *((volatile uint8_t *)(0x42600240UL)) +#define bFM_EXTI_ELVR1_LB24 *((volatile uint8_t *)(0x42600244UL)) +#define bFM4_EXTI_ELVR1_LB24 *((volatile uint8_t *)(0x42600244UL)) +#define bFM_EXTI_ELVR1_LA25 *((volatile uint8_t *)(0x42600248UL)) +#define bFM4_EXTI_ELVR1_LA25 *((volatile uint8_t *)(0x42600248UL)) +#define bFM_EXTI_ELVR1_LB25 *((volatile uint8_t *)(0x4260024CUL)) +#define bFM4_EXTI_ELVR1_LB25 *((volatile uint8_t *)(0x4260024CUL)) +#define bFM_EXTI_ELVR1_LA26 *((volatile uint8_t *)(0x42600250UL)) +#define bFM4_EXTI_ELVR1_LA26 *((volatile uint8_t *)(0x42600250UL)) +#define bFM_EXTI_ELVR1_LB26 *((volatile uint8_t *)(0x42600254UL)) +#define bFM4_EXTI_ELVR1_LB26 *((volatile uint8_t *)(0x42600254UL)) +#define bFM_EXTI_ELVR1_LA27 *((volatile uint8_t *)(0x42600258UL)) +#define bFM4_EXTI_ELVR1_LA27 *((volatile uint8_t *)(0x42600258UL)) +#define bFM_EXTI_ELVR1_LB27 *((volatile uint8_t *)(0x4260025CUL)) +#define bFM4_EXTI_ELVR1_LB27 *((volatile uint8_t *)(0x4260025CUL)) +#define bFM_EXTI_ELVR1_LA28 *((volatile uint8_t *)(0x42600260UL)) +#define bFM4_EXTI_ELVR1_LA28 *((volatile uint8_t *)(0x42600260UL)) +#define bFM_EXTI_ELVR1_LB28 *((volatile uint8_t *)(0x42600264UL)) +#define bFM4_EXTI_ELVR1_LB28 *((volatile uint8_t *)(0x42600264UL)) +#define bFM_EXTI_ELVR1_LA29 *((volatile uint8_t *)(0x42600268UL)) +#define bFM4_EXTI_ELVR1_LA29 *((volatile uint8_t *)(0x42600268UL)) +#define bFM_EXTI_ELVR1_LB29 *((volatile uint8_t *)(0x4260026CUL)) +#define bFM4_EXTI_ELVR1_LB29 *((volatile uint8_t *)(0x4260026CUL)) +#define bFM_EXTI_ELVR1_LA30 *((volatile uint8_t *)(0x42600270UL)) +#define bFM4_EXTI_ELVR1_LA30 *((volatile uint8_t *)(0x42600270UL)) +#define bFM_EXTI_ELVR1_LB30 *((volatile uint8_t *)(0x42600274UL)) +#define bFM4_EXTI_ELVR1_LB30 *((volatile uint8_t *)(0x42600274UL)) +#define bFM_EXTI_ELVR1_LA31 *((volatile uint8_t *)(0x42600278UL)) +#define bFM4_EXTI_ELVR1_LA31 *((volatile uint8_t *)(0x42600278UL)) +#define bFM_EXTI_ELVR1_LB31 *((volatile uint8_t *)(0x4260027CUL)) +#define bFM4_EXTI_ELVR1_LB31 *((volatile uint8_t *)(0x4260027CUL)) + +#define bFM_EXTI_ENIR_EN0 *((volatile uint8_t *)(0x42600000UL)) +#define bFM4_EXTI_ENIR_EN0 *((volatile uint8_t *)(0x42600000UL)) +#define bFM_EXTI_ENIR_EN1 *((volatile uint8_t *)(0x42600004UL)) +#define bFM4_EXTI_ENIR_EN1 *((volatile uint8_t *)(0x42600004UL)) +#define bFM_EXTI_ENIR_EN2 *((volatile uint8_t *)(0x42600008UL)) +#define bFM4_EXTI_ENIR_EN2 *((volatile uint8_t *)(0x42600008UL)) +#define bFM_EXTI_ENIR_EN3 *((volatile uint8_t *)(0x4260000CUL)) +#define bFM4_EXTI_ENIR_EN3 *((volatile uint8_t *)(0x4260000CUL)) +#define bFM_EXTI_ENIR_EN4 *((volatile uint8_t *)(0x42600010UL)) +#define bFM4_EXTI_ENIR_EN4 *((volatile uint8_t *)(0x42600010UL)) +#define bFM_EXTI_ENIR_EN5 *((volatile uint8_t *)(0x42600014UL)) +#define bFM4_EXTI_ENIR_EN5 *((volatile uint8_t *)(0x42600014UL)) +#define bFM_EXTI_ENIR_EN6 *((volatile uint8_t *)(0x42600018UL)) +#define bFM4_EXTI_ENIR_EN6 *((volatile uint8_t *)(0x42600018UL)) +#define bFM_EXTI_ENIR_EN7 *((volatile uint8_t *)(0x4260001CUL)) +#define bFM4_EXTI_ENIR_EN7 *((volatile uint8_t *)(0x4260001CUL)) +#define bFM_EXTI_ENIR_EN8 *((volatile uint8_t *)(0x42600020UL)) +#define bFM4_EXTI_ENIR_EN8 *((volatile uint8_t *)(0x42600020UL)) +#define bFM_EXTI_ENIR_EN9 *((volatile uint8_t *)(0x42600024UL)) +#define bFM4_EXTI_ENIR_EN9 *((volatile uint8_t *)(0x42600024UL)) +#define bFM_EXTI_ENIR_EN10 *((volatile uint8_t *)(0x42600028UL)) +#define bFM4_EXTI_ENIR_EN10 *((volatile uint8_t *)(0x42600028UL)) +#define bFM_EXTI_ENIR_EN11 *((volatile uint8_t *)(0x4260002CUL)) +#define bFM4_EXTI_ENIR_EN11 *((volatile uint8_t *)(0x4260002CUL)) +#define bFM_EXTI_ENIR_EN12 *((volatile uint8_t *)(0x42600030UL)) +#define bFM4_EXTI_ENIR_EN12 *((volatile uint8_t *)(0x42600030UL)) +#define bFM_EXTI_ENIR_EN13 *((volatile uint8_t *)(0x42600034UL)) +#define bFM4_EXTI_ENIR_EN13 *((volatile uint8_t *)(0x42600034UL)) +#define bFM_EXTI_ENIR_EN14 *((volatile uint8_t *)(0x42600038UL)) +#define bFM4_EXTI_ENIR_EN14 *((volatile uint8_t *)(0x42600038UL)) +#define bFM_EXTI_ENIR_EN15 *((volatile uint8_t *)(0x4260003CUL)) +#define bFM4_EXTI_ENIR_EN15 *((volatile uint8_t *)(0x4260003CUL)) +#define bFM_EXTI_ENIR_EN16 *((volatile uint8_t *)(0x42600040UL)) +#define bFM4_EXTI_ENIR_EN16 *((volatile uint8_t *)(0x42600040UL)) +#define bFM_EXTI_ENIR_EN17 *((volatile uint8_t *)(0x42600044UL)) +#define bFM4_EXTI_ENIR_EN17 *((volatile uint8_t *)(0x42600044UL)) +#define bFM_EXTI_ENIR_EN18 *((volatile uint8_t *)(0x42600048UL)) +#define bFM4_EXTI_ENIR_EN18 *((volatile uint8_t *)(0x42600048UL)) +#define bFM_EXTI_ENIR_EN19 *((volatile uint8_t *)(0x4260004CUL)) +#define bFM4_EXTI_ENIR_EN19 *((volatile uint8_t *)(0x4260004CUL)) +#define bFM_EXTI_ENIR_EN20 *((volatile uint8_t *)(0x42600050UL)) +#define bFM4_EXTI_ENIR_EN20 *((volatile uint8_t *)(0x42600050UL)) +#define bFM_EXTI_ENIR_EN21 *((volatile uint8_t *)(0x42600054UL)) +#define bFM4_EXTI_ENIR_EN21 *((volatile uint8_t *)(0x42600054UL)) +#define bFM_EXTI_ENIR_EN22 *((volatile uint8_t *)(0x42600058UL)) +#define bFM4_EXTI_ENIR_EN22 *((volatile uint8_t *)(0x42600058UL)) +#define bFM_EXTI_ENIR_EN23 *((volatile uint8_t *)(0x4260005CUL)) +#define bFM4_EXTI_ENIR_EN23 *((volatile uint8_t *)(0x4260005CUL)) +#define bFM_EXTI_ENIR_EN24 *((volatile uint8_t *)(0x42600060UL)) +#define bFM4_EXTI_ENIR_EN24 *((volatile uint8_t *)(0x42600060UL)) +#define bFM_EXTI_ENIR_EN25 *((volatile uint8_t *)(0x42600064UL)) +#define bFM4_EXTI_ENIR_EN25 *((volatile uint8_t *)(0x42600064UL)) +#define bFM_EXTI_ENIR_EN26 *((volatile uint8_t *)(0x42600068UL)) +#define bFM4_EXTI_ENIR_EN26 *((volatile uint8_t *)(0x42600068UL)) +#define bFM_EXTI_ENIR_EN27 *((volatile uint8_t *)(0x4260006CUL)) +#define bFM4_EXTI_ENIR_EN27 *((volatile uint8_t *)(0x4260006CUL)) +#define bFM_EXTI_ENIR_EN28 *((volatile uint8_t *)(0x42600070UL)) +#define bFM4_EXTI_ENIR_EN28 *((volatile uint8_t *)(0x42600070UL)) +#define bFM_EXTI_ENIR_EN29 *((volatile uint8_t *)(0x42600074UL)) +#define bFM4_EXTI_ENIR_EN29 *((volatile uint8_t *)(0x42600074UL)) +#define bFM_EXTI_ENIR_EN30 *((volatile uint8_t *)(0x42600078UL)) +#define bFM4_EXTI_ENIR_EN30 *((volatile uint8_t *)(0x42600078UL)) +#define bFM_EXTI_ENIR_EN31 *((volatile uint8_t *)(0x4260007CUL)) +#define bFM4_EXTI_ENIR_EN31 *((volatile uint8_t *)(0x4260007CUL)) + +#define bFM_EXTI_NMICL_NCL *((volatile uint8_t *)(0x42600300UL)) +#define bFM4_EXTI_NMICL_NCL *((volatile uint8_t *)(0x42600300UL)) + +#define bFM_EXTI_NMIRR_NR *((volatile uint8_t *)(0x42600280UL)) +#define bFM4_EXTI_NMIRR_NR *((volatile uint8_t *)(0x42600280UL)) + + +/******************************************************************************* +* FLASH_IF Registers FLASH_IF +* Bitband Section +*******************************************************************************/ +#define bFM_FLASH_IF_DFCTRLR_DFE *((volatile uint32_t*)(0x42000600UL)) +#define bFM4_FLASH_IF_DFCTRLR_DFE *((volatile uint32_t*)(0x42000600UL)) +#define bFM_FLASH_IF_DFCTRLR_RME *((volatile uint32_t*)(0x42000604UL)) +#define bFM4_FLASH_IF_DFCTRLR_RME *((volatile uint32_t*)(0x42000604UL)) + +#define bFM_FLASH_IF_FBFCR_BE *((volatile uint8_t *)(0x42000280UL)) +#define bFM4_FLASH_IF_FBFCR_BE *((volatile uint8_t *)(0x42000280UL)) +#define bFM_FLASH_IF_FBFCR_BS *((volatile uint8_t *)(0x42000284UL)) +#define bFM4_FLASH_IF_FBFCR_BS *((volatile uint8_t *)(0x42000284UL)) + +#define bFM_FLASH_IF_FICLR_RDYIC *((volatile uint8_t *)(0x42000500UL)) +#define bFM4_FLASH_IF_FICLR_RDYIC *((volatile uint8_t *)(0x42000500UL)) +#define bFM_FLASH_IF_FICLR_HNGIC *((volatile uint8_t *)(0x42000504UL)) +#define bFM4_FLASH_IF_FICLR_HNGIC *((volatile uint8_t *)(0x42000504UL)) +#define bFM_FLASH_IF_FICLR_ERRIC *((volatile uint8_t *)(0x42000508UL)) +#define bFM4_FLASH_IF_FICLR_ERRIC *((volatile uint8_t *)(0x42000508UL)) + +#define bFM_FLASH_IF_FICR_RDYIE *((volatile uint8_t *)(0x42000400UL)) +#define bFM4_FLASH_IF_FICR_RDYIE *((volatile uint8_t *)(0x42000400UL)) +#define bFM_FLASH_IF_FICR_HNGIE *((volatile uint8_t *)(0x42000404UL)) +#define bFM4_FLASH_IF_FICR_HNGIE *((volatile uint8_t *)(0x42000404UL)) +#define bFM_FLASH_IF_FICR_ERRIE *((volatile uint8_t *)(0x42000408UL)) +#define bFM4_FLASH_IF_FICR_ERRIE *((volatile uint8_t *)(0x42000408UL)) + +#define bFM_FLASH_IF_FISR_RDYIF *((volatile uint8_t *)(0x42000480UL)) +#define bFM4_FLASH_IF_FISR_RDYIF *((volatile uint8_t *)(0x42000480UL)) +#define bFM_FLASH_IF_FISR_HNGIF *((volatile uint8_t *)(0x42000484UL)) +#define bFM4_FLASH_IF_FISR_HNGIF *((volatile uint8_t *)(0x42000484UL)) +#define bFM_FLASH_IF_FISR_ERRIF *((volatile uint8_t *)(0x42000488UL)) +#define bFM4_FLASH_IF_FISR_ERRIF *((volatile uint8_t *)(0x42000488UL)) + +#define bFM_FLASH_IF_FSTR_RDY *((volatile uint8_t *)(0x42000100UL)) +#define bFM4_FLASH_IF_FSTR_RDY *((volatile uint8_t *)(0x42000100UL)) +#define bFM_FLASH_IF_FSTR_HNG *((volatile uint8_t *)(0x42000104UL)) +#define bFM4_FLASH_IF_FSTR_HNG *((volatile uint8_t *)(0x42000104UL)) +#define bFM_FLASH_IF_FSTR_ERR *((volatile uint8_t *)(0x42000108UL)) +#define bFM4_FLASH_IF_FSTR_ERR *((volatile uint8_t *)(0x42000108UL)) + + +/******************************************************************************* +* GPIO Registers GPIO +* Bitband Section +*******************************************************************************/ +#define bFM_GPIO_ADE_AN00 *((volatile uint8_t *)(0x42DEA000UL)) +#define bFM4_GPIO_ADE_AN00 *((volatile uint8_t *)(0x42DEA000UL)) +#define bFM_GPIO_ADE_AN01 *((volatile uint8_t *)(0x42DEA004UL)) +#define bFM4_GPIO_ADE_AN01 *((volatile uint8_t *)(0x42DEA004UL)) +#define bFM_GPIO_ADE_AN02 *((volatile uint8_t *)(0x42DEA008UL)) +#define bFM4_GPIO_ADE_AN02 *((volatile uint8_t *)(0x42DEA008UL)) +#define bFM_GPIO_ADE_AN03 *((volatile uint8_t *)(0x42DEA00CUL)) +#define bFM4_GPIO_ADE_AN03 *((volatile uint8_t *)(0x42DEA00CUL)) +#define bFM_GPIO_ADE_AN04 *((volatile uint8_t *)(0x42DEA010UL)) +#define bFM4_GPIO_ADE_AN04 *((volatile uint8_t *)(0x42DEA010UL)) +#define bFM_GPIO_ADE_AN05 *((volatile uint8_t *)(0x42DEA014UL)) +#define bFM4_GPIO_ADE_AN05 *((volatile uint8_t *)(0x42DEA014UL)) +#define bFM_GPIO_ADE_AN06 *((volatile uint8_t *)(0x42DEA018UL)) +#define bFM4_GPIO_ADE_AN06 *((volatile uint8_t *)(0x42DEA018UL)) +#define bFM_GPIO_ADE_AN07 *((volatile uint8_t *)(0x42DEA01CUL)) +#define bFM4_GPIO_ADE_AN07 *((volatile uint8_t *)(0x42DEA01CUL)) +#define bFM_GPIO_ADE_AN08 *((volatile uint8_t *)(0x42DEA020UL)) +#define bFM4_GPIO_ADE_AN08 *((volatile uint8_t *)(0x42DEA020UL)) +#define bFM_GPIO_ADE_AN09 *((volatile uint8_t *)(0x42DEA024UL)) +#define bFM4_GPIO_ADE_AN09 *((volatile uint8_t *)(0x42DEA024UL)) +#define bFM_GPIO_ADE_AN10 *((volatile uint8_t *)(0x42DEA028UL)) +#define bFM4_GPIO_ADE_AN10 *((volatile uint8_t *)(0x42DEA028UL)) +#define bFM_GPIO_ADE_AN11 *((volatile uint8_t *)(0x42DEA02CUL)) +#define bFM4_GPIO_ADE_AN11 *((volatile uint8_t *)(0x42DEA02CUL)) +#define bFM_GPIO_ADE_AN12 *((volatile uint8_t *)(0x42DEA030UL)) +#define bFM4_GPIO_ADE_AN12 *((volatile uint8_t *)(0x42DEA030UL)) +#define bFM_GPIO_ADE_AN13 *((volatile uint8_t *)(0x42DEA034UL)) +#define bFM4_GPIO_ADE_AN13 *((volatile uint8_t *)(0x42DEA034UL)) +#define bFM_GPIO_ADE_AN14 *((volatile uint8_t *)(0x42DEA038UL)) +#define bFM4_GPIO_ADE_AN14 *((volatile uint8_t *)(0x42DEA038UL)) +#define bFM_GPIO_ADE_AN15 *((volatile uint8_t *)(0x42DEA03CUL)) +#define bFM4_GPIO_ADE_AN15 *((volatile uint8_t *)(0x42DEA03CUL)) +#define bFM_GPIO_ADE_AN24 *((volatile uint8_t *)(0x42DEA060UL)) +#define bFM4_GPIO_ADE_AN24 *((volatile uint8_t *)(0x42DEA060UL)) +#define bFM_GPIO_ADE_AN25 *((volatile uint8_t *)(0x42DEA064UL)) +#define bFM4_GPIO_ADE_AN25 *((volatile uint8_t *)(0x42DEA064UL)) +#define bFM_GPIO_ADE_AN26 *((volatile uint8_t *)(0x42DEA068UL)) +#define bFM4_GPIO_ADE_AN26 *((volatile uint8_t *)(0x42DEA068UL)) +#define bFM_GPIO_ADE_AN27 *((volatile uint8_t *)(0x42DEA06CUL)) +#define bFM4_GPIO_ADE_AN27 *((volatile uint8_t *)(0x42DEA06CUL)) +#define bFM_GPIO_ADE_AN28 *((volatile uint8_t *)(0x42DEA070UL)) +#define bFM4_GPIO_ADE_AN28 *((volatile uint8_t *)(0x42DEA070UL)) +#define bFM_GPIO_ADE_AN29 *((volatile uint8_t *)(0x42DEA074UL)) +#define bFM4_GPIO_ADE_AN29 *((volatile uint8_t *)(0x42DEA074UL)) +#define bFM_GPIO_ADE_AN30 *((volatile uint8_t *)(0x42DEA078UL)) +#define bFM4_GPIO_ADE_AN30 *((volatile uint8_t *)(0x42DEA078UL)) +#define bFM_GPIO_ADE_AN31 *((volatile uint8_t *)(0x42DEA07CUL)) +#define bFM4_GPIO_ADE_AN31 *((volatile uint8_t *)(0x42DEA07CUL)) + +#define bFM_GPIO_DDR0_P0 *((volatile uint8_t *)(0x42DE4000UL)) +#define bFM4_GPIO_DDR0_P0 *((volatile uint8_t *)(0x42DE4000UL)) +#define bFM_GPIO_DDR0_P1 *((volatile uint8_t *)(0x42DE4004UL)) +#define bFM4_GPIO_DDR0_P1 *((volatile uint8_t *)(0x42DE4004UL)) +#define bFM_GPIO_DDR0_P2 *((volatile uint8_t *)(0x42DE4008UL)) +#define bFM4_GPIO_DDR0_P2 *((volatile uint8_t *)(0x42DE4008UL)) +#define bFM_GPIO_DDR0_P3 *((volatile uint8_t *)(0x42DE400CUL)) +#define bFM4_GPIO_DDR0_P3 *((volatile uint8_t *)(0x42DE400CUL)) +#define bFM_GPIO_DDR0_P4 *((volatile uint8_t *)(0x42DE4010UL)) +#define bFM4_GPIO_DDR0_P4 *((volatile uint8_t *)(0x42DE4010UL)) +#define bFM_GPIO_DDR0_P8 *((volatile uint8_t *)(0x42DE4020UL)) +#define bFM4_GPIO_DDR0_P8 *((volatile uint8_t *)(0x42DE4020UL)) +#define bFM_GPIO_DDR0_P9 *((volatile uint8_t *)(0x42DE4024UL)) +#define bFM4_GPIO_DDR0_P9 *((volatile uint8_t *)(0x42DE4024UL)) +#define bFM_GPIO_DDR0_PA *((volatile uint8_t *)(0x42DE4028UL)) +#define bFM4_GPIO_DDR0_PA *((volatile uint8_t *)(0x42DE4028UL)) + +#define bFM_GPIO_DDR1_P0 *((volatile uint8_t *)(0x42DE4080UL)) +#define bFM4_GPIO_DDR1_P0 *((volatile uint8_t *)(0x42DE4080UL)) +#define bFM_GPIO_DDR1_P1 *((volatile uint8_t *)(0x42DE4084UL)) +#define bFM4_GPIO_DDR1_P1 *((volatile uint8_t *)(0x42DE4084UL)) +#define bFM_GPIO_DDR1_P2 *((volatile uint8_t *)(0x42DE4088UL)) +#define bFM4_GPIO_DDR1_P2 *((volatile uint8_t *)(0x42DE4088UL)) +#define bFM_GPIO_DDR1_P3 *((volatile uint8_t *)(0x42DE408CUL)) +#define bFM4_GPIO_DDR1_P3 *((volatile uint8_t *)(0x42DE408CUL)) +#define bFM_GPIO_DDR1_P4 *((volatile uint8_t *)(0x42DE4090UL)) +#define bFM4_GPIO_DDR1_P4 *((volatile uint8_t *)(0x42DE4090UL)) +#define bFM_GPIO_DDR1_P5 *((volatile uint8_t *)(0x42DE4094UL)) +#define bFM4_GPIO_DDR1_P5 *((volatile uint8_t *)(0x42DE4094UL)) +#define bFM_GPIO_DDR1_P6 *((volatile uint8_t *)(0x42DE4098UL)) +#define bFM4_GPIO_DDR1_P6 *((volatile uint8_t *)(0x42DE4098UL)) +#define bFM_GPIO_DDR1_P7 *((volatile uint8_t *)(0x42DE409CUL)) +#define bFM4_GPIO_DDR1_P7 *((volatile uint8_t *)(0x42DE409CUL)) +#define bFM_GPIO_DDR1_P8 *((volatile uint8_t *)(0x42DE40A0UL)) +#define bFM4_GPIO_DDR1_P8 *((volatile uint8_t *)(0x42DE40A0UL)) +#define bFM_GPIO_DDR1_P9 *((volatile uint8_t *)(0x42DE40A4UL)) +#define bFM4_GPIO_DDR1_P9 *((volatile uint8_t *)(0x42DE40A4UL)) +#define bFM_GPIO_DDR1_PA *((volatile uint8_t *)(0x42DE40A8UL)) +#define bFM4_GPIO_DDR1_PA *((volatile uint8_t *)(0x42DE40A8UL)) +#define bFM_GPIO_DDR1_PB *((volatile uint8_t *)(0x42DE40ACUL)) +#define bFM4_GPIO_DDR1_PB *((volatile uint8_t *)(0x42DE40ACUL)) +#define bFM_GPIO_DDR1_PC *((volatile uint8_t *)(0x42DE40B0UL)) +#define bFM4_GPIO_DDR1_PC *((volatile uint8_t *)(0x42DE40B0UL)) +#define bFM_GPIO_DDR1_PD *((volatile uint8_t *)(0x42DE40B4UL)) +#define bFM4_GPIO_DDR1_PD *((volatile uint8_t *)(0x42DE40B4UL)) +#define bFM_GPIO_DDR1_PE *((volatile uint8_t *)(0x42DE40B8UL)) +#define bFM4_GPIO_DDR1_PE *((volatile uint8_t *)(0x42DE40B8UL)) +#define bFM_GPIO_DDR1_PF *((volatile uint8_t *)(0x42DE40BCUL)) +#define bFM4_GPIO_DDR1_PF *((volatile uint8_t *)(0x42DE40BCUL)) + +#define bFM_GPIO_DDR2_P0 *((volatile uint8_t *)(0x42DE4100UL)) +#define bFM4_GPIO_DDR2_P0 *((volatile uint8_t *)(0x42DE4100UL)) +#define bFM_GPIO_DDR2_P1 *((volatile uint8_t *)(0x42DE4104UL)) +#define bFM4_GPIO_DDR2_P1 *((volatile uint8_t *)(0x42DE4104UL)) +#define bFM_GPIO_DDR2_P2 *((volatile uint8_t *)(0x42DE4108UL)) +#define bFM4_GPIO_DDR2_P2 *((volatile uint8_t *)(0x42DE4108UL)) +#define bFM_GPIO_DDR2_P3 *((volatile uint8_t *)(0x42DE410CUL)) +#define bFM4_GPIO_DDR2_P3 *((volatile uint8_t *)(0x42DE410CUL)) +#define bFM_GPIO_DDR2_P4 *((volatile uint8_t *)(0x42DE4110UL)) +#define bFM4_GPIO_DDR2_P4 *((volatile uint8_t *)(0x42DE4110UL)) +#define bFM_GPIO_DDR2_P5 *((volatile uint8_t *)(0x42DE4114UL)) +#define bFM4_GPIO_DDR2_P5 *((volatile uint8_t *)(0x42DE4114UL)) +#define bFM_GPIO_DDR2_P6 *((volatile uint8_t *)(0x42DE4118UL)) +#define bFM4_GPIO_DDR2_P6 *((volatile uint8_t *)(0x42DE4118UL)) +#define bFM_GPIO_DDR2_P7 *((volatile uint8_t *)(0x42DE411CUL)) +#define bFM4_GPIO_DDR2_P7 *((volatile uint8_t *)(0x42DE411CUL)) +#define bFM_GPIO_DDR2_P8 *((volatile uint8_t *)(0x42DE4120UL)) +#define bFM4_GPIO_DDR2_P8 *((volatile uint8_t *)(0x42DE4120UL)) +#define bFM_GPIO_DDR2_P9 *((volatile uint8_t *)(0x42DE4124UL)) +#define bFM4_GPIO_DDR2_P9 *((volatile uint8_t *)(0x42DE4124UL)) +#define bFM_GPIO_DDR2_PA *((volatile uint8_t *)(0x42DE4128UL)) +#define bFM4_GPIO_DDR2_PA *((volatile uint8_t *)(0x42DE4128UL)) + +#define bFM_GPIO_DDR3_P2 *((volatile uint8_t *)(0x42DE4188UL)) +#define bFM4_GPIO_DDR3_P2 *((volatile uint8_t *)(0x42DE4188UL)) +#define bFM_GPIO_DDR3_P3 *((volatile uint8_t *)(0x42DE418CUL)) +#define bFM4_GPIO_DDR3_P3 *((volatile uint8_t *)(0x42DE418CUL)) +#define bFM_GPIO_DDR3_P4 *((volatile uint8_t *)(0x42DE4190UL)) +#define bFM4_GPIO_DDR3_P4 *((volatile uint8_t *)(0x42DE4190UL)) +#define bFM_GPIO_DDR3_P5 *((volatile uint8_t *)(0x42DE4194UL)) +#define bFM4_GPIO_DDR3_P5 *((volatile uint8_t *)(0x42DE4194UL)) +#define bFM_GPIO_DDR3_P6 *((volatile uint8_t *)(0x42DE4198UL)) +#define bFM4_GPIO_DDR3_P6 *((volatile uint8_t *)(0x42DE4198UL)) +#define bFM_GPIO_DDR3_P7 *((volatile uint8_t *)(0x42DE419CUL)) +#define bFM4_GPIO_DDR3_P7 *((volatile uint8_t *)(0x42DE419CUL)) +#define bFM_GPIO_DDR3_P8 *((volatile uint8_t *)(0x42DE41A0UL)) +#define bFM4_GPIO_DDR3_P8 *((volatile uint8_t *)(0x42DE41A0UL)) +#define bFM_GPIO_DDR3_P9 *((volatile uint8_t *)(0x42DE41A4UL)) +#define bFM4_GPIO_DDR3_P9 *((volatile uint8_t *)(0x42DE41A4UL)) +#define bFM_GPIO_DDR3_PA *((volatile uint8_t *)(0x42DE41A8UL)) +#define bFM4_GPIO_DDR3_PA *((volatile uint8_t *)(0x42DE41A8UL)) +#define bFM_GPIO_DDR3_PB *((volatile uint8_t *)(0x42DE41ACUL)) +#define bFM4_GPIO_DDR3_PB *((volatile uint8_t *)(0x42DE41ACUL)) +#define bFM_GPIO_DDR3_PC *((volatile uint8_t *)(0x42DE41B0UL)) +#define bFM4_GPIO_DDR3_PC *((volatile uint8_t *)(0x42DE41B0UL)) +#define bFM_GPIO_DDR3_PD *((volatile uint8_t *)(0x42DE41B4UL)) +#define bFM4_GPIO_DDR3_PD *((volatile uint8_t *)(0x42DE41B4UL)) +#define bFM_GPIO_DDR3_PE *((volatile uint8_t *)(0x42DE41B8UL)) +#define bFM4_GPIO_DDR3_PE *((volatile uint8_t *)(0x42DE41B8UL)) + +#define bFM_GPIO_DDR4_P0 *((volatile uint8_t *)(0x42DE4200UL)) +#define bFM4_GPIO_DDR4_P0 *((volatile uint8_t *)(0x42DE4200UL)) +#define bFM_GPIO_DDR4_P1 *((volatile uint8_t *)(0x42DE4204UL)) +#define bFM4_GPIO_DDR4_P1 *((volatile uint8_t *)(0x42DE4204UL)) +#define bFM_GPIO_DDR4_P2 *((volatile uint8_t *)(0x42DE4208UL)) +#define bFM4_GPIO_DDR4_P2 *((volatile uint8_t *)(0x42DE4208UL)) +#define bFM_GPIO_DDR4_P3 *((volatile uint8_t *)(0x42DE420CUL)) +#define bFM4_GPIO_DDR4_P3 *((volatile uint8_t *)(0x42DE420CUL)) +#define bFM_GPIO_DDR4_P4 *((volatile uint8_t *)(0x42DE4210UL)) +#define bFM4_GPIO_DDR4_P4 *((volatile uint8_t *)(0x42DE4210UL)) +#define bFM_GPIO_DDR4_P5 *((volatile uint8_t *)(0x42DE4214UL)) +#define bFM4_GPIO_DDR4_P5 *((volatile uint8_t *)(0x42DE4214UL)) +#define bFM_GPIO_DDR4_P6 *((volatile uint8_t *)(0x42DE4218UL)) +#define bFM4_GPIO_DDR4_P6 *((volatile uint8_t *)(0x42DE4218UL)) +#define bFM_GPIO_DDR4_P7 *((volatile uint8_t *)(0x42DE421CUL)) +#define bFM4_GPIO_DDR4_P7 *((volatile uint8_t *)(0x42DE421CUL)) +#define bFM_GPIO_DDR4_P8 *((volatile uint8_t *)(0x42DE4220UL)) +#define bFM4_GPIO_DDR4_P8 *((volatile uint8_t *)(0x42DE4220UL)) +#define bFM_GPIO_DDR4_P9 *((volatile uint8_t *)(0x42DE4224UL)) +#define bFM4_GPIO_DDR4_P9 *((volatile uint8_t *)(0x42DE4224UL)) + +#define bFM_GPIO_DDR6_P0 *((volatile uint8_t *)(0x42DE4300UL)) +#define bFM4_GPIO_DDR6_P0 *((volatile uint8_t *)(0x42DE4300UL)) +#define bFM_GPIO_DDR6_P1 *((volatile uint8_t *)(0x42DE4304UL)) +#define bFM4_GPIO_DDR6_P1 *((volatile uint8_t *)(0x42DE4304UL)) +#define bFM_GPIO_DDR6_P2 *((volatile uint8_t *)(0x42DE4308UL)) +#define bFM4_GPIO_DDR6_P2 *((volatile uint8_t *)(0x42DE4308UL)) +#define bFM_GPIO_DDR6_P3 *((volatile uint8_t *)(0x42DE430CUL)) +#define bFM4_GPIO_DDR6_P3 *((volatile uint8_t *)(0x42DE430CUL)) +#define bFM_GPIO_DDR6_PE *((volatile uint8_t *)(0x42DE4338UL)) +#define bFM4_GPIO_DDR6_PE *((volatile uint8_t *)(0x42DE4338UL)) + +#define bFM_GPIO_DDR7_P0 *((volatile uint8_t *)(0x42DE4380UL)) +#define bFM4_GPIO_DDR7_P0 *((volatile uint8_t *)(0x42DE4380UL)) +#define bFM_GPIO_DDR7_P1 *((volatile uint8_t *)(0x42DE4384UL)) +#define bFM4_GPIO_DDR7_P1 *((volatile uint8_t *)(0x42DE4384UL)) +#define bFM_GPIO_DDR7_P2 *((volatile uint8_t *)(0x42DE4388UL)) +#define bFM4_GPIO_DDR7_P2 *((volatile uint8_t *)(0x42DE4388UL)) +#define bFM_GPIO_DDR7_P3 *((volatile uint8_t *)(0x42DE438CUL)) +#define bFM4_GPIO_DDR7_P3 *((volatile uint8_t *)(0x42DE438CUL)) +#define bFM_GPIO_DDR7_P4 *((volatile uint8_t *)(0x42DE4390UL)) +#define bFM4_GPIO_DDR7_P4 *((volatile uint8_t *)(0x42DE4390UL)) +#define bFM_GPIO_DDR7_P5 *((volatile uint8_t *)(0x42DE4394UL)) +#define bFM4_GPIO_DDR7_P5 *((volatile uint8_t *)(0x42DE4394UL)) +#define bFM_GPIO_DDR7_P6 *((volatile uint8_t *)(0x42DE4398UL)) +#define bFM4_GPIO_DDR7_P6 *((volatile uint8_t *)(0x42DE4398UL)) +#define bFM_GPIO_DDR7_P7 *((volatile uint8_t *)(0x42DE439CUL)) +#define bFM4_GPIO_DDR7_P7 *((volatile uint8_t *)(0x42DE439CUL)) +#define bFM_GPIO_DDR7_P8 *((volatile uint8_t *)(0x42DE43A0UL)) +#define bFM4_GPIO_DDR7_P8 *((volatile uint8_t *)(0x42DE43A0UL)) +#define bFM_GPIO_DDR7_P9 *((volatile uint8_t *)(0x42DE43A4UL)) +#define bFM4_GPIO_DDR7_P9 *((volatile uint8_t *)(0x42DE43A4UL)) +#define bFM_GPIO_DDR7_PA *((volatile uint8_t *)(0x42DE43A8UL)) +#define bFM4_GPIO_DDR7_PA *((volatile uint8_t *)(0x42DE43A8UL)) +#define bFM_GPIO_DDR7_PB *((volatile uint8_t *)(0x42DE43ACUL)) +#define bFM4_GPIO_DDR7_PB *((volatile uint8_t *)(0x42DE43ACUL)) +#define bFM_GPIO_DDR7_PC *((volatile uint8_t *)(0x42DE43B0UL)) +#define bFM4_GPIO_DDR7_PC *((volatile uint8_t *)(0x42DE43B0UL)) +#define bFM_GPIO_DDR7_PD *((volatile uint8_t *)(0x42DE43B4UL)) +#define bFM4_GPIO_DDR7_PD *((volatile uint8_t *)(0x42DE43B4UL)) +#define bFM_GPIO_DDR7_PE *((volatile uint8_t *)(0x42DE43B8UL)) +#define bFM4_GPIO_DDR7_PE *((volatile uint8_t *)(0x42DE43B8UL)) + +#define bFM_GPIO_DDR8_P0 *((volatile uint8_t *)(0x42DE4400UL)) +#define bFM4_GPIO_DDR8_P0 *((volatile uint8_t *)(0x42DE4400UL)) +#define bFM_GPIO_DDR8_P1 *((volatile uint8_t *)(0x42DE4404UL)) +#define bFM4_GPIO_DDR8_P1 *((volatile uint8_t *)(0x42DE4404UL)) +#define bFM_GPIO_DDR8_P2 *((volatile uint8_t *)(0x42DE4408UL)) +#define bFM4_GPIO_DDR8_P2 *((volatile uint8_t *)(0x42DE4408UL)) +#define bFM_GPIO_DDR8_P3 *((volatile uint8_t *)(0x42DE440CUL)) +#define bFM4_GPIO_DDR8_P3 *((volatile uint8_t *)(0x42DE440CUL)) + +#define bFM_GPIO_DDRA_P0 *((volatile uint8_t *)(0x42DE4500UL)) +#define bFM4_GPIO_DDRA_P0 *((volatile uint8_t *)(0x42DE4500UL)) +#define bFM_GPIO_DDRA_P1 *((volatile uint8_t *)(0x42DE4504UL)) +#define bFM4_GPIO_DDRA_P1 *((volatile uint8_t *)(0x42DE4504UL)) +#define bFM_GPIO_DDRA_P2 *((volatile uint8_t *)(0x42DE4508UL)) +#define bFM4_GPIO_DDRA_P2 *((volatile uint8_t *)(0x42DE4508UL)) +#define bFM_GPIO_DDRA_P3 *((volatile uint8_t *)(0x42DE450CUL)) +#define bFM4_GPIO_DDRA_P3 *((volatile uint8_t *)(0x42DE450CUL)) +#define bFM_GPIO_DDRA_P4 *((volatile uint8_t *)(0x42DE4510UL)) +#define bFM4_GPIO_DDRA_P4 *((volatile uint8_t *)(0x42DE4510UL)) +#define bFM_GPIO_DDRA_P5 *((volatile uint8_t *)(0x42DE4514UL)) +#define bFM4_GPIO_DDRA_P5 *((volatile uint8_t *)(0x42DE4514UL)) +#define bFM_GPIO_DDRA_P6 *((volatile uint8_t *)(0x42DE4518UL)) +#define bFM4_GPIO_DDRA_P6 *((volatile uint8_t *)(0x42DE4518UL)) +#define bFM_GPIO_DDRA_P7 *((volatile uint8_t *)(0x42DE451CUL)) +#define bFM4_GPIO_DDRA_P7 *((volatile uint8_t *)(0x42DE451CUL)) +#define bFM_GPIO_DDRA_P8 *((volatile uint8_t *)(0x42DE4520UL)) +#define bFM4_GPIO_DDRA_P8 *((volatile uint8_t *)(0x42DE4520UL)) +#define bFM_GPIO_DDRA_P9 *((volatile uint8_t *)(0x42DE4524UL)) +#define bFM4_GPIO_DDRA_P9 *((volatile uint8_t *)(0x42DE4524UL)) +#define bFM_GPIO_DDRA_PA *((volatile uint8_t *)(0x42DE4528UL)) +#define bFM4_GPIO_DDRA_PA *((volatile uint8_t *)(0x42DE4528UL)) +#define bFM_GPIO_DDRA_PB *((volatile uint8_t *)(0x42DE452CUL)) +#define bFM4_GPIO_DDRA_PB *((volatile uint8_t *)(0x42DE452CUL)) +#define bFM_GPIO_DDRA_PC *((volatile uint8_t *)(0x42DE4530UL)) +#define bFM4_GPIO_DDRA_PC *((volatile uint8_t *)(0x42DE4530UL)) +#define bFM_GPIO_DDRA_PD *((volatile uint8_t *)(0x42DE4534UL)) +#define bFM4_GPIO_DDRA_PD *((volatile uint8_t *)(0x42DE4534UL)) +#define bFM_GPIO_DDRA_PE *((volatile uint8_t *)(0x42DE4538UL)) +#define bFM4_GPIO_DDRA_PE *((volatile uint8_t *)(0x42DE4538UL)) +#define bFM_GPIO_DDRA_PF *((volatile uint8_t *)(0x42DE453CUL)) +#define bFM4_GPIO_DDRA_PF *((volatile uint8_t *)(0x42DE453CUL)) + +#define bFM_GPIO_DDRC_P0 *((volatile uint8_t *)(0x42DE4600UL)) +#define bFM4_GPIO_DDRC_P0 *((volatile uint8_t *)(0x42DE4600UL)) +#define bFM_GPIO_DDRC_P1 *((volatile uint8_t *)(0x42DE4604UL)) +#define bFM4_GPIO_DDRC_P1 *((volatile uint8_t *)(0x42DE4604UL)) +#define bFM_GPIO_DDRC_P2 *((volatile uint8_t *)(0x42DE4608UL)) +#define bFM4_GPIO_DDRC_P2 *((volatile uint8_t *)(0x42DE4608UL)) +#define bFM_GPIO_DDRC_P3 *((volatile uint8_t *)(0x42DE460CUL)) +#define bFM4_GPIO_DDRC_P3 *((volatile uint8_t *)(0x42DE460CUL)) +#define bFM_GPIO_DDRC_P4 *((volatile uint8_t *)(0x42DE4610UL)) +#define bFM4_GPIO_DDRC_P4 *((volatile uint8_t *)(0x42DE4610UL)) +#define bFM_GPIO_DDRC_P5 *((volatile uint8_t *)(0x42DE4614UL)) +#define bFM4_GPIO_DDRC_P5 *((volatile uint8_t *)(0x42DE4614UL)) +#define bFM_GPIO_DDRC_P6 *((volatile uint8_t *)(0x42DE4618UL)) +#define bFM4_GPIO_DDRC_P6 *((volatile uint8_t *)(0x42DE4618UL)) +#define bFM_GPIO_DDRC_P7 *((volatile uint8_t *)(0x42DE461CUL)) +#define bFM4_GPIO_DDRC_P7 *((volatile uint8_t *)(0x42DE461CUL)) +#define bFM_GPIO_DDRC_P8 *((volatile uint8_t *)(0x42DE4620UL)) +#define bFM4_GPIO_DDRC_P8 *((volatile uint8_t *)(0x42DE4620UL)) +#define bFM_GPIO_DDRC_P9 *((volatile uint8_t *)(0x42DE4624UL)) +#define bFM4_GPIO_DDRC_P9 *((volatile uint8_t *)(0x42DE4624UL)) +#define bFM_GPIO_DDRC_PA *((volatile uint8_t *)(0x42DE4628UL)) +#define bFM4_GPIO_DDRC_PA *((volatile uint8_t *)(0x42DE4628UL)) +#define bFM_GPIO_DDRC_PB *((volatile uint8_t *)(0x42DE462CUL)) +#define bFM4_GPIO_DDRC_PB *((volatile uint8_t *)(0x42DE462CUL)) +#define bFM_GPIO_DDRC_PC *((volatile uint8_t *)(0x42DE4630UL)) +#define bFM4_GPIO_DDRC_PC *((volatile uint8_t *)(0x42DE4630UL)) +#define bFM_GPIO_DDRC_PD *((volatile uint8_t *)(0x42DE4634UL)) +#define bFM4_GPIO_DDRC_PD *((volatile uint8_t *)(0x42DE4634UL)) +#define bFM_GPIO_DDRC_PE *((volatile uint8_t *)(0x42DE4638UL)) +#define bFM4_GPIO_DDRC_PE *((volatile uint8_t *)(0x42DE4638UL)) +#define bFM_GPIO_DDRC_PF *((volatile uint8_t *)(0x42DE463CUL)) +#define bFM4_GPIO_DDRC_PF *((volatile uint8_t *)(0x42DE463CUL)) + +#define bFM_GPIO_DDRD_P0 *((volatile uint8_t *)(0x42DE4680UL)) +#define bFM4_GPIO_DDRD_P0 *((volatile uint8_t *)(0x42DE4680UL)) +#define bFM_GPIO_DDRD_P1 *((volatile uint8_t *)(0x42DE4684UL)) +#define bFM4_GPIO_DDRD_P1 *((volatile uint8_t *)(0x42DE4684UL)) +#define bFM_GPIO_DDRD_P2 *((volatile uint8_t *)(0x42DE4688UL)) +#define bFM4_GPIO_DDRD_P2 *((volatile uint8_t *)(0x42DE4688UL)) + +#define bFM_GPIO_DDRE_P0 *((volatile uint8_t *)(0x42DE4700UL)) +#define bFM4_GPIO_DDRE_P0 *((volatile uint8_t *)(0x42DE4700UL)) +#define bFM_GPIO_DDRE_P2 *((volatile uint8_t *)(0x42DE4708UL)) +#define bFM4_GPIO_DDRE_P2 *((volatile uint8_t *)(0x42DE4708UL)) +#define bFM_GPIO_DDRE_P3 *((volatile uint8_t *)(0x42DE470CUL)) +#define bFM4_GPIO_DDRE_P3 *((volatile uint8_t *)(0x42DE470CUL)) + +#define bFM_GPIO_EPFR00_NMIS *((volatile uint8_t *)(0x42DEC000UL)) +#define bFM4_GPIO_EPFR00_NMIS *((volatile uint8_t *)(0x42DEC000UL)) +#define bFM_GPIO_EPFR00_USBP0E *((volatile uint8_t *)(0x42DEC024UL)) +#define bFM4_GPIO_EPFR00_USBP0E *((volatile uint8_t *)(0x42DEC024UL)) +#define bFM_GPIO_EPFR00_USBP1E *((volatile uint8_t *)(0x42DEC034UL)) +#define bFM4_GPIO_EPFR00_USBP1E *((volatile uint8_t *)(0x42DEC034UL)) +#define bFM_GPIO_EPFR00_JTAGEN0B *((volatile uint8_t *)(0x42DEC040UL)) +#define bFM4_GPIO_EPFR00_JTAGEN0B *((volatile uint8_t *)(0x42DEC040UL)) +#define bFM_GPIO_EPFR00_JTAGEN1S *((volatile uint8_t *)(0x42DEC044UL)) +#define bFM4_GPIO_EPFR00_JTAGEN1S *((volatile uint8_t *)(0x42DEC044UL)) +#define bFM_GPIO_EPFR00_TRC0E *((volatile uint8_t *)(0x42DEC060UL)) +#define bFM4_GPIO_EPFR00_TRC0E *((volatile uint8_t *)(0x42DEC060UL)) +#define bFM_GPIO_EPFR00_TRC1E *((volatile uint8_t *)(0x42DEC064UL)) +#define bFM4_GPIO_EPFR00_TRC1E *((volatile uint8_t *)(0x42DEC064UL)) +#define bFM_GPIO_EPFR00_TRC2E *((volatile uint8_t *)(0x42DEC068UL)) +#define bFM4_GPIO_EPFR00_TRC2E *((volatile uint8_t *)(0x42DEC068UL)) +#define bFM_GPIO_EPFR00_TRC3E *((volatile uint8_t *)(0x42DEC06CUL)) +#define bFM4_GPIO_EPFR00_TRC3E *((volatile uint8_t *)(0x42DEC06CUL)) + +#define bFM_GPIO_EPFR01_DTTI0C *((volatile uint8_t *)(0x42DEC0B0UL)) +#define bFM4_GPIO_EPFR01_DTTI0C *((volatile uint8_t *)(0x42DEC0B0UL)) + +#define bFM_GPIO_EPFR02_DTTI1C *((volatile uint8_t *)(0x42DEC130UL)) +#define bFM4_GPIO_EPFR02_DTTI1C *((volatile uint8_t *)(0x42DEC130UL)) + +#define bFM_GPIO_EPFR03_DTTI2C *((volatile uint8_t *)(0x42DEC1B0UL)) +#define bFM4_GPIO_EPFR03_DTTI2C *((volatile uint8_t *)(0x42DEC1B0UL)) + +#define bFM_GPIO_EPFR10_UEDEFB *((volatile uint8_t *)(0x42DEC500UL)) +#define bFM4_GPIO_EPFR10_UEDEFB *((volatile uint8_t *)(0x42DEC500UL)) +#define bFM_GPIO_EPFR10_UEDTHB *((volatile uint8_t *)(0x42DEC504UL)) +#define bFM4_GPIO_EPFR10_UEDTHB *((volatile uint8_t *)(0x42DEC504UL)) +#define bFM_GPIO_EPFR10_UECLKE *((volatile uint8_t *)(0x42DEC508UL)) +#define bFM4_GPIO_EPFR10_UECLKE *((volatile uint8_t *)(0x42DEC508UL)) +#define bFM_GPIO_EPFR10_UEWEXE *((volatile uint8_t *)(0x42DEC50CUL)) +#define bFM4_GPIO_EPFR10_UEWEXE *((volatile uint8_t *)(0x42DEC50CUL)) +#define bFM_GPIO_EPFR10_UEDQME *((volatile uint8_t *)(0x42DEC510UL)) +#define bFM4_GPIO_EPFR10_UEDQME *((volatile uint8_t *)(0x42DEC510UL)) +#define bFM_GPIO_EPFR10_UEOEXE *((volatile uint8_t *)(0x42DEC514UL)) +#define bFM4_GPIO_EPFR10_UEOEXE *((volatile uint8_t *)(0x42DEC514UL)) +#define bFM_GPIO_EPFR10_UEFLSE *((volatile uint8_t *)(0x42DEC518UL)) +#define bFM4_GPIO_EPFR10_UEFLSE *((volatile uint8_t *)(0x42DEC518UL)) +#define bFM_GPIO_EPFR10_UECS1E *((volatile uint8_t *)(0x42DEC51CUL)) +#define bFM4_GPIO_EPFR10_UECS1E *((volatile uint8_t *)(0x42DEC51CUL)) +#define bFM_GPIO_EPFR10_UECS2E *((volatile uint8_t *)(0x42DEC520UL)) +#define bFM4_GPIO_EPFR10_UECS2E *((volatile uint8_t *)(0x42DEC520UL)) +#define bFM_GPIO_EPFR10_UECS3E *((volatile uint8_t *)(0x42DEC524UL)) +#define bFM4_GPIO_EPFR10_UECS3E *((volatile uint8_t *)(0x42DEC524UL)) +#define bFM_GPIO_EPFR10_UECS4E *((volatile uint8_t *)(0x42DEC528UL)) +#define bFM4_GPIO_EPFR10_UECS4E *((volatile uint8_t *)(0x42DEC528UL)) +#define bFM_GPIO_EPFR10_UECS5E *((volatile uint8_t *)(0x42DEC52CUL)) +#define bFM4_GPIO_EPFR10_UECS5E *((volatile uint8_t *)(0x42DEC52CUL)) +#define bFM_GPIO_EPFR10_UECS6E *((volatile uint8_t *)(0x42DEC530UL)) +#define bFM4_GPIO_EPFR10_UECS6E *((volatile uint8_t *)(0x42DEC530UL)) +#define bFM_GPIO_EPFR10_UECS7E *((volatile uint8_t *)(0x42DEC534UL)) +#define bFM4_GPIO_EPFR10_UECS7E *((volatile uint8_t *)(0x42DEC534UL)) +#define bFM_GPIO_EPFR10_UEAOOE *((volatile uint8_t *)(0x42DEC538UL)) +#define bFM4_GPIO_EPFR10_UEAOOE *((volatile uint8_t *)(0x42DEC538UL)) +#define bFM_GPIO_EPFR10_UEA08E *((volatile uint8_t *)(0x42DEC53CUL)) +#define bFM4_GPIO_EPFR10_UEA08E *((volatile uint8_t *)(0x42DEC53CUL)) +#define bFM_GPIO_EPFR10_UEA09E *((volatile uint8_t *)(0x42DEC540UL)) +#define bFM4_GPIO_EPFR10_UEA09E *((volatile uint8_t *)(0x42DEC540UL)) +#define bFM_GPIO_EPFR10_UEA10E *((volatile uint8_t *)(0x42DEC544UL)) +#define bFM4_GPIO_EPFR10_UEA10E *((volatile uint8_t *)(0x42DEC544UL)) +#define bFM_GPIO_EPFR10_UEA11E *((volatile uint8_t *)(0x42DEC548UL)) +#define bFM4_GPIO_EPFR10_UEA11E *((volatile uint8_t *)(0x42DEC548UL)) +#define bFM_GPIO_EPFR10_UEA12E *((volatile uint8_t *)(0x42DEC54CUL)) +#define bFM4_GPIO_EPFR10_UEA12E *((volatile uint8_t *)(0x42DEC54CUL)) +#define bFM_GPIO_EPFR10_UEA13E *((volatile uint8_t *)(0x42DEC550UL)) +#define bFM4_GPIO_EPFR10_UEA13E *((volatile uint8_t *)(0x42DEC550UL)) +#define bFM_GPIO_EPFR10_UEA14E *((volatile uint8_t *)(0x42DEC554UL)) +#define bFM4_GPIO_EPFR10_UEA14E *((volatile uint8_t *)(0x42DEC554UL)) +#define bFM_GPIO_EPFR10_UEA15E *((volatile uint8_t *)(0x42DEC558UL)) +#define bFM4_GPIO_EPFR10_UEA15E *((volatile uint8_t *)(0x42DEC558UL)) +#define bFM_GPIO_EPFR10_UEA16E *((volatile uint8_t *)(0x42DEC55CUL)) +#define bFM4_GPIO_EPFR10_UEA16E *((volatile uint8_t *)(0x42DEC55CUL)) +#define bFM_GPIO_EPFR10_UEA17E *((volatile uint8_t *)(0x42DEC560UL)) +#define bFM4_GPIO_EPFR10_UEA17E *((volatile uint8_t *)(0x42DEC560UL)) +#define bFM_GPIO_EPFR10_UEA18E *((volatile uint8_t *)(0x42DEC564UL)) +#define bFM4_GPIO_EPFR10_UEA18E *((volatile uint8_t *)(0x42DEC564UL)) +#define bFM_GPIO_EPFR10_UEA19E *((volatile uint8_t *)(0x42DEC568UL)) +#define bFM4_GPIO_EPFR10_UEA19E *((volatile uint8_t *)(0x42DEC568UL)) +#define bFM_GPIO_EPFR10_UEA20E *((volatile uint8_t *)(0x42DEC56CUL)) +#define bFM4_GPIO_EPFR10_UEA20E *((volatile uint8_t *)(0x42DEC56CUL)) +#define bFM_GPIO_EPFR10_UEA21E *((volatile uint8_t *)(0x42DEC570UL)) +#define bFM4_GPIO_EPFR10_UEA21E *((volatile uint8_t *)(0x42DEC570UL)) +#define bFM_GPIO_EPFR10_UEA22E *((volatile uint8_t *)(0x42DEC574UL)) +#define bFM4_GPIO_EPFR10_UEA22E *((volatile uint8_t *)(0x42DEC574UL)) +#define bFM_GPIO_EPFR10_UEA23E *((volatile uint8_t *)(0x42DEC578UL)) +#define bFM4_GPIO_EPFR10_UEA23E *((volatile uint8_t *)(0x42DEC578UL)) +#define bFM_GPIO_EPFR10_UEA24E *((volatile uint8_t *)(0x42DEC57CUL)) +#define bFM4_GPIO_EPFR10_UEA24E *((volatile uint8_t *)(0x42DEC57CUL)) + +#define bFM_GPIO_EPFR11_UEALEE *((volatile uint8_t *)(0x42DEC580UL)) +#define bFM4_GPIO_EPFR11_UEALEE *((volatile uint8_t *)(0x42DEC580UL)) +#define bFM_GPIO_EPFR11_UECS0E *((volatile uint8_t *)(0x42DEC584UL)) +#define bFM4_GPIO_EPFR11_UECS0E *((volatile uint8_t *)(0x42DEC584UL)) +#define bFM_GPIO_EPFR11_UEA01E *((volatile uint8_t *)(0x42DEC588UL)) +#define bFM4_GPIO_EPFR11_UEA01E *((volatile uint8_t *)(0x42DEC588UL)) +#define bFM_GPIO_EPFR11_UEA02E *((volatile uint8_t *)(0x42DEC58CUL)) +#define bFM4_GPIO_EPFR11_UEA02E *((volatile uint8_t *)(0x42DEC58CUL)) +#define bFM_GPIO_EPFR11_UEA03E *((volatile uint8_t *)(0x42DEC590UL)) +#define bFM4_GPIO_EPFR11_UEA03E *((volatile uint8_t *)(0x42DEC590UL)) +#define bFM_GPIO_EPFR11_UEA04E *((volatile uint8_t *)(0x42DEC594UL)) +#define bFM4_GPIO_EPFR11_UEA04E *((volatile uint8_t *)(0x42DEC594UL)) +#define bFM_GPIO_EPFR11_UEA05E *((volatile uint8_t *)(0x42DEC598UL)) +#define bFM4_GPIO_EPFR11_UEA05E *((volatile uint8_t *)(0x42DEC598UL)) +#define bFM_GPIO_EPFR11_UEA06E *((volatile uint8_t *)(0x42DEC59CUL)) +#define bFM4_GPIO_EPFR11_UEA06E *((volatile uint8_t *)(0x42DEC59CUL)) +#define bFM_GPIO_EPFR11_UEA07E *((volatile uint8_t *)(0x42DEC5A0UL)) +#define bFM4_GPIO_EPFR11_UEA07E *((volatile uint8_t *)(0x42DEC5A0UL)) +#define bFM_GPIO_EPFR11_UED00B *((volatile uint8_t *)(0x42DEC5A4UL)) +#define bFM4_GPIO_EPFR11_UED00B *((volatile uint8_t *)(0x42DEC5A4UL)) +#define bFM_GPIO_EPFR11_UED01B *((volatile uint8_t *)(0x42DEC5A8UL)) +#define bFM4_GPIO_EPFR11_UED01B *((volatile uint8_t *)(0x42DEC5A8UL)) +#define bFM_GPIO_EPFR11_UED02B *((volatile uint8_t *)(0x42DEC5ACUL)) +#define bFM4_GPIO_EPFR11_UED02B *((volatile uint8_t *)(0x42DEC5ACUL)) +#define bFM_GPIO_EPFR11_UED03B *((volatile uint8_t *)(0x42DEC5B0UL)) +#define bFM4_GPIO_EPFR11_UED03B *((volatile uint8_t *)(0x42DEC5B0UL)) +#define bFM_GPIO_EPFR11_UED04B *((volatile uint8_t *)(0x42DEC5B4UL)) +#define bFM4_GPIO_EPFR11_UED04B *((volatile uint8_t *)(0x42DEC5B4UL)) +#define bFM_GPIO_EPFR11_UED05B *((volatile uint8_t *)(0x42DEC5B8UL)) +#define bFM4_GPIO_EPFR11_UED05B *((volatile uint8_t *)(0x42DEC5B8UL)) +#define bFM_GPIO_EPFR11_UED06B *((volatile uint8_t *)(0x42DEC5BCUL)) +#define bFM4_GPIO_EPFR11_UED06B *((volatile uint8_t *)(0x42DEC5BCUL)) +#define bFM_GPIO_EPFR11_UED07B *((volatile uint8_t *)(0x42DEC5C0UL)) +#define bFM4_GPIO_EPFR11_UED07B *((volatile uint8_t *)(0x42DEC5C0UL)) +#define bFM_GPIO_EPFR11_UED08B *((volatile uint8_t *)(0x42DEC5C4UL)) +#define bFM4_GPIO_EPFR11_UED08B *((volatile uint8_t *)(0x42DEC5C4UL)) +#define bFM_GPIO_EPFR11_UED09B *((volatile uint8_t *)(0x42DEC5C8UL)) +#define bFM4_GPIO_EPFR11_UED09B *((volatile uint8_t *)(0x42DEC5C8UL)) +#define bFM_GPIO_EPFR11_UED10B *((volatile uint8_t *)(0x42DEC5CCUL)) +#define bFM4_GPIO_EPFR11_UED10B *((volatile uint8_t *)(0x42DEC5CCUL)) +#define bFM_GPIO_EPFR11_UED11B *((volatile uint8_t *)(0x42DEC5D0UL)) +#define bFM4_GPIO_EPFR11_UED11B *((volatile uint8_t *)(0x42DEC5D0UL)) +#define bFM_GPIO_EPFR11_UED12B *((volatile uint8_t *)(0x42DEC5D4UL)) +#define bFM4_GPIO_EPFR11_UED12B *((volatile uint8_t *)(0x42DEC5D4UL)) +#define bFM_GPIO_EPFR11_UED13B *((volatile uint8_t *)(0x42DEC5D8UL)) +#define bFM4_GPIO_EPFR11_UED13B *((volatile uint8_t *)(0x42DEC5D8UL)) +#define bFM_GPIO_EPFR11_UED14B *((volatile uint8_t *)(0x42DEC5DCUL)) +#define bFM4_GPIO_EPFR11_UED14B *((volatile uint8_t *)(0x42DEC5DCUL)) +#define bFM_GPIO_EPFR11_UED15B *((volatile uint8_t *)(0x42DEC5E0UL)) +#define bFM4_GPIO_EPFR11_UED15B *((volatile uint8_t *)(0x42DEC5E0UL)) +#define bFM_GPIO_EPFR11_UERLC *((volatile uint8_t *)(0x42DEC5E4UL)) +#define bFM4_GPIO_EPFR11_UERLC *((volatile uint8_t *)(0x42DEC5E4UL)) + +#define bFM_GPIO_EPFR14_E_TD0E *((volatile uint8_t *)(0x42DEC748UL)) +#define bFM4_GPIO_EPFR14_E_TD0E *((volatile uint8_t *)(0x42DEC748UL)) +#define bFM_GPIO_EPFR14_E_TD1E *((volatile uint8_t *)(0x42DEC74CUL)) +#define bFM4_GPIO_EPFR14_E_TD1E *((volatile uint8_t *)(0x42DEC74CUL)) +#define bFM_GPIO_EPFR14_E_TE0E *((volatile uint8_t *)(0x42DEC750UL)) +#define bFM4_GPIO_EPFR14_E_TE0E *((volatile uint8_t *)(0x42DEC750UL)) +#define bFM_GPIO_EPFR14_E_TE1E *((volatile uint8_t *)(0x42DEC754UL)) +#define bFM4_GPIO_EPFR14_E_TE1E *((volatile uint8_t *)(0x42DEC754UL)) +#define bFM_GPIO_EPFR14_E_MC0E *((volatile uint8_t *)(0x42DEC758UL)) +#define bFM4_GPIO_EPFR14_E_MC0E *((volatile uint8_t *)(0x42DEC758UL)) +#define bFM_GPIO_EPFR14_E_MC1B *((volatile uint8_t *)(0x42DEC75CUL)) +#define bFM4_GPIO_EPFR14_E_MC1B *((volatile uint8_t *)(0x42DEC75CUL)) +#define bFM_GPIO_EPFR14_E_MD0B *((volatile uint8_t *)(0x42DEC760UL)) +#define bFM4_GPIO_EPFR14_E_MD0B *((volatile uint8_t *)(0x42DEC760UL)) +#define bFM_GPIO_EPFR14_E_MD1B *((volatile uint8_t *)(0x42DEC764UL)) +#define bFM4_GPIO_EPFR14_E_MD1B *((volatile uint8_t *)(0x42DEC764UL)) +#define bFM_GPIO_EPFR14_E_CKE *((volatile uint8_t *)(0x42DEC768UL)) +#define bFM4_GPIO_EPFR14_E_CKE *((volatile uint8_t *)(0x42DEC768UL)) +#define bFM_GPIO_EPFR14_E_PSE *((volatile uint8_t *)(0x42DEC76CUL)) +#define bFM4_GPIO_EPFR14_E_PSE *((volatile uint8_t *)(0x42DEC76CUL)) + +#define bFM_GPIO_EPFR16_SFMPAC *((volatile uint8_t *)(0x42DEC870UL)) +#define bFM4_GPIO_EPFR16_SFMPAC *((volatile uint8_t *)(0x42DEC870UL)) +#define bFM_GPIO_EPFR16_SFMPBC *((volatile uint8_t *)(0x42DEC874UL)) +#define bFM4_GPIO_EPFR16_SFMPBC *((volatile uint8_t *)(0x42DEC874UL)) + +#define bFM_GPIO_EPFR20_UESMCKE *((volatile uint8_t *)(0x42DECA00UL)) +#define bFM4_GPIO_EPFR20_UESMCKE *((volatile uint8_t *)(0x42DECA00UL)) +#define bFM_GPIO_EPFR20_UESMCEE *((volatile uint8_t *)(0x42DECA04UL)) +#define bFM4_GPIO_EPFR20_UESMCEE *((volatile uint8_t *)(0x42DECA04UL)) +#define bFM_GPIO_EPFR20_UERASE *((volatile uint8_t *)(0x42DECA08UL)) +#define bFM4_GPIO_EPFR20_UERASE *((volatile uint8_t *)(0x42DECA08UL)) +#define bFM_GPIO_EPFR20_UECASE *((volatile uint8_t *)(0x42DECA0CUL)) +#define bFM4_GPIO_EPFR20_UECASE *((volatile uint8_t *)(0x42DECA0CUL)) +#define bFM_GPIO_EPFR20_UEDWEXE *((volatile uint8_t *)(0x42DECA10UL)) +#define bFM4_GPIO_EPFR20_UEDWEXE *((volatile uint8_t *)(0x42DECA10UL)) +#define bFM_GPIO_EPFR20_UECSXE *((volatile uint8_t *)(0x42DECA14UL)) +#define bFM4_GPIO_EPFR20_UECSXE *((volatile uint8_t *)(0x42DECA14UL)) +#define bFM_GPIO_EPFR20_UEDQM2E *((volatile uint8_t *)(0x42DECA18UL)) +#define bFM4_GPIO_EPFR20_UEDQM2E *((volatile uint8_t *)(0x42DECA18UL)) +#define bFM_GPIO_EPFR20_UEDQM3E *((volatile uint8_t *)(0x42DECA1CUL)) +#define bFM4_GPIO_EPFR20_UEDQM3E *((volatile uint8_t *)(0x42DECA1CUL)) +#define bFM_GPIO_EPFR20_UEDTHHB *((volatile uint8_t *)(0x42DECA20UL)) +#define bFM4_GPIO_EPFR20_UEDTHHB *((volatile uint8_t *)(0x42DECA20UL)) +#define bFM_GPIO_EPFR20_UED16B *((volatile uint8_t *)(0x42DECA24UL)) +#define bFM4_GPIO_EPFR20_UED16B *((volatile uint8_t *)(0x42DECA24UL)) +#define bFM_GPIO_EPFR20_UED17B *((volatile uint8_t *)(0x42DECA28UL)) +#define bFM4_GPIO_EPFR20_UED17B *((volatile uint8_t *)(0x42DECA28UL)) +#define bFM_GPIO_EPFR20_UED18B *((volatile uint8_t *)(0x42DECA2CUL)) +#define bFM4_GPIO_EPFR20_UED18B *((volatile uint8_t *)(0x42DECA2CUL)) +#define bFM_GPIO_EPFR20_UED19B *((volatile uint8_t *)(0x42DECA30UL)) +#define bFM4_GPIO_EPFR20_UED19B *((volatile uint8_t *)(0x42DECA30UL)) +#define bFM_GPIO_EPFR20_UED20B *((volatile uint8_t *)(0x42DECA34UL)) +#define bFM4_GPIO_EPFR20_UED20B *((volatile uint8_t *)(0x42DECA34UL)) +#define bFM_GPIO_EPFR20_UED21B *((volatile uint8_t *)(0x42DECA38UL)) +#define bFM4_GPIO_EPFR20_UED21B *((volatile uint8_t *)(0x42DECA38UL)) +#define bFM_GPIO_EPFR20_UED22B *((volatile uint8_t *)(0x42DECA3CUL)) +#define bFM4_GPIO_EPFR20_UED22B *((volatile uint8_t *)(0x42DECA3CUL)) +#define bFM_GPIO_EPFR20_UED23B *((volatile uint8_t *)(0x42DECA40UL)) +#define bFM4_GPIO_EPFR20_UED23B *((volatile uint8_t *)(0x42DECA40UL)) +#define bFM_GPIO_EPFR20_UED24B *((volatile uint8_t *)(0x42DECA44UL)) +#define bFM4_GPIO_EPFR20_UED24B *((volatile uint8_t *)(0x42DECA44UL)) +#define bFM_GPIO_EPFR20_UED25B *((volatile uint8_t *)(0x42DECA48UL)) +#define bFM4_GPIO_EPFR20_UED25B *((volatile uint8_t *)(0x42DECA48UL)) +#define bFM_GPIO_EPFR20_UED26B *((volatile uint8_t *)(0x42DECA4CUL)) +#define bFM4_GPIO_EPFR20_UED26B *((volatile uint8_t *)(0x42DECA4CUL)) +#define bFM_GPIO_EPFR20_UED27B *((volatile uint8_t *)(0x42DECA50UL)) +#define bFM4_GPIO_EPFR20_UED27B *((volatile uint8_t *)(0x42DECA50UL)) +#define bFM_GPIO_EPFR20_UED28B *((volatile uint8_t *)(0x42DECA54UL)) +#define bFM4_GPIO_EPFR20_UED28B *((volatile uint8_t *)(0x42DECA54UL)) +#define bFM_GPIO_EPFR20_UED29B *((volatile uint8_t *)(0x42DECA58UL)) +#define bFM4_GPIO_EPFR20_UED29B *((volatile uint8_t *)(0x42DECA58UL)) +#define bFM_GPIO_EPFR20_UED30B *((volatile uint8_t *)(0x42DECA5CUL)) +#define bFM4_GPIO_EPFR20_UED30B *((volatile uint8_t *)(0x42DECA5CUL)) +#define bFM_GPIO_EPFR20_UED31B *((volatile uint8_t *)(0x42DECA60UL)) +#define bFM4_GPIO_EPFR20_UED31B *((volatile uint8_t *)(0x42DECA60UL)) + +#define bFM_GPIO_PCR0_P0 *((volatile uint8_t *)(0x42DE2000UL)) +#define bFM4_GPIO_PCR0_P0 *((volatile uint8_t *)(0x42DE2000UL)) +#define bFM_GPIO_PCR0_P1 *((volatile uint8_t *)(0x42DE2004UL)) +#define bFM4_GPIO_PCR0_P1 *((volatile uint8_t *)(0x42DE2004UL)) +#define bFM_GPIO_PCR0_P2 *((volatile uint8_t *)(0x42DE2008UL)) +#define bFM4_GPIO_PCR0_P2 *((volatile uint8_t *)(0x42DE2008UL)) +#define bFM_GPIO_PCR0_P3 *((volatile uint8_t *)(0x42DE200CUL)) +#define bFM4_GPIO_PCR0_P3 *((volatile uint8_t *)(0x42DE200CUL)) +#define bFM_GPIO_PCR0_P4 *((volatile uint8_t *)(0x42DE2010UL)) +#define bFM4_GPIO_PCR0_P4 *((volatile uint8_t *)(0x42DE2010UL)) +#define bFM_GPIO_PCR0_P8 *((volatile uint8_t *)(0x42DE2020UL)) +#define bFM4_GPIO_PCR0_P8 *((volatile uint8_t *)(0x42DE2020UL)) +#define bFM_GPIO_PCR0_P9 *((volatile uint8_t *)(0x42DE2024UL)) +#define bFM4_GPIO_PCR0_P9 *((volatile uint8_t *)(0x42DE2024UL)) +#define bFM_GPIO_PCR0_PA *((volatile uint8_t *)(0x42DE2028UL)) +#define bFM4_GPIO_PCR0_PA *((volatile uint8_t *)(0x42DE2028UL)) + +#define bFM_GPIO_PCR1_P0 *((volatile uint8_t *)(0x42DE2080UL)) +#define bFM4_GPIO_PCR1_P0 *((volatile uint8_t *)(0x42DE2080UL)) +#define bFM_GPIO_PCR1_P1 *((volatile uint8_t *)(0x42DE2084UL)) +#define bFM4_GPIO_PCR1_P1 *((volatile uint8_t *)(0x42DE2084UL)) +#define bFM_GPIO_PCR1_P2 *((volatile uint8_t *)(0x42DE2088UL)) +#define bFM4_GPIO_PCR1_P2 *((volatile uint8_t *)(0x42DE2088UL)) +#define bFM_GPIO_PCR1_P3 *((volatile uint8_t *)(0x42DE208CUL)) +#define bFM4_GPIO_PCR1_P3 *((volatile uint8_t *)(0x42DE208CUL)) +#define bFM_GPIO_PCR1_P4 *((volatile uint8_t *)(0x42DE2090UL)) +#define bFM4_GPIO_PCR1_P4 *((volatile uint8_t *)(0x42DE2090UL)) +#define bFM_GPIO_PCR1_P5 *((volatile uint8_t *)(0x42DE2094UL)) +#define bFM4_GPIO_PCR1_P5 *((volatile uint8_t *)(0x42DE2094UL)) +#define bFM_GPIO_PCR1_P6 *((volatile uint8_t *)(0x42DE2098UL)) +#define bFM4_GPIO_PCR1_P6 *((volatile uint8_t *)(0x42DE2098UL)) +#define bFM_GPIO_PCR1_P7 *((volatile uint8_t *)(0x42DE209CUL)) +#define bFM4_GPIO_PCR1_P7 *((volatile uint8_t *)(0x42DE209CUL)) +#define bFM_GPIO_PCR1_P8 *((volatile uint8_t *)(0x42DE20A0UL)) +#define bFM4_GPIO_PCR1_P8 *((volatile uint8_t *)(0x42DE20A0UL)) +#define bFM_GPIO_PCR1_P9 *((volatile uint8_t *)(0x42DE20A4UL)) +#define bFM4_GPIO_PCR1_P9 *((volatile uint8_t *)(0x42DE20A4UL)) +#define bFM_GPIO_PCR1_PA *((volatile uint8_t *)(0x42DE20A8UL)) +#define bFM4_GPIO_PCR1_PA *((volatile uint8_t *)(0x42DE20A8UL)) +#define bFM_GPIO_PCR1_PB *((volatile uint8_t *)(0x42DE20ACUL)) +#define bFM4_GPIO_PCR1_PB *((volatile uint8_t *)(0x42DE20ACUL)) +#define bFM_GPIO_PCR1_PC *((volatile uint8_t *)(0x42DE20B0UL)) +#define bFM4_GPIO_PCR1_PC *((volatile uint8_t *)(0x42DE20B0UL)) +#define bFM_GPIO_PCR1_PD *((volatile uint8_t *)(0x42DE20B4UL)) +#define bFM4_GPIO_PCR1_PD *((volatile uint8_t *)(0x42DE20B4UL)) +#define bFM_GPIO_PCR1_PE *((volatile uint8_t *)(0x42DE20B8UL)) +#define bFM4_GPIO_PCR1_PE *((volatile uint8_t *)(0x42DE20B8UL)) +#define bFM_GPIO_PCR1_PF *((volatile uint8_t *)(0x42DE20BCUL)) +#define bFM4_GPIO_PCR1_PF *((volatile uint8_t *)(0x42DE20BCUL)) + +#define bFM_GPIO_PCR2_P0 *((volatile uint8_t *)(0x42DE2100UL)) +#define bFM4_GPIO_PCR2_P0 *((volatile uint8_t *)(0x42DE2100UL)) +#define bFM_GPIO_PCR2_P1 *((volatile uint8_t *)(0x42DE2104UL)) +#define bFM4_GPIO_PCR2_P1 *((volatile uint8_t *)(0x42DE2104UL)) +#define bFM_GPIO_PCR2_P2 *((volatile uint8_t *)(0x42DE2108UL)) +#define bFM4_GPIO_PCR2_P2 *((volatile uint8_t *)(0x42DE2108UL)) +#define bFM_GPIO_PCR2_P3 *((volatile uint8_t *)(0x42DE210CUL)) +#define bFM4_GPIO_PCR2_P3 *((volatile uint8_t *)(0x42DE210CUL)) +#define bFM_GPIO_PCR2_P4 *((volatile uint8_t *)(0x42DE2110UL)) +#define bFM4_GPIO_PCR2_P4 *((volatile uint8_t *)(0x42DE2110UL)) +#define bFM_GPIO_PCR2_P5 *((volatile uint8_t *)(0x42DE2114UL)) +#define bFM4_GPIO_PCR2_P5 *((volatile uint8_t *)(0x42DE2114UL)) +#define bFM_GPIO_PCR2_P6 *((volatile uint8_t *)(0x42DE2118UL)) +#define bFM4_GPIO_PCR2_P6 *((volatile uint8_t *)(0x42DE2118UL)) +#define bFM_GPIO_PCR2_P7 *((volatile uint8_t *)(0x42DE211CUL)) +#define bFM4_GPIO_PCR2_P7 *((volatile uint8_t *)(0x42DE211CUL)) +#define bFM_GPIO_PCR2_P8 *((volatile uint8_t *)(0x42DE2120UL)) +#define bFM4_GPIO_PCR2_P8 *((volatile uint8_t *)(0x42DE2120UL)) +#define bFM_GPIO_PCR2_P9 *((volatile uint8_t *)(0x42DE2124UL)) +#define bFM4_GPIO_PCR2_P9 *((volatile uint8_t *)(0x42DE2124UL)) +#define bFM_GPIO_PCR2_PA *((volatile uint8_t *)(0x42DE2128UL)) +#define bFM4_GPIO_PCR2_PA *((volatile uint8_t *)(0x42DE2128UL)) + +#define bFM_GPIO_PCR3_P2 *((volatile uint8_t *)(0x42DE2188UL)) +#define bFM4_GPIO_PCR3_P2 *((volatile uint8_t *)(0x42DE2188UL)) +#define bFM_GPIO_PCR3_P3 *((volatile uint8_t *)(0x42DE218CUL)) +#define bFM4_GPIO_PCR3_P3 *((volatile uint8_t *)(0x42DE218CUL)) +#define bFM_GPIO_PCR3_P4 *((volatile uint8_t *)(0x42DE2190UL)) +#define bFM4_GPIO_PCR3_P4 *((volatile uint8_t *)(0x42DE2190UL)) +#define bFM_GPIO_PCR3_P5 *((volatile uint8_t *)(0x42DE2194UL)) +#define bFM4_GPIO_PCR3_P5 *((volatile uint8_t *)(0x42DE2194UL)) +#define bFM_GPIO_PCR3_P6 *((volatile uint8_t *)(0x42DE2198UL)) +#define bFM4_GPIO_PCR3_P6 *((volatile uint8_t *)(0x42DE2198UL)) +#define bFM_GPIO_PCR3_P7 *((volatile uint8_t *)(0x42DE219CUL)) +#define bFM4_GPIO_PCR3_P7 *((volatile uint8_t *)(0x42DE219CUL)) +#define bFM_GPIO_PCR3_P8 *((volatile uint8_t *)(0x42DE21A0UL)) +#define bFM4_GPIO_PCR3_P8 *((volatile uint8_t *)(0x42DE21A0UL)) +#define bFM_GPIO_PCR3_P9 *((volatile uint8_t *)(0x42DE21A4UL)) +#define bFM4_GPIO_PCR3_P9 *((volatile uint8_t *)(0x42DE21A4UL)) +#define bFM_GPIO_PCR3_PA *((volatile uint8_t *)(0x42DE21A8UL)) +#define bFM4_GPIO_PCR3_PA *((volatile uint8_t *)(0x42DE21A8UL)) +#define bFM_GPIO_PCR3_PB *((volatile uint8_t *)(0x42DE21ACUL)) +#define bFM4_GPIO_PCR3_PB *((volatile uint8_t *)(0x42DE21ACUL)) +#define bFM_GPIO_PCR3_PC *((volatile uint8_t *)(0x42DE21B0UL)) +#define bFM4_GPIO_PCR3_PC *((volatile uint8_t *)(0x42DE21B0UL)) +#define bFM_GPIO_PCR3_PD *((volatile uint8_t *)(0x42DE21B4UL)) +#define bFM4_GPIO_PCR3_PD *((volatile uint8_t *)(0x42DE21B4UL)) +#define bFM_GPIO_PCR3_PE *((volatile uint8_t *)(0x42DE21B8UL)) +#define bFM4_GPIO_PCR3_PE *((volatile uint8_t *)(0x42DE21B8UL)) + +#define bFM_GPIO_PCR4_P0 *((volatile uint8_t *)(0x42DE2200UL)) +#define bFM4_GPIO_PCR4_P0 *((volatile uint8_t *)(0x42DE2200UL)) +#define bFM_GPIO_PCR4_P1 *((volatile uint8_t *)(0x42DE2204UL)) +#define bFM4_GPIO_PCR4_P1 *((volatile uint8_t *)(0x42DE2204UL)) +#define bFM_GPIO_PCR4_P2 *((volatile uint8_t *)(0x42DE2208UL)) +#define bFM4_GPIO_PCR4_P2 *((volatile uint8_t *)(0x42DE2208UL)) +#define bFM_GPIO_PCR4_P3 *((volatile uint8_t *)(0x42DE220CUL)) +#define bFM4_GPIO_PCR4_P3 *((volatile uint8_t *)(0x42DE220CUL)) +#define bFM_GPIO_PCR4_P4 *((volatile uint8_t *)(0x42DE2210UL)) +#define bFM4_GPIO_PCR4_P4 *((volatile uint8_t *)(0x42DE2210UL)) +#define bFM_GPIO_PCR4_P5 *((volatile uint8_t *)(0x42DE2214UL)) +#define bFM4_GPIO_PCR4_P5 *((volatile uint8_t *)(0x42DE2214UL)) +#define bFM_GPIO_PCR4_P6 *((volatile uint8_t *)(0x42DE2218UL)) +#define bFM4_GPIO_PCR4_P6 *((volatile uint8_t *)(0x42DE2218UL)) +#define bFM_GPIO_PCR4_P7 *((volatile uint8_t *)(0x42DE221CUL)) +#define bFM4_GPIO_PCR4_P7 *((volatile uint8_t *)(0x42DE221CUL)) +#define bFM_GPIO_PCR4_P8 *((volatile uint8_t *)(0x42DE2220UL)) +#define bFM4_GPIO_PCR4_P8 *((volatile uint8_t *)(0x42DE2220UL)) +#define bFM_GPIO_PCR4_P9 *((volatile uint8_t *)(0x42DE2224UL)) +#define bFM4_GPIO_PCR4_P9 *((volatile uint8_t *)(0x42DE2224UL)) + +#define bFM_GPIO_PCR6_P0 *((volatile uint8_t *)(0x42DE2300UL)) +#define bFM4_GPIO_PCR6_P0 *((volatile uint8_t *)(0x42DE2300UL)) +#define bFM_GPIO_PCR6_P1 *((volatile uint8_t *)(0x42DE2304UL)) +#define bFM4_GPIO_PCR6_P1 *((volatile uint8_t *)(0x42DE2304UL)) +#define bFM_GPIO_PCR6_P2 *((volatile uint8_t *)(0x42DE2308UL)) +#define bFM4_GPIO_PCR6_P2 *((volatile uint8_t *)(0x42DE2308UL)) +#define bFM_GPIO_PCR6_P3 *((volatile uint8_t *)(0x42DE230CUL)) +#define bFM4_GPIO_PCR6_P3 *((volatile uint8_t *)(0x42DE230CUL)) +#define bFM_GPIO_PCR6_PE *((volatile uint8_t *)(0x42DE2338UL)) +#define bFM4_GPIO_PCR6_PE *((volatile uint8_t *)(0x42DE2338UL)) + +#define bFM_GPIO_PCR7_P0 *((volatile uint8_t *)(0x42DE2380UL)) +#define bFM4_GPIO_PCR7_P0 *((volatile uint8_t *)(0x42DE2380UL)) +#define bFM_GPIO_PCR7_P1 *((volatile uint8_t *)(0x42DE2384UL)) +#define bFM4_GPIO_PCR7_P1 *((volatile uint8_t *)(0x42DE2384UL)) +#define bFM_GPIO_PCR7_P2 *((volatile uint8_t *)(0x42DE2388UL)) +#define bFM4_GPIO_PCR7_P2 *((volatile uint8_t *)(0x42DE2388UL)) +#define bFM_GPIO_PCR7_P3 *((volatile uint8_t *)(0x42DE238CUL)) +#define bFM4_GPIO_PCR7_P3 *((volatile uint8_t *)(0x42DE238CUL)) +#define bFM_GPIO_PCR7_P4 *((volatile uint8_t *)(0x42DE2390UL)) +#define bFM4_GPIO_PCR7_P4 *((volatile uint8_t *)(0x42DE2390UL)) +#define bFM_GPIO_PCR7_P5 *((volatile uint8_t *)(0x42DE2394UL)) +#define bFM4_GPIO_PCR7_P5 *((volatile uint8_t *)(0x42DE2394UL)) +#define bFM_GPIO_PCR7_P6 *((volatile uint8_t *)(0x42DE2398UL)) +#define bFM4_GPIO_PCR7_P6 *((volatile uint8_t *)(0x42DE2398UL)) +#define bFM_GPIO_PCR7_P7 *((volatile uint8_t *)(0x42DE239CUL)) +#define bFM4_GPIO_PCR7_P7 *((volatile uint8_t *)(0x42DE239CUL)) +#define bFM_GPIO_PCR7_P8 *((volatile uint8_t *)(0x42DE23A0UL)) +#define bFM4_GPIO_PCR7_P8 *((volatile uint8_t *)(0x42DE23A0UL)) +#define bFM_GPIO_PCR7_P9 *((volatile uint8_t *)(0x42DE23A4UL)) +#define bFM4_GPIO_PCR7_P9 *((volatile uint8_t *)(0x42DE23A4UL)) +#define bFM_GPIO_PCR7_PA *((volatile uint8_t *)(0x42DE23A8UL)) +#define bFM4_GPIO_PCR7_PA *((volatile uint8_t *)(0x42DE23A8UL)) +#define bFM_GPIO_PCR7_PB *((volatile uint8_t *)(0x42DE23ACUL)) +#define bFM4_GPIO_PCR7_PB *((volatile uint8_t *)(0x42DE23ACUL)) +#define bFM_GPIO_PCR7_PC *((volatile uint8_t *)(0x42DE23B0UL)) +#define bFM4_GPIO_PCR7_PC *((volatile uint8_t *)(0x42DE23B0UL)) +#define bFM_GPIO_PCR7_PD *((volatile uint8_t *)(0x42DE23B4UL)) +#define bFM4_GPIO_PCR7_PD *((volatile uint8_t *)(0x42DE23B4UL)) +#define bFM_GPIO_PCR7_PE *((volatile uint8_t *)(0x42DE23B8UL)) +#define bFM4_GPIO_PCR7_PE *((volatile uint8_t *)(0x42DE23B8UL)) + +#define bFM_GPIO_PCRA_P0 *((volatile uint8_t *)(0x42DE2500UL)) +#define bFM4_GPIO_PCRA_P0 *((volatile uint8_t *)(0x42DE2500UL)) +#define bFM_GPIO_PCRA_P1 *((volatile uint8_t *)(0x42DE2504UL)) +#define bFM4_GPIO_PCRA_P1 *((volatile uint8_t *)(0x42DE2504UL)) +#define bFM_GPIO_PCRA_P2 *((volatile uint8_t *)(0x42DE2508UL)) +#define bFM4_GPIO_PCRA_P2 *((volatile uint8_t *)(0x42DE2508UL)) +#define bFM_GPIO_PCRA_P3 *((volatile uint8_t *)(0x42DE250CUL)) +#define bFM4_GPIO_PCRA_P3 *((volatile uint8_t *)(0x42DE250CUL)) +#define bFM_GPIO_PCRA_P4 *((volatile uint8_t *)(0x42DE2510UL)) +#define bFM4_GPIO_PCRA_P4 *((volatile uint8_t *)(0x42DE2510UL)) +#define bFM_GPIO_PCRA_P5 *((volatile uint8_t *)(0x42DE2514UL)) +#define bFM4_GPIO_PCRA_P5 *((volatile uint8_t *)(0x42DE2514UL)) +#define bFM_GPIO_PCRA_P6 *((volatile uint8_t *)(0x42DE2518UL)) +#define bFM4_GPIO_PCRA_P6 *((volatile uint8_t *)(0x42DE2518UL)) +#define bFM_GPIO_PCRA_P7 *((volatile uint8_t *)(0x42DE251CUL)) +#define bFM4_GPIO_PCRA_P7 *((volatile uint8_t *)(0x42DE251CUL)) +#define bFM_GPIO_PCRA_P8 *((volatile uint8_t *)(0x42DE2520UL)) +#define bFM4_GPIO_PCRA_P8 *((volatile uint8_t *)(0x42DE2520UL)) +#define bFM_GPIO_PCRA_P9 *((volatile uint8_t *)(0x42DE2524UL)) +#define bFM4_GPIO_PCRA_P9 *((volatile uint8_t *)(0x42DE2524UL)) +#define bFM_GPIO_PCRA_PA *((volatile uint8_t *)(0x42DE2528UL)) +#define bFM4_GPIO_PCRA_PA *((volatile uint8_t *)(0x42DE2528UL)) +#define bFM_GPIO_PCRA_PB *((volatile uint8_t *)(0x42DE252CUL)) +#define bFM4_GPIO_PCRA_PB *((volatile uint8_t *)(0x42DE252CUL)) +#define bFM_GPIO_PCRA_PC *((volatile uint8_t *)(0x42DE2530UL)) +#define bFM4_GPIO_PCRA_PC *((volatile uint8_t *)(0x42DE2530UL)) +#define bFM_GPIO_PCRA_PD *((volatile uint8_t *)(0x42DE2534UL)) +#define bFM4_GPIO_PCRA_PD *((volatile uint8_t *)(0x42DE2534UL)) +#define bFM_GPIO_PCRA_PE *((volatile uint8_t *)(0x42DE2538UL)) +#define bFM4_GPIO_PCRA_PE *((volatile uint8_t *)(0x42DE2538UL)) +#define bFM_GPIO_PCRA_PF *((volatile uint8_t *)(0x42DE253CUL)) +#define bFM4_GPIO_PCRA_PF *((volatile uint8_t *)(0x42DE253CUL)) + +#define bFM_GPIO_PCRC_P0 *((volatile uint8_t *)(0x42DE2600UL)) +#define bFM4_GPIO_PCRC_P0 *((volatile uint8_t *)(0x42DE2600UL)) +#define bFM_GPIO_PCRC_P1 *((volatile uint8_t *)(0x42DE2604UL)) +#define bFM4_GPIO_PCRC_P1 *((volatile uint8_t *)(0x42DE2604UL)) +#define bFM_GPIO_PCRC_P2 *((volatile uint8_t *)(0x42DE2608UL)) +#define bFM4_GPIO_PCRC_P2 *((volatile uint8_t *)(0x42DE2608UL)) +#define bFM_GPIO_PCRC_P3 *((volatile uint8_t *)(0x42DE260CUL)) +#define bFM4_GPIO_PCRC_P3 *((volatile uint8_t *)(0x42DE260CUL)) +#define bFM_GPIO_PCRC_P4 *((volatile uint8_t *)(0x42DE2610UL)) +#define bFM4_GPIO_PCRC_P4 *((volatile uint8_t *)(0x42DE2610UL)) +#define bFM_GPIO_PCRC_P5 *((volatile uint8_t *)(0x42DE2614UL)) +#define bFM4_GPIO_PCRC_P5 *((volatile uint8_t *)(0x42DE2614UL)) +#define bFM_GPIO_PCRC_P6 *((volatile uint8_t *)(0x42DE2618UL)) +#define bFM4_GPIO_PCRC_P6 *((volatile uint8_t *)(0x42DE2618UL)) +#define bFM_GPIO_PCRC_P7 *((volatile uint8_t *)(0x42DE261CUL)) +#define bFM4_GPIO_PCRC_P7 *((volatile uint8_t *)(0x42DE261CUL)) +#define bFM_GPIO_PCRC_P8 *((volatile uint8_t *)(0x42DE2620UL)) +#define bFM4_GPIO_PCRC_P8 *((volatile uint8_t *)(0x42DE2620UL)) +#define bFM_GPIO_PCRC_P9 *((volatile uint8_t *)(0x42DE2624UL)) +#define bFM4_GPIO_PCRC_P9 *((volatile uint8_t *)(0x42DE2624UL)) +#define bFM_GPIO_PCRC_PA *((volatile uint8_t *)(0x42DE2628UL)) +#define bFM4_GPIO_PCRC_PA *((volatile uint8_t *)(0x42DE2628UL)) +#define bFM_GPIO_PCRC_PB *((volatile uint8_t *)(0x42DE262CUL)) +#define bFM4_GPIO_PCRC_PB *((volatile uint8_t *)(0x42DE262CUL)) +#define bFM_GPIO_PCRC_PC *((volatile uint8_t *)(0x42DE2630UL)) +#define bFM4_GPIO_PCRC_PC *((volatile uint8_t *)(0x42DE2630UL)) +#define bFM_GPIO_PCRC_PD *((volatile uint8_t *)(0x42DE2634UL)) +#define bFM4_GPIO_PCRC_PD *((volatile uint8_t *)(0x42DE2634UL)) +#define bFM_GPIO_PCRC_PE *((volatile uint8_t *)(0x42DE2638UL)) +#define bFM4_GPIO_PCRC_PE *((volatile uint8_t *)(0x42DE2638UL)) +#define bFM_GPIO_PCRC_PF *((volatile uint8_t *)(0x42DE263CUL)) +#define bFM4_GPIO_PCRC_PF *((volatile uint8_t *)(0x42DE263CUL)) + +#define bFM_GPIO_PCRD_P0 *((volatile uint8_t *)(0x42DE2680UL)) +#define bFM4_GPIO_PCRD_P0 *((volatile uint8_t *)(0x42DE2680UL)) +#define bFM_GPIO_PCRD_P1 *((volatile uint8_t *)(0x42DE2684UL)) +#define bFM4_GPIO_PCRD_P1 *((volatile uint8_t *)(0x42DE2684UL)) +#define bFM_GPIO_PCRD_P2 *((volatile uint8_t *)(0x42DE2688UL)) +#define bFM4_GPIO_PCRD_P2 *((volatile uint8_t *)(0x42DE2688UL)) + +#define bFM_GPIO_PCRE_P0 *((volatile uint8_t *)(0x42DE2700UL)) +#define bFM4_GPIO_PCRE_P0 *((volatile uint8_t *)(0x42DE2700UL)) +#define bFM_GPIO_PCRE_P2 *((volatile uint8_t *)(0x42DE2708UL)) +#define bFM4_GPIO_PCRE_P2 *((volatile uint8_t *)(0x42DE2708UL)) +#define bFM_GPIO_PCRE_P3 *((volatile uint8_t *)(0x42DE270CUL)) +#define bFM4_GPIO_PCRE_P3 *((volatile uint8_t *)(0x42DE270CUL)) + +#define bFM_GPIO_PDIR0_P0 *((volatile uint8_t *)(0x42DE6000UL)) +#define bFM4_GPIO_PDIR0_P0 *((volatile uint8_t *)(0x42DE6000UL)) +#define bFM_GPIO_PDIR0_P1 *((volatile uint8_t *)(0x42DE6004UL)) +#define bFM4_GPIO_PDIR0_P1 *((volatile uint8_t *)(0x42DE6004UL)) +#define bFM_GPIO_PDIR0_P2 *((volatile uint8_t *)(0x42DE6008UL)) +#define bFM4_GPIO_PDIR0_P2 *((volatile uint8_t *)(0x42DE6008UL)) +#define bFM_GPIO_PDIR0_P3 *((volatile uint8_t *)(0x42DE600CUL)) +#define bFM4_GPIO_PDIR0_P3 *((volatile uint8_t *)(0x42DE600CUL)) +#define bFM_GPIO_PDIR0_P4 *((volatile uint8_t *)(0x42DE6010UL)) +#define bFM4_GPIO_PDIR0_P4 *((volatile uint8_t *)(0x42DE6010UL)) +#define bFM_GPIO_PDIR0_P8 *((volatile uint8_t *)(0x42DE6020UL)) +#define bFM4_GPIO_PDIR0_P8 *((volatile uint8_t *)(0x42DE6020UL)) +#define bFM_GPIO_PDIR0_P9 *((volatile uint8_t *)(0x42DE6024UL)) +#define bFM4_GPIO_PDIR0_P9 *((volatile uint8_t *)(0x42DE6024UL)) +#define bFM_GPIO_PDIR0_PA *((volatile uint8_t *)(0x42DE6028UL)) +#define bFM4_GPIO_PDIR0_PA *((volatile uint8_t *)(0x42DE6028UL)) + +#define bFM_GPIO_PDIR1_P0 *((volatile uint8_t *)(0x42DE6080UL)) +#define bFM4_GPIO_PDIR1_P0 *((volatile uint8_t *)(0x42DE6080UL)) +#define bFM_GPIO_PDIR1_P1 *((volatile uint8_t *)(0x42DE6084UL)) +#define bFM4_GPIO_PDIR1_P1 *((volatile uint8_t *)(0x42DE6084UL)) +#define bFM_GPIO_PDIR1_P2 *((volatile uint8_t *)(0x42DE6088UL)) +#define bFM4_GPIO_PDIR1_P2 *((volatile uint8_t *)(0x42DE6088UL)) +#define bFM_GPIO_PDIR1_P3 *((volatile uint8_t *)(0x42DE608CUL)) +#define bFM4_GPIO_PDIR1_P3 *((volatile uint8_t *)(0x42DE608CUL)) +#define bFM_GPIO_PDIR1_P4 *((volatile uint8_t *)(0x42DE6090UL)) +#define bFM4_GPIO_PDIR1_P4 *((volatile uint8_t *)(0x42DE6090UL)) +#define bFM_GPIO_PDIR1_P5 *((volatile uint8_t *)(0x42DE6094UL)) +#define bFM4_GPIO_PDIR1_P5 *((volatile uint8_t *)(0x42DE6094UL)) +#define bFM_GPIO_PDIR1_P6 *((volatile uint8_t *)(0x42DE6098UL)) +#define bFM4_GPIO_PDIR1_P6 *((volatile uint8_t *)(0x42DE6098UL)) +#define bFM_GPIO_PDIR1_P7 *((volatile uint8_t *)(0x42DE609CUL)) +#define bFM4_GPIO_PDIR1_P7 *((volatile uint8_t *)(0x42DE609CUL)) +#define bFM_GPIO_PDIR1_P8 *((volatile uint8_t *)(0x42DE60A0UL)) +#define bFM4_GPIO_PDIR1_P8 *((volatile uint8_t *)(0x42DE60A0UL)) +#define bFM_GPIO_PDIR1_P9 *((volatile uint8_t *)(0x42DE60A4UL)) +#define bFM4_GPIO_PDIR1_P9 *((volatile uint8_t *)(0x42DE60A4UL)) +#define bFM_GPIO_PDIR1_PA *((volatile uint8_t *)(0x42DE60A8UL)) +#define bFM4_GPIO_PDIR1_PA *((volatile uint8_t *)(0x42DE60A8UL)) +#define bFM_GPIO_PDIR1_PB *((volatile uint8_t *)(0x42DE60ACUL)) +#define bFM4_GPIO_PDIR1_PB *((volatile uint8_t *)(0x42DE60ACUL)) +#define bFM_GPIO_PDIR1_PC *((volatile uint8_t *)(0x42DE60B0UL)) +#define bFM4_GPIO_PDIR1_PC *((volatile uint8_t *)(0x42DE60B0UL)) +#define bFM_GPIO_PDIR1_PD *((volatile uint8_t *)(0x42DE60B4UL)) +#define bFM4_GPIO_PDIR1_PD *((volatile uint8_t *)(0x42DE60B4UL)) +#define bFM_GPIO_PDIR1_PE *((volatile uint8_t *)(0x42DE60B8UL)) +#define bFM4_GPIO_PDIR1_PE *((volatile uint8_t *)(0x42DE60B8UL)) +#define bFM_GPIO_PDIR1_PF *((volatile uint8_t *)(0x42DE60BCUL)) +#define bFM4_GPIO_PDIR1_PF *((volatile uint8_t *)(0x42DE60BCUL)) + +#define bFM_GPIO_PDIR2_P0 *((volatile uint8_t *)(0x42DE6100UL)) +#define bFM4_GPIO_PDIR2_P0 *((volatile uint8_t *)(0x42DE6100UL)) +#define bFM_GPIO_PDIR2_P1 *((volatile uint8_t *)(0x42DE6104UL)) +#define bFM4_GPIO_PDIR2_P1 *((volatile uint8_t *)(0x42DE6104UL)) +#define bFM_GPIO_PDIR2_P2 *((volatile uint8_t *)(0x42DE6108UL)) +#define bFM4_GPIO_PDIR2_P2 *((volatile uint8_t *)(0x42DE6108UL)) +#define bFM_GPIO_PDIR2_P3 *((volatile uint8_t *)(0x42DE610CUL)) +#define bFM4_GPIO_PDIR2_P3 *((volatile uint8_t *)(0x42DE610CUL)) +#define bFM_GPIO_PDIR2_P4 *((volatile uint8_t *)(0x42DE6110UL)) +#define bFM4_GPIO_PDIR2_P4 *((volatile uint8_t *)(0x42DE6110UL)) +#define bFM_GPIO_PDIR2_P5 *((volatile uint8_t *)(0x42DE6114UL)) +#define bFM4_GPIO_PDIR2_P5 *((volatile uint8_t *)(0x42DE6114UL)) +#define bFM_GPIO_PDIR2_P6 *((volatile uint8_t *)(0x42DE6118UL)) +#define bFM4_GPIO_PDIR2_P6 *((volatile uint8_t *)(0x42DE6118UL)) +#define bFM_GPIO_PDIR2_P7 *((volatile uint8_t *)(0x42DE611CUL)) +#define bFM4_GPIO_PDIR2_P7 *((volatile uint8_t *)(0x42DE611CUL)) +#define bFM_GPIO_PDIR2_P8 *((volatile uint8_t *)(0x42DE6120UL)) +#define bFM4_GPIO_PDIR2_P8 *((volatile uint8_t *)(0x42DE6120UL)) +#define bFM_GPIO_PDIR2_P9 *((volatile uint8_t *)(0x42DE6124UL)) +#define bFM4_GPIO_PDIR2_P9 *((volatile uint8_t *)(0x42DE6124UL)) +#define bFM_GPIO_PDIR2_PA *((volatile uint8_t *)(0x42DE6128UL)) +#define bFM4_GPIO_PDIR2_PA *((volatile uint8_t *)(0x42DE6128UL)) + +#define bFM_GPIO_PDIR3_P2 *((volatile uint8_t *)(0x42DE6188UL)) +#define bFM4_GPIO_PDIR3_P2 *((volatile uint8_t *)(0x42DE6188UL)) +#define bFM_GPIO_PDIR3_P3 *((volatile uint8_t *)(0x42DE618CUL)) +#define bFM4_GPIO_PDIR3_P3 *((volatile uint8_t *)(0x42DE618CUL)) +#define bFM_GPIO_PDIR3_P4 *((volatile uint8_t *)(0x42DE6190UL)) +#define bFM4_GPIO_PDIR3_P4 *((volatile uint8_t *)(0x42DE6190UL)) +#define bFM_GPIO_PDIR3_P5 *((volatile uint8_t *)(0x42DE6194UL)) +#define bFM4_GPIO_PDIR3_P5 *((volatile uint8_t *)(0x42DE6194UL)) +#define bFM_GPIO_PDIR3_P6 *((volatile uint8_t *)(0x42DE6198UL)) +#define bFM4_GPIO_PDIR3_P6 *((volatile uint8_t *)(0x42DE6198UL)) +#define bFM_GPIO_PDIR3_P7 *((volatile uint8_t *)(0x42DE619CUL)) +#define bFM4_GPIO_PDIR3_P7 *((volatile uint8_t *)(0x42DE619CUL)) +#define bFM_GPIO_PDIR3_P8 *((volatile uint8_t *)(0x42DE61A0UL)) +#define bFM4_GPIO_PDIR3_P8 *((volatile uint8_t *)(0x42DE61A0UL)) +#define bFM_GPIO_PDIR3_P9 *((volatile uint8_t *)(0x42DE61A4UL)) +#define bFM4_GPIO_PDIR3_P9 *((volatile uint8_t *)(0x42DE61A4UL)) +#define bFM_GPIO_PDIR3_PA *((volatile uint8_t *)(0x42DE61A8UL)) +#define bFM4_GPIO_PDIR3_PA *((volatile uint8_t *)(0x42DE61A8UL)) +#define bFM_GPIO_PDIR3_PB *((volatile uint8_t *)(0x42DE61ACUL)) +#define bFM4_GPIO_PDIR3_PB *((volatile uint8_t *)(0x42DE61ACUL)) +#define bFM_GPIO_PDIR3_PC *((volatile uint8_t *)(0x42DE61B0UL)) +#define bFM4_GPIO_PDIR3_PC *((volatile uint8_t *)(0x42DE61B0UL)) +#define bFM_GPIO_PDIR3_PD *((volatile uint8_t *)(0x42DE61B4UL)) +#define bFM4_GPIO_PDIR3_PD *((volatile uint8_t *)(0x42DE61B4UL)) +#define bFM_GPIO_PDIR3_PE *((volatile uint8_t *)(0x42DE61B8UL)) +#define bFM4_GPIO_PDIR3_PE *((volatile uint8_t *)(0x42DE61B8UL)) + +#define bFM_GPIO_PDIR4_P0 *((volatile uint8_t *)(0x42DE6200UL)) +#define bFM4_GPIO_PDIR4_P0 *((volatile uint8_t *)(0x42DE6200UL)) +#define bFM_GPIO_PDIR4_P1 *((volatile uint8_t *)(0x42DE6204UL)) +#define bFM4_GPIO_PDIR4_P1 *((volatile uint8_t *)(0x42DE6204UL)) +#define bFM_GPIO_PDIR4_P2 *((volatile uint8_t *)(0x42DE6208UL)) +#define bFM4_GPIO_PDIR4_P2 *((volatile uint8_t *)(0x42DE6208UL)) +#define bFM_GPIO_PDIR4_P3 *((volatile uint8_t *)(0x42DE620CUL)) +#define bFM4_GPIO_PDIR4_P3 *((volatile uint8_t *)(0x42DE620CUL)) +#define bFM_GPIO_PDIR4_P4 *((volatile uint8_t *)(0x42DE6210UL)) +#define bFM4_GPIO_PDIR4_P4 *((volatile uint8_t *)(0x42DE6210UL)) +#define bFM_GPIO_PDIR4_P5 *((volatile uint8_t *)(0x42DE6214UL)) +#define bFM4_GPIO_PDIR4_P5 *((volatile uint8_t *)(0x42DE6214UL)) +#define bFM_GPIO_PDIR4_P6 *((volatile uint8_t *)(0x42DE6218UL)) +#define bFM4_GPIO_PDIR4_P6 *((volatile uint8_t *)(0x42DE6218UL)) +#define bFM_GPIO_PDIR4_P7 *((volatile uint8_t *)(0x42DE621CUL)) +#define bFM4_GPIO_PDIR4_P7 *((volatile uint8_t *)(0x42DE621CUL)) +#define bFM_GPIO_PDIR4_P8 *((volatile uint8_t *)(0x42DE6220UL)) +#define bFM4_GPIO_PDIR4_P8 *((volatile uint8_t *)(0x42DE6220UL)) +#define bFM_GPIO_PDIR4_P9 *((volatile uint8_t *)(0x42DE6224UL)) +#define bFM4_GPIO_PDIR4_P9 *((volatile uint8_t *)(0x42DE6224UL)) + +#define bFM_GPIO_PDIR6_P0 *((volatile uint8_t *)(0x42DE6300UL)) +#define bFM4_GPIO_PDIR6_P0 *((volatile uint8_t *)(0x42DE6300UL)) +#define bFM_GPIO_PDIR6_P1 *((volatile uint8_t *)(0x42DE6304UL)) +#define bFM4_GPIO_PDIR6_P1 *((volatile uint8_t *)(0x42DE6304UL)) +#define bFM_GPIO_PDIR6_P2 *((volatile uint8_t *)(0x42DE6308UL)) +#define bFM4_GPIO_PDIR6_P2 *((volatile uint8_t *)(0x42DE6308UL)) +#define bFM_GPIO_PDIR6_P3 *((volatile uint8_t *)(0x42DE630CUL)) +#define bFM4_GPIO_PDIR6_P3 *((volatile uint8_t *)(0x42DE630CUL)) +#define bFM_GPIO_PDIR6_PE *((volatile uint8_t *)(0x42DE6338UL)) +#define bFM4_GPIO_PDIR6_PE *((volatile uint8_t *)(0x42DE6338UL)) + +#define bFM_GPIO_PDIR7_P0 *((volatile uint8_t *)(0x42DE6380UL)) +#define bFM4_GPIO_PDIR7_P0 *((volatile uint8_t *)(0x42DE6380UL)) +#define bFM_GPIO_PDIR7_P1 *((volatile uint8_t *)(0x42DE6384UL)) +#define bFM4_GPIO_PDIR7_P1 *((volatile uint8_t *)(0x42DE6384UL)) +#define bFM_GPIO_PDIR7_P2 *((volatile uint8_t *)(0x42DE6388UL)) +#define bFM4_GPIO_PDIR7_P2 *((volatile uint8_t *)(0x42DE6388UL)) +#define bFM_GPIO_PDIR7_P3 *((volatile uint8_t *)(0x42DE638CUL)) +#define bFM4_GPIO_PDIR7_P3 *((volatile uint8_t *)(0x42DE638CUL)) +#define bFM_GPIO_PDIR7_P4 *((volatile uint8_t *)(0x42DE6390UL)) +#define bFM4_GPIO_PDIR7_P4 *((volatile uint8_t *)(0x42DE6390UL)) +#define bFM_GPIO_PDIR7_P5 *((volatile uint8_t *)(0x42DE6394UL)) +#define bFM4_GPIO_PDIR7_P5 *((volatile uint8_t *)(0x42DE6394UL)) +#define bFM_GPIO_PDIR7_P6 *((volatile uint8_t *)(0x42DE6398UL)) +#define bFM4_GPIO_PDIR7_P6 *((volatile uint8_t *)(0x42DE6398UL)) +#define bFM_GPIO_PDIR7_P7 *((volatile uint8_t *)(0x42DE639CUL)) +#define bFM4_GPIO_PDIR7_P7 *((volatile uint8_t *)(0x42DE639CUL)) +#define bFM_GPIO_PDIR7_P8 *((volatile uint8_t *)(0x42DE63A0UL)) +#define bFM4_GPIO_PDIR7_P8 *((volatile uint8_t *)(0x42DE63A0UL)) +#define bFM_GPIO_PDIR7_P9 *((volatile uint8_t *)(0x42DE63A4UL)) +#define bFM4_GPIO_PDIR7_P9 *((volatile uint8_t *)(0x42DE63A4UL)) +#define bFM_GPIO_PDIR7_PA *((volatile uint8_t *)(0x42DE63A8UL)) +#define bFM4_GPIO_PDIR7_PA *((volatile uint8_t *)(0x42DE63A8UL)) +#define bFM_GPIO_PDIR7_PB *((volatile uint8_t *)(0x42DE63ACUL)) +#define bFM4_GPIO_PDIR7_PB *((volatile uint8_t *)(0x42DE63ACUL)) +#define bFM_GPIO_PDIR7_PC *((volatile uint8_t *)(0x42DE63B0UL)) +#define bFM4_GPIO_PDIR7_PC *((volatile uint8_t *)(0x42DE63B0UL)) +#define bFM_GPIO_PDIR7_PD *((volatile uint8_t *)(0x42DE63B4UL)) +#define bFM4_GPIO_PDIR7_PD *((volatile uint8_t *)(0x42DE63B4UL)) +#define bFM_GPIO_PDIR7_PE *((volatile uint8_t *)(0x42DE63B8UL)) +#define bFM4_GPIO_PDIR7_PE *((volatile uint8_t *)(0x42DE63B8UL)) + +#define bFM_GPIO_PDIR8_P0 *((volatile uint8_t *)(0x42DE6400UL)) +#define bFM4_GPIO_PDIR8_P0 *((volatile uint8_t *)(0x42DE6400UL)) +#define bFM_GPIO_PDIR8_P1 *((volatile uint8_t *)(0x42DE6404UL)) +#define bFM4_GPIO_PDIR8_P1 *((volatile uint8_t *)(0x42DE6404UL)) +#define bFM_GPIO_PDIR8_P2 *((volatile uint8_t *)(0x42DE6408UL)) +#define bFM4_GPIO_PDIR8_P2 *((volatile uint8_t *)(0x42DE6408UL)) +#define bFM_GPIO_PDIR8_P3 *((volatile uint8_t *)(0x42DE640CUL)) +#define bFM4_GPIO_PDIR8_P3 *((volatile uint8_t *)(0x42DE640CUL)) + +#define bFM_GPIO_PDIRA_P0 *((volatile uint8_t *)(0x42DE6500UL)) +#define bFM4_GPIO_PDIRA_P0 *((volatile uint8_t *)(0x42DE6500UL)) +#define bFM_GPIO_PDIRA_P1 *((volatile uint8_t *)(0x42DE6504UL)) +#define bFM4_GPIO_PDIRA_P1 *((volatile uint8_t *)(0x42DE6504UL)) +#define bFM_GPIO_PDIRA_P2 *((volatile uint8_t *)(0x42DE6508UL)) +#define bFM4_GPIO_PDIRA_P2 *((volatile uint8_t *)(0x42DE6508UL)) +#define bFM_GPIO_PDIRA_P3 *((volatile uint8_t *)(0x42DE650CUL)) +#define bFM4_GPIO_PDIRA_P3 *((volatile uint8_t *)(0x42DE650CUL)) +#define bFM_GPIO_PDIRA_P4 *((volatile uint8_t *)(0x42DE6510UL)) +#define bFM4_GPIO_PDIRA_P4 *((volatile uint8_t *)(0x42DE6510UL)) +#define bFM_GPIO_PDIRA_P5 *((volatile uint8_t *)(0x42DE6514UL)) +#define bFM4_GPIO_PDIRA_P5 *((volatile uint8_t *)(0x42DE6514UL)) +#define bFM_GPIO_PDIRA_P6 *((volatile uint8_t *)(0x42DE6518UL)) +#define bFM4_GPIO_PDIRA_P6 *((volatile uint8_t *)(0x42DE6518UL)) +#define bFM_GPIO_PDIRA_P7 *((volatile uint8_t *)(0x42DE651CUL)) +#define bFM4_GPIO_PDIRA_P7 *((volatile uint8_t *)(0x42DE651CUL)) +#define bFM_GPIO_PDIRA_P8 *((volatile uint8_t *)(0x42DE6520UL)) +#define bFM4_GPIO_PDIRA_P8 *((volatile uint8_t *)(0x42DE6520UL)) +#define bFM_GPIO_PDIRA_P9 *((volatile uint8_t *)(0x42DE6524UL)) +#define bFM4_GPIO_PDIRA_P9 *((volatile uint8_t *)(0x42DE6524UL)) +#define bFM_GPIO_PDIRA_PA *((volatile uint8_t *)(0x42DE6528UL)) +#define bFM4_GPIO_PDIRA_PA *((volatile uint8_t *)(0x42DE6528UL)) +#define bFM_GPIO_PDIRA_PB *((volatile uint8_t *)(0x42DE652CUL)) +#define bFM4_GPIO_PDIRA_PB *((volatile uint8_t *)(0x42DE652CUL)) +#define bFM_GPIO_PDIRA_PC *((volatile uint8_t *)(0x42DE6530UL)) +#define bFM4_GPIO_PDIRA_PC *((volatile uint8_t *)(0x42DE6530UL)) +#define bFM_GPIO_PDIRA_PD *((volatile uint8_t *)(0x42DE6534UL)) +#define bFM4_GPIO_PDIRA_PD *((volatile uint8_t *)(0x42DE6534UL)) +#define bFM_GPIO_PDIRA_PE *((volatile uint8_t *)(0x42DE6538UL)) +#define bFM4_GPIO_PDIRA_PE *((volatile uint8_t *)(0x42DE6538UL)) +#define bFM_GPIO_PDIRA_PF *((volatile uint8_t *)(0x42DE653CUL)) +#define bFM4_GPIO_PDIRA_PF *((volatile uint8_t *)(0x42DE653CUL)) + +#define bFM_GPIO_PDIRC_P0 *((volatile uint8_t *)(0x42DE6600UL)) +#define bFM4_GPIO_PDIRC_P0 *((volatile uint8_t *)(0x42DE6600UL)) +#define bFM_GPIO_PDIRC_P1 *((volatile uint8_t *)(0x42DE6604UL)) +#define bFM4_GPIO_PDIRC_P1 *((volatile uint8_t *)(0x42DE6604UL)) +#define bFM_GPIO_PDIRC_P2 *((volatile uint8_t *)(0x42DE6608UL)) +#define bFM4_GPIO_PDIRC_P2 *((volatile uint8_t *)(0x42DE6608UL)) +#define bFM_GPIO_PDIRC_P3 *((volatile uint8_t *)(0x42DE660CUL)) +#define bFM4_GPIO_PDIRC_P3 *((volatile uint8_t *)(0x42DE660CUL)) +#define bFM_GPIO_PDIRC_P4 *((volatile uint8_t *)(0x42DE6610UL)) +#define bFM4_GPIO_PDIRC_P4 *((volatile uint8_t *)(0x42DE6610UL)) +#define bFM_GPIO_PDIRC_P5 *((volatile uint8_t *)(0x42DE6614UL)) +#define bFM4_GPIO_PDIRC_P5 *((volatile uint8_t *)(0x42DE6614UL)) +#define bFM_GPIO_PDIRC_P6 *((volatile uint8_t *)(0x42DE6618UL)) +#define bFM4_GPIO_PDIRC_P6 *((volatile uint8_t *)(0x42DE6618UL)) +#define bFM_GPIO_PDIRC_P7 *((volatile uint8_t *)(0x42DE661CUL)) +#define bFM4_GPIO_PDIRC_P7 *((volatile uint8_t *)(0x42DE661CUL)) +#define bFM_GPIO_PDIRC_P8 *((volatile uint8_t *)(0x42DE6620UL)) +#define bFM4_GPIO_PDIRC_P8 *((volatile uint8_t *)(0x42DE6620UL)) +#define bFM_GPIO_PDIRC_P9 *((volatile uint8_t *)(0x42DE6624UL)) +#define bFM4_GPIO_PDIRC_P9 *((volatile uint8_t *)(0x42DE6624UL)) +#define bFM_GPIO_PDIRC_PA *((volatile uint8_t *)(0x42DE6628UL)) +#define bFM4_GPIO_PDIRC_PA *((volatile uint8_t *)(0x42DE6628UL)) +#define bFM_GPIO_PDIRC_PB *((volatile uint8_t *)(0x42DE662CUL)) +#define bFM4_GPIO_PDIRC_PB *((volatile uint8_t *)(0x42DE662CUL)) +#define bFM_GPIO_PDIRC_PC *((volatile uint8_t *)(0x42DE6630UL)) +#define bFM4_GPIO_PDIRC_PC *((volatile uint8_t *)(0x42DE6630UL)) +#define bFM_GPIO_PDIRC_PD *((volatile uint8_t *)(0x42DE6634UL)) +#define bFM4_GPIO_PDIRC_PD *((volatile uint8_t *)(0x42DE6634UL)) +#define bFM_GPIO_PDIRC_PE *((volatile uint8_t *)(0x42DE6638UL)) +#define bFM4_GPIO_PDIRC_PE *((volatile uint8_t *)(0x42DE6638UL)) +#define bFM_GPIO_PDIRC_PF *((volatile uint8_t *)(0x42DE663CUL)) +#define bFM4_GPIO_PDIRC_PF *((volatile uint8_t *)(0x42DE663CUL)) + +#define bFM_GPIO_PDIRD_P0 *((volatile uint8_t *)(0x42DE6680UL)) +#define bFM4_GPIO_PDIRD_P0 *((volatile uint8_t *)(0x42DE6680UL)) +#define bFM_GPIO_PDIRD_P1 *((volatile uint8_t *)(0x42DE6684UL)) +#define bFM4_GPIO_PDIRD_P1 *((volatile uint8_t *)(0x42DE6684UL)) +#define bFM_GPIO_PDIRD_P2 *((volatile uint8_t *)(0x42DE6688UL)) +#define bFM4_GPIO_PDIRD_P2 *((volatile uint8_t *)(0x42DE6688UL)) + +#define bFM_GPIO_PDIRE_P0 *((volatile uint8_t *)(0x42DE6700UL)) +#define bFM4_GPIO_PDIRE_P0 *((volatile uint8_t *)(0x42DE6700UL)) +#define bFM_GPIO_PDIRE_P2 *((volatile uint8_t *)(0x42DE6708UL)) +#define bFM4_GPIO_PDIRE_P2 *((volatile uint8_t *)(0x42DE6708UL)) +#define bFM_GPIO_PDIRE_P3 *((volatile uint8_t *)(0x42DE670CUL)) +#define bFM4_GPIO_PDIRE_P3 *((volatile uint8_t *)(0x42DE670CUL)) + +#define bFM_GPIO_PDOR0_P0 *((volatile uint8_t *)(0x42DE8000UL)) +#define bFM4_GPIO_PDOR0_P0 *((volatile uint8_t *)(0x42DE8000UL)) +#define bFM_GPIO_PDOR0_P1 *((volatile uint8_t *)(0x42DE8004UL)) +#define bFM4_GPIO_PDOR0_P1 *((volatile uint8_t *)(0x42DE8004UL)) +#define bFM_GPIO_PDOR0_P2 *((volatile uint8_t *)(0x42DE8008UL)) +#define bFM4_GPIO_PDOR0_P2 *((volatile uint8_t *)(0x42DE8008UL)) +#define bFM_GPIO_PDOR0_P3 *((volatile uint8_t *)(0x42DE800CUL)) +#define bFM4_GPIO_PDOR0_P3 *((volatile uint8_t *)(0x42DE800CUL)) +#define bFM_GPIO_PDOR0_P4 *((volatile uint8_t *)(0x42DE8010UL)) +#define bFM4_GPIO_PDOR0_P4 *((volatile uint8_t *)(0x42DE8010UL)) +#define bFM_GPIO_PDOR0_P8 *((volatile uint8_t *)(0x42DE8020UL)) +#define bFM4_GPIO_PDOR0_P8 *((volatile uint8_t *)(0x42DE8020UL)) +#define bFM_GPIO_PDOR0_P9 *((volatile uint8_t *)(0x42DE8024UL)) +#define bFM4_GPIO_PDOR0_P9 *((volatile uint8_t *)(0x42DE8024UL)) +#define bFM_GPIO_PDOR0_PA *((volatile uint8_t *)(0x42DE8028UL)) +#define bFM4_GPIO_PDOR0_PA *((volatile uint8_t *)(0x42DE8028UL)) + +#define bFM_GPIO_PDOR1_P0 *((volatile uint8_t *)(0x42DE8080UL)) +#define bFM4_GPIO_PDOR1_P0 *((volatile uint8_t *)(0x42DE8080UL)) +#define bFM_GPIO_PDOR1_P1 *((volatile uint8_t *)(0x42DE8084UL)) +#define bFM4_GPIO_PDOR1_P1 *((volatile uint8_t *)(0x42DE8084UL)) +#define bFM_GPIO_PDOR1_P2 *((volatile uint8_t *)(0x42DE8088UL)) +#define bFM4_GPIO_PDOR1_P2 *((volatile uint8_t *)(0x42DE8088UL)) +#define bFM_GPIO_PDOR1_P3 *((volatile uint8_t *)(0x42DE808CUL)) +#define bFM4_GPIO_PDOR1_P3 *((volatile uint8_t *)(0x42DE808CUL)) +#define bFM_GPIO_PDOR1_P4 *((volatile uint8_t *)(0x42DE8090UL)) +#define bFM4_GPIO_PDOR1_P4 *((volatile uint8_t *)(0x42DE8090UL)) +#define bFM_GPIO_PDOR1_P5 *((volatile uint8_t *)(0x42DE8094UL)) +#define bFM4_GPIO_PDOR1_P5 *((volatile uint8_t *)(0x42DE8094UL)) +#define bFM_GPIO_PDOR1_P6 *((volatile uint8_t *)(0x42DE8098UL)) +#define bFM4_GPIO_PDOR1_P6 *((volatile uint8_t *)(0x42DE8098UL)) +#define bFM_GPIO_PDOR1_P7 *((volatile uint8_t *)(0x42DE809CUL)) +#define bFM4_GPIO_PDOR1_P7 *((volatile uint8_t *)(0x42DE809CUL)) +#define bFM_GPIO_PDOR1_P8 *((volatile uint8_t *)(0x42DE80A0UL)) +#define bFM4_GPIO_PDOR1_P8 *((volatile uint8_t *)(0x42DE80A0UL)) +#define bFM_GPIO_PDOR1_P9 *((volatile uint8_t *)(0x42DE80A4UL)) +#define bFM4_GPIO_PDOR1_P9 *((volatile uint8_t *)(0x42DE80A4UL)) +#define bFM_GPIO_PDOR1_PA *((volatile uint8_t *)(0x42DE80A8UL)) +#define bFM4_GPIO_PDOR1_PA *((volatile uint8_t *)(0x42DE80A8UL)) +#define bFM_GPIO_PDOR1_PB *((volatile uint8_t *)(0x42DE80ACUL)) +#define bFM4_GPIO_PDOR1_PB *((volatile uint8_t *)(0x42DE80ACUL)) +#define bFM_GPIO_PDOR1_PC *((volatile uint8_t *)(0x42DE80B0UL)) +#define bFM4_GPIO_PDOR1_PC *((volatile uint8_t *)(0x42DE80B0UL)) +#define bFM_GPIO_PDOR1_PD *((volatile uint8_t *)(0x42DE80B4UL)) +#define bFM4_GPIO_PDOR1_PD *((volatile uint8_t *)(0x42DE80B4UL)) +#define bFM_GPIO_PDOR1_PE *((volatile uint8_t *)(0x42DE80B8UL)) +#define bFM4_GPIO_PDOR1_PE *((volatile uint8_t *)(0x42DE80B8UL)) +#define bFM_GPIO_PDOR1_PF *((volatile uint8_t *)(0x42DE80BCUL)) +#define bFM4_GPIO_PDOR1_PF *((volatile uint8_t *)(0x42DE80BCUL)) + +#define bFM_GPIO_PDOR2_P0 *((volatile uint8_t *)(0x42DE8100UL)) +#define bFM4_GPIO_PDOR2_P0 *((volatile uint8_t *)(0x42DE8100UL)) +#define bFM_GPIO_PDOR2_P1 *((volatile uint8_t *)(0x42DE8104UL)) +#define bFM4_GPIO_PDOR2_P1 *((volatile uint8_t *)(0x42DE8104UL)) +#define bFM_GPIO_PDOR2_P2 *((volatile uint8_t *)(0x42DE8108UL)) +#define bFM4_GPIO_PDOR2_P2 *((volatile uint8_t *)(0x42DE8108UL)) +#define bFM_GPIO_PDOR2_P3 *((volatile uint8_t *)(0x42DE810CUL)) +#define bFM4_GPIO_PDOR2_P3 *((volatile uint8_t *)(0x42DE810CUL)) +#define bFM_GPIO_PDOR2_P4 *((volatile uint8_t *)(0x42DE8110UL)) +#define bFM4_GPIO_PDOR2_P4 *((volatile uint8_t *)(0x42DE8110UL)) +#define bFM_GPIO_PDOR2_P5 *((volatile uint8_t *)(0x42DE8114UL)) +#define bFM4_GPIO_PDOR2_P5 *((volatile uint8_t *)(0x42DE8114UL)) +#define bFM_GPIO_PDOR2_P6 *((volatile uint8_t *)(0x42DE8118UL)) +#define bFM4_GPIO_PDOR2_P6 *((volatile uint8_t *)(0x42DE8118UL)) +#define bFM_GPIO_PDOR2_P7 *((volatile uint8_t *)(0x42DE811CUL)) +#define bFM4_GPIO_PDOR2_P7 *((volatile uint8_t *)(0x42DE811CUL)) +#define bFM_GPIO_PDOR2_P8 *((volatile uint8_t *)(0x42DE8120UL)) +#define bFM4_GPIO_PDOR2_P8 *((volatile uint8_t *)(0x42DE8120UL)) +#define bFM_GPIO_PDOR2_P9 *((volatile uint8_t *)(0x42DE8124UL)) +#define bFM4_GPIO_PDOR2_P9 *((volatile uint8_t *)(0x42DE8124UL)) +#define bFM_GPIO_PDOR2_PA *((volatile uint8_t *)(0x42DE8128UL)) +#define bFM4_GPIO_PDOR2_PA *((volatile uint8_t *)(0x42DE8128UL)) + +#define bFM_GPIO_PDOR3_P2 *((volatile uint8_t *)(0x42DE8188UL)) +#define bFM4_GPIO_PDOR3_P2 *((volatile uint8_t *)(0x42DE8188UL)) +#define bFM_GPIO_PDOR3_P3 *((volatile uint8_t *)(0x42DE818CUL)) +#define bFM4_GPIO_PDOR3_P3 *((volatile uint8_t *)(0x42DE818CUL)) +#define bFM_GPIO_PDOR3_P4 *((volatile uint8_t *)(0x42DE8190UL)) +#define bFM4_GPIO_PDOR3_P4 *((volatile uint8_t *)(0x42DE8190UL)) +#define bFM_GPIO_PDOR3_P5 *((volatile uint8_t *)(0x42DE8194UL)) +#define bFM4_GPIO_PDOR3_P5 *((volatile uint8_t *)(0x42DE8194UL)) +#define bFM_GPIO_PDOR3_P6 *((volatile uint8_t *)(0x42DE8198UL)) +#define bFM4_GPIO_PDOR3_P6 *((volatile uint8_t *)(0x42DE8198UL)) +#define bFM_GPIO_PDOR3_P7 *((volatile uint8_t *)(0x42DE819CUL)) +#define bFM4_GPIO_PDOR3_P7 *((volatile uint8_t *)(0x42DE819CUL)) +#define bFM_GPIO_PDOR3_P8 *((volatile uint8_t *)(0x42DE81A0UL)) +#define bFM4_GPIO_PDOR3_P8 *((volatile uint8_t *)(0x42DE81A0UL)) +#define bFM_GPIO_PDOR3_P9 *((volatile uint8_t *)(0x42DE81A4UL)) +#define bFM4_GPIO_PDOR3_P9 *((volatile uint8_t *)(0x42DE81A4UL)) +#define bFM_GPIO_PDOR3_PA *((volatile uint8_t *)(0x42DE81A8UL)) +#define bFM4_GPIO_PDOR3_PA *((volatile uint8_t *)(0x42DE81A8UL)) +#define bFM_GPIO_PDOR3_PB *((volatile uint8_t *)(0x42DE81ACUL)) +#define bFM4_GPIO_PDOR3_PB *((volatile uint8_t *)(0x42DE81ACUL)) +#define bFM_GPIO_PDOR3_PC *((volatile uint8_t *)(0x42DE81B0UL)) +#define bFM4_GPIO_PDOR3_PC *((volatile uint8_t *)(0x42DE81B0UL)) +#define bFM_GPIO_PDOR3_PD *((volatile uint8_t *)(0x42DE81B4UL)) +#define bFM4_GPIO_PDOR3_PD *((volatile uint8_t *)(0x42DE81B4UL)) +#define bFM_GPIO_PDOR3_PE *((volatile uint8_t *)(0x42DE81B8UL)) +#define bFM4_GPIO_PDOR3_PE *((volatile uint8_t *)(0x42DE81B8UL)) + +#define bFM_GPIO_PDOR4_P0 *((volatile uint8_t *)(0x42DE8200UL)) +#define bFM4_GPIO_PDOR4_P0 *((volatile uint8_t *)(0x42DE8200UL)) +#define bFM_GPIO_PDOR4_P1 *((volatile uint8_t *)(0x42DE8204UL)) +#define bFM4_GPIO_PDOR4_P1 *((volatile uint8_t *)(0x42DE8204UL)) +#define bFM_GPIO_PDOR4_P2 *((volatile uint8_t *)(0x42DE8208UL)) +#define bFM4_GPIO_PDOR4_P2 *((volatile uint8_t *)(0x42DE8208UL)) +#define bFM_GPIO_PDOR4_P3 *((volatile uint8_t *)(0x42DE820CUL)) +#define bFM4_GPIO_PDOR4_P3 *((volatile uint8_t *)(0x42DE820CUL)) +#define bFM_GPIO_PDOR4_P4 *((volatile uint8_t *)(0x42DE8210UL)) +#define bFM4_GPIO_PDOR4_P4 *((volatile uint8_t *)(0x42DE8210UL)) +#define bFM_GPIO_PDOR4_P5 *((volatile uint8_t *)(0x42DE8214UL)) +#define bFM4_GPIO_PDOR4_P5 *((volatile uint8_t *)(0x42DE8214UL)) +#define bFM_GPIO_PDOR4_P6 *((volatile uint8_t *)(0x42DE8218UL)) +#define bFM4_GPIO_PDOR4_P6 *((volatile uint8_t *)(0x42DE8218UL)) +#define bFM_GPIO_PDOR4_P7 *((volatile uint8_t *)(0x42DE821CUL)) +#define bFM4_GPIO_PDOR4_P7 *((volatile uint8_t *)(0x42DE821CUL)) +#define bFM_GPIO_PDOR4_P8 *((volatile uint8_t *)(0x42DE8220UL)) +#define bFM4_GPIO_PDOR4_P8 *((volatile uint8_t *)(0x42DE8220UL)) +#define bFM_GPIO_PDOR4_P9 *((volatile uint8_t *)(0x42DE8224UL)) +#define bFM4_GPIO_PDOR4_P9 *((volatile uint8_t *)(0x42DE8224UL)) + +#define bFM_GPIO_PDOR6_P0 *((volatile uint8_t *)(0x42DE8300UL)) +#define bFM4_GPIO_PDOR6_P0 *((volatile uint8_t *)(0x42DE8300UL)) +#define bFM_GPIO_PDOR6_P1 *((volatile uint8_t *)(0x42DE8304UL)) +#define bFM4_GPIO_PDOR6_P1 *((volatile uint8_t *)(0x42DE8304UL)) +#define bFM_GPIO_PDOR6_P2 *((volatile uint8_t *)(0x42DE8308UL)) +#define bFM4_GPIO_PDOR6_P2 *((volatile uint8_t *)(0x42DE8308UL)) +#define bFM_GPIO_PDOR6_P3 *((volatile uint8_t *)(0x42DE830CUL)) +#define bFM4_GPIO_PDOR6_P3 *((volatile uint8_t *)(0x42DE830CUL)) +#define bFM_GPIO_PDOR6_PE *((volatile uint8_t *)(0x42DE8338UL)) +#define bFM4_GPIO_PDOR6_PE *((volatile uint8_t *)(0x42DE8338UL)) + +#define bFM_GPIO_PDOR7_P0 *((volatile uint8_t *)(0x42DE8380UL)) +#define bFM4_GPIO_PDOR7_P0 *((volatile uint8_t *)(0x42DE8380UL)) +#define bFM_GPIO_PDOR7_P1 *((volatile uint8_t *)(0x42DE8384UL)) +#define bFM4_GPIO_PDOR7_P1 *((volatile uint8_t *)(0x42DE8384UL)) +#define bFM_GPIO_PDOR7_P2 *((volatile uint8_t *)(0x42DE8388UL)) +#define bFM4_GPIO_PDOR7_P2 *((volatile uint8_t *)(0x42DE8388UL)) +#define bFM_GPIO_PDOR7_P3 *((volatile uint8_t *)(0x42DE838CUL)) +#define bFM4_GPIO_PDOR7_P3 *((volatile uint8_t *)(0x42DE838CUL)) +#define bFM_GPIO_PDOR7_P4 *((volatile uint8_t *)(0x42DE8390UL)) +#define bFM4_GPIO_PDOR7_P4 *((volatile uint8_t *)(0x42DE8390UL)) +#define bFM_GPIO_PDOR7_P5 *((volatile uint8_t *)(0x42DE8394UL)) +#define bFM4_GPIO_PDOR7_P5 *((volatile uint8_t *)(0x42DE8394UL)) +#define bFM_GPIO_PDOR7_P6 *((volatile uint8_t *)(0x42DE8398UL)) +#define bFM4_GPIO_PDOR7_P6 *((volatile uint8_t *)(0x42DE8398UL)) +#define bFM_GPIO_PDOR7_P7 *((volatile uint8_t *)(0x42DE839CUL)) +#define bFM4_GPIO_PDOR7_P7 *((volatile uint8_t *)(0x42DE839CUL)) +#define bFM_GPIO_PDOR7_P8 *((volatile uint8_t *)(0x42DE83A0UL)) +#define bFM4_GPIO_PDOR7_P8 *((volatile uint8_t *)(0x42DE83A0UL)) +#define bFM_GPIO_PDOR7_P9 *((volatile uint8_t *)(0x42DE83A4UL)) +#define bFM4_GPIO_PDOR7_P9 *((volatile uint8_t *)(0x42DE83A4UL)) +#define bFM_GPIO_PDOR7_PA *((volatile uint8_t *)(0x42DE83A8UL)) +#define bFM4_GPIO_PDOR7_PA *((volatile uint8_t *)(0x42DE83A8UL)) +#define bFM_GPIO_PDOR7_PB *((volatile uint8_t *)(0x42DE83ACUL)) +#define bFM4_GPIO_PDOR7_PB *((volatile uint8_t *)(0x42DE83ACUL)) +#define bFM_GPIO_PDOR7_PC *((volatile uint8_t *)(0x42DE83B0UL)) +#define bFM4_GPIO_PDOR7_PC *((volatile uint8_t *)(0x42DE83B0UL)) +#define bFM_GPIO_PDOR7_PD *((volatile uint8_t *)(0x42DE83B4UL)) +#define bFM4_GPIO_PDOR7_PD *((volatile uint8_t *)(0x42DE83B4UL)) +#define bFM_GPIO_PDOR7_PE *((volatile uint8_t *)(0x42DE83B8UL)) +#define bFM4_GPIO_PDOR7_PE *((volatile uint8_t *)(0x42DE83B8UL)) + +#define bFM_GPIO_PDOR8_P0 *((volatile uint8_t *)(0x42DE8400UL)) +#define bFM4_GPIO_PDOR8_P0 *((volatile uint8_t *)(0x42DE8400UL)) +#define bFM_GPIO_PDOR8_P1 *((volatile uint8_t *)(0x42DE8404UL)) +#define bFM4_GPIO_PDOR8_P1 *((volatile uint8_t *)(0x42DE8404UL)) +#define bFM_GPIO_PDOR8_P2 *((volatile uint8_t *)(0x42DE8408UL)) +#define bFM4_GPIO_PDOR8_P2 *((volatile uint8_t *)(0x42DE8408UL)) +#define bFM_GPIO_PDOR8_P3 *((volatile uint8_t *)(0x42DE840CUL)) +#define bFM4_GPIO_PDOR8_P3 *((volatile uint8_t *)(0x42DE840CUL)) + +#define bFM_GPIO_PDORA_P0 *((volatile uint8_t *)(0x42DE8500UL)) +#define bFM4_GPIO_PDORA_P0 *((volatile uint8_t *)(0x42DE8500UL)) +#define bFM_GPIO_PDORA_P1 *((volatile uint8_t *)(0x42DE8504UL)) +#define bFM4_GPIO_PDORA_P1 *((volatile uint8_t *)(0x42DE8504UL)) +#define bFM_GPIO_PDORA_P2 *((volatile uint8_t *)(0x42DE8508UL)) +#define bFM4_GPIO_PDORA_P2 *((volatile uint8_t *)(0x42DE8508UL)) +#define bFM_GPIO_PDORA_P3 *((volatile uint8_t *)(0x42DE850CUL)) +#define bFM4_GPIO_PDORA_P3 *((volatile uint8_t *)(0x42DE850CUL)) +#define bFM_GPIO_PDORA_P4 *((volatile uint8_t *)(0x42DE8510UL)) +#define bFM4_GPIO_PDORA_P4 *((volatile uint8_t *)(0x42DE8510UL)) +#define bFM_GPIO_PDORA_P5 *((volatile uint8_t *)(0x42DE8514UL)) +#define bFM4_GPIO_PDORA_P5 *((volatile uint8_t *)(0x42DE8514UL)) +#define bFM_GPIO_PDORA_P6 *((volatile uint8_t *)(0x42DE8518UL)) +#define bFM4_GPIO_PDORA_P6 *((volatile uint8_t *)(0x42DE8518UL)) +#define bFM_GPIO_PDORA_P7 *((volatile uint8_t *)(0x42DE851CUL)) +#define bFM4_GPIO_PDORA_P7 *((volatile uint8_t *)(0x42DE851CUL)) +#define bFM_GPIO_PDORA_P8 *((volatile uint8_t *)(0x42DE8520UL)) +#define bFM4_GPIO_PDORA_P8 *((volatile uint8_t *)(0x42DE8520UL)) +#define bFM_GPIO_PDORA_P9 *((volatile uint8_t *)(0x42DE8524UL)) +#define bFM4_GPIO_PDORA_P9 *((volatile uint8_t *)(0x42DE8524UL)) +#define bFM_GPIO_PDORA_PA *((volatile uint8_t *)(0x42DE8528UL)) +#define bFM4_GPIO_PDORA_PA *((volatile uint8_t *)(0x42DE8528UL)) +#define bFM_GPIO_PDORA_PB *((volatile uint8_t *)(0x42DE852CUL)) +#define bFM4_GPIO_PDORA_PB *((volatile uint8_t *)(0x42DE852CUL)) +#define bFM_GPIO_PDORA_PC *((volatile uint8_t *)(0x42DE8530UL)) +#define bFM4_GPIO_PDORA_PC *((volatile uint8_t *)(0x42DE8530UL)) +#define bFM_GPIO_PDORA_PD *((volatile uint8_t *)(0x42DE8534UL)) +#define bFM4_GPIO_PDORA_PD *((volatile uint8_t *)(0x42DE8534UL)) +#define bFM_GPIO_PDORA_PE *((volatile uint8_t *)(0x42DE8538UL)) +#define bFM4_GPIO_PDORA_PE *((volatile uint8_t *)(0x42DE8538UL)) +#define bFM_GPIO_PDORA_PF *((volatile uint8_t *)(0x42DE853CUL)) +#define bFM4_GPIO_PDORA_PF *((volatile uint8_t *)(0x42DE853CUL)) + +#define bFM_GPIO_PDORC_P0 *((volatile uint8_t *)(0x42DE8600UL)) +#define bFM4_GPIO_PDORC_P0 *((volatile uint8_t *)(0x42DE8600UL)) +#define bFM_GPIO_PDORC_P1 *((volatile uint8_t *)(0x42DE8604UL)) +#define bFM4_GPIO_PDORC_P1 *((volatile uint8_t *)(0x42DE8604UL)) +#define bFM_GPIO_PDORC_P2 *((volatile uint8_t *)(0x42DE8608UL)) +#define bFM4_GPIO_PDORC_P2 *((volatile uint8_t *)(0x42DE8608UL)) +#define bFM_GPIO_PDORC_P3 *((volatile uint8_t *)(0x42DE860CUL)) +#define bFM4_GPIO_PDORC_P3 *((volatile uint8_t *)(0x42DE860CUL)) +#define bFM_GPIO_PDORC_P4 *((volatile uint8_t *)(0x42DE8610UL)) +#define bFM4_GPIO_PDORC_P4 *((volatile uint8_t *)(0x42DE8610UL)) +#define bFM_GPIO_PDORC_P5 *((volatile uint8_t *)(0x42DE8614UL)) +#define bFM4_GPIO_PDORC_P5 *((volatile uint8_t *)(0x42DE8614UL)) +#define bFM_GPIO_PDORC_P6 *((volatile uint8_t *)(0x42DE8618UL)) +#define bFM4_GPIO_PDORC_P6 *((volatile uint8_t *)(0x42DE8618UL)) +#define bFM_GPIO_PDORC_P7 *((volatile uint8_t *)(0x42DE861CUL)) +#define bFM4_GPIO_PDORC_P7 *((volatile uint8_t *)(0x42DE861CUL)) +#define bFM_GPIO_PDORC_P8 *((volatile uint8_t *)(0x42DE8620UL)) +#define bFM4_GPIO_PDORC_P8 *((volatile uint8_t *)(0x42DE8620UL)) +#define bFM_GPIO_PDORC_P9 *((volatile uint8_t *)(0x42DE8624UL)) +#define bFM4_GPIO_PDORC_P9 *((volatile uint8_t *)(0x42DE8624UL)) +#define bFM_GPIO_PDORC_PA *((volatile uint8_t *)(0x42DE8628UL)) +#define bFM4_GPIO_PDORC_PA *((volatile uint8_t *)(0x42DE8628UL)) +#define bFM_GPIO_PDORC_PB *((volatile uint8_t *)(0x42DE862CUL)) +#define bFM4_GPIO_PDORC_PB *((volatile uint8_t *)(0x42DE862CUL)) +#define bFM_GPIO_PDORC_PC *((volatile uint8_t *)(0x42DE8630UL)) +#define bFM4_GPIO_PDORC_PC *((volatile uint8_t *)(0x42DE8630UL)) +#define bFM_GPIO_PDORC_PD *((volatile uint8_t *)(0x42DE8634UL)) +#define bFM4_GPIO_PDORC_PD *((volatile uint8_t *)(0x42DE8634UL)) +#define bFM_GPIO_PDORC_PE *((volatile uint8_t *)(0x42DE8638UL)) +#define bFM4_GPIO_PDORC_PE *((volatile uint8_t *)(0x42DE8638UL)) +#define bFM_GPIO_PDORC_PF *((volatile uint8_t *)(0x42DE863CUL)) +#define bFM4_GPIO_PDORC_PF *((volatile uint8_t *)(0x42DE863CUL)) + +#define bFM_GPIO_PDORD_P0 *((volatile uint8_t *)(0x42DE8680UL)) +#define bFM4_GPIO_PDORD_P0 *((volatile uint8_t *)(0x42DE8680UL)) +#define bFM_GPIO_PDORD_P1 *((volatile uint8_t *)(0x42DE8684UL)) +#define bFM4_GPIO_PDORD_P1 *((volatile uint8_t *)(0x42DE8684UL)) +#define bFM_GPIO_PDORD_P2 *((volatile uint8_t *)(0x42DE8688UL)) +#define bFM4_GPIO_PDORD_P2 *((volatile uint8_t *)(0x42DE8688UL)) + +#define bFM_GPIO_PDORE_P0 *((volatile uint8_t *)(0x42DE8700UL)) +#define bFM4_GPIO_PDORE_P0 *((volatile uint8_t *)(0x42DE8700UL)) +#define bFM_GPIO_PDORE_P2 *((volatile uint8_t *)(0x42DE8708UL)) +#define bFM4_GPIO_PDORE_P2 *((volatile uint8_t *)(0x42DE8708UL)) +#define bFM_GPIO_PDORE_P3 *((volatile uint8_t *)(0x42DE870CUL)) +#define bFM4_GPIO_PDORE_P3 *((volatile uint8_t *)(0x42DE870CUL)) + +#define bFM_GPIO_PDSR0_P0 *((volatile uint8_t *)(0x42DEE800UL)) +#define bFM4_GPIO_PDSR0_P0 *((volatile uint8_t *)(0x42DEE800UL)) +#define bFM_GPIO_PDSR0_P1 *((volatile uint8_t *)(0x42DEE804UL)) +#define bFM4_GPIO_PDSR0_P1 *((volatile uint8_t *)(0x42DEE804UL)) +#define bFM_GPIO_PDSR0_P2 *((volatile uint8_t *)(0x42DEE808UL)) +#define bFM4_GPIO_PDSR0_P2 *((volatile uint8_t *)(0x42DEE808UL)) +#define bFM_GPIO_PDSR0_P3 *((volatile uint8_t *)(0x42DEE80CUL)) +#define bFM4_GPIO_PDSR0_P3 *((volatile uint8_t *)(0x42DEE80CUL)) +#define bFM_GPIO_PDSR0_P4 *((volatile uint8_t *)(0x42DEE810UL)) +#define bFM4_GPIO_PDSR0_P4 *((volatile uint8_t *)(0x42DEE810UL)) +#define bFM_GPIO_PDSR0_P8 *((volatile uint8_t *)(0x42DEE820UL)) +#define bFM4_GPIO_PDSR0_P8 *((volatile uint8_t *)(0x42DEE820UL)) +#define bFM_GPIO_PDSR0_P9 *((volatile uint8_t *)(0x42DEE824UL)) +#define bFM4_GPIO_PDSR0_P9 *((volatile uint8_t *)(0x42DEE824UL)) +#define bFM_GPIO_PDSR0_PA *((volatile uint8_t *)(0x42DEE828UL)) +#define bFM4_GPIO_PDSR0_PA *((volatile uint8_t *)(0x42DEE828UL)) + +#define bFM_GPIO_PDSR1_P0 *((volatile uint8_t *)(0x42DEE880UL)) +#define bFM4_GPIO_PDSR1_P0 *((volatile uint8_t *)(0x42DEE880UL)) +#define bFM_GPIO_PDSR1_P1 *((volatile uint8_t *)(0x42DEE884UL)) +#define bFM4_GPIO_PDSR1_P1 *((volatile uint8_t *)(0x42DEE884UL)) +#define bFM_GPIO_PDSR1_P2 *((volatile uint8_t *)(0x42DEE888UL)) +#define bFM4_GPIO_PDSR1_P2 *((volatile uint8_t *)(0x42DEE888UL)) +#define bFM_GPIO_PDSR1_P3 *((volatile uint8_t *)(0x42DEE88CUL)) +#define bFM4_GPIO_PDSR1_P3 *((volatile uint8_t *)(0x42DEE88CUL)) +#define bFM_GPIO_PDSR1_P4 *((volatile uint8_t *)(0x42DEE890UL)) +#define bFM4_GPIO_PDSR1_P4 *((volatile uint8_t *)(0x42DEE890UL)) +#define bFM_GPIO_PDSR1_P5 *((volatile uint8_t *)(0x42DEE894UL)) +#define bFM4_GPIO_PDSR1_P5 *((volatile uint8_t *)(0x42DEE894UL)) +#define bFM_GPIO_PDSR1_P6 *((volatile uint8_t *)(0x42DEE898UL)) +#define bFM4_GPIO_PDSR1_P6 *((volatile uint8_t *)(0x42DEE898UL)) +#define bFM_GPIO_PDSR1_P7 *((volatile uint8_t *)(0x42DEE89CUL)) +#define bFM4_GPIO_PDSR1_P7 *((volatile uint8_t *)(0x42DEE89CUL)) +#define bFM_GPIO_PDSR1_P8 *((volatile uint8_t *)(0x42DEE8A0UL)) +#define bFM4_GPIO_PDSR1_P8 *((volatile uint8_t *)(0x42DEE8A0UL)) +#define bFM_GPIO_PDSR1_P9 *((volatile uint8_t *)(0x42DEE8A4UL)) +#define bFM4_GPIO_PDSR1_P9 *((volatile uint8_t *)(0x42DEE8A4UL)) +#define bFM_GPIO_PDSR1_PA *((volatile uint8_t *)(0x42DEE8A8UL)) +#define bFM4_GPIO_PDSR1_PA *((volatile uint8_t *)(0x42DEE8A8UL)) +#define bFM_GPIO_PDSR1_PB *((volatile uint8_t *)(0x42DEE8ACUL)) +#define bFM4_GPIO_PDSR1_PB *((volatile uint8_t *)(0x42DEE8ACUL)) +#define bFM_GPIO_PDSR1_PC *((volatile uint8_t *)(0x42DEE8B0UL)) +#define bFM4_GPIO_PDSR1_PC *((volatile uint8_t *)(0x42DEE8B0UL)) +#define bFM_GPIO_PDSR1_PD *((volatile uint8_t *)(0x42DEE8B4UL)) +#define bFM4_GPIO_PDSR1_PD *((volatile uint8_t *)(0x42DEE8B4UL)) +#define bFM_GPIO_PDSR1_PE *((volatile uint8_t *)(0x42DEE8B8UL)) +#define bFM4_GPIO_PDSR1_PE *((volatile uint8_t *)(0x42DEE8B8UL)) +#define bFM_GPIO_PDSR1_PF *((volatile uint8_t *)(0x42DEE8BCUL)) +#define bFM4_GPIO_PDSR1_PF *((volatile uint8_t *)(0x42DEE8BCUL)) + +#define bFM_GPIO_PDSR2_P0 *((volatile uint8_t *)(0x42DEE900UL)) +#define bFM4_GPIO_PDSR2_P0 *((volatile uint8_t *)(0x42DEE900UL)) +#define bFM_GPIO_PDSR2_P1 *((volatile uint8_t *)(0x42DEE904UL)) +#define bFM4_GPIO_PDSR2_P1 *((volatile uint8_t *)(0x42DEE904UL)) +#define bFM_GPIO_PDSR2_P2 *((volatile uint8_t *)(0x42DEE908UL)) +#define bFM4_GPIO_PDSR2_P2 *((volatile uint8_t *)(0x42DEE908UL)) +#define bFM_GPIO_PDSR2_P3 *((volatile uint8_t *)(0x42DEE90CUL)) +#define bFM4_GPIO_PDSR2_P3 *((volatile uint8_t *)(0x42DEE90CUL)) +#define bFM_GPIO_PDSR2_P4 *((volatile uint8_t *)(0x42DEE910UL)) +#define bFM4_GPIO_PDSR2_P4 *((volatile uint8_t *)(0x42DEE910UL)) +#define bFM_GPIO_PDSR2_P5 *((volatile uint8_t *)(0x42DEE914UL)) +#define bFM4_GPIO_PDSR2_P5 *((volatile uint8_t *)(0x42DEE914UL)) +#define bFM_GPIO_PDSR2_P6 *((volatile uint8_t *)(0x42DEE918UL)) +#define bFM4_GPIO_PDSR2_P6 *((volatile uint8_t *)(0x42DEE918UL)) +#define bFM_GPIO_PDSR2_P7 *((volatile uint8_t *)(0x42DEE91CUL)) +#define bFM4_GPIO_PDSR2_P7 *((volatile uint8_t *)(0x42DEE91CUL)) +#define bFM_GPIO_PDSR2_P8 *((volatile uint8_t *)(0x42DEE920UL)) +#define bFM4_GPIO_PDSR2_P8 *((volatile uint8_t *)(0x42DEE920UL)) +#define bFM_GPIO_PDSR2_P9 *((volatile uint8_t *)(0x42DEE924UL)) +#define bFM4_GPIO_PDSR2_P9 *((volatile uint8_t *)(0x42DEE924UL)) +#define bFM_GPIO_PDSR2_PA *((volatile uint8_t *)(0x42DEE928UL)) +#define bFM4_GPIO_PDSR2_PA *((volatile uint8_t *)(0x42DEE928UL)) + +#define bFM_GPIO_PDSR3_P2 *((volatile uint8_t *)(0x42DEE988UL)) +#define bFM4_GPIO_PDSR3_P2 *((volatile uint8_t *)(0x42DEE988UL)) +#define bFM_GPIO_PDSR3_P3 *((volatile uint8_t *)(0x42DEE98CUL)) +#define bFM4_GPIO_PDSR3_P3 *((volatile uint8_t *)(0x42DEE98CUL)) +#define bFM_GPIO_PDSR3_P4 *((volatile uint8_t *)(0x42DEE990UL)) +#define bFM4_GPIO_PDSR3_P4 *((volatile uint8_t *)(0x42DEE990UL)) +#define bFM_GPIO_PDSR3_P5 *((volatile uint8_t *)(0x42DEE994UL)) +#define bFM4_GPIO_PDSR3_P5 *((volatile uint8_t *)(0x42DEE994UL)) +#define bFM_GPIO_PDSR3_P6 *((volatile uint8_t *)(0x42DEE998UL)) +#define bFM4_GPIO_PDSR3_P6 *((volatile uint8_t *)(0x42DEE998UL)) +#define bFM_GPIO_PDSR3_P7 *((volatile uint8_t *)(0x42DEE99CUL)) +#define bFM4_GPIO_PDSR3_P7 *((volatile uint8_t *)(0x42DEE99CUL)) +#define bFM_GPIO_PDSR3_P8 *((volatile uint8_t *)(0x42DEE9A0UL)) +#define bFM4_GPIO_PDSR3_P8 *((volatile uint8_t *)(0x42DEE9A0UL)) +#define bFM_GPIO_PDSR3_P9 *((volatile uint8_t *)(0x42DEE9A4UL)) +#define bFM4_GPIO_PDSR3_P9 *((volatile uint8_t *)(0x42DEE9A4UL)) +#define bFM_GPIO_PDSR3_PA *((volatile uint8_t *)(0x42DEE9A8UL)) +#define bFM4_GPIO_PDSR3_PA *((volatile uint8_t *)(0x42DEE9A8UL)) +#define bFM_GPIO_PDSR3_PB *((volatile uint8_t *)(0x42DEE9ACUL)) +#define bFM4_GPIO_PDSR3_PB *((volatile uint8_t *)(0x42DEE9ACUL)) +#define bFM_GPIO_PDSR3_PC *((volatile uint8_t *)(0x42DEE9B0UL)) +#define bFM4_GPIO_PDSR3_PC *((volatile uint8_t *)(0x42DEE9B0UL)) +#define bFM_GPIO_PDSR3_PD *((volatile uint8_t *)(0x42DEE9B4UL)) +#define bFM4_GPIO_PDSR3_PD *((volatile uint8_t *)(0x42DEE9B4UL)) +#define bFM_GPIO_PDSR3_PE *((volatile uint8_t *)(0x42DEE9B8UL)) +#define bFM4_GPIO_PDSR3_PE *((volatile uint8_t *)(0x42DEE9B8UL)) + +#define bFM_GPIO_PDSR4_P0 *((volatile uint8_t *)(0x42DEEA00UL)) +#define bFM4_GPIO_PDSR4_P0 *((volatile uint8_t *)(0x42DEEA00UL)) +#define bFM_GPIO_PDSR4_P1 *((volatile uint8_t *)(0x42DEEA04UL)) +#define bFM4_GPIO_PDSR4_P1 *((volatile uint8_t *)(0x42DEEA04UL)) +#define bFM_GPIO_PDSR4_P2 *((volatile uint8_t *)(0x42DEEA08UL)) +#define bFM4_GPIO_PDSR4_P2 *((volatile uint8_t *)(0x42DEEA08UL)) +#define bFM_GPIO_PDSR4_P3 *((volatile uint8_t *)(0x42DEEA0CUL)) +#define bFM4_GPIO_PDSR4_P3 *((volatile uint8_t *)(0x42DEEA0CUL)) +#define bFM_GPIO_PDSR4_P4 *((volatile uint8_t *)(0x42DEEA10UL)) +#define bFM4_GPIO_PDSR4_P4 *((volatile uint8_t *)(0x42DEEA10UL)) +#define bFM_GPIO_PDSR4_P5 *((volatile uint8_t *)(0x42DEEA14UL)) +#define bFM4_GPIO_PDSR4_P5 *((volatile uint8_t *)(0x42DEEA14UL)) +#define bFM_GPIO_PDSR4_P6 *((volatile uint8_t *)(0x42DEEA18UL)) +#define bFM4_GPIO_PDSR4_P6 *((volatile uint8_t *)(0x42DEEA18UL)) +#define bFM_GPIO_PDSR4_P7 *((volatile uint8_t *)(0x42DEEA1CUL)) +#define bFM4_GPIO_PDSR4_P7 *((volatile uint8_t *)(0x42DEEA1CUL)) +#define bFM_GPIO_PDSR4_P8 *((volatile uint8_t *)(0x42DEEA20UL)) +#define bFM4_GPIO_PDSR4_P8 *((volatile uint8_t *)(0x42DEEA20UL)) +#define bFM_GPIO_PDSR4_P9 *((volatile uint8_t *)(0x42DEEA24UL)) +#define bFM4_GPIO_PDSR4_P9 *((volatile uint8_t *)(0x42DEEA24UL)) + +#define bFM_GPIO_PDSR6_P0 *((volatile uint8_t *)(0x42DEEB00UL)) +#define bFM4_GPIO_PDSR6_P0 *((volatile uint8_t *)(0x42DEEB00UL)) +#define bFM_GPIO_PDSR6_P1 *((volatile uint8_t *)(0x42DEEB04UL)) +#define bFM4_GPIO_PDSR6_P1 *((volatile uint8_t *)(0x42DEEB04UL)) +#define bFM_GPIO_PDSR6_P2 *((volatile uint8_t *)(0x42DEEB08UL)) +#define bFM4_GPIO_PDSR6_P2 *((volatile uint8_t *)(0x42DEEB08UL)) +#define bFM_GPIO_PDSR6_P3 *((volatile uint8_t *)(0x42DEEB0CUL)) +#define bFM4_GPIO_PDSR6_P3 *((volatile uint8_t *)(0x42DEEB0CUL)) +#define bFM_GPIO_PDSR6_PE *((volatile uint8_t *)(0x42DEEB38UL)) +#define bFM4_GPIO_PDSR6_PE *((volatile uint8_t *)(0x42DEEB38UL)) + +#define bFM_GPIO_PDSR7_P0 *((volatile uint8_t *)(0x42DEEB80UL)) +#define bFM4_GPIO_PDSR7_P0 *((volatile uint8_t *)(0x42DEEB80UL)) +#define bFM_GPIO_PDSR7_P1 *((volatile uint8_t *)(0x42DEEB84UL)) +#define bFM4_GPIO_PDSR7_P1 *((volatile uint8_t *)(0x42DEEB84UL)) +#define bFM_GPIO_PDSR7_P2 *((volatile uint8_t *)(0x42DEEB88UL)) +#define bFM4_GPIO_PDSR7_P2 *((volatile uint8_t *)(0x42DEEB88UL)) +#define bFM_GPIO_PDSR7_P3 *((volatile uint8_t *)(0x42DEEB8CUL)) +#define bFM4_GPIO_PDSR7_P3 *((volatile uint8_t *)(0x42DEEB8CUL)) +#define bFM_GPIO_PDSR7_P4 *((volatile uint8_t *)(0x42DEEB90UL)) +#define bFM4_GPIO_PDSR7_P4 *((volatile uint8_t *)(0x42DEEB90UL)) +#define bFM_GPIO_PDSR7_P5 *((volatile uint8_t *)(0x42DEEB94UL)) +#define bFM4_GPIO_PDSR7_P5 *((volatile uint8_t *)(0x42DEEB94UL)) +#define bFM_GPIO_PDSR7_P6 *((volatile uint8_t *)(0x42DEEB98UL)) +#define bFM4_GPIO_PDSR7_P6 *((volatile uint8_t *)(0x42DEEB98UL)) +#define bFM_GPIO_PDSR7_P7 *((volatile uint8_t *)(0x42DEEB9CUL)) +#define bFM4_GPIO_PDSR7_P7 *((volatile uint8_t *)(0x42DEEB9CUL)) +#define bFM_GPIO_PDSR7_P8 *((volatile uint8_t *)(0x42DEEBA0UL)) +#define bFM4_GPIO_PDSR7_P8 *((volatile uint8_t *)(0x42DEEBA0UL)) +#define bFM_GPIO_PDSR7_P9 *((volatile uint8_t *)(0x42DEEBA4UL)) +#define bFM4_GPIO_PDSR7_P9 *((volatile uint8_t *)(0x42DEEBA4UL)) +#define bFM_GPIO_PDSR7_PA *((volatile uint8_t *)(0x42DEEBA8UL)) +#define bFM4_GPIO_PDSR7_PA *((volatile uint8_t *)(0x42DEEBA8UL)) +#define bFM_GPIO_PDSR7_PB *((volatile uint8_t *)(0x42DEEBACUL)) +#define bFM4_GPIO_PDSR7_PB *((volatile uint8_t *)(0x42DEEBACUL)) +#define bFM_GPIO_PDSR7_PC *((volatile uint8_t *)(0x42DEEBB0UL)) +#define bFM4_GPIO_PDSR7_PC *((volatile uint8_t *)(0x42DEEBB0UL)) +#define bFM_GPIO_PDSR7_PD *((volatile uint8_t *)(0x42DEEBB4UL)) +#define bFM4_GPIO_PDSR7_PD *((volatile uint8_t *)(0x42DEEBB4UL)) +#define bFM_GPIO_PDSR7_PE *((volatile uint8_t *)(0x42DEEBB8UL)) +#define bFM4_GPIO_PDSR7_PE *((volatile uint8_t *)(0x42DEEBB8UL)) + +#define bFM_GPIO_PDSR8_P0 *((volatile uint8_t *)(0x42DEEC00UL)) +#define bFM4_GPIO_PDSR8_P0 *((volatile uint8_t *)(0x42DEEC00UL)) +#define bFM_GPIO_PDSR8_P1 *((volatile uint8_t *)(0x42DEEC04UL)) +#define bFM4_GPIO_PDSR8_P1 *((volatile uint8_t *)(0x42DEEC04UL)) +#define bFM_GPIO_PDSR8_P2 *((volatile uint8_t *)(0x42DEEC08UL)) +#define bFM4_GPIO_PDSR8_P2 *((volatile uint8_t *)(0x42DEEC08UL)) +#define bFM_GPIO_PDSR8_P3 *((volatile uint8_t *)(0x42DEEC0CUL)) +#define bFM4_GPIO_PDSR8_P3 *((volatile uint8_t *)(0x42DEEC0CUL)) + +#define bFM_GPIO_PDSRA_P0 *((volatile uint8_t *)(0x42DEED00UL)) +#define bFM4_GPIO_PDSRA_P0 *((volatile uint8_t *)(0x42DEED00UL)) +#define bFM_GPIO_PDSRA_P1 *((volatile uint8_t *)(0x42DEED04UL)) +#define bFM4_GPIO_PDSRA_P1 *((volatile uint8_t *)(0x42DEED04UL)) +#define bFM_GPIO_PDSRA_P2 *((volatile uint8_t *)(0x42DEED08UL)) +#define bFM4_GPIO_PDSRA_P2 *((volatile uint8_t *)(0x42DEED08UL)) +#define bFM_GPIO_PDSRA_P3 *((volatile uint8_t *)(0x42DEED0CUL)) +#define bFM4_GPIO_PDSRA_P3 *((volatile uint8_t *)(0x42DEED0CUL)) +#define bFM_GPIO_PDSRA_P4 *((volatile uint8_t *)(0x42DEED10UL)) +#define bFM4_GPIO_PDSRA_P4 *((volatile uint8_t *)(0x42DEED10UL)) +#define bFM_GPIO_PDSRA_P5 *((volatile uint8_t *)(0x42DEED14UL)) +#define bFM4_GPIO_PDSRA_P5 *((volatile uint8_t *)(0x42DEED14UL)) +#define bFM_GPIO_PDSRA_P6 *((volatile uint8_t *)(0x42DEED18UL)) +#define bFM4_GPIO_PDSRA_P6 *((volatile uint8_t *)(0x42DEED18UL)) +#define bFM_GPIO_PDSRA_P7 *((volatile uint8_t *)(0x42DEED1CUL)) +#define bFM4_GPIO_PDSRA_P7 *((volatile uint8_t *)(0x42DEED1CUL)) +#define bFM_GPIO_PDSRA_P8 *((volatile uint8_t *)(0x42DEED20UL)) +#define bFM4_GPIO_PDSRA_P8 *((volatile uint8_t *)(0x42DEED20UL)) +#define bFM_GPIO_PDSRA_P9 *((volatile uint8_t *)(0x42DEED24UL)) +#define bFM4_GPIO_PDSRA_P9 *((volatile uint8_t *)(0x42DEED24UL)) +#define bFM_GPIO_PDSRA_PA *((volatile uint8_t *)(0x42DEED28UL)) +#define bFM4_GPIO_PDSRA_PA *((volatile uint8_t *)(0x42DEED28UL)) +#define bFM_GPIO_PDSRA_PB *((volatile uint8_t *)(0x42DEED2CUL)) +#define bFM4_GPIO_PDSRA_PB *((volatile uint8_t *)(0x42DEED2CUL)) +#define bFM_GPIO_PDSRA_PC *((volatile uint8_t *)(0x42DEED30UL)) +#define bFM4_GPIO_PDSRA_PC *((volatile uint8_t *)(0x42DEED30UL)) +#define bFM_GPIO_PDSRA_PD *((volatile uint8_t *)(0x42DEED34UL)) +#define bFM4_GPIO_PDSRA_PD *((volatile uint8_t *)(0x42DEED34UL)) +#define bFM_GPIO_PDSRA_PE *((volatile uint8_t *)(0x42DEED38UL)) +#define bFM4_GPIO_PDSRA_PE *((volatile uint8_t *)(0x42DEED38UL)) +#define bFM_GPIO_PDSRA_PF *((volatile uint8_t *)(0x42DEED3CUL)) +#define bFM4_GPIO_PDSRA_PF *((volatile uint8_t *)(0x42DEED3CUL)) + +#define bFM_GPIO_PDSRC_P0 *((volatile uint8_t *)(0x42DEEE00UL)) +#define bFM4_GPIO_PDSRC_P0 *((volatile uint8_t *)(0x42DEEE00UL)) +#define bFM_GPIO_PDSRC_P1 *((volatile uint8_t *)(0x42DEEE04UL)) +#define bFM4_GPIO_PDSRC_P1 *((volatile uint8_t *)(0x42DEEE04UL)) +#define bFM_GPIO_PDSRC_P2 *((volatile uint8_t *)(0x42DEEE08UL)) +#define bFM4_GPIO_PDSRC_P2 *((volatile uint8_t *)(0x42DEEE08UL)) +#define bFM_GPIO_PDSRC_P3 *((volatile uint8_t *)(0x42DEEE0CUL)) +#define bFM4_GPIO_PDSRC_P3 *((volatile uint8_t *)(0x42DEEE0CUL)) +#define bFM_GPIO_PDSRC_P4 *((volatile uint8_t *)(0x42DEEE10UL)) +#define bFM4_GPIO_PDSRC_P4 *((volatile uint8_t *)(0x42DEEE10UL)) +#define bFM_GPIO_PDSRC_P5 *((volatile uint8_t *)(0x42DEEE14UL)) +#define bFM4_GPIO_PDSRC_P5 *((volatile uint8_t *)(0x42DEEE14UL)) +#define bFM_GPIO_PDSRC_P6 *((volatile uint8_t *)(0x42DEEE18UL)) +#define bFM4_GPIO_PDSRC_P6 *((volatile uint8_t *)(0x42DEEE18UL)) +#define bFM_GPIO_PDSRC_P7 *((volatile uint8_t *)(0x42DEEE1CUL)) +#define bFM4_GPIO_PDSRC_P7 *((volatile uint8_t *)(0x42DEEE1CUL)) +#define bFM_GPIO_PDSRC_P8 *((volatile uint8_t *)(0x42DEEE20UL)) +#define bFM4_GPIO_PDSRC_P8 *((volatile uint8_t *)(0x42DEEE20UL)) +#define bFM_GPIO_PDSRC_P9 *((volatile uint8_t *)(0x42DEEE24UL)) +#define bFM4_GPIO_PDSRC_P9 *((volatile uint8_t *)(0x42DEEE24UL)) +#define bFM_GPIO_PDSRC_PA *((volatile uint8_t *)(0x42DEEE28UL)) +#define bFM4_GPIO_PDSRC_PA *((volatile uint8_t *)(0x42DEEE28UL)) +#define bFM_GPIO_PDSRC_PB *((volatile uint8_t *)(0x42DEEE2CUL)) +#define bFM4_GPIO_PDSRC_PB *((volatile uint8_t *)(0x42DEEE2CUL)) +#define bFM_GPIO_PDSRC_PC *((volatile uint8_t *)(0x42DEEE30UL)) +#define bFM4_GPIO_PDSRC_PC *((volatile uint8_t *)(0x42DEEE30UL)) +#define bFM_GPIO_PDSRC_PD *((volatile uint8_t *)(0x42DEEE34UL)) +#define bFM4_GPIO_PDSRC_PD *((volatile uint8_t *)(0x42DEEE34UL)) +#define bFM_GPIO_PDSRC_PE *((volatile uint8_t *)(0x42DEEE38UL)) +#define bFM4_GPIO_PDSRC_PE *((volatile uint8_t *)(0x42DEEE38UL)) +#define bFM_GPIO_PDSRC_PF *((volatile uint8_t *)(0x42DEEE3CUL)) +#define bFM4_GPIO_PDSRC_PF *((volatile uint8_t *)(0x42DEEE3CUL)) + +#define bFM_GPIO_PDSRD_P0 *((volatile uint8_t *)(0x42DEEE80UL)) +#define bFM4_GPIO_PDSRD_P0 *((volatile uint8_t *)(0x42DEEE80UL)) +#define bFM_GPIO_PDSRD_P1 *((volatile uint8_t *)(0x42DEEE84UL)) +#define bFM4_GPIO_PDSRD_P1 *((volatile uint8_t *)(0x42DEEE84UL)) +#define bFM_GPIO_PDSRD_P2 *((volatile uint8_t *)(0x42DEEE88UL)) +#define bFM4_GPIO_PDSRD_P2 *((volatile uint8_t *)(0x42DEEE88UL)) + +#define bFM_GPIO_PDSRE_P0 *((volatile uint8_t *)(0x42DEEF00UL)) +#define bFM4_GPIO_PDSRE_P0 *((volatile uint8_t *)(0x42DEEF00UL)) +#define bFM_GPIO_PDSRE_P2 *((volatile uint8_t *)(0x42DEEF08UL)) +#define bFM4_GPIO_PDSRE_P2 *((volatile uint8_t *)(0x42DEEF08UL)) +#define bFM_GPIO_PDSRE_P3 *((volatile uint8_t *)(0x42DEEF0CUL)) +#define bFM4_GPIO_PDSRE_P3 *((volatile uint8_t *)(0x42DEEF0CUL)) + +#define bFM_GPIO_PFR0_P0 *((volatile uint8_t *)(0x42DE0000UL)) +#define bFM4_GPIO_PFR0_P0 *((volatile uint8_t *)(0x42DE0000UL)) +#define bFM_GPIO_PFR0_P1 *((volatile uint8_t *)(0x42DE0004UL)) +#define bFM4_GPIO_PFR0_P1 *((volatile uint8_t *)(0x42DE0004UL)) +#define bFM_GPIO_PFR0_P2 *((volatile uint8_t *)(0x42DE0008UL)) +#define bFM4_GPIO_PFR0_P2 *((volatile uint8_t *)(0x42DE0008UL)) +#define bFM_GPIO_PFR0_P3 *((volatile uint8_t *)(0x42DE000CUL)) +#define bFM4_GPIO_PFR0_P3 *((volatile uint8_t *)(0x42DE000CUL)) +#define bFM_GPIO_PFR0_P4 *((volatile uint8_t *)(0x42DE0010UL)) +#define bFM4_GPIO_PFR0_P4 *((volatile uint8_t *)(0x42DE0010UL)) +#define bFM_GPIO_PFR0_P8 *((volatile uint8_t *)(0x42DE0020UL)) +#define bFM4_GPIO_PFR0_P8 *((volatile uint8_t *)(0x42DE0020UL)) +#define bFM_GPIO_PFR0_P9 *((volatile uint8_t *)(0x42DE0024UL)) +#define bFM4_GPIO_PFR0_P9 *((volatile uint8_t *)(0x42DE0024UL)) +#define bFM_GPIO_PFR0_PA *((volatile uint8_t *)(0x42DE0028UL)) +#define bFM4_GPIO_PFR0_PA *((volatile uint8_t *)(0x42DE0028UL)) + +#define bFM_GPIO_PFR1_P0 *((volatile uint8_t *)(0x42DE0080UL)) +#define bFM4_GPIO_PFR1_P0 *((volatile uint8_t *)(0x42DE0080UL)) +#define bFM_GPIO_PFR1_P1 *((volatile uint8_t *)(0x42DE0084UL)) +#define bFM4_GPIO_PFR1_P1 *((volatile uint8_t *)(0x42DE0084UL)) +#define bFM_GPIO_PFR1_P2 *((volatile uint8_t *)(0x42DE0088UL)) +#define bFM4_GPIO_PFR1_P2 *((volatile uint8_t *)(0x42DE0088UL)) +#define bFM_GPIO_PFR1_P3 *((volatile uint8_t *)(0x42DE008CUL)) +#define bFM4_GPIO_PFR1_P3 *((volatile uint8_t *)(0x42DE008CUL)) +#define bFM_GPIO_PFR1_P4 *((volatile uint8_t *)(0x42DE0090UL)) +#define bFM4_GPIO_PFR1_P4 *((volatile uint8_t *)(0x42DE0090UL)) +#define bFM_GPIO_PFR1_P5 *((volatile uint8_t *)(0x42DE0094UL)) +#define bFM4_GPIO_PFR1_P5 *((volatile uint8_t *)(0x42DE0094UL)) +#define bFM_GPIO_PFR1_P6 *((volatile uint8_t *)(0x42DE0098UL)) +#define bFM4_GPIO_PFR1_P6 *((volatile uint8_t *)(0x42DE0098UL)) +#define bFM_GPIO_PFR1_P7 *((volatile uint8_t *)(0x42DE009CUL)) +#define bFM4_GPIO_PFR1_P7 *((volatile uint8_t *)(0x42DE009CUL)) +#define bFM_GPIO_PFR1_P8 *((volatile uint8_t *)(0x42DE00A0UL)) +#define bFM4_GPIO_PFR1_P8 *((volatile uint8_t *)(0x42DE00A0UL)) +#define bFM_GPIO_PFR1_P9 *((volatile uint8_t *)(0x42DE00A4UL)) +#define bFM4_GPIO_PFR1_P9 *((volatile uint8_t *)(0x42DE00A4UL)) +#define bFM_GPIO_PFR1_PA *((volatile uint8_t *)(0x42DE00A8UL)) +#define bFM4_GPIO_PFR1_PA *((volatile uint8_t *)(0x42DE00A8UL)) +#define bFM_GPIO_PFR1_PB *((volatile uint8_t *)(0x42DE00ACUL)) +#define bFM4_GPIO_PFR1_PB *((volatile uint8_t *)(0x42DE00ACUL)) +#define bFM_GPIO_PFR1_PC *((volatile uint8_t *)(0x42DE00B0UL)) +#define bFM4_GPIO_PFR1_PC *((volatile uint8_t *)(0x42DE00B0UL)) +#define bFM_GPIO_PFR1_PD *((volatile uint8_t *)(0x42DE00B4UL)) +#define bFM4_GPIO_PFR1_PD *((volatile uint8_t *)(0x42DE00B4UL)) +#define bFM_GPIO_PFR1_PE *((volatile uint8_t *)(0x42DE00B8UL)) +#define bFM4_GPIO_PFR1_PE *((volatile uint8_t *)(0x42DE00B8UL)) +#define bFM_GPIO_PFR1_PF *((volatile uint8_t *)(0x42DE00BCUL)) +#define bFM4_GPIO_PFR1_PF *((volatile uint8_t *)(0x42DE00BCUL)) + +#define bFM_GPIO_PFR2_P0 *((volatile uint8_t *)(0x42DE0100UL)) +#define bFM4_GPIO_PFR2_P0 *((volatile uint8_t *)(0x42DE0100UL)) +#define bFM_GPIO_PFR2_P1 *((volatile uint8_t *)(0x42DE0104UL)) +#define bFM4_GPIO_PFR2_P1 *((volatile uint8_t *)(0x42DE0104UL)) +#define bFM_GPIO_PFR2_P2 *((volatile uint8_t *)(0x42DE0108UL)) +#define bFM4_GPIO_PFR2_P2 *((volatile uint8_t *)(0x42DE0108UL)) +#define bFM_GPIO_PFR2_P3 *((volatile uint8_t *)(0x42DE010CUL)) +#define bFM4_GPIO_PFR2_P3 *((volatile uint8_t *)(0x42DE010CUL)) +#define bFM_GPIO_PFR2_P4 *((volatile uint8_t *)(0x42DE0110UL)) +#define bFM4_GPIO_PFR2_P4 *((volatile uint8_t *)(0x42DE0110UL)) +#define bFM_GPIO_PFR2_P5 *((volatile uint8_t *)(0x42DE0114UL)) +#define bFM4_GPIO_PFR2_P5 *((volatile uint8_t *)(0x42DE0114UL)) +#define bFM_GPIO_PFR2_P6 *((volatile uint8_t *)(0x42DE0118UL)) +#define bFM4_GPIO_PFR2_P6 *((volatile uint8_t *)(0x42DE0118UL)) +#define bFM_GPIO_PFR2_P7 *((volatile uint8_t *)(0x42DE011CUL)) +#define bFM4_GPIO_PFR2_P7 *((volatile uint8_t *)(0x42DE011CUL)) +#define bFM_GPIO_PFR2_P8 *((volatile uint8_t *)(0x42DE0120UL)) +#define bFM4_GPIO_PFR2_P8 *((volatile uint8_t *)(0x42DE0120UL)) +#define bFM_GPIO_PFR2_P9 *((volatile uint8_t *)(0x42DE0124UL)) +#define bFM4_GPIO_PFR2_P9 *((volatile uint8_t *)(0x42DE0124UL)) +#define bFM_GPIO_PFR2_PA *((volatile uint8_t *)(0x42DE0128UL)) +#define bFM4_GPIO_PFR2_PA *((volatile uint8_t *)(0x42DE0128UL)) + +#define bFM_GPIO_PFR3_P2 *((volatile uint8_t *)(0x42DE0188UL)) +#define bFM4_GPIO_PFR3_P2 *((volatile uint8_t *)(0x42DE0188UL)) +#define bFM_GPIO_PFR3_P3 *((volatile uint8_t *)(0x42DE018CUL)) +#define bFM4_GPIO_PFR3_P3 *((volatile uint8_t *)(0x42DE018CUL)) +#define bFM_GPIO_PFR3_P4 *((volatile uint8_t *)(0x42DE0190UL)) +#define bFM4_GPIO_PFR3_P4 *((volatile uint8_t *)(0x42DE0190UL)) +#define bFM_GPIO_PFR3_P5 *((volatile uint8_t *)(0x42DE0194UL)) +#define bFM4_GPIO_PFR3_P5 *((volatile uint8_t *)(0x42DE0194UL)) +#define bFM_GPIO_PFR3_P6 *((volatile uint8_t *)(0x42DE0198UL)) +#define bFM4_GPIO_PFR3_P6 *((volatile uint8_t *)(0x42DE0198UL)) +#define bFM_GPIO_PFR3_P7 *((volatile uint8_t *)(0x42DE019CUL)) +#define bFM4_GPIO_PFR3_P7 *((volatile uint8_t *)(0x42DE019CUL)) +#define bFM_GPIO_PFR3_P8 *((volatile uint8_t *)(0x42DE01A0UL)) +#define bFM4_GPIO_PFR3_P8 *((volatile uint8_t *)(0x42DE01A0UL)) +#define bFM_GPIO_PFR3_P9 *((volatile uint8_t *)(0x42DE01A4UL)) +#define bFM4_GPIO_PFR3_P9 *((volatile uint8_t *)(0x42DE01A4UL)) +#define bFM_GPIO_PFR3_PA *((volatile uint8_t *)(0x42DE01A8UL)) +#define bFM4_GPIO_PFR3_PA *((volatile uint8_t *)(0x42DE01A8UL)) +#define bFM_GPIO_PFR3_PB *((volatile uint8_t *)(0x42DE01ACUL)) +#define bFM4_GPIO_PFR3_PB *((volatile uint8_t *)(0x42DE01ACUL)) +#define bFM_GPIO_PFR3_PC *((volatile uint8_t *)(0x42DE01B0UL)) +#define bFM4_GPIO_PFR3_PC *((volatile uint8_t *)(0x42DE01B0UL)) +#define bFM_GPIO_PFR3_PD *((volatile uint8_t *)(0x42DE01B4UL)) +#define bFM4_GPIO_PFR3_PD *((volatile uint8_t *)(0x42DE01B4UL)) +#define bFM_GPIO_PFR3_PE *((volatile uint8_t *)(0x42DE01B8UL)) +#define bFM4_GPIO_PFR3_PE *((volatile uint8_t *)(0x42DE01B8UL)) + +#define bFM_GPIO_PFR4_P0 *((volatile uint8_t *)(0x42DE0200UL)) +#define bFM4_GPIO_PFR4_P0 *((volatile uint8_t *)(0x42DE0200UL)) +#define bFM_GPIO_PFR4_P1 *((volatile uint8_t *)(0x42DE0204UL)) +#define bFM4_GPIO_PFR4_P1 *((volatile uint8_t *)(0x42DE0204UL)) +#define bFM_GPIO_PFR4_P2 *((volatile uint8_t *)(0x42DE0208UL)) +#define bFM4_GPIO_PFR4_P2 *((volatile uint8_t *)(0x42DE0208UL)) +#define bFM_GPIO_PFR4_P3 *((volatile uint8_t *)(0x42DE020CUL)) +#define bFM4_GPIO_PFR4_P3 *((volatile uint8_t *)(0x42DE020CUL)) +#define bFM_GPIO_PFR4_P4 *((volatile uint8_t *)(0x42DE0210UL)) +#define bFM4_GPIO_PFR4_P4 *((volatile uint8_t *)(0x42DE0210UL)) +#define bFM_GPIO_PFR4_P5 *((volatile uint8_t *)(0x42DE0214UL)) +#define bFM4_GPIO_PFR4_P5 *((volatile uint8_t *)(0x42DE0214UL)) +#define bFM_GPIO_PFR4_P6 *((volatile uint8_t *)(0x42DE0218UL)) +#define bFM4_GPIO_PFR4_P6 *((volatile uint8_t *)(0x42DE0218UL)) +#define bFM_GPIO_PFR4_P7 *((volatile uint8_t *)(0x42DE021CUL)) +#define bFM4_GPIO_PFR4_P7 *((volatile uint8_t *)(0x42DE021CUL)) +#define bFM_GPIO_PFR4_P8 *((volatile uint8_t *)(0x42DE0220UL)) +#define bFM4_GPIO_PFR4_P8 *((volatile uint8_t *)(0x42DE0220UL)) +#define bFM_GPIO_PFR4_P9 *((volatile uint8_t *)(0x42DE0224UL)) +#define bFM4_GPIO_PFR4_P9 *((volatile uint8_t *)(0x42DE0224UL)) + +#define bFM_GPIO_PFR6_P0 *((volatile uint8_t *)(0x42DE0300UL)) +#define bFM4_GPIO_PFR6_P0 *((volatile uint8_t *)(0x42DE0300UL)) +#define bFM_GPIO_PFR6_P1 *((volatile uint8_t *)(0x42DE0304UL)) +#define bFM4_GPIO_PFR6_P1 *((volatile uint8_t *)(0x42DE0304UL)) +#define bFM_GPIO_PFR6_P2 *((volatile uint8_t *)(0x42DE0308UL)) +#define bFM4_GPIO_PFR6_P2 *((volatile uint8_t *)(0x42DE0308UL)) +#define bFM_GPIO_PFR6_P3 *((volatile uint8_t *)(0x42DE030CUL)) +#define bFM4_GPIO_PFR6_P3 *((volatile uint8_t *)(0x42DE030CUL)) +#define bFM_GPIO_PFR6_PE *((volatile uint8_t *)(0x42DE0338UL)) +#define bFM4_GPIO_PFR6_PE *((volatile uint8_t *)(0x42DE0338UL)) + +#define bFM_GPIO_PFR7_P0 *((volatile uint8_t *)(0x42DE0380UL)) +#define bFM4_GPIO_PFR7_P0 *((volatile uint8_t *)(0x42DE0380UL)) +#define bFM_GPIO_PFR7_P1 *((volatile uint8_t *)(0x42DE0384UL)) +#define bFM4_GPIO_PFR7_P1 *((volatile uint8_t *)(0x42DE0384UL)) +#define bFM_GPIO_PFR7_P2 *((volatile uint8_t *)(0x42DE0388UL)) +#define bFM4_GPIO_PFR7_P2 *((volatile uint8_t *)(0x42DE0388UL)) +#define bFM_GPIO_PFR7_P3 *((volatile uint8_t *)(0x42DE038CUL)) +#define bFM4_GPIO_PFR7_P3 *((volatile uint8_t *)(0x42DE038CUL)) +#define bFM_GPIO_PFR7_P4 *((volatile uint8_t *)(0x42DE0390UL)) +#define bFM4_GPIO_PFR7_P4 *((volatile uint8_t *)(0x42DE0390UL)) +#define bFM_GPIO_PFR7_P5 *((volatile uint8_t *)(0x42DE0394UL)) +#define bFM4_GPIO_PFR7_P5 *((volatile uint8_t *)(0x42DE0394UL)) +#define bFM_GPIO_PFR7_P6 *((volatile uint8_t *)(0x42DE0398UL)) +#define bFM4_GPIO_PFR7_P6 *((volatile uint8_t *)(0x42DE0398UL)) +#define bFM_GPIO_PFR7_P7 *((volatile uint8_t *)(0x42DE039CUL)) +#define bFM4_GPIO_PFR7_P7 *((volatile uint8_t *)(0x42DE039CUL)) +#define bFM_GPIO_PFR7_P8 *((volatile uint8_t *)(0x42DE03A0UL)) +#define bFM4_GPIO_PFR7_P8 *((volatile uint8_t *)(0x42DE03A0UL)) +#define bFM_GPIO_PFR7_P9 *((volatile uint8_t *)(0x42DE03A4UL)) +#define bFM4_GPIO_PFR7_P9 *((volatile uint8_t *)(0x42DE03A4UL)) +#define bFM_GPIO_PFR7_PA *((volatile uint8_t *)(0x42DE03A8UL)) +#define bFM4_GPIO_PFR7_PA *((volatile uint8_t *)(0x42DE03A8UL)) +#define bFM_GPIO_PFR7_PB *((volatile uint8_t *)(0x42DE03ACUL)) +#define bFM4_GPIO_PFR7_PB *((volatile uint8_t *)(0x42DE03ACUL)) +#define bFM_GPIO_PFR7_PC *((volatile uint8_t *)(0x42DE03B0UL)) +#define bFM4_GPIO_PFR7_PC *((volatile uint8_t *)(0x42DE03B0UL)) +#define bFM_GPIO_PFR7_PD *((volatile uint8_t *)(0x42DE03B4UL)) +#define bFM4_GPIO_PFR7_PD *((volatile uint8_t *)(0x42DE03B4UL)) +#define bFM_GPIO_PFR7_PE *((volatile uint8_t *)(0x42DE03B8UL)) +#define bFM4_GPIO_PFR7_PE *((volatile uint8_t *)(0x42DE03B8UL)) + +#define bFM_GPIO_PFR8_P0 *((volatile uint8_t *)(0x42DE0400UL)) +#define bFM4_GPIO_PFR8_P0 *((volatile uint8_t *)(0x42DE0400UL)) +#define bFM_GPIO_PFR8_P1 *((volatile uint8_t *)(0x42DE0404UL)) +#define bFM4_GPIO_PFR8_P1 *((volatile uint8_t *)(0x42DE0404UL)) +#define bFM_GPIO_PFR8_P2 *((volatile uint8_t *)(0x42DE0408UL)) +#define bFM4_GPIO_PFR8_P2 *((volatile uint8_t *)(0x42DE0408UL)) +#define bFM_GPIO_PFR8_P3 *((volatile uint8_t *)(0x42DE040CUL)) +#define bFM4_GPIO_PFR8_P3 *((volatile uint8_t *)(0x42DE040CUL)) + +#define bFM_GPIO_PFRA_P0 *((volatile uint8_t *)(0x42DE0500UL)) +#define bFM4_GPIO_PFRA_P0 *((volatile uint8_t *)(0x42DE0500UL)) +#define bFM_GPIO_PFRA_P1 *((volatile uint8_t *)(0x42DE0504UL)) +#define bFM4_GPIO_PFRA_P1 *((volatile uint8_t *)(0x42DE0504UL)) +#define bFM_GPIO_PFRA_P2 *((volatile uint8_t *)(0x42DE0508UL)) +#define bFM4_GPIO_PFRA_P2 *((volatile uint8_t *)(0x42DE0508UL)) +#define bFM_GPIO_PFRA_P3 *((volatile uint8_t *)(0x42DE050CUL)) +#define bFM4_GPIO_PFRA_P3 *((volatile uint8_t *)(0x42DE050CUL)) +#define bFM_GPIO_PFRA_P4 *((volatile uint8_t *)(0x42DE0510UL)) +#define bFM4_GPIO_PFRA_P4 *((volatile uint8_t *)(0x42DE0510UL)) +#define bFM_GPIO_PFRA_P5 *((volatile uint8_t *)(0x42DE0514UL)) +#define bFM4_GPIO_PFRA_P5 *((volatile uint8_t *)(0x42DE0514UL)) +#define bFM_GPIO_PFRA_P6 *((volatile uint8_t *)(0x42DE0518UL)) +#define bFM4_GPIO_PFRA_P6 *((volatile uint8_t *)(0x42DE0518UL)) +#define bFM_GPIO_PFRA_P7 *((volatile uint8_t *)(0x42DE051CUL)) +#define bFM4_GPIO_PFRA_P7 *((volatile uint8_t *)(0x42DE051CUL)) +#define bFM_GPIO_PFRA_P8 *((volatile uint8_t *)(0x42DE0520UL)) +#define bFM4_GPIO_PFRA_P8 *((volatile uint8_t *)(0x42DE0520UL)) +#define bFM_GPIO_PFRA_P9 *((volatile uint8_t *)(0x42DE0524UL)) +#define bFM4_GPIO_PFRA_P9 *((volatile uint8_t *)(0x42DE0524UL)) +#define bFM_GPIO_PFRA_PA *((volatile uint8_t *)(0x42DE0528UL)) +#define bFM4_GPIO_PFRA_PA *((volatile uint8_t *)(0x42DE0528UL)) +#define bFM_GPIO_PFRA_PB *((volatile uint8_t *)(0x42DE052CUL)) +#define bFM4_GPIO_PFRA_PB *((volatile uint8_t *)(0x42DE052CUL)) +#define bFM_GPIO_PFRA_PC *((volatile uint8_t *)(0x42DE0530UL)) +#define bFM4_GPIO_PFRA_PC *((volatile uint8_t *)(0x42DE0530UL)) +#define bFM_GPIO_PFRA_PD *((volatile uint8_t *)(0x42DE0534UL)) +#define bFM4_GPIO_PFRA_PD *((volatile uint8_t *)(0x42DE0534UL)) +#define bFM_GPIO_PFRA_PE *((volatile uint8_t *)(0x42DE0538UL)) +#define bFM4_GPIO_PFRA_PE *((volatile uint8_t *)(0x42DE0538UL)) +#define bFM_GPIO_PFRA_PF *((volatile uint8_t *)(0x42DE053CUL)) +#define bFM4_GPIO_PFRA_PF *((volatile uint8_t *)(0x42DE053CUL)) + +#define bFM_GPIO_PFRC_P0 *((volatile uint8_t *)(0x42DE0600UL)) +#define bFM4_GPIO_PFRC_P0 *((volatile uint8_t *)(0x42DE0600UL)) +#define bFM_GPIO_PFRC_P1 *((volatile uint8_t *)(0x42DE0604UL)) +#define bFM4_GPIO_PFRC_P1 *((volatile uint8_t *)(0x42DE0604UL)) +#define bFM_GPIO_PFRC_P2 *((volatile uint8_t *)(0x42DE0608UL)) +#define bFM4_GPIO_PFRC_P2 *((volatile uint8_t *)(0x42DE0608UL)) +#define bFM_GPIO_PFRC_P3 *((volatile uint8_t *)(0x42DE060CUL)) +#define bFM4_GPIO_PFRC_P3 *((volatile uint8_t *)(0x42DE060CUL)) +#define bFM_GPIO_PFRC_P4 *((volatile uint8_t *)(0x42DE0610UL)) +#define bFM4_GPIO_PFRC_P4 *((volatile uint8_t *)(0x42DE0610UL)) +#define bFM_GPIO_PFRC_P5 *((volatile uint8_t *)(0x42DE0614UL)) +#define bFM4_GPIO_PFRC_P5 *((volatile uint8_t *)(0x42DE0614UL)) +#define bFM_GPIO_PFRC_P6 *((volatile uint8_t *)(0x42DE0618UL)) +#define bFM4_GPIO_PFRC_P6 *((volatile uint8_t *)(0x42DE0618UL)) +#define bFM_GPIO_PFRC_P7 *((volatile uint8_t *)(0x42DE061CUL)) +#define bFM4_GPIO_PFRC_P7 *((volatile uint8_t *)(0x42DE061CUL)) +#define bFM_GPIO_PFRC_P8 *((volatile uint8_t *)(0x42DE0620UL)) +#define bFM4_GPIO_PFRC_P8 *((volatile uint8_t *)(0x42DE0620UL)) +#define bFM_GPIO_PFRC_P9 *((volatile uint8_t *)(0x42DE0624UL)) +#define bFM4_GPIO_PFRC_P9 *((volatile uint8_t *)(0x42DE0624UL)) +#define bFM_GPIO_PFRC_PA *((volatile uint8_t *)(0x42DE0628UL)) +#define bFM4_GPIO_PFRC_PA *((volatile uint8_t *)(0x42DE0628UL)) +#define bFM_GPIO_PFRC_PB *((volatile uint8_t *)(0x42DE062CUL)) +#define bFM4_GPIO_PFRC_PB *((volatile uint8_t *)(0x42DE062CUL)) +#define bFM_GPIO_PFRC_PC *((volatile uint8_t *)(0x42DE0630UL)) +#define bFM4_GPIO_PFRC_PC *((volatile uint8_t *)(0x42DE0630UL)) +#define bFM_GPIO_PFRC_PD *((volatile uint8_t *)(0x42DE0634UL)) +#define bFM4_GPIO_PFRC_PD *((volatile uint8_t *)(0x42DE0634UL)) +#define bFM_GPIO_PFRC_PE *((volatile uint8_t *)(0x42DE0638UL)) +#define bFM4_GPIO_PFRC_PE *((volatile uint8_t *)(0x42DE0638UL)) +#define bFM_GPIO_PFRC_PF *((volatile uint8_t *)(0x42DE063CUL)) +#define bFM4_GPIO_PFRC_PF *((volatile uint8_t *)(0x42DE063CUL)) + +#define bFM_GPIO_PFRD_P0 *((volatile uint8_t *)(0x42DE0680UL)) +#define bFM4_GPIO_PFRD_P0 *((volatile uint8_t *)(0x42DE0680UL)) +#define bFM_GPIO_PFRD_P1 *((volatile uint8_t *)(0x42DE0684UL)) +#define bFM4_GPIO_PFRD_P1 *((volatile uint8_t *)(0x42DE0684UL)) +#define bFM_GPIO_PFRD_P2 *((volatile uint8_t *)(0x42DE0688UL)) +#define bFM4_GPIO_PFRD_P2 *((volatile uint8_t *)(0x42DE0688UL)) + +#define bFM_GPIO_PFRE_P0 *((volatile uint8_t *)(0x42DE0700UL)) +#define bFM4_GPIO_PFRE_P0 *((volatile uint8_t *)(0x42DE0700UL)) +#define bFM_GPIO_PFRE_P2 *((volatile uint8_t *)(0x42DE0708UL)) +#define bFM4_GPIO_PFRE_P2 *((volatile uint8_t *)(0x42DE0708UL)) +#define bFM_GPIO_PFRE_P3 *((volatile uint8_t *)(0x42DE070CUL)) +#define bFM4_GPIO_PFRE_P3 *((volatile uint8_t *)(0x42DE070CUL)) + +#define bFM_GPIO_PZR0_P0 *((volatile uint8_t *)(0x42DEE000UL)) +#define bFM4_GPIO_PZR0_P0 *((volatile uint8_t *)(0x42DEE000UL)) +#define bFM_GPIO_PZR0_P1 *((volatile uint8_t *)(0x42DEE004UL)) +#define bFM4_GPIO_PZR0_P1 *((volatile uint8_t *)(0x42DEE004UL)) +#define bFM_GPIO_PZR0_P2 *((volatile uint8_t *)(0x42DEE008UL)) +#define bFM4_GPIO_PZR0_P2 *((volatile uint8_t *)(0x42DEE008UL)) +#define bFM_GPIO_PZR0_P3 *((volatile uint8_t *)(0x42DEE00CUL)) +#define bFM4_GPIO_PZR0_P3 *((volatile uint8_t *)(0x42DEE00CUL)) +#define bFM_GPIO_PZR0_P4 *((volatile uint8_t *)(0x42DEE010UL)) +#define bFM4_GPIO_PZR0_P4 *((volatile uint8_t *)(0x42DEE010UL)) +#define bFM_GPIO_PZR0_P8 *((volatile uint8_t *)(0x42DEE020UL)) +#define bFM4_GPIO_PZR0_P8 *((volatile uint8_t *)(0x42DEE020UL)) +#define bFM_GPIO_PZR0_P9 *((volatile uint8_t *)(0x42DEE024UL)) +#define bFM4_GPIO_PZR0_P9 *((volatile uint8_t *)(0x42DEE024UL)) +#define bFM_GPIO_PZR0_PA *((volatile uint8_t *)(0x42DEE028UL)) +#define bFM4_GPIO_PZR0_PA *((volatile uint8_t *)(0x42DEE028UL)) + +#define bFM_GPIO_PZR1_P0 *((volatile uint8_t *)(0x42DEE080UL)) +#define bFM4_GPIO_PZR1_P0 *((volatile uint8_t *)(0x42DEE080UL)) +#define bFM_GPIO_PZR1_P1 *((volatile uint8_t *)(0x42DEE084UL)) +#define bFM4_GPIO_PZR1_P1 *((volatile uint8_t *)(0x42DEE084UL)) +#define bFM_GPIO_PZR1_P2 *((volatile uint8_t *)(0x42DEE088UL)) +#define bFM4_GPIO_PZR1_P2 *((volatile uint8_t *)(0x42DEE088UL)) +#define bFM_GPIO_PZR1_P3 *((volatile uint8_t *)(0x42DEE08CUL)) +#define bFM4_GPIO_PZR1_P3 *((volatile uint8_t *)(0x42DEE08CUL)) +#define bFM_GPIO_PZR1_P4 *((volatile uint8_t *)(0x42DEE090UL)) +#define bFM4_GPIO_PZR1_P4 *((volatile uint8_t *)(0x42DEE090UL)) +#define bFM_GPIO_PZR1_P5 *((volatile uint8_t *)(0x42DEE094UL)) +#define bFM4_GPIO_PZR1_P5 *((volatile uint8_t *)(0x42DEE094UL)) +#define bFM_GPIO_PZR1_P6 *((volatile uint8_t *)(0x42DEE098UL)) +#define bFM4_GPIO_PZR1_P6 *((volatile uint8_t *)(0x42DEE098UL)) +#define bFM_GPIO_PZR1_P7 *((volatile uint8_t *)(0x42DEE09CUL)) +#define bFM4_GPIO_PZR1_P7 *((volatile uint8_t *)(0x42DEE09CUL)) +#define bFM_GPIO_PZR1_P8 *((volatile uint8_t *)(0x42DEE0A0UL)) +#define bFM4_GPIO_PZR1_P8 *((volatile uint8_t *)(0x42DEE0A0UL)) +#define bFM_GPIO_PZR1_P9 *((volatile uint8_t *)(0x42DEE0A4UL)) +#define bFM4_GPIO_PZR1_P9 *((volatile uint8_t *)(0x42DEE0A4UL)) +#define bFM_GPIO_PZR1_PA *((volatile uint8_t *)(0x42DEE0A8UL)) +#define bFM4_GPIO_PZR1_PA *((volatile uint8_t *)(0x42DEE0A8UL)) +#define bFM_GPIO_PZR1_PB *((volatile uint8_t *)(0x42DEE0ACUL)) +#define bFM4_GPIO_PZR1_PB *((volatile uint8_t *)(0x42DEE0ACUL)) +#define bFM_GPIO_PZR1_PC *((volatile uint8_t *)(0x42DEE0B0UL)) +#define bFM4_GPIO_PZR1_PC *((volatile uint8_t *)(0x42DEE0B0UL)) +#define bFM_GPIO_PZR1_PD *((volatile uint8_t *)(0x42DEE0B4UL)) +#define bFM4_GPIO_PZR1_PD *((volatile uint8_t *)(0x42DEE0B4UL)) +#define bFM_GPIO_PZR1_PE *((volatile uint8_t *)(0x42DEE0B8UL)) +#define bFM4_GPIO_PZR1_PE *((volatile uint8_t *)(0x42DEE0B8UL)) +#define bFM_GPIO_PZR1_PF *((volatile uint8_t *)(0x42DEE0BCUL)) +#define bFM4_GPIO_PZR1_PF *((volatile uint8_t *)(0x42DEE0BCUL)) + +#define bFM_GPIO_PZR2_P0 *((volatile uint8_t *)(0x42DEE100UL)) +#define bFM4_GPIO_PZR2_P0 *((volatile uint8_t *)(0x42DEE100UL)) +#define bFM_GPIO_PZR2_P1 *((volatile uint8_t *)(0x42DEE104UL)) +#define bFM4_GPIO_PZR2_P1 *((volatile uint8_t *)(0x42DEE104UL)) +#define bFM_GPIO_PZR2_P2 *((volatile uint8_t *)(0x42DEE108UL)) +#define bFM4_GPIO_PZR2_P2 *((volatile uint8_t *)(0x42DEE108UL)) +#define bFM_GPIO_PZR2_P3 *((volatile uint8_t *)(0x42DEE10CUL)) +#define bFM4_GPIO_PZR2_P3 *((volatile uint8_t *)(0x42DEE10CUL)) +#define bFM_GPIO_PZR2_P4 *((volatile uint8_t *)(0x42DEE110UL)) +#define bFM4_GPIO_PZR2_P4 *((volatile uint8_t *)(0x42DEE110UL)) +#define bFM_GPIO_PZR2_P5 *((volatile uint8_t *)(0x42DEE114UL)) +#define bFM4_GPIO_PZR2_P5 *((volatile uint8_t *)(0x42DEE114UL)) +#define bFM_GPIO_PZR2_P6 *((volatile uint8_t *)(0x42DEE118UL)) +#define bFM4_GPIO_PZR2_P6 *((volatile uint8_t *)(0x42DEE118UL)) +#define bFM_GPIO_PZR2_P7 *((volatile uint8_t *)(0x42DEE11CUL)) +#define bFM4_GPIO_PZR2_P7 *((volatile uint8_t *)(0x42DEE11CUL)) +#define bFM_GPIO_PZR2_P8 *((volatile uint8_t *)(0x42DEE120UL)) +#define bFM4_GPIO_PZR2_P8 *((volatile uint8_t *)(0x42DEE120UL)) +#define bFM_GPIO_PZR2_P9 *((volatile uint8_t *)(0x42DEE124UL)) +#define bFM4_GPIO_PZR2_P9 *((volatile uint8_t *)(0x42DEE124UL)) +#define bFM_GPIO_PZR2_PA *((volatile uint8_t *)(0x42DEE128UL)) +#define bFM4_GPIO_PZR2_PA *((volatile uint8_t *)(0x42DEE128UL)) + +#define bFM_GPIO_PZR3_P2 *((volatile uint8_t *)(0x42DEE188UL)) +#define bFM4_GPIO_PZR3_P2 *((volatile uint8_t *)(0x42DEE188UL)) +#define bFM_GPIO_PZR3_P3 *((volatile uint8_t *)(0x42DEE18CUL)) +#define bFM4_GPIO_PZR3_P3 *((volatile uint8_t *)(0x42DEE18CUL)) +#define bFM_GPIO_PZR3_P4 *((volatile uint8_t *)(0x42DEE190UL)) +#define bFM4_GPIO_PZR3_P4 *((volatile uint8_t *)(0x42DEE190UL)) +#define bFM_GPIO_PZR3_P5 *((volatile uint8_t *)(0x42DEE194UL)) +#define bFM4_GPIO_PZR3_P5 *((volatile uint8_t *)(0x42DEE194UL)) +#define bFM_GPIO_PZR3_P6 *((volatile uint8_t *)(0x42DEE198UL)) +#define bFM4_GPIO_PZR3_P6 *((volatile uint8_t *)(0x42DEE198UL)) +#define bFM_GPIO_PZR3_P7 *((volatile uint8_t *)(0x42DEE19CUL)) +#define bFM4_GPIO_PZR3_P7 *((volatile uint8_t *)(0x42DEE19CUL)) +#define bFM_GPIO_PZR3_P8 *((volatile uint8_t *)(0x42DEE1A0UL)) +#define bFM4_GPIO_PZR3_P8 *((volatile uint8_t *)(0x42DEE1A0UL)) +#define bFM_GPIO_PZR3_P9 *((volatile uint8_t *)(0x42DEE1A4UL)) +#define bFM4_GPIO_PZR3_P9 *((volatile uint8_t *)(0x42DEE1A4UL)) +#define bFM_GPIO_PZR3_PA *((volatile uint8_t *)(0x42DEE1A8UL)) +#define bFM4_GPIO_PZR3_PA *((volatile uint8_t *)(0x42DEE1A8UL)) +#define bFM_GPIO_PZR3_PB *((volatile uint8_t *)(0x42DEE1ACUL)) +#define bFM4_GPIO_PZR3_PB *((volatile uint8_t *)(0x42DEE1ACUL)) +#define bFM_GPIO_PZR3_PC *((volatile uint8_t *)(0x42DEE1B0UL)) +#define bFM4_GPIO_PZR3_PC *((volatile uint8_t *)(0x42DEE1B0UL)) +#define bFM_GPIO_PZR3_PD *((volatile uint8_t *)(0x42DEE1B4UL)) +#define bFM4_GPIO_PZR3_PD *((volatile uint8_t *)(0x42DEE1B4UL)) +#define bFM_GPIO_PZR3_PE *((volatile uint8_t *)(0x42DEE1B8UL)) +#define bFM4_GPIO_PZR3_PE *((volatile uint8_t *)(0x42DEE1B8UL)) + +#define bFM_GPIO_PZR4_P0 *((volatile uint8_t *)(0x42DEE200UL)) +#define bFM4_GPIO_PZR4_P0 *((volatile uint8_t *)(0x42DEE200UL)) +#define bFM_GPIO_PZR4_P1 *((volatile uint8_t *)(0x42DEE204UL)) +#define bFM4_GPIO_PZR4_P1 *((volatile uint8_t *)(0x42DEE204UL)) +#define bFM_GPIO_PZR4_P2 *((volatile uint8_t *)(0x42DEE208UL)) +#define bFM4_GPIO_PZR4_P2 *((volatile uint8_t *)(0x42DEE208UL)) +#define bFM_GPIO_PZR4_P3 *((volatile uint8_t *)(0x42DEE20CUL)) +#define bFM4_GPIO_PZR4_P3 *((volatile uint8_t *)(0x42DEE20CUL)) +#define bFM_GPIO_PZR4_P4 *((volatile uint8_t *)(0x42DEE210UL)) +#define bFM4_GPIO_PZR4_P4 *((volatile uint8_t *)(0x42DEE210UL)) +#define bFM_GPIO_PZR4_P5 *((volatile uint8_t *)(0x42DEE214UL)) +#define bFM4_GPIO_PZR4_P5 *((volatile uint8_t *)(0x42DEE214UL)) +#define bFM_GPIO_PZR4_P6 *((volatile uint8_t *)(0x42DEE218UL)) +#define bFM4_GPIO_PZR4_P6 *((volatile uint8_t *)(0x42DEE218UL)) +#define bFM_GPIO_PZR4_P7 *((volatile uint8_t *)(0x42DEE21CUL)) +#define bFM4_GPIO_PZR4_P7 *((volatile uint8_t *)(0x42DEE21CUL)) +#define bFM_GPIO_PZR4_P8 *((volatile uint8_t *)(0x42DEE220UL)) +#define bFM4_GPIO_PZR4_P8 *((volatile uint8_t *)(0x42DEE220UL)) +#define bFM_GPIO_PZR4_P9 *((volatile uint8_t *)(0x42DEE224UL)) +#define bFM4_GPIO_PZR4_P9 *((volatile uint8_t *)(0x42DEE224UL)) + +#define bFM_GPIO_PZR6_P0 *((volatile uint8_t *)(0x42DEE300UL)) +#define bFM4_GPIO_PZR6_P0 *((volatile uint8_t *)(0x42DEE300UL)) +#define bFM_GPIO_PZR6_P1 *((volatile uint8_t *)(0x42DEE304UL)) +#define bFM4_GPIO_PZR6_P1 *((volatile uint8_t *)(0x42DEE304UL)) +#define bFM_GPIO_PZR6_P2 *((volatile uint8_t *)(0x42DEE308UL)) +#define bFM4_GPIO_PZR6_P2 *((volatile uint8_t *)(0x42DEE308UL)) +#define bFM_GPIO_PZR6_P3 *((volatile uint8_t *)(0x42DEE30CUL)) +#define bFM4_GPIO_PZR6_P3 *((volatile uint8_t *)(0x42DEE30CUL)) +#define bFM_GPIO_PZR6_PE *((volatile uint8_t *)(0x42DEE338UL)) +#define bFM4_GPIO_PZR6_PE *((volatile uint8_t *)(0x42DEE338UL)) + +#define bFM_GPIO_PZR7_P0 *((volatile uint8_t *)(0x42DEE380UL)) +#define bFM4_GPIO_PZR7_P0 *((volatile uint8_t *)(0x42DEE380UL)) +#define bFM_GPIO_PZR7_P1 *((volatile uint8_t *)(0x42DEE384UL)) +#define bFM4_GPIO_PZR7_P1 *((volatile uint8_t *)(0x42DEE384UL)) +#define bFM_GPIO_PZR7_P2 *((volatile uint8_t *)(0x42DEE388UL)) +#define bFM4_GPIO_PZR7_P2 *((volatile uint8_t *)(0x42DEE388UL)) +#define bFM_GPIO_PZR7_P3 *((volatile uint8_t *)(0x42DEE38CUL)) +#define bFM4_GPIO_PZR7_P3 *((volatile uint8_t *)(0x42DEE38CUL)) +#define bFM_GPIO_PZR7_P4 *((volatile uint8_t *)(0x42DEE390UL)) +#define bFM4_GPIO_PZR7_P4 *((volatile uint8_t *)(0x42DEE390UL)) +#define bFM_GPIO_PZR7_P5 *((volatile uint8_t *)(0x42DEE394UL)) +#define bFM4_GPIO_PZR7_P5 *((volatile uint8_t *)(0x42DEE394UL)) +#define bFM_GPIO_PZR7_P6 *((volatile uint8_t *)(0x42DEE398UL)) +#define bFM4_GPIO_PZR7_P6 *((volatile uint8_t *)(0x42DEE398UL)) +#define bFM_GPIO_PZR7_P7 *((volatile uint8_t *)(0x42DEE39CUL)) +#define bFM4_GPIO_PZR7_P7 *((volatile uint8_t *)(0x42DEE39CUL)) +#define bFM_GPIO_PZR7_P8 *((volatile uint8_t *)(0x42DEE3A0UL)) +#define bFM4_GPIO_PZR7_P8 *((volatile uint8_t *)(0x42DEE3A0UL)) +#define bFM_GPIO_PZR7_P9 *((volatile uint8_t *)(0x42DEE3A4UL)) +#define bFM4_GPIO_PZR7_P9 *((volatile uint8_t *)(0x42DEE3A4UL)) +#define bFM_GPIO_PZR7_PA *((volatile uint8_t *)(0x42DEE3A8UL)) +#define bFM4_GPIO_PZR7_PA *((volatile uint8_t *)(0x42DEE3A8UL)) +#define bFM_GPIO_PZR7_PB *((volatile uint8_t *)(0x42DEE3ACUL)) +#define bFM4_GPIO_PZR7_PB *((volatile uint8_t *)(0x42DEE3ACUL)) +#define bFM_GPIO_PZR7_PC *((volatile uint8_t *)(0x42DEE3B0UL)) +#define bFM4_GPIO_PZR7_PC *((volatile uint8_t *)(0x42DEE3B0UL)) +#define bFM_GPIO_PZR7_PD *((volatile uint8_t *)(0x42DEE3B4UL)) +#define bFM4_GPIO_PZR7_PD *((volatile uint8_t *)(0x42DEE3B4UL)) +#define bFM_GPIO_PZR7_PE *((volatile uint8_t *)(0x42DEE3B8UL)) +#define bFM4_GPIO_PZR7_PE *((volatile uint8_t *)(0x42DEE3B8UL)) + +#define bFM_GPIO_PZR8_P0 *((volatile uint8_t *)(0x42DEE400UL)) +#define bFM4_GPIO_PZR8_P0 *((volatile uint8_t *)(0x42DEE400UL)) +#define bFM_GPIO_PZR8_P1 *((volatile uint8_t *)(0x42DEE404UL)) +#define bFM4_GPIO_PZR8_P1 *((volatile uint8_t *)(0x42DEE404UL)) +#define bFM_GPIO_PZR8_P2 *((volatile uint8_t *)(0x42DEE408UL)) +#define bFM4_GPIO_PZR8_P2 *((volatile uint8_t *)(0x42DEE408UL)) +#define bFM_GPIO_PZR8_P3 *((volatile uint8_t *)(0x42DEE40CUL)) +#define bFM4_GPIO_PZR8_P3 *((volatile uint8_t *)(0x42DEE40CUL)) + +#define bFM_GPIO_PZRA_P0 *((volatile uint8_t *)(0x42DEE500UL)) +#define bFM4_GPIO_PZRA_P0 *((volatile uint8_t *)(0x42DEE500UL)) +#define bFM_GPIO_PZRA_P1 *((volatile uint8_t *)(0x42DEE504UL)) +#define bFM4_GPIO_PZRA_P1 *((volatile uint8_t *)(0x42DEE504UL)) +#define bFM_GPIO_PZRA_P2 *((volatile uint8_t *)(0x42DEE508UL)) +#define bFM4_GPIO_PZRA_P2 *((volatile uint8_t *)(0x42DEE508UL)) +#define bFM_GPIO_PZRA_P3 *((volatile uint8_t *)(0x42DEE50CUL)) +#define bFM4_GPIO_PZRA_P3 *((volatile uint8_t *)(0x42DEE50CUL)) +#define bFM_GPIO_PZRA_P4 *((volatile uint8_t *)(0x42DEE510UL)) +#define bFM4_GPIO_PZRA_P4 *((volatile uint8_t *)(0x42DEE510UL)) +#define bFM_GPIO_PZRA_P5 *((volatile uint8_t *)(0x42DEE514UL)) +#define bFM4_GPIO_PZRA_P5 *((volatile uint8_t *)(0x42DEE514UL)) +#define bFM_GPIO_PZRA_P6 *((volatile uint8_t *)(0x42DEE518UL)) +#define bFM4_GPIO_PZRA_P6 *((volatile uint8_t *)(0x42DEE518UL)) +#define bFM_GPIO_PZRA_P7 *((volatile uint8_t *)(0x42DEE51CUL)) +#define bFM4_GPIO_PZRA_P7 *((volatile uint8_t *)(0x42DEE51CUL)) +#define bFM_GPIO_PZRA_P8 *((volatile uint8_t *)(0x42DEE520UL)) +#define bFM4_GPIO_PZRA_P8 *((volatile uint8_t *)(0x42DEE520UL)) +#define bFM_GPIO_PZRA_P9 *((volatile uint8_t *)(0x42DEE524UL)) +#define bFM4_GPIO_PZRA_P9 *((volatile uint8_t *)(0x42DEE524UL)) +#define bFM_GPIO_PZRA_PA *((volatile uint8_t *)(0x42DEE528UL)) +#define bFM4_GPIO_PZRA_PA *((volatile uint8_t *)(0x42DEE528UL)) +#define bFM_GPIO_PZRA_PB *((volatile uint8_t *)(0x42DEE52CUL)) +#define bFM4_GPIO_PZRA_PB *((volatile uint8_t *)(0x42DEE52CUL)) +#define bFM_GPIO_PZRA_PC *((volatile uint8_t *)(0x42DEE530UL)) +#define bFM4_GPIO_PZRA_PC *((volatile uint8_t *)(0x42DEE530UL)) +#define bFM_GPIO_PZRA_PD *((volatile uint8_t *)(0x42DEE534UL)) +#define bFM4_GPIO_PZRA_PD *((volatile uint8_t *)(0x42DEE534UL)) +#define bFM_GPIO_PZRA_PE *((volatile uint8_t *)(0x42DEE538UL)) +#define bFM4_GPIO_PZRA_PE *((volatile uint8_t *)(0x42DEE538UL)) +#define bFM_GPIO_PZRA_PF *((volatile uint8_t *)(0x42DEE53CUL)) +#define bFM4_GPIO_PZRA_PF *((volatile uint8_t *)(0x42DEE53CUL)) + +#define bFM_GPIO_PZRC_P0 *((volatile uint8_t *)(0x42DEE600UL)) +#define bFM4_GPIO_PZRC_P0 *((volatile uint8_t *)(0x42DEE600UL)) +#define bFM_GPIO_PZRC_P1 *((volatile uint8_t *)(0x42DEE604UL)) +#define bFM4_GPIO_PZRC_P1 *((volatile uint8_t *)(0x42DEE604UL)) +#define bFM_GPIO_PZRC_P2 *((volatile uint8_t *)(0x42DEE608UL)) +#define bFM4_GPIO_PZRC_P2 *((volatile uint8_t *)(0x42DEE608UL)) +#define bFM_GPIO_PZRC_P3 *((volatile uint8_t *)(0x42DEE60CUL)) +#define bFM4_GPIO_PZRC_P3 *((volatile uint8_t *)(0x42DEE60CUL)) +#define bFM_GPIO_PZRC_P4 *((volatile uint8_t *)(0x42DEE610UL)) +#define bFM4_GPIO_PZRC_P4 *((volatile uint8_t *)(0x42DEE610UL)) +#define bFM_GPIO_PZRC_P5 *((volatile uint8_t *)(0x42DEE614UL)) +#define bFM4_GPIO_PZRC_P5 *((volatile uint8_t *)(0x42DEE614UL)) +#define bFM_GPIO_PZRC_P6 *((volatile uint8_t *)(0x42DEE618UL)) +#define bFM4_GPIO_PZRC_P6 *((volatile uint8_t *)(0x42DEE618UL)) +#define bFM_GPIO_PZRC_P7 *((volatile uint8_t *)(0x42DEE61CUL)) +#define bFM4_GPIO_PZRC_P7 *((volatile uint8_t *)(0x42DEE61CUL)) +#define bFM_GPIO_PZRC_P8 *((volatile uint8_t *)(0x42DEE620UL)) +#define bFM4_GPIO_PZRC_P8 *((volatile uint8_t *)(0x42DEE620UL)) +#define bFM_GPIO_PZRC_P9 *((volatile uint8_t *)(0x42DEE624UL)) +#define bFM4_GPIO_PZRC_P9 *((volatile uint8_t *)(0x42DEE624UL)) +#define bFM_GPIO_PZRC_PA *((volatile uint8_t *)(0x42DEE628UL)) +#define bFM4_GPIO_PZRC_PA *((volatile uint8_t *)(0x42DEE628UL)) +#define bFM_GPIO_PZRC_PB *((volatile uint8_t *)(0x42DEE62CUL)) +#define bFM4_GPIO_PZRC_PB *((volatile uint8_t *)(0x42DEE62CUL)) +#define bFM_GPIO_PZRC_PC *((volatile uint8_t *)(0x42DEE630UL)) +#define bFM4_GPIO_PZRC_PC *((volatile uint8_t *)(0x42DEE630UL)) +#define bFM_GPIO_PZRC_PD *((volatile uint8_t *)(0x42DEE634UL)) +#define bFM4_GPIO_PZRC_PD *((volatile uint8_t *)(0x42DEE634UL)) +#define bFM_GPIO_PZRC_PE *((volatile uint8_t *)(0x42DEE638UL)) +#define bFM4_GPIO_PZRC_PE *((volatile uint8_t *)(0x42DEE638UL)) +#define bFM_GPIO_PZRC_PF *((volatile uint8_t *)(0x42DEE63CUL)) +#define bFM4_GPIO_PZRC_PF *((volatile uint8_t *)(0x42DEE63CUL)) + +#define bFM_GPIO_PZRD_P0 *((volatile uint8_t *)(0x42DEE680UL)) +#define bFM4_GPIO_PZRD_P0 *((volatile uint8_t *)(0x42DEE680UL)) +#define bFM_GPIO_PZRD_P1 *((volatile uint8_t *)(0x42DEE684UL)) +#define bFM4_GPIO_PZRD_P1 *((volatile uint8_t *)(0x42DEE684UL)) +#define bFM_GPIO_PZRD_P2 *((volatile uint8_t *)(0x42DEE688UL)) +#define bFM4_GPIO_PZRD_P2 *((volatile uint8_t *)(0x42DEE688UL)) + +#define bFM_GPIO_PZRE_P0 *((volatile uint8_t *)(0x42DEE700UL)) +#define bFM4_GPIO_PZRE_P0 *((volatile uint8_t *)(0x42DEE700UL)) +#define bFM_GPIO_PZRE_P2 *((volatile uint8_t *)(0x42DEE708UL)) +#define bFM4_GPIO_PZRE_P2 *((volatile uint8_t *)(0x42DEE708UL)) +#define bFM_GPIO_PZRE_P3 *((volatile uint8_t *)(0x42DEE70CUL)) +#define bFM4_GPIO_PZRE_P3 *((volatile uint8_t *)(0x42DEE70CUL)) + +#define bFM_GPIO_SPSR_USB0C *((volatile uint8_t *)(0x42DEB010UL)) +#define bFM4_GPIO_SPSR_USB0C *((volatile uint8_t *)(0x42DEB010UL)) +#define bFM_GPIO_SPSR_USB1C *((volatile uint8_t *)(0x42DEB014UL)) +#define bFM4_GPIO_SPSR_USB1C *((volatile uint8_t *)(0x42DEB014UL)) + + +/******************************************************************************* +* HSSPI Registers HSSPI +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* HWWDT Registers HWWDT +* Bitband Section +*******************************************************************************/ +#define bFM_HWWDT_WDG_CTL_INTEN *((volatile uint32_t*)(0x42220100UL)) +#define bFM4_HWWDT_WDG_CTL_INTEN *((volatile uint32_t*)(0x42220100UL)) +#define bFM_HWWDT_WDG_CTL_RESEN *((volatile uint32_t*)(0x42220104UL)) +#define bFM4_HWWDT_WDG_CTL_RESEN *((volatile uint32_t*)(0x42220104UL)) + +#define bFM_HWWDT_WDG_RIS_RIS *((volatile uint32_t*)(0x42220200UL)) +#define bFM4_HWWDT_WDG_RIS_RIS *((volatile uint32_t*)(0x42220200UL)) + + +/******************************************************************************* +* I2S Registers I2S0 +* Bitband Section +*******************************************************************************/ +#define bFM_I2S0_CNTREG_FSPL *((volatile uint8_t *)(0x42D80100UL)) +#define bFM4_I2S0_CNTREG_FSPL *((volatile uint8_t *)(0x42D80100UL)) +#define bFM_I2S0_CNTREG_FSLN *((volatile uint8_t *)(0x42D80104UL)) +#define bFM4_I2S0_CNTREG_FSLN *((volatile uint8_t *)(0x42D80104UL)) +#define bFM_I2S0_CNTREG_FSPH *((volatile uint8_t *)(0x42D80108UL)) +#define bFM4_I2S0_CNTREG_FSPH *((volatile uint8_t *)(0x42D80108UL)) +#define bFM_I2S0_CNTREG_CPOL *((volatile uint8_t *)(0x42D8010CUL)) +#define bFM4_I2S0_CNTREG_CPOL *((volatile uint8_t *)(0x42D8010CUL)) +#define bFM_I2S0_CNTREG_SMPL *((volatile uint8_t *)(0x42D80110UL)) +#define bFM4_I2S0_CNTREG_SMPL *((volatile uint8_t *)(0x42D80110UL)) +#define bFM_I2S0_CNTREG_RXDIS *((volatile uint8_t *)(0x42D80114UL)) +#define bFM4_I2S0_CNTREG_RXDIS *((volatile uint8_t *)(0x42D80114UL)) +#define bFM_I2S0_CNTREG_TXDIS *((volatile uint8_t *)(0x42D80118UL)) +#define bFM4_I2S0_CNTREG_TXDIS *((volatile uint8_t *)(0x42D80118UL)) +#define bFM_I2S0_CNTREG_MLSB *((volatile uint8_t *)(0x42D8011CUL)) +#define bFM4_I2S0_CNTREG_MLSB *((volatile uint8_t *)(0x42D8011CUL)) +#define bFM_I2S0_CNTREG_FRUN *((volatile uint8_t *)(0x42D80120UL)) +#define bFM4_I2S0_CNTREG_FRUN *((volatile uint8_t *)(0x42D80120UL)) +#define bFM_I2S0_CNTREG_BEXT *((volatile uint8_t *)(0x42D80124UL)) +#define bFM4_I2S0_CNTREG_BEXT *((volatile uint8_t *)(0x42D80124UL)) +#define bFM_I2S0_CNTREG_ECKM *((volatile uint8_t *)(0x42D80128UL)) +#define bFM4_I2S0_CNTREG_ECKM *((volatile uint8_t *)(0x42D80128UL)) +#define bFM_I2S0_CNTREG_RHLL *((volatile uint8_t *)(0x42D8012CUL)) +#define bFM4_I2S0_CNTREG_RHLL *((volatile uint8_t *)(0x42D8012CUL)) +#define bFM_I2S0_CNTREG_SBFN *((volatile uint8_t *)(0x42D80130UL)) +#define bFM4_I2S0_CNTREG_SBFN *((volatile uint8_t *)(0x42D80130UL)) +#define bFM_I2S0_CNTREG_MSMD *((volatile uint8_t *)(0x42D80134UL)) +#define bFM4_I2S0_CNTREG_MSMD *((volatile uint8_t *)(0x42D80134UL)) +#define bFM_I2S0_CNTREG_MSKB *((volatile uint8_t *)(0x42D80138UL)) +#define bFM4_I2S0_CNTREG_MSKB *((volatile uint8_t *)(0x42D80138UL)) + +#define bFM_I2S0_DMAACT_RDMACT *((volatile uint8_t *)(0x42D80500UL)) +#define bFM4_I2S0_DMAACT_RDMACT *((volatile uint8_t *)(0x42D80500UL)) +#define bFM_I2S0_DMAACT_RL1E0 *((volatile uint8_t *)(0x42D80520UL)) +#define bFM4_I2S0_DMAACT_RL1E0 *((volatile uint8_t *)(0x42D80520UL)) +#define bFM_I2S0_DMAACT_TDMACT *((volatile uint8_t *)(0x42D80540UL)) +#define bFM4_I2S0_DMAACT_TDMACT *((volatile uint8_t *)(0x42D80540UL)) +#define bFM_I2S0_DMAACT_TL1E0 *((volatile uint8_t *)(0x42D80560UL)) +#define bFM4_I2S0_DMAACT_TL1E0 *((volatile uint8_t *)(0x42D80560UL)) + +#define bFM_I2S0_INTCNT_RXFIM *((volatile uint8_t *)(0x42D80440UL)) +#define bFM4_I2S0_INTCNT_RXFIM *((volatile uint8_t *)(0x42D80440UL)) +#define bFM_I2S0_INTCNT_RXFDM *((volatile uint8_t *)(0x42D80444UL)) +#define bFM4_I2S0_INTCNT_RXFDM *((volatile uint8_t *)(0x42D80444UL)) +#define bFM_I2S0_INTCNT_EOPM *((volatile uint8_t *)(0x42D80448UL)) +#define bFM4_I2S0_INTCNT_EOPM *((volatile uint8_t *)(0x42D80448UL)) +#define bFM_I2S0_INTCNT_RXOVM *((volatile uint8_t *)(0x42D8044CUL)) +#define bFM4_I2S0_INTCNT_RXOVM *((volatile uint8_t *)(0x42D8044CUL)) +#define bFM_I2S0_INTCNT_RXUDM *((volatile uint8_t *)(0x42D80450UL)) +#define bFM4_I2S0_INTCNT_RXUDM *((volatile uint8_t *)(0x42D80450UL)) +#define bFM_I2S0_INTCNT_RBERM *((volatile uint8_t *)(0x42D80454UL)) +#define bFM4_I2S0_INTCNT_RBERM *((volatile uint8_t *)(0x42D80454UL)) +#define bFM_I2S0_INTCNT_TXFIM *((volatile uint8_t *)(0x42D80460UL)) +#define bFM4_I2S0_INTCNT_TXFIM *((volatile uint8_t *)(0x42D80460UL)) +#define bFM_I2S0_INTCNT_TXFDM *((volatile uint8_t *)(0x42D80464UL)) +#define bFM4_I2S0_INTCNT_TXFDM *((volatile uint8_t *)(0x42D80464UL)) +#define bFM_I2S0_INTCNT_TXOVM *((volatile uint8_t *)(0x42D80468UL)) +#define bFM4_I2S0_INTCNT_TXOVM *((volatile uint8_t *)(0x42D80468UL)) +#define bFM_I2S0_INTCNT_TXUD0M *((volatile uint8_t *)(0x42D8046CUL)) +#define bFM4_I2S0_INTCNT_TXUD0M *((volatile uint8_t *)(0x42D8046CUL)) +#define bFM_I2S0_INTCNT_FERRM *((volatile uint8_t *)(0x42D80470UL)) +#define bFM4_I2S0_INTCNT_FERRM *((volatile uint8_t *)(0x42D80470UL)) +#define bFM_I2S0_INTCNT_TBERM *((volatile uint8_t *)(0x42D80474UL)) +#define bFM4_I2S0_INTCNT_TBERM *((volatile uint8_t *)(0x42D80474UL)) +#define bFM_I2S0_INTCNT_TXUD1M *((volatile uint8_t *)(0x42D80478UL)) +#define bFM4_I2S0_INTCNT_TXUD1M *((volatile uint8_t *)(0x42D80478UL)) + +#define bFM_I2S0_MCR1REG_S0CH00 *((volatile uint8_t *)(0x42D80200UL)) +#define bFM4_I2S0_MCR1REG_S0CH00 *((volatile uint8_t *)(0x42D80200UL)) +#define bFM_I2S0_MCR1REG_S0CH01 *((volatile uint8_t *)(0x42D80204UL)) +#define bFM4_I2S0_MCR1REG_S0CH01 *((volatile uint8_t *)(0x42D80204UL)) +#define bFM_I2S0_MCR1REG_S0CH02 *((volatile uint8_t *)(0x42D80208UL)) +#define bFM4_I2S0_MCR1REG_S0CH02 *((volatile uint8_t *)(0x42D80208UL)) +#define bFM_I2S0_MCR1REG_S0CH03 *((volatile uint8_t *)(0x42D8020CUL)) +#define bFM4_I2S0_MCR1REG_S0CH03 *((volatile uint8_t *)(0x42D8020CUL)) +#define bFM_I2S0_MCR1REG_S0CH04 *((volatile uint8_t *)(0x42D80210UL)) +#define bFM4_I2S0_MCR1REG_S0CH04 *((volatile uint8_t *)(0x42D80210UL)) +#define bFM_I2S0_MCR1REG_S0CH05 *((volatile uint8_t *)(0x42D80214UL)) +#define bFM4_I2S0_MCR1REG_S0CH05 *((volatile uint8_t *)(0x42D80214UL)) +#define bFM_I2S0_MCR1REG_S0CH06 *((volatile uint8_t *)(0x42D80218UL)) +#define bFM4_I2S0_MCR1REG_S0CH06 *((volatile uint8_t *)(0x42D80218UL)) +#define bFM_I2S0_MCR1REG_S0CH07 *((volatile uint8_t *)(0x42D8021CUL)) +#define bFM4_I2S0_MCR1REG_S0CH07 *((volatile uint8_t *)(0x42D8021CUL)) +#define bFM_I2S0_MCR1REG_S0CH08 *((volatile uint8_t *)(0x42D80220UL)) +#define bFM4_I2S0_MCR1REG_S0CH08 *((volatile uint8_t *)(0x42D80220UL)) +#define bFM_I2S0_MCR1REG_S0CH09 *((volatile uint8_t *)(0x42D80224UL)) +#define bFM4_I2S0_MCR1REG_S0CH09 *((volatile uint8_t *)(0x42D80224UL)) +#define bFM_I2S0_MCR1REG_S0CH10 *((volatile uint8_t *)(0x42D80228UL)) +#define bFM4_I2S0_MCR1REG_S0CH10 *((volatile uint8_t *)(0x42D80228UL)) +#define bFM_I2S0_MCR1REG_S0CH11 *((volatile uint8_t *)(0x42D8022CUL)) +#define bFM4_I2S0_MCR1REG_S0CH11 *((volatile uint8_t *)(0x42D8022CUL)) +#define bFM_I2S0_MCR1REG_S0CH12 *((volatile uint8_t *)(0x42D80230UL)) +#define bFM4_I2S0_MCR1REG_S0CH12 *((volatile uint8_t *)(0x42D80230UL)) +#define bFM_I2S0_MCR1REG_S0CH13 *((volatile uint8_t *)(0x42D80234UL)) +#define bFM4_I2S0_MCR1REG_S0CH13 *((volatile uint8_t *)(0x42D80234UL)) +#define bFM_I2S0_MCR1REG_S0CH14 *((volatile uint8_t *)(0x42D80238UL)) +#define bFM4_I2S0_MCR1REG_S0CH14 *((volatile uint8_t *)(0x42D80238UL)) +#define bFM_I2S0_MCR1REG_S0CH15 *((volatile uint8_t *)(0x42D8023CUL)) +#define bFM4_I2S0_MCR1REG_S0CH15 *((volatile uint8_t *)(0x42D8023CUL)) +#define bFM_I2S0_MCR1REG_S0CH16 *((volatile uint8_t *)(0x42D80240UL)) +#define bFM4_I2S0_MCR1REG_S0CH16 *((volatile uint8_t *)(0x42D80240UL)) +#define bFM_I2S0_MCR1REG_S0CH17 *((volatile uint8_t *)(0x42D80244UL)) +#define bFM4_I2S0_MCR1REG_S0CH17 *((volatile uint8_t *)(0x42D80244UL)) +#define bFM_I2S0_MCR1REG_S0CH18 *((volatile uint8_t *)(0x42D80248UL)) +#define bFM4_I2S0_MCR1REG_S0CH18 *((volatile uint8_t *)(0x42D80248UL)) +#define bFM_I2S0_MCR1REG_S0CH19 *((volatile uint8_t *)(0x42D8024CUL)) +#define bFM4_I2S0_MCR1REG_S0CH19 *((volatile uint8_t *)(0x42D8024CUL)) +#define bFM_I2S0_MCR1REG_S0CH20 *((volatile uint8_t *)(0x42D80250UL)) +#define bFM4_I2S0_MCR1REG_S0CH20 *((volatile uint8_t *)(0x42D80250UL)) +#define bFM_I2S0_MCR1REG_S0CH21 *((volatile uint8_t *)(0x42D80254UL)) +#define bFM4_I2S0_MCR1REG_S0CH21 *((volatile uint8_t *)(0x42D80254UL)) +#define bFM_I2S0_MCR1REG_S0CH22 *((volatile uint8_t *)(0x42D80258UL)) +#define bFM4_I2S0_MCR1REG_S0CH22 *((volatile uint8_t *)(0x42D80258UL)) +#define bFM_I2S0_MCR1REG_S0CH23 *((volatile uint8_t *)(0x42D8025CUL)) +#define bFM4_I2S0_MCR1REG_S0CH23 *((volatile uint8_t *)(0x42D8025CUL)) +#define bFM_I2S0_MCR1REG_S0CH24 *((volatile uint8_t *)(0x42D80260UL)) +#define bFM4_I2S0_MCR1REG_S0CH24 *((volatile uint8_t *)(0x42D80260UL)) +#define bFM_I2S0_MCR1REG_S0CH25 *((volatile uint8_t *)(0x42D80264UL)) +#define bFM4_I2S0_MCR1REG_S0CH25 *((volatile uint8_t *)(0x42D80264UL)) +#define bFM_I2S0_MCR1REG_S0CH26 *((volatile uint8_t *)(0x42D80268UL)) +#define bFM4_I2S0_MCR1REG_S0CH26 *((volatile uint8_t *)(0x42D80268UL)) +#define bFM_I2S0_MCR1REG_S0CH27 *((volatile uint8_t *)(0x42D8026CUL)) +#define bFM4_I2S0_MCR1REG_S0CH27 *((volatile uint8_t *)(0x42D8026CUL)) +#define bFM_I2S0_MCR1REG_S0CH28 *((volatile uint8_t *)(0x42D80270UL)) +#define bFM4_I2S0_MCR1REG_S0CH28 *((volatile uint8_t *)(0x42D80270UL)) +#define bFM_I2S0_MCR1REG_S0CH29 *((volatile uint8_t *)(0x42D80274UL)) +#define bFM4_I2S0_MCR1REG_S0CH29 *((volatile uint8_t *)(0x42D80274UL)) +#define bFM_I2S0_MCR1REG_S0CH30 *((volatile uint8_t *)(0x42D80278UL)) +#define bFM4_I2S0_MCR1REG_S0CH30 *((volatile uint8_t *)(0x42D80278UL)) +#define bFM_I2S0_MCR1REG_S0CH31 *((volatile uint8_t *)(0x42D8027CUL)) +#define bFM4_I2S0_MCR1REG_S0CH31 *((volatile uint8_t *)(0x42D8027CUL)) + +#define bFM_I2S0_MCR2REG_S1CH00 *((volatile uint8_t *)(0x42D80280UL)) +#define bFM4_I2S0_MCR2REG_S1CH00 *((volatile uint8_t *)(0x42D80280UL)) +#define bFM_I2S0_MCR2REG_S1CH01 *((volatile uint8_t *)(0x42D80284UL)) +#define bFM4_I2S0_MCR2REG_S1CH01 *((volatile uint8_t *)(0x42D80284UL)) +#define bFM_I2S0_MCR2REG_S1CH02 *((volatile uint8_t *)(0x42D80288UL)) +#define bFM4_I2S0_MCR2REG_S1CH02 *((volatile uint8_t *)(0x42D80288UL)) +#define bFM_I2S0_MCR2REG_S1CH03 *((volatile uint8_t *)(0x42D8028CUL)) +#define bFM4_I2S0_MCR2REG_S1CH03 *((volatile uint8_t *)(0x42D8028CUL)) +#define bFM_I2S0_MCR2REG_S1CH04 *((volatile uint8_t *)(0x42D80290UL)) +#define bFM4_I2S0_MCR2REG_S1CH04 *((volatile uint8_t *)(0x42D80290UL)) +#define bFM_I2S0_MCR2REG_S1CH05 *((volatile uint8_t *)(0x42D80294UL)) +#define bFM4_I2S0_MCR2REG_S1CH05 *((volatile uint8_t *)(0x42D80294UL)) +#define bFM_I2S0_MCR2REG_S1CH06 *((volatile uint8_t *)(0x42D80298UL)) +#define bFM4_I2S0_MCR2REG_S1CH06 *((volatile uint8_t *)(0x42D80298UL)) +#define bFM_I2S0_MCR2REG_S1CH07 *((volatile uint8_t *)(0x42D8029CUL)) +#define bFM4_I2S0_MCR2REG_S1CH07 *((volatile uint8_t *)(0x42D8029CUL)) +#define bFM_I2S0_MCR2REG_S1CH08 *((volatile uint8_t *)(0x42D802A0UL)) +#define bFM4_I2S0_MCR2REG_S1CH08 *((volatile uint8_t *)(0x42D802A0UL)) +#define bFM_I2S0_MCR2REG_S1CH09 *((volatile uint8_t *)(0x42D802A4UL)) +#define bFM4_I2S0_MCR2REG_S1CH09 *((volatile uint8_t *)(0x42D802A4UL)) +#define bFM_I2S0_MCR2REG_S1CH10 *((volatile uint8_t *)(0x42D802A8UL)) +#define bFM4_I2S0_MCR2REG_S1CH10 *((volatile uint8_t *)(0x42D802A8UL)) +#define bFM_I2S0_MCR2REG_S1CH11 *((volatile uint8_t *)(0x42D802ACUL)) +#define bFM4_I2S0_MCR2REG_S1CH11 *((volatile uint8_t *)(0x42D802ACUL)) +#define bFM_I2S0_MCR2REG_S1CH12 *((volatile uint8_t *)(0x42D802B0UL)) +#define bFM4_I2S0_MCR2REG_S1CH12 *((volatile uint8_t *)(0x42D802B0UL)) +#define bFM_I2S0_MCR2REG_S1CH13 *((volatile uint8_t *)(0x42D802B4UL)) +#define bFM4_I2S0_MCR2REG_S1CH13 *((volatile uint8_t *)(0x42D802B4UL)) +#define bFM_I2S0_MCR2REG_S1CH14 *((volatile uint8_t *)(0x42D802B8UL)) +#define bFM4_I2S0_MCR2REG_S1CH14 *((volatile uint8_t *)(0x42D802B8UL)) +#define bFM_I2S0_MCR2REG_S1CH15 *((volatile uint8_t *)(0x42D802BCUL)) +#define bFM4_I2S0_MCR2REG_S1CH15 *((volatile uint8_t *)(0x42D802BCUL)) +#define bFM_I2S0_MCR2REG_S1CH16 *((volatile uint8_t *)(0x42D802C0UL)) +#define bFM4_I2S0_MCR2REG_S1CH16 *((volatile uint8_t *)(0x42D802C0UL)) +#define bFM_I2S0_MCR2REG_S1CH17 *((volatile uint8_t *)(0x42D802C4UL)) +#define bFM4_I2S0_MCR2REG_S1CH17 *((volatile uint8_t *)(0x42D802C4UL)) +#define bFM_I2S0_MCR2REG_S1CH18 *((volatile uint8_t *)(0x42D802C8UL)) +#define bFM4_I2S0_MCR2REG_S1CH18 *((volatile uint8_t *)(0x42D802C8UL)) +#define bFM_I2S0_MCR2REG_S1CH19 *((volatile uint8_t *)(0x42D802CCUL)) +#define bFM4_I2S0_MCR2REG_S1CH19 *((volatile uint8_t *)(0x42D802CCUL)) +#define bFM_I2S0_MCR2REG_S1CH20 *((volatile uint8_t *)(0x42D802D0UL)) +#define bFM4_I2S0_MCR2REG_S1CH20 *((volatile uint8_t *)(0x42D802D0UL)) +#define bFM_I2S0_MCR2REG_S1CH21 *((volatile uint8_t *)(0x42D802D4UL)) +#define bFM4_I2S0_MCR2REG_S1CH21 *((volatile uint8_t *)(0x42D802D4UL)) +#define bFM_I2S0_MCR2REG_S1CH22 *((volatile uint8_t *)(0x42D802D8UL)) +#define bFM4_I2S0_MCR2REG_S1CH22 *((volatile uint8_t *)(0x42D802D8UL)) +#define bFM_I2S0_MCR2REG_S1CH23 *((volatile uint8_t *)(0x42D802DCUL)) +#define bFM4_I2S0_MCR2REG_S1CH23 *((volatile uint8_t *)(0x42D802DCUL)) +#define bFM_I2S0_MCR2REG_S1CH24 *((volatile uint8_t *)(0x42D802E0UL)) +#define bFM4_I2S0_MCR2REG_S1CH24 *((volatile uint8_t *)(0x42D802E0UL)) +#define bFM_I2S0_MCR2REG_S1CH25 *((volatile uint8_t *)(0x42D802E4UL)) +#define bFM4_I2S0_MCR2REG_S1CH25 *((volatile uint8_t *)(0x42D802E4UL)) +#define bFM_I2S0_MCR2REG_S1CH26 *((volatile uint8_t *)(0x42D802E8UL)) +#define bFM4_I2S0_MCR2REG_S1CH26 *((volatile uint8_t *)(0x42D802E8UL)) +#define bFM_I2S0_MCR2REG_S1CH27 *((volatile uint8_t *)(0x42D802ECUL)) +#define bFM4_I2S0_MCR2REG_S1CH27 *((volatile uint8_t *)(0x42D802ECUL)) +#define bFM_I2S0_MCR2REG_S1CH28 *((volatile uint8_t *)(0x42D802F0UL)) +#define bFM4_I2S0_MCR2REG_S1CH28 *((volatile uint8_t *)(0x42D802F0UL)) +#define bFM_I2S0_MCR2REG_S1CH29 *((volatile uint8_t *)(0x42D802F4UL)) +#define bFM4_I2S0_MCR2REG_S1CH29 *((volatile uint8_t *)(0x42D802F4UL)) +#define bFM_I2S0_MCR2REG_S1CH30 *((volatile uint8_t *)(0x42D802F8UL)) +#define bFM4_I2S0_MCR2REG_S1CH30 *((volatile uint8_t *)(0x42D802F8UL)) +#define bFM_I2S0_MCR2REG_S1CH31 *((volatile uint8_t *)(0x42D802FCUL)) +#define bFM4_I2S0_MCR2REG_S1CH31 *((volatile uint8_t *)(0x42D802FCUL)) + +#define bFM_I2S0_OPRREG_START *((volatile uint8_t *)(0x42D80300UL)) +#define bFM4_I2S0_OPRREG_START *((volatile uint8_t *)(0x42D80300UL)) +#define bFM_I2S0_OPRREG_TXENB *((volatile uint8_t *)(0x42D80340UL)) +#define bFM4_I2S0_OPRREG_TXENB *((volatile uint8_t *)(0x42D80340UL)) +#define bFM_I2S0_OPRREG_RXENB *((volatile uint8_t *)(0x42D80360UL)) +#define bFM4_I2S0_OPRREG_RXENB *((volatile uint8_t *)(0x42D80360UL)) + +#define bFM_I2S0_SRST_SRST *((volatile uint8_t *)(0x42D80380UL)) +#define bFM4_I2S0_SRST_SRST *((volatile uint8_t *)(0x42D80380UL)) + +#define bFM_I2S0_STATUS_RXFI *((volatile uint8_t *)(0x42D804C0UL)) +#define bFM4_I2S0_STATUS_RXFI *((volatile uint8_t *)(0x42D804C0UL)) +#define bFM_I2S0_STATUS_TXFI *((volatile uint8_t *)(0x42D804C4UL)) +#define bFM4_I2S0_STATUS_TXFI *((volatile uint8_t *)(0x42D804C4UL)) +#define bFM_I2S0_STATUS_BSY *((volatile uint8_t *)(0x42D804C8UL)) +#define bFM4_I2S0_STATUS_BSY *((volatile uint8_t *)(0x42D804C8UL)) +#define bFM_I2S0_STATUS_EOPI *((volatile uint8_t *)(0x42D804CCUL)) +#define bFM4_I2S0_STATUS_EOPI *((volatile uint8_t *)(0x42D804CCUL)) +#define bFM_I2S0_STATUS_RXOVR *((volatile uint8_t *)(0x42D804E0UL)) +#define bFM4_I2S0_STATUS_RXOVR *((volatile uint8_t *)(0x42D804E0UL)) +#define bFM_I2S0_STATUS_RXUDR *((volatile uint8_t *)(0x42D804E4UL)) +#define bFM4_I2S0_STATUS_RXUDR *((volatile uint8_t *)(0x42D804E4UL)) +#define bFM_I2S0_STATUS_TXOVR *((volatile uint8_t *)(0x42D804E8UL)) +#define bFM4_I2S0_STATUS_TXOVR *((volatile uint8_t *)(0x42D804E8UL)) +#define bFM_I2S0_STATUS_TXUDR0 *((volatile uint8_t *)(0x42D804ECUL)) +#define bFM4_I2S0_STATUS_TXUDR0 *((volatile uint8_t *)(0x42D804ECUL)) +#define bFM_I2S0_STATUS_TXUDR1 *((volatile uint8_t *)(0x42D804F0UL)) +#define bFM4_I2S0_STATUS_TXUDR1 *((volatile uint8_t *)(0x42D804F0UL)) +#define bFM_I2S0_STATUS_FERR *((volatile uint8_t *)(0x42D804F4UL)) +#define bFM4_I2S0_STATUS_FERR *((volatile uint8_t *)(0x42D804F4UL)) +#define bFM_I2S0_STATUS_RBERR *((volatile uint8_t *)(0x42D804F8UL)) +#define bFM4_I2S0_STATUS_RBERR *((volatile uint8_t *)(0x42D804F8UL)) +#define bFM_I2S0_STATUS_TBERR *((volatile uint8_t *)(0x42D804FCUL)) +#define bFM4_I2S0_STATUS_TBERR *((volatile uint8_t *)(0x42D804FCUL)) + +#define bFM_I2S0_TSTREG_LBMD *((volatile uint8_t *)(0x42D80580UL)) +#define bFM4_I2S0_TSTREG_LBMD *((volatile uint8_t *)(0x42D80580UL)) + + +/******************************************************************************* +* I2SPRE Registers I2SPRE +* Bitband Section +*******************************************************************************/ +#define bFM_I2SPRE_ICCR_I2SEN *((volatile uint8_t *)(0x427A0000UL)) +#define bFM4_I2SPRE_ICCR_I2SEN *((volatile uint8_t *)(0x427A0000UL)) +#define bFM_I2SPRE_ICCR_ICSEL *((volatile uint8_t *)(0x427A0004UL)) +#define bFM4_I2SPRE_ICCR_ICSEL *((volatile uint8_t *)(0x427A0004UL)) + +#define bFM_I2SPRE_IP_STR_IPRDY *((volatile uint8_t *)(0x427A0280UL)) +#define bFM4_I2SPRE_IP_STR_IPRDY *((volatile uint8_t *)(0x427A0280UL)) + +#define bFM_I2SPRE_IPCR1_IPLLEN *((volatile uint8_t *)(0x427A0080UL)) +#define bFM4_I2SPRE_IPCR1_IPLLEN *((volatile uint8_t *)(0x427A0080UL)) + +#define bFM_I2SPRE_IPINT_CLR_IPCSC *((volatile uint8_t *)(0x427A0380UL)) +#define bFM4_I2SPRE_IPINT_CLR_IPCSC *((volatile uint8_t *)(0x427A0380UL)) + +#define bFM_I2SPRE_IPINT_ENR_IPCSE *((volatile uint8_t *)(0x427A0300UL)) +#define bFM4_I2SPRE_IPINT_ENR_IPCSE *((volatile uint8_t *)(0x427A0300UL)) + +#define bFM_I2SPRE_IPINT_STR_IPCSI *((volatile uint8_t *)(0x427A0400UL)) +#define bFM4_I2SPRE_IPINT_STR_IPCSI *((volatile uint8_t *)(0x427A0400UL)) + + +/******************************************************************************* +* INTREQ Registers INTREQ +* Bitband Section +*******************************************************************************/ +#define bFM_INTREQ_DRQSEL_USBEP1 *((volatile uint8_t *)(0x42620000UL)) +#define bFM4_INTREQ_DRQSEL_USBEP1 *((volatile uint8_t *)(0x42620000UL)) +#define bFM_INTREQ_DRQSEL_USBEP2 *((volatile uint8_t *)(0x42620004UL)) +#define bFM4_INTREQ_DRQSEL_USBEP2 *((volatile uint8_t *)(0x42620004UL)) +#define bFM_INTREQ_DRQSEL_USBEP3 *((volatile uint8_t *)(0x42620008UL)) +#define bFM4_INTREQ_DRQSEL_USBEP3 *((volatile uint8_t *)(0x42620008UL)) +#define bFM_INTREQ_DRQSEL_USBEP4 *((volatile uint8_t *)(0x4262000CUL)) +#define bFM4_INTREQ_DRQSEL_USBEP4 *((volatile uint8_t *)(0x4262000CUL)) +#define bFM_INTREQ_DRQSEL_USBEP5 *((volatile uint8_t *)(0x42620010UL)) +#define bFM4_INTREQ_DRQSEL_USBEP5 *((volatile uint8_t *)(0x42620010UL)) +#define bFM_INTREQ_DRQSEL_ADCSCAN0 *((volatile uint8_t *)(0x42620014UL)) +#define bFM4_INTREQ_DRQSEL_ADCSCAN0 *((volatile uint8_t *)(0x42620014UL)) +#define bFM_INTREQ_DRQSEL_ADCSCAN1 *((volatile uint8_t *)(0x42620018UL)) +#define bFM4_INTREQ_DRQSEL_ADCSCAN1 *((volatile uint8_t *)(0x42620018UL)) +#define bFM_INTREQ_DRQSEL_ADCSCAN2 *((volatile uint8_t *)(0x4262001CUL)) +#define bFM4_INTREQ_DRQSEL_ADCSCAN2 *((volatile uint8_t *)(0x4262001CUL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT0 *((volatile uint8_t *)(0x42620020UL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT0 *((volatile uint8_t *)(0x42620020UL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT2 *((volatile uint8_t *)(0x42620024UL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT2 *((volatile uint8_t *)(0x42620024UL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT4 *((volatile uint8_t *)(0x42620028UL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT4 *((volatile uint8_t *)(0x42620028UL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT6 *((volatile uint8_t *)(0x4262002CUL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT6 *((volatile uint8_t *)(0x4262002CUL)) +#define bFM_INTREQ_DRQSEL_MFS0RX *((volatile uint8_t *)(0x42620030UL)) +#define bFM4_INTREQ_DRQSEL_MFS0RX *((volatile uint8_t *)(0x42620030UL)) +#define bFM_INTREQ_DRQSEL_MFS0TX *((volatile uint8_t *)(0x42620034UL)) +#define bFM4_INTREQ_DRQSEL_MFS0TX *((volatile uint8_t *)(0x42620034UL)) +#define bFM_INTREQ_DRQSEL_MFS1RX *((volatile uint8_t *)(0x42620038UL)) +#define bFM4_INTREQ_DRQSEL_MFS1RX *((volatile uint8_t *)(0x42620038UL)) +#define bFM_INTREQ_DRQSEL_MFS1TX *((volatile uint8_t *)(0x4262003CUL)) +#define bFM4_INTREQ_DRQSEL_MFS1TX *((volatile uint8_t *)(0x4262003CUL)) +#define bFM_INTREQ_DRQSEL_MFS2RX *((volatile uint8_t *)(0x42620040UL)) +#define bFM4_INTREQ_DRQSEL_MFS2RX *((volatile uint8_t *)(0x42620040UL)) +#define bFM_INTREQ_DRQSEL_MFS2TX *((volatile uint8_t *)(0x42620044UL)) +#define bFM4_INTREQ_DRQSEL_MFS2TX *((volatile uint8_t *)(0x42620044UL)) +#define bFM_INTREQ_DRQSEL_MFS3RX *((volatile uint8_t *)(0x42620048UL)) +#define bFM4_INTREQ_DRQSEL_MFS3RX *((volatile uint8_t *)(0x42620048UL)) +#define bFM_INTREQ_DRQSEL_MFS3TX *((volatile uint8_t *)(0x4262004CUL)) +#define bFM4_INTREQ_DRQSEL_MFS3TX *((volatile uint8_t *)(0x4262004CUL)) +#define bFM_INTREQ_DRQSEL_MFS4RX *((volatile uint8_t *)(0x42620050UL)) +#define bFM4_INTREQ_DRQSEL_MFS4RX *((volatile uint8_t *)(0x42620050UL)) +#define bFM_INTREQ_DRQSEL_MFS4TX *((volatile uint8_t *)(0x42620054UL)) +#define bFM4_INTREQ_DRQSEL_MFS4TX *((volatile uint8_t *)(0x42620054UL)) +#define bFM_INTREQ_DRQSEL_MFS5RX *((volatile uint8_t *)(0x42620058UL)) +#define bFM4_INTREQ_DRQSEL_MFS5RX *((volatile uint8_t *)(0x42620058UL)) +#define bFM_INTREQ_DRQSEL_MFS5TX *((volatile uint8_t *)(0x4262005CUL)) +#define bFM4_INTREQ_DRQSEL_MFS5TX *((volatile uint8_t *)(0x4262005CUL)) +#define bFM_INTREQ_DRQSEL_MFS6RX *((volatile uint8_t *)(0x42620060UL)) +#define bFM4_INTREQ_DRQSEL_MFS6RX *((volatile uint8_t *)(0x42620060UL)) +#define bFM_INTREQ_DRQSEL_MFS6TX *((volatile uint8_t *)(0x42620064UL)) +#define bFM4_INTREQ_DRQSEL_MFS6TX *((volatile uint8_t *)(0x42620064UL)) +#define bFM_INTREQ_DRQSEL_MFS7RX *((volatile uint8_t *)(0x42620068UL)) +#define bFM4_INTREQ_DRQSEL_MFS7RX *((volatile uint8_t *)(0x42620068UL)) +#define bFM_INTREQ_DRQSEL_MFS7TX *((volatile uint8_t *)(0x4262006CUL)) +#define bFM4_INTREQ_DRQSEL_MFS7TX *((volatile uint8_t *)(0x4262006CUL)) +#define bFM_INTREQ_DRQSEL_EXINT0 *((volatile uint8_t *)(0x42620070UL)) +#define bFM4_INTREQ_DRQSEL_EXINT0 *((volatile uint8_t *)(0x42620070UL)) +#define bFM_INTREQ_DRQSEL_EXINT1 *((volatile uint8_t *)(0x42620074UL)) +#define bFM4_INTREQ_DRQSEL_EXINT1 *((volatile uint8_t *)(0x42620074UL)) +#define bFM_INTREQ_DRQSEL_EXINT2 *((volatile uint8_t *)(0x42620078UL)) +#define bFM4_INTREQ_DRQSEL_EXINT2 *((volatile uint8_t *)(0x42620078UL)) +#define bFM_INTREQ_DRQSEL_EXINT3 *((volatile uint8_t *)(0x4262007CUL)) +#define bFM4_INTREQ_DRQSEL_EXINT3 *((volatile uint8_t *)(0x4262007CUL)) + +#define bFM_INTREQ_EXC02MON_NMI *((volatile uint8_t *)(0x42624000UL)) +#define bFM4_INTREQ_EXC02MON_NMI *((volatile uint8_t *)(0x42624000UL)) +#define bFM_INTREQ_EXC02MON_HWINT *((volatile uint8_t *)(0x42624004UL)) +#define bFM4_INTREQ_EXC02MON_HWINT *((volatile uint8_t *)(0x42624004UL)) + +#define bFM_INTREQ_IRQ000MON_FCSINT *((volatile uint8_t *)(0x42624080UL)) +#define bFM4_INTREQ_IRQ000MON_FCSINT *((volatile uint8_t *)(0x42624080UL)) + +#define bFM_INTREQ_IRQ001MON_SWWDTINT *((volatile uint8_t *)(0x42624100UL)) +#define bFM4_INTREQ_IRQ001MON_SWWDTINT *((volatile uint8_t *)(0x42624100UL)) + +#define bFM_INTREQ_IRQ002MON_LVDINT *((volatile uint8_t *)(0x42624180UL)) +#define bFM4_INTREQ_IRQ002MON_LVDINT *((volatile uint8_t *)(0x42624180UL)) + +#define bFM_INTREQ_IRQ003MON_IRQBIT0 *((volatile uint8_t *)(0x42624200UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT0 *((volatile uint8_t *)(0x42624200UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT1 *((volatile uint8_t *)(0x42624204UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT1 *((volatile uint8_t *)(0x42624204UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT2 *((volatile uint8_t *)(0x42624208UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT2 *((volatile uint8_t *)(0x42624208UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT3 *((volatile uint8_t *)(0x4262420CUL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT3 *((volatile uint8_t *)(0x4262420CUL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT4 *((volatile uint8_t *)(0x42624210UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT4 *((volatile uint8_t *)(0x42624210UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT5 *((volatile uint8_t *)(0x42624214UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT5 *((volatile uint8_t *)(0x42624214UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT6 *((volatile uint8_t *)(0x42624218UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT6 *((volatile uint8_t *)(0x42624218UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT7 *((volatile uint8_t *)(0x4262421CUL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT7 *((volatile uint8_t *)(0x4262421CUL)) + +#define bFM_INTREQ_IRQ003SEL_SELBIT0 *((volatile uint8_t *)(0x42622240UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT0 *((volatile uint8_t *)(0x42622240UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT1 *((volatile uint8_t *)(0x42622244UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT1 *((volatile uint8_t *)(0x42622244UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT2 *((volatile uint8_t *)(0x42622248UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT2 *((volatile uint8_t *)(0x42622248UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT3 *((volatile uint8_t *)(0x4262224CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT3 *((volatile uint8_t *)(0x4262224CUL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT4 *((volatile uint8_t *)(0x42622250UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT4 *((volatile uint8_t *)(0x42622250UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT5 *((volatile uint8_t *)(0x42622254UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT5 *((volatile uint8_t *)(0x42622254UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT6 *((volatile uint8_t *)(0x42622258UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT6 *((volatile uint8_t *)(0x42622258UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT7 *((volatile uint8_t *)(0x4262225CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT7 *((volatile uint8_t *)(0x4262225CUL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT8 *((volatile uint8_t *)(0x42622260UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT8 *((volatile uint8_t *)(0x42622260UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT9 *((volatile uint8_t *)(0x42622264UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT9 *((volatile uint8_t *)(0x42622264UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT10 *((volatile uint8_t *)(0x42622268UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT10 *((volatile uint8_t *)(0x42622268UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT11 *((volatile uint8_t *)(0x4262226CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT11 *((volatile uint8_t *)(0x4262226CUL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT12 *((volatile uint8_t *)(0x42622270UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT12 *((volatile uint8_t *)(0x42622270UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT13 *((volatile uint8_t *)(0x42622274UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT13 *((volatile uint8_t *)(0x42622274UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT14 *((volatile uint8_t *)(0x42622278UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT14 *((volatile uint8_t *)(0x42622278UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT15 *((volatile uint8_t *)(0x4262227CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT15 *((volatile uint8_t *)(0x4262227CUL)) + +#define bFM_INTREQ_IRQ004MON_IRQBIT0 *((volatile uint8_t *)(0x42624280UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT0 *((volatile uint8_t *)(0x42624280UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT1 *((volatile uint8_t *)(0x42624284UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT1 *((volatile uint8_t *)(0x42624284UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT2 *((volatile uint8_t *)(0x42624288UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT2 *((volatile uint8_t *)(0x42624288UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT3 *((volatile uint8_t *)(0x4262428CUL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT3 *((volatile uint8_t *)(0x4262428CUL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT4 *((volatile uint8_t *)(0x42624290UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT4 *((volatile uint8_t *)(0x42624290UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT5 *((volatile uint8_t *)(0x42624294UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT5 *((volatile uint8_t *)(0x42624294UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT6 *((volatile uint8_t *)(0x42624298UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT6 *((volatile uint8_t *)(0x42624298UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT7 *((volatile uint8_t *)(0x4262429CUL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT7 *((volatile uint8_t *)(0x4262429CUL)) + +#define bFM_INTREQ_IRQ004SEL_SELBIT0 *((volatile uint8_t *)(0x426222C0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT0 *((volatile uint8_t *)(0x426222C0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT1 *((volatile uint8_t *)(0x426222C4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT1 *((volatile uint8_t *)(0x426222C4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT2 *((volatile uint8_t *)(0x426222C8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT2 *((volatile uint8_t *)(0x426222C8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT3 *((volatile uint8_t *)(0x426222CCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT3 *((volatile uint8_t *)(0x426222CCUL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT4 *((volatile uint8_t *)(0x426222D0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT4 *((volatile uint8_t *)(0x426222D0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT5 *((volatile uint8_t *)(0x426222D4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT5 *((volatile uint8_t *)(0x426222D4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT6 *((volatile uint8_t *)(0x426222D8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT6 *((volatile uint8_t *)(0x426222D8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT7 *((volatile uint8_t *)(0x426222DCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT7 *((volatile uint8_t *)(0x426222DCUL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT8 *((volatile uint8_t *)(0x426222E0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT8 *((volatile uint8_t *)(0x426222E0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT9 *((volatile uint8_t *)(0x426222E4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT9 *((volatile uint8_t *)(0x426222E4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT10 *((volatile uint8_t *)(0x426222E8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT10 *((volatile uint8_t *)(0x426222E8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT11 *((volatile uint8_t *)(0x426222ECUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT11 *((volatile uint8_t *)(0x426222ECUL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT12 *((volatile uint8_t *)(0x426222F0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT12 *((volatile uint8_t *)(0x426222F0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT13 *((volatile uint8_t *)(0x426222F4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT13 *((volatile uint8_t *)(0x426222F4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT14 *((volatile uint8_t *)(0x426222F8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT14 *((volatile uint8_t *)(0x426222F8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT15 *((volatile uint8_t *)(0x426222FCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT15 *((volatile uint8_t *)(0x426222FCUL)) + +#define bFM_INTREQ_IRQ005MON_IRQBIT0 *((volatile uint8_t *)(0x42624300UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT0 *((volatile uint8_t *)(0x42624300UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT1 *((volatile uint8_t *)(0x42624304UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT1 *((volatile uint8_t *)(0x42624304UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT2 *((volatile uint8_t *)(0x42624308UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT2 *((volatile uint8_t *)(0x42624308UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT3 *((volatile uint8_t *)(0x4262430CUL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT3 *((volatile uint8_t *)(0x4262430CUL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT4 *((volatile uint8_t *)(0x42624310UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT4 *((volatile uint8_t *)(0x42624310UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT5 *((volatile uint8_t *)(0x42624314UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT5 *((volatile uint8_t *)(0x42624314UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT6 *((volatile uint8_t *)(0x42624318UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT6 *((volatile uint8_t *)(0x42624318UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT7 *((volatile uint8_t *)(0x4262431CUL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT7 *((volatile uint8_t *)(0x4262431CUL)) + +#define bFM_INTREQ_IRQ005SEL_SELBIT0 *((volatile uint8_t *)(0x42622340UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT0 *((volatile uint8_t *)(0x42622340UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT1 *((volatile uint8_t *)(0x42622344UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT1 *((volatile uint8_t *)(0x42622344UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT2 *((volatile uint8_t *)(0x42622348UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT2 *((volatile uint8_t *)(0x42622348UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT3 *((volatile uint8_t *)(0x4262234CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT3 *((volatile uint8_t *)(0x4262234CUL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT4 *((volatile uint8_t *)(0x42622350UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT4 *((volatile uint8_t *)(0x42622350UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT5 *((volatile uint8_t *)(0x42622354UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT5 *((volatile uint8_t *)(0x42622354UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT6 *((volatile uint8_t *)(0x42622358UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT6 *((volatile uint8_t *)(0x42622358UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT7 *((volatile uint8_t *)(0x4262235CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT7 *((volatile uint8_t *)(0x4262235CUL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT8 *((volatile uint8_t *)(0x42622360UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT8 *((volatile uint8_t *)(0x42622360UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT9 *((volatile uint8_t *)(0x42622364UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT9 *((volatile uint8_t *)(0x42622364UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT10 *((volatile uint8_t *)(0x42622368UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT10 *((volatile uint8_t *)(0x42622368UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT11 *((volatile uint8_t *)(0x4262236CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT11 *((volatile uint8_t *)(0x4262236CUL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT12 *((volatile uint8_t *)(0x42622370UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT12 *((volatile uint8_t *)(0x42622370UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT13 *((volatile uint8_t *)(0x42622374UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT13 *((volatile uint8_t *)(0x42622374UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT14 *((volatile uint8_t *)(0x42622378UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT14 *((volatile uint8_t *)(0x42622378UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT15 *((volatile uint8_t *)(0x4262237CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT15 *((volatile uint8_t *)(0x4262237CUL)) + +#define bFM_INTREQ_IRQ006MON_IRQBIT0 *((volatile uint8_t *)(0x42624380UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT0 *((volatile uint8_t *)(0x42624380UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT1 *((volatile uint8_t *)(0x42624384UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT1 *((volatile uint8_t *)(0x42624384UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT2 *((volatile uint8_t *)(0x42624388UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT2 *((volatile uint8_t *)(0x42624388UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT3 *((volatile uint8_t *)(0x4262438CUL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT3 *((volatile uint8_t *)(0x4262438CUL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT4 *((volatile uint8_t *)(0x42624390UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT4 *((volatile uint8_t *)(0x42624390UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT5 *((volatile uint8_t *)(0x42624394UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT5 *((volatile uint8_t *)(0x42624394UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT6 *((volatile uint8_t *)(0x42624398UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT6 *((volatile uint8_t *)(0x42624398UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT7 *((volatile uint8_t *)(0x4262439CUL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT7 *((volatile uint8_t *)(0x4262439CUL)) + +#define bFM_INTREQ_IRQ006SEL_SELBIT0 *((volatile uint8_t *)(0x426223C0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT0 *((volatile uint8_t *)(0x426223C0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT1 *((volatile uint8_t *)(0x426223C4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT1 *((volatile uint8_t *)(0x426223C4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT2 *((volatile uint8_t *)(0x426223C8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT2 *((volatile uint8_t *)(0x426223C8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT3 *((volatile uint8_t *)(0x426223CCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT3 *((volatile uint8_t *)(0x426223CCUL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT4 *((volatile uint8_t *)(0x426223D0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT4 *((volatile uint8_t *)(0x426223D0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT5 *((volatile uint8_t *)(0x426223D4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT5 *((volatile uint8_t *)(0x426223D4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT6 *((volatile uint8_t *)(0x426223D8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT6 *((volatile uint8_t *)(0x426223D8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT7 *((volatile uint8_t *)(0x426223DCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT7 *((volatile uint8_t *)(0x426223DCUL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT8 *((volatile uint8_t *)(0x426223E0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT8 *((volatile uint8_t *)(0x426223E0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT9 *((volatile uint8_t *)(0x426223E4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT9 *((volatile uint8_t *)(0x426223E4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT10 *((volatile uint8_t *)(0x426223E8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT10 *((volatile uint8_t *)(0x426223E8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT11 *((volatile uint8_t *)(0x426223ECUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT11 *((volatile uint8_t *)(0x426223ECUL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT12 *((volatile uint8_t *)(0x426223F0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT12 *((volatile uint8_t *)(0x426223F0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT13 *((volatile uint8_t *)(0x426223F4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT13 *((volatile uint8_t *)(0x426223F4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT14 *((volatile uint8_t *)(0x426223F8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT14 *((volatile uint8_t *)(0x426223F8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT15 *((volatile uint8_t *)(0x426223FCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT15 *((volatile uint8_t *)(0x426223FCUL)) + +#define bFM_INTREQ_IRQ007MON_IRQBIT0 *((volatile uint8_t *)(0x42624400UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT0 *((volatile uint8_t *)(0x42624400UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT1 *((volatile uint8_t *)(0x42624404UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT1 *((volatile uint8_t *)(0x42624404UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT2 *((volatile uint8_t *)(0x42624408UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT2 *((volatile uint8_t *)(0x42624408UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT3 *((volatile uint8_t *)(0x4262440CUL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT3 *((volatile uint8_t *)(0x4262440CUL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT4 *((volatile uint8_t *)(0x42624410UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT4 *((volatile uint8_t *)(0x42624410UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT5 *((volatile uint8_t *)(0x42624414UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT5 *((volatile uint8_t *)(0x42624414UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT6 *((volatile uint8_t *)(0x42624418UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT6 *((volatile uint8_t *)(0x42624418UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT7 *((volatile uint8_t *)(0x4262441CUL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT7 *((volatile uint8_t *)(0x4262441CUL)) + +#define bFM_INTREQ_IRQ007SEL_SELBIT0 *((volatile uint8_t *)(0x42622440UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT0 *((volatile uint8_t *)(0x42622440UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT1 *((volatile uint8_t *)(0x42622444UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT1 *((volatile uint8_t *)(0x42622444UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT2 *((volatile uint8_t *)(0x42622448UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT2 *((volatile uint8_t *)(0x42622448UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT3 *((volatile uint8_t *)(0x4262244CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT3 *((volatile uint8_t *)(0x4262244CUL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT4 *((volatile uint8_t *)(0x42622450UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT4 *((volatile uint8_t *)(0x42622450UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT5 *((volatile uint8_t *)(0x42622454UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT5 *((volatile uint8_t *)(0x42622454UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT6 *((volatile uint8_t *)(0x42622458UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT6 *((volatile uint8_t *)(0x42622458UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT7 *((volatile uint8_t *)(0x4262245CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT7 *((volatile uint8_t *)(0x4262245CUL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT8 *((volatile uint8_t *)(0x42622460UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT8 *((volatile uint8_t *)(0x42622460UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT9 *((volatile uint8_t *)(0x42622464UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT9 *((volatile uint8_t *)(0x42622464UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT10 *((volatile uint8_t *)(0x42622468UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT10 *((volatile uint8_t *)(0x42622468UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT11 *((volatile uint8_t *)(0x4262246CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT11 *((volatile uint8_t *)(0x4262246CUL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT12 *((volatile uint8_t *)(0x42622470UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT12 *((volatile uint8_t *)(0x42622470UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT13 *((volatile uint8_t *)(0x42622474UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT13 *((volatile uint8_t *)(0x42622474UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT14 *((volatile uint8_t *)(0x42622478UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT14 *((volatile uint8_t *)(0x42622478UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT15 *((volatile uint8_t *)(0x4262247CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT15 *((volatile uint8_t *)(0x4262247CUL)) + +#define bFM_INTREQ_IRQ008MON_IRQBIT0 *((volatile uint8_t *)(0x42624480UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT0 *((volatile uint8_t *)(0x42624480UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT1 *((volatile uint8_t *)(0x42624484UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT1 *((volatile uint8_t *)(0x42624484UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT2 *((volatile uint8_t *)(0x42624488UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT2 *((volatile uint8_t *)(0x42624488UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT3 *((volatile uint8_t *)(0x4262448CUL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT3 *((volatile uint8_t *)(0x4262448CUL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT4 *((volatile uint8_t *)(0x42624490UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT4 *((volatile uint8_t *)(0x42624490UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT5 *((volatile uint8_t *)(0x42624494UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT5 *((volatile uint8_t *)(0x42624494UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT6 *((volatile uint8_t *)(0x42624498UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT6 *((volatile uint8_t *)(0x42624498UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT7 *((volatile uint8_t *)(0x4262449CUL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT7 *((volatile uint8_t *)(0x4262449CUL)) + +#define bFM_INTREQ_IRQ008SEL_SELBIT0 *((volatile uint8_t *)(0x426224C0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT0 *((volatile uint8_t *)(0x426224C0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT1 *((volatile uint8_t *)(0x426224C4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT1 *((volatile uint8_t *)(0x426224C4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT2 *((volatile uint8_t *)(0x426224C8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT2 *((volatile uint8_t *)(0x426224C8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT3 *((volatile uint8_t *)(0x426224CCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT3 *((volatile uint8_t *)(0x426224CCUL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT4 *((volatile uint8_t *)(0x426224D0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT4 *((volatile uint8_t *)(0x426224D0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT5 *((volatile uint8_t *)(0x426224D4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT5 *((volatile uint8_t *)(0x426224D4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT6 *((volatile uint8_t *)(0x426224D8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT6 *((volatile uint8_t *)(0x426224D8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT7 *((volatile uint8_t *)(0x426224DCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT7 *((volatile uint8_t *)(0x426224DCUL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT8 *((volatile uint8_t *)(0x426224E0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT8 *((volatile uint8_t *)(0x426224E0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT9 *((volatile uint8_t *)(0x426224E4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT9 *((volatile uint8_t *)(0x426224E4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT10 *((volatile uint8_t *)(0x426224E8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT10 *((volatile uint8_t *)(0x426224E8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT11 *((volatile uint8_t *)(0x426224ECUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT11 *((volatile uint8_t *)(0x426224ECUL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT12 *((volatile uint8_t *)(0x426224F0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT12 *((volatile uint8_t *)(0x426224F0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT13 *((volatile uint8_t *)(0x426224F4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT13 *((volatile uint8_t *)(0x426224F4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT14 *((volatile uint8_t *)(0x426224F8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT14 *((volatile uint8_t *)(0x426224F8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT15 *((volatile uint8_t *)(0x426224FCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT15 *((volatile uint8_t *)(0x426224FCUL)) + +#define bFM_INTREQ_IRQ009MON_IRQBIT0 *((volatile uint8_t *)(0x42624500UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT0 *((volatile uint8_t *)(0x42624500UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT1 *((volatile uint8_t *)(0x42624504UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT1 *((volatile uint8_t *)(0x42624504UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT2 *((volatile uint8_t *)(0x42624508UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT2 *((volatile uint8_t *)(0x42624508UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT3 *((volatile uint8_t *)(0x4262450CUL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT3 *((volatile uint8_t *)(0x4262450CUL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT4 *((volatile uint8_t *)(0x42624510UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT4 *((volatile uint8_t *)(0x42624510UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT5 *((volatile uint8_t *)(0x42624514UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT5 *((volatile uint8_t *)(0x42624514UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT6 *((volatile uint8_t *)(0x42624518UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT6 *((volatile uint8_t *)(0x42624518UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT7 *((volatile uint8_t *)(0x4262451CUL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT7 *((volatile uint8_t *)(0x4262451CUL)) + +#define bFM_INTREQ_IRQ009SEL_SELBIT0 *((volatile uint8_t *)(0x42622540UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT0 *((volatile uint8_t *)(0x42622540UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT1 *((volatile uint8_t *)(0x42622544UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT1 *((volatile uint8_t *)(0x42622544UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT2 *((volatile uint8_t *)(0x42622548UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT2 *((volatile uint8_t *)(0x42622548UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT3 *((volatile uint8_t *)(0x4262254CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT3 *((volatile uint8_t *)(0x4262254CUL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT4 *((volatile uint8_t *)(0x42622550UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT4 *((volatile uint8_t *)(0x42622550UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT5 *((volatile uint8_t *)(0x42622554UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT5 *((volatile uint8_t *)(0x42622554UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT6 *((volatile uint8_t *)(0x42622558UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT6 *((volatile uint8_t *)(0x42622558UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT7 *((volatile uint8_t *)(0x4262255CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT7 *((volatile uint8_t *)(0x4262255CUL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT8 *((volatile uint8_t *)(0x42622560UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT8 *((volatile uint8_t *)(0x42622560UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT9 *((volatile uint8_t *)(0x42622564UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT9 *((volatile uint8_t *)(0x42622564UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT10 *((volatile uint8_t *)(0x42622568UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT10 *((volatile uint8_t *)(0x42622568UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT11 *((volatile uint8_t *)(0x4262256CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT11 *((volatile uint8_t *)(0x4262256CUL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT12 *((volatile uint8_t *)(0x42622570UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT12 *((volatile uint8_t *)(0x42622570UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT13 *((volatile uint8_t *)(0x42622574UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT13 *((volatile uint8_t *)(0x42622574UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT14 *((volatile uint8_t *)(0x42622578UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT14 *((volatile uint8_t *)(0x42622578UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT15 *((volatile uint8_t *)(0x4262257CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT15 *((volatile uint8_t *)(0x4262257CUL)) + +#define bFM_INTREQ_IRQ010MON_IRQBIT0 *((volatile uint8_t *)(0x42624580UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT0 *((volatile uint8_t *)(0x42624580UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT1 *((volatile uint8_t *)(0x42624584UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT1 *((volatile uint8_t *)(0x42624584UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT2 *((volatile uint8_t *)(0x42624588UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT2 *((volatile uint8_t *)(0x42624588UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT3 *((volatile uint8_t *)(0x4262458CUL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT3 *((volatile uint8_t *)(0x4262458CUL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT4 *((volatile uint8_t *)(0x42624590UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT4 *((volatile uint8_t *)(0x42624590UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT5 *((volatile uint8_t *)(0x42624594UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT5 *((volatile uint8_t *)(0x42624594UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT6 *((volatile uint8_t *)(0x42624598UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT6 *((volatile uint8_t *)(0x42624598UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT7 *((volatile uint8_t *)(0x4262459CUL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT7 *((volatile uint8_t *)(0x4262459CUL)) + +#define bFM_INTREQ_IRQ010SEL_SELBIT0 *((volatile uint8_t *)(0x426225C0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT0 *((volatile uint8_t *)(0x426225C0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT1 *((volatile uint8_t *)(0x426225C4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT1 *((volatile uint8_t *)(0x426225C4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT2 *((volatile uint8_t *)(0x426225C8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT2 *((volatile uint8_t *)(0x426225C8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT3 *((volatile uint8_t *)(0x426225CCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT3 *((volatile uint8_t *)(0x426225CCUL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT4 *((volatile uint8_t *)(0x426225D0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT4 *((volatile uint8_t *)(0x426225D0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT5 *((volatile uint8_t *)(0x426225D4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT5 *((volatile uint8_t *)(0x426225D4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT6 *((volatile uint8_t *)(0x426225D8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT6 *((volatile uint8_t *)(0x426225D8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT7 *((volatile uint8_t *)(0x426225DCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT7 *((volatile uint8_t *)(0x426225DCUL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT8 *((volatile uint8_t *)(0x426225E0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT8 *((volatile uint8_t *)(0x426225E0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT9 *((volatile uint8_t *)(0x426225E4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT9 *((volatile uint8_t *)(0x426225E4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT10 *((volatile uint8_t *)(0x426225E8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT10 *((volatile uint8_t *)(0x426225E8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT11 *((volatile uint8_t *)(0x426225ECUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT11 *((volatile uint8_t *)(0x426225ECUL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT12 *((volatile uint8_t *)(0x426225F0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT12 *((volatile uint8_t *)(0x426225F0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT13 *((volatile uint8_t *)(0x426225F4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT13 *((volatile uint8_t *)(0x426225F4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT14 *((volatile uint8_t *)(0x426225F8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT14 *((volatile uint8_t *)(0x426225F8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT15 *((volatile uint8_t *)(0x426225FCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT15 *((volatile uint8_t *)(0x426225FCUL)) + +#define bFM_INTREQ_IRQ011MON_EXTINT *((volatile uint8_t *)(0x42624600UL)) +#define bFM4_INTREQ_IRQ011MON_EXTINT *((volatile uint8_t *)(0x42624600UL)) + +#define bFM_INTREQ_IRQ012MON_EXTINT *((volatile uint8_t *)(0x42624680UL)) +#define bFM4_INTREQ_IRQ012MON_EXTINT *((volatile uint8_t *)(0x42624680UL)) + +#define bFM_INTREQ_IRQ013MON_EXTINT *((volatile uint8_t *)(0x42624700UL)) +#define bFM4_INTREQ_IRQ013MON_EXTINT *((volatile uint8_t *)(0x42624700UL)) + +#define bFM_INTREQ_IRQ014MON_EXTINT *((volatile uint8_t *)(0x42624780UL)) +#define bFM4_INTREQ_IRQ014MON_EXTINT *((volatile uint8_t *)(0x42624780UL)) + +#define bFM_INTREQ_IRQ015MON_EXTINT *((volatile uint8_t *)(0x42624800UL)) +#define bFM4_INTREQ_IRQ015MON_EXTINT *((volatile uint8_t *)(0x42624800UL)) + +#define bFM_INTREQ_IRQ016MON_EXTINT *((volatile uint8_t *)(0x42624880UL)) +#define bFM4_INTREQ_IRQ016MON_EXTINT *((volatile uint8_t *)(0x42624880UL)) + +#define bFM_INTREQ_IRQ017MON_EXTINT *((volatile uint8_t *)(0x42624900UL)) +#define bFM4_INTREQ_IRQ017MON_EXTINT *((volatile uint8_t *)(0x42624900UL)) + +#define bFM_INTREQ_IRQ018MON_EXTINT *((volatile uint8_t *)(0x42624980UL)) +#define bFM4_INTREQ_IRQ018MON_EXTINT *((volatile uint8_t *)(0x42624980UL)) + +#define bFM_INTREQ_IRQ019MON_QPRCINT0 *((volatile uint8_t *)(0x42624A00UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT0 *((volatile uint8_t *)(0x42624A00UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT1 *((volatile uint8_t *)(0x42624A04UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT1 *((volatile uint8_t *)(0x42624A04UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT2 *((volatile uint8_t *)(0x42624A08UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT2 *((volatile uint8_t *)(0x42624A08UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT3 *((volatile uint8_t *)(0x42624A0CUL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT3 *((volatile uint8_t *)(0x42624A0CUL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT4 *((volatile uint8_t *)(0x42624A10UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT4 *((volatile uint8_t *)(0x42624A10UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT5 *((volatile uint8_t *)(0x42624A14UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT5 *((volatile uint8_t *)(0x42624A14UL)) + +#define bFM_INTREQ_IRQ020MON_QPRCINT0 *((volatile uint8_t *)(0x42624A80UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT0 *((volatile uint8_t *)(0x42624A80UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT1 *((volatile uint8_t *)(0x42624A84UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT1 *((volatile uint8_t *)(0x42624A84UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT2 *((volatile uint8_t *)(0x42624A88UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT2 *((volatile uint8_t *)(0x42624A88UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT3 *((volatile uint8_t *)(0x42624A8CUL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT3 *((volatile uint8_t *)(0x42624A8CUL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT4 *((volatile uint8_t *)(0x42624A90UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT4 *((volatile uint8_t *)(0x42624A90UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT5 *((volatile uint8_t *)(0x42624A94UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT5 *((volatile uint8_t *)(0x42624A94UL)) + +#define bFM_INTREQ_IRQ021MON_WAVEINT0 *((volatile uint8_t *)(0x42624B00UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT0 *((volatile uint8_t *)(0x42624B00UL)) +#define bFM_INTREQ_IRQ021MON_WAVEINT1 *((volatile uint8_t *)(0x42624B04UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT1 *((volatile uint8_t *)(0x42624B04UL)) +#define bFM_INTREQ_IRQ021MON_WAVEINT2 *((volatile uint8_t *)(0x42624B08UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT2 *((volatile uint8_t *)(0x42624B08UL)) +#define bFM_INTREQ_IRQ021MON_WAVEINT3 *((volatile uint8_t *)(0x42624B0CUL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT3 *((volatile uint8_t *)(0x42624B0CUL)) + +#define bFM_INTREQ_IRQ022MON_WAVEINT0 *((volatile uint8_t *)(0x42624B80UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT0 *((volatile uint8_t *)(0x42624B80UL)) +#define bFM_INTREQ_IRQ022MON_WAVEINT1 *((volatile uint8_t *)(0x42624B84UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT1 *((volatile uint8_t *)(0x42624B84UL)) +#define bFM_INTREQ_IRQ022MON_WAVEINT2 *((volatile uint8_t *)(0x42624B88UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT2 *((volatile uint8_t *)(0x42624B88UL)) +#define bFM_INTREQ_IRQ022MON_WAVEINT3 *((volatile uint8_t *)(0x42624B8CUL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT3 *((volatile uint8_t *)(0x42624B8CUL)) + +#define bFM_INTREQ_IRQ023MON_WAVEINT0 *((volatile uint8_t *)(0x42624C00UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT0 *((volatile uint8_t *)(0x42624C00UL)) +#define bFM_INTREQ_IRQ023MON_WAVEINT1 *((volatile uint8_t *)(0x42624C04UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT1 *((volatile uint8_t *)(0x42624C04UL)) +#define bFM_INTREQ_IRQ023MON_WAVEINT2 *((volatile uint8_t *)(0x42624C08UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT2 *((volatile uint8_t *)(0x42624C08UL)) +#define bFM_INTREQ_IRQ023MON_WAVEINT3 *((volatile uint8_t *)(0x42624C0CUL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT3 *((volatile uint8_t *)(0x42624C0CUL)) + +#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624C80UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624C80UL)) +#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624C84UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624C84UL)) +#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624C88UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624C88UL)) + +#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624D00UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624D00UL)) +#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624D04UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624D04UL)) +#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624D08UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624D08UL)) + +#define bFM_INTREQ_IRQ026MON_ICUINT0 *((volatile uint8_t *)(0x42624D80UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT0 *((volatile uint8_t *)(0x42624D80UL)) +#define bFM_INTREQ_IRQ026MON_ICUINT1 *((volatile uint8_t *)(0x42624D84UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT1 *((volatile uint8_t *)(0x42624D84UL)) +#define bFM_INTREQ_IRQ026MON_ICUINT2 *((volatile uint8_t *)(0x42624D88UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT2 *((volatile uint8_t *)(0x42624D88UL)) +#define bFM_INTREQ_IRQ026MON_ICUINT3 *((volatile uint8_t *)(0x42624D8CUL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT3 *((volatile uint8_t *)(0x42624D8CUL)) + +#define bFM_INTREQ_IRQ027MON_OCUINT0 *((volatile uint8_t *)(0x42624E00UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT0 *((volatile uint8_t *)(0x42624E00UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT1 *((volatile uint8_t *)(0x42624E04UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT1 *((volatile uint8_t *)(0x42624E04UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT2 *((volatile uint8_t *)(0x42624E08UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT2 *((volatile uint8_t *)(0x42624E08UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT3 *((volatile uint8_t *)(0x42624E0CUL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT3 *((volatile uint8_t *)(0x42624E0CUL)) +#define bFM_INTREQ_IRQ027MON_OCUINT4 *((volatile uint8_t *)(0x42624E10UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT4 *((volatile uint8_t *)(0x42624E10UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT5 *((volatile uint8_t *)(0x42624E14UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT5 *((volatile uint8_t *)(0x42624E14UL)) + +#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624E80UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624E80UL)) +#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624E84UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624E84UL)) +#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624E88UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624E88UL)) + +#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624F00UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624F00UL)) +#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624F04UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624F04UL)) +#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624F08UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624F08UL)) + +#define bFM_INTREQ_IRQ030MON_ICUINT0 *((volatile uint8_t *)(0x42624F80UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT0 *((volatile uint8_t *)(0x42624F80UL)) +#define bFM_INTREQ_IRQ030MON_ICUINT1 *((volatile uint8_t *)(0x42624F84UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT1 *((volatile uint8_t *)(0x42624F84UL)) +#define bFM_INTREQ_IRQ030MON_ICUINT2 *((volatile uint8_t *)(0x42624F88UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT2 *((volatile uint8_t *)(0x42624F88UL)) +#define bFM_INTREQ_IRQ030MON_ICUINT3 *((volatile uint8_t *)(0x42624F8CUL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT3 *((volatile uint8_t *)(0x42624F8CUL)) + +#define bFM_INTREQ_IRQ031MON_OCUINT0 *((volatile uint8_t *)(0x42625000UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT0 *((volatile uint8_t *)(0x42625000UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT1 *((volatile uint8_t *)(0x42625004UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT1 *((volatile uint8_t *)(0x42625004UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT2 *((volatile uint8_t *)(0x42625008UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT2 *((volatile uint8_t *)(0x42625008UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT3 *((volatile uint8_t *)(0x4262500CUL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT3 *((volatile uint8_t *)(0x4262500CUL)) +#define bFM_INTREQ_IRQ031MON_OCUINT4 *((volatile uint8_t *)(0x42625010UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT4 *((volatile uint8_t *)(0x42625010UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT5 *((volatile uint8_t *)(0x42625014UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT5 *((volatile uint8_t *)(0x42625014UL)) + +#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42625080UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42625080UL)) +#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42625084UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42625084UL)) +#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42625088UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42625088UL)) + +#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42625100UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42625100UL)) +#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42625104UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42625104UL)) +#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42625108UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42625108UL)) + +#define bFM_INTREQ_IRQ034MON_ICUINT0 *((volatile uint8_t *)(0x42625180UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT0 *((volatile uint8_t *)(0x42625180UL)) +#define bFM_INTREQ_IRQ034MON_ICUINT1 *((volatile uint8_t *)(0x42625184UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT1 *((volatile uint8_t *)(0x42625184UL)) +#define bFM_INTREQ_IRQ034MON_ICUINT2 *((volatile uint8_t *)(0x42625188UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT2 *((volatile uint8_t *)(0x42625188UL)) +#define bFM_INTREQ_IRQ034MON_ICUINT3 *((volatile uint8_t *)(0x4262518CUL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT3 *((volatile uint8_t *)(0x4262518CUL)) + +#define bFM_INTREQ_IRQ035MON_OCUINT0 *((volatile uint8_t *)(0x42625200UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT0 *((volatile uint8_t *)(0x42625200UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT1 *((volatile uint8_t *)(0x42625204UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT1 *((volatile uint8_t *)(0x42625204UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT2 *((volatile uint8_t *)(0x42625208UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT2 *((volatile uint8_t *)(0x42625208UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT3 *((volatile uint8_t *)(0x4262520CUL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT3 *((volatile uint8_t *)(0x4262520CUL)) +#define bFM_INTREQ_IRQ035MON_OCUINT4 *((volatile uint8_t *)(0x42625210UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT4 *((volatile uint8_t *)(0x42625210UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT5 *((volatile uint8_t *)(0x42625214UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT5 *((volatile uint8_t *)(0x42625214UL)) + +#define bFM_INTREQ_IRQ036MON_PPGINT0 *((volatile uint8_t *)(0x42625280UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT0 *((volatile uint8_t *)(0x42625280UL)) +#define bFM_INTREQ_IRQ036MON_PPGINT1 *((volatile uint8_t *)(0x42625284UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT1 *((volatile uint8_t *)(0x42625284UL)) +#define bFM_INTREQ_IRQ036MON_PPGINT2 *((volatile uint8_t *)(0x42625288UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT2 *((volatile uint8_t *)(0x42625288UL)) + +#define bFM_INTREQ_IRQ037MON_PPGINT0 *((volatile uint8_t *)(0x42625300UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT0 *((volatile uint8_t *)(0x42625300UL)) +#define bFM_INTREQ_IRQ037MON_PPGINT1 *((volatile uint8_t *)(0x42625304UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT1 *((volatile uint8_t *)(0x42625304UL)) +#define bFM_INTREQ_IRQ037MON_PPGINT2 *((volatile uint8_t *)(0x42625308UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT2 *((volatile uint8_t *)(0x42625308UL)) + +#define bFM_INTREQ_IRQ038MON_PPGINT0 *((volatile uint8_t *)(0x42625380UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT0 *((volatile uint8_t *)(0x42625380UL)) +#define bFM_INTREQ_IRQ038MON_PPGINT1 *((volatile uint8_t *)(0x42625384UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT1 *((volatile uint8_t *)(0x42625384UL)) +#define bFM_INTREQ_IRQ038MON_PPGINT2 *((volatile uint8_t *)(0x42625388UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT2 *((volatile uint8_t *)(0x42625388UL)) + +#define bFM_INTREQ_IRQ039MON_BTINT0 *((volatile uint8_t *)(0x42625400UL)) +#define bFM4_INTREQ_IRQ039MON_BTINT0 *((volatile uint8_t *)(0x42625400UL)) +#define bFM_INTREQ_IRQ039MON_BTINT1 *((volatile uint8_t *)(0x42625404UL)) +#define bFM4_INTREQ_IRQ039MON_BTINT1 *((volatile uint8_t *)(0x42625404UL)) + +#define bFM_INTREQ_IRQ040MON_BTINT0 *((volatile uint8_t *)(0x42625480UL)) +#define bFM4_INTREQ_IRQ040MON_BTINT0 *((volatile uint8_t *)(0x42625480UL)) +#define bFM_INTREQ_IRQ040MON_BTINT1 *((volatile uint8_t *)(0x42625484UL)) +#define bFM4_INTREQ_IRQ040MON_BTINT1 *((volatile uint8_t *)(0x42625484UL)) + +#define bFM_INTREQ_IRQ041MON_BTINT0 *((volatile uint8_t *)(0x42625500UL)) +#define bFM4_INTREQ_IRQ041MON_BTINT0 *((volatile uint8_t *)(0x42625500UL)) +#define bFM_INTREQ_IRQ041MON_BTINT1 *((volatile uint8_t *)(0x42625504UL)) +#define bFM4_INTREQ_IRQ041MON_BTINT1 *((volatile uint8_t *)(0x42625504UL)) + +#define bFM_INTREQ_IRQ042MON_BTINT0 *((volatile uint8_t *)(0x42625580UL)) +#define bFM4_INTREQ_IRQ042MON_BTINT0 *((volatile uint8_t *)(0x42625580UL)) +#define bFM_INTREQ_IRQ042MON_BTINT1 *((volatile uint8_t *)(0x42625584UL)) +#define bFM4_INTREQ_IRQ042MON_BTINT1 *((volatile uint8_t *)(0x42625584UL)) + +#define bFM_INTREQ_IRQ043MON_BTINT0 *((volatile uint8_t *)(0x42625600UL)) +#define bFM4_INTREQ_IRQ043MON_BTINT0 *((volatile uint8_t *)(0x42625600UL)) +#define bFM_INTREQ_IRQ043MON_BTINT1 *((volatile uint8_t *)(0x42625604UL)) +#define bFM4_INTREQ_IRQ043MON_BTINT1 *((volatile uint8_t *)(0x42625604UL)) + +#define bFM_INTREQ_IRQ044MON_BTINT0 *((volatile uint8_t *)(0x42625680UL)) +#define bFM4_INTREQ_IRQ044MON_BTINT0 *((volatile uint8_t *)(0x42625680UL)) +#define bFM_INTREQ_IRQ044MON_BTINT1 *((volatile uint8_t *)(0x42625684UL)) +#define bFM4_INTREQ_IRQ044MON_BTINT1 *((volatile uint8_t *)(0x42625684UL)) + +#define bFM_INTREQ_IRQ045MON_BTINT0 *((volatile uint8_t *)(0x42625700UL)) +#define bFM4_INTREQ_IRQ045MON_BTINT0 *((volatile uint8_t *)(0x42625700UL)) +#define bFM_INTREQ_IRQ045MON_BTINT1 *((volatile uint8_t *)(0x42625704UL)) +#define bFM4_INTREQ_IRQ045MON_BTINT1 *((volatile uint8_t *)(0x42625704UL)) + +#define bFM_INTREQ_IRQ046MON_BTINT0 *((volatile uint8_t *)(0x42625780UL)) +#define bFM4_INTREQ_IRQ046MON_BTINT0 *((volatile uint8_t *)(0x42625780UL)) +#define bFM_INTREQ_IRQ046MON_BTINT1 *((volatile uint8_t *)(0x42625784UL)) +#define bFM4_INTREQ_IRQ046MON_BTINT1 *((volatile uint8_t *)(0x42625784UL)) + +#define bFM_INTREQ_IRQ047MON_TIMINT1 *((volatile uint8_t *)(0x42625800UL)) +#define bFM4_INTREQ_IRQ047MON_TIMINT1 *((volatile uint8_t *)(0x42625800UL)) +#define bFM_INTREQ_IRQ047MON_TIMINT2 *((volatile uint8_t *)(0x42625804UL)) +#define bFM4_INTREQ_IRQ047MON_TIMINT2 *((volatile uint8_t *)(0x42625804UL)) + +#define bFM_INTREQ_IRQ048MON_WCINT *((volatile uint8_t *)(0x42625880UL)) +#define bFM4_INTREQ_IRQ048MON_WCINT *((volatile uint8_t *)(0x42625880UL)) + +#define bFM_INTREQ_IRQ049MON_BMEMCS *((volatile uint8_t *)(0x42625900UL)) +#define bFM4_INTREQ_IRQ049MON_BMEMCS *((volatile uint8_t *)(0x42625900UL)) + +#define bFM_INTREQ_IRQ050MON_RTCINT *((volatile uint8_t *)(0x42625980UL)) +#define bFM4_INTREQ_IRQ050MON_RTCINT *((volatile uint8_t *)(0x42625980UL)) + +#define bFM_INTREQ_IRQ051MON_EXTINT *((volatile uint8_t *)(0x42625A00UL)) +#define bFM4_INTREQ_IRQ051MON_EXTINT *((volatile uint8_t *)(0x42625A00UL)) + +#define bFM_INTREQ_IRQ052MON_EXTINT *((volatile uint8_t *)(0x42625A80UL)) +#define bFM4_INTREQ_IRQ052MON_EXTINT *((volatile uint8_t *)(0x42625A80UL)) + +#define bFM_INTREQ_IRQ053MON_EXTINT *((volatile uint8_t *)(0x42625B00UL)) +#define bFM4_INTREQ_IRQ053MON_EXTINT *((volatile uint8_t *)(0x42625B00UL)) + +#define bFM_INTREQ_IRQ054MON_EXTINT *((volatile uint8_t *)(0x42625B80UL)) +#define bFM4_INTREQ_IRQ054MON_EXTINT *((volatile uint8_t *)(0x42625B80UL)) + +#define bFM_INTREQ_IRQ055MON_EXTINT *((volatile uint8_t *)(0x42625C00UL)) +#define bFM4_INTREQ_IRQ055MON_EXTINT *((volatile uint8_t *)(0x42625C00UL)) + +#define bFM_INTREQ_IRQ056MON_EXTINT *((volatile uint8_t *)(0x42625C80UL)) +#define bFM4_INTREQ_IRQ056MON_EXTINT *((volatile uint8_t *)(0x42625C80UL)) + +#define bFM_INTREQ_IRQ057MON_EXTINT *((volatile uint8_t *)(0x42625D00UL)) +#define bFM4_INTREQ_IRQ057MON_EXTINT *((volatile uint8_t *)(0x42625D00UL)) + +#define bFM_INTREQ_IRQ058MON_EXTINT *((volatile uint8_t *)(0x42625D80UL)) +#define bFM4_INTREQ_IRQ058MON_EXTINT *((volatile uint8_t *)(0x42625D80UL)) + +#define bFM_INTREQ_IRQ059MON_MOSCINT *((volatile uint8_t *)(0x42625E00UL)) +#define bFM4_INTREQ_IRQ059MON_MOSCINT *((volatile uint8_t *)(0x42625E00UL)) +#define bFM_INTREQ_IRQ059MON_SOSCINT *((volatile uint8_t *)(0x42625E04UL)) +#define bFM4_INTREQ_IRQ059MON_SOSCINT *((volatile uint8_t *)(0x42625E04UL)) +#define bFM_INTREQ_IRQ059MON_MPLLINT *((volatile uint8_t *)(0x42625E08UL)) +#define bFM4_INTREQ_IRQ059MON_MPLLINT *((volatile uint8_t *)(0x42625E08UL)) +#define bFM_INTREQ_IRQ059MON_UPLLINT *((volatile uint8_t *)(0x42625E0CUL)) +#define bFM4_INTREQ_IRQ059MON_UPLLINT *((volatile uint8_t *)(0x42625E0CUL)) +#define bFM_INTREQ_IRQ059MON_IPLLINT *((volatile uint8_t *)(0x42625E10UL)) +#define bFM4_INTREQ_IRQ059MON_IPLLINT *((volatile uint8_t *)(0x42625E10UL)) + +#define bFM_INTREQ_IRQ060MON_MFSINT0_RX *((volatile uint8_t *)(0x42625E80UL)) +#define bFM4_INTREQ_IRQ060MON_MFSINT0_RX *((volatile uint8_t *)(0x42625E80UL)) + +#define bFM_INTREQ_IRQ061MON_MFSINT0_TX *((volatile uint8_t *)(0x42625F00UL)) +#define bFM4_INTREQ_IRQ061MON_MFSINT0_TX *((volatile uint8_t *)(0x42625F00UL)) +#define bFM_INTREQ_IRQ061MON_MFSINT0_STATUS *((volatile uint8_t *)(0x42625F04UL)) +#define bFM4_INTREQ_IRQ061MON_MFSINT0_STATUS *((volatile uint8_t *)(0x42625F04UL)) + +#define bFM_INTREQ_IRQ062MON_MFSINT1_RX *((volatile uint8_t *)(0x42625F80UL)) +#define bFM4_INTREQ_IRQ062MON_MFSINT1_RX *((volatile uint8_t *)(0x42625F80UL)) + +#define bFM_INTREQ_IRQ063MON_MFSINT1_TX *((volatile uint8_t *)(0x42626000UL)) +#define bFM4_INTREQ_IRQ063MON_MFSINT1_TX *((volatile uint8_t *)(0x42626000UL)) +#define bFM_INTREQ_IRQ063MON_MFSINT1_STATUS *((volatile uint8_t *)(0x42626004UL)) +#define bFM4_INTREQ_IRQ063MON_MFSINT1_STATUS *((volatile uint8_t *)(0x42626004UL)) + +#define bFM_INTREQ_IRQ064MON_MFSINT2_RX *((volatile uint8_t *)(0x42626080UL)) +#define bFM4_INTREQ_IRQ064MON_MFSINT2_RX *((volatile uint8_t *)(0x42626080UL)) + +#define bFM_INTREQ_IRQ065MON_MFSINT2_TX *((volatile uint8_t *)(0x42626100UL)) +#define bFM4_INTREQ_IRQ065MON_MFSINT2_TX *((volatile uint8_t *)(0x42626100UL)) +#define bFM_INTREQ_IRQ065MON_MFSINT2_STATUS *((volatile uint8_t *)(0x42626104UL)) +#define bFM4_INTREQ_IRQ065MON_MFSINT2_STATUS *((volatile uint8_t *)(0x42626104UL)) + +#define bFM_INTREQ_IRQ066MON_MFSINT3_RX *((volatile uint8_t *)(0x42626180UL)) +#define bFM4_INTREQ_IRQ066MON_MFSINT3_RX *((volatile uint8_t *)(0x42626180UL)) + +#define bFM_INTREQ_IRQ067MON_MFSINT3_TX *((volatile uint8_t *)(0x42626200UL)) +#define bFM4_INTREQ_IRQ067MON_MFSINT3_TX *((volatile uint8_t *)(0x42626200UL)) +#define bFM_INTREQ_IRQ067MON_MFSINT3_STATUS *((volatile uint8_t *)(0x42626204UL)) +#define bFM4_INTREQ_IRQ067MON_MFSINT3_STATUS *((volatile uint8_t *)(0x42626204UL)) + +#define bFM_INTREQ_IRQ068MON_MFSINT4_RX *((volatile uint8_t *)(0x42626280UL)) +#define bFM4_INTREQ_IRQ068MON_MFSINT4_RX *((volatile uint8_t *)(0x42626280UL)) + +#define bFM_INTREQ_IRQ069MON_MFSINT4_TX *((volatile uint8_t *)(0x42626300UL)) +#define bFM4_INTREQ_IRQ069MON_MFSINT4_TX *((volatile uint8_t *)(0x42626300UL)) +#define bFM_INTREQ_IRQ069MON_MFSINT4_STATUS *((volatile uint8_t *)(0x42626304UL)) +#define bFM4_INTREQ_IRQ069MON_MFSINT4_STATUS *((volatile uint8_t *)(0x42626304UL)) + +#define bFM_INTREQ_IRQ070MON_MFSINT5_RX *((volatile uint8_t *)(0x42626380UL)) +#define bFM4_INTREQ_IRQ070MON_MFSINT5_RX *((volatile uint8_t *)(0x42626380UL)) + +#define bFM_INTREQ_IRQ071MON_MFSINT5_TX *((volatile uint8_t *)(0x42626400UL)) +#define bFM4_INTREQ_IRQ071MON_MFSINT5_TX *((volatile uint8_t *)(0x42626400UL)) +#define bFM_INTREQ_IRQ071MON_MFSINT5_STATUS *((volatile uint8_t *)(0x42626404UL)) +#define bFM4_INTREQ_IRQ071MON_MFSINT5_STATUS *((volatile uint8_t *)(0x42626404UL)) + +#define bFM_INTREQ_IRQ072MON_MFSINT6_RX *((volatile uint8_t *)(0x42626480UL)) +#define bFM4_INTREQ_IRQ072MON_MFSINT6_RX *((volatile uint8_t *)(0x42626480UL)) + +#define bFM_INTREQ_IRQ073MON_MFSINT6_TX *((volatile uint8_t *)(0x42626500UL)) +#define bFM4_INTREQ_IRQ073MON_MFSINT6_TX *((volatile uint8_t *)(0x42626500UL)) +#define bFM_INTREQ_IRQ073MON_MFSINT6_STATUS *((volatile uint8_t *)(0x42626504UL)) +#define bFM4_INTREQ_IRQ073MON_MFSINT6_STATUS *((volatile uint8_t *)(0x42626504UL)) + +#define bFM_INTREQ_IRQ074MON_MFSINT7_RX *((volatile uint8_t *)(0x42626580UL)) +#define bFM4_INTREQ_IRQ074MON_MFSINT7_RX *((volatile uint8_t *)(0x42626580UL)) + +#define bFM_INTREQ_IRQ075MON_MFSINT7_TX *((volatile uint8_t *)(0x42626600UL)) +#define bFM4_INTREQ_IRQ075MON_MFSINT7_TX *((volatile uint8_t *)(0x42626600UL)) +#define bFM_INTREQ_IRQ075MON_MFSINT7_STATUS *((volatile uint8_t *)(0x42626604UL)) +#define bFM4_INTREQ_IRQ075MON_MFSINT7_STATUS *((volatile uint8_t *)(0x42626604UL)) + +#define bFM_INTREQ_IRQ076MON_ADCINT0 *((volatile uint8_t *)(0x42626680UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT0 *((volatile uint8_t *)(0x42626680UL)) +#define bFM_INTREQ_IRQ076MON_ADCINT1 *((volatile uint8_t *)(0x42626684UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT1 *((volatile uint8_t *)(0x42626684UL)) +#define bFM_INTREQ_IRQ076MON_ADCINT2 *((volatile uint8_t *)(0x42626688UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT2 *((volatile uint8_t *)(0x42626688UL)) +#define bFM_INTREQ_IRQ076MON_ADCINT3 *((volatile uint8_t *)(0x4262668CUL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT3 *((volatile uint8_t *)(0x4262668CUL)) +#define bFM_INTREQ_IRQ076MON_ADCINT4 *((volatile uint8_t *)(0x42626690UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT4 *((volatile uint8_t *)(0x42626690UL)) + +#define bFM_INTREQ_IRQ077MON_ADCINT0 *((volatile uint8_t *)(0x42626700UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT0 *((volatile uint8_t *)(0x42626700UL)) +#define bFM_INTREQ_IRQ077MON_ADCINT1 *((volatile uint8_t *)(0x42626704UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT1 *((volatile uint8_t *)(0x42626704UL)) +#define bFM_INTREQ_IRQ077MON_ADCINT2 *((volatile uint8_t *)(0x42626708UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT2 *((volatile uint8_t *)(0x42626708UL)) +#define bFM_INTREQ_IRQ077MON_ADCINT3 *((volatile uint8_t *)(0x4262670CUL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT3 *((volatile uint8_t *)(0x4262670CUL)) +#define bFM_INTREQ_IRQ077MON_ADCINT4 *((volatile uint8_t *)(0x42626710UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT4 *((volatile uint8_t *)(0x42626710UL)) + +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42626780UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42626780UL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42626784UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42626784UL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42626788UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42626788UL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262678CUL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262678CUL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42626790UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42626790UL)) + +#define bFM_INTREQ_IRQ079MON_USB_INT0 *((volatile uint8_t *)(0x42626800UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT0 *((volatile uint8_t *)(0x42626800UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT1 *((volatile uint8_t *)(0x42626804UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT1 *((volatile uint8_t *)(0x42626804UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT2 *((volatile uint8_t *)(0x42626808UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT2 *((volatile uint8_t *)(0x42626808UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT3 *((volatile uint8_t *)(0x4262680CUL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT3 *((volatile uint8_t *)(0x4262680CUL)) +#define bFM_INTREQ_IRQ079MON_USB_INT4 *((volatile uint8_t *)(0x42626810UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT4 *((volatile uint8_t *)(0x42626810UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT5 *((volatile uint8_t *)(0x42626814UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT5 *((volatile uint8_t *)(0x42626814UL)) + +#define bFM_INTREQ_IRQ080MON_CANINT *((volatile uint8_t *)(0x42626880UL)) +#define bFM4_INTREQ_IRQ080MON_CANINT *((volatile uint8_t *)(0x42626880UL)) + +#define bFM_INTREQ_IRQ081MON_CANINT *((volatile uint8_t *)(0x42626900UL)) +#define bFM4_INTREQ_IRQ081MON_CANINT *((volatile uint8_t *)(0x42626900UL)) +#define bFM_INTREQ_IRQ081MON_CANDEINT *((volatile uint8_t *)(0x42626904UL)) +#define bFM4_INTREQ_IRQ081MON_CANDEINT *((volatile uint8_t *)(0x42626904UL)) +#define bFM_INTREQ_IRQ081MON_CANSEINT *((volatile uint8_t *)(0x42626908UL)) +#define bFM4_INTREQ_IRQ081MON_CANSEINT *((volatile uint8_t *)(0x42626908UL)) +#define bFM_INTREQ_IRQ081MON_CAN0INT *((volatile uint8_t *)(0x4262690CUL)) +#define bFM4_INTREQ_IRQ081MON_CAN0INT *((volatile uint8_t *)(0x4262690CUL)) +#define bFM_INTREQ_IRQ081MON_CAN1INT *((volatile uint8_t *)(0x42626910UL)) +#define bFM4_INTREQ_IRQ081MON_CAN1INT *((volatile uint8_t *)(0x42626910UL)) + +#define bFM_INTREQ_IRQ082MON_MACSBD *((volatile uint8_t *)(0x42626980UL)) +#define bFM4_INTREQ_IRQ082MON_MACSBD *((volatile uint8_t *)(0x42626980UL)) +#define bFM_INTREQ_IRQ082MON_MACPMT *((volatile uint8_t *)(0x42626984UL)) +#define bFM4_INTREQ_IRQ082MON_MACPMT *((volatile uint8_t *)(0x42626984UL)) +#define bFM_INTREQ_IRQ082MON_MACLPI *((volatile uint8_t *)(0x42626988UL)) +#define bFM4_INTREQ_IRQ082MON_MACLPI *((volatile uint8_t *)(0x42626988UL)) + +#define bFM_INTREQ_IRQ083MON_DMACINT *((volatile uint8_t *)(0x42626A00UL)) +#define bFM4_INTREQ_IRQ083MON_DMACINT *((volatile uint8_t *)(0x42626A00UL)) + +#define bFM_INTREQ_IRQ084MON_DMACINT *((volatile uint8_t *)(0x42626A80UL)) +#define bFM4_INTREQ_IRQ084MON_DMACINT *((volatile uint8_t *)(0x42626A80UL)) + +#define bFM_INTREQ_IRQ085MON_DMACINT *((volatile uint8_t *)(0x42626B00UL)) +#define bFM4_INTREQ_IRQ085MON_DMACINT *((volatile uint8_t *)(0x42626B00UL)) + +#define bFM_INTREQ_IRQ086MON_DMACINT *((volatile uint8_t *)(0x42626B80UL)) +#define bFM4_INTREQ_IRQ086MON_DMACINT *((volatile uint8_t *)(0x42626B80UL)) + +#define bFM_INTREQ_IRQ087MON_DMACINT *((volatile uint8_t *)(0x42626C00UL)) +#define bFM4_INTREQ_IRQ087MON_DMACINT *((volatile uint8_t *)(0x42626C00UL)) + +#define bFM_INTREQ_IRQ088MON_DMACINT *((volatile uint8_t *)(0x42626C80UL)) +#define bFM4_INTREQ_IRQ088MON_DMACINT *((volatile uint8_t *)(0x42626C80UL)) + +#define bFM_INTREQ_IRQ089MON_DMACINT *((volatile uint8_t *)(0x42626D00UL)) +#define bFM4_INTREQ_IRQ089MON_DMACINT *((volatile uint8_t *)(0x42626D00UL)) + +#define bFM_INTREQ_IRQ090MON_DMACINT *((volatile uint8_t *)(0x42626D80UL)) +#define bFM4_INTREQ_IRQ090MON_DMACINT *((volatile uint8_t *)(0x42626D80UL)) + +#define bFM_INTREQ_IRQ091MON_DSTCINT0 *((volatile uint8_t *)(0x42626E00UL)) +#define bFM4_INTREQ_IRQ091MON_DSTCINT0 *((volatile uint8_t *)(0x42626E00UL)) +#define bFM_INTREQ_IRQ091MON_DSTCINT1 *((volatile uint8_t *)(0x42626E04UL)) +#define bFM4_INTREQ_IRQ091MON_DSTCINT1 *((volatile uint8_t *)(0x42626E04UL)) + +#define bFM_INTREQ_IRQ092MON_EXTINT0 *((volatile uint8_t *)(0x42626E80UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT0 *((volatile uint8_t *)(0x42626E80UL)) +#define bFM_INTREQ_IRQ092MON_EXTINT1 *((volatile uint8_t *)(0x42626E84UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT1 *((volatile uint8_t *)(0x42626E84UL)) +#define bFM_INTREQ_IRQ092MON_EXTINT2 *((volatile uint8_t *)(0x42626E88UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT2 *((volatile uint8_t *)(0x42626E88UL)) +#define bFM_INTREQ_IRQ092MON_EXTINT3 *((volatile uint8_t *)(0x42626E8CUL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT3 *((volatile uint8_t *)(0x42626E8CUL)) + +#define bFM_INTREQ_IRQ093MON_EXTINT0 *((volatile uint8_t *)(0x42626F00UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT0 *((volatile uint8_t *)(0x42626F00UL)) +#define bFM_INTREQ_IRQ093MON_EXTINT1 *((volatile uint8_t *)(0x42626F04UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT1 *((volatile uint8_t *)(0x42626F04UL)) +#define bFM_INTREQ_IRQ093MON_EXTINT2 *((volatile uint8_t *)(0x42626F08UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT2 *((volatile uint8_t *)(0x42626F08UL)) +#define bFM_INTREQ_IRQ093MON_EXTINT3 *((volatile uint8_t *)(0x42626F0CUL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT3 *((volatile uint8_t *)(0x42626F0CUL)) + +#define bFM_INTREQ_IRQ094MON_EXTINT0 *((volatile uint8_t *)(0x42626F80UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT0 *((volatile uint8_t *)(0x42626F80UL)) +#define bFM_INTREQ_IRQ094MON_EXTINT1 *((volatile uint8_t *)(0x42626F84UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT1 *((volatile uint8_t *)(0x42626F84UL)) +#define bFM_INTREQ_IRQ094MON_EXTINT2 *((volatile uint8_t *)(0x42626F88UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT2 *((volatile uint8_t *)(0x42626F88UL)) +#define bFM_INTREQ_IRQ094MON_EXTINT3 *((volatile uint8_t *)(0x42626F8CUL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT3 *((volatile uint8_t *)(0x42626F8CUL)) + +#define bFM_INTREQ_IRQ095MON_EXTINT0 *((volatile uint8_t *)(0x42627000UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT0 *((volatile uint8_t *)(0x42627000UL)) +#define bFM_INTREQ_IRQ095MON_EXTINT1 *((volatile uint8_t *)(0x42627004UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT1 *((volatile uint8_t *)(0x42627004UL)) +#define bFM_INTREQ_IRQ095MON_EXTINT2 *((volatile uint8_t *)(0x42627008UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT2 *((volatile uint8_t *)(0x42627008UL)) +#define bFM_INTREQ_IRQ095MON_EXTINT3 *((volatile uint8_t *)(0x4262700CUL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT3 *((volatile uint8_t *)(0x4262700CUL)) + +#define bFM_INTREQ_IRQ096MON_QPRCINT0 *((volatile uint8_t *)(0x42627080UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT0 *((volatile uint8_t *)(0x42627080UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT1 *((volatile uint8_t *)(0x42627084UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT1 *((volatile uint8_t *)(0x42627084UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT2 *((volatile uint8_t *)(0x42627088UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT2 *((volatile uint8_t *)(0x42627088UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT3 *((volatile uint8_t *)(0x4262708CUL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT3 *((volatile uint8_t *)(0x4262708CUL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT4 *((volatile uint8_t *)(0x42627090UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT4 *((volatile uint8_t *)(0x42627090UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT5 *((volatile uint8_t *)(0x42627094UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT5 *((volatile uint8_t *)(0x42627094UL)) + +#define bFM_INTREQ_IRQ097MON_QPRCINT0 *((volatile uint8_t *)(0x42627100UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT0 *((volatile uint8_t *)(0x42627100UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT1 *((volatile uint8_t *)(0x42627104UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT1 *((volatile uint8_t *)(0x42627104UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT2 *((volatile uint8_t *)(0x42627108UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT2 *((volatile uint8_t *)(0x42627108UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT3 *((volatile uint8_t *)(0x4262710CUL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT3 *((volatile uint8_t *)(0x4262710CUL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT4 *((volatile uint8_t *)(0x42627110UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT4 *((volatile uint8_t *)(0x42627110UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT5 *((volatile uint8_t *)(0x42627114UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT5 *((volatile uint8_t *)(0x42627114UL)) + +#define bFM_INTREQ_IRQ098MON_BTINT0 *((volatile uint8_t *)(0x42627180UL)) +#define bFM4_INTREQ_IRQ098MON_BTINT0 *((volatile uint8_t *)(0x42627180UL)) +#define bFM_INTREQ_IRQ098MON_BTINT1 *((volatile uint8_t *)(0x42627184UL)) +#define bFM4_INTREQ_IRQ098MON_BTINT1 *((volatile uint8_t *)(0x42627184UL)) + +#define bFM_INTREQ_IRQ099MON_BTINT0 *((volatile uint8_t *)(0x42627200UL)) +#define bFM4_INTREQ_IRQ099MON_BTINT0 *((volatile uint8_t *)(0x42627200UL)) +#define bFM_INTREQ_IRQ099MON_BTINT1 *((volatile uint8_t *)(0x42627204UL)) +#define bFM4_INTREQ_IRQ099MON_BTINT1 *((volatile uint8_t *)(0x42627204UL)) + +#define bFM_INTREQ_IRQ100MON_BTINT0 *((volatile uint8_t *)(0x42627280UL)) +#define bFM4_INTREQ_IRQ100MON_BTINT0 *((volatile uint8_t *)(0x42627280UL)) +#define bFM_INTREQ_IRQ100MON_BTINT1 *((volatile uint8_t *)(0x42627284UL)) +#define bFM4_INTREQ_IRQ100MON_BTINT1 *((volatile uint8_t *)(0x42627284UL)) + +#define bFM_INTREQ_IRQ101MON_BTINT0 *((volatile uint8_t *)(0x42627300UL)) +#define bFM4_INTREQ_IRQ101MON_BTINT0 *((volatile uint8_t *)(0x42627300UL)) +#define bFM_INTREQ_IRQ101MON_BTINT1 *((volatile uint8_t *)(0x42627304UL)) +#define bFM4_INTREQ_IRQ101MON_BTINT1 *((volatile uint8_t *)(0x42627304UL)) + +#define bFM_INTREQ_IRQ102MON_BTINT0 *((volatile uint8_t *)(0x42627380UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT0 *((volatile uint8_t *)(0x42627380UL)) +#define bFM_INTREQ_IRQ102MON_BTINT1 *((volatile uint8_t *)(0x42627384UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT1 *((volatile uint8_t *)(0x42627384UL)) +#define bFM_INTREQ_IRQ102MON_BTINT2 *((volatile uint8_t *)(0x42627388UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT2 *((volatile uint8_t *)(0x42627388UL)) +#define bFM_INTREQ_IRQ102MON_BTINT3 *((volatile uint8_t *)(0x4262738CUL)) +#define bFM4_INTREQ_IRQ102MON_BTINT3 *((volatile uint8_t *)(0x4262738CUL)) +#define bFM_INTREQ_IRQ102MON_BTINT4 *((volatile uint8_t *)(0x42627390UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT4 *((volatile uint8_t *)(0x42627390UL)) +#define bFM_INTREQ_IRQ102MON_BTINT5 *((volatile uint8_t *)(0x42627394UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT5 *((volatile uint8_t *)(0x42627394UL)) +#define bFM_INTREQ_IRQ102MON_BTINT6 *((volatile uint8_t *)(0x42627398UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT6 *((volatile uint8_t *)(0x42627398UL)) +#define bFM_INTREQ_IRQ102MON_BTINT7 *((volatile uint8_t *)(0x4262739CUL)) +#define bFM4_INTREQ_IRQ102MON_BTINT7 *((volatile uint8_t *)(0x4262739CUL)) + +#define bFM_INTREQ_IRQ103MON_MFSINT8_RX *((volatile uint8_t *)(0x42627400UL)) +#define bFM4_INTREQ_IRQ103MON_MFSINT8_RX *((volatile uint8_t *)(0x42627400UL)) + +#define bFM_INTREQ_IRQ104MON_MFSINT8_TX *((volatile uint8_t *)(0x42627480UL)) +#define bFM4_INTREQ_IRQ104MON_MFSINT8_TX *((volatile uint8_t *)(0x42627480UL)) +#define bFM_INTREQ_IRQ104MON_MFSINT8_STATUS *((volatile uint8_t *)(0x42627484UL)) +#define bFM4_INTREQ_IRQ104MON_MFSINT8_STATUS *((volatile uint8_t *)(0x42627484UL)) + +#define bFM_INTREQ_IRQ105MON_MFSINT9_RX *((volatile uint8_t *)(0x42627500UL)) +#define bFM4_INTREQ_IRQ105MON_MFSINT9_RX *((volatile uint8_t *)(0x42627500UL)) + +#define bFM_INTREQ_IRQ106MON_MFSINT9_TX *((volatile uint8_t *)(0x42627580UL)) +#define bFM4_INTREQ_IRQ106MON_MFSINT9_TX *((volatile uint8_t *)(0x42627580UL)) +#define bFM_INTREQ_IRQ106MON_MFSINT9_STATUS *((volatile uint8_t *)(0x42627584UL)) +#define bFM4_INTREQ_IRQ106MON_MFSINT9_STATUS *((volatile uint8_t *)(0x42627584UL)) + +#define bFM_INTREQ_IRQ107MON_MFSINT10_RX *((volatile uint8_t *)(0x42627600UL)) +#define bFM4_INTREQ_IRQ107MON_MFSINT10_RX *((volatile uint8_t *)(0x42627600UL)) + +#define bFM_INTREQ_IRQ108MON_MFSINT10_TX *((volatile uint8_t *)(0x42627680UL)) +#define bFM4_INTREQ_IRQ108MON_MFSINT10_TX *((volatile uint8_t *)(0x42627680UL)) +#define bFM_INTREQ_IRQ108MON_MFSINT10_STATUS *((volatile uint8_t *)(0x42627684UL)) +#define bFM4_INTREQ_IRQ108MON_MFSINT10_STATUS *((volatile uint8_t *)(0x42627684UL)) + +#define bFM_INTREQ_IRQ109MON_MFSINT11_RX *((volatile uint8_t *)(0x42627700UL)) +#define bFM4_INTREQ_IRQ109MON_MFSINT11_RX *((volatile uint8_t *)(0x42627700UL)) + +#define bFM_INTREQ_IRQ110MON_MFSINT11_TX *((volatile uint8_t *)(0x42627780UL)) +#define bFM4_INTREQ_IRQ110MON_MFSINT11_TX *((volatile uint8_t *)(0x42627780UL)) +#define bFM_INTREQ_IRQ110MON_MFSINT11_STATUS *((volatile uint8_t *)(0x42627784UL)) +#define bFM4_INTREQ_IRQ110MON_MFSINT11_STATUS *((volatile uint8_t *)(0x42627784UL)) + +#define bFM_INTREQ_IRQ111MON_ADCINT0 *((volatile uint8_t *)(0x42627800UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT0 *((volatile uint8_t *)(0x42627800UL)) +#define bFM_INTREQ_IRQ111MON_ADCINT1 *((volatile uint8_t *)(0x42627804UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT1 *((volatile uint8_t *)(0x42627804UL)) +#define bFM_INTREQ_IRQ111MON_ADCINT2 *((volatile uint8_t *)(0x42627808UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT2 *((volatile uint8_t *)(0x42627808UL)) +#define bFM_INTREQ_IRQ111MON_ADCINT3 *((volatile uint8_t *)(0x4262780CUL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT3 *((volatile uint8_t *)(0x4262780CUL)) +#define bFM_INTREQ_IRQ111MON_ADCINT4 *((volatile uint8_t *)(0x42627810UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT4 *((volatile uint8_t *)(0x42627810UL)) + +#define bFM_INTREQ_IRQ112MON_I2SDINT0 *((volatile uint8_t *)(0x42627880UL)) +#define bFM4_INTREQ_IRQ112MON_I2SDINT0 *((volatile uint8_t *)(0x42627880UL)) +#define bFM_INTREQ_IRQ112MON_I2SDINT1 *((volatile uint8_t *)(0x42627884UL)) +#define bFM4_INTREQ_IRQ112MON_I2SDINT1 *((volatile uint8_t *)(0x42627884UL)) +#define bFM_INTREQ_IRQ112MON_HSSPIDINT0 *((volatile uint8_t *)(0x42627888UL)) +#define bFM4_INTREQ_IRQ112MON_HSSPIDINT0 *((volatile uint8_t *)(0x42627888UL)) +#define bFM_INTREQ_IRQ112MON_HSSPIDINT1 *((volatile uint8_t *)(0x4262788CUL)) +#define bFM4_INTREQ_IRQ112MON_HSSPIDINT1 *((volatile uint8_t *)(0x4262788CUL)) +#define bFM_INTREQ_IRQ112MON_PCRCDINT *((volatile uint8_t *)(0x42627890UL)) +#define bFM4_INTREQ_IRQ112MON_PCRCDINT *((volatile uint8_t *)(0x42627890UL)) +#define bFM_INTREQ_IRQ112MON_CANDINT *((volatile uint8_t *)(0x42627894UL)) +#define bFM4_INTREQ_IRQ112MON_CANDINT *((volatile uint8_t *)(0x42627894UL)) + +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42627900UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42627900UL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42627904UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42627904UL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42627908UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42627908UL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262790CUL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262790CUL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42627910UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42627910UL)) +#define bFM_INTREQ_IRQ113MON_RCEC0INT *((volatile uint8_t *)(0x42627914UL)) +#define bFM4_INTREQ_IRQ113MON_RCEC0INT *((volatile uint8_t *)(0x42627914UL)) + +#define bFM_INTREQ_IRQ114MON_USB_INT0 *((volatile uint8_t *)(0x42627980UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT0 *((volatile uint8_t *)(0x42627980UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT1 *((volatile uint8_t *)(0x42627984UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT1 *((volatile uint8_t *)(0x42627984UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT2 *((volatile uint8_t *)(0x42627988UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT2 *((volatile uint8_t *)(0x42627988UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT3 *((volatile uint8_t *)(0x4262798CUL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT3 *((volatile uint8_t *)(0x4262798CUL)) +#define bFM_INTREQ_IRQ114MON_USB_INT4 *((volatile uint8_t *)(0x42627990UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT4 *((volatile uint8_t *)(0x42627990UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT5 *((volatile uint8_t *)(0x42627994UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT5 *((volatile uint8_t *)(0x42627994UL)) +#define bFM_INTREQ_IRQ114MON_RCEC1INT *((volatile uint8_t *)(0x42627998UL)) +#define bFM4_INTREQ_IRQ114MON_RCEC1INT *((volatile uint8_t *)(0x42627998UL)) + +#define bFM_INTREQ_IRQ115MON_HSSPIINT0 *((volatile uint8_t *)(0x42627A00UL)) +#define bFM4_INTREQ_IRQ115MON_HSSPIINT0 *((volatile uint8_t *)(0x42627A00UL)) +#define bFM_INTREQ_IRQ115MON_HSSPIINT1 *((volatile uint8_t *)(0x42627A04UL)) +#define bFM4_INTREQ_IRQ115MON_HSSPIINT1 *((volatile uint8_t *)(0x42627A04UL)) +#define bFM_INTREQ_IRQ115MON_HSSPIINT2 *((volatile uint8_t *)(0x42627A08UL)) +#define bFM4_INTREQ_IRQ115MON_HSSPIINT2 *((volatile uint8_t *)(0x42627A08UL)) + +#define bFM_INTREQ_IRQ117MON_I2SINT *((volatile uint8_t *)(0x42627B00UL)) +#define bFM4_INTREQ_IRQ117MON_I2SINT *((volatile uint8_t *)(0x42627B00UL)) +#define bFM_INTREQ_IRQ117MON_PCRC *((volatile uint8_t *)(0x42627B04UL)) +#define bFM4_INTREQ_IRQ117MON_PCRC *((volatile uint8_t *)(0x42627B04UL)) + +#define bFM_INTREQ_IRQ118MON_SDINT0 *((volatile uint8_t *)(0x42627B80UL)) +#define bFM4_INTREQ_IRQ118MON_SDINT0 *((volatile uint8_t *)(0x42627B80UL)) +#define bFM_INTREQ_IRQ118MON_SDINT1 *((volatile uint8_t *)(0x42627B84UL)) +#define bFM4_INTREQ_IRQ118MON_SDINT1 *((volatile uint8_t *)(0x42627B84UL)) + +#define bFM_INTREQ_IRQ119MON_FLINT *((volatile uint8_t *)(0x42627C00UL)) +#define bFM4_INTREQ_IRQ119MON_FLINT *((volatile uint8_t *)(0x42627C00UL)) + +#define bFM_INTREQ_IRQ120MON_MFSINT12_RX *((volatile uint8_t *)(0x42627C80UL)) +#define bFM4_INTREQ_IRQ120MON_MFSINT12_RX *((volatile uint8_t *)(0x42627C80UL)) + +#define bFM_INTREQ_IRQ121MON_MFSINT12_TX *((volatile uint8_t *)(0x42627D00UL)) +#define bFM4_INTREQ_IRQ121MON_MFSINT12_TX *((volatile uint8_t *)(0x42627D00UL)) +#define bFM_INTREQ_IRQ121MON_MFSINT12_STATUS *((volatile uint8_t *)(0x42627D04UL)) +#define bFM4_INTREQ_IRQ121MON_MFSINT12_STATUS *((volatile uint8_t *)(0x42627D04UL)) + +#define bFM_INTREQ_IRQ122MON_MFSINT13_RX *((volatile uint8_t *)(0x42627D80UL)) +#define bFM4_INTREQ_IRQ122MON_MFSINT13_RX *((volatile uint8_t *)(0x42627D80UL)) + +#define bFM_INTREQ_IRQ123MON_MFSINT13_TX *((volatile uint8_t *)(0x42627E00UL)) +#define bFM4_INTREQ_IRQ123MON_MFSINT13_TX *((volatile uint8_t *)(0x42627E00UL)) +#define bFM_INTREQ_IRQ123MON_MFSINT13_STATUS *((volatile uint8_t *)(0x42627E04UL)) +#define bFM4_INTREQ_IRQ123MON_MFSINT13_STATUS *((volatile uint8_t *)(0x42627E04UL)) + +#define bFM_INTREQ_IRQ124MON_MFSINT14_RX *((volatile uint8_t *)(0x42627E80UL)) +#define bFM4_INTREQ_IRQ124MON_MFSINT14_RX *((volatile uint8_t *)(0x42627E80UL)) + +#define bFM_INTREQ_IRQ125MON_MFSINT14_TX *((volatile uint8_t *)(0x42627F00UL)) +#define bFM4_INTREQ_IRQ125MON_MFSINT14_TX *((volatile uint8_t *)(0x42627F00UL)) +#define bFM_INTREQ_IRQ125MON_MFSINT14_STATUS *((volatile uint8_t *)(0x42627F04UL)) +#define bFM4_INTREQ_IRQ125MON_MFSINT14_STATUS *((volatile uint8_t *)(0x42627F04UL)) + +#define bFM_INTREQ_IRQ126MON_MFSINT15_RX *((volatile uint8_t *)(0x42627F80UL)) +#define bFM4_INTREQ_IRQ126MON_MFSINT15_RX *((volatile uint8_t *)(0x42627F80UL)) + +#define bFM_INTREQ_IRQ127MON_MFSINT15_TX *((volatile uint8_t *)(0x42628000UL)) +#define bFM4_INTREQ_IRQ127MON_MFSINT15_TX *((volatile uint8_t *)(0x42628000UL)) +#define bFM_INTREQ_IRQ127MON_MFSINT15_STATUS *((volatile uint8_t *)(0x42628004UL)) +#define bFM4_INTREQ_IRQ127MON_MFSINT15_STATUS *((volatile uint8_t *)(0x42628004UL)) + +#define bFM_INTREQ_ODDPKS_ODDPKS0 *((volatile uint8_t *)(0x42620200UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS0 *((volatile uint8_t *)(0x42620200UL)) +#define bFM_INTREQ_ODDPKS_ODDPKS1 *((volatile uint8_t *)(0x42620204UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS1 *((volatile uint8_t *)(0x42620204UL)) +#define bFM_INTREQ_ODDPKS_ODDPKS2 *((volatile uint8_t *)(0x42620208UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS2 *((volatile uint8_t *)(0x42620208UL)) +#define bFM_INTREQ_ODDPKS_ODDPKS3 *((volatile uint8_t *)(0x4262020CUL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS3 *((volatile uint8_t *)(0x4262020CUL)) +#define bFM_INTREQ_ODDPKS_ODDPKS4 *((volatile uint8_t *)(0x42620210UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS4 *((volatile uint8_t *)(0x42620210UL)) + +#define bFM_INTREQ_ODDPKS1_ODDPKS10 *((volatile uint8_t *)(0x42620280UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS10 *((volatile uint8_t *)(0x42620280UL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS11 *((volatile uint8_t *)(0x42620284UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS11 *((volatile uint8_t *)(0x42620284UL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS12 *((volatile uint8_t *)(0x42620288UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS12 *((volatile uint8_t *)(0x42620288UL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS13 *((volatile uint8_t *)(0x4262028CUL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS13 *((volatile uint8_t *)(0x4262028CUL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS14 *((volatile uint8_t *)(0x42620290UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS14 *((volatile uint8_t *)(0x42620290UL)) + + +/******************************************************************************* +* LSCRP Registers LSCRP +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* LVD Registers LVD +* Bitband Section +*******************************************************************************/ +#define bFM_LVD_LVD_CLR_LVDCL *((volatile uint8_t *)(0x426A011CUL)) +#define bFM4_LVD_LVD_CLR_LVDCL *((volatile uint8_t *)(0x426A011CUL)) + +#define bFM_LVD_LVD_CTL_LVDIE *((volatile uint8_t *)(0x426A001CUL)) +#define bFM4_LVD_LVD_CTL_LVDIE *((volatile uint8_t *)(0x426A001CUL)) + +#define bFM_LVD_LVD_STR_LVDIR *((volatile uint8_t *)(0x426A009CUL)) +#define bFM4_LVD_LVD_STR_LVDIR *((volatile uint8_t *)(0x426A009CUL)) + +#define bFM_LVD_LVD_STR2_LVDIRDY *((volatile uint8_t *)(0x426A021CUL)) +#define bFM4_LVD_LVD_STR2_LVDIRDY *((volatile uint8_t *)(0x426A021CUL)) + + +/******************************************************************************* +* MFS Registers MFS0 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS0_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42700094UL)) +#define bFM4_MFS0_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42700094UL)) +#define bFM_MFS0_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42700098UL)) +#define bFM_MFS0_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270009CUL)) +#define bFM4_MFS0_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270009CUL)) + +#define bFM_MFS0_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_CSIO_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_CSIO_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_CSIO_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_CSIO_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_CSIO_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_CSIO_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42700480UL)) +#define bFM4_MFS0_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42700480UL)) +#define bFM_MFS0_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42700498UL)) +#define bFM4_MFS0_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42700498UL)) +#define bFM_MFS0_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270049CUL)) +#define bFM4_MFS0_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270049CUL)) +#define bFM_MFS0_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427004A0UL)) +#define bFM4_MFS0_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427004A0UL)) +#define bFM_MFS0_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427004ACUL)) +#define bFM4_MFS0_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427004ACUL)) +#define bFM_MFS0_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427004B0UL)) +#define bFM4_MFS0_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427004B0UL)) +#define bFM_MFS0_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427004B4UL)) +#define bFM4_MFS0_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427004B4UL)) + +#define bFM_MFS0_CSIO_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_CSIO_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_CSIO_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_CSIO_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_CSIO_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_CSIO_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_CSIO_SCR_SPI *((volatile uint8_t *)(0x42700034UL)) +#define bFM4_MFS0_CSIO_SCR_SPI *((volatile uint8_t *)(0x42700034UL)) +#define bFM_MFS0_CSIO_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM4_MFS0_CSIO_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM_MFS0_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42700600UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42700600UL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42700604UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42700604UL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42700608UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42700608UL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270060CUL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270060CUL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42700610UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42700610UL)) +#define bFM_MFS0_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42700614UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42700614UL)) +#define bFM_MFS0_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42700624UL)) +#define bFM4_MFS0_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42700624UL)) + +#define bFM_MFS0_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42700694UL)) +#define bFM4_MFS0_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42700694UL)) +#define bFM_MFS0_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42700698UL)) +#define bFM4_MFS0_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42700698UL)) +#define bFM_MFS0_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270069CUL)) +#define bFM4_MFS0_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270069CUL)) + +#define bFM_MFS0_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427006B4UL)) +#define bFM4_MFS0_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427006B4UL)) +#define bFM_MFS0_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427006B8UL)) +#define bFM4_MFS0_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427006B8UL)) +#define bFM_MFS0_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427006BCUL)) +#define bFM4_MFS0_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427006BCUL)) + +#define bFM_MFS0_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42700714UL)) +#define bFM4_MFS0_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42700714UL)) +#define bFM_MFS0_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42700718UL)) +#define bFM4_MFS0_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42700718UL)) +#define bFM_MFS0_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270071CUL)) +#define bFM4_MFS0_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270071CUL)) + +#define bFM_MFS0_CSIO_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM4_MFS0_CSIO_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM_MFS0_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42700004UL)) +#define bFM4_MFS0_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42700004UL)) +#define bFM_MFS0_CSIO_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM4_MFS0_CSIO_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM_MFS0_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270000CUL)) + +#define bFM_MFS0_CSIO_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_CSIO_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_CSIO_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_CSIO_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_CSIO_SSR_AWC *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_CSIO_SSR_AWC *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_CSIO_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_CSIO_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + +#define bFM_MFS0_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427003A0UL)) +#define bFM4_MFS0_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427003A0UL)) +#define bFM_MFS0_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427003A4UL)) +#define bFM4_MFS0_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427003A4UL)) +#define bFM_MFS0_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427003A8UL)) +#define bFM4_MFS0_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427003A8UL)) +#define bFM_MFS0_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427003ACUL)) +#define bFM4_MFS0_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427003ACUL)) +#define bFM_MFS0_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427003B0UL)) +#define bFM4_MFS0_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427003B0UL)) +#define bFM_MFS0_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427003B4UL)) +#define bFM4_MFS0_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427003B4UL)) + +#define bFM_MFS0_I2C_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_I2C_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_I2C_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_I2C_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_I2C_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_I2C_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_I2C_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_I2C_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_I2C_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_I2C_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_I2C_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_I2C_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_I2C_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_I2C_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_I2C_IBCR_INT *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_I2C_IBCR_INT *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_I2C_IBCR_BER *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_I2C_IBCR_BER *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_I2C_IBCR_INTE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_I2C_IBCR_INTE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42700034UL)) +#define bFM4_MFS0_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42700034UL)) +#define bFM_MFS0_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42700038UL)) +#define bFM4_MFS0_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42700038UL)) +#define bFM_MFS0_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_I2C_IBSR_BB *((volatile uint8_t *)(0x42700080UL)) +#define bFM4_MFS0_I2C_IBSR_BB *((volatile uint8_t *)(0x42700080UL)) +#define bFM_MFS0_I2C_IBSR_SPC *((volatile uint8_t *)(0x42700084UL)) +#define bFM4_MFS0_I2C_IBSR_SPC *((volatile uint8_t *)(0x42700084UL)) +#define bFM_MFS0_I2C_IBSR_RSC *((volatile uint8_t *)(0x42700088UL)) +#define bFM4_MFS0_I2C_IBSR_RSC *((volatile uint8_t *)(0x42700088UL)) +#define bFM_MFS0_I2C_IBSR_AL *((volatile uint8_t *)(0x4270008CUL)) +#define bFM4_MFS0_I2C_IBSR_AL *((volatile uint8_t *)(0x4270008CUL)) +#define bFM_MFS0_I2C_IBSR_TRX *((volatile uint8_t *)(0x42700090UL)) +#define bFM4_MFS0_I2C_IBSR_TRX *((volatile uint8_t *)(0x42700090UL)) +#define bFM_MFS0_I2C_IBSR_RSA *((volatile uint8_t *)(0x42700094UL)) +#define bFM4_MFS0_I2C_IBSR_RSA *((volatile uint8_t *)(0x42700094UL)) +#define bFM_MFS0_I2C_IBSR_RACK *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_I2C_IBSR_RACK *((volatile uint8_t *)(0x42700098UL)) +#define bFM_MFS0_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270009CUL)) +#define bFM4_MFS0_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270009CUL)) + +#define bFM_MFS0_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270021CUL)) +#define bFM4_MFS0_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270021CUL)) + +#define bFM_MFS0_I2C_ISMK_EN *((volatile uint8_t *)(0x4270023CUL)) +#define bFM4_MFS0_I2C_ISMK_EN *((volatile uint8_t *)(0x4270023CUL)) + +#define bFM_MFS0_I2C_SMR_TIE *((volatile uint8_t *)(0x42700008UL)) +#define bFM4_MFS0_I2C_SMR_TIE *((volatile uint8_t *)(0x42700008UL)) +#define bFM_MFS0_I2C_SMR_RIE *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_I2C_SMR_RIE *((volatile uint8_t *)(0x4270000CUL)) + +#define bFM_MFS0_I2C_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_I2C_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_I2C_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_I2C_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_I2C_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_I2C_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_I2C_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_I2C_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_I2C_SSR_TBIE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_I2C_SSR_TBIE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_I2C_SSR_DMA *((volatile uint8_t *)(0x427000B4UL)) +#define bFM4_MFS0_I2C_SSR_DMA *((volatile uint8_t *)(0x427000B4UL)) +#define bFM_MFS0_I2C_SSR_TSET *((volatile uint8_t *)(0x427000B8UL)) +#define bFM4_MFS0_I2C_SSR_TSET *((volatile uint8_t *)(0x427000B8UL)) +#define bFM_MFS0_I2C_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_I2C_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + +#define bFM_MFS0_LIN_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) +#define bFM4_MFS0_LIN_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) + +#define bFM_MFS0_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42700090UL)) +#define bFM4_MFS0_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42700090UL)) +#define bFM_MFS0_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) + +#define bFM_MFS0_LIN_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_LIN_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_LIN_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_LIN_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_LIN_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_LIN_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_LIN_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_LIN_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_LIN_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_LIN_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_LIN_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_LIN_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_LIN_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_LIN_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_LIN_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_LIN_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_LIN_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_LIN_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_LIN_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_LIN_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_LIN_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_LIN_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_LIN_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_LIN_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_LIN_SCR_LBR *((volatile uint8_t *)(0x42700034UL)) +#define bFM4_MFS0_LIN_SCR_LBR *((volatile uint8_t *)(0x42700034UL)) +#define bFM_MFS0_LIN_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM4_MFS0_LIN_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM_MFS0_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_LIN_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM4_MFS0_LIN_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM_MFS0_LIN_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_LIN_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) +#define bFM_MFS0_LIN_SMR_WUCR *((volatile uint8_t *)(0x42700010UL)) +#define bFM4_MFS0_LIN_SMR_WUCR *((volatile uint8_t *)(0x42700010UL)) + +#define bFM_MFS0_LIN_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_LIN_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_LIN_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_LIN_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_LIN_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_LIN_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_LIN_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_LIN_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_LIN_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_LIN_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_LIN_SSR_LBD *((volatile uint8_t *)(0x427000B4UL)) +#define bFM4_MFS0_LIN_SSR_LBD *((volatile uint8_t *)(0x427000B4UL)) +#define bFM_MFS0_LIN_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_LIN_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + +#define bFM_MFS0_UART_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) +#define bFM4_MFS0_UART_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) + +#define bFM_MFS0_UART_ESCR_P *((volatile uint8_t *)(0x4270008CUL)) +#define bFM4_MFS0_UART_ESCR_P *((volatile uint8_t *)(0x4270008CUL)) +#define bFM_MFS0_UART_ESCR_PEN *((volatile uint8_t *)(0x42700090UL)) +#define bFM4_MFS0_UART_ESCR_PEN *((volatile uint8_t *)(0x42700090UL)) +#define bFM_MFS0_UART_ESCR_INV *((volatile uint8_t *)(0x42700094UL)) +#define bFM4_MFS0_UART_ESCR_INV *((volatile uint8_t *)(0x42700094UL)) +#define bFM_MFS0_UART_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_UART_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) +#define bFM_MFS0_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270009CUL)) +#define bFM4_MFS0_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270009CUL)) + +#define bFM_MFS0_UART_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_UART_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_UART_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_UART_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_UART_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_UART_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_UART_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_UART_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_UART_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_UART_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_UART_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_UART_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_UART_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_UART_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_UART_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_UART_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_UART_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_UART_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_UART_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_UART_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_UART_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_UART_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_UART_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_UART_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_UART_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_UART_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_UART_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_UART_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_UART_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_UART_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_UART_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_UART_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_UART_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_UART_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_UART_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM4_MFS0_UART_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM_MFS0_UART_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM4_MFS0_UART_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM_MFS0_UART_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_UART_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) + +#define bFM_MFS0_UART_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_UART_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_UART_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_UART_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_UART_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_UART_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_UART_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_UART_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_UART_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_UART_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_UART_SSR_PE *((volatile uint8_t *)(0x427000B4UL)) +#define bFM4_MFS0_UART_SSR_PE *((volatile uint8_t *)(0x427000B4UL)) +#define bFM_MFS0_UART_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_UART_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + + +/******************************************************************************* +* MFS Registers MFS1 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS1_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42702094UL)) +#define bFM4_MFS1_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42702094UL)) +#define bFM_MFS1_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42702098UL)) +#define bFM_MFS1_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270209CUL)) +#define bFM4_MFS1_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270209CUL)) + +#define bFM_MFS1_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_CSIO_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_CSIO_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_CSIO_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_CSIO_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_CSIO_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_CSIO_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42702480UL)) +#define bFM4_MFS1_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42702480UL)) +#define bFM_MFS1_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42702498UL)) +#define bFM4_MFS1_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42702498UL)) +#define bFM_MFS1_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270249CUL)) +#define bFM4_MFS1_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270249CUL)) +#define bFM_MFS1_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427024A0UL)) +#define bFM4_MFS1_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427024A0UL)) +#define bFM_MFS1_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427024ACUL)) +#define bFM4_MFS1_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427024ACUL)) +#define bFM_MFS1_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427024B0UL)) +#define bFM4_MFS1_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427024B0UL)) +#define bFM_MFS1_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427024B4UL)) +#define bFM4_MFS1_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427024B4UL)) + +#define bFM_MFS1_CSIO_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_CSIO_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_CSIO_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_CSIO_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_CSIO_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_CSIO_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_CSIO_SCR_SPI *((volatile uint8_t *)(0x42702034UL)) +#define bFM4_MFS1_CSIO_SCR_SPI *((volatile uint8_t *)(0x42702034UL)) +#define bFM_MFS1_CSIO_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM4_MFS1_CSIO_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM_MFS1_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42702600UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42702600UL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42702604UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42702604UL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42702608UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42702608UL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270260CUL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270260CUL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42702610UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42702610UL)) +#define bFM_MFS1_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42702614UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42702614UL)) +#define bFM_MFS1_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42702624UL)) +#define bFM4_MFS1_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42702624UL)) + +#define bFM_MFS1_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42702694UL)) +#define bFM4_MFS1_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42702694UL)) +#define bFM_MFS1_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42702698UL)) +#define bFM4_MFS1_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42702698UL)) +#define bFM_MFS1_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270269CUL)) +#define bFM4_MFS1_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270269CUL)) + +#define bFM_MFS1_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427026B4UL)) +#define bFM4_MFS1_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427026B4UL)) +#define bFM_MFS1_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427026B8UL)) +#define bFM4_MFS1_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427026B8UL)) +#define bFM_MFS1_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427026BCUL)) +#define bFM4_MFS1_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427026BCUL)) + +#define bFM_MFS1_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42702714UL)) +#define bFM4_MFS1_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42702714UL)) +#define bFM_MFS1_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42702718UL)) +#define bFM4_MFS1_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42702718UL)) +#define bFM_MFS1_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270271CUL)) +#define bFM4_MFS1_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270271CUL)) + +#define bFM_MFS1_CSIO_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM4_MFS1_CSIO_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM_MFS1_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42702004UL)) +#define bFM4_MFS1_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42702004UL)) +#define bFM_MFS1_CSIO_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM4_MFS1_CSIO_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM_MFS1_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270200CUL)) + +#define bFM_MFS1_CSIO_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_CSIO_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_CSIO_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_CSIO_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_CSIO_SSR_AWC *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_CSIO_SSR_AWC *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_CSIO_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_CSIO_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + +#define bFM_MFS1_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427023A0UL)) +#define bFM4_MFS1_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427023A0UL)) +#define bFM_MFS1_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427023A4UL)) +#define bFM4_MFS1_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427023A4UL)) +#define bFM_MFS1_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427023A8UL)) +#define bFM4_MFS1_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427023A8UL)) +#define bFM_MFS1_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427023ACUL)) +#define bFM4_MFS1_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427023ACUL)) +#define bFM_MFS1_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427023B0UL)) +#define bFM4_MFS1_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427023B0UL)) +#define bFM_MFS1_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427023B4UL)) +#define bFM4_MFS1_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427023B4UL)) + +#define bFM_MFS1_I2C_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_I2C_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_I2C_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_I2C_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_I2C_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_I2C_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_I2C_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_I2C_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_I2C_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_I2C_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_I2C_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_I2C_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_I2C_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_I2C_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_I2C_IBCR_INT *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_I2C_IBCR_INT *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_I2C_IBCR_BER *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_I2C_IBCR_BER *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_I2C_IBCR_INTE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_I2C_IBCR_INTE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42702034UL)) +#define bFM4_MFS1_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42702034UL)) +#define bFM_MFS1_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42702038UL)) +#define bFM4_MFS1_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42702038UL)) +#define bFM_MFS1_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_I2C_IBSR_BB *((volatile uint8_t *)(0x42702080UL)) +#define bFM4_MFS1_I2C_IBSR_BB *((volatile uint8_t *)(0x42702080UL)) +#define bFM_MFS1_I2C_IBSR_SPC *((volatile uint8_t *)(0x42702084UL)) +#define bFM4_MFS1_I2C_IBSR_SPC *((volatile uint8_t *)(0x42702084UL)) +#define bFM_MFS1_I2C_IBSR_RSC *((volatile uint8_t *)(0x42702088UL)) +#define bFM4_MFS1_I2C_IBSR_RSC *((volatile uint8_t *)(0x42702088UL)) +#define bFM_MFS1_I2C_IBSR_AL *((volatile uint8_t *)(0x4270208CUL)) +#define bFM4_MFS1_I2C_IBSR_AL *((volatile uint8_t *)(0x4270208CUL)) +#define bFM_MFS1_I2C_IBSR_TRX *((volatile uint8_t *)(0x42702090UL)) +#define bFM4_MFS1_I2C_IBSR_TRX *((volatile uint8_t *)(0x42702090UL)) +#define bFM_MFS1_I2C_IBSR_RSA *((volatile uint8_t *)(0x42702094UL)) +#define bFM4_MFS1_I2C_IBSR_RSA *((volatile uint8_t *)(0x42702094UL)) +#define bFM_MFS1_I2C_IBSR_RACK *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_I2C_IBSR_RACK *((volatile uint8_t *)(0x42702098UL)) +#define bFM_MFS1_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270209CUL)) +#define bFM4_MFS1_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270209CUL)) + +#define bFM_MFS1_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270221CUL)) +#define bFM4_MFS1_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270221CUL)) + +#define bFM_MFS1_I2C_ISMK_EN *((volatile uint8_t *)(0x4270223CUL)) +#define bFM4_MFS1_I2C_ISMK_EN *((volatile uint8_t *)(0x4270223CUL)) + +#define bFM_MFS1_I2C_SMR_TIE *((volatile uint8_t *)(0x42702008UL)) +#define bFM4_MFS1_I2C_SMR_TIE *((volatile uint8_t *)(0x42702008UL)) +#define bFM_MFS1_I2C_SMR_RIE *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_I2C_SMR_RIE *((volatile uint8_t *)(0x4270200CUL)) + +#define bFM_MFS1_I2C_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_I2C_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_I2C_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_I2C_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_I2C_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_I2C_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_I2C_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_I2C_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_I2C_SSR_TBIE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_I2C_SSR_TBIE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_I2C_SSR_DMA *((volatile uint8_t *)(0x427020B4UL)) +#define bFM4_MFS1_I2C_SSR_DMA *((volatile uint8_t *)(0x427020B4UL)) +#define bFM_MFS1_I2C_SSR_TSET *((volatile uint8_t *)(0x427020B8UL)) +#define bFM4_MFS1_I2C_SSR_TSET *((volatile uint8_t *)(0x427020B8UL)) +#define bFM_MFS1_I2C_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_I2C_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + +#define bFM_MFS1_LIN_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) +#define bFM4_MFS1_LIN_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) + +#define bFM_MFS1_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42702090UL)) +#define bFM4_MFS1_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42702090UL)) +#define bFM_MFS1_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) + +#define bFM_MFS1_LIN_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_LIN_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_LIN_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_LIN_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_LIN_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_LIN_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_LIN_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_LIN_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_LIN_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_LIN_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_LIN_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_LIN_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_LIN_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_LIN_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_LIN_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_LIN_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_LIN_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_LIN_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_LIN_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_LIN_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_LIN_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_LIN_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_LIN_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_LIN_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_LIN_SCR_LBR *((volatile uint8_t *)(0x42702034UL)) +#define bFM4_MFS1_LIN_SCR_LBR *((volatile uint8_t *)(0x42702034UL)) +#define bFM_MFS1_LIN_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM4_MFS1_LIN_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM_MFS1_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_LIN_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM4_MFS1_LIN_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM_MFS1_LIN_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_LIN_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) +#define bFM_MFS1_LIN_SMR_WUCR *((volatile uint8_t *)(0x42702010UL)) +#define bFM4_MFS1_LIN_SMR_WUCR *((volatile uint8_t *)(0x42702010UL)) + +#define bFM_MFS1_LIN_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_LIN_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_LIN_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_LIN_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_LIN_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_LIN_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_LIN_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_LIN_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_LIN_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_LIN_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_LIN_SSR_LBD *((volatile uint8_t *)(0x427020B4UL)) +#define bFM4_MFS1_LIN_SSR_LBD *((volatile uint8_t *)(0x427020B4UL)) +#define bFM_MFS1_LIN_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_LIN_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + +#define bFM_MFS1_UART_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) +#define bFM4_MFS1_UART_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) + +#define bFM_MFS1_UART_ESCR_P *((volatile uint8_t *)(0x4270208CUL)) +#define bFM4_MFS1_UART_ESCR_P *((volatile uint8_t *)(0x4270208CUL)) +#define bFM_MFS1_UART_ESCR_PEN *((volatile uint8_t *)(0x42702090UL)) +#define bFM4_MFS1_UART_ESCR_PEN *((volatile uint8_t *)(0x42702090UL)) +#define bFM_MFS1_UART_ESCR_INV *((volatile uint8_t *)(0x42702094UL)) +#define bFM4_MFS1_UART_ESCR_INV *((volatile uint8_t *)(0x42702094UL)) +#define bFM_MFS1_UART_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_UART_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) +#define bFM_MFS1_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270209CUL)) +#define bFM4_MFS1_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270209CUL)) + +#define bFM_MFS1_UART_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_UART_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_UART_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_UART_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_UART_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_UART_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_UART_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_UART_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_UART_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_UART_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_UART_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_UART_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_UART_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_UART_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_UART_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_UART_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_UART_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_UART_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_UART_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_UART_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_UART_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_UART_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_UART_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_UART_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_UART_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_UART_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_UART_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_UART_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_UART_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_UART_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_UART_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_UART_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_UART_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_UART_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_UART_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM4_MFS1_UART_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM_MFS1_UART_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM4_MFS1_UART_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM_MFS1_UART_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_UART_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) + +#define bFM_MFS1_UART_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_UART_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_UART_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_UART_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_UART_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_UART_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_UART_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_UART_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_UART_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_UART_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_UART_SSR_PE *((volatile uint8_t *)(0x427020B4UL)) +#define bFM4_MFS1_UART_SSR_PE *((volatile uint8_t *)(0x427020B4UL)) +#define bFM_MFS1_UART_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_UART_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + + +/******************************************************************************* +* MFS Registers MFS10 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS10_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42714094UL)) +#define bFM4_MFS10_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42714094UL)) +#define bFM_MFS10_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42714098UL)) +#define bFM_MFS10_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271409CUL)) +#define bFM4_MFS10_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271409CUL)) + +#define bFM_MFS10_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_CSIO_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_CSIO_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_CSIO_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_CSIO_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_CSIO_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_CSIO_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42714480UL)) +#define bFM4_MFS10_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42714480UL)) +#define bFM_MFS10_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42714498UL)) +#define bFM4_MFS10_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42714498UL)) +#define bFM_MFS10_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271449CUL)) +#define bFM4_MFS10_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271449CUL)) +#define bFM_MFS10_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427144A0UL)) +#define bFM4_MFS10_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427144A0UL)) +#define bFM_MFS10_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427144ACUL)) +#define bFM4_MFS10_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427144ACUL)) +#define bFM_MFS10_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427144B0UL)) +#define bFM4_MFS10_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427144B0UL)) +#define bFM_MFS10_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427144B4UL)) +#define bFM4_MFS10_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427144B4UL)) + +#define bFM_MFS10_CSIO_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_CSIO_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_CSIO_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_CSIO_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_CSIO_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_CSIO_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_CSIO_SCR_SPI *((volatile uint8_t *)(0x42714034UL)) +#define bFM4_MFS10_CSIO_SCR_SPI *((volatile uint8_t *)(0x42714034UL)) +#define bFM_MFS10_CSIO_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM4_MFS10_CSIO_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM_MFS10_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42714600UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42714600UL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42714604UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42714604UL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42714608UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42714608UL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271460CUL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271460CUL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42714610UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42714610UL)) +#define bFM_MFS10_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42714614UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42714614UL)) +#define bFM_MFS10_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42714624UL)) +#define bFM4_MFS10_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42714624UL)) + +#define bFM_MFS10_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42714694UL)) +#define bFM4_MFS10_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42714694UL)) +#define bFM_MFS10_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42714698UL)) +#define bFM4_MFS10_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42714698UL)) +#define bFM_MFS10_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271469CUL)) +#define bFM4_MFS10_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271469CUL)) + +#define bFM_MFS10_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427146B4UL)) +#define bFM4_MFS10_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427146B4UL)) +#define bFM_MFS10_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427146B8UL)) +#define bFM4_MFS10_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427146B8UL)) +#define bFM_MFS10_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427146BCUL)) +#define bFM4_MFS10_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427146BCUL)) + +#define bFM_MFS10_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42714714UL)) +#define bFM4_MFS10_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42714714UL)) +#define bFM_MFS10_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42714718UL)) +#define bFM4_MFS10_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42714718UL)) +#define bFM_MFS10_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271471CUL)) +#define bFM4_MFS10_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271471CUL)) + +#define bFM_MFS10_CSIO_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM4_MFS10_CSIO_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM_MFS10_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42714004UL)) +#define bFM4_MFS10_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42714004UL)) +#define bFM_MFS10_CSIO_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM4_MFS10_CSIO_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM_MFS10_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271400CUL)) + +#define bFM_MFS10_CSIO_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_CSIO_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_CSIO_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_CSIO_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_CSIO_SSR_AWC *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_CSIO_SSR_AWC *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_CSIO_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_CSIO_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + +#define bFM_MFS10_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427143A0UL)) +#define bFM4_MFS10_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427143A0UL)) +#define bFM_MFS10_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427143A4UL)) +#define bFM4_MFS10_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427143A4UL)) +#define bFM_MFS10_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427143A8UL)) +#define bFM4_MFS10_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427143A8UL)) +#define bFM_MFS10_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427143ACUL)) +#define bFM4_MFS10_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427143ACUL)) +#define bFM_MFS10_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427143B0UL)) +#define bFM4_MFS10_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427143B0UL)) +#define bFM_MFS10_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427143B4UL)) +#define bFM4_MFS10_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427143B4UL)) + +#define bFM_MFS10_I2C_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_I2C_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_I2C_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_I2C_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_I2C_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_I2C_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_I2C_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_I2C_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_I2C_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_I2C_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_I2C_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_I2C_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_I2C_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_I2C_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_I2C_IBCR_INT *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_I2C_IBCR_INT *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_I2C_IBCR_BER *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_I2C_IBCR_BER *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_I2C_IBCR_INTE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_I2C_IBCR_INTE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42714034UL)) +#define bFM4_MFS10_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42714034UL)) +#define bFM_MFS10_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42714038UL)) +#define bFM4_MFS10_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42714038UL)) +#define bFM_MFS10_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_I2C_IBSR_BB *((volatile uint8_t *)(0x42714080UL)) +#define bFM4_MFS10_I2C_IBSR_BB *((volatile uint8_t *)(0x42714080UL)) +#define bFM_MFS10_I2C_IBSR_SPC *((volatile uint8_t *)(0x42714084UL)) +#define bFM4_MFS10_I2C_IBSR_SPC *((volatile uint8_t *)(0x42714084UL)) +#define bFM_MFS10_I2C_IBSR_RSC *((volatile uint8_t *)(0x42714088UL)) +#define bFM4_MFS10_I2C_IBSR_RSC *((volatile uint8_t *)(0x42714088UL)) +#define bFM_MFS10_I2C_IBSR_AL *((volatile uint8_t *)(0x4271408CUL)) +#define bFM4_MFS10_I2C_IBSR_AL *((volatile uint8_t *)(0x4271408CUL)) +#define bFM_MFS10_I2C_IBSR_TRX *((volatile uint8_t *)(0x42714090UL)) +#define bFM4_MFS10_I2C_IBSR_TRX *((volatile uint8_t *)(0x42714090UL)) +#define bFM_MFS10_I2C_IBSR_RSA *((volatile uint8_t *)(0x42714094UL)) +#define bFM4_MFS10_I2C_IBSR_RSA *((volatile uint8_t *)(0x42714094UL)) +#define bFM_MFS10_I2C_IBSR_RACK *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_I2C_IBSR_RACK *((volatile uint8_t *)(0x42714098UL)) +#define bFM_MFS10_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271409CUL)) +#define bFM4_MFS10_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271409CUL)) + +#define bFM_MFS10_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271421CUL)) +#define bFM4_MFS10_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271421CUL)) + +#define bFM_MFS10_I2C_ISMK_EN *((volatile uint8_t *)(0x4271423CUL)) +#define bFM4_MFS10_I2C_ISMK_EN *((volatile uint8_t *)(0x4271423CUL)) + +#define bFM_MFS10_I2C_SMR_TIE *((volatile uint8_t *)(0x42714008UL)) +#define bFM4_MFS10_I2C_SMR_TIE *((volatile uint8_t *)(0x42714008UL)) +#define bFM_MFS10_I2C_SMR_RIE *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_I2C_SMR_RIE *((volatile uint8_t *)(0x4271400CUL)) + +#define bFM_MFS10_I2C_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_I2C_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_I2C_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_I2C_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_I2C_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_I2C_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_I2C_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_I2C_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_I2C_SSR_TBIE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_I2C_SSR_TBIE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_I2C_SSR_DMA *((volatile uint8_t *)(0x427140B4UL)) +#define bFM4_MFS10_I2C_SSR_DMA *((volatile uint8_t *)(0x427140B4UL)) +#define bFM_MFS10_I2C_SSR_TSET *((volatile uint8_t *)(0x427140B8UL)) +#define bFM4_MFS10_I2C_SSR_TSET *((volatile uint8_t *)(0x427140B8UL)) +#define bFM_MFS10_I2C_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_I2C_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + +#define bFM_MFS10_LIN_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) +#define bFM4_MFS10_LIN_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) + +#define bFM_MFS10_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42714090UL)) +#define bFM4_MFS10_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42714090UL)) +#define bFM_MFS10_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) + +#define bFM_MFS10_LIN_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_LIN_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_LIN_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_LIN_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_LIN_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_LIN_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_LIN_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_LIN_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_LIN_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_LIN_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_LIN_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_LIN_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_LIN_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_LIN_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_LIN_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_LIN_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_LIN_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_LIN_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_LIN_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_LIN_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_LIN_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_LIN_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_LIN_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_LIN_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_LIN_SCR_LBR *((volatile uint8_t *)(0x42714034UL)) +#define bFM4_MFS10_LIN_SCR_LBR *((volatile uint8_t *)(0x42714034UL)) +#define bFM_MFS10_LIN_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM4_MFS10_LIN_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM_MFS10_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_LIN_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM4_MFS10_LIN_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM_MFS10_LIN_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_LIN_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) +#define bFM_MFS10_LIN_SMR_WUCR *((volatile uint8_t *)(0x42714010UL)) +#define bFM4_MFS10_LIN_SMR_WUCR *((volatile uint8_t *)(0x42714010UL)) + +#define bFM_MFS10_LIN_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_LIN_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_LIN_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_LIN_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_LIN_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_LIN_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_LIN_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_LIN_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_LIN_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_LIN_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_LIN_SSR_LBD *((volatile uint8_t *)(0x427140B4UL)) +#define bFM4_MFS10_LIN_SSR_LBD *((volatile uint8_t *)(0x427140B4UL)) +#define bFM_MFS10_LIN_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_LIN_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + +#define bFM_MFS10_UART_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) +#define bFM4_MFS10_UART_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) + +#define bFM_MFS10_UART_ESCR_P *((volatile uint8_t *)(0x4271408CUL)) +#define bFM4_MFS10_UART_ESCR_P *((volatile uint8_t *)(0x4271408CUL)) +#define bFM_MFS10_UART_ESCR_PEN *((volatile uint8_t *)(0x42714090UL)) +#define bFM4_MFS10_UART_ESCR_PEN *((volatile uint8_t *)(0x42714090UL)) +#define bFM_MFS10_UART_ESCR_INV *((volatile uint8_t *)(0x42714094UL)) +#define bFM4_MFS10_UART_ESCR_INV *((volatile uint8_t *)(0x42714094UL)) +#define bFM_MFS10_UART_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_UART_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) +#define bFM_MFS10_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271409CUL)) +#define bFM4_MFS10_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271409CUL)) + +#define bFM_MFS10_UART_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_UART_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_UART_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_UART_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_UART_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_UART_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_UART_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_UART_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_UART_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_UART_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_UART_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_UART_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_UART_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_UART_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_UART_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_UART_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_UART_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_UART_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_UART_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_UART_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_UART_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_UART_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_UART_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_UART_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_UART_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_UART_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_UART_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_UART_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_UART_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_UART_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_UART_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_UART_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_UART_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_UART_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_UART_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM4_MFS10_UART_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM_MFS10_UART_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM4_MFS10_UART_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM_MFS10_UART_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_UART_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) + +#define bFM_MFS10_UART_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_UART_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_UART_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_UART_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_UART_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_UART_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_UART_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_UART_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_UART_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_UART_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_UART_SSR_PE *((volatile uint8_t *)(0x427140B4UL)) +#define bFM4_MFS10_UART_SSR_PE *((volatile uint8_t *)(0x427140B4UL)) +#define bFM_MFS10_UART_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_UART_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + + +/******************************************************************************* +* MFS Registers MFS11 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS11_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42716094UL)) +#define bFM4_MFS11_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42716094UL)) +#define bFM_MFS11_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42716098UL)) +#define bFM_MFS11_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271609CUL)) +#define bFM4_MFS11_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271609CUL)) + +#define bFM_MFS11_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_CSIO_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_CSIO_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_CSIO_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_CSIO_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_CSIO_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_CSIO_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42716480UL)) +#define bFM4_MFS11_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42716480UL)) +#define bFM_MFS11_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42716498UL)) +#define bFM4_MFS11_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42716498UL)) +#define bFM_MFS11_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271649CUL)) +#define bFM4_MFS11_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271649CUL)) +#define bFM_MFS11_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427164A0UL)) +#define bFM4_MFS11_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427164A0UL)) +#define bFM_MFS11_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427164ACUL)) +#define bFM4_MFS11_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427164ACUL)) +#define bFM_MFS11_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427164B0UL)) +#define bFM4_MFS11_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427164B0UL)) +#define bFM_MFS11_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427164B4UL)) +#define bFM4_MFS11_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427164B4UL)) + +#define bFM_MFS11_CSIO_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_CSIO_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_CSIO_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_CSIO_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_CSIO_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_CSIO_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_CSIO_SCR_SPI *((volatile uint8_t *)(0x42716034UL)) +#define bFM4_MFS11_CSIO_SCR_SPI *((volatile uint8_t *)(0x42716034UL)) +#define bFM_MFS11_CSIO_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM4_MFS11_CSIO_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM_MFS11_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42716600UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42716600UL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42716604UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42716604UL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42716608UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42716608UL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271660CUL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271660CUL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42716610UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42716610UL)) +#define bFM_MFS11_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42716614UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42716614UL)) +#define bFM_MFS11_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42716624UL)) +#define bFM4_MFS11_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42716624UL)) + +#define bFM_MFS11_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42716694UL)) +#define bFM4_MFS11_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42716694UL)) +#define bFM_MFS11_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42716698UL)) +#define bFM4_MFS11_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42716698UL)) +#define bFM_MFS11_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271669CUL)) +#define bFM4_MFS11_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271669CUL)) + +#define bFM_MFS11_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427166B4UL)) +#define bFM4_MFS11_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427166B4UL)) +#define bFM_MFS11_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427166B8UL)) +#define bFM4_MFS11_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427166B8UL)) +#define bFM_MFS11_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427166BCUL)) +#define bFM4_MFS11_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427166BCUL)) + +#define bFM_MFS11_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42716714UL)) +#define bFM4_MFS11_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42716714UL)) +#define bFM_MFS11_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42716718UL)) +#define bFM4_MFS11_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42716718UL)) +#define bFM_MFS11_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271671CUL)) +#define bFM4_MFS11_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271671CUL)) + +#define bFM_MFS11_CSIO_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM4_MFS11_CSIO_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM_MFS11_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42716004UL)) +#define bFM4_MFS11_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42716004UL)) +#define bFM_MFS11_CSIO_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM4_MFS11_CSIO_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM_MFS11_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271600CUL)) + +#define bFM_MFS11_CSIO_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_CSIO_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_CSIO_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_CSIO_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_CSIO_SSR_AWC *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_CSIO_SSR_AWC *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_CSIO_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_CSIO_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + +#define bFM_MFS11_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427163A0UL)) +#define bFM4_MFS11_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427163A0UL)) +#define bFM_MFS11_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427163A4UL)) +#define bFM4_MFS11_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427163A4UL)) +#define bFM_MFS11_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427163A8UL)) +#define bFM4_MFS11_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427163A8UL)) +#define bFM_MFS11_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427163ACUL)) +#define bFM4_MFS11_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427163ACUL)) +#define bFM_MFS11_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427163B0UL)) +#define bFM4_MFS11_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427163B0UL)) +#define bFM_MFS11_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427163B4UL)) +#define bFM4_MFS11_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427163B4UL)) + +#define bFM_MFS11_I2C_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_I2C_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_I2C_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_I2C_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_I2C_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_I2C_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_I2C_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_I2C_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_I2C_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_I2C_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_I2C_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_I2C_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_I2C_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_I2C_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_I2C_IBCR_INT *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_I2C_IBCR_INT *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_I2C_IBCR_BER *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_I2C_IBCR_BER *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_I2C_IBCR_INTE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_I2C_IBCR_INTE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42716034UL)) +#define bFM4_MFS11_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42716034UL)) +#define bFM_MFS11_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42716038UL)) +#define bFM4_MFS11_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42716038UL)) +#define bFM_MFS11_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_I2C_IBSR_BB *((volatile uint8_t *)(0x42716080UL)) +#define bFM4_MFS11_I2C_IBSR_BB *((volatile uint8_t *)(0x42716080UL)) +#define bFM_MFS11_I2C_IBSR_SPC *((volatile uint8_t *)(0x42716084UL)) +#define bFM4_MFS11_I2C_IBSR_SPC *((volatile uint8_t *)(0x42716084UL)) +#define bFM_MFS11_I2C_IBSR_RSC *((volatile uint8_t *)(0x42716088UL)) +#define bFM4_MFS11_I2C_IBSR_RSC *((volatile uint8_t *)(0x42716088UL)) +#define bFM_MFS11_I2C_IBSR_AL *((volatile uint8_t *)(0x4271608CUL)) +#define bFM4_MFS11_I2C_IBSR_AL *((volatile uint8_t *)(0x4271608CUL)) +#define bFM_MFS11_I2C_IBSR_TRX *((volatile uint8_t *)(0x42716090UL)) +#define bFM4_MFS11_I2C_IBSR_TRX *((volatile uint8_t *)(0x42716090UL)) +#define bFM_MFS11_I2C_IBSR_RSA *((volatile uint8_t *)(0x42716094UL)) +#define bFM4_MFS11_I2C_IBSR_RSA *((volatile uint8_t *)(0x42716094UL)) +#define bFM_MFS11_I2C_IBSR_RACK *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_I2C_IBSR_RACK *((volatile uint8_t *)(0x42716098UL)) +#define bFM_MFS11_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271609CUL)) +#define bFM4_MFS11_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271609CUL)) + +#define bFM_MFS11_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271621CUL)) +#define bFM4_MFS11_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271621CUL)) + +#define bFM_MFS11_I2C_ISMK_EN *((volatile uint8_t *)(0x4271623CUL)) +#define bFM4_MFS11_I2C_ISMK_EN *((volatile uint8_t *)(0x4271623CUL)) + +#define bFM_MFS11_I2C_SMR_TIE *((volatile uint8_t *)(0x42716008UL)) +#define bFM4_MFS11_I2C_SMR_TIE *((volatile uint8_t *)(0x42716008UL)) +#define bFM_MFS11_I2C_SMR_RIE *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_I2C_SMR_RIE *((volatile uint8_t *)(0x4271600CUL)) + +#define bFM_MFS11_I2C_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_I2C_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_I2C_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_I2C_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_I2C_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_I2C_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_I2C_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_I2C_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_I2C_SSR_TBIE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_I2C_SSR_TBIE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_I2C_SSR_DMA *((volatile uint8_t *)(0x427160B4UL)) +#define bFM4_MFS11_I2C_SSR_DMA *((volatile uint8_t *)(0x427160B4UL)) +#define bFM_MFS11_I2C_SSR_TSET *((volatile uint8_t *)(0x427160B8UL)) +#define bFM4_MFS11_I2C_SSR_TSET *((volatile uint8_t *)(0x427160B8UL)) +#define bFM_MFS11_I2C_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_I2C_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + +#define bFM_MFS11_LIN_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) +#define bFM4_MFS11_LIN_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) + +#define bFM_MFS11_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42716090UL)) +#define bFM4_MFS11_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42716090UL)) +#define bFM_MFS11_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) + +#define bFM_MFS11_LIN_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_LIN_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_LIN_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_LIN_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_LIN_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_LIN_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_LIN_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_LIN_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_LIN_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_LIN_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_LIN_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_LIN_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_LIN_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_LIN_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_LIN_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_LIN_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_LIN_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_LIN_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_LIN_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_LIN_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_LIN_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_LIN_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_LIN_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_LIN_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_LIN_SCR_LBR *((volatile uint8_t *)(0x42716034UL)) +#define bFM4_MFS11_LIN_SCR_LBR *((volatile uint8_t *)(0x42716034UL)) +#define bFM_MFS11_LIN_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM4_MFS11_LIN_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM_MFS11_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_LIN_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM4_MFS11_LIN_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM_MFS11_LIN_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_LIN_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) +#define bFM_MFS11_LIN_SMR_WUCR *((volatile uint8_t *)(0x42716010UL)) +#define bFM4_MFS11_LIN_SMR_WUCR *((volatile uint8_t *)(0x42716010UL)) + +#define bFM_MFS11_LIN_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_LIN_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_LIN_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_LIN_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_LIN_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_LIN_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_LIN_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_LIN_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_LIN_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_LIN_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_LIN_SSR_LBD *((volatile uint8_t *)(0x427160B4UL)) +#define bFM4_MFS11_LIN_SSR_LBD *((volatile uint8_t *)(0x427160B4UL)) +#define bFM_MFS11_LIN_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_LIN_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + +#define bFM_MFS11_UART_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) +#define bFM4_MFS11_UART_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) + +#define bFM_MFS11_UART_ESCR_P *((volatile uint8_t *)(0x4271608CUL)) +#define bFM4_MFS11_UART_ESCR_P *((volatile uint8_t *)(0x4271608CUL)) +#define bFM_MFS11_UART_ESCR_PEN *((volatile uint8_t *)(0x42716090UL)) +#define bFM4_MFS11_UART_ESCR_PEN *((volatile uint8_t *)(0x42716090UL)) +#define bFM_MFS11_UART_ESCR_INV *((volatile uint8_t *)(0x42716094UL)) +#define bFM4_MFS11_UART_ESCR_INV *((volatile uint8_t *)(0x42716094UL)) +#define bFM_MFS11_UART_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_UART_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) +#define bFM_MFS11_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271609CUL)) +#define bFM4_MFS11_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271609CUL)) + +#define bFM_MFS11_UART_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_UART_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_UART_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_UART_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_UART_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_UART_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_UART_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_UART_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_UART_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_UART_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_UART_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_UART_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_UART_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_UART_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_UART_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_UART_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_UART_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_UART_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_UART_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_UART_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_UART_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_UART_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_UART_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_UART_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_UART_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_UART_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_UART_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_UART_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_UART_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_UART_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_UART_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_UART_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_UART_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_UART_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_UART_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM4_MFS11_UART_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM_MFS11_UART_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM4_MFS11_UART_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM_MFS11_UART_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_UART_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) + +#define bFM_MFS11_UART_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_UART_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_UART_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_UART_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_UART_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_UART_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_UART_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_UART_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_UART_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_UART_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_UART_SSR_PE *((volatile uint8_t *)(0x427160B4UL)) +#define bFM4_MFS11_UART_SSR_PE *((volatile uint8_t *)(0x427160B4UL)) +#define bFM_MFS11_UART_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_UART_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + + +/******************************************************************************* +* MFS Registers MFS12 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS12_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42718094UL)) +#define bFM4_MFS12_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42718094UL)) +#define bFM_MFS12_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42718098UL)) +#define bFM_MFS12_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271809CUL)) +#define bFM4_MFS12_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271809CUL)) + +#define bFM_MFS12_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_CSIO_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_CSIO_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_CSIO_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_CSIO_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_CSIO_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_CSIO_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42718480UL)) +#define bFM4_MFS12_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42718480UL)) +#define bFM_MFS12_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42718498UL)) +#define bFM4_MFS12_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42718498UL)) +#define bFM_MFS12_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271849CUL)) +#define bFM4_MFS12_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271849CUL)) +#define bFM_MFS12_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427184A0UL)) +#define bFM4_MFS12_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427184A0UL)) +#define bFM_MFS12_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427184ACUL)) +#define bFM4_MFS12_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427184ACUL)) +#define bFM_MFS12_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427184B0UL)) +#define bFM4_MFS12_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427184B0UL)) +#define bFM_MFS12_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427184B4UL)) +#define bFM4_MFS12_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427184B4UL)) + +#define bFM_MFS12_CSIO_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_CSIO_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_CSIO_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_CSIO_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_CSIO_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_CSIO_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_CSIO_SCR_SPI *((volatile uint8_t *)(0x42718034UL)) +#define bFM4_MFS12_CSIO_SCR_SPI *((volatile uint8_t *)(0x42718034UL)) +#define bFM_MFS12_CSIO_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM4_MFS12_CSIO_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM_MFS12_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42718600UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42718600UL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42718604UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42718604UL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42718608UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42718608UL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271860CUL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271860CUL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42718610UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42718610UL)) +#define bFM_MFS12_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42718614UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42718614UL)) +#define bFM_MFS12_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42718624UL)) +#define bFM4_MFS12_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42718624UL)) + +#define bFM_MFS12_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42718694UL)) +#define bFM4_MFS12_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42718694UL)) +#define bFM_MFS12_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42718698UL)) +#define bFM4_MFS12_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42718698UL)) +#define bFM_MFS12_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271869CUL)) +#define bFM4_MFS12_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271869CUL)) + +#define bFM_MFS12_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427186B4UL)) +#define bFM4_MFS12_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427186B4UL)) +#define bFM_MFS12_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427186B8UL)) +#define bFM4_MFS12_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427186B8UL)) +#define bFM_MFS12_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427186BCUL)) +#define bFM4_MFS12_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427186BCUL)) + +#define bFM_MFS12_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42718714UL)) +#define bFM4_MFS12_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42718714UL)) +#define bFM_MFS12_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42718718UL)) +#define bFM4_MFS12_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42718718UL)) +#define bFM_MFS12_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271871CUL)) +#define bFM4_MFS12_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271871CUL)) + +#define bFM_MFS12_CSIO_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM4_MFS12_CSIO_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM_MFS12_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42718004UL)) +#define bFM4_MFS12_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42718004UL)) +#define bFM_MFS12_CSIO_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM4_MFS12_CSIO_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM_MFS12_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271800CUL)) + +#define bFM_MFS12_CSIO_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_CSIO_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_CSIO_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_CSIO_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_CSIO_SSR_AWC *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_CSIO_SSR_AWC *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_CSIO_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_CSIO_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + +#define bFM_MFS12_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427183A0UL)) +#define bFM4_MFS12_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427183A0UL)) +#define bFM_MFS12_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427183A4UL)) +#define bFM4_MFS12_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427183A4UL)) +#define bFM_MFS12_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427183A8UL)) +#define bFM4_MFS12_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427183A8UL)) +#define bFM_MFS12_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427183ACUL)) +#define bFM4_MFS12_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427183ACUL)) +#define bFM_MFS12_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427183B0UL)) +#define bFM4_MFS12_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427183B0UL)) +#define bFM_MFS12_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427183B4UL)) +#define bFM4_MFS12_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427183B4UL)) + +#define bFM_MFS12_I2C_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_I2C_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_I2C_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_I2C_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_I2C_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_I2C_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_I2C_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_I2C_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_I2C_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_I2C_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_I2C_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_I2C_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_I2C_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_I2C_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_I2C_IBCR_INT *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_I2C_IBCR_INT *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_I2C_IBCR_BER *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_I2C_IBCR_BER *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_I2C_IBCR_INTE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_I2C_IBCR_INTE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42718034UL)) +#define bFM4_MFS12_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42718034UL)) +#define bFM_MFS12_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42718038UL)) +#define bFM4_MFS12_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42718038UL)) +#define bFM_MFS12_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_I2C_IBSR_BB *((volatile uint8_t *)(0x42718080UL)) +#define bFM4_MFS12_I2C_IBSR_BB *((volatile uint8_t *)(0x42718080UL)) +#define bFM_MFS12_I2C_IBSR_SPC *((volatile uint8_t *)(0x42718084UL)) +#define bFM4_MFS12_I2C_IBSR_SPC *((volatile uint8_t *)(0x42718084UL)) +#define bFM_MFS12_I2C_IBSR_RSC *((volatile uint8_t *)(0x42718088UL)) +#define bFM4_MFS12_I2C_IBSR_RSC *((volatile uint8_t *)(0x42718088UL)) +#define bFM_MFS12_I2C_IBSR_AL *((volatile uint8_t *)(0x4271808CUL)) +#define bFM4_MFS12_I2C_IBSR_AL *((volatile uint8_t *)(0x4271808CUL)) +#define bFM_MFS12_I2C_IBSR_TRX *((volatile uint8_t *)(0x42718090UL)) +#define bFM4_MFS12_I2C_IBSR_TRX *((volatile uint8_t *)(0x42718090UL)) +#define bFM_MFS12_I2C_IBSR_RSA *((volatile uint8_t *)(0x42718094UL)) +#define bFM4_MFS12_I2C_IBSR_RSA *((volatile uint8_t *)(0x42718094UL)) +#define bFM_MFS12_I2C_IBSR_RACK *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_I2C_IBSR_RACK *((volatile uint8_t *)(0x42718098UL)) +#define bFM_MFS12_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271809CUL)) +#define bFM4_MFS12_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271809CUL)) + +#define bFM_MFS12_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271821CUL)) +#define bFM4_MFS12_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271821CUL)) + +#define bFM_MFS12_I2C_ISMK_EN *((volatile uint8_t *)(0x4271823CUL)) +#define bFM4_MFS12_I2C_ISMK_EN *((volatile uint8_t *)(0x4271823CUL)) + +#define bFM_MFS12_I2C_SMR_TIE *((volatile uint8_t *)(0x42718008UL)) +#define bFM4_MFS12_I2C_SMR_TIE *((volatile uint8_t *)(0x42718008UL)) +#define bFM_MFS12_I2C_SMR_RIE *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_I2C_SMR_RIE *((volatile uint8_t *)(0x4271800CUL)) + +#define bFM_MFS12_I2C_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_I2C_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_I2C_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_I2C_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_I2C_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_I2C_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_I2C_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_I2C_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_I2C_SSR_TBIE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_I2C_SSR_TBIE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_I2C_SSR_DMA *((volatile uint8_t *)(0x427180B4UL)) +#define bFM4_MFS12_I2C_SSR_DMA *((volatile uint8_t *)(0x427180B4UL)) +#define bFM_MFS12_I2C_SSR_TSET *((volatile uint8_t *)(0x427180B8UL)) +#define bFM4_MFS12_I2C_SSR_TSET *((volatile uint8_t *)(0x427180B8UL)) +#define bFM_MFS12_I2C_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_I2C_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + +#define bFM_MFS12_LIN_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) +#define bFM4_MFS12_LIN_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) + +#define bFM_MFS12_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42718090UL)) +#define bFM4_MFS12_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42718090UL)) +#define bFM_MFS12_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) + +#define bFM_MFS12_LIN_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_LIN_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_LIN_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_LIN_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_LIN_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_LIN_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_LIN_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_LIN_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_LIN_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_LIN_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_LIN_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_LIN_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_LIN_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_LIN_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_LIN_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_LIN_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_LIN_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_LIN_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_LIN_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_LIN_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_LIN_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_LIN_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_LIN_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_LIN_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_LIN_SCR_LBR *((volatile uint8_t *)(0x42718034UL)) +#define bFM4_MFS12_LIN_SCR_LBR *((volatile uint8_t *)(0x42718034UL)) +#define bFM_MFS12_LIN_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM4_MFS12_LIN_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM_MFS12_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_LIN_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM4_MFS12_LIN_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM_MFS12_LIN_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_LIN_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) +#define bFM_MFS12_LIN_SMR_WUCR *((volatile uint8_t *)(0x42718010UL)) +#define bFM4_MFS12_LIN_SMR_WUCR *((volatile uint8_t *)(0x42718010UL)) + +#define bFM_MFS12_LIN_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_LIN_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_LIN_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_LIN_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_LIN_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_LIN_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_LIN_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_LIN_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_LIN_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_LIN_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_LIN_SSR_LBD *((volatile uint8_t *)(0x427180B4UL)) +#define bFM4_MFS12_LIN_SSR_LBD *((volatile uint8_t *)(0x427180B4UL)) +#define bFM_MFS12_LIN_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_LIN_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + +#define bFM_MFS12_UART_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) +#define bFM4_MFS12_UART_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) + +#define bFM_MFS12_UART_ESCR_P *((volatile uint8_t *)(0x4271808CUL)) +#define bFM4_MFS12_UART_ESCR_P *((volatile uint8_t *)(0x4271808CUL)) +#define bFM_MFS12_UART_ESCR_PEN *((volatile uint8_t *)(0x42718090UL)) +#define bFM4_MFS12_UART_ESCR_PEN *((volatile uint8_t *)(0x42718090UL)) +#define bFM_MFS12_UART_ESCR_INV *((volatile uint8_t *)(0x42718094UL)) +#define bFM4_MFS12_UART_ESCR_INV *((volatile uint8_t *)(0x42718094UL)) +#define bFM_MFS12_UART_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_UART_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) +#define bFM_MFS12_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271809CUL)) +#define bFM4_MFS12_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271809CUL)) + +#define bFM_MFS12_UART_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_UART_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_UART_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_UART_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_UART_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_UART_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_UART_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_UART_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_UART_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_UART_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_UART_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_UART_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_UART_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_UART_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_UART_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_UART_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_UART_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_UART_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_UART_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_UART_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_UART_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_UART_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_UART_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_UART_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_UART_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_UART_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_UART_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_UART_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_UART_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_UART_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_UART_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_UART_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_UART_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_UART_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_UART_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM4_MFS12_UART_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM_MFS12_UART_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM4_MFS12_UART_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM_MFS12_UART_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_UART_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) + +#define bFM_MFS12_UART_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_UART_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_UART_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_UART_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_UART_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_UART_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_UART_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_UART_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_UART_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_UART_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_UART_SSR_PE *((volatile uint8_t *)(0x427180B4UL)) +#define bFM4_MFS12_UART_SSR_PE *((volatile uint8_t *)(0x427180B4UL)) +#define bFM_MFS12_UART_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_UART_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + + +/******************************************************************************* +* MFS Registers MFS13 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS13_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271A094UL)) +#define bFM4_MFS13_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271A094UL)) +#define bFM_MFS13_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271A098UL)) +#define bFM_MFS13_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271A09CUL)) +#define bFM4_MFS13_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271A09CUL)) + +#define bFM_MFS13_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271A480UL)) +#define bFM4_MFS13_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271A480UL)) +#define bFM_MFS13_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271A498UL)) +#define bFM4_MFS13_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271A498UL)) +#define bFM_MFS13_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271A49CUL)) +#define bFM4_MFS13_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271A49CUL)) +#define bFM_MFS13_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271A4A0UL)) +#define bFM4_MFS13_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271A4A0UL)) +#define bFM_MFS13_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271A4ACUL)) +#define bFM4_MFS13_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271A4ACUL)) +#define bFM_MFS13_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271A4B0UL)) +#define bFM4_MFS13_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271A4B0UL)) +#define bFM_MFS13_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271A4B4UL)) +#define bFM4_MFS13_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271A4B4UL)) + +#define bFM_MFS13_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271A034UL)) +#define bFM4_MFS13_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271A034UL)) +#define bFM_MFS13_CSIO_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM4_MFS13_CSIO_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM_MFS13_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271A600UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271A600UL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271A604UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271A604UL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271A608UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271A608UL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271A60CUL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271A60CUL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271A610UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271A610UL)) +#define bFM_MFS13_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271A614UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271A614UL)) +#define bFM_MFS13_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271A624UL)) +#define bFM4_MFS13_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271A624UL)) + +#define bFM_MFS13_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271A694UL)) +#define bFM4_MFS13_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271A694UL)) +#define bFM_MFS13_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271A698UL)) +#define bFM4_MFS13_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271A698UL)) +#define bFM_MFS13_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271A69CUL)) +#define bFM4_MFS13_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271A69CUL)) + +#define bFM_MFS13_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271A6B4UL)) +#define bFM4_MFS13_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271A6B4UL)) +#define bFM_MFS13_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271A6B8UL)) +#define bFM4_MFS13_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271A6B8UL)) +#define bFM_MFS13_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271A6BCUL)) +#define bFM4_MFS13_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271A6BCUL)) + +#define bFM_MFS13_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271A714UL)) +#define bFM4_MFS13_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271A714UL)) +#define bFM_MFS13_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271A718UL)) +#define bFM4_MFS13_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271A718UL)) +#define bFM_MFS13_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271A71CUL)) +#define bFM4_MFS13_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271A71CUL)) + +#define bFM_MFS13_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM4_MFS13_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM_MFS13_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271A004UL)) +#define bFM4_MFS13_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271A004UL)) +#define bFM_MFS13_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM4_MFS13_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM_MFS13_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271A00CUL)) + +#define bFM_MFS13_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_CSIO_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_CSIO_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + +#define bFM_MFS13_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271A3A0UL)) +#define bFM4_MFS13_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271A3A0UL)) +#define bFM_MFS13_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271A3A4UL)) +#define bFM4_MFS13_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271A3A4UL)) +#define bFM_MFS13_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271A3A8UL)) +#define bFM4_MFS13_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271A3A8UL)) +#define bFM_MFS13_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271A3ACUL)) +#define bFM4_MFS13_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271A3ACUL)) +#define bFM_MFS13_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271A3B0UL)) +#define bFM4_MFS13_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271A3B0UL)) +#define bFM_MFS13_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271A3B4UL)) +#define bFM4_MFS13_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271A3B4UL)) + +#define bFM_MFS13_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_I2C_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_I2C_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_I2C_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_I2C_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_I2C_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_I2C_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_I2C_IBCR_INT *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_I2C_IBCR_INT *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_I2C_IBCR_BER *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_I2C_IBCR_BER *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271A034UL)) +#define bFM4_MFS13_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271A034UL)) +#define bFM_MFS13_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271A038UL)) +#define bFM4_MFS13_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271A038UL)) +#define bFM_MFS13_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_I2C_IBSR_BB *((volatile uint8_t *)(0x4271A080UL)) +#define bFM4_MFS13_I2C_IBSR_BB *((volatile uint8_t *)(0x4271A080UL)) +#define bFM_MFS13_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271A084UL)) +#define bFM4_MFS13_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271A084UL)) +#define bFM_MFS13_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271A088UL)) +#define bFM4_MFS13_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271A088UL)) +#define bFM_MFS13_I2C_IBSR_AL *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM4_MFS13_I2C_IBSR_AL *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM_MFS13_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271A090UL)) +#define bFM4_MFS13_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271A090UL)) +#define bFM_MFS13_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271A094UL)) +#define bFM4_MFS13_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271A094UL)) +#define bFM_MFS13_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271A098UL)) +#define bFM_MFS13_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271A09CUL)) +#define bFM4_MFS13_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271A09CUL)) + +#define bFM_MFS13_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271A21CUL)) +#define bFM4_MFS13_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271A21CUL)) + +#define bFM_MFS13_I2C_ISMK_EN *((volatile uint8_t *)(0x4271A23CUL)) +#define bFM4_MFS13_I2C_ISMK_EN *((volatile uint8_t *)(0x4271A23CUL)) + +#define bFM_MFS13_I2C_SMR_TIE *((volatile uint8_t *)(0x4271A008UL)) +#define bFM4_MFS13_I2C_SMR_TIE *((volatile uint8_t *)(0x4271A008UL)) +#define bFM_MFS13_I2C_SMR_RIE *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_I2C_SMR_RIE *((volatile uint8_t *)(0x4271A00CUL)) + +#define bFM_MFS13_I2C_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_I2C_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_I2C_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_I2C_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_I2C_SSR_DMA *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM4_MFS13_I2C_SSR_DMA *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM_MFS13_I2C_SSR_TSET *((volatile uint8_t *)(0x4271A0B8UL)) +#define bFM4_MFS13_I2C_SSR_TSET *((volatile uint8_t *)(0x4271A0B8UL)) +#define bFM_MFS13_I2C_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_I2C_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + +#define bFM_MFS13_LIN_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) +#define bFM4_MFS13_LIN_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) + +#define bFM_MFS13_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271A090UL)) +#define bFM4_MFS13_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271A090UL)) +#define bFM_MFS13_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) + +#define bFM_MFS13_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_LIN_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_LIN_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_LIN_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_LIN_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_LIN_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_LIN_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_LIN_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_LIN_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_LIN_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_LIN_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_LIN_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_LIN_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_LIN_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_LIN_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_LIN_SCR_LBR *((volatile uint8_t *)(0x4271A034UL)) +#define bFM4_MFS13_LIN_SCR_LBR *((volatile uint8_t *)(0x4271A034UL)) +#define bFM_MFS13_LIN_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM4_MFS13_LIN_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM_MFS13_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_LIN_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM4_MFS13_LIN_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM_MFS13_LIN_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_LIN_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM_MFS13_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271A010UL)) +#define bFM4_MFS13_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271A010UL)) + +#define bFM_MFS13_LIN_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_LIN_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_LIN_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_LIN_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_LIN_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_LIN_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_LIN_SSR_LBD *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM4_MFS13_LIN_SSR_LBD *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM_MFS13_LIN_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_LIN_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + +#define bFM_MFS13_UART_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) +#define bFM4_MFS13_UART_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) + +#define bFM_MFS13_UART_ESCR_P *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM4_MFS13_UART_ESCR_P *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM_MFS13_UART_ESCR_PEN *((volatile uint8_t *)(0x4271A090UL)) +#define bFM4_MFS13_UART_ESCR_PEN *((volatile uint8_t *)(0x4271A090UL)) +#define bFM_MFS13_UART_ESCR_INV *((volatile uint8_t *)(0x4271A094UL)) +#define bFM4_MFS13_UART_ESCR_INV *((volatile uint8_t *)(0x4271A094UL)) +#define bFM_MFS13_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) +#define bFM_MFS13_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271A09CUL)) +#define bFM4_MFS13_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271A09CUL)) + +#define bFM_MFS13_UART_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_UART_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_UART_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_UART_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_UART_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_UART_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_UART_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_UART_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_UART_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_UART_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_UART_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_UART_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_UART_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_UART_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_UART_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_UART_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_UART_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_UART_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_UART_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_UART_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_UART_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_UART_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_UART_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_UART_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_UART_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_UART_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_UART_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM4_MFS13_UART_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM_MFS13_UART_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM4_MFS13_UART_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM_MFS13_UART_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_UART_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) + +#define bFM_MFS13_UART_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_UART_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_UART_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_UART_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_UART_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_UART_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_UART_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_UART_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_UART_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_UART_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_UART_SSR_PE *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM4_MFS13_UART_SSR_PE *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM_MFS13_UART_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_UART_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS14 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS14_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271C094UL)) +#define bFM4_MFS14_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271C094UL)) +#define bFM_MFS14_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271C098UL)) +#define bFM_MFS14_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271C09CUL)) +#define bFM4_MFS14_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271C09CUL)) + +#define bFM_MFS14_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271C480UL)) +#define bFM4_MFS14_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271C480UL)) +#define bFM_MFS14_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271C498UL)) +#define bFM4_MFS14_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271C498UL)) +#define bFM_MFS14_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271C49CUL)) +#define bFM4_MFS14_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271C49CUL)) +#define bFM_MFS14_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271C4A0UL)) +#define bFM4_MFS14_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271C4A0UL)) +#define bFM_MFS14_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271C4ACUL)) +#define bFM4_MFS14_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271C4ACUL)) +#define bFM_MFS14_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271C4B0UL)) +#define bFM4_MFS14_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271C4B0UL)) +#define bFM_MFS14_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271C4B4UL)) +#define bFM4_MFS14_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271C4B4UL)) + +#define bFM_MFS14_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271C034UL)) +#define bFM4_MFS14_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271C034UL)) +#define bFM_MFS14_CSIO_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM4_MFS14_CSIO_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM_MFS14_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271C600UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271C600UL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271C604UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271C604UL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271C608UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271C608UL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271C60CUL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271C60CUL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271C610UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271C610UL)) +#define bFM_MFS14_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271C614UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271C614UL)) +#define bFM_MFS14_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271C624UL)) +#define bFM4_MFS14_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271C624UL)) + +#define bFM_MFS14_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271C694UL)) +#define bFM4_MFS14_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271C694UL)) +#define bFM_MFS14_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271C698UL)) +#define bFM4_MFS14_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271C698UL)) +#define bFM_MFS14_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271C69CUL)) +#define bFM4_MFS14_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271C69CUL)) + +#define bFM_MFS14_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271C6B4UL)) +#define bFM4_MFS14_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271C6B4UL)) +#define bFM_MFS14_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271C6B8UL)) +#define bFM4_MFS14_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271C6B8UL)) +#define bFM_MFS14_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271C6BCUL)) +#define bFM4_MFS14_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271C6BCUL)) + +#define bFM_MFS14_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271C714UL)) +#define bFM4_MFS14_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271C714UL)) +#define bFM_MFS14_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271C718UL)) +#define bFM4_MFS14_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271C718UL)) +#define bFM_MFS14_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271C71CUL)) +#define bFM4_MFS14_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271C71CUL)) + +#define bFM_MFS14_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM4_MFS14_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM_MFS14_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271C004UL)) +#define bFM4_MFS14_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271C004UL)) +#define bFM_MFS14_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM4_MFS14_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM_MFS14_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271C00CUL)) + +#define bFM_MFS14_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_CSIO_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_CSIO_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + +#define bFM_MFS14_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271C3A0UL)) +#define bFM4_MFS14_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271C3A0UL)) +#define bFM_MFS14_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271C3A4UL)) +#define bFM4_MFS14_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271C3A4UL)) +#define bFM_MFS14_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271C3A8UL)) +#define bFM4_MFS14_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271C3A8UL)) +#define bFM_MFS14_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271C3ACUL)) +#define bFM4_MFS14_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271C3ACUL)) +#define bFM_MFS14_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271C3B0UL)) +#define bFM4_MFS14_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271C3B0UL)) +#define bFM_MFS14_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271C3B4UL)) +#define bFM4_MFS14_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271C3B4UL)) + +#define bFM_MFS14_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_I2C_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_I2C_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_I2C_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_I2C_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_I2C_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_I2C_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_I2C_IBCR_INT *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_I2C_IBCR_INT *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_I2C_IBCR_BER *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_I2C_IBCR_BER *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271C034UL)) +#define bFM4_MFS14_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271C034UL)) +#define bFM_MFS14_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271C038UL)) +#define bFM4_MFS14_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271C038UL)) +#define bFM_MFS14_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_I2C_IBSR_BB *((volatile uint8_t *)(0x4271C080UL)) +#define bFM4_MFS14_I2C_IBSR_BB *((volatile uint8_t *)(0x4271C080UL)) +#define bFM_MFS14_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271C084UL)) +#define bFM4_MFS14_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271C084UL)) +#define bFM_MFS14_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271C088UL)) +#define bFM4_MFS14_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271C088UL)) +#define bFM_MFS14_I2C_IBSR_AL *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM4_MFS14_I2C_IBSR_AL *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM_MFS14_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271C090UL)) +#define bFM4_MFS14_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271C090UL)) +#define bFM_MFS14_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271C094UL)) +#define bFM4_MFS14_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271C094UL)) +#define bFM_MFS14_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271C098UL)) +#define bFM_MFS14_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271C09CUL)) +#define bFM4_MFS14_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271C09CUL)) + +#define bFM_MFS14_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271C21CUL)) +#define bFM4_MFS14_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271C21CUL)) + +#define bFM_MFS14_I2C_ISMK_EN *((volatile uint8_t *)(0x4271C23CUL)) +#define bFM4_MFS14_I2C_ISMK_EN *((volatile uint8_t *)(0x4271C23CUL)) + +#define bFM_MFS14_I2C_SMR_TIE *((volatile uint8_t *)(0x4271C008UL)) +#define bFM4_MFS14_I2C_SMR_TIE *((volatile uint8_t *)(0x4271C008UL)) +#define bFM_MFS14_I2C_SMR_RIE *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_I2C_SMR_RIE *((volatile uint8_t *)(0x4271C00CUL)) + +#define bFM_MFS14_I2C_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_I2C_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_I2C_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_I2C_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_I2C_SSR_DMA *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM4_MFS14_I2C_SSR_DMA *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM_MFS14_I2C_SSR_TSET *((volatile uint8_t *)(0x4271C0B8UL)) +#define bFM4_MFS14_I2C_SSR_TSET *((volatile uint8_t *)(0x4271C0B8UL)) +#define bFM_MFS14_I2C_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_I2C_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + +#define bFM_MFS14_LIN_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) +#define bFM4_MFS14_LIN_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) + +#define bFM_MFS14_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271C090UL)) +#define bFM4_MFS14_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271C090UL)) +#define bFM_MFS14_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) + +#define bFM_MFS14_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_LIN_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_LIN_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_LIN_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_LIN_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_LIN_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_LIN_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_LIN_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_LIN_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_LIN_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_LIN_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_LIN_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_LIN_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_LIN_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_LIN_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_LIN_SCR_LBR *((volatile uint8_t *)(0x4271C034UL)) +#define bFM4_MFS14_LIN_SCR_LBR *((volatile uint8_t *)(0x4271C034UL)) +#define bFM_MFS14_LIN_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM4_MFS14_LIN_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM_MFS14_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_LIN_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM4_MFS14_LIN_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM_MFS14_LIN_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_LIN_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM_MFS14_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271C010UL)) +#define bFM4_MFS14_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271C010UL)) + +#define bFM_MFS14_LIN_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_LIN_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_LIN_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_LIN_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_LIN_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_LIN_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_LIN_SSR_LBD *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM4_MFS14_LIN_SSR_LBD *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM_MFS14_LIN_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_LIN_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + +#define bFM_MFS14_UART_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) +#define bFM4_MFS14_UART_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) + +#define bFM_MFS14_UART_ESCR_P *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM4_MFS14_UART_ESCR_P *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM_MFS14_UART_ESCR_PEN *((volatile uint8_t *)(0x4271C090UL)) +#define bFM4_MFS14_UART_ESCR_PEN *((volatile uint8_t *)(0x4271C090UL)) +#define bFM_MFS14_UART_ESCR_INV *((volatile uint8_t *)(0x4271C094UL)) +#define bFM4_MFS14_UART_ESCR_INV *((volatile uint8_t *)(0x4271C094UL)) +#define bFM_MFS14_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) +#define bFM_MFS14_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271C09CUL)) +#define bFM4_MFS14_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271C09CUL)) + +#define bFM_MFS14_UART_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_UART_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_UART_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_UART_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_UART_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_UART_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_UART_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_UART_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_UART_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_UART_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_UART_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_UART_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_UART_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_UART_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_UART_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_UART_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_UART_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_UART_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_UART_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_UART_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_UART_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_UART_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_UART_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_UART_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_UART_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_UART_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_UART_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM4_MFS14_UART_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM_MFS14_UART_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM4_MFS14_UART_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM_MFS14_UART_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_UART_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) + +#define bFM_MFS14_UART_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_UART_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_UART_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_UART_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_UART_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_UART_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_UART_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_UART_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_UART_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_UART_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_UART_SSR_PE *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM4_MFS14_UART_SSR_PE *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM_MFS14_UART_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_UART_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS15 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS15_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271E094UL)) +#define bFM4_MFS15_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271E094UL)) +#define bFM_MFS15_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271E098UL)) +#define bFM_MFS15_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271E09CUL)) +#define bFM4_MFS15_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271E09CUL)) + +#define bFM_MFS15_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271E480UL)) +#define bFM4_MFS15_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271E480UL)) +#define bFM_MFS15_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271E498UL)) +#define bFM4_MFS15_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271E498UL)) +#define bFM_MFS15_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271E49CUL)) +#define bFM4_MFS15_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271E49CUL)) +#define bFM_MFS15_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271E4A0UL)) +#define bFM4_MFS15_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271E4A0UL)) +#define bFM_MFS15_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271E4ACUL)) +#define bFM4_MFS15_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271E4ACUL)) +#define bFM_MFS15_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271E4B0UL)) +#define bFM4_MFS15_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271E4B0UL)) +#define bFM_MFS15_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271E4B4UL)) +#define bFM4_MFS15_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271E4B4UL)) + +#define bFM_MFS15_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271E034UL)) +#define bFM4_MFS15_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271E034UL)) +#define bFM_MFS15_CSIO_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM4_MFS15_CSIO_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM_MFS15_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271E600UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271E600UL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271E604UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271E604UL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271E608UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271E608UL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271E60CUL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271E60CUL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271E610UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271E610UL)) +#define bFM_MFS15_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271E614UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271E614UL)) +#define bFM_MFS15_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271E624UL)) +#define bFM4_MFS15_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271E624UL)) + +#define bFM_MFS15_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271E694UL)) +#define bFM4_MFS15_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271E694UL)) +#define bFM_MFS15_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271E698UL)) +#define bFM4_MFS15_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271E698UL)) +#define bFM_MFS15_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271E69CUL)) +#define bFM4_MFS15_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271E69CUL)) + +#define bFM_MFS15_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271E6B4UL)) +#define bFM4_MFS15_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271E6B4UL)) +#define bFM_MFS15_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271E6B8UL)) +#define bFM4_MFS15_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271E6B8UL)) +#define bFM_MFS15_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271E6BCUL)) +#define bFM4_MFS15_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271E6BCUL)) + +#define bFM_MFS15_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271E714UL)) +#define bFM4_MFS15_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271E714UL)) +#define bFM_MFS15_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271E718UL)) +#define bFM4_MFS15_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271E718UL)) +#define bFM_MFS15_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271E71CUL)) +#define bFM4_MFS15_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271E71CUL)) + +#define bFM_MFS15_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM4_MFS15_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM_MFS15_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271E004UL)) +#define bFM4_MFS15_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271E004UL)) +#define bFM_MFS15_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM4_MFS15_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM_MFS15_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271E00CUL)) + +#define bFM_MFS15_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_CSIO_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_CSIO_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + +#define bFM_MFS15_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271E3A0UL)) +#define bFM4_MFS15_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271E3A0UL)) +#define bFM_MFS15_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271E3A4UL)) +#define bFM4_MFS15_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271E3A4UL)) +#define bFM_MFS15_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271E3A8UL)) +#define bFM4_MFS15_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271E3A8UL)) +#define bFM_MFS15_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271E3ACUL)) +#define bFM4_MFS15_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271E3ACUL)) +#define bFM_MFS15_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271E3B0UL)) +#define bFM4_MFS15_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271E3B0UL)) +#define bFM_MFS15_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271E3B4UL)) +#define bFM4_MFS15_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271E3B4UL)) + +#define bFM_MFS15_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_I2C_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_I2C_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_I2C_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_I2C_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_I2C_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_I2C_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_I2C_IBCR_INT *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_I2C_IBCR_INT *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_I2C_IBCR_BER *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_I2C_IBCR_BER *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271E034UL)) +#define bFM4_MFS15_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271E034UL)) +#define bFM_MFS15_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271E038UL)) +#define bFM4_MFS15_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271E038UL)) +#define bFM_MFS15_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_I2C_IBSR_BB *((volatile uint8_t *)(0x4271E080UL)) +#define bFM4_MFS15_I2C_IBSR_BB *((volatile uint8_t *)(0x4271E080UL)) +#define bFM_MFS15_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271E084UL)) +#define bFM4_MFS15_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271E084UL)) +#define bFM_MFS15_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271E088UL)) +#define bFM4_MFS15_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271E088UL)) +#define bFM_MFS15_I2C_IBSR_AL *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM4_MFS15_I2C_IBSR_AL *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM_MFS15_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271E090UL)) +#define bFM4_MFS15_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271E090UL)) +#define bFM_MFS15_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271E094UL)) +#define bFM4_MFS15_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271E094UL)) +#define bFM_MFS15_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271E098UL)) +#define bFM_MFS15_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271E09CUL)) +#define bFM4_MFS15_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271E09CUL)) + +#define bFM_MFS15_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271E21CUL)) +#define bFM4_MFS15_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271E21CUL)) + +#define bFM_MFS15_I2C_ISMK_EN *((volatile uint8_t *)(0x4271E23CUL)) +#define bFM4_MFS15_I2C_ISMK_EN *((volatile uint8_t *)(0x4271E23CUL)) + +#define bFM_MFS15_I2C_SMR_TIE *((volatile uint8_t *)(0x4271E008UL)) +#define bFM4_MFS15_I2C_SMR_TIE *((volatile uint8_t *)(0x4271E008UL)) +#define bFM_MFS15_I2C_SMR_RIE *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_I2C_SMR_RIE *((volatile uint8_t *)(0x4271E00CUL)) + +#define bFM_MFS15_I2C_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_I2C_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_I2C_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_I2C_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_I2C_SSR_DMA *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM4_MFS15_I2C_SSR_DMA *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM_MFS15_I2C_SSR_TSET *((volatile uint8_t *)(0x4271E0B8UL)) +#define bFM4_MFS15_I2C_SSR_TSET *((volatile uint8_t *)(0x4271E0B8UL)) +#define bFM_MFS15_I2C_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_I2C_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + +#define bFM_MFS15_LIN_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) +#define bFM4_MFS15_LIN_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) + +#define bFM_MFS15_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271E090UL)) +#define bFM4_MFS15_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271E090UL)) +#define bFM_MFS15_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) + +#define bFM_MFS15_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_LIN_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_LIN_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_LIN_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_LIN_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_LIN_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_LIN_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_LIN_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_LIN_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_LIN_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_LIN_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_LIN_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_LIN_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_LIN_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_LIN_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_LIN_SCR_LBR *((volatile uint8_t *)(0x4271E034UL)) +#define bFM4_MFS15_LIN_SCR_LBR *((volatile uint8_t *)(0x4271E034UL)) +#define bFM_MFS15_LIN_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM4_MFS15_LIN_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM_MFS15_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_LIN_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM4_MFS15_LIN_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM_MFS15_LIN_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_LIN_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM_MFS15_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271E010UL)) +#define bFM4_MFS15_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271E010UL)) + +#define bFM_MFS15_LIN_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_LIN_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_LIN_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_LIN_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_LIN_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_LIN_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_LIN_SSR_LBD *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM4_MFS15_LIN_SSR_LBD *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM_MFS15_LIN_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_LIN_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + +#define bFM_MFS15_UART_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) +#define bFM4_MFS15_UART_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) + +#define bFM_MFS15_UART_ESCR_P *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM4_MFS15_UART_ESCR_P *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM_MFS15_UART_ESCR_PEN *((volatile uint8_t *)(0x4271E090UL)) +#define bFM4_MFS15_UART_ESCR_PEN *((volatile uint8_t *)(0x4271E090UL)) +#define bFM_MFS15_UART_ESCR_INV *((volatile uint8_t *)(0x4271E094UL)) +#define bFM4_MFS15_UART_ESCR_INV *((volatile uint8_t *)(0x4271E094UL)) +#define bFM_MFS15_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) +#define bFM_MFS15_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271E09CUL)) +#define bFM4_MFS15_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271E09CUL)) + +#define bFM_MFS15_UART_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_UART_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_UART_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_UART_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_UART_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_UART_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_UART_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_UART_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_UART_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_UART_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_UART_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_UART_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_UART_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_UART_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_UART_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_UART_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_UART_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_UART_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_UART_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_UART_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_UART_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_UART_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_UART_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_UART_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_UART_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_UART_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_UART_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM4_MFS15_UART_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM_MFS15_UART_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM4_MFS15_UART_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM_MFS15_UART_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_UART_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) + +#define bFM_MFS15_UART_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_UART_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_UART_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_UART_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_UART_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_UART_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_UART_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_UART_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_UART_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_UART_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_UART_SSR_PE *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM4_MFS15_UART_SSR_PE *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM_MFS15_UART_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_UART_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS2 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS2_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42704094UL)) +#define bFM4_MFS2_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42704094UL)) +#define bFM_MFS2_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42704098UL)) +#define bFM_MFS2_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270409CUL)) +#define bFM4_MFS2_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270409CUL)) + +#define bFM_MFS2_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_CSIO_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_CSIO_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_CSIO_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_CSIO_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_CSIO_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_CSIO_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42704480UL)) +#define bFM4_MFS2_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42704480UL)) +#define bFM_MFS2_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42704498UL)) +#define bFM4_MFS2_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42704498UL)) +#define bFM_MFS2_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270449CUL)) +#define bFM4_MFS2_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270449CUL)) +#define bFM_MFS2_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427044A0UL)) +#define bFM4_MFS2_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427044A0UL)) +#define bFM_MFS2_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427044ACUL)) +#define bFM4_MFS2_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427044ACUL)) +#define bFM_MFS2_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427044B0UL)) +#define bFM4_MFS2_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427044B0UL)) +#define bFM_MFS2_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427044B4UL)) +#define bFM4_MFS2_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427044B4UL)) + +#define bFM_MFS2_CSIO_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_CSIO_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_CSIO_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_CSIO_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_CSIO_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_CSIO_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_CSIO_SCR_SPI *((volatile uint8_t *)(0x42704034UL)) +#define bFM4_MFS2_CSIO_SCR_SPI *((volatile uint8_t *)(0x42704034UL)) +#define bFM_MFS2_CSIO_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM4_MFS2_CSIO_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM_MFS2_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42704600UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42704600UL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42704604UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42704604UL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42704608UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42704608UL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270460CUL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270460CUL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42704610UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42704610UL)) +#define bFM_MFS2_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42704614UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42704614UL)) +#define bFM_MFS2_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42704624UL)) +#define bFM4_MFS2_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42704624UL)) + +#define bFM_MFS2_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42704694UL)) +#define bFM4_MFS2_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42704694UL)) +#define bFM_MFS2_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42704698UL)) +#define bFM4_MFS2_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42704698UL)) +#define bFM_MFS2_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270469CUL)) +#define bFM4_MFS2_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270469CUL)) + +#define bFM_MFS2_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427046B4UL)) +#define bFM4_MFS2_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427046B4UL)) +#define bFM_MFS2_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427046B8UL)) +#define bFM4_MFS2_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427046B8UL)) +#define bFM_MFS2_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427046BCUL)) +#define bFM4_MFS2_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427046BCUL)) + +#define bFM_MFS2_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42704714UL)) +#define bFM4_MFS2_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42704714UL)) +#define bFM_MFS2_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42704718UL)) +#define bFM4_MFS2_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42704718UL)) +#define bFM_MFS2_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270471CUL)) +#define bFM4_MFS2_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270471CUL)) + +#define bFM_MFS2_CSIO_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM4_MFS2_CSIO_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM_MFS2_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42704004UL)) +#define bFM4_MFS2_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42704004UL)) +#define bFM_MFS2_CSIO_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM4_MFS2_CSIO_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM_MFS2_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270400CUL)) + +#define bFM_MFS2_CSIO_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_CSIO_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_CSIO_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_CSIO_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_CSIO_SSR_AWC *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_CSIO_SSR_AWC *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_CSIO_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_CSIO_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + +#define bFM_MFS2_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427043A0UL)) +#define bFM4_MFS2_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427043A0UL)) +#define bFM_MFS2_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427043A4UL)) +#define bFM4_MFS2_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427043A4UL)) +#define bFM_MFS2_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427043A8UL)) +#define bFM4_MFS2_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427043A8UL)) +#define bFM_MFS2_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427043ACUL)) +#define bFM4_MFS2_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427043ACUL)) +#define bFM_MFS2_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427043B0UL)) +#define bFM4_MFS2_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427043B0UL)) +#define bFM_MFS2_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427043B4UL)) +#define bFM4_MFS2_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427043B4UL)) + +#define bFM_MFS2_I2C_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_I2C_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_I2C_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_I2C_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_I2C_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_I2C_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_I2C_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_I2C_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_I2C_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_I2C_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_I2C_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_I2C_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_I2C_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_I2C_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_I2C_IBCR_INT *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_I2C_IBCR_INT *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_I2C_IBCR_BER *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_I2C_IBCR_BER *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_I2C_IBCR_INTE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_I2C_IBCR_INTE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42704034UL)) +#define bFM4_MFS2_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42704034UL)) +#define bFM_MFS2_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42704038UL)) +#define bFM4_MFS2_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42704038UL)) +#define bFM_MFS2_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_I2C_IBSR_BB *((volatile uint8_t *)(0x42704080UL)) +#define bFM4_MFS2_I2C_IBSR_BB *((volatile uint8_t *)(0x42704080UL)) +#define bFM_MFS2_I2C_IBSR_SPC *((volatile uint8_t *)(0x42704084UL)) +#define bFM4_MFS2_I2C_IBSR_SPC *((volatile uint8_t *)(0x42704084UL)) +#define bFM_MFS2_I2C_IBSR_RSC *((volatile uint8_t *)(0x42704088UL)) +#define bFM4_MFS2_I2C_IBSR_RSC *((volatile uint8_t *)(0x42704088UL)) +#define bFM_MFS2_I2C_IBSR_AL *((volatile uint8_t *)(0x4270408CUL)) +#define bFM4_MFS2_I2C_IBSR_AL *((volatile uint8_t *)(0x4270408CUL)) +#define bFM_MFS2_I2C_IBSR_TRX *((volatile uint8_t *)(0x42704090UL)) +#define bFM4_MFS2_I2C_IBSR_TRX *((volatile uint8_t *)(0x42704090UL)) +#define bFM_MFS2_I2C_IBSR_RSA *((volatile uint8_t *)(0x42704094UL)) +#define bFM4_MFS2_I2C_IBSR_RSA *((volatile uint8_t *)(0x42704094UL)) +#define bFM_MFS2_I2C_IBSR_RACK *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_I2C_IBSR_RACK *((volatile uint8_t *)(0x42704098UL)) +#define bFM_MFS2_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270409CUL)) +#define bFM4_MFS2_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270409CUL)) + +#define bFM_MFS2_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270421CUL)) +#define bFM4_MFS2_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270421CUL)) + +#define bFM_MFS2_I2C_ISMK_EN *((volatile uint8_t *)(0x4270423CUL)) +#define bFM4_MFS2_I2C_ISMK_EN *((volatile uint8_t *)(0x4270423CUL)) + +#define bFM_MFS2_I2C_SMR_TIE *((volatile uint8_t *)(0x42704008UL)) +#define bFM4_MFS2_I2C_SMR_TIE *((volatile uint8_t *)(0x42704008UL)) +#define bFM_MFS2_I2C_SMR_RIE *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_I2C_SMR_RIE *((volatile uint8_t *)(0x4270400CUL)) + +#define bFM_MFS2_I2C_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_I2C_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_I2C_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_I2C_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_I2C_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_I2C_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_I2C_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_I2C_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_I2C_SSR_TBIE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_I2C_SSR_TBIE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_I2C_SSR_DMA *((volatile uint8_t *)(0x427040B4UL)) +#define bFM4_MFS2_I2C_SSR_DMA *((volatile uint8_t *)(0x427040B4UL)) +#define bFM_MFS2_I2C_SSR_TSET *((volatile uint8_t *)(0x427040B8UL)) +#define bFM4_MFS2_I2C_SSR_TSET *((volatile uint8_t *)(0x427040B8UL)) +#define bFM_MFS2_I2C_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_I2C_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + +#define bFM_MFS2_LIN_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) +#define bFM4_MFS2_LIN_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) + +#define bFM_MFS2_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42704090UL)) +#define bFM4_MFS2_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42704090UL)) +#define bFM_MFS2_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) + +#define bFM_MFS2_LIN_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_LIN_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_LIN_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_LIN_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_LIN_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_LIN_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_LIN_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_LIN_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_LIN_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_LIN_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_LIN_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_LIN_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_LIN_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_LIN_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_LIN_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_LIN_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_LIN_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_LIN_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_LIN_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_LIN_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_LIN_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_LIN_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_LIN_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_LIN_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_LIN_SCR_LBR *((volatile uint8_t *)(0x42704034UL)) +#define bFM4_MFS2_LIN_SCR_LBR *((volatile uint8_t *)(0x42704034UL)) +#define bFM_MFS2_LIN_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM4_MFS2_LIN_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM_MFS2_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_LIN_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM4_MFS2_LIN_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM_MFS2_LIN_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_LIN_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) +#define bFM_MFS2_LIN_SMR_WUCR *((volatile uint8_t *)(0x42704010UL)) +#define bFM4_MFS2_LIN_SMR_WUCR *((volatile uint8_t *)(0x42704010UL)) + +#define bFM_MFS2_LIN_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_LIN_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_LIN_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_LIN_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_LIN_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_LIN_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_LIN_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_LIN_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_LIN_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_LIN_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_LIN_SSR_LBD *((volatile uint8_t *)(0x427040B4UL)) +#define bFM4_MFS2_LIN_SSR_LBD *((volatile uint8_t *)(0x427040B4UL)) +#define bFM_MFS2_LIN_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_LIN_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + +#define bFM_MFS2_UART_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) +#define bFM4_MFS2_UART_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) + +#define bFM_MFS2_UART_ESCR_P *((volatile uint8_t *)(0x4270408CUL)) +#define bFM4_MFS2_UART_ESCR_P *((volatile uint8_t *)(0x4270408CUL)) +#define bFM_MFS2_UART_ESCR_PEN *((volatile uint8_t *)(0x42704090UL)) +#define bFM4_MFS2_UART_ESCR_PEN *((volatile uint8_t *)(0x42704090UL)) +#define bFM_MFS2_UART_ESCR_INV *((volatile uint8_t *)(0x42704094UL)) +#define bFM4_MFS2_UART_ESCR_INV *((volatile uint8_t *)(0x42704094UL)) +#define bFM_MFS2_UART_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_UART_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) +#define bFM_MFS2_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270409CUL)) +#define bFM4_MFS2_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270409CUL)) + +#define bFM_MFS2_UART_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_UART_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_UART_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_UART_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_UART_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_UART_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_UART_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_UART_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_UART_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_UART_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_UART_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_UART_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_UART_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_UART_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_UART_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_UART_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_UART_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_UART_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_UART_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_UART_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_UART_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_UART_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_UART_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_UART_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_UART_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_UART_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_UART_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_UART_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_UART_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_UART_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_UART_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_UART_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_UART_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_UART_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_UART_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM4_MFS2_UART_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM_MFS2_UART_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM4_MFS2_UART_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM_MFS2_UART_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_UART_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) + +#define bFM_MFS2_UART_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_UART_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_UART_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_UART_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_UART_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_UART_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_UART_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_UART_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_UART_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_UART_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_UART_SSR_PE *((volatile uint8_t *)(0x427040B4UL)) +#define bFM4_MFS2_UART_SSR_PE *((volatile uint8_t *)(0x427040B4UL)) +#define bFM_MFS2_UART_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_UART_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + + +/******************************************************************************* +* MFS Registers MFS3 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS3_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42706094UL)) +#define bFM4_MFS3_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42706094UL)) +#define bFM_MFS3_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42706098UL)) +#define bFM_MFS3_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270609CUL)) +#define bFM4_MFS3_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270609CUL)) + +#define bFM_MFS3_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_CSIO_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_CSIO_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_CSIO_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_CSIO_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_CSIO_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_CSIO_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42706480UL)) +#define bFM4_MFS3_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42706480UL)) +#define bFM_MFS3_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42706498UL)) +#define bFM4_MFS3_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42706498UL)) +#define bFM_MFS3_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270649CUL)) +#define bFM4_MFS3_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270649CUL)) +#define bFM_MFS3_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427064A0UL)) +#define bFM4_MFS3_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427064A0UL)) +#define bFM_MFS3_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427064ACUL)) +#define bFM4_MFS3_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427064ACUL)) +#define bFM_MFS3_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427064B0UL)) +#define bFM4_MFS3_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427064B0UL)) +#define bFM_MFS3_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427064B4UL)) +#define bFM4_MFS3_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427064B4UL)) + +#define bFM_MFS3_CSIO_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_CSIO_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_CSIO_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_CSIO_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_CSIO_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_CSIO_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_CSIO_SCR_SPI *((volatile uint8_t *)(0x42706034UL)) +#define bFM4_MFS3_CSIO_SCR_SPI *((volatile uint8_t *)(0x42706034UL)) +#define bFM_MFS3_CSIO_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM4_MFS3_CSIO_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM_MFS3_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42706600UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42706600UL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42706604UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42706604UL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42706608UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42706608UL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270660CUL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270660CUL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42706610UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42706610UL)) +#define bFM_MFS3_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42706614UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42706614UL)) +#define bFM_MFS3_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42706624UL)) +#define bFM4_MFS3_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42706624UL)) + +#define bFM_MFS3_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42706694UL)) +#define bFM4_MFS3_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42706694UL)) +#define bFM_MFS3_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42706698UL)) +#define bFM4_MFS3_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42706698UL)) +#define bFM_MFS3_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270669CUL)) +#define bFM4_MFS3_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270669CUL)) + +#define bFM_MFS3_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427066B4UL)) +#define bFM4_MFS3_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427066B4UL)) +#define bFM_MFS3_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427066B8UL)) +#define bFM4_MFS3_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427066B8UL)) +#define bFM_MFS3_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427066BCUL)) +#define bFM4_MFS3_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427066BCUL)) + +#define bFM_MFS3_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42706714UL)) +#define bFM4_MFS3_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42706714UL)) +#define bFM_MFS3_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42706718UL)) +#define bFM4_MFS3_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42706718UL)) +#define bFM_MFS3_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270671CUL)) +#define bFM4_MFS3_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270671CUL)) + +#define bFM_MFS3_CSIO_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM4_MFS3_CSIO_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM_MFS3_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42706004UL)) +#define bFM4_MFS3_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42706004UL)) +#define bFM_MFS3_CSIO_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM4_MFS3_CSIO_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM_MFS3_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270600CUL)) + +#define bFM_MFS3_CSIO_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_CSIO_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_CSIO_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_CSIO_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_CSIO_SSR_AWC *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_CSIO_SSR_AWC *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_CSIO_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_CSIO_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + +#define bFM_MFS3_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427063A0UL)) +#define bFM4_MFS3_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427063A0UL)) +#define bFM_MFS3_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427063A4UL)) +#define bFM4_MFS3_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427063A4UL)) +#define bFM_MFS3_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427063A8UL)) +#define bFM4_MFS3_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427063A8UL)) +#define bFM_MFS3_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427063ACUL)) +#define bFM4_MFS3_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427063ACUL)) +#define bFM_MFS3_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427063B0UL)) +#define bFM4_MFS3_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427063B0UL)) +#define bFM_MFS3_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427063B4UL)) +#define bFM4_MFS3_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427063B4UL)) + +#define bFM_MFS3_I2C_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_I2C_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_I2C_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_I2C_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_I2C_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_I2C_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_I2C_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_I2C_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_I2C_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_I2C_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_I2C_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_I2C_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_I2C_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_I2C_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_I2C_IBCR_INT *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_I2C_IBCR_INT *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_I2C_IBCR_BER *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_I2C_IBCR_BER *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_I2C_IBCR_INTE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_I2C_IBCR_INTE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42706034UL)) +#define bFM4_MFS3_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42706034UL)) +#define bFM_MFS3_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42706038UL)) +#define bFM4_MFS3_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42706038UL)) +#define bFM_MFS3_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_I2C_IBSR_BB *((volatile uint8_t *)(0x42706080UL)) +#define bFM4_MFS3_I2C_IBSR_BB *((volatile uint8_t *)(0x42706080UL)) +#define bFM_MFS3_I2C_IBSR_SPC *((volatile uint8_t *)(0x42706084UL)) +#define bFM4_MFS3_I2C_IBSR_SPC *((volatile uint8_t *)(0x42706084UL)) +#define bFM_MFS3_I2C_IBSR_RSC *((volatile uint8_t *)(0x42706088UL)) +#define bFM4_MFS3_I2C_IBSR_RSC *((volatile uint8_t *)(0x42706088UL)) +#define bFM_MFS3_I2C_IBSR_AL *((volatile uint8_t *)(0x4270608CUL)) +#define bFM4_MFS3_I2C_IBSR_AL *((volatile uint8_t *)(0x4270608CUL)) +#define bFM_MFS3_I2C_IBSR_TRX *((volatile uint8_t *)(0x42706090UL)) +#define bFM4_MFS3_I2C_IBSR_TRX *((volatile uint8_t *)(0x42706090UL)) +#define bFM_MFS3_I2C_IBSR_RSA *((volatile uint8_t *)(0x42706094UL)) +#define bFM4_MFS3_I2C_IBSR_RSA *((volatile uint8_t *)(0x42706094UL)) +#define bFM_MFS3_I2C_IBSR_RACK *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_I2C_IBSR_RACK *((volatile uint8_t *)(0x42706098UL)) +#define bFM_MFS3_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270609CUL)) +#define bFM4_MFS3_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270609CUL)) + +#define bFM_MFS3_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270621CUL)) +#define bFM4_MFS3_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270621CUL)) + +#define bFM_MFS3_I2C_ISMK_EN *((volatile uint8_t *)(0x4270623CUL)) +#define bFM4_MFS3_I2C_ISMK_EN *((volatile uint8_t *)(0x4270623CUL)) + +#define bFM_MFS3_I2C_SMR_TIE *((volatile uint8_t *)(0x42706008UL)) +#define bFM4_MFS3_I2C_SMR_TIE *((volatile uint8_t *)(0x42706008UL)) +#define bFM_MFS3_I2C_SMR_RIE *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_I2C_SMR_RIE *((volatile uint8_t *)(0x4270600CUL)) + +#define bFM_MFS3_I2C_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_I2C_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_I2C_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_I2C_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_I2C_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_I2C_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_I2C_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_I2C_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_I2C_SSR_TBIE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_I2C_SSR_TBIE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_I2C_SSR_DMA *((volatile uint8_t *)(0x427060B4UL)) +#define bFM4_MFS3_I2C_SSR_DMA *((volatile uint8_t *)(0x427060B4UL)) +#define bFM_MFS3_I2C_SSR_TSET *((volatile uint8_t *)(0x427060B8UL)) +#define bFM4_MFS3_I2C_SSR_TSET *((volatile uint8_t *)(0x427060B8UL)) +#define bFM_MFS3_I2C_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_I2C_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + +#define bFM_MFS3_LIN_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) +#define bFM4_MFS3_LIN_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) + +#define bFM_MFS3_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42706090UL)) +#define bFM4_MFS3_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42706090UL)) +#define bFM_MFS3_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) + +#define bFM_MFS3_LIN_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_LIN_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_LIN_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_LIN_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_LIN_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_LIN_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_LIN_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_LIN_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_LIN_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_LIN_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_LIN_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_LIN_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_LIN_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_LIN_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_LIN_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_LIN_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_LIN_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_LIN_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_LIN_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_LIN_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_LIN_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_LIN_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_LIN_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_LIN_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_LIN_SCR_LBR *((volatile uint8_t *)(0x42706034UL)) +#define bFM4_MFS3_LIN_SCR_LBR *((volatile uint8_t *)(0x42706034UL)) +#define bFM_MFS3_LIN_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM4_MFS3_LIN_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM_MFS3_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_LIN_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM4_MFS3_LIN_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM_MFS3_LIN_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_LIN_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) +#define bFM_MFS3_LIN_SMR_WUCR *((volatile uint8_t *)(0x42706010UL)) +#define bFM4_MFS3_LIN_SMR_WUCR *((volatile uint8_t *)(0x42706010UL)) + +#define bFM_MFS3_LIN_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_LIN_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_LIN_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_LIN_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_LIN_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_LIN_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_LIN_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_LIN_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_LIN_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_LIN_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_LIN_SSR_LBD *((volatile uint8_t *)(0x427060B4UL)) +#define bFM4_MFS3_LIN_SSR_LBD *((volatile uint8_t *)(0x427060B4UL)) +#define bFM_MFS3_LIN_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_LIN_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + +#define bFM_MFS3_UART_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) +#define bFM4_MFS3_UART_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) + +#define bFM_MFS3_UART_ESCR_P *((volatile uint8_t *)(0x4270608CUL)) +#define bFM4_MFS3_UART_ESCR_P *((volatile uint8_t *)(0x4270608CUL)) +#define bFM_MFS3_UART_ESCR_PEN *((volatile uint8_t *)(0x42706090UL)) +#define bFM4_MFS3_UART_ESCR_PEN *((volatile uint8_t *)(0x42706090UL)) +#define bFM_MFS3_UART_ESCR_INV *((volatile uint8_t *)(0x42706094UL)) +#define bFM4_MFS3_UART_ESCR_INV *((volatile uint8_t *)(0x42706094UL)) +#define bFM_MFS3_UART_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_UART_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) +#define bFM_MFS3_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270609CUL)) +#define bFM4_MFS3_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270609CUL)) + +#define bFM_MFS3_UART_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_UART_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_UART_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_UART_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_UART_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_UART_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_UART_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_UART_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_UART_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_UART_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_UART_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_UART_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_UART_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_UART_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_UART_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_UART_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_UART_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_UART_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_UART_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_UART_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_UART_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_UART_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_UART_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_UART_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_UART_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_UART_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_UART_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_UART_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_UART_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_UART_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_UART_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_UART_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_UART_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_UART_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_UART_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM4_MFS3_UART_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM_MFS3_UART_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM4_MFS3_UART_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM_MFS3_UART_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_UART_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) + +#define bFM_MFS3_UART_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_UART_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_UART_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_UART_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_UART_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_UART_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_UART_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_UART_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_UART_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_UART_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_UART_SSR_PE *((volatile uint8_t *)(0x427060B4UL)) +#define bFM4_MFS3_UART_SSR_PE *((volatile uint8_t *)(0x427060B4UL)) +#define bFM_MFS3_UART_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_UART_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + + +/******************************************************************************* +* MFS Registers MFS4 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS4_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42708094UL)) +#define bFM4_MFS4_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42708094UL)) +#define bFM_MFS4_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42708098UL)) +#define bFM_MFS4_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270809CUL)) +#define bFM4_MFS4_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270809CUL)) + +#define bFM_MFS4_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_CSIO_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_CSIO_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_CSIO_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_CSIO_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_CSIO_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_CSIO_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42708480UL)) +#define bFM4_MFS4_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42708480UL)) +#define bFM_MFS4_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42708498UL)) +#define bFM4_MFS4_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42708498UL)) +#define bFM_MFS4_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270849CUL)) +#define bFM4_MFS4_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270849CUL)) +#define bFM_MFS4_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427084A0UL)) +#define bFM4_MFS4_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427084A0UL)) +#define bFM_MFS4_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427084ACUL)) +#define bFM4_MFS4_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427084ACUL)) +#define bFM_MFS4_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427084B0UL)) +#define bFM4_MFS4_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427084B0UL)) +#define bFM_MFS4_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427084B4UL)) +#define bFM4_MFS4_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427084B4UL)) + +#define bFM_MFS4_CSIO_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_CSIO_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_CSIO_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_CSIO_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_CSIO_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_CSIO_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_CSIO_SCR_SPI *((volatile uint8_t *)(0x42708034UL)) +#define bFM4_MFS4_CSIO_SCR_SPI *((volatile uint8_t *)(0x42708034UL)) +#define bFM_MFS4_CSIO_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM4_MFS4_CSIO_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM_MFS4_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42708600UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42708600UL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42708604UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42708604UL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42708608UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42708608UL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270860CUL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270860CUL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42708610UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42708610UL)) +#define bFM_MFS4_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42708614UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42708614UL)) +#define bFM_MFS4_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42708624UL)) +#define bFM4_MFS4_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42708624UL)) + +#define bFM_MFS4_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42708694UL)) +#define bFM4_MFS4_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42708694UL)) +#define bFM_MFS4_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42708698UL)) +#define bFM4_MFS4_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42708698UL)) +#define bFM_MFS4_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270869CUL)) +#define bFM4_MFS4_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270869CUL)) + +#define bFM_MFS4_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427086B4UL)) +#define bFM4_MFS4_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427086B4UL)) +#define bFM_MFS4_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427086B8UL)) +#define bFM4_MFS4_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427086B8UL)) +#define bFM_MFS4_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427086BCUL)) +#define bFM4_MFS4_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427086BCUL)) + +#define bFM_MFS4_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42708714UL)) +#define bFM4_MFS4_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42708714UL)) +#define bFM_MFS4_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42708718UL)) +#define bFM4_MFS4_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42708718UL)) +#define bFM_MFS4_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270871CUL)) +#define bFM4_MFS4_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270871CUL)) + +#define bFM_MFS4_CSIO_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM4_MFS4_CSIO_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM_MFS4_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42708004UL)) +#define bFM4_MFS4_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42708004UL)) +#define bFM_MFS4_CSIO_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM4_MFS4_CSIO_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM_MFS4_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270800CUL)) + +#define bFM_MFS4_CSIO_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_CSIO_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_CSIO_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_CSIO_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_CSIO_SSR_AWC *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_CSIO_SSR_AWC *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_CSIO_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_CSIO_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + +#define bFM_MFS4_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427083A0UL)) +#define bFM4_MFS4_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427083A0UL)) +#define bFM_MFS4_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427083A4UL)) +#define bFM4_MFS4_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427083A4UL)) +#define bFM_MFS4_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427083A8UL)) +#define bFM4_MFS4_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427083A8UL)) +#define bFM_MFS4_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427083ACUL)) +#define bFM4_MFS4_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427083ACUL)) +#define bFM_MFS4_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427083B0UL)) +#define bFM4_MFS4_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427083B0UL)) +#define bFM_MFS4_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427083B4UL)) +#define bFM4_MFS4_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427083B4UL)) + +#define bFM_MFS4_I2C_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_I2C_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_I2C_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_I2C_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_I2C_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_I2C_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_I2C_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_I2C_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_I2C_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_I2C_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_I2C_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_I2C_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_I2C_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_I2C_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_I2C_IBCR_INT *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_I2C_IBCR_INT *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_I2C_IBCR_BER *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_I2C_IBCR_BER *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_I2C_IBCR_INTE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_I2C_IBCR_INTE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42708034UL)) +#define bFM4_MFS4_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42708034UL)) +#define bFM_MFS4_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42708038UL)) +#define bFM4_MFS4_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42708038UL)) +#define bFM_MFS4_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_I2C_IBSR_BB *((volatile uint8_t *)(0x42708080UL)) +#define bFM4_MFS4_I2C_IBSR_BB *((volatile uint8_t *)(0x42708080UL)) +#define bFM_MFS4_I2C_IBSR_SPC *((volatile uint8_t *)(0x42708084UL)) +#define bFM4_MFS4_I2C_IBSR_SPC *((volatile uint8_t *)(0x42708084UL)) +#define bFM_MFS4_I2C_IBSR_RSC *((volatile uint8_t *)(0x42708088UL)) +#define bFM4_MFS4_I2C_IBSR_RSC *((volatile uint8_t *)(0x42708088UL)) +#define bFM_MFS4_I2C_IBSR_AL *((volatile uint8_t *)(0x4270808CUL)) +#define bFM4_MFS4_I2C_IBSR_AL *((volatile uint8_t *)(0x4270808CUL)) +#define bFM_MFS4_I2C_IBSR_TRX *((volatile uint8_t *)(0x42708090UL)) +#define bFM4_MFS4_I2C_IBSR_TRX *((volatile uint8_t *)(0x42708090UL)) +#define bFM_MFS4_I2C_IBSR_RSA *((volatile uint8_t *)(0x42708094UL)) +#define bFM4_MFS4_I2C_IBSR_RSA *((volatile uint8_t *)(0x42708094UL)) +#define bFM_MFS4_I2C_IBSR_RACK *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_I2C_IBSR_RACK *((volatile uint8_t *)(0x42708098UL)) +#define bFM_MFS4_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270809CUL)) +#define bFM4_MFS4_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270809CUL)) + +#define bFM_MFS4_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270821CUL)) +#define bFM4_MFS4_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270821CUL)) + +#define bFM_MFS4_I2C_ISMK_EN *((volatile uint8_t *)(0x4270823CUL)) +#define bFM4_MFS4_I2C_ISMK_EN *((volatile uint8_t *)(0x4270823CUL)) + +#define bFM_MFS4_I2C_SMR_TIE *((volatile uint8_t *)(0x42708008UL)) +#define bFM4_MFS4_I2C_SMR_TIE *((volatile uint8_t *)(0x42708008UL)) +#define bFM_MFS4_I2C_SMR_RIE *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_I2C_SMR_RIE *((volatile uint8_t *)(0x4270800CUL)) + +#define bFM_MFS4_I2C_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_I2C_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_I2C_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_I2C_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_I2C_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_I2C_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_I2C_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_I2C_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_I2C_SSR_TBIE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_I2C_SSR_TBIE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_I2C_SSR_DMA *((volatile uint8_t *)(0x427080B4UL)) +#define bFM4_MFS4_I2C_SSR_DMA *((volatile uint8_t *)(0x427080B4UL)) +#define bFM_MFS4_I2C_SSR_TSET *((volatile uint8_t *)(0x427080B8UL)) +#define bFM4_MFS4_I2C_SSR_TSET *((volatile uint8_t *)(0x427080B8UL)) +#define bFM_MFS4_I2C_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_I2C_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + +#define bFM_MFS4_LIN_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) +#define bFM4_MFS4_LIN_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) + +#define bFM_MFS4_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42708090UL)) +#define bFM4_MFS4_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42708090UL)) +#define bFM_MFS4_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) + +#define bFM_MFS4_LIN_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_LIN_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_LIN_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_LIN_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_LIN_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_LIN_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_LIN_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_LIN_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_LIN_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_LIN_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_LIN_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_LIN_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_LIN_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_LIN_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_LIN_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_LIN_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_LIN_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_LIN_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_LIN_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_LIN_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_LIN_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_LIN_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_LIN_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_LIN_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_LIN_SCR_LBR *((volatile uint8_t *)(0x42708034UL)) +#define bFM4_MFS4_LIN_SCR_LBR *((volatile uint8_t *)(0x42708034UL)) +#define bFM_MFS4_LIN_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM4_MFS4_LIN_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM_MFS4_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_LIN_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM4_MFS4_LIN_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM_MFS4_LIN_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_LIN_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) +#define bFM_MFS4_LIN_SMR_WUCR *((volatile uint8_t *)(0x42708010UL)) +#define bFM4_MFS4_LIN_SMR_WUCR *((volatile uint8_t *)(0x42708010UL)) + +#define bFM_MFS4_LIN_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_LIN_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_LIN_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_LIN_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_LIN_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_LIN_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_LIN_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_LIN_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_LIN_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_LIN_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_LIN_SSR_LBD *((volatile uint8_t *)(0x427080B4UL)) +#define bFM4_MFS4_LIN_SSR_LBD *((volatile uint8_t *)(0x427080B4UL)) +#define bFM_MFS4_LIN_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_LIN_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + +#define bFM_MFS4_UART_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) +#define bFM4_MFS4_UART_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) + +#define bFM_MFS4_UART_ESCR_P *((volatile uint8_t *)(0x4270808CUL)) +#define bFM4_MFS4_UART_ESCR_P *((volatile uint8_t *)(0x4270808CUL)) +#define bFM_MFS4_UART_ESCR_PEN *((volatile uint8_t *)(0x42708090UL)) +#define bFM4_MFS4_UART_ESCR_PEN *((volatile uint8_t *)(0x42708090UL)) +#define bFM_MFS4_UART_ESCR_INV *((volatile uint8_t *)(0x42708094UL)) +#define bFM4_MFS4_UART_ESCR_INV *((volatile uint8_t *)(0x42708094UL)) +#define bFM_MFS4_UART_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_UART_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) +#define bFM_MFS4_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270809CUL)) +#define bFM4_MFS4_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270809CUL)) + +#define bFM_MFS4_UART_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_UART_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_UART_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_UART_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_UART_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_UART_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_UART_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_UART_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_UART_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_UART_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_UART_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_UART_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_UART_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_UART_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_UART_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_UART_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_UART_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_UART_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_UART_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_UART_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_UART_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_UART_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_UART_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_UART_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_UART_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_UART_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_UART_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_UART_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_UART_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_UART_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_UART_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_UART_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_UART_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_UART_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_UART_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM4_MFS4_UART_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM_MFS4_UART_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM4_MFS4_UART_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM_MFS4_UART_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_UART_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) + +#define bFM_MFS4_UART_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_UART_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_UART_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_UART_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_UART_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_UART_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_UART_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_UART_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_UART_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_UART_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_UART_SSR_PE *((volatile uint8_t *)(0x427080B4UL)) +#define bFM4_MFS4_UART_SSR_PE *((volatile uint8_t *)(0x427080B4UL)) +#define bFM_MFS4_UART_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_UART_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + + +/******************************************************************************* +* MFS Registers MFS5 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS5_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270A094UL)) +#define bFM4_MFS5_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270A094UL)) +#define bFM_MFS5_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270A098UL)) +#define bFM_MFS5_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270A09CUL)) +#define bFM4_MFS5_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270A09CUL)) + +#define bFM_MFS5_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270A480UL)) +#define bFM4_MFS5_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270A480UL)) +#define bFM_MFS5_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270A498UL)) +#define bFM4_MFS5_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270A498UL)) +#define bFM_MFS5_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270A49CUL)) +#define bFM4_MFS5_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270A49CUL)) +#define bFM_MFS5_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270A4A0UL)) +#define bFM4_MFS5_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270A4A0UL)) +#define bFM_MFS5_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270A4ACUL)) +#define bFM4_MFS5_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270A4ACUL)) +#define bFM_MFS5_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270A4B0UL)) +#define bFM4_MFS5_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270A4B0UL)) +#define bFM_MFS5_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270A4B4UL)) +#define bFM4_MFS5_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270A4B4UL)) + +#define bFM_MFS5_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270A034UL)) +#define bFM4_MFS5_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270A034UL)) +#define bFM_MFS5_CSIO_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM4_MFS5_CSIO_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM_MFS5_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270A600UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270A600UL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270A604UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270A604UL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270A608UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270A608UL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270A60CUL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270A60CUL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270A610UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270A610UL)) +#define bFM_MFS5_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270A614UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270A614UL)) +#define bFM_MFS5_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270A624UL)) +#define bFM4_MFS5_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270A624UL)) + +#define bFM_MFS5_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270A694UL)) +#define bFM4_MFS5_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270A694UL)) +#define bFM_MFS5_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270A698UL)) +#define bFM4_MFS5_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270A698UL)) +#define bFM_MFS5_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270A69CUL)) +#define bFM4_MFS5_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270A69CUL)) + +#define bFM_MFS5_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270A6B4UL)) +#define bFM4_MFS5_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270A6B4UL)) +#define bFM_MFS5_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270A6B8UL)) +#define bFM4_MFS5_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270A6B8UL)) +#define bFM_MFS5_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270A6BCUL)) +#define bFM4_MFS5_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270A6BCUL)) + +#define bFM_MFS5_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270A714UL)) +#define bFM4_MFS5_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270A714UL)) +#define bFM_MFS5_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270A718UL)) +#define bFM4_MFS5_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270A718UL)) +#define bFM_MFS5_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270A71CUL)) +#define bFM4_MFS5_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270A71CUL)) + +#define bFM_MFS5_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM4_MFS5_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM_MFS5_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270A004UL)) +#define bFM4_MFS5_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270A004UL)) +#define bFM_MFS5_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM4_MFS5_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM_MFS5_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270A00CUL)) + +#define bFM_MFS5_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_CSIO_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_CSIO_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + +#define bFM_MFS5_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270A3A0UL)) +#define bFM4_MFS5_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270A3A0UL)) +#define bFM_MFS5_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270A3A4UL)) +#define bFM4_MFS5_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270A3A4UL)) +#define bFM_MFS5_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270A3A8UL)) +#define bFM4_MFS5_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270A3A8UL)) +#define bFM_MFS5_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270A3ACUL)) +#define bFM4_MFS5_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270A3ACUL)) +#define bFM_MFS5_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270A3B0UL)) +#define bFM4_MFS5_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270A3B0UL)) +#define bFM_MFS5_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270A3B4UL)) +#define bFM4_MFS5_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270A3B4UL)) + +#define bFM_MFS5_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_I2C_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_I2C_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_I2C_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_I2C_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_I2C_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_I2C_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_I2C_IBCR_INT *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_I2C_IBCR_INT *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_I2C_IBCR_BER *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_I2C_IBCR_BER *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270A034UL)) +#define bFM4_MFS5_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270A034UL)) +#define bFM_MFS5_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270A038UL)) +#define bFM4_MFS5_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270A038UL)) +#define bFM_MFS5_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_I2C_IBSR_BB *((volatile uint8_t *)(0x4270A080UL)) +#define bFM4_MFS5_I2C_IBSR_BB *((volatile uint8_t *)(0x4270A080UL)) +#define bFM_MFS5_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270A084UL)) +#define bFM4_MFS5_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270A084UL)) +#define bFM_MFS5_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270A088UL)) +#define bFM4_MFS5_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270A088UL)) +#define bFM_MFS5_I2C_IBSR_AL *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM4_MFS5_I2C_IBSR_AL *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM_MFS5_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270A090UL)) +#define bFM4_MFS5_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270A090UL)) +#define bFM_MFS5_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270A094UL)) +#define bFM4_MFS5_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270A094UL)) +#define bFM_MFS5_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270A098UL)) +#define bFM_MFS5_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270A09CUL)) +#define bFM4_MFS5_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270A09CUL)) + +#define bFM_MFS5_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270A21CUL)) +#define bFM4_MFS5_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270A21CUL)) + +#define bFM_MFS5_I2C_ISMK_EN *((volatile uint8_t *)(0x4270A23CUL)) +#define bFM4_MFS5_I2C_ISMK_EN *((volatile uint8_t *)(0x4270A23CUL)) + +#define bFM_MFS5_I2C_SMR_TIE *((volatile uint8_t *)(0x4270A008UL)) +#define bFM4_MFS5_I2C_SMR_TIE *((volatile uint8_t *)(0x4270A008UL)) +#define bFM_MFS5_I2C_SMR_RIE *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_I2C_SMR_RIE *((volatile uint8_t *)(0x4270A00CUL)) + +#define bFM_MFS5_I2C_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_I2C_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_I2C_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_I2C_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_I2C_SSR_DMA *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM4_MFS5_I2C_SSR_DMA *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM_MFS5_I2C_SSR_TSET *((volatile uint8_t *)(0x4270A0B8UL)) +#define bFM4_MFS5_I2C_SSR_TSET *((volatile uint8_t *)(0x4270A0B8UL)) +#define bFM_MFS5_I2C_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_I2C_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + +#define bFM_MFS5_LIN_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) +#define bFM4_MFS5_LIN_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) + +#define bFM_MFS5_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270A090UL)) +#define bFM4_MFS5_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270A090UL)) +#define bFM_MFS5_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) + +#define bFM_MFS5_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_LIN_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_LIN_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_LIN_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_LIN_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_LIN_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_LIN_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_LIN_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_LIN_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_LIN_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_LIN_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_LIN_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_LIN_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_LIN_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_LIN_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_LIN_SCR_LBR *((volatile uint8_t *)(0x4270A034UL)) +#define bFM4_MFS5_LIN_SCR_LBR *((volatile uint8_t *)(0x4270A034UL)) +#define bFM_MFS5_LIN_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM4_MFS5_LIN_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM_MFS5_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_LIN_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM4_MFS5_LIN_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM_MFS5_LIN_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_LIN_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM_MFS5_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270A010UL)) +#define bFM4_MFS5_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270A010UL)) + +#define bFM_MFS5_LIN_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_LIN_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_LIN_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_LIN_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_LIN_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_LIN_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_LIN_SSR_LBD *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM4_MFS5_LIN_SSR_LBD *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM_MFS5_LIN_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_LIN_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + +#define bFM_MFS5_UART_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) +#define bFM4_MFS5_UART_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) + +#define bFM_MFS5_UART_ESCR_P *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM4_MFS5_UART_ESCR_P *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM_MFS5_UART_ESCR_PEN *((volatile uint8_t *)(0x4270A090UL)) +#define bFM4_MFS5_UART_ESCR_PEN *((volatile uint8_t *)(0x4270A090UL)) +#define bFM_MFS5_UART_ESCR_INV *((volatile uint8_t *)(0x4270A094UL)) +#define bFM4_MFS5_UART_ESCR_INV *((volatile uint8_t *)(0x4270A094UL)) +#define bFM_MFS5_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) +#define bFM_MFS5_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270A09CUL)) +#define bFM4_MFS5_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270A09CUL)) + +#define bFM_MFS5_UART_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_UART_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_UART_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_UART_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_UART_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_UART_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_UART_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_UART_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_UART_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_UART_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_UART_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_UART_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_UART_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_UART_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_UART_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_UART_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_UART_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_UART_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_UART_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_UART_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_UART_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_UART_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_UART_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_UART_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_UART_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_UART_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_UART_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM4_MFS5_UART_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM_MFS5_UART_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM4_MFS5_UART_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM_MFS5_UART_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_UART_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) + +#define bFM_MFS5_UART_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_UART_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_UART_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_UART_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_UART_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_UART_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_UART_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_UART_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_UART_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_UART_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_UART_SSR_PE *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM4_MFS5_UART_SSR_PE *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM_MFS5_UART_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_UART_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS6 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS6_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270C094UL)) +#define bFM4_MFS6_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270C094UL)) +#define bFM_MFS6_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270C098UL)) +#define bFM_MFS6_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270C09CUL)) +#define bFM4_MFS6_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270C09CUL)) + +#define bFM_MFS6_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270C480UL)) +#define bFM4_MFS6_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270C480UL)) +#define bFM_MFS6_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270C498UL)) +#define bFM4_MFS6_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270C498UL)) +#define bFM_MFS6_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270C49CUL)) +#define bFM4_MFS6_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270C49CUL)) +#define bFM_MFS6_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270C4A0UL)) +#define bFM4_MFS6_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270C4A0UL)) +#define bFM_MFS6_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270C4ACUL)) +#define bFM4_MFS6_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270C4ACUL)) +#define bFM_MFS6_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270C4B0UL)) +#define bFM4_MFS6_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270C4B0UL)) +#define bFM_MFS6_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270C4B4UL)) +#define bFM4_MFS6_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270C4B4UL)) + +#define bFM_MFS6_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270C034UL)) +#define bFM4_MFS6_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270C034UL)) +#define bFM_MFS6_CSIO_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM4_MFS6_CSIO_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM_MFS6_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270C600UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270C600UL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270C604UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270C604UL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270C608UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270C608UL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270C60CUL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270C60CUL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270C610UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270C610UL)) +#define bFM_MFS6_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270C614UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270C614UL)) +#define bFM_MFS6_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270C624UL)) +#define bFM4_MFS6_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270C624UL)) + +#define bFM_MFS6_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270C694UL)) +#define bFM4_MFS6_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270C694UL)) +#define bFM_MFS6_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270C698UL)) +#define bFM4_MFS6_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270C698UL)) +#define bFM_MFS6_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270C69CUL)) +#define bFM4_MFS6_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270C69CUL)) + +#define bFM_MFS6_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270C6B4UL)) +#define bFM4_MFS6_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270C6B4UL)) +#define bFM_MFS6_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270C6B8UL)) +#define bFM4_MFS6_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270C6B8UL)) +#define bFM_MFS6_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270C6BCUL)) +#define bFM4_MFS6_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270C6BCUL)) + +#define bFM_MFS6_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270C714UL)) +#define bFM4_MFS6_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270C714UL)) +#define bFM_MFS6_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270C718UL)) +#define bFM4_MFS6_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270C718UL)) +#define bFM_MFS6_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270C71CUL)) +#define bFM4_MFS6_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270C71CUL)) + +#define bFM_MFS6_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM4_MFS6_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM_MFS6_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270C004UL)) +#define bFM4_MFS6_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270C004UL)) +#define bFM_MFS6_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM4_MFS6_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM_MFS6_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270C00CUL)) + +#define bFM_MFS6_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_CSIO_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_CSIO_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + +#define bFM_MFS6_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270C3A0UL)) +#define bFM4_MFS6_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270C3A0UL)) +#define bFM_MFS6_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270C3A4UL)) +#define bFM4_MFS6_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270C3A4UL)) +#define bFM_MFS6_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270C3A8UL)) +#define bFM4_MFS6_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270C3A8UL)) +#define bFM_MFS6_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270C3ACUL)) +#define bFM4_MFS6_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270C3ACUL)) +#define bFM_MFS6_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270C3B0UL)) +#define bFM4_MFS6_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270C3B0UL)) +#define bFM_MFS6_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270C3B4UL)) +#define bFM4_MFS6_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270C3B4UL)) + +#define bFM_MFS6_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_I2C_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_I2C_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_I2C_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_I2C_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_I2C_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_I2C_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_I2C_IBCR_INT *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_I2C_IBCR_INT *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_I2C_IBCR_BER *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_I2C_IBCR_BER *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270C034UL)) +#define bFM4_MFS6_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270C034UL)) +#define bFM_MFS6_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270C038UL)) +#define bFM4_MFS6_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270C038UL)) +#define bFM_MFS6_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_I2C_IBSR_BB *((volatile uint8_t *)(0x4270C080UL)) +#define bFM4_MFS6_I2C_IBSR_BB *((volatile uint8_t *)(0x4270C080UL)) +#define bFM_MFS6_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270C084UL)) +#define bFM4_MFS6_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270C084UL)) +#define bFM_MFS6_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270C088UL)) +#define bFM4_MFS6_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270C088UL)) +#define bFM_MFS6_I2C_IBSR_AL *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM4_MFS6_I2C_IBSR_AL *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM_MFS6_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270C090UL)) +#define bFM4_MFS6_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270C090UL)) +#define bFM_MFS6_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270C094UL)) +#define bFM4_MFS6_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270C094UL)) +#define bFM_MFS6_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270C098UL)) +#define bFM_MFS6_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270C09CUL)) +#define bFM4_MFS6_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270C09CUL)) + +#define bFM_MFS6_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270C21CUL)) +#define bFM4_MFS6_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270C21CUL)) + +#define bFM_MFS6_I2C_ISMK_EN *((volatile uint8_t *)(0x4270C23CUL)) +#define bFM4_MFS6_I2C_ISMK_EN *((volatile uint8_t *)(0x4270C23CUL)) + +#define bFM_MFS6_I2C_SMR_TIE *((volatile uint8_t *)(0x4270C008UL)) +#define bFM4_MFS6_I2C_SMR_TIE *((volatile uint8_t *)(0x4270C008UL)) +#define bFM_MFS6_I2C_SMR_RIE *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_I2C_SMR_RIE *((volatile uint8_t *)(0x4270C00CUL)) + +#define bFM_MFS6_I2C_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_I2C_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_I2C_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_I2C_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_I2C_SSR_DMA *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM4_MFS6_I2C_SSR_DMA *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM_MFS6_I2C_SSR_TSET *((volatile uint8_t *)(0x4270C0B8UL)) +#define bFM4_MFS6_I2C_SSR_TSET *((volatile uint8_t *)(0x4270C0B8UL)) +#define bFM_MFS6_I2C_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_I2C_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + +#define bFM_MFS6_LIN_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) +#define bFM4_MFS6_LIN_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) + +#define bFM_MFS6_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270C090UL)) +#define bFM4_MFS6_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270C090UL)) +#define bFM_MFS6_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) + +#define bFM_MFS6_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_LIN_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_LIN_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_LIN_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_LIN_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_LIN_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_LIN_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_LIN_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_LIN_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_LIN_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_LIN_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_LIN_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_LIN_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_LIN_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_LIN_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_LIN_SCR_LBR *((volatile uint8_t *)(0x4270C034UL)) +#define bFM4_MFS6_LIN_SCR_LBR *((volatile uint8_t *)(0x4270C034UL)) +#define bFM_MFS6_LIN_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM4_MFS6_LIN_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM_MFS6_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_LIN_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM4_MFS6_LIN_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM_MFS6_LIN_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_LIN_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM_MFS6_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270C010UL)) +#define bFM4_MFS6_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270C010UL)) + +#define bFM_MFS6_LIN_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_LIN_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_LIN_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_LIN_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_LIN_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_LIN_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_LIN_SSR_LBD *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM4_MFS6_LIN_SSR_LBD *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM_MFS6_LIN_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_LIN_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + +#define bFM_MFS6_UART_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) +#define bFM4_MFS6_UART_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) + +#define bFM_MFS6_UART_ESCR_P *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM4_MFS6_UART_ESCR_P *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM_MFS6_UART_ESCR_PEN *((volatile uint8_t *)(0x4270C090UL)) +#define bFM4_MFS6_UART_ESCR_PEN *((volatile uint8_t *)(0x4270C090UL)) +#define bFM_MFS6_UART_ESCR_INV *((volatile uint8_t *)(0x4270C094UL)) +#define bFM4_MFS6_UART_ESCR_INV *((volatile uint8_t *)(0x4270C094UL)) +#define bFM_MFS6_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) +#define bFM_MFS6_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270C09CUL)) +#define bFM4_MFS6_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270C09CUL)) + +#define bFM_MFS6_UART_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_UART_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_UART_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_UART_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_UART_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_UART_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_UART_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_UART_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_UART_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_UART_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_UART_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_UART_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_UART_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_UART_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_UART_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_UART_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_UART_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_UART_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_UART_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_UART_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_UART_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_UART_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_UART_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_UART_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_UART_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_UART_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_UART_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM4_MFS6_UART_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM_MFS6_UART_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM4_MFS6_UART_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM_MFS6_UART_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_UART_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) + +#define bFM_MFS6_UART_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_UART_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_UART_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_UART_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_UART_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_UART_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_UART_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_UART_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_UART_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_UART_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_UART_SSR_PE *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM4_MFS6_UART_SSR_PE *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM_MFS6_UART_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_UART_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS7 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS7_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270E094UL)) +#define bFM4_MFS7_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270E094UL)) +#define bFM_MFS7_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270E098UL)) +#define bFM_MFS7_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270E09CUL)) +#define bFM4_MFS7_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270E09CUL)) + +#define bFM_MFS7_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270E480UL)) +#define bFM4_MFS7_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270E480UL)) +#define bFM_MFS7_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270E498UL)) +#define bFM4_MFS7_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270E498UL)) +#define bFM_MFS7_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270E49CUL)) +#define bFM4_MFS7_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270E49CUL)) +#define bFM_MFS7_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270E4A0UL)) +#define bFM4_MFS7_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270E4A0UL)) +#define bFM_MFS7_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270E4ACUL)) +#define bFM4_MFS7_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270E4ACUL)) +#define bFM_MFS7_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270E4B0UL)) +#define bFM4_MFS7_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270E4B0UL)) +#define bFM_MFS7_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270E4B4UL)) +#define bFM4_MFS7_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270E4B4UL)) + +#define bFM_MFS7_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270E034UL)) +#define bFM4_MFS7_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270E034UL)) +#define bFM_MFS7_CSIO_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM4_MFS7_CSIO_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM_MFS7_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270E600UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270E600UL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270E604UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270E604UL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270E608UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270E608UL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270E60CUL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270E60CUL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270E610UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270E610UL)) +#define bFM_MFS7_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270E614UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270E614UL)) +#define bFM_MFS7_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270E624UL)) +#define bFM4_MFS7_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270E624UL)) + +#define bFM_MFS7_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270E694UL)) +#define bFM4_MFS7_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270E694UL)) +#define bFM_MFS7_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270E698UL)) +#define bFM4_MFS7_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270E698UL)) +#define bFM_MFS7_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270E69CUL)) +#define bFM4_MFS7_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270E69CUL)) + +#define bFM_MFS7_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270E6B4UL)) +#define bFM4_MFS7_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270E6B4UL)) +#define bFM_MFS7_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270E6B8UL)) +#define bFM4_MFS7_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270E6B8UL)) +#define bFM_MFS7_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270E6BCUL)) +#define bFM4_MFS7_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270E6BCUL)) + +#define bFM_MFS7_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270E714UL)) +#define bFM4_MFS7_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270E714UL)) +#define bFM_MFS7_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270E718UL)) +#define bFM4_MFS7_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270E718UL)) +#define bFM_MFS7_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270E71CUL)) +#define bFM4_MFS7_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270E71CUL)) + +#define bFM_MFS7_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM4_MFS7_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM_MFS7_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270E004UL)) +#define bFM4_MFS7_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270E004UL)) +#define bFM_MFS7_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM4_MFS7_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM_MFS7_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270E00CUL)) + +#define bFM_MFS7_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_CSIO_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_CSIO_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + +#define bFM_MFS7_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270E3A0UL)) +#define bFM4_MFS7_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270E3A0UL)) +#define bFM_MFS7_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270E3A4UL)) +#define bFM4_MFS7_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270E3A4UL)) +#define bFM_MFS7_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270E3A8UL)) +#define bFM4_MFS7_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270E3A8UL)) +#define bFM_MFS7_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270E3ACUL)) +#define bFM4_MFS7_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270E3ACUL)) +#define bFM_MFS7_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270E3B0UL)) +#define bFM4_MFS7_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270E3B0UL)) +#define bFM_MFS7_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270E3B4UL)) +#define bFM4_MFS7_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270E3B4UL)) + +#define bFM_MFS7_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_I2C_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_I2C_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_I2C_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_I2C_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_I2C_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_I2C_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_I2C_IBCR_INT *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_I2C_IBCR_INT *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_I2C_IBCR_BER *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_I2C_IBCR_BER *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270E034UL)) +#define bFM4_MFS7_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270E034UL)) +#define bFM_MFS7_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270E038UL)) +#define bFM4_MFS7_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270E038UL)) +#define bFM_MFS7_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_I2C_IBSR_BB *((volatile uint8_t *)(0x4270E080UL)) +#define bFM4_MFS7_I2C_IBSR_BB *((volatile uint8_t *)(0x4270E080UL)) +#define bFM_MFS7_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270E084UL)) +#define bFM4_MFS7_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270E084UL)) +#define bFM_MFS7_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270E088UL)) +#define bFM4_MFS7_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270E088UL)) +#define bFM_MFS7_I2C_IBSR_AL *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM4_MFS7_I2C_IBSR_AL *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM_MFS7_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270E090UL)) +#define bFM4_MFS7_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270E090UL)) +#define bFM_MFS7_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270E094UL)) +#define bFM4_MFS7_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270E094UL)) +#define bFM_MFS7_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270E098UL)) +#define bFM_MFS7_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270E09CUL)) +#define bFM4_MFS7_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270E09CUL)) + +#define bFM_MFS7_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270E21CUL)) +#define bFM4_MFS7_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270E21CUL)) + +#define bFM_MFS7_I2C_ISMK_EN *((volatile uint8_t *)(0x4270E23CUL)) +#define bFM4_MFS7_I2C_ISMK_EN *((volatile uint8_t *)(0x4270E23CUL)) + +#define bFM_MFS7_I2C_SMR_TIE *((volatile uint8_t *)(0x4270E008UL)) +#define bFM4_MFS7_I2C_SMR_TIE *((volatile uint8_t *)(0x4270E008UL)) +#define bFM_MFS7_I2C_SMR_RIE *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_I2C_SMR_RIE *((volatile uint8_t *)(0x4270E00CUL)) + +#define bFM_MFS7_I2C_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_I2C_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_I2C_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_I2C_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_I2C_SSR_DMA *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM4_MFS7_I2C_SSR_DMA *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM_MFS7_I2C_SSR_TSET *((volatile uint8_t *)(0x4270E0B8UL)) +#define bFM4_MFS7_I2C_SSR_TSET *((volatile uint8_t *)(0x4270E0B8UL)) +#define bFM_MFS7_I2C_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_I2C_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + +#define bFM_MFS7_LIN_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) +#define bFM4_MFS7_LIN_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) + +#define bFM_MFS7_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270E090UL)) +#define bFM4_MFS7_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270E090UL)) +#define bFM_MFS7_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) + +#define bFM_MFS7_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_LIN_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_LIN_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_LIN_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_LIN_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_LIN_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_LIN_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_LIN_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_LIN_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_LIN_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_LIN_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_LIN_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_LIN_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_LIN_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_LIN_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_LIN_SCR_LBR *((volatile uint8_t *)(0x4270E034UL)) +#define bFM4_MFS7_LIN_SCR_LBR *((volatile uint8_t *)(0x4270E034UL)) +#define bFM_MFS7_LIN_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM4_MFS7_LIN_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM_MFS7_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_LIN_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM4_MFS7_LIN_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM_MFS7_LIN_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_LIN_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM_MFS7_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270E010UL)) +#define bFM4_MFS7_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270E010UL)) + +#define bFM_MFS7_LIN_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_LIN_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_LIN_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_LIN_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_LIN_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_LIN_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_LIN_SSR_LBD *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM4_MFS7_LIN_SSR_LBD *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM_MFS7_LIN_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_LIN_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + +#define bFM_MFS7_UART_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) +#define bFM4_MFS7_UART_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) + +#define bFM_MFS7_UART_ESCR_P *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM4_MFS7_UART_ESCR_P *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM_MFS7_UART_ESCR_PEN *((volatile uint8_t *)(0x4270E090UL)) +#define bFM4_MFS7_UART_ESCR_PEN *((volatile uint8_t *)(0x4270E090UL)) +#define bFM_MFS7_UART_ESCR_INV *((volatile uint8_t *)(0x4270E094UL)) +#define bFM4_MFS7_UART_ESCR_INV *((volatile uint8_t *)(0x4270E094UL)) +#define bFM_MFS7_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) +#define bFM_MFS7_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270E09CUL)) +#define bFM4_MFS7_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270E09CUL)) + +#define bFM_MFS7_UART_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_UART_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_UART_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_UART_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_UART_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_UART_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_UART_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_UART_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_UART_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_UART_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_UART_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_UART_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_UART_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_UART_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_UART_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_UART_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_UART_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_UART_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_UART_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_UART_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_UART_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_UART_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_UART_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_UART_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_UART_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_UART_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_UART_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM4_MFS7_UART_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM_MFS7_UART_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM4_MFS7_UART_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM_MFS7_UART_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_UART_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) + +#define bFM_MFS7_UART_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_UART_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_UART_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_UART_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_UART_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_UART_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_UART_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_UART_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_UART_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_UART_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_UART_SSR_PE *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM4_MFS7_UART_SSR_PE *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM_MFS7_UART_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_UART_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS8 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS8_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42710094UL)) +#define bFM4_MFS8_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42710094UL)) +#define bFM_MFS8_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42710098UL)) +#define bFM_MFS8_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271009CUL)) +#define bFM4_MFS8_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271009CUL)) + +#define bFM_MFS8_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_CSIO_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_CSIO_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_CSIO_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_CSIO_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_CSIO_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_CSIO_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42710480UL)) +#define bFM4_MFS8_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42710480UL)) +#define bFM_MFS8_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42710498UL)) +#define bFM4_MFS8_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42710498UL)) +#define bFM_MFS8_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271049CUL)) +#define bFM4_MFS8_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271049CUL)) +#define bFM_MFS8_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427104A0UL)) +#define bFM4_MFS8_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427104A0UL)) +#define bFM_MFS8_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427104ACUL)) +#define bFM4_MFS8_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427104ACUL)) +#define bFM_MFS8_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427104B0UL)) +#define bFM4_MFS8_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427104B0UL)) +#define bFM_MFS8_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427104B4UL)) +#define bFM4_MFS8_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427104B4UL)) + +#define bFM_MFS8_CSIO_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_CSIO_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_CSIO_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_CSIO_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_CSIO_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_CSIO_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_CSIO_SCR_SPI *((volatile uint8_t *)(0x42710034UL)) +#define bFM4_MFS8_CSIO_SCR_SPI *((volatile uint8_t *)(0x42710034UL)) +#define bFM_MFS8_CSIO_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM4_MFS8_CSIO_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM_MFS8_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42710600UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42710600UL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42710604UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42710604UL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42710608UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42710608UL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271060CUL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271060CUL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42710610UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42710610UL)) +#define bFM_MFS8_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42710614UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42710614UL)) +#define bFM_MFS8_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42710624UL)) +#define bFM4_MFS8_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42710624UL)) + +#define bFM_MFS8_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42710694UL)) +#define bFM4_MFS8_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42710694UL)) +#define bFM_MFS8_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42710698UL)) +#define bFM4_MFS8_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42710698UL)) +#define bFM_MFS8_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271069CUL)) +#define bFM4_MFS8_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271069CUL)) + +#define bFM_MFS8_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427106B4UL)) +#define bFM4_MFS8_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427106B4UL)) +#define bFM_MFS8_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427106B8UL)) +#define bFM4_MFS8_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427106B8UL)) +#define bFM_MFS8_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427106BCUL)) +#define bFM4_MFS8_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427106BCUL)) + +#define bFM_MFS8_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42710714UL)) +#define bFM4_MFS8_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42710714UL)) +#define bFM_MFS8_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42710718UL)) +#define bFM4_MFS8_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42710718UL)) +#define bFM_MFS8_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271071CUL)) +#define bFM4_MFS8_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271071CUL)) + +#define bFM_MFS8_CSIO_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM4_MFS8_CSIO_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM_MFS8_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42710004UL)) +#define bFM4_MFS8_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42710004UL)) +#define bFM_MFS8_CSIO_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM4_MFS8_CSIO_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM_MFS8_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271000CUL)) + +#define bFM_MFS8_CSIO_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_CSIO_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_CSIO_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_CSIO_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_CSIO_SSR_AWC *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_CSIO_SSR_AWC *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_CSIO_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_CSIO_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + +#define bFM_MFS8_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427103A0UL)) +#define bFM4_MFS8_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427103A0UL)) +#define bFM_MFS8_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427103A4UL)) +#define bFM4_MFS8_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427103A4UL)) +#define bFM_MFS8_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427103A8UL)) +#define bFM4_MFS8_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427103A8UL)) +#define bFM_MFS8_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427103ACUL)) +#define bFM4_MFS8_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427103ACUL)) +#define bFM_MFS8_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427103B0UL)) +#define bFM4_MFS8_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427103B0UL)) +#define bFM_MFS8_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427103B4UL)) +#define bFM4_MFS8_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427103B4UL)) + +#define bFM_MFS8_I2C_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_I2C_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_I2C_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_I2C_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_I2C_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_I2C_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_I2C_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_I2C_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_I2C_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_I2C_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_I2C_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_I2C_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_I2C_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_I2C_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_I2C_IBCR_INT *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_I2C_IBCR_INT *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_I2C_IBCR_BER *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_I2C_IBCR_BER *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_I2C_IBCR_INTE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_I2C_IBCR_INTE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42710034UL)) +#define bFM4_MFS8_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42710034UL)) +#define bFM_MFS8_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42710038UL)) +#define bFM4_MFS8_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42710038UL)) +#define bFM_MFS8_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_I2C_IBSR_BB *((volatile uint8_t *)(0x42710080UL)) +#define bFM4_MFS8_I2C_IBSR_BB *((volatile uint8_t *)(0x42710080UL)) +#define bFM_MFS8_I2C_IBSR_SPC *((volatile uint8_t *)(0x42710084UL)) +#define bFM4_MFS8_I2C_IBSR_SPC *((volatile uint8_t *)(0x42710084UL)) +#define bFM_MFS8_I2C_IBSR_RSC *((volatile uint8_t *)(0x42710088UL)) +#define bFM4_MFS8_I2C_IBSR_RSC *((volatile uint8_t *)(0x42710088UL)) +#define bFM_MFS8_I2C_IBSR_AL *((volatile uint8_t *)(0x4271008CUL)) +#define bFM4_MFS8_I2C_IBSR_AL *((volatile uint8_t *)(0x4271008CUL)) +#define bFM_MFS8_I2C_IBSR_TRX *((volatile uint8_t *)(0x42710090UL)) +#define bFM4_MFS8_I2C_IBSR_TRX *((volatile uint8_t *)(0x42710090UL)) +#define bFM_MFS8_I2C_IBSR_RSA *((volatile uint8_t *)(0x42710094UL)) +#define bFM4_MFS8_I2C_IBSR_RSA *((volatile uint8_t *)(0x42710094UL)) +#define bFM_MFS8_I2C_IBSR_RACK *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_I2C_IBSR_RACK *((volatile uint8_t *)(0x42710098UL)) +#define bFM_MFS8_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271009CUL)) +#define bFM4_MFS8_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271009CUL)) + +#define bFM_MFS8_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271021CUL)) +#define bFM4_MFS8_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271021CUL)) + +#define bFM_MFS8_I2C_ISMK_EN *((volatile uint8_t *)(0x4271023CUL)) +#define bFM4_MFS8_I2C_ISMK_EN *((volatile uint8_t *)(0x4271023CUL)) + +#define bFM_MFS8_I2C_SMR_TIE *((volatile uint8_t *)(0x42710008UL)) +#define bFM4_MFS8_I2C_SMR_TIE *((volatile uint8_t *)(0x42710008UL)) +#define bFM_MFS8_I2C_SMR_RIE *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_I2C_SMR_RIE *((volatile uint8_t *)(0x4271000CUL)) + +#define bFM_MFS8_I2C_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_I2C_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_I2C_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_I2C_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_I2C_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_I2C_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_I2C_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_I2C_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_I2C_SSR_TBIE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_I2C_SSR_TBIE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_I2C_SSR_DMA *((volatile uint8_t *)(0x427100B4UL)) +#define bFM4_MFS8_I2C_SSR_DMA *((volatile uint8_t *)(0x427100B4UL)) +#define bFM_MFS8_I2C_SSR_TSET *((volatile uint8_t *)(0x427100B8UL)) +#define bFM4_MFS8_I2C_SSR_TSET *((volatile uint8_t *)(0x427100B8UL)) +#define bFM_MFS8_I2C_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_I2C_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + +#define bFM_MFS8_LIN_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) +#define bFM4_MFS8_LIN_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) + +#define bFM_MFS8_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42710090UL)) +#define bFM4_MFS8_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42710090UL)) +#define bFM_MFS8_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) + +#define bFM_MFS8_LIN_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_LIN_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_LIN_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_LIN_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_LIN_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_LIN_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_LIN_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_LIN_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_LIN_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_LIN_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_LIN_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_LIN_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_LIN_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_LIN_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_LIN_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_LIN_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_LIN_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_LIN_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_LIN_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_LIN_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_LIN_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_LIN_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_LIN_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_LIN_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_LIN_SCR_LBR *((volatile uint8_t *)(0x42710034UL)) +#define bFM4_MFS8_LIN_SCR_LBR *((volatile uint8_t *)(0x42710034UL)) +#define bFM_MFS8_LIN_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM4_MFS8_LIN_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM_MFS8_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_LIN_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM4_MFS8_LIN_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM_MFS8_LIN_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_LIN_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) +#define bFM_MFS8_LIN_SMR_WUCR *((volatile uint8_t *)(0x42710010UL)) +#define bFM4_MFS8_LIN_SMR_WUCR *((volatile uint8_t *)(0x42710010UL)) + +#define bFM_MFS8_LIN_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_LIN_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_LIN_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_LIN_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_LIN_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_LIN_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_LIN_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_LIN_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_LIN_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_LIN_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_LIN_SSR_LBD *((volatile uint8_t *)(0x427100B4UL)) +#define bFM4_MFS8_LIN_SSR_LBD *((volatile uint8_t *)(0x427100B4UL)) +#define bFM_MFS8_LIN_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_LIN_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + +#define bFM_MFS8_UART_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) +#define bFM4_MFS8_UART_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) + +#define bFM_MFS8_UART_ESCR_P *((volatile uint8_t *)(0x4271008CUL)) +#define bFM4_MFS8_UART_ESCR_P *((volatile uint8_t *)(0x4271008CUL)) +#define bFM_MFS8_UART_ESCR_PEN *((volatile uint8_t *)(0x42710090UL)) +#define bFM4_MFS8_UART_ESCR_PEN *((volatile uint8_t *)(0x42710090UL)) +#define bFM_MFS8_UART_ESCR_INV *((volatile uint8_t *)(0x42710094UL)) +#define bFM4_MFS8_UART_ESCR_INV *((volatile uint8_t *)(0x42710094UL)) +#define bFM_MFS8_UART_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_UART_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) +#define bFM_MFS8_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271009CUL)) +#define bFM4_MFS8_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271009CUL)) + +#define bFM_MFS8_UART_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_UART_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_UART_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_UART_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_UART_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_UART_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_UART_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_UART_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_UART_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_UART_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_UART_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_UART_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_UART_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_UART_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_UART_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_UART_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_UART_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_UART_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_UART_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_UART_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_UART_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_UART_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_UART_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_UART_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_UART_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_UART_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_UART_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_UART_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_UART_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_UART_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_UART_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_UART_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_UART_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_UART_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_UART_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM4_MFS8_UART_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM_MFS8_UART_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM4_MFS8_UART_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM_MFS8_UART_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_UART_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) + +#define bFM_MFS8_UART_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_UART_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_UART_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_UART_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_UART_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_UART_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_UART_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_UART_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_UART_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_UART_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_UART_SSR_PE *((volatile uint8_t *)(0x427100B4UL)) +#define bFM4_MFS8_UART_SSR_PE *((volatile uint8_t *)(0x427100B4UL)) +#define bFM_MFS8_UART_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_UART_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + + +/******************************************************************************* +* MFS Registers MFS9 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS9_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42712094UL)) +#define bFM4_MFS9_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42712094UL)) +#define bFM_MFS9_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42712098UL)) +#define bFM_MFS9_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271209CUL)) +#define bFM4_MFS9_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271209CUL)) + +#define bFM_MFS9_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_CSIO_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_CSIO_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_CSIO_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_CSIO_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_CSIO_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_CSIO_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42712480UL)) +#define bFM4_MFS9_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42712480UL)) +#define bFM_MFS9_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42712498UL)) +#define bFM4_MFS9_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42712498UL)) +#define bFM_MFS9_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271249CUL)) +#define bFM4_MFS9_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271249CUL)) +#define bFM_MFS9_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427124A0UL)) +#define bFM4_MFS9_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427124A0UL)) +#define bFM_MFS9_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427124ACUL)) +#define bFM4_MFS9_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427124ACUL)) +#define bFM_MFS9_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427124B0UL)) +#define bFM4_MFS9_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427124B0UL)) +#define bFM_MFS9_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427124B4UL)) +#define bFM4_MFS9_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427124B4UL)) + +#define bFM_MFS9_CSIO_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_CSIO_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_CSIO_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_CSIO_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_CSIO_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_CSIO_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_CSIO_SCR_SPI *((volatile uint8_t *)(0x42712034UL)) +#define bFM4_MFS9_CSIO_SCR_SPI *((volatile uint8_t *)(0x42712034UL)) +#define bFM_MFS9_CSIO_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM4_MFS9_CSIO_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM_MFS9_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42712600UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42712600UL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42712604UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42712604UL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42712608UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42712608UL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271260CUL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271260CUL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42712610UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42712610UL)) +#define bFM_MFS9_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42712614UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42712614UL)) +#define bFM_MFS9_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42712624UL)) +#define bFM4_MFS9_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42712624UL)) + +#define bFM_MFS9_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42712694UL)) +#define bFM4_MFS9_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42712694UL)) +#define bFM_MFS9_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42712698UL)) +#define bFM4_MFS9_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42712698UL)) +#define bFM_MFS9_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271269CUL)) +#define bFM4_MFS9_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271269CUL)) + +#define bFM_MFS9_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427126B4UL)) +#define bFM4_MFS9_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427126B4UL)) +#define bFM_MFS9_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427126B8UL)) +#define bFM4_MFS9_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427126B8UL)) +#define bFM_MFS9_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427126BCUL)) +#define bFM4_MFS9_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427126BCUL)) + +#define bFM_MFS9_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42712714UL)) +#define bFM4_MFS9_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42712714UL)) +#define bFM_MFS9_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42712718UL)) +#define bFM4_MFS9_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42712718UL)) +#define bFM_MFS9_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271271CUL)) +#define bFM4_MFS9_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271271CUL)) + +#define bFM_MFS9_CSIO_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM4_MFS9_CSIO_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM_MFS9_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42712004UL)) +#define bFM4_MFS9_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42712004UL)) +#define bFM_MFS9_CSIO_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM4_MFS9_CSIO_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM_MFS9_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271200CUL)) + +#define bFM_MFS9_CSIO_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_CSIO_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_CSIO_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_CSIO_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_CSIO_SSR_AWC *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_CSIO_SSR_AWC *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_CSIO_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_CSIO_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + +#define bFM_MFS9_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427123A0UL)) +#define bFM4_MFS9_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427123A0UL)) +#define bFM_MFS9_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427123A4UL)) +#define bFM4_MFS9_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427123A4UL)) +#define bFM_MFS9_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427123A8UL)) +#define bFM4_MFS9_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427123A8UL)) +#define bFM_MFS9_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427123ACUL)) +#define bFM4_MFS9_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427123ACUL)) +#define bFM_MFS9_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427123B0UL)) +#define bFM4_MFS9_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427123B0UL)) +#define bFM_MFS9_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427123B4UL)) +#define bFM4_MFS9_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427123B4UL)) + +#define bFM_MFS9_I2C_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_I2C_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_I2C_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_I2C_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_I2C_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_I2C_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_I2C_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_I2C_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_I2C_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_I2C_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_I2C_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_I2C_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_I2C_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_I2C_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_I2C_IBCR_INT *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_I2C_IBCR_INT *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_I2C_IBCR_BER *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_I2C_IBCR_BER *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_I2C_IBCR_INTE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_I2C_IBCR_INTE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42712034UL)) +#define bFM4_MFS9_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42712034UL)) +#define bFM_MFS9_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42712038UL)) +#define bFM4_MFS9_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42712038UL)) +#define bFM_MFS9_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_I2C_IBSR_BB *((volatile uint8_t *)(0x42712080UL)) +#define bFM4_MFS9_I2C_IBSR_BB *((volatile uint8_t *)(0x42712080UL)) +#define bFM_MFS9_I2C_IBSR_SPC *((volatile uint8_t *)(0x42712084UL)) +#define bFM4_MFS9_I2C_IBSR_SPC *((volatile uint8_t *)(0x42712084UL)) +#define bFM_MFS9_I2C_IBSR_RSC *((volatile uint8_t *)(0x42712088UL)) +#define bFM4_MFS9_I2C_IBSR_RSC *((volatile uint8_t *)(0x42712088UL)) +#define bFM_MFS9_I2C_IBSR_AL *((volatile uint8_t *)(0x4271208CUL)) +#define bFM4_MFS9_I2C_IBSR_AL *((volatile uint8_t *)(0x4271208CUL)) +#define bFM_MFS9_I2C_IBSR_TRX *((volatile uint8_t *)(0x42712090UL)) +#define bFM4_MFS9_I2C_IBSR_TRX *((volatile uint8_t *)(0x42712090UL)) +#define bFM_MFS9_I2C_IBSR_RSA *((volatile uint8_t *)(0x42712094UL)) +#define bFM4_MFS9_I2C_IBSR_RSA *((volatile uint8_t *)(0x42712094UL)) +#define bFM_MFS9_I2C_IBSR_RACK *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_I2C_IBSR_RACK *((volatile uint8_t *)(0x42712098UL)) +#define bFM_MFS9_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271209CUL)) +#define bFM4_MFS9_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271209CUL)) + +#define bFM_MFS9_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271221CUL)) +#define bFM4_MFS9_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271221CUL)) + +#define bFM_MFS9_I2C_ISMK_EN *((volatile uint8_t *)(0x4271223CUL)) +#define bFM4_MFS9_I2C_ISMK_EN *((volatile uint8_t *)(0x4271223CUL)) + +#define bFM_MFS9_I2C_SMR_TIE *((volatile uint8_t *)(0x42712008UL)) +#define bFM4_MFS9_I2C_SMR_TIE *((volatile uint8_t *)(0x42712008UL)) +#define bFM_MFS9_I2C_SMR_RIE *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_I2C_SMR_RIE *((volatile uint8_t *)(0x4271200CUL)) + +#define bFM_MFS9_I2C_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_I2C_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_I2C_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_I2C_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_I2C_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_I2C_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_I2C_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_I2C_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_I2C_SSR_TBIE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_I2C_SSR_TBIE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_I2C_SSR_DMA *((volatile uint8_t *)(0x427120B4UL)) +#define bFM4_MFS9_I2C_SSR_DMA *((volatile uint8_t *)(0x427120B4UL)) +#define bFM_MFS9_I2C_SSR_TSET *((volatile uint8_t *)(0x427120B8UL)) +#define bFM4_MFS9_I2C_SSR_TSET *((volatile uint8_t *)(0x427120B8UL)) +#define bFM_MFS9_I2C_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_I2C_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + +#define bFM_MFS9_LIN_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) +#define bFM4_MFS9_LIN_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) + +#define bFM_MFS9_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42712090UL)) +#define bFM4_MFS9_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42712090UL)) +#define bFM_MFS9_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) + +#define bFM_MFS9_LIN_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_LIN_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_LIN_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_LIN_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_LIN_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_LIN_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_LIN_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_LIN_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_LIN_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_LIN_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_LIN_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_LIN_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_LIN_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_LIN_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_LIN_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_LIN_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_LIN_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_LIN_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_LIN_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_LIN_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_LIN_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_LIN_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_LIN_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_LIN_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_LIN_SCR_LBR *((volatile uint8_t *)(0x42712034UL)) +#define bFM4_MFS9_LIN_SCR_LBR *((volatile uint8_t *)(0x42712034UL)) +#define bFM_MFS9_LIN_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM4_MFS9_LIN_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM_MFS9_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_LIN_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM4_MFS9_LIN_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM_MFS9_LIN_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_LIN_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) +#define bFM_MFS9_LIN_SMR_WUCR *((volatile uint8_t *)(0x42712010UL)) +#define bFM4_MFS9_LIN_SMR_WUCR *((volatile uint8_t *)(0x42712010UL)) + +#define bFM_MFS9_LIN_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_LIN_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_LIN_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_LIN_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_LIN_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_LIN_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_LIN_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_LIN_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_LIN_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_LIN_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_LIN_SSR_LBD *((volatile uint8_t *)(0x427120B4UL)) +#define bFM4_MFS9_LIN_SSR_LBD *((volatile uint8_t *)(0x427120B4UL)) +#define bFM_MFS9_LIN_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_LIN_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + +#define bFM_MFS9_UART_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) +#define bFM4_MFS9_UART_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) + +#define bFM_MFS9_UART_ESCR_P *((volatile uint8_t *)(0x4271208CUL)) +#define bFM4_MFS9_UART_ESCR_P *((volatile uint8_t *)(0x4271208CUL)) +#define bFM_MFS9_UART_ESCR_PEN *((volatile uint8_t *)(0x42712090UL)) +#define bFM4_MFS9_UART_ESCR_PEN *((volatile uint8_t *)(0x42712090UL)) +#define bFM_MFS9_UART_ESCR_INV *((volatile uint8_t *)(0x42712094UL)) +#define bFM4_MFS9_UART_ESCR_INV *((volatile uint8_t *)(0x42712094UL)) +#define bFM_MFS9_UART_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_UART_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) +#define bFM_MFS9_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271209CUL)) +#define bFM4_MFS9_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271209CUL)) + +#define bFM_MFS9_UART_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_UART_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_UART_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_UART_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_UART_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_UART_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_UART_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_UART_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_UART_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_UART_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_UART_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_UART_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_UART_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_UART_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_UART_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_UART_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_UART_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_UART_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_UART_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_UART_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_UART_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_UART_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_UART_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_UART_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_UART_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_UART_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_UART_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_UART_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_UART_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_UART_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_UART_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_UART_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_UART_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_UART_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_UART_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM4_MFS9_UART_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM_MFS9_UART_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM4_MFS9_UART_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM_MFS9_UART_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_UART_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) + +#define bFM_MFS9_UART_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_UART_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_UART_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_UART_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_UART_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_UART_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_UART_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_UART_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_UART_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_UART_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_UART_SSR_PE *((volatile uint8_t *)(0x427120B4UL)) +#define bFM4_MFS9_UART_SSR_PE *((volatile uint8_t *)(0x427120B4UL)) +#define bFM_MFS9_UART_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_UART_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + + +/******************************************************************************* +* MFT_PPG Registers MFT_PPG +* Bitband Section +*******************************************************************************/ +#define bFM_MFT_PPG_GATEC0_EDGE0 *((volatile uint8_t *)(0x42484300UL)) +#define bFM4_MFT_PPG_GATEC0_EDGE0 *((volatile uint8_t *)(0x42484300UL)) +#define bFM_MFT_PPG_GATEC0_STRG0 *((volatile uint8_t *)(0x42484304UL)) +#define bFM4_MFT_PPG_GATEC0_STRG0 *((volatile uint8_t *)(0x42484304UL)) +#define bFM_MFT_PPG_GATEC0_EDGE2 *((volatile uint8_t *)(0x42484310UL)) +#define bFM4_MFT_PPG_GATEC0_EDGE2 *((volatile uint8_t *)(0x42484310UL)) +#define bFM_MFT_PPG_GATEC0_STRG2 *((volatile uint8_t *)(0x42484314UL)) +#define bFM4_MFT_PPG_GATEC0_STRG2 *((volatile uint8_t *)(0x42484314UL)) + +#define bFM_MFT_PPG_GATEC12_EDGE12 *((volatile uint8_t *)(0x42485B00UL)) +#define bFM4_MFT_PPG_GATEC12_EDGE12 *((volatile uint8_t *)(0x42485B00UL)) +#define bFM_MFT_PPG_GATEC12_STRG12 *((volatile uint8_t *)(0x42485B04UL)) +#define bFM4_MFT_PPG_GATEC12_STRG12 *((volatile uint8_t *)(0x42485B04UL)) +#define bFM_MFT_PPG_GATEC12_EDGE14 *((volatile uint8_t *)(0x42485B10UL)) +#define bFM4_MFT_PPG_GATEC12_EDGE14 *((volatile uint8_t *)(0x42485B10UL)) +#define bFM_MFT_PPG_GATEC12_STRG14 *((volatile uint8_t *)(0x42485B14UL)) +#define bFM4_MFT_PPG_GATEC12_STRG14 *((volatile uint8_t *)(0x42485B14UL)) + +#define bFM_MFT_PPG_GATEC16_EDGE16 *((volatile uint8_t *)(0x42486300UL)) +#define bFM4_MFT_PPG_GATEC16_EDGE16 *((volatile uint8_t *)(0x42486300UL)) +#define bFM_MFT_PPG_GATEC16_STRG16 *((volatile uint8_t *)(0x42486304UL)) +#define bFM4_MFT_PPG_GATEC16_STRG16 *((volatile uint8_t *)(0x42486304UL)) +#define bFM_MFT_PPG_GATEC16_EDGE18 *((volatile uint8_t *)(0x42486310UL)) +#define bFM4_MFT_PPG_GATEC16_EDGE18 *((volatile uint8_t *)(0x42486310UL)) +#define bFM_MFT_PPG_GATEC16_STRG18 *((volatile uint8_t *)(0x42486314UL)) +#define bFM4_MFT_PPG_GATEC16_STRG18 *((volatile uint8_t *)(0x42486314UL)) + +#define bFM_MFT_PPG_GATEC20_EDGE20 *((volatile uint8_t *)(0x42486B00UL)) +#define bFM4_MFT_PPG_GATEC20_EDGE20 *((volatile uint8_t *)(0x42486B00UL)) +#define bFM_MFT_PPG_GATEC20_STRG20 *((volatile uint8_t *)(0x42486B04UL)) +#define bFM4_MFT_PPG_GATEC20_STRG20 *((volatile uint8_t *)(0x42486B04UL)) +#define bFM_MFT_PPG_GATEC20_EDGE22 *((volatile uint8_t *)(0x42486B10UL)) +#define bFM4_MFT_PPG_GATEC20_EDGE22 *((volatile uint8_t *)(0x42486B10UL)) +#define bFM_MFT_PPG_GATEC20_STRG22 *((volatile uint8_t *)(0x42486B14UL)) +#define bFM4_MFT_PPG_GATEC20_STRG22 *((volatile uint8_t *)(0x42486B14UL)) + +#define bFM_MFT_PPG_GATEC4_EDGE4 *((volatile uint8_t *)(0x42484B00UL)) +#define bFM4_MFT_PPG_GATEC4_EDGE4 *((volatile uint8_t *)(0x42484B00UL)) +#define bFM_MFT_PPG_GATEC4_STRG4 *((volatile uint8_t *)(0x42484B04UL)) +#define bFM4_MFT_PPG_GATEC4_STRG4 *((volatile uint8_t *)(0x42484B04UL)) +#define bFM_MFT_PPG_GATEC4_EDGE6 *((volatile uint8_t *)(0x42484B10UL)) +#define bFM4_MFT_PPG_GATEC4_EDGE6 *((volatile uint8_t *)(0x42484B10UL)) +#define bFM_MFT_PPG_GATEC4_STRG6 *((volatile uint8_t *)(0x42484B14UL)) +#define bFM4_MFT_PPG_GATEC4_STRG6 *((volatile uint8_t *)(0x42484B14UL)) + +#define bFM_MFT_PPG_GATEC8_EDGE8 *((volatile uint8_t *)(0x42485300UL)) +#define bFM4_MFT_PPG_GATEC8_EDGE8 *((volatile uint8_t *)(0x42485300UL)) +#define bFM_MFT_PPG_GATEC8_STRG8 *((volatile uint8_t *)(0x42485304UL)) +#define bFM4_MFT_PPG_GATEC8_STRG8 *((volatile uint8_t *)(0x42485304UL)) +#define bFM_MFT_PPG_GATEC8_EDGE10 *((volatile uint8_t *)(0x42485310UL)) +#define bFM4_MFT_PPG_GATEC8_EDGE10 *((volatile uint8_t *)(0x42485310UL)) +#define bFM_MFT_PPG_GATEC8_STRG10 *((volatile uint8_t *)(0x42485314UL)) +#define bFM4_MFT_PPG_GATEC8_STRG10 *((volatile uint8_t *)(0x42485314UL)) + +#define bFM_MFT_PPG_PPGC0_TTRG *((volatile uint8_t *)(0x42484020UL)) +#define bFM4_MFT_PPG_PPGC0_TTRG *((volatile uint8_t *)(0x42484020UL)) +#define bFM_MFT_PPG_PPGC0_INTM *((volatile uint8_t *)(0x42484034UL)) +#define bFM4_MFT_PPG_PPGC0_INTM *((volatile uint8_t *)(0x42484034UL)) +#define bFM_MFT_PPG_PPGC0_PUF *((volatile uint8_t *)(0x42484038UL)) +#define bFM4_MFT_PPG_PPGC0_PUF *((volatile uint8_t *)(0x42484038UL)) +#define bFM_MFT_PPG_PPGC0_PIE *((volatile uint8_t *)(0x4248403CUL)) +#define bFM4_MFT_PPG_PPGC0_PIE *((volatile uint8_t *)(0x4248403CUL)) + +#define bFM_MFT_PPG_PPGC1_INTM *((volatile uint8_t *)(0x42484014UL)) +#define bFM4_MFT_PPG_PPGC1_INTM *((volatile uint8_t *)(0x42484014UL)) +#define bFM_MFT_PPG_PPGC1_PUF *((volatile uint8_t *)(0x42484018UL)) +#define bFM4_MFT_PPG_PPGC1_PUF *((volatile uint8_t *)(0x42484018UL)) +#define bFM_MFT_PPG_PPGC1_PIE *((volatile uint8_t *)(0x4248401CUL)) +#define bFM4_MFT_PPG_PPGC1_PIE *((volatile uint8_t *)(0x4248401CUL)) + +#define bFM_MFT_PPG_PPGC10_TTRG *((volatile uint8_t *)(0x424850A0UL)) +#define bFM4_MFT_PPG_PPGC10_TTRG *((volatile uint8_t *)(0x424850A0UL)) +#define bFM_MFT_PPG_PPGC10_INTM *((volatile uint8_t *)(0x424850B4UL)) +#define bFM4_MFT_PPG_PPGC10_INTM *((volatile uint8_t *)(0x424850B4UL)) +#define bFM_MFT_PPG_PPGC10_PUF *((volatile uint8_t *)(0x424850B8UL)) +#define bFM4_MFT_PPG_PPGC10_PUF *((volatile uint8_t *)(0x424850B8UL)) +#define bFM_MFT_PPG_PPGC10_PIE *((volatile uint8_t *)(0x424850BCUL)) +#define bFM4_MFT_PPG_PPGC10_PIE *((volatile uint8_t *)(0x424850BCUL)) + +#define bFM_MFT_PPG_PPGC11_INTM *((volatile uint8_t *)(0x42485094UL)) +#define bFM4_MFT_PPG_PPGC11_INTM *((volatile uint8_t *)(0x42485094UL)) +#define bFM_MFT_PPG_PPGC11_PUF *((volatile uint8_t *)(0x42485098UL)) +#define bFM4_MFT_PPG_PPGC11_PUF *((volatile uint8_t *)(0x42485098UL)) +#define bFM_MFT_PPG_PPGC11_PIE *((volatile uint8_t *)(0x4248509CUL)) +#define bFM4_MFT_PPG_PPGC11_PIE *((volatile uint8_t *)(0x4248509CUL)) + +#define bFM_MFT_PPG_PPGC12_TTRG *((volatile uint8_t *)(0x42485820UL)) +#define bFM4_MFT_PPG_PPGC12_TTRG *((volatile uint8_t *)(0x42485820UL)) +#define bFM_MFT_PPG_PPGC12_INTM *((volatile uint8_t *)(0x42485834UL)) +#define bFM4_MFT_PPG_PPGC12_INTM *((volatile uint8_t *)(0x42485834UL)) +#define bFM_MFT_PPG_PPGC12_PUF *((volatile uint8_t *)(0x42485838UL)) +#define bFM4_MFT_PPG_PPGC12_PUF *((volatile uint8_t *)(0x42485838UL)) +#define bFM_MFT_PPG_PPGC12_PIE *((volatile uint8_t *)(0x4248583CUL)) +#define bFM4_MFT_PPG_PPGC12_PIE *((volatile uint8_t *)(0x4248583CUL)) + +#define bFM_MFT_PPG_PPGC13_INTM *((volatile uint8_t *)(0x42485814UL)) +#define bFM4_MFT_PPG_PPGC13_INTM *((volatile uint8_t *)(0x42485814UL)) +#define bFM_MFT_PPG_PPGC13_PUF *((volatile uint8_t *)(0x42485818UL)) +#define bFM4_MFT_PPG_PPGC13_PUF *((volatile uint8_t *)(0x42485818UL)) +#define bFM_MFT_PPG_PPGC13_PIE *((volatile uint8_t *)(0x4248581CUL)) +#define bFM4_MFT_PPG_PPGC13_PIE *((volatile uint8_t *)(0x4248581CUL)) + +#define bFM_MFT_PPG_PPGC14_TTRG *((volatile uint8_t *)(0x424858A0UL)) +#define bFM4_MFT_PPG_PPGC14_TTRG *((volatile uint8_t *)(0x424858A0UL)) +#define bFM_MFT_PPG_PPGC14_INTM *((volatile uint8_t *)(0x424858B4UL)) +#define bFM4_MFT_PPG_PPGC14_INTM *((volatile uint8_t *)(0x424858B4UL)) +#define bFM_MFT_PPG_PPGC14_PUF *((volatile uint8_t *)(0x424858B8UL)) +#define bFM4_MFT_PPG_PPGC14_PUF *((volatile uint8_t *)(0x424858B8UL)) +#define bFM_MFT_PPG_PPGC14_PIE *((volatile uint8_t *)(0x424858BCUL)) +#define bFM4_MFT_PPG_PPGC14_PIE *((volatile uint8_t *)(0x424858BCUL)) + +#define bFM_MFT_PPG_PPGC15_INTM *((volatile uint8_t *)(0x42485894UL)) +#define bFM4_MFT_PPG_PPGC15_INTM *((volatile uint8_t *)(0x42485894UL)) +#define bFM_MFT_PPG_PPGC15_PUF *((volatile uint8_t *)(0x42485898UL)) +#define bFM4_MFT_PPG_PPGC15_PUF *((volatile uint8_t *)(0x42485898UL)) +#define bFM_MFT_PPG_PPGC15_PIE *((volatile uint8_t *)(0x4248589CUL)) +#define bFM4_MFT_PPG_PPGC15_PIE *((volatile uint8_t *)(0x4248589CUL)) + +#define bFM_MFT_PPG_PPGC16_TTRG *((volatile uint8_t *)(0x42486020UL)) +#define bFM4_MFT_PPG_PPGC16_TTRG *((volatile uint8_t *)(0x42486020UL)) +#define bFM_MFT_PPG_PPGC16_INTM *((volatile uint8_t *)(0x42486034UL)) +#define bFM4_MFT_PPG_PPGC16_INTM *((volatile uint8_t *)(0x42486034UL)) +#define bFM_MFT_PPG_PPGC16_PUF *((volatile uint8_t *)(0x42486038UL)) +#define bFM4_MFT_PPG_PPGC16_PUF *((volatile uint8_t *)(0x42486038UL)) +#define bFM_MFT_PPG_PPGC16_PIE *((volatile uint8_t *)(0x4248603CUL)) +#define bFM4_MFT_PPG_PPGC16_PIE *((volatile uint8_t *)(0x4248603CUL)) + +#define bFM_MFT_PPG_PPGC17_INTM *((volatile uint8_t *)(0x42486014UL)) +#define bFM4_MFT_PPG_PPGC17_INTM *((volatile uint8_t *)(0x42486014UL)) +#define bFM_MFT_PPG_PPGC17_PUF *((volatile uint8_t *)(0x42486018UL)) +#define bFM4_MFT_PPG_PPGC17_PUF *((volatile uint8_t *)(0x42486018UL)) +#define bFM_MFT_PPG_PPGC17_PIE *((volatile uint8_t *)(0x4248601CUL)) +#define bFM4_MFT_PPG_PPGC17_PIE *((volatile uint8_t *)(0x4248601CUL)) + +#define bFM_MFT_PPG_PPGC18_TTRG *((volatile uint8_t *)(0x424860A0UL)) +#define bFM4_MFT_PPG_PPGC18_TTRG *((volatile uint8_t *)(0x424860A0UL)) +#define bFM_MFT_PPG_PPGC18_INTM *((volatile uint8_t *)(0x424860B4UL)) +#define bFM4_MFT_PPG_PPGC18_INTM *((volatile uint8_t *)(0x424860B4UL)) +#define bFM_MFT_PPG_PPGC18_PUF *((volatile uint8_t *)(0x424860B8UL)) +#define bFM4_MFT_PPG_PPGC18_PUF *((volatile uint8_t *)(0x424860B8UL)) +#define bFM_MFT_PPG_PPGC18_PIE *((volatile uint8_t *)(0x424860BCUL)) +#define bFM4_MFT_PPG_PPGC18_PIE *((volatile uint8_t *)(0x424860BCUL)) + +#define bFM_MFT_PPG_PPGC19_INTM *((volatile uint8_t *)(0x42486094UL)) +#define bFM4_MFT_PPG_PPGC19_INTM *((volatile uint8_t *)(0x42486094UL)) +#define bFM_MFT_PPG_PPGC19_PUF *((volatile uint8_t *)(0x42486098UL)) +#define bFM4_MFT_PPG_PPGC19_PUF *((volatile uint8_t *)(0x42486098UL)) +#define bFM_MFT_PPG_PPGC19_PIE *((volatile uint8_t *)(0x4248609CUL)) +#define bFM4_MFT_PPG_PPGC19_PIE *((volatile uint8_t *)(0x4248609CUL)) + +#define bFM_MFT_PPG_PPGC2_TTRG *((volatile uint8_t *)(0x424840A0UL)) +#define bFM4_MFT_PPG_PPGC2_TTRG *((volatile uint8_t *)(0x424840A0UL)) +#define bFM_MFT_PPG_PPGC2_INTM *((volatile uint8_t *)(0x424840B4UL)) +#define bFM4_MFT_PPG_PPGC2_INTM *((volatile uint8_t *)(0x424840B4UL)) +#define bFM_MFT_PPG_PPGC2_PUF *((volatile uint8_t *)(0x424840B8UL)) +#define bFM4_MFT_PPG_PPGC2_PUF *((volatile uint8_t *)(0x424840B8UL)) +#define bFM_MFT_PPG_PPGC2_PIE *((volatile uint8_t *)(0x424840BCUL)) +#define bFM4_MFT_PPG_PPGC2_PIE *((volatile uint8_t *)(0x424840BCUL)) + +#define bFM_MFT_PPG_PPGC20_TTRG *((volatile uint8_t *)(0x42486820UL)) +#define bFM4_MFT_PPG_PPGC20_TTRG *((volatile uint8_t *)(0x42486820UL)) +#define bFM_MFT_PPG_PPGC20_INTM *((volatile uint8_t *)(0x42486834UL)) +#define bFM4_MFT_PPG_PPGC20_INTM *((volatile uint8_t *)(0x42486834UL)) +#define bFM_MFT_PPG_PPGC20_PUF *((volatile uint8_t *)(0x42486838UL)) +#define bFM4_MFT_PPG_PPGC20_PUF *((volatile uint8_t *)(0x42486838UL)) +#define bFM_MFT_PPG_PPGC20_PIE *((volatile uint8_t *)(0x4248683CUL)) +#define bFM4_MFT_PPG_PPGC20_PIE *((volatile uint8_t *)(0x4248683CUL)) + +#define bFM_MFT_PPG_PPGC21_INTM *((volatile uint8_t *)(0x42486814UL)) +#define bFM4_MFT_PPG_PPGC21_INTM *((volatile uint8_t *)(0x42486814UL)) +#define bFM_MFT_PPG_PPGC21_PUF *((volatile uint8_t *)(0x42486818UL)) +#define bFM4_MFT_PPG_PPGC21_PUF *((volatile uint8_t *)(0x42486818UL)) +#define bFM_MFT_PPG_PPGC21_PIE *((volatile uint8_t *)(0x4248681CUL)) +#define bFM4_MFT_PPG_PPGC21_PIE *((volatile uint8_t *)(0x4248681CUL)) + +#define bFM_MFT_PPG_PPGC22_TTRG *((volatile uint8_t *)(0x424868A0UL)) +#define bFM4_MFT_PPG_PPGC22_TTRG *((volatile uint8_t *)(0x424868A0UL)) +#define bFM_MFT_PPG_PPGC22_INTM *((volatile uint8_t *)(0x424868B4UL)) +#define bFM4_MFT_PPG_PPGC22_INTM *((volatile uint8_t *)(0x424868B4UL)) +#define bFM_MFT_PPG_PPGC22_PUF *((volatile uint8_t *)(0x424868B8UL)) +#define bFM4_MFT_PPG_PPGC22_PUF *((volatile uint8_t *)(0x424868B8UL)) +#define bFM_MFT_PPG_PPGC22_PIE *((volatile uint8_t *)(0x424868BCUL)) +#define bFM4_MFT_PPG_PPGC22_PIE *((volatile uint8_t *)(0x424868BCUL)) + +#define bFM_MFT_PPG_PPGC23_INTM *((volatile uint8_t *)(0x42486894UL)) +#define bFM4_MFT_PPG_PPGC23_INTM *((volatile uint8_t *)(0x42486894UL)) +#define bFM_MFT_PPG_PPGC23_PUF *((volatile uint8_t *)(0x42486898UL)) +#define bFM4_MFT_PPG_PPGC23_PUF *((volatile uint8_t *)(0x42486898UL)) +#define bFM_MFT_PPG_PPGC23_PIE *((volatile uint8_t *)(0x4248689CUL)) +#define bFM4_MFT_PPG_PPGC23_PIE *((volatile uint8_t *)(0x4248689CUL)) + +#define bFM_MFT_PPG_PPGC3_INTM *((volatile uint8_t *)(0x42484094UL)) +#define bFM4_MFT_PPG_PPGC3_INTM *((volatile uint8_t *)(0x42484094UL)) +#define bFM_MFT_PPG_PPGC3_PUF *((volatile uint8_t *)(0x42484098UL)) +#define bFM4_MFT_PPG_PPGC3_PUF *((volatile uint8_t *)(0x42484098UL)) +#define bFM_MFT_PPG_PPGC3_PIE *((volatile uint8_t *)(0x4248409CUL)) +#define bFM4_MFT_PPG_PPGC3_PIE *((volatile uint8_t *)(0x4248409CUL)) + +#define bFM_MFT_PPG_PPGC4_TTRG *((volatile uint8_t *)(0x42484820UL)) +#define bFM4_MFT_PPG_PPGC4_TTRG *((volatile uint8_t *)(0x42484820UL)) +#define bFM_MFT_PPG_PPGC4_INTM *((volatile uint8_t *)(0x42484834UL)) +#define bFM4_MFT_PPG_PPGC4_INTM *((volatile uint8_t *)(0x42484834UL)) +#define bFM_MFT_PPG_PPGC4_PUF *((volatile uint8_t *)(0x42484838UL)) +#define bFM4_MFT_PPG_PPGC4_PUF *((volatile uint8_t *)(0x42484838UL)) +#define bFM_MFT_PPG_PPGC4_PIE *((volatile uint8_t *)(0x4248483CUL)) +#define bFM4_MFT_PPG_PPGC4_PIE *((volatile uint8_t *)(0x4248483CUL)) + +#define bFM_MFT_PPG_PPGC5_INTM *((volatile uint8_t *)(0x42484814UL)) +#define bFM4_MFT_PPG_PPGC5_INTM *((volatile uint8_t *)(0x42484814UL)) +#define bFM_MFT_PPG_PPGC5_PUF *((volatile uint8_t *)(0x42484818UL)) +#define bFM4_MFT_PPG_PPGC5_PUF *((volatile uint8_t *)(0x42484818UL)) +#define bFM_MFT_PPG_PPGC5_PIE *((volatile uint8_t *)(0x4248481CUL)) +#define bFM4_MFT_PPG_PPGC5_PIE *((volatile uint8_t *)(0x4248481CUL)) + +#define bFM_MFT_PPG_PPGC6_TTRG *((volatile uint8_t *)(0x424848A0UL)) +#define bFM4_MFT_PPG_PPGC6_TTRG *((volatile uint8_t *)(0x424848A0UL)) +#define bFM_MFT_PPG_PPGC6_INTM *((volatile uint8_t *)(0x424848B4UL)) +#define bFM4_MFT_PPG_PPGC6_INTM *((volatile uint8_t *)(0x424848B4UL)) +#define bFM_MFT_PPG_PPGC6_PUF *((volatile uint8_t *)(0x424848B8UL)) +#define bFM4_MFT_PPG_PPGC6_PUF *((volatile uint8_t *)(0x424848B8UL)) +#define bFM_MFT_PPG_PPGC6_PIE *((volatile uint8_t *)(0x424848BCUL)) +#define bFM4_MFT_PPG_PPGC6_PIE *((volatile uint8_t *)(0x424848BCUL)) + +#define bFM_MFT_PPG_PPGC7_INTM *((volatile uint8_t *)(0x42484894UL)) +#define bFM4_MFT_PPG_PPGC7_INTM *((volatile uint8_t *)(0x42484894UL)) +#define bFM_MFT_PPG_PPGC7_PUF *((volatile uint8_t *)(0x42484898UL)) +#define bFM4_MFT_PPG_PPGC7_PUF *((volatile uint8_t *)(0x42484898UL)) +#define bFM_MFT_PPG_PPGC7_PIE *((volatile uint8_t *)(0x4248489CUL)) +#define bFM4_MFT_PPG_PPGC7_PIE *((volatile uint8_t *)(0x4248489CUL)) + +#define bFM_MFT_PPG_PPGC8_TTRG *((volatile uint8_t *)(0x42485020UL)) +#define bFM4_MFT_PPG_PPGC8_TTRG *((volatile uint8_t *)(0x42485020UL)) +#define bFM_MFT_PPG_PPGC8_INTM *((volatile uint8_t *)(0x42485034UL)) +#define bFM4_MFT_PPG_PPGC8_INTM *((volatile uint8_t *)(0x42485034UL)) +#define bFM_MFT_PPG_PPGC8_PUF *((volatile uint8_t *)(0x42485038UL)) +#define bFM4_MFT_PPG_PPGC8_PUF *((volatile uint8_t *)(0x42485038UL)) +#define bFM_MFT_PPG_PPGC8_PIE *((volatile uint8_t *)(0x4248503CUL)) +#define bFM4_MFT_PPG_PPGC8_PIE *((volatile uint8_t *)(0x4248503CUL)) + +#define bFM_MFT_PPG_PPGC9_INTM *((volatile uint8_t *)(0x42485014UL)) +#define bFM4_MFT_PPG_PPGC9_INTM *((volatile uint8_t *)(0x42485014UL)) +#define bFM_MFT_PPG_PPGC9_PUF *((volatile uint8_t *)(0x42485018UL)) +#define bFM4_MFT_PPG_PPGC9_PUF *((volatile uint8_t *)(0x42485018UL)) +#define bFM_MFT_PPG_PPGC9_PIE *((volatile uint8_t *)(0x4248501CUL)) +#define bFM4_MFT_PPG_PPGC9_PIE *((volatile uint8_t *)(0x4248501CUL)) + +#define bFM_MFT_PPG_REVC0_REV00 *((volatile uint8_t *)(0x42482080UL)) +#define bFM4_MFT_PPG_REVC0_REV00 *((volatile uint8_t *)(0x42482080UL)) +#define bFM_MFT_PPG_REVC0_REV01 *((volatile uint8_t *)(0x42482084UL)) +#define bFM4_MFT_PPG_REVC0_REV01 *((volatile uint8_t *)(0x42482084UL)) +#define bFM_MFT_PPG_REVC0_REV02 *((volatile uint8_t *)(0x42482088UL)) +#define bFM4_MFT_PPG_REVC0_REV02 *((volatile uint8_t *)(0x42482088UL)) +#define bFM_MFT_PPG_REVC0_REV03 *((volatile uint8_t *)(0x4248208CUL)) +#define bFM4_MFT_PPG_REVC0_REV03 *((volatile uint8_t *)(0x4248208CUL)) +#define bFM_MFT_PPG_REVC0_REV04 *((volatile uint8_t *)(0x42482090UL)) +#define bFM4_MFT_PPG_REVC0_REV04 *((volatile uint8_t *)(0x42482090UL)) +#define bFM_MFT_PPG_REVC0_REV05 *((volatile uint8_t *)(0x42482094UL)) +#define bFM4_MFT_PPG_REVC0_REV05 *((volatile uint8_t *)(0x42482094UL)) +#define bFM_MFT_PPG_REVC0_REV06 *((volatile uint8_t *)(0x42482098UL)) +#define bFM4_MFT_PPG_REVC0_REV06 *((volatile uint8_t *)(0x42482098UL)) +#define bFM_MFT_PPG_REVC0_REV07 *((volatile uint8_t *)(0x4248209CUL)) +#define bFM4_MFT_PPG_REVC0_REV07 *((volatile uint8_t *)(0x4248209CUL)) +#define bFM_MFT_PPG_REVC0_REV08 *((volatile uint8_t *)(0x424820A0UL)) +#define bFM4_MFT_PPG_REVC0_REV08 *((volatile uint8_t *)(0x424820A0UL)) +#define bFM_MFT_PPG_REVC0_REV09 *((volatile uint8_t *)(0x424820A4UL)) +#define bFM4_MFT_PPG_REVC0_REV09 *((volatile uint8_t *)(0x424820A4UL)) +#define bFM_MFT_PPG_REVC0_REV10 *((volatile uint8_t *)(0x424820A8UL)) +#define bFM4_MFT_PPG_REVC0_REV10 *((volatile uint8_t *)(0x424820A8UL)) +#define bFM_MFT_PPG_REVC0_REV11 *((volatile uint8_t *)(0x424820ACUL)) +#define bFM4_MFT_PPG_REVC0_REV11 *((volatile uint8_t *)(0x424820ACUL)) +#define bFM_MFT_PPG_REVC0_REV12 *((volatile uint8_t *)(0x424820B0UL)) +#define bFM4_MFT_PPG_REVC0_REV12 *((volatile uint8_t *)(0x424820B0UL)) +#define bFM_MFT_PPG_REVC0_REV13 *((volatile uint8_t *)(0x424820B4UL)) +#define bFM4_MFT_PPG_REVC0_REV13 *((volatile uint8_t *)(0x424820B4UL)) +#define bFM_MFT_PPG_REVC0_REV14 *((volatile uint8_t *)(0x424820B8UL)) +#define bFM4_MFT_PPG_REVC0_REV14 *((volatile uint8_t *)(0x424820B8UL)) +#define bFM_MFT_PPG_REVC0_REV15 *((volatile uint8_t *)(0x424820BCUL)) +#define bFM4_MFT_PPG_REVC0_REV15 *((volatile uint8_t *)(0x424820BCUL)) + +#define bFM_MFT_PPG_REVC1_REV16 *((volatile uint8_t *)(0x42482880UL)) +#define bFM4_MFT_PPG_REVC1_REV16 *((volatile uint8_t *)(0x42482880UL)) +#define bFM_MFT_PPG_REVC1_REV17 *((volatile uint8_t *)(0x42482884UL)) +#define bFM4_MFT_PPG_REVC1_REV17 *((volatile uint8_t *)(0x42482884UL)) +#define bFM_MFT_PPG_REVC1_REV18 *((volatile uint8_t *)(0x42482888UL)) +#define bFM4_MFT_PPG_REVC1_REV18 *((volatile uint8_t *)(0x42482888UL)) +#define bFM_MFT_PPG_REVC1_REV19 *((volatile uint8_t *)(0x4248288CUL)) +#define bFM4_MFT_PPG_REVC1_REV19 *((volatile uint8_t *)(0x4248288CUL)) +#define bFM_MFT_PPG_REVC1_REV20 *((volatile uint8_t *)(0x42482890UL)) +#define bFM4_MFT_PPG_REVC1_REV20 *((volatile uint8_t *)(0x42482890UL)) +#define bFM_MFT_PPG_REVC1_REV21 *((volatile uint8_t *)(0x42482894UL)) +#define bFM4_MFT_PPG_REVC1_REV21 *((volatile uint8_t *)(0x42482894UL)) +#define bFM_MFT_PPG_REVC1_REV22 *((volatile uint8_t *)(0x42482898UL)) +#define bFM4_MFT_PPG_REVC1_REV22 *((volatile uint8_t *)(0x42482898UL)) +#define bFM_MFT_PPG_REVC1_REV23 *((volatile uint8_t *)(0x4248289CUL)) +#define bFM4_MFT_PPG_REVC1_REV23 *((volatile uint8_t *)(0x4248289CUL)) + +#define bFM_MFT_PPG_TRG0_PEN00 *((volatile uint8_t *)(0x42482000UL)) +#define bFM4_MFT_PPG_TRG0_PEN00 *((volatile uint8_t *)(0x42482000UL)) +#define bFM_MFT_PPG_TRG0_PEN01 *((volatile uint8_t *)(0x42482004UL)) +#define bFM4_MFT_PPG_TRG0_PEN01 *((volatile uint8_t *)(0x42482004UL)) +#define bFM_MFT_PPG_TRG0_PEN02 *((volatile uint8_t *)(0x42482008UL)) +#define bFM4_MFT_PPG_TRG0_PEN02 *((volatile uint8_t *)(0x42482008UL)) +#define bFM_MFT_PPG_TRG0_PEN03 *((volatile uint8_t *)(0x4248200CUL)) +#define bFM4_MFT_PPG_TRG0_PEN03 *((volatile uint8_t *)(0x4248200CUL)) +#define bFM_MFT_PPG_TRG0_PEN04 *((volatile uint8_t *)(0x42482010UL)) +#define bFM4_MFT_PPG_TRG0_PEN04 *((volatile uint8_t *)(0x42482010UL)) +#define bFM_MFT_PPG_TRG0_PEN05 *((volatile uint8_t *)(0x42482014UL)) +#define bFM4_MFT_PPG_TRG0_PEN05 *((volatile uint8_t *)(0x42482014UL)) +#define bFM_MFT_PPG_TRG0_PEN06 *((volatile uint8_t *)(0x42482018UL)) +#define bFM4_MFT_PPG_TRG0_PEN06 *((volatile uint8_t *)(0x42482018UL)) +#define bFM_MFT_PPG_TRG0_PEN07 *((volatile uint8_t *)(0x4248201CUL)) +#define bFM4_MFT_PPG_TRG0_PEN07 *((volatile uint8_t *)(0x4248201CUL)) +#define bFM_MFT_PPG_TRG0_PEN08 *((volatile uint8_t *)(0x42482020UL)) +#define bFM4_MFT_PPG_TRG0_PEN08 *((volatile uint8_t *)(0x42482020UL)) +#define bFM_MFT_PPG_TRG0_PEN09 *((volatile uint8_t *)(0x42482024UL)) +#define bFM4_MFT_PPG_TRG0_PEN09 *((volatile uint8_t *)(0x42482024UL)) +#define bFM_MFT_PPG_TRG0_PEN10 *((volatile uint8_t *)(0x42482028UL)) +#define bFM4_MFT_PPG_TRG0_PEN10 *((volatile uint8_t *)(0x42482028UL)) +#define bFM_MFT_PPG_TRG0_PEN11 *((volatile uint8_t *)(0x4248202CUL)) +#define bFM4_MFT_PPG_TRG0_PEN11 *((volatile uint8_t *)(0x4248202CUL)) +#define bFM_MFT_PPG_TRG0_PEN12 *((volatile uint8_t *)(0x42482030UL)) +#define bFM4_MFT_PPG_TRG0_PEN12 *((volatile uint8_t *)(0x42482030UL)) +#define bFM_MFT_PPG_TRG0_PEN13 *((volatile uint8_t *)(0x42482034UL)) +#define bFM4_MFT_PPG_TRG0_PEN13 *((volatile uint8_t *)(0x42482034UL)) +#define bFM_MFT_PPG_TRG0_PEN14 *((volatile uint8_t *)(0x42482038UL)) +#define bFM4_MFT_PPG_TRG0_PEN14 *((volatile uint8_t *)(0x42482038UL)) +#define bFM_MFT_PPG_TRG0_PEN15 *((volatile uint8_t *)(0x4248203CUL)) +#define bFM4_MFT_PPG_TRG0_PEN15 *((volatile uint8_t *)(0x4248203CUL)) + +#define bFM_MFT_PPG_TRG1_PEN16 *((volatile uint8_t *)(0x42482800UL)) +#define bFM4_MFT_PPG_TRG1_PEN16 *((volatile uint8_t *)(0x42482800UL)) +#define bFM_MFT_PPG_TRG1_PEN17 *((volatile uint8_t *)(0x42482804UL)) +#define bFM4_MFT_PPG_TRG1_PEN17 *((volatile uint8_t *)(0x42482804UL)) +#define bFM_MFT_PPG_TRG1_PEN18 *((volatile uint8_t *)(0x42482808UL)) +#define bFM4_MFT_PPG_TRG1_PEN18 *((volatile uint8_t *)(0x42482808UL)) +#define bFM_MFT_PPG_TRG1_PEN19 *((volatile uint8_t *)(0x4248280CUL)) +#define bFM4_MFT_PPG_TRG1_PEN19 *((volatile uint8_t *)(0x4248280CUL)) +#define bFM_MFT_PPG_TRG1_PEN20 *((volatile uint8_t *)(0x42482810UL)) +#define bFM4_MFT_PPG_TRG1_PEN20 *((volatile uint8_t *)(0x42482810UL)) +#define bFM_MFT_PPG_TRG1_PEN21 *((volatile uint8_t *)(0x42482814UL)) +#define bFM4_MFT_PPG_TRG1_PEN21 *((volatile uint8_t *)(0x42482814UL)) +#define bFM_MFT_PPG_TRG1_PEN22 *((volatile uint8_t *)(0x42482818UL)) +#define bFM4_MFT_PPG_TRG1_PEN22 *((volatile uint8_t *)(0x42482818UL)) +#define bFM_MFT_PPG_TRG1_PEN23 *((volatile uint8_t *)(0x4248281CUL)) +#define bFM4_MFT_PPG_TRG1_PEN23 *((volatile uint8_t *)(0x4248281CUL)) + +#define bFM_MFT_PPG_TTCR0_STR0 *((volatile uint8_t *)(0x42480020UL)) +#define bFM4_MFT_PPG_TTCR0_STR0 *((volatile uint8_t *)(0x42480020UL)) +#define bFM_MFT_PPG_TTCR0_MONI0 *((volatile uint8_t *)(0x42480024UL)) +#define bFM4_MFT_PPG_TTCR0_MONI0 *((volatile uint8_t *)(0x42480024UL)) +#define bFM_MFT_PPG_TTCR0_TRG0O *((volatile uint8_t *)(0x42480030UL)) +#define bFM4_MFT_PPG_TTCR0_TRG0O *((volatile uint8_t *)(0x42480030UL)) +#define bFM_MFT_PPG_TTCR0_TRG2O *((volatile uint8_t *)(0x42480034UL)) +#define bFM4_MFT_PPG_TTCR0_TRG2O *((volatile uint8_t *)(0x42480034UL)) +#define bFM_MFT_PPG_TTCR0_TRG4O *((volatile uint8_t *)(0x42480038UL)) +#define bFM4_MFT_PPG_TTCR0_TRG4O *((volatile uint8_t *)(0x42480038UL)) +#define bFM_MFT_PPG_TTCR0_TRG6O *((volatile uint8_t *)(0x4248003CUL)) +#define bFM4_MFT_PPG_TTCR0_TRG6O *((volatile uint8_t *)(0x4248003CUL)) + +#define bFM_MFT_PPG_TTCR1_STR1 *((volatile uint8_t *)(0x42480420UL)) +#define bFM4_MFT_PPG_TTCR1_STR1 *((volatile uint8_t *)(0x42480420UL)) +#define bFM_MFT_PPG_TTCR1_MONI1 *((volatile uint8_t *)(0x42480424UL)) +#define bFM4_MFT_PPG_TTCR1_MONI1 *((volatile uint8_t *)(0x42480424UL)) +#define bFM_MFT_PPG_TTCR1_TRG1O *((volatile uint8_t *)(0x42480430UL)) +#define bFM4_MFT_PPG_TTCR1_TRG1O *((volatile uint8_t *)(0x42480430UL)) +#define bFM_MFT_PPG_TTCR1_TRG3O *((volatile uint8_t *)(0x42480434UL)) +#define bFM4_MFT_PPG_TTCR1_TRG3O *((volatile uint8_t *)(0x42480434UL)) +#define bFM_MFT_PPG_TTCR1_TRG5O *((volatile uint8_t *)(0x42480438UL)) +#define bFM4_MFT_PPG_TTCR1_TRG5O *((volatile uint8_t *)(0x42480438UL)) +#define bFM_MFT_PPG_TTCR1_TRG7O *((volatile uint8_t *)(0x4248043CUL)) +#define bFM4_MFT_PPG_TTCR1_TRG7O *((volatile uint8_t *)(0x4248043CUL)) + +#define bFM_MFT_PPG_TTCR2_STR2 *((volatile uint8_t *)(0x42480820UL)) +#define bFM4_MFT_PPG_TTCR2_STR2 *((volatile uint8_t *)(0x42480820UL)) +#define bFM_MFT_PPG_TTCR2_MONI2 *((volatile uint8_t *)(0x42480824UL)) +#define bFM4_MFT_PPG_TTCR2_MONI2 *((volatile uint8_t *)(0x42480824UL)) +#define bFM_MFT_PPG_TTCR2_TRG16O *((volatile uint8_t *)(0x42480830UL)) +#define bFM4_MFT_PPG_TTCR2_TRG16O *((volatile uint8_t *)(0x42480830UL)) +#define bFM_MFT_PPG_TTCR2_TRG18O *((volatile uint8_t *)(0x42480834UL)) +#define bFM4_MFT_PPG_TTCR2_TRG18O *((volatile uint8_t *)(0x42480834UL)) +#define bFM_MFT_PPG_TTCR2_TRG20O *((volatile uint8_t *)(0x42480838UL)) +#define bFM4_MFT_PPG_TTCR2_TRG20O *((volatile uint8_t *)(0x42480838UL)) +#define bFM_MFT_PPG_TTCR2_TRG22O *((volatile uint8_t *)(0x4248083CUL)) +#define bFM4_MFT_PPG_TTCR2_TRG22O *((volatile uint8_t *)(0x4248083CUL)) + + +/******************************************************************************* +* MFT Registers MFT0 +* Bitband Section +*******************************************************************************/ +#define bFM_MFT0_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42403AD8UL)) +#define bFM4_MFT0_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42403AD8UL)) +#define bFM_MFT0_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42403ADCUL)) +#define bFM4_MFT0_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42403ADCUL)) + +#define bFM_MFT0_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42403B58UL)) +#define bFM4_MFT0_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42403B58UL)) +#define bFM_MFT0_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42403B5CUL)) +#define bFM4_MFT0_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42403B5CUL)) + +#define bFM_MFT0_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42403BD8UL)) +#define bFM4_MFT0_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42403BD8UL)) +#define bFM_MFT0_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42403BDCUL)) +#define bFM4_MFT0_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42403BDCUL)) + +#define bFM_MFT0_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42403C58UL)) +#define bFM4_MFT0_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42403C58UL)) +#define bFM_MFT0_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42403C5CUL)) +#define bFM4_MFT0_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42403C5CUL)) + +#define bFM_MFT0_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42403CD8UL)) +#define bFM4_MFT0_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42403CD8UL)) +#define bFM_MFT0_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42403CDCUL)) +#define bFM4_MFT0_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42403CDCUL)) + +#define bFM_MFT0_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42403D58UL)) +#define bFM4_MFT0_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42403D58UL)) +#define bFM_MFT0_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42403D5CUL)) +#define bFM4_MFT0_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42403D5CUL)) + +#define bFM_MFT0_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42403A94UL)) +#define bFM4_MFT0_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42403A94UL)) + +#define bFM_MFT0_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42403B14UL)) +#define bFM4_MFT0_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42403B14UL)) + +#define bFM_MFT0_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42403B94UL)) +#define bFM4_MFT0_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42403B94UL)) + +#define bFM_MFT0_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42403C14UL)) +#define bFM4_MFT0_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42403C14UL)) + +#define bFM_MFT0_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42403C94UL)) +#define bFM4_MFT0_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42403C94UL)) + +#define bFM_MFT0_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42403D14UL)) +#define bFM4_MFT0_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42403D14UL)) + +#define bFM_MFT0_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42403AA0UL)) +#define bFM4_MFT0_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42403AA0UL)) +#define bFM_MFT0_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42403AA4UL)) +#define bFM4_MFT0_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42403AA4UL)) +#define bFM_MFT0_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42403AB0UL)) +#define bFM4_MFT0_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42403AB0UL)) +#define bFM_MFT0_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42403AB4UL)) +#define bFM4_MFT0_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42403AB4UL)) +#define bFM_MFT0_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42403AB8UL)) +#define bFM4_MFT0_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42403AB8UL)) +#define bFM_MFT0_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42403ABCUL)) +#define bFM4_MFT0_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42403ABCUL)) + +#define bFM_MFT0_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42403B20UL)) +#define bFM4_MFT0_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42403B20UL)) +#define bFM_MFT0_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42403B24UL)) +#define bFM4_MFT0_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42403B24UL)) +#define bFM_MFT0_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42403B30UL)) +#define bFM4_MFT0_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42403B30UL)) +#define bFM_MFT0_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42403B34UL)) +#define bFM4_MFT0_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42403B34UL)) +#define bFM_MFT0_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42403B38UL)) +#define bFM4_MFT0_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42403B38UL)) +#define bFM_MFT0_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42403B3CUL)) +#define bFM4_MFT0_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42403B3CUL)) + +#define bFM_MFT0_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42403BA0UL)) +#define bFM4_MFT0_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42403BA0UL)) +#define bFM_MFT0_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42403BA4UL)) +#define bFM4_MFT0_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42403BA4UL)) +#define bFM_MFT0_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42403BB0UL)) +#define bFM4_MFT0_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42403BB0UL)) +#define bFM_MFT0_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42403BB4UL)) +#define bFM4_MFT0_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42403BB4UL)) +#define bFM_MFT0_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42403BB8UL)) +#define bFM4_MFT0_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42403BB8UL)) +#define bFM_MFT0_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42403BBCUL)) +#define bFM4_MFT0_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42403BBCUL)) + +#define bFM_MFT0_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42403C20UL)) +#define bFM4_MFT0_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42403C20UL)) +#define bFM_MFT0_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42403C24UL)) +#define bFM4_MFT0_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42403C24UL)) +#define bFM_MFT0_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42403C30UL)) +#define bFM4_MFT0_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42403C30UL)) +#define bFM_MFT0_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42403C34UL)) +#define bFM4_MFT0_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42403C34UL)) +#define bFM_MFT0_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42403C38UL)) +#define bFM4_MFT0_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42403C38UL)) +#define bFM_MFT0_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42403C3CUL)) +#define bFM4_MFT0_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42403C3CUL)) + +#define bFM_MFT0_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42403CA0UL)) +#define bFM4_MFT0_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42403CA0UL)) +#define bFM_MFT0_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42403CA4UL)) +#define bFM4_MFT0_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42403CA4UL)) +#define bFM_MFT0_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42403CB0UL)) +#define bFM4_MFT0_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42403CB0UL)) +#define bFM_MFT0_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42403CB4UL)) +#define bFM4_MFT0_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42403CB4UL)) +#define bFM_MFT0_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42403CB8UL)) +#define bFM4_MFT0_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42403CB8UL)) +#define bFM_MFT0_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42403CBCUL)) +#define bFM4_MFT0_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42403CBCUL)) + +#define bFM_MFT0_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42403D20UL)) +#define bFM4_MFT0_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42403D20UL)) +#define bFM_MFT0_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42403D24UL)) +#define bFM4_MFT0_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42403D24UL)) +#define bFM_MFT0_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42403D30UL)) +#define bFM4_MFT0_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42403D30UL)) +#define bFM_MFT0_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42403D34UL)) +#define bFM4_MFT0_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42403D34UL)) +#define bFM_MFT0_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42403D38UL)) +#define bFM4_MFT0_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42403D38UL)) +#define bFM_MFT0_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42403D3CUL)) +#define bFM4_MFT0_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42403D3CUL)) + +#define bFM_MFT0_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42402C80UL)) +#define bFM4_MFT0_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42402C80UL)) +#define bFM_MFT0_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42402C84UL)) +#define bFM4_MFT0_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42402C84UL)) +#define bFM_MFT0_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42402C88UL)) +#define bFM4_MFT0_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42402C88UL)) +#define bFM_MFT0_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42402C8CUL)) +#define bFM4_MFT0_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42402C8CUL)) +#define bFM_MFT0_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42402C90UL)) +#define bFM4_MFT0_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42402C90UL)) +#define bFM_MFT0_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42402C94UL)) +#define bFM4_MFT0_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42402C94UL)) +#define bFM_MFT0_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42402C98UL)) +#define bFM4_MFT0_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42402C98UL)) +#define bFM_MFT0_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42402C9CUL)) +#define bFM4_MFT0_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42402C9CUL)) +#define bFM_MFT0_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42402CA0UL)) +#define bFM4_MFT0_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42402CA0UL)) +#define bFM_MFT0_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42402CC0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42402CC0UL)) +#define bFM_MFT0_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42402CC4UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42402CC4UL)) +#define bFM_MFT0_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42402CC8UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42402CC8UL)) +#define bFM_MFT0_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42402CCCUL)) +#define bFM4_MFT0_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42402CCCUL)) +#define bFM_MFT0_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42402CD0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42402CD0UL)) +#define bFM_MFT0_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42402CD4UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42402CD4UL)) +#define bFM_MFT0_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42402CD8UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42402CD8UL)) +#define bFM_MFT0_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42402CDCUL)) +#define bFM4_MFT0_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42402CDCUL)) +#define bFM_MFT0_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42402CE0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42402CE0UL)) + +#define bFM_MFT0_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42402910UL)) +#define bFM4_MFT0_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42402910UL)) +#define bFM_MFT0_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42402914UL)) +#define bFM4_MFT0_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42402914UL)) +#define bFM_MFT0_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42402918UL)) +#define bFM4_MFT0_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42402918UL)) +#define bFM_MFT0_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4240291CUL)) +#define bFM4_MFT0_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4240291CUL)) +#define bFM_MFT0_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42402920UL)) +#define bFM4_MFT0_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42402920UL)) +#define bFM_MFT0_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42402924UL)) +#define bFM4_MFT0_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42402924UL)) +#define bFM_MFT0_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42402934UL)) +#define bFM4_MFT0_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42402934UL)) +#define bFM_MFT0_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42402938UL)) +#define bFM4_MFT0_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42402938UL)) +#define bFM_MFT0_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4240293CUL)) +#define bFM4_MFT0_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4240293CUL)) + +#define bFM_MFT0_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42402A90UL)) +#define bFM4_MFT0_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42402A90UL)) +#define bFM_MFT0_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42402A94UL)) +#define bFM4_MFT0_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42402A94UL)) +#define bFM_MFT0_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42402A98UL)) +#define bFM4_MFT0_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42402A98UL)) +#define bFM_MFT0_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42402A9CUL)) +#define bFM4_MFT0_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42402A9CUL)) +#define bFM_MFT0_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42402AA0UL)) +#define bFM4_MFT0_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42402AA0UL)) +#define bFM_MFT0_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42402AA4UL)) +#define bFM4_MFT0_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42402AA4UL)) +#define bFM_MFT0_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42402AB4UL)) +#define bFM4_MFT0_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42402AB4UL)) +#define bFM_MFT0_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42402AB8UL)) +#define bFM4_MFT0_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42402AB8UL)) +#define bFM_MFT0_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42402ABCUL)) +#define bFM4_MFT0_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42402ABCUL)) + +#define bFM_MFT0_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42402C10UL)) +#define bFM4_MFT0_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42402C10UL)) +#define bFM_MFT0_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42402C14UL)) +#define bFM4_MFT0_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42402C14UL)) +#define bFM_MFT0_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42402C18UL)) +#define bFM4_MFT0_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42402C18UL)) +#define bFM_MFT0_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42402C1CUL)) +#define bFM4_MFT0_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42402C1CUL)) +#define bFM_MFT0_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42402C20UL)) +#define bFM4_MFT0_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42402C20UL)) +#define bFM_MFT0_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42402C24UL)) +#define bFM4_MFT0_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42402C24UL)) +#define bFM_MFT0_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42402C34UL)) +#define bFM4_MFT0_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42402C34UL)) +#define bFM_MFT0_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42402C38UL)) +#define bFM4_MFT0_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42402C38UL)) +#define bFM_MFT0_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42402C3CUL)) +#define bFM4_MFT0_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42402C3CUL)) + +#define bFM_MFT0_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42403D80UL)) +#define bFM4_MFT0_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42403D80UL)) +#define bFM_MFT0_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42403D84UL)) +#define bFM4_MFT0_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42403D84UL)) + +#define bFM_MFT0_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42403090UL)) +#define bFM4_MFT0_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42403090UL)) +#define bFM_MFT0_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42403094UL)) +#define bFM4_MFT0_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42403094UL)) +#define bFM_MFT0_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42403098UL)) +#define bFM4_MFT0_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42403098UL)) +#define bFM_MFT0_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4240309CUL)) +#define bFM4_MFT0_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4240309CUL)) + +#define bFM_MFT0_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42403110UL)) +#define bFM4_MFT0_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42403110UL)) +#define bFM_MFT0_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42403114UL)) +#define bFM4_MFT0_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42403114UL)) +#define bFM_MFT0_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42403118UL)) +#define bFM4_MFT0_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42403118UL)) +#define bFM_MFT0_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4240311CUL)) +#define bFM4_MFT0_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4240311CUL)) + +#define bFM_MFT0_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424030A0UL)) +#define bFM4_MFT0_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424030A0UL)) +#define bFM_MFT0_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424030A4UL)) +#define bFM4_MFT0_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424030A4UL)) + +#define bFM_MFT0_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42403120UL)) +#define bFM4_MFT0_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42403120UL)) +#define bFM_MFT0_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42403124UL)) +#define bFM4_MFT0_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42403124UL)) + +#define bFM_MFT0_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42402300UL)) +#define bFM4_MFT0_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42402300UL)) +#define bFM_MFT0_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42402304UL)) +#define bFM4_MFT0_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42402304UL)) +#define bFM_MFT0_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42402310UL)) +#define bFM4_MFT0_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42402310UL)) +#define bFM_MFT0_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42402314UL)) +#define bFM4_MFT0_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42402314UL)) +#define bFM_MFT0_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42402318UL)) +#define bFM4_MFT0_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42402318UL)) +#define bFM_MFT0_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4240231CUL)) +#define bFM4_MFT0_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4240231CUL)) + +#define bFM_MFT0_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42402380UL)) +#define bFM4_MFT0_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42402380UL)) +#define bFM_MFT0_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42402384UL)) +#define bFM4_MFT0_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42402384UL)) +#define bFM_MFT0_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42402390UL)) +#define bFM4_MFT0_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42402390UL)) +#define bFM_MFT0_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42402394UL)) +#define bFM4_MFT0_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42402394UL)) +#define bFM_MFT0_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42402398UL)) +#define bFM4_MFT0_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42402398UL)) +#define bFM_MFT0_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4240239CUL)) +#define bFM4_MFT0_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4240239CUL)) + +#define bFM_MFT0_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42402400UL)) +#define bFM4_MFT0_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42402400UL)) +#define bFM_MFT0_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42402404UL)) +#define bFM4_MFT0_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42402404UL)) +#define bFM_MFT0_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42402410UL)) +#define bFM4_MFT0_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42402410UL)) +#define bFM_MFT0_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42402414UL)) +#define bFM4_MFT0_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42402414UL)) +#define bFM_MFT0_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42402418UL)) +#define bFM4_MFT0_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42402418UL)) +#define bFM_MFT0_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4240241CUL)) +#define bFM4_MFT0_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4240241CUL)) + +#define bFM_MFT0_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42402320UL)) +#define bFM4_MFT0_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42402320UL)) +#define bFM_MFT0_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42402324UL)) +#define bFM4_MFT0_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42402324UL)) +#define bFM_MFT0_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42402330UL)) +#define bFM4_MFT0_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42402330UL)) +#define bFM_MFT0_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4240233CUL)) +#define bFM4_MFT0_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4240233CUL)) + +#define bFM_MFT0_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424023A0UL)) +#define bFM4_MFT0_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424023A0UL)) +#define bFM_MFT0_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424023A4UL)) +#define bFM4_MFT0_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424023A4UL)) +#define bFM_MFT0_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424023B0UL)) +#define bFM4_MFT0_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424023B0UL)) +#define bFM_MFT0_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424023BCUL)) +#define bFM4_MFT0_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424023BCUL)) + +#define bFM_MFT0_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42402420UL)) +#define bFM4_MFT0_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42402420UL)) +#define bFM_MFT0_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42402424UL)) +#define bFM4_MFT0_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42402424UL)) +#define bFM_MFT0_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42402430UL)) +#define bFM4_MFT0_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42402430UL)) +#define bFM_MFT0_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4240243CUL)) +#define bFM4_MFT0_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4240243CUL)) + +#define bFM_MFT0_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424024A0UL)) +#define bFM4_MFT0_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424024A0UL)) +#define bFM_MFT0_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424024A4UL)) +#define bFM4_MFT0_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424024A4UL)) +#define bFM_MFT0_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424024A8UL)) +#define bFM4_MFT0_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424024A8UL)) +#define bFM_MFT0_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424024ACUL)) +#define bFM4_MFT0_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424024ACUL)) +#define bFM_MFT0_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424024B0UL)) +#define bFM4_MFT0_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424024B0UL)) +#define bFM_MFT0_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424024B4UL)) +#define bFM4_MFT0_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424024B4UL)) + +#define bFM_MFT0_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42402360UL)) +#define bFM4_MFT0_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42402360UL)) +#define bFM_MFT0_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42402364UL)) +#define bFM4_MFT0_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42402364UL)) +#define bFM_MFT0_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42402368UL)) +#define bFM4_MFT0_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42402368UL)) +#define bFM_MFT0_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4240236CUL)) +#define bFM4_MFT0_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4240236CUL)) +#define bFM_MFT0_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42402370UL)) +#define bFM4_MFT0_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42402370UL)) +#define bFM_MFT0_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42402374UL)) +#define bFM4_MFT0_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42402374UL)) + +#define bFM_MFT0_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424023E0UL)) +#define bFM4_MFT0_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424023E0UL)) +#define bFM_MFT0_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424023E4UL)) +#define bFM4_MFT0_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424023E4UL)) +#define bFM_MFT0_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424023E8UL)) +#define bFM4_MFT0_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424023E8UL)) +#define bFM_MFT0_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424023ECUL)) +#define bFM4_MFT0_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424023ECUL)) +#define bFM_MFT0_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424023F0UL)) +#define bFM4_MFT0_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424023F0UL)) +#define bFM_MFT0_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424023F4UL)) +#define bFM4_MFT0_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424023F4UL)) + +#define bFM_MFT0_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42402460UL)) +#define bFM4_MFT0_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42402460UL)) +#define bFM_MFT0_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42402464UL)) +#define bFM4_MFT0_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42402464UL)) +#define bFM_MFT0_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42402468UL)) +#define bFM4_MFT0_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42402468UL)) +#define bFM_MFT0_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4240246CUL)) +#define bFM4_MFT0_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4240246CUL)) +#define bFM_MFT0_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42402470UL)) +#define bFM4_MFT0_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42402470UL)) +#define bFM_MFT0_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42402474UL)) +#define bFM4_MFT0_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42402474UL)) + +#define bFM_MFT0_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42403680UL)) +#define bFM4_MFT0_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42403680UL)) +#define bFM_MFT0_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42403690UL)) +#define bFM4_MFT0_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42403690UL)) +#define bFM_MFT0_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42403694UL)) +#define bFM4_MFT0_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42403694UL)) +#define bFM_MFT0_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4240369CUL)) +#define bFM4_MFT0_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4240369CUL)) +#define bFM_MFT0_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424036A0UL)) +#define bFM4_MFT0_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424036A0UL)) +#define bFM_MFT0_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424036A4UL)) +#define bFM4_MFT0_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424036A4UL)) +#define bFM_MFT0_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424036B0UL)) +#define bFM4_MFT0_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424036B0UL)) +#define bFM_MFT0_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424036B4UL)) +#define bFM4_MFT0_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424036B4UL)) +#define bFM_MFT0_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424036B8UL)) +#define bFM4_MFT0_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424036B8UL)) + +#define bFM_MFT0_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42403600UL)) +#define bFM4_MFT0_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42403600UL)) +#define bFM_MFT0_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42403604UL)) +#define bFM4_MFT0_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42403604UL)) +#define bFM_MFT0_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42403608UL)) +#define bFM4_MFT0_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42403608UL)) +#define bFM_MFT0_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4240360CUL)) +#define bFM4_MFT0_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4240360CUL)) +#define bFM_MFT0_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42403610UL)) +#define bFM4_MFT0_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42403610UL)) +#define bFM_MFT0_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42403614UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42403614UL)) +#define bFM_MFT0_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42403618UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42403618UL)) +#define bFM_MFT0_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4240361CUL)) +#define bFM4_MFT0_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4240361CUL)) +#define bFM_MFT0_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42403620UL)) +#define bFM4_MFT0_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42403620UL)) +#define bFM_MFT0_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42403624UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42403624UL)) +#define bFM_MFT0_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42403628UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42403628UL)) +#define bFM_MFT0_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4240362CUL)) +#define bFM4_MFT0_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4240362CUL)) +#define bFM_MFT0_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42403630UL)) +#define bFM4_MFT0_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42403630UL)) +#define bFM_MFT0_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42403634UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42403634UL)) +#define bFM_MFT0_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42403638UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42403638UL)) +#define bFM_MFT0_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4240363CUL)) +#define bFM4_MFT0_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4240363CUL)) + + +/******************************************************************************* +* MFT Registers MFT1 +* Bitband Section +*******************************************************************************/ +#define bFM_MFT1_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42423AD8UL)) +#define bFM4_MFT1_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42423AD8UL)) +#define bFM_MFT1_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42423ADCUL)) +#define bFM4_MFT1_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42423ADCUL)) + +#define bFM_MFT1_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42423B58UL)) +#define bFM4_MFT1_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42423B58UL)) +#define bFM_MFT1_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42423B5CUL)) +#define bFM4_MFT1_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42423B5CUL)) + +#define bFM_MFT1_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42423BD8UL)) +#define bFM4_MFT1_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42423BD8UL)) +#define bFM_MFT1_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42423BDCUL)) +#define bFM4_MFT1_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42423BDCUL)) + +#define bFM_MFT1_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42423C58UL)) +#define bFM4_MFT1_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42423C58UL)) +#define bFM_MFT1_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42423C5CUL)) +#define bFM4_MFT1_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42423C5CUL)) + +#define bFM_MFT1_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42423CD8UL)) +#define bFM4_MFT1_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42423CD8UL)) +#define bFM_MFT1_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42423CDCUL)) +#define bFM4_MFT1_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42423CDCUL)) + +#define bFM_MFT1_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42423D58UL)) +#define bFM4_MFT1_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42423D58UL)) +#define bFM_MFT1_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42423D5CUL)) +#define bFM4_MFT1_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42423D5CUL)) + +#define bFM_MFT1_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42423A94UL)) +#define bFM4_MFT1_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42423A94UL)) + +#define bFM_MFT1_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42423B14UL)) +#define bFM4_MFT1_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42423B14UL)) + +#define bFM_MFT1_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42423B94UL)) +#define bFM4_MFT1_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42423B94UL)) + +#define bFM_MFT1_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42423C14UL)) +#define bFM4_MFT1_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42423C14UL)) + +#define bFM_MFT1_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42423C94UL)) +#define bFM4_MFT1_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42423C94UL)) + +#define bFM_MFT1_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42423D14UL)) +#define bFM4_MFT1_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42423D14UL)) + +#define bFM_MFT1_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42423AA0UL)) +#define bFM4_MFT1_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42423AA0UL)) +#define bFM_MFT1_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42423AA4UL)) +#define bFM4_MFT1_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42423AA4UL)) +#define bFM_MFT1_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42423AB0UL)) +#define bFM4_MFT1_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42423AB0UL)) +#define bFM_MFT1_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42423AB4UL)) +#define bFM4_MFT1_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42423AB4UL)) +#define bFM_MFT1_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42423AB8UL)) +#define bFM4_MFT1_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42423AB8UL)) +#define bFM_MFT1_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42423ABCUL)) +#define bFM4_MFT1_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42423ABCUL)) + +#define bFM_MFT1_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42423B20UL)) +#define bFM4_MFT1_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42423B20UL)) +#define bFM_MFT1_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42423B24UL)) +#define bFM4_MFT1_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42423B24UL)) +#define bFM_MFT1_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42423B30UL)) +#define bFM4_MFT1_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42423B30UL)) +#define bFM_MFT1_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42423B34UL)) +#define bFM4_MFT1_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42423B34UL)) +#define bFM_MFT1_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42423B38UL)) +#define bFM4_MFT1_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42423B38UL)) +#define bFM_MFT1_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42423B3CUL)) +#define bFM4_MFT1_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42423B3CUL)) + +#define bFM_MFT1_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42423BA0UL)) +#define bFM4_MFT1_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42423BA0UL)) +#define bFM_MFT1_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42423BA4UL)) +#define bFM4_MFT1_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42423BA4UL)) +#define bFM_MFT1_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42423BB0UL)) +#define bFM4_MFT1_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42423BB0UL)) +#define bFM_MFT1_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42423BB4UL)) +#define bFM4_MFT1_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42423BB4UL)) +#define bFM_MFT1_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42423BB8UL)) +#define bFM4_MFT1_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42423BB8UL)) +#define bFM_MFT1_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42423BBCUL)) +#define bFM4_MFT1_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42423BBCUL)) + +#define bFM_MFT1_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42423C20UL)) +#define bFM4_MFT1_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42423C20UL)) +#define bFM_MFT1_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42423C24UL)) +#define bFM4_MFT1_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42423C24UL)) +#define bFM_MFT1_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42423C30UL)) +#define bFM4_MFT1_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42423C30UL)) +#define bFM_MFT1_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42423C34UL)) +#define bFM4_MFT1_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42423C34UL)) +#define bFM_MFT1_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42423C38UL)) +#define bFM4_MFT1_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42423C38UL)) +#define bFM_MFT1_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42423C3CUL)) +#define bFM4_MFT1_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42423C3CUL)) + +#define bFM_MFT1_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42423CA0UL)) +#define bFM4_MFT1_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42423CA0UL)) +#define bFM_MFT1_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42423CA4UL)) +#define bFM4_MFT1_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42423CA4UL)) +#define bFM_MFT1_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42423CB0UL)) +#define bFM4_MFT1_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42423CB0UL)) +#define bFM_MFT1_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42423CB4UL)) +#define bFM4_MFT1_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42423CB4UL)) +#define bFM_MFT1_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42423CB8UL)) +#define bFM4_MFT1_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42423CB8UL)) +#define bFM_MFT1_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42423CBCUL)) +#define bFM4_MFT1_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42423CBCUL)) + +#define bFM_MFT1_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42423D20UL)) +#define bFM4_MFT1_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42423D20UL)) +#define bFM_MFT1_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42423D24UL)) +#define bFM4_MFT1_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42423D24UL)) +#define bFM_MFT1_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42423D30UL)) +#define bFM4_MFT1_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42423D30UL)) +#define bFM_MFT1_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42423D34UL)) +#define bFM4_MFT1_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42423D34UL)) +#define bFM_MFT1_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42423D38UL)) +#define bFM4_MFT1_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42423D38UL)) +#define bFM_MFT1_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42423D3CUL)) +#define bFM4_MFT1_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42423D3CUL)) + +#define bFM_MFT1_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42422C80UL)) +#define bFM4_MFT1_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42422C80UL)) +#define bFM_MFT1_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42422C84UL)) +#define bFM4_MFT1_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42422C84UL)) +#define bFM_MFT1_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42422C88UL)) +#define bFM4_MFT1_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42422C88UL)) +#define bFM_MFT1_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42422C8CUL)) +#define bFM4_MFT1_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42422C8CUL)) +#define bFM_MFT1_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42422C90UL)) +#define bFM4_MFT1_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42422C90UL)) +#define bFM_MFT1_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42422C94UL)) +#define bFM4_MFT1_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42422C94UL)) +#define bFM_MFT1_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42422C98UL)) +#define bFM4_MFT1_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42422C98UL)) +#define bFM_MFT1_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42422C9CUL)) +#define bFM4_MFT1_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42422C9CUL)) +#define bFM_MFT1_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42422CA0UL)) +#define bFM4_MFT1_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42422CA0UL)) +#define bFM_MFT1_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42422CC0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42422CC0UL)) +#define bFM_MFT1_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42422CC4UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42422CC4UL)) +#define bFM_MFT1_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42422CC8UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42422CC8UL)) +#define bFM_MFT1_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42422CCCUL)) +#define bFM4_MFT1_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42422CCCUL)) +#define bFM_MFT1_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42422CD0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42422CD0UL)) +#define bFM_MFT1_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42422CD4UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42422CD4UL)) +#define bFM_MFT1_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42422CD8UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42422CD8UL)) +#define bFM_MFT1_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42422CDCUL)) +#define bFM4_MFT1_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42422CDCUL)) +#define bFM_MFT1_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42422CE0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42422CE0UL)) + +#define bFM_MFT1_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42422910UL)) +#define bFM4_MFT1_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42422910UL)) +#define bFM_MFT1_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42422914UL)) +#define bFM4_MFT1_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42422914UL)) +#define bFM_MFT1_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42422918UL)) +#define bFM4_MFT1_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42422918UL)) +#define bFM_MFT1_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4242291CUL)) +#define bFM4_MFT1_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4242291CUL)) +#define bFM_MFT1_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42422920UL)) +#define bFM4_MFT1_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42422920UL)) +#define bFM_MFT1_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42422924UL)) +#define bFM4_MFT1_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42422924UL)) +#define bFM_MFT1_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42422934UL)) +#define bFM4_MFT1_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42422934UL)) +#define bFM_MFT1_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42422938UL)) +#define bFM4_MFT1_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42422938UL)) +#define bFM_MFT1_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4242293CUL)) +#define bFM4_MFT1_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4242293CUL)) + +#define bFM_MFT1_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42422A90UL)) +#define bFM4_MFT1_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42422A90UL)) +#define bFM_MFT1_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42422A94UL)) +#define bFM4_MFT1_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42422A94UL)) +#define bFM_MFT1_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42422A98UL)) +#define bFM4_MFT1_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42422A98UL)) +#define bFM_MFT1_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42422A9CUL)) +#define bFM4_MFT1_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42422A9CUL)) +#define bFM_MFT1_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42422AA0UL)) +#define bFM4_MFT1_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42422AA0UL)) +#define bFM_MFT1_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42422AA4UL)) +#define bFM4_MFT1_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42422AA4UL)) +#define bFM_MFT1_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42422AB4UL)) +#define bFM4_MFT1_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42422AB4UL)) +#define bFM_MFT1_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42422AB8UL)) +#define bFM4_MFT1_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42422AB8UL)) +#define bFM_MFT1_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42422ABCUL)) +#define bFM4_MFT1_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42422ABCUL)) + +#define bFM_MFT1_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42422C10UL)) +#define bFM4_MFT1_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42422C10UL)) +#define bFM_MFT1_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42422C14UL)) +#define bFM4_MFT1_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42422C14UL)) +#define bFM_MFT1_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42422C18UL)) +#define bFM4_MFT1_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42422C18UL)) +#define bFM_MFT1_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42422C1CUL)) +#define bFM4_MFT1_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42422C1CUL)) +#define bFM_MFT1_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42422C20UL)) +#define bFM4_MFT1_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42422C20UL)) +#define bFM_MFT1_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42422C24UL)) +#define bFM4_MFT1_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42422C24UL)) +#define bFM_MFT1_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42422C34UL)) +#define bFM4_MFT1_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42422C34UL)) +#define bFM_MFT1_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42422C38UL)) +#define bFM4_MFT1_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42422C38UL)) +#define bFM_MFT1_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42422C3CUL)) +#define bFM4_MFT1_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42422C3CUL)) + +#define bFM_MFT1_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42423D80UL)) +#define bFM4_MFT1_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42423D80UL)) +#define bFM_MFT1_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42423D84UL)) +#define bFM4_MFT1_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42423D84UL)) + +#define bFM_MFT1_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42423090UL)) +#define bFM4_MFT1_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42423090UL)) +#define bFM_MFT1_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42423094UL)) +#define bFM4_MFT1_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42423094UL)) +#define bFM_MFT1_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42423098UL)) +#define bFM4_MFT1_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42423098UL)) +#define bFM_MFT1_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4242309CUL)) +#define bFM4_MFT1_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4242309CUL)) + +#define bFM_MFT1_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42423110UL)) +#define bFM4_MFT1_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42423110UL)) +#define bFM_MFT1_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42423114UL)) +#define bFM4_MFT1_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42423114UL)) +#define bFM_MFT1_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42423118UL)) +#define bFM4_MFT1_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42423118UL)) +#define bFM_MFT1_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4242311CUL)) +#define bFM4_MFT1_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4242311CUL)) + +#define bFM_MFT1_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424230A0UL)) +#define bFM4_MFT1_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424230A0UL)) +#define bFM_MFT1_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424230A4UL)) +#define bFM4_MFT1_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424230A4UL)) + +#define bFM_MFT1_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42423120UL)) +#define bFM4_MFT1_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42423120UL)) +#define bFM_MFT1_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42423124UL)) +#define bFM4_MFT1_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42423124UL)) + +#define bFM_MFT1_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42422300UL)) +#define bFM4_MFT1_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42422300UL)) +#define bFM_MFT1_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42422304UL)) +#define bFM4_MFT1_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42422304UL)) +#define bFM_MFT1_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42422310UL)) +#define bFM4_MFT1_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42422310UL)) +#define bFM_MFT1_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42422314UL)) +#define bFM4_MFT1_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42422314UL)) +#define bFM_MFT1_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42422318UL)) +#define bFM4_MFT1_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42422318UL)) +#define bFM_MFT1_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4242231CUL)) +#define bFM4_MFT1_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4242231CUL)) + +#define bFM_MFT1_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42422380UL)) +#define bFM4_MFT1_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42422380UL)) +#define bFM_MFT1_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42422384UL)) +#define bFM4_MFT1_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42422384UL)) +#define bFM_MFT1_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42422390UL)) +#define bFM4_MFT1_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42422390UL)) +#define bFM_MFT1_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42422394UL)) +#define bFM4_MFT1_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42422394UL)) +#define bFM_MFT1_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42422398UL)) +#define bFM4_MFT1_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42422398UL)) +#define bFM_MFT1_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4242239CUL)) +#define bFM4_MFT1_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4242239CUL)) + +#define bFM_MFT1_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42422400UL)) +#define bFM4_MFT1_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42422400UL)) +#define bFM_MFT1_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42422404UL)) +#define bFM4_MFT1_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42422404UL)) +#define bFM_MFT1_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42422410UL)) +#define bFM4_MFT1_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42422410UL)) +#define bFM_MFT1_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42422414UL)) +#define bFM4_MFT1_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42422414UL)) +#define bFM_MFT1_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42422418UL)) +#define bFM4_MFT1_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42422418UL)) +#define bFM_MFT1_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4242241CUL)) +#define bFM4_MFT1_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4242241CUL)) + +#define bFM_MFT1_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42422320UL)) +#define bFM4_MFT1_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42422320UL)) +#define bFM_MFT1_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42422324UL)) +#define bFM4_MFT1_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42422324UL)) +#define bFM_MFT1_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42422330UL)) +#define bFM4_MFT1_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42422330UL)) +#define bFM_MFT1_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4242233CUL)) +#define bFM4_MFT1_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4242233CUL)) + +#define bFM_MFT1_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424223A0UL)) +#define bFM4_MFT1_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424223A0UL)) +#define bFM_MFT1_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424223A4UL)) +#define bFM4_MFT1_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424223A4UL)) +#define bFM_MFT1_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424223B0UL)) +#define bFM4_MFT1_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424223B0UL)) +#define bFM_MFT1_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424223BCUL)) +#define bFM4_MFT1_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424223BCUL)) + +#define bFM_MFT1_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42422420UL)) +#define bFM4_MFT1_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42422420UL)) +#define bFM_MFT1_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42422424UL)) +#define bFM4_MFT1_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42422424UL)) +#define bFM_MFT1_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42422430UL)) +#define bFM4_MFT1_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42422430UL)) +#define bFM_MFT1_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4242243CUL)) +#define bFM4_MFT1_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4242243CUL)) + +#define bFM_MFT1_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424224A0UL)) +#define bFM4_MFT1_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424224A0UL)) +#define bFM_MFT1_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424224A4UL)) +#define bFM4_MFT1_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424224A4UL)) +#define bFM_MFT1_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424224A8UL)) +#define bFM4_MFT1_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424224A8UL)) +#define bFM_MFT1_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424224ACUL)) +#define bFM4_MFT1_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424224ACUL)) +#define bFM_MFT1_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424224B0UL)) +#define bFM4_MFT1_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424224B0UL)) +#define bFM_MFT1_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424224B4UL)) +#define bFM4_MFT1_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424224B4UL)) + +#define bFM_MFT1_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42422360UL)) +#define bFM4_MFT1_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42422360UL)) +#define bFM_MFT1_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42422364UL)) +#define bFM4_MFT1_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42422364UL)) +#define bFM_MFT1_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42422368UL)) +#define bFM4_MFT1_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42422368UL)) +#define bFM_MFT1_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4242236CUL)) +#define bFM4_MFT1_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4242236CUL)) +#define bFM_MFT1_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42422370UL)) +#define bFM4_MFT1_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42422370UL)) +#define bFM_MFT1_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42422374UL)) +#define bFM4_MFT1_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42422374UL)) + +#define bFM_MFT1_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424223E0UL)) +#define bFM4_MFT1_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424223E0UL)) +#define bFM_MFT1_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424223E4UL)) +#define bFM4_MFT1_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424223E4UL)) +#define bFM_MFT1_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424223E8UL)) +#define bFM4_MFT1_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424223E8UL)) +#define bFM_MFT1_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424223ECUL)) +#define bFM4_MFT1_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424223ECUL)) +#define bFM_MFT1_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424223F0UL)) +#define bFM4_MFT1_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424223F0UL)) +#define bFM_MFT1_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424223F4UL)) +#define bFM4_MFT1_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424223F4UL)) + +#define bFM_MFT1_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42422460UL)) +#define bFM4_MFT1_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42422460UL)) +#define bFM_MFT1_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42422464UL)) +#define bFM4_MFT1_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42422464UL)) +#define bFM_MFT1_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42422468UL)) +#define bFM4_MFT1_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42422468UL)) +#define bFM_MFT1_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4242246CUL)) +#define bFM4_MFT1_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4242246CUL)) +#define bFM_MFT1_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42422470UL)) +#define bFM4_MFT1_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42422470UL)) +#define bFM_MFT1_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42422474UL)) +#define bFM4_MFT1_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42422474UL)) + +#define bFM_MFT1_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42423680UL)) +#define bFM4_MFT1_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42423680UL)) +#define bFM_MFT1_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42423690UL)) +#define bFM4_MFT1_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42423690UL)) +#define bFM_MFT1_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42423694UL)) +#define bFM4_MFT1_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42423694UL)) +#define bFM_MFT1_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4242369CUL)) +#define bFM4_MFT1_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4242369CUL)) +#define bFM_MFT1_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424236A0UL)) +#define bFM4_MFT1_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424236A0UL)) +#define bFM_MFT1_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424236A4UL)) +#define bFM4_MFT1_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424236A4UL)) +#define bFM_MFT1_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424236B0UL)) +#define bFM4_MFT1_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424236B0UL)) +#define bFM_MFT1_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424236B4UL)) +#define bFM4_MFT1_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424236B4UL)) +#define bFM_MFT1_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424236B8UL)) +#define bFM4_MFT1_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424236B8UL)) + +#define bFM_MFT1_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42423600UL)) +#define bFM4_MFT1_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42423600UL)) +#define bFM_MFT1_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42423604UL)) +#define bFM4_MFT1_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42423604UL)) +#define bFM_MFT1_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42423608UL)) +#define bFM4_MFT1_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42423608UL)) +#define bFM_MFT1_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4242360CUL)) +#define bFM4_MFT1_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4242360CUL)) +#define bFM_MFT1_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42423610UL)) +#define bFM4_MFT1_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42423610UL)) +#define bFM_MFT1_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42423614UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42423614UL)) +#define bFM_MFT1_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42423618UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42423618UL)) +#define bFM_MFT1_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4242361CUL)) +#define bFM4_MFT1_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4242361CUL)) +#define bFM_MFT1_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42423620UL)) +#define bFM4_MFT1_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42423620UL)) +#define bFM_MFT1_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42423624UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42423624UL)) +#define bFM_MFT1_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42423628UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42423628UL)) +#define bFM_MFT1_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4242362CUL)) +#define bFM4_MFT1_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4242362CUL)) +#define bFM_MFT1_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42423630UL)) +#define bFM4_MFT1_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42423630UL)) +#define bFM_MFT1_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42423634UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42423634UL)) +#define bFM_MFT1_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42423638UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42423638UL)) +#define bFM_MFT1_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4242363CUL)) +#define bFM4_MFT1_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4242363CUL)) + + +/******************************************************************************* +* MFT Registers MFT2 +* Bitband Section +*******************************************************************************/ +#define bFM_MFT2_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42443AD8UL)) +#define bFM4_MFT2_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42443AD8UL)) +#define bFM_MFT2_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42443ADCUL)) +#define bFM4_MFT2_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42443ADCUL)) + +#define bFM_MFT2_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42443B58UL)) +#define bFM4_MFT2_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42443B58UL)) +#define bFM_MFT2_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42443B5CUL)) +#define bFM4_MFT2_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42443B5CUL)) + +#define bFM_MFT2_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42443BD8UL)) +#define bFM4_MFT2_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42443BD8UL)) +#define bFM_MFT2_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42443BDCUL)) +#define bFM4_MFT2_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42443BDCUL)) + +#define bFM_MFT2_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42443C58UL)) +#define bFM4_MFT2_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42443C58UL)) +#define bFM_MFT2_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42443C5CUL)) +#define bFM4_MFT2_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42443C5CUL)) + +#define bFM_MFT2_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42443CD8UL)) +#define bFM4_MFT2_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42443CD8UL)) +#define bFM_MFT2_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42443CDCUL)) +#define bFM4_MFT2_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42443CDCUL)) + +#define bFM_MFT2_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42443D58UL)) +#define bFM4_MFT2_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42443D58UL)) +#define bFM_MFT2_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42443D5CUL)) +#define bFM4_MFT2_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42443D5CUL)) + +#define bFM_MFT2_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42443A94UL)) +#define bFM4_MFT2_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42443A94UL)) + +#define bFM_MFT2_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42443B14UL)) +#define bFM4_MFT2_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42443B14UL)) + +#define bFM_MFT2_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42443B94UL)) +#define bFM4_MFT2_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42443B94UL)) + +#define bFM_MFT2_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42443C14UL)) +#define bFM4_MFT2_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42443C14UL)) + +#define bFM_MFT2_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42443C94UL)) +#define bFM4_MFT2_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42443C94UL)) + +#define bFM_MFT2_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42443D14UL)) +#define bFM4_MFT2_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42443D14UL)) + +#define bFM_MFT2_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42443AA0UL)) +#define bFM4_MFT2_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42443AA0UL)) +#define bFM_MFT2_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42443AA4UL)) +#define bFM4_MFT2_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42443AA4UL)) +#define bFM_MFT2_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42443AB0UL)) +#define bFM4_MFT2_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42443AB0UL)) +#define bFM_MFT2_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42443AB4UL)) +#define bFM4_MFT2_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42443AB4UL)) +#define bFM_MFT2_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42443AB8UL)) +#define bFM4_MFT2_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42443AB8UL)) +#define bFM_MFT2_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42443ABCUL)) +#define bFM4_MFT2_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42443ABCUL)) + +#define bFM_MFT2_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42443B20UL)) +#define bFM4_MFT2_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42443B20UL)) +#define bFM_MFT2_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42443B24UL)) +#define bFM4_MFT2_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42443B24UL)) +#define bFM_MFT2_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42443B30UL)) +#define bFM4_MFT2_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42443B30UL)) +#define bFM_MFT2_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42443B34UL)) +#define bFM4_MFT2_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42443B34UL)) +#define bFM_MFT2_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42443B38UL)) +#define bFM4_MFT2_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42443B38UL)) +#define bFM_MFT2_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42443B3CUL)) +#define bFM4_MFT2_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42443B3CUL)) + +#define bFM_MFT2_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42443BA0UL)) +#define bFM4_MFT2_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42443BA0UL)) +#define bFM_MFT2_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42443BA4UL)) +#define bFM4_MFT2_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42443BA4UL)) +#define bFM_MFT2_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42443BB0UL)) +#define bFM4_MFT2_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42443BB0UL)) +#define bFM_MFT2_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42443BB4UL)) +#define bFM4_MFT2_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42443BB4UL)) +#define bFM_MFT2_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42443BB8UL)) +#define bFM4_MFT2_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42443BB8UL)) +#define bFM_MFT2_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42443BBCUL)) +#define bFM4_MFT2_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42443BBCUL)) + +#define bFM_MFT2_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42443C20UL)) +#define bFM4_MFT2_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42443C20UL)) +#define bFM_MFT2_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42443C24UL)) +#define bFM4_MFT2_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42443C24UL)) +#define bFM_MFT2_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42443C30UL)) +#define bFM4_MFT2_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42443C30UL)) +#define bFM_MFT2_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42443C34UL)) +#define bFM4_MFT2_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42443C34UL)) +#define bFM_MFT2_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42443C38UL)) +#define bFM4_MFT2_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42443C38UL)) +#define bFM_MFT2_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42443C3CUL)) +#define bFM4_MFT2_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42443C3CUL)) + +#define bFM_MFT2_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42443CA0UL)) +#define bFM4_MFT2_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42443CA0UL)) +#define bFM_MFT2_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42443CA4UL)) +#define bFM4_MFT2_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42443CA4UL)) +#define bFM_MFT2_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42443CB0UL)) +#define bFM4_MFT2_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42443CB0UL)) +#define bFM_MFT2_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42443CB4UL)) +#define bFM4_MFT2_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42443CB4UL)) +#define bFM_MFT2_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42443CB8UL)) +#define bFM4_MFT2_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42443CB8UL)) +#define bFM_MFT2_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42443CBCUL)) +#define bFM4_MFT2_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42443CBCUL)) + +#define bFM_MFT2_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42443D20UL)) +#define bFM4_MFT2_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42443D20UL)) +#define bFM_MFT2_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42443D24UL)) +#define bFM4_MFT2_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42443D24UL)) +#define bFM_MFT2_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42443D30UL)) +#define bFM4_MFT2_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42443D30UL)) +#define bFM_MFT2_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42443D34UL)) +#define bFM4_MFT2_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42443D34UL)) +#define bFM_MFT2_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42443D38UL)) +#define bFM4_MFT2_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42443D38UL)) +#define bFM_MFT2_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42443D3CUL)) +#define bFM4_MFT2_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42443D3CUL)) + +#define bFM_MFT2_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42442C80UL)) +#define bFM4_MFT2_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42442C80UL)) +#define bFM_MFT2_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42442C84UL)) +#define bFM4_MFT2_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42442C84UL)) +#define bFM_MFT2_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42442C88UL)) +#define bFM4_MFT2_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42442C88UL)) +#define bFM_MFT2_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42442C8CUL)) +#define bFM4_MFT2_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42442C8CUL)) +#define bFM_MFT2_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42442C90UL)) +#define bFM4_MFT2_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42442C90UL)) +#define bFM_MFT2_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42442C94UL)) +#define bFM4_MFT2_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42442C94UL)) +#define bFM_MFT2_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42442C98UL)) +#define bFM4_MFT2_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42442C98UL)) +#define bFM_MFT2_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42442C9CUL)) +#define bFM4_MFT2_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42442C9CUL)) +#define bFM_MFT2_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42442CA0UL)) +#define bFM4_MFT2_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42442CA0UL)) +#define bFM_MFT2_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42442CC0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42442CC0UL)) +#define bFM_MFT2_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42442CC4UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42442CC4UL)) +#define bFM_MFT2_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42442CC8UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42442CC8UL)) +#define bFM_MFT2_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42442CCCUL)) +#define bFM4_MFT2_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42442CCCUL)) +#define bFM_MFT2_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42442CD0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42442CD0UL)) +#define bFM_MFT2_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42442CD4UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42442CD4UL)) +#define bFM_MFT2_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42442CD8UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42442CD8UL)) +#define bFM_MFT2_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42442CDCUL)) +#define bFM4_MFT2_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42442CDCUL)) +#define bFM_MFT2_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42442CE0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42442CE0UL)) + +#define bFM_MFT2_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42442910UL)) +#define bFM4_MFT2_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42442910UL)) +#define bFM_MFT2_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42442914UL)) +#define bFM4_MFT2_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42442914UL)) +#define bFM_MFT2_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42442918UL)) +#define bFM4_MFT2_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42442918UL)) +#define bFM_MFT2_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4244291CUL)) +#define bFM4_MFT2_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4244291CUL)) +#define bFM_MFT2_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42442920UL)) +#define bFM4_MFT2_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42442920UL)) +#define bFM_MFT2_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42442924UL)) +#define bFM4_MFT2_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42442924UL)) +#define bFM_MFT2_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42442934UL)) +#define bFM4_MFT2_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42442934UL)) +#define bFM_MFT2_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42442938UL)) +#define bFM4_MFT2_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42442938UL)) +#define bFM_MFT2_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4244293CUL)) +#define bFM4_MFT2_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4244293CUL)) + +#define bFM_MFT2_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42442A90UL)) +#define bFM4_MFT2_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42442A90UL)) +#define bFM_MFT2_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42442A94UL)) +#define bFM4_MFT2_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42442A94UL)) +#define bFM_MFT2_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42442A98UL)) +#define bFM4_MFT2_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42442A98UL)) +#define bFM_MFT2_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42442A9CUL)) +#define bFM4_MFT2_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42442A9CUL)) +#define bFM_MFT2_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42442AA0UL)) +#define bFM4_MFT2_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42442AA0UL)) +#define bFM_MFT2_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42442AA4UL)) +#define bFM4_MFT2_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42442AA4UL)) +#define bFM_MFT2_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42442AB4UL)) +#define bFM4_MFT2_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42442AB4UL)) +#define bFM_MFT2_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42442AB8UL)) +#define bFM4_MFT2_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42442AB8UL)) +#define bFM_MFT2_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42442ABCUL)) +#define bFM4_MFT2_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42442ABCUL)) + +#define bFM_MFT2_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42442C10UL)) +#define bFM4_MFT2_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42442C10UL)) +#define bFM_MFT2_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42442C14UL)) +#define bFM4_MFT2_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42442C14UL)) +#define bFM_MFT2_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42442C18UL)) +#define bFM4_MFT2_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42442C18UL)) +#define bFM_MFT2_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42442C1CUL)) +#define bFM4_MFT2_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42442C1CUL)) +#define bFM_MFT2_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42442C20UL)) +#define bFM4_MFT2_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42442C20UL)) +#define bFM_MFT2_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42442C24UL)) +#define bFM4_MFT2_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42442C24UL)) +#define bFM_MFT2_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42442C34UL)) +#define bFM4_MFT2_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42442C34UL)) +#define bFM_MFT2_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42442C38UL)) +#define bFM4_MFT2_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42442C38UL)) +#define bFM_MFT2_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42442C3CUL)) +#define bFM4_MFT2_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42442C3CUL)) + +#define bFM_MFT2_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42443D80UL)) +#define bFM4_MFT2_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42443D80UL)) +#define bFM_MFT2_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42443D84UL)) +#define bFM4_MFT2_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42443D84UL)) + +#define bFM_MFT2_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42443090UL)) +#define bFM4_MFT2_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42443090UL)) +#define bFM_MFT2_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42443094UL)) +#define bFM4_MFT2_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42443094UL)) +#define bFM_MFT2_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42443098UL)) +#define bFM4_MFT2_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42443098UL)) +#define bFM_MFT2_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4244309CUL)) +#define bFM4_MFT2_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4244309CUL)) + +#define bFM_MFT2_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42443110UL)) +#define bFM4_MFT2_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42443110UL)) +#define bFM_MFT2_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42443114UL)) +#define bFM4_MFT2_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42443114UL)) +#define bFM_MFT2_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42443118UL)) +#define bFM4_MFT2_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42443118UL)) +#define bFM_MFT2_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4244311CUL)) +#define bFM4_MFT2_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4244311CUL)) + +#define bFM_MFT2_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424430A0UL)) +#define bFM4_MFT2_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424430A0UL)) +#define bFM_MFT2_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424430A4UL)) +#define bFM4_MFT2_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424430A4UL)) + +#define bFM_MFT2_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42443120UL)) +#define bFM4_MFT2_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42443120UL)) +#define bFM_MFT2_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42443124UL)) +#define bFM4_MFT2_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42443124UL)) + +#define bFM_MFT2_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42442300UL)) +#define bFM4_MFT2_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42442300UL)) +#define bFM_MFT2_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42442304UL)) +#define bFM4_MFT2_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42442304UL)) +#define bFM_MFT2_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42442310UL)) +#define bFM4_MFT2_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42442310UL)) +#define bFM_MFT2_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42442314UL)) +#define bFM4_MFT2_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42442314UL)) +#define bFM_MFT2_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42442318UL)) +#define bFM4_MFT2_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42442318UL)) +#define bFM_MFT2_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4244231CUL)) +#define bFM4_MFT2_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4244231CUL)) + +#define bFM_MFT2_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42442380UL)) +#define bFM4_MFT2_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42442380UL)) +#define bFM_MFT2_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42442384UL)) +#define bFM4_MFT2_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42442384UL)) +#define bFM_MFT2_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42442390UL)) +#define bFM4_MFT2_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42442390UL)) +#define bFM_MFT2_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42442394UL)) +#define bFM4_MFT2_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42442394UL)) +#define bFM_MFT2_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42442398UL)) +#define bFM4_MFT2_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42442398UL)) +#define bFM_MFT2_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4244239CUL)) +#define bFM4_MFT2_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4244239CUL)) + +#define bFM_MFT2_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42442400UL)) +#define bFM4_MFT2_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42442400UL)) +#define bFM_MFT2_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42442404UL)) +#define bFM4_MFT2_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42442404UL)) +#define bFM_MFT2_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42442410UL)) +#define bFM4_MFT2_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42442410UL)) +#define bFM_MFT2_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42442414UL)) +#define bFM4_MFT2_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42442414UL)) +#define bFM_MFT2_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42442418UL)) +#define bFM4_MFT2_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42442418UL)) +#define bFM_MFT2_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4244241CUL)) +#define bFM4_MFT2_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4244241CUL)) + +#define bFM_MFT2_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42442320UL)) +#define bFM4_MFT2_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42442320UL)) +#define bFM_MFT2_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42442324UL)) +#define bFM4_MFT2_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42442324UL)) +#define bFM_MFT2_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42442330UL)) +#define bFM4_MFT2_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42442330UL)) +#define bFM_MFT2_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4244233CUL)) +#define bFM4_MFT2_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4244233CUL)) + +#define bFM_MFT2_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424423A0UL)) +#define bFM4_MFT2_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424423A0UL)) +#define bFM_MFT2_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424423A4UL)) +#define bFM4_MFT2_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424423A4UL)) +#define bFM_MFT2_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424423B0UL)) +#define bFM4_MFT2_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424423B0UL)) +#define bFM_MFT2_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424423BCUL)) +#define bFM4_MFT2_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424423BCUL)) + +#define bFM_MFT2_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42442420UL)) +#define bFM4_MFT2_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42442420UL)) +#define bFM_MFT2_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42442424UL)) +#define bFM4_MFT2_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42442424UL)) +#define bFM_MFT2_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42442430UL)) +#define bFM4_MFT2_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42442430UL)) +#define bFM_MFT2_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4244243CUL)) +#define bFM4_MFT2_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4244243CUL)) + +#define bFM_MFT2_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424424A0UL)) +#define bFM4_MFT2_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424424A0UL)) +#define bFM_MFT2_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424424A4UL)) +#define bFM4_MFT2_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424424A4UL)) +#define bFM_MFT2_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424424A8UL)) +#define bFM4_MFT2_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424424A8UL)) +#define bFM_MFT2_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424424ACUL)) +#define bFM4_MFT2_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424424ACUL)) +#define bFM_MFT2_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424424B0UL)) +#define bFM4_MFT2_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424424B0UL)) +#define bFM_MFT2_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424424B4UL)) +#define bFM4_MFT2_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424424B4UL)) + +#define bFM_MFT2_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42442360UL)) +#define bFM4_MFT2_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42442360UL)) +#define bFM_MFT2_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42442364UL)) +#define bFM4_MFT2_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42442364UL)) +#define bFM_MFT2_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42442368UL)) +#define bFM4_MFT2_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42442368UL)) +#define bFM_MFT2_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4244236CUL)) +#define bFM4_MFT2_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4244236CUL)) +#define bFM_MFT2_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42442370UL)) +#define bFM4_MFT2_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42442370UL)) +#define bFM_MFT2_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42442374UL)) +#define bFM4_MFT2_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42442374UL)) + +#define bFM_MFT2_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424423E0UL)) +#define bFM4_MFT2_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424423E0UL)) +#define bFM_MFT2_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424423E4UL)) +#define bFM4_MFT2_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424423E4UL)) +#define bFM_MFT2_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424423E8UL)) +#define bFM4_MFT2_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424423E8UL)) +#define bFM_MFT2_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424423ECUL)) +#define bFM4_MFT2_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424423ECUL)) +#define bFM_MFT2_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424423F0UL)) +#define bFM4_MFT2_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424423F0UL)) +#define bFM_MFT2_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424423F4UL)) +#define bFM4_MFT2_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424423F4UL)) + +#define bFM_MFT2_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42442460UL)) +#define bFM4_MFT2_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42442460UL)) +#define bFM_MFT2_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42442464UL)) +#define bFM4_MFT2_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42442464UL)) +#define bFM_MFT2_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42442468UL)) +#define bFM4_MFT2_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42442468UL)) +#define bFM_MFT2_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4244246CUL)) +#define bFM4_MFT2_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4244246CUL)) +#define bFM_MFT2_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42442470UL)) +#define bFM4_MFT2_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42442470UL)) +#define bFM_MFT2_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42442474UL)) +#define bFM4_MFT2_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42442474UL)) + +#define bFM_MFT2_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42443680UL)) +#define bFM4_MFT2_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42443680UL)) +#define bFM_MFT2_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42443690UL)) +#define bFM4_MFT2_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42443690UL)) +#define bFM_MFT2_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42443694UL)) +#define bFM4_MFT2_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42443694UL)) +#define bFM_MFT2_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4244369CUL)) +#define bFM4_MFT2_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4244369CUL)) +#define bFM_MFT2_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424436A0UL)) +#define bFM4_MFT2_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424436A0UL)) +#define bFM_MFT2_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424436A4UL)) +#define bFM4_MFT2_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424436A4UL)) +#define bFM_MFT2_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424436B0UL)) +#define bFM4_MFT2_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424436B0UL)) +#define bFM_MFT2_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424436B4UL)) +#define bFM4_MFT2_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424436B4UL)) +#define bFM_MFT2_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424436B8UL)) +#define bFM4_MFT2_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424436B8UL)) + +#define bFM_MFT2_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42443600UL)) +#define bFM4_MFT2_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42443600UL)) +#define bFM_MFT2_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42443604UL)) +#define bFM4_MFT2_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42443604UL)) +#define bFM_MFT2_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42443608UL)) +#define bFM4_MFT2_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42443608UL)) +#define bFM_MFT2_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4244360CUL)) +#define bFM4_MFT2_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4244360CUL)) +#define bFM_MFT2_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42443610UL)) +#define bFM4_MFT2_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42443610UL)) +#define bFM_MFT2_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42443614UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42443614UL)) +#define bFM_MFT2_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42443618UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42443618UL)) +#define bFM_MFT2_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4244361CUL)) +#define bFM4_MFT2_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4244361CUL)) +#define bFM_MFT2_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42443620UL)) +#define bFM4_MFT2_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42443620UL)) +#define bFM_MFT2_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42443624UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42443624UL)) +#define bFM_MFT2_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42443628UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42443628UL)) +#define bFM_MFT2_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4244362CUL)) +#define bFM4_MFT2_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4244362CUL)) +#define bFM_MFT2_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42443630UL)) +#define bFM4_MFT2_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42443630UL)) +#define bFM_MFT2_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42443634UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42443634UL)) +#define bFM_MFT2_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42443638UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42443638UL)) +#define bFM_MFT2_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4244363CUL)) +#define bFM4_MFT2_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4244363CUL)) + + +/******************************************************************************* +* PCRC Registers PCRC +* Bitband Section +*******************************************************************************/ +#define bFM_PCRC_PCRC_CFG_CIRQCLR *((volatile uint8_t *)(0x43000180UL)) +#define bFM4_PCRC_PCRC_CFG_CIRQCLR *((volatile uint8_t *)(0x43000180UL)) +#define bFM_PCRC_PCRC_CFG_CIRQ *((volatile uint8_t *)(0x430001E0UL)) +#define bFM4_PCRC_PCRC_CFG_CIRQ *((volatile uint8_t *)(0x430001E0UL)) +#define bFM_PCRC_PCRC_CFG_CIEN *((volatile uint8_t *)(0x430001E4UL)) +#define bFM4_PCRC_PCRC_CFG_CIEN *((volatile uint8_t *)(0x430001E4UL)) +#define bFM_PCRC_PCRC_CFG_CDEN *((volatile uint8_t *)(0x430001E8UL)) +#define bFM4_PCRC_PCRC_CFG_CDEN *((volatile uint8_t *)(0x430001E8UL)) +#define bFM_PCRC_PCRC_CFG_LOCK *((volatile uint8_t *)(0x430001F0UL)) +#define bFM4_PCRC_PCRC_CFG_LOCK *((volatile uint8_t *)(0x430001F0UL)) + + +/******************************************************************************* +* QPRC Registers QPRC0 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC0_QCR_PSTP *((volatile uint8_t *)(0x424C0310UL)) +#define bFM4_QPRC0_QCR_PSTP *((volatile uint8_t *)(0x424C0310UL)) +#define bFM_QPRC0_QCR_CGSC *((volatile uint8_t *)(0x424C0314UL)) +#define bFM4_QPRC0_QCR_CGSC *((volatile uint8_t *)(0x424C0314UL)) +#define bFM_QPRC0_QCR_RSEL *((volatile uint8_t *)(0x424C0318UL)) +#define bFM4_QPRC0_QCR_RSEL *((volatile uint8_t *)(0x424C0318UL)) +#define bFM_QPRC0_QCR_SWAP *((volatile uint8_t *)(0x424C031CUL)) +#define bFM4_QPRC0_QCR_SWAP *((volatile uint8_t *)(0x424C031CUL)) + +#define bFM_QPRC0_QECR_ORNGMD *((volatile uint8_t *)(0x424C0380UL)) +#define bFM4_QPRC0_QECR_ORNGMD *((volatile uint8_t *)(0x424C0380UL)) +#define bFM_QPRC0_QECR_ORNGF *((volatile uint8_t *)(0x424C0384UL)) +#define bFM4_QPRC0_QECR_ORNGF *((volatile uint8_t *)(0x424C0384UL)) +#define bFM_QPRC0_QECR_ORNGIE *((volatile uint8_t *)(0x424C0388UL)) +#define bFM4_QPRC0_QECR_ORNGIE *((volatile uint8_t *)(0x424C0388UL)) +#define bFM_QPRC0_QECR_PEC *((volatile uint8_t *)(0x424C038CUL)) +#define bFM4_QPRC0_QECR_PEC *((volatile uint8_t *)(0x424C038CUL)) + +#define bFM_QPRC0_QICRH_CDCIE *((volatile uint8_t *)(0x424C02A0UL)) +#define bFM4_QPRC0_QICRH_CDCIE *((volatile uint8_t *)(0x424C02A0UL)) +#define bFM_QPRC0_QICRH_CDCF *((volatile uint8_t *)(0x424C02A4UL)) +#define bFM4_QPRC0_QICRH_CDCF *((volatile uint8_t *)(0x424C02A4UL)) +#define bFM_QPRC0_QICRH_DIRPC *((volatile uint8_t *)(0x424C02A8UL)) +#define bFM4_QPRC0_QICRH_DIRPC *((volatile uint8_t *)(0x424C02A8UL)) +#define bFM_QPRC0_QICRH_DIROU *((volatile uint8_t *)(0x424C02ACUL)) +#define bFM4_QPRC0_QICRH_DIROU *((volatile uint8_t *)(0x424C02ACUL)) +#define bFM_QPRC0_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C02B0UL)) +#define bFM4_QPRC0_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C02B0UL)) +#define bFM_QPRC0_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C02B4UL)) +#define bFM4_QPRC0_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C02B4UL)) + +#define bFM_QPRC0_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0280UL)) +#define bFM4_QPRC0_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0280UL)) +#define bFM_QPRC0_QICRL_QPCMF *((volatile uint8_t *)(0x424C0284UL)) +#define bFM4_QPRC0_QICRL_QPCMF *((volatile uint8_t *)(0x424C0284UL)) +#define bFM_QPRC0_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0288UL)) +#define bFM4_QPRC0_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0288UL)) +#define bFM_QPRC0_QICRL_QPRCMF *((volatile uint8_t *)(0x424C028CUL)) +#define bFM4_QPRC0_QICRL_QPRCMF *((volatile uint8_t *)(0x424C028CUL)) +#define bFM_QPRC0_QICRL_OUZIE *((volatile uint8_t *)(0x424C0290UL)) +#define bFM4_QPRC0_QICRL_OUZIE *((volatile uint8_t *)(0x424C0290UL)) +#define bFM_QPRC0_QICRL_UFDF *((volatile uint8_t *)(0x424C0294UL)) +#define bFM4_QPRC0_QICRL_UFDF *((volatile uint8_t *)(0x424C0294UL)) +#define bFM_QPRC0_QICRL_OFDF *((volatile uint8_t *)(0x424C0298UL)) +#define bFM4_QPRC0_QICRL_OFDF *((volatile uint8_t *)(0x424C0298UL)) +#define bFM_QPRC0_QICRL_ZIIF *((volatile uint8_t *)(0x424C029CUL)) +#define bFM4_QPRC0_QICRL_ZIIF *((volatile uint8_t *)(0x424C029CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC0_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC0_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2010UL)) +#define bFM4_QPRC0_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2010UL)) +#define bFM_QPRC0_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2014UL)) +#define bFM4_QPRC0_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2014UL)) + +#define bFM_QPRC0_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2090UL)) +#define bFM4_QPRC0_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2090UL)) +#define bFM_QPRC0_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2094UL)) +#define bFM4_QPRC0_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2094UL)) + +#define bFM_QPRC0_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2110UL)) +#define bFM4_QPRC0_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2110UL)) +#define bFM_QPRC0_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2114UL)) +#define bFM4_QPRC0_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2114UL)) + + +/******************************************************************************* +* QPRC Registers QPRC1 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC1_QCR_PSTP *((volatile uint8_t *)(0x424C0B10UL)) +#define bFM4_QPRC1_QCR_PSTP *((volatile uint8_t *)(0x424C0B10UL)) +#define bFM_QPRC1_QCR_CGSC *((volatile uint8_t *)(0x424C0B14UL)) +#define bFM4_QPRC1_QCR_CGSC *((volatile uint8_t *)(0x424C0B14UL)) +#define bFM_QPRC1_QCR_RSEL *((volatile uint8_t *)(0x424C0B18UL)) +#define bFM4_QPRC1_QCR_RSEL *((volatile uint8_t *)(0x424C0B18UL)) +#define bFM_QPRC1_QCR_SWAP *((volatile uint8_t *)(0x424C0B1CUL)) +#define bFM4_QPRC1_QCR_SWAP *((volatile uint8_t *)(0x424C0B1CUL)) + +#define bFM_QPRC1_QECR_ORNGMD *((volatile uint8_t *)(0x424C0B80UL)) +#define bFM4_QPRC1_QECR_ORNGMD *((volatile uint8_t *)(0x424C0B80UL)) +#define bFM_QPRC1_QECR_ORNGF *((volatile uint8_t *)(0x424C0B84UL)) +#define bFM4_QPRC1_QECR_ORNGF *((volatile uint8_t *)(0x424C0B84UL)) +#define bFM_QPRC1_QECR_ORNGIE *((volatile uint8_t *)(0x424C0B88UL)) +#define bFM4_QPRC1_QECR_ORNGIE *((volatile uint8_t *)(0x424C0B88UL)) +#define bFM_QPRC1_QECR_PEC *((volatile uint8_t *)(0x424C0B8CUL)) +#define bFM4_QPRC1_QECR_PEC *((volatile uint8_t *)(0x424C0B8CUL)) + +#define bFM_QPRC1_QICRH_CDCIE *((volatile uint8_t *)(0x424C0AA0UL)) +#define bFM4_QPRC1_QICRH_CDCIE *((volatile uint8_t *)(0x424C0AA0UL)) +#define bFM_QPRC1_QICRH_CDCF *((volatile uint8_t *)(0x424C0AA4UL)) +#define bFM4_QPRC1_QICRH_CDCF *((volatile uint8_t *)(0x424C0AA4UL)) +#define bFM_QPRC1_QICRH_DIRPC *((volatile uint8_t *)(0x424C0AA8UL)) +#define bFM4_QPRC1_QICRH_DIRPC *((volatile uint8_t *)(0x424C0AA8UL)) +#define bFM_QPRC1_QICRH_DIROU *((volatile uint8_t *)(0x424C0AACUL)) +#define bFM4_QPRC1_QICRH_DIROU *((volatile uint8_t *)(0x424C0AACUL)) +#define bFM_QPRC1_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C0AB0UL)) +#define bFM4_QPRC1_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C0AB0UL)) +#define bFM_QPRC1_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C0AB4UL)) +#define bFM4_QPRC1_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C0AB4UL)) + +#define bFM_QPRC1_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0A80UL)) +#define bFM4_QPRC1_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0A80UL)) +#define bFM_QPRC1_QICRL_QPCMF *((volatile uint8_t *)(0x424C0A84UL)) +#define bFM4_QPRC1_QICRL_QPCMF *((volatile uint8_t *)(0x424C0A84UL)) +#define bFM_QPRC1_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0A88UL)) +#define bFM4_QPRC1_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0A88UL)) +#define bFM_QPRC1_QICRL_QPRCMF *((volatile uint8_t *)(0x424C0A8CUL)) +#define bFM4_QPRC1_QICRL_QPRCMF *((volatile uint8_t *)(0x424C0A8CUL)) +#define bFM_QPRC1_QICRL_OUZIE *((volatile uint8_t *)(0x424C0A90UL)) +#define bFM4_QPRC1_QICRL_OUZIE *((volatile uint8_t *)(0x424C0A90UL)) +#define bFM_QPRC1_QICRL_UFDF *((volatile uint8_t *)(0x424C0A94UL)) +#define bFM4_QPRC1_QICRL_UFDF *((volatile uint8_t *)(0x424C0A94UL)) +#define bFM_QPRC1_QICRL_OFDF *((volatile uint8_t *)(0x424C0A98UL)) +#define bFM4_QPRC1_QICRL_OFDF *((volatile uint8_t *)(0x424C0A98UL)) +#define bFM_QPRC1_QICRL_ZIIF *((volatile uint8_t *)(0x424C0A9CUL)) +#define bFM4_QPRC1_QICRL_ZIIF *((volatile uint8_t *)(0x424C0A9CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC1_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC1_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2210UL)) +#define bFM4_QPRC1_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2210UL)) +#define bFM_QPRC1_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2214UL)) +#define bFM4_QPRC1_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2214UL)) + +#define bFM_QPRC1_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2290UL)) +#define bFM4_QPRC1_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2290UL)) +#define bFM_QPRC1_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2294UL)) +#define bFM4_QPRC1_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2294UL)) + +#define bFM_QPRC1_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2310UL)) +#define bFM4_QPRC1_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2310UL)) +#define bFM_QPRC1_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2314UL)) +#define bFM4_QPRC1_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2314UL)) + + +/******************************************************************************* +* QPRC Registers QPRC2 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC2_QCR_PSTP *((volatile uint8_t *)(0x424C1310UL)) +#define bFM4_QPRC2_QCR_PSTP *((volatile uint8_t *)(0x424C1310UL)) +#define bFM_QPRC2_QCR_CGSC *((volatile uint8_t *)(0x424C1314UL)) +#define bFM4_QPRC2_QCR_CGSC *((volatile uint8_t *)(0x424C1314UL)) +#define bFM_QPRC2_QCR_RSEL *((volatile uint8_t *)(0x424C1318UL)) +#define bFM4_QPRC2_QCR_RSEL *((volatile uint8_t *)(0x424C1318UL)) +#define bFM_QPRC2_QCR_SWAP *((volatile uint8_t *)(0x424C131CUL)) +#define bFM4_QPRC2_QCR_SWAP *((volatile uint8_t *)(0x424C131CUL)) + +#define bFM_QPRC2_QECR_ORNGMD *((volatile uint8_t *)(0x424C1380UL)) +#define bFM4_QPRC2_QECR_ORNGMD *((volatile uint8_t *)(0x424C1380UL)) +#define bFM_QPRC2_QECR_ORNGF *((volatile uint8_t *)(0x424C1384UL)) +#define bFM4_QPRC2_QECR_ORNGF *((volatile uint8_t *)(0x424C1384UL)) +#define bFM_QPRC2_QECR_ORNGIE *((volatile uint8_t *)(0x424C1388UL)) +#define bFM4_QPRC2_QECR_ORNGIE *((volatile uint8_t *)(0x424C1388UL)) +#define bFM_QPRC2_QECR_PEC *((volatile uint8_t *)(0x424C138CUL)) +#define bFM4_QPRC2_QECR_PEC *((volatile uint8_t *)(0x424C138CUL)) + +#define bFM_QPRC2_QICRH_CDCIE *((volatile uint8_t *)(0x424C12A0UL)) +#define bFM4_QPRC2_QICRH_CDCIE *((volatile uint8_t *)(0x424C12A0UL)) +#define bFM_QPRC2_QICRH_CDCF *((volatile uint8_t *)(0x424C12A4UL)) +#define bFM4_QPRC2_QICRH_CDCF *((volatile uint8_t *)(0x424C12A4UL)) +#define bFM_QPRC2_QICRH_DIRPC *((volatile uint8_t *)(0x424C12A8UL)) +#define bFM4_QPRC2_QICRH_DIRPC *((volatile uint8_t *)(0x424C12A8UL)) +#define bFM_QPRC2_QICRH_DIROU *((volatile uint8_t *)(0x424C12ACUL)) +#define bFM4_QPRC2_QICRH_DIROU *((volatile uint8_t *)(0x424C12ACUL)) +#define bFM_QPRC2_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C12B0UL)) +#define bFM4_QPRC2_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C12B0UL)) +#define bFM_QPRC2_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C12B4UL)) +#define bFM4_QPRC2_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C12B4UL)) + +#define bFM_QPRC2_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1280UL)) +#define bFM4_QPRC2_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1280UL)) +#define bFM_QPRC2_QICRL_QPCMF *((volatile uint8_t *)(0x424C1284UL)) +#define bFM4_QPRC2_QICRL_QPCMF *((volatile uint8_t *)(0x424C1284UL)) +#define bFM_QPRC2_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1288UL)) +#define bFM4_QPRC2_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1288UL)) +#define bFM_QPRC2_QICRL_QPRCMF *((volatile uint8_t *)(0x424C128CUL)) +#define bFM4_QPRC2_QICRL_QPRCMF *((volatile uint8_t *)(0x424C128CUL)) +#define bFM_QPRC2_QICRL_OUZIE *((volatile uint8_t *)(0x424C1290UL)) +#define bFM4_QPRC2_QICRL_OUZIE *((volatile uint8_t *)(0x424C1290UL)) +#define bFM_QPRC2_QICRL_UFDF *((volatile uint8_t *)(0x424C1294UL)) +#define bFM4_QPRC2_QICRL_UFDF *((volatile uint8_t *)(0x424C1294UL)) +#define bFM_QPRC2_QICRL_OFDF *((volatile uint8_t *)(0x424C1298UL)) +#define bFM4_QPRC2_QICRL_OFDF *((volatile uint8_t *)(0x424C1298UL)) +#define bFM_QPRC2_QICRL_ZIIF *((volatile uint8_t *)(0x424C129CUL)) +#define bFM4_QPRC2_QICRL_ZIIF *((volatile uint8_t *)(0x424C129CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC2_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC2_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2410UL)) +#define bFM4_QPRC2_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2410UL)) +#define bFM_QPRC2_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2414UL)) +#define bFM4_QPRC2_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2414UL)) + +#define bFM_QPRC2_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2490UL)) +#define bFM4_QPRC2_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2490UL)) +#define bFM_QPRC2_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2494UL)) +#define bFM4_QPRC2_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2494UL)) + +#define bFM_QPRC2_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2510UL)) +#define bFM4_QPRC2_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2510UL)) +#define bFM_QPRC2_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2514UL)) +#define bFM4_QPRC2_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2514UL)) + + +/******************************************************************************* +* QPRC Registers QPRC3 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC3_QCR_PSTP *((volatile uint8_t *)(0x424C1B10UL)) +#define bFM4_QPRC3_QCR_PSTP *((volatile uint8_t *)(0x424C1B10UL)) +#define bFM_QPRC3_QCR_CGSC *((volatile uint8_t *)(0x424C1B14UL)) +#define bFM4_QPRC3_QCR_CGSC *((volatile uint8_t *)(0x424C1B14UL)) +#define bFM_QPRC3_QCR_RSEL *((volatile uint8_t *)(0x424C1B18UL)) +#define bFM4_QPRC3_QCR_RSEL *((volatile uint8_t *)(0x424C1B18UL)) +#define bFM_QPRC3_QCR_SWAP *((volatile uint8_t *)(0x424C1B1CUL)) +#define bFM4_QPRC3_QCR_SWAP *((volatile uint8_t *)(0x424C1B1CUL)) + +#define bFM_QPRC3_QECR_ORNGMD *((volatile uint8_t *)(0x424C1B80UL)) +#define bFM4_QPRC3_QECR_ORNGMD *((volatile uint8_t *)(0x424C1B80UL)) +#define bFM_QPRC3_QECR_ORNGF *((volatile uint8_t *)(0x424C1B84UL)) +#define bFM4_QPRC3_QECR_ORNGF *((volatile uint8_t *)(0x424C1B84UL)) +#define bFM_QPRC3_QECR_ORNGIE *((volatile uint8_t *)(0x424C1B88UL)) +#define bFM4_QPRC3_QECR_ORNGIE *((volatile uint8_t *)(0x424C1B88UL)) +#define bFM_QPRC3_QECR_PEC *((volatile uint8_t *)(0x424C1B8CUL)) +#define bFM4_QPRC3_QECR_PEC *((volatile uint8_t *)(0x424C1B8CUL)) + +#define bFM_QPRC3_QICRH_CDCIE *((volatile uint8_t *)(0x424C1AA0UL)) +#define bFM4_QPRC3_QICRH_CDCIE *((volatile uint8_t *)(0x424C1AA0UL)) +#define bFM_QPRC3_QICRH_CDCF *((volatile uint8_t *)(0x424C1AA4UL)) +#define bFM4_QPRC3_QICRH_CDCF *((volatile uint8_t *)(0x424C1AA4UL)) +#define bFM_QPRC3_QICRH_DIRPC *((volatile uint8_t *)(0x424C1AA8UL)) +#define bFM4_QPRC3_QICRH_DIRPC *((volatile uint8_t *)(0x424C1AA8UL)) +#define bFM_QPRC3_QICRH_DIROU *((volatile uint8_t *)(0x424C1AACUL)) +#define bFM4_QPRC3_QICRH_DIROU *((volatile uint8_t *)(0x424C1AACUL)) +#define bFM_QPRC3_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C1AB0UL)) +#define bFM4_QPRC3_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C1AB0UL)) +#define bFM_QPRC3_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C1AB4UL)) +#define bFM4_QPRC3_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C1AB4UL)) + +#define bFM_QPRC3_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1A80UL)) +#define bFM4_QPRC3_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1A80UL)) +#define bFM_QPRC3_QICRL_QPCMF *((volatile uint8_t *)(0x424C1A84UL)) +#define bFM4_QPRC3_QICRL_QPCMF *((volatile uint8_t *)(0x424C1A84UL)) +#define bFM_QPRC3_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1A88UL)) +#define bFM4_QPRC3_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1A88UL)) +#define bFM_QPRC3_QICRL_QPRCMF *((volatile uint8_t *)(0x424C1A8CUL)) +#define bFM4_QPRC3_QICRL_QPRCMF *((volatile uint8_t *)(0x424C1A8CUL)) +#define bFM_QPRC3_QICRL_OUZIE *((volatile uint8_t *)(0x424C1A90UL)) +#define bFM4_QPRC3_QICRL_OUZIE *((volatile uint8_t *)(0x424C1A90UL)) +#define bFM_QPRC3_QICRL_UFDF *((volatile uint8_t *)(0x424C1A94UL)) +#define bFM4_QPRC3_QICRL_UFDF *((volatile uint8_t *)(0x424C1A94UL)) +#define bFM_QPRC3_QICRL_OFDF *((volatile uint8_t *)(0x424C1A98UL)) +#define bFM4_QPRC3_QICRL_OFDF *((volatile uint8_t *)(0x424C1A98UL)) +#define bFM_QPRC3_QICRL_ZIIF *((volatile uint8_t *)(0x424C1A9CUL)) +#define bFM4_QPRC3_QICRL_ZIIF *((volatile uint8_t *)(0x424C1A9CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC3_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC3_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2610UL)) +#define bFM4_QPRC3_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2610UL)) +#define bFM_QPRC3_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2614UL)) +#define bFM4_QPRC3_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2614UL)) + +#define bFM_QPRC3_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2690UL)) +#define bFM4_QPRC3_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2690UL)) +#define bFM_QPRC3_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2694UL)) +#define bFM4_QPRC3_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2694UL)) + +#define bFM_QPRC3_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2710UL)) +#define bFM4_QPRC3_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2710UL)) +#define bFM_QPRC3_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2714UL)) +#define bFM4_QPRC3_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2714UL)) + + +/******************************************************************************* +* RTC Registers RTC +* Bitband Section +*******************************************************************************/ +#define bFM_RTC_ALMOR_TAMO *((volatile uint8_t *)(0x42762890UL)) +#define bFM4_RTC_ALMOR_TAMO *((volatile uint8_t *)(0x42762890UL)) + +#define bFM_RTC_EWKUP_WUP0 *((volatile uint8_t *)(0x42763180UL)) +#define bFM4_RTC_EWKUP_WUP0 *((volatile uint8_t *)(0x42763180UL)) + +#define bFM_RTC_HIBRST_HIBRST *((volatile uint8_t *)(0x42763300UL)) +#define bFM4_RTC_HIBRST_HIBRST *((volatile uint8_t *)(0x42763300UL)) + +#define bFM_RTC_VBDDR_VDDR0 *((volatile uint8_t *)(0x42763480UL)) +#define bFM4_RTC_VBDDR_VDDR0 *((volatile uint8_t *)(0x42763480UL)) +#define bFM_RTC_VBDDR_VDDR1 *((volatile uint8_t *)(0x42763484UL)) +#define bFM4_RTC_VBDDR_VDDR1 *((volatile uint8_t *)(0x42763484UL)) +#define bFM_RTC_VBDDR_VDDR2 *((volatile uint8_t *)(0x42763488UL)) +#define bFM4_RTC_VBDDR_VDDR2 *((volatile uint8_t *)(0x42763488UL)) +#define bFM_RTC_VBDDR_VDDR3 *((volatile uint8_t *)(0x4276348CUL)) +#define bFM4_RTC_VBDDR_VDDR3 *((volatile uint8_t *)(0x4276348CUL)) + +#define bFM_RTC_VBDIR_VDIR0 *((volatile uint8_t *)(0x42763500UL)) +#define bFM4_RTC_VBDIR_VDIR0 *((volatile uint8_t *)(0x42763500UL)) +#define bFM_RTC_VBDIR_VDIR1 *((volatile uint8_t *)(0x42763504UL)) +#define bFM4_RTC_VBDIR_VDIR1 *((volatile uint8_t *)(0x42763504UL)) +#define bFM_RTC_VBDIR_VDIR2 *((volatile uint8_t *)(0x42763508UL)) +#define bFM4_RTC_VBDIR_VDIR2 *((volatile uint8_t *)(0x42763508UL)) +#define bFM_RTC_VBDIR_VDIR3 *((volatile uint8_t *)(0x4276350CUL)) +#define bFM4_RTC_VBDIR_VDIR3 *((volatile uint8_t *)(0x4276350CUL)) + +#define bFM_RTC_VBDOR_VDOR0 *((volatile uint8_t *)(0x42763580UL)) +#define bFM4_RTC_VBDOR_VDOR0 *((volatile uint8_t *)(0x42763580UL)) +#define bFM_RTC_VBDOR_VDOR1 *((volatile uint8_t *)(0x42763584UL)) +#define bFM4_RTC_VBDOR_VDOR1 *((volatile uint8_t *)(0x42763584UL)) +#define bFM_RTC_VBDOR_VDOR2 *((volatile uint8_t *)(0x42763588UL)) +#define bFM4_RTC_VBDOR_VDOR2 *((volatile uint8_t *)(0x42763588UL)) +#define bFM_RTC_VBDOR_VDOR3 *((volatile uint8_t *)(0x4276358CUL)) +#define bFM4_RTC_VBDOR_VDOR3 *((volatile uint8_t *)(0x4276358CUL)) + +#define bFM_RTC_VBPCR_VPCR0 *((volatile uint8_t *)(0x42763400UL)) +#define bFM4_RTC_VBPCR_VPCR0 *((volatile uint8_t *)(0x42763400UL)) +#define bFM_RTC_VBPCR_VPCR1 *((volatile uint8_t *)(0x42763404UL)) +#define bFM4_RTC_VBPCR_VPCR1 *((volatile uint8_t *)(0x42763404UL)) +#define bFM_RTC_VBPCR_VPCR2 *((volatile uint8_t *)(0x42763408UL)) +#define bFM4_RTC_VBPCR_VPCR2 *((volatile uint8_t *)(0x42763408UL)) +#define bFM_RTC_VBPCR_VPCR3 *((volatile uint8_t *)(0x4276340CUL)) +#define bFM4_RTC_VBPCR_VPCR3 *((volatile uint8_t *)(0x4276340CUL)) + +#define bFM_RTC_VBPFR_VPFR0 *((volatile uint8_t *)(0x42763380UL)) +#define bFM4_RTC_VBPFR_VPFR0 *((volatile uint8_t *)(0x42763380UL)) +#define bFM_RTC_VBPFR_VPFR1 *((volatile uint8_t *)(0x42763384UL)) +#define bFM4_RTC_VBPFR_VPFR1 *((volatile uint8_t *)(0x42763384UL)) +#define bFM_RTC_VBPFR_VPFR2 *((volatile uint8_t *)(0x42763388UL)) +#define bFM4_RTC_VBPFR_VPFR2 *((volatile uint8_t *)(0x42763388UL)) +#define bFM_RTC_VBPFR_VPFR3 *((volatile uint8_t *)(0x4276338CUL)) +#define bFM4_RTC_VBPFR_VPFR3 *((volatile uint8_t *)(0x4276338CUL)) + +#define bFM_RTC_VBPZR_VPZR0 *((volatile uint8_t *)(0x42763600UL)) +#define bFM4_RTC_VBPZR_VPZR0 *((volatile uint8_t *)(0x42763600UL)) +#define bFM_RTC_VBPZR_VPZR1 *((volatile uint8_t *)(0x42763604UL)) +#define bFM4_RTC_VBPZR_VPZR1 *((volatile uint8_t *)(0x42763604UL)) + +#define bFM_RTC_VDET_PON *((volatile uint8_t *)(0x4276321CUL)) +#define bFM4_RTC_VDET_PON *((volatile uint8_t *)(0x4276321CUL)) + +#define bFM_RTC_WTCALEN_WTCALEN *((volatile uint8_t *)(0x42762C00UL)) +#define bFM4_RTC_WTCALEN_WTCALEN *((volatile uint8_t *)(0x42762C00UL)) + +#define bFM_RTC_WTCOSEL_WTCOSEL *((volatile uint8_t *)(0x42762E00UL)) +#define bFM4_RTC_WTCOSEL_WTCOSEL *((volatile uint8_t *)(0x42762E00UL)) + +#define bFM_RTC_WTCR10_ST *((volatile uint8_t *)(0x42762000UL)) +#define bFM4_RTC_WTCR10_ST *((volatile uint8_t *)(0x42762000UL)) +#define bFM_RTC_WTCR10_RUN *((volatile uint8_t *)(0x42762008UL)) +#define bFM4_RTC_WTCR10_RUN *((volatile uint8_t *)(0x42762008UL)) +#define bFM_RTC_WTCR10_SRST *((volatile uint8_t *)(0x4276200CUL)) +#define bFM4_RTC_WTCR10_SRST *((volatile uint8_t *)(0x4276200CUL)) +#define bFM_RTC_WTCR10_SCST *((volatile uint8_t *)(0x42762010UL)) +#define bFM4_RTC_WTCR10_SCST *((volatile uint8_t *)(0x42762010UL)) +#define bFM_RTC_WTCR10_SCRST *((volatile uint8_t *)(0x42762014UL)) +#define bFM4_RTC_WTCR10_SCRST *((volatile uint8_t *)(0x42762014UL)) +#define bFM_RTC_WTCR10_BUSY *((volatile uint8_t *)(0x42762018UL)) +#define bFM4_RTC_WTCR10_BUSY *((volatile uint8_t *)(0x42762018UL)) +#define bFM_RTC_WTCR10_TRANS *((volatile uint8_t *)(0x4276201CUL)) +#define bFM4_RTC_WTCR10_TRANS *((volatile uint8_t *)(0x4276201CUL)) + +#define bFM_RTC_WTCR11_MIEN *((volatile uint8_t *)(0x42762080UL)) +#define bFM4_RTC_WTCR11_MIEN *((volatile uint8_t *)(0x42762080UL)) +#define bFM_RTC_WTCR11_HEN *((volatile uint8_t *)(0x42762084UL)) +#define bFM4_RTC_WTCR11_HEN *((volatile uint8_t *)(0x42762084UL)) +#define bFM_RTC_WTCR11_DEN *((volatile uint8_t *)(0x42762088UL)) +#define bFM4_RTC_WTCR11_DEN *((volatile uint8_t *)(0x42762088UL)) +#define bFM_RTC_WTCR11_MOEN *((volatile uint8_t *)(0x4276208CUL)) +#define bFM4_RTC_WTCR11_MOEN *((volatile uint8_t *)(0x4276208CUL)) +#define bFM_RTC_WTCR11_YEN *((volatile uint8_t *)(0x42762090UL)) +#define bFM4_RTC_WTCR11_YEN *((volatile uint8_t *)(0x42762090UL)) + +#define bFM_RTC_WTCR12_INTSSI *((volatile uint8_t *)(0x42762100UL)) +#define bFM4_RTC_WTCR12_INTSSI *((volatile uint8_t *)(0x42762100UL)) +#define bFM_RTC_WTCR12_INTSI *((volatile uint8_t *)(0x42762104UL)) +#define bFM4_RTC_WTCR12_INTSI *((volatile uint8_t *)(0x42762104UL)) +#define bFM_RTC_WTCR12_INTMI *((volatile uint8_t *)(0x42762108UL)) +#define bFM4_RTC_WTCR12_INTMI *((volatile uint8_t *)(0x42762108UL)) +#define bFM_RTC_WTCR12_INTHI *((volatile uint8_t *)(0x4276210CUL)) +#define bFM4_RTC_WTCR12_INTHI *((volatile uint8_t *)(0x4276210CUL)) +#define bFM_RTC_WTCR12_INTTMI *((volatile uint8_t *)(0x42762110UL)) +#define bFM4_RTC_WTCR12_INTTMI *((volatile uint8_t *)(0x42762110UL)) +#define bFM_RTC_WTCR12_INTALI *((volatile uint8_t *)(0x42762114UL)) +#define bFM4_RTC_WTCR12_INTALI *((volatile uint8_t *)(0x42762114UL)) +#define bFM_RTC_WTCR12_INTERI *((volatile uint8_t *)(0x42762118UL)) +#define bFM4_RTC_WTCR12_INTERI *((volatile uint8_t *)(0x42762118UL)) +#define bFM_RTC_WTCR12_INTCRI *((volatile uint8_t *)(0x4276211CUL)) +#define bFM4_RTC_WTCR12_INTCRI *((volatile uint8_t *)(0x4276211CUL)) + +#define bFM_RTC_WTCR13_INTSSIE *((volatile uint8_t *)(0x42762180UL)) +#define bFM4_RTC_WTCR13_INTSSIE *((volatile uint8_t *)(0x42762180UL)) +#define bFM_RTC_WTCR13_INTSIE *((volatile uint8_t *)(0x42762184UL)) +#define bFM4_RTC_WTCR13_INTSIE *((volatile uint8_t *)(0x42762184UL)) +#define bFM_RTC_WTCR13_INTMIE *((volatile uint8_t *)(0x42762188UL)) +#define bFM4_RTC_WTCR13_INTMIE *((volatile uint8_t *)(0x42762188UL)) +#define bFM_RTC_WTCR13_INTHIE *((volatile uint8_t *)(0x4276218CUL)) +#define bFM4_RTC_WTCR13_INTHIE *((volatile uint8_t *)(0x4276218CUL)) +#define bFM_RTC_WTCR13_INTTMIE *((volatile uint8_t *)(0x42762190UL)) +#define bFM4_RTC_WTCR13_INTTMIE *((volatile uint8_t *)(0x42762190UL)) +#define bFM_RTC_WTCR13_INTALIE *((volatile uint8_t *)(0x42762194UL)) +#define bFM4_RTC_WTCR13_INTALIE *((volatile uint8_t *)(0x42762194UL)) +#define bFM_RTC_WTCR13_INTERIE *((volatile uint8_t *)(0x42762198UL)) +#define bFM4_RTC_WTCR13_INTERIE *((volatile uint8_t *)(0x42762198UL)) +#define bFM_RTC_WTCR13_INTCRIE *((volatile uint8_t *)(0x4276219CUL)) +#define bFM4_RTC_WTCR13_INTCRIE *((volatile uint8_t *)(0x4276219CUL)) + +#define bFM_RTC_WTCR20_CREAD *((volatile uint8_t *)(0x42762200UL)) +#define bFM4_RTC_WTCR20_CREAD *((volatile uint8_t *)(0x42762200UL)) +#define bFM_RTC_WTCR20_CWRITE *((volatile uint8_t *)(0x42762204UL)) +#define bFM4_RTC_WTCR20_CWRITE *((volatile uint8_t *)(0x42762204UL)) +#define bFM_RTC_WTCR20_BREAD *((volatile uint8_t *)(0x42762208UL)) +#define bFM4_RTC_WTCR20_BREAD *((volatile uint8_t *)(0x42762208UL)) +#define bFM_RTC_WTCR20_BWRITE *((volatile uint8_t *)(0x4276220CUL)) +#define bFM4_RTC_WTCR20_BWRITE *((volatile uint8_t *)(0x4276220CUL)) +#define bFM_RTC_WTCR20_PREAD *((volatile uint8_t *)(0x42762210UL)) +#define bFM4_RTC_WTCR20_PREAD *((volatile uint8_t *)(0x42762210UL)) +#define bFM_RTC_WTCR20_PWRITE *((volatile uint8_t *)(0x42762214UL)) +#define bFM4_RTC_WTCR20_PWRITE *((volatile uint8_t *)(0x42762214UL)) + +#define bFM_RTC_WTCR21_TMST *((volatile uint8_t *)(0x42762280UL)) +#define bFM4_RTC_WTCR21_TMST *((volatile uint8_t *)(0x42762280UL)) +#define bFM_RTC_WTCR21_TMEN *((volatile uint8_t *)(0x42762284UL)) +#define bFM4_RTC_WTCR21_TMEN *((volatile uint8_t *)(0x42762284UL)) +#define bFM_RTC_WTCR21_TMRUN *((volatile uint8_t *)(0x42762288UL)) +#define bFM4_RTC_WTCR21_TMRUN *((volatile uint8_t *)(0x42762288UL)) + +#define bFM_RTC_WTDIVEN_WTDIVEN *((volatile uint8_t *)(0x42762D00UL)) +#define bFM4_RTC_WTDIVEN_WTDIVEN *((volatile uint8_t *)(0x42762D00UL)) +#define bFM_RTC_WTDIVEN_WTDIVRDY *((volatile uint8_t *)(0x42762D04UL)) +#define bFM4_RTC_WTDIVEN_WTDIVRDY *((volatile uint8_t *)(0x42762D04UL)) + +#define bFM_RTC_WTMOR_TMO *((volatile uint8_t *)(0x42762610UL)) +#define bFM4_RTC_WTMOR_TMO *((volatile uint8_t *)(0x42762610UL)) + +#define bFM_RTC_WTOSCCNT_SOSCEX *((volatile uint8_t *)(0x42762F00UL)) +#define bFM4_RTC_WTOSCCNT_SOSCEX *((volatile uint8_t *)(0x42762F00UL)) +#define bFM_RTC_WTOSCCNT_SOSCNTL *((volatile uint8_t *)(0x42762F04UL)) +#define bFM4_RTC_WTOSCCNT_SOSCNTL *((volatile uint8_t *)(0x42762F04UL)) + + +/******************************************************************************* +* SBSSR Registers SBSSR +* Bitband Section +*******************************************************************************/ +#define bFM_SBSSR_BTSSSR_SSSR0 *((volatile uint8_t *)(0x424BFF80UL)) +#define bFM4_SBSSR_BTSSSR_SSSR0 *((volatile uint8_t *)(0x424BFF80UL)) +#define bFM_SBSSR_BTSSSR_SSSR1 *((volatile uint8_t *)(0x424BFF84UL)) +#define bFM4_SBSSR_BTSSSR_SSSR1 *((volatile uint8_t *)(0x424BFF84UL)) +#define bFM_SBSSR_BTSSSR_SSSR2 *((volatile uint8_t *)(0x424BFF88UL)) +#define bFM4_SBSSR_BTSSSR_SSSR2 *((volatile uint8_t *)(0x424BFF88UL)) +#define bFM_SBSSR_BTSSSR_SSSR3 *((volatile uint8_t *)(0x424BFF8CUL)) +#define bFM4_SBSSR_BTSSSR_SSSR3 *((volatile uint8_t *)(0x424BFF8CUL)) +#define bFM_SBSSR_BTSSSR_SSSR4 *((volatile uint8_t *)(0x424BFF90UL)) +#define bFM4_SBSSR_BTSSSR_SSSR4 *((volatile uint8_t *)(0x424BFF90UL)) +#define bFM_SBSSR_BTSSSR_SSSR5 *((volatile uint8_t *)(0x424BFF94UL)) +#define bFM4_SBSSR_BTSSSR_SSSR5 *((volatile uint8_t *)(0x424BFF94UL)) +#define bFM_SBSSR_BTSSSR_SSSR6 *((volatile uint8_t *)(0x424BFF98UL)) +#define bFM4_SBSSR_BTSSSR_SSSR6 *((volatile uint8_t *)(0x424BFF98UL)) +#define bFM_SBSSR_BTSSSR_SSSR7 *((volatile uint8_t *)(0x424BFF9CUL)) +#define bFM4_SBSSR_BTSSSR_SSSR7 *((volatile uint8_t *)(0x424BFF9CUL)) +#define bFM_SBSSR_BTSSSR_SSSR8 *((volatile uint8_t *)(0x424BFFA0UL)) +#define bFM4_SBSSR_BTSSSR_SSSR8 *((volatile uint8_t *)(0x424BFFA0UL)) +#define bFM_SBSSR_BTSSSR_SSSR9 *((volatile uint8_t *)(0x424BFFA4UL)) +#define bFM4_SBSSR_BTSSSR_SSSR9 *((volatile uint8_t *)(0x424BFFA4UL)) +#define bFM_SBSSR_BTSSSR_SSSR10 *((volatile uint8_t *)(0x424BFFA8UL)) +#define bFM4_SBSSR_BTSSSR_SSSR10 *((volatile uint8_t *)(0x424BFFA8UL)) +#define bFM_SBSSR_BTSSSR_SSSR11 *((volatile uint8_t *)(0x424BFFACUL)) +#define bFM4_SBSSR_BTSSSR_SSSR11 *((volatile uint8_t *)(0x424BFFACUL)) +#define bFM_SBSSR_BTSSSR_SSSR12 *((volatile uint8_t *)(0x424BFFB0UL)) +#define bFM4_SBSSR_BTSSSR_SSSR12 *((volatile uint8_t *)(0x424BFFB0UL)) +#define bFM_SBSSR_BTSSSR_SSSR13 *((volatile uint8_t *)(0x424BFFB4UL)) +#define bFM4_SBSSR_BTSSSR_SSSR13 *((volatile uint8_t *)(0x424BFFB4UL)) +#define bFM_SBSSR_BTSSSR_SSSR14 *((volatile uint8_t *)(0x424BFFB8UL)) +#define bFM4_SBSSR_BTSSSR_SSSR14 *((volatile uint8_t *)(0x424BFFB8UL)) +#define bFM_SBSSR_BTSSSR_SSSR15 *((volatile uint8_t *)(0x424BFFBCUL)) +#define bFM4_SBSSR_BTSSSR_SSSR15 *((volatile uint8_t *)(0x424BFFBCUL)) + + +/******************************************************************************* +* SDIF Registers SDIF +* Bitband Section +*******************************************************************************/ +#define bFM_SDIF_ADMAEST_ADMALENME *((volatile uint8_t *)(0x42DC0A88UL)) +#define bFM4_SDIF_ADMAEST_ADMALENME *((volatile uint8_t *)(0x42DC0A88UL)) + +#define bFM_SDIF_AHBCFGL_SINEN *((volatile uint8_t *)(0x42DC200CUL)) +#define bFM4_SDIF_AHBCFGL_SINEN *((volatile uint8_t *)(0x42DC200CUL)) +#define bFM_SDIF_AHBCFGL_BSLOCK *((volatile uint8_t *)(0x42DC2010UL)) +#define bFM4_SDIF_AHBCFGL_BSLOCK *((volatile uint8_t *)(0x42DC2010UL)) +#define bFM_SDIF_AHBCFGL_BSLOCKSEL *((volatile uint8_t *)(0x42DC2014UL)) +#define bFM4_SDIF_AHBCFGL_BSLOCKSEL *((volatile uint8_t *)(0x42DC2014UL)) +#define bFM_SDIF_AHBCFGL_ENDIANSEL *((volatile uint8_t *)(0x42DC2018UL)) +#define bFM4_SDIF_AHBCFGL_ENDIANSEL *((volatile uint8_t *)(0x42DC2018UL)) + +#define bFM_SDIF_CAPBLTY0_TOCLKUNIT *((volatile uint8_t *)(0x42DC081CUL)) +#define bFM4_SDIF_CAPBLTY0_TOCLKUNIT *((volatile uint8_t *)(0x42DC081CUL)) + +#define bFM_SDIF_CAPBLTY1_EMBD8BIT *((volatile uint8_t *)(0x42DC0848UL)) +#define bFM4_SDIF_CAPBLTY1_EMBD8BIT *((volatile uint8_t *)(0x42DC0848UL)) +#define bFM_SDIF_CAPBLTY1_ADMA2SPT *((volatile uint8_t *)(0x42DC084CUL)) +#define bFM4_SDIF_CAPBLTY1_ADMA2SPT *((volatile uint8_t *)(0x42DC084CUL)) +#define bFM_SDIF_CAPBLTY1_HGHSPDSPT *((volatile uint8_t *)(0x42DC0854UL)) +#define bFM4_SDIF_CAPBLTY1_HGHSPDSPT *((volatile uint8_t *)(0x42DC0854UL)) +#define bFM_SDIF_CAPBLTY1_SDMASPT *((volatile uint8_t *)(0x42DC0858UL)) +#define bFM4_SDIF_CAPBLTY1_SDMASPT *((volatile uint8_t *)(0x42DC0858UL)) +#define bFM_SDIF_CAPBLTY1_LWPWRSPT *((volatile uint8_t *)(0x42DC085CUL)) +#define bFM4_SDIF_CAPBLTY1_LWPWRSPT *((volatile uint8_t *)(0x42DC085CUL)) +#define bFM_SDIF_CAPBLTY1_V33SPT *((volatile uint8_t *)(0x42DC0860UL)) +#define bFM4_SDIF_CAPBLTY1_V33SPT *((volatile uint8_t *)(0x42DC0860UL)) +#define bFM_SDIF_CAPBLTY1_V30SPT *((volatile uint8_t *)(0x42DC0864UL)) +#define bFM4_SDIF_CAPBLTY1_V30SPT *((volatile uint8_t *)(0x42DC0864UL)) +#define bFM_SDIF_CAPBLTY1_V18SPT *((volatile uint8_t *)(0x42DC0868UL)) +#define bFM4_SDIF_CAPBLTY1_V18SPT *((volatile uint8_t *)(0x42DC0868UL)) +#define bFM_SDIF_CAPBLTY1_BUS64SPT *((volatile uint8_t *)(0x42DC0870UL)) +#define bFM4_SDIF_CAPBLTY1_BUS64SPT *((volatile uint8_t *)(0x42DC0870UL)) +#define bFM_SDIF_CAPBLTY1_ASYINTSPT *((volatile uint8_t *)(0x42DC0874UL)) +#define bFM4_SDIF_CAPBLTY1_ASYINTSPT *((volatile uint8_t *)(0x42DC0874UL)) + +#define bFM_SDIF_CAPBLTY2_SDR50SPT *((volatile uint8_t *)(0x42DC0880UL)) +#define bFM4_SDIF_CAPBLTY2_SDR50SPT *((volatile uint8_t *)(0x42DC0880UL)) +#define bFM_SDIF_CAPBLTY2_SDR104SPT *((volatile uint8_t *)(0x42DC0884UL)) +#define bFM4_SDIF_CAPBLTY2_SDR104SPT *((volatile uint8_t *)(0x42DC0884UL)) +#define bFM_SDIF_CAPBLTY2_DDR50SPT *((volatile uint8_t *)(0x42DC0888UL)) +#define bFM4_SDIF_CAPBLTY2_DDR50SPT *((volatile uint8_t *)(0x42DC0888UL)) +#define bFM_SDIF_CAPBLTY2_DRVTPASPT *((volatile uint8_t *)(0x42DC0890UL)) +#define bFM4_SDIF_CAPBLTY2_DRVTPASPT *((volatile uint8_t *)(0x42DC0890UL)) +#define bFM_SDIF_CAPBLTY2_DRVTPCSPT *((volatile uint8_t *)(0x42DC0894UL)) +#define bFM4_SDIF_CAPBLTY2_DRVTPCSPT *((volatile uint8_t *)(0x42DC0894UL)) +#define bFM_SDIF_CAPBLTY2_DRVTPDSPT *((volatile uint8_t *)(0x42DC0898UL)) +#define bFM4_SDIF_CAPBLTY2_DRVTPDSPT *((volatile uint8_t *)(0x42DC0898UL)) +#define bFM_SDIF_CAPBLTY2_USETNSDR50 *((volatile uint8_t *)(0x42DC08B4UL)) +#define bFM4_SDIF_CAPBLTY2_USETNSDR50 *((volatile uint8_t *)(0x42DC08B4UL)) + +#define bFM_SDIF_FEACEST_FEVNT12ND *((volatile uint8_t *)(0x42DC0A00UL)) +#define bFM4_SDIF_FEACEST_FEVNT12ND *((volatile uint8_t *)(0x42DC0A00UL)) +#define bFM_SDIF_FEACEST_FEVNTTO *((volatile uint8_t *)(0x42DC0A04UL)) +#define bFM4_SDIF_FEACEST_FEVNTTO *((volatile uint8_t *)(0x42DC0A04UL)) +#define bFM_SDIF_FEACEST_FEVNTCRC *((volatile uint8_t *)(0x42DC0A08UL)) +#define bFM4_SDIF_FEACEST_FEVNTCRC *((volatile uint8_t *)(0x42DC0A08UL)) +#define bFM_SDIF_FEACEST_FEVNTEB *((volatile uint8_t *)(0x42DC0A0CUL)) +#define bFM4_SDIF_FEACEST_FEVNTEB *((volatile uint8_t *)(0x42DC0A0CUL)) +#define bFM_SDIF_FEACEST_FEVNTIDX *((volatile uint8_t *)(0x42DC0A10UL)) +#define bFM4_SDIF_FEACEST_FEVNTIDX *((volatile uint8_t *)(0x42DC0A10UL)) +#define bFM_SDIF_FEACEST_FEVNTCMD12 *((volatile uint8_t *)(0x42DC0A1CUL)) +#define bFM4_SDIF_FEACEST_FEVNTCMD12 *((volatile uint8_t *)(0x42DC0A1CUL)) + +#define bFM_SDIF_MCWIRQC0_WTIRQEN *((volatile uint8_t *)(0x42DC2500UL)) +#define bFM4_SDIF_MCWIRQC0_WTIRQEN *((volatile uint8_t *)(0x42DC2500UL)) +#define bFM_SDIF_MCWIRQC0_WTIRQST *((volatile uint8_t *)(0x42DC2504UL)) +#define bFM4_SDIF_MCWIRQC0_WTIRQST *((volatile uint8_t *)(0x42DC2504UL)) + +#define bFM_SDIF_MMCSDCH_BTACKENMMC *((volatile uint8_t *)(0x42DC24C0UL)) +#define bFM4_SDIF_MMCSDCH_BTACKENMMC *((volatile uint8_t *)(0x42DC24C0UL)) +#define bFM_SDIF_MMCSDCH_BTABTENMMC *((volatile uint8_t *)(0x42DC24C4UL)) +#define bFM4_SDIF_MMCSDCH_BTABTENMMC *((volatile uint8_t *)(0x42DC24C4UL)) +#define bFM_SDIF_MMCSDCH_BTMDENMMC *((volatile uint8_t *)(0x42DC24C8UL)) +#define bFM4_SDIF_MMCSDCH_BTMDENMMC *((volatile uint8_t *)(0x42DC24C8UL)) + +#define bFM_SDIF_MMCSDCL_LCKRSTESD *((volatile uint8_t *)(0x42DC2480UL)) +#define bFM4_SDIF_MMCSDCL_LCKRSTESD *((volatile uint8_t *)(0x42DC2480UL)) +#define bFM_SDIF_MMCSDCL_RSTMMC *((volatile uint8_t *)(0x42DC2484UL)) +#define bFM4_SDIF_MMCSDCL_RSTMMC *((volatile uint8_t *)(0x42DC2484UL)) +#define bFM_SDIF_MMCSDCL_VCCCTLMMC *((volatile uint8_t *)(0x42DC2488UL)) +#define bFM4_SDIF_MMCSDCL_VCCCTLMMC *((volatile uint8_t *)(0x42DC2488UL)) +#define bFM_SDIF_MMCSDCL_VCCQCTLMMC *((volatile uint8_t *)(0x42DC248CUL)) +#define bFM4_SDIF_MMCSDCL_VCCQCTLMMC *((volatile uint8_t *)(0x42DC248CUL)) +#define bFM_SDIF_MMCSDCL_MMCDDRSEL *((volatile uint8_t *)(0x42DC24A0UL)) +#define bFM4_SDIF_MMCSDCL_MMCDDRSEL *((volatile uint8_t *)(0x42DC24A0UL)) +#define bFM_SDIF_MMCSDCL_CMDDATDLY *((volatile uint8_t *)(0x42DC24A4UL)) +#define bFM4_SDIF_MMCSDCL_CMDDATDLY *((volatile uint8_t *)(0x42DC24A4UL)) + +#define bFM_SDIF_PSWISGEL_INT5MSSGEN *((volatile uint8_t *)(0x42DC2400UL)) +#define bFM4_SDIF_PSWISGEL_INT5MSSGEN *((volatile uint8_t *)(0x42DC2400UL)) +#define bFM_SDIF_PSWISGEL_INT1MSSGEN *((volatile uint8_t *)(0x42DC2404UL)) +#define bFM4_SDIF_PSWISGEL_INT1MSSGEN *((volatile uint8_t *)(0x42DC2404UL)) + +#define bFM_SDIF_PSWISTEL_INT5MSSTS *((volatile uint8_t *)(0x42DC2380UL)) +#define bFM4_SDIF_PSWISTEL_INT5MSSTS *((volatile uint8_t *)(0x42DC2380UL)) +#define bFM_SDIF_PSWISTEL_INT1MSSTS *((volatile uint8_t *)(0x42DC2384UL)) +#define bFM4_SDIF_PSWISTEL_INT1MSSTS *((volatile uint8_t *)(0x42DC2384UL)) + +#define bFM_SDIF_PSWISTL_INT5MS *((volatile uint8_t *)(0x42DC2300UL)) +#define bFM4_SDIF_PSWISTL_INT5MS *((volatile uint8_t *)(0x42DC2300UL)) +#define bFM_SDIF_PSWISTL_INT1MS *((volatile uint8_t *)(0x42DC2304UL)) +#define bFM4_SDIF_PSWISTL_INT1MS *((volatile uint8_t *)(0x42DC2304UL)) + +#define bFM_SDIF_SACMDEST_ACMD12NOEX *((volatile uint8_t *)(0x42DC0780UL)) +#define bFM4_SDIF_SACMDEST_ACMD12NOEX *((volatile uint8_t *)(0x42DC0780UL)) +#define bFM_SDIF_SACMDEST_ACMDTOERR *((volatile uint8_t *)(0x42DC0784UL)) +#define bFM4_SDIF_SACMDEST_ACMDTOERR *((volatile uint8_t *)(0x42DC0784UL)) +#define bFM_SDIF_SACMDEST_ACMDCRCERR *((volatile uint8_t *)(0x42DC0788UL)) +#define bFM4_SDIF_SACMDEST_ACMDCRCERR *((volatile uint8_t *)(0x42DC0788UL)) +#define bFM_SDIF_SACMDEST_ACMDEBERR *((volatile uint8_t *)(0x42DC078CUL)) +#define bFM4_SDIF_SACMDEST_ACMDEBERR *((volatile uint8_t *)(0x42DC078CUL)) +#define bFM_SDIF_SACMDEST_ACMDIDXERR *((volatile uint8_t *)(0x42DC0790UL)) +#define bFM4_SDIF_SACMDEST_ACMDIDXERR *((volatile uint8_t *)(0x42DC0790UL)) +#define bFM_SDIF_SACMDEST_CMDND12ERR *((volatile uint8_t *)(0x42DC079CUL)) +#define bFM4_SDIF_SACMDEST_CMDND12ERR *((volatile uint8_t *)(0x42DC079CUL)) + +#define bFM_SDIF_SBLKGPCTL_BLCKGSTPREQ *((volatile uint8_t *)(0x42DC0540UL)) +#define bFM4_SDIF_SBLKGPCTL_BLCKGSTPREQ *((volatile uint8_t *)(0x42DC0540UL)) +#define bFM_SDIF_SBLKGPCTL_CONTREQ *((volatile uint8_t *)(0x42DC0544UL)) +#define bFM4_SDIF_SBLKGPCTL_CONTREQ *((volatile uint8_t *)(0x42DC0544UL)) +#define bFM_SDIF_SBLKGPCTL_RDWAITCTL *((volatile uint8_t *)(0x42DC0548UL)) +#define bFM4_SDIF_SBLKGPCTL_RDWAITCTL *((volatile uint8_t *)(0x42DC0548UL)) +#define bFM_SDIF_SBLKGPCTL_BLCKGAPINT *((volatile uint8_t *)(0x42DC054CUL)) +#define bFM4_SDIF_SBLKGPCTL_BLCKGAPINT *((volatile uint8_t *)(0x42DC054CUL)) + +#define bFM_SDIF_SCLKCTL_INTLCLCKEN *((volatile uint8_t *)(0x42DC0580UL)) +#define bFM4_SDIF_SCLKCTL_INTLCLCKEN *((volatile uint8_t *)(0x42DC0580UL)) +#define bFM_SDIF_SCLKCTL_INTLCLCKST *((volatile uint8_t *)(0x42DC0584UL)) +#define bFM4_SDIF_SCLKCTL_INTLCLCKST *((volatile uint8_t *)(0x42DC0584UL)) +#define bFM_SDIF_SCLKCTL_SDCLCKEN *((volatile uint8_t *)(0x42DC0588UL)) +#define bFM4_SDIF_SCLKCTL_SDCLCKEN *((volatile uint8_t *)(0x42DC0588UL)) +#define bFM_SDIF_SCLKCTL_CLCKGENSEL *((volatile uint8_t *)(0x42DC0594UL)) +#define bFM4_SDIF_SCLKCTL_CLCKGENSEL *((volatile uint8_t *)(0x42DC0594UL)) + +#define bFM_SDIF_SCMMD_CMDCRCCHKE *((volatile uint8_t *)(0x42DC01CCUL)) +#define bFM4_SDIF_SCMMD_CMDCRCCHKE *((volatile uint8_t *)(0x42DC01CCUL)) +#define bFM_SDIF_SCMMD_CMDIDXCHKE *((volatile uint8_t *)(0x42DC01D0UL)) +#define bFM4_SDIF_SCMMD_CMDIDXCHKE *((volatile uint8_t *)(0x42DC01D0UL)) +#define bFM_SDIF_SCMMD_DATPRESSEL *((volatile uint8_t *)(0x42DC01D4UL)) +#define bFM4_SDIF_SCMMD_DATPRESSEL *((volatile uint8_t *)(0x42DC01D4UL)) + +#define bFM_SDIF_SEINTSGE_CMDTOERRG *((volatile uint8_t *)(0x42DC0740UL)) +#define bFM4_SDIF_SEINTSGE_CMDTOERRG *((volatile uint8_t *)(0x42DC0740UL)) +#define bFM_SDIF_SEINTSGE_CMDCRCERRG *((volatile uint8_t *)(0x42DC0744UL)) +#define bFM4_SDIF_SEINTSGE_CMDCRCERRG *((volatile uint8_t *)(0x42DC0744UL)) +#define bFM_SDIF_SEINTSGE_CMDEBERRG *((volatile uint8_t *)(0x42DC0748UL)) +#define bFM4_SDIF_SEINTSGE_CMDEBERRG *((volatile uint8_t *)(0x42DC0748UL)) +#define bFM_SDIF_SEINTSGE_CMDIDXERRG *((volatile uint8_t *)(0x42DC074CUL)) +#define bFM4_SDIF_SEINTSGE_CMDIDXERRG *((volatile uint8_t *)(0x42DC074CUL)) +#define bFM_SDIF_SEINTSGE_DTTOERRG *((volatile uint8_t *)(0x42DC0750UL)) +#define bFM4_SDIF_SEINTSGE_DTTOERRG *((volatile uint8_t *)(0x42DC0750UL)) +#define bFM_SDIF_SEINTSGE_DTCRCERRG *((volatile uint8_t *)(0x42DC0754UL)) +#define bFM4_SDIF_SEINTSGE_DTCRCERRG *((volatile uint8_t *)(0x42DC0754UL)) +#define bFM_SDIF_SEINTSGE_DTEBERRG *((volatile uint8_t *)(0x42DC0758UL)) +#define bFM4_SDIF_SEINTSGE_DTEBERRG *((volatile uint8_t *)(0x42DC0758UL)) +#define bFM_SDIF_SEINTSGE_CRTLMTERRG *((volatile uint8_t *)(0x42DC075CUL)) +#define bFM4_SDIF_SEINTSGE_CRTLMTERRG *((volatile uint8_t *)(0x42DC075CUL)) +#define bFM_SDIF_SEINTSGE_ACMD12ERRG *((volatile uint8_t *)(0x42DC0760UL)) +#define bFM4_SDIF_SEINTSGE_ACMD12ERRG *((volatile uint8_t *)(0x42DC0760UL)) +#define bFM_SDIF_SEINTSGE_ADMAERRG *((volatile uint8_t *)(0x42DC0764UL)) +#define bFM4_SDIF_SEINTSGE_ADMAERRG *((volatile uint8_t *)(0x42DC0764UL)) +#define bFM_SDIF_SEINTSGE_TUNINGERRG *((volatile uint8_t *)(0x42DC0768UL)) +#define bFM4_SDIF_SEINTSGE_TUNINGERRG *((volatile uint8_t *)(0x42DC0768UL)) +#define bFM_SDIF_SEINTSGE_BTACKERRG *((volatile uint8_t *)(0x42DC0770UL)) +#define bFM4_SDIF_SEINTSGE_BTACKERRG *((volatile uint8_t *)(0x42DC0770UL)) +#define bFM_SDIF_SEINTSGE_ACMD19ERRG *((volatile uint8_t *)(0x42DC0774UL)) +#define bFM4_SDIF_SEINTSGE_ACMD19ERRG *((volatile uint8_t *)(0x42DC0774UL)) +#define bFM_SDIF_SEINTSGE_AHBMSTERRG *((volatile uint8_t *)(0x42DC0778UL)) +#define bFM4_SDIF_SEINTSGE_AHBMSTERRG *((volatile uint8_t *)(0x42DC0778UL)) + +#define bFM_SDIF_SEINTST_CMDTOERR *((volatile uint8_t *)(0x42DC0640UL)) +#define bFM4_SDIF_SEINTST_CMDTOERR *((volatile uint8_t *)(0x42DC0640UL)) +#define bFM_SDIF_SEINTST_CMDCRCERR *((volatile uint8_t *)(0x42DC0644UL)) +#define bFM4_SDIF_SEINTST_CMDCRCERR *((volatile uint8_t *)(0x42DC0644UL)) +#define bFM_SDIF_SEINTST_CMDEBERR *((volatile uint8_t *)(0x42DC0648UL)) +#define bFM4_SDIF_SEINTST_CMDEBERR *((volatile uint8_t *)(0x42DC0648UL)) +#define bFM_SDIF_SEINTST_CMDIDXERR *((volatile uint8_t *)(0x42DC064CUL)) +#define bFM4_SDIF_SEINTST_CMDIDXERR *((volatile uint8_t *)(0x42DC064CUL)) +#define bFM_SDIF_SEINTST_DTTOERR *((volatile uint8_t *)(0x42DC0650UL)) +#define bFM4_SDIF_SEINTST_DTTOERR *((volatile uint8_t *)(0x42DC0650UL)) +#define bFM_SDIF_SEINTST_DTCRCERR *((volatile uint8_t *)(0x42DC0654UL)) +#define bFM4_SDIF_SEINTST_DTCRCERR *((volatile uint8_t *)(0x42DC0654UL)) +#define bFM_SDIF_SEINTST_DTEBERR *((volatile uint8_t *)(0x42DC0658UL)) +#define bFM4_SDIF_SEINTST_DTEBERR *((volatile uint8_t *)(0x42DC0658UL)) +#define bFM_SDIF_SEINTST_CRTLMTERR *((volatile uint8_t *)(0x42DC065CUL)) +#define bFM4_SDIF_SEINTST_CRTLMTERR *((volatile uint8_t *)(0x42DC065CUL)) +#define bFM_SDIF_SEINTST_ACMD12ERR *((volatile uint8_t *)(0x42DC0660UL)) +#define bFM4_SDIF_SEINTST_ACMD12ERR *((volatile uint8_t *)(0x42DC0660UL)) +#define bFM_SDIF_SEINTST_ADMAERR *((volatile uint8_t *)(0x42DC0664UL)) +#define bFM4_SDIF_SEINTST_ADMAERR *((volatile uint8_t *)(0x42DC0664UL)) +#define bFM_SDIF_SEINTST_TUNINGERR *((volatile uint8_t *)(0x42DC0668UL)) +#define bFM4_SDIF_SEINTST_TUNINGERR *((volatile uint8_t *)(0x42DC0668UL)) +#define bFM_SDIF_SEINTST_BTACKERR *((volatile uint8_t *)(0x42DC0670UL)) +#define bFM4_SDIF_SEINTST_BTACKERR *((volatile uint8_t *)(0x42DC0670UL)) +#define bFM_SDIF_SEINTST_ACMD19ERR *((volatile uint8_t *)(0x42DC0674UL)) +#define bFM4_SDIF_SEINTST_ACMD19ERR *((volatile uint8_t *)(0x42DC0674UL)) +#define bFM_SDIF_SEINTST_AHBMSTERR *((volatile uint8_t *)(0x42DC0678UL)) +#define bFM4_SDIF_SEINTST_AHBMSTERR *((volatile uint8_t *)(0x42DC0678UL)) + +#define bFM_SDIF_SEINTSTE_CMDTOERRS *((volatile uint8_t *)(0x42DC06C0UL)) +#define bFM4_SDIF_SEINTSTE_CMDTOERRS *((volatile uint8_t *)(0x42DC06C0UL)) +#define bFM_SDIF_SEINTSTE_CMDCRCERRS *((volatile uint8_t *)(0x42DC06C4UL)) +#define bFM4_SDIF_SEINTSTE_CMDCRCERRS *((volatile uint8_t *)(0x42DC06C4UL)) +#define bFM_SDIF_SEINTSTE_CMDEBERRS *((volatile uint8_t *)(0x42DC06C8UL)) +#define bFM4_SDIF_SEINTSTE_CMDEBERRS *((volatile uint8_t *)(0x42DC06C8UL)) +#define bFM_SDIF_SEINTSTE_CMDIDXERRS *((volatile uint8_t *)(0x42DC06CCUL)) +#define bFM4_SDIF_SEINTSTE_CMDIDXERRS *((volatile uint8_t *)(0x42DC06CCUL)) +#define bFM_SDIF_SEINTSTE_DTTOERRS *((volatile uint8_t *)(0x42DC06D0UL)) +#define bFM4_SDIF_SEINTSTE_DTTOERRS *((volatile uint8_t *)(0x42DC06D0UL)) +#define bFM_SDIF_SEINTSTE_DTCRCERRS *((volatile uint8_t *)(0x42DC06D4UL)) +#define bFM4_SDIF_SEINTSTE_DTCRCERRS *((volatile uint8_t *)(0x42DC06D4UL)) +#define bFM_SDIF_SEINTSTE_DTEBERRS *((volatile uint8_t *)(0x42DC06D8UL)) +#define bFM4_SDIF_SEINTSTE_DTEBERRS *((volatile uint8_t *)(0x42DC06D8UL)) +#define bFM_SDIF_SEINTSTE_CRTLMTERRS *((volatile uint8_t *)(0x42DC06DCUL)) +#define bFM4_SDIF_SEINTSTE_CRTLMTERRS *((volatile uint8_t *)(0x42DC06DCUL)) +#define bFM_SDIF_SEINTSTE_ACMD12ERRS *((volatile uint8_t *)(0x42DC06E0UL)) +#define bFM4_SDIF_SEINTSTE_ACMD12ERRS *((volatile uint8_t *)(0x42DC06E0UL)) +#define bFM_SDIF_SEINTSTE_ADMAERRS *((volatile uint8_t *)(0x42DC06E4UL)) +#define bFM4_SDIF_SEINTSTE_ADMAERRS *((volatile uint8_t *)(0x42DC06E4UL)) +#define bFM_SDIF_SEINTSTE_TUNINGERRS *((volatile uint8_t *)(0x42DC06E8UL)) +#define bFM4_SDIF_SEINTSTE_TUNINGERRS *((volatile uint8_t *)(0x42DC06E8UL)) +#define bFM_SDIF_SEINTSTE_BTACKERRS *((volatile uint8_t *)(0x42DC06F0UL)) +#define bFM4_SDIF_SEINTSTE_BTACKERRS *((volatile uint8_t *)(0x42DC06F0UL)) +#define bFM_SDIF_SEINTSTE_ACMD19ERRS *((volatile uint8_t *)(0x42DC06F4UL)) +#define bFM4_SDIF_SEINTSTE_ACMD19ERRS *((volatile uint8_t *)(0x42DC06F4UL)) +#define bFM_SDIF_SEINTSTE_AHBMSTERRS *((volatile uint8_t *)(0x42DC06F8UL)) +#define bFM4_SDIF_SEINTSTE_AHBMSTERRS *((volatile uint8_t *)(0x42DC06F8UL)) + +#define bFM_SDIF_SFEEIST_FETOERR *((volatile uint8_t *)(0x42DC0A40UL)) +#define bFM4_SDIF_SFEEIST_FETOERR *((volatile uint8_t *)(0x42DC0A40UL)) +#define bFM_SDIF_SFEEIST_FECRCERR *((volatile uint8_t *)(0x42DC0A44UL)) +#define bFM4_SDIF_SFEEIST_FECRCERR *((volatile uint8_t *)(0x42DC0A44UL)) +#define bFM_SDIF_SFEEIST_FEEBERR *((volatile uint8_t *)(0x42DC0A48UL)) +#define bFM4_SDIF_SFEEIST_FEEBERR *((volatile uint8_t *)(0x42DC0A48UL)) +#define bFM_SDIF_SFEEIST_FEIDXERR *((volatile uint8_t *)(0x42DC0A4CUL)) +#define bFM4_SDIF_SFEEIST_FEIDXERR *((volatile uint8_t *)(0x42DC0A4CUL)) +#define bFM_SDIF_SFEEIST_FEDTOTERR *((volatile uint8_t *)(0x42DC0A50UL)) +#define bFM4_SDIF_SFEEIST_FEDTOTERR *((volatile uint8_t *)(0x42DC0A50UL)) +#define bFM_SDIF_SFEEIST_FEDTCRCERR *((volatile uint8_t *)(0x42DC0A54UL)) +#define bFM4_SDIF_SFEEIST_FEDTCRCERR *((volatile uint8_t *)(0x42DC0A54UL)) +#define bFM_SDIF_SFEEIST_FEDTEBERR *((volatile uint8_t *)(0x42DC0A58UL)) +#define bFM4_SDIF_SFEEIST_FEDTEBERR *((volatile uint8_t *)(0x42DC0A58UL)) +#define bFM_SDIF_SFEEIST_FECRLTERR *((volatile uint8_t *)(0x42DC0A5CUL)) +#define bFM4_SDIF_SFEEIST_FECRLTERR *((volatile uint8_t *)(0x42DC0A5CUL)) +#define bFM_SDIF_SFEEIST_FEA12ERR *((volatile uint8_t *)(0x42DC0A60UL)) +#define bFM4_SDIF_SFEEIST_FEA12ERR *((volatile uint8_t *)(0x42DC0A60UL)) +#define bFM_SDIF_SFEEIST_FEADMAERR *((volatile uint8_t *)(0x42DC0A64UL)) +#define bFM4_SDIF_SFEEIST_FEADMAERR *((volatile uint8_t *)(0x42DC0A64UL)) +#define bFM_SDIF_SFEEIST_FETUNEERR *((volatile uint8_t *)(0x42DC0A68UL)) +#define bFM4_SDIF_SFEEIST_FETUNEERR *((volatile uint8_t *)(0x42DC0A68UL)) +#define bFM_SDIF_SFEEIST_FEACKERR *((volatile uint8_t *)(0x42DC0A70UL)) +#define bFM4_SDIF_SFEEIST_FEACKERR *((volatile uint8_t *)(0x42DC0A70UL)) +#define bFM_SDIF_SFEEIST_FEA19ERR *((volatile uint8_t *)(0x42DC0A74UL)) +#define bFM4_SDIF_SFEEIST_FEA19ERR *((volatile uint8_t *)(0x42DC0A74UL)) +#define bFM_SDIF_SFEEIST_FEAHBMSERR *((volatile uint8_t *)(0x42DC0A78UL)) +#define bFM4_SDIF_SFEEIST_FEAHBMSERR *((volatile uint8_t *)(0x42DC0A78UL)) + +#define bFM_SDIF_SHCTL1_LEDCTRL *((volatile uint8_t *)(0x42DC0500UL)) +#define bFM4_SDIF_SHCTL1_LEDCTRL *((volatile uint8_t *)(0x42DC0500UL)) +#define bFM_SDIF_SHCTL1_DATAWIDTH *((volatile uint8_t *)(0x42DC0504UL)) +#define bFM4_SDIF_SHCTL1_DATAWIDTH *((volatile uint8_t *)(0x42DC0504UL)) +#define bFM_SDIF_SHCTL1_HIGHSPDEN *((volatile uint8_t *)(0x42DC0508UL)) +#define bFM4_SDIF_SHCTL1_HIGHSPDEN *((volatile uint8_t *)(0x42DC0508UL)) +#define bFM_SDIF_SHCTL1_EXTDTWIDTH *((volatile uint8_t *)(0x42DC0514UL)) +#define bFM4_SDIF_SHCTL1_EXTDTWIDTH *((volatile uint8_t *)(0x42DC0514UL)) +#define bFM_SDIF_SHCTL1_CDTSTLVL *((volatile uint8_t *)(0x42DC0518UL)) +#define bFM4_SDIF_SHCTL1_CDTSTLVL *((volatile uint8_t *)(0x42DC0518UL)) +#define bFM_SDIF_SHCTL1_CDSGNSEL *((volatile uint8_t *)(0x42DC051CUL)) +#define bFM4_SDIF_SHCTL1_CDSGNSEL *((volatile uint8_t *)(0x42DC051CUL)) + +#define bFM_SDIF_SHCTL2_V18SGNEN *((volatile uint8_t *)(0x42DC07CCUL)) +#define bFM4_SDIF_SHCTL2_V18SGNEN *((volatile uint8_t *)(0x42DC07CCUL)) +#define bFM_SDIF_SHCTL2_DOTUING *((volatile uint8_t *)(0x42DC07D8UL)) +#define bFM4_SDIF_SHCTL2_DOTUING *((volatile uint8_t *)(0x42DC07D8UL)) +#define bFM_SDIF_SHCTL2_SMPCLKSEL *((volatile uint8_t *)(0x42DC07DCUL)) +#define bFM4_SDIF_SHCTL2_SMPCLKSEL *((volatile uint8_t *)(0x42DC07DCUL)) +#define bFM_SDIF_SHCTL2_ASYINTEN *((volatile uint8_t *)(0x42DC07F8UL)) +#define bFM4_SDIF_SHCTL2_ASYINTEN *((volatile uint8_t *)(0x42DC07F8UL)) +#define bFM_SDIF_SHCTL2_PREVALEN *((volatile uint8_t *)(0x42DC07FCUL)) +#define bFM4_SDIF_SHCTL2_PREVALEN *((volatile uint8_t *)(0x42DC07FCUL)) + +#define bFM_SDIF_SNINTSGE_CMDCMPLTG *((volatile uint8_t *)(0x42DC0700UL)) +#define bFM4_SDIF_SNINTSGE_CMDCMPLTG *((volatile uint8_t *)(0x42DC0700UL)) +#define bFM_SDIF_SNINTSGE_TRSFCMPLTG *((volatile uint8_t *)(0x42DC0704UL)) +#define bFM4_SDIF_SNINTSGE_TRSFCMPLTG *((volatile uint8_t *)(0x42DC0704UL)) +#define bFM_SDIF_SNINTSGE_BLCKGEVNTG *((volatile uint8_t *)(0x42DC0708UL)) +#define bFM4_SDIF_SNINTSGE_BLCKGEVNTG *((volatile uint8_t *)(0x42DC0708UL)) +#define bFM_SDIF_SNINTSGE_DMAINTG *((volatile uint8_t *)(0x42DC070CUL)) +#define bFM4_SDIF_SNINTSGE_DMAINTG *((volatile uint8_t *)(0x42DC070CUL)) +#define bFM_SDIF_SNINTSGE_BUFWRRDYG *((volatile uint8_t *)(0x42DC0710UL)) +#define bFM4_SDIF_SNINTSGE_BUFWRRDYG *((volatile uint8_t *)(0x42DC0710UL)) +#define bFM_SDIF_SNINTSGE_BUFRDRDYG *((volatile uint8_t *)(0x42DC0714UL)) +#define bFM4_SDIF_SNINTSGE_BUFRDRDYG *((volatile uint8_t *)(0x42DC0714UL)) +#define bFM_SDIF_SNINTSGE_CARDINSG *((volatile uint8_t *)(0x42DC0718UL)) +#define bFM4_SDIF_SNINTSGE_CARDINSG *((volatile uint8_t *)(0x42DC0718UL)) +#define bFM_SDIF_SNINTSGE_CARDRMVG *((volatile uint8_t *)(0x42DC071CUL)) +#define bFM4_SDIF_SNINTSGE_CARDRMVG *((volatile uint8_t *)(0x42DC071CUL)) +#define bFM_SDIF_SNINTSGE_CARDINTG *((volatile uint8_t *)(0x42DC0720UL)) +#define bFM4_SDIF_SNINTSGE_CARDINTG *((volatile uint8_t *)(0x42DC0720UL)) +#define bFM_SDIF_SNINTSGE_INT_AG *((volatile uint8_t *)(0x42DC0724UL)) +#define bFM4_SDIF_SNINTSGE_INT_AG *((volatile uint8_t *)(0x42DC0724UL)) +#define bFM_SDIF_SNINTSGE_INT_BG *((volatile uint8_t *)(0x42DC0728UL)) +#define bFM4_SDIF_SNINTSGE_INT_BG *((volatile uint8_t *)(0x42DC0728UL)) +#define bFM_SDIF_SNINTSGE_INT_CG *((volatile uint8_t *)(0x42DC072CUL)) +#define bFM4_SDIF_SNINTSGE_INT_CG *((volatile uint8_t *)(0x42DC072CUL)) +#define bFM_SDIF_SNINTSGE_RETUNEEVTG *((volatile uint8_t *)(0x42DC0730UL)) +#define bFM4_SDIF_SNINTSGE_RETUNEEVTG *((volatile uint8_t *)(0x42DC0730UL)) + +#define bFM_SDIF_SNINTST_CMDCMPLT *((volatile uint8_t *)(0x42DC0600UL)) +#define bFM4_SDIF_SNINTST_CMDCMPLT *((volatile uint8_t *)(0x42DC0600UL)) +#define bFM_SDIF_SNINTST_TRSFCMPLT *((volatile uint8_t *)(0x42DC0604UL)) +#define bFM4_SDIF_SNINTST_TRSFCMPLT *((volatile uint8_t *)(0x42DC0604UL)) +#define bFM_SDIF_SNINTST_BLCKGEVNT *((volatile uint8_t *)(0x42DC0608UL)) +#define bFM4_SDIF_SNINTST_BLCKGEVNT *((volatile uint8_t *)(0x42DC0608UL)) +#define bFM_SDIF_SNINTST_DMAINT *((volatile uint8_t *)(0x42DC060CUL)) +#define bFM4_SDIF_SNINTST_DMAINT *((volatile uint8_t *)(0x42DC060CUL)) +#define bFM_SDIF_SNINTST_BUFWRRDY *((volatile uint8_t *)(0x42DC0610UL)) +#define bFM4_SDIF_SNINTST_BUFWRRDY *((volatile uint8_t *)(0x42DC0610UL)) +#define bFM_SDIF_SNINTST_BUFRDRDY *((volatile uint8_t *)(0x42DC0614UL)) +#define bFM4_SDIF_SNINTST_BUFRDRDY *((volatile uint8_t *)(0x42DC0614UL)) +#define bFM_SDIF_SNINTST_CARDINS *((volatile uint8_t *)(0x42DC0618UL)) +#define bFM4_SDIF_SNINTST_CARDINS *((volatile uint8_t *)(0x42DC0618UL)) +#define bFM_SDIF_SNINTST_CARDRMV *((volatile uint8_t *)(0x42DC061CUL)) +#define bFM4_SDIF_SNINTST_CARDRMV *((volatile uint8_t *)(0x42DC061CUL)) +#define bFM_SDIF_SNINTST_CARDINT *((volatile uint8_t *)(0x42DC0620UL)) +#define bFM4_SDIF_SNINTST_CARDINT *((volatile uint8_t *)(0x42DC0620UL)) +#define bFM_SDIF_SNINTST_INT_A *((volatile uint8_t *)(0x42DC0624UL)) +#define bFM4_SDIF_SNINTST_INT_A *((volatile uint8_t *)(0x42DC0624UL)) +#define bFM_SDIF_SNINTST_INT_B *((volatile uint8_t *)(0x42DC0628UL)) +#define bFM4_SDIF_SNINTST_INT_B *((volatile uint8_t *)(0x42DC0628UL)) +#define bFM_SDIF_SNINTST_INT_C *((volatile uint8_t *)(0x42DC062CUL)) +#define bFM4_SDIF_SNINTST_INT_C *((volatile uint8_t *)(0x42DC062CUL)) +#define bFM_SDIF_SNINTST_RETUNEEVT *((volatile uint8_t *)(0x42DC0630UL)) +#define bFM4_SDIF_SNINTST_RETUNEEVT *((volatile uint8_t *)(0x42DC0630UL)) +#define bFM_SDIF_SNINTST_ERRORINT *((volatile uint8_t *)(0x42DC063CUL)) +#define bFM4_SDIF_SNINTST_ERRORINT *((volatile uint8_t *)(0x42DC063CUL)) + +#define bFM_SDIF_SNINTSTE_CMDCMPLTS *((volatile uint8_t *)(0x42DC0680UL)) +#define bFM4_SDIF_SNINTSTE_CMDCMPLTS *((volatile uint8_t *)(0x42DC0680UL)) +#define bFM_SDIF_SNINTSTE_TRSFCMPLTS *((volatile uint8_t *)(0x42DC0684UL)) +#define bFM4_SDIF_SNINTSTE_TRSFCMPLTS *((volatile uint8_t *)(0x42DC0684UL)) +#define bFM_SDIF_SNINTSTE_BLCKGEVNTS *((volatile uint8_t *)(0x42DC0688UL)) +#define bFM4_SDIF_SNINTSTE_BLCKGEVNTS *((volatile uint8_t *)(0x42DC0688UL)) +#define bFM_SDIF_SNINTSTE_DMAINTS *((volatile uint8_t *)(0x42DC068CUL)) +#define bFM4_SDIF_SNINTSTE_DMAINTS *((volatile uint8_t *)(0x42DC068CUL)) +#define bFM_SDIF_SNINTSTE_BUFWRRDYS *((volatile uint8_t *)(0x42DC0690UL)) +#define bFM4_SDIF_SNINTSTE_BUFWRRDYS *((volatile uint8_t *)(0x42DC0690UL)) +#define bFM_SDIF_SNINTSTE_BUFRDRDYS *((volatile uint8_t *)(0x42DC0694UL)) +#define bFM4_SDIF_SNINTSTE_BUFRDRDYS *((volatile uint8_t *)(0x42DC0694UL)) +#define bFM_SDIF_SNINTSTE_CARDINSS *((volatile uint8_t *)(0x42DC0698UL)) +#define bFM4_SDIF_SNINTSTE_CARDINSS *((volatile uint8_t *)(0x42DC0698UL)) +#define bFM_SDIF_SNINTSTE_CARDRMVS *((volatile uint8_t *)(0x42DC069CUL)) +#define bFM4_SDIF_SNINTSTE_CARDRMVS *((volatile uint8_t *)(0x42DC069CUL)) +#define bFM_SDIF_SNINTSTE_CARDINTS *((volatile uint8_t *)(0x42DC06A0UL)) +#define bFM4_SDIF_SNINTSTE_CARDINTS *((volatile uint8_t *)(0x42DC06A0UL)) +#define bFM_SDIF_SNINTSTE_INT_AS *((volatile uint8_t *)(0x42DC06A4UL)) +#define bFM4_SDIF_SNINTSTE_INT_AS *((volatile uint8_t *)(0x42DC06A4UL)) +#define bFM_SDIF_SNINTSTE_INT_BS *((volatile uint8_t *)(0x42DC06A8UL)) +#define bFM4_SDIF_SNINTSTE_INT_BS *((volatile uint8_t *)(0x42DC06A8UL)) +#define bFM_SDIF_SNINTSTE_INT_CS *((volatile uint8_t *)(0x42DC06ACUL)) +#define bFM4_SDIF_SNINTSTE_INT_CS *((volatile uint8_t *)(0x42DC06ACUL)) +#define bFM_SDIF_SNINTSTE_RETUNEEVTS *((volatile uint8_t *)(0x42DC06B0UL)) +#define bFM4_SDIF_SNINTSTE_RETUNEEVTS *((volatile uint8_t *)(0x42DC06B0UL)) + +#define bFM_SDIF_SPRSTAT_CMDINH *((volatile uint8_t *)(0x42DC0480UL)) +#define bFM4_SDIF_SPRSTAT_CMDINH *((volatile uint8_t *)(0x42DC0480UL)) +#define bFM_SDIF_SPRSTAT_CMDDATINH *((volatile uint8_t *)(0x42DC0484UL)) +#define bFM4_SDIF_SPRSTAT_CMDDATINH *((volatile uint8_t *)(0x42DC0484UL)) +#define bFM_SDIF_SPRSTAT_DATLNACT *((volatile uint8_t *)(0x42DC0488UL)) +#define bFM4_SDIF_SPRSTAT_DATLNACT *((volatile uint8_t *)(0x42DC0488UL)) +#define bFM_SDIF_SPRSTAT_RETUNEREQ *((volatile uint8_t *)(0x42DC048CUL)) +#define bFM4_SDIF_SPRSTAT_RETUNEREQ *((volatile uint8_t *)(0x42DC048CUL)) +#define bFM_SDIF_SPRSTAT_WRTRSFACT *((volatile uint8_t *)(0x42DC04A0UL)) +#define bFM4_SDIF_SPRSTAT_WRTRSFACT *((volatile uint8_t *)(0x42DC04A0UL)) +#define bFM_SDIF_SPRSTAT_RDTRSFACT *((volatile uint8_t *)(0x42DC04A4UL)) +#define bFM4_SDIF_SPRSTAT_RDTRSFACT *((volatile uint8_t *)(0x42DC04A4UL)) +#define bFM_SDIF_SPRSTAT_BUFWREN *((volatile uint8_t *)(0x42DC04A8UL)) +#define bFM4_SDIF_SPRSTAT_BUFWREN *((volatile uint8_t *)(0x42DC04A8UL)) +#define bFM_SDIF_SPRSTAT_BUFRDEN *((volatile uint8_t *)(0x42DC04ACUL)) +#define bFM4_SDIF_SPRSTAT_BUFRDEN *((volatile uint8_t *)(0x42DC04ACUL)) +#define bFM_SDIF_SPRSTAT_CARDINS *((volatile uint8_t *)(0x42DC04C0UL)) +#define bFM4_SDIF_SPRSTAT_CARDINS *((volatile uint8_t *)(0x42DC04C0UL)) +#define bFM_SDIF_SPRSTAT_CARDSTB *((volatile uint8_t *)(0x42DC04C4UL)) +#define bFM4_SDIF_SPRSTAT_CARDSTB *((volatile uint8_t *)(0x42DC04C4UL)) +#define bFM_SDIF_SPRSTAT_CARDDET *((volatile uint8_t *)(0x42DC04C8UL)) +#define bFM4_SDIF_SPRSTAT_CARDDET *((volatile uint8_t *)(0x42DC04C8UL)) +#define bFM_SDIF_SPRSTAT_WPPINLVL *((volatile uint8_t *)(0x42DC04CCUL)) +#define bFM4_SDIF_SPRSTAT_WPPINLVL *((volatile uint8_t *)(0x42DC04CCUL)) +#define bFM_SDIF_SPRSTAT_CMDLNSGN *((volatile uint8_t *)(0x42DC04E0UL)) +#define bFM4_SDIF_SPRSTAT_CMDLNSGN *((volatile uint8_t *)(0x42DC04E0UL)) + +#define bFM_SDIF_SPRVAL0_CGSELVAL *((volatile uint8_t *)(0x42DC0C28UL)) +#define bFM4_SDIF_SPRVAL0_CGSELVAL *((volatile uint8_t *)(0x42DC0C28UL)) + +#define bFM_SDIF_SPRVAL1_CGSELVAL *((volatile uint8_t *)(0x42DC0C68UL)) +#define bFM4_SDIF_SPRVAL1_CGSELVAL *((volatile uint8_t *)(0x42DC0C68UL)) + +#define bFM_SDIF_SPRVAL2_CGSELVAL *((volatile uint8_t *)(0x42DC0CA8UL)) +#define bFM4_SDIF_SPRVAL2_CGSELVAL *((volatile uint8_t *)(0x42DC0CA8UL)) + +#define bFM_SDIF_SPRVAL3_CGSELVAL *((volatile uint8_t *)(0x42DC0CE8UL)) +#define bFM4_SDIF_SPRVAL3_CGSELVAL *((volatile uint8_t *)(0x42DC0CE8UL)) + +#define bFM_SDIF_SPRVAL4_CGSELVAL *((volatile uint8_t *)(0x42DC0D28UL)) +#define bFM4_SDIF_SPRVAL4_CGSELVAL *((volatile uint8_t *)(0x42DC0D28UL)) + +#define bFM_SDIF_SPRVAL5_CGSELVAL *((volatile uint8_t *)(0x42DC0D68UL)) +#define bFM4_SDIF_SPRVAL5_CGSELVAL *((volatile uint8_t *)(0x42DC0D68UL)) + +#define bFM_SDIF_SPRVAL6_CGSELVAL *((volatile uint8_t *)(0x42DC0DA8UL)) +#define bFM4_SDIF_SPRVAL6_CGSELVAL *((volatile uint8_t *)(0x42DC0DA8UL)) + +#define bFM_SDIF_SPRVAL7_CGSELVAL *((volatile uint8_t *)(0x42DC0DE8UL)) +#define bFM4_SDIF_SPRVAL7_CGSELVAL *((volatile uint8_t *)(0x42DC0DE8UL)) + +#define bFM_SDIF_SPWRCTL_SDBUSPWR *((volatile uint8_t *)(0x42DC0520UL)) +#define bFM4_SDIF_SPWRCTL_SDBUSPWR *((volatile uint8_t *)(0x42DC0520UL)) + +#define bFM_SDIF_SPWSWCL_ATPWRSWEN *((volatile uint8_t *)(0x42DC2080UL)) +#define bFM4_SDIF_SPWSWCL_ATPWRSWEN *((volatile uint8_t *)(0x42DC2080UL)) +#define bFM_SDIF_SPWSWCL_IOREGSEL *((volatile uint8_t *)(0x42DC2084UL)) +#define bFM4_SDIF_SPWSWCL_IOREGSEL *((volatile uint8_t *)(0x42DC2084UL)) + +#define bFM_SDIF_SSRST_SWRSTALL *((volatile uint8_t *)(0x42DC05E0UL)) +#define bFM4_SDIF_SSRST_SWRSTALL *((volatile uint8_t *)(0x42DC05E0UL)) +#define bFM_SDIF_SSRST_SWRSTCMDLN *((volatile uint8_t *)(0x42DC05E4UL)) +#define bFM4_SDIF_SSRST_SWRSTCMDLN *((volatile uint8_t *)(0x42DC05E4UL)) +#define bFM_SDIF_SSRST_SWRSTDATLN *((volatile uint8_t *)(0x42DC05E8UL)) +#define bFM4_SDIF_SSRST_SWRSTDATLN *((volatile uint8_t *)(0x42DC05E8UL)) + +#define bFM_SDIF_STRSFMD_DMAEN *((volatile uint8_t *)(0x42DC0180UL)) +#define bFM4_SDIF_STRSFMD_DMAEN *((volatile uint8_t *)(0x42DC0180UL)) +#define bFM_SDIF_STRSFMD_BLCKCNTEN *((volatile uint8_t *)(0x42DC0184UL)) +#define bFM4_SDIF_STRSFMD_BLCKCNTEN *((volatile uint8_t *)(0x42DC0184UL)) +#define bFM_SDIF_STRSFMD_DTTRSFDIR *((volatile uint8_t *)(0x42DC0190UL)) +#define bFM4_SDIF_STRSFMD_DTTRSFDIR *((volatile uint8_t *)(0x42DC0190UL)) +#define bFM_SDIF_STRSFMD_BLCKCNTSEL *((volatile uint8_t *)(0x42DC0194UL)) +#define bFM4_SDIF_STRSFMD_BLCKCNTSEL *((volatile uint8_t *)(0x42DC0194UL)) + +#define bFM_SDIF_STUNSETH_CMDCFCHKDS *((volatile uint8_t *)(0x42DC2140UL)) +#define bFM4_SDIF_STUNSETH_CMDCFCHKDS *((volatile uint8_t *)(0x42DC2140UL)) + +#define bFM_SDIF_STUNSETL_TNPHSELEN *((volatile uint8_t *)(0x42DC2120UL)) +#define bFM4_SDIF_STUNSETL_TNPHSELEN *((volatile uint8_t *)(0x42DC2120UL)) +#define bFM_SDIF_STUNSETL_TNERRBDSEL *((volatile uint8_t *)(0x42DC2124UL)) +#define bFM4_SDIF_STUNSETL_TNERRBDSEL *((volatile uint8_t *)(0x42DC2124UL)) +#define bFM_SDIF_STUNSETL_RETNTAPSEL *((volatile uint8_t *)(0x42DC2128UL)) +#define bFM4_SDIF_STUNSETL_RETNTAPSEL *((volatile uint8_t *)(0x42DC2128UL)) + +#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN0 *((volatile uint8_t *)(0x42DC0560UL)) +#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN0 *((volatile uint8_t *)(0x42DC0560UL)) +#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN1 *((volatile uint8_t *)(0x42DC0564UL)) +#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN1 *((volatile uint8_t *)(0x42DC0564UL)) +#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN2 *((volatile uint8_t *)(0x42DC0568UL)) +#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN2 *((volatile uint8_t *)(0x42DC0568UL)) + + +/******************************************************************************* +* SWWDT Registers SWWDT +* Bitband Section +*******************************************************************************/ +#define bFM_SWWDT_WDOGCONTROL_INTEN *((volatile uint32_t*)(0x42240100UL)) +#define bFM4_SWWDT_WDOGCONTROL_INTEN *((volatile uint32_t*)(0x42240100UL)) +#define bFM_SWWDT_WDOGCONTROL_RESEN *((volatile uint32_t*)(0x42240104UL)) +#define bFM4_SWWDT_WDOGCONTROL_RESEN *((volatile uint32_t*)(0x42240104UL)) +#define bFM_SWWDT_WDOGCONTROL_SPM *((volatile uint32_t*)(0x42240110UL)) +#define bFM4_SWWDT_WDOGCONTROL_SPM *((volatile uint32_t*)(0x42240110UL)) + +#define bFM_SWWDT_WDOGRIS_RIS *((volatile uint32_t*)(0x42240200UL)) +#define bFM4_SWWDT_WDOGRIS_RIS *((volatile uint32_t*)(0x42240200UL)) + +#define bFM_SWWDT_WDOGSPMC_TGR *((volatile uint32_t*)(0x42240300UL)) +#define bFM4_SWWDT_WDOGSPMC_TGR *((volatile uint32_t*)(0x42240300UL)) + + +/******************************************************************************* +* UNIQUE_ID Registers UNIQUE_ID +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* USB Registers USB0 +* Bitband Section +*******************************************************************************/ +#define bFM_USB0_EP0C_STAL *((volatile uint16_t*)(0x428424A4UL)) +#define bFM4_USB0_EP0C_STAL *((volatile uint16_t*)(0x428424A4UL)) + +#define bFM_USB0_EP0IS_DRQI *((volatile uint16_t*)(0x428428A8UL)) +#define bFM4_USB0_EP0IS_DRQI *((volatile uint16_t*)(0x428428A8UL)) +#define bFM_USB0_EP0IS_DRQIIE *((volatile uint16_t*)(0x428428B8UL)) +#define bFM4_USB0_EP0IS_DRQIIE *((volatile uint16_t*)(0x428428B8UL)) +#define bFM_USB0_EP0IS_BFINI *((volatile uint16_t*)(0x428428BCUL)) +#define bFM4_USB0_EP0IS_BFINI *((volatile uint16_t*)(0x428428BCUL)) + +#define bFM_USB0_EP0OS_SPK *((volatile uint16_t*)(0x42842924UL)) +#define bFM4_USB0_EP0OS_SPK *((volatile uint16_t*)(0x42842924UL)) +#define bFM_USB0_EP0OS_DRQO *((volatile uint16_t*)(0x42842928UL)) +#define bFM4_USB0_EP0OS_DRQO *((volatile uint16_t*)(0x42842928UL)) +#define bFM_USB0_EP0OS_SPKIE *((volatile uint16_t*)(0x42842934UL)) +#define bFM4_USB0_EP0OS_SPKIE *((volatile uint16_t*)(0x42842934UL)) +#define bFM_USB0_EP0OS_DRQOIE *((volatile uint16_t*)(0x42842938UL)) +#define bFM4_USB0_EP0OS_DRQOIE *((volatile uint16_t*)(0x42842938UL)) +#define bFM_USB0_EP0OS_BFINI *((volatile uint16_t*)(0x4284293CUL)) +#define bFM4_USB0_EP0OS_BFINI *((volatile uint16_t*)(0x4284293CUL)) + +#define bFM_USB0_EP1C_STAL *((volatile uint16_t*)(0x42842524UL)) +#define bFM4_USB0_EP1C_STAL *((volatile uint16_t*)(0x42842524UL)) +#define bFM_USB0_EP1C_NULE *((volatile uint16_t*)(0x42842528UL)) +#define bFM4_USB0_EP1C_NULE *((volatile uint16_t*)(0x42842528UL)) +#define bFM_USB0_EP1C_DMAE *((volatile uint16_t*)(0x4284252CUL)) +#define bFM4_USB0_EP1C_DMAE *((volatile uint16_t*)(0x4284252CUL)) +#define bFM_USB0_EP1C_DIR *((volatile uint16_t*)(0x42842530UL)) +#define bFM4_USB0_EP1C_DIR *((volatile uint16_t*)(0x42842530UL)) +#define bFM_USB0_EP1C_EPEN *((volatile uint16_t*)(0x4284253CUL)) +#define bFM4_USB0_EP1C_EPEN *((volatile uint16_t*)(0x4284253CUL)) + +#define bFM_USB0_EP1S_SPK *((volatile uint16_t*)(0x428429A4UL)) +#define bFM4_USB0_EP1S_SPK *((volatile uint16_t*)(0x428429A4UL)) +#define bFM_USB0_EP1S_DRQ *((volatile uint16_t*)(0x428429A8UL)) +#define bFM4_USB0_EP1S_DRQ *((volatile uint16_t*)(0x428429A8UL)) +#define bFM_USB0_EP1S_BUSY *((volatile uint16_t*)(0x428429ACUL)) +#define bFM4_USB0_EP1S_BUSY *((volatile uint16_t*)(0x428429ACUL)) +#define bFM_USB0_EP1S_SPKIE *((volatile uint16_t*)(0x428429B4UL)) +#define bFM4_USB0_EP1S_SPKIE *((volatile uint16_t*)(0x428429B4UL)) +#define bFM_USB0_EP1S_DRQIE *((volatile uint16_t*)(0x428429B8UL)) +#define bFM4_USB0_EP1S_DRQIE *((volatile uint16_t*)(0x428429B8UL)) +#define bFM_USB0_EP1S_BFINI *((volatile uint16_t*)(0x428429BCUL)) +#define bFM4_USB0_EP1S_BFINI *((volatile uint16_t*)(0x428429BCUL)) + +#define bFM_USB0_EP2C_STAL *((volatile uint16_t*)(0x428425A4UL)) +#define bFM4_USB0_EP2C_STAL *((volatile uint16_t*)(0x428425A4UL)) +#define bFM_USB0_EP2C_NULE *((volatile uint16_t*)(0x428425A8UL)) +#define bFM4_USB0_EP2C_NULE *((volatile uint16_t*)(0x428425A8UL)) +#define bFM_USB0_EP2C_DMAE *((volatile uint16_t*)(0x428425ACUL)) +#define bFM4_USB0_EP2C_DMAE *((volatile uint16_t*)(0x428425ACUL)) +#define bFM_USB0_EP2C_DIR *((volatile uint16_t*)(0x428425B0UL)) +#define bFM4_USB0_EP2C_DIR *((volatile uint16_t*)(0x428425B0UL)) +#define bFM_USB0_EP2C_EPEN *((volatile uint16_t*)(0x428425BCUL)) +#define bFM4_USB0_EP2C_EPEN *((volatile uint16_t*)(0x428425BCUL)) + +#define bFM_USB0_EP2S_SPK *((volatile uint16_t*)(0x42842A24UL)) +#define bFM4_USB0_EP2S_SPK *((volatile uint16_t*)(0x42842A24UL)) +#define bFM_USB0_EP2S_DRQ *((volatile uint16_t*)(0x42842A28UL)) +#define bFM4_USB0_EP2S_DRQ *((volatile uint16_t*)(0x42842A28UL)) +#define bFM_USB0_EP2S_BUSY *((volatile uint16_t*)(0x42842A2CUL)) +#define bFM4_USB0_EP2S_BUSY *((volatile uint16_t*)(0x42842A2CUL)) +#define bFM_USB0_EP2S_SPKIE *((volatile uint16_t*)(0x42842A34UL)) +#define bFM4_USB0_EP2S_SPKIE *((volatile uint16_t*)(0x42842A34UL)) +#define bFM_USB0_EP2S_DRQIE *((volatile uint16_t*)(0x42842A38UL)) +#define bFM4_USB0_EP2S_DRQIE *((volatile uint16_t*)(0x42842A38UL)) +#define bFM_USB0_EP2S_BFINI *((volatile uint16_t*)(0x42842A3CUL)) +#define bFM4_USB0_EP2S_BFINI *((volatile uint16_t*)(0x42842A3CUL)) + +#define bFM_USB0_EP3C_STAL *((volatile uint16_t*)(0x42842624UL)) +#define bFM4_USB0_EP3C_STAL *((volatile uint16_t*)(0x42842624UL)) +#define bFM_USB0_EP3C_NULE *((volatile uint16_t*)(0x42842628UL)) +#define bFM4_USB0_EP3C_NULE *((volatile uint16_t*)(0x42842628UL)) +#define bFM_USB0_EP3C_DMAE *((volatile uint16_t*)(0x4284262CUL)) +#define bFM4_USB0_EP3C_DMAE *((volatile uint16_t*)(0x4284262CUL)) +#define bFM_USB0_EP3C_DIR *((volatile uint16_t*)(0x42842630UL)) +#define bFM4_USB0_EP3C_DIR *((volatile uint16_t*)(0x42842630UL)) +#define bFM_USB0_EP3C_EPEN *((volatile uint16_t*)(0x4284263CUL)) +#define bFM4_USB0_EP3C_EPEN *((volatile uint16_t*)(0x4284263CUL)) + +#define bFM_USB0_EP3S_SPK *((volatile uint16_t*)(0x42842AA4UL)) +#define bFM4_USB0_EP3S_SPK *((volatile uint16_t*)(0x42842AA4UL)) +#define bFM_USB0_EP3S_DRQ *((volatile uint16_t*)(0x42842AA8UL)) +#define bFM4_USB0_EP3S_DRQ *((volatile uint16_t*)(0x42842AA8UL)) +#define bFM_USB0_EP3S_BUSY *((volatile uint16_t*)(0x42842AACUL)) +#define bFM4_USB0_EP3S_BUSY *((volatile uint16_t*)(0x42842AACUL)) +#define bFM_USB0_EP3S_SPKIE *((volatile uint16_t*)(0x42842AB4UL)) +#define bFM4_USB0_EP3S_SPKIE *((volatile uint16_t*)(0x42842AB4UL)) +#define bFM_USB0_EP3S_DRQIE *((volatile uint16_t*)(0x42842AB8UL)) +#define bFM4_USB0_EP3S_DRQIE *((volatile uint16_t*)(0x42842AB8UL)) +#define bFM_USB0_EP3S_BFINI *((volatile uint16_t*)(0x42842ABCUL)) +#define bFM4_USB0_EP3S_BFINI *((volatile uint16_t*)(0x42842ABCUL)) + +#define bFM_USB0_EP4C_STAL *((volatile uint16_t*)(0x428426A4UL)) +#define bFM4_USB0_EP4C_STAL *((volatile uint16_t*)(0x428426A4UL)) +#define bFM_USB0_EP4C_NULE *((volatile uint16_t*)(0x428426A8UL)) +#define bFM4_USB0_EP4C_NULE *((volatile uint16_t*)(0x428426A8UL)) +#define bFM_USB0_EP4C_DMAE *((volatile uint16_t*)(0x428426ACUL)) +#define bFM4_USB0_EP4C_DMAE *((volatile uint16_t*)(0x428426ACUL)) +#define bFM_USB0_EP4C_DIR *((volatile uint16_t*)(0x428426B0UL)) +#define bFM4_USB0_EP4C_DIR *((volatile uint16_t*)(0x428426B0UL)) +#define bFM_USB0_EP4C_EPEN *((volatile uint16_t*)(0x428426BCUL)) +#define bFM4_USB0_EP4C_EPEN *((volatile uint16_t*)(0x428426BCUL)) + +#define bFM_USB0_EP4S_SPK *((volatile uint16_t*)(0x42842B24UL)) +#define bFM4_USB0_EP4S_SPK *((volatile uint16_t*)(0x42842B24UL)) +#define bFM_USB0_EP4S_DRQ *((volatile uint16_t*)(0x42842B28UL)) +#define bFM4_USB0_EP4S_DRQ *((volatile uint16_t*)(0x42842B28UL)) +#define bFM_USB0_EP4S_BUSY *((volatile uint16_t*)(0x42842B2CUL)) +#define bFM4_USB0_EP4S_BUSY *((volatile uint16_t*)(0x42842B2CUL)) +#define bFM_USB0_EP4S_SPKIE *((volatile uint16_t*)(0x42842B34UL)) +#define bFM4_USB0_EP4S_SPKIE *((volatile uint16_t*)(0x42842B34UL)) +#define bFM_USB0_EP4S_DRQIE *((volatile uint16_t*)(0x42842B38UL)) +#define bFM4_USB0_EP4S_DRQIE *((volatile uint16_t*)(0x42842B38UL)) +#define bFM_USB0_EP4S_BFINI *((volatile uint16_t*)(0x42842B3CUL)) +#define bFM4_USB0_EP4S_BFINI *((volatile uint16_t*)(0x42842B3CUL)) + +#define bFM_USB0_EP5C_STAL *((volatile uint16_t*)(0x42842724UL)) +#define bFM4_USB0_EP5C_STAL *((volatile uint16_t*)(0x42842724UL)) +#define bFM_USB0_EP5C_NULE *((volatile uint16_t*)(0x42842728UL)) +#define bFM4_USB0_EP5C_NULE *((volatile uint16_t*)(0x42842728UL)) +#define bFM_USB0_EP5C_DMAE *((volatile uint16_t*)(0x4284272CUL)) +#define bFM4_USB0_EP5C_DMAE *((volatile uint16_t*)(0x4284272CUL)) +#define bFM_USB0_EP5C_DIR *((volatile uint16_t*)(0x42842730UL)) +#define bFM4_USB0_EP5C_DIR *((volatile uint16_t*)(0x42842730UL)) +#define bFM_USB0_EP5C_EPEN *((volatile uint16_t*)(0x4284273CUL)) +#define bFM4_USB0_EP5C_EPEN *((volatile uint16_t*)(0x4284273CUL)) + +#define bFM_USB0_EP5S_SPK *((volatile uint16_t*)(0x42842BA4UL)) +#define bFM4_USB0_EP5S_SPK *((volatile uint16_t*)(0x42842BA4UL)) +#define bFM_USB0_EP5S_DRQ *((volatile uint16_t*)(0x42842BA8UL)) +#define bFM4_USB0_EP5S_DRQ *((volatile uint16_t*)(0x42842BA8UL)) +#define bFM_USB0_EP5S_BUSY *((volatile uint16_t*)(0x42842BACUL)) +#define bFM4_USB0_EP5S_BUSY *((volatile uint16_t*)(0x42842BACUL)) +#define bFM_USB0_EP5S_SPKIE *((volatile uint16_t*)(0x42842BB4UL)) +#define bFM4_USB0_EP5S_SPKIE *((volatile uint16_t*)(0x42842BB4UL)) +#define bFM_USB0_EP5S_DRQIE *((volatile uint16_t*)(0x42842BB8UL)) +#define bFM4_USB0_EP5S_DRQIE *((volatile uint16_t*)(0x42842BB8UL)) +#define bFM_USB0_EP5S_BFINI *((volatile uint16_t*)(0x42842BBCUL)) +#define bFM4_USB0_EP5S_BFINI *((volatile uint16_t*)(0x42842BBCUL)) + +#define bFM_USB0_HCNT_HOST *((volatile uint8_t *)(0x42842000UL)) +#define bFM4_USB0_HCNT_HOST *((volatile uint8_t *)(0x42842000UL)) +#define bFM_USB0_HCNT_URST *((volatile uint8_t *)(0x42842004UL)) +#define bFM4_USB0_HCNT_URST *((volatile uint8_t *)(0x42842004UL)) +#define bFM_USB0_HCNT_SOFIRE *((volatile uint8_t *)(0x42842008UL)) +#define bFM4_USB0_HCNT_SOFIRE *((volatile uint8_t *)(0x42842008UL)) +#define bFM_USB0_HCNT_DIRE *((volatile uint8_t *)(0x4284200CUL)) +#define bFM4_USB0_HCNT_DIRE *((volatile uint8_t *)(0x4284200CUL)) +#define bFM_USB0_HCNT_CNNIRE *((volatile uint8_t *)(0x42842010UL)) +#define bFM4_USB0_HCNT_CNNIRE *((volatile uint8_t *)(0x42842010UL)) +#define bFM_USB0_HCNT_CMPIRE *((volatile uint8_t *)(0x42842014UL)) +#define bFM4_USB0_HCNT_CMPIRE *((volatile uint8_t *)(0x42842014UL)) +#define bFM_USB0_HCNT_URIRE *((volatile uint8_t *)(0x42842018UL)) +#define bFM4_USB0_HCNT_URIRE *((volatile uint8_t *)(0x42842018UL)) +#define bFM_USB0_HCNT_RWKIRE *((volatile uint8_t *)(0x4284201CUL)) +#define bFM4_USB0_HCNT_RWKIRE *((volatile uint8_t *)(0x4284201CUL)) +#define bFM_USB0_HCNT_RETRY *((volatile uint8_t *)(0x42842020UL)) +#define bFM4_USB0_HCNT_RETRY *((volatile uint8_t *)(0x42842020UL)) +#define bFM_USB0_HCNT_CANCEL *((volatile uint8_t *)(0x42842024UL)) +#define bFM4_USB0_HCNT_CANCEL *((volatile uint8_t *)(0x42842024UL)) +#define bFM_USB0_HCNT_SOFSTEP *((volatile uint8_t *)(0x42842028UL)) +#define bFM4_USB0_HCNT_SOFSTEP *((volatile uint8_t *)(0x42842028UL)) + +#define bFM_USB0_HERR_STUFF *((volatile uint8_t *)(0x428420A8UL)) +#define bFM4_USB0_HERR_STUFF *((volatile uint8_t *)(0x428420A8UL)) +#define bFM_USB0_HERR_TGERR *((volatile uint8_t *)(0x428420ACUL)) +#define bFM4_USB0_HERR_TGERR *((volatile uint8_t *)(0x428420ACUL)) +#define bFM_USB0_HERR_CRC *((volatile uint8_t *)(0x428420B0UL)) +#define bFM4_USB0_HERR_CRC *((volatile uint8_t *)(0x428420B0UL)) +#define bFM_USB0_HERR_TOUT *((volatile uint8_t *)(0x428420B4UL)) +#define bFM4_USB0_HERR_TOUT *((volatile uint8_t *)(0x428420B4UL)) +#define bFM_USB0_HERR_RERR *((volatile uint8_t *)(0x428420B8UL)) +#define bFM4_USB0_HERR_RERR *((volatile uint8_t *)(0x428420B8UL)) +#define bFM_USB0_HERR_LSTSOF *((volatile uint8_t *)(0x428420BCUL)) +#define bFM4_USB0_HERR_LSTSOF *((volatile uint8_t *)(0x428420BCUL)) + +#define bFM_USB0_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42842080UL)) +#define bFM4_USB0_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42842080UL)) +#define bFM_USB0_HIRQ_DIRQ *((volatile uint8_t *)(0x42842084UL)) +#define bFM4_USB0_HIRQ_DIRQ *((volatile uint8_t *)(0x42842084UL)) +#define bFM_USB0_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42842088UL)) +#define bFM4_USB0_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42842088UL)) +#define bFM_USB0_HIRQ_CMPIRQ *((volatile uint8_t *)(0x4284208CUL)) +#define bFM4_USB0_HIRQ_CMPIRQ *((volatile uint8_t *)(0x4284208CUL)) +#define bFM_USB0_HIRQ_URIRQ *((volatile uint8_t *)(0x42842090UL)) +#define bFM4_USB0_HIRQ_URIRQ *((volatile uint8_t *)(0x42842090UL)) +#define bFM_USB0_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42842094UL)) +#define bFM4_USB0_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42842094UL)) +#define bFM_USB0_HIRQ_TCAN *((volatile uint8_t *)(0x4284209CUL)) +#define bFM4_USB0_HIRQ_TCAN *((volatile uint8_t *)(0x4284209CUL)) + +#define bFM_USB0_HSTATE_CSTAT *((volatile uint8_t *)(0x42842100UL)) +#define bFM4_USB0_HSTATE_CSTAT *((volatile uint8_t *)(0x42842100UL)) +#define bFM_USB0_HSTATE_TMODE *((volatile uint8_t *)(0x42842104UL)) +#define bFM4_USB0_HSTATE_TMODE *((volatile uint8_t *)(0x42842104UL)) +#define bFM_USB0_HSTATE_SUSP *((volatile uint8_t *)(0x42842108UL)) +#define bFM4_USB0_HSTATE_SUSP *((volatile uint8_t *)(0x42842108UL)) +#define bFM_USB0_HSTATE_SOFBUSY *((volatile uint8_t *)(0x4284210CUL)) +#define bFM4_USB0_HSTATE_SOFBUSY *((volatile uint8_t *)(0x4284210CUL)) +#define bFM_USB0_HSTATE_CLKSEL *((volatile uint8_t *)(0x42842110UL)) +#define bFM4_USB0_HSTATE_CLKSEL *((volatile uint8_t *)(0x42842110UL)) +#define bFM_USB0_HSTATE_ALIVE *((volatile uint8_t *)(0x42842114UL)) +#define bFM4_USB0_HSTATE_ALIVE *((volatile uint8_t *)(0x42842114UL)) + +#define bFM_USB0_HTOKEN_TGGL *((volatile uint8_t *)(0x4284239CUL)) +#define bFM4_USB0_HTOKEN_TGGL *((volatile uint8_t *)(0x4284239CUL)) + +#define bFM_USB0_UDCC_PWC *((volatile uint8_t *)(0x42842400UL)) +#define bFM4_USB0_UDCC_PWC *((volatile uint8_t *)(0x42842400UL)) +#define bFM_USB0_UDCC_RFBK *((volatile uint8_t *)(0x42842404UL)) +#define bFM4_USB0_UDCC_RFBK *((volatile uint8_t *)(0x42842404UL)) +#define bFM_USB0_UDCC_STALCLREN *((volatile uint8_t *)(0x4284240CUL)) +#define bFM4_USB0_UDCC_STALCLREN *((volatile uint8_t *)(0x4284240CUL)) +#define bFM_USB0_UDCC_USTP *((volatile uint8_t *)(0x42842410UL)) +#define bFM4_USB0_UDCC_USTP *((volatile uint8_t *)(0x42842410UL)) +#define bFM_USB0_UDCC_HCONX *((volatile uint8_t *)(0x42842414UL)) +#define bFM4_USB0_UDCC_HCONX *((volatile uint8_t *)(0x42842414UL)) +#define bFM_USB0_UDCC_RESUM *((volatile uint8_t *)(0x42842418UL)) +#define bFM4_USB0_UDCC_RESUM *((volatile uint8_t *)(0x42842418UL)) +#define bFM_USB0_UDCC_RST *((volatile uint8_t *)(0x4284241CUL)) +#define bFM4_USB0_UDCC_RST *((volatile uint8_t *)(0x4284241CUL)) + +#define bFM_USB0_UDCIE_CONFIE *((volatile uint8_t *)(0x42842820UL)) +#define bFM4_USB0_UDCIE_CONFIE *((volatile uint8_t *)(0x42842820UL)) +#define bFM_USB0_UDCIE_CONFN *((volatile uint8_t *)(0x42842824UL)) +#define bFM4_USB0_UDCIE_CONFN *((volatile uint8_t *)(0x42842824UL)) +#define bFM_USB0_UDCIE_WKUPIE *((volatile uint8_t *)(0x42842828UL)) +#define bFM4_USB0_UDCIE_WKUPIE *((volatile uint8_t *)(0x42842828UL)) +#define bFM_USB0_UDCIE_BRSTIE *((volatile uint8_t *)(0x4284282CUL)) +#define bFM4_USB0_UDCIE_BRSTIE *((volatile uint8_t *)(0x4284282CUL)) +#define bFM_USB0_UDCIE_SOFIE *((volatile uint8_t *)(0x42842830UL)) +#define bFM4_USB0_UDCIE_SOFIE *((volatile uint8_t *)(0x42842830UL)) +#define bFM_USB0_UDCIE_SUSPIE *((volatile uint8_t *)(0x42842834UL)) +#define bFM4_USB0_UDCIE_SUSPIE *((volatile uint8_t *)(0x42842834UL)) + +#define bFM_USB0_UDCS_CONF *((volatile uint8_t *)(0x42842800UL)) +#define bFM4_USB0_UDCS_CONF *((volatile uint8_t *)(0x42842800UL)) +#define bFM_USB0_UDCS_SETP *((volatile uint8_t *)(0x42842804UL)) +#define bFM4_USB0_UDCS_SETP *((volatile uint8_t *)(0x42842804UL)) +#define bFM_USB0_UDCS_WKUP *((volatile uint8_t *)(0x42842808UL)) +#define bFM4_USB0_UDCS_WKUP *((volatile uint8_t *)(0x42842808UL)) +#define bFM_USB0_UDCS_BRST *((volatile uint8_t *)(0x4284280CUL)) +#define bFM4_USB0_UDCS_BRST *((volatile uint8_t *)(0x4284280CUL)) +#define bFM_USB0_UDCS_SOF *((volatile uint8_t *)(0x42842810UL)) +#define bFM4_USB0_UDCS_SOF *((volatile uint8_t *)(0x42842810UL)) +#define bFM_USB0_UDCS_SUSP *((volatile uint8_t *)(0x42842814UL)) +#define bFM4_USB0_UDCS_SUSP *((volatile uint8_t *)(0x42842814UL)) + + +/******************************************************************************* +* USB Registers USB1 +* Bitband Section +*******************************************************************************/ +#define bFM_USB1_EP0C_STAL *((volatile uint16_t*)(0x42A844A4UL)) +#define bFM4_USB1_EP0C_STAL *((volatile uint16_t*)(0x42A844A4UL)) + +#define bFM_USB1_EP0IS_DRQI *((volatile uint16_t*)(0x42A848A8UL)) +#define bFM4_USB1_EP0IS_DRQI *((volatile uint16_t*)(0x42A848A8UL)) +#define bFM_USB1_EP0IS_DRQIIE *((volatile uint16_t*)(0x42A848B8UL)) +#define bFM4_USB1_EP0IS_DRQIIE *((volatile uint16_t*)(0x42A848B8UL)) +#define bFM_USB1_EP0IS_BFINI *((volatile uint16_t*)(0x42A848BCUL)) +#define bFM4_USB1_EP0IS_BFINI *((volatile uint16_t*)(0x42A848BCUL)) + +#define bFM_USB1_EP0OS_SPK *((volatile uint16_t*)(0x42A84924UL)) +#define bFM4_USB1_EP0OS_SPK *((volatile uint16_t*)(0x42A84924UL)) +#define bFM_USB1_EP0OS_DRQO *((volatile uint16_t*)(0x42A84928UL)) +#define bFM4_USB1_EP0OS_DRQO *((volatile uint16_t*)(0x42A84928UL)) +#define bFM_USB1_EP0OS_SPKIE *((volatile uint16_t*)(0x42A84934UL)) +#define bFM4_USB1_EP0OS_SPKIE *((volatile uint16_t*)(0x42A84934UL)) +#define bFM_USB1_EP0OS_DRQOIE *((volatile uint16_t*)(0x42A84938UL)) +#define bFM4_USB1_EP0OS_DRQOIE *((volatile uint16_t*)(0x42A84938UL)) +#define bFM_USB1_EP0OS_BFINI *((volatile uint16_t*)(0x42A8493CUL)) +#define bFM4_USB1_EP0OS_BFINI *((volatile uint16_t*)(0x42A8493CUL)) + +#define bFM_USB1_EP1C_STAL *((volatile uint16_t*)(0x42A84524UL)) +#define bFM4_USB1_EP1C_STAL *((volatile uint16_t*)(0x42A84524UL)) +#define bFM_USB1_EP1C_NULE *((volatile uint16_t*)(0x42A84528UL)) +#define bFM4_USB1_EP1C_NULE *((volatile uint16_t*)(0x42A84528UL)) +#define bFM_USB1_EP1C_DMAE *((volatile uint16_t*)(0x42A8452CUL)) +#define bFM4_USB1_EP1C_DMAE *((volatile uint16_t*)(0x42A8452CUL)) +#define bFM_USB1_EP1C_DIR *((volatile uint16_t*)(0x42A84530UL)) +#define bFM4_USB1_EP1C_DIR *((volatile uint16_t*)(0x42A84530UL)) +#define bFM_USB1_EP1C_EPEN *((volatile uint16_t*)(0x42A8453CUL)) +#define bFM4_USB1_EP1C_EPEN *((volatile uint16_t*)(0x42A8453CUL)) + +#define bFM_USB1_EP1S_SPK *((volatile uint16_t*)(0x42A849A4UL)) +#define bFM4_USB1_EP1S_SPK *((volatile uint16_t*)(0x42A849A4UL)) +#define bFM_USB1_EP1S_DRQ *((volatile uint16_t*)(0x42A849A8UL)) +#define bFM4_USB1_EP1S_DRQ *((volatile uint16_t*)(0x42A849A8UL)) +#define bFM_USB1_EP1S_BUSY *((volatile uint16_t*)(0x42A849ACUL)) +#define bFM4_USB1_EP1S_BUSY *((volatile uint16_t*)(0x42A849ACUL)) +#define bFM_USB1_EP1S_SPKIE *((volatile uint16_t*)(0x42A849B4UL)) +#define bFM4_USB1_EP1S_SPKIE *((volatile uint16_t*)(0x42A849B4UL)) +#define bFM_USB1_EP1S_DRQIE *((volatile uint16_t*)(0x42A849B8UL)) +#define bFM4_USB1_EP1S_DRQIE *((volatile uint16_t*)(0x42A849B8UL)) +#define bFM_USB1_EP1S_BFINI *((volatile uint16_t*)(0x42A849BCUL)) +#define bFM4_USB1_EP1S_BFINI *((volatile uint16_t*)(0x42A849BCUL)) + +#define bFM_USB1_EP2C_STAL *((volatile uint16_t*)(0x42A845A4UL)) +#define bFM4_USB1_EP2C_STAL *((volatile uint16_t*)(0x42A845A4UL)) +#define bFM_USB1_EP2C_NULE *((volatile uint16_t*)(0x42A845A8UL)) +#define bFM4_USB1_EP2C_NULE *((volatile uint16_t*)(0x42A845A8UL)) +#define bFM_USB1_EP2C_DMAE *((volatile uint16_t*)(0x42A845ACUL)) +#define bFM4_USB1_EP2C_DMAE *((volatile uint16_t*)(0x42A845ACUL)) +#define bFM_USB1_EP2C_DIR *((volatile uint16_t*)(0x42A845B0UL)) +#define bFM4_USB1_EP2C_DIR *((volatile uint16_t*)(0x42A845B0UL)) +#define bFM_USB1_EP2C_EPEN *((volatile uint16_t*)(0x42A845BCUL)) +#define bFM4_USB1_EP2C_EPEN *((volatile uint16_t*)(0x42A845BCUL)) + +#define bFM_USB1_EP2S_SPK *((volatile uint16_t*)(0x42A84A24UL)) +#define bFM4_USB1_EP2S_SPK *((volatile uint16_t*)(0x42A84A24UL)) +#define bFM_USB1_EP2S_DRQ *((volatile uint16_t*)(0x42A84A28UL)) +#define bFM4_USB1_EP2S_DRQ *((volatile uint16_t*)(0x42A84A28UL)) +#define bFM_USB1_EP2S_BUSY *((volatile uint16_t*)(0x42A84A2CUL)) +#define bFM4_USB1_EP2S_BUSY *((volatile uint16_t*)(0x42A84A2CUL)) +#define bFM_USB1_EP2S_SPKIE *((volatile uint16_t*)(0x42A84A34UL)) +#define bFM4_USB1_EP2S_SPKIE *((volatile uint16_t*)(0x42A84A34UL)) +#define bFM_USB1_EP2S_DRQIE *((volatile uint16_t*)(0x42A84A38UL)) +#define bFM4_USB1_EP2S_DRQIE *((volatile uint16_t*)(0x42A84A38UL)) +#define bFM_USB1_EP2S_BFINI *((volatile uint16_t*)(0x42A84A3CUL)) +#define bFM4_USB1_EP2S_BFINI *((volatile uint16_t*)(0x42A84A3CUL)) + +#define bFM_USB1_EP3C_STAL *((volatile uint16_t*)(0x42A84624UL)) +#define bFM4_USB1_EP3C_STAL *((volatile uint16_t*)(0x42A84624UL)) +#define bFM_USB1_EP3C_NULE *((volatile uint16_t*)(0x42A84628UL)) +#define bFM4_USB1_EP3C_NULE *((volatile uint16_t*)(0x42A84628UL)) +#define bFM_USB1_EP3C_DMAE *((volatile uint16_t*)(0x42A8462CUL)) +#define bFM4_USB1_EP3C_DMAE *((volatile uint16_t*)(0x42A8462CUL)) +#define bFM_USB1_EP3C_DIR *((volatile uint16_t*)(0x42A84630UL)) +#define bFM4_USB1_EP3C_DIR *((volatile uint16_t*)(0x42A84630UL)) +#define bFM_USB1_EP3C_EPEN *((volatile uint16_t*)(0x42A8463CUL)) +#define bFM4_USB1_EP3C_EPEN *((volatile uint16_t*)(0x42A8463CUL)) + +#define bFM_USB1_EP3S_SPK *((volatile uint16_t*)(0x42A84AA4UL)) +#define bFM4_USB1_EP3S_SPK *((volatile uint16_t*)(0x42A84AA4UL)) +#define bFM_USB1_EP3S_DRQ *((volatile uint16_t*)(0x42A84AA8UL)) +#define bFM4_USB1_EP3S_DRQ *((volatile uint16_t*)(0x42A84AA8UL)) +#define bFM_USB1_EP3S_BUSY *((volatile uint16_t*)(0x42A84AACUL)) +#define bFM4_USB1_EP3S_BUSY *((volatile uint16_t*)(0x42A84AACUL)) +#define bFM_USB1_EP3S_SPKIE *((volatile uint16_t*)(0x42A84AB4UL)) +#define bFM4_USB1_EP3S_SPKIE *((volatile uint16_t*)(0x42A84AB4UL)) +#define bFM_USB1_EP3S_DRQIE *((volatile uint16_t*)(0x42A84AB8UL)) +#define bFM4_USB1_EP3S_DRQIE *((volatile uint16_t*)(0x42A84AB8UL)) +#define bFM_USB1_EP3S_BFINI *((volatile uint16_t*)(0x42A84ABCUL)) +#define bFM4_USB1_EP3S_BFINI *((volatile uint16_t*)(0x42A84ABCUL)) + +#define bFM_USB1_EP4C_STAL *((volatile uint16_t*)(0x42A846A4UL)) +#define bFM4_USB1_EP4C_STAL *((volatile uint16_t*)(0x42A846A4UL)) +#define bFM_USB1_EP4C_NULE *((volatile uint16_t*)(0x42A846A8UL)) +#define bFM4_USB1_EP4C_NULE *((volatile uint16_t*)(0x42A846A8UL)) +#define bFM_USB1_EP4C_DMAE *((volatile uint16_t*)(0x42A846ACUL)) +#define bFM4_USB1_EP4C_DMAE *((volatile uint16_t*)(0x42A846ACUL)) +#define bFM_USB1_EP4C_DIR *((volatile uint16_t*)(0x42A846B0UL)) +#define bFM4_USB1_EP4C_DIR *((volatile uint16_t*)(0x42A846B0UL)) +#define bFM_USB1_EP4C_EPEN *((volatile uint16_t*)(0x42A846BCUL)) +#define bFM4_USB1_EP4C_EPEN *((volatile uint16_t*)(0x42A846BCUL)) + +#define bFM_USB1_EP4S_SPK *((volatile uint16_t*)(0x42A84B24UL)) +#define bFM4_USB1_EP4S_SPK *((volatile uint16_t*)(0x42A84B24UL)) +#define bFM_USB1_EP4S_DRQ *((volatile uint16_t*)(0x42A84B28UL)) +#define bFM4_USB1_EP4S_DRQ *((volatile uint16_t*)(0x42A84B28UL)) +#define bFM_USB1_EP4S_BUSY *((volatile uint16_t*)(0x42A84B2CUL)) +#define bFM4_USB1_EP4S_BUSY *((volatile uint16_t*)(0x42A84B2CUL)) +#define bFM_USB1_EP4S_SPKIE *((volatile uint16_t*)(0x42A84B34UL)) +#define bFM4_USB1_EP4S_SPKIE *((volatile uint16_t*)(0x42A84B34UL)) +#define bFM_USB1_EP4S_DRQIE *((volatile uint16_t*)(0x42A84B38UL)) +#define bFM4_USB1_EP4S_DRQIE *((volatile uint16_t*)(0x42A84B38UL)) +#define bFM_USB1_EP4S_BFINI *((volatile uint16_t*)(0x42A84B3CUL)) +#define bFM4_USB1_EP4S_BFINI *((volatile uint16_t*)(0x42A84B3CUL)) + +#define bFM_USB1_EP5C_STAL *((volatile uint16_t*)(0x42A84724UL)) +#define bFM4_USB1_EP5C_STAL *((volatile uint16_t*)(0x42A84724UL)) +#define bFM_USB1_EP5C_NULE *((volatile uint16_t*)(0x42A84728UL)) +#define bFM4_USB1_EP5C_NULE *((volatile uint16_t*)(0x42A84728UL)) +#define bFM_USB1_EP5C_DMAE *((volatile uint16_t*)(0x42A8472CUL)) +#define bFM4_USB1_EP5C_DMAE *((volatile uint16_t*)(0x42A8472CUL)) +#define bFM_USB1_EP5C_DIR *((volatile uint16_t*)(0x42A84730UL)) +#define bFM4_USB1_EP5C_DIR *((volatile uint16_t*)(0x42A84730UL)) +#define bFM_USB1_EP5C_EPEN *((volatile uint16_t*)(0x42A8473CUL)) +#define bFM4_USB1_EP5C_EPEN *((volatile uint16_t*)(0x42A8473CUL)) + +#define bFM_USB1_EP5S_SPK *((volatile uint16_t*)(0x42A84BA4UL)) +#define bFM4_USB1_EP5S_SPK *((volatile uint16_t*)(0x42A84BA4UL)) +#define bFM_USB1_EP5S_DRQ *((volatile uint16_t*)(0x42A84BA8UL)) +#define bFM4_USB1_EP5S_DRQ *((volatile uint16_t*)(0x42A84BA8UL)) +#define bFM_USB1_EP5S_BUSY *((volatile uint16_t*)(0x42A84BACUL)) +#define bFM4_USB1_EP5S_BUSY *((volatile uint16_t*)(0x42A84BACUL)) +#define bFM_USB1_EP5S_SPKIE *((volatile uint16_t*)(0x42A84BB4UL)) +#define bFM4_USB1_EP5S_SPKIE *((volatile uint16_t*)(0x42A84BB4UL)) +#define bFM_USB1_EP5S_DRQIE *((volatile uint16_t*)(0x42A84BB8UL)) +#define bFM4_USB1_EP5S_DRQIE *((volatile uint16_t*)(0x42A84BB8UL)) +#define bFM_USB1_EP5S_BFINI *((volatile uint16_t*)(0x42A84BBCUL)) +#define bFM4_USB1_EP5S_BFINI *((volatile uint16_t*)(0x42A84BBCUL)) + +#define bFM_USB1_HCNT_HOST *((volatile uint8_t *)(0x42A84000UL)) +#define bFM4_USB1_HCNT_HOST *((volatile uint8_t *)(0x42A84000UL)) +#define bFM_USB1_HCNT_URST *((volatile uint8_t *)(0x42A84004UL)) +#define bFM4_USB1_HCNT_URST *((volatile uint8_t *)(0x42A84004UL)) +#define bFM_USB1_HCNT_SOFIRE *((volatile uint8_t *)(0x42A84008UL)) +#define bFM4_USB1_HCNT_SOFIRE *((volatile uint8_t *)(0x42A84008UL)) +#define bFM_USB1_HCNT_DIRE *((volatile uint8_t *)(0x42A8400CUL)) +#define bFM4_USB1_HCNT_DIRE *((volatile uint8_t *)(0x42A8400CUL)) +#define bFM_USB1_HCNT_CNNIRE *((volatile uint8_t *)(0x42A84010UL)) +#define bFM4_USB1_HCNT_CNNIRE *((volatile uint8_t *)(0x42A84010UL)) +#define bFM_USB1_HCNT_CMPIRE *((volatile uint8_t *)(0x42A84014UL)) +#define bFM4_USB1_HCNT_CMPIRE *((volatile uint8_t *)(0x42A84014UL)) +#define bFM_USB1_HCNT_URIRE *((volatile uint8_t *)(0x42A84018UL)) +#define bFM4_USB1_HCNT_URIRE *((volatile uint8_t *)(0x42A84018UL)) +#define bFM_USB1_HCNT_RWKIRE *((volatile uint8_t *)(0x42A8401CUL)) +#define bFM4_USB1_HCNT_RWKIRE *((volatile uint8_t *)(0x42A8401CUL)) +#define bFM_USB1_HCNT_RETRY *((volatile uint8_t *)(0x42A84020UL)) +#define bFM4_USB1_HCNT_RETRY *((volatile uint8_t *)(0x42A84020UL)) +#define bFM_USB1_HCNT_CANCEL *((volatile uint8_t *)(0x42A84024UL)) +#define bFM4_USB1_HCNT_CANCEL *((volatile uint8_t *)(0x42A84024UL)) +#define bFM_USB1_HCNT_SOFSTEP *((volatile uint8_t *)(0x42A84028UL)) +#define bFM4_USB1_HCNT_SOFSTEP *((volatile uint8_t *)(0x42A84028UL)) + +#define bFM_USB1_HERR_STUFF *((volatile uint8_t *)(0x42A840A8UL)) +#define bFM4_USB1_HERR_STUFF *((volatile uint8_t *)(0x42A840A8UL)) +#define bFM_USB1_HERR_TGERR *((volatile uint8_t *)(0x42A840ACUL)) +#define bFM4_USB1_HERR_TGERR *((volatile uint8_t *)(0x42A840ACUL)) +#define bFM_USB1_HERR_CRC *((volatile uint8_t *)(0x42A840B0UL)) +#define bFM4_USB1_HERR_CRC *((volatile uint8_t *)(0x42A840B0UL)) +#define bFM_USB1_HERR_TOUT *((volatile uint8_t *)(0x42A840B4UL)) +#define bFM4_USB1_HERR_TOUT *((volatile uint8_t *)(0x42A840B4UL)) +#define bFM_USB1_HERR_RERR *((volatile uint8_t *)(0x42A840B8UL)) +#define bFM4_USB1_HERR_RERR *((volatile uint8_t *)(0x42A840B8UL)) +#define bFM_USB1_HERR_LSTSOF *((volatile uint8_t *)(0x42A840BCUL)) +#define bFM4_USB1_HERR_LSTSOF *((volatile uint8_t *)(0x42A840BCUL)) + +#define bFM_USB1_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42A84080UL)) +#define bFM4_USB1_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42A84080UL)) +#define bFM_USB1_HIRQ_DIRQ *((volatile uint8_t *)(0x42A84084UL)) +#define bFM4_USB1_HIRQ_DIRQ *((volatile uint8_t *)(0x42A84084UL)) +#define bFM_USB1_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42A84088UL)) +#define bFM4_USB1_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42A84088UL)) +#define bFM_USB1_HIRQ_CMPIRQ *((volatile uint8_t *)(0x42A8408CUL)) +#define bFM4_USB1_HIRQ_CMPIRQ *((volatile uint8_t *)(0x42A8408CUL)) +#define bFM_USB1_HIRQ_URIRQ *((volatile uint8_t *)(0x42A84090UL)) +#define bFM4_USB1_HIRQ_URIRQ *((volatile uint8_t *)(0x42A84090UL)) +#define bFM_USB1_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42A84094UL)) +#define bFM4_USB1_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42A84094UL)) +#define bFM_USB1_HIRQ_TCAN *((volatile uint8_t *)(0x42A8409CUL)) +#define bFM4_USB1_HIRQ_TCAN *((volatile uint8_t *)(0x42A8409CUL)) + +#define bFM_USB1_HSTATE_CSTAT *((volatile uint8_t *)(0x42A84100UL)) +#define bFM4_USB1_HSTATE_CSTAT *((volatile uint8_t *)(0x42A84100UL)) +#define bFM_USB1_HSTATE_TMODE *((volatile uint8_t *)(0x42A84104UL)) +#define bFM4_USB1_HSTATE_TMODE *((volatile uint8_t *)(0x42A84104UL)) +#define bFM_USB1_HSTATE_SUSP *((volatile uint8_t *)(0x42A84108UL)) +#define bFM4_USB1_HSTATE_SUSP *((volatile uint8_t *)(0x42A84108UL)) +#define bFM_USB1_HSTATE_SOFBUSY *((volatile uint8_t *)(0x42A8410CUL)) +#define bFM4_USB1_HSTATE_SOFBUSY *((volatile uint8_t *)(0x42A8410CUL)) +#define bFM_USB1_HSTATE_CLKSEL *((volatile uint8_t *)(0x42A84110UL)) +#define bFM4_USB1_HSTATE_CLKSEL *((volatile uint8_t *)(0x42A84110UL)) +#define bFM_USB1_HSTATE_ALIVE *((volatile uint8_t *)(0x42A84114UL)) +#define bFM4_USB1_HSTATE_ALIVE *((volatile uint8_t *)(0x42A84114UL)) + +#define bFM_USB1_HTOKEN_TGGL *((volatile uint8_t *)(0x42A8439CUL)) +#define bFM4_USB1_HTOKEN_TGGL *((volatile uint8_t *)(0x42A8439CUL)) + +#define bFM_USB1_UDCC_PWC *((volatile uint8_t *)(0x42A84400UL)) +#define bFM4_USB1_UDCC_PWC *((volatile uint8_t *)(0x42A84400UL)) +#define bFM_USB1_UDCC_RFBK *((volatile uint8_t *)(0x42A84404UL)) +#define bFM4_USB1_UDCC_RFBK *((volatile uint8_t *)(0x42A84404UL)) +#define bFM_USB1_UDCC_STALCLREN *((volatile uint8_t *)(0x42A8440CUL)) +#define bFM4_USB1_UDCC_STALCLREN *((volatile uint8_t *)(0x42A8440CUL)) +#define bFM_USB1_UDCC_USTP *((volatile uint8_t *)(0x42A84410UL)) +#define bFM4_USB1_UDCC_USTP *((volatile uint8_t *)(0x42A84410UL)) +#define bFM_USB1_UDCC_HCONX *((volatile uint8_t *)(0x42A84414UL)) +#define bFM4_USB1_UDCC_HCONX *((volatile uint8_t *)(0x42A84414UL)) +#define bFM_USB1_UDCC_RESUM *((volatile uint8_t *)(0x42A84418UL)) +#define bFM4_USB1_UDCC_RESUM *((volatile uint8_t *)(0x42A84418UL)) +#define bFM_USB1_UDCC_RST *((volatile uint8_t *)(0x42A8441CUL)) +#define bFM4_USB1_UDCC_RST *((volatile uint8_t *)(0x42A8441CUL)) + +#define bFM_USB1_UDCIE_CONFIE *((volatile uint8_t *)(0x42A84820UL)) +#define bFM4_USB1_UDCIE_CONFIE *((volatile uint8_t *)(0x42A84820UL)) +#define bFM_USB1_UDCIE_CONFN *((volatile uint8_t *)(0x42A84824UL)) +#define bFM4_USB1_UDCIE_CONFN *((volatile uint8_t *)(0x42A84824UL)) +#define bFM_USB1_UDCIE_WKUPIE *((volatile uint8_t *)(0x42A84828UL)) +#define bFM4_USB1_UDCIE_WKUPIE *((volatile uint8_t *)(0x42A84828UL)) +#define bFM_USB1_UDCIE_BRSTIE *((volatile uint8_t *)(0x42A8482CUL)) +#define bFM4_USB1_UDCIE_BRSTIE *((volatile uint8_t *)(0x42A8482CUL)) +#define bFM_USB1_UDCIE_SOFIE *((volatile uint8_t *)(0x42A84830UL)) +#define bFM4_USB1_UDCIE_SOFIE *((volatile uint8_t *)(0x42A84830UL)) +#define bFM_USB1_UDCIE_SUSPIE *((volatile uint8_t *)(0x42A84834UL)) +#define bFM4_USB1_UDCIE_SUSPIE *((volatile uint8_t *)(0x42A84834UL)) + +#define bFM_USB1_UDCS_CONF *((volatile uint8_t *)(0x42A84800UL)) +#define bFM4_USB1_UDCS_CONF *((volatile uint8_t *)(0x42A84800UL)) +#define bFM_USB1_UDCS_SETP *((volatile uint8_t *)(0x42A84804UL)) +#define bFM4_USB1_UDCS_SETP *((volatile uint8_t *)(0x42A84804UL)) +#define bFM_USB1_UDCS_WKUP *((volatile uint8_t *)(0x42A84808UL)) +#define bFM4_USB1_UDCS_WKUP *((volatile uint8_t *)(0x42A84808UL)) +#define bFM_USB1_UDCS_BRST *((volatile uint8_t *)(0x42A8480CUL)) +#define bFM4_USB1_UDCS_BRST *((volatile uint8_t *)(0x42A8480CUL)) +#define bFM_USB1_UDCS_SOF *((volatile uint8_t *)(0x42A84810UL)) +#define bFM4_USB1_UDCS_SOF *((volatile uint8_t *)(0x42A84810UL)) +#define bFM_USB1_UDCS_SUSP *((volatile uint8_t *)(0x42A84814UL)) +#define bFM4_USB1_UDCS_SUSP *((volatile uint8_t *)(0x42A84814UL)) + + +/******************************************************************************* +* USBCLK Registers USBCLK +* Bitband Section +*******************************************************************************/ +#define bFM_USBCLK_UCCR_UCEN0 *((volatile uint8_t *)(0x426C0000UL)) +#define bFM4_USBCLK_UCCR_UCEN0 *((volatile uint8_t *)(0x426C0000UL)) +#define bFM_USBCLK_UCCR_UCSEL *((volatile uint8_t *)(0x426C0004UL)) +#define bFM4_USBCLK_UCCR_UCSEL *((volatile uint8_t *)(0x426C0004UL)) +#define bFM_USBCLK_UCCR_UCEN1 *((volatile uint8_t *)(0x426C000CUL)) +#define bFM4_USBCLK_UCCR_UCEN1 *((volatile uint8_t *)(0x426C000CUL)) + +#define bFM_USBCLK_UP_STR_UPRDY *((volatile uint8_t *)(0x426C0280UL)) +#define bFM4_USBCLK_UP_STR_UPRDY *((volatile uint8_t *)(0x426C0280UL)) + +#define bFM_USBCLK_UPCR1_UPLLEN *((volatile uint8_t *)(0x426C0080UL)) +#define bFM4_USBCLK_UPCR1_UPLLEN *((volatile uint8_t *)(0x426C0080UL)) +#define bFM_USBCLK_UPCR1_UPINC *((volatile uint8_t *)(0x426C0084UL)) +#define bFM4_USBCLK_UPCR1_UPINC *((volatile uint8_t *)(0x426C0084UL)) + +#define bFM_USBCLK_UPINT_CLR_UPCSC *((volatile uint8_t *)(0x426C0380UL)) +#define bFM4_USBCLK_UPINT_CLR_UPCSC *((volatile uint8_t *)(0x426C0380UL)) + +#define bFM_USBCLK_UPINT_ENR_UPCSE *((volatile uint8_t *)(0x426C0300UL)) +#define bFM4_USBCLK_UPINT_ENR_UPCSE *((volatile uint8_t *)(0x426C0300UL)) + +#define bFM_USBCLK_UPINT_STR_UPCSI *((volatile uint8_t *)(0x426C0400UL)) +#define bFM4_USBCLK_UPINT_STR_UPCSI *((volatile uint8_t *)(0x426C0400UL)) + +#define bFM_USBCLK_USBEN0_USBEN0 *((volatile uint8_t *)(0x426C0600UL)) +#define bFM4_USBCLK_USBEN0_USBEN0 *((volatile uint8_t *)(0x426C0600UL)) + +#define bFM_USBCLK_USBEN1_USBEN1 *((volatile uint8_t *)(0x426C0680UL)) +#define bFM4_USBCLK_USBEN1_USBEN1 *((volatile uint8_t *)(0x426C0680UL)) + + +/******************************************************************************* +* WC Registers WC +* Bitband Section +*******************************************************************************/ +#define bFM_WC_CLK_EN_CLK_EN *((volatile uint8_t *)(0x42740280UL)) +#define bFM4_WC_CLK_EN_CLK_EN *((volatile uint8_t *)(0x42740280UL)) +#define bFM_WC_CLK_EN_CLK_EN_R *((volatile uint8_t *)(0x42740284UL)) +#define bFM4_WC_CLK_EN_CLK_EN_R *((volatile uint8_t *)(0x42740284UL)) + +#define bFM_WC_WCCR_WCIF *((volatile uint8_t *)(0x42740040UL)) +#define bFM4_WC_WCCR_WCIF *((volatile uint8_t *)(0x42740040UL)) +#define bFM_WC_WCCR_WCIE *((volatile uint8_t *)(0x42740044UL)) +#define bFM4_WC_WCCR_WCIE *((volatile uint8_t *)(0x42740044UL)) +#define bFM_WC_WCCR_WCOP *((volatile uint8_t *)(0x42740058UL)) +#define bFM4_WC_WCCR_WCOP *((volatile uint8_t *)(0x42740058UL)) +#define bFM_WC_WCCR_WCEN *((volatile uint8_t *)(0x4274005CUL)) +#define bFM4_WC_WCCR_WCEN *((volatile uint8_t *)(0x4274005CUL)) + + +#if defined __cplusplus +} +#endif + +#endif /* _S6E2C5XH_H_ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xl.h b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xl.h new file mode 100644 index 0000000000..f1ca191291 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/s6e2c5xl.h @@ -0,0 +1,72329 @@ +/******************************************************************************* +* \file s6e2c5xl.h +* +* \version 1.0 +* +* \date 7/29/2016 +* +* \brief CMSIS Core Peripheral Access Layer Header File for s6e2c5xl Device +* +******************************************************************************** +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef _S6E2C5XL_H_ +#define _S6E2C5XL_H_ +#define __S6E2C5XL_H__ +#define __S6E2C5_H__ + +#if defined __cplusplus +extern "C" { +#endif + +#define FM_GENERAL_MCUHEADER_VERSION 0201 + + +#ifndef FM_DEVICE_PACKAGE_S6E_L +#define FM_DEVICE_PACKAGE_S6E_L +#endif + +/******************************************************************************* +* Configuration of the Cortex-M4 Processor and Core Peripherals +*******************************************************************************/ +#define FM4_DEVICE_TYPE 3 +#define FM_DEVICE_TYPE 4003u +#define FM_CORE_TYPE_FM4 1 +#define __CM4_REV 0x0001 +#define __MPU_PRESENT 1 +#define __NVIC_PRIO_BITS 4 +#define __Vendor_SysTickConfig 0 +#define __FPU_PRESENT 1 +#define __FPU_DP 0 +#define __ICACHE_PRESENT 0 +#define __DCACHE_PRESENT 0 +#define __DTCM_PRESENT 0 + +/******************************************************************************* +* Peripheral Types +*******************************************************************************/ +#define FM4_ADC_TYPE_A 1 +#define FM4_BT_TYPE_A 1 +#define FM4_BTIOSEL03_TYPE_A 1 +#define FM4_BTIOSEL47_TYPE_A 1 +#define FM4_BTIOSEL8B_TYPE_A 1 +#define FM4_BTIOSELCF_TYPE_A 1 +#define FM4_CAN_TYPE_A 1 +#define FM4_CANFD_TYPE_A 1 +#define FM4_CANPRES_TYPE_A 1 +#define FM4_CLK_GATING_TYPE_B 1 +#define FM4_CRC_TYPE_A 1 +#define FM4_CRG_TYPE_B 1 +#define FM4_CRTRIM_TYPE_A 1 +#define FM4_DAC_TYPE_A 1 +#define FM4_DMAC_TYPE_A 1 +#define FM4_DS_TYPE_A 1 +#define FM4_DSTC_TYPE_A 1 +#define FM4_DT_TYPE_A 1 +#define FM4_DUALFLASH_IF_TYPE_A 1 +#define FM4_ECC_CAPTURE_TYPE_A 1 +#define FM4_EXBUS_TYPE_B 1 +#define FM4_EXTI_TYPE_A 1 +#define FM4_FLASH_IF_TYPE_B 1 +#define FM4_GPIO_TYPE_B 1 +#define FM4_HSSPI_TYPE_A 1 +#define FM4_HWWDT_TYPE_A 1 +#define FM4_I2S_TYPE_A 1 +#define FM4_I2SPRE_TYPE_A 1 +#define FM4_INTREQ_TYPE_B 1 +#define FM4_LSCRP_TYPE_A 1 +#define FM4_LVD_TYPE_A 1 +#define FM4_MFS_TYPE_B 1 +#define FM4_MFT_TYPE_B 1 +#define FM4_MFT_PPG_TYPE_A 1 +#define FM4_PCRC_TYPE_A 1 +#define FM4_QPRC_TYPE_B 1 +#define FM4_QPRC_NF_TYPE_A 1 +#define FM4_RTC_TYPE_A 1 +#define FM4_SBSSR_TYPE_A 1 +#define FM4_SDIF_TYPE_A 1 +#define FM4_SWWDT_TYPE_A 1 +#define FM4_UNIQUE_ID_TYPE_A 1 +#define FM4_USB_TYPE_A 1 +#define FM4_USBCLK_TYPE_A 1 +#define FM4_WC_TYPE_A 1 + +/******************************************************************************* +* Available Peripherals +*******************************************************************************/ +#define FM4_ADC_AVAILABLE 1 +#define FM_ADC_AVAILABLE 1 +#define FM4_BT_AVAILABLE 1 +#define FM_BT_AVAILABLE 1 +#define FM4_BT_PPG_AVAILABLE 1 +#define FM_BT_PPG_AVAILABLE 1 +#define FM4_BT_PWC_AVAILABLE 1 +#define FM_BT_PWC_AVAILABLE 1 +#define FM4_BT_PWM_AVAILABLE 1 +#define FM_BT_PWM_AVAILABLE 1 +#define FM4_BT_RT_AVAILABLE 1 +#define FM_BT_RT_AVAILABLE 1 +#define FM4_BTIOSEL03_AVAILABLE 1 +#define FM_BTIOSEL03_AVAILABLE 1 +#define FM4_BTIOSEL47_AVAILABLE 1 +#define FM_BTIOSEL47_AVAILABLE 1 +#define FM4_BTIOSEL8B_AVAILABLE 1 +#define FM_BTIOSEL8B_AVAILABLE 1 +#define FM4_BTIOSELCF_AVAILABLE 1 +#define FM_BTIOSELCF_AVAILABLE 1 +#define FM4_CAN_AVAILABLE 1 +#define FM_CAN_AVAILABLE 1 +#define FM4_CANFD_AVAILABLE 1 +#define FM_CANFD_AVAILABLE 1 +#define FM4_CANPRES_AVAILABLE 1 +#define FM_CANPRES_AVAILABLE 1 +#define FM4_CLK_GATING_AVAILABLE 1 +#define FM_CLK_GATING_AVAILABLE 1 +#define FM4_CRC_AVAILABLE 1 +#define FM_CRC_AVAILABLE 1 +#define FM4_CRG_AVAILABLE 1 +#define FM_CRG_AVAILABLE 1 +#define FM4_CRTRIM_AVAILABLE 1 +#define FM_CRTRIM_AVAILABLE 1 +#define FM4_DAC_AVAILABLE 1 +#define FM_DAC_AVAILABLE 1 +#define FM4_DMAC_AVAILABLE 1 +#define FM_DMAC_AVAILABLE 1 +#define FM4_DS_AVAILABLE 1 +#define FM_DS_AVAILABLE 1 +#define FM4_DSTC_AVAILABLE 1 +#define FM_DSTC_AVAILABLE 1 +#define FM4_DT_AVAILABLE 1 +#define FM_DT_AVAILABLE 1 +#define FM4_DUALFLASH_IF_AVAILABLE 1 +#define FM_DUALFLASH_IF_AVAILABLE 1 +#define FM4_ECC_CAPTURE_AVAILABLE 1 +#define FM_ECC_CAPTURE_AVAILABLE 1 +#define FM4_EXBUS_AVAILABLE 1 +#define FM_EXBUS_AVAILABLE 1 +#define FM4_EXTI_AVAILABLE 1 +#define FM_EXTI_AVAILABLE 1 +#define FM4_FLASH_IF_AVAILABLE 1 +#define FM_FLASH_IF_AVAILABLE 1 +#define FM4_GPIO_AVAILABLE 1 +#define FM_GPIO_AVAILABLE 1 +#define FM4_HSSPI_AVAILABLE 1 +#define FM_HSSPI_AVAILABLE 1 +#define FM4_HWWDT_AVAILABLE 1 +#define FM_HWWDT_AVAILABLE 1 +#define FM4_I2S_AVAILABLE 1 +#define FM_I2S_AVAILABLE 1 +#define FM4_I2SPRE_AVAILABLE 1 +#define FM_I2SPRE_AVAILABLE 1 +#define FM4_INTREQ_AVAILABLE 1 +#define FM_INTREQ_AVAILABLE 1 +#define FM4_LSCRP_AVAILABLE 1 +#define FM_LSCRP_AVAILABLE 1 +#define FM4_LVD_AVAILABLE 1 +#define FM_LVD_AVAILABLE 1 +#define FM4_MFS_AVAILABLE 1 +#define FM_MFS_AVAILABLE 1 +#define FM4_MFS_CSIO_AVAILABLE 1 +#define FM_MFS_CSIO_AVAILABLE 1 +#define FM4_MFS_I2C_AVAILABLE 1 +#define FM_MFS_I2C_AVAILABLE 1 +#define FM4_MFS_LIN_AVAILABLE 1 +#define FM_MFS_LIN_AVAILABLE 1 +#define FM4_MFS_UART_AVAILABLE 1 +#define FM_MFS_UART_AVAILABLE 1 +#define FM4_MFT_AVAILABLE 1 +#define FM_MFT_AVAILABLE 1 +#define FM4_MFT_ADCMP_AVAILABLE 1 +#define FM_MFT_ADCMP_AVAILABLE 1 +#define FM4_MFT_FRT_AVAILABLE 1 +#define FM_MFT_FRT_AVAILABLE 1 +#define FM4_MFT_ICU_AVAILABLE 1 +#define FM_MFT_ICU_AVAILABLE 1 +#define FM4_MFT_OCU_AVAILABLE 1 +#define FM_MFT_OCU_AVAILABLE 1 +#define FM4_MFT_PPG_AVAILABLE 1 +#define FM_MFT_PPG_AVAILABLE 1 +#define FM4_MFT_WFG_AVAILABLE 1 +#define FM_MFT_WFG_AVAILABLE 1 +#define FM4_PCRC_AVAILABLE 1 +#define FM_PCRC_AVAILABLE 1 +#define FM4_QPRC_AVAILABLE 1 +#define FM_QPRC_AVAILABLE 1 +#define FM4_QPRC_NF_AVAILABLE 1 +#define FM_QPRC_NF_AVAILABLE 1 +#define FM4_RTC_AVAILABLE 1 +#define FM_RTC_AVAILABLE 1 +#define FM4_SBSSR_AVAILABLE 1 +#define FM_SBSSR_AVAILABLE 1 +#define FM4_SDIF_AVAILABLE 1 +#define FM_SDIF_AVAILABLE 1 +#define FM4_SWWDT_AVAILABLE 1 +#define FM_SWWDT_AVAILABLE 1 +#define FM4_UNIQUE_ID_AVAILABLE 1 +#define FM_UNIQUE_ID_AVAILABLE 1 +#define FM4_USB_AVAILABLE 1 +#define FM_USB_AVAILABLE 1 +#define FM4_USBCLK_AVAILABLE 1 +#define FM_USBCLK_AVAILABLE 1 +#define FM4_WC_AVAILABLE 1 +#define FM_WC_AVAILABLE 1 + +/******************************************************************************* +* \brief Interrupt number definition for all type MCUs +*******************************************************************************/ +#define FM_INTERRUPT_TYPE 0x400Bu + +#define IRQ_NMI_AVAILABLE 1 +#define IRQ_HARDFAULT_AVAILABLE 1 +#define IRQ_MEMMANAGE_AVAILABLE 1 +#define IRQ_BUSFAULT_AVAILABLE 1 +#define IRQ_USAGEFAULT_AVAILABLE 1 +#define IRQ_SVC_AVAILABLE 1 +#define IRQ_DEBUGMONITOR_AVAILABLE 1 +#define IRQ_PENDSV_AVAILABLE 1 +#define IRQ_SYSTICK_AVAILABLE 1 + +#define IRQ_CSV_AVAILABLE 1 +#define IRQ_SWDT_AVAILABLE 1 +#define IRQ_LVD_AVAILABLE 1 +#define IRQ_IRQ003SEL_AVAILABLE 1 +#define IRQ_IRQ004SEL_AVAILABLE 1 +#define IRQ_IRQ005SEL_AVAILABLE 1 +#define IRQ_IRQ006SEL_AVAILABLE 1 +#define IRQ_IRQ007SEL_AVAILABLE 1 +#define IRQ_IRQ008SEL_AVAILABLE 1 +#define IRQ_IRQ009SEL_AVAILABLE 1 +#define IRQ_IRQ010SEL_AVAILABLE 1 +#define IRQ_EXINT0_AVAILABLE 1 +#define IRQ_EXINT1_AVAILABLE 1 +#define IRQ_EXINT2_AVAILABLE 1 +#define IRQ_EXINT3_AVAILABLE 1 +#define IRQ_EXINT4_AVAILABLE 1 +#define IRQ_EXINT5_AVAILABLE 1 +#define IRQ_EXINT6_AVAILABLE 1 +#define IRQ_EXINT7_AVAILABLE 1 +#define IRQ_QPRC0_AVAILABLE 1 +#define IRQ_QPRC1_AVAILABLE 1 +#define IRQ_MFT0_WFG_DTIF_AVAILABLE 1 +#define IRQ_MFT1_WFG_DTIF_AVAILABLE 1 +#define IRQ_MFT2_WFG_DTIF_AVAILABLE 1 +#define IRQ_MFT0_FRT_PEAK_AVAILABLE 1 +#define IRQ_MFT0_FRT_ZERO_AVAILABLE 1 +#define IRQ_MFT0_ICU_AVAILABLE 1 +#define IRQ_MFT0_OCU_AVAILABLE 1 +#define IRQ_MFT1_FRT_PEAK_AVAILABLE 1 +#define IRQ_MFT1_FRT_ZERO_AVAILABLE 1 +#define IRQ_MFT1_ICU_AVAILABLE 1 +#define IRQ_MFT1_OCU_AVAILABLE 1 +#define IRQ_MFT2_FRT_PEAK_AVAILABLE 1 +#define IRQ_MFT2_FRT_ZERO_AVAILABLE 1 +#define IRQ_MFT2_ICU_AVAILABLE 1 +#define IRQ_MFT2_OCU_AVAILABLE 1 +#define IRQ_PPG00_02_04_AVAILABLE 1 +#define IRQ_PPG08_10_12_AVAILABLE 1 +#define IRQ_PPG16_18_20_AVAILABLE 1 +#define IRQ_BT0_AVAILABLE 1 +#define IRQ_BT1_AVAILABLE 1 +#define IRQ_BT2_AVAILABLE 1 +#define IRQ_BT3_AVAILABLE 1 +#define IRQ_BT4_AVAILABLE 1 +#define IRQ_BT5_AVAILABLE 1 +#define IRQ_BT6_AVAILABLE 1 +#define IRQ_BT7_AVAILABLE 1 +#define IRQ_DT_AVAILABLE 1 +#define IRQ_WC_AVAILABLE 1 +#define IRQ_EXTBUS_ERR_AVAILABLE 1 +#define IRQ_RTC_AVAILABLE 1 +#define IRQ_EXINT8_AVAILABLE 1 +#define IRQ_EXINT9_AVAILABLE 1 +#define IRQ_EXINT10_AVAILABLE 1 +#define IRQ_EXINT11_AVAILABLE 1 +#define IRQ_EXINT12_AVAILABLE 1 +#define IRQ_EXINT13_AVAILABLE 1 +#define IRQ_EXINT14_AVAILABLE 1 +#define IRQ_EXINT15_AVAILABLE 1 +#define IRQ_TIM_AVAILABLE 1 +#define IRQ_MFS0_RX_AVAILABLE 1 +#define IRQ_MFS0_TX_AVAILABLE 1 +#define IRQ_MFS1_RX_AVAILABLE 1 +#define IRQ_MFS1_TX_AVAILABLE 1 +#define IRQ_MFS2_RX_AVAILABLE 1 +#define IRQ_MFS2_TX_AVAILABLE 1 +#define IRQ_MFS3_RX_AVAILABLE 1 +#define IRQ_MFS3_TX_AVAILABLE 1 +#define IRQ_MFS4_RX_AVAILABLE 1 +#define IRQ_MFS4_TX_AVAILABLE 1 +#define IRQ_MFS5_RX_AVAILABLE 1 +#define IRQ_MFS5_TX_AVAILABLE 1 +#define IRQ_MFS6_RX_AVAILABLE 1 +#define IRQ_MFS6_TX_AVAILABLE 1 +#define IRQ_MFS7_RX_AVAILABLE 1 +#define IRQ_MFS7_TX_AVAILABLE 1 +#define IRQ_ADC0_AVAILABLE 1 +#define IRQ_ADC1_AVAILABLE 1 +#define IRQ_USB0_F_AVAILABLE 1 +#define IRQ_USB0_H_F_AVAILABLE 1 +#define IRQ_CAN0_AVAILABLE 1 +#define IRQ_CAN1_CANFD0_AVAILABLE 1 +#define IRQ_DMAC0_AVAILABLE 1 +#define IRQ_DMAC1_AVAILABLE 1 +#define IRQ_DMAC2_AVAILABLE 1 +#define IRQ_DMAC3_AVAILABLE 1 +#define IRQ_DMAC4_AVAILABLE 1 +#define IRQ_DMAC5_AVAILABLE 1 +#define IRQ_DMAC6_AVAILABLE 1 +#define IRQ_DMAC7_AVAILABLE 1 +#define IRQ_DSTC_AVAILABLE 1 +#define IRQ_EXINT16_19_AVAILABLE 1 +#define IRQ_EXINT20_23_AVAILABLE 1 +#define IRQ_EXINT24_27_AVAILABLE 1 +#define IRQ_EXINT28_31_AVAILABLE 1 +#define IRQ_QPRC2_AVAILABLE 1 +#define IRQ_QPRC3_AVAILABLE 1 +#define IRQ_BT8_AVAILABLE 1 +#define IRQ_BT9_AVAILABLE 1 +#define IRQ_BT10_AVAILABLE 1 +#define IRQ_BT11_AVAILABLE 1 +#define IRQ_BT12_15_AVAILABLE 1 +#define IRQ_MFS8_RX_AVAILABLE 1 +#define IRQ_MFS8_TX_AVAILABLE 1 +#define IRQ_MFS9_RX_AVAILABLE 1 +#define IRQ_MFS9_TX_AVAILABLE 1 +#define IRQ_MFS10_RX_AVAILABLE 1 +#define IRQ_MFS10_TX_AVAILABLE 1 +#define IRQ_MFS11_RX_AVAILABLE 1 +#define IRQ_MFS11_TX_AVAILABLE 1 +#define IRQ_ADC2_AVAILABLE 1 +#define IRQ_DSTC_HW_AVAILABLE 1 +#define IRQ_USB1_F_AVAILABLE 1 +#define IRQ_USB1_H_F_AVAILABLE 1 +#define IRQ_HSSPI_AVAILABLE 1 +#define IRQ_PCRC_I2S0_1_AVAILABLE 1 +#define IRQ_SD_AVAILABLE 1 +#define IRQ_FLASHIF_AVAILABLE 1 +#define IRQ_MFS12_RX_AVAILABLE 1 +#define IRQ_MFS12_TX_AVAILABLE 1 +#define IRQ_MFS13_RX_AVAILABLE 1 +#define IRQ_MFS13_TX_AVAILABLE 1 +#define IRQ_MFS14_RX_AVAILABLE 1 +#define IRQ_MFS14_TX_AVAILABLE 1 +#define IRQ_MFS15_RX_AVAILABLE 1 +#define IRQ_MFS15_TX_AVAILABLE 1 + + +typedef enum IRQn +{ + NMI_IRQn = -14, /* Non Maskable Interrupt NMI */ + HardFault_IRQn = -13, /* HardFault HardFault */ + MemManage_IRQn = -12, /* Memory Management MemManage */ + BusFault_IRQn = -11, /* Bus Fault BusFault */ + UsageFault_IRQn = -10, /* Usage Fault UsageFault */ + SVC_IRQn = -5, /* SV Call SVC */ + DebugMonitor_IRQn = -4, /* Debug Monitor DebugMonitor */ + PendSV_IRQn = -2, /* Pend SV PendSV */ + SysTick_IRQn = -1, /* System Tick SysTick */ + + CSV_IRQn = 0, /* CSV_IRQ */ + SWDT_IRQn = 1, /* SWDT_IRQ */ + LVD_IRQn = 2, /* LVD_IRQ */ + IRQ003SEL_IRQn = 3, /* IRQ003SEL_IRQ */ + IRQ004SEL_IRQn = 4, /* IRQ004SEL_IRQ */ + IRQ005SEL_IRQn = 5, /* IRQ005SEL_IRQ */ + IRQ006SEL_IRQn = 6, /* IRQ006SEL_IRQ */ + IRQ007SEL_IRQn = 7, /* IRQ007SEL_IRQ */ + IRQ008SEL_IRQn = 8, /* IRQ008SEL_IRQ */ + IRQ009SEL_IRQn = 9, /* IRQ009SEL_IRQ */ + IRQ010SEL_IRQn = 10, /* IRQ010SEL_IRQ */ + EXINT0_IRQn = 11, /* EXINT0_IRQ */ + EXINT1_IRQn = 12, /* EXINT1_IRQ */ + EXINT2_IRQn = 13, /* EXINT2_IRQ */ + EXINT3_IRQn = 14, /* EXINT3_IRQ */ + EXINT4_IRQn = 15, /* EXINT4_IRQ */ + EXINT5_IRQn = 16, /* EXINT5_IRQ */ + EXINT6_IRQn = 17, /* EXINT6_IRQ */ + EXINT7_IRQn = 18, /* EXINT7_IRQ */ + QPRC0_IRQn = 19, /* QPRC0_IRQ */ + QPRC1_IRQn = 20, /* QPRC1_IRQ */ + MFT0_WFG_DTIF_IRQn = 21, /* MFT0_WFG_DTIF_IRQ */ + MFT1_WFG_DTIF_IRQn = 22, /* MFT1_WFG_DTIF_IRQ */ + MFT2_WFG_DTIF_IRQn = 23, /* MFT2_WFG_DTIF_IRQ */ + MFT0_FRT_PEAK_IRQn = 24, /* MFT0_FRT_PEAK_IRQ */ + MFT0_FRT_ZERO_IRQn = 25, /* MFT0_FRT_ZERO_IRQ */ + MFT0_ICU_IRQn = 26, /* MFT0_ICU_IRQ */ + MFT0_OCU_IRQn = 27, /* MFT0_OCU_IRQ */ + MFT1_FRT_PEAK_IRQn = 28, /* MFT1_FRT_PEAK_IRQ */ + MFT1_FRT_ZERO_IRQn = 29, /* MFT1_FRT_ZERO_IRQ */ + MFT1_ICU_IRQn = 30, /* MFT1_ICU_IRQ */ + MFT1_OCU_IRQn = 31, /* MFT1_OCU_IRQ */ + MFT2_FRT_PEAK_IRQn = 32, /* MFT2_FRT_PEAK_IRQ */ + MFT2_FRT_ZERO_IRQn = 33, /* MFT2_FRT_ZERO_IRQ */ + MFT2_ICU_IRQn = 34, /* MFT2_ICU_IRQ */ + MFT2_OCU_IRQn = 35, /* MFT2_OCU_IRQ */ + PPG00_02_04_IRQn = 36, /* PPG00_02_04_IRQ */ + PPG08_10_12_IRQn = 37, /* PPG08_10_12_IRQ */ + PPG16_18_20_IRQn = 38, /* PPG16_18_20_IRQ */ + BT0_IRQn = 39, /* BT0_IRQ */ + BT1_IRQn = 40, /* BT1_IRQ */ + BT2_IRQn = 41, /* BT2_IRQ */ + BT3_IRQn = 42, /* BT3_IRQ */ + BT4_IRQn = 43, /* BT4_IRQ */ + BT5_IRQn = 44, /* BT5_IRQ */ + BT6_IRQn = 45, /* BT6_IRQ */ + BT7_IRQn = 46, /* BT7_IRQ */ + DT_IRQn = 47, /* DT_IRQ */ + WC_IRQn = 48, /* WC_IRQ */ + EXTBUS_ERR_IRQn = 49, /* EXTBUS_ERR_IRQ */ + RTC_IRQn = 50, /* RTC_IRQ */ + EXINT8_IRQn = 51, /* EXINT8_IRQ */ + EXINT9_IRQn = 52, /* EXINT9_IRQ */ + EXINT10_IRQn = 53, /* EXINT10_IRQ */ + EXINT11_IRQn = 54, /* EXINT11_IRQ */ + EXINT12_IRQn = 55, /* EXINT12_IRQ */ + EXINT13_IRQn = 56, /* EXINT13_IRQ */ + EXINT14_IRQn = 57, /* EXINT14_IRQ */ + EXINT15_IRQn = 58, /* EXINT15_IRQ */ + TIM_IRQn = 59, /* TIM_IRQ */ + MFS0_RX_IRQn = 60, /* MFS0_RX_IRQ */ + MFS0_TX_IRQn = 61, /* MFS0_TX_IRQ */ + MFS1_RX_IRQn = 62, /* MFS1_RX_IRQ */ + MFS1_TX_IRQn = 63, /* MFS1_TX_IRQ */ + MFS2_RX_IRQn = 64, /* MFS2_RX_IRQ */ + MFS2_TX_IRQn = 65, /* MFS2_TX_IRQ */ + MFS3_RX_IRQn = 66, /* MFS3_RX_IRQ */ + MFS3_TX_IRQn = 67, /* MFS3_TX_IRQ */ + MFS4_RX_IRQn = 68, /* MFS4_RX_IRQ */ + MFS4_TX_IRQn = 69, /* MFS4_TX_IRQ */ + MFS5_RX_IRQn = 70, /* MFS5_RX_IRQ */ + MFS5_TX_IRQn = 71, /* MFS5_TX_IRQ */ + MFS6_RX_IRQn = 72, /* MFS6_RX_IRQ */ + MFS6_TX_IRQn = 73, /* MFS6_TX_IRQ */ + MFS7_RX_IRQn = 74, /* MFS7_RX_IRQ */ + MFS7_TX_IRQn = 75, /* MFS7_TX_IRQ */ + ADC0_IRQn = 76, /* ADC0_IRQ */ + ADC1_IRQn = 77, /* ADC1_IRQ */ + USB0_F_IRQn = 78, /* USB0_F_IRQ */ + USB0_H_F_IRQn = 79, /* USB0_H_F_IRQ */ + CAN0_IRQn = 80, /* CAN0_IRQ */ + CAN1_CANFD0_IRQn = 81, /* CAN1_CANFD0_IRQ */ + DMAC0_IRQn = 83, /* DMAC0_IRQ */ + DMAC1_IRQn = 84, /* DMAC1_IRQ */ + DMAC2_IRQn = 85, /* DMAC2_IRQ */ + DMAC3_IRQn = 86, /* DMAC3_IRQ */ + DMAC4_IRQn = 87, /* DMAC4_IRQ */ + DMAC5_IRQn = 88, /* DMAC5_IRQ */ + DMAC6_IRQn = 89, /* DMAC6_IRQ */ + DMAC7_IRQn = 90, /* DMAC7_IRQ */ + DSTC_IRQn = 91, /* DSTC_IRQ */ + EXINT16_19_IRQn = 92, /* EXINT16_19_IRQ */ + EXINT20_23_IRQn = 93, /* EXINT20_23_IRQ */ + EXINT24_27_IRQn = 94, /* EXINT24_27_IRQ */ + EXINT28_31_IRQn = 95, /* EXINT28_31_IRQ */ + QPRC2_IRQn = 96, /* QPRC2_IRQ */ + QPRC3_IRQn = 97, /* QPRC3_IRQ */ + BT8_IRQn = 98, /* BT8_IRQ */ + BT9_IRQn = 99, /* BT9_IRQ */ + BT10_IRQn = 100, /* BT10_IRQ */ + BT11_IRQn = 101, /* BT11_IRQ */ + BT12_15_IRQn = 102, /* BT12_15_IRQ */ + MFS8_RX_IRQn = 103, /* MFS8_RX_IRQ */ + MFS8_TX_IRQn = 104, /* MFS8_TX_IRQ */ + MFS9_RX_IRQn = 105, /* MFS9_RX_IRQ */ + MFS9_TX_IRQn = 106, /* MFS9_TX_IRQ */ + MFS10_RX_IRQn = 107, /* MFS10_RX_IRQ */ + MFS10_TX_IRQn = 108, /* MFS10_TX_IRQ */ + MFS11_RX_IRQn = 109, /* MFS11_RX_IRQ */ + MFS11_TX_IRQn = 110, /* MFS11_TX_IRQ */ + ADC2_IRQn = 111, /* ADC2_IRQ */ + DSTC_HW_IRQn = 112, /* DSTC_HW_IRQ */ + USB1_F_IRQn = 113, /* USB1_F_IRQ */ + USB1_H_F_IRQn = 114, /* USB1_H_F_IRQ */ + HSSPI_IRQn = 115, /* HSSPI_IRQ */ + PCRC_I2S0_1_IRQn = 117, /* PCRC_I2S0_1_IRQ */ + SD_IRQn = 118, /* SD_IRQ */ + FLASHIF_IRQn = 119, /* FLASHIF_IRQ */ + MFS12_RX_IRQn = 120, /* MFS12_RX_IRQ */ + MFS12_TX_IRQn = 121, /* MFS12_TX_IRQ */ + MFS13_RX_IRQn = 122, /* MFS13_RX_IRQ */ + MFS13_TX_IRQn = 123, /* MFS13_TX_IRQ */ + MFS14_RX_IRQn = 124, /* MFS14_RX_IRQ */ + MFS14_TX_IRQn = 125, /* MFS14_TX_IRQ */ + MFS15_RX_IRQn = 126, /* MFS15_RX_IRQ */ + MFS15_TX_IRQn = 127, /* MFS15_TX_IRQ */ +} IRQn_Type; + +#include "core_cm4.h" +#include + +/******************************************************************************* +* Device Specific Peripheral Registers structures +*******************************************************************************/ +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************* +* ADC_MODULE +*******************************************************************************/ +typedef struct stc_adc_adsr_field +{ + __IO uint8_t SCS :1; + __IO uint8_t PCS :1; + __IO uint8_t PCNS :1; + __IO uint8_t RESERVED0 :3; + __IO uint8_t FDAS :1; + __IO uint8_t ADSTP :1; +} stc_adc_adsr_field_t; + +typedef struct stc_adc_adcr_field +{ + __IO uint8_t OVRIE :1; + __IO uint8_t CMPIE :1; + __IO uint8_t PCIE :1; + __IO uint8_t SCIE :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t CMPIF :1; + __IO uint8_t PCIF :1; + __IO uint8_t SCIF :1; +} stc_adc_adcr_field_t; + +typedef struct stc_adc_sfns_field +{ + union { + struct { + __IO uint8_t SFS :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t SFS0 :1; + __IO uint8_t SFS1 :1; + __IO uint8_t SFS2 :1; + __IO uint8_t SFS3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_adc_sfns_field_t; + +typedef struct stc_adc_sccr_field +{ + __IO uint8_t SSTR :1; + __IO uint8_t SHEN :1; + __IO uint8_t RPT :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t SFCLR :1; + __IO uint8_t SOVR :1; + __IO uint8_t SFUL :1; + __IO uint8_t SEMP :1; +} stc_adc_sccr_field_t; + +typedef struct stc_adc_scfd_fdas1_field +{ + union { + struct { + __IO uint32_t SC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t SD :12; + __IO uint32_t RESERVED5 :4; + }; + struct { + __IO uint32_t SC0 :1; + __IO uint32_t SC1 :1; + __IO uint32_t SC2 :1; + __IO uint32_t SC3 :1; + __IO uint32_t SC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RESERVED4 :6; + __IO uint32_t SD0 :1; + __IO uint32_t SD1 :1; + __IO uint32_t SD2 :1; + __IO uint32_t SD3 :1; + __IO uint32_t SD4 :1; + __IO uint32_t SD5 :1; + __IO uint32_t SD6 :1; + __IO uint32_t SD7 :1; + __IO uint32_t SD8 :1; + __IO uint32_t SD9 :1; + __IO uint32_t SD10 :1; + __IO uint32_t SD11 :1; + __IO uint32_t RESERVED6 :4; + }; + }; +} stc_adc_scfd_fdas1_field_t; + +typedef struct stc_adc_scfd_field +{ + union { + struct { + __IO uint32_t SC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :7; + __IO uint32_t SD :12; + }; + struct { + __IO uint32_t SC0 :1; + __IO uint32_t SC1 :1; + __IO uint32_t SC2 :1; + __IO uint32_t SC3 :1; + __IO uint32_t SC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RESERVED4 :10; + __IO uint32_t SD0 :1; + __IO uint32_t SD1 :1; + __IO uint32_t SD2 :1; + __IO uint32_t SD3 :1; + __IO uint32_t SD4 :1; + __IO uint32_t SD5 :1; + __IO uint32_t SD6 :1; + __IO uint32_t SD7 :1; + __IO uint32_t SD8 :1; + __IO uint32_t SD9 :1; + __IO uint32_t SD10 :1; + __IO uint32_t SD11 :1; + }; + }; +} stc_adc_scfd_field_t; + +typedef struct stc_adc_scis23_field +{ + __IO uint16_t AN16 :1; + __IO uint16_t AN17 :1; + __IO uint16_t AN18 :1; + __IO uint16_t AN19 :1; + __IO uint16_t AN20 :1; + __IO uint16_t AN21 :1; + __IO uint16_t AN22 :1; + __IO uint16_t AN23 :1; + __IO uint16_t AN24 :1; + __IO uint16_t AN25 :1; + __IO uint16_t AN26 :1; + __IO uint16_t AN27 :1; + __IO uint16_t AN28 :1; + __IO uint16_t AN29 :1; + __IO uint16_t AN30 :1; + __IO uint16_t AN31 :1; +} stc_adc_scis23_field_t; + +typedef struct stc_adc_scis01_field +{ + __IO uint16_t AN0 :1; + __IO uint16_t AN1 :1; + __IO uint16_t AN2 :1; + __IO uint16_t AN3 :1; + __IO uint16_t AN4 :1; + __IO uint16_t AN5 :1; + __IO uint16_t AN6 :1; + __IO uint16_t AN7 :1; + __IO uint16_t AN8 :1; + __IO uint16_t AN9 :1; + __IO uint16_t AN10 :1; + __IO uint16_t AN11 :1; + __IO uint16_t AN12 :1; + __IO uint16_t AN13 :1; + __IO uint16_t AN14 :1; + __IO uint16_t AN15 :1; +} stc_adc_scis01_field_t; + +typedef struct stc_adc_pfns_field +{ + union { + struct { + __IO uint8_t PFS :2; + __IO uint8_t RESERVED0 :2; + __IO uint8_t TEST :2; + __IO uint8_t RESERVED2 :2; + }; + struct { + __IO uint8_t PFS0 :1; + __IO uint8_t PFS1 :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t TEST0 :1; + __IO uint8_t TEST1 :1; + __IO uint8_t RESERVED3 :2; + }; + }; +} stc_adc_pfns_field_t; + +typedef struct stc_adc_pccr_field +{ + __IO uint8_t PSTR :1; + __IO uint8_t PHEN :1; + __IO uint8_t PEEN :1; + __IO uint8_t ESCE :1; + __IO uint8_t PFCLR :1; + __IO uint8_t POVR :1; + __IO uint8_t PFUL :1; + __IO uint8_t PEMP :1; +} stc_adc_pccr_field_t; + +typedef struct stc_adc_pcfd_fdas1_field +{ + union { + struct { + __IO uint32_t PC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t PD :12; + __IO uint32_t RESERVED5 :4; + }; + struct { + __IO uint32_t PC0 :1; + __IO uint32_t PC1 :1; + __IO uint32_t PC2 :1; + __IO uint32_t PC3 :1; + __IO uint32_t PC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RS2 :1; + __IO uint32_t RESERVED4 :5; + __IO uint32_t PD0 :1; + __IO uint32_t PD1 :1; + __IO uint32_t PD2 :1; + __IO uint32_t PD3 :1; + __IO uint32_t PD4 :1; + __IO uint32_t PD5 :1; + __IO uint32_t PD6 :1; + __IO uint32_t PD7 :1; + __IO uint32_t PD8 :1; + __IO uint32_t PD9 :1; + __IO uint32_t PD10 :1; + __IO uint32_t PD11 :1; + __IO uint32_t RESERVED6 :4; + }; + }; +} stc_adc_pcfd_fdas1_field_t; + +typedef struct stc_adc_pcfd_field +{ + union { + struct { + __IO uint32_t PC :5; + __IO uint32_t RESERVED0 :3; + __IO uint32_t RS :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t INVL :1; + __IO uint32_t RESERVED3 :7; + __IO uint32_t PD :12; + }; + struct { + __IO uint32_t PC0 :1; + __IO uint32_t PC1 :1; + __IO uint32_t PC2 :1; + __IO uint32_t PC3 :1; + __IO uint32_t PC4 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t RS0 :1; + __IO uint32_t RS1 :1; + __IO uint32_t RS2 :1; + __IO uint32_t RESERVED4 :9; + __IO uint32_t PD0 :1; + __IO uint32_t PD1 :1; + __IO uint32_t PD2 :1; + __IO uint32_t PD3 :1; + __IO uint32_t PD4 :1; + __IO uint32_t PD5 :1; + __IO uint32_t PD6 :1; + __IO uint32_t PD7 :1; + __IO uint32_t PD8 :1; + __IO uint32_t PD9 :1; + __IO uint32_t PD10 :1; + __IO uint32_t PD11 :1; + }; + }; +} stc_adc_pcfd_field_t; + +typedef struct stc_adc_pcis_field +{ + union { + struct { + __IO uint8_t P1A :3; + __IO uint8_t P2A :5; + }; + struct { + __IO uint8_t P1A0 :1; + __IO uint8_t P1A1 :1; + __IO uint8_t P1A2 :1; + __IO uint8_t P2A0 :1; + __IO uint8_t P2A1 :1; + __IO uint8_t P2A2 :1; + __IO uint8_t P2A3 :1; + __IO uint8_t P2A4 :1; + }; + }; +} stc_adc_pcis_field_t; + +typedef struct stc_adc_cmpcr_field +{ + union { + struct { + __IO uint8_t CCH :5; + __IO uint8_t CMD0 :1; + __IO uint8_t CMD1 :1; + __IO uint8_t CMPEN :1; + }; + struct { + __IO uint8_t CCH0 :1; + __IO uint8_t CCH1 :1; + __IO uint8_t CCH2 :1; + __IO uint8_t CCH3 :1; + __IO uint8_t CCH4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_adc_cmpcr_field_t; + +typedef struct stc_adc_cmpd_field +{ + union { + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CMAD :10; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t CMAD0 :1; + __IO uint16_t CMAD1 :1; + __IO uint16_t CMAD2 :1; + __IO uint16_t CMAD3 :1; + __IO uint16_t CMAD4 :1; + __IO uint16_t CMAD5 :1; + __IO uint16_t CMAD6 :1; + __IO uint16_t CMAD7 :1; + __IO uint16_t CMAD8 :1; + __IO uint16_t CMAD9 :1; + }; + }; +} stc_adc_cmpd_field_t; + +typedef struct stc_adc_adss23_field +{ + __IO uint16_t TS16 :1; + __IO uint16_t TS17 :1; + __IO uint16_t TS18 :1; + __IO uint16_t TS19 :1; + __IO uint16_t TS20 :1; + __IO uint16_t TS21 :1; + __IO uint16_t TS22 :1; + __IO uint16_t TS23 :1; + __IO uint16_t TS24 :1; + __IO uint16_t TS25 :1; + __IO uint16_t TS26 :1; + __IO uint16_t TS27 :1; + __IO uint16_t TS28 :1; + __IO uint16_t TS29 :1; + __IO uint16_t TS30 :1; + __IO uint16_t TS31 :1; +} stc_adc_adss23_field_t; + +typedef struct stc_adc_adss01_field +{ + __IO uint16_t TS0 :1; + __IO uint16_t TS1 :1; + __IO uint16_t TS2 :1; + __IO uint16_t TS3 :1; + __IO uint16_t TS4 :1; + __IO uint16_t TS5 :1; + __IO uint16_t TS6 :1; + __IO uint16_t TS7 :1; + __IO uint16_t TS8 :1; + __IO uint16_t TS9 :1; + __IO uint16_t TS10 :1; + __IO uint16_t TS11 :1; + __IO uint16_t TS12 :1; + __IO uint16_t TS13 :1; + __IO uint16_t TS14 :1; + __IO uint16_t TS15 :1; +} stc_adc_adss01_field_t; + +typedef struct stc_adc_adst01_field +{ + union { + struct { + __IO uint16_t ST1 :5; + __IO uint16_t STX1 :3; + __IO uint16_t ST0 :5; + __IO uint16_t STX0 :3; + }; + struct { + __IO uint16_t ST10 :1; + __IO uint16_t ST11 :1; + __IO uint16_t ST12 :1; + __IO uint16_t ST13 :1; + __IO uint16_t ST14 :1; + __IO uint16_t STX10 :1; + __IO uint16_t STX11 :1; + __IO uint16_t STX12 :1; + __IO uint16_t ST00 :1; + __IO uint16_t ST01 :1; + __IO uint16_t ST02 :1; + __IO uint16_t ST03 :1; + __IO uint16_t ST04 :1; + __IO uint16_t STX00 :1; + __IO uint16_t STX01 :1; + __IO uint16_t STX02 :1; + }; + }; +} stc_adc_adst01_field_t; + +typedef struct stc_adc_adct_field +{ + union { + struct { + __IO uint8_t CT :8; + }; + struct { + __IO uint8_t CT0 :1; + __IO uint8_t CT1 :1; + __IO uint8_t CT2 :1; + __IO uint8_t CT3 :1; + __IO uint8_t CT4 :1; + __IO uint8_t CT5 :1; + __IO uint8_t CT6 :1; + __IO uint8_t CT7 :1; + }; + }; +} stc_adc_adct_field_t; + +typedef struct stc_adc_prtsl_field +{ + union { + struct { + __IO uint8_t PRTSL :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t PRTSL0 :1; + __IO uint8_t PRTSL1 :1; + __IO uint8_t PRTSL2 :1; + __IO uint8_t PRTSL3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_adc_prtsl_field_t; + +typedef struct stc_adc_sctsl_field +{ + union { + struct { + __IO uint8_t SCTSL :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t SCTSL0 :1; + __IO uint8_t SCTSL1 :1; + __IO uint8_t SCTSL2 :1; + __IO uint8_t SCTSL3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_adc_sctsl_field_t; + +typedef struct stc_adc_adcen_field +{ + union { + struct { + __IO uint16_t ENBL :1; + __IO uint16_t READY :1; + __IO uint16_t RESERVED0 :6; + __IO uint16_t ENBLTIME :8; + }; + struct { + __IO uint16_t RESERVED1 :8; + __IO uint16_t ENBLTIME0 :1; + __IO uint16_t ENBLTIME1 :1; + __IO uint16_t ENBLTIME2 :1; + __IO uint16_t ENBLTIME3 :1; + __IO uint16_t ENBLTIME4 :1; + __IO uint16_t ENBLTIME5 :1; + __IO uint16_t ENBLTIME6 :1; + __IO uint16_t ENBLTIME7 :1; + }; + }; +} stc_adc_adcen_field_t; + +typedef struct stc_adc_calsr_field +{ + union { + struct { + __IO uint32_t OFST :8; + __IO uint32_t CLBEN :1; + __IO uint32_t RESERVED0 :23; + }; + struct { + __IO uint32_t OFST0 :1; + __IO uint32_t OFST1 :1; + __IO uint32_t OFST2 :1; + __IO uint32_t OFST3 :1; + __IO uint32_t OFST4 :1; + __IO uint32_t OFST5 :1; + __IO uint32_t OFST6 :1; + __IO uint32_t OFST7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_adc_calsr_field_t; + +typedef struct stc_adc_wcmrcot_field +{ + __IO uint8_t RCOOF :1; + __IO uint8_t RESERVED0 :7; +} stc_adc_wcmrcot_field_t; + +typedef struct stc_adc_wcmrcif_field +{ + __IO uint8_t RCINT :1; + __IO uint8_t RESERVED0 :7; +} stc_adc_wcmrcif_field_t; + +typedef struct stc_adc_wcmpcr_field +{ + union { + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t RCOE :1; + __IO uint8_t RCOIE :1; + __IO uint8_t RCOIRS :1; + __IO uint8_t RCOCD :3; + }; + struct { + __IO uint8_t RESERVED1 :5; + __IO uint8_t RCOCD0 :1; + __IO uint8_t RCOCD1 :1; + __IO uint8_t RCOCD2 :1; + }; + }; +} stc_adc_wcmpcr_field_t; + +typedef struct stc_adc_wcmpsr_field +{ + union { + struct { + __IO uint8_t WCCH :5; + __IO uint8_t WCMD :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t WCCH0 :1; + __IO uint8_t WCCH1 :1; + __IO uint8_t WCCH2 :1; + __IO uint8_t WCCH3 :1; + __IO uint8_t WCCH4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_adc_wcmpsr_field_t; + +typedef struct stc_adc_wcmpdl_field +{ + union { + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CMLD :10; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t CMLD0 :1; + __IO uint16_t CMLD1 :1; + __IO uint16_t CMLD2 :1; + __IO uint16_t CMLD3 :1; + __IO uint16_t CMLD4 :1; + __IO uint16_t CMLD5 :1; + __IO uint16_t CMLD6 :1; + __IO uint16_t CMLD7 :1; + __IO uint16_t CMLD8 :1; + __IO uint16_t CMLD9 :1; + }; + }; +} stc_adc_wcmpdl_field_t; + +typedef struct stc_adc_wcmpdh_field +{ + union { + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CMHD :10; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t CMHD0 :1; + __IO uint16_t CMHD1 :1; + __IO uint16_t CMHD2 :1; + __IO uint16_t CMHD3 :1; + __IO uint16_t CMHD4 :1; + __IO uint16_t CMHD5 :1; + __IO uint16_t CMHD6 :1; + __IO uint16_t CMHD7 :1; + __IO uint16_t CMHD8 :1; + __IO uint16_t CMHD9 :1; + }; + }; +} stc_adc_wcmpdh_field_t; + +/******************************************************************************* +* BT_MODULE +*******************************************************************************/ +typedef struct stc_bt_tmcr_field +{ + union { + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t RESERVED1 :1; + __IO uint16_t EGS :2; + __IO uint16_t PMSK :1; + __IO uint16_t RTGEN :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t RESERVED0 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED2 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED3 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED5 :1; + }; + }; + union { + struct { + __IO uint16_t RESERVED6 :7; + __IO uint16_t T32 :1; + __IO uint16_t RESERVED7 :8; + }; + struct { + __IO uint16_t RESERVED8 :16; + }; + }; + }; +} stc_bt_tmcr_field_t; + +typedef struct stc_bt_stc_field +{ + union { + struct { + __IO uint8_t UDIR :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED1 :1; + __IO uint8_t UDIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t OVIR :1; + __IO uint8_t RESERVED5 :1; + __IO uint8_t EDIR :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t OVIE :1; + __IO uint8_t RESERVED7 :1; + __IO uint8_t EDIE :1; + __IO uint8_t ERR :1; + }; + struct { + __IO uint8_t RESERVED9 :1; + __IO uint8_t DTIR :1; + __IO uint8_t RESERVED10 :3; + __IO uint8_t DTIE :1; + __IO uint8_t RESERVED11 :2; + }; + }; +} stc_bt_stc_field_t; + +typedef struct stc_bt_tmcr2_field +{ + union { + struct { + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED0 :7; + }; + struct { + __IO uint8_t RESERVED6 :7; + __IO uint8_t GATE :1; + }; + }; +} stc_bt_tmcr2_field_t; + +typedef struct stc_bt_ppg_tmcr_field +{ + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t RESERVED1 :1; + __IO uint16_t EGS :2; + __IO uint16_t PMSK :1; + __IO uint16_t RTGEN :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t RESERVED0 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED2 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED3 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_bt_ppg_tmcr_field_t; + +typedef struct stc_bt_pwc_tmcr_field +{ + union { + struct { + __IO uint16_t RESERVED6 :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t RESERVED7 :1; + __IO uint16_t FMD :3; + __IO uint16_t T32 :1; + __IO uint16_t EGS :3; + __IO uint16_t RESERVED10 :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED12 :1; + }; + struct { + __IO uint16_t RESERVED8 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED9 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t EGS2 :1; + __IO uint16_t RESERVED11 :1; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED13 :1; + }; + }; +} stc_bt_pwc_tmcr_field_t; + +typedef struct stc_bt_pwm_tmcr_field +{ + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t RESERVED15 :1; + __IO uint16_t EGS :2; + __IO uint16_t PMSK :1; + __IO uint16_t RTGEN :1; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED18 :1; + }; + struct { + __IO uint16_t RESERVED14 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED16 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED17 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED19 :1; + }; + }; +} stc_bt_pwm_tmcr_field_t; + +typedef struct stc_bt_rt_tmcr_field +{ + union { + struct { + __IO uint16_t STRG :1; + __IO uint16_t CTEN :1; + __IO uint16_t MDSE :1; + __IO uint16_t OSEL :1; + __IO uint16_t FMD :3; + __IO uint16_t T32 :1; + __IO uint16_t EGS :2; + __IO uint16_t RESERVED22 :2; + __IO uint16_t CKS :3; + __IO uint16_t RESERVED24 :1; + }; + struct { + __IO uint16_t RESERVED20 :4; + __IO uint16_t FMD0 :1; + __IO uint16_t FMD1 :1; + __IO uint16_t FMD2 :1; + __IO uint16_t RESERVED21 :1; + __IO uint16_t EGS0 :1; + __IO uint16_t EGS1 :1; + __IO uint16_t RESERVED23 :2; + __IO uint16_t CKS0 :1; + __IO uint16_t CKS1 :1; + __IO uint16_t CKS2 :1; + __IO uint16_t RESERVED25 :1; + }; + }; +} stc_bt_rt_tmcr_field_t; + +typedef struct stc_bt_ppg_stc_field +{ + __IO uint8_t UDIR :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED1 :1; + __IO uint8_t UDIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED3 :1; +} stc_bt_ppg_stc_field_t; + +typedef struct stc_bt_pwc_stc_field +{ + __IO uint8_t OVIR :1; + __IO uint8_t RESERVED5 :1; + __IO uint8_t EDIR :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t OVIE :1; + __IO uint8_t RESERVED7 :1; + __IO uint8_t EDIE :1; + __IO uint8_t ERR :1; +} stc_bt_pwc_stc_field_t; + +typedef struct stc_bt_pwm_stc_field +{ + __IO uint8_t UDIR :1; + __IO uint8_t DTIR :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED9 :1; + __IO uint8_t UDIE :1; + __IO uint8_t DTIE :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED10 :1; +} stc_bt_pwm_stc_field_t; + +typedef struct stc_bt_rt_stc_field +{ + __IO uint8_t UDIR :1; + __IO uint8_t RESERVED12 :1; + __IO uint8_t TGIR :1; + __IO uint8_t RESERVED13 :1; + __IO uint8_t UDIE :1; + __IO uint8_t RESERVED14 :1; + __IO uint8_t TGIE :1; + __IO uint8_t RESERVED15 :1; +} stc_bt_rt_stc_field_t; + +typedef struct stc_bt_ppg_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED0 :7; +} stc_bt_ppg_tmcr2_field_t; + +typedef struct stc_bt_pwc_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED2 :7; +} stc_bt_pwc_tmcr2_field_t; + +typedef struct stc_bt_pwm_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED4 :7; +} stc_bt_pwm_tmcr2_field_t; + +typedef struct stc_bt_rt_tmcr2_field +{ + __IO uint8_t CKS3 :1; + __IO uint8_t RESERVED6 :6; + __IO uint8_t GATE :1; +} stc_bt_rt_tmcr2_field_t; + +/******************************************************************************* +* BTIOSEL03_MODULE +*******************************************************************************/ +typedef struct stc_btiosel03_btsel0123_field +{ + union { + struct { + __IO uint8_t SEL01 :4; + __IO uint8_t SEL23 :4; + }; + struct { + __IO uint8_t SEL010 :1; + __IO uint8_t SEL011 :1; + __IO uint8_t SEL012 :1; + __IO uint8_t SEL013 :1; + __IO uint8_t SEL230 :1; + __IO uint8_t SEL231 :1; + __IO uint8_t SEL232 :1; + __IO uint8_t SEL233 :1; + }; + }; +} stc_btiosel03_btsel0123_field_t; + +/******************************************************************************* +* BTIOSEL47_MODULE +*******************************************************************************/ +typedef struct stc_btiosel47_btsel4567_field +{ + union { + struct { + __IO uint8_t SEL45 :4; + __IO uint8_t SEL67 :4; + }; + struct { + __IO uint8_t SEL450 :1; + __IO uint8_t SEL451 :1; + __IO uint8_t SEL452 :1; + __IO uint8_t SEL453 :1; + __IO uint8_t SEL670 :1; + __IO uint8_t SEL671 :1; + __IO uint8_t SEL672 :1; + __IO uint8_t SEL673 :1; + }; + }; +} stc_btiosel47_btsel4567_field_t; + +/******************************************************************************* +* BTIOSEL8B_MODULE +*******************************************************************************/ +typedef struct stc_btiosel8b_btsel89ab_field +{ + union { + struct { + __IO uint8_t SEL89 :4; + __IO uint8_t SELAB :4; + }; + struct { + __IO uint8_t SEL890 :1; + __IO uint8_t SEL891 :1; + __IO uint8_t SEL892 :1; + __IO uint8_t SEL893 :1; + __IO uint8_t SELAB0 :1; + __IO uint8_t SELAB1 :1; + __IO uint8_t SELAB2 :1; + __IO uint8_t SELAB3 :1; + }; + }; +} stc_btiosel8b_btsel89ab_field_t; + +/******************************************************************************* +* BTIOSELCF_MODULE +*******************************************************************************/ +typedef struct stc_btioselcf_btselcdef_field +{ + union { + struct { + __IO uint8_t SELCD :4; + __IO uint8_t SELEF :4; + }; + struct { + __IO uint8_t SELCD0 :1; + __IO uint8_t SELCD1 :1; + __IO uint8_t SELCD2 :1; + __IO uint8_t SELCD3 :1; + __IO uint8_t SELEF0 :1; + __IO uint8_t SELEF1 :1; + __IO uint8_t SELEF2 :1; + __IO uint8_t SELEF3 :1; + }; + }; +} stc_btioselcf_btselcdef_field_t; + +/******************************************************************************* +* CAN_MODULE +*******************************************************************************/ +typedef struct stc_can_ctrlr_field +{ + __IO uint16_t INIT :1; + __IO uint16_t IE :1; + __IO uint16_t SIE :1; + __IO uint16_t EIE :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t DAR :1; + __IO uint16_t CCE :1; + __IO uint16_t TEST :1; + __IO uint16_t RESERVED1 :8; +} stc_can_ctrlr_field_t; + +typedef struct stc_can_statr_field +{ + union { + struct { + __IO uint16_t LEC :3; + __IO uint16_t TXOK :1; + __IO uint16_t RXOK :1; + __IO uint16_t EPASS :1; + __IO uint16_t EWARN :1; + __IO uint16_t BOFF :1; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t LEC0 :1; + __IO uint16_t LEC1 :1; + __IO uint16_t LEC2 :1; + __IO uint16_t RESERVED1 :13; + }; + }; +} stc_can_statr_field_t; + +typedef struct stc_can_errcnt_field +{ + union { + struct { + __IO uint16_t TEC :8; + __IO uint16_t REC :7; + __IO uint16_t RP :1; + }; + struct { + __IO uint16_t TEC0 :1; + __IO uint16_t TEC1 :1; + __IO uint16_t TEC2 :1; + __IO uint16_t TEC3 :1; + __IO uint16_t TEC4 :1; + __IO uint16_t TEC5 :1; + __IO uint16_t TEC6 :1; + __IO uint16_t TEC7 :1; + __IO uint16_t REC0 :1; + __IO uint16_t REC1 :1; + __IO uint16_t REC2 :1; + __IO uint16_t REC3 :1; + __IO uint16_t REC4 :1; + __IO uint16_t REC5 :1; + __IO uint16_t REC6 :1; + __IO uint16_t RESERVED0 :1; + }; + }; +} stc_can_errcnt_field_t; + +typedef struct stc_can_btr_field +{ + union { + struct { + __IO uint16_t BRP :6; + __IO uint16_t SJW :2; + __IO uint16_t TSEG1 :4; + __IO uint16_t TSEG2 :3; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t BRP0 :1; + __IO uint16_t BRP1 :1; + __IO uint16_t BRP2 :1; + __IO uint16_t BRP3 :1; + __IO uint16_t BRP4 :1; + __IO uint16_t BRP5 :1; + __IO uint16_t SJW0 :1; + __IO uint16_t SJW1 :1; + __IO uint16_t TSEG10 :1; + __IO uint16_t TSEG11 :1; + __IO uint16_t TSEG12 :1; + __IO uint16_t TSEG13 :1; + __IO uint16_t TSEG20 :1; + __IO uint16_t TSEG21 :1; + __IO uint16_t TSEG22 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_can_btr_field_t; + +typedef struct stc_can_intr_field +{ + union { + struct { + __IO uint16_t INTID :16; + }; + struct { + __IO uint16_t INTID0 :1; + __IO uint16_t INTID1 :1; + __IO uint16_t INTID2 :1; + __IO uint16_t INTID3 :1; + __IO uint16_t INTID4 :1; + __IO uint16_t INTID5 :1; + __IO uint16_t INTID6 :1; + __IO uint16_t INTID7 :1; + __IO uint16_t INTID8 :1; + __IO uint16_t INTID9 :1; + __IO uint16_t INTID10 :1; + __IO uint16_t INTID11 :1; + __IO uint16_t INTID12 :1; + __IO uint16_t INTID13 :1; + __IO uint16_t INTID14 :1; + __IO uint16_t INTID15 :1; + }; + }; +} stc_can_intr_field_t; + +typedef struct stc_can_testr_field +{ + union { + struct { + __IO uint16_t RESERVED0 :2; + __IO uint16_t BASIC :1; + __IO uint16_t SILENT :1; + __IO uint16_t LBACK :1; + __IO uint16_t TX :2; + __IO uint16_t RX :1; + __IO uint16_t RESERVED2 :8; + }; + struct { + __IO uint16_t RESERVED1 :5; + __IO uint16_t TX0 :1; + __IO uint16_t TX1 :1; + __IO uint16_t RESERVED3 :9; + }; + }; +} stc_can_testr_field_t; + +typedef struct stc_can_brper_field +{ + union { + struct { + __IO uint16_t BRPE :4; + __IO uint16_t RESERVED0 :12; + }; + struct { + __IO uint16_t BRPE0 :1; + __IO uint16_t BRPE1 :1; + __IO uint16_t BRPE2 :1; + __IO uint16_t BRPE3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_can_brper_field_t; + +typedef struct stc_can_if1creq_field +{ + union { + struct { + __IO uint16_t MESSAGENUMBER :8; + __IO uint16_t RESERVED0 :7; + __IO uint16_t BUSY :1; + }; + struct { + __IO uint16_t MESSAGENUMBER0 :1; + __IO uint16_t MESSAGENUMBER1 :1; + __IO uint16_t MESSAGENUMBER2 :1; + __IO uint16_t MESSAGENUMBER3 :1; + __IO uint16_t MESSAGENUMBER4 :1; + __IO uint16_t MESSAGENUMBER5 :1; + __IO uint16_t MESSAGENUMBER6 :1; + __IO uint16_t MESSAGENUMBER7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_can_if1creq_field_t; + +typedef struct stc_can_if1cmsk_field +{ + __IO uint16_t DATAB :1; + __IO uint16_t DATAA :1; + __IO uint16_t NEWDAT :1; + __IO uint16_t CIP :1; + __IO uint16_t CONTROL :1; + __IO uint16_t ARB :1; + __IO uint16_t MASK :1; + __IO uint16_t WR_RD :1; + __IO uint16_t RESERVED0 :8; +} stc_can_if1cmsk_field_t; + +typedef struct stc_can_if1msk_field +{ + union { + struct { + __IO uint32_t MSK :29; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MDIR :1; + __IO uint32_t MXTD :1; + }; + struct { + __IO uint32_t MSK0 :1; + __IO uint32_t MSK1 :1; + __IO uint32_t MSK2 :1; + __IO uint32_t MSK3 :1; + __IO uint32_t MSK4 :1; + __IO uint32_t MSK5 :1; + __IO uint32_t MSK6 :1; + __IO uint32_t MSK7 :1; + __IO uint32_t MSK8 :1; + __IO uint32_t MSK9 :1; + __IO uint32_t MSK10 :1; + __IO uint32_t MSK11 :1; + __IO uint32_t MSK12 :1; + __IO uint32_t MSK13 :1; + __IO uint32_t MSK14 :1; + __IO uint32_t MSK15 :1; + __IO uint32_t MSK16 :1; + __IO uint32_t MSK17 :1; + __IO uint32_t MSK18 :1; + __IO uint32_t MSK19 :1; + __IO uint32_t MSK20 :1; + __IO uint32_t MSK21 :1; + __IO uint32_t MSK22 :1; + __IO uint32_t MSK23 :1; + __IO uint32_t MSK24 :1; + __IO uint32_t MSK25 :1; + __IO uint32_t MSK26 :1; + __IO uint32_t MSK27 :1; + __IO uint32_t MSK28 :1; + __IO uint32_t RESERVED1 :3; + }; + }; +} stc_can_if1msk_field_t; + +typedef struct stc_can_if1arb_field +{ + union { + struct { + __IO uint32_t ID :29; + __IO uint32_t DIR :1; + __IO uint32_t XTD :1; + __IO uint32_t MSGVAL :1; + }; + struct { + __IO uint32_t ID0 :1; + __IO uint32_t ID1 :1; + __IO uint32_t ID2 :1; + __IO uint32_t ID3 :1; + __IO uint32_t ID4 :1; + __IO uint32_t ID5 :1; + __IO uint32_t ID6 :1; + __IO uint32_t ID7 :1; + __IO uint32_t ID8 :1; + __IO uint32_t ID9 :1; + __IO uint32_t ID10 :1; + __IO uint32_t ID11 :1; + __IO uint32_t ID12 :1; + __IO uint32_t ID13 :1; + __IO uint32_t ID14 :1; + __IO uint32_t ID15 :1; + __IO uint32_t ID16 :1; + __IO uint32_t ID17 :1; + __IO uint32_t ID18 :1; + __IO uint32_t ID19 :1; + __IO uint32_t ID20 :1; + __IO uint32_t ID21 :1; + __IO uint32_t ID22 :1; + __IO uint32_t ID23 :1; + __IO uint32_t ID24 :1; + __IO uint32_t ID25 :1; + __IO uint32_t ID26 :1; + __IO uint32_t ID27 :1; + __IO uint32_t ID28 :1; + __IO uint32_t RESERVED0 :3; + }; + }; +} stc_can_if1arb_field_t; + +typedef struct stc_can_if1mctr_field +{ + union { + struct { + __IO uint16_t DLC :4; + __IO uint16_t RESERVED0 :3; + __IO uint16_t EOB :1; + __IO uint16_t TXRQST :1; + __IO uint16_t RMTEN :1; + __IO uint16_t RXIE :1; + __IO uint16_t TXIE :1; + __IO uint16_t UMASK :1; + __IO uint16_t INTPND :1; + __IO uint16_t MSGLST :1; + __IO uint16_t NEWDAT :1; + }; + struct { + __IO uint16_t DLC0 :1; + __IO uint16_t DLC1 :1; + __IO uint16_t DLC2 :1; + __IO uint16_t DLC3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_can_if1mctr_field_t; + +typedef struct stc_can_if1dta_l_field +{ + union { + struct { + __IO uint32_t DATA0 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA3 :8; + }; + struct { + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + }; + }; +} stc_can_if1dta_l_field_t; + +typedef struct stc_can_if1dtb_l_field +{ + union { + struct { + __IO uint32_t DATA4 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA7 :8; + }; + struct { + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + }; + }; +} stc_can_if1dtb_l_field_t; + +typedef struct stc_can_if1dta_b_field +{ + union { + struct { + __IO uint32_t DATA3 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA0 :8; + }; + struct { + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + }; + }; +} stc_can_if1dta_b_field_t; + +typedef struct stc_can_if1dtb_b_field +{ + union { + struct { + __IO uint32_t DATA7 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA4 :8; + }; + struct { + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + }; + }; +} stc_can_if1dtb_b_field_t; + +typedef struct stc_can_if2creq_field +{ + union { + struct { + __IO uint16_t MESSAGENUMBER :8; + __IO uint16_t RESERVED0 :7; + __IO uint16_t BUSY :1; + }; + struct { + __IO uint16_t MESSAGENUMBER0 :1; + __IO uint16_t MESSAGENUMBER1 :1; + __IO uint16_t MESSAGENUMBER2 :1; + __IO uint16_t MESSAGENUMBER3 :1; + __IO uint16_t MESSAGENUMBER4 :1; + __IO uint16_t MESSAGENUMBER5 :1; + __IO uint16_t MESSAGENUMBER6 :1; + __IO uint16_t MESSAGENUMBER7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_can_if2creq_field_t; + +typedef struct stc_can_if2cmsk_field +{ + __IO uint16_t DATAB :1; + __IO uint16_t DATAA :1; + __IO uint16_t NEWDAT :1; + __IO uint16_t CIP :1; + __IO uint16_t CONTROL :1; + __IO uint16_t ARB :1; + __IO uint16_t MASK :1; + __IO uint16_t WR_RD :1; + __IO uint16_t RESERVED0 :8; +} stc_can_if2cmsk_field_t; + +typedef struct stc_can_if2msk_field +{ + union { + struct { + __IO uint32_t MSK :29; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MDIR :1; + __IO uint32_t MXTD :1; + }; + struct { + __IO uint32_t MSK0 :1; + __IO uint32_t MSK1 :1; + __IO uint32_t MSK2 :1; + __IO uint32_t MSK3 :1; + __IO uint32_t MSK4 :1; + __IO uint32_t MSK5 :1; + __IO uint32_t MSK6 :1; + __IO uint32_t MSK7 :1; + __IO uint32_t MSK8 :1; + __IO uint32_t MSK9 :1; + __IO uint32_t MSK10 :1; + __IO uint32_t MSK11 :1; + __IO uint32_t MSK12 :1; + __IO uint32_t MSK13 :1; + __IO uint32_t MSK14 :1; + __IO uint32_t MSK15 :1; + __IO uint32_t MSK16 :1; + __IO uint32_t MSK17 :1; + __IO uint32_t MSK18 :1; + __IO uint32_t MSK19 :1; + __IO uint32_t MSK20 :1; + __IO uint32_t MSK21 :1; + __IO uint32_t MSK22 :1; + __IO uint32_t MSK23 :1; + __IO uint32_t MSK24 :1; + __IO uint32_t MSK25 :1; + __IO uint32_t MSK26 :1; + __IO uint32_t MSK27 :1; + __IO uint32_t MSK28 :1; + __IO uint32_t RESERVED1 :3; + }; + }; +} stc_can_if2msk_field_t; + +typedef struct stc_can_if2arb_field +{ + union { + struct { + __IO uint32_t ID :29; + __IO uint32_t DIR :1; + __IO uint32_t XTD :1; + __IO uint32_t MSGVAL :1; + }; + struct { + __IO uint32_t ID0 :1; + __IO uint32_t ID1 :1; + __IO uint32_t ID2 :1; + __IO uint32_t ID3 :1; + __IO uint32_t ID4 :1; + __IO uint32_t ID5 :1; + __IO uint32_t ID6 :1; + __IO uint32_t ID7 :1; + __IO uint32_t ID8 :1; + __IO uint32_t ID9 :1; + __IO uint32_t ID10 :1; + __IO uint32_t ID11 :1; + __IO uint32_t ID12 :1; + __IO uint32_t ID13 :1; + __IO uint32_t ID14 :1; + __IO uint32_t ID15 :1; + __IO uint32_t ID16 :1; + __IO uint32_t ID17 :1; + __IO uint32_t ID18 :1; + __IO uint32_t ID19 :1; + __IO uint32_t ID20 :1; + __IO uint32_t ID21 :1; + __IO uint32_t ID22 :1; + __IO uint32_t ID23 :1; + __IO uint32_t ID24 :1; + __IO uint32_t ID25 :1; + __IO uint32_t ID26 :1; + __IO uint32_t ID27 :1; + __IO uint32_t ID28 :1; + __IO uint32_t RESERVED0 :3; + }; + }; +} stc_can_if2arb_field_t; + +typedef struct stc_can_if2mctr_field +{ + union { + struct { + __IO uint16_t DLC :4; + __IO uint16_t RESERVED0 :3; + __IO uint16_t EOB :1; + __IO uint16_t TXRQST :1; + __IO uint16_t RMTEN :1; + __IO uint16_t RXIE :1; + __IO uint16_t TXIE :1; + __IO uint16_t UMASK :1; + __IO uint16_t INTPND :1; + __IO uint16_t MSGLST :1; + __IO uint16_t NEWDAT :1; + }; + struct { + __IO uint16_t DLC0 :1; + __IO uint16_t DLC1 :1; + __IO uint16_t DLC2 :1; + __IO uint16_t DLC3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_can_if2mctr_field_t; + +typedef struct stc_can_if2dta_l_field +{ + union { + struct { + __IO uint32_t DATA0 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA3 :8; + }; + struct { + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + }; + }; +} stc_can_if2dta_l_field_t; + +typedef struct stc_can_if2dtb_l_field +{ + union { + struct { + __IO uint32_t DATA4 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA7 :8; + }; + struct { + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + }; + }; +} stc_can_if2dtb_l_field_t; + +typedef struct stc_can_if2dta_b_field +{ + union { + struct { + __IO uint32_t DATA3 :8; + __IO uint32_t DATA2 :8; + __IO uint32_t DATA1 :8; + __IO uint32_t DATA0 :8; + }; + struct { + __IO uint32_t DATA30 :1; + __IO uint32_t DATA31 :1; + __IO uint32_t DATA32 :1; + __IO uint32_t DATA33 :1; + __IO uint32_t DATA34 :1; + __IO uint32_t DATA35 :1; + __IO uint32_t DATA36 :1; + __IO uint32_t DATA37 :1; + __IO uint32_t DATA20 :1; + __IO uint32_t DATA21 :1; + __IO uint32_t DATA22 :1; + __IO uint32_t DATA23 :1; + __IO uint32_t DATA24 :1; + __IO uint32_t DATA25 :1; + __IO uint32_t DATA26 :1; + __IO uint32_t DATA27 :1; + __IO uint32_t DATA10 :1; + __IO uint32_t DATA11 :1; + __IO uint32_t DATA12 :1; + __IO uint32_t DATA13 :1; + __IO uint32_t DATA14 :1; + __IO uint32_t DATA15 :1; + __IO uint32_t DATA16 :1; + __IO uint32_t DATA17 :1; + __IO uint32_t DATA00 :1; + __IO uint32_t DATA01 :1; + __IO uint32_t DATA02 :1; + __IO uint32_t DATA03 :1; + __IO uint32_t DATA04 :1; + __IO uint32_t DATA05 :1; + __IO uint32_t DATA06 :1; + __IO uint32_t DATA07 :1; + }; + }; +} stc_can_if2dta_b_field_t; + +typedef struct stc_can_if2dtb_b_field +{ + union { + struct { + __IO uint32_t DATA7 :8; + __IO uint32_t DATA6 :8; + __IO uint32_t DATA5 :8; + __IO uint32_t DATA4 :8; + }; + struct { + __IO uint32_t DATA70 :1; + __IO uint32_t DATA71 :1; + __IO uint32_t DATA72 :1; + __IO uint32_t DATA73 :1; + __IO uint32_t DATA74 :1; + __IO uint32_t DATA75 :1; + __IO uint32_t DATA76 :1; + __IO uint32_t DATA77 :1; + __IO uint32_t DATA60 :1; + __IO uint32_t DATA61 :1; + __IO uint32_t DATA62 :1; + __IO uint32_t DATA63 :1; + __IO uint32_t DATA64 :1; + __IO uint32_t DATA65 :1; + __IO uint32_t DATA66 :1; + __IO uint32_t DATA67 :1; + __IO uint32_t DATA50 :1; + __IO uint32_t DATA51 :1; + __IO uint32_t DATA52 :1; + __IO uint32_t DATA53 :1; + __IO uint32_t DATA54 :1; + __IO uint32_t DATA55 :1; + __IO uint32_t DATA56 :1; + __IO uint32_t DATA57 :1; + __IO uint32_t DATA40 :1; + __IO uint32_t DATA41 :1; + __IO uint32_t DATA42 :1; + __IO uint32_t DATA43 :1; + __IO uint32_t DATA44 :1; + __IO uint32_t DATA45 :1; + __IO uint32_t DATA46 :1; + __IO uint32_t DATA47 :1; + }; + }; +} stc_can_if2dtb_b_field_t; + +typedef struct stc_can_treqr_field +{ + __IO uint32_t TXRQST1 :1; + __IO uint32_t TXRQST2 :1; + __IO uint32_t TXRQST3 :1; + __IO uint32_t TXRQST4 :1; + __IO uint32_t TXRQST5 :1; + __IO uint32_t TXRQST6 :1; + __IO uint32_t TXRQST7 :1; + __IO uint32_t TXRQST8 :1; + __IO uint32_t TXRQST9 :1; + __IO uint32_t TXRQST10 :1; + __IO uint32_t TXRQST11 :1; + __IO uint32_t TXRQST12 :1; + __IO uint32_t TXRQST13 :1; + __IO uint32_t TXRQST14 :1; + __IO uint32_t TXRQST15 :1; + __IO uint32_t TXRQST16 :1; + __IO uint32_t TXRQST17 :1; + __IO uint32_t TXRQST18 :1; + __IO uint32_t TXRQST19 :1; + __IO uint32_t TXRQST20 :1; + __IO uint32_t TXRQST21 :1; + __IO uint32_t TXRQST22 :1; + __IO uint32_t TXRQST23 :1; + __IO uint32_t TXRQST24 :1; + __IO uint32_t TXRQST25 :1; + __IO uint32_t TXRQST26 :1; + __IO uint32_t TXRQST27 :1; + __IO uint32_t TXRQST28 :1; + __IO uint32_t TXRQST29 :1; + __IO uint32_t TXRQST30 :1; + __IO uint32_t TXRQST31 :1; + __IO uint32_t TXRQST32 :1; +} stc_can_treqr_field_t; + +typedef struct stc_can_newdt_field +{ + __IO uint32_t NEWDAT1 :1; + __IO uint32_t NEWDAT2 :1; + __IO uint32_t NEWDAT3 :1; + __IO uint32_t NEWDAT4 :1; + __IO uint32_t NEWDAT5 :1; + __IO uint32_t NEWDAT6 :1; + __IO uint32_t NEWDAT7 :1; + __IO uint32_t NEWDAT8 :1; + __IO uint32_t NEWDAT9 :1; + __IO uint32_t NEWDAT10 :1; + __IO uint32_t NEWDAT11 :1; + __IO uint32_t NEWDAT12 :1; + __IO uint32_t NEWDAT13 :1; + __IO uint32_t NEWDAT14 :1; + __IO uint32_t NEWDAT15 :1; + __IO uint32_t NEWDAT16 :1; + __IO uint32_t NEWDAT17 :1; + __IO uint32_t NEWDAT18 :1; + __IO uint32_t NEWDAT19 :1; + __IO uint32_t NEWDAT20 :1; + __IO uint32_t NEWDAT21 :1; + __IO uint32_t NEWDAT22 :1; + __IO uint32_t NEWDAT23 :1; + __IO uint32_t NEWDAT24 :1; + __IO uint32_t NEWDAT25 :1; + __IO uint32_t NEWDAT26 :1; + __IO uint32_t NEWDAT27 :1; + __IO uint32_t NEWDAT28 :1; + __IO uint32_t NEWDAT29 :1; + __IO uint32_t NEWDAT30 :1; + __IO uint32_t NEWDAT31 :1; + __IO uint32_t NEWDAT32 :1; +} stc_can_newdt_field_t; + +typedef struct stc_can_intpnd_field +{ + __IO uint32_t INTPND1 :1; + __IO uint32_t INTPND2 :1; + __IO uint32_t INTPND3 :1; + __IO uint32_t INTPND4 :1; + __IO uint32_t INTPND5 :1; + __IO uint32_t INTPND6 :1; + __IO uint32_t INTPND7 :1; + __IO uint32_t INTPND8 :1; + __IO uint32_t INTPND9 :1; + __IO uint32_t INTPND10 :1; + __IO uint32_t INTPND11 :1; + __IO uint32_t INTPND12 :1; + __IO uint32_t INTPND13 :1; + __IO uint32_t INTPND14 :1; + __IO uint32_t INTPND15 :1; + __IO uint32_t INTPND16 :1; + __IO uint32_t INTPND17 :1; + __IO uint32_t INTPND18 :1; + __IO uint32_t INTPND19 :1; + __IO uint32_t INTPND20 :1; + __IO uint32_t INTPND21 :1; + __IO uint32_t INTPND22 :1; + __IO uint32_t INTPND23 :1; + __IO uint32_t INTPND24 :1; + __IO uint32_t INTPND25 :1; + __IO uint32_t INTPND26 :1; + __IO uint32_t INTPND27 :1; + __IO uint32_t INTPND28 :1; + __IO uint32_t INTPND29 :1; + __IO uint32_t INTPND30 :1; + __IO uint32_t INTPND31 :1; + __IO uint32_t INTPND32 :1; +} stc_can_intpnd_field_t; + +typedef struct stc_can_msgval_field +{ + __IO uint32_t MSGVAL1 :1; + __IO uint32_t MSGVAL2 :1; + __IO uint32_t MSGVAL3 :1; + __IO uint32_t MSGVAL4 :1; + __IO uint32_t MSGVAL5 :1; + __IO uint32_t MSGVAL6 :1; + __IO uint32_t MSGVAL7 :1; + __IO uint32_t MSGVAL8 :1; + __IO uint32_t MSGVAL9 :1; + __IO uint32_t MSGVAL10 :1; + __IO uint32_t MSGVAL11 :1; + __IO uint32_t MSGVAL12 :1; + __IO uint32_t MSGVAL13 :1; + __IO uint32_t MSGVAL14 :1; + __IO uint32_t MSGVAL15 :1; + __IO uint32_t MSGVAL16 :1; + __IO uint32_t MSGVAL17 :1; + __IO uint32_t MSGVAL18 :1; + __IO uint32_t MSGVAL19 :1; + __IO uint32_t MSGVAL20 :1; + __IO uint32_t MSGVAL21 :1; + __IO uint32_t MSGVAL22 :1; + __IO uint32_t MSGVAL23 :1; + __IO uint32_t MSGVAL24 :1; + __IO uint32_t MSGVAL25 :1; + __IO uint32_t MSGVAL26 :1; + __IO uint32_t MSGVAL27 :1; + __IO uint32_t MSGVAL28 :1; + __IO uint32_t MSGVAL29 :1; + __IO uint32_t MSGVAL30 :1; + __IO uint32_t MSGVAL31 :1; + __IO uint32_t MSGVAL32 :1; +} stc_can_msgval_field_t; + +/******************************************************************************* +* CANFD_MODULE +*******************************************************************************/ +typedef struct stc_canfd_crel_field +{ + union { + struct { + __IO uint32_t DAY :8; + __IO uint32_t MON :8; + __IO uint32_t YEAR :4; + __IO uint32_t SUBSTEP :4; + __IO uint32_t STEP :4; + __IO uint32_t REL :4; + }; + struct { + __IO uint32_t DAY0 :1; + __IO uint32_t DAY1 :1; + __IO uint32_t DAY2 :1; + __IO uint32_t DAY3 :1; + __IO uint32_t DAY4 :1; + __IO uint32_t DAY5 :1; + __IO uint32_t DAY6 :1; + __IO uint32_t DAY7 :1; + __IO uint32_t MON0 :1; + __IO uint32_t MON1 :1; + __IO uint32_t MON2 :1; + __IO uint32_t MON3 :1; + __IO uint32_t MON4 :1; + __IO uint32_t MON5 :1; + __IO uint32_t MON6 :1; + __IO uint32_t MON7 :1; + __IO uint32_t YEAR0 :1; + __IO uint32_t YEAR1 :1; + __IO uint32_t YEAR2 :1; + __IO uint32_t YEAR3 :1; + __IO uint32_t SUBSTEP0 :1; + __IO uint32_t SUBSTEP1 :1; + __IO uint32_t SUBSTEP2 :1; + __IO uint32_t SUBSTEP3 :1; + __IO uint32_t STEP0 :1; + __IO uint32_t STEP1 :1; + __IO uint32_t STEP2 :1; + __IO uint32_t STEP3 :1; + __IO uint32_t REL0 :1; + __IO uint32_t REL1 :1; + __IO uint32_t REL2 :1; + __IO uint32_t REL3 :1; + }; + }; +} stc_canfd_crel_field_t; + +typedef struct stc_canfd_endn_field +{ + union { + struct { + __IO uint32_t ETV :32; + }; + struct { + __IO uint32_t ETV0 :1; + __IO uint32_t ETV1 :1; + __IO uint32_t ETV2 :1; + __IO uint32_t ETV3 :1; + __IO uint32_t ETV4 :1; + __IO uint32_t ETV5 :1; + __IO uint32_t ETV6 :1; + __IO uint32_t ETV7 :1; + __IO uint32_t ETV8 :1; + __IO uint32_t ETV9 :1; + __IO uint32_t ETV10 :1; + __IO uint32_t ETV11 :1; + __IO uint32_t ETV12 :1; + __IO uint32_t ETV13 :1; + __IO uint32_t ETV14 :1; + __IO uint32_t ETV15 :1; + __IO uint32_t ETV16 :1; + __IO uint32_t ETV17 :1; + __IO uint32_t ETV18 :1; + __IO uint32_t ETV19 :1; + __IO uint32_t ETV20 :1; + __IO uint32_t ETV21 :1; + __IO uint32_t ETV22 :1; + __IO uint32_t ETV23 :1; + __IO uint32_t ETV24 :1; + __IO uint32_t ETV25 :1; + __IO uint32_t ETV26 :1; + __IO uint32_t ETV27 :1; + __IO uint32_t ETV28 :1; + __IO uint32_t ETV29 :1; + __IO uint32_t ETV30 :1; + __IO uint32_t ETV31 :1; + }; + }; +} stc_canfd_endn_field_t; + +typedef struct stc_canfd_fbtp_field +{ + union { + struct { + __IO uint32_t FSJW :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FTSEG2 :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t FTSEG1 :4; + __IO uint32_t RESERVED4 :4; + __IO uint32_t FBRP :5; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TDC :1; + __IO uint32_t TDCO :5; + __IO uint32_t RESERVED8 :3; + }; + struct { + __IO uint32_t FSJW0 :1; + __IO uint32_t FSJW1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t FTSEG20 :1; + __IO uint32_t FTSEG21 :1; + __IO uint32_t FTSEG22 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t FTSEG10 :1; + __IO uint32_t FTSEG11 :1; + __IO uint32_t FTSEG12 :1; + __IO uint32_t FTSEG13 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t FBRP0 :1; + __IO uint32_t FBRP1 :1; + __IO uint32_t FBRP2 :1; + __IO uint32_t FBRP3 :1; + __IO uint32_t FBRP4 :1; + __IO uint32_t RESERVED7 :3; + __IO uint32_t TDCO0 :1; + __IO uint32_t TDCO1 :1; + __IO uint32_t TDCO2 :1; + __IO uint32_t TDCO3 :1; + __IO uint32_t TDCO4 :1; + __IO uint32_t RESERVED9 :3; + }; + }; +} stc_canfd_fbtp_field_t; + +typedef struct stc_canfd_test_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t LBCK :1; + __IO uint32_t TX :2; + __IO uint32_t RX :1; + __IO uint32_t TDCV :6; + __IO uint32_t RESERVED3 :18; + }; + struct { + __IO uint32_t RESERVED1 :5; + __IO uint32_t TX0 :1; + __IO uint32_t TX1 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t TDCV0 :1; + __IO uint32_t TDCV1 :1; + __IO uint32_t TDCV2 :1; + __IO uint32_t TDCV3 :1; + __IO uint32_t TDCV4 :1; + __IO uint32_t TDCV5 :1; + __IO uint32_t RESERVED4 :18; + }; + }; +} stc_canfd_test_field_t; + +typedef struct stc_canfd_rwd_field +{ + union { + struct { + __IO uint32_t WDC :8; + __IO uint32_t WDV :8; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t WDC0 :1; + __IO uint32_t WDC1 :1; + __IO uint32_t WDC2 :1; + __IO uint32_t WDC3 :1; + __IO uint32_t WDC4 :1; + __IO uint32_t WDC5 :1; + __IO uint32_t WDC6 :1; + __IO uint32_t WDC7 :1; + __IO uint32_t WDV0 :1; + __IO uint32_t WDV1 :1; + __IO uint32_t WDV2 :1; + __IO uint32_t WDV3 :1; + __IO uint32_t WDV4 :1; + __IO uint32_t WDV5 :1; + __IO uint32_t WDV6 :1; + __IO uint32_t WDV7 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_rwd_field_t; + +typedef struct stc_canfd_cccr_field +{ + union { + struct { + __IO uint32_t INIT :1; + __IO uint32_t CCE :1; + __IO uint32_t ASM :1; + __IO uint32_t CSA :1; + __IO uint32_t CSR :1; + __IO uint32_t MON :1; + __IO uint32_t DAR :1; + __IO uint32_t TEST :1; + __IO uint32_t CME :2; + __IO uint32_t CMR :2; + __IO uint32_t FDO :1; + __IO uint32_t FDBS :1; + __IO uint32_t TXP :1; + __IO uint32_t RESERVED1 :17; + }; + struct { + __IO uint32_t RESERVED0 :8; + __IO uint32_t CME0 :1; + __IO uint32_t CME1 :1; + __IO uint32_t CMR0 :1; + __IO uint32_t CMR1 :1; + __IO uint32_t RESERVED2 :20; + }; + }; +} stc_canfd_cccr_field_t; + +typedef struct stc_canfd_btp_field +{ + union { + struct { + __IO uint32_t SJW :4; + __IO uint32_t TSEG2 :4; + __IO uint32_t TSEG1 :6; + __IO uint32_t RESERVED0 :2; + __IO uint32_t BRP :10; + __IO uint32_t RESERVED2 :6; + }; + struct { + __IO uint32_t SJW0 :1; + __IO uint32_t SJW1 :1; + __IO uint32_t SJW2 :1; + __IO uint32_t SJW3 :1; + __IO uint32_t TSEG20 :1; + __IO uint32_t TSEG21 :1; + __IO uint32_t TSEG22 :1; + __IO uint32_t TSEG23 :1; + __IO uint32_t TSEG10 :1; + __IO uint32_t TSEG11 :1; + __IO uint32_t TSEG12 :1; + __IO uint32_t TSEG13 :1; + __IO uint32_t TSEG14 :1; + __IO uint32_t TSEG15 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t BRP0 :1; + __IO uint32_t BRP1 :1; + __IO uint32_t BRP2 :1; + __IO uint32_t BRP3 :1; + __IO uint32_t BRP4 :1; + __IO uint32_t BRP5 :1; + __IO uint32_t BRP6 :1; + __IO uint32_t BRP7 :1; + __IO uint32_t BRP8 :1; + __IO uint32_t BRP9 :1; + __IO uint32_t RESERVED3 :6; + }; + }; +} stc_canfd_btp_field_t; + +typedef struct stc_canfd_tscc_field +{ + union { + struct { + __IO uint32_t TSS :2; + __IO uint32_t RESERVED0 :14; + __IO uint32_t TCP :4; + __IO uint32_t RESERVED2 :12; + }; + struct { + __IO uint32_t TSS0 :1; + __IO uint32_t TSS1 :1; + __IO uint32_t RESERVED1 :14; + __IO uint32_t TCP0 :1; + __IO uint32_t TCP1 :1; + __IO uint32_t TCP2 :1; + __IO uint32_t TCP3 :1; + __IO uint32_t RESERVED3 :12; + }; + }; +} stc_canfd_tscc_field_t; + +typedef struct stc_canfd_tscv_field +{ + union { + struct { + __IO uint32_t TSC :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t TSC0 :1; + __IO uint32_t TSC1 :1; + __IO uint32_t TSC2 :1; + __IO uint32_t TSC3 :1; + __IO uint32_t TSC4 :1; + __IO uint32_t TSC5 :1; + __IO uint32_t TSC6 :1; + __IO uint32_t TSC7 :1; + __IO uint32_t TSC8 :1; + __IO uint32_t TSC9 :1; + __IO uint32_t TSC10 :1; + __IO uint32_t TSC11 :1; + __IO uint32_t TSC12 :1; + __IO uint32_t TSC13 :1; + __IO uint32_t TSC14 :1; + __IO uint32_t TSC15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_tscv_field_t; + +typedef struct stc_canfd_tocc_field +{ + union { + struct { + __IO uint32_t ETOC :1; + __IO uint32_t TOS :2; + __IO uint32_t RESERVED1 :13; + __IO uint32_t TOP :16; + }; + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t TOS0 :1; + __IO uint32_t TOS1 :1; + __IO uint32_t RESERVED2 :13; + __IO uint32_t TOP0 :1; + __IO uint32_t TOP1 :1; + __IO uint32_t TOP2 :1; + __IO uint32_t TOP3 :1; + __IO uint32_t TOP4 :1; + __IO uint32_t TOP5 :1; + __IO uint32_t TOP6 :1; + __IO uint32_t TOP7 :1; + __IO uint32_t TOP8 :1; + __IO uint32_t TOP9 :1; + __IO uint32_t TOP10 :1; + __IO uint32_t TOP11 :1; + __IO uint32_t TOP12 :1; + __IO uint32_t TOP13 :1; + __IO uint32_t TOP14 :1; + __IO uint32_t TOP15 :1; + }; + }; +} stc_canfd_tocc_field_t; + +typedef struct stc_canfd_tocv_field +{ + union { + struct { + __IO uint32_t TOC :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t TOC0 :1; + __IO uint32_t TOC1 :1; + __IO uint32_t TOC2 :1; + __IO uint32_t TOC3 :1; + __IO uint32_t TOC4 :1; + __IO uint32_t TOC5 :1; + __IO uint32_t TOC6 :1; + __IO uint32_t TOC7 :1; + __IO uint32_t TOC8 :1; + __IO uint32_t TOC9 :1; + __IO uint32_t TOC10 :1; + __IO uint32_t TOC11 :1; + __IO uint32_t TOC12 :1; + __IO uint32_t TOC13 :1; + __IO uint32_t TOC14 :1; + __IO uint32_t TOC15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_tocv_field_t; + +typedef struct stc_canfd_ecr_field +{ + union { + struct { + __IO uint32_t TEC :8; + __IO uint32_t REC :7; + __IO uint32_t RP :1; + __IO uint32_t CEL :8; + __IO uint32_t RESERVED1 :8; + }; + struct { + __IO uint32_t TEC0 :1; + __IO uint32_t TEC1 :1; + __IO uint32_t TEC2 :1; + __IO uint32_t TEC3 :1; + __IO uint32_t TEC4 :1; + __IO uint32_t TEC5 :1; + __IO uint32_t TEC6 :1; + __IO uint32_t TEC7 :1; + __IO uint32_t REC0 :1; + __IO uint32_t REC1 :1; + __IO uint32_t REC2 :1; + __IO uint32_t REC3 :1; + __IO uint32_t REC4 :1; + __IO uint32_t REC5 :1; + __IO uint32_t REC6 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t CEL0 :1; + __IO uint32_t CEL1 :1; + __IO uint32_t CEL2 :1; + __IO uint32_t CEL3 :1; + __IO uint32_t CEL4 :1; + __IO uint32_t CEL5 :1; + __IO uint32_t CEL6 :1; + __IO uint32_t CEL7 :1; + __IO uint32_t RESERVED2 :8; + }; + }; +} stc_canfd_ecr_field_t; + +typedef struct stc_canfd_psr_field +{ + union { + struct { + __IO uint32_t LEC :3; + __IO uint32_t ACT :2; + __IO uint32_t EP :1; + __IO uint32_t EW :1; + __IO uint32_t BO :1; + __IO uint32_t FLEC :3; + __IO uint32_t RESI :1; + __IO uint32_t RBRS :1; + __IO uint32_t REDL :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t LEC0 :1; + __IO uint32_t LEC1 :1; + __IO uint32_t LEC2 :1; + __IO uint32_t ACT0 :1; + __IO uint32_t ACT1 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t FLEC0 :1; + __IO uint32_t FLEC1 :1; + __IO uint32_t FLEC2 :1; + __IO uint32_t RESERVED2 :21; + }; + }; +} stc_canfd_psr_field_t; + +typedef struct stc_canfd_ir_field +{ + __IO uint32_t RF0N :1; + __IO uint32_t RF0W :1; + __IO uint32_t RF0F :1; + __IO uint32_t RF0L :1; + __IO uint32_t RF1N :1; + __IO uint32_t RF1W :1; + __IO uint32_t RF1F :1; + __IO uint32_t RF1L :1; + __IO uint32_t HPM :1; + __IO uint32_t TC :1; + __IO uint32_t TCF :1; + __IO uint32_t TFE :1; + __IO uint32_t TEFN :1; + __IO uint32_t TEFW :1; + __IO uint32_t TEFF :1; + __IO uint32_t TEFL :1; + __IO uint32_t TSW :1; + __IO uint32_t MRAF :1; + __IO uint32_t TOO :1; + __IO uint32_t DRX :1; + __IO uint32_t BEC :1; + __IO uint32_t BEU :1; + __IO uint32_t ELO :1; + __IO uint32_t EP :1; + __IO uint32_t EW :1; + __IO uint32_t BO :1; + __IO uint32_t WDI :1; + __IO uint32_t CRCE :1; + __IO uint32_t BE :1; + __IO uint32_t ACKE :1; + __IO uint32_t FOE :1; + __IO uint32_t STE :1; +} stc_canfd_ir_field_t; + +typedef struct stc_canfd_ie_field +{ + __IO uint32_t RF0NE :1; + __IO uint32_t RF0WE :1; + __IO uint32_t RF0FE :1; + __IO uint32_t RF0LE :1; + __IO uint32_t RF1NE :1; + __IO uint32_t RF1WE :1; + __IO uint32_t RF1FE :1; + __IO uint32_t RF1LE :1; + __IO uint32_t HPME :1; + __IO uint32_t TCE :1; + __IO uint32_t TCFE :1; + __IO uint32_t TFEE :1; + __IO uint32_t TEFNE :1; + __IO uint32_t TEFWE :1; + __IO uint32_t TEFFE :1; + __IO uint32_t TEFLE :1; + __IO uint32_t TSWE :1; + __IO uint32_t MRAFE :1; + __IO uint32_t TOOE :1; + __IO uint32_t DRXE :1; + __IO uint32_t BECE :1; + __IO uint32_t BEUE :1; + __IO uint32_t ELOE :1; + __IO uint32_t EPE :1; + __IO uint32_t EWE :1; + __IO uint32_t BOE :1; + __IO uint32_t WDIE :1; + __IO uint32_t CRCEE :1; + __IO uint32_t BEE :1; + __IO uint32_t ACKEE :1; + __IO uint32_t FOEE :1; + __IO uint32_t STEE :1; +} stc_canfd_ie_field_t; + +typedef struct stc_canfd_ils_field +{ + __IO uint32_t RF0NL :1; + __IO uint32_t RF0WL :1; + __IO uint32_t RF0FL :1; + __IO uint32_t RF0LL :1; + __IO uint32_t RF1NL :1; + __IO uint32_t RF1WL :1; + __IO uint32_t RF1FL :1; + __IO uint32_t RF1LL :1; + __IO uint32_t HPML :1; + __IO uint32_t TCL :1; + __IO uint32_t TCFL :1; + __IO uint32_t TFEL :1; + __IO uint32_t TEFNL :1; + __IO uint32_t TEFWL :1; + __IO uint32_t TEFFL :1; + __IO uint32_t TEFLL :1; + __IO uint32_t TSWL :1; + __IO uint32_t MRAFL :1; + __IO uint32_t TOOL :1; + __IO uint32_t DRXL :1; + __IO uint32_t BECL :1; + __IO uint32_t BEUL :1; + __IO uint32_t ELOL :1; + __IO uint32_t EPL :1; + __IO uint32_t EWL :1; + __IO uint32_t BOL :1; + __IO uint32_t WDIL :1; + __IO uint32_t CRCEL :1; + __IO uint32_t BEL :1; + __IO uint32_t ACKEL :1; + __IO uint32_t FOEL :1; + __IO uint32_t STEL :1; +} stc_canfd_ils_field_t; + +typedef struct stc_canfd_ile_field +{ + __IO uint32_t EINT0 :1; + __IO uint32_t EINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_canfd_ile_field_t; + +typedef struct stc_canfd_gfc_field +{ + union { + struct { + __IO uint32_t RRFE :1; + __IO uint32_t RRFS :1; + __IO uint32_t ANFE :2; + __IO uint32_t ANFS :2; + __IO uint32_t RESERVED1 :26; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t ANFE0 :1; + __IO uint32_t ANFE1 :1; + __IO uint32_t ANFS0 :1; + __IO uint32_t ANFS1 :1; + __IO uint32_t RESERVED2 :26; + }; + }; +} stc_canfd_gfc_field_t; + +typedef struct stc_canfd_sidfc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t FLSSA :14; + __IO uint32_t LSS :8; + __IO uint32_t RESERVED2 :8; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t FLSSA0 :1; + __IO uint32_t FLSSA1 :1; + __IO uint32_t FLSSA2 :1; + __IO uint32_t FLSSA3 :1; + __IO uint32_t FLSSA4 :1; + __IO uint32_t FLSSA5 :1; + __IO uint32_t FLSSA6 :1; + __IO uint32_t FLSSA7 :1; + __IO uint32_t FLSSA8 :1; + __IO uint32_t FLSSA9 :1; + __IO uint32_t FLSSA10 :1; + __IO uint32_t FLSSA11 :1; + __IO uint32_t FLSSA12 :1; + __IO uint32_t FLSSA13 :1; + __IO uint32_t LSS0 :1; + __IO uint32_t LSS1 :1; + __IO uint32_t LSS2 :1; + __IO uint32_t LSS3 :1; + __IO uint32_t LSS4 :1; + __IO uint32_t LSS5 :1; + __IO uint32_t LSS6 :1; + __IO uint32_t LSS7 :1; + __IO uint32_t RESERVED3 :8; + }; + }; +} stc_canfd_sidfc_field_t; + +typedef struct stc_canfd_xidfc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t FLESA :14; + __IO uint32_t LSE :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t FLESA0 :1; + __IO uint32_t FLESA1 :1; + __IO uint32_t FLESA2 :1; + __IO uint32_t FLESA3 :1; + __IO uint32_t FLESA4 :1; + __IO uint32_t FLESA5 :1; + __IO uint32_t FLESA6 :1; + __IO uint32_t FLESA7 :1; + __IO uint32_t FLESA8 :1; + __IO uint32_t FLESA9 :1; + __IO uint32_t FLESA10 :1; + __IO uint32_t FLESA11 :1; + __IO uint32_t FLESA12 :1; + __IO uint32_t FLESA13 :1; + __IO uint32_t LSE0 :1; + __IO uint32_t LSE1 :1; + __IO uint32_t LSE2 :1; + __IO uint32_t LSE3 :1; + __IO uint32_t LSE4 :1; + __IO uint32_t LSE5 :1; + __IO uint32_t LSE6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_canfd_xidfc_field_t; + +typedef struct stc_canfd_xidam_field +{ + union { + struct { + __IO uint32_t EIDM :29; + __IO uint32_t RESERVED0 :3; + }; + struct { + __IO uint32_t EIDM0 :1; + __IO uint32_t EIDM1 :1; + __IO uint32_t EIDM2 :1; + __IO uint32_t EIDM3 :1; + __IO uint32_t EIDM4 :1; + __IO uint32_t EIDM5 :1; + __IO uint32_t EIDM6 :1; + __IO uint32_t EIDM7 :1; + __IO uint32_t EIDM8 :1; + __IO uint32_t EIDM9 :1; + __IO uint32_t EIDM10 :1; + __IO uint32_t EIDM11 :1; + __IO uint32_t EIDM12 :1; + __IO uint32_t EIDM13 :1; + __IO uint32_t EIDM14 :1; + __IO uint32_t EIDM15 :1; + __IO uint32_t EIDM16 :1; + __IO uint32_t EIDM17 :1; + __IO uint32_t EIDM18 :1; + __IO uint32_t EIDM19 :1; + __IO uint32_t EIDM20 :1; + __IO uint32_t EIDM21 :1; + __IO uint32_t EIDM22 :1; + __IO uint32_t EIDM23 :1; + __IO uint32_t EIDM24 :1; + __IO uint32_t EIDM25 :1; + __IO uint32_t EIDM26 :1; + __IO uint32_t EIDM27 :1; + __IO uint32_t EIDM28 :1; + __IO uint32_t RESERVED1 :3; + }; + }; +} stc_canfd_xidam_field_t; + +typedef struct stc_canfd_hpms_field +{ + union { + struct { + __IO uint32_t BIDX :6; + __IO uint32_t MSI :2; + __IO uint32_t FIDX :7; + __IO uint32_t FLST :1; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t BIDX0 :1; + __IO uint32_t BIDX1 :1; + __IO uint32_t BIDX2 :1; + __IO uint32_t BIDX3 :1; + __IO uint32_t BIDX4 :1; + __IO uint32_t BIDX5 :1; + __IO uint32_t MSI0 :1; + __IO uint32_t MSI1 :1; + __IO uint32_t FIDX0 :1; + __IO uint32_t FIDX1 :1; + __IO uint32_t FIDX2 :1; + __IO uint32_t FIDX3 :1; + __IO uint32_t FIDX4 :1; + __IO uint32_t FIDX5 :1; + __IO uint32_t FIDX6 :1; + __IO uint32_t RESERVED1 :17; + }; + }; +} stc_canfd_hpms_field_t; + +typedef struct stc_canfd_ndat1_field +{ + __IO uint32_t ND0 :1; + __IO uint32_t ND1 :1; + __IO uint32_t ND2 :1; + __IO uint32_t ND3 :1; + __IO uint32_t ND4 :1; + __IO uint32_t ND5 :1; + __IO uint32_t ND6 :1; + __IO uint32_t ND7 :1; + __IO uint32_t ND8 :1; + __IO uint32_t ND9 :1; + __IO uint32_t ND10 :1; + __IO uint32_t ND11 :1; + __IO uint32_t ND12 :1; + __IO uint32_t ND13 :1; + __IO uint32_t ND14 :1; + __IO uint32_t ND15 :1; + __IO uint32_t ND16 :1; + __IO uint32_t ND17 :1; + __IO uint32_t ND18 :1; + __IO uint32_t ND19 :1; + __IO uint32_t ND20 :1; + __IO uint32_t ND21 :1; + __IO uint32_t ND22 :1; + __IO uint32_t ND23 :1; + __IO uint32_t ND24 :1; + __IO uint32_t ND25 :1; + __IO uint32_t ND26 :1; + __IO uint32_t ND27 :1; + __IO uint32_t ND28 :1; + __IO uint32_t ND29 :1; + __IO uint32_t ND30 :1; + __IO uint32_t ND31 :1; +} stc_canfd_ndat1_field_t; + +typedef struct stc_canfd_ndat2_field +{ + __IO uint32_t ND32 :1; + __IO uint32_t ND33 :1; + __IO uint32_t ND34 :1; + __IO uint32_t ND35 :1; + __IO uint32_t ND36 :1; + __IO uint32_t ND37 :1; + __IO uint32_t ND38 :1; + __IO uint32_t ND39 :1; + __IO uint32_t ND40 :1; + __IO uint32_t ND41 :1; + __IO uint32_t ND42 :1; + __IO uint32_t ND43 :1; + __IO uint32_t ND44 :1; + __IO uint32_t ND45 :1; + __IO uint32_t ND46 :1; + __IO uint32_t ND47 :1; + __IO uint32_t ND48 :1; + __IO uint32_t ND49 :1; + __IO uint32_t ND50 :1; + __IO uint32_t ND51 :1; + __IO uint32_t ND52 :1; + __IO uint32_t ND53 :1; + __IO uint32_t ND54 :1; + __IO uint32_t ND55 :1; + __IO uint32_t ND56 :1; + __IO uint32_t ND57 :1; + __IO uint32_t ND58 :1; + __IO uint32_t ND59 :1; + __IO uint32_t ND60 :1; + __IO uint32_t ND61 :1; + __IO uint32_t ND62 :1; + __IO uint32_t ND63 :1; +} stc_canfd_ndat2_field_t; + +typedef struct stc_canfd_rxf0c_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t F0SA :14; + __IO uint32_t F0S :7; + __IO uint32_t RESERVED2 :1; + __IO uint32_t F0WM :7; + __IO uint32_t F0OM :1; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t F0SA0 :1; + __IO uint32_t F0SA1 :1; + __IO uint32_t F0SA2 :1; + __IO uint32_t F0SA3 :1; + __IO uint32_t F0SA4 :1; + __IO uint32_t F0SA5 :1; + __IO uint32_t F0SA6 :1; + __IO uint32_t F0SA7 :1; + __IO uint32_t F0SA8 :1; + __IO uint32_t F0SA9 :1; + __IO uint32_t F0SA10 :1; + __IO uint32_t F0SA11 :1; + __IO uint32_t F0SA12 :1; + __IO uint32_t F0SA13 :1; + __IO uint32_t F0S0 :1; + __IO uint32_t F0S1 :1; + __IO uint32_t F0S2 :1; + __IO uint32_t F0S3 :1; + __IO uint32_t F0S4 :1; + __IO uint32_t F0S5 :1; + __IO uint32_t F0S6 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t F0WM0 :1; + __IO uint32_t F0WM1 :1; + __IO uint32_t F0WM2 :1; + __IO uint32_t F0WM3 :1; + __IO uint32_t F0WM4 :1; + __IO uint32_t F0WM5 :1; + __IO uint32_t F0WM6 :1; + __IO uint32_t RESERVED4 :1; + }; + }; +} stc_canfd_rxf0c_field_t; + +typedef struct stc_canfd_rxf0s_field +{ + union { + struct { + __IO uint32_t F0FL :7; + __IO uint32_t RESERVED0 :1; + __IO uint32_t F0GI :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t F0PI :6; + __IO uint32_t RESERVED4 :2; + __IO uint32_t F0F :1; + __IO uint32_t RF0L :1; + __IO uint32_t RESERVED5 :6; + }; + struct { + __IO uint32_t F0FL0 :1; + __IO uint32_t F0FL1 :1; + __IO uint32_t F0FL2 :1; + __IO uint32_t F0FL3 :1; + __IO uint32_t F0FL4 :1; + __IO uint32_t F0FL5 :1; + __IO uint32_t F0FL6 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t F0GI0 :1; + __IO uint32_t F0GI1 :1; + __IO uint32_t F0GI2 :1; + __IO uint32_t F0GI3 :1; + __IO uint32_t F0GI4 :1; + __IO uint32_t F0GI5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t F0PI0 :1; + __IO uint32_t F0PI1 :1; + __IO uint32_t F0PI2 :1; + __IO uint32_t F0PI3 :1; + __IO uint32_t F0PI4 :1; + __IO uint32_t F0PI5 :1; + __IO uint32_t RESERVED6 :10; + }; + }; +} stc_canfd_rxf0s_field_t; + +typedef struct stc_canfd_rxf0a_field +{ + union { + struct { + __IO uint32_t F0AI :6; + __IO uint32_t RESERVED0 :26; + }; + struct { + __IO uint32_t F0AI0 :1; + __IO uint32_t F0AI1 :1; + __IO uint32_t F0AI2 :1; + __IO uint32_t F0AI3 :1; + __IO uint32_t F0AI4 :1; + __IO uint32_t F0AI5 :1; + __IO uint32_t RESERVED1 :26; + }; + }; +} stc_canfd_rxf0a_field_t; + +typedef struct stc_canfd_rxbc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t RBSA :14; + __IO uint32_t RESERVED2 :16; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t RBSA0 :1; + __IO uint32_t RBSA1 :1; + __IO uint32_t RBSA2 :1; + __IO uint32_t RBSA3 :1; + __IO uint32_t RBSA4 :1; + __IO uint32_t RBSA5 :1; + __IO uint32_t RBSA6 :1; + __IO uint32_t RBSA7 :1; + __IO uint32_t RBSA8 :1; + __IO uint32_t RBSA9 :1; + __IO uint32_t RBSA10 :1; + __IO uint32_t RBSA11 :1; + __IO uint32_t RBSA12 :1; + __IO uint32_t RBSA13 :1; + __IO uint32_t RESERVED3 :16; + }; + }; +} stc_canfd_rxbc_field_t; + +typedef struct stc_canfd_rxf1c_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t F1SA :14; + __IO uint32_t F1S :7; + __IO uint32_t RESERVED2 :1; + __IO uint32_t F1WM :7; + __IO uint32_t F1OM :1; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t F1SA0 :1; + __IO uint32_t F1SA1 :1; + __IO uint32_t F1SA2 :1; + __IO uint32_t F1SA3 :1; + __IO uint32_t F1SA4 :1; + __IO uint32_t F1SA5 :1; + __IO uint32_t F1SA6 :1; + __IO uint32_t F1SA7 :1; + __IO uint32_t F1SA8 :1; + __IO uint32_t F1SA9 :1; + __IO uint32_t F1SA10 :1; + __IO uint32_t F1SA11 :1; + __IO uint32_t F1SA12 :1; + __IO uint32_t F1SA13 :1; + __IO uint32_t F1S0 :1; + __IO uint32_t F1S1 :1; + __IO uint32_t F1S2 :1; + __IO uint32_t F1S3 :1; + __IO uint32_t F1S4 :1; + __IO uint32_t F1S5 :1; + __IO uint32_t F1S6 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t F1WM0 :1; + __IO uint32_t F1WM1 :1; + __IO uint32_t F1WM2 :1; + __IO uint32_t F1WM3 :1; + __IO uint32_t F1WM4 :1; + __IO uint32_t F1WM5 :1; + __IO uint32_t F1WM6 :1; + __IO uint32_t RESERVED4 :1; + }; + }; +} stc_canfd_rxf1c_field_t; + +typedef struct stc_canfd_rxf1s_field +{ + union { + struct { + __IO uint32_t F1FL :7; + __IO uint32_t RESERVED0 :1; + __IO uint32_t F1GI :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t F1PI :6; + __IO uint32_t RESERVED4 :2; + __IO uint32_t F1F :1; + __IO uint32_t RF1L :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t DMS :2; + }; + struct { + __IO uint32_t F1FL0 :1; + __IO uint32_t F1FL1 :1; + __IO uint32_t F1FL2 :1; + __IO uint32_t F1FL3 :1; + __IO uint32_t F1FL4 :1; + __IO uint32_t F1FL5 :1; + __IO uint32_t F1FL6 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t F1GI0 :1; + __IO uint32_t F1GI1 :1; + __IO uint32_t F1GI2 :1; + __IO uint32_t F1GI3 :1; + __IO uint32_t F1GI4 :1; + __IO uint32_t F1GI5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t F1PI0 :1; + __IO uint32_t F1PI1 :1; + __IO uint32_t F1PI2 :1; + __IO uint32_t F1PI3 :1; + __IO uint32_t F1PI4 :1; + __IO uint32_t F1PI5 :1; + __IO uint32_t RESERVED6 :8; + __IO uint32_t DMS0 :1; + __IO uint32_t DMS1 :1; + }; + }; +} stc_canfd_rxf1s_field_t; + +typedef struct stc_canfd_rxf1a_field +{ + union { + struct { + __IO uint32_t F1AI :6; + __IO uint32_t RESERVED0 :26; + }; + struct { + __IO uint32_t F1AI0 :1; + __IO uint32_t F1AI1 :1; + __IO uint32_t F1AI2 :1; + __IO uint32_t F1AI3 :1; + __IO uint32_t F1AI4 :1; + __IO uint32_t F1AI5 :1; + __IO uint32_t RESERVED1 :26; + }; + }; +} stc_canfd_rxf1a_field_t; + +typedef struct stc_canfd_rxesc_field +{ + union { + struct { + __IO uint32_t F0DS :3; + __IO uint32_t RESERVED0 :1; + __IO uint32_t F1DS :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t RBDS :3; + __IO uint32_t RESERVED4 :21; + }; + struct { + __IO uint32_t F0DS0 :1; + __IO uint32_t F0DS1 :1; + __IO uint32_t F0DS2 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t F1DS0 :1; + __IO uint32_t F1DS1 :1; + __IO uint32_t F1DS2 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t RBDS0 :1; + __IO uint32_t RBDS1 :1; + __IO uint32_t RBDS2 :1; + __IO uint32_t RESERVED5 :21; + }; + }; +} stc_canfd_rxesc_field_t; + +typedef struct stc_canfd_txbc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TBSA :14; + __IO uint32_t NDTB :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TFQS :6; + __IO uint32_t TFQM :1; + __IO uint32_t RESERVED4 :1; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TBSA0 :1; + __IO uint32_t TBSA1 :1; + __IO uint32_t TBSA2 :1; + __IO uint32_t TBSA3 :1; + __IO uint32_t TBSA4 :1; + __IO uint32_t TBSA5 :1; + __IO uint32_t TBSA6 :1; + __IO uint32_t TBSA7 :1; + __IO uint32_t TBSA8 :1; + __IO uint32_t TBSA9 :1; + __IO uint32_t TBSA10 :1; + __IO uint32_t TBSA11 :1; + __IO uint32_t TBSA12 :1; + __IO uint32_t TBSA13 :1; + __IO uint32_t NDTB0 :1; + __IO uint32_t NDTB1 :1; + __IO uint32_t NDTB2 :1; + __IO uint32_t NDTB3 :1; + __IO uint32_t NDTB4 :1; + __IO uint32_t NDTB5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TFQS0 :1; + __IO uint32_t TFQS1 :1; + __IO uint32_t TFQS2 :1; + __IO uint32_t TFQS3 :1; + __IO uint32_t TFQS4 :1; + __IO uint32_t TFQS5 :1; + __IO uint32_t RESERVED5 :2; + }; + }; +} stc_canfd_txbc_field_t; + +typedef struct stc_canfd_txfqs_field +{ + union { + struct { + __IO uint32_t TFFL :6; + __IO uint32_t RESERVED0 :2; + __IO uint32_t TFGI :5; + __IO uint32_t RESERVED2 :3; + __IO uint32_t TFQPI :5; + __IO uint32_t TFQF :1; + __IO uint32_t RESERVED4 :10; + }; + struct { + __IO uint32_t TFFL0 :1; + __IO uint32_t TFFL1 :1; + __IO uint32_t TFFL2 :1; + __IO uint32_t TFFL3 :1; + __IO uint32_t TFFL4 :1; + __IO uint32_t TFFL5 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t TFGI0 :1; + __IO uint32_t TFGI1 :1; + __IO uint32_t TFGI2 :1; + __IO uint32_t TFGI3 :1; + __IO uint32_t TFGI4 :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t TFQPI0 :1; + __IO uint32_t TFQPI1 :1; + __IO uint32_t TFQPI2 :1; + __IO uint32_t TFQPI3 :1; + __IO uint32_t TFQPI4 :1; + __IO uint32_t RESERVED5 :11; + }; + }; +} stc_canfd_txfqs_field_t; + +typedef struct stc_canfd_txesc_field +{ + union { + struct { + __IO uint32_t TBDS :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t TBDS0 :1; + __IO uint32_t TBDS1 :1; + __IO uint32_t TBDS2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_canfd_txesc_field_t; + +typedef struct stc_canfd_txbrp_field +{ + __IO uint32_t TRP0 :1; + __IO uint32_t TRP1 :1; + __IO uint32_t TRP2 :1; + __IO uint32_t TRP3 :1; + __IO uint32_t TRP4 :1; + __IO uint32_t TRP5 :1; + __IO uint32_t TRP6 :1; + __IO uint32_t TRP7 :1; + __IO uint32_t TRP8 :1; + __IO uint32_t TRP9 :1; + __IO uint32_t TRP10 :1; + __IO uint32_t TRP11 :1; + __IO uint32_t TRP12 :1; + __IO uint32_t TRP13 :1; + __IO uint32_t TRP14 :1; + __IO uint32_t TRP15 :1; + __IO uint32_t TRP16 :1; + __IO uint32_t TRP17 :1; + __IO uint32_t TRP18 :1; + __IO uint32_t TRP19 :1; + __IO uint32_t TRP20 :1; + __IO uint32_t TRP21 :1; + __IO uint32_t TRP22 :1; + __IO uint32_t TRP23 :1; + __IO uint32_t TRP24 :1; + __IO uint32_t TRP25 :1; + __IO uint32_t TRP26 :1; + __IO uint32_t TRP27 :1; + __IO uint32_t TRP28 :1; + __IO uint32_t TRP29 :1; + __IO uint32_t TRP30 :1; + __IO uint32_t TRP31 :1; +} stc_canfd_txbrp_field_t; + +typedef struct stc_canfd_txbar_field +{ + __IO uint32_t AR0 :1; + __IO uint32_t AR1 :1; + __IO uint32_t AR2 :1; + __IO uint32_t AR3 :1; + __IO uint32_t AR4 :1; + __IO uint32_t AR5 :1; + __IO uint32_t AR6 :1; + __IO uint32_t AR7 :1; + __IO uint32_t AR8 :1; + __IO uint32_t AR9 :1; + __IO uint32_t AR10 :1; + __IO uint32_t AR11 :1; + __IO uint32_t AR12 :1; + __IO uint32_t AR13 :1; + __IO uint32_t AR14 :1; + __IO uint32_t AR15 :1; + __IO uint32_t AR16 :1; + __IO uint32_t AR17 :1; + __IO uint32_t AR18 :1; + __IO uint32_t AR19 :1; + __IO uint32_t AR20 :1; + __IO uint32_t AR21 :1; + __IO uint32_t AR22 :1; + __IO uint32_t AR23 :1; + __IO uint32_t AR24 :1; + __IO uint32_t AR25 :1; + __IO uint32_t AR26 :1; + __IO uint32_t AR27 :1; + __IO uint32_t AR28 :1; + __IO uint32_t AR29 :1; + __IO uint32_t AR30 :1; + __IO uint32_t AR31 :1; +} stc_canfd_txbar_field_t; + +typedef struct stc_canfd_txbcr_field +{ + __IO uint32_t CR0 :1; + __IO uint32_t CR1 :1; + __IO uint32_t CR2 :1; + __IO uint32_t CR3 :1; + __IO uint32_t CR4 :1; + __IO uint32_t CR5 :1; + __IO uint32_t CR6 :1; + __IO uint32_t CR7 :1; + __IO uint32_t CR8 :1; + __IO uint32_t CR9 :1; + __IO uint32_t CR10 :1; + __IO uint32_t CR11 :1; + __IO uint32_t CR12 :1; + __IO uint32_t CR13 :1; + __IO uint32_t CR14 :1; + __IO uint32_t CR15 :1; + __IO uint32_t CR16 :1; + __IO uint32_t CR17 :1; + __IO uint32_t CR18 :1; + __IO uint32_t CR19 :1; + __IO uint32_t CR20 :1; + __IO uint32_t CR21 :1; + __IO uint32_t CR22 :1; + __IO uint32_t CR23 :1; + __IO uint32_t CR24 :1; + __IO uint32_t CR25 :1; + __IO uint32_t CR26 :1; + __IO uint32_t CR27 :1; + __IO uint32_t CR28 :1; + __IO uint32_t CR29 :1; + __IO uint32_t CR30 :1; + __IO uint32_t CR31 :1; +} stc_canfd_txbcr_field_t; + +typedef struct stc_canfd_txbto_field +{ + __IO uint32_t TO0 :1; + __IO uint32_t TO1 :1; + __IO uint32_t TO2 :1; + __IO uint32_t TO3 :1; + __IO uint32_t TO4 :1; + __IO uint32_t TO5 :1; + __IO uint32_t TO6 :1; + __IO uint32_t TO7 :1; + __IO uint32_t TO8 :1; + __IO uint32_t TO9 :1; + __IO uint32_t TO10 :1; + __IO uint32_t TO11 :1; + __IO uint32_t TO12 :1; + __IO uint32_t TO13 :1; + __IO uint32_t TO14 :1; + __IO uint32_t TO15 :1; + __IO uint32_t TO16 :1; + __IO uint32_t TO17 :1; + __IO uint32_t TO18 :1; + __IO uint32_t TO19 :1; + __IO uint32_t TO20 :1; + __IO uint32_t TO21 :1; + __IO uint32_t TO22 :1; + __IO uint32_t TO23 :1; + __IO uint32_t TO24 :1; + __IO uint32_t TO25 :1; + __IO uint32_t TO26 :1; + __IO uint32_t TO27 :1; + __IO uint32_t TO28 :1; + __IO uint32_t TO29 :1; + __IO uint32_t TO30 :1; + __IO uint32_t TO31 :1; +} stc_canfd_txbto_field_t; + +typedef struct stc_canfd_txbcf_field +{ + __IO uint32_t CF0 :1; + __IO uint32_t CF1 :1; + __IO uint32_t CF2 :1; + __IO uint32_t CF3 :1; + __IO uint32_t CF4 :1; + __IO uint32_t CF5 :1; + __IO uint32_t CF6 :1; + __IO uint32_t CF7 :1; + __IO uint32_t CF8 :1; + __IO uint32_t CF9 :1; + __IO uint32_t CF10 :1; + __IO uint32_t CF11 :1; + __IO uint32_t CF12 :1; + __IO uint32_t CF13 :1; + __IO uint32_t CF14 :1; + __IO uint32_t CF15 :1; + __IO uint32_t CF16 :1; + __IO uint32_t CF17 :1; + __IO uint32_t CF18 :1; + __IO uint32_t CF19 :1; + __IO uint32_t CF20 :1; + __IO uint32_t CF21 :1; + __IO uint32_t CF22 :1; + __IO uint32_t CF23 :1; + __IO uint32_t CF24 :1; + __IO uint32_t CF25 :1; + __IO uint32_t CF26 :1; + __IO uint32_t CF27 :1; + __IO uint32_t CF28 :1; + __IO uint32_t CF29 :1; + __IO uint32_t CF30 :1; + __IO uint32_t CF31 :1; +} stc_canfd_txbcf_field_t; + +typedef struct stc_canfd_txbtie_field +{ + __IO uint32_t TIE0 :1; + __IO uint32_t TIE1 :1; + __IO uint32_t TIE2 :1; + __IO uint32_t TIE3 :1; + __IO uint32_t TIE4 :1; + __IO uint32_t TIE5 :1; + __IO uint32_t TIE6 :1; + __IO uint32_t TIE7 :1; + __IO uint32_t TIE8 :1; + __IO uint32_t TIE9 :1; + __IO uint32_t TIE10 :1; + __IO uint32_t TIE11 :1; + __IO uint32_t TIE12 :1; + __IO uint32_t TIE13 :1; + __IO uint32_t TIE14 :1; + __IO uint32_t TIE15 :1; + __IO uint32_t TIE16 :1; + __IO uint32_t TIE17 :1; + __IO uint32_t TIE18 :1; + __IO uint32_t TIE19 :1; + __IO uint32_t TIE20 :1; + __IO uint32_t TIE21 :1; + __IO uint32_t TIE22 :1; + __IO uint32_t TIE23 :1; + __IO uint32_t TIE24 :1; + __IO uint32_t TIE25 :1; + __IO uint32_t TIE26 :1; + __IO uint32_t TIE27 :1; + __IO uint32_t TIE28 :1; + __IO uint32_t TIE29 :1; + __IO uint32_t TIE30 :1; + __IO uint32_t TIE31 :1; +} stc_canfd_txbtie_field_t; + +typedef struct stc_canfd_txbcie_field +{ + __IO uint32_t CFIE0 :1; + __IO uint32_t CFIE1 :1; + __IO uint32_t CFIE2 :1; + __IO uint32_t CFIE3 :1; + __IO uint32_t CFIE4 :1; + __IO uint32_t CFIE5 :1; + __IO uint32_t CFIE6 :1; + __IO uint32_t CFIE7 :1; + __IO uint32_t CFIE8 :1; + __IO uint32_t CFIE9 :1; + __IO uint32_t CFIE10 :1; + __IO uint32_t CFIE11 :1; + __IO uint32_t CFIE12 :1; + __IO uint32_t CFIE13 :1; + __IO uint32_t CFIE14 :1; + __IO uint32_t CFIE15 :1; + __IO uint32_t CFIE16 :1; + __IO uint32_t CFIE17 :1; + __IO uint32_t CFIE18 :1; + __IO uint32_t CFIE19 :1; + __IO uint32_t CFIE20 :1; + __IO uint32_t CFIE21 :1; + __IO uint32_t CFIE22 :1; + __IO uint32_t CFIE23 :1; + __IO uint32_t CFIE24 :1; + __IO uint32_t CFIE25 :1; + __IO uint32_t CFIE26 :1; + __IO uint32_t CFIE27 :1; + __IO uint32_t CFIE28 :1; + __IO uint32_t CFIE29 :1; + __IO uint32_t CFIE30 :1; + __IO uint32_t CFIE31 :1; +} stc_canfd_txbcie_field_t; + +typedef struct stc_canfd_txefc_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t EFSA :14; + __IO uint32_t EFS :6; + __IO uint32_t RESERVED2 :2; + __IO uint32_t EFWM :6; + __IO uint32_t RESERVED4 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t EFSA0 :1; + __IO uint32_t EFSA1 :1; + __IO uint32_t EFSA2 :1; + __IO uint32_t EFSA3 :1; + __IO uint32_t EFSA4 :1; + __IO uint32_t EFSA5 :1; + __IO uint32_t EFSA6 :1; + __IO uint32_t EFSA7 :1; + __IO uint32_t EFSA8 :1; + __IO uint32_t EFSA9 :1; + __IO uint32_t EFSA10 :1; + __IO uint32_t EFSA11 :1; + __IO uint32_t EFSA12 :1; + __IO uint32_t EFSA13 :1; + __IO uint32_t EFS0 :1; + __IO uint32_t EFS1 :1; + __IO uint32_t EFS2 :1; + __IO uint32_t EFS3 :1; + __IO uint32_t EFS4 :1; + __IO uint32_t EFS5 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t EFWM0 :1; + __IO uint32_t EFWM1 :1; + __IO uint32_t EFWM2 :1; + __IO uint32_t EFWM3 :1; + __IO uint32_t EFWM4 :1; + __IO uint32_t EFWM5 :1; + __IO uint32_t RESERVED5 :2; + }; + }; +} stc_canfd_txefc_field_t; + +typedef struct stc_canfd_txfs_field +{ + union { + struct { + __IO uint32_t EFFL :6; + __IO uint32_t RESERVED0 :2; + __IO uint32_t EFGI :5; + __IO uint32_t RESERVED2 :3; + __IO uint32_t EFPI :5; + __IO uint32_t RESERVED4 :3; + __IO uint32_t EFF :1; + __IO uint32_t TEFL :1; + __IO uint32_t RESERVED5 :6; + }; + struct { + __IO uint32_t EFFL0 :1; + __IO uint32_t EFFL1 :1; + __IO uint32_t EFFL2 :1; + __IO uint32_t EFFL3 :1; + __IO uint32_t EFFL4 :1; + __IO uint32_t EFFL5 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t EFGI0 :1; + __IO uint32_t EFGI1 :1; + __IO uint32_t EFGI2 :1; + __IO uint32_t EFGI3 :1; + __IO uint32_t EFGI4 :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t EFPI0 :1; + __IO uint32_t EFPI1 :1; + __IO uint32_t EFPI2 :1; + __IO uint32_t EFPI3 :1; + __IO uint32_t EFPI4 :1; + __IO uint32_t RESERVED6 :11; + }; + }; +} stc_canfd_txfs_field_t; + +typedef struct stc_canfd_txfa_field +{ + union { + struct { + __IO uint32_t EFAI :5; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t EFAI0 :1; + __IO uint32_t EFAI1 :1; + __IO uint32_t EFAI2 :1; + __IO uint32_t EFAI3 :1; + __IO uint32_t EFAI4 :1; + __IO uint32_t RESERVED1 :27; + }; + }; +} stc_canfd_txfa_field_t; + +typedef struct stc_canfd_fdecr_field +{ + __IO uint8_t SEIE :1; + __IO uint8_t DEIE :1; + __IO uint8_t CEREN :1; + __IO uint8_t CEIV :1; + __IO uint8_t RESERVED0 :4; +} stc_canfd_fdecr_field_t; + +typedef struct stc_canfd_fdesr_field +{ + __IO uint8_t SEI :1; + __IO uint8_t DEI :1; + __IO uint8_t RESERVED0 :6; +} stc_canfd_fdesr_field_t; + +typedef struct stc_canfd_fdsear_field +{ + union { + struct { + __IO uint16_t SRA :16; + }; + struct { + __IO uint16_t SRA0 :1; + __IO uint16_t SRA1 :1; + __IO uint16_t SRA2 :1; + __IO uint16_t SRA3 :1; + __IO uint16_t SRA4 :1; + __IO uint16_t SRA5 :1; + __IO uint16_t SRA6 :1; + __IO uint16_t SRA7 :1; + __IO uint16_t SRA8 :1; + __IO uint16_t SRA9 :1; + __IO uint16_t SRA10 :1; + __IO uint16_t SRA11 :1; + __IO uint16_t SRA12 :1; + __IO uint16_t SRA13 :1; + __IO uint16_t SRA14 :1; + __IO uint16_t SRA15 :1; + }; + }; +} stc_canfd_fdsear_field_t; + +typedef struct stc_canfd_fdescr_field +{ + __IO uint8_t SEIC :1; + __IO uint8_t DEIC :1; + __IO uint8_t RESERVED0 :6; +} stc_canfd_fdescr_field_t; + +typedef struct stc_canfd_fddear_field +{ + union { + struct { + __IO uint16_t DRA :16; + }; + struct { + __IO uint16_t DRA0 :1; + __IO uint16_t DRA1 :1; + __IO uint16_t DRA2 :1; + __IO uint16_t DRA3 :1; + __IO uint16_t DRA4 :1; + __IO uint16_t DRA5 :1; + __IO uint16_t DRA6 :1; + __IO uint16_t DRA7 :1; + __IO uint16_t DRA8 :1; + __IO uint16_t DRA9 :1; + __IO uint16_t DRA10 :1; + __IO uint16_t DRA11 :1; + __IO uint16_t DRA12 :1; + __IO uint16_t DRA13 :1; + __IO uint16_t DRA14 :1; + __IO uint16_t DRA15 :1; + }; + }; +} stc_canfd_fddear_field_t; + +typedef struct stc_canfd_tscntr_field +{ + __IO uint16_t CCLR :1; + __IO uint16_t RESERVED0 :15; +} stc_canfd_tscntr_field_t; + +typedef struct stc_canfd_tsmdr_field +{ + __IO uint16_t CNTEN :1; + __IO uint16_t RESERVED0 :15; +} stc_canfd_tsmdr_field_t; + +typedef struct stc_canfd_tsdivr_field +{ + union { + struct { + __IO uint32_t CDIV :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t CDIV0 :1; + __IO uint32_t CDIV1 :1; + __IO uint32_t CDIV2 :1; + __IO uint32_t CDIV3 :1; + __IO uint32_t CDIV4 :1; + __IO uint32_t CDIV5 :1; + __IO uint32_t CDIV6 :1; + __IO uint32_t CDIV7 :1; + __IO uint32_t CDIV8 :1; + __IO uint32_t CDIV9 :1; + __IO uint32_t CDIV10 :1; + __IO uint32_t CDIV11 :1; + __IO uint32_t CDIV12 :1; + __IO uint32_t CDIV13 :1; + __IO uint32_t CDIV14 :1; + __IO uint32_t CDIV15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_canfd_tsdivr_field_t; + +typedef struct stc_canfd_tscdtr_field +{ + union { + struct { + __IO uint16_t CNT :16; + }; + struct { + __IO uint16_t CNT0 :1; + __IO uint16_t CNT1 :1; + __IO uint16_t CNT2 :1; + __IO uint16_t CNT3 :1; + __IO uint16_t CNT4 :1; + __IO uint16_t CNT5 :1; + __IO uint16_t CNT6 :1; + __IO uint16_t CNT7 :1; + __IO uint16_t CNT8 :1; + __IO uint16_t CNT9 :1; + __IO uint16_t CNT10 :1; + __IO uint16_t CNT11 :1; + __IO uint16_t CNT12 :1; + __IO uint16_t CNT13 :1; + __IO uint16_t CNT14 :1; + __IO uint16_t CNT15 :1; + }; + }; +} stc_canfd_tscdtr_field_t; + +typedef struct stc_canfd_tscpclr_field +{ + union { + struct { + __IO uint16_t CMP :16; + }; + struct { + __IO uint16_t CMP0 :1; + __IO uint16_t CMP1 :1; + __IO uint16_t CMP2 :1; + __IO uint16_t CMP3 :1; + __IO uint16_t CMP4 :1; + __IO uint16_t CMP5 :1; + __IO uint16_t CMP6 :1; + __IO uint16_t CMP7 :1; + __IO uint16_t CMP8 :1; + __IO uint16_t CMP9 :1; + __IO uint16_t CMP10 :1; + __IO uint16_t CMP11 :1; + __IO uint16_t CMP12 :1; + __IO uint16_t CMP13 :1; + __IO uint16_t CMP14 :1; + __IO uint16_t CMP15 :1; + }; + }; +} stc_canfd_tscpclr_field_t; + +/******************************************************************************* +* CANPRES_MODULE +*******************************************************************************/ +typedef struct stc_canpres_canpre_field +{ + union { + struct { + __IO uint8_t CANPRE :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t CANPRE0 :1; + __IO uint8_t CANPRE1 :1; + __IO uint8_t CANPRE2 :1; + __IO uint8_t CANPRE3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_canpres_canpre_field_t; + +/******************************************************************************* +* CLK_GATING_MODULE +*******************************************************************************/ +typedef struct stc_clk_gating_cken0_field +{ + __IO uint32_t MFSCK0 :1; + __IO uint32_t MFSCK1 :1; + __IO uint32_t MFSCK2 :1; + __IO uint32_t MFSCK3 :1; + __IO uint32_t MFSCK4 :1; + __IO uint32_t MFSCK5 :1; + __IO uint32_t MFSCK6 :1; + __IO uint32_t MFSCK7 :1; + __IO uint32_t MFSCK8 :1; + __IO uint32_t MFSCK9 :1; + __IO uint32_t MFSCK10 :1; + __IO uint32_t MFSCK11 :1; + __IO uint32_t MFSCK12 :1; + __IO uint32_t MFSCK13 :1; + __IO uint32_t MFSCK14 :1; + __IO uint32_t MFSCK15 :1; + __IO uint32_t ADCCK0 :1; + __IO uint32_t ADCCK1 :1; + __IO uint32_t ADCCK2 :1; + __IO uint32_t ADCCK3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t DMACK :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t EXBCK :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t GIOCK :1; + __IO uint32_t RESERVED3 :3; +} stc_clk_gating_cken0_field_t; + +typedef struct stc_clk_gating_mrst0_field +{ + __IO uint32_t MFSRST0 :1; + __IO uint32_t MFSRST1 :1; + __IO uint32_t MFSRST2 :1; + __IO uint32_t MFSRST3 :1; + __IO uint32_t MFSRST4 :1; + __IO uint32_t MFSRST5 :1; + __IO uint32_t MFSRST6 :1; + __IO uint32_t MFSRST7 :1; + __IO uint32_t MFSRST8 :1; + __IO uint32_t MFSRST9 :1; + __IO uint32_t MFSRST10 :1; + __IO uint32_t MFSRST11 :1; + __IO uint32_t MFSRST12 :1; + __IO uint32_t MFSRST13 :1; + __IO uint32_t MFSRST14 :1; + __IO uint32_t MFSRST15 :1; + __IO uint32_t ADCRST0 :1; + __IO uint32_t ADCRST1 :1; + __IO uint32_t ADCRST2 :1; + __IO uint32_t ADCRST3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t DMARST :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t EXBRST :1; + __IO uint32_t RESERVED2 :5; +} stc_clk_gating_mrst0_field_t; + +typedef struct stc_clk_gating_cken1_field +{ + __IO uint32_t BTMCK0 :1; + __IO uint32_t BTMCK1 :1; + __IO uint32_t BTMCK2 :1; + __IO uint32_t BTMCK3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t MFTCK0 :1; + __IO uint32_t MFTCK1 :1; + __IO uint32_t MFTCK2 :1; + __IO uint32_t MFTCK3 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t QDUCK0 :1; + __IO uint32_t QDUCK1 :1; + __IO uint32_t QDUCK2 :1; + __IO uint32_t QDUCK3 :1; + __IO uint32_t RESERVED2 :12; +} stc_clk_gating_cken1_field_t; + +typedef struct stc_clk_gating_mrst1_field +{ + __IO uint32_t BTMRST0 :1; + __IO uint32_t BTMRST1 :1; + __IO uint32_t BTMRST2 :1; + __IO uint32_t BTMRST3 :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t MFTRST0 :1; + __IO uint32_t MFTRST1 :1; + __IO uint32_t MFTRST2 :1; + __IO uint32_t MFTRST3 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t QDURST0 :1; + __IO uint32_t QDURST1 :1; + __IO uint32_t QDURST2 :1; + __IO uint32_t QDURST3 :1; + __IO uint32_t RESERVED2 :12; +} stc_clk_gating_mrst1_field_t; + +typedef struct stc_clk_gating_cken2_field +{ + __IO uint32_t USBCK0 :1; + __IO uint32_t USBCK1 :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t CANCK0 :1; + __IO uint32_t CANCK1 :1; + __IO uint32_t CANCK2 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SDCCK :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t I2SCK0 :1; + __IO uint32_t I2SCK1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t PCRCCK :1; + __IO uint32_t RESERVED4 :3; + __IO uint32_t CECCK0 :1; + __IO uint32_t CECCK1 :1; + __IO uint32_t RESERVED5 :2; + __IO uint32_t HSSPICK :1; + __IO uint32_t RESERVED6 :3; +} stc_clk_gating_cken2_field_t; + +typedef struct stc_clk_gating_mrst2_field +{ + __IO uint32_t USBRST0 :1; + __IO uint32_t USBRST1 :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t CANRST0 :1; + __IO uint32_t CANRST1 :1; + __IO uint32_t CANRST2 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SDCRST :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t I2SRST0 :1; + __IO uint32_t I2SRST1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t PCRCRST :1; + __IO uint32_t RESERVED4 :3; + __IO uint32_t CECRST0 :1; + __IO uint32_t CECRST1 :1; + __IO uint32_t RESERVED5 :2; + __IO uint32_t HSSPIRST :1; + __IO uint32_t RESERVED6 :3; +} stc_clk_gating_mrst2_field_t; + +/******************************************************************************* +* CRC_MODULE +*******************************************************************************/ +typedef struct stc_crc_crccr_field +{ + __IO uint8_t INIT :1; + __IO uint8_t CRC32 :1; + __IO uint8_t LTLEND :1; + __IO uint8_t LSBFST :1; + __IO uint8_t CRCLTE :1; + __IO uint8_t CRCLSF :1; + __IO uint8_t FXOR :1; + __IO uint8_t RESERVED0 :1; +} stc_crc_crccr_field_t; + +typedef struct stc_crc_crcinit_field +{ + union { + struct { + __IO uint32_t D :32; + }; + struct { + __IO uint32_t D0 :1; + __IO uint32_t D1 :1; + __IO uint32_t D2 :1; + __IO uint32_t D3 :1; + __IO uint32_t D4 :1; + __IO uint32_t D5 :1; + __IO uint32_t D6 :1; + __IO uint32_t D7 :1; + __IO uint32_t D8 :1; + __IO uint32_t D9 :1; + __IO uint32_t D10 :1; + __IO uint32_t D11 :1; + __IO uint32_t D12 :1; + __IO uint32_t D13 :1; + __IO uint32_t D14 :1; + __IO uint32_t D15 :1; + __IO uint32_t D16 :1; + __IO uint32_t D17 :1; + __IO uint32_t D18 :1; + __IO uint32_t D19 :1; + __IO uint32_t D20 :1; + __IO uint32_t D21 :1; + __IO uint32_t D22 :1; + __IO uint32_t D23 :1; + __IO uint32_t D24 :1; + __IO uint32_t D25 :1; + __IO uint32_t D26 :1; + __IO uint32_t D27 :1; + __IO uint32_t D28 :1; + __IO uint32_t D29 :1; + __IO uint32_t D30 :1; + __IO uint32_t D31 :1; + }; + }; +} stc_crc_crcinit_field_t; + +typedef struct stc_crc_crcin_field +{ + union { + struct { + __IO uint32_t D :32; + }; + struct { + __IO uint32_t D0 :1; + __IO uint32_t D1 :1; + __IO uint32_t D2 :1; + __IO uint32_t D3 :1; + __IO uint32_t D4 :1; + __IO uint32_t D5 :1; + __IO uint32_t D6 :1; + __IO uint32_t D7 :1; + __IO uint32_t D8 :1; + __IO uint32_t D9 :1; + __IO uint32_t D10 :1; + __IO uint32_t D11 :1; + __IO uint32_t D12 :1; + __IO uint32_t D13 :1; + __IO uint32_t D14 :1; + __IO uint32_t D15 :1; + __IO uint32_t D16 :1; + __IO uint32_t D17 :1; + __IO uint32_t D18 :1; + __IO uint32_t D19 :1; + __IO uint32_t D20 :1; + __IO uint32_t D21 :1; + __IO uint32_t D22 :1; + __IO uint32_t D23 :1; + __IO uint32_t D24 :1; + __IO uint32_t D25 :1; + __IO uint32_t D26 :1; + __IO uint32_t D27 :1; + __IO uint32_t D28 :1; + __IO uint32_t D29 :1; + __IO uint32_t D30 :1; + __IO uint32_t D31 :1; + }; + }; +} stc_crc_crcin_field_t; + +typedef struct stc_crc_crcr_field +{ + union { + struct { + __IO uint32_t D :32; + }; + struct { + __IO uint32_t D0 :1; + __IO uint32_t D1 :1; + __IO uint32_t D2 :1; + __IO uint32_t D3 :1; + __IO uint32_t D4 :1; + __IO uint32_t D5 :1; + __IO uint32_t D6 :1; + __IO uint32_t D7 :1; + __IO uint32_t D8 :1; + __IO uint32_t D9 :1; + __IO uint32_t D10 :1; + __IO uint32_t D11 :1; + __IO uint32_t D12 :1; + __IO uint32_t D13 :1; + __IO uint32_t D14 :1; + __IO uint32_t D15 :1; + __IO uint32_t D16 :1; + __IO uint32_t D17 :1; + __IO uint32_t D18 :1; + __IO uint32_t D19 :1; + __IO uint32_t D20 :1; + __IO uint32_t D21 :1; + __IO uint32_t D22 :1; + __IO uint32_t D23 :1; + __IO uint32_t D24 :1; + __IO uint32_t D25 :1; + __IO uint32_t D26 :1; + __IO uint32_t D27 :1; + __IO uint32_t D28 :1; + __IO uint32_t D29 :1; + __IO uint32_t D30 :1; + __IO uint32_t D31 :1; + }; + }; +} stc_crc_crcr_field_t; + +/******************************************************************************* +* CRG_MODULE +*******************************************************************************/ +typedef struct stc_crg_scm_ctl_field +{ + union { + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t MOSCE :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SOSCE :1; + __IO uint32_t PLLE :1; + __IO uint32_t RCS :3; + __IO uint32_t RESERVED3 :24; + }; + struct { + __IO uint32_t RESERVED2 :5; + __IO uint32_t RCS0 :1; + __IO uint32_t RCS1 :1; + __IO uint32_t RCS2 :1; + __IO uint32_t RESERVED4 :24; + }; + }; +} stc_crg_scm_ctl_field_t; + +typedef struct stc_crg_scm_str_field +{ + union { + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t MORDY :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t SORDY :1; + __IO uint32_t PLRDY :1; + __IO uint32_t RCM :3; + __IO uint32_t RESERVED3 :24; + }; + struct { + __IO uint32_t RESERVED2 :5; + __IO uint32_t RCM0 :1; + __IO uint32_t RCM1 :1; + __IO uint32_t RCM2 :1; + __IO uint32_t RESERVED4 :24; + }; + }; +} stc_crg_scm_str_field_t; + +typedef struct stc_crg_stb_ctl_field +{ + union { + struct { + __IO uint32_t STM :2; + __IO uint32_t DSTM :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t SPL :1; + __IO uint32_t RESERVED1 :11; + __IO uint32_t KEY :16; + }; + struct { + __IO uint32_t STM0 :1; + __IO uint32_t STM1 :1; + __IO uint32_t RESERVED2 :14; + __IO uint32_t KEY0 :1; + __IO uint32_t KEY1 :1; + __IO uint32_t KEY2 :1; + __IO uint32_t KEY3 :1; + __IO uint32_t KEY4 :1; + __IO uint32_t KEY5 :1; + __IO uint32_t KEY6 :1; + __IO uint32_t KEY7 :1; + __IO uint32_t KEY8 :1; + __IO uint32_t KEY9 :1; + __IO uint32_t KEY10 :1; + __IO uint32_t KEY11 :1; + __IO uint32_t KEY12 :1; + __IO uint32_t KEY13 :1; + __IO uint32_t KEY14 :1; + __IO uint32_t KEY15 :1; + }; + }; +} stc_crg_stb_ctl_field_t; + +typedef struct stc_crg_rst_str_field +{ + __IO uint32_t PONR :1; + __IO uint32_t INITX :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t SWDT :1; + __IO uint32_t HWDT :1; + __IO uint32_t CSVR :1; + __IO uint32_t FCSR :1; + __IO uint32_t SRST :1; + __IO uint32_t RESERVED1 :23; +} stc_crg_rst_str_field_t; + +typedef struct stc_crg_bsc_psr_field +{ + union { + struct { + __IO uint32_t BSR :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t BSR0 :1; + __IO uint32_t BSR1 :1; + __IO uint32_t BSR2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_crg_bsc_psr_field_t; + +typedef struct stc_crg_apbc0_psr_field +{ + union { + struct { + __IO uint32_t APBC0 :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t APBC00 :1; + __IO uint32_t APBC01 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_crg_apbc0_psr_field_t; + +typedef struct stc_crg_apbc1_psr_field +{ + union { + struct { + __IO uint32_t APBC1 :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t APBC1RST :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t APBC1EN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t APBC10 :1; + __IO uint32_t APBC11 :1; + __IO uint32_t RESERVED3 :30; + }; + }; +} stc_crg_apbc1_psr_field_t; + +typedef struct stc_crg_apbc2_psr_field +{ + union { + struct { + __IO uint32_t APBC2 :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t APBC2RST :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t APBC2EN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t APBC20 :1; + __IO uint32_t APBC21 :1; + __IO uint32_t RESERVED3 :30; + }; + }; +} stc_crg_apbc2_psr_field_t; + +typedef struct stc_crg_swc_psr_field +{ + union { + struct { + __IO uint32_t SWDS :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t SWDS0 :1; + __IO uint32_t SWDS1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_crg_swc_psr_field_t; + +typedef struct stc_crg_ttc_psr_field +{ + union { + struct { + __IO uint32_t TTC :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t TTC0 :1; + __IO uint32_t TTC1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_crg_ttc_psr_field_t; + +typedef struct stc_crg_csw_tmr_field +{ + union { + struct { + __IO uint32_t MOWT :4; + __IO uint32_t SOWT :4; + __IO uint32_t RESERVED0 :24; + }; + struct { + __IO uint32_t MOWT0 :1; + __IO uint32_t MOWT1 :1; + __IO uint32_t MOWT2 :1; + __IO uint32_t MOWT3 :1; + __IO uint32_t SOWT0 :1; + __IO uint32_t SOWT1 :1; + __IO uint32_t SOWT2 :1; + __IO uint32_t SOWT3 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_crg_csw_tmr_field_t; + +typedef struct stc_crg_psw_tmr_field +{ + union { + struct { + __IO uint32_t POWT :3; + __IO uint32_t RESERVED0 :1; + __IO uint32_t PINC :1; + __IO uint32_t RESERVED1 :27; + }; + struct { + __IO uint32_t POWT0 :1; + __IO uint32_t POWT1 :1; + __IO uint32_t POWT2 :1; + __IO uint32_t RESERVED2 :29; + }; + }; +} stc_crg_psw_tmr_field_t; + +typedef struct stc_crg_pll_ctl1_field +{ + union { + struct { + __IO uint32_t PLLM :4; + __IO uint32_t PLLK :4; + __IO uint32_t RESERVED0 :24; + }; + struct { + __IO uint32_t PLLM0 :1; + __IO uint32_t PLLM1 :1; + __IO uint32_t PLLM2 :1; + __IO uint32_t PLLM3 :1; + __IO uint32_t PLLK0 :1; + __IO uint32_t PLLK1 :1; + __IO uint32_t PLLK2 :1; + __IO uint32_t PLLK3 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_crg_pll_ctl1_field_t; + +typedef struct stc_crg_pll_ctl2_field +{ + union { + struct { + __IO uint32_t PLLN :6; + __IO uint32_t RESERVED0 :26; + }; + struct { + __IO uint32_t PLLN0 :1; + __IO uint32_t PLLN1 :1; + __IO uint32_t PLLN2 :1; + __IO uint32_t PLLN3 :1; + __IO uint32_t PLLN4 :1; + __IO uint32_t PLLN5 :1; + __IO uint32_t RESERVED1 :26; + }; + }; +} stc_crg_pll_ctl2_field_t; + +typedef struct stc_crg_csv_ctl_field +{ + union { + struct { + __IO uint32_t MCSVE :1; + __IO uint32_t SCSVE :1; + __IO uint32_t RESERVED0 :6; + __IO uint32_t FCSDE :1; + __IO uint32_t FCSRE :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t FCD :3; + __IO uint32_t RESERVED3 :17; + }; + struct { + __IO uint32_t RESERVED2 :12; + __IO uint32_t FCD0 :1; + __IO uint32_t FCD1 :1; + __IO uint32_t FCD2 :1; + __IO uint32_t RESERVED4 :17; + }; + }; +} stc_crg_csv_ctl_field_t; + +typedef struct stc_crg_csv_str_field +{ + __IO uint32_t MCMF :1; + __IO uint32_t SCMF :1; + __IO uint32_t RESERVED0 :30; +} stc_crg_csv_str_field_t; + +typedef struct stc_crg_fcswh_ctl_field +{ + union { + struct { + __IO uint32_t FWH :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t FWH0 :1; + __IO uint32_t FWH1 :1; + __IO uint32_t FWH2 :1; + __IO uint32_t FWH3 :1; + __IO uint32_t FWH4 :1; + __IO uint32_t FWH5 :1; + __IO uint32_t FWH6 :1; + __IO uint32_t FWH7 :1; + __IO uint32_t FWH8 :1; + __IO uint32_t FWH9 :1; + __IO uint32_t FWH10 :1; + __IO uint32_t FWH11 :1; + __IO uint32_t FWH12 :1; + __IO uint32_t FWH13 :1; + __IO uint32_t FWH14 :1; + __IO uint32_t FWH15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_crg_fcswh_ctl_field_t; + +typedef struct stc_crg_fcswl_ctl_field +{ + union { + struct { + __IO uint32_t FWL :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t FWL0 :1; + __IO uint32_t FWL1 :1; + __IO uint32_t FWL2 :1; + __IO uint32_t FWL3 :1; + __IO uint32_t FWL4 :1; + __IO uint32_t FWL5 :1; + __IO uint32_t FWL6 :1; + __IO uint32_t FWL7 :1; + __IO uint32_t FWL8 :1; + __IO uint32_t FWL9 :1; + __IO uint32_t FWL10 :1; + __IO uint32_t FWL11 :1; + __IO uint32_t FWL12 :1; + __IO uint32_t FWL13 :1; + __IO uint32_t FWL14 :1; + __IO uint32_t FWL15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_crg_fcswl_ctl_field_t; + +typedef struct stc_crg_fcswd_ctl_field +{ + union { + struct { + __IO uint32_t FWD :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t FWD0 :1; + __IO uint32_t FWD1 :1; + __IO uint32_t FWD2 :1; + __IO uint32_t FWD3 :1; + __IO uint32_t FWD4 :1; + __IO uint32_t FWD5 :1; + __IO uint32_t FWD6 :1; + __IO uint32_t FWD7 :1; + __IO uint32_t FWD8 :1; + __IO uint32_t FWD9 :1; + __IO uint32_t FWD10 :1; + __IO uint32_t FWD11 :1; + __IO uint32_t FWD12 :1; + __IO uint32_t FWD13 :1; + __IO uint32_t FWD14 :1; + __IO uint32_t FWD15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_crg_fcswd_ctl_field_t; + +typedef struct stc_crg_dbwdt_ctl_field +{ + __IO uint32_t RESERVED0 :5; + __IO uint32_t DPSWBE :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t DPHWBE :1; + __IO uint32_t RESERVED2 :24; +} stc_crg_dbwdt_ctl_field_t; + +typedef struct stc_crg_int_enr_field +{ + __IO uint32_t MCSE :1; + __IO uint32_t SCSE :1; + __IO uint32_t PCSE :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FCSE :1; + __IO uint32_t RESERVED1 :26; +} stc_crg_int_enr_field_t; + +typedef struct stc_crg_int_str_field +{ + __IO uint32_t MCSI :1; + __IO uint32_t SCSI :1; + __IO uint32_t PCSI :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FCSI :1; + __IO uint32_t RESERVED1 :26; +} stc_crg_int_str_field_t; + +typedef struct stc_crg_int_clr_field +{ + __IO uint32_t MCSC :1; + __IO uint32_t SCSC :1; + __IO uint32_t PCSC :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t FCSC :1; + __IO uint32_t RESERVED1 :26; +} stc_crg_int_clr_field_t; + +typedef struct stc_crg_pllcg_ctl_field +{ + union { + struct { + __IO uint32_t PLLCGEN :1; + __IO uint32_t PLLCGSTR :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t PLLCGSTS :2; + __IO uint32_t PLLCGSSN :6; + __IO uint32_t PLLCGSTP :2; + __IO uint32_t PLLCGLP :8; + __IO uint32_t RESERVED2 :8; + }; + struct { + __IO uint32_t RESERVED1 :6; + __IO uint32_t PLLCGSTS0 :1; + __IO uint32_t PLLCGSTS1 :1; + __IO uint32_t PLLCGSSN0 :1; + __IO uint32_t PLLCGSSN1 :1; + __IO uint32_t PLLCGSSN2 :1; + __IO uint32_t PLLCGSSN3 :1; + __IO uint32_t PLLCGSSN4 :1; + __IO uint32_t PLLCGSSN5 :1; + __IO uint32_t PLLCGSTP0 :1; + __IO uint32_t PLLCGSTP1 :1; + __IO uint32_t PLLCGLP0 :1; + __IO uint32_t PLLCGLP1 :1; + __IO uint32_t PLLCGLP2 :1; + __IO uint32_t PLLCGLP3 :1; + __IO uint32_t PLLCGLP4 :1; + __IO uint32_t PLLCGLP5 :1; + __IO uint32_t PLLCGLP6 :1; + __IO uint32_t PLLCGLP7 :1; + __IO uint32_t RESERVED3 :8; + }; + }; +} stc_crg_pllcg_ctl_field_t; + +/******************************************************************************* +* CRTRIM_MODULE +*******************************************************************************/ +typedef struct stc_crtrim_mcr_psr_field +{ + union { + struct { + __IO uint8_t CSR :3; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t CSR0 :1; + __IO uint8_t CSR1 :1; + __IO uint8_t CSR2 :1; + __IO uint8_t RESERVED1 :5; + }; + }; +} stc_crtrim_mcr_psr_field_t; + +typedef struct stc_crtrim_mcr_ftrm_field +{ + union { + struct { + __IO uint32_t TRD :10; + __IO uint32_t RESERVED0 :22; + }; + struct { + __IO uint32_t TRD0 :1; + __IO uint32_t TRD1 :1; + __IO uint32_t TRD2 :1; + __IO uint32_t TRD3 :1; + __IO uint32_t TRD4 :1; + __IO uint32_t TRD5 :1; + __IO uint32_t TRD6 :1; + __IO uint32_t TRD7 :1; + __IO uint32_t TRD8 :1; + __IO uint32_t TRD9 :1; + __IO uint32_t RESERVED1 :22; + }; + }; +} stc_crtrim_mcr_ftrm_field_t; + +typedef struct stc_crtrim_mcr_ttrm_field +{ + union { + struct { + __IO uint32_t TRT :5; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t TRT0 :1; + __IO uint32_t TRT1 :1; + __IO uint32_t TRT2 :1; + __IO uint32_t TRT3 :1; + __IO uint32_t TRT4 :1; + __IO uint32_t RESERVED1 :27; + }; + }; +} stc_crtrim_mcr_ttrm_field_t; + +typedef struct stc_crtrim_mcr_rlr_field +{ + union { + struct { + __IO uint32_t TRMLCK :32; + }; + struct { + __IO uint32_t TRMLCK0 :1; + __IO uint32_t TRMLCK1 :1; + __IO uint32_t TRMLCK2 :1; + __IO uint32_t TRMLCK3 :1; + __IO uint32_t TRMLCK4 :1; + __IO uint32_t TRMLCK5 :1; + __IO uint32_t TRMLCK6 :1; + __IO uint32_t TRMLCK7 :1; + __IO uint32_t TRMLCK8 :1; + __IO uint32_t TRMLCK9 :1; + __IO uint32_t TRMLCK10 :1; + __IO uint32_t TRMLCK11 :1; + __IO uint32_t TRMLCK12 :1; + __IO uint32_t TRMLCK13 :1; + __IO uint32_t TRMLCK14 :1; + __IO uint32_t TRMLCK15 :1; + __IO uint32_t TRMLCK16 :1; + __IO uint32_t TRMLCK17 :1; + __IO uint32_t TRMLCK18 :1; + __IO uint32_t TRMLCK19 :1; + __IO uint32_t TRMLCK20 :1; + __IO uint32_t TRMLCK21 :1; + __IO uint32_t TRMLCK22 :1; + __IO uint32_t TRMLCK23 :1; + __IO uint32_t TRMLCK24 :1; + __IO uint32_t TRMLCK25 :1; + __IO uint32_t TRMLCK26 :1; + __IO uint32_t TRMLCK27 :1; + __IO uint32_t TRMLCK28 :1; + __IO uint32_t TRMLCK29 :1; + __IO uint32_t TRMLCK30 :1; + __IO uint32_t TRMLCK31 :1; + }; + }; +} stc_crtrim_mcr_rlr_field_t; + +/******************************************************************************* +* DAC_MODULE +*******************************************************************************/ +typedef struct stc_dac_dacr_field +{ + __IO uint8_t DAE :1; + __IO uint8_t DRDY :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DAC10 :1; + __IO uint8_t DDAS :1; + __IO uint8_t RESERVED1 :2; +} stc_dac_dacr_field_t; + +typedef struct stc_dac_dadr_field +{ + union { + struct { + __IO uint16_t DA :12; + __IO uint16_t RESERVED0 :4; + }; + struct { + __IO uint16_t DA0 :1; + __IO uint16_t DA1 :1; + __IO uint16_t DA2 :1; + __IO uint16_t DA3 :1; + __IO uint16_t DA4 :1; + __IO uint16_t DA5 :1; + __IO uint16_t DA6 :1; + __IO uint16_t DA7 :1; + __IO uint16_t DA8 :1; + __IO uint16_t DA9 :1; + __IO uint16_t DA10 :1; + __IO uint16_t DA11 :1; + __IO uint16_t RESERVED1 :4; + }; + }; +} stc_dac_dadr_field_t; + +/******************************************************************************* +* DMAC_MODULE +*******************************************************************************/ +typedef struct stc_dmac_dmacr_field +{ + union { + struct { + __IO uint32_t RESERVED0 :24; + __IO uint32_t DH :4; + __IO uint32_t PR :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t DS :1; + __IO uint32_t DE :1; + }; + struct { + __IO uint32_t RESERVED1 :24; + __IO uint32_t DH0 :1; + __IO uint32_t DH1 :1; + __IO uint32_t DH2 :1; + __IO uint32_t DH3 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_dmac_dmacr_field_t; + +typedef struct stc_dmac_dmaca0_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca0_field_t; + +typedef struct stc_dmac_dmacb0_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb0_field_t; + +typedef struct stc_dmac_dmaca1_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca1_field_t; + +typedef struct stc_dmac_dmacb1_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb1_field_t; + +typedef struct stc_dmac_dmaca2_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca2_field_t; + +typedef struct stc_dmac_dmacb2_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb2_field_t; + +typedef struct stc_dmac_dmaca3_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca3_field_t; + +typedef struct stc_dmac_dmacb3_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb3_field_t; + +typedef struct stc_dmac_dmaca4_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca4_field_t; + +typedef struct stc_dmac_dmacb4_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb4_field_t; + +typedef struct stc_dmac_dmaca5_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca5_field_t; + +typedef struct stc_dmac_dmacb5_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb5_field_t; + +typedef struct stc_dmac_dmaca6_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca6_field_t; + +typedef struct stc_dmac_dmacb6_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb6_field_t; + +typedef struct stc_dmac_dmaca7_field +{ + union { + struct { + __IO uint32_t TC :16; + __IO uint32_t BC :4; + __IO uint32_t RESERVED0 :3; + __IO uint32_t IS :6; + __IO uint32_t ST :1; + __IO uint32_t PB :1; + __IO uint32_t EB :1; + }; + struct { + __IO uint32_t TC0 :1; + __IO uint32_t TC1 :1; + __IO uint32_t TC2 :1; + __IO uint32_t TC3 :1; + __IO uint32_t TC4 :1; + __IO uint32_t TC5 :1; + __IO uint32_t TC6 :1; + __IO uint32_t TC7 :1; + __IO uint32_t TC8 :1; + __IO uint32_t TC9 :1; + __IO uint32_t TC10 :1; + __IO uint32_t TC11 :1; + __IO uint32_t TC12 :1; + __IO uint32_t TC13 :1; + __IO uint32_t TC14 :1; + __IO uint32_t TC15 :1; + __IO uint32_t BC0 :1; + __IO uint32_t BC1 :1; + __IO uint32_t BC2 :1; + __IO uint32_t BC3 :1; + __IO uint32_t RESERVED1 :3; + __IO uint32_t IS0 :1; + __IO uint32_t IS1 :1; + __IO uint32_t IS2 :1; + __IO uint32_t IS3 :1; + __IO uint32_t IS4 :1; + __IO uint32_t IS5 :1; + __IO uint32_t RESERVED2 :3; + }; + }; +} stc_dmac_dmaca7_field_t; + +typedef struct stc_dmac_dmacb7_field +{ + union { + struct { + __IO uint32_t EM :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t SS :3; + __IO uint32_t CI :1; + __IO uint32_t EI :1; + __IO uint32_t RD :1; + __IO uint32_t RS :1; + __IO uint32_t RC :1; + __IO uint32_t FD :1; + __IO uint32_t FS :1; + __IO uint32_t TW :2; + __IO uint32_t MS :2; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t SS0 :1; + __IO uint32_t SS1 :1; + __IO uint32_t SS2 :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TW0 :1; + __IO uint32_t TW1 :1; + __IO uint32_t MS0 :1; + __IO uint32_t MS1 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dmac_dmacb7_field_t; + +/******************************************************************************* +* DS_MODULE +*******************************************************************************/ +typedef struct stc_ds_rck_ctl_field +{ + __IO uint8_t RTCCKE :1; + __IO uint8_t CECCKE :1; + __IO uint8_t RESERVED0 :6; +} stc_ds_rck_ctl_field_t; + +typedef struct stc_ds_pmd_ctl_field +{ + __IO uint8_t RTCE :1; + __IO uint8_t RESERVED0 :7; +} stc_ds_pmd_ctl_field_t; + +typedef struct stc_ds_wrfsr_field +{ + __IO uint8_t WINITX :1; + __IO uint8_t WLVDH :1; + __IO uint8_t RESERVED0 :6; +} stc_ds_wrfsr_field_t; + +typedef struct stc_ds_wifsr_field +{ + __IO uint16_t WRTCI :1; + __IO uint16_t WLVDI :1; + __IO uint16_t WUI0 :1; + __IO uint16_t WUI1 :1; + __IO uint16_t WUI2 :1; + __IO uint16_t WUI3 :1; + __IO uint16_t WUI4 :1; + __IO uint16_t WUI5 :1; + __IO uint16_t RESERVED0 :8; +} stc_ds_wifsr_field_t; + +typedef struct stc_ds_wier_field +{ + __IO uint16_t WRTCE :1; + __IO uint16_t WLVDE :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t WUI1E :1; + __IO uint16_t WUI2E :1; + __IO uint16_t WUI3E :1; + __IO uint16_t WUI4E :1; + __IO uint16_t WUI5E :1; + __IO uint16_t RESERVED1 :8; +} stc_ds_wier_field_t; + +typedef struct stc_ds_wilvr_field +{ + __IO uint8_t WUI1LV :1; + __IO uint8_t WUI2LV :1; + __IO uint8_t WUI3LV :1; + __IO uint8_t WUI4LV :1; + __IO uint8_t WUI5LV :1; + __IO uint8_t RESERVED0 :3; +} stc_ds_wilvr_field_t; + +typedef struct stc_ds_dsramr_field +{ + union { + struct { + __IO uint8_t SRAMR :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t SRAMR0 :1; + __IO uint8_t SRAMR1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_ds_dsramr_field_t; + +/******************************************************************************* +* DSTC_MODULE +*******************************************************************************/ +typedef struct stc_dstc_hwdesp_field +{ + union { + struct { + __IO uint32_t CHANNEL :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t HWDESP :14; + __IO uint32_t RESERVED2 :2; + }; + struct { + __IO uint32_t CHANNEL0 :1; + __IO uint32_t CHANNEL1 :1; + __IO uint32_t CHANNEL2 :1; + __IO uint32_t CHANNEL3 :1; + __IO uint32_t CHANNEL4 :1; + __IO uint32_t CHANNEL5 :1; + __IO uint32_t CHANNEL6 :1; + __IO uint32_t CHANNEL7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t HWDESP0 :1; + __IO uint32_t HWDESP1 :1; + __IO uint32_t HWDESP2 :1; + __IO uint32_t HWDESP3 :1; + __IO uint32_t HWDESP4 :1; + __IO uint32_t HWDESP5 :1; + __IO uint32_t HWDESP6 :1; + __IO uint32_t HWDESP7 :1; + __IO uint32_t HWDESP8 :1; + __IO uint32_t HWDESP9 :1; + __IO uint32_t HWDESP10 :1; + __IO uint32_t HWDESP11 :1; + __IO uint32_t HWDESP12 :1; + __IO uint32_t HWDESP13 :1; + __IO uint32_t RESERVED3 :2; + }; + }; +} stc_dstc_hwdesp_field_t; + +typedef struct stc_dstc_cfg_field +{ + union { + struct { + __IO uint8_t SWINTE :1; + __IO uint8_t ERINTE :1; + __IO uint8_t RBDIS :1; + __IO uint8_t ESTE :1; + __IO uint8_t SWPR :3; + __IO uint8_t RESERVED1 :1; + }; + struct { + __IO uint8_t RESERVED0 :4; + __IO uint8_t SWPR0 :1; + __IO uint8_t SWPR1 :1; + __IO uint8_t SWPR2 :1; + __IO uint8_t RESERVED2 :1; + }; + }; +} stc_dstc_cfg_field_t; + +typedef struct stc_dstc_swtr_field +{ + union { + struct { + __IO uint16_t SWDESP :14; + __IO uint16_t SWREQ :1; + __IO uint16_t SWST :1; + }; + struct { + __IO uint16_t SWDESP0 :1; + __IO uint16_t SWDESP1 :1; + __IO uint16_t SWDESP2 :1; + __IO uint16_t SWDESP3 :1; + __IO uint16_t SWDESP4 :1; + __IO uint16_t SWDESP5 :1; + __IO uint16_t SWDESP6 :1; + __IO uint16_t SWDESP7 :1; + __IO uint16_t SWDESP8 :1; + __IO uint16_t SWDESP9 :1; + __IO uint16_t SWDESP10 :1; + __IO uint16_t SWDESP11 :1; + __IO uint16_t SWDESP12 :1; + __IO uint16_t SWDESP13 :1; + __IO uint16_t RESERVED0 :2; + }; + }; +} stc_dstc_swtr_field_t; + +typedef struct stc_dstc_moners_field +{ + union { + struct { + __IO uint32_t EST :3; + __IO uint32_t DER :1; + __IO uint32_t ESTOP :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t EHS :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t ECH :8; + __IO uint32_t EDESP :14; + __IO uint32_t RESERVED3 :2; + }; + struct { + __IO uint32_t EST0 :1; + __IO uint32_t EST1 :1; + __IO uint32_t EST2 :1; + __IO uint32_t RESERVED2 :5; + __IO uint32_t ECH0 :1; + __IO uint32_t ECH1 :1; + __IO uint32_t ECH2 :1; + __IO uint32_t ECH3 :1; + __IO uint32_t ECH4 :1; + __IO uint32_t ECH5 :1; + __IO uint32_t ECH6 :1; + __IO uint32_t ECH7 :1; + __IO uint32_t EDESP0 :1; + __IO uint32_t EDESP1 :1; + __IO uint32_t EDESP2 :1; + __IO uint32_t EDESP3 :1; + __IO uint32_t EDESP4 :1; + __IO uint32_t EDESP5 :1; + __IO uint32_t EDESP6 :1; + __IO uint32_t EDESP7 :1; + __IO uint32_t EDESP8 :1; + __IO uint32_t EDESP9 :1; + __IO uint32_t EDESP10 :1; + __IO uint32_t EDESP11 :1; + __IO uint32_t EDESP12 :1; + __IO uint32_t EDESP13 :1; + __IO uint32_t RESERVED4 :2; + }; + }; +} stc_dstc_moners_field_t; + +/******************************************************************************* +* DT_MODULE +*******************************************************************************/ +typedef struct stc_dt_timer1control_field +{ + union { + struct { + __IO uint32_t ONESHOT :1; + __IO uint32_t TIMERSIZE :1; + __IO uint32_t TIMERPRE :2; + __IO uint32_t RESERVED1 :1; + __IO uint32_t INTENABLE :1; + __IO uint32_t TIMERMODE :1; + __IO uint32_t TIMEREN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIMERPRE0 :1; + __IO uint32_t TIMERPRE1 :1; + __IO uint32_t RESERVED3 :28; + }; + }; +} stc_dt_timer1control_field_t; + +typedef struct stc_dt_timer1ris_field +{ + __IO uint32_t TIMER1RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer1ris_field_t; + +typedef struct stc_dt_timer1mis_field +{ + __IO uint32_t TIMER1MIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer1mis_field_t; + +typedef struct stc_dt_timer2control_field +{ + union { + struct { + __IO uint32_t ONESHOT :1; + __IO uint32_t TIMERSIZE :1; + __IO uint32_t TIMERPRE :2; + __IO uint32_t RESERVED1 :1; + __IO uint32_t INTENABLE :1; + __IO uint32_t TIMERMODE :1; + __IO uint32_t TIMEREN :1; + __IO uint32_t RESERVED2 :24; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIMERPRE0 :1; + __IO uint32_t TIMERPRE1 :1; + __IO uint32_t RESERVED3 :28; + }; + }; +} stc_dt_timer2control_field_t; + +typedef struct stc_dt_timer2ris_field +{ + __IO uint32_t TIMER2RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer2ris_field_t; + +typedef struct stc_dt_timer2mis_field +{ + __IO uint32_t TIMER2MIS :1; + __IO uint32_t RESERVED0 :31; +} stc_dt_timer2mis_field_t; + +/******************************************************************************* +* DUALFLASH_IF_MODULE +*******************************************************************************/ +typedef struct stc_dualflash_if_dfaszr_field +{ + union { + struct { + __IO uint32_t DASZ :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t DASZ0 :1; + __IO uint32_t DASZ1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_dualflash_if_dfaszr_field_t; + +typedef struct stc_dualflash_if_dfrwtr_field +{ + union { + struct { + __IO uint32_t DRWT :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t DRWT0 :1; + __IO uint32_t DRWT1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_dualflash_if_dfrwtr_field_t; + +typedef struct stc_dualflash_if_dfstr_field +{ + __IO uint32_t DFRDY :1; + __IO uint32_t DFHNG :1; + __IO uint32_t DFERR :1; + __IO uint32_t RESERVED0 :29; +} stc_dualflash_if_dfstr_field_t; + +/******************************************************************************* +* ECC_CAPTURE_MODULE +*******************************************************************************/ +typedef struct stc_ecc_capture_ferrad_field +{ + union { + struct { + __IO uint32_t ERRAD :23; + __IO uint32_t RESERVED0 :9; + }; + struct { + __IO uint32_t ERRAD0 :1; + __IO uint32_t ERRAD1 :1; + __IO uint32_t ERRAD2 :1; + __IO uint32_t ERRAD3 :1; + __IO uint32_t ERRAD4 :1; + __IO uint32_t ERRAD5 :1; + __IO uint32_t ERRAD6 :1; + __IO uint32_t ERRAD7 :1; + __IO uint32_t ERRAD8 :1; + __IO uint32_t ERRAD9 :1; + __IO uint32_t ERRAD10 :1; + __IO uint32_t ERRAD11 :1; + __IO uint32_t ERRAD12 :1; + __IO uint32_t ERRAD13 :1; + __IO uint32_t ERRAD14 :1; + __IO uint32_t ERRAD15 :1; + __IO uint32_t ERRAD16 :1; + __IO uint32_t ERRAD17 :1; + __IO uint32_t ERRAD18 :1; + __IO uint32_t ERRAD19 :1; + __IO uint32_t ERRAD20 :1; + __IO uint32_t ERRAD21 :1; + __IO uint32_t ERRAD22 :1; + __IO uint32_t RESERVED1 :9; + }; + }; +} stc_ecc_capture_ferrad_field_t; + +/******************************************************************************* +* EXBUS_MODULE +*******************************************************************************/ +typedef struct stc_exbus_mode0_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode0_field_t; + +typedef struct stc_exbus_mode1_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode1_field_t; + +typedef struct stc_exbus_mode2_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode2_field_t; + +typedef struct stc_exbus_mode3_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode3_field_t; + +typedef struct stc_exbus_mode4_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode4_field_t; + +typedef struct stc_exbus_mode5_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode5_field_t; + +typedef struct stc_exbus_mode6_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode6_field_t; + +typedef struct stc_exbus_mode7_field +{ + union { + struct { + __IO uint32_t WDTH :2; + __IO uint32_t RBMON :1; + __IO uint32_t WEOFF :1; + __IO uint32_t NAND :1; + __IO uint32_t PAGE :1; + __IO uint32_t RDY :1; + __IO uint32_t SHRTDOUT :1; + __IO uint32_t MPXMODE :1; + __IO uint32_t ALEINV :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t MPXDOFF :1; + __IO uint32_t MPXCSOF :1; + __IO uint32_t MOEXEUP :1; + __IO uint32_t RESERVED1 :18; + }; + struct { + __IO uint32_t WDTH0 :1; + __IO uint32_t WDTH1 :1; + __IO uint32_t RESERVED2 :30; + }; + }; +} stc_exbus_mode7_field_t; + +typedef struct stc_exbus_tim0_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim0_field_t; + +typedef struct stc_exbus_tim1_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim1_field_t; + +typedef struct stc_exbus_tim2_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim2_field_t; + +typedef struct stc_exbus_tim3_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim3_field_t; + +typedef struct stc_exbus_tim4_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim4_field_t; + +typedef struct stc_exbus_tim5_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim5_field_t; + +typedef struct stc_exbus_tim6_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim6_field_t; + +typedef struct stc_exbus_tim7_field +{ + union { + struct { + __IO uint32_t RACC :4; + __IO uint32_t RADC :4; + __IO uint32_t FRADC :4; + __IO uint32_t RIDLC :4; + __IO uint32_t WACC :4; + __IO uint32_t WADC :4; + __IO uint32_t WWEC :4; + __IO uint32_t WIDLC :4; + }; + struct { + __IO uint32_t RACC0 :1; + __IO uint32_t RACC1 :1; + __IO uint32_t RACC2 :1; + __IO uint32_t RACC3 :1; + __IO uint32_t RADC0 :1; + __IO uint32_t RADC1 :1; + __IO uint32_t RADC2 :1; + __IO uint32_t RADC3 :1; + __IO uint32_t FRADC0 :1; + __IO uint32_t FRADC1 :1; + __IO uint32_t FRADC2 :1; + __IO uint32_t FRADC3 :1; + __IO uint32_t RIDLC0 :1; + __IO uint32_t RIDLC1 :1; + __IO uint32_t RIDLC2 :1; + __IO uint32_t RIDLC3 :1; + __IO uint32_t WACC0 :1; + __IO uint32_t WACC1 :1; + __IO uint32_t WACC2 :1; + __IO uint32_t WACC3 :1; + __IO uint32_t WADC0 :1; + __IO uint32_t WADC1 :1; + __IO uint32_t WADC2 :1; + __IO uint32_t WADC3 :1; + __IO uint32_t WWEC0 :1; + __IO uint32_t WWEC1 :1; + __IO uint32_t WWEC2 :1; + __IO uint32_t WWEC3 :1; + __IO uint32_t WIDLC0 :1; + __IO uint32_t WIDLC1 :1; + __IO uint32_t WIDLC2 :1; + __IO uint32_t WIDLC3 :1; + }; + }; +} stc_exbus_tim7_field_t; + +typedef struct stc_exbus_area0_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area0_field_t; + +typedef struct stc_exbus_area1_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area1_field_t; + +typedef struct stc_exbus_area2_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area2_field_t; + +typedef struct stc_exbus_area3_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area3_field_t; + +typedef struct stc_exbus_area4_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area4_field_t; + +typedef struct stc_exbus_area5_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area5_field_t; + +typedef struct stc_exbus_area6_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area6_field_t; + +typedef struct stc_exbus_area7_field +{ + union { + struct { + __IO uint32_t ADDR :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t MASK :7; + __IO uint32_t RESERVED2 :9; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t RESERVED1 :8; + __IO uint32_t MASK0 :1; + __IO uint32_t MASK1 :1; + __IO uint32_t MASK2 :1; + __IO uint32_t MASK3 :1; + __IO uint32_t MASK4 :1; + __IO uint32_t MASK5 :1; + __IO uint32_t MASK6 :1; + __IO uint32_t RESERVED3 :9; + }; + }; +} stc_exbus_area7_field_t; + +typedef struct stc_exbus_atim0_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim0_field_t; + +typedef struct stc_exbus_atim1_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim1_field_t; + +typedef struct stc_exbus_atim2_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim2_field_t; + +typedef struct stc_exbus_atim3_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim3_field_t; + +typedef struct stc_exbus_atim4_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim4_field_t; + +typedef struct stc_exbus_atim5_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim5_field_t; + +typedef struct stc_exbus_atim6_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim6_field_t; + +typedef struct stc_exbus_atim7_field +{ + union { + struct { + __IO uint32_t ALC :4; + __IO uint32_t ALES :4; + __IO uint32_t ALEW :4; + __IO uint32_t RESERVED0 :20; + }; + struct { + __IO uint32_t ALC0 :1; + __IO uint32_t ALC1 :1; + __IO uint32_t ALC2 :1; + __IO uint32_t ALC3 :1; + __IO uint32_t ALES0 :1; + __IO uint32_t ALES1 :1; + __IO uint32_t ALES2 :1; + __IO uint32_t ALES3 :1; + __IO uint32_t ALEW0 :1; + __IO uint32_t ALEW1 :1; + __IO uint32_t ALEW2 :1; + __IO uint32_t ALEW3 :1; + __IO uint32_t RESERVED1 :20; + }; + }; +} stc_exbus_atim7_field_t; + +typedef struct stc_exbus_sdmode_field +{ + union { + struct { + __IO uint32_t SDON :1; + __IO uint32_t PDON :1; + __IO uint32_t ROFF :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t CASEL :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t RASEL :4; + __IO uint32_t BASEL :4; + __IO uint32_t MSDCLKOFF :1; + __IO uint32_t RESERVED4 :15; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t CASEL0 :1; + __IO uint32_t CASEL1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t RASEL0 :1; + __IO uint32_t RASEL1 :1; + __IO uint32_t RASEL2 :1; + __IO uint32_t RASEL3 :1; + __IO uint32_t BASEL0 :1; + __IO uint32_t BASEL1 :1; + __IO uint32_t BASEL2 :1; + __IO uint32_t BASEL3 :1; + __IO uint32_t RESERVED5 :16; + }; + }; +} stc_exbus_sdmode_field_t; + +typedef struct stc_exbus_reftim_field +{ + union { + struct { + __IO uint32_t REFC :16; + __IO uint32_t NREF :8; + __IO uint32_t PREF :1; + __IO uint32_t RESERVED0 :7; + }; + struct { + __IO uint32_t REFC0 :1; + __IO uint32_t REFC1 :1; + __IO uint32_t REFC2 :1; + __IO uint32_t REFC3 :1; + __IO uint32_t REFC4 :1; + __IO uint32_t REFC5 :1; + __IO uint32_t REFC6 :1; + __IO uint32_t REFC7 :1; + __IO uint32_t REFC8 :1; + __IO uint32_t REFC9 :1; + __IO uint32_t REFC10 :1; + __IO uint32_t REFC11 :1; + __IO uint32_t REFC12 :1; + __IO uint32_t REFC13 :1; + __IO uint32_t REFC14 :1; + __IO uint32_t REFC15 :1; + __IO uint32_t NREF0 :1; + __IO uint32_t NREF1 :1; + __IO uint32_t NREF2 :1; + __IO uint32_t NREF3 :1; + __IO uint32_t NREF4 :1; + __IO uint32_t NREF5 :1; + __IO uint32_t NREF6 :1; + __IO uint32_t NREF7 :1; + __IO uint32_t RESERVED1 :8; + }; + }; +} stc_exbus_reftim_field_t; + +typedef struct stc_exbus_pwrdwn_field +{ + union { + struct { + __IO uint32_t PDC :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t PDC0 :1; + __IO uint32_t PDC1 :1; + __IO uint32_t PDC2 :1; + __IO uint32_t PDC3 :1; + __IO uint32_t PDC4 :1; + __IO uint32_t PDC5 :1; + __IO uint32_t PDC6 :1; + __IO uint32_t PDC7 :1; + __IO uint32_t PDC8 :1; + __IO uint32_t PDC9 :1; + __IO uint32_t PDC10 :1; + __IO uint32_t PDC11 :1; + __IO uint32_t PDC12 :1; + __IO uint32_t PDC13 :1; + __IO uint32_t PDC14 :1; + __IO uint32_t PDC15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_exbus_pwrdwn_field_t; + +typedef struct stc_exbus_sdtim_field +{ + union { + struct { + __IO uint32_t CL :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t TRC :4; + __IO uint32_t TRP :4; + __IO uint32_t TRCD :4; + __IO uint32_t TRAS :4; + __IO uint32_t TREFC :4; + __IO uint32_t TDPL :2; + __IO uint32_t RESERVED2 :5; + __IO uint32_t BOFF :1; + }; + struct { + __IO uint32_t CL0 :1; + __IO uint32_t CL1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t TRC0 :1; + __IO uint32_t TRC1 :1; + __IO uint32_t TRC2 :1; + __IO uint32_t TRC3 :1; + __IO uint32_t TRP0 :1; + __IO uint32_t TRP1 :1; + __IO uint32_t TRP2 :1; + __IO uint32_t TRP3 :1; + __IO uint32_t TRCD0 :1; + __IO uint32_t TRCD1 :1; + __IO uint32_t TRCD2 :1; + __IO uint32_t TRCD3 :1; + __IO uint32_t TRAS0 :1; + __IO uint32_t TRAS1 :1; + __IO uint32_t TRAS2 :1; + __IO uint32_t TRAS3 :1; + __IO uint32_t TREFC0 :1; + __IO uint32_t TREFC1 :1; + __IO uint32_t TREFC2 :1; + __IO uint32_t TREFC3 :1; + __IO uint32_t TDPL0 :1; + __IO uint32_t TDPL1 :1; + __IO uint32_t RESERVED3 :6; + }; + }; +} stc_exbus_sdtim_field_t; + +typedef struct stc_exbus_sdcmd_field +{ + union { + struct { + __IO uint32_t SDAD :16; + __IO uint32_t SDWE :1; + __IO uint32_t SDCAS :1; + __IO uint32_t SDRAS :1; + __IO uint32_t SDCS :1; + __IO uint32_t SDCKE :1; + __IO uint32_t RESERVED0 :10; + __IO uint32_t PEND :1; + }; + struct { + __IO uint32_t SDAD0 :1; + __IO uint32_t SDAD1 :1; + __IO uint32_t SDAD2 :1; + __IO uint32_t SDAD3 :1; + __IO uint32_t SDAD4 :1; + __IO uint32_t SDAD5 :1; + __IO uint32_t SDAD6 :1; + __IO uint32_t SDAD7 :1; + __IO uint32_t SDAD8 :1; + __IO uint32_t SDAD9 :1; + __IO uint32_t SDAD10 :1; + __IO uint32_t SDAD11 :1; + __IO uint32_t SDAD12 :1; + __IO uint32_t SDAD13 :1; + __IO uint32_t SDAD14 :1; + __IO uint32_t SDAD15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_exbus_sdcmd_field_t; + +typedef struct stc_exbus_memcerr_field +{ + __IO uint32_t SFER :1; + __IO uint32_t SDER :1; + __IO uint32_t SFION :1; + __IO uint32_t SDION :1; + __IO uint32_t RESERVED0 :28; +} stc_exbus_memcerr_field_t; + +typedef struct stc_exbus_dclkr_field +{ + union { + struct { + __IO uint32_t MDIV :4; + __IO uint32_t MCLKON :1; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t MDIV0 :1; + __IO uint32_t MDIV1 :1; + __IO uint32_t MDIV2 :1; + __IO uint32_t MDIV3 :1; + __IO uint32_t RESERVED1 :28; + }; + }; +} stc_exbus_dclkr_field_t; + +typedef struct stc_exbus_est_field +{ + __IO uint32_t WERR :1; + __IO uint32_t RESERVED0 :31; +} stc_exbus_est_field_t; + +typedef struct stc_exbus_wead_field +{ + union { + struct { + __IO uint32_t ADDR :32; + }; + struct { + __IO uint32_t ADDR0 :1; + __IO uint32_t ADDR1 :1; + __IO uint32_t ADDR2 :1; + __IO uint32_t ADDR3 :1; + __IO uint32_t ADDR4 :1; + __IO uint32_t ADDR5 :1; + __IO uint32_t ADDR6 :1; + __IO uint32_t ADDR7 :1; + __IO uint32_t ADDR8 :1; + __IO uint32_t ADDR9 :1; + __IO uint32_t ADDR10 :1; + __IO uint32_t ADDR11 :1; + __IO uint32_t ADDR12 :1; + __IO uint32_t ADDR13 :1; + __IO uint32_t ADDR14 :1; + __IO uint32_t ADDR15 :1; + __IO uint32_t ADDR16 :1; + __IO uint32_t ADDR17 :1; + __IO uint32_t ADDR18 :1; + __IO uint32_t ADDR19 :1; + __IO uint32_t ADDR20 :1; + __IO uint32_t ADDR21 :1; + __IO uint32_t ADDR22 :1; + __IO uint32_t ADDR23 :1; + __IO uint32_t ADDR24 :1; + __IO uint32_t ADDR25 :1; + __IO uint32_t ADDR26 :1; + __IO uint32_t ADDR27 :1; + __IO uint32_t ADDR28 :1; + __IO uint32_t ADDR29 :1; + __IO uint32_t ADDR30 :1; + __IO uint32_t ADDR31 :1; + }; + }; +} stc_exbus_wead_field_t; + +typedef struct stc_exbus_esclr_field +{ + __IO uint32_t WERRCLR :1; + __IO uint32_t RESERVED0 :31; +} stc_exbus_esclr_field_t; + +typedef struct stc_exbus_amode_field +{ + __IO uint32_t WAEN :1; + __IO uint32_t RESERVED0 :31; +} stc_exbus_amode_field_t; + +/******************************************************************************* +* EXTI_MODULE +*******************************************************************************/ +typedef struct stc_exti_enir_field +{ + __IO uint32_t EN0 :1; + __IO uint32_t EN1 :1; + __IO uint32_t EN2 :1; + __IO uint32_t EN3 :1; + __IO uint32_t EN4 :1; + __IO uint32_t EN5 :1; + __IO uint32_t EN6 :1; + __IO uint32_t EN7 :1; + __IO uint32_t EN8 :1; + __IO uint32_t EN9 :1; + __IO uint32_t EN10 :1; + __IO uint32_t EN11 :1; + __IO uint32_t EN12 :1; + __IO uint32_t EN13 :1; + __IO uint32_t EN14 :1; + __IO uint32_t EN15 :1; + __IO uint32_t EN16 :1; + __IO uint32_t EN17 :1; + __IO uint32_t EN18 :1; + __IO uint32_t EN19 :1; + __IO uint32_t EN20 :1; + __IO uint32_t EN21 :1; + __IO uint32_t EN22 :1; + __IO uint32_t EN23 :1; + __IO uint32_t EN24 :1; + __IO uint32_t EN25 :1; + __IO uint32_t EN26 :1; + __IO uint32_t EN27 :1; + __IO uint32_t EN28 :1; + __IO uint32_t EN29 :1; + __IO uint32_t EN30 :1; + __IO uint32_t EN31 :1; +} stc_exti_enir_field_t; + +typedef struct stc_exti_eirr_field +{ + __IO uint32_t ER0 :1; + __IO uint32_t ER1 :1; + __IO uint32_t ER2 :1; + __IO uint32_t ER3 :1; + __IO uint32_t ER4 :1; + __IO uint32_t ER5 :1; + __IO uint32_t ER6 :1; + __IO uint32_t ER7 :1; + __IO uint32_t ER8 :1; + __IO uint32_t ER9 :1; + __IO uint32_t ER10 :1; + __IO uint32_t ER11 :1; + __IO uint32_t ER12 :1; + __IO uint32_t ER13 :1; + __IO uint32_t ER14 :1; + __IO uint32_t ER15 :1; + __IO uint32_t ER16 :1; + __IO uint32_t ER17 :1; + __IO uint32_t ER18 :1; + __IO uint32_t ER19 :1; + __IO uint32_t ER20 :1; + __IO uint32_t ER21 :1; + __IO uint32_t ER22 :1; + __IO uint32_t ER23 :1; + __IO uint32_t ER24 :1; + __IO uint32_t ER25 :1; + __IO uint32_t ER26 :1; + __IO uint32_t ER27 :1; + __IO uint32_t ER28 :1; + __IO uint32_t ER29 :1; + __IO uint32_t ER30 :1; + __IO uint32_t ER31 :1; +} stc_exti_eirr_field_t; + +typedef struct stc_exti_eicl_field +{ + __IO uint32_t ECL0 :1; + __IO uint32_t ECL1 :1; + __IO uint32_t ECL2 :1; + __IO uint32_t ECL3 :1; + __IO uint32_t ECL4 :1; + __IO uint32_t ECL5 :1; + __IO uint32_t ECL6 :1; + __IO uint32_t ECL7 :1; + __IO uint32_t ECL8 :1; + __IO uint32_t ECL9 :1; + __IO uint32_t ECL10 :1; + __IO uint32_t ECL11 :1; + __IO uint32_t ECL12 :1; + __IO uint32_t ECL13 :1; + __IO uint32_t ECL14 :1; + __IO uint32_t ECL15 :1; + __IO uint32_t ECL16 :1; + __IO uint32_t ECL17 :1; + __IO uint32_t ECL18 :1; + __IO uint32_t ECL19 :1; + __IO uint32_t ECL20 :1; + __IO uint32_t ECL21 :1; + __IO uint32_t ECL22 :1; + __IO uint32_t ECL23 :1; + __IO uint32_t ECL24 :1; + __IO uint32_t ECL25 :1; + __IO uint32_t ECL26 :1; + __IO uint32_t ECL27 :1; + __IO uint32_t ECL28 :1; + __IO uint32_t ECL29 :1; + __IO uint32_t ECL30 :1; + __IO uint32_t ECL31 :1; +} stc_exti_eicl_field_t; + +typedef struct stc_exti_elvr_field +{ + __IO uint32_t LA0 :1; + __IO uint32_t LB0 :1; + __IO uint32_t LA1 :1; + __IO uint32_t LB1 :1; + __IO uint32_t LA2 :1; + __IO uint32_t LB2 :1; + __IO uint32_t LA3 :1; + __IO uint32_t LB3 :1; + __IO uint32_t LA4 :1; + __IO uint32_t LB4 :1; + __IO uint32_t LA5 :1; + __IO uint32_t LB5 :1; + __IO uint32_t LA6 :1; + __IO uint32_t LB6 :1; + __IO uint32_t LA7 :1; + __IO uint32_t LB7 :1; + __IO uint32_t LA8 :1; + __IO uint32_t LB8 :1; + __IO uint32_t LA9 :1; + __IO uint32_t LB9 :1; + __IO uint32_t LA10 :1; + __IO uint32_t LB10 :1; + __IO uint32_t LA11 :1; + __IO uint32_t LB11 :1; + __IO uint32_t LA12 :1; + __IO uint32_t LB12 :1; + __IO uint32_t LA13 :1; + __IO uint32_t LB13 :1; + __IO uint32_t LA14 :1; + __IO uint32_t LB14 :1; + __IO uint32_t LA15 :1; + __IO uint32_t LB15 :1; +} stc_exti_elvr_field_t; + +typedef struct stc_exti_elvr1_field +{ + __IO uint32_t LA16 :1; + __IO uint32_t LB16 :1; + __IO uint32_t LA17 :1; + __IO uint32_t LB17 :1; + __IO uint32_t LA18 :1; + __IO uint32_t LB18 :1; + __IO uint32_t LA19 :1; + __IO uint32_t LB19 :1; + __IO uint32_t LA20 :1; + __IO uint32_t LB20 :1; + __IO uint32_t LA21 :1; + __IO uint32_t LB21 :1; + __IO uint32_t LA22 :1; + __IO uint32_t LB22 :1; + __IO uint32_t LA23 :1; + __IO uint32_t LB23 :1; + __IO uint32_t LA24 :1; + __IO uint32_t LB24 :1; + __IO uint32_t LA25 :1; + __IO uint32_t LB25 :1; + __IO uint32_t LA26 :1; + __IO uint32_t LB26 :1; + __IO uint32_t LA27 :1; + __IO uint32_t LB27 :1; + __IO uint32_t LA28 :1; + __IO uint32_t LB28 :1; + __IO uint32_t LA29 :1; + __IO uint32_t LB29 :1; + __IO uint32_t LA30 :1; + __IO uint32_t LB30 :1; + __IO uint32_t LA31 :1; + __IO uint32_t LB31 :1; +} stc_exti_elvr1_field_t; + +typedef struct stc_exti_nmirr_field +{ + __IO uint16_t NR :1; + __IO uint16_t RESERVED0 :15; +} stc_exti_nmirr_field_t; + +typedef struct stc_exti_nmicl_field +{ + __IO uint16_t NCL :1; + __IO uint16_t RESERVED0 :15; +} stc_exti_nmicl_field_t; + +/******************************************************************************* +* FLASH_IF_MODULE +*******************************************************************************/ +typedef struct stc_flash_if_faszr_field +{ + union { + struct { + __IO uint32_t ASZ :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t ASZ0 :1; + __IO uint32_t ASZ1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_flash_if_faszr_field_t; + +typedef struct stc_flash_if_frwtr_field +{ + union { + struct { + __IO uint32_t RWT :2; + __IO uint32_t RESERVED0 :30; + }; + struct { + __IO uint32_t RWT0 :1; + __IO uint32_t RWT1 :1; + __IO uint32_t RESERVED1 :30; + }; + }; +} stc_flash_if_frwtr_field_t; + +typedef struct stc_flash_if_fstr_field +{ + __IO uint32_t RDY :1; + __IO uint32_t HNG :1; + __IO uint32_t ERR :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_fstr_field_t; + +typedef struct stc_flash_if_fsyndn_field +{ + union { + struct { + __IO uint32_t SD :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t SD0 :1; + __IO uint32_t SD1 :1; + __IO uint32_t SD2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_flash_if_fsyndn_field_t; + +typedef struct stc_flash_if_fbfcr_field +{ + __IO uint32_t BE :1; + __IO uint32_t BS :1; + __IO uint32_t RESERVED0 :30; +} stc_flash_if_fbfcr_field_t; + +typedef struct stc_flash_if_ficr_field +{ + __IO uint32_t RDYIE :1; + __IO uint32_t HNGIE :1; + __IO uint32_t ERRIE :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_ficr_field_t; + +typedef struct stc_flash_if_fisr_field +{ + __IO uint32_t RDYIF :1; + __IO uint32_t HNGIF :1; + __IO uint32_t ERRIF :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_fisr_field_t; + +typedef struct stc_flash_if_ficlr_field +{ + __IO uint32_t RDYIC :1; + __IO uint32_t HNGIC :1; + __IO uint32_t ERRIC :1; + __IO uint32_t RESERVED0 :29; +} stc_flash_if_ficlr_field_t; + +typedef struct stc_flash_if_dfctrlr_field +{ + union { + struct { + __IO uint32_t DFE :1; + __IO uint32_t RME :1; + __IO uint32_t RESERVED0 :14; + __IO uint32_t WKEY :16; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t WKEY0 :1; + __IO uint32_t WKEY1 :1; + __IO uint32_t WKEY2 :1; + __IO uint32_t WKEY3 :1; + __IO uint32_t WKEY4 :1; + __IO uint32_t WKEY5 :1; + __IO uint32_t WKEY6 :1; + __IO uint32_t WKEY7 :1; + __IO uint32_t WKEY8 :1; + __IO uint32_t WKEY9 :1; + __IO uint32_t WKEY10 :1; + __IO uint32_t WKEY11 :1; + __IO uint32_t WKEY12 :1; + __IO uint32_t WKEY13 :1; + __IO uint32_t WKEY14 :1; + __IO uint32_t WKEY15 :1; + }; + }; +} stc_flash_if_dfctrlr_field_t; + +typedef struct stc_flash_if_crtrmm_field +{ + union { + struct { + __IO uint32_t TRMM :10; + __IO uint32_t RESERVED0 :6; + __IO uint32_t TTRMM :5; + __IO uint32_t RESERVED2 :11; + }; + struct { + __IO uint32_t TRMM0 :1; + __IO uint32_t TRMM1 :1; + __IO uint32_t TRMM2 :1; + __IO uint32_t TRMM3 :1; + __IO uint32_t TRMM4 :1; + __IO uint32_t TRMM5 :1; + __IO uint32_t TRMM6 :1; + __IO uint32_t TRMM7 :1; + __IO uint32_t TRMM8 :1; + __IO uint32_t TRMM9 :1; + __IO uint32_t RESERVED1 :6; + __IO uint32_t TTRMM0 :1; + __IO uint32_t TTRMM1 :1; + __IO uint32_t TTRMM2 :1; + __IO uint32_t TTRMM3 :1; + __IO uint32_t TTRMM4 :1; + __IO uint32_t RESERVED3 :11; + }; + }; +} stc_flash_if_crtrmm_field_t; + +typedef struct stc_flash_if_fgpdm1_field +{ + union { + struct { + __IO uint32_t GPD1 :32; + }; + struct { + __IO uint32_t GPD10 :1; + __IO uint32_t GPD11 :1; + __IO uint32_t GPD12 :1; + __IO uint32_t GPD13 :1; + __IO uint32_t GPD14 :1; + __IO uint32_t GPD15 :1; + __IO uint32_t GPD16 :1; + __IO uint32_t GPD17 :1; + __IO uint32_t GPD18 :1; + __IO uint32_t GPD19 :1; + __IO uint32_t GPD110 :1; + __IO uint32_t GPD111 :1; + __IO uint32_t GPD112 :1; + __IO uint32_t GPD113 :1; + __IO uint32_t GPD114 :1; + __IO uint32_t GPD115 :1; + __IO uint32_t GPD116 :1; + __IO uint32_t GPD117 :1; + __IO uint32_t GPD118 :1; + __IO uint32_t GPD119 :1; + __IO uint32_t GPD120 :1; + __IO uint32_t GPD121 :1; + __IO uint32_t GPD122 :1; + __IO uint32_t GPD123 :1; + __IO uint32_t GPD124 :1; + __IO uint32_t GPD125 :1; + __IO uint32_t GPD126 :1; + __IO uint32_t GPD127 :1; + __IO uint32_t GPD128 :1; + __IO uint32_t GPD129 :1; + __IO uint32_t GPD130 :1; + __IO uint32_t GPD131 :1; + }; + }; +} stc_flash_if_fgpdm1_field_t; + +typedef struct stc_flash_if_fgpdm2_field +{ + union { + struct { + __IO uint32_t GPD2 :32; + }; + struct { + __IO uint32_t GPD20 :1; + __IO uint32_t GPD21 :1; + __IO uint32_t GPD22 :1; + __IO uint32_t GPD23 :1; + __IO uint32_t GPD24 :1; + __IO uint32_t GPD25 :1; + __IO uint32_t GPD26 :1; + __IO uint32_t GPD27 :1; + __IO uint32_t GPD28 :1; + __IO uint32_t GPD29 :1; + __IO uint32_t GPD210 :1; + __IO uint32_t GPD211 :1; + __IO uint32_t GPD212 :1; + __IO uint32_t GPD213 :1; + __IO uint32_t GPD214 :1; + __IO uint32_t GPD215 :1; + __IO uint32_t GPD216 :1; + __IO uint32_t GPD217 :1; + __IO uint32_t GPD218 :1; + __IO uint32_t GPD219 :1; + __IO uint32_t GPD220 :1; + __IO uint32_t GPD221 :1; + __IO uint32_t GPD222 :1; + __IO uint32_t GPD223 :1; + __IO uint32_t GPD224 :1; + __IO uint32_t GPD225 :1; + __IO uint32_t GPD226 :1; + __IO uint32_t GPD227 :1; + __IO uint32_t GPD228 :1; + __IO uint32_t GPD229 :1; + __IO uint32_t GPD230 :1; + __IO uint32_t GPD231 :1; + }; + }; +} stc_flash_if_fgpdm2_field_t; + +typedef struct stc_flash_if_fgpdm3_field +{ + union { + struct { + __IO uint32_t GPD3 :32; + }; + struct { + __IO uint32_t GPD30 :1; + __IO uint32_t GPD31 :1; + __IO uint32_t GPD32 :1; + __IO uint32_t GPD33 :1; + __IO uint32_t GPD34 :1; + __IO uint32_t GPD35 :1; + __IO uint32_t GPD36 :1; + __IO uint32_t GPD37 :1; + __IO uint32_t GPD38 :1; + __IO uint32_t GPD39 :1; + __IO uint32_t GPD310 :1; + __IO uint32_t GPD311 :1; + __IO uint32_t GPD312 :1; + __IO uint32_t GPD313 :1; + __IO uint32_t GPD314 :1; + __IO uint32_t GPD315 :1; + __IO uint32_t GPD316 :1; + __IO uint32_t GPD317 :1; + __IO uint32_t GPD318 :1; + __IO uint32_t GPD319 :1; + __IO uint32_t GPD320 :1; + __IO uint32_t GPD321 :1; + __IO uint32_t GPD322 :1; + __IO uint32_t GPD323 :1; + __IO uint32_t GPD324 :1; + __IO uint32_t GPD325 :1; + __IO uint32_t GPD326 :1; + __IO uint32_t GPD327 :1; + __IO uint32_t GPD328 :1; + __IO uint32_t GPD329 :1; + __IO uint32_t GPD330 :1; + __IO uint32_t GPD331 :1; + }; + }; +} stc_flash_if_fgpdm3_field_t; + +typedef struct stc_flash_if_fgpdm4_field +{ + union { + struct { + __IO uint32_t GPD4 :32; + }; + struct { + __IO uint32_t GPD40 :1; + __IO uint32_t GPD41 :1; + __IO uint32_t GPD42 :1; + __IO uint32_t GPD43 :1; + __IO uint32_t GPD44 :1; + __IO uint32_t GPD45 :1; + __IO uint32_t GPD46 :1; + __IO uint32_t GPD47 :1; + __IO uint32_t GPD48 :1; + __IO uint32_t GPD49 :1; + __IO uint32_t GPD410 :1; + __IO uint32_t GPD411 :1; + __IO uint32_t GPD412 :1; + __IO uint32_t GPD413 :1; + __IO uint32_t GPD414 :1; + __IO uint32_t GPD415 :1; + __IO uint32_t GPD416 :1; + __IO uint32_t GPD417 :1; + __IO uint32_t GPD418 :1; + __IO uint32_t GPD419 :1; + __IO uint32_t GPD420 :1; + __IO uint32_t GPD421 :1; + __IO uint32_t GPD422 :1; + __IO uint32_t GPD423 :1; + __IO uint32_t GPD424 :1; + __IO uint32_t GPD425 :1; + __IO uint32_t GPD426 :1; + __IO uint32_t GPD427 :1; + __IO uint32_t GPD428 :1; + __IO uint32_t GPD429 :1; + __IO uint32_t GPD430 :1; + __IO uint32_t GPD431 :1; + }; + }; +} stc_flash_if_fgpdm4_field_t; + +/******************************************************************************* +* GPIO_MODULE +*******************************************************************************/ +typedef struct stc_gpio_pfr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pfr0_field_t; + +typedef struct stc_gpio_pfr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfr1_field_t; + +typedef struct stc_gpio_pfr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pfr2_field_t; + +typedef struct stc_gpio_pfr3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pfr3_field_t; + +typedef struct stc_gpio_pfr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pfr4_field_t; + +typedef struct stc_gpio_pfr5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfr5_field_t; + +typedef struct stc_gpio_pfr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pfr6_field_t; + +typedef struct stc_gpio_pfr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pfr7_field_t; + +typedef struct stc_gpio_pfr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pfr8_field_t; + +typedef struct stc_gpio_pfr9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_pfr9_field_t; + +typedef struct stc_gpio_pfra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfra_field_t; + +typedef struct stc_gpio_pfrb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfrb_field_t; + +typedef struct stc_gpio_pfrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pfrc_field_t; + +typedef struct stc_gpio_pfrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pfrd_field_t; + +typedef struct stc_gpio_pfre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pfre_field_t; + +typedef struct stc_gpio_pfrf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_pfrf_field_t; + +typedef struct stc_gpio_pcr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pcr0_field_t; + +typedef struct stc_gpio_pcr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcr1_field_t; + +typedef struct stc_gpio_pcr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pcr2_field_t; + +typedef struct stc_gpio_pcr3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pcr3_field_t; + +typedef struct stc_gpio_pcr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pcr4_field_t; + +typedef struct stc_gpio_pcr5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcr5_field_t; + +typedef struct stc_gpio_pcr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pcr6_field_t; + +typedef struct stc_gpio_pcr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pcr7_field_t; + +typedef struct stc_gpio_pcr9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_pcr9_field_t; + +typedef struct stc_gpio_pcra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcra_field_t; + +typedef struct stc_gpio_pcrb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcrb_field_t; + +typedef struct stc_gpio_pcrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pcrc_field_t; + +typedef struct stc_gpio_pcrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pcrd_field_t; + +typedef struct stc_gpio_pcre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pcre_field_t; + +typedef struct stc_gpio_pcrf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_pcrf_field_t; + +typedef struct stc_gpio_ddr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_ddr0_field_t; + +typedef struct stc_gpio_ddr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddr1_field_t; + +typedef struct stc_gpio_ddr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_ddr2_field_t; + +typedef struct stc_gpio_ddr3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_ddr3_field_t; + +typedef struct stc_gpio_ddr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_ddr4_field_t; + +typedef struct stc_gpio_ddr5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddr5_field_t; + +typedef struct stc_gpio_ddr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_ddr6_field_t; + +typedef struct stc_gpio_ddr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_ddr7_field_t; + +typedef struct stc_gpio_ddr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_ddr8_field_t; + +typedef struct stc_gpio_ddr9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_ddr9_field_t; + +typedef struct stc_gpio_ddra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddra_field_t; + +typedef struct stc_gpio_ddrb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddrb_field_t; + +typedef struct stc_gpio_ddrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_ddrc_field_t; + +typedef struct stc_gpio_ddrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_ddrd_field_t; + +typedef struct stc_gpio_ddre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_ddre_field_t; + +typedef struct stc_gpio_ddrf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_ddrf_field_t; + +typedef struct stc_gpio_pdir0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pdir0_field_t; + +typedef struct stc_gpio_pdir1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdir1_field_t; + +typedef struct stc_gpio_pdir2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pdir2_field_t; + +typedef struct stc_gpio_pdir3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdir3_field_t; + +typedef struct stc_gpio_pdir4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdir4_field_t; + +typedef struct stc_gpio_pdir5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdir5_field_t; + +typedef struct stc_gpio_pdir6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdir6_field_t; + +typedef struct stc_gpio_pdir7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdir7_field_t; + +typedef struct stc_gpio_pdir8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pdir8_field_t; + +typedef struct stc_gpio_pdir9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_pdir9_field_t; + +typedef struct stc_gpio_pdira_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdira_field_t; + +typedef struct stc_gpio_pdirb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdirb_field_t; + +typedef struct stc_gpio_pdirc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdirc_field_t; + +typedef struct stc_gpio_pdird_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pdird_field_t; + +typedef struct stc_gpio_pdire_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pdire_field_t; + +typedef struct stc_gpio_pdirf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_pdirf_field_t; + +typedef struct stc_gpio_pdor0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pdor0_field_t; + +typedef struct stc_gpio_pdor1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdor1_field_t; + +typedef struct stc_gpio_pdor2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pdor2_field_t; + +typedef struct stc_gpio_pdor3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdor3_field_t; + +typedef struct stc_gpio_pdor4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdor4_field_t; + +typedef struct stc_gpio_pdor5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdor5_field_t; + +typedef struct stc_gpio_pdor6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdor6_field_t; + +typedef struct stc_gpio_pdor7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdor7_field_t; + +typedef struct stc_gpio_pdor8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pdor8_field_t; + +typedef struct stc_gpio_pdor9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_pdor9_field_t; + +typedef struct stc_gpio_pdora_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdora_field_t; + +typedef struct stc_gpio_pdorb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdorb_field_t; + +typedef struct stc_gpio_pdorc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdorc_field_t; + +typedef struct stc_gpio_pdord_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pdord_field_t; + +typedef struct stc_gpio_pdore_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pdore_field_t; + +typedef struct stc_gpio_pdorf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_pdorf_field_t; + +typedef struct stc_gpio_ade_field +{ + __IO uint32_t AN00 :1; + __IO uint32_t AN01 :1; + __IO uint32_t AN02 :1; + __IO uint32_t AN03 :1; + __IO uint32_t AN04 :1; + __IO uint32_t AN05 :1; + __IO uint32_t AN06 :1; + __IO uint32_t AN07 :1; + __IO uint32_t AN08 :1; + __IO uint32_t AN09 :1; + __IO uint32_t AN10 :1; + __IO uint32_t AN11 :1; + __IO uint32_t AN12 :1; + __IO uint32_t AN13 :1; + __IO uint32_t AN14 :1; + __IO uint32_t AN15 :1; + __IO uint32_t AN16 :1; + __IO uint32_t AN17 :1; + __IO uint32_t AN18 :1; + __IO uint32_t AN19 :1; + __IO uint32_t AN20 :1; + __IO uint32_t AN21 :1; + __IO uint32_t AN22 :1; + __IO uint32_t AN23 :1; + __IO uint32_t AN24 :1; + __IO uint32_t AN25 :1; + __IO uint32_t AN26 :1; + __IO uint32_t AN27 :1; + __IO uint32_t AN28 :1; + __IO uint32_t AN29 :1; + __IO uint32_t AN30 :1; + __IO uint32_t AN31 :1; +} stc_gpio_ade_field_t; + +typedef struct stc_gpio_spsr_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t MAINXC :2; + __IO uint32_t USB0C :1; + __IO uint32_t USB1C :1; + __IO uint32_t RESERVED2 :26; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t MAINXC0 :1; + __IO uint32_t MAINXC1 :1; + __IO uint32_t RESERVED3 :28; + }; + }; +} stc_gpio_spsr_field_t; + +typedef struct stc_gpio_epfr00_field +{ + union { + struct { + __IO uint32_t NMIS :1; + __IO uint32_t CROUTE :2; + __IO uint32_t RESERVED1 :1; + __IO uint32_t RTCCOE :2; + __IO uint32_t SUBOUTE :2; + __IO uint32_t RESERVED3 :1; + __IO uint32_t USBP0E :1; + __IO uint32_t RESERVED4 :3; + __IO uint32_t USBP1E :1; + __IO uint32_t RESERVED5 :2; + __IO uint32_t JTAGEN0B :1; + __IO uint32_t JTAGEN1S :1; + __IO uint32_t RESERVED6 :6; + __IO uint32_t TRC0E :1; + __IO uint32_t TRC1E :1; + __IO uint32_t TRC2E :1; + __IO uint32_t TRC3E :1; + __IO uint32_t RESERVED7 :4; + }; + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t CROUTE0 :1; + __IO uint32_t CROUTE1 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t RTCCOE0 :1; + __IO uint32_t RTCCOE1 :1; + __IO uint32_t SUBOUTE0 :1; + __IO uint32_t SUBOUTE1 :1; + __IO uint32_t RESERVED8 :24; + }; + }; +} stc_gpio_epfr00_field_t; + +typedef struct stc_gpio_epfr01_field +{ + union { + struct { + __IO uint32_t RTO00E :2; + __IO uint32_t RTO01E :2; + __IO uint32_t RTO02E :2; + __IO uint32_t RTO03E :2; + __IO uint32_t RTO04E :2; + __IO uint32_t RTO05E :2; + __IO uint32_t DTTI0C :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t DTTI0S :2; + __IO uint32_t FRCK0S :2; + __IO uint32_t IC00S :3; + __IO uint32_t IC01S :3; + __IO uint32_t IC02S :3; + __IO uint32_t IC03S :3; + }; + struct { + __IO uint32_t RTO00E0 :1; + __IO uint32_t RTO00E1 :1; + __IO uint32_t RTO01E0 :1; + __IO uint32_t RTO01E1 :1; + __IO uint32_t RTO02E0 :1; + __IO uint32_t RTO02E1 :1; + __IO uint32_t RTO03E0 :1; + __IO uint32_t RTO03E1 :1; + __IO uint32_t RTO04E0 :1; + __IO uint32_t RTO04E1 :1; + __IO uint32_t RTO05E0 :1; + __IO uint32_t RTO05E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t DTTI0S0 :1; + __IO uint32_t DTTI0S1 :1; + __IO uint32_t FRCK0S0 :1; + __IO uint32_t FRCK0S1 :1; + __IO uint32_t IC00S0 :1; + __IO uint32_t IC00S1 :1; + __IO uint32_t IC00S2 :1; + __IO uint32_t IC01S0 :1; + __IO uint32_t IC01S1 :1; + __IO uint32_t IC01S2 :1; + __IO uint32_t IC02S0 :1; + __IO uint32_t IC02S1 :1; + __IO uint32_t IC02S2 :1; + __IO uint32_t IC03S0 :1; + __IO uint32_t IC03S1 :1; + __IO uint32_t IC03S2 :1; + }; + }; +} stc_gpio_epfr01_field_t; + +typedef struct stc_gpio_epfr02_field +{ + union { + struct { + __IO uint32_t RTO10E :2; + __IO uint32_t RTO11E :2; + __IO uint32_t RTO12E :2; + __IO uint32_t RTO13E :2; + __IO uint32_t RTO14E :2; + __IO uint32_t RTO15E :2; + __IO uint32_t DTTI1C :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t DTTI1S :2; + __IO uint32_t FRCK1S :2; + __IO uint32_t IC10S :3; + __IO uint32_t IC11S :3; + __IO uint32_t IC12S :3; + __IO uint32_t IC13S :3; + }; + struct { + __IO uint32_t RTO10E0 :1; + __IO uint32_t RTO10E1 :1; + __IO uint32_t RTO11E0 :1; + __IO uint32_t RTO11E1 :1; + __IO uint32_t RTO12E0 :1; + __IO uint32_t RTO12E1 :1; + __IO uint32_t RTO13E0 :1; + __IO uint32_t RTO13E1 :1; + __IO uint32_t RTO14E0 :1; + __IO uint32_t RTO14E1 :1; + __IO uint32_t RTO15E0 :1; + __IO uint32_t RTO15E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t DTTI1S0 :1; + __IO uint32_t DTTI1S1 :1; + __IO uint32_t FRCK1S0 :1; + __IO uint32_t FRCK1S1 :1; + __IO uint32_t IC10S0 :1; + __IO uint32_t IC10S1 :1; + __IO uint32_t IC10S2 :1; + __IO uint32_t IC11S0 :1; + __IO uint32_t IC11S1 :1; + __IO uint32_t IC11S2 :1; + __IO uint32_t IC12S0 :1; + __IO uint32_t IC12S1 :1; + __IO uint32_t IC12S2 :1; + __IO uint32_t IC13S0 :1; + __IO uint32_t IC13S1 :1; + __IO uint32_t IC13S2 :1; + }; + }; +} stc_gpio_epfr02_field_t; + +typedef struct stc_gpio_epfr03_field +{ + union { + struct { + __IO uint32_t RTO20E :2; + __IO uint32_t RTO21E :2; + __IO uint32_t RTO22E :2; + __IO uint32_t RTO23E :2; + __IO uint32_t RTO24E :2; + __IO uint32_t RTO25E :2; + __IO uint32_t DTTI2C :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t DTTI2S :2; + __IO uint32_t FRCK2S :2; + __IO uint32_t IC20S :3; + __IO uint32_t IC21S :3; + __IO uint32_t IC22S :3; + __IO uint32_t IC23S :3; + }; + struct { + __IO uint32_t RTO20E0 :1; + __IO uint32_t RTO20E1 :1; + __IO uint32_t RTO21E0 :1; + __IO uint32_t RTO21E1 :1; + __IO uint32_t RTO22E0 :1; + __IO uint32_t RTO22E1 :1; + __IO uint32_t RTO23E0 :1; + __IO uint32_t RTO23E1 :1; + __IO uint32_t RTO24E0 :1; + __IO uint32_t RTO24E1 :1; + __IO uint32_t RTO25E0 :1; + __IO uint32_t RTO25E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t DTTI2S0 :1; + __IO uint32_t DTTI2S1 :1; + __IO uint32_t FRCK2S0 :1; + __IO uint32_t FRCK2S1 :1; + __IO uint32_t IC20S0 :1; + __IO uint32_t IC20S1 :1; + __IO uint32_t IC20S2 :1; + __IO uint32_t IC21S0 :1; + __IO uint32_t IC21S1 :1; + __IO uint32_t IC21S2 :1; + __IO uint32_t IC22S0 :1; + __IO uint32_t IC22S1 :1; + __IO uint32_t IC22S2 :1; + __IO uint32_t IC23S0 :1; + __IO uint32_t IC23S1 :1; + __IO uint32_t IC23S2 :1; + }; + }; +} stc_gpio_epfr03_field_t; + +typedef struct stc_gpio_epfr04_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA0E :2; + __IO uint32_t TIOB0S :3; + __IO uint32_t RESERVED2 :1; + __IO uint32_t TIOA1S :2; + __IO uint32_t TIOA1E :2; + __IO uint32_t TIOB1S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA2E :2; + __IO uint32_t TIOB2S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA3S :2; + __IO uint32_t TIOA3E :2; + __IO uint32_t TIOB3S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA0E0 :1; + __IO uint32_t TIOA0E1 :1; + __IO uint32_t TIOB0S0 :1; + __IO uint32_t TIOB0S1 :1; + __IO uint32_t TIOB0S2 :1; + __IO uint32_t RESERVED3 :1; + __IO uint32_t TIOA1S0 :1; + __IO uint32_t TIOA1S1 :1; + __IO uint32_t TIOA1E0 :1; + __IO uint32_t TIOA1E1 :1; + __IO uint32_t TIOB1S0 :1; + __IO uint32_t TIOB1S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA2E0 :1; + __IO uint32_t TIOA2E1 :1; + __IO uint32_t TIOB2S0 :1; + __IO uint32_t TIOB2S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA3S0 :1; + __IO uint32_t TIOA3S1 :1; + __IO uint32_t TIOA3E0 :1; + __IO uint32_t TIOA3E1 :1; + __IO uint32_t TIOB3S0 :1; + __IO uint32_t TIOB3S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr04_field_t; + +typedef struct stc_gpio_epfr05_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA4E :2; + __IO uint32_t TIOB4S :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TIOA5S :2; + __IO uint32_t TIOA5E :2; + __IO uint32_t TIOB5S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA6E :2; + __IO uint32_t TIOB6S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA7S :2; + __IO uint32_t TIOA7E :2; + __IO uint32_t TIOB7S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA4E0 :1; + __IO uint32_t TIOA4E1 :1; + __IO uint32_t TIOB4S0 :1; + __IO uint32_t TIOB4S1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TIOA5S0 :1; + __IO uint32_t TIOA5S1 :1; + __IO uint32_t TIOA5E0 :1; + __IO uint32_t TIOA5E1 :1; + __IO uint32_t TIOB5S0 :1; + __IO uint32_t TIOB5S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA6E0 :1; + __IO uint32_t TIOA6E1 :1; + __IO uint32_t TIOB6S0 :1; + __IO uint32_t TIOB6S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA7S0 :1; + __IO uint32_t TIOA7S1 :1; + __IO uint32_t TIOA7E0 :1; + __IO uint32_t TIOA7E1 :1; + __IO uint32_t TIOB7S0 :1; + __IO uint32_t TIOB7S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr05_field_t; + +typedef struct stc_gpio_epfr06_field +{ + union { + struct { + __IO uint32_t EINT00S :2; + __IO uint32_t EINT01S :2; + __IO uint32_t EINT02S :2; + __IO uint32_t EINT03S :2; + __IO uint32_t EINT04S :2; + __IO uint32_t EINT05S :2; + __IO uint32_t EINT06S :2; + __IO uint32_t EINT07S :2; + __IO uint32_t EINT08S :2; + __IO uint32_t EINT09S :2; + __IO uint32_t EINT10S :2; + __IO uint32_t EINT11S :2; + __IO uint32_t EINT12S :2; + __IO uint32_t EINT13S :2; + __IO uint32_t EINT14S :2; + __IO uint32_t EINT15S :2; + }; + struct { + __IO uint32_t EINT00S0 :1; + __IO uint32_t EINT00S1 :1; + __IO uint32_t EINT01S0 :1; + __IO uint32_t EINT01S1 :1; + __IO uint32_t EINT02S0 :1; + __IO uint32_t EINT02S1 :1; + __IO uint32_t EINT03S0 :1; + __IO uint32_t EINT03S1 :1; + __IO uint32_t EINT04S0 :1; + __IO uint32_t EINT04S1 :1; + __IO uint32_t EINT05S0 :1; + __IO uint32_t EINT05S1 :1; + __IO uint32_t EINT06S0 :1; + __IO uint32_t EINT06S1 :1; + __IO uint32_t EINT07S0 :1; + __IO uint32_t EINT07S1 :1; + __IO uint32_t EINT08S0 :1; + __IO uint32_t EINT08S1 :1; + __IO uint32_t EINT09S0 :1; + __IO uint32_t EINT09S1 :1; + __IO uint32_t EINT10S0 :1; + __IO uint32_t EINT10S1 :1; + __IO uint32_t EINT11S0 :1; + __IO uint32_t EINT11S1 :1; + __IO uint32_t EINT12S0 :1; + __IO uint32_t EINT12S1 :1; + __IO uint32_t EINT13S0 :1; + __IO uint32_t EINT13S1 :1; + __IO uint32_t EINT14S0 :1; + __IO uint32_t EINT14S1 :1; + __IO uint32_t EINT15S0 :1; + __IO uint32_t EINT15S1 :1; + }; + }; +} stc_gpio_epfr06_field_t; + +typedef struct stc_gpio_epfr07_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t SIN0S :2; + __IO uint32_t SOT0B :2; + __IO uint32_t SCK0B :2; + __IO uint32_t SIN1S :2; + __IO uint32_t SOT1B :2; + __IO uint32_t SCK1B :2; + __IO uint32_t SIN2S :2; + __IO uint32_t SOT2B :2; + __IO uint32_t SCK2B :2; + __IO uint32_t SIN3S :2; + __IO uint32_t SOT3B :2; + __IO uint32_t SCK3B :2; + __IO uint32_t RESERVED2 :4; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t SIN0S0 :1; + __IO uint32_t SIN0S1 :1; + __IO uint32_t SOT0B0 :1; + __IO uint32_t SOT0B1 :1; + __IO uint32_t SCK0B0 :1; + __IO uint32_t SCK0B1 :1; + __IO uint32_t SIN1S0 :1; + __IO uint32_t SIN1S1 :1; + __IO uint32_t SOT1B0 :1; + __IO uint32_t SOT1B1 :1; + __IO uint32_t SCK1B0 :1; + __IO uint32_t SCK1B1 :1; + __IO uint32_t SIN2S0 :1; + __IO uint32_t SIN2S1 :1; + __IO uint32_t SOT2B0 :1; + __IO uint32_t SOT2B1 :1; + __IO uint32_t SCK2B0 :1; + __IO uint32_t SCK2B1 :1; + __IO uint32_t SIN3S0 :1; + __IO uint32_t SIN3S1 :1; + __IO uint32_t SOT3B0 :1; + __IO uint32_t SOT3B1 :1; + __IO uint32_t SCK3B0 :1; + __IO uint32_t SCK3B1 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_gpio_epfr07_field_t; + +typedef struct stc_gpio_epfr08_field +{ + union { + struct { + __IO uint32_t RTS4E :2; + __IO uint32_t CTS4S :2; + __IO uint32_t SIN4S :2; + __IO uint32_t SOT4B :2; + __IO uint32_t SCK4B :2; + __IO uint32_t SIN5S :2; + __IO uint32_t SOT5B :2; + __IO uint32_t SCK5B :2; + __IO uint32_t SIN6S :2; + __IO uint32_t SOT6B :2; + __IO uint32_t SCK6B :2; + __IO uint32_t SIN7S :2; + __IO uint32_t SOT7B :2; + __IO uint32_t SCK7B :2; + __IO uint32_t RTS5E :2; + __IO uint32_t CTS5S :2; + }; + struct { + __IO uint32_t RTS4E0 :1; + __IO uint32_t RTS4E1 :1; + __IO uint32_t CTS4S0 :1; + __IO uint32_t CTS4S1 :1; + __IO uint32_t SIN4S0 :1; + __IO uint32_t SIN4S1 :1; + __IO uint32_t SOT4B0 :1; + __IO uint32_t SOT4B1 :1; + __IO uint32_t SCK4B0 :1; + __IO uint32_t SCK4B1 :1; + __IO uint32_t SIN5S0 :1; + __IO uint32_t SIN5S1 :1; + __IO uint32_t SOT5B0 :1; + __IO uint32_t SOT5B1 :1; + __IO uint32_t SCK5B0 :1; + __IO uint32_t SCK5B1 :1; + __IO uint32_t SIN6S0 :1; + __IO uint32_t SIN6S1 :1; + __IO uint32_t SOT6B0 :1; + __IO uint32_t SOT6B1 :1; + __IO uint32_t SCK6B0 :1; + __IO uint32_t SCK6B1 :1; + __IO uint32_t SIN7S0 :1; + __IO uint32_t SIN7S1 :1; + __IO uint32_t SOT7B0 :1; + __IO uint32_t SOT7B1 :1; + __IO uint32_t SCK7B0 :1; + __IO uint32_t SCK7B1 :1; + __IO uint32_t RTS5E0 :1; + __IO uint32_t RTS5E1 :1; + __IO uint32_t CTS5S0 :1; + __IO uint32_t CTS5S1 :1; + }; + }; +} stc_gpio_epfr08_field_t; + +typedef struct stc_gpio_epfr09_field +{ + union { + struct { + __IO uint32_t QAIN0S :2; + __IO uint32_t QBIN0S :2; + __IO uint32_t QZIN0S :2; + __IO uint32_t QAIN1S :2; + __IO uint32_t QBIN1S :2; + __IO uint32_t QZIN1S :2; + __IO uint32_t ADTRG0S :4; + __IO uint32_t ADTRG1S :4; + __IO uint32_t ADTRG2S :4; + __IO uint32_t CRX0S :2; + __IO uint32_t CTX0E :2; + __IO uint32_t CRX1S :2; + __IO uint32_t CTX1E :2; + }; + struct { + __IO uint32_t QAIN0S0 :1; + __IO uint32_t QAIN0S1 :1; + __IO uint32_t QBIN0S0 :1; + __IO uint32_t QBIN0S1 :1; + __IO uint32_t QZIN0S0 :1; + __IO uint32_t QZIN0S1 :1; + __IO uint32_t QAIN1S0 :1; + __IO uint32_t QAIN1S1 :1; + __IO uint32_t QBIN1S0 :1; + __IO uint32_t QBIN1S1 :1; + __IO uint32_t QZIN1S0 :1; + __IO uint32_t QZIN1S1 :1; + __IO uint32_t ADTRG0S0 :1; + __IO uint32_t ADTRG0S1 :1; + __IO uint32_t ADTRG0S2 :1; + __IO uint32_t ADTRG0S3 :1; + __IO uint32_t ADTRG1S0 :1; + __IO uint32_t ADTRG1S1 :1; + __IO uint32_t ADTRG1S2 :1; + __IO uint32_t ADTRG1S3 :1; + __IO uint32_t ADTRG2S0 :1; + __IO uint32_t ADTRG2S1 :1; + __IO uint32_t ADTRG2S2 :1; + __IO uint32_t ADTRG2S3 :1; + __IO uint32_t CRX0S0 :1; + __IO uint32_t CRX0S1 :1; + __IO uint32_t CTX0E0 :1; + __IO uint32_t CTX0E1 :1; + __IO uint32_t CRX1S0 :1; + __IO uint32_t CRX1S1 :1; + __IO uint32_t CTX1E0 :1; + __IO uint32_t CTX1E1 :1; + }; + }; +} stc_gpio_epfr09_field_t; + +typedef struct stc_gpio_epfr10_field +{ + __IO uint32_t UEDEFB :1; + __IO uint32_t UEDTHB :1; + __IO uint32_t UECLKE :1; + __IO uint32_t UEWEXE :1; + __IO uint32_t UEDQME :1; + __IO uint32_t UEOEXE :1; + __IO uint32_t UEFLSE :1; + __IO uint32_t UECS1E :1; + __IO uint32_t UECS2E :1; + __IO uint32_t UECS3E :1; + __IO uint32_t UECS4E :1; + __IO uint32_t UECS5E :1; + __IO uint32_t UECS6E :1; + __IO uint32_t UECS7E :1; + __IO uint32_t UEAOOE :1; + __IO uint32_t UEA08E :1; + __IO uint32_t UEA09E :1; + __IO uint32_t UEA10E :1; + __IO uint32_t UEA11E :1; + __IO uint32_t UEA12E :1; + __IO uint32_t UEA13E :1; + __IO uint32_t UEA14E :1; + __IO uint32_t UEA15E :1; + __IO uint32_t UEA16E :1; + __IO uint32_t UEA17E :1; + __IO uint32_t UEA18E :1; + __IO uint32_t UEA19E :1; + __IO uint32_t UEA20E :1; + __IO uint32_t UEA21E :1; + __IO uint32_t UEA22E :1; + __IO uint32_t UEA23E :1; + __IO uint32_t UEA24E :1; +} stc_gpio_epfr10_field_t; + +typedef struct stc_gpio_epfr11_field +{ + __IO uint32_t UEALEE :1; + __IO uint32_t UECS0E :1; + __IO uint32_t UEA01E :1; + __IO uint32_t UEA02E :1; + __IO uint32_t UEA03E :1; + __IO uint32_t UEA04E :1; + __IO uint32_t UEA05E :1; + __IO uint32_t UEA06E :1; + __IO uint32_t UEA07E :1; + __IO uint32_t UED00B :1; + __IO uint32_t UED01B :1; + __IO uint32_t UED02B :1; + __IO uint32_t UED03B :1; + __IO uint32_t UED04B :1; + __IO uint32_t UED05B :1; + __IO uint32_t UED06B :1; + __IO uint32_t UED07B :1; + __IO uint32_t UED08B :1; + __IO uint32_t UED09B :1; + __IO uint32_t UED10B :1; + __IO uint32_t UED11B :1; + __IO uint32_t UED12B :1; + __IO uint32_t UED13B :1; + __IO uint32_t UED14B :1; + __IO uint32_t UED15B :1; + __IO uint32_t UERLC :1; + __IO uint32_t RESERVED0 :6; +} stc_gpio_epfr11_field_t; + +typedef struct stc_gpio_epfr12_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA8E :2; + __IO uint32_t TIOB8S :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TIOA9S :2; + __IO uint32_t TIOA9E :2; + __IO uint32_t TIOB9S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA10E :2; + __IO uint32_t TIOB10S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA11S :2; + __IO uint32_t TIOA11E :2; + __IO uint32_t TIOB11S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA8E0 :1; + __IO uint32_t TIOA8E1 :1; + __IO uint32_t TIOB8S0 :1; + __IO uint32_t TIOB8S1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TIOA9S0 :1; + __IO uint32_t TIOA9S1 :1; + __IO uint32_t TIOA9E0 :1; + __IO uint32_t TIOA9E1 :1; + __IO uint32_t TIOB9S0 :1; + __IO uint32_t TIOB9S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA10E0 :1; + __IO uint32_t TIOA10E1 :1; + __IO uint32_t TIOB10S0 :1; + __IO uint32_t TIOB10S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA11S0 :1; + __IO uint32_t TIOA11S1 :1; + __IO uint32_t TIOA11E0 :1; + __IO uint32_t TIOA11E1 :1; + __IO uint32_t TIOB11S0 :1; + __IO uint32_t TIOB11S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr12_field_t; + +typedef struct stc_gpio_epfr13_field +{ + union { + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TIOA12E :2; + __IO uint32_t TIOB12S :2; + __IO uint32_t RESERVED2 :2; + __IO uint32_t TIOA13S :2; + __IO uint32_t TIOA13E :2; + __IO uint32_t TIOB13S :2; + __IO uint32_t RESERVED4 :4; + __IO uint32_t TIOA14E :2; + __IO uint32_t TIOB14S :2; + __IO uint32_t RESERVED6 :2; + __IO uint32_t TIOA15S :2; + __IO uint32_t TIOA15E :2; + __IO uint32_t TIOB15S :2; + __IO uint32_t RESERVED8 :2; + }; + struct { + __IO uint32_t RESERVED1 :2; + __IO uint32_t TIOA12E0 :1; + __IO uint32_t TIOA12E1 :1; + __IO uint32_t TIOB12S0 :1; + __IO uint32_t TIOB12S1 :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TIOA13S0 :1; + __IO uint32_t TIOA13S1 :1; + __IO uint32_t TIOA13E0 :1; + __IO uint32_t TIOA13E1 :1; + __IO uint32_t TIOB13S0 :1; + __IO uint32_t TIOB13S1 :1; + __IO uint32_t RESERVED5 :4; + __IO uint32_t TIOA14E0 :1; + __IO uint32_t TIOA14E1 :1; + __IO uint32_t TIOB14S0 :1; + __IO uint32_t TIOB14S1 :1; + __IO uint32_t RESERVED7 :2; + __IO uint32_t TIOA15S0 :1; + __IO uint32_t TIOA15S1 :1; + __IO uint32_t TIOA15E0 :1; + __IO uint32_t TIOA15E1 :1; + __IO uint32_t TIOB15S0 :1; + __IO uint32_t TIOB15S1 :1; + __IO uint32_t RESERVED9 :2; + }; + }; +} stc_gpio_epfr13_field_t; + +typedef struct stc_gpio_epfr14_field +{ + union { + struct { + __IO uint32_t QAIN2S :2; + __IO uint32_t QBIN2S :2; + __IO uint32_t QZIN2S :2; + __IO uint32_t RESERVED0 :12; + __IO uint32_t E_TD0E :1; + __IO uint32_t E_TD1E :1; + __IO uint32_t E_TE0E :1; + __IO uint32_t E_TE1E :1; + __IO uint32_t E_MC0E :1; + __IO uint32_t E_MC1B :1; + __IO uint32_t E_MD0B :1; + __IO uint32_t E_MD1B :1; + __IO uint32_t E_CKE :1; + __IO uint32_t E_PSE :1; + __IO uint32_t E_SPLC :2; + __IO uint32_t RESERVED2 :2; + }; + struct { + __IO uint32_t QAIN2S0 :1; + __IO uint32_t QAIN2S1 :1; + __IO uint32_t QBIN2S0 :1; + __IO uint32_t QBIN2S1 :1; + __IO uint32_t QZIN2S0 :1; + __IO uint32_t QZIN2S1 :1; + __IO uint32_t RESERVED1 :22; + __IO uint32_t E_SPLC0 :1; + __IO uint32_t E_SPLC1 :1; + __IO uint32_t RESERVED3 :2; + }; + }; +} stc_gpio_epfr14_field_t; + +typedef struct stc_gpio_epfr15_field +{ + union { + struct { + __IO uint32_t EINT16S :2; + __IO uint32_t EINT17S :2; + __IO uint32_t EINT18S :2; + __IO uint32_t EINT19S :2; + __IO uint32_t EINT20S :2; + __IO uint32_t EINT21S :2; + __IO uint32_t EINT22S :2; + __IO uint32_t EINT23S :2; + __IO uint32_t EINT24S :2; + __IO uint32_t EINT25S :2; + __IO uint32_t EINT26S :2; + __IO uint32_t EINT27S :2; + __IO uint32_t EINT28S :2; + __IO uint32_t EINT29S :2; + __IO uint32_t EINT30S :2; + __IO uint32_t EINT31S :2; + }; + struct { + __IO uint32_t EINT16S0 :1; + __IO uint32_t EINT16S1 :1; + __IO uint32_t EINT17S0 :1; + __IO uint32_t EINT17S1 :1; + __IO uint32_t EINT18S0 :1; + __IO uint32_t EINT18S1 :1; + __IO uint32_t EINT19S0 :1; + __IO uint32_t EINT19S1 :1; + __IO uint32_t EINT20S0 :1; + __IO uint32_t EINT20S1 :1; + __IO uint32_t EINT21S0 :1; + __IO uint32_t EINT21S1 :1; + __IO uint32_t EINT22S0 :1; + __IO uint32_t EINT22S1 :1; + __IO uint32_t EINT23S0 :1; + __IO uint32_t EINT23S1 :1; + __IO uint32_t EINT24S0 :1; + __IO uint32_t EINT24S1 :1; + __IO uint32_t EINT25S0 :1; + __IO uint32_t EINT25S1 :1; + __IO uint32_t EINT26S0 :1; + __IO uint32_t EINT26S1 :1; + __IO uint32_t EINT27S0 :1; + __IO uint32_t EINT27S1 :1; + __IO uint32_t EINT28S0 :1; + __IO uint32_t EINT28S1 :1; + __IO uint32_t EINT29S0 :1; + __IO uint32_t EINT29S1 :1; + __IO uint32_t EINT30S0 :1; + __IO uint32_t EINT30S1 :1; + __IO uint32_t EINT31S0 :1; + __IO uint32_t EINT31S1 :1; + }; + }; +} stc_gpio_epfr15_field_t; + +typedef struct stc_gpio_epfr16_field +{ + union { + struct { + __IO uint32_t SCS6B :2; + __IO uint32_t SCS7B :2; + __IO uint32_t SIN8S :2; + __IO uint32_t SOT8B :2; + __IO uint32_t SCK8B :2; + __IO uint32_t SIN9S :2; + __IO uint32_t SOT9B :2; + __IO uint32_t SCK9B :2; + __IO uint32_t SIN10S :2; + __IO uint32_t SOT10B :2; + __IO uint32_t SCK10B :2; + __IO uint32_t SIN11S :2; + __IO uint32_t SOT11B :2; + __IO uint32_t SCK11B :2; + __IO uint32_t SFMPAC :1; + __IO uint32_t SFMPBC :1; + __IO uint32_t RESERVED0 :2; + }; + struct { + __IO uint32_t SCS6B0 :1; + __IO uint32_t SCS6B1 :1; + __IO uint32_t SCS7B0 :1; + __IO uint32_t SCS7B1 :1; + __IO uint32_t SIN8S0 :1; + __IO uint32_t SIN8S1 :1; + __IO uint32_t SOT8B0 :1; + __IO uint32_t SOT8B1 :1; + __IO uint32_t SCK8B0 :1; + __IO uint32_t SCK8B1 :1; + __IO uint32_t SIN9S0 :1; + __IO uint32_t SIN9S1 :1; + __IO uint32_t SOT9B0 :1; + __IO uint32_t SOT9B1 :1; + __IO uint32_t SCK9B0 :1; + __IO uint32_t SCK9B1 :1; + __IO uint32_t SIN10S0 :1; + __IO uint32_t SIN10S1 :1; + __IO uint32_t SOT10B0 :1; + __IO uint32_t SOT10B1 :1; + __IO uint32_t SCK10B0 :1; + __IO uint32_t SCK10B1 :1; + __IO uint32_t SIN11S0 :1; + __IO uint32_t SIN11S1 :1; + __IO uint32_t SOT11B0 :1; + __IO uint32_t SOT11B1 :1; + __IO uint32_t SCK11B0 :1; + __IO uint32_t SCK11B1 :1; + __IO uint32_t RESERVED1 :4; + }; + }; +} stc_gpio_epfr16_field_t; + +typedef struct stc_gpio_epfr17_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t SIN12S :2; + __IO uint32_t SOT12B :2; + __IO uint32_t SCK12B :2; + __IO uint32_t SIN13S :2; + __IO uint32_t SOT13B :2; + __IO uint32_t SCK13B :2; + __IO uint32_t SIN14S :2; + __IO uint32_t SOT14B :2; + __IO uint32_t SCK14B :2; + __IO uint32_t SIN15S :2; + __IO uint32_t SOT15B :2; + __IO uint32_t SCK15B :2; + __IO uint32_t RESERVED2 :4; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t SIN12S0 :1; + __IO uint32_t SIN12S1 :1; + __IO uint32_t SOT12B0 :1; + __IO uint32_t SOT12B1 :1; + __IO uint32_t SCK12B0 :1; + __IO uint32_t SCK12B1 :1; + __IO uint32_t SIN13S0 :1; + __IO uint32_t SIN13S1 :1; + __IO uint32_t SOT13B0 :1; + __IO uint32_t SOT13B1 :1; + __IO uint32_t SCK13B0 :1; + __IO uint32_t SCK13B1 :1; + __IO uint32_t SIN14S0 :1; + __IO uint32_t SIN14S1 :1; + __IO uint32_t SOT14B0 :1; + __IO uint32_t SOT14B1 :1; + __IO uint32_t SCK14B0 :1; + __IO uint32_t SCK14B1 :1; + __IO uint32_t SIN15S0 :1; + __IO uint32_t SIN15S1 :1; + __IO uint32_t SOT15B0 :1; + __IO uint32_t SOT15B1 :1; + __IO uint32_t SCK15B0 :1; + __IO uint32_t SCK15B1 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_gpio_epfr17_field_t; + +typedef struct stc_gpio_epfr18_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t QAIN3S :2; + __IO uint32_t QBIN3S :2; + __IO uint32_t QZIN3S :2; + __IO uint32_t RESERVED2 :4; + __IO uint32_t SDCLKE :2; + __IO uint32_t SDCMDB :2; + __IO uint32_t SDDATA0B :2; + __IO uint32_t SDDATA1B :2; + __IO uint32_t SDDATA2B :2; + __IO uint32_t SDDATA3B :2; + __IO uint32_t SDCDS :2; + __IO uint32_t SDWPS :2; + __IO uint32_t RESERVED4 :2; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t QAIN3S0 :1; + __IO uint32_t QAIN3S1 :1; + __IO uint32_t QBIN3S0 :1; + __IO uint32_t QBIN3S1 :1; + __IO uint32_t QZIN3S0 :1; + __IO uint32_t QZIN3S1 :1; + __IO uint32_t RESERVED3 :4; + __IO uint32_t SDCLKE0 :1; + __IO uint32_t SDCLKE1 :1; + __IO uint32_t SDCMDB0 :1; + __IO uint32_t SDCMDB1 :1; + __IO uint32_t SDDATA0B0 :1; + __IO uint32_t SDDATA0B1 :1; + __IO uint32_t SDDATA1B0 :1; + __IO uint32_t SDDATA1B1 :1; + __IO uint32_t SDDATA2B0 :1; + __IO uint32_t SDDATA2B1 :1; + __IO uint32_t SDDATA3B0 :1; + __IO uint32_t SDDATA3B1 :1; + __IO uint32_t SDCDS0 :1; + __IO uint32_t SDCDS1 :1; + __IO uint32_t SDWPS0 :1; + __IO uint32_t SDWPS1 :1; + __IO uint32_t RESERVED5 :2; + }; + }; +} stc_gpio_epfr18_field_t; + +typedef struct stc_gpio_epfr20_field +{ + __IO uint32_t UESMCKE :1; + __IO uint32_t UESMCEE :1; + __IO uint32_t UERASE :1; + __IO uint32_t UECASE :1; + __IO uint32_t UEDWEXE :1; + __IO uint32_t UECSXE :1; + __IO uint32_t UEDQM2E :1; + __IO uint32_t UEDQM3E :1; + __IO uint32_t UEDTHHB :1; + __IO uint32_t UED16B :1; + __IO uint32_t UED17B :1; + __IO uint32_t UED18B :1; + __IO uint32_t UED19B :1; + __IO uint32_t UED20B :1; + __IO uint32_t UED21B :1; + __IO uint32_t UED22B :1; + __IO uint32_t UED23B :1; + __IO uint32_t UED24B :1; + __IO uint32_t UED25B :1; + __IO uint32_t UED26B :1; + __IO uint32_t UED27B :1; + __IO uint32_t UED28B :1; + __IO uint32_t UED29B :1; + __IO uint32_t UED30B :1; + __IO uint32_t UED31B :1; + __IO uint32_t RESERVED0 :7; +} stc_gpio_epfr20_field_t; + +typedef struct stc_gpio_epfr23_field +{ + union { + struct { + __IO uint32_t SCS60E :2; + __IO uint32_t SCS61E :2; + __IO uint32_t SCS62E :2; + __IO uint32_t SCS63E :2; + __IO uint32_t SCS70E :2; + __IO uint32_t SCS71E :2; + __IO uint32_t SCS72E :2; + __IO uint32_t SCS73E :2; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t SCS60E0 :1; + __IO uint32_t SCS60E1 :1; + __IO uint32_t SCS61E0 :1; + __IO uint32_t SCS61E1 :1; + __IO uint32_t SCS62E0 :1; + __IO uint32_t SCS62E1 :1; + __IO uint32_t SCS63E0 :1; + __IO uint32_t SCS63E1 :1; + __IO uint32_t SCS70E0 :1; + __IO uint32_t SCS70E1 :1; + __IO uint32_t SCS71E0 :1; + __IO uint32_t SCS71E1 :1; + __IO uint32_t SCS72E0 :1; + __IO uint32_t SCS72E1 :1; + __IO uint32_t SCS73E0 :1; + __IO uint32_t SCS73E1 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_gpio_epfr23_field_t; + +typedef struct stc_gpio_epfr24_field +{ + union { + struct { + __IO uint32_t I2SM4_MCLK0S :2; + __IO uint32_t I2SM4_MCLK0E :2; + __IO uint32_t I2SM4_SCK0B :2; + __IO uint32_t I2SM4_WS0B :2; + __IO uint32_t I2SM4_SDI0S :2; + __IO uint32_t I2SM4_SDO0E :2; + __IO uint32_t RESERVED0 :4; + __IO uint32_t I2SM4_MCLK1S :2; + __IO uint32_t I2SM4_MCLK1E :2; + __IO uint32_t I2SM4_SCK1B :2; + __IO uint32_t I2SM4_WS1B :2; + __IO uint32_t I2SM4_SDI1S :2; + __IO uint32_t I2SM4_SDO1E :2; + __IO uint32_t RESERVED2 :4; + }; + struct { + __IO uint32_t I2SM4_MCLK0S0 :1; + __IO uint32_t I2SM4_MCLK0S1 :1; + __IO uint32_t I2SM4_MCLK0E0 :1; + __IO uint32_t I2SM4_MCLK0E1 :1; + __IO uint32_t I2SM4_SCK0B0 :1; + __IO uint32_t I2SM4_SCK0B1 :1; + __IO uint32_t I2SM4_WS0B0 :1; + __IO uint32_t I2SM4_WS0B1 :1; + __IO uint32_t I2SM4_SDI0S0 :1; + __IO uint32_t I2SM4_SDI0S1 :1; + __IO uint32_t I2SM4_SDO0E0 :1; + __IO uint32_t I2SM4_SDO0E1 :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t I2SM4_MCLK1S0 :1; + __IO uint32_t I2SM4_MCLK1S1 :1; + __IO uint32_t I2SM4_MCLK1E0 :1; + __IO uint32_t I2SM4_MCLK1E1 :1; + __IO uint32_t I2SM4_SCK1B0 :1; + __IO uint32_t I2SM4_SCK1B1 :1; + __IO uint32_t I2SM4_WS1B0 :1; + __IO uint32_t I2SM4_WS1B1 :1; + __IO uint32_t I2SM4_SDI1S0 :1; + __IO uint32_t I2SM4_SDI1S1 :1; + __IO uint32_t I2SM4_SDO1E0 :1; + __IO uint32_t I2SM4_SDO1E1 :1; + __IO uint32_t RESERVED3 :4; + }; + }; +} stc_gpio_epfr24_field_t; + +typedef struct stc_gpio_epfr25_field +{ + union { + struct { + __IO uint32_t MCRX2S :2; + __IO uint32_t MCTX2E :2; + __IO uint32_t RESERVED0 :28; + }; + struct { + __IO uint32_t MCRX2S0 :1; + __IO uint32_t MCRX2S1 :1; + __IO uint32_t MCTX2E0 :1; + __IO uint32_t MCTX2E1 :1; + __IO uint32_t RESERVED1 :28; + }; + }; +} stc_gpio_epfr25_field_t; + +typedef struct stc_gpio_epfr26_field +{ + union { + struct { + __IO uint32_t Q_SCKB :2; + __IO uint32_t Q_CS0E :2; + __IO uint32_t Q_CS1E :2; + __IO uint32_t Q_CS2E :2; + __IO uint32_t Q_CS3E :2; + __IO uint32_t Q_IO0B :2; + __IO uint32_t Q_IO1B :2; + __IO uint32_t Q_IO2B :2; + __IO uint32_t Q_IO3B :2; + __IO uint32_t RESERVED0 :14; + }; + struct { + __IO uint32_t Q_SCKB0 :1; + __IO uint32_t Q_SCKB1 :1; + __IO uint32_t Q_CS0E0 :1; + __IO uint32_t Q_CS0E1 :1; + __IO uint32_t Q_CS1E0 :1; + __IO uint32_t Q_CS1E1 :1; + __IO uint32_t Q_CS2E0 :1; + __IO uint32_t Q_CS2E1 :1; + __IO uint32_t Q_CS3E0 :1; + __IO uint32_t Q_CS3E1 :1; + __IO uint32_t Q_IO0B0 :1; + __IO uint32_t Q_IO0B1 :1; + __IO uint32_t Q_IO1B0 :1; + __IO uint32_t Q_IO1B1 :1; + __IO uint32_t Q_IO2B0 :1; + __IO uint32_t Q_IO2B1 :1; + __IO uint32_t Q_IO3B0 :1; + __IO uint32_t Q_IO3B1 :1; + __IO uint32_t RESERVED1 :14; + }; + }; +} stc_gpio_epfr26_field_t; + +typedef struct stc_gpio_pzr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pzr0_field_t; + +typedef struct stc_gpio_pzr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzr1_field_t; + +typedef struct stc_gpio_pzr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pzr2_field_t; + +typedef struct stc_gpio_pzr3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pzr3_field_t; + +typedef struct stc_gpio_pzr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pzr4_field_t; + +typedef struct stc_gpio_pzr5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzr5_field_t; + +typedef struct stc_gpio_pzr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pzr6_field_t; + +typedef struct stc_gpio_pzr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pzr7_field_t; + +typedef struct stc_gpio_pzr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pzr8_field_t; + +typedef struct stc_gpio_pzr9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_pzr9_field_t; + +typedef struct stc_gpio_pzra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzra_field_t; + +typedef struct stc_gpio_pzrb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzrb_field_t; + +typedef struct stc_gpio_pzrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pzrc_field_t; + +typedef struct stc_gpio_pzrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pzrd_field_t; + +typedef struct stc_gpio_pzre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pzre_field_t; + +typedef struct stc_gpio_pzrf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_pzrf_field_t; + +typedef struct stc_gpio_pdsr0_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t RESERVED0 :3; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED1 :21; +} stc_gpio_pdsr0_field_t; + +typedef struct stc_gpio_pdsr1_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsr1_field_t; + +typedef struct stc_gpio_pdsr2_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t RESERVED0 :21; +} stc_gpio_pdsr2_field_t; + +typedef struct stc_gpio_pdsr3_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdsr3_field_t; + +typedef struct stc_gpio_pdsr4_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdsr4_field_t; + +typedef struct stc_gpio_pdsr5_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsr5_field_t; + +typedef struct stc_gpio_pdsr6_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdsr6_field_t; + +typedef struct stc_gpio_pdsr7_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t RESERVED0 :17; +} stc_gpio_pdsr7_field_t; + +typedef struct stc_gpio_pdsr8_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED0 :28; +} stc_gpio_pdsr8_field_t; + +typedef struct stc_gpio_pdsr9_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t RESERVED0 :24; +} stc_gpio_pdsr9_field_t; + +typedef struct stc_gpio_pdsra_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsra_field_t; + +typedef struct stc_gpio_pdsrb_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsrb_field_t; + +typedef struct stc_gpio_pdsrc_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t PD :1; + __IO uint32_t PE :1; + __IO uint32_t PF :1; + __IO uint32_t RESERVED0 :16; +} stc_gpio_pdsrc_field_t; + +typedef struct stc_gpio_pdsrd_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t RESERVED0 :29; +} stc_gpio_pdsrd_field_t; + +typedef struct stc_gpio_pdsre_field +{ + __IO uint32_t P0 :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t RESERVED1 :28; +} stc_gpio_pdsre_field_t; + +typedef struct stc_gpio_pdsrf_field +{ + __IO uint32_t P0 :1; + __IO uint32_t P1 :1; + __IO uint32_t P2 :1; + __IO uint32_t P3 :1; + __IO uint32_t P4 :1; + __IO uint32_t P5 :1; + __IO uint32_t P6 :1; + __IO uint32_t P7 :1; + __IO uint32_t P8 :1; + __IO uint32_t P9 :1; + __IO uint32_t PA :1; + __IO uint32_t PB :1; + __IO uint32_t PC :1; + __IO uint32_t RESERVED0 :19; +} stc_gpio_pdsrf_field_t; + +/******************************************************************************* +* HSSPI_MODULE +*******************************************************************************/ +typedef struct stc_hsspi_mctrl_field +{ + __IO uint32_t MEN :1; + __IO uint32_t CSEN :1; + __IO uint32_t RESERVED0 :2; + __IO uint32_t MES :1; + __IO uint32_t SYNCON :1; + __IO uint32_t RESERVED1 :26; +} stc_hsspi_mctrl_field_t; + +typedef struct stc_hsspi_pcc0_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc0_field_t; + +typedef struct stc_hsspi_pcc1_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc1_field_t; + +typedef struct stc_hsspi_pcc2_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc2_field_t; + +typedef struct stc_hsspi_pcc3_field +{ + union { + struct { + __IO uint32_t CPHA :1; + __IO uint32_t CPOL :1; + __IO uint32_t ACES :1; + __IO uint32_t RTM :1; + __IO uint32_t SSPOL :1; + __IO uint32_t SS2CD :2; + __IO uint32_t SDIR :1; + __IO uint32_t SENDIAN :1; + __IO uint32_t CDRS :7; + __IO uint32_t SAFESYNC :1; + __IO uint32_t WRDSEL :4; + __IO uint32_t RDDSEL :2; + __IO uint32_t RESERVED3 :9; + }; + struct { + __IO uint32_t RESERVED0 :5; + __IO uint32_t SS2CD0 :1; + __IO uint32_t SS2CD1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t CDRS0 :1; + __IO uint32_t CDRS1 :1; + __IO uint32_t CDRS2 :1; + __IO uint32_t CDRS3 :1; + __IO uint32_t CDRS4 :1; + __IO uint32_t CDRS5 :1; + __IO uint32_t CDRS6 :1; + __IO uint32_t RESERVED2 :1; + __IO uint32_t WRDSEL0 :1; + __IO uint32_t WRDSEL1 :1; + __IO uint32_t WRDSEL2 :1; + __IO uint32_t WRDSEL3 :1; + __IO uint32_t RDDSEL0 :1; + __IO uint32_t RDDSEL1 :1; + __IO uint32_t RESERVED4 :9; + }; + }; +} stc_hsspi_pcc3_field_t; + +typedef struct stc_hsspi_txf_field +{ + __IO uint32_t TFFS :1; + __IO uint32_t TFES :1; + __IO uint32_t TFOS :1; + __IO uint32_t TFUS :1; + __IO uint32_t TFLETS :1; + __IO uint32_t TFMTS :1; + __IO uint32_t TSSRS :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_txf_field_t; + +typedef struct stc_hsspi_txe_field +{ + __IO uint32_t TFFE :1; + __IO uint32_t TFEE :1; + __IO uint32_t TFOE :1; + __IO uint32_t TFUE :1; + __IO uint32_t TFLETE :1; + __IO uint32_t TFMTE :1; + __IO uint32_t TSSRE :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_txe_field_t; + +typedef struct stc_hsspi_txc_field +{ + __IO uint32_t TFFC :1; + __IO uint32_t TFEC :1; + __IO uint32_t TFOC :1; + __IO uint32_t TFUC :1; + __IO uint32_t TFLETC :1; + __IO uint32_t TFMTC :1; + __IO uint32_t TSSRC :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_txc_field_t; + +typedef struct stc_hsspi_rxf_field +{ + __IO uint32_t RFFS :1; + __IO uint32_t RFES :1; + __IO uint32_t RFOS :1; + __IO uint32_t RFUS :1; + __IO uint32_t RFLETS :1; + __IO uint32_t RFMTS :1; + __IO uint32_t RSSRS :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_rxf_field_t; + +typedef struct stc_hsspi_rxe_field +{ + __IO uint32_t RFFE :1; + __IO uint32_t RFEE :1; + __IO uint32_t RFOE :1; + __IO uint32_t RFUE :1; + __IO uint32_t RFLETE :1; + __IO uint32_t RFMTE :1; + __IO uint32_t RSSRE :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_rxe_field_t; + +typedef struct stc_hsspi_rxc_field +{ + __IO uint32_t RFFC :1; + __IO uint32_t RFEC :1; + __IO uint32_t RFOC :1; + __IO uint32_t RFUC :1; + __IO uint32_t RFLETC :1; + __IO uint32_t RFMTC :1; + __IO uint32_t RSSRC :1; + __IO uint32_t RESERVED0 :25; +} stc_hsspi_rxc_field_t; + +typedef struct stc_hsspi_faultf_field +{ + __IO uint32_t UMAFS :1; + __IO uint32_t WAFS :1; + __IO uint32_t PVFS :1; + __IO uint32_t DWCBSFS :1; + __IO uint32_t DRCBSFS :1; + __IO uint32_t RESERVED0 :27; +} stc_hsspi_faultf_field_t; + +typedef struct stc_hsspi_faultc_field +{ + __IO uint32_t UMAFC :1; + __IO uint32_t WAFC :1; + __IO uint32_t PVFC :1; + __IO uint32_t DWCBSFC :1; + __IO uint32_t DRCBSFC :1; + __IO uint32_t RESERVED0 :27; +} stc_hsspi_faultc_field_t; + +typedef struct stc_hsspi_dmcfg_field +{ + __IO uint8_t RESERVED0 :1; + __IO uint8_t SSDC :1; + __IO uint8_t RESERVED1 :6; +} stc_hsspi_dmcfg_field_t; + +typedef struct stc_hsspi_dmdmaen_field +{ + __IO uint8_t RXDMAEN :1; + __IO uint8_t TXDMAEN :1; + __IO uint8_t RESERVED0 :6; +} stc_hsspi_dmdmaen_field_t; + +typedef struct stc_hsspi_dmstart_field +{ + __IO uint8_t START :1; + __IO uint8_t RESERVED0 :7; +} stc_hsspi_dmstart_field_t; + +typedef struct stc_hsspi_dmstop_field +{ + __IO uint8_t STOP :1; + __IO uint8_t RESERVED0 :7; +} stc_hsspi_dmstop_field_t; + +typedef struct stc_hsspi_dmpsel_field +{ + union { + struct { + __IO uint8_t PSEL :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t PSEL0 :1; + __IO uint8_t PSEL1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_hsspi_dmpsel_field_t; + +typedef struct stc_hsspi_dmtrp_field +{ + union { + struct { + __IO uint8_t TRP :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t TRP0 :1; + __IO uint8_t TRP1 :1; + __IO uint8_t TRP2 :1; + __IO uint8_t TRP3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_hsspi_dmtrp_field_t; + +typedef struct stc_hsspi_dmbcc_field +{ + union { + struct { + __IO uint16_t BCC :16; + }; + struct { + __IO uint16_t BCC0 :1; + __IO uint16_t BCC1 :1; + __IO uint16_t BCC2 :1; + __IO uint16_t BCC3 :1; + __IO uint16_t BCC4 :1; + __IO uint16_t BCC5 :1; + __IO uint16_t BCC6 :1; + __IO uint16_t BCC7 :1; + __IO uint16_t BCC8 :1; + __IO uint16_t BCC9 :1; + __IO uint16_t BCC10 :1; + __IO uint16_t BCC11 :1; + __IO uint16_t BCC12 :1; + __IO uint16_t BCC13 :1; + __IO uint16_t BCC14 :1; + __IO uint16_t BCC15 :1; + }; + }; +} stc_hsspi_dmbcc_field_t; + +typedef struct stc_hsspi_dmbcs_field +{ + union { + struct { + __IO uint16_t BCS :16; + }; + struct { + __IO uint16_t BCS0 :1; + __IO uint16_t BCS1 :1; + __IO uint16_t BCS2 :1; + __IO uint16_t BCS3 :1; + __IO uint16_t BCS4 :1; + __IO uint16_t BCS5 :1; + __IO uint16_t BCS6 :1; + __IO uint16_t BCS7 :1; + __IO uint16_t BCS8 :1; + __IO uint16_t BCS9 :1; + __IO uint16_t BCS10 :1; + __IO uint16_t BCS11 :1; + __IO uint16_t BCS12 :1; + __IO uint16_t BCS13 :1; + __IO uint16_t BCS14 :1; + __IO uint16_t BCS15 :1; + }; + }; +} stc_hsspi_dmbcs_field_t; + +typedef struct stc_hsspi_dmstatus_field +{ + union { + struct { + __IO uint32_t RXACTIVE :1; + __IO uint32_t TXACTIVE :1; + __IO uint32_t RESERVED0 :6; + __IO uint32_t RXFLEVEL :5; + __IO uint32_t RESERVED2 :3; + __IO uint32_t TXFLEVEL :5; + __IO uint32_t RESERVED4 :11; + }; + struct { + __IO uint32_t RESERVED1 :8; + __IO uint32_t RXFLEVEL0 :1; + __IO uint32_t RXFLEVEL1 :1; + __IO uint32_t RXFLEVEL2 :1; + __IO uint32_t RXFLEVEL3 :1; + __IO uint32_t RXFLEVEL4 :1; + __IO uint32_t RESERVED3 :3; + __IO uint32_t TXFLEVEL0 :1; + __IO uint32_t TXFLEVEL1 :1; + __IO uint32_t TXFLEVEL2 :1; + __IO uint32_t TXFLEVEL3 :1; + __IO uint32_t TXFLEVEL4 :1; + __IO uint32_t RESERVED5 :11; + }; + }; +} stc_hsspi_dmstatus_field_t; + +typedef struct stc_hsspi_fifocfg_field +{ + union { + struct { + __IO uint32_t RXFTH :4; + __IO uint32_t TXFTH :4; + __IO uint32_t FWIDTH :2; + __IO uint32_t TXCTRL :1; + __IO uint32_t RXFLSH :1; + __IO uint32_t TXFLSH :1; + __IO uint32_t RESERVED0 :19; + }; + struct { + __IO uint32_t RXFTH0 :1; + __IO uint32_t RXFTH1 :1; + __IO uint32_t RXFTH2 :1; + __IO uint32_t RXFTH3 :1; + __IO uint32_t TXFTH0 :1; + __IO uint32_t TXFTH1 :1; + __IO uint32_t TXFTH2 :1; + __IO uint32_t TXFTH3 :1; + __IO uint32_t FWIDTH0 :1; + __IO uint32_t FWIDTH1 :1; + __IO uint32_t RESERVED1 :22; + }; + }; +} stc_hsspi_fifocfg_field_t; + +typedef struct stc_hsspi_txfifo0_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo0_field_t; + +typedef struct stc_hsspi_txfifo1_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo1_field_t; + +typedef struct stc_hsspi_txfifo2_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo2_field_t; + +typedef struct stc_hsspi_txfifo3_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo3_field_t; + +typedef struct stc_hsspi_txfifo4_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo4_field_t; + +typedef struct stc_hsspi_txfifo5_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo5_field_t; + +typedef struct stc_hsspi_txfifo6_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo6_field_t; + +typedef struct stc_hsspi_txfifo7_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo7_field_t; + +typedef struct stc_hsspi_txfifo8_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo8_field_t; + +typedef struct stc_hsspi_txfifo9_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo9_field_t; + +typedef struct stc_hsspi_txfifo10_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo10_field_t; + +typedef struct stc_hsspi_txfifo11_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo11_field_t; + +typedef struct stc_hsspi_txfifo12_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo12_field_t; + +typedef struct stc_hsspi_txfifo13_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo13_field_t; + +typedef struct stc_hsspi_txfifo14_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo14_field_t; + +typedef struct stc_hsspi_txfifo15_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_hsspi_txfifo15_field_t; + +typedef struct stc_hsspi_rxfifo0_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo0_field_t; + +typedef struct stc_hsspi_rxfifo1_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo1_field_t; + +typedef struct stc_hsspi_rxfifo2_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo2_field_t; + +typedef struct stc_hsspi_rxfifo3_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo3_field_t; + +typedef struct stc_hsspi_rxfifo4_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo4_field_t; + +typedef struct stc_hsspi_rxfifo5_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo5_field_t; + +typedef struct stc_hsspi_rxfifo6_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo6_field_t; + +typedef struct stc_hsspi_rxfifo7_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo7_field_t; + +typedef struct stc_hsspi_rxfifo8_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo8_field_t; + +typedef struct stc_hsspi_rxfifo9_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo9_field_t; + +typedef struct stc_hsspi_rxfifo10_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo10_field_t; + +typedef struct stc_hsspi_rxfifo11_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo11_field_t; + +typedef struct stc_hsspi_rxfifo12_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo12_field_t; + +typedef struct stc_hsspi_rxfifo13_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo13_field_t; + +typedef struct stc_hsspi_rxfifo14_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo14_field_t; + +typedef struct stc_hsspi_rxfifo15_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_hsspi_rxfifo15_field_t; + +typedef struct stc_hsspi_cscfg_field +{ + union { + struct { + __IO uint32_t SRAM :1; + __IO uint32_t MBM :2; + __IO uint32_t RESERVED1 :5; + __IO uint32_t SSEL0EN :1; + __IO uint32_t SSEL1EN :1; + __IO uint32_t SSEL2EN :1; + __IO uint32_t SSEL3EN :1; + __IO uint32_t RESERVED2 :4; + __IO uint32_t MSEL :4; + __IO uint32_t RESERVED4 :12; + }; + struct { + __IO uint32_t RESERVED0 :1; + __IO uint32_t MBM0 :1; + __IO uint32_t MBM1 :1; + __IO uint32_t RESERVED3 :13; + __IO uint32_t MSEL0 :1; + __IO uint32_t MSEL1 :1; + __IO uint32_t MSEL2 :1; + __IO uint32_t MSEL3 :1; + __IO uint32_t RESERVED5 :12; + }; + }; +} stc_hsspi_cscfg_field_t; + +typedef struct stc_hsspi_csitime_field +{ + union { + struct { + __IO uint32_t ITIME :16; + __IO uint32_t RESERVED0 :16; + }; + struct { + __IO uint32_t ITIME0 :1; + __IO uint32_t ITIME1 :1; + __IO uint32_t ITIME2 :1; + __IO uint32_t ITIME3 :1; + __IO uint32_t ITIME4 :1; + __IO uint32_t ITIME5 :1; + __IO uint32_t ITIME6 :1; + __IO uint32_t ITIME7 :1; + __IO uint32_t ITIME8 :1; + __IO uint32_t ITIME9 :1; + __IO uint32_t ITIME10 :1; + __IO uint32_t ITIME11 :1; + __IO uint32_t ITIME12 :1; + __IO uint32_t ITIME13 :1; + __IO uint32_t ITIME14 :1; + __IO uint32_t ITIME15 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_hsspi_csitime_field_t; + +typedef struct stc_hsspi_csaext_field +{ + union { + struct { + __IO uint32_t RESERVED0 :13; + __IO uint32_t AEXT :19; + }; + struct { + __IO uint32_t RESERVED1 :13; + __IO uint32_t AEXT0 :1; + __IO uint32_t AEXT1 :1; + __IO uint32_t AEXT2 :1; + __IO uint32_t AEXT3 :1; + __IO uint32_t AEXT4 :1; + __IO uint32_t AEXT5 :1; + __IO uint32_t AEXT6 :1; + __IO uint32_t AEXT7 :1; + __IO uint32_t AEXT8 :1; + __IO uint32_t AEXT9 :1; + __IO uint32_t AEXT10 :1; + __IO uint32_t AEXT11 :1; + __IO uint32_t AEXT12 :1; + __IO uint32_t AEXT13 :1; + __IO uint32_t AEXT14 :1; + __IO uint32_t AEXT15 :1; + __IO uint32_t AEXT16 :1; + __IO uint32_t AEXT17 :1; + __IO uint32_t AEXT18 :1; + }; + }; +} stc_hsspi_csaext_field_t; + +typedef struct stc_hsspi_rdcsdc0_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc0_field_t; + +typedef struct stc_hsspi_rdcsdc1_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc1_field_t; + +typedef struct stc_hsspi_rdcsdc2_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc2_field_t; + +typedef struct stc_hsspi_rdcsdc3_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc3_field_t; + +typedef struct stc_hsspi_rdcsdc4_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc4_field_t; + +typedef struct stc_hsspi_rdcsdc5_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc5_field_t; + +typedef struct stc_hsspi_rdcsdc6_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc6_field_t; + +typedef struct stc_hsspi_rdcsdc7_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t RDCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t RDCSDATA0 :1; + __IO uint16_t RDCSDATA1 :1; + __IO uint16_t RDCSDATA2 :1; + __IO uint16_t RDCSDATA3 :1; + __IO uint16_t RDCSDATA4 :1; + __IO uint16_t RDCSDATA5 :1; + __IO uint16_t RDCSDATA6 :1; + __IO uint16_t RDCSDATA7 :1; + }; + }; +} stc_hsspi_rdcsdc7_field_t; + +typedef struct stc_hsspi_wrcsdc0_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc0_field_t; + +typedef struct stc_hsspi_wrcsdc1_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc1_field_t; + +typedef struct stc_hsspi_wrcsdc2_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc2_field_t; + +typedef struct stc_hsspi_wrcsdc3_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc3_field_t; + +typedef struct stc_hsspi_wrcsdc4_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc4_field_t; + +typedef struct stc_hsspi_wrcsdc5_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc5_field_t; + +typedef struct stc_hsspi_wrcsdc6_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc6_field_t; + +typedef struct stc_hsspi_wrcsdc7_field +{ + union { + struct { + __IO uint16_t DEC :1; + __IO uint16_t TRP :2; + __IO uint16_t CONT :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t WRCSDATA :8; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TRP0 :1; + __IO uint16_t TRP1 :1; + __IO uint16_t RESERVED2 :5; + __IO uint16_t WRCSDATA0 :1; + __IO uint16_t WRCSDATA1 :1; + __IO uint16_t WRCSDATA2 :1; + __IO uint16_t WRCSDATA3 :1; + __IO uint16_t WRCSDATA4 :1; + __IO uint16_t WRCSDATA5 :1; + __IO uint16_t WRCSDATA6 :1; + __IO uint16_t WRCSDATA7 :1; + }; + }; +} stc_hsspi_wrcsdc7_field_t; + +typedef struct stc_hsspi_mid_field +{ + union { + struct { + __IO uint32_t MID :32; + }; + struct { + __IO uint32_t MID0 :1; + __IO uint32_t MID1 :1; + __IO uint32_t MID2 :1; + __IO uint32_t MID3 :1; + __IO uint32_t MID4 :1; + __IO uint32_t MID5 :1; + __IO uint32_t MID6 :1; + __IO uint32_t MID7 :1; + __IO uint32_t MID8 :1; + __IO uint32_t MID9 :1; + __IO uint32_t MID10 :1; + __IO uint32_t MID11 :1; + __IO uint32_t MID12 :1; + __IO uint32_t MID13 :1; + __IO uint32_t MID14 :1; + __IO uint32_t MID15 :1; + __IO uint32_t MID16 :1; + __IO uint32_t MID17 :1; + __IO uint32_t MID18 :1; + __IO uint32_t MID19 :1; + __IO uint32_t MID20 :1; + __IO uint32_t MID21 :1; + __IO uint32_t MID22 :1; + __IO uint32_t MID23 :1; + __IO uint32_t MID24 :1; + __IO uint32_t MID25 :1; + __IO uint32_t MID26 :1; + __IO uint32_t MID27 :1; + __IO uint32_t MID28 :1; + __IO uint32_t MID29 :1; + __IO uint32_t MID30 :1; + __IO uint32_t MID31 :1; + }; + }; +} stc_hsspi_mid_field_t; + +typedef struct stc_hsspi_qdclkr_field +{ + union { + struct { + __IO uint8_t QHDIV :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t QHDIV0 :1; + __IO uint8_t QHDIV1 :1; + __IO uint8_t QHDIV2 :1; + __IO uint8_t QHDIV3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_hsspi_qdclkr_field_t; + +typedef struct stc_hsspi_dbcnt_field +{ + __IO uint8_t RXDBEN :1; + __IO uint8_t TXDBEN :1; + __IO uint8_t RESERVED0 :6; +} stc_hsspi_dbcnt_field_t; + +/******************************************************************************* +* HWWDT_MODULE +*******************************************************************************/ +typedef struct stc_hwwdt_wdg_ctl_field +{ + __IO uint32_t INTEN :1; + __IO uint32_t RESEN :1; + __IO uint32_t RESERVED0 :30; +} stc_hwwdt_wdg_ctl_field_t; + +typedef struct stc_hwwdt_wdg_ris_field +{ + __IO uint32_t RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_hwwdt_wdg_ris_field_t; + +/******************************************************************************* +* I2S_MODULE +*******************************************************************************/ +typedef struct stc_i2s_rxfdat_field +{ + union { + struct { + __IO uint32_t RXDATA :32; + }; + struct { + __IO uint32_t RXDATA0 :1; + __IO uint32_t RXDATA1 :1; + __IO uint32_t RXDATA2 :1; + __IO uint32_t RXDATA3 :1; + __IO uint32_t RXDATA4 :1; + __IO uint32_t RXDATA5 :1; + __IO uint32_t RXDATA6 :1; + __IO uint32_t RXDATA7 :1; + __IO uint32_t RXDATA8 :1; + __IO uint32_t RXDATA9 :1; + __IO uint32_t RXDATA10 :1; + __IO uint32_t RXDATA11 :1; + __IO uint32_t RXDATA12 :1; + __IO uint32_t RXDATA13 :1; + __IO uint32_t RXDATA14 :1; + __IO uint32_t RXDATA15 :1; + __IO uint32_t RXDATA16 :1; + __IO uint32_t RXDATA17 :1; + __IO uint32_t RXDATA18 :1; + __IO uint32_t RXDATA19 :1; + __IO uint32_t RXDATA20 :1; + __IO uint32_t RXDATA21 :1; + __IO uint32_t RXDATA22 :1; + __IO uint32_t RXDATA23 :1; + __IO uint32_t RXDATA24 :1; + __IO uint32_t RXDATA25 :1; + __IO uint32_t RXDATA26 :1; + __IO uint32_t RXDATA27 :1; + __IO uint32_t RXDATA28 :1; + __IO uint32_t RXDATA29 :1; + __IO uint32_t RXDATA30 :1; + __IO uint32_t RXDATA31 :1; + }; + }; +} stc_i2s_rxfdat_field_t; + +typedef struct stc_i2s_txfdat_field +{ + union { + struct { + __IO uint32_t TXDATA :32; + }; + struct { + __IO uint32_t TXDATA0 :1; + __IO uint32_t TXDATA1 :1; + __IO uint32_t TXDATA2 :1; + __IO uint32_t TXDATA3 :1; + __IO uint32_t TXDATA4 :1; + __IO uint32_t TXDATA5 :1; + __IO uint32_t TXDATA6 :1; + __IO uint32_t TXDATA7 :1; + __IO uint32_t TXDATA8 :1; + __IO uint32_t TXDATA9 :1; + __IO uint32_t TXDATA10 :1; + __IO uint32_t TXDATA11 :1; + __IO uint32_t TXDATA12 :1; + __IO uint32_t TXDATA13 :1; + __IO uint32_t TXDATA14 :1; + __IO uint32_t TXDATA15 :1; + __IO uint32_t TXDATA16 :1; + __IO uint32_t TXDATA17 :1; + __IO uint32_t TXDATA18 :1; + __IO uint32_t TXDATA19 :1; + __IO uint32_t TXDATA20 :1; + __IO uint32_t TXDATA21 :1; + __IO uint32_t TXDATA22 :1; + __IO uint32_t TXDATA23 :1; + __IO uint32_t TXDATA24 :1; + __IO uint32_t TXDATA25 :1; + __IO uint32_t TXDATA26 :1; + __IO uint32_t TXDATA27 :1; + __IO uint32_t TXDATA28 :1; + __IO uint32_t TXDATA29 :1; + __IO uint32_t TXDATA30 :1; + __IO uint32_t TXDATA31 :1; + }; + }; +} stc_i2s_txfdat_field_t; + +typedef struct stc_i2s_cntreg_field +{ + union { + struct { + __IO uint32_t FSPL :1; + __IO uint32_t FSLN :1; + __IO uint32_t FSPH :1; + __IO uint32_t CPOL :1; + __IO uint32_t SMPL :1; + __IO uint32_t RXDIS :1; + __IO uint32_t TXDIS :1; + __IO uint32_t MLSB :1; + __IO uint32_t FRUN :1; + __IO uint32_t BEXT :1; + __IO uint32_t ECKM :1; + __IO uint32_t RHLL :1; + __IO uint32_t SBFN :1; + __IO uint32_t MSMD :1; + __IO uint32_t MSKB :1; + __IO uint32_t RESERVED0 :1; + __IO uint32_t OVHD :10; + __IO uint32_t CKRT :6; + }; + struct { + __IO uint32_t RESERVED1 :16; + __IO uint32_t OVHD0 :1; + __IO uint32_t OVHD1 :1; + __IO uint32_t OVHD2 :1; + __IO uint32_t OVHD3 :1; + __IO uint32_t OVHD4 :1; + __IO uint32_t OVHD5 :1; + __IO uint32_t OVHD6 :1; + __IO uint32_t OVHD7 :1; + __IO uint32_t OVHD8 :1; + __IO uint32_t OVHD9 :1; + __IO uint32_t CKRT0 :1; + __IO uint32_t CKRT1 :1; + __IO uint32_t CKRT2 :1; + __IO uint32_t CKRT3 :1; + __IO uint32_t CKRT4 :1; + __IO uint32_t CKRT5 :1; + }; + }; +} stc_i2s_cntreg_field_t; + +typedef struct stc_i2s_mcr0reg_field +{ + union { + struct { + __IO uint32_t S0WDL :5; + __IO uint32_t S0CHL :5; + __IO uint32_t S0CHN :5; + __IO uint32_t RESERVED0 :1; + __IO uint32_t S1WDL :5; + __IO uint32_t S1CHL :5; + __IO uint32_t S1CHN :5; + __IO uint32_t RESERVED2 :1; + }; + struct { + __IO uint32_t S0WDL0 :1; + __IO uint32_t S0WDL1 :1; + __IO uint32_t S0WDL2 :1; + __IO uint32_t S0WDL3 :1; + __IO uint32_t S0WDL4 :1; + __IO uint32_t S0CHL0 :1; + __IO uint32_t S0CHL1 :1; + __IO uint32_t S0CHL2 :1; + __IO uint32_t S0CHL3 :1; + __IO uint32_t S0CHL4 :1; + __IO uint32_t S0CHN0 :1; + __IO uint32_t S0CHN1 :1; + __IO uint32_t S0CHN2 :1; + __IO uint32_t S0CHN3 :1; + __IO uint32_t S0CHN4 :1; + __IO uint32_t RESERVED1 :1; + __IO uint32_t S1WDL0 :1; + __IO uint32_t S1WDL1 :1; + __IO uint32_t S1WDL2 :1; + __IO uint32_t S1WDL3 :1; + __IO uint32_t S1WDL4 :1; + __IO uint32_t S1CHL0 :1; + __IO uint32_t S1CHL1 :1; + __IO uint32_t S1CHL2 :1; + __IO uint32_t S1CHL3 :1; + __IO uint32_t S1CHL4 :1; + __IO uint32_t S1CHN0 :1; + __IO uint32_t S1CHN1 :1; + __IO uint32_t S1CHN2 :1; + __IO uint32_t S1CHN3 :1; + __IO uint32_t S1CHN4 :1; + __IO uint32_t RESERVED3 :1; + }; + }; +} stc_i2s_mcr0reg_field_t; + +typedef struct stc_i2s_mcr1reg_field +{ + __IO uint32_t S0CH00 :1; + __IO uint32_t S0CH01 :1; + __IO uint32_t S0CH02 :1; + __IO uint32_t S0CH03 :1; + __IO uint32_t S0CH04 :1; + __IO uint32_t S0CH05 :1; + __IO uint32_t S0CH06 :1; + __IO uint32_t S0CH07 :1; + __IO uint32_t S0CH08 :1; + __IO uint32_t S0CH09 :1; + __IO uint32_t S0CH10 :1; + __IO uint32_t S0CH11 :1; + __IO uint32_t S0CH12 :1; + __IO uint32_t S0CH13 :1; + __IO uint32_t S0CH14 :1; + __IO uint32_t S0CH15 :1; + __IO uint32_t S0CH16 :1; + __IO uint32_t S0CH17 :1; + __IO uint32_t S0CH18 :1; + __IO uint32_t S0CH19 :1; + __IO uint32_t S0CH20 :1; + __IO uint32_t S0CH21 :1; + __IO uint32_t S0CH22 :1; + __IO uint32_t S0CH23 :1; + __IO uint32_t S0CH24 :1; + __IO uint32_t S0CH25 :1; + __IO uint32_t S0CH26 :1; + __IO uint32_t S0CH27 :1; + __IO uint32_t S0CH28 :1; + __IO uint32_t S0CH29 :1; + __IO uint32_t S0CH30 :1; + __IO uint32_t S0CH31 :1; +} stc_i2s_mcr1reg_field_t; + +typedef struct stc_i2s_mcr2reg_field +{ + __IO uint32_t S1CH00 :1; + __IO uint32_t S1CH01 :1; + __IO uint32_t S1CH02 :1; + __IO uint32_t S1CH03 :1; + __IO uint32_t S1CH04 :1; + __IO uint32_t S1CH05 :1; + __IO uint32_t S1CH06 :1; + __IO uint32_t S1CH07 :1; + __IO uint32_t S1CH08 :1; + __IO uint32_t S1CH09 :1; + __IO uint32_t S1CH10 :1; + __IO uint32_t S1CH11 :1; + __IO uint32_t S1CH12 :1; + __IO uint32_t S1CH13 :1; + __IO uint32_t S1CH14 :1; + __IO uint32_t S1CH15 :1; + __IO uint32_t S1CH16 :1; + __IO uint32_t S1CH17 :1; + __IO uint32_t S1CH18 :1; + __IO uint32_t S1CH19 :1; + __IO uint32_t S1CH20 :1; + __IO uint32_t S1CH21 :1; + __IO uint32_t S1CH22 :1; + __IO uint32_t S1CH23 :1; + __IO uint32_t S1CH24 :1; + __IO uint32_t S1CH25 :1; + __IO uint32_t S1CH26 :1; + __IO uint32_t S1CH27 :1; + __IO uint32_t S1CH28 :1; + __IO uint32_t S1CH29 :1; + __IO uint32_t S1CH30 :1; + __IO uint32_t S1CH31 :1; +} stc_i2s_mcr2reg_field_t; + +typedef struct stc_i2s_oprreg_field +{ + __IO uint32_t START :1; + __IO uint32_t RESERVED0 :15; + __IO uint32_t TXENB :1; + __IO uint32_t RESERVED1 :7; + __IO uint32_t RXENB :1; + __IO uint32_t RESERVED2 :7; +} stc_i2s_oprreg_field_t; + +typedef struct stc_i2s_srst_field +{ + __IO uint32_t SRST :1; + __IO uint32_t RESERVED0 :31; +} stc_i2s_srst_field_t; + +typedef struct stc_i2s_intcnt_field +{ + union { + struct { + __IO uint32_t RFTH :4; + __IO uint32_t RPTMR :2; + __IO uint32_t RESERVED0 :2; + __IO uint32_t TFTH :4; + __IO uint32_t RESERVED2 :4; + __IO uint32_t RXFIM :1; + __IO uint32_t RXFDM :1; + __IO uint32_t EOPM :1; + __IO uint32_t RXOVM :1; + __IO uint32_t RXUDM :1; + __IO uint32_t RBERM :1; + __IO uint32_t RESERVED3 :2; + __IO uint32_t TXFIM :1; + __IO uint32_t TXFDM :1; + __IO uint32_t TXOVM :1; + __IO uint32_t TXUD0M :1; + __IO uint32_t FERRM :1; + __IO uint32_t TBERM :1; + __IO uint32_t TXUD1M :1; + __IO uint32_t RESERVED4 :1; + }; + struct { + __IO uint32_t RFTH0 :1; + __IO uint32_t RFTH1 :1; + __IO uint32_t RFTH2 :1; + __IO uint32_t RFTH3 :1; + __IO uint32_t RPTMR0 :1; + __IO uint32_t RPTMR1 :1; + __IO uint32_t RESERVED1 :2; + __IO uint32_t TFTH0 :1; + __IO uint32_t TFTH1 :1; + __IO uint32_t TFTH2 :1; + __IO uint32_t TFTH3 :1; + __IO uint32_t RESERVED5 :20; + }; + }; +} stc_i2s_intcnt_field_t; + +typedef struct stc_i2s_status_field +{ + union { + struct { + __IO uint32_t RXNUM :8; + __IO uint32_t TXNUM :8; + __IO uint32_t RXFI :1; + __IO uint32_t TXFI :1; + __IO uint32_t BSY :1; + __IO uint32_t EOPI :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t RXOVR :1; + __IO uint32_t RXUDR :1; + __IO uint32_t TXOVR :1; + __IO uint32_t TXUDR0 :1; + __IO uint32_t TXUDR1 :1; + __IO uint32_t FERR :1; + __IO uint32_t RBERR :1; + __IO uint32_t TBERR :1; + }; + struct { + __IO uint32_t RXNUM0 :1; + __IO uint32_t RXNUM1 :1; + __IO uint32_t RXNUM2 :1; + __IO uint32_t RXNUM3 :1; + __IO uint32_t RXNUM4 :1; + __IO uint32_t RXNUM5 :1; + __IO uint32_t RXNUM6 :1; + __IO uint32_t RXNUM7 :1; + __IO uint32_t TXNUM0 :1; + __IO uint32_t TXNUM1 :1; + __IO uint32_t TXNUM2 :1; + __IO uint32_t TXNUM3 :1; + __IO uint32_t TXNUM4 :1; + __IO uint32_t TXNUM5 :1; + __IO uint32_t TXNUM6 :1; + __IO uint32_t TXNUM7 :1; + __IO uint32_t RESERVED1 :16; + }; + }; +} stc_i2s_status_field_t; + +typedef struct stc_i2s_dmaact_field +{ + __IO uint32_t RDMACT :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t RL1E0 :1; + __IO uint32_t RESERVED1 :7; + __IO uint32_t TDMACT :1; + __IO uint32_t RESERVED2 :7; + __IO uint32_t TL1E0 :1; + __IO uint32_t RESERVED3 :7; +} stc_i2s_dmaact_field_t; + +typedef struct stc_i2s_tstreg_field +{ + __IO uint32_t LBMD :1; + __IO uint32_t RESERVED0 :31; +} stc_i2s_tstreg_field_t; + +/******************************************************************************* +* I2SPRE_MODULE +*******************************************************************************/ +typedef struct stc_i2spre_iccr_field +{ + __IO uint32_t I2SEN :1; + __IO uint32_t ICSEL :1; + __IO uint32_t RESERVED0 :30; +} stc_i2spre_iccr_field_t; + +typedef struct stc_i2spre_ipcr1_field +{ + __IO uint32_t IPLLEN :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipcr1_field_t; + +typedef struct stc_i2spre_ipcr2_field +{ + union { + struct { + __IO uint32_t IPOWT :3; + __IO uint32_t RESERVED0 :29; + }; + struct { + __IO uint32_t IPOWT0 :1; + __IO uint32_t IPOWT1 :1; + __IO uint32_t IPOWT2 :1; + __IO uint32_t RESERVED1 :29; + }; + }; +} stc_i2spre_ipcr2_field_t; + +typedef struct stc_i2spre_ipcr3_field +{ + union { + struct { + __IO uint32_t IPLLK :5; + __IO uint32_t RESERVED0 :27; + }; + struct { + __IO uint32_t IPLLK0 :1; + __IO uint32_t IPLLK1 :1; + __IO uint32_t IPLLK2 :1; + __IO uint32_t IPLLK3 :1; + __IO uint32_t IPLLK4 :1; + __IO uint32_t RESERVED1 :27; + }; + }; +} stc_i2spre_ipcr3_field_t; + +typedef struct stc_i2spre_ipcr4_field +{ + union { + struct { + __IO uint32_t IPLLN :7; + __IO uint32_t RESERVED0 :25; + }; + struct { + __IO uint32_t IPLLN0 :1; + __IO uint32_t IPLLN1 :1; + __IO uint32_t IPLLN2 :1; + __IO uint32_t IPLLN3 :1; + __IO uint32_t IPLLN4 :1; + __IO uint32_t IPLLN5 :1; + __IO uint32_t IPLLN6 :1; + __IO uint32_t RESERVED1 :25; + }; + }; +} stc_i2spre_ipcr4_field_t; + +typedef struct stc_i2spre_ip_str_field +{ + __IO uint32_t IPRDY :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ip_str_field_t; + +typedef struct stc_i2spre_ipint_enr_field +{ + __IO uint32_t IPCSE :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipint_enr_field_t; + +typedef struct stc_i2spre_ipint_clr_field +{ + __IO uint32_t IPCSC :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipint_clr_field_t; + +typedef struct stc_i2spre_ipint_str_field +{ + __IO uint32_t IPCSI :1; + __IO uint32_t RESERVED0 :31; +} stc_i2spre_ipint_str_field_t; + +typedef struct stc_i2spre_ipcr5_field +{ + union { + struct { + __IO uint32_t IPLLM :7; + __IO uint32_t RESERVED0 :25; + }; + struct { + __IO uint32_t IPLLM0 :1; + __IO uint32_t IPLLM1 :1; + __IO uint32_t IPLLM2 :1; + __IO uint32_t IPLLM3 :1; + __IO uint32_t IPLLM4 :1; + __IO uint32_t IPLLM5 :1; + __IO uint32_t IPLLM6 :1; + __IO uint32_t RESERVED1 :25; + }; + }; +} stc_i2spre_ipcr5_field_t; + +/******************************************************************************* +* INTREQ_MODULE +*******************************************************************************/ +typedef struct stc_intreq_drqsel_field +{ + __IO uint32_t USBEP1 :1; + __IO uint32_t USBEP2 :1; + __IO uint32_t USBEP3 :1; + __IO uint32_t USBEP4 :1; + __IO uint32_t USBEP5 :1; + __IO uint32_t ADCSCAN0 :1; + __IO uint32_t ADCSCAN1 :1; + __IO uint32_t ADCSCAN2 :1; + __IO uint32_t IRQ0BT0 :1; + __IO uint32_t IRQ0BT2 :1; + __IO uint32_t IRQ0BT4 :1; + __IO uint32_t IRQ0BT6 :1; + __IO uint32_t MFS0RX :1; + __IO uint32_t MFS0TX :1; + __IO uint32_t MFS1RX :1; + __IO uint32_t MFS1TX :1; + __IO uint32_t MFS2RX :1; + __IO uint32_t MFS2TX :1; + __IO uint32_t MFS3RX :1; + __IO uint32_t MFS3TX :1; + __IO uint32_t MFS4RX :1; + __IO uint32_t MFS4TX :1; + __IO uint32_t MFS5RX :1; + __IO uint32_t MFS5TX :1; + __IO uint32_t MFS6RX :1; + __IO uint32_t MFS6TX :1; + __IO uint32_t MFS7RX :1; + __IO uint32_t MFS7TX :1; + __IO uint32_t EXINT0 :1; + __IO uint32_t EXINT1 :1; + __IO uint32_t EXINT2 :1; + __IO uint32_t EXINT3 :1; +} stc_intreq_drqsel_field_t; + +typedef struct stc_intreq_oddpks_field +{ + __IO uint8_t ODDPKS0 :1; + __IO uint8_t ODDPKS1 :1; + __IO uint8_t ODDPKS2 :1; + __IO uint8_t ODDPKS3 :1; + __IO uint8_t ODDPKS4 :1; + __IO uint8_t RESERVED0 :3; +} stc_intreq_oddpks_field_t; + +typedef struct stc_intreq_oddpks1_field +{ + __IO uint8_t ODDPKS10 :1; + __IO uint8_t ODDPKS11 :1; + __IO uint8_t ODDPKS12 :1; + __IO uint8_t ODDPKS13 :1; + __IO uint8_t ODDPKS14 :1; + __IO uint8_t RESERVED0 :3; +} stc_intreq_oddpks1_field_t; + +typedef struct stc_intreq_irq003sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq003sel_field_t; + +typedef struct stc_intreq_irq004sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq004sel_field_t; + +typedef struct stc_intreq_irq005sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq005sel_field_t; + +typedef struct stc_intreq_irq006sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq006sel_field_t; + +typedef struct stc_intreq_irq007sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq007sel_field_t; + +typedef struct stc_intreq_irq008sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq008sel_field_t; + +typedef struct stc_intreq_irq009sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq009sel_field_t; + +typedef struct stc_intreq_irq010sel_field +{ + union { + struct { + __IO uint32_t SELIRQ :8; + __IO uint32_t RESERVED0 :8; + __IO uint32_t SELBIT0 :1; + __IO uint32_t SELBIT1 :1; + __IO uint32_t SELBIT2 :1; + __IO uint32_t SELBIT3 :1; + __IO uint32_t SELBIT4 :1; + __IO uint32_t SELBIT5 :1; + __IO uint32_t SELBIT6 :1; + __IO uint32_t SELBIT7 :1; + __IO uint32_t SELBIT8 :1; + __IO uint32_t SELBIT9 :1; + __IO uint32_t SELBIT10 :1; + __IO uint32_t SELBIT11 :1; + __IO uint32_t SELBIT12 :1; + __IO uint32_t SELBIT13 :1; + __IO uint32_t SELBIT14 :1; + __IO uint32_t SELBIT15 :1; + }; + struct { + __IO uint32_t SELIRQ0 :1; + __IO uint32_t SELIRQ1 :1; + __IO uint32_t SELIRQ2 :1; + __IO uint32_t SELIRQ3 :1; + __IO uint32_t SELIRQ4 :1; + __IO uint32_t SELIRQ5 :1; + __IO uint32_t SELIRQ6 :1; + __IO uint32_t SELIRQ7 :1; + __IO uint32_t RESERVED1 :24; + }; + }; +} stc_intreq_irq010sel_field_t; + +typedef struct stc_intreq_exc02mon_field +{ + __IO uint32_t NMI :1; + __IO uint32_t HWINT :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_exc02mon_field_t; + +typedef struct stc_intreq_irq000mon_field +{ + __IO uint32_t FCSINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq000mon_field_t; + +typedef struct stc_intreq_irq001mon_field +{ + __IO uint32_t SWWDTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq001mon_field_t; + +typedef struct stc_intreq_irq002mon_field +{ + __IO uint32_t LVDINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq002mon_field_t; + +typedef struct stc_intreq_irq003mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq003mon_field_t; + +typedef struct stc_intreq_irq004mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq004mon_field_t; + +typedef struct stc_intreq_irq005mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq005mon_field_t; + +typedef struct stc_intreq_irq006mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq006mon_field_t; + +typedef struct stc_intreq_irq007mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq007mon_field_t; + +typedef struct stc_intreq_irq008mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq008mon_field_t; + +typedef struct stc_intreq_irq009mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq009mon_field_t; + +typedef struct stc_intreq_irq010mon_field +{ + __IO uint32_t IRQBIT0 :1; + __IO uint32_t IRQBIT1 :1; + __IO uint32_t IRQBIT2 :1; + __IO uint32_t IRQBIT3 :1; + __IO uint32_t IRQBIT4 :1; + __IO uint32_t IRQBIT5 :1; + __IO uint32_t IRQBIT6 :1; + __IO uint32_t IRQBIT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq010mon_field_t; + +typedef struct stc_intreq_irq011mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq011mon_field_t; + +typedef struct stc_intreq_irq012mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq012mon_field_t; + +typedef struct stc_intreq_irq013mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq013mon_field_t; + +typedef struct stc_intreq_irq014mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq014mon_field_t; + +typedef struct stc_intreq_irq015mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq015mon_field_t; + +typedef struct stc_intreq_irq016mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq016mon_field_t; + +typedef struct stc_intreq_irq017mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq017mon_field_t; + +typedef struct stc_intreq_irq018mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq018mon_field_t; + +typedef struct stc_intreq_irq019mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq019mon_field_t; + +typedef struct stc_intreq_irq020mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq020mon_field_t; + +typedef struct stc_intreq_irq021mon_field +{ + __IO uint32_t WAVEINT0 :1; + __IO uint32_t WAVEINT1 :1; + __IO uint32_t WAVEINT2 :1; + __IO uint32_t WAVEINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq021mon_field_t; + +typedef struct stc_intreq_irq022mon_field +{ + __IO uint32_t WAVEINT0 :1; + __IO uint32_t WAVEINT1 :1; + __IO uint32_t WAVEINT2 :1; + __IO uint32_t WAVEINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq022mon_field_t; + +typedef struct stc_intreq_irq023mon_field +{ + __IO uint32_t WAVEINT0 :1; + __IO uint32_t WAVEINT1 :1; + __IO uint32_t WAVEINT2 :1; + __IO uint32_t WAVEINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq023mon_field_t; + +typedef struct stc_intreq_irq024mon_field +{ + __IO uint32_t FRT_PEAK_INT0 :1; + __IO uint32_t FRT_PEAK_INT1 :1; + __IO uint32_t FRT_PEAK_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq024mon_field_t; + +typedef struct stc_intreq_irq025mon_field +{ + __IO uint32_t FRT_ZERO_INT0 :1; + __IO uint32_t FRT_ZERO_INT1 :1; + __IO uint32_t FRT_ZERO_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq025mon_field_t; + +typedef struct stc_intreq_irq026mon_field +{ + __IO uint32_t ICUINT0 :1; + __IO uint32_t ICUINT1 :1; + __IO uint32_t ICUINT2 :1; + __IO uint32_t ICUINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq026mon_field_t; + +typedef struct stc_intreq_irq027mon_field +{ + __IO uint32_t OCUINT0 :1; + __IO uint32_t OCUINT1 :1; + __IO uint32_t OCUINT2 :1; + __IO uint32_t OCUINT3 :1; + __IO uint32_t OCUINT4 :1; + __IO uint32_t OCUINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq027mon_field_t; + +typedef struct stc_intreq_irq028mon_field +{ + __IO uint32_t FRT_PEAK_INT0 :1; + __IO uint32_t FRT_PEAK_INT1 :1; + __IO uint32_t FRT_PEAK_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq028mon_field_t; + +typedef struct stc_intreq_irq029mon_field +{ + __IO uint32_t FRT_ZERO_INT0 :1; + __IO uint32_t FRT_ZERO_INT1 :1; + __IO uint32_t FRT_ZERO_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq029mon_field_t; + +typedef struct stc_intreq_irq030mon_field +{ + __IO uint32_t ICUINT0 :1; + __IO uint32_t ICUINT1 :1; + __IO uint32_t ICUINT2 :1; + __IO uint32_t ICUINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq030mon_field_t; + +typedef struct stc_intreq_irq031mon_field +{ + __IO uint32_t OCUINT0 :1; + __IO uint32_t OCUINT1 :1; + __IO uint32_t OCUINT2 :1; + __IO uint32_t OCUINT3 :1; + __IO uint32_t OCUINT4 :1; + __IO uint32_t OCUINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq031mon_field_t; + +typedef struct stc_intreq_irq032mon_field +{ + __IO uint32_t FRT_PEAK_INT0 :1; + __IO uint32_t FRT_PEAK_INT1 :1; + __IO uint32_t FRT_PEAK_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq032mon_field_t; + +typedef struct stc_intreq_irq033mon_field +{ + __IO uint32_t FRT_ZERO_INT0 :1; + __IO uint32_t FRT_ZERO_INT1 :1; + __IO uint32_t FRT_ZERO_INT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq033mon_field_t; + +typedef struct stc_intreq_irq034mon_field +{ + __IO uint32_t ICUINT0 :1; + __IO uint32_t ICUINT1 :1; + __IO uint32_t ICUINT2 :1; + __IO uint32_t ICUINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq034mon_field_t; + +typedef struct stc_intreq_irq035mon_field +{ + __IO uint32_t OCUINT0 :1; + __IO uint32_t OCUINT1 :1; + __IO uint32_t OCUINT2 :1; + __IO uint32_t OCUINT3 :1; + __IO uint32_t OCUINT4 :1; + __IO uint32_t OCUINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq035mon_field_t; + +typedef struct stc_intreq_irq036mon_field +{ + __IO uint32_t PPGINT0 :1; + __IO uint32_t PPGINT1 :1; + __IO uint32_t PPGINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq036mon_field_t; + +typedef struct stc_intreq_irq037mon_field +{ + __IO uint32_t PPGINT0 :1; + __IO uint32_t PPGINT1 :1; + __IO uint32_t PPGINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq037mon_field_t; + +typedef struct stc_intreq_irq038mon_field +{ + __IO uint32_t PPGINT0 :1; + __IO uint32_t PPGINT1 :1; + __IO uint32_t PPGINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq038mon_field_t; + +typedef struct stc_intreq_irq039mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq039mon_field_t; + +typedef struct stc_intreq_irq040mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq040mon_field_t; + +typedef struct stc_intreq_irq041mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq041mon_field_t; + +typedef struct stc_intreq_irq042mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq042mon_field_t; + +typedef struct stc_intreq_irq043mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq043mon_field_t; + +typedef struct stc_intreq_irq044mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq044mon_field_t; + +typedef struct stc_intreq_irq045mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq045mon_field_t; + +typedef struct stc_intreq_irq046mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq046mon_field_t; + +typedef struct stc_intreq_irq047mon_field +{ + __IO uint32_t TIMINT1 :1; + __IO uint32_t TIMINT2 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq047mon_field_t; + +typedef struct stc_intreq_irq048mon_field +{ + __IO uint32_t WCINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq048mon_field_t; + +typedef struct stc_intreq_irq049mon_field +{ + __IO uint32_t BMEMCS :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq049mon_field_t; + +typedef struct stc_intreq_irq050mon_field +{ + __IO uint32_t RTCINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq050mon_field_t; + +typedef struct stc_intreq_irq051mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq051mon_field_t; + +typedef struct stc_intreq_irq052mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq052mon_field_t; + +typedef struct stc_intreq_irq053mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq053mon_field_t; + +typedef struct stc_intreq_irq054mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq054mon_field_t; + +typedef struct stc_intreq_irq055mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq055mon_field_t; + +typedef struct stc_intreq_irq056mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq056mon_field_t; + +typedef struct stc_intreq_irq057mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq057mon_field_t; + +typedef struct stc_intreq_irq058mon_field +{ + __IO uint32_t EXTINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq058mon_field_t; + +typedef struct stc_intreq_irq059mon_field +{ + __IO uint32_t MOSCINT :1; + __IO uint32_t SOSCINT :1; + __IO uint32_t MPLLINT :1; + __IO uint32_t UPLLINT :1; + __IO uint32_t IPLLINT :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq059mon_field_t; + +typedef struct stc_intreq_irq060mon_field +{ + __IO uint32_t MFSINT0_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq060mon_field_t; + +typedef struct stc_intreq_irq061mon_field +{ + __IO uint32_t MFSINT0_TX :1; + __IO uint32_t MFSINT0_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq061mon_field_t; + +typedef struct stc_intreq_irq062mon_field +{ + __IO uint32_t MFSINT1_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq062mon_field_t; + +typedef struct stc_intreq_irq063mon_field +{ + __IO uint32_t MFSINT1_TX :1; + __IO uint32_t MFSINT1_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq063mon_field_t; + +typedef struct stc_intreq_irq064mon_field +{ + __IO uint32_t MFSINT2_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq064mon_field_t; + +typedef struct stc_intreq_irq065mon_field +{ + __IO uint32_t MFSINT2_TX :1; + __IO uint32_t MFSINT2_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq065mon_field_t; + +typedef struct stc_intreq_irq066mon_field +{ + __IO uint32_t MFSINT3_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq066mon_field_t; + +typedef struct stc_intreq_irq067mon_field +{ + __IO uint32_t MFSINT3_TX :1; + __IO uint32_t MFSINT3_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq067mon_field_t; + +typedef struct stc_intreq_irq068mon_field +{ + __IO uint32_t MFSINT4_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq068mon_field_t; + +typedef struct stc_intreq_irq069mon_field +{ + __IO uint32_t MFSINT4_TX :1; + __IO uint32_t MFSINT4_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq069mon_field_t; + +typedef struct stc_intreq_irq070mon_field +{ + __IO uint32_t MFSINT5_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq070mon_field_t; + +typedef struct stc_intreq_irq071mon_field +{ + __IO uint32_t MFSINT5_TX :1; + __IO uint32_t MFSINT5_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq071mon_field_t; + +typedef struct stc_intreq_irq072mon_field +{ + __IO uint32_t MFSINT6_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq072mon_field_t; + +typedef struct stc_intreq_irq073mon_field +{ + __IO uint32_t MFSINT6_TX :1; + __IO uint32_t MFSINT6_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq073mon_field_t; + +typedef struct stc_intreq_irq074mon_field +{ + __IO uint32_t MFSINT7_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq074mon_field_t; + +typedef struct stc_intreq_irq075mon_field +{ + __IO uint32_t MFSINT7_TX :1; + __IO uint32_t MFSINT7_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq075mon_field_t; + +typedef struct stc_intreq_irq076mon_field +{ + __IO uint32_t ADCINT0 :1; + __IO uint32_t ADCINT1 :1; + __IO uint32_t ADCINT2 :1; + __IO uint32_t ADCINT3 :1; + __IO uint32_t ADCINT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq076mon_field_t; + +typedef struct stc_intreq_irq077mon_field +{ + __IO uint32_t ADCINT0 :1; + __IO uint32_t ADCINT1 :1; + __IO uint32_t ADCINT2 :1; + __IO uint32_t ADCINT3 :1; + __IO uint32_t ADCINT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq077mon_field_t; + +typedef struct stc_intreq_irq078mon_field +{ + __IO uint32_t USB_DRQ_INT0 :1; + __IO uint32_t USB_DRQ_INT1 :1; + __IO uint32_t USB_DRQ_INT2 :1; + __IO uint32_t USB_DRQ_INT3 :1; + __IO uint32_t USB_DRQ_INT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq078mon_field_t; + +typedef struct stc_intreq_irq079mon_field +{ + __IO uint32_t USB_INT0 :1; + __IO uint32_t USB_INT1 :1; + __IO uint32_t USB_INT2 :1; + __IO uint32_t USB_INT3 :1; + __IO uint32_t USB_INT4 :1; + __IO uint32_t USB_INT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq079mon_field_t; + +typedef struct stc_intreq_irq080mon_field +{ + __IO uint32_t CANINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq080mon_field_t; + +typedef struct stc_intreq_irq081mon_field +{ + __IO uint32_t CANINT :1; + __IO uint32_t CANDEINT :1; + __IO uint32_t CANSEINT :1; + __IO uint32_t CAN0INT :1; + __IO uint32_t CAN1INT :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq081mon_field_t; + +typedef struct stc_intreq_irq082mon_field +{ + __IO uint32_t MACSBD :1; + __IO uint32_t MACPMT :1; + __IO uint32_t MACLPI :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq082mon_field_t; + +typedef struct stc_intreq_irq083mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq083mon_field_t; + +typedef struct stc_intreq_irq084mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq084mon_field_t; + +typedef struct stc_intreq_irq085mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq085mon_field_t; + +typedef struct stc_intreq_irq086mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq086mon_field_t; + +typedef struct stc_intreq_irq087mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq087mon_field_t; + +typedef struct stc_intreq_irq088mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq088mon_field_t; + +typedef struct stc_intreq_irq089mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq089mon_field_t; + +typedef struct stc_intreq_irq090mon_field +{ + __IO uint32_t DMACINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq090mon_field_t; + +typedef struct stc_intreq_irq091mon_field +{ + __IO uint32_t DSTCINT0 :1; + __IO uint32_t DSTCINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq091mon_field_t; + +typedef struct stc_intreq_irq092mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq092mon_field_t; + +typedef struct stc_intreq_irq093mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq093mon_field_t; + +typedef struct stc_intreq_irq094mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq094mon_field_t; + +typedef struct stc_intreq_irq095mon_field +{ + __IO uint32_t EXTINT0 :1; + __IO uint32_t EXTINT1 :1; + __IO uint32_t EXTINT2 :1; + __IO uint32_t EXTINT3 :1; + __IO uint32_t RESERVED0 :28; +} stc_intreq_irq095mon_field_t; + +typedef struct stc_intreq_irq096mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq096mon_field_t; + +typedef struct stc_intreq_irq097mon_field +{ + __IO uint32_t QPRCINT0 :1; + __IO uint32_t QPRCINT1 :1; + __IO uint32_t QPRCINT2 :1; + __IO uint32_t QPRCINT3 :1; + __IO uint32_t QPRCINT4 :1; + __IO uint32_t QPRCINT5 :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq097mon_field_t; + +typedef struct stc_intreq_irq098mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq098mon_field_t; + +typedef struct stc_intreq_irq099mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq099mon_field_t; + +typedef struct stc_intreq_irq100mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq100mon_field_t; + +typedef struct stc_intreq_irq101mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq101mon_field_t; + +typedef struct stc_intreq_irq102mon_field +{ + __IO uint32_t BTINT0 :1; + __IO uint32_t BTINT1 :1; + __IO uint32_t BTINT2 :1; + __IO uint32_t BTINT3 :1; + __IO uint32_t BTINT4 :1; + __IO uint32_t BTINT5 :1; + __IO uint32_t BTINT6 :1; + __IO uint32_t BTINT7 :1; + __IO uint32_t RESERVED0 :24; +} stc_intreq_irq102mon_field_t; + +typedef struct stc_intreq_irq103mon_field +{ + __IO uint32_t MFSINT8_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq103mon_field_t; + +typedef struct stc_intreq_irq104mon_field +{ + __IO uint32_t MFSINT8_TX :1; + __IO uint32_t MFSINT8_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq104mon_field_t; + +typedef struct stc_intreq_irq105mon_field +{ + __IO uint32_t MFSINT9_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq105mon_field_t; + +typedef struct stc_intreq_irq106mon_field +{ + __IO uint32_t MFSINT9_TX :1; + __IO uint32_t MFSINT9_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq106mon_field_t; + +typedef struct stc_intreq_irq107mon_field +{ + __IO uint32_t MFSINT10_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq107mon_field_t; + +typedef struct stc_intreq_irq108mon_field +{ + __IO uint32_t MFSINT10_TX :1; + __IO uint32_t MFSINT10_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq108mon_field_t; + +typedef struct stc_intreq_irq109mon_field +{ + __IO uint32_t MFSINT11_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq109mon_field_t; + +typedef struct stc_intreq_irq110mon_field +{ + __IO uint32_t MFSINT11_TX :1; + __IO uint32_t MFSINT11_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq110mon_field_t; + +typedef struct stc_intreq_irq111mon_field +{ + __IO uint32_t ADCINT0 :1; + __IO uint32_t ADCINT1 :1; + __IO uint32_t ADCINT2 :1; + __IO uint32_t ADCINT3 :1; + __IO uint32_t ADCINT4 :1; + __IO uint32_t RESERVED0 :27; +} stc_intreq_irq111mon_field_t; + +typedef struct stc_intreq_irq112mon_field +{ + __IO uint32_t I2SDINT0 :1; + __IO uint32_t I2SDINT1 :1; + __IO uint32_t HSSPIDINT0 :1; + __IO uint32_t HSSPIDINT1 :1; + __IO uint32_t PCRCDINT :1; + __IO uint32_t CANDINT :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq112mon_field_t; + +typedef struct stc_intreq_irq113mon_field +{ + __IO uint32_t USB_DRQ_INT0 :1; + __IO uint32_t USB_DRQ_INT1 :1; + __IO uint32_t USB_DRQ_INT2 :1; + __IO uint32_t USB_DRQ_INT3 :1; + __IO uint32_t USB_DRQ_INT4 :1; + __IO uint32_t RCEC0INT :1; + __IO uint32_t RESERVED0 :26; +} stc_intreq_irq113mon_field_t; + +typedef struct stc_intreq_irq114mon_field +{ + __IO uint32_t USB_INT0 :1; + __IO uint32_t USB_INT1 :1; + __IO uint32_t USB_INT2 :1; + __IO uint32_t USB_INT3 :1; + __IO uint32_t USB_INT4 :1; + __IO uint32_t USB_INT5 :1; + __IO uint32_t RCEC1INT :1; + __IO uint32_t RESERVED0 :25; +} stc_intreq_irq114mon_field_t; + +typedef struct stc_intreq_irq115mon_field +{ + __IO uint32_t HSSPIINT0 :1; + __IO uint32_t HSSPIINT1 :1; + __IO uint32_t HSSPIINT2 :1; + __IO uint32_t RESERVED0 :29; +} stc_intreq_irq115mon_field_t; + +typedef struct stc_intreq_irq117mon_field +{ + __IO uint32_t I2SINT :1; + __IO uint32_t PCRC :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq117mon_field_t; + +typedef struct stc_intreq_irq118mon_field +{ + __IO uint32_t SDINT0 :1; + __IO uint32_t SDINT1 :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq118mon_field_t; + +typedef struct stc_intreq_irq119mon_field +{ + __IO uint32_t FLINT :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq119mon_field_t; + +typedef struct stc_intreq_irq120mon_field +{ + __IO uint32_t MFSINT12_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq120mon_field_t; + +typedef struct stc_intreq_irq121mon_field +{ + __IO uint32_t MFSINT12_TX :1; + __IO uint32_t MFSINT12_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq121mon_field_t; + +typedef struct stc_intreq_irq122mon_field +{ + __IO uint32_t MFSINT13_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq122mon_field_t; + +typedef struct stc_intreq_irq123mon_field +{ + __IO uint32_t MFSINT13_TX :1; + __IO uint32_t MFSINT13_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq123mon_field_t; + +typedef struct stc_intreq_irq124mon_field +{ + __IO uint32_t MFSINT14_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq124mon_field_t; + +typedef struct stc_intreq_irq125mon_field +{ + __IO uint32_t MFSINT14_TX :1; + __IO uint32_t MFSINT14_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq125mon_field_t; + +typedef struct stc_intreq_irq126mon_field +{ + __IO uint32_t MFSINT15_RX :1; + __IO uint32_t RESERVED0 :31; +} stc_intreq_irq126mon_field_t; + +typedef struct stc_intreq_irq127mon_field +{ + __IO uint32_t MFSINT15_TX :1; + __IO uint32_t MFSINT15_STATUS :1; + __IO uint32_t RESERVED0 :30; +} stc_intreq_irq127mon_field_t; + +/******************************************************************************* +* LSCRP_MODULE +*******************************************************************************/ +typedef struct stc_lscrp_lcr_prsld_field +{ + union { + struct { + __IO uint8_t LCR_PRSLD :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t LCR_PRSLD0 :1; + __IO uint8_t LCR_PRSLD1 :1; + __IO uint8_t LCR_PRSLD2 :1; + __IO uint8_t LCR_PRSLD3 :1; + __IO uint8_t LCR_PRSLD4 :1; + __IO uint8_t LCR_PRSLD5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_lscrp_lcr_prsld_field_t; + +/******************************************************************************* +* LVD_MODULE +*******************************************************************************/ +typedef struct stc_lvd_lvd_ctl_field +{ + union { + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t SVHI :5; + __IO uint8_t LVDIE :1; + }; + struct { + __IO uint8_t RESERVED1 :2; + __IO uint8_t SVHI0 :1; + __IO uint8_t SVHI1 :1; + __IO uint8_t SVHI2 :1; + __IO uint8_t SVHI3 :1; + __IO uint8_t SVHI4 :1; + __IO uint8_t RESERVED2 :1; + }; + }; +} stc_lvd_lvd_ctl_field_t; + +typedef struct stc_lvd_lvd_str_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t LVDIR :1; +} stc_lvd_lvd_str_field_t; + +typedef struct stc_lvd_lvd_clr_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t LVDCL :1; +} stc_lvd_lvd_clr_field_t; + +typedef struct stc_lvd_lvd_rlr_field +{ + union { + struct { + __IO uint32_t LVDLCK :32; + }; + struct { + __IO uint32_t LVDLCK0 :1; + __IO uint32_t LVDLCK1 :1; + __IO uint32_t LVDLCK2 :1; + __IO uint32_t LVDLCK3 :1; + __IO uint32_t LVDLCK4 :1; + __IO uint32_t LVDLCK5 :1; + __IO uint32_t LVDLCK6 :1; + __IO uint32_t LVDLCK7 :1; + __IO uint32_t LVDLCK8 :1; + __IO uint32_t LVDLCK9 :1; + __IO uint32_t LVDLCK10 :1; + __IO uint32_t LVDLCK11 :1; + __IO uint32_t LVDLCK12 :1; + __IO uint32_t LVDLCK13 :1; + __IO uint32_t LVDLCK14 :1; + __IO uint32_t LVDLCK15 :1; + __IO uint32_t LVDLCK16 :1; + __IO uint32_t LVDLCK17 :1; + __IO uint32_t LVDLCK18 :1; + __IO uint32_t LVDLCK19 :1; + __IO uint32_t LVDLCK20 :1; + __IO uint32_t LVDLCK21 :1; + __IO uint32_t LVDLCK22 :1; + __IO uint32_t LVDLCK23 :1; + __IO uint32_t LVDLCK24 :1; + __IO uint32_t LVDLCK25 :1; + __IO uint32_t LVDLCK26 :1; + __IO uint32_t LVDLCK27 :1; + __IO uint32_t LVDLCK28 :1; + __IO uint32_t LVDLCK29 :1; + __IO uint32_t LVDLCK30 :1; + __IO uint32_t LVDLCK31 :1; + }; + }; +} stc_lvd_lvd_rlr_field_t; + +typedef struct stc_lvd_lvd_str2_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t LVDIRDY :1; +} stc_lvd_lvd_str2_field_t; + +/******************************************************************************* +* MFS_MODULE +*******************************************************************************/ +typedef struct stc_mfs_smr_field +{ + union { + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t SCKE :1; + __IO uint8_t BDS :1; + __IO uint8_t SCINV :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED1 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; + union { + struct { + __IO uint8_t RESERVED2 :2; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t RESERVED3 :4; + }; + struct { + __IO uint8_t RESERVED4 :8; + }; + }; + union { + struct { + __IO uint8_t RESERVED5 :3; + __IO uint8_t SBL :1; + __IO uint8_t WUCR :1; + __IO uint8_t RESERVED6 :3; + }; + struct { + __IO uint8_t RESERVED7 :8; + }; + }; + }; +} stc_mfs_smr_field_t; + +typedef struct stc_mfs_ibcr_field +{ + union { + struct { + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t SPI :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; + }; + struct { + __IO uint8_t INT :1; + __IO uint8_t BER :1; + __IO uint8_t INTE :1; + __IO uint8_t CNDE :1; + __IO uint8_t WSEL :1; + __IO uint8_t ACKE :1; + __IO uint8_t ACT_SCC :1; + __IO uint8_t MSS :1; + }; + struct { + __IO uint8_t RESERVED2 :5; + __IO uint8_t LBR :1; + __IO uint8_t RESERVED3 :2; + }; + }; +} stc_mfs_ibcr_field_t; + +typedef struct stc_mfs_scr_field +{ + union { + struct { + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t SPI :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; + }; + struct { + __IO uint8_t INT :1; + __IO uint8_t BER :1; + __IO uint8_t INTE :1; + __IO uint8_t CNDE :1; + __IO uint8_t WSEL :1; + __IO uint8_t ACKE :1; + __IO uint8_t ACT_SCC :1; + __IO uint8_t MSS :1; + }; + struct { + __IO uint8_t RESERVED2 :5; + __IO uint8_t LBR :1; + __IO uint8_t RESERVED3 :2; + }; + }; +} stc_mfs_scr_field_t; + +typedef struct stc_mfs_escr_field +{ + union { + union { + struct { + __IO uint8_t L :3; + __IO uint8_t WT :2; + __IO uint8_t CSFE :1; + __IO uint8_t L3 :1; + __IO uint8_t SOP :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t WT0 :1; + __IO uint8_t WT1 :1; + __IO uint8_t RESERVED0 :3; + }; + }; + struct { + __IO uint8_t BB :1; + __IO uint8_t SPC :1; + __IO uint8_t RSC :1; + __IO uint8_t AL :1; + __IO uint8_t TRX :1; + __IO uint8_t RSA :1; + __IO uint8_t RACK :1; + __IO uint8_t FBT :1; + }; + union { + struct { + __IO uint8_t DEL :2; + __IO uint8_t LBL :2; + __IO uint8_t LBIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t ESBL :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t DEL0 :1; + __IO uint8_t DEL1 :1; + __IO uint8_t LBL0 :1; + __IO uint8_t LBL1 :1; + __IO uint8_t RESERVED4 :4; + }; + }; + union { + struct { + __IO uint8_t RESERVED5 :3; + __IO uint8_t P :1; + __IO uint8_t PEN :1; + __IO uint8_t INV :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t FLWEN :1; + }; + struct { + __IO uint8_t RESERVED7 :8; + }; + }; + }; +} stc_mfs_escr_field_t; + +typedef struct stc_mfs_ibsr_field +{ + union { + union { + struct { + __IO uint8_t L :3; + __IO uint8_t WT :2; + __IO uint8_t CSFE :1; + __IO uint8_t L3 :1; + __IO uint8_t SOP :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t WT0 :1; + __IO uint8_t WT1 :1; + __IO uint8_t RESERVED0 :3; + }; + }; + struct { + __IO uint8_t BB :1; + __IO uint8_t SPC :1; + __IO uint8_t RSC :1; + __IO uint8_t AL :1; + __IO uint8_t TRX :1; + __IO uint8_t RSA :1; + __IO uint8_t RACK :1; + __IO uint8_t FBT :1; + }; + union { + struct { + __IO uint8_t DEL :2; + __IO uint8_t LBL :2; + __IO uint8_t LBIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t ESBL :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t DEL0 :1; + __IO uint8_t DEL1 :1; + __IO uint8_t LBL0 :1; + __IO uint8_t LBL1 :1; + __IO uint8_t RESERVED4 :4; + }; + }; + union { + struct { + __IO uint8_t RESERVED5 :3; + __IO uint8_t P :1; + __IO uint8_t PEN :1; + __IO uint8_t INV :1; + __IO uint8_t RESERVED6 :1; + __IO uint8_t FLWEN :1; + }; + struct { + __IO uint8_t RESERVED7 :8; + }; + }; + }; +} stc_mfs_ibsr_field_t; + +typedef struct stc_mfs_ssr_field +{ + union { + struct { + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t AWC :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t REC :1; + }; + struct { + __IO uint8_t RESERVED2 :4; + __IO uint8_t TBIE :1; + __IO uint8_t DMA :1; + __IO uint8_t TSET :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t RESERVED5 :4; + __IO uint8_t FRE :1; + __IO uint8_t LBD :1; + __IO uint8_t RESERVED6 :2; + }; + struct { + __IO uint8_t RESERVED8 :5; + __IO uint8_t PE :1; + __IO uint8_t RESERVED9 :2; + }; + }; +} stc_mfs_ssr_field_t; + +typedef struct stc_mfs_rdr_field +{ + union { + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; + }; +} stc_mfs_rdr_field_t; + +typedef struct stc_mfs_tdr_field +{ + union { + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; + }; +} stc_mfs_tdr_field_t; + +typedef struct stc_mfs_bgr_field +{ + union { + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED1 :1; + }; + }; + union { + struct { + __IO uint16_t RESERVED4 :15; + __IO uint16_t EXT :1; + }; + struct { + __IO uint16_t RESERVED5 :16; + }; + }; + }; +} stc_mfs_bgr_field_t; + +typedef struct stc_mfs_isba_field +{ + union { + struct { + __IO uint8_t SA :7; + __IO uint8_t SAEN :1; + }; + struct { + __IO uint8_t SA0 :1; + __IO uint8_t SA1 :1; + __IO uint8_t SA2 :1; + __IO uint8_t SA3 :1; + __IO uint8_t SA4 :1; + __IO uint8_t SA5 :1; + __IO uint8_t SA6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_isba_field_t; + +typedef struct stc_mfs_ismk_field +{ + union { + struct { + __IO uint8_t SM :7; + __IO uint8_t EN :1; + }; + struct { + __IO uint8_t SM0 :1; + __IO uint8_t SM1 :1; + __IO uint8_t SM2 :1; + __IO uint8_t SM3 :1; + __IO uint8_t SM4 :1; + __IO uint8_t SM5 :1; + __IO uint8_t SM6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_ismk_field_t; + +typedef struct stc_mfs_fcr_field +{ + union { + struct { + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED1 :3; + }; + }; +} stc_mfs_fcr_field_t; + +typedef struct stc_mfs_fbyte1_field +{ + union { + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; + }; +} stc_mfs_fbyte1_field_t; + +typedef struct stc_mfs_fbyte2_field +{ + union { + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; + }; +} stc_mfs_fbyte2_field_t; + +typedef struct stc_mfs_nfcr_field +{ + union { + union { + struct { + __IO uint8_t CSHD :8; + }; + struct { + __IO uint8_t CSHD0 :1; + __IO uint8_t CSHD1 :1; + __IO uint8_t CSHD2 :1; + __IO uint8_t CSHD3 :1; + __IO uint8_t CSHD4 :1; + __IO uint8_t CSHD5 :1; + __IO uint8_t CSHD6 :1; + __IO uint8_t CSHD7 :1; + }; + }; + union { + struct { + __IO uint8_t NFT :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t NFT0 :1; + __IO uint8_t NFT1 :1; + __IO uint8_t NFT2 :1; + __IO uint8_t NFT3 :1; + __IO uint8_t NFT4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; + }; +} stc_mfs_nfcr_field_t; + +typedef struct stc_mfs_scstr0_field +{ + union { + union { + struct { + __IO uint8_t CSHD :8; + }; + struct { + __IO uint8_t CSHD0 :1; + __IO uint8_t CSHD1 :1; + __IO uint8_t CSHD2 :1; + __IO uint8_t CSHD3 :1; + __IO uint8_t CSHD4 :1; + __IO uint8_t CSHD5 :1; + __IO uint8_t CSHD6 :1; + __IO uint8_t CSHD7 :1; + }; + }; + union { + struct { + __IO uint8_t NFT :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t NFT0 :1; + __IO uint8_t NFT1 :1; + __IO uint8_t NFT2 :1; + __IO uint8_t NFT3 :1; + __IO uint8_t NFT4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; + }; +} stc_mfs_scstr0_field_t; + +typedef struct stc_mfs_eibcr_field +{ + union { + union { + struct { + __IO uint8_t CSSU :8; + }; + struct { + __IO uint8_t CSSU0 :1; + __IO uint8_t CSSU1 :1; + __IO uint8_t CSSU2 :1; + __IO uint8_t CSSU3 :1; + __IO uint8_t CSSU4 :1; + __IO uint8_t CSSU5 :1; + __IO uint8_t CSSU6 :1; + __IO uint8_t CSSU7 :1; + }; + }; + struct { + __IO uint8_t BEC :1; + __IO uint8_t SOCE :1; + __IO uint8_t SCLC :1; + __IO uint8_t SDAC :1; + __IO uint8_t SCLS :1; + __IO uint8_t SDAS :1; + __IO uint8_t RESERVED0 :2; + }; + }; +} stc_mfs_eibcr_field_t; + +typedef struct stc_mfs_scstr1_field +{ + union { + union { + struct { + __IO uint8_t CSSU :8; + }; + struct { + __IO uint8_t CSSU0 :1; + __IO uint8_t CSSU1 :1; + __IO uint8_t CSSU2 :1; + __IO uint8_t CSSU3 :1; + __IO uint8_t CSSU4 :1; + __IO uint8_t CSSU5 :1; + __IO uint8_t CSSU6 :1; + __IO uint8_t CSSU7 :1; + }; + }; + struct { + __IO uint8_t BEC :1; + __IO uint8_t SOCE :1; + __IO uint8_t SCLC :1; + __IO uint8_t SDAC :1; + __IO uint8_t SCLS :1; + __IO uint8_t SDAS :1; + __IO uint8_t RESERVED0 :2; + }; + }; +} stc_mfs_scstr1_field_t; + +typedef struct stc_mfs_scstr32_field +{ + union { + struct { + __IO uint16_t CSDS :16; + }; + struct { + __IO uint16_t CSDS0 :1; + __IO uint16_t CSDS1 :1; + __IO uint16_t CSDS2 :1; + __IO uint16_t CSDS3 :1; + __IO uint16_t CSDS4 :1; + __IO uint16_t CSDS5 :1; + __IO uint16_t CSDS6 :1; + __IO uint16_t CSDS7 :1; + __IO uint16_t CSDS8 :1; + __IO uint16_t CSDS9 :1; + __IO uint16_t CSDS10 :1; + __IO uint16_t CSDS11 :1; + __IO uint16_t CSDS12 :1; + __IO uint16_t CSDS13 :1; + __IO uint16_t CSDS14 :1; + __IO uint16_t CSDS15 :1; + }; + }; +} stc_mfs_scstr32_field_t; + +typedef struct stc_mfs_sacsr_field +{ + union { + struct { + __IO uint16_t TMRE :1; + __IO uint16_t TDIV :4; + __IO uint16_t RESERVED1 :1; + __IO uint16_t TSYNE :1; + __IO uint16_t TINTE :1; + __IO uint16_t TINT :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t CSE :1; + __IO uint16_t CSEIE :1; + __IO uint16_t TBEEN :1; + __IO uint16_t RESERVED3 :2; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TDIV0 :1; + __IO uint16_t TDIV1 :1; + __IO uint16_t TDIV2 :1; + __IO uint16_t TDIV3 :1; + __IO uint16_t RESERVED4 :11; + }; + }; +} stc_mfs_sacsr_field_t; + +typedef struct stc_mfs_stmr_field +{ + union { + struct { + __IO uint16_t TM :16; + }; + struct { + __IO uint16_t TM0 :1; + __IO uint16_t TM1 :1; + __IO uint16_t TM2 :1; + __IO uint16_t TM3 :1; + __IO uint16_t TM4 :1; + __IO uint16_t TM5 :1; + __IO uint16_t TM6 :1; + __IO uint16_t TM7 :1; + __IO uint16_t TM8 :1; + __IO uint16_t TM9 :1; + __IO uint16_t TM10 :1; + __IO uint16_t TM11 :1; + __IO uint16_t TM12 :1; + __IO uint16_t TM13 :1; + __IO uint16_t TM14 :1; + __IO uint16_t TM15 :1; + }; + }; +} stc_mfs_stmr_field_t; + +typedef struct stc_mfs_stmcr_field +{ + union { + struct { + __IO uint16_t TC :16; + }; + struct { + __IO uint16_t TC0 :1; + __IO uint16_t TC1 :1; + __IO uint16_t TC2 :1; + __IO uint16_t TC3 :1; + __IO uint16_t TC4 :1; + __IO uint16_t TC5 :1; + __IO uint16_t TC6 :1; + __IO uint16_t TC7 :1; + __IO uint16_t TC8 :1; + __IO uint16_t TC9 :1; + __IO uint16_t TC10 :1; + __IO uint16_t TC11 :1; + __IO uint16_t TC12 :1; + __IO uint16_t TC13 :1; + __IO uint16_t TC14 :1; + __IO uint16_t TC15 :1; + }; + }; +} stc_mfs_stmcr_field_t; + +typedef struct stc_mfs_scscr_field +{ + union { + struct { + __IO uint16_t CSOE :1; + __IO uint16_t CSEN0 :1; + __IO uint16_t CSEN1 :1; + __IO uint16_t CSEN2 :1; + __IO uint16_t CSEN3 :1; + __IO uint16_t CSLVL :1; + __IO uint16_t CDIV :3; + __IO uint16_t SCAM :1; + __IO uint16_t SCD :2; + __IO uint16_t SED :2; + __IO uint16_t SST :2; + }; + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CDIV0 :1; + __IO uint16_t CDIV1 :1; + __IO uint16_t CDIV2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SCD0 :1; + __IO uint16_t SCD1 :1; + __IO uint16_t SED0 :1; + __IO uint16_t SED1 :1; + __IO uint16_t SST0 :1; + __IO uint16_t SST1 :1; + }; + }; +} stc_mfs_scscr_field_t; + +typedef struct stc_mfs_scsfr0_field +{ + union { + struct { + __IO uint8_t CS1L :5; + __IO uint8_t CS1SPI :1; + __IO uint8_t CS1SCINV :1; + __IO uint8_t CS1CSLVL :1; + }; + struct { + __IO uint8_t CS1L0 :1; + __IO uint8_t CS1L1 :1; + __IO uint8_t CS1L2 :1; + __IO uint8_t CS1L3 :1; + __IO uint8_t CS1L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_scsfr0_field_t; + +typedef struct stc_mfs_scsfr1_field +{ + union { + struct { + __IO uint8_t CS2L :5; + __IO uint8_t CS2SPI :1; + __IO uint8_t CS2SCINV :1; + __IO uint8_t CS2CSLVL :1; + }; + struct { + __IO uint8_t CS2L0 :1; + __IO uint8_t CS2L1 :1; + __IO uint8_t CS2L2 :1; + __IO uint8_t CS2L3 :1; + __IO uint8_t CS2L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_scsfr1_field_t; + +typedef struct stc_mfs_scsfr2_field +{ + union { + struct { + __IO uint8_t CS3L :5; + __IO uint8_t CS3SPI :1; + __IO uint8_t CS3SCINV :1; + __IO uint8_t CS3CSLVL :1; + }; + struct { + __IO uint8_t CS3L0 :1; + __IO uint8_t CS3L1 :1; + __IO uint8_t CS3L2 :1; + __IO uint8_t CS3L3 :1; + __IO uint8_t CS3L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_scsfr2_field_t; + +typedef struct stc_mfs_csio_smr_field +{ + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t SCKE :1; + __IO uint8_t BDS :1; + __IO uint8_t SCINV :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED1 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_csio_smr_field_t; + +typedef struct stc_mfs_i2c_smr_field +{ + union { + struct { + __IO uint8_t RESERVED2 :2; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t RESERVED3 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED4 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_i2c_smr_field_t; + +typedef struct stc_mfs_lin_smr_field +{ + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t RESERVED5 :2; + __IO uint8_t SBL :1; + __IO uint8_t WUCR :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED6 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_lin_smr_field_t; + +typedef struct stc_mfs_uart_smr_field +{ + union { + struct { + __IO uint8_t SOE :1; + __IO uint8_t RESERVED7 :1; + __IO uint8_t BDS :1; + __IO uint8_t SBL :1; + __IO uint8_t RESERVED8 :1; + __IO uint8_t MD :3; + }; + struct { + __IO uint8_t RESERVED9 :5; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t MD2 :1; + }; + }; +} stc_mfs_uart_smr_field_t; + +typedef struct stc_mfs_csio_scr_field +{ + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t SPI :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; +} stc_mfs_csio_scr_field_t; + +typedef struct stc_mfs_i2c_ibcr_field +{ + __IO uint8_t INT :1; + __IO uint8_t BER :1; + __IO uint8_t INTE :1; + __IO uint8_t CNDE :1; + __IO uint8_t WSEL :1; + __IO uint8_t ACKE :1; + __IO uint8_t ACT_SCC :1; + __IO uint8_t MSS :1; +} stc_mfs_i2c_ibcr_field_t; + +typedef struct stc_mfs_lin_scr_field +{ + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t LBR :1; + __IO uint8_t MS :1; + __IO uint8_t UPCL :1; +} stc_mfs_lin_scr_field_t; + +typedef struct stc_mfs_uart_scr_field +{ + __IO uint8_t TXE :1; + __IO uint8_t RXE :1; + __IO uint8_t TBIE :1; + __IO uint8_t TIE :1; + __IO uint8_t RIE :1; + __IO uint8_t RESERVED3 :2; + __IO uint8_t UPCL :1; +} stc_mfs_uart_scr_field_t; + +typedef struct stc_mfs_csio_escr_field +{ + union { + struct { + __IO uint8_t L :3; + __IO uint8_t WT :2; + __IO uint8_t CSFE :1; + __IO uint8_t L3 :1; + __IO uint8_t SOP :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t WT0 :1; + __IO uint8_t WT1 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_escr_field_t; + +typedef struct stc_mfs_i2c_ibsr_field +{ + __IO uint8_t BB :1; + __IO uint8_t SPC :1; + __IO uint8_t RSC :1; + __IO uint8_t AL :1; + __IO uint8_t TRX :1; + __IO uint8_t RSA :1; + __IO uint8_t RACK :1; + __IO uint8_t FBT :1; +} stc_mfs_i2c_ibsr_field_t; + +typedef struct stc_mfs_lin_escr_field +{ + union { + struct { + __IO uint8_t DEL :2; + __IO uint8_t LBL :2; + __IO uint8_t LBIE :1; + __IO uint8_t RESERVED2 :1; + __IO uint8_t ESBL :1; + __IO uint8_t RESERVED3 :1; + }; + struct { + __IO uint8_t DEL0 :1; + __IO uint8_t DEL1 :1; + __IO uint8_t LBL0 :1; + __IO uint8_t LBL1 :1; + __IO uint8_t RESERVED4 :4; + }; + }; +} stc_mfs_lin_escr_field_t; + +typedef struct stc_mfs_uart_escr_field +{ + union { + struct { + __IO uint8_t L :3; + __IO uint8_t P :1; + __IO uint8_t PEN :1; + __IO uint8_t INV :1; + __IO uint8_t ESBL :1; + __IO uint8_t FLWEN :1; + }; + struct { + __IO uint8_t L0 :1; + __IO uint8_t L1 :1; + __IO uint8_t L2 :1; + __IO uint8_t RESERVED5 :5; + }; + }; +} stc_mfs_uart_escr_field_t; + +typedef struct stc_mfs_csio_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t AWC :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t REC :1; +} stc_mfs_csio_ssr_field_t; + +typedef struct stc_mfs_i2c_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t TBIE :1; + __IO uint8_t DMA :1; + __IO uint8_t TSET :1; + __IO uint8_t REC :1; +} stc_mfs_i2c_ssr_field_t; + +typedef struct stc_mfs_lin_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t FRE :1; + __IO uint8_t LBD :1; + __IO uint8_t RESERVED3 :1; + __IO uint8_t REC :1; +} stc_mfs_lin_ssr_field_t; + +typedef struct stc_mfs_uart_ssr_field +{ + __IO uint8_t TBI :1; + __IO uint8_t TDRE :1; + __IO uint8_t RDRF :1; + __IO uint8_t ORE :1; + __IO uint8_t FRE :1; + __IO uint8_t PE :1; + __IO uint8_t RESERVED5 :1; + __IO uint8_t REC :1; +} stc_mfs_uart_ssr_field_t; + +typedef struct stc_mfs_csio_rdr_field +{ + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; +} stc_mfs_csio_rdr_field_t; + +typedef struct stc_mfs_csio_tdr_field +{ + union { + struct { + __IO uint16_t D :16; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t D9 :1; + __IO uint16_t D10 :1; + __IO uint16_t D11 :1; + __IO uint16_t D12 :1; + __IO uint16_t D13 :1; + __IO uint16_t D14 :1; + __IO uint16_t D15 :1; + }; + }; +} stc_mfs_csio_tdr_field_t; + +typedef struct stc_mfs_i2c_rdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mfs_i2c_rdr_field_t; + +typedef struct stc_mfs_i2c_tdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED2 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED3 :8; + }; + }; +} stc_mfs_i2c_tdr_field_t; + +typedef struct stc_mfs_lin_rdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED4 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED5 :8; + }; + }; +} stc_mfs_lin_rdr_field_t; + +typedef struct stc_mfs_lin_tdr_field +{ + union { + struct { + __IO uint16_t D :8; + __IO uint16_t RESERVED6 :8; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t RESERVED7 :8; + }; + }; +} stc_mfs_lin_tdr_field_t; + +typedef struct stc_mfs_uart_rdr_field +{ + union { + struct { + __IO uint16_t D :9; + __IO uint16_t RESERVED8 :7; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t RESERVED9 :7; + }; + }; +} stc_mfs_uart_rdr_field_t; + +typedef struct stc_mfs_uart_tdr_field +{ + union { + struct { + __IO uint16_t D :9; + __IO uint16_t RESERVED10 :7; + }; + struct { + __IO uint16_t D0 :1; + __IO uint16_t D1 :1; + __IO uint16_t D2 :1; + __IO uint16_t D3 :1; + __IO uint16_t D4 :1; + __IO uint16_t D5 :1; + __IO uint16_t D6 :1; + __IO uint16_t D7 :1; + __IO uint16_t D8 :1; + __IO uint16_t RESERVED11 :7; + }; + }; +} stc_mfs_uart_tdr_field_t; + +typedef struct stc_mfs_csio_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_mfs_csio_bgr_field_t; + +typedef struct stc_mfs_i2c_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t RESERVED2 :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED3 :1; + }; + }; +} stc_mfs_i2c_bgr_field_t; + +typedef struct stc_mfs_lin_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t EXT :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED4 :1; + }; + }; +} stc_mfs_lin_bgr_field_t; + +typedef struct stc_mfs_uart_bgr_field +{ + union { + struct { + __IO uint16_t BGR :15; + __IO uint16_t EXT :1; + }; + struct { + __IO uint16_t BGR0 :1; + __IO uint16_t BGR1 :1; + __IO uint16_t BGR2 :1; + __IO uint16_t BGR3 :1; + __IO uint16_t BGR4 :1; + __IO uint16_t BGR5 :1; + __IO uint16_t BGR6 :1; + __IO uint16_t BGR7 :1; + __IO uint16_t BGR8 :1; + __IO uint16_t BGR9 :1; + __IO uint16_t BGR10 :1; + __IO uint16_t BGR11 :1; + __IO uint16_t BGR12 :1; + __IO uint16_t BGR13 :1; + __IO uint16_t BGR14 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_mfs_uart_bgr_field_t; + +typedef struct stc_mfs_i2c_isba_field +{ + union { + struct { + __IO uint8_t SA :7; + __IO uint8_t SAEN :1; + }; + struct { + __IO uint8_t SA0 :1; + __IO uint8_t SA1 :1; + __IO uint8_t SA2 :1; + __IO uint8_t SA3 :1; + __IO uint8_t SA4 :1; + __IO uint8_t SA5 :1; + __IO uint8_t SA6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_i2c_isba_field_t; + +typedef struct stc_mfs_i2c_ismk_field +{ + union { + struct { + __IO uint8_t SM :7; + __IO uint8_t EN :1; + }; + struct { + __IO uint8_t SM0 :1; + __IO uint8_t SM1 :1; + __IO uint8_t SM2 :1; + __IO uint8_t SM3 :1; + __IO uint8_t SM4 :1; + __IO uint8_t SM5 :1; + __IO uint8_t SM6 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_mfs_i2c_ismk_field_t; + +typedef struct stc_mfs_csio_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED1 :3; +} stc_mfs_csio_fcr_field_t; + +typedef struct stc_mfs_i2c_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED3 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED4 :3; +} stc_mfs_i2c_fcr_field_t; + +typedef struct stc_mfs_lin_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED6 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED7 :3; +} stc_mfs_lin_fcr_field_t; + +typedef struct stc_mfs_uart_fcr_field +{ + __IO uint16_t FE1 :1; + __IO uint16_t FE2 :1; + __IO uint16_t FCL1 :1; + __IO uint16_t FCL2 :1; + __IO uint16_t FSET :1; + __IO uint16_t FLD :1; + __IO uint16_t FLST :1; + __IO uint16_t RESERVED9 :1; + __IO uint16_t FSEL :1; + __IO uint16_t FTIE :1; + __IO uint16_t FDRQ :1; + __IO uint16_t FRIIE :1; + __IO uint16_t FLSTE :1; + __IO uint16_t RESERVED10 :3; +} stc_mfs_uart_fcr_field_t; + +typedef struct stc_mfs_csio_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_csio_fbyte1_field_t; + +typedef struct stc_mfs_i2c_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_i2c_fbyte1_field_t; + +typedef struct stc_mfs_lin_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_lin_fbyte1_field_t; + +typedef struct stc_mfs_uart_fbyte1_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_uart_fbyte1_field_t; + +typedef struct stc_mfs_csio_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_csio_fbyte2_field_t; + +typedef struct stc_mfs_i2c_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_i2c_fbyte2_field_t; + +typedef struct stc_mfs_lin_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_lin_fbyte2_field_t; + +typedef struct stc_mfs_uart_fbyte2_field +{ + union { + struct { + __IO uint8_t FD :8; + }; + struct { + __IO uint8_t FD0 :1; + __IO uint8_t FD1 :1; + __IO uint8_t FD2 :1; + __IO uint8_t FD3 :1; + __IO uint8_t FD4 :1; + __IO uint8_t FD5 :1; + __IO uint8_t FD6 :1; + __IO uint8_t FD7 :1; + }; + }; +} stc_mfs_uart_fbyte2_field_t; + +typedef struct stc_mfs_csio_scstr0_field +{ + union { + struct { + __IO uint8_t CSHD :8; + }; + struct { + __IO uint8_t CSHD0 :1; + __IO uint8_t CSHD1 :1; + __IO uint8_t CSHD2 :1; + __IO uint8_t CSHD3 :1; + __IO uint8_t CSHD4 :1; + __IO uint8_t CSHD5 :1; + __IO uint8_t CSHD6 :1; + __IO uint8_t CSHD7 :1; + }; + }; +} stc_mfs_csio_scstr0_field_t; + +typedef struct stc_mfs_i2c_nfcr_field +{ + union { + struct { + __IO uint8_t NFT :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t NFT0 :1; + __IO uint8_t NFT1 :1; + __IO uint8_t NFT2 :1; + __IO uint8_t NFT3 :1; + __IO uint8_t NFT4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mfs_i2c_nfcr_field_t; + +typedef struct stc_mfs_csio_scstr1_field +{ + union { + struct { + __IO uint8_t CSSU :8; + }; + struct { + __IO uint8_t CSSU0 :1; + __IO uint8_t CSSU1 :1; + __IO uint8_t CSSU2 :1; + __IO uint8_t CSSU3 :1; + __IO uint8_t CSSU4 :1; + __IO uint8_t CSSU5 :1; + __IO uint8_t CSSU6 :1; + __IO uint8_t CSSU7 :1; + }; + }; +} stc_mfs_csio_scstr1_field_t; + +typedef struct stc_mfs_i2c_eibcr_field +{ + __IO uint8_t BEC :1; + __IO uint8_t SOCE :1; + __IO uint8_t SCLC :1; + __IO uint8_t SDAC :1; + __IO uint8_t SCLS :1; + __IO uint8_t SDAS :1; + __IO uint8_t RESERVED0 :2; +} stc_mfs_i2c_eibcr_field_t; + +typedef struct stc_mfs_csio_scstr32_field +{ + union { + struct { + __IO uint16_t CSDS :16; + }; + struct { + __IO uint16_t CSDS0 :1; + __IO uint16_t CSDS1 :1; + __IO uint16_t CSDS2 :1; + __IO uint16_t CSDS3 :1; + __IO uint16_t CSDS4 :1; + __IO uint16_t CSDS5 :1; + __IO uint16_t CSDS6 :1; + __IO uint16_t CSDS7 :1; + __IO uint16_t CSDS8 :1; + __IO uint16_t CSDS9 :1; + __IO uint16_t CSDS10 :1; + __IO uint16_t CSDS11 :1; + __IO uint16_t CSDS12 :1; + __IO uint16_t CSDS13 :1; + __IO uint16_t CSDS14 :1; + __IO uint16_t CSDS15 :1; + }; + }; +} stc_mfs_csio_scstr32_field_t; + +typedef struct stc_mfs_csio_sacsr_field +{ + union { + struct { + __IO uint16_t TMRE :1; + __IO uint16_t TDIV :4; + __IO uint16_t RESERVED1 :1; + __IO uint16_t TSYNE :1; + __IO uint16_t TINTE :1; + __IO uint16_t TINT :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t CSE :1; + __IO uint16_t CSEIE :1; + __IO uint16_t TBEEN :1; + __IO uint16_t RESERVED3 :2; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t TDIV0 :1; + __IO uint16_t TDIV1 :1; + __IO uint16_t TDIV2 :1; + __IO uint16_t TDIV3 :1; + __IO uint16_t RESERVED4 :11; + }; + }; +} stc_mfs_csio_sacsr_field_t; + +typedef struct stc_mfs_csio_stmr_field +{ + union { + struct { + __IO uint16_t TM :16; + }; + struct { + __IO uint16_t TM0 :1; + __IO uint16_t TM1 :1; + __IO uint16_t TM2 :1; + __IO uint16_t TM3 :1; + __IO uint16_t TM4 :1; + __IO uint16_t TM5 :1; + __IO uint16_t TM6 :1; + __IO uint16_t TM7 :1; + __IO uint16_t TM8 :1; + __IO uint16_t TM9 :1; + __IO uint16_t TM10 :1; + __IO uint16_t TM11 :1; + __IO uint16_t TM12 :1; + __IO uint16_t TM13 :1; + __IO uint16_t TM14 :1; + __IO uint16_t TM15 :1; + }; + }; +} stc_mfs_csio_stmr_field_t; + +typedef struct stc_mfs_csio_stmcr_field +{ + union { + struct { + __IO uint16_t TC :16; + }; + struct { + __IO uint16_t TC0 :1; + __IO uint16_t TC1 :1; + __IO uint16_t TC2 :1; + __IO uint16_t TC3 :1; + __IO uint16_t TC4 :1; + __IO uint16_t TC5 :1; + __IO uint16_t TC6 :1; + __IO uint16_t TC7 :1; + __IO uint16_t TC8 :1; + __IO uint16_t TC9 :1; + __IO uint16_t TC10 :1; + __IO uint16_t TC11 :1; + __IO uint16_t TC12 :1; + __IO uint16_t TC13 :1; + __IO uint16_t TC14 :1; + __IO uint16_t TC15 :1; + }; + }; +} stc_mfs_csio_stmcr_field_t; + +typedef struct stc_mfs_csio_scscr_field +{ + union { + struct { + __IO uint16_t CSOE :1; + __IO uint16_t CSEN0 :1; + __IO uint16_t CSEN1 :1; + __IO uint16_t CSEN2 :1; + __IO uint16_t CSEN3 :1; + __IO uint16_t CSLVL :1; + __IO uint16_t CDIV :3; + __IO uint16_t SCAM :1; + __IO uint16_t SCD :2; + __IO uint16_t SED :2; + __IO uint16_t SST :2; + }; + struct { + __IO uint16_t RESERVED0 :6; + __IO uint16_t CDIV0 :1; + __IO uint16_t CDIV1 :1; + __IO uint16_t CDIV2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SCD0 :1; + __IO uint16_t SCD1 :1; + __IO uint16_t SED0 :1; + __IO uint16_t SED1 :1; + __IO uint16_t SST0 :1; + __IO uint16_t SST1 :1; + }; + }; +} stc_mfs_csio_scscr_field_t; + +typedef struct stc_mfs_csio_scsfr0_field +{ + union { + struct { + __IO uint8_t CS1L :5; + __IO uint8_t CS1SPI :1; + __IO uint8_t CS1SCINV :1; + __IO uint8_t CS1CSLVL :1; + }; + struct { + __IO uint8_t CS1L0 :1; + __IO uint8_t CS1L1 :1; + __IO uint8_t CS1L2 :1; + __IO uint8_t CS1L3 :1; + __IO uint8_t CS1L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_scsfr0_field_t; + +typedef struct stc_mfs_csio_scsfr1_field +{ + union { + struct { + __IO uint8_t CS2L :5; + __IO uint8_t CS2SPI :1; + __IO uint8_t CS2SCINV :1; + __IO uint8_t CS2CSLVL :1; + }; + struct { + __IO uint8_t CS2L0 :1; + __IO uint8_t CS2L1 :1; + __IO uint8_t CS2L2 :1; + __IO uint8_t CS2L3 :1; + __IO uint8_t CS2L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_scsfr1_field_t; + +typedef struct stc_mfs_csio_scsfr2_field +{ + union { + struct { + __IO uint8_t CS3L :5; + __IO uint8_t CS3SPI :1; + __IO uint8_t CS3SCINV :1; + __IO uint8_t CS3CSLVL :1; + }; + struct { + __IO uint8_t CS3L0 :1; + __IO uint8_t CS3L1 :1; + __IO uint8_t CS3L2 :1; + __IO uint8_t CS3L3 :1; + __IO uint8_t CS3L4 :1; + __IO uint8_t RESERVED0 :3; + }; + }; +} stc_mfs_csio_scsfr2_field_t; + +/******************************************************************************* +* MFT_MODULE +*******************************************************************************/ +typedef struct stc_mft_ocsa10_field +{ + __IO uint8_t CST0 :1; + __IO uint8_t CST1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE0 :1; + __IO uint8_t IOE1 :1; + __IO uint8_t IOP0 :1; + __IO uint8_t IOP1 :1; +} stc_mft_ocsa10_field_t; + +typedef struct stc_mft_ocsb10_field +{ + __IO uint8_t OTD0 :1; + __IO uint8_t OTD1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocsb10_field_t; + +typedef struct stc_mft_ocsd10_field +{ + union { + struct { + __IO uint16_t OCCP0BUFE :2; + __IO uint16_t OCCP1BUFE :2; + __IO uint16_t OCSE0BUFE :2; + __IO uint16_t OCSE1BUFE :2; + __IO uint16_t OPBM0 :1; + __IO uint16_t OPBM1 :1; + __IO uint16_t OEBM0 :1; + __IO uint16_t OEBM1 :1; + __IO uint16_t OFEX0 :1; + __IO uint16_t OFEX1 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP0BUFE0 :1; + __IO uint16_t OCCP0BUFE1 :1; + __IO uint16_t OCCP1BUFE0 :1; + __IO uint16_t OCCP1BUFE1 :1; + __IO uint16_t OCSE0BUFE0 :1; + __IO uint16_t OCSE0BUFE1 :1; + __IO uint16_t OCSE1BUFE0 :1; + __IO uint16_t OCSE1BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocsd10_field_t; + +typedef struct stc_mft_ocsa32_field +{ + __IO uint8_t CST2 :1; + __IO uint8_t CST3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE2 :1; + __IO uint8_t IOE3 :1; + __IO uint8_t IOP2 :1; + __IO uint8_t IOP3 :1; +} stc_mft_ocsa32_field_t; + +typedef struct stc_mft_ocsb32_field +{ + __IO uint8_t OTD2 :1; + __IO uint8_t OTD3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocsb32_field_t; + +typedef struct stc_mft_ocsd32_field +{ + union { + struct { + __IO uint16_t OCCP2BUFE :2; + __IO uint16_t OCCP3BUFE :2; + __IO uint16_t OCSE2BUFE :2; + __IO uint16_t OCSE3BUFE :2; + __IO uint16_t OPBM2 :1; + __IO uint16_t OPBM3 :1; + __IO uint16_t OEBM2 :1; + __IO uint16_t OEBM3 :1; + __IO uint16_t OFEX2 :1; + __IO uint16_t OFEX3 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP2BUFE0 :1; + __IO uint16_t OCCP2BUFE1 :1; + __IO uint16_t OCCP3BUFE0 :1; + __IO uint16_t OCCP3BUFE1 :1; + __IO uint16_t OCSE2BUFE0 :1; + __IO uint16_t OCSE2BUFE1 :1; + __IO uint16_t OCSE3BUFE0 :1; + __IO uint16_t OCSE3BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocsd32_field_t; + +typedef struct stc_mft_ocsa54_field +{ + __IO uint8_t CST4 :1; + __IO uint8_t CST5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE4 :1; + __IO uint8_t IOE5 :1; + __IO uint8_t IOP4 :1; + __IO uint8_t IOP5 :1; +} stc_mft_ocsa54_field_t; + +typedef struct stc_mft_ocsb54_field +{ + __IO uint8_t OTD4 :1; + __IO uint8_t OTD5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocsb54_field_t; + +typedef struct stc_mft_ocsd54_field +{ + union { + struct { + __IO uint16_t OCCP4BUFE :2; + __IO uint16_t OCCP5BUFE :2; + __IO uint16_t OCSE4BUFE :2; + __IO uint16_t OCSE5BUFE :2; + __IO uint16_t OPBM4 :1; + __IO uint16_t OPBM5 :1; + __IO uint16_t OEBM4 :1; + __IO uint16_t OEBM5 :1; + __IO uint16_t OFEX4 :1; + __IO uint16_t OFEX5 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP4BUFE0 :1; + __IO uint16_t OCCP4BUFE1 :1; + __IO uint16_t OCCP5BUFE0 :1; + __IO uint16_t OCCP5BUFE1 :1; + __IO uint16_t OCSE4BUFE0 :1; + __IO uint16_t OCSE4BUFE1 :1; + __IO uint16_t OCSE5BUFE0 :1; + __IO uint16_t OCSE5BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocsd54_field_t; + +typedef struct stc_mft_ocsc_field +{ + __IO uint8_t MOD0 :1; + __IO uint8_t MOD1 :1; + __IO uint8_t MOD2 :1; + __IO uint8_t MOD3 :1; + __IO uint8_t MOD4 :1; + __IO uint8_t MOD5 :1; + __IO uint8_t RESERVED0 :2; +} stc_mft_ocsc_field_t; + +typedef struct stc_mft_ocse0_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocse0_field_t; + +typedef struct stc_mft_ocse1_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocse1_field_t; + +typedef struct stc_mft_ocse2_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocse2_field_t; + +typedef struct stc_mft_ocse3_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocse3_field_t; + +typedef struct stc_mft_ocse4_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocse4_field_t; + +typedef struct stc_mft_ocse5_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocse5_field_t; + +typedef struct stc_mft_tccp0_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_tccp0_field_t; + +typedef struct stc_mft_tcsa0_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_tcsa0_field_t; + +typedef struct stc_mft_tcsc0_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_tcsc0_field_t; + +typedef struct stc_mft_tccp1_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_tccp1_field_t; + +typedef struct stc_mft_tcsa1_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_tcsa1_field_t; + +typedef struct stc_mft_tcsc1_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_tcsc1_field_t; + +typedef struct stc_mft_tccp2_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_tccp2_field_t; + +typedef struct stc_mft_tcsa2_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_tcsa2_field_t; + +typedef struct stc_mft_tcsc2_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_tcsc2_field_t; + +typedef struct stc_mft_tcal_field +{ + __IO uint32_t STOP00 :1; + __IO uint32_t STOP01 :1; + __IO uint32_t STOP02 :1; + __IO uint32_t STOP10 :1; + __IO uint32_t STOP11 :1; + __IO uint32_t STOP12 :1; + __IO uint32_t STOP20 :1; + __IO uint32_t STOP21 :1; + __IO uint32_t STOP22 :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t SCLR00 :1; + __IO uint32_t SCLR01 :1; + __IO uint32_t SCLR02 :1; + __IO uint32_t SCLR10 :1; + __IO uint32_t SCLR11 :1; + __IO uint32_t SCLR12 :1; + __IO uint32_t SCLR20 :1; + __IO uint32_t SCLR21 :1; + __IO uint32_t SCLR22 :1; + __IO uint32_t RESERVED1 :7; +} stc_mft_tcal_field_t; + +typedef struct stc_mft_ocfs10_field +{ + union { + struct { + __IO uint8_t FSO0 :4; + __IO uint8_t FSO1 :4; + }; + struct { + __IO uint8_t FSO00 :1; + __IO uint8_t FSO01 :1; + __IO uint8_t FSO02 :1; + __IO uint8_t FSO03 :1; + __IO uint8_t FSO10 :1; + __IO uint8_t FSO11 :1; + __IO uint8_t FSO12 :1; + __IO uint8_t FSO13 :1; + }; + }; +} stc_mft_ocfs10_field_t; + +typedef struct stc_mft_ocfs32_field +{ + union { + struct { + __IO uint8_t FSO2 :4; + __IO uint8_t FSO3 :4; + }; + struct { + __IO uint8_t FSO20 :1; + __IO uint8_t FSO21 :1; + __IO uint8_t FSO22 :1; + __IO uint8_t FSO23 :1; + __IO uint8_t FSO30 :1; + __IO uint8_t FSO31 :1; + __IO uint8_t FSO32 :1; + __IO uint8_t FSO33 :1; + }; + }; +} stc_mft_ocfs32_field_t; + +typedef struct stc_mft_ocfs54_field +{ + union { + struct { + __IO uint8_t FSO4 :4; + __IO uint8_t FSO5 :4; + }; + struct { + __IO uint8_t FSO40 :1; + __IO uint8_t FSO41 :1; + __IO uint8_t FSO42 :1; + __IO uint8_t FSO43 :1; + __IO uint8_t FSO50 :1; + __IO uint8_t FSO51 :1; + __IO uint8_t FSO52 :1; + __IO uint8_t FSO53 :1; + }; + }; +} stc_mft_ocfs54_field_t; + +typedef struct stc_mft_icfs10_field +{ + union { + struct { + __IO uint8_t FSI0 :4; + __IO uint8_t FSI1 :4; + }; + struct { + __IO uint8_t FSI00 :1; + __IO uint8_t FSI01 :1; + __IO uint8_t FSI02 :1; + __IO uint8_t FSI03 :1; + __IO uint8_t FSI10 :1; + __IO uint8_t FSI11 :1; + __IO uint8_t FSI12 :1; + __IO uint8_t FSI13 :1; + }; + }; +} stc_mft_icfs10_field_t; + +typedef struct stc_mft_icfs32_field +{ + union { + struct { + __IO uint8_t FSI2 :4; + __IO uint8_t FSI3 :4; + }; + struct { + __IO uint8_t FSI20 :1; + __IO uint8_t FSI21 :1; + __IO uint8_t FSI22 :1; + __IO uint8_t FSI23 :1; + __IO uint8_t FSI30 :1; + __IO uint8_t FSI31 :1; + __IO uint8_t FSI32 :1; + __IO uint8_t FSI33 :1; + }; + }; +} stc_mft_icfs32_field_t; + +typedef struct stc_mft_acfs10_field +{ + union { + struct { + __IO uint8_t FSA0 :4; + __IO uint8_t FSA1 :4; + }; + struct { + __IO uint8_t FSA00 :1; + __IO uint8_t FSA01 :1; + __IO uint8_t FSA02 :1; + __IO uint8_t FSA03 :1; + __IO uint8_t FSA10 :1; + __IO uint8_t FSA11 :1; + __IO uint8_t FSA12 :1; + __IO uint8_t FSA13 :1; + }; + }; +} stc_mft_acfs10_field_t; + +typedef struct stc_mft_acfs32_field +{ + union { + struct { + __IO uint8_t FSA2 :4; + __IO uint8_t FSA3 :4; + }; + struct { + __IO uint8_t FSA20 :1; + __IO uint8_t FSA21 :1; + __IO uint8_t FSA22 :1; + __IO uint8_t FSA23 :1; + __IO uint8_t FSA30 :1; + __IO uint8_t FSA31 :1; + __IO uint8_t FSA32 :1; + __IO uint8_t FSA33 :1; + }; + }; +} stc_mft_acfs32_field_t; + +typedef struct stc_mft_acfs54_field +{ + union { + struct { + __IO uint8_t FSA4 :4; + __IO uint8_t FSA5 :4; + }; + struct { + __IO uint8_t FSA40 :1; + __IO uint8_t FSA41 :1; + __IO uint8_t FSA42 :1; + __IO uint8_t FSA43 :1; + __IO uint8_t FSA50 :1; + __IO uint8_t FSA51 :1; + __IO uint8_t FSA52 :1; + __IO uint8_t FSA53 :1; + }; + }; +} stc_mft_acfs54_field_t; + +typedef struct stc_mft_icsa10_field +{ + union { + struct { + __IO uint8_t EG0 :2; + __IO uint8_t EG1 :2; + __IO uint8_t ICE0 :1; + __IO uint8_t ICE1 :1; + __IO uint8_t ICP0 :1; + __IO uint8_t ICP1 :1; + }; + struct { + __IO uint8_t EG00 :1; + __IO uint8_t EG01 :1; + __IO uint8_t EG10 :1; + __IO uint8_t EG11 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icsa10_field_t; + +typedef struct stc_mft_icsb10_field +{ + __IO uint8_t IEI0 :1; + __IO uint8_t IEI1 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icsb10_field_t; + +typedef struct stc_mft_icsa32_field +{ + union { + struct { + __IO uint8_t EG2 :2; + __IO uint8_t EG3 :2; + __IO uint8_t ICE2 :1; + __IO uint8_t ICE3 :1; + __IO uint8_t ICP2 :1; + __IO uint8_t ICP3 :1; + }; + struct { + __IO uint8_t EG20 :1; + __IO uint8_t EG21 :1; + __IO uint8_t EG30 :1; + __IO uint8_t EG31 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icsa32_field_t; + +typedef struct stc_mft_icsb32_field +{ + __IO uint8_t IEI2 :1; + __IO uint8_t IEI3 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icsb32_field_t; + +typedef struct stc_mft_wfsa10_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfsa10_field_t; + +typedef struct stc_mft_wfsa32_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfsa32_field_t; + +typedef struct stc_mft_wfsa54_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfsa54_field_t; + +typedef struct stc_mft_wfir_field +{ + __IO uint16_t DTIFA :1; + __IO uint16_t DTICA :1; + __IO uint16_t DTIFB :1; + __IO uint16_t DTICB :1; + __IO uint16_t TMIF10 :1; + __IO uint16_t TMIC10 :1; + __IO uint16_t TMIE10 :1; + __IO uint16_t TMIS10 :1; + __IO uint16_t TMIF32 :1; + __IO uint16_t TMIC32 :1; + __IO uint16_t TMIE32 :1; + __IO uint16_t TMIS32 :1; + __IO uint16_t TMIF54 :1; + __IO uint16_t TMIC54 :1; + __IO uint16_t TMIE54 :1; + __IO uint16_t TMIS54 :1; +} stc_mft_wfir_field_t; + +typedef struct stc_mft_nzcl_field +{ + union { + struct { + __IO uint16_t DTIEA :1; + __IO uint16_t NWS :3; + __IO uint16_t SDTI :1; + __IO uint16_t DTIEB :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t DHOLD :1; + __IO uint16_t DIMA :1; + __IO uint16_t DIMB :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t WIM10 :1; + __IO uint16_t WIM32 :1; + __IO uint16_t WIM54 :1; + __IO uint16_t RESERVED3 :1; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t NWS0 :1; + __IO uint16_t NWS1 :1; + __IO uint16_t NWS2 :1; + __IO uint16_t RESERVED4 :12; + }; + }; +} stc_mft_nzcl_field_t; + +typedef struct stc_mft_acmp0_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp0_field_t; + +typedef struct stc_mft_acmp1_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp1_field_t; + +typedef struct stc_mft_acmp2_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp2_field_t; + +typedef struct stc_mft_acmp3_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp3_field_t; + +typedef struct stc_mft_acmp4_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp4_field_t; + +typedef struct stc_mft_acmp5_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_acmp5_field_t; + +typedef struct stc_mft_acsa_field +{ + union { + struct { + __IO uint16_t CE10 :2; + __IO uint16_t CE32 :2; + __IO uint16_t CE54 :2; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SEL10 :2; + __IO uint16_t SEL32 :2; + __IO uint16_t SEL54 :2; + __IO uint16_t RESERVED2 :2; + }; + struct { + __IO uint16_t CE100 :1; + __IO uint16_t CE101 :1; + __IO uint16_t CE320 :1; + __IO uint16_t CE321 :1; + __IO uint16_t CE540 :1; + __IO uint16_t CE541 :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SEL100 :1; + __IO uint16_t SEL101 :1; + __IO uint16_t SEL320 :1; + __IO uint16_t SEL321 :1; + __IO uint16_t SEL540 :1; + __IO uint16_t SEL541 :1; + __IO uint16_t RESERVED3 :2; + }; + }; +} stc_mft_acsa_field_t; + +typedef struct stc_mft_acsc0_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc0_field_t; + +typedef struct stc_mft_acsd0_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd0_field_t; + +typedef struct stc_mft_acmc0_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc0_field_t; + +typedef struct stc_mft_acsc1_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc1_field_t; + +typedef struct stc_mft_acsd1_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd1_field_t; + +typedef struct stc_mft_acmc1_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc1_field_t; + +typedef struct stc_mft_acsc2_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc2_field_t; + +typedef struct stc_mft_acsd2_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd2_field_t; + +typedef struct stc_mft_acmc2_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc2_field_t; + +typedef struct stc_mft_acsc3_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc3_field_t; + +typedef struct stc_mft_acsd3_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd3_field_t; + +typedef struct stc_mft_acmc3_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc3_field_t; + +typedef struct stc_mft_acsc4_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc4_field_t; + +typedef struct stc_mft_acsd4_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd4_field_t; + +typedef struct stc_mft_acmc4_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc4_field_t; + +typedef struct stc_mft_acsc5_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_acsc5_field_t; + +typedef struct stc_mft_acsd5_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_acsd5_field_t; + +typedef struct stc_mft_acmc5_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_acmc5_field_t; + +typedef struct stc_mft_tcsd_field +{ + __IO uint8_t OFMD1 :1; + __IO uint8_t OFMD2 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_tcsd_field_t; + +typedef struct stc_mft_ocu_ocsa10_field +{ + __IO uint8_t CST0 :1; + __IO uint8_t CST1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE0 :1; + __IO uint8_t IOE1 :1; + __IO uint8_t IOP0 :1; + __IO uint8_t IOP1 :1; +} stc_mft_ocu_ocsa10_field_t; + +typedef struct stc_mft_ocu_ocsb10_field +{ + __IO uint8_t OTD0 :1; + __IO uint8_t OTD1 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocu_ocsb10_field_t; + +typedef struct stc_mft_ocu_ocsd10_field +{ + union { + struct { + __IO uint16_t OCCP0BUFE :2; + __IO uint16_t OCCP1BUFE :2; + __IO uint16_t OCSE0BUFE :2; + __IO uint16_t OCSE1BUFE :2; + __IO uint16_t OPBM0 :1; + __IO uint16_t OPBM1 :1; + __IO uint16_t OEBM0 :1; + __IO uint16_t OEBM1 :1; + __IO uint16_t OFEX0 :1; + __IO uint16_t OFEX1 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP0BUFE0 :1; + __IO uint16_t OCCP0BUFE1 :1; + __IO uint16_t OCCP1BUFE0 :1; + __IO uint16_t OCCP1BUFE1 :1; + __IO uint16_t OCSE0BUFE0 :1; + __IO uint16_t OCSE0BUFE1 :1; + __IO uint16_t OCSE1BUFE0 :1; + __IO uint16_t OCSE1BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocu_ocsd10_field_t; + +typedef struct stc_mft_ocu_ocsa32_field +{ + __IO uint8_t CST2 :1; + __IO uint8_t CST3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE2 :1; + __IO uint8_t IOE3 :1; + __IO uint8_t IOP2 :1; + __IO uint8_t IOP3 :1; +} stc_mft_ocu_ocsa32_field_t; + +typedef struct stc_mft_ocu_ocsb32_field +{ + __IO uint8_t OTD2 :1; + __IO uint8_t OTD3 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocu_ocsb32_field_t; + +typedef struct stc_mft_ocu_ocsd32_field +{ + union { + struct { + __IO uint16_t OCCP2BUFE :2; + __IO uint16_t OCCP3BUFE :2; + __IO uint16_t OCSE2BUFE :2; + __IO uint16_t OCSE3BUFE :2; + __IO uint16_t OPBM2 :1; + __IO uint16_t OPBM3 :1; + __IO uint16_t OEBM2 :1; + __IO uint16_t OEBM3 :1; + __IO uint16_t OFEX2 :1; + __IO uint16_t OFEX3 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP2BUFE0 :1; + __IO uint16_t OCCP2BUFE1 :1; + __IO uint16_t OCCP3BUFE0 :1; + __IO uint16_t OCCP3BUFE1 :1; + __IO uint16_t OCSE2BUFE0 :1; + __IO uint16_t OCSE2BUFE1 :1; + __IO uint16_t OCSE3BUFE0 :1; + __IO uint16_t OCSE3BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocu_ocsd32_field_t; + +typedef struct stc_mft_ocu_ocsa54_field +{ + __IO uint8_t CST4 :1; + __IO uint8_t CST5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t IOE4 :1; + __IO uint8_t IOE5 :1; + __IO uint8_t IOP4 :1; + __IO uint8_t IOP5 :1; +} stc_mft_ocu_ocsa54_field_t; + +typedef struct stc_mft_ocu_ocsb54_field +{ + __IO uint8_t OTD4 :1; + __IO uint8_t OTD5 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t CMOD :1; + __IO uint8_t RESERVED1 :2; + __IO uint8_t FM4 :1; +} stc_mft_ocu_ocsb54_field_t; + +typedef struct stc_mft_ocu_ocsd54_field +{ + union { + struct { + __IO uint16_t OCCP4BUFE :2; + __IO uint16_t OCCP5BUFE :2; + __IO uint16_t OCSE4BUFE :2; + __IO uint16_t OCSE5BUFE :2; + __IO uint16_t OPBM4 :1; + __IO uint16_t OPBM5 :1; + __IO uint16_t OEBM4 :1; + __IO uint16_t OEBM5 :1; + __IO uint16_t OFEX4 :1; + __IO uint16_t OFEX5 :1; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t OCCP4BUFE0 :1; + __IO uint16_t OCCP4BUFE1 :1; + __IO uint16_t OCCP5BUFE0 :1; + __IO uint16_t OCCP5BUFE1 :1; + __IO uint16_t OCSE4BUFE0 :1; + __IO uint16_t OCSE4BUFE1 :1; + __IO uint16_t OCSE5BUFE0 :1; + __IO uint16_t OCSE5BUFE1 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_mft_ocu_ocsd54_field_t; + +typedef struct stc_mft_ocu_ocsc_field +{ + __IO uint8_t MOD0 :1; + __IO uint8_t MOD1 :1; + __IO uint8_t MOD2 :1; + __IO uint8_t MOD3 :1; + __IO uint8_t MOD4 :1; + __IO uint8_t MOD5 :1; + __IO uint8_t RESERVED0 :2; +} stc_mft_ocu_ocsc_field_t; + +typedef struct stc_mft_ocu_ocse0_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocu_ocse0_field_t; + +typedef struct stc_mft_ocu_ocse1_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocu_ocse1_field_t; + +typedef struct stc_mft_ocu_ocse2_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocu_ocse2_field_t; + +typedef struct stc_mft_ocu_ocse3_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocu_ocse3_field_t; + +typedef struct stc_mft_ocu_ocse4_field +{ + union { + struct { + __IO uint16_t OCSE :16; + }; + struct { + __IO uint16_t OCSE0 :1; + __IO uint16_t OCSE1 :1; + __IO uint16_t OCSE2 :1; + __IO uint16_t OCSE3 :1; + __IO uint16_t OCSE4 :1; + __IO uint16_t OCSE5 :1; + __IO uint16_t OCSE6 :1; + __IO uint16_t OCSE7 :1; + __IO uint16_t OCSE8 :1; + __IO uint16_t OCSE9 :1; + __IO uint16_t OCSE10 :1; + __IO uint16_t OCSE11 :1; + __IO uint16_t OCSE12 :1; + __IO uint16_t OCSE13 :1; + __IO uint16_t OCSE14 :1; + __IO uint16_t OCSE15 :1; + }; + }; +} stc_mft_ocu_ocse4_field_t; + +typedef struct stc_mft_ocu_ocse5_field +{ + union { + struct { + __IO uint32_t OCSE :32; + }; + struct { + __IO uint32_t OCSE0 :1; + __IO uint32_t OCSE1 :1; + __IO uint32_t OCSE2 :1; + __IO uint32_t OCSE3 :1; + __IO uint32_t OCSE4 :1; + __IO uint32_t OCSE5 :1; + __IO uint32_t OCSE6 :1; + __IO uint32_t OCSE7 :1; + __IO uint32_t OCSE8 :1; + __IO uint32_t OCSE9 :1; + __IO uint32_t OCSE10 :1; + __IO uint32_t OCSE11 :1; + __IO uint32_t OCSE12 :1; + __IO uint32_t OCSE13 :1; + __IO uint32_t OCSE14 :1; + __IO uint32_t OCSE15 :1; + __IO uint32_t OCSE16 :1; + __IO uint32_t OCSE17 :1; + __IO uint32_t OCSE18 :1; + __IO uint32_t OCSE19 :1; + __IO uint32_t OCSE20 :1; + __IO uint32_t OCSE21 :1; + __IO uint32_t OCSE22 :1; + __IO uint32_t OCSE23 :1; + __IO uint32_t OCSE24 :1; + __IO uint32_t OCSE25 :1; + __IO uint32_t OCSE26 :1; + __IO uint32_t OCSE27 :1; + __IO uint32_t OCSE28 :1; + __IO uint32_t OCSE29 :1; + __IO uint32_t OCSE30 :1; + __IO uint32_t OCSE31 :1; + }; + }; +} stc_mft_ocu_ocse5_field_t; + +typedef struct stc_mft_frt_tccp0_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_frt_tccp0_field_t; + +typedef struct stc_mft_frt_tcsa0_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_frt_tcsa0_field_t; + +typedef struct stc_mft_frt_tcsc0_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_frt_tcsc0_field_t; + +typedef struct stc_mft_frt_tccp1_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_frt_tccp1_field_t; + +typedef struct stc_mft_frt_tcsa1_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_frt_tcsa1_field_t; + +typedef struct stc_mft_frt_tcsc1_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_frt_tcsc1_field_t; + +typedef struct stc_mft_frt_tccp2_field +{ + union { + struct { + __IO uint16_t TCCP :16; + }; + struct { + __IO uint16_t TCCP0 :1; + __IO uint16_t TCCP1 :1; + __IO uint16_t TCCP2 :1; + __IO uint16_t TCCP3 :1; + __IO uint16_t TCCP4 :1; + __IO uint16_t TCCP5 :1; + __IO uint16_t TCCP6 :1; + __IO uint16_t TCCP7 :1; + __IO uint16_t TCCP8 :1; + __IO uint16_t TCCP9 :1; + __IO uint16_t TCCP10 :1; + __IO uint16_t TCCP11 :1; + __IO uint16_t TCCP12 :1; + __IO uint16_t TCCP13 :1; + __IO uint16_t TCCP14 :1; + __IO uint16_t TCCP15 :1; + }; + }; +} stc_mft_frt_tccp2_field_t; + +typedef struct stc_mft_frt_tcsa2_field +{ + union { + struct { + __IO uint16_t CLK :4; + __IO uint16_t SCLR :1; + __IO uint16_t MODE :1; + __IO uint16_t STOP :1; + __IO uint16_t BFE :1; + __IO uint16_t ICRE :1; + __IO uint16_t ICLR :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t IRQZE :1; + __IO uint16_t IRQZF :1; + __IO uint16_t ECKE :1; + }; + struct { + __IO uint16_t CLK0 :1; + __IO uint16_t CLK1 :1; + __IO uint16_t CLK2 :1; + __IO uint16_t CLK3 :1; + __IO uint16_t RESERVED1 :12; + }; + }; +} stc_mft_frt_tcsa2_field_t; + +typedef struct stc_mft_frt_tcsc2_field +{ + union { + struct { + __IO uint16_t MSZI :4; + __IO uint16_t MSPI :4; + __IO uint16_t MSZC :4; + __IO uint16_t MSPC :4; + }; + struct { + __IO uint16_t MSZI0 :1; + __IO uint16_t MSZI1 :1; + __IO uint16_t MSZI2 :1; + __IO uint16_t MSZI3 :1; + __IO uint16_t MSPI0 :1; + __IO uint16_t MSPI1 :1; + __IO uint16_t MSPI2 :1; + __IO uint16_t MSPI3 :1; + __IO uint16_t MSZC0 :1; + __IO uint16_t MSZC1 :1; + __IO uint16_t MSZC2 :1; + __IO uint16_t MSZC3 :1; + __IO uint16_t MSPC0 :1; + __IO uint16_t MSPC1 :1; + __IO uint16_t MSPC2 :1; + __IO uint16_t MSPC3 :1; + }; + }; +} stc_mft_frt_tcsc2_field_t; + +typedef struct stc_mft_frt_tcal_field +{ + __IO uint32_t STOP00 :1; + __IO uint32_t STOP01 :1; + __IO uint32_t STOP02 :1; + __IO uint32_t STOP10 :1; + __IO uint32_t STOP11 :1; + __IO uint32_t STOP12 :1; + __IO uint32_t STOP20 :1; + __IO uint32_t STOP21 :1; + __IO uint32_t STOP22 :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t SCLR00 :1; + __IO uint32_t SCLR01 :1; + __IO uint32_t SCLR02 :1; + __IO uint32_t SCLR10 :1; + __IO uint32_t SCLR11 :1; + __IO uint32_t SCLR12 :1; + __IO uint32_t SCLR20 :1; + __IO uint32_t SCLR21 :1; + __IO uint32_t SCLR22 :1; + __IO uint32_t RESERVED1 :7; +} stc_mft_frt_tcal_field_t; + +typedef struct stc_mft_ocu_ocfs10_field +{ + union { + struct { + __IO uint8_t FSO0 :4; + __IO uint8_t FSO1 :4; + }; + struct { + __IO uint8_t FSO00 :1; + __IO uint8_t FSO01 :1; + __IO uint8_t FSO02 :1; + __IO uint8_t FSO03 :1; + __IO uint8_t FSO10 :1; + __IO uint8_t FSO11 :1; + __IO uint8_t FSO12 :1; + __IO uint8_t FSO13 :1; + }; + }; +} stc_mft_ocu_ocfs10_field_t; + +typedef struct stc_mft_ocu_ocfs32_field +{ + union { + struct { + __IO uint8_t FSO2 :4; + __IO uint8_t FSO3 :4; + }; + struct { + __IO uint8_t FSO20 :1; + __IO uint8_t FSO21 :1; + __IO uint8_t FSO22 :1; + __IO uint8_t FSO23 :1; + __IO uint8_t FSO30 :1; + __IO uint8_t FSO31 :1; + __IO uint8_t FSO32 :1; + __IO uint8_t FSO33 :1; + }; + }; +} stc_mft_ocu_ocfs32_field_t; + +typedef struct stc_mft_ocu_ocfs54_field +{ + union { + struct { + __IO uint8_t FSO4 :4; + __IO uint8_t FSO5 :4; + }; + struct { + __IO uint8_t FSO40 :1; + __IO uint8_t FSO41 :1; + __IO uint8_t FSO42 :1; + __IO uint8_t FSO43 :1; + __IO uint8_t FSO50 :1; + __IO uint8_t FSO51 :1; + __IO uint8_t FSO52 :1; + __IO uint8_t FSO53 :1; + }; + }; +} stc_mft_ocu_ocfs54_field_t; + +typedef struct stc_mft_icu_icfs10_field +{ + union { + struct { + __IO uint8_t FSI0 :4; + __IO uint8_t FSI1 :4; + }; + struct { + __IO uint8_t FSI00 :1; + __IO uint8_t FSI01 :1; + __IO uint8_t FSI02 :1; + __IO uint8_t FSI03 :1; + __IO uint8_t FSI10 :1; + __IO uint8_t FSI11 :1; + __IO uint8_t FSI12 :1; + __IO uint8_t FSI13 :1; + }; + }; +} stc_mft_icu_icfs10_field_t; + +typedef struct stc_mft_icu_icfs32_field +{ + union { + struct { + __IO uint8_t FSI2 :4; + __IO uint8_t FSI3 :4; + }; + struct { + __IO uint8_t FSI20 :1; + __IO uint8_t FSI21 :1; + __IO uint8_t FSI22 :1; + __IO uint8_t FSI23 :1; + __IO uint8_t FSI30 :1; + __IO uint8_t FSI31 :1; + __IO uint8_t FSI32 :1; + __IO uint8_t FSI33 :1; + }; + }; +} stc_mft_icu_icfs32_field_t; + +typedef struct stc_mft_adcmp_acfs10_field +{ + union { + struct { + __IO uint8_t FSA0 :4; + __IO uint8_t FSA1 :4; + }; + struct { + __IO uint8_t FSA00 :1; + __IO uint8_t FSA01 :1; + __IO uint8_t FSA02 :1; + __IO uint8_t FSA03 :1; + __IO uint8_t FSA10 :1; + __IO uint8_t FSA11 :1; + __IO uint8_t FSA12 :1; + __IO uint8_t FSA13 :1; + }; + }; +} stc_mft_adcmp_acfs10_field_t; + +typedef struct stc_mft_adcmp_acfs32_field +{ + union { + struct { + __IO uint8_t FSA2 :4; + __IO uint8_t FSA3 :4; + }; + struct { + __IO uint8_t FSA20 :1; + __IO uint8_t FSA21 :1; + __IO uint8_t FSA22 :1; + __IO uint8_t FSA23 :1; + __IO uint8_t FSA30 :1; + __IO uint8_t FSA31 :1; + __IO uint8_t FSA32 :1; + __IO uint8_t FSA33 :1; + }; + }; +} stc_mft_adcmp_acfs32_field_t; + +typedef struct stc_mft_adcmp_acfs54_field +{ + union { + struct { + __IO uint8_t FSA4 :4; + __IO uint8_t FSA5 :4; + }; + struct { + __IO uint8_t FSA40 :1; + __IO uint8_t FSA41 :1; + __IO uint8_t FSA42 :1; + __IO uint8_t FSA43 :1; + __IO uint8_t FSA50 :1; + __IO uint8_t FSA51 :1; + __IO uint8_t FSA52 :1; + __IO uint8_t FSA53 :1; + }; + }; +} stc_mft_adcmp_acfs54_field_t; + +typedef struct stc_mft_icu_icsa10_field +{ + union { + struct { + __IO uint8_t EG0 :2; + __IO uint8_t EG1 :2; + __IO uint8_t ICE0 :1; + __IO uint8_t ICE1 :1; + __IO uint8_t ICP0 :1; + __IO uint8_t ICP1 :1; + }; + struct { + __IO uint8_t EG00 :1; + __IO uint8_t EG01 :1; + __IO uint8_t EG10 :1; + __IO uint8_t EG11 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icu_icsa10_field_t; + +typedef struct stc_mft_icu_icsb10_field +{ + __IO uint8_t IEI0 :1; + __IO uint8_t IEI1 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icu_icsb10_field_t; + +typedef struct stc_mft_icu_icsa32_field +{ + union { + struct { + __IO uint8_t EG2 :2; + __IO uint8_t EG3 :2; + __IO uint8_t ICE2 :1; + __IO uint8_t ICE3 :1; + __IO uint8_t ICP2 :1; + __IO uint8_t ICP3 :1; + }; + struct { + __IO uint8_t EG20 :1; + __IO uint8_t EG21 :1; + __IO uint8_t EG30 :1; + __IO uint8_t EG31 :1; + __IO uint8_t RESERVED0 :4; + }; + }; +} stc_mft_icu_icsa32_field_t; + +typedef struct stc_mft_icu_icsb32_field +{ + __IO uint8_t IEI2 :1; + __IO uint8_t IEI3 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_icu_icsb32_field_t; + +typedef struct stc_mft_wfg_wfsa10_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfg_wfsa10_field_t; + +typedef struct stc_mft_wfg_wfsa32_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfg_wfsa32_field_t; + +typedef struct stc_mft_wfg_wfsa54_field +{ + union { + struct { + __IO uint16_t DCK :3; + __IO uint16_t TMD :3; + __IO uint16_t GTEN :2; + __IO uint16_t PSEL :2; + __IO uint16_t PGEN :2; + __IO uint16_t DMOD :2; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t DCK0 :1; + __IO uint16_t DCK1 :1; + __IO uint16_t DCK2 :1; + __IO uint16_t TMD0 :1; + __IO uint16_t TMD1 :1; + __IO uint16_t TMD2 :1; + __IO uint16_t GTEN0 :1; + __IO uint16_t GTEN1 :1; + __IO uint16_t PSEL0 :1; + __IO uint16_t PSEL1 :1; + __IO uint16_t PGEN0 :1; + __IO uint16_t PGEN1 :1; + __IO uint16_t DMOD0 :1; + __IO uint16_t DMOD1 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_mft_wfg_wfsa54_field_t; + +typedef struct stc_mft_wfg_wfir_field +{ + __IO uint16_t DTIFA :1; + __IO uint16_t DTICA :1; + __IO uint16_t DTIFB :1; + __IO uint16_t DTICB :1; + __IO uint16_t TMIF10 :1; + __IO uint16_t TMIC10 :1; + __IO uint16_t TMIE10 :1; + __IO uint16_t TMIS10 :1; + __IO uint16_t TMIF32 :1; + __IO uint16_t TMIC32 :1; + __IO uint16_t TMIE32 :1; + __IO uint16_t TMIS32 :1; + __IO uint16_t TMIF54 :1; + __IO uint16_t TMIC54 :1; + __IO uint16_t TMIE54 :1; + __IO uint16_t TMIS54 :1; +} stc_mft_wfg_wfir_field_t; + +typedef struct stc_mft_wfg_nzcl_field +{ + union { + struct { + __IO uint16_t DTIEA :1; + __IO uint16_t NWS :3; + __IO uint16_t SDTI :1; + __IO uint16_t DTIEB :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t DHOLD :1; + __IO uint16_t DIMA :1; + __IO uint16_t DIMB :1; + __IO uint16_t RESERVED2 :2; + __IO uint16_t WIM10 :1; + __IO uint16_t WIM32 :1; + __IO uint16_t WIM54 :1; + __IO uint16_t RESERVED3 :1; + }; + struct { + __IO uint16_t RESERVED0 :1; + __IO uint16_t NWS0 :1; + __IO uint16_t NWS1 :1; + __IO uint16_t NWS2 :1; + __IO uint16_t RESERVED4 :12; + }; + }; +} stc_mft_wfg_nzcl_field_t; + +typedef struct stc_mft_adcmp_acmp0_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp0_field_t; + +typedef struct stc_mft_adcmp_acmp1_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp1_field_t; + +typedef struct stc_mft_adcmp_acmp2_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp2_field_t; + +typedef struct stc_mft_adcmp_acmp3_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp3_field_t; + +typedef struct stc_mft_adcmp_acmp4_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp4_field_t; + +typedef struct stc_mft_adcmp_acmp5_field +{ + union { + struct { + __IO uint16_t ACMP :16; + }; + struct { + __IO uint16_t ACMP0 :1; + __IO uint16_t ACMP1 :1; + __IO uint16_t ACMP2 :1; + __IO uint16_t ACMP3 :1; + __IO uint16_t ACMP4 :1; + __IO uint16_t ACMP5 :1; + __IO uint16_t ACMP6 :1; + __IO uint16_t ACMP7 :1; + __IO uint16_t ACMP8 :1; + __IO uint16_t ACMP9 :1; + __IO uint16_t ACMP10 :1; + __IO uint16_t ACMP11 :1; + __IO uint16_t ACMP12 :1; + __IO uint16_t ACMP13 :1; + __IO uint16_t ACMP14 :1; + __IO uint16_t ACMP15 :1; + }; + }; +} stc_mft_adcmp_acmp5_field_t; + +typedef struct stc_mft_adcmp_acsa_field +{ + union { + struct { + __IO uint16_t CE10 :2; + __IO uint16_t CE32 :2; + __IO uint16_t CE54 :2; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SEL10 :2; + __IO uint16_t SEL32 :2; + __IO uint16_t SEL54 :2; + __IO uint16_t RESERVED2 :2; + }; + struct { + __IO uint16_t CE100 :1; + __IO uint16_t CE101 :1; + __IO uint16_t CE320 :1; + __IO uint16_t CE321 :1; + __IO uint16_t CE540 :1; + __IO uint16_t CE541 :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SEL100 :1; + __IO uint16_t SEL101 :1; + __IO uint16_t SEL320 :1; + __IO uint16_t SEL321 :1; + __IO uint16_t SEL540 :1; + __IO uint16_t SEL541 :1; + __IO uint16_t RESERVED3 :2; + }; + }; +} stc_mft_adcmp_acsa_field_t; + +typedef struct stc_mft_adcmp_acsc0_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc0_field_t; + +typedef struct stc_mft_adcmp_acsd0_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd0_field_t; + +typedef struct stc_mft_adcmp_acmc0_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc0_field_t; + +typedef struct stc_mft_adcmp_acsc1_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc1_field_t; + +typedef struct stc_mft_adcmp_acsd1_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd1_field_t; + +typedef struct stc_mft_adcmp_acmc1_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc1_field_t; + +typedef struct stc_mft_adcmp_acsc2_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc2_field_t; + +typedef struct stc_mft_adcmp_acsd2_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd2_field_t; + +typedef struct stc_mft_adcmp_acmc2_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc2_field_t; + +typedef struct stc_mft_adcmp_acsc3_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc3_field_t; + +typedef struct stc_mft_adcmp_acsd3_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd3_field_t; + +typedef struct stc_mft_adcmp_acmc3_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc3_field_t; + +typedef struct stc_mft_adcmp_acsc4_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc4_field_t; + +typedef struct stc_mft_adcmp_acsd4_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd4_field_t; + +typedef struct stc_mft_adcmp_acmc4_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc4_field_t; + +typedef struct stc_mft_adcmp_acsc5_field +{ + union { + struct { + __IO uint8_t BUFE :2; + __IO uint8_t ADSEL :3; + __IO uint8_t APBM :1; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t BUFE0 :1; + __IO uint8_t BUFE1 :1; + __IO uint8_t ADSEL0 :1; + __IO uint8_t ADSEL1 :1; + __IO uint8_t ADSEL2 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_adcmp_acsc5_field_t; + +typedef struct stc_mft_adcmp_acsd5_field +{ + __IO uint8_t AMOD :1; + __IO uint8_t OCUS :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t DE :1; + __IO uint8_t PE :1; + __IO uint8_t UE :1; + __IO uint8_t ZE :1; +} stc_mft_adcmp_acsd5_field_t; + +typedef struct stc_mft_adcmp_acmc5_field +{ + union { + struct { + __IO uint8_t AMC :4; + __IO uint8_t RESERVED0 :2; + __IO uint8_t MZCE :1; + __IO uint8_t MPCE :1; + }; + struct { + __IO uint8_t AMC0 :1; + __IO uint8_t AMC1 :1; + __IO uint8_t AMC2 :1; + __IO uint8_t AMC3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_adcmp_acmc5_field_t; + +typedef struct stc_mft_frt_tcsd_field +{ + __IO uint8_t OFMD1 :1; + __IO uint8_t OFMD2 :1; + __IO uint8_t RESERVED0 :6; +} stc_mft_frt_tcsd_field_t; + +/******************************************************************************* +* MFT_PPG_MODULE +*******************************************************************************/ +typedef struct stc_mft_ppg_ttcr0_field +{ + union { + struct { + __IO uint8_t STR0 :1; + __IO uint8_t MONI0 :1; + __IO uint8_t CS0 :2; + __IO uint8_t TRG0O :1; + __IO uint8_t TRG2O :1; + __IO uint8_t TRG4O :1; + __IO uint8_t TRG6O :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS00 :1; + __IO uint8_t CS01 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_ppg_ttcr0_field_t; + +typedef struct stc_mft_ppg_ttcr1_field +{ + union { + struct { + __IO uint8_t STR1 :1; + __IO uint8_t MONI1 :1; + __IO uint8_t CS1 :2; + __IO uint8_t TRG1O :1; + __IO uint8_t TRG3O :1; + __IO uint8_t TRG5O :1; + __IO uint8_t TRG7O :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS10 :1; + __IO uint8_t CS11 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_ppg_ttcr1_field_t; + +typedef struct stc_mft_ppg_ttcr2_field +{ + union { + struct { + __IO uint8_t STR2 :1; + __IO uint8_t MONI2 :1; + __IO uint8_t CS2 :2; + __IO uint8_t TRG16O :1; + __IO uint8_t TRG18O :1; + __IO uint8_t TRG20O :1; + __IO uint8_t TRG22O :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS20 :1; + __IO uint8_t CS21 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_mft_ppg_ttcr2_field_t; + +typedef struct stc_mft_ppg_trg0_field +{ + __IO uint16_t PEN00 :1; + __IO uint16_t PEN01 :1; + __IO uint16_t PEN02 :1; + __IO uint16_t PEN03 :1; + __IO uint16_t PEN04 :1; + __IO uint16_t PEN05 :1; + __IO uint16_t PEN06 :1; + __IO uint16_t PEN07 :1; + __IO uint16_t PEN08 :1; + __IO uint16_t PEN09 :1; + __IO uint16_t PEN10 :1; + __IO uint16_t PEN11 :1; + __IO uint16_t PEN12 :1; + __IO uint16_t PEN13 :1; + __IO uint16_t PEN14 :1; + __IO uint16_t PEN15 :1; +} stc_mft_ppg_trg0_field_t; + +typedef struct stc_mft_ppg_revc0_field +{ + __IO uint16_t REV00 :1; + __IO uint16_t REV01 :1; + __IO uint16_t REV02 :1; + __IO uint16_t REV03 :1; + __IO uint16_t REV04 :1; + __IO uint16_t REV05 :1; + __IO uint16_t REV06 :1; + __IO uint16_t REV07 :1; + __IO uint16_t REV08 :1; + __IO uint16_t REV09 :1; + __IO uint16_t REV10 :1; + __IO uint16_t REV11 :1; + __IO uint16_t REV12 :1; + __IO uint16_t REV13 :1; + __IO uint16_t REV14 :1; + __IO uint16_t REV15 :1; +} stc_mft_ppg_revc0_field_t; + +typedef struct stc_mft_ppg_trg1_field +{ + __IO uint16_t PEN16 :1; + __IO uint16_t PEN17 :1; + __IO uint16_t PEN18 :1; + __IO uint16_t PEN19 :1; + __IO uint16_t PEN20 :1; + __IO uint16_t PEN21 :1; + __IO uint16_t PEN22 :1; + __IO uint16_t PEN23 :1; + __IO uint16_t RESERVED0 :8; +} stc_mft_ppg_trg1_field_t; + +typedef struct stc_mft_ppg_revc1_field +{ + __IO uint16_t REV16 :1; + __IO uint16_t REV17 :1; + __IO uint16_t REV18 :1; + __IO uint16_t REV19 :1; + __IO uint16_t REV20 :1; + __IO uint16_t REV21 :1; + __IO uint16_t REV22 :1; + __IO uint16_t REV23 :1; + __IO uint16_t RESERVED0 :8; +} stc_mft_ppg_revc1_field_t; + +typedef struct stc_mft_ppg_ppgc1_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc1_field_t; + +typedef struct stc_mft_ppg_ppgc0_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc0_field_t; + +typedef struct stc_mft_ppg_ppgc3_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc3_field_t; + +typedef struct stc_mft_ppg_ppgc2_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc2_field_t; + +typedef struct stc_mft_ppg_prll0_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll0_field_t; + +typedef struct stc_mft_ppg_prlh0_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh0_field_t; + +typedef struct stc_mft_ppg_prll1_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll1_field_t; + +typedef struct stc_mft_ppg_prlh1_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh1_field_t; + +typedef struct stc_mft_ppg_prll2_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll2_field_t; + +typedef struct stc_mft_ppg_prlh2_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh2_field_t; + +typedef struct stc_mft_ppg_prll3_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll3_field_t; + +typedef struct stc_mft_ppg_prlh3_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh3_field_t; + +typedef struct stc_mft_ppg_gatec0_field +{ + __IO uint8_t EDGE0 :1; + __IO uint8_t STRG0 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE2 :1; + __IO uint8_t STRG2 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec0_field_t; + +typedef struct stc_mft_ppg_ppgc5_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc5_field_t; + +typedef struct stc_mft_ppg_ppgc4_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc4_field_t; + +typedef struct stc_mft_ppg_ppgc7_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc7_field_t; + +typedef struct stc_mft_ppg_ppgc6_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc6_field_t; + +typedef struct stc_mft_ppg_prll4_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll4_field_t; + +typedef struct stc_mft_ppg_prlh4_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh4_field_t; + +typedef struct stc_mft_ppg_prll5_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll5_field_t; + +typedef struct stc_mft_ppg_prlh5_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh5_field_t; + +typedef struct stc_mft_ppg_prll6_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll6_field_t; + +typedef struct stc_mft_ppg_prlh6_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh6_field_t; + +typedef struct stc_mft_ppg_prll7_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll7_field_t; + +typedef struct stc_mft_ppg_prlh7_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh7_field_t; + +typedef struct stc_mft_ppg_gatec4_field +{ + __IO uint8_t EDGE4 :1; + __IO uint8_t STRG4 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE6 :1; + __IO uint8_t STRG6 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec4_field_t; + +typedef struct stc_mft_ppg_ppgc9_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc9_field_t; + +typedef struct stc_mft_ppg_ppgc8_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc8_field_t; + +typedef struct stc_mft_ppg_ppgc11_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc11_field_t; + +typedef struct stc_mft_ppg_ppgc10_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc10_field_t; + +typedef struct stc_mft_ppg_prll8_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll8_field_t; + +typedef struct stc_mft_ppg_prlh8_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh8_field_t; + +typedef struct stc_mft_ppg_prll9_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll9_field_t; + +typedef struct stc_mft_ppg_prlh9_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh9_field_t; + +typedef struct stc_mft_ppg_prll10_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll10_field_t; + +typedef struct stc_mft_ppg_prlh10_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh10_field_t; + +typedef struct stc_mft_ppg_prll11_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll11_field_t; + +typedef struct stc_mft_ppg_prlh11_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh11_field_t; + +typedef struct stc_mft_ppg_gatec8_field +{ + __IO uint8_t EDGE8 :1; + __IO uint8_t STRG8 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE10 :1; + __IO uint8_t STRG10 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec8_field_t; + +typedef struct stc_mft_ppg_ppgc13_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc13_field_t; + +typedef struct stc_mft_ppg_ppgc12_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc12_field_t; + +typedef struct stc_mft_ppg_ppgc15_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc15_field_t; + +typedef struct stc_mft_ppg_ppgc14_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc14_field_t; + +typedef struct stc_mft_ppg_prll12_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll12_field_t; + +typedef struct stc_mft_ppg_prlh12_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh12_field_t; + +typedef struct stc_mft_ppg_prll13_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll13_field_t; + +typedef struct stc_mft_ppg_prlh13_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh13_field_t; + +typedef struct stc_mft_ppg_prll14_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll14_field_t; + +typedef struct stc_mft_ppg_prlh14_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh14_field_t; + +typedef struct stc_mft_ppg_prll15_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll15_field_t; + +typedef struct stc_mft_ppg_prlh15_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh15_field_t; + +typedef struct stc_mft_ppg_gatec12_field +{ + __IO uint8_t EDGE12 :1; + __IO uint8_t STRG12 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE14 :1; + __IO uint8_t STRG14 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec12_field_t; + +typedef struct stc_mft_ppg_ppgc17_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc17_field_t; + +typedef struct stc_mft_ppg_ppgc16_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc16_field_t; + +typedef struct stc_mft_ppg_ppgc19_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc19_field_t; + +typedef struct stc_mft_ppg_ppgc18_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc18_field_t; + +typedef struct stc_mft_ppg_prll16_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll16_field_t; + +typedef struct stc_mft_ppg_prlh16_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh16_field_t; + +typedef struct stc_mft_ppg_prll17_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll17_field_t; + +typedef struct stc_mft_ppg_prlh17_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh17_field_t; + +typedef struct stc_mft_ppg_prll18_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll18_field_t; + +typedef struct stc_mft_ppg_prlh18_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh18_field_t; + +typedef struct stc_mft_ppg_prll19_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll19_field_t; + +typedef struct stc_mft_ppg_prlh19_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh19_field_t; + +typedef struct stc_mft_ppg_gatec16_field +{ + __IO uint8_t EDGE16 :1; + __IO uint8_t STRG16 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE18 :1; + __IO uint8_t STRG18 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec16_field_t; + +typedef struct stc_mft_ppg_ppgc21_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc21_field_t; + +typedef struct stc_mft_ppg_ppgc20_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc20_field_t; + +typedef struct stc_mft_ppg_ppgc23_field +{ + union { + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED1 :3; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED2 :3; + }; + }; +} stc_mft_ppg_ppgc23_field_t; + +typedef struct stc_mft_ppg_ppgc22_field +{ + union { + struct { + __IO uint8_t TTRG :1; + __IO uint8_t MD :2; + __IO uint8_t PCS :2; + __IO uint8_t INTM :1; + __IO uint8_t PUF :1; + __IO uint8_t PIE :1; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t MD0 :1; + __IO uint8_t MD1 :1; + __IO uint8_t PCS0 :1; + __IO uint8_t PCS1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_mft_ppg_ppgc22_field_t; + +typedef struct stc_mft_ppg_prll20_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll20_field_t; + +typedef struct stc_mft_ppg_prlh20_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh20_field_t; + +typedef struct stc_mft_ppg_prll21_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll21_field_t; + +typedef struct stc_mft_ppg_prlh21_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh21_field_t; + +typedef struct stc_mft_ppg_prll22_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll22_field_t; + +typedef struct stc_mft_ppg_prlh22_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh22_field_t; + +typedef struct stc_mft_ppg_prll23_field +{ + union { + struct { + __IO uint8_t PRLL :8; + }; + struct { + __IO uint8_t PRLL0 :1; + __IO uint8_t PRLL1 :1; + __IO uint8_t PRLL2 :1; + __IO uint8_t PRLL3 :1; + __IO uint8_t PRLL4 :1; + __IO uint8_t PRLL5 :1; + __IO uint8_t PRLL6 :1; + __IO uint8_t PRLL7 :1; + }; + }; +} stc_mft_ppg_prll23_field_t; + +typedef struct stc_mft_ppg_prlh23_field +{ + union { + struct { + __IO uint8_t PRLH :8; + }; + struct { + __IO uint8_t PRLH0 :1; + __IO uint8_t PRLH1 :1; + __IO uint8_t PRLH2 :1; + __IO uint8_t PRLH3 :1; + __IO uint8_t PRLH4 :1; + __IO uint8_t PRLH5 :1; + __IO uint8_t PRLH6 :1; + __IO uint8_t PRLH7 :1; + }; + }; +} stc_mft_ppg_prlh23_field_t; + +typedef struct stc_mft_ppg_gatec20_field +{ + __IO uint8_t EDGE20 :1; + __IO uint8_t STRG20 :1; + __IO uint8_t RESERVED0 :2; + __IO uint8_t EDGE22 :1; + __IO uint8_t STRG22 :1; + __IO uint8_t RESERVED1 :2; +} stc_mft_ppg_gatec20_field_t; + +/******************************************************************************* +* PCRC_MODULE +*******************************************************************************/ +typedef struct stc_pcrc_pcrc_cfg_field +{ + union { + struct { + __IO uint32_t CIRQCLR :1; + __IO uint32_t RESERVED0 :7; + __IO uint32_t FO :2; + __IO uint32_t FI :2; + __IO uint32_t RESERVED2 :4; + __IO uint32_t TEST :6; + __IO uint32_t SZ :2; + __IO uint32_t CIRQ :1; + __IO uint32_t CIEN :1; + __IO uint32_t CDEN :1; + __IO uint32_t RESERVED4 :1; + __IO uint32_t LOCK :1; + __IO uint32_t RESERVED5 :3; + }; + struct { + __IO uint32_t RESERVED1 :8; + __IO uint32_t FO0 :1; + __IO uint32_t FO1 :1; + __IO uint32_t FI0 :1; + __IO uint32_t FI1 :1; + __IO uint32_t RESERVED3 :4; + __IO uint32_t TEST0 :1; + __IO uint32_t TEST1 :1; + __IO uint32_t TEST2 :1; + __IO uint32_t TEST3 :1; + __IO uint32_t TEST4 :1; + __IO uint32_t TEST5 :1; + __IO uint32_t SZ0 :1; + __IO uint32_t SZ1 :1; + __IO uint32_t RESERVED6 :8; + }; + }; +} stc_pcrc_pcrc_cfg_field_t; + +/******************************************************************************* +* QPRC_MODULE +*******************************************************************************/ +typedef struct stc_qprc_qicrl_field +{ + __IO uint8_t QPCMIE :1; + __IO uint8_t QPCMF :1; + __IO uint8_t QPRCMIE :1; + __IO uint8_t QPRCMF :1; + __IO uint8_t OUZIE :1; + __IO uint8_t UFDF :1; + __IO uint8_t OFDF :1; + __IO uint8_t ZIIF :1; +} stc_qprc_qicrl_field_t; + +typedef struct stc_qprc_qicrh_field +{ + __IO uint8_t CDCIE :1; + __IO uint8_t CDCF :1; + __IO uint8_t DIRPC :1; + __IO uint8_t DIROU :1; + __IO uint8_t QPCNRCMIE :1; + __IO uint8_t QPCNRCMF :1; + __IO uint8_t RESERVED0 :2; +} stc_qprc_qicrh_field_t; + +typedef struct stc_qprc_qcr_field +{ + union { + struct { + __IO uint16_t PCM :2; + __IO uint16_t RCM :2; + __IO uint16_t PSTP :1; + __IO uint16_t CGSC :1; + __IO uint16_t RSEL :1; + __IO uint16_t SWAP :1; + __IO uint16_t PCRM :2; + __IO uint16_t AES :2; + __IO uint16_t BES :2; + __IO uint16_t CGE :2; + }; + struct { + __IO uint16_t PCM0 :1; + __IO uint16_t PCM1 :1; + __IO uint16_t RCM0 :1; + __IO uint16_t RCM1 :1; + __IO uint16_t RESERVED0 :4; + __IO uint16_t PCRM0 :1; + __IO uint16_t PCRM1 :1; + __IO uint16_t AES0 :1; + __IO uint16_t AES1 :1; + __IO uint16_t BES0 :1; + __IO uint16_t BES1 :1; + __IO uint16_t CGE0 :1; + __IO uint16_t CGE1 :1; + }; + }; +} stc_qprc_qcr_field_t; + +typedef struct stc_qprc_qecr_field +{ + __IO uint16_t ORNGMD :1; + __IO uint16_t ORNGF :1; + __IO uint16_t ORNGIE :1; + __IO uint16_t PEC :1; + __IO uint16_t RESERVED0 :12; +} stc_qprc_qecr_field_t; + +typedef struct stc_qprc_qprcrr_field +{ + union { + struct { + __IO uint32_t QPCRR :16; + __IO uint32_t QRCRR :16; + }; + struct { + __IO uint32_t QPCRR0 :1; + __IO uint32_t QPCRR1 :1; + __IO uint32_t QPCRR2 :1; + __IO uint32_t QPCRR3 :1; + __IO uint32_t QPCRR4 :1; + __IO uint32_t QPCRR5 :1; + __IO uint32_t QPCRR6 :1; + __IO uint32_t QPCRR7 :1; + __IO uint32_t QPCRR8 :1; + __IO uint32_t QPCRR9 :1; + __IO uint32_t QPCRR10 :1; + __IO uint32_t QPCRR11 :1; + __IO uint32_t QPCRR12 :1; + __IO uint32_t QPCRR13 :1; + __IO uint32_t QPCRR14 :1; + __IO uint32_t QPCRR15 :1; + __IO uint32_t QRCRR0 :1; + __IO uint32_t QRCRR1 :1; + __IO uint32_t QRCRR2 :1; + __IO uint32_t QRCRR3 :1; + __IO uint32_t QRCRR4 :1; + __IO uint32_t QRCRR5 :1; + __IO uint32_t QRCRR6 :1; + __IO uint32_t QRCRR7 :1; + __IO uint32_t QRCRR8 :1; + __IO uint32_t QRCRR9 :1; + __IO uint32_t QRCRR10 :1; + __IO uint32_t QRCRR11 :1; + __IO uint32_t QRCRR12 :1; + __IO uint32_t QRCRR13 :1; + __IO uint32_t QRCRR14 :1; + __IO uint32_t QRCRR15 :1; + }; + }; +} stc_qprc_qprcrr_field_t; + +/******************************************************************************* +* QPRC_NF_MODULE +*******************************************************************************/ +typedef struct stc_qprc_nf_nfctla_field +{ + union { + struct { + __IO uint8_t AINNWS :3; + __IO uint8_t RESERVED0 :1; + __IO uint8_t AINLV :1; + __IO uint8_t AINMD :1; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t AINNWS0 :1; + __IO uint8_t AINNWS1 :1; + __IO uint8_t AINNWS2 :1; + __IO uint8_t RESERVED2 :5; + }; + }; +} stc_qprc_nf_nfctla_field_t; + +typedef struct stc_qprc_nf_nfctlb_field +{ + union { + struct { + __IO uint8_t BINNWS :3; + __IO uint8_t RESERVED0 :1; + __IO uint8_t BINLV :1; + __IO uint8_t BINMD :1; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t BINNWS0 :1; + __IO uint8_t BINNWS1 :1; + __IO uint8_t BINNWS2 :1; + __IO uint8_t RESERVED2 :5; + }; + }; +} stc_qprc_nf_nfctlb_field_t; + +typedef struct stc_qprc_nf_nfctlz_field +{ + union { + struct { + __IO uint8_t ZINNWS :3; + __IO uint8_t RESERVED0 :1; + __IO uint8_t ZINLV :1; + __IO uint8_t ZINMD :1; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t ZINNWS0 :1; + __IO uint8_t ZINNWS1 :1; + __IO uint8_t ZINNWS2 :1; + __IO uint8_t RESERVED2 :5; + }; + }; +} stc_qprc_nf_nfctlz_field_t; + +/******************************************************************************* +* RTC_MODULE +*******************************************************************************/ +typedef struct stc_rtc_wtcr10_field +{ + __IO uint8_t ST :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t RUN :1; + __IO uint8_t SRST :1; + __IO uint8_t SCST :1; + __IO uint8_t SCRST :1; + __IO uint8_t BUSY :1; + __IO uint8_t TRANS :1; +} stc_rtc_wtcr10_field_t; + +typedef struct stc_rtc_wtcr11_field +{ + __IO uint8_t MIEN :1; + __IO uint8_t HEN :1; + __IO uint8_t DEN :1; + __IO uint8_t MOEN :1; + __IO uint8_t YEN :1; + __IO uint8_t RESERVED0 :3; +} stc_rtc_wtcr11_field_t; + +typedef struct stc_rtc_wtcr12_field +{ + __IO uint8_t INTSSI :1; + __IO uint8_t INTSI :1; + __IO uint8_t INTMI :1; + __IO uint8_t INTHI :1; + __IO uint8_t INTTMI :1; + __IO uint8_t INTALI :1; + __IO uint8_t INTERI :1; + __IO uint8_t INTCRI :1; +} stc_rtc_wtcr12_field_t; + +typedef struct stc_rtc_wtcr13_field +{ + __IO uint8_t INTSSIE :1; + __IO uint8_t INTSIE :1; + __IO uint8_t INTMIE :1; + __IO uint8_t INTHIE :1; + __IO uint8_t INTTMIE :1; + __IO uint8_t INTALIE :1; + __IO uint8_t INTERIE :1; + __IO uint8_t INTCRIE :1; +} stc_rtc_wtcr13_field_t; + +typedef struct stc_rtc_wtcr20_field +{ + __IO uint8_t CREAD :1; + __IO uint8_t CWRITE :1; + __IO uint8_t BREAD :1; + __IO uint8_t BWRITE :1; + __IO uint8_t PREAD :1; + __IO uint8_t PWRITE :1; + __IO uint8_t RESERVED0 :2; +} stc_rtc_wtcr20_field_t; + +typedef struct stc_rtc_wtcr21_field +{ + __IO uint8_t TMST :1; + __IO uint8_t TMEN :1; + __IO uint8_t TMRUN :1; + __IO uint8_t RESERVED0 :5; +} stc_rtc_wtcr21_field_t; + +typedef struct stc_rtc_wtsr_field +{ + union { + struct { + __IO uint8_t S :4; + __IO uint8_t TS :3; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t S0 :1; + __IO uint8_t S1 :1; + __IO uint8_t S2 :1; + __IO uint8_t S3 :1; + __IO uint8_t TS0 :1; + __IO uint8_t TS1 :1; + __IO uint8_t TS2 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_rtc_wtsr_field_t; + +typedef struct stc_rtc_wtmir_field +{ + union { + struct { + __IO uint8_t MI :4; + __IO uint8_t TMI :3; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t MI0 :1; + __IO uint8_t MI1 :1; + __IO uint8_t MI2 :1; + __IO uint8_t MI3 :1; + __IO uint8_t TMI0 :1; + __IO uint8_t TMI1 :1; + __IO uint8_t TMI2 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_rtc_wtmir_field_t; + +typedef struct stc_rtc_wthr_field +{ + union { + struct { + __IO uint8_t H :4; + __IO uint8_t TH :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t H0 :1; + __IO uint8_t H1 :1; + __IO uint8_t H2 :1; + __IO uint8_t H3 :1; + __IO uint8_t TH0 :1; + __IO uint8_t TH1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_wthr_field_t; + +typedef struct stc_rtc_wtdr_field +{ + union { + struct { + __IO uint8_t D :4; + __IO uint8_t TD :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t D0 :1; + __IO uint8_t D1 :1; + __IO uint8_t D2 :1; + __IO uint8_t D3 :1; + __IO uint8_t TD0 :1; + __IO uint8_t TD1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_wtdr_field_t; + +typedef struct stc_rtc_wtdw_field +{ + union { + struct { + __IO uint8_t DW :3; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t DW0 :1; + __IO uint8_t DW1 :1; + __IO uint8_t DW2 :1; + __IO uint8_t RESERVED1 :5; + }; + }; +} stc_rtc_wtdw_field_t; + +typedef struct stc_rtc_wtmor_field +{ + union { + struct { + __IO uint8_t MO :4; + __IO uint8_t TMO :1; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t MO0 :1; + __IO uint8_t MO1 :1; + __IO uint8_t MO2 :1; + __IO uint8_t MO3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_rtc_wtmor_field_t; + +typedef struct stc_rtc_wtyr_field +{ + union { + struct { + __IO uint8_t Y :4; + __IO uint8_t TY :4; + }; + struct { + __IO uint8_t Y0 :1; + __IO uint8_t Y1 :1; + __IO uint8_t Y2 :1; + __IO uint8_t Y3 :1; + __IO uint8_t TY0 :1; + __IO uint8_t TY1 :1; + __IO uint8_t TY2 :1; + __IO uint8_t TY3 :1; + }; + }; +} stc_rtc_wtyr_field_t; + +typedef struct stc_rtc_almir_field +{ + union { + struct { + __IO uint8_t AMI :4; + __IO uint8_t TAMI :3; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t AMI0 :1; + __IO uint8_t AMI1 :1; + __IO uint8_t AMI2 :1; + __IO uint8_t AMI3 :1; + __IO uint8_t TAMI0 :1; + __IO uint8_t TAMI1 :1; + __IO uint8_t TAMI2 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_rtc_almir_field_t; + +typedef struct stc_rtc_alhr_field +{ + union { + struct { + __IO uint8_t AH :4; + __IO uint8_t TAH :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t AH0 :1; + __IO uint8_t AH1 :1; + __IO uint8_t AH2 :1; + __IO uint8_t AH3 :1; + __IO uint8_t TAH0 :1; + __IO uint8_t TAH1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_alhr_field_t; + +typedef struct stc_rtc_aldr_field +{ + union { + struct { + __IO uint8_t AD :4; + __IO uint8_t TAD :2; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t AD0 :1; + __IO uint8_t AD1 :1; + __IO uint8_t AD2 :1; + __IO uint8_t AD3 :1; + __IO uint8_t TAD0 :1; + __IO uint8_t TAD1 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_aldr_field_t; + +typedef struct stc_rtc_almor_field +{ + union { + struct { + __IO uint8_t AMO :4; + __IO uint8_t TAMO :1; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t AMO0 :1; + __IO uint8_t AMO1 :1; + __IO uint8_t AMO2 :1; + __IO uint8_t AMO3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_rtc_almor_field_t; + +typedef struct stc_rtc_alyr_field +{ + union { + struct { + __IO uint8_t AY :4; + __IO uint8_t TAY :4; + }; + struct { + __IO uint8_t AY0 :1; + __IO uint8_t AY1 :1; + __IO uint8_t AY2 :1; + __IO uint8_t AY3 :1; + __IO uint8_t TAY0 :1; + __IO uint8_t TAY1 :1; + __IO uint8_t TAY2 :1; + __IO uint8_t TAY3 :1; + }; + }; +} stc_rtc_alyr_field_t; + +typedef struct stc_rtc_wttr0_field +{ + union { + struct { + __IO uint8_t TM :8; + }; + struct { + __IO uint8_t TM0 :1; + __IO uint8_t TM1 :1; + __IO uint8_t TM2 :1; + __IO uint8_t TM3 :1; + __IO uint8_t TM4 :1; + __IO uint8_t TM5 :1; + __IO uint8_t TM6 :1; + __IO uint8_t TM7 :1; + }; + }; +} stc_rtc_wttr0_field_t; + +typedef struct stc_rtc_wttr1_field +{ + union { + struct { + __IO uint8_t TM :8; + }; + struct { + __IO uint8_t TM0 :1; + __IO uint8_t TM1 :1; + __IO uint8_t TM2 :1; + __IO uint8_t TM3 :1; + __IO uint8_t TM4 :1; + __IO uint8_t TM5 :1; + __IO uint8_t TM6 :1; + __IO uint8_t TM7 :1; + }; + }; +} stc_rtc_wttr1_field_t; + +typedef struct stc_rtc_wttr2_field +{ + union { + struct { + __IO uint8_t TM :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t TM0 :1; + __IO uint8_t TM1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_rtc_wttr2_field_t; + +typedef struct stc_rtc_wtcal0_field +{ + union { + struct { + __IO uint8_t WTCAL0 :8; + }; + struct { + __IO uint8_t WTCAL00 :1; + __IO uint8_t WTCAL01 :1; + __IO uint8_t WTCAL02 :1; + __IO uint8_t WTCAL03 :1; + __IO uint8_t WTCAL04 :1; + __IO uint8_t WTCAL05 :1; + __IO uint8_t WTCAL06 :1; + __IO uint8_t WTCAL07 :1; + }; + }; +} stc_rtc_wtcal0_field_t; + +typedef struct stc_rtc_wtcal1_field +{ + union { + struct { + __IO uint8_t WTCAL1 :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t WTCAL10 :1; + __IO uint8_t WTCAL11 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_rtc_wtcal1_field_t; + +typedef struct stc_rtc_wtcalen_field +{ + __IO uint8_t WTCALEN :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_wtcalen_field_t; + +typedef struct stc_rtc_wtdiv_field +{ + union { + struct { + __IO uint8_t WTDIV :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t WTDIV0 :1; + __IO uint8_t WTDIV1 :1; + __IO uint8_t WTDIV2 :1; + __IO uint8_t WTDIV3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_rtc_wtdiv_field_t; + +typedef struct stc_rtc_wtdiven_field +{ + __IO uint8_t WTDIVEN :1; + __IO uint8_t WTDIVRDY :1; + __IO uint8_t RESERVED0 :6; +} stc_rtc_wtdiven_field_t; + +typedef struct stc_rtc_wtcalprd_field +{ + union { + struct { + __IO uint8_t WTCALPRD :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t WTCALPRD0 :1; + __IO uint8_t WTCALPRD1 :1; + __IO uint8_t WTCALPRD2 :1; + __IO uint8_t WTCALPRD3 :1; + __IO uint8_t WTCALPRD4 :1; + __IO uint8_t WTCALPRD5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_rtc_wtcalprd_field_t; + +typedef struct stc_rtc_wtcosel_field +{ + __IO uint8_t WTCOSEL :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_wtcosel_field_t; + +typedef struct stc_rtc_vb_clkdiv_field +{ + union { + struct { + __IO uint8_t DIV :8; + }; + struct { + __IO uint8_t DIV0 :1; + __IO uint8_t DIV1 :1; + __IO uint8_t DIV2 :1; + __IO uint8_t DIV3 :1; + __IO uint8_t DIV4 :1; + __IO uint8_t DIV5 :1; + __IO uint8_t DIV6 :1; + __IO uint8_t DIV7 :1; + }; + }; +} stc_rtc_vb_clkdiv_field_t; + +typedef struct stc_rtc_wtosccnt_field +{ + __IO uint8_t SOSCEX :1; + __IO uint8_t SOSCNTL :1; + __IO uint8_t RESERVED0 :6; +} stc_rtc_wtosccnt_field_t; + +typedef struct stc_rtc_ccs_field +{ + union { + struct { + __IO uint8_t CCS :8; + }; + struct { + __IO uint8_t CCS0 :1; + __IO uint8_t CCS1 :1; + __IO uint8_t CCS2 :1; + __IO uint8_t CCS3 :1; + __IO uint8_t CCS4 :1; + __IO uint8_t CCS5 :1; + __IO uint8_t CCS6 :1; + __IO uint8_t CCS7 :1; + }; + }; +} stc_rtc_ccs_field_t; + +typedef struct stc_rtc_ccb_field +{ + union { + struct { + __IO uint8_t CCB :8; + }; + struct { + __IO uint8_t CCB0 :1; + __IO uint8_t CCB1 :1; + __IO uint8_t CCB2 :1; + __IO uint8_t CCB3 :1; + __IO uint8_t CCB4 :1; + __IO uint8_t CCB5 :1; + __IO uint8_t CCB6 :1; + __IO uint8_t CCB7 :1; + }; + }; +} stc_rtc_ccb_field_t; + +typedef struct stc_rtc_boost_field +{ + union { + struct { + __IO uint8_t BOOST :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t BOOST0 :1; + __IO uint8_t BOOST1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_rtc_boost_field_t; + +typedef struct stc_rtc_ewkup_field +{ + __IO uint8_t WUP0 :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_ewkup_field_t; + +typedef struct stc_rtc_vdet_field +{ + __IO uint8_t RESERVED0 :7; + __IO uint8_t PON :1; +} stc_rtc_vdet_field_t; + +typedef struct stc_rtc_hibrst_field +{ + __IO uint8_t HIBRST :1; + __IO uint8_t RESERVED0 :7; +} stc_rtc_hibrst_field_t; + +typedef struct stc_rtc_vbpfr_field +{ + union { + struct { + __IO uint8_t VPFR0 :1; + __IO uint8_t VPFR1 :1; + __IO uint8_t VPFR2 :1; + __IO uint8_t VPFR3 :1; + __IO uint8_t SPSR :2; + __IO uint8_t RESERVED1 :2; + }; + struct { + __IO uint8_t RESERVED0 :4; + __IO uint8_t SPSR0 :1; + __IO uint8_t SPSR1 :1; + __IO uint8_t RESERVED2 :2; + }; + }; +} stc_rtc_vbpfr_field_t; + +typedef struct stc_rtc_vbpcr_field +{ + __IO uint8_t VPCR0 :1; + __IO uint8_t VPCR1 :1; + __IO uint8_t VPCR2 :1; + __IO uint8_t VPCR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbpcr_field_t; + +typedef struct stc_rtc_vbddr_field +{ + __IO uint8_t VDDR0 :1; + __IO uint8_t VDDR1 :1; + __IO uint8_t VDDR2 :1; + __IO uint8_t VDDR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbddr_field_t; + +typedef struct stc_rtc_vbdir_field +{ + __IO uint8_t VDIR0 :1; + __IO uint8_t VDIR1 :1; + __IO uint8_t VDIR2 :1; + __IO uint8_t VDIR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbdir_field_t; + +typedef struct stc_rtc_vbdor_field +{ + __IO uint8_t VDOR0 :1; + __IO uint8_t VDOR1 :1; + __IO uint8_t VDOR2 :1; + __IO uint8_t VDOR3 :1; + __IO uint8_t RESERVED0 :4; +} stc_rtc_vbdor_field_t; + +typedef struct stc_rtc_vbpzr_field +{ + __IO uint8_t VPZR0 :1; + __IO uint8_t VPZR1 :1; + __IO uint8_t RESERVED0 :6; +} stc_rtc_vbpzr_field_t; + +/******************************************************************************* +* SBSSR_MODULE +*******************************************************************************/ +typedef struct stc_sbssr_btsssr_field +{ + __IO uint16_t SSSR0 :1; + __IO uint16_t SSSR1 :1; + __IO uint16_t SSSR2 :1; + __IO uint16_t SSSR3 :1; + __IO uint16_t SSSR4 :1; + __IO uint16_t SSSR5 :1; + __IO uint16_t SSSR6 :1; + __IO uint16_t SSSR7 :1; + __IO uint16_t SSSR8 :1; + __IO uint16_t SSSR9 :1; + __IO uint16_t SSSR10 :1; + __IO uint16_t SSSR11 :1; + __IO uint16_t SSSR12 :1; + __IO uint16_t SSSR13 :1; + __IO uint16_t SSSR14 :1; + __IO uint16_t SSSR15 :1; +} stc_sbssr_btsssr_field_t; + +/******************************************************************************* +* SDIF_MODULE +*******************************************************************************/ +typedef struct stc_sdif_sbsize_field +{ + union { + struct { + __IO uint16_t TRSFBLCKSZ :12; + __IO uint16_t HSDMABUFBD :3; + __IO uint16_t RESERVED0 :1; + }; + struct { + __IO uint16_t TRSFBLCKSZ0 :1; + __IO uint16_t TRSFBLCKSZ1 :1; + __IO uint16_t TRSFBLCKSZ2 :1; + __IO uint16_t TRSFBLCKSZ3 :1; + __IO uint16_t TRSFBLCKSZ4 :1; + __IO uint16_t TRSFBLCKSZ5 :1; + __IO uint16_t TRSFBLCKSZ6 :1; + __IO uint16_t TRSFBLCKSZ7 :1; + __IO uint16_t TRSFBLCKSZ8 :1; + __IO uint16_t TRSFBLCKSZ9 :1; + __IO uint16_t TRSFBLCKSZ10 :1; + __IO uint16_t TRSFBLCKSZ11 :1; + __IO uint16_t HSDMABUFBD0 :1; + __IO uint16_t HSDMABUFBD1 :1; + __IO uint16_t HSDMABUFBD2 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_sdif_sbsize_field_t; + +typedef struct stc_sdif_strsfmd_field +{ + union { + struct { + __IO uint16_t DMAEN :1; + __IO uint16_t BLCKCNTEN :1; + __IO uint16_t AUTOCMDEN :2; + __IO uint16_t DTTRSFDIR :1; + __IO uint16_t BLCKCNTSEL :1; + __IO uint16_t RESERVED1 :10; + }; + struct { + __IO uint16_t RESERVED0 :2; + __IO uint16_t AUTOCMDEN0 :1; + __IO uint16_t AUTOCMDEN1 :1; + __IO uint16_t RESERVED2 :12; + }; + }; +} stc_sdif_strsfmd_field_t; + +typedef struct stc_sdif_scmmd_field +{ + union { + struct { + __IO uint16_t RESPTYPE :2; + __IO uint16_t RESERVED0 :1; + __IO uint16_t CMDCRCCHKE :1; + __IO uint16_t CMDIDXCHKE :1; + __IO uint16_t DATPRESSEL :1; + __IO uint16_t CMDTYPE :2; + __IO uint16_t CMDINDEX :6; + __IO uint16_t RESERVED2 :2; + }; + struct { + __IO uint16_t RESPTYPE0 :1; + __IO uint16_t RESPTYPE1 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t CMDTYPE0 :1; + __IO uint16_t CMDTYPE1 :1; + __IO uint16_t CMDINDEX0 :1; + __IO uint16_t CMDINDEX1 :1; + __IO uint16_t CMDINDEX2 :1; + __IO uint16_t CMDINDEX3 :1; + __IO uint16_t CMDINDEX4 :1; + __IO uint16_t CMDINDEX5 :1; + __IO uint16_t RESERVED3 :2; + }; + }; +} stc_sdif_scmmd_field_t; + +typedef struct stc_sdif_sprstat_field +{ + union { + struct { + __IO uint32_t CMDINH :1; + __IO uint32_t CMDDATINH :1; + __IO uint32_t DATLNACT :1; + __IO uint32_t RETUNEREQ :1; + __IO uint32_t RESERVED0 :4; + __IO uint32_t WRTRSFACT :1; + __IO uint32_t RDTRSFACT :1; + __IO uint32_t BUFWREN :1; + __IO uint32_t BUFRDEN :1; + __IO uint32_t RESERVED1 :4; + __IO uint32_t CARDINS :1; + __IO uint32_t CARDSTB :1; + __IO uint32_t CARDDET :1; + __IO uint32_t WPPINLVL :1; + __IO uint32_t LNSGNLVL :4; + __IO uint32_t CMDLNSGN :1; + __IO uint32_t RESERVED3 :7; + }; + struct { + __IO uint32_t RESERVED2 :20; + __IO uint32_t LNSGNLVL0 :1; + __IO uint32_t LNSGNLVL1 :1; + __IO uint32_t LNSGNLVL2 :1; + __IO uint32_t LNSGNLVL3 :1; + __IO uint32_t RESERVED4 :8; + }; + }; +} stc_sdif_sprstat_field_t; + +typedef struct stc_sdif_shctl1_field +{ + union { + struct { + __IO uint8_t LEDCTRL :1; + __IO uint8_t DATAWIDTH :1; + __IO uint8_t HIGHSPDEN :1; + __IO uint8_t DMASEL :2; + __IO uint8_t EXTDTWIDTH :1; + __IO uint8_t CDTSTLVL :1; + __IO uint8_t CDSGNSEL :1; + }; + struct { + __IO uint8_t RESERVED0 :3; + __IO uint8_t DMASEL0 :1; + __IO uint8_t DMASEL1 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_sdif_shctl1_field_t; + +typedef struct stc_sdif_spwrctl_field +{ + union { + struct { + __IO uint8_t SDBUSPWR :1; + __IO uint8_t SDBUSVLSEL :3; + __IO uint8_t RESERVED1 :4; + }; + struct { + __IO uint8_t RESERVED0 :1; + __IO uint8_t SDBUSVLSEL0 :1; + __IO uint8_t SDBUSVLSEL1 :1; + __IO uint8_t SDBUSVLSEL2 :1; + __IO uint8_t RESERVED2 :4; + }; + }; +} stc_sdif_spwrctl_field_t; + +typedef struct stc_sdif_sblkgpctl_field +{ + __IO uint8_t BLCKGSTPREQ :1; + __IO uint8_t CONTREQ :1; + __IO uint8_t RDWAITCTL :1; + __IO uint8_t BLCKGAPINT :1; + __IO uint8_t RESERVED0 :4; +} stc_sdif_sblkgpctl_field_t; + +typedef struct stc_sdif_swkupctl_field +{ + __IO uint8_t WKUPEVNTEN0 :1; + __IO uint8_t WKUPEVNTEN1 :1; + __IO uint8_t WKUPEVNTEN2 :1; + __IO uint8_t RESERVED0 :5; +} stc_sdif_swkupctl_field_t; + +typedef struct stc_sdif_sclkctl_field +{ + union { + struct { + __IO uint16_t INTLCLCKEN :1; + __IO uint16_t INTLCLCKST :1; + __IO uint16_t SDCLCKEN :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t CLCKGENSEL :1; + __IO uint16_t UPSDCLKSEL :2; + __IO uint16_t SDCLKSEL :8; + }; + struct { + __IO uint16_t RESERVED1 :6; + __IO uint16_t UPSDCLKSEL0 :1; + __IO uint16_t UPSDCLKSEL1 :1; + __IO uint16_t SDCLKSEL0 :1; + __IO uint16_t SDCLKSEL1 :1; + __IO uint16_t SDCLKSEL2 :1; + __IO uint16_t SDCLKSEL3 :1; + __IO uint16_t SDCLKSEL4 :1; + __IO uint16_t SDCLKSEL5 :1; + __IO uint16_t SDCLKSEL6 :1; + __IO uint16_t SDCLKSEL7 :1; + }; + }; +} stc_sdif_sclkctl_field_t; + +typedef struct stc_sdif_stoctl_field +{ + union { + struct { + __IO uint8_t DTTMOUTVAL :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t DTTMOUTVAL0 :1; + __IO uint8_t DTTMOUTVAL1 :1; + __IO uint8_t DTTMOUTVAL2 :1; + __IO uint8_t DTTMOUTVAL3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_sdif_stoctl_field_t; + +typedef struct stc_sdif_ssrst_field +{ + __IO uint8_t SWRSTALL :1; + __IO uint8_t SWRSTCMDLN :1; + __IO uint8_t SWRSTDATLN :1; + __IO uint8_t RESERVED0 :5; +} stc_sdif_ssrst_field_t; + +typedef struct stc_sdif_snintst_field +{ + __IO uint16_t CMDCMPLT :1; + __IO uint16_t TRSFCMPLT :1; + __IO uint16_t BLCKGEVNT :1; + __IO uint16_t DMAINT :1; + __IO uint16_t BUFWRRDY :1; + __IO uint16_t BUFRDRDY :1; + __IO uint16_t CARDINS :1; + __IO uint16_t CARDRMV :1; + __IO uint16_t CARDINT :1; + __IO uint16_t INT_A :1; + __IO uint16_t INT_B :1; + __IO uint16_t INT_C :1; + __IO uint16_t RETUNEEVT :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t ERRORINT :1; +} stc_sdif_snintst_field_t; + +typedef struct stc_sdif_seintst_field +{ + __IO uint16_t CMDTOERR :1; + __IO uint16_t CMDCRCERR :1; + __IO uint16_t CMDEBERR :1; + __IO uint16_t CMDIDXERR :1; + __IO uint16_t DTTOERR :1; + __IO uint16_t DTCRCERR :1; + __IO uint16_t DTEBERR :1; + __IO uint16_t CRTLMTERR :1; + __IO uint16_t ACMD12ERR :1; + __IO uint16_t ADMAERR :1; + __IO uint16_t TUNINGERR :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t BTACKERR :1; + __IO uint16_t ACMD19ERR :1; + __IO uint16_t AHBMSTERR :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_seintst_field_t; + +typedef struct stc_sdif_snintste_field +{ + __IO uint16_t CMDCMPLTS :1; + __IO uint16_t TRSFCMPLTS :1; + __IO uint16_t BLCKGEVNTS :1; + __IO uint16_t DMAINTS :1; + __IO uint16_t BUFWRRDYS :1; + __IO uint16_t BUFRDRDYS :1; + __IO uint16_t CARDINSS :1; + __IO uint16_t CARDRMVS :1; + __IO uint16_t CARDINTS :1; + __IO uint16_t INT_AS :1; + __IO uint16_t INT_BS :1; + __IO uint16_t INT_CS :1; + __IO uint16_t RETUNEEVTS :1; + __IO uint16_t RESERVED0 :3; +} stc_sdif_snintste_field_t; + +typedef struct stc_sdif_seintste_field +{ + __IO uint16_t CMDTOERRS :1; + __IO uint16_t CMDCRCERRS :1; + __IO uint16_t CMDEBERRS :1; + __IO uint16_t CMDIDXERRS :1; + __IO uint16_t DTTOERRS :1; + __IO uint16_t DTCRCERRS :1; + __IO uint16_t DTEBERRS :1; + __IO uint16_t CRTLMTERRS :1; + __IO uint16_t ACMD12ERRS :1; + __IO uint16_t ADMAERRS :1; + __IO uint16_t TUNINGERRS :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t BTACKERRS :1; + __IO uint16_t ACMD19ERRS :1; + __IO uint16_t AHBMSTERRS :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_seintste_field_t; + +typedef struct stc_sdif_snintsge_field +{ + __IO uint16_t CMDCMPLTG :1; + __IO uint16_t TRSFCMPLTG :1; + __IO uint16_t BLCKGEVNTG :1; + __IO uint16_t DMAINTG :1; + __IO uint16_t BUFWRRDYG :1; + __IO uint16_t BUFRDRDYG :1; + __IO uint16_t CARDINSG :1; + __IO uint16_t CARDRMVG :1; + __IO uint16_t CARDINTG :1; + __IO uint16_t INT_AG :1; + __IO uint16_t INT_BG :1; + __IO uint16_t INT_CG :1; + __IO uint16_t RETUNEEVTG :1; + __IO uint16_t RESERVED0 :3; +} stc_sdif_snintsge_field_t; + +typedef struct stc_sdif_seintsge_field +{ + __IO uint16_t CMDTOERRG :1; + __IO uint16_t CMDCRCERRG :1; + __IO uint16_t CMDEBERRG :1; + __IO uint16_t CMDIDXERRG :1; + __IO uint16_t DTTOERRG :1; + __IO uint16_t DTCRCERRG :1; + __IO uint16_t DTEBERRG :1; + __IO uint16_t CRTLMTERRG :1; + __IO uint16_t ACMD12ERRG :1; + __IO uint16_t ADMAERRG :1; + __IO uint16_t TUNINGERRG :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t BTACKERRG :1; + __IO uint16_t ACMD19ERRG :1; + __IO uint16_t AHBMSTERRG :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_seintsge_field_t; + +typedef struct stc_sdif_sacmdest_field +{ + __IO uint16_t ACMD12NOEX :1; + __IO uint16_t ACMDTOERR :1; + __IO uint16_t ACMDCRCERR :1; + __IO uint16_t ACMDEBERR :1; + __IO uint16_t ACMDIDXERR :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t CMDND12ERR :1; + __IO uint16_t RESERVED1 :8; +} stc_sdif_sacmdest_field_t; + +typedef struct stc_sdif_shctl2_field +{ + union { + struct { + __IO uint16_t UHSMDSEL :3; + __IO uint16_t V18SGNEN :1; + __IO uint16_t DRVSEL :2; + __IO uint16_t DOTUING :1; + __IO uint16_t SMPCLKSEL :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t ASYINTEN :1; + __IO uint16_t PREVALEN :1; + }; + struct { + __IO uint16_t UHSMDSEL0 :1; + __IO uint16_t UHSMDSEL1 :1; + __IO uint16_t UHSMDSEL2 :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t DRVSEL0 :1; + __IO uint16_t DRVSEL1 :1; + __IO uint16_t RESERVED2 :10; + }; + }; +} stc_sdif_shctl2_field_t; + +typedef struct stc_sdif_capblty0_field +{ + union { + struct { + __IO uint16_t TOCLKFREQ :6; + __IO uint16_t RESERVED0 :1; + __IO uint16_t TOCLKUNIT :1; + __IO uint16_t SDBASECLK :8; + }; + struct { + __IO uint16_t TOCLKFREQ0 :1; + __IO uint16_t TOCLKFREQ1 :1; + __IO uint16_t TOCLKFREQ2 :1; + __IO uint16_t TOCLKFREQ3 :1; + __IO uint16_t TOCLKFREQ4 :1; + __IO uint16_t TOCLKFREQ5 :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SDBASECLK0 :1; + __IO uint16_t SDBASECLK1 :1; + __IO uint16_t SDBASECLK2 :1; + __IO uint16_t SDBASECLK3 :1; + __IO uint16_t SDBASECLK4 :1; + __IO uint16_t SDBASECLK5 :1; + __IO uint16_t SDBASECLK6 :1; + __IO uint16_t SDBASECLK7 :1; + }; + }; +} stc_sdif_capblty0_field_t; + +typedef struct stc_sdif_capblty1_field +{ + union { + struct { + __IO uint16_t MAXBLCKLEN :2; + __IO uint16_t EMBD8BIT :1; + __IO uint16_t ADMA2SPT :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t HGHSPDSPT :1; + __IO uint16_t SDMASPT :1; + __IO uint16_t LWPWRSPT :1; + __IO uint16_t V33SPT :1; + __IO uint16_t V30SPT :1; + __IO uint16_t V18SPT :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t BUS64SPT :1; + __IO uint16_t ASYINTSPT :1; + __IO uint16_t STOPTYPE :2; + }; + struct { + __IO uint16_t MAXBLCKLEN0 :1; + __IO uint16_t MAXBLCKLEN1 :1; + __IO uint16_t RESERVED2 :12; + __IO uint16_t STOPTYPE0 :1; + __IO uint16_t STOPTYPE1 :1; + }; + }; +} stc_sdif_capblty1_field_t; + +typedef struct stc_sdif_capblty2_field +{ + union { + struct { + __IO uint16_t SDR50SPT :1; + __IO uint16_t SDR104SPT :1; + __IO uint16_t DDR50SPT :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t DRVTPASPT :1; + __IO uint16_t DRVTPCSPT :1; + __IO uint16_t DRVTPDSPT :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t TMCNTRETN :4; + __IO uint16_t RESERVED3 :1; + __IO uint16_t USETNSDR50 :1; + __IO uint16_t RETNMODE :2; + }; + struct { + __IO uint16_t RESERVED2 :8; + __IO uint16_t TMCNTRETN0 :1; + __IO uint16_t TMCNTRETN1 :1; + __IO uint16_t TMCNTRETN2 :1; + __IO uint16_t TMCNTRETN3 :1; + __IO uint16_t RESERVED4 :2; + __IO uint16_t RETNMODE0 :1; + __IO uint16_t RETNMODE1 :1; + }; + }; +} stc_sdif_capblty2_field_t; + +typedef struct stc_sdif_capblty3_field +{ + union { + struct { + __IO uint16_t CLKMULTPL :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t CLKMULTPL0 :1; + __IO uint16_t CLKMULTPL1 :1; + __IO uint16_t CLKMULTPL2 :1; + __IO uint16_t CLKMULTPL3 :1; + __IO uint16_t CLKMULTPL4 :1; + __IO uint16_t CLKMULTPL5 :1; + __IO uint16_t CLKMULTPL6 :1; + __IO uint16_t CLKMULTPL7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_capblty3_field_t; + +typedef struct stc_sdif_mxccapy0_field +{ + union { + struct { + __IO uint16_t V33MAXCUR :8; + __IO uint16_t V30MAXCUR :8; + }; + struct { + __IO uint16_t V33MAXCUR0 :1; + __IO uint16_t V33MAXCUR1 :1; + __IO uint16_t V33MAXCUR2 :1; + __IO uint16_t V33MAXCUR3 :1; + __IO uint16_t V33MAXCUR4 :1; + __IO uint16_t V33MAXCUR5 :1; + __IO uint16_t V33MAXCUR6 :1; + __IO uint16_t V33MAXCUR7 :1; + __IO uint16_t V30MAXCUR0 :1; + __IO uint16_t V30MAXCUR1 :1; + __IO uint16_t V30MAXCUR2 :1; + __IO uint16_t V30MAXCUR3 :1; + __IO uint16_t V30MAXCUR4 :1; + __IO uint16_t V30MAXCUR5 :1; + __IO uint16_t V30MAXCUR6 :1; + __IO uint16_t V30MAXCUR7 :1; + }; + }; +} stc_sdif_mxccapy0_field_t; + +typedef struct stc_sdif_mxccapy1_field +{ + union { + struct { + __IO uint16_t V18MAXCUR :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t V18MAXCUR0 :1; + __IO uint16_t V18MAXCUR1 :1; + __IO uint16_t V18MAXCUR2 :1; + __IO uint16_t V18MAXCUR3 :1; + __IO uint16_t V18MAXCUR4 :1; + __IO uint16_t V18MAXCUR5 :1; + __IO uint16_t V18MAXCUR6 :1; + __IO uint16_t V18MAXCUR7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_mxccapy1_field_t; + +typedef struct stc_sdif_feacest_field +{ + __IO uint16_t FEVNT12ND :1; + __IO uint16_t FEVNTTO :1; + __IO uint16_t FEVNTCRC :1; + __IO uint16_t FEVNTEB :1; + __IO uint16_t FEVNTIDX :1; + __IO uint16_t RESERVED0 :2; + __IO uint16_t FEVNTCMD12 :1; + __IO uint16_t RESERVED1 :8; +} stc_sdif_feacest_field_t; + +typedef struct stc_sdif_sfeeist_field +{ + __IO uint16_t FETOERR :1; + __IO uint16_t FECRCERR :1; + __IO uint16_t FEEBERR :1; + __IO uint16_t FEIDXERR :1; + __IO uint16_t FEDTOTERR :1; + __IO uint16_t FEDTCRCERR :1; + __IO uint16_t FEDTEBERR :1; + __IO uint16_t FECRLTERR :1; + __IO uint16_t FEA12ERR :1; + __IO uint16_t FEADMAERR :1; + __IO uint16_t FETUNEERR :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t FEACKERR :1; + __IO uint16_t FEA19ERR :1; + __IO uint16_t FEAHBMSERR :1; + __IO uint16_t RESERVED1 :1; +} stc_sdif_sfeeist_field_t; + +typedef struct stc_sdif_admaest_field +{ + union { + struct { + __IO uint8_t ADMAERRS :2; + __IO uint8_t ADMALENME :1; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t ADMAERRS0 :1; + __IO uint8_t ADMAERRS1 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_sdif_admaest_field_t; + +typedef struct stc_sdif_sadsa0_field +{ + union { + struct { + __IO uint16_t ADR1500 :16; + }; + struct { + __IO uint16_t ADR15000 :1; + __IO uint16_t ADR15001 :1; + __IO uint16_t ADR15002 :1; + __IO uint16_t ADR15003 :1; + __IO uint16_t ADR15004 :1; + __IO uint16_t ADR15005 :1; + __IO uint16_t ADR15006 :1; + __IO uint16_t ADR15007 :1; + __IO uint16_t ADR15008 :1; + __IO uint16_t ADR15009 :1; + __IO uint16_t ADR150010 :1; + __IO uint16_t ADR150011 :1; + __IO uint16_t ADR150012 :1; + __IO uint16_t ADR150013 :1; + __IO uint16_t ADR150014 :1; + __IO uint16_t ADR150015 :1; + }; + }; +} stc_sdif_sadsa0_field_t; + +typedef struct stc_sdif_sadsa1_field +{ + union { + struct { + __IO uint16_t ADR3116 :16; + }; + struct { + __IO uint16_t ADR31160 :1; + __IO uint16_t ADR31161 :1; + __IO uint16_t ADR31162 :1; + __IO uint16_t ADR31163 :1; + __IO uint16_t ADR31164 :1; + __IO uint16_t ADR31165 :1; + __IO uint16_t ADR31166 :1; + __IO uint16_t ADR31167 :1; + __IO uint16_t ADR31168 :1; + __IO uint16_t ADR31169 :1; + __IO uint16_t ADR311610 :1; + __IO uint16_t ADR311611 :1; + __IO uint16_t ADR311612 :1; + __IO uint16_t ADR311613 :1; + __IO uint16_t ADR311614 :1; + __IO uint16_t ADR311615 :1; + }; + }; +} stc_sdif_sadsa1_field_t; + +typedef struct stc_sdif_sadsa2_field +{ + union { + struct { + __IO uint16_t ADR4732 :16; + }; + struct { + __IO uint16_t ADR47320 :1; + __IO uint16_t ADR47321 :1; + __IO uint16_t ADR47322 :1; + __IO uint16_t ADR47323 :1; + __IO uint16_t ADR47324 :1; + __IO uint16_t ADR47325 :1; + __IO uint16_t ADR47326 :1; + __IO uint16_t ADR47327 :1; + __IO uint16_t ADR47328 :1; + __IO uint16_t ADR47329 :1; + __IO uint16_t ADR473210 :1; + __IO uint16_t ADR473211 :1; + __IO uint16_t ADR473212 :1; + __IO uint16_t ADR473213 :1; + __IO uint16_t ADR473214 :1; + __IO uint16_t ADR473215 :1; + }; + }; +} stc_sdif_sadsa2_field_t; + +typedef struct stc_sdif_sadsa3_field +{ + union { + struct { + __IO uint16_t ADR6348 :16; + }; + struct { + __IO uint16_t ADR63480 :1; + __IO uint16_t ADR63481 :1; + __IO uint16_t ADR63482 :1; + __IO uint16_t ADR63483 :1; + __IO uint16_t ADR63484 :1; + __IO uint16_t ADR63485 :1; + __IO uint16_t ADR63486 :1; + __IO uint16_t ADR63487 :1; + __IO uint16_t ADR63488 :1; + __IO uint16_t ADR63489 :1; + __IO uint16_t ADR634810 :1; + __IO uint16_t ADR634811 :1; + __IO uint16_t ADR634812 :1; + __IO uint16_t ADR634813 :1; + __IO uint16_t ADR634814 :1; + __IO uint16_t ADR634815 :1; + }; + }; +} stc_sdif_sadsa3_field_t; + +typedef struct stc_sdif_sprval0_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval0_field_t; + +typedef struct stc_sdif_sprval1_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval1_field_t; + +typedef struct stc_sdif_sprval2_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval2_field_t; + +typedef struct stc_sdif_sprval3_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval3_field_t; + +typedef struct stc_sdif_sprval4_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval4_field_t; + +typedef struct stc_sdif_sprval5_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval5_field_t; + +typedef struct stc_sdif_sprval6_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval6_field_t; + +typedef struct stc_sdif_sprval7_field +{ + union { + struct { + __IO uint16_t SCFSELVAL :10; + __IO uint16_t CGSELVAL :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t DSSELVAL :2; + }; + struct { + __IO uint16_t SCFSELVAL0 :1; + __IO uint16_t SCFSELVAL1 :1; + __IO uint16_t SCFSELVAL2 :1; + __IO uint16_t SCFSELVAL3 :1; + __IO uint16_t SCFSELVAL4 :1; + __IO uint16_t SCFSELVAL5 :1; + __IO uint16_t SCFSELVAL6 :1; + __IO uint16_t SCFSELVAL7 :1; + __IO uint16_t SCFSELVAL8 :1; + __IO uint16_t SCFSELVAL9 :1; + __IO uint16_t RESERVED1 :4; + __IO uint16_t DSSELVAL0 :1; + __IO uint16_t DSSELVAL1 :1; + }; + }; +} stc_sdif_sprval7_field_t; + +typedef struct stc_sdif_sshbctll_field +{ + union { + struct { + __IO uint16_t CLCKPIN :3; + __IO uint16_t RESERVED0 :1; + __IO uint16_t INTINPIN :2; + __IO uint16_t RESERVED2 :2; + __IO uint16_t BUSWDPRST :7; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t CLCKPIN0 :1; + __IO uint16_t CLCKPIN1 :1; + __IO uint16_t CLCKPIN2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t INTINPIN0 :1; + __IO uint16_t INTINPIN1 :1; + __IO uint16_t RESERVED3 :2; + __IO uint16_t BUSWDPRST0 :1; + __IO uint16_t BUSWDPRST1 :1; + __IO uint16_t BUSWDPRST2 :1; + __IO uint16_t BUSWDPRST3 :1; + __IO uint16_t BUSWDPRST4 :1; + __IO uint16_t BUSWDPRST5 :1; + __IO uint16_t BUSWDPRST6 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_sdif_sshbctll_field_t; + +typedef struct stc_sdif_sshbctlh_field +{ + union { + struct { + __IO uint16_t CLCKPINSEL :3; + __IO uint16_t RESERVED0 :1; + __IO uint16_t INTPINSEL :3; + __IO uint16_t RESERVED2 :1; + __IO uint16_t BEPWRCTL :7; + __IO uint16_t RESERVED4 :1; + }; + struct { + __IO uint16_t CLCKPINSEL0 :1; + __IO uint16_t CLCKPINSEL1 :1; + __IO uint16_t CLCKPINSEL2 :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t INTPINSEL0 :1; + __IO uint16_t INTPINSEL1 :1; + __IO uint16_t INTPINSEL2 :1; + __IO uint16_t RESERVED3 :1; + __IO uint16_t BEPWRCTL0 :1; + __IO uint16_t BEPWRCTL1 :1; + __IO uint16_t BEPWRCTL2 :1; + __IO uint16_t BEPWRCTL3 :1; + __IO uint16_t BEPWRCTL4 :1; + __IO uint16_t BEPWRCTL5 :1; + __IO uint16_t BEPWRCTL6 :1; + __IO uint16_t RESERVED5 :1; + }; + }; +} stc_sdif_sshbctlh_field_t; + +typedef struct stc_sdif_sslist_field +{ + union { + struct { + __IO uint16_t SLOTINTSGN :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t SLOTINTSGN0 :1; + __IO uint16_t SLOTINTSGN1 :1; + __IO uint16_t SLOTINTSGN2 :1; + __IO uint16_t SLOTINTSGN3 :1; + __IO uint16_t SLOTINTSGN4 :1; + __IO uint16_t SLOTINTSGN5 :1; + __IO uint16_t SLOTINTSGN6 :1; + __IO uint16_t SLOTINTSGN7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_sslist_field_t; + +typedef struct stc_sdif_shctlv_field +{ + union { + struct { + __IO uint16_t SPECVERNUM :8; + __IO uint16_t VNDVERNUM :8; + }; + struct { + __IO uint16_t SPECVERNUM0 :1; + __IO uint16_t SPECVERNUM1 :1; + __IO uint16_t SPECVERNUM2 :1; + __IO uint16_t SPECVERNUM3 :1; + __IO uint16_t SPECVERNUM4 :1; + __IO uint16_t SPECVERNUM5 :1; + __IO uint16_t SPECVERNUM6 :1; + __IO uint16_t SPECVERNUM7 :1; + __IO uint16_t VNDVERNUM0 :1; + __IO uint16_t VNDVERNUM1 :1; + __IO uint16_t VNDVERNUM2 :1; + __IO uint16_t VNDVERNUM3 :1; + __IO uint16_t VNDVERNUM4 :1; + __IO uint16_t VNDVERNUM5 :1; + __IO uint16_t VNDVERNUM6 :1; + __IO uint16_t VNDVERNUM7 :1; + }; + }; +} stc_sdif_shctlv_field_t; + +typedef struct stc_sdif_ahbcfgl_field +{ + union { + struct { + __IO uint16_t INCRSEL :3; + __IO uint16_t SINEN :1; + __IO uint16_t BSLOCK :1; + __IO uint16_t BSLOCKSEL :1; + __IO uint16_t ENDIANSEL :1; + __IO uint16_t RESERVED0 :9; + }; + struct { + __IO uint16_t INCRSEL0 :1; + __IO uint16_t INCRSEL1 :1; + __IO uint16_t INCRSEL2 :1; + __IO uint16_t RESERVED1 :13; + }; + }; +} stc_sdif_ahbcfgl_field_t; + +typedef struct stc_sdif_spwswcl_field +{ + __IO uint16_t ATPWRSWEN :1; + __IO uint16_t IOREGSEL :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_spwswcl_field_t; + +typedef struct stc_sdif_stunsetl_field +{ + union { + struct { + __IO uint16_t TNPTSEL :8; + __IO uint16_t TNPHSELEN :1; + __IO uint16_t TNERRBDSEL :1; + __IO uint16_t RETNTAPSEL :1; + __IO uint16_t RETNRNGSEL :2; + __IO uint16_t RESERVED1 :3; + }; + struct { + __IO uint16_t TNPTSEL0 :1; + __IO uint16_t TNPTSEL1 :1; + __IO uint16_t TNPTSEL2 :1; + __IO uint16_t TNPTSEL3 :1; + __IO uint16_t TNPTSEL4 :1; + __IO uint16_t TNPTSEL5 :1; + __IO uint16_t TNPTSEL6 :1; + __IO uint16_t TNPTSEL7 :1; + __IO uint16_t RESERVED0 :3; + __IO uint16_t RETNRNGSEL0 :1; + __IO uint16_t RETNRNGSEL1 :1; + __IO uint16_t RESERVED2 :3; + }; + }; +} stc_sdif_stunsetl_field_t; + +typedef struct stc_sdif_stunseth_field +{ + union { + struct { + __IO uint16_t CMDCFCHKDS :1; + __IO uint16_t RESERVED0 :7; + __IO uint16_t DTOTCNTVAL :4; + __IO uint16_t RESERVED2 :4; + }; + struct { + __IO uint16_t RESERVED1 :8; + __IO uint16_t DTOTCNTVAL0 :1; + __IO uint16_t DTOTCNTVAL1 :1; + __IO uint16_t DTOTCNTVAL2 :1; + __IO uint16_t DTOTCNTVAL3 :1; + __IO uint16_t RESERVED3 :4; + }; + }; +} stc_sdif_stunseth_field_t; + +typedef struct stc_sdif_stunstl_field +{ + union { + struct { + __IO uint16_t REP8TNRSLT :8; + __IO uint16_t REP3TNRSLT :3; + __IO uint16_t RESERVED0 :5; + }; + struct { + __IO uint16_t REP8TNRSLT0 :1; + __IO uint16_t REP8TNRSLT1 :1; + __IO uint16_t REP8TNRSLT2 :1; + __IO uint16_t REP8TNRSLT3 :1; + __IO uint16_t REP8TNRSLT4 :1; + __IO uint16_t REP8TNRSLT5 :1; + __IO uint16_t REP8TNRSLT6 :1; + __IO uint16_t REP8TNRSLT7 :1; + __IO uint16_t REP3TNRSLT0 :1; + __IO uint16_t REP3TNRSLT1 :1; + __IO uint16_t REP3TNRSLT2 :1; + __IO uint16_t RESERVED1 :5; + }; + }; +} stc_sdif_stunstl_field_t; + +typedef struct stc_sdif_stunsth_field +{ + union { + struct { + __IO uint16_t PRSTTNPNT :8; + __IO uint16_t RESERVED0 :8; + }; + struct { + __IO uint16_t PRSTTNPNT0 :1; + __IO uint16_t PRSTTNPNT1 :1; + __IO uint16_t PRSTTNPNT2 :1; + __IO uint16_t PRSTTNPNT3 :1; + __IO uint16_t PRSTTNPNT4 :1; + __IO uint16_t PRSTTNPNT5 :1; + __IO uint16_t PRSTTNPNT6 :1; + __IO uint16_t PRSTTNPNT7 :1; + __IO uint16_t RESERVED1 :8; + }; + }; +} stc_sdif_stunsth_field_t; + +typedef struct stc_sdif_pswistl_field +{ + __IO uint16_t INT5MS :1; + __IO uint16_t INT1MS :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_pswistl_field_t; + +typedef struct stc_sdif_pswistel_field +{ + __IO uint16_t INT5MSSTS :1; + __IO uint16_t INT1MSSTS :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_pswistel_field_t; + +typedef struct stc_sdif_pswisgel_field +{ + __IO uint16_t INT5MSSGEN :1; + __IO uint16_t INT1MSSGEN :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_pswisgel_field_t; + +typedef struct stc_sdif_mmcsdcl_field +{ + __IO uint16_t LCKRSTESD :1; + __IO uint16_t RSTMMC :1; + __IO uint16_t VCCCTLMMC :1; + __IO uint16_t VCCQCTLMMC :1; + __IO uint16_t RESERVED0 :4; + __IO uint16_t MMCDDRSEL :1; + __IO uint16_t CMDDATDLY :1; + __IO uint16_t RESERVED1 :6; +} stc_sdif_mmcsdcl_field_t; + +typedef struct stc_sdif_mmcsdch_field +{ + __IO uint16_t BTACKENMMC :1; + __IO uint16_t BTABTENMMC :1; + __IO uint16_t BTMDENMMC :1; + __IO uint16_t RESERVED0 :13; +} stc_sdif_mmcsdch_field_t; + +typedef struct stc_sdif_mcwirqc0_field +{ + __IO uint16_t WTIRQEN :1; + __IO uint16_t WTIRQST :1; + __IO uint16_t RESERVED0 :14; +} stc_sdif_mcwirqc0_field_t; + +typedef struct stc_sdif_mcwirqc1_field +{ + union { + struct { + __IO uint16_t WTIRQCNCLR :16; + }; + struct { + __IO uint16_t WTIRQCNCLR0 :1; + __IO uint16_t WTIRQCNCLR1 :1; + __IO uint16_t WTIRQCNCLR2 :1; + __IO uint16_t WTIRQCNCLR3 :1; + __IO uint16_t WTIRQCNCLR4 :1; + __IO uint16_t WTIRQCNCLR5 :1; + __IO uint16_t WTIRQCNCLR6 :1; + __IO uint16_t WTIRQCNCLR7 :1; + __IO uint16_t WTIRQCNCLR8 :1; + __IO uint16_t WTIRQCNCLR9 :1; + __IO uint16_t WTIRQCNCLR10 :1; + __IO uint16_t WTIRQCNCLR11 :1; + __IO uint16_t WTIRQCNCLR12 :1; + __IO uint16_t WTIRQCNCLR13 :1; + __IO uint16_t WTIRQCNCLR14 :1; + __IO uint16_t WTIRQCNCLR15 :1; + }; + }; +} stc_sdif_mcwirqc1_field_t; + +typedef struct stc_sdif_mcwirqc2_field +{ + union { + struct { + __IO uint16_t WTIRQCNCLR :16; + }; + struct { + __IO uint16_t WTIRQCNCLR0 :1; + __IO uint16_t WTIRQCNCLR1 :1; + __IO uint16_t WTIRQCNCLR2 :1; + __IO uint16_t WTIRQCNCLR3 :1; + __IO uint16_t WTIRQCNCLR4 :1; + __IO uint16_t WTIRQCNCLR5 :1; + __IO uint16_t WTIRQCNCLR6 :1; + __IO uint16_t WTIRQCNCLR7 :1; + __IO uint16_t WTIRQCNCLR8 :1; + __IO uint16_t WTIRQCNCLR9 :1; + __IO uint16_t WTIRQCNCLR10 :1; + __IO uint16_t WTIRQCNCLR11 :1; + __IO uint16_t WTIRQCNCLR12 :1; + __IO uint16_t WTIRQCNCLR13 :1; + __IO uint16_t WTIRQCNCLR14 :1; + __IO uint16_t WTIRQCNCLR15 :1; + }; + }; +} stc_sdif_mcwirqc2_field_t; + +typedef struct stc_sdif_mcwirqc3_field +{ + union { + struct { + __IO uint16_t WTIRQCNCLR :16; + }; + struct { + __IO uint16_t WTIRQCNCLR0 :1; + __IO uint16_t WTIRQCNCLR1 :1; + __IO uint16_t WTIRQCNCLR2 :1; + __IO uint16_t WTIRQCNCLR3 :1; + __IO uint16_t WTIRQCNCLR4 :1; + __IO uint16_t WTIRQCNCLR5 :1; + __IO uint16_t WTIRQCNCLR6 :1; + __IO uint16_t WTIRQCNCLR7 :1; + __IO uint16_t WTIRQCNCLR8 :1; + __IO uint16_t WTIRQCNCLR9 :1; + __IO uint16_t WTIRQCNCLR10 :1; + __IO uint16_t WTIRQCNCLR11 :1; + __IO uint16_t WTIRQCNCLR12 :1; + __IO uint16_t WTIRQCNCLR13 :1; + __IO uint16_t WTIRQCNCLR14 :1; + __IO uint16_t WTIRQCNCLR15 :1; + }; + }; +} stc_sdif_mcwirqc3_field_t; + +typedef struct stc_sdif_mcrpckbl_field +{ + union { + struct { + __IO uint16_t CHECKBIT1 :7; + __IO uint16_t CHECKBIT2 :6; + __IO uint16_t RESERVED0 :3; + }; + struct { + __IO uint16_t CHECKBIT10 :1; + __IO uint16_t CHECKBIT11 :1; + __IO uint16_t CHECKBIT12 :1; + __IO uint16_t CHECKBIT13 :1; + __IO uint16_t CHECKBIT14 :1; + __IO uint16_t CHECKBIT15 :1; + __IO uint16_t CHECKBIT16 :1; + __IO uint16_t CHECKBIT20 :1; + __IO uint16_t CHECKBIT21 :1; + __IO uint16_t CHECKBIT22 :1; + __IO uint16_t CHECKBIT23 :1; + __IO uint16_t CHECKBIT24 :1; + __IO uint16_t CHECKBIT25 :1; + __IO uint16_t RESERVED1 :3; + }; + }; +} stc_sdif_mcrpckbl_field_t; + +typedef struct stc_sdif_scdetecs_field +{ + union { + struct { + __IO uint16_t RESERVED0 :8; + __IO uint16_t CDDEBTCVAL :4; + __IO uint16_t RESERVED2 :4; + }; + struct { + __IO uint16_t RESERVED1 :8; + __IO uint16_t CDDEBTCVAL0 :1; + __IO uint16_t CDDEBTCVAL1 :1; + __IO uint16_t CDDEBTCVAL2 :1; + __IO uint16_t CDDEBTCVAL3 :1; + __IO uint16_t RESERVED3 :4; + }; + }; +} stc_sdif_scdetecs_field_t; + +/******************************************************************************* +* SWWDT_MODULE +*******************************************************************************/ +typedef struct stc_swwdt_wdogcontrol_field +{ + union { + struct { + __IO uint32_t INTEN :1; + __IO uint32_t RESEN :1; + __IO uint32_t TWD :2; + __IO uint32_t SPM :1; + __IO uint32_t RESERVED1 :27; + }; + struct { + __IO uint32_t RESERVED0 :2; + __IO uint32_t TWD0 :1; + __IO uint32_t TWD1 :1; + __IO uint32_t RESERVED2 :28; + }; + }; +} stc_swwdt_wdogcontrol_field_t; + +typedef struct stc_swwdt_wdogris_field +{ + __IO uint32_t RIS :1; + __IO uint32_t RESERVED0 :31; +} stc_swwdt_wdogris_field_t; + +typedef struct stc_swwdt_wdogspmc_field +{ + __IO uint32_t TGR :1; + __IO uint32_t RESERVED0 :31; +} stc_swwdt_wdogspmc_field_t; + +/******************************************************************************* +* UNIQUE_ID_MODULE +*******************************************************************************/ +typedef struct stc_unique_id_uidr0_field +{ + union { + struct { + __IO uint32_t RESERVED0 :4; + __IO uint32_t UID :28; + }; + struct { + __IO uint32_t RESERVED1 :4; + __IO uint32_t UID0 :1; + __IO uint32_t UID1 :1; + __IO uint32_t UID2 :1; + __IO uint32_t UID3 :1; + __IO uint32_t UID4 :1; + __IO uint32_t UID5 :1; + __IO uint32_t UID6 :1; + __IO uint32_t UID7 :1; + __IO uint32_t UID8 :1; + __IO uint32_t UID9 :1; + __IO uint32_t UID10 :1; + __IO uint32_t UID11 :1; + __IO uint32_t UID12 :1; + __IO uint32_t UID13 :1; + __IO uint32_t UID14 :1; + __IO uint32_t UID15 :1; + __IO uint32_t UID16 :1; + __IO uint32_t UID17 :1; + __IO uint32_t UID18 :1; + __IO uint32_t UID19 :1; + __IO uint32_t UID20 :1; + __IO uint32_t UID21 :1; + __IO uint32_t UID22 :1; + __IO uint32_t UID23 :1; + __IO uint32_t UID24 :1; + __IO uint32_t UID25 :1; + __IO uint32_t UID26 :1; + __IO uint32_t UID27 :1; + }; + }; +} stc_unique_id_uidr0_field_t; + +typedef struct stc_unique_id_uidr1_field +{ + union { + struct { + __IO uint32_t UID :13; + __IO uint32_t RESERVED0 :19; + }; + struct { + __IO uint32_t UID0 :1; + __IO uint32_t UID1 :1; + __IO uint32_t UID2 :1; + __IO uint32_t UID3 :1; + __IO uint32_t UID4 :1; + __IO uint32_t UID5 :1; + __IO uint32_t UID6 :1; + __IO uint32_t UID7 :1; + __IO uint32_t UID8 :1; + __IO uint32_t UID9 :1; + __IO uint32_t UID10 :1; + __IO uint32_t UID11 :1; + __IO uint32_t UID12 :1; + __IO uint32_t RESERVED1 :19; + }; + }; +} stc_unique_id_uidr1_field_t; + +/******************************************************************************* +* USB_MODULE +*******************************************************************************/ +typedef struct stc_usb_hcnt_field +{ + __IO uint16_t HOST :1; + __IO uint16_t URST :1; + __IO uint16_t SOFIRE :1; + __IO uint16_t DIRE :1; + __IO uint16_t CNNIRE :1; + __IO uint16_t CMPIRE :1; + __IO uint16_t URIRE :1; + __IO uint16_t RWKIRE :1; + __IO uint16_t RETRY :1; + __IO uint16_t CANCEL :1; + __IO uint16_t SOFSTEP :1; + __IO uint16_t RESERVED0 :5; +} stc_usb_hcnt_field_t; + +typedef struct stc_usb_hirq_field +{ + __IO uint8_t SOFIRQ :1; + __IO uint8_t DIRQ :1; + __IO uint8_t CNNIRQ :1; + __IO uint8_t CMPIRQ :1; + __IO uint8_t URIRQ :1; + __IO uint8_t RWKIRQ :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t TCAN :1; +} stc_usb_hirq_field_t; + +typedef struct stc_usb_herr_field +{ + union { + struct { + __IO uint8_t HS :2; + __IO uint8_t STUFF :1; + __IO uint8_t TGERR :1; + __IO uint8_t CRC :1; + __IO uint8_t TOUT :1; + __IO uint8_t RERR :1; + __IO uint8_t LSTSOF :1; + }; + struct { + __IO uint8_t HS0 :1; + __IO uint8_t HS1 :1; + __IO uint8_t RESERVED0 :6; + }; + }; +} stc_usb_herr_field_t; + +typedef struct stc_usb_hstate_field +{ + __IO uint8_t CSTAT :1; + __IO uint8_t TMODE :1; + __IO uint8_t SUSP :1; + __IO uint8_t SOFBUSY :1; + __IO uint8_t CLKSEL :1; + __IO uint8_t ALIVE :1; + __IO uint8_t RESERVED0 :2; +} stc_usb_hstate_field_t; + +typedef struct stc_usb_hfcomp_field +{ + union { + struct { + __IO uint8_t FRAMECOMP :8; + }; + struct { + __IO uint8_t FRAMECOMP0 :1; + __IO uint8_t FRAMECOMP1 :1; + __IO uint8_t FRAMECOMP2 :1; + __IO uint8_t FRAMECOMP3 :1; + __IO uint8_t FRAMECOMP4 :1; + __IO uint8_t FRAMECOMP5 :1; + __IO uint8_t FRAMECOMP6 :1; + __IO uint8_t FRAMECOMP7 :1; + }; + }; +} stc_usb_hfcomp_field_t; + +typedef struct stc_usb_hrtimer_field +{ + union { + struct { + __IO uint16_t RTIMER :16; + }; + struct { + __IO uint16_t RTIMER0 :1; + __IO uint16_t RTIMER1 :1; + __IO uint16_t RTIMER2 :1; + __IO uint16_t RTIMER3 :1; + __IO uint16_t RTIMER4 :1; + __IO uint16_t RTIMER5 :1; + __IO uint16_t RTIMER6 :1; + __IO uint16_t RTIMER7 :1; + __IO uint16_t RTIMER8 :1; + __IO uint16_t RTIMER9 :1; + __IO uint16_t RTIMER10 :1; + __IO uint16_t RTIMER11 :1; + __IO uint16_t RTIMER12 :1; + __IO uint16_t RTIMER13 :1; + __IO uint16_t RTIMER14 :1; + __IO uint16_t RTIMER15 :1; + }; + }; +} stc_usb_hrtimer_field_t; + +typedef struct stc_usb_hrtimer2_field +{ + union { + struct { + __IO uint8_t RTIMER2 :2; + __IO uint8_t RESERVED0 :6; + }; + struct { + __IO uint8_t RTIMER20 :1; + __IO uint8_t RTIMER21 :1; + __IO uint8_t RESERVED1 :6; + }; + }; +} stc_usb_hrtimer2_field_t; + +typedef struct stc_usb_hadr_field +{ + union { + struct { + __IO uint8_t ADDRESS :7; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t ADDRESS0 :1; + __IO uint8_t ADDRESS1 :1; + __IO uint8_t ADDRESS2 :1; + __IO uint8_t ADDRESS3 :1; + __IO uint8_t ADDRESS4 :1; + __IO uint8_t ADDRESS5 :1; + __IO uint8_t ADDRESS6 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_usb_hadr_field_t; + +typedef struct stc_usb_heof_field +{ + union { + struct { + __IO uint16_t HEOF :14; + __IO uint16_t RESERVED0 :2; + }; + struct { + __IO uint16_t HEOF0 :1; + __IO uint16_t HEOF1 :1; + __IO uint16_t HEOF2 :1; + __IO uint16_t HEOF3 :1; + __IO uint16_t HEOF4 :1; + __IO uint16_t HEOF5 :1; + __IO uint16_t HEOF6 :1; + __IO uint16_t HEOF7 :1; + __IO uint16_t HEOF8 :1; + __IO uint16_t HEOF9 :1; + __IO uint16_t HEOF10 :1; + __IO uint16_t HEOF11 :1; + __IO uint16_t HEOF12 :1; + __IO uint16_t HEOF13 :1; + __IO uint16_t RESERVED1 :2; + }; + }; +} stc_usb_heof_field_t; + +typedef struct stc_usb_hframe_field +{ + union { + struct { + __IO uint16_t FRAME :11; + __IO uint16_t RESERVED0 :5; + }; + struct { + __IO uint16_t FRAME0 :1; + __IO uint16_t FRAME1 :1; + __IO uint16_t FRAME2 :1; + __IO uint16_t FRAME3 :1; + __IO uint16_t FRAME4 :1; + __IO uint16_t FRAME5 :1; + __IO uint16_t FRAME6 :1; + __IO uint16_t FRAME7 :1; + __IO uint16_t FRAME8 :1; + __IO uint16_t FRAME9 :1; + __IO uint16_t FRAME10 :1; + __IO uint16_t RESERVED1 :5; + }; + }; +} stc_usb_hframe_field_t; + +typedef struct stc_usb_htoken_field +{ + union { + struct { + __IO uint8_t ENDPT :4; + __IO uint8_t TKNEN :3; + __IO uint8_t TGGL :1; + }; + struct { + __IO uint8_t ENDPT0 :1; + __IO uint8_t ENDPT1 :1; + __IO uint8_t ENDPT2 :1; + __IO uint8_t ENDPT3 :1; + __IO uint8_t TKNEN0 :1; + __IO uint8_t TKNEN1 :1; + __IO uint8_t TKNEN2 :1; + __IO uint8_t RESERVED0 :1; + }; + }; +} stc_usb_htoken_field_t; + +typedef struct stc_usb_udcc_field +{ + __IO uint16_t PWC :1; + __IO uint16_t RFBK :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t STALCLREN :1; + __IO uint16_t USTP :1; + __IO uint16_t HCONX :1; + __IO uint16_t RESUM :1; + __IO uint16_t RST :1; + __IO uint16_t RESERVED1 :8; +} stc_usb_udcc_field_t; + +typedef struct stc_usb_ep0c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t RESERVED1 :6; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep0c_field_t; + +typedef struct stc_usb_ep1c_field +{ + union { + struct { + __IO uint16_t PKS :9; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t PKS7 :1; + __IO uint16_t PKS8 :1; + __IO uint16_t RESERVED0 :4; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED1 :1; + }; + }; +} stc_usb_ep1c_field_t; + +typedef struct stc_usb_ep2c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep2c_field_t; + +typedef struct stc_usb_ep3c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep3c_field_t; + +typedef struct stc_usb_ep4c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep4c_field_t; + +typedef struct stc_usb_ep5c_field +{ + union { + struct { + __IO uint16_t PKS :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t STAL :1; + __IO uint16_t NULE :1; + __IO uint16_t DMAE :1; + __IO uint16_t DIR :1; + __IO uint16_t TYPE :2; + __IO uint16_t EPEN :1; + }; + struct { + __IO uint16_t PKS0 :1; + __IO uint16_t PKS1 :1; + __IO uint16_t PKS2 :1; + __IO uint16_t PKS3 :1; + __IO uint16_t PKS4 :1; + __IO uint16_t PKS5 :1; + __IO uint16_t PKS6 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t TYPE0 :1; + __IO uint16_t TYPE1 :1; + __IO uint16_t RESERVED2 :1; + }; + }; +} stc_usb_ep5c_field_t; + +typedef struct stc_usb_tmsp_field +{ + union { + struct { + __IO uint16_t TMSP :11; + __IO uint16_t RESERVED0 :5; + }; + struct { + __IO uint16_t TMSP0 :1; + __IO uint16_t TMSP1 :1; + __IO uint16_t TMSP2 :1; + __IO uint16_t TMSP3 :1; + __IO uint16_t TMSP4 :1; + __IO uint16_t TMSP5 :1; + __IO uint16_t TMSP6 :1; + __IO uint16_t TMSP7 :1; + __IO uint16_t TMSP8 :1; + __IO uint16_t TMSP9 :1; + __IO uint16_t TMSP10 :1; + __IO uint16_t RESERVED1 :5; + }; + }; +} stc_usb_tmsp_field_t; + +typedef struct stc_usb_udcs_field +{ + __IO uint8_t CONF :1; + __IO uint8_t SETP :1; + __IO uint8_t WKUP :1; + __IO uint8_t BRST :1; + __IO uint8_t SOF :1; + __IO uint8_t SUSP :1; + __IO uint8_t RESERVED0 :2; +} stc_usb_udcs_field_t; + +typedef struct stc_usb_udcie_field +{ + __IO uint8_t CONFIE :1; + __IO uint8_t CONFN :1; + __IO uint8_t WKUPIE :1; + __IO uint8_t BRSTIE :1; + __IO uint8_t SOFIE :1; + __IO uint8_t SUSPIE :1; + __IO uint8_t RESERVED0 :2; +} stc_usb_udcie_field_t; + +typedef struct stc_usb_ep0is_field +{ + __IO uint16_t RESERVED0 :10; + __IO uint16_t DRQI :1; + __IO uint16_t RESERVED1 :3; + __IO uint16_t DRQIIE :1; + __IO uint16_t BFINI :1; +} stc_usb_ep0is_field_t; + +typedef struct stc_usb_ep0os_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQO :1; + __IO uint16_t RESERVED1 :2; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQOIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep0os_field_t; + +typedef struct stc_usb_ep1s_field +{ + union { + struct { + __IO uint16_t SIZE :9; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED0 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t SIZE7 :1; + __IO uint16_t SIZE8 :1; + __IO uint16_t RESERVED1 :7; + }; + }; +} stc_usb_ep1s_field_t; + +typedef struct stc_usb_ep2s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep2s_field_t; + +typedef struct stc_usb_ep3s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep3s_field_t; + +typedef struct stc_usb_ep4s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep4s_field_t; + +typedef struct stc_usb_ep5s_field +{ + union { + struct { + __IO uint16_t SIZE :7; + __IO uint16_t RESERVED0 :2; + __IO uint16_t SPK :1; + __IO uint16_t DRQ :1; + __IO uint16_t BUSY :1; + __IO uint16_t RESERVED1 :1; + __IO uint16_t SPKIE :1; + __IO uint16_t DRQIE :1; + __IO uint16_t BFINI :1; + }; + struct { + __IO uint16_t SIZE0 :1; + __IO uint16_t SIZE1 :1; + __IO uint16_t SIZE2 :1; + __IO uint16_t SIZE3 :1; + __IO uint16_t SIZE4 :1; + __IO uint16_t SIZE5 :1; + __IO uint16_t SIZE6 :1; + __IO uint16_t RESERVED2 :9; + }; + }; +} stc_usb_ep5s_field_t; + +typedef struct stc_usb_ep0dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep0dt_field_t; + +typedef struct stc_usb_ep1dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep1dt_field_t; + +typedef struct stc_usb_ep2dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep2dt_field_t; + +typedef struct stc_usb_ep3dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep3dt_field_t; + +typedef struct stc_usb_ep4dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep4dt_field_t; + +typedef struct stc_usb_ep5dt_field +{ + union { + struct { + __IO uint16_t BFDT :16; + }; + struct { + __IO uint16_t BFDT0 :1; + __IO uint16_t BFDT1 :1; + __IO uint16_t BFDT2 :1; + __IO uint16_t BFDT3 :1; + __IO uint16_t BFDT4 :1; + __IO uint16_t BFDT5 :1; + __IO uint16_t BFDT6 :1; + __IO uint16_t BFDT7 :1; + __IO uint16_t BFDT8 :1; + __IO uint16_t BFDT9 :1; + __IO uint16_t BFDT10 :1; + __IO uint16_t BFDT11 :1; + __IO uint16_t BFDT12 :1; + __IO uint16_t BFDT13 :1; + __IO uint16_t BFDT14 :1; + __IO uint16_t BFDT15 :1; + }; + }; +} stc_usb_ep5dt_field_t; + +/******************************************************************************* +* USBCLK_MODULE +*******************************************************************************/ +typedef struct stc_usbclk_uccr_field +{ + __IO uint8_t UCEN0 :1; + __IO uint8_t UCSEL :1; + __IO uint8_t RESERVED0 :1; + __IO uint8_t UCEN1 :1; + __IO uint8_t RESERVED1 :4; +} stc_usbclk_uccr_field_t; + +typedef struct stc_usbclk_upcr1_field +{ + __IO uint8_t UPLLEN :1; + __IO uint8_t UPINC :1; + __IO uint8_t RESERVED0 :6; +} stc_usbclk_upcr1_field_t; + +typedef struct stc_usbclk_upcr2_field +{ + union { + struct { + __IO uint8_t UPOWT :3; + __IO uint8_t RESERVED0 :5; + }; + struct { + __IO uint8_t UPOWT0 :1; + __IO uint8_t UPOWT1 :1; + __IO uint8_t UPOWT2 :1; + __IO uint8_t RESERVED1 :5; + }; + }; +} stc_usbclk_upcr2_field_t; + +typedef struct stc_usbclk_upcr3_field +{ + union { + struct { + __IO uint8_t UPLLK :5; + __IO uint8_t RESERVED0 :3; + }; + struct { + __IO uint8_t UPLLK0 :1; + __IO uint8_t UPLLK1 :1; + __IO uint8_t UPLLK2 :1; + __IO uint8_t UPLLK3 :1; + __IO uint8_t UPLLK4 :1; + __IO uint8_t RESERVED1 :3; + }; + }; +} stc_usbclk_upcr3_field_t; + +typedef struct stc_usbclk_upcr4_field +{ + union { + struct { + __IO uint8_t UPLLN :7; + __IO uint8_t RESERVED0 :1; + }; + struct { + __IO uint8_t UPLLN0 :1; + __IO uint8_t UPLLN1 :1; + __IO uint8_t UPLLN2 :1; + __IO uint8_t UPLLN3 :1; + __IO uint8_t UPLLN4 :1; + __IO uint8_t UPLLN5 :1; + __IO uint8_t UPLLN6 :1; + __IO uint8_t RESERVED1 :1; + }; + }; +} stc_usbclk_upcr4_field_t; + +typedef struct stc_usbclk_up_str_field +{ + __IO uint8_t UPRDY :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_up_str_field_t; + +typedef struct stc_usbclk_upint_enr_field +{ + __IO uint8_t UPCSE :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_upint_enr_field_t; + +typedef struct stc_usbclk_upint_clr_field +{ + __IO uint8_t UPCSC :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_upint_clr_field_t; + +typedef struct stc_usbclk_upint_str_field +{ + __IO uint8_t UPCSI :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_upint_str_field_t; + +typedef struct stc_usbclk_upcr5_field +{ + union { + struct { + __IO uint8_t UPLLM :4; + __IO uint8_t RESERVED0 :4; + }; + struct { + __IO uint8_t UPLLM0 :1; + __IO uint8_t UPLLM1 :1; + __IO uint8_t UPLLM2 :1; + __IO uint8_t UPLLM3 :1; + __IO uint8_t RESERVED1 :4; + }; + }; +} stc_usbclk_upcr5_field_t; + +typedef struct stc_usbclk_usben0_field +{ + __IO uint8_t USBEN0 :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_usben0_field_t; + +typedef struct stc_usbclk_usben1_field +{ + __IO uint8_t USBEN1 :1; + __IO uint8_t RESERVED0 :7; +} stc_usbclk_usben1_field_t; + +/******************************************************************************* +* WC_MODULE +*******************************************************************************/ +typedef struct stc_wc_wcrd_field +{ + union { + struct { + __IO uint8_t CTR :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t CTR0 :1; + __IO uint8_t CTR1 :1; + __IO uint8_t CTR2 :1; + __IO uint8_t CTR3 :1; + __IO uint8_t CTR4 :1; + __IO uint8_t CTR5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_wc_wcrd_field_t; + +typedef struct stc_wc_wcrl_field +{ + union { + struct { + __IO uint8_t RLC :6; + __IO uint8_t RESERVED0 :2; + }; + struct { + __IO uint8_t RLC0 :1; + __IO uint8_t RLC1 :1; + __IO uint8_t RLC2 :1; + __IO uint8_t RLC3 :1; + __IO uint8_t RLC4 :1; + __IO uint8_t RLC5 :1; + __IO uint8_t RESERVED1 :2; + }; + }; +} stc_wc_wcrl_field_t; + +typedef struct stc_wc_wccr_field +{ + union { + struct { + __IO uint8_t WCIF :1; + __IO uint8_t WCIE :1; + __IO uint8_t CS :2; + __IO uint8_t RESERVED1 :2; + __IO uint8_t WCOP :1; + __IO uint8_t WCEN :1; + }; + struct { + __IO uint8_t RESERVED0 :2; + __IO uint8_t CS0 :1; + __IO uint8_t CS1 :1; + __IO uint8_t RESERVED2 :4; + }; + }; +} stc_wc_wccr_field_t; + +typedef struct stc_wc_clk_sel_field +{ + union { + struct { + __IO uint16_t SEL_IN :2; + __IO uint16_t RESERVED0 :6; + __IO uint16_t SEL_OUT :3; + __IO uint16_t RESERVED2 :5; + }; + struct { + __IO uint16_t SEL_IN0 :1; + __IO uint16_t SEL_IN1 :1; + __IO uint16_t RESERVED1 :6; + __IO uint16_t SEL_OUT0 :1; + __IO uint16_t SEL_OUT1 :1; + __IO uint16_t SEL_OUT2 :1; + __IO uint16_t RESERVED3 :5; + }; + }; +} stc_wc_clk_sel_field_t; + +typedef struct stc_wc_clk_en_field +{ + __IO uint8_t CLK_EN :1; + __IO uint8_t CLK_EN_R :1; + __IO uint8_t RESERVED0 :6; +} stc_wc_clk_en_field_t; + +/******************************************************************************* +* Peripheral register structures +*******************************************************************************/ + +/******************************************************************************* +* ADC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t ADSR; + stc_adc_adsr_field_t ADSR_f; + }; + union { + __IO uint8_t ADCR; + stc_adc_adcr_field_t ADCR_f; + }; + __IO uint8_t RESERVED0[6]; + union { + __IO uint8_t SFNS; + stc_adc_sfns_field_t SFNS_f; + }; + union { + __IO uint8_t SCCR; + stc_adc_sccr_field_t SCCR_f; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint32_t SCFD; + stc_adc_scfd_field_t SCFD_f; + struct { + union { + __IO uint16_t SCFDL; + struct { + __IO uint8_t SCFDLL; + __IO uint8_t SCFDLH; + }; + }; + union { + __IO uint16_t SCFDH; + struct { + __IO uint8_t SCFDHL; + __IO uint8_t SCFDHH; + }; + }; + }; + __IO uint32_t SCFD_FDAS1; + stc_adc_scfd_fdas1_field_t SCFD_FDAS1_f; + struct { + union { + __IO uint16_t SCFD_FDAS1L; + struct { + __IO uint8_t SCFD_FDAS1LL; + __IO uint8_t SCFD_FDAS1LH; + }; + }; + union { + __IO uint16_t SCFD_FDAS1H; + struct { + __IO uint8_t SCFD_FDAS1HL; + __IO uint8_t SCFD_FDAS1HH; + }; + }; + }; + }; + union { + __IO uint16_t SCIS23; + stc_adc_scis23_field_t SCIS23_f; + struct { + __IO uint8_t SCIS23L; + __IO uint8_t SCIS23H; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t SCIS01; + stc_adc_scis01_field_t SCIS01_f; + struct { + __IO uint8_t SCIS01L; + __IO uint8_t SCIS01H; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint8_t PFNS; + stc_adc_pfns_field_t PFNS_f; + }; + union { + __IO uint8_t PCCR; + stc_adc_pccr_field_t PCCR_f; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint32_t PCFD; + stc_adc_pcfd_field_t PCFD_f; + struct { + union { + __IO uint16_t PCFDL; + struct { + __IO uint8_t PCFDLL; + __IO uint8_t PCFDLH; + }; + }; + union { + __IO uint16_t PCFDH; + struct { + __IO uint8_t PCFDHL; + __IO uint8_t PCFDHH; + }; + }; + }; + __IO uint32_t PCFD_FDAS1; + stc_adc_pcfd_fdas1_field_t PCFD_FDAS1_f; + struct { + union { + __IO uint16_t PCFD_FDAS1L; + struct { + __IO uint8_t PCFD_FDAS1LL; + __IO uint8_t PCFD_FDAS1LH; + }; + }; + union { + __IO uint16_t PCFD_FDAS1H; + struct { + __IO uint8_t PCFD_FDAS1HL; + __IO uint8_t PCFD_FDAS1HH; + }; + }; + }; + }; + union { + __IO uint8_t PCIS; + stc_adc_pcis_field_t PCIS_f; + }; + __IO uint8_t RESERVED5[3]; + union { + __IO uint8_t CMPCR; + stc_adc_cmpcr_field_t CMPCR_f; + }; + __IO uint8_t RESERVED6[1]; + union { + __IO uint16_t CMPD; + stc_adc_cmpd_field_t CMPD_f; + struct { + __IO uint8_t CMPDL; + __IO uint8_t CMPDH; + }; + }; + union { + __IO uint16_t ADSS23; + stc_adc_adss23_field_t ADSS23_f; + struct { + __IO uint8_t ADSS23L; + __IO uint8_t ADSS23H; + }; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint16_t ADSS01; + stc_adc_adss01_field_t ADSS01_f; + struct { + __IO uint8_t ADSS01L; + __IO uint8_t ADSS01H; + }; + }; + __IO uint8_t RESERVED8[2]; + union { + __IO uint16_t ADST01; + stc_adc_adst01_field_t ADST01_f; + struct { + __IO uint8_t ADST01L; + __IO uint8_t ADST01H; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint8_t ADCT; + stc_adc_adct_field_t ADCT_f; + }; + __IO uint8_t RESERVED10[3]; + union { + __IO uint8_t PRTSL; + stc_adc_prtsl_field_t PRTSL_f; + }; + union { + __IO uint8_t SCTSL; + stc_adc_sctsl_field_t SCTSL_f; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t ADCEN; + stc_adc_adcen_field_t ADCEN_f; + struct { + __IO uint8_t ADCENL; + __IO uint8_t ADCENH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint32_t CALSR; + stc_adc_calsr_field_t CALSR_f; + struct { + union { + __IO uint16_t CALSRL; + struct { + __IO uint8_t CALSRLL; + __IO uint8_t CALSRLH; + }; + }; + union { + __IO uint16_t CALSRH; + struct { + __IO uint8_t CALSRHL; + __IO uint8_t CALSRHH; + }; + }; + }; + }; + union { + __IO uint8_t WCMRCOT; + stc_adc_wcmrcot_field_t WCMRCOT_f; + }; + __IO uint8_t RESERVED13[3]; + union { + __IO uint8_t WCMRCIF; + stc_adc_wcmrcif_field_t WCMRCIF_f; + }; + __IO uint8_t RESERVED14[3]; + union { + __IO uint8_t WCMPCR; + stc_adc_wcmpcr_field_t WCMPCR_f; + }; + union { + __IO uint8_t WCMPSR; + stc_adc_wcmpsr_field_t WCMPSR_f; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint16_t WCMPDL; + stc_adc_wcmpdl_field_t WCMPDL_f; + struct { + __IO uint8_t WCMPDLL; + __IO uint8_t WCMPDLH; + }; + }; + union { + __IO uint16_t WCMPDH; + stc_adc_wcmpdh_field_t WCMPDH_f; + struct { + __IO uint8_t WCMPDHL; + __IO uint8_t WCMPDHH; + }; + }; +} FM_ADC_TypeDef, FM4_ADC_TypeDef; + +/******************************************************************************* +* BT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PRLL; + struct { + __IO uint8_t PRLLL; + __IO uint8_t PRLLH; + }; + __IO uint16_t PPG_PRLL; + struct { + __IO uint8_t PPG_PRLLL; + __IO uint8_t PPG_PRLLH; + }; + __IO uint16_t PCSR; + struct { + __IO uint8_t PCSRL; + __IO uint8_t PCSRH; + }; + __IO uint16_t PWM_PCSR; + struct { + __IO uint8_t PWM_PCSRL; + __IO uint8_t PWM_PCSRH; + }; + __IO uint16_t RT_PCSR; + struct { + __IO uint8_t RT_PCSRL; + __IO uint8_t RT_PCSRH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t PRLH; + struct { + __IO uint8_t PRLHL; + __IO uint8_t PRLHH; + }; + __IO uint16_t PPG_PRLH; + struct { + __IO uint8_t PPG_PRLHL; + __IO uint8_t PPG_PRLHH; + }; + __IO uint16_t DTBF; + struct { + __IO uint8_t DTBFL; + __IO uint8_t DTBFH; + }; + __IO uint16_t PWC_DTBF; + struct { + __IO uint8_t PWC_DTBFL; + __IO uint8_t PWC_DTBFH; + }; + __IO uint16_t PDUT; + struct { + __IO uint8_t PDUTL; + __IO uint8_t PDUTH; + }; + __IO uint16_t PWM_PDUT; + struct { + __IO uint8_t PWM_PDUTL; + __IO uint8_t PWM_PDUTH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + __IO uint16_t PPG_TMR; + struct { + __IO uint8_t PPG_TMRL; + __IO uint8_t PPG_TMRH; + }; + __IO uint16_t PWM_TMR; + struct { + __IO uint8_t PWM_TMRL; + __IO uint8_t PWM_TMRH; + }; + __IO uint16_t RT_TMR; + struct { + __IO uint8_t RT_TMRL; + __IO uint8_t RT_TMRH; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t TMCR; + stc_bt_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + __IO uint16_t PPG_TMCR; + stc_bt_ppg_tmcr_field_t PPG_TMCR_f; + struct { + __IO uint8_t PPG_TMCRL; + __IO uint8_t PPG_TMCRH; + }; + __IO uint16_t PWC_TMCR; + stc_bt_pwc_tmcr_field_t PWC_TMCR_f; + struct { + __IO uint8_t PWC_TMCRL; + __IO uint8_t PWC_TMCRH; + }; + __IO uint16_t PWM_TMCR; + stc_bt_pwm_tmcr_field_t PWM_TMCR_f; + struct { + __IO uint8_t PWM_TMCRL; + __IO uint8_t PWM_TMCRH; + }; + __IO uint16_t RT_TMCR; + stc_bt_rt_tmcr_field_t RT_TMCR_f; + struct { + __IO uint8_t RT_TMCRL; + __IO uint8_t RT_TMCRH; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint8_t STC; + stc_bt_stc_field_t STC_f; + __IO uint8_t PPG_STC; + stc_bt_ppg_stc_field_t PPG_STC_f; + __IO uint8_t PWC_STC; + stc_bt_pwc_stc_field_t PWC_STC_f; + __IO uint8_t PWM_STC; + stc_bt_pwm_stc_field_t PWM_STC_f; + __IO uint8_t RT_STC; + stc_bt_rt_stc_field_t RT_STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_tmcr2_field_t TMCR2_f; + __IO uint8_t PPG_TMCR2; + stc_bt_ppg_tmcr2_field_t PPG_TMCR2_f; + __IO uint8_t PWC_TMCR2; + stc_bt_pwc_tmcr2_field_t PWC_TMCR2_f; + __IO uint8_t PWM_TMCR2; + stc_bt_pwm_tmcr2_field_t PWM_TMCR2_f; + __IO uint8_t RT_TMCR2; + stc_bt_rt_tmcr2_field_t RT_TMCR2_f; + }; +} FM_BT_TypeDef, FM4_BT_TypeDef; + +/******************************************************************************* +* BT_PPG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PRLL; + struct { + __IO uint8_t PRLLL; + __IO uint8_t PRLLH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t PRLH; + struct { + __IO uint8_t PRLHL; + __IO uint8_t PRLHH; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint16_t TMCR; + stc_bt_ppg_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint8_t STC; + stc_bt_ppg_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_ppg_tmcr2_field_t TMCR2_f; + }; +} FM_BT_PPG_TypeDef, FM4_BT_PPG_TypeDef; + +/******************************************************************************* +* BT_PWC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED8[4]; + union { + __IO uint16_t DTBF; + struct { + __IO uint8_t DTBFL; + __IO uint8_t DTBFH; + }; + }; + __IO uint8_t RESERVED9[6]; + union { + __IO uint16_t TMCR; + stc_bt_pwc_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint8_t STC; + stc_bt_pwc_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwc_tmcr2_field_t TMCR2_f; + }; +} FM_BT_PWC_TypeDef, FM4_BT_PWC_TypeDef; + +/******************************************************************************* +* BT_PWM_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PCSR; + struct { + __IO uint8_t PCSRL; + __IO uint8_t PCSRH; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t PDUT; + struct { + __IO uint8_t PDUTL; + __IO uint8_t PDUTH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint16_t TMCR; + stc_bt_pwm_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED14[2]; + union { + __IO uint8_t STC; + stc_bt_pwm_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_pwm_tmcr2_field_t TMCR2_f; + }; +} FM_BT_PWM_TypeDef, FM4_BT_PWM_TypeDef; + +/******************************************************************************* +* BT_RT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t PCSR; + struct { + __IO uint8_t PCSRL; + __IO uint8_t PCSRH; + }; + }; + __IO uint8_t RESERVED15[6]; + union { + __IO uint16_t TMR; + struct { + __IO uint8_t TMRL; + __IO uint8_t TMRH; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint16_t TMCR; + stc_bt_rt_tmcr_field_t TMCR_f; + struct { + __IO uint8_t TMCRL; + __IO uint8_t TMCRH; + }; + }; + __IO uint8_t RESERVED17[2]; + union { + __IO uint8_t STC; + stc_bt_rt_stc_field_t STC_f; + }; + union { + __IO uint8_t TMCR2; + stc_bt_rt_tmcr2_field_t TMCR2_f; + }; +} FM_BT_RT_TypeDef, FM4_BT_RT_TypeDef; + +/******************************************************************************* +* BTIOSEL03_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSEL0123; + stc_btiosel03_btsel0123_field_t BTSEL0123_f; + }; +} FM_BTIOSEL03_TypeDef, FM4_BTIOSEL03_TypeDef; + +/******************************************************************************* +* BTIOSEL47_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSEL4567; + stc_btiosel47_btsel4567_field_t BTSEL4567_f; + }; +} FM_BTIOSEL47_TypeDef, FM4_BTIOSEL47_TypeDef; + +/******************************************************************************* +* BTIOSEL8B_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSEL89AB; + stc_btiosel8b_btsel89ab_field_t BTSEL89AB_f; + }; +} FM_BTIOSEL8B_TypeDef, FM4_BTIOSEL8B_TypeDef; + +/******************************************************************************* +* BTIOSELCF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t BTSELCDEF; + stc_btioselcf_btselcdef_field_t BTSELCDEF_f; + }; +} FM_BTIOSELCF_TypeDef, FM4_BTIOSELCF_TypeDef; + +/******************************************************************************* +* CAN_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t CTRLR; + stc_can_ctrlr_field_t CTRLR_f; + struct { + __IO uint8_t CTRLRL; + __IO uint8_t CTRLRH; + }; + }; + union { + __IO uint16_t STATR; + stc_can_statr_field_t STATR_f; + struct { + __IO uint8_t STATRL; + __IO uint8_t STATRH; + }; + }; + union { + __IO uint16_t ERRCNT; + stc_can_errcnt_field_t ERRCNT_f; + struct { + __IO uint8_t ERRCNTL; + __IO uint8_t ERRCNTH; + }; + }; + union { + __IO uint16_t BTR; + stc_can_btr_field_t BTR_f; + struct { + __IO uint8_t BTRL; + __IO uint8_t BTRH; + }; + }; + union { + __IO uint16_t INTR; + stc_can_intr_field_t INTR_f; + struct { + __IO uint8_t INTRL; + __IO uint8_t INTRH; + }; + }; + union { + __IO uint16_t TESTR; + stc_can_testr_field_t TESTR_f; + struct { + __IO uint8_t TESTRL; + __IO uint8_t TESTRH; + }; + }; + union { + __IO uint16_t BRPER; + stc_can_brper_field_t BRPER_f; + struct { + __IO uint8_t BRPERL; + __IO uint8_t BRPERH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t IF1CREQ; + stc_can_if1creq_field_t IF1CREQ_f; + struct { + __IO uint8_t IF1CREQL; + __IO uint8_t IF1CREQH; + }; + }; + union { + __IO uint16_t IF1CMSK; + stc_can_if1cmsk_field_t IF1CMSK_f; + struct { + __IO uint8_t IF1CMSKL; + __IO uint8_t IF1CMSKH; + }; + }; + union { + __IO uint32_t IF1MSK; + stc_can_if1msk_field_t IF1MSK_f; + struct { + union { + __IO uint16_t IF1MSKL; + struct { + __IO uint8_t IF1MSKLL; + __IO uint8_t IF1MSKLH; + }; + }; + union { + __IO uint16_t IF1MSKH; + struct { + __IO uint8_t IF1MSKHL; + __IO uint8_t IF1MSKHH; + }; + }; + }; + }; + union { + __IO uint32_t IF1ARB; + stc_can_if1arb_field_t IF1ARB_f; + struct { + union { + __IO uint16_t IF1ARBL; + struct { + __IO uint8_t IF1ARBLL; + __IO uint8_t IF1ARBLH; + }; + }; + union { + __IO uint16_t IF1ARBH; + struct { + __IO uint8_t IF1ARBHL; + __IO uint8_t IF1ARBHH; + }; + }; + }; + }; + union { + __IO uint16_t IF1MCTR; + stc_can_if1mctr_field_t IF1MCTR_f; + struct { + __IO uint8_t IF1MCTRL; + __IO uint8_t IF1MCTRH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint32_t IF1DTA_L; + stc_can_if1dta_l_field_t IF1DTA_L_f; + struct { + union { + __IO uint16_t IF1DTA_LL; + struct { + __IO uint8_t IF1DTA_LLL; + __IO uint8_t IF1DTA_LLH; + }; + }; + union { + __IO uint16_t IF1DTA_LH; + struct { + __IO uint8_t IF1DTA_LHL; + __IO uint8_t IF1DTA_LHH; + }; + }; + }; + }; + union { + __IO uint32_t IF1DTB_L; + stc_can_if1dtb_l_field_t IF1DTB_L_f; + struct { + union { + __IO uint16_t IF1DTB_LL; + struct { + __IO uint8_t IF1DTB_LLL; + __IO uint8_t IF1DTB_LLH; + }; + }; + union { + __IO uint16_t IF1DTB_LH; + struct { + __IO uint8_t IF1DTB_LHL; + __IO uint8_t IF1DTB_LHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[8]; + union { + __IO uint32_t IF1DTA_B; + stc_can_if1dta_b_field_t IF1DTA_B_f; + struct { + union { + __IO uint16_t IF1DTA_BL; + struct { + __IO uint8_t IF1DTA_BLL; + __IO uint8_t IF1DTA_BLH; + }; + }; + union { + __IO uint16_t IF1DTA_BH; + struct { + __IO uint8_t IF1DTA_BHL; + __IO uint8_t IF1DTA_BHH; + }; + }; + }; + }; + union { + __IO uint32_t IF1DTB_B; + stc_can_if1dtb_b_field_t IF1DTB_B_f; + struct { + union { + __IO uint16_t IF1DTB_BL; + struct { + __IO uint8_t IF1DTB_BLL; + __IO uint8_t IF1DTB_BLH; + }; + }; + union { + __IO uint16_t IF1DTB_BH; + struct { + __IO uint8_t IF1DTB_BHL; + __IO uint8_t IF1DTB_BHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[8]; + union { + __IO uint16_t IF2CREQ; + stc_can_if2creq_field_t IF2CREQ_f; + struct { + __IO uint8_t IF2CREQL; + __IO uint8_t IF2CREQH; + }; + }; + union { + __IO uint16_t IF2CMSK; + stc_can_if2cmsk_field_t IF2CMSK_f; + struct { + __IO uint8_t IF2CMSKL; + __IO uint8_t IF2CMSKH; + }; + }; + union { + __IO uint32_t IF2MSK; + stc_can_if2msk_field_t IF2MSK_f; + struct { + union { + __IO uint16_t IF2MSKL; + struct { + __IO uint8_t IF2MSKLL; + __IO uint8_t IF2MSKLH; + }; + }; + union { + __IO uint16_t IF2MSKH; + struct { + __IO uint8_t IF2MSKHL; + __IO uint8_t IF2MSKHH; + }; + }; + }; + }; + union { + __IO uint32_t IF2ARB; + stc_can_if2arb_field_t IF2ARB_f; + struct { + union { + __IO uint16_t IF2ARBL; + struct { + __IO uint8_t IF2ARBLL; + __IO uint8_t IF2ARBLH; + }; + }; + union { + __IO uint16_t IF2ARBH; + struct { + __IO uint8_t IF2ARBHL; + __IO uint8_t IF2ARBHH; + }; + }; + }; + }; + union { + __IO uint16_t IF2MCTR; + stc_can_if2mctr_field_t IF2MCTR_f; + struct { + __IO uint8_t IF2MCTRL; + __IO uint8_t IF2MCTRH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint32_t IF2DTA_L; + stc_can_if2dta_l_field_t IF2DTA_L_f; + struct { + union { + __IO uint16_t IF2DTA_LL; + struct { + __IO uint8_t IF2DTA_LLL; + __IO uint8_t IF2DTA_LLH; + }; + }; + union { + __IO uint16_t IF2DTA_LH; + struct { + __IO uint8_t IF2DTA_LHL; + __IO uint8_t IF2DTA_LHH; + }; + }; + }; + }; + union { + __IO uint32_t IF2DTB_L; + stc_can_if2dtb_l_field_t IF2DTB_L_f; + struct { + union { + __IO uint16_t IF2DTB_LL; + struct { + __IO uint8_t IF2DTB_LLL; + __IO uint8_t IF2DTB_LLH; + }; + }; + union { + __IO uint16_t IF2DTB_LH; + struct { + __IO uint8_t IF2DTB_LHL; + __IO uint8_t IF2DTB_LHH; + }; + }; + }; + }; + __IO uint8_t RESERVED5[8]; + union { + __IO uint32_t IF2DTA_B; + stc_can_if2dta_b_field_t IF2DTA_B_f; + struct { + union { + __IO uint16_t IF2DTA_BL; + struct { + __IO uint8_t IF2DTA_BLL; + __IO uint8_t IF2DTA_BLH; + }; + }; + union { + __IO uint16_t IF2DTA_BH; + struct { + __IO uint8_t IF2DTA_BHL; + __IO uint8_t IF2DTA_BHH; + }; + }; + }; + }; + union { + __IO uint32_t IF2DTB_B; + stc_can_if2dtb_b_field_t IF2DTB_B_f; + struct { + union { + __IO uint16_t IF2DTB_BL; + struct { + __IO uint8_t IF2DTB_BLL; + __IO uint8_t IF2DTB_BLH; + }; + }; + union { + __IO uint16_t IF2DTB_BH; + struct { + __IO uint8_t IF2DTB_BHL; + __IO uint8_t IF2DTB_BHH; + }; + }; + }; + }; + __IO uint8_t RESERVED6[24]; + union { + __IO uint32_t TREQR; + stc_can_treqr_field_t TREQR_f; + struct { + union { + __IO uint16_t TREQRL; + struct { + __IO uint8_t TREQRLL; + __IO uint8_t TREQRLH; + }; + }; + union { + __IO uint16_t TREQRH; + struct { + __IO uint8_t TREQRHL; + __IO uint8_t TREQRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED7[12]; + union { + __IO uint32_t NEWDT; + stc_can_newdt_field_t NEWDT_f; + struct { + union { + __IO uint16_t NEWDTL; + struct { + __IO uint8_t NEWDTLL; + __IO uint8_t NEWDTLH; + }; + }; + union { + __IO uint16_t NEWDTH; + struct { + __IO uint8_t NEWDTHL; + __IO uint8_t NEWDTHH; + }; + }; + }; + }; + __IO uint8_t RESERVED8[12]; + union { + __IO uint32_t INTPND; + stc_can_intpnd_field_t INTPND_f; + struct { + union { + __IO uint16_t INTPNDL; + struct { + __IO uint8_t INTPNDLL; + __IO uint8_t INTPNDLH; + }; + }; + union { + __IO uint16_t INTPNDH; + struct { + __IO uint8_t INTPNDHL; + __IO uint8_t INTPNDHH; + }; + }; + }; + }; + __IO uint8_t RESERVED9[12]; + union { + __IO uint32_t MSGVAL; + stc_can_msgval_field_t MSGVAL_f; + struct { + union { + __IO uint16_t MSGVALL; + struct { + __IO uint8_t MSGVALLL; + __IO uint8_t MSGVALLH; + }; + }; + union { + __IO uint16_t MSGVALH; + struct { + __IO uint8_t MSGVALHL; + __IO uint8_t MSGVALHH; + }; + }; + }; + }; +} FM_CAN_TypeDef, FM4_CAN_TypeDef; + +/******************************************************************************* +* CANFD_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t CREL; + stc_canfd_crel_field_t CREL_f; + struct { + union { + __IO uint16_t CRELL; + struct { + __IO uint8_t CRELLL; + __IO uint8_t CRELLH; + }; + }; + union { + __IO uint16_t CRELH; + struct { + __IO uint8_t CRELHL; + __IO uint8_t CRELHH; + }; + }; + }; + }; + union { + __IO uint32_t ENDN; + stc_canfd_endn_field_t ENDN_f; + struct { + union { + __IO uint16_t ENDNL; + struct { + __IO uint8_t ENDNLL; + __IO uint8_t ENDNLH; + }; + }; + union { + __IO uint16_t ENDNH; + struct { + __IO uint8_t ENDNHL; + __IO uint8_t ENDNHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t FBTP; + stc_canfd_fbtp_field_t FBTP_f; + struct { + union { + __IO uint16_t FBTPL; + struct { + __IO uint8_t FBTPLL; + __IO uint8_t FBTPLH; + }; + }; + union { + __IO uint16_t FBTPH; + struct { + __IO uint8_t FBTPHL; + __IO uint8_t FBTPHH; + }; + }; + }; + }; + union { + __IO uint32_t TEST; + stc_canfd_test_field_t TEST_f; + struct { + union { + __IO uint16_t TESTL; + struct { + __IO uint8_t TESTLL; + __IO uint8_t TESTLH; + }; + }; + union { + __IO uint16_t TESTH; + struct { + __IO uint8_t TESTHL; + __IO uint8_t TESTHH; + }; + }; + }; + }; + union { + __IO uint32_t RWD; + stc_canfd_rwd_field_t RWD_f; + struct { + union { + __IO uint16_t RWDL; + struct { + __IO uint8_t RWDLL; + __IO uint8_t RWDLH; + }; + }; + union { + __IO uint16_t RWDH; + struct { + __IO uint8_t RWDHL; + __IO uint8_t RWDHH; + }; + }; + }; + }; + union { + __IO uint32_t CCCR; + stc_canfd_cccr_field_t CCCR_f; + struct { + union { + __IO uint16_t CCCRL; + struct { + __IO uint8_t CCCRLL; + __IO uint8_t CCCRLH; + }; + }; + union { + __IO uint16_t CCCRH; + struct { + __IO uint8_t CCCRHL; + __IO uint8_t CCCRHH; + }; + }; + }; + }; + union { + __IO uint32_t BTP; + stc_canfd_btp_field_t BTP_f; + struct { + union { + __IO uint16_t BTPL; + struct { + __IO uint8_t BTPLL; + __IO uint8_t BTPLH; + }; + }; + union { + __IO uint16_t BTPH; + struct { + __IO uint8_t BTPHL; + __IO uint8_t BTPHH; + }; + }; + }; + }; + union { + __IO uint32_t TSCC; + stc_canfd_tscc_field_t TSCC_f; + struct { + union { + __IO uint16_t TSCCL; + struct { + __IO uint8_t TSCCLL; + __IO uint8_t TSCCLH; + }; + }; + union { + __IO uint16_t TSCCH; + struct { + __IO uint8_t TSCCHL; + __IO uint8_t TSCCHH; + }; + }; + }; + }; + union { + __IO uint32_t TSCV; + stc_canfd_tscv_field_t TSCV_f; + struct { + union { + __IO uint16_t TSCVL; + struct { + __IO uint8_t TSCVLL; + __IO uint8_t TSCVLH; + }; + }; + union { + __IO uint16_t TSCVH; + struct { + __IO uint8_t TSCVHL; + __IO uint8_t TSCVHH; + }; + }; + }; + }; + union { + __IO uint32_t TOCC; + stc_canfd_tocc_field_t TOCC_f; + struct { + union { + __IO uint16_t TOCCL; + struct { + __IO uint8_t TOCCLL; + __IO uint8_t TOCCLH; + }; + }; + union { + __IO uint16_t TOCCH; + struct { + __IO uint8_t TOCCHL; + __IO uint8_t TOCCHH; + }; + }; + }; + }; + union { + __IO uint32_t TOCV; + stc_canfd_tocv_field_t TOCV_f; + struct { + union { + __IO uint16_t TOCVL; + struct { + __IO uint8_t TOCVLL; + __IO uint8_t TOCVLH; + }; + }; + union { + __IO uint16_t TOCVH; + struct { + __IO uint8_t TOCVHL; + __IO uint8_t TOCVHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[16]; + union { + __IO uint32_t ECR; + stc_canfd_ecr_field_t ECR_f; + struct { + union { + __IO uint16_t ECRL; + struct { + __IO uint8_t ECRLL; + __IO uint8_t ECRLH; + }; + }; + union { + __IO uint16_t ECRH; + struct { + __IO uint8_t ECRHL; + __IO uint8_t ECRHH; + }; + }; + }; + }; + union { + __IO uint32_t PSR; + stc_canfd_psr_field_t PSR_f; + struct { + union { + __IO uint16_t PSRL; + struct { + __IO uint8_t PSRLL; + __IO uint8_t PSRLH; + }; + }; + union { + __IO uint16_t PSRH; + struct { + __IO uint8_t PSRHL; + __IO uint8_t PSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[8]; + union { + __IO uint32_t IR; + stc_canfd_ir_field_t IR_f; + struct { + union { + __IO uint16_t IRL; + struct { + __IO uint8_t IRLL; + __IO uint8_t IRLH; + }; + }; + union { + __IO uint16_t IRH; + struct { + __IO uint8_t IRHL; + __IO uint8_t IRHH; + }; + }; + }; + }; + union { + __IO uint32_t IE; + stc_canfd_ie_field_t IE_f; + struct { + union { + __IO uint16_t IEL; + struct { + __IO uint8_t IELL; + __IO uint8_t IELH; + }; + }; + union { + __IO uint16_t IEH; + struct { + __IO uint8_t IEHL; + __IO uint8_t IEHH; + }; + }; + }; + }; + union { + __IO uint32_t ILS; + stc_canfd_ils_field_t ILS_f; + struct { + union { + __IO uint16_t ILSL; + struct { + __IO uint8_t ILSLL; + __IO uint8_t ILSLH; + }; + }; + union { + __IO uint16_t ILSH; + struct { + __IO uint8_t ILSHL; + __IO uint8_t ILSHH; + }; + }; + }; + }; + union { + __IO uint32_t ILE; + stc_canfd_ile_field_t ILE_f; + struct { + union { + __IO uint16_t ILEL; + struct { + __IO uint8_t ILELL; + __IO uint8_t ILELH; + }; + }; + union { + __IO uint16_t ILEH; + struct { + __IO uint8_t ILEHL; + __IO uint8_t ILEHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[32]; + union { + __IO uint32_t GFC; + stc_canfd_gfc_field_t GFC_f; + struct { + union { + __IO uint16_t GFCL; + struct { + __IO uint8_t GFCLL; + __IO uint8_t GFCLH; + }; + }; + union { + __IO uint16_t GFCH; + struct { + __IO uint8_t GFCHL; + __IO uint8_t GFCHH; + }; + }; + }; + }; + union { + __IO uint32_t SIDFC; + stc_canfd_sidfc_field_t SIDFC_f; + struct { + union { + __IO uint16_t SIDFCL; + struct { + __IO uint8_t SIDFCLL; + __IO uint8_t SIDFCLH; + }; + }; + union { + __IO uint16_t SIDFCH; + struct { + __IO uint8_t SIDFCHL; + __IO uint8_t SIDFCHH; + }; + }; + }; + }; + union { + __IO uint32_t XIDFC; + stc_canfd_xidfc_field_t XIDFC_f; + struct { + union { + __IO uint16_t XIDFCL; + struct { + __IO uint8_t XIDFCLL; + __IO uint8_t XIDFCLH; + }; + }; + union { + __IO uint16_t XIDFCH; + struct { + __IO uint8_t XIDFCHL; + __IO uint8_t XIDFCHH; + }; + }; + }; + }; + __IO uint8_t RESERVED4[4]; + union { + __IO uint32_t XIDAM; + stc_canfd_xidam_field_t XIDAM_f; + struct { + union { + __IO uint16_t XIDAML; + struct { + __IO uint8_t XIDAMLL; + __IO uint8_t XIDAMLH; + }; + }; + union { + __IO uint16_t XIDAMH; + struct { + __IO uint8_t XIDAMHL; + __IO uint8_t XIDAMHH; + }; + }; + }; + }; + union { + __IO uint32_t HPMS; + stc_canfd_hpms_field_t HPMS_f; + struct { + union { + __IO uint16_t HPMSL; + struct { + __IO uint8_t HPMSLL; + __IO uint8_t HPMSLH; + }; + }; + union { + __IO uint16_t HPMSH; + struct { + __IO uint8_t HPMSHL; + __IO uint8_t HPMSHH; + }; + }; + }; + }; + union { + __IO uint32_t NDAT1; + stc_canfd_ndat1_field_t NDAT1_f; + struct { + union { + __IO uint16_t NDAT1L; + struct { + __IO uint8_t NDAT1LL; + __IO uint8_t NDAT1LH; + }; + }; + union { + __IO uint16_t NDAT1H; + struct { + __IO uint8_t NDAT1HL; + __IO uint8_t NDAT1HH; + }; + }; + }; + }; + union { + __IO uint32_t NDAT2; + stc_canfd_ndat2_field_t NDAT2_f; + struct { + union { + __IO uint16_t NDAT2L; + struct { + __IO uint8_t NDAT2LL; + __IO uint8_t NDAT2LH; + }; + }; + union { + __IO uint16_t NDAT2H; + struct { + __IO uint8_t NDAT2HL; + __IO uint8_t NDAT2HH; + }; + }; + }; + }; + union { + __IO uint32_t RXF0C; + stc_canfd_rxf0c_field_t RXF0C_f; + struct { + union { + __IO uint16_t RXF0CL; + struct { + __IO uint8_t RXF0CLL; + __IO uint8_t RXF0CLH; + }; + }; + union { + __IO uint16_t RXF0CH; + struct { + __IO uint8_t RXF0CHL; + __IO uint8_t RXF0CHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF0S; + stc_canfd_rxf0s_field_t RXF0S_f; + struct { + union { + __IO uint16_t RXF0SL; + struct { + __IO uint8_t RXF0SLL; + __IO uint8_t RXF0SLH; + }; + }; + union { + __IO uint16_t RXF0SH; + struct { + __IO uint8_t RXF0SHL; + __IO uint8_t RXF0SHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF0A; + stc_canfd_rxf0a_field_t RXF0A_f; + struct { + union { + __IO uint16_t RXF0AL; + struct { + __IO uint8_t RXF0ALL; + __IO uint8_t RXF0ALH; + }; + }; + union { + __IO uint16_t RXF0AH; + struct { + __IO uint8_t RXF0AHL; + __IO uint8_t RXF0AHH; + }; + }; + }; + }; + union { + __IO uint32_t RXBC; + stc_canfd_rxbc_field_t RXBC_f; + struct { + union { + __IO uint16_t RXBCL; + struct { + __IO uint8_t RXBCLL; + __IO uint8_t RXBCLH; + }; + }; + union { + __IO uint16_t RXBCH; + struct { + __IO uint8_t RXBCHL; + __IO uint8_t RXBCHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF1C; + stc_canfd_rxf1c_field_t RXF1C_f; + struct { + union { + __IO uint16_t RXF1CL; + struct { + __IO uint8_t RXF1CLL; + __IO uint8_t RXF1CLH; + }; + }; + union { + __IO uint16_t RXF1CH; + struct { + __IO uint8_t RXF1CHL; + __IO uint8_t RXF1CHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF1S; + stc_canfd_rxf1s_field_t RXF1S_f; + struct { + union { + __IO uint16_t RXF1SL; + struct { + __IO uint8_t RXF1SLL; + __IO uint8_t RXF1SLH; + }; + }; + union { + __IO uint16_t RXF1SH; + struct { + __IO uint8_t RXF1SHL; + __IO uint8_t RXF1SHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF1A; + stc_canfd_rxf1a_field_t RXF1A_f; + struct { + union { + __IO uint16_t RXF1AL; + struct { + __IO uint8_t RXF1ALL; + __IO uint8_t RXF1ALH; + }; + }; + union { + __IO uint16_t RXF1AH; + struct { + __IO uint8_t RXF1AHL; + __IO uint8_t RXF1AHH; + }; + }; + }; + }; + union { + __IO uint32_t RXESC; + stc_canfd_rxesc_field_t RXESC_f; + struct { + union { + __IO uint16_t RXESCL; + struct { + __IO uint8_t RXESCLL; + __IO uint8_t RXESCLH; + }; + }; + union { + __IO uint16_t RXESCH; + struct { + __IO uint8_t RXESCHL; + __IO uint8_t RXESCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBC; + stc_canfd_txbc_field_t TXBC_f; + struct { + union { + __IO uint16_t TXBCL; + struct { + __IO uint8_t TXBCLL; + __IO uint8_t TXBCLH; + }; + }; + union { + __IO uint16_t TXBCH; + struct { + __IO uint8_t TXBCHL; + __IO uint8_t TXBCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFQS; + stc_canfd_txfqs_field_t TXFQS_f; + struct { + union { + __IO uint16_t TXFQSL; + struct { + __IO uint8_t TXFQSLL; + __IO uint8_t TXFQSLH; + }; + }; + union { + __IO uint16_t TXFQSH; + struct { + __IO uint8_t TXFQSHL; + __IO uint8_t TXFQSHH; + }; + }; + }; + }; + union { + __IO uint32_t TXESC; + stc_canfd_txesc_field_t TXESC_f; + struct { + union { + __IO uint16_t TXESCL; + struct { + __IO uint8_t TXESCLL; + __IO uint8_t TXESCLH; + }; + }; + union { + __IO uint16_t TXESCH; + struct { + __IO uint8_t TXESCHL; + __IO uint8_t TXESCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBRP; + stc_canfd_txbrp_field_t TXBRP_f; + struct { + union { + __IO uint16_t TXBRPL; + struct { + __IO uint8_t TXBRPLL; + __IO uint8_t TXBRPLH; + }; + }; + union { + __IO uint16_t TXBRPH; + struct { + __IO uint8_t TXBRPHL; + __IO uint8_t TXBRPHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBAR; + stc_canfd_txbar_field_t TXBAR_f; + struct { + union { + __IO uint16_t TXBARL; + struct { + __IO uint8_t TXBARLL; + __IO uint8_t TXBARLH; + }; + }; + union { + __IO uint16_t TXBARH; + struct { + __IO uint8_t TXBARHL; + __IO uint8_t TXBARHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBCR; + stc_canfd_txbcr_field_t TXBCR_f; + struct { + union { + __IO uint16_t TXBCRL; + struct { + __IO uint8_t TXBCRLL; + __IO uint8_t TXBCRLH; + }; + }; + union { + __IO uint16_t TXBCRH; + struct { + __IO uint8_t TXBCRHL; + __IO uint8_t TXBCRHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBTO; + stc_canfd_txbto_field_t TXBTO_f; + struct { + union { + __IO uint16_t TXBTOL; + struct { + __IO uint8_t TXBTOLL; + __IO uint8_t TXBTOLH; + }; + }; + union { + __IO uint16_t TXBTOH; + struct { + __IO uint8_t TXBTOHL; + __IO uint8_t TXBTOHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBCF; + stc_canfd_txbcf_field_t TXBCF_f; + struct { + union { + __IO uint16_t TXBCFL; + struct { + __IO uint8_t TXBCFLL; + __IO uint8_t TXBCFLH; + }; + }; + union { + __IO uint16_t TXBCFH; + struct { + __IO uint8_t TXBCFHL; + __IO uint8_t TXBCFHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBTIE; + stc_canfd_txbtie_field_t TXBTIE_f; + struct { + union { + __IO uint16_t TXBTIEL; + struct { + __IO uint8_t TXBTIELL; + __IO uint8_t TXBTIELH; + }; + }; + union { + __IO uint16_t TXBTIEH; + struct { + __IO uint8_t TXBTIEHL; + __IO uint8_t TXBTIEHH; + }; + }; + }; + }; + union { + __IO uint32_t TXBCIE; + stc_canfd_txbcie_field_t TXBCIE_f; + struct { + union { + __IO uint16_t TXBCIEL; + struct { + __IO uint8_t TXBCIELL; + __IO uint8_t TXBCIELH; + }; + }; + union { + __IO uint16_t TXBCIEH; + struct { + __IO uint8_t TXBCIEHL; + __IO uint8_t TXBCIEHH; + }; + }; + }; + }; + __IO uint8_t RESERVED5[8]; + union { + __IO uint32_t TXEFC; + stc_canfd_txefc_field_t TXEFC_f; + struct { + union { + __IO uint16_t TXEFCL; + struct { + __IO uint8_t TXEFCLL; + __IO uint8_t TXEFCLH; + }; + }; + union { + __IO uint16_t TXEFCH; + struct { + __IO uint8_t TXEFCHL; + __IO uint8_t TXEFCHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFS; + stc_canfd_txfs_field_t TXFS_f; + struct { + union { + __IO uint16_t TXFSL; + struct { + __IO uint8_t TXFSLL; + __IO uint8_t TXFSLH; + }; + }; + union { + __IO uint16_t TXFSH; + struct { + __IO uint8_t TXFSHL; + __IO uint8_t TXFSHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFA; + stc_canfd_txfa_field_t TXFA_f; + struct { + union { + __IO uint16_t TXFAL; + struct { + __IO uint8_t TXFALL; + __IO uint8_t TXFALH; + }; + }; + union { + __IO uint16_t TXFAH; + struct { + __IO uint8_t TXFAHL; + __IO uint8_t TXFAHH; + }; + }; + }; + }; + __IO uint8_t RESERVED6[260]; + union { + __IO uint8_t FDECR; + stc_canfd_fdecr_field_t FDECR_f; + }; + union { + __IO uint8_t FDESR; + stc_canfd_fdesr_field_t FDESR_f; + }; + union { + __IO uint16_t FDSEAR; + stc_canfd_fdsear_field_t FDSEAR_f; + struct { + __IO uint8_t FDSEARL; + __IO uint8_t FDSEARH; + }; + }; + __IO uint8_t RESERVED7[1]; + union { + __IO uint8_t FDESCR; + stc_canfd_fdescr_field_t FDESCR_f; + }; + union { + __IO uint16_t FDDEAR; + stc_canfd_fddear_field_t FDDEAR_f; + struct { + __IO uint8_t FDDEARL; + __IO uint8_t FDDEARH; + }; + }; + __IO uint8_t RESERVED8[8]; + union { + __IO uint16_t TSCNTR; + stc_canfd_tscntr_field_t TSCNTR_f; + struct { + __IO uint8_t TSCNTRL; + __IO uint8_t TSCNTRH; + }; + }; + union { + __IO uint16_t TSMDR; + stc_canfd_tsmdr_field_t TSMDR_f; + struct { + __IO uint8_t TSMDRL; + __IO uint8_t TSMDRH; + }; + }; + union { + __IO uint32_t TSDIVR; + stc_canfd_tsdivr_field_t TSDIVR_f; + struct { + union { + __IO uint16_t TSDIVRL; + struct { + __IO uint8_t TSDIVRLL; + __IO uint8_t TSDIVRLH; + }; + }; + union { + __IO uint16_t TSDIVRH; + struct { + __IO uint8_t TSDIVRHL; + __IO uint8_t TSDIVRHH; + }; + }; + }; + }; + union { + __IO uint16_t TSCDTR; + stc_canfd_tscdtr_field_t TSCDTR_f; + struct { + __IO uint8_t TSCDTRL; + __IO uint8_t TSCDTRH; + }; + }; + union { + __IO uint16_t TSCPCLR; + stc_canfd_tscpclr_field_t TSCPCLR_f; + struct { + __IO uint8_t TSCPCLRL; + __IO uint8_t TSCPCLRH; + }; + }; +} FM_CANFD_TypeDef, FM4_CANFD_TypeDef; + +/******************************************************************************* +* CANPRES_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t CANPRE; + stc_canpres_canpre_field_t CANPRE_f; + }; +} FM_CANPRES_TypeDef, FM4_CANPRES_TypeDef; + +/******************************************************************************* +* CLK_GATING_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t CKEN0; + stc_clk_gating_cken0_field_t CKEN0_f; + struct { + union { + __IO uint16_t CKEN0L; + struct { + __IO uint8_t CKEN0LL; + __IO uint8_t CKEN0LH; + }; + }; + union { + __IO uint16_t CKEN0H; + struct { + __IO uint8_t CKEN0HL; + __IO uint8_t CKEN0HH; + }; + }; + }; + }; + union { + __IO uint32_t MRST0; + stc_clk_gating_mrst0_field_t MRST0_f; + struct { + union { + __IO uint16_t MRST0L; + struct { + __IO uint8_t MRST0LL; + __IO uint8_t MRST0LH; + }; + }; + union { + __IO uint16_t MRST0H; + struct { + __IO uint8_t MRST0HL; + __IO uint8_t MRST0HH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[8]; + union { + __IO uint32_t CKEN1; + stc_clk_gating_cken1_field_t CKEN1_f; + struct { + union { + __IO uint16_t CKEN1L; + struct { + __IO uint8_t CKEN1LL; + __IO uint8_t CKEN1LH; + }; + }; + union { + __IO uint16_t CKEN1H; + struct { + __IO uint8_t CKEN1HL; + __IO uint8_t CKEN1HH; + }; + }; + }; + }; + union { + __IO uint32_t MRST1; + stc_clk_gating_mrst1_field_t MRST1_f; + struct { + union { + __IO uint16_t MRST1L; + struct { + __IO uint8_t MRST1LL; + __IO uint8_t MRST1LH; + }; + }; + union { + __IO uint16_t MRST1H; + struct { + __IO uint8_t MRST1HL; + __IO uint8_t MRST1HH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[8]; + union { + __IO uint32_t CKEN2; + stc_clk_gating_cken2_field_t CKEN2_f; + struct { + union { + __IO uint16_t CKEN2L; + struct { + __IO uint8_t CKEN2LL; + __IO uint8_t CKEN2LH; + }; + }; + union { + __IO uint16_t CKEN2H; + struct { + __IO uint8_t CKEN2HL; + __IO uint8_t CKEN2HH; + }; + }; + }; + }; + union { + __IO uint32_t MRST2; + stc_clk_gating_mrst2_field_t MRST2_f; + struct { + union { + __IO uint16_t MRST2L; + struct { + __IO uint8_t MRST2LL; + __IO uint8_t MRST2LH; + }; + }; + union { + __IO uint16_t MRST2H; + struct { + __IO uint8_t MRST2HL; + __IO uint8_t MRST2HH; + }; + }; + }; + }; +} FM_CLK_GATING_TypeDef, FM4_CLK_GATING_TypeDef; + +/******************************************************************************* +* CRC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t CRCCR; + stc_crc_crccr_field_t CRCCR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint32_t CRCINIT; + stc_crc_crcinit_field_t CRCINIT_f; + struct { + union { + __IO uint16_t CRCINITL; + struct { + __IO uint8_t CRCINITLL; + __IO uint8_t CRCINITLH; + }; + }; + union { + __IO uint16_t CRCINITH; + struct { + __IO uint8_t CRCINITHL; + __IO uint8_t CRCINITHH; + }; + }; + }; + }; + union { + __IO uint32_t CRCIN; + stc_crc_crcin_field_t CRCIN_f; + struct { + union { + __IO uint16_t CRCINL; + struct { + __IO uint8_t CRCINLL; + __IO uint8_t CRCINLH; + }; + }; + union { + __IO uint16_t CRCINH; + struct { + __IO uint8_t CRCINHL; + __IO uint8_t CRCINHH; + }; + }; + }; + }; + union { + __IO uint32_t CRCR; + stc_crc_crcr_field_t CRCR_f; + struct { + union { + __IO uint16_t CRCRL; + struct { + __IO uint8_t CRCRLL; + __IO uint8_t CRCRLH; + }; + }; + union { + __IO uint16_t CRCRH; + struct { + __IO uint8_t CRCRHL; + __IO uint8_t CRCRHH; + }; + }; + }; + }; +} FM_CRC_TypeDef, FM4_CRC_TypeDef; + +/******************************************************************************* +* CRG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t SCM_CTL; + stc_crg_scm_ctl_field_t SCM_CTL_f; + struct { + union { + __IO uint16_t SCM_CTLL; + struct { + __IO uint8_t SCM_CTLLL; + __IO uint8_t SCM_CTLLH; + }; + }; + union { + __IO uint16_t SCM_CTLH; + struct { + __IO uint8_t SCM_CTLHL; + __IO uint8_t SCM_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t SCM_STR; + stc_crg_scm_str_field_t SCM_STR_f; + struct { + union { + __IO uint16_t SCM_STRL; + struct { + __IO uint8_t SCM_STRLL; + __IO uint8_t SCM_STRLH; + }; + }; + union { + __IO uint16_t SCM_STRH; + struct { + __IO uint8_t SCM_STRHL; + __IO uint8_t SCM_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t STB_CTL; + stc_crg_stb_ctl_field_t STB_CTL_f; + struct { + union { + __IO uint16_t STB_CTLL; + struct { + __IO uint8_t STB_CTLLL; + __IO uint8_t STB_CTLLH; + }; + }; + union { + __IO uint16_t STB_CTLH; + struct { + __IO uint8_t STB_CTLHL; + __IO uint8_t STB_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t RST_STR; + stc_crg_rst_str_field_t RST_STR_f; + struct { + union { + __IO uint16_t RST_STRL; + struct { + __IO uint8_t RST_STRLL; + __IO uint8_t RST_STRLH; + }; + }; + union { + __IO uint16_t RST_STRH; + struct { + __IO uint8_t RST_STRHL; + __IO uint8_t RST_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t BSC_PSR; + stc_crg_bsc_psr_field_t BSC_PSR_f; + struct { + union { + __IO uint16_t BSC_PSRL; + struct { + __IO uint8_t BSC_PSRLL; + __IO uint8_t BSC_PSRLH; + }; + }; + union { + __IO uint16_t BSC_PSRH; + struct { + __IO uint8_t BSC_PSRHL; + __IO uint8_t BSC_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t APBC0_PSR; + stc_crg_apbc0_psr_field_t APBC0_PSR_f; + struct { + union { + __IO uint16_t APBC0_PSRL; + struct { + __IO uint8_t APBC0_PSRLL; + __IO uint8_t APBC0_PSRLH; + }; + }; + union { + __IO uint16_t APBC0_PSRH; + struct { + __IO uint8_t APBC0_PSRHL; + __IO uint8_t APBC0_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t APBC1_PSR; + stc_crg_apbc1_psr_field_t APBC1_PSR_f; + struct { + union { + __IO uint16_t APBC1_PSRL; + struct { + __IO uint8_t APBC1_PSRLL; + __IO uint8_t APBC1_PSRLH; + }; + }; + union { + __IO uint16_t APBC1_PSRH; + struct { + __IO uint8_t APBC1_PSRHL; + __IO uint8_t APBC1_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t APBC2_PSR; + stc_crg_apbc2_psr_field_t APBC2_PSR_f; + struct { + union { + __IO uint16_t APBC2_PSRL; + struct { + __IO uint8_t APBC2_PSRLL; + __IO uint8_t APBC2_PSRLH; + }; + }; + union { + __IO uint16_t APBC2_PSRH; + struct { + __IO uint8_t APBC2_PSRHL; + __IO uint8_t APBC2_PSRHH; + }; + }; + }; + }; + union { + __IO uint32_t SWC_PSR; + stc_crg_swc_psr_field_t SWC_PSR_f; + struct { + union { + __IO uint16_t SWC_PSRL; + struct { + __IO uint8_t SWC_PSRLL; + __IO uint8_t SWC_PSRLH; + }; + }; + union { + __IO uint16_t SWC_PSRH; + struct { + __IO uint8_t SWC_PSRHL; + __IO uint8_t SWC_PSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t TTC_PSR; + stc_crg_ttc_psr_field_t TTC_PSR_f; + struct { + union { + __IO uint16_t TTC_PSRL; + struct { + __IO uint8_t TTC_PSRLL; + __IO uint8_t TTC_PSRLH; + }; + }; + union { + __IO uint16_t TTC_PSRH; + struct { + __IO uint8_t TTC_PSRHL; + __IO uint8_t TTC_PSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[4]; + union { + __IO uint32_t CSW_TMR; + stc_crg_csw_tmr_field_t CSW_TMR_f; + struct { + union { + __IO uint16_t CSW_TMRL; + struct { + __IO uint8_t CSW_TMRLL; + __IO uint8_t CSW_TMRLH; + }; + }; + union { + __IO uint16_t CSW_TMRH; + struct { + __IO uint8_t CSW_TMRHL; + __IO uint8_t CSW_TMRHH; + }; + }; + }; + }; + union { + __IO uint32_t PSW_TMR; + stc_crg_psw_tmr_field_t PSW_TMR_f; + struct { + union { + __IO uint16_t PSW_TMRL; + struct { + __IO uint8_t PSW_TMRLL; + __IO uint8_t PSW_TMRLH; + }; + }; + union { + __IO uint16_t PSW_TMRH; + struct { + __IO uint8_t PSW_TMRHL; + __IO uint8_t PSW_TMRHH; + }; + }; + }; + }; + union { + __IO uint32_t PLL_CTL1; + stc_crg_pll_ctl1_field_t PLL_CTL1_f; + struct { + union { + __IO uint16_t PLL_CTL1L; + struct { + __IO uint8_t PLL_CTL1LL; + __IO uint8_t PLL_CTL1LH; + }; + }; + union { + __IO uint16_t PLL_CTL1H; + struct { + __IO uint8_t PLL_CTL1HL; + __IO uint8_t PLL_CTL1HH; + }; + }; + }; + }; + union { + __IO uint32_t PLL_CTL2; + stc_crg_pll_ctl2_field_t PLL_CTL2_f; + struct { + union { + __IO uint16_t PLL_CTL2L; + struct { + __IO uint8_t PLL_CTL2LL; + __IO uint8_t PLL_CTL2LH; + }; + }; + union { + __IO uint16_t PLL_CTL2H; + struct { + __IO uint8_t PLL_CTL2HL; + __IO uint8_t PLL_CTL2HH; + }; + }; + }; + }; + union { + __IO uint32_t CSV_CTL; + stc_crg_csv_ctl_field_t CSV_CTL_f; + struct { + union { + __IO uint16_t CSV_CTLL; + struct { + __IO uint8_t CSV_CTLLL; + __IO uint8_t CSV_CTLLH; + }; + }; + union { + __IO uint16_t CSV_CTLH; + struct { + __IO uint8_t CSV_CTLHL; + __IO uint8_t CSV_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t CSV_STR; + stc_crg_csv_str_field_t CSV_STR_f; + struct { + union { + __IO uint16_t CSV_STRL; + struct { + __IO uint8_t CSV_STRLL; + __IO uint8_t CSV_STRLH; + }; + }; + union { + __IO uint16_t CSV_STRH; + struct { + __IO uint8_t CSV_STRHL; + __IO uint8_t CSV_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t FCSWH_CTL; + stc_crg_fcswh_ctl_field_t FCSWH_CTL_f; + struct { + union { + __IO uint16_t FCSWH_CTLL; + struct { + __IO uint8_t FCSWH_CTLLL; + __IO uint8_t FCSWH_CTLLH; + }; + }; + union { + __IO uint16_t FCSWH_CTLH; + struct { + __IO uint8_t FCSWH_CTLHL; + __IO uint8_t FCSWH_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t FCSWL_CTL; + stc_crg_fcswl_ctl_field_t FCSWL_CTL_f; + struct { + union { + __IO uint16_t FCSWL_CTLL; + struct { + __IO uint8_t FCSWL_CTLLL; + __IO uint8_t FCSWL_CTLLH; + }; + }; + union { + __IO uint16_t FCSWL_CTLH; + struct { + __IO uint8_t FCSWL_CTLHL; + __IO uint8_t FCSWL_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t FCSWD_CTL; + stc_crg_fcswd_ctl_field_t FCSWD_CTL_f; + struct { + union { + __IO uint16_t FCSWD_CTLL; + struct { + __IO uint8_t FCSWD_CTLLL; + __IO uint8_t FCSWD_CTLLH; + }; + }; + union { + __IO uint16_t FCSWD_CTLH; + struct { + __IO uint8_t FCSWD_CTLHL; + __IO uint8_t FCSWD_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t DBWDT_CTL; + stc_crg_dbwdt_ctl_field_t DBWDT_CTL_f; + struct { + union { + __IO uint16_t DBWDT_CTLL; + struct { + __IO uint8_t DBWDT_CTLLL; + __IO uint8_t DBWDT_CTLLH; + }; + }; + union { + __IO uint16_t DBWDT_CTLH; + struct { + __IO uint8_t DBWDT_CTLHL; + __IO uint8_t DBWDT_CTLHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[8]; + union { + __IO uint32_t INT_ENR; + stc_crg_int_enr_field_t INT_ENR_f; + struct { + union { + __IO uint16_t INT_ENRL; + struct { + __IO uint8_t INT_ENRLL; + __IO uint8_t INT_ENRLH; + }; + }; + union { + __IO uint16_t INT_ENRH; + struct { + __IO uint8_t INT_ENRHL; + __IO uint8_t INT_ENRHH; + }; + }; + }; + }; + union { + __IO uint32_t INT_STR; + stc_crg_int_str_field_t INT_STR_f; + struct { + union { + __IO uint16_t INT_STRL; + struct { + __IO uint8_t INT_STRLL; + __IO uint8_t INT_STRLH; + }; + }; + union { + __IO uint16_t INT_STRH; + struct { + __IO uint8_t INT_STRHL; + __IO uint8_t INT_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t INT_CLR; + stc_crg_int_clr_field_t INT_CLR_f; + struct { + union { + __IO uint16_t INT_CLRL; + struct { + __IO uint8_t INT_CLRLL; + __IO uint8_t INT_CLRLH; + }; + }; + union { + __IO uint16_t INT_CLRH; + struct { + __IO uint8_t INT_CLRHL; + __IO uint8_t INT_CLRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[8]; + union { + __IO uint32_t PLLCG_CTL; + stc_crg_pllcg_ctl_field_t PLLCG_CTL_f; + struct { + union { + __IO uint16_t PLLCG_CTLL; + struct { + __IO uint8_t PLLCG_CTLLL; + __IO uint8_t PLLCG_CTLLH; + }; + }; + union { + __IO uint16_t PLLCG_CTLH; + struct { + __IO uint8_t PLLCG_CTLHL; + __IO uint8_t PLLCG_CTLHH; + }; + }; + }; + }; +} FM_CRG_TypeDef, FM4_CRG_TypeDef; + +/******************************************************************************* +* CRTRIM_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t MCR_PSR; + stc_crtrim_mcr_psr_field_t MCR_PSR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint32_t MCR_FTRM; + stc_crtrim_mcr_ftrm_field_t MCR_FTRM_f; + struct { + union { + __IO uint16_t MCR_FTRML; + struct { + __IO uint8_t MCR_FTRMLL; + __IO uint8_t MCR_FTRMLH; + }; + }; + union { + __IO uint16_t MCR_FTRMH; + struct { + __IO uint8_t MCR_FTRMHL; + __IO uint8_t MCR_FTRMHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR_TTRM; + stc_crtrim_mcr_ttrm_field_t MCR_TTRM_f; + struct { + union { + __IO uint16_t MCR_TTRML; + struct { + __IO uint8_t MCR_TTRMLL; + __IO uint8_t MCR_TTRMLH; + }; + }; + union { + __IO uint16_t MCR_TTRMH; + struct { + __IO uint8_t MCR_TTRMHL; + __IO uint8_t MCR_TTRMHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR_RLR; + stc_crtrim_mcr_rlr_field_t MCR_RLR_f; + struct { + union { + __IO uint16_t MCR_RLRL; + struct { + __IO uint8_t MCR_RLRLL; + __IO uint8_t MCR_RLRLH; + }; + }; + union { + __IO uint16_t MCR_RLRH; + struct { + __IO uint8_t MCR_RLRHL; + __IO uint8_t MCR_RLRHH; + }; + }; + }; + }; +} FM_CRTRIM_TypeDef, FM4_CRTRIM_TypeDef; + +/******************************************************************************* +* DAC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t DACR; + stc_dac_dacr_field_t DACR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint16_t DADR; + stc_dac_dadr_field_t DADR_f; + struct { + __IO uint8_t DADRL; + __IO uint8_t DADRH; + }; + }; +} FM_DAC_TypeDef, FM4_DAC_TypeDef; + +/******************************************************************************* +* DMAC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DMACR; + stc_dmac_dmacr_field_t DMACR_f; + struct { + union { + __IO uint16_t DMACRL; + struct { + __IO uint8_t DMACRLL; + __IO uint8_t DMACRLH; + }; + }; + union { + __IO uint16_t DMACRH; + struct { + __IO uint8_t DMACRHL; + __IO uint8_t DMACRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[12]; + union { + __IO uint32_t DMACA0; + stc_dmac_dmaca0_field_t DMACA0_f; + struct { + union { + __IO uint16_t DMACA0L; + struct { + __IO uint8_t DMACA0LL; + __IO uint8_t DMACA0LH; + }; + }; + union { + __IO uint16_t DMACA0H; + struct { + __IO uint8_t DMACA0HL; + __IO uint8_t DMACA0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB0; + stc_dmac_dmacb0_field_t DMACB0_f; + struct { + union { + __IO uint16_t DMACB0L; + struct { + __IO uint8_t DMACB0LL; + __IO uint8_t DMACB0LH; + }; + }; + union { + __IO uint16_t DMACB0H; + struct { + __IO uint8_t DMACB0HL; + __IO uint8_t DMACB0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA0; + struct { + union { + __IO uint16_t DMACSA0L; + struct { + __IO uint8_t DMACSA0LL; + __IO uint8_t DMACSA0LH; + }; + }; + union { + __IO uint16_t DMACSA0H; + struct { + __IO uint8_t DMACSA0HL; + __IO uint8_t DMACSA0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA0; + struct { + union { + __IO uint16_t DMACDA0L; + struct { + __IO uint8_t DMACDA0LL; + __IO uint8_t DMACDA0LH; + }; + }; + union { + __IO uint16_t DMACDA0H; + struct { + __IO uint8_t DMACDA0HL; + __IO uint8_t DMACDA0HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA1; + stc_dmac_dmaca1_field_t DMACA1_f; + struct { + union { + __IO uint16_t DMACA1L; + struct { + __IO uint8_t DMACA1LL; + __IO uint8_t DMACA1LH; + }; + }; + union { + __IO uint16_t DMACA1H; + struct { + __IO uint8_t DMACA1HL; + __IO uint8_t DMACA1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB1; + stc_dmac_dmacb1_field_t DMACB1_f; + struct { + union { + __IO uint16_t DMACB1L; + struct { + __IO uint8_t DMACB1LL; + __IO uint8_t DMACB1LH; + }; + }; + union { + __IO uint16_t DMACB1H; + struct { + __IO uint8_t DMACB1HL; + __IO uint8_t DMACB1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA1; + struct { + union { + __IO uint16_t DMACSA1L; + struct { + __IO uint8_t DMACSA1LL; + __IO uint8_t DMACSA1LH; + }; + }; + union { + __IO uint16_t DMACSA1H; + struct { + __IO uint8_t DMACSA1HL; + __IO uint8_t DMACSA1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA1; + struct { + union { + __IO uint16_t DMACDA1L; + struct { + __IO uint8_t DMACDA1LL; + __IO uint8_t DMACDA1LH; + }; + }; + union { + __IO uint16_t DMACDA1H; + struct { + __IO uint8_t DMACDA1HL; + __IO uint8_t DMACDA1HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA2; + stc_dmac_dmaca2_field_t DMACA2_f; + struct { + union { + __IO uint16_t DMACA2L; + struct { + __IO uint8_t DMACA2LL; + __IO uint8_t DMACA2LH; + }; + }; + union { + __IO uint16_t DMACA2H; + struct { + __IO uint8_t DMACA2HL; + __IO uint8_t DMACA2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB2; + stc_dmac_dmacb2_field_t DMACB2_f; + struct { + union { + __IO uint16_t DMACB2L; + struct { + __IO uint8_t DMACB2LL; + __IO uint8_t DMACB2LH; + }; + }; + union { + __IO uint16_t DMACB2H; + struct { + __IO uint8_t DMACB2HL; + __IO uint8_t DMACB2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA2; + struct { + union { + __IO uint16_t DMACSA2L; + struct { + __IO uint8_t DMACSA2LL; + __IO uint8_t DMACSA2LH; + }; + }; + union { + __IO uint16_t DMACSA2H; + struct { + __IO uint8_t DMACSA2HL; + __IO uint8_t DMACSA2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA2; + struct { + union { + __IO uint16_t DMACDA2L; + struct { + __IO uint8_t DMACDA2LL; + __IO uint8_t DMACDA2LH; + }; + }; + union { + __IO uint16_t DMACDA2H; + struct { + __IO uint8_t DMACDA2HL; + __IO uint8_t DMACDA2HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA3; + stc_dmac_dmaca3_field_t DMACA3_f; + struct { + union { + __IO uint16_t DMACA3L; + struct { + __IO uint8_t DMACA3LL; + __IO uint8_t DMACA3LH; + }; + }; + union { + __IO uint16_t DMACA3H; + struct { + __IO uint8_t DMACA3HL; + __IO uint8_t DMACA3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB3; + stc_dmac_dmacb3_field_t DMACB3_f; + struct { + union { + __IO uint16_t DMACB3L; + struct { + __IO uint8_t DMACB3LL; + __IO uint8_t DMACB3LH; + }; + }; + union { + __IO uint16_t DMACB3H; + struct { + __IO uint8_t DMACB3HL; + __IO uint8_t DMACB3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA3; + struct { + union { + __IO uint16_t DMACSA3L; + struct { + __IO uint8_t DMACSA3LL; + __IO uint8_t DMACSA3LH; + }; + }; + union { + __IO uint16_t DMACSA3H; + struct { + __IO uint8_t DMACSA3HL; + __IO uint8_t DMACSA3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA3; + struct { + union { + __IO uint16_t DMACDA3L; + struct { + __IO uint8_t DMACDA3LL; + __IO uint8_t DMACDA3LH; + }; + }; + union { + __IO uint16_t DMACDA3H; + struct { + __IO uint8_t DMACDA3HL; + __IO uint8_t DMACDA3HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA4; + stc_dmac_dmaca4_field_t DMACA4_f; + struct { + union { + __IO uint16_t DMACA4L; + struct { + __IO uint8_t DMACA4LL; + __IO uint8_t DMACA4LH; + }; + }; + union { + __IO uint16_t DMACA4H; + struct { + __IO uint8_t DMACA4HL; + __IO uint8_t DMACA4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB4; + stc_dmac_dmacb4_field_t DMACB4_f; + struct { + union { + __IO uint16_t DMACB4L; + struct { + __IO uint8_t DMACB4LL; + __IO uint8_t DMACB4LH; + }; + }; + union { + __IO uint16_t DMACB4H; + struct { + __IO uint8_t DMACB4HL; + __IO uint8_t DMACB4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA4; + struct { + union { + __IO uint16_t DMACSA4L; + struct { + __IO uint8_t DMACSA4LL; + __IO uint8_t DMACSA4LH; + }; + }; + union { + __IO uint16_t DMACSA4H; + struct { + __IO uint8_t DMACSA4HL; + __IO uint8_t DMACSA4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA4; + struct { + union { + __IO uint16_t DMACDA4L; + struct { + __IO uint8_t DMACDA4LL; + __IO uint8_t DMACDA4LH; + }; + }; + union { + __IO uint16_t DMACDA4H; + struct { + __IO uint8_t DMACDA4HL; + __IO uint8_t DMACDA4HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA5; + stc_dmac_dmaca5_field_t DMACA5_f; + struct { + union { + __IO uint16_t DMACA5L; + struct { + __IO uint8_t DMACA5LL; + __IO uint8_t DMACA5LH; + }; + }; + union { + __IO uint16_t DMACA5H; + struct { + __IO uint8_t DMACA5HL; + __IO uint8_t DMACA5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB5; + stc_dmac_dmacb5_field_t DMACB5_f; + struct { + union { + __IO uint16_t DMACB5L; + struct { + __IO uint8_t DMACB5LL; + __IO uint8_t DMACB5LH; + }; + }; + union { + __IO uint16_t DMACB5H; + struct { + __IO uint8_t DMACB5HL; + __IO uint8_t DMACB5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA5; + struct { + union { + __IO uint16_t DMACSA5L; + struct { + __IO uint8_t DMACSA5LL; + __IO uint8_t DMACSA5LH; + }; + }; + union { + __IO uint16_t DMACSA5H; + struct { + __IO uint8_t DMACSA5HL; + __IO uint8_t DMACSA5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA5; + struct { + union { + __IO uint16_t DMACDA5L; + struct { + __IO uint8_t DMACDA5LL; + __IO uint8_t DMACDA5LH; + }; + }; + union { + __IO uint16_t DMACDA5H; + struct { + __IO uint8_t DMACDA5HL; + __IO uint8_t DMACDA5HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA6; + stc_dmac_dmaca6_field_t DMACA6_f; + struct { + union { + __IO uint16_t DMACA6L; + struct { + __IO uint8_t DMACA6LL; + __IO uint8_t DMACA6LH; + }; + }; + union { + __IO uint16_t DMACA6H; + struct { + __IO uint8_t DMACA6HL; + __IO uint8_t DMACA6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB6; + stc_dmac_dmacb6_field_t DMACB6_f; + struct { + union { + __IO uint16_t DMACB6L; + struct { + __IO uint8_t DMACB6LL; + __IO uint8_t DMACB6LH; + }; + }; + union { + __IO uint16_t DMACB6H; + struct { + __IO uint8_t DMACB6HL; + __IO uint8_t DMACB6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA6; + struct { + union { + __IO uint16_t DMACSA6L; + struct { + __IO uint8_t DMACSA6LL; + __IO uint8_t DMACSA6LH; + }; + }; + union { + __IO uint16_t DMACSA6H; + struct { + __IO uint8_t DMACSA6HL; + __IO uint8_t DMACSA6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA6; + struct { + union { + __IO uint16_t DMACDA6L; + struct { + __IO uint8_t DMACDA6LL; + __IO uint8_t DMACDA6LH; + }; + }; + union { + __IO uint16_t DMACDA6H; + struct { + __IO uint8_t DMACDA6HL; + __IO uint8_t DMACDA6HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACA7; + stc_dmac_dmaca7_field_t DMACA7_f; + struct { + union { + __IO uint16_t DMACA7L; + struct { + __IO uint8_t DMACA7LL; + __IO uint8_t DMACA7LH; + }; + }; + union { + __IO uint16_t DMACA7H; + struct { + __IO uint8_t DMACA7HL; + __IO uint8_t DMACA7HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACB7; + stc_dmac_dmacb7_field_t DMACB7_f; + struct { + union { + __IO uint16_t DMACB7L; + struct { + __IO uint8_t DMACB7LL; + __IO uint8_t DMACB7LH; + }; + }; + union { + __IO uint16_t DMACB7H; + struct { + __IO uint8_t DMACB7HL; + __IO uint8_t DMACB7HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACSA7; + struct { + union { + __IO uint16_t DMACSA7L; + struct { + __IO uint8_t DMACSA7LL; + __IO uint8_t DMACSA7LH; + }; + }; + union { + __IO uint16_t DMACSA7H; + struct { + __IO uint8_t DMACSA7HL; + __IO uint8_t DMACSA7HH; + }; + }; + }; + }; + union { + __IO uint32_t DMACDA7; + struct { + union { + __IO uint16_t DMACDA7L; + struct { + __IO uint8_t DMACDA7LL; + __IO uint8_t DMACDA7LH; + }; + }; + union { + __IO uint16_t DMACDA7H; + struct { + __IO uint8_t DMACDA7HL; + __IO uint8_t DMACDA7HH; + }; + }; + }; + }; +} FM_DMAC_TypeDef, FM4_DMAC_TypeDef; + +/******************************************************************************* +* DS_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[4]; + union { + __IO uint8_t RCK_CTL; + stc_ds_rck_ctl_field_t RCK_CTL_f; + }; + __IO uint8_t RESERVED1[1787]; + union { + __IO uint8_t PMD_CTL; + stc_ds_pmd_ctl_field_t PMD_CTL_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint8_t WRFSR; + stc_ds_wrfsr_field_t WRFSR_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint16_t WIFSR; + stc_ds_wifsr_field_t WIFSR_f; + struct { + __IO uint8_t WIFSRL; + __IO uint8_t WIFSRH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t WIER; + stc_ds_wier_field_t WIER_f; + struct { + __IO uint8_t WIERL; + __IO uint8_t WIERH; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint8_t WILVR; + stc_ds_wilvr_field_t WILVR_f; + }; + __IO uint8_t RESERVED6[3]; + union { + __IO uint8_t DSRAMR; + stc_ds_dsramr_field_t DSRAMR_f; + }; + __IO uint8_t RESERVED7[235]; + __IO uint8_t BUR01; + __IO uint8_t BUR02; + __IO uint8_t BUR03; + __IO uint8_t BUR04; + __IO uint8_t BUR05; + __IO uint8_t BUR06; + __IO uint8_t BUR07; + __IO uint8_t BUR08; + __IO uint8_t BUR09; + __IO uint8_t BUR10; + __IO uint8_t BUR11; + __IO uint8_t BUR12; + __IO uint8_t BUR13; + __IO uint8_t BUR14; + __IO uint8_t BUR15; + __IO uint8_t BUR16; +} FM_DS_TypeDef, FM4_DS_TypeDef; + +/******************************************************************************* +* DSTC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DESTP; + struct { + union { + __IO uint16_t DESTPL; + struct { + __IO uint8_t DESTPLL; + __IO uint8_t DESTPLH; + }; + }; + union { + __IO uint16_t DESTPH; + struct { + __IO uint8_t DESTPHL; + __IO uint8_t DESTPHH; + }; + }; + }; + }; + union { + __IO uint32_t HWDESP; + stc_dstc_hwdesp_field_t HWDESP_f; + struct { + union { + __IO uint16_t HWDESPL; + struct { + __IO uint8_t HWDESPLL; + __IO uint8_t HWDESPLH; + }; + }; + union { + __IO uint16_t HWDESPH; + struct { + __IO uint8_t HWDESPHL; + __IO uint8_t HWDESPHH; + }; + }; + }; + }; + __IO uint8_t CMD; + union { + __IO uint8_t CFG; + stc_dstc_cfg_field_t CFG_f; + }; + union { + __IO uint16_t SWTR; + stc_dstc_swtr_field_t SWTR_f; + struct { + __IO uint8_t SWTRL; + __IO uint8_t SWTRH; + }; + }; + union { + __IO uint32_t MONERS; + stc_dstc_moners_field_t MONERS_f; + struct { + union { + __IO uint16_t MONERSL; + struct { + __IO uint8_t MONERSLL; + __IO uint8_t MONERSLH; + }; + }; + union { + __IO uint16_t MONERSH; + struct { + __IO uint8_t MONERSHL; + __IO uint8_t MONERSHH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB0; + struct { + union { + __IO uint16_t DREQENB0L; + struct { + __IO uint8_t DREQENB0LL; + __IO uint8_t DREQENB0LH; + }; + }; + union { + __IO uint16_t DREQENB0H; + struct { + __IO uint8_t DREQENB0HL; + __IO uint8_t DREQENB0HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB1; + struct { + union { + __IO uint16_t DREQENB1L; + struct { + __IO uint8_t DREQENB1LL; + __IO uint8_t DREQENB1LH; + }; + }; + union { + __IO uint16_t DREQENB1H; + struct { + __IO uint8_t DREQENB1HL; + __IO uint8_t DREQENB1HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB2; + struct { + union { + __IO uint16_t DREQENB2L; + struct { + __IO uint8_t DREQENB2LL; + __IO uint8_t DREQENB2LH; + }; + }; + union { + __IO uint16_t DREQENB2H; + struct { + __IO uint8_t DREQENB2HL; + __IO uint8_t DREQENB2HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB3; + struct { + union { + __IO uint16_t DREQENB3L; + struct { + __IO uint8_t DREQENB3LL; + __IO uint8_t DREQENB3LH; + }; + }; + union { + __IO uint16_t DREQENB3H; + struct { + __IO uint8_t DREQENB3HL; + __IO uint8_t DREQENB3HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB4; + struct { + union { + __IO uint16_t DREQENB4L; + struct { + __IO uint8_t DREQENB4LL; + __IO uint8_t DREQENB4LH; + }; + }; + union { + __IO uint16_t DREQENB4H; + struct { + __IO uint8_t DREQENB4HL; + __IO uint8_t DREQENB4HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB5; + struct { + union { + __IO uint16_t DREQENB5L; + struct { + __IO uint8_t DREQENB5LL; + __IO uint8_t DREQENB5LH; + }; + }; + union { + __IO uint16_t DREQENB5H; + struct { + __IO uint8_t DREQENB5HL; + __IO uint8_t DREQENB5HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB6; + struct { + union { + __IO uint16_t DREQENB6L; + struct { + __IO uint8_t DREQENB6LL; + __IO uint8_t DREQENB6LH; + }; + }; + union { + __IO uint16_t DREQENB6H; + struct { + __IO uint8_t DREQENB6HL; + __IO uint8_t DREQENB6HH; + }; + }; + }; + }; + union { + __IO uint32_t DREQENB7; + struct { + union { + __IO uint16_t DREQENB7L; + struct { + __IO uint8_t DREQENB7LL; + __IO uint8_t DREQENB7LH; + }; + }; + union { + __IO uint16_t DREQENB7H; + struct { + __IO uint8_t DREQENB7HL; + __IO uint8_t DREQENB7HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT0; + struct { + union { + __IO uint16_t HWINT0L; + struct { + __IO uint8_t HWINT0LL; + __IO uint8_t HWINT0LH; + }; + }; + union { + __IO uint16_t HWINT0H; + struct { + __IO uint8_t HWINT0HL; + __IO uint8_t HWINT0HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT1; + struct { + union { + __IO uint16_t HWINT1L; + struct { + __IO uint8_t HWINT1LL; + __IO uint8_t HWINT1LH; + }; + }; + union { + __IO uint16_t HWINT1H; + struct { + __IO uint8_t HWINT1HL; + __IO uint8_t HWINT1HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT2; + struct { + union { + __IO uint16_t HWINT2L; + struct { + __IO uint8_t HWINT2LL; + __IO uint8_t HWINT2LH; + }; + }; + union { + __IO uint16_t HWINT2H; + struct { + __IO uint8_t HWINT2HL; + __IO uint8_t HWINT2HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT3; + struct { + union { + __IO uint16_t HWINT3L; + struct { + __IO uint8_t HWINT3LL; + __IO uint8_t HWINT3LH; + }; + }; + union { + __IO uint16_t HWINT3H; + struct { + __IO uint8_t HWINT3HL; + __IO uint8_t HWINT3HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT4; + struct { + union { + __IO uint16_t HWINT4L; + struct { + __IO uint8_t HWINT4LL; + __IO uint8_t HWINT4LH; + }; + }; + union { + __IO uint16_t HWINT4H; + struct { + __IO uint8_t HWINT4HL; + __IO uint8_t HWINT4HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT5; + struct { + union { + __IO uint16_t HWINT5L; + struct { + __IO uint8_t HWINT5LL; + __IO uint8_t HWINT5LH; + }; + }; + union { + __IO uint16_t HWINT5H; + struct { + __IO uint8_t HWINT5HL; + __IO uint8_t HWINT5HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT6; + struct { + union { + __IO uint16_t HWINT6L; + struct { + __IO uint8_t HWINT6LL; + __IO uint8_t HWINT6LH; + }; + }; + union { + __IO uint16_t HWINT6H; + struct { + __IO uint8_t HWINT6HL; + __IO uint8_t HWINT6HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINT7; + struct { + union { + __IO uint16_t HWINT7L; + struct { + __IO uint8_t HWINT7LL; + __IO uint8_t HWINT7LH; + }; + }; + union { + __IO uint16_t HWINT7H; + struct { + __IO uint8_t HWINT7HL; + __IO uint8_t HWINT7HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR0; + struct { + union { + __IO uint16_t HWINTCLR0L; + struct { + __IO uint8_t HWINTCLR0LL; + __IO uint8_t HWINTCLR0LH; + }; + }; + union { + __IO uint16_t HWINTCLR0H; + struct { + __IO uint8_t HWINTCLR0HL; + __IO uint8_t HWINTCLR0HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR1; + struct { + union { + __IO uint16_t HWINTCLR1L; + struct { + __IO uint8_t HWINTCLR1LL; + __IO uint8_t HWINTCLR1LH; + }; + }; + union { + __IO uint16_t HWINTCLR1H; + struct { + __IO uint8_t HWINTCLR1HL; + __IO uint8_t HWINTCLR1HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR2; + struct { + union { + __IO uint16_t HWINTCLR2L; + struct { + __IO uint8_t HWINTCLR2LL; + __IO uint8_t HWINTCLR2LH; + }; + }; + union { + __IO uint16_t HWINTCLR2H; + struct { + __IO uint8_t HWINTCLR2HL; + __IO uint8_t HWINTCLR2HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR3; + struct { + union { + __IO uint16_t HWINTCLR3L; + struct { + __IO uint8_t HWINTCLR3LL; + __IO uint8_t HWINTCLR3LH; + }; + }; + union { + __IO uint16_t HWINTCLR3H; + struct { + __IO uint8_t HWINTCLR3HL; + __IO uint8_t HWINTCLR3HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR4; + struct { + union { + __IO uint16_t HWINTCLR4L; + struct { + __IO uint8_t HWINTCLR4LL; + __IO uint8_t HWINTCLR4LH; + }; + }; + union { + __IO uint16_t HWINTCLR4H; + struct { + __IO uint8_t HWINTCLR4HL; + __IO uint8_t HWINTCLR4HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR5; + struct { + union { + __IO uint16_t HWINTCLR5L; + struct { + __IO uint8_t HWINTCLR5LL; + __IO uint8_t HWINTCLR5LH; + }; + }; + union { + __IO uint16_t HWINTCLR5H; + struct { + __IO uint8_t HWINTCLR5HL; + __IO uint8_t HWINTCLR5HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR6; + struct { + union { + __IO uint16_t HWINTCLR6L; + struct { + __IO uint8_t HWINTCLR6LL; + __IO uint8_t HWINTCLR6LH; + }; + }; + union { + __IO uint16_t HWINTCLR6H; + struct { + __IO uint8_t HWINTCLR6HL; + __IO uint8_t HWINTCLR6HH; + }; + }; + }; + }; + union { + __IO uint32_t HWINTCLR7; + struct { + union { + __IO uint16_t HWINTCLR7L; + struct { + __IO uint8_t HWINTCLR7LL; + __IO uint8_t HWINTCLR7LH; + }; + }; + union { + __IO uint16_t HWINTCLR7H; + struct { + __IO uint8_t HWINTCLR7HL; + __IO uint8_t HWINTCLR7HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK0; + struct { + union { + __IO uint16_t DQMSK0L; + struct { + __IO uint8_t DQMSK0LL; + __IO uint8_t DQMSK0LH; + }; + }; + union { + __IO uint16_t DQMSK0H; + struct { + __IO uint8_t DQMSK0HL; + __IO uint8_t DQMSK0HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK1; + struct { + union { + __IO uint16_t DQMSK1L; + struct { + __IO uint8_t DQMSK1LL; + __IO uint8_t DQMSK1LH; + }; + }; + union { + __IO uint16_t DQMSK1H; + struct { + __IO uint8_t DQMSK1HL; + __IO uint8_t DQMSK1HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK2; + struct { + union { + __IO uint16_t DQMSK2L; + struct { + __IO uint8_t DQMSK2LL; + __IO uint8_t DQMSK2LH; + }; + }; + union { + __IO uint16_t DQMSK2H; + struct { + __IO uint8_t DQMSK2HL; + __IO uint8_t DQMSK2HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK3; + struct { + union { + __IO uint16_t DQMSK3L; + struct { + __IO uint8_t DQMSK3LL; + __IO uint8_t DQMSK3LH; + }; + }; + union { + __IO uint16_t DQMSK3H; + struct { + __IO uint8_t DQMSK3HL; + __IO uint8_t DQMSK3HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK4; + struct { + union { + __IO uint16_t DQMSK4L; + struct { + __IO uint8_t DQMSK4LL; + __IO uint8_t DQMSK4LH; + }; + }; + union { + __IO uint16_t DQMSK4H; + struct { + __IO uint8_t DQMSK4HL; + __IO uint8_t DQMSK4HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK5; + struct { + union { + __IO uint16_t DQMSK5L; + struct { + __IO uint8_t DQMSK5LL; + __IO uint8_t DQMSK5LH; + }; + }; + union { + __IO uint16_t DQMSK5H; + struct { + __IO uint8_t DQMSK5HL; + __IO uint8_t DQMSK5HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK6; + struct { + union { + __IO uint16_t DQMSK6L; + struct { + __IO uint8_t DQMSK6LL; + __IO uint8_t DQMSK6LH; + }; + }; + union { + __IO uint16_t DQMSK6H; + struct { + __IO uint8_t DQMSK6HL; + __IO uint8_t DQMSK6HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSK7; + struct { + union { + __IO uint16_t DQMSK7L; + struct { + __IO uint8_t DQMSK7LL; + __IO uint8_t DQMSK7LH; + }; + }; + union { + __IO uint16_t DQMSK7H; + struct { + __IO uint8_t DQMSK7HL; + __IO uint8_t DQMSK7HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR0; + struct { + union { + __IO uint16_t DQMSKCLR0L; + struct { + __IO uint8_t DQMSKCLR0LL; + __IO uint8_t DQMSKCLR0LH; + }; + }; + union { + __IO uint16_t DQMSKCLR0H; + struct { + __IO uint8_t DQMSKCLR0HL; + __IO uint8_t DQMSKCLR0HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR1; + struct { + union { + __IO uint16_t DQMSKCLR1L; + struct { + __IO uint8_t DQMSKCLR1LL; + __IO uint8_t DQMSKCLR1LH; + }; + }; + union { + __IO uint16_t DQMSKCLR1H; + struct { + __IO uint8_t DQMSKCLR1HL; + __IO uint8_t DQMSKCLR1HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR2; + struct { + union { + __IO uint16_t DQMSKCLR2L; + struct { + __IO uint8_t DQMSKCLR2LL; + __IO uint8_t DQMSKCLR2LH; + }; + }; + union { + __IO uint16_t DQMSKCLR2H; + struct { + __IO uint8_t DQMSKCLR2HL; + __IO uint8_t DQMSKCLR2HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR3; + struct { + union { + __IO uint16_t DQMSKCLR3L; + struct { + __IO uint8_t DQMSKCLR3LL; + __IO uint8_t DQMSKCLR3LH; + }; + }; + union { + __IO uint16_t DQMSKCLR3H; + struct { + __IO uint8_t DQMSKCLR3HL; + __IO uint8_t DQMSKCLR3HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR4; + struct { + union { + __IO uint16_t DQMSKCLR4L; + struct { + __IO uint8_t DQMSKCLR4LL; + __IO uint8_t DQMSKCLR4LH; + }; + }; + union { + __IO uint16_t DQMSKCLR4H; + struct { + __IO uint8_t DQMSKCLR4HL; + __IO uint8_t DQMSKCLR4HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR5; + struct { + union { + __IO uint16_t DQMSKCLR5L; + struct { + __IO uint8_t DQMSKCLR5LL; + __IO uint8_t DQMSKCLR5LH; + }; + }; + union { + __IO uint16_t DQMSKCLR5H; + struct { + __IO uint8_t DQMSKCLR5HL; + __IO uint8_t DQMSKCLR5HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR6; + struct { + union { + __IO uint16_t DQMSKCLR6L; + struct { + __IO uint8_t DQMSKCLR6LL; + __IO uint8_t DQMSKCLR6LH; + }; + }; + union { + __IO uint16_t DQMSKCLR6H; + struct { + __IO uint8_t DQMSKCLR6HL; + __IO uint8_t DQMSKCLR6HH; + }; + }; + }; + }; + union { + __IO uint32_t DQMSKCLR7; + struct { + union { + __IO uint16_t DQMSKCLR7L; + struct { + __IO uint8_t DQMSKCLR7LL; + __IO uint8_t DQMSKCLR7LH; + }; + }; + union { + __IO uint16_t DQMSKCLR7H; + struct { + __IO uint8_t DQMSKCLR7HL; + __IO uint8_t DQMSKCLR7HH; + }; + }; + }; + }; +} FM_DSTC_TypeDef, FM4_DSTC_TypeDef; + +/******************************************************************************* +* DT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t TIMER1LOAD; + struct { + union { + __IO uint16_t TIMER1LOADL; + struct { + __IO uint8_t TIMER1LOADLL; + __IO uint8_t TIMER1LOADLH; + }; + }; + union { + __IO uint16_t TIMER1LOADH; + struct { + __IO uint8_t TIMER1LOADHL; + __IO uint8_t TIMER1LOADHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1VALUE; + struct { + union { + __IO uint16_t TIMER1VALUEL; + struct { + __IO uint8_t TIMER1VALUELL; + __IO uint8_t TIMER1VALUELH; + }; + }; + union { + __IO uint16_t TIMER1VALUEH; + struct { + __IO uint8_t TIMER1VALUEHL; + __IO uint8_t TIMER1VALUEHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1CONTROL; + stc_dt_timer1control_field_t TIMER1CONTROL_f; + struct { + union { + __IO uint16_t TIMER1CONTROLL; + struct { + __IO uint8_t TIMER1CONTROLLL; + __IO uint8_t TIMER1CONTROLLH; + }; + }; + union { + __IO uint16_t TIMER1CONTROLH; + struct { + __IO uint8_t TIMER1CONTROLHL; + __IO uint8_t TIMER1CONTROLHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1INTCLR; + struct { + union { + __IO uint16_t TIMER1INTCLRL; + struct { + __IO uint8_t TIMER1INTCLRLL; + __IO uint8_t TIMER1INTCLRLH; + }; + }; + union { + __IO uint16_t TIMER1INTCLRH; + struct { + __IO uint8_t TIMER1INTCLRHL; + __IO uint8_t TIMER1INTCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1RIS; + stc_dt_timer1ris_field_t TIMER1RIS_f; + struct { + union { + __IO uint16_t TIMER1RISL; + struct { + __IO uint8_t TIMER1RISLL; + __IO uint8_t TIMER1RISLH; + }; + }; + union { + __IO uint16_t TIMER1RISH; + struct { + __IO uint8_t TIMER1RISHL; + __IO uint8_t TIMER1RISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1MIS; + stc_dt_timer1mis_field_t TIMER1MIS_f; + struct { + union { + __IO uint16_t TIMER1MISL; + struct { + __IO uint8_t TIMER1MISLL; + __IO uint8_t TIMER1MISLH; + }; + }; + union { + __IO uint16_t TIMER1MISH; + struct { + __IO uint8_t TIMER1MISHL; + __IO uint8_t TIMER1MISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER1BGLOAD; + struct { + union { + __IO uint16_t TIMER1BGLOADL; + struct { + __IO uint8_t TIMER1BGLOADLL; + __IO uint8_t TIMER1BGLOADLH; + }; + }; + union { + __IO uint16_t TIMER1BGLOADH; + struct { + __IO uint8_t TIMER1BGLOADHL; + __IO uint8_t TIMER1BGLOADHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t TIMER2LOAD; + struct { + union { + __IO uint16_t TIMER2LOADL; + struct { + __IO uint8_t TIMER2LOADLL; + __IO uint8_t TIMER2LOADLH; + }; + }; + union { + __IO uint16_t TIMER2LOADH; + struct { + __IO uint8_t TIMER2LOADHL; + __IO uint8_t TIMER2LOADHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2VALUE; + struct { + union { + __IO uint16_t TIMER2VALUEL; + struct { + __IO uint8_t TIMER2VALUELL; + __IO uint8_t TIMER2VALUELH; + }; + }; + union { + __IO uint16_t TIMER2VALUEH; + struct { + __IO uint8_t TIMER2VALUEHL; + __IO uint8_t TIMER2VALUEHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2CONTROL; + stc_dt_timer2control_field_t TIMER2CONTROL_f; + struct { + union { + __IO uint16_t TIMER2CONTROLL; + struct { + __IO uint8_t TIMER2CONTROLLL; + __IO uint8_t TIMER2CONTROLLH; + }; + }; + union { + __IO uint16_t TIMER2CONTROLH; + struct { + __IO uint8_t TIMER2CONTROLHL; + __IO uint8_t TIMER2CONTROLHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2INTCLR; + struct { + union { + __IO uint16_t TIMER2INTCLRL; + struct { + __IO uint8_t TIMER2INTCLRLL; + __IO uint8_t TIMER2INTCLRLH; + }; + }; + union { + __IO uint16_t TIMER2INTCLRH; + struct { + __IO uint8_t TIMER2INTCLRHL; + __IO uint8_t TIMER2INTCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2RIS; + stc_dt_timer2ris_field_t TIMER2RIS_f; + struct { + union { + __IO uint16_t TIMER2RISL; + struct { + __IO uint8_t TIMER2RISLL; + __IO uint8_t TIMER2RISLH; + }; + }; + union { + __IO uint16_t TIMER2RISH; + struct { + __IO uint8_t TIMER2RISHL; + __IO uint8_t TIMER2RISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2MIS; + stc_dt_timer2mis_field_t TIMER2MIS_f; + struct { + union { + __IO uint16_t TIMER2MISL; + struct { + __IO uint8_t TIMER2MISLL; + __IO uint8_t TIMER2MISLH; + }; + }; + union { + __IO uint16_t TIMER2MISH; + struct { + __IO uint8_t TIMER2MISHL; + __IO uint8_t TIMER2MISHH; + }; + }; + }; + }; + union { + __IO uint32_t TIMER2BGLOAD; + struct { + union { + __IO uint16_t TIMER2BGLOADL; + struct { + __IO uint8_t TIMER2BGLOADLL; + __IO uint8_t TIMER2BGLOADLH; + }; + }; + union { + __IO uint16_t TIMER2BGLOADH; + struct { + __IO uint8_t TIMER2BGLOADHL; + __IO uint8_t TIMER2BGLOADHH; + }; + }; + }; + }; +} FM_DT_TypeDef, FM4_DT_TypeDef; + +/******************************************************************************* +* DUALFLASH_IF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DFASZR; + stc_dualflash_if_dfaszr_field_t DFASZR_f; + struct { + union { + __IO uint16_t DFASZRL; + struct { + __IO uint8_t DFASZRLL; + __IO uint8_t DFASZRLH; + }; + }; + union { + __IO uint16_t DFASZRH; + struct { + __IO uint8_t DFASZRHL; + __IO uint8_t DFASZRHH; + }; + }; + }; + }; + union { + __IO uint32_t DFRWTR; + stc_dualflash_if_dfrwtr_field_t DFRWTR_f; + struct { + union { + __IO uint16_t DFRWTRL; + struct { + __IO uint8_t DFRWTRLL; + __IO uint8_t DFRWTRLH; + }; + }; + union { + __IO uint16_t DFRWTRH; + struct { + __IO uint8_t DFRWTRHL; + __IO uint8_t DFRWTRHH; + }; + }; + }; + }; + union { + __IO uint32_t DFSTR; + stc_dualflash_if_dfstr_field_t DFSTR_f; + struct { + union { + __IO uint16_t DFSTRL; + struct { + __IO uint8_t DFSTRLL; + __IO uint8_t DFSTRLH; + }; + }; + union { + __IO uint16_t DFSTRH; + struct { + __IO uint8_t DFSTRHL; + __IO uint8_t DFSTRHH; + }; + }; + }; + }; +} FM_DUALFLASH_IF_TypeDef, FM4_DUALFLASH_IF_TypeDef; + +/******************************************************************************* +* ECC_CAPTURE_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t FERRAD; + stc_ecc_capture_ferrad_field_t FERRAD_f; + struct { + union { + __IO uint16_t FERRADL; + struct { + __IO uint8_t FERRADLL; + __IO uint8_t FERRADLH; + }; + }; + union { + __IO uint16_t FERRADH; + struct { + __IO uint8_t FERRADHL; + __IO uint8_t FERRADHH; + }; + }; + }; + }; +} FM_ECC_CAPTURE_TypeDef, FM4_ECC_CAPTURE_TypeDef; + +/******************************************************************************* +* EXBUS_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t MODE0; + stc_exbus_mode0_field_t MODE0_f; + struct { + union { + __IO uint16_t MODE0L; + struct { + __IO uint8_t MODE0LL; + __IO uint8_t MODE0LH; + }; + }; + union { + __IO uint16_t MODE0H; + struct { + __IO uint8_t MODE0HL; + __IO uint8_t MODE0HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE1; + stc_exbus_mode1_field_t MODE1_f; + struct { + union { + __IO uint16_t MODE1L; + struct { + __IO uint8_t MODE1LL; + __IO uint8_t MODE1LH; + }; + }; + union { + __IO uint16_t MODE1H; + struct { + __IO uint8_t MODE1HL; + __IO uint8_t MODE1HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE2; + stc_exbus_mode2_field_t MODE2_f; + struct { + union { + __IO uint16_t MODE2L; + struct { + __IO uint8_t MODE2LL; + __IO uint8_t MODE2LH; + }; + }; + union { + __IO uint16_t MODE2H; + struct { + __IO uint8_t MODE2HL; + __IO uint8_t MODE2HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE3; + stc_exbus_mode3_field_t MODE3_f; + struct { + union { + __IO uint16_t MODE3L; + struct { + __IO uint8_t MODE3LL; + __IO uint8_t MODE3LH; + }; + }; + union { + __IO uint16_t MODE3H; + struct { + __IO uint8_t MODE3HL; + __IO uint8_t MODE3HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE4; + stc_exbus_mode4_field_t MODE4_f; + struct { + union { + __IO uint16_t MODE4L; + struct { + __IO uint8_t MODE4LL; + __IO uint8_t MODE4LH; + }; + }; + union { + __IO uint16_t MODE4H; + struct { + __IO uint8_t MODE4HL; + __IO uint8_t MODE4HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE5; + stc_exbus_mode5_field_t MODE5_f; + struct { + union { + __IO uint16_t MODE5L; + struct { + __IO uint8_t MODE5LL; + __IO uint8_t MODE5LH; + }; + }; + union { + __IO uint16_t MODE5H; + struct { + __IO uint8_t MODE5HL; + __IO uint8_t MODE5HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE6; + stc_exbus_mode6_field_t MODE6_f; + struct { + union { + __IO uint16_t MODE6L; + struct { + __IO uint8_t MODE6LL; + __IO uint8_t MODE6LH; + }; + }; + union { + __IO uint16_t MODE6H; + struct { + __IO uint8_t MODE6HL; + __IO uint8_t MODE6HH; + }; + }; + }; + }; + union { + __IO uint32_t MODE7; + stc_exbus_mode7_field_t MODE7_f; + struct { + union { + __IO uint16_t MODE7L; + struct { + __IO uint8_t MODE7LL; + __IO uint8_t MODE7LH; + }; + }; + union { + __IO uint16_t MODE7H; + struct { + __IO uint8_t MODE7HL; + __IO uint8_t MODE7HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM0; + stc_exbus_tim0_field_t TIM0_f; + struct { + union { + __IO uint16_t TIM0L; + struct { + __IO uint8_t TIM0LL; + __IO uint8_t TIM0LH; + }; + }; + union { + __IO uint16_t TIM0H; + struct { + __IO uint8_t TIM0HL; + __IO uint8_t TIM0HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM1; + stc_exbus_tim1_field_t TIM1_f; + struct { + union { + __IO uint16_t TIM1L; + struct { + __IO uint8_t TIM1LL; + __IO uint8_t TIM1LH; + }; + }; + union { + __IO uint16_t TIM1H; + struct { + __IO uint8_t TIM1HL; + __IO uint8_t TIM1HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM2; + stc_exbus_tim2_field_t TIM2_f; + struct { + union { + __IO uint16_t TIM2L; + struct { + __IO uint8_t TIM2LL; + __IO uint8_t TIM2LH; + }; + }; + union { + __IO uint16_t TIM2H; + struct { + __IO uint8_t TIM2HL; + __IO uint8_t TIM2HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM3; + stc_exbus_tim3_field_t TIM3_f; + struct { + union { + __IO uint16_t TIM3L; + struct { + __IO uint8_t TIM3LL; + __IO uint8_t TIM3LH; + }; + }; + union { + __IO uint16_t TIM3H; + struct { + __IO uint8_t TIM3HL; + __IO uint8_t TIM3HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM4; + stc_exbus_tim4_field_t TIM4_f; + struct { + union { + __IO uint16_t TIM4L; + struct { + __IO uint8_t TIM4LL; + __IO uint8_t TIM4LH; + }; + }; + union { + __IO uint16_t TIM4H; + struct { + __IO uint8_t TIM4HL; + __IO uint8_t TIM4HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM5; + stc_exbus_tim5_field_t TIM5_f; + struct { + union { + __IO uint16_t TIM5L; + struct { + __IO uint8_t TIM5LL; + __IO uint8_t TIM5LH; + }; + }; + union { + __IO uint16_t TIM5H; + struct { + __IO uint8_t TIM5HL; + __IO uint8_t TIM5HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM6; + stc_exbus_tim6_field_t TIM6_f; + struct { + union { + __IO uint16_t TIM6L; + struct { + __IO uint8_t TIM6LL; + __IO uint8_t TIM6LH; + }; + }; + union { + __IO uint16_t TIM6H; + struct { + __IO uint8_t TIM6HL; + __IO uint8_t TIM6HH; + }; + }; + }; + }; + union { + __IO uint32_t TIM7; + stc_exbus_tim7_field_t TIM7_f; + struct { + union { + __IO uint16_t TIM7L; + struct { + __IO uint8_t TIM7LL; + __IO uint8_t TIM7LH; + }; + }; + union { + __IO uint16_t TIM7H; + struct { + __IO uint8_t TIM7HL; + __IO uint8_t TIM7HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA0; + stc_exbus_area0_field_t AREA0_f; + struct { + union { + __IO uint16_t AREA0L; + struct { + __IO uint8_t AREA0LL; + __IO uint8_t AREA0LH; + }; + }; + union { + __IO uint16_t AREA0H; + struct { + __IO uint8_t AREA0HL; + __IO uint8_t AREA0HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA1; + stc_exbus_area1_field_t AREA1_f; + struct { + union { + __IO uint16_t AREA1L; + struct { + __IO uint8_t AREA1LL; + __IO uint8_t AREA1LH; + }; + }; + union { + __IO uint16_t AREA1H; + struct { + __IO uint8_t AREA1HL; + __IO uint8_t AREA1HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA2; + stc_exbus_area2_field_t AREA2_f; + struct { + union { + __IO uint16_t AREA2L; + struct { + __IO uint8_t AREA2LL; + __IO uint8_t AREA2LH; + }; + }; + union { + __IO uint16_t AREA2H; + struct { + __IO uint8_t AREA2HL; + __IO uint8_t AREA2HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA3; + stc_exbus_area3_field_t AREA3_f; + struct { + union { + __IO uint16_t AREA3L; + struct { + __IO uint8_t AREA3LL; + __IO uint8_t AREA3LH; + }; + }; + union { + __IO uint16_t AREA3H; + struct { + __IO uint8_t AREA3HL; + __IO uint8_t AREA3HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA4; + stc_exbus_area4_field_t AREA4_f; + struct { + union { + __IO uint16_t AREA4L; + struct { + __IO uint8_t AREA4LL; + __IO uint8_t AREA4LH; + }; + }; + union { + __IO uint16_t AREA4H; + struct { + __IO uint8_t AREA4HL; + __IO uint8_t AREA4HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA5; + stc_exbus_area5_field_t AREA5_f; + struct { + union { + __IO uint16_t AREA5L; + struct { + __IO uint8_t AREA5LL; + __IO uint8_t AREA5LH; + }; + }; + union { + __IO uint16_t AREA5H; + struct { + __IO uint8_t AREA5HL; + __IO uint8_t AREA5HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA6; + stc_exbus_area6_field_t AREA6_f; + struct { + union { + __IO uint16_t AREA6L; + struct { + __IO uint8_t AREA6LL; + __IO uint8_t AREA6LH; + }; + }; + union { + __IO uint16_t AREA6H; + struct { + __IO uint8_t AREA6HL; + __IO uint8_t AREA6HH; + }; + }; + }; + }; + union { + __IO uint32_t AREA7; + stc_exbus_area7_field_t AREA7_f; + struct { + union { + __IO uint16_t AREA7L; + struct { + __IO uint8_t AREA7LL; + __IO uint8_t AREA7LH; + }; + }; + union { + __IO uint16_t AREA7H; + struct { + __IO uint8_t AREA7HL; + __IO uint8_t AREA7HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM0; + stc_exbus_atim0_field_t ATIM0_f; + struct { + union { + __IO uint16_t ATIM0L; + struct { + __IO uint8_t ATIM0LL; + __IO uint8_t ATIM0LH; + }; + }; + union { + __IO uint16_t ATIM0H; + struct { + __IO uint8_t ATIM0HL; + __IO uint8_t ATIM0HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM1; + stc_exbus_atim1_field_t ATIM1_f; + struct { + union { + __IO uint16_t ATIM1L; + struct { + __IO uint8_t ATIM1LL; + __IO uint8_t ATIM1LH; + }; + }; + union { + __IO uint16_t ATIM1H; + struct { + __IO uint8_t ATIM1HL; + __IO uint8_t ATIM1HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM2; + stc_exbus_atim2_field_t ATIM2_f; + struct { + union { + __IO uint16_t ATIM2L; + struct { + __IO uint8_t ATIM2LL; + __IO uint8_t ATIM2LH; + }; + }; + union { + __IO uint16_t ATIM2H; + struct { + __IO uint8_t ATIM2HL; + __IO uint8_t ATIM2HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM3; + stc_exbus_atim3_field_t ATIM3_f; + struct { + union { + __IO uint16_t ATIM3L; + struct { + __IO uint8_t ATIM3LL; + __IO uint8_t ATIM3LH; + }; + }; + union { + __IO uint16_t ATIM3H; + struct { + __IO uint8_t ATIM3HL; + __IO uint8_t ATIM3HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM4; + stc_exbus_atim4_field_t ATIM4_f; + struct { + union { + __IO uint16_t ATIM4L; + struct { + __IO uint8_t ATIM4LL; + __IO uint8_t ATIM4LH; + }; + }; + union { + __IO uint16_t ATIM4H; + struct { + __IO uint8_t ATIM4HL; + __IO uint8_t ATIM4HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM5; + stc_exbus_atim5_field_t ATIM5_f; + struct { + union { + __IO uint16_t ATIM5L; + struct { + __IO uint8_t ATIM5LL; + __IO uint8_t ATIM5LH; + }; + }; + union { + __IO uint16_t ATIM5H; + struct { + __IO uint8_t ATIM5HL; + __IO uint8_t ATIM5HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM6; + stc_exbus_atim6_field_t ATIM6_f; + struct { + union { + __IO uint16_t ATIM6L; + struct { + __IO uint8_t ATIM6LL; + __IO uint8_t ATIM6LH; + }; + }; + union { + __IO uint16_t ATIM6H; + struct { + __IO uint8_t ATIM6HL; + __IO uint8_t ATIM6HH; + }; + }; + }; + }; + union { + __IO uint32_t ATIM7; + stc_exbus_atim7_field_t ATIM7_f; + struct { + union { + __IO uint16_t ATIM7L; + struct { + __IO uint8_t ATIM7LL; + __IO uint8_t ATIM7LH; + }; + }; + union { + __IO uint16_t ATIM7H; + struct { + __IO uint8_t ATIM7HL; + __IO uint8_t ATIM7HH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[128]; + union { + __IO uint32_t SDMODE; + stc_exbus_sdmode_field_t SDMODE_f; + struct { + union { + __IO uint16_t SDMODEL; + struct { + __IO uint8_t SDMODELL; + __IO uint8_t SDMODELH; + }; + }; + union { + __IO uint16_t SDMODEH; + struct { + __IO uint8_t SDMODEHL; + __IO uint8_t SDMODEHH; + }; + }; + }; + }; + union { + __IO uint32_t REFTIM; + stc_exbus_reftim_field_t REFTIM_f; + struct { + union { + __IO uint16_t REFTIML; + struct { + __IO uint8_t REFTIMLL; + __IO uint8_t REFTIMLH; + }; + }; + union { + __IO uint16_t REFTIMH; + struct { + __IO uint8_t REFTIMHL; + __IO uint8_t REFTIMHH; + }; + }; + }; + }; + union { + __IO uint32_t PWRDWN; + stc_exbus_pwrdwn_field_t PWRDWN_f; + struct { + union { + __IO uint16_t PWRDWNL; + struct { + __IO uint8_t PWRDWNLL; + __IO uint8_t PWRDWNLH; + }; + }; + union { + __IO uint16_t PWRDWNH; + struct { + __IO uint8_t PWRDWNHL; + __IO uint8_t PWRDWNHH; + }; + }; + }; + }; + union { + __IO uint32_t SDTIM; + stc_exbus_sdtim_field_t SDTIM_f; + struct { + union { + __IO uint16_t SDTIML; + struct { + __IO uint8_t SDTIMLL; + __IO uint8_t SDTIMLH; + }; + }; + union { + __IO uint16_t SDTIMH; + struct { + __IO uint8_t SDTIMHL; + __IO uint8_t SDTIMHH; + }; + }; + }; + }; + union { + __IO uint32_t SDCMD; + stc_exbus_sdcmd_field_t SDCMD_f; + struct { + union { + __IO uint16_t SDCMDL; + struct { + __IO uint8_t SDCMDLL; + __IO uint8_t SDCMDLH; + }; + }; + union { + __IO uint16_t SDCMDH; + struct { + __IO uint8_t SDCMDHL; + __IO uint8_t SDCMDHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[236]; + union { + __IO uint32_t MEMCERR; + stc_exbus_memcerr_field_t MEMCERR_f; + struct { + union { + __IO uint16_t MEMCERRL; + struct { + __IO uint8_t MEMCERRLL; + __IO uint8_t MEMCERRLH; + }; + }; + union { + __IO uint16_t MEMCERRH; + struct { + __IO uint8_t MEMCERRHL; + __IO uint8_t MEMCERRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[252]; + union { + __IO uint32_t DCLKR; + stc_exbus_dclkr_field_t DCLKR_f; + struct { + union { + __IO uint16_t DCLKRL; + struct { + __IO uint8_t DCLKRLL; + __IO uint8_t DCLKRLH; + }; + }; + union { + __IO uint16_t DCLKRH; + struct { + __IO uint8_t DCLKRHL; + __IO uint8_t DCLKRHH; + }; + }; + }; + }; + union { + __IO uint32_t EST; + stc_exbus_est_field_t EST_f; + struct { + union { + __IO uint16_t ESTL; + struct { + __IO uint8_t ESTLL; + __IO uint8_t ESTLH; + }; + }; + union { + __IO uint16_t ESTH; + struct { + __IO uint8_t ESTHL; + __IO uint8_t ESTHH; + }; + }; + }; + }; + union { + __IO uint32_t WEAD; + stc_exbus_wead_field_t WEAD_f; + struct { + union { + __IO uint16_t WEADL; + struct { + __IO uint8_t WEADLL; + __IO uint8_t WEADLH; + }; + }; + union { + __IO uint16_t WEADH; + struct { + __IO uint8_t WEADHL; + __IO uint8_t WEADHH; + }; + }; + }; + }; + union { + __IO uint32_t ESCLR; + stc_exbus_esclr_field_t ESCLR_f; + struct { + union { + __IO uint16_t ESCLRL; + struct { + __IO uint8_t ESCLRLL; + __IO uint8_t ESCLRLH; + }; + }; + union { + __IO uint16_t ESCLRH; + struct { + __IO uint8_t ESCLRHL; + __IO uint8_t ESCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t AMODE; + stc_exbus_amode_field_t AMODE_f; + struct { + union { + __IO uint16_t AMODEL; + struct { + __IO uint8_t AMODELL; + __IO uint8_t AMODELH; + }; + }; + union { + __IO uint16_t AMODEH; + struct { + __IO uint8_t AMODEHL; + __IO uint8_t AMODEHH; + }; + }; + }; + }; +} FM_EXBUS_TypeDef, FM4_EXBUS_TypeDef; + +/******************************************************************************* +* EXTI_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t ENIR; + stc_exti_enir_field_t ENIR_f; + struct { + union { + __IO uint16_t ENIRL; + struct { + __IO uint8_t ENIRLL; + __IO uint8_t ENIRLH; + }; + }; + union { + __IO uint16_t ENIRH; + struct { + __IO uint8_t ENIRHL; + __IO uint8_t ENIRHH; + }; + }; + }; + }; + union { + __IO uint32_t EIRR; + stc_exti_eirr_field_t EIRR_f; + struct { + union { + __IO uint16_t EIRRL; + struct { + __IO uint8_t EIRRLL; + __IO uint8_t EIRRLH; + }; + }; + union { + __IO uint16_t EIRRH; + struct { + __IO uint8_t EIRRHL; + __IO uint8_t EIRRHH; + }; + }; + }; + }; + union { + __IO uint32_t EICL; + stc_exti_eicl_field_t EICL_f; + struct { + union { + __IO uint16_t EICLL; + struct { + __IO uint8_t EICLLL; + __IO uint8_t EICLLH; + }; + }; + union { + __IO uint16_t EICLH; + struct { + __IO uint8_t EICLHL; + __IO uint8_t EICLHH; + }; + }; + }; + }; + union { + __IO uint32_t ELVR; + stc_exti_elvr_field_t ELVR_f; + struct { + union { + __IO uint16_t ELVRL; + struct { + __IO uint8_t ELVRLL; + __IO uint8_t ELVRLH; + }; + }; + union { + __IO uint16_t ELVRH; + struct { + __IO uint8_t ELVRHL; + __IO uint8_t ELVRHH; + }; + }; + }; + }; + union { + __IO uint32_t ELVR1; + stc_exti_elvr1_field_t ELVR1_f; + struct { + union { + __IO uint16_t ELVR1L; + struct { + __IO uint8_t ELVR1LL; + __IO uint8_t ELVR1LH; + }; + }; + union { + __IO uint16_t ELVR1H; + struct { + __IO uint8_t ELVR1HL; + __IO uint8_t ELVR1HH; + }; + }; + }; + }; + union { + __IO uint16_t NMIRR; + stc_exti_nmirr_field_t NMIRR_f; + struct { + __IO uint8_t NMIRRL; + __IO uint8_t NMIRRH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t NMICL; + stc_exti_nmicl_field_t NMICL_f; + struct { + __IO uint8_t NMICLL; + __IO uint8_t NMICLH; + }; + }; +} FM_EXTI_TypeDef, FM4_EXTI_TypeDef; + +/******************************************************************************* +* FLASH_IF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t FASZR; + stc_flash_if_faszr_field_t FASZR_f; + struct { + union { + __IO uint16_t FASZRL; + struct { + __IO uint8_t FASZRLL; + __IO uint8_t FASZRLH; + }; + }; + union { + __IO uint16_t FASZRH; + struct { + __IO uint8_t FASZRHL; + __IO uint8_t FASZRHH; + }; + }; + }; + }; + union { + __IO uint32_t FRWTR; + stc_flash_if_frwtr_field_t FRWTR_f; + struct { + union { + __IO uint16_t FRWTRL; + struct { + __IO uint8_t FRWTRLL; + __IO uint8_t FRWTRLH; + }; + }; + union { + __IO uint16_t FRWTRH; + struct { + __IO uint8_t FRWTRHL; + __IO uint8_t FRWTRHH; + }; + }; + }; + }; + union { + __IO uint32_t FSTR; + stc_flash_if_fstr_field_t FSTR_f; + struct { + union { + __IO uint16_t FSTRL; + struct { + __IO uint8_t FSTRLL; + __IO uint8_t FSTRLH; + }; + }; + union { + __IO uint16_t FSTRH; + struct { + __IO uint8_t FSTRHL; + __IO uint8_t FSTRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t FSYNDN; + stc_flash_if_fsyndn_field_t FSYNDN_f; + struct { + union { + __IO uint16_t FSYNDNL; + struct { + __IO uint8_t FSYNDNLL; + __IO uint8_t FSYNDNLH; + }; + }; + union { + __IO uint16_t FSYNDNH; + struct { + __IO uint8_t FSYNDNHL; + __IO uint8_t FSYNDNHH; + }; + }; + }; + }; + union { + __IO uint32_t FBFCR; + stc_flash_if_fbfcr_field_t FBFCR_f; + struct { + union { + __IO uint16_t FBFCRL; + struct { + __IO uint8_t FBFCRLL; + __IO uint8_t FBFCRLH; + }; + }; + union { + __IO uint16_t FBFCRH; + struct { + __IO uint8_t FBFCRHL; + __IO uint8_t FBFCRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[8]; + union { + __IO uint32_t FICR; + stc_flash_if_ficr_field_t FICR_f; + struct { + union { + __IO uint16_t FICRL; + struct { + __IO uint8_t FICRLL; + __IO uint8_t FICRLH; + }; + }; + union { + __IO uint16_t FICRH; + struct { + __IO uint8_t FICRHL; + __IO uint8_t FICRHH; + }; + }; + }; + }; + union { + __IO uint32_t FISR; + stc_flash_if_fisr_field_t FISR_f; + struct { + union { + __IO uint16_t FISRL; + struct { + __IO uint8_t FISRLL; + __IO uint8_t FISRLH; + }; + }; + union { + __IO uint16_t FISRH; + struct { + __IO uint8_t FISRHL; + __IO uint8_t FISRHH; + }; + }; + }; + }; + union { + __IO uint32_t FICLR; + stc_flash_if_ficlr_field_t FICLR_f; + struct { + union { + __IO uint16_t FICLRL; + struct { + __IO uint8_t FICLRLL; + __IO uint8_t FICLRLH; + }; + }; + union { + __IO uint16_t FICLRH; + struct { + __IO uint8_t FICLRHL; + __IO uint8_t FICLRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[4]; + union { + __IO uint32_t DFCTRLR; + stc_flash_if_dfctrlr_field_t DFCTRLR_f; + struct { + union { + __IO uint16_t DFCTRLRL; + struct { + __IO uint8_t DFCTRLRLL; + __IO uint8_t DFCTRLRLH; + }; + }; + union { + __IO uint16_t DFCTRLRH; + struct { + __IO uint8_t DFCTRLRHL; + __IO uint8_t DFCTRLRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[204]; + union { + __IO uint32_t CRTRMM; + stc_flash_if_crtrmm_field_t CRTRMM_f; + struct { + union { + __IO uint16_t CRTRMML; + struct { + __IO uint8_t CRTRMMLL; + __IO uint8_t CRTRMMLH; + }; + }; + union { + __IO uint16_t CRTRMMH; + struct { + __IO uint8_t CRTRMMHL; + __IO uint8_t CRTRMMHH; + }; + }; + }; + }; + __IO uint8_t RESERVED4[12]; + union { + __IO uint32_t FGPDM1; + stc_flash_if_fgpdm1_field_t FGPDM1_f; + struct { + union { + __IO uint16_t FGPDM1L; + struct { + __IO uint8_t FGPDM1LL; + __IO uint8_t FGPDM1LH; + }; + }; + union { + __IO uint16_t FGPDM1H; + struct { + __IO uint8_t FGPDM1HL; + __IO uint8_t FGPDM1HH; + }; + }; + }; + }; + union { + __IO uint32_t FGPDM2; + stc_flash_if_fgpdm2_field_t FGPDM2_f; + struct { + union { + __IO uint16_t FGPDM2L; + struct { + __IO uint8_t FGPDM2LL; + __IO uint8_t FGPDM2LH; + }; + }; + union { + __IO uint16_t FGPDM2H; + struct { + __IO uint8_t FGPDM2HL; + __IO uint8_t FGPDM2HH; + }; + }; + }; + }; + union { + __IO uint32_t FGPDM3; + stc_flash_if_fgpdm3_field_t FGPDM3_f; + struct { + union { + __IO uint16_t FGPDM3L; + struct { + __IO uint8_t FGPDM3LL; + __IO uint8_t FGPDM3LH; + }; + }; + union { + __IO uint16_t FGPDM3H; + struct { + __IO uint8_t FGPDM3HL; + __IO uint8_t FGPDM3HH; + }; + }; + }; + }; + union { + __IO uint32_t FGPDM4; + stc_flash_if_fgpdm4_field_t FGPDM4_f; + struct { + union { + __IO uint16_t FGPDM4L; + struct { + __IO uint8_t FGPDM4LL; + __IO uint8_t FGPDM4LH; + }; + }; + union { + __IO uint16_t FGPDM4H; + struct { + __IO uint8_t FGPDM4HL; + __IO uint8_t FGPDM4HH; + }; + }; + }; + }; +} FM_FLASH_IF_TypeDef, FM4_FLASH_IF_TypeDef; + +/******************************************************************************* +* GPIO_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t PFR0; + stc_gpio_pfr0_field_t PFR0_f; + struct { + union { + __IO uint16_t PFR0L; + struct { + __IO uint8_t PFR0LL; + __IO uint8_t PFR0LH; + }; + }; + union { + __IO uint16_t PFR0H; + struct { + __IO uint8_t PFR0HL; + __IO uint8_t PFR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR1; + stc_gpio_pfr1_field_t PFR1_f; + struct { + union { + __IO uint16_t PFR1L; + struct { + __IO uint8_t PFR1LL; + __IO uint8_t PFR1LH; + }; + }; + union { + __IO uint16_t PFR1H; + struct { + __IO uint8_t PFR1HL; + __IO uint8_t PFR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR2; + stc_gpio_pfr2_field_t PFR2_f; + struct { + union { + __IO uint16_t PFR2L; + struct { + __IO uint8_t PFR2LL; + __IO uint8_t PFR2LH; + }; + }; + union { + __IO uint16_t PFR2H; + struct { + __IO uint8_t PFR2HL; + __IO uint8_t PFR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR3; + stc_gpio_pfr3_field_t PFR3_f; + struct { + union { + __IO uint16_t PFR3L; + struct { + __IO uint8_t PFR3LL; + __IO uint8_t PFR3LH; + }; + }; + union { + __IO uint16_t PFR3H; + struct { + __IO uint8_t PFR3HL; + __IO uint8_t PFR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR4; + stc_gpio_pfr4_field_t PFR4_f; + struct { + union { + __IO uint16_t PFR4L; + struct { + __IO uint8_t PFR4LL; + __IO uint8_t PFR4LH; + }; + }; + union { + __IO uint16_t PFR4H; + struct { + __IO uint8_t PFR4HL; + __IO uint8_t PFR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR5; + stc_gpio_pfr5_field_t PFR5_f; + struct { + union { + __IO uint16_t PFR5L; + struct { + __IO uint8_t PFR5LL; + __IO uint8_t PFR5LH; + }; + }; + union { + __IO uint16_t PFR5H; + struct { + __IO uint8_t PFR5HL; + __IO uint8_t PFR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR6; + stc_gpio_pfr6_field_t PFR6_f; + struct { + union { + __IO uint16_t PFR6L; + struct { + __IO uint8_t PFR6LL; + __IO uint8_t PFR6LH; + }; + }; + union { + __IO uint16_t PFR6H; + struct { + __IO uint8_t PFR6HL; + __IO uint8_t PFR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR7; + stc_gpio_pfr7_field_t PFR7_f; + struct { + union { + __IO uint16_t PFR7L; + struct { + __IO uint8_t PFR7LL; + __IO uint8_t PFR7LH; + }; + }; + union { + __IO uint16_t PFR7H; + struct { + __IO uint8_t PFR7HL; + __IO uint8_t PFR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR8; + stc_gpio_pfr8_field_t PFR8_f; + struct { + union { + __IO uint16_t PFR8L; + struct { + __IO uint8_t PFR8LL; + __IO uint8_t PFR8LH; + }; + }; + union { + __IO uint16_t PFR8H; + struct { + __IO uint8_t PFR8HL; + __IO uint8_t PFR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PFR9; + stc_gpio_pfr9_field_t PFR9_f; + struct { + union { + __IO uint16_t PFR9L; + struct { + __IO uint8_t PFR9LL; + __IO uint8_t PFR9LH; + }; + }; + union { + __IO uint16_t PFR9H; + struct { + __IO uint8_t PFR9HL; + __IO uint8_t PFR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PFRA; + stc_gpio_pfra_field_t PFRA_f; + struct { + union { + __IO uint16_t PFRAL; + struct { + __IO uint8_t PFRALL; + __IO uint8_t PFRALH; + }; + }; + union { + __IO uint16_t PFRAH; + struct { + __IO uint8_t PFRAHL; + __IO uint8_t PFRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRB; + stc_gpio_pfrb_field_t PFRB_f; + struct { + union { + __IO uint16_t PFRBL; + struct { + __IO uint8_t PFRBLL; + __IO uint8_t PFRBLH; + }; + }; + union { + __IO uint16_t PFRBH; + struct { + __IO uint8_t PFRBHL; + __IO uint8_t PFRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRC; + stc_gpio_pfrc_field_t PFRC_f; + struct { + union { + __IO uint16_t PFRCL; + struct { + __IO uint8_t PFRCLL; + __IO uint8_t PFRCLH; + }; + }; + union { + __IO uint16_t PFRCH; + struct { + __IO uint8_t PFRCHL; + __IO uint8_t PFRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRD; + stc_gpio_pfrd_field_t PFRD_f; + struct { + union { + __IO uint16_t PFRDL; + struct { + __IO uint8_t PFRDLL; + __IO uint8_t PFRDLH; + }; + }; + union { + __IO uint16_t PFRDH; + struct { + __IO uint8_t PFRDHL; + __IO uint8_t PFRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRE; + stc_gpio_pfre_field_t PFRE_f; + struct { + union { + __IO uint16_t PFREL; + struct { + __IO uint8_t PFRELL; + __IO uint8_t PFRELH; + }; + }; + union { + __IO uint16_t PFREH; + struct { + __IO uint8_t PFREHL; + __IO uint8_t PFREHH; + }; + }; + }; + }; + union { + __IO uint32_t PFRF; + stc_gpio_pfrf_field_t PFRF_f; + struct { + union { + __IO uint16_t PFRFL; + struct { + __IO uint8_t PFRFLL; + __IO uint8_t PFRFLH; + }; + }; + union { + __IO uint16_t PFRFH; + struct { + __IO uint8_t PFRFHL; + __IO uint8_t PFRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[192]; + union { + __IO uint32_t PCR0; + stc_gpio_pcr0_field_t PCR0_f; + struct { + union { + __IO uint16_t PCR0L; + struct { + __IO uint8_t PCR0LL; + __IO uint8_t PCR0LH; + }; + }; + union { + __IO uint16_t PCR0H; + struct { + __IO uint8_t PCR0HL; + __IO uint8_t PCR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR1; + stc_gpio_pcr1_field_t PCR1_f; + struct { + union { + __IO uint16_t PCR1L; + struct { + __IO uint8_t PCR1LL; + __IO uint8_t PCR1LH; + }; + }; + union { + __IO uint16_t PCR1H; + struct { + __IO uint8_t PCR1HL; + __IO uint8_t PCR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR2; + stc_gpio_pcr2_field_t PCR2_f; + struct { + union { + __IO uint16_t PCR2L; + struct { + __IO uint8_t PCR2LL; + __IO uint8_t PCR2LH; + }; + }; + union { + __IO uint16_t PCR2H; + struct { + __IO uint8_t PCR2HL; + __IO uint8_t PCR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR3; + stc_gpio_pcr3_field_t PCR3_f; + struct { + union { + __IO uint16_t PCR3L; + struct { + __IO uint8_t PCR3LL; + __IO uint8_t PCR3LH; + }; + }; + union { + __IO uint16_t PCR3H; + struct { + __IO uint8_t PCR3HL; + __IO uint8_t PCR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR4; + stc_gpio_pcr4_field_t PCR4_f; + struct { + union { + __IO uint16_t PCR4L; + struct { + __IO uint8_t PCR4LL; + __IO uint8_t PCR4LH; + }; + }; + union { + __IO uint16_t PCR4H; + struct { + __IO uint8_t PCR4HL; + __IO uint8_t PCR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR5; + stc_gpio_pcr5_field_t PCR5_f; + struct { + union { + __IO uint16_t PCR5L; + struct { + __IO uint8_t PCR5LL; + __IO uint8_t PCR5LH; + }; + }; + union { + __IO uint16_t PCR5H; + struct { + __IO uint8_t PCR5HL; + __IO uint8_t PCR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR6; + stc_gpio_pcr6_field_t PCR6_f; + struct { + union { + __IO uint16_t PCR6L; + struct { + __IO uint8_t PCR6LL; + __IO uint8_t PCR6LH; + }; + }; + union { + __IO uint16_t PCR6H; + struct { + __IO uint8_t PCR6HL; + __IO uint8_t PCR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PCR7; + stc_gpio_pcr7_field_t PCR7_f; + struct { + union { + __IO uint16_t PCR7L; + struct { + __IO uint8_t PCR7LL; + __IO uint8_t PCR7LH; + }; + }; + union { + __IO uint16_t PCR7H; + struct { + __IO uint8_t PCR7HL; + __IO uint8_t PCR7HH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[4]; + union { + __IO uint32_t PCR9; + stc_gpio_pcr9_field_t PCR9_f; + struct { + union { + __IO uint16_t PCR9L; + struct { + __IO uint8_t PCR9LL; + __IO uint8_t PCR9LH; + }; + }; + union { + __IO uint16_t PCR9H; + struct { + __IO uint8_t PCR9HL; + __IO uint8_t PCR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PCRA; + stc_gpio_pcra_field_t PCRA_f; + struct { + union { + __IO uint16_t PCRAL; + struct { + __IO uint8_t PCRALL; + __IO uint8_t PCRALH; + }; + }; + union { + __IO uint16_t PCRAH; + struct { + __IO uint8_t PCRAHL; + __IO uint8_t PCRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRB; + stc_gpio_pcrb_field_t PCRB_f; + struct { + union { + __IO uint16_t PCRBL; + struct { + __IO uint8_t PCRBLL; + __IO uint8_t PCRBLH; + }; + }; + union { + __IO uint16_t PCRBH; + struct { + __IO uint8_t PCRBHL; + __IO uint8_t PCRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC; + stc_gpio_pcrc_field_t PCRC_f; + struct { + union { + __IO uint16_t PCRCL; + struct { + __IO uint8_t PCRCLL; + __IO uint8_t PCRCLH; + }; + }; + union { + __IO uint16_t PCRCH; + struct { + __IO uint8_t PCRCHL; + __IO uint8_t PCRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRD; + stc_gpio_pcrd_field_t PCRD_f; + struct { + union { + __IO uint16_t PCRDL; + struct { + __IO uint8_t PCRDLL; + __IO uint8_t PCRDLH; + }; + }; + union { + __IO uint16_t PCRDH; + struct { + __IO uint8_t PCRDHL; + __IO uint8_t PCRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRE; + stc_gpio_pcre_field_t PCRE_f; + struct { + union { + __IO uint16_t PCREL; + struct { + __IO uint8_t PCRELL; + __IO uint8_t PCRELH; + }; + }; + union { + __IO uint16_t PCREH; + struct { + __IO uint8_t PCREHL; + __IO uint8_t PCREHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRF; + stc_gpio_pcrf_field_t PCRF_f; + struct { + union { + __IO uint16_t PCRFL; + struct { + __IO uint8_t PCRFLL; + __IO uint8_t PCRFLH; + }; + }; + union { + __IO uint16_t PCRFH; + struct { + __IO uint8_t PCRFHL; + __IO uint8_t PCRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[192]; + union { + __IO uint32_t DDR0; + stc_gpio_ddr0_field_t DDR0_f; + struct { + union { + __IO uint16_t DDR0L; + struct { + __IO uint8_t DDR0LL; + __IO uint8_t DDR0LH; + }; + }; + union { + __IO uint16_t DDR0H; + struct { + __IO uint8_t DDR0HL; + __IO uint8_t DDR0HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR1; + stc_gpio_ddr1_field_t DDR1_f; + struct { + union { + __IO uint16_t DDR1L; + struct { + __IO uint8_t DDR1LL; + __IO uint8_t DDR1LH; + }; + }; + union { + __IO uint16_t DDR1H; + struct { + __IO uint8_t DDR1HL; + __IO uint8_t DDR1HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR2; + stc_gpio_ddr2_field_t DDR2_f; + struct { + union { + __IO uint16_t DDR2L; + struct { + __IO uint8_t DDR2LL; + __IO uint8_t DDR2LH; + }; + }; + union { + __IO uint16_t DDR2H; + struct { + __IO uint8_t DDR2HL; + __IO uint8_t DDR2HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR3; + stc_gpio_ddr3_field_t DDR3_f; + struct { + union { + __IO uint16_t DDR3L; + struct { + __IO uint8_t DDR3LL; + __IO uint8_t DDR3LH; + }; + }; + union { + __IO uint16_t DDR3H; + struct { + __IO uint8_t DDR3HL; + __IO uint8_t DDR3HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR4; + stc_gpio_ddr4_field_t DDR4_f; + struct { + union { + __IO uint16_t DDR4L; + struct { + __IO uint8_t DDR4LL; + __IO uint8_t DDR4LH; + }; + }; + union { + __IO uint16_t DDR4H; + struct { + __IO uint8_t DDR4HL; + __IO uint8_t DDR4HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR5; + stc_gpio_ddr5_field_t DDR5_f; + struct { + union { + __IO uint16_t DDR5L; + struct { + __IO uint8_t DDR5LL; + __IO uint8_t DDR5LH; + }; + }; + union { + __IO uint16_t DDR5H; + struct { + __IO uint8_t DDR5HL; + __IO uint8_t DDR5HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR6; + stc_gpio_ddr6_field_t DDR6_f; + struct { + union { + __IO uint16_t DDR6L; + struct { + __IO uint8_t DDR6LL; + __IO uint8_t DDR6LH; + }; + }; + union { + __IO uint16_t DDR6H; + struct { + __IO uint8_t DDR6HL; + __IO uint8_t DDR6HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR7; + stc_gpio_ddr7_field_t DDR7_f; + struct { + union { + __IO uint16_t DDR7L; + struct { + __IO uint8_t DDR7LL; + __IO uint8_t DDR7LH; + }; + }; + union { + __IO uint16_t DDR7H; + struct { + __IO uint8_t DDR7HL; + __IO uint8_t DDR7HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR8; + stc_gpio_ddr8_field_t DDR8_f; + struct { + union { + __IO uint16_t DDR8L; + struct { + __IO uint8_t DDR8LL; + __IO uint8_t DDR8LH; + }; + }; + union { + __IO uint16_t DDR8H; + struct { + __IO uint8_t DDR8HL; + __IO uint8_t DDR8HH; + }; + }; + }; + }; + union { + __IO uint32_t DDR9; + stc_gpio_ddr9_field_t DDR9_f; + struct { + union { + __IO uint16_t DDR9L; + struct { + __IO uint8_t DDR9LL; + __IO uint8_t DDR9LH; + }; + }; + union { + __IO uint16_t DDR9H; + struct { + __IO uint8_t DDR9HL; + __IO uint8_t DDR9HH; + }; + }; + }; + }; + union { + __IO uint32_t DDRA; + stc_gpio_ddra_field_t DDRA_f; + struct { + union { + __IO uint16_t DDRAL; + struct { + __IO uint8_t DDRALL; + __IO uint8_t DDRALH; + }; + }; + union { + __IO uint16_t DDRAH; + struct { + __IO uint8_t DDRAHL; + __IO uint8_t DDRAHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRB; + stc_gpio_ddrb_field_t DDRB_f; + struct { + union { + __IO uint16_t DDRBL; + struct { + __IO uint8_t DDRBLL; + __IO uint8_t DDRBLH; + }; + }; + union { + __IO uint16_t DDRBH; + struct { + __IO uint8_t DDRBHL; + __IO uint8_t DDRBHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRC; + stc_gpio_ddrc_field_t DDRC_f; + struct { + union { + __IO uint16_t DDRCL; + struct { + __IO uint8_t DDRCLL; + __IO uint8_t DDRCLH; + }; + }; + union { + __IO uint16_t DDRCH; + struct { + __IO uint8_t DDRCHL; + __IO uint8_t DDRCHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRD; + stc_gpio_ddrd_field_t DDRD_f; + struct { + union { + __IO uint16_t DDRDL; + struct { + __IO uint8_t DDRDLL; + __IO uint8_t DDRDLH; + }; + }; + union { + __IO uint16_t DDRDH; + struct { + __IO uint8_t DDRDHL; + __IO uint8_t DDRDHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRE; + stc_gpio_ddre_field_t DDRE_f; + struct { + union { + __IO uint16_t DDREL; + struct { + __IO uint8_t DDRELL; + __IO uint8_t DDRELH; + }; + }; + union { + __IO uint16_t DDREH; + struct { + __IO uint8_t DDREHL; + __IO uint8_t DDREHH; + }; + }; + }; + }; + union { + __IO uint32_t DDRF; + stc_gpio_ddrf_field_t DDRF_f; + struct { + union { + __IO uint16_t DDRFL; + struct { + __IO uint8_t DDRFLL; + __IO uint8_t DDRFLH; + }; + }; + union { + __IO uint16_t DDRFH; + struct { + __IO uint8_t DDRFHL; + __IO uint8_t DDRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[192]; + union { + __IO uint32_t PDIR0; + stc_gpio_pdir0_field_t PDIR0_f; + struct { + union { + __IO uint16_t PDIR0L; + struct { + __IO uint8_t PDIR0LL; + __IO uint8_t PDIR0LH; + }; + }; + union { + __IO uint16_t PDIR0H; + struct { + __IO uint8_t PDIR0HL; + __IO uint8_t PDIR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR1; + stc_gpio_pdir1_field_t PDIR1_f; + struct { + union { + __IO uint16_t PDIR1L; + struct { + __IO uint8_t PDIR1LL; + __IO uint8_t PDIR1LH; + }; + }; + union { + __IO uint16_t PDIR1H; + struct { + __IO uint8_t PDIR1HL; + __IO uint8_t PDIR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR2; + stc_gpio_pdir2_field_t PDIR2_f; + struct { + union { + __IO uint16_t PDIR2L; + struct { + __IO uint8_t PDIR2LL; + __IO uint8_t PDIR2LH; + }; + }; + union { + __IO uint16_t PDIR2H; + struct { + __IO uint8_t PDIR2HL; + __IO uint8_t PDIR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR3; + stc_gpio_pdir3_field_t PDIR3_f; + struct { + union { + __IO uint16_t PDIR3L; + struct { + __IO uint8_t PDIR3LL; + __IO uint8_t PDIR3LH; + }; + }; + union { + __IO uint16_t PDIR3H; + struct { + __IO uint8_t PDIR3HL; + __IO uint8_t PDIR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR4; + stc_gpio_pdir4_field_t PDIR4_f; + struct { + union { + __IO uint16_t PDIR4L; + struct { + __IO uint8_t PDIR4LL; + __IO uint8_t PDIR4LH; + }; + }; + union { + __IO uint16_t PDIR4H; + struct { + __IO uint8_t PDIR4HL; + __IO uint8_t PDIR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR5; + stc_gpio_pdir5_field_t PDIR5_f; + struct { + union { + __IO uint16_t PDIR5L; + struct { + __IO uint8_t PDIR5LL; + __IO uint8_t PDIR5LH; + }; + }; + union { + __IO uint16_t PDIR5H; + struct { + __IO uint8_t PDIR5HL; + __IO uint8_t PDIR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR6; + stc_gpio_pdir6_field_t PDIR6_f; + struct { + union { + __IO uint16_t PDIR6L; + struct { + __IO uint8_t PDIR6LL; + __IO uint8_t PDIR6LH; + }; + }; + union { + __IO uint16_t PDIR6H; + struct { + __IO uint8_t PDIR6HL; + __IO uint8_t PDIR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR7; + stc_gpio_pdir7_field_t PDIR7_f; + struct { + union { + __IO uint16_t PDIR7L; + struct { + __IO uint8_t PDIR7LL; + __IO uint8_t PDIR7LH; + }; + }; + union { + __IO uint16_t PDIR7H; + struct { + __IO uint8_t PDIR7HL; + __IO uint8_t PDIR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR8; + stc_gpio_pdir8_field_t PDIR8_f; + struct { + union { + __IO uint16_t PDIR8L; + struct { + __IO uint8_t PDIR8LL; + __IO uint8_t PDIR8LH; + }; + }; + union { + __IO uint16_t PDIR8H; + struct { + __IO uint8_t PDIR8HL; + __IO uint8_t PDIR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIR9; + stc_gpio_pdir9_field_t PDIR9_f; + struct { + union { + __IO uint16_t PDIR9L; + struct { + __IO uint8_t PDIR9LL; + __IO uint8_t PDIR9LH; + }; + }; + union { + __IO uint16_t PDIR9H; + struct { + __IO uint8_t PDIR9HL; + __IO uint8_t PDIR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRA; + stc_gpio_pdira_field_t PDIRA_f; + struct { + union { + __IO uint16_t PDIRAL; + struct { + __IO uint8_t PDIRALL; + __IO uint8_t PDIRALH; + }; + }; + union { + __IO uint16_t PDIRAH; + struct { + __IO uint8_t PDIRAHL; + __IO uint8_t PDIRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRB; + stc_gpio_pdirb_field_t PDIRB_f; + struct { + union { + __IO uint16_t PDIRBL; + struct { + __IO uint8_t PDIRBLL; + __IO uint8_t PDIRBLH; + }; + }; + union { + __IO uint16_t PDIRBH; + struct { + __IO uint8_t PDIRBHL; + __IO uint8_t PDIRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRC; + stc_gpio_pdirc_field_t PDIRC_f; + struct { + union { + __IO uint16_t PDIRCL; + struct { + __IO uint8_t PDIRCLL; + __IO uint8_t PDIRCLH; + }; + }; + union { + __IO uint16_t PDIRCH; + struct { + __IO uint8_t PDIRCHL; + __IO uint8_t PDIRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRD; + stc_gpio_pdird_field_t PDIRD_f; + struct { + union { + __IO uint16_t PDIRDL; + struct { + __IO uint8_t PDIRDLL; + __IO uint8_t PDIRDLH; + }; + }; + union { + __IO uint16_t PDIRDH; + struct { + __IO uint8_t PDIRDHL; + __IO uint8_t PDIRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRE; + stc_gpio_pdire_field_t PDIRE_f; + struct { + union { + __IO uint16_t PDIREL; + struct { + __IO uint8_t PDIRELL; + __IO uint8_t PDIRELH; + }; + }; + union { + __IO uint16_t PDIREH; + struct { + __IO uint8_t PDIREHL; + __IO uint8_t PDIREHH; + }; + }; + }; + }; + union { + __IO uint32_t PDIRF; + stc_gpio_pdirf_field_t PDIRF_f; + struct { + union { + __IO uint16_t PDIRFL; + struct { + __IO uint8_t PDIRFLL; + __IO uint8_t PDIRFLH; + }; + }; + union { + __IO uint16_t PDIRFH; + struct { + __IO uint8_t PDIRFHL; + __IO uint8_t PDIRFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED4[192]; + union { + __IO uint32_t PDOR0; + stc_gpio_pdor0_field_t PDOR0_f; + struct { + union { + __IO uint16_t PDOR0L; + struct { + __IO uint8_t PDOR0LL; + __IO uint8_t PDOR0LH; + }; + }; + union { + __IO uint16_t PDOR0H; + struct { + __IO uint8_t PDOR0HL; + __IO uint8_t PDOR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR1; + stc_gpio_pdor1_field_t PDOR1_f; + struct { + union { + __IO uint16_t PDOR1L; + struct { + __IO uint8_t PDOR1LL; + __IO uint8_t PDOR1LH; + }; + }; + union { + __IO uint16_t PDOR1H; + struct { + __IO uint8_t PDOR1HL; + __IO uint8_t PDOR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR2; + stc_gpio_pdor2_field_t PDOR2_f; + struct { + union { + __IO uint16_t PDOR2L; + struct { + __IO uint8_t PDOR2LL; + __IO uint8_t PDOR2LH; + }; + }; + union { + __IO uint16_t PDOR2H; + struct { + __IO uint8_t PDOR2HL; + __IO uint8_t PDOR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR3; + stc_gpio_pdor3_field_t PDOR3_f; + struct { + union { + __IO uint16_t PDOR3L; + struct { + __IO uint8_t PDOR3LL; + __IO uint8_t PDOR3LH; + }; + }; + union { + __IO uint16_t PDOR3H; + struct { + __IO uint8_t PDOR3HL; + __IO uint8_t PDOR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR4; + stc_gpio_pdor4_field_t PDOR4_f; + struct { + union { + __IO uint16_t PDOR4L; + struct { + __IO uint8_t PDOR4LL; + __IO uint8_t PDOR4LH; + }; + }; + union { + __IO uint16_t PDOR4H; + struct { + __IO uint8_t PDOR4HL; + __IO uint8_t PDOR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR5; + stc_gpio_pdor5_field_t PDOR5_f; + struct { + union { + __IO uint16_t PDOR5L; + struct { + __IO uint8_t PDOR5LL; + __IO uint8_t PDOR5LH; + }; + }; + union { + __IO uint16_t PDOR5H; + struct { + __IO uint8_t PDOR5HL; + __IO uint8_t PDOR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR6; + stc_gpio_pdor6_field_t PDOR6_f; + struct { + union { + __IO uint16_t PDOR6L; + struct { + __IO uint8_t PDOR6LL; + __IO uint8_t PDOR6LH; + }; + }; + union { + __IO uint16_t PDOR6H; + struct { + __IO uint8_t PDOR6HL; + __IO uint8_t PDOR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR7; + stc_gpio_pdor7_field_t PDOR7_f; + struct { + union { + __IO uint16_t PDOR7L; + struct { + __IO uint8_t PDOR7LL; + __IO uint8_t PDOR7LH; + }; + }; + union { + __IO uint16_t PDOR7H; + struct { + __IO uint8_t PDOR7HL; + __IO uint8_t PDOR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR8; + stc_gpio_pdor8_field_t PDOR8_f; + struct { + union { + __IO uint16_t PDOR8L; + struct { + __IO uint8_t PDOR8LL; + __IO uint8_t PDOR8LH; + }; + }; + union { + __IO uint16_t PDOR8H; + struct { + __IO uint8_t PDOR8HL; + __IO uint8_t PDOR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PDOR9; + stc_gpio_pdor9_field_t PDOR9_f; + struct { + union { + __IO uint16_t PDOR9L; + struct { + __IO uint8_t PDOR9LL; + __IO uint8_t PDOR9LH; + }; + }; + union { + __IO uint16_t PDOR9H; + struct { + __IO uint8_t PDOR9HL; + __IO uint8_t PDOR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PDORA; + stc_gpio_pdora_field_t PDORA_f; + struct { + union { + __IO uint16_t PDORAL; + struct { + __IO uint8_t PDORALL; + __IO uint8_t PDORALH; + }; + }; + union { + __IO uint16_t PDORAH; + struct { + __IO uint8_t PDORAHL; + __IO uint8_t PDORAHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORB; + stc_gpio_pdorb_field_t PDORB_f; + struct { + union { + __IO uint16_t PDORBL; + struct { + __IO uint8_t PDORBLL; + __IO uint8_t PDORBLH; + }; + }; + union { + __IO uint16_t PDORBH; + struct { + __IO uint8_t PDORBHL; + __IO uint8_t PDORBHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORC; + stc_gpio_pdorc_field_t PDORC_f; + struct { + union { + __IO uint16_t PDORCL; + struct { + __IO uint8_t PDORCLL; + __IO uint8_t PDORCLH; + }; + }; + union { + __IO uint16_t PDORCH; + struct { + __IO uint8_t PDORCHL; + __IO uint8_t PDORCHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORD; + stc_gpio_pdord_field_t PDORD_f; + struct { + union { + __IO uint16_t PDORDL; + struct { + __IO uint8_t PDORDLL; + __IO uint8_t PDORDLH; + }; + }; + union { + __IO uint16_t PDORDH; + struct { + __IO uint8_t PDORDHL; + __IO uint8_t PDORDHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORE; + stc_gpio_pdore_field_t PDORE_f; + struct { + union { + __IO uint16_t PDOREL; + struct { + __IO uint8_t PDORELL; + __IO uint8_t PDORELH; + }; + }; + union { + __IO uint16_t PDOREH; + struct { + __IO uint8_t PDOREHL; + __IO uint8_t PDOREHH; + }; + }; + }; + }; + union { + __IO uint32_t PDORF; + stc_gpio_pdorf_field_t PDORF_f; + struct { + union { + __IO uint16_t PDORFL; + struct { + __IO uint8_t PDORFLL; + __IO uint8_t PDORFLH; + }; + }; + union { + __IO uint16_t PDORFH; + struct { + __IO uint8_t PDORFHL; + __IO uint8_t PDORFHH; + }; + }; + }; + }; + __IO uint8_t RESERVED5[192]; + union { + __IO uint32_t ADE; + stc_gpio_ade_field_t ADE_f; + struct { + union { + __IO uint16_t ADEL; + struct { + __IO uint8_t ADELL; + __IO uint8_t ADELH; + }; + }; + union { + __IO uint16_t ADEH; + struct { + __IO uint8_t ADEHL; + __IO uint8_t ADEHH; + }; + }; + }; + }; + __IO uint8_t RESERVED6[124]; + union { + __IO uint32_t SPSR; + stc_gpio_spsr_field_t SPSR_f; + struct { + union { + __IO uint16_t SPSRL; + struct { + __IO uint8_t SPSRLL; + __IO uint8_t SPSRLH; + }; + }; + union { + __IO uint16_t SPSRH; + struct { + __IO uint8_t SPSRHL; + __IO uint8_t SPSRHH; + }; + }; + }; + }; + __IO uint8_t RESERVED7[124]; + union { + __IO uint32_t EPFR00; + stc_gpio_epfr00_field_t EPFR00_f; + struct { + union { + __IO uint16_t EPFR00L; + struct { + __IO uint8_t EPFR00LL; + __IO uint8_t EPFR00LH; + }; + }; + union { + __IO uint16_t EPFR00H; + struct { + __IO uint8_t EPFR00HL; + __IO uint8_t EPFR00HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR01; + stc_gpio_epfr01_field_t EPFR01_f; + struct { + union { + __IO uint16_t EPFR01L; + struct { + __IO uint8_t EPFR01LL; + __IO uint8_t EPFR01LH; + }; + }; + union { + __IO uint16_t EPFR01H; + struct { + __IO uint8_t EPFR01HL; + __IO uint8_t EPFR01HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR02; + stc_gpio_epfr02_field_t EPFR02_f; + struct { + union { + __IO uint16_t EPFR02L; + struct { + __IO uint8_t EPFR02LL; + __IO uint8_t EPFR02LH; + }; + }; + union { + __IO uint16_t EPFR02H; + struct { + __IO uint8_t EPFR02HL; + __IO uint8_t EPFR02HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR03; + stc_gpio_epfr03_field_t EPFR03_f; + struct { + union { + __IO uint16_t EPFR03L; + struct { + __IO uint8_t EPFR03LL; + __IO uint8_t EPFR03LH; + }; + }; + union { + __IO uint16_t EPFR03H; + struct { + __IO uint8_t EPFR03HL; + __IO uint8_t EPFR03HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR04; + stc_gpio_epfr04_field_t EPFR04_f; + struct { + union { + __IO uint16_t EPFR04L; + struct { + __IO uint8_t EPFR04LL; + __IO uint8_t EPFR04LH; + }; + }; + union { + __IO uint16_t EPFR04H; + struct { + __IO uint8_t EPFR04HL; + __IO uint8_t EPFR04HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR05; + stc_gpio_epfr05_field_t EPFR05_f; + struct { + union { + __IO uint16_t EPFR05L; + struct { + __IO uint8_t EPFR05LL; + __IO uint8_t EPFR05LH; + }; + }; + union { + __IO uint16_t EPFR05H; + struct { + __IO uint8_t EPFR05HL; + __IO uint8_t EPFR05HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR06; + stc_gpio_epfr06_field_t EPFR06_f; + struct { + union { + __IO uint16_t EPFR06L; + struct { + __IO uint8_t EPFR06LL; + __IO uint8_t EPFR06LH; + }; + }; + union { + __IO uint16_t EPFR06H; + struct { + __IO uint8_t EPFR06HL; + __IO uint8_t EPFR06HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR07; + stc_gpio_epfr07_field_t EPFR07_f; + struct { + union { + __IO uint16_t EPFR07L; + struct { + __IO uint8_t EPFR07LL; + __IO uint8_t EPFR07LH; + }; + }; + union { + __IO uint16_t EPFR07H; + struct { + __IO uint8_t EPFR07HL; + __IO uint8_t EPFR07HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR08; + stc_gpio_epfr08_field_t EPFR08_f; + struct { + union { + __IO uint16_t EPFR08L; + struct { + __IO uint8_t EPFR08LL; + __IO uint8_t EPFR08LH; + }; + }; + union { + __IO uint16_t EPFR08H; + struct { + __IO uint8_t EPFR08HL; + __IO uint8_t EPFR08HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR09; + stc_gpio_epfr09_field_t EPFR09_f; + struct { + union { + __IO uint16_t EPFR09L; + struct { + __IO uint8_t EPFR09LL; + __IO uint8_t EPFR09LH; + }; + }; + union { + __IO uint16_t EPFR09H; + struct { + __IO uint8_t EPFR09HL; + __IO uint8_t EPFR09HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR10; + stc_gpio_epfr10_field_t EPFR10_f; + struct { + union { + __IO uint16_t EPFR10L; + struct { + __IO uint8_t EPFR10LL; + __IO uint8_t EPFR10LH; + }; + }; + union { + __IO uint16_t EPFR10H; + struct { + __IO uint8_t EPFR10HL; + __IO uint8_t EPFR10HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR11; + stc_gpio_epfr11_field_t EPFR11_f; + struct { + union { + __IO uint16_t EPFR11L; + struct { + __IO uint8_t EPFR11LL; + __IO uint8_t EPFR11LH; + }; + }; + union { + __IO uint16_t EPFR11H; + struct { + __IO uint8_t EPFR11HL; + __IO uint8_t EPFR11HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR12; + stc_gpio_epfr12_field_t EPFR12_f; + struct { + union { + __IO uint16_t EPFR12L; + struct { + __IO uint8_t EPFR12LL; + __IO uint8_t EPFR12LH; + }; + }; + union { + __IO uint16_t EPFR12H; + struct { + __IO uint8_t EPFR12HL; + __IO uint8_t EPFR12HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR13; + stc_gpio_epfr13_field_t EPFR13_f; + struct { + union { + __IO uint16_t EPFR13L; + struct { + __IO uint8_t EPFR13LL; + __IO uint8_t EPFR13LH; + }; + }; + union { + __IO uint16_t EPFR13H; + struct { + __IO uint8_t EPFR13HL; + __IO uint8_t EPFR13HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR14; + stc_gpio_epfr14_field_t EPFR14_f; + struct { + union { + __IO uint16_t EPFR14L; + struct { + __IO uint8_t EPFR14LL; + __IO uint8_t EPFR14LH; + }; + }; + union { + __IO uint16_t EPFR14H; + struct { + __IO uint8_t EPFR14HL; + __IO uint8_t EPFR14HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR15; + stc_gpio_epfr15_field_t EPFR15_f; + struct { + union { + __IO uint16_t EPFR15L; + struct { + __IO uint8_t EPFR15LL; + __IO uint8_t EPFR15LH; + }; + }; + union { + __IO uint16_t EPFR15H; + struct { + __IO uint8_t EPFR15HL; + __IO uint8_t EPFR15HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR16; + stc_gpio_epfr16_field_t EPFR16_f; + struct { + union { + __IO uint16_t EPFR16L; + struct { + __IO uint8_t EPFR16LL; + __IO uint8_t EPFR16LH; + }; + }; + union { + __IO uint16_t EPFR16H; + struct { + __IO uint8_t EPFR16HL; + __IO uint8_t EPFR16HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR17; + stc_gpio_epfr17_field_t EPFR17_f; + struct { + union { + __IO uint16_t EPFR17L; + struct { + __IO uint8_t EPFR17LL; + __IO uint8_t EPFR17LH; + }; + }; + union { + __IO uint16_t EPFR17H; + struct { + __IO uint8_t EPFR17HL; + __IO uint8_t EPFR17HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR18; + stc_gpio_epfr18_field_t EPFR18_f; + struct { + union { + __IO uint16_t EPFR18L; + struct { + __IO uint8_t EPFR18LL; + __IO uint8_t EPFR18LH; + }; + }; + union { + __IO uint16_t EPFR18H; + struct { + __IO uint8_t EPFR18HL; + __IO uint8_t EPFR18HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR19; + struct { + union { + __IO uint16_t EPFR19L; + struct { + __IO uint8_t EPFR19LL; + __IO uint8_t EPFR19LH; + }; + }; + union { + __IO uint16_t EPFR19H; + struct { + __IO uint8_t EPFR19HL; + __IO uint8_t EPFR19HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR20; + stc_gpio_epfr20_field_t EPFR20_f; + struct { + union { + __IO uint16_t EPFR20L; + struct { + __IO uint8_t EPFR20LL; + __IO uint8_t EPFR20LH; + }; + }; + union { + __IO uint16_t EPFR20H; + struct { + __IO uint8_t EPFR20HL; + __IO uint8_t EPFR20HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR21; + struct { + union { + __IO uint16_t EPFR21L; + struct { + __IO uint8_t EPFR21LL; + __IO uint8_t EPFR21LH; + }; + }; + union { + __IO uint16_t EPFR21H; + struct { + __IO uint8_t EPFR21HL; + __IO uint8_t EPFR21HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR22; + struct { + union { + __IO uint16_t EPFR22L; + struct { + __IO uint8_t EPFR22LL; + __IO uint8_t EPFR22LH; + }; + }; + union { + __IO uint16_t EPFR22H; + struct { + __IO uint8_t EPFR22HL; + __IO uint8_t EPFR22HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR23; + stc_gpio_epfr23_field_t EPFR23_f; + struct { + union { + __IO uint16_t EPFR23L; + struct { + __IO uint8_t EPFR23LL; + __IO uint8_t EPFR23LH; + }; + }; + union { + __IO uint16_t EPFR23H; + struct { + __IO uint8_t EPFR23HL; + __IO uint8_t EPFR23HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR24; + stc_gpio_epfr24_field_t EPFR24_f; + struct { + union { + __IO uint16_t EPFR24L; + struct { + __IO uint8_t EPFR24LL; + __IO uint8_t EPFR24LH; + }; + }; + union { + __IO uint16_t EPFR24H; + struct { + __IO uint8_t EPFR24HL; + __IO uint8_t EPFR24HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR25; + stc_gpio_epfr25_field_t EPFR25_f; + struct { + union { + __IO uint16_t EPFR25L; + struct { + __IO uint8_t EPFR25LL; + __IO uint8_t EPFR25LH; + }; + }; + union { + __IO uint16_t EPFR25H; + struct { + __IO uint8_t EPFR25HL; + __IO uint8_t EPFR25HH; + }; + }; + }; + }; + union { + __IO uint32_t EPFR26; + stc_gpio_epfr26_field_t EPFR26_f; + struct { + union { + __IO uint16_t EPFR26L; + struct { + __IO uint8_t EPFR26LL; + __IO uint8_t EPFR26LH; + }; + }; + union { + __IO uint16_t EPFR26H; + struct { + __IO uint8_t EPFR26HL; + __IO uint8_t EPFR26HH; + }; + }; + }; + }; + __IO uint8_t RESERVED8[148]; + union { + __IO uint32_t PZR0; + stc_gpio_pzr0_field_t PZR0_f; + struct { + union { + __IO uint16_t PZR0L; + struct { + __IO uint8_t PZR0LL; + __IO uint8_t PZR0LH; + }; + }; + union { + __IO uint16_t PZR0H; + struct { + __IO uint8_t PZR0HL; + __IO uint8_t PZR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR1; + stc_gpio_pzr1_field_t PZR1_f; + struct { + union { + __IO uint16_t PZR1L; + struct { + __IO uint8_t PZR1LL; + __IO uint8_t PZR1LH; + }; + }; + union { + __IO uint16_t PZR1H; + struct { + __IO uint8_t PZR1HL; + __IO uint8_t PZR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR2; + stc_gpio_pzr2_field_t PZR2_f; + struct { + union { + __IO uint16_t PZR2L; + struct { + __IO uint8_t PZR2LL; + __IO uint8_t PZR2LH; + }; + }; + union { + __IO uint16_t PZR2H; + struct { + __IO uint8_t PZR2HL; + __IO uint8_t PZR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR3; + stc_gpio_pzr3_field_t PZR3_f; + struct { + union { + __IO uint16_t PZR3L; + struct { + __IO uint8_t PZR3LL; + __IO uint8_t PZR3LH; + }; + }; + union { + __IO uint16_t PZR3H; + struct { + __IO uint8_t PZR3HL; + __IO uint8_t PZR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR4; + stc_gpio_pzr4_field_t PZR4_f; + struct { + union { + __IO uint16_t PZR4L; + struct { + __IO uint8_t PZR4LL; + __IO uint8_t PZR4LH; + }; + }; + union { + __IO uint16_t PZR4H; + struct { + __IO uint8_t PZR4HL; + __IO uint8_t PZR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR5; + stc_gpio_pzr5_field_t PZR5_f; + struct { + union { + __IO uint16_t PZR5L; + struct { + __IO uint8_t PZR5LL; + __IO uint8_t PZR5LH; + }; + }; + union { + __IO uint16_t PZR5H; + struct { + __IO uint8_t PZR5HL; + __IO uint8_t PZR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR6; + stc_gpio_pzr6_field_t PZR6_f; + struct { + union { + __IO uint16_t PZR6L; + struct { + __IO uint8_t PZR6LL; + __IO uint8_t PZR6LH; + }; + }; + union { + __IO uint16_t PZR6H; + struct { + __IO uint8_t PZR6HL; + __IO uint8_t PZR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR7; + stc_gpio_pzr7_field_t PZR7_f; + struct { + union { + __IO uint16_t PZR7L; + struct { + __IO uint8_t PZR7LL; + __IO uint8_t PZR7LH; + }; + }; + union { + __IO uint16_t PZR7H; + struct { + __IO uint8_t PZR7HL; + __IO uint8_t PZR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR8; + stc_gpio_pzr8_field_t PZR8_f; + struct { + union { + __IO uint16_t PZR8L; + struct { + __IO uint8_t PZR8LL; + __IO uint8_t PZR8LH; + }; + }; + union { + __IO uint16_t PZR8H; + struct { + __IO uint8_t PZR8HL; + __IO uint8_t PZR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PZR9; + stc_gpio_pzr9_field_t PZR9_f; + struct { + union { + __IO uint16_t PZR9L; + struct { + __IO uint8_t PZR9LL; + __IO uint8_t PZR9LH; + }; + }; + union { + __IO uint16_t PZR9H; + struct { + __IO uint8_t PZR9HL; + __IO uint8_t PZR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PZRA; + stc_gpio_pzra_field_t PZRA_f; + struct { + union { + __IO uint16_t PZRAL; + struct { + __IO uint8_t PZRALL; + __IO uint8_t PZRALH; + }; + }; + union { + __IO uint16_t PZRAH; + struct { + __IO uint8_t PZRAHL; + __IO uint8_t PZRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRB; + stc_gpio_pzrb_field_t PZRB_f; + struct { + union { + __IO uint16_t PZRBL; + struct { + __IO uint8_t PZRBLL; + __IO uint8_t PZRBLH; + }; + }; + union { + __IO uint16_t PZRBH; + struct { + __IO uint8_t PZRBHL; + __IO uint8_t PZRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRC; + stc_gpio_pzrc_field_t PZRC_f; + struct { + union { + __IO uint16_t PZRCL; + struct { + __IO uint8_t PZRCLL; + __IO uint8_t PZRCLH; + }; + }; + union { + __IO uint16_t PZRCH; + struct { + __IO uint8_t PZRCHL; + __IO uint8_t PZRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRD; + stc_gpio_pzrd_field_t PZRD_f; + struct { + union { + __IO uint16_t PZRDL; + struct { + __IO uint8_t PZRDLL; + __IO uint8_t PZRDLH; + }; + }; + union { + __IO uint16_t PZRDH; + struct { + __IO uint8_t PZRDHL; + __IO uint8_t PZRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRE; + stc_gpio_pzre_field_t PZRE_f; + struct { + union { + __IO uint16_t PZREL; + struct { + __IO uint8_t PZRELL; + __IO uint8_t PZRELH; + }; + }; + union { + __IO uint16_t PZREH; + struct { + __IO uint8_t PZREHL; + __IO uint8_t PZREHH; + }; + }; + }; + }; + union { + __IO uint32_t PZRF; + stc_gpio_pzrf_field_t PZRF_f; + struct { + union { + __IO uint16_t PZRFL; + struct { + __IO uint8_t PZRFLL; + __IO uint8_t PZRFLH; + }; + }; + union { + __IO uint16_t PZRFH; + struct { + __IO uint8_t PZRFHL; + __IO uint8_t PZRFHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR0; + stc_gpio_pdsr0_field_t PDSR0_f; + struct { + union { + __IO uint16_t PDSR0L; + struct { + __IO uint8_t PDSR0LL; + __IO uint8_t PDSR0LH; + }; + }; + union { + __IO uint16_t PDSR0H; + struct { + __IO uint8_t PDSR0HL; + __IO uint8_t PDSR0HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR1; + stc_gpio_pdsr1_field_t PDSR1_f; + struct { + union { + __IO uint16_t PDSR1L; + struct { + __IO uint8_t PDSR1LL; + __IO uint8_t PDSR1LH; + }; + }; + union { + __IO uint16_t PDSR1H; + struct { + __IO uint8_t PDSR1HL; + __IO uint8_t PDSR1HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR2; + stc_gpio_pdsr2_field_t PDSR2_f; + struct { + union { + __IO uint16_t PDSR2L; + struct { + __IO uint8_t PDSR2LL; + __IO uint8_t PDSR2LH; + }; + }; + union { + __IO uint16_t PDSR2H; + struct { + __IO uint8_t PDSR2HL; + __IO uint8_t PDSR2HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR3; + stc_gpio_pdsr3_field_t PDSR3_f; + struct { + union { + __IO uint16_t PDSR3L; + struct { + __IO uint8_t PDSR3LL; + __IO uint8_t PDSR3LH; + }; + }; + union { + __IO uint16_t PDSR3H; + struct { + __IO uint8_t PDSR3HL; + __IO uint8_t PDSR3HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR4; + stc_gpio_pdsr4_field_t PDSR4_f; + struct { + union { + __IO uint16_t PDSR4L; + struct { + __IO uint8_t PDSR4LL; + __IO uint8_t PDSR4LH; + }; + }; + union { + __IO uint16_t PDSR4H; + struct { + __IO uint8_t PDSR4HL; + __IO uint8_t PDSR4HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR5; + stc_gpio_pdsr5_field_t PDSR5_f; + struct { + union { + __IO uint16_t PDSR5L; + struct { + __IO uint8_t PDSR5LL; + __IO uint8_t PDSR5LH; + }; + }; + union { + __IO uint16_t PDSR5H; + struct { + __IO uint8_t PDSR5HL; + __IO uint8_t PDSR5HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR6; + stc_gpio_pdsr6_field_t PDSR6_f; + struct { + union { + __IO uint16_t PDSR6L; + struct { + __IO uint8_t PDSR6LL; + __IO uint8_t PDSR6LH; + }; + }; + union { + __IO uint16_t PDSR6H; + struct { + __IO uint8_t PDSR6HL; + __IO uint8_t PDSR6HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR7; + stc_gpio_pdsr7_field_t PDSR7_f; + struct { + union { + __IO uint16_t PDSR7L; + struct { + __IO uint8_t PDSR7LL; + __IO uint8_t PDSR7LH; + }; + }; + union { + __IO uint16_t PDSR7H; + struct { + __IO uint8_t PDSR7HL; + __IO uint8_t PDSR7HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR8; + stc_gpio_pdsr8_field_t PDSR8_f; + struct { + union { + __IO uint16_t PDSR8L; + struct { + __IO uint8_t PDSR8LL; + __IO uint8_t PDSR8LH; + }; + }; + union { + __IO uint16_t PDSR8H; + struct { + __IO uint8_t PDSR8HL; + __IO uint8_t PDSR8HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSR9; + stc_gpio_pdsr9_field_t PDSR9_f; + struct { + union { + __IO uint16_t PDSR9L; + struct { + __IO uint8_t PDSR9LL; + __IO uint8_t PDSR9LH; + }; + }; + union { + __IO uint16_t PDSR9H; + struct { + __IO uint8_t PDSR9HL; + __IO uint8_t PDSR9HH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRA; + stc_gpio_pdsra_field_t PDSRA_f; + struct { + union { + __IO uint16_t PDSRAL; + struct { + __IO uint8_t PDSRALL; + __IO uint8_t PDSRALH; + }; + }; + union { + __IO uint16_t PDSRAH; + struct { + __IO uint8_t PDSRAHL; + __IO uint8_t PDSRAHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRB; + stc_gpio_pdsrb_field_t PDSRB_f; + struct { + union { + __IO uint16_t PDSRBL; + struct { + __IO uint8_t PDSRBLL; + __IO uint8_t PDSRBLH; + }; + }; + union { + __IO uint16_t PDSRBH; + struct { + __IO uint8_t PDSRBHL; + __IO uint8_t PDSRBHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRC; + stc_gpio_pdsrc_field_t PDSRC_f; + struct { + union { + __IO uint16_t PDSRCL; + struct { + __IO uint8_t PDSRCLL; + __IO uint8_t PDSRCLH; + }; + }; + union { + __IO uint16_t PDSRCH; + struct { + __IO uint8_t PDSRCHL; + __IO uint8_t PDSRCHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRD; + stc_gpio_pdsrd_field_t PDSRD_f; + struct { + union { + __IO uint16_t PDSRDL; + struct { + __IO uint8_t PDSRDLL; + __IO uint8_t PDSRDLH; + }; + }; + union { + __IO uint16_t PDSRDH; + struct { + __IO uint8_t PDSRDHL; + __IO uint8_t PDSRDHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRE; + stc_gpio_pdsre_field_t PDSRE_f; + struct { + union { + __IO uint16_t PDSREL; + struct { + __IO uint8_t PDSRELL; + __IO uint8_t PDSRELH; + }; + }; + union { + __IO uint16_t PDSREH; + struct { + __IO uint8_t PDSREHL; + __IO uint8_t PDSREHH; + }; + }; + }; + }; + union { + __IO uint32_t PDSRF; + stc_gpio_pdsrf_field_t PDSRF_f; + struct { + union { + __IO uint16_t PDSRFL; + struct { + __IO uint8_t PDSRFLL; + __IO uint8_t PDSRFLH; + }; + }; + union { + __IO uint16_t PDSRFH; + struct { + __IO uint8_t PDSRFHL; + __IO uint8_t PDSRFHH; + }; + }; + }; + }; +} FM_GPIO_TypeDef, FM4_GPIO_TypeDef; + +/******************************************************************************* +* HSSPI_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t MCTRL; + stc_hsspi_mctrl_field_t MCTRL_f; + struct { + union { + __IO uint16_t MCTRLL; + struct { + __IO uint8_t MCTRLLL; + __IO uint8_t MCTRLLH; + }; + }; + union { + __IO uint16_t MCTRLH; + struct { + __IO uint8_t MCTRLHL; + __IO uint8_t MCTRLHH; + }; + }; + }; + }; + union { + __IO uint32_t PCC0; + stc_hsspi_pcc0_field_t PCC0_f; + struct { + union { + __IO uint16_t PCC0L; + struct { + __IO uint8_t PCC0LL; + __IO uint8_t PCC0LH; + }; + }; + union { + __IO uint16_t PCC0H; + struct { + __IO uint8_t PCC0HL; + __IO uint8_t PCC0HH; + }; + }; + }; + }; + union { + __IO uint32_t PCC1; + stc_hsspi_pcc1_field_t PCC1_f; + struct { + union { + __IO uint16_t PCC1L; + struct { + __IO uint8_t PCC1LL; + __IO uint8_t PCC1LH; + }; + }; + union { + __IO uint16_t PCC1H; + struct { + __IO uint8_t PCC1HL; + __IO uint8_t PCC1HH; + }; + }; + }; + }; + union { + __IO uint32_t PCC2; + stc_hsspi_pcc2_field_t PCC2_f; + struct { + union { + __IO uint16_t PCC2L; + struct { + __IO uint8_t PCC2LL; + __IO uint8_t PCC2LH; + }; + }; + union { + __IO uint16_t PCC2H; + struct { + __IO uint8_t PCC2HL; + __IO uint8_t PCC2HH; + }; + }; + }; + }; + union { + __IO uint32_t PCC3; + stc_hsspi_pcc3_field_t PCC3_f; + struct { + union { + __IO uint16_t PCC3L; + struct { + __IO uint8_t PCC3LL; + __IO uint8_t PCC3LH; + }; + }; + union { + __IO uint16_t PCC3H; + struct { + __IO uint8_t PCC3HL; + __IO uint8_t PCC3HH; + }; + }; + }; + }; + union { + __IO uint32_t TXF; + stc_hsspi_txf_field_t TXF_f; + struct { + union { + __IO uint16_t TXFL; + struct { + __IO uint8_t TXFLL; + __IO uint8_t TXFLH; + }; + }; + union { + __IO uint16_t TXFH; + struct { + __IO uint8_t TXFHL; + __IO uint8_t TXFHH; + }; + }; + }; + }; + union { + __IO uint32_t TXE; + stc_hsspi_txe_field_t TXE_f; + struct { + union { + __IO uint16_t TXEL; + struct { + __IO uint8_t TXELL; + __IO uint8_t TXELH; + }; + }; + union { + __IO uint16_t TXEH; + struct { + __IO uint8_t TXEHL; + __IO uint8_t TXEHH; + }; + }; + }; + }; + union { + __IO uint32_t TXC; + stc_hsspi_txc_field_t TXC_f; + struct { + union { + __IO uint16_t TXCL; + struct { + __IO uint8_t TXCLL; + __IO uint8_t TXCLH; + }; + }; + union { + __IO uint16_t TXCH; + struct { + __IO uint8_t TXCHL; + __IO uint8_t TXCHH; + }; + }; + }; + }; + union { + __IO uint32_t RXF; + stc_hsspi_rxf_field_t RXF_f; + struct { + union { + __IO uint16_t RXFL; + struct { + __IO uint8_t RXFLL; + __IO uint8_t RXFLH; + }; + }; + union { + __IO uint16_t RXFH; + struct { + __IO uint8_t RXFHL; + __IO uint8_t RXFHH; + }; + }; + }; + }; + union { + __IO uint32_t RXE; + stc_hsspi_rxe_field_t RXE_f; + struct { + union { + __IO uint16_t RXEL; + struct { + __IO uint8_t RXELL; + __IO uint8_t RXELH; + }; + }; + union { + __IO uint16_t RXEH; + struct { + __IO uint8_t RXEHL; + __IO uint8_t RXEHH; + }; + }; + }; + }; + union { + __IO uint32_t RXC; + stc_hsspi_rxc_field_t RXC_f; + struct { + union { + __IO uint16_t RXCL; + struct { + __IO uint8_t RXCLL; + __IO uint8_t RXCLH; + }; + }; + union { + __IO uint16_t RXCH; + struct { + __IO uint8_t RXCHL; + __IO uint8_t RXCHH; + }; + }; + }; + }; + union { + __IO uint32_t FAULTF; + stc_hsspi_faultf_field_t FAULTF_f; + struct { + union { + __IO uint16_t FAULTFL; + struct { + __IO uint8_t FAULTFLL; + __IO uint8_t FAULTFLH; + }; + }; + union { + __IO uint16_t FAULTFH; + struct { + __IO uint8_t FAULTFHL; + __IO uint8_t FAULTFHH; + }; + }; + }; + }; + union { + __IO uint32_t FAULTC; + stc_hsspi_faultc_field_t FAULTC_f; + struct { + union { + __IO uint16_t FAULTCL; + struct { + __IO uint8_t FAULTCLL; + __IO uint8_t FAULTCLH; + }; + }; + union { + __IO uint16_t FAULTCH; + struct { + __IO uint8_t FAULTCHL; + __IO uint8_t FAULTCHH; + }; + }; + }; + }; + union { + __IO uint8_t DMCFG; + stc_hsspi_dmcfg_field_t DMCFG_f; + }; + union { + __IO uint8_t DMDMAEN; + stc_hsspi_dmdmaen_field_t DMDMAEN_f; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint8_t DMSTART; + stc_hsspi_dmstart_field_t DMSTART_f; + }; + union { + __IO uint8_t DMSTOP; + stc_hsspi_dmstop_field_t DMSTOP_f; + }; + union { + __IO uint8_t DMPSEL; + stc_hsspi_dmpsel_field_t DMPSEL_f; + }; + union { + __IO uint8_t DMTRP; + stc_hsspi_dmtrp_field_t DMTRP_f; + }; + union { + __IO uint16_t DMBCC; + stc_hsspi_dmbcc_field_t DMBCC_f; + struct { + __IO uint8_t DMBCCL; + __IO uint8_t DMBCCH; + }; + }; + union { + __IO uint16_t DMBCS; + stc_hsspi_dmbcs_field_t DMBCS_f; + struct { + __IO uint8_t DMBCSL; + __IO uint8_t DMBCSH; + }; + }; + union { + __IO uint32_t DMSTATUS; + stc_hsspi_dmstatus_field_t DMSTATUS_f; + struct { + union { + __IO uint16_t DMSTATUSL; + struct { + __IO uint8_t DMSTATUSLL; + __IO uint8_t DMSTATUSLH; + }; + }; + union { + __IO uint16_t DMSTATUSH; + struct { + __IO uint8_t DMSTATUSHL; + __IO uint8_t DMSTATUSHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[8]; + union { + __IO uint32_t FIFOCFG; + stc_hsspi_fifocfg_field_t FIFOCFG_f; + struct { + union { + __IO uint16_t FIFOCFGL; + struct { + __IO uint8_t FIFOCFGLL; + __IO uint8_t FIFOCFGLH; + }; + }; + union { + __IO uint16_t FIFOCFGH; + struct { + __IO uint8_t FIFOCFGHL; + __IO uint8_t FIFOCFGHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO0; + stc_hsspi_txfifo0_field_t TXFIFO0_f; + struct { + union { + __IO uint16_t TXFIFO0L; + struct { + __IO uint8_t TXFIFO0LL; + __IO uint8_t TXFIFO0LH; + }; + }; + union { + __IO uint16_t TXFIFO0H; + struct { + __IO uint8_t TXFIFO0HL; + __IO uint8_t TXFIFO0HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO1; + stc_hsspi_txfifo1_field_t TXFIFO1_f; + struct { + union { + __IO uint16_t TXFIFO1L; + struct { + __IO uint8_t TXFIFO1LL; + __IO uint8_t TXFIFO1LH; + }; + }; + union { + __IO uint16_t TXFIFO1H; + struct { + __IO uint8_t TXFIFO1HL; + __IO uint8_t TXFIFO1HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO2; + stc_hsspi_txfifo2_field_t TXFIFO2_f; + struct { + union { + __IO uint16_t TXFIFO2L; + struct { + __IO uint8_t TXFIFO2LL; + __IO uint8_t TXFIFO2LH; + }; + }; + union { + __IO uint16_t TXFIFO2H; + struct { + __IO uint8_t TXFIFO2HL; + __IO uint8_t TXFIFO2HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO3; + stc_hsspi_txfifo3_field_t TXFIFO3_f; + struct { + union { + __IO uint16_t TXFIFO3L; + struct { + __IO uint8_t TXFIFO3LL; + __IO uint8_t TXFIFO3LH; + }; + }; + union { + __IO uint16_t TXFIFO3H; + struct { + __IO uint8_t TXFIFO3HL; + __IO uint8_t TXFIFO3HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO4; + stc_hsspi_txfifo4_field_t TXFIFO4_f; + struct { + union { + __IO uint16_t TXFIFO4L; + struct { + __IO uint8_t TXFIFO4LL; + __IO uint8_t TXFIFO4LH; + }; + }; + union { + __IO uint16_t TXFIFO4H; + struct { + __IO uint8_t TXFIFO4HL; + __IO uint8_t TXFIFO4HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO5; + stc_hsspi_txfifo5_field_t TXFIFO5_f; + struct { + union { + __IO uint16_t TXFIFO5L; + struct { + __IO uint8_t TXFIFO5LL; + __IO uint8_t TXFIFO5LH; + }; + }; + union { + __IO uint16_t TXFIFO5H; + struct { + __IO uint8_t TXFIFO5HL; + __IO uint8_t TXFIFO5HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO6; + stc_hsspi_txfifo6_field_t TXFIFO6_f; + struct { + union { + __IO uint16_t TXFIFO6L; + struct { + __IO uint8_t TXFIFO6LL; + __IO uint8_t TXFIFO6LH; + }; + }; + union { + __IO uint16_t TXFIFO6H; + struct { + __IO uint8_t TXFIFO6HL; + __IO uint8_t TXFIFO6HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO7; + stc_hsspi_txfifo7_field_t TXFIFO7_f; + struct { + union { + __IO uint16_t TXFIFO7L; + struct { + __IO uint8_t TXFIFO7LL; + __IO uint8_t TXFIFO7LH; + }; + }; + union { + __IO uint16_t TXFIFO7H; + struct { + __IO uint8_t TXFIFO7HL; + __IO uint8_t TXFIFO7HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO8; + stc_hsspi_txfifo8_field_t TXFIFO8_f; + struct { + union { + __IO uint16_t TXFIFO8L; + struct { + __IO uint8_t TXFIFO8LL; + __IO uint8_t TXFIFO8LH; + }; + }; + union { + __IO uint16_t TXFIFO8H; + struct { + __IO uint8_t TXFIFO8HL; + __IO uint8_t TXFIFO8HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO9; + stc_hsspi_txfifo9_field_t TXFIFO9_f; + struct { + union { + __IO uint16_t TXFIFO9L; + struct { + __IO uint8_t TXFIFO9LL; + __IO uint8_t TXFIFO9LH; + }; + }; + union { + __IO uint16_t TXFIFO9H; + struct { + __IO uint8_t TXFIFO9HL; + __IO uint8_t TXFIFO9HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO10; + stc_hsspi_txfifo10_field_t TXFIFO10_f; + struct { + union { + __IO uint16_t TXFIFO10L; + struct { + __IO uint8_t TXFIFO10LL; + __IO uint8_t TXFIFO10LH; + }; + }; + union { + __IO uint16_t TXFIFO10H; + struct { + __IO uint8_t TXFIFO10HL; + __IO uint8_t TXFIFO10HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO11; + stc_hsspi_txfifo11_field_t TXFIFO11_f; + struct { + union { + __IO uint16_t TXFIFO11L; + struct { + __IO uint8_t TXFIFO11LL; + __IO uint8_t TXFIFO11LH; + }; + }; + union { + __IO uint16_t TXFIFO11H; + struct { + __IO uint8_t TXFIFO11HL; + __IO uint8_t TXFIFO11HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO12; + stc_hsspi_txfifo12_field_t TXFIFO12_f; + struct { + union { + __IO uint16_t TXFIFO12L; + struct { + __IO uint8_t TXFIFO12LL; + __IO uint8_t TXFIFO12LH; + }; + }; + union { + __IO uint16_t TXFIFO12H; + struct { + __IO uint8_t TXFIFO12HL; + __IO uint8_t TXFIFO12HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO13; + stc_hsspi_txfifo13_field_t TXFIFO13_f; + struct { + union { + __IO uint16_t TXFIFO13L; + struct { + __IO uint8_t TXFIFO13LL; + __IO uint8_t TXFIFO13LH; + }; + }; + union { + __IO uint16_t TXFIFO13H; + struct { + __IO uint8_t TXFIFO13HL; + __IO uint8_t TXFIFO13HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO14; + stc_hsspi_txfifo14_field_t TXFIFO14_f; + struct { + union { + __IO uint16_t TXFIFO14L; + struct { + __IO uint8_t TXFIFO14LL; + __IO uint8_t TXFIFO14LH; + }; + }; + union { + __IO uint16_t TXFIFO14H; + struct { + __IO uint8_t TXFIFO14HL; + __IO uint8_t TXFIFO14HH; + }; + }; + }; + }; + union { + __IO uint32_t TXFIFO15; + stc_hsspi_txfifo15_field_t TXFIFO15_f; + struct { + union { + __IO uint16_t TXFIFO15L; + struct { + __IO uint8_t TXFIFO15LL; + __IO uint8_t TXFIFO15LH; + }; + }; + union { + __IO uint16_t TXFIFO15H; + struct { + __IO uint8_t TXFIFO15HL; + __IO uint8_t TXFIFO15HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO0; + stc_hsspi_rxfifo0_field_t RXFIFO0_f; + struct { + union { + __IO uint16_t RXFIFO0L; + struct { + __IO uint8_t RXFIFO0LL; + __IO uint8_t RXFIFO0LH; + }; + }; + union { + __IO uint16_t RXFIFO0H; + struct { + __IO uint8_t RXFIFO0HL; + __IO uint8_t RXFIFO0HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO1; + stc_hsspi_rxfifo1_field_t RXFIFO1_f; + struct { + union { + __IO uint16_t RXFIFO1L; + struct { + __IO uint8_t RXFIFO1LL; + __IO uint8_t RXFIFO1LH; + }; + }; + union { + __IO uint16_t RXFIFO1H; + struct { + __IO uint8_t RXFIFO1HL; + __IO uint8_t RXFIFO1HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO2; + stc_hsspi_rxfifo2_field_t RXFIFO2_f; + struct { + union { + __IO uint16_t RXFIFO2L; + struct { + __IO uint8_t RXFIFO2LL; + __IO uint8_t RXFIFO2LH; + }; + }; + union { + __IO uint16_t RXFIFO2H; + struct { + __IO uint8_t RXFIFO2HL; + __IO uint8_t RXFIFO2HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO3; + stc_hsspi_rxfifo3_field_t RXFIFO3_f; + struct { + union { + __IO uint16_t RXFIFO3L; + struct { + __IO uint8_t RXFIFO3LL; + __IO uint8_t RXFIFO3LH; + }; + }; + union { + __IO uint16_t RXFIFO3H; + struct { + __IO uint8_t RXFIFO3HL; + __IO uint8_t RXFIFO3HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO4; + stc_hsspi_rxfifo4_field_t RXFIFO4_f; + struct { + union { + __IO uint16_t RXFIFO4L; + struct { + __IO uint8_t RXFIFO4LL; + __IO uint8_t RXFIFO4LH; + }; + }; + union { + __IO uint16_t RXFIFO4H; + struct { + __IO uint8_t RXFIFO4HL; + __IO uint8_t RXFIFO4HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO5; + stc_hsspi_rxfifo5_field_t RXFIFO5_f; + struct { + union { + __IO uint16_t RXFIFO5L; + struct { + __IO uint8_t RXFIFO5LL; + __IO uint8_t RXFIFO5LH; + }; + }; + union { + __IO uint16_t RXFIFO5H; + struct { + __IO uint8_t RXFIFO5HL; + __IO uint8_t RXFIFO5HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO6; + stc_hsspi_rxfifo6_field_t RXFIFO6_f; + struct { + union { + __IO uint16_t RXFIFO6L; + struct { + __IO uint8_t RXFIFO6LL; + __IO uint8_t RXFIFO6LH; + }; + }; + union { + __IO uint16_t RXFIFO6H; + struct { + __IO uint8_t RXFIFO6HL; + __IO uint8_t RXFIFO6HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO7; + stc_hsspi_rxfifo7_field_t RXFIFO7_f; + struct { + union { + __IO uint16_t RXFIFO7L; + struct { + __IO uint8_t RXFIFO7LL; + __IO uint8_t RXFIFO7LH; + }; + }; + union { + __IO uint16_t RXFIFO7H; + struct { + __IO uint8_t RXFIFO7HL; + __IO uint8_t RXFIFO7HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO8; + stc_hsspi_rxfifo8_field_t RXFIFO8_f; + struct { + union { + __IO uint16_t RXFIFO8L; + struct { + __IO uint8_t RXFIFO8LL; + __IO uint8_t RXFIFO8LH; + }; + }; + union { + __IO uint16_t RXFIFO8H; + struct { + __IO uint8_t RXFIFO8HL; + __IO uint8_t RXFIFO8HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO9; + stc_hsspi_rxfifo9_field_t RXFIFO9_f; + struct { + union { + __IO uint16_t RXFIFO9L; + struct { + __IO uint8_t RXFIFO9LL; + __IO uint8_t RXFIFO9LH; + }; + }; + union { + __IO uint16_t RXFIFO9H; + struct { + __IO uint8_t RXFIFO9HL; + __IO uint8_t RXFIFO9HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO10; + stc_hsspi_rxfifo10_field_t RXFIFO10_f; + struct { + union { + __IO uint16_t RXFIFO10L; + struct { + __IO uint8_t RXFIFO10LL; + __IO uint8_t RXFIFO10LH; + }; + }; + union { + __IO uint16_t RXFIFO10H; + struct { + __IO uint8_t RXFIFO10HL; + __IO uint8_t RXFIFO10HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO11; + stc_hsspi_rxfifo11_field_t RXFIFO11_f; + struct { + union { + __IO uint16_t RXFIFO11L; + struct { + __IO uint8_t RXFIFO11LL; + __IO uint8_t RXFIFO11LH; + }; + }; + union { + __IO uint16_t RXFIFO11H; + struct { + __IO uint8_t RXFIFO11HL; + __IO uint8_t RXFIFO11HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO12; + stc_hsspi_rxfifo12_field_t RXFIFO12_f; + struct { + union { + __IO uint16_t RXFIFO12L; + struct { + __IO uint8_t RXFIFO12LL; + __IO uint8_t RXFIFO12LH; + }; + }; + union { + __IO uint16_t RXFIFO12H; + struct { + __IO uint8_t RXFIFO12HL; + __IO uint8_t RXFIFO12HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO13; + stc_hsspi_rxfifo13_field_t RXFIFO13_f; + struct { + union { + __IO uint16_t RXFIFO13L; + struct { + __IO uint8_t RXFIFO13LL; + __IO uint8_t RXFIFO13LH; + }; + }; + union { + __IO uint16_t RXFIFO13H; + struct { + __IO uint8_t RXFIFO13HL; + __IO uint8_t RXFIFO13HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO14; + stc_hsspi_rxfifo14_field_t RXFIFO14_f; + struct { + union { + __IO uint16_t RXFIFO14L; + struct { + __IO uint8_t RXFIFO14LL; + __IO uint8_t RXFIFO14LH; + }; + }; + union { + __IO uint16_t RXFIFO14H; + struct { + __IO uint8_t RXFIFO14HL; + __IO uint8_t RXFIFO14HH; + }; + }; + }; + }; + union { + __IO uint32_t RXFIFO15; + stc_hsspi_rxfifo15_field_t RXFIFO15_f; + struct { + union { + __IO uint16_t RXFIFO15L; + struct { + __IO uint8_t RXFIFO15LL; + __IO uint8_t RXFIFO15LH; + }; + }; + union { + __IO uint16_t RXFIFO15H; + struct { + __IO uint8_t RXFIFO15HL; + __IO uint8_t RXFIFO15HH; + }; + }; + }; + }; + union { + __IO uint32_t CSCFG; + stc_hsspi_cscfg_field_t CSCFG_f; + struct { + union { + __IO uint16_t CSCFGL; + struct { + __IO uint8_t CSCFGLL; + __IO uint8_t CSCFGLH; + }; + }; + union { + __IO uint16_t CSCFGH; + struct { + __IO uint8_t CSCFGHL; + __IO uint8_t CSCFGHH; + }; + }; + }; + }; + union { + __IO uint32_t CSITIME; + stc_hsspi_csitime_field_t CSITIME_f; + struct { + union { + __IO uint16_t CSITIMEL; + struct { + __IO uint8_t CSITIMELL; + __IO uint8_t CSITIMELH; + }; + }; + union { + __IO uint16_t CSITIMEH; + struct { + __IO uint8_t CSITIMEHL; + __IO uint8_t CSITIMEHH; + }; + }; + }; + }; + union { + __IO uint32_t CSAEXT; + stc_hsspi_csaext_field_t CSAEXT_f; + struct { + union { + __IO uint16_t CSAEXTL; + struct { + __IO uint8_t CSAEXTLL; + __IO uint8_t CSAEXTLH; + }; + }; + union { + __IO uint16_t CSAEXTH; + struct { + __IO uint8_t CSAEXTHL; + __IO uint8_t CSAEXTHH; + }; + }; + }; + }; + union { + __IO uint16_t RDCSDC0; + stc_hsspi_rdcsdc0_field_t RDCSDC0_f; + struct { + __IO uint8_t RDCSDC0L; + __IO uint8_t RDCSDC0H; + }; + }; + union { + __IO uint16_t RDCSDC1; + stc_hsspi_rdcsdc1_field_t RDCSDC1_f; + struct { + __IO uint8_t RDCSDC1L; + __IO uint8_t RDCSDC1H; + }; + }; + union { + __IO uint16_t RDCSDC2; + stc_hsspi_rdcsdc2_field_t RDCSDC2_f; + struct { + __IO uint8_t RDCSDC2L; + __IO uint8_t RDCSDC2H; + }; + }; + union { + __IO uint16_t RDCSDC3; + stc_hsspi_rdcsdc3_field_t RDCSDC3_f; + struct { + __IO uint8_t RDCSDC3L; + __IO uint8_t RDCSDC3H; + }; + }; + union { + __IO uint16_t RDCSDC4; + stc_hsspi_rdcsdc4_field_t RDCSDC4_f; + struct { + __IO uint8_t RDCSDC4L; + __IO uint8_t RDCSDC4H; + }; + }; + union { + __IO uint16_t RDCSDC5; + stc_hsspi_rdcsdc5_field_t RDCSDC5_f; + struct { + __IO uint8_t RDCSDC5L; + __IO uint8_t RDCSDC5H; + }; + }; + union { + __IO uint16_t RDCSDC6; + stc_hsspi_rdcsdc6_field_t RDCSDC6_f; + struct { + __IO uint8_t RDCSDC6L; + __IO uint8_t RDCSDC6H; + }; + }; + union { + __IO uint16_t RDCSDC7; + stc_hsspi_rdcsdc7_field_t RDCSDC7_f; + struct { + __IO uint8_t RDCSDC7L; + __IO uint8_t RDCSDC7H; + }; + }; + union { + __IO uint16_t WRCSDC0; + stc_hsspi_wrcsdc0_field_t WRCSDC0_f; + struct { + __IO uint8_t WRCSDC0L; + __IO uint8_t WRCSDC0H; + }; + }; + union { + __IO uint16_t WRCSDC1; + stc_hsspi_wrcsdc1_field_t WRCSDC1_f; + struct { + __IO uint8_t WRCSDC1L; + __IO uint8_t WRCSDC1H; + }; + }; + union { + __IO uint16_t WRCSDC2; + stc_hsspi_wrcsdc2_field_t WRCSDC2_f; + struct { + __IO uint8_t WRCSDC2L; + __IO uint8_t WRCSDC2H; + }; + }; + union { + __IO uint16_t WRCSDC3; + stc_hsspi_wrcsdc3_field_t WRCSDC3_f; + struct { + __IO uint8_t WRCSDC3L; + __IO uint8_t WRCSDC3H; + }; + }; + union { + __IO uint16_t WRCSDC4; + stc_hsspi_wrcsdc4_field_t WRCSDC4_f; + struct { + __IO uint8_t WRCSDC4L; + __IO uint8_t WRCSDC4H; + }; + }; + union { + __IO uint16_t WRCSDC5; + stc_hsspi_wrcsdc5_field_t WRCSDC5_f; + struct { + __IO uint8_t WRCSDC5L; + __IO uint8_t WRCSDC5H; + }; + }; + union { + __IO uint16_t WRCSDC6; + stc_hsspi_wrcsdc6_field_t WRCSDC6_f; + struct { + __IO uint8_t WRCSDC6L; + __IO uint8_t WRCSDC6H; + }; + }; + union { + __IO uint16_t WRCSDC7; + stc_hsspi_wrcsdc7_field_t WRCSDC7_f; + struct { + __IO uint8_t WRCSDC7L; + __IO uint8_t WRCSDC7H; + }; + }; + union { + __IO uint32_t MID; + stc_hsspi_mid_field_t MID_f; + struct { + union { + __IO uint16_t MIDL; + struct { + __IO uint8_t MIDLL; + __IO uint8_t MIDLH; + }; + }; + union { + __IO uint16_t MIDH; + struct { + __IO uint8_t MIDHL; + __IO uint8_t MIDHH; + }; + }; + }; + }; + __IO uint8_t RESERVED2[768]; + union { + __IO uint8_t QDCLKR; + stc_hsspi_qdclkr_field_t QDCLKR_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint8_t DBCNT; + stc_hsspi_dbcnt_field_t DBCNT_f; + }; +} FM_HSSPI_TypeDef, FM4_HSSPI_TypeDef; + +/******************************************************************************* +* HWWDT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t WDG_LDR; + struct { + union { + __IO uint16_t WDG_LDRL; + struct { + __IO uint8_t WDG_LDRLL; + __IO uint8_t WDG_LDRLH; + }; + }; + union { + __IO uint16_t WDG_LDRH; + struct { + __IO uint8_t WDG_LDRHL; + __IO uint8_t WDG_LDRHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_VLR; + struct { + union { + __IO uint16_t WDG_VLRL; + struct { + __IO uint8_t WDG_VLRLL; + __IO uint8_t WDG_VLRLH; + }; + }; + union { + __IO uint16_t WDG_VLRH; + struct { + __IO uint8_t WDG_VLRHL; + __IO uint8_t WDG_VLRHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_CTL; + stc_hwwdt_wdg_ctl_field_t WDG_CTL_f; + struct { + union { + __IO uint16_t WDG_CTLL; + struct { + __IO uint8_t WDG_CTLLL; + __IO uint8_t WDG_CTLLH; + }; + }; + union { + __IO uint16_t WDG_CTLH; + struct { + __IO uint8_t WDG_CTLHL; + __IO uint8_t WDG_CTLHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_ICL; + struct { + union { + __IO uint16_t WDG_ICLL; + struct { + __IO uint8_t WDG_ICLLL; + __IO uint8_t WDG_ICLLH; + }; + }; + union { + __IO uint16_t WDG_ICLH; + struct { + __IO uint8_t WDG_ICLHL; + __IO uint8_t WDG_ICLHH; + }; + }; + }; + }; + union { + __IO uint32_t WDG_RIS; + stc_hwwdt_wdg_ris_field_t WDG_RIS_f; + struct { + union { + __IO uint16_t WDG_RISL; + struct { + __IO uint8_t WDG_RISLL; + __IO uint8_t WDG_RISLH; + }; + }; + union { + __IO uint16_t WDG_RISH; + struct { + __IO uint8_t WDG_RISHL; + __IO uint8_t WDG_RISHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[3052]; + union { + __IO uint32_t WDG_LCK; + struct { + union { + __IO uint16_t WDG_LCKL; + struct { + __IO uint8_t WDG_LCKLL; + __IO uint8_t WDG_LCKLH; + }; + }; + union { + __IO uint16_t WDG_LCKH; + struct { + __IO uint8_t WDG_LCKHL; + __IO uint8_t WDG_LCKHH; + }; + }; + }; + }; +} FM_HWWDT_TypeDef, FM4_HWWDT_TypeDef; + +/******************************************************************************* +* I2S_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t RXFDAT; + stc_i2s_rxfdat_field_t RXFDAT_f; + struct { + union { + __IO uint16_t RXFDATL; + struct { + __IO uint8_t RXFDATLL; + __IO uint8_t RXFDATLH; + }; + }; + union { + __IO uint16_t RXFDATH; + struct { + __IO uint8_t RXFDATHL; + __IO uint8_t RXFDATHH; + }; + }; + }; + }; + union { + __IO uint32_t TXFDAT; + stc_i2s_txfdat_field_t TXFDAT_f; + struct { + union { + __IO uint16_t TXFDATL; + struct { + __IO uint8_t TXFDATLL; + __IO uint8_t TXFDATLH; + }; + }; + union { + __IO uint16_t TXFDATH; + struct { + __IO uint8_t TXFDATHL; + __IO uint8_t TXFDATHH; + }; + }; + }; + }; + union { + __IO uint32_t CNTREG; + stc_i2s_cntreg_field_t CNTREG_f; + struct { + union { + __IO uint16_t CNTREGL; + struct { + __IO uint8_t CNTREGLL; + __IO uint8_t CNTREGLH; + }; + }; + union { + __IO uint16_t CNTREGH; + struct { + __IO uint8_t CNTREGHL; + __IO uint8_t CNTREGHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR0REG; + stc_i2s_mcr0reg_field_t MCR0REG_f; + struct { + union { + __IO uint16_t MCR0REGL; + struct { + __IO uint8_t MCR0REGLL; + __IO uint8_t MCR0REGLH; + }; + }; + union { + __IO uint16_t MCR0REGH; + struct { + __IO uint8_t MCR0REGHL; + __IO uint8_t MCR0REGHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR1REG; + stc_i2s_mcr1reg_field_t MCR1REG_f; + struct { + union { + __IO uint16_t MCR1REGL; + struct { + __IO uint8_t MCR1REGLL; + __IO uint8_t MCR1REGLH; + }; + }; + union { + __IO uint16_t MCR1REGH; + struct { + __IO uint8_t MCR1REGHL; + __IO uint8_t MCR1REGHH; + }; + }; + }; + }; + union { + __IO uint32_t MCR2REG; + stc_i2s_mcr2reg_field_t MCR2REG_f; + struct { + union { + __IO uint16_t MCR2REGL; + struct { + __IO uint8_t MCR2REGLL; + __IO uint8_t MCR2REGLH; + }; + }; + union { + __IO uint16_t MCR2REGH; + struct { + __IO uint8_t MCR2REGHL; + __IO uint8_t MCR2REGHH; + }; + }; + }; + }; + union { + __IO uint32_t OPRREG; + stc_i2s_oprreg_field_t OPRREG_f; + struct { + union { + __IO uint16_t OPRREGL; + struct { + __IO uint8_t OPRREGLL; + __IO uint8_t OPRREGLH; + }; + }; + union { + __IO uint16_t OPRREGH; + struct { + __IO uint8_t OPRREGHL; + __IO uint8_t OPRREGHH; + }; + }; + }; + }; + union { + __IO uint32_t SRST; + stc_i2s_srst_field_t SRST_f; + struct { + union { + __IO uint16_t SRSTL; + struct { + __IO uint8_t SRSTLL; + __IO uint8_t SRSTLH; + }; + }; + union { + __IO uint16_t SRSTH; + struct { + __IO uint8_t SRSTHL; + __IO uint8_t SRSTHH; + }; + }; + }; + }; + union { + __IO uint32_t INTCNT; + stc_i2s_intcnt_field_t INTCNT_f; + struct { + union { + __IO uint16_t INTCNTL; + struct { + __IO uint8_t INTCNTLL; + __IO uint8_t INTCNTLH; + }; + }; + union { + __IO uint16_t INTCNTH; + struct { + __IO uint8_t INTCNTHL; + __IO uint8_t INTCNTHH; + }; + }; + }; + }; + union { + __IO uint32_t STATUS; + stc_i2s_status_field_t STATUS_f; + struct { + union { + __IO uint16_t STATUSL; + struct { + __IO uint8_t STATUSLL; + __IO uint8_t STATUSLH; + }; + }; + union { + __IO uint16_t STATUSH; + struct { + __IO uint8_t STATUSHL; + __IO uint8_t STATUSHH; + }; + }; + }; + }; + union { + __IO uint32_t DMAACT; + stc_i2s_dmaact_field_t DMAACT_f; + struct { + union { + __IO uint16_t DMAACTL; + struct { + __IO uint8_t DMAACTLL; + __IO uint8_t DMAACTLH; + }; + }; + union { + __IO uint16_t DMAACTH; + struct { + __IO uint8_t DMAACTHL; + __IO uint8_t DMAACTHH; + }; + }; + }; + }; + union { + __IO uint32_t TSTREG; + stc_i2s_tstreg_field_t TSTREG_f; + struct { + union { + __IO uint16_t TSTREGL; + struct { + __IO uint8_t TSTREGLL; + __IO uint8_t TSTREGLH; + }; + }; + union { + __IO uint16_t TSTREGH; + struct { + __IO uint8_t TSTREGHL; + __IO uint8_t TSTREGHH; + }; + }; + }; + }; +} FM_I2S_TypeDef, FM4_I2S_TypeDef; + +/******************************************************************************* +* I2SPRE_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t ICCR; + stc_i2spre_iccr_field_t ICCR_f; + struct { + union { + __IO uint16_t ICCRL; + struct { + __IO uint8_t ICCRLL; + __IO uint8_t ICCRLH; + }; + }; + union { + __IO uint16_t ICCRH; + struct { + __IO uint8_t ICCRHL; + __IO uint8_t ICCRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR1; + stc_i2spre_ipcr1_field_t IPCR1_f; + struct { + union { + __IO uint16_t IPCR1L; + struct { + __IO uint8_t IPCR1LL; + __IO uint8_t IPCR1LH; + }; + }; + union { + __IO uint16_t IPCR1H; + struct { + __IO uint8_t IPCR1HL; + __IO uint8_t IPCR1HH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR2; + stc_i2spre_ipcr2_field_t IPCR2_f; + struct { + union { + __IO uint16_t IPCR2L; + struct { + __IO uint8_t IPCR2LL; + __IO uint8_t IPCR2LH; + }; + }; + union { + __IO uint16_t IPCR2H; + struct { + __IO uint8_t IPCR2HL; + __IO uint8_t IPCR2HH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR3; + stc_i2spre_ipcr3_field_t IPCR3_f; + struct { + union { + __IO uint16_t IPCR3L; + struct { + __IO uint8_t IPCR3LL; + __IO uint8_t IPCR3LH; + }; + }; + union { + __IO uint16_t IPCR3H; + struct { + __IO uint8_t IPCR3HL; + __IO uint8_t IPCR3HH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR4; + stc_i2spre_ipcr4_field_t IPCR4_f; + struct { + union { + __IO uint16_t IPCR4L; + struct { + __IO uint8_t IPCR4LL; + __IO uint8_t IPCR4LH; + }; + }; + union { + __IO uint16_t IPCR4H; + struct { + __IO uint8_t IPCR4HL; + __IO uint8_t IPCR4HH; + }; + }; + }; + }; + union { + __IO uint32_t IP_STR; + stc_i2spre_ip_str_field_t IP_STR_f; + struct { + union { + __IO uint16_t IP_STRL; + struct { + __IO uint8_t IP_STRLL; + __IO uint8_t IP_STRLH; + }; + }; + union { + __IO uint16_t IP_STRH; + struct { + __IO uint8_t IP_STRHL; + __IO uint8_t IP_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPINT_ENR; + stc_i2spre_ipint_enr_field_t IPINT_ENR_f; + struct { + union { + __IO uint16_t IPINT_ENRL; + struct { + __IO uint8_t IPINT_ENRLL; + __IO uint8_t IPINT_ENRLH; + }; + }; + union { + __IO uint16_t IPINT_ENRH; + struct { + __IO uint8_t IPINT_ENRHL; + __IO uint8_t IPINT_ENRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPINT_CLR; + stc_i2spre_ipint_clr_field_t IPINT_CLR_f; + struct { + union { + __IO uint16_t IPINT_CLRL; + struct { + __IO uint8_t IPINT_CLRLL; + __IO uint8_t IPINT_CLRLH; + }; + }; + union { + __IO uint16_t IPINT_CLRH; + struct { + __IO uint8_t IPINT_CLRHL; + __IO uint8_t IPINT_CLRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPINT_STR; + stc_i2spre_ipint_str_field_t IPINT_STR_f; + struct { + union { + __IO uint16_t IPINT_STRL; + struct { + __IO uint8_t IPINT_STRLL; + __IO uint8_t IPINT_STRLH; + }; + }; + union { + __IO uint16_t IPINT_STRH; + struct { + __IO uint8_t IPINT_STRHL; + __IO uint8_t IPINT_STRHH; + }; + }; + }; + }; + union { + __IO uint32_t IPCR5; + stc_i2spre_ipcr5_field_t IPCR5_f; + struct { + union { + __IO uint16_t IPCR5L; + struct { + __IO uint8_t IPCR5LL; + __IO uint8_t IPCR5LH; + }; + }; + union { + __IO uint16_t IPCR5H; + struct { + __IO uint8_t IPCR5HL; + __IO uint8_t IPCR5HH; + }; + }; + }; + }; +} FM_I2SPRE_TypeDef, FM4_I2SPRE_TypeDef; + +/******************************************************************************* +* INTREQ_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t DRQSEL; + stc_intreq_drqsel_field_t DRQSEL_f; + struct { + union { + __IO uint16_t DRQSELL; + struct { + __IO uint8_t DRQSELLL; + __IO uint8_t DRQSELLH; + }; + }; + union { + __IO uint16_t DRQSELH; + struct { + __IO uint8_t DRQSELHL; + __IO uint8_t DRQSELHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[12]; + union { + __IO uint8_t ODDPKS; + stc_intreq_oddpks_field_t ODDPKS_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t ODDPKS1; + stc_intreq_oddpks1_field_t ODDPKS1_f; + }; + __IO uint8_t RESERVED2[251]; + union { + __IO uint32_t IRQ003SEL; + stc_intreq_irq003sel_field_t IRQ003SEL_f; + struct { + union { + __IO uint16_t IRQ003SELL; + struct { + __IO uint8_t IRQ003SELLL; + __IO uint8_t IRQ003SELLH; + }; + }; + union { + __IO uint16_t IRQ003SELH; + struct { + __IO uint8_t IRQ003SELHL; + __IO uint8_t IRQ003SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ004SEL; + stc_intreq_irq004sel_field_t IRQ004SEL_f; + struct { + union { + __IO uint16_t IRQ004SELL; + struct { + __IO uint8_t IRQ004SELLL; + __IO uint8_t IRQ004SELLH; + }; + }; + union { + __IO uint16_t IRQ004SELH; + struct { + __IO uint8_t IRQ004SELHL; + __IO uint8_t IRQ004SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ005SEL; + stc_intreq_irq005sel_field_t IRQ005SEL_f; + struct { + union { + __IO uint16_t IRQ005SELL; + struct { + __IO uint8_t IRQ005SELLL; + __IO uint8_t IRQ005SELLH; + }; + }; + union { + __IO uint16_t IRQ005SELH; + struct { + __IO uint8_t IRQ005SELHL; + __IO uint8_t IRQ005SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ006SEL; + stc_intreq_irq006sel_field_t IRQ006SEL_f; + struct { + union { + __IO uint16_t IRQ006SELL; + struct { + __IO uint8_t IRQ006SELLL; + __IO uint8_t IRQ006SELLH; + }; + }; + union { + __IO uint16_t IRQ006SELH; + struct { + __IO uint8_t IRQ006SELHL; + __IO uint8_t IRQ006SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ007SEL; + stc_intreq_irq007sel_field_t IRQ007SEL_f; + struct { + union { + __IO uint16_t IRQ007SELL; + struct { + __IO uint8_t IRQ007SELLL; + __IO uint8_t IRQ007SELLH; + }; + }; + union { + __IO uint16_t IRQ007SELH; + struct { + __IO uint8_t IRQ007SELHL; + __IO uint8_t IRQ007SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ008SEL; + stc_intreq_irq008sel_field_t IRQ008SEL_f; + struct { + union { + __IO uint16_t IRQ008SELL; + struct { + __IO uint8_t IRQ008SELLL; + __IO uint8_t IRQ008SELLH; + }; + }; + union { + __IO uint16_t IRQ008SELH; + struct { + __IO uint8_t IRQ008SELHL; + __IO uint8_t IRQ008SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ009SEL; + stc_intreq_irq009sel_field_t IRQ009SEL_f; + struct { + union { + __IO uint16_t IRQ009SELL; + struct { + __IO uint8_t IRQ009SELLL; + __IO uint8_t IRQ009SELLH; + }; + }; + union { + __IO uint16_t IRQ009SELH; + struct { + __IO uint8_t IRQ009SELHL; + __IO uint8_t IRQ009SELHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ010SEL; + stc_intreq_irq010sel_field_t IRQ010SEL_f; + struct { + union { + __IO uint16_t IRQ010SELL; + struct { + __IO uint8_t IRQ010SELLL; + __IO uint8_t IRQ010SELLH; + }; + }; + union { + __IO uint16_t IRQ010SELH; + struct { + __IO uint8_t IRQ010SELHL; + __IO uint8_t IRQ010SELHH; + }; + }; + }; + }; + __IO uint8_t RESERVED3[208]; + union { + __IO uint32_t EXC02MON; + stc_intreq_exc02mon_field_t EXC02MON_f; + struct { + union { + __IO uint16_t EXC02MONL; + struct { + __IO uint8_t EXC02MONLL; + __IO uint8_t EXC02MONLH; + }; + }; + union { + __IO uint16_t EXC02MONH; + struct { + __IO uint8_t EXC02MONHL; + __IO uint8_t EXC02MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ000MON; + stc_intreq_irq000mon_field_t IRQ000MON_f; + struct { + union { + __IO uint16_t IRQ000MONL; + struct { + __IO uint8_t IRQ000MONLL; + __IO uint8_t IRQ000MONLH; + }; + }; + union { + __IO uint16_t IRQ000MONH; + struct { + __IO uint8_t IRQ000MONHL; + __IO uint8_t IRQ000MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ001MON; + stc_intreq_irq001mon_field_t IRQ001MON_f; + struct { + union { + __IO uint16_t IRQ001MONL; + struct { + __IO uint8_t IRQ001MONLL; + __IO uint8_t IRQ001MONLH; + }; + }; + union { + __IO uint16_t IRQ001MONH; + struct { + __IO uint8_t IRQ001MONHL; + __IO uint8_t IRQ001MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ002MON; + stc_intreq_irq002mon_field_t IRQ002MON_f; + struct { + union { + __IO uint16_t IRQ002MONL; + struct { + __IO uint8_t IRQ002MONLL; + __IO uint8_t IRQ002MONLH; + }; + }; + union { + __IO uint16_t IRQ002MONH; + struct { + __IO uint8_t IRQ002MONHL; + __IO uint8_t IRQ002MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ003MON; + stc_intreq_irq003mon_field_t IRQ003MON_f; + struct { + union { + __IO uint16_t IRQ003MONL; + struct { + __IO uint8_t IRQ003MONLL; + __IO uint8_t IRQ003MONLH; + }; + }; + union { + __IO uint16_t IRQ003MONH; + struct { + __IO uint8_t IRQ003MONHL; + __IO uint8_t IRQ003MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ004MON; + stc_intreq_irq004mon_field_t IRQ004MON_f; + struct { + union { + __IO uint16_t IRQ004MONL; + struct { + __IO uint8_t IRQ004MONLL; + __IO uint8_t IRQ004MONLH; + }; + }; + union { + __IO uint16_t IRQ004MONH; + struct { + __IO uint8_t IRQ004MONHL; + __IO uint8_t IRQ004MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ005MON; + stc_intreq_irq005mon_field_t IRQ005MON_f; + struct { + union { + __IO uint16_t IRQ005MONL; + struct { + __IO uint8_t IRQ005MONLL; + __IO uint8_t IRQ005MONLH; + }; + }; + union { + __IO uint16_t IRQ005MONH; + struct { + __IO uint8_t IRQ005MONHL; + __IO uint8_t IRQ005MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ006MON; + stc_intreq_irq006mon_field_t IRQ006MON_f; + struct { + union { + __IO uint16_t IRQ006MONL; + struct { + __IO uint8_t IRQ006MONLL; + __IO uint8_t IRQ006MONLH; + }; + }; + union { + __IO uint16_t IRQ006MONH; + struct { + __IO uint8_t IRQ006MONHL; + __IO uint8_t IRQ006MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ007MON; + stc_intreq_irq007mon_field_t IRQ007MON_f; + struct { + union { + __IO uint16_t IRQ007MONL; + struct { + __IO uint8_t IRQ007MONLL; + __IO uint8_t IRQ007MONLH; + }; + }; + union { + __IO uint16_t IRQ007MONH; + struct { + __IO uint8_t IRQ007MONHL; + __IO uint8_t IRQ007MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ008MON; + stc_intreq_irq008mon_field_t IRQ008MON_f; + struct { + union { + __IO uint16_t IRQ008MONL; + struct { + __IO uint8_t IRQ008MONLL; + __IO uint8_t IRQ008MONLH; + }; + }; + union { + __IO uint16_t IRQ008MONH; + struct { + __IO uint8_t IRQ008MONHL; + __IO uint8_t IRQ008MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ009MON; + stc_intreq_irq009mon_field_t IRQ009MON_f; + struct { + union { + __IO uint16_t IRQ009MONL; + struct { + __IO uint8_t IRQ009MONLL; + __IO uint8_t IRQ009MONLH; + }; + }; + union { + __IO uint16_t IRQ009MONH; + struct { + __IO uint8_t IRQ009MONHL; + __IO uint8_t IRQ009MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ010MON; + stc_intreq_irq010mon_field_t IRQ010MON_f; + struct { + union { + __IO uint16_t IRQ010MONL; + struct { + __IO uint8_t IRQ010MONLL; + __IO uint8_t IRQ010MONLH; + }; + }; + union { + __IO uint16_t IRQ010MONH; + struct { + __IO uint8_t IRQ010MONHL; + __IO uint8_t IRQ010MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ011MON; + stc_intreq_irq011mon_field_t IRQ011MON_f; + struct { + union { + __IO uint16_t IRQ011MONL; + struct { + __IO uint8_t IRQ011MONLL; + __IO uint8_t IRQ011MONLH; + }; + }; + union { + __IO uint16_t IRQ011MONH; + struct { + __IO uint8_t IRQ011MONHL; + __IO uint8_t IRQ011MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ012MON; + stc_intreq_irq012mon_field_t IRQ012MON_f; + struct { + union { + __IO uint16_t IRQ012MONL; + struct { + __IO uint8_t IRQ012MONLL; + __IO uint8_t IRQ012MONLH; + }; + }; + union { + __IO uint16_t IRQ012MONH; + struct { + __IO uint8_t IRQ012MONHL; + __IO uint8_t IRQ012MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ013MON; + stc_intreq_irq013mon_field_t IRQ013MON_f; + struct { + union { + __IO uint16_t IRQ013MONL; + struct { + __IO uint8_t IRQ013MONLL; + __IO uint8_t IRQ013MONLH; + }; + }; + union { + __IO uint16_t IRQ013MONH; + struct { + __IO uint8_t IRQ013MONHL; + __IO uint8_t IRQ013MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ014MON; + stc_intreq_irq014mon_field_t IRQ014MON_f; + struct { + union { + __IO uint16_t IRQ014MONL; + struct { + __IO uint8_t IRQ014MONLL; + __IO uint8_t IRQ014MONLH; + }; + }; + union { + __IO uint16_t IRQ014MONH; + struct { + __IO uint8_t IRQ014MONHL; + __IO uint8_t IRQ014MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ015MON; + stc_intreq_irq015mon_field_t IRQ015MON_f; + struct { + union { + __IO uint16_t IRQ015MONL; + struct { + __IO uint8_t IRQ015MONLL; + __IO uint8_t IRQ015MONLH; + }; + }; + union { + __IO uint16_t IRQ015MONH; + struct { + __IO uint8_t IRQ015MONHL; + __IO uint8_t IRQ015MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ016MON; + stc_intreq_irq016mon_field_t IRQ016MON_f; + struct { + union { + __IO uint16_t IRQ016MONL; + struct { + __IO uint8_t IRQ016MONLL; + __IO uint8_t IRQ016MONLH; + }; + }; + union { + __IO uint16_t IRQ016MONH; + struct { + __IO uint8_t IRQ016MONHL; + __IO uint8_t IRQ016MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ017MON; + stc_intreq_irq017mon_field_t IRQ017MON_f; + struct { + union { + __IO uint16_t IRQ017MONL; + struct { + __IO uint8_t IRQ017MONLL; + __IO uint8_t IRQ017MONLH; + }; + }; + union { + __IO uint16_t IRQ017MONH; + struct { + __IO uint8_t IRQ017MONHL; + __IO uint8_t IRQ017MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ018MON; + stc_intreq_irq018mon_field_t IRQ018MON_f; + struct { + union { + __IO uint16_t IRQ018MONL; + struct { + __IO uint8_t IRQ018MONLL; + __IO uint8_t IRQ018MONLH; + }; + }; + union { + __IO uint16_t IRQ018MONH; + struct { + __IO uint8_t IRQ018MONHL; + __IO uint8_t IRQ018MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ019MON; + stc_intreq_irq019mon_field_t IRQ019MON_f; + struct { + union { + __IO uint16_t IRQ019MONL; + struct { + __IO uint8_t IRQ019MONLL; + __IO uint8_t IRQ019MONLH; + }; + }; + union { + __IO uint16_t IRQ019MONH; + struct { + __IO uint8_t IRQ019MONHL; + __IO uint8_t IRQ019MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ020MON; + stc_intreq_irq020mon_field_t IRQ020MON_f; + struct { + union { + __IO uint16_t IRQ020MONL; + struct { + __IO uint8_t IRQ020MONLL; + __IO uint8_t IRQ020MONLH; + }; + }; + union { + __IO uint16_t IRQ020MONH; + struct { + __IO uint8_t IRQ020MONHL; + __IO uint8_t IRQ020MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ021MON; + stc_intreq_irq021mon_field_t IRQ021MON_f; + struct { + union { + __IO uint16_t IRQ021MONL; + struct { + __IO uint8_t IRQ021MONLL; + __IO uint8_t IRQ021MONLH; + }; + }; + union { + __IO uint16_t IRQ021MONH; + struct { + __IO uint8_t IRQ021MONHL; + __IO uint8_t IRQ021MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ022MON; + stc_intreq_irq022mon_field_t IRQ022MON_f; + struct { + union { + __IO uint16_t IRQ022MONL; + struct { + __IO uint8_t IRQ022MONLL; + __IO uint8_t IRQ022MONLH; + }; + }; + union { + __IO uint16_t IRQ022MONH; + struct { + __IO uint8_t IRQ022MONHL; + __IO uint8_t IRQ022MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ023MON; + stc_intreq_irq023mon_field_t IRQ023MON_f; + struct { + union { + __IO uint16_t IRQ023MONL; + struct { + __IO uint8_t IRQ023MONLL; + __IO uint8_t IRQ023MONLH; + }; + }; + union { + __IO uint16_t IRQ023MONH; + struct { + __IO uint8_t IRQ023MONHL; + __IO uint8_t IRQ023MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ024MON; + stc_intreq_irq024mon_field_t IRQ024MON_f; + struct { + union { + __IO uint16_t IRQ024MONL; + struct { + __IO uint8_t IRQ024MONLL; + __IO uint8_t IRQ024MONLH; + }; + }; + union { + __IO uint16_t IRQ024MONH; + struct { + __IO uint8_t IRQ024MONHL; + __IO uint8_t IRQ024MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ025MON; + stc_intreq_irq025mon_field_t IRQ025MON_f; + struct { + union { + __IO uint16_t IRQ025MONL; + struct { + __IO uint8_t IRQ025MONLL; + __IO uint8_t IRQ025MONLH; + }; + }; + union { + __IO uint16_t IRQ025MONH; + struct { + __IO uint8_t IRQ025MONHL; + __IO uint8_t IRQ025MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ026MON; + stc_intreq_irq026mon_field_t IRQ026MON_f; + struct { + union { + __IO uint16_t IRQ026MONL; + struct { + __IO uint8_t IRQ026MONLL; + __IO uint8_t IRQ026MONLH; + }; + }; + union { + __IO uint16_t IRQ026MONH; + struct { + __IO uint8_t IRQ026MONHL; + __IO uint8_t IRQ026MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ027MON; + stc_intreq_irq027mon_field_t IRQ027MON_f; + struct { + union { + __IO uint16_t IRQ027MONL; + struct { + __IO uint8_t IRQ027MONLL; + __IO uint8_t IRQ027MONLH; + }; + }; + union { + __IO uint16_t IRQ027MONH; + struct { + __IO uint8_t IRQ027MONHL; + __IO uint8_t IRQ027MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ028MON; + stc_intreq_irq028mon_field_t IRQ028MON_f; + struct { + union { + __IO uint16_t IRQ028MONL; + struct { + __IO uint8_t IRQ028MONLL; + __IO uint8_t IRQ028MONLH; + }; + }; + union { + __IO uint16_t IRQ028MONH; + struct { + __IO uint8_t IRQ028MONHL; + __IO uint8_t IRQ028MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ029MON; + stc_intreq_irq029mon_field_t IRQ029MON_f; + struct { + union { + __IO uint16_t IRQ029MONL; + struct { + __IO uint8_t IRQ029MONLL; + __IO uint8_t IRQ029MONLH; + }; + }; + union { + __IO uint16_t IRQ029MONH; + struct { + __IO uint8_t IRQ029MONHL; + __IO uint8_t IRQ029MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ030MON; + stc_intreq_irq030mon_field_t IRQ030MON_f; + struct { + union { + __IO uint16_t IRQ030MONL; + struct { + __IO uint8_t IRQ030MONLL; + __IO uint8_t IRQ030MONLH; + }; + }; + union { + __IO uint16_t IRQ030MONH; + struct { + __IO uint8_t IRQ030MONHL; + __IO uint8_t IRQ030MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ031MON; + stc_intreq_irq031mon_field_t IRQ031MON_f; + struct { + union { + __IO uint16_t IRQ031MONL; + struct { + __IO uint8_t IRQ031MONLL; + __IO uint8_t IRQ031MONLH; + }; + }; + union { + __IO uint16_t IRQ031MONH; + struct { + __IO uint8_t IRQ031MONHL; + __IO uint8_t IRQ031MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ032MON; + stc_intreq_irq032mon_field_t IRQ032MON_f; + struct { + union { + __IO uint16_t IRQ032MONL; + struct { + __IO uint8_t IRQ032MONLL; + __IO uint8_t IRQ032MONLH; + }; + }; + union { + __IO uint16_t IRQ032MONH; + struct { + __IO uint8_t IRQ032MONHL; + __IO uint8_t IRQ032MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ033MON; + stc_intreq_irq033mon_field_t IRQ033MON_f; + struct { + union { + __IO uint16_t IRQ033MONL; + struct { + __IO uint8_t IRQ033MONLL; + __IO uint8_t IRQ033MONLH; + }; + }; + union { + __IO uint16_t IRQ033MONH; + struct { + __IO uint8_t IRQ033MONHL; + __IO uint8_t IRQ033MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ034MON; + stc_intreq_irq034mon_field_t IRQ034MON_f; + struct { + union { + __IO uint16_t IRQ034MONL; + struct { + __IO uint8_t IRQ034MONLL; + __IO uint8_t IRQ034MONLH; + }; + }; + union { + __IO uint16_t IRQ034MONH; + struct { + __IO uint8_t IRQ034MONHL; + __IO uint8_t IRQ034MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ035MON; + stc_intreq_irq035mon_field_t IRQ035MON_f; + struct { + union { + __IO uint16_t IRQ035MONL; + struct { + __IO uint8_t IRQ035MONLL; + __IO uint8_t IRQ035MONLH; + }; + }; + union { + __IO uint16_t IRQ035MONH; + struct { + __IO uint8_t IRQ035MONHL; + __IO uint8_t IRQ035MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ036MON; + stc_intreq_irq036mon_field_t IRQ036MON_f; + struct { + union { + __IO uint16_t IRQ036MONL; + struct { + __IO uint8_t IRQ036MONLL; + __IO uint8_t IRQ036MONLH; + }; + }; + union { + __IO uint16_t IRQ036MONH; + struct { + __IO uint8_t IRQ036MONHL; + __IO uint8_t IRQ036MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ037MON; + stc_intreq_irq037mon_field_t IRQ037MON_f; + struct { + union { + __IO uint16_t IRQ037MONL; + struct { + __IO uint8_t IRQ037MONLL; + __IO uint8_t IRQ037MONLH; + }; + }; + union { + __IO uint16_t IRQ037MONH; + struct { + __IO uint8_t IRQ037MONHL; + __IO uint8_t IRQ037MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ038MON; + stc_intreq_irq038mon_field_t IRQ038MON_f; + struct { + union { + __IO uint16_t IRQ038MONL; + struct { + __IO uint8_t IRQ038MONLL; + __IO uint8_t IRQ038MONLH; + }; + }; + union { + __IO uint16_t IRQ038MONH; + struct { + __IO uint8_t IRQ038MONHL; + __IO uint8_t IRQ038MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ039MON; + stc_intreq_irq039mon_field_t IRQ039MON_f; + struct { + union { + __IO uint16_t IRQ039MONL; + struct { + __IO uint8_t IRQ039MONLL; + __IO uint8_t IRQ039MONLH; + }; + }; + union { + __IO uint16_t IRQ039MONH; + struct { + __IO uint8_t IRQ039MONHL; + __IO uint8_t IRQ039MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ040MON; + stc_intreq_irq040mon_field_t IRQ040MON_f; + struct { + union { + __IO uint16_t IRQ040MONL; + struct { + __IO uint8_t IRQ040MONLL; + __IO uint8_t IRQ040MONLH; + }; + }; + union { + __IO uint16_t IRQ040MONH; + struct { + __IO uint8_t IRQ040MONHL; + __IO uint8_t IRQ040MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ041MON; + stc_intreq_irq041mon_field_t IRQ041MON_f; + struct { + union { + __IO uint16_t IRQ041MONL; + struct { + __IO uint8_t IRQ041MONLL; + __IO uint8_t IRQ041MONLH; + }; + }; + union { + __IO uint16_t IRQ041MONH; + struct { + __IO uint8_t IRQ041MONHL; + __IO uint8_t IRQ041MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ042MON; + stc_intreq_irq042mon_field_t IRQ042MON_f; + struct { + union { + __IO uint16_t IRQ042MONL; + struct { + __IO uint8_t IRQ042MONLL; + __IO uint8_t IRQ042MONLH; + }; + }; + union { + __IO uint16_t IRQ042MONH; + struct { + __IO uint8_t IRQ042MONHL; + __IO uint8_t IRQ042MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ043MON; + stc_intreq_irq043mon_field_t IRQ043MON_f; + struct { + union { + __IO uint16_t IRQ043MONL; + struct { + __IO uint8_t IRQ043MONLL; + __IO uint8_t IRQ043MONLH; + }; + }; + union { + __IO uint16_t IRQ043MONH; + struct { + __IO uint8_t IRQ043MONHL; + __IO uint8_t IRQ043MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ044MON; + stc_intreq_irq044mon_field_t IRQ044MON_f; + struct { + union { + __IO uint16_t IRQ044MONL; + struct { + __IO uint8_t IRQ044MONLL; + __IO uint8_t IRQ044MONLH; + }; + }; + union { + __IO uint16_t IRQ044MONH; + struct { + __IO uint8_t IRQ044MONHL; + __IO uint8_t IRQ044MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ045MON; + stc_intreq_irq045mon_field_t IRQ045MON_f; + struct { + union { + __IO uint16_t IRQ045MONL; + struct { + __IO uint8_t IRQ045MONLL; + __IO uint8_t IRQ045MONLH; + }; + }; + union { + __IO uint16_t IRQ045MONH; + struct { + __IO uint8_t IRQ045MONHL; + __IO uint8_t IRQ045MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ046MON; + stc_intreq_irq046mon_field_t IRQ046MON_f; + struct { + union { + __IO uint16_t IRQ046MONL; + struct { + __IO uint8_t IRQ046MONLL; + __IO uint8_t IRQ046MONLH; + }; + }; + union { + __IO uint16_t IRQ046MONH; + struct { + __IO uint8_t IRQ046MONHL; + __IO uint8_t IRQ046MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ047MON; + stc_intreq_irq047mon_field_t IRQ047MON_f; + struct { + union { + __IO uint16_t IRQ047MONL; + struct { + __IO uint8_t IRQ047MONLL; + __IO uint8_t IRQ047MONLH; + }; + }; + union { + __IO uint16_t IRQ047MONH; + struct { + __IO uint8_t IRQ047MONHL; + __IO uint8_t IRQ047MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ048MON; + stc_intreq_irq048mon_field_t IRQ048MON_f; + struct { + union { + __IO uint16_t IRQ048MONL; + struct { + __IO uint8_t IRQ048MONLL; + __IO uint8_t IRQ048MONLH; + }; + }; + union { + __IO uint16_t IRQ048MONH; + struct { + __IO uint8_t IRQ048MONHL; + __IO uint8_t IRQ048MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ049MON; + stc_intreq_irq049mon_field_t IRQ049MON_f; + struct { + union { + __IO uint16_t IRQ049MONL; + struct { + __IO uint8_t IRQ049MONLL; + __IO uint8_t IRQ049MONLH; + }; + }; + union { + __IO uint16_t IRQ049MONH; + struct { + __IO uint8_t IRQ049MONHL; + __IO uint8_t IRQ049MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ050MON; + stc_intreq_irq050mon_field_t IRQ050MON_f; + struct { + union { + __IO uint16_t IRQ050MONL; + struct { + __IO uint8_t IRQ050MONLL; + __IO uint8_t IRQ050MONLH; + }; + }; + union { + __IO uint16_t IRQ050MONH; + struct { + __IO uint8_t IRQ050MONHL; + __IO uint8_t IRQ050MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ051MON; + stc_intreq_irq051mon_field_t IRQ051MON_f; + struct { + union { + __IO uint16_t IRQ051MONL; + struct { + __IO uint8_t IRQ051MONLL; + __IO uint8_t IRQ051MONLH; + }; + }; + union { + __IO uint16_t IRQ051MONH; + struct { + __IO uint8_t IRQ051MONHL; + __IO uint8_t IRQ051MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ052MON; + stc_intreq_irq052mon_field_t IRQ052MON_f; + struct { + union { + __IO uint16_t IRQ052MONL; + struct { + __IO uint8_t IRQ052MONLL; + __IO uint8_t IRQ052MONLH; + }; + }; + union { + __IO uint16_t IRQ052MONH; + struct { + __IO uint8_t IRQ052MONHL; + __IO uint8_t IRQ052MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ053MON; + stc_intreq_irq053mon_field_t IRQ053MON_f; + struct { + union { + __IO uint16_t IRQ053MONL; + struct { + __IO uint8_t IRQ053MONLL; + __IO uint8_t IRQ053MONLH; + }; + }; + union { + __IO uint16_t IRQ053MONH; + struct { + __IO uint8_t IRQ053MONHL; + __IO uint8_t IRQ053MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ054MON; + stc_intreq_irq054mon_field_t IRQ054MON_f; + struct { + union { + __IO uint16_t IRQ054MONL; + struct { + __IO uint8_t IRQ054MONLL; + __IO uint8_t IRQ054MONLH; + }; + }; + union { + __IO uint16_t IRQ054MONH; + struct { + __IO uint8_t IRQ054MONHL; + __IO uint8_t IRQ054MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ055MON; + stc_intreq_irq055mon_field_t IRQ055MON_f; + struct { + union { + __IO uint16_t IRQ055MONL; + struct { + __IO uint8_t IRQ055MONLL; + __IO uint8_t IRQ055MONLH; + }; + }; + union { + __IO uint16_t IRQ055MONH; + struct { + __IO uint8_t IRQ055MONHL; + __IO uint8_t IRQ055MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ056MON; + stc_intreq_irq056mon_field_t IRQ056MON_f; + struct { + union { + __IO uint16_t IRQ056MONL; + struct { + __IO uint8_t IRQ056MONLL; + __IO uint8_t IRQ056MONLH; + }; + }; + union { + __IO uint16_t IRQ056MONH; + struct { + __IO uint8_t IRQ056MONHL; + __IO uint8_t IRQ056MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ057MON; + stc_intreq_irq057mon_field_t IRQ057MON_f; + struct { + union { + __IO uint16_t IRQ057MONL; + struct { + __IO uint8_t IRQ057MONLL; + __IO uint8_t IRQ057MONLH; + }; + }; + union { + __IO uint16_t IRQ057MONH; + struct { + __IO uint8_t IRQ057MONHL; + __IO uint8_t IRQ057MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ058MON; + stc_intreq_irq058mon_field_t IRQ058MON_f; + struct { + union { + __IO uint16_t IRQ058MONL; + struct { + __IO uint8_t IRQ058MONLL; + __IO uint8_t IRQ058MONLH; + }; + }; + union { + __IO uint16_t IRQ058MONH; + struct { + __IO uint8_t IRQ058MONHL; + __IO uint8_t IRQ058MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ059MON; + stc_intreq_irq059mon_field_t IRQ059MON_f; + struct { + union { + __IO uint16_t IRQ059MONL; + struct { + __IO uint8_t IRQ059MONLL; + __IO uint8_t IRQ059MONLH; + }; + }; + union { + __IO uint16_t IRQ059MONH; + struct { + __IO uint8_t IRQ059MONHL; + __IO uint8_t IRQ059MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ060MON; + stc_intreq_irq060mon_field_t IRQ060MON_f; + struct { + union { + __IO uint16_t IRQ060MONL; + struct { + __IO uint8_t IRQ060MONLL; + __IO uint8_t IRQ060MONLH; + }; + }; + union { + __IO uint16_t IRQ060MONH; + struct { + __IO uint8_t IRQ060MONHL; + __IO uint8_t IRQ060MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ061MON; + stc_intreq_irq061mon_field_t IRQ061MON_f; + struct { + union { + __IO uint16_t IRQ061MONL; + struct { + __IO uint8_t IRQ061MONLL; + __IO uint8_t IRQ061MONLH; + }; + }; + union { + __IO uint16_t IRQ061MONH; + struct { + __IO uint8_t IRQ061MONHL; + __IO uint8_t IRQ061MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ062MON; + stc_intreq_irq062mon_field_t IRQ062MON_f; + struct { + union { + __IO uint16_t IRQ062MONL; + struct { + __IO uint8_t IRQ062MONLL; + __IO uint8_t IRQ062MONLH; + }; + }; + union { + __IO uint16_t IRQ062MONH; + struct { + __IO uint8_t IRQ062MONHL; + __IO uint8_t IRQ062MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ063MON; + stc_intreq_irq063mon_field_t IRQ063MON_f; + struct { + union { + __IO uint16_t IRQ063MONL; + struct { + __IO uint8_t IRQ063MONLL; + __IO uint8_t IRQ063MONLH; + }; + }; + union { + __IO uint16_t IRQ063MONH; + struct { + __IO uint8_t IRQ063MONHL; + __IO uint8_t IRQ063MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ064MON; + stc_intreq_irq064mon_field_t IRQ064MON_f; + struct { + union { + __IO uint16_t IRQ064MONL; + struct { + __IO uint8_t IRQ064MONLL; + __IO uint8_t IRQ064MONLH; + }; + }; + union { + __IO uint16_t IRQ064MONH; + struct { + __IO uint8_t IRQ064MONHL; + __IO uint8_t IRQ064MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ065MON; + stc_intreq_irq065mon_field_t IRQ065MON_f; + struct { + union { + __IO uint16_t IRQ065MONL; + struct { + __IO uint8_t IRQ065MONLL; + __IO uint8_t IRQ065MONLH; + }; + }; + union { + __IO uint16_t IRQ065MONH; + struct { + __IO uint8_t IRQ065MONHL; + __IO uint8_t IRQ065MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ066MON; + stc_intreq_irq066mon_field_t IRQ066MON_f; + struct { + union { + __IO uint16_t IRQ066MONL; + struct { + __IO uint8_t IRQ066MONLL; + __IO uint8_t IRQ066MONLH; + }; + }; + union { + __IO uint16_t IRQ066MONH; + struct { + __IO uint8_t IRQ066MONHL; + __IO uint8_t IRQ066MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ067MON; + stc_intreq_irq067mon_field_t IRQ067MON_f; + struct { + union { + __IO uint16_t IRQ067MONL; + struct { + __IO uint8_t IRQ067MONLL; + __IO uint8_t IRQ067MONLH; + }; + }; + union { + __IO uint16_t IRQ067MONH; + struct { + __IO uint8_t IRQ067MONHL; + __IO uint8_t IRQ067MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ068MON; + stc_intreq_irq068mon_field_t IRQ068MON_f; + struct { + union { + __IO uint16_t IRQ068MONL; + struct { + __IO uint8_t IRQ068MONLL; + __IO uint8_t IRQ068MONLH; + }; + }; + union { + __IO uint16_t IRQ068MONH; + struct { + __IO uint8_t IRQ068MONHL; + __IO uint8_t IRQ068MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ069MON; + stc_intreq_irq069mon_field_t IRQ069MON_f; + struct { + union { + __IO uint16_t IRQ069MONL; + struct { + __IO uint8_t IRQ069MONLL; + __IO uint8_t IRQ069MONLH; + }; + }; + union { + __IO uint16_t IRQ069MONH; + struct { + __IO uint8_t IRQ069MONHL; + __IO uint8_t IRQ069MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ070MON; + stc_intreq_irq070mon_field_t IRQ070MON_f; + struct { + union { + __IO uint16_t IRQ070MONL; + struct { + __IO uint8_t IRQ070MONLL; + __IO uint8_t IRQ070MONLH; + }; + }; + union { + __IO uint16_t IRQ070MONH; + struct { + __IO uint8_t IRQ070MONHL; + __IO uint8_t IRQ070MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ071MON; + stc_intreq_irq071mon_field_t IRQ071MON_f; + struct { + union { + __IO uint16_t IRQ071MONL; + struct { + __IO uint8_t IRQ071MONLL; + __IO uint8_t IRQ071MONLH; + }; + }; + union { + __IO uint16_t IRQ071MONH; + struct { + __IO uint8_t IRQ071MONHL; + __IO uint8_t IRQ071MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ072MON; + stc_intreq_irq072mon_field_t IRQ072MON_f; + struct { + union { + __IO uint16_t IRQ072MONL; + struct { + __IO uint8_t IRQ072MONLL; + __IO uint8_t IRQ072MONLH; + }; + }; + union { + __IO uint16_t IRQ072MONH; + struct { + __IO uint8_t IRQ072MONHL; + __IO uint8_t IRQ072MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ073MON; + stc_intreq_irq073mon_field_t IRQ073MON_f; + struct { + union { + __IO uint16_t IRQ073MONL; + struct { + __IO uint8_t IRQ073MONLL; + __IO uint8_t IRQ073MONLH; + }; + }; + union { + __IO uint16_t IRQ073MONH; + struct { + __IO uint8_t IRQ073MONHL; + __IO uint8_t IRQ073MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ074MON; + stc_intreq_irq074mon_field_t IRQ074MON_f; + struct { + union { + __IO uint16_t IRQ074MONL; + struct { + __IO uint8_t IRQ074MONLL; + __IO uint8_t IRQ074MONLH; + }; + }; + union { + __IO uint16_t IRQ074MONH; + struct { + __IO uint8_t IRQ074MONHL; + __IO uint8_t IRQ074MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ075MON; + stc_intreq_irq075mon_field_t IRQ075MON_f; + struct { + union { + __IO uint16_t IRQ075MONL; + struct { + __IO uint8_t IRQ075MONLL; + __IO uint8_t IRQ075MONLH; + }; + }; + union { + __IO uint16_t IRQ075MONH; + struct { + __IO uint8_t IRQ075MONHL; + __IO uint8_t IRQ075MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ076MON; + stc_intreq_irq076mon_field_t IRQ076MON_f; + struct { + union { + __IO uint16_t IRQ076MONL; + struct { + __IO uint8_t IRQ076MONLL; + __IO uint8_t IRQ076MONLH; + }; + }; + union { + __IO uint16_t IRQ076MONH; + struct { + __IO uint8_t IRQ076MONHL; + __IO uint8_t IRQ076MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ077MON; + stc_intreq_irq077mon_field_t IRQ077MON_f; + struct { + union { + __IO uint16_t IRQ077MONL; + struct { + __IO uint8_t IRQ077MONLL; + __IO uint8_t IRQ077MONLH; + }; + }; + union { + __IO uint16_t IRQ077MONH; + struct { + __IO uint8_t IRQ077MONHL; + __IO uint8_t IRQ077MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ078MON; + stc_intreq_irq078mon_field_t IRQ078MON_f; + struct { + union { + __IO uint16_t IRQ078MONL; + struct { + __IO uint8_t IRQ078MONLL; + __IO uint8_t IRQ078MONLH; + }; + }; + union { + __IO uint16_t IRQ078MONH; + struct { + __IO uint8_t IRQ078MONHL; + __IO uint8_t IRQ078MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ079MON; + stc_intreq_irq079mon_field_t IRQ079MON_f; + struct { + union { + __IO uint16_t IRQ079MONL; + struct { + __IO uint8_t IRQ079MONLL; + __IO uint8_t IRQ079MONLH; + }; + }; + union { + __IO uint16_t IRQ079MONH; + struct { + __IO uint8_t IRQ079MONHL; + __IO uint8_t IRQ079MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ080MON; + stc_intreq_irq080mon_field_t IRQ080MON_f; + struct { + union { + __IO uint16_t IRQ080MONL; + struct { + __IO uint8_t IRQ080MONLL; + __IO uint8_t IRQ080MONLH; + }; + }; + union { + __IO uint16_t IRQ080MONH; + struct { + __IO uint8_t IRQ080MONHL; + __IO uint8_t IRQ080MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ081MON; + stc_intreq_irq081mon_field_t IRQ081MON_f; + struct { + union { + __IO uint16_t IRQ081MONL; + struct { + __IO uint8_t IRQ081MONLL; + __IO uint8_t IRQ081MONLH; + }; + }; + union { + __IO uint16_t IRQ081MONH; + struct { + __IO uint8_t IRQ081MONHL; + __IO uint8_t IRQ081MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ082MON; + stc_intreq_irq082mon_field_t IRQ082MON_f; + struct { + union { + __IO uint16_t IRQ082MONL; + struct { + __IO uint8_t IRQ082MONLL; + __IO uint8_t IRQ082MONLH; + }; + }; + union { + __IO uint16_t IRQ082MONH; + struct { + __IO uint8_t IRQ082MONHL; + __IO uint8_t IRQ082MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ083MON; + stc_intreq_irq083mon_field_t IRQ083MON_f; + struct { + union { + __IO uint16_t IRQ083MONL; + struct { + __IO uint8_t IRQ083MONLL; + __IO uint8_t IRQ083MONLH; + }; + }; + union { + __IO uint16_t IRQ083MONH; + struct { + __IO uint8_t IRQ083MONHL; + __IO uint8_t IRQ083MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ084MON; + stc_intreq_irq084mon_field_t IRQ084MON_f; + struct { + union { + __IO uint16_t IRQ084MONL; + struct { + __IO uint8_t IRQ084MONLL; + __IO uint8_t IRQ084MONLH; + }; + }; + union { + __IO uint16_t IRQ084MONH; + struct { + __IO uint8_t IRQ084MONHL; + __IO uint8_t IRQ084MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ085MON; + stc_intreq_irq085mon_field_t IRQ085MON_f; + struct { + union { + __IO uint16_t IRQ085MONL; + struct { + __IO uint8_t IRQ085MONLL; + __IO uint8_t IRQ085MONLH; + }; + }; + union { + __IO uint16_t IRQ085MONH; + struct { + __IO uint8_t IRQ085MONHL; + __IO uint8_t IRQ085MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ086MON; + stc_intreq_irq086mon_field_t IRQ086MON_f; + struct { + union { + __IO uint16_t IRQ086MONL; + struct { + __IO uint8_t IRQ086MONLL; + __IO uint8_t IRQ086MONLH; + }; + }; + union { + __IO uint16_t IRQ086MONH; + struct { + __IO uint8_t IRQ086MONHL; + __IO uint8_t IRQ086MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ087MON; + stc_intreq_irq087mon_field_t IRQ087MON_f; + struct { + union { + __IO uint16_t IRQ087MONL; + struct { + __IO uint8_t IRQ087MONLL; + __IO uint8_t IRQ087MONLH; + }; + }; + union { + __IO uint16_t IRQ087MONH; + struct { + __IO uint8_t IRQ087MONHL; + __IO uint8_t IRQ087MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ088MON; + stc_intreq_irq088mon_field_t IRQ088MON_f; + struct { + union { + __IO uint16_t IRQ088MONL; + struct { + __IO uint8_t IRQ088MONLL; + __IO uint8_t IRQ088MONLH; + }; + }; + union { + __IO uint16_t IRQ088MONH; + struct { + __IO uint8_t IRQ088MONHL; + __IO uint8_t IRQ088MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ089MON; + stc_intreq_irq089mon_field_t IRQ089MON_f; + struct { + union { + __IO uint16_t IRQ089MONL; + struct { + __IO uint8_t IRQ089MONLL; + __IO uint8_t IRQ089MONLH; + }; + }; + union { + __IO uint16_t IRQ089MONH; + struct { + __IO uint8_t IRQ089MONHL; + __IO uint8_t IRQ089MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ090MON; + stc_intreq_irq090mon_field_t IRQ090MON_f; + struct { + union { + __IO uint16_t IRQ090MONL; + struct { + __IO uint8_t IRQ090MONLL; + __IO uint8_t IRQ090MONLH; + }; + }; + union { + __IO uint16_t IRQ090MONH; + struct { + __IO uint8_t IRQ090MONHL; + __IO uint8_t IRQ090MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ091MON; + stc_intreq_irq091mon_field_t IRQ091MON_f; + struct { + union { + __IO uint16_t IRQ091MONL; + struct { + __IO uint8_t IRQ091MONLL; + __IO uint8_t IRQ091MONLH; + }; + }; + union { + __IO uint16_t IRQ091MONH; + struct { + __IO uint8_t IRQ091MONHL; + __IO uint8_t IRQ091MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ092MON; + stc_intreq_irq092mon_field_t IRQ092MON_f; + struct { + union { + __IO uint16_t IRQ092MONL; + struct { + __IO uint8_t IRQ092MONLL; + __IO uint8_t IRQ092MONLH; + }; + }; + union { + __IO uint16_t IRQ092MONH; + struct { + __IO uint8_t IRQ092MONHL; + __IO uint8_t IRQ092MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ093MON; + stc_intreq_irq093mon_field_t IRQ093MON_f; + struct { + union { + __IO uint16_t IRQ093MONL; + struct { + __IO uint8_t IRQ093MONLL; + __IO uint8_t IRQ093MONLH; + }; + }; + union { + __IO uint16_t IRQ093MONH; + struct { + __IO uint8_t IRQ093MONHL; + __IO uint8_t IRQ093MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ094MON; + stc_intreq_irq094mon_field_t IRQ094MON_f; + struct { + union { + __IO uint16_t IRQ094MONL; + struct { + __IO uint8_t IRQ094MONLL; + __IO uint8_t IRQ094MONLH; + }; + }; + union { + __IO uint16_t IRQ094MONH; + struct { + __IO uint8_t IRQ094MONHL; + __IO uint8_t IRQ094MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ095MON; + stc_intreq_irq095mon_field_t IRQ095MON_f; + struct { + union { + __IO uint16_t IRQ095MONL; + struct { + __IO uint8_t IRQ095MONLL; + __IO uint8_t IRQ095MONLH; + }; + }; + union { + __IO uint16_t IRQ095MONH; + struct { + __IO uint8_t IRQ095MONHL; + __IO uint8_t IRQ095MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ096MON; + stc_intreq_irq096mon_field_t IRQ096MON_f; + struct { + union { + __IO uint16_t IRQ096MONL; + struct { + __IO uint8_t IRQ096MONLL; + __IO uint8_t IRQ096MONLH; + }; + }; + union { + __IO uint16_t IRQ096MONH; + struct { + __IO uint8_t IRQ096MONHL; + __IO uint8_t IRQ096MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ097MON; + stc_intreq_irq097mon_field_t IRQ097MON_f; + struct { + union { + __IO uint16_t IRQ097MONL; + struct { + __IO uint8_t IRQ097MONLL; + __IO uint8_t IRQ097MONLH; + }; + }; + union { + __IO uint16_t IRQ097MONH; + struct { + __IO uint8_t IRQ097MONHL; + __IO uint8_t IRQ097MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ098MON; + stc_intreq_irq098mon_field_t IRQ098MON_f; + struct { + union { + __IO uint16_t IRQ098MONL; + struct { + __IO uint8_t IRQ098MONLL; + __IO uint8_t IRQ098MONLH; + }; + }; + union { + __IO uint16_t IRQ098MONH; + struct { + __IO uint8_t IRQ098MONHL; + __IO uint8_t IRQ098MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ099MON; + stc_intreq_irq099mon_field_t IRQ099MON_f; + struct { + union { + __IO uint16_t IRQ099MONL; + struct { + __IO uint8_t IRQ099MONLL; + __IO uint8_t IRQ099MONLH; + }; + }; + union { + __IO uint16_t IRQ099MONH; + struct { + __IO uint8_t IRQ099MONHL; + __IO uint8_t IRQ099MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ100MON; + stc_intreq_irq100mon_field_t IRQ100MON_f; + struct { + union { + __IO uint16_t IRQ100MONL; + struct { + __IO uint8_t IRQ100MONLL; + __IO uint8_t IRQ100MONLH; + }; + }; + union { + __IO uint16_t IRQ100MONH; + struct { + __IO uint8_t IRQ100MONHL; + __IO uint8_t IRQ100MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ101MON; + stc_intreq_irq101mon_field_t IRQ101MON_f; + struct { + union { + __IO uint16_t IRQ101MONL; + struct { + __IO uint8_t IRQ101MONLL; + __IO uint8_t IRQ101MONLH; + }; + }; + union { + __IO uint16_t IRQ101MONH; + struct { + __IO uint8_t IRQ101MONHL; + __IO uint8_t IRQ101MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ102MON; + stc_intreq_irq102mon_field_t IRQ102MON_f; + struct { + union { + __IO uint16_t IRQ102MONL; + struct { + __IO uint8_t IRQ102MONLL; + __IO uint8_t IRQ102MONLH; + }; + }; + union { + __IO uint16_t IRQ102MONH; + struct { + __IO uint8_t IRQ102MONHL; + __IO uint8_t IRQ102MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ103MON; + stc_intreq_irq103mon_field_t IRQ103MON_f; + struct { + union { + __IO uint16_t IRQ103MONL; + struct { + __IO uint8_t IRQ103MONLL; + __IO uint8_t IRQ103MONLH; + }; + }; + union { + __IO uint16_t IRQ103MONH; + struct { + __IO uint8_t IRQ103MONHL; + __IO uint8_t IRQ103MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ104MON; + stc_intreq_irq104mon_field_t IRQ104MON_f; + struct { + union { + __IO uint16_t IRQ104MONL; + struct { + __IO uint8_t IRQ104MONLL; + __IO uint8_t IRQ104MONLH; + }; + }; + union { + __IO uint16_t IRQ104MONH; + struct { + __IO uint8_t IRQ104MONHL; + __IO uint8_t IRQ104MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ105MON; + stc_intreq_irq105mon_field_t IRQ105MON_f; + struct { + union { + __IO uint16_t IRQ105MONL; + struct { + __IO uint8_t IRQ105MONLL; + __IO uint8_t IRQ105MONLH; + }; + }; + union { + __IO uint16_t IRQ105MONH; + struct { + __IO uint8_t IRQ105MONHL; + __IO uint8_t IRQ105MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ106MON; + stc_intreq_irq106mon_field_t IRQ106MON_f; + struct { + union { + __IO uint16_t IRQ106MONL; + struct { + __IO uint8_t IRQ106MONLL; + __IO uint8_t IRQ106MONLH; + }; + }; + union { + __IO uint16_t IRQ106MONH; + struct { + __IO uint8_t IRQ106MONHL; + __IO uint8_t IRQ106MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ107MON; + stc_intreq_irq107mon_field_t IRQ107MON_f; + struct { + union { + __IO uint16_t IRQ107MONL; + struct { + __IO uint8_t IRQ107MONLL; + __IO uint8_t IRQ107MONLH; + }; + }; + union { + __IO uint16_t IRQ107MONH; + struct { + __IO uint8_t IRQ107MONHL; + __IO uint8_t IRQ107MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ108MON; + stc_intreq_irq108mon_field_t IRQ108MON_f; + struct { + union { + __IO uint16_t IRQ108MONL; + struct { + __IO uint8_t IRQ108MONLL; + __IO uint8_t IRQ108MONLH; + }; + }; + union { + __IO uint16_t IRQ108MONH; + struct { + __IO uint8_t IRQ108MONHL; + __IO uint8_t IRQ108MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ109MON; + stc_intreq_irq109mon_field_t IRQ109MON_f; + struct { + union { + __IO uint16_t IRQ109MONL; + struct { + __IO uint8_t IRQ109MONLL; + __IO uint8_t IRQ109MONLH; + }; + }; + union { + __IO uint16_t IRQ109MONH; + struct { + __IO uint8_t IRQ109MONHL; + __IO uint8_t IRQ109MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ110MON; + stc_intreq_irq110mon_field_t IRQ110MON_f; + struct { + union { + __IO uint16_t IRQ110MONL; + struct { + __IO uint8_t IRQ110MONLL; + __IO uint8_t IRQ110MONLH; + }; + }; + union { + __IO uint16_t IRQ110MONH; + struct { + __IO uint8_t IRQ110MONHL; + __IO uint8_t IRQ110MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ111MON; + stc_intreq_irq111mon_field_t IRQ111MON_f; + struct { + union { + __IO uint16_t IRQ111MONL; + struct { + __IO uint8_t IRQ111MONLL; + __IO uint8_t IRQ111MONLH; + }; + }; + union { + __IO uint16_t IRQ111MONH; + struct { + __IO uint8_t IRQ111MONHL; + __IO uint8_t IRQ111MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ112MON; + stc_intreq_irq112mon_field_t IRQ112MON_f; + struct { + union { + __IO uint16_t IRQ112MONL; + struct { + __IO uint8_t IRQ112MONLL; + __IO uint8_t IRQ112MONLH; + }; + }; + union { + __IO uint16_t IRQ112MONH; + struct { + __IO uint8_t IRQ112MONHL; + __IO uint8_t IRQ112MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ113MON; + stc_intreq_irq113mon_field_t IRQ113MON_f; + struct { + union { + __IO uint16_t IRQ113MONL; + struct { + __IO uint8_t IRQ113MONLL; + __IO uint8_t IRQ113MONLH; + }; + }; + union { + __IO uint16_t IRQ113MONH; + struct { + __IO uint8_t IRQ113MONHL; + __IO uint8_t IRQ113MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ114MON; + stc_intreq_irq114mon_field_t IRQ114MON_f; + struct { + union { + __IO uint16_t IRQ114MONL; + struct { + __IO uint8_t IRQ114MONLL; + __IO uint8_t IRQ114MONLH; + }; + }; + union { + __IO uint16_t IRQ114MONH; + struct { + __IO uint8_t IRQ114MONHL; + __IO uint8_t IRQ114MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ115MON; + stc_intreq_irq115mon_field_t IRQ115MON_f; + struct { + union { + __IO uint16_t IRQ115MONL; + struct { + __IO uint8_t IRQ115MONLL; + __IO uint8_t IRQ115MONLH; + }; + }; + union { + __IO uint16_t IRQ115MONH; + struct { + __IO uint8_t IRQ115MONHL; + __IO uint8_t IRQ115MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ116MON; + struct { + union { + __IO uint16_t IRQ116MONL; + struct { + __IO uint8_t IRQ116MONLL; + __IO uint8_t IRQ116MONLH; + }; + }; + union { + __IO uint16_t IRQ116MONH; + struct { + __IO uint8_t IRQ116MONHL; + __IO uint8_t IRQ116MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ117MON; + stc_intreq_irq117mon_field_t IRQ117MON_f; + struct { + union { + __IO uint16_t IRQ117MONL; + struct { + __IO uint8_t IRQ117MONLL; + __IO uint8_t IRQ117MONLH; + }; + }; + union { + __IO uint16_t IRQ117MONH; + struct { + __IO uint8_t IRQ117MONHL; + __IO uint8_t IRQ117MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ118MON; + stc_intreq_irq118mon_field_t IRQ118MON_f; + struct { + union { + __IO uint16_t IRQ118MONL; + struct { + __IO uint8_t IRQ118MONLL; + __IO uint8_t IRQ118MONLH; + }; + }; + union { + __IO uint16_t IRQ118MONH; + struct { + __IO uint8_t IRQ118MONHL; + __IO uint8_t IRQ118MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ119MON; + stc_intreq_irq119mon_field_t IRQ119MON_f; + struct { + union { + __IO uint16_t IRQ119MONL; + struct { + __IO uint8_t IRQ119MONLL; + __IO uint8_t IRQ119MONLH; + }; + }; + union { + __IO uint16_t IRQ119MONH; + struct { + __IO uint8_t IRQ119MONHL; + __IO uint8_t IRQ119MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ120MON; + stc_intreq_irq120mon_field_t IRQ120MON_f; + struct { + union { + __IO uint16_t IRQ120MONL; + struct { + __IO uint8_t IRQ120MONLL; + __IO uint8_t IRQ120MONLH; + }; + }; + union { + __IO uint16_t IRQ120MONH; + struct { + __IO uint8_t IRQ120MONHL; + __IO uint8_t IRQ120MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ121MON; + stc_intreq_irq121mon_field_t IRQ121MON_f; + struct { + union { + __IO uint16_t IRQ121MONL; + struct { + __IO uint8_t IRQ121MONLL; + __IO uint8_t IRQ121MONLH; + }; + }; + union { + __IO uint16_t IRQ121MONH; + struct { + __IO uint8_t IRQ121MONHL; + __IO uint8_t IRQ121MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ122MON; + stc_intreq_irq122mon_field_t IRQ122MON_f; + struct { + union { + __IO uint16_t IRQ122MONL; + struct { + __IO uint8_t IRQ122MONLL; + __IO uint8_t IRQ122MONLH; + }; + }; + union { + __IO uint16_t IRQ122MONH; + struct { + __IO uint8_t IRQ122MONHL; + __IO uint8_t IRQ122MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ123MON; + stc_intreq_irq123mon_field_t IRQ123MON_f; + struct { + union { + __IO uint16_t IRQ123MONL; + struct { + __IO uint8_t IRQ123MONLL; + __IO uint8_t IRQ123MONLH; + }; + }; + union { + __IO uint16_t IRQ123MONH; + struct { + __IO uint8_t IRQ123MONHL; + __IO uint8_t IRQ123MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ124MON; + stc_intreq_irq124mon_field_t IRQ124MON_f; + struct { + union { + __IO uint16_t IRQ124MONL; + struct { + __IO uint8_t IRQ124MONLL; + __IO uint8_t IRQ124MONLH; + }; + }; + union { + __IO uint16_t IRQ124MONH; + struct { + __IO uint8_t IRQ124MONHL; + __IO uint8_t IRQ124MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ125MON; + stc_intreq_irq125mon_field_t IRQ125MON_f; + struct { + union { + __IO uint16_t IRQ125MONL; + struct { + __IO uint8_t IRQ125MONLL; + __IO uint8_t IRQ125MONLH; + }; + }; + union { + __IO uint16_t IRQ125MONH; + struct { + __IO uint8_t IRQ125MONHL; + __IO uint8_t IRQ125MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ126MON; + stc_intreq_irq126mon_field_t IRQ126MON_f; + struct { + union { + __IO uint16_t IRQ126MONL; + struct { + __IO uint8_t IRQ126MONLL; + __IO uint8_t IRQ126MONLH; + }; + }; + union { + __IO uint16_t IRQ126MONH; + struct { + __IO uint8_t IRQ126MONHL; + __IO uint8_t IRQ126MONHH; + }; + }; + }; + }; + union { + __IO uint32_t IRQ127MON; + stc_intreq_irq127mon_field_t IRQ127MON_f; + struct { + union { + __IO uint16_t IRQ127MONL; + struct { + __IO uint8_t IRQ127MONLL; + __IO uint8_t IRQ127MONLH; + }; + }; + union { + __IO uint16_t IRQ127MONH; + struct { + __IO uint8_t IRQ127MONHL; + __IO uint8_t IRQ127MONHH; + }; + }; + }; + }; +} FM_INTREQ_TypeDef, FM4_INTREQ_TypeDef; + +/******************************************************************************* +* LSCRP_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t LCR_PRSLD; + stc_lscrp_lcr_prsld_field_t LCR_PRSLD_f; + }; +} FM_LSCRP_TypeDef, FM4_LSCRP_TypeDef; + +/******************************************************************************* +* LVD_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t LVD_CTL; + stc_lvd_lvd_ctl_field_t LVD_CTL_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t LVD_STR; + stc_lvd_lvd_str_field_t LVD_STR_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t LVD_CLR; + stc_lvd_lvd_clr_field_t LVD_CLR_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint32_t LVD_RLR; + stc_lvd_lvd_rlr_field_t LVD_RLR_f; + struct { + union { + __IO uint16_t LVD_RLRL; + struct { + __IO uint8_t LVD_RLRLL; + __IO uint8_t LVD_RLRLH; + }; + }; + union { + __IO uint16_t LVD_RLRH; + struct { + __IO uint8_t LVD_RLRHL; + __IO uint8_t LVD_RLRHH; + }; + }; + }; + }; + union { + __IO uint8_t LVD_STR2; + stc_lvd_lvd_str2_field_t LVD_STR2_f; + }; +} FM_LVD_TypeDef, FM4_LVD_TypeDef; + +/******************************************************************************* +* MFS_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_smr_field_t SMR_f; + __IO uint8_t CSIO_SMR; + stc_mfs_csio_smr_field_t CSIO_SMR_f; + __IO uint8_t I2C_SMR; + stc_mfs_i2c_smr_field_t I2C_SMR_f; + __IO uint8_t LIN_SMR; + stc_mfs_lin_smr_field_t LIN_SMR_f; + __IO uint8_t UART_SMR; + stc_mfs_uart_smr_field_t UART_SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_scr_field_t SCR_f; + __IO uint8_t CSIO_SCR; + stc_mfs_csio_scr_field_t CSIO_SCR_f; + __IO uint8_t IBCR; + stc_mfs_ibcr_field_t IBCR_f; + __IO uint8_t I2C_IBCR; + stc_mfs_i2c_ibcr_field_t I2C_IBCR_f; + __IO uint8_t LIN_SCR; + stc_mfs_lin_scr_field_t LIN_SCR_f; + __IO uint8_t UART_SCR; + stc_mfs_uart_scr_field_t UART_SCR_f; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint8_t ESCR; + stc_mfs_escr_field_t ESCR_f; + __IO uint8_t CSIO_ESCR; + stc_mfs_csio_escr_field_t CSIO_ESCR_f; + __IO uint8_t IBSR; + stc_mfs_ibsr_field_t IBSR_f; + __IO uint8_t I2C_IBSR; + stc_mfs_i2c_ibsr_field_t I2C_IBSR_f; + __IO uint8_t LIN_ESCR; + stc_mfs_lin_escr_field_t LIN_ESCR_f; + __IO uint8_t UART_ESCR; + stc_mfs_uart_escr_field_t UART_ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_ssr_field_t SSR_f; + __IO uint8_t CSIO_SSR; + stc_mfs_csio_ssr_field_t CSIO_SSR_f; + __IO uint8_t I2C_SSR; + stc_mfs_i2c_ssr_field_t I2C_SSR_f; + __IO uint8_t LIN_SSR; + stc_mfs_lin_ssr_field_t LIN_SSR_f; + __IO uint8_t UART_SSR; + stc_mfs_uart_ssr_field_t UART_SSR_f; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t RDR; + stc_mfs_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t CSIO_RDR; + stc_mfs_csio_rdr_field_t CSIO_RDR_f; + struct { + __IO uint8_t CSIO_RDRL; + __IO uint8_t CSIO_RDRH; + }; + __IO uint16_t TDR; + stc_mfs_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + __IO uint16_t CSIO_TDR; + stc_mfs_csio_tdr_field_t CSIO_TDR_f; + struct { + __IO uint8_t CSIO_TDRL; + __IO uint8_t CSIO_TDRH; + }; + __IO uint16_t I2C_RDR; + stc_mfs_i2c_rdr_field_t I2C_RDR_f; + struct { + __IO uint8_t I2C_RDRL; + __IO uint8_t I2C_RDRH; + }; + __IO uint16_t I2C_TDR; + stc_mfs_i2c_tdr_field_t I2C_TDR_f; + struct { + __IO uint8_t I2C_TDRL; + __IO uint8_t I2C_TDRH; + }; + __IO uint16_t LIN_RDR; + stc_mfs_lin_rdr_field_t LIN_RDR_f; + struct { + __IO uint8_t LIN_RDRL; + __IO uint8_t LIN_RDRH; + }; + __IO uint16_t LIN_TDR; + stc_mfs_lin_tdr_field_t LIN_TDR_f; + struct { + __IO uint8_t LIN_TDRL; + __IO uint8_t LIN_TDRH; + }; + __IO uint16_t UART_RDR; + stc_mfs_uart_rdr_field_t UART_RDR_f; + struct { + __IO uint8_t UART_RDRL; + __IO uint8_t UART_RDRH; + }; + __IO uint16_t UART_TDR; + stc_mfs_uart_tdr_field_t UART_TDR_f; + struct { + __IO uint8_t UART_TDRL; + __IO uint8_t UART_TDRH; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t BGR; + stc_mfs_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + __IO uint16_t CSIO_BGR; + stc_mfs_csio_bgr_field_t CSIO_BGR_f; + struct { + __IO uint8_t CSIO_BGRL; + __IO uint8_t CSIO_BGRH; + }; + __IO uint16_t I2C_BGR; + stc_mfs_i2c_bgr_field_t I2C_BGR_f; + struct { + __IO uint8_t I2C_BGRL; + __IO uint8_t I2C_BGRH; + }; + __IO uint16_t LIN_BGR; + stc_mfs_lin_bgr_field_t LIN_BGR_f; + struct { + __IO uint8_t LIN_BGRL; + __IO uint8_t LIN_BGRH; + }; + __IO uint16_t UART_BGR; + stc_mfs_uart_bgr_field_t UART_BGR_f; + struct { + __IO uint8_t UART_BGRL; + __IO uint8_t UART_BGRH; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint8_t ISBA; + stc_mfs_isba_field_t ISBA_f; + __IO uint8_t I2C_ISBA; + stc_mfs_i2c_isba_field_t I2C_ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs_ismk_field_t ISMK_f; + __IO uint8_t I2C_ISMK; + stc_mfs_i2c_ismk_field_t I2C_ISMK_f; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t FCR; + stc_mfs_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + __IO uint16_t CSIO_FCR; + stc_mfs_csio_fcr_field_t CSIO_FCR_f; + struct { + __IO uint8_t CSIO_FCRL; + __IO uint8_t CSIO_FCRH; + }; + __IO uint16_t I2C_FCR; + stc_mfs_i2c_fcr_field_t I2C_FCR_f; + struct { + __IO uint8_t I2C_FCRL; + __IO uint8_t I2C_FCRH; + }; + __IO uint16_t LIN_FCR; + stc_mfs_lin_fcr_field_t LIN_FCR_f; + struct { + __IO uint8_t LIN_FCRL; + __IO uint8_t LIN_FCRH; + }; + __IO uint16_t UART_FCR; + stc_mfs_uart_fcr_field_t UART_FCR_f; + struct { + __IO uint8_t UART_FCRL; + __IO uint8_t UART_FCRH; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_fbyte1_field_t FBYTE1_f; + __IO uint8_t CSIO_FBYTE1; + stc_mfs_csio_fbyte1_field_t CSIO_FBYTE1_f; + __IO uint8_t I2C_FBYTE1; + stc_mfs_i2c_fbyte1_field_t I2C_FBYTE1_f; + __IO uint8_t LIN_FBYTE1; + stc_mfs_lin_fbyte1_field_t LIN_FBYTE1_f; + __IO uint8_t UART_FBYTE1; + stc_mfs_uart_fbyte1_field_t UART_FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_fbyte2_field_t FBYTE2_f; + __IO uint8_t CSIO_FBYTE2; + stc_mfs_csio_fbyte2_field_t CSIO_FBYTE2_f; + __IO uint8_t I2C_FBYTE2; + stc_mfs_i2c_fbyte2_field_t I2C_FBYTE2_f; + __IO uint8_t LIN_FBYTE2; + stc_mfs_lin_fbyte2_field_t LIN_FBYTE2_f; + __IO uint8_t UART_FBYTE2; + stc_mfs_uart_fbyte2_field_t UART_FBYTE2_f; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint8_t SCSTR0; + stc_mfs_scstr0_field_t SCSTR0_f; + __IO uint8_t CSIO_SCSTR0; + stc_mfs_csio_scstr0_field_t CSIO_SCSTR0_f; + __IO uint8_t NFCR; + stc_mfs_nfcr_field_t NFCR_f; + __IO uint8_t I2C_NFCR; + stc_mfs_i2c_nfcr_field_t I2C_NFCR_f; + }; + union { + __IO uint8_t SCSTR1; + stc_mfs_scstr1_field_t SCSTR1_f; + __IO uint8_t CSIO_SCSTR1; + stc_mfs_csio_scstr1_field_t CSIO_SCSTR1_f; + __IO uint8_t EIBCR; + stc_mfs_eibcr_field_t EIBCR_f; + __IO uint8_t I2C_EIBCR; + stc_mfs_i2c_eibcr_field_t I2C_EIBCR_f; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint16_t SCSTR32; + stc_mfs_scstr32_field_t SCSTR32_f; + struct { + __IO uint8_t SCSTR32L; + __IO uint8_t SCSTR32H; + }; + __IO uint16_t CSIO_SCSTR32; + stc_mfs_csio_scstr32_field_t CSIO_SCSTR32_f; + struct { + __IO uint8_t CSIO_SCSTR32L; + __IO uint8_t CSIO_SCSTR32H; + }; + }; + __IO uint8_t RESERVED8[2]; + union { + __IO uint16_t SACSR; + stc_mfs_sacsr_field_t SACSR_f; + struct { + __IO uint8_t SACSRL; + __IO uint8_t SACSRH; + }; + __IO uint16_t CSIO_SACSR; + stc_mfs_csio_sacsr_field_t CSIO_SACSR_f; + struct { + __IO uint8_t CSIO_SACSRL; + __IO uint8_t CSIO_SACSRH; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint16_t STMR; + stc_mfs_stmr_field_t STMR_f; + struct { + __IO uint8_t STMRL; + __IO uint8_t STMRH; + }; + __IO uint16_t CSIO_STMR; + stc_mfs_csio_stmr_field_t CSIO_STMR_f; + struct { + __IO uint8_t CSIO_STMRL; + __IO uint8_t CSIO_STMRH; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint16_t STMCR; + stc_mfs_stmcr_field_t STMCR_f; + struct { + __IO uint8_t STMCRL; + __IO uint8_t STMCRH; + }; + __IO uint16_t CSIO_STMCR; + stc_mfs_csio_stmcr_field_t CSIO_STMCR_f; + struct { + __IO uint8_t CSIO_STMCRL; + __IO uint8_t CSIO_STMCRH; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t SCSCR; + stc_mfs_scscr_field_t SCSCR_f; + struct { + __IO uint8_t SCSCRL; + __IO uint8_t SCSCRH; + }; + __IO uint16_t CSIO_SCSCR; + stc_mfs_csio_scscr_field_t CSIO_SCSCR_f; + struct { + __IO uint8_t CSIO_SCSCRL; + __IO uint8_t CSIO_SCSCRH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint8_t SCSFR0; + stc_mfs_scsfr0_field_t SCSFR0_f; + __IO uint8_t CSIO_SCSFR0; + stc_mfs_csio_scsfr0_field_t CSIO_SCSFR0_f; + }; + union { + __IO uint8_t SCSFR1; + stc_mfs_scsfr1_field_t SCSFR1_f; + __IO uint8_t CSIO_SCSFR1; + stc_mfs_csio_scsfr1_field_t CSIO_SCSFR1_f; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint8_t SCSFR2; + stc_mfs_scsfr2_field_t SCSFR2_f; + __IO uint8_t CSIO_SCSFR2; + stc_mfs_csio_scsfr2_field_t CSIO_SCSFR2_f; + }; + __IO uint8_t RESERVED14[3]; + union { + __IO uint8_t TBYTE0; + __IO uint8_t CSIO_TBYTE0; + }; + union { + __IO uint8_t TBYTE1; + __IO uint8_t CSIO_TBYTE1; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint8_t TBYTE2; + __IO uint8_t CSIO_TBYTE2; + }; + union { + __IO uint8_t TBYTE3; + __IO uint8_t CSIO_TBYTE3; + }; +} FM_MFS_TypeDef, FM4_MFS_TypeDef; + +/******************************************************************************* +* MFS_CSIO_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_csio_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_csio_scr_field_t SCR_f; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint8_t ESCR; + stc_mfs_csio_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_csio_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED17[2]; + union { + __IO uint16_t RDR; + stc_mfs_csio_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_csio_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint16_t BGR; + stc_mfs_csio_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED19[6]; + union { + __IO uint16_t FCR; + stc_mfs_csio_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_csio_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_csio_fbyte2_field_t FBYTE2_f; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint8_t SCSTR0; + stc_mfs_csio_scstr0_field_t SCSTR0_f; + }; + union { + __IO uint8_t SCSTR1; + stc_mfs_csio_scstr1_field_t SCSTR1_f; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint16_t SCSTR32; + stc_mfs_csio_scstr32_field_t SCSTR32_f; + struct { + __IO uint8_t SCSTR32L; + __IO uint8_t SCSTR32H; + }; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint16_t SACSR; + stc_mfs_csio_sacsr_field_t SACSR_f; + struct { + __IO uint8_t SACSRL; + __IO uint8_t SACSRH; + }; + }; + __IO uint8_t RESERVED24[2]; + union { + __IO uint16_t STMR; + stc_mfs_csio_stmr_field_t STMR_f; + struct { + __IO uint8_t STMRL; + __IO uint8_t STMRH; + }; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint16_t STMCR; + stc_mfs_csio_stmcr_field_t STMCR_f; + struct { + __IO uint8_t STMCRL; + __IO uint8_t STMCRH; + }; + }; + __IO uint8_t RESERVED26[2]; + union { + __IO uint16_t SCSCR; + stc_mfs_csio_scscr_field_t SCSCR_f; + struct { + __IO uint8_t SCSCRL; + __IO uint8_t SCSCRH; + }; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint8_t SCSFR0; + stc_mfs_csio_scsfr0_field_t SCSFR0_f; + }; + union { + __IO uint8_t SCSFR1; + stc_mfs_csio_scsfr1_field_t SCSFR1_f; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint8_t SCSFR2; + stc_mfs_csio_scsfr2_field_t SCSFR2_f; + }; + __IO uint8_t RESERVED29[3]; + __IO uint8_t TBYTE0; + __IO uint8_t TBYTE1; + __IO uint8_t RESERVED30[2]; + __IO uint8_t TBYTE2; + __IO uint8_t TBYTE3; +} FM_MFS_CSIO_TypeDef, FM4_MFS_CSIO_TypeDef; + +/******************************************************************************* +* MFS_I2C_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_i2c_smr_field_t SMR_f; + }; + union { + __IO uint8_t IBCR; + stc_mfs_i2c_ibcr_field_t IBCR_f; + }; + __IO uint8_t RESERVED31[2]; + union { + __IO uint8_t IBSR; + stc_mfs_i2c_ibsr_field_t IBSR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_i2c_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED32[2]; + union { + __IO uint16_t RDR; + stc_mfs_i2c_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_i2c_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED33[2]; + union { + __IO uint16_t BGR; + stc_mfs_i2c_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED34[2]; + union { + __IO uint8_t ISBA; + stc_mfs_i2c_isba_field_t ISBA_f; + }; + union { + __IO uint8_t ISMK; + stc_mfs_i2c_ismk_field_t ISMK_f; + }; + __IO uint8_t RESERVED35[2]; + union { + __IO uint16_t FCR; + stc_mfs_i2c_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED36[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_i2c_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_i2c_fbyte2_field_t FBYTE2_f; + }; + __IO uint8_t RESERVED37[2]; + union { + __IO uint8_t NFCR; + stc_mfs_i2c_nfcr_field_t NFCR_f; + }; + union { + __IO uint8_t EIBCR; + stc_mfs_i2c_eibcr_field_t EIBCR_f; + }; +} FM_MFS_I2C_TypeDef, FM4_MFS_I2C_TypeDef; + +/******************************************************************************* +* MFS_LIN_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_lin_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_lin_scr_field_t SCR_f; + }; + __IO uint8_t RESERVED38[2]; + union { + __IO uint8_t ESCR; + stc_mfs_lin_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_lin_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED39[2]; + union { + __IO uint16_t RDR; + stc_mfs_lin_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_lin_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED40[2]; + union { + __IO uint16_t BGR; + stc_mfs_lin_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED41[6]; + union { + __IO uint16_t FCR; + stc_mfs_lin_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED42[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_lin_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_lin_fbyte2_field_t FBYTE2_f; + }; +} FM_MFS_LIN_TypeDef, FM4_MFS_LIN_TypeDef; + +/******************************************************************************* +* MFS_UART_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t SMR; + stc_mfs_uart_smr_field_t SMR_f; + }; + union { + __IO uint8_t SCR; + stc_mfs_uart_scr_field_t SCR_f; + }; + __IO uint8_t RESERVED43[2]; + union { + __IO uint8_t ESCR; + stc_mfs_uart_escr_field_t ESCR_f; + }; + union { + __IO uint8_t SSR; + stc_mfs_uart_ssr_field_t SSR_f; + }; + __IO uint8_t RESERVED44[2]; + union { + __IO uint16_t RDR; + stc_mfs_uart_rdr_field_t RDR_f; + struct { + __IO uint8_t RDRL; + __IO uint8_t RDRH; + }; + __IO uint16_t TDR; + stc_mfs_uart_tdr_field_t TDR_f; + struct { + __IO uint8_t TDRL; + __IO uint8_t TDRH; + }; + }; + __IO uint8_t RESERVED45[2]; + union { + __IO uint16_t BGR; + stc_mfs_uart_bgr_field_t BGR_f; + struct { + __IO uint8_t BGRL; + __IO uint8_t BGRH; + }; + }; + __IO uint8_t RESERVED46[6]; + union { + __IO uint16_t FCR; + stc_mfs_uart_fcr_field_t FCR_f; + struct { + __IO uint8_t FCRL; + __IO uint8_t FCRH; + }; + }; + __IO uint8_t RESERVED47[2]; + union { + __IO uint8_t FBYTE1; + stc_mfs_uart_fbyte1_field_t FBYTE1_f; + }; + union { + __IO uint8_t FBYTE2; + stc_mfs_uart_fbyte2_field_t FBYTE2_f; + }; +} FM_MFS_UART_TypeDef, FM4_MFS_UART_TypeDef; + +/******************************************************************************* +* MFT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[258]; + union { + __IO uint16_t OCCP0; + struct { + __IO uint8_t OCCP0L; + __IO uint8_t OCCP0H; + }; + __IO uint16_t OCU_OCCP0; + struct { + __IO uint8_t OCU_OCCP0L; + __IO uint8_t OCU_OCCP0H; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t OCCP1; + struct { + __IO uint8_t OCCP1L; + __IO uint8_t OCCP1H; + }; + __IO uint16_t OCU_OCCP1; + struct { + __IO uint8_t OCU_OCCP1L; + __IO uint8_t OCU_OCCP1H; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t OCCP2; + struct { + __IO uint8_t OCCP2L; + __IO uint8_t OCCP2H; + }; + __IO uint16_t OCU_OCCP2; + struct { + __IO uint8_t OCU_OCCP2L; + __IO uint8_t OCU_OCCP2H; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint16_t OCCP3; + struct { + __IO uint8_t OCCP3L; + __IO uint8_t OCCP3H; + }; + __IO uint16_t OCU_OCCP3; + struct { + __IO uint8_t OCU_OCCP3L; + __IO uint8_t OCU_OCCP3H; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint16_t OCCP4; + struct { + __IO uint8_t OCCP4L; + __IO uint8_t OCCP4H; + }; + __IO uint16_t OCU_OCCP4; + struct { + __IO uint8_t OCU_OCCP4L; + __IO uint8_t OCU_OCCP4H; + }; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t OCCP5; + struct { + __IO uint8_t OCCP5L; + __IO uint8_t OCCP5H; + }; + __IO uint16_t OCU_OCCP5; + struct { + __IO uint8_t OCU_OCCP5L; + __IO uint8_t OCU_OCCP5H; + }; + }; + union { + __IO uint8_t OCSA10; + stc_mft_ocsa10_field_t OCSA10_f; + __IO uint8_t OCU_OCSA10; + stc_mft_ocu_ocsa10_field_t OCU_OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocsb10_field_t OCSB10_f; + __IO uint8_t OCU_OCSB10; + stc_mft_ocu_ocsb10_field_t OCU_OCSB10_f; + }; + union { + __IO uint16_t OCSD10; + stc_mft_ocsd10_field_t OCSD10_f; + struct { + __IO uint8_t OCSD10L; + __IO uint8_t OCSD10H; + }; + __IO uint16_t OCU_OCSD10; + stc_mft_ocu_ocsd10_field_t OCU_OCSD10_f; + struct { + __IO uint8_t OCU_OCSD10L; + __IO uint8_t OCU_OCSD10H; + }; + }; + union { + __IO uint8_t OCSA32; + stc_mft_ocsa32_field_t OCSA32_f; + __IO uint8_t OCU_OCSA32; + stc_mft_ocu_ocsa32_field_t OCU_OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocsb32_field_t OCSB32_f; + __IO uint8_t OCU_OCSB32; + stc_mft_ocu_ocsb32_field_t OCU_OCSB32_f; + }; + union { + __IO uint16_t OCSD32; + stc_mft_ocsd32_field_t OCSD32_f; + struct { + __IO uint8_t OCSD32L; + __IO uint8_t OCSD32H; + }; + __IO uint16_t OCU_OCSD32; + stc_mft_ocu_ocsd32_field_t OCU_OCSD32_f; + struct { + __IO uint8_t OCU_OCSD32L; + __IO uint8_t OCU_OCSD32H; + }; + }; + union { + __IO uint8_t OCSA54; + stc_mft_ocsa54_field_t OCSA54_f; + __IO uint8_t OCU_OCSA54; + stc_mft_ocu_ocsa54_field_t OCU_OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocsb54_field_t OCSB54_f; + __IO uint8_t OCU_OCSB54; + stc_mft_ocu_ocsb54_field_t OCU_OCSB54_f; + }; + union { + __IO uint16_t OCSD54; + stc_mft_ocsd54_field_t OCSD54_f; + struct { + __IO uint8_t OCSD54L; + __IO uint8_t OCSD54H; + }; + __IO uint16_t OCU_OCSD54; + stc_mft_ocu_ocsd54_field_t OCU_OCSD54_f; + struct { + __IO uint8_t OCU_OCSD54L; + __IO uint8_t OCU_OCSD54H; + }; + }; + __IO uint8_t RESERVED6[1]; + union { + __IO uint8_t OCSC; + stc_mft_ocsc_field_t OCSC_f; + __IO uint8_t OCU_OCSC; + stc_mft_ocu_ocsc_field_t OCU_OCSC_f; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint16_t OCSE0; + stc_mft_ocse0_field_t OCSE0_f; + struct { + __IO uint8_t OCSE0L; + __IO uint8_t OCSE0H; + }; + __IO uint16_t OCU_OCSE0; + stc_mft_ocu_ocse0_field_t OCU_OCSE0_f; + struct { + __IO uint8_t OCU_OCSE0L; + __IO uint8_t OCU_OCSE0H; + }; + }; + __IO uint8_t RESERVED8[2]; + union { + __IO uint32_t OCSE1; + stc_mft_ocse1_field_t OCSE1_f; + struct { + union { + __IO uint16_t OCSE1L; + struct { + __IO uint8_t OCSE1LL; + __IO uint8_t OCSE1LH; + }; + }; + union { + __IO uint16_t OCSE1H; + struct { + __IO uint8_t OCSE1HL; + __IO uint8_t OCSE1HH; + }; + }; + }; + __IO uint32_t OCU_OCSE1; + stc_mft_ocu_ocse1_field_t OCU_OCSE1_f; + struct { + union { + __IO uint16_t OCU_OCSE1L; + struct { + __IO uint8_t OCU_OCSE1LL; + __IO uint8_t OCU_OCSE1LH; + }; + }; + union { + __IO uint16_t OCU_OCSE1H; + struct { + __IO uint8_t OCU_OCSE1HL; + __IO uint8_t OCU_OCSE1HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE2; + stc_mft_ocse2_field_t OCSE2_f; + struct { + __IO uint8_t OCSE2L; + __IO uint8_t OCSE2H; + }; + __IO uint16_t OCU_OCSE2; + stc_mft_ocu_ocse2_field_t OCU_OCSE2_f; + struct { + __IO uint8_t OCU_OCSE2L; + __IO uint8_t OCU_OCSE2H; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint32_t OCSE3; + stc_mft_ocse3_field_t OCSE3_f; + struct { + union { + __IO uint16_t OCSE3L; + struct { + __IO uint8_t OCSE3LL; + __IO uint8_t OCSE3LH; + }; + }; + union { + __IO uint16_t OCSE3H; + struct { + __IO uint8_t OCSE3HL; + __IO uint8_t OCSE3HH; + }; + }; + }; + __IO uint32_t OCU_OCSE3; + stc_mft_ocu_ocse3_field_t OCU_OCSE3_f; + struct { + union { + __IO uint16_t OCU_OCSE3L; + struct { + __IO uint8_t OCU_OCSE3LL; + __IO uint8_t OCU_OCSE3LH; + }; + }; + union { + __IO uint16_t OCU_OCSE3H; + struct { + __IO uint8_t OCU_OCSE3HL; + __IO uint8_t OCU_OCSE3HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE4; + stc_mft_ocse4_field_t OCSE4_f; + struct { + __IO uint8_t OCSE4L; + __IO uint8_t OCSE4H; + }; + __IO uint16_t OCU_OCSE4; + stc_mft_ocu_ocse4_field_t OCU_OCSE4_f; + struct { + __IO uint8_t OCU_OCSE4L; + __IO uint8_t OCU_OCSE4H; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint32_t OCSE5; + stc_mft_ocse5_field_t OCSE5_f; + struct { + union { + __IO uint16_t OCSE5L; + struct { + __IO uint8_t OCSE5LL; + __IO uint8_t OCSE5LH; + }; + }; + union { + __IO uint16_t OCSE5H; + struct { + __IO uint8_t OCSE5HL; + __IO uint8_t OCSE5HH; + }; + }; + }; + __IO uint32_t OCU_OCSE5; + stc_mft_ocu_ocse5_field_t OCU_OCSE5_f; + struct { + union { + __IO uint16_t OCU_OCSE5L; + struct { + __IO uint8_t OCU_OCSE5LL; + __IO uint8_t OCU_OCSE5LH; + }; + }; + union { + __IO uint16_t OCU_OCSE5H; + struct { + __IO uint8_t OCU_OCSE5HL; + __IO uint8_t OCU_OCSE5HH; + }; + }; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t TCCP0; + stc_mft_tccp0_field_t TCCP0_f; + struct { + __IO uint8_t TCCP0L; + __IO uint8_t TCCP0H; + }; + __IO uint16_t FRT_TCCP0; + stc_mft_frt_tccp0_field_t FRT_TCCP0_f; + struct { + __IO uint8_t FRT_TCCP0L; + __IO uint8_t FRT_TCCP0H; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint16_t TCDT0; + struct { + __IO uint8_t TCDT0L; + __IO uint8_t TCDT0H; + }; + __IO uint16_t FRT_TCDT0; + struct { + __IO uint8_t FRT_TCDT0L; + __IO uint8_t FRT_TCDT0H; + }; + }; + union { + __IO uint16_t TCSA0; + stc_mft_tcsa0_field_t TCSA0_f; + struct { + __IO uint8_t TCSA0L; + __IO uint8_t TCSA0H; + }; + __IO uint16_t FRT_TCSA0; + stc_mft_frt_tcsa0_field_t FRT_TCSA0_f; + struct { + __IO uint8_t FRT_TCSA0L; + __IO uint8_t FRT_TCSA0H; + }; + }; + union { + __IO uint16_t TCSC0; + stc_mft_tcsc0_field_t TCSC0_f; + struct { + __IO uint8_t TCSC0L; + __IO uint8_t TCSC0H; + }; + __IO uint16_t FRT_TCSC0; + stc_mft_frt_tcsc0_field_t FRT_TCSC0_f; + struct { + __IO uint8_t FRT_TCSC0L; + __IO uint8_t FRT_TCSC0H; + }; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint16_t TCCP1; + stc_mft_tccp1_field_t TCCP1_f; + struct { + __IO uint8_t TCCP1L; + __IO uint8_t TCCP1H; + }; + __IO uint16_t FRT_TCCP1; + stc_mft_frt_tccp1_field_t FRT_TCCP1_f; + struct { + __IO uint8_t FRT_TCCP1L; + __IO uint8_t FRT_TCCP1H; + }; + }; + __IO uint8_t RESERVED14[2]; + union { + __IO uint16_t TCDT1; + struct { + __IO uint8_t TCDT1L; + __IO uint8_t TCDT1H; + }; + __IO uint16_t FRT_TCDT1; + struct { + __IO uint8_t FRT_TCDT1L; + __IO uint8_t FRT_TCDT1H; + }; + }; + union { + __IO uint16_t TCSA1; + stc_mft_tcsa1_field_t TCSA1_f; + struct { + __IO uint8_t TCSA1L; + __IO uint8_t TCSA1H; + }; + __IO uint16_t FRT_TCSA1; + stc_mft_frt_tcsa1_field_t FRT_TCSA1_f; + struct { + __IO uint8_t FRT_TCSA1L; + __IO uint8_t FRT_TCSA1H; + }; + }; + union { + __IO uint16_t TCSC1; + stc_mft_tcsc1_field_t TCSC1_f; + struct { + __IO uint8_t TCSC1L; + __IO uint8_t TCSC1H; + }; + __IO uint16_t FRT_TCSC1; + stc_mft_frt_tcsc1_field_t FRT_TCSC1_f; + struct { + __IO uint8_t FRT_TCSC1L; + __IO uint8_t FRT_TCSC1H; + }; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint16_t TCCP2; + stc_mft_tccp2_field_t TCCP2_f; + struct { + __IO uint8_t TCCP2L; + __IO uint8_t TCCP2H; + }; + __IO uint16_t FRT_TCCP2; + stc_mft_frt_tccp2_field_t FRT_TCCP2_f; + struct { + __IO uint8_t FRT_TCCP2L; + __IO uint8_t FRT_TCCP2H; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint16_t TCDT2; + struct { + __IO uint8_t TCDT2L; + __IO uint8_t TCDT2H; + }; + __IO uint16_t FRT_TCDT2; + struct { + __IO uint8_t FRT_TCDT2L; + __IO uint8_t FRT_TCDT2H; + }; + }; + union { + __IO uint16_t TCSA2; + stc_mft_tcsa2_field_t TCSA2_f; + struct { + __IO uint8_t TCSA2L; + __IO uint8_t TCSA2H; + }; + __IO uint16_t FRT_TCSA2; + stc_mft_frt_tcsa2_field_t FRT_TCSA2_f; + struct { + __IO uint8_t FRT_TCSA2L; + __IO uint8_t FRT_TCSA2H; + }; + }; + union { + __IO uint16_t TCSC2; + stc_mft_tcsc2_field_t TCSC2_f; + struct { + __IO uint8_t TCSC2L; + __IO uint8_t TCSC2H; + }; + __IO uint16_t FRT_TCSC2; + stc_mft_frt_tcsc2_field_t FRT_TCSC2_f; + struct { + __IO uint8_t FRT_TCSC2L; + __IO uint8_t FRT_TCSC2H; + }; + }; + union { + __IO uint32_t TCAL; + stc_mft_tcal_field_t TCAL_f; + struct { + union { + __IO uint16_t TCALL; + struct { + __IO uint8_t TCALLL; + __IO uint8_t TCALLH; + }; + }; + union { + __IO uint16_t TCALH; + struct { + __IO uint8_t TCALHL; + __IO uint8_t TCALHH; + }; + }; + }; + __IO uint32_t FRT_TCAL; + stc_mft_frt_tcal_field_t FRT_TCAL_f; + struct { + union { + __IO uint16_t FRT_TCALL; + struct { + __IO uint8_t FRT_TCALLL; + __IO uint8_t FRT_TCALLH; + }; + }; + union { + __IO uint16_t FRT_TCALH; + struct { + __IO uint8_t FRT_TCALHL; + __IO uint8_t FRT_TCALHH; + }; + }; + }; + }; + union { + __IO uint8_t OCFS10; + stc_mft_ocfs10_field_t OCFS10_f; + __IO uint8_t OCU_OCFS10; + stc_mft_ocu_ocfs10_field_t OCU_OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocfs32_field_t OCFS32_f; + __IO uint8_t OCU_OCFS32; + stc_mft_ocu_ocfs32_field_t OCU_OCFS32_f; + }; + union { + __IO uint8_t OCFS54; + stc_mft_ocfs54_field_t OCFS54_f; + __IO uint8_t OCU_OCFS54; + stc_mft_ocu_ocfs54_field_t OCU_OCFS54_f; + }; + __IO uint8_t RESERVED17[1]; + union { + __IO uint8_t ICFS10; + stc_mft_icfs10_field_t ICFS10_f; + __IO uint8_t ICU_ICFS10; + stc_mft_icu_icfs10_field_t ICU_ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icfs32_field_t ICFS32_f; + __IO uint8_t ICU_ICFS32; + stc_mft_icu_icfs32_field_t ICU_ICFS32_f; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint8_t ACFS10; + stc_mft_acfs10_field_t ACFS10_f; + __IO uint8_t ADCMP_ACFS10; + stc_mft_adcmp_acfs10_field_t ADCMP_ACFS10_f; + }; + union { + __IO uint8_t ACFS32; + stc_mft_acfs32_field_t ACFS32_f; + __IO uint8_t ADCMP_ACFS32; + stc_mft_adcmp_acfs32_field_t ADCMP_ACFS32_f; + }; + union { + __IO uint8_t ACFS54; + stc_mft_acfs54_field_t ACFS54_f; + __IO uint8_t ADCMP_ACFS54; + stc_mft_adcmp_acfs54_field_t ADCMP_ACFS54_f; + }; + __IO uint8_t RESERVED19[3]; + union { + __IO uint16_t ICCP0; + struct { + __IO uint8_t ICCP0L; + __IO uint8_t ICCP0H; + }; + __IO uint16_t ICU_ICCP0; + struct { + __IO uint8_t ICU_ICCP0L; + __IO uint8_t ICU_ICCP0H; + }; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint16_t ICCP1; + struct { + __IO uint8_t ICCP1L; + __IO uint8_t ICCP1H; + }; + __IO uint16_t ICU_ICCP1; + struct { + __IO uint8_t ICU_ICCP1L; + __IO uint8_t ICU_ICCP1H; + }; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint16_t ICCP2; + struct { + __IO uint8_t ICCP2L; + __IO uint8_t ICCP2H; + }; + __IO uint16_t ICU_ICCP2; + struct { + __IO uint8_t ICU_ICCP2L; + __IO uint8_t ICU_ICCP2H; + }; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint16_t ICCP3; + struct { + __IO uint8_t ICCP3L; + __IO uint8_t ICCP3H; + }; + __IO uint16_t ICU_ICCP3; + struct { + __IO uint8_t ICU_ICCP3L; + __IO uint8_t ICU_ICCP3H; + }; + }; + union { + __IO uint8_t ICSA10; + stc_mft_icsa10_field_t ICSA10_f; + __IO uint8_t ICU_ICSA10; + stc_mft_icu_icsa10_field_t ICU_ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icsb10_field_t ICSB10_f; + __IO uint8_t ICU_ICSB10; + stc_mft_icu_icsb10_field_t ICU_ICSB10_f; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icsa32_field_t ICSA32_f; + __IO uint8_t ICU_ICSA32; + stc_mft_icu_icsa32_field_t ICU_ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icsb32_field_t ICSB32_f; + __IO uint8_t ICU_ICSB32; + stc_mft_icu_icsb32_field_t ICU_ICSB32_f; + }; + __IO uint8_t RESERVED24[4]; + union { + __IO uint16_t WFTF10; + struct { + __IO uint8_t WFTF10L; + __IO uint8_t WFTF10H; + }; + __IO uint16_t WFG_WFTF10; + struct { + __IO uint8_t WFG_WFTF10L; + __IO uint8_t WFG_WFTF10H; + }; + }; + union { + __IO uint16_t WFTA10; + struct { + __IO uint8_t WFTA10L; + __IO uint8_t WFTA10H; + }; + __IO uint16_t WFG_WFTA10; + struct { + __IO uint8_t WFG_WFTA10L; + __IO uint8_t WFG_WFTA10H; + }; + }; + union { + __IO uint16_t WFTB10; + struct { + __IO uint8_t WFTB10L; + __IO uint8_t WFTB10H; + }; + __IO uint16_t WFG_WFTB10; + struct { + __IO uint8_t WFG_WFTB10L; + __IO uint8_t WFG_WFTB10H; + }; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint16_t WFTF32; + struct { + __IO uint8_t WFTF32L; + __IO uint8_t WFTF32H; + }; + __IO uint16_t WFG_WFTF32; + struct { + __IO uint8_t WFG_WFTF32L; + __IO uint8_t WFG_WFTF32H; + }; + }; + union { + __IO uint16_t WFTA32; + struct { + __IO uint8_t WFTA32L; + __IO uint8_t WFTA32H; + }; + __IO uint16_t WFG_WFTA32; + struct { + __IO uint8_t WFG_WFTA32L; + __IO uint8_t WFG_WFTA32H; + }; + }; + union { + __IO uint16_t WFTB32; + struct { + __IO uint8_t WFTB32L; + __IO uint8_t WFTB32H; + }; + __IO uint16_t WFG_WFTB32; + struct { + __IO uint8_t WFG_WFTB32L; + __IO uint8_t WFG_WFTB32H; + }; + }; + __IO uint8_t RESERVED26[2]; + union { + __IO uint16_t WFTF54; + struct { + __IO uint8_t WFTF54L; + __IO uint8_t WFTF54H; + }; + __IO uint16_t WFG_WFTF54; + struct { + __IO uint8_t WFG_WFTF54L; + __IO uint8_t WFG_WFTF54H; + }; + }; + union { + __IO uint16_t WFTA54; + struct { + __IO uint8_t WFTA54L; + __IO uint8_t WFTA54H; + }; + __IO uint16_t WFG_WFTA54; + struct { + __IO uint8_t WFG_WFTA54L; + __IO uint8_t WFG_WFTA54H; + }; + }; + union { + __IO uint16_t WFTB54; + struct { + __IO uint8_t WFTB54L; + __IO uint8_t WFTB54H; + }; + __IO uint16_t WFG_WFTB54; + struct { + __IO uint8_t WFG_WFTB54L; + __IO uint8_t WFG_WFTB54H; + }; + }; + union { + __IO uint16_t WFSA10; + stc_mft_wfsa10_field_t WFSA10_f; + struct { + __IO uint8_t WFSA10L; + __IO uint8_t WFSA10H; + }; + __IO uint16_t WFG_WFSA10; + stc_mft_wfg_wfsa10_field_t WFG_WFSA10_f; + struct { + __IO uint8_t WFG_WFSA10L; + __IO uint8_t WFG_WFSA10H; + }; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfsa32_field_t WFSA32_f; + struct { + __IO uint8_t WFSA32L; + __IO uint8_t WFSA32H; + }; + __IO uint16_t WFG_WFSA32; + stc_mft_wfg_wfsa32_field_t WFG_WFSA32_f; + struct { + __IO uint8_t WFG_WFSA32L; + __IO uint8_t WFG_WFSA32H; + }; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfsa54_field_t WFSA54_f; + struct { + __IO uint8_t WFSA54L; + __IO uint8_t WFSA54H; + }; + __IO uint16_t WFG_WFSA54; + stc_mft_wfg_wfsa54_field_t WFG_WFSA54_f; + struct { + __IO uint8_t WFG_WFSA54L; + __IO uint8_t WFG_WFSA54H; + }; + }; + __IO uint8_t RESERVED29[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfir_field_t WFIR_f; + struct { + __IO uint8_t WFIRL; + __IO uint8_t WFIRH; + }; + __IO uint16_t WFG_WFIR; + stc_mft_wfg_wfir_field_t WFG_WFIR_f; + struct { + __IO uint8_t WFG_WFIRL; + __IO uint8_t WFG_WFIRH; + }; + }; + __IO uint8_t RESERVED30[2]; + union { + __IO uint16_t NZCL; + stc_mft_nzcl_field_t NZCL_f; + struct { + __IO uint8_t NZCLL; + __IO uint8_t NZCLH; + }; + __IO uint16_t WFG_NZCL; + stc_mft_wfg_nzcl_field_t WFG_NZCL_f; + struct { + __IO uint8_t WFG_NZCLL; + __IO uint8_t WFG_NZCLH; + }; + }; + __IO uint8_t RESERVED31[4]; + union { + __IO uint16_t ACMP0; + stc_mft_acmp0_field_t ACMP0_f; + struct { + __IO uint8_t ACMP0L; + __IO uint8_t ACMP0H; + }; + __IO uint16_t ADCMP_ACMP0; + stc_mft_adcmp_acmp0_field_t ADCMP_ACMP0_f; + struct { + __IO uint8_t ADCMP_ACMP0L; + __IO uint8_t ADCMP_ACMP0H; + }; + }; + __IO uint8_t RESERVED32[2]; + union { + __IO uint16_t ACMP1; + stc_mft_acmp1_field_t ACMP1_f; + struct { + __IO uint8_t ACMP1L; + __IO uint8_t ACMP1H; + }; + __IO uint16_t ADCMP_ACMP1; + stc_mft_adcmp_acmp1_field_t ADCMP_ACMP1_f; + struct { + __IO uint8_t ADCMP_ACMP1L; + __IO uint8_t ADCMP_ACMP1H; + }; + }; + __IO uint8_t RESERVED33[2]; + union { + __IO uint16_t ACMP2; + stc_mft_acmp2_field_t ACMP2_f; + struct { + __IO uint8_t ACMP2L; + __IO uint8_t ACMP2H; + }; + __IO uint16_t ADCMP_ACMP2; + stc_mft_adcmp_acmp2_field_t ADCMP_ACMP2_f; + struct { + __IO uint8_t ADCMP_ACMP2L; + __IO uint8_t ADCMP_ACMP2H; + }; + }; + __IO uint8_t RESERVED34[2]; + union { + __IO uint16_t ACMP3; + stc_mft_acmp3_field_t ACMP3_f; + struct { + __IO uint8_t ACMP3L; + __IO uint8_t ACMP3H; + }; + __IO uint16_t ADCMP_ACMP3; + stc_mft_adcmp_acmp3_field_t ADCMP_ACMP3_f; + struct { + __IO uint8_t ADCMP_ACMP3L; + __IO uint8_t ADCMP_ACMP3H; + }; + }; + __IO uint8_t RESERVED35[2]; + union { + __IO uint16_t ACMP4; + stc_mft_acmp4_field_t ACMP4_f; + struct { + __IO uint8_t ACMP4L; + __IO uint8_t ACMP4H; + }; + __IO uint16_t ADCMP_ACMP4; + stc_mft_adcmp_acmp4_field_t ADCMP_ACMP4_f; + struct { + __IO uint8_t ADCMP_ACMP4L; + __IO uint8_t ADCMP_ACMP4H; + }; + }; + __IO uint8_t RESERVED36[2]; + union { + __IO uint16_t ACMP5; + stc_mft_acmp5_field_t ACMP5_f; + struct { + __IO uint8_t ACMP5L; + __IO uint8_t ACMP5H; + }; + __IO uint16_t ADCMP_ACMP5; + stc_mft_adcmp_acmp5_field_t ADCMP_ACMP5_f; + struct { + __IO uint8_t ADCMP_ACMP5L; + __IO uint8_t ADCMP_ACMP5H; + }; + }; + union { + __IO uint16_t ACSA; + stc_mft_acsa_field_t ACSA_f; + struct { + __IO uint8_t ACSAL; + __IO uint8_t ACSAH; + }; + __IO uint16_t ADCMP_ACSA; + stc_mft_adcmp_acsa_field_t ADCMP_ACSA_f; + struct { + __IO uint8_t ADCMP_ACSAL; + __IO uint8_t ADCMP_ACSAH; + }; + }; + __IO uint8_t RESERVED37[2]; + union { + __IO uint8_t ACSC0; + stc_mft_acsc0_field_t ACSC0_f; + __IO uint8_t ADCMP_ACSC0; + stc_mft_adcmp_acsc0_field_t ADCMP_ACSC0_f; + }; + union { + __IO uint8_t ACSD0; + stc_mft_acsd0_field_t ACSD0_f; + __IO uint8_t ADCMP_ACSD0; + stc_mft_adcmp_acsd0_field_t ADCMP_ACSD0_f; + }; + union { + __IO uint8_t ACMC0; + stc_mft_acmc0_field_t ACMC0_f; + __IO uint8_t ADCMP_ACMC0; + stc_mft_adcmp_acmc0_field_t ADCMP_ACMC0_f; + }; + __IO uint8_t RESERVED38[1]; + union { + __IO uint8_t ACSC1; + stc_mft_acsc1_field_t ACSC1_f; + __IO uint8_t ADCMP_ACSC1; + stc_mft_adcmp_acsc1_field_t ADCMP_ACSC1_f; + }; + union { + __IO uint8_t ACSD1; + stc_mft_acsd1_field_t ACSD1_f; + __IO uint8_t ADCMP_ACSD1; + stc_mft_adcmp_acsd1_field_t ADCMP_ACSD1_f; + }; + union { + __IO uint8_t ACMC1; + stc_mft_acmc1_field_t ACMC1_f; + __IO uint8_t ADCMP_ACMC1; + stc_mft_adcmp_acmc1_field_t ADCMP_ACMC1_f; + }; + __IO uint8_t RESERVED39[1]; + union { + __IO uint8_t ACSC2; + stc_mft_acsc2_field_t ACSC2_f; + __IO uint8_t ADCMP_ACSC2; + stc_mft_adcmp_acsc2_field_t ADCMP_ACSC2_f; + }; + union { + __IO uint8_t ACSD2; + stc_mft_acsd2_field_t ACSD2_f; + __IO uint8_t ADCMP_ACSD2; + stc_mft_adcmp_acsd2_field_t ADCMP_ACSD2_f; + }; + union { + __IO uint8_t ACMC2; + stc_mft_acmc2_field_t ACMC2_f; + __IO uint8_t ADCMP_ACMC2; + stc_mft_adcmp_acmc2_field_t ADCMP_ACMC2_f; + }; + __IO uint8_t RESERVED40[1]; + union { + __IO uint8_t ACSC3; + stc_mft_acsc3_field_t ACSC3_f; + __IO uint8_t ADCMP_ACSC3; + stc_mft_adcmp_acsc3_field_t ADCMP_ACSC3_f; + }; + union { + __IO uint8_t ACSD3; + stc_mft_acsd3_field_t ACSD3_f; + __IO uint8_t ADCMP_ACSD3; + stc_mft_adcmp_acsd3_field_t ADCMP_ACSD3_f; + }; + union { + __IO uint8_t ACMC3; + stc_mft_acmc3_field_t ACMC3_f; + __IO uint8_t ADCMP_ACMC3; + stc_mft_adcmp_acmc3_field_t ADCMP_ACMC3_f; + }; + __IO uint8_t RESERVED41[1]; + union { + __IO uint8_t ACSC4; + stc_mft_acsc4_field_t ACSC4_f; + __IO uint8_t ADCMP_ACSC4; + stc_mft_adcmp_acsc4_field_t ADCMP_ACSC4_f; + }; + union { + __IO uint8_t ACSD4; + stc_mft_acsd4_field_t ACSD4_f; + __IO uint8_t ADCMP_ACSD4; + stc_mft_adcmp_acsd4_field_t ADCMP_ACSD4_f; + }; + union { + __IO uint8_t ACMC4; + stc_mft_acmc4_field_t ACMC4_f; + __IO uint8_t ADCMP_ACMC4; + stc_mft_adcmp_acmc4_field_t ADCMP_ACMC4_f; + }; + __IO uint8_t RESERVED42[1]; + union { + __IO uint8_t ACSC5; + stc_mft_acsc5_field_t ACSC5_f; + __IO uint8_t ADCMP_ACSC5; + stc_mft_adcmp_acsc5_field_t ADCMP_ACSC5_f; + }; + union { + __IO uint8_t ACSD5; + stc_mft_acsd5_field_t ACSD5_f; + __IO uint8_t ADCMP_ACSD5; + stc_mft_adcmp_acsd5_field_t ADCMP_ACSD5_f; + }; + union { + __IO uint8_t ACMC5; + stc_mft_acmc5_field_t ACMC5_f; + __IO uint8_t ADCMP_ACMC5; + stc_mft_adcmp_acmc5_field_t ADCMP_ACMC5_f; + }; + __IO uint8_t RESERVED43[1]; + union { + __IO uint8_t TCSD; + stc_mft_tcsd_field_t TCSD_f; + __IO uint8_t FRT_TCSD; + stc_mft_frt_tcsd_field_t FRT_TCSD_f; + }; +} FM_MFT_TypeDef, FM4_MFT_TypeDef; + +/******************************************************************************* +* MFT_ADCMP_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED44[368]; + union { + __IO uint8_t ACFS10; + stc_mft_adcmp_acfs10_field_t ACFS10_f; + }; + union { + __IO uint8_t ACFS32; + stc_mft_adcmp_acfs32_field_t ACFS32_f; + }; + union { + __IO uint8_t ACFS54; + stc_mft_adcmp_acfs54_field_t ACFS54_f; + }; + __IO uint8_t RESERVED45[71]; + union { + __IO uint16_t ACMP0; + stc_mft_adcmp_acmp0_field_t ACMP0_f; + struct { + __IO uint8_t ACMP0L; + __IO uint8_t ACMP0H; + }; + }; + __IO uint8_t RESERVED46[2]; + union { + __IO uint16_t ACMP1; + stc_mft_adcmp_acmp1_field_t ACMP1_f; + struct { + __IO uint8_t ACMP1L; + __IO uint8_t ACMP1H; + }; + }; + __IO uint8_t RESERVED47[2]; + union { + __IO uint16_t ACMP2; + stc_mft_adcmp_acmp2_field_t ACMP2_f; + struct { + __IO uint8_t ACMP2L; + __IO uint8_t ACMP2H; + }; + }; + __IO uint8_t RESERVED48[2]; + union { + __IO uint16_t ACMP3; + stc_mft_adcmp_acmp3_field_t ACMP3_f; + struct { + __IO uint8_t ACMP3L; + __IO uint8_t ACMP3H; + }; + }; + __IO uint8_t RESERVED49[2]; + union { + __IO uint16_t ACMP4; + stc_mft_adcmp_acmp4_field_t ACMP4_f; + struct { + __IO uint8_t ACMP4L; + __IO uint8_t ACMP4H; + }; + }; + __IO uint8_t RESERVED50[2]; + union { + __IO uint16_t ACMP5; + stc_mft_adcmp_acmp5_field_t ACMP5_f; + struct { + __IO uint8_t ACMP5L; + __IO uint8_t ACMP5H; + }; + }; + union { + __IO uint16_t ACSA; + stc_mft_adcmp_acsa_field_t ACSA_f; + struct { + __IO uint8_t ACSAL; + __IO uint8_t ACSAH; + }; + }; + __IO uint8_t RESERVED51[2]; + union { + __IO uint8_t ACSC0; + stc_mft_adcmp_acsc0_field_t ACSC0_f; + }; + union { + __IO uint8_t ACSD0; + stc_mft_adcmp_acsd0_field_t ACSD0_f; + }; + union { + __IO uint8_t ACMC0; + stc_mft_adcmp_acmc0_field_t ACMC0_f; + }; + __IO uint8_t RESERVED52[1]; + union { + __IO uint8_t ACSC1; + stc_mft_adcmp_acsc1_field_t ACSC1_f; + }; + union { + __IO uint8_t ACSD1; + stc_mft_adcmp_acsd1_field_t ACSD1_f; + }; + union { + __IO uint8_t ACMC1; + stc_mft_adcmp_acmc1_field_t ACMC1_f; + }; + __IO uint8_t RESERVED53[1]; + union { + __IO uint8_t ACSC2; + stc_mft_adcmp_acsc2_field_t ACSC2_f; + }; + union { + __IO uint8_t ACSD2; + stc_mft_adcmp_acsd2_field_t ACSD2_f; + }; + union { + __IO uint8_t ACMC2; + stc_mft_adcmp_acmc2_field_t ACMC2_f; + }; + __IO uint8_t RESERVED54[1]; + union { + __IO uint8_t ACSC3; + stc_mft_adcmp_acsc3_field_t ACSC3_f; + }; + union { + __IO uint8_t ACSD3; + stc_mft_adcmp_acsd3_field_t ACSD3_f; + }; + union { + __IO uint8_t ACMC3; + stc_mft_adcmp_acmc3_field_t ACMC3_f; + }; + __IO uint8_t RESERVED55[1]; + union { + __IO uint8_t ACSC4; + stc_mft_adcmp_acsc4_field_t ACSC4_f; + }; + union { + __IO uint8_t ACSD4; + stc_mft_adcmp_acsd4_field_t ACSD4_f; + }; + union { + __IO uint8_t ACMC4; + stc_mft_adcmp_acmc4_field_t ACMC4_f; + }; + __IO uint8_t RESERVED56[1]; + union { + __IO uint8_t ACSC5; + stc_mft_adcmp_acsc5_field_t ACSC5_f; + }; + union { + __IO uint8_t ACSD5; + stc_mft_adcmp_acsd5_field_t ACSD5_f; + }; + union { + __IO uint8_t ACMC5; + stc_mft_adcmp_acmc5_field_t ACMC5_f; + }; +} FM_MFT_ADCMP_TypeDef, FM4_MFT_ADCMP_TypeDef; + +/******************************************************************************* +* MFT_FRT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED57[322]; + union { + __IO uint16_t TCCP0; + stc_mft_frt_tccp0_field_t TCCP0_f; + struct { + __IO uint8_t TCCP0L; + __IO uint8_t TCCP0H; + }; + }; + __IO uint8_t RESERVED58[2]; + union { + __IO uint16_t TCDT0; + struct { + __IO uint8_t TCDT0L; + __IO uint8_t TCDT0H; + }; + }; + union { + __IO uint16_t TCSA0; + stc_mft_frt_tcsa0_field_t TCSA0_f; + struct { + __IO uint8_t TCSA0L; + __IO uint8_t TCSA0H; + }; + }; + union { + __IO uint16_t TCSC0; + stc_mft_frt_tcsc0_field_t TCSC0_f; + struct { + __IO uint8_t TCSC0L; + __IO uint8_t TCSC0H; + }; + }; + __IO uint8_t RESERVED59[2]; + union { + __IO uint16_t TCCP1; + stc_mft_frt_tccp1_field_t TCCP1_f; + struct { + __IO uint8_t TCCP1L; + __IO uint8_t TCCP1H; + }; + }; + __IO uint8_t RESERVED60[2]; + union { + __IO uint16_t TCDT1; + struct { + __IO uint8_t TCDT1L; + __IO uint8_t TCDT1H; + }; + }; + union { + __IO uint16_t TCSA1; + stc_mft_frt_tcsa1_field_t TCSA1_f; + struct { + __IO uint8_t TCSA1L; + __IO uint8_t TCSA1H; + }; + }; + union { + __IO uint16_t TCSC1; + stc_mft_frt_tcsc1_field_t TCSC1_f; + struct { + __IO uint8_t TCSC1L; + __IO uint8_t TCSC1H; + }; + }; + __IO uint8_t RESERVED61[2]; + union { + __IO uint16_t TCCP2; + stc_mft_frt_tccp2_field_t TCCP2_f; + struct { + __IO uint8_t TCCP2L; + __IO uint8_t TCCP2H; + }; + }; + __IO uint8_t RESERVED62[2]; + union { + __IO uint16_t TCDT2; + struct { + __IO uint8_t TCDT2L; + __IO uint8_t TCDT2H; + }; + }; + union { + __IO uint16_t TCSA2; + stc_mft_frt_tcsa2_field_t TCSA2_f; + struct { + __IO uint8_t TCSA2L; + __IO uint8_t TCSA2H; + }; + }; + union { + __IO uint16_t TCSC2; + stc_mft_frt_tcsc2_field_t TCSC2_f; + struct { + __IO uint8_t TCSC2L; + __IO uint8_t TCSC2H; + }; + }; + union { + __IO uint32_t TCAL; + stc_mft_frt_tcal_field_t TCAL_f; + struct { + union { + __IO uint16_t TCALL; + struct { + __IO uint8_t TCALLL; + __IO uint8_t TCALLH; + }; + }; + union { + __IO uint16_t TCALH; + struct { + __IO uint8_t TCALHL; + __IO uint8_t TCALHH; + }; + }; + }; + }; + __IO uint8_t RESERVED63[132]; + union { + __IO uint8_t TCSD; + stc_mft_frt_tcsd_field_t TCSD_f; + }; +} FM_MFT_FRT_TypeDef, FM4_MFT_FRT_TypeDef; + +/******************************************************************************* +* MFT_ICU_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED64[364]; + union { + __IO uint8_t ICFS10; + stc_mft_icu_icfs10_field_t ICFS10_f; + }; + union { + __IO uint8_t ICFS32; + stc_mft_icu_icfs32_field_t ICFS32_f; + }; + __IO uint8_t RESERVED65[8]; + union { + __IO uint16_t ICCP0; + struct { + __IO uint8_t ICCP0L; + __IO uint8_t ICCP0H; + }; + }; + __IO uint8_t RESERVED66[2]; + union { + __IO uint16_t ICCP1; + struct { + __IO uint8_t ICCP1L; + __IO uint8_t ICCP1H; + }; + }; + __IO uint8_t RESERVED67[2]; + union { + __IO uint16_t ICCP2; + struct { + __IO uint8_t ICCP2L; + __IO uint8_t ICCP2H; + }; + }; + __IO uint8_t RESERVED68[2]; + union { + __IO uint16_t ICCP3; + struct { + __IO uint8_t ICCP3L; + __IO uint8_t ICCP3H; + }; + }; + union { + __IO uint8_t ICSA10; + stc_mft_icu_icsa10_field_t ICSA10_f; + }; + union { + __IO uint8_t ICSB10; + stc_mft_icu_icsb10_field_t ICSB10_f; + }; + __IO uint8_t RESERVED69[2]; + union { + __IO uint8_t ICSA32; + stc_mft_icu_icsa32_field_t ICSA32_f; + }; + union { + __IO uint8_t ICSB32; + stc_mft_icu_icsb32_field_t ICSB32_f; + }; +} FM_MFT_ICU_TypeDef, FM4_MFT_ICU_TypeDef; + +/******************************************************************************* +* MFT_OCU_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED70[258]; + union { + __IO uint16_t OCCP0; + struct { + __IO uint8_t OCCP0L; + __IO uint8_t OCCP0H; + }; + }; + __IO uint8_t RESERVED71[2]; + union { + __IO uint16_t OCCP1; + struct { + __IO uint8_t OCCP1L; + __IO uint8_t OCCP1H; + }; + }; + __IO uint8_t RESERVED72[2]; + union { + __IO uint16_t OCCP2; + struct { + __IO uint8_t OCCP2L; + __IO uint8_t OCCP2H; + }; + }; + __IO uint8_t RESERVED73[2]; + union { + __IO uint16_t OCCP3; + struct { + __IO uint8_t OCCP3L; + __IO uint8_t OCCP3H; + }; + }; + __IO uint8_t RESERVED74[2]; + union { + __IO uint16_t OCCP4; + struct { + __IO uint8_t OCCP4L; + __IO uint8_t OCCP4H; + }; + }; + __IO uint8_t RESERVED75[2]; + union { + __IO uint16_t OCCP5; + struct { + __IO uint8_t OCCP5L; + __IO uint8_t OCCP5H; + }; + }; + union { + __IO uint8_t OCSA10; + stc_mft_ocu_ocsa10_field_t OCSA10_f; + }; + union { + __IO uint8_t OCSB10; + stc_mft_ocu_ocsb10_field_t OCSB10_f; + }; + union { + __IO uint16_t OCSD10; + stc_mft_ocu_ocsd10_field_t OCSD10_f; + struct { + __IO uint8_t OCSD10L; + __IO uint8_t OCSD10H; + }; + }; + union { + __IO uint8_t OCSA32; + stc_mft_ocu_ocsa32_field_t OCSA32_f; + }; + union { + __IO uint8_t OCSB32; + stc_mft_ocu_ocsb32_field_t OCSB32_f; + }; + union { + __IO uint16_t OCSD32; + stc_mft_ocu_ocsd32_field_t OCSD32_f; + struct { + __IO uint8_t OCSD32L; + __IO uint8_t OCSD32H; + }; + }; + union { + __IO uint8_t OCSA54; + stc_mft_ocu_ocsa54_field_t OCSA54_f; + }; + union { + __IO uint8_t OCSB54; + stc_mft_ocu_ocsb54_field_t OCSB54_f; + }; + union { + __IO uint16_t OCSD54; + stc_mft_ocu_ocsd54_field_t OCSD54_f; + struct { + __IO uint8_t OCSD54L; + __IO uint8_t OCSD54H; + }; + }; + __IO uint8_t RESERVED76[1]; + union { + __IO uint8_t OCSC; + stc_mft_ocu_ocsc_field_t OCSC_f; + }; + __IO uint8_t RESERVED77[2]; + union { + __IO uint16_t OCSE0; + stc_mft_ocu_ocse0_field_t OCSE0_f; + struct { + __IO uint8_t OCSE0L; + __IO uint8_t OCSE0H; + }; + }; + __IO uint8_t RESERVED78[2]; + union { + __IO uint32_t OCSE1; + stc_mft_ocu_ocse1_field_t OCSE1_f; + struct { + union { + __IO uint16_t OCSE1L; + struct { + __IO uint8_t OCSE1LL; + __IO uint8_t OCSE1LH; + }; + }; + union { + __IO uint16_t OCSE1H; + struct { + __IO uint8_t OCSE1HL; + __IO uint8_t OCSE1HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE2; + stc_mft_ocu_ocse2_field_t OCSE2_f; + struct { + __IO uint8_t OCSE2L; + __IO uint8_t OCSE2H; + }; + }; + __IO uint8_t RESERVED79[2]; + union { + __IO uint32_t OCSE3; + stc_mft_ocu_ocse3_field_t OCSE3_f; + struct { + union { + __IO uint16_t OCSE3L; + struct { + __IO uint8_t OCSE3LL; + __IO uint8_t OCSE3LH; + }; + }; + union { + __IO uint16_t OCSE3H; + struct { + __IO uint8_t OCSE3HL; + __IO uint8_t OCSE3HH; + }; + }; + }; + }; + union { + __IO uint16_t OCSE4; + stc_mft_ocu_ocse4_field_t OCSE4_f; + struct { + __IO uint8_t OCSE4L; + __IO uint8_t OCSE4H; + }; + }; + __IO uint8_t RESERVED80[2]; + union { + __IO uint32_t OCSE5; + stc_mft_ocu_ocse5_field_t OCSE5_f; + struct { + union { + __IO uint16_t OCSE5L; + struct { + __IO uint8_t OCSE5LL; + __IO uint8_t OCSE5LH; + }; + }; + union { + __IO uint16_t OCSE5H; + struct { + __IO uint8_t OCSE5HL; + __IO uint8_t OCSE5HH; + }; + }; + }; + }; + __IO uint8_t RESERVED81[40]; + union { + __IO uint8_t OCFS10; + stc_mft_ocu_ocfs10_field_t OCFS10_f; + }; + union { + __IO uint8_t OCFS32; + stc_mft_ocu_ocfs32_field_t OCFS32_f; + }; + union { + __IO uint8_t OCFS54; + stc_mft_ocu_ocfs54_field_t OCFS54_f; + }; +} FM_MFT_OCU_TypeDef, FM4_MFT_OCU_TypeDef; + +/******************************************************************************* +* MFT_WFG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED82[398]; + union { + __IO uint16_t WFTF10; + struct { + __IO uint8_t WFTF10L; + __IO uint8_t WFTF10H; + }; + }; + union { + __IO uint16_t WFTA10; + struct { + __IO uint8_t WFTA10L; + __IO uint8_t WFTA10H; + }; + }; + union { + __IO uint16_t WFTB10; + struct { + __IO uint8_t WFTB10L; + __IO uint8_t WFTB10H; + }; + }; + __IO uint8_t RESERVED83[2]; + union { + __IO uint16_t WFTF32; + struct { + __IO uint8_t WFTF32L; + __IO uint8_t WFTF32H; + }; + }; + union { + __IO uint16_t WFTA32; + struct { + __IO uint8_t WFTA32L; + __IO uint8_t WFTA32H; + }; + }; + union { + __IO uint16_t WFTB32; + struct { + __IO uint8_t WFTB32L; + __IO uint8_t WFTB32H; + }; + }; + __IO uint8_t RESERVED84[2]; + union { + __IO uint16_t WFTF54; + struct { + __IO uint8_t WFTF54L; + __IO uint8_t WFTF54H; + }; + }; + union { + __IO uint16_t WFTA54; + struct { + __IO uint8_t WFTA54L; + __IO uint8_t WFTA54H; + }; + }; + union { + __IO uint16_t WFTB54; + struct { + __IO uint8_t WFTB54L; + __IO uint8_t WFTB54H; + }; + }; + union { + __IO uint16_t WFSA10; + stc_mft_wfg_wfsa10_field_t WFSA10_f; + struct { + __IO uint8_t WFSA10L; + __IO uint8_t WFSA10H; + }; + }; + __IO uint8_t RESERVED85[2]; + union { + __IO uint16_t WFSA32; + stc_mft_wfg_wfsa32_field_t WFSA32_f; + struct { + __IO uint8_t WFSA32L; + __IO uint8_t WFSA32H; + }; + }; + __IO uint8_t RESERVED86[2]; + union { + __IO uint16_t WFSA54; + stc_mft_wfg_wfsa54_field_t WFSA54_f; + struct { + __IO uint8_t WFSA54L; + __IO uint8_t WFSA54H; + }; + }; + __IO uint8_t RESERVED87[2]; + union { + __IO uint16_t WFIR; + stc_mft_wfg_wfir_field_t WFIR_f; + struct { + __IO uint8_t WFIRL; + __IO uint8_t WFIRH; + }; + }; + __IO uint8_t RESERVED88[2]; + union { + __IO uint16_t NZCL; + stc_mft_wfg_nzcl_field_t NZCL_f; + struct { + __IO uint8_t NZCLL; + __IO uint8_t NZCLH; + }; + }; +} FM_MFT_WFG_TypeDef, FM4_MFT_WFG_TypeDef; + +/******************************************************************************* +* MFT_PPG_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[1]; + union { + __IO uint8_t TTCR0; + stc_mft_ppg_ttcr0_field_t TTCR0_f; + }; + __IO uint8_t RESERVED1[7]; + __IO uint8_t COMP0; + __IO uint8_t RESERVED2[2]; + __IO uint8_t COMP2; + __IO uint8_t RESERVED3[4]; + __IO uint8_t COMP4; + __IO uint8_t RESERVED4[2]; + __IO uint8_t COMP6; + __IO uint8_t RESERVED5[12]; + union { + __IO uint8_t TTCR1; + stc_mft_ppg_ttcr1_field_t TTCR1_f; + }; + __IO uint8_t RESERVED6[7]; + __IO uint8_t COMP1; + __IO uint8_t RESERVED7[2]; + __IO uint8_t COMP3; + __IO uint8_t RESERVED8[4]; + __IO uint8_t COMP5; + __IO uint8_t RESERVED9[2]; + __IO uint8_t COMP7; + __IO uint8_t RESERVED10[12]; + union { + __IO uint8_t TTCR2; + stc_mft_ppg_ttcr2_field_t TTCR2_f; + }; + __IO uint8_t RESERVED11[7]; + __IO uint8_t COMP8; + __IO uint8_t RESERVED12[2]; + __IO uint8_t COMP10; + __IO uint8_t RESERVED13[4]; + __IO uint8_t COMP12; + __IO uint8_t RESERVED14[2]; + __IO uint8_t COMP14; + __IO uint8_t RESERVED15[171]; + union { + __IO uint16_t TRG0; + stc_mft_ppg_trg0_field_t TRG0_f; + struct { + __IO uint8_t TRG0L; + __IO uint8_t TRG0H; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint16_t REVC0; + stc_mft_ppg_revc0_field_t REVC0_f; + struct { + __IO uint8_t REVC0L; + __IO uint8_t REVC0H; + }; + }; + __IO uint8_t RESERVED17[58]; + union { + __IO uint16_t TRG1; + stc_mft_ppg_trg1_field_t TRG1_f; + struct { + __IO uint8_t TRG1L; + __IO uint8_t TRG1H; + }; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint16_t REVC1; + stc_mft_ppg_revc1_field_t REVC1_f; + struct { + __IO uint8_t REVC1L; + __IO uint8_t REVC1H; + }; + }; + __IO uint8_t RESERVED19[186]; + union { + __IO uint8_t PPGC1; + stc_mft_ppg_ppgc1_field_t PPGC1_f; + }; + union { + __IO uint8_t PPGC0; + stc_mft_ppg_ppgc0_field_t PPGC0_f; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint8_t PPGC3; + stc_mft_ppg_ppgc3_field_t PPGC3_f; + }; + union { + __IO uint8_t PPGC2; + stc_mft_ppg_ppgc2_field_t PPGC2_f; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint8_t PRLL0; + stc_mft_ppg_prll0_field_t PRLL0_f; + }; + union { + __IO uint8_t PRLH0; + stc_mft_ppg_prlh0_field_t PRLH0_f; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint8_t PRLL1; + stc_mft_ppg_prll1_field_t PRLL1_f; + }; + union { + __IO uint8_t PRLH1; + stc_mft_ppg_prlh1_field_t PRLH1_f; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint8_t PRLL2; + stc_mft_ppg_prll2_field_t PRLL2_f; + }; + union { + __IO uint8_t PRLH2; + stc_mft_ppg_prlh2_field_t PRLH2_f; + }; + __IO uint8_t RESERVED24[2]; + union { + __IO uint8_t PRLL3; + stc_mft_ppg_prll3_field_t PRLL3_f; + }; + union { + __IO uint8_t PRLH3; + stc_mft_ppg_prlh3_field_t PRLH3_f; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint8_t GATEC0; + stc_mft_ppg_gatec0_field_t GATEC0_f; + }; + __IO uint8_t RESERVED26[39]; + union { + __IO uint8_t PPGC5; + stc_mft_ppg_ppgc5_field_t PPGC5_f; + }; + union { + __IO uint8_t PPGC4; + stc_mft_ppg_ppgc4_field_t PPGC4_f; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint8_t PPGC7; + stc_mft_ppg_ppgc7_field_t PPGC7_f; + }; + union { + __IO uint8_t PPGC6; + stc_mft_ppg_ppgc6_field_t PPGC6_f; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint8_t PRLL4; + stc_mft_ppg_prll4_field_t PRLL4_f; + }; + union { + __IO uint8_t PRLH4; + stc_mft_ppg_prlh4_field_t PRLH4_f; + }; + __IO uint8_t RESERVED29[2]; + union { + __IO uint8_t PRLL5; + stc_mft_ppg_prll5_field_t PRLL5_f; + }; + union { + __IO uint8_t PRLH5; + stc_mft_ppg_prlh5_field_t PRLH5_f; + }; + __IO uint8_t RESERVED30[2]; + union { + __IO uint8_t PRLL6; + stc_mft_ppg_prll6_field_t PRLL6_f; + }; + union { + __IO uint8_t PRLH6; + stc_mft_ppg_prlh6_field_t PRLH6_f; + }; + __IO uint8_t RESERVED31[2]; + union { + __IO uint8_t PRLL7; + stc_mft_ppg_prll7_field_t PRLL7_f; + }; + union { + __IO uint8_t PRLH7; + stc_mft_ppg_prlh7_field_t PRLH7_f; + }; + __IO uint8_t RESERVED32[2]; + union { + __IO uint8_t GATEC4; + stc_mft_ppg_gatec4_field_t GATEC4_f; + }; + __IO uint8_t RESERVED33[39]; + union { + __IO uint8_t PPGC9; + stc_mft_ppg_ppgc9_field_t PPGC9_f; + }; + union { + __IO uint8_t PPGC8; + stc_mft_ppg_ppgc8_field_t PPGC8_f; + }; + __IO uint8_t RESERVED34[2]; + union { + __IO uint8_t PPGC11; + stc_mft_ppg_ppgc11_field_t PPGC11_f; + }; + union { + __IO uint8_t PPGC10; + stc_mft_ppg_ppgc10_field_t PPGC10_f; + }; + __IO uint8_t RESERVED35[2]; + union { + __IO uint8_t PRLL8; + stc_mft_ppg_prll8_field_t PRLL8_f; + }; + union { + __IO uint8_t PRLH8; + stc_mft_ppg_prlh8_field_t PRLH8_f; + }; + __IO uint8_t RESERVED36[2]; + union { + __IO uint8_t PRLL9; + stc_mft_ppg_prll9_field_t PRLL9_f; + }; + union { + __IO uint8_t PRLH9; + stc_mft_ppg_prlh9_field_t PRLH9_f; + }; + __IO uint8_t RESERVED37[2]; + union { + __IO uint8_t PRLL10; + stc_mft_ppg_prll10_field_t PRLL10_f; + }; + union { + __IO uint8_t PRLH10; + stc_mft_ppg_prlh10_field_t PRLH10_f; + }; + __IO uint8_t RESERVED38[2]; + union { + __IO uint8_t PRLL11; + stc_mft_ppg_prll11_field_t PRLL11_f; + }; + union { + __IO uint8_t PRLH11; + stc_mft_ppg_prlh11_field_t PRLH11_f; + }; + __IO uint8_t RESERVED39[2]; + union { + __IO uint8_t GATEC8; + stc_mft_ppg_gatec8_field_t GATEC8_f; + }; + __IO uint8_t RESERVED40[39]; + union { + __IO uint8_t PPGC13; + stc_mft_ppg_ppgc13_field_t PPGC13_f; + }; + union { + __IO uint8_t PPGC12; + stc_mft_ppg_ppgc12_field_t PPGC12_f; + }; + __IO uint8_t RESERVED41[2]; + union { + __IO uint8_t PPGC15; + stc_mft_ppg_ppgc15_field_t PPGC15_f; + }; + union { + __IO uint8_t PPGC14; + stc_mft_ppg_ppgc14_field_t PPGC14_f; + }; + __IO uint8_t RESERVED42[2]; + union { + __IO uint8_t PRLL12; + stc_mft_ppg_prll12_field_t PRLL12_f; + }; + union { + __IO uint8_t PRLH12; + stc_mft_ppg_prlh12_field_t PRLH12_f; + }; + __IO uint8_t RESERVED43[2]; + union { + __IO uint8_t PRLL13; + stc_mft_ppg_prll13_field_t PRLL13_f; + }; + union { + __IO uint8_t PRLH13; + stc_mft_ppg_prlh13_field_t PRLH13_f; + }; + __IO uint8_t RESERVED44[2]; + union { + __IO uint8_t PRLL14; + stc_mft_ppg_prll14_field_t PRLL14_f; + }; + union { + __IO uint8_t PRLH14; + stc_mft_ppg_prlh14_field_t PRLH14_f; + }; + __IO uint8_t RESERVED45[2]; + union { + __IO uint8_t PRLL15; + stc_mft_ppg_prll15_field_t PRLL15_f; + }; + union { + __IO uint8_t PRLH15; + stc_mft_ppg_prlh15_field_t PRLH15_f; + }; + __IO uint8_t RESERVED46[2]; + union { + __IO uint8_t GATEC12; + stc_mft_ppg_gatec12_field_t GATEC12_f; + }; + __IO uint8_t RESERVED47[39]; + union { + __IO uint8_t PPGC17; + stc_mft_ppg_ppgc17_field_t PPGC17_f; + }; + union { + __IO uint8_t PPGC16; + stc_mft_ppg_ppgc16_field_t PPGC16_f; + }; + __IO uint8_t RESERVED48[2]; + union { + __IO uint8_t PPGC19; + stc_mft_ppg_ppgc19_field_t PPGC19_f; + }; + union { + __IO uint8_t PPGC18; + stc_mft_ppg_ppgc18_field_t PPGC18_f; + }; + __IO uint8_t RESERVED49[2]; + union { + __IO uint8_t PRLL16; + stc_mft_ppg_prll16_field_t PRLL16_f; + }; + union { + __IO uint8_t PRLH16; + stc_mft_ppg_prlh16_field_t PRLH16_f; + }; + __IO uint8_t RESERVED50[2]; + union { + __IO uint8_t PRLL17; + stc_mft_ppg_prll17_field_t PRLL17_f; + }; + union { + __IO uint8_t PRLH17; + stc_mft_ppg_prlh17_field_t PRLH17_f; + }; + __IO uint8_t RESERVED51[2]; + union { + __IO uint8_t PRLL18; + stc_mft_ppg_prll18_field_t PRLL18_f; + }; + union { + __IO uint8_t PRLH18; + stc_mft_ppg_prlh18_field_t PRLH18_f; + }; + __IO uint8_t RESERVED52[2]; + union { + __IO uint8_t PRLL19; + stc_mft_ppg_prll19_field_t PRLL19_f; + }; + union { + __IO uint8_t PRLH19; + stc_mft_ppg_prlh19_field_t PRLH19_f; + }; + __IO uint8_t RESERVED53[2]; + union { + __IO uint8_t GATEC16; + stc_mft_ppg_gatec16_field_t GATEC16_f; + }; + __IO uint8_t RESERVED54[39]; + union { + __IO uint8_t PPGC21; + stc_mft_ppg_ppgc21_field_t PPGC21_f; + }; + union { + __IO uint8_t PPGC20; + stc_mft_ppg_ppgc20_field_t PPGC20_f; + }; + __IO uint8_t RESERVED55[2]; + union { + __IO uint8_t PPGC23; + stc_mft_ppg_ppgc23_field_t PPGC23_f; + }; + union { + __IO uint8_t PPGC22; + stc_mft_ppg_ppgc22_field_t PPGC22_f; + }; + __IO uint8_t RESERVED56[2]; + union { + __IO uint8_t PRLL20; + stc_mft_ppg_prll20_field_t PRLL20_f; + }; + union { + __IO uint8_t PRLH20; + stc_mft_ppg_prlh20_field_t PRLH20_f; + }; + __IO uint8_t RESERVED57[2]; + union { + __IO uint8_t PRLL21; + stc_mft_ppg_prll21_field_t PRLL21_f; + }; + union { + __IO uint8_t PRLH21; + stc_mft_ppg_prlh21_field_t PRLH21_f; + }; + __IO uint8_t RESERVED58[2]; + union { + __IO uint8_t PRLL22; + stc_mft_ppg_prll22_field_t PRLL22_f; + }; + union { + __IO uint8_t PRLH22; + stc_mft_ppg_prlh22_field_t PRLH22_f; + }; + __IO uint8_t RESERVED59[2]; + union { + __IO uint8_t PRLL23; + stc_mft_ppg_prll23_field_t PRLL23_f; + }; + union { + __IO uint8_t PRLH23; + stc_mft_ppg_prlh23_field_t PRLH23_f; + }; + __IO uint8_t RESERVED60[2]; + union { + __IO uint8_t GATEC20; + stc_mft_ppg_gatec20_field_t GATEC20_f; + }; +} FM_MFT_PPG_TypeDef, FM4_MFT_PPG_TypeDef; + +/******************************************************************************* +* PCRC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t PCRC_POLY; + struct { + union { + __IO uint16_t PCRC_POLYL; + struct { + __IO uint8_t PCRC_POLYLL; + __IO uint8_t PCRC_POLYLH; + }; + }; + union { + __IO uint16_t PCRC_POLYH; + struct { + __IO uint8_t PCRC_POLYHL; + __IO uint8_t PCRC_POLYHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_SEED; + struct { + union { + __IO uint16_t PCRC_SEEDL; + struct { + __IO uint8_t PCRC_SEEDLL; + __IO uint8_t PCRC_SEEDLH; + }; + }; + union { + __IO uint16_t PCRC_SEEDH; + struct { + __IO uint8_t PCRC_SEEDHL; + __IO uint8_t PCRC_SEEDHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_FXOR; + struct { + union { + __IO uint16_t PCRC_FXORL; + struct { + __IO uint8_t PCRC_FXORLL; + __IO uint8_t PCRC_FXORLH; + }; + }; + union { + __IO uint16_t PCRC_FXORH; + struct { + __IO uint8_t PCRC_FXORHL; + __IO uint8_t PCRC_FXORHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_CFG; + stc_pcrc_pcrc_cfg_field_t PCRC_CFG_f; + struct { + union { + __IO uint16_t PCRC_CFGL; + struct { + __IO uint8_t PCRC_CFGLL; + __IO uint8_t PCRC_CFGLH; + }; + }; + union { + __IO uint16_t PCRC_CFGH; + struct { + __IO uint8_t PCRC_CFGHL; + __IO uint8_t PCRC_CFGHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_WR; + struct { + union { + __IO uint16_t PCRC_WRL; + struct { + __IO uint8_t PCRC_WRLL; + __IO uint8_t PCRC_WRLH; + }; + }; + union { + __IO uint16_t PCRC_WRH; + struct { + __IO uint8_t PCRC_WRHL; + __IO uint8_t PCRC_WRHH; + }; + }; + }; + }; + union { + __IO uint32_t PCRC_RD; + struct { + union { + __IO uint16_t PCRC_RDL; + struct { + __IO uint8_t PCRC_RDLL; + __IO uint8_t PCRC_RDLH; + }; + }; + union { + __IO uint16_t PCRC_RDH; + struct { + __IO uint8_t PCRC_RDHL; + __IO uint8_t PCRC_RDHH; + }; + }; + }; + }; +} FM_PCRC_TypeDef, FM4_PCRC_TypeDef; + +/******************************************************************************* +* QPRC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint16_t QPCR; + struct { + __IO uint8_t QPCRL; + __IO uint8_t QPCRH; + }; + }; + __IO uint8_t RESERVED0[2]; + union { + __IO uint16_t QRCR; + struct { + __IO uint8_t QRCRL; + __IO uint8_t QRCRH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint16_t QPCCR; + struct { + __IO uint8_t QPCCRL; + __IO uint8_t QPCCRH; + }; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint16_t QPRCR; + struct { + __IO uint8_t QPRCRL; + __IO uint8_t QPRCRH; + }; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint16_t QMPR; + struct { + __IO uint8_t QMPRL; + __IO uint8_t QMPRH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint8_t QICRL; + stc_qprc_qicrl_field_t QICRL_f; + }; + union { + __IO uint8_t QICRH; + stc_qprc_qicrh_field_t QICRH_f; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t QCR; + stc_qprc_qcr_field_t QCR_f; + struct { + __IO uint8_t QCRL; + __IO uint8_t QCRH; + }; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint16_t QECR; + stc_qprc_qecr_field_t QECR_f; + struct { + __IO uint8_t QECRL; + __IO uint8_t QECRH; + }; + }; + __IO uint8_t RESERVED7[30]; + union { + __IO uint32_t QPRCRR; + stc_qprc_qprcrr_field_t QPRCRR_f; + struct { + union { + __IO uint16_t QPRCRRL; + struct { + __IO uint8_t QPRCRRLL; + __IO uint8_t QPRCRRLH; + }; + }; + union { + __IO uint16_t QPRCRRH; + struct { + __IO uint8_t QPRCRRHL; + __IO uint8_t QPRCRRHH; + }; + }; + }; + }; +} FM_QPRC_TypeDef, FM4_QPRC_TypeDef; + +/******************************************************************************* +* QPRC_NF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t NFCTLA; + stc_qprc_nf_nfctla_field_t NFCTLA_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t NFCTLB; + stc_qprc_nf_nfctlb_field_t NFCTLB_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t NFCTLZ; + stc_qprc_nf_nfctlz_field_t NFCTLZ_f; + }; +} FM_QPRC_NF_TypeDef, FM4_QPRC_NF_TypeDef; + +/******************************************************************************* +* RTC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t WTCR10; + stc_rtc_wtcr10_field_t WTCR10_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t WTCR11; + stc_rtc_wtcr11_field_t WTCR11_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t WTCR12; + stc_rtc_wtcr12_field_t WTCR12_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint8_t WTCR13; + stc_rtc_wtcr13_field_t WTCR13_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint8_t WTCR20; + stc_rtc_wtcr20_field_t WTCR20_f; + }; + __IO uint8_t RESERVED4[3]; + union { + __IO uint8_t WTCR21; + stc_rtc_wtcr21_field_t WTCR21_f; + }; + __IO uint8_t RESERVED5[7]; + union { + __IO uint8_t WTSR; + stc_rtc_wtsr_field_t WTSR_f; + }; + __IO uint8_t RESERVED6[3]; + union { + __IO uint8_t WTMIR; + stc_rtc_wtmir_field_t WTMIR_f; + }; + __IO uint8_t RESERVED7[3]; + union { + __IO uint8_t WTHR; + stc_rtc_wthr_field_t WTHR_f; + }; + __IO uint8_t RESERVED8[3]; + union { + __IO uint8_t WTDR; + stc_rtc_wtdr_field_t WTDR_f; + }; + __IO uint8_t RESERVED9[3]; + union { + __IO uint8_t WTDW; + stc_rtc_wtdw_field_t WTDW_f; + }; + __IO uint8_t RESERVED10[3]; + union { + __IO uint8_t WTMOR; + stc_rtc_wtmor_field_t WTMOR_f; + }; + __IO uint8_t RESERVED11[3]; + union { + __IO uint8_t WTYR; + stc_rtc_wtyr_field_t WTYR_f; + }; + __IO uint8_t RESERVED12[3]; + union { + __IO uint8_t ALMIR; + stc_rtc_almir_field_t ALMIR_f; + }; + __IO uint8_t RESERVED13[3]; + union { + __IO uint8_t ALHR; + stc_rtc_alhr_field_t ALHR_f; + }; + __IO uint8_t RESERVED14[3]; + union { + __IO uint8_t ALDR; + stc_rtc_aldr_field_t ALDR_f; + }; + __IO uint8_t RESERVED15[3]; + union { + __IO uint8_t ALMOR; + stc_rtc_almor_field_t ALMOR_f; + }; + __IO uint8_t RESERVED16[3]; + union { + __IO uint8_t ALYR; + stc_rtc_alyr_field_t ALYR_f; + }; + __IO uint8_t RESERVED17[3]; + union { + __IO uint8_t WTTR0; + stc_rtc_wttr0_field_t WTTR0_f; + }; + __IO uint8_t RESERVED18[3]; + union { + __IO uint8_t WTTR1; + stc_rtc_wttr1_field_t WTTR1_f; + }; + __IO uint8_t RESERVED19[3]; + union { + __IO uint8_t WTTR2; + stc_rtc_wttr2_field_t WTTR2_f; + }; + __IO uint8_t RESERVED20[3]; + union { + __IO uint8_t WTCAL0; + stc_rtc_wtcal0_field_t WTCAL0_f; + }; + __IO uint8_t RESERVED21[3]; + union { + __IO uint8_t WTCAL1; + stc_rtc_wtcal1_field_t WTCAL1_f; + }; + __IO uint8_t RESERVED22[3]; + union { + __IO uint8_t WTCALEN; + stc_rtc_wtcalen_field_t WTCALEN_f; + }; + __IO uint8_t RESERVED23[3]; + union { + __IO uint8_t WTDIV; + stc_rtc_wtdiv_field_t WTDIV_f; + }; + __IO uint8_t RESERVED24[3]; + union { + __IO uint8_t WTDIVEN; + stc_rtc_wtdiven_field_t WTDIVEN_f; + }; + __IO uint8_t RESERVED25[3]; + union { + __IO uint8_t WTCALPRD; + stc_rtc_wtcalprd_field_t WTCALPRD_f; + }; + __IO uint8_t RESERVED26[3]; + union { + __IO uint8_t WTCOSEL; + stc_rtc_wtcosel_field_t WTCOSEL_f; + }; + __IO uint8_t RESERVED27[3]; + union { + __IO uint8_t VB_CLKDIV; + stc_rtc_vb_clkdiv_field_t VB_CLKDIV_f; + }; + __IO uint8_t RESERVED28[3]; + union { + __IO uint8_t WTOSCCNT; + stc_rtc_wtosccnt_field_t WTOSCCNT_f; + }; + __IO uint8_t RESERVED29[3]; + union { + __IO uint8_t CCS; + stc_rtc_ccs_field_t CCS_f; + }; + __IO uint8_t RESERVED30[3]; + union { + __IO uint8_t CCB; + stc_rtc_ccb_field_t CCB_f; + }; + __IO uint8_t RESERVED31[7]; + union { + __IO uint8_t BOOST; + stc_rtc_boost_field_t BOOST_f; + }; + __IO uint8_t RESERVED32[3]; + union { + __IO uint8_t EWKUP; + stc_rtc_ewkup_field_t EWKUP_f; + }; + __IO uint8_t RESERVED33[3]; + union { + __IO uint8_t VDET; + stc_rtc_vdet_field_t VDET_f; + }; + __IO uint8_t RESERVED34[7]; + union { + __IO uint8_t HIBRST; + stc_rtc_hibrst_field_t HIBRST_f; + }; + __IO uint8_t RESERVED35[3]; + union { + __IO uint8_t VBPFR; + stc_rtc_vbpfr_field_t VBPFR_f; + }; + __IO uint8_t RESERVED36[3]; + union { + __IO uint8_t VBPCR; + stc_rtc_vbpcr_field_t VBPCR_f; + }; + __IO uint8_t RESERVED37[3]; + union { + __IO uint8_t VBDDR; + stc_rtc_vbddr_field_t VBDDR_f; + }; + __IO uint8_t RESERVED38[3]; + union { + __IO uint8_t VBDIR; + stc_rtc_vbdir_field_t VBDIR_f; + }; + __IO uint8_t RESERVED39[3]; + union { + __IO uint8_t VBDOR; + stc_rtc_vbdor_field_t VBDOR_f; + }; + __IO uint8_t RESERVED40[3]; + union { + __IO uint8_t VBPZR; + stc_rtc_vbpzr_field_t VBPZR_f; + }; + __IO uint8_t RESERVED41[79]; + __IO uint8_t BREG00; + __IO uint8_t BREG01; + __IO uint8_t BREG02; + __IO uint8_t BREG03; + __IO uint8_t BREG04; + __IO uint8_t BREG05; + __IO uint8_t BREG06; + __IO uint8_t BREG07; + __IO uint8_t BREG08; + __IO uint8_t BREG09; + __IO uint8_t BREG0A; + __IO uint8_t BREG0B; + __IO uint8_t BREG0C; + __IO uint8_t BREG0D; + __IO uint8_t BREG0E; + __IO uint8_t BREG0F; + __IO uint8_t BREG10; + __IO uint8_t BREG11; + __IO uint8_t BREG12; + __IO uint8_t BREG13; + __IO uint8_t BREG14; + __IO uint8_t BREG15; + __IO uint8_t BREG16; + __IO uint8_t BREG17; + __IO uint8_t BREG18; + __IO uint8_t BREG19; + __IO uint8_t BREG1A; + __IO uint8_t BREG1B; + __IO uint8_t BREG1C; + __IO uint8_t BREG1D; + __IO uint8_t BREG1E; + __IO uint8_t BREG1F; + __IO uint8_t BREG20; + __IO uint8_t BREG21; + __IO uint8_t BREG22; + __IO uint8_t BREG23; + __IO uint8_t BREG24; + __IO uint8_t BREG25; + __IO uint8_t BREG26; + __IO uint8_t BREG27; + __IO uint8_t BREG28; + __IO uint8_t BREG29; + __IO uint8_t BREG2A; + __IO uint8_t BREG2B; + __IO uint8_t BREG2C; + __IO uint8_t BREG2D; + __IO uint8_t BREG2E; + __IO uint8_t BREG2F; + __IO uint8_t BREG30; + __IO uint8_t BREG31; + __IO uint8_t BREG32; + __IO uint8_t BREG33; + __IO uint8_t BREG34; + __IO uint8_t BREG35; + __IO uint8_t BREG36; + __IO uint8_t BREG37; + __IO uint8_t BREG38; + __IO uint8_t BREG39; + __IO uint8_t BREG3A; + __IO uint8_t BREG3B; + __IO uint8_t BREG3C; + __IO uint8_t BREG3D; + __IO uint8_t BREG3E; + __IO uint8_t BREG3F; + __IO uint8_t BREG40; + __IO uint8_t BREG41; + __IO uint8_t BREG42; + __IO uint8_t BREG43; + __IO uint8_t BREG44; + __IO uint8_t BREG45; + __IO uint8_t BREG46; + __IO uint8_t BREG47; + __IO uint8_t BREG48; + __IO uint8_t BREG49; + __IO uint8_t BREG4A; + __IO uint8_t BREG4B; + __IO uint8_t BREG4C; + __IO uint8_t BREG4D; + __IO uint8_t BREG4E; + __IO uint8_t BREG4F; + __IO uint8_t BREG50; + __IO uint8_t BREG51; + __IO uint8_t BREG52; + __IO uint8_t BREG53; + __IO uint8_t BREG54; + __IO uint8_t BREG55; + __IO uint8_t BREG56; + __IO uint8_t BREG57; + __IO uint8_t BREG58; + __IO uint8_t BREG59; + __IO uint8_t BREG5A; + __IO uint8_t BREG5B; + __IO uint8_t BREG5C; + __IO uint8_t BREG5D; + __IO uint8_t BREG5E; + __IO uint8_t BREG5F; + __IO uint8_t BREG60; + __IO uint8_t BREG61; + __IO uint8_t BREG62; + __IO uint8_t BREG63; + __IO uint8_t BREG64; + __IO uint8_t BREG65; + __IO uint8_t BREG66; + __IO uint8_t BREG67; + __IO uint8_t BREG68; + __IO uint8_t BREG69; + __IO uint8_t BREG6A; + __IO uint8_t BREG6B; + __IO uint8_t BREG6C; + __IO uint8_t BREG6D; + __IO uint8_t BREG6E; + __IO uint8_t BREG6F; + __IO uint8_t BREG70; + __IO uint8_t BREG71; + __IO uint8_t BREG72; + __IO uint8_t BREG73; + __IO uint8_t BREG74; + __IO uint8_t BREG75; + __IO uint8_t BREG76; + __IO uint8_t BREG77; + __IO uint8_t BREG78; + __IO uint8_t BREG79; + __IO uint8_t BREG7A; + __IO uint8_t BREG7B; + __IO uint8_t BREG7C; + __IO uint8_t BREG7D; + __IO uint8_t BREG7E; + __IO uint8_t BREG7F; +} FM_RTC_TypeDef, FM4_RTC_TypeDef; + +/******************************************************************************* +* SBSSR_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[252]; + union { + __IO uint16_t BTSSSR; + stc_sbssr_btsssr_field_t BTSSSR_f; + struct { + __IO uint8_t BTSSSRL; + __IO uint8_t BTSSSRH; + }; + }; +} FM_SBSSR_TypeDef, FM4_SBSSR_TypeDef; + +/******************************************************************************* +* SDIF_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t SSA2; + struct { + union { + __IO uint16_t SSA2L; + struct { + __IO uint8_t SSA2LL; + __IO uint8_t SSA2LH; + }; + }; + union { + __IO uint16_t SSA2H; + struct { + __IO uint8_t SSA2HL; + __IO uint8_t SSA2HH; + }; + }; + }; + }; + union { + __IO uint16_t SBSIZE; + stc_sdif_sbsize_field_t SBSIZE_f; + struct { + __IO uint8_t SBSIZEL; + __IO uint8_t SBSIZEH; + }; + }; + union { + __IO uint16_t SBLCNT; + struct { + __IO uint8_t SBLCNTL; + __IO uint8_t SBLCNTH; + }; + }; + union { + __IO uint32_t SSA1; + struct { + union { + __IO uint16_t SSA1L; + struct { + __IO uint8_t SSA1LL; + __IO uint8_t SSA1LH; + }; + }; + union { + __IO uint16_t SSA1H; + struct { + __IO uint8_t SSA1HL; + __IO uint8_t SSA1HH; + }; + }; + }; + }; + union { + __IO uint16_t STRSFMD; + stc_sdif_strsfmd_field_t STRSFMD_f; + struct { + __IO uint8_t STRSFMDL; + __IO uint8_t STRSFMDH; + }; + }; + union { + __IO uint16_t SCMMD; + stc_sdif_scmmd_field_t SCMMD_f; + struct { + __IO uint8_t SCMMDL; + __IO uint8_t SCMMDH; + }; + }; + union { + __IO uint16_t SRESP0; + struct { + __IO uint8_t SRESP0L; + __IO uint8_t SRESP0H; + }; + }; + union { + __IO uint16_t SRESP1; + struct { + __IO uint8_t SRESP1L; + __IO uint8_t SRESP1H; + }; + }; + union { + __IO uint16_t SRESP2; + struct { + __IO uint8_t SRESP2L; + __IO uint8_t SRESP2H; + }; + }; + union { + __IO uint16_t SRESP3; + struct { + __IO uint8_t SRESP3L; + __IO uint8_t SRESP3H; + }; + }; + union { + __IO uint16_t SRESP4; + struct { + __IO uint8_t SRESP4L; + __IO uint8_t SRESP4H; + }; + }; + union { + __IO uint16_t SRESP5; + struct { + __IO uint8_t SRESP5L; + __IO uint8_t SRESP5H; + }; + }; + union { + __IO uint16_t SRESP6; + struct { + __IO uint8_t SRESP6L; + __IO uint8_t SRESP6H; + }; + }; + union { + __IO uint16_t SRESP7; + struct { + __IO uint8_t SRESP7L; + __IO uint8_t SRESP7H; + }; + }; + union { + __IO uint32_t SBUFDP; + struct { + union { + __IO uint16_t SBUFDPL; + struct { + __IO uint8_t SBUFDPLL; + __IO uint8_t SBUFDPLH; + }; + }; + union { + __IO uint16_t SBUFDPH; + struct { + __IO uint8_t SBUFDPHL; + __IO uint8_t SBUFDPHH; + }; + }; + }; + }; + union { + __IO uint32_t SPRSTAT; + stc_sdif_sprstat_field_t SPRSTAT_f; + struct { + union { + __IO uint16_t SPRSTATL; + struct { + __IO uint8_t SPRSTATLL; + __IO uint8_t SPRSTATLH; + }; + }; + union { + __IO uint16_t SPRSTATH; + struct { + __IO uint8_t SPRSTATHL; + __IO uint8_t SPRSTATHH; + }; + }; + }; + }; + union { + __IO uint8_t SHCTL1; + stc_sdif_shctl1_field_t SHCTL1_f; + }; + union { + __IO uint8_t SPWRCTL; + stc_sdif_spwrctl_field_t SPWRCTL_f; + }; + union { + __IO uint8_t SBLKGPCTL; + stc_sdif_sblkgpctl_field_t SBLKGPCTL_f; + }; + union { + __IO uint8_t SWKUPCTL; + stc_sdif_swkupctl_field_t SWKUPCTL_f; + }; + union { + __IO uint16_t SCLKCTL; + stc_sdif_sclkctl_field_t SCLKCTL_f; + struct { + __IO uint8_t SCLKCTLL; + __IO uint8_t SCLKCTLH; + }; + }; + union { + __IO uint8_t STOCTL; + stc_sdif_stoctl_field_t STOCTL_f; + }; + union { + __IO uint8_t SSRST; + stc_sdif_ssrst_field_t SSRST_f; + }; + union { + __IO uint16_t SNINTST; + stc_sdif_snintst_field_t SNINTST_f; + struct { + __IO uint8_t SNINTSTL; + __IO uint8_t SNINTSTH; + }; + }; + union { + __IO uint16_t SEINTST; + stc_sdif_seintst_field_t SEINTST_f; + struct { + __IO uint8_t SEINTSTL; + __IO uint8_t SEINTSTH; + }; + }; + union { + __IO uint16_t SNINTSTE; + stc_sdif_snintste_field_t SNINTSTE_f; + struct { + __IO uint8_t SNINTSTEL; + __IO uint8_t SNINTSTEH; + }; + }; + union { + __IO uint16_t SEINTSTE; + stc_sdif_seintste_field_t SEINTSTE_f; + struct { + __IO uint8_t SEINTSTEL; + __IO uint8_t SEINTSTEH; + }; + }; + union { + __IO uint16_t SNINTSGE; + stc_sdif_snintsge_field_t SNINTSGE_f; + struct { + __IO uint8_t SNINTSGEL; + __IO uint8_t SNINTSGEH; + }; + }; + union { + __IO uint16_t SEINTSGE; + stc_sdif_seintsge_field_t SEINTSGE_f; + struct { + __IO uint8_t SEINTSGEL; + __IO uint8_t SEINTSGEH; + }; + }; + union { + __IO uint16_t SACMDEST; + stc_sdif_sacmdest_field_t SACMDEST_f; + struct { + __IO uint8_t SACMDESTL; + __IO uint8_t SACMDESTH; + }; + }; + union { + __IO uint16_t SHCTL2; + stc_sdif_shctl2_field_t SHCTL2_f; + struct { + __IO uint8_t SHCTL2L; + __IO uint8_t SHCTL2H; + }; + }; + union { + __IO uint16_t CAPBLTY0; + stc_sdif_capblty0_field_t CAPBLTY0_f; + struct { + __IO uint8_t CAPBLTY0L; + __IO uint8_t CAPBLTY0H; + }; + }; + union { + __IO uint16_t CAPBLTY1; + stc_sdif_capblty1_field_t CAPBLTY1_f; + struct { + __IO uint8_t CAPBLTY1L; + __IO uint8_t CAPBLTY1H; + }; + }; + union { + __IO uint16_t CAPBLTY2; + stc_sdif_capblty2_field_t CAPBLTY2_f; + struct { + __IO uint8_t CAPBLTY2L; + __IO uint8_t CAPBLTY2H; + }; + }; + union { + __IO uint16_t CAPBLTY3; + stc_sdif_capblty3_field_t CAPBLTY3_f; + struct { + __IO uint8_t CAPBLTY3L; + __IO uint8_t CAPBLTY3H; + }; + }; + union { + __IO uint16_t MXCCAPY0; + stc_sdif_mxccapy0_field_t MXCCAPY0_f; + struct { + __IO uint8_t MXCCAPY0L; + __IO uint8_t MXCCAPY0H; + }; + }; + union { + __IO uint16_t MXCCAPY1; + stc_sdif_mxccapy1_field_t MXCCAPY1_f; + struct { + __IO uint8_t MXCCAPY1L; + __IO uint8_t MXCCAPY1H; + }; + }; + union { + __IO uint16_t MXCCAPY2; + struct { + __IO uint8_t MXCCAPY2L; + __IO uint8_t MXCCAPY2H; + }; + }; + union { + __IO uint16_t MXCCAPY3; + struct { + __IO uint8_t MXCCAPY3L; + __IO uint8_t MXCCAPY3H; + }; + }; + union { + __IO uint16_t FEACEST; + stc_sdif_feacest_field_t FEACEST_f; + struct { + __IO uint8_t FEACESTL; + __IO uint8_t FEACESTH; + }; + }; + union { + __IO uint16_t SFEEIST; + stc_sdif_sfeeist_field_t SFEEIST_f; + struct { + __IO uint8_t SFEEISTL; + __IO uint8_t SFEEISTH; + }; + }; + union { + __IO uint8_t ADMAEST; + stc_sdif_admaest_field_t ADMAEST_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint16_t SADSA0; + stc_sdif_sadsa0_field_t SADSA0_f; + struct { + __IO uint8_t SADSA0L; + __IO uint8_t SADSA0H; + }; + }; + union { + __IO uint16_t SADSA1; + stc_sdif_sadsa1_field_t SADSA1_f; + struct { + __IO uint8_t SADSA1L; + __IO uint8_t SADSA1H; + }; + }; + union { + __IO uint16_t SADSA2; + stc_sdif_sadsa2_field_t SADSA2_f; + struct { + __IO uint8_t SADSA2L; + __IO uint8_t SADSA2H; + }; + }; + union { + __IO uint16_t SADSA3; + stc_sdif_sadsa3_field_t SADSA3_f; + struct { + __IO uint8_t SADSA3L; + __IO uint8_t SADSA3H; + }; + }; + union { + __IO uint16_t SPRVAL0; + stc_sdif_sprval0_field_t SPRVAL0_f; + struct { + __IO uint8_t SPRVAL0L; + __IO uint8_t SPRVAL0H; + }; + }; + union { + __IO uint16_t SPRVAL1; + stc_sdif_sprval1_field_t SPRVAL1_f; + struct { + __IO uint8_t SPRVAL1L; + __IO uint8_t SPRVAL1H; + }; + }; + union { + __IO uint16_t SPRVAL2; + stc_sdif_sprval2_field_t SPRVAL2_f; + struct { + __IO uint8_t SPRVAL2L; + __IO uint8_t SPRVAL2H; + }; + }; + union { + __IO uint16_t SPRVAL3; + stc_sdif_sprval3_field_t SPRVAL3_f; + struct { + __IO uint8_t SPRVAL3L; + __IO uint8_t SPRVAL3H; + }; + }; + union { + __IO uint16_t SPRVAL4; + stc_sdif_sprval4_field_t SPRVAL4_f; + struct { + __IO uint8_t SPRVAL4L; + __IO uint8_t SPRVAL4H; + }; + }; + union { + __IO uint16_t SPRVAL5; + stc_sdif_sprval5_field_t SPRVAL5_f; + struct { + __IO uint8_t SPRVAL5L; + __IO uint8_t SPRVAL5H; + }; + }; + union { + __IO uint16_t SPRVAL6; + stc_sdif_sprval6_field_t SPRVAL6_f; + struct { + __IO uint8_t SPRVAL6L; + __IO uint8_t SPRVAL6H; + }; + }; + union { + __IO uint16_t SPRVAL7; + stc_sdif_sprval7_field_t SPRVAL7_f; + struct { + __IO uint8_t SPRVAL7L; + __IO uint8_t SPRVAL7H; + }; + }; + __IO uint8_t RESERVED1[112]; + union { + __IO uint16_t SSHBCTLL; + stc_sdif_sshbctll_field_t SSHBCTLL_f; + struct { + __IO uint8_t SSHBCTLLL; + __IO uint8_t SSHBCTLLH; + }; + }; + union { + __IO uint16_t SSHBCTLH; + stc_sdif_sshbctlh_field_t SSHBCTLH_f; + struct { + __IO uint8_t SSHBCTLHL; + __IO uint8_t SSHBCTLHH; + }; + }; + __IO uint8_t RESERVED2[24]; + union { + __IO uint16_t SSLIST; + stc_sdif_sslist_field_t SSLIST_f; + struct { + __IO uint8_t SSLISTL; + __IO uint8_t SSLISTH; + }; + }; + union { + __IO uint16_t SHCTLV; + stc_sdif_shctlv_field_t SHCTLV_f; + struct { + __IO uint8_t SHCTLVL; + __IO uint8_t SHCTLVH; + }; + }; + union { + __IO uint16_t AHBCFGL; + stc_sdif_ahbcfgl_field_t AHBCFGL_f; + struct { + __IO uint8_t AHBCFGLL; + __IO uint8_t AHBCFGLH; + }; + }; + union { + __IO uint16_t AHBCFGH; + struct { + __IO uint8_t AHBCFGHL; + __IO uint8_t AHBCFGHH; + }; + }; + union { + __IO uint16_t SPWSWCL; + stc_sdif_spwswcl_field_t SPWSWCL_f; + struct { + __IO uint8_t SPWSWCLL; + __IO uint8_t SPWSWCLH; + }; + }; + union { + __IO uint16_t SPWSWCH; + struct { + __IO uint8_t SPWSWCHL; + __IO uint8_t SPWSWCHH; + }; + }; + union { + __IO uint16_t STUNSETL; + stc_sdif_stunsetl_field_t STUNSETL_f; + struct { + __IO uint8_t STUNSETLL; + __IO uint8_t STUNSETLH; + }; + }; + union { + __IO uint16_t STUNSETH; + stc_sdif_stunseth_field_t STUNSETH_f; + struct { + __IO uint8_t STUNSETHL; + __IO uint8_t STUNSETHH; + }; + }; + union { + __IO uint16_t STUNSTL; + stc_sdif_stunstl_field_t STUNSTL_f; + struct { + __IO uint8_t STUNSTLL; + __IO uint8_t STUNSTLH; + }; + }; + union { + __IO uint16_t STUNSTH; + stc_sdif_stunsth_field_t STUNSTH_f; + struct { + __IO uint8_t STUNSTHL; + __IO uint8_t STUNSTHH; + }; + }; + __IO uint8_t RESERVED3[8]; + union { + __IO uint16_t PSWISTL; + stc_sdif_pswistl_field_t PSWISTL_f; + struct { + __IO uint8_t PSWISTLL; + __IO uint8_t PSWISTLH; + }; + }; + union { + __IO uint16_t PSWISTH; + struct { + __IO uint8_t PSWISTHL; + __IO uint8_t PSWISTHH; + }; + }; + union { + __IO uint16_t PSWISTEL; + stc_sdif_pswistel_field_t PSWISTEL_f; + struct { + __IO uint8_t PSWISTELL; + __IO uint8_t PSWISTELH; + }; + }; + union { + __IO uint16_t PSWISTEH; + struct { + __IO uint8_t PSWISTEHL; + __IO uint8_t PSWISTEHH; + }; + }; + union { + __IO uint16_t PSWISGEL; + stc_sdif_pswisgel_field_t PSWISGEL_f; + struct { + __IO uint8_t PSWISGELL; + __IO uint8_t PSWISGELH; + }; + }; + union { + __IO uint16_t PSWISGEH; + struct { + __IO uint8_t PSWISGEHL; + __IO uint8_t PSWISGEHH; + }; + }; + union { + __IO uint16_t MMCSDCL; + stc_sdif_mmcsdcl_field_t MMCSDCL_f; + struct { + __IO uint8_t MMCSDCLL; + __IO uint8_t MMCSDCLH; + }; + }; + union { + __IO uint16_t MMCSDCH; + stc_sdif_mmcsdch_field_t MMCSDCH_f; + struct { + __IO uint8_t MMCSDCHL; + __IO uint8_t MMCSDCHH; + }; + }; + union { + __IO uint16_t MCWIRQC0; + stc_sdif_mcwirqc0_field_t MCWIRQC0_f; + struct { + __IO uint8_t MCWIRQC0L; + __IO uint8_t MCWIRQC0H; + }; + }; + union { + __IO uint16_t MCWIRQC1; + stc_sdif_mcwirqc1_field_t MCWIRQC1_f; + struct { + __IO uint8_t MCWIRQC1L; + __IO uint8_t MCWIRQC1H; + }; + }; + union { + __IO uint16_t MCWIRQC2; + stc_sdif_mcwirqc2_field_t MCWIRQC2_f; + struct { + __IO uint8_t MCWIRQC2L; + __IO uint8_t MCWIRQC2H; + }; + }; + union { + __IO uint16_t MCWIRQC3; + stc_sdif_mcwirqc3_field_t MCWIRQC3_f; + struct { + __IO uint8_t MCWIRQC3L; + __IO uint8_t MCWIRQC3H; + }; + }; + union { + __IO uint16_t MCRPCKBL; + stc_sdif_mcrpckbl_field_t MCRPCKBL_f; + struct { + __IO uint8_t MCRPCKBLL; + __IO uint8_t MCRPCKBLH; + }; + }; + union { + __IO uint16_t MCRPCKBH; + struct { + __IO uint8_t MCRPCKBHL; + __IO uint8_t MCRPCKBHH; + }; + }; + __IO uint8_t RESERVED4[32]; + union { + __IO uint16_t SCDETECS; + stc_sdif_scdetecs_field_t SCDETECS_f; + struct { + __IO uint8_t SCDETECSL; + __IO uint8_t SCDETECSH; + }; + }; +} FM_SDIF_TypeDef, FM4_SDIF_TypeDef; + +/******************************************************************************* +* SWWDT_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t WDOGLOAD; + struct { + union { + __IO uint16_t WDOGLOADL; + struct { + __IO uint8_t WDOGLOADLL; + __IO uint8_t WDOGLOADLH; + }; + }; + union { + __IO uint16_t WDOGLOADH; + struct { + __IO uint8_t WDOGLOADHL; + __IO uint8_t WDOGLOADHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGVALUE; + struct { + union { + __IO uint16_t WDOGVALUEL; + struct { + __IO uint8_t WDOGVALUELL; + __IO uint8_t WDOGVALUELH; + }; + }; + union { + __IO uint16_t WDOGVALUEH; + struct { + __IO uint8_t WDOGVALUEHL; + __IO uint8_t WDOGVALUEHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGCONTROL; + stc_swwdt_wdogcontrol_field_t WDOGCONTROL_f; + struct { + union { + __IO uint16_t WDOGCONTROLL; + struct { + __IO uint8_t WDOGCONTROLLL; + __IO uint8_t WDOGCONTROLLH; + }; + }; + union { + __IO uint16_t WDOGCONTROLH; + struct { + __IO uint8_t WDOGCONTROLHL; + __IO uint8_t WDOGCONTROLHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGINTCLR; + struct { + union { + __IO uint16_t WDOGINTCLRL; + struct { + __IO uint8_t WDOGINTCLRLL; + __IO uint8_t WDOGINTCLRLH; + }; + }; + union { + __IO uint16_t WDOGINTCLRH; + struct { + __IO uint8_t WDOGINTCLRHL; + __IO uint8_t WDOGINTCLRHH; + }; + }; + }; + }; + union { + __IO uint32_t WDOGRIS; + stc_swwdt_wdogris_field_t WDOGRIS_f; + struct { + union { + __IO uint16_t WDOGRISL; + struct { + __IO uint8_t WDOGRISLL; + __IO uint8_t WDOGRISLH; + }; + }; + union { + __IO uint16_t WDOGRISH; + struct { + __IO uint8_t WDOGRISHL; + __IO uint8_t WDOGRISHH; + }; + }; + }; + }; + __IO uint8_t RESERVED0[4]; + union { + __IO uint32_t WDOGSPMC; + stc_swwdt_wdogspmc_field_t WDOGSPMC_f; + struct { + union { + __IO uint16_t WDOGSPMCL; + struct { + __IO uint8_t WDOGSPMCLL; + __IO uint8_t WDOGSPMCLH; + }; + }; + union { + __IO uint16_t WDOGSPMCH; + struct { + __IO uint8_t WDOGSPMCHL; + __IO uint8_t WDOGSPMCHH; + }; + }; + }; + }; + __IO uint8_t RESERVED1[3044]; + union { + __IO uint32_t WDOGLOCK; + struct { + union { + __IO uint16_t WDOGLOCKL; + struct { + __IO uint8_t WDOGLOCKLL; + __IO uint8_t WDOGLOCKLH; + }; + }; + union { + __IO uint16_t WDOGLOCKH; + struct { + __IO uint8_t WDOGLOCKHL; + __IO uint8_t WDOGLOCKHH; + }; + }; + }; + }; +} FM_SWWDT_TypeDef, FM4_SWWDT_TypeDef; + +/******************************************************************************* +* UNIQUE_ID_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint32_t UIDR0; + stc_unique_id_uidr0_field_t UIDR0_f; + struct { + union { + __IO uint16_t UIDR0L; + struct { + __IO uint8_t UIDR0LL; + __IO uint8_t UIDR0LH; + }; + }; + union { + __IO uint16_t UIDR0H; + struct { + __IO uint8_t UIDR0HL; + __IO uint8_t UIDR0HH; + }; + }; + }; + }; + union { + __IO uint32_t UIDR1; + stc_unique_id_uidr1_field_t UIDR1_f; + struct { + union { + __IO uint16_t UIDR1L; + struct { + __IO uint8_t UIDR1LL; + __IO uint8_t UIDR1LH; + }; + }; + union { + __IO uint16_t UIDR1H; + struct { + __IO uint8_t UIDR1HL; + __IO uint8_t UIDR1HH; + }; + }; + }; + }; +} FM_UNIQUE_ID_TypeDef, FM4_UNIQUE_ID_TypeDef; + +/******************************************************************************* +* USB_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + __IO uint8_t RESERVED0[8448]; + union { + __IO uint16_t HCNT; + stc_usb_hcnt_field_t HCNT_f; + struct { + __IO uint8_t HCNTL; + __IO uint8_t HCNTH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint8_t HIRQ; + stc_usb_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usb_herr_field_t HERR_f; + }; + __IO uint8_t RESERVED2[2]; + union { + __IO uint8_t HSTATE; + stc_usb_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usb_hfcomp_field_t HFCOMP_f; + }; + __IO uint8_t RESERVED3[2]; + union { + __IO uint16_t HRTIMER; + stc_usb_hrtimer_field_t HRTIMER_f; + struct { + __IO uint8_t HRTIMERL; + __IO uint8_t HRTIMERH; + }; + }; + __IO uint8_t RESERVED4[2]; + union { + __IO uint8_t HRTIMER2; + stc_usb_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usb_hadr_field_t HADR_f; + }; + __IO uint8_t RESERVED5[2]; + union { + __IO uint16_t HEOF; + stc_usb_heof_field_t HEOF_f; + struct { + __IO uint8_t HEOFL; + __IO uint8_t HEOFH; + }; + }; + __IO uint8_t RESERVED6[2]; + union { + __IO uint16_t HFRAME; + stc_usb_hframe_field_t HFRAME_f; + struct { + __IO uint8_t HFRAMEL; + __IO uint8_t HFRAMEH; + }; + }; + __IO uint8_t RESERVED7[2]; + union { + __IO uint8_t HTOKEN; + stc_usb_htoken_field_t HTOKEN_f; + }; + __IO uint8_t RESERVED8[3]; + union { + __IO uint16_t UDCC; + stc_usb_udcc_field_t UDCC_f; + struct { + __IO uint8_t UDCCL; + __IO uint8_t UDCCH; + }; + }; + __IO uint8_t RESERVED9[2]; + union { + __IO uint16_t EP0C; + stc_usb_ep0c_field_t EP0C_f; + struct { + __IO uint8_t EP0CL; + __IO uint8_t EP0CH; + }; + }; + __IO uint8_t RESERVED10[2]; + union { + __IO uint16_t EP1C; + stc_usb_ep1c_field_t EP1C_f; + struct { + __IO uint8_t EP1CL; + __IO uint8_t EP1CH; + }; + }; + __IO uint8_t RESERVED11[2]; + union { + __IO uint16_t EP2C; + stc_usb_ep2c_field_t EP2C_f; + struct { + __IO uint8_t EP2CL; + __IO uint8_t EP2CH; + }; + }; + __IO uint8_t RESERVED12[2]; + union { + __IO uint16_t EP3C; + stc_usb_ep3c_field_t EP3C_f; + struct { + __IO uint8_t EP3CL; + __IO uint8_t EP3CH; + }; + }; + __IO uint8_t RESERVED13[2]; + union { + __IO uint16_t EP4C; + stc_usb_ep4c_field_t EP4C_f; + struct { + __IO uint8_t EP4CL; + __IO uint8_t EP4CH; + }; + }; + __IO uint8_t RESERVED14[2]; + union { + __IO uint16_t EP5C; + stc_usb_ep5c_field_t EP5C_f; + struct { + __IO uint8_t EP5CL; + __IO uint8_t EP5CH; + }; + }; + __IO uint8_t RESERVED15[2]; + union { + __IO uint16_t TMSP; + stc_usb_tmsp_field_t TMSP_f; + struct { + __IO uint8_t TMSPL; + __IO uint8_t TMSPH; + }; + }; + __IO uint8_t RESERVED16[2]; + union { + __IO uint8_t UDCS; + stc_usb_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usb_udcie_field_t UDCIE_f; + }; + __IO uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0IS; + stc_usb_ep0is_field_t EP0IS_f; + struct { + __IO uint8_t EP0ISL; + __IO uint8_t EP0ISH; + }; + }; + __IO uint8_t RESERVED18[2]; + union { + __IO uint16_t EP0OS; + stc_usb_ep0os_field_t EP0OS_f; + struct { + __IO uint8_t EP0OSL; + __IO uint8_t EP0OSH; + }; + }; + __IO uint8_t RESERVED19[2]; + union { + __IO uint16_t EP1S; + stc_usb_ep1s_field_t EP1S_f; + struct { + __IO uint8_t EP1SL; + __IO uint8_t EP1SH; + }; + }; + __IO uint8_t RESERVED20[2]; + union { + __IO uint16_t EP2S; + stc_usb_ep2s_field_t EP2S_f; + struct { + __IO uint8_t EP2SL; + __IO uint8_t EP2SH; + }; + }; + __IO uint8_t RESERVED21[2]; + union { + __IO uint16_t EP3S; + stc_usb_ep3s_field_t EP3S_f; + struct { + __IO uint8_t EP3SL; + __IO uint8_t EP3SH; + }; + }; + __IO uint8_t RESERVED22[2]; + union { + __IO uint16_t EP4S; + stc_usb_ep4s_field_t EP4S_f; + struct { + __IO uint8_t EP4SL; + __IO uint8_t EP4SH; + }; + }; + __IO uint8_t RESERVED23[2]; + union { + __IO uint16_t EP5S; + stc_usb_ep5s_field_t EP5S_f; + struct { + __IO uint8_t EP5SL; + __IO uint8_t EP5SH; + }; + }; + __IO uint8_t RESERVED24[2]; + union { + __IO uint16_t EP0DT; + stc_usb_ep0dt_field_t EP0DT_f; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + __IO uint8_t RESERVED25[2]; + union { + __IO uint16_t EP1DT; + stc_usb_ep1dt_field_t EP1DT_f; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + __IO uint8_t RESERVED26[2]; + union { + __IO uint16_t EP2DT; + stc_usb_ep2dt_field_t EP2DT_f; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + __IO uint8_t RESERVED27[2]; + union { + __IO uint16_t EP3DT; + stc_usb_ep3dt_field_t EP3DT_f; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + __IO uint8_t RESERVED28[2]; + union { + __IO uint16_t EP4DT; + stc_usb_ep4dt_field_t EP4DT_f; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + __IO uint8_t RESERVED29[2]; + union { + __IO uint16_t EP5DT; + stc_usb_ep5dt_field_t EP5DT_f; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +} FM_USB_TypeDef, FM4_USB_TypeDef; + +/******************************************************************************* +* USBCLK_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t UCCR; + stc_usbclk_uccr_field_t UCCR_f; + }; + __IO uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclk_upcr1_field_t UPCR1_f; + }; + __IO uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclk_upcr2_field_t UPCR2_f; + }; + __IO uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclk_upcr3_field_t UPCR3_f; + }; + __IO uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclk_upcr4_field_t UPCR4_f; + }; + __IO uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclk_up_str_field_t UP_STR_f; + }; + __IO uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclk_upint_enr_field_t UPINT_ENR_f; + }; + __IO uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclk_upint_clr_field_t UPINT_CLR_f; + }; + __IO uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclk_upint_str_field_t UPINT_STR_f; + }; + __IO uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbclk_upcr5_field_t UPCR5_f; + }; + __IO uint8_t RESERVED9[11]; + union { + __IO uint8_t USBEN0; + stc_usbclk_usben0_field_t USBEN0_f; + }; + __IO uint8_t RESERVED10[3]; + union { + __IO uint8_t USBEN1; + stc_usbclk_usben1_field_t USBEN1_f; + }; +} FM_USBCLK_TypeDef, FM4_USBCLK_TypeDef; + +/******************************************************************************* +* WC_MODULE +* register structur +*******************************************************************************/ +typedef struct +{ + union { + __IO uint8_t WCRD; + stc_wc_wcrd_field_t WCRD_f; + }; + union { + __IO uint8_t WCRL; + stc_wc_wcrl_field_t WCRL_f; + }; + union { + __IO uint8_t WCCR; + stc_wc_wccr_field_t WCCR_f; + }; + __IO uint8_t RESERVED0[13]; + union { + __IO uint16_t CLK_SEL; + stc_wc_clk_sel_field_t CLK_SEL_f; + struct { + __IO uint8_t CLK_SELL; + __IO uint8_t CLK_SELH; + }; + }; + __IO uint8_t RESERVED1[2]; + union { + __IO uint8_t CLK_EN; + stc_wc_clk_en_field_t CLK_EN_f; + }; +} FM_WC_TypeDef, FM4_WC_TypeDef; + +/******************************************************************************* +* Peripheral Memory Map +*******************************************************************************/ +#define FM_FLASH_BASE (0x00000000UL) /* Flash Base Address */ +#define FM4_FLASH_BASE (0x00000000UL) /* Flash Base Address */ +#define FM_PERIPH_BASE (0x40000000UL) /* Peripheral Base Address */ +#define FM4_PERIPH_BASE (0x40000000UL) /* Peripheral Base Address */ +#define FM_CM4_BASE (0xE0100000UL) /* CM4 Private */ +#define FM4_CM4_BASE (0xE0100000UL) /* CM4 Private */ + +#define FM_ADC0_BASE (0x40027000UL) /* ADC0 Base Address */ +#define FM4_ADC0_BASE (0x40027000UL) /* ADC0 Base Address */ +#define FM_ADC1_BASE (0x40027100UL) /* ADC1 Base Address */ +#define FM4_ADC1_BASE (0x40027100UL) /* ADC1 Base Address */ +#define FM_ADC2_BASE (0x40027200UL) /* ADC2 Base Address */ +#define FM4_ADC2_BASE (0x40027200UL) /* ADC2 Base Address */ +#define FM_BT0_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_PPG_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_PPG_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_PWC_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_PWC_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_PWM_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_PWM_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT0_RT_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM4_BT0_RT_BASE (0x40025000UL) /* BT0 Base Address */ +#define FM_BT1_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_PPG_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_PPG_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_PWC_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_PWC_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_PWM_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_PWM_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT1_RT_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM4_BT1_RT_BASE (0x40025040UL) /* BT1 Base Address */ +#define FM_BT10_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_PPG_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_PPG_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_PWC_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_PWC_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_PWM_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_PWM_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT10_RT_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM4_BT10_RT_BASE (0x40025480UL) /* BT10 Base Address */ +#define FM_BT11_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_PPG_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_PPG_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_PWC_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_PWC_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_PWM_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_PWM_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT11_RT_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM4_BT11_RT_BASE (0x400254C0UL) /* BT11 Base Address */ +#define FM_BT12_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_PPG_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_PPG_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_PWC_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_PWC_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_PWM_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_PWM_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT12_RT_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM4_BT12_RT_BASE (0x40025600UL) /* BT12 Base Address */ +#define FM_BT13_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_PPG_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_PPG_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_PWC_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_PWC_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_PWM_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_PWM_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT13_RT_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM4_BT13_RT_BASE (0x40025640UL) /* BT13 Base Address */ +#define FM_BT14_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_PPG_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_PPG_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_PWC_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_PWC_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_PWM_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_PWM_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT14_RT_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM4_BT14_RT_BASE (0x40025680UL) /* BT14 Base Address */ +#define FM_BT15_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_PPG_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_PPG_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_PWC_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_PWC_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_PWM_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_PWM_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT15_RT_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM4_BT15_RT_BASE (0x400256C0UL) /* BT15 Base Address */ +#define FM_BT2_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_PPG_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_PPG_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_PWC_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_PWC_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_PWM_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_PWM_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT2_RT_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM4_BT2_RT_BASE (0x40025080UL) /* BT2 Base Address */ +#define FM_BT3_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_PPG_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_PPG_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_PWC_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_PWC_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_PWM_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_PWM_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT3_RT_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM4_BT3_RT_BASE (0x400250C0UL) /* BT3 Base Address */ +#define FM_BT4_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_PPG_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_PPG_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_PWC_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_PWC_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_PWM_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_PWM_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT4_RT_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM4_BT4_RT_BASE (0x40025200UL) /* BT4 Base Address */ +#define FM_BT5_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_PPG_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_PPG_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_PWC_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_PWC_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_PWM_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_PWM_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT5_RT_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM4_BT5_RT_BASE (0x40025240UL) /* BT5 Base Address */ +#define FM_BT6_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_PPG_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_PPG_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_PWC_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_PWC_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_PWM_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_PWM_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT6_RT_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM4_BT6_RT_BASE (0x40025280UL) /* BT6 Base Address */ +#define FM_BT7_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_PPG_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_PPG_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_PWC_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_PWC_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_PWM_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_PWM_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT7_RT_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM4_BT7_RT_BASE (0x400252C0UL) /* BT7 Base Address */ +#define FM_BT8_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_PPG_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_PPG_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_PWC_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_PWC_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_PWM_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_PWM_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT8_RT_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM4_BT8_RT_BASE (0x40025400UL) /* BT8 Base Address */ +#define FM_BT9_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_PPG_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_PPG_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_PWC_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_PWC_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_PWM_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_PWM_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BT9_RT_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM4_BT9_RT_BASE (0x40025440UL) /* BT9 Base Address */ +#define FM_BTIOSEL03_BASE (0x40025100UL) /* BTIOSEL03 Base Address */ +#define FM4_BTIOSEL03_BASE (0x40025100UL) /* BTIOSEL03 Base Address */ +#define FM_BTIOSEL47_BASE (0x40025300UL) /* BTIOSEL47 Base Address */ +#define FM4_BTIOSEL47_BASE (0x40025300UL) /* BTIOSEL47 Base Address */ +#define FM_BTIOSEL8B_BASE (0x40025500UL) /* BTIOSEL8B Base Address */ +#define FM4_BTIOSEL8B_BASE (0x40025500UL) /* BTIOSEL8B Base Address */ +#define FM_BTIOSELCF_BASE (0x40025700UL) /* BTIOSELCF Base Address */ +#define FM4_BTIOSELCF_BASE (0x40025700UL) /* BTIOSELCF Base Address */ +#define FM_CAN0_BASE (0x40062000UL) /* CAN0 Base Address */ +#define FM4_CAN0_BASE (0x40062000UL) /* CAN0 Base Address */ +#define FM_CAN1_BASE (0x40063000UL) /* CAN1 Base Address */ +#define FM4_CAN1_BASE (0x40063000UL) /* CAN1 Base Address */ +#define FM_CANFD0_BASE (0x40070000UL) /* CANFD0 Base Address */ +#define FM4_CANFD0_BASE (0x40070000UL) /* CANFD0 Base Address */ +#define FM_CANPRES_BASE (0x40037000UL) /* CANPRES Base Address */ +#define FM4_CANPRES_BASE (0x40037000UL) /* CANPRES Base Address */ +#define FM_CLK_GATING_BASE (0x4003C100UL) /* CLK_GATING Base Address */ +#define FM4_CLK_GATING_BASE (0x4003C100UL) /* CLK_GATING Base Address */ +#define FM_CRC_BASE (0x40039000UL) /* CRC Base Address */ +#define FM4_CRC_BASE (0x40039000UL) /* CRC Base Address */ +#define FM_CRG_BASE (0x40010000UL) /* CRG Base Address */ +#define FM4_CRG_BASE (0x40010000UL) /* CRG Base Address */ +#define FM_CRTRIM_BASE (0x4002E000UL) /* CRTRIM Base Address */ +#define FM4_CRTRIM_BASE (0x4002E000UL) /* CRTRIM Base Address */ +#define FM_DAC0_BASE (0x40033000UL) /* DAC0 Base Address */ +#define FM4_DAC0_BASE (0x40033000UL) /* DAC0 Base Address */ +#define FM_DAC1_BASE (0x40033008UL) /* DAC1 Base Address */ +#define FM4_DAC1_BASE (0x40033008UL) /* DAC1 Base Address */ +#define FM_DMAC_BASE (0x40060000UL) /* DMAC Base Address */ +#define FM4_DMAC_BASE (0x40060000UL) /* DMAC Base Address */ +#define FM_DS_BASE (0x40035100UL) /* DS Base Address */ +#define FM4_DS_BASE (0x40035100UL) /* DS Base Address */ +#define FM_DSTC_BASE (0x40061000UL) /* DSTC Base Address */ +#define FM4_DSTC_BASE (0x40061000UL) /* DSTC Base Address */ +#define FM_DT_BASE (0x40015000UL) /* DT Base Address */ +#define FM4_DT_BASE (0x40015000UL) /* DT Base Address */ +#define FM_DUALFLASH_IF_BASE (0x40000400UL) /* DUALFLASH_IF Base Address */ +#define FM4_DUALFLASH_IF_BASE (0x40000400UL) /* DUALFLASH_IF Base Address */ +#define FM_ECC_CAPTURE_BASE (0x40000300UL) /* ECC_CAPTURE Base Address */ +#define FM4_ECC_CAPTURE_BASE (0x40000300UL) /* ECC_CAPTURE Base Address */ +#define FM_EXBUS_BASE (0x4003F000UL) /* EXBUS Base Address */ +#define FM4_EXBUS_BASE (0x4003F000UL) /* EXBUS Base Address */ +#define FM_EXTI_BASE (0x40030000UL) /* EXTI Base Address */ +#define FM4_EXTI_BASE (0x40030000UL) /* EXTI Base Address */ +#define FM_FLASH_IF_BASE (0x40000000UL) /* FLASH_IF Base Address */ +#define FM4_FLASH_IF_BASE (0x40000000UL) /* FLASH_IF Base Address */ +#define FM_GPIO_BASE (0x4006F000UL) /* GPIO Base Address */ +#define FM4_GPIO_BASE (0x4006F000UL) /* GPIO Base Address */ +#define FM_HSSPI_BASE (0xD0000000UL) /* HSSPI Base Address */ +#define FM4_HSSPI_BASE (0xD0000000UL) /* HSSPI Base Address */ +#define FM_HWWDT_BASE (0x40011000UL) /* HWWDT Base Address */ +#define FM4_HWWDT_BASE (0x40011000UL) /* HWWDT Base Address */ +#define FM_I2S0_BASE (0x4006C000UL) /* I2S0 Base Address */ +#define FM4_I2S0_BASE (0x4006C000UL) /* I2S0 Base Address */ +#define FM_I2SPRE_BASE (0x4003D000UL) /* I2SPRE Base Address */ +#define FM4_I2SPRE_BASE (0x4003D000UL) /* I2SPRE Base Address */ +#define FM_INTREQ_BASE (0x40031000UL) /* INTREQ Base Address */ +#define FM4_INTREQ_BASE (0x40031000UL) /* INTREQ Base Address */ +#define FM_LSCRP_BASE (0x4003C000UL) /* LSCRP Base Address */ +#define FM4_LSCRP_BASE (0x4003C000UL) /* LSCRP Base Address */ +#define FM_LVD_BASE (0x40035000UL) /* LVD Base Address */ +#define FM4_LVD_BASE (0x40035000UL) /* LVD Base Address */ +#define FM_MFS0_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_CSIO_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_CSIO_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_I2C_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_I2C_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_LIN_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_LIN_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS0_UART_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM4_MFS0_UART_BASE (0x40038000UL) /* MFS0 Base Address */ +#define FM_MFS1_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_CSIO_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_CSIO_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_I2C_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_I2C_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_LIN_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_LIN_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS1_UART_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM4_MFS1_UART_BASE (0x40038100UL) /* MFS1 Base Address */ +#define FM_MFS10_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_CSIO_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_CSIO_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_I2C_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_I2C_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_LIN_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_LIN_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS10_UART_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM4_MFS10_UART_BASE (0x40038A00UL) /* MFS10 Base Address */ +#define FM_MFS11_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_CSIO_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_CSIO_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_I2C_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_I2C_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_LIN_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_LIN_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS11_UART_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM4_MFS11_UART_BASE (0x40038B00UL) /* MFS11 Base Address */ +#define FM_MFS12_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_CSIO_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_CSIO_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_I2C_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_I2C_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_LIN_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_LIN_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS12_UART_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM4_MFS12_UART_BASE (0x40038C00UL) /* MFS12 Base Address */ +#define FM_MFS13_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_CSIO_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_CSIO_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_I2C_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_I2C_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_LIN_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_LIN_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS13_UART_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM4_MFS13_UART_BASE (0x40038D00UL) /* MFS13 Base Address */ +#define FM_MFS14_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_CSIO_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_CSIO_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_I2C_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_I2C_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_LIN_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_LIN_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS14_UART_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM4_MFS14_UART_BASE (0x40038E00UL) /* MFS14 Base Address */ +#define FM_MFS15_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_CSIO_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_CSIO_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_I2C_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_I2C_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_LIN_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_LIN_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS15_UART_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM4_MFS15_UART_BASE (0x40038F00UL) /* MFS15 Base Address */ +#define FM_MFS2_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_CSIO_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_CSIO_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_I2C_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_I2C_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_LIN_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_LIN_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS2_UART_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM4_MFS2_UART_BASE (0x40038200UL) /* MFS2 Base Address */ +#define FM_MFS3_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_CSIO_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_CSIO_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_I2C_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_I2C_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_LIN_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_LIN_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS3_UART_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM4_MFS3_UART_BASE (0x40038300UL) /* MFS3 Base Address */ +#define FM_MFS4_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_CSIO_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_CSIO_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_I2C_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_I2C_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_LIN_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_LIN_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS4_UART_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM4_MFS4_UART_BASE (0x40038400UL) /* MFS4 Base Address */ +#define FM_MFS5_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_CSIO_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_CSIO_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_I2C_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_I2C_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_LIN_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_LIN_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS5_UART_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM4_MFS5_UART_BASE (0x40038500UL) /* MFS5 Base Address */ +#define FM_MFS6_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_CSIO_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_CSIO_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_I2C_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_I2C_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_LIN_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_LIN_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS6_UART_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM4_MFS6_UART_BASE (0x40038600UL) /* MFS6 Base Address */ +#define FM_MFS7_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_CSIO_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_CSIO_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_I2C_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_I2C_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_LIN_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_LIN_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS7_UART_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM4_MFS7_UART_BASE (0x40038700UL) /* MFS7 Base Address */ +#define FM_MFS8_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_CSIO_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_CSIO_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_I2C_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_I2C_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_LIN_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_LIN_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS8_UART_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM4_MFS8_UART_BASE (0x40038800UL) /* MFS8 Base Address */ +#define FM_MFS9_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_CSIO_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_CSIO_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_I2C_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_I2C_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_LIN_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_LIN_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFS9_UART_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM4_MFS9_UART_BASE (0x40038900UL) /* MFS9 Base Address */ +#define FM_MFT_PPG_BASE (0x40024000UL) /* MFT_PPG Base Address */ +#define FM4_MFT_PPG_BASE (0x40024000UL) /* MFT_PPG Base Address */ +#define FM_MFT0_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_ADCMP_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_ADCMP_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_FRT_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_FRT_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_ICU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_ICU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_OCU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_OCU_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT0_WFG_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM4_MFT0_WFG_BASE (0x40020000UL) /* MFT0 Base Address */ +#define FM_MFT1_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_ADCMP_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_ADCMP_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_FRT_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_FRT_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_ICU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_ICU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_OCU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_OCU_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT1_WFG_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM4_MFT1_WFG_BASE (0x40021000UL) /* MFT1 Base Address */ +#define FM_MFT2_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_ADCMP_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_ADCMP_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_FRT_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_FRT_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_ICU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_ICU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_OCU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_OCU_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_MFT2_WFG_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM4_MFT2_WFG_BASE (0x40022000UL) /* MFT2 Base Address */ +#define FM_PCRC_BASE (0x40080000UL) /* PCRC Base Address */ +#define FM4_PCRC_BASE (0x40080000UL) /* PCRC Base Address */ +#define FM_QPRC0_BASE (0x40026000UL) /* QPRC0 Base Address */ +#define FM4_QPRC0_BASE (0x40026000UL) /* QPRC0 Base Address */ +#define FM_QPRC0_NF_BASE (0x40026100UL) /* QPRC0_NF Base Address */ +#define FM4_QPRC0_NF_BASE (0x40026100UL) /* QPRC0_NF Base Address */ +#define FM_QPRC1_BASE (0x40026040UL) /* QPRC1 Base Address */ +#define FM4_QPRC1_BASE (0x40026040UL) /* QPRC1 Base Address */ +#define FM_QPRC1_NF_BASE (0x40026110UL) /* QPRC1_NF Base Address */ +#define FM4_QPRC1_NF_BASE (0x40026110UL) /* QPRC1_NF Base Address */ +#define FM_QPRC2_BASE (0x40026080UL) /* QPRC2 Base Address */ +#define FM4_QPRC2_BASE (0x40026080UL) /* QPRC2 Base Address */ +#define FM_QPRC2_NF_BASE (0x40026120UL) /* QPRC2_NF Base Address */ +#define FM4_QPRC2_NF_BASE (0x40026120UL) /* QPRC2_NF Base Address */ +#define FM_QPRC3_BASE (0x400260C0UL) /* QPRC3 Base Address */ +#define FM4_QPRC3_BASE (0x400260C0UL) /* QPRC3 Base Address */ +#define FM_QPRC3_NF_BASE (0x40026130UL) /* QPRC3_NF Base Address */ +#define FM4_QPRC3_NF_BASE (0x40026130UL) /* QPRC3_NF Base Address */ +#define FM_RTC_BASE (0x4003B100UL) /* RTC Base Address */ +#define FM4_RTC_BASE (0x4003B100UL) /* RTC Base Address */ +#define FM_SBSSR_BASE (0x40025F00UL) /* SBSSR Base Address */ +#define FM4_SBSSR_BASE (0x40025F00UL) /* SBSSR Base Address */ +#define FM_SDIF_BASE (0x4006E000UL) /* SDIF Base Address */ +#define FM4_SDIF_BASE (0x4006E000UL) /* SDIF Base Address */ +#define FM_SWWDT_BASE (0x40012000UL) /* SWWDT Base Address */ +#define FM4_SWWDT_BASE (0x40012000UL) /* SWWDT Base Address */ +#define FM_UNIQUE_ID_BASE (0x40000200UL) /* UNIQUE_ID Base Address */ +#define FM4_UNIQUE_ID_BASE (0x40000200UL) /* UNIQUE_ID Base Address */ +#define FM_USB0_BASE (0x40040000UL) /* USB0 Base Address */ +#define FM4_USB0_BASE (0x40040000UL) /* USB0 Base Address */ +#define FM_USB1_BASE (0x40052100UL) /* USB1 Base Address */ +#define FM4_USB1_BASE (0x40052100UL) /* USB1 Base Address */ +#define FM_USBCLK_BASE (0x40036000UL) /* USBCLK Base Address */ +#define FM4_USBCLK_BASE (0x40036000UL) /* USBCLK Base Address */ +#define FM_WC_BASE (0x4003A000UL) /* WC Base Address */ +#define FM4_WC_BASE (0x4003A000UL) /* WC Base Address */ +/******************************************************************************* +* Peripheral declaration +*******************************************************************************/ +#define FM4_ADC0 ((FM_ADC_TypeDef *)FM4_ADC0_BASE) +#define FM_ADC0 ((FM_ADC_TypeDef *)FM4_ADC0_BASE) +#define FM4_ADC1 ((FM_ADC_TypeDef *)FM4_ADC1_BASE) +#define FM_ADC1 ((FM_ADC_TypeDef *)FM4_ADC1_BASE) +#define FM4_ADC2 ((FM_ADC_TypeDef *)FM4_ADC2_BASE) +#define FM_ADC2 ((FM_ADC_TypeDef *)FM4_ADC2_BASE) +#define FM4_BT0 ((FM_BT_TypeDef *)FM4_BT0_BASE) +#define FM_BT0 ((FM_BT_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_PPG ((FM_BT_PPG_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_PPG ((FM_BT_PPG_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_PWC ((FM_BT_PWC_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_PWC ((FM_BT_PWC_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_PWM ((FM_BT_PWM_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_PWM ((FM_BT_PWM_TypeDef *)FM4_BT0_BASE) +#define FM4_BT0_RT ((FM_BT_RT_TypeDef *)FM4_BT0_BASE) +#define FM_BT0_RT ((FM_BT_RT_TypeDef *)FM4_BT0_BASE) +#define FM4_BT1 ((FM_BT_TypeDef *)FM4_BT1_BASE) +#define FM_BT1 ((FM_BT_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_PPG ((FM_BT_PPG_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_PPG ((FM_BT_PPG_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_PWC ((FM_BT_PWC_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_PWC ((FM_BT_PWC_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_PWM ((FM_BT_PWM_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_PWM ((FM_BT_PWM_TypeDef *)FM4_BT1_BASE) +#define FM4_BT1_RT ((FM_BT_RT_TypeDef *)FM4_BT1_BASE) +#define FM_BT1_RT ((FM_BT_RT_TypeDef *)FM4_BT1_BASE) +#define FM4_BT10 ((FM_BT_TypeDef *)FM4_BT10_BASE) +#define FM_BT10 ((FM_BT_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_PPG ((FM_BT_PPG_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_PPG ((FM_BT_PPG_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_PWC ((FM_BT_PWC_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_PWC ((FM_BT_PWC_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_PWM ((FM_BT_PWM_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_PWM ((FM_BT_PWM_TypeDef *)FM4_BT10_BASE) +#define FM4_BT10_RT ((FM_BT_RT_TypeDef *)FM4_BT10_BASE) +#define FM_BT10_RT ((FM_BT_RT_TypeDef *)FM4_BT10_BASE) +#define FM4_BT11 ((FM_BT_TypeDef *)FM4_BT11_BASE) +#define FM_BT11 ((FM_BT_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_PPG ((FM_BT_PPG_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_PPG ((FM_BT_PPG_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_PWC ((FM_BT_PWC_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_PWC ((FM_BT_PWC_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_PWM ((FM_BT_PWM_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_PWM ((FM_BT_PWM_TypeDef *)FM4_BT11_BASE) +#define FM4_BT11_RT ((FM_BT_RT_TypeDef *)FM4_BT11_BASE) +#define FM_BT11_RT ((FM_BT_RT_TypeDef *)FM4_BT11_BASE) +#define FM4_BT12 ((FM_BT_TypeDef *)FM4_BT12_BASE) +#define FM_BT12 ((FM_BT_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_PPG ((FM_BT_PPG_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_PPG ((FM_BT_PPG_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_PWC ((FM_BT_PWC_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_PWC ((FM_BT_PWC_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_PWM ((FM_BT_PWM_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_PWM ((FM_BT_PWM_TypeDef *)FM4_BT12_BASE) +#define FM4_BT12_RT ((FM_BT_RT_TypeDef *)FM4_BT12_BASE) +#define FM_BT12_RT ((FM_BT_RT_TypeDef *)FM4_BT12_BASE) +#define FM4_BT13 ((FM_BT_TypeDef *)FM4_BT13_BASE) +#define FM_BT13 ((FM_BT_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_PPG ((FM_BT_PPG_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_PPG ((FM_BT_PPG_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_PWC ((FM_BT_PWC_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_PWC ((FM_BT_PWC_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_PWM ((FM_BT_PWM_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_PWM ((FM_BT_PWM_TypeDef *)FM4_BT13_BASE) +#define FM4_BT13_RT ((FM_BT_RT_TypeDef *)FM4_BT13_BASE) +#define FM_BT13_RT ((FM_BT_RT_TypeDef *)FM4_BT13_BASE) +#define FM4_BT14 ((FM_BT_TypeDef *)FM4_BT14_BASE) +#define FM_BT14 ((FM_BT_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_PPG ((FM_BT_PPG_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_PPG ((FM_BT_PPG_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_PWC ((FM_BT_PWC_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_PWC ((FM_BT_PWC_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_PWM ((FM_BT_PWM_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_PWM ((FM_BT_PWM_TypeDef *)FM4_BT14_BASE) +#define FM4_BT14_RT ((FM_BT_RT_TypeDef *)FM4_BT14_BASE) +#define FM_BT14_RT ((FM_BT_RT_TypeDef *)FM4_BT14_BASE) +#define FM4_BT15 ((FM_BT_TypeDef *)FM4_BT15_BASE) +#define FM_BT15 ((FM_BT_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_PPG ((FM_BT_PPG_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_PPG ((FM_BT_PPG_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_PWC ((FM_BT_PWC_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_PWC ((FM_BT_PWC_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_PWM ((FM_BT_PWM_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_PWM ((FM_BT_PWM_TypeDef *)FM4_BT15_BASE) +#define FM4_BT15_RT ((FM_BT_RT_TypeDef *)FM4_BT15_BASE) +#define FM_BT15_RT ((FM_BT_RT_TypeDef *)FM4_BT15_BASE) +#define FM4_BT2 ((FM_BT_TypeDef *)FM4_BT2_BASE) +#define FM_BT2 ((FM_BT_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_PPG ((FM_BT_PPG_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_PPG ((FM_BT_PPG_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_PWC ((FM_BT_PWC_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_PWC ((FM_BT_PWC_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_PWM ((FM_BT_PWM_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_PWM ((FM_BT_PWM_TypeDef *)FM4_BT2_BASE) +#define FM4_BT2_RT ((FM_BT_RT_TypeDef *)FM4_BT2_BASE) +#define FM_BT2_RT ((FM_BT_RT_TypeDef *)FM4_BT2_BASE) +#define FM4_BT3 ((FM_BT_TypeDef *)FM4_BT3_BASE) +#define FM_BT3 ((FM_BT_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_PPG ((FM_BT_PPG_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_PPG ((FM_BT_PPG_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_PWC ((FM_BT_PWC_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_PWC ((FM_BT_PWC_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_PWM ((FM_BT_PWM_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_PWM ((FM_BT_PWM_TypeDef *)FM4_BT3_BASE) +#define FM4_BT3_RT ((FM_BT_RT_TypeDef *)FM4_BT3_BASE) +#define FM_BT3_RT ((FM_BT_RT_TypeDef *)FM4_BT3_BASE) +#define FM4_BT4 ((FM_BT_TypeDef *)FM4_BT4_BASE) +#define FM_BT4 ((FM_BT_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_PPG ((FM_BT_PPG_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_PPG ((FM_BT_PPG_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_PWC ((FM_BT_PWC_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_PWC ((FM_BT_PWC_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_PWM ((FM_BT_PWM_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_PWM ((FM_BT_PWM_TypeDef *)FM4_BT4_BASE) +#define FM4_BT4_RT ((FM_BT_RT_TypeDef *)FM4_BT4_BASE) +#define FM_BT4_RT ((FM_BT_RT_TypeDef *)FM4_BT4_BASE) +#define FM4_BT5 ((FM_BT_TypeDef *)FM4_BT5_BASE) +#define FM_BT5 ((FM_BT_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_PPG ((FM_BT_PPG_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_PPG ((FM_BT_PPG_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_PWC ((FM_BT_PWC_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_PWC ((FM_BT_PWC_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_PWM ((FM_BT_PWM_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_PWM ((FM_BT_PWM_TypeDef *)FM4_BT5_BASE) +#define FM4_BT5_RT ((FM_BT_RT_TypeDef *)FM4_BT5_BASE) +#define FM_BT5_RT ((FM_BT_RT_TypeDef *)FM4_BT5_BASE) +#define FM4_BT6 ((FM_BT_TypeDef *)FM4_BT6_BASE) +#define FM_BT6 ((FM_BT_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_PPG ((FM_BT_PPG_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_PPG ((FM_BT_PPG_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_PWC ((FM_BT_PWC_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_PWC ((FM_BT_PWC_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_PWM ((FM_BT_PWM_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_PWM ((FM_BT_PWM_TypeDef *)FM4_BT6_BASE) +#define FM4_BT6_RT ((FM_BT_RT_TypeDef *)FM4_BT6_BASE) +#define FM_BT6_RT ((FM_BT_RT_TypeDef *)FM4_BT6_BASE) +#define FM4_BT7 ((FM_BT_TypeDef *)FM4_BT7_BASE) +#define FM_BT7 ((FM_BT_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_PPG ((FM_BT_PPG_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_PPG ((FM_BT_PPG_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_PWC ((FM_BT_PWC_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_PWC ((FM_BT_PWC_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_PWM ((FM_BT_PWM_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_PWM ((FM_BT_PWM_TypeDef *)FM4_BT7_BASE) +#define FM4_BT7_RT ((FM_BT_RT_TypeDef *)FM4_BT7_BASE) +#define FM_BT7_RT ((FM_BT_RT_TypeDef *)FM4_BT7_BASE) +#define FM4_BT8 ((FM_BT_TypeDef *)FM4_BT8_BASE) +#define FM_BT8 ((FM_BT_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_PPG ((FM_BT_PPG_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_PPG ((FM_BT_PPG_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_PWC ((FM_BT_PWC_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_PWC ((FM_BT_PWC_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_PWM ((FM_BT_PWM_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_PWM ((FM_BT_PWM_TypeDef *)FM4_BT8_BASE) +#define FM4_BT8_RT ((FM_BT_RT_TypeDef *)FM4_BT8_BASE) +#define FM_BT8_RT ((FM_BT_RT_TypeDef *)FM4_BT8_BASE) +#define FM4_BT9 ((FM_BT_TypeDef *)FM4_BT9_BASE) +#define FM_BT9 ((FM_BT_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_PPG ((FM_BT_PPG_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_PPG ((FM_BT_PPG_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_PWC ((FM_BT_PWC_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_PWC ((FM_BT_PWC_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_PWM ((FM_BT_PWM_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_PWM ((FM_BT_PWM_TypeDef *)FM4_BT9_BASE) +#define FM4_BT9_RT ((FM_BT_RT_TypeDef *)FM4_BT9_BASE) +#define FM_BT9_RT ((FM_BT_RT_TypeDef *)FM4_BT9_BASE) +#define FM4_BTIOSEL03 ((FM_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE) +#define FM_BTIOSEL03 ((FM_BTIOSEL03_TypeDef *)FM4_BTIOSEL03_BASE) +#define FM4_BTIOSEL47 ((FM_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE) +#define FM_BTIOSEL47 ((FM_BTIOSEL47_TypeDef *)FM4_BTIOSEL47_BASE) +#define FM4_BTIOSEL8B ((FM_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE) +#define FM_BTIOSEL8B ((FM_BTIOSEL8B_TypeDef *)FM4_BTIOSEL8B_BASE) +#define FM4_BTIOSELCF ((FM_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE) +#define FM_BTIOSELCF ((FM_BTIOSELCF_TypeDef *)FM4_BTIOSELCF_BASE) +#define FM4_CAN0 ((FM_CAN_TypeDef *)FM4_CAN0_BASE) +#define FM_CAN0 ((FM_CAN_TypeDef *)FM4_CAN0_BASE) +#define FM4_CAN1 ((FM_CAN_TypeDef *)FM4_CAN1_BASE) +#define FM_CAN1 ((FM_CAN_TypeDef *)FM4_CAN1_BASE) +#define FM4_CANFD0 ((FM_CANFD_TypeDef *)FM4_CANFD0_BASE) +#define FM_CANFD0 ((FM_CANFD_TypeDef *)FM4_CANFD0_BASE) +#define FM4_CANPRES ((FM_CANPRES_TypeDef *)FM4_CANPRES_BASE) +#define FM_CANPRES ((FM_CANPRES_TypeDef *)FM4_CANPRES_BASE) +#define FM4_CLK_GATING ((FM_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE) +#define FM_CLK_GATING ((FM_CLK_GATING_TypeDef *)FM4_CLK_GATING_BASE) +#define FM4_CRC ((FM_CRC_TypeDef *)FM4_CRC_BASE) +#define FM_CRC ((FM_CRC_TypeDef *)FM4_CRC_BASE) +#define FM4_CRG ((FM_CRG_TypeDef *)FM4_CRG_BASE) +#define FM_CRG ((FM_CRG_TypeDef *)FM4_CRG_BASE) +#define FM4_CRTRIM ((FM_CRTRIM_TypeDef *)FM4_CRTRIM_BASE) +#define FM_CRTRIM ((FM_CRTRIM_TypeDef *)FM4_CRTRIM_BASE) +#define FM4_DAC0 ((FM_DAC_TypeDef *)FM4_DAC0_BASE) +#define FM_DAC0 ((FM_DAC_TypeDef *)FM4_DAC0_BASE) +#define FM4_DAC1 ((FM_DAC_TypeDef *)FM4_DAC1_BASE) +#define FM_DAC1 ((FM_DAC_TypeDef *)FM4_DAC1_BASE) +#define FM4_DMAC ((FM_DMAC_TypeDef *)FM4_DMAC_BASE) +#define FM_DMAC ((FM_DMAC_TypeDef *)FM4_DMAC_BASE) +#define FM4_DS ((FM_DS_TypeDef *)FM4_DS_BASE) +#define FM_DS ((FM_DS_TypeDef *)FM4_DS_BASE) +#define FM4_DSTC ((FM_DSTC_TypeDef *)FM4_DSTC_BASE) +#define FM_DSTC ((FM_DSTC_TypeDef *)FM4_DSTC_BASE) +#define FM4_DT ((FM_DT_TypeDef *)FM4_DT_BASE) +#define FM_DT ((FM_DT_TypeDef *)FM4_DT_BASE) +#define FM4_DUALFLASH_IF ((FM_DUALFLASH_IF_TypeDef *)FM4_DUALFLASH_IF_BASE) +#define FM_DUALFLASH_IF ((FM_DUALFLASH_IF_TypeDef *)FM4_DUALFLASH_IF_BASE) +#define FM4_ECC_CAPTURE ((FM_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE) +#define FM_ECC_CAPTURE ((FM_ECC_CAPTURE_TypeDef *)FM4_ECC_CAPTURE_BASE) +#define FM4_EXBUS ((FM_EXBUS_TypeDef *)FM4_EXBUS_BASE) +#define FM_EXBUS ((FM_EXBUS_TypeDef *)FM4_EXBUS_BASE) +#define FM4_EXTI ((FM_EXTI_TypeDef *)FM4_EXTI_BASE) +#define FM_EXTI ((FM_EXTI_TypeDef *)FM4_EXTI_BASE) +#define FM4_FLASH_IF ((FM_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE) +#define FM_FLASH_IF ((FM_FLASH_IF_TypeDef *)FM4_FLASH_IF_BASE) +#define FM4_GPIO ((FM_GPIO_TypeDef *)FM4_GPIO_BASE) +#define FM_GPIO ((FM_GPIO_TypeDef *)FM4_GPIO_BASE) +#define FM4_HSSPI ((FM_HSSPI_TypeDef *)FM4_HSSPI_BASE) +#define FM_HSSPI ((FM_HSSPI_TypeDef *)FM4_HSSPI_BASE) +#define FM4_HWWDT ((FM_HWWDT_TypeDef *)FM4_HWWDT_BASE) +#define FM_HWWDT ((FM_HWWDT_TypeDef *)FM4_HWWDT_BASE) +#define FM4_I2S0 ((FM_I2S_TypeDef *)FM4_I2S0_BASE) +#define FM_I2S0 ((FM_I2S_TypeDef *)FM4_I2S0_BASE) +#define FM4_I2SPRE ((FM_I2SPRE_TypeDef *)FM4_I2SPRE_BASE) +#define FM_I2SPRE ((FM_I2SPRE_TypeDef *)FM4_I2SPRE_BASE) +#define FM4_INTREQ ((FM_INTREQ_TypeDef *)FM4_INTREQ_BASE) +#define FM_INTREQ ((FM_INTREQ_TypeDef *)FM4_INTREQ_BASE) +#define FM4_LSCRP ((FM_LSCRP_TypeDef *)FM4_LSCRP_BASE) +#define FM_LSCRP ((FM_LSCRP_TypeDef *)FM4_LSCRP_BASE) +#define FM4_LVD ((FM_LVD_TypeDef *)FM4_LVD_BASE) +#define FM_LVD ((FM_LVD_TypeDef *)FM4_LVD_BASE) +#define FM4_MFS0 ((FM_MFS_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0 ((FM_MFS_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS0_UART ((FM_MFS_UART_TypeDef *)FM4_MFS0_BASE) +#define FM_MFS0_UART ((FM_MFS_UART_TypeDef *)FM4_MFS0_BASE) +#define FM4_MFS1 ((FM_MFS_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1 ((FM_MFS_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS1_UART ((FM_MFS_UART_TypeDef *)FM4_MFS1_BASE) +#define FM_MFS1_UART ((FM_MFS_UART_TypeDef *)FM4_MFS1_BASE) +#define FM4_MFS10 ((FM_MFS_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10 ((FM_MFS_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS10_UART ((FM_MFS_UART_TypeDef *)FM4_MFS10_BASE) +#define FM_MFS10_UART ((FM_MFS_UART_TypeDef *)FM4_MFS10_BASE) +#define FM4_MFS11 ((FM_MFS_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11 ((FM_MFS_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS11_UART ((FM_MFS_UART_TypeDef *)FM4_MFS11_BASE) +#define FM_MFS11_UART ((FM_MFS_UART_TypeDef *)FM4_MFS11_BASE) +#define FM4_MFS12 ((FM_MFS_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12 ((FM_MFS_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS12_UART ((FM_MFS_UART_TypeDef *)FM4_MFS12_BASE) +#define FM_MFS12_UART ((FM_MFS_UART_TypeDef *)FM4_MFS12_BASE) +#define FM4_MFS13 ((FM_MFS_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13 ((FM_MFS_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS13_UART ((FM_MFS_UART_TypeDef *)FM4_MFS13_BASE) +#define FM_MFS13_UART ((FM_MFS_UART_TypeDef *)FM4_MFS13_BASE) +#define FM4_MFS14 ((FM_MFS_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14 ((FM_MFS_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS14_UART ((FM_MFS_UART_TypeDef *)FM4_MFS14_BASE) +#define FM_MFS14_UART ((FM_MFS_UART_TypeDef *)FM4_MFS14_BASE) +#define FM4_MFS15 ((FM_MFS_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15 ((FM_MFS_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS15_UART ((FM_MFS_UART_TypeDef *)FM4_MFS15_BASE) +#define FM_MFS15_UART ((FM_MFS_UART_TypeDef *)FM4_MFS15_BASE) +#define FM4_MFS2 ((FM_MFS_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2 ((FM_MFS_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS2_UART ((FM_MFS_UART_TypeDef *)FM4_MFS2_BASE) +#define FM_MFS2_UART ((FM_MFS_UART_TypeDef *)FM4_MFS2_BASE) +#define FM4_MFS3 ((FM_MFS_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3 ((FM_MFS_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS3_UART ((FM_MFS_UART_TypeDef *)FM4_MFS3_BASE) +#define FM_MFS3_UART ((FM_MFS_UART_TypeDef *)FM4_MFS3_BASE) +#define FM4_MFS4 ((FM_MFS_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4 ((FM_MFS_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS4_UART ((FM_MFS_UART_TypeDef *)FM4_MFS4_BASE) +#define FM_MFS4_UART ((FM_MFS_UART_TypeDef *)FM4_MFS4_BASE) +#define FM4_MFS5 ((FM_MFS_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5 ((FM_MFS_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS5_UART ((FM_MFS_UART_TypeDef *)FM4_MFS5_BASE) +#define FM_MFS5_UART ((FM_MFS_UART_TypeDef *)FM4_MFS5_BASE) +#define FM4_MFS6 ((FM_MFS_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6 ((FM_MFS_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS6_UART ((FM_MFS_UART_TypeDef *)FM4_MFS6_BASE) +#define FM_MFS6_UART ((FM_MFS_UART_TypeDef *)FM4_MFS6_BASE) +#define FM4_MFS7 ((FM_MFS_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7 ((FM_MFS_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS7_UART ((FM_MFS_UART_TypeDef *)FM4_MFS7_BASE) +#define FM_MFS7_UART ((FM_MFS_UART_TypeDef *)FM4_MFS7_BASE) +#define FM4_MFS8 ((FM_MFS_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8 ((FM_MFS_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS8_UART ((FM_MFS_UART_TypeDef *)FM4_MFS8_BASE) +#define FM_MFS8_UART ((FM_MFS_UART_TypeDef *)FM4_MFS8_BASE) +#define FM4_MFS9 ((FM_MFS_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9 ((FM_MFS_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_CSIO ((FM_MFS_CSIO_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_I2C ((FM_MFS_I2C_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_LIN ((FM_MFS_LIN_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFS9_UART ((FM_MFS_UART_TypeDef *)FM4_MFS9_BASE) +#define FM_MFS9_UART ((FM_MFS_UART_TypeDef *)FM4_MFS9_BASE) +#define FM4_MFT_PPG ((FM_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE) +#define FM_MFT_PPG ((FM_MFT_PPG_TypeDef *)FM4_MFT_PPG_BASE) +#define FM4_MFT0 ((FM_MFT_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0 ((FM_MFT_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT0_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT0_BASE) +#define FM_MFT0_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT0_BASE) +#define FM4_MFT1 ((FM_MFT_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1 ((FM_MFT_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT1_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT1_BASE) +#define FM_MFT1_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT1_BASE) +#define FM4_MFT2 ((FM_MFT_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2 ((FM_MFT_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_ADCMP ((FM_MFT_ADCMP_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_FRT ((FM_MFT_FRT_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_ICU ((FM_MFT_ICU_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_OCU ((FM_MFT_OCU_TypeDef *)FM4_MFT2_BASE) +#define FM4_MFT2_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT2_BASE) +#define FM_MFT2_WFG ((FM_MFT_WFG_TypeDef *)FM4_MFT2_BASE) +#define FM4_PCRC ((FM_PCRC_TypeDef *)FM4_PCRC_BASE) +#define FM_PCRC ((FM_PCRC_TypeDef *)FM4_PCRC_BASE) +#define FM4_QPRC0 ((FM_QPRC_TypeDef *)FM4_QPRC0_BASE) +#define FM_QPRC0 ((FM_QPRC_TypeDef *)FM4_QPRC0_BASE) +#define FM4_QPRC0_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE) +#define FM_QPRC0_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC0_NF_BASE) +#define FM4_QPRC1 ((FM_QPRC_TypeDef *)FM4_QPRC1_BASE) +#define FM_QPRC1 ((FM_QPRC_TypeDef *)FM4_QPRC1_BASE) +#define FM4_QPRC1_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE) +#define FM_QPRC1_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC1_NF_BASE) +#define FM4_QPRC2 ((FM_QPRC_TypeDef *)FM4_QPRC2_BASE) +#define FM_QPRC2 ((FM_QPRC_TypeDef *)FM4_QPRC2_BASE) +#define FM4_QPRC2_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE) +#define FM_QPRC2_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC2_NF_BASE) +#define FM4_QPRC3 ((FM_QPRC_TypeDef *)FM4_QPRC3_BASE) +#define FM_QPRC3 ((FM_QPRC_TypeDef *)FM4_QPRC3_BASE) +#define FM4_QPRC3_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE) +#define FM_QPRC3_NF ((FM_QPRC_NF_TypeDef *)FM4_QPRC3_NF_BASE) +#define FM4_RTC ((FM_RTC_TypeDef *)FM4_RTC_BASE) +#define FM_RTC ((FM_RTC_TypeDef *)FM4_RTC_BASE) +#define FM4_SBSSR ((FM_SBSSR_TypeDef *)FM4_SBSSR_BASE) +#define FM_SBSSR ((FM_SBSSR_TypeDef *)FM4_SBSSR_BASE) +#define FM4_SDIF ((FM_SDIF_TypeDef *)FM4_SDIF_BASE) +#define FM_SDIF ((FM_SDIF_TypeDef *)FM4_SDIF_BASE) +#define FM4_SWWDT ((FM_SWWDT_TypeDef *)FM4_SWWDT_BASE) +#define FM_SWWDT ((FM_SWWDT_TypeDef *)FM4_SWWDT_BASE) +#define FM4_UNIQUE_ID ((FM_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE) +#define FM_UNIQUE_ID ((FM_UNIQUE_ID_TypeDef *)FM4_UNIQUE_ID_BASE) +#define FM4_USB0 ((FM_USB_TypeDef *)FM4_USB0_BASE) +#define FM_USB0 ((FM_USB_TypeDef *)FM4_USB0_BASE) +#define FM4_USB1 ((FM_USB_TypeDef *)FM4_USB1_BASE) +#define FM_USB1 ((FM_USB_TypeDef *)FM4_USB1_BASE) +#define FM4_USBCLK ((FM_USBCLK_TypeDef *)FM4_USBCLK_BASE) +#define FM_USBCLK ((FM_USBCLK_TypeDef *)FM4_USBCLK_BASE) +#define FM4_WC ((FM_WC_TypeDef *)FM4_WC_BASE) +#define FM_WC ((FM_WC_TypeDef *)FM4_WC_BASE) +/******************************************************************************* +* Register Definitions +*******************************************************************************/ +/******************************************************************************* +* ADC Registers ADC0 +* Register Definition +*******************************************************************************/ +#define FM_ADC0_ADSR *((volatile uint8_t*)(0x40027000UL)) +#define FM4_ADC0_ADSR *((volatile uint8_t*)(0x40027000UL)) +#define FM_ADC0_ADCR *((volatile uint8_t*)(0x40027001UL)) +#define FM4_ADC0_ADCR *((volatile uint8_t*)(0x40027001UL)) +#define FM_ADC0_SFNS *((volatile uint8_t*)(0x40027008UL)) +#define FM4_ADC0_SFNS *((volatile uint8_t*)(0x40027008UL)) +#define FM_ADC0_SCCR *((volatile uint8_t*)(0x40027009UL)) +#define FM4_ADC0_SCCR *((volatile uint8_t*)(0x40027009UL)) +#define FM_ADC0_SCFD *((volatile uint32_t*)(0x4002700CUL)) +#define FM4_ADC0_SCFD *((volatile uint32_t*)(0x4002700CUL)) +#define FM_ADC0_SCFD_FDAS1 *((volatile uint32_t*)(0x4002700CUL)) +#define FM4_ADC0_SCFD_FDAS1 *((volatile uint32_t*)(0x4002700CUL)) +#define FM_ADC0_SCIS23 *((volatile uint16_t*)(0x40027010UL)) +#define FM4_ADC0_SCIS23 *((volatile uint16_t*)(0x40027010UL)) +#define FM_ADC0_SCIS01 *((volatile uint16_t*)(0x40027014UL)) +#define FM4_ADC0_SCIS01 *((volatile uint16_t*)(0x40027014UL)) +#define FM_ADC0_PFNS *((volatile uint8_t*)(0x40027018UL)) +#define FM4_ADC0_PFNS *((volatile uint8_t*)(0x40027018UL)) +#define FM_ADC0_PCCR *((volatile uint8_t*)(0x40027019UL)) +#define FM4_ADC0_PCCR *((volatile uint8_t*)(0x40027019UL)) +#define FM_ADC0_PCFD *((volatile uint32_t*)(0x4002701CUL)) +#define FM4_ADC0_PCFD *((volatile uint32_t*)(0x4002701CUL)) +#define FM_ADC0_PCFD_FDAS1 *((volatile uint32_t*)(0x4002701CUL)) +#define FM4_ADC0_PCFD_FDAS1 *((volatile uint32_t*)(0x4002701CUL)) +#define FM_ADC0_PCIS *((volatile uint8_t*)(0x40027020UL)) +#define FM4_ADC0_PCIS *((volatile uint8_t*)(0x40027020UL)) +#define FM_ADC0_CMPCR *((volatile uint8_t*)(0x40027024UL)) +#define FM4_ADC0_CMPCR *((volatile uint8_t*)(0x40027024UL)) +#define FM_ADC0_CMPD *((volatile uint16_t*)(0x40027026UL)) +#define FM4_ADC0_CMPD *((volatile uint16_t*)(0x40027026UL)) +#define FM_ADC0_ADSS23 *((volatile uint16_t*)(0x40027028UL)) +#define FM4_ADC0_ADSS23 *((volatile uint16_t*)(0x40027028UL)) +#define FM_ADC0_ADSS01 *((volatile uint16_t*)(0x4002702CUL)) +#define FM4_ADC0_ADSS01 *((volatile uint16_t*)(0x4002702CUL)) +#define FM_ADC0_ADST01 *((volatile uint16_t*)(0x40027030UL)) +#define FM4_ADC0_ADST01 *((volatile uint16_t*)(0x40027030UL)) +#define FM_ADC0_ADCT *((volatile uint8_t*)(0x40027034UL)) +#define FM4_ADC0_ADCT *((volatile uint8_t*)(0x40027034UL)) +#define FM_ADC0_PRTSL *((volatile uint8_t*)(0x40027038UL)) +#define FM4_ADC0_PRTSL *((volatile uint8_t*)(0x40027038UL)) +#define FM_ADC0_SCTSL *((volatile uint8_t*)(0x40027039UL)) +#define FM4_ADC0_SCTSL *((volatile uint8_t*)(0x40027039UL)) +#define FM_ADC0_ADCEN *((volatile uint16_t*)(0x4002703CUL)) +#define FM4_ADC0_ADCEN *((volatile uint16_t*)(0x4002703CUL)) +#define FM_ADC0_CALSR *((volatile uint32_t*)(0x40027040UL)) +#define FM4_ADC0_CALSR *((volatile uint32_t*)(0x40027040UL)) +#define FM_ADC0_WCMRCOT *((volatile uint8_t*)(0x40027044UL)) +#define FM4_ADC0_WCMRCOT *((volatile uint8_t*)(0x40027044UL)) +#define FM_ADC0_WCMRCIF *((volatile uint8_t*)(0x40027048UL)) +#define FM4_ADC0_WCMRCIF *((volatile uint8_t*)(0x40027048UL)) +#define FM_ADC0_WCMPCR *((volatile uint8_t*)(0x4002704CUL)) +#define FM4_ADC0_WCMPCR *((volatile uint8_t*)(0x4002704CUL)) +#define FM_ADC0_WCMPSR *((volatile uint8_t*)(0x4002704DUL)) +#define FM4_ADC0_WCMPSR *((volatile uint8_t*)(0x4002704DUL)) +#define FM_ADC0_WCMPDL *((volatile uint16_t*)(0x40027050UL)) +#define FM4_ADC0_WCMPDL *((volatile uint16_t*)(0x40027050UL)) +#define FM_ADC0_WCMPDH *((volatile uint16_t*)(0x40027052UL)) +#define FM4_ADC0_WCMPDH *((volatile uint16_t*)(0x40027052UL)) + +/******************************************************************************* +* ADC Registers ADC1 +* Register Definition +*******************************************************************************/ +#define FM_ADC1_ADSR *((volatile uint8_t*)(0x40027100UL)) +#define FM4_ADC1_ADSR *((volatile uint8_t*)(0x40027100UL)) +#define FM_ADC1_ADCR *((volatile uint8_t*)(0x40027101UL)) +#define FM4_ADC1_ADCR *((volatile uint8_t*)(0x40027101UL)) +#define FM_ADC1_SFNS *((volatile uint8_t*)(0x40027108UL)) +#define FM4_ADC1_SFNS *((volatile uint8_t*)(0x40027108UL)) +#define FM_ADC1_SCCR *((volatile uint8_t*)(0x40027109UL)) +#define FM4_ADC1_SCCR *((volatile uint8_t*)(0x40027109UL)) +#define FM_ADC1_SCFD *((volatile uint32_t*)(0x4002710CUL)) +#define FM4_ADC1_SCFD *((volatile uint32_t*)(0x4002710CUL)) +#define FM_ADC1_SCFD_FDAS1 *((volatile uint32_t*)(0x4002710CUL)) +#define FM4_ADC1_SCFD_FDAS1 *((volatile uint32_t*)(0x4002710CUL)) +#define FM_ADC1_SCIS23 *((volatile uint16_t*)(0x40027110UL)) +#define FM4_ADC1_SCIS23 *((volatile uint16_t*)(0x40027110UL)) +#define FM_ADC1_SCIS01 *((volatile uint16_t*)(0x40027114UL)) +#define FM4_ADC1_SCIS01 *((volatile uint16_t*)(0x40027114UL)) +#define FM_ADC1_PFNS *((volatile uint8_t*)(0x40027118UL)) +#define FM4_ADC1_PFNS *((volatile uint8_t*)(0x40027118UL)) +#define FM_ADC1_PCCR *((volatile uint8_t*)(0x40027119UL)) +#define FM4_ADC1_PCCR *((volatile uint8_t*)(0x40027119UL)) +#define FM_ADC1_PCFD *((volatile uint32_t*)(0x4002711CUL)) +#define FM4_ADC1_PCFD *((volatile uint32_t*)(0x4002711CUL)) +#define FM_ADC1_PCFD_FDAS1 *((volatile uint32_t*)(0x4002711CUL)) +#define FM4_ADC1_PCFD_FDAS1 *((volatile uint32_t*)(0x4002711CUL)) +#define FM_ADC1_PCIS *((volatile uint8_t*)(0x40027120UL)) +#define FM4_ADC1_PCIS *((volatile uint8_t*)(0x40027120UL)) +#define FM_ADC1_CMPCR *((volatile uint8_t*)(0x40027124UL)) +#define FM4_ADC1_CMPCR *((volatile uint8_t*)(0x40027124UL)) +#define FM_ADC1_CMPD *((volatile uint16_t*)(0x40027126UL)) +#define FM4_ADC1_CMPD *((volatile uint16_t*)(0x40027126UL)) +#define FM_ADC1_ADSS23 *((volatile uint16_t*)(0x40027128UL)) +#define FM4_ADC1_ADSS23 *((volatile uint16_t*)(0x40027128UL)) +#define FM_ADC1_ADSS01 *((volatile uint16_t*)(0x4002712CUL)) +#define FM4_ADC1_ADSS01 *((volatile uint16_t*)(0x4002712CUL)) +#define FM_ADC1_ADST01 *((volatile uint16_t*)(0x40027130UL)) +#define FM4_ADC1_ADST01 *((volatile uint16_t*)(0x40027130UL)) +#define FM_ADC1_ADCT *((volatile uint8_t*)(0x40027134UL)) +#define FM4_ADC1_ADCT *((volatile uint8_t*)(0x40027134UL)) +#define FM_ADC1_PRTSL *((volatile uint8_t*)(0x40027138UL)) +#define FM4_ADC1_PRTSL *((volatile uint8_t*)(0x40027138UL)) +#define FM_ADC1_SCTSL *((volatile uint8_t*)(0x40027139UL)) +#define FM4_ADC1_SCTSL *((volatile uint8_t*)(0x40027139UL)) +#define FM_ADC1_ADCEN *((volatile uint16_t*)(0x4002713CUL)) +#define FM4_ADC1_ADCEN *((volatile uint16_t*)(0x4002713CUL)) +#define FM_ADC1_CALSR *((volatile uint32_t*)(0x40027140UL)) +#define FM4_ADC1_CALSR *((volatile uint32_t*)(0x40027140UL)) +#define FM_ADC1_WCMRCOT *((volatile uint8_t*)(0x40027144UL)) +#define FM4_ADC1_WCMRCOT *((volatile uint8_t*)(0x40027144UL)) +#define FM_ADC1_WCMRCIF *((volatile uint8_t*)(0x40027148UL)) +#define FM4_ADC1_WCMRCIF *((volatile uint8_t*)(0x40027148UL)) +#define FM_ADC1_WCMPCR *((volatile uint8_t*)(0x4002714CUL)) +#define FM4_ADC1_WCMPCR *((volatile uint8_t*)(0x4002714CUL)) +#define FM_ADC1_WCMPSR *((volatile uint8_t*)(0x4002714DUL)) +#define FM4_ADC1_WCMPSR *((volatile uint8_t*)(0x4002714DUL)) +#define FM_ADC1_WCMPDL *((volatile uint16_t*)(0x40027150UL)) +#define FM4_ADC1_WCMPDL *((volatile uint16_t*)(0x40027150UL)) +#define FM_ADC1_WCMPDH *((volatile uint16_t*)(0x40027152UL)) +#define FM4_ADC1_WCMPDH *((volatile uint16_t*)(0x40027152UL)) + +/******************************************************************************* +* ADC Registers ADC2 +* Register Definition +*******************************************************************************/ +#define FM_ADC2_ADSR *((volatile uint8_t*)(0x40027200UL)) +#define FM4_ADC2_ADSR *((volatile uint8_t*)(0x40027200UL)) +#define FM_ADC2_ADCR *((volatile uint8_t*)(0x40027201UL)) +#define FM4_ADC2_ADCR *((volatile uint8_t*)(0x40027201UL)) +#define FM_ADC2_SFNS *((volatile uint8_t*)(0x40027208UL)) +#define FM4_ADC2_SFNS *((volatile uint8_t*)(0x40027208UL)) +#define FM_ADC2_SCCR *((volatile uint8_t*)(0x40027209UL)) +#define FM4_ADC2_SCCR *((volatile uint8_t*)(0x40027209UL)) +#define FM_ADC2_SCFD *((volatile uint32_t*)(0x4002720CUL)) +#define FM4_ADC2_SCFD *((volatile uint32_t*)(0x4002720CUL)) +#define FM_ADC2_SCFD_FDAS1 *((volatile uint32_t*)(0x4002720CUL)) +#define FM4_ADC2_SCFD_FDAS1 *((volatile uint32_t*)(0x4002720CUL)) +#define FM_ADC2_SCIS23 *((volatile uint16_t*)(0x40027210UL)) +#define FM4_ADC2_SCIS23 *((volatile uint16_t*)(0x40027210UL)) +#define FM_ADC2_SCIS01 *((volatile uint16_t*)(0x40027214UL)) +#define FM4_ADC2_SCIS01 *((volatile uint16_t*)(0x40027214UL)) +#define FM_ADC2_PFNS *((volatile uint8_t*)(0x40027218UL)) +#define FM4_ADC2_PFNS *((volatile uint8_t*)(0x40027218UL)) +#define FM_ADC2_PCCR *((volatile uint8_t*)(0x40027219UL)) +#define FM4_ADC2_PCCR *((volatile uint8_t*)(0x40027219UL)) +#define FM_ADC2_PCFD *((volatile uint32_t*)(0x4002721CUL)) +#define FM4_ADC2_PCFD *((volatile uint32_t*)(0x4002721CUL)) +#define FM_ADC2_PCFD_FDAS1 *((volatile uint32_t*)(0x4002721CUL)) +#define FM4_ADC2_PCFD_FDAS1 *((volatile uint32_t*)(0x4002721CUL)) +#define FM_ADC2_PCIS *((volatile uint8_t*)(0x40027220UL)) +#define FM4_ADC2_PCIS *((volatile uint8_t*)(0x40027220UL)) +#define FM_ADC2_CMPCR *((volatile uint8_t*)(0x40027224UL)) +#define FM4_ADC2_CMPCR *((volatile uint8_t*)(0x40027224UL)) +#define FM_ADC2_CMPD *((volatile uint16_t*)(0x40027226UL)) +#define FM4_ADC2_CMPD *((volatile uint16_t*)(0x40027226UL)) +#define FM_ADC2_ADSS23 *((volatile uint16_t*)(0x40027228UL)) +#define FM4_ADC2_ADSS23 *((volatile uint16_t*)(0x40027228UL)) +#define FM_ADC2_ADSS01 *((volatile uint16_t*)(0x4002722CUL)) +#define FM4_ADC2_ADSS01 *((volatile uint16_t*)(0x4002722CUL)) +#define FM_ADC2_ADST01 *((volatile uint16_t*)(0x40027230UL)) +#define FM4_ADC2_ADST01 *((volatile uint16_t*)(0x40027230UL)) +#define FM_ADC2_ADCT *((volatile uint8_t*)(0x40027234UL)) +#define FM4_ADC2_ADCT *((volatile uint8_t*)(0x40027234UL)) +#define FM_ADC2_PRTSL *((volatile uint8_t*)(0x40027238UL)) +#define FM4_ADC2_PRTSL *((volatile uint8_t*)(0x40027238UL)) +#define FM_ADC2_SCTSL *((volatile uint8_t*)(0x40027239UL)) +#define FM4_ADC2_SCTSL *((volatile uint8_t*)(0x40027239UL)) +#define FM_ADC2_ADCEN *((volatile uint16_t*)(0x4002723CUL)) +#define FM4_ADC2_ADCEN *((volatile uint16_t*)(0x4002723CUL)) +#define FM_ADC2_CALSR *((volatile uint32_t*)(0x40027240UL)) +#define FM4_ADC2_CALSR *((volatile uint32_t*)(0x40027240UL)) +#define FM_ADC2_WCMRCOT *((volatile uint8_t*)(0x40027244UL)) +#define FM4_ADC2_WCMRCOT *((volatile uint8_t*)(0x40027244UL)) +#define FM_ADC2_WCMRCIF *((volatile uint8_t*)(0x40027248UL)) +#define FM4_ADC2_WCMRCIF *((volatile uint8_t*)(0x40027248UL)) +#define FM_ADC2_WCMPCR *((volatile uint8_t*)(0x4002724CUL)) +#define FM4_ADC2_WCMPCR *((volatile uint8_t*)(0x4002724CUL)) +#define FM_ADC2_WCMPSR *((volatile uint8_t*)(0x4002724DUL)) +#define FM4_ADC2_WCMPSR *((volatile uint8_t*)(0x4002724DUL)) +#define FM_ADC2_WCMPDL *((volatile uint16_t*)(0x40027250UL)) +#define FM4_ADC2_WCMPDL *((volatile uint16_t*)(0x40027250UL)) +#define FM_ADC2_WCMPDH *((volatile uint16_t*)(0x40027252UL)) +#define FM4_ADC2_WCMPDH *((volatile uint16_t*)(0x40027252UL)) + +/******************************************************************************* +* BT Registers BT0 +* Register Definition +*******************************************************************************/ +#define FM_BT0_PPG_PRLL *((volatile uint16_t*)(0x40025000UL)) +#define FM4_BT0_PPG_PRLL *((volatile uint16_t*)(0x40025000UL)) +#define FM_BT0_PWM_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM4_BT0_PWM_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM_BT0_RT_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM4_BT0_RT_PCSR *((volatile uint16_t*)(0x40025000UL)) +#define FM_BT0_PPG_PRLH *((volatile uint16_t*)(0x40025004UL)) +#define FM4_BT0_PPG_PRLH *((volatile uint16_t*)(0x40025004UL)) +#define FM_BT0_PWC_DTBF *((volatile uint16_t*)(0x40025004UL)) +#define FM4_BT0_PWC_DTBF *((volatile uint16_t*)(0x40025004UL)) +#define FM_BT0_PWM_PDUT *((volatile uint16_t*)(0x40025004UL)) +#define FM4_BT0_PWM_PDUT *((volatile uint16_t*)(0x40025004UL)) +#define FM_BT0_PPG_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM4_BT0_PPG_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM_BT0_PWM_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM4_BT0_PWM_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM_BT0_RT_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM4_BT0_RT_TMR *((volatile uint16_t*)(0x40025008UL)) +#define FM_BT0_PPG_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_PPG_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_PWC_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_PWC_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_PWM_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_PWM_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_RT_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM4_BT0_RT_TMCR *((volatile uint16_t*)(0x4002500CUL)) +#define FM_BT0_PPG_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_PPG_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_PWC_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_PWC_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_PWM_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_PWM_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_RT_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM4_BT0_RT_STC *((volatile uint8_t*)(0x40025010UL)) +#define FM_BT0_PPG_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_PPG_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM_BT0_PWC_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_PWC_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM_BT0_PWM_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_PWM_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM_BT0_RT_TMCR2 *((volatile uint8_t*)(0x40025011UL)) +#define FM4_BT0_RT_TMCR2 *((volatile uint8_t*)(0x40025011UL)) + +/******************************************************************************* +* BT Registers BT1 +* Register Definition +*******************************************************************************/ +#define FM_BT1_PPG_PRLL *((volatile uint16_t*)(0x40025040UL)) +#define FM4_BT1_PPG_PRLL *((volatile uint16_t*)(0x40025040UL)) +#define FM_BT1_PWM_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM4_BT1_PWM_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM_BT1_RT_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM4_BT1_RT_PCSR *((volatile uint16_t*)(0x40025040UL)) +#define FM_BT1_PPG_PRLH *((volatile uint16_t*)(0x40025044UL)) +#define FM4_BT1_PPG_PRLH *((volatile uint16_t*)(0x40025044UL)) +#define FM_BT1_PWC_DTBF *((volatile uint16_t*)(0x40025044UL)) +#define FM4_BT1_PWC_DTBF *((volatile uint16_t*)(0x40025044UL)) +#define FM_BT1_PWM_PDUT *((volatile uint16_t*)(0x40025044UL)) +#define FM4_BT1_PWM_PDUT *((volatile uint16_t*)(0x40025044UL)) +#define FM_BT1_PPG_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM4_BT1_PPG_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM_BT1_PWM_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM4_BT1_PWM_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM_BT1_RT_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM4_BT1_RT_TMR *((volatile uint16_t*)(0x40025048UL)) +#define FM_BT1_PPG_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_PPG_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_PWC_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_PWC_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_PWM_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_PWM_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_RT_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM4_BT1_RT_TMCR *((volatile uint16_t*)(0x4002504CUL)) +#define FM_BT1_PPG_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_PPG_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_PWC_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_PWC_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_PWM_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_PWM_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_RT_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM4_BT1_RT_STC *((volatile uint8_t*)(0x40025050UL)) +#define FM_BT1_PPG_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_PPG_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM_BT1_PWC_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_PWC_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM_BT1_PWM_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_PWM_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM_BT1_RT_TMCR2 *((volatile uint8_t*)(0x40025051UL)) +#define FM4_BT1_RT_TMCR2 *((volatile uint8_t*)(0x40025051UL)) + +/******************************************************************************* +* BT Registers BT10 +* Register Definition +*******************************************************************************/ +#define FM_BT10_PPG_PRLL *((volatile uint16_t*)(0x40025480UL)) +#define FM4_BT10_PPG_PRLL *((volatile uint16_t*)(0x40025480UL)) +#define FM_BT10_PWM_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM4_BT10_PWM_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM_BT10_RT_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM4_BT10_RT_PCSR *((volatile uint16_t*)(0x40025480UL)) +#define FM_BT10_PPG_PRLH *((volatile uint16_t*)(0x40025484UL)) +#define FM4_BT10_PPG_PRLH *((volatile uint16_t*)(0x40025484UL)) +#define FM_BT10_PWC_DTBF *((volatile uint16_t*)(0x40025484UL)) +#define FM4_BT10_PWC_DTBF *((volatile uint16_t*)(0x40025484UL)) +#define FM_BT10_PWM_PDUT *((volatile uint16_t*)(0x40025484UL)) +#define FM4_BT10_PWM_PDUT *((volatile uint16_t*)(0x40025484UL)) +#define FM_BT10_PPG_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM4_BT10_PPG_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM_BT10_PWM_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM4_BT10_PWM_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM_BT10_RT_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM4_BT10_RT_TMR *((volatile uint16_t*)(0x40025488UL)) +#define FM_BT10_PPG_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_PPG_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_PWC_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_PWC_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_PWM_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_PWM_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_RT_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM4_BT10_RT_TMCR *((volatile uint16_t*)(0x4002548CUL)) +#define FM_BT10_PPG_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_PPG_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_PWC_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_PWC_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_PWM_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_PWM_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_RT_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM4_BT10_RT_STC *((volatile uint8_t*)(0x40025490UL)) +#define FM_BT10_PPG_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_PPG_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM_BT10_PWC_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_PWC_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM_BT10_PWM_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_PWM_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM_BT10_RT_TMCR2 *((volatile uint8_t*)(0x40025491UL)) +#define FM4_BT10_RT_TMCR2 *((volatile uint8_t*)(0x40025491UL)) + +/******************************************************************************* +* BT Registers BT11 +* Register Definition +*******************************************************************************/ +#define FM_BT11_PPG_PRLL *((volatile uint16_t*)(0x400254C0UL)) +#define FM4_BT11_PPG_PRLL *((volatile uint16_t*)(0x400254C0UL)) +#define FM_BT11_PWM_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM4_BT11_PWM_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM_BT11_RT_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM4_BT11_RT_PCSR *((volatile uint16_t*)(0x400254C0UL)) +#define FM_BT11_PPG_PRLH *((volatile uint16_t*)(0x400254C4UL)) +#define FM4_BT11_PPG_PRLH *((volatile uint16_t*)(0x400254C4UL)) +#define FM_BT11_PWC_DTBF *((volatile uint16_t*)(0x400254C4UL)) +#define FM4_BT11_PWC_DTBF *((volatile uint16_t*)(0x400254C4UL)) +#define FM_BT11_PWM_PDUT *((volatile uint16_t*)(0x400254C4UL)) +#define FM4_BT11_PWM_PDUT *((volatile uint16_t*)(0x400254C4UL)) +#define FM_BT11_PPG_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM4_BT11_PPG_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM_BT11_PWM_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM4_BT11_PWM_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM_BT11_RT_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM4_BT11_RT_TMR *((volatile uint16_t*)(0x400254C8UL)) +#define FM_BT11_PPG_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_PPG_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_PWC_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_PWC_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_PWM_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_PWM_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_RT_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM4_BT11_RT_TMCR *((volatile uint16_t*)(0x400254CCUL)) +#define FM_BT11_PPG_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_PPG_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_PWC_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_PWC_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_PWM_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_PWM_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_RT_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM4_BT11_RT_STC *((volatile uint8_t*)(0x400254D0UL)) +#define FM_BT11_PPG_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_PPG_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM_BT11_PWC_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_PWC_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM_BT11_PWM_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_PWM_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM_BT11_RT_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) +#define FM4_BT11_RT_TMCR2 *((volatile uint8_t*)(0x400254D1UL)) + +/******************************************************************************* +* BT Registers BT12 +* Register Definition +*******************************************************************************/ +#define FM_BT12_PPG_PRLL *((volatile uint16_t*)(0x40025600UL)) +#define FM4_BT12_PPG_PRLL *((volatile uint16_t*)(0x40025600UL)) +#define FM_BT12_PWM_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM4_BT12_PWM_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM_BT12_RT_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM4_BT12_RT_PCSR *((volatile uint16_t*)(0x40025600UL)) +#define FM_BT12_PPG_PRLH *((volatile uint16_t*)(0x40025604UL)) +#define FM4_BT12_PPG_PRLH *((volatile uint16_t*)(0x40025604UL)) +#define FM_BT12_PWC_DTBF *((volatile uint16_t*)(0x40025604UL)) +#define FM4_BT12_PWC_DTBF *((volatile uint16_t*)(0x40025604UL)) +#define FM_BT12_PWM_PDUT *((volatile uint16_t*)(0x40025604UL)) +#define FM4_BT12_PWM_PDUT *((volatile uint16_t*)(0x40025604UL)) +#define FM_BT12_PPG_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM4_BT12_PPG_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM_BT12_PWM_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM4_BT12_PWM_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM_BT12_RT_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM4_BT12_RT_TMR *((volatile uint16_t*)(0x40025608UL)) +#define FM_BT12_PPG_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_PPG_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_PWC_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_PWC_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_PWM_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_PWM_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_RT_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM4_BT12_RT_TMCR *((volatile uint16_t*)(0x4002560CUL)) +#define FM_BT12_PPG_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_PPG_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_PWC_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_PWC_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_PWM_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_PWM_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_RT_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM4_BT12_RT_STC *((volatile uint8_t*)(0x40025610UL)) +#define FM_BT12_PPG_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_PPG_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM_BT12_PWC_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_PWC_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM_BT12_PWM_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_PWM_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM_BT12_RT_TMCR2 *((volatile uint8_t*)(0x40025611UL)) +#define FM4_BT12_RT_TMCR2 *((volatile uint8_t*)(0x40025611UL)) + +/******************************************************************************* +* BT Registers BT13 +* Register Definition +*******************************************************************************/ +#define FM_BT13_PPG_PRLL *((volatile uint16_t*)(0x40025640UL)) +#define FM4_BT13_PPG_PRLL *((volatile uint16_t*)(0x40025640UL)) +#define FM_BT13_PWM_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM4_BT13_PWM_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM_BT13_RT_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM4_BT13_RT_PCSR *((volatile uint16_t*)(0x40025640UL)) +#define FM_BT13_PPG_PRLH *((volatile uint16_t*)(0x40025644UL)) +#define FM4_BT13_PPG_PRLH *((volatile uint16_t*)(0x40025644UL)) +#define FM_BT13_PWC_DTBF *((volatile uint16_t*)(0x40025644UL)) +#define FM4_BT13_PWC_DTBF *((volatile uint16_t*)(0x40025644UL)) +#define FM_BT13_PWM_PDUT *((volatile uint16_t*)(0x40025644UL)) +#define FM4_BT13_PWM_PDUT *((volatile uint16_t*)(0x40025644UL)) +#define FM_BT13_PPG_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM4_BT13_PPG_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM_BT13_PWM_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM4_BT13_PWM_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM_BT13_RT_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM4_BT13_RT_TMR *((volatile uint16_t*)(0x40025648UL)) +#define FM_BT13_PPG_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_PPG_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_PWC_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_PWC_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_PWM_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_PWM_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_RT_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM4_BT13_RT_TMCR *((volatile uint16_t*)(0x4002564CUL)) +#define FM_BT13_PPG_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_PPG_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_PWC_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_PWC_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_PWM_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_PWM_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_RT_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM4_BT13_RT_STC *((volatile uint8_t*)(0x40025650UL)) +#define FM_BT13_PPG_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_PPG_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM_BT13_PWC_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_PWC_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM_BT13_PWM_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_PWM_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM_BT13_RT_TMCR2 *((volatile uint8_t*)(0x40025651UL)) +#define FM4_BT13_RT_TMCR2 *((volatile uint8_t*)(0x40025651UL)) + +/******************************************************************************* +* BT Registers BT14 +* Register Definition +*******************************************************************************/ +#define FM_BT14_PPG_PRLL *((volatile uint16_t*)(0x40025680UL)) +#define FM4_BT14_PPG_PRLL *((volatile uint16_t*)(0x40025680UL)) +#define FM_BT14_PWM_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM4_BT14_PWM_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM_BT14_RT_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM4_BT14_RT_PCSR *((volatile uint16_t*)(0x40025680UL)) +#define FM_BT14_PPG_PRLH *((volatile uint16_t*)(0x40025684UL)) +#define FM4_BT14_PPG_PRLH *((volatile uint16_t*)(0x40025684UL)) +#define FM_BT14_PWC_DTBF *((volatile uint16_t*)(0x40025684UL)) +#define FM4_BT14_PWC_DTBF *((volatile uint16_t*)(0x40025684UL)) +#define FM_BT14_PWM_PDUT *((volatile uint16_t*)(0x40025684UL)) +#define FM4_BT14_PWM_PDUT *((volatile uint16_t*)(0x40025684UL)) +#define FM_BT14_PPG_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM4_BT14_PPG_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM_BT14_PWM_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM4_BT14_PWM_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM_BT14_RT_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM4_BT14_RT_TMR *((volatile uint16_t*)(0x40025688UL)) +#define FM_BT14_PPG_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_PPG_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_PWC_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_PWC_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_PWM_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_PWM_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_RT_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM4_BT14_RT_TMCR *((volatile uint16_t*)(0x4002568CUL)) +#define FM_BT14_PPG_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_PPG_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_PWC_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_PWC_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_PWM_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_PWM_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_RT_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM4_BT14_RT_STC *((volatile uint8_t*)(0x40025690UL)) +#define FM_BT14_PPG_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_PPG_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM_BT14_PWC_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_PWC_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM_BT14_PWM_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_PWM_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM_BT14_RT_TMCR2 *((volatile uint8_t*)(0x40025691UL)) +#define FM4_BT14_RT_TMCR2 *((volatile uint8_t*)(0x40025691UL)) + +/******************************************************************************* +* BT Registers BT15 +* Register Definition +*******************************************************************************/ +#define FM_BT15_PPG_PRLL *((volatile uint16_t*)(0x400256C0UL)) +#define FM4_BT15_PPG_PRLL *((volatile uint16_t*)(0x400256C0UL)) +#define FM_BT15_PWM_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM4_BT15_PWM_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM_BT15_RT_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM4_BT15_RT_PCSR *((volatile uint16_t*)(0x400256C0UL)) +#define FM_BT15_PPG_PRLH *((volatile uint16_t*)(0x400256C4UL)) +#define FM4_BT15_PPG_PRLH *((volatile uint16_t*)(0x400256C4UL)) +#define FM_BT15_PWC_DTBF *((volatile uint16_t*)(0x400256C4UL)) +#define FM4_BT15_PWC_DTBF *((volatile uint16_t*)(0x400256C4UL)) +#define FM_BT15_PWM_PDUT *((volatile uint16_t*)(0x400256C4UL)) +#define FM4_BT15_PWM_PDUT *((volatile uint16_t*)(0x400256C4UL)) +#define FM_BT15_PPG_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM4_BT15_PPG_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM_BT15_PWM_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM4_BT15_PWM_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM_BT15_RT_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM4_BT15_RT_TMR *((volatile uint16_t*)(0x400256C8UL)) +#define FM_BT15_PPG_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_PPG_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_PWC_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_PWC_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_PWM_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_PWM_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_RT_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM4_BT15_RT_TMCR *((volatile uint16_t*)(0x400256CCUL)) +#define FM_BT15_PPG_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_PPG_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_PWC_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_PWC_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_PWM_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_PWM_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_RT_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM4_BT15_RT_STC *((volatile uint8_t*)(0x400256D0UL)) +#define FM_BT15_PPG_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_PPG_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM_BT15_PWC_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_PWC_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM_BT15_PWM_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_PWM_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM_BT15_RT_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) +#define FM4_BT15_RT_TMCR2 *((volatile uint8_t*)(0x400256D1UL)) + +/******************************************************************************* +* BT Registers BT2 +* Register Definition +*******************************************************************************/ +#define FM_BT2_PPG_PRLL *((volatile uint16_t*)(0x40025080UL)) +#define FM4_BT2_PPG_PRLL *((volatile uint16_t*)(0x40025080UL)) +#define FM_BT2_PWM_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM4_BT2_PWM_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM_BT2_RT_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM4_BT2_RT_PCSR *((volatile uint16_t*)(0x40025080UL)) +#define FM_BT2_PPG_PRLH *((volatile uint16_t*)(0x40025084UL)) +#define FM4_BT2_PPG_PRLH *((volatile uint16_t*)(0x40025084UL)) +#define FM_BT2_PWC_DTBF *((volatile uint16_t*)(0x40025084UL)) +#define FM4_BT2_PWC_DTBF *((volatile uint16_t*)(0x40025084UL)) +#define FM_BT2_PWM_PDUT *((volatile uint16_t*)(0x40025084UL)) +#define FM4_BT2_PWM_PDUT *((volatile uint16_t*)(0x40025084UL)) +#define FM_BT2_PPG_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM4_BT2_PPG_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM_BT2_PWM_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM4_BT2_PWM_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM_BT2_RT_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM4_BT2_RT_TMR *((volatile uint16_t*)(0x40025088UL)) +#define FM_BT2_PPG_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_PPG_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_PWC_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_PWC_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_PWM_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_PWM_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_RT_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM4_BT2_RT_TMCR *((volatile uint16_t*)(0x4002508CUL)) +#define FM_BT2_PPG_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_PPG_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_PWC_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_PWC_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_PWM_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_PWM_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_RT_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM4_BT2_RT_STC *((volatile uint8_t*)(0x40025090UL)) +#define FM_BT2_PPG_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_PPG_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM_BT2_PWC_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_PWC_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM_BT2_PWM_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_PWM_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM_BT2_RT_TMCR2 *((volatile uint8_t*)(0x40025091UL)) +#define FM4_BT2_RT_TMCR2 *((volatile uint8_t*)(0x40025091UL)) + +/******************************************************************************* +* BT Registers BT3 +* Register Definition +*******************************************************************************/ +#define FM_BT3_PPG_PRLL *((volatile uint16_t*)(0x400250C0UL)) +#define FM4_BT3_PPG_PRLL *((volatile uint16_t*)(0x400250C0UL)) +#define FM_BT3_PWM_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM4_BT3_PWM_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM_BT3_RT_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM4_BT3_RT_PCSR *((volatile uint16_t*)(0x400250C0UL)) +#define FM_BT3_PPG_PRLH *((volatile uint16_t*)(0x400250C4UL)) +#define FM4_BT3_PPG_PRLH *((volatile uint16_t*)(0x400250C4UL)) +#define FM_BT3_PWC_DTBF *((volatile uint16_t*)(0x400250C4UL)) +#define FM4_BT3_PWC_DTBF *((volatile uint16_t*)(0x400250C4UL)) +#define FM_BT3_PWM_PDUT *((volatile uint16_t*)(0x400250C4UL)) +#define FM4_BT3_PWM_PDUT *((volatile uint16_t*)(0x400250C4UL)) +#define FM_BT3_PPG_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM4_BT3_PPG_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM_BT3_PWM_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM4_BT3_PWM_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM_BT3_RT_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM4_BT3_RT_TMR *((volatile uint16_t*)(0x400250C8UL)) +#define FM_BT3_PPG_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_PPG_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_PWC_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_PWC_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_PWM_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_PWM_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_RT_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM4_BT3_RT_TMCR *((volatile uint16_t*)(0x400250CCUL)) +#define FM_BT3_PPG_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_PPG_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_PWC_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_PWC_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_PWM_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_PWM_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_RT_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM4_BT3_RT_STC *((volatile uint8_t*)(0x400250D0UL)) +#define FM_BT3_PPG_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_PPG_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM_BT3_PWC_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_PWC_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM_BT3_PWM_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_PWM_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM_BT3_RT_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) +#define FM4_BT3_RT_TMCR2 *((volatile uint8_t*)(0x400250D1UL)) + +/******************************************************************************* +* BT Registers BT4 +* Register Definition +*******************************************************************************/ +#define FM_BT4_PPG_PRLL *((volatile uint16_t*)(0x40025200UL)) +#define FM4_BT4_PPG_PRLL *((volatile uint16_t*)(0x40025200UL)) +#define FM_BT4_PWM_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM4_BT4_PWM_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM_BT4_RT_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM4_BT4_RT_PCSR *((volatile uint16_t*)(0x40025200UL)) +#define FM_BT4_PPG_PRLH *((volatile uint16_t*)(0x40025204UL)) +#define FM4_BT4_PPG_PRLH *((volatile uint16_t*)(0x40025204UL)) +#define FM_BT4_PWC_DTBF *((volatile uint16_t*)(0x40025204UL)) +#define FM4_BT4_PWC_DTBF *((volatile uint16_t*)(0x40025204UL)) +#define FM_BT4_PWM_PDUT *((volatile uint16_t*)(0x40025204UL)) +#define FM4_BT4_PWM_PDUT *((volatile uint16_t*)(0x40025204UL)) +#define FM_BT4_PPG_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM4_BT4_PPG_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM_BT4_PWM_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM4_BT4_PWM_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM_BT4_RT_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM4_BT4_RT_TMR *((volatile uint16_t*)(0x40025208UL)) +#define FM_BT4_PPG_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_PPG_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_PWC_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_PWC_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_PWM_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_PWM_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_RT_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM4_BT4_RT_TMCR *((volatile uint16_t*)(0x4002520CUL)) +#define FM_BT4_PPG_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_PPG_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_PWC_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_PWC_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_PWM_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_PWM_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_RT_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM4_BT4_RT_STC *((volatile uint8_t*)(0x40025210UL)) +#define FM_BT4_PPG_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_PPG_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM_BT4_PWC_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_PWC_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM_BT4_PWM_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_PWM_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM_BT4_RT_TMCR2 *((volatile uint8_t*)(0x40025211UL)) +#define FM4_BT4_RT_TMCR2 *((volatile uint8_t*)(0x40025211UL)) + +/******************************************************************************* +* BT Registers BT5 +* Register Definition +*******************************************************************************/ +#define FM_BT5_PPG_PRLL *((volatile uint16_t*)(0x40025240UL)) +#define FM4_BT5_PPG_PRLL *((volatile uint16_t*)(0x40025240UL)) +#define FM_BT5_PWM_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM4_BT5_PWM_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM_BT5_RT_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM4_BT5_RT_PCSR *((volatile uint16_t*)(0x40025240UL)) +#define FM_BT5_PPG_PRLH *((volatile uint16_t*)(0x40025244UL)) +#define FM4_BT5_PPG_PRLH *((volatile uint16_t*)(0x40025244UL)) +#define FM_BT5_PWC_DTBF *((volatile uint16_t*)(0x40025244UL)) +#define FM4_BT5_PWC_DTBF *((volatile uint16_t*)(0x40025244UL)) +#define FM_BT5_PWM_PDUT *((volatile uint16_t*)(0x40025244UL)) +#define FM4_BT5_PWM_PDUT *((volatile uint16_t*)(0x40025244UL)) +#define FM_BT5_PPG_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM4_BT5_PPG_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM_BT5_PWM_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM4_BT5_PWM_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM_BT5_RT_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM4_BT5_RT_TMR *((volatile uint16_t*)(0x40025248UL)) +#define FM_BT5_PPG_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_PPG_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_PWC_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_PWC_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_PWM_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_PWM_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_RT_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM4_BT5_RT_TMCR *((volatile uint16_t*)(0x4002524CUL)) +#define FM_BT5_PPG_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_PPG_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_PWC_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_PWC_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_PWM_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_PWM_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_RT_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM4_BT5_RT_STC *((volatile uint8_t*)(0x40025250UL)) +#define FM_BT5_PPG_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_PPG_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM_BT5_PWC_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_PWC_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM_BT5_PWM_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_PWM_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM_BT5_RT_TMCR2 *((volatile uint8_t*)(0x40025251UL)) +#define FM4_BT5_RT_TMCR2 *((volatile uint8_t*)(0x40025251UL)) + +/******************************************************************************* +* BT Registers BT6 +* Register Definition +*******************************************************************************/ +#define FM_BT6_PPG_PRLL *((volatile uint16_t*)(0x40025280UL)) +#define FM4_BT6_PPG_PRLL *((volatile uint16_t*)(0x40025280UL)) +#define FM_BT6_PWM_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM4_BT6_PWM_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM_BT6_RT_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM4_BT6_RT_PCSR *((volatile uint16_t*)(0x40025280UL)) +#define FM_BT6_PPG_PRLH *((volatile uint16_t*)(0x40025284UL)) +#define FM4_BT6_PPG_PRLH *((volatile uint16_t*)(0x40025284UL)) +#define FM_BT6_PWC_DTBF *((volatile uint16_t*)(0x40025284UL)) +#define FM4_BT6_PWC_DTBF *((volatile uint16_t*)(0x40025284UL)) +#define FM_BT6_PWM_PDUT *((volatile uint16_t*)(0x40025284UL)) +#define FM4_BT6_PWM_PDUT *((volatile uint16_t*)(0x40025284UL)) +#define FM_BT6_PPG_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM4_BT6_PPG_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM_BT6_PWM_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM4_BT6_PWM_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM_BT6_RT_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM4_BT6_RT_TMR *((volatile uint16_t*)(0x40025288UL)) +#define FM_BT6_PPG_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_PPG_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_PWC_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_PWC_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_PWM_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_PWM_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_RT_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM4_BT6_RT_TMCR *((volatile uint16_t*)(0x4002528CUL)) +#define FM_BT6_PPG_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_PPG_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_PWC_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_PWC_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_PWM_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_PWM_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_RT_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM4_BT6_RT_STC *((volatile uint8_t*)(0x40025290UL)) +#define FM_BT6_PPG_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_PPG_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM_BT6_PWC_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_PWC_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM_BT6_PWM_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_PWM_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM_BT6_RT_TMCR2 *((volatile uint8_t*)(0x40025291UL)) +#define FM4_BT6_RT_TMCR2 *((volatile uint8_t*)(0x40025291UL)) + +/******************************************************************************* +* BT Registers BT7 +* Register Definition +*******************************************************************************/ +#define FM_BT7_PPG_PRLL *((volatile uint16_t*)(0x400252C0UL)) +#define FM4_BT7_PPG_PRLL *((volatile uint16_t*)(0x400252C0UL)) +#define FM_BT7_PWM_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM4_BT7_PWM_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM_BT7_RT_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM4_BT7_RT_PCSR *((volatile uint16_t*)(0x400252C0UL)) +#define FM_BT7_PPG_PRLH *((volatile uint16_t*)(0x400252C4UL)) +#define FM4_BT7_PPG_PRLH *((volatile uint16_t*)(0x400252C4UL)) +#define FM_BT7_PWC_DTBF *((volatile uint16_t*)(0x400252C4UL)) +#define FM4_BT7_PWC_DTBF *((volatile uint16_t*)(0x400252C4UL)) +#define FM_BT7_PWM_PDUT *((volatile uint16_t*)(0x400252C4UL)) +#define FM4_BT7_PWM_PDUT *((volatile uint16_t*)(0x400252C4UL)) +#define FM_BT7_PPG_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM4_BT7_PPG_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM_BT7_PWM_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM4_BT7_PWM_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM_BT7_RT_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM4_BT7_RT_TMR *((volatile uint16_t*)(0x400252C8UL)) +#define FM_BT7_PPG_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_PPG_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_PWC_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_PWC_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_PWM_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_PWM_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_RT_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM4_BT7_RT_TMCR *((volatile uint16_t*)(0x400252CCUL)) +#define FM_BT7_PPG_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_PPG_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_PWC_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_PWC_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_PWM_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_PWM_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_RT_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM4_BT7_RT_STC *((volatile uint8_t*)(0x400252D0UL)) +#define FM_BT7_PPG_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_PPG_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM_BT7_PWC_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_PWC_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM_BT7_PWM_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_PWM_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM_BT7_RT_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) +#define FM4_BT7_RT_TMCR2 *((volatile uint8_t*)(0x400252D1UL)) + +/******************************************************************************* +* BT Registers BT8 +* Register Definition +*******************************************************************************/ +#define FM_BT8_PPG_PRLL *((volatile uint16_t*)(0x40025400UL)) +#define FM4_BT8_PPG_PRLL *((volatile uint16_t*)(0x40025400UL)) +#define FM_BT8_PWM_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM4_BT8_PWM_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM_BT8_RT_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM4_BT8_RT_PCSR *((volatile uint16_t*)(0x40025400UL)) +#define FM_BT8_PPG_PRLH *((volatile uint16_t*)(0x40025404UL)) +#define FM4_BT8_PPG_PRLH *((volatile uint16_t*)(0x40025404UL)) +#define FM_BT8_PWC_DTBF *((volatile uint16_t*)(0x40025404UL)) +#define FM4_BT8_PWC_DTBF *((volatile uint16_t*)(0x40025404UL)) +#define FM_BT8_PWM_PDUT *((volatile uint16_t*)(0x40025404UL)) +#define FM4_BT8_PWM_PDUT *((volatile uint16_t*)(0x40025404UL)) +#define FM_BT8_PPG_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM4_BT8_PPG_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM_BT8_PWM_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM4_BT8_PWM_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM_BT8_RT_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM4_BT8_RT_TMR *((volatile uint16_t*)(0x40025408UL)) +#define FM_BT8_PPG_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_PPG_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_PWC_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_PWC_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_PWM_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_PWM_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_RT_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM4_BT8_RT_TMCR *((volatile uint16_t*)(0x4002540CUL)) +#define FM_BT8_PPG_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_PPG_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_PWC_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_PWC_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_PWM_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_PWM_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_RT_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM4_BT8_RT_STC *((volatile uint8_t*)(0x40025410UL)) +#define FM_BT8_PPG_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_PPG_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM_BT8_PWC_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_PWC_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM_BT8_PWM_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_PWM_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM_BT8_RT_TMCR2 *((volatile uint8_t*)(0x40025411UL)) +#define FM4_BT8_RT_TMCR2 *((volatile uint8_t*)(0x40025411UL)) + +/******************************************************************************* +* BT Registers BT9 +* Register Definition +*******************************************************************************/ +#define FM_BT9_PPG_PRLL *((volatile uint16_t*)(0x40025440UL)) +#define FM4_BT9_PPG_PRLL *((volatile uint16_t*)(0x40025440UL)) +#define FM_BT9_PWM_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM4_BT9_PWM_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM_BT9_RT_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM4_BT9_RT_PCSR *((volatile uint16_t*)(0x40025440UL)) +#define FM_BT9_PPG_PRLH *((volatile uint16_t*)(0x40025444UL)) +#define FM4_BT9_PPG_PRLH *((volatile uint16_t*)(0x40025444UL)) +#define FM_BT9_PWC_DTBF *((volatile uint16_t*)(0x40025444UL)) +#define FM4_BT9_PWC_DTBF *((volatile uint16_t*)(0x40025444UL)) +#define FM_BT9_PWM_PDUT *((volatile uint16_t*)(0x40025444UL)) +#define FM4_BT9_PWM_PDUT *((volatile uint16_t*)(0x40025444UL)) +#define FM_BT9_PPG_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM4_BT9_PPG_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM_BT9_PWM_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM4_BT9_PWM_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM_BT9_RT_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM4_BT9_RT_TMR *((volatile uint16_t*)(0x40025448UL)) +#define FM_BT9_PPG_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_PPG_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_PWC_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_PWC_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_PWM_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_PWM_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_RT_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM4_BT9_RT_TMCR *((volatile uint16_t*)(0x4002544CUL)) +#define FM_BT9_PPG_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_PPG_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_PWC_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_PWC_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_PWM_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_PWM_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_RT_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM4_BT9_RT_STC *((volatile uint8_t*)(0x40025450UL)) +#define FM_BT9_PPG_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_PPG_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM_BT9_PWC_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_PWC_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM_BT9_PWM_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_PWM_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM_BT9_RT_TMCR2 *((volatile uint8_t*)(0x40025451UL)) +#define FM4_BT9_RT_TMCR2 *((volatile uint8_t*)(0x40025451UL)) + +/******************************************************************************* +* BTIOSEL03 Registers BTIOSEL03 +* Register Definition +*******************************************************************************/ +#define FM_BTIOSEL03_BTSEL0123 *((volatile uint8_t*)(0x40025101UL)) +#define FM4_BTIOSEL03_BTSEL0123 *((volatile uint8_t*)(0x40025101UL)) + +/******************************************************************************* +* BTIOSEL47 Registers BTIOSEL47 +* Register Definition +*******************************************************************************/ +#define FM_BTIOSEL47_BTSEL4567 *((volatile uint8_t*)(0x40025301UL)) +#define FM4_BTIOSEL47_BTSEL4567 *((volatile uint8_t*)(0x40025301UL)) + +/******************************************************************************* +* BTIOSEL8B Registers BTIOSEL8B +* Register Definition +*******************************************************************************/ +#define FM_BTIOSEL8B_BTSEL89AB *((volatile uint8_t*)(0x40025501UL)) +#define FM4_BTIOSEL8B_BTSEL89AB *((volatile uint8_t*)(0x40025501UL)) + +/******************************************************************************* +* BTIOSELCF Registers BTIOSELCF +* Register Definition +*******************************************************************************/ +#define FM_BTIOSELCF_BTSELCDEF *((volatile uint8_t*)(0x40025701UL)) +#define FM4_BTIOSELCF_BTSELCDEF *((volatile uint8_t*)(0x40025701UL)) + +/******************************************************************************* +* CAN Registers CAN0 +* Register Definition +*******************************************************************************/ +#define FM_CAN0_CTRLR *((volatile uint16_t*)(0x40062000UL)) +#define FM4_CAN0_CTRLR *((volatile uint16_t*)(0x40062000UL)) +#define FM_CAN0_STATR *((volatile uint16_t*)(0x40062002UL)) +#define FM4_CAN0_STATR *((volatile uint16_t*)(0x40062002UL)) +#define FM_CAN0_ERRCNT *((volatile uint16_t*)(0x40062004UL)) +#define FM4_CAN0_ERRCNT *((volatile uint16_t*)(0x40062004UL)) +#define FM_CAN0_BTR *((volatile uint16_t*)(0x40062006UL)) +#define FM4_CAN0_BTR *((volatile uint16_t*)(0x40062006UL)) +#define FM_CAN0_INTR *((volatile uint16_t*)(0x40062008UL)) +#define FM4_CAN0_INTR *((volatile uint16_t*)(0x40062008UL)) +#define FM_CAN0_TESTR *((volatile uint16_t*)(0x4006200AUL)) +#define FM4_CAN0_TESTR *((volatile uint16_t*)(0x4006200AUL)) +#define FM_CAN0_BRPER *((volatile uint16_t*)(0x4006200CUL)) +#define FM4_CAN0_BRPER *((volatile uint16_t*)(0x4006200CUL)) +#define FM_CAN0_IF1CREQ *((volatile uint16_t*)(0x40062010UL)) +#define FM4_CAN0_IF1CREQ *((volatile uint16_t*)(0x40062010UL)) +#define FM_CAN0_IF1CMSK *((volatile uint16_t*)(0x40062012UL)) +#define FM4_CAN0_IF1CMSK *((volatile uint16_t*)(0x40062012UL)) +#define FM_CAN0_IF1MSK *((volatile uint32_t*)(0x40062014UL)) +#define FM4_CAN0_IF1MSK *((volatile uint32_t*)(0x40062014UL)) +#define FM_CAN0_IF1ARB *((volatile uint32_t*)(0x40062018UL)) +#define FM4_CAN0_IF1ARB *((volatile uint32_t*)(0x40062018UL)) +#define FM_CAN0_IF1MCTR *((volatile uint16_t*)(0x4006201CUL)) +#define FM4_CAN0_IF1MCTR *((volatile uint16_t*)(0x4006201CUL)) +#define FM_CAN0_IF1DTA_L *((volatile uint32_t*)(0x40062020UL)) +#define FM4_CAN0_IF1DTA_L *((volatile uint32_t*)(0x40062020UL)) +#define FM_CAN0_IF1DTB_L *((volatile uint32_t*)(0x40062024UL)) +#define FM4_CAN0_IF1DTB_L *((volatile uint32_t*)(0x40062024UL)) +#define FM_CAN0_IF1DTA_B *((volatile uint32_t*)(0x40062030UL)) +#define FM4_CAN0_IF1DTA_B *((volatile uint32_t*)(0x40062030UL)) +#define FM_CAN0_IF1DTB_B *((volatile uint32_t*)(0x40062034UL)) +#define FM4_CAN0_IF1DTB_B *((volatile uint32_t*)(0x40062034UL)) +#define FM_CAN0_IF2CREQ *((volatile uint16_t*)(0x40062040UL)) +#define FM4_CAN0_IF2CREQ *((volatile uint16_t*)(0x40062040UL)) +#define FM_CAN0_IF2CMSK *((volatile uint16_t*)(0x40062042UL)) +#define FM4_CAN0_IF2CMSK *((volatile uint16_t*)(0x40062042UL)) +#define FM_CAN0_IF2MSK *((volatile uint32_t*)(0x40062044UL)) +#define FM4_CAN0_IF2MSK *((volatile uint32_t*)(0x40062044UL)) +#define FM_CAN0_IF2ARB *((volatile uint32_t*)(0x40062048UL)) +#define FM4_CAN0_IF2ARB *((volatile uint32_t*)(0x40062048UL)) +#define FM_CAN0_IF2MCTR *((volatile uint16_t*)(0x4006204CUL)) +#define FM4_CAN0_IF2MCTR *((volatile uint16_t*)(0x4006204CUL)) +#define FM_CAN0_IF2DTA_L *((volatile uint32_t*)(0x40062050UL)) +#define FM4_CAN0_IF2DTA_L *((volatile uint32_t*)(0x40062050UL)) +#define FM_CAN0_IF2DTB_L *((volatile uint32_t*)(0x40062054UL)) +#define FM4_CAN0_IF2DTB_L *((volatile uint32_t*)(0x40062054UL)) +#define FM_CAN0_IF2DTA_B *((volatile uint32_t*)(0x40062060UL)) +#define FM4_CAN0_IF2DTA_B *((volatile uint32_t*)(0x40062060UL)) +#define FM_CAN0_IF2DTB_B *((volatile uint32_t*)(0x40062064UL)) +#define FM4_CAN0_IF2DTB_B *((volatile uint32_t*)(0x40062064UL)) +#define FM_CAN0_TREQR *((volatile uint32_t*)(0x40062080UL)) +#define FM4_CAN0_TREQR *((volatile uint32_t*)(0x40062080UL)) +#define FM_CAN0_NEWDT *((volatile uint32_t*)(0x40062090UL)) +#define FM4_CAN0_NEWDT *((volatile uint32_t*)(0x40062090UL)) +#define FM_CAN0_INTPND *((volatile uint32_t*)(0x400620A0UL)) +#define FM4_CAN0_INTPND *((volatile uint32_t*)(0x400620A0UL)) +#define FM_CAN0_MSGVAL *((volatile uint32_t*)(0x400620B0UL)) +#define FM4_CAN0_MSGVAL *((volatile uint32_t*)(0x400620B0UL)) + +/******************************************************************************* +* CAN Registers CAN1 +* Register Definition +*******************************************************************************/ +#define FM_CAN1_CTRLR *((volatile uint16_t*)(0x40063000UL)) +#define FM4_CAN1_CTRLR *((volatile uint16_t*)(0x40063000UL)) +#define FM_CAN1_STATR *((volatile uint16_t*)(0x40063002UL)) +#define FM4_CAN1_STATR *((volatile uint16_t*)(0x40063002UL)) +#define FM_CAN1_ERRCNT *((volatile uint16_t*)(0x40063004UL)) +#define FM4_CAN1_ERRCNT *((volatile uint16_t*)(0x40063004UL)) +#define FM_CAN1_BTR *((volatile uint16_t*)(0x40063006UL)) +#define FM4_CAN1_BTR *((volatile uint16_t*)(0x40063006UL)) +#define FM_CAN1_INTR *((volatile uint16_t*)(0x40063008UL)) +#define FM4_CAN1_INTR *((volatile uint16_t*)(0x40063008UL)) +#define FM_CAN1_TESTR *((volatile uint16_t*)(0x4006300AUL)) +#define FM4_CAN1_TESTR *((volatile uint16_t*)(0x4006300AUL)) +#define FM_CAN1_BRPER *((volatile uint16_t*)(0x4006300CUL)) +#define FM4_CAN1_BRPER *((volatile uint16_t*)(0x4006300CUL)) +#define FM_CAN1_IF1CREQ *((volatile uint16_t*)(0x40063010UL)) +#define FM4_CAN1_IF1CREQ *((volatile uint16_t*)(0x40063010UL)) +#define FM_CAN1_IF1CMSK *((volatile uint16_t*)(0x40063012UL)) +#define FM4_CAN1_IF1CMSK *((volatile uint16_t*)(0x40063012UL)) +#define FM_CAN1_IF1MSK *((volatile uint32_t*)(0x40063014UL)) +#define FM4_CAN1_IF1MSK *((volatile uint32_t*)(0x40063014UL)) +#define FM_CAN1_IF1ARB *((volatile uint32_t*)(0x40063018UL)) +#define FM4_CAN1_IF1ARB *((volatile uint32_t*)(0x40063018UL)) +#define FM_CAN1_IF1MCTR *((volatile uint16_t*)(0x4006301CUL)) +#define FM4_CAN1_IF1MCTR *((volatile uint16_t*)(0x4006301CUL)) +#define FM_CAN1_IF1DTA_L *((volatile uint32_t*)(0x40063020UL)) +#define FM4_CAN1_IF1DTA_L *((volatile uint32_t*)(0x40063020UL)) +#define FM_CAN1_IF1DTB_L *((volatile uint32_t*)(0x40063024UL)) +#define FM4_CAN1_IF1DTB_L *((volatile uint32_t*)(0x40063024UL)) +#define FM_CAN1_IF1DTA_B *((volatile uint32_t*)(0x40063030UL)) +#define FM4_CAN1_IF1DTA_B *((volatile uint32_t*)(0x40063030UL)) +#define FM_CAN1_IF1DTB_B *((volatile uint32_t*)(0x40063034UL)) +#define FM4_CAN1_IF1DTB_B *((volatile uint32_t*)(0x40063034UL)) +#define FM_CAN1_IF2CREQ *((volatile uint16_t*)(0x40063040UL)) +#define FM4_CAN1_IF2CREQ *((volatile uint16_t*)(0x40063040UL)) +#define FM_CAN1_IF2CMSK *((volatile uint16_t*)(0x40063042UL)) +#define FM4_CAN1_IF2CMSK *((volatile uint16_t*)(0x40063042UL)) +#define FM_CAN1_IF2MSK *((volatile uint32_t*)(0x40063044UL)) +#define FM4_CAN1_IF2MSK *((volatile uint32_t*)(0x40063044UL)) +#define FM_CAN1_IF2ARB *((volatile uint32_t*)(0x40063048UL)) +#define FM4_CAN1_IF2ARB *((volatile uint32_t*)(0x40063048UL)) +#define FM_CAN1_IF2MCTR *((volatile uint16_t*)(0x4006304CUL)) +#define FM4_CAN1_IF2MCTR *((volatile uint16_t*)(0x4006304CUL)) +#define FM_CAN1_IF2DTA_L *((volatile uint32_t*)(0x40063050UL)) +#define FM4_CAN1_IF2DTA_L *((volatile uint32_t*)(0x40063050UL)) +#define FM_CAN1_IF2DTB_L *((volatile uint32_t*)(0x40063054UL)) +#define FM4_CAN1_IF2DTB_L *((volatile uint32_t*)(0x40063054UL)) +#define FM_CAN1_IF2DTA_B *((volatile uint32_t*)(0x40063060UL)) +#define FM4_CAN1_IF2DTA_B *((volatile uint32_t*)(0x40063060UL)) +#define FM_CAN1_IF2DTB_B *((volatile uint32_t*)(0x40063064UL)) +#define FM4_CAN1_IF2DTB_B *((volatile uint32_t*)(0x40063064UL)) +#define FM_CAN1_TREQR *((volatile uint32_t*)(0x40063080UL)) +#define FM4_CAN1_TREQR *((volatile uint32_t*)(0x40063080UL)) +#define FM_CAN1_NEWDT *((volatile uint32_t*)(0x40063090UL)) +#define FM4_CAN1_NEWDT *((volatile uint32_t*)(0x40063090UL)) +#define FM_CAN1_INTPND *((volatile uint32_t*)(0x400630A0UL)) +#define FM4_CAN1_INTPND *((volatile uint32_t*)(0x400630A0UL)) +#define FM_CAN1_MSGVAL *((volatile uint32_t*)(0x400630B0UL)) +#define FM4_CAN1_MSGVAL *((volatile uint32_t*)(0x400630B0UL)) + +/******************************************************************************* +* CANFD Registers CANFD0 +* Register Definition +*******************************************************************************/ +#define FM_CANFD0_CREL *((volatile uint32_t*)(0x40070000UL)) +#define FM4_CANFD0_CREL *((volatile uint32_t*)(0x40070000UL)) +#define FM_CANFD0_ENDN *((volatile uint32_t*)(0x40070004UL)) +#define FM4_CANFD0_ENDN *((volatile uint32_t*)(0x40070004UL)) +#define FM_CANFD0_FBTP *((volatile uint32_t*)(0x4007000CUL)) +#define FM4_CANFD0_FBTP *((volatile uint32_t*)(0x4007000CUL)) +#define FM_CANFD0_TEST *((volatile uint32_t*)(0x40070010UL)) +#define FM4_CANFD0_TEST *((volatile uint32_t*)(0x40070010UL)) +#define FM_CANFD0_RWD *((volatile uint32_t*)(0x40070014UL)) +#define FM4_CANFD0_RWD *((volatile uint32_t*)(0x40070014UL)) +#define FM_CANFD0_CCCR *((volatile uint32_t*)(0x40070018UL)) +#define FM4_CANFD0_CCCR *((volatile uint32_t*)(0x40070018UL)) +#define FM_CANFD0_BTP *((volatile uint32_t*)(0x4007001CUL)) +#define FM4_CANFD0_BTP *((volatile uint32_t*)(0x4007001CUL)) +#define FM_CANFD0_TSCC *((volatile uint32_t*)(0x40070020UL)) +#define FM4_CANFD0_TSCC *((volatile uint32_t*)(0x40070020UL)) +#define FM_CANFD0_TSCV *((volatile uint32_t*)(0x40070024UL)) +#define FM4_CANFD0_TSCV *((volatile uint32_t*)(0x40070024UL)) +#define FM_CANFD0_TOCC *((volatile uint32_t*)(0x40070028UL)) +#define FM4_CANFD0_TOCC *((volatile uint32_t*)(0x40070028UL)) +#define FM_CANFD0_TOCV *((volatile uint32_t*)(0x4007002CUL)) +#define FM4_CANFD0_TOCV *((volatile uint32_t*)(0x4007002CUL)) +#define FM_CANFD0_ECR *((volatile uint32_t*)(0x40070040UL)) +#define FM4_CANFD0_ECR *((volatile uint32_t*)(0x40070040UL)) +#define FM_CANFD0_PSR *((volatile uint32_t*)(0x40070044UL)) +#define FM4_CANFD0_PSR *((volatile uint32_t*)(0x40070044UL)) +#define FM_CANFD0_IR *((volatile uint32_t*)(0x40070050UL)) +#define FM4_CANFD0_IR *((volatile uint32_t*)(0x40070050UL)) +#define FM_CANFD0_IE *((volatile uint32_t*)(0x40070054UL)) +#define FM4_CANFD0_IE *((volatile uint32_t*)(0x40070054UL)) +#define FM_CANFD0_ILS *((volatile uint32_t*)(0x40070058UL)) +#define FM4_CANFD0_ILS *((volatile uint32_t*)(0x40070058UL)) +#define FM_CANFD0_ILE *((volatile uint32_t*)(0x4007005CUL)) +#define FM4_CANFD0_ILE *((volatile uint32_t*)(0x4007005CUL)) +#define FM_CANFD0_GFC *((volatile uint32_t*)(0x40070080UL)) +#define FM4_CANFD0_GFC *((volatile uint32_t*)(0x40070080UL)) +#define FM_CANFD0_SIDFC *((volatile uint32_t*)(0x40070084UL)) +#define FM4_CANFD0_SIDFC *((volatile uint32_t*)(0x40070084UL)) +#define FM_CANFD0_XIDFC *((volatile uint32_t*)(0x40070088UL)) +#define FM4_CANFD0_XIDFC *((volatile uint32_t*)(0x40070088UL)) +#define FM_CANFD0_XIDAM *((volatile uint32_t*)(0x40070090UL)) +#define FM4_CANFD0_XIDAM *((volatile uint32_t*)(0x40070090UL)) +#define FM_CANFD0_HPMS *((volatile uint32_t*)(0x40070094UL)) +#define FM4_CANFD0_HPMS *((volatile uint32_t*)(0x40070094UL)) +#define FM_CANFD0_NDAT1 *((volatile uint32_t*)(0x40070098UL)) +#define FM4_CANFD0_NDAT1 *((volatile uint32_t*)(0x40070098UL)) +#define FM_CANFD0_NDAT2 *((volatile uint32_t*)(0x4007009CUL)) +#define FM4_CANFD0_NDAT2 *((volatile uint32_t*)(0x4007009CUL)) +#define FM_CANFD0_RXF0C *((volatile uint32_t*)(0x400700A0UL)) +#define FM4_CANFD0_RXF0C *((volatile uint32_t*)(0x400700A0UL)) +#define FM_CANFD0_RXF0S *((volatile uint32_t*)(0x400700A4UL)) +#define FM4_CANFD0_RXF0S *((volatile uint32_t*)(0x400700A4UL)) +#define FM_CANFD0_RXF0A *((volatile uint32_t*)(0x400700A8UL)) +#define FM4_CANFD0_RXF0A *((volatile uint32_t*)(0x400700A8UL)) +#define FM_CANFD0_RXBC *((volatile uint32_t*)(0x400700ACUL)) +#define FM4_CANFD0_RXBC *((volatile uint32_t*)(0x400700ACUL)) +#define FM_CANFD0_RXF1C *((volatile uint32_t*)(0x400700B0UL)) +#define FM4_CANFD0_RXF1C *((volatile uint32_t*)(0x400700B0UL)) +#define FM_CANFD0_RXF1S *((volatile uint32_t*)(0x400700B4UL)) +#define FM4_CANFD0_RXF1S *((volatile uint32_t*)(0x400700B4UL)) +#define FM_CANFD0_RXF1A *((volatile uint32_t*)(0x400700B8UL)) +#define FM4_CANFD0_RXF1A *((volatile uint32_t*)(0x400700B8UL)) +#define FM_CANFD0_RXESC *((volatile uint32_t*)(0x400700BCUL)) +#define FM4_CANFD0_RXESC *((volatile uint32_t*)(0x400700BCUL)) +#define FM_CANFD0_TXBC *((volatile uint32_t*)(0x400700C0UL)) +#define FM4_CANFD0_TXBC *((volatile uint32_t*)(0x400700C0UL)) +#define FM_CANFD0_TXFQS *((volatile uint32_t*)(0x400700C4UL)) +#define FM4_CANFD0_TXFQS *((volatile uint32_t*)(0x400700C4UL)) +#define FM_CANFD0_TXESC *((volatile uint32_t*)(0x400700C8UL)) +#define FM4_CANFD0_TXESC *((volatile uint32_t*)(0x400700C8UL)) +#define FM_CANFD0_TXBRP *((volatile uint32_t*)(0x400700CCUL)) +#define FM4_CANFD0_TXBRP *((volatile uint32_t*)(0x400700CCUL)) +#define FM_CANFD0_TXBAR *((volatile uint32_t*)(0x400700D0UL)) +#define FM4_CANFD0_TXBAR *((volatile uint32_t*)(0x400700D0UL)) +#define FM_CANFD0_TXBCR *((volatile uint32_t*)(0x400700D4UL)) +#define FM4_CANFD0_TXBCR *((volatile uint32_t*)(0x400700D4UL)) +#define FM_CANFD0_TXBTO *((volatile uint32_t*)(0x400700D8UL)) +#define FM4_CANFD0_TXBTO *((volatile uint32_t*)(0x400700D8UL)) +#define FM_CANFD0_TXBCF *((volatile uint32_t*)(0x400700DCUL)) +#define FM4_CANFD0_TXBCF *((volatile uint32_t*)(0x400700DCUL)) +#define FM_CANFD0_TXBTIE *((volatile uint32_t*)(0x400700E0UL)) +#define FM4_CANFD0_TXBTIE *((volatile uint32_t*)(0x400700E0UL)) +#define FM_CANFD0_TXBCIE *((volatile uint32_t*)(0x400700E4UL)) +#define FM4_CANFD0_TXBCIE *((volatile uint32_t*)(0x400700E4UL)) +#define FM_CANFD0_TXEFC *((volatile uint32_t*)(0x400700F0UL)) +#define FM4_CANFD0_TXEFC *((volatile uint32_t*)(0x400700F0UL)) +#define FM_CANFD0_TXFS *((volatile uint32_t*)(0x400700F4UL)) +#define FM4_CANFD0_TXFS *((volatile uint32_t*)(0x400700F4UL)) +#define FM_CANFD0_TXFA *((volatile uint32_t*)(0x400700F8UL)) +#define FM4_CANFD0_TXFA *((volatile uint32_t*)(0x400700F8UL)) +#define FM_CANFD0_FDECR *((volatile uint8_t*)(0x40070200UL)) +#define FM4_CANFD0_FDECR *((volatile uint8_t*)(0x40070200UL)) +#define FM_CANFD0_FDESR *((volatile uint8_t*)(0x40070201UL)) +#define FM4_CANFD0_FDESR *((volatile uint8_t*)(0x40070201UL)) +#define FM_CANFD0_FDSEAR *((volatile uint16_t*)(0x40070202UL)) +#define FM4_CANFD0_FDSEAR *((volatile uint16_t*)(0x40070202UL)) +#define FM_CANFD0_FDESCR *((volatile uint8_t*)(0x40070205UL)) +#define FM4_CANFD0_FDESCR *((volatile uint8_t*)(0x40070205UL)) +#define FM_CANFD0_FDDEAR *((volatile uint16_t*)(0x40070206UL)) +#define FM4_CANFD0_FDDEAR *((volatile uint16_t*)(0x40070206UL)) +#define FM_CANFD0_TSCNTR *((volatile uint16_t*)(0x40070210UL)) +#define FM4_CANFD0_TSCNTR *((volatile uint16_t*)(0x40070210UL)) +#define FM_CANFD0_TSMDR *((volatile uint16_t*)(0x40070212UL)) +#define FM4_CANFD0_TSMDR *((volatile uint16_t*)(0x40070212UL)) +#define FM_CANFD0_TSDIVR *((volatile uint32_t*)(0x40070214UL)) +#define FM4_CANFD0_TSDIVR *((volatile uint32_t*)(0x40070214UL)) +#define FM_CANFD0_TSCDTR *((volatile uint16_t*)(0x40070218UL)) +#define FM4_CANFD0_TSCDTR *((volatile uint16_t*)(0x40070218UL)) +#define FM_CANFD0_TSCPCLR *((volatile uint16_t*)(0x4007021AUL)) +#define FM4_CANFD0_TSCPCLR *((volatile uint16_t*)(0x4007021AUL)) + +/******************************************************************************* +* CANPRES Registers CANPRES +* Register Definition +*******************************************************************************/ +#define FM_CANPRES_CANPRE *((volatile uint8_t*)(0x40037000UL)) +#define FM4_CANPRES_CANPRE *((volatile uint8_t*)(0x40037000UL)) + +/******************************************************************************* +* CLK_GATING Registers CLK_GATING +* Register Definition +*******************************************************************************/ +#define FM_CLK_GATING_CKEN0 *((volatile uint32_t*)(0x4003C100UL)) +#define FM4_CLK_GATING_CKEN0 *((volatile uint32_t*)(0x4003C100UL)) +#define FM_CLK_GATING_MRST0 *((volatile uint32_t*)(0x4003C104UL)) +#define FM4_CLK_GATING_MRST0 *((volatile uint32_t*)(0x4003C104UL)) +#define FM_CLK_GATING_CKEN1 *((volatile uint32_t*)(0x4003C110UL)) +#define FM4_CLK_GATING_CKEN1 *((volatile uint32_t*)(0x4003C110UL)) +#define FM_CLK_GATING_MRST1 *((volatile uint32_t*)(0x4003C114UL)) +#define FM4_CLK_GATING_MRST1 *((volatile uint32_t*)(0x4003C114UL)) +#define FM_CLK_GATING_CKEN2 *((volatile uint32_t*)(0x4003C120UL)) +#define FM4_CLK_GATING_CKEN2 *((volatile uint32_t*)(0x4003C120UL)) +#define FM_CLK_GATING_MRST2 *((volatile uint32_t*)(0x4003C124UL)) +#define FM4_CLK_GATING_MRST2 *((volatile uint32_t*)(0x4003C124UL)) + +/******************************************************************************* +* CRC Registers CRC +* Register Definition +*******************************************************************************/ +#define FM_CRC_CRCCR *((volatile uint8_t*)(0x40039000UL)) +#define FM4_CRC_CRCCR *((volatile uint8_t*)(0x40039000UL)) +#define FM_CRC_CRCINIT *((volatile uint32_t*)(0x40039004UL)) +#define FM4_CRC_CRCINIT *((volatile uint32_t*)(0x40039004UL)) +#define FM_CRC_CRCIN *((volatile uint32_t*)(0x40039008UL)) +#define FM4_CRC_CRCIN *((volatile uint32_t*)(0x40039008UL)) +#define FM_CRC_CRCR *((volatile uint32_t*)(0x4003900CUL)) +#define FM4_CRC_CRCR *((volatile uint32_t*)(0x4003900CUL)) + +/******************************************************************************* +* CRG Registers CRG +* Register Definition +*******************************************************************************/ +#define FM_CRG_SCM_CTL *((volatile uint32_t*)(0x40010000UL)) +#define FM4_CRG_SCM_CTL *((volatile uint32_t*)(0x40010000UL)) +#define FM_CRG_SCM_STR *((volatile uint32_t*)(0x40010004UL)) +#define FM4_CRG_SCM_STR *((volatile uint32_t*)(0x40010004UL)) +#define FM_CRG_STB_CTL *((volatile uint32_t*)(0x40010008UL)) +#define FM4_CRG_STB_CTL *((volatile uint32_t*)(0x40010008UL)) +#define FM_CRG_RST_STR *((volatile uint32_t*)(0x4001000CUL)) +#define FM4_CRG_RST_STR *((volatile uint32_t*)(0x4001000CUL)) +#define FM_CRG_BSC_PSR *((volatile uint32_t*)(0x40010010UL)) +#define FM4_CRG_BSC_PSR *((volatile uint32_t*)(0x40010010UL)) +#define FM_CRG_APBC0_PSR *((volatile uint32_t*)(0x40010014UL)) +#define FM4_CRG_APBC0_PSR *((volatile uint32_t*)(0x40010014UL)) +#define FM_CRG_APBC1_PSR *((volatile uint32_t*)(0x40010018UL)) +#define FM4_CRG_APBC1_PSR *((volatile uint32_t*)(0x40010018UL)) +#define FM_CRG_APBC2_PSR *((volatile uint32_t*)(0x4001001CUL)) +#define FM4_CRG_APBC2_PSR *((volatile uint32_t*)(0x4001001CUL)) +#define FM_CRG_SWC_PSR *((volatile uint32_t*)(0x40010020UL)) +#define FM4_CRG_SWC_PSR *((volatile uint32_t*)(0x40010020UL)) +#define FM_CRG_TTC_PSR *((volatile uint32_t*)(0x40010028UL)) +#define FM4_CRG_TTC_PSR *((volatile uint32_t*)(0x40010028UL)) +#define FM_CRG_CSW_TMR *((volatile uint32_t*)(0x40010030UL)) +#define FM4_CRG_CSW_TMR *((volatile uint32_t*)(0x40010030UL)) +#define FM_CRG_PSW_TMR *((volatile uint32_t*)(0x40010034UL)) +#define FM4_CRG_PSW_TMR *((volatile uint32_t*)(0x40010034UL)) +#define FM_CRG_PLL_CTL1 *((volatile uint32_t*)(0x40010038UL)) +#define FM4_CRG_PLL_CTL1 *((volatile uint32_t*)(0x40010038UL)) +#define FM_CRG_PLL_CTL2 *((volatile uint32_t*)(0x4001003CUL)) +#define FM4_CRG_PLL_CTL2 *((volatile uint32_t*)(0x4001003CUL)) +#define FM_CRG_CSV_CTL *((volatile uint32_t*)(0x40010040UL)) +#define FM4_CRG_CSV_CTL *((volatile uint32_t*)(0x40010040UL)) +#define FM_CRG_CSV_STR *((volatile uint32_t*)(0x40010044UL)) +#define FM4_CRG_CSV_STR *((volatile uint32_t*)(0x40010044UL)) +#define FM_CRG_FCSWH_CTL *((volatile uint32_t*)(0x40010048UL)) +#define FM4_CRG_FCSWH_CTL *((volatile uint32_t*)(0x40010048UL)) +#define FM_CRG_FCSWL_CTL *((volatile uint32_t*)(0x4001004CUL)) +#define FM4_CRG_FCSWL_CTL *((volatile uint32_t*)(0x4001004CUL)) +#define FM_CRG_FCSWD_CTL *((volatile uint32_t*)(0x40010050UL)) +#define FM4_CRG_FCSWD_CTL *((volatile uint32_t*)(0x40010050UL)) +#define FM_CRG_DBWDT_CTL *((volatile uint32_t*)(0x40010054UL)) +#define FM4_CRG_DBWDT_CTL *((volatile uint32_t*)(0x40010054UL)) +#define FM_CRG_INT_ENR *((volatile uint32_t*)(0x40010060UL)) +#define FM4_CRG_INT_ENR *((volatile uint32_t*)(0x40010060UL)) +#define FM_CRG_INT_STR *((volatile uint32_t*)(0x40010064UL)) +#define FM4_CRG_INT_STR *((volatile uint32_t*)(0x40010064UL)) +#define FM_CRG_INT_CLR *((volatile uint32_t*)(0x40010068UL)) +#define FM4_CRG_INT_CLR *((volatile uint32_t*)(0x40010068UL)) +#define FM_CRG_PLLCG_CTL *((volatile uint32_t*)(0x40010074UL)) +#define FM4_CRG_PLLCG_CTL *((volatile uint32_t*)(0x40010074UL)) + +/******************************************************************************* +* CRTRIM Registers CRTRIM +* Register Definition +*******************************************************************************/ +#define FM_CRTRIM_MCR_PSR *((volatile uint8_t*)(0x4002E000UL)) +#define FM4_CRTRIM_MCR_PSR *((volatile uint8_t*)(0x4002E000UL)) +#define FM_CRTRIM_MCR_FTRM *((volatile uint32_t*)(0x4002E004UL)) +#define FM4_CRTRIM_MCR_FTRM *((volatile uint32_t*)(0x4002E004UL)) +#define FM_CRTRIM_MCR_TTRM *((volatile uint32_t*)(0x4002E008UL)) +#define FM4_CRTRIM_MCR_TTRM *((volatile uint32_t*)(0x4002E008UL)) +#define FM_CRTRIM_MCR_RLR *((volatile uint32_t*)(0x4002E00CUL)) +#define FM4_CRTRIM_MCR_RLR *((volatile uint32_t*)(0x4002E00CUL)) + +/******************************************************************************* +* DAC Registers DAC0 +* Register Definition +*******************************************************************************/ +#define FM_DAC0_DACR *((volatile uint8_t*)(0x40033000UL)) +#define FM4_DAC0_DACR *((volatile uint8_t*)(0x40033000UL)) +#define FM_DAC0_DADR *((volatile uint16_t*)(0x40033004UL)) +#define FM4_DAC0_DADR *((volatile uint16_t*)(0x40033004UL)) + +/******************************************************************************* +* DAC Registers DAC1 +* Register Definition +*******************************************************************************/ +#define FM_DAC1_DACR *((volatile uint8_t*)(0x40033008UL)) +#define FM4_DAC1_DACR *((volatile uint8_t*)(0x40033008UL)) +#define FM_DAC1_DADR *((volatile uint16_t*)(0x4003300CUL)) +#define FM4_DAC1_DADR *((volatile uint16_t*)(0x4003300CUL)) + +/******************************************************************************* +* DMAC Registers DMAC +* Register Definition +*******************************************************************************/ +#define FM_DMAC_DMACR *((volatile uint32_t*)(0x40060000UL)) +#define FM4_DMAC_DMACR *((volatile uint32_t*)(0x40060000UL)) +#define FM_DMAC_DMACA0 *((volatile uint32_t*)(0x40060010UL)) +#define FM4_DMAC_DMACA0 *((volatile uint32_t*)(0x40060010UL)) +#define FM_DMAC_DMACB0 *((volatile uint32_t*)(0x40060014UL)) +#define FM4_DMAC_DMACB0 *((volatile uint32_t*)(0x40060014UL)) +#define FM_DMAC_DMACSA0 *((volatile uint32_t*)(0x40060018UL)) +#define FM4_DMAC_DMACSA0 *((volatile uint32_t*)(0x40060018UL)) +#define FM_DMAC_DMACDA0 *((volatile uint32_t*)(0x4006001CUL)) +#define FM4_DMAC_DMACDA0 *((volatile uint32_t*)(0x4006001CUL)) +#define FM_DMAC_DMACA1 *((volatile uint32_t*)(0x40060020UL)) +#define FM4_DMAC_DMACA1 *((volatile uint32_t*)(0x40060020UL)) +#define FM_DMAC_DMACB1 *((volatile uint32_t*)(0x40060024UL)) +#define FM4_DMAC_DMACB1 *((volatile uint32_t*)(0x40060024UL)) +#define FM_DMAC_DMACSA1 *((volatile uint32_t*)(0x40060028UL)) +#define FM4_DMAC_DMACSA1 *((volatile uint32_t*)(0x40060028UL)) +#define FM_DMAC_DMACDA1 *((volatile uint32_t*)(0x4006002CUL)) +#define FM4_DMAC_DMACDA1 *((volatile uint32_t*)(0x4006002CUL)) +#define FM_DMAC_DMACA2 *((volatile uint32_t*)(0x40060030UL)) +#define FM4_DMAC_DMACA2 *((volatile uint32_t*)(0x40060030UL)) +#define FM_DMAC_DMACB2 *((volatile uint32_t*)(0x40060034UL)) +#define FM4_DMAC_DMACB2 *((volatile uint32_t*)(0x40060034UL)) +#define FM_DMAC_DMACSA2 *((volatile uint32_t*)(0x40060038UL)) +#define FM4_DMAC_DMACSA2 *((volatile uint32_t*)(0x40060038UL)) +#define FM_DMAC_DMACDA2 *((volatile uint32_t*)(0x4006003CUL)) +#define FM4_DMAC_DMACDA2 *((volatile uint32_t*)(0x4006003CUL)) +#define FM_DMAC_DMACA3 *((volatile uint32_t*)(0x40060040UL)) +#define FM4_DMAC_DMACA3 *((volatile uint32_t*)(0x40060040UL)) +#define FM_DMAC_DMACB3 *((volatile uint32_t*)(0x40060044UL)) +#define FM4_DMAC_DMACB3 *((volatile uint32_t*)(0x40060044UL)) +#define FM_DMAC_DMACSA3 *((volatile uint32_t*)(0x40060048UL)) +#define FM4_DMAC_DMACSA3 *((volatile uint32_t*)(0x40060048UL)) +#define FM_DMAC_DMACDA3 *((volatile uint32_t*)(0x4006004CUL)) +#define FM4_DMAC_DMACDA3 *((volatile uint32_t*)(0x4006004CUL)) +#define FM_DMAC_DMACA4 *((volatile uint32_t*)(0x40060050UL)) +#define FM4_DMAC_DMACA4 *((volatile uint32_t*)(0x40060050UL)) +#define FM_DMAC_DMACB4 *((volatile uint32_t*)(0x40060054UL)) +#define FM4_DMAC_DMACB4 *((volatile uint32_t*)(0x40060054UL)) +#define FM_DMAC_DMACSA4 *((volatile uint32_t*)(0x40060058UL)) +#define FM4_DMAC_DMACSA4 *((volatile uint32_t*)(0x40060058UL)) +#define FM_DMAC_DMACDA4 *((volatile uint32_t*)(0x4006005CUL)) +#define FM4_DMAC_DMACDA4 *((volatile uint32_t*)(0x4006005CUL)) +#define FM_DMAC_DMACA5 *((volatile uint32_t*)(0x40060060UL)) +#define FM4_DMAC_DMACA5 *((volatile uint32_t*)(0x40060060UL)) +#define FM_DMAC_DMACB5 *((volatile uint32_t*)(0x40060064UL)) +#define FM4_DMAC_DMACB5 *((volatile uint32_t*)(0x40060064UL)) +#define FM_DMAC_DMACSA5 *((volatile uint32_t*)(0x40060068UL)) +#define FM4_DMAC_DMACSA5 *((volatile uint32_t*)(0x40060068UL)) +#define FM_DMAC_DMACDA5 *((volatile uint32_t*)(0x4006006CUL)) +#define FM4_DMAC_DMACDA5 *((volatile uint32_t*)(0x4006006CUL)) +#define FM_DMAC_DMACA6 *((volatile uint32_t*)(0x40060070UL)) +#define FM4_DMAC_DMACA6 *((volatile uint32_t*)(0x40060070UL)) +#define FM_DMAC_DMACB6 *((volatile uint32_t*)(0x40060074UL)) +#define FM4_DMAC_DMACB6 *((volatile uint32_t*)(0x40060074UL)) +#define FM_DMAC_DMACSA6 *((volatile uint32_t*)(0x40060078UL)) +#define FM4_DMAC_DMACSA6 *((volatile uint32_t*)(0x40060078UL)) +#define FM_DMAC_DMACDA6 *((volatile uint32_t*)(0x4006007CUL)) +#define FM4_DMAC_DMACDA6 *((volatile uint32_t*)(0x4006007CUL)) +#define FM_DMAC_DMACA7 *((volatile uint32_t*)(0x40060080UL)) +#define FM4_DMAC_DMACA7 *((volatile uint32_t*)(0x40060080UL)) +#define FM_DMAC_DMACB7 *((volatile uint32_t*)(0x40060084UL)) +#define FM4_DMAC_DMACB7 *((volatile uint32_t*)(0x40060084UL)) +#define FM_DMAC_DMACSA7 *((volatile uint32_t*)(0x40060088UL)) +#define FM4_DMAC_DMACSA7 *((volatile uint32_t*)(0x40060088UL)) +#define FM_DMAC_DMACDA7 *((volatile uint32_t*)(0x4006008CUL)) +#define FM4_DMAC_DMACDA7 *((volatile uint32_t*)(0x4006008CUL)) + +/******************************************************************************* +* DS Registers DS +* Register Definition +*******************************************************************************/ +#define FM_DS_RCK_CTL *((volatile uint8_t*)(0x40035104UL)) +#define FM4_DS_RCK_CTL *((volatile uint8_t*)(0x40035104UL)) +#define FM_DS_PMD_CTL *((volatile uint8_t*)(0x40035800UL)) +#define FM4_DS_PMD_CTL *((volatile uint8_t*)(0x40035800UL)) +#define FM_DS_WRFSR *((volatile uint8_t*)(0x40035804UL)) +#define FM4_DS_WRFSR *((volatile uint8_t*)(0x40035804UL)) +#define FM_DS_WIFSR *((volatile uint16_t*)(0x40035808UL)) +#define FM4_DS_WIFSR *((volatile uint16_t*)(0x40035808UL)) +#define FM_DS_WIER *((volatile uint16_t*)(0x4003580CUL)) +#define FM4_DS_WIER *((volatile uint16_t*)(0x4003580CUL)) +#define FM_DS_WILVR *((volatile uint8_t*)(0x40035810UL)) +#define FM4_DS_WILVR *((volatile uint8_t*)(0x40035810UL)) +#define FM_DS_DSRAMR *((volatile uint8_t*)(0x40035814UL)) +#define FM4_DS_DSRAMR *((volatile uint8_t*)(0x40035814UL)) +#define FM_DS_BUR01 *((volatile uint8_t*)(0x40035900UL)) +#define FM4_DS_BUR01 *((volatile uint8_t*)(0x40035900UL)) +#define FM_DS_BUR02 *((volatile uint8_t*)(0x40035901UL)) +#define FM4_DS_BUR02 *((volatile uint8_t*)(0x40035901UL)) +#define FM_DS_BUR03 *((volatile uint8_t*)(0x40035902UL)) +#define FM4_DS_BUR03 *((volatile uint8_t*)(0x40035902UL)) +#define FM_DS_BUR04 *((volatile uint8_t*)(0x40035903UL)) +#define FM4_DS_BUR04 *((volatile uint8_t*)(0x40035903UL)) +#define FM_DS_BUR05 *((volatile uint8_t*)(0x40035904UL)) +#define FM4_DS_BUR05 *((volatile uint8_t*)(0x40035904UL)) +#define FM_DS_BUR06 *((volatile uint8_t*)(0x40035905UL)) +#define FM4_DS_BUR06 *((volatile uint8_t*)(0x40035905UL)) +#define FM_DS_BUR07 *((volatile uint8_t*)(0x40035906UL)) +#define FM4_DS_BUR07 *((volatile uint8_t*)(0x40035906UL)) +#define FM_DS_BUR08 *((volatile uint8_t*)(0x40035907UL)) +#define FM4_DS_BUR08 *((volatile uint8_t*)(0x40035907UL)) +#define FM_DS_BUR09 *((volatile uint8_t*)(0x40035908UL)) +#define FM4_DS_BUR09 *((volatile uint8_t*)(0x40035908UL)) +#define FM_DS_BUR10 *((volatile uint8_t*)(0x40035909UL)) +#define FM4_DS_BUR10 *((volatile uint8_t*)(0x40035909UL)) +#define FM_DS_BUR11 *((volatile uint8_t*)(0x4003590AUL)) +#define FM4_DS_BUR11 *((volatile uint8_t*)(0x4003590AUL)) +#define FM_DS_BUR12 *((volatile uint8_t*)(0x4003590BUL)) +#define FM4_DS_BUR12 *((volatile uint8_t*)(0x4003590BUL)) +#define FM_DS_BUR13 *((volatile uint8_t*)(0x4003590CUL)) +#define FM4_DS_BUR13 *((volatile uint8_t*)(0x4003590CUL)) +#define FM_DS_BUR14 *((volatile uint8_t*)(0x4003590DUL)) +#define FM4_DS_BUR14 *((volatile uint8_t*)(0x4003590DUL)) +#define FM_DS_BUR15 *((volatile uint8_t*)(0x4003590EUL)) +#define FM4_DS_BUR15 *((volatile uint8_t*)(0x4003590EUL)) +#define FM_DS_BUR16 *((volatile uint8_t*)(0x4003590FUL)) +#define FM4_DS_BUR16 *((volatile uint8_t*)(0x4003590FUL)) + +/******************************************************************************* +* DSTC Registers DSTC +* Register Definition +*******************************************************************************/ +#define FM_DSTC_DESTP *((volatile uint32_t*)(0x40061000UL)) +#define FM4_DSTC_DESTP *((volatile uint32_t*)(0x40061000UL)) +#define FM_DSTC_HWDESP *((volatile uint32_t*)(0x40061004UL)) +#define FM4_DSTC_HWDESP *((volatile uint32_t*)(0x40061004UL)) +#define FM_DSTC_CMD *((volatile uint8_t*)(0x40061008UL)) +#define FM4_DSTC_CMD *((volatile uint8_t*)(0x40061008UL)) +#define FM_DSTC_CFG *((volatile uint8_t*)(0x40061009UL)) +#define FM4_DSTC_CFG *((volatile uint8_t*)(0x40061009UL)) +#define FM_DSTC_SWTR *((volatile uint16_t*)(0x4006100AUL)) +#define FM4_DSTC_SWTR *((volatile uint16_t*)(0x4006100AUL)) +#define FM_DSTC_MONERS *((volatile uint32_t*)(0x4006100CUL)) +#define FM4_DSTC_MONERS *((volatile uint32_t*)(0x4006100CUL)) +#define FM_DSTC_DREQENB0 *((volatile uint32_t*)(0x40061010UL)) +#define FM4_DSTC_DREQENB0 *((volatile uint32_t*)(0x40061010UL)) +#define FM_DSTC_DREQENB1 *((volatile uint32_t*)(0x40061014UL)) +#define FM4_DSTC_DREQENB1 *((volatile uint32_t*)(0x40061014UL)) +#define FM_DSTC_DREQENB2 *((volatile uint32_t*)(0x40061018UL)) +#define FM4_DSTC_DREQENB2 *((volatile uint32_t*)(0x40061018UL)) +#define FM_DSTC_DREQENB3 *((volatile uint32_t*)(0x4006101CUL)) +#define FM4_DSTC_DREQENB3 *((volatile uint32_t*)(0x4006101CUL)) +#define FM_DSTC_DREQENB4 *((volatile uint32_t*)(0x40061020UL)) +#define FM4_DSTC_DREQENB4 *((volatile uint32_t*)(0x40061020UL)) +#define FM_DSTC_DREQENB5 *((volatile uint32_t*)(0x40061024UL)) +#define FM4_DSTC_DREQENB5 *((volatile uint32_t*)(0x40061024UL)) +#define FM_DSTC_DREQENB6 *((volatile uint32_t*)(0x40061028UL)) +#define FM4_DSTC_DREQENB6 *((volatile uint32_t*)(0x40061028UL)) +#define FM_DSTC_DREQENB7 *((volatile uint32_t*)(0x4006102CUL)) +#define FM4_DSTC_DREQENB7 *((volatile uint32_t*)(0x4006102CUL)) +#define FM_DSTC_HWINT0 *((volatile uint32_t*)(0x40061030UL)) +#define FM4_DSTC_HWINT0 *((volatile uint32_t*)(0x40061030UL)) +#define FM_DSTC_HWINT1 *((volatile uint32_t*)(0x40061034UL)) +#define FM4_DSTC_HWINT1 *((volatile uint32_t*)(0x40061034UL)) +#define FM_DSTC_HWINT2 *((volatile uint32_t*)(0x40061038UL)) +#define FM4_DSTC_HWINT2 *((volatile uint32_t*)(0x40061038UL)) +#define FM_DSTC_HWINT3 *((volatile uint32_t*)(0x4006103CUL)) +#define FM4_DSTC_HWINT3 *((volatile uint32_t*)(0x4006103CUL)) +#define FM_DSTC_HWINT4 *((volatile uint32_t*)(0x40061040UL)) +#define FM4_DSTC_HWINT4 *((volatile uint32_t*)(0x40061040UL)) +#define FM_DSTC_HWINT5 *((volatile uint32_t*)(0x40061044UL)) +#define FM4_DSTC_HWINT5 *((volatile uint32_t*)(0x40061044UL)) +#define FM_DSTC_HWINT6 *((volatile uint32_t*)(0x40061048UL)) +#define FM4_DSTC_HWINT6 *((volatile uint32_t*)(0x40061048UL)) +#define FM_DSTC_HWINT7 *((volatile uint32_t*)(0x4006104CUL)) +#define FM4_DSTC_HWINT7 *((volatile uint32_t*)(0x4006104CUL)) +#define FM_DSTC_HWINTCLR0 *((volatile uint32_t*)(0x40061050UL)) +#define FM4_DSTC_HWINTCLR0 *((volatile uint32_t*)(0x40061050UL)) +#define FM_DSTC_HWINTCLR1 *((volatile uint32_t*)(0x40061054UL)) +#define FM4_DSTC_HWINTCLR1 *((volatile uint32_t*)(0x40061054UL)) +#define FM_DSTC_HWINTCLR2 *((volatile uint32_t*)(0x40061058UL)) +#define FM4_DSTC_HWINTCLR2 *((volatile uint32_t*)(0x40061058UL)) +#define FM_DSTC_HWINTCLR3 *((volatile uint32_t*)(0x4006105CUL)) +#define FM4_DSTC_HWINTCLR3 *((volatile uint32_t*)(0x4006105CUL)) +#define FM_DSTC_HWINTCLR4 *((volatile uint32_t*)(0x40061060UL)) +#define FM4_DSTC_HWINTCLR4 *((volatile uint32_t*)(0x40061060UL)) +#define FM_DSTC_HWINTCLR5 *((volatile uint32_t*)(0x40061064UL)) +#define FM4_DSTC_HWINTCLR5 *((volatile uint32_t*)(0x40061064UL)) +#define FM_DSTC_HWINTCLR6 *((volatile uint32_t*)(0x40061068UL)) +#define FM4_DSTC_HWINTCLR6 *((volatile uint32_t*)(0x40061068UL)) +#define FM_DSTC_HWINTCLR7 *((volatile uint32_t*)(0x4006106CUL)) +#define FM4_DSTC_HWINTCLR7 *((volatile uint32_t*)(0x4006106CUL)) +#define FM_DSTC_DQMSK0 *((volatile uint32_t*)(0x40061070UL)) +#define FM4_DSTC_DQMSK0 *((volatile uint32_t*)(0x40061070UL)) +#define FM_DSTC_DQMSK1 *((volatile uint32_t*)(0x40061074UL)) +#define FM4_DSTC_DQMSK1 *((volatile uint32_t*)(0x40061074UL)) +#define FM_DSTC_DQMSK2 *((volatile uint32_t*)(0x40061078UL)) +#define FM4_DSTC_DQMSK2 *((volatile uint32_t*)(0x40061078UL)) +#define FM_DSTC_DQMSK3 *((volatile uint32_t*)(0x4006107CUL)) +#define FM4_DSTC_DQMSK3 *((volatile uint32_t*)(0x4006107CUL)) +#define FM_DSTC_DQMSK4 *((volatile uint32_t*)(0x40061080UL)) +#define FM4_DSTC_DQMSK4 *((volatile uint32_t*)(0x40061080UL)) +#define FM_DSTC_DQMSK5 *((volatile uint32_t*)(0x40061084UL)) +#define FM4_DSTC_DQMSK5 *((volatile uint32_t*)(0x40061084UL)) +#define FM_DSTC_DQMSK6 *((volatile uint32_t*)(0x40061088UL)) +#define FM4_DSTC_DQMSK6 *((volatile uint32_t*)(0x40061088UL)) +#define FM_DSTC_DQMSK7 *((volatile uint32_t*)(0x4006108CUL)) +#define FM4_DSTC_DQMSK7 *((volatile uint32_t*)(0x4006108CUL)) +#define FM_DSTC_DQMSKCLR0 *((volatile uint32_t*)(0x40061090UL)) +#define FM4_DSTC_DQMSKCLR0 *((volatile uint32_t*)(0x40061090UL)) +#define FM_DSTC_DQMSKCLR1 *((volatile uint32_t*)(0x40061094UL)) +#define FM4_DSTC_DQMSKCLR1 *((volatile uint32_t*)(0x40061094UL)) +#define FM_DSTC_DQMSKCLR2 *((volatile uint32_t*)(0x40061098UL)) +#define FM4_DSTC_DQMSKCLR2 *((volatile uint32_t*)(0x40061098UL)) +#define FM_DSTC_DQMSKCLR3 *((volatile uint32_t*)(0x4006109CUL)) +#define FM4_DSTC_DQMSKCLR3 *((volatile uint32_t*)(0x4006109CUL)) +#define FM_DSTC_DQMSKCLR4 *((volatile uint32_t*)(0x400610A0UL)) +#define FM4_DSTC_DQMSKCLR4 *((volatile uint32_t*)(0x400610A0UL)) +#define FM_DSTC_DQMSKCLR5 *((volatile uint32_t*)(0x400610A4UL)) +#define FM4_DSTC_DQMSKCLR5 *((volatile uint32_t*)(0x400610A4UL)) +#define FM_DSTC_DQMSKCLR6 *((volatile uint32_t*)(0x400610A8UL)) +#define FM4_DSTC_DQMSKCLR6 *((volatile uint32_t*)(0x400610A8UL)) +#define FM_DSTC_DQMSKCLR7 *((volatile uint32_t*)(0x400610ACUL)) +#define FM4_DSTC_DQMSKCLR7 *((volatile uint32_t*)(0x400610ACUL)) + +/******************************************************************************* +* DT Registers DT +* Register Definition +*******************************************************************************/ +#define FM_DT_TIMER1LOAD *((volatile uint32_t*)(0x40015000UL)) +#define FM4_DT_TIMER1LOAD *((volatile uint32_t*)(0x40015000UL)) +#define FM_DT_TIMER1VALUE *((volatile uint32_t*)(0x40015004UL)) +#define FM4_DT_TIMER1VALUE *((volatile uint32_t*)(0x40015004UL)) +#define FM_DT_TIMER1CONTROL *((volatile uint32_t*)(0x40015008UL)) +#define FM4_DT_TIMER1CONTROL *((volatile uint32_t*)(0x40015008UL)) +#define FM_DT_TIMER1INTCLR *((volatile uint32_t*)(0x4001500CUL)) +#define FM4_DT_TIMER1INTCLR *((volatile uint32_t*)(0x4001500CUL)) +#define FM_DT_TIMER1RIS *((volatile uint32_t*)(0x40015010UL)) +#define FM4_DT_TIMER1RIS *((volatile uint32_t*)(0x40015010UL)) +#define FM_DT_TIMER1MIS *((volatile uint32_t*)(0x40015014UL)) +#define FM4_DT_TIMER1MIS *((volatile uint32_t*)(0x40015014UL)) +#define FM_DT_TIMER1BGLOAD *((volatile uint32_t*)(0x40015018UL)) +#define FM4_DT_TIMER1BGLOAD *((volatile uint32_t*)(0x40015018UL)) +#define FM_DT_TIMER2LOAD *((volatile uint32_t*)(0x40015020UL)) +#define FM4_DT_TIMER2LOAD *((volatile uint32_t*)(0x40015020UL)) +#define FM_DT_TIMER2VALUE *((volatile uint32_t*)(0x40015024UL)) +#define FM4_DT_TIMER2VALUE *((volatile uint32_t*)(0x40015024UL)) +#define FM_DT_TIMER2CONTROL *((volatile uint32_t*)(0x40015028UL)) +#define FM4_DT_TIMER2CONTROL *((volatile uint32_t*)(0x40015028UL)) +#define FM_DT_TIMER2INTCLR *((volatile uint32_t*)(0x4001502CUL)) +#define FM4_DT_TIMER2INTCLR *((volatile uint32_t*)(0x4001502CUL)) +#define FM_DT_TIMER2RIS *((volatile uint32_t*)(0x40015030UL)) +#define FM4_DT_TIMER2RIS *((volatile uint32_t*)(0x40015030UL)) +#define FM_DT_TIMER2MIS *((volatile uint32_t*)(0x40015034UL)) +#define FM4_DT_TIMER2MIS *((volatile uint32_t*)(0x40015034UL)) +#define FM_DT_TIMER2BGLOAD *((volatile uint32_t*)(0x40015038UL)) +#define FM4_DT_TIMER2BGLOAD *((volatile uint32_t*)(0x40015038UL)) + +/******************************************************************************* +* DUALFLASH_IF Registers DUALFLASH_IF +* Register Definition +*******************************************************************************/ +#define FM_DUALFLASH_IF_DFASZR *((volatile uint32_t*)(0x40000400UL)) +#define FM4_DUALFLASH_IF_DFASZR *((volatile uint32_t*)(0x40000400UL)) +#define FM_DUALFLASH_IF_DFRWTR *((volatile uint32_t*)(0x40000404UL)) +#define FM4_DUALFLASH_IF_DFRWTR *((volatile uint32_t*)(0x40000404UL)) +#define FM_DUALFLASH_IF_DFSTR *((volatile uint32_t*)(0x40000408UL)) +#define FM4_DUALFLASH_IF_DFSTR *((volatile uint32_t*)(0x40000408UL)) + +/******************************************************************************* +* ECC_CAPTURE Registers ECC_CAPTURE +* Register Definition +*******************************************************************************/ +#define FM_ECC_CAPTURE_FERRAD *((volatile uint32_t*)(0x40000300UL)) +#define FM4_ECC_CAPTURE_FERRAD *((volatile uint32_t*)(0x40000300UL)) + +/******************************************************************************* +* EXBUS Registers EXBUS +* Register Definition +*******************************************************************************/ +#define FM_EXBUS_MODE0 *((volatile uint32_t*)(0x4003F000UL)) +#define FM4_EXBUS_MODE0 *((volatile uint32_t*)(0x4003F000UL)) +#define FM_EXBUS_MODE1 *((volatile uint32_t*)(0x4003F004UL)) +#define FM4_EXBUS_MODE1 *((volatile uint32_t*)(0x4003F004UL)) +#define FM_EXBUS_MODE2 *((volatile uint32_t*)(0x4003F008UL)) +#define FM4_EXBUS_MODE2 *((volatile uint32_t*)(0x4003F008UL)) +#define FM_EXBUS_MODE3 *((volatile uint32_t*)(0x4003F00CUL)) +#define FM4_EXBUS_MODE3 *((volatile uint32_t*)(0x4003F00CUL)) +#define FM_EXBUS_MODE4 *((volatile uint32_t*)(0x4003F010UL)) +#define FM4_EXBUS_MODE4 *((volatile uint32_t*)(0x4003F010UL)) +#define FM_EXBUS_MODE5 *((volatile uint32_t*)(0x4003F014UL)) +#define FM4_EXBUS_MODE5 *((volatile uint32_t*)(0x4003F014UL)) +#define FM_EXBUS_MODE6 *((volatile uint32_t*)(0x4003F018UL)) +#define FM4_EXBUS_MODE6 *((volatile uint32_t*)(0x4003F018UL)) +#define FM_EXBUS_MODE7 *((volatile uint32_t*)(0x4003F01CUL)) +#define FM4_EXBUS_MODE7 *((volatile uint32_t*)(0x4003F01CUL)) +#define FM_EXBUS_TIM0 *((volatile uint32_t*)(0x4003F020UL)) +#define FM4_EXBUS_TIM0 *((volatile uint32_t*)(0x4003F020UL)) +#define FM_EXBUS_TIM1 *((volatile uint32_t*)(0x4003F024UL)) +#define FM4_EXBUS_TIM1 *((volatile uint32_t*)(0x4003F024UL)) +#define FM_EXBUS_TIM2 *((volatile uint32_t*)(0x4003F028UL)) +#define FM4_EXBUS_TIM2 *((volatile uint32_t*)(0x4003F028UL)) +#define FM_EXBUS_TIM3 *((volatile uint32_t*)(0x4003F02CUL)) +#define FM4_EXBUS_TIM3 *((volatile uint32_t*)(0x4003F02CUL)) +#define FM_EXBUS_TIM4 *((volatile uint32_t*)(0x4003F030UL)) +#define FM4_EXBUS_TIM4 *((volatile uint32_t*)(0x4003F030UL)) +#define FM_EXBUS_TIM5 *((volatile uint32_t*)(0x4003F034UL)) +#define FM4_EXBUS_TIM5 *((volatile uint32_t*)(0x4003F034UL)) +#define FM_EXBUS_TIM6 *((volatile uint32_t*)(0x4003F038UL)) +#define FM4_EXBUS_TIM6 *((volatile uint32_t*)(0x4003F038UL)) +#define FM_EXBUS_TIM7 *((volatile uint32_t*)(0x4003F03CUL)) +#define FM4_EXBUS_TIM7 *((volatile uint32_t*)(0x4003F03CUL)) +#define FM_EXBUS_AREA0 *((volatile uint32_t*)(0x4003F040UL)) +#define FM4_EXBUS_AREA0 *((volatile uint32_t*)(0x4003F040UL)) +#define FM_EXBUS_AREA1 *((volatile uint32_t*)(0x4003F044UL)) +#define FM4_EXBUS_AREA1 *((volatile uint32_t*)(0x4003F044UL)) +#define FM_EXBUS_AREA2 *((volatile uint32_t*)(0x4003F048UL)) +#define FM4_EXBUS_AREA2 *((volatile uint32_t*)(0x4003F048UL)) +#define FM_EXBUS_AREA3 *((volatile uint32_t*)(0x4003F04CUL)) +#define FM4_EXBUS_AREA3 *((volatile uint32_t*)(0x4003F04CUL)) +#define FM_EXBUS_AREA4 *((volatile uint32_t*)(0x4003F050UL)) +#define FM4_EXBUS_AREA4 *((volatile uint32_t*)(0x4003F050UL)) +#define FM_EXBUS_AREA5 *((volatile uint32_t*)(0x4003F054UL)) +#define FM4_EXBUS_AREA5 *((volatile uint32_t*)(0x4003F054UL)) +#define FM_EXBUS_AREA6 *((volatile uint32_t*)(0x4003F058UL)) +#define FM4_EXBUS_AREA6 *((volatile uint32_t*)(0x4003F058UL)) +#define FM_EXBUS_AREA7 *((volatile uint32_t*)(0x4003F05CUL)) +#define FM4_EXBUS_AREA7 *((volatile uint32_t*)(0x4003F05CUL)) +#define FM_EXBUS_ATIM0 *((volatile uint32_t*)(0x4003F060UL)) +#define FM4_EXBUS_ATIM0 *((volatile uint32_t*)(0x4003F060UL)) +#define FM_EXBUS_ATIM1 *((volatile uint32_t*)(0x4003F064UL)) +#define FM4_EXBUS_ATIM1 *((volatile uint32_t*)(0x4003F064UL)) +#define FM_EXBUS_ATIM2 *((volatile uint32_t*)(0x4003F068UL)) +#define FM4_EXBUS_ATIM2 *((volatile uint32_t*)(0x4003F068UL)) +#define FM_EXBUS_ATIM3 *((volatile uint32_t*)(0x4003F06CUL)) +#define FM4_EXBUS_ATIM3 *((volatile uint32_t*)(0x4003F06CUL)) +#define FM_EXBUS_ATIM4 *((volatile uint32_t*)(0x4003F070UL)) +#define FM4_EXBUS_ATIM4 *((volatile uint32_t*)(0x4003F070UL)) +#define FM_EXBUS_ATIM5 *((volatile uint32_t*)(0x4003F074UL)) +#define FM4_EXBUS_ATIM5 *((volatile uint32_t*)(0x4003F074UL)) +#define FM_EXBUS_ATIM6 *((volatile uint32_t*)(0x4003F078UL)) +#define FM4_EXBUS_ATIM6 *((volatile uint32_t*)(0x4003F078UL)) +#define FM_EXBUS_ATIM7 *((volatile uint32_t*)(0x4003F07CUL)) +#define FM4_EXBUS_ATIM7 *((volatile uint32_t*)(0x4003F07CUL)) +#define FM_EXBUS_SDMODE *((volatile uint32_t*)(0x4003F100UL)) +#define FM4_EXBUS_SDMODE *((volatile uint32_t*)(0x4003F100UL)) +#define FM_EXBUS_REFTIM *((volatile uint32_t*)(0x4003F104UL)) +#define FM4_EXBUS_REFTIM *((volatile uint32_t*)(0x4003F104UL)) +#define FM_EXBUS_PWRDWN *((volatile uint32_t*)(0x4003F108UL)) +#define FM4_EXBUS_PWRDWN *((volatile uint32_t*)(0x4003F108UL)) +#define FM_EXBUS_SDTIM *((volatile uint32_t*)(0x4003F10CUL)) +#define FM4_EXBUS_SDTIM *((volatile uint32_t*)(0x4003F10CUL)) +#define FM_EXBUS_SDCMD *((volatile uint32_t*)(0x4003F110UL)) +#define FM4_EXBUS_SDCMD *((volatile uint32_t*)(0x4003F110UL)) +#define FM_EXBUS_MEMCERR *((volatile uint32_t*)(0x4003F200UL)) +#define FM4_EXBUS_MEMCERR *((volatile uint32_t*)(0x4003F200UL)) +#define FM_EXBUS_DCLKR *((volatile uint32_t*)(0x4003F300UL)) +#define FM4_EXBUS_DCLKR *((volatile uint32_t*)(0x4003F300UL)) +#define FM_EXBUS_EST *((volatile uint32_t*)(0x4003F304UL)) +#define FM4_EXBUS_EST *((volatile uint32_t*)(0x4003F304UL)) +#define FM_EXBUS_WEAD *((volatile uint32_t*)(0x4003F308UL)) +#define FM4_EXBUS_WEAD *((volatile uint32_t*)(0x4003F308UL)) +#define FM_EXBUS_ESCLR *((volatile uint32_t*)(0x4003F30CUL)) +#define FM4_EXBUS_ESCLR *((volatile uint32_t*)(0x4003F30CUL)) +#define FM_EXBUS_AMODE *((volatile uint32_t*)(0x4003F310UL)) +#define FM4_EXBUS_AMODE *((volatile uint32_t*)(0x4003F310UL)) + +/******************************************************************************* +* EXTI Registers EXTI +* Register Definition +*******************************************************************************/ +#define FM_EXTI_ENIR *((volatile uint32_t*)(0x40030000UL)) +#define FM4_EXTI_ENIR *((volatile uint32_t*)(0x40030000UL)) +#define FM_EXTI_EIRR *((volatile uint32_t*)(0x40030004UL)) +#define FM4_EXTI_EIRR *((volatile uint32_t*)(0x40030004UL)) +#define FM_EXTI_EICL *((volatile uint32_t*)(0x40030008UL)) +#define FM4_EXTI_EICL *((volatile uint32_t*)(0x40030008UL)) +#define FM_EXTI_ELVR *((volatile uint32_t*)(0x4003000CUL)) +#define FM4_EXTI_ELVR *((volatile uint32_t*)(0x4003000CUL)) +#define FM_EXTI_ELVR1 *((volatile uint32_t*)(0x40030010UL)) +#define FM4_EXTI_ELVR1 *((volatile uint32_t*)(0x40030010UL)) +#define FM_EXTI_NMIRR *((volatile uint16_t*)(0x40030014UL)) +#define FM4_EXTI_NMIRR *((volatile uint16_t*)(0x40030014UL)) +#define FM_EXTI_NMICL *((volatile uint16_t*)(0x40030018UL)) +#define FM4_EXTI_NMICL *((volatile uint16_t*)(0x40030018UL)) + +/******************************************************************************* +* FLASH_IF Registers FLASH_IF +* Register Definition +*******************************************************************************/ +#define FM_FLASH_IF_FASZR *((volatile uint32_t*)(0x40000000UL)) +#define FM4_FLASH_IF_FASZR *((volatile uint32_t*)(0x40000000UL)) +#define FM_FLASH_IF_FRWTR *((volatile uint32_t*)(0x40000004UL)) +#define FM4_FLASH_IF_FRWTR *((volatile uint32_t*)(0x40000004UL)) +#define FM_FLASH_IF_FSTR *((volatile uint32_t*)(0x40000008UL)) +#define FM4_FLASH_IF_FSTR *((volatile uint32_t*)(0x40000008UL)) +#define FM_FLASH_IF_FSYNDN *((volatile uint32_t*)(0x40000010UL)) +#define FM4_FLASH_IF_FSYNDN *((volatile uint32_t*)(0x40000010UL)) +#define FM_FLASH_IF_FBFCR *((volatile uint32_t*)(0x40000014UL)) +#define FM4_FLASH_IF_FBFCR *((volatile uint32_t*)(0x40000014UL)) +#define FM_FLASH_IF_FICR *((volatile uint32_t*)(0x40000020UL)) +#define FM4_FLASH_IF_FICR *((volatile uint32_t*)(0x40000020UL)) +#define FM_FLASH_IF_FISR *((volatile uint32_t*)(0x40000024UL)) +#define FM4_FLASH_IF_FISR *((volatile uint32_t*)(0x40000024UL)) +#define FM_FLASH_IF_FICLR *((volatile uint32_t*)(0x40000028UL)) +#define FM4_FLASH_IF_FICLR *((volatile uint32_t*)(0x40000028UL)) +#define FM_FLASH_IF_DFCTRLR *((volatile uint32_t*)(0x40000030UL)) +#define FM4_FLASH_IF_DFCTRLR *((volatile uint32_t*)(0x40000030UL)) +#define FM_FLASH_IF_CRTRMM *((volatile uint32_t*)(0x40000100UL)) +#define FM4_FLASH_IF_CRTRMM *((volatile uint32_t*)(0x40000100UL)) +#define FM_FLASH_IF_FGPDM1 *((volatile uint32_t*)(0x40000110UL)) +#define FM4_FLASH_IF_FGPDM1 *((volatile uint32_t*)(0x40000110UL)) +#define FM_FLASH_IF_FGPDM2 *((volatile uint32_t*)(0x40000114UL)) +#define FM4_FLASH_IF_FGPDM2 *((volatile uint32_t*)(0x40000114UL)) +#define FM_FLASH_IF_FGPDM3 *((volatile uint32_t*)(0x40000118UL)) +#define FM4_FLASH_IF_FGPDM3 *((volatile uint32_t*)(0x40000118UL)) +#define FM_FLASH_IF_FGPDM4 *((volatile uint32_t*)(0x4000011CUL)) +#define FM4_FLASH_IF_FGPDM4 *((volatile uint32_t*)(0x4000011CUL)) + +/******************************************************************************* +* GPIO Registers GPIO +* Register Definition +*******************************************************************************/ +#define FM_GPIO_PFR0 *((volatile uint32_t*)(0x4006F000UL)) +#define FM4_GPIO_PFR0 *((volatile uint32_t*)(0x4006F000UL)) +#define FM_GPIO_PFR1 *((volatile uint32_t*)(0x4006F004UL)) +#define FM4_GPIO_PFR1 *((volatile uint32_t*)(0x4006F004UL)) +#define FM_GPIO_PFR2 *((volatile uint32_t*)(0x4006F008UL)) +#define FM4_GPIO_PFR2 *((volatile uint32_t*)(0x4006F008UL)) +#define FM_GPIO_PFR3 *((volatile uint32_t*)(0x4006F00CUL)) +#define FM4_GPIO_PFR3 *((volatile uint32_t*)(0x4006F00CUL)) +#define FM_GPIO_PFR4 *((volatile uint32_t*)(0x4006F010UL)) +#define FM4_GPIO_PFR4 *((volatile uint32_t*)(0x4006F010UL)) +#define FM_GPIO_PFR5 *((volatile uint32_t*)(0x4006F014UL)) +#define FM4_GPIO_PFR5 *((volatile uint32_t*)(0x4006F014UL)) +#define FM_GPIO_PFR6 *((volatile uint32_t*)(0x4006F018UL)) +#define FM4_GPIO_PFR6 *((volatile uint32_t*)(0x4006F018UL)) +#define FM_GPIO_PFR7 *((volatile uint32_t*)(0x4006F01CUL)) +#define FM4_GPIO_PFR7 *((volatile uint32_t*)(0x4006F01CUL)) +#define FM_GPIO_PFR8 *((volatile uint32_t*)(0x4006F020UL)) +#define FM4_GPIO_PFR8 *((volatile uint32_t*)(0x4006F020UL)) +#define FM_GPIO_PFR9 *((volatile uint32_t*)(0x4006F024UL)) +#define FM4_GPIO_PFR9 *((volatile uint32_t*)(0x4006F024UL)) +#define FM_GPIO_PFRA *((volatile uint32_t*)(0x4006F028UL)) +#define FM4_GPIO_PFRA *((volatile uint32_t*)(0x4006F028UL)) +#define FM_GPIO_PFRB *((volatile uint32_t*)(0x4006F02CUL)) +#define FM4_GPIO_PFRB *((volatile uint32_t*)(0x4006F02CUL)) +#define FM_GPIO_PFRC *((volatile uint32_t*)(0x4006F030UL)) +#define FM4_GPIO_PFRC *((volatile uint32_t*)(0x4006F030UL)) +#define FM_GPIO_PFRD *((volatile uint32_t*)(0x4006F034UL)) +#define FM4_GPIO_PFRD *((volatile uint32_t*)(0x4006F034UL)) +#define FM_GPIO_PFRE *((volatile uint32_t*)(0x4006F038UL)) +#define FM4_GPIO_PFRE *((volatile uint32_t*)(0x4006F038UL)) +#define FM_GPIO_PFRF *((volatile uint32_t*)(0x4006F03CUL)) +#define FM4_GPIO_PFRF *((volatile uint32_t*)(0x4006F03CUL)) +#define FM_GPIO_PCR0 *((volatile uint32_t*)(0x4006F100UL)) +#define FM4_GPIO_PCR0 *((volatile uint32_t*)(0x4006F100UL)) +#define FM_GPIO_PCR1 *((volatile uint32_t*)(0x4006F104UL)) +#define FM4_GPIO_PCR1 *((volatile uint32_t*)(0x4006F104UL)) +#define FM_GPIO_PCR2 *((volatile uint32_t*)(0x4006F108UL)) +#define FM4_GPIO_PCR2 *((volatile uint32_t*)(0x4006F108UL)) +#define FM_GPIO_PCR3 *((volatile uint32_t*)(0x4006F10CUL)) +#define FM4_GPIO_PCR3 *((volatile uint32_t*)(0x4006F10CUL)) +#define FM_GPIO_PCR4 *((volatile uint32_t*)(0x4006F110UL)) +#define FM4_GPIO_PCR4 *((volatile uint32_t*)(0x4006F110UL)) +#define FM_GPIO_PCR5 *((volatile uint32_t*)(0x4006F114UL)) +#define FM4_GPIO_PCR5 *((volatile uint32_t*)(0x4006F114UL)) +#define FM_GPIO_PCR6 *((volatile uint32_t*)(0x4006F118UL)) +#define FM4_GPIO_PCR6 *((volatile uint32_t*)(0x4006F118UL)) +#define FM_GPIO_PCR7 *((volatile uint32_t*)(0x4006F11CUL)) +#define FM4_GPIO_PCR7 *((volatile uint32_t*)(0x4006F11CUL)) +#define FM_GPIO_PCR9 *((volatile uint32_t*)(0x4006F124UL)) +#define FM4_GPIO_PCR9 *((volatile uint32_t*)(0x4006F124UL)) +#define FM_GPIO_PCRA *((volatile uint32_t*)(0x4006F128UL)) +#define FM4_GPIO_PCRA *((volatile uint32_t*)(0x4006F128UL)) +#define FM_GPIO_PCRB *((volatile uint32_t*)(0x4006F12CUL)) +#define FM4_GPIO_PCRB *((volatile uint32_t*)(0x4006F12CUL)) +#define FM_GPIO_PCRC *((volatile uint32_t*)(0x4006F130UL)) +#define FM4_GPIO_PCRC *((volatile uint32_t*)(0x4006F130UL)) +#define FM_GPIO_PCRD *((volatile uint32_t*)(0x4006F134UL)) +#define FM4_GPIO_PCRD *((volatile uint32_t*)(0x4006F134UL)) +#define FM_GPIO_PCRE *((volatile uint32_t*)(0x4006F138UL)) +#define FM4_GPIO_PCRE *((volatile uint32_t*)(0x4006F138UL)) +#define FM_GPIO_PCRF *((volatile uint32_t*)(0x4006F13CUL)) +#define FM4_GPIO_PCRF *((volatile uint32_t*)(0x4006F13CUL)) +#define FM_GPIO_DDR0 *((volatile uint32_t*)(0x4006F200UL)) +#define FM4_GPIO_DDR0 *((volatile uint32_t*)(0x4006F200UL)) +#define FM_GPIO_DDR1 *((volatile uint32_t*)(0x4006F204UL)) +#define FM4_GPIO_DDR1 *((volatile uint32_t*)(0x4006F204UL)) +#define FM_GPIO_DDR2 *((volatile uint32_t*)(0x4006F208UL)) +#define FM4_GPIO_DDR2 *((volatile uint32_t*)(0x4006F208UL)) +#define FM_GPIO_DDR3 *((volatile uint32_t*)(0x4006F20CUL)) +#define FM4_GPIO_DDR3 *((volatile uint32_t*)(0x4006F20CUL)) +#define FM_GPIO_DDR4 *((volatile uint32_t*)(0x4006F210UL)) +#define FM4_GPIO_DDR4 *((volatile uint32_t*)(0x4006F210UL)) +#define FM_GPIO_DDR5 *((volatile uint32_t*)(0x4006F214UL)) +#define FM4_GPIO_DDR5 *((volatile uint32_t*)(0x4006F214UL)) +#define FM_GPIO_DDR6 *((volatile uint32_t*)(0x4006F218UL)) +#define FM4_GPIO_DDR6 *((volatile uint32_t*)(0x4006F218UL)) +#define FM_GPIO_DDR7 *((volatile uint32_t*)(0x4006F21CUL)) +#define FM4_GPIO_DDR7 *((volatile uint32_t*)(0x4006F21CUL)) +#define FM_GPIO_DDR8 *((volatile uint32_t*)(0x4006F220UL)) +#define FM4_GPIO_DDR8 *((volatile uint32_t*)(0x4006F220UL)) +#define FM_GPIO_DDR9 *((volatile uint32_t*)(0x4006F224UL)) +#define FM4_GPIO_DDR9 *((volatile uint32_t*)(0x4006F224UL)) +#define FM_GPIO_DDRA *((volatile uint32_t*)(0x4006F228UL)) +#define FM4_GPIO_DDRA *((volatile uint32_t*)(0x4006F228UL)) +#define FM_GPIO_DDRB *((volatile uint32_t*)(0x4006F22CUL)) +#define FM4_GPIO_DDRB *((volatile uint32_t*)(0x4006F22CUL)) +#define FM_GPIO_DDRC *((volatile uint32_t*)(0x4006F230UL)) +#define FM4_GPIO_DDRC *((volatile uint32_t*)(0x4006F230UL)) +#define FM_GPIO_DDRD *((volatile uint32_t*)(0x4006F234UL)) +#define FM4_GPIO_DDRD *((volatile uint32_t*)(0x4006F234UL)) +#define FM_GPIO_DDRE *((volatile uint32_t*)(0x4006F238UL)) +#define FM4_GPIO_DDRE *((volatile uint32_t*)(0x4006F238UL)) +#define FM_GPIO_DDRF *((volatile uint32_t*)(0x4006F23CUL)) +#define FM4_GPIO_DDRF *((volatile uint32_t*)(0x4006F23CUL)) +#define FM_GPIO_PDIR0 *((volatile uint32_t*)(0x4006F300UL)) +#define FM4_GPIO_PDIR0 *((volatile uint32_t*)(0x4006F300UL)) +#define FM_GPIO_PDIR1 *((volatile uint32_t*)(0x4006F304UL)) +#define FM4_GPIO_PDIR1 *((volatile uint32_t*)(0x4006F304UL)) +#define FM_GPIO_PDIR2 *((volatile uint32_t*)(0x4006F308UL)) +#define FM4_GPIO_PDIR2 *((volatile uint32_t*)(0x4006F308UL)) +#define FM_GPIO_PDIR3 *((volatile uint32_t*)(0x4006F30CUL)) +#define FM4_GPIO_PDIR3 *((volatile uint32_t*)(0x4006F30CUL)) +#define FM_GPIO_PDIR4 *((volatile uint32_t*)(0x4006F310UL)) +#define FM4_GPIO_PDIR4 *((volatile uint32_t*)(0x4006F310UL)) +#define FM_GPIO_PDIR5 *((volatile uint32_t*)(0x4006F314UL)) +#define FM4_GPIO_PDIR5 *((volatile uint32_t*)(0x4006F314UL)) +#define FM_GPIO_PDIR6 *((volatile uint32_t*)(0x4006F318UL)) +#define FM4_GPIO_PDIR6 *((volatile uint32_t*)(0x4006F318UL)) +#define FM_GPIO_PDIR7 *((volatile uint32_t*)(0x4006F31CUL)) +#define FM4_GPIO_PDIR7 *((volatile uint32_t*)(0x4006F31CUL)) +#define FM_GPIO_PDIR8 *((volatile uint32_t*)(0x4006F320UL)) +#define FM4_GPIO_PDIR8 *((volatile uint32_t*)(0x4006F320UL)) +#define FM_GPIO_PDIR9 *((volatile uint32_t*)(0x4006F324UL)) +#define FM4_GPIO_PDIR9 *((volatile uint32_t*)(0x4006F324UL)) +#define FM_GPIO_PDIRA *((volatile uint32_t*)(0x4006F328UL)) +#define FM4_GPIO_PDIRA *((volatile uint32_t*)(0x4006F328UL)) +#define FM_GPIO_PDIRB *((volatile uint32_t*)(0x4006F32CUL)) +#define FM4_GPIO_PDIRB *((volatile uint32_t*)(0x4006F32CUL)) +#define FM_GPIO_PDIRC *((volatile uint32_t*)(0x4006F330UL)) +#define FM4_GPIO_PDIRC *((volatile uint32_t*)(0x4006F330UL)) +#define FM_GPIO_PDIRD *((volatile uint32_t*)(0x4006F334UL)) +#define FM4_GPIO_PDIRD *((volatile uint32_t*)(0x4006F334UL)) +#define FM_GPIO_PDIRE *((volatile uint32_t*)(0x4006F338UL)) +#define FM4_GPIO_PDIRE *((volatile uint32_t*)(0x4006F338UL)) +#define FM_GPIO_PDIRF *((volatile uint32_t*)(0x4006F33CUL)) +#define FM4_GPIO_PDIRF *((volatile uint32_t*)(0x4006F33CUL)) +#define FM_GPIO_PDOR0 *((volatile uint32_t*)(0x4006F400UL)) +#define FM4_GPIO_PDOR0 *((volatile uint32_t*)(0x4006F400UL)) +#define FM_GPIO_PDOR1 *((volatile uint32_t*)(0x4006F404UL)) +#define FM4_GPIO_PDOR1 *((volatile uint32_t*)(0x4006F404UL)) +#define FM_GPIO_PDOR2 *((volatile uint32_t*)(0x4006F408UL)) +#define FM4_GPIO_PDOR2 *((volatile uint32_t*)(0x4006F408UL)) +#define FM_GPIO_PDOR3 *((volatile uint32_t*)(0x4006F40CUL)) +#define FM4_GPIO_PDOR3 *((volatile uint32_t*)(0x4006F40CUL)) +#define FM_GPIO_PDOR4 *((volatile uint32_t*)(0x4006F410UL)) +#define FM4_GPIO_PDOR4 *((volatile uint32_t*)(0x4006F410UL)) +#define FM_GPIO_PDOR5 *((volatile uint32_t*)(0x4006F414UL)) +#define FM4_GPIO_PDOR5 *((volatile uint32_t*)(0x4006F414UL)) +#define FM_GPIO_PDOR6 *((volatile uint32_t*)(0x4006F418UL)) +#define FM4_GPIO_PDOR6 *((volatile uint32_t*)(0x4006F418UL)) +#define FM_GPIO_PDOR7 *((volatile uint32_t*)(0x4006F41CUL)) +#define FM4_GPIO_PDOR7 *((volatile uint32_t*)(0x4006F41CUL)) +#define FM_GPIO_PDOR8 *((volatile uint32_t*)(0x4006F420UL)) +#define FM4_GPIO_PDOR8 *((volatile uint32_t*)(0x4006F420UL)) +#define FM_GPIO_PDOR9 *((volatile uint32_t*)(0x4006F424UL)) +#define FM4_GPIO_PDOR9 *((volatile uint32_t*)(0x4006F424UL)) +#define FM_GPIO_PDORA *((volatile uint32_t*)(0x4006F428UL)) +#define FM4_GPIO_PDORA *((volatile uint32_t*)(0x4006F428UL)) +#define FM_GPIO_PDORB *((volatile uint32_t*)(0x4006F42CUL)) +#define FM4_GPIO_PDORB *((volatile uint32_t*)(0x4006F42CUL)) +#define FM_GPIO_PDORC *((volatile uint32_t*)(0x4006F430UL)) +#define FM4_GPIO_PDORC *((volatile uint32_t*)(0x4006F430UL)) +#define FM_GPIO_PDORD *((volatile uint32_t*)(0x4006F434UL)) +#define FM4_GPIO_PDORD *((volatile uint32_t*)(0x4006F434UL)) +#define FM_GPIO_PDORE *((volatile uint32_t*)(0x4006F438UL)) +#define FM4_GPIO_PDORE *((volatile uint32_t*)(0x4006F438UL)) +#define FM_GPIO_PDORF *((volatile uint32_t*)(0x4006F43CUL)) +#define FM4_GPIO_PDORF *((volatile uint32_t*)(0x4006F43CUL)) +#define FM_GPIO_ADE *((volatile uint32_t*)(0x4006F500UL)) +#define FM4_GPIO_ADE *((volatile uint32_t*)(0x4006F500UL)) +#define FM_GPIO_SPSR *((volatile uint32_t*)(0x4006F580UL)) +#define FM4_GPIO_SPSR *((volatile uint32_t*)(0x4006F580UL)) +#define FM_GPIO_EPFR00 *((volatile uint32_t*)(0x4006F600UL)) +#define FM4_GPIO_EPFR00 *((volatile uint32_t*)(0x4006F600UL)) +#define FM_GPIO_EPFR01 *((volatile uint32_t*)(0x4006F604UL)) +#define FM4_GPIO_EPFR01 *((volatile uint32_t*)(0x4006F604UL)) +#define FM_GPIO_EPFR02 *((volatile uint32_t*)(0x4006F608UL)) +#define FM4_GPIO_EPFR02 *((volatile uint32_t*)(0x4006F608UL)) +#define FM_GPIO_EPFR03 *((volatile uint32_t*)(0x4006F60CUL)) +#define FM4_GPIO_EPFR03 *((volatile uint32_t*)(0x4006F60CUL)) +#define FM_GPIO_EPFR04 *((volatile uint32_t*)(0x4006F610UL)) +#define FM4_GPIO_EPFR04 *((volatile uint32_t*)(0x4006F610UL)) +#define FM_GPIO_EPFR05 *((volatile uint32_t*)(0x4006F614UL)) +#define FM4_GPIO_EPFR05 *((volatile uint32_t*)(0x4006F614UL)) +#define FM_GPIO_EPFR06 *((volatile uint32_t*)(0x4006F618UL)) +#define FM4_GPIO_EPFR06 *((volatile uint32_t*)(0x4006F618UL)) +#define FM_GPIO_EPFR07 *((volatile uint32_t*)(0x4006F61CUL)) +#define FM4_GPIO_EPFR07 *((volatile uint32_t*)(0x4006F61CUL)) +#define FM_GPIO_EPFR08 *((volatile uint32_t*)(0x4006F620UL)) +#define FM4_GPIO_EPFR08 *((volatile uint32_t*)(0x4006F620UL)) +#define FM_GPIO_EPFR09 *((volatile uint32_t*)(0x4006F624UL)) +#define FM4_GPIO_EPFR09 *((volatile uint32_t*)(0x4006F624UL)) +#define FM_GPIO_EPFR10 *((volatile uint32_t*)(0x4006F628UL)) +#define FM4_GPIO_EPFR10 *((volatile uint32_t*)(0x4006F628UL)) +#define FM_GPIO_EPFR11 *((volatile uint32_t*)(0x4006F62CUL)) +#define FM4_GPIO_EPFR11 *((volatile uint32_t*)(0x4006F62CUL)) +#define FM_GPIO_EPFR12 *((volatile uint32_t*)(0x4006F630UL)) +#define FM4_GPIO_EPFR12 *((volatile uint32_t*)(0x4006F630UL)) +#define FM_GPIO_EPFR13 *((volatile uint32_t*)(0x4006F634UL)) +#define FM4_GPIO_EPFR13 *((volatile uint32_t*)(0x4006F634UL)) +#define FM_GPIO_EPFR14 *((volatile uint32_t*)(0x4006F638UL)) +#define FM4_GPIO_EPFR14 *((volatile uint32_t*)(0x4006F638UL)) +#define FM_GPIO_EPFR15 *((volatile uint32_t*)(0x4006F63CUL)) +#define FM4_GPIO_EPFR15 *((volatile uint32_t*)(0x4006F63CUL)) +#define FM_GPIO_EPFR16 *((volatile uint32_t*)(0x4006F640UL)) +#define FM4_GPIO_EPFR16 *((volatile uint32_t*)(0x4006F640UL)) +#define FM_GPIO_EPFR17 *((volatile uint32_t*)(0x4006F644UL)) +#define FM4_GPIO_EPFR17 *((volatile uint32_t*)(0x4006F644UL)) +#define FM_GPIO_EPFR18 *((volatile uint32_t*)(0x4006F648UL)) +#define FM4_GPIO_EPFR18 *((volatile uint32_t*)(0x4006F648UL)) +#define FM_GPIO_EPFR19 *((volatile uint32_t*)(0x4006F64CUL)) +#define FM4_GPIO_EPFR19 *((volatile uint32_t*)(0x4006F64CUL)) +#define FM_GPIO_EPFR20 *((volatile uint32_t*)(0x4006F650UL)) +#define FM4_GPIO_EPFR20 *((volatile uint32_t*)(0x4006F650UL)) +#define FM_GPIO_EPFR21 *((volatile uint32_t*)(0x4006F654UL)) +#define FM4_GPIO_EPFR21 *((volatile uint32_t*)(0x4006F654UL)) +#define FM_GPIO_EPFR22 *((volatile uint32_t*)(0x4006F658UL)) +#define FM4_GPIO_EPFR22 *((volatile uint32_t*)(0x4006F658UL)) +#define FM_GPIO_EPFR23 *((volatile uint32_t*)(0x4006F65CUL)) +#define FM4_GPIO_EPFR23 *((volatile uint32_t*)(0x4006F65CUL)) +#define FM_GPIO_EPFR24 *((volatile uint32_t*)(0x4006F660UL)) +#define FM4_GPIO_EPFR24 *((volatile uint32_t*)(0x4006F660UL)) +#define FM_GPIO_EPFR25 *((volatile uint32_t*)(0x4006F664UL)) +#define FM4_GPIO_EPFR25 *((volatile uint32_t*)(0x4006F664UL)) +#define FM_GPIO_EPFR26 *((volatile uint32_t*)(0x4006F668UL)) +#define FM4_GPIO_EPFR26 *((volatile uint32_t*)(0x4006F668UL)) +#define FM_GPIO_PZR0 *((volatile uint32_t*)(0x4006F700UL)) +#define FM4_GPIO_PZR0 *((volatile uint32_t*)(0x4006F700UL)) +#define FM_GPIO_PZR1 *((volatile uint32_t*)(0x4006F704UL)) +#define FM4_GPIO_PZR1 *((volatile uint32_t*)(0x4006F704UL)) +#define FM_GPIO_PZR2 *((volatile uint32_t*)(0x4006F708UL)) +#define FM4_GPIO_PZR2 *((volatile uint32_t*)(0x4006F708UL)) +#define FM_GPIO_PZR3 *((volatile uint32_t*)(0x4006F70CUL)) +#define FM4_GPIO_PZR3 *((volatile uint32_t*)(0x4006F70CUL)) +#define FM_GPIO_PZR4 *((volatile uint32_t*)(0x4006F710UL)) +#define FM4_GPIO_PZR4 *((volatile uint32_t*)(0x4006F710UL)) +#define FM_GPIO_PZR5 *((volatile uint32_t*)(0x4006F714UL)) +#define FM4_GPIO_PZR5 *((volatile uint32_t*)(0x4006F714UL)) +#define FM_GPIO_PZR6 *((volatile uint32_t*)(0x4006F718UL)) +#define FM4_GPIO_PZR6 *((volatile uint32_t*)(0x4006F718UL)) +#define FM_GPIO_PZR7 *((volatile uint32_t*)(0x4006F71CUL)) +#define FM4_GPIO_PZR7 *((volatile uint32_t*)(0x4006F71CUL)) +#define FM_GPIO_PZR8 *((volatile uint32_t*)(0x4006F720UL)) +#define FM4_GPIO_PZR8 *((volatile uint32_t*)(0x4006F720UL)) +#define FM_GPIO_PZR9 *((volatile uint32_t*)(0x4006F724UL)) +#define FM4_GPIO_PZR9 *((volatile uint32_t*)(0x4006F724UL)) +#define FM_GPIO_PZRA *((volatile uint32_t*)(0x4006F728UL)) +#define FM4_GPIO_PZRA *((volatile uint32_t*)(0x4006F728UL)) +#define FM_GPIO_PZRB *((volatile uint32_t*)(0x4006F72CUL)) +#define FM4_GPIO_PZRB *((volatile uint32_t*)(0x4006F72CUL)) +#define FM_GPIO_PZRC *((volatile uint32_t*)(0x4006F730UL)) +#define FM4_GPIO_PZRC *((volatile uint32_t*)(0x4006F730UL)) +#define FM_GPIO_PZRD *((volatile uint32_t*)(0x4006F734UL)) +#define FM4_GPIO_PZRD *((volatile uint32_t*)(0x4006F734UL)) +#define FM_GPIO_PZRE *((volatile uint32_t*)(0x4006F738UL)) +#define FM4_GPIO_PZRE *((volatile uint32_t*)(0x4006F738UL)) +#define FM_GPIO_PZRF *((volatile uint32_t*)(0x4006F73CUL)) +#define FM4_GPIO_PZRF *((volatile uint32_t*)(0x4006F73CUL)) +#define FM_GPIO_PDSR0 *((volatile uint32_t*)(0x4006F740UL)) +#define FM4_GPIO_PDSR0 *((volatile uint32_t*)(0x4006F740UL)) +#define FM_GPIO_PDSR1 *((volatile uint32_t*)(0x4006F744UL)) +#define FM4_GPIO_PDSR1 *((volatile uint32_t*)(0x4006F744UL)) +#define FM_GPIO_PDSR2 *((volatile uint32_t*)(0x4006F748UL)) +#define FM4_GPIO_PDSR2 *((volatile uint32_t*)(0x4006F748UL)) +#define FM_GPIO_PDSR3 *((volatile uint32_t*)(0x4006F74CUL)) +#define FM4_GPIO_PDSR3 *((volatile uint32_t*)(0x4006F74CUL)) +#define FM_GPIO_PDSR4 *((volatile uint32_t*)(0x4006F750UL)) +#define FM4_GPIO_PDSR4 *((volatile uint32_t*)(0x4006F750UL)) +#define FM_GPIO_PDSR5 *((volatile uint32_t*)(0x4006F754UL)) +#define FM4_GPIO_PDSR5 *((volatile uint32_t*)(0x4006F754UL)) +#define FM_GPIO_PDSR6 *((volatile uint32_t*)(0x4006F758UL)) +#define FM4_GPIO_PDSR6 *((volatile uint32_t*)(0x4006F758UL)) +#define FM_GPIO_PDSR7 *((volatile uint32_t*)(0x4006F75CUL)) +#define FM4_GPIO_PDSR7 *((volatile uint32_t*)(0x4006F75CUL)) +#define FM_GPIO_PDSR8 *((volatile uint32_t*)(0x4006F760UL)) +#define FM4_GPIO_PDSR8 *((volatile uint32_t*)(0x4006F760UL)) +#define FM_GPIO_PDSR9 *((volatile uint32_t*)(0x4006F764UL)) +#define FM4_GPIO_PDSR9 *((volatile uint32_t*)(0x4006F764UL)) +#define FM_GPIO_PDSRA *((volatile uint32_t*)(0x4006F768UL)) +#define FM4_GPIO_PDSRA *((volatile uint32_t*)(0x4006F768UL)) +#define FM_GPIO_PDSRB *((volatile uint32_t*)(0x4006F76CUL)) +#define FM4_GPIO_PDSRB *((volatile uint32_t*)(0x4006F76CUL)) +#define FM_GPIO_PDSRC *((volatile uint32_t*)(0x4006F770UL)) +#define FM4_GPIO_PDSRC *((volatile uint32_t*)(0x4006F770UL)) +#define FM_GPIO_PDSRD *((volatile uint32_t*)(0x4006F774UL)) +#define FM4_GPIO_PDSRD *((volatile uint32_t*)(0x4006F774UL)) +#define FM_GPIO_PDSRE *((volatile uint32_t*)(0x4006F778UL)) +#define FM4_GPIO_PDSRE *((volatile uint32_t*)(0x4006F778UL)) +#define FM_GPIO_PDSRF *((volatile uint32_t*)(0x4006F77CUL)) +#define FM4_GPIO_PDSRF *((volatile uint32_t*)(0x4006F77CUL)) + +/******************************************************************************* +* HSSPI Registers HSSPI +* Register Definition +*******************************************************************************/ +#define FM_HSSPI_MCTRL *((volatile uint32_t*)(0xD0000000UL)) +#define FM4_HSSPI_MCTRL *((volatile uint32_t*)(0xD0000000UL)) +#define FM_HSSPI_PCC0 *((volatile uint32_t*)(0xD0000004UL)) +#define FM4_HSSPI_PCC0 *((volatile uint32_t*)(0xD0000004UL)) +#define FM_HSSPI_PCC1 *((volatile uint32_t*)(0xD0000008UL)) +#define FM4_HSSPI_PCC1 *((volatile uint32_t*)(0xD0000008UL)) +#define FM_HSSPI_PCC2 *((volatile uint32_t*)(0xD000000CUL)) +#define FM4_HSSPI_PCC2 *((volatile uint32_t*)(0xD000000CUL)) +#define FM_HSSPI_PCC3 *((volatile uint32_t*)(0xD0000010UL)) +#define FM4_HSSPI_PCC3 *((volatile uint32_t*)(0xD0000010UL)) +#define FM_HSSPI_TXF *((volatile uint32_t*)(0xD0000014UL)) +#define FM4_HSSPI_TXF *((volatile uint32_t*)(0xD0000014UL)) +#define FM_HSSPI_TXE *((volatile uint32_t*)(0xD0000018UL)) +#define FM4_HSSPI_TXE *((volatile uint32_t*)(0xD0000018UL)) +#define FM_HSSPI_TXC *((volatile uint32_t*)(0xD000001CUL)) +#define FM4_HSSPI_TXC *((volatile uint32_t*)(0xD000001CUL)) +#define FM_HSSPI_RXF *((volatile uint32_t*)(0xD0000020UL)) +#define FM4_HSSPI_RXF *((volatile uint32_t*)(0xD0000020UL)) +#define FM_HSSPI_RXE *((volatile uint32_t*)(0xD0000024UL)) +#define FM4_HSSPI_RXE *((volatile uint32_t*)(0xD0000024UL)) +#define FM_HSSPI_RXC *((volatile uint32_t*)(0xD0000028UL)) +#define FM4_HSSPI_RXC *((volatile uint32_t*)(0xD0000028UL)) +#define FM_HSSPI_FAULTF *((volatile uint32_t*)(0xD000002CUL)) +#define FM4_HSSPI_FAULTF *((volatile uint32_t*)(0xD000002CUL)) +#define FM_HSSPI_FAULTC *((volatile uint32_t*)(0xD0000030UL)) +#define FM4_HSSPI_FAULTC *((volatile uint32_t*)(0xD0000030UL)) +#define FM_HSSPI_DMCFG *((volatile uint8_t*)(0xD0000034UL)) +#define FM4_HSSPI_DMCFG *((volatile uint8_t*)(0xD0000034UL)) +#define FM_HSSPI_DMDMAEN *((volatile uint8_t*)(0xD0000035UL)) +#define FM4_HSSPI_DMDMAEN *((volatile uint8_t*)(0xD0000035UL)) +#define FM_HSSPI_DMSTART *((volatile uint8_t*)(0xD0000038UL)) +#define FM4_HSSPI_DMSTART *((volatile uint8_t*)(0xD0000038UL)) +#define FM_HSSPI_DMSTOP *((volatile uint8_t*)(0xD0000039UL)) +#define FM4_HSSPI_DMSTOP *((volatile uint8_t*)(0xD0000039UL)) +#define FM_HSSPI_DMPSEL *((volatile uint8_t*)(0xD000003AUL)) +#define FM4_HSSPI_DMPSEL *((volatile uint8_t*)(0xD000003AUL)) +#define FM_HSSPI_DMTRP *((volatile uint8_t*)(0xD000003BUL)) +#define FM4_HSSPI_DMTRP *((volatile uint8_t*)(0xD000003BUL)) +#define FM_HSSPI_DMBCC *((volatile uint16_t*)(0xD000003CUL)) +#define FM4_HSSPI_DMBCC *((volatile uint16_t*)(0xD000003CUL)) +#define FM_HSSPI_DMBCS *((volatile uint16_t*)(0xD000003EUL)) +#define FM4_HSSPI_DMBCS *((volatile uint16_t*)(0xD000003EUL)) +#define FM_HSSPI_DMSTATUS *((volatile uint32_t*)(0xD0000040UL)) +#define FM4_HSSPI_DMSTATUS *((volatile uint32_t*)(0xD0000040UL)) +#define FM_HSSPI_FIFOCFG *((volatile uint32_t*)(0xD000004CUL)) +#define FM4_HSSPI_FIFOCFG *((volatile uint32_t*)(0xD000004CUL)) +#define FM_HSSPI_TXFIFO0 *((volatile uint32_t*)(0xD0000050UL)) +#define FM4_HSSPI_TXFIFO0 *((volatile uint32_t*)(0xD0000050UL)) +#define FM_HSSPI_TXFIFO1 *((volatile uint32_t*)(0xD0000054UL)) +#define FM4_HSSPI_TXFIFO1 *((volatile uint32_t*)(0xD0000054UL)) +#define FM_HSSPI_TXFIFO2 *((volatile uint32_t*)(0xD0000058UL)) +#define FM4_HSSPI_TXFIFO2 *((volatile uint32_t*)(0xD0000058UL)) +#define FM_HSSPI_TXFIFO3 *((volatile uint32_t*)(0xD000005CUL)) +#define FM4_HSSPI_TXFIFO3 *((volatile uint32_t*)(0xD000005CUL)) +#define FM_HSSPI_TXFIFO4 *((volatile uint32_t*)(0xD0000060UL)) +#define FM4_HSSPI_TXFIFO4 *((volatile uint32_t*)(0xD0000060UL)) +#define FM_HSSPI_TXFIFO5 *((volatile uint32_t*)(0xD0000064UL)) +#define FM4_HSSPI_TXFIFO5 *((volatile uint32_t*)(0xD0000064UL)) +#define FM_HSSPI_TXFIFO6 *((volatile uint32_t*)(0xD0000068UL)) +#define FM4_HSSPI_TXFIFO6 *((volatile uint32_t*)(0xD0000068UL)) +#define FM_HSSPI_TXFIFO7 *((volatile uint32_t*)(0xD000006CUL)) +#define FM4_HSSPI_TXFIFO7 *((volatile uint32_t*)(0xD000006CUL)) +#define FM_HSSPI_TXFIFO8 *((volatile uint32_t*)(0xD0000070UL)) +#define FM4_HSSPI_TXFIFO8 *((volatile uint32_t*)(0xD0000070UL)) +#define FM_HSSPI_TXFIFO9 *((volatile uint32_t*)(0xD0000074UL)) +#define FM4_HSSPI_TXFIFO9 *((volatile uint32_t*)(0xD0000074UL)) +#define FM_HSSPI_TXFIFO10 *((volatile uint32_t*)(0xD0000078UL)) +#define FM4_HSSPI_TXFIFO10 *((volatile uint32_t*)(0xD0000078UL)) +#define FM_HSSPI_TXFIFO11 *((volatile uint32_t*)(0xD000007CUL)) +#define FM4_HSSPI_TXFIFO11 *((volatile uint32_t*)(0xD000007CUL)) +#define FM_HSSPI_TXFIFO12 *((volatile uint32_t*)(0xD0000080UL)) +#define FM4_HSSPI_TXFIFO12 *((volatile uint32_t*)(0xD0000080UL)) +#define FM_HSSPI_TXFIFO13 *((volatile uint32_t*)(0xD0000084UL)) +#define FM4_HSSPI_TXFIFO13 *((volatile uint32_t*)(0xD0000084UL)) +#define FM_HSSPI_TXFIFO14 *((volatile uint32_t*)(0xD0000088UL)) +#define FM4_HSSPI_TXFIFO14 *((volatile uint32_t*)(0xD0000088UL)) +#define FM_HSSPI_TXFIFO15 *((volatile uint32_t*)(0xD000008CUL)) +#define FM4_HSSPI_TXFIFO15 *((volatile uint32_t*)(0xD000008CUL)) +#define FM_HSSPI_RXFIFO0 *((volatile uint32_t*)(0xD0000090UL)) +#define FM4_HSSPI_RXFIFO0 *((volatile uint32_t*)(0xD0000090UL)) +#define FM_HSSPI_RXFIFO1 *((volatile uint32_t*)(0xD0000094UL)) +#define FM4_HSSPI_RXFIFO1 *((volatile uint32_t*)(0xD0000094UL)) +#define FM_HSSPI_RXFIFO2 *((volatile uint32_t*)(0xD0000098UL)) +#define FM4_HSSPI_RXFIFO2 *((volatile uint32_t*)(0xD0000098UL)) +#define FM_HSSPI_RXFIFO3 *((volatile uint32_t*)(0xD000009CUL)) +#define FM4_HSSPI_RXFIFO3 *((volatile uint32_t*)(0xD000009CUL)) +#define FM_HSSPI_RXFIFO4 *((volatile uint32_t*)(0xD00000A0UL)) +#define FM4_HSSPI_RXFIFO4 *((volatile uint32_t*)(0xD00000A0UL)) +#define FM_HSSPI_RXFIFO5 *((volatile uint32_t*)(0xD00000A4UL)) +#define FM4_HSSPI_RXFIFO5 *((volatile uint32_t*)(0xD00000A4UL)) +#define FM_HSSPI_RXFIFO6 *((volatile uint32_t*)(0xD00000A8UL)) +#define FM4_HSSPI_RXFIFO6 *((volatile uint32_t*)(0xD00000A8UL)) +#define FM_HSSPI_RXFIFO7 *((volatile uint32_t*)(0xD00000ACUL)) +#define FM4_HSSPI_RXFIFO7 *((volatile uint32_t*)(0xD00000ACUL)) +#define FM_HSSPI_RXFIFO8 *((volatile uint32_t*)(0xD00000B0UL)) +#define FM4_HSSPI_RXFIFO8 *((volatile uint32_t*)(0xD00000B0UL)) +#define FM_HSSPI_RXFIFO9 *((volatile uint32_t*)(0xD00000B4UL)) +#define FM4_HSSPI_RXFIFO9 *((volatile uint32_t*)(0xD00000B4UL)) +#define FM_HSSPI_RXFIFO10 *((volatile uint32_t*)(0xD00000B8UL)) +#define FM4_HSSPI_RXFIFO10 *((volatile uint32_t*)(0xD00000B8UL)) +#define FM_HSSPI_RXFIFO11 *((volatile uint32_t*)(0xD00000BCUL)) +#define FM4_HSSPI_RXFIFO11 *((volatile uint32_t*)(0xD00000BCUL)) +#define FM_HSSPI_RXFIFO12 *((volatile uint32_t*)(0xD00000C0UL)) +#define FM4_HSSPI_RXFIFO12 *((volatile uint32_t*)(0xD00000C0UL)) +#define FM_HSSPI_RXFIFO13 *((volatile uint32_t*)(0xD00000C4UL)) +#define FM4_HSSPI_RXFIFO13 *((volatile uint32_t*)(0xD00000C4UL)) +#define FM_HSSPI_RXFIFO14 *((volatile uint32_t*)(0xD00000C8UL)) +#define FM4_HSSPI_RXFIFO14 *((volatile uint32_t*)(0xD00000C8UL)) +#define FM_HSSPI_RXFIFO15 *((volatile uint32_t*)(0xD00000CCUL)) +#define FM4_HSSPI_RXFIFO15 *((volatile uint32_t*)(0xD00000CCUL)) +#define FM_HSSPI_CSCFG *((volatile uint32_t*)(0xD00000D0UL)) +#define FM4_HSSPI_CSCFG *((volatile uint32_t*)(0xD00000D0UL)) +#define FM_HSSPI_CSITIME *((volatile uint32_t*)(0xD00000D4UL)) +#define FM4_HSSPI_CSITIME *((volatile uint32_t*)(0xD00000D4UL)) +#define FM_HSSPI_CSAEXT *((volatile uint32_t*)(0xD00000D8UL)) +#define FM4_HSSPI_CSAEXT *((volatile uint32_t*)(0xD00000D8UL)) +#define FM_HSSPI_RDCSDC0 *((volatile uint16_t*)(0xD00000DCUL)) +#define FM4_HSSPI_RDCSDC0 *((volatile uint16_t*)(0xD00000DCUL)) +#define FM_HSSPI_RDCSDC1 *((volatile uint16_t*)(0xD00000DEUL)) +#define FM4_HSSPI_RDCSDC1 *((volatile uint16_t*)(0xD00000DEUL)) +#define FM_HSSPI_RDCSDC2 *((volatile uint16_t*)(0xD00000E0UL)) +#define FM4_HSSPI_RDCSDC2 *((volatile uint16_t*)(0xD00000E0UL)) +#define FM_HSSPI_RDCSDC3 *((volatile uint16_t*)(0xD00000E2UL)) +#define FM4_HSSPI_RDCSDC3 *((volatile uint16_t*)(0xD00000E2UL)) +#define FM_HSSPI_RDCSDC4 *((volatile uint16_t*)(0xD00000E4UL)) +#define FM4_HSSPI_RDCSDC4 *((volatile uint16_t*)(0xD00000E4UL)) +#define FM_HSSPI_RDCSDC5 *((volatile uint16_t*)(0xD00000E6UL)) +#define FM4_HSSPI_RDCSDC5 *((volatile uint16_t*)(0xD00000E6UL)) +#define FM_HSSPI_RDCSDC6 *((volatile uint16_t*)(0xD00000E8UL)) +#define FM4_HSSPI_RDCSDC6 *((volatile uint16_t*)(0xD00000E8UL)) +#define FM_HSSPI_RDCSDC7 *((volatile uint16_t*)(0xD00000EAUL)) +#define FM4_HSSPI_RDCSDC7 *((volatile uint16_t*)(0xD00000EAUL)) +#define FM_HSSPI_WRCSDC0 *((volatile uint16_t*)(0xD00000ECUL)) +#define FM4_HSSPI_WRCSDC0 *((volatile uint16_t*)(0xD00000ECUL)) +#define FM_HSSPI_WRCSDC1 *((volatile uint16_t*)(0xD00000EEUL)) +#define FM4_HSSPI_WRCSDC1 *((volatile uint16_t*)(0xD00000EEUL)) +#define FM_HSSPI_WRCSDC2 *((volatile uint16_t*)(0xD00000F0UL)) +#define FM4_HSSPI_WRCSDC2 *((volatile uint16_t*)(0xD00000F0UL)) +#define FM_HSSPI_WRCSDC3 *((volatile uint16_t*)(0xD00000F2UL)) +#define FM4_HSSPI_WRCSDC3 *((volatile uint16_t*)(0xD00000F2UL)) +#define FM_HSSPI_WRCSDC4 *((volatile uint16_t*)(0xD00000F4UL)) +#define FM4_HSSPI_WRCSDC4 *((volatile uint16_t*)(0xD00000F4UL)) +#define FM_HSSPI_WRCSDC5 *((volatile uint16_t*)(0xD00000F6UL)) +#define FM4_HSSPI_WRCSDC5 *((volatile uint16_t*)(0xD00000F6UL)) +#define FM_HSSPI_WRCSDC6 *((volatile uint16_t*)(0xD00000F8UL)) +#define FM4_HSSPI_WRCSDC6 *((volatile uint16_t*)(0xD00000F8UL)) +#define FM_HSSPI_WRCSDC7 *((volatile uint16_t*)(0xD00000FAUL)) +#define FM4_HSSPI_WRCSDC7 *((volatile uint16_t*)(0xD00000FAUL)) +#define FM_HSSPI_MID *((volatile uint32_t*)(0xD00000FCUL)) +#define FM4_HSSPI_MID *((volatile uint32_t*)(0xD00000FCUL)) +#define FM_HSSPI_QDCLKR *((volatile uint8_t*)(0xD0000400UL)) +#define FM4_HSSPI_QDCLKR *((volatile uint8_t*)(0xD0000400UL)) +#define FM_HSSPI_DBCNT *((volatile uint8_t*)(0xD0000404UL)) +#define FM4_HSSPI_DBCNT *((volatile uint8_t*)(0xD0000404UL)) + +/******************************************************************************* +* HWWDT Registers HWWDT +* Register Definition +*******************************************************************************/ +#define FM_HWWDT_WDG_LDR *((volatile uint32_t*)(0x40011000UL)) +#define FM4_HWWDT_WDG_LDR *((volatile uint32_t*)(0x40011000UL)) +#define FM_HWWDT_WDG_VLR *((volatile uint32_t*)(0x40011004UL)) +#define FM4_HWWDT_WDG_VLR *((volatile uint32_t*)(0x40011004UL)) +#define FM_HWWDT_WDG_CTL *((volatile uint32_t*)(0x40011008UL)) +#define FM4_HWWDT_WDG_CTL *((volatile uint32_t*)(0x40011008UL)) +#define FM_HWWDT_WDG_ICL *((volatile uint32_t*)(0x4001100CUL)) +#define FM4_HWWDT_WDG_ICL *((volatile uint32_t*)(0x4001100CUL)) +#define FM_HWWDT_WDG_RIS *((volatile uint32_t*)(0x40011010UL)) +#define FM4_HWWDT_WDG_RIS *((volatile uint32_t*)(0x40011010UL)) +#define FM_HWWDT_WDG_LCK *((volatile uint32_t*)(0x40011C00UL)) +#define FM4_HWWDT_WDG_LCK *((volatile uint32_t*)(0x40011C00UL)) + +/******************************************************************************* +* I2S Registers I2S0 +* Register Definition +*******************************************************************************/ +#define FM_I2S0_RXFDAT *((volatile uint32_t*)(0x4006C000UL)) +#define FM4_I2S0_RXFDAT *((volatile uint32_t*)(0x4006C000UL)) +#define FM_I2S0_TXFDAT *((volatile uint32_t*)(0x4006C004UL)) +#define FM4_I2S0_TXFDAT *((volatile uint32_t*)(0x4006C004UL)) +#define FM_I2S0_CNTREG *((volatile uint32_t*)(0x4006C008UL)) +#define FM4_I2S0_CNTREG *((volatile uint32_t*)(0x4006C008UL)) +#define FM_I2S0_MCR0REG *((volatile uint32_t*)(0x4006C00CUL)) +#define FM4_I2S0_MCR0REG *((volatile uint32_t*)(0x4006C00CUL)) +#define FM_I2S0_MCR1REG *((volatile uint32_t*)(0x4006C010UL)) +#define FM4_I2S0_MCR1REG *((volatile uint32_t*)(0x4006C010UL)) +#define FM_I2S0_MCR2REG *((volatile uint32_t*)(0x4006C014UL)) +#define FM4_I2S0_MCR2REG *((volatile uint32_t*)(0x4006C014UL)) +#define FM_I2S0_OPRREG *((volatile uint32_t*)(0x4006C018UL)) +#define FM4_I2S0_OPRREG *((volatile uint32_t*)(0x4006C018UL)) +#define FM_I2S0_SRST *((volatile uint32_t*)(0x4006C01CUL)) +#define FM4_I2S0_SRST *((volatile uint32_t*)(0x4006C01CUL)) +#define FM_I2S0_INTCNT *((volatile uint32_t*)(0x4006C020UL)) +#define FM4_I2S0_INTCNT *((volatile uint32_t*)(0x4006C020UL)) +#define FM_I2S0_STATUS *((volatile uint32_t*)(0x4006C024UL)) +#define FM4_I2S0_STATUS *((volatile uint32_t*)(0x4006C024UL)) +#define FM_I2S0_DMAACT *((volatile uint32_t*)(0x4006C028UL)) +#define FM4_I2S0_DMAACT *((volatile uint32_t*)(0x4006C028UL)) +#define FM_I2S0_TSTREG *((volatile uint32_t*)(0x4006C02CUL)) +#define FM4_I2S0_TSTREG *((volatile uint32_t*)(0x4006C02CUL)) + +/******************************************************************************* +* I2SPRE Registers I2SPRE +* Register Definition +*******************************************************************************/ +#define FM_I2SPRE_ICCR *((volatile uint32_t*)(0x4003D000UL)) +#define FM4_I2SPRE_ICCR *((volatile uint32_t*)(0x4003D000UL)) +#define FM_I2SPRE_IPCR1 *((volatile uint32_t*)(0x4003D004UL)) +#define FM4_I2SPRE_IPCR1 *((volatile uint32_t*)(0x4003D004UL)) +#define FM_I2SPRE_IPCR2 *((volatile uint32_t*)(0x4003D008UL)) +#define FM4_I2SPRE_IPCR2 *((volatile uint32_t*)(0x4003D008UL)) +#define FM_I2SPRE_IPCR3 *((volatile uint32_t*)(0x4003D00CUL)) +#define FM4_I2SPRE_IPCR3 *((volatile uint32_t*)(0x4003D00CUL)) +#define FM_I2SPRE_IPCR4 *((volatile uint32_t*)(0x4003D010UL)) +#define FM4_I2SPRE_IPCR4 *((volatile uint32_t*)(0x4003D010UL)) +#define FM_I2SPRE_IP_STR *((volatile uint32_t*)(0x4003D014UL)) +#define FM4_I2SPRE_IP_STR *((volatile uint32_t*)(0x4003D014UL)) +#define FM_I2SPRE_IPINT_ENR *((volatile uint32_t*)(0x4003D018UL)) +#define FM4_I2SPRE_IPINT_ENR *((volatile uint32_t*)(0x4003D018UL)) +#define FM_I2SPRE_IPINT_CLR *((volatile uint32_t*)(0x4003D01CUL)) +#define FM4_I2SPRE_IPINT_CLR *((volatile uint32_t*)(0x4003D01CUL)) +#define FM_I2SPRE_IPINT_STR *((volatile uint32_t*)(0x4003D020UL)) +#define FM4_I2SPRE_IPINT_STR *((volatile uint32_t*)(0x4003D020UL)) +#define FM_I2SPRE_IPCR5 *((volatile uint32_t*)(0x4003D024UL)) +#define FM4_I2SPRE_IPCR5 *((volatile uint32_t*)(0x4003D024UL)) + +/******************************************************************************* +* INTREQ Registers INTREQ +* Register Definition +*******************************************************************************/ +#define FM_INTREQ_DRQSEL *((volatile uint32_t*)(0x40031000UL)) +#define FM4_INTREQ_DRQSEL *((volatile uint32_t*)(0x40031000UL)) +#define FM_INTREQ_ODDPKS *((volatile uint8_t*)(0x40031010UL)) +#define FM4_INTREQ_ODDPKS *((volatile uint8_t*)(0x40031010UL)) +#define FM_INTREQ_ODDPKS1 *((volatile uint8_t*)(0x40031014UL)) +#define FM4_INTREQ_ODDPKS1 *((volatile uint8_t*)(0x40031014UL)) +#define FM_INTREQ_IRQ003SEL *((volatile uint32_t*)(0x40031110UL)) +#define FM4_INTREQ_IRQ003SEL *((volatile uint32_t*)(0x40031110UL)) +#define FM_INTREQ_IRQ004SEL *((volatile uint32_t*)(0x40031114UL)) +#define FM4_INTREQ_IRQ004SEL *((volatile uint32_t*)(0x40031114UL)) +#define FM_INTREQ_IRQ005SEL *((volatile uint32_t*)(0x40031118UL)) +#define FM4_INTREQ_IRQ005SEL *((volatile uint32_t*)(0x40031118UL)) +#define FM_INTREQ_IRQ006SEL *((volatile uint32_t*)(0x4003111CUL)) +#define FM4_INTREQ_IRQ006SEL *((volatile uint32_t*)(0x4003111CUL)) +#define FM_INTREQ_IRQ007SEL *((volatile uint32_t*)(0x40031120UL)) +#define FM4_INTREQ_IRQ007SEL *((volatile uint32_t*)(0x40031120UL)) +#define FM_INTREQ_IRQ008SEL *((volatile uint32_t*)(0x40031124UL)) +#define FM4_INTREQ_IRQ008SEL *((volatile uint32_t*)(0x40031124UL)) +#define FM_INTREQ_IRQ009SEL *((volatile uint32_t*)(0x40031128UL)) +#define FM4_INTREQ_IRQ009SEL *((volatile uint32_t*)(0x40031128UL)) +#define FM_INTREQ_IRQ010SEL *((volatile uint32_t*)(0x4003112CUL)) +#define FM4_INTREQ_IRQ010SEL *((volatile uint32_t*)(0x4003112CUL)) +#define FM_INTREQ_EXC02MON *((volatile uint32_t*)(0x40031200UL)) +#define FM4_INTREQ_EXC02MON *((volatile uint32_t*)(0x40031200UL)) +#define FM_INTREQ_IRQ000MON *((volatile uint32_t*)(0x40031204UL)) +#define FM4_INTREQ_IRQ000MON *((volatile uint32_t*)(0x40031204UL)) +#define FM_INTREQ_IRQ001MON *((volatile uint32_t*)(0x40031208UL)) +#define FM4_INTREQ_IRQ001MON *((volatile uint32_t*)(0x40031208UL)) +#define FM_INTREQ_IRQ002MON *((volatile uint32_t*)(0x4003120CUL)) +#define FM4_INTREQ_IRQ002MON *((volatile uint32_t*)(0x4003120CUL)) +#define FM_INTREQ_IRQ003MON *((volatile uint32_t*)(0x40031210UL)) +#define FM4_INTREQ_IRQ003MON *((volatile uint32_t*)(0x40031210UL)) +#define FM_INTREQ_IRQ004MON *((volatile uint32_t*)(0x40031214UL)) +#define FM4_INTREQ_IRQ004MON *((volatile uint32_t*)(0x40031214UL)) +#define FM_INTREQ_IRQ005MON *((volatile uint32_t*)(0x40031218UL)) +#define FM4_INTREQ_IRQ005MON *((volatile uint32_t*)(0x40031218UL)) +#define FM_INTREQ_IRQ006MON *((volatile uint32_t*)(0x4003121CUL)) +#define FM4_INTREQ_IRQ006MON *((volatile uint32_t*)(0x4003121CUL)) +#define FM_INTREQ_IRQ007MON *((volatile uint32_t*)(0x40031220UL)) +#define FM4_INTREQ_IRQ007MON *((volatile uint32_t*)(0x40031220UL)) +#define FM_INTREQ_IRQ008MON *((volatile uint32_t*)(0x40031224UL)) +#define FM4_INTREQ_IRQ008MON *((volatile uint32_t*)(0x40031224UL)) +#define FM_INTREQ_IRQ009MON *((volatile uint32_t*)(0x40031228UL)) +#define FM4_INTREQ_IRQ009MON *((volatile uint32_t*)(0x40031228UL)) +#define FM_INTREQ_IRQ010MON *((volatile uint32_t*)(0x4003122CUL)) +#define FM4_INTREQ_IRQ010MON *((volatile uint32_t*)(0x4003122CUL)) +#define FM_INTREQ_IRQ011MON *((volatile uint32_t*)(0x40031230UL)) +#define FM4_INTREQ_IRQ011MON *((volatile uint32_t*)(0x40031230UL)) +#define FM_INTREQ_IRQ012MON *((volatile uint32_t*)(0x40031234UL)) +#define FM4_INTREQ_IRQ012MON *((volatile uint32_t*)(0x40031234UL)) +#define FM_INTREQ_IRQ013MON *((volatile uint32_t*)(0x40031238UL)) +#define FM4_INTREQ_IRQ013MON *((volatile uint32_t*)(0x40031238UL)) +#define FM_INTREQ_IRQ014MON *((volatile uint32_t*)(0x4003123CUL)) +#define FM4_INTREQ_IRQ014MON *((volatile uint32_t*)(0x4003123CUL)) +#define FM_INTREQ_IRQ015MON *((volatile uint32_t*)(0x40031240UL)) +#define FM4_INTREQ_IRQ015MON *((volatile uint32_t*)(0x40031240UL)) +#define FM_INTREQ_IRQ016MON *((volatile uint32_t*)(0x40031244UL)) +#define FM4_INTREQ_IRQ016MON *((volatile uint32_t*)(0x40031244UL)) +#define FM_INTREQ_IRQ017MON *((volatile uint32_t*)(0x40031248UL)) +#define FM4_INTREQ_IRQ017MON *((volatile uint32_t*)(0x40031248UL)) +#define FM_INTREQ_IRQ018MON *((volatile uint32_t*)(0x4003124CUL)) +#define FM4_INTREQ_IRQ018MON *((volatile uint32_t*)(0x4003124CUL)) +#define FM_INTREQ_IRQ019MON *((volatile uint32_t*)(0x40031250UL)) +#define FM4_INTREQ_IRQ019MON *((volatile uint32_t*)(0x40031250UL)) +#define FM_INTREQ_IRQ020MON *((volatile uint32_t*)(0x40031254UL)) +#define FM4_INTREQ_IRQ020MON *((volatile uint32_t*)(0x40031254UL)) +#define FM_INTREQ_IRQ021MON *((volatile uint32_t*)(0x40031258UL)) +#define FM4_INTREQ_IRQ021MON *((volatile uint32_t*)(0x40031258UL)) +#define FM_INTREQ_IRQ022MON *((volatile uint32_t*)(0x4003125CUL)) +#define FM4_INTREQ_IRQ022MON *((volatile uint32_t*)(0x4003125CUL)) +#define FM_INTREQ_IRQ023MON *((volatile uint32_t*)(0x40031260UL)) +#define FM4_INTREQ_IRQ023MON *((volatile uint32_t*)(0x40031260UL)) +#define FM_INTREQ_IRQ024MON *((volatile uint32_t*)(0x40031264UL)) +#define FM4_INTREQ_IRQ024MON *((volatile uint32_t*)(0x40031264UL)) +#define FM_INTREQ_IRQ025MON *((volatile uint32_t*)(0x40031268UL)) +#define FM4_INTREQ_IRQ025MON *((volatile uint32_t*)(0x40031268UL)) +#define FM_INTREQ_IRQ026MON *((volatile uint32_t*)(0x4003126CUL)) +#define FM4_INTREQ_IRQ026MON *((volatile uint32_t*)(0x4003126CUL)) +#define FM_INTREQ_IRQ027MON *((volatile uint32_t*)(0x40031270UL)) +#define FM4_INTREQ_IRQ027MON *((volatile uint32_t*)(0x40031270UL)) +#define FM_INTREQ_IRQ028MON *((volatile uint32_t*)(0x40031274UL)) +#define FM4_INTREQ_IRQ028MON *((volatile uint32_t*)(0x40031274UL)) +#define FM_INTREQ_IRQ029MON *((volatile uint32_t*)(0x40031278UL)) +#define FM4_INTREQ_IRQ029MON *((volatile uint32_t*)(0x40031278UL)) +#define FM_INTREQ_IRQ030MON *((volatile uint32_t*)(0x4003127CUL)) +#define FM4_INTREQ_IRQ030MON *((volatile uint32_t*)(0x4003127CUL)) +#define FM_INTREQ_IRQ031MON *((volatile uint32_t*)(0x40031280UL)) +#define FM4_INTREQ_IRQ031MON *((volatile uint32_t*)(0x40031280UL)) +#define FM_INTREQ_IRQ032MON *((volatile uint32_t*)(0x40031284UL)) +#define FM4_INTREQ_IRQ032MON *((volatile uint32_t*)(0x40031284UL)) +#define FM_INTREQ_IRQ033MON *((volatile uint32_t*)(0x40031288UL)) +#define FM4_INTREQ_IRQ033MON *((volatile uint32_t*)(0x40031288UL)) +#define FM_INTREQ_IRQ034MON *((volatile uint32_t*)(0x4003128CUL)) +#define FM4_INTREQ_IRQ034MON *((volatile uint32_t*)(0x4003128CUL)) +#define FM_INTREQ_IRQ035MON *((volatile uint32_t*)(0x40031290UL)) +#define FM4_INTREQ_IRQ035MON *((volatile uint32_t*)(0x40031290UL)) +#define FM_INTREQ_IRQ036MON *((volatile uint32_t*)(0x40031294UL)) +#define FM4_INTREQ_IRQ036MON *((volatile uint32_t*)(0x40031294UL)) +#define FM_INTREQ_IRQ037MON *((volatile uint32_t*)(0x40031298UL)) +#define FM4_INTREQ_IRQ037MON *((volatile uint32_t*)(0x40031298UL)) +#define FM_INTREQ_IRQ038MON *((volatile uint32_t*)(0x4003129CUL)) +#define FM4_INTREQ_IRQ038MON *((volatile uint32_t*)(0x4003129CUL)) +#define FM_INTREQ_IRQ039MON *((volatile uint32_t*)(0x400312A0UL)) +#define FM4_INTREQ_IRQ039MON *((volatile uint32_t*)(0x400312A0UL)) +#define FM_INTREQ_IRQ040MON *((volatile uint32_t*)(0x400312A4UL)) +#define FM4_INTREQ_IRQ040MON *((volatile uint32_t*)(0x400312A4UL)) +#define FM_INTREQ_IRQ041MON *((volatile uint32_t*)(0x400312A8UL)) +#define FM4_INTREQ_IRQ041MON *((volatile uint32_t*)(0x400312A8UL)) +#define FM_INTREQ_IRQ042MON *((volatile uint32_t*)(0x400312ACUL)) +#define FM4_INTREQ_IRQ042MON *((volatile uint32_t*)(0x400312ACUL)) +#define FM_INTREQ_IRQ043MON *((volatile uint32_t*)(0x400312B0UL)) +#define FM4_INTREQ_IRQ043MON *((volatile uint32_t*)(0x400312B0UL)) +#define FM_INTREQ_IRQ044MON *((volatile uint32_t*)(0x400312B4UL)) +#define FM4_INTREQ_IRQ044MON *((volatile uint32_t*)(0x400312B4UL)) +#define FM_INTREQ_IRQ045MON *((volatile uint32_t*)(0x400312B8UL)) +#define FM4_INTREQ_IRQ045MON *((volatile uint32_t*)(0x400312B8UL)) +#define FM_INTREQ_IRQ046MON *((volatile uint32_t*)(0x400312BCUL)) +#define FM4_INTREQ_IRQ046MON *((volatile uint32_t*)(0x400312BCUL)) +#define FM_INTREQ_IRQ047MON *((volatile uint32_t*)(0x400312C0UL)) +#define FM4_INTREQ_IRQ047MON *((volatile uint32_t*)(0x400312C0UL)) +#define FM_INTREQ_IRQ048MON *((volatile uint32_t*)(0x400312C4UL)) +#define FM4_INTREQ_IRQ048MON *((volatile uint32_t*)(0x400312C4UL)) +#define FM_INTREQ_IRQ049MON *((volatile uint32_t*)(0x400312C8UL)) +#define FM4_INTREQ_IRQ049MON *((volatile uint32_t*)(0x400312C8UL)) +#define FM_INTREQ_IRQ050MON *((volatile uint32_t*)(0x400312CCUL)) +#define FM4_INTREQ_IRQ050MON *((volatile uint32_t*)(0x400312CCUL)) +#define FM_INTREQ_IRQ051MON *((volatile uint32_t*)(0x400312D0UL)) +#define FM4_INTREQ_IRQ051MON *((volatile uint32_t*)(0x400312D0UL)) +#define FM_INTREQ_IRQ052MON *((volatile uint32_t*)(0x400312D4UL)) +#define FM4_INTREQ_IRQ052MON *((volatile uint32_t*)(0x400312D4UL)) +#define FM_INTREQ_IRQ053MON *((volatile uint32_t*)(0x400312D8UL)) +#define FM4_INTREQ_IRQ053MON *((volatile uint32_t*)(0x400312D8UL)) +#define FM_INTREQ_IRQ054MON *((volatile uint32_t*)(0x400312DCUL)) +#define FM4_INTREQ_IRQ054MON *((volatile uint32_t*)(0x400312DCUL)) +#define FM_INTREQ_IRQ055MON *((volatile uint32_t*)(0x400312E0UL)) +#define FM4_INTREQ_IRQ055MON *((volatile uint32_t*)(0x400312E0UL)) +#define FM_INTREQ_IRQ056MON *((volatile uint32_t*)(0x400312E4UL)) +#define FM4_INTREQ_IRQ056MON *((volatile uint32_t*)(0x400312E4UL)) +#define FM_INTREQ_IRQ057MON *((volatile uint32_t*)(0x400312E8UL)) +#define FM4_INTREQ_IRQ057MON *((volatile uint32_t*)(0x400312E8UL)) +#define FM_INTREQ_IRQ058MON *((volatile uint32_t*)(0x400312ECUL)) +#define FM4_INTREQ_IRQ058MON *((volatile uint32_t*)(0x400312ECUL)) +#define FM_INTREQ_IRQ059MON *((volatile uint32_t*)(0x400312F0UL)) +#define FM4_INTREQ_IRQ059MON *((volatile uint32_t*)(0x400312F0UL)) +#define FM_INTREQ_IRQ060MON *((volatile uint32_t*)(0x400312F4UL)) +#define FM4_INTREQ_IRQ060MON *((volatile uint32_t*)(0x400312F4UL)) +#define FM_INTREQ_IRQ061MON *((volatile uint32_t*)(0x400312F8UL)) +#define FM4_INTREQ_IRQ061MON *((volatile uint32_t*)(0x400312F8UL)) +#define FM_INTREQ_IRQ062MON *((volatile uint32_t*)(0x400312FCUL)) +#define FM4_INTREQ_IRQ062MON *((volatile uint32_t*)(0x400312FCUL)) +#define FM_INTREQ_IRQ063MON *((volatile uint32_t*)(0x40031300UL)) +#define FM4_INTREQ_IRQ063MON *((volatile uint32_t*)(0x40031300UL)) +#define FM_INTREQ_IRQ064MON *((volatile uint32_t*)(0x40031304UL)) +#define FM4_INTREQ_IRQ064MON *((volatile uint32_t*)(0x40031304UL)) +#define FM_INTREQ_IRQ065MON *((volatile uint32_t*)(0x40031308UL)) +#define FM4_INTREQ_IRQ065MON *((volatile uint32_t*)(0x40031308UL)) +#define FM_INTREQ_IRQ066MON *((volatile uint32_t*)(0x4003130CUL)) +#define FM4_INTREQ_IRQ066MON *((volatile uint32_t*)(0x4003130CUL)) +#define FM_INTREQ_IRQ067MON *((volatile uint32_t*)(0x40031310UL)) +#define FM4_INTREQ_IRQ067MON *((volatile uint32_t*)(0x40031310UL)) +#define FM_INTREQ_IRQ068MON *((volatile uint32_t*)(0x40031314UL)) +#define FM4_INTREQ_IRQ068MON *((volatile uint32_t*)(0x40031314UL)) +#define FM_INTREQ_IRQ069MON *((volatile uint32_t*)(0x40031318UL)) +#define FM4_INTREQ_IRQ069MON *((volatile uint32_t*)(0x40031318UL)) +#define FM_INTREQ_IRQ070MON *((volatile uint32_t*)(0x4003131CUL)) +#define FM4_INTREQ_IRQ070MON *((volatile uint32_t*)(0x4003131CUL)) +#define FM_INTREQ_IRQ071MON *((volatile uint32_t*)(0x40031320UL)) +#define FM4_INTREQ_IRQ071MON *((volatile uint32_t*)(0x40031320UL)) +#define FM_INTREQ_IRQ072MON *((volatile uint32_t*)(0x40031324UL)) +#define FM4_INTREQ_IRQ072MON *((volatile uint32_t*)(0x40031324UL)) +#define FM_INTREQ_IRQ073MON *((volatile uint32_t*)(0x40031328UL)) +#define FM4_INTREQ_IRQ073MON *((volatile uint32_t*)(0x40031328UL)) +#define FM_INTREQ_IRQ074MON *((volatile uint32_t*)(0x4003132CUL)) +#define FM4_INTREQ_IRQ074MON *((volatile uint32_t*)(0x4003132CUL)) +#define FM_INTREQ_IRQ075MON *((volatile uint32_t*)(0x40031330UL)) +#define FM4_INTREQ_IRQ075MON *((volatile uint32_t*)(0x40031330UL)) +#define FM_INTREQ_IRQ076MON *((volatile uint32_t*)(0x40031334UL)) +#define FM4_INTREQ_IRQ076MON *((volatile uint32_t*)(0x40031334UL)) +#define FM_INTREQ_IRQ077MON *((volatile uint32_t*)(0x40031338UL)) +#define FM4_INTREQ_IRQ077MON *((volatile uint32_t*)(0x40031338UL)) +#define FM_INTREQ_IRQ078MON *((volatile uint32_t*)(0x4003133CUL)) +#define FM4_INTREQ_IRQ078MON *((volatile uint32_t*)(0x4003133CUL)) +#define FM_INTREQ_IRQ079MON *((volatile uint32_t*)(0x40031340UL)) +#define FM4_INTREQ_IRQ079MON *((volatile uint32_t*)(0x40031340UL)) +#define FM_INTREQ_IRQ080MON *((volatile uint32_t*)(0x40031344UL)) +#define FM4_INTREQ_IRQ080MON *((volatile uint32_t*)(0x40031344UL)) +#define FM_INTREQ_IRQ081MON *((volatile uint32_t*)(0x40031348UL)) +#define FM4_INTREQ_IRQ081MON *((volatile uint32_t*)(0x40031348UL)) +#define FM_INTREQ_IRQ082MON *((volatile uint32_t*)(0x4003134CUL)) +#define FM4_INTREQ_IRQ082MON *((volatile uint32_t*)(0x4003134CUL)) +#define FM_INTREQ_IRQ083MON *((volatile uint32_t*)(0x40031350UL)) +#define FM4_INTREQ_IRQ083MON *((volatile uint32_t*)(0x40031350UL)) +#define FM_INTREQ_IRQ084MON *((volatile uint32_t*)(0x40031354UL)) +#define FM4_INTREQ_IRQ084MON *((volatile uint32_t*)(0x40031354UL)) +#define FM_INTREQ_IRQ085MON *((volatile uint32_t*)(0x40031358UL)) +#define FM4_INTREQ_IRQ085MON *((volatile uint32_t*)(0x40031358UL)) +#define FM_INTREQ_IRQ086MON *((volatile uint32_t*)(0x4003135CUL)) +#define FM4_INTREQ_IRQ086MON *((volatile uint32_t*)(0x4003135CUL)) +#define FM_INTREQ_IRQ087MON *((volatile uint32_t*)(0x40031360UL)) +#define FM4_INTREQ_IRQ087MON *((volatile uint32_t*)(0x40031360UL)) +#define FM_INTREQ_IRQ088MON *((volatile uint32_t*)(0x40031364UL)) +#define FM4_INTREQ_IRQ088MON *((volatile uint32_t*)(0x40031364UL)) +#define FM_INTREQ_IRQ089MON *((volatile uint32_t*)(0x40031368UL)) +#define FM4_INTREQ_IRQ089MON *((volatile uint32_t*)(0x40031368UL)) +#define FM_INTREQ_IRQ090MON *((volatile uint32_t*)(0x4003136CUL)) +#define FM4_INTREQ_IRQ090MON *((volatile uint32_t*)(0x4003136CUL)) +#define FM_INTREQ_IRQ091MON *((volatile uint32_t*)(0x40031370UL)) +#define FM4_INTREQ_IRQ091MON *((volatile uint32_t*)(0x40031370UL)) +#define FM_INTREQ_IRQ092MON *((volatile uint32_t*)(0x40031374UL)) +#define FM4_INTREQ_IRQ092MON *((volatile uint32_t*)(0x40031374UL)) +#define FM_INTREQ_IRQ093MON *((volatile uint32_t*)(0x40031378UL)) +#define FM4_INTREQ_IRQ093MON *((volatile uint32_t*)(0x40031378UL)) +#define FM_INTREQ_IRQ094MON *((volatile uint32_t*)(0x4003137CUL)) +#define FM4_INTREQ_IRQ094MON *((volatile uint32_t*)(0x4003137CUL)) +#define FM_INTREQ_IRQ095MON *((volatile uint32_t*)(0x40031380UL)) +#define FM4_INTREQ_IRQ095MON *((volatile uint32_t*)(0x40031380UL)) +#define FM_INTREQ_IRQ096MON *((volatile uint32_t*)(0x40031384UL)) +#define FM4_INTREQ_IRQ096MON *((volatile uint32_t*)(0x40031384UL)) +#define FM_INTREQ_IRQ097MON *((volatile uint32_t*)(0x40031388UL)) +#define FM4_INTREQ_IRQ097MON *((volatile uint32_t*)(0x40031388UL)) +#define FM_INTREQ_IRQ098MON *((volatile uint32_t*)(0x4003138CUL)) +#define FM4_INTREQ_IRQ098MON *((volatile uint32_t*)(0x4003138CUL)) +#define FM_INTREQ_IRQ099MON *((volatile uint32_t*)(0x40031390UL)) +#define FM4_INTREQ_IRQ099MON *((volatile uint32_t*)(0x40031390UL)) +#define FM_INTREQ_IRQ100MON *((volatile uint32_t*)(0x40031394UL)) +#define FM4_INTREQ_IRQ100MON *((volatile uint32_t*)(0x40031394UL)) +#define FM_INTREQ_IRQ101MON *((volatile uint32_t*)(0x40031398UL)) +#define FM4_INTREQ_IRQ101MON *((volatile uint32_t*)(0x40031398UL)) +#define FM_INTREQ_IRQ102MON *((volatile uint32_t*)(0x4003139CUL)) +#define FM4_INTREQ_IRQ102MON *((volatile uint32_t*)(0x4003139CUL)) +#define FM_INTREQ_IRQ103MON *((volatile uint32_t*)(0x400313A0UL)) +#define FM4_INTREQ_IRQ103MON *((volatile uint32_t*)(0x400313A0UL)) +#define FM_INTREQ_IRQ104MON *((volatile uint32_t*)(0x400313A4UL)) +#define FM4_INTREQ_IRQ104MON *((volatile uint32_t*)(0x400313A4UL)) +#define FM_INTREQ_IRQ105MON *((volatile uint32_t*)(0x400313A8UL)) +#define FM4_INTREQ_IRQ105MON *((volatile uint32_t*)(0x400313A8UL)) +#define FM_INTREQ_IRQ106MON *((volatile uint32_t*)(0x400313ACUL)) +#define FM4_INTREQ_IRQ106MON *((volatile uint32_t*)(0x400313ACUL)) +#define FM_INTREQ_IRQ107MON *((volatile uint32_t*)(0x400313B0UL)) +#define FM4_INTREQ_IRQ107MON *((volatile uint32_t*)(0x400313B0UL)) +#define FM_INTREQ_IRQ108MON *((volatile uint32_t*)(0x400313B4UL)) +#define FM4_INTREQ_IRQ108MON *((volatile uint32_t*)(0x400313B4UL)) +#define FM_INTREQ_IRQ109MON *((volatile uint32_t*)(0x400313B8UL)) +#define FM4_INTREQ_IRQ109MON *((volatile uint32_t*)(0x400313B8UL)) +#define FM_INTREQ_IRQ110MON *((volatile uint32_t*)(0x400313BCUL)) +#define FM4_INTREQ_IRQ110MON *((volatile uint32_t*)(0x400313BCUL)) +#define FM_INTREQ_IRQ111MON *((volatile uint32_t*)(0x400313C0UL)) +#define FM4_INTREQ_IRQ111MON *((volatile uint32_t*)(0x400313C0UL)) +#define FM_INTREQ_IRQ112MON *((volatile uint32_t*)(0x400313C4UL)) +#define FM4_INTREQ_IRQ112MON *((volatile uint32_t*)(0x400313C4UL)) +#define FM_INTREQ_IRQ113MON *((volatile uint32_t*)(0x400313C8UL)) +#define FM4_INTREQ_IRQ113MON *((volatile uint32_t*)(0x400313C8UL)) +#define FM_INTREQ_IRQ114MON *((volatile uint32_t*)(0x400313CCUL)) +#define FM4_INTREQ_IRQ114MON *((volatile uint32_t*)(0x400313CCUL)) +#define FM_INTREQ_IRQ115MON *((volatile uint32_t*)(0x400313D0UL)) +#define FM4_INTREQ_IRQ115MON *((volatile uint32_t*)(0x400313D0UL)) +#define FM_INTREQ_IRQ116MON *((volatile uint32_t*)(0x400313D4UL)) +#define FM4_INTREQ_IRQ116MON *((volatile uint32_t*)(0x400313D4UL)) +#define FM_INTREQ_IRQ117MON *((volatile uint32_t*)(0x400313D8UL)) +#define FM4_INTREQ_IRQ117MON *((volatile uint32_t*)(0x400313D8UL)) +#define FM_INTREQ_IRQ118MON *((volatile uint32_t*)(0x400313DCUL)) +#define FM4_INTREQ_IRQ118MON *((volatile uint32_t*)(0x400313DCUL)) +#define FM_INTREQ_IRQ119MON *((volatile uint32_t*)(0x400313E0UL)) +#define FM4_INTREQ_IRQ119MON *((volatile uint32_t*)(0x400313E0UL)) +#define FM_INTREQ_IRQ120MON *((volatile uint32_t*)(0x400313E4UL)) +#define FM4_INTREQ_IRQ120MON *((volatile uint32_t*)(0x400313E4UL)) +#define FM_INTREQ_IRQ121MON *((volatile uint32_t*)(0x400313E8UL)) +#define FM4_INTREQ_IRQ121MON *((volatile uint32_t*)(0x400313E8UL)) +#define FM_INTREQ_IRQ122MON *((volatile uint32_t*)(0x400313ECUL)) +#define FM4_INTREQ_IRQ122MON *((volatile uint32_t*)(0x400313ECUL)) +#define FM_INTREQ_IRQ123MON *((volatile uint32_t*)(0x400313F0UL)) +#define FM4_INTREQ_IRQ123MON *((volatile uint32_t*)(0x400313F0UL)) +#define FM_INTREQ_IRQ124MON *((volatile uint32_t*)(0x400313F4UL)) +#define FM4_INTREQ_IRQ124MON *((volatile uint32_t*)(0x400313F4UL)) +#define FM_INTREQ_IRQ125MON *((volatile uint32_t*)(0x400313F8UL)) +#define FM4_INTREQ_IRQ125MON *((volatile uint32_t*)(0x400313F8UL)) +#define FM_INTREQ_IRQ126MON *((volatile uint32_t*)(0x400313FCUL)) +#define FM4_INTREQ_IRQ126MON *((volatile uint32_t*)(0x400313FCUL)) +#define FM_INTREQ_IRQ127MON *((volatile uint32_t*)(0x40031400UL)) +#define FM4_INTREQ_IRQ127MON *((volatile uint32_t*)(0x40031400UL)) + +/******************************************************************************* +* LSCRP Registers LSCRP +* Register Definition +*******************************************************************************/ +#define FM_LSCRP_LCR_PRSLD *((volatile uint8_t*)(0x4003C000UL)) +#define FM4_LSCRP_LCR_PRSLD *((volatile uint8_t*)(0x4003C000UL)) + +/******************************************************************************* +* LVD Registers LVD +* Register Definition +*******************************************************************************/ +#define FM_LVD_LVD_CTL *((volatile uint8_t*)(0x40035000UL)) +#define FM4_LVD_LVD_CTL *((volatile uint8_t*)(0x40035000UL)) +#define FM_LVD_LVD_STR *((volatile uint8_t*)(0x40035004UL)) +#define FM4_LVD_LVD_STR *((volatile uint8_t*)(0x40035004UL)) +#define FM_LVD_LVD_CLR *((volatile uint8_t*)(0x40035008UL)) +#define FM4_LVD_LVD_CLR *((volatile uint8_t*)(0x40035008UL)) +#define FM_LVD_LVD_RLR *((volatile uint32_t*)(0x4003500CUL)) +#define FM4_LVD_LVD_RLR *((volatile uint32_t*)(0x4003500CUL)) +#define FM_LVD_LVD_STR2 *((volatile uint8_t*)(0x40035010UL)) +#define FM4_LVD_LVD_STR2 *((volatile uint8_t*)(0x40035010UL)) + +/******************************************************************************* +* MFS Registers MFS0 +* Register Definition +*******************************************************************************/ +#define FM_MFS0_CSIO_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_CSIO_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_I2C_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_I2C_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_LIN_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_LIN_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_UART_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM4_MFS0_UART_SMR *((volatile uint8_t*)(0x40038000UL)) +#define FM_MFS0_CSIO_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_CSIO_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_I2C_IBCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_I2C_IBCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_LIN_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_LIN_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_UART_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM4_MFS0_UART_SCR *((volatile uint8_t*)(0x40038001UL)) +#define FM_MFS0_CSIO_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_CSIO_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_I2C_IBSR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_I2C_IBSR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_LIN_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_LIN_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_UART_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM4_MFS0_UART_ESCR *((volatile uint8_t*)(0x40038004UL)) +#define FM_MFS0_CSIO_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_CSIO_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_I2C_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_I2C_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_LIN_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_LIN_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_UART_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM4_MFS0_UART_SSR *((volatile uint8_t*)(0x40038005UL)) +#define FM_MFS0_CSIO_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_CSIO_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_CSIO_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_CSIO_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_I2C_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_I2C_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_I2C_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_I2C_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_LIN_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_LIN_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_LIN_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_LIN_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_UART_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_UART_RDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_UART_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM4_MFS0_UART_TDR *((volatile uint16_t*)(0x40038008UL)) +#define FM_MFS0_CSIO_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_CSIO_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_I2C_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_I2C_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_LIN_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_LIN_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_UART_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM4_MFS0_UART_BGR *((volatile uint16_t*)(0x4003800CUL)) +#define FM_MFS0_I2C_ISBA *((volatile uint8_t*)(0x40038010UL)) +#define FM4_MFS0_I2C_ISBA *((volatile uint8_t*)(0x40038010UL)) +#define FM_MFS0_I2C_ISMK *((volatile uint8_t*)(0x40038011UL)) +#define FM4_MFS0_I2C_ISMK *((volatile uint8_t*)(0x40038011UL)) +#define FM_MFS0_CSIO_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_CSIO_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_I2C_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_I2C_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_LIN_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_LIN_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_UART_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM4_MFS0_UART_FCR *((volatile uint16_t*)(0x40038014UL)) +#define FM_MFS0_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_I2C_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_I2C_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_LIN_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_LIN_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_UART_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM4_MFS0_UART_FBYTE1 *((volatile uint8_t*)(0x40038018UL)) +#define FM_MFS0_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_I2C_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_I2C_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_LIN_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_LIN_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_UART_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM4_MFS0_UART_FBYTE2 *((volatile uint8_t*)(0x40038019UL)) +#define FM_MFS0_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003801CUL)) +#define FM4_MFS0_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003801CUL)) +#define FM_MFS0_I2C_NFCR *((volatile uint8_t*)(0x4003801CUL)) +#define FM4_MFS0_I2C_NFCR *((volatile uint8_t*)(0x4003801CUL)) +#define FM_MFS0_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003801DUL)) +#define FM4_MFS0_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003801DUL)) +#define FM_MFS0_I2C_EIBCR *((volatile uint8_t*)(0x4003801DUL)) +#define FM4_MFS0_I2C_EIBCR *((volatile uint8_t*)(0x4003801DUL)) +#define FM_MFS0_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038020UL)) +#define FM4_MFS0_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038020UL)) +#define FM_MFS0_CSIO_SACSR *((volatile uint16_t*)(0x40038024UL)) +#define FM4_MFS0_CSIO_SACSR *((volatile uint16_t*)(0x40038024UL)) +#define FM_MFS0_CSIO_STMR *((volatile uint16_t*)(0x40038028UL)) +#define FM4_MFS0_CSIO_STMR *((volatile uint16_t*)(0x40038028UL)) +#define FM_MFS0_CSIO_STMCR *((volatile uint16_t*)(0x4003802CUL)) +#define FM4_MFS0_CSIO_STMCR *((volatile uint16_t*)(0x4003802CUL)) +#define FM_MFS0_CSIO_SCSCR *((volatile uint16_t*)(0x40038030UL)) +#define FM4_MFS0_CSIO_SCSCR *((volatile uint16_t*)(0x40038030UL)) +#define FM_MFS0_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038034UL)) +#define FM4_MFS0_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038034UL)) +#define FM_MFS0_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038035UL)) +#define FM4_MFS0_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038035UL)) +#define FM_MFS0_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038038UL)) +#define FM4_MFS0_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038038UL)) +#define FM_MFS0_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003803CUL)) +#define FM4_MFS0_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003803CUL)) +#define FM_MFS0_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003803DUL)) +#define FM4_MFS0_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003803DUL)) +#define FM_MFS0_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038040UL)) +#define FM4_MFS0_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038040UL)) +#define FM_MFS0_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038041UL)) +#define FM4_MFS0_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038041UL)) + +/******************************************************************************* +* MFS Registers MFS1 +* Register Definition +*******************************************************************************/ +#define FM_MFS1_CSIO_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_CSIO_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_I2C_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_I2C_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_LIN_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_LIN_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_UART_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM4_MFS1_UART_SMR *((volatile uint8_t*)(0x40038100UL)) +#define FM_MFS1_CSIO_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_CSIO_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_I2C_IBCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_I2C_IBCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_LIN_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_LIN_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_UART_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM4_MFS1_UART_SCR *((volatile uint8_t*)(0x40038101UL)) +#define FM_MFS1_CSIO_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_CSIO_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_I2C_IBSR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_I2C_IBSR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_LIN_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_LIN_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_UART_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM4_MFS1_UART_ESCR *((volatile uint8_t*)(0x40038104UL)) +#define FM_MFS1_CSIO_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_CSIO_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_I2C_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_I2C_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_LIN_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_LIN_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_UART_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM4_MFS1_UART_SSR *((volatile uint8_t*)(0x40038105UL)) +#define FM_MFS1_CSIO_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_CSIO_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_CSIO_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_CSIO_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_I2C_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_I2C_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_I2C_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_I2C_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_LIN_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_LIN_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_LIN_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_LIN_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_UART_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_UART_RDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_UART_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM4_MFS1_UART_TDR *((volatile uint16_t*)(0x40038108UL)) +#define FM_MFS1_CSIO_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_CSIO_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_I2C_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_I2C_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_LIN_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_LIN_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_UART_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM4_MFS1_UART_BGR *((volatile uint16_t*)(0x4003810CUL)) +#define FM_MFS1_I2C_ISBA *((volatile uint8_t*)(0x40038110UL)) +#define FM4_MFS1_I2C_ISBA *((volatile uint8_t*)(0x40038110UL)) +#define FM_MFS1_I2C_ISMK *((volatile uint8_t*)(0x40038111UL)) +#define FM4_MFS1_I2C_ISMK *((volatile uint8_t*)(0x40038111UL)) +#define FM_MFS1_CSIO_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_CSIO_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_I2C_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_I2C_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_LIN_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_LIN_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_UART_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM4_MFS1_UART_FCR *((volatile uint16_t*)(0x40038114UL)) +#define FM_MFS1_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_I2C_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_I2C_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_LIN_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_LIN_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_UART_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM4_MFS1_UART_FBYTE1 *((volatile uint8_t*)(0x40038118UL)) +#define FM_MFS1_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_I2C_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_I2C_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_LIN_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_LIN_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_UART_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM4_MFS1_UART_FBYTE2 *((volatile uint8_t*)(0x40038119UL)) +#define FM_MFS1_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003811CUL)) +#define FM4_MFS1_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003811CUL)) +#define FM_MFS1_I2C_NFCR *((volatile uint8_t*)(0x4003811CUL)) +#define FM4_MFS1_I2C_NFCR *((volatile uint8_t*)(0x4003811CUL)) +#define FM_MFS1_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003811DUL)) +#define FM4_MFS1_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003811DUL)) +#define FM_MFS1_I2C_EIBCR *((volatile uint8_t*)(0x4003811DUL)) +#define FM4_MFS1_I2C_EIBCR *((volatile uint8_t*)(0x4003811DUL)) +#define FM_MFS1_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038120UL)) +#define FM4_MFS1_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038120UL)) +#define FM_MFS1_CSIO_SACSR *((volatile uint16_t*)(0x40038124UL)) +#define FM4_MFS1_CSIO_SACSR *((volatile uint16_t*)(0x40038124UL)) +#define FM_MFS1_CSIO_STMR *((volatile uint16_t*)(0x40038128UL)) +#define FM4_MFS1_CSIO_STMR *((volatile uint16_t*)(0x40038128UL)) +#define FM_MFS1_CSIO_STMCR *((volatile uint16_t*)(0x4003812CUL)) +#define FM4_MFS1_CSIO_STMCR *((volatile uint16_t*)(0x4003812CUL)) +#define FM_MFS1_CSIO_SCSCR *((volatile uint16_t*)(0x40038130UL)) +#define FM4_MFS1_CSIO_SCSCR *((volatile uint16_t*)(0x40038130UL)) +#define FM_MFS1_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038134UL)) +#define FM4_MFS1_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038134UL)) +#define FM_MFS1_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038135UL)) +#define FM4_MFS1_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038135UL)) +#define FM_MFS1_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038138UL)) +#define FM4_MFS1_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038138UL)) +#define FM_MFS1_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003813CUL)) +#define FM4_MFS1_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003813CUL)) +#define FM_MFS1_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003813DUL)) +#define FM4_MFS1_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003813DUL)) +#define FM_MFS1_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038140UL)) +#define FM4_MFS1_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038140UL)) +#define FM_MFS1_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038141UL)) +#define FM4_MFS1_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038141UL)) + +/******************************************************************************* +* MFS Registers MFS10 +* Register Definition +*******************************************************************************/ +#define FM_MFS10_CSIO_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_CSIO_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_I2C_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_I2C_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_LIN_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_LIN_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_UART_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM4_MFS10_UART_SMR *((volatile uint8_t*)(0x40038A00UL)) +#define FM_MFS10_CSIO_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_CSIO_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_I2C_IBCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_I2C_IBCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_LIN_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_LIN_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_UART_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM4_MFS10_UART_SCR *((volatile uint8_t*)(0x40038A01UL)) +#define FM_MFS10_CSIO_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_CSIO_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_I2C_IBSR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_I2C_IBSR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_LIN_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_LIN_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_UART_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM4_MFS10_UART_ESCR *((volatile uint8_t*)(0x40038A04UL)) +#define FM_MFS10_CSIO_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_CSIO_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_I2C_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_I2C_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_LIN_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_LIN_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_UART_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM4_MFS10_UART_SSR *((volatile uint8_t*)(0x40038A05UL)) +#define FM_MFS10_CSIO_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_CSIO_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_CSIO_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_CSIO_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_I2C_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_I2C_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_I2C_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_I2C_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_LIN_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_LIN_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_LIN_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_LIN_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_UART_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_UART_RDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_UART_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM4_MFS10_UART_TDR *((volatile uint16_t*)(0x40038A08UL)) +#define FM_MFS10_CSIO_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_CSIO_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_I2C_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_I2C_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_LIN_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_LIN_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_UART_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM4_MFS10_UART_BGR *((volatile uint16_t*)(0x40038A0CUL)) +#define FM_MFS10_I2C_ISBA *((volatile uint8_t*)(0x40038A10UL)) +#define FM4_MFS10_I2C_ISBA *((volatile uint8_t*)(0x40038A10UL)) +#define FM_MFS10_I2C_ISMK *((volatile uint8_t*)(0x40038A11UL)) +#define FM4_MFS10_I2C_ISMK *((volatile uint8_t*)(0x40038A11UL)) +#define FM_MFS10_CSIO_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_CSIO_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_I2C_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_I2C_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_LIN_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_LIN_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_UART_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM4_MFS10_UART_FCR *((volatile uint16_t*)(0x40038A14UL)) +#define FM_MFS10_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_I2C_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_I2C_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_LIN_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_LIN_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_UART_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM4_MFS10_UART_FBYTE1 *((volatile uint8_t*)(0x40038A18UL)) +#define FM_MFS10_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_I2C_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_I2C_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_LIN_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_LIN_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_UART_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM4_MFS10_UART_FBYTE2 *((volatile uint8_t*)(0x40038A19UL)) +#define FM_MFS10_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038A1CUL)) +#define FM4_MFS10_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038A1CUL)) +#define FM_MFS10_I2C_NFCR *((volatile uint8_t*)(0x40038A1CUL)) +#define FM4_MFS10_I2C_NFCR *((volatile uint8_t*)(0x40038A1CUL)) +#define FM_MFS10_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038A1DUL)) +#define FM4_MFS10_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038A1DUL)) +#define FM_MFS10_I2C_EIBCR *((volatile uint8_t*)(0x40038A1DUL)) +#define FM4_MFS10_I2C_EIBCR *((volatile uint8_t*)(0x40038A1DUL)) +#define FM_MFS10_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038A20UL)) +#define FM4_MFS10_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038A20UL)) +#define FM_MFS10_CSIO_SACSR *((volatile uint16_t*)(0x40038A24UL)) +#define FM4_MFS10_CSIO_SACSR *((volatile uint16_t*)(0x40038A24UL)) +#define FM_MFS10_CSIO_STMR *((volatile uint16_t*)(0x40038A28UL)) +#define FM4_MFS10_CSIO_STMR *((volatile uint16_t*)(0x40038A28UL)) +#define FM_MFS10_CSIO_STMCR *((volatile uint16_t*)(0x40038A2CUL)) +#define FM4_MFS10_CSIO_STMCR *((volatile uint16_t*)(0x40038A2CUL)) +#define FM_MFS10_CSIO_SCSCR *((volatile uint16_t*)(0x40038A30UL)) +#define FM4_MFS10_CSIO_SCSCR *((volatile uint16_t*)(0x40038A30UL)) +#define FM_MFS10_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038A34UL)) +#define FM4_MFS10_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038A34UL)) +#define FM_MFS10_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038A35UL)) +#define FM4_MFS10_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038A35UL)) +#define FM_MFS10_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038A38UL)) +#define FM4_MFS10_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038A38UL)) +#define FM_MFS10_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038A3CUL)) +#define FM4_MFS10_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038A3CUL)) +#define FM_MFS10_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038A3DUL)) +#define FM4_MFS10_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038A3DUL)) +#define FM_MFS10_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038A40UL)) +#define FM4_MFS10_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038A40UL)) +#define FM_MFS10_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038A41UL)) +#define FM4_MFS10_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038A41UL)) + +/******************************************************************************* +* MFS Registers MFS11 +* Register Definition +*******************************************************************************/ +#define FM_MFS11_CSIO_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_CSIO_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_I2C_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_I2C_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_LIN_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_LIN_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_UART_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM4_MFS11_UART_SMR *((volatile uint8_t*)(0x40038B00UL)) +#define FM_MFS11_CSIO_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_CSIO_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_I2C_IBCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_I2C_IBCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_LIN_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_LIN_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_UART_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM4_MFS11_UART_SCR *((volatile uint8_t*)(0x40038B01UL)) +#define FM_MFS11_CSIO_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_CSIO_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_I2C_IBSR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_I2C_IBSR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_LIN_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_LIN_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_UART_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM4_MFS11_UART_ESCR *((volatile uint8_t*)(0x40038B04UL)) +#define FM_MFS11_CSIO_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_CSIO_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_I2C_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_I2C_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_LIN_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_LIN_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_UART_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM4_MFS11_UART_SSR *((volatile uint8_t*)(0x40038B05UL)) +#define FM_MFS11_CSIO_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_CSIO_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_CSIO_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_CSIO_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_I2C_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_I2C_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_I2C_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_I2C_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_LIN_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_LIN_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_LIN_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_LIN_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_UART_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_UART_RDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_UART_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM4_MFS11_UART_TDR *((volatile uint16_t*)(0x40038B08UL)) +#define FM_MFS11_CSIO_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_CSIO_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_I2C_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_I2C_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_LIN_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_LIN_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_UART_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM4_MFS11_UART_BGR *((volatile uint16_t*)(0x40038B0CUL)) +#define FM_MFS11_I2C_ISBA *((volatile uint8_t*)(0x40038B10UL)) +#define FM4_MFS11_I2C_ISBA *((volatile uint8_t*)(0x40038B10UL)) +#define FM_MFS11_I2C_ISMK *((volatile uint8_t*)(0x40038B11UL)) +#define FM4_MFS11_I2C_ISMK *((volatile uint8_t*)(0x40038B11UL)) +#define FM_MFS11_CSIO_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_CSIO_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_I2C_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_I2C_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_LIN_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_LIN_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_UART_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM4_MFS11_UART_FCR *((volatile uint16_t*)(0x40038B14UL)) +#define FM_MFS11_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_I2C_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_I2C_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_LIN_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_LIN_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_UART_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM4_MFS11_UART_FBYTE1 *((volatile uint8_t*)(0x40038B18UL)) +#define FM_MFS11_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_I2C_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_I2C_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_LIN_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_LIN_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_UART_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM4_MFS11_UART_FBYTE2 *((volatile uint8_t*)(0x40038B19UL)) +#define FM_MFS11_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038B1CUL)) +#define FM4_MFS11_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038B1CUL)) +#define FM_MFS11_I2C_NFCR *((volatile uint8_t*)(0x40038B1CUL)) +#define FM4_MFS11_I2C_NFCR *((volatile uint8_t*)(0x40038B1CUL)) +#define FM_MFS11_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038B1DUL)) +#define FM4_MFS11_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038B1DUL)) +#define FM_MFS11_I2C_EIBCR *((volatile uint8_t*)(0x40038B1DUL)) +#define FM4_MFS11_I2C_EIBCR *((volatile uint8_t*)(0x40038B1DUL)) +#define FM_MFS11_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038B20UL)) +#define FM4_MFS11_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038B20UL)) +#define FM_MFS11_CSIO_SACSR *((volatile uint16_t*)(0x40038B24UL)) +#define FM4_MFS11_CSIO_SACSR *((volatile uint16_t*)(0x40038B24UL)) +#define FM_MFS11_CSIO_STMR *((volatile uint16_t*)(0x40038B28UL)) +#define FM4_MFS11_CSIO_STMR *((volatile uint16_t*)(0x40038B28UL)) +#define FM_MFS11_CSIO_STMCR *((volatile uint16_t*)(0x40038B2CUL)) +#define FM4_MFS11_CSIO_STMCR *((volatile uint16_t*)(0x40038B2CUL)) +#define FM_MFS11_CSIO_SCSCR *((volatile uint16_t*)(0x40038B30UL)) +#define FM4_MFS11_CSIO_SCSCR *((volatile uint16_t*)(0x40038B30UL)) +#define FM_MFS11_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038B34UL)) +#define FM4_MFS11_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038B34UL)) +#define FM_MFS11_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038B35UL)) +#define FM4_MFS11_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038B35UL)) +#define FM_MFS11_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038B38UL)) +#define FM4_MFS11_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038B38UL)) +#define FM_MFS11_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038B3CUL)) +#define FM4_MFS11_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038B3CUL)) +#define FM_MFS11_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038B3DUL)) +#define FM4_MFS11_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038B3DUL)) +#define FM_MFS11_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038B40UL)) +#define FM4_MFS11_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038B40UL)) +#define FM_MFS11_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038B41UL)) +#define FM4_MFS11_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038B41UL)) + +/******************************************************************************* +* MFS Registers MFS12 +* Register Definition +*******************************************************************************/ +#define FM_MFS12_CSIO_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_CSIO_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_I2C_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_I2C_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_LIN_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_LIN_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_UART_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM4_MFS12_UART_SMR *((volatile uint8_t*)(0x40038C00UL)) +#define FM_MFS12_CSIO_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_CSIO_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_I2C_IBCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_I2C_IBCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_LIN_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_LIN_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_UART_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM4_MFS12_UART_SCR *((volatile uint8_t*)(0x40038C01UL)) +#define FM_MFS12_CSIO_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_CSIO_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_I2C_IBSR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_I2C_IBSR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_LIN_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_LIN_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_UART_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM4_MFS12_UART_ESCR *((volatile uint8_t*)(0x40038C04UL)) +#define FM_MFS12_CSIO_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_CSIO_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_I2C_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_I2C_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_LIN_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_LIN_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_UART_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM4_MFS12_UART_SSR *((volatile uint8_t*)(0x40038C05UL)) +#define FM_MFS12_CSIO_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_CSIO_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_CSIO_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_CSIO_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_I2C_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_I2C_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_I2C_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_I2C_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_LIN_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_LIN_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_LIN_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_LIN_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_UART_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_UART_RDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_UART_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM4_MFS12_UART_TDR *((volatile uint16_t*)(0x40038C08UL)) +#define FM_MFS12_CSIO_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_CSIO_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_I2C_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_I2C_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_LIN_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_LIN_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_UART_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM4_MFS12_UART_BGR *((volatile uint16_t*)(0x40038C0CUL)) +#define FM_MFS12_I2C_ISBA *((volatile uint8_t*)(0x40038C10UL)) +#define FM4_MFS12_I2C_ISBA *((volatile uint8_t*)(0x40038C10UL)) +#define FM_MFS12_I2C_ISMK *((volatile uint8_t*)(0x40038C11UL)) +#define FM4_MFS12_I2C_ISMK *((volatile uint8_t*)(0x40038C11UL)) +#define FM_MFS12_CSIO_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_CSIO_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_I2C_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_I2C_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_LIN_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_LIN_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_UART_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM4_MFS12_UART_FCR *((volatile uint16_t*)(0x40038C14UL)) +#define FM_MFS12_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_I2C_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_I2C_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_LIN_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_LIN_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_UART_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM4_MFS12_UART_FBYTE1 *((volatile uint8_t*)(0x40038C18UL)) +#define FM_MFS12_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_I2C_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_I2C_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_LIN_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_LIN_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_UART_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM4_MFS12_UART_FBYTE2 *((volatile uint8_t*)(0x40038C19UL)) +#define FM_MFS12_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038C1CUL)) +#define FM4_MFS12_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038C1CUL)) +#define FM_MFS12_I2C_NFCR *((volatile uint8_t*)(0x40038C1CUL)) +#define FM4_MFS12_I2C_NFCR *((volatile uint8_t*)(0x40038C1CUL)) +#define FM_MFS12_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038C1DUL)) +#define FM4_MFS12_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038C1DUL)) +#define FM_MFS12_I2C_EIBCR *((volatile uint8_t*)(0x40038C1DUL)) +#define FM4_MFS12_I2C_EIBCR *((volatile uint8_t*)(0x40038C1DUL)) +#define FM_MFS12_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038C20UL)) +#define FM4_MFS12_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038C20UL)) +#define FM_MFS12_CSIO_SACSR *((volatile uint16_t*)(0x40038C24UL)) +#define FM4_MFS12_CSIO_SACSR *((volatile uint16_t*)(0x40038C24UL)) +#define FM_MFS12_CSIO_STMR *((volatile uint16_t*)(0x40038C28UL)) +#define FM4_MFS12_CSIO_STMR *((volatile uint16_t*)(0x40038C28UL)) +#define FM_MFS12_CSIO_STMCR *((volatile uint16_t*)(0x40038C2CUL)) +#define FM4_MFS12_CSIO_STMCR *((volatile uint16_t*)(0x40038C2CUL)) +#define FM_MFS12_CSIO_SCSCR *((volatile uint16_t*)(0x40038C30UL)) +#define FM4_MFS12_CSIO_SCSCR *((volatile uint16_t*)(0x40038C30UL)) +#define FM_MFS12_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038C34UL)) +#define FM4_MFS12_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038C34UL)) +#define FM_MFS12_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038C35UL)) +#define FM4_MFS12_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038C35UL)) +#define FM_MFS12_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038C38UL)) +#define FM4_MFS12_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038C38UL)) +#define FM_MFS12_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038C3CUL)) +#define FM4_MFS12_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038C3CUL)) +#define FM_MFS12_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038C3DUL)) +#define FM4_MFS12_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038C3DUL)) +#define FM_MFS12_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038C40UL)) +#define FM4_MFS12_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038C40UL)) +#define FM_MFS12_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038C41UL)) +#define FM4_MFS12_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038C41UL)) + +/******************************************************************************* +* MFS Registers MFS13 +* Register Definition +*******************************************************************************/ +#define FM_MFS13_CSIO_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_CSIO_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_I2C_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_I2C_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_LIN_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_LIN_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_UART_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM4_MFS13_UART_SMR *((volatile uint8_t*)(0x40038D00UL)) +#define FM_MFS13_CSIO_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_CSIO_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_I2C_IBCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_I2C_IBCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_LIN_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_LIN_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_UART_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM4_MFS13_UART_SCR *((volatile uint8_t*)(0x40038D01UL)) +#define FM_MFS13_CSIO_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_CSIO_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_I2C_IBSR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_I2C_IBSR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_LIN_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_LIN_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_UART_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM4_MFS13_UART_ESCR *((volatile uint8_t*)(0x40038D04UL)) +#define FM_MFS13_CSIO_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_CSIO_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_I2C_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_I2C_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_LIN_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_LIN_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_UART_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM4_MFS13_UART_SSR *((volatile uint8_t*)(0x40038D05UL)) +#define FM_MFS13_CSIO_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_CSIO_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_CSIO_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_CSIO_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_I2C_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_I2C_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_I2C_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_I2C_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_LIN_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_LIN_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_LIN_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_LIN_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_UART_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_UART_RDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_UART_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM4_MFS13_UART_TDR *((volatile uint16_t*)(0x40038D08UL)) +#define FM_MFS13_CSIO_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_CSIO_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_I2C_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_I2C_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_LIN_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_LIN_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_UART_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM4_MFS13_UART_BGR *((volatile uint16_t*)(0x40038D0CUL)) +#define FM_MFS13_I2C_ISBA *((volatile uint8_t*)(0x40038D10UL)) +#define FM4_MFS13_I2C_ISBA *((volatile uint8_t*)(0x40038D10UL)) +#define FM_MFS13_I2C_ISMK *((volatile uint8_t*)(0x40038D11UL)) +#define FM4_MFS13_I2C_ISMK *((volatile uint8_t*)(0x40038D11UL)) +#define FM_MFS13_CSIO_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_CSIO_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_I2C_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_I2C_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_LIN_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_LIN_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_UART_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM4_MFS13_UART_FCR *((volatile uint16_t*)(0x40038D14UL)) +#define FM_MFS13_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_I2C_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_I2C_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_LIN_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_LIN_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_UART_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM4_MFS13_UART_FBYTE1 *((volatile uint8_t*)(0x40038D18UL)) +#define FM_MFS13_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_I2C_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_I2C_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_LIN_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_LIN_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_UART_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM4_MFS13_UART_FBYTE2 *((volatile uint8_t*)(0x40038D19UL)) +#define FM_MFS13_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038D1CUL)) +#define FM4_MFS13_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038D1CUL)) +#define FM_MFS13_I2C_NFCR *((volatile uint8_t*)(0x40038D1CUL)) +#define FM4_MFS13_I2C_NFCR *((volatile uint8_t*)(0x40038D1CUL)) +#define FM_MFS13_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038D1DUL)) +#define FM4_MFS13_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038D1DUL)) +#define FM_MFS13_I2C_EIBCR *((volatile uint8_t*)(0x40038D1DUL)) +#define FM4_MFS13_I2C_EIBCR *((volatile uint8_t*)(0x40038D1DUL)) +#define FM_MFS13_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038D20UL)) +#define FM4_MFS13_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038D20UL)) +#define FM_MFS13_CSIO_SACSR *((volatile uint16_t*)(0x40038D24UL)) +#define FM4_MFS13_CSIO_SACSR *((volatile uint16_t*)(0x40038D24UL)) +#define FM_MFS13_CSIO_STMR *((volatile uint16_t*)(0x40038D28UL)) +#define FM4_MFS13_CSIO_STMR *((volatile uint16_t*)(0x40038D28UL)) +#define FM_MFS13_CSIO_STMCR *((volatile uint16_t*)(0x40038D2CUL)) +#define FM4_MFS13_CSIO_STMCR *((volatile uint16_t*)(0x40038D2CUL)) +#define FM_MFS13_CSIO_SCSCR *((volatile uint16_t*)(0x40038D30UL)) +#define FM4_MFS13_CSIO_SCSCR *((volatile uint16_t*)(0x40038D30UL)) +#define FM_MFS13_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038D34UL)) +#define FM4_MFS13_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038D34UL)) +#define FM_MFS13_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038D35UL)) +#define FM4_MFS13_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038D35UL)) +#define FM_MFS13_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038D38UL)) +#define FM4_MFS13_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038D38UL)) +#define FM_MFS13_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038D3CUL)) +#define FM4_MFS13_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038D3CUL)) +#define FM_MFS13_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038D3DUL)) +#define FM4_MFS13_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038D3DUL)) +#define FM_MFS13_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038D40UL)) +#define FM4_MFS13_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038D40UL)) +#define FM_MFS13_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038D41UL)) +#define FM4_MFS13_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038D41UL)) + +/******************************************************************************* +* MFS Registers MFS14 +* Register Definition +*******************************************************************************/ +#define FM_MFS14_CSIO_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_CSIO_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_I2C_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_I2C_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_LIN_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_LIN_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_UART_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM4_MFS14_UART_SMR *((volatile uint8_t*)(0x40038E00UL)) +#define FM_MFS14_CSIO_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_CSIO_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_I2C_IBCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_I2C_IBCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_LIN_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_LIN_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_UART_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM4_MFS14_UART_SCR *((volatile uint8_t*)(0x40038E01UL)) +#define FM_MFS14_CSIO_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_CSIO_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_I2C_IBSR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_I2C_IBSR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_LIN_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_LIN_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_UART_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM4_MFS14_UART_ESCR *((volatile uint8_t*)(0x40038E04UL)) +#define FM_MFS14_CSIO_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_CSIO_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_I2C_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_I2C_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_LIN_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_LIN_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_UART_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM4_MFS14_UART_SSR *((volatile uint8_t*)(0x40038E05UL)) +#define FM_MFS14_CSIO_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_CSIO_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_CSIO_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_CSIO_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_I2C_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_I2C_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_I2C_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_I2C_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_LIN_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_LIN_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_LIN_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_LIN_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_UART_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_UART_RDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_UART_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM4_MFS14_UART_TDR *((volatile uint16_t*)(0x40038E08UL)) +#define FM_MFS14_CSIO_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_CSIO_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_I2C_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_I2C_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_LIN_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_LIN_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_UART_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM4_MFS14_UART_BGR *((volatile uint16_t*)(0x40038E0CUL)) +#define FM_MFS14_I2C_ISBA *((volatile uint8_t*)(0x40038E10UL)) +#define FM4_MFS14_I2C_ISBA *((volatile uint8_t*)(0x40038E10UL)) +#define FM_MFS14_I2C_ISMK *((volatile uint8_t*)(0x40038E11UL)) +#define FM4_MFS14_I2C_ISMK *((volatile uint8_t*)(0x40038E11UL)) +#define FM_MFS14_CSIO_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_CSIO_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_I2C_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_I2C_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_LIN_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_LIN_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_UART_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM4_MFS14_UART_FCR *((volatile uint16_t*)(0x40038E14UL)) +#define FM_MFS14_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_I2C_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_I2C_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_LIN_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_LIN_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_UART_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM4_MFS14_UART_FBYTE1 *((volatile uint8_t*)(0x40038E18UL)) +#define FM_MFS14_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_I2C_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_I2C_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_LIN_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_LIN_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_UART_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM4_MFS14_UART_FBYTE2 *((volatile uint8_t*)(0x40038E19UL)) +#define FM_MFS14_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038E1CUL)) +#define FM4_MFS14_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038E1CUL)) +#define FM_MFS14_I2C_NFCR *((volatile uint8_t*)(0x40038E1CUL)) +#define FM4_MFS14_I2C_NFCR *((volatile uint8_t*)(0x40038E1CUL)) +#define FM_MFS14_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038E1DUL)) +#define FM4_MFS14_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038E1DUL)) +#define FM_MFS14_I2C_EIBCR *((volatile uint8_t*)(0x40038E1DUL)) +#define FM4_MFS14_I2C_EIBCR *((volatile uint8_t*)(0x40038E1DUL)) +#define FM_MFS14_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038E20UL)) +#define FM4_MFS14_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038E20UL)) +#define FM_MFS14_CSIO_SACSR *((volatile uint16_t*)(0x40038E24UL)) +#define FM4_MFS14_CSIO_SACSR *((volatile uint16_t*)(0x40038E24UL)) +#define FM_MFS14_CSIO_STMR *((volatile uint16_t*)(0x40038E28UL)) +#define FM4_MFS14_CSIO_STMR *((volatile uint16_t*)(0x40038E28UL)) +#define FM_MFS14_CSIO_STMCR *((volatile uint16_t*)(0x40038E2CUL)) +#define FM4_MFS14_CSIO_STMCR *((volatile uint16_t*)(0x40038E2CUL)) +#define FM_MFS14_CSIO_SCSCR *((volatile uint16_t*)(0x40038E30UL)) +#define FM4_MFS14_CSIO_SCSCR *((volatile uint16_t*)(0x40038E30UL)) +#define FM_MFS14_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038E34UL)) +#define FM4_MFS14_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038E34UL)) +#define FM_MFS14_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038E35UL)) +#define FM4_MFS14_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038E35UL)) +#define FM_MFS14_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038E38UL)) +#define FM4_MFS14_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038E38UL)) +#define FM_MFS14_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038E3CUL)) +#define FM4_MFS14_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038E3CUL)) +#define FM_MFS14_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038E3DUL)) +#define FM4_MFS14_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038E3DUL)) +#define FM_MFS14_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038E40UL)) +#define FM4_MFS14_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038E40UL)) +#define FM_MFS14_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038E41UL)) +#define FM4_MFS14_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038E41UL)) + +/******************************************************************************* +* MFS Registers MFS15 +* Register Definition +*******************************************************************************/ +#define FM_MFS15_CSIO_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_CSIO_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_I2C_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_I2C_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_LIN_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_LIN_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_UART_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM4_MFS15_UART_SMR *((volatile uint8_t*)(0x40038F00UL)) +#define FM_MFS15_CSIO_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_CSIO_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_I2C_IBCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_I2C_IBCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_LIN_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_LIN_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_UART_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM4_MFS15_UART_SCR *((volatile uint8_t*)(0x40038F01UL)) +#define FM_MFS15_CSIO_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_CSIO_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_I2C_IBSR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_I2C_IBSR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_LIN_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_LIN_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_UART_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM4_MFS15_UART_ESCR *((volatile uint8_t*)(0x40038F04UL)) +#define FM_MFS15_CSIO_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_CSIO_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_I2C_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_I2C_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_LIN_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_LIN_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_UART_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM4_MFS15_UART_SSR *((volatile uint8_t*)(0x40038F05UL)) +#define FM_MFS15_CSIO_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_CSIO_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_CSIO_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_CSIO_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_I2C_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_I2C_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_I2C_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_I2C_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_LIN_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_LIN_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_LIN_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_LIN_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_UART_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_UART_RDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_UART_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM4_MFS15_UART_TDR *((volatile uint16_t*)(0x40038F08UL)) +#define FM_MFS15_CSIO_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_CSIO_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_I2C_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_I2C_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_LIN_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_LIN_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_UART_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM4_MFS15_UART_BGR *((volatile uint16_t*)(0x40038F0CUL)) +#define FM_MFS15_I2C_ISBA *((volatile uint8_t*)(0x40038F10UL)) +#define FM4_MFS15_I2C_ISBA *((volatile uint8_t*)(0x40038F10UL)) +#define FM_MFS15_I2C_ISMK *((volatile uint8_t*)(0x40038F11UL)) +#define FM4_MFS15_I2C_ISMK *((volatile uint8_t*)(0x40038F11UL)) +#define FM_MFS15_CSIO_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_CSIO_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_I2C_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_I2C_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_LIN_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_LIN_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_UART_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM4_MFS15_UART_FCR *((volatile uint16_t*)(0x40038F14UL)) +#define FM_MFS15_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_I2C_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_I2C_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_LIN_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_LIN_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_UART_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM4_MFS15_UART_FBYTE1 *((volatile uint8_t*)(0x40038F18UL)) +#define FM_MFS15_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_I2C_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_I2C_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_LIN_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_LIN_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_UART_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM4_MFS15_UART_FBYTE2 *((volatile uint8_t*)(0x40038F19UL)) +#define FM_MFS15_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038F1CUL)) +#define FM4_MFS15_CSIO_SCSTR0 *((volatile uint8_t*)(0x40038F1CUL)) +#define FM_MFS15_I2C_NFCR *((volatile uint8_t*)(0x40038F1CUL)) +#define FM4_MFS15_I2C_NFCR *((volatile uint8_t*)(0x40038F1CUL)) +#define FM_MFS15_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038F1DUL)) +#define FM4_MFS15_CSIO_SCSTR1 *((volatile uint8_t*)(0x40038F1DUL)) +#define FM_MFS15_I2C_EIBCR *((volatile uint8_t*)(0x40038F1DUL)) +#define FM4_MFS15_I2C_EIBCR *((volatile uint8_t*)(0x40038F1DUL)) +#define FM_MFS15_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038F20UL)) +#define FM4_MFS15_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038F20UL)) +#define FM_MFS15_CSIO_SACSR *((volatile uint16_t*)(0x40038F24UL)) +#define FM4_MFS15_CSIO_SACSR *((volatile uint16_t*)(0x40038F24UL)) +#define FM_MFS15_CSIO_STMR *((volatile uint16_t*)(0x40038F28UL)) +#define FM4_MFS15_CSIO_STMR *((volatile uint16_t*)(0x40038F28UL)) +#define FM_MFS15_CSIO_STMCR *((volatile uint16_t*)(0x40038F2CUL)) +#define FM4_MFS15_CSIO_STMCR *((volatile uint16_t*)(0x40038F2CUL)) +#define FM_MFS15_CSIO_SCSCR *((volatile uint16_t*)(0x40038F30UL)) +#define FM4_MFS15_CSIO_SCSCR *((volatile uint16_t*)(0x40038F30UL)) +#define FM_MFS15_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038F34UL)) +#define FM4_MFS15_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038F34UL)) +#define FM_MFS15_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038F35UL)) +#define FM4_MFS15_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038F35UL)) +#define FM_MFS15_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038F38UL)) +#define FM4_MFS15_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038F38UL)) +#define FM_MFS15_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038F3CUL)) +#define FM4_MFS15_CSIO_TBYTE0 *((volatile uint8_t*)(0x40038F3CUL)) +#define FM_MFS15_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038F3DUL)) +#define FM4_MFS15_CSIO_TBYTE1 *((volatile uint8_t*)(0x40038F3DUL)) +#define FM_MFS15_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038F40UL)) +#define FM4_MFS15_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038F40UL)) +#define FM_MFS15_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038F41UL)) +#define FM4_MFS15_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038F41UL)) + +/******************************************************************************* +* MFS Registers MFS2 +* Register Definition +*******************************************************************************/ +#define FM_MFS2_CSIO_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_CSIO_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_I2C_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_I2C_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_LIN_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_LIN_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_UART_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM4_MFS2_UART_SMR *((volatile uint8_t*)(0x40038200UL)) +#define FM_MFS2_CSIO_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_CSIO_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_I2C_IBCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_I2C_IBCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_LIN_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_LIN_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_UART_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM4_MFS2_UART_SCR *((volatile uint8_t*)(0x40038201UL)) +#define FM_MFS2_CSIO_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_CSIO_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_I2C_IBSR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_I2C_IBSR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_LIN_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_LIN_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_UART_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM4_MFS2_UART_ESCR *((volatile uint8_t*)(0x40038204UL)) +#define FM_MFS2_CSIO_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_CSIO_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_I2C_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_I2C_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_LIN_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_LIN_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_UART_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM4_MFS2_UART_SSR *((volatile uint8_t*)(0x40038205UL)) +#define FM_MFS2_CSIO_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_CSIO_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_CSIO_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_CSIO_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_I2C_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_I2C_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_I2C_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_I2C_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_LIN_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_LIN_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_LIN_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_LIN_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_UART_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_UART_RDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_UART_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM4_MFS2_UART_TDR *((volatile uint16_t*)(0x40038208UL)) +#define FM_MFS2_CSIO_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_CSIO_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_I2C_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_I2C_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_LIN_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_LIN_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_UART_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM4_MFS2_UART_BGR *((volatile uint16_t*)(0x4003820CUL)) +#define FM_MFS2_I2C_ISBA *((volatile uint8_t*)(0x40038210UL)) +#define FM4_MFS2_I2C_ISBA *((volatile uint8_t*)(0x40038210UL)) +#define FM_MFS2_I2C_ISMK *((volatile uint8_t*)(0x40038211UL)) +#define FM4_MFS2_I2C_ISMK *((volatile uint8_t*)(0x40038211UL)) +#define FM_MFS2_CSIO_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_CSIO_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_I2C_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_I2C_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_LIN_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_LIN_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_UART_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM4_MFS2_UART_FCR *((volatile uint16_t*)(0x40038214UL)) +#define FM_MFS2_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_I2C_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_I2C_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_LIN_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_LIN_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_UART_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM4_MFS2_UART_FBYTE1 *((volatile uint8_t*)(0x40038218UL)) +#define FM_MFS2_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_I2C_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_I2C_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_LIN_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_LIN_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_UART_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM4_MFS2_UART_FBYTE2 *((volatile uint8_t*)(0x40038219UL)) +#define FM_MFS2_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003821CUL)) +#define FM4_MFS2_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003821CUL)) +#define FM_MFS2_I2C_NFCR *((volatile uint8_t*)(0x4003821CUL)) +#define FM4_MFS2_I2C_NFCR *((volatile uint8_t*)(0x4003821CUL)) +#define FM_MFS2_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003821DUL)) +#define FM4_MFS2_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003821DUL)) +#define FM_MFS2_I2C_EIBCR *((volatile uint8_t*)(0x4003821DUL)) +#define FM4_MFS2_I2C_EIBCR *((volatile uint8_t*)(0x4003821DUL)) +#define FM_MFS2_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038220UL)) +#define FM4_MFS2_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038220UL)) +#define FM_MFS2_CSIO_SACSR *((volatile uint16_t*)(0x40038224UL)) +#define FM4_MFS2_CSIO_SACSR *((volatile uint16_t*)(0x40038224UL)) +#define FM_MFS2_CSIO_STMR *((volatile uint16_t*)(0x40038228UL)) +#define FM4_MFS2_CSIO_STMR *((volatile uint16_t*)(0x40038228UL)) +#define FM_MFS2_CSIO_STMCR *((volatile uint16_t*)(0x4003822CUL)) +#define FM4_MFS2_CSIO_STMCR *((volatile uint16_t*)(0x4003822CUL)) +#define FM_MFS2_CSIO_SCSCR *((volatile uint16_t*)(0x40038230UL)) +#define FM4_MFS2_CSIO_SCSCR *((volatile uint16_t*)(0x40038230UL)) +#define FM_MFS2_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038234UL)) +#define FM4_MFS2_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038234UL)) +#define FM_MFS2_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038235UL)) +#define FM4_MFS2_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038235UL)) +#define FM_MFS2_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038238UL)) +#define FM4_MFS2_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038238UL)) +#define FM_MFS2_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003823CUL)) +#define FM4_MFS2_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003823CUL)) +#define FM_MFS2_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003823DUL)) +#define FM4_MFS2_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003823DUL)) +#define FM_MFS2_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038240UL)) +#define FM4_MFS2_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038240UL)) +#define FM_MFS2_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038241UL)) +#define FM4_MFS2_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038241UL)) + +/******************************************************************************* +* MFS Registers MFS3 +* Register Definition +*******************************************************************************/ +#define FM_MFS3_CSIO_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_CSIO_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_I2C_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_I2C_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_LIN_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_LIN_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_UART_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM4_MFS3_UART_SMR *((volatile uint8_t*)(0x40038300UL)) +#define FM_MFS3_CSIO_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_CSIO_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_I2C_IBCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_I2C_IBCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_LIN_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_LIN_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_UART_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM4_MFS3_UART_SCR *((volatile uint8_t*)(0x40038301UL)) +#define FM_MFS3_CSIO_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_CSIO_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_I2C_IBSR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_I2C_IBSR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_LIN_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_LIN_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_UART_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM4_MFS3_UART_ESCR *((volatile uint8_t*)(0x40038304UL)) +#define FM_MFS3_CSIO_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_CSIO_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_I2C_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_I2C_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_LIN_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_LIN_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_UART_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM4_MFS3_UART_SSR *((volatile uint8_t*)(0x40038305UL)) +#define FM_MFS3_CSIO_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_CSIO_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_CSIO_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_CSIO_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_I2C_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_I2C_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_I2C_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_I2C_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_LIN_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_LIN_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_LIN_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_LIN_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_UART_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_UART_RDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_UART_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM4_MFS3_UART_TDR *((volatile uint16_t*)(0x40038308UL)) +#define FM_MFS3_CSIO_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_CSIO_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_I2C_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_I2C_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_LIN_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_LIN_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_UART_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM4_MFS3_UART_BGR *((volatile uint16_t*)(0x4003830CUL)) +#define FM_MFS3_I2C_ISBA *((volatile uint8_t*)(0x40038310UL)) +#define FM4_MFS3_I2C_ISBA *((volatile uint8_t*)(0x40038310UL)) +#define FM_MFS3_I2C_ISMK *((volatile uint8_t*)(0x40038311UL)) +#define FM4_MFS3_I2C_ISMK *((volatile uint8_t*)(0x40038311UL)) +#define FM_MFS3_CSIO_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_CSIO_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_I2C_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_I2C_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_LIN_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_LIN_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_UART_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM4_MFS3_UART_FCR *((volatile uint16_t*)(0x40038314UL)) +#define FM_MFS3_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_I2C_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_I2C_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_LIN_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_LIN_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_UART_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM4_MFS3_UART_FBYTE1 *((volatile uint8_t*)(0x40038318UL)) +#define FM_MFS3_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_I2C_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_I2C_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_LIN_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_LIN_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_UART_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM4_MFS3_UART_FBYTE2 *((volatile uint8_t*)(0x40038319UL)) +#define FM_MFS3_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003831CUL)) +#define FM4_MFS3_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003831CUL)) +#define FM_MFS3_I2C_NFCR *((volatile uint8_t*)(0x4003831CUL)) +#define FM4_MFS3_I2C_NFCR *((volatile uint8_t*)(0x4003831CUL)) +#define FM_MFS3_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003831DUL)) +#define FM4_MFS3_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003831DUL)) +#define FM_MFS3_I2C_EIBCR *((volatile uint8_t*)(0x4003831DUL)) +#define FM4_MFS3_I2C_EIBCR *((volatile uint8_t*)(0x4003831DUL)) +#define FM_MFS3_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038320UL)) +#define FM4_MFS3_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038320UL)) +#define FM_MFS3_CSIO_SACSR *((volatile uint16_t*)(0x40038324UL)) +#define FM4_MFS3_CSIO_SACSR *((volatile uint16_t*)(0x40038324UL)) +#define FM_MFS3_CSIO_STMR *((volatile uint16_t*)(0x40038328UL)) +#define FM4_MFS3_CSIO_STMR *((volatile uint16_t*)(0x40038328UL)) +#define FM_MFS3_CSIO_STMCR *((volatile uint16_t*)(0x4003832CUL)) +#define FM4_MFS3_CSIO_STMCR *((volatile uint16_t*)(0x4003832CUL)) +#define FM_MFS3_CSIO_SCSCR *((volatile uint16_t*)(0x40038330UL)) +#define FM4_MFS3_CSIO_SCSCR *((volatile uint16_t*)(0x40038330UL)) +#define FM_MFS3_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038334UL)) +#define FM4_MFS3_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038334UL)) +#define FM_MFS3_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038335UL)) +#define FM4_MFS3_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038335UL)) +#define FM_MFS3_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038338UL)) +#define FM4_MFS3_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038338UL)) +#define FM_MFS3_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003833CUL)) +#define FM4_MFS3_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003833CUL)) +#define FM_MFS3_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003833DUL)) +#define FM4_MFS3_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003833DUL)) +#define FM_MFS3_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038340UL)) +#define FM4_MFS3_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038340UL)) +#define FM_MFS3_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038341UL)) +#define FM4_MFS3_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038341UL)) + +/******************************************************************************* +* MFS Registers MFS4 +* Register Definition +*******************************************************************************/ +#define FM_MFS4_CSIO_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_CSIO_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_I2C_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_I2C_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_LIN_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_LIN_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_UART_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM4_MFS4_UART_SMR *((volatile uint8_t*)(0x40038400UL)) +#define FM_MFS4_CSIO_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_CSIO_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_I2C_IBCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_I2C_IBCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_LIN_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_LIN_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_UART_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM4_MFS4_UART_SCR *((volatile uint8_t*)(0x40038401UL)) +#define FM_MFS4_CSIO_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_CSIO_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_I2C_IBSR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_I2C_IBSR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_LIN_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_LIN_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_UART_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM4_MFS4_UART_ESCR *((volatile uint8_t*)(0x40038404UL)) +#define FM_MFS4_CSIO_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_CSIO_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_I2C_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_I2C_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_LIN_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_LIN_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_UART_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM4_MFS4_UART_SSR *((volatile uint8_t*)(0x40038405UL)) +#define FM_MFS4_CSIO_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_CSIO_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_CSIO_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_CSIO_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_I2C_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_I2C_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_I2C_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_I2C_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_LIN_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_LIN_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_LIN_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_LIN_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_UART_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_UART_RDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_UART_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM4_MFS4_UART_TDR *((volatile uint16_t*)(0x40038408UL)) +#define FM_MFS4_CSIO_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_CSIO_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_I2C_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_I2C_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_LIN_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_LIN_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_UART_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM4_MFS4_UART_BGR *((volatile uint16_t*)(0x4003840CUL)) +#define FM_MFS4_I2C_ISBA *((volatile uint8_t*)(0x40038410UL)) +#define FM4_MFS4_I2C_ISBA *((volatile uint8_t*)(0x40038410UL)) +#define FM_MFS4_I2C_ISMK *((volatile uint8_t*)(0x40038411UL)) +#define FM4_MFS4_I2C_ISMK *((volatile uint8_t*)(0x40038411UL)) +#define FM_MFS4_CSIO_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_CSIO_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_I2C_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_I2C_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_LIN_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_LIN_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_UART_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM4_MFS4_UART_FCR *((volatile uint16_t*)(0x40038414UL)) +#define FM_MFS4_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_I2C_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_I2C_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_LIN_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_LIN_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_UART_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM4_MFS4_UART_FBYTE1 *((volatile uint8_t*)(0x40038418UL)) +#define FM_MFS4_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_I2C_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_I2C_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_LIN_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_LIN_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_UART_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM4_MFS4_UART_FBYTE2 *((volatile uint8_t*)(0x40038419UL)) +#define FM_MFS4_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003841CUL)) +#define FM4_MFS4_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003841CUL)) +#define FM_MFS4_I2C_NFCR *((volatile uint8_t*)(0x4003841CUL)) +#define FM4_MFS4_I2C_NFCR *((volatile uint8_t*)(0x4003841CUL)) +#define FM_MFS4_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003841DUL)) +#define FM4_MFS4_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003841DUL)) +#define FM_MFS4_I2C_EIBCR *((volatile uint8_t*)(0x4003841DUL)) +#define FM4_MFS4_I2C_EIBCR *((volatile uint8_t*)(0x4003841DUL)) +#define FM_MFS4_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038420UL)) +#define FM4_MFS4_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038420UL)) +#define FM_MFS4_CSIO_SACSR *((volatile uint16_t*)(0x40038424UL)) +#define FM4_MFS4_CSIO_SACSR *((volatile uint16_t*)(0x40038424UL)) +#define FM_MFS4_CSIO_STMR *((volatile uint16_t*)(0x40038428UL)) +#define FM4_MFS4_CSIO_STMR *((volatile uint16_t*)(0x40038428UL)) +#define FM_MFS4_CSIO_STMCR *((volatile uint16_t*)(0x4003842CUL)) +#define FM4_MFS4_CSIO_STMCR *((volatile uint16_t*)(0x4003842CUL)) +#define FM_MFS4_CSIO_SCSCR *((volatile uint16_t*)(0x40038430UL)) +#define FM4_MFS4_CSIO_SCSCR *((volatile uint16_t*)(0x40038430UL)) +#define FM_MFS4_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038434UL)) +#define FM4_MFS4_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038434UL)) +#define FM_MFS4_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038435UL)) +#define FM4_MFS4_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038435UL)) +#define FM_MFS4_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038438UL)) +#define FM4_MFS4_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038438UL)) +#define FM_MFS4_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003843CUL)) +#define FM4_MFS4_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003843CUL)) +#define FM_MFS4_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003843DUL)) +#define FM4_MFS4_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003843DUL)) +#define FM_MFS4_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038440UL)) +#define FM4_MFS4_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038440UL)) +#define FM_MFS4_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038441UL)) +#define FM4_MFS4_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038441UL)) + +/******************************************************************************* +* MFS Registers MFS5 +* Register Definition +*******************************************************************************/ +#define FM_MFS5_CSIO_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_CSIO_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_I2C_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_I2C_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_LIN_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_LIN_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_UART_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM4_MFS5_UART_SMR *((volatile uint8_t*)(0x40038500UL)) +#define FM_MFS5_CSIO_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_CSIO_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_I2C_IBCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_I2C_IBCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_LIN_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_LIN_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_UART_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM4_MFS5_UART_SCR *((volatile uint8_t*)(0x40038501UL)) +#define FM_MFS5_CSIO_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_CSIO_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_I2C_IBSR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_I2C_IBSR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_LIN_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_LIN_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_UART_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM4_MFS5_UART_ESCR *((volatile uint8_t*)(0x40038504UL)) +#define FM_MFS5_CSIO_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_CSIO_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_I2C_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_I2C_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_LIN_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_LIN_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_UART_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM4_MFS5_UART_SSR *((volatile uint8_t*)(0x40038505UL)) +#define FM_MFS5_CSIO_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_CSIO_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_CSIO_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_CSIO_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_I2C_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_I2C_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_I2C_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_I2C_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_LIN_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_LIN_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_LIN_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_LIN_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_UART_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_UART_RDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_UART_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM4_MFS5_UART_TDR *((volatile uint16_t*)(0x40038508UL)) +#define FM_MFS5_CSIO_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_CSIO_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_I2C_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_I2C_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_LIN_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_LIN_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_UART_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM4_MFS5_UART_BGR *((volatile uint16_t*)(0x4003850CUL)) +#define FM_MFS5_I2C_ISBA *((volatile uint8_t*)(0x40038510UL)) +#define FM4_MFS5_I2C_ISBA *((volatile uint8_t*)(0x40038510UL)) +#define FM_MFS5_I2C_ISMK *((volatile uint8_t*)(0x40038511UL)) +#define FM4_MFS5_I2C_ISMK *((volatile uint8_t*)(0x40038511UL)) +#define FM_MFS5_CSIO_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_CSIO_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_I2C_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_I2C_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_LIN_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_LIN_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_UART_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM4_MFS5_UART_FCR *((volatile uint16_t*)(0x40038514UL)) +#define FM_MFS5_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_I2C_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_I2C_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_LIN_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_LIN_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_UART_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM4_MFS5_UART_FBYTE1 *((volatile uint8_t*)(0x40038518UL)) +#define FM_MFS5_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_I2C_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_I2C_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_LIN_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_LIN_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_UART_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM4_MFS5_UART_FBYTE2 *((volatile uint8_t*)(0x40038519UL)) +#define FM_MFS5_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003851CUL)) +#define FM4_MFS5_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003851CUL)) +#define FM_MFS5_I2C_NFCR *((volatile uint8_t*)(0x4003851CUL)) +#define FM4_MFS5_I2C_NFCR *((volatile uint8_t*)(0x4003851CUL)) +#define FM_MFS5_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003851DUL)) +#define FM4_MFS5_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003851DUL)) +#define FM_MFS5_I2C_EIBCR *((volatile uint8_t*)(0x4003851DUL)) +#define FM4_MFS5_I2C_EIBCR *((volatile uint8_t*)(0x4003851DUL)) +#define FM_MFS5_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038520UL)) +#define FM4_MFS5_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038520UL)) +#define FM_MFS5_CSIO_SACSR *((volatile uint16_t*)(0x40038524UL)) +#define FM4_MFS5_CSIO_SACSR *((volatile uint16_t*)(0x40038524UL)) +#define FM_MFS5_CSIO_STMR *((volatile uint16_t*)(0x40038528UL)) +#define FM4_MFS5_CSIO_STMR *((volatile uint16_t*)(0x40038528UL)) +#define FM_MFS5_CSIO_STMCR *((volatile uint16_t*)(0x4003852CUL)) +#define FM4_MFS5_CSIO_STMCR *((volatile uint16_t*)(0x4003852CUL)) +#define FM_MFS5_CSIO_SCSCR *((volatile uint16_t*)(0x40038530UL)) +#define FM4_MFS5_CSIO_SCSCR *((volatile uint16_t*)(0x40038530UL)) +#define FM_MFS5_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038534UL)) +#define FM4_MFS5_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038534UL)) +#define FM_MFS5_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038535UL)) +#define FM4_MFS5_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038535UL)) +#define FM_MFS5_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038538UL)) +#define FM4_MFS5_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038538UL)) +#define FM_MFS5_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003853CUL)) +#define FM4_MFS5_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003853CUL)) +#define FM_MFS5_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003853DUL)) +#define FM4_MFS5_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003853DUL)) +#define FM_MFS5_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038540UL)) +#define FM4_MFS5_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038540UL)) +#define FM_MFS5_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038541UL)) +#define FM4_MFS5_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038541UL)) + +/******************************************************************************* +* MFS Registers MFS6 +* Register Definition +*******************************************************************************/ +#define FM_MFS6_CSIO_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_CSIO_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_I2C_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_I2C_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_LIN_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_LIN_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_UART_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM4_MFS6_UART_SMR *((volatile uint8_t*)(0x40038600UL)) +#define FM_MFS6_CSIO_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_CSIO_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_I2C_IBCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_I2C_IBCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_LIN_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_LIN_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_UART_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM4_MFS6_UART_SCR *((volatile uint8_t*)(0x40038601UL)) +#define FM_MFS6_CSIO_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_CSIO_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_I2C_IBSR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_I2C_IBSR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_LIN_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_LIN_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_UART_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM4_MFS6_UART_ESCR *((volatile uint8_t*)(0x40038604UL)) +#define FM_MFS6_CSIO_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_CSIO_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_I2C_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_I2C_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_LIN_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_LIN_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_UART_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM4_MFS6_UART_SSR *((volatile uint8_t*)(0x40038605UL)) +#define FM_MFS6_CSIO_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_CSIO_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_CSIO_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_CSIO_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_I2C_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_I2C_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_I2C_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_I2C_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_LIN_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_LIN_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_LIN_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_LIN_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_UART_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_UART_RDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_UART_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM4_MFS6_UART_TDR *((volatile uint16_t*)(0x40038608UL)) +#define FM_MFS6_CSIO_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_CSIO_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_I2C_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_I2C_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_LIN_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_LIN_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_UART_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM4_MFS6_UART_BGR *((volatile uint16_t*)(0x4003860CUL)) +#define FM_MFS6_I2C_ISBA *((volatile uint8_t*)(0x40038610UL)) +#define FM4_MFS6_I2C_ISBA *((volatile uint8_t*)(0x40038610UL)) +#define FM_MFS6_I2C_ISMK *((volatile uint8_t*)(0x40038611UL)) +#define FM4_MFS6_I2C_ISMK *((volatile uint8_t*)(0x40038611UL)) +#define FM_MFS6_CSIO_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_CSIO_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_I2C_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_I2C_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_LIN_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_LIN_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_UART_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM4_MFS6_UART_FCR *((volatile uint16_t*)(0x40038614UL)) +#define FM_MFS6_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_I2C_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_I2C_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_LIN_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_LIN_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_UART_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM4_MFS6_UART_FBYTE1 *((volatile uint8_t*)(0x40038618UL)) +#define FM_MFS6_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_I2C_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_I2C_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_LIN_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_LIN_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_UART_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM4_MFS6_UART_FBYTE2 *((volatile uint8_t*)(0x40038619UL)) +#define FM_MFS6_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003861CUL)) +#define FM4_MFS6_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003861CUL)) +#define FM_MFS6_I2C_NFCR *((volatile uint8_t*)(0x4003861CUL)) +#define FM4_MFS6_I2C_NFCR *((volatile uint8_t*)(0x4003861CUL)) +#define FM_MFS6_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003861DUL)) +#define FM4_MFS6_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003861DUL)) +#define FM_MFS6_I2C_EIBCR *((volatile uint8_t*)(0x4003861DUL)) +#define FM4_MFS6_I2C_EIBCR *((volatile uint8_t*)(0x4003861DUL)) +#define FM_MFS6_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038620UL)) +#define FM4_MFS6_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038620UL)) +#define FM_MFS6_CSIO_SACSR *((volatile uint16_t*)(0x40038624UL)) +#define FM4_MFS6_CSIO_SACSR *((volatile uint16_t*)(0x40038624UL)) +#define FM_MFS6_CSIO_STMR *((volatile uint16_t*)(0x40038628UL)) +#define FM4_MFS6_CSIO_STMR *((volatile uint16_t*)(0x40038628UL)) +#define FM_MFS6_CSIO_STMCR *((volatile uint16_t*)(0x4003862CUL)) +#define FM4_MFS6_CSIO_STMCR *((volatile uint16_t*)(0x4003862CUL)) +#define FM_MFS6_CSIO_SCSCR *((volatile uint16_t*)(0x40038630UL)) +#define FM4_MFS6_CSIO_SCSCR *((volatile uint16_t*)(0x40038630UL)) +#define FM_MFS6_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038634UL)) +#define FM4_MFS6_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038634UL)) +#define FM_MFS6_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038635UL)) +#define FM4_MFS6_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038635UL)) +#define FM_MFS6_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038638UL)) +#define FM4_MFS6_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038638UL)) +#define FM_MFS6_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003863CUL)) +#define FM4_MFS6_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003863CUL)) +#define FM_MFS6_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003863DUL)) +#define FM4_MFS6_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003863DUL)) +#define FM_MFS6_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038640UL)) +#define FM4_MFS6_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038640UL)) +#define FM_MFS6_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038641UL)) +#define FM4_MFS6_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038641UL)) + +/******************************************************************************* +* MFS Registers MFS7 +* Register Definition +*******************************************************************************/ +#define FM_MFS7_CSIO_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_CSIO_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_I2C_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_I2C_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_LIN_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_LIN_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_UART_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM4_MFS7_UART_SMR *((volatile uint8_t*)(0x40038700UL)) +#define FM_MFS7_CSIO_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_CSIO_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_I2C_IBCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_I2C_IBCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_LIN_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_LIN_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_UART_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM4_MFS7_UART_SCR *((volatile uint8_t*)(0x40038701UL)) +#define FM_MFS7_CSIO_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_CSIO_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_I2C_IBSR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_I2C_IBSR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_LIN_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_LIN_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_UART_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM4_MFS7_UART_ESCR *((volatile uint8_t*)(0x40038704UL)) +#define FM_MFS7_CSIO_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_CSIO_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_I2C_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_I2C_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_LIN_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_LIN_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_UART_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM4_MFS7_UART_SSR *((volatile uint8_t*)(0x40038705UL)) +#define FM_MFS7_CSIO_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_CSIO_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_CSIO_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_CSIO_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_I2C_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_I2C_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_I2C_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_I2C_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_LIN_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_LIN_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_LIN_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_LIN_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_UART_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_UART_RDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_UART_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM4_MFS7_UART_TDR *((volatile uint16_t*)(0x40038708UL)) +#define FM_MFS7_CSIO_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_CSIO_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_I2C_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_I2C_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_LIN_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_LIN_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_UART_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM4_MFS7_UART_BGR *((volatile uint16_t*)(0x4003870CUL)) +#define FM_MFS7_I2C_ISBA *((volatile uint8_t*)(0x40038710UL)) +#define FM4_MFS7_I2C_ISBA *((volatile uint8_t*)(0x40038710UL)) +#define FM_MFS7_I2C_ISMK *((volatile uint8_t*)(0x40038711UL)) +#define FM4_MFS7_I2C_ISMK *((volatile uint8_t*)(0x40038711UL)) +#define FM_MFS7_CSIO_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_CSIO_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_I2C_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_I2C_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_LIN_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_LIN_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_UART_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM4_MFS7_UART_FCR *((volatile uint16_t*)(0x40038714UL)) +#define FM_MFS7_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_I2C_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_I2C_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_LIN_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_LIN_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_UART_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM4_MFS7_UART_FBYTE1 *((volatile uint8_t*)(0x40038718UL)) +#define FM_MFS7_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_I2C_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_I2C_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_LIN_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_LIN_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_UART_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM4_MFS7_UART_FBYTE2 *((volatile uint8_t*)(0x40038719UL)) +#define FM_MFS7_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003871CUL)) +#define FM4_MFS7_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003871CUL)) +#define FM_MFS7_I2C_NFCR *((volatile uint8_t*)(0x4003871CUL)) +#define FM4_MFS7_I2C_NFCR *((volatile uint8_t*)(0x4003871CUL)) +#define FM_MFS7_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003871DUL)) +#define FM4_MFS7_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003871DUL)) +#define FM_MFS7_I2C_EIBCR *((volatile uint8_t*)(0x4003871DUL)) +#define FM4_MFS7_I2C_EIBCR *((volatile uint8_t*)(0x4003871DUL)) +#define FM_MFS7_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038720UL)) +#define FM4_MFS7_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038720UL)) +#define FM_MFS7_CSIO_SACSR *((volatile uint16_t*)(0x40038724UL)) +#define FM4_MFS7_CSIO_SACSR *((volatile uint16_t*)(0x40038724UL)) +#define FM_MFS7_CSIO_STMR *((volatile uint16_t*)(0x40038728UL)) +#define FM4_MFS7_CSIO_STMR *((volatile uint16_t*)(0x40038728UL)) +#define FM_MFS7_CSIO_STMCR *((volatile uint16_t*)(0x4003872CUL)) +#define FM4_MFS7_CSIO_STMCR *((volatile uint16_t*)(0x4003872CUL)) +#define FM_MFS7_CSIO_SCSCR *((volatile uint16_t*)(0x40038730UL)) +#define FM4_MFS7_CSIO_SCSCR *((volatile uint16_t*)(0x40038730UL)) +#define FM_MFS7_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038734UL)) +#define FM4_MFS7_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038734UL)) +#define FM_MFS7_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038735UL)) +#define FM4_MFS7_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038735UL)) +#define FM_MFS7_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038738UL)) +#define FM4_MFS7_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038738UL)) +#define FM_MFS7_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003873CUL)) +#define FM4_MFS7_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003873CUL)) +#define FM_MFS7_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003873DUL)) +#define FM4_MFS7_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003873DUL)) +#define FM_MFS7_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038740UL)) +#define FM4_MFS7_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038740UL)) +#define FM_MFS7_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038741UL)) +#define FM4_MFS7_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038741UL)) + +/******************************************************************************* +* MFS Registers MFS8 +* Register Definition +*******************************************************************************/ +#define FM_MFS8_CSIO_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_CSIO_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_I2C_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_I2C_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_LIN_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_LIN_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_UART_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM4_MFS8_UART_SMR *((volatile uint8_t*)(0x40038800UL)) +#define FM_MFS8_CSIO_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_CSIO_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_I2C_IBCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_I2C_IBCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_LIN_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_LIN_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_UART_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM4_MFS8_UART_SCR *((volatile uint8_t*)(0x40038801UL)) +#define FM_MFS8_CSIO_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_CSIO_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_I2C_IBSR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_I2C_IBSR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_LIN_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_LIN_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_UART_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM4_MFS8_UART_ESCR *((volatile uint8_t*)(0x40038804UL)) +#define FM_MFS8_CSIO_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_CSIO_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_I2C_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_I2C_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_LIN_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_LIN_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_UART_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM4_MFS8_UART_SSR *((volatile uint8_t*)(0x40038805UL)) +#define FM_MFS8_CSIO_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_CSIO_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_CSIO_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_CSIO_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_I2C_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_I2C_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_I2C_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_I2C_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_LIN_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_LIN_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_LIN_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_LIN_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_UART_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_UART_RDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_UART_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM4_MFS8_UART_TDR *((volatile uint16_t*)(0x40038808UL)) +#define FM_MFS8_CSIO_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_CSIO_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_I2C_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_I2C_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_LIN_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_LIN_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_UART_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM4_MFS8_UART_BGR *((volatile uint16_t*)(0x4003880CUL)) +#define FM_MFS8_I2C_ISBA *((volatile uint8_t*)(0x40038810UL)) +#define FM4_MFS8_I2C_ISBA *((volatile uint8_t*)(0x40038810UL)) +#define FM_MFS8_I2C_ISMK *((volatile uint8_t*)(0x40038811UL)) +#define FM4_MFS8_I2C_ISMK *((volatile uint8_t*)(0x40038811UL)) +#define FM_MFS8_CSIO_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_CSIO_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_I2C_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_I2C_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_LIN_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_LIN_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_UART_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM4_MFS8_UART_FCR *((volatile uint16_t*)(0x40038814UL)) +#define FM_MFS8_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_I2C_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_I2C_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_LIN_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_LIN_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_UART_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM4_MFS8_UART_FBYTE1 *((volatile uint8_t*)(0x40038818UL)) +#define FM_MFS8_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_I2C_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_I2C_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_LIN_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_LIN_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_UART_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM4_MFS8_UART_FBYTE2 *((volatile uint8_t*)(0x40038819UL)) +#define FM_MFS8_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003881CUL)) +#define FM4_MFS8_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003881CUL)) +#define FM_MFS8_I2C_NFCR *((volatile uint8_t*)(0x4003881CUL)) +#define FM4_MFS8_I2C_NFCR *((volatile uint8_t*)(0x4003881CUL)) +#define FM_MFS8_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003881DUL)) +#define FM4_MFS8_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003881DUL)) +#define FM_MFS8_I2C_EIBCR *((volatile uint8_t*)(0x4003881DUL)) +#define FM4_MFS8_I2C_EIBCR *((volatile uint8_t*)(0x4003881DUL)) +#define FM_MFS8_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038820UL)) +#define FM4_MFS8_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038820UL)) +#define FM_MFS8_CSIO_SACSR *((volatile uint16_t*)(0x40038824UL)) +#define FM4_MFS8_CSIO_SACSR *((volatile uint16_t*)(0x40038824UL)) +#define FM_MFS8_CSIO_STMR *((volatile uint16_t*)(0x40038828UL)) +#define FM4_MFS8_CSIO_STMR *((volatile uint16_t*)(0x40038828UL)) +#define FM_MFS8_CSIO_STMCR *((volatile uint16_t*)(0x4003882CUL)) +#define FM4_MFS8_CSIO_STMCR *((volatile uint16_t*)(0x4003882CUL)) +#define FM_MFS8_CSIO_SCSCR *((volatile uint16_t*)(0x40038830UL)) +#define FM4_MFS8_CSIO_SCSCR *((volatile uint16_t*)(0x40038830UL)) +#define FM_MFS8_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038834UL)) +#define FM4_MFS8_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038834UL)) +#define FM_MFS8_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038835UL)) +#define FM4_MFS8_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038835UL)) +#define FM_MFS8_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038838UL)) +#define FM4_MFS8_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038838UL)) +#define FM_MFS8_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003883CUL)) +#define FM4_MFS8_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003883CUL)) +#define FM_MFS8_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003883DUL)) +#define FM4_MFS8_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003883DUL)) +#define FM_MFS8_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038840UL)) +#define FM4_MFS8_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038840UL)) +#define FM_MFS8_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038841UL)) +#define FM4_MFS8_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038841UL)) + +/******************************************************************************* +* MFS Registers MFS9 +* Register Definition +*******************************************************************************/ +#define FM_MFS9_CSIO_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_CSIO_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_I2C_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_I2C_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_LIN_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_LIN_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_UART_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM4_MFS9_UART_SMR *((volatile uint8_t*)(0x40038900UL)) +#define FM_MFS9_CSIO_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_CSIO_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_I2C_IBCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_I2C_IBCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_LIN_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_LIN_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_UART_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM4_MFS9_UART_SCR *((volatile uint8_t*)(0x40038901UL)) +#define FM_MFS9_CSIO_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_CSIO_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_I2C_IBSR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_I2C_IBSR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_LIN_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_LIN_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_UART_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM4_MFS9_UART_ESCR *((volatile uint8_t*)(0x40038904UL)) +#define FM_MFS9_CSIO_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_CSIO_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_I2C_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_I2C_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_LIN_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_LIN_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_UART_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM4_MFS9_UART_SSR *((volatile uint8_t*)(0x40038905UL)) +#define FM_MFS9_CSIO_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_CSIO_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_CSIO_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_CSIO_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_I2C_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_I2C_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_I2C_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_I2C_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_LIN_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_LIN_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_LIN_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_LIN_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_UART_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_UART_RDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_UART_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM4_MFS9_UART_TDR *((volatile uint16_t*)(0x40038908UL)) +#define FM_MFS9_CSIO_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_CSIO_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_I2C_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_I2C_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_LIN_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_LIN_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_UART_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM4_MFS9_UART_BGR *((volatile uint16_t*)(0x4003890CUL)) +#define FM_MFS9_I2C_ISBA *((volatile uint8_t*)(0x40038910UL)) +#define FM4_MFS9_I2C_ISBA *((volatile uint8_t*)(0x40038910UL)) +#define FM_MFS9_I2C_ISMK *((volatile uint8_t*)(0x40038911UL)) +#define FM4_MFS9_I2C_ISMK *((volatile uint8_t*)(0x40038911UL)) +#define FM_MFS9_CSIO_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_CSIO_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_I2C_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_I2C_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_LIN_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_LIN_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_UART_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM4_MFS9_UART_FCR *((volatile uint16_t*)(0x40038914UL)) +#define FM_MFS9_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_CSIO_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_I2C_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_I2C_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_LIN_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_LIN_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_UART_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM4_MFS9_UART_FBYTE1 *((volatile uint8_t*)(0x40038918UL)) +#define FM_MFS9_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_CSIO_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_I2C_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_I2C_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_LIN_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_LIN_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_UART_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM4_MFS9_UART_FBYTE2 *((volatile uint8_t*)(0x40038919UL)) +#define FM_MFS9_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003891CUL)) +#define FM4_MFS9_CSIO_SCSTR0 *((volatile uint8_t*)(0x4003891CUL)) +#define FM_MFS9_I2C_NFCR *((volatile uint8_t*)(0x4003891CUL)) +#define FM4_MFS9_I2C_NFCR *((volatile uint8_t*)(0x4003891CUL)) +#define FM_MFS9_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003891DUL)) +#define FM4_MFS9_CSIO_SCSTR1 *((volatile uint8_t*)(0x4003891DUL)) +#define FM_MFS9_I2C_EIBCR *((volatile uint8_t*)(0x4003891DUL)) +#define FM4_MFS9_I2C_EIBCR *((volatile uint8_t*)(0x4003891DUL)) +#define FM_MFS9_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038920UL)) +#define FM4_MFS9_CSIO_SCSTR32 *((volatile uint16_t*)(0x40038920UL)) +#define FM_MFS9_CSIO_SACSR *((volatile uint16_t*)(0x40038924UL)) +#define FM4_MFS9_CSIO_SACSR *((volatile uint16_t*)(0x40038924UL)) +#define FM_MFS9_CSIO_STMR *((volatile uint16_t*)(0x40038928UL)) +#define FM4_MFS9_CSIO_STMR *((volatile uint16_t*)(0x40038928UL)) +#define FM_MFS9_CSIO_STMCR *((volatile uint16_t*)(0x4003892CUL)) +#define FM4_MFS9_CSIO_STMCR *((volatile uint16_t*)(0x4003892CUL)) +#define FM_MFS9_CSIO_SCSCR *((volatile uint16_t*)(0x40038930UL)) +#define FM4_MFS9_CSIO_SCSCR *((volatile uint16_t*)(0x40038930UL)) +#define FM_MFS9_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038934UL)) +#define FM4_MFS9_CSIO_SCSFR0 *((volatile uint8_t*)(0x40038934UL)) +#define FM_MFS9_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038935UL)) +#define FM4_MFS9_CSIO_SCSFR1 *((volatile uint8_t*)(0x40038935UL)) +#define FM_MFS9_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038938UL)) +#define FM4_MFS9_CSIO_SCSFR2 *((volatile uint8_t*)(0x40038938UL)) +#define FM_MFS9_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003893CUL)) +#define FM4_MFS9_CSIO_TBYTE0 *((volatile uint8_t*)(0x4003893CUL)) +#define FM_MFS9_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003893DUL)) +#define FM4_MFS9_CSIO_TBYTE1 *((volatile uint8_t*)(0x4003893DUL)) +#define FM_MFS9_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038940UL)) +#define FM4_MFS9_CSIO_TBYTE2 *((volatile uint8_t*)(0x40038940UL)) +#define FM_MFS9_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038941UL)) +#define FM4_MFS9_CSIO_TBYTE3 *((volatile uint8_t*)(0x40038941UL)) + +/******************************************************************************* +* MFT_PPG Registers MFT_PPG +* Register Definition +*******************************************************************************/ +#define FM_MFT_PPG_TTCR0 *((volatile uint8_t*)(0x40024001UL)) +#define FM4_MFT_PPG_TTCR0 *((volatile uint8_t*)(0x40024001UL)) +#define FM_MFT_PPG_COMP0 *((volatile uint8_t*)(0x40024009UL)) +#define FM4_MFT_PPG_COMP0 *((volatile uint8_t*)(0x40024009UL)) +#define FM_MFT_PPG_COMP2 *((volatile uint8_t*)(0x4002400CUL)) +#define FM4_MFT_PPG_COMP2 *((volatile uint8_t*)(0x4002400CUL)) +#define FM_MFT_PPG_COMP4 *((volatile uint8_t*)(0x40024011UL)) +#define FM4_MFT_PPG_COMP4 *((volatile uint8_t*)(0x40024011UL)) +#define FM_MFT_PPG_COMP6 *((volatile uint8_t*)(0x40024014UL)) +#define FM4_MFT_PPG_COMP6 *((volatile uint8_t*)(0x40024014UL)) +#define FM_MFT_PPG_TTCR1 *((volatile uint8_t*)(0x40024021UL)) +#define FM4_MFT_PPG_TTCR1 *((volatile uint8_t*)(0x40024021UL)) +#define FM_MFT_PPG_COMP1 *((volatile uint8_t*)(0x40024029UL)) +#define FM4_MFT_PPG_COMP1 *((volatile uint8_t*)(0x40024029UL)) +#define FM_MFT_PPG_COMP3 *((volatile uint8_t*)(0x4002402CUL)) +#define FM4_MFT_PPG_COMP3 *((volatile uint8_t*)(0x4002402CUL)) +#define FM_MFT_PPG_COMP5 *((volatile uint8_t*)(0x40024031UL)) +#define FM4_MFT_PPG_COMP5 *((volatile uint8_t*)(0x40024031UL)) +#define FM_MFT_PPG_COMP7 *((volatile uint8_t*)(0x40024034UL)) +#define FM4_MFT_PPG_COMP7 *((volatile uint8_t*)(0x40024034UL)) +#define FM_MFT_PPG_TTCR2 *((volatile uint8_t*)(0x40024041UL)) +#define FM4_MFT_PPG_TTCR2 *((volatile uint8_t*)(0x40024041UL)) +#define FM_MFT_PPG_COMP8 *((volatile uint8_t*)(0x40024049UL)) +#define FM4_MFT_PPG_COMP8 *((volatile uint8_t*)(0x40024049UL)) +#define FM_MFT_PPG_COMP10 *((volatile uint8_t*)(0x4002404CUL)) +#define FM4_MFT_PPG_COMP10 *((volatile uint8_t*)(0x4002404CUL)) +#define FM_MFT_PPG_COMP12 *((volatile uint8_t*)(0x40024051UL)) +#define FM4_MFT_PPG_COMP12 *((volatile uint8_t*)(0x40024051UL)) +#define FM_MFT_PPG_COMP14 *((volatile uint8_t*)(0x40024054UL)) +#define FM4_MFT_PPG_COMP14 *((volatile uint8_t*)(0x40024054UL)) +#define FM_MFT_PPG_TRG0 *((volatile uint16_t*)(0x40024100UL)) +#define FM4_MFT_PPG_TRG0 *((volatile uint16_t*)(0x40024100UL)) +#define FM_MFT_PPG_REVC0 *((volatile uint16_t*)(0x40024104UL)) +#define FM4_MFT_PPG_REVC0 *((volatile uint16_t*)(0x40024104UL)) +#define FM_MFT_PPG_TRG1 *((volatile uint16_t*)(0x40024140UL)) +#define FM4_MFT_PPG_TRG1 *((volatile uint16_t*)(0x40024140UL)) +#define FM_MFT_PPG_REVC1 *((volatile uint16_t*)(0x40024144UL)) +#define FM4_MFT_PPG_REVC1 *((volatile uint16_t*)(0x40024144UL)) +#define FM_MFT_PPG_PPGC1 *((volatile uint8_t*)(0x40024200UL)) +#define FM4_MFT_PPG_PPGC1 *((volatile uint8_t*)(0x40024200UL)) +#define FM_MFT_PPG_PPGC0 *((volatile uint8_t*)(0x40024201UL)) +#define FM4_MFT_PPG_PPGC0 *((volatile uint8_t*)(0x40024201UL)) +#define FM_MFT_PPG_PPGC3 *((volatile uint8_t*)(0x40024204UL)) +#define FM4_MFT_PPG_PPGC3 *((volatile uint8_t*)(0x40024204UL)) +#define FM_MFT_PPG_PPGC2 *((volatile uint8_t*)(0x40024205UL)) +#define FM4_MFT_PPG_PPGC2 *((volatile uint8_t*)(0x40024205UL)) +#define FM_MFT_PPG_PRLL0 *((volatile uint8_t*)(0x40024208UL)) +#define FM4_MFT_PPG_PRLL0 *((volatile uint8_t*)(0x40024208UL)) +#define FM_MFT_PPG_PRLH0 *((volatile uint8_t*)(0x40024209UL)) +#define FM4_MFT_PPG_PRLH0 *((volatile uint8_t*)(0x40024209UL)) +#define FM_MFT_PPG_PRLL1 *((volatile uint8_t*)(0x4002420CUL)) +#define FM4_MFT_PPG_PRLL1 *((volatile uint8_t*)(0x4002420CUL)) +#define FM_MFT_PPG_PRLH1 *((volatile uint8_t*)(0x4002420DUL)) +#define FM4_MFT_PPG_PRLH1 *((volatile uint8_t*)(0x4002420DUL)) +#define FM_MFT_PPG_PRLL2 *((volatile uint8_t*)(0x40024210UL)) +#define FM4_MFT_PPG_PRLL2 *((volatile uint8_t*)(0x40024210UL)) +#define FM_MFT_PPG_PRLH2 *((volatile uint8_t*)(0x40024211UL)) +#define FM4_MFT_PPG_PRLH2 *((volatile uint8_t*)(0x40024211UL)) +#define FM_MFT_PPG_PRLL3 *((volatile uint8_t*)(0x40024214UL)) +#define FM4_MFT_PPG_PRLL3 *((volatile uint8_t*)(0x40024214UL)) +#define FM_MFT_PPG_PRLH3 *((volatile uint8_t*)(0x40024215UL)) +#define FM4_MFT_PPG_PRLH3 *((volatile uint8_t*)(0x40024215UL)) +#define FM_MFT_PPG_GATEC0 *((volatile uint8_t*)(0x40024218UL)) +#define FM4_MFT_PPG_GATEC0 *((volatile uint8_t*)(0x40024218UL)) +#define FM_MFT_PPG_PPGC5 *((volatile uint8_t*)(0x40024240UL)) +#define FM4_MFT_PPG_PPGC5 *((volatile uint8_t*)(0x40024240UL)) +#define FM_MFT_PPG_PPGC4 *((volatile uint8_t*)(0x40024241UL)) +#define FM4_MFT_PPG_PPGC4 *((volatile uint8_t*)(0x40024241UL)) +#define FM_MFT_PPG_PPGC7 *((volatile uint8_t*)(0x40024244UL)) +#define FM4_MFT_PPG_PPGC7 *((volatile uint8_t*)(0x40024244UL)) +#define FM_MFT_PPG_PPGC6 *((volatile uint8_t*)(0x40024245UL)) +#define FM4_MFT_PPG_PPGC6 *((volatile uint8_t*)(0x40024245UL)) +#define FM_MFT_PPG_PRLL4 *((volatile uint8_t*)(0x40024248UL)) +#define FM4_MFT_PPG_PRLL4 *((volatile uint8_t*)(0x40024248UL)) +#define FM_MFT_PPG_PRLH4 *((volatile uint8_t*)(0x40024249UL)) +#define FM4_MFT_PPG_PRLH4 *((volatile uint8_t*)(0x40024249UL)) +#define FM_MFT_PPG_PRLL5 *((volatile uint8_t*)(0x4002424CUL)) +#define FM4_MFT_PPG_PRLL5 *((volatile uint8_t*)(0x4002424CUL)) +#define FM_MFT_PPG_PRLH5 *((volatile uint8_t*)(0x4002424DUL)) +#define FM4_MFT_PPG_PRLH5 *((volatile uint8_t*)(0x4002424DUL)) +#define FM_MFT_PPG_PRLL6 *((volatile uint8_t*)(0x40024250UL)) +#define FM4_MFT_PPG_PRLL6 *((volatile uint8_t*)(0x40024250UL)) +#define FM_MFT_PPG_PRLH6 *((volatile uint8_t*)(0x40024251UL)) +#define FM4_MFT_PPG_PRLH6 *((volatile uint8_t*)(0x40024251UL)) +#define FM_MFT_PPG_PRLL7 *((volatile uint8_t*)(0x40024254UL)) +#define FM4_MFT_PPG_PRLL7 *((volatile uint8_t*)(0x40024254UL)) +#define FM_MFT_PPG_PRLH7 *((volatile uint8_t*)(0x40024255UL)) +#define FM4_MFT_PPG_PRLH7 *((volatile uint8_t*)(0x40024255UL)) +#define FM_MFT_PPG_GATEC4 *((volatile uint8_t*)(0x40024258UL)) +#define FM4_MFT_PPG_GATEC4 *((volatile uint8_t*)(0x40024258UL)) +#define FM_MFT_PPG_PPGC9 *((volatile uint8_t*)(0x40024280UL)) +#define FM4_MFT_PPG_PPGC9 *((volatile uint8_t*)(0x40024280UL)) +#define FM_MFT_PPG_PPGC8 *((volatile uint8_t*)(0x40024281UL)) +#define FM4_MFT_PPG_PPGC8 *((volatile uint8_t*)(0x40024281UL)) +#define FM_MFT_PPG_PPGC11 *((volatile uint8_t*)(0x40024284UL)) +#define FM4_MFT_PPG_PPGC11 *((volatile uint8_t*)(0x40024284UL)) +#define FM_MFT_PPG_PPGC10 *((volatile uint8_t*)(0x40024285UL)) +#define FM4_MFT_PPG_PPGC10 *((volatile uint8_t*)(0x40024285UL)) +#define FM_MFT_PPG_PRLL8 *((volatile uint8_t*)(0x40024288UL)) +#define FM4_MFT_PPG_PRLL8 *((volatile uint8_t*)(0x40024288UL)) +#define FM_MFT_PPG_PRLH8 *((volatile uint8_t*)(0x40024289UL)) +#define FM4_MFT_PPG_PRLH8 *((volatile uint8_t*)(0x40024289UL)) +#define FM_MFT_PPG_PRLL9 *((volatile uint8_t*)(0x4002428CUL)) +#define FM4_MFT_PPG_PRLL9 *((volatile uint8_t*)(0x4002428CUL)) +#define FM_MFT_PPG_PRLH9 *((volatile uint8_t*)(0x4002428DUL)) +#define FM4_MFT_PPG_PRLH9 *((volatile uint8_t*)(0x4002428DUL)) +#define FM_MFT_PPG_PRLL10 *((volatile uint8_t*)(0x40024290UL)) +#define FM4_MFT_PPG_PRLL10 *((volatile uint8_t*)(0x40024290UL)) +#define FM_MFT_PPG_PRLH10 *((volatile uint8_t*)(0x40024291UL)) +#define FM4_MFT_PPG_PRLH10 *((volatile uint8_t*)(0x40024291UL)) +#define FM_MFT_PPG_PRLL11 *((volatile uint8_t*)(0x40024294UL)) +#define FM4_MFT_PPG_PRLL11 *((volatile uint8_t*)(0x40024294UL)) +#define FM_MFT_PPG_PRLH11 *((volatile uint8_t*)(0x40024295UL)) +#define FM4_MFT_PPG_PRLH11 *((volatile uint8_t*)(0x40024295UL)) +#define FM_MFT_PPG_GATEC8 *((volatile uint8_t*)(0x40024298UL)) +#define FM4_MFT_PPG_GATEC8 *((volatile uint8_t*)(0x40024298UL)) +#define FM_MFT_PPG_PPGC13 *((volatile uint8_t*)(0x400242C0UL)) +#define FM4_MFT_PPG_PPGC13 *((volatile uint8_t*)(0x400242C0UL)) +#define FM_MFT_PPG_PPGC12 *((volatile uint8_t*)(0x400242C1UL)) +#define FM4_MFT_PPG_PPGC12 *((volatile uint8_t*)(0x400242C1UL)) +#define FM_MFT_PPG_PPGC15 *((volatile uint8_t*)(0x400242C4UL)) +#define FM4_MFT_PPG_PPGC15 *((volatile uint8_t*)(0x400242C4UL)) +#define FM_MFT_PPG_PPGC14 *((volatile uint8_t*)(0x400242C5UL)) +#define FM4_MFT_PPG_PPGC14 *((volatile uint8_t*)(0x400242C5UL)) +#define FM_MFT_PPG_PRLL12 *((volatile uint8_t*)(0x400242C8UL)) +#define FM4_MFT_PPG_PRLL12 *((volatile uint8_t*)(0x400242C8UL)) +#define FM_MFT_PPG_PRLH12 *((volatile uint8_t*)(0x400242C9UL)) +#define FM4_MFT_PPG_PRLH12 *((volatile uint8_t*)(0x400242C9UL)) +#define FM_MFT_PPG_PRLL13 *((volatile uint8_t*)(0x400242CCUL)) +#define FM4_MFT_PPG_PRLL13 *((volatile uint8_t*)(0x400242CCUL)) +#define FM_MFT_PPG_PRLH13 *((volatile uint8_t*)(0x400242CDUL)) +#define FM4_MFT_PPG_PRLH13 *((volatile uint8_t*)(0x400242CDUL)) +#define FM_MFT_PPG_PRLL14 *((volatile uint8_t*)(0x400242D0UL)) +#define FM4_MFT_PPG_PRLL14 *((volatile uint8_t*)(0x400242D0UL)) +#define FM_MFT_PPG_PRLH14 *((volatile uint8_t*)(0x400242D1UL)) +#define FM4_MFT_PPG_PRLH14 *((volatile uint8_t*)(0x400242D1UL)) +#define FM_MFT_PPG_PRLL15 *((volatile uint8_t*)(0x400242D4UL)) +#define FM4_MFT_PPG_PRLL15 *((volatile uint8_t*)(0x400242D4UL)) +#define FM_MFT_PPG_PRLH15 *((volatile uint8_t*)(0x400242D5UL)) +#define FM4_MFT_PPG_PRLH15 *((volatile uint8_t*)(0x400242D5UL)) +#define FM_MFT_PPG_GATEC12 *((volatile uint8_t*)(0x400242D8UL)) +#define FM4_MFT_PPG_GATEC12 *((volatile uint8_t*)(0x400242D8UL)) +#define FM_MFT_PPG_PPGC17 *((volatile uint8_t*)(0x40024300UL)) +#define FM4_MFT_PPG_PPGC17 *((volatile uint8_t*)(0x40024300UL)) +#define FM_MFT_PPG_PPGC16 *((volatile uint8_t*)(0x40024301UL)) +#define FM4_MFT_PPG_PPGC16 *((volatile uint8_t*)(0x40024301UL)) +#define FM_MFT_PPG_PPGC19 *((volatile uint8_t*)(0x40024304UL)) +#define FM4_MFT_PPG_PPGC19 *((volatile uint8_t*)(0x40024304UL)) +#define FM_MFT_PPG_PPGC18 *((volatile uint8_t*)(0x40024305UL)) +#define FM4_MFT_PPG_PPGC18 *((volatile uint8_t*)(0x40024305UL)) +#define FM_MFT_PPG_PRLL16 *((volatile uint8_t*)(0x40024308UL)) +#define FM4_MFT_PPG_PRLL16 *((volatile uint8_t*)(0x40024308UL)) +#define FM_MFT_PPG_PRLH16 *((volatile uint8_t*)(0x40024309UL)) +#define FM4_MFT_PPG_PRLH16 *((volatile uint8_t*)(0x40024309UL)) +#define FM_MFT_PPG_PRLL17 *((volatile uint8_t*)(0x4002430CUL)) +#define FM4_MFT_PPG_PRLL17 *((volatile uint8_t*)(0x4002430CUL)) +#define FM_MFT_PPG_PRLH17 *((volatile uint8_t*)(0x4002430DUL)) +#define FM4_MFT_PPG_PRLH17 *((volatile uint8_t*)(0x4002430DUL)) +#define FM_MFT_PPG_PRLL18 *((volatile uint8_t*)(0x40024310UL)) +#define FM4_MFT_PPG_PRLL18 *((volatile uint8_t*)(0x40024310UL)) +#define FM_MFT_PPG_PRLH18 *((volatile uint8_t*)(0x40024311UL)) +#define FM4_MFT_PPG_PRLH18 *((volatile uint8_t*)(0x40024311UL)) +#define FM_MFT_PPG_PRLL19 *((volatile uint8_t*)(0x40024314UL)) +#define FM4_MFT_PPG_PRLL19 *((volatile uint8_t*)(0x40024314UL)) +#define FM_MFT_PPG_PRLH19 *((volatile uint8_t*)(0x40024315UL)) +#define FM4_MFT_PPG_PRLH19 *((volatile uint8_t*)(0x40024315UL)) +#define FM_MFT_PPG_GATEC16 *((volatile uint8_t*)(0x40024318UL)) +#define FM4_MFT_PPG_GATEC16 *((volatile uint8_t*)(0x40024318UL)) +#define FM_MFT_PPG_PPGC21 *((volatile uint8_t*)(0x40024340UL)) +#define FM4_MFT_PPG_PPGC21 *((volatile uint8_t*)(0x40024340UL)) +#define FM_MFT_PPG_PPGC20 *((volatile uint8_t*)(0x40024341UL)) +#define FM4_MFT_PPG_PPGC20 *((volatile uint8_t*)(0x40024341UL)) +#define FM_MFT_PPG_PPGC23 *((volatile uint8_t*)(0x40024344UL)) +#define FM4_MFT_PPG_PPGC23 *((volatile uint8_t*)(0x40024344UL)) +#define FM_MFT_PPG_PPGC22 *((volatile uint8_t*)(0x40024345UL)) +#define FM4_MFT_PPG_PPGC22 *((volatile uint8_t*)(0x40024345UL)) +#define FM_MFT_PPG_PRLL20 *((volatile uint8_t*)(0x40024348UL)) +#define FM4_MFT_PPG_PRLL20 *((volatile uint8_t*)(0x40024348UL)) +#define FM_MFT_PPG_PRLH20 *((volatile uint8_t*)(0x40024349UL)) +#define FM4_MFT_PPG_PRLH20 *((volatile uint8_t*)(0x40024349UL)) +#define FM_MFT_PPG_PRLL21 *((volatile uint8_t*)(0x4002434CUL)) +#define FM4_MFT_PPG_PRLL21 *((volatile uint8_t*)(0x4002434CUL)) +#define FM_MFT_PPG_PRLH21 *((volatile uint8_t*)(0x4002434DUL)) +#define FM4_MFT_PPG_PRLH21 *((volatile uint8_t*)(0x4002434DUL)) +#define FM_MFT_PPG_PRLL22 *((volatile uint8_t*)(0x40024350UL)) +#define FM4_MFT_PPG_PRLL22 *((volatile uint8_t*)(0x40024350UL)) +#define FM_MFT_PPG_PRLH22 *((volatile uint8_t*)(0x40024351UL)) +#define FM4_MFT_PPG_PRLH22 *((volatile uint8_t*)(0x40024351UL)) +#define FM_MFT_PPG_PRLL23 *((volatile uint8_t*)(0x40024354UL)) +#define FM4_MFT_PPG_PRLL23 *((volatile uint8_t*)(0x40024354UL)) +#define FM_MFT_PPG_PRLH23 *((volatile uint8_t*)(0x40024355UL)) +#define FM4_MFT_PPG_PRLH23 *((volatile uint8_t*)(0x40024355UL)) +#define FM_MFT_PPG_GATEC20 *((volatile uint8_t*)(0x40024358UL)) +#define FM4_MFT_PPG_GATEC20 *((volatile uint8_t*)(0x40024358UL)) + +/******************************************************************************* +* MFT Registers MFT0 +* Register Definition +*******************************************************************************/ +#define FM_MFT0_OCU_OCCP0 *((volatile uint16_t*)(0x40020102UL)) +#define FM4_MFT0_OCU_OCCP0 *((volatile uint16_t*)(0x40020102UL)) +#define FM_MFT0_OCU_OCCP1 *((volatile uint16_t*)(0x40020106UL)) +#define FM4_MFT0_OCU_OCCP1 *((volatile uint16_t*)(0x40020106UL)) +#define FM_MFT0_OCU_OCCP2 *((volatile uint16_t*)(0x4002010AUL)) +#define FM4_MFT0_OCU_OCCP2 *((volatile uint16_t*)(0x4002010AUL)) +#define FM_MFT0_OCU_OCCP3 *((volatile uint16_t*)(0x4002010EUL)) +#define FM4_MFT0_OCU_OCCP3 *((volatile uint16_t*)(0x4002010EUL)) +#define FM_MFT0_OCU_OCCP4 *((volatile uint16_t*)(0x40020112UL)) +#define FM4_MFT0_OCU_OCCP4 *((volatile uint16_t*)(0x40020112UL)) +#define FM_MFT0_OCU_OCCP5 *((volatile uint16_t*)(0x40020116UL)) +#define FM4_MFT0_OCU_OCCP5 *((volatile uint16_t*)(0x40020116UL)) +#define FM_MFT0_OCU_OCSA10 *((volatile uint8_t*)(0x40020118UL)) +#define FM4_MFT0_OCU_OCSA10 *((volatile uint8_t*)(0x40020118UL)) +#define FM_MFT0_OCU_OCSB10 *((volatile uint8_t*)(0x40020119UL)) +#define FM4_MFT0_OCU_OCSB10 *((volatile uint8_t*)(0x40020119UL)) +#define FM_MFT0_OCU_OCSD10 *((volatile uint16_t*)(0x4002011AUL)) +#define FM4_MFT0_OCU_OCSD10 *((volatile uint16_t*)(0x4002011AUL)) +#define FM_MFT0_OCU_OCSA32 *((volatile uint8_t*)(0x4002011CUL)) +#define FM4_MFT0_OCU_OCSA32 *((volatile uint8_t*)(0x4002011CUL)) +#define FM_MFT0_OCU_OCSB32 *((volatile uint8_t*)(0x4002011DUL)) +#define FM4_MFT0_OCU_OCSB32 *((volatile uint8_t*)(0x4002011DUL)) +#define FM_MFT0_OCU_OCSD32 *((volatile uint16_t*)(0x4002011EUL)) +#define FM4_MFT0_OCU_OCSD32 *((volatile uint16_t*)(0x4002011EUL)) +#define FM_MFT0_OCU_OCSA54 *((volatile uint8_t*)(0x40020120UL)) +#define FM4_MFT0_OCU_OCSA54 *((volatile uint8_t*)(0x40020120UL)) +#define FM_MFT0_OCU_OCSB54 *((volatile uint8_t*)(0x40020121UL)) +#define FM4_MFT0_OCU_OCSB54 *((volatile uint8_t*)(0x40020121UL)) +#define FM_MFT0_OCU_OCSD54 *((volatile uint16_t*)(0x40020122UL)) +#define FM4_MFT0_OCU_OCSD54 *((volatile uint16_t*)(0x40020122UL)) +#define FM_MFT0_OCU_OCSC *((volatile uint8_t*)(0x40020125UL)) +#define FM4_MFT0_OCU_OCSC *((volatile uint8_t*)(0x40020125UL)) +#define FM_MFT0_OCU_OCSE0 *((volatile uint16_t*)(0x40020128UL)) +#define FM4_MFT0_OCU_OCSE0 *((volatile uint16_t*)(0x40020128UL)) +#define FM_MFT0_OCU_OCSE1 *((volatile uint32_t*)(0x4002012CUL)) +#define FM4_MFT0_OCU_OCSE1 *((volatile uint32_t*)(0x4002012CUL)) +#define FM_MFT0_OCU_OCSE2 *((volatile uint16_t*)(0x40020130UL)) +#define FM4_MFT0_OCU_OCSE2 *((volatile uint16_t*)(0x40020130UL)) +#define FM_MFT0_OCU_OCSE3 *((volatile uint32_t*)(0x40020134UL)) +#define FM4_MFT0_OCU_OCSE3 *((volatile uint32_t*)(0x40020134UL)) +#define FM_MFT0_OCU_OCSE4 *((volatile uint16_t*)(0x40020138UL)) +#define FM4_MFT0_OCU_OCSE4 *((volatile uint16_t*)(0x40020138UL)) +#define FM_MFT0_OCU_OCSE5 *((volatile uint32_t*)(0x4002013CUL)) +#define FM4_MFT0_OCU_OCSE5 *((volatile uint32_t*)(0x4002013CUL)) +#define FM_MFT0_FRT_TCCP0 *((volatile uint16_t*)(0x40020142UL)) +#define FM4_MFT0_FRT_TCCP0 *((volatile uint16_t*)(0x40020142UL)) +#define FM_MFT0_FRT_TCDT0 *((volatile uint16_t*)(0x40020146UL)) +#define FM4_MFT0_FRT_TCDT0 *((volatile uint16_t*)(0x40020146UL)) +#define FM_MFT0_FRT_TCSA0 *((volatile uint16_t*)(0x40020148UL)) +#define FM4_MFT0_FRT_TCSA0 *((volatile uint16_t*)(0x40020148UL)) +#define FM_MFT0_FRT_TCSC0 *((volatile uint16_t*)(0x4002014AUL)) +#define FM4_MFT0_FRT_TCSC0 *((volatile uint16_t*)(0x4002014AUL)) +#define FM_MFT0_FRT_TCCP1 *((volatile uint16_t*)(0x4002014EUL)) +#define FM4_MFT0_FRT_TCCP1 *((volatile uint16_t*)(0x4002014EUL)) +#define FM_MFT0_FRT_TCDT1 *((volatile uint16_t*)(0x40020152UL)) +#define FM4_MFT0_FRT_TCDT1 *((volatile uint16_t*)(0x40020152UL)) +#define FM_MFT0_FRT_TCSA1 *((volatile uint16_t*)(0x40020154UL)) +#define FM4_MFT0_FRT_TCSA1 *((volatile uint16_t*)(0x40020154UL)) +#define FM_MFT0_FRT_TCSC1 *((volatile uint16_t*)(0x40020156UL)) +#define FM4_MFT0_FRT_TCSC1 *((volatile uint16_t*)(0x40020156UL)) +#define FM_MFT0_FRT_TCCP2 *((volatile uint16_t*)(0x4002015AUL)) +#define FM4_MFT0_FRT_TCCP2 *((volatile uint16_t*)(0x4002015AUL)) +#define FM_MFT0_FRT_TCDT2 *((volatile uint16_t*)(0x4002015EUL)) +#define FM4_MFT0_FRT_TCDT2 *((volatile uint16_t*)(0x4002015EUL)) +#define FM_MFT0_FRT_TCSA2 *((volatile uint16_t*)(0x40020160UL)) +#define FM4_MFT0_FRT_TCSA2 *((volatile uint16_t*)(0x40020160UL)) +#define FM_MFT0_FRT_TCSC2 *((volatile uint16_t*)(0x40020162UL)) +#define FM4_MFT0_FRT_TCSC2 *((volatile uint16_t*)(0x40020162UL)) +#define FM_MFT0_FRT_TCAL *((volatile uint32_t*)(0x40020164UL)) +#define FM4_MFT0_FRT_TCAL *((volatile uint32_t*)(0x40020164UL)) +#define FM_MFT0_OCU_OCFS10 *((volatile uint8_t*)(0x40020168UL)) +#define FM4_MFT0_OCU_OCFS10 *((volatile uint8_t*)(0x40020168UL)) +#define FM_MFT0_OCU_OCFS32 *((volatile uint8_t*)(0x40020169UL)) +#define FM4_MFT0_OCU_OCFS32 *((volatile uint8_t*)(0x40020169UL)) +#define FM_MFT0_OCU_OCFS54 *((volatile uint8_t*)(0x4002016AUL)) +#define FM4_MFT0_OCU_OCFS54 *((volatile uint8_t*)(0x4002016AUL)) +#define FM_MFT0_ICU_ICFS10 *((volatile uint8_t*)(0x4002016CUL)) +#define FM4_MFT0_ICU_ICFS10 *((volatile uint8_t*)(0x4002016CUL)) +#define FM_MFT0_ICU_ICFS32 *((volatile uint8_t*)(0x4002016DUL)) +#define FM4_MFT0_ICU_ICFS32 *((volatile uint8_t*)(0x4002016DUL)) +#define FM_MFT0_ADCMP_ACFS10 *((volatile uint8_t*)(0x40020170UL)) +#define FM4_MFT0_ADCMP_ACFS10 *((volatile uint8_t*)(0x40020170UL)) +#define FM_MFT0_ADCMP_ACFS32 *((volatile uint8_t*)(0x40020171UL)) +#define FM4_MFT0_ADCMP_ACFS32 *((volatile uint8_t*)(0x40020171UL)) +#define FM_MFT0_ADCMP_ACFS54 *((volatile uint8_t*)(0x40020172UL)) +#define FM4_MFT0_ADCMP_ACFS54 *((volatile uint8_t*)(0x40020172UL)) +#define FM_MFT0_ICU_ICCP0 *((volatile uint16_t*)(0x40020176UL)) +#define FM4_MFT0_ICU_ICCP0 *((volatile uint16_t*)(0x40020176UL)) +#define FM_MFT0_ICU_ICCP1 *((volatile uint16_t*)(0x4002017AUL)) +#define FM4_MFT0_ICU_ICCP1 *((volatile uint16_t*)(0x4002017AUL)) +#define FM_MFT0_ICU_ICCP2 *((volatile uint16_t*)(0x4002017EUL)) +#define FM4_MFT0_ICU_ICCP2 *((volatile uint16_t*)(0x4002017EUL)) +#define FM_MFT0_ICU_ICCP3 *((volatile uint16_t*)(0x40020182UL)) +#define FM4_MFT0_ICU_ICCP3 *((volatile uint16_t*)(0x40020182UL)) +#define FM_MFT0_ICU_ICSA10 *((volatile uint8_t*)(0x40020184UL)) +#define FM4_MFT0_ICU_ICSA10 *((volatile uint8_t*)(0x40020184UL)) +#define FM_MFT0_ICU_ICSB10 *((volatile uint8_t*)(0x40020185UL)) +#define FM4_MFT0_ICU_ICSB10 *((volatile uint8_t*)(0x40020185UL)) +#define FM_MFT0_ICU_ICSA32 *((volatile uint8_t*)(0x40020188UL)) +#define FM4_MFT0_ICU_ICSA32 *((volatile uint8_t*)(0x40020188UL)) +#define FM_MFT0_ICU_ICSB32 *((volatile uint8_t*)(0x40020189UL)) +#define FM4_MFT0_ICU_ICSB32 *((volatile uint8_t*)(0x40020189UL)) +#define FM_MFT0_WFG_WFTF10 *((volatile uint16_t*)(0x4002018EUL)) +#define FM4_MFT0_WFG_WFTF10 *((volatile uint16_t*)(0x4002018EUL)) +#define FM_MFT0_WFG_WFTA10 *((volatile uint16_t*)(0x40020190UL)) +#define FM4_MFT0_WFG_WFTA10 *((volatile uint16_t*)(0x40020190UL)) +#define FM_MFT0_WFG_WFTB10 *((volatile uint16_t*)(0x40020192UL)) +#define FM4_MFT0_WFG_WFTB10 *((volatile uint16_t*)(0x40020192UL)) +#define FM_MFT0_WFG_WFTF32 *((volatile uint16_t*)(0x40020196UL)) +#define FM4_MFT0_WFG_WFTF32 *((volatile uint16_t*)(0x40020196UL)) +#define FM_MFT0_WFG_WFTA32 *((volatile uint16_t*)(0x40020198UL)) +#define FM4_MFT0_WFG_WFTA32 *((volatile uint16_t*)(0x40020198UL)) +#define FM_MFT0_WFG_WFTB32 *((volatile uint16_t*)(0x4002019AUL)) +#define FM4_MFT0_WFG_WFTB32 *((volatile uint16_t*)(0x4002019AUL)) +#define FM_MFT0_WFG_WFTF54 *((volatile uint16_t*)(0x4002019EUL)) +#define FM4_MFT0_WFG_WFTF54 *((volatile uint16_t*)(0x4002019EUL)) +#define FM_MFT0_WFG_WFTA54 *((volatile uint16_t*)(0x400201A0UL)) +#define FM4_MFT0_WFG_WFTA54 *((volatile uint16_t*)(0x400201A0UL)) +#define FM_MFT0_WFG_WFTB54 *((volatile uint16_t*)(0x400201A2UL)) +#define FM4_MFT0_WFG_WFTB54 *((volatile uint16_t*)(0x400201A2UL)) +#define FM_MFT0_WFG_WFSA10 *((volatile uint16_t*)(0x400201A4UL)) +#define FM4_MFT0_WFG_WFSA10 *((volatile uint16_t*)(0x400201A4UL)) +#define FM_MFT0_WFG_WFSA32 *((volatile uint16_t*)(0x400201A8UL)) +#define FM4_MFT0_WFG_WFSA32 *((volatile uint16_t*)(0x400201A8UL)) +#define FM_MFT0_WFG_WFSA54 *((volatile uint16_t*)(0x400201ACUL)) +#define FM4_MFT0_WFG_WFSA54 *((volatile uint16_t*)(0x400201ACUL)) +#define FM_MFT0_WFG_WFIR *((volatile uint16_t*)(0x400201B0UL)) +#define FM4_MFT0_WFG_WFIR *((volatile uint16_t*)(0x400201B0UL)) +#define FM_MFT0_WFG_NZCL *((volatile uint16_t*)(0x400201B4UL)) +#define FM4_MFT0_WFG_NZCL *((volatile uint16_t*)(0x400201B4UL)) +#define FM_MFT0_ADCMP_ACMP0 *((volatile uint16_t*)(0x400201BAUL)) +#define FM4_MFT0_ADCMP_ACMP0 *((volatile uint16_t*)(0x400201BAUL)) +#define FM_MFT0_ADCMP_ACMP1 *((volatile uint16_t*)(0x400201BEUL)) +#define FM4_MFT0_ADCMP_ACMP1 *((volatile uint16_t*)(0x400201BEUL)) +#define FM_MFT0_ADCMP_ACMP2 *((volatile uint16_t*)(0x400201C2UL)) +#define FM4_MFT0_ADCMP_ACMP2 *((volatile uint16_t*)(0x400201C2UL)) +#define FM_MFT0_ADCMP_ACMP3 *((volatile uint16_t*)(0x400201C6UL)) +#define FM4_MFT0_ADCMP_ACMP3 *((volatile uint16_t*)(0x400201C6UL)) +#define FM_MFT0_ADCMP_ACMP4 *((volatile uint16_t*)(0x400201CAUL)) +#define FM4_MFT0_ADCMP_ACMP4 *((volatile uint16_t*)(0x400201CAUL)) +#define FM_MFT0_ADCMP_ACMP5 *((volatile uint16_t*)(0x400201CEUL)) +#define FM4_MFT0_ADCMP_ACMP5 *((volatile uint16_t*)(0x400201CEUL)) +#define FM_MFT0_ADCMP_ACSA *((volatile uint16_t*)(0x400201D0UL)) +#define FM4_MFT0_ADCMP_ACSA *((volatile uint16_t*)(0x400201D0UL)) +#define FM_MFT0_ADCMP_ACSC0 *((volatile uint8_t*)(0x400201D4UL)) +#define FM4_MFT0_ADCMP_ACSC0 *((volatile uint8_t*)(0x400201D4UL)) +#define FM_MFT0_ADCMP_ACSD0 *((volatile uint8_t*)(0x400201D5UL)) +#define FM4_MFT0_ADCMP_ACSD0 *((volatile uint8_t*)(0x400201D5UL)) +#define FM_MFT0_ADCMP_ACMC0 *((volatile uint8_t*)(0x400201D6UL)) +#define FM4_MFT0_ADCMP_ACMC0 *((volatile uint8_t*)(0x400201D6UL)) +#define FM_MFT0_ADCMP_ACSC1 *((volatile uint8_t*)(0x400201D8UL)) +#define FM4_MFT0_ADCMP_ACSC1 *((volatile uint8_t*)(0x400201D8UL)) +#define FM_MFT0_ADCMP_ACSD1 *((volatile uint8_t*)(0x400201D9UL)) +#define FM4_MFT0_ADCMP_ACSD1 *((volatile uint8_t*)(0x400201D9UL)) +#define FM_MFT0_ADCMP_ACMC1 *((volatile uint8_t*)(0x400201DAUL)) +#define FM4_MFT0_ADCMP_ACMC1 *((volatile uint8_t*)(0x400201DAUL)) +#define FM_MFT0_ADCMP_ACSC2 *((volatile uint8_t*)(0x400201DCUL)) +#define FM4_MFT0_ADCMP_ACSC2 *((volatile uint8_t*)(0x400201DCUL)) +#define FM_MFT0_ADCMP_ACSD2 *((volatile uint8_t*)(0x400201DDUL)) +#define FM4_MFT0_ADCMP_ACSD2 *((volatile uint8_t*)(0x400201DDUL)) +#define FM_MFT0_ADCMP_ACMC2 *((volatile uint8_t*)(0x400201DEUL)) +#define FM4_MFT0_ADCMP_ACMC2 *((volatile uint8_t*)(0x400201DEUL)) +#define FM_MFT0_ADCMP_ACSC3 *((volatile uint8_t*)(0x400201E0UL)) +#define FM4_MFT0_ADCMP_ACSC3 *((volatile uint8_t*)(0x400201E0UL)) +#define FM_MFT0_ADCMP_ACSD3 *((volatile uint8_t*)(0x400201E1UL)) +#define FM4_MFT0_ADCMP_ACSD3 *((volatile uint8_t*)(0x400201E1UL)) +#define FM_MFT0_ADCMP_ACMC3 *((volatile uint8_t*)(0x400201E2UL)) +#define FM4_MFT0_ADCMP_ACMC3 *((volatile uint8_t*)(0x400201E2UL)) +#define FM_MFT0_ADCMP_ACSC4 *((volatile uint8_t*)(0x400201E4UL)) +#define FM4_MFT0_ADCMP_ACSC4 *((volatile uint8_t*)(0x400201E4UL)) +#define FM_MFT0_ADCMP_ACSD4 *((volatile uint8_t*)(0x400201E5UL)) +#define FM4_MFT0_ADCMP_ACSD4 *((volatile uint8_t*)(0x400201E5UL)) +#define FM_MFT0_ADCMP_ACMC4 *((volatile uint8_t*)(0x400201E6UL)) +#define FM4_MFT0_ADCMP_ACMC4 *((volatile uint8_t*)(0x400201E6UL)) +#define FM_MFT0_ADCMP_ACSC5 *((volatile uint8_t*)(0x400201E8UL)) +#define FM4_MFT0_ADCMP_ACSC5 *((volatile uint8_t*)(0x400201E8UL)) +#define FM_MFT0_ADCMP_ACSD5 *((volatile uint8_t*)(0x400201E9UL)) +#define FM4_MFT0_ADCMP_ACSD5 *((volatile uint8_t*)(0x400201E9UL)) +#define FM_MFT0_ADCMP_ACMC5 *((volatile uint8_t*)(0x400201EAUL)) +#define FM4_MFT0_ADCMP_ACMC5 *((volatile uint8_t*)(0x400201EAUL)) +#define FM_MFT0_FRT_TCSD *((volatile uint8_t*)(0x400201ECUL)) +#define FM4_MFT0_FRT_TCSD *((volatile uint8_t*)(0x400201ECUL)) + +/******************************************************************************* +* MFT Registers MFT1 +* Register Definition +*******************************************************************************/ +#define FM_MFT1_OCU_OCCP0 *((volatile uint16_t*)(0x40021102UL)) +#define FM4_MFT1_OCU_OCCP0 *((volatile uint16_t*)(0x40021102UL)) +#define FM_MFT1_OCU_OCCP1 *((volatile uint16_t*)(0x40021106UL)) +#define FM4_MFT1_OCU_OCCP1 *((volatile uint16_t*)(0x40021106UL)) +#define FM_MFT1_OCU_OCCP2 *((volatile uint16_t*)(0x4002110AUL)) +#define FM4_MFT1_OCU_OCCP2 *((volatile uint16_t*)(0x4002110AUL)) +#define FM_MFT1_OCU_OCCP3 *((volatile uint16_t*)(0x4002110EUL)) +#define FM4_MFT1_OCU_OCCP3 *((volatile uint16_t*)(0x4002110EUL)) +#define FM_MFT1_OCU_OCCP4 *((volatile uint16_t*)(0x40021112UL)) +#define FM4_MFT1_OCU_OCCP4 *((volatile uint16_t*)(0x40021112UL)) +#define FM_MFT1_OCU_OCCP5 *((volatile uint16_t*)(0x40021116UL)) +#define FM4_MFT1_OCU_OCCP5 *((volatile uint16_t*)(0x40021116UL)) +#define FM_MFT1_OCU_OCSA10 *((volatile uint8_t*)(0x40021118UL)) +#define FM4_MFT1_OCU_OCSA10 *((volatile uint8_t*)(0x40021118UL)) +#define FM_MFT1_OCU_OCSB10 *((volatile uint8_t*)(0x40021119UL)) +#define FM4_MFT1_OCU_OCSB10 *((volatile uint8_t*)(0x40021119UL)) +#define FM_MFT1_OCU_OCSD10 *((volatile uint16_t*)(0x4002111AUL)) +#define FM4_MFT1_OCU_OCSD10 *((volatile uint16_t*)(0x4002111AUL)) +#define FM_MFT1_OCU_OCSA32 *((volatile uint8_t*)(0x4002111CUL)) +#define FM4_MFT1_OCU_OCSA32 *((volatile uint8_t*)(0x4002111CUL)) +#define FM_MFT1_OCU_OCSB32 *((volatile uint8_t*)(0x4002111DUL)) +#define FM4_MFT1_OCU_OCSB32 *((volatile uint8_t*)(0x4002111DUL)) +#define FM_MFT1_OCU_OCSD32 *((volatile uint16_t*)(0x4002111EUL)) +#define FM4_MFT1_OCU_OCSD32 *((volatile uint16_t*)(0x4002111EUL)) +#define FM_MFT1_OCU_OCSA54 *((volatile uint8_t*)(0x40021120UL)) +#define FM4_MFT1_OCU_OCSA54 *((volatile uint8_t*)(0x40021120UL)) +#define FM_MFT1_OCU_OCSB54 *((volatile uint8_t*)(0x40021121UL)) +#define FM4_MFT1_OCU_OCSB54 *((volatile uint8_t*)(0x40021121UL)) +#define FM_MFT1_OCU_OCSD54 *((volatile uint16_t*)(0x40021122UL)) +#define FM4_MFT1_OCU_OCSD54 *((volatile uint16_t*)(0x40021122UL)) +#define FM_MFT1_OCU_OCSC *((volatile uint8_t*)(0x40021125UL)) +#define FM4_MFT1_OCU_OCSC *((volatile uint8_t*)(0x40021125UL)) +#define FM_MFT1_OCU_OCSE0 *((volatile uint16_t*)(0x40021128UL)) +#define FM4_MFT1_OCU_OCSE0 *((volatile uint16_t*)(0x40021128UL)) +#define FM_MFT1_OCU_OCSE1 *((volatile uint32_t*)(0x4002112CUL)) +#define FM4_MFT1_OCU_OCSE1 *((volatile uint32_t*)(0x4002112CUL)) +#define FM_MFT1_OCU_OCSE2 *((volatile uint16_t*)(0x40021130UL)) +#define FM4_MFT1_OCU_OCSE2 *((volatile uint16_t*)(0x40021130UL)) +#define FM_MFT1_OCU_OCSE3 *((volatile uint32_t*)(0x40021134UL)) +#define FM4_MFT1_OCU_OCSE3 *((volatile uint32_t*)(0x40021134UL)) +#define FM_MFT1_OCU_OCSE4 *((volatile uint16_t*)(0x40021138UL)) +#define FM4_MFT1_OCU_OCSE4 *((volatile uint16_t*)(0x40021138UL)) +#define FM_MFT1_OCU_OCSE5 *((volatile uint32_t*)(0x4002113CUL)) +#define FM4_MFT1_OCU_OCSE5 *((volatile uint32_t*)(0x4002113CUL)) +#define FM_MFT1_FRT_TCCP0 *((volatile uint16_t*)(0x40021142UL)) +#define FM4_MFT1_FRT_TCCP0 *((volatile uint16_t*)(0x40021142UL)) +#define FM_MFT1_FRT_TCDT0 *((volatile uint16_t*)(0x40021146UL)) +#define FM4_MFT1_FRT_TCDT0 *((volatile uint16_t*)(0x40021146UL)) +#define FM_MFT1_FRT_TCSA0 *((volatile uint16_t*)(0x40021148UL)) +#define FM4_MFT1_FRT_TCSA0 *((volatile uint16_t*)(0x40021148UL)) +#define FM_MFT1_FRT_TCSC0 *((volatile uint16_t*)(0x4002114AUL)) +#define FM4_MFT1_FRT_TCSC0 *((volatile uint16_t*)(0x4002114AUL)) +#define FM_MFT1_FRT_TCCP1 *((volatile uint16_t*)(0x4002114EUL)) +#define FM4_MFT1_FRT_TCCP1 *((volatile uint16_t*)(0x4002114EUL)) +#define FM_MFT1_FRT_TCDT1 *((volatile uint16_t*)(0x40021152UL)) +#define FM4_MFT1_FRT_TCDT1 *((volatile uint16_t*)(0x40021152UL)) +#define FM_MFT1_FRT_TCSA1 *((volatile uint16_t*)(0x40021154UL)) +#define FM4_MFT1_FRT_TCSA1 *((volatile uint16_t*)(0x40021154UL)) +#define FM_MFT1_FRT_TCSC1 *((volatile uint16_t*)(0x40021156UL)) +#define FM4_MFT1_FRT_TCSC1 *((volatile uint16_t*)(0x40021156UL)) +#define FM_MFT1_FRT_TCCP2 *((volatile uint16_t*)(0x4002115AUL)) +#define FM4_MFT1_FRT_TCCP2 *((volatile uint16_t*)(0x4002115AUL)) +#define FM_MFT1_FRT_TCDT2 *((volatile uint16_t*)(0x4002115EUL)) +#define FM4_MFT1_FRT_TCDT2 *((volatile uint16_t*)(0x4002115EUL)) +#define FM_MFT1_FRT_TCSA2 *((volatile uint16_t*)(0x40021160UL)) +#define FM4_MFT1_FRT_TCSA2 *((volatile uint16_t*)(0x40021160UL)) +#define FM_MFT1_FRT_TCSC2 *((volatile uint16_t*)(0x40021162UL)) +#define FM4_MFT1_FRT_TCSC2 *((volatile uint16_t*)(0x40021162UL)) +#define FM_MFT1_FRT_TCAL *((volatile uint32_t*)(0x40021164UL)) +#define FM4_MFT1_FRT_TCAL *((volatile uint32_t*)(0x40021164UL)) +#define FM_MFT1_OCU_OCFS10 *((volatile uint8_t*)(0x40021168UL)) +#define FM4_MFT1_OCU_OCFS10 *((volatile uint8_t*)(0x40021168UL)) +#define FM_MFT1_OCU_OCFS32 *((volatile uint8_t*)(0x40021169UL)) +#define FM4_MFT1_OCU_OCFS32 *((volatile uint8_t*)(0x40021169UL)) +#define FM_MFT1_OCU_OCFS54 *((volatile uint8_t*)(0x4002116AUL)) +#define FM4_MFT1_OCU_OCFS54 *((volatile uint8_t*)(0x4002116AUL)) +#define FM_MFT1_ICU_ICFS10 *((volatile uint8_t*)(0x4002116CUL)) +#define FM4_MFT1_ICU_ICFS10 *((volatile uint8_t*)(0x4002116CUL)) +#define FM_MFT1_ICU_ICFS32 *((volatile uint8_t*)(0x4002116DUL)) +#define FM4_MFT1_ICU_ICFS32 *((volatile uint8_t*)(0x4002116DUL)) +#define FM_MFT1_ADCMP_ACFS10 *((volatile uint8_t*)(0x40021170UL)) +#define FM4_MFT1_ADCMP_ACFS10 *((volatile uint8_t*)(0x40021170UL)) +#define FM_MFT1_ADCMP_ACFS32 *((volatile uint8_t*)(0x40021171UL)) +#define FM4_MFT1_ADCMP_ACFS32 *((volatile uint8_t*)(0x40021171UL)) +#define FM_MFT1_ADCMP_ACFS54 *((volatile uint8_t*)(0x40021172UL)) +#define FM4_MFT1_ADCMP_ACFS54 *((volatile uint8_t*)(0x40021172UL)) +#define FM_MFT1_ICU_ICCP0 *((volatile uint16_t*)(0x40021176UL)) +#define FM4_MFT1_ICU_ICCP0 *((volatile uint16_t*)(0x40021176UL)) +#define FM_MFT1_ICU_ICCP1 *((volatile uint16_t*)(0x4002117AUL)) +#define FM4_MFT1_ICU_ICCP1 *((volatile uint16_t*)(0x4002117AUL)) +#define FM_MFT1_ICU_ICCP2 *((volatile uint16_t*)(0x4002117EUL)) +#define FM4_MFT1_ICU_ICCP2 *((volatile uint16_t*)(0x4002117EUL)) +#define FM_MFT1_ICU_ICCP3 *((volatile uint16_t*)(0x40021182UL)) +#define FM4_MFT1_ICU_ICCP3 *((volatile uint16_t*)(0x40021182UL)) +#define FM_MFT1_ICU_ICSA10 *((volatile uint8_t*)(0x40021184UL)) +#define FM4_MFT1_ICU_ICSA10 *((volatile uint8_t*)(0x40021184UL)) +#define FM_MFT1_ICU_ICSB10 *((volatile uint8_t*)(0x40021185UL)) +#define FM4_MFT1_ICU_ICSB10 *((volatile uint8_t*)(0x40021185UL)) +#define FM_MFT1_ICU_ICSA32 *((volatile uint8_t*)(0x40021188UL)) +#define FM4_MFT1_ICU_ICSA32 *((volatile uint8_t*)(0x40021188UL)) +#define FM_MFT1_ICU_ICSB32 *((volatile uint8_t*)(0x40021189UL)) +#define FM4_MFT1_ICU_ICSB32 *((volatile uint8_t*)(0x40021189UL)) +#define FM_MFT1_WFG_WFTF10 *((volatile uint16_t*)(0x4002118EUL)) +#define FM4_MFT1_WFG_WFTF10 *((volatile uint16_t*)(0x4002118EUL)) +#define FM_MFT1_WFG_WFTA10 *((volatile uint16_t*)(0x40021190UL)) +#define FM4_MFT1_WFG_WFTA10 *((volatile uint16_t*)(0x40021190UL)) +#define FM_MFT1_WFG_WFTB10 *((volatile uint16_t*)(0x40021192UL)) +#define FM4_MFT1_WFG_WFTB10 *((volatile uint16_t*)(0x40021192UL)) +#define FM_MFT1_WFG_WFTF32 *((volatile uint16_t*)(0x40021196UL)) +#define FM4_MFT1_WFG_WFTF32 *((volatile uint16_t*)(0x40021196UL)) +#define FM_MFT1_WFG_WFTA32 *((volatile uint16_t*)(0x40021198UL)) +#define FM4_MFT1_WFG_WFTA32 *((volatile uint16_t*)(0x40021198UL)) +#define FM_MFT1_WFG_WFTB32 *((volatile uint16_t*)(0x4002119AUL)) +#define FM4_MFT1_WFG_WFTB32 *((volatile uint16_t*)(0x4002119AUL)) +#define FM_MFT1_WFG_WFTF54 *((volatile uint16_t*)(0x4002119EUL)) +#define FM4_MFT1_WFG_WFTF54 *((volatile uint16_t*)(0x4002119EUL)) +#define FM_MFT1_WFG_WFTA54 *((volatile uint16_t*)(0x400211A0UL)) +#define FM4_MFT1_WFG_WFTA54 *((volatile uint16_t*)(0x400211A0UL)) +#define FM_MFT1_WFG_WFTB54 *((volatile uint16_t*)(0x400211A2UL)) +#define FM4_MFT1_WFG_WFTB54 *((volatile uint16_t*)(0x400211A2UL)) +#define FM_MFT1_WFG_WFSA10 *((volatile uint16_t*)(0x400211A4UL)) +#define FM4_MFT1_WFG_WFSA10 *((volatile uint16_t*)(0x400211A4UL)) +#define FM_MFT1_WFG_WFSA32 *((volatile uint16_t*)(0x400211A8UL)) +#define FM4_MFT1_WFG_WFSA32 *((volatile uint16_t*)(0x400211A8UL)) +#define FM_MFT1_WFG_WFSA54 *((volatile uint16_t*)(0x400211ACUL)) +#define FM4_MFT1_WFG_WFSA54 *((volatile uint16_t*)(0x400211ACUL)) +#define FM_MFT1_WFG_WFIR *((volatile uint16_t*)(0x400211B0UL)) +#define FM4_MFT1_WFG_WFIR *((volatile uint16_t*)(0x400211B0UL)) +#define FM_MFT1_WFG_NZCL *((volatile uint16_t*)(0x400211B4UL)) +#define FM4_MFT1_WFG_NZCL *((volatile uint16_t*)(0x400211B4UL)) +#define FM_MFT1_ADCMP_ACMP0 *((volatile uint16_t*)(0x400211BAUL)) +#define FM4_MFT1_ADCMP_ACMP0 *((volatile uint16_t*)(0x400211BAUL)) +#define FM_MFT1_ADCMP_ACMP1 *((volatile uint16_t*)(0x400211BEUL)) +#define FM4_MFT1_ADCMP_ACMP1 *((volatile uint16_t*)(0x400211BEUL)) +#define FM_MFT1_ADCMP_ACMP2 *((volatile uint16_t*)(0x400211C2UL)) +#define FM4_MFT1_ADCMP_ACMP2 *((volatile uint16_t*)(0x400211C2UL)) +#define FM_MFT1_ADCMP_ACMP3 *((volatile uint16_t*)(0x400211C6UL)) +#define FM4_MFT1_ADCMP_ACMP3 *((volatile uint16_t*)(0x400211C6UL)) +#define FM_MFT1_ADCMP_ACMP4 *((volatile uint16_t*)(0x400211CAUL)) +#define FM4_MFT1_ADCMP_ACMP4 *((volatile uint16_t*)(0x400211CAUL)) +#define FM_MFT1_ADCMP_ACMP5 *((volatile uint16_t*)(0x400211CEUL)) +#define FM4_MFT1_ADCMP_ACMP5 *((volatile uint16_t*)(0x400211CEUL)) +#define FM_MFT1_ADCMP_ACSA *((volatile uint16_t*)(0x400211D0UL)) +#define FM4_MFT1_ADCMP_ACSA *((volatile uint16_t*)(0x400211D0UL)) +#define FM_MFT1_ADCMP_ACSC0 *((volatile uint8_t*)(0x400211D4UL)) +#define FM4_MFT1_ADCMP_ACSC0 *((volatile uint8_t*)(0x400211D4UL)) +#define FM_MFT1_ADCMP_ACSD0 *((volatile uint8_t*)(0x400211D5UL)) +#define FM4_MFT1_ADCMP_ACSD0 *((volatile uint8_t*)(0x400211D5UL)) +#define FM_MFT1_ADCMP_ACMC0 *((volatile uint8_t*)(0x400211D6UL)) +#define FM4_MFT1_ADCMP_ACMC0 *((volatile uint8_t*)(0x400211D6UL)) +#define FM_MFT1_ADCMP_ACSC1 *((volatile uint8_t*)(0x400211D8UL)) +#define FM4_MFT1_ADCMP_ACSC1 *((volatile uint8_t*)(0x400211D8UL)) +#define FM_MFT1_ADCMP_ACSD1 *((volatile uint8_t*)(0x400211D9UL)) +#define FM4_MFT1_ADCMP_ACSD1 *((volatile uint8_t*)(0x400211D9UL)) +#define FM_MFT1_ADCMP_ACMC1 *((volatile uint8_t*)(0x400211DAUL)) +#define FM4_MFT1_ADCMP_ACMC1 *((volatile uint8_t*)(0x400211DAUL)) +#define FM_MFT1_ADCMP_ACSC2 *((volatile uint8_t*)(0x400211DCUL)) +#define FM4_MFT1_ADCMP_ACSC2 *((volatile uint8_t*)(0x400211DCUL)) +#define FM_MFT1_ADCMP_ACSD2 *((volatile uint8_t*)(0x400211DDUL)) +#define FM4_MFT1_ADCMP_ACSD2 *((volatile uint8_t*)(0x400211DDUL)) +#define FM_MFT1_ADCMP_ACMC2 *((volatile uint8_t*)(0x400211DEUL)) +#define FM4_MFT1_ADCMP_ACMC2 *((volatile uint8_t*)(0x400211DEUL)) +#define FM_MFT1_ADCMP_ACSC3 *((volatile uint8_t*)(0x400211E0UL)) +#define FM4_MFT1_ADCMP_ACSC3 *((volatile uint8_t*)(0x400211E0UL)) +#define FM_MFT1_ADCMP_ACSD3 *((volatile uint8_t*)(0x400211E1UL)) +#define FM4_MFT1_ADCMP_ACSD3 *((volatile uint8_t*)(0x400211E1UL)) +#define FM_MFT1_ADCMP_ACMC3 *((volatile uint8_t*)(0x400211E2UL)) +#define FM4_MFT1_ADCMP_ACMC3 *((volatile uint8_t*)(0x400211E2UL)) +#define FM_MFT1_ADCMP_ACSC4 *((volatile uint8_t*)(0x400211E4UL)) +#define FM4_MFT1_ADCMP_ACSC4 *((volatile uint8_t*)(0x400211E4UL)) +#define FM_MFT1_ADCMP_ACSD4 *((volatile uint8_t*)(0x400211E5UL)) +#define FM4_MFT1_ADCMP_ACSD4 *((volatile uint8_t*)(0x400211E5UL)) +#define FM_MFT1_ADCMP_ACMC4 *((volatile uint8_t*)(0x400211E6UL)) +#define FM4_MFT1_ADCMP_ACMC4 *((volatile uint8_t*)(0x400211E6UL)) +#define FM_MFT1_ADCMP_ACSC5 *((volatile uint8_t*)(0x400211E8UL)) +#define FM4_MFT1_ADCMP_ACSC5 *((volatile uint8_t*)(0x400211E8UL)) +#define FM_MFT1_ADCMP_ACSD5 *((volatile uint8_t*)(0x400211E9UL)) +#define FM4_MFT1_ADCMP_ACSD5 *((volatile uint8_t*)(0x400211E9UL)) +#define FM_MFT1_ADCMP_ACMC5 *((volatile uint8_t*)(0x400211EAUL)) +#define FM4_MFT1_ADCMP_ACMC5 *((volatile uint8_t*)(0x400211EAUL)) +#define FM_MFT1_FRT_TCSD *((volatile uint8_t*)(0x400211ECUL)) +#define FM4_MFT1_FRT_TCSD *((volatile uint8_t*)(0x400211ECUL)) + +/******************************************************************************* +* MFT Registers MFT2 +* Register Definition +*******************************************************************************/ +#define FM_MFT2_OCU_OCCP0 *((volatile uint16_t*)(0x40022102UL)) +#define FM4_MFT2_OCU_OCCP0 *((volatile uint16_t*)(0x40022102UL)) +#define FM_MFT2_OCU_OCCP1 *((volatile uint16_t*)(0x40022106UL)) +#define FM4_MFT2_OCU_OCCP1 *((volatile uint16_t*)(0x40022106UL)) +#define FM_MFT2_OCU_OCCP2 *((volatile uint16_t*)(0x4002210AUL)) +#define FM4_MFT2_OCU_OCCP2 *((volatile uint16_t*)(0x4002210AUL)) +#define FM_MFT2_OCU_OCCP3 *((volatile uint16_t*)(0x4002210EUL)) +#define FM4_MFT2_OCU_OCCP3 *((volatile uint16_t*)(0x4002210EUL)) +#define FM_MFT2_OCU_OCCP4 *((volatile uint16_t*)(0x40022112UL)) +#define FM4_MFT2_OCU_OCCP4 *((volatile uint16_t*)(0x40022112UL)) +#define FM_MFT2_OCU_OCCP5 *((volatile uint16_t*)(0x40022116UL)) +#define FM4_MFT2_OCU_OCCP5 *((volatile uint16_t*)(0x40022116UL)) +#define FM_MFT2_OCU_OCSA10 *((volatile uint8_t*)(0x40022118UL)) +#define FM4_MFT2_OCU_OCSA10 *((volatile uint8_t*)(0x40022118UL)) +#define FM_MFT2_OCU_OCSB10 *((volatile uint8_t*)(0x40022119UL)) +#define FM4_MFT2_OCU_OCSB10 *((volatile uint8_t*)(0x40022119UL)) +#define FM_MFT2_OCU_OCSD10 *((volatile uint16_t*)(0x4002211AUL)) +#define FM4_MFT2_OCU_OCSD10 *((volatile uint16_t*)(0x4002211AUL)) +#define FM_MFT2_OCU_OCSA32 *((volatile uint8_t*)(0x4002211CUL)) +#define FM4_MFT2_OCU_OCSA32 *((volatile uint8_t*)(0x4002211CUL)) +#define FM_MFT2_OCU_OCSB32 *((volatile uint8_t*)(0x4002211DUL)) +#define FM4_MFT2_OCU_OCSB32 *((volatile uint8_t*)(0x4002211DUL)) +#define FM_MFT2_OCU_OCSD32 *((volatile uint16_t*)(0x4002211EUL)) +#define FM4_MFT2_OCU_OCSD32 *((volatile uint16_t*)(0x4002211EUL)) +#define FM_MFT2_OCU_OCSA54 *((volatile uint8_t*)(0x40022120UL)) +#define FM4_MFT2_OCU_OCSA54 *((volatile uint8_t*)(0x40022120UL)) +#define FM_MFT2_OCU_OCSB54 *((volatile uint8_t*)(0x40022121UL)) +#define FM4_MFT2_OCU_OCSB54 *((volatile uint8_t*)(0x40022121UL)) +#define FM_MFT2_OCU_OCSD54 *((volatile uint16_t*)(0x40022122UL)) +#define FM4_MFT2_OCU_OCSD54 *((volatile uint16_t*)(0x40022122UL)) +#define FM_MFT2_OCU_OCSC *((volatile uint8_t*)(0x40022125UL)) +#define FM4_MFT2_OCU_OCSC *((volatile uint8_t*)(0x40022125UL)) +#define FM_MFT2_OCU_OCSE0 *((volatile uint16_t*)(0x40022128UL)) +#define FM4_MFT2_OCU_OCSE0 *((volatile uint16_t*)(0x40022128UL)) +#define FM_MFT2_OCU_OCSE1 *((volatile uint32_t*)(0x4002212CUL)) +#define FM4_MFT2_OCU_OCSE1 *((volatile uint32_t*)(0x4002212CUL)) +#define FM_MFT2_OCU_OCSE2 *((volatile uint16_t*)(0x40022130UL)) +#define FM4_MFT2_OCU_OCSE2 *((volatile uint16_t*)(0x40022130UL)) +#define FM_MFT2_OCU_OCSE3 *((volatile uint32_t*)(0x40022134UL)) +#define FM4_MFT2_OCU_OCSE3 *((volatile uint32_t*)(0x40022134UL)) +#define FM_MFT2_OCU_OCSE4 *((volatile uint16_t*)(0x40022138UL)) +#define FM4_MFT2_OCU_OCSE4 *((volatile uint16_t*)(0x40022138UL)) +#define FM_MFT2_OCU_OCSE5 *((volatile uint32_t*)(0x4002213CUL)) +#define FM4_MFT2_OCU_OCSE5 *((volatile uint32_t*)(0x4002213CUL)) +#define FM_MFT2_FRT_TCCP0 *((volatile uint16_t*)(0x40022142UL)) +#define FM4_MFT2_FRT_TCCP0 *((volatile uint16_t*)(0x40022142UL)) +#define FM_MFT2_FRT_TCDT0 *((volatile uint16_t*)(0x40022146UL)) +#define FM4_MFT2_FRT_TCDT0 *((volatile uint16_t*)(0x40022146UL)) +#define FM_MFT2_FRT_TCSA0 *((volatile uint16_t*)(0x40022148UL)) +#define FM4_MFT2_FRT_TCSA0 *((volatile uint16_t*)(0x40022148UL)) +#define FM_MFT2_FRT_TCSC0 *((volatile uint16_t*)(0x4002214AUL)) +#define FM4_MFT2_FRT_TCSC0 *((volatile uint16_t*)(0x4002214AUL)) +#define FM_MFT2_FRT_TCCP1 *((volatile uint16_t*)(0x4002214EUL)) +#define FM4_MFT2_FRT_TCCP1 *((volatile uint16_t*)(0x4002214EUL)) +#define FM_MFT2_FRT_TCDT1 *((volatile uint16_t*)(0x40022152UL)) +#define FM4_MFT2_FRT_TCDT1 *((volatile uint16_t*)(0x40022152UL)) +#define FM_MFT2_FRT_TCSA1 *((volatile uint16_t*)(0x40022154UL)) +#define FM4_MFT2_FRT_TCSA1 *((volatile uint16_t*)(0x40022154UL)) +#define FM_MFT2_FRT_TCSC1 *((volatile uint16_t*)(0x40022156UL)) +#define FM4_MFT2_FRT_TCSC1 *((volatile uint16_t*)(0x40022156UL)) +#define FM_MFT2_FRT_TCCP2 *((volatile uint16_t*)(0x4002215AUL)) +#define FM4_MFT2_FRT_TCCP2 *((volatile uint16_t*)(0x4002215AUL)) +#define FM_MFT2_FRT_TCDT2 *((volatile uint16_t*)(0x4002215EUL)) +#define FM4_MFT2_FRT_TCDT2 *((volatile uint16_t*)(0x4002215EUL)) +#define FM_MFT2_FRT_TCSA2 *((volatile uint16_t*)(0x40022160UL)) +#define FM4_MFT2_FRT_TCSA2 *((volatile uint16_t*)(0x40022160UL)) +#define FM_MFT2_FRT_TCSC2 *((volatile uint16_t*)(0x40022162UL)) +#define FM4_MFT2_FRT_TCSC2 *((volatile uint16_t*)(0x40022162UL)) +#define FM_MFT2_FRT_TCAL *((volatile uint32_t*)(0x40022164UL)) +#define FM4_MFT2_FRT_TCAL *((volatile uint32_t*)(0x40022164UL)) +#define FM_MFT2_OCU_OCFS10 *((volatile uint8_t*)(0x40022168UL)) +#define FM4_MFT2_OCU_OCFS10 *((volatile uint8_t*)(0x40022168UL)) +#define FM_MFT2_OCU_OCFS32 *((volatile uint8_t*)(0x40022169UL)) +#define FM4_MFT2_OCU_OCFS32 *((volatile uint8_t*)(0x40022169UL)) +#define FM_MFT2_OCU_OCFS54 *((volatile uint8_t*)(0x4002216AUL)) +#define FM4_MFT2_OCU_OCFS54 *((volatile uint8_t*)(0x4002216AUL)) +#define FM_MFT2_ICU_ICFS10 *((volatile uint8_t*)(0x4002216CUL)) +#define FM4_MFT2_ICU_ICFS10 *((volatile uint8_t*)(0x4002216CUL)) +#define FM_MFT2_ICU_ICFS32 *((volatile uint8_t*)(0x4002216DUL)) +#define FM4_MFT2_ICU_ICFS32 *((volatile uint8_t*)(0x4002216DUL)) +#define FM_MFT2_ADCMP_ACFS10 *((volatile uint8_t*)(0x40022170UL)) +#define FM4_MFT2_ADCMP_ACFS10 *((volatile uint8_t*)(0x40022170UL)) +#define FM_MFT2_ADCMP_ACFS32 *((volatile uint8_t*)(0x40022171UL)) +#define FM4_MFT2_ADCMP_ACFS32 *((volatile uint8_t*)(0x40022171UL)) +#define FM_MFT2_ADCMP_ACFS54 *((volatile uint8_t*)(0x40022172UL)) +#define FM4_MFT2_ADCMP_ACFS54 *((volatile uint8_t*)(0x40022172UL)) +#define FM_MFT2_ICU_ICCP0 *((volatile uint16_t*)(0x40022176UL)) +#define FM4_MFT2_ICU_ICCP0 *((volatile uint16_t*)(0x40022176UL)) +#define FM_MFT2_ICU_ICCP1 *((volatile uint16_t*)(0x4002217AUL)) +#define FM4_MFT2_ICU_ICCP1 *((volatile uint16_t*)(0x4002217AUL)) +#define FM_MFT2_ICU_ICCP2 *((volatile uint16_t*)(0x4002217EUL)) +#define FM4_MFT2_ICU_ICCP2 *((volatile uint16_t*)(0x4002217EUL)) +#define FM_MFT2_ICU_ICCP3 *((volatile uint16_t*)(0x40022182UL)) +#define FM4_MFT2_ICU_ICCP3 *((volatile uint16_t*)(0x40022182UL)) +#define FM_MFT2_ICU_ICSA10 *((volatile uint8_t*)(0x40022184UL)) +#define FM4_MFT2_ICU_ICSA10 *((volatile uint8_t*)(0x40022184UL)) +#define FM_MFT2_ICU_ICSB10 *((volatile uint8_t*)(0x40022185UL)) +#define FM4_MFT2_ICU_ICSB10 *((volatile uint8_t*)(0x40022185UL)) +#define FM_MFT2_ICU_ICSA32 *((volatile uint8_t*)(0x40022188UL)) +#define FM4_MFT2_ICU_ICSA32 *((volatile uint8_t*)(0x40022188UL)) +#define FM_MFT2_ICU_ICSB32 *((volatile uint8_t*)(0x40022189UL)) +#define FM4_MFT2_ICU_ICSB32 *((volatile uint8_t*)(0x40022189UL)) +#define FM_MFT2_WFG_WFTF10 *((volatile uint16_t*)(0x4002218EUL)) +#define FM4_MFT2_WFG_WFTF10 *((volatile uint16_t*)(0x4002218EUL)) +#define FM_MFT2_WFG_WFTA10 *((volatile uint16_t*)(0x40022190UL)) +#define FM4_MFT2_WFG_WFTA10 *((volatile uint16_t*)(0x40022190UL)) +#define FM_MFT2_WFG_WFTB10 *((volatile uint16_t*)(0x40022192UL)) +#define FM4_MFT2_WFG_WFTB10 *((volatile uint16_t*)(0x40022192UL)) +#define FM_MFT2_WFG_WFTF32 *((volatile uint16_t*)(0x40022196UL)) +#define FM4_MFT2_WFG_WFTF32 *((volatile uint16_t*)(0x40022196UL)) +#define FM_MFT2_WFG_WFTA32 *((volatile uint16_t*)(0x40022198UL)) +#define FM4_MFT2_WFG_WFTA32 *((volatile uint16_t*)(0x40022198UL)) +#define FM_MFT2_WFG_WFTB32 *((volatile uint16_t*)(0x4002219AUL)) +#define FM4_MFT2_WFG_WFTB32 *((volatile uint16_t*)(0x4002219AUL)) +#define FM_MFT2_WFG_WFTF54 *((volatile uint16_t*)(0x4002219EUL)) +#define FM4_MFT2_WFG_WFTF54 *((volatile uint16_t*)(0x4002219EUL)) +#define FM_MFT2_WFG_WFTA54 *((volatile uint16_t*)(0x400221A0UL)) +#define FM4_MFT2_WFG_WFTA54 *((volatile uint16_t*)(0x400221A0UL)) +#define FM_MFT2_WFG_WFTB54 *((volatile uint16_t*)(0x400221A2UL)) +#define FM4_MFT2_WFG_WFTB54 *((volatile uint16_t*)(0x400221A2UL)) +#define FM_MFT2_WFG_WFSA10 *((volatile uint16_t*)(0x400221A4UL)) +#define FM4_MFT2_WFG_WFSA10 *((volatile uint16_t*)(0x400221A4UL)) +#define FM_MFT2_WFG_WFSA32 *((volatile uint16_t*)(0x400221A8UL)) +#define FM4_MFT2_WFG_WFSA32 *((volatile uint16_t*)(0x400221A8UL)) +#define FM_MFT2_WFG_WFSA54 *((volatile uint16_t*)(0x400221ACUL)) +#define FM4_MFT2_WFG_WFSA54 *((volatile uint16_t*)(0x400221ACUL)) +#define FM_MFT2_WFG_WFIR *((volatile uint16_t*)(0x400221B0UL)) +#define FM4_MFT2_WFG_WFIR *((volatile uint16_t*)(0x400221B0UL)) +#define FM_MFT2_WFG_NZCL *((volatile uint16_t*)(0x400221B4UL)) +#define FM4_MFT2_WFG_NZCL *((volatile uint16_t*)(0x400221B4UL)) +#define FM_MFT2_ADCMP_ACMP0 *((volatile uint16_t*)(0x400221BAUL)) +#define FM4_MFT2_ADCMP_ACMP0 *((volatile uint16_t*)(0x400221BAUL)) +#define FM_MFT2_ADCMP_ACMP1 *((volatile uint16_t*)(0x400221BEUL)) +#define FM4_MFT2_ADCMP_ACMP1 *((volatile uint16_t*)(0x400221BEUL)) +#define FM_MFT2_ADCMP_ACMP2 *((volatile uint16_t*)(0x400221C2UL)) +#define FM4_MFT2_ADCMP_ACMP2 *((volatile uint16_t*)(0x400221C2UL)) +#define FM_MFT2_ADCMP_ACMP3 *((volatile uint16_t*)(0x400221C6UL)) +#define FM4_MFT2_ADCMP_ACMP3 *((volatile uint16_t*)(0x400221C6UL)) +#define FM_MFT2_ADCMP_ACMP4 *((volatile uint16_t*)(0x400221CAUL)) +#define FM4_MFT2_ADCMP_ACMP4 *((volatile uint16_t*)(0x400221CAUL)) +#define FM_MFT2_ADCMP_ACMP5 *((volatile uint16_t*)(0x400221CEUL)) +#define FM4_MFT2_ADCMP_ACMP5 *((volatile uint16_t*)(0x400221CEUL)) +#define FM_MFT2_ADCMP_ACSA *((volatile uint16_t*)(0x400221D0UL)) +#define FM4_MFT2_ADCMP_ACSA *((volatile uint16_t*)(0x400221D0UL)) +#define FM_MFT2_ADCMP_ACSC0 *((volatile uint8_t*)(0x400221D4UL)) +#define FM4_MFT2_ADCMP_ACSC0 *((volatile uint8_t*)(0x400221D4UL)) +#define FM_MFT2_ADCMP_ACSD0 *((volatile uint8_t*)(0x400221D5UL)) +#define FM4_MFT2_ADCMP_ACSD0 *((volatile uint8_t*)(0x400221D5UL)) +#define FM_MFT2_ADCMP_ACMC0 *((volatile uint8_t*)(0x400221D6UL)) +#define FM4_MFT2_ADCMP_ACMC0 *((volatile uint8_t*)(0x400221D6UL)) +#define FM_MFT2_ADCMP_ACSC1 *((volatile uint8_t*)(0x400221D8UL)) +#define FM4_MFT2_ADCMP_ACSC1 *((volatile uint8_t*)(0x400221D8UL)) +#define FM_MFT2_ADCMP_ACSD1 *((volatile uint8_t*)(0x400221D9UL)) +#define FM4_MFT2_ADCMP_ACSD1 *((volatile uint8_t*)(0x400221D9UL)) +#define FM_MFT2_ADCMP_ACMC1 *((volatile uint8_t*)(0x400221DAUL)) +#define FM4_MFT2_ADCMP_ACMC1 *((volatile uint8_t*)(0x400221DAUL)) +#define FM_MFT2_ADCMP_ACSC2 *((volatile uint8_t*)(0x400221DCUL)) +#define FM4_MFT2_ADCMP_ACSC2 *((volatile uint8_t*)(0x400221DCUL)) +#define FM_MFT2_ADCMP_ACSD2 *((volatile uint8_t*)(0x400221DDUL)) +#define FM4_MFT2_ADCMP_ACSD2 *((volatile uint8_t*)(0x400221DDUL)) +#define FM_MFT2_ADCMP_ACMC2 *((volatile uint8_t*)(0x400221DEUL)) +#define FM4_MFT2_ADCMP_ACMC2 *((volatile uint8_t*)(0x400221DEUL)) +#define FM_MFT2_ADCMP_ACSC3 *((volatile uint8_t*)(0x400221E0UL)) +#define FM4_MFT2_ADCMP_ACSC3 *((volatile uint8_t*)(0x400221E0UL)) +#define FM_MFT2_ADCMP_ACSD3 *((volatile uint8_t*)(0x400221E1UL)) +#define FM4_MFT2_ADCMP_ACSD3 *((volatile uint8_t*)(0x400221E1UL)) +#define FM_MFT2_ADCMP_ACMC3 *((volatile uint8_t*)(0x400221E2UL)) +#define FM4_MFT2_ADCMP_ACMC3 *((volatile uint8_t*)(0x400221E2UL)) +#define FM_MFT2_ADCMP_ACSC4 *((volatile uint8_t*)(0x400221E4UL)) +#define FM4_MFT2_ADCMP_ACSC4 *((volatile uint8_t*)(0x400221E4UL)) +#define FM_MFT2_ADCMP_ACSD4 *((volatile uint8_t*)(0x400221E5UL)) +#define FM4_MFT2_ADCMP_ACSD4 *((volatile uint8_t*)(0x400221E5UL)) +#define FM_MFT2_ADCMP_ACMC4 *((volatile uint8_t*)(0x400221E6UL)) +#define FM4_MFT2_ADCMP_ACMC4 *((volatile uint8_t*)(0x400221E6UL)) +#define FM_MFT2_ADCMP_ACSC5 *((volatile uint8_t*)(0x400221E8UL)) +#define FM4_MFT2_ADCMP_ACSC5 *((volatile uint8_t*)(0x400221E8UL)) +#define FM_MFT2_ADCMP_ACSD5 *((volatile uint8_t*)(0x400221E9UL)) +#define FM4_MFT2_ADCMP_ACSD5 *((volatile uint8_t*)(0x400221E9UL)) +#define FM_MFT2_ADCMP_ACMC5 *((volatile uint8_t*)(0x400221EAUL)) +#define FM4_MFT2_ADCMP_ACMC5 *((volatile uint8_t*)(0x400221EAUL)) +#define FM_MFT2_FRT_TCSD *((volatile uint8_t*)(0x400221ECUL)) +#define FM4_MFT2_FRT_TCSD *((volatile uint8_t*)(0x400221ECUL)) + +/******************************************************************************* +* PCRC Registers PCRC +* Register Definition +*******************************************************************************/ +#define FM_PCRC_PCRC_POLY *((volatile uint32_t*)(0x40080000UL)) +#define FM4_PCRC_PCRC_POLY *((volatile uint32_t*)(0x40080000UL)) +#define FM_PCRC_PCRC_SEED *((volatile uint32_t*)(0x40080004UL)) +#define FM4_PCRC_PCRC_SEED *((volatile uint32_t*)(0x40080004UL)) +#define FM_PCRC_PCRC_FXOR *((volatile uint32_t*)(0x40080008UL)) +#define FM4_PCRC_PCRC_FXOR *((volatile uint32_t*)(0x40080008UL)) +#define FM_PCRC_PCRC_CFG *((volatile uint32_t*)(0x4008000CUL)) +#define FM4_PCRC_PCRC_CFG *((volatile uint32_t*)(0x4008000CUL)) +#define FM_PCRC_PCRC_WR *((volatile uint32_t*)(0x40080010UL)) +#define FM4_PCRC_PCRC_WR *((volatile uint32_t*)(0x40080010UL)) +#define FM_PCRC_PCRC_RD *((volatile uint32_t*)(0x40080014UL)) +#define FM4_PCRC_PCRC_RD *((volatile uint32_t*)(0x40080014UL)) + +/******************************************************************************* +* QPRC Registers QPRC0 +* Register Definition +*******************************************************************************/ +#define FM_QPRC0_QPCR *((volatile uint16_t*)(0x40026000UL)) +#define FM4_QPRC0_QPCR *((volatile uint16_t*)(0x40026000UL)) +#define FM_QPRC0_QRCR *((volatile uint16_t*)(0x40026004UL)) +#define FM4_QPRC0_QRCR *((volatile uint16_t*)(0x40026004UL)) +#define FM_QPRC0_QPCCR *((volatile uint16_t*)(0x40026008UL)) +#define FM4_QPRC0_QPCCR *((volatile uint16_t*)(0x40026008UL)) +#define FM_QPRC0_QPRCR *((volatile uint16_t*)(0x4002600CUL)) +#define FM4_QPRC0_QPRCR *((volatile uint16_t*)(0x4002600CUL)) +#define FM_QPRC0_QMPR *((volatile uint16_t*)(0x40026010UL)) +#define FM4_QPRC0_QMPR *((volatile uint16_t*)(0x40026010UL)) +#define FM_QPRC0_QICRL *((volatile uint8_t*)(0x40026014UL)) +#define FM4_QPRC0_QICRL *((volatile uint8_t*)(0x40026014UL)) +#define FM_QPRC0_QICRH *((volatile uint8_t*)(0x40026015UL)) +#define FM4_QPRC0_QICRH *((volatile uint8_t*)(0x40026015UL)) +#define FM_QPRC0_QCR *((volatile uint16_t*)(0x40026018UL)) +#define FM4_QPRC0_QCR *((volatile uint16_t*)(0x40026018UL)) +#define FM_QPRC0_QECR *((volatile uint16_t*)(0x4002601CUL)) +#define FM4_QPRC0_QECR *((volatile uint16_t*)(0x4002601CUL)) +#define FM_QPRC0_QPRCRR *((volatile uint32_t*)(0x4002603CUL)) +#define FM4_QPRC0_QPRCRR *((volatile uint32_t*)(0x4002603CUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC0_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC0_NF_NFCTLA *((volatile uint8_t*)(0x40026100UL)) +#define FM4_QPRC0_NF_NFCTLA *((volatile uint8_t*)(0x40026100UL)) +#define FM_QPRC0_NF_NFCTLB *((volatile uint8_t*)(0x40026104UL)) +#define FM4_QPRC0_NF_NFCTLB *((volatile uint8_t*)(0x40026104UL)) +#define FM_QPRC0_NF_NFCTLZ *((volatile uint8_t*)(0x40026108UL)) +#define FM4_QPRC0_NF_NFCTLZ *((volatile uint8_t*)(0x40026108UL)) + +/******************************************************************************* +* QPRC Registers QPRC1 +* Register Definition +*******************************************************************************/ +#define FM_QPRC1_QPCR *((volatile uint16_t*)(0x40026040UL)) +#define FM4_QPRC1_QPCR *((volatile uint16_t*)(0x40026040UL)) +#define FM_QPRC1_QRCR *((volatile uint16_t*)(0x40026044UL)) +#define FM4_QPRC1_QRCR *((volatile uint16_t*)(0x40026044UL)) +#define FM_QPRC1_QPCCR *((volatile uint16_t*)(0x40026048UL)) +#define FM4_QPRC1_QPCCR *((volatile uint16_t*)(0x40026048UL)) +#define FM_QPRC1_QPRCR *((volatile uint16_t*)(0x4002604CUL)) +#define FM4_QPRC1_QPRCR *((volatile uint16_t*)(0x4002604CUL)) +#define FM_QPRC1_QMPR *((volatile uint16_t*)(0x40026050UL)) +#define FM4_QPRC1_QMPR *((volatile uint16_t*)(0x40026050UL)) +#define FM_QPRC1_QICRL *((volatile uint8_t*)(0x40026054UL)) +#define FM4_QPRC1_QICRL *((volatile uint8_t*)(0x40026054UL)) +#define FM_QPRC1_QICRH *((volatile uint8_t*)(0x40026055UL)) +#define FM4_QPRC1_QICRH *((volatile uint8_t*)(0x40026055UL)) +#define FM_QPRC1_QCR *((volatile uint16_t*)(0x40026058UL)) +#define FM4_QPRC1_QCR *((volatile uint16_t*)(0x40026058UL)) +#define FM_QPRC1_QECR *((volatile uint16_t*)(0x4002605CUL)) +#define FM4_QPRC1_QECR *((volatile uint16_t*)(0x4002605CUL)) +#define FM_QPRC1_QPRCRR *((volatile uint32_t*)(0x4002607CUL)) +#define FM4_QPRC1_QPRCRR *((volatile uint32_t*)(0x4002607CUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC1_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC1_NF_NFCTLA *((volatile uint8_t*)(0x40026110UL)) +#define FM4_QPRC1_NF_NFCTLA *((volatile uint8_t*)(0x40026110UL)) +#define FM_QPRC1_NF_NFCTLB *((volatile uint8_t*)(0x40026114UL)) +#define FM4_QPRC1_NF_NFCTLB *((volatile uint8_t*)(0x40026114UL)) +#define FM_QPRC1_NF_NFCTLZ *((volatile uint8_t*)(0x40026118UL)) +#define FM4_QPRC1_NF_NFCTLZ *((volatile uint8_t*)(0x40026118UL)) + +/******************************************************************************* +* QPRC Registers QPRC2 +* Register Definition +*******************************************************************************/ +#define FM_QPRC2_QPCR *((volatile uint16_t*)(0x40026080UL)) +#define FM4_QPRC2_QPCR *((volatile uint16_t*)(0x40026080UL)) +#define FM_QPRC2_QRCR *((volatile uint16_t*)(0x40026084UL)) +#define FM4_QPRC2_QRCR *((volatile uint16_t*)(0x40026084UL)) +#define FM_QPRC2_QPCCR *((volatile uint16_t*)(0x40026088UL)) +#define FM4_QPRC2_QPCCR *((volatile uint16_t*)(0x40026088UL)) +#define FM_QPRC2_QPRCR *((volatile uint16_t*)(0x4002608CUL)) +#define FM4_QPRC2_QPRCR *((volatile uint16_t*)(0x4002608CUL)) +#define FM_QPRC2_QMPR *((volatile uint16_t*)(0x40026090UL)) +#define FM4_QPRC2_QMPR *((volatile uint16_t*)(0x40026090UL)) +#define FM_QPRC2_QICRL *((volatile uint8_t*)(0x40026094UL)) +#define FM4_QPRC2_QICRL *((volatile uint8_t*)(0x40026094UL)) +#define FM_QPRC2_QICRH *((volatile uint8_t*)(0x40026095UL)) +#define FM4_QPRC2_QICRH *((volatile uint8_t*)(0x40026095UL)) +#define FM_QPRC2_QCR *((volatile uint16_t*)(0x40026098UL)) +#define FM4_QPRC2_QCR *((volatile uint16_t*)(0x40026098UL)) +#define FM_QPRC2_QECR *((volatile uint16_t*)(0x4002609CUL)) +#define FM4_QPRC2_QECR *((volatile uint16_t*)(0x4002609CUL)) +#define FM_QPRC2_QPRCRR *((volatile uint32_t*)(0x400260BCUL)) +#define FM4_QPRC2_QPRCRR *((volatile uint32_t*)(0x400260BCUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC2_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC2_NF_NFCTLA *((volatile uint8_t*)(0x40026120UL)) +#define FM4_QPRC2_NF_NFCTLA *((volatile uint8_t*)(0x40026120UL)) +#define FM_QPRC2_NF_NFCTLB *((volatile uint8_t*)(0x40026124UL)) +#define FM4_QPRC2_NF_NFCTLB *((volatile uint8_t*)(0x40026124UL)) +#define FM_QPRC2_NF_NFCTLZ *((volatile uint8_t*)(0x40026128UL)) +#define FM4_QPRC2_NF_NFCTLZ *((volatile uint8_t*)(0x40026128UL)) + +/******************************************************************************* +* QPRC Registers QPRC3 +* Register Definition +*******************************************************************************/ +#define FM_QPRC3_QPCR *((volatile uint16_t*)(0x400260C0UL)) +#define FM4_QPRC3_QPCR *((volatile uint16_t*)(0x400260C0UL)) +#define FM_QPRC3_QRCR *((volatile uint16_t*)(0x400260C4UL)) +#define FM4_QPRC3_QRCR *((volatile uint16_t*)(0x400260C4UL)) +#define FM_QPRC3_QPCCR *((volatile uint16_t*)(0x400260C8UL)) +#define FM4_QPRC3_QPCCR *((volatile uint16_t*)(0x400260C8UL)) +#define FM_QPRC3_QPRCR *((volatile uint16_t*)(0x400260CCUL)) +#define FM4_QPRC3_QPRCR *((volatile uint16_t*)(0x400260CCUL)) +#define FM_QPRC3_QMPR *((volatile uint16_t*)(0x400260D0UL)) +#define FM4_QPRC3_QMPR *((volatile uint16_t*)(0x400260D0UL)) +#define FM_QPRC3_QICRL *((volatile uint8_t*)(0x400260D4UL)) +#define FM4_QPRC3_QICRL *((volatile uint8_t*)(0x400260D4UL)) +#define FM_QPRC3_QICRH *((volatile uint8_t*)(0x400260D5UL)) +#define FM4_QPRC3_QICRH *((volatile uint8_t*)(0x400260D5UL)) +#define FM_QPRC3_QCR *((volatile uint16_t*)(0x400260D8UL)) +#define FM4_QPRC3_QCR *((volatile uint16_t*)(0x400260D8UL)) +#define FM_QPRC3_QECR *((volatile uint16_t*)(0x400260DCUL)) +#define FM4_QPRC3_QECR *((volatile uint16_t*)(0x400260DCUL)) +#define FM_QPRC3_QPRCRR *((volatile uint32_t*)(0x400260FCUL)) +#define FM4_QPRC3_QPRCRR *((volatile uint32_t*)(0x400260FCUL)) + +/******************************************************************************* +* QPRC_NF Registers QPRC3_NF +* Register Definition +*******************************************************************************/ +#define FM_QPRC3_NF_NFCTLA *((volatile uint8_t*)(0x40026130UL)) +#define FM4_QPRC3_NF_NFCTLA *((volatile uint8_t*)(0x40026130UL)) +#define FM_QPRC3_NF_NFCTLB *((volatile uint8_t*)(0x40026134UL)) +#define FM4_QPRC3_NF_NFCTLB *((volatile uint8_t*)(0x40026134UL)) +#define FM_QPRC3_NF_NFCTLZ *((volatile uint8_t*)(0x40026138UL)) +#define FM4_QPRC3_NF_NFCTLZ *((volatile uint8_t*)(0x40026138UL)) + +/******************************************************************************* +* RTC Registers RTC +* Register Definition +*******************************************************************************/ +#define FM_RTC_WTCR10 *((volatile uint8_t*)(0x4003B100UL)) +#define FM4_RTC_WTCR10 *((volatile uint8_t*)(0x4003B100UL)) +#define FM_RTC_WTCR11 *((volatile uint8_t*)(0x4003B104UL)) +#define FM4_RTC_WTCR11 *((volatile uint8_t*)(0x4003B104UL)) +#define FM_RTC_WTCR12 *((volatile uint8_t*)(0x4003B108UL)) +#define FM4_RTC_WTCR12 *((volatile uint8_t*)(0x4003B108UL)) +#define FM_RTC_WTCR13 *((volatile uint8_t*)(0x4003B10CUL)) +#define FM4_RTC_WTCR13 *((volatile uint8_t*)(0x4003B10CUL)) +#define FM_RTC_WTCR20 *((volatile uint8_t*)(0x4003B110UL)) +#define FM4_RTC_WTCR20 *((volatile uint8_t*)(0x4003B110UL)) +#define FM_RTC_WTCR21 *((volatile uint8_t*)(0x4003B114UL)) +#define FM4_RTC_WTCR21 *((volatile uint8_t*)(0x4003B114UL)) +#define FM_RTC_WTSR *((volatile uint8_t*)(0x4003B11CUL)) +#define FM4_RTC_WTSR *((volatile uint8_t*)(0x4003B11CUL)) +#define FM_RTC_WTMIR *((volatile uint8_t*)(0x4003B120UL)) +#define FM4_RTC_WTMIR *((volatile uint8_t*)(0x4003B120UL)) +#define FM_RTC_WTHR *((volatile uint8_t*)(0x4003B124UL)) +#define FM4_RTC_WTHR *((volatile uint8_t*)(0x4003B124UL)) +#define FM_RTC_WTDR *((volatile uint8_t*)(0x4003B128UL)) +#define FM4_RTC_WTDR *((volatile uint8_t*)(0x4003B128UL)) +#define FM_RTC_WTDW *((volatile uint8_t*)(0x4003B12CUL)) +#define FM4_RTC_WTDW *((volatile uint8_t*)(0x4003B12CUL)) +#define FM_RTC_WTMOR *((volatile uint8_t*)(0x4003B130UL)) +#define FM4_RTC_WTMOR *((volatile uint8_t*)(0x4003B130UL)) +#define FM_RTC_WTYR *((volatile uint8_t*)(0x4003B134UL)) +#define FM4_RTC_WTYR *((volatile uint8_t*)(0x4003B134UL)) +#define FM_RTC_ALMIR *((volatile uint8_t*)(0x4003B138UL)) +#define FM4_RTC_ALMIR *((volatile uint8_t*)(0x4003B138UL)) +#define FM_RTC_ALHR *((volatile uint8_t*)(0x4003B13CUL)) +#define FM4_RTC_ALHR *((volatile uint8_t*)(0x4003B13CUL)) +#define FM_RTC_ALDR *((volatile uint8_t*)(0x4003B140UL)) +#define FM4_RTC_ALDR *((volatile uint8_t*)(0x4003B140UL)) +#define FM_RTC_ALMOR *((volatile uint8_t*)(0x4003B144UL)) +#define FM4_RTC_ALMOR *((volatile uint8_t*)(0x4003B144UL)) +#define FM_RTC_ALYR *((volatile uint8_t*)(0x4003B148UL)) +#define FM4_RTC_ALYR *((volatile uint8_t*)(0x4003B148UL)) +#define FM_RTC_WTTR0 *((volatile uint8_t*)(0x4003B14CUL)) +#define FM4_RTC_WTTR0 *((volatile uint8_t*)(0x4003B14CUL)) +#define FM_RTC_WTTR1 *((volatile uint8_t*)(0x4003B150UL)) +#define FM4_RTC_WTTR1 *((volatile uint8_t*)(0x4003B150UL)) +#define FM_RTC_WTTR2 *((volatile uint8_t*)(0x4003B154UL)) +#define FM4_RTC_WTTR2 *((volatile uint8_t*)(0x4003B154UL)) +#define FM_RTC_WTCAL0 *((volatile uint8_t*)(0x4003B158UL)) +#define FM4_RTC_WTCAL0 *((volatile uint8_t*)(0x4003B158UL)) +#define FM_RTC_WTCAL1 *((volatile uint8_t*)(0x4003B15CUL)) +#define FM4_RTC_WTCAL1 *((volatile uint8_t*)(0x4003B15CUL)) +#define FM_RTC_WTCALEN *((volatile uint8_t*)(0x4003B160UL)) +#define FM4_RTC_WTCALEN *((volatile uint8_t*)(0x4003B160UL)) +#define FM_RTC_WTDIV *((volatile uint8_t*)(0x4003B164UL)) +#define FM4_RTC_WTDIV *((volatile uint8_t*)(0x4003B164UL)) +#define FM_RTC_WTDIVEN *((volatile uint8_t*)(0x4003B168UL)) +#define FM4_RTC_WTDIVEN *((volatile uint8_t*)(0x4003B168UL)) +#define FM_RTC_WTCALPRD *((volatile uint8_t*)(0x4003B16CUL)) +#define FM4_RTC_WTCALPRD *((volatile uint8_t*)(0x4003B16CUL)) +#define FM_RTC_WTCOSEL *((volatile uint8_t*)(0x4003B170UL)) +#define FM4_RTC_WTCOSEL *((volatile uint8_t*)(0x4003B170UL)) +#define FM_RTC_VB_CLKDIV *((volatile uint8_t*)(0x4003B174UL)) +#define FM4_RTC_VB_CLKDIV *((volatile uint8_t*)(0x4003B174UL)) +#define FM_RTC_WTOSCCNT *((volatile uint8_t*)(0x4003B178UL)) +#define FM4_RTC_WTOSCCNT *((volatile uint8_t*)(0x4003B178UL)) +#define FM_RTC_CCS *((volatile uint8_t*)(0x4003B17CUL)) +#define FM4_RTC_CCS *((volatile uint8_t*)(0x4003B17CUL)) +#define FM_RTC_CCB *((volatile uint8_t*)(0x4003B180UL)) +#define FM4_RTC_CCB *((volatile uint8_t*)(0x4003B180UL)) +#define FM_RTC_BOOST *((volatile uint8_t*)(0x4003B188UL)) +#define FM4_RTC_BOOST *((volatile uint8_t*)(0x4003B188UL)) +#define FM_RTC_EWKUP *((volatile uint8_t*)(0x4003B18CUL)) +#define FM4_RTC_EWKUP *((volatile uint8_t*)(0x4003B18CUL)) +#define FM_RTC_VDET *((volatile uint8_t*)(0x4003B190UL)) +#define FM4_RTC_VDET *((volatile uint8_t*)(0x4003B190UL)) +#define FM_RTC_HIBRST *((volatile uint8_t*)(0x4003B198UL)) +#define FM4_RTC_HIBRST *((volatile uint8_t*)(0x4003B198UL)) +#define FM_RTC_VBPFR *((volatile uint8_t*)(0x4003B19CUL)) +#define FM4_RTC_VBPFR *((volatile uint8_t*)(0x4003B19CUL)) +#define FM_RTC_VBPCR *((volatile uint8_t*)(0x4003B1A0UL)) +#define FM4_RTC_VBPCR *((volatile uint8_t*)(0x4003B1A0UL)) +#define FM_RTC_VBDDR *((volatile uint8_t*)(0x4003B1A4UL)) +#define FM4_RTC_VBDDR *((volatile uint8_t*)(0x4003B1A4UL)) +#define FM_RTC_VBDIR *((volatile uint8_t*)(0x4003B1A8UL)) +#define FM4_RTC_VBDIR *((volatile uint8_t*)(0x4003B1A8UL)) +#define FM_RTC_VBDOR *((volatile uint8_t*)(0x4003B1ACUL)) +#define FM4_RTC_VBDOR *((volatile uint8_t*)(0x4003B1ACUL)) +#define FM_RTC_VBPZR *((volatile uint8_t*)(0x4003B1B0UL)) +#define FM4_RTC_VBPZR *((volatile uint8_t*)(0x4003B1B0UL)) +#define FM_RTC_BREG00 *((volatile uint8_t*)(0x4003B200UL)) +#define FM4_RTC_BREG00 *((volatile uint8_t*)(0x4003B200UL)) +#define FM_RTC_BREG01 *((volatile uint8_t*)(0x4003B201UL)) +#define FM4_RTC_BREG01 *((volatile uint8_t*)(0x4003B201UL)) +#define FM_RTC_BREG02 *((volatile uint8_t*)(0x4003B202UL)) +#define FM4_RTC_BREG02 *((volatile uint8_t*)(0x4003B202UL)) +#define FM_RTC_BREG03 *((volatile uint8_t*)(0x4003B203UL)) +#define FM4_RTC_BREG03 *((volatile uint8_t*)(0x4003B203UL)) +#define FM_RTC_BREG04 *((volatile uint8_t*)(0x4003B204UL)) +#define FM4_RTC_BREG04 *((volatile uint8_t*)(0x4003B204UL)) +#define FM_RTC_BREG05 *((volatile uint8_t*)(0x4003B205UL)) +#define FM4_RTC_BREG05 *((volatile uint8_t*)(0x4003B205UL)) +#define FM_RTC_BREG06 *((volatile uint8_t*)(0x4003B206UL)) +#define FM4_RTC_BREG06 *((volatile uint8_t*)(0x4003B206UL)) +#define FM_RTC_BREG07 *((volatile uint8_t*)(0x4003B207UL)) +#define FM4_RTC_BREG07 *((volatile uint8_t*)(0x4003B207UL)) +#define FM_RTC_BREG08 *((volatile uint8_t*)(0x4003B208UL)) +#define FM4_RTC_BREG08 *((volatile uint8_t*)(0x4003B208UL)) +#define FM_RTC_BREG09 *((volatile uint8_t*)(0x4003B209UL)) +#define FM4_RTC_BREG09 *((volatile uint8_t*)(0x4003B209UL)) +#define FM_RTC_BREG0A *((volatile uint8_t*)(0x4003B20AUL)) +#define FM4_RTC_BREG0A *((volatile uint8_t*)(0x4003B20AUL)) +#define FM_RTC_BREG0B *((volatile uint8_t*)(0x4003B20BUL)) +#define FM4_RTC_BREG0B *((volatile uint8_t*)(0x4003B20BUL)) +#define FM_RTC_BREG0C *((volatile uint8_t*)(0x4003B20CUL)) +#define FM4_RTC_BREG0C *((volatile uint8_t*)(0x4003B20CUL)) +#define FM_RTC_BREG0D *((volatile uint8_t*)(0x4003B20DUL)) +#define FM4_RTC_BREG0D *((volatile uint8_t*)(0x4003B20DUL)) +#define FM_RTC_BREG0E *((volatile uint8_t*)(0x4003B20EUL)) +#define FM4_RTC_BREG0E *((volatile uint8_t*)(0x4003B20EUL)) +#define FM_RTC_BREG0F *((volatile uint8_t*)(0x4003B20FUL)) +#define FM4_RTC_BREG0F *((volatile uint8_t*)(0x4003B20FUL)) +#define FM_RTC_BREG10 *((volatile uint8_t*)(0x4003B210UL)) +#define FM4_RTC_BREG10 *((volatile uint8_t*)(0x4003B210UL)) +#define FM_RTC_BREG11 *((volatile uint8_t*)(0x4003B211UL)) +#define FM4_RTC_BREG11 *((volatile uint8_t*)(0x4003B211UL)) +#define FM_RTC_BREG12 *((volatile uint8_t*)(0x4003B212UL)) +#define FM4_RTC_BREG12 *((volatile uint8_t*)(0x4003B212UL)) +#define FM_RTC_BREG13 *((volatile uint8_t*)(0x4003B213UL)) +#define FM4_RTC_BREG13 *((volatile uint8_t*)(0x4003B213UL)) +#define FM_RTC_BREG14 *((volatile uint8_t*)(0x4003B214UL)) +#define FM4_RTC_BREG14 *((volatile uint8_t*)(0x4003B214UL)) +#define FM_RTC_BREG15 *((volatile uint8_t*)(0x4003B215UL)) +#define FM4_RTC_BREG15 *((volatile uint8_t*)(0x4003B215UL)) +#define FM_RTC_BREG16 *((volatile uint8_t*)(0x4003B216UL)) +#define FM4_RTC_BREG16 *((volatile uint8_t*)(0x4003B216UL)) +#define FM_RTC_BREG17 *((volatile uint8_t*)(0x4003B217UL)) +#define FM4_RTC_BREG17 *((volatile uint8_t*)(0x4003B217UL)) +#define FM_RTC_BREG18 *((volatile uint8_t*)(0x4003B218UL)) +#define FM4_RTC_BREG18 *((volatile uint8_t*)(0x4003B218UL)) +#define FM_RTC_BREG19 *((volatile uint8_t*)(0x4003B219UL)) +#define FM4_RTC_BREG19 *((volatile uint8_t*)(0x4003B219UL)) +#define FM_RTC_BREG1A *((volatile uint8_t*)(0x4003B21AUL)) +#define FM4_RTC_BREG1A *((volatile uint8_t*)(0x4003B21AUL)) +#define FM_RTC_BREG1B *((volatile uint8_t*)(0x4003B21BUL)) +#define FM4_RTC_BREG1B *((volatile uint8_t*)(0x4003B21BUL)) +#define FM_RTC_BREG1C *((volatile uint8_t*)(0x4003B21CUL)) +#define FM4_RTC_BREG1C *((volatile uint8_t*)(0x4003B21CUL)) +#define FM_RTC_BREG1D *((volatile uint8_t*)(0x4003B21DUL)) +#define FM4_RTC_BREG1D *((volatile uint8_t*)(0x4003B21DUL)) +#define FM_RTC_BREG1E *((volatile uint8_t*)(0x4003B21EUL)) +#define FM4_RTC_BREG1E *((volatile uint8_t*)(0x4003B21EUL)) +#define FM_RTC_BREG1F *((volatile uint8_t*)(0x4003B21FUL)) +#define FM4_RTC_BREG1F *((volatile uint8_t*)(0x4003B21FUL)) +#define FM_RTC_BREG20 *((volatile uint8_t*)(0x4003B220UL)) +#define FM4_RTC_BREG20 *((volatile uint8_t*)(0x4003B220UL)) +#define FM_RTC_BREG21 *((volatile uint8_t*)(0x4003B221UL)) +#define FM4_RTC_BREG21 *((volatile uint8_t*)(0x4003B221UL)) +#define FM_RTC_BREG22 *((volatile uint8_t*)(0x4003B222UL)) +#define FM4_RTC_BREG22 *((volatile uint8_t*)(0x4003B222UL)) +#define FM_RTC_BREG23 *((volatile uint8_t*)(0x4003B223UL)) +#define FM4_RTC_BREG23 *((volatile uint8_t*)(0x4003B223UL)) +#define FM_RTC_BREG24 *((volatile uint8_t*)(0x4003B224UL)) +#define FM4_RTC_BREG24 *((volatile uint8_t*)(0x4003B224UL)) +#define FM_RTC_BREG25 *((volatile uint8_t*)(0x4003B225UL)) +#define FM4_RTC_BREG25 *((volatile uint8_t*)(0x4003B225UL)) +#define FM_RTC_BREG26 *((volatile uint8_t*)(0x4003B226UL)) +#define FM4_RTC_BREG26 *((volatile uint8_t*)(0x4003B226UL)) +#define FM_RTC_BREG27 *((volatile uint8_t*)(0x4003B227UL)) +#define FM4_RTC_BREG27 *((volatile uint8_t*)(0x4003B227UL)) +#define FM_RTC_BREG28 *((volatile uint8_t*)(0x4003B228UL)) +#define FM4_RTC_BREG28 *((volatile uint8_t*)(0x4003B228UL)) +#define FM_RTC_BREG29 *((volatile uint8_t*)(0x4003B229UL)) +#define FM4_RTC_BREG29 *((volatile uint8_t*)(0x4003B229UL)) +#define FM_RTC_BREG2A *((volatile uint8_t*)(0x4003B22AUL)) +#define FM4_RTC_BREG2A *((volatile uint8_t*)(0x4003B22AUL)) +#define FM_RTC_BREG2B *((volatile uint8_t*)(0x4003B22BUL)) +#define FM4_RTC_BREG2B *((volatile uint8_t*)(0x4003B22BUL)) +#define FM_RTC_BREG2C *((volatile uint8_t*)(0x4003B22CUL)) +#define FM4_RTC_BREG2C *((volatile uint8_t*)(0x4003B22CUL)) +#define FM_RTC_BREG2D *((volatile uint8_t*)(0x4003B22DUL)) +#define FM4_RTC_BREG2D *((volatile uint8_t*)(0x4003B22DUL)) +#define FM_RTC_BREG2E *((volatile uint8_t*)(0x4003B22EUL)) +#define FM4_RTC_BREG2E *((volatile uint8_t*)(0x4003B22EUL)) +#define FM_RTC_BREG2F *((volatile uint8_t*)(0x4003B22FUL)) +#define FM4_RTC_BREG2F *((volatile uint8_t*)(0x4003B22FUL)) +#define FM_RTC_BREG30 *((volatile uint8_t*)(0x4003B230UL)) +#define FM4_RTC_BREG30 *((volatile uint8_t*)(0x4003B230UL)) +#define FM_RTC_BREG31 *((volatile uint8_t*)(0x4003B231UL)) +#define FM4_RTC_BREG31 *((volatile uint8_t*)(0x4003B231UL)) +#define FM_RTC_BREG32 *((volatile uint8_t*)(0x4003B232UL)) +#define FM4_RTC_BREG32 *((volatile uint8_t*)(0x4003B232UL)) +#define FM_RTC_BREG33 *((volatile uint8_t*)(0x4003B233UL)) +#define FM4_RTC_BREG33 *((volatile uint8_t*)(0x4003B233UL)) +#define FM_RTC_BREG34 *((volatile uint8_t*)(0x4003B234UL)) +#define FM4_RTC_BREG34 *((volatile uint8_t*)(0x4003B234UL)) +#define FM_RTC_BREG35 *((volatile uint8_t*)(0x4003B235UL)) +#define FM4_RTC_BREG35 *((volatile uint8_t*)(0x4003B235UL)) +#define FM_RTC_BREG36 *((volatile uint8_t*)(0x4003B236UL)) +#define FM4_RTC_BREG36 *((volatile uint8_t*)(0x4003B236UL)) +#define FM_RTC_BREG37 *((volatile uint8_t*)(0x4003B237UL)) +#define FM4_RTC_BREG37 *((volatile uint8_t*)(0x4003B237UL)) +#define FM_RTC_BREG38 *((volatile uint8_t*)(0x4003B238UL)) +#define FM4_RTC_BREG38 *((volatile uint8_t*)(0x4003B238UL)) +#define FM_RTC_BREG39 *((volatile uint8_t*)(0x4003B239UL)) +#define FM4_RTC_BREG39 *((volatile uint8_t*)(0x4003B239UL)) +#define FM_RTC_BREG3A *((volatile uint8_t*)(0x4003B23AUL)) +#define FM4_RTC_BREG3A *((volatile uint8_t*)(0x4003B23AUL)) +#define FM_RTC_BREG3B *((volatile uint8_t*)(0x4003B23BUL)) +#define FM4_RTC_BREG3B *((volatile uint8_t*)(0x4003B23BUL)) +#define FM_RTC_BREG3C *((volatile uint8_t*)(0x4003B23CUL)) +#define FM4_RTC_BREG3C *((volatile uint8_t*)(0x4003B23CUL)) +#define FM_RTC_BREG3D *((volatile uint8_t*)(0x4003B23DUL)) +#define FM4_RTC_BREG3D *((volatile uint8_t*)(0x4003B23DUL)) +#define FM_RTC_BREG3E *((volatile uint8_t*)(0x4003B23EUL)) +#define FM4_RTC_BREG3E *((volatile uint8_t*)(0x4003B23EUL)) +#define FM_RTC_BREG3F *((volatile uint8_t*)(0x4003B23FUL)) +#define FM4_RTC_BREG3F *((volatile uint8_t*)(0x4003B23FUL)) +#define FM_RTC_BREG40 *((volatile uint8_t*)(0x4003B240UL)) +#define FM4_RTC_BREG40 *((volatile uint8_t*)(0x4003B240UL)) +#define FM_RTC_BREG41 *((volatile uint8_t*)(0x4003B241UL)) +#define FM4_RTC_BREG41 *((volatile uint8_t*)(0x4003B241UL)) +#define FM_RTC_BREG42 *((volatile uint8_t*)(0x4003B242UL)) +#define FM4_RTC_BREG42 *((volatile uint8_t*)(0x4003B242UL)) +#define FM_RTC_BREG43 *((volatile uint8_t*)(0x4003B243UL)) +#define FM4_RTC_BREG43 *((volatile uint8_t*)(0x4003B243UL)) +#define FM_RTC_BREG44 *((volatile uint8_t*)(0x4003B244UL)) +#define FM4_RTC_BREG44 *((volatile uint8_t*)(0x4003B244UL)) +#define FM_RTC_BREG45 *((volatile uint8_t*)(0x4003B245UL)) +#define FM4_RTC_BREG45 *((volatile uint8_t*)(0x4003B245UL)) +#define FM_RTC_BREG46 *((volatile uint8_t*)(0x4003B246UL)) +#define FM4_RTC_BREG46 *((volatile uint8_t*)(0x4003B246UL)) +#define FM_RTC_BREG47 *((volatile uint8_t*)(0x4003B247UL)) +#define FM4_RTC_BREG47 *((volatile uint8_t*)(0x4003B247UL)) +#define FM_RTC_BREG48 *((volatile uint8_t*)(0x4003B248UL)) +#define FM4_RTC_BREG48 *((volatile uint8_t*)(0x4003B248UL)) +#define FM_RTC_BREG49 *((volatile uint8_t*)(0x4003B249UL)) +#define FM4_RTC_BREG49 *((volatile uint8_t*)(0x4003B249UL)) +#define FM_RTC_BREG4A *((volatile uint8_t*)(0x4003B24AUL)) +#define FM4_RTC_BREG4A *((volatile uint8_t*)(0x4003B24AUL)) +#define FM_RTC_BREG4B *((volatile uint8_t*)(0x4003B24BUL)) +#define FM4_RTC_BREG4B *((volatile uint8_t*)(0x4003B24BUL)) +#define FM_RTC_BREG4C *((volatile uint8_t*)(0x4003B24CUL)) +#define FM4_RTC_BREG4C *((volatile uint8_t*)(0x4003B24CUL)) +#define FM_RTC_BREG4D *((volatile uint8_t*)(0x4003B24DUL)) +#define FM4_RTC_BREG4D *((volatile uint8_t*)(0x4003B24DUL)) +#define FM_RTC_BREG4E *((volatile uint8_t*)(0x4003B24EUL)) +#define FM4_RTC_BREG4E *((volatile uint8_t*)(0x4003B24EUL)) +#define FM_RTC_BREG4F *((volatile uint8_t*)(0x4003B24FUL)) +#define FM4_RTC_BREG4F *((volatile uint8_t*)(0x4003B24FUL)) +#define FM_RTC_BREG50 *((volatile uint8_t*)(0x4003B250UL)) +#define FM4_RTC_BREG50 *((volatile uint8_t*)(0x4003B250UL)) +#define FM_RTC_BREG51 *((volatile uint8_t*)(0x4003B251UL)) +#define FM4_RTC_BREG51 *((volatile uint8_t*)(0x4003B251UL)) +#define FM_RTC_BREG52 *((volatile uint8_t*)(0x4003B252UL)) +#define FM4_RTC_BREG52 *((volatile uint8_t*)(0x4003B252UL)) +#define FM_RTC_BREG53 *((volatile uint8_t*)(0x4003B253UL)) +#define FM4_RTC_BREG53 *((volatile uint8_t*)(0x4003B253UL)) +#define FM_RTC_BREG54 *((volatile uint8_t*)(0x4003B254UL)) +#define FM4_RTC_BREG54 *((volatile uint8_t*)(0x4003B254UL)) +#define FM_RTC_BREG55 *((volatile uint8_t*)(0x4003B255UL)) +#define FM4_RTC_BREG55 *((volatile uint8_t*)(0x4003B255UL)) +#define FM_RTC_BREG56 *((volatile uint8_t*)(0x4003B256UL)) +#define FM4_RTC_BREG56 *((volatile uint8_t*)(0x4003B256UL)) +#define FM_RTC_BREG57 *((volatile uint8_t*)(0x4003B257UL)) +#define FM4_RTC_BREG57 *((volatile uint8_t*)(0x4003B257UL)) +#define FM_RTC_BREG58 *((volatile uint8_t*)(0x4003B258UL)) +#define FM4_RTC_BREG58 *((volatile uint8_t*)(0x4003B258UL)) +#define FM_RTC_BREG59 *((volatile uint8_t*)(0x4003B259UL)) +#define FM4_RTC_BREG59 *((volatile uint8_t*)(0x4003B259UL)) +#define FM_RTC_BREG5A *((volatile uint8_t*)(0x4003B25AUL)) +#define FM4_RTC_BREG5A *((volatile uint8_t*)(0x4003B25AUL)) +#define FM_RTC_BREG5B *((volatile uint8_t*)(0x4003B25BUL)) +#define FM4_RTC_BREG5B *((volatile uint8_t*)(0x4003B25BUL)) +#define FM_RTC_BREG5C *((volatile uint8_t*)(0x4003B25CUL)) +#define FM4_RTC_BREG5C *((volatile uint8_t*)(0x4003B25CUL)) +#define FM_RTC_BREG5D *((volatile uint8_t*)(0x4003B25DUL)) +#define FM4_RTC_BREG5D *((volatile uint8_t*)(0x4003B25DUL)) +#define FM_RTC_BREG5E *((volatile uint8_t*)(0x4003B25EUL)) +#define FM4_RTC_BREG5E *((volatile uint8_t*)(0x4003B25EUL)) +#define FM_RTC_BREG5F *((volatile uint8_t*)(0x4003B25FUL)) +#define FM4_RTC_BREG5F *((volatile uint8_t*)(0x4003B25FUL)) +#define FM_RTC_BREG60 *((volatile uint8_t*)(0x4003B260UL)) +#define FM4_RTC_BREG60 *((volatile uint8_t*)(0x4003B260UL)) +#define FM_RTC_BREG61 *((volatile uint8_t*)(0x4003B261UL)) +#define FM4_RTC_BREG61 *((volatile uint8_t*)(0x4003B261UL)) +#define FM_RTC_BREG62 *((volatile uint8_t*)(0x4003B262UL)) +#define FM4_RTC_BREG62 *((volatile uint8_t*)(0x4003B262UL)) +#define FM_RTC_BREG63 *((volatile uint8_t*)(0x4003B263UL)) +#define FM4_RTC_BREG63 *((volatile uint8_t*)(0x4003B263UL)) +#define FM_RTC_BREG64 *((volatile uint8_t*)(0x4003B264UL)) +#define FM4_RTC_BREG64 *((volatile uint8_t*)(0x4003B264UL)) +#define FM_RTC_BREG65 *((volatile uint8_t*)(0x4003B265UL)) +#define FM4_RTC_BREG65 *((volatile uint8_t*)(0x4003B265UL)) +#define FM_RTC_BREG66 *((volatile uint8_t*)(0x4003B266UL)) +#define FM4_RTC_BREG66 *((volatile uint8_t*)(0x4003B266UL)) +#define FM_RTC_BREG67 *((volatile uint8_t*)(0x4003B267UL)) +#define FM4_RTC_BREG67 *((volatile uint8_t*)(0x4003B267UL)) +#define FM_RTC_BREG68 *((volatile uint8_t*)(0x4003B268UL)) +#define FM4_RTC_BREG68 *((volatile uint8_t*)(0x4003B268UL)) +#define FM_RTC_BREG69 *((volatile uint8_t*)(0x4003B269UL)) +#define FM4_RTC_BREG69 *((volatile uint8_t*)(0x4003B269UL)) +#define FM_RTC_BREG6A *((volatile uint8_t*)(0x4003B26AUL)) +#define FM4_RTC_BREG6A *((volatile uint8_t*)(0x4003B26AUL)) +#define FM_RTC_BREG6B *((volatile uint8_t*)(0x4003B26BUL)) +#define FM4_RTC_BREG6B *((volatile uint8_t*)(0x4003B26BUL)) +#define FM_RTC_BREG6C *((volatile uint8_t*)(0x4003B26CUL)) +#define FM4_RTC_BREG6C *((volatile uint8_t*)(0x4003B26CUL)) +#define FM_RTC_BREG6D *((volatile uint8_t*)(0x4003B26DUL)) +#define FM4_RTC_BREG6D *((volatile uint8_t*)(0x4003B26DUL)) +#define FM_RTC_BREG6E *((volatile uint8_t*)(0x4003B26EUL)) +#define FM4_RTC_BREG6E *((volatile uint8_t*)(0x4003B26EUL)) +#define FM_RTC_BREG6F *((volatile uint8_t*)(0x4003B26FUL)) +#define FM4_RTC_BREG6F *((volatile uint8_t*)(0x4003B26FUL)) +#define FM_RTC_BREG70 *((volatile uint8_t*)(0x4003B270UL)) +#define FM4_RTC_BREG70 *((volatile uint8_t*)(0x4003B270UL)) +#define FM_RTC_BREG71 *((volatile uint8_t*)(0x4003B271UL)) +#define FM4_RTC_BREG71 *((volatile uint8_t*)(0x4003B271UL)) +#define FM_RTC_BREG72 *((volatile uint8_t*)(0x4003B272UL)) +#define FM4_RTC_BREG72 *((volatile uint8_t*)(0x4003B272UL)) +#define FM_RTC_BREG73 *((volatile uint8_t*)(0x4003B273UL)) +#define FM4_RTC_BREG73 *((volatile uint8_t*)(0x4003B273UL)) +#define FM_RTC_BREG74 *((volatile uint8_t*)(0x4003B274UL)) +#define FM4_RTC_BREG74 *((volatile uint8_t*)(0x4003B274UL)) +#define FM_RTC_BREG75 *((volatile uint8_t*)(0x4003B275UL)) +#define FM4_RTC_BREG75 *((volatile uint8_t*)(0x4003B275UL)) +#define FM_RTC_BREG76 *((volatile uint8_t*)(0x4003B276UL)) +#define FM4_RTC_BREG76 *((volatile uint8_t*)(0x4003B276UL)) +#define FM_RTC_BREG77 *((volatile uint8_t*)(0x4003B277UL)) +#define FM4_RTC_BREG77 *((volatile uint8_t*)(0x4003B277UL)) +#define FM_RTC_BREG78 *((volatile uint8_t*)(0x4003B278UL)) +#define FM4_RTC_BREG78 *((volatile uint8_t*)(0x4003B278UL)) +#define FM_RTC_BREG79 *((volatile uint8_t*)(0x4003B279UL)) +#define FM4_RTC_BREG79 *((volatile uint8_t*)(0x4003B279UL)) +#define FM_RTC_BREG7A *((volatile uint8_t*)(0x4003B27AUL)) +#define FM4_RTC_BREG7A *((volatile uint8_t*)(0x4003B27AUL)) +#define FM_RTC_BREG7B *((volatile uint8_t*)(0x4003B27BUL)) +#define FM4_RTC_BREG7B *((volatile uint8_t*)(0x4003B27BUL)) +#define FM_RTC_BREG7C *((volatile uint8_t*)(0x4003B27CUL)) +#define FM4_RTC_BREG7C *((volatile uint8_t*)(0x4003B27CUL)) +#define FM_RTC_BREG7D *((volatile uint8_t*)(0x4003B27DUL)) +#define FM4_RTC_BREG7D *((volatile uint8_t*)(0x4003B27DUL)) +#define FM_RTC_BREG7E *((volatile uint8_t*)(0x4003B27EUL)) +#define FM4_RTC_BREG7E *((volatile uint8_t*)(0x4003B27EUL)) +#define FM_RTC_BREG7F *((volatile uint8_t*)(0x4003B27FUL)) +#define FM4_RTC_BREG7F *((volatile uint8_t*)(0x4003B27FUL)) + +/******************************************************************************* +* SBSSR Registers SBSSR +* Register Definition +*******************************************************************************/ +#define FM_SBSSR_BTSSSR *((volatile uint16_t*)(0x40025FFCUL)) +#define FM4_SBSSR_BTSSSR *((volatile uint16_t*)(0x40025FFCUL)) + +/******************************************************************************* +* SDIF Registers SDIF +* Register Definition +*******************************************************************************/ +#define FM_SDIF_SSA2 *((volatile uint32_t*)(0x4006E000UL)) +#define FM4_SDIF_SSA2 *((volatile uint32_t*)(0x4006E000UL)) +#define FM_SDIF_SBSIZE *((volatile uint16_t*)(0x4006E004UL)) +#define FM4_SDIF_SBSIZE *((volatile uint16_t*)(0x4006E004UL)) +#define FM_SDIF_SBLCNT *((volatile uint16_t*)(0x4006E006UL)) +#define FM4_SDIF_SBLCNT *((volatile uint16_t*)(0x4006E006UL)) +#define FM_SDIF_SSA1 *((volatile uint32_t*)(0x4006E008UL)) +#define FM4_SDIF_SSA1 *((volatile uint32_t*)(0x4006E008UL)) +#define FM_SDIF_STRSFMD *((volatile uint16_t*)(0x4006E00CUL)) +#define FM4_SDIF_STRSFMD *((volatile uint16_t*)(0x4006E00CUL)) +#define FM_SDIF_SCMMD *((volatile uint16_t*)(0x4006E00EUL)) +#define FM4_SDIF_SCMMD *((volatile uint16_t*)(0x4006E00EUL)) +#define FM_SDIF_SRESP0 *((volatile uint16_t*)(0x4006E010UL)) +#define FM4_SDIF_SRESP0 *((volatile uint16_t*)(0x4006E010UL)) +#define FM_SDIF_SRESP1 *((volatile uint16_t*)(0x4006E012UL)) +#define FM4_SDIF_SRESP1 *((volatile uint16_t*)(0x4006E012UL)) +#define FM_SDIF_SRESP2 *((volatile uint16_t*)(0x4006E014UL)) +#define FM4_SDIF_SRESP2 *((volatile uint16_t*)(0x4006E014UL)) +#define FM_SDIF_SRESP3 *((volatile uint16_t*)(0x4006E016UL)) +#define FM4_SDIF_SRESP3 *((volatile uint16_t*)(0x4006E016UL)) +#define FM_SDIF_SRESP4 *((volatile uint16_t*)(0x4006E018UL)) +#define FM4_SDIF_SRESP4 *((volatile uint16_t*)(0x4006E018UL)) +#define FM_SDIF_SRESP5 *((volatile uint16_t*)(0x4006E01AUL)) +#define FM4_SDIF_SRESP5 *((volatile uint16_t*)(0x4006E01AUL)) +#define FM_SDIF_SRESP6 *((volatile uint16_t*)(0x4006E01CUL)) +#define FM4_SDIF_SRESP6 *((volatile uint16_t*)(0x4006E01CUL)) +#define FM_SDIF_SRESP7 *((volatile uint16_t*)(0x4006E01EUL)) +#define FM4_SDIF_SRESP7 *((volatile uint16_t*)(0x4006E01EUL)) +#define FM_SDIF_SBUFDP *((volatile uint32_t*)(0x4006E020UL)) +#define FM4_SDIF_SBUFDP *((volatile uint32_t*)(0x4006E020UL)) +#define FM_SDIF_SPRSTAT *((volatile uint32_t*)(0x4006E024UL)) +#define FM4_SDIF_SPRSTAT *((volatile uint32_t*)(0x4006E024UL)) +#define FM_SDIF_SHCTL1 *((volatile uint8_t*)(0x4006E028UL)) +#define FM4_SDIF_SHCTL1 *((volatile uint8_t*)(0x4006E028UL)) +#define FM_SDIF_SPWRCTL *((volatile uint8_t*)(0x4006E029UL)) +#define FM4_SDIF_SPWRCTL *((volatile uint8_t*)(0x4006E029UL)) +#define FM_SDIF_SBLKGPCTL *((volatile uint8_t*)(0x4006E02AUL)) +#define FM4_SDIF_SBLKGPCTL *((volatile uint8_t*)(0x4006E02AUL)) +#define FM_SDIF_SWKUPCTL *((volatile uint8_t*)(0x4006E02BUL)) +#define FM4_SDIF_SWKUPCTL *((volatile uint8_t*)(0x4006E02BUL)) +#define FM_SDIF_SCLKCTL *((volatile uint16_t*)(0x4006E02CUL)) +#define FM4_SDIF_SCLKCTL *((volatile uint16_t*)(0x4006E02CUL)) +#define FM_SDIF_STOCTL *((volatile uint8_t*)(0x4006E02EUL)) +#define FM4_SDIF_STOCTL *((volatile uint8_t*)(0x4006E02EUL)) +#define FM_SDIF_SSRST *((volatile uint8_t*)(0x4006E02FUL)) +#define FM4_SDIF_SSRST *((volatile uint8_t*)(0x4006E02FUL)) +#define FM_SDIF_SNINTST *((volatile uint16_t*)(0x4006E030UL)) +#define FM4_SDIF_SNINTST *((volatile uint16_t*)(0x4006E030UL)) +#define FM_SDIF_SEINTST *((volatile uint16_t*)(0x4006E032UL)) +#define FM4_SDIF_SEINTST *((volatile uint16_t*)(0x4006E032UL)) +#define FM_SDIF_SNINTSTE *((volatile uint16_t*)(0x4006E034UL)) +#define FM4_SDIF_SNINTSTE *((volatile uint16_t*)(0x4006E034UL)) +#define FM_SDIF_SEINTSTE *((volatile uint16_t*)(0x4006E036UL)) +#define FM4_SDIF_SEINTSTE *((volatile uint16_t*)(0x4006E036UL)) +#define FM_SDIF_SNINTSGE *((volatile uint16_t*)(0x4006E038UL)) +#define FM4_SDIF_SNINTSGE *((volatile uint16_t*)(0x4006E038UL)) +#define FM_SDIF_SEINTSGE *((volatile uint16_t*)(0x4006E03AUL)) +#define FM4_SDIF_SEINTSGE *((volatile uint16_t*)(0x4006E03AUL)) +#define FM_SDIF_SACMDEST *((volatile uint16_t*)(0x4006E03CUL)) +#define FM4_SDIF_SACMDEST *((volatile uint16_t*)(0x4006E03CUL)) +#define FM_SDIF_SHCTL2 *((volatile uint16_t*)(0x4006E03EUL)) +#define FM4_SDIF_SHCTL2 *((volatile uint16_t*)(0x4006E03EUL)) +#define FM_SDIF_CAPBLTY0 *((volatile uint16_t*)(0x4006E040UL)) +#define FM4_SDIF_CAPBLTY0 *((volatile uint16_t*)(0x4006E040UL)) +#define FM_SDIF_CAPBLTY1 *((volatile uint16_t*)(0x4006E042UL)) +#define FM4_SDIF_CAPBLTY1 *((volatile uint16_t*)(0x4006E042UL)) +#define FM_SDIF_CAPBLTY2 *((volatile uint16_t*)(0x4006E044UL)) +#define FM4_SDIF_CAPBLTY2 *((volatile uint16_t*)(0x4006E044UL)) +#define FM_SDIF_CAPBLTY3 *((volatile uint16_t*)(0x4006E046UL)) +#define FM4_SDIF_CAPBLTY3 *((volatile uint16_t*)(0x4006E046UL)) +#define FM_SDIF_MXCCAPY0 *((volatile uint16_t*)(0x4006E048UL)) +#define FM4_SDIF_MXCCAPY0 *((volatile uint16_t*)(0x4006E048UL)) +#define FM_SDIF_MXCCAPY1 *((volatile uint16_t*)(0x4006E04AUL)) +#define FM4_SDIF_MXCCAPY1 *((volatile uint16_t*)(0x4006E04AUL)) +#define FM_SDIF_MXCCAPY2 *((volatile uint16_t*)(0x4006E04CUL)) +#define FM4_SDIF_MXCCAPY2 *((volatile uint16_t*)(0x4006E04CUL)) +#define FM_SDIF_MXCCAPY3 *((volatile uint16_t*)(0x4006E04EUL)) +#define FM4_SDIF_MXCCAPY3 *((volatile uint16_t*)(0x4006E04EUL)) +#define FM_SDIF_FEACEST *((volatile uint16_t*)(0x4006E050UL)) +#define FM4_SDIF_FEACEST *((volatile uint16_t*)(0x4006E050UL)) +#define FM_SDIF_SFEEIST *((volatile uint16_t*)(0x4006E052UL)) +#define FM4_SDIF_SFEEIST *((volatile uint16_t*)(0x4006E052UL)) +#define FM_SDIF_ADMAEST *((volatile uint8_t*)(0x4006E054UL)) +#define FM4_SDIF_ADMAEST *((volatile uint8_t*)(0x4006E054UL)) +#define FM_SDIF_SADSA0 *((volatile uint16_t*)(0x4006E058UL)) +#define FM4_SDIF_SADSA0 *((volatile uint16_t*)(0x4006E058UL)) +#define FM_SDIF_SADSA1 *((volatile uint16_t*)(0x4006E05AUL)) +#define FM4_SDIF_SADSA1 *((volatile uint16_t*)(0x4006E05AUL)) +#define FM_SDIF_SADSA2 *((volatile uint16_t*)(0x4006E05CUL)) +#define FM4_SDIF_SADSA2 *((volatile uint16_t*)(0x4006E05CUL)) +#define FM_SDIF_SADSA3 *((volatile uint16_t*)(0x4006E05EUL)) +#define FM4_SDIF_SADSA3 *((volatile uint16_t*)(0x4006E05EUL)) +#define FM_SDIF_SPRVAL0 *((volatile uint16_t*)(0x4006E060UL)) +#define FM4_SDIF_SPRVAL0 *((volatile uint16_t*)(0x4006E060UL)) +#define FM_SDIF_SPRVAL1 *((volatile uint16_t*)(0x4006E062UL)) +#define FM4_SDIF_SPRVAL1 *((volatile uint16_t*)(0x4006E062UL)) +#define FM_SDIF_SPRVAL2 *((volatile uint16_t*)(0x4006E064UL)) +#define FM4_SDIF_SPRVAL2 *((volatile uint16_t*)(0x4006E064UL)) +#define FM_SDIF_SPRVAL3 *((volatile uint16_t*)(0x4006E066UL)) +#define FM4_SDIF_SPRVAL3 *((volatile uint16_t*)(0x4006E066UL)) +#define FM_SDIF_SPRVAL4 *((volatile uint16_t*)(0x4006E068UL)) +#define FM4_SDIF_SPRVAL4 *((volatile uint16_t*)(0x4006E068UL)) +#define FM_SDIF_SPRVAL5 *((volatile uint16_t*)(0x4006E06AUL)) +#define FM4_SDIF_SPRVAL5 *((volatile uint16_t*)(0x4006E06AUL)) +#define FM_SDIF_SPRVAL6 *((volatile uint16_t*)(0x4006E06CUL)) +#define FM4_SDIF_SPRVAL6 *((volatile uint16_t*)(0x4006E06CUL)) +#define FM_SDIF_SPRVAL7 *((volatile uint16_t*)(0x4006E06EUL)) +#define FM4_SDIF_SPRVAL7 *((volatile uint16_t*)(0x4006E06EUL)) +#define FM_SDIF_SSHBCTLL *((volatile uint16_t*)(0x4006E0E0UL)) +#define FM4_SDIF_SSHBCTLL *((volatile uint16_t*)(0x4006E0E0UL)) +#define FM_SDIF_SSHBCTLH *((volatile uint16_t*)(0x4006E0E2UL)) +#define FM4_SDIF_SSHBCTLH *((volatile uint16_t*)(0x4006E0E2UL)) +#define FM_SDIF_SSLIST *((volatile uint16_t*)(0x4006E0FCUL)) +#define FM4_SDIF_SSLIST *((volatile uint16_t*)(0x4006E0FCUL)) +#define FM_SDIF_SHCTLV *((volatile uint16_t*)(0x4006E0FEUL)) +#define FM4_SDIF_SHCTLV *((volatile uint16_t*)(0x4006E0FEUL)) +#define FM_SDIF_AHBCFGL *((volatile uint16_t*)(0x4006E100UL)) +#define FM4_SDIF_AHBCFGL *((volatile uint16_t*)(0x4006E100UL)) +#define FM_SDIF_AHBCFGH *((volatile uint16_t*)(0x4006E102UL)) +#define FM4_SDIF_AHBCFGH *((volatile uint16_t*)(0x4006E102UL)) +#define FM_SDIF_SPWSWCL *((volatile uint16_t*)(0x4006E104UL)) +#define FM4_SDIF_SPWSWCL *((volatile uint16_t*)(0x4006E104UL)) +#define FM_SDIF_SPWSWCH *((volatile uint16_t*)(0x4006E106UL)) +#define FM4_SDIF_SPWSWCH *((volatile uint16_t*)(0x4006E106UL)) +#define FM_SDIF_STUNSETL *((volatile uint16_t*)(0x4006E108UL)) +#define FM4_SDIF_STUNSETL *((volatile uint16_t*)(0x4006E108UL)) +#define FM_SDIF_STUNSETH *((volatile uint16_t*)(0x4006E10AUL)) +#define FM4_SDIF_STUNSETH *((volatile uint16_t*)(0x4006E10AUL)) +#define FM_SDIF_STUNSTL *((volatile uint16_t*)(0x4006E10CUL)) +#define FM4_SDIF_STUNSTL *((volatile uint16_t*)(0x4006E10CUL)) +#define FM_SDIF_STUNSTH *((volatile uint16_t*)(0x4006E10EUL)) +#define FM4_SDIF_STUNSTH *((volatile uint16_t*)(0x4006E10EUL)) +#define FM_SDIF_PSWISTL *((volatile uint16_t*)(0x4006E118UL)) +#define FM4_SDIF_PSWISTL *((volatile uint16_t*)(0x4006E118UL)) +#define FM_SDIF_PSWISTH *((volatile uint16_t*)(0x4006E11AUL)) +#define FM4_SDIF_PSWISTH *((volatile uint16_t*)(0x4006E11AUL)) +#define FM_SDIF_PSWISTEL *((volatile uint16_t*)(0x4006E11CUL)) +#define FM4_SDIF_PSWISTEL *((volatile uint16_t*)(0x4006E11CUL)) +#define FM_SDIF_PSWISTEH *((volatile uint16_t*)(0x4006E11EUL)) +#define FM4_SDIF_PSWISTEH *((volatile uint16_t*)(0x4006E11EUL)) +#define FM_SDIF_PSWISGEL *((volatile uint16_t*)(0x4006E120UL)) +#define FM4_SDIF_PSWISGEL *((volatile uint16_t*)(0x4006E120UL)) +#define FM_SDIF_PSWISGEH *((volatile uint16_t*)(0x4006E122UL)) +#define FM4_SDIF_PSWISGEH *((volatile uint16_t*)(0x4006E122UL)) +#define FM_SDIF_MMCSDCL *((volatile uint16_t*)(0x4006E124UL)) +#define FM4_SDIF_MMCSDCL *((volatile uint16_t*)(0x4006E124UL)) +#define FM_SDIF_MMCSDCH *((volatile uint16_t*)(0x4006E126UL)) +#define FM4_SDIF_MMCSDCH *((volatile uint16_t*)(0x4006E126UL)) +#define FM_SDIF_MCWIRQC0 *((volatile uint16_t*)(0x4006E128UL)) +#define FM4_SDIF_MCWIRQC0 *((volatile uint16_t*)(0x4006E128UL)) +#define FM_SDIF_MCWIRQC1 *((volatile uint16_t*)(0x4006E12AUL)) +#define FM4_SDIF_MCWIRQC1 *((volatile uint16_t*)(0x4006E12AUL)) +#define FM_SDIF_MCWIRQC2 *((volatile uint16_t*)(0x4006E12CUL)) +#define FM4_SDIF_MCWIRQC2 *((volatile uint16_t*)(0x4006E12CUL)) +#define FM_SDIF_MCWIRQC3 *((volatile uint16_t*)(0x4006E12EUL)) +#define FM4_SDIF_MCWIRQC3 *((volatile uint16_t*)(0x4006E12EUL)) +#define FM_SDIF_MCRPCKBL *((volatile uint16_t*)(0x4006E130UL)) +#define FM4_SDIF_MCRPCKBL *((volatile uint16_t*)(0x4006E130UL)) +#define FM_SDIF_MCRPCKBH *((volatile uint16_t*)(0x4006E132UL)) +#define FM4_SDIF_MCRPCKBH *((volatile uint16_t*)(0x4006E132UL)) +#define FM_SDIF_SCDETECS *((volatile uint16_t*)(0x4006E154UL)) +#define FM4_SDIF_SCDETECS *((volatile uint16_t*)(0x4006E154UL)) + +/******************************************************************************* +* SWWDT Registers SWWDT +* Register Definition +*******************************************************************************/ +#define FM_SWWDT_WDOGLOAD *((volatile uint32_t*)(0x40012000UL)) +#define FM4_SWWDT_WDOGLOAD *((volatile uint32_t*)(0x40012000UL)) +#define FM_SWWDT_WDOGVALUE *((volatile uint32_t*)(0x40012004UL)) +#define FM4_SWWDT_WDOGVALUE *((volatile uint32_t*)(0x40012004UL)) +#define FM_SWWDT_WDOGCONTROL *((volatile uint32_t*)(0x40012008UL)) +#define FM4_SWWDT_WDOGCONTROL *((volatile uint32_t*)(0x40012008UL)) +#define FM_SWWDT_WDOGINTCLR *((volatile uint32_t*)(0x4001200CUL)) +#define FM4_SWWDT_WDOGINTCLR *((volatile uint32_t*)(0x4001200CUL)) +#define FM_SWWDT_WDOGRIS *((volatile uint32_t*)(0x40012010UL)) +#define FM4_SWWDT_WDOGRIS *((volatile uint32_t*)(0x40012010UL)) +#define FM_SWWDT_WDOGSPMC *((volatile uint32_t*)(0x40012018UL)) +#define FM4_SWWDT_WDOGSPMC *((volatile uint32_t*)(0x40012018UL)) +#define FM_SWWDT_WDOGLOCK *((volatile uint32_t*)(0x40012C00UL)) +#define FM4_SWWDT_WDOGLOCK *((volatile uint32_t*)(0x40012C00UL)) + +/******************************************************************************* +* UNIQUE_ID Registers UNIQUE_ID +* Register Definition +*******************************************************************************/ +#define FM_UNIQUE_ID_UIDR0 *((volatile uint32_t*)(0x40000200UL)) +#define FM4_UNIQUE_ID_UIDR0 *((volatile uint32_t*)(0x40000200UL)) +#define FM_UNIQUE_ID_UIDR1 *((volatile uint32_t*)(0x40000204UL)) +#define FM4_UNIQUE_ID_UIDR1 *((volatile uint32_t*)(0x40000204UL)) + +/******************************************************************************* +* USB Registers USB0 +* Register Definition +*******************************************************************************/ +#define FM_USB0_HCNT *((volatile uint16_t*)(0x40042100UL)) +#define FM4_USB0_HCNT *((volatile uint16_t*)(0x40042100UL)) +#define FM_USB0_HIRQ *((volatile uint8_t*)(0x40042104UL)) +#define FM4_USB0_HIRQ *((volatile uint8_t*)(0x40042104UL)) +#define FM_USB0_HERR *((volatile uint8_t*)(0x40042105UL)) +#define FM4_USB0_HERR *((volatile uint8_t*)(0x40042105UL)) +#define FM_USB0_HSTATE *((volatile uint8_t*)(0x40042108UL)) +#define FM4_USB0_HSTATE *((volatile uint8_t*)(0x40042108UL)) +#define FM_USB0_HFCOMP *((volatile uint8_t*)(0x40042109UL)) +#define FM4_USB0_HFCOMP *((volatile uint8_t*)(0x40042109UL)) +#define FM_USB0_HRTIMER *((volatile uint16_t*)(0x4004210CUL)) +#define FM4_USB0_HRTIMER *((volatile uint16_t*)(0x4004210CUL)) +#define FM_USB0_HRTIMER2 *((volatile uint8_t*)(0x40042110UL)) +#define FM4_USB0_HRTIMER2 *((volatile uint8_t*)(0x40042110UL)) +#define FM_USB0_HADR *((volatile uint8_t*)(0x40042111UL)) +#define FM4_USB0_HADR *((volatile uint8_t*)(0x40042111UL)) +#define FM_USB0_HEOF *((volatile uint16_t*)(0x40042114UL)) +#define FM4_USB0_HEOF *((volatile uint16_t*)(0x40042114UL)) +#define FM_USB0_HFRAME *((volatile uint16_t*)(0x40042118UL)) +#define FM4_USB0_HFRAME *((volatile uint16_t*)(0x40042118UL)) +#define FM_USB0_HTOKEN *((volatile uint8_t*)(0x4004211CUL)) +#define FM4_USB0_HTOKEN *((volatile uint8_t*)(0x4004211CUL)) +#define FM_USB0_UDCC *((volatile uint16_t*)(0x40042120UL)) +#define FM4_USB0_UDCC *((volatile uint16_t*)(0x40042120UL)) +#define FM_USB0_EP0C *((volatile uint16_t*)(0x40042124UL)) +#define FM4_USB0_EP0C *((volatile uint16_t*)(0x40042124UL)) +#define FM_USB0_EP1C *((volatile uint16_t*)(0x40042128UL)) +#define FM4_USB0_EP1C *((volatile uint16_t*)(0x40042128UL)) +#define FM_USB0_EP2C *((volatile uint16_t*)(0x4004212CUL)) +#define FM4_USB0_EP2C *((volatile uint16_t*)(0x4004212CUL)) +#define FM_USB0_EP3C *((volatile uint16_t*)(0x40042130UL)) +#define FM4_USB0_EP3C *((volatile uint16_t*)(0x40042130UL)) +#define FM_USB0_EP4C *((volatile uint16_t*)(0x40042134UL)) +#define FM4_USB0_EP4C *((volatile uint16_t*)(0x40042134UL)) +#define FM_USB0_EP5C *((volatile uint16_t*)(0x40042138UL)) +#define FM4_USB0_EP5C *((volatile uint16_t*)(0x40042138UL)) +#define FM_USB0_TMSP *((volatile uint16_t*)(0x4004213CUL)) +#define FM4_USB0_TMSP *((volatile uint16_t*)(0x4004213CUL)) +#define FM_USB0_UDCS *((volatile uint8_t*)(0x40042140UL)) +#define FM4_USB0_UDCS *((volatile uint8_t*)(0x40042140UL)) +#define FM_USB0_UDCIE *((volatile uint8_t*)(0x40042141UL)) +#define FM4_USB0_UDCIE *((volatile uint8_t*)(0x40042141UL)) +#define FM_USB0_EP0IS *((volatile uint16_t*)(0x40042144UL)) +#define FM4_USB0_EP0IS *((volatile uint16_t*)(0x40042144UL)) +#define FM_USB0_EP0OS *((volatile uint16_t*)(0x40042148UL)) +#define FM4_USB0_EP0OS *((volatile uint16_t*)(0x40042148UL)) +#define FM_USB0_EP1S *((volatile uint16_t*)(0x4004214CUL)) +#define FM4_USB0_EP1S *((volatile uint16_t*)(0x4004214CUL)) +#define FM_USB0_EP2S *((volatile uint16_t*)(0x40042150UL)) +#define FM4_USB0_EP2S *((volatile uint16_t*)(0x40042150UL)) +#define FM_USB0_EP3S *((volatile uint16_t*)(0x40042154UL)) +#define FM4_USB0_EP3S *((volatile uint16_t*)(0x40042154UL)) +#define FM_USB0_EP4S *((volatile uint16_t*)(0x40042158UL)) +#define FM4_USB0_EP4S *((volatile uint16_t*)(0x40042158UL)) +#define FM_USB0_EP5S *((volatile uint16_t*)(0x4004215CUL)) +#define FM4_USB0_EP5S *((volatile uint16_t*)(0x4004215CUL)) +#define FM_USB0_EP0DT *((volatile uint16_t*)(0x40042160UL)) +#define FM4_USB0_EP0DT *((volatile uint16_t*)(0x40042160UL)) +#define FM_USB0_EP1DT *((volatile uint16_t*)(0x40042164UL)) +#define FM4_USB0_EP1DT *((volatile uint16_t*)(0x40042164UL)) +#define FM_USB0_EP2DT *((volatile uint16_t*)(0x40042168UL)) +#define FM4_USB0_EP2DT *((volatile uint16_t*)(0x40042168UL)) +#define FM_USB0_EP3DT *((volatile uint16_t*)(0x4004216CUL)) +#define FM4_USB0_EP3DT *((volatile uint16_t*)(0x4004216CUL)) +#define FM_USB0_EP4DT *((volatile uint16_t*)(0x40042170UL)) +#define FM4_USB0_EP4DT *((volatile uint16_t*)(0x40042170UL)) +#define FM_USB0_EP5DT *((volatile uint16_t*)(0x40042174UL)) +#define FM4_USB0_EP5DT *((volatile uint16_t*)(0x40042174UL)) + +/******************************************************************************* +* USB Registers USB1 +* Register Definition +*******************************************************************************/ +#define FM_USB1_HCNT *((volatile uint16_t*)(0x40054200UL)) +#define FM4_USB1_HCNT *((volatile uint16_t*)(0x40054200UL)) +#define FM_USB1_HIRQ *((volatile uint8_t*)(0x40054204UL)) +#define FM4_USB1_HIRQ *((volatile uint8_t*)(0x40054204UL)) +#define FM_USB1_HERR *((volatile uint8_t*)(0x40054205UL)) +#define FM4_USB1_HERR *((volatile uint8_t*)(0x40054205UL)) +#define FM_USB1_HSTATE *((volatile uint8_t*)(0x40054208UL)) +#define FM4_USB1_HSTATE *((volatile uint8_t*)(0x40054208UL)) +#define FM_USB1_HFCOMP *((volatile uint8_t*)(0x40054209UL)) +#define FM4_USB1_HFCOMP *((volatile uint8_t*)(0x40054209UL)) +#define FM_USB1_HRTIMER *((volatile uint16_t*)(0x4005420CUL)) +#define FM4_USB1_HRTIMER *((volatile uint16_t*)(0x4005420CUL)) +#define FM_USB1_HRTIMER2 *((volatile uint8_t*)(0x40054210UL)) +#define FM4_USB1_HRTIMER2 *((volatile uint8_t*)(0x40054210UL)) +#define FM_USB1_HADR *((volatile uint8_t*)(0x40054211UL)) +#define FM4_USB1_HADR *((volatile uint8_t*)(0x40054211UL)) +#define FM_USB1_HEOF *((volatile uint16_t*)(0x40054214UL)) +#define FM4_USB1_HEOF *((volatile uint16_t*)(0x40054214UL)) +#define FM_USB1_HFRAME *((volatile uint16_t*)(0x40054218UL)) +#define FM4_USB1_HFRAME *((volatile uint16_t*)(0x40054218UL)) +#define FM_USB1_HTOKEN *((volatile uint8_t*)(0x4005421CUL)) +#define FM4_USB1_HTOKEN *((volatile uint8_t*)(0x4005421CUL)) +#define FM_USB1_UDCC *((volatile uint16_t*)(0x40054220UL)) +#define FM4_USB1_UDCC *((volatile uint16_t*)(0x40054220UL)) +#define FM_USB1_EP0C *((volatile uint16_t*)(0x40054224UL)) +#define FM4_USB1_EP0C *((volatile uint16_t*)(0x40054224UL)) +#define FM_USB1_EP1C *((volatile uint16_t*)(0x40054228UL)) +#define FM4_USB1_EP1C *((volatile uint16_t*)(0x40054228UL)) +#define FM_USB1_EP2C *((volatile uint16_t*)(0x4005422CUL)) +#define FM4_USB1_EP2C *((volatile uint16_t*)(0x4005422CUL)) +#define FM_USB1_EP3C *((volatile uint16_t*)(0x40054230UL)) +#define FM4_USB1_EP3C *((volatile uint16_t*)(0x40054230UL)) +#define FM_USB1_EP4C *((volatile uint16_t*)(0x40054234UL)) +#define FM4_USB1_EP4C *((volatile uint16_t*)(0x40054234UL)) +#define FM_USB1_EP5C *((volatile uint16_t*)(0x40054238UL)) +#define FM4_USB1_EP5C *((volatile uint16_t*)(0x40054238UL)) +#define FM_USB1_TMSP *((volatile uint16_t*)(0x4005423CUL)) +#define FM4_USB1_TMSP *((volatile uint16_t*)(0x4005423CUL)) +#define FM_USB1_UDCS *((volatile uint8_t*)(0x40054240UL)) +#define FM4_USB1_UDCS *((volatile uint8_t*)(0x40054240UL)) +#define FM_USB1_UDCIE *((volatile uint8_t*)(0x40054241UL)) +#define FM4_USB1_UDCIE *((volatile uint8_t*)(0x40054241UL)) +#define FM_USB1_EP0IS *((volatile uint16_t*)(0x40054244UL)) +#define FM4_USB1_EP0IS *((volatile uint16_t*)(0x40054244UL)) +#define FM_USB1_EP0OS *((volatile uint16_t*)(0x40054248UL)) +#define FM4_USB1_EP0OS *((volatile uint16_t*)(0x40054248UL)) +#define FM_USB1_EP1S *((volatile uint16_t*)(0x4005424CUL)) +#define FM4_USB1_EP1S *((volatile uint16_t*)(0x4005424CUL)) +#define FM_USB1_EP2S *((volatile uint16_t*)(0x40054250UL)) +#define FM4_USB1_EP2S *((volatile uint16_t*)(0x40054250UL)) +#define FM_USB1_EP3S *((volatile uint16_t*)(0x40054254UL)) +#define FM4_USB1_EP3S *((volatile uint16_t*)(0x40054254UL)) +#define FM_USB1_EP4S *((volatile uint16_t*)(0x40054258UL)) +#define FM4_USB1_EP4S *((volatile uint16_t*)(0x40054258UL)) +#define FM_USB1_EP5S *((volatile uint16_t*)(0x4005425CUL)) +#define FM4_USB1_EP5S *((volatile uint16_t*)(0x4005425CUL)) +#define FM_USB1_EP0DT *((volatile uint16_t*)(0x40054260UL)) +#define FM4_USB1_EP0DT *((volatile uint16_t*)(0x40054260UL)) +#define FM_USB1_EP1DT *((volatile uint16_t*)(0x40054264UL)) +#define FM4_USB1_EP1DT *((volatile uint16_t*)(0x40054264UL)) +#define FM_USB1_EP2DT *((volatile uint16_t*)(0x40054268UL)) +#define FM4_USB1_EP2DT *((volatile uint16_t*)(0x40054268UL)) +#define FM_USB1_EP3DT *((volatile uint16_t*)(0x4005426CUL)) +#define FM4_USB1_EP3DT *((volatile uint16_t*)(0x4005426CUL)) +#define FM_USB1_EP4DT *((volatile uint16_t*)(0x40054270UL)) +#define FM4_USB1_EP4DT *((volatile uint16_t*)(0x40054270UL)) +#define FM_USB1_EP5DT *((volatile uint16_t*)(0x40054274UL)) +#define FM4_USB1_EP5DT *((volatile uint16_t*)(0x40054274UL)) + +/******************************************************************************* +* USBCLK Registers USBCLK +* Register Definition +*******************************************************************************/ +#define FM_USBCLK_UCCR *((volatile uint8_t*)(0x40036000UL)) +#define FM4_USBCLK_UCCR *((volatile uint8_t*)(0x40036000UL)) +#define FM_USBCLK_UPCR1 *((volatile uint8_t*)(0x40036004UL)) +#define FM4_USBCLK_UPCR1 *((volatile uint8_t*)(0x40036004UL)) +#define FM_USBCLK_UPCR2 *((volatile uint8_t*)(0x40036008UL)) +#define FM4_USBCLK_UPCR2 *((volatile uint8_t*)(0x40036008UL)) +#define FM_USBCLK_UPCR3 *((volatile uint8_t*)(0x4003600CUL)) +#define FM4_USBCLK_UPCR3 *((volatile uint8_t*)(0x4003600CUL)) +#define FM_USBCLK_UPCR4 *((volatile uint8_t*)(0x40036010UL)) +#define FM4_USBCLK_UPCR4 *((volatile uint8_t*)(0x40036010UL)) +#define FM_USBCLK_UP_STR *((volatile uint8_t*)(0x40036014UL)) +#define FM4_USBCLK_UP_STR *((volatile uint8_t*)(0x40036014UL)) +#define FM_USBCLK_UPINT_ENR *((volatile uint8_t*)(0x40036018UL)) +#define FM4_USBCLK_UPINT_ENR *((volatile uint8_t*)(0x40036018UL)) +#define FM_USBCLK_UPINT_CLR *((volatile uint8_t*)(0x4003601CUL)) +#define FM4_USBCLK_UPINT_CLR *((volatile uint8_t*)(0x4003601CUL)) +#define FM_USBCLK_UPINT_STR *((volatile uint8_t*)(0x40036020UL)) +#define FM4_USBCLK_UPINT_STR *((volatile uint8_t*)(0x40036020UL)) +#define FM_USBCLK_UPCR5 *((volatile uint8_t*)(0x40036024UL)) +#define FM4_USBCLK_UPCR5 *((volatile uint8_t*)(0x40036024UL)) +#define FM_USBCLK_USBEN0 *((volatile uint8_t*)(0x40036030UL)) +#define FM4_USBCLK_USBEN0 *((volatile uint8_t*)(0x40036030UL)) +#define FM_USBCLK_USBEN1 *((volatile uint8_t*)(0x40036034UL)) +#define FM4_USBCLK_USBEN1 *((volatile uint8_t*)(0x40036034UL)) + +/******************************************************************************* +* WC Registers WC +* Register Definition +*******************************************************************************/ +#define FM_WC_WCRD *((volatile uint8_t*)(0x4003A000UL)) +#define FM4_WC_WCRD *((volatile uint8_t*)(0x4003A000UL)) +#define FM_WC_WCRL *((volatile uint8_t*)(0x4003A001UL)) +#define FM4_WC_WCRL *((volatile uint8_t*)(0x4003A001UL)) +#define FM_WC_WCCR *((volatile uint8_t*)(0x4003A002UL)) +#define FM4_WC_WCCR *((volatile uint8_t*)(0x4003A002UL)) +#define FM_WC_CLK_SEL *((volatile uint16_t*)(0x4003A010UL)) +#define FM4_WC_CLK_SEL *((volatile uint16_t*)(0x4003A010UL)) +#define FM_WC_CLK_EN *((volatile uint8_t*)(0x4003A014UL)) +#define FM4_WC_CLK_EN *((volatile uint8_t*)(0x4003A014UL)) + +/******************************************************************************* +* Available Registers +*******************************************************************************/ +/******************************************************************************* +* ADC0 +*******************************************************************************/ +#define FM4_ADC_ADCEN_AVAILABLE 1 +#define FM_ADC_ADCEN_AVAILABLE 1 +#define FM4_ADC_ADCR_AVAILABLE 1 +#define FM_ADC_ADCR_AVAILABLE 1 +#define FM4_ADC_ADCT_AVAILABLE 1 +#define FM_ADC_ADCT_AVAILABLE 1 +#define FM4_ADC_ADSR_AVAILABLE 1 +#define FM_ADC_ADSR_AVAILABLE 1 +#define FM4_ADC_ADSS01_AVAILABLE 1 +#define FM_ADC_ADSS01_AVAILABLE 1 +#define FM4_ADC_ADSS23_AVAILABLE 1 +#define FM_ADC_ADSS23_AVAILABLE 1 +#define FM4_ADC_ADST01_AVAILABLE 1 +#define FM_ADC_ADST01_AVAILABLE 1 +#define FM4_ADC_CALSR_AVAILABLE 1 +#define FM_ADC_CALSR_AVAILABLE 1 +#define FM4_ADC_CMPCR_AVAILABLE 1 +#define FM_ADC_CMPCR_AVAILABLE 1 +#define FM4_ADC_CMPD_AVAILABLE 1 +#define FM_ADC_CMPD_AVAILABLE 1 +#define FM4_ADC_PCCR_AVAILABLE 1 +#define FM_ADC_PCCR_AVAILABLE 1 +#define FM4_ADC_PCFD_AVAILABLE 1 +#define FM_ADC_PCFD_AVAILABLE 1 +#define FM4_ADC_PCFD_FDAS1_AVAILABLE 1 +#define FM_ADC_PCFD_FDAS1_AVAILABLE 1 +#define FM4_ADC_PCIS_AVAILABLE 1 +#define FM_ADC_PCIS_AVAILABLE 1 +#define FM4_ADC_PFNS_AVAILABLE 1 +#define FM_ADC_PFNS_AVAILABLE 1 +#define FM4_ADC_PRTSL_AVAILABLE 1 +#define FM_ADC_PRTSL_AVAILABLE 1 +#define FM4_ADC_SCCR_AVAILABLE 1 +#define FM_ADC_SCCR_AVAILABLE 1 +#define FM4_ADC_SCFD_AVAILABLE 1 +#define FM_ADC_SCFD_AVAILABLE 1 +#define FM4_ADC_SCFD_FDAS1_AVAILABLE 1 +#define FM_ADC_SCFD_FDAS1_AVAILABLE 1 +#define FM4_ADC_SCIS01_AVAILABLE 1 +#define FM_ADC_SCIS01_AVAILABLE 1 +#define FM4_ADC_SCIS23_AVAILABLE 1 +#define FM_ADC_SCIS23_AVAILABLE 1 +#define FM4_ADC_SCTSL_AVAILABLE 1 +#define FM_ADC_SCTSL_AVAILABLE 1 +#define FM4_ADC_SFNS_AVAILABLE 1 +#define FM_ADC_SFNS_AVAILABLE 1 +#define FM4_ADC_WCMPCR_AVAILABLE 1 +#define FM_ADC_WCMPCR_AVAILABLE 1 +#define FM4_ADC_WCMPDH_AVAILABLE 1 +#define FM_ADC_WCMPDH_AVAILABLE 1 +#define FM4_ADC_WCMPDL_AVAILABLE 1 +#define FM_ADC_WCMPDL_AVAILABLE 1 +#define FM4_ADC_WCMPSR_AVAILABLE 1 +#define FM_ADC_WCMPSR_AVAILABLE 1 +#define FM4_ADC_WCMRCIF_AVAILABLE 1 +#define FM_ADC_WCMRCIF_AVAILABLE 1 +#define FM4_ADC_WCMRCOT_AVAILABLE 1 +#define FM_ADC_WCMRCOT_AVAILABLE 1 +/******************************************************************************* +* BT0 +*******************************************************************************/ +#define FM4_BT_PPG_PRLH_AVAILABLE 1 +#define FM_BT_PPG_PRLH_AVAILABLE 1 +#define FM4_BT_PPG_PRLL_AVAILABLE 1 +#define FM_BT_PPG_PRLL_AVAILABLE 1 +#define FM4_BT_PPG_STC_AVAILABLE 1 +#define FM_BT_PPG_STC_AVAILABLE 1 +#define FM4_BT_PPG_TMCR_AVAILABLE 1 +#define FM_BT_PPG_TMCR_AVAILABLE 1 +#define FM4_BT_PPG_TMCR2_AVAILABLE 1 +#define FM_BT_PPG_TMCR2_AVAILABLE 1 +#define FM4_BT_PPG_TMR_AVAILABLE 1 +#define FM_BT_PPG_TMR_AVAILABLE 1 +#define FM4_BT_PWC_DTBF_AVAILABLE 1 +#define FM_BT_PWC_DTBF_AVAILABLE 1 +#define FM4_BT_PWC_STC_AVAILABLE 1 +#define FM_BT_PWC_STC_AVAILABLE 1 +#define FM4_BT_PWC_TMCR_AVAILABLE 1 +#define FM_BT_PWC_TMCR_AVAILABLE 1 +#define FM4_BT_PWC_TMCR2_AVAILABLE 1 +#define FM_BT_PWC_TMCR2_AVAILABLE 1 +#define FM4_BT_PWM_PCSR_AVAILABLE 1 +#define FM_BT_PWM_PCSR_AVAILABLE 1 +#define FM4_BT_PWM_PDUT_AVAILABLE 1 +#define FM_BT_PWM_PDUT_AVAILABLE 1 +#define FM4_BT_PWM_STC_AVAILABLE 1 +#define FM_BT_PWM_STC_AVAILABLE 1 +#define FM4_BT_PWM_TMCR_AVAILABLE 1 +#define FM_BT_PWM_TMCR_AVAILABLE 1 +#define FM4_BT_PWM_TMCR2_AVAILABLE 1 +#define FM_BT_PWM_TMCR2_AVAILABLE 1 +#define FM4_BT_PWM_TMR_AVAILABLE 1 +#define FM_BT_PWM_TMR_AVAILABLE 1 +#define FM4_BT_RT_PCSR_AVAILABLE 1 +#define FM_BT_RT_PCSR_AVAILABLE 1 +#define FM4_BT_RT_STC_AVAILABLE 1 +#define FM_BT_RT_STC_AVAILABLE 1 +#define FM4_BT_RT_TMCR_AVAILABLE 1 +#define FM_BT_RT_TMCR_AVAILABLE 1 +#define FM4_BT_RT_TMCR2_AVAILABLE 1 +#define FM_BT_RT_TMCR2_AVAILABLE 1 +#define FM4_BT_RT_TMR_AVAILABLE 1 +#define FM_BT_RT_TMR_AVAILABLE 1 +/******************************************************************************* +* BTIOSEL03 +*******************************************************************************/ +#define FM4_BTIOSEL03_BTSEL0123_AVAILABLE 1 +#define FM_BTIOSEL03_BTSEL0123_AVAILABLE 1 +/******************************************************************************* +* BTIOSEL47 +*******************************************************************************/ +#define FM4_BTIOSEL47_BTSEL4567_AVAILABLE 1 +#define FM_BTIOSEL47_BTSEL4567_AVAILABLE 1 +/******************************************************************************* +* BTIOSEL8B +*******************************************************************************/ +#define FM4_BTIOSEL8B_BTSEL89AB_AVAILABLE 1 +#define FM_BTIOSEL8B_BTSEL89AB_AVAILABLE 1 +/******************************************************************************* +* BTIOSELCF +*******************************************************************************/ +#define FM4_BTIOSELCF_BTSELCDEF_AVAILABLE 1 +#define FM_BTIOSELCF_BTSELCDEF_AVAILABLE 1 +/******************************************************************************* +* CAN0 +*******************************************************************************/ +#define FM4_CAN_BRPER_AVAILABLE 1 +#define FM_CAN_BRPER_AVAILABLE 1 +#define FM4_CAN_BTR_AVAILABLE 1 +#define FM_CAN_BTR_AVAILABLE 1 +#define FM4_CAN_CTRLR_AVAILABLE 1 +#define FM_CAN_CTRLR_AVAILABLE 1 +#define FM4_CAN_ERRCNT_AVAILABLE 1 +#define FM_CAN_ERRCNT_AVAILABLE 1 +#define FM4_CAN_IF1ARB_AVAILABLE 1 +#define FM_CAN_IF1ARB_AVAILABLE 1 +#define FM4_CAN_IF1CMSK_AVAILABLE 1 +#define FM_CAN_IF1CMSK_AVAILABLE 1 +#define FM4_CAN_IF1CREQ_AVAILABLE 1 +#define FM_CAN_IF1CREQ_AVAILABLE 1 +#define FM4_CAN_IF1DTA_B_AVAILABLE 1 +#define FM_CAN_IF1DTA_B_AVAILABLE 1 +#define FM4_CAN_IF1DTA_L_AVAILABLE 1 +#define FM_CAN_IF1DTA_L_AVAILABLE 1 +#define FM4_CAN_IF1DTB_B_AVAILABLE 1 +#define FM_CAN_IF1DTB_B_AVAILABLE 1 +#define FM4_CAN_IF1DTB_L_AVAILABLE 1 +#define FM_CAN_IF1DTB_L_AVAILABLE 1 +#define FM4_CAN_IF1MCTR_AVAILABLE 1 +#define FM_CAN_IF1MCTR_AVAILABLE 1 +#define FM4_CAN_IF1MSK_AVAILABLE 1 +#define FM_CAN_IF1MSK_AVAILABLE 1 +#define FM4_CAN_IF2ARB_AVAILABLE 1 +#define FM_CAN_IF2ARB_AVAILABLE 1 +#define FM4_CAN_IF2CMSK_AVAILABLE 1 +#define FM_CAN_IF2CMSK_AVAILABLE 1 +#define FM4_CAN_IF2CREQ_AVAILABLE 1 +#define FM_CAN_IF2CREQ_AVAILABLE 1 +#define FM4_CAN_IF2DTA_B_AVAILABLE 1 +#define FM_CAN_IF2DTA_B_AVAILABLE 1 +#define FM4_CAN_IF2DTA_L_AVAILABLE 1 +#define FM_CAN_IF2DTA_L_AVAILABLE 1 +#define FM4_CAN_IF2DTB_B_AVAILABLE 1 +#define FM_CAN_IF2DTB_B_AVAILABLE 1 +#define FM4_CAN_IF2DTB_L_AVAILABLE 1 +#define FM_CAN_IF2DTB_L_AVAILABLE 1 +#define FM4_CAN_IF2MCTR_AVAILABLE 1 +#define FM_CAN_IF2MCTR_AVAILABLE 1 +#define FM4_CAN_IF2MSK_AVAILABLE 1 +#define FM_CAN_IF2MSK_AVAILABLE 1 +#define FM4_CAN_INTPND_AVAILABLE 1 +#define FM_CAN_INTPND_AVAILABLE 1 +#define FM4_CAN_INTR_AVAILABLE 1 +#define FM_CAN_INTR_AVAILABLE 1 +#define FM4_CAN_MSGVAL_AVAILABLE 1 +#define FM_CAN_MSGVAL_AVAILABLE 1 +#define FM4_CAN_NEWDT_AVAILABLE 1 +#define FM_CAN_NEWDT_AVAILABLE 1 +#define FM4_CAN_STATR_AVAILABLE 1 +#define FM_CAN_STATR_AVAILABLE 1 +#define FM4_CAN_TESTR_AVAILABLE 1 +#define FM_CAN_TESTR_AVAILABLE 1 +#define FM4_CAN_TREQR_AVAILABLE 1 +#define FM_CAN_TREQR_AVAILABLE 1 +/******************************************************************************* +* CANFD0 +*******************************************************************************/ +#define FM4_CANFD_BTP_AVAILABLE 1 +#define FM_CANFD_BTP_AVAILABLE 1 +#define FM4_CANFD_CCCR_AVAILABLE 1 +#define FM_CANFD_CCCR_AVAILABLE 1 +#define FM4_CANFD_CREL_AVAILABLE 1 +#define FM_CANFD_CREL_AVAILABLE 1 +#define FM4_CANFD_ECR_AVAILABLE 1 +#define FM_CANFD_ECR_AVAILABLE 1 +#define FM4_CANFD_ENDN_AVAILABLE 1 +#define FM_CANFD_ENDN_AVAILABLE 1 +#define FM4_CANFD_FBTP_AVAILABLE 1 +#define FM_CANFD_FBTP_AVAILABLE 1 +#define FM4_CANFD_FDDEAR_AVAILABLE 1 +#define FM_CANFD_FDDEAR_AVAILABLE 1 +#define FM4_CANFD_FDECR_AVAILABLE 1 +#define FM_CANFD_FDECR_AVAILABLE 1 +#define FM4_CANFD_FDESCR_AVAILABLE 1 +#define FM_CANFD_FDESCR_AVAILABLE 1 +#define FM4_CANFD_FDESR_AVAILABLE 1 +#define FM_CANFD_FDESR_AVAILABLE 1 +#define FM4_CANFD_FDSEAR_AVAILABLE 1 +#define FM_CANFD_FDSEAR_AVAILABLE 1 +#define FM4_CANFD_GFC_AVAILABLE 1 +#define FM_CANFD_GFC_AVAILABLE 1 +#define FM4_CANFD_HPMS_AVAILABLE 1 +#define FM_CANFD_HPMS_AVAILABLE 1 +#define FM4_CANFD_IE_AVAILABLE 1 +#define FM_CANFD_IE_AVAILABLE 1 +#define FM4_CANFD_ILE_AVAILABLE 1 +#define FM_CANFD_ILE_AVAILABLE 1 +#define FM4_CANFD_ILS_AVAILABLE 1 +#define FM_CANFD_ILS_AVAILABLE 1 +#define FM4_CANFD_IR_AVAILABLE 1 +#define FM_CANFD_IR_AVAILABLE 1 +#define FM4_CANFD_NDAT1_AVAILABLE 1 +#define FM_CANFD_NDAT1_AVAILABLE 1 +#define FM4_CANFD_NDAT2_AVAILABLE 1 +#define FM_CANFD_NDAT2_AVAILABLE 1 +#define FM4_CANFD_PSR_AVAILABLE 1 +#define FM_CANFD_PSR_AVAILABLE 1 +#define FM4_CANFD_RWD_AVAILABLE 1 +#define FM_CANFD_RWD_AVAILABLE 1 +#define FM4_CANFD_RXBC_AVAILABLE 1 +#define FM_CANFD_RXBC_AVAILABLE 1 +#define FM4_CANFD_RXESC_AVAILABLE 1 +#define FM_CANFD_RXESC_AVAILABLE 1 +#define FM4_CANFD_RXF0A_AVAILABLE 1 +#define FM_CANFD_RXF0A_AVAILABLE 1 +#define FM4_CANFD_RXF0C_AVAILABLE 1 +#define FM_CANFD_RXF0C_AVAILABLE 1 +#define FM4_CANFD_RXF0S_AVAILABLE 1 +#define FM_CANFD_RXF0S_AVAILABLE 1 +#define FM4_CANFD_RXF1A_AVAILABLE 1 +#define FM_CANFD_RXF1A_AVAILABLE 1 +#define FM4_CANFD_RXF1C_AVAILABLE 1 +#define FM_CANFD_RXF1C_AVAILABLE 1 +#define FM4_CANFD_RXF1S_AVAILABLE 1 +#define FM_CANFD_RXF1S_AVAILABLE 1 +#define FM4_CANFD_SIDFC_AVAILABLE 1 +#define FM_CANFD_SIDFC_AVAILABLE 1 +#define FM4_CANFD_TEST_AVAILABLE 1 +#define FM_CANFD_TEST_AVAILABLE 1 +#define FM4_CANFD_TOCC_AVAILABLE 1 +#define FM_CANFD_TOCC_AVAILABLE 1 +#define FM4_CANFD_TOCV_AVAILABLE 1 +#define FM_CANFD_TOCV_AVAILABLE 1 +#define FM4_CANFD_TSCC_AVAILABLE 1 +#define FM_CANFD_TSCC_AVAILABLE 1 +#define FM4_CANFD_TSCDTR_AVAILABLE 1 +#define FM_CANFD_TSCDTR_AVAILABLE 1 +#define FM4_CANFD_TSCNTR_AVAILABLE 1 +#define FM_CANFD_TSCNTR_AVAILABLE 1 +#define FM4_CANFD_TSCPCLR_AVAILABLE 1 +#define FM_CANFD_TSCPCLR_AVAILABLE 1 +#define FM4_CANFD_TSCV_AVAILABLE 1 +#define FM_CANFD_TSCV_AVAILABLE 1 +#define FM4_CANFD_TSDIVR_AVAILABLE 1 +#define FM_CANFD_TSDIVR_AVAILABLE 1 +#define FM4_CANFD_TSMDR_AVAILABLE 1 +#define FM_CANFD_TSMDR_AVAILABLE 1 +#define FM4_CANFD_TXBAR_AVAILABLE 1 +#define FM_CANFD_TXBAR_AVAILABLE 1 +#define FM4_CANFD_TXBC_AVAILABLE 1 +#define FM_CANFD_TXBC_AVAILABLE 1 +#define FM4_CANFD_TXBCF_AVAILABLE 1 +#define FM_CANFD_TXBCF_AVAILABLE 1 +#define FM4_CANFD_TXBCIE_AVAILABLE 1 +#define FM_CANFD_TXBCIE_AVAILABLE 1 +#define FM4_CANFD_TXBCR_AVAILABLE 1 +#define FM_CANFD_TXBCR_AVAILABLE 1 +#define FM4_CANFD_TXBRP_AVAILABLE 1 +#define FM_CANFD_TXBRP_AVAILABLE 1 +#define FM4_CANFD_TXBTIE_AVAILABLE 1 +#define FM_CANFD_TXBTIE_AVAILABLE 1 +#define FM4_CANFD_TXBTO_AVAILABLE 1 +#define FM_CANFD_TXBTO_AVAILABLE 1 +#define FM4_CANFD_TXEFC_AVAILABLE 1 +#define FM_CANFD_TXEFC_AVAILABLE 1 +#define FM4_CANFD_TXESC_AVAILABLE 1 +#define FM_CANFD_TXESC_AVAILABLE 1 +#define FM4_CANFD_TXFA_AVAILABLE 1 +#define FM_CANFD_TXFA_AVAILABLE 1 +#define FM4_CANFD_TXFQS_AVAILABLE 1 +#define FM_CANFD_TXFQS_AVAILABLE 1 +#define FM4_CANFD_TXFS_AVAILABLE 1 +#define FM_CANFD_TXFS_AVAILABLE 1 +#define FM4_CANFD_XIDAM_AVAILABLE 1 +#define FM_CANFD_XIDAM_AVAILABLE 1 +#define FM4_CANFD_XIDFC_AVAILABLE 1 +#define FM_CANFD_XIDFC_AVAILABLE 1 +/******************************************************************************* +* CANPRES +*******************************************************************************/ +#define FM4_CANPRES_CANPRE_AVAILABLE 1 +#define FM_CANPRES_CANPRE_AVAILABLE 1 +/******************************************************************************* +* CLK_GATING +*******************************************************************************/ +#define FM4_CLK_GATING_CKEN0_AVAILABLE 1 +#define FM_CLK_GATING_CKEN0_AVAILABLE 1 +#define FM4_CLK_GATING_CKEN1_AVAILABLE 1 +#define FM_CLK_GATING_CKEN1_AVAILABLE 1 +#define FM4_CLK_GATING_CKEN2_AVAILABLE 1 +#define FM_CLK_GATING_CKEN2_AVAILABLE 1 +#define FM4_CLK_GATING_MRST0_AVAILABLE 1 +#define FM_CLK_GATING_MRST0_AVAILABLE 1 +#define FM4_CLK_GATING_MRST1_AVAILABLE 1 +#define FM_CLK_GATING_MRST1_AVAILABLE 1 +#define FM4_CLK_GATING_MRST2_AVAILABLE 1 +#define FM_CLK_GATING_MRST2_AVAILABLE 1 +/******************************************************************************* +* CRC +*******************************************************************************/ +#define FM4_CRC_CRCCR_AVAILABLE 1 +#define FM_CRC_CRCCR_AVAILABLE 1 +#define FM4_CRC_CRCIN_AVAILABLE 1 +#define FM_CRC_CRCIN_AVAILABLE 1 +#define FM4_CRC_CRCINIT_AVAILABLE 1 +#define FM_CRC_CRCINIT_AVAILABLE 1 +#define FM4_CRC_CRCR_AVAILABLE 1 +#define FM_CRC_CRCR_AVAILABLE 1 +/******************************************************************************* +* CRG +*******************************************************************************/ +#define FM4_CRG_APBC0_PSR_AVAILABLE 1 +#define FM_CRG_APBC0_PSR_AVAILABLE 1 +#define FM4_CRG_APBC1_PSR_AVAILABLE 1 +#define FM_CRG_APBC1_PSR_AVAILABLE 1 +#define FM4_CRG_APBC2_PSR_AVAILABLE 1 +#define FM_CRG_APBC2_PSR_AVAILABLE 1 +#define FM4_CRG_BSC_PSR_AVAILABLE 1 +#define FM_CRG_BSC_PSR_AVAILABLE 1 +#define FM4_CRG_CSV_CTL_AVAILABLE 1 +#define FM_CRG_CSV_CTL_AVAILABLE 1 +#define FM4_CRG_CSV_STR_AVAILABLE 1 +#define FM_CRG_CSV_STR_AVAILABLE 1 +#define FM4_CRG_CSW_TMR_AVAILABLE 1 +#define FM_CRG_CSW_TMR_AVAILABLE 1 +#define FM4_CRG_DBWDT_CTL_AVAILABLE 1 +#define FM_CRG_DBWDT_CTL_AVAILABLE 1 +#define FM4_CRG_FCSWD_CTL_AVAILABLE 1 +#define FM_CRG_FCSWD_CTL_AVAILABLE 1 +#define FM4_CRG_FCSWH_CTL_AVAILABLE 1 +#define FM_CRG_FCSWH_CTL_AVAILABLE 1 +#define FM4_CRG_FCSWL_CTL_AVAILABLE 1 +#define FM_CRG_FCSWL_CTL_AVAILABLE 1 +#define FM4_CRG_INT_CLR_AVAILABLE 1 +#define FM_CRG_INT_CLR_AVAILABLE 1 +#define FM4_CRG_INT_ENR_AVAILABLE 1 +#define FM_CRG_INT_ENR_AVAILABLE 1 +#define FM4_CRG_INT_STR_AVAILABLE 1 +#define FM_CRG_INT_STR_AVAILABLE 1 +#define FM4_CRG_PLL_CTL1_AVAILABLE 1 +#define FM_CRG_PLL_CTL1_AVAILABLE 1 +#define FM4_CRG_PLL_CTL2_AVAILABLE 1 +#define FM_CRG_PLL_CTL2_AVAILABLE 1 +#define FM4_CRG_PLLCG_CTL_AVAILABLE 1 +#define FM_CRG_PLLCG_CTL_AVAILABLE 1 +#define FM4_CRG_PSW_TMR_AVAILABLE 1 +#define FM_CRG_PSW_TMR_AVAILABLE 1 +#define FM4_CRG_RST_STR_AVAILABLE 1 +#define FM_CRG_RST_STR_AVAILABLE 1 +#define FM4_CRG_SCM_CTL_AVAILABLE 1 +#define FM_CRG_SCM_CTL_AVAILABLE 1 +#define FM4_CRG_SCM_STR_AVAILABLE 1 +#define FM_CRG_SCM_STR_AVAILABLE 1 +#define FM4_CRG_STB_CTL_AVAILABLE 1 +#define FM_CRG_STB_CTL_AVAILABLE 1 +#define FM4_CRG_SWC_PSR_AVAILABLE 1 +#define FM_CRG_SWC_PSR_AVAILABLE 1 +#define FM4_CRG_TTC_PSR_AVAILABLE 1 +#define FM_CRG_TTC_PSR_AVAILABLE 1 +/******************************************************************************* +* CRTRIM +*******************************************************************************/ +#define FM4_CRTRIM_MCR_FTRM_AVAILABLE 1 +#define FM_CRTRIM_MCR_FTRM_AVAILABLE 1 +#define FM4_CRTRIM_MCR_PSR_AVAILABLE 1 +#define FM_CRTRIM_MCR_PSR_AVAILABLE 1 +#define FM4_CRTRIM_MCR_RLR_AVAILABLE 1 +#define FM_CRTRIM_MCR_RLR_AVAILABLE 1 +#define FM4_CRTRIM_MCR_TTRM_AVAILABLE 1 +#define FM_CRTRIM_MCR_TTRM_AVAILABLE 1 +/******************************************************************************* +* DAC0 +*******************************************************************************/ +#define FM4_DAC_DACR_AVAILABLE 1 +#define FM_DAC_DACR_AVAILABLE 1 +#define FM4_DAC_DADR_AVAILABLE 1 +#define FM_DAC_DADR_AVAILABLE 1 +/******************************************************************************* +* DMAC +*******************************************************************************/ +#define FM4_DMAC_DMACA0_AVAILABLE 1 +#define FM_DMAC_DMACA0_AVAILABLE 1 +#define FM4_DMAC_DMACA1_AVAILABLE 1 +#define FM_DMAC_DMACA1_AVAILABLE 1 +#define FM4_DMAC_DMACA2_AVAILABLE 1 +#define FM_DMAC_DMACA2_AVAILABLE 1 +#define FM4_DMAC_DMACA3_AVAILABLE 1 +#define FM_DMAC_DMACA3_AVAILABLE 1 +#define FM4_DMAC_DMACA4_AVAILABLE 1 +#define FM_DMAC_DMACA4_AVAILABLE 1 +#define FM4_DMAC_DMACA5_AVAILABLE 1 +#define FM_DMAC_DMACA5_AVAILABLE 1 +#define FM4_DMAC_DMACA6_AVAILABLE 1 +#define FM_DMAC_DMACA6_AVAILABLE 1 +#define FM4_DMAC_DMACA7_AVAILABLE 1 +#define FM_DMAC_DMACA7_AVAILABLE 1 +#define FM4_DMAC_DMACB0_AVAILABLE 1 +#define FM_DMAC_DMACB0_AVAILABLE 1 +#define FM4_DMAC_DMACB1_AVAILABLE 1 +#define FM_DMAC_DMACB1_AVAILABLE 1 +#define FM4_DMAC_DMACB2_AVAILABLE 1 +#define FM_DMAC_DMACB2_AVAILABLE 1 +#define FM4_DMAC_DMACB3_AVAILABLE 1 +#define FM_DMAC_DMACB3_AVAILABLE 1 +#define FM4_DMAC_DMACB4_AVAILABLE 1 +#define FM_DMAC_DMACB4_AVAILABLE 1 +#define FM4_DMAC_DMACB5_AVAILABLE 1 +#define FM_DMAC_DMACB5_AVAILABLE 1 +#define FM4_DMAC_DMACB6_AVAILABLE 1 +#define FM_DMAC_DMACB6_AVAILABLE 1 +#define FM4_DMAC_DMACB7_AVAILABLE 1 +#define FM_DMAC_DMACB7_AVAILABLE 1 +#define FM4_DMAC_DMACDA0_AVAILABLE 1 +#define FM_DMAC_DMACDA0_AVAILABLE 1 +#define FM4_DMAC_DMACDA1_AVAILABLE 1 +#define FM_DMAC_DMACDA1_AVAILABLE 1 +#define FM4_DMAC_DMACDA2_AVAILABLE 1 +#define FM_DMAC_DMACDA2_AVAILABLE 1 +#define FM4_DMAC_DMACDA3_AVAILABLE 1 +#define FM_DMAC_DMACDA3_AVAILABLE 1 +#define FM4_DMAC_DMACDA4_AVAILABLE 1 +#define FM_DMAC_DMACDA4_AVAILABLE 1 +#define FM4_DMAC_DMACDA5_AVAILABLE 1 +#define FM_DMAC_DMACDA5_AVAILABLE 1 +#define FM4_DMAC_DMACDA6_AVAILABLE 1 +#define FM_DMAC_DMACDA6_AVAILABLE 1 +#define FM4_DMAC_DMACDA7_AVAILABLE 1 +#define FM_DMAC_DMACDA7_AVAILABLE 1 +#define FM4_DMAC_DMACR_AVAILABLE 1 +#define FM_DMAC_DMACR_AVAILABLE 1 +#define FM4_DMAC_DMACSA0_AVAILABLE 1 +#define FM_DMAC_DMACSA0_AVAILABLE 1 +#define FM4_DMAC_DMACSA1_AVAILABLE 1 +#define FM_DMAC_DMACSA1_AVAILABLE 1 +#define FM4_DMAC_DMACSA2_AVAILABLE 1 +#define FM_DMAC_DMACSA2_AVAILABLE 1 +#define FM4_DMAC_DMACSA3_AVAILABLE 1 +#define FM_DMAC_DMACSA3_AVAILABLE 1 +#define FM4_DMAC_DMACSA4_AVAILABLE 1 +#define FM_DMAC_DMACSA4_AVAILABLE 1 +#define FM4_DMAC_DMACSA5_AVAILABLE 1 +#define FM_DMAC_DMACSA5_AVAILABLE 1 +#define FM4_DMAC_DMACSA6_AVAILABLE 1 +#define FM_DMAC_DMACSA6_AVAILABLE 1 +#define FM4_DMAC_DMACSA7_AVAILABLE 1 +#define FM_DMAC_DMACSA7_AVAILABLE 1 +/******************************************************************************* +* DS +*******************************************************************************/ +#define FM4_DS_BUR01_AVAILABLE 1 +#define FM_DS_BUR01_AVAILABLE 1 +#define FM4_DS_BUR02_AVAILABLE 1 +#define FM_DS_BUR02_AVAILABLE 1 +#define FM4_DS_BUR03_AVAILABLE 1 +#define FM_DS_BUR03_AVAILABLE 1 +#define FM4_DS_BUR04_AVAILABLE 1 +#define FM_DS_BUR04_AVAILABLE 1 +#define FM4_DS_BUR05_AVAILABLE 1 +#define FM_DS_BUR05_AVAILABLE 1 +#define FM4_DS_BUR06_AVAILABLE 1 +#define FM_DS_BUR06_AVAILABLE 1 +#define FM4_DS_BUR07_AVAILABLE 1 +#define FM_DS_BUR07_AVAILABLE 1 +#define FM4_DS_BUR08_AVAILABLE 1 +#define FM_DS_BUR08_AVAILABLE 1 +#define FM4_DS_BUR09_AVAILABLE 1 +#define FM_DS_BUR09_AVAILABLE 1 +#define FM4_DS_BUR10_AVAILABLE 1 +#define FM_DS_BUR10_AVAILABLE 1 +#define FM4_DS_BUR11_AVAILABLE 1 +#define FM_DS_BUR11_AVAILABLE 1 +#define FM4_DS_BUR12_AVAILABLE 1 +#define FM_DS_BUR12_AVAILABLE 1 +#define FM4_DS_BUR13_AVAILABLE 1 +#define FM_DS_BUR13_AVAILABLE 1 +#define FM4_DS_BUR14_AVAILABLE 1 +#define FM_DS_BUR14_AVAILABLE 1 +#define FM4_DS_BUR15_AVAILABLE 1 +#define FM_DS_BUR15_AVAILABLE 1 +#define FM4_DS_BUR16_AVAILABLE 1 +#define FM_DS_BUR16_AVAILABLE 1 +#define FM4_DS_DSRAMR_AVAILABLE 1 +#define FM_DS_DSRAMR_AVAILABLE 1 +#define FM4_DS_PMD_CTL_AVAILABLE 1 +#define FM_DS_PMD_CTL_AVAILABLE 1 +#define FM4_DS_RCK_CTL_AVAILABLE 1 +#define FM_DS_RCK_CTL_AVAILABLE 1 +#define FM4_DS_WIER_AVAILABLE 1 +#define FM_DS_WIER_AVAILABLE 1 +#define FM4_DS_WIFSR_AVAILABLE 1 +#define FM_DS_WIFSR_AVAILABLE 1 +#define FM4_DS_WILVR_AVAILABLE 1 +#define FM_DS_WILVR_AVAILABLE 1 +#define FM4_DS_WRFSR_AVAILABLE 1 +#define FM_DS_WRFSR_AVAILABLE 1 +/******************************************************************************* +* DSTC +*******************************************************************************/ +#define FM4_DSTC_CFG_AVAILABLE 1 +#define FM_DSTC_CFG_AVAILABLE 1 +#define FM4_DSTC_CMD_AVAILABLE 1 +#define FM_DSTC_CMD_AVAILABLE 1 +#define FM4_DSTC_DESTP_AVAILABLE 1 +#define FM_DSTC_DESTP_AVAILABLE 1 +#define FM4_DSTC_DQMSK0_AVAILABLE 1 +#define FM_DSTC_DQMSK0_AVAILABLE 1 +#define FM4_DSTC_DQMSK1_AVAILABLE 1 +#define FM_DSTC_DQMSK1_AVAILABLE 1 +#define FM4_DSTC_DQMSK2_AVAILABLE 1 +#define FM_DSTC_DQMSK2_AVAILABLE 1 +#define FM4_DSTC_DQMSK3_AVAILABLE 1 +#define FM_DSTC_DQMSK3_AVAILABLE 1 +#define FM4_DSTC_DQMSK4_AVAILABLE 1 +#define FM_DSTC_DQMSK4_AVAILABLE 1 +#define FM4_DSTC_DQMSK5_AVAILABLE 1 +#define FM_DSTC_DQMSK5_AVAILABLE 1 +#define FM4_DSTC_DQMSK6_AVAILABLE 1 +#define FM_DSTC_DQMSK6_AVAILABLE 1 +#define FM4_DSTC_DQMSK7_AVAILABLE 1 +#define FM_DSTC_DQMSK7_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR0_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR0_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR1_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR1_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR2_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR2_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR3_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR3_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR4_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR4_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR5_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR5_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR6_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR6_AVAILABLE 1 +#define FM4_DSTC_DQMSKCLR7_AVAILABLE 1 +#define FM_DSTC_DQMSKCLR7_AVAILABLE 1 +#define FM4_DSTC_DREQENB0_AVAILABLE 1 +#define FM_DSTC_DREQENB0_AVAILABLE 1 +#define FM4_DSTC_DREQENB1_AVAILABLE 1 +#define FM_DSTC_DREQENB1_AVAILABLE 1 +#define FM4_DSTC_DREQENB2_AVAILABLE 1 +#define FM_DSTC_DREQENB2_AVAILABLE 1 +#define FM4_DSTC_DREQENB3_AVAILABLE 1 +#define FM_DSTC_DREQENB3_AVAILABLE 1 +#define FM4_DSTC_DREQENB4_AVAILABLE 1 +#define FM_DSTC_DREQENB4_AVAILABLE 1 +#define FM4_DSTC_DREQENB5_AVAILABLE 1 +#define FM_DSTC_DREQENB5_AVAILABLE 1 +#define FM4_DSTC_DREQENB6_AVAILABLE 1 +#define FM_DSTC_DREQENB6_AVAILABLE 1 +#define FM4_DSTC_DREQENB7_AVAILABLE 1 +#define FM_DSTC_DREQENB7_AVAILABLE 1 +#define FM4_DSTC_HWDESP_AVAILABLE 1 +#define FM_DSTC_HWDESP_AVAILABLE 1 +#define FM4_DSTC_HWINT0_AVAILABLE 1 +#define FM_DSTC_HWINT0_AVAILABLE 1 +#define FM4_DSTC_HWINT1_AVAILABLE 1 +#define FM_DSTC_HWINT1_AVAILABLE 1 +#define FM4_DSTC_HWINT2_AVAILABLE 1 +#define FM_DSTC_HWINT2_AVAILABLE 1 +#define FM4_DSTC_HWINT3_AVAILABLE 1 +#define FM_DSTC_HWINT3_AVAILABLE 1 +#define FM4_DSTC_HWINT4_AVAILABLE 1 +#define FM_DSTC_HWINT4_AVAILABLE 1 +#define FM4_DSTC_HWINT5_AVAILABLE 1 +#define FM_DSTC_HWINT5_AVAILABLE 1 +#define FM4_DSTC_HWINT6_AVAILABLE 1 +#define FM_DSTC_HWINT6_AVAILABLE 1 +#define FM4_DSTC_HWINT7_AVAILABLE 1 +#define FM_DSTC_HWINT7_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR0_AVAILABLE 1 +#define FM_DSTC_HWINTCLR0_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR1_AVAILABLE 1 +#define FM_DSTC_HWINTCLR1_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR2_AVAILABLE 1 +#define FM_DSTC_HWINTCLR2_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR3_AVAILABLE 1 +#define FM_DSTC_HWINTCLR3_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR4_AVAILABLE 1 +#define FM_DSTC_HWINTCLR4_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR5_AVAILABLE 1 +#define FM_DSTC_HWINTCLR5_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR6_AVAILABLE 1 +#define FM_DSTC_HWINTCLR6_AVAILABLE 1 +#define FM4_DSTC_HWINTCLR7_AVAILABLE 1 +#define FM_DSTC_HWINTCLR7_AVAILABLE 1 +#define FM4_DSTC_MONERS_AVAILABLE 1 +#define FM_DSTC_MONERS_AVAILABLE 1 +#define FM4_DSTC_SWTR_AVAILABLE 1 +#define FM_DSTC_SWTR_AVAILABLE 1 +/******************************************************************************* +* DT +*******************************************************************************/ +#define FM4_DT_TIMER1BGLOAD_AVAILABLE 1 +#define FM_DT_TIMER1BGLOAD_AVAILABLE 1 +#define FM4_DT_TIMER1CONTROL_AVAILABLE 1 +#define FM_DT_TIMER1CONTROL_AVAILABLE 1 +#define FM4_DT_TIMER1INTCLR_AVAILABLE 1 +#define FM_DT_TIMER1INTCLR_AVAILABLE 1 +#define FM4_DT_TIMER1LOAD_AVAILABLE 1 +#define FM_DT_TIMER1LOAD_AVAILABLE 1 +#define FM4_DT_TIMER1MIS_AVAILABLE 1 +#define FM_DT_TIMER1MIS_AVAILABLE 1 +#define FM4_DT_TIMER1RIS_AVAILABLE 1 +#define FM_DT_TIMER1RIS_AVAILABLE 1 +#define FM4_DT_TIMER1VALUE_AVAILABLE 1 +#define FM_DT_TIMER1VALUE_AVAILABLE 1 +#define FM4_DT_TIMER2BGLOAD_AVAILABLE 1 +#define FM_DT_TIMER2BGLOAD_AVAILABLE 1 +#define FM4_DT_TIMER2CONTROL_AVAILABLE 1 +#define FM_DT_TIMER2CONTROL_AVAILABLE 1 +#define FM4_DT_TIMER2INTCLR_AVAILABLE 1 +#define FM_DT_TIMER2INTCLR_AVAILABLE 1 +#define FM4_DT_TIMER2LOAD_AVAILABLE 1 +#define FM_DT_TIMER2LOAD_AVAILABLE 1 +#define FM4_DT_TIMER2MIS_AVAILABLE 1 +#define FM_DT_TIMER2MIS_AVAILABLE 1 +#define FM4_DT_TIMER2RIS_AVAILABLE 1 +#define FM_DT_TIMER2RIS_AVAILABLE 1 +#define FM4_DT_TIMER2VALUE_AVAILABLE 1 +#define FM_DT_TIMER2VALUE_AVAILABLE 1 +/******************************************************************************* +* DUALFLASH_IF +*******************************************************************************/ +#define FM4_DUALFLASH_IF_DFASZR_AVAILABLE 1 +#define FM_DUALFLASH_IF_DFASZR_AVAILABLE 1 +#define FM4_DUALFLASH_IF_DFRWTR_AVAILABLE 1 +#define FM_DUALFLASH_IF_DFRWTR_AVAILABLE 1 +#define FM4_DUALFLASH_IF_DFSTR_AVAILABLE 1 +#define FM_DUALFLASH_IF_DFSTR_AVAILABLE 1 +/******************************************************************************* +* ECC_CAPTURE +*******************************************************************************/ +#define FM4_ECC_CAPTURE_FERRAD_AVAILABLE 1 +#define FM_ECC_CAPTURE_FERRAD_AVAILABLE 1 +/******************************************************************************* +* EXBUS +*******************************************************************************/ +#define FM4_EXBUS_AMODE_AVAILABLE 1 +#define FM_EXBUS_AMODE_AVAILABLE 1 +#define FM4_EXBUS_AREA0_AVAILABLE 1 +#define FM_EXBUS_AREA0_AVAILABLE 1 +#define FM4_EXBUS_AREA1_AVAILABLE 1 +#define FM_EXBUS_AREA1_AVAILABLE 1 +#define FM4_EXBUS_AREA2_AVAILABLE 1 +#define FM_EXBUS_AREA2_AVAILABLE 1 +#define FM4_EXBUS_AREA3_AVAILABLE 1 +#define FM_EXBUS_AREA3_AVAILABLE 1 +#define FM4_EXBUS_AREA4_AVAILABLE 1 +#define FM_EXBUS_AREA4_AVAILABLE 1 +#define FM4_EXBUS_AREA5_AVAILABLE 1 +#define FM_EXBUS_AREA5_AVAILABLE 1 +#define FM4_EXBUS_AREA6_AVAILABLE 1 +#define FM_EXBUS_AREA6_AVAILABLE 1 +#define FM4_EXBUS_AREA7_AVAILABLE 1 +#define FM_EXBUS_AREA7_AVAILABLE 1 +#define FM4_EXBUS_ATIM0_AVAILABLE 1 +#define FM_EXBUS_ATIM0_AVAILABLE 1 +#define FM4_EXBUS_ATIM1_AVAILABLE 1 +#define FM_EXBUS_ATIM1_AVAILABLE 1 +#define FM4_EXBUS_ATIM2_AVAILABLE 1 +#define FM_EXBUS_ATIM2_AVAILABLE 1 +#define FM4_EXBUS_ATIM3_AVAILABLE 1 +#define FM_EXBUS_ATIM3_AVAILABLE 1 +#define FM4_EXBUS_ATIM4_AVAILABLE 1 +#define FM_EXBUS_ATIM4_AVAILABLE 1 +#define FM4_EXBUS_ATIM5_AVAILABLE 1 +#define FM_EXBUS_ATIM5_AVAILABLE 1 +#define FM4_EXBUS_ATIM6_AVAILABLE 1 +#define FM_EXBUS_ATIM6_AVAILABLE 1 +#define FM4_EXBUS_ATIM7_AVAILABLE 1 +#define FM_EXBUS_ATIM7_AVAILABLE 1 +#define FM4_EXBUS_DCLKR_AVAILABLE 1 +#define FM_EXBUS_DCLKR_AVAILABLE 1 +#define FM4_EXBUS_ESCLR_AVAILABLE 1 +#define FM_EXBUS_ESCLR_AVAILABLE 1 +#define FM4_EXBUS_EST_AVAILABLE 1 +#define FM_EXBUS_EST_AVAILABLE 1 +#define FM4_EXBUS_MEMCERR_AVAILABLE 1 +#define FM_EXBUS_MEMCERR_AVAILABLE 1 +#define FM4_EXBUS_MODE0_AVAILABLE 1 +#define FM_EXBUS_MODE0_AVAILABLE 1 +#define FM4_EXBUS_MODE1_AVAILABLE 1 +#define FM_EXBUS_MODE1_AVAILABLE 1 +#define FM4_EXBUS_MODE2_AVAILABLE 1 +#define FM_EXBUS_MODE2_AVAILABLE 1 +#define FM4_EXBUS_MODE3_AVAILABLE 1 +#define FM_EXBUS_MODE3_AVAILABLE 1 +#define FM4_EXBUS_MODE4_AVAILABLE 1 +#define FM_EXBUS_MODE4_AVAILABLE 1 +#define FM4_EXBUS_MODE5_AVAILABLE 1 +#define FM_EXBUS_MODE5_AVAILABLE 1 +#define FM4_EXBUS_MODE6_AVAILABLE 1 +#define FM_EXBUS_MODE6_AVAILABLE 1 +#define FM4_EXBUS_MODE7_AVAILABLE 1 +#define FM_EXBUS_MODE7_AVAILABLE 1 +#define FM4_EXBUS_PWRDWN_AVAILABLE 1 +#define FM_EXBUS_PWRDWN_AVAILABLE 1 +#define FM4_EXBUS_REFTIM_AVAILABLE 1 +#define FM_EXBUS_REFTIM_AVAILABLE 1 +#define FM4_EXBUS_SDCMD_AVAILABLE 1 +#define FM_EXBUS_SDCMD_AVAILABLE 1 +#define FM4_EXBUS_SDMODE_AVAILABLE 1 +#define FM_EXBUS_SDMODE_AVAILABLE 1 +#define FM4_EXBUS_SDTIM_AVAILABLE 1 +#define FM_EXBUS_SDTIM_AVAILABLE 1 +#define FM4_EXBUS_TIM0_AVAILABLE 1 +#define FM_EXBUS_TIM0_AVAILABLE 1 +#define FM4_EXBUS_TIM1_AVAILABLE 1 +#define FM_EXBUS_TIM1_AVAILABLE 1 +#define FM4_EXBUS_TIM2_AVAILABLE 1 +#define FM_EXBUS_TIM2_AVAILABLE 1 +#define FM4_EXBUS_TIM3_AVAILABLE 1 +#define FM_EXBUS_TIM3_AVAILABLE 1 +#define FM4_EXBUS_TIM4_AVAILABLE 1 +#define FM_EXBUS_TIM4_AVAILABLE 1 +#define FM4_EXBUS_TIM5_AVAILABLE 1 +#define FM_EXBUS_TIM5_AVAILABLE 1 +#define FM4_EXBUS_TIM6_AVAILABLE 1 +#define FM_EXBUS_TIM6_AVAILABLE 1 +#define FM4_EXBUS_TIM7_AVAILABLE 1 +#define FM_EXBUS_TIM7_AVAILABLE 1 +#define FM4_EXBUS_WEAD_AVAILABLE 1 +#define FM_EXBUS_WEAD_AVAILABLE 1 +/******************************************************************************* +* EXTI +*******************************************************************************/ +#define FM4_EXTI_EICL_AVAILABLE 1 +#define FM_EXTI_EICL_AVAILABLE 1 +#define FM4_EXTI_EIRR_AVAILABLE 1 +#define FM_EXTI_EIRR_AVAILABLE 1 +#define FM4_EXTI_ELVR_AVAILABLE 1 +#define FM_EXTI_ELVR_AVAILABLE 1 +#define FM4_EXTI_ELVR1_AVAILABLE 1 +#define FM_EXTI_ELVR1_AVAILABLE 1 +#define FM4_EXTI_ENIR_AVAILABLE 1 +#define FM_EXTI_ENIR_AVAILABLE 1 +#define FM4_EXTI_NMICL_AVAILABLE 1 +#define FM_EXTI_NMICL_AVAILABLE 1 +#define FM4_EXTI_NMIRR_AVAILABLE 1 +#define FM_EXTI_NMIRR_AVAILABLE 1 +/******************************************************************************* +* FLASH_IF +*******************************************************************************/ +#define FM4_FLASH_IF_CRTRMM_AVAILABLE 1 +#define FM_FLASH_IF_CRTRMM_AVAILABLE 1 +#define FM4_FLASH_IF_DFCTRLR_AVAILABLE 1 +#define FM_FLASH_IF_DFCTRLR_AVAILABLE 1 +#define FM4_FLASH_IF_FASZR_AVAILABLE 1 +#define FM_FLASH_IF_FASZR_AVAILABLE 1 +#define FM4_FLASH_IF_FBFCR_AVAILABLE 1 +#define FM_FLASH_IF_FBFCR_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM1_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM1_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM2_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM2_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM3_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM3_AVAILABLE 1 +#define FM4_FLASH_IF_FGPDM4_AVAILABLE 1 +#define FM_FLASH_IF_FGPDM4_AVAILABLE 1 +#define FM4_FLASH_IF_FICLR_AVAILABLE 1 +#define FM_FLASH_IF_FICLR_AVAILABLE 1 +#define FM4_FLASH_IF_FICR_AVAILABLE 1 +#define FM_FLASH_IF_FICR_AVAILABLE 1 +#define FM4_FLASH_IF_FISR_AVAILABLE 1 +#define FM_FLASH_IF_FISR_AVAILABLE 1 +#define FM4_FLASH_IF_FRWTR_AVAILABLE 1 +#define FM_FLASH_IF_FRWTR_AVAILABLE 1 +#define FM4_FLASH_IF_FSTR_AVAILABLE 1 +#define FM_FLASH_IF_FSTR_AVAILABLE 1 +#define FM4_FLASH_IF_FSYNDN_AVAILABLE 1 +#define FM_FLASH_IF_FSYNDN_AVAILABLE 1 +/******************************************************************************* +* GPIO +*******************************************************************************/ +#define FM4_GPIO_ADE_AVAILABLE 1 +#define FM_GPIO_ADE_AVAILABLE 1 +#define FM4_GPIO_DDR0_AVAILABLE 1 +#define FM_GPIO_DDR0_AVAILABLE 1 +#define FM4_GPIO_DDR1_AVAILABLE 1 +#define FM_GPIO_DDR1_AVAILABLE 1 +#define FM4_GPIO_DDR2_AVAILABLE 1 +#define FM_GPIO_DDR2_AVAILABLE 1 +#define FM4_GPIO_DDR3_AVAILABLE 1 +#define FM_GPIO_DDR3_AVAILABLE 1 +#define FM4_GPIO_DDR4_AVAILABLE 1 +#define FM_GPIO_DDR4_AVAILABLE 1 +#define FM4_GPIO_DDR5_AVAILABLE 1 +#define FM_GPIO_DDR5_AVAILABLE 1 +#define FM4_GPIO_DDR6_AVAILABLE 1 +#define FM_GPIO_DDR6_AVAILABLE 1 +#define FM4_GPIO_DDR7_AVAILABLE 1 +#define FM_GPIO_DDR7_AVAILABLE 1 +#define FM4_GPIO_DDR8_AVAILABLE 1 +#define FM_GPIO_DDR8_AVAILABLE 1 +#define FM4_GPIO_DDR9_AVAILABLE 1 +#define FM_GPIO_DDR9_AVAILABLE 1 +#define FM4_GPIO_DDRA_AVAILABLE 1 +#define FM_GPIO_DDRA_AVAILABLE 1 +#define FM4_GPIO_DDRB_AVAILABLE 1 +#define FM_GPIO_DDRB_AVAILABLE 1 +#define FM4_GPIO_DDRC_AVAILABLE 1 +#define FM_GPIO_DDRC_AVAILABLE 1 +#define FM4_GPIO_DDRD_AVAILABLE 1 +#define FM_GPIO_DDRD_AVAILABLE 1 +#define FM4_GPIO_DDRE_AVAILABLE 1 +#define FM_GPIO_DDRE_AVAILABLE 1 +#define FM4_GPIO_DDRF_AVAILABLE 1 +#define FM_GPIO_DDRF_AVAILABLE 1 +#define FM4_GPIO_EPFR00_AVAILABLE 1 +#define FM_GPIO_EPFR00_AVAILABLE 1 +#define FM4_GPIO_EPFR01_AVAILABLE 1 +#define FM_GPIO_EPFR01_AVAILABLE 1 +#define FM4_GPIO_EPFR02_AVAILABLE 1 +#define FM_GPIO_EPFR02_AVAILABLE 1 +#define FM4_GPIO_EPFR03_AVAILABLE 1 +#define FM_GPIO_EPFR03_AVAILABLE 1 +#define FM4_GPIO_EPFR04_AVAILABLE 1 +#define FM_GPIO_EPFR04_AVAILABLE 1 +#define FM4_GPIO_EPFR05_AVAILABLE 1 +#define FM_GPIO_EPFR05_AVAILABLE 1 +#define FM4_GPIO_EPFR06_AVAILABLE 1 +#define FM_GPIO_EPFR06_AVAILABLE 1 +#define FM4_GPIO_EPFR07_AVAILABLE 1 +#define FM_GPIO_EPFR07_AVAILABLE 1 +#define FM4_GPIO_EPFR08_AVAILABLE 1 +#define FM_GPIO_EPFR08_AVAILABLE 1 +#define FM4_GPIO_EPFR09_AVAILABLE 1 +#define FM_GPIO_EPFR09_AVAILABLE 1 +#define FM4_GPIO_EPFR10_AVAILABLE 1 +#define FM_GPIO_EPFR10_AVAILABLE 1 +#define FM4_GPIO_EPFR11_AVAILABLE 1 +#define FM_GPIO_EPFR11_AVAILABLE 1 +#define FM4_GPIO_EPFR12_AVAILABLE 1 +#define FM_GPIO_EPFR12_AVAILABLE 1 +#define FM4_GPIO_EPFR13_AVAILABLE 1 +#define FM_GPIO_EPFR13_AVAILABLE 1 +#define FM4_GPIO_EPFR14_AVAILABLE 1 +#define FM_GPIO_EPFR14_AVAILABLE 1 +#define FM4_GPIO_EPFR15_AVAILABLE 1 +#define FM_GPIO_EPFR15_AVAILABLE 1 +#define FM4_GPIO_EPFR16_AVAILABLE 1 +#define FM_GPIO_EPFR16_AVAILABLE 1 +#define FM4_GPIO_EPFR17_AVAILABLE 1 +#define FM_GPIO_EPFR17_AVAILABLE 1 +#define FM4_GPIO_EPFR18_AVAILABLE 1 +#define FM_GPIO_EPFR18_AVAILABLE 1 +#define FM4_GPIO_EPFR19_AVAILABLE 1 +#define FM_GPIO_EPFR19_AVAILABLE 1 +#define FM4_GPIO_EPFR20_AVAILABLE 1 +#define FM_GPIO_EPFR20_AVAILABLE 1 +#define FM4_GPIO_EPFR21_AVAILABLE 1 +#define FM_GPIO_EPFR21_AVAILABLE 1 +#define FM4_GPIO_EPFR22_AVAILABLE 1 +#define FM_GPIO_EPFR22_AVAILABLE 1 +#define FM4_GPIO_EPFR23_AVAILABLE 1 +#define FM_GPIO_EPFR23_AVAILABLE 1 +#define FM4_GPIO_EPFR24_AVAILABLE 1 +#define FM_GPIO_EPFR24_AVAILABLE 1 +#define FM4_GPIO_EPFR25_AVAILABLE 1 +#define FM_GPIO_EPFR25_AVAILABLE 1 +#define FM4_GPIO_EPFR26_AVAILABLE 1 +#define FM_GPIO_EPFR26_AVAILABLE 1 +#define FM4_GPIO_PCR0_AVAILABLE 1 +#define FM_GPIO_PCR0_AVAILABLE 1 +#define FM4_GPIO_PCR1_AVAILABLE 1 +#define FM_GPIO_PCR1_AVAILABLE 1 +#define FM4_GPIO_PCR2_AVAILABLE 1 +#define FM_GPIO_PCR2_AVAILABLE 1 +#define FM4_GPIO_PCR3_AVAILABLE 1 +#define FM_GPIO_PCR3_AVAILABLE 1 +#define FM4_GPIO_PCR4_AVAILABLE 1 +#define FM_GPIO_PCR4_AVAILABLE 1 +#define FM4_GPIO_PCR5_AVAILABLE 1 +#define FM_GPIO_PCR5_AVAILABLE 1 +#define FM4_GPIO_PCR6_AVAILABLE 1 +#define FM_GPIO_PCR6_AVAILABLE 1 +#define FM4_GPIO_PCR7_AVAILABLE 1 +#define FM_GPIO_PCR7_AVAILABLE 1 +#define FM4_GPIO_PCR9_AVAILABLE 1 +#define FM_GPIO_PCR9_AVAILABLE 1 +#define FM4_GPIO_PCRA_AVAILABLE 1 +#define FM_GPIO_PCRA_AVAILABLE 1 +#define FM4_GPIO_PCRB_AVAILABLE 1 +#define FM_GPIO_PCRB_AVAILABLE 1 +#define FM4_GPIO_PCRC_AVAILABLE 1 +#define FM_GPIO_PCRC_AVAILABLE 1 +#define FM4_GPIO_PCRD_AVAILABLE 1 +#define FM_GPIO_PCRD_AVAILABLE 1 +#define FM4_GPIO_PCRE_AVAILABLE 1 +#define FM_GPIO_PCRE_AVAILABLE 1 +#define FM4_GPIO_PCRF_AVAILABLE 1 +#define FM_GPIO_PCRF_AVAILABLE 1 +#define FM4_GPIO_PDIR0_AVAILABLE 1 +#define FM_GPIO_PDIR0_AVAILABLE 1 +#define FM4_GPIO_PDIR1_AVAILABLE 1 +#define FM_GPIO_PDIR1_AVAILABLE 1 +#define FM4_GPIO_PDIR2_AVAILABLE 1 +#define FM_GPIO_PDIR2_AVAILABLE 1 +#define FM4_GPIO_PDIR3_AVAILABLE 1 +#define FM_GPIO_PDIR3_AVAILABLE 1 +#define FM4_GPIO_PDIR4_AVAILABLE 1 +#define FM_GPIO_PDIR4_AVAILABLE 1 +#define FM4_GPIO_PDIR5_AVAILABLE 1 +#define FM_GPIO_PDIR5_AVAILABLE 1 +#define FM4_GPIO_PDIR6_AVAILABLE 1 +#define FM_GPIO_PDIR6_AVAILABLE 1 +#define FM4_GPIO_PDIR7_AVAILABLE 1 +#define FM_GPIO_PDIR7_AVAILABLE 1 +#define FM4_GPIO_PDIR8_AVAILABLE 1 +#define FM_GPIO_PDIR8_AVAILABLE 1 +#define FM4_GPIO_PDIR9_AVAILABLE 1 +#define FM_GPIO_PDIR9_AVAILABLE 1 +#define FM4_GPIO_PDIRA_AVAILABLE 1 +#define FM_GPIO_PDIRA_AVAILABLE 1 +#define FM4_GPIO_PDIRB_AVAILABLE 1 +#define FM_GPIO_PDIRB_AVAILABLE 1 +#define FM4_GPIO_PDIRC_AVAILABLE 1 +#define FM_GPIO_PDIRC_AVAILABLE 1 +#define FM4_GPIO_PDIRD_AVAILABLE 1 +#define FM_GPIO_PDIRD_AVAILABLE 1 +#define FM4_GPIO_PDIRE_AVAILABLE 1 +#define FM_GPIO_PDIRE_AVAILABLE 1 +#define FM4_GPIO_PDIRF_AVAILABLE 1 +#define FM_GPIO_PDIRF_AVAILABLE 1 +#define FM4_GPIO_PDOR0_AVAILABLE 1 +#define FM_GPIO_PDOR0_AVAILABLE 1 +#define FM4_GPIO_PDOR1_AVAILABLE 1 +#define FM_GPIO_PDOR1_AVAILABLE 1 +#define FM4_GPIO_PDOR2_AVAILABLE 1 +#define FM_GPIO_PDOR2_AVAILABLE 1 +#define FM4_GPIO_PDOR3_AVAILABLE 1 +#define FM_GPIO_PDOR3_AVAILABLE 1 +#define FM4_GPIO_PDOR4_AVAILABLE 1 +#define FM_GPIO_PDOR4_AVAILABLE 1 +#define FM4_GPIO_PDOR5_AVAILABLE 1 +#define FM_GPIO_PDOR5_AVAILABLE 1 +#define FM4_GPIO_PDOR6_AVAILABLE 1 +#define FM_GPIO_PDOR6_AVAILABLE 1 +#define FM4_GPIO_PDOR7_AVAILABLE 1 +#define FM_GPIO_PDOR7_AVAILABLE 1 +#define FM4_GPIO_PDOR8_AVAILABLE 1 +#define FM_GPIO_PDOR8_AVAILABLE 1 +#define FM4_GPIO_PDOR9_AVAILABLE 1 +#define FM_GPIO_PDOR9_AVAILABLE 1 +#define FM4_GPIO_PDORA_AVAILABLE 1 +#define FM_GPIO_PDORA_AVAILABLE 1 +#define FM4_GPIO_PDORB_AVAILABLE 1 +#define FM_GPIO_PDORB_AVAILABLE 1 +#define FM4_GPIO_PDORC_AVAILABLE 1 +#define FM_GPIO_PDORC_AVAILABLE 1 +#define FM4_GPIO_PDORD_AVAILABLE 1 +#define FM_GPIO_PDORD_AVAILABLE 1 +#define FM4_GPIO_PDORE_AVAILABLE 1 +#define FM_GPIO_PDORE_AVAILABLE 1 +#define FM4_GPIO_PDORF_AVAILABLE 1 +#define FM_GPIO_PDORF_AVAILABLE 1 +#define FM4_GPIO_PDSR0_AVAILABLE 1 +#define FM_GPIO_PDSR0_AVAILABLE 1 +#define FM4_GPIO_PDSR1_AVAILABLE 1 +#define FM_GPIO_PDSR1_AVAILABLE 1 +#define FM4_GPIO_PDSR2_AVAILABLE 1 +#define FM_GPIO_PDSR2_AVAILABLE 1 +#define FM4_GPIO_PDSR3_AVAILABLE 1 +#define FM_GPIO_PDSR3_AVAILABLE 1 +#define FM4_GPIO_PDSR4_AVAILABLE 1 +#define FM_GPIO_PDSR4_AVAILABLE 1 +#define FM4_GPIO_PDSR5_AVAILABLE 1 +#define FM_GPIO_PDSR5_AVAILABLE 1 +#define FM4_GPIO_PDSR6_AVAILABLE 1 +#define FM_GPIO_PDSR6_AVAILABLE 1 +#define FM4_GPIO_PDSR7_AVAILABLE 1 +#define FM_GPIO_PDSR7_AVAILABLE 1 +#define FM4_GPIO_PDSR8_AVAILABLE 1 +#define FM_GPIO_PDSR8_AVAILABLE 1 +#define FM4_GPIO_PDSR9_AVAILABLE 1 +#define FM_GPIO_PDSR9_AVAILABLE 1 +#define FM4_GPIO_PDSRA_AVAILABLE 1 +#define FM_GPIO_PDSRA_AVAILABLE 1 +#define FM4_GPIO_PDSRB_AVAILABLE 1 +#define FM_GPIO_PDSRB_AVAILABLE 1 +#define FM4_GPIO_PDSRC_AVAILABLE 1 +#define FM_GPIO_PDSRC_AVAILABLE 1 +#define FM4_GPIO_PDSRD_AVAILABLE 1 +#define FM_GPIO_PDSRD_AVAILABLE 1 +#define FM4_GPIO_PDSRE_AVAILABLE 1 +#define FM_GPIO_PDSRE_AVAILABLE 1 +#define FM4_GPIO_PDSRF_AVAILABLE 1 +#define FM_GPIO_PDSRF_AVAILABLE 1 +#define FM4_GPIO_PFR0_AVAILABLE 1 +#define FM_GPIO_PFR0_AVAILABLE 1 +#define FM4_GPIO_PFR1_AVAILABLE 1 +#define FM_GPIO_PFR1_AVAILABLE 1 +#define FM4_GPIO_PFR2_AVAILABLE 1 +#define FM_GPIO_PFR2_AVAILABLE 1 +#define FM4_GPIO_PFR3_AVAILABLE 1 +#define FM_GPIO_PFR3_AVAILABLE 1 +#define FM4_GPIO_PFR4_AVAILABLE 1 +#define FM_GPIO_PFR4_AVAILABLE 1 +#define FM4_GPIO_PFR5_AVAILABLE 1 +#define FM_GPIO_PFR5_AVAILABLE 1 +#define FM4_GPIO_PFR6_AVAILABLE 1 +#define FM_GPIO_PFR6_AVAILABLE 1 +#define FM4_GPIO_PFR7_AVAILABLE 1 +#define FM_GPIO_PFR7_AVAILABLE 1 +#define FM4_GPIO_PFR8_AVAILABLE 1 +#define FM_GPIO_PFR8_AVAILABLE 1 +#define FM4_GPIO_PFR9_AVAILABLE 1 +#define FM_GPIO_PFR9_AVAILABLE 1 +#define FM4_GPIO_PFRA_AVAILABLE 1 +#define FM_GPIO_PFRA_AVAILABLE 1 +#define FM4_GPIO_PFRB_AVAILABLE 1 +#define FM_GPIO_PFRB_AVAILABLE 1 +#define FM4_GPIO_PFRC_AVAILABLE 1 +#define FM_GPIO_PFRC_AVAILABLE 1 +#define FM4_GPIO_PFRD_AVAILABLE 1 +#define FM_GPIO_PFRD_AVAILABLE 1 +#define FM4_GPIO_PFRE_AVAILABLE 1 +#define FM_GPIO_PFRE_AVAILABLE 1 +#define FM4_GPIO_PFRF_AVAILABLE 1 +#define FM_GPIO_PFRF_AVAILABLE 1 +#define FM4_GPIO_PZR0_AVAILABLE 1 +#define FM_GPIO_PZR0_AVAILABLE 1 +#define FM4_GPIO_PZR1_AVAILABLE 1 +#define FM_GPIO_PZR1_AVAILABLE 1 +#define FM4_GPIO_PZR2_AVAILABLE 1 +#define FM_GPIO_PZR2_AVAILABLE 1 +#define FM4_GPIO_PZR3_AVAILABLE 1 +#define FM_GPIO_PZR3_AVAILABLE 1 +#define FM4_GPIO_PZR4_AVAILABLE 1 +#define FM_GPIO_PZR4_AVAILABLE 1 +#define FM4_GPIO_PZR5_AVAILABLE 1 +#define FM_GPIO_PZR5_AVAILABLE 1 +#define FM4_GPIO_PZR6_AVAILABLE 1 +#define FM_GPIO_PZR6_AVAILABLE 1 +#define FM4_GPIO_PZR7_AVAILABLE 1 +#define FM_GPIO_PZR7_AVAILABLE 1 +#define FM4_GPIO_PZR8_AVAILABLE 1 +#define FM_GPIO_PZR8_AVAILABLE 1 +#define FM4_GPIO_PZR9_AVAILABLE 1 +#define FM_GPIO_PZR9_AVAILABLE 1 +#define FM4_GPIO_PZRA_AVAILABLE 1 +#define FM_GPIO_PZRA_AVAILABLE 1 +#define FM4_GPIO_PZRB_AVAILABLE 1 +#define FM_GPIO_PZRB_AVAILABLE 1 +#define FM4_GPIO_PZRC_AVAILABLE 1 +#define FM_GPIO_PZRC_AVAILABLE 1 +#define FM4_GPIO_PZRD_AVAILABLE 1 +#define FM_GPIO_PZRD_AVAILABLE 1 +#define FM4_GPIO_PZRE_AVAILABLE 1 +#define FM_GPIO_PZRE_AVAILABLE 1 +#define FM4_GPIO_PZRF_AVAILABLE 1 +#define FM_GPIO_PZRF_AVAILABLE 1 +#define FM4_GPIO_SPSR_AVAILABLE 1 +#define FM_GPIO_SPSR_AVAILABLE 1 +/******************************************************************************* +* HSSPI +*******************************************************************************/ +#define FM4_HSSPI_CSAEXT_AVAILABLE 1 +#define FM_HSSPI_CSAEXT_AVAILABLE 1 +#define FM4_HSSPI_CSCFG_AVAILABLE 1 +#define FM_HSSPI_CSCFG_AVAILABLE 1 +#define FM4_HSSPI_CSITIME_AVAILABLE 1 +#define FM_HSSPI_CSITIME_AVAILABLE 1 +#define FM4_HSSPI_DBCNT_AVAILABLE 1 +#define FM_HSSPI_DBCNT_AVAILABLE 1 +#define FM4_HSSPI_DMBCC_AVAILABLE 1 +#define FM_HSSPI_DMBCC_AVAILABLE 1 +#define FM4_HSSPI_DMBCS_AVAILABLE 1 +#define FM_HSSPI_DMBCS_AVAILABLE 1 +#define FM4_HSSPI_DMCFG_AVAILABLE 1 +#define FM_HSSPI_DMCFG_AVAILABLE 1 +#define FM4_HSSPI_DMDMAEN_AVAILABLE 1 +#define FM_HSSPI_DMDMAEN_AVAILABLE 1 +#define FM4_HSSPI_DMPSEL_AVAILABLE 1 +#define FM_HSSPI_DMPSEL_AVAILABLE 1 +#define FM4_HSSPI_DMSTART_AVAILABLE 1 +#define FM_HSSPI_DMSTART_AVAILABLE 1 +#define FM4_HSSPI_DMSTATUS_AVAILABLE 1 +#define FM_HSSPI_DMSTATUS_AVAILABLE 1 +#define FM4_HSSPI_DMSTOP_AVAILABLE 1 +#define FM_HSSPI_DMSTOP_AVAILABLE 1 +#define FM4_HSSPI_DMTRP_AVAILABLE 1 +#define FM_HSSPI_DMTRP_AVAILABLE 1 +#define FM4_HSSPI_FAULTC_AVAILABLE 1 +#define FM_HSSPI_FAULTC_AVAILABLE 1 +#define FM4_HSSPI_FAULTF_AVAILABLE 1 +#define FM_HSSPI_FAULTF_AVAILABLE 1 +#define FM4_HSSPI_FIFOCFG_AVAILABLE 1 +#define FM_HSSPI_FIFOCFG_AVAILABLE 1 +#define FM4_HSSPI_MCTRL_AVAILABLE 1 +#define FM_HSSPI_MCTRL_AVAILABLE 1 +#define FM4_HSSPI_MID_AVAILABLE 1 +#define FM_HSSPI_MID_AVAILABLE 1 +#define FM4_HSSPI_PCC0_AVAILABLE 1 +#define FM_HSSPI_PCC0_AVAILABLE 1 +#define FM4_HSSPI_PCC1_AVAILABLE 1 +#define FM_HSSPI_PCC1_AVAILABLE 1 +#define FM4_HSSPI_PCC2_AVAILABLE 1 +#define FM_HSSPI_PCC2_AVAILABLE 1 +#define FM4_HSSPI_PCC3_AVAILABLE 1 +#define FM_HSSPI_PCC3_AVAILABLE 1 +#define FM4_HSSPI_QDCLKR_AVAILABLE 1 +#define FM_HSSPI_QDCLKR_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC0_AVAILABLE 1 +#define FM_HSSPI_RDCSDC0_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC1_AVAILABLE 1 +#define FM_HSSPI_RDCSDC1_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC2_AVAILABLE 1 +#define FM_HSSPI_RDCSDC2_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC3_AVAILABLE 1 +#define FM_HSSPI_RDCSDC3_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC4_AVAILABLE 1 +#define FM_HSSPI_RDCSDC4_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC5_AVAILABLE 1 +#define FM_HSSPI_RDCSDC5_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC6_AVAILABLE 1 +#define FM_HSSPI_RDCSDC6_AVAILABLE 1 +#define FM4_HSSPI_RDCSDC7_AVAILABLE 1 +#define FM_HSSPI_RDCSDC7_AVAILABLE 1 +#define FM4_HSSPI_RXC_AVAILABLE 1 +#define FM_HSSPI_RXC_AVAILABLE 1 +#define FM4_HSSPI_RXE_AVAILABLE 1 +#define FM_HSSPI_RXE_AVAILABLE 1 +#define FM4_HSSPI_RXF_AVAILABLE 1 +#define FM_HSSPI_RXF_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO0_AVAILABLE 1 +#define FM_HSSPI_RXFIFO0_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO1_AVAILABLE 1 +#define FM_HSSPI_RXFIFO1_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO10_AVAILABLE 1 +#define FM_HSSPI_RXFIFO10_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO11_AVAILABLE 1 +#define FM_HSSPI_RXFIFO11_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO12_AVAILABLE 1 +#define FM_HSSPI_RXFIFO12_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO13_AVAILABLE 1 +#define FM_HSSPI_RXFIFO13_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO14_AVAILABLE 1 +#define FM_HSSPI_RXFIFO14_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO15_AVAILABLE 1 +#define FM_HSSPI_RXFIFO15_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO2_AVAILABLE 1 +#define FM_HSSPI_RXFIFO2_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO3_AVAILABLE 1 +#define FM_HSSPI_RXFIFO3_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO4_AVAILABLE 1 +#define FM_HSSPI_RXFIFO4_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO5_AVAILABLE 1 +#define FM_HSSPI_RXFIFO5_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO6_AVAILABLE 1 +#define FM_HSSPI_RXFIFO6_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO7_AVAILABLE 1 +#define FM_HSSPI_RXFIFO7_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO8_AVAILABLE 1 +#define FM_HSSPI_RXFIFO8_AVAILABLE 1 +#define FM4_HSSPI_RXFIFO9_AVAILABLE 1 +#define FM_HSSPI_RXFIFO9_AVAILABLE 1 +#define FM4_HSSPI_TXC_AVAILABLE 1 +#define FM_HSSPI_TXC_AVAILABLE 1 +#define FM4_HSSPI_TXE_AVAILABLE 1 +#define FM_HSSPI_TXE_AVAILABLE 1 +#define FM4_HSSPI_TXF_AVAILABLE 1 +#define FM_HSSPI_TXF_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO0_AVAILABLE 1 +#define FM_HSSPI_TXFIFO0_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO1_AVAILABLE 1 +#define FM_HSSPI_TXFIFO1_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO10_AVAILABLE 1 +#define FM_HSSPI_TXFIFO10_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO11_AVAILABLE 1 +#define FM_HSSPI_TXFIFO11_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO12_AVAILABLE 1 +#define FM_HSSPI_TXFIFO12_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO13_AVAILABLE 1 +#define FM_HSSPI_TXFIFO13_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO14_AVAILABLE 1 +#define FM_HSSPI_TXFIFO14_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO15_AVAILABLE 1 +#define FM_HSSPI_TXFIFO15_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO2_AVAILABLE 1 +#define FM_HSSPI_TXFIFO2_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO3_AVAILABLE 1 +#define FM_HSSPI_TXFIFO3_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO4_AVAILABLE 1 +#define FM_HSSPI_TXFIFO4_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO5_AVAILABLE 1 +#define FM_HSSPI_TXFIFO5_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO6_AVAILABLE 1 +#define FM_HSSPI_TXFIFO6_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO7_AVAILABLE 1 +#define FM_HSSPI_TXFIFO7_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO8_AVAILABLE 1 +#define FM_HSSPI_TXFIFO8_AVAILABLE 1 +#define FM4_HSSPI_TXFIFO9_AVAILABLE 1 +#define FM_HSSPI_TXFIFO9_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC0_AVAILABLE 1 +#define FM_HSSPI_WRCSDC0_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC1_AVAILABLE 1 +#define FM_HSSPI_WRCSDC1_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC2_AVAILABLE 1 +#define FM_HSSPI_WRCSDC2_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC3_AVAILABLE 1 +#define FM_HSSPI_WRCSDC3_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC4_AVAILABLE 1 +#define FM_HSSPI_WRCSDC4_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC5_AVAILABLE 1 +#define FM_HSSPI_WRCSDC5_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC6_AVAILABLE 1 +#define FM_HSSPI_WRCSDC6_AVAILABLE 1 +#define FM4_HSSPI_WRCSDC7_AVAILABLE 1 +#define FM_HSSPI_WRCSDC7_AVAILABLE 1 +/******************************************************************************* +* HWWDT +*******************************************************************************/ +#define FM4_HWWDT_WDG_CTL_AVAILABLE 1 +#define FM_HWWDT_WDG_CTL_AVAILABLE 1 +#define FM4_HWWDT_WDG_ICL_AVAILABLE 1 +#define FM_HWWDT_WDG_ICL_AVAILABLE 1 +#define FM4_HWWDT_WDG_LCK_AVAILABLE 1 +#define FM_HWWDT_WDG_LCK_AVAILABLE 1 +#define FM4_HWWDT_WDG_LDR_AVAILABLE 1 +#define FM_HWWDT_WDG_LDR_AVAILABLE 1 +#define FM4_HWWDT_WDG_RIS_AVAILABLE 1 +#define FM_HWWDT_WDG_RIS_AVAILABLE 1 +#define FM4_HWWDT_WDG_VLR_AVAILABLE 1 +#define FM_HWWDT_WDG_VLR_AVAILABLE 1 +/******************************************************************************* +* I2S0 +*******************************************************************************/ +#define FM4_I2S_CNTREG_AVAILABLE 1 +#define FM_I2S_CNTREG_AVAILABLE 1 +#define FM4_I2S_DMAACT_AVAILABLE 1 +#define FM_I2S_DMAACT_AVAILABLE 1 +#define FM4_I2S_INTCNT_AVAILABLE 1 +#define FM_I2S_INTCNT_AVAILABLE 1 +#define FM4_I2S_MCR0REG_AVAILABLE 1 +#define FM_I2S_MCR0REG_AVAILABLE 1 +#define FM4_I2S_MCR1REG_AVAILABLE 1 +#define FM_I2S_MCR1REG_AVAILABLE 1 +#define FM4_I2S_MCR2REG_AVAILABLE 1 +#define FM_I2S_MCR2REG_AVAILABLE 1 +#define FM4_I2S_OPRREG_AVAILABLE 1 +#define FM_I2S_OPRREG_AVAILABLE 1 +#define FM4_I2S_RXFDAT_AVAILABLE 1 +#define FM_I2S_RXFDAT_AVAILABLE 1 +#define FM4_I2S_SRST_AVAILABLE 1 +#define FM_I2S_SRST_AVAILABLE 1 +#define FM4_I2S_STATUS_AVAILABLE 1 +#define FM_I2S_STATUS_AVAILABLE 1 +#define FM4_I2S_TSTREG_AVAILABLE 1 +#define FM_I2S_TSTREG_AVAILABLE 1 +#define FM4_I2S_TXFDAT_AVAILABLE 1 +#define FM_I2S_TXFDAT_AVAILABLE 1 +/******************************************************************************* +* I2SPRE +*******************************************************************************/ +#define FM4_I2SPRE_ICCR_AVAILABLE 1 +#define FM_I2SPRE_ICCR_AVAILABLE 1 +#define FM4_I2SPRE_IP_STR_AVAILABLE 1 +#define FM_I2SPRE_IP_STR_AVAILABLE 1 +#define FM4_I2SPRE_IPCR1_AVAILABLE 1 +#define FM_I2SPRE_IPCR1_AVAILABLE 1 +#define FM4_I2SPRE_IPCR2_AVAILABLE 1 +#define FM_I2SPRE_IPCR2_AVAILABLE 1 +#define FM4_I2SPRE_IPCR3_AVAILABLE 1 +#define FM_I2SPRE_IPCR3_AVAILABLE 1 +#define FM4_I2SPRE_IPCR4_AVAILABLE 1 +#define FM_I2SPRE_IPCR4_AVAILABLE 1 +#define FM4_I2SPRE_IPCR5_AVAILABLE 1 +#define FM_I2SPRE_IPCR5_AVAILABLE 1 +#define FM4_I2SPRE_IPINT_CLR_AVAILABLE 1 +#define FM_I2SPRE_IPINT_CLR_AVAILABLE 1 +#define FM4_I2SPRE_IPINT_ENR_AVAILABLE 1 +#define FM_I2SPRE_IPINT_ENR_AVAILABLE 1 +#define FM4_I2SPRE_IPINT_STR_AVAILABLE 1 +#define FM_I2SPRE_IPINT_STR_AVAILABLE 1 +/******************************************************************************* +* INTREQ +*******************************************************************************/ +#define FM4_INTREQ_DRQSEL_AVAILABLE 1 +#define FM_INTREQ_DRQSEL_AVAILABLE 1 +#define FM4_INTREQ_EXC02MON_AVAILABLE 1 +#define FM_INTREQ_EXC02MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ000MON_AVAILABLE 1 +#define FM_INTREQ_IRQ000MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ001MON_AVAILABLE 1 +#define FM_INTREQ_IRQ001MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ002MON_AVAILABLE 1 +#define FM_INTREQ_IRQ002MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ003MON_AVAILABLE 1 +#define FM_INTREQ_IRQ003MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ003SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ003SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ004MON_AVAILABLE 1 +#define FM_INTREQ_IRQ004MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ004SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ004SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ005MON_AVAILABLE 1 +#define FM_INTREQ_IRQ005MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ005SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ005SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ006MON_AVAILABLE 1 +#define FM_INTREQ_IRQ006MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ006SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ006SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ007MON_AVAILABLE 1 +#define FM_INTREQ_IRQ007MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ007SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ007SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ008MON_AVAILABLE 1 +#define FM_INTREQ_IRQ008MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ008SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ008SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ009MON_AVAILABLE 1 +#define FM_INTREQ_IRQ009MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ009SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ009SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ010MON_AVAILABLE 1 +#define FM_INTREQ_IRQ010MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ010SEL_AVAILABLE 1 +#define FM_INTREQ_IRQ010SEL_AVAILABLE 1 +#define FM4_INTREQ_IRQ011MON_AVAILABLE 1 +#define FM_INTREQ_IRQ011MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ012MON_AVAILABLE 1 +#define FM_INTREQ_IRQ012MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ013MON_AVAILABLE 1 +#define FM_INTREQ_IRQ013MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ014MON_AVAILABLE 1 +#define FM_INTREQ_IRQ014MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ015MON_AVAILABLE 1 +#define FM_INTREQ_IRQ015MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ016MON_AVAILABLE 1 +#define FM_INTREQ_IRQ016MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ017MON_AVAILABLE 1 +#define FM_INTREQ_IRQ017MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ018MON_AVAILABLE 1 +#define FM_INTREQ_IRQ018MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ019MON_AVAILABLE 1 +#define FM_INTREQ_IRQ019MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ020MON_AVAILABLE 1 +#define FM_INTREQ_IRQ020MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ021MON_AVAILABLE 1 +#define FM_INTREQ_IRQ021MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ022MON_AVAILABLE 1 +#define FM_INTREQ_IRQ022MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ023MON_AVAILABLE 1 +#define FM_INTREQ_IRQ023MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ024MON_AVAILABLE 1 +#define FM_INTREQ_IRQ024MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ025MON_AVAILABLE 1 +#define FM_INTREQ_IRQ025MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ026MON_AVAILABLE 1 +#define FM_INTREQ_IRQ026MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ027MON_AVAILABLE 1 +#define FM_INTREQ_IRQ027MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ028MON_AVAILABLE 1 +#define FM_INTREQ_IRQ028MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ029MON_AVAILABLE 1 +#define FM_INTREQ_IRQ029MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ030MON_AVAILABLE 1 +#define FM_INTREQ_IRQ030MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ031MON_AVAILABLE 1 +#define FM_INTREQ_IRQ031MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ032MON_AVAILABLE 1 +#define FM_INTREQ_IRQ032MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ033MON_AVAILABLE 1 +#define FM_INTREQ_IRQ033MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ034MON_AVAILABLE 1 +#define FM_INTREQ_IRQ034MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ035MON_AVAILABLE 1 +#define FM_INTREQ_IRQ035MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ036MON_AVAILABLE 1 +#define FM_INTREQ_IRQ036MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ037MON_AVAILABLE 1 +#define FM_INTREQ_IRQ037MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ038MON_AVAILABLE 1 +#define FM_INTREQ_IRQ038MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ039MON_AVAILABLE 1 +#define FM_INTREQ_IRQ039MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ040MON_AVAILABLE 1 +#define FM_INTREQ_IRQ040MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ041MON_AVAILABLE 1 +#define FM_INTREQ_IRQ041MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ042MON_AVAILABLE 1 +#define FM_INTREQ_IRQ042MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ043MON_AVAILABLE 1 +#define FM_INTREQ_IRQ043MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ044MON_AVAILABLE 1 +#define FM_INTREQ_IRQ044MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ045MON_AVAILABLE 1 +#define FM_INTREQ_IRQ045MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ046MON_AVAILABLE 1 +#define FM_INTREQ_IRQ046MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ047MON_AVAILABLE 1 +#define FM_INTREQ_IRQ047MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ048MON_AVAILABLE 1 +#define FM_INTREQ_IRQ048MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ049MON_AVAILABLE 1 +#define FM_INTREQ_IRQ049MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ050MON_AVAILABLE 1 +#define FM_INTREQ_IRQ050MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ051MON_AVAILABLE 1 +#define FM_INTREQ_IRQ051MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ052MON_AVAILABLE 1 +#define FM_INTREQ_IRQ052MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ053MON_AVAILABLE 1 +#define FM_INTREQ_IRQ053MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ054MON_AVAILABLE 1 +#define FM_INTREQ_IRQ054MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ055MON_AVAILABLE 1 +#define FM_INTREQ_IRQ055MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ056MON_AVAILABLE 1 +#define FM_INTREQ_IRQ056MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ057MON_AVAILABLE 1 +#define FM_INTREQ_IRQ057MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ058MON_AVAILABLE 1 +#define FM_INTREQ_IRQ058MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ059MON_AVAILABLE 1 +#define FM_INTREQ_IRQ059MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ060MON_AVAILABLE 1 +#define FM_INTREQ_IRQ060MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ061MON_AVAILABLE 1 +#define FM_INTREQ_IRQ061MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ062MON_AVAILABLE 1 +#define FM_INTREQ_IRQ062MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ063MON_AVAILABLE 1 +#define FM_INTREQ_IRQ063MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ064MON_AVAILABLE 1 +#define FM_INTREQ_IRQ064MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ065MON_AVAILABLE 1 +#define FM_INTREQ_IRQ065MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ066MON_AVAILABLE 1 +#define FM_INTREQ_IRQ066MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ067MON_AVAILABLE 1 +#define FM_INTREQ_IRQ067MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ068MON_AVAILABLE 1 +#define FM_INTREQ_IRQ068MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ069MON_AVAILABLE 1 +#define FM_INTREQ_IRQ069MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ070MON_AVAILABLE 1 +#define FM_INTREQ_IRQ070MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ071MON_AVAILABLE 1 +#define FM_INTREQ_IRQ071MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ072MON_AVAILABLE 1 +#define FM_INTREQ_IRQ072MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ073MON_AVAILABLE 1 +#define FM_INTREQ_IRQ073MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ074MON_AVAILABLE 1 +#define FM_INTREQ_IRQ074MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ075MON_AVAILABLE 1 +#define FM_INTREQ_IRQ075MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ076MON_AVAILABLE 1 +#define FM_INTREQ_IRQ076MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ077MON_AVAILABLE 1 +#define FM_INTREQ_IRQ077MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ078MON_AVAILABLE 1 +#define FM_INTREQ_IRQ078MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ079MON_AVAILABLE 1 +#define FM_INTREQ_IRQ079MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ080MON_AVAILABLE 1 +#define FM_INTREQ_IRQ080MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ081MON_AVAILABLE 1 +#define FM_INTREQ_IRQ081MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ082MON_AVAILABLE 1 +#define FM_INTREQ_IRQ082MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ083MON_AVAILABLE 1 +#define FM_INTREQ_IRQ083MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ084MON_AVAILABLE 1 +#define FM_INTREQ_IRQ084MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ085MON_AVAILABLE 1 +#define FM_INTREQ_IRQ085MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ086MON_AVAILABLE 1 +#define FM_INTREQ_IRQ086MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ087MON_AVAILABLE 1 +#define FM_INTREQ_IRQ087MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ088MON_AVAILABLE 1 +#define FM_INTREQ_IRQ088MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ089MON_AVAILABLE 1 +#define FM_INTREQ_IRQ089MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ090MON_AVAILABLE 1 +#define FM_INTREQ_IRQ090MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ091MON_AVAILABLE 1 +#define FM_INTREQ_IRQ091MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ092MON_AVAILABLE 1 +#define FM_INTREQ_IRQ092MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ093MON_AVAILABLE 1 +#define FM_INTREQ_IRQ093MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ094MON_AVAILABLE 1 +#define FM_INTREQ_IRQ094MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ095MON_AVAILABLE 1 +#define FM_INTREQ_IRQ095MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ096MON_AVAILABLE 1 +#define FM_INTREQ_IRQ096MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ097MON_AVAILABLE 1 +#define FM_INTREQ_IRQ097MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ098MON_AVAILABLE 1 +#define FM_INTREQ_IRQ098MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ099MON_AVAILABLE 1 +#define FM_INTREQ_IRQ099MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ100MON_AVAILABLE 1 +#define FM_INTREQ_IRQ100MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ101MON_AVAILABLE 1 +#define FM_INTREQ_IRQ101MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ102MON_AVAILABLE 1 +#define FM_INTREQ_IRQ102MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ103MON_AVAILABLE 1 +#define FM_INTREQ_IRQ103MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ104MON_AVAILABLE 1 +#define FM_INTREQ_IRQ104MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ105MON_AVAILABLE 1 +#define FM_INTREQ_IRQ105MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ106MON_AVAILABLE 1 +#define FM_INTREQ_IRQ106MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ107MON_AVAILABLE 1 +#define FM_INTREQ_IRQ107MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ108MON_AVAILABLE 1 +#define FM_INTREQ_IRQ108MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ109MON_AVAILABLE 1 +#define FM_INTREQ_IRQ109MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ110MON_AVAILABLE 1 +#define FM_INTREQ_IRQ110MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ111MON_AVAILABLE 1 +#define FM_INTREQ_IRQ111MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ112MON_AVAILABLE 1 +#define FM_INTREQ_IRQ112MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ113MON_AVAILABLE 1 +#define FM_INTREQ_IRQ113MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ114MON_AVAILABLE 1 +#define FM_INTREQ_IRQ114MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ115MON_AVAILABLE 1 +#define FM_INTREQ_IRQ115MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ116MON_AVAILABLE 1 +#define FM_INTREQ_IRQ116MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ117MON_AVAILABLE 1 +#define FM_INTREQ_IRQ117MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ118MON_AVAILABLE 1 +#define FM_INTREQ_IRQ118MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ119MON_AVAILABLE 1 +#define FM_INTREQ_IRQ119MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ120MON_AVAILABLE 1 +#define FM_INTREQ_IRQ120MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ121MON_AVAILABLE 1 +#define FM_INTREQ_IRQ121MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ122MON_AVAILABLE 1 +#define FM_INTREQ_IRQ122MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ123MON_AVAILABLE 1 +#define FM_INTREQ_IRQ123MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ124MON_AVAILABLE 1 +#define FM_INTREQ_IRQ124MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ125MON_AVAILABLE 1 +#define FM_INTREQ_IRQ125MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ126MON_AVAILABLE 1 +#define FM_INTREQ_IRQ126MON_AVAILABLE 1 +#define FM4_INTREQ_IRQ127MON_AVAILABLE 1 +#define FM_INTREQ_IRQ127MON_AVAILABLE 1 +#define FM4_INTREQ_ODDPKS_AVAILABLE 1 +#define FM_INTREQ_ODDPKS_AVAILABLE 1 +#define FM4_INTREQ_ODDPKS1_AVAILABLE 1 +#define FM_INTREQ_ODDPKS1_AVAILABLE 1 +/******************************************************************************* +* LSCRP +*******************************************************************************/ +#define FM4_LSCRP_LCR_PRSLD_AVAILABLE 1 +#define FM_LSCRP_LCR_PRSLD_AVAILABLE 1 +/******************************************************************************* +* LVD +*******************************************************************************/ +#define FM4_LVD_LVD_CLR_AVAILABLE 1 +#define FM_LVD_LVD_CLR_AVAILABLE 1 +#define FM4_LVD_LVD_CTL_AVAILABLE 1 +#define FM_LVD_LVD_CTL_AVAILABLE 1 +#define FM4_LVD_LVD_RLR_AVAILABLE 1 +#define FM_LVD_LVD_RLR_AVAILABLE 1 +#define FM4_LVD_LVD_STR_AVAILABLE 1 +#define FM_LVD_LVD_STR_AVAILABLE 1 +#define FM4_LVD_LVD_STR2_AVAILABLE 1 +#define FM_LVD_LVD_STR2_AVAILABLE 1 +/******************************************************************************* +* MFS0 +*******************************************************************************/ +#define FM4_MFS_CSIO_BGR_AVAILABLE 1 +#define FM_MFS_CSIO_BGR_AVAILABLE 1 +#define FM4_MFS_CSIO_ESCR_AVAILABLE 1 +#define FM_MFS_CSIO_ESCR_AVAILABLE 1 +#define FM4_MFS_CSIO_FBYTE1_AVAILABLE 1 +#define FM_MFS_CSIO_FBYTE1_AVAILABLE 1 +#define FM4_MFS_CSIO_FBYTE2_AVAILABLE 1 +#define FM_MFS_CSIO_FBYTE2_AVAILABLE 1 +#define FM4_MFS_CSIO_FCR_AVAILABLE 1 +#define FM_MFS_CSIO_FCR_AVAILABLE 1 +#define FM4_MFS_CSIO_RDR_AVAILABLE 1 +#define FM_MFS_CSIO_RDR_AVAILABLE 1 +#define FM4_MFS_CSIO_SACSR_AVAILABLE 1 +#define FM_MFS_CSIO_SACSR_AVAILABLE 1 +#define FM4_MFS_CSIO_SCR_AVAILABLE 1 +#define FM_MFS_CSIO_SCR_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSCR_AVAILABLE 1 +#define FM_MFS_CSIO_SCSCR_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSFR0_AVAILABLE 1 +#define FM_MFS_CSIO_SCSFR0_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSFR1_AVAILABLE 1 +#define FM_MFS_CSIO_SCSFR1_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSFR2_AVAILABLE 1 +#define FM_MFS_CSIO_SCSFR2_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSTR0_AVAILABLE 1 +#define FM_MFS_CSIO_SCSTR0_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSTR1_AVAILABLE 1 +#define FM_MFS_CSIO_SCSTR1_AVAILABLE 1 +#define FM4_MFS_CSIO_SCSTR32_AVAILABLE 1 +#define FM_MFS_CSIO_SCSTR32_AVAILABLE 1 +#define FM4_MFS_CSIO_SMR_AVAILABLE 1 +#define FM_MFS_CSIO_SMR_AVAILABLE 1 +#define FM4_MFS_CSIO_SSR_AVAILABLE 1 +#define FM_MFS_CSIO_SSR_AVAILABLE 1 +#define FM4_MFS_CSIO_STMCR_AVAILABLE 1 +#define FM_MFS_CSIO_STMCR_AVAILABLE 1 +#define FM4_MFS_CSIO_STMR_AVAILABLE 1 +#define FM_MFS_CSIO_STMR_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE0_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE0_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE1_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE1_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE2_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE2_AVAILABLE 1 +#define FM4_MFS_CSIO_TBYTE3_AVAILABLE 1 +#define FM_MFS_CSIO_TBYTE3_AVAILABLE 1 +#define FM4_MFS_CSIO_TDR_AVAILABLE 1 +#define FM_MFS_CSIO_TDR_AVAILABLE 1 +#define FM4_MFS_I2C_BGR_AVAILABLE 1 +#define FM_MFS_I2C_BGR_AVAILABLE 1 +#define FM4_MFS_I2C_EIBCR_AVAILABLE 1 +#define FM_MFS_I2C_EIBCR_AVAILABLE 1 +#define FM4_MFS_I2C_FBYTE1_AVAILABLE 1 +#define FM_MFS_I2C_FBYTE1_AVAILABLE 1 +#define FM4_MFS_I2C_FBYTE2_AVAILABLE 1 +#define FM_MFS_I2C_FBYTE2_AVAILABLE 1 +#define FM4_MFS_I2C_FCR_AVAILABLE 1 +#define FM_MFS_I2C_FCR_AVAILABLE 1 +#define FM4_MFS_I2C_IBCR_AVAILABLE 1 +#define FM_MFS_I2C_IBCR_AVAILABLE 1 +#define FM4_MFS_I2C_IBSR_AVAILABLE 1 +#define FM_MFS_I2C_IBSR_AVAILABLE 1 +#define FM4_MFS_I2C_ISBA_AVAILABLE 1 +#define FM_MFS_I2C_ISBA_AVAILABLE 1 +#define FM4_MFS_I2C_ISMK_AVAILABLE 1 +#define FM_MFS_I2C_ISMK_AVAILABLE 1 +#define FM4_MFS_I2C_NFCR_AVAILABLE 1 +#define FM_MFS_I2C_NFCR_AVAILABLE 1 +#define FM4_MFS_I2C_RDR_AVAILABLE 1 +#define FM_MFS_I2C_RDR_AVAILABLE 1 +#define FM4_MFS_I2C_SMR_AVAILABLE 1 +#define FM_MFS_I2C_SMR_AVAILABLE 1 +#define FM4_MFS_I2C_SSR_AVAILABLE 1 +#define FM_MFS_I2C_SSR_AVAILABLE 1 +#define FM4_MFS_I2C_TDR_AVAILABLE 1 +#define FM_MFS_I2C_TDR_AVAILABLE 1 +#define FM4_MFS_LIN_BGR_AVAILABLE 1 +#define FM_MFS_LIN_BGR_AVAILABLE 1 +#define FM4_MFS_LIN_ESCR_AVAILABLE 1 +#define FM_MFS_LIN_ESCR_AVAILABLE 1 +#define FM4_MFS_LIN_FBYTE1_AVAILABLE 1 +#define FM_MFS_LIN_FBYTE1_AVAILABLE 1 +#define FM4_MFS_LIN_FBYTE2_AVAILABLE 1 +#define FM_MFS_LIN_FBYTE2_AVAILABLE 1 +#define FM4_MFS_LIN_FCR_AVAILABLE 1 +#define FM_MFS_LIN_FCR_AVAILABLE 1 +#define FM4_MFS_LIN_RDR_AVAILABLE 1 +#define FM_MFS_LIN_RDR_AVAILABLE 1 +#define FM4_MFS_LIN_SCR_AVAILABLE 1 +#define FM_MFS_LIN_SCR_AVAILABLE 1 +#define FM4_MFS_LIN_SMR_AVAILABLE 1 +#define FM_MFS_LIN_SMR_AVAILABLE 1 +#define FM4_MFS_LIN_SSR_AVAILABLE 1 +#define FM_MFS_LIN_SSR_AVAILABLE 1 +#define FM4_MFS_LIN_TDR_AVAILABLE 1 +#define FM_MFS_LIN_TDR_AVAILABLE 1 +#define FM4_MFS_UART_BGR_AVAILABLE 1 +#define FM_MFS_UART_BGR_AVAILABLE 1 +#define FM4_MFS_UART_ESCR_AVAILABLE 1 +#define FM_MFS_UART_ESCR_AVAILABLE 1 +#define FM4_MFS_UART_FBYTE1_AVAILABLE 1 +#define FM_MFS_UART_FBYTE1_AVAILABLE 1 +#define FM4_MFS_UART_FBYTE2_AVAILABLE 1 +#define FM_MFS_UART_FBYTE2_AVAILABLE 1 +#define FM4_MFS_UART_FCR_AVAILABLE 1 +#define FM_MFS_UART_FCR_AVAILABLE 1 +#define FM4_MFS_UART_RDR_AVAILABLE 1 +#define FM_MFS_UART_RDR_AVAILABLE 1 +#define FM4_MFS_UART_SCR_AVAILABLE 1 +#define FM_MFS_UART_SCR_AVAILABLE 1 +#define FM4_MFS_UART_SMR_AVAILABLE 1 +#define FM_MFS_UART_SMR_AVAILABLE 1 +#define FM4_MFS_UART_SSR_AVAILABLE 1 +#define FM_MFS_UART_SSR_AVAILABLE 1 +#define FM4_MFS_UART_TDR_AVAILABLE 1 +#define FM_MFS_UART_TDR_AVAILABLE 1 +/******************************************************************************* +* MFT0 +*******************************************************************************/ +#define FM4_MFT_ADCMP_ACFS10_AVAILABLE 1 +#define FM_MFT_ADCMP_ACFS10_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACFS32_AVAILABLE 1 +#define FM_MFT_ADCMP_ACFS32_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACFS54_AVAILABLE 1 +#define FM_MFT_ADCMP_ACFS54_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMC5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMC5_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACMP5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACMP5_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSA_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSA_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSC5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSC5_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD0_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD0_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD1_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD1_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD2_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD2_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD3_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD3_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD4_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD4_AVAILABLE 1 +#define FM4_MFT_ADCMP_ACSD5_AVAILABLE 1 +#define FM_MFT_ADCMP_ACSD5_AVAILABLE 1 +#define FM4_MFT_FRT_TCAL_AVAILABLE 1 +#define FM_MFT_FRT_TCAL_AVAILABLE 1 +#define FM4_MFT_FRT_TCCP0_AVAILABLE 1 +#define FM_MFT_FRT_TCCP0_AVAILABLE 1 +#define FM4_MFT_FRT_TCCP1_AVAILABLE 1 +#define FM_MFT_FRT_TCCP1_AVAILABLE 1 +#define FM4_MFT_FRT_TCCP2_AVAILABLE 1 +#define FM_MFT_FRT_TCCP2_AVAILABLE 1 +#define FM4_MFT_FRT_TCDT0_AVAILABLE 1 +#define FM_MFT_FRT_TCDT0_AVAILABLE 1 +#define FM4_MFT_FRT_TCDT1_AVAILABLE 1 +#define FM_MFT_FRT_TCDT1_AVAILABLE 1 +#define FM4_MFT_FRT_TCDT2_AVAILABLE 1 +#define FM_MFT_FRT_TCDT2_AVAILABLE 1 +#define FM4_MFT_FRT_TCSA0_AVAILABLE 1 +#define FM_MFT_FRT_TCSA0_AVAILABLE 1 +#define FM4_MFT_FRT_TCSA1_AVAILABLE 1 +#define FM_MFT_FRT_TCSA1_AVAILABLE 1 +#define FM4_MFT_FRT_TCSA2_AVAILABLE 1 +#define FM_MFT_FRT_TCSA2_AVAILABLE 1 +#define FM4_MFT_FRT_TCSC0_AVAILABLE 1 +#define FM_MFT_FRT_TCSC0_AVAILABLE 1 +#define FM4_MFT_FRT_TCSC1_AVAILABLE 1 +#define FM_MFT_FRT_TCSC1_AVAILABLE 1 +#define FM4_MFT_FRT_TCSC2_AVAILABLE 1 +#define FM_MFT_FRT_TCSC2_AVAILABLE 1 +#define FM4_MFT_FRT_TCSD_AVAILABLE 1 +#define FM_MFT_FRT_TCSD_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP0_AVAILABLE 1 +#define FM_MFT_ICU_ICCP0_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP1_AVAILABLE 1 +#define FM_MFT_ICU_ICCP1_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP2_AVAILABLE 1 +#define FM_MFT_ICU_ICCP2_AVAILABLE 1 +#define FM4_MFT_ICU_ICCP3_AVAILABLE 1 +#define FM_MFT_ICU_ICCP3_AVAILABLE 1 +#define FM4_MFT_ICU_ICFS10_AVAILABLE 1 +#define FM_MFT_ICU_ICFS10_AVAILABLE 1 +#define FM4_MFT_ICU_ICFS32_AVAILABLE 1 +#define FM_MFT_ICU_ICFS32_AVAILABLE 1 +#define FM4_MFT_ICU_ICSA10_AVAILABLE 1 +#define FM_MFT_ICU_ICSA10_AVAILABLE 1 +#define FM4_MFT_ICU_ICSA32_AVAILABLE 1 +#define FM_MFT_ICU_ICSA32_AVAILABLE 1 +#define FM4_MFT_ICU_ICSB10_AVAILABLE 1 +#define FM_MFT_ICU_ICSB10_AVAILABLE 1 +#define FM4_MFT_ICU_ICSB32_AVAILABLE 1 +#define FM_MFT_ICU_ICSB32_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP0_AVAILABLE 1 +#define FM_MFT_OCU_OCCP0_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP1_AVAILABLE 1 +#define FM_MFT_OCU_OCCP1_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP2_AVAILABLE 1 +#define FM_MFT_OCU_OCCP2_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP3_AVAILABLE 1 +#define FM_MFT_OCU_OCCP3_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP4_AVAILABLE 1 +#define FM_MFT_OCU_OCCP4_AVAILABLE 1 +#define FM4_MFT_OCU_OCCP5_AVAILABLE 1 +#define FM_MFT_OCU_OCCP5_AVAILABLE 1 +#define FM4_MFT_OCU_OCFS10_AVAILABLE 1 +#define FM_MFT_OCU_OCFS10_AVAILABLE 1 +#define FM4_MFT_OCU_OCFS32_AVAILABLE 1 +#define FM_MFT_OCU_OCFS32_AVAILABLE 1 +#define FM4_MFT_OCU_OCFS54_AVAILABLE 1 +#define FM_MFT_OCU_OCFS54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSA10_AVAILABLE 1 +#define FM_MFT_OCU_OCSA10_AVAILABLE 1 +#define FM4_MFT_OCU_OCSA32_AVAILABLE 1 +#define FM_MFT_OCU_OCSA32_AVAILABLE 1 +#define FM4_MFT_OCU_OCSA54_AVAILABLE 1 +#define FM_MFT_OCU_OCSA54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSB10_AVAILABLE 1 +#define FM_MFT_OCU_OCSB10_AVAILABLE 1 +#define FM4_MFT_OCU_OCSB32_AVAILABLE 1 +#define FM_MFT_OCU_OCSB32_AVAILABLE 1 +#define FM4_MFT_OCU_OCSB54_AVAILABLE 1 +#define FM_MFT_OCU_OCSB54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSC_AVAILABLE 1 +#define FM_MFT_OCU_OCSC_AVAILABLE 1 +#define FM4_MFT_OCU_OCSD10_AVAILABLE 1 +#define FM_MFT_OCU_OCSD10_AVAILABLE 1 +#define FM4_MFT_OCU_OCSD32_AVAILABLE 1 +#define FM_MFT_OCU_OCSD32_AVAILABLE 1 +#define FM4_MFT_OCU_OCSD54_AVAILABLE 1 +#define FM_MFT_OCU_OCSD54_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE0_AVAILABLE 1 +#define FM_MFT_OCU_OCSE0_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE1_AVAILABLE 1 +#define FM_MFT_OCU_OCSE1_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE2_AVAILABLE 1 +#define FM_MFT_OCU_OCSE2_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE3_AVAILABLE 1 +#define FM_MFT_OCU_OCSE3_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE4_AVAILABLE 1 +#define FM_MFT_OCU_OCSE4_AVAILABLE 1 +#define FM4_MFT_OCU_OCSE5_AVAILABLE 1 +#define FM_MFT_OCU_OCSE5_AVAILABLE 1 +#define FM4_MFT_WFG_NZCL_AVAILABLE 1 +#define FM_MFT_WFG_NZCL_AVAILABLE 1 +#define FM4_MFT_WFG_WFIR_AVAILABLE 1 +#define FM_MFT_WFG_WFIR_AVAILABLE 1 +#define FM4_MFT_WFG_WFSA10_AVAILABLE 1 +#define FM_MFT_WFG_WFSA10_AVAILABLE 1 +#define FM4_MFT_WFG_WFSA32_AVAILABLE 1 +#define FM_MFT_WFG_WFSA32_AVAILABLE 1 +#define FM4_MFT_WFG_WFSA54_AVAILABLE 1 +#define FM_MFT_WFG_WFSA54_AVAILABLE 1 +#define FM4_MFT_WFG_WFTA10_AVAILABLE 1 +#define FM_MFT_WFG_WFTA10_AVAILABLE 1 +#define FM4_MFT_WFG_WFTA32_AVAILABLE 1 +#define FM_MFT_WFG_WFTA32_AVAILABLE 1 +#define FM4_MFT_WFG_WFTA54_AVAILABLE 1 +#define FM_MFT_WFG_WFTA54_AVAILABLE 1 +#define FM4_MFT_WFG_WFTB10_AVAILABLE 1 +#define FM_MFT_WFG_WFTB10_AVAILABLE 1 +#define FM4_MFT_WFG_WFTB32_AVAILABLE 1 +#define FM_MFT_WFG_WFTB32_AVAILABLE 1 +#define FM4_MFT_WFG_WFTB54_AVAILABLE 1 +#define FM_MFT_WFG_WFTB54_AVAILABLE 1 +#define FM4_MFT_WFG_WFTF10_AVAILABLE 1 +#define FM_MFT_WFG_WFTF10_AVAILABLE 1 +#define FM4_MFT_WFG_WFTF32_AVAILABLE 1 +#define FM_MFT_WFG_WFTF32_AVAILABLE 1 +#define FM4_MFT_WFG_WFTF54_AVAILABLE 1 +#define FM_MFT_WFG_WFTF54_AVAILABLE 1 +/******************************************************************************* +* MFT_PPG +*******************************************************************************/ +#define FM4_MFT_PPG_COMP0_AVAILABLE 1 +#define FM_MFT_PPG_COMP0_AVAILABLE 1 +#define FM4_MFT_PPG_COMP1_AVAILABLE 1 +#define FM_MFT_PPG_COMP1_AVAILABLE 1 +#define FM4_MFT_PPG_COMP10_AVAILABLE 1 +#define FM_MFT_PPG_COMP10_AVAILABLE 1 +#define FM4_MFT_PPG_COMP12_AVAILABLE 1 +#define FM_MFT_PPG_COMP12_AVAILABLE 1 +#define FM4_MFT_PPG_COMP14_AVAILABLE 1 +#define FM_MFT_PPG_COMP14_AVAILABLE 1 +#define FM4_MFT_PPG_COMP2_AVAILABLE 1 +#define FM_MFT_PPG_COMP2_AVAILABLE 1 +#define FM4_MFT_PPG_COMP3_AVAILABLE 1 +#define FM_MFT_PPG_COMP3_AVAILABLE 1 +#define FM4_MFT_PPG_COMP4_AVAILABLE 1 +#define FM_MFT_PPG_COMP4_AVAILABLE 1 +#define FM4_MFT_PPG_COMP5_AVAILABLE 1 +#define FM_MFT_PPG_COMP5_AVAILABLE 1 +#define FM4_MFT_PPG_COMP6_AVAILABLE 1 +#define FM_MFT_PPG_COMP6_AVAILABLE 1 +#define FM4_MFT_PPG_COMP7_AVAILABLE 1 +#define FM_MFT_PPG_COMP7_AVAILABLE 1 +#define FM4_MFT_PPG_COMP8_AVAILABLE 1 +#define FM_MFT_PPG_COMP8_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC0_AVAILABLE 1 +#define FM_MFT_PPG_GATEC0_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC12_AVAILABLE 1 +#define FM_MFT_PPG_GATEC12_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC16_AVAILABLE 1 +#define FM_MFT_PPG_GATEC16_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC20_AVAILABLE 1 +#define FM_MFT_PPG_GATEC20_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC4_AVAILABLE 1 +#define FM_MFT_PPG_GATEC4_AVAILABLE 1 +#define FM4_MFT_PPG_GATEC8_AVAILABLE 1 +#define FM_MFT_PPG_GATEC8_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC0_AVAILABLE 1 +#define FM_MFT_PPG_PPGC0_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC1_AVAILABLE 1 +#define FM_MFT_PPG_PPGC1_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC10_AVAILABLE 1 +#define FM_MFT_PPG_PPGC10_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC11_AVAILABLE 1 +#define FM_MFT_PPG_PPGC11_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC12_AVAILABLE 1 +#define FM_MFT_PPG_PPGC12_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC13_AVAILABLE 1 +#define FM_MFT_PPG_PPGC13_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC14_AVAILABLE 1 +#define FM_MFT_PPG_PPGC14_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC15_AVAILABLE 1 +#define FM_MFT_PPG_PPGC15_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC16_AVAILABLE 1 +#define FM_MFT_PPG_PPGC16_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC17_AVAILABLE 1 +#define FM_MFT_PPG_PPGC17_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC18_AVAILABLE 1 +#define FM_MFT_PPG_PPGC18_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC19_AVAILABLE 1 +#define FM_MFT_PPG_PPGC19_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC2_AVAILABLE 1 +#define FM_MFT_PPG_PPGC2_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC20_AVAILABLE 1 +#define FM_MFT_PPG_PPGC20_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC21_AVAILABLE 1 +#define FM_MFT_PPG_PPGC21_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC22_AVAILABLE 1 +#define FM_MFT_PPG_PPGC22_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC23_AVAILABLE 1 +#define FM_MFT_PPG_PPGC23_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC3_AVAILABLE 1 +#define FM_MFT_PPG_PPGC3_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC4_AVAILABLE 1 +#define FM_MFT_PPG_PPGC4_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC5_AVAILABLE 1 +#define FM_MFT_PPG_PPGC5_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC6_AVAILABLE 1 +#define FM_MFT_PPG_PPGC6_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC7_AVAILABLE 1 +#define FM_MFT_PPG_PPGC7_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC8_AVAILABLE 1 +#define FM_MFT_PPG_PPGC8_AVAILABLE 1 +#define FM4_MFT_PPG_PPGC9_AVAILABLE 1 +#define FM_MFT_PPG_PPGC9_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH0_AVAILABLE 1 +#define FM_MFT_PPG_PRLH0_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH1_AVAILABLE 1 +#define FM_MFT_PPG_PRLH1_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH10_AVAILABLE 1 +#define FM_MFT_PPG_PRLH10_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH11_AVAILABLE 1 +#define FM_MFT_PPG_PRLH11_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH12_AVAILABLE 1 +#define FM_MFT_PPG_PRLH12_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH13_AVAILABLE 1 +#define FM_MFT_PPG_PRLH13_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH14_AVAILABLE 1 +#define FM_MFT_PPG_PRLH14_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH15_AVAILABLE 1 +#define FM_MFT_PPG_PRLH15_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH16_AVAILABLE 1 +#define FM_MFT_PPG_PRLH16_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH17_AVAILABLE 1 +#define FM_MFT_PPG_PRLH17_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH18_AVAILABLE 1 +#define FM_MFT_PPG_PRLH18_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH19_AVAILABLE 1 +#define FM_MFT_PPG_PRLH19_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH2_AVAILABLE 1 +#define FM_MFT_PPG_PRLH2_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH20_AVAILABLE 1 +#define FM_MFT_PPG_PRLH20_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH21_AVAILABLE 1 +#define FM_MFT_PPG_PRLH21_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH22_AVAILABLE 1 +#define FM_MFT_PPG_PRLH22_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH23_AVAILABLE 1 +#define FM_MFT_PPG_PRLH23_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH3_AVAILABLE 1 +#define FM_MFT_PPG_PRLH3_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH4_AVAILABLE 1 +#define FM_MFT_PPG_PRLH4_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH5_AVAILABLE 1 +#define FM_MFT_PPG_PRLH5_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH6_AVAILABLE 1 +#define FM_MFT_PPG_PRLH6_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH7_AVAILABLE 1 +#define FM_MFT_PPG_PRLH7_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH8_AVAILABLE 1 +#define FM_MFT_PPG_PRLH8_AVAILABLE 1 +#define FM4_MFT_PPG_PRLH9_AVAILABLE 1 +#define FM_MFT_PPG_PRLH9_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL0_AVAILABLE 1 +#define FM_MFT_PPG_PRLL0_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL1_AVAILABLE 1 +#define FM_MFT_PPG_PRLL1_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL10_AVAILABLE 1 +#define FM_MFT_PPG_PRLL10_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL11_AVAILABLE 1 +#define FM_MFT_PPG_PRLL11_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL12_AVAILABLE 1 +#define FM_MFT_PPG_PRLL12_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL13_AVAILABLE 1 +#define FM_MFT_PPG_PRLL13_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL14_AVAILABLE 1 +#define FM_MFT_PPG_PRLL14_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL15_AVAILABLE 1 +#define FM_MFT_PPG_PRLL15_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL16_AVAILABLE 1 +#define FM_MFT_PPG_PRLL16_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL17_AVAILABLE 1 +#define FM_MFT_PPG_PRLL17_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL18_AVAILABLE 1 +#define FM_MFT_PPG_PRLL18_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL19_AVAILABLE 1 +#define FM_MFT_PPG_PRLL19_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL2_AVAILABLE 1 +#define FM_MFT_PPG_PRLL2_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL20_AVAILABLE 1 +#define FM_MFT_PPG_PRLL20_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL21_AVAILABLE 1 +#define FM_MFT_PPG_PRLL21_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL22_AVAILABLE 1 +#define FM_MFT_PPG_PRLL22_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL23_AVAILABLE 1 +#define FM_MFT_PPG_PRLL23_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL3_AVAILABLE 1 +#define FM_MFT_PPG_PRLL3_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL4_AVAILABLE 1 +#define FM_MFT_PPG_PRLL4_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL5_AVAILABLE 1 +#define FM_MFT_PPG_PRLL5_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL6_AVAILABLE 1 +#define FM_MFT_PPG_PRLL6_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL7_AVAILABLE 1 +#define FM_MFT_PPG_PRLL7_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL8_AVAILABLE 1 +#define FM_MFT_PPG_PRLL8_AVAILABLE 1 +#define FM4_MFT_PPG_PRLL9_AVAILABLE 1 +#define FM_MFT_PPG_PRLL9_AVAILABLE 1 +#define FM4_MFT_PPG_REVC0_AVAILABLE 1 +#define FM_MFT_PPG_REVC0_AVAILABLE 1 +#define FM4_MFT_PPG_REVC1_AVAILABLE 1 +#define FM_MFT_PPG_REVC1_AVAILABLE 1 +#define FM4_MFT_PPG_TRG0_AVAILABLE 1 +#define FM_MFT_PPG_TRG0_AVAILABLE 1 +#define FM4_MFT_PPG_TRG1_AVAILABLE 1 +#define FM_MFT_PPG_TRG1_AVAILABLE 1 +#define FM4_MFT_PPG_TTCR0_AVAILABLE 1 +#define FM_MFT_PPG_TTCR0_AVAILABLE 1 +#define FM4_MFT_PPG_TTCR1_AVAILABLE 1 +#define FM_MFT_PPG_TTCR1_AVAILABLE 1 +#define FM4_MFT_PPG_TTCR2_AVAILABLE 1 +#define FM_MFT_PPG_TTCR2_AVAILABLE 1 +/******************************************************************************* +* PCRC +*******************************************************************************/ +#define FM4_PCRC_PCRC_CFG_AVAILABLE 1 +#define FM_PCRC_PCRC_CFG_AVAILABLE 1 +#define FM4_PCRC_PCRC_FXOR_AVAILABLE 1 +#define FM_PCRC_PCRC_FXOR_AVAILABLE 1 +#define FM4_PCRC_PCRC_POLY_AVAILABLE 1 +#define FM_PCRC_PCRC_POLY_AVAILABLE 1 +#define FM4_PCRC_PCRC_RD_AVAILABLE 1 +#define FM_PCRC_PCRC_RD_AVAILABLE 1 +#define FM4_PCRC_PCRC_SEED_AVAILABLE 1 +#define FM_PCRC_PCRC_SEED_AVAILABLE 1 +#define FM4_PCRC_PCRC_WR_AVAILABLE 1 +#define FM_PCRC_PCRC_WR_AVAILABLE 1 +/******************************************************************************* +* QPRC0 +*******************************************************************************/ +#define FM4_QPRC_QCR_AVAILABLE 1 +#define FM_QPRC_QCR_AVAILABLE 1 +#define FM4_QPRC_QECR_AVAILABLE 1 +#define FM_QPRC_QECR_AVAILABLE 1 +#define FM4_QPRC_QICRH_AVAILABLE 1 +#define FM_QPRC_QICRH_AVAILABLE 1 +#define FM4_QPRC_QICRL_AVAILABLE 1 +#define FM_QPRC_QICRL_AVAILABLE 1 +#define FM4_QPRC_QMPR_AVAILABLE 1 +#define FM_QPRC_QMPR_AVAILABLE 1 +#define FM4_QPRC_QPCCR_AVAILABLE 1 +#define FM_QPRC_QPCCR_AVAILABLE 1 +#define FM4_QPRC_QPCR_AVAILABLE 1 +#define FM_QPRC_QPCR_AVAILABLE 1 +#define FM4_QPRC_QPRCR_AVAILABLE 1 +#define FM_QPRC_QPRCR_AVAILABLE 1 +#define FM4_QPRC_QPRCRR_AVAILABLE 1 +#define FM_QPRC_QPRCRR_AVAILABLE 1 +#define FM4_QPRC_QRCR_AVAILABLE 1 +#define FM_QPRC_QRCR_AVAILABLE 1 +/******************************************************************************* +* QPRC0_NF +*******************************************************************************/ +#define FM4_QPRC_NF_NFCTLA_AVAILABLE 1 +#define FM_QPRC_NF_NFCTLA_AVAILABLE 1 +#define FM4_QPRC_NF_NFCTLB_AVAILABLE 1 +#define FM_QPRC_NF_NFCTLB_AVAILABLE 1 +#define FM4_QPRC_NF_NFCTLZ_AVAILABLE 1 +#define FM_QPRC_NF_NFCTLZ_AVAILABLE 1 +/******************************************************************************* +* RTC +*******************************************************************************/ +#define FM4_RTC_ALDR_AVAILABLE 1 +#define FM_RTC_ALDR_AVAILABLE 1 +#define FM4_RTC_ALHR_AVAILABLE 1 +#define FM_RTC_ALHR_AVAILABLE 1 +#define FM4_RTC_ALMIR_AVAILABLE 1 +#define FM_RTC_ALMIR_AVAILABLE 1 +#define FM4_RTC_ALMOR_AVAILABLE 1 +#define FM_RTC_ALMOR_AVAILABLE 1 +#define FM4_RTC_ALYR_AVAILABLE 1 +#define FM_RTC_ALYR_AVAILABLE 1 +#define FM4_RTC_BOOST_AVAILABLE 1 +#define FM_RTC_BOOST_AVAILABLE 1 +#define FM4_RTC_BREG00_AVAILABLE 1 +#define FM_RTC_BREG00_AVAILABLE 1 +#define FM4_RTC_BREG01_AVAILABLE 1 +#define FM_RTC_BREG01_AVAILABLE 1 +#define FM4_RTC_BREG02_AVAILABLE 1 +#define FM_RTC_BREG02_AVAILABLE 1 +#define FM4_RTC_BREG03_AVAILABLE 1 +#define FM_RTC_BREG03_AVAILABLE 1 +#define FM4_RTC_BREG04_AVAILABLE 1 +#define FM_RTC_BREG04_AVAILABLE 1 +#define FM4_RTC_BREG05_AVAILABLE 1 +#define FM_RTC_BREG05_AVAILABLE 1 +#define FM4_RTC_BREG06_AVAILABLE 1 +#define FM_RTC_BREG06_AVAILABLE 1 +#define FM4_RTC_BREG07_AVAILABLE 1 +#define FM_RTC_BREG07_AVAILABLE 1 +#define FM4_RTC_BREG08_AVAILABLE 1 +#define FM_RTC_BREG08_AVAILABLE 1 +#define FM4_RTC_BREG09_AVAILABLE 1 +#define FM_RTC_BREG09_AVAILABLE 1 +#define FM4_RTC_BREG0A_AVAILABLE 1 +#define FM_RTC_BREG0A_AVAILABLE 1 +#define FM4_RTC_BREG0B_AVAILABLE 1 +#define FM_RTC_BREG0B_AVAILABLE 1 +#define FM4_RTC_BREG0C_AVAILABLE 1 +#define FM_RTC_BREG0C_AVAILABLE 1 +#define FM4_RTC_BREG0D_AVAILABLE 1 +#define FM_RTC_BREG0D_AVAILABLE 1 +#define FM4_RTC_BREG0E_AVAILABLE 1 +#define FM_RTC_BREG0E_AVAILABLE 1 +#define FM4_RTC_BREG0F_AVAILABLE 1 +#define FM_RTC_BREG0F_AVAILABLE 1 +#define FM4_RTC_BREG10_AVAILABLE 1 +#define FM_RTC_BREG10_AVAILABLE 1 +#define FM4_RTC_BREG11_AVAILABLE 1 +#define FM_RTC_BREG11_AVAILABLE 1 +#define FM4_RTC_BREG12_AVAILABLE 1 +#define FM_RTC_BREG12_AVAILABLE 1 +#define FM4_RTC_BREG13_AVAILABLE 1 +#define FM_RTC_BREG13_AVAILABLE 1 +#define FM4_RTC_BREG14_AVAILABLE 1 +#define FM_RTC_BREG14_AVAILABLE 1 +#define FM4_RTC_BREG15_AVAILABLE 1 +#define FM_RTC_BREG15_AVAILABLE 1 +#define FM4_RTC_BREG16_AVAILABLE 1 +#define FM_RTC_BREG16_AVAILABLE 1 +#define FM4_RTC_BREG17_AVAILABLE 1 +#define FM_RTC_BREG17_AVAILABLE 1 +#define FM4_RTC_BREG18_AVAILABLE 1 +#define FM_RTC_BREG18_AVAILABLE 1 +#define FM4_RTC_BREG19_AVAILABLE 1 +#define FM_RTC_BREG19_AVAILABLE 1 +#define FM4_RTC_BREG1A_AVAILABLE 1 +#define FM_RTC_BREG1A_AVAILABLE 1 +#define FM4_RTC_BREG1B_AVAILABLE 1 +#define FM_RTC_BREG1B_AVAILABLE 1 +#define FM4_RTC_BREG1C_AVAILABLE 1 +#define FM_RTC_BREG1C_AVAILABLE 1 +#define FM4_RTC_BREG1D_AVAILABLE 1 +#define FM_RTC_BREG1D_AVAILABLE 1 +#define FM4_RTC_BREG1E_AVAILABLE 1 +#define FM_RTC_BREG1E_AVAILABLE 1 +#define FM4_RTC_BREG1F_AVAILABLE 1 +#define FM_RTC_BREG1F_AVAILABLE 1 +#define FM4_RTC_BREG20_AVAILABLE 1 +#define FM_RTC_BREG20_AVAILABLE 1 +#define FM4_RTC_BREG21_AVAILABLE 1 +#define FM_RTC_BREG21_AVAILABLE 1 +#define FM4_RTC_BREG22_AVAILABLE 1 +#define FM_RTC_BREG22_AVAILABLE 1 +#define FM4_RTC_BREG23_AVAILABLE 1 +#define FM_RTC_BREG23_AVAILABLE 1 +#define FM4_RTC_BREG24_AVAILABLE 1 +#define FM_RTC_BREG24_AVAILABLE 1 +#define FM4_RTC_BREG25_AVAILABLE 1 +#define FM_RTC_BREG25_AVAILABLE 1 +#define FM4_RTC_BREG26_AVAILABLE 1 +#define FM_RTC_BREG26_AVAILABLE 1 +#define FM4_RTC_BREG27_AVAILABLE 1 +#define FM_RTC_BREG27_AVAILABLE 1 +#define FM4_RTC_BREG28_AVAILABLE 1 +#define FM_RTC_BREG28_AVAILABLE 1 +#define FM4_RTC_BREG29_AVAILABLE 1 +#define FM_RTC_BREG29_AVAILABLE 1 +#define FM4_RTC_BREG2A_AVAILABLE 1 +#define FM_RTC_BREG2A_AVAILABLE 1 +#define FM4_RTC_BREG2B_AVAILABLE 1 +#define FM_RTC_BREG2B_AVAILABLE 1 +#define FM4_RTC_BREG2C_AVAILABLE 1 +#define FM_RTC_BREG2C_AVAILABLE 1 +#define FM4_RTC_BREG2D_AVAILABLE 1 +#define FM_RTC_BREG2D_AVAILABLE 1 +#define FM4_RTC_BREG2E_AVAILABLE 1 +#define FM_RTC_BREG2E_AVAILABLE 1 +#define FM4_RTC_BREG2F_AVAILABLE 1 +#define FM_RTC_BREG2F_AVAILABLE 1 +#define FM4_RTC_BREG30_AVAILABLE 1 +#define FM_RTC_BREG30_AVAILABLE 1 +#define FM4_RTC_BREG31_AVAILABLE 1 +#define FM_RTC_BREG31_AVAILABLE 1 +#define FM4_RTC_BREG32_AVAILABLE 1 +#define FM_RTC_BREG32_AVAILABLE 1 +#define FM4_RTC_BREG33_AVAILABLE 1 +#define FM_RTC_BREG33_AVAILABLE 1 +#define FM4_RTC_BREG34_AVAILABLE 1 +#define FM_RTC_BREG34_AVAILABLE 1 +#define FM4_RTC_BREG35_AVAILABLE 1 +#define FM_RTC_BREG35_AVAILABLE 1 +#define FM4_RTC_BREG36_AVAILABLE 1 +#define FM_RTC_BREG36_AVAILABLE 1 +#define FM4_RTC_BREG37_AVAILABLE 1 +#define FM_RTC_BREG37_AVAILABLE 1 +#define FM4_RTC_BREG38_AVAILABLE 1 +#define FM_RTC_BREG38_AVAILABLE 1 +#define FM4_RTC_BREG39_AVAILABLE 1 +#define FM_RTC_BREG39_AVAILABLE 1 +#define FM4_RTC_BREG3A_AVAILABLE 1 +#define FM_RTC_BREG3A_AVAILABLE 1 +#define FM4_RTC_BREG3B_AVAILABLE 1 +#define FM_RTC_BREG3B_AVAILABLE 1 +#define FM4_RTC_BREG3C_AVAILABLE 1 +#define FM_RTC_BREG3C_AVAILABLE 1 +#define FM4_RTC_BREG3D_AVAILABLE 1 +#define FM_RTC_BREG3D_AVAILABLE 1 +#define FM4_RTC_BREG3E_AVAILABLE 1 +#define FM_RTC_BREG3E_AVAILABLE 1 +#define FM4_RTC_BREG3F_AVAILABLE 1 +#define FM_RTC_BREG3F_AVAILABLE 1 +#define FM4_RTC_BREG40_AVAILABLE 1 +#define FM_RTC_BREG40_AVAILABLE 1 +#define FM4_RTC_BREG41_AVAILABLE 1 +#define FM_RTC_BREG41_AVAILABLE 1 +#define FM4_RTC_BREG42_AVAILABLE 1 +#define FM_RTC_BREG42_AVAILABLE 1 +#define FM4_RTC_BREG43_AVAILABLE 1 +#define FM_RTC_BREG43_AVAILABLE 1 +#define FM4_RTC_BREG44_AVAILABLE 1 +#define FM_RTC_BREG44_AVAILABLE 1 +#define FM4_RTC_BREG45_AVAILABLE 1 +#define FM_RTC_BREG45_AVAILABLE 1 +#define FM4_RTC_BREG46_AVAILABLE 1 +#define FM_RTC_BREG46_AVAILABLE 1 +#define FM4_RTC_BREG47_AVAILABLE 1 +#define FM_RTC_BREG47_AVAILABLE 1 +#define FM4_RTC_BREG48_AVAILABLE 1 +#define FM_RTC_BREG48_AVAILABLE 1 +#define FM4_RTC_BREG49_AVAILABLE 1 +#define FM_RTC_BREG49_AVAILABLE 1 +#define FM4_RTC_BREG4A_AVAILABLE 1 +#define FM_RTC_BREG4A_AVAILABLE 1 +#define FM4_RTC_BREG4B_AVAILABLE 1 +#define FM_RTC_BREG4B_AVAILABLE 1 +#define FM4_RTC_BREG4C_AVAILABLE 1 +#define FM_RTC_BREG4C_AVAILABLE 1 +#define FM4_RTC_BREG4D_AVAILABLE 1 +#define FM_RTC_BREG4D_AVAILABLE 1 +#define FM4_RTC_BREG4E_AVAILABLE 1 +#define FM_RTC_BREG4E_AVAILABLE 1 +#define FM4_RTC_BREG4F_AVAILABLE 1 +#define FM_RTC_BREG4F_AVAILABLE 1 +#define FM4_RTC_BREG50_AVAILABLE 1 +#define FM_RTC_BREG50_AVAILABLE 1 +#define FM4_RTC_BREG51_AVAILABLE 1 +#define FM_RTC_BREG51_AVAILABLE 1 +#define FM4_RTC_BREG52_AVAILABLE 1 +#define FM_RTC_BREG52_AVAILABLE 1 +#define FM4_RTC_BREG53_AVAILABLE 1 +#define FM_RTC_BREG53_AVAILABLE 1 +#define FM4_RTC_BREG54_AVAILABLE 1 +#define FM_RTC_BREG54_AVAILABLE 1 +#define FM4_RTC_BREG55_AVAILABLE 1 +#define FM_RTC_BREG55_AVAILABLE 1 +#define FM4_RTC_BREG56_AVAILABLE 1 +#define FM_RTC_BREG56_AVAILABLE 1 +#define FM4_RTC_BREG57_AVAILABLE 1 +#define FM_RTC_BREG57_AVAILABLE 1 +#define FM4_RTC_BREG58_AVAILABLE 1 +#define FM_RTC_BREG58_AVAILABLE 1 +#define FM4_RTC_BREG59_AVAILABLE 1 +#define FM_RTC_BREG59_AVAILABLE 1 +#define FM4_RTC_BREG5A_AVAILABLE 1 +#define FM_RTC_BREG5A_AVAILABLE 1 +#define FM4_RTC_BREG5B_AVAILABLE 1 +#define FM_RTC_BREG5B_AVAILABLE 1 +#define FM4_RTC_BREG5C_AVAILABLE 1 +#define FM_RTC_BREG5C_AVAILABLE 1 +#define FM4_RTC_BREG5D_AVAILABLE 1 +#define FM_RTC_BREG5D_AVAILABLE 1 +#define FM4_RTC_BREG5E_AVAILABLE 1 +#define FM_RTC_BREG5E_AVAILABLE 1 +#define FM4_RTC_BREG5F_AVAILABLE 1 +#define FM_RTC_BREG5F_AVAILABLE 1 +#define FM4_RTC_BREG60_AVAILABLE 1 +#define FM_RTC_BREG60_AVAILABLE 1 +#define FM4_RTC_BREG61_AVAILABLE 1 +#define FM_RTC_BREG61_AVAILABLE 1 +#define FM4_RTC_BREG62_AVAILABLE 1 +#define FM_RTC_BREG62_AVAILABLE 1 +#define FM4_RTC_BREG63_AVAILABLE 1 +#define FM_RTC_BREG63_AVAILABLE 1 +#define FM4_RTC_BREG64_AVAILABLE 1 +#define FM_RTC_BREG64_AVAILABLE 1 +#define FM4_RTC_BREG65_AVAILABLE 1 +#define FM_RTC_BREG65_AVAILABLE 1 +#define FM4_RTC_BREG66_AVAILABLE 1 +#define FM_RTC_BREG66_AVAILABLE 1 +#define FM4_RTC_BREG67_AVAILABLE 1 +#define FM_RTC_BREG67_AVAILABLE 1 +#define FM4_RTC_BREG68_AVAILABLE 1 +#define FM_RTC_BREG68_AVAILABLE 1 +#define FM4_RTC_BREG69_AVAILABLE 1 +#define FM_RTC_BREG69_AVAILABLE 1 +#define FM4_RTC_BREG6A_AVAILABLE 1 +#define FM_RTC_BREG6A_AVAILABLE 1 +#define FM4_RTC_BREG6B_AVAILABLE 1 +#define FM_RTC_BREG6B_AVAILABLE 1 +#define FM4_RTC_BREG6C_AVAILABLE 1 +#define FM_RTC_BREG6C_AVAILABLE 1 +#define FM4_RTC_BREG6D_AVAILABLE 1 +#define FM_RTC_BREG6D_AVAILABLE 1 +#define FM4_RTC_BREG6E_AVAILABLE 1 +#define FM_RTC_BREG6E_AVAILABLE 1 +#define FM4_RTC_BREG6F_AVAILABLE 1 +#define FM_RTC_BREG6F_AVAILABLE 1 +#define FM4_RTC_BREG70_AVAILABLE 1 +#define FM_RTC_BREG70_AVAILABLE 1 +#define FM4_RTC_BREG71_AVAILABLE 1 +#define FM_RTC_BREG71_AVAILABLE 1 +#define FM4_RTC_BREG72_AVAILABLE 1 +#define FM_RTC_BREG72_AVAILABLE 1 +#define FM4_RTC_BREG73_AVAILABLE 1 +#define FM_RTC_BREG73_AVAILABLE 1 +#define FM4_RTC_BREG74_AVAILABLE 1 +#define FM_RTC_BREG74_AVAILABLE 1 +#define FM4_RTC_BREG75_AVAILABLE 1 +#define FM_RTC_BREG75_AVAILABLE 1 +#define FM4_RTC_BREG76_AVAILABLE 1 +#define FM_RTC_BREG76_AVAILABLE 1 +#define FM4_RTC_BREG77_AVAILABLE 1 +#define FM_RTC_BREG77_AVAILABLE 1 +#define FM4_RTC_BREG78_AVAILABLE 1 +#define FM_RTC_BREG78_AVAILABLE 1 +#define FM4_RTC_BREG79_AVAILABLE 1 +#define FM_RTC_BREG79_AVAILABLE 1 +#define FM4_RTC_BREG7A_AVAILABLE 1 +#define FM_RTC_BREG7A_AVAILABLE 1 +#define FM4_RTC_BREG7B_AVAILABLE 1 +#define FM_RTC_BREG7B_AVAILABLE 1 +#define FM4_RTC_BREG7C_AVAILABLE 1 +#define FM_RTC_BREG7C_AVAILABLE 1 +#define FM4_RTC_BREG7D_AVAILABLE 1 +#define FM_RTC_BREG7D_AVAILABLE 1 +#define FM4_RTC_BREG7E_AVAILABLE 1 +#define FM_RTC_BREG7E_AVAILABLE 1 +#define FM4_RTC_BREG7F_AVAILABLE 1 +#define FM_RTC_BREG7F_AVAILABLE 1 +#define FM4_RTC_CCB_AVAILABLE 1 +#define FM_RTC_CCB_AVAILABLE 1 +#define FM4_RTC_CCS_AVAILABLE 1 +#define FM_RTC_CCS_AVAILABLE 1 +#define FM4_RTC_EWKUP_AVAILABLE 1 +#define FM_RTC_EWKUP_AVAILABLE 1 +#define FM4_RTC_HIBRST_AVAILABLE 1 +#define FM_RTC_HIBRST_AVAILABLE 1 +#define FM4_RTC_VB_CLKDIV_AVAILABLE 1 +#define FM_RTC_VB_CLKDIV_AVAILABLE 1 +#define FM4_RTC_VBDDR_AVAILABLE 1 +#define FM_RTC_VBDDR_AVAILABLE 1 +#define FM4_RTC_VBDIR_AVAILABLE 1 +#define FM_RTC_VBDIR_AVAILABLE 1 +#define FM4_RTC_VBDOR_AVAILABLE 1 +#define FM_RTC_VBDOR_AVAILABLE 1 +#define FM4_RTC_VBPCR_AVAILABLE 1 +#define FM_RTC_VBPCR_AVAILABLE 1 +#define FM4_RTC_VBPFR_AVAILABLE 1 +#define FM_RTC_VBPFR_AVAILABLE 1 +#define FM4_RTC_VBPZR_AVAILABLE 1 +#define FM_RTC_VBPZR_AVAILABLE 1 +#define FM4_RTC_VDET_AVAILABLE 1 +#define FM_RTC_VDET_AVAILABLE 1 +#define FM4_RTC_WTCAL0_AVAILABLE 1 +#define FM_RTC_WTCAL0_AVAILABLE 1 +#define FM4_RTC_WTCAL1_AVAILABLE 1 +#define FM_RTC_WTCAL1_AVAILABLE 1 +#define FM4_RTC_WTCALEN_AVAILABLE 1 +#define FM_RTC_WTCALEN_AVAILABLE 1 +#define FM4_RTC_WTCALPRD_AVAILABLE 1 +#define FM_RTC_WTCALPRD_AVAILABLE 1 +#define FM4_RTC_WTCOSEL_AVAILABLE 1 +#define FM_RTC_WTCOSEL_AVAILABLE 1 +#define FM4_RTC_WTCR10_AVAILABLE 1 +#define FM_RTC_WTCR10_AVAILABLE 1 +#define FM4_RTC_WTCR11_AVAILABLE 1 +#define FM_RTC_WTCR11_AVAILABLE 1 +#define FM4_RTC_WTCR12_AVAILABLE 1 +#define FM_RTC_WTCR12_AVAILABLE 1 +#define FM4_RTC_WTCR13_AVAILABLE 1 +#define FM_RTC_WTCR13_AVAILABLE 1 +#define FM4_RTC_WTCR20_AVAILABLE 1 +#define FM_RTC_WTCR20_AVAILABLE 1 +#define FM4_RTC_WTCR21_AVAILABLE 1 +#define FM_RTC_WTCR21_AVAILABLE 1 +#define FM4_RTC_WTDIV_AVAILABLE 1 +#define FM_RTC_WTDIV_AVAILABLE 1 +#define FM4_RTC_WTDIVEN_AVAILABLE 1 +#define FM_RTC_WTDIVEN_AVAILABLE 1 +#define FM4_RTC_WTDR_AVAILABLE 1 +#define FM_RTC_WTDR_AVAILABLE 1 +#define FM4_RTC_WTDW_AVAILABLE 1 +#define FM_RTC_WTDW_AVAILABLE 1 +#define FM4_RTC_WTHR_AVAILABLE 1 +#define FM_RTC_WTHR_AVAILABLE 1 +#define FM4_RTC_WTMIR_AVAILABLE 1 +#define FM_RTC_WTMIR_AVAILABLE 1 +#define FM4_RTC_WTMOR_AVAILABLE 1 +#define FM_RTC_WTMOR_AVAILABLE 1 +#define FM4_RTC_WTOSCCNT_AVAILABLE 1 +#define FM_RTC_WTOSCCNT_AVAILABLE 1 +#define FM4_RTC_WTSR_AVAILABLE 1 +#define FM_RTC_WTSR_AVAILABLE 1 +#define FM4_RTC_WTTR0_AVAILABLE 1 +#define FM_RTC_WTTR0_AVAILABLE 1 +#define FM4_RTC_WTTR1_AVAILABLE 1 +#define FM_RTC_WTTR1_AVAILABLE 1 +#define FM4_RTC_WTTR2_AVAILABLE 1 +#define FM_RTC_WTTR2_AVAILABLE 1 +#define FM4_RTC_WTYR_AVAILABLE 1 +#define FM_RTC_WTYR_AVAILABLE 1 +/******************************************************************************* +* SBSSR +*******************************************************************************/ +#define FM4_SBSSR_BTSSSR_AVAILABLE 1 +#define FM_SBSSR_BTSSSR_AVAILABLE 1 +/******************************************************************************* +* SDIF +*******************************************************************************/ +#define FM4_SDIF_ADMAEST_AVAILABLE 1 +#define FM_SDIF_ADMAEST_AVAILABLE 1 +#define FM4_SDIF_AHBCFGH_AVAILABLE 1 +#define FM_SDIF_AHBCFGH_AVAILABLE 1 +#define FM4_SDIF_AHBCFGL_AVAILABLE 1 +#define FM_SDIF_AHBCFGL_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY0_AVAILABLE 1 +#define FM_SDIF_CAPBLTY0_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY1_AVAILABLE 1 +#define FM_SDIF_CAPBLTY1_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY2_AVAILABLE 1 +#define FM_SDIF_CAPBLTY2_AVAILABLE 1 +#define FM4_SDIF_CAPBLTY3_AVAILABLE 1 +#define FM_SDIF_CAPBLTY3_AVAILABLE 1 +#define FM4_SDIF_FEACEST_AVAILABLE 1 +#define FM_SDIF_FEACEST_AVAILABLE 1 +#define FM4_SDIF_MCRPCKBH_AVAILABLE 1 +#define FM_SDIF_MCRPCKBH_AVAILABLE 1 +#define FM4_SDIF_MCRPCKBL_AVAILABLE 1 +#define FM_SDIF_MCRPCKBL_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC0_AVAILABLE 1 +#define FM_SDIF_MCWIRQC0_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC1_AVAILABLE 1 +#define FM_SDIF_MCWIRQC1_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC2_AVAILABLE 1 +#define FM_SDIF_MCWIRQC2_AVAILABLE 1 +#define FM4_SDIF_MCWIRQC3_AVAILABLE 1 +#define FM_SDIF_MCWIRQC3_AVAILABLE 1 +#define FM4_SDIF_MMCSDCH_AVAILABLE 1 +#define FM_SDIF_MMCSDCH_AVAILABLE 1 +#define FM4_SDIF_MMCSDCL_AVAILABLE 1 +#define FM_SDIF_MMCSDCL_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY0_AVAILABLE 1 +#define FM_SDIF_MXCCAPY0_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY1_AVAILABLE 1 +#define FM_SDIF_MXCCAPY1_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY2_AVAILABLE 1 +#define FM_SDIF_MXCCAPY2_AVAILABLE 1 +#define FM4_SDIF_MXCCAPY3_AVAILABLE 1 +#define FM_SDIF_MXCCAPY3_AVAILABLE 1 +#define FM4_SDIF_PSWISGEH_AVAILABLE 1 +#define FM_SDIF_PSWISGEH_AVAILABLE 1 +#define FM4_SDIF_PSWISGEL_AVAILABLE 1 +#define FM_SDIF_PSWISGEL_AVAILABLE 1 +#define FM4_SDIF_PSWISTEH_AVAILABLE 1 +#define FM_SDIF_PSWISTEH_AVAILABLE 1 +#define FM4_SDIF_PSWISTEL_AVAILABLE 1 +#define FM_SDIF_PSWISTEL_AVAILABLE 1 +#define FM4_SDIF_PSWISTH_AVAILABLE 1 +#define FM_SDIF_PSWISTH_AVAILABLE 1 +#define FM4_SDIF_PSWISTL_AVAILABLE 1 +#define FM_SDIF_PSWISTL_AVAILABLE 1 +#define FM4_SDIF_SACMDEST_AVAILABLE 1 +#define FM_SDIF_SACMDEST_AVAILABLE 1 +#define FM4_SDIF_SADSA0_AVAILABLE 1 +#define FM_SDIF_SADSA0_AVAILABLE 1 +#define FM4_SDIF_SADSA1_AVAILABLE 1 +#define FM_SDIF_SADSA1_AVAILABLE 1 +#define FM4_SDIF_SADSA2_AVAILABLE 1 +#define FM_SDIF_SADSA2_AVAILABLE 1 +#define FM4_SDIF_SADSA3_AVAILABLE 1 +#define FM_SDIF_SADSA3_AVAILABLE 1 +#define FM4_SDIF_SBLCNT_AVAILABLE 1 +#define FM_SDIF_SBLCNT_AVAILABLE 1 +#define FM4_SDIF_SBLKGPCTL_AVAILABLE 1 +#define FM_SDIF_SBLKGPCTL_AVAILABLE 1 +#define FM4_SDIF_SBSIZE_AVAILABLE 1 +#define FM_SDIF_SBSIZE_AVAILABLE 1 +#define FM4_SDIF_SBUFDP_AVAILABLE 1 +#define FM_SDIF_SBUFDP_AVAILABLE 1 +#define FM4_SDIF_SCDETECS_AVAILABLE 1 +#define FM_SDIF_SCDETECS_AVAILABLE 1 +#define FM4_SDIF_SCLKCTL_AVAILABLE 1 +#define FM_SDIF_SCLKCTL_AVAILABLE 1 +#define FM4_SDIF_SCMMD_AVAILABLE 1 +#define FM_SDIF_SCMMD_AVAILABLE 1 +#define FM4_SDIF_SEINTSGE_AVAILABLE 1 +#define FM_SDIF_SEINTSGE_AVAILABLE 1 +#define FM4_SDIF_SEINTST_AVAILABLE 1 +#define FM_SDIF_SEINTST_AVAILABLE 1 +#define FM4_SDIF_SEINTSTE_AVAILABLE 1 +#define FM_SDIF_SEINTSTE_AVAILABLE 1 +#define FM4_SDIF_SFEEIST_AVAILABLE 1 +#define FM_SDIF_SFEEIST_AVAILABLE 1 +#define FM4_SDIF_SHCTL1_AVAILABLE 1 +#define FM_SDIF_SHCTL1_AVAILABLE 1 +#define FM4_SDIF_SHCTL2_AVAILABLE 1 +#define FM_SDIF_SHCTL2_AVAILABLE 1 +#define FM4_SDIF_SHCTLV_AVAILABLE 1 +#define FM_SDIF_SHCTLV_AVAILABLE 1 +#define FM4_SDIF_SNINTSGE_AVAILABLE 1 +#define FM_SDIF_SNINTSGE_AVAILABLE 1 +#define FM4_SDIF_SNINTST_AVAILABLE 1 +#define FM_SDIF_SNINTST_AVAILABLE 1 +#define FM4_SDIF_SNINTSTE_AVAILABLE 1 +#define FM_SDIF_SNINTSTE_AVAILABLE 1 +#define FM4_SDIF_SPRSTAT_AVAILABLE 1 +#define FM_SDIF_SPRSTAT_AVAILABLE 1 +#define FM4_SDIF_SPRVAL0_AVAILABLE 1 +#define FM_SDIF_SPRVAL0_AVAILABLE 1 +#define FM4_SDIF_SPRVAL1_AVAILABLE 1 +#define FM_SDIF_SPRVAL1_AVAILABLE 1 +#define FM4_SDIF_SPRVAL2_AVAILABLE 1 +#define FM_SDIF_SPRVAL2_AVAILABLE 1 +#define FM4_SDIF_SPRVAL3_AVAILABLE 1 +#define FM_SDIF_SPRVAL3_AVAILABLE 1 +#define FM4_SDIF_SPRVAL4_AVAILABLE 1 +#define FM_SDIF_SPRVAL4_AVAILABLE 1 +#define FM4_SDIF_SPRVAL5_AVAILABLE 1 +#define FM_SDIF_SPRVAL5_AVAILABLE 1 +#define FM4_SDIF_SPRVAL6_AVAILABLE 1 +#define FM_SDIF_SPRVAL6_AVAILABLE 1 +#define FM4_SDIF_SPRVAL7_AVAILABLE 1 +#define FM_SDIF_SPRVAL7_AVAILABLE 1 +#define FM4_SDIF_SPWRCTL_AVAILABLE 1 +#define FM_SDIF_SPWRCTL_AVAILABLE 1 +#define FM4_SDIF_SPWSWCH_AVAILABLE 1 +#define FM_SDIF_SPWSWCH_AVAILABLE 1 +#define FM4_SDIF_SPWSWCL_AVAILABLE 1 +#define FM_SDIF_SPWSWCL_AVAILABLE 1 +#define FM4_SDIF_SRESP0_AVAILABLE 1 +#define FM_SDIF_SRESP0_AVAILABLE 1 +#define FM4_SDIF_SRESP1_AVAILABLE 1 +#define FM_SDIF_SRESP1_AVAILABLE 1 +#define FM4_SDIF_SRESP2_AVAILABLE 1 +#define FM_SDIF_SRESP2_AVAILABLE 1 +#define FM4_SDIF_SRESP3_AVAILABLE 1 +#define FM_SDIF_SRESP3_AVAILABLE 1 +#define FM4_SDIF_SRESP4_AVAILABLE 1 +#define FM_SDIF_SRESP4_AVAILABLE 1 +#define FM4_SDIF_SRESP5_AVAILABLE 1 +#define FM_SDIF_SRESP5_AVAILABLE 1 +#define FM4_SDIF_SRESP6_AVAILABLE 1 +#define FM_SDIF_SRESP6_AVAILABLE 1 +#define FM4_SDIF_SRESP7_AVAILABLE 1 +#define FM_SDIF_SRESP7_AVAILABLE 1 +#define FM4_SDIF_SSA1_AVAILABLE 1 +#define FM_SDIF_SSA1_AVAILABLE 1 +#define FM4_SDIF_SSA2_AVAILABLE 1 +#define FM_SDIF_SSA2_AVAILABLE 1 +#define FM4_SDIF_SSHBCTLH_AVAILABLE 1 +#define FM_SDIF_SSHBCTLH_AVAILABLE 1 +#define FM4_SDIF_SSHBCTLL_AVAILABLE 1 +#define FM_SDIF_SSHBCTLL_AVAILABLE 1 +#define FM4_SDIF_SSLIST_AVAILABLE 1 +#define FM_SDIF_SSLIST_AVAILABLE 1 +#define FM4_SDIF_SSRST_AVAILABLE 1 +#define FM_SDIF_SSRST_AVAILABLE 1 +#define FM4_SDIF_STOCTL_AVAILABLE 1 +#define FM_SDIF_STOCTL_AVAILABLE 1 +#define FM4_SDIF_STRSFMD_AVAILABLE 1 +#define FM_SDIF_STRSFMD_AVAILABLE 1 +#define FM4_SDIF_STUNSETH_AVAILABLE 1 +#define FM_SDIF_STUNSETH_AVAILABLE 1 +#define FM4_SDIF_STUNSETL_AVAILABLE 1 +#define FM_SDIF_STUNSETL_AVAILABLE 1 +#define FM4_SDIF_STUNSTH_AVAILABLE 1 +#define FM_SDIF_STUNSTH_AVAILABLE 1 +#define FM4_SDIF_STUNSTL_AVAILABLE 1 +#define FM_SDIF_STUNSTL_AVAILABLE 1 +#define FM4_SDIF_SWKUPCTL_AVAILABLE 1 +#define FM_SDIF_SWKUPCTL_AVAILABLE 1 +/******************************************************************************* +* SWWDT +*******************************************************************************/ +#define FM4_SWWDT_WDOGCONTROL_AVAILABLE 1 +#define FM_SWWDT_WDOGCONTROL_AVAILABLE 1 +#define FM4_SWWDT_WDOGINTCLR_AVAILABLE 1 +#define FM_SWWDT_WDOGINTCLR_AVAILABLE 1 +#define FM4_SWWDT_WDOGLOAD_AVAILABLE 1 +#define FM_SWWDT_WDOGLOAD_AVAILABLE 1 +#define FM4_SWWDT_WDOGLOCK_AVAILABLE 1 +#define FM_SWWDT_WDOGLOCK_AVAILABLE 1 +#define FM4_SWWDT_WDOGRIS_AVAILABLE 1 +#define FM_SWWDT_WDOGRIS_AVAILABLE 1 +#define FM4_SWWDT_WDOGSPMC_AVAILABLE 1 +#define FM_SWWDT_WDOGSPMC_AVAILABLE 1 +#define FM4_SWWDT_WDOGVALUE_AVAILABLE 1 +#define FM_SWWDT_WDOGVALUE_AVAILABLE 1 +/******************************************************************************* +* UNIQUE_ID +*******************************************************************************/ +#define FM4_UNIQUE_ID_UIDR0_AVAILABLE 1 +#define FM_UNIQUE_ID_UIDR0_AVAILABLE 1 +#define FM4_UNIQUE_ID_UIDR1_AVAILABLE 1 +#define FM_UNIQUE_ID_UIDR1_AVAILABLE 1 +/******************************************************************************* +* USB0 +*******************************************************************************/ +#define FM4_USB_EP0C_AVAILABLE 1 +#define FM_USB_EP0C_AVAILABLE 1 +#define FM4_USB_EP0DT_AVAILABLE 1 +#define FM_USB_EP0DT_AVAILABLE 1 +#define FM4_USB_EP0IS_AVAILABLE 1 +#define FM_USB_EP0IS_AVAILABLE 1 +#define FM4_USB_EP0OS_AVAILABLE 1 +#define FM_USB_EP0OS_AVAILABLE 1 +#define FM4_USB_EP1C_AVAILABLE 1 +#define FM_USB_EP1C_AVAILABLE 1 +#define FM4_USB_EP1DT_AVAILABLE 1 +#define FM_USB_EP1DT_AVAILABLE 1 +#define FM4_USB_EP1S_AVAILABLE 1 +#define FM_USB_EP1S_AVAILABLE 1 +#define FM4_USB_EP2C_AVAILABLE 1 +#define FM_USB_EP2C_AVAILABLE 1 +#define FM4_USB_EP2DT_AVAILABLE 1 +#define FM_USB_EP2DT_AVAILABLE 1 +#define FM4_USB_EP2S_AVAILABLE 1 +#define FM_USB_EP2S_AVAILABLE 1 +#define FM4_USB_EP3C_AVAILABLE 1 +#define FM_USB_EP3C_AVAILABLE 1 +#define FM4_USB_EP3DT_AVAILABLE 1 +#define FM_USB_EP3DT_AVAILABLE 1 +#define FM4_USB_EP3S_AVAILABLE 1 +#define FM_USB_EP3S_AVAILABLE 1 +#define FM4_USB_EP4C_AVAILABLE 1 +#define FM_USB_EP4C_AVAILABLE 1 +#define FM4_USB_EP4DT_AVAILABLE 1 +#define FM_USB_EP4DT_AVAILABLE 1 +#define FM4_USB_EP4S_AVAILABLE 1 +#define FM_USB_EP4S_AVAILABLE 1 +#define FM4_USB_EP5C_AVAILABLE 1 +#define FM_USB_EP5C_AVAILABLE 1 +#define FM4_USB_EP5DT_AVAILABLE 1 +#define FM_USB_EP5DT_AVAILABLE 1 +#define FM4_USB_EP5S_AVAILABLE 1 +#define FM_USB_EP5S_AVAILABLE 1 +#define FM4_USB_HADR_AVAILABLE 1 +#define FM_USB_HADR_AVAILABLE 1 +#define FM4_USB_HCNT_AVAILABLE 1 +#define FM_USB_HCNT_AVAILABLE 1 +#define FM4_USB_HEOF_AVAILABLE 1 +#define FM_USB_HEOF_AVAILABLE 1 +#define FM4_USB_HERR_AVAILABLE 1 +#define FM_USB_HERR_AVAILABLE 1 +#define FM4_USB_HFCOMP_AVAILABLE 1 +#define FM_USB_HFCOMP_AVAILABLE 1 +#define FM4_USB_HFRAME_AVAILABLE 1 +#define FM_USB_HFRAME_AVAILABLE 1 +#define FM4_USB_HIRQ_AVAILABLE 1 +#define FM_USB_HIRQ_AVAILABLE 1 +#define FM4_USB_HRTIMER_AVAILABLE 1 +#define FM_USB_HRTIMER_AVAILABLE 1 +#define FM4_USB_HRTIMER2_AVAILABLE 1 +#define FM_USB_HRTIMER2_AVAILABLE 1 +#define FM4_USB_HSTATE_AVAILABLE 1 +#define FM_USB_HSTATE_AVAILABLE 1 +#define FM4_USB_HTOKEN_AVAILABLE 1 +#define FM_USB_HTOKEN_AVAILABLE 1 +#define FM4_USB_TMSP_AVAILABLE 1 +#define FM_USB_TMSP_AVAILABLE 1 +#define FM4_USB_UDCC_AVAILABLE 1 +#define FM_USB_UDCC_AVAILABLE 1 +#define FM4_USB_UDCIE_AVAILABLE 1 +#define FM_USB_UDCIE_AVAILABLE 1 +#define FM4_USB_UDCS_AVAILABLE 1 +#define FM_USB_UDCS_AVAILABLE 1 +/******************************************************************************* +* USBCLK +*******************************************************************************/ +#define FM4_USBCLK_UCCR_AVAILABLE 1 +#define FM_USBCLK_UCCR_AVAILABLE 1 +#define FM4_USBCLK_UP_STR_AVAILABLE 1 +#define FM_USBCLK_UP_STR_AVAILABLE 1 +#define FM4_USBCLK_UPCR1_AVAILABLE 1 +#define FM_USBCLK_UPCR1_AVAILABLE 1 +#define FM4_USBCLK_UPCR2_AVAILABLE 1 +#define FM_USBCLK_UPCR2_AVAILABLE 1 +#define FM4_USBCLK_UPCR3_AVAILABLE 1 +#define FM_USBCLK_UPCR3_AVAILABLE 1 +#define FM4_USBCLK_UPCR4_AVAILABLE 1 +#define FM_USBCLK_UPCR4_AVAILABLE 1 +#define FM4_USBCLK_UPCR5_AVAILABLE 1 +#define FM_USBCLK_UPCR5_AVAILABLE 1 +#define FM4_USBCLK_UPINT_CLR_AVAILABLE 1 +#define FM_USBCLK_UPINT_CLR_AVAILABLE 1 +#define FM4_USBCLK_UPINT_ENR_AVAILABLE 1 +#define FM_USBCLK_UPINT_ENR_AVAILABLE 1 +#define FM4_USBCLK_UPINT_STR_AVAILABLE 1 +#define FM_USBCLK_UPINT_STR_AVAILABLE 1 +#define FM4_USBCLK_USBEN0_AVAILABLE 1 +#define FM_USBCLK_USBEN0_AVAILABLE 1 +#define FM4_USBCLK_USBEN1_AVAILABLE 1 +#define FM_USBCLK_USBEN1_AVAILABLE 1 +/******************************************************************************* +* WC +*******************************************************************************/ +#define FM4_WC_CLK_EN_AVAILABLE 1 +#define FM_WC_CLK_EN_AVAILABLE 1 +#define FM4_WC_CLK_SEL_AVAILABLE 1 +#define FM_WC_CLK_SEL_AVAILABLE 1 +#define FM4_WC_WCCR_AVAILABLE 1 +#define FM_WC_WCCR_AVAILABLE 1 +#define FM4_WC_WCRD_AVAILABLE 1 +#define FM_WC_WCRD_AVAILABLE 1 +#define FM4_WC_WCRL_AVAILABLE 1 +#define FM_WC_WCRL_AVAILABLE 1 + +/******************************************************************************* +* Peripheral Bit Band Alias declaration +*******************************************************************************/ +/******************************************************************************* +* ADC Registers ADC0 +* Bitband Section +*******************************************************************************/ +#define bFM_ADC0_ADCEN_ENBL *((volatile uint8_t *)(0x424E0780UL)) +#define bFM4_ADC0_ADCEN_ENBL *((volatile uint8_t *)(0x424E0780UL)) +#define bFM_ADC0_ADCEN_READY *((volatile uint8_t *)(0x424E0784UL)) +#define bFM4_ADC0_ADCEN_READY *((volatile uint8_t *)(0x424E0784UL)) + +#define bFM_ADC0_ADCR_OVRIE *((volatile uint8_t *)(0x424E0020UL)) +#define bFM4_ADC0_ADCR_OVRIE *((volatile uint8_t *)(0x424E0020UL)) +#define bFM_ADC0_ADCR_CMPIE *((volatile uint8_t *)(0x424E0024UL)) +#define bFM4_ADC0_ADCR_CMPIE *((volatile uint8_t *)(0x424E0024UL)) +#define bFM_ADC0_ADCR_PCIE *((volatile uint8_t *)(0x424E0028UL)) +#define bFM4_ADC0_ADCR_PCIE *((volatile uint8_t *)(0x424E0028UL)) +#define bFM_ADC0_ADCR_SCIE *((volatile uint8_t *)(0x424E002CUL)) +#define bFM4_ADC0_ADCR_SCIE *((volatile uint8_t *)(0x424E002CUL)) +#define bFM_ADC0_ADCR_CMPIF *((volatile uint8_t *)(0x424E0034UL)) +#define bFM4_ADC0_ADCR_CMPIF *((volatile uint8_t *)(0x424E0034UL)) +#define bFM_ADC0_ADCR_PCIF *((volatile uint8_t *)(0x424E0038UL)) +#define bFM4_ADC0_ADCR_PCIF *((volatile uint8_t *)(0x424E0038UL)) +#define bFM_ADC0_ADCR_SCIF *((volatile uint8_t *)(0x424E003CUL)) +#define bFM4_ADC0_ADCR_SCIF *((volatile uint8_t *)(0x424E003CUL)) + +#define bFM_ADC0_ADSR_SCS *((volatile uint8_t *)(0x424E0000UL)) +#define bFM4_ADC0_ADSR_SCS *((volatile uint8_t *)(0x424E0000UL)) +#define bFM_ADC0_ADSR_PCS *((volatile uint8_t *)(0x424E0004UL)) +#define bFM4_ADC0_ADSR_PCS *((volatile uint8_t *)(0x424E0004UL)) +#define bFM_ADC0_ADSR_PCNS *((volatile uint8_t *)(0x424E0008UL)) +#define bFM4_ADC0_ADSR_PCNS *((volatile uint8_t *)(0x424E0008UL)) +#define bFM_ADC0_ADSR_FDAS *((volatile uint8_t *)(0x424E0018UL)) +#define bFM4_ADC0_ADSR_FDAS *((volatile uint8_t *)(0x424E0018UL)) +#define bFM_ADC0_ADSR_ADSTP *((volatile uint8_t *)(0x424E001CUL)) +#define bFM4_ADC0_ADSR_ADSTP *((volatile uint8_t *)(0x424E001CUL)) + +#define bFM_ADC0_ADSS01_TS0 *((volatile uint8_t *)(0x424E0580UL)) +#define bFM4_ADC0_ADSS01_TS0 *((volatile uint8_t *)(0x424E0580UL)) +#define bFM_ADC0_ADSS01_TS1 *((volatile uint8_t *)(0x424E0584UL)) +#define bFM4_ADC0_ADSS01_TS1 *((volatile uint8_t *)(0x424E0584UL)) +#define bFM_ADC0_ADSS01_TS2 *((volatile uint8_t *)(0x424E0588UL)) +#define bFM4_ADC0_ADSS01_TS2 *((volatile uint8_t *)(0x424E0588UL)) +#define bFM_ADC0_ADSS01_TS3 *((volatile uint8_t *)(0x424E058CUL)) +#define bFM4_ADC0_ADSS01_TS3 *((volatile uint8_t *)(0x424E058CUL)) +#define bFM_ADC0_ADSS01_TS4 *((volatile uint8_t *)(0x424E0590UL)) +#define bFM4_ADC0_ADSS01_TS4 *((volatile uint8_t *)(0x424E0590UL)) +#define bFM_ADC0_ADSS01_TS5 *((volatile uint8_t *)(0x424E0594UL)) +#define bFM4_ADC0_ADSS01_TS5 *((volatile uint8_t *)(0x424E0594UL)) +#define bFM_ADC0_ADSS01_TS6 *((volatile uint8_t *)(0x424E0598UL)) +#define bFM4_ADC0_ADSS01_TS6 *((volatile uint8_t *)(0x424E0598UL)) +#define bFM_ADC0_ADSS01_TS7 *((volatile uint8_t *)(0x424E059CUL)) +#define bFM4_ADC0_ADSS01_TS7 *((volatile uint8_t *)(0x424E059CUL)) +#define bFM_ADC0_ADSS01_TS8 *((volatile uint8_t *)(0x424E05A0UL)) +#define bFM4_ADC0_ADSS01_TS8 *((volatile uint8_t *)(0x424E05A0UL)) +#define bFM_ADC0_ADSS01_TS9 *((volatile uint8_t *)(0x424E05A4UL)) +#define bFM4_ADC0_ADSS01_TS9 *((volatile uint8_t *)(0x424E05A4UL)) +#define bFM_ADC0_ADSS01_TS10 *((volatile uint8_t *)(0x424E05A8UL)) +#define bFM4_ADC0_ADSS01_TS10 *((volatile uint8_t *)(0x424E05A8UL)) +#define bFM_ADC0_ADSS01_TS11 *((volatile uint8_t *)(0x424E05ACUL)) +#define bFM4_ADC0_ADSS01_TS11 *((volatile uint8_t *)(0x424E05ACUL)) +#define bFM_ADC0_ADSS01_TS12 *((volatile uint8_t *)(0x424E05B0UL)) +#define bFM4_ADC0_ADSS01_TS12 *((volatile uint8_t *)(0x424E05B0UL)) +#define bFM_ADC0_ADSS01_TS13 *((volatile uint8_t *)(0x424E05B4UL)) +#define bFM4_ADC0_ADSS01_TS13 *((volatile uint8_t *)(0x424E05B4UL)) +#define bFM_ADC0_ADSS01_TS14 *((volatile uint8_t *)(0x424E05B8UL)) +#define bFM4_ADC0_ADSS01_TS14 *((volatile uint8_t *)(0x424E05B8UL)) +#define bFM_ADC0_ADSS01_TS15 *((volatile uint8_t *)(0x424E05BCUL)) +#define bFM4_ADC0_ADSS01_TS15 *((volatile uint8_t *)(0x424E05BCUL)) + +#define bFM_ADC0_ADSS23_TS16 *((volatile uint8_t *)(0x424E0500UL)) +#define bFM4_ADC0_ADSS23_TS16 *((volatile uint8_t *)(0x424E0500UL)) +#define bFM_ADC0_ADSS23_TS17 *((volatile uint8_t *)(0x424E0504UL)) +#define bFM4_ADC0_ADSS23_TS17 *((volatile uint8_t *)(0x424E0504UL)) +#define bFM_ADC0_ADSS23_TS18 *((volatile uint8_t *)(0x424E0508UL)) +#define bFM4_ADC0_ADSS23_TS18 *((volatile uint8_t *)(0x424E0508UL)) +#define bFM_ADC0_ADSS23_TS19 *((volatile uint8_t *)(0x424E050CUL)) +#define bFM4_ADC0_ADSS23_TS19 *((volatile uint8_t *)(0x424E050CUL)) +#define bFM_ADC0_ADSS23_TS20 *((volatile uint8_t *)(0x424E0510UL)) +#define bFM4_ADC0_ADSS23_TS20 *((volatile uint8_t *)(0x424E0510UL)) +#define bFM_ADC0_ADSS23_TS21 *((volatile uint8_t *)(0x424E0514UL)) +#define bFM4_ADC0_ADSS23_TS21 *((volatile uint8_t *)(0x424E0514UL)) +#define bFM_ADC0_ADSS23_TS22 *((volatile uint8_t *)(0x424E0518UL)) +#define bFM4_ADC0_ADSS23_TS22 *((volatile uint8_t *)(0x424E0518UL)) +#define bFM_ADC0_ADSS23_TS23 *((volatile uint8_t *)(0x424E051CUL)) +#define bFM4_ADC0_ADSS23_TS23 *((volatile uint8_t *)(0x424E051CUL)) +#define bFM_ADC0_ADSS23_TS24 *((volatile uint8_t *)(0x424E0520UL)) +#define bFM4_ADC0_ADSS23_TS24 *((volatile uint8_t *)(0x424E0520UL)) +#define bFM_ADC0_ADSS23_TS25 *((volatile uint8_t *)(0x424E0524UL)) +#define bFM4_ADC0_ADSS23_TS25 *((volatile uint8_t *)(0x424E0524UL)) +#define bFM_ADC0_ADSS23_TS26 *((volatile uint8_t *)(0x424E0528UL)) +#define bFM4_ADC0_ADSS23_TS26 *((volatile uint8_t *)(0x424E0528UL)) +#define bFM_ADC0_ADSS23_TS27 *((volatile uint8_t *)(0x424E052CUL)) +#define bFM4_ADC0_ADSS23_TS27 *((volatile uint8_t *)(0x424E052CUL)) +#define bFM_ADC0_ADSS23_TS28 *((volatile uint8_t *)(0x424E0530UL)) +#define bFM4_ADC0_ADSS23_TS28 *((volatile uint8_t *)(0x424E0530UL)) +#define bFM_ADC0_ADSS23_TS29 *((volatile uint8_t *)(0x424E0534UL)) +#define bFM4_ADC0_ADSS23_TS29 *((volatile uint8_t *)(0x424E0534UL)) +#define bFM_ADC0_ADSS23_TS30 *((volatile uint8_t *)(0x424E0538UL)) +#define bFM4_ADC0_ADSS23_TS30 *((volatile uint8_t *)(0x424E0538UL)) +#define bFM_ADC0_ADSS23_TS31 *((volatile uint8_t *)(0x424E053CUL)) +#define bFM4_ADC0_ADSS23_TS31 *((volatile uint8_t *)(0x424E053CUL)) + +#define bFM_ADC0_CALSR_CLBEN *((volatile uint8_t *)(0x424E0820UL)) +#define bFM4_ADC0_CALSR_CLBEN *((volatile uint8_t *)(0x424E0820UL)) + +#define bFM_ADC0_CMPCR_CMD0 *((volatile uint8_t *)(0x424E0494UL)) +#define bFM4_ADC0_CMPCR_CMD0 *((volatile uint8_t *)(0x424E0494UL)) +#define bFM_ADC0_CMPCR_CMD1 *((volatile uint8_t *)(0x424E0498UL)) +#define bFM4_ADC0_CMPCR_CMD1 *((volatile uint8_t *)(0x424E0498UL)) +#define bFM_ADC0_CMPCR_CMPEN *((volatile uint8_t *)(0x424E049CUL)) +#define bFM4_ADC0_CMPCR_CMPEN *((volatile uint8_t *)(0x424E049CUL)) + +#define bFM_ADC0_PCCR_PSTR *((volatile uint8_t *)(0x424E0320UL)) +#define bFM4_ADC0_PCCR_PSTR *((volatile uint8_t *)(0x424E0320UL)) +#define bFM_ADC0_PCCR_PHEN *((volatile uint8_t *)(0x424E0324UL)) +#define bFM4_ADC0_PCCR_PHEN *((volatile uint8_t *)(0x424E0324UL)) +#define bFM_ADC0_PCCR_PEEN *((volatile uint8_t *)(0x424E0328UL)) +#define bFM4_ADC0_PCCR_PEEN *((volatile uint8_t *)(0x424E0328UL)) +#define bFM_ADC0_PCCR_ESCE *((volatile uint8_t *)(0x424E032CUL)) +#define bFM4_ADC0_PCCR_ESCE *((volatile uint8_t *)(0x424E032CUL)) +#define bFM_ADC0_PCCR_PFCLR *((volatile uint8_t *)(0x424E0330UL)) +#define bFM4_ADC0_PCCR_PFCLR *((volatile uint8_t *)(0x424E0330UL)) +#define bFM_ADC0_PCCR_POVR *((volatile uint8_t *)(0x424E0334UL)) +#define bFM4_ADC0_PCCR_POVR *((volatile uint8_t *)(0x424E0334UL)) +#define bFM_ADC0_PCCR_PFUL *((volatile uint8_t *)(0x424E0338UL)) +#define bFM4_ADC0_PCCR_PFUL *((volatile uint8_t *)(0x424E0338UL)) +#define bFM_ADC0_PCCR_PEMP *((volatile uint8_t *)(0x424E033CUL)) +#define bFM4_ADC0_PCCR_PEMP *((volatile uint8_t *)(0x424E033CUL)) + +#define bFM_ADC0_PCFD_INVL *((volatile uint8_t *)(0x424E03B0UL)) +#define bFM4_ADC0_PCFD_INVL *((volatile uint8_t *)(0x424E03B0UL)) + +#define bFM_ADC0_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E03B0UL)) +#define bFM4_ADC0_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E03B0UL)) + +#define bFM_ADC0_SCCR_SSTR *((volatile uint8_t *)(0x424E0120UL)) +#define bFM4_ADC0_SCCR_SSTR *((volatile uint8_t *)(0x424E0120UL)) +#define bFM_ADC0_SCCR_SHEN *((volatile uint8_t *)(0x424E0124UL)) +#define bFM4_ADC0_SCCR_SHEN *((volatile uint8_t *)(0x424E0124UL)) +#define bFM_ADC0_SCCR_RPT *((volatile uint8_t *)(0x424E0128UL)) +#define bFM4_ADC0_SCCR_RPT *((volatile uint8_t *)(0x424E0128UL)) +#define bFM_ADC0_SCCR_SFCLR *((volatile uint8_t *)(0x424E0130UL)) +#define bFM4_ADC0_SCCR_SFCLR *((volatile uint8_t *)(0x424E0130UL)) +#define bFM_ADC0_SCCR_SOVR *((volatile uint8_t *)(0x424E0134UL)) +#define bFM4_ADC0_SCCR_SOVR *((volatile uint8_t *)(0x424E0134UL)) +#define bFM_ADC0_SCCR_SFUL *((volatile uint8_t *)(0x424E0138UL)) +#define bFM4_ADC0_SCCR_SFUL *((volatile uint8_t *)(0x424E0138UL)) +#define bFM_ADC0_SCCR_SEMP *((volatile uint8_t *)(0x424E013CUL)) +#define bFM4_ADC0_SCCR_SEMP *((volatile uint8_t *)(0x424E013CUL)) + +#define bFM_ADC0_SCFD_INVL *((volatile uint8_t *)(0x424E01B0UL)) +#define bFM4_ADC0_SCFD_INVL *((volatile uint8_t *)(0x424E01B0UL)) + +#define bFM_ADC0_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E01B0UL)) +#define bFM4_ADC0_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E01B0UL)) + +#define bFM_ADC0_SCIS01_AN0 *((volatile uint8_t *)(0x424E0280UL)) +#define bFM4_ADC0_SCIS01_AN0 *((volatile uint8_t *)(0x424E0280UL)) +#define bFM_ADC0_SCIS01_AN1 *((volatile uint8_t *)(0x424E0284UL)) +#define bFM4_ADC0_SCIS01_AN1 *((volatile uint8_t *)(0x424E0284UL)) +#define bFM_ADC0_SCIS01_AN2 *((volatile uint8_t *)(0x424E0288UL)) +#define bFM4_ADC0_SCIS01_AN2 *((volatile uint8_t *)(0x424E0288UL)) +#define bFM_ADC0_SCIS01_AN3 *((volatile uint8_t *)(0x424E028CUL)) +#define bFM4_ADC0_SCIS01_AN3 *((volatile uint8_t *)(0x424E028CUL)) +#define bFM_ADC0_SCIS01_AN4 *((volatile uint8_t *)(0x424E0290UL)) +#define bFM4_ADC0_SCIS01_AN4 *((volatile uint8_t *)(0x424E0290UL)) +#define bFM_ADC0_SCIS01_AN5 *((volatile uint8_t *)(0x424E0294UL)) +#define bFM4_ADC0_SCIS01_AN5 *((volatile uint8_t *)(0x424E0294UL)) +#define bFM_ADC0_SCIS01_AN6 *((volatile uint8_t *)(0x424E0298UL)) +#define bFM4_ADC0_SCIS01_AN6 *((volatile uint8_t *)(0x424E0298UL)) +#define bFM_ADC0_SCIS01_AN7 *((volatile uint8_t *)(0x424E029CUL)) +#define bFM4_ADC0_SCIS01_AN7 *((volatile uint8_t *)(0x424E029CUL)) +#define bFM_ADC0_SCIS01_AN8 *((volatile uint8_t *)(0x424E02A0UL)) +#define bFM4_ADC0_SCIS01_AN8 *((volatile uint8_t *)(0x424E02A0UL)) +#define bFM_ADC0_SCIS01_AN9 *((volatile uint8_t *)(0x424E02A4UL)) +#define bFM4_ADC0_SCIS01_AN9 *((volatile uint8_t *)(0x424E02A4UL)) +#define bFM_ADC0_SCIS01_AN10 *((volatile uint8_t *)(0x424E02A8UL)) +#define bFM4_ADC0_SCIS01_AN10 *((volatile uint8_t *)(0x424E02A8UL)) +#define bFM_ADC0_SCIS01_AN11 *((volatile uint8_t *)(0x424E02ACUL)) +#define bFM4_ADC0_SCIS01_AN11 *((volatile uint8_t *)(0x424E02ACUL)) +#define bFM_ADC0_SCIS01_AN12 *((volatile uint8_t *)(0x424E02B0UL)) +#define bFM4_ADC0_SCIS01_AN12 *((volatile uint8_t *)(0x424E02B0UL)) +#define bFM_ADC0_SCIS01_AN13 *((volatile uint8_t *)(0x424E02B4UL)) +#define bFM4_ADC0_SCIS01_AN13 *((volatile uint8_t *)(0x424E02B4UL)) +#define bFM_ADC0_SCIS01_AN14 *((volatile uint8_t *)(0x424E02B8UL)) +#define bFM4_ADC0_SCIS01_AN14 *((volatile uint8_t *)(0x424E02B8UL)) +#define bFM_ADC0_SCIS01_AN15 *((volatile uint8_t *)(0x424E02BCUL)) +#define bFM4_ADC0_SCIS01_AN15 *((volatile uint8_t *)(0x424E02BCUL)) + +#define bFM_ADC0_SCIS23_AN16 *((volatile uint8_t *)(0x424E0200UL)) +#define bFM4_ADC0_SCIS23_AN16 *((volatile uint8_t *)(0x424E0200UL)) +#define bFM_ADC0_SCIS23_AN17 *((volatile uint8_t *)(0x424E0204UL)) +#define bFM4_ADC0_SCIS23_AN17 *((volatile uint8_t *)(0x424E0204UL)) +#define bFM_ADC0_SCIS23_AN18 *((volatile uint8_t *)(0x424E0208UL)) +#define bFM4_ADC0_SCIS23_AN18 *((volatile uint8_t *)(0x424E0208UL)) +#define bFM_ADC0_SCIS23_AN19 *((volatile uint8_t *)(0x424E020CUL)) +#define bFM4_ADC0_SCIS23_AN19 *((volatile uint8_t *)(0x424E020CUL)) +#define bFM_ADC0_SCIS23_AN20 *((volatile uint8_t *)(0x424E0210UL)) +#define bFM4_ADC0_SCIS23_AN20 *((volatile uint8_t *)(0x424E0210UL)) +#define bFM_ADC0_SCIS23_AN21 *((volatile uint8_t *)(0x424E0214UL)) +#define bFM4_ADC0_SCIS23_AN21 *((volatile uint8_t *)(0x424E0214UL)) +#define bFM_ADC0_SCIS23_AN22 *((volatile uint8_t *)(0x424E0218UL)) +#define bFM4_ADC0_SCIS23_AN22 *((volatile uint8_t *)(0x424E0218UL)) +#define bFM_ADC0_SCIS23_AN23 *((volatile uint8_t *)(0x424E021CUL)) +#define bFM4_ADC0_SCIS23_AN23 *((volatile uint8_t *)(0x424E021CUL)) +#define bFM_ADC0_SCIS23_AN24 *((volatile uint8_t *)(0x424E0220UL)) +#define bFM4_ADC0_SCIS23_AN24 *((volatile uint8_t *)(0x424E0220UL)) +#define bFM_ADC0_SCIS23_AN25 *((volatile uint8_t *)(0x424E0224UL)) +#define bFM4_ADC0_SCIS23_AN25 *((volatile uint8_t *)(0x424E0224UL)) +#define bFM_ADC0_SCIS23_AN26 *((volatile uint8_t *)(0x424E0228UL)) +#define bFM4_ADC0_SCIS23_AN26 *((volatile uint8_t *)(0x424E0228UL)) +#define bFM_ADC0_SCIS23_AN27 *((volatile uint8_t *)(0x424E022CUL)) +#define bFM4_ADC0_SCIS23_AN27 *((volatile uint8_t *)(0x424E022CUL)) +#define bFM_ADC0_SCIS23_AN28 *((volatile uint8_t *)(0x424E0230UL)) +#define bFM4_ADC0_SCIS23_AN28 *((volatile uint8_t *)(0x424E0230UL)) +#define bFM_ADC0_SCIS23_AN29 *((volatile uint8_t *)(0x424E0234UL)) +#define bFM4_ADC0_SCIS23_AN29 *((volatile uint8_t *)(0x424E0234UL)) +#define bFM_ADC0_SCIS23_AN30 *((volatile uint8_t *)(0x424E0238UL)) +#define bFM4_ADC0_SCIS23_AN30 *((volatile uint8_t *)(0x424E0238UL)) +#define bFM_ADC0_SCIS23_AN31 *((volatile uint8_t *)(0x424E023CUL)) +#define bFM4_ADC0_SCIS23_AN31 *((volatile uint8_t *)(0x424E023CUL)) + +#define bFM_ADC0_WCMPCR_RCOE *((volatile uint8_t *)(0x424E0988UL)) +#define bFM4_ADC0_WCMPCR_RCOE *((volatile uint8_t *)(0x424E0988UL)) +#define bFM_ADC0_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E098CUL)) +#define bFM4_ADC0_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E098CUL)) +#define bFM_ADC0_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E0990UL)) +#define bFM4_ADC0_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E0990UL)) + +#define bFM_ADC0_WCMPSR_WCMD *((volatile uint8_t *)(0x424E09B4UL)) +#define bFM4_ADC0_WCMPSR_WCMD *((volatile uint8_t *)(0x424E09B4UL)) + +#define bFM_ADC0_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E0900UL)) +#define bFM4_ADC0_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E0900UL)) + +#define bFM_ADC0_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E0880UL)) +#define bFM4_ADC0_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E0880UL)) + + +/******************************************************************************* +* ADC Registers ADC1 +* Bitband Section +*******************************************************************************/ +#define bFM_ADC1_ADCEN_ENBL *((volatile uint8_t *)(0x424E2780UL)) +#define bFM4_ADC1_ADCEN_ENBL *((volatile uint8_t *)(0x424E2780UL)) +#define bFM_ADC1_ADCEN_READY *((volatile uint8_t *)(0x424E2784UL)) +#define bFM4_ADC1_ADCEN_READY *((volatile uint8_t *)(0x424E2784UL)) + +#define bFM_ADC1_ADCR_OVRIE *((volatile uint8_t *)(0x424E2020UL)) +#define bFM4_ADC1_ADCR_OVRIE *((volatile uint8_t *)(0x424E2020UL)) +#define bFM_ADC1_ADCR_CMPIE *((volatile uint8_t *)(0x424E2024UL)) +#define bFM4_ADC1_ADCR_CMPIE *((volatile uint8_t *)(0x424E2024UL)) +#define bFM_ADC1_ADCR_PCIE *((volatile uint8_t *)(0x424E2028UL)) +#define bFM4_ADC1_ADCR_PCIE *((volatile uint8_t *)(0x424E2028UL)) +#define bFM_ADC1_ADCR_SCIE *((volatile uint8_t *)(0x424E202CUL)) +#define bFM4_ADC1_ADCR_SCIE *((volatile uint8_t *)(0x424E202CUL)) +#define bFM_ADC1_ADCR_CMPIF *((volatile uint8_t *)(0x424E2034UL)) +#define bFM4_ADC1_ADCR_CMPIF *((volatile uint8_t *)(0x424E2034UL)) +#define bFM_ADC1_ADCR_PCIF *((volatile uint8_t *)(0x424E2038UL)) +#define bFM4_ADC1_ADCR_PCIF *((volatile uint8_t *)(0x424E2038UL)) +#define bFM_ADC1_ADCR_SCIF *((volatile uint8_t *)(0x424E203CUL)) +#define bFM4_ADC1_ADCR_SCIF *((volatile uint8_t *)(0x424E203CUL)) + +#define bFM_ADC1_ADSR_SCS *((volatile uint8_t *)(0x424E2000UL)) +#define bFM4_ADC1_ADSR_SCS *((volatile uint8_t *)(0x424E2000UL)) +#define bFM_ADC1_ADSR_PCS *((volatile uint8_t *)(0x424E2004UL)) +#define bFM4_ADC1_ADSR_PCS *((volatile uint8_t *)(0x424E2004UL)) +#define bFM_ADC1_ADSR_PCNS *((volatile uint8_t *)(0x424E2008UL)) +#define bFM4_ADC1_ADSR_PCNS *((volatile uint8_t *)(0x424E2008UL)) +#define bFM_ADC1_ADSR_FDAS *((volatile uint8_t *)(0x424E2018UL)) +#define bFM4_ADC1_ADSR_FDAS *((volatile uint8_t *)(0x424E2018UL)) +#define bFM_ADC1_ADSR_ADSTP *((volatile uint8_t *)(0x424E201CUL)) +#define bFM4_ADC1_ADSR_ADSTP *((volatile uint8_t *)(0x424E201CUL)) + +#define bFM_ADC1_ADSS01_TS0 *((volatile uint8_t *)(0x424E2580UL)) +#define bFM4_ADC1_ADSS01_TS0 *((volatile uint8_t *)(0x424E2580UL)) +#define bFM_ADC1_ADSS01_TS1 *((volatile uint8_t *)(0x424E2584UL)) +#define bFM4_ADC1_ADSS01_TS1 *((volatile uint8_t *)(0x424E2584UL)) +#define bFM_ADC1_ADSS01_TS2 *((volatile uint8_t *)(0x424E2588UL)) +#define bFM4_ADC1_ADSS01_TS2 *((volatile uint8_t *)(0x424E2588UL)) +#define bFM_ADC1_ADSS01_TS3 *((volatile uint8_t *)(0x424E258CUL)) +#define bFM4_ADC1_ADSS01_TS3 *((volatile uint8_t *)(0x424E258CUL)) +#define bFM_ADC1_ADSS01_TS4 *((volatile uint8_t *)(0x424E2590UL)) +#define bFM4_ADC1_ADSS01_TS4 *((volatile uint8_t *)(0x424E2590UL)) +#define bFM_ADC1_ADSS01_TS5 *((volatile uint8_t *)(0x424E2594UL)) +#define bFM4_ADC1_ADSS01_TS5 *((volatile uint8_t *)(0x424E2594UL)) +#define bFM_ADC1_ADSS01_TS6 *((volatile uint8_t *)(0x424E2598UL)) +#define bFM4_ADC1_ADSS01_TS6 *((volatile uint8_t *)(0x424E2598UL)) +#define bFM_ADC1_ADSS01_TS7 *((volatile uint8_t *)(0x424E259CUL)) +#define bFM4_ADC1_ADSS01_TS7 *((volatile uint8_t *)(0x424E259CUL)) +#define bFM_ADC1_ADSS01_TS8 *((volatile uint8_t *)(0x424E25A0UL)) +#define bFM4_ADC1_ADSS01_TS8 *((volatile uint8_t *)(0x424E25A0UL)) +#define bFM_ADC1_ADSS01_TS9 *((volatile uint8_t *)(0x424E25A4UL)) +#define bFM4_ADC1_ADSS01_TS9 *((volatile uint8_t *)(0x424E25A4UL)) +#define bFM_ADC1_ADSS01_TS10 *((volatile uint8_t *)(0x424E25A8UL)) +#define bFM4_ADC1_ADSS01_TS10 *((volatile uint8_t *)(0x424E25A8UL)) +#define bFM_ADC1_ADSS01_TS11 *((volatile uint8_t *)(0x424E25ACUL)) +#define bFM4_ADC1_ADSS01_TS11 *((volatile uint8_t *)(0x424E25ACUL)) +#define bFM_ADC1_ADSS01_TS12 *((volatile uint8_t *)(0x424E25B0UL)) +#define bFM4_ADC1_ADSS01_TS12 *((volatile uint8_t *)(0x424E25B0UL)) +#define bFM_ADC1_ADSS01_TS13 *((volatile uint8_t *)(0x424E25B4UL)) +#define bFM4_ADC1_ADSS01_TS13 *((volatile uint8_t *)(0x424E25B4UL)) +#define bFM_ADC1_ADSS01_TS14 *((volatile uint8_t *)(0x424E25B8UL)) +#define bFM4_ADC1_ADSS01_TS14 *((volatile uint8_t *)(0x424E25B8UL)) +#define bFM_ADC1_ADSS01_TS15 *((volatile uint8_t *)(0x424E25BCUL)) +#define bFM4_ADC1_ADSS01_TS15 *((volatile uint8_t *)(0x424E25BCUL)) + +#define bFM_ADC1_ADSS23_TS16 *((volatile uint8_t *)(0x424E2500UL)) +#define bFM4_ADC1_ADSS23_TS16 *((volatile uint8_t *)(0x424E2500UL)) +#define bFM_ADC1_ADSS23_TS17 *((volatile uint8_t *)(0x424E2504UL)) +#define bFM4_ADC1_ADSS23_TS17 *((volatile uint8_t *)(0x424E2504UL)) +#define bFM_ADC1_ADSS23_TS18 *((volatile uint8_t *)(0x424E2508UL)) +#define bFM4_ADC1_ADSS23_TS18 *((volatile uint8_t *)(0x424E2508UL)) +#define bFM_ADC1_ADSS23_TS19 *((volatile uint8_t *)(0x424E250CUL)) +#define bFM4_ADC1_ADSS23_TS19 *((volatile uint8_t *)(0x424E250CUL)) +#define bFM_ADC1_ADSS23_TS20 *((volatile uint8_t *)(0x424E2510UL)) +#define bFM4_ADC1_ADSS23_TS20 *((volatile uint8_t *)(0x424E2510UL)) +#define bFM_ADC1_ADSS23_TS21 *((volatile uint8_t *)(0x424E2514UL)) +#define bFM4_ADC1_ADSS23_TS21 *((volatile uint8_t *)(0x424E2514UL)) +#define bFM_ADC1_ADSS23_TS22 *((volatile uint8_t *)(0x424E2518UL)) +#define bFM4_ADC1_ADSS23_TS22 *((volatile uint8_t *)(0x424E2518UL)) +#define bFM_ADC1_ADSS23_TS23 *((volatile uint8_t *)(0x424E251CUL)) +#define bFM4_ADC1_ADSS23_TS23 *((volatile uint8_t *)(0x424E251CUL)) +#define bFM_ADC1_ADSS23_TS24 *((volatile uint8_t *)(0x424E2520UL)) +#define bFM4_ADC1_ADSS23_TS24 *((volatile uint8_t *)(0x424E2520UL)) +#define bFM_ADC1_ADSS23_TS25 *((volatile uint8_t *)(0x424E2524UL)) +#define bFM4_ADC1_ADSS23_TS25 *((volatile uint8_t *)(0x424E2524UL)) +#define bFM_ADC1_ADSS23_TS26 *((volatile uint8_t *)(0x424E2528UL)) +#define bFM4_ADC1_ADSS23_TS26 *((volatile uint8_t *)(0x424E2528UL)) +#define bFM_ADC1_ADSS23_TS27 *((volatile uint8_t *)(0x424E252CUL)) +#define bFM4_ADC1_ADSS23_TS27 *((volatile uint8_t *)(0x424E252CUL)) +#define bFM_ADC1_ADSS23_TS28 *((volatile uint8_t *)(0x424E2530UL)) +#define bFM4_ADC1_ADSS23_TS28 *((volatile uint8_t *)(0x424E2530UL)) +#define bFM_ADC1_ADSS23_TS29 *((volatile uint8_t *)(0x424E2534UL)) +#define bFM4_ADC1_ADSS23_TS29 *((volatile uint8_t *)(0x424E2534UL)) +#define bFM_ADC1_ADSS23_TS30 *((volatile uint8_t *)(0x424E2538UL)) +#define bFM4_ADC1_ADSS23_TS30 *((volatile uint8_t *)(0x424E2538UL)) +#define bFM_ADC1_ADSS23_TS31 *((volatile uint8_t *)(0x424E253CUL)) +#define bFM4_ADC1_ADSS23_TS31 *((volatile uint8_t *)(0x424E253CUL)) + +#define bFM_ADC1_CALSR_CLBEN *((volatile uint8_t *)(0x424E2820UL)) +#define bFM4_ADC1_CALSR_CLBEN *((volatile uint8_t *)(0x424E2820UL)) + +#define bFM_ADC1_CMPCR_CMD0 *((volatile uint8_t *)(0x424E2494UL)) +#define bFM4_ADC1_CMPCR_CMD0 *((volatile uint8_t *)(0x424E2494UL)) +#define bFM_ADC1_CMPCR_CMD1 *((volatile uint8_t *)(0x424E2498UL)) +#define bFM4_ADC1_CMPCR_CMD1 *((volatile uint8_t *)(0x424E2498UL)) +#define bFM_ADC1_CMPCR_CMPEN *((volatile uint8_t *)(0x424E249CUL)) +#define bFM4_ADC1_CMPCR_CMPEN *((volatile uint8_t *)(0x424E249CUL)) + +#define bFM_ADC1_PCCR_PSTR *((volatile uint8_t *)(0x424E2320UL)) +#define bFM4_ADC1_PCCR_PSTR *((volatile uint8_t *)(0x424E2320UL)) +#define bFM_ADC1_PCCR_PHEN *((volatile uint8_t *)(0x424E2324UL)) +#define bFM4_ADC1_PCCR_PHEN *((volatile uint8_t *)(0x424E2324UL)) +#define bFM_ADC1_PCCR_PEEN *((volatile uint8_t *)(0x424E2328UL)) +#define bFM4_ADC1_PCCR_PEEN *((volatile uint8_t *)(0x424E2328UL)) +#define bFM_ADC1_PCCR_ESCE *((volatile uint8_t *)(0x424E232CUL)) +#define bFM4_ADC1_PCCR_ESCE *((volatile uint8_t *)(0x424E232CUL)) +#define bFM_ADC1_PCCR_PFCLR *((volatile uint8_t *)(0x424E2330UL)) +#define bFM4_ADC1_PCCR_PFCLR *((volatile uint8_t *)(0x424E2330UL)) +#define bFM_ADC1_PCCR_POVR *((volatile uint8_t *)(0x424E2334UL)) +#define bFM4_ADC1_PCCR_POVR *((volatile uint8_t *)(0x424E2334UL)) +#define bFM_ADC1_PCCR_PFUL *((volatile uint8_t *)(0x424E2338UL)) +#define bFM4_ADC1_PCCR_PFUL *((volatile uint8_t *)(0x424E2338UL)) +#define bFM_ADC1_PCCR_PEMP *((volatile uint8_t *)(0x424E233CUL)) +#define bFM4_ADC1_PCCR_PEMP *((volatile uint8_t *)(0x424E233CUL)) + +#define bFM_ADC1_PCFD_INVL *((volatile uint8_t *)(0x424E23B0UL)) +#define bFM4_ADC1_PCFD_INVL *((volatile uint8_t *)(0x424E23B0UL)) + +#define bFM_ADC1_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E23B0UL)) +#define bFM4_ADC1_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E23B0UL)) + +#define bFM_ADC1_SCCR_SSTR *((volatile uint8_t *)(0x424E2120UL)) +#define bFM4_ADC1_SCCR_SSTR *((volatile uint8_t *)(0x424E2120UL)) +#define bFM_ADC1_SCCR_SHEN *((volatile uint8_t *)(0x424E2124UL)) +#define bFM4_ADC1_SCCR_SHEN *((volatile uint8_t *)(0x424E2124UL)) +#define bFM_ADC1_SCCR_RPT *((volatile uint8_t *)(0x424E2128UL)) +#define bFM4_ADC1_SCCR_RPT *((volatile uint8_t *)(0x424E2128UL)) +#define bFM_ADC1_SCCR_SFCLR *((volatile uint8_t *)(0x424E2130UL)) +#define bFM4_ADC1_SCCR_SFCLR *((volatile uint8_t *)(0x424E2130UL)) +#define bFM_ADC1_SCCR_SOVR *((volatile uint8_t *)(0x424E2134UL)) +#define bFM4_ADC1_SCCR_SOVR *((volatile uint8_t *)(0x424E2134UL)) +#define bFM_ADC1_SCCR_SFUL *((volatile uint8_t *)(0x424E2138UL)) +#define bFM4_ADC1_SCCR_SFUL *((volatile uint8_t *)(0x424E2138UL)) +#define bFM_ADC1_SCCR_SEMP *((volatile uint8_t *)(0x424E213CUL)) +#define bFM4_ADC1_SCCR_SEMP *((volatile uint8_t *)(0x424E213CUL)) + +#define bFM_ADC1_SCFD_INVL *((volatile uint8_t *)(0x424E21B0UL)) +#define bFM4_ADC1_SCFD_INVL *((volatile uint8_t *)(0x424E21B0UL)) + +#define bFM_ADC1_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E21B0UL)) +#define bFM4_ADC1_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E21B0UL)) + +#define bFM_ADC1_SCIS01_AN0 *((volatile uint8_t *)(0x424E2280UL)) +#define bFM4_ADC1_SCIS01_AN0 *((volatile uint8_t *)(0x424E2280UL)) +#define bFM_ADC1_SCIS01_AN1 *((volatile uint8_t *)(0x424E2284UL)) +#define bFM4_ADC1_SCIS01_AN1 *((volatile uint8_t *)(0x424E2284UL)) +#define bFM_ADC1_SCIS01_AN2 *((volatile uint8_t *)(0x424E2288UL)) +#define bFM4_ADC1_SCIS01_AN2 *((volatile uint8_t *)(0x424E2288UL)) +#define bFM_ADC1_SCIS01_AN3 *((volatile uint8_t *)(0x424E228CUL)) +#define bFM4_ADC1_SCIS01_AN3 *((volatile uint8_t *)(0x424E228CUL)) +#define bFM_ADC1_SCIS01_AN4 *((volatile uint8_t *)(0x424E2290UL)) +#define bFM4_ADC1_SCIS01_AN4 *((volatile uint8_t *)(0x424E2290UL)) +#define bFM_ADC1_SCIS01_AN5 *((volatile uint8_t *)(0x424E2294UL)) +#define bFM4_ADC1_SCIS01_AN5 *((volatile uint8_t *)(0x424E2294UL)) +#define bFM_ADC1_SCIS01_AN6 *((volatile uint8_t *)(0x424E2298UL)) +#define bFM4_ADC1_SCIS01_AN6 *((volatile uint8_t *)(0x424E2298UL)) +#define bFM_ADC1_SCIS01_AN7 *((volatile uint8_t *)(0x424E229CUL)) +#define bFM4_ADC1_SCIS01_AN7 *((volatile uint8_t *)(0x424E229CUL)) +#define bFM_ADC1_SCIS01_AN8 *((volatile uint8_t *)(0x424E22A0UL)) +#define bFM4_ADC1_SCIS01_AN8 *((volatile uint8_t *)(0x424E22A0UL)) +#define bFM_ADC1_SCIS01_AN9 *((volatile uint8_t *)(0x424E22A4UL)) +#define bFM4_ADC1_SCIS01_AN9 *((volatile uint8_t *)(0x424E22A4UL)) +#define bFM_ADC1_SCIS01_AN10 *((volatile uint8_t *)(0x424E22A8UL)) +#define bFM4_ADC1_SCIS01_AN10 *((volatile uint8_t *)(0x424E22A8UL)) +#define bFM_ADC1_SCIS01_AN11 *((volatile uint8_t *)(0x424E22ACUL)) +#define bFM4_ADC1_SCIS01_AN11 *((volatile uint8_t *)(0x424E22ACUL)) +#define bFM_ADC1_SCIS01_AN12 *((volatile uint8_t *)(0x424E22B0UL)) +#define bFM4_ADC1_SCIS01_AN12 *((volatile uint8_t *)(0x424E22B0UL)) +#define bFM_ADC1_SCIS01_AN13 *((volatile uint8_t *)(0x424E22B4UL)) +#define bFM4_ADC1_SCIS01_AN13 *((volatile uint8_t *)(0x424E22B4UL)) +#define bFM_ADC1_SCIS01_AN14 *((volatile uint8_t *)(0x424E22B8UL)) +#define bFM4_ADC1_SCIS01_AN14 *((volatile uint8_t *)(0x424E22B8UL)) +#define bFM_ADC1_SCIS01_AN15 *((volatile uint8_t *)(0x424E22BCUL)) +#define bFM4_ADC1_SCIS01_AN15 *((volatile uint8_t *)(0x424E22BCUL)) + +#define bFM_ADC1_SCIS23_AN16 *((volatile uint8_t *)(0x424E2200UL)) +#define bFM4_ADC1_SCIS23_AN16 *((volatile uint8_t *)(0x424E2200UL)) +#define bFM_ADC1_SCIS23_AN17 *((volatile uint8_t *)(0x424E2204UL)) +#define bFM4_ADC1_SCIS23_AN17 *((volatile uint8_t *)(0x424E2204UL)) +#define bFM_ADC1_SCIS23_AN18 *((volatile uint8_t *)(0x424E2208UL)) +#define bFM4_ADC1_SCIS23_AN18 *((volatile uint8_t *)(0x424E2208UL)) +#define bFM_ADC1_SCIS23_AN19 *((volatile uint8_t *)(0x424E220CUL)) +#define bFM4_ADC1_SCIS23_AN19 *((volatile uint8_t *)(0x424E220CUL)) +#define bFM_ADC1_SCIS23_AN20 *((volatile uint8_t *)(0x424E2210UL)) +#define bFM4_ADC1_SCIS23_AN20 *((volatile uint8_t *)(0x424E2210UL)) +#define bFM_ADC1_SCIS23_AN21 *((volatile uint8_t *)(0x424E2214UL)) +#define bFM4_ADC1_SCIS23_AN21 *((volatile uint8_t *)(0x424E2214UL)) +#define bFM_ADC1_SCIS23_AN22 *((volatile uint8_t *)(0x424E2218UL)) +#define bFM4_ADC1_SCIS23_AN22 *((volatile uint8_t *)(0x424E2218UL)) +#define bFM_ADC1_SCIS23_AN23 *((volatile uint8_t *)(0x424E221CUL)) +#define bFM4_ADC1_SCIS23_AN23 *((volatile uint8_t *)(0x424E221CUL)) +#define bFM_ADC1_SCIS23_AN24 *((volatile uint8_t *)(0x424E2220UL)) +#define bFM4_ADC1_SCIS23_AN24 *((volatile uint8_t *)(0x424E2220UL)) +#define bFM_ADC1_SCIS23_AN25 *((volatile uint8_t *)(0x424E2224UL)) +#define bFM4_ADC1_SCIS23_AN25 *((volatile uint8_t *)(0x424E2224UL)) +#define bFM_ADC1_SCIS23_AN26 *((volatile uint8_t *)(0x424E2228UL)) +#define bFM4_ADC1_SCIS23_AN26 *((volatile uint8_t *)(0x424E2228UL)) +#define bFM_ADC1_SCIS23_AN27 *((volatile uint8_t *)(0x424E222CUL)) +#define bFM4_ADC1_SCIS23_AN27 *((volatile uint8_t *)(0x424E222CUL)) +#define bFM_ADC1_SCIS23_AN28 *((volatile uint8_t *)(0x424E2230UL)) +#define bFM4_ADC1_SCIS23_AN28 *((volatile uint8_t *)(0x424E2230UL)) +#define bFM_ADC1_SCIS23_AN29 *((volatile uint8_t *)(0x424E2234UL)) +#define bFM4_ADC1_SCIS23_AN29 *((volatile uint8_t *)(0x424E2234UL)) +#define bFM_ADC1_SCIS23_AN30 *((volatile uint8_t *)(0x424E2238UL)) +#define bFM4_ADC1_SCIS23_AN30 *((volatile uint8_t *)(0x424E2238UL)) +#define bFM_ADC1_SCIS23_AN31 *((volatile uint8_t *)(0x424E223CUL)) +#define bFM4_ADC1_SCIS23_AN31 *((volatile uint8_t *)(0x424E223CUL)) + +#define bFM_ADC1_WCMPCR_RCOE *((volatile uint8_t *)(0x424E2988UL)) +#define bFM4_ADC1_WCMPCR_RCOE *((volatile uint8_t *)(0x424E2988UL)) +#define bFM_ADC1_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E298CUL)) +#define bFM4_ADC1_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E298CUL)) +#define bFM_ADC1_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E2990UL)) +#define bFM4_ADC1_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E2990UL)) + +#define bFM_ADC1_WCMPSR_WCMD *((volatile uint8_t *)(0x424E29B4UL)) +#define bFM4_ADC1_WCMPSR_WCMD *((volatile uint8_t *)(0x424E29B4UL)) + +#define bFM_ADC1_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E2900UL)) +#define bFM4_ADC1_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E2900UL)) + +#define bFM_ADC1_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E2880UL)) +#define bFM4_ADC1_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E2880UL)) + + +/******************************************************************************* +* ADC Registers ADC2 +* Bitband Section +*******************************************************************************/ +#define bFM_ADC2_ADCEN_ENBL *((volatile uint8_t *)(0x424E4780UL)) +#define bFM4_ADC2_ADCEN_ENBL *((volatile uint8_t *)(0x424E4780UL)) +#define bFM_ADC2_ADCEN_READY *((volatile uint8_t *)(0x424E4784UL)) +#define bFM4_ADC2_ADCEN_READY *((volatile uint8_t *)(0x424E4784UL)) + +#define bFM_ADC2_ADCR_OVRIE *((volatile uint8_t *)(0x424E4020UL)) +#define bFM4_ADC2_ADCR_OVRIE *((volatile uint8_t *)(0x424E4020UL)) +#define bFM_ADC2_ADCR_CMPIE *((volatile uint8_t *)(0x424E4024UL)) +#define bFM4_ADC2_ADCR_CMPIE *((volatile uint8_t *)(0x424E4024UL)) +#define bFM_ADC2_ADCR_PCIE *((volatile uint8_t *)(0x424E4028UL)) +#define bFM4_ADC2_ADCR_PCIE *((volatile uint8_t *)(0x424E4028UL)) +#define bFM_ADC2_ADCR_SCIE *((volatile uint8_t *)(0x424E402CUL)) +#define bFM4_ADC2_ADCR_SCIE *((volatile uint8_t *)(0x424E402CUL)) +#define bFM_ADC2_ADCR_CMPIF *((volatile uint8_t *)(0x424E4034UL)) +#define bFM4_ADC2_ADCR_CMPIF *((volatile uint8_t *)(0x424E4034UL)) +#define bFM_ADC2_ADCR_PCIF *((volatile uint8_t *)(0x424E4038UL)) +#define bFM4_ADC2_ADCR_PCIF *((volatile uint8_t *)(0x424E4038UL)) +#define bFM_ADC2_ADCR_SCIF *((volatile uint8_t *)(0x424E403CUL)) +#define bFM4_ADC2_ADCR_SCIF *((volatile uint8_t *)(0x424E403CUL)) + +#define bFM_ADC2_ADSR_SCS *((volatile uint8_t *)(0x424E4000UL)) +#define bFM4_ADC2_ADSR_SCS *((volatile uint8_t *)(0x424E4000UL)) +#define bFM_ADC2_ADSR_PCS *((volatile uint8_t *)(0x424E4004UL)) +#define bFM4_ADC2_ADSR_PCS *((volatile uint8_t *)(0x424E4004UL)) +#define bFM_ADC2_ADSR_PCNS *((volatile uint8_t *)(0x424E4008UL)) +#define bFM4_ADC2_ADSR_PCNS *((volatile uint8_t *)(0x424E4008UL)) +#define bFM_ADC2_ADSR_FDAS *((volatile uint8_t *)(0x424E4018UL)) +#define bFM4_ADC2_ADSR_FDAS *((volatile uint8_t *)(0x424E4018UL)) +#define bFM_ADC2_ADSR_ADSTP *((volatile uint8_t *)(0x424E401CUL)) +#define bFM4_ADC2_ADSR_ADSTP *((volatile uint8_t *)(0x424E401CUL)) + +#define bFM_ADC2_ADSS01_TS0 *((volatile uint8_t *)(0x424E4580UL)) +#define bFM4_ADC2_ADSS01_TS0 *((volatile uint8_t *)(0x424E4580UL)) +#define bFM_ADC2_ADSS01_TS1 *((volatile uint8_t *)(0x424E4584UL)) +#define bFM4_ADC2_ADSS01_TS1 *((volatile uint8_t *)(0x424E4584UL)) +#define bFM_ADC2_ADSS01_TS2 *((volatile uint8_t *)(0x424E4588UL)) +#define bFM4_ADC2_ADSS01_TS2 *((volatile uint8_t *)(0x424E4588UL)) +#define bFM_ADC2_ADSS01_TS3 *((volatile uint8_t *)(0x424E458CUL)) +#define bFM4_ADC2_ADSS01_TS3 *((volatile uint8_t *)(0x424E458CUL)) +#define bFM_ADC2_ADSS01_TS4 *((volatile uint8_t *)(0x424E4590UL)) +#define bFM4_ADC2_ADSS01_TS4 *((volatile uint8_t *)(0x424E4590UL)) +#define bFM_ADC2_ADSS01_TS5 *((volatile uint8_t *)(0x424E4594UL)) +#define bFM4_ADC2_ADSS01_TS5 *((volatile uint8_t *)(0x424E4594UL)) +#define bFM_ADC2_ADSS01_TS6 *((volatile uint8_t *)(0x424E4598UL)) +#define bFM4_ADC2_ADSS01_TS6 *((volatile uint8_t *)(0x424E4598UL)) +#define bFM_ADC2_ADSS01_TS7 *((volatile uint8_t *)(0x424E459CUL)) +#define bFM4_ADC2_ADSS01_TS7 *((volatile uint8_t *)(0x424E459CUL)) +#define bFM_ADC2_ADSS01_TS8 *((volatile uint8_t *)(0x424E45A0UL)) +#define bFM4_ADC2_ADSS01_TS8 *((volatile uint8_t *)(0x424E45A0UL)) +#define bFM_ADC2_ADSS01_TS9 *((volatile uint8_t *)(0x424E45A4UL)) +#define bFM4_ADC2_ADSS01_TS9 *((volatile uint8_t *)(0x424E45A4UL)) +#define bFM_ADC2_ADSS01_TS10 *((volatile uint8_t *)(0x424E45A8UL)) +#define bFM4_ADC2_ADSS01_TS10 *((volatile uint8_t *)(0x424E45A8UL)) +#define bFM_ADC2_ADSS01_TS11 *((volatile uint8_t *)(0x424E45ACUL)) +#define bFM4_ADC2_ADSS01_TS11 *((volatile uint8_t *)(0x424E45ACUL)) +#define bFM_ADC2_ADSS01_TS12 *((volatile uint8_t *)(0x424E45B0UL)) +#define bFM4_ADC2_ADSS01_TS12 *((volatile uint8_t *)(0x424E45B0UL)) +#define bFM_ADC2_ADSS01_TS13 *((volatile uint8_t *)(0x424E45B4UL)) +#define bFM4_ADC2_ADSS01_TS13 *((volatile uint8_t *)(0x424E45B4UL)) +#define bFM_ADC2_ADSS01_TS14 *((volatile uint8_t *)(0x424E45B8UL)) +#define bFM4_ADC2_ADSS01_TS14 *((volatile uint8_t *)(0x424E45B8UL)) +#define bFM_ADC2_ADSS01_TS15 *((volatile uint8_t *)(0x424E45BCUL)) +#define bFM4_ADC2_ADSS01_TS15 *((volatile uint8_t *)(0x424E45BCUL)) + +#define bFM_ADC2_ADSS23_TS16 *((volatile uint8_t *)(0x424E4500UL)) +#define bFM4_ADC2_ADSS23_TS16 *((volatile uint8_t *)(0x424E4500UL)) +#define bFM_ADC2_ADSS23_TS17 *((volatile uint8_t *)(0x424E4504UL)) +#define bFM4_ADC2_ADSS23_TS17 *((volatile uint8_t *)(0x424E4504UL)) +#define bFM_ADC2_ADSS23_TS18 *((volatile uint8_t *)(0x424E4508UL)) +#define bFM4_ADC2_ADSS23_TS18 *((volatile uint8_t *)(0x424E4508UL)) +#define bFM_ADC2_ADSS23_TS19 *((volatile uint8_t *)(0x424E450CUL)) +#define bFM4_ADC2_ADSS23_TS19 *((volatile uint8_t *)(0x424E450CUL)) +#define bFM_ADC2_ADSS23_TS20 *((volatile uint8_t *)(0x424E4510UL)) +#define bFM4_ADC2_ADSS23_TS20 *((volatile uint8_t *)(0x424E4510UL)) +#define bFM_ADC2_ADSS23_TS21 *((volatile uint8_t *)(0x424E4514UL)) +#define bFM4_ADC2_ADSS23_TS21 *((volatile uint8_t *)(0x424E4514UL)) +#define bFM_ADC2_ADSS23_TS22 *((volatile uint8_t *)(0x424E4518UL)) +#define bFM4_ADC2_ADSS23_TS22 *((volatile uint8_t *)(0x424E4518UL)) +#define bFM_ADC2_ADSS23_TS23 *((volatile uint8_t *)(0x424E451CUL)) +#define bFM4_ADC2_ADSS23_TS23 *((volatile uint8_t *)(0x424E451CUL)) +#define bFM_ADC2_ADSS23_TS24 *((volatile uint8_t *)(0x424E4520UL)) +#define bFM4_ADC2_ADSS23_TS24 *((volatile uint8_t *)(0x424E4520UL)) +#define bFM_ADC2_ADSS23_TS25 *((volatile uint8_t *)(0x424E4524UL)) +#define bFM4_ADC2_ADSS23_TS25 *((volatile uint8_t *)(0x424E4524UL)) +#define bFM_ADC2_ADSS23_TS26 *((volatile uint8_t *)(0x424E4528UL)) +#define bFM4_ADC2_ADSS23_TS26 *((volatile uint8_t *)(0x424E4528UL)) +#define bFM_ADC2_ADSS23_TS27 *((volatile uint8_t *)(0x424E452CUL)) +#define bFM4_ADC2_ADSS23_TS27 *((volatile uint8_t *)(0x424E452CUL)) +#define bFM_ADC2_ADSS23_TS28 *((volatile uint8_t *)(0x424E4530UL)) +#define bFM4_ADC2_ADSS23_TS28 *((volatile uint8_t *)(0x424E4530UL)) +#define bFM_ADC2_ADSS23_TS29 *((volatile uint8_t *)(0x424E4534UL)) +#define bFM4_ADC2_ADSS23_TS29 *((volatile uint8_t *)(0x424E4534UL)) +#define bFM_ADC2_ADSS23_TS30 *((volatile uint8_t *)(0x424E4538UL)) +#define bFM4_ADC2_ADSS23_TS30 *((volatile uint8_t *)(0x424E4538UL)) +#define bFM_ADC2_ADSS23_TS31 *((volatile uint8_t *)(0x424E453CUL)) +#define bFM4_ADC2_ADSS23_TS31 *((volatile uint8_t *)(0x424E453CUL)) + +#define bFM_ADC2_CALSR_CLBEN *((volatile uint8_t *)(0x424E4820UL)) +#define bFM4_ADC2_CALSR_CLBEN *((volatile uint8_t *)(0x424E4820UL)) + +#define bFM_ADC2_CMPCR_CMD0 *((volatile uint8_t *)(0x424E4494UL)) +#define bFM4_ADC2_CMPCR_CMD0 *((volatile uint8_t *)(0x424E4494UL)) +#define bFM_ADC2_CMPCR_CMD1 *((volatile uint8_t *)(0x424E4498UL)) +#define bFM4_ADC2_CMPCR_CMD1 *((volatile uint8_t *)(0x424E4498UL)) +#define bFM_ADC2_CMPCR_CMPEN *((volatile uint8_t *)(0x424E449CUL)) +#define bFM4_ADC2_CMPCR_CMPEN *((volatile uint8_t *)(0x424E449CUL)) + +#define bFM_ADC2_PCCR_PSTR *((volatile uint8_t *)(0x424E4320UL)) +#define bFM4_ADC2_PCCR_PSTR *((volatile uint8_t *)(0x424E4320UL)) +#define bFM_ADC2_PCCR_PHEN *((volatile uint8_t *)(0x424E4324UL)) +#define bFM4_ADC2_PCCR_PHEN *((volatile uint8_t *)(0x424E4324UL)) +#define bFM_ADC2_PCCR_PEEN *((volatile uint8_t *)(0x424E4328UL)) +#define bFM4_ADC2_PCCR_PEEN *((volatile uint8_t *)(0x424E4328UL)) +#define bFM_ADC2_PCCR_ESCE *((volatile uint8_t *)(0x424E432CUL)) +#define bFM4_ADC2_PCCR_ESCE *((volatile uint8_t *)(0x424E432CUL)) +#define bFM_ADC2_PCCR_PFCLR *((volatile uint8_t *)(0x424E4330UL)) +#define bFM4_ADC2_PCCR_PFCLR *((volatile uint8_t *)(0x424E4330UL)) +#define bFM_ADC2_PCCR_POVR *((volatile uint8_t *)(0x424E4334UL)) +#define bFM4_ADC2_PCCR_POVR *((volatile uint8_t *)(0x424E4334UL)) +#define bFM_ADC2_PCCR_PFUL *((volatile uint8_t *)(0x424E4338UL)) +#define bFM4_ADC2_PCCR_PFUL *((volatile uint8_t *)(0x424E4338UL)) +#define bFM_ADC2_PCCR_PEMP *((volatile uint8_t *)(0x424E433CUL)) +#define bFM4_ADC2_PCCR_PEMP *((volatile uint8_t *)(0x424E433CUL)) + +#define bFM_ADC2_PCFD_INVL *((volatile uint8_t *)(0x424E43B0UL)) +#define bFM4_ADC2_PCFD_INVL *((volatile uint8_t *)(0x424E43B0UL)) + +#define bFM_ADC2_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E43B0UL)) +#define bFM4_ADC2_PCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E43B0UL)) + +#define bFM_ADC2_SCCR_SSTR *((volatile uint8_t *)(0x424E4120UL)) +#define bFM4_ADC2_SCCR_SSTR *((volatile uint8_t *)(0x424E4120UL)) +#define bFM_ADC2_SCCR_SHEN *((volatile uint8_t *)(0x424E4124UL)) +#define bFM4_ADC2_SCCR_SHEN *((volatile uint8_t *)(0x424E4124UL)) +#define bFM_ADC2_SCCR_RPT *((volatile uint8_t *)(0x424E4128UL)) +#define bFM4_ADC2_SCCR_RPT *((volatile uint8_t *)(0x424E4128UL)) +#define bFM_ADC2_SCCR_SFCLR *((volatile uint8_t *)(0x424E4130UL)) +#define bFM4_ADC2_SCCR_SFCLR *((volatile uint8_t *)(0x424E4130UL)) +#define bFM_ADC2_SCCR_SOVR *((volatile uint8_t *)(0x424E4134UL)) +#define bFM4_ADC2_SCCR_SOVR *((volatile uint8_t *)(0x424E4134UL)) +#define bFM_ADC2_SCCR_SFUL *((volatile uint8_t *)(0x424E4138UL)) +#define bFM4_ADC2_SCCR_SFUL *((volatile uint8_t *)(0x424E4138UL)) +#define bFM_ADC2_SCCR_SEMP *((volatile uint8_t *)(0x424E413CUL)) +#define bFM4_ADC2_SCCR_SEMP *((volatile uint8_t *)(0x424E413CUL)) + +#define bFM_ADC2_SCFD_INVL *((volatile uint8_t *)(0x424E41B0UL)) +#define bFM4_ADC2_SCFD_INVL *((volatile uint8_t *)(0x424E41B0UL)) + +#define bFM_ADC2_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E41B0UL)) +#define bFM4_ADC2_SCFD_FDAS1_INVL *((volatile uint8_t *)(0x424E41B0UL)) + +#define bFM_ADC2_SCIS01_AN0 *((volatile uint8_t *)(0x424E4280UL)) +#define bFM4_ADC2_SCIS01_AN0 *((volatile uint8_t *)(0x424E4280UL)) +#define bFM_ADC2_SCIS01_AN1 *((volatile uint8_t *)(0x424E4284UL)) +#define bFM4_ADC2_SCIS01_AN1 *((volatile uint8_t *)(0x424E4284UL)) +#define bFM_ADC2_SCIS01_AN2 *((volatile uint8_t *)(0x424E4288UL)) +#define bFM4_ADC2_SCIS01_AN2 *((volatile uint8_t *)(0x424E4288UL)) +#define bFM_ADC2_SCIS01_AN3 *((volatile uint8_t *)(0x424E428CUL)) +#define bFM4_ADC2_SCIS01_AN3 *((volatile uint8_t *)(0x424E428CUL)) +#define bFM_ADC2_SCIS01_AN4 *((volatile uint8_t *)(0x424E4290UL)) +#define bFM4_ADC2_SCIS01_AN4 *((volatile uint8_t *)(0x424E4290UL)) +#define bFM_ADC2_SCIS01_AN5 *((volatile uint8_t *)(0x424E4294UL)) +#define bFM4_ADC2_SCIS01_AN5 *((volatile uint8_t *)(0x424E4294UL)) +#define bFM_ADC2_SCIS01_AN6 *((volatile uint8_t *)(0x424E4298UL)) +#define bFM4_ADC2_SCIS01_AN6 *((volatile uint8_t *)(0x424E4298UL)) +#define bFM_ADC2_SCIS01_AN7 *((volatile uint8_t *)(0x424E429CUL)) +#define bFM4_ADC2_SCIS01_AN7 *((volatile uint8_t *)(0x424E429CUL)) +#define bFM_ADC2_SCIS01_AN8 *((volatile uint8_t *)(0x424E42A0UL)) +#define bFM4_ADC2_SCIS01_AN8 *((volatile uint8_t *)(0x424E42A0UL)) +#define bFM_ADC2_SCIS01_AN9 *((volatile uint8_t *)(0x424E42A4UL)) +#define bFM4_ADC2_SCIS01_AN9 *((volatile uint8_t *)(0x424E42A4UL)) +#define bFM_ADC2_SCIS01_AN10 *((volatile uint8_t *)(0x424E42A8UL)) +#define bFM4_ADC2_SCIS01_AN10 *((volatile uint8_t *)(0x424E42A8UL)) +#define bFM_ADC2_SCIS01_AN11 *((volatile uint8_t *)(0x424E42ACUL)) +#define bFM4_ADC2_SCIS01_AN11 *((volatile uint8_t *)(0x424E42ACUL)) +#define bFM_ADC2_SCIS01_AN12 *((volatile uint8_t *)(0x424E42B0UL)) +#define bFM4_ADC2_SCIS01_AN12 *((volatile uint8_t *)(0x424E42B0UL)) +#define bFM_ADC2_SCIS01_AN13 *((volatile uint8_t *)(0x424E42B4UL)) +#define bFM4_ADC2_SCIS01_AN13 *((volatile uint8_t *)(0x424E42B4UL)) +#define bFM_ADC2_SCIS01_AN14 *((volatile uint8_t *)(0x424E42B8UL)) +#define bFM4_ADC2_SCIS01_AN14 *((volatile uint8_t *)(0x424E42B8UL)) +#define bFM_ADC2_SCIS01_AN15 *((volatile uint8_t *)(0x424E42BCUL)) +#define bFM4_ADC2_SCIS01_AN15 *((volatile uint8_t *)(0x424E42BCUL)) + +#define bFM_ADC2_SCIS23_AN16 *((volatile uint8_t *)(0x424E4200UL)) +#define bFM4_ADC2_SCIS23_AN16 *((volatile uint8_t *)(0x424E4200UL)) +#define bFM_ADC2_SCIS23_AN17 *((volatile uint8_t *)(0x424E4204UL)) +#define bFM4_ADC2_SCIS23_AN17 *((volatile uint8_t *)(0x424E4204UL)) +#define bFM_ADC2_SCIS23_AN18 *((volatile uint8_t *)(0x424E4208UL)) +#define bFM4_ADC2_SCIS23_AN18 *((volatile uint8_t *)(0x424E4208UL)) +#define bFM_ADC2_SCIS23_AN19 *((volatile uint8_t *)(0x424E420CUL)) +#define bFM4_ADC2_SCIS23_AN19 *((volatile uint8_t *)(0x424E420CUL)) +#define bFM_ADC2_SCIS23_AN20 *((volatile uint8_t *)(0x424E4210UL)) +#define bFM4_ADC2_SCIS23_AN20 *((volatile uint8_t *)(0x424E4210UL)) +#define bFM_ADC2_SCIS23_AN21 *((volatile uint8_t *)(0x424E4214UL)) +#define bFM4_ADC2_SCIS23_AN21 *((volatile uint8_t *)(0x424E4214UL)) +#define bFM_ADC2_SCIS23_AN22 *((volatile uint8_t *)(0x424E4218UL)) +#define bFM4_ADC2_SCIS23_AN22 *((volatile uint8_t *)(0x424E4218UL)) +#define bFM_ADC2_SCIS23_AN23 *((volatile uint8_t *)(0x424E421CUL)) +#define bFM4_ADC2_SCIS23_AN23 *((volatile uint8_t *)(0x424E421CUL)) +#define bFM_ADC2_SCIS23_AN24 *((volatile uint8_t *)(0x424E4220UL)) +#define bFM4_ADC2_SCIS23_AN24 *((volatile uint8_t *)(0x424E4220UL)) +#define bFM_ADC2_SCIS23_AN25 *((volatile uint8_t *)(0x424E4224UL)) +#define bFM4_ADC2_SCIS23_AN25 *((volatile uint8_t *)(0x424E4224UL)) +#define bFM_ADC2_SCIS23_AN26 *((volatile uint8_t *)(0x424E4228UL)) +#define bFM4_ADC2_SCIS23_AN26 *((volatile uint8_t *)(0x424E4228UL)) +#define bFM_ADC2_SCIS23_AN27 *((volatile uint8_t *)(0x424E422CUL)) +#define bFM4_ADC2_SCIS23_AN27 *((volatile uint8_t *)(0x424E422CUL)) +#define bFM_ADC2_SCIS23_AN28 *((volatile uint8_t *)(0x424E4230UL)) +#define bFM4_ADC2_SCIS23_AN28 *((volatile uint8_t *)(0x424E4230UL)) +#define bFM_ADC2_SCIS23_AN29 *((volatile uint8_t *)(0x424E4234UL)) +#define bFM4_ADC2_SCIS23_AN29 *((volatile uint8_t *)(0x424E4234UL)) +#define bFM_ADC2_SCIS23_AN30 *((volatile uint8_t *)(0x424E4238UL)) +#define bFM4_ADC2_SCIS23_AN30 *((volatile uint8_t *)(0x424E4238UL)) +#define bFM_ADC2_SCIS23_AN31 *((volatile uint8_t *)(0x424E423CUL)) +#define bFM4_ADC2_SCIS23_AN31 *((volatile uint8_t *)(0x424E423CUL)) + +#define bFM_ADC2_WCMPCR_RCOE *((volatile uint8_t *)(0x424E4988UL)) +#define bFM4_ADC2_WCMPCR_RCOE *((volatile uint8_t *)(0x424E4988UL)) +#define bFM_ADC2_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E498CUL)) +#define bFM4_ADC2_WCMPCR_RCOIE *((volatile uint8_t *)(0x424E498CUL)) +#define bFM_ADC2_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E4990UL)) +#define bFM4_ADC2_WCMPCR_RCOIRS *((volatile uint8_t *)(0x424E4990UL)) + +#define bFM_ADC2_WCMPSR_WCMD *((volatile uint8_t *)(0x424E49B4UL)) +#define bFM4_ADC2_WCMPSR_WCMD *((volatile uint8_t *)(0x424E49B4UL)) + +#define bFM_ADC2_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E4900UL)) +#define bFM4_ADC2_WCMRCIF_RCINT *((volatile uint8_t *)(0x424E4900UL)) + +#define bFM_ADC2_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E4880UL)) +#define bFM4_ADC2_WCMRCOT_RCOOF *((volatile uint8_t *)(0x424E4880UL)) + + +/******************************************************************************* +* BT Registers BT0 +* Bitband Section +*******************************************************************************/ +#define bFM_BT0_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) + +#define bFM_BT0_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM4_BT0_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM_BT0_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM4_BT0_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM_BT0_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM4_BT0_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM_BT0_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) +#define bFM4_BT0_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) + +#define bFM_BT0_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) + +#define bFM_BT0_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM_BT0_PWC_STC_ERR *((volatile uint8_t *)(0x424A021CUL)) +#define bFM4_BT0_PWC_STC_ERR *((volatile uint8_t *)(0x424A021CUL)) + +#define bFM_BT0_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) +#define bFM4_BT0_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) + +#define bFM_BT0_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) + +#define bFM_BT0_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0204UL)) +#define bFM4_BT0_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0204UL)) +#define bFM_BT0_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0214UL)) +#define bFM4_BT0_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0214UL)) +#define bFM_BT0_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) + +#define bFM_BT0_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM4_BT0_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM_BT0_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM4_BT0_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM_BT0_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM4_BT0_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A01A8UL)) +#define bFM_BT0_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) +#define bFM4_BT0_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A01ACUL)) + +#define bFM_BT0_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) + +#define bFM_BT0_RT_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM4_BT0_RT_STC_UDIR *((volatile uint8_t *)(0x424A0200UL)) +#define bFM_BT0_RT_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM4_BT0_RT_STC_TGIR *((volatile uint8_t *)(0x424A0208UL)) +#define bFM_BT0_RT_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM4_BT0_RT_STC_UDIE *((volatile uint8_t *)(0x424A0210UL)) +#define bFM_BT0_RT_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) +#define bFM4_BT0_RT_STC_TGIE *((volatile uint8_t *)(0x424A0218UL)) + +#define bFM_BT0_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM4_BT0_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0180UL)) +#define bFM_BT0_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM4_BT0_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0184UL)) +#define bFM_BT0_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM4_BT0_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0188UL)) +#define bFM_BT0_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM4_BT0_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A018CUL)) +#define bFM_BT0_RT_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) +#define bFM4_BT0_RT_TMCR_T32 *((volatile uint8_t *)(0x424A019CUL)) + +#define bFM_BT0_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM4_BT0_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0220UL)) +#define bFM_BT0_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A023CUL)) +#define bFM4_BT0_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A023CUL)) + + +/******************************************************************************* +* BT Registers BT1 +* Bitband Section +*******************************************************************************/ +#define bFM_BT1_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_PPG_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_PPG_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_PPG_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_PPG_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) + +#define bFM_BT1_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM4_BT1_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM_BT1_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM4_BT1_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM_BT1_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM4_BT1_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM_BT1_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) +#define bFM4_BT1_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) + +#define bFM_BT1_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) + +#define bFM_BT1_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_PWC_STC_OVIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_PWC_STC_EDIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_PWC_STC_OVIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_PWC_STC_EDIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM_BT1_PWC_STC_ERR *((volatile uint8_t *)(0x424A0A1CUL)) +#define bFM4_BT1_PWC_STC_ERR *((volatile uint8_t *)(0x424A0A1CUL)) + +#define bFM_BT1_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) +#define bFM4_BT1_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) + +#define bFM_BT1_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) + +#define bFM_BT1_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_PWM_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0A04UL)) +#define bFM4_BT1_PWM_STC_DTIR *((volatile uint8_t *)(0x424A0A04UL)) +#define bFM_BT1_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_PWM_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_PWM_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0A14UL)) +#define bFM4_BT1_PWM_STC_DTIE *((volatile uint8_t *)(0x424A0A14UL)) +#define bFM_BT1_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_PWM_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) + +#define bFM_BT1_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM4_BT1_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM_BT1_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM4_BT1_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM_BT1_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM4_BT1_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A09A8UL)) +#define bFM_BT1_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) +#define bFM4_BT1_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A09ACUL)) + +#define bFM_BT1_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) + +#define bFM_BT1_RT_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM4_BT1_RT_STC_UDIR *((volatile uint8_t *)(0x424A0A00UL)) +#define bFM_BT1_RT_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM4_BT1_RT_STC_TGIR *((volatile uint8_t *)(0x424A0A08UL)) +#define bFM_BT1_RT_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM4_BT1_RT_STC_UDIE *((volatile uint8_t *)(0x424A0A10UL)) +#define bFM_BT1_RT_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) +#define bFM4_BT1_RT_STC_TGIE *((volatile uint8_t *)(0x424A0A18UL)) + +#define bFM_BT1_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM4_BT1_RT_TMCR_STRG *((volatile uint8_t *)(0x424A0980UL)) +#define bFM_BT1_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM4_BT1_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A0984UL)) +#define bFM_BT1_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM4_BT1_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A0988UL)) +#define bFM_BT1_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM4_BT1_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A098CUL)) +#define bFM_BT1_RT_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) +#define bFM4_BT1_RT_TMCR_T32 *((volatile uint8_t *)(0x424A099CUL)) + +#define bFM_BT1_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM4_BT1_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A0A20UL)) +#define bFM_BT1_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A0A3CUL)) +#define bFM4_BT1_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A0A3CUL)) + + +/******************************************************************************* +* BT Registers BT10 +* Bitband Section +*******************************************************************************/ +#define bFM_BT10_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) + +#define bFM_BT10_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM4_BT10_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM_BT10_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM4_BT10_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM_BT10_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM4_BT10_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM_BT10_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) +#define bFM4_BT10_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) + +#define bFM_BT10_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) + +#define bFM_BT10_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM_BT10_PWC_STC_ERR *((volatile uint8_t *)(0x424A921CUL)) +#define bFM4_BT10_PWC_STC_ERR *((volatile uint8_t *)(0x424A921CUL)) + +#define bFM_BT10_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) +#define bFM4_BT10_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) + +#define bFM_BT10_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) + +#define bFM_BT10_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9204UL)) +#define bFM4_BT10_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9204UL)) +#define bFM_BT10_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9214UL)) +#define bFM4_BT10_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9214UL)) +#define bFM_BT10_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) + +#define bFM_BT10_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM4_BT10_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM_BT10_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM4_BT10_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM_BT10_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM4_BT10_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A91A8UL)) +#define bFM_BT10_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) +#define bFM4_BT10_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A91ACUL)) + +#define bFM_BT10_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) + +#define bFM_BT10_RT_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM4_BT10_RT_STC_UDIR *((volatile uint8_t *)(0x424A9200UL)) +#define bFM_BT10_RT_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM4_BT10_RT_STC_TGIR *((volatile uint8_t *)(0x424A9208UL)) +#define bFM_BT10_RT_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM4_BT10_RT_STC_UDIE *((volatile uint8_t *)(0x424A9210UL)) +#define bFM_BT10_RT_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) +#define bFM4_BT10_RT_STC_TGIE *((volatile uint8_t *)(0x424A9218UL)) + +#define bFM_BT10_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM4_BT10_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9180UL)) +#define bFM_BT10_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM4_BT10_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9184UL)) +#define bFM_BT10_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM4_BT10_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9188UL)) +#define bFM_BT10_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM4_BT10_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A918CUL)) +#define bFM_BT10_RT_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) +#define bFM4_BT10_RT_TMCR_T32 *((volatile uint8_t *)(0x424A919CUL)) + +#define bFM_BT10_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM4_BT10_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9220UL)) +#define bFM_BT10_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A923CUL)) +#define bFM4_BT10_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A923CUL)) + + +/******************************************************************************* +* BT Registers BT11 +* Bitband Section +*******************************************************************************/ +#define bFM_BT11_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_PPG_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_PPG_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_PPG_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_PPG_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) + +#define bFM_BT11_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM4_BT11_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM_BT11_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM4_BT11_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM_BT11_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM4_BT11_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM_BT11_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) +#define bFM4_BT11_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) + +#define bFM_BT11_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) + +#define bFM_BT11_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_PWC_STC_OVIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_PWC_STC_EDIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_PWC_STC_OVIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_PWC_STC_EDIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM_BT11_PWC_STC_ERR *((volatile uint8_t *)(0x424A9A1CUL)) +#define bFM4_BT11_PWC_STC_ERR *((volatile uint8_t *)(0x424A9A1CUL)) + +#define bFM_BT11_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) +#define bFM4_BT11_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) + +#define bFM_BT11_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) + +#define bFM_BT11_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_PWM_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9A04UL)) +#define bFM4_BT11_PWM_STC_DTIR *((volatile uint8_t *)(0x424A9A04UL)) +#define bFM_BT11_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_PWM_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_PWM_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9A14UL)) +#define bFM4_BT11_PWM_STC_DTIE *((volatile uint8_t *)(0x424A9A14UL)) +#define bFM_BT11_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_PWM_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) + +#define bFM_BT11_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM4_BT11_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM_BT11_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM4_BT11_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM_BT11_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM4_BT11_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A99A8UL)) +#define bFM_BT11_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) +#define bFM4_BT11_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A99ACUL)) + +#define bFM_BT11_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) + +#define bFM_BT11_RT_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM4_BT11_RT_STC_UDIR *((volatile uint8_t *)(0x424A9A00UL)) +#define bFM_BT11_RT_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM4_BT11_RT_STC_TGIR *((volatile uint8_t *)(0x424A9A08UL)) +#define bFM_BT11_RT_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM4_BT11_RT_STC_UDIE *((volatile uint8_t *)(0x424A9A10UL)) +#define bFM_BT11_RT_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) +#define bFM4_BT11_RT_STC_TGIE *((volatile uint8_t *)(0x424A9A18UL)) + +#define bFM_BT11_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM4_BT11_RT_TMCR_STRG *((volatile uint8_t *)(0x424A9980UL)) +#define bFM_BT11_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM4_BT11_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A9984UL)) +#define bFM_BT11_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM4_BT11_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A9988UL)) +#define bFM_BT11_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM4_BT11_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A998CUL)) +#define bFM_BT11_RT_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) +#define bFM4_BT11_RT_TMCR_T32 *((volatile uint8_t *)(0x424A999CUL)) + +#define bFM_BT11_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM4_BT11_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A9A20UL)) +#define bFM_BT11_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A9A3CUL)) +#define bFM4_BT11_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A9A3CUL)) + + +/******************************************************************************* +* BT Registers BT12 +* Bitband Section +*******************************************************************************/ +#define bFM_BT12_PPG_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_PPG_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_PPG_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_PPG_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_PPG_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_PPG_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_PPG_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_PPG_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) + +#define bFM_BT12_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM4_BT12_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM_BT12_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM4_BT12_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM_BT12_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM4_BT12_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM_BT12_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) +#define bFM4_BT12_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) + +#define bFM_BT12_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) + +#define bFM_BT12_PWC_STC_OVIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_PWC_STC_OVIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_PWC_STC_EDIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_PWC_STC_EDIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_PWC_STC_OVIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_PWC_STC_OVIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_PWC_STC_EDIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_PWC_STC_EDIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM_BT12_PWC_STC_ERR *((volatile uint8_t *)(0x424AC21CUL)) +#define bFM4_BT12_PWC_STC_ERR *((volatile uint8_t *)(0x424AC21CUL)) + +#define bFM_BT12_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) +#define bFM4_BT12_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) + +#define bFM_BT12_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) + +#define bFM_BT12_PWM_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_PWM_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_PWM_STC_DTIR *((volatile uint8_t *)(0x424AC204UL)) +#define bFM4_BT12_PWM_STC_DTIR *((volatile uint8_t *)(0x424AC204UL)) +#define bFM_BT12_PWM_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_PWM_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_PWM_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_PWM_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_PWM_STC_DTIE *((volatile uint8_t *)(0x424AC214UL)) +#define bFM4_BT12_PWM_STC_DTIE *((volatile uint8_t *)(0x424AC214UL)) +#define bFM_BT12_PWM_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_PWM_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) + +#define bFM_BT12_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM4_BT12_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM_BT12_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM4_BT12_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM_BT12_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM4_BT12_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC1A8UL)) +#define bFM_BT12_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) +#define bFM4_BT12_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC1ACUL)) + +#define bFM_BT12_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) + +#define bFM_BT12_RT_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM4_BT12_RT_STC_UDIR *((volatile uint8_t *)(0x424AC200UL)) +#define bFM_BT12_RT_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM4_BT12_RT_STC_TGIR *((volatile uint8_t *)(0x424AC208UL)) +#define bFM_BT12_RT_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM4_BT12_RT_STC_UDIE *((volatile uint8_t *)(0x424AC210UL)) +#define bFM_BT12_RT_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) +#define bFM4_BT12_RT_STC_TGIE *((volatile uint8_t *)(0x424AC218UL)) + +#define bFM_BT12_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM4_BT12_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC180UL)) +#define bFM_BT12_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM4_BT12_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC184UL)) +#define bFM_BT12_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM4_BT12_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC188UL)) +#define bFM_BT12_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM4_BT12_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC18CUL)) +#define bFM_BT12_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) +#define bFM4_BT12_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC19CUL)) + +#define bFM_BT12_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM4_BT12_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AC220UL)) +#define bFM_BT12_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AC23CUL)) +#define bFM4_BT12_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AC23CUL)) + + +/******************************************************************************* +* BT Registers BT13 +* Bitband Section +*******************************************************************************/ +#define bFM_BT13_PPG_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_PPG_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_PPG_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_PPG_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_PPG_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_PPG_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_PPG_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_PPG_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) + +#define bFM_BT13_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM4_BT13_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM_BT13_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM4_BT13_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM_BT13_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM4_BT13_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM_BT13_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) +#define bFM4_BT13_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) + +#define bFM_BT13_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) + +#define bFM_BT13_PWC_STC_OVIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_PWC_STC_OVIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_PWC_STC_EDIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_PWC_STC_EDIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_PWC_STC_OVIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_PWC_STC_OVIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_PWC_STC_EDIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_PWC_STC_EDIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM_BT13_PWC_STC_ERR *((volatile uint8_t *)(0x424ACA1CUL)) +#define bFM4_BT13_PWC_STC_ERR *((volatile uint8_t *)(0x424ACA1CUL)) + +#define bFM_BT13_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) +#define bFM4_BT13_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) + +#define bFM_BT13_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) + +#define bFM_BT13_PWM_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_PWM_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_PWM_STC_DTIR *((volatile uint8_t *)(0x424ACA04UL)) +#define bFM4_BT13_PWM_STC_DTIR *((volatile uint8_t *)(0x424ACA04UL)) +#define bFM_BT13_PWM_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_PWM_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_PWM_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_PWM_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_PWM_STC_DTIE *((volatile uint8_t *)(0x424ACA14UL)) +#define bFM4_BT13_PWM_STC_DTIE *((volatile uint8_t *)(0x424ACA14UL)) +#define bFM_BT13_PWM_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_PWM_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) + +#define bFM_BT13_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM4_BT13_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM_BT13_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM4_BT13_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM_BT13_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM4_BT13_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AC9A8UL)) +#define bFM_BT13_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) +#define bFM4_BT13_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AC9ACUL)) + +#define bFM_BT13_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) + +#define bFM_BT13_RT_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM4_BT13_RT_STC_UDIR *((volatile uint8_t *)(0x424ACA00UL)) +#define bFM_BT13_RT_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM4_BT13_RT_STC_TGIR *((volatile uint8_t *)(0x424ACA08UL)) +#define bFM_BT13_RT_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM4_BT13_RT_STC_UDIE *((volatile uint8_t *)(0x424ACA10UL)) +#define bFM_BT13_RT_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) +#define bFM4_BT13_RT_STC_TGIE *((volatile uint8_t *)(0x424ACA18UL)) + +#define bFM_BT13_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM4_BT13_RT_TMCR_STRG *((volatile uint8_t *)(0x424AC980UL)) +#define bFM_BT13_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM4_BT13_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AC984UL)) +#define bFM_BT13_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM4_BT13_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AC988UL)) +#define bFM_BT13_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM4_BT13_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AC98CUL)) +#define bFM_BT13_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) +#define bFM4_BT13_RT_TMCR_T32 *((volatile uint8_t *)(0x424AC99CUL)) + +#define bFM_BT13_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM4_BT13_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ACA20UL)) +#define bFM_BT13_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ACA3CUL)) +#define bFM4_BT13_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ACA3CUL)) + + +/******************************************************************************* +* BT Registers BT14 +* Bitband Section +*******************************************************************************/ +#define bFM_BT14_PPG_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_PPG_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_PPG_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_PPG_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_PPG_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_PPG_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_PPG_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_PPG_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) + +#define bFM_BT14_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM4_BT14_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM_BT14_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM4_BT14_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM_BT14_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM4_BT14_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM_BT14_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) +#define bFM4_BT14_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) + +#define bFM_BT14_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) + +#define bFM_BT14_PWC_STC_OVIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_PWC_STC_OVIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_PWC_STC_EDIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_PWC_STC_EDIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_PWC_STC_OVIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_PWC_STC_OVIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_PWC_STC_EDIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_PWC_STC_EDIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM_BT14_PWC_STC_ERR *((volatile uint8_t *)(0x424AD21CUL)) +#define bFM4_BT14_PWC_STC_ERR *((volatile uint8_t *)(0x424AD21CUL)) + +#define bFM_BT14_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) +#define bFM4_BT14_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) + +#define bFM_BT14_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) + +#define bFM_BT14_PWM_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_PWM_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_PWM_STC_DTIR *((volatile uint8_t *)(0x424AD204UL)) +#define bFM4_BT14_PWM_STC_DTIR *((volatile uint8_t *)(0x424AD204UL)) +#define bFM_BT14_PWM_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_PWM_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_PWM_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_PWM_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_PWM_STC_DTIE *((volatile uint8_t *)(0x424AD214UL)) +#define bFM4_BT14_PWM_STC_DTIE *((volatile uint8_t *)(0x424AD214UL)) +#define bFM_BT14_PWM_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_PWM_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) + +#define bFM_BT14_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM4_BT14_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM_BT14_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM4_BT14_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM_BT14_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM4_BT14_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD1A8UL)) +#define bFM_BT14_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) +#define bFM4_BT14_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD1ACUL)) + +#define bFM_BT14_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) + +#define bFM_BT14_RT_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM4_BT14_RT_STC_UDIR *((volatile uint8_t *)(0x424AD200UL)) +#define bFM_BT14_RT_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM4_BT14_RT_STC_TGIR *((volatile uint8_t *)(0x424AD208UL)) +#define bFM_BT14_RT_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM4_BT14_RT_STC_UDIE *((volatile uint8_t *)(0x424AD210UL)) +#define bFM_BT14_RT_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) +#define bFM4_BT14_RT_STC_TGIE *((volatile uint8_t *)(0x424AD218UL)) + +#define bFM_BT14_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM4_BT14_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD180UL)) +#define bFM_BT14_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM4_BT14_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD184UL)) +#define bFM_BT14_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM4_BT14_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD188UL)) +#define bFM_BT14_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM4_BT14_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD18CUL)) +#define bFM_BT14_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) +#define bFM4_BT14_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD19CUL)) + +#define bFM_BT14_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM4_BT14_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424AD220UL)) +#define bFM_BT14_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AD23CUL)) +#define bFM4_BT14_RT_TMCR2_GATE *((volatile uint8_t *)(0x424AD23CUL)) + + +/******************************************************************************* +* BT Registers BT15 +* Bitband Section +*******************************************************************************/ +#define bFM_BT15_PPG_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_PPG_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_PPG_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_PPG_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_PPG_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_PPG_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_PPG_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_PPG_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) + +#define bFM_BT15_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM4_BT15_PPG_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM_BT15_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM4_BT15_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM_BT15_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM4_BT15_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM_BT15_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) +#define bFM4_BT15_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) + +#define bFM_BT15_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) + +#define bFM_BT15_PWC_STC_OVIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_PWC_STC_OVIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_PWC_STC_EDIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_PWC_STC_EDIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_PWC_STC_OVIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_PWC_STC_OVIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_PWC_STC_EDIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_PWC_STC_EDIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM_BT15_PWC_STC_ERR *((volatile uint8_t *)(0x424ADA1CUL)) +#define bFM4_BT15_PWC_STC_ERR *((volatile uint8_t *)(0x424ADA1CUL)) + +#define bFM_BT15_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) +#define bFM4_BT15_PWC_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) + +#define bFM_BT15_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) + +#define bFM_BT15_PWM_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_PWM_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_PWM_STC_DTIR *((volatile uint8_t *)(0x424ADA04UL)) +#define bFM4_BT15_PWM_STC_DTIR *((volatile uint8_t *)(0x424ADA04UL)) +#define bFM_BT15_PWM_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_PWM_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_PWM_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_PWM_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_PWM_STC_DTIE *((volatile uint8_t *)(0x424ADA14UL)) +#define bFM4_BT15_PWM_STC_DTIE *((volatile uint8_t *)(0x424ADA14UL)) +#define bFM_BT15_PWM_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_PWM_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) + +#define bFM_BT15_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM4_BT15_PWM_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM_BT15_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM4_BT15_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM_BT15_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM4_BT15_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424AD9A8UL)) +#define bFM_BT15_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) +#define bFM4_BT15_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424AD9ACUL)) + +#define bFM_BT15_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) + +#define bFM_BT15_RT_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM4_BT15_RT_STC_UDIR *((volatile uint8_t *)(0x424ADA00UL)) +#define bFM_BT15_RT_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM4_BT15_RT_STC_TGIR *((volatile uint8_t *)(0x424ADA08UL)) +#define bFM_BT15_RT_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM4_BT15_RT_STC_UDIE *((volatile uint8_t *)(0x424ADA10UL)) +#define bFM_BT15_RT_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) +#define bFM4_BT15_RT_STC_TGIE *((volatile uint8_t *)(0x424ADA18UL)) + +#define bFM_BT15_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM4_BT15_RT_TMCR_STRG *((volatile uint8_t *)(0x424AD980UL)) +#define bFM_BT15_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM4_BT15_RT_TMCR_CTEN *((volatile uint8_t *)(0x424AD984UL)) +#define bFM_BT15_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM4_BT15_RT_TMCR_MDSE *((volatile uint8_t *)(0x424AD988UL)) +#define bFM_BT15_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM4_BT15_RT_TMCR_OSEL *((volatile uint8_t *)(0x424AD98CUL)) +#define bFM_BT15_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) +#define bFM4_BT15_RT_TMCR_T32 *((volatile uint8_t *)(0x424AD99CUL)) + +#define bFM_BT15_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM4_BT15_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424ADA20UL)) +#define bFM_BT15_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ADA3CUL)) +#define bFM4_BT15_RT_TMCR2_GATE *((volatile uint8_t *)(0x424ADA3CUL)) + + +/******************************************************************************* +* BT Registers BT2 +* Bitband Section +*******************************************************************************/ +#define bFM_BT2_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) + +#define bFM_BT2_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM4_BT2_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM_BT2_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM4_BT2_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM_BT2_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM4_BT2_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM_BT2_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) +#define bFM4_BT2_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) + +#define bFM_BT2_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) + +#define bFM_BT2_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM_BT2_PWC_STC_ERR *((volatile uint8_t *)(0x424A121CUL)) +#define bFM4_BT2_PWC_STC_ERR *((volatile uint8_t *)(0x424A121CUL)) + +#define bFM_BT2_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) +#define bFM4_BT2_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) + +#define bFM_BT2_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) + +#define bFM_BT2_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1204UL)) +#define bFM4_BT2_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1204UL)) +#define bFM_BT2_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1214UL)) +#define bFM4_BT2_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1214UL)) +#define bFM_BT2_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) + +#define bFM_BT2_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM4_BT2_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM_BT2_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM4_BT2_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM_BT2_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM4_BT2_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A11A8UL)) +#define bFM_BT2_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) +#define bFM4_BT2_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A11ACUL)) + +#define bFM_BT2_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) + +#define bFM_BT2_RT_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM4_BT2_RT_STC_UDIR *((volatile uint8_t *)(0x424A1200UL)) +#define bFM_BT2_RT_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM4_BT2_RT_STC_TGIR *((volatile uint8_t *)(0x424A1208UL)) +#define bFM_BT2_RT_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM4_BT2_RT_STC_UDIE *((volatile uint8_t *)(0x424A1210UL)) +#define bFM_BT2_RT_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) +#define bFM4_BT2_RT_STC_TGIE *((volatile uint8_t *)(0x424A1218UL)) + +#define bFM_BT2_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM4_BT2_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1180UL)) +#define bFM_BT2_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM4_BT2_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1184UL)) +#define bFM_BT2_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM4_BT2_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1188UL)) +#define bFM_BT2_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM4_BT2_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A118CUL)) +#define bFM_BT2_RT_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) +#define bFM4_BT2_RT_TMCR_T32 *((volatile uint8_t *)(0x424A119CUL)) + +#define bFM_BT2_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM4_BT2_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1220UL)) +#define bFM_BT2_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A123CUL)) +#define bFM4_BT2_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A123CUL)) + + +/******************************************************************************* +* BT Registers BT3 +* Bitband Section +*******************************************************************************/ +#define bFM_BT3_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_PPG_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_PPG_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_PPG_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_PPG_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) + +#define bFM_BT3_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM4_BT3_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM_BT3_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM4_BT3_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM_BT3_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM4_BT3_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM_BT3_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) +#define bFM4_BT3_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) + +#define bFM_BT3_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) + +#define bFM_BT3_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_PWC_STC_OVIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_PWC_STC_EDIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_PWC_STC_OVIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_PWC_STC_EDIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM_BT3_PWC_STC_ERR *((volatile uint8_t *)(0x424A1A1CUL)) +#define bFM4_BT3_PWC_STC_ERR *((volatile uint8_t *)(0x424A1A1CUL)) + +#define bFM_BT3_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) +#define bFM4_BT3_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) + +#define bFM_BT3_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) + +#define bFM_BT3_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_PWM_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1A04UL)) +#define bFM4_BT3_PWM_STC_DTIR *((volatile uint8_t *)(0x424A1A04UL)) +#define bFM_BT3_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_PWM_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_PWM_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1A14UL)) +#define bFM4_BT3_PWM_STC_DTIE *((volatile uint8_t *)(0x424A1A14UL)) +#define bFM_BT3_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_PWM_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) + +#define bFM_BT3_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM4_BT3_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM_BT3_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM4_BT3_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM_BT3_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM4_BT3_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A19A8UL)) +#define bFM_BT3_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) +#define bFM4_BT3_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A19ACUL)) + +#define bFM_BT3_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) + +#define bFM_BT3_RT_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM4_BT3_RT_STC_UDIR *((volatile uint8_t *)(0x424A1A00UL)) +#define bFM_BT3_RT_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM4_BT3_RT_STC_TGIR *((volatile uint8_t *)(0x424A1A08UL)) +#define bFM_BT3_RT_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM4_BT3_RT_STC_UDIE *((volatile uint8_t *)(0x424A1A10UL)) +#define bFM_BT3_RT_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) +#define bFM4_BT3_RT_STC_TGIE *((volatile uint8_t *)(0x424A1A18UL)) + +#define bFM_BT3_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM4_BT3_RT_TMCR_STRG *((volatile uint8_t *)(0x424A1980UL)) +#define bFM_BT3_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM4_BT3_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A1984UL)) +#define bFM_BT3_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM4_BT3_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A1988UL)) +#define bFM_BT3_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM4_BT3_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A198CUL)) +#define bFM_BT3_RT_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) +#define bFM4_BT3_RT_TMCR_T32 *((volatile uint8_t *)(0x424A199CUL)) + +#define bFM_BT3_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM4_BT3_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A1A20UL)) +#define bFM_BT3_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A1A3CUL)) +#define bFM4_BT3_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A1A3CUL)) + + +/******************************************************************************* +* BT Registers BT4 +* Bitband Section +*******************************************************************************/ +#define bFM_BT4_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) + +#define bFM_BT4_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM4_BT4_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM_BT4_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM4_BT4_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM_BT4_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM4_BT4_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM_BT4_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) +#define bFM4_BT4_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) + +#define bFM_BT4_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) + +#define bFM_BT4_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM_BT4_PWC_STC_ERR *((volatile uint8_t *)(0x424A421CUL)) +#define bFM4_BT4_PWC_STC_ERR *((volatile uint8_t *)(0x424A421CUL)) + +#define bFM_BT4_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) +#define bFM4_BT4_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) + +#define bFM_BT4_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) + +#define bFM_BT4_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4204UL)) +#define bFM4_BT4_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4204UL)) +#define bFM_BT4_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4214UL)) +#define bFM4_BT4_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4214UL)) +#define bFM_BT4_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) + +#define bFM_BT4_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM4_BT4_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM_BT4_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM4_BT4_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM_BT4_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM4_BT4_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A41A8UL)) +#define bFM_BT4_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) +#define bFM4_BT4_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A41ACUL)) + +#define bFM_BT4_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) + +#define bFM_BT4_RT_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM4_BT4_RT_STC_UDIR *((volatile uint8_t *)(0x424A4200UL)) +#define bFM_BT4_RT_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM4_BT4_RT_STC_TGIR *((volatile uint8_t *)(0x424A4208UL)) +#define bFM_BT4_RT_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM4_BT4_RT_STC_UDIE *((volatile uint8_t *)(0x424A4210UL)) +#define bFM_BT4_RT_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) +#define bFM4_BT4_RT_STC_TGIE *((volatile uint8_t *)(0x424A4218UL)) + +#define bFM_BT4_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM4_BT4_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4180UL)) +#define bFM_BT4_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM4_BT4_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4184UL)) +#define bFM_BT4_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM4_BT4_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4188UL)) +#define bFM_BT4_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM4_BT4_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A418CUL)) +#define bFM_BT4_RT_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) +#define bFM4_BT4_RT_TMCR_T32 *((volatile uint8_t *)(0x424A419CUL)) + +#define bFM_BT4_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM4_BT4_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4220UL)) +#define bFM_BT4_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A423CUL)) +#define bFM4_BT4_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A423CUL)) + + +/******************************************************************************* +* BT Registers BT5 +* Bitband Section +*******************************************************************************/ +#define bFM_BT5_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_PPG_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_PPG_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_PPG_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_PPG_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) + +#define bFM_BT5_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM4_BT5_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM_BT5_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM4_BT5_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM_BT5_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM4_BT5_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM_BT5_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) +#define bFM4_BT5_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) + +#define bFM_BT5_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) + +#define bFM_BT5_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_PWC_STC_OVIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_PWC_STC_EDIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_PWC_STC_OVIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_PWC_STC_EDIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM_BT5_PWC_STC_ERR *((volatile uint8_t *)(0x424A4A1CUL)) +#define bFM4_BT5_PWC_STC_ERR *((volatile uint8_t *)(0x424A4A1CUL)) + +#define bFM_BT5_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) +#define bFM4_BT5_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) + +#define bFM_BT5_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) + +#define bFM_BT5_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_PWM_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4A04UL)) +#define bFM4_BT5_PWM_STC_DTIR *((volatile uint8_t *)(0x424A4A04UL)) +#define bFM_BT5_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_PWM_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_PWM_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4A14UL)) +#define bFM4_BT5_PWM_STC_DTIE *((volatile uint8_t *)(0x424A4A14UL)) +#define bFM_BT5_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_PWM_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) + +#define bFM_BT5_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM4_BT5_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM_BT5_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM4_BT5_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM_BT5_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM4_BT5_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A49A8UL)) +#define bFM_BT5_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) +#define bFM4_BT5_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A49ACUL)) + +#define bFM_BT5_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) + +#define bFM_BT5_RT_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM4_BT5_RT_STC_UDIR *((volatile uint8_t *)(0x424A4A00UL)) +#define bFM_BT5_RT_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM4_BT5_RT_STC_TGIR *((volatile uint8_t *)(0x424A4A08UL)) +#define bFM_BT5_RT_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM4_BT5_RT_STC_UDIE *((volatile uint8_t *)(0x424A4A10UL)) +#define bFM_BT5_RT_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) +#define bFM4_BT5_RT_STC_TGIE *((volatile uint8_t *)(0x424A4A18UL)) + +#define bFM_BT5_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM4_BT5_RT_TMCR_STRG *((volatile uint8_t *)(0x424A4980UL)) +#define bFM_BT5_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM4_BT5_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A4984UL)) +#define bFM_BT5_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM4_BT5_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A4988UL)) +#define bFM_BT5_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM4_BT5_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A498CUL)) +#define bFM_BT5_RT_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) +#define bFM4_BT5_RT_TMCR_T32 *((volatile uint8_t *)(0x424A499CUL)) + +#define bFM_BT5_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM4_BT5_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A4A20UL)) +#define bFM_BT5_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A4A3CUL)) +#define bFM4_BT5_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A4A3CUL)) + + +/******************************************************************************* +* BT Registers BT6 +* Bitband Section +*******************************************************************************/ +#define bFM_BT6_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) + +#define bFM_BT6_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM4_BT6_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM_BT6_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM4_BT6_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM_BT6_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM4_BT6_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM_BT6_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) +#define bFM4_BT6_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) + +#define bFM_BT6_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) + +#define bFM_BT6_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM_BT6_PWC_STC_ERR *((volatile uint8_t *)(0x424A521CUL)) +#define bFM4_BT6_PWC_STC_ERR *((volatile uint8_t *)(0x424A521CUL)) + +#define bFM_BT6_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) +#define bFM4_BT6_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) + +#define bFM_BT6_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) + +#define bFM_BT6_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5204UL)) +#define bFM4_BT6_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5204UL)) +#define bFM_BT6_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5214UL)) +#define bFM4_BT6_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5214UL)) +#define bFM_BT6_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) + +#define bFM_BT6_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM4_BT6_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM_BT6_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM4_BT6_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM_BT6_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM4_BT6_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A51A8UL)) +#define bFM_BT6_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) +#define bFM4_BT6_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A51ACUL)) + +#define bFM_BT6_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) + +#define bFM_BT6_RT_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM4_BT6_RT_STC_UDIR *((volatile uint8_t *)(0x424A5200UL)) +#define bFM_BT6_RT_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM4_BT6_RT_STC_TGIR *((volatile uint8_t *)(0x424A5208UL)) +#define bFM_BT6_RT_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM4_BT6_RT_STC_UDIE *((volatile uint8_t *)(0x424A5210UL)) +#define bFM_BT6_RT_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) +#define bFM4_BT6_RT_STC_TGIE *((volatile uint8_t *)(0x424A5218UL)) + +#define bFM_BT6_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM4_BT6_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5180UL)) +#define bFM_BT6_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM4_BT6_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5184UL)) +#define bFM_BT6_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM4_BT6_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5188UL)) +#define bFM_BT6_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM4_BT6_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A518CUL)) +#define bFM_BT6_RT_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) +#define bFM4_BT6_RT_TMCR_T32 *((volatile uint8_t *)(0x424A519CUL)) + +#define bFM_BT6_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM4_BT6_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5220UL)) +#define bFM_BT6_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A523CUL)) +#define bFM4_BT6_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A523CUL)) + + +/******************************************************************************* +* BT Registers BT7 +* Bitband Section +*******************************************************************************/ +#define bFM_BT7_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_PPG_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_PPG_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_PPG_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_PPG_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) + +#define bFM_BT7_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM4_BT7_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM_BT7_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM4_BT7_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM_BT7_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM4_BT7_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM_BT7_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) +#define bFM4_BT7_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) + +#define bFM_BT7_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) + +#define bFM_BT7_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_PWC_STC_OVIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_PWC_STC_EDIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_PWC_STC_OVIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_PWC_STC_EDIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM_BT7_PWC_STC_ERR *((volatile uint8_t *)(0x424A5A1CUL)) +#define bFM4_BT7_PWC_STC_ERR *((volatile uint8_t *)(0x424A5A1CUL)) + +#define bFM_BT7_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) +#define bFM4_BT7_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) + +#define bFM_BT7_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) + +#define bFM_BT7_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_PWM_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5A04UL)) +#define bFM4_BT7_PWM_STC_DTIR *((volatile uint8_t *)(0x424A5A04UL)) +#define bFM_BT7_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_PWM_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_PWM_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5A14UL)) +#define bFM4_BT7_PWM_STC_DTIE *((volatile uint8_t *)(0x424A5A14UL)) +#define bFM_BT7_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_PWM_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) + +#define bFM_BT7_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM4_BT7_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM_BT7_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM4_BT7_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM_BT7_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM4_BT7_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A59A8UL)) +#define bFM_BT7_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) +#define bFM4_BT7_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A59ACUL)) + +#define bFM_BT7_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) + +#define bFM_BT7_RT_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM4_BT7_RT_STC_UDIR *((volatile uint8_t *)(0x424A5A00UL)) +#define bFM_BT7_RT_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM4_BT7_RT_STC_TGIR *((volatile uint8_t *)(0x424A5A08UL)) +#define bFM_BT7_RT_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM4_BT7_RT_STC_UDIE *((volatile uint8_t *)(0x424A5A10UL)) +#define bFM_BT7_RT_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) +#define bFM4_BT7_RT_STC_TGIE *((volatile uint8_t *)(0x424A5A18UL)) + +#define bFM_BT7_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM4_BT7_RT_TMCR_STRG *((volatile uint8_t *)(0x424A5980UL)) +#define bFM_BT7_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM4_BT7_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A5984UL)) +#define bFM_BT7_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM4_BT7_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A5988UL)) +#define bFM_BT7_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM4_BT7_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A598CUL)) +#define bFM_BT7_RT_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) +#define bFM4_BT7_RT_TMCR_T32 *((volatile uint8_t *)(0x424A599CUL)) + +#define bFM_BT7_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM4_BT7_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A5A20UL)) +#define bFM_BT7_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A5A3CUL)) +#define bFM4_BT7_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A5A3CUL)) + + +/******************************************************************************* +* BT Registers BT8 +* Bitband Section +*******************************************************************************/ +#define bFM_BT8_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) + +#define bFM_BT8_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM4_BT8_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM_BT8_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM4_BT8_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM_BT8_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM4_BT8_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM_BT8_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) +#define bFM4_BT8_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) + +#define bFM_BT8_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) + +#define bFM_BT8_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM_BT8_PWC_STC_ERR *((volatile uint8_t *)(0x424A821CUL)) +#define bFM4_BT8_PWC_STC_ERR *((volatile uint8_t *)(0x424A821CUL)) + +#define bFM_BT8_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) +#define bFM4_BT8_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) + +#define bFM_BT8_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) + +#define bFM_BT8_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8204UL)) +#define bFM4_BT8_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8204UL)) +#define bFM_BT8_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8214UL)) +#define bFM4_BT8_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8214UL)) +#define bFM_BT8_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) + +#define bFM_BT8_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM4_BT8_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM_BT8_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM4_BT8_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM_BT8_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM4_BT8_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A81A8UL)) +#define bFM_BT8_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) +#define bFM4_BT8_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A81ACUL)) + +#define bFM_BT8_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) + +#define bFM_BT8_RT_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM4_BT8_RT_STC_UDIR *((volatile uint8_t *)(0x424A8200UL)) +#define bFM_BT8_RT_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM4_BT8_RT_STC_TGIR *((volatile uint8_t *)(0x424A8208UL)) +#define bFM_BT8_RT_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM4_BT8_RT_STC_UDIE *((volatile uint8_t *)(0x424A8210UL)) +#define bFM_BT8_RT_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) +#define bFM4_BT8_RT_STC_TGIE *((volatile uint8_t *)(0x424A8218UL)) + +#define bFM_BT8_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM4_BT8_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8180UL)) +#define bFM_BT8_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM4_BT8_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8184UL)) +#define bFM_BT8_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM4_BT8_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8188UL)) +#define bFM_BT8_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM4_BT8_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A818CUL)) +#define bFM_BT8_RT_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) +#define bFM4_BT8_RT_TMCR_T32 *((volatile uint8_t *)(0x424A819CUL)) + +#define bFM_BT8_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM4_BT8_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8220UL)) +#define bFM_BT8_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A823CUL)) +#define bFM4_BT8_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A823CUL)) + + +/******************************************************************************* +* BT Registers BT9 +* Bitband Section +*******************************************************************************/ +#define bFM_BT9_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_PPG_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_PPG_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_PPG_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_PPG_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) + +#define bFM_BT9_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM4_BT9_PPG_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM_BT9_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_PPG_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_PPG_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM4_BT9_PPG_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM_BT9_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM4_BT9_PPG_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM_BT9_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) +#define bFM4_BT9_PPG_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) + +#define bFM_BT9_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_PPG_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) + +#define bFM_BT9_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_PWC_STC_OVIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_PWC_STC_EDIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_PWC_STC_OVIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_PWC_STC_EDIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM_BT9_PWC_STC_ERR *((volatile uint8_t *)(0x424A8A1CUL)) +#define bFM4_BT9_PWC_STC_ERR *((volatile uint8_t *)(0x424A8A1CUL)) + +#define bFM_BT9_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_PWC_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_PWC_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) +#define bFM4_BT9_PWC_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) + +#define bFM_BT9_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_PWC_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) + +#define bFM_BT9_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_PWM_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8A04UL)) +#define bFM4_BT9_PWM_STC_DTIR *((volatile uint8_t *)(0x424A8A04UL)) +#define bFM_BT9_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_PWM_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_PWM_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8A14UL)) +#define bFM4_BT9_PWM_STC_DTIE *((volatile uint8_t *)(0x424A8A14UL)) +#define bFM_BT9_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_PWM_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) + +#define bFM_BT9_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM4_BT9_PWM_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM_BT9_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_PWM_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_PWM_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM4_BT9_PWM_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM_BT9_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM4_BT9_PWM_TMCR_PMSK *((volatile uint8_t *)(0x424A89A8UL)) +#define bFM_BT9_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) +#define bFM4_BT9_PWM_TMCR_RTGEN *((volatile uint8_t *)(0x424A89ACUL)) + +#define bFM_BT9_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_PWM_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) + +#define bFM_BT9_RT_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM4_BT9_RT_STC_UDIR *((volatile uint8_t *)(0x424A8A00UL)) +#define bFM_BT9_RT_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM4_BT9_RT_STC_TGIR *((volatile uint8_t *)(0x424A8A08UL)) +#define bFM_BT9_RT_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM4_BT9_RT_STC_UDIE *((volatile uint8_t *)(0x424A8A10UL)) +#define bFM_BT9_RT_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) +#define bFM4_BT9_RT_STC_TGIE *((volatile uint8_t *)(0x424A8A18UL)) + +#define bFM_BT9_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM4_BT9_RT_TMCR_STRG *((volatile uint8_t *)(0x424A8980UL)) +#define bFM_BT9_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM4_BT9_RT_TMCR_CTEN *((volatile uint8_t *)(0x424A8984UL)) +#define bFM_BT9_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM4_BT9_RT_TMCR_MDSE *((volatile uint8_t *)(0x424A8988UL)) +#define bFM_BT9_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM4_BT9_RT_TMCR_OSEL *((volatile uint8_t *)(0x424A898CUL)) +#define bFM_BT9_RT_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) +#define bFM4_BT9_RT_TMCR_T32 *((volatile uint8_t *)(0x424A899CUL)) + +#define bFM_BT9_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM4_BT9_RT_TMCR2_CKS3 *((volatile uint8_t *)(0x424A8A20UL)) +#define bFM_BT9_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A8A3CUL)) +#define bFM4_BT9_RT_TMCR2_GATE *((volatile uint8_t *)(0x424A8A3CUL)) + + +/******************************************************************************* +* BTIOSEL03 Registers BTIOSEL03 +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* BTIOSEL47 Registers BTIOSEL47 +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* BTIOSEL8B Registers BTIOSEL8B +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* BTIOSELCF Registers BTIOSELCF +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* CAN Registers CAN0 +* Bitband Section +*******************************************************************************/ +#define bFM_CAN0_CTRLR_INIT *((volatile uint8_t *)(0x42C40000UL)) +#define bFM4_CAN0_CTRLR_INIT *((volatile uint8_t *)(0x42C40000UL)) +#define bFM_CAN0_CTRLR_IE *((volatile uint8_t *)(0x42C40004UL)) +#define bFM4_CAN0_CTRLR_IE *((volatile uint8_t *)(0x42C40004UL)) +#define bFM_CAN0_CTRLR_SIE *((volatile uint8_t *)(0x42C40008UL)) +#define bFM4_CAN0_CTRLR_SIE *((volatile uint8_t *)(0x42C40008UL)) +#define bFM_CAN0_CTRLR_EIE *((volatile uint8_t *)(0x42C4000CUL)) +#define bFM4_CAN0_CTRLR_EIE *((volatile uint8_t *)(0x42C4000CUL)) +#define bFM_CAN0_CTRLR_DAR *((volatile uint8_t *)(0x42C40014UL)) +#define bFM4_CAN0_CTRLR_DAR *((volatile uint8_t *)(0x42C40014UL)) +#define bFM_CAN0_CTRLR_CCE *((volatile uint8_t *)(0x42C40018UL)) +#define bFM4_CAN0_CTRLR_CCE *((volatile uint8_t *)(0x42C40018UL)) +#define bFM_CAN0_CTRLR_TEST *((volatile uint8_t *)(0x42C4001CUL)) +#define bFM4_CAN0_CTRLR_TEST *((volatile uint8_t *)(0x42C4001CUL)) + +#define bFM_CAN0_ERRCNT_RP *((volatile uint8_t *)(0x42C400BCUL)) +#define bFM4_CAN0_ERRCNT_RP *((volatile uint8_t *)(0x42C400BCUL)) + +#define bFM_CAN0_IF1ARB_DIR *((volatile uint8_t *)(0x42C40374UL)) +#define bFM4_CAN0_IF1ARB_DIR *((volatile uint8_t *)(0x42C40374UL)) +#define bFM_CAN0_IF1ARB_XTD *((volatile uint8_t *)(0x42C40378UL)) +#define bFM4_CAN0_IF1ARB_XTD *((volatile uint8_t *)(0x42C40378UL)) +#define bFM_CAN0_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C4037CUL)) +#define bFM4_CAN0_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C4037CUL)) + +#define bFM_CAN0_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C40240UL)) +#define bFM4_CAN0_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C40240UL)) +#define bFM_CAN0_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C40244UL)) +#define bFM4_CAN0_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C40244UL)) +#define bFM_CAN0_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C40248UL)) +#define bFM4_CAN0_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C40248UL)) +#define bFM_CAN0_IF1CMSK_CIP *((volatile uint8_t *)(0x42C4024CUL)) +#define bFM4_CAN0_IF1CMSK_CIP *((volatile uint8_t *)(0x42C4024CUL)) +#define bFM_CAN0_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C40250UL)) +#define bFM4_CAN0_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C40250UL)) +#define bFM_CAN0_IF1CMSK_ARB *((volatile uint8_t *)(0x42C40254UL)) +#define bFM4_CAN0_IF1CMSK_ARB *((volatile uint8_t *)(0x42C40254UL)) +#define bFM_CAN0_IF1CMSK_MASK *((volatile uint8_t *)(0x42C40258UL)) +#define bFM4_CAN0_IF1CMSK_MASK *((volatile uint8_t *)(0x42C40258UL)) +#define bFM_CAN0_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C4025CUL)) +#define bFM4_CAN0_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C4025CUL)) + +#define bFM_CAN0_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C4023CUL)) +#define bFM4_CAN0_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C4023CUL)) + +#define bFM_CAN0_IF1MCTR_EOB *((volatile uint8_t *)(0x42C4039CUL)) +#define bFM4_CAN0_IF1MCTR_EOB *((volatile uint8_t *)(0x42C4039CUL)) +#define bFM_CAN0_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C403A0UL)) +#define bFM4_CAN0_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C403A0UL)) +#define bFM_CAN0_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C403A4UL)) +#define bFM4_CAN0_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C403A4UL)) +#define bFM_CAN0_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C403A8UL)) +#define bFM4_CAN0_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C403A8UL)) +#define bFM_CAN0_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C403ACUL)) +#define bFM4_CAN0_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C403ACUL)) +#define bFM_CAN0_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C403B0UL)) +#define bFM4_CAN0_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C403B0UL)) +#define bFM_CAN0_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C403B4UL)) +#define bFM4_CAN0_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C403B4UL)) +#define bFM_CAN0_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C403B8UL)) +#define bFM4_CAN0_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C403B8UL)) +#define bFM_CAN0_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C403BCUL)) +#define bFM4_CAN0_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C403BCUL)) + +#define bFM_CAN0_IF1MSK_MDIR *((volatile uint8_t *)(0x42C402F8UL)) +#define bFM4_CAN0_IF1MSK_MDIR *((volatile uint8_t *)(0x42C402F8UL)) +#define bFM_CAN0_IF1MSK_MXTD *((volatile uint8_t *)(0x42C402FCUL)) +#define bFM4_CAN0_IF1MSK_MXTD *((volatile uint8_t *)(0x42C402FCUL)) + +#define bFM_CAN0_IF2ARB_DIR *((volatile uint8_t *)(0x42C40974UL)) +#define bFM4_CAN0_IF2ARB_DIR *((volatile uint8_t *)(0x42C40974UL)) +#define bFM_CAN0_IF2ARB_XTD *((volatile uint8_t *)(0x42C40978UL)) +#define bFM4_CAN0_IF2ARB_XTD *((volatile uint8_t *)(0x42C40978UL)) +#define bFM_CAN0_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C4097CUL)) +#define bFM4_CAN0_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C4097CUL)) + +#define bFM_CAN0_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C40840UL)) +#define bFM4_CAN0_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C40840UL)) +#define bFM_CAN0_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C40844UL)) +#define bFM4_CAN0_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C40844UL)) +#define bFM_CAN0_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C40848UL)) +#define bFM4_CAN0_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C40848UL)) +#define bFM_CAN0_IF2CMSK_CIP *((volatile uint8_t *)(0x42C4084CUL)) +#define bFM4_CAN0_IF2CMSK_CIP *((volatile uint8_t *)(0x42C4084CUL)) +#define bFM_CAN0_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C40850UL)) +#define bFM4_CAN0_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C40850UL)) +#define bFM_CAN0_IF2CMSK_ARB *((volatile uint8_t *)(0x42C40854UL)) +#define bFM4_CAN0_IF2CMSK_ARB *((volatile uint8_t *)(0x42C40854UL)) +#define bFM_CAN0_IF2CMSK_MASK *((volatile uint8_t *)(0x42C40858UL)) +#define bFM4_CAN0_IF2CMSK_MASK *((volatile uint8_t *)(0x42C40858UL)) +#define bFM_CAN0_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C4085CUL)) +#define bFM4_CAN0_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C4085CUL)) + +#define bFM_CAN0_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C4083CUL)) +#define bFM4_CAN0_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C4083CUL)) + +#define bFM_CAN0_IF2MCTR_EOB *((volatile uint8_t *)(0x42C4099CUL)) +#define bFM4_CAN0_IF2MCTR_EOB *((volatile uint8_t *)(0x42C4099CUL)) +#define bFM_CAN0_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C409A0UL)) +#define bFM4_CAN0_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C409A0UL)) +#define bFM_CAN0_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C409A4UL)) +#define bFM4_CAN0_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C409A4UL)) +#define bFM_CAN0_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C409A8UL)) +#define bFM4_CAN0_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C409A8UL)) +#define bFM_CAN0_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C409ACUL)) +#define bFM4_CAN0_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C409ACUL)) +#define bFM_CAN0_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C409B0UL)) +#define bFM4_CAN0_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C409B0UL)) +#define bFM_CAN0_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C409B4UL)) +#define bFM4_CAN0_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C409B4UL)) +#define bFM_CAN0_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C409B8UL)) +#define bFM4_CAN0_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C409B8UL)) +#define bFM_CAN0_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C409BCUL)) +#define bFM4_CAN0_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C409BCUL)) + +#define bFM_CAN0_IF2MSK_MDIR *((volatile uint8_t *)(0x42C408F8UL)) +#define bFM4_CAN0_IF2MSK_MDIR *((volatile uint8_t *)(0x42C408F8UL)) +#define bFM_CAN0_IF2MSK_MXTD *((volatile uint8_t *)(0x42C408FCUL)) +#define bFM4_CAN0_IF2MSK_MXTD *((volatile uint8_t *)(0x42C408FCUL)) + +#define bFM_CAN0_INTPND_INTPND1 *((volatile uint8_t *)(0x42C41400UL)) +#define bFM4_CAN0_INTPND_INTPND1 *((volatile uint8_t *)(0x42C41400UL)) +#define bFM_CAN0_INTPND_INTPND2 *((volatile uint8_t *)(0x42C41404UL)) +#define bFM4_CAN0_INTPND_INTPND2 *((volatile uint8_t *)(0x42C41404UL)) +#define bFM_CAN0_INTPND_INTPND3 *((volatile uint8_t *)(0x42C41408UL)) +#define bFM4_CAN0_INTPND_INTPND3 *((volatile uint8_t *)(0x42C41408UL)) +#define bFM_CAN0_INTPND_INTPND4 *((volatile uint8_t *)(0x42C4140CUL)) +#define bFM4_CAN0_INTPND_INTPND4 *((volatile uint8_t *)(0x42C4140CUL)) +#define bFM_CAN0_INTPND_INTPND5 *((volatile uint8_t *)(0x42C41410UL)) +#define bFM4_CAN0_INTPND_INTPND5 *((volatile uint8_t *)(0x42C41410UL)) +#define bFM_CAN0_INTPND_INTPND6 *((volatile uint8_t *)(0x42C41414UL)) +#define bFM4_CAN0_INTPND_INTPND6 *((volatile uint8_t *)(0x42C41414UL)) +#define bFM_CAN0_INTPND_INTPND7 *((volatile uint8_t *)(0x42C41418UL)) +#define bFM4_CAN0_INTPND_INTPND7 *((volatile uint8_t *)(0x42C41418UL)) +#define bFM_CAN0_INTPND_INTPND8 *((volatile uint8_t *)(0x42C4141CUL)) +#define bFM4_CAN0_INTPND_INTPND8 *((volatile uint8_t *)(0x42C4141CUL)) +#define bFM_CAN0_INTPND_INTPND9 *((volatile uint8_t *)(0x42C41420UL)) +#define bFM4_CAN0_INTPND_INTPND9 *((volatile uint8_t *)(0x42C41420UL)) +#define bFM_CAN0_INTPND_INTPND10 *((volatile uint8_t *)(0x42C41424UL)) +#define bFM4_CAN0_INTPND_INTPND10 *((volatile uint8_t *)(0x42C41424UL)) +#define bFM_CAN0_INTPND_INTPND11 *((volatile uint8_t *)(0x42C41428UL)) +#define bFM4_CAN0_INTPND_INTPND11 *((volatile uint8_t *)(0x42C41428UL)) +#define bFM_CAN0_INTPND_INTPND12 *((volatile uint8_t *)(0x42C4142CUL)) +#define bFM4_CAN0_INTPND_INTPND12 *((volatile uint8_t *)(0x42C4142CUL)) +#define bFM_CAN0_INTPND_INTPND13 *((volatile uint8_t *)(0x42C41430UL)) +#define bFM4_CAN0_INTPND_INTPND13 *((volatile uint8_t *)(0x42C41430UL)) +#define bFM_CAN0_INTPND_INTPND14 *((volatile uint8_t *)(0x42C41434UL)) +#define bFM4_CAN0_INTPND_INTPND14 *((volatile uint8_t *)(0x42C41434UL)) +#define bFM_CAN0_INTPND_INTPND15 *((volatile uint8_t *)(0x42C41438UL)) +#define bFM4_CAN0_INTPND_INTPND15 *((volatile uint8_t *)(0x42C41438UL)) +#define bFM_CAN0_INTPND_INTPND16 *((volatile uint8_t *)(0x42C4143CUL)) +#define bFM4_CAN0_INTPND_INTPND16 *((volatile uint8_t *)(0x42C4143CUL)) +#define bFM_CAN0_INTPND_INTPND17 *((volatile uint8_t *)(0x42C41440UL)) +#define bFM4_CAN0_INTPND_INTPND17 *((volatile uint8_t *)(0x42C41440UL)) +#define bFM_CAN0_INTPND_INTPND18 *((volatile uint8_t *)(0x42C41444UL)) +#define bFM4_CAN0_INTPND_INTPND18 *((volatile uint8_t *)(0x42C41444UL)) +#define bFM_CAN0_INTPND_INTPND19 *((volatile uint8_t *)(0x42C41448UL)) +#define bFM4_CAN0_INTPND_INTPND19 *((volatile uint8_t *)(0x42C41448UL)) +#define bFM_CAN0_INTPND_INTPND20 *((volatile uint8_t *)(0x42C4144CUL)) +#define bFM4_CAN0_INTPND_INTPND20 *((volatile uint8_t *)(0x42C4144CUL)) +#define bFM_CAN0_INTPND_INTPND21 *((volatile uint8_t *)(0x42C41450UL)) +#define bFM4_CAN0_INTPND_INTPND21 *((volatile uint8_t *)(0x42C41450UL)) +#define bFM_CAN0_INTPND_INTPND22 *((volatile uint8_t *)(0x42C41454UL)) +#define bFM4_CAN0_INTPND_INTPND22 *((volatile uint8_t *)(0x42C41454UL)) +#define bFM_CAN0_INTPND_INTPND23 *((volatile uint8_t *)(0x42C41458UL)) +#define bFM4_CAN0_INTPND_INTPND23 *((volatile uint8_t *)(0x42C41458UL)) +#define bFM_CAN0_INTPND_INTPND24 *((volatile uint8_t *)(0x42C4145CUL)) +#define bFM4_CAN0_INTPND_INTPND24 *((volatile uint8_t *)(0x42C4145CUL)) +#define bFM_CAN0_INTPND_INTPND25 *((volatile uint8_t *)(0x42C41460UL)) +#define bFM4_CAN0_INTPND_INTPND25 *((volatile uint8_t *)(0x42C41460UL)) +#define bFM_CAN0_INTPND_INTPND26 *((volatile uint8_t *)(0x42C41464UL)) +#define bFM4_CAN0_INTPND_INTPND26 *((volatile uint8_t *)(0x42C41464UL)) +#define bFM_CAN0_INTPND_INTPND27 *((volatile uint8_t *)(0x42C41468UL)) +#define bFM4_CAN0_INTPND_INTPND27 *((volatile uint8_t *)(0x42C41468UL)) +#define bFM_CAN0_INTPND_INTPND28 *((volatile uint8_t *)(0x42C4146CUL)) +#define bFM4_CAN0_INTPND_INTPND28 *((volatile uint8_t *)(0x42C4146CUL)) +#define bFM_CAN0_INTPND_INTPND29 *((volatile uint8_t *)(0x42C41470UL)) +#define bFM4_CAN0_INTPND_INTPND29 *((volatile uint8_t *)(0x42C41470UL)) +#define bFM_CAN0_INTPND_INTPND30 *((volatile uint8_t *)(0x42C41474UL)) +#define bFM4_CAN0_INTPND_INTPND30 *((volatile uint8_t *)(0x42C41474UL)) +#define bFM_CAN0_INTPND_INTPND31 *((volatile uint8_t *)(0x42C41478UL)) +#define bFM4_CAN0_INTPND_INTPND31 *((volatile uint8_t *)(0x42C41478UL)) +#define bFM_CAN0_INTPND_INTPND32 *((volatile uint8_t *)(0x42C4147CUL)) +#define bFM4_CAN0_INTPND_INTPND32 *((volatile uint8_t *)(0x42C4147CUL)) + +#define bFM_CAN0_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C41600UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C41600UL)) +#define bFM_CAN0_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C41604UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C41604UL)) +#define bFM_CAN0_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C41608UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C41608UL)) +#define bFM_CAN0_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C4160CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C4160CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C41610UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C41610UL)) +#define bFM_CAN0_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C41614UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C41614UL)) +#define bFM_CAN0_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C41618UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C41618UL)) +#define bFM_CAN0_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C4161CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C4161CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C41620UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C41620UL)) +#define bFM_CAN0_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C41624UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C41624UL)) +#define bFM_CAN0_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C41628UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C41628UL)) +#define bFM_CAN0_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C4162CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C4162CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C41630UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C41630UL)) +#define bFM_CAN0_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C41634UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C41634UL)) +#define bFM_CAN0_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C41638UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C41638UL)) +#define bFM_CAN0_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C4163CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C4163CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C41640UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C41640UL)) +#define bFM_CAN0_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C41644UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C41644UL)) +#define bFM_CAN0_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C41648UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C41648UL)) +#define bFM_CAN0_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C4164CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C4164CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C41650UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C41650UL)) +#define bFM_CAN0_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C41654UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C41654UL)) +#define bFM_CAN0_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C41658UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C41658UL)) +#define bFM_CAN0_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C4165CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C4165CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C41660UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C41660UL)) +#define bFM_CAN0_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C41664UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C41664UL)) +#define bFM_CAN0_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C41668UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C41668UL)) +#define bFM_CAN0_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C4166CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C4166CUL)) +#define bFM_CAN0_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C41670UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C41670UL)) +#define bFM_CAN0_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C41674UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C41674UL)) +#define bFM_CAN0_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C41678UL)) +#define bFM4_CAN0_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C41678UL)) +#define bFM_CAN0_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C4167CUL)) +#define bFM4_CAN0_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C4167CUL)) + +#define bFM_CAN0_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C41200UL)) +#define bFM4_CAN0_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C41200UL)) +#define bFM_CAN0_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C41204UL)) +#define bFM4_CAN0_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C41204UL)) +#define bFM_CAN0_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C41208UL)) +#define bFM4_CAN0_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C41208UL)) +#define bFM_CAN0_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C4120CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C4120CUL)) +#define bFM_CAN0_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C41210UL)) +#define bFM4_CAN0_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C41210UL)) +#define bFM_CAN0_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C41214UL)) +#define bFM4_CAN0_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C41214UL)) +#define bFM_CAN0_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C41218UL)) +#define bFM4_CAN0_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C41218UL)) +#define bFM_CAN0_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C4121CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C4121CUL)) +#define bFM_CAN0_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C41220UL)) +#define bFM4_CAN0_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C41220UL)) +#define bFM_CAN0_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C41224UL)) +#define bFM4_CAN0_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C41224UL)) +#define bFM_CAN0_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C41228UL)) +#define bFM4_CAN0_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C41228UL)) +#define bFM_CAN0_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C4122CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C4122CUL)) +#define bFM_CAN0_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C41230UL)) +#define bFM4_CAN0_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C41230UL)) +#define bFM_CAN0_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C41234UL)) +#define bFM4_CAN0_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C41234UL)) +#define bFM_CAN0_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C41238UL)) +#define bFM4_CAN0_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C41238UL)) +#define bFM_CAN0_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C4123CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C4123CUL)) +#define bFM_CAN0_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C41240UL)) +#define bFM4_CAN0_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C41240UL)) +#define bFM_CAN0_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C41244UL)) +#define bFM4_CAN0_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C41244UL)) +#define bFM_CAN0_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C41248UL)) +#define bFM4_CAN0_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C41248UL)) +#define bFM_CAN0_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C4124CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C4124CUL)) +#define bFM_CAN0_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C41250UL)) +#define bFM4_CAN0_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C41250UL)) +#define bFM_CAN0_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C41254UL)) +#define bFM4_CAN0_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C41254UL)) +#define bFM_CAN0_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C41258UL)) +#define bFM4_CAN0_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C41258UL)) +#define bFM_CAN0_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C4125CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C4125CUL)) +#define bFM_CAN0_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C41260UL)) +#define bFM4_CAN0_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C41260UL)) +#define bFM_CAN0_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C41264UL)) +#define bFM4_CAN0_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C41264UL)) +#define bFM_CAN0_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C41268UL)) +#define bFM4_CAN0_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C41268UL)) +#define bFM_CAN0_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C4126CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C4126CUL)) +#define bFM_CAN0_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C41270UL)) +#define bFM4_CAN0_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C41270UL)) +#define bFM_CAN0_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C41274UL)) +#define bFM4_CAN0_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C41274UL)) +#define bFM_CAN0_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C41278UL)) +#define bFM4_CAN0_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C41278UL)) +#define bFM_CAN0_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C4127CUL)) +#define bFM4_CAN0_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C4127CUL)) + +#define bFM_CAN0_STATR_TXOK *((volatile uint8_t *)(0x42C4004CUL)) +#define bFM4_CAN0_STATR_TXOK *((volatile uint8_t *)(0x42C4004CUL)) +#define bFM_CAN0_STATR_RXOK *((volatile uint8_t *)(0x42C40050UL)) +#define bFM4_CAN0_STATR_RXOK *((volatile uint8_t *)(0x42C40050UL)) +#define bFM_CAN0_STATR_EPASS *((volatile uint8_t *)(0x42C40054UL)) +#define bFM4_CAN0_STATR_EPASS *((volatile uint8_t *)(0x42C40054UL)) +#define bFM_CAN0_STATR_EWARN *((volatile uint8_t *)(0x42C40058UL)) +#define bFM4_CAN0_STATR_EWARN *((volatile uint8_t *)(0x42C40058UL)) +#define bFM_CAN0_STATR_BOFF *((volatile uint8_t *)(0x42C4005CUL)) +#define bFM4_CAN0_STATR_BOFF *((volatile uint8_t *)(0x42C4005CUL)) + +#define bFM_CAN0_TESTR_BASIC *((volatile uint8_t *)(0x42C40148UL)) +#define bFM4_CAN0_TESTR_BASIC *((volatile uint8_t *)(0x42C40148UL)) +#define bFM_CAN0_TESTR_SILENT *((volatile uint8_t *)(0x42C4014CUL)) +#define bFM4_CAN0_TESTR_SILENT *((volatile uint8_t *)(0x42C4014CUL)) +#define bFM_CAN0_TESTR_LBACK *((volatile uint8_t *)(0x42C40150UL)) +#define bFM4_CAN0_TESTR_LBACK *((volatile uint8_t *)(0x42C40150UL)) +#define bFM_CAN0_TESTR_RX *((volatile uint8_t *)(0x42C4015CUL)) +#define bFM4_CAN0_TESTR_RX *((volatile uint8_t *)(0x42C4015CUL)) + +#define bFM_CAN0_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C41000UL)) +#define bFM4_CAN0_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C41000UL)) +#define bFM_CAN0_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C41004UL)) +#define bFM4_CAN0_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C41004UL)) +#define bFM_CAN0_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C41008UL)) +#define bFM4_CAN0_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C41008UL)) +#define bFM_CAN0_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C4100CUL)) +#define bFM4_CAN0_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C4100CUL)) +#define bFM_CAN0_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C41010UL)) +#define bFM4_CAN0_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C41010UL)) +#define bFM_CAN0_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C41014UL)) +#define bFM4_CAN0_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C41014UL)) +#define bFM_CAN0_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C41018UL)) +#define bFM4_CAN0_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C41018UL)) +#define bFM_CAN0_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C4101CUL)) +#define bFM4_CAN0_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C4101CUL)) +#define bFM_CAN0_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C41020UL)) +#define bFM4_CAN0_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C41020UL)) +#define bFM_CAN0_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C41024UL)) +#define bFM4_CAN0_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C41024UL)) +#define bFM_CAN0_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C41028UL)) +#define bFM4_CAN0_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C41028UL)) +#define bFM_CAN0_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C4102CUL)) +#define bFM4_CAN0_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C4102CUL)) +#define bFM_CAN0_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C41030UL)) +#define bFM4_CAN0_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C41030UL)) +#define bFM_CAN0_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C41034UL)) +#define bFM4_CAN0_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C41034UL)) +#define bFM_CAN0_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C41038UL)) +#define bFM4_CAN0_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C41038UL)) +#define bFM_CAN0_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C4103CUL)) +#define bFM4_CAN0_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C4103CUL)) +#define bFM_CAN0_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C41040UL)) +#define bFM4_CAN0_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C41040UL)) +#define bFM_CAN0_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C41044UL)) +#define bFM4_CAN0_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C41044UL)) +#define bFM_CAN0_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C41048UL)) +#define bFM4_CAN0_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C41048UL)) +#define bFM_CAN0_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C4104CUL)) +#define bFM4_CAN0_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C4104CUL)) +#define bFM_CAN0_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C41050UL)) +#define bFM4_CAN0_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C41050UL)) +#define bFM_CAN0_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C41054UL)) +#define bFM4_CAN0_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C41054UL)) +#define bFM_CAN0_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C41058UL)) +#define bFM4_CAN0_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C41058UL)) +#define bFM_CAN0_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C4105CUL)) +#define bFM4_CAN0_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C4105CUL)) +#define bFM_CAN0_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C41060UL)) +#define bFM4_CAN0_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C41060UL)) +#define bFM_CAN0_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C41064UL)) +#define bFM4_CAN0_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C41064UL)) +#define bFM_CAN0_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C41068UL)) +#define bFM4_CAN0_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C41068UL)) +#define bFM_CAN0_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C4106CUL)) +#define bFM4_CAN0_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C4106CUL)) +#define bFM_CAN0_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C41070UL)) +#define bFM4_CAN0_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C41070UL)) +#define bFM_CAN0_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C41074UL)) +#define bFM4_CAN0_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C41074UL)) +#define bFM_CAN0_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C41078UL)) +#define bFM4_CAN0_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C41078UL)) +#define bFM_CAN0_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C4107CUL)) +#define bFM4_CAN0_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C4107CUL)) + + +/******************************************************************************* +* CAN Registers CAN1 +* Bitband Section +*******************************************************************************/ +#define bFM_CAN1_CTRLR_INIT *((volatile uint8_t *)(0x42C60000UL)) +#define bFM4_CAN1_CTRLR_INIT *((volatile uint8_t *)(0x42C60000UL)) +#define bFM_CAN1_CTRLR_IE *((volatile uint8_t *)(0x42C60004UL)) +#define bFM4_CAN1_CTRLR_IE *((volatile uint8_t *)(0x42C60004UL)) +#define bFM_CAN1_CTRLR_SIE *((volatile uint8_t *)(0x42C60008UL)) +#define bFM4_CAN1_CTRLR_SIE *((volatile uint8_t *)(0x42C60008UL)) +#define bFM_CAN1_CTRLR_EIE *((volatile uint8_t *)(0x42C6000CUL)) +#define bFM4_CAN1_CTRLR_EIE *((volatile uint8_t *)(0x42C6000CUL)) +#define bFM_CAN1_CTRLR_DAR *((volatile uint8_t *)(0x42C60014UL)) +#define bFM4_CAN1_CTRLR_DAR *((volatile uint8_t *)(0x42C60014UL)) +#define bFM_CAN1_CTRLR_CCE *((volatile uint8_t *)(0x42C60018UL)) +#define bFM4_CAN1_CTRLR_CCE *((volatile uint8_t *)(0x42C60018UL)) +#define bFM_CAN1_CTRLR_TEST *((volatile uint8_t *)(0x42C6001CUL)) +#define bFM4_CAN1_CTRLR_TEST *((volatile uint8_t *)(0x42C6001CUL)) + +#define bFM_CAN1_ERRCNT_RP *((volatile uint8_t *)(0x42C600BCUL)) +#define bFM4_CAN1_ERRCNT_RP *((volatile uint8_t *)(0x42C600BCUL)) + +#define bFM_CAN1_IF1ARB_DIR *((volatile uint8_t *)(0x42C60374UL)) +#define bFM4_CAN1_IF1ARB_DIR *((volatile uint8_t *)(0x42C60374UL)) +#define bFM_CAN1_IF1ARB_XTD *((volatile uint8_t *)(0x42C60378UL)) +#define bFM4_CAN1_IF1ARB_XTD *((volatile uint8_t *)(0x42C60378UL)) +#define bFM_CAN1_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C6037CUL)) +#define bFM4_CAN1_IF1ARB_MSGVAL *((volatile uint8_t *)(0x42C6037CUL)) + +#define bFM_CAN1_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C60240UL)) +#define bFM4_CAN1_IF1CMSK_DATAB *((volatile uint8_t *)(0x42C60240UL)) +#define bFM_CAN1_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C60244UL)) +#define bFM4_CAN1_IF1CMSK_DATAA *((volatile uint8_t *)(0x42C60244UL)) +#define bFM_CAN1_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C60248UL)) +#define bFM4_CAN1_IF1CMSK_NEWDAT *((volatile uint8_t *)(0x42C60248UL)) +#define bFM_CAN1_IF1CMSK_CIP *((volatile uint8_t *)(0x42C6024CUL)) +#define bFM4_CAN1_IF1CMSK_CIP *((volatile uint8_t *)(0x42C6024CUL)) +#define bFM_CAN1_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C60250UL)) +#define bFM4_CAN1_IF1CMSK_CONTROL *((volatile uint8_t *)(0x42C60250UL)) +#define bFM_CAN1_IF1CMSK_ARB *((volatile uint8_t *)(0x42C60254UL)) +#define bFM4_CAN1_IF1CMSK_ARB *((volatile uint8_t *)(0x42C60254UL)) +#define bFM_CAN1_IF1CMSK_MASK *((volatile uint8_t *)(0x42C60258UL)) +#define bFM4_CAN1_IF1CMSK_MASK *((volatile uint8_t *)(0x42C60258UL)) +#define bFM_CAN1_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C6025CUL)) +#define bFM4_CAN1_IF1CMSK_WR_RD *((volatile uint8_t *)(0x42C6025CUL)) + +#define bFM_CAN1_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C6023CUL)) +#define bFM4_CAN1_IF1CREQ_BUSY *((volatile uint8_t *)(0x42C6023CUL)) + +#define bFM_CAN1_IF1MCTR_EOB *((volatile uint8_t *)(0x42C6039CUL)) +#define bFM4_CAN1_IF1MCTR_EOB *((volatile uint8_t *)(0x42C6039CUL)) +#define bFM_CAN1_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C603A0UL)) +#define bFM4_CAN1_IF1MCTR_TXRQST *((volatile uint8_t *)(0x42C603A0UL)) +#define bFM_CAN1_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C603A4UL)) +#define bFM4_CAN1_IF1MCTR_RMTEN *((volatile uint8_t *)(0x42C603A4UL)) +#define bFM_CAN1_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C603A8UL)) +#define bFM4_CAN1_IF1MCTR_RXIE *((volatile uint8_t *)(0x42C603A8UL)) +#define bFM_CAN1_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C603ACUL)) +#define bFM4_CAN1_IF1MCTR_TXIE *((volatile uint8_t *)(0x42C603ACUL)) +#define bFM_CAN1_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C603B0UL)) +#define bFM4_CAN1_IF1MCTR_UMASK *((volatile uint8_t *)(0x42C603B0UL)) +#define bFM_CAN1_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C603B4UL)) +#define bFM4_CAN1_IF1MCTR_INTPND *((volatile uint8_t *)(0x42C603B4UL)) +#define bFM_CAN1_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C603B8UL)) +#define bFM4_CAN1_IF1MCTR_MSGLST *((volatile uint8_t *)(0x42C603B8UL)) +#define bFM_CAN1_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C603BCUL)) +#define bFM4_CAN1_IF1MCTR_NEWDAT *((volatile uint8_t *)(0x42C603BCUL)) + +#define bFM_CAN1_IF1MSK_MDIR *((volatile uint8_t *)(0x42C602F8UL)) +#define bFM4_CAN1_IF1MSK_MDIR *((volatile uint8_t *)(0x42C602F8UL)) +#define bFM_CAN1_IF1MSK_MXTD *((volatile uint8_t *)(0x42C602FCUL)) +#define bFM4_CAN1_IF1MSK_MXTD *((volatile uint8_t *)(0x42C602FCUL)) + +#define bFM_CAN1_IF2ARB_DIR *((volatile uint8_t *)(0x42C60974UL)) +#define bFM4_CAN1_IF2ARB_DIR *((volatile uint8_t *)(0x42C60974UL)) +#define bFM_CAN1_IF2ARB_XTD *((volatile uint8_t *)(0x42C60978UL)) +#define bFM4_CAN1_IF2ARB_XTD *((volatile uint8_t *)(0x42C60978UL)) +#define bFM_CAN1_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C6097CUL)) +#define bFM4_CAN1_IF2ARB_MSGVAL *((volatile uint8_t *)(0x42C6097CUL)) + +#define bFM_CAN1_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C60840UL)) +#define bFM4_CAN1_IF2CMSK_DATAB *((volatile uint8_t *)(0x42C60840UL)) +#define bFM_CAN1_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C60844UL)) +#define bFM4_CAN1_IF2CMSK_DATAA *((volatile uint8_t *)(0x42C60844UL)) +#define bFM_CAN1_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C60848UL)) +#define bFM4_CAN1_IF2CMSK_NEWDAT *((volatile uint8_t *)(0x42C60848UL)) +#define bFM_CAN1_IF2CMSK_CIP *((volatile uint8_t *)(0x42C6084CUL)) +#define bFM4_CAN1_IF2CMSK_CIP *((volatile uint8_t *)(0x42C6084CUL)) +#define bFM_CAN1_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C60850UL)) +#define bFM4_CAN1_IF2CMSK_CONTROL *((volatile uint8_t *)(0x42C60850UL)) +#define bFM_CAN1_IF2CMSK_ARB *((volatile uint8_t *)(0x42C60854UL)) +#define bFM4_CAN1_IF2CMSK_ARB *((volatile uint8_t *)(0x42C60854UL)) +#define bFM_CAN1_IF2CMSK_MASK *((volatile uint8_t *)(0x42C60858UL)) +#define bFM4_CAN1_IF2CMSK_MASK *((volatile uint8_t *)(0x42C60858UL)) +#define bFM_CAN1_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C6085CUL)) +#define bFM4_CAN1_IF2CMSK_WR_RD *((volatile uint8_t *)(0x42C6085CUL)) + +#define bFM_CAN1_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C6083CUL)) +#define bFM4_CAN1_IF2CREQ_BUSY *((volatile uint8_t *)(0x42C6083CUL)) + +#define bFM_CAN1_IF2MCTR_EOB *((volatile uint8_t *)(0x42C6099CUL)) +#define bFM4_CAN1_IF2MCTR_EOB *((volatile uint8_t *)(0x42C6099CUL)) +#define bFM_CAN1_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C609A0UL)) +#define bFM4_CAN1_IF2MCTR_TXRQST *((volatile uint8_t *)(0x42C609A0UL)) +#define bFM_CAN1_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C609A4UL)) +#define bFM4_CAN1_IF2MCTR_RMTEN *((volatile uint8_t *)(0x42C609A4UL)) +#define bFM_CAN1_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C609A8UL)) +#define bFM4_CAN1_IF2MCTR_RXIE *((volatile uint8_t *)(0x42C609A8UL)) +#define bFM_CAN1_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C609ACUL)) +#define bFM4_CAN1_IF2MCTR_TXIE *((volatile uint8_t *)(0x42C609ACUL)) +#define bFM_CAN1_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C609B0UL)) +#define bFM4_CAN1_IF2MCTR_UMASK *((volatile uint8_t *)(0x42C609B0UL)) +#define bFM_CAN1_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C609B4UL)) +#define bFM4_CAN1_IF2MCTR_INTPND *((volatile uint8_t *)(0x42C609B4UL)) +#define bFM_CAN1_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C609B8UL)) +#define bFM4_CAN1_IF2MCTR_MSGLST *((volatile uint8_t *)(0x42C609B8UL)) +#define bFM_CAN1_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C609BCUL)) +#define bFM4_CAN1_IF2MCTR_NEWDAT *((volatile uint8_t *)(0x42C609BCUL)) + +#define bFM_CAN1_IF2MSK_MDIR *((volatile uint8_t *)(0x42C608F8UL)) +#define bFM4_CAN1_IF2MSK_MDIR *((volatile uint8_t *)(0x42C608F8UL)) +#define bFM_CAN1_IF2MSK_MXTD *((volatile uint8_t *)(0x42C608FCUL)) +#define bFM4_CAN1_IF2MSK_MXTD *((volatile uint8_t *)(0x42C608FCUL)) + +#define bFM_CAN1_INTPND_INTPND1 *((volatile uint8_t *)(0x42C61400UL)) +#define bFM4_CAN1_INTPND_INTPND1 *((volatile uint8_t *)(0x42C61400UL)) +#define bFM_CAN1_INTPND_INTPND2 *((volatile uint8_t *)(0x42C61404UL)) +#define bFM4_CAN1_INTPND_INTPND2 *((volatile uint8_t *)(0x42C61404UL)) +#define bFM_CAN1_INTPND_INTPND3 *((volatile uint8_t *)(0x42C61408UL)) +#define bFM4_CAN1_INTPND_INTPND3 *((volatile uint8_t *)(0x42C61408UL)) +#define bFM_CAN1_INTPND_INTPND4 *((volatile uint8_t *)(0x42C6140CUL)) +#define bFM4_CAN1_INTPND_INTPND4 *((volatile uint8_t *)(0x42C6140CUL)) +#define bFM_CAN1_INTPND_INTPND5 *((volatile uint8_t *)(0x42C61410UL)) +#define bFM4_CAN1_INTPND_INTPND5 *((volatile uint8_t *)(0x42C61410UL)) +#define bFM_CAN1_INTPND_INTPND6 *((volatile uint8_t *)(0x42C61414UL)) +#define bFM4_CAN1_INTPND_INTPND6 *((volatile uint8_t *)(0x42C61414UL)) +#define bFM_CAN1_INTPND_INTPND7 *((volatile uint8_t *)(0x42C61418UL)) +#define bFM4_CAN1_INTPND_INTPND7 *((volatile uint8_t *)(0x42C61418UL)) +#define bFM_CAN1_INTPND_INTPND8 *((volatile uint8_t *)(0x42C6141CUL)) +#define bFM4_CAN1_INTPND_INTPND8 *((volatile uint8_t *)(0x42C6141CUL)) +#define bFM_CAN1_INTPND_INTPND9 *((volatile uint8_t *)(0x42C61420UL)) +#define bFM4_CAN1_INTPND_INTPND9 *((volatile uint8_t *)(0x42C61420UL)) +#define bFM_CAN1_INTPND_INTPND10 *((volatile uint8_t *)(0x42C61424UL)) +#define bFM4_CAN1_INTPND_INTPND10 *((volatile uint8_t *)(0x42C61424UL)) +#define bFM_CAN1_INTPND_INTPND11 *((volatile uint8_t *)(0x42C61428UL)) +#define bFM4_CAN1_INTPND_INTPND11 *((volatile uint8_t *)(0x42C61428UL)) +#define bFM_CAN1_INTPND_INTPND12 *((volatile uint8_t *)(0x42C6142CUL)) +#define bFM4_CAN1_INTPND_INTPND12 *((volatile uint8_t *)(0x42C6142CUL)) +#define bFM_CAN1_INTPND_INTPND13 *((volatile uint8_t *)(0x42C61430UL)) +#define bFM4_CAN1_INTPND_INTPND13 *((volatile uint8_t *)(0x42C61430UL)) +#define bFM_CAN1_INTPND_INTPND14 *((volatile uint8_t *)(0x42C61434UL)) +#define bFM4_CAN1_INTPND_INTPND14 *((volatile uint8_t *)(0x42C61434UL)) +#define bFM_CAN1_INTPND_INTPND15 *((volatile uint8_t *)(0x42C61438UL)) +#define bFM4_CAN1_INTPND_INTPND15 *((volatile uint8_t *)(0x42C61438UL)) +#define bFM_CAN1_INTPND_INTPND16 *((volatile uint8_t *)(0x42C6143CUL)) +#define bFM4_CAN1_INTPND_INTPND16 *((volatile uint8_t *)(0x42C6143CUL)) +#define bFM_CAN1_INTPND_INTPND17 *((volatile uint8_t *)(0x42C61440UL)) +#define bFM4_CAN1_INTPND_INTPND17 *((volatile uint8_t *)(0x42C61440UL)) +#define bFM_CAN1_INTPND_INTPND18 *((volatile uint8_t *)(0x42C61444UL)) +#define bFM4_CAN1_INTPND_INTPND18 *((volatile uint8_t *)(0x42C61444UL)) +#define bFM_CAN1_INTPND_INTPND19 *((volatile uint8_t *)(0x42C61448UL)) +#define bFM4_CAN1_INTPND_INTPND19 *((volatile uint8_t *)(0x42C61448UL)) +#define bFM_CAN1_INTPND_INTPND20 *((volatile uint8_t *)(0x42C6144CUL)) +#define bFM4_CAN1_INTPND_INTPND20 *((volatile uint8_t *)(0x42C6144CUL)) +#define bFM_CAN1_INTPND_INTPND21 *((volatile uint8_t *)(0x42C61450UL)) +#define bFM4_CAN1_INTPND_INTPND21 *((volatile uint8_t *)(0x42C61450UL)) +#define bFM_CAN1_INTPND_INTPND22 *((volatile uint8_t *)(0x42C61454UL)) +#define bFM4_CAN1_INTPND_INTPND22 *((volatile uint8_t *)(0x42C61454UL)) +#define bFM_CAN1_INTPND_INTPND23 *((volatile uint8_t *)(0x42C61458UL)) +#define bFM4_CAN1_INTPND_INTPND23 *((volatile uint8_t *)(0x42C61458UL)) +#define bFM_CAN1_INTPND_INTPND24 *((volatile uint8_t *)(0x42C6145CUL)) +#define bFM4_CAN1_INTPND_INTPND24 *((volatile uint8_t *)(0x42C6145CUL)) +#define bFM_CAN1_INTPND_INTPND25 *((volatile uint8_t *)(0x42C61460UL)) +#define bFM4_CAN1_INTPND_INTPND25 *((volatile uint8_t *)(0x42C61460UL)) +#define bFM_CAN1_INTPND_INTPND26 *((volatile uint8_t *)(0x42C61464UL)) +#define bFM4_CAN1_INTPND_INTPND26 *((volatile uint8_t *)(0x42C61464UL)) +#define bFM_CAN1_INTPND_INTPND27 *((volatile uint8_t *)(0x42C61468UL)) +#define bFM4_CAN1_INTPND_INTPND27 *((volatile uint8_t *)(0x42C61468UL)) +#define bFM_CAN1_INTPND_INTPND28 *((volatile uint8_t *)(0x42C6146CUL)) +#define bFM4_CAN1_INTPND_INTPND28 *((volatile uint8_t *)(0x42C6146CUL)) +#define bFM_CAN1_INTPND_INTPND29 *((volatile uint8_t *)(0x42C61470UL)) +#define bFM4_CAN1_INTPND_INTPND29 *((volatile uint8_t *)(0x42C61470UL)) +#define bFM_CAN1_INTPND_INTPND30 *((volatile uint8_t *)(0x42C61474UL)) +#define bFM4_CAN1_INTPND_INTPND30 *((volatile uint8_t *)(0x42C61474UL)) +#define bFM_CAN1_INTPND_INTPND31 *((volatile uint8_t *)(0x42C61478UL)) +#define bFM4_CAN1_INTPND_INTPND31 *((volatile uint8_t *)(0x42C61478UL)) +#define bFM_CAN1_INTPND_INTPND32 *((volatile uint8_t *)(0x42C6147CUL)) +#define bFM4_CAN1_INTPND_INTPND32 *((volatile uint8_t *)(0x42C6147CUL)) + +#define bFM_CAN1_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C61600UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL1 *((volatile uint8_t *)(0x42C61600UL)) +#define bFM_CAN1_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C61604UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL2 *((volatile uint8_t *)(0x42C61604UL)) +#define bFM_CAN1_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C61608UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL3 *((volatile uint8_t *)(0x42C61608UL)) +#define bFM_CAN1_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C6160CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL4 *((volatile uint8_t *)(0x42C6160CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C61610UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL5 *((volatile uint8_t *)(0x42C61610UL)) +#define bFM_CAN1_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C61614UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL6 *((volatile uint8_t *)(0x42C61614UL)) +#define bFM_CAN1_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C61618UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL7 *((volatile uint8_t *)(0x42C61618UL)) +#define bFM_CAN1_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C6161CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL8 *((volatile uint8_t *)(0x42C6161CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C61620UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL9 *((volatile uint8_t *)(0x42C61620UL)) +#define bFM_CAN1_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C61624UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL10 *((volatile uint8_t *)(0x42C61624UL)) +#define bFM_CAN1_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C61628UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL11 *((volatile uint8_t *)(0x42C61628UL)) +#define bFM_CAN1_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C6162CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL12 *((volatile uint8_t *)(0x42C6162CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C61630UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL13 *((volatile uint8_t *)(0x42C61630UL)) +#define bFM_CAN1_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C61634UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL14 *((volatile uint8_t *)(0x42C61634UL)) +#define bFM_CAN1_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C61638UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL15 *((volatile uint8_t *)(0x42C61638UL)) +#define bFM_CAN1_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C6163CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL16 *((volatile uint8_t *)(0x42C6163CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C61640UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL17 *((volatile uint8_t *)(0x42C61640UL)) +#define bFM_CAN1_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C61644UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL18 *((volatile uint8_t *)(0x42C61644UL)) +#define bFM_CAN1_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C61648UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL19 *((volatile uint8_t *)(0x42C61648UL)) +#define bFM_CAN1_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C6164CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL20 *((volatile uint8_t *)(0x42C6164CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C61650UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL21 *((volatile uint8_t *)(0x42C61650UL)) +#define bFM_CAN1_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C61654UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL22 *((volatile uint8_t *)(0x42C61654UL)) +#define bFM_CAN1_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C61658UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL23 *((volatile uint8_t *)(0x42C61658UL)) +#define bFM_CAN1_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C6165CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL24 *((volatile uint8_t *)(0x42C6165CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C61660UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL25 *((volatile uint8_t *)(0x42C61660UL)) +#define bFM_CAN1_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C61664UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL26 *((volatile uint8_t *)(0x42C61664UL)) +#define bFM_CAN1_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C61668UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL27 *((volatile uint8_t *)(0x42C61668UL)) +#define bFM_CAN1_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C6166CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL28 *((volatile uint8_t *)(0x42C6166CUL)) +#define bFM_CAN1_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C61670UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL29 *((volatile uint8_t *)(0x42C61670UL)) +#define bFM_CAN1_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C61674UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL30 *((volatile uint8_t *)(0x42C61674UL)) +#define bFM_CAN1_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C61678UL)) +#define bFM4_CAN1_MSGVAL_MSGVAL31 *((volatile uint8_t *)(0x42C61678UL)) +#define bFM_CAN1_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C6167CUL)) +#define bFM4_CAN1_MSGVAL_MSGVAL32 *((volatile uint8_t *)(0x42C6167CUL)) + +#define bFM_CAN1_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C61200UL)) +#define bFM4_CAN1_NEWDT_NEWDAT1 *((volatile uint8_t *)(0x42C61200UL)) +#define bFM_CAN1_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C61204UL)) +#define bFM4_CAN1_NEWDT_NEWDAT2 *((volatile uint8_t *)(0x42C61204UL)) +#define bFM_CAN1_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C61208UL)) +#define bFM4_CAN1_NEWDT_NEWDAT3 *((volatile uint8_t *)(0x42C61208UL)) +#define bFM_CAN1_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C6120CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT4 *((volatile uint8_t *)(0x42C6120CUL)) +#define bFM_CAN1_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C61210UL)) +#define bFM4_CAN1_NEWDT_NEWDAT5 *((volatile uint8_t *)(0x42C61210UL)) +#define bFM_CAN1_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C61214UL)) +#define bFM4_CAN1_NEWDT_NEWDAT6 *((volatile uint8_t *)(0x42C61214UL)) +#define bFM_CAN1_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C61218UL)) +#define bFM4_CAN1_NEWDT_NEWDAT7 *((volatile uint8_t *)(0x42C61218UL)) +#define bFM_CAN1_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C6121CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT8 *((volatile uint8_t *)(0x42C6121CUL)) +#define bFM_CAN1_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C61220UL)) +#define bFM4_CAN1_NEWDT_NEWDAT9 *((volatile uint8_t *)(0x42C61220UL)) +#define bFM_CAN1_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C61224UL)) +#define bFM4_CAN1_NEWDT_NEWDAT10 *((volatile uint8_t *)(0x42C61224UL)) +#define bFM_CAN1_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C61228UL)) +#define bFM4_CAN1_NEWDT_NEWDAT11 *((volatile uint8_t *)(0x42C61228UL)) +#define bFM_CAN1_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C6122CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT12 *((volatile uint8_t *)(0x42C6122CUL)) +#define bFM_CAN1_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C61230UL)) +#define bFM4_CAN1_NEWDT_NEWDAT13 *((volatile uint8_t *)(0x42C61230UL)) +#define bFM_CAN1_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C61234UL)) +#define bFM4_CAN1_NEWDT_NEWDAT14 *((volatile uint8_t *)(0x42C61234UL)) +#define bFM_CAN1_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C61238UL)) +#define bFM4_CAN1_NEWDT_NEWDAT15 *((volatile uint8_t *)(0x42C61238UL)) +#define bFM_CAN1_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C6123CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT16 *((volatile uint8_t *)(0x42C6123CUL)) +#define bFM_CAN1_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C61240UL)) +#define bFM4_CAN1_NEWDT_NEWDAT17 *((volatile uint8_t *)(0x42C61240UL)) +#define bFM_CAN1_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C61244UL)) +#define bFM4_CAN1_NEWDT_NEWDAT18 *((volatile uint8_t *)(0x42C61244UL)) +#define bFM_CAN1_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C61248UL)) +#define bFM4_CAN1_NEWDT_NEWDAT19 *((volatile uint8_t *)(0x42C61248UL)) +#define bFM_CAN1_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C6124CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT20 *((volatile uint8_t *)(0x42C6124CUL)) +#define bFM_CAN1_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C61250UL)) +#define bFM4_CAN1_NEWDT_NEWDAT21 *((volatile uint8_t *)(0x42C61250UL)) +#define bFM_CAN1_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C61254UL)) +#define bFM4_CAN1_NEWDT_NEWDAT22 *((volatile uint8_t *)(0x42C61254UL)) +#define bFM_CAN1_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C61258UL)) +#define bFM4_CAN1_NEWDT_NEWDAT23 *((volatile uint8_t *)(0x42C61258UL)) +#define bFM_CAN1_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C6125CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT24 *((volatile uint8_t *)(0x42C6125CUL)) +#define bFM_CAN1_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C61260UL)) +#define bFM4_CAN1_NEWDT_NEWDAT25 *((volatile uint8_t *)(0x42C61260UL)) +#define bFM_CAN1_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C61264UL)) +#define bFM4_CAN1_NEWDT_NEWDAT26 *((volatile uint8_t *)(0x42C61264UL)) +#define bFM_CAN1_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C61268UL)) +#define bFM4_CAN1_NEWDT_NEWDAT27 *((volatile uint8_t *)(0x42C61268UL)) +#define bFM_CAN1_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C6126CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT28 *((volatile uint8_t *)(0x42C6126CUL)) +#define bFM_CAN1_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C61270UL)) +#define bFM4_CAN1_NEWDT_NEWDAT29 *((volatile uint8_t *)(0x42C61270UL)) +#define bFM_CAN1_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C61274UL)) +#define bFM4_CAN1_NEWDT_NEWDAT30 *((volatile uint8_t *)(0x42C61274UL)) +#define bFM_CAN1_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C61278UL)) +#define bFM4_CAN1_NEWDT_NEWDAT31 *((volatile uint8_t *)(0x42C61278UL)) +#define bFM_CAN1_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C6127CUL)) +#define bFM4_CAN1_NEWDT_NEWDAT32 *((volatile uint8_t *)(0x42C6127CUL)) + +#define bFM_CAN1_STATR_TXOK *((volatile uint8_t *)(0x42C6004CUL)) +#define bFM4_CAN1_STATR_TXOK *((volatile uint8_t *)(0x42C6004CUL)) +#define bFM_CAN1_STATR_RXOK *((volatile uint8_t *)(0x42C60050UL)) +#define bFM4_CAN1_STATR_RXOK *((volatile uint8_t *)(0x42C60050UL)) +#define bFM_CAN1_STATR_EPASS *((volatile uint8_t *)(0x42C60054UL)) +#define bFM4_CAN1_STATR_EPASS *((volatile uint8_t *)(0x42C60054UL)) +#define bFM_CAN1_STATR_EWARN *((volatile uint8_t *)(0x42C60058UL)) +#define bFM4_CAN1_STATR_EWARN *((volatile uint8_t *)(0x42C60058UL)) +#define bFM_CAN1_STATR_BOFF *((volatile uint8_t *)(0x42C6005CUL)) +#define bFM4_CAN1_STATR_BOFF *((volatile uint8_t *)(0x42C6005CUL)) + +#define bFM_CAN1_TESTR_BASIC *((volatile uint8_t *)(0x42C60148UL)) +#define bFM4_CAN1_TESTR_BASIC *((volatile uint8_t *)(0x42C60148UL)) +#define bFM_CAN1_TESTR_SILENT *((volatile uint8_t *)(0x42C6014CUL)) +#define bFM4_CAN1_TESTR_SILENT *((volatile uint8_t *)(0x42C6014CUL)) +#define bFM_CAN1_TESTR_LBACK *((volatile uint8_t *)(0x42C60150UL)) +#define bFM4_CAN1_TESTR_LBACK *((volatile uint8_t *)(0x42C60150UL)) +#define bFM_CAN1_TESTR_RX *((volatile uint8_t *)(0x42C6015CUL)) +#define bFM4_CAN1_TESTR_RX *((volatile uint8_t *)(0x42C6015CUL)) + +#define bFM_CAN1_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C61000UL)) +#define bFM4_CAN1_TREQR_TXRQST1 *((volatile uint8_t *)(0x42C61000UL)) +#define bFM_CAN1_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C61004UL)) +#define bFM4_CAN1_TREQR_TXRQST2 *((volatile uint8_t *)(0x42C61004UL)) +#define bFM_CAN1_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C61008UL)) +#define bFM4_CAN1_TREQR_TXRQST3 *((volatile uint8_t *)(0x42C61008UL)) +#define bFM_CAN1_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C6100CUL)) +#define bFM4_CAN1_TREQR_TXRQST4 *((volatile uint8_t *)(0x42C6100CUL)) +#define bFM_CAN1_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C61010UL)) +#define bFM4_CAN1_TREQR_TXRQST5 *((volatile uint8_t *)(0x42C61010UL)) +#define bFM_CAN1_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C61014UL)) +#define bFM4_CAN1_TREQR_TXRQST6 *((volatile uint8_t *)(0x42C61014UL)) +#define bFM_CAN1_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C61018UL)) +#define bFM4_CAN1_TREQR_TXRQST7 *((volatile uint8_t *)(0x42C61018UL)) +#define bFM_CAN1_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C6101CUL)) +#define bFM4_CAN1_TREQR_TXRQST8 *((volatile uint8_t *)(0x42C6101CUL)) +#define bFM_CAN1_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C61020UL)) +#define bFM4_CAN1_TREQR_TXRQST9 *((volatile uint8_t *)(0x42C61020UL)) +#define bFM_CAN1_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C61024UL)) +#define bFM4_CAN1_TREQR_TXRQST10 *((volatile uint8_t *)(0x42C61024UL)) +#define bFM_CAN1_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C61028UL)) +#define bFM4_CAN1_TREQR_TXRQST11 *((volatile uint8_t *)(0x42C61028UL)) +#define bFM_CAN1_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C6102CUL)) +#define bFM4_CAN1_TREQR_TXRQST12 *((volatile uint8_t *)(0x42C6102CUL)) +#define bFM_CAN1_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C61030UL)) +#define bFM4_CAN1_TREQR_TXRQST13 *((volatile uint8_t *)(0x42C61030UL)) +#define bFM_CAN1_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C61034UL)) +#define bFM4_CAN1_TREQR_TXRQST14 *((volatile uint8_t *)(0x42C61034UL)) +#define bFM_CAN1_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C61038UL)) +#define bFM4_CAN1_TREQR_TXRQST15 *((volatile uint8_t *)(0x42C61038UL)) +#define bFM_CAN1_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C6103CUL)) +#define bFM4_CAN1_TREQR_TXRQST16 *((volatile uint8_t *)(0x42C6103CUL)) +#define bFM_CAN1_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C61040UL)) +#define bFM4_CAN1_TREQR_TXRQST17 *((volatile uint8_t *)(0x42C61040UL)) +#define bFM_CAN1_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C61044UL)) +#define bFM4_CAN1_TREQR_TXRQST18 *((volatile uint8_t *)(0x42C61044UL)) +#define bFM_CAN1_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C61048UL)) +#define bFM4_CAN1_TREQR_TXRQST19 *((volatile uint8_t *)(0x42C61048UL)) +#define bFM_CAN1_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C6104CUL)) +#define bFM4_CAN1_TREQR_TXRQST20 *((volatile uint8_t *)(0x42C6104CUL)) +#define bFM_CAN1_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C61050UL)) +#define bFM4_CAN1_TREQR_TXRQST21 *((volatile uint8_t *)(0x42C61050UL)) +#define bFM_CAN1_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C61054UL)) +#define bFM4_CAN1_TREQR_TXRQST22 *((volatile uint8_t *)(0x42C61054UL)) +#define bFM_CAN1_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C61058UL)) +#define bFM4_CAN1_TREQR_TXRQST23 *((volatile uint8_t *)(0x42C61058UL)) +#define bFM_CAN1_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C6105CUL)) +#define bFM4_CAN1_TREQR_TXRQST24 *((volatile uint8_t *)(0x42C6105CUL)) +#define bFM_CAN1_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C61060UL)) +#define bFM4_CAN1_TREQR_TXRQST25 *((volatile uint8_t *)(0x42C61060UL)) +#define bFM_CAN1_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C61064UL)) +#define bFM4_CAN1_TREQR_TXRQST26 *((volatile uint8_t *)(0x42C61064UL)) +#define bFM_CAN1_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C61068UL)) +#define bFM4_CAN1_TREQR_TXRQST27 *((volatile uint8_t *)(0x42C61068UL)) +#define bFM_CAN1_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C6106CUL)) +#define bFM4_CAN1_TREQR_TXRQST28 *((volatile uint8_t *)(0x42C6106CUL)) +#define bFM_CAN1_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C61070UL)) +#define bFM4_CAN1_TREQR_TXRQST29 *((volatile uint8_t *)(0x42C61070UL)) +#define bFM_CAN1_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C61074UL)) +#define bFM4_CAN1_TREQR_TXRQST30 *((volatile uint8_t *)(0x42C61074UL)) +#define bFM_CAN1_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C61078UL)) +#define bFM4_CAN1_TREQR_TXRQST31 *((volatile uint8_t *)(0x42C61078UL)) +#define bFM_CAN1_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C6107CUL)) +#define bFM4_CAN1_TREQR_TXRQST32 *((volatile uint8_t *)(0x42C6107CUL)) + + +/******************************************************************************* +* CANFD Registers CANFD0 +* Bitband Section +*******************************************************************************/ +#define bFM_CANFD0_CCCR_INIT *((volatile uint8_t *)(0x42E00300UL)) +#define bFM4_CANFD0_CCCR_INIT *((volatile uint8_t *)(0x42E00300UL)) +#define bFM_CANFD0_CCCR_CCE *((volatile uint8_t *)(0x42E00304UL)) +#define bFM4_CANFD0_CCCR_CCE *((volatile uint8_t *)(0x42E00304UL)) +#define bFM_CANFD0_CCCR_ASM *((volatile uint8_t *)(0x42E00308UL)) +#define bFM4_CANFD0_CCCR_ASM *((volatile uint8_t *)(0x42E00308UL)) +#define bFM_CANFD0_CCCR_CSA *((volatile uint8_t *)(0x42E0030CUL)) +#define bFM4_CANFD0_CCCR_CSA *((volatile uint8_t *)(0x42E0030CUL)) +#define bFM_CANFD0_CCCR_CSR *((volatile uint8_t *)(0x42E00310UL)) +#define bFM4_CANFD0_CCCR_CSR *((volatile uint8_t *)(0x42E00310UL)) +#define bFM_CANFD0_CCCR_MON *((volatile uint8_t *)(0x42E00314UL)) +#define bFM4_CANFD0_CCCR_MON *((volatile uint8_t *)(0x42E00314UL)) +#define bFM_CANFD0_CCCR_DAR *((volatile uint8_t *)(0x42E00318UL)) +#define bFM4_CANFD0_CCCR_DAR *((volatile uint8_t *)(0x42E00318UL)) +#define bFM_CANFD0_CCCR_TEST *((volatile uint8_t *)(0x42E0031CUL)) +#define bFM4_CANFD0_CCCR_TEST *((volatile uint8_t *)(0x42E0031CUL)) +#define bFM_CANFD0_CCCR_FDO *((volatile uint8_t *)(0x42E00330UL)) +#define bFM4_CANFD0_CCCR_FDO *((volatile uint8_t *)(0x42E00330UL)) +#define bFM_CANFD0_CCCR_FDBS *((volatile uint8_t *)(0x42E00334UL)) +#define bFM4_CANFD0_CCCR_FDBS *((volatile uint8_t *)(0x42E00334UL)) +#define bFM_CANFD0_CCCR_TXP *((volatile uint8_t *)(0x42E00338UL)) +#define bFM4_CANFD0_CCCR_TXP *((volatile uint8_t *)(0x42E00338UL)) + +#define bFM_CANFD0_ECR_RP *((volatile uint8_t *)(0x42E0083CUL)) +#define bFM4_CANFD0_ECR_RP *((volatile uint8_t *)(0x42E0083CUL)) + +#define bFM_CANFD0_FBTP_TDC *((volatile uint8_t *)(0x42E001DCUL)) +#define bFM4_CANFD0_FBTP_TDC *((volatile uint8_t *)(0x42E001DCUL)) + +#define bFM_CANFD0_FDECR_SEIE *((volatile uint8_t *)(0x42E04000UL)) +#define bFM4_CANFD0_FDECR_SEIE *((volatile uint8_t *)(0x42E04000UL)) +#define bFM_CANFD0_FDECR_DEIE *((volatile uint8_t *)(0x42E04004UL)) +#define bFM4_CANFD0_FDECR_DEIE *((volatile uint8_t *)(0x42E04004UL)) +#define bFM_CANFD0_FDECR_CEREN *((volatile uint8_t *)(0x42E04008UL)) +#define bFM4_CANFD0_FDECR_CEREN *((volatile uint8_t *)(0x42E04008UL)) +#define bFM_CANFD0_FDECR_CEIV *((volatile uint8_t *)(0x42E0400CUL)) +#define bFM4_CANFD0_FDECR_CEIV *((volatile uint8_t *)(0x42E0400CUL)) + +#define bFM_CANFD0_FDESCR_SEIC *((volatile uint8_t *)(0x42E040A0UL)) +#define bFM4_CANFD0_FDESCR_SEIC *((volatile uint8_t *)(0x42E040A0UL)) +#define bFM_CANFD0_FDESCR_DEIC *((volatile uint8_t *)(0x42E040A4UL)) +#define bFM4_CANFD0_FDESCR_DEIC *((volatile uint8_t *)(0x42E040A4UL)) + +#define bFM_CANFD0_FDESR_SEI *((volatile uint8_t *)(0x42E04020UL)) +#define bFM4_CANFD0_FDESR_SEI *((volatile uint8_t *)(0x42E04020UL)) +#define bFM_CANFD0_FDESR_DEI *((volatile uint8_t *)(0x42E04024UL)) +#define bFM4_CANFD0_FDESR_DEI *((volatile uint8_t *)(0x42E04024UL)) + +#define bFM_CANFD0_GFC_RRFE *((volatile uint8_t *)(0x42E01000UL)) +#define bFM4_CANFD0_GFC_RRFE *((volatile uint8_t *)(0x42E01000UL)) +#define bFM_CANFD0_GFC_RRFS *((volatile uint8_t *)(0x42E01004UL)) +#define bFM4_CANFD0_GFC_RRFS *((volatile uint8_t *)(0x42E01004UL)) + +#define bFM_CANFD0_HPMS_FLST *((volatile uint8_t *)(0x42E012BCUL)) +#define bFM4_CANFD0_HPMS_FLST *((volatile uint8_t *)(0x42E012BCUL)) + +#define bFM_CANFD0_IE_RF0NE *((volatile uint8_t *)(0x42E00A80UL)) +#define bFM4_CANFD0_IE_RF0NE *((volatile uint8_t *)(0x42E00A80UL)) +#define bFM_CANFD0_IE_RF0WE *((volatile uint8_t *)(0x42E00A84UL)) +#define bFM4_CANFD0_IE_RF0WE *((volatile uint8_t *)(0x42E00A84UL)) +#define bFM_CANFD0_IE_RF0FE *((volatile uint8_t *)(0x42E00A88UL)) +#define bFM4_CANFD0_IE_RF0FE *((volatile uint8_t *)(0x42E00A88UL)) +#define bFM_CANFD0_IE_RF0LE *((volatile uint8_t *)(0x42E00A8CUL)) +#define bFM4_CANFD0_IE_RF0LE *((volatile uint8_t *)(0x42E00A8CUL)) +#define bFM_CANFD0_IE_RF1NE *((volatile uint8_t *)(0x42E00A90UL)) +#define bFM4_CANFD0_IE_RF1NE *((volatile uint8_t *)(0x42E00A90UL)) +#define bFM_CANFD0_IE_RF1WE *((volatile uint8_t *)(0x42E00A94UL)) +#define bFM4_CANFD0_IE_RF1WE *((volatile uint8_t *)(0x42E00A94UL)) +#define bFM_CANFD0_IE_RF1FE *((volatile uint8_t *)(0x42E00A98UL)) +#define bFM4_CANFD0_IE_RF1FE *((volatile uint8_t *)(0x42E00A98UL)) +#define bFM_CANFD0_IE_RF1LE *((volatile uint8_t *)(0x42E00A9CUL)) +#define bFM4_CANFD0_IE_RF1LE *((volatile uint8_t *)(0x42E00A9CUL)) +#define bFM_CANFD0_IE_HPME *((volatile uint8_t *)(0x42E00AA0UL)) +#define bFM4_CANFD0_IE_HPME *((volatile uint8_t *)(0x42E00AA0UL)) +#define bFM_CANFD0_IE_TCE *((volatile uint8_t *)(0x42E00AA4UL)) +#define bFM4_CANFD0_IE_TCE *((volatile uint8_t *)(0x42E00AA4UL)) +#define bFM_CANFD0_IE_TCFE *((volatile uint8_t *)(0x42E00AA8UL)) +#define bFM4_CANFD0_IE_TCFE *((volatile uint8_t *)(0x42E00AA8UL)) +#define bFM_CANFD0_IE_TFEE *((volatile uint8_t *)(0x42E00AACUL)) +#define bFM4_CANFD0_IE_TFEE *((volatile uint8_t *)(0x42E00AACUL)) +#define bFM_CANFD0_IE_TEFNE *((volatile uint8_t *)(0x42E00AB0UL)) +#define bFM4_CANFD0_IE_TEFNE *((volatile uint8_t *)(0x42E00AB0UL)) +#define bFM_CANFD0_IE_TEFWE *((volatile uint8_t *)(0x42E00AB4UL)) +#define bFM4_CANFD0_IE_TEFWE *((volatile uint8_t *)(0x42E00AB4UL)) +#define bFM_CANFD0_IE_TEFFE *((volatile uint8_t *)(0x42E00AB8UL)) +#define bFM4_CANFD0_IE_TEFFE *((volatile uint8_t *)(0x42E00AB8UL)) +#define bFM_CANFD0_IE_TEFLE *((volatile uint8_t *)(0x42E00ABCUL)) +#define bFM4_CANFD0_IE_TEFLE *((volatile uint8_t *)(0x42E00ABCUL)) +#define bFM_CANFD0_IE_TSWE *((volatile uint8_t *)(0x42E00AC0UL)) +#define bFM4_CANFD0_IE_TSWE *((volatile uint8_t *)(0x42E00AC0UL)) +#define bFM_CANFD0_IE_MRAFE *((volatile uint8_t *)(0x42E00AC4UL)) +#define bFM4_CANFD0_IE_MRAFE *((volatile uint8_t *)(0x42E00AC4UL)) +#define bFM_CANFD0_IE_TOOE *((volatile uint8_t *)(0x42E00AC8UL)) +#define bFM4_CANFD0_IE_TOOE *((volatile uint8_t *)(0x42E00AC8UL)) +#define bFM_CANFD0_IE_DRXE *((volatile uint8_t *)(0x42E00ACCUL)) +#define bFM4_CANFD0_IE_DRXE *((volatile uint8_t *)(0x42E00ACCUL)) +#define bFM_CANFD0_IE_BECE *((volatile uint8_t *)(0x42E00AD0UL)) +#define bFM4_CANFD0_IE_BECE *((volatile uint8_t *)(0x42E00AD0UL)) +#define bFM_CANFD0_IE_BEUE *((volatile uint8_t *)(0x42E00AD4UL)) +#define bFM4_CANFD0_IE_BEUE *((volatile uint8_t *)(0x42E00AD4UL)) +#define bFM_CANFD0_IE_ELOE *((volatile uint8_t *)(0x42E00AD8UL)) +#define bFM4_CANFD0_IE_ELOE *((volatile uint8_t *)(0x42E00AD8UL)) +#define bFM_CANFD0_IE_EPE *((volatile uint8_t *)(0x42E00ADCUL)) +#define bFM4_CANFD0_IE_EPE *((volatile uint8_t *)(0x42E00ADCUL)) +#define bFM_CANFD0_IE_EWE *((volatile uint8_t *)(0x42E00AE0UL)) +#define bFM4_CANFD0_IE_EWE *((volatile uint8_t *)(0x42E00AE0UL)) +#define bFM_CANFD0_IE_BOE *((volatile uint8_t *)(0x42E00AE4UL)) +#define bFM4_CANFD0_IE_BOE *((volatile uint8_t *)(0x42E00AE4UL)) +#define bFM_CANFD0_IE_WDIE *((volatile uint8_t *)(0x42E00AE8UL)) +#define bFM4_CANFD0_IE_WDIE *((volatile uint8_t *)(0x42E00AE8UL)) +#define bFM_CANFD0_IE_CRCEE *((volatile uint8_t *)(0x42E00AECUL)) +#define bFM4_CANFD0_IE_CRCEE *((volatile uint8_t *)(0x42E00AECUL)) +#define bFM_CANFD0_IE_BEE *((volatile uint8_t *)(0x42E00AF0UL)) +#define bFM4_CANFD0_IE_BEE *((volatile uint8_t *)(0x42E00AF0UL)) +#define bFM_CANFD0_IE_ACKEE *((volatile uint8_t *)(0x42E00AF4UL)) +#define bFM4_CANFD0_IE_ACKEE *((volatile uint8_t *)(0x42E00AF4UL)) +#define bFM_CANFD0_IE_FOEE *((volatile uint8_t *)(0x42E00AF8UL)) +#define bFM4_CANFD0_IE_FOEE *((volatile uint8_t *)(0x42E00AF8UL)) +#define bFM_CANFD0_IE_STEE *((volatile uint8_t *)(0x42E00AFCUL)) +#define bFM4_CANFD0_IE_STEE *((volatile uint8_t *)(0x42E00AFCUL)) + +#define bFM_CANFD0_ILE_EINT0 *((volatile uint8_t *)(0x42E00B80UL)) +#define bFM4_CANFD0_ILE_EINT0 *((volatile uint8_t *)(0x42E00B80UL)) +#define bFM_CANFD0_ILE_EINT1 *((volatile uint8_t *)(0x42E00B84UL)) +#define bFM4_CANFD0_ILE_EINT1 *((volatile uint8_t *)(0x42E00B84UL)) + +#define bFM_CANFD0_ILS_RF0NL *((volatile uint8_t *)(0x42E00B00UL)) +#define bFM4_CANFD0_ILS_RF0NL *((volatile uint8_t *)(0x42E00B00UL)) +#define bFM_CANFD0_ILS_RF0WL *((volatile uint8_t *)(0x42E00B04UL)) +#define bFM4_CANFD0_ILS_RF0WL *((volatile uint8_t *)(0x42E00B04UL)) +#define bFM_CANFD0_ILS_RF0FL *((volatile uint8_t *)(0x42E00B08UL)) +#define bFM4_CANFD0_ILS_RF0FL *((volatile uint8_t *)(0x42E00B08UL)) +#define bFM_CANFD0_ILS_RF0LL *((volatile uint8_t *)(0x42E00B0CUL)) +#define bFM4_CANFD0_ILS_RF0LL *((volatile uint8_t *)(0x42E00B0CUL)) +#define bFM_CANFD0_ILS_RF1NL *((volatile uint8_t *)(0x42E00B10UL)) +#define bFM4_CANFD0_ILS_RF1NL *((volatile uint8_t *)(0x42E00B10UL)) +#define bFM_CANFD0_ILS_RF1WL *((volatile uint8_t *)(0x42E00B14UL)) +#define bFM4_CANFD0_ILS_RF1WL *((volatile uint8_t *)(0x42E00B14UL)) +#define bFM_CANFD0_ILS_RF1FL *((volatile uint8_t *)(0x42E00B18UL)) +#define bFM4_CANFD0_ILS_RF1FL *((volatile uint8_t *)(0x42E00B18UL)) +#define bFM_CANFD0_ILS_RF1LL *((volatile uint8_t *)(0x42E00B1CUL)) +#define bFM4_CANFD0_ILS_RF1LL *((volatile uint8_t *)(0x42E00B1CUL)) +#define bFM_CANFD0_ILS_HPML *((volatile uint8_t *)(0x42E00B20UL)) +#define bFM4_CANFD0_ILS_HPML *((volatile uint8_t *)(0x42E00B20UL)) +#define bFM_CANFD0_ILS_TCL *((volatile uint8_t *)(0x42E00B24UL)) +#define bFM4_CANFD0_ILS_TCL *((volatile uint8_t *)(0x42E00B24UL)) +#define bFM_CANFD0_ILS_TCFL *((volatile uint8_t *)(0x42E00B28UL)) +#define bFM4_CANFD0_ILS_TCFL *((volatile uint8_t *)(0x42E00B28UL)) +#define bFM_CANFD0_ILS_TFEL *((volatile uint8_t *)(0x42E00B2CUL)) +#define bFM4_CANFD0_ILS_TFEL *((volatile uint8_t *)(0x42E00B2CUL)) +#define bFM_CANFD0_ILS_TEFNL *((volatile uint8_t *)(0x42E00B30UL)) +#define bFM4_CANFD0_ILS_TEFNL *((volatile uint8_t *)(0x42E00B30UL)) +#define bFM_CANFD0_ILS_TEFWL *((volatile uint8_t *)(0x42E00B34UL)) +#define bFM4_CANFD0_ILS_TEFWL *((volatile uint8_t *)(0x42E00B34UL)) +#define bFM_CANFD0_ILS_TEFFL *((volatile uint8_t *)(0x42E00B38UL)) +#define bFM4_CANFD0_ILS_TEFFL *((volatile uint8_t *)(0x42E00B38UL)) +#define bFM_CANFD0_ILS_TEFLL *((volatile uint8_t *)(0x42E00B3CUL)) +#define bFM4_CANFD0_ILS_TEFLL *((volatile uint8_t *)(0x42E00B3CUL)) +#define bFM_CANFD0_ILS_TSWL *((volatile uint8_t *)(0x42E00B40UL)) +#define bFM4_CANFD0_ILS_TSWL *((volatile uint8_t *)(0x42E00B40UL)) +#define bFM_CANFD0_ILS_MRAFL *((volatile uint8_t *)(0x42E00B44UL)) +#define bFM4_CANFD0_ILS_MRAFL *((volatile uint8_t *)(0x42E00B44UL)) +#define bFM_CANFD0_ILS_TOOL *((volatile uint8_t *)(0x42E00B48UL)) +#define bFM4_CANFD0_ILS_TOOL *((volatile uint8_t *)(0x42E00B48UL)) +#define bFM_CANFD0_ILS_DRXL *((volatile uint8_t *)(0x42E00B4CUL)) +#define bFM4_CANFD0_ILS_DRXL *((volatile uint8_t *)(0x42E00B4CUL)) +#define bFM_CANFD0_ILS_BECL *((volatile uint8_t *)(0x42E00B50UL)) +#define bFM4_CANFD0_ILS_BECL *((volatile uint8_t *)(0x42E00B50UL)) +#define bFM_CANFD0_ILS_BEUL *((volatile uint8_t *)(0x42E00B54UL)) +#define bFM4_CANFD0_ILS_BEUL *((volatile uint8_t *)(0x42E00B54UL)) +#define bFM_CANFD0_ILS_ELOL *((volatile uint8_t *)(0x42E00B58UL)) +#define bFM4_CANFD0_ILS_ELOL *((volatile uint8_t *)(0x42E00B58UL)) +#define bFM_CANFD0_ILS_EPL *((volatile uint8_t *)(0x42E00B5CUL)) +#define bFM4_CANFD0_ILS_EPL *((volatile uint8_t *)(0x42E00B5CUL)) +#define bFM_CANFD0_ILS_EWL *((volatile uint8_t *)(0x42E00B60UL)) +#define bFM4_CANFD0_ILS_EWL *((volatile uint8_t *)(0x42E00B60UL)) +#define bFM_CANFD0_ILS_BOL *((volatile uint8_t *)(0x42E00B64UL)) +#define bFM4_CANFD0_ILS_BOL *((volatile uint8_t *)(0x42E00B64UL)) +#define bFM_CANFD0_ILS_WDIL *((volatile uint8_t *)(0x42E00B68UL)) +#define bFM4_CANFD0_ILS_WDIL *((volatile uint8_t *)(0x42E00B68UL)) +#define bFM_CANFD0_ILS_CRCEL *((volatile uint8_t *)(0x42E00B6CUL)) +#define bFM4_CANFD0_ILS_CRCEL *((volatile uint8_t *)(0x42E00B6CUL)) +#define bFM_CANFD0_ILS_BEL *((volatile uint8_t *)(0x42E00B70UL)) +#define bFM4_CANFD0_ILS_BEL *((volatile uint8_t *)(0x42E00B70UL)) +#define bFM_CANFD0_ILS_ACKEL *((volatile uint8_t *)(0x42E00B74UL)) +#define bFM4_CANFD0_ILS_ACKEL *((volatile uint8_t *)(0x42E00B74UL)) +#define bFM_CANFD0_ILS_FOEL *((volatile uint8_t *)(0x42E00B78UL)) +#define bFM4_CANFD0_ILS_FOEL *((volatile uint8_t *)(0x42E00B78UL)) +#define bFM_CANFD0_ILS_STEL *((volatile uint8_t *)(0x42E00B7CUL)) +#define bFM4_CANFD0_ILS_STEL *((volatile uint8_t *)(0x42E00B7CUL)) + +#define bFM_CANFD0_IR_RF0N *((volatile uint8_t *)(0x42E00A00UL)) +#define bFM4_CANFD0_IR_RF0N *((volatile uint8_t *)(0x42E00A00UL)) +#define bFM_CANFD0_IR_RF0W *((volatile uint8_t *)(0x42E00A04UL)) +#define bFM4_CANFD0_IR_RF0W *((volatile uint8_t *)(0x42E00A04UL)) +#define bFM_CANFD0_IR_RF0F *((volatile uint8_t *)(0x42E00A08UL)) +#define bFM4_CANFD0_IR_RF0F *((volatile uint8_t *)(0x42E00A08UL)) +#define bFM_CANFD0_IR_RF0L *((volatile uint8_t *)(0x42E00A0CUL)) +#define bFM4_CANFD0_IR_RF0L *((volatile uint8_t *)(0x42E00A0CUL)) +#define bFM_CANFD0_IR_RF1N *((volatile uint8_t *)(0x42E00A10UL)) +#define bFM4_CANFD0_IR_RF1N *((volatile uint8_t *)(0x42E00A10UL)) +#define bFM_CANFD0_IR_RF1W *((volatile uint8_t *)(0x42E00A14UL)) +#define bFM4_CANFD0_IR_RF1W *((volatile uint8_t *)(0x42E00A14UL)) +#define bFM_CANFD0_IR_RF1F *((volatile uint8_t *)(0x42E00A18UL)) +#define bFM4_CANFD0_IR_RF1F *((volatile uint8_t *)(0x42E00A18UL)) +#define bFM_CANFD0_IR_RF1L *((volatile uint8_t *)(0x42E00A1CUL)) +#define bFM4_CANFD0_IR_RF1L *((volatile uint8_t *)(0x42E00A1CUL)) +#define bFM_CANFD0_IR_HPM *((volatile uint8_t *)(0x42E00A20UL)) +#define bFM4_CANFD0_IR_HPM *((volatile uint8_t *)(0x42E00A20UL)) +#define bFM_CANFD0_IR_TC *((volatile uint8_t *)(0x42E00A24UL)) +#define bFM4_CANFD0_IR_TC *((volatile uint8_t *)(0x42E00A24UL)) +#define bFM_CANFD0_IR_TCF *((volatile uint8_t *)(0x42E00A28UL)) +#define bFM4_CANFD0_IR_TCF *((volatile uint8_t *)(0x42E00A28UL)) +#define bFM_CANFD0_IR_TFE *((volatile uint8_t *)(0x42E00A2CUL)) +#define bFM4_CANFD0_IR_TFE *((volatile uint8_t *)(0x42E00A2CUL)) +#define bFM_CANFD0_IR_TEFN *((volatile uint8_t *)(0x42E00A30UL)) +#define bFM4_CANFD0_IR_TEFN *((volatile uint8_t *)(0x42E00A30UL)) +#define bFM_CANFD0_IR_TEFW *((volatile uint8_t *)(0x42E00A34UL)) +#define bFM4_CANFD0_IR_TEFW *((volatile uint8_t *)(0x42E00A34UL)) +#define bFM_CANFD0_IR_TEFF *((volatile uint8_t *)(0x42E00A38UL)) +#define bFM4_CANFD0_IR_TEFF *((volatile uint8_t *)(0x42E00A38UL)) +#define bFM_CANFD0_IR_TEFL *((volatile uint8_t *)(0x42E00A3CUL)) +#define bFM4_CANFD0_IR_TEFL *((volatile uint8_t *)(0x42E00A3CUL)) +#define bFM_CANFD0_IR_TSW *((volatile uint8_t *)(0x42E00A40UL)) +#define bFM4_CANFD0_IR_TSW *((volatile uint8_t *)(0x42E00A40UL)) +#define bFM_CANFD0_IR_MRAF *((volatile uint8_t *)(0x42E00A44UL)) +#define bFM4_CANFD0_IR_MRAF *((volatile uint8_t *)(0x42E00A44UL)) +#define bFM_CANFD0_IR_TOO *((volatile uint8_t *)(0x42E00A48UL)) +#define bFM4_CANFD0_IR_TOO *((volatile uint8_t *)(0x42E00A48UL)) +#define bFM_CANFD0_IR_DRX *((volatile uint8_t *)(0x42E00A4CUL)) +#define bFM4_CANFD0_IR_DRX *((volatile uint8_t *)(0x42E00A4CUL)) +#define bFM_CANFD0_IR_BEC *((volatile uint8_t *)(0x42E00A50UL)) +#define bFM4_CANFD0_IR_BEC *((volatile uint8_t *)(0x42E00A50UL)) +#define bFM_CANFD0_IR_BEU *((volatile uint8_t *)(0x42E00A54UL)) +#define bFM4_CANFD0_IR_BEU *((volatile uint8_t *)(0x42E00A54UL)) +#define bFM_CANFD0_IR_ELO *((volatile uint8_t *)(0x42E00A58UL)) +#define bFM4_CANFD0_IR_ELO *((volatile uint8_t *)(0x42E00A58UL)) +#define bFM_CANFD0_IR_EP *((volatile uint8_t *)(0x42E00A5CUL)) +#define bFM4_CANFD0_IR_EP *((volatile uint8_t *)(0x42E00A5CUL)) +#define bFM_CANFD0_IR_EW *((volatile uint8_t *)(0x42E00A60UL)) +#define bFM4_CANFD0_IR_EW *((volatile uint8_t *)(0x42E00A60UL)) +#define bFM_CANFD0_IR_BO *((volatile uint8_t *)(0x42E00A64UL)) +#define bFM4_CANFD0_IR_BO *((volatile uint8_t *)(0x42E00A64UL)) +#define bFM_CANFD0_IR_WDI *((volatile uint8_t *)(0x42E00A68UL)) +#define bFM4_CANFD0_IR_WDI *((volatile uint8_t *)(0x42E00A68UL)) +#define bFM_CANFD0_IR_CRCE *((volatile uint8_t *)(0x42E00A6CUL)) +#define bFM4_CANFD0_IR_CRCE *((volatile uint8_t *)(0x42E00A6CUL)) +#define bFM_CANFD0_IR_BE *((volatile uint8_t *)(0x42E00A70UL)) +#define bFM4_CANFD0_IR_BE *((volatile uint8_t *)(0x42E00A70UL)) +#define bFM_CANFD0_IR_ACKE *((volatile uint8_t *)(0x42E00A74UL)) +#define bFM4_CANFD0_IR_ACKE *((volatile uint8_t *)(0x42E00A74UL)) +#define bFM_CANFD0_IR_FOE *((volatile uint8_t *)(0x42E00A78UL)) +#define bFM4_CANFD0_IR_FOE *((volatile uint8_t *)(0x42E00A78UL)) +#define bFM_CANFD0_IR_STE *((volatile uint8_t *)(0x42E00A7CUL)) +#define bFM4_CANFD0_IR_STE *((volatile uint8_t *)(0x42E00A7CUL)) + +#define bFM_CANFD0_NDAT1_ND0 *((volatile uint8_t *)(0x42E01300UL)) +#define bFM4_CANFD0_NDAT1_ND0 *((volatile uint8_t *)(0x42E01300UL)) +#define bFM_CANFD0_NDAT1_ND1 *((volatile uint8_t *)(0x42E01304UL)) +#define bFM4_CANFD0_NDAT1_ND1 *((volatile uint8_t *)(0x42E01304UL)) +#define bFM_CANFD0_NDAT1_ND2 *((volatile uint8_t *)(0x42E01308UL)) +#define bFM4_CANFD0_NDAT1_ND2 *((volatile uint8_t *)(0x42E01308UL)) +#define bFM_CANFD0_NDAT1_ND3 *((volatile uint8_t *)(0x42E0130CUL)) +#define bFM4_CANFD0_NDAT1_ND3 *((volatile uint8_t *)(0x42E0130CUL)) +#define bFM_CANFD0_NDAT1_ND4 *((volatile uint8_t *)(0x42E01310UL)) +#define bFM4_CANFD0_NDAT1_ND4 *((volatile uint8_t *)(0x42E01310UL)) +#define bFM_CANFD0_NDAT1_ND5 *((volatile uint8_t *)(0x42E01314UL)) +#define bFM4_CANFD0_NDAT1_ND5 *((volatile uint8_t *)(0x42E01314UL)) +#define bFM_CANFD0_NDAT1_ND6 *((volatile uint8_t *)(0x42E01318UL)) +#define bFM4_CANFD0_NDAT1_ND6 *((volatile uint8_t *)(0x42E01318UL)) +#define bFM_CANFD0_NDAT1_ND7 *((volatile uint8_t *)(0x42E0131CUL)) +#define bFM4_CANFD0_NDAT1_ND7 *((volatile uint8_t *)(0x42E0131CUL)) +#define bFM_CANFD0_NDAT1_ND8 *((volatile uint8_t *)(0x42E01320UL)) +#define bFM4_CANFD0_NDAT1_ND8 *((volatile uint8_t *)(0x42E01320UL)) +#define bFM_CANFD0_NDAT1_ND9 *((volatile uint8_t *)(0x42E01324UL)) +#define bFM4_CANFD0_NDAT1_ND9 *((volatile uint8_t *)(0x42E01324UL)) +#define bFM_CANFD0_NDAT1_ND10 *((volatile uint8_t *)(0x42E01328UL)) +#define bFM4_CANFD0_NDAT1_ND10 *((volatile uint8_t *)(0x42E01328UL)) +#define bFM_CANFD0_NDAT1_ND11 *((volatile uint8_t *)(0x42E0132CUL)) +#define bFM4_CANFD0_NDAT1_ND11 *((volatile uint8_t *)(0x42E0132CUL)) +#define bFM_CANFD0_NDAT1_ND12 *((volatile uint8_t *)(0x42E01330UL)) +#define bFM4_CANFD0_NDAT1_ND12 *((volatile uint8_t *)(0x42E01330UL)) +#define bFM_CANFD0_NDAT1_ND13 *((volatile uint8_t *)(0x42E01334UL)) +#define bFM4_CANFD0_NDAT1_ND13 *((volatile uint8_t *)(0x42E01334UL)) +#define bFM_CANFD0_NDAT1_ND14 *((volatile uint8_t *)(0x42E01338UL)) +#define bFM4_CANFD0_NDAT1_ND14 *((volatile uint8_t *)(0x42E01338UL)) +#define bFM_CANFD0_NDAT1_ND15 *((volatile uint8_t *)(0x42E0133CUL)) +#define bFM4_CANFD0_NDAT1_ND15 *((volatile uint8_t *)(0x42E0133CUL)) +#define bFM_CANFD0_NDAT1_ND16 *((volatile uint8_t *)(0x42E01340UL)) +#define bFM4_CANFD0_NDAT1_ND16 *((volatile uint8_t *)(0x42E01340UL)) +#define bFM_CANFD0_NDAT1_ND17 *((volatile uint8_t *)(0x42E01344UL)) +#define bFM4_CANFD0_NDAT1_ND17 *((volatile uint8_t *)(0x42E01344UL)) +#define bFM_CANFD0_NDAT1_ND18 *((volatile uint8_t *)(0x42E01348UL)) +#define bFM4_CANFD0_NDAT1_ND18 *((volatile uint8_t *)(0x42E01348UL)) +#define bFM_CANFD0_NDAT1_ND19 *((volatile uint8_t *)(0x42E0134CUL)) +#define bFM4_CANFD0_NDAT1_ND19 *((volatile uint8_t *)(0x42E0134CUL)) +#define bFM_CANFD0_NDAT1_ND20 *((volatile uint8_t *)(0x42E01350UL)) +#define bFM4_CANFD0_NDAT1_ND20 *((volatile uint8_t *)(0x42E01350UL)) +#define bFM_CANFD0_NDAT1_ND21 *((volatile uint8_t *)(0x42E01354UL)) +#define bFM4_CANFD0_NDAT1_ND21 *((volatile uint8_t *)(0x42E01354UL)) +#define bFM_CANFD0_NDAT1_ND22 *((volatile uint8_t *)(0x42E01358UL)) +#define bFM4_CANFD0_NDAT1_ND22 *((volatile uint8_t *)(0x42E01358UL)) +#define bFM_CANFD0_NDAT1_ND23 *((volatile uint8_t *)(0x42E0135CUL)) +#define bFM4_CANFD0_NDAT1_ND23 *((volatile uint8_t *)(0x42E0135CUL)) +#define bFM_CANFD0_NDAT1_ND24 *((volatile uint8_t *)(0x42E01360UL)) +#define bFM4_CANFD0_NDAT1_ND24 *((volatile uint8_t *)(0x42E01360UL)) +#define bFM_CANFD0_NDAT1_ND25 *((volatile uint8_t *)(0x42E01364UL)) +#define bFM4_CANFD0_NDAT1_ND25 *((volatile uint8_t *)(0x42E01364UL)) +#define bFM_CANFD0_NDAT1_ND26 *((volatile uint8_t *)(0x42E01368UL)) +#define bFM4_CANFD0_NDAT1_ND26 *((volatile uint8_t *)(0x42E01368UL)) +#define bFM_CANFD0_NDAT1_ND27 *((volatile uint8_t *)(0x42E0136CUL)) +#define bFM4_CANFD0_NDAT1_ND27 *((volatile uint8_t *)(0x42E0136CUL)) +#define bFM_CANFD0_NDAT1_ND28 *((volatile uint8_t *)(0x42E01370UL)) +#define bFM4_CANFD0_NDAT1_ND28 *((volatile uint8_t *)(0x42E01370UL)) +#define bFM_CANFD0_NDAT1_ND29 *((volatile uint8_t *)(0x42E01374UL)) +#define bFM4_CANFD0_NDAT1_ND29 *((volatile uint8_t *)(0x42E01374UL)) +#define bFM_CANFD0_NDAT1_ND30 *((volatile uint8_t *)(0x42E01378UL)) +#define bFM4_CANFD0_NDAT1_ND30 *((volatile uint8_t *)(0x42E01378UL)) +#define bFM_CANFD0_NDAT1_ND31 *((volatile uint8_t *)(0x42E0137CUL)) +#define bFM4_CANFD0_NDAT1_ND31 *((volatile uint8_t *)(0x42E0137CUL)) + +#define bFM_CANFD0_NDAT2_ND32 *((volatile uint8_t *)(0x42E01380UL)) +#define bFM4_CANFD0_NDAT2_ND32 *((volatile uint8_t *)(0x42E01380UL)) +#define bFM_CANFD0_NDAT2_ND33 *((volatile uint8_t *)(0x42E01384UL)) +#define bFM4_CANFD0_NDAT2_ND33 *((volatile uint8_t *)(0x42E01384UL)) +#define bFM_CANFD0_NDAT2_ND34 *((volatile uint8_t *)(0x42E01388UL)) +#define bFM4_CANFD0_NDAT2_ND34 *((volatile uint8_t *)(0x42E01388UL)) +#define bFM_CANFD0_NDAT2_ND35 *((volatile uint8_t *)(0x42E0138CUL)) +#define bFM4_CANFD0_NDAT2_ND35 *((volatile uint8_t *)(0x42E0138CUL)) +#define bFM_CANFD0_NDAT2_ND36 *((volatile uint8_t *)(0x42E01390UL)) +#define bFM4_CANFD0_NDAT2_ND36 *((volatile uint8_t *)(0x42E01390UL)) +#define bFM_CANFD0_NDAT2_ND37 *((volatile uint8_t *)(0x42E01394UL)) +#define bFM4_CANFD0_NDAT2_ND37 *((volatile uint8_t *)(0x42E01394UL)) +#define bFM_CANFD0_NDAT2_ND38 *((volatile uint8_t *)(0x42E01398UL)) +#define bFM4_CANFD0_NDAT2_ND38 *((volatile uint8_t *)(0x42E01398UL)) +#define bFM_CANFD0_NDAT2_ND39 *((volatile uint8_t *)(0x42E0139CUL)) +#define bFM4_CANFD0_NDAT2_ND39 *((volatile uint8_t *)(0x42E0139CUL)) +#define bFM_CANFD0_NDAT2_ND40 *((volatile uint8_t *)(0x42E013A0UL)) +#define bFM4_CANFD0_NDAT2_ND40 *((volatile uint8_t *)(0x42E013A0UL)) +#define bFM_CANFD0_NDAT2_ND41 *((volatile uint8_t *)(0x42E013A4UL)) +#define bFM4_CANFD0_NDAT2_ND41 *((volatile uint8_t *)(0x42E013A4UL)) +#define bFM_CANFD0_NDAT2_ND42 *((volatile uint8_t *)(0x42E013A8UL)) +#define bFM4_CANFD0_NDAT2_ND42 *((volatile uint8_t *)(0x42E013A8UL)) +#define bFM_CANFD0_NDAT2_ND43 *((volatile uint8_t *)(0x42E013ACUL)) +#define bFM4_CANFD0_NDAT2_ND43 *((volatile uint8_t *)(0x42E013ACUL)) +#define bFM_CANFD0_NDAT2_ND44 *((volatile uint8_t *)(0x42E013B0UL)) +#define bFM4_CANFD0_NDAT2_ND44 *((volatile uint8_t *)(0x42E013B0UL)) +#define bFM_CANFD0_NDAT2_ND45 *((volatile uint8_t *)(0x42E013B4UL)) +#define bFM4_CANFD0_NDAT2_ND45 *((volatile uint8_t *)(0x42E013B4UL)) +#define bFM_CANFD0_NDAT2_ND46 *((volatile uint8_t *)(0x42E013B8UL)) +#define bFM4_CANFD0_NDAT2_ND46 *((volatile uint8_t *)(0x42E013B8UL)) +#define bFM_CANFD0_NDAT2_ND47 *((volatile uint8_t *)(0x42E013BCUL)) +#define bFM4_CANFD0_NDAT2_ND47 *((volatile uint8_t *)(0x42E013BCUL)) +#define bFM_CANFD0_NDAT2_ND48 *((volatile uint8_t *)(0x42E013C0UL)) +#define bFM4_CANFD0_NDAT2_ND48 *((volatile uint8_t *)(0x42E013C0UL)) +#define bFM_CANFD0_NDAT2_ND49 *((volatile uint8_t *)(0x42E013C4UL)) +#define bFM4_CANFD0_NDAT2_ND49 *((volatile uint8_t *)(0x42E013C4UL)) +#define bFM_CANFD0_NDAT2_ND50 *((volatile uint8_t *)(0x42E013C8UL)) +#define bFM4_CANFD0_NDAT2_ND50 *((volatile uint8_t *)(0x42E013C8UL)) +#define bFM_CANFD0_NDAT2_ND51 *((volatile uint8_t *)(0x42E013CCUL)) +#define bFM4_CANFD0_NDAT2_ND51 *((volatile uint8_t *)(0x42E013CCUL)) +#define bFM_CANFD0_NDAT2_ND52 *((volatile uint8_t *)(0x42E013D0UL)) +#define bFM4_CANFD0_NDAT2_ND52 *((volatile uint8_t *)(0x42E013D0UL)) +#define bFM_CANFD0_NDAT2_ND53 *((volatile uint8_t *)(0x42E013D4UL)) +#define bFM4_CANFD0_NDAT2_ND53 *((volatile uint8_t *)(0x42E013D4UL)) +#define bFM_CANFD0_NDAT2_ND54 *((volatile uint8_t *)(0x42E013D8UL)) +#define bFM4_CANFD0_NDAT2_ND54 *((volatile uint8_t *)(0x42E013D8UL)) +#define bFM_CANFD0_NDAT2_ND55 *((volatile uint8_t *)(0x42E013DCUL)) +#define bFM4_CANFD0_NDAT2_ND55 *((volatile uint8_t *)(0x42E013DCUL)) +#define bFM_CANFD0_NDAT2_ND56 *((volatile uint8_t *)(0x42E013E0UL)) +#define bFM4_CANFD0_NDAT2_ND56 *((volatile uint8_t *)(0x42E013E0UL)) +#define bFM_CANFD0_NDAT2_ND57 *((volatile uint8_t *)(0x42E013E4UL)) +#define bFM4_CANFD0_NDAT2_ND57 *((volatile uint8_t *)(0x42E013E4UL)) +#define bFM_CANFD0_NDAT2_ND58 *((volatile uint8_t *)(0x42E013E8UL)) +#define bFM4_CANFD0_NDAT2_ND58 *((volatile uint8_t *)(0x42E013E8UL)) +#define bFM_CANFD0_NDAT2_ND59 *((volatile uint8_t *)(0x42E013ECUL)) +#define bFM4_CANFD0_NDAT2_ND59 *((volatile uint8_t *)(0x42E013ECUL)) +#define bFM_CANFD0_NDAT2_ND60 *((volatile uint8_t *)(0x42E013F0UL)) +#define bFM4_CANFD0_NDAT2_ND60 *((volatile uint8_t *)(0x42E013F0UL)) +#define bFM_CANFD0_NDAT2_ND61 *((volatile uint8_t *)(0x42E013F4UL)) +#define bFM4_CANFD0_NDAT2_ND61 *((volatile uint8_t *)(0x42E013F4UL)) +#define bFM_CANFD0_NDAT2_ND62 *((volatile uint8_t *)(0x42E013F8UL)) +#define bFM4_CANFD0_NDAT2_ND62 *((volatile uint8_t *)(0x42E013F8UL)) +#define bFM_CANFD0_NDAT2_ND63 *((volatile uint8_t *)(0x42E013FCUL)) +#define bFM4_CANFD0_NDAT2_ND63 *((volatile uint8_t *)(0x42E013FCUL)) + +#define bFM_CANFD0_PSR_EP *((volatile uint8_t *)(0x42E00894UL)) +#define bFM4_CANFD0_PSR_EP *((volatile uint8_t *)(0x42E00894UL)) +#define bFM_CANFD0_PSR_EW *((volatile uint8_t *)(0x42E00898UL)) +#define bFM4_CANFD0_PSR_EW *((volatile uint8_t *)(0x42E00898UL)) +#define bFM_CANFD0_PSR_BO *((volatile uint8_t *)(0x42E0089CUL)) +#define bFM4_CANFD0_PSR_BO *((volatile uint8_t *)(0x42E0089CUL)) +#define bFM_CANFD0_PSR_RESI *((volatile uint8_t *)(0x42E008ACUL)) +#define bFM4_CANFD0_PSR_RESI *((volatile uint8_t *)(0x42E008ACUL)) +#define bFM_CANFD0_PSR_RBRS *((volatile uint8_t *)(0x42E008B0UL)) +#define bFM4_CANFD0_PSR_RBRS *((volatile uint8_t *)(0x42E008B0UL)) +#define bFM_CANFD0_PSR_REDL *((volatile uint8_t *)(0x42E008B4UL)) +#define bFM4_CANFD0_PSR_REDL *((volatile uint8_t *)(0x42E008B4UL)) + +#define bFM_CANFD0_RXF0C_F0OM *((volatile uint8_t *)(0x42E0147CUL)) +#define bFM4_CANFD0_RXF0C_F0OM *((volatile uint8_t *)(0x42E0147CUL)) + +#define bFM_CANFD0_RXF0S_F0F *((volatile uint8_t *)(0x42E014E0UL)) +#define bFM4_CANFD0_RXF0S_F0F *((volatile uint8_t *)(0x42E014E0UL)) +#define bFM_CANFD0_RXF0S_RF0L *((volatile uint8_t *)(0x42E014E4UL)) +#define bFM4_CANFD0_RXF0S_RF0L *((volatile uint8_t *)(0x42E014E4UL)) + +#define bFM_CANFD0_RXF1C_F1OM *((volatile uint8_t *)(0x42E0167CUL)) +#define bFM4_CANFD0_RXF1C_F1OM *((volatile uint8_t *)(0x42E0167CUL)) + +#define bFM_CANFD0_RXF1S_F1F *((volatile uint8_t *)(0x42E016E0UL)) +#define bFM4_CANFD0_RXF1S_F1F *((volatile uint8_t *)(0x42E016E0UL)) +#define bFM_CANFD0_RXF1S_RF1L *((volatile uint8_t *)(0x42E016E4UL)) +#define bFM4_CANFD0_RXF1S_RF1L *((volatile uint8_t *)(0x42E016E4UL)) + +#define bFM_CANFD0_TEST_LBCK *((volatile uint8_t *)(0x42E00210UL)) +#define bFM4_CANFD0_TEST_LBCK *((volatile uint8_t *)(0x42E00210UL)) +#define bFM_CANFD0_TEST_RX *((volatile uint8_t *)(0x42E0021CUL)) +#define bFM4_CANFD0_TEST_RX *((volatile uint8_t *)(0x42E0021CUL)) + +#define bFM_CANFD0_TOCC_ETOC *((volatile uint8_t *)(0x42E00500UL)) +#define bFM4_CANFD0_TOCC_ETOC *((volatile uint8_t *)(0x42E00500UL)) + +#define bFM_CANFD0_TSCNTR_CCLR *((volatile uint8_t *)(0x42E04200UL)) +#define bFM4_CANFD0_TSCNTR_CCLR *((volatile uint8_t *)(0x42E04200UL)) + +#define bFM_CANFD0_TSMDR_CNTEN *((volatile uint8_t *)(0x42E04240UL)) +#define bFM4_CANFD0_TSMDR_CNTEN *((volatile uint8_t *)(0x42E04240UL)) + +#define bFM_CANFD0_TXBAR_AR0 *((volatile uint8_t *)(0x42E01A00UL)) +#define bFM4_CANFD0_TXBAR_AR0 *((volatile uint8_t *)(0x42E01A00UL)) +#define bFM_CANFD0_TXBAR_AR1 *((volatile uint8_t *)(0x42E01A04UL)) +#define bFM4_CANFD0_TXBAR_AR1 *((volatile uint8_t *)(0x42E01A04UL)) +#define bFM_CANFD0_TXBAR_AR2 *((volatile uint8_t *)(0x42E01A08UL)) +#define bFM4_CANFD0_TXBAR_AR2 *((volatile uint8_t *)(0x42E01A08UL)) +#define bFM_CANFD0_TXBAR_AR3 *((volatile uint8_t *)(0x42E01A0CUL)) +#define bFM4_CANFD0_TXBAR_AR3 *((volatile uint8_t *)(0x42E01A0CUL)) +#define bFM_CANFD0_TXBAR_AR4 *((volatile uint8_t *)(0x42E01A10UL)) +#define bFM4_CANFD0_TXBAR_AR4 *((volatile uint8_t *)(0x42E01A10UL)) +#define bFM_CANFD0_TXBAR_AR5 *((volatile uint8_t *)(0x42E01A14UL)) +#define bFM4_CANFD0_TXBAR_AR5 *((volatile uint8_t *)(0x42E01A14UL)) +#define bFM_CANFD0_TXBAR_AR6 *((volatile uint8_t *)(0x42E01A18UL)) +#define bFM4_CANFD0_TXBAR_AR6 *((volatile uint8_t *)(0x42E01A18UL)) +#define bFM_CANFD0_TXBAR_AR7 *((volatile uint8_t *)(0x42E01A1CUL)) +#define bFM4_CANFD0_TXBAR_AR7 *((volatile uint8_t *)(0x42E01A1CUL)) +#define bFM_CANFD0_TXBAR_AR8 *((volatile uint8_t *)(0x42E01A20UL)) +#define bFM4_CANFD0_TXBAR_AR8 *((volatile uint8_t *)(0x42E01A20UL)) +#define bFM_CANFD0_TXBAR_AR9 *((volatile uint8_t *)(0x42E01A24UL)) +#define bFM4_CANFD0_TXBAR_AR9 *((volatile uint8_t *)(0x42E01A24UL)) +#define bFM_CANFD0_TXBAR_AR10 *((volatile uint8_t *)(0x42E01A28UL)) +#define bFM4_CANFD0_TXBAR_AR10 *((volatile uint8_t *)(0x42E01A28UL)) +#define bFM_CANFD0_TXBAR_AR11 *((volatile uint8_t *)(0x42E01A2CUL)) +#define bFM4_CANFD0_TXBAR_AR11 *((volatile uint8_t *)(0x42E01A2CUL)) +#define bFM_CANFD0_TXBAR_AR12 *((volatile uint8_t *)(0x42E01A30UL)) +#define bFM4_CANFD0_TXBAR_AR12 *((volatile uint8_t *)(0x42E01A30UL)) +#define bFM_CANFD0_TXBAR_AR13 *((volatile uint8_t *)(0x42E01A34UL)) +#define bFM4_CANFD0_TXBAR_AR13 *((volatile uint8_t *)(0x42E01A34UL)) +#define bFM_CANFD0_TXBAR_AR14 *((volatile uint8_t *)(0x42E01A38UL)) +#define bFM4_CANFD0_TXBAR_AR14 *((volatile uint8_t *)(0x42E01A38UL)) +#define bFM_CANFD0_TXBAR_AR15 *((volatile uint8_t *)(0x42E01A3CUL)) +#define bFM4_CANFD0_TXBAR_AR15 *((volatile uint8_t *)(0x42E01A3CUL)) +#define bFM_CANFD0_TXBAR_AR16 *((volatile uint8_t *)(0x42E01A40UL)) +#define bFM4_CANFD0_TXBAR_AR16 *((volatile uint8_t *)(0x42E01A40UL)) +#define bFM_CANFD0_TXBAR_AR17 *((volatile uint8_t *)(0x42E01A44UL)) +#define bFM4_CANFD0_TXBAR_AR17 *((volatile uint8_t *)(0x42E01A44UL)) +#define bFM_CANFD0_TXBAR_AR18 *((volatile uint8_t *)(0x42E01A48UL)) +#define bFM4_CANFD0_TXBAR_AR18 *((volatile uint8_t *)(0x42E01A48UL)) +#define bFM_CANFD0_TXBAR_AR19 *((volatile uint8_t *)(0x42E01A4CUL)) +#define bFM4_CANFD0_TXBAR_AR19 *((volatile uint8_t *)(0x42E01A4CUL)) +#define bFM_CANFD0_TXBAR_AR20 *((volatile uint8_t *)(0x42E01A50UL)) +#define bFM4_CANFD0_TXBAR_AR20 *((volatile uint8_t *)(0x42E01A50UL)) +#define bFM_CANFD0_TXBAR_AR21 *((volatile uint8_t *)(0x42E01A54UL)) +#define bFM4_CANFD0_TXBAR_AR21 *((volatile uint8_t *)(0x42E01A54UL)) +#define bFM_CANFD0_TXBAR_AR22 *((volatile uint8_t *)(0x42E01A58UL)) +#define bFM4_CANFD0_TXBAR_AR22 *((volatile uint8_t *)(0x42E01A58UL)) +#define bFM_CANFD0_TXBAR_AR23 *((volatile uint8_t *)(0x42E01A5CUL)) +#define bFM4_CANFD0_TXBAR_AR23 *((volatile uint8_t *)(0x42E01A5CUL)) +#define bFM_CANFD0_TXBAR_AR24 *((volatile uint8_t *)(0x42E01A60UL)) +#define bFM4_CANFD0_TXBAR_AR24 *((volatile uint8_t *)(0x42E01A60UL)) +#define bFM_CANFD0_TXBAR_AR25 *((volatile uint8_t *)(0x42E01A64UL)) +#define bFM4_CANFD0_TXBAR_AR25 *((volatile uint8_t *)(0x42E01A64UL)) +#define bFM_CANFD0_TXBAR_AR26 *((volatile uint8_t *)(0x42E01A68UL)) +#define bFM4_CANFD0_TXBAR_AR26 *((volatile uint8_t *)(0x42E01A68UL)) +#define bFM_CANFD0_TXBAR_AR27 *((volatile uint8_t *)(0x42E01A6CUL)) +#define bFM4_CANFD0_TXBAR_AR27 *((volatile uint8_t *)(0x42E01A6CUL)) +#define bFM_CANFD0_TXBAR_AR28 *((volatile uint8_t *)(0x42E01A70UL)) +#define bFM4_CANFD0_TXBAR_AR28 *((volatile uint8_t *)(0x42E01A70UL)) +#define bFM_CANFD0_TXBAR_AR29 *((volatile uint8_t *)(0x42E01A74UL)) +#define bFM4_CANFD0_TXBAR_AR29 *((volatile uint8_t *)(0x42E01A74UL)) +#define bFM_CANFD0_TXBAR_AR30 *((volatile uint8_t *)(0x42E01A78UL)) +#define bFM4_CANFD0_TXBAR_AR30 *((volatile uint8_t *)(0x42E01A78UL)) +#define bFM_CANFD0_TXBAR_AR31 *((volatile uint8_t *)(0x42E01A7CUL)) +#define bFM4_CANFD0_TXBAR_AR31 *((volatile uint8_t *)(0x42E01A7CUL)) + +#define bFM_CANFD0_TXBC_TFQM *((volatile uint8_t *)(0x42E01878UL)) +#define bFM4_CANFD0_TXBC_TFQM *((volatile uint8_t *)(0x42E01878UL)) + +#define bFM_CANFD0_TXBCF_CF0 *((volatile uint8_t *)(0x42E01B80UL)) +#define bFM4_CANFD0_TXBCF_CF0 *((volatile uint8_t *)(0x42E01B80UL)) +#define bFM_CANFD0_TXBCF_CF1 *((volatile uint8_t *)(0x42E01B84UL)) +#define bFM4_CANFD0_TXBCF_CF1 *((volatile uint8_t *)(0x42E01B84UL)) +#define bFM_CANFD0_TXBCF_CF2 *((volatile uint8_t *)(0x42E01B88UL)) +#define bFM4_CANFD0_TXBCF_CF2 *((volatile uint8_t *)(0x42E01B88UL)) +#define bFM_CANFD0_TXBCF_CF3 *((volatile uint8_t *)(0x42E01B8CUL)) +#define bFM4_CANFD0_TXBCF_CF3 *((volatile uint8_t *)(0x42E01B8CUL)) +#define bFM_CANFD0_TXBCF_CF4 *((volatile uint8_t *)(0x42E01B90UL)) +#define bFM4_CANFD0_TXBCF_CF4 *((volatile uint8_t *)(0x42E01B90UL)) +#define bFM_CANFD0_TXBCF_CF5 *((volatile uint8_t *)(0x42E01B94UL)) +#define bFM4_CANFD0_TXBCF_CF5 *((volatile uint8_t *)(0x42E01B94UL)) +#define bFM_CANFD0_TXBCF_CF6 *((volatile uint8_t *)(0x42E01B98UL)) +#define bFM4_CANFD0_TXBCF_CF6 *((volatile uint8_t *)(0x42E01B98UL)) +#define bFM_CANFD0_TXBCF_CF7 *((volatile uint8_t *)(0x42E01B9CUL)) +#define bFM4_CANFD0_TXBCF_CF7 *((volatile uint8_t *)(0x42E01B9CUL)) +#define bFM_CANFD0_TXBCF_CF8 *((volatile uint8_t *)(0x42E01BA0UL)) +#define bFM4_CANFD0_TXBCF_CF8 *((volatile uint8_t *)(0x42E01BA0UL)) +#define bFM_CANFD0_TXBCF_CF9 *((volatile uint8_t *)(0x42E01BA4UL)) +#define bFM4_CANFD0_TXBCF_CF9 *((volatile uint8_t *)(0x42E01BA4UL)) +#define bFM_CANFD0_TXBCF_CF10 *((volatile uint8_t *)(0x42E01BA8UL)) +#define bFM4_CANFD0_TXBCF_CF10 *((volatile uint8_t *)(0x42E01BA8UL)) +#define bFM_CANFD0_TXBCF_CF11 *((volatile uint8_t *)(0x42E01BACUL)) +#define bFM4_CANFD0_TXBCF_CF11 *((volatile uint8_t *)(0x42E01BACUL)) +#define bFM_CANFD0_TXBCF_CF12 *((volatile uint8_t *)(0x42E01BB0UL)) +#define bFM4_CANFD0_TXBCF_CF12 *((volatile uint8_t *)(0x42E01BB0UL)) +#define bFM_CANFD0_TXBCF_CF13 *((volatile uint8_t *)(0x42E01BB4UL)) +#define bFM4_CANFD0_TXBCF_CF13 *((volatile uint8_t *)(0x42E01BB4UL)) +#define bFM_CANFD0_TXBCF_CF14 *((volatile uint8_t *)(0x42E01BB8UL)) +#define bFM4_CANFD0_TXBCF_CF14 *((volatile uint8_t *)(0x42E01BB8UL)) +#define bFM_CANFD0_TXBCF_CF15 *((volatile uint8_t *)(0x42E01BBCUL)) +#define bFM4_CANFD0_TXBCF_CF15 *((volatile uint8_t *)(0x42E01BBCUL)) +#define bFM_CANFD0_TXBCF_CF16 *((volatile uint8_t *)(0x42E01BC0UL)) +#define bFM4_CANFD0_TXBCF_CF16 *((volatile uint8_t *)(0x42E01BC0UL)) +#define bFM_CANFD0_TXBCF_CF17 *((volatile uint8_t *)(0x42E01BC4UL)) +#define bFM4_CANFD0_TXBCF_CF17 *((volatile uint8_t *)(0x42E01BC4UL)) +#define bFM_CANFD0_TXBCF_CF18 *((volatile uint8_t *)(0x42E01BC8UL)) +#define bFM4_CANFD0_TXBCF_CF18 *((volatile uint8_t *)(0x42E01BC8UL)) +#define bFM_CANFD0_TXBCF_CF19 *((volatile uint8_t *)(0x42E01BCCUL)) +#define bFM4_CANFD0_TXBCF_CF19 *((volatile uint8_t *)(0x42E01BCCUL)) +#define bFM_CANFD0_TXBCF_CF20 *((volatile uint8_t *)(0x42E01BD0UL)) +#define bFM4_CANFD0_TXBCF_CF20 *((volatile uint8_t *)(0x42E01BD0UL)) +#define bFM_CANFD0_TXBCF_CF21 *((volatile uint8_t *)(0x42E01BD4UL)) +#define bFM4_CANFD0_TXBCF_CF21 *((volatile uint8_t *)(0x42E01BD4UL)) +#define bFM_CANFD0_TXBCF_CF22 *((volatile uint8_t *)(0x42E01BD8UL)) +#define bFM4_CANFD0_TXBCF_CF22 *((volatile uint8_t *)(0x42E01BD8UL)) +#define bFM_CANFD0_TXBCF_CF23 *((volatile uint8_t *)(0x42E01BDCUL)) +#define bFM4_CANFD0_TXBCF_CF23 *((volatile uint8_t *)(0x42E01BDCUL)) +#define bFM_CANFD0_TXBCF_CF24 *((volatile uint8_t *)(0x42E01BE0UL)) +#define bFM4_CANFD0_TXBCF_CF24 *((volatile uint8_t *)(0x42E01BE0UL)) +#define bFM_CANFD0_TXBCF_CF25 *((volatile uint8_t *)(0x42E01BE4UL)) +#define bFM4_CANFD0_TXBCF_CF25 *((volatile uint8_t *)(0x42E01BE4UL)) +#define bFM_CANFD0_TXBCF_CF26 *((volatile uint8_t *)(0x42E01BE8UL)) +#define bFM4_CANFD0_TXBCF_CF26 *((volatile uint8_t *)(0x42E01BE8UL)) +#define bFM_CANFD0_TXBCF_CF27 *((volatile uint8_t *)(0x42E01BECUL)) +#define bFM4_CANFD0_TXBCF_CF27 *((volatile uint8_t *)(0x42E01BECUL)) +#define bFM_CANFD0_TXBCF_CF28 *((volatile uint8_t *)(0x42E01BF0UL)) +#define bFM4_CANFD0_TXBCF_CF28 *((volatile uint8_t *)(0x42E01BF0UL)) +#define bFM_CANFD0_TXBCF_CF29 *((volatile uint8_t *)(0x42E01BF4UL)) +#define bFM4_CANFD0_TXBCF_CF29 *((volatile uint8_t *)(0x42E01BF4UL)) +#define bFM_CANFD0_TXBCF_CF30 *((volatile uint8_t *)(0x42E01BF8UL)) +#define bFM4_CANFD0_TXBCF_CF30 *((volatile uint8_t *)(0x42E01BF8UL)) +#define bFM_CANFD0_TXBCF_CF31 *((volatile uint8_t *)(0x42E01BFCUL)) +#define bFM4_CANFD0_TXBCF_CF31 *((volatile uint8_t *)(0x42E01BFCUL)) + +#define bFM_CANFD0_TXBCIE_CFIE0 *((volatile uint8_t *)(0x42E01C80UL)) +#define bFM4_CANFD0_TXBCIE_CFIE0 *((volatile uint8_t *)(0x42E01C80UL)) +#define bFM_CANFD0_TXBCIE_CFIE1 *((volatile uint8_t *)(0x42E01C84UL)) +#define bFM4_CANFD0_TXBCIE_CFIE1 *((volatile uint8_t *)(0x42E01C84UL)) +#define bFM_CANFD0_TXBCIE_CFIE2 *((volatile uint8_t *)(0x42E01C88UL)) +#define bFM4_CANFD0_TXBCIE_CFIE2 *((volatile uint8_t *)(0x42E01C88UL)) +#define bFM_CANFD0_TXBCIE_CFIE3 *((volatile uint8_t *)(0x42E01C8CUL)) +#define bFM4_CANFD0_TXBCIE_CFIE3 *((volatile uint8_t *)(0x42E01C8CUL)) +#define bFM_CANFD0_TXBCIE_CFIE4 *((volatile uint8_t *)(0x42E01C90UL)) +#define bFM4_CANFD0_TXBCIE_CFIE4 *((volatile uint8_t *)(0x42E01C90UL)) +#define bFM_CANFD0_TXBCIE_CFIE5 *((volatile uint8_t *)(0x42E01C94UL)) +#define bFM4_CANFD0_TXBCIE_CFIE5 *((volatile uint8_t *)(0x42E01C94UL)) +#define bFM_CANFD0_TXBCIE_CFIE6 *((volatile uint8_t *)(0x42E01C98UL)) +#define bFM4_CANFD0_TXBCIE_CFIE6 *((volatile uint8_t *)(0x42E01C98UL)) +#define bFM_CANFD0_TXBCIE_CFIE7 *((volatile uint8_t *)(0x42E01C9CUL)) +#define bFM4_CANFD0_TXBCIE_CFIE7 *((volatile uint8_t *)(0x42E01C9CUL)) +#define bFM_CANFD0_TXBCIE_CFIE8 *((volatile uint8_t *)(0x42E01CA0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE8 *((volatile uint8_t *)(0x42E01CA0UL)) +#define bFM_CANFD0_TXBCIE_CFIE9 *((volatile uint8_t *)(0x42E01CA4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE9 *((volatile uint8_t *)(0x42E01CA4UL)) +#define bFM_CANFD0_TXBCIE_CFIE10 *((volatile uint8_t *)(0x42E01CA8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE10 *((volatile uint8_t *)(0x42E01CA8UL)) +#define bFM_CANFD0_TXBCIE_CFIE11 *((volatile uint8_t *)(0x42E01CACUL)) +#define bFM4_CANFD0_TXBCIE_CFIE11 *((volatile uint8_t *)(0x42E01CACUL)) +#define bFM_CANFD0_TXBCIE_CFIE12 *((volatile uint8_t *)(0x42E01CB0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE12 *((volatile uint8_t *)(0x42E01CB0UL)) +#define bFM_CANFD0_TXBCIE_CFIE13 *((volatile uint8_t *)(0x42E01CB4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE13 *((volatile uint8_t *)(0x42E01CB4UL)) +#define bFM_CANFD0_TXBCIE_CFIE14 *((volatile uint8_t *)(0x42E01CB8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE14 *((volatile uint8_t *)(0x42E01CB8UL)) +#define bFM_CANFD0_TXBCIE_CFIE15 *((volatile uint8_t *)(0x42E01CBCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE15 *((volatile uint8_t *)(0x42E01CBCUL)) +#define bFM_CANFD0_TXBCIE_CFIE16 *((volatile uint8_t *)(0x42E01CC0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE16 *((volatile uint8_t *)(0x42E01CC0UL)) +#define bFM_CANFD0_TXBCIE_CFIE17 *((volatile uint8_t *)(0x42E01CC4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE17 *((volatile uint8_t *)(0x42E01CC4UL)) +#define bFM_CANFD0_TXBCIE_CFIE18 *((volatile uint8_t *)(0x42E01CC8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE18 *((volatile uint8_t *)(0x42E01CC8UL)) +#define bFM_CANFD0_TXBCIE_CFIE19 *((volatile uint8_t *)(0x42E01CCCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE19 *((volatile uint8_t *)(0x42E01CCCUL)) +#define bFM_CANFD0_TXBCIE_CFIE20 *((volatile uint8_t *)(0x42E01CD0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE20 *((volatile uint8_t *)(0x42E01CD0UL)) +#define bFM_CANFD0_TXBCIE_CFIE21 *((volatile uint8_t *)(0x42E01CD4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE21 *((volatile uint8_t *)(0x42E01CD4UL)) +#define bFM_CANFD0_TXBCIE_CFIE22 *((volatile uint8_t *)(0x42E01CD8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE22 *((volatile uint8_t *)(0x42E01CD8UL)) +#define bFM_CANFD0_TXBCIE_CFIE23 *((volatile uint8_t *)(0x42E01CDCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE23 *((volatile uint8_t *)(0x42E01CDCUL)) +#define bFM_CANFD0_TXBCIE_CFIE24 *((volatile uint8_t *)(0x42E01CE0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE24 *((volatile uint8_t *)(0x42E01CE0UL)) +#define bFM_CANFD0_TXBCIE_CFIE25 *((volatile uint8_t *)(0x42E01CE4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE25 *((volatile uint8_t *)(0x42E01CE4UL)) +#define bFM_CANFD0_TXBCIE_CFIE26 *((volatile uint8_t *)(0x42E01CE8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE26 *((volatile uint8_t *)(0x42E01CE8UL)) +#define bFM_CANFD0_TXBCIE_CFIE27 *((volatile uint8_t *)(0x42E01CECUL)) +#define bFM4_CANFD0_TXBCIE_CFIE27 *((volatile uint8_t *)(0x42E01CECUL)) +#define bFM_CANFD0_TXBCIE_CFIE28 *((volatile uint8_t *)(0x42E01CF0UL)) +#define bFM4_CANFD0_TXBCIE_CFIE28 *((volatile uint8_t *)(0x42E01CF0UL)) +#define bFM_CANFD0_TXBCIE_CFIE29 *((volatile uint8_t *)(0x42E01CF4UL)) +#define bFM4_CANFD0_TXBCIE_CFIE29 *((volatile uint8_t *)(0x42E01CF4UL)) +#define bFM_CANFD0_TXBCIE_CFIE30 *((volatile uint8_t *)(0x42E01CF8UL)) +#define bFM4_CANFD0_TXBCIE_CFIE30 *((volatile uint8_t *)(0x42E01CF8UL)) +#define bFM_CANFD0_TXBCIE_CFIE31 *((volatile uint8_t *)(0x42E01CFCUL)) +#define bFM4_CANFD0_TXBCIE_CFIE31 *((volatile uint8_t *)(0x42E01CFCUL)) + +#define bFM_CANFD0_TXBCR_CR0 *((volatile uint8_t *)(0x42E01A80UL)) +#define bFM4_CANFD0_TXBCR_CR0 *((volatile uint8_t *)(0x42E01A80UL)) +#define bFM_CANFD0_TXBCR_CR1 *((volatile uint8_t *)(0x42E01A84UL)) +#define bFM4_CANFD0_TXBCR_CR1 *((volatile uint8_t *)(0x42E01A84UL)) +#define bFM_CANFD0_TXBCR_CR2 *((volatile uint8_t *)(0x42E01A88UL)) +#define bFM4_CANFD0_TXBCR_CR2 *((volatile uint8_t *)(0x42E01A88UL)) +#define bFM_CANFD0_TXBCR_CR3 *((volatile uint8_t *)(0x42E01A8CUL)) +#define bFM4_CANFD0_TXBCR_CR3 *((volatile uint8_t *)(0x42E01A8CUL)) +#define bFM_CANFD0_TXBCR_CR4 *((volatile uint8_t *)(0x42E01A90UL)) +#define bFM4_CANFD0_TXBCR_CR4 *((volatile uint8_t *)(0x42E01A90UL)) +#define bFM_CANFD0_TXBCR_CR5 *((volatile uint8_t *)(0x42E01A94UL)) +#define bFM4_CANFD0_TXBCR_CR5 *((volatile uint8_t *)(0x42E01A94UL)) +#define bFM_CANFD0_TXBCR_CR6 *((volatile uint8_t *)(0x42E01A98UL)) +#define bFM4_CANFD0_TXBCR_CR6 *((volatile uint8_t *)(0x42E01A98UL)) +#define bFM_CANFD0_TXBCR_CR7 *((volatile uint8_t *)(0x42E01A9CUL)) +#define bFM4_CANFD0_TXBCR_CR7 *((volatile uint8_t *)(0x42E01A9CUL)) +#define bFM_CANFD0_TXBCR_CR8 *((volatile uint8_t *)(0x42E01AA0UL)) +#define bFM4_CANFD0_TXBCR_CR8 *((volatile uint8_t *)(0x42E01AA0UL)) +#define bFM_CANFD0_TXBCR_CR9 *((volatile uint8_t *)(0x42E01AA4UL)) +#define bFM4_CANFD0_TXBCR_CR9 *((volatile uint8_t *)(0x42E01AA4UL)) +#define bFM_CANFD0_TXBCR_CR10 *((volatile uint8_t *)(0x42E01AA8UL)) +#define bFM4_CANFD0_TXBCR_CR10 *((volatile uint8_t *)(0x42E01AA8UL)) +#define bFM_CANFD0_TXBCR_CR11 *((volatile uint8_t *)(0x42E01AACUL)) +#define bFM4_CANFD0_TXBCR_CR11 *((volatile uint8_t *)(0x42E01AACUL)) +#define bFM_CANFD0_TXBCR_CR12 *((volatile uint8_t *)(0x42E01AB0UL)) +#define bFM4_CANFD0_TXBCR_CR12 *((volatile uint8_t *)(0x42E01AB0UL)) +#define bFM_CANFD0_TXBCR_CR13 *((volatile uint8_t *)(0x42E01AB4UL)) +#define bFM4_CANFD0_TXBCR_CR13 *((volatile uint8_t *)(0x42E01AB4UL)) +#define bFM_CANFD0_TXBCR_CR14 *((volatile uint8_t *)(0x42E01AB8UL)) +#define bFM4_CANFD0_TXBCR_CR14 *((volatile uint8_t *)(0x42E01AB8UL)) +#define bFM_CANFD0_TXBCR_CR15 *((volatile uint8_t *)(0x42E01ABCUL)) +#define bFM4_CANFD0_TXBCR_CR15 *((volatile uint8_t *)(0x42E01ABCUL)) +#define bFM_CANFD0_TXBCR_CR16 *((volatile uint8_t *)(0x42E01AC0UL)) +#define bFM4_CANFD0_TXBCR_CR16 *((volatile uint8_t *)(0x42E01AC0UL)) +#define bFM_CANFD0_TXBCR_CR17 *((volatile uint8_t *)(0x42E01AC4UL)) +#define bFM4_CANFD0_TXBCR_CR17 *((volatile uint8_t *)(0x42E01AC4UL)) +#define bFM_CANFD0_TXBCR_CR18 *((volatile uint8_t *)(0x42E01AC8UL)) +#define bFM4_CANFD0_TXBCR_CR18 *((volatile uint8_t *)(0x42E01AC8UL)) +#define bFM_CANFD0_TXBCR_CR19 *((volatile uint8_t *)(0x42E01ACCUL)) +#define bFM4_CANFD0_TXBCR_CR19 *((volatile uint8_t *)(0x42E01ACCUL)) +#define bFM_CANFD0_TXBCR_CR20 *((volatile uint8_t *)(0x42E01AD0UL)) +#define bFM4_CANFD0_TXBCR_CR20 *((volatile uint8_t *)(0x42E01AD0UL)) +#define bFM_CANFD0_TXBCR_CR21 *((volatile uint8_t *)(0x42E01AD4UL)) +#define bFM4_CANFD0_TXBCR_CR21 *((volatile uint8_t *)(0x42E01AD4UL)) +#define bFM_CANFD0_TXBCR_CR22 *((volatile uint8_t *)(0x42E01AD8UL)) +#define bFM4_CANFD0_TXBCR_CR22 *((volatile uint8_t *)(0x42E01AD8UL)) +#define bFM_CANFD0_TXBCR_CR23 *((volatile uint8_t *)(0x42E01ADCUL)) +#define bFM4_CANFD0_TXBCR_CR23 *((volatile uint8_t *)(0x42E01ADCUL)) +#define bFM_CANFD0_TXBCR_CR24 *((volatile uint8_t *)(0x42E01AE0UL)) +#define bFM4_CANFD0_TXBCR_CR24 *((volatile uint8_t *)(0x42E01AE0UL)) +#define bFM_CANFD0_TXBCR_CR25 *((volatile uint8_t *)(0x42E01AE4UL)) +#define bFM4_CANFD0_TXBCR_CR25 *((volatile uint8_t *)(0x42E01AE4UL)) +#define bFM_CANFD0_TXBCR_CR26 *((volatile uint8_t *)(0x42E01AE8UL)) +#define bFM4_CANFD0_TXBCR_CR26 *((volatile uint8_t *)(0x42E01AE8UL)) +#define bFM_CANFD0_TXBCR_CR27 *((volatile uint8_t *)(0x42E01AECUL)) +#define bFM4_CANFD0_TXBCR_CR27 *((volatile uint8_t *)(0x42E01AECUL)) +#define bFM_CANFD0_TXBCR_CR28 *((volatile uint8_t *)(0x42E01AF0UL)) +#define bFM4_CANFD0_TXBCR_CR28 *((volatile uint8_t *)(0x42E01AF0UL)) +#define bFM_CANFD0_TXBCR_CR29 *((volatile uint8_t *)(0x42E01AF4UL)) +#define bFM4_CANFD0_TXBCR_CR29 *((volatile uint8_t *)(0x42E01AF4UL)) +#define bFM_CANFD0_TXBCR_CR30 *((volatile uint8_t *)(0x42E01AF8UL)) +#define bFM4_CANFD0_TXBCR_CR30 *((volatile uint8_t *)(0x42E01AF8UL)) +#define bFM_CANFD0_TXBCR_CR31 *((volatile uint8_t *)(0x42E01AFCUL)) +#define bFM4_CANFD0_TXBCR_CR31 *((volatile uint8_t *)(0x42E01AFCUL)) + +#define bFM_CANFD0_TXBRP_TRP0 *((volatile uint8_t *)(0x42E01980UL)) +#define bFM4_CANFD0_TXBRP_TRP0 *((volatile uint8_t *)(0x42E01980UL)) +#define bFM_CANFD0_TXBRP_TRP1 *((volatile uint8_t *)(0x42E01984UL)) +#define bFM4_CANFD0_TXBRP_TRP1 *((volatile uint8_t *)(0x42E01984UL)) +#define bFM_CANFD0_TXBRP_TRP2 *((volatile uint8_t *)(0x42E01988UL)) +#define bFM4_CANFD0_TXBRP_TRP2 *((volatile uint8_t *)(0x42E01988UL)) +#define bFM_CANFD0_TXBRP_TRP3 *((volatile uint8_t *)(0x42E0198CUL)) +#define bFM4_CANFD0_TXBRP_TRP3 *((volatile uint8_t *)(0x42E0198CUL)) +#define bFM_CANFD0_TXBRP_TRP4 *((volatile uint8_t *)(0x42E01990UL)) +#define bFM4_CANFD0_TXBRP_TRP4 *((volatile uint8_t *)(0x42E01990UL)) +#define bFM_CANFD0_TXBRP_TRP5 *((volatile uint8_t *)(0x42E01994UL)) +#define bFM4_CANFD0_TXBRP_TRP5 *((volatile uint8_t *)(0x42E01994UL)) +#define bFM_CANFD0_TXBRP_TRP6 *((volatile uint8_t *)(0x42E01998UL)) +#define bFM4_CANFD0_TXBRP_TRP6 *((volatile uint8_t *)(0x42E01998UL)) +#define bFM_CANFD0_TXBRP_TRP7 *((volatile uint8_t *)(0x42E0199CUL)) +#define bFM4_CANFD0_TXBRP_TRP7 *((volatile uint8_t *)(0x42E0199CUL)) +#define bFM_CANFD0_TXBRP_TRP8 *((volatile uint8_t *)(0x42E019A0UL)) +#define bFM4_CANFD0_TXBRP_TRP8 *((volatile uint8_t *)(0x42E019A0UL)) +#define bFM_CANFD0_TXBRP_TRP9 *((volatile uint8_t *)(0x42E019A4UL)) +#define bFM4_CANFD0_TXBRP_TRP9 *((volatile uint8_t *)(0x42E019A4UL)) +#define bFM_CANFD0_TXBRP_TRP10 *((volatile uint8_t *)(0x42E019A8UL)) +#define bFM4_CANFD0_TXBRP_TRP10 *((volatile uint8_t *)(0x42E019A8UL)) +#define bFM_CANFD0_TXBRP_TRP11 *((volatile uint8_t *)(0x42E019ACUL)) +#define bFM4_CANFD0_TXBRP_TRP11 *((volatile uint8_t *)(0x42E019ACUL)) +#define bFM_CANFD0_TXBRP_TRP12 *((volatile uint8_t *)(0x42E019B0UL)) +#define bFM4_CANFD0_TXBRP_TRP12 *((volatile uint8_t *)(0x42E019B0UL)) +#define bFM_CANFD0_TXBRP_TRP13 *((volatile uint8_t *)(0x42E019B4UL)) +#define bFM4_CANFD0_TXBRP_TRP13 *((volatile uint8_t *)(0x42E019B4UL)) +#define bFM_CANFD0_TXBRP_TRP14 *((volatile uint8_t *)(0x42E019B8UL)) +#define bFM4_CANFD0_TXBRP_TRP14 *((volatile uint8_t *)(0x42E019B8UL)) +#define bFM_CANFD0_TXBRP_TRP15 *((volatile uint8_t *)(0x42E019BCUL)) +#define bFM4_CANFD0_TXBRP_TRP15 *((volatile uint8_t *)(0x42E019BCUL)) +#define bFM_CANFD0_TXBRP_TRP16 *((volatile uint8_t *)(0x42E019C0UL)) +#define bFM4_CANFD0_TXBRP_TRP16 *((volatile uint8_t *)(0x42E019C0UL)) +#define bFM_CANFD0_TXBRP_TRP17 *((volatile uint8_t *)(0x42E019C4UL)) +#define bFM4_CANFD0_TXBRP_TRP17 *((volatile uint8_t *)(0x42E019C4UL)) +#define bFM_CANFD0_TXBRP_TRP18 *((volatile uint8_t *)(0x42E019C8UL)) +#define bFM4_CANFD0_TXBRP_TRP18 *((volatile uint8_t *)(0x42E019C8UL)) +#define bFM_CANFD0_TXBRP_TRP19 *((volatile uint8_t *)(0x42E019CCUL)) +#define bFM4_CANFD0_TXBRP_TRP19 *((volatile uint8_t *)(0x42E019CCUL)) +#define bFM_CANFD0_TXBRP_TRP20 *((volatile uint8_t *)(0x42E019D0UL)) +#define bFM4_CANFD0_TXBRP_TRP20 *((volatile uint8_t *)(0x42E019D0UL)) +#define bFM_CANFD0_TXBRP_TRP21 *((volatile uint8_t *)(0x42E019D4UL)) +#define bFM4_CANFD0_TXBRP_TRP21 *((volatile uint8_t *)(0x42E019D4UL)) +#define bFM_CANFD0_TXBRP_TRP22 *((volatile uint8_t *)(0x42E019D8UL)) +#define bFM4_CANFD0_TXBRP_TRP22 *((volatile uint8_t *)(0x42E019D8UL)) +#define bFM_CANFD0_TXBRP_TRP23 *((volatile uint8_t *)(0x42E019DCUL)) +#define bFM4_CANFD0_TXBRP_TRP23 *((volatile uint8_t *)(0x42E019DCUL)) +#define bFM_CANFD0_TXBRP_TRP24 *((volatile uint8_t *)(0x42E019E0UL)) +#define bFM4_CANFD0_TXBRP_TRP24 *((volatile uint8_t *)(0x42E019E0UL)) +#define bFM_CANFD0_TXBRP_TRP25 *((volatile uint8_t *)(0x42E019E4UL)) +#define bFM4_CANFD0_TXBRP_TRP25 *((volatile uint8_t *)(0x42E019E4UL)) +#define bFM_CANFD0_TXBRP_TRP26 *((volatile uint8_t *)(0x42E019E8UL)) +#define bFM4_CANFD0_TXBRP_TRP26 *((volatile uint8_t *)(0x42E019E8UL)) +#define bFM_CANFD0_TXBRP_TRP27 *((volatile uint8_t *)(0x42E019ECUL)) +#define bFM4_CANFD0_TXBRP_TRP27 *((volatile uint8_t *)(0x42E019ECUL)) +#define bFM_CANFD0_TXBRP_TRP28 *((volatile uint8_t *)(0x42E019F0UL)) +#define bFM4_CANFD0_TXBRP_TRP28 *((volatile uint8_t *)(0x42E019F0UL)) +#define bFM_CANFD0_TXBRP_TRP29 *((volatile uint8_t *)(0x42E019F4UL)) +#define bFM4_CANFD0_TXBRP_TRP29 *((volatile uint8_t *)(0x42E019F4UL)) +#define bFM_CANFD0_TXBRP_TRP30 *((volatile uint8_t *)(0x42E019F8UL)) +#define bFM4_CANFD0_TXBRP_TRP30 *((volatile uint8_t *)(0x42E019F8UL)) +#define bFM_CANFD0_TXBRP_TRP31 *((volatile uint8_t *)(0x42E019FCUL)) +#define bFM4_CANFD0_TXBRP_TRP31 *((volatile uint8_t *)(0x42E019FCUL)) + +#define bFM_CANFD0_TXBTIE_TIE0 *((volatile uint8_t *)(0x42E01C00UL)) +#define bFM4_CANFD0_TXBTIE_TIE0 *((volatile uint8_t *)(0x42E01C00UL)) +#define bFM_CANFD0_TXBTIE_TIE1 *((volatile uint8_t *)(0x42E01C04UL)) +#define bFM4_CANFD0_TXBTIE_TIE1 *((volatile uint8_t *)(0x42E01C04UL)) +#define bFM_CANFD0_TXBTIE_TIE2 *((volatile uint8_t *)(0x42E01C08UL)) +#define bFM4_CANFD0_TXBTIE_TIE2 *((volatile uint8_t *)(0x42E01C08UL)) +#define bFM_CANFD0_TXBTIE_TIE3 *((volatile uint8_t *)(0x42E01C0CUL)) +#define bFM4_CANFD0_TXBTIE_TIE3 *((volatile uint8_t *)(0x42E01C0CUL)) +#define bFM_CANFD0_TXBTIE_TIE4 *((volatile uint8_t *)(0x42E01C10UL)) +#define bFM4_CANFD0_TXBTIE_TIE4 *((volatile uint8_t *)(0x42E01C10UL)) +#define bFM_CANFD0_TXBTIE_TIE5 *((volatile uint8_t *)(0x42E01C14UL)) +#define bFM4_CANFD0_TXBTIE_TIE5 *((volatile uint8_t *)(0x42E01C14UL)) +#define bFM_CANFD0_TXBTIE_TIE6 *((volatile uint8_t *)(0x42E01C18UL)) +#define bFM4_CANFD0_TXBTIE_TIE6 *((volatile uint8_t *)(0x42E01C18UL)) +#define bFM_CANFD0_TXBTIE_TIE7 *((volatile uint8_t *)(0x42E01C1CUL)) +#define bFM4_CANFD0_TXBTIE_TIE7 *((volatile uint8_t *)(0x42E01C1CUL)) +#define bFM_CANFD0_TXBTIE_TIE8 *((volatile uint8_t *)(0x42E01C20UL)) +#define bFM4_CANFD0_TXBTIE_TIE8 *((volatile uint8_t *)(0x42E01C20UL)) +#define bFM_CANFD0_TXBTIE_TIE9 *((volatile uint8_t *)(0x42E01C24UL)) +#define bFM4_CANFD0_TXBTIE_TIE9 *((volatile uint8_t *)(0x42E01C24UL)) +#define bFM_CANFD0_TXBTIE_TIE10 *((volatile uint8_t *)(0x42E01C28UL)) +#define bFM4_CANFD0_TXBTIE_TIE10 *((volatile uint8_t *)(0x42E01C28UL)) +#define bFM_CANFD0_TXBTIE_TIE11 *((volatile uint8_t *)(0x42E01C2CUL)) +#define bFM4_CANFD0_TXBTIE_TIE11 *((volatile uint8_t *)(0x42E01C2CUL)) +#define bFM_CANFD0_TXBTIE_TIE12 *((volatile uint8_t *)(0x42E01C30UL)) +#define bFM4_CANFD0_TXBTIE_TIE12 *((volatile uint8_t *)(0x42E01C30UL)) +#define bFM_CANFD0_TXBTIE_TIE13 *((volatile uint8_t *)(0x42E01C34UL)) +#define bFM4_CANFD0_TXBTIE_TIE13 *((volatile uint8_t *)(0x42E01C34UL)) +#define bFM_CANFD0_TXBTIE_TIE14 *((volatile uint8_t *)(0x42E01C38UL)) +#define bFM4_CANFD0_TXBTIE_TIE14 *((volatile uint8_t *)(0x42E01C38UL)) +#define bFM_CANFD0_TXBTIE_TIE15 *((volatile uint8_t *)(0x42E01C3CUL)) +#define bFM4_CANFD0_TXBTIE_TIE15 *((volatile uint8_t *)(0x42E01C3CUL)) +#define bFM_CANFD0_TXBTIE_TIE16 *((volatile uint8_t *)(0x42E01C40UL)) +#define bFM4_CANFD0_TXBTIE_TIE16 *((volatile uint8_t *)(0x42E01C40UL)) +#define bFM_CANFD0_TXBTIE_TIE17 *((volatile uint8_t *)(0x42E01C44UL)) +#define bFM4_CANFD0_TXBTIE_TIE17 *((volatile uint8_t *)(0x42E01C44UL)) +#define bFM_CANFD0_TXBTIE_TIE18 *((volatile uint8_t *)(0x42E01C48UL)) +#define bFM4_CANFD0_TXBTIE_TIE18 *((volatile uint8_t *)(0x42E01C48UL)) +#define bFM_CANFD0_TXBTIE_TIE19 *((volatile uint8_t *)(0x42E01C4CUL)) +#define bFM4_CANFD0_TXBTIE_TIE19 *((volatile uint8_t *)(0x42E01C4CUL)) +#define bFM_CANFD0_TXBTIE_TIE20 *((volatile uint8_t *)(0x42E01C50UL)) +#define bFM4_CANFD0_TXBTIE_TIE20 *((volatile uint8_t *)(0x42E01C50UL)) +#define bFM_CANFD0_TXBTIE_TIE21 *((volatile uint8_t *)(0x42E01C54UL)) +#define bFM4_CANFD0_TXBTIE_TIE21 *((volatile uint8_t *)(0x42E01C54UL)) +#define bFM_CANFD0_TXBTIE_TIE22 *((volatile uint8_t *)(0x42E01C58UL)) +#define bFM4_CANFD0_TXBTIE_TIE22 *((volatile uint8_t *)(0x42E01C58UL)) +#define bFM_CANFD0_TXBTIE_TIE23 *((volatile uint8_t *)(0x42E01C5CUL)) +#define bFM4_CANFD0_TXBTIE_TIE23 *((volatile uint8_t *)(0x42E01C5CUL)) +#define bFM_CANFD0_TXBTIE_TIE24 *((volatile uint8_t *)(0x42E01C60UL)) +#define bFM4_CANFD0_TXBTIE_TIE24 *((volatile uint8_t *)(0x42E01C60UL)) +#define bFM_CANFD0_TXBTIE_TIE25 *((volatile uint8_t *)(0x42E01C64UL)) +#define bFM4_CANFD0_TXBTIE_TIE25 *((volatile uint8_t *)(0x42E01C64UL)) +#define bFM_CANFD0_TXBTIE_TIE26 *((volatile uint8_t *)(0x42E01C68UL)) +#define bFM4_CANFD0_TXBTIE_TIE26 *((volatile uint8_t *)(0x42E01C68UL)) +#define bFM_CANFD0_TXBTIE_TIE27 *((volatile uint8_t *)(0x42E01C6CUL)) +#define bFM4_CANFD0_TXBTIE_TIE27 *((volatile uint8_t *)(0x42E01C6CUL)) +#define bFM_CANFD0_TXBTIE_TIE28 *((volatile uint8_t *)(0x42E01C70UL)) +#define bFM4_CANFD0_TXBTIE_TIE28 *((volatile uint8_t *)(0x42E01C70UL)) +#define bFM_CANFD0_TXBTIE_TIE29 *((volatile uint8_t *)(0x42E01C74UL)) +#define bFM4_CANFD0_TXBTIE_TIE29 *((volatile uint8_t *)(0x42E01C74UL)) +#define bFM_CANFD0_TXBTIE_TIE30 *((volatile uint8_t *)(0x42E01C78UL)) +#define bFM4_CANFD0_TXBTIE_TIE30 *((volatile uint8_t *)(0x42E01C78UL)) +#define bFM_CANFD0_TXBTIE_TIE31 *((volatile uint8_t *)(0x42E01C7CUL)) +#define bFM4_CANFD0_TXBTIE_TIE31 *((volatile uint8_t *)(0x42E01C7CUL)) + +#define bFM_CANFD0_TXBTO_TO0 *((volatile uint8_t *)(0x42E01B00UL)) +#define bFM4_CANFD0_TXBTO_TO0 *((volatile uint8_t *)(0x42E01B00UL)) +#define bFM_CANFD0_TXBTO_TO1 *((volatile uint8_t *)(0x42E01B04UL)) +#define bFM4_CANFD0_TXBTO_TO1 *((volatile uint8_t *)(0x42E01B04UL)) +#define bFM_CANFD0_TXBTO_TO2 *((volatile uint8_t *)(0x42E01B08UL)) +#define bFM4_CANFD0_TXBTO_TO2 *((volatile uint8_t *)(0x42E01B08UL)) +#define bFM_CANFD0_TXBTO_TO3 *((volatile uint8_t *)(0x42E01B0CUL)) +#define bFM4_CANFD0_TXBTO_TO3 *((volatile uint8_t *)(0x42E01B0CUL)) +#define bFM_CANFD0_TXBTO_TO4 *((volatile uint8_t *)(0x42E01B10UL)) +#define bFM4_CANFD0_TXBTO_TO4 *((volatile uint8_t *)(0x42E01B10UL)) +#define bFM_CANFD0_TXBTO_TO5 *((volatile uint8_t *)(0x42E01B14UL)) +#define bFM4_CANFD0_TXBTO_TO5 *((volatile uint8_t *)(0x42E01B14UL)) +#define bFM_CANFD0_TXBTO_TO6 *((volatile uint8_t *)(0x42E01B18UL)) +#define bFM4_CANFD0_TXBTO_TO6 *((volatile uint8_t *)(0x42E01B18UL)) +#define bFM_CANFD0_TXBTO_TO7 *((volatile uint8_t *)(0x42E01B1CUL)) +#define bFM4_CANFD0_TXBTO_TO7 *((volatile uint8_t *)(0x42E01B1CUL)) +#define bFM_CANFD0_TXBTO_TO8 *((volatile uint8_t *)(0x42E01B20UL)) +#define bFM4_CANFD0_TXBTO_TO8 *((volatile uint8_t *)(0x42E01B20UL)) +#define bFM_CANFD0_TXBTO_TO9 *((volatile uint8_t *)(0x42E01B24UL)) +#define bFM4_CANFD0_TXBTO_TO9 *((volatile uint8_t *)(0x42E01B24UL)) +#define bFM_CANFD0_TXBTO_TO10 *((volatile uint8_t *)(0x42E01B28UL)) +#define bFM4_CANFD0_TXBTO_TO10 *((volatile uint8_t *)(0x42E01B28UL)) +#define bFM_CANFD0_TXBTO_TO11 *((volatile uint8_t *)(0x42E01B2CUL)) +#define bFM4_CANFD0_TXBTO_TO11 *((volatile uint8_t *)(0x42E01B2CUL)) +#define bFM_CANFD0_TXBTO_TO12 *((volatile uint8_t *)(0x42E01B30UL)) +#define bFM4_CANFD0_TXBTO_TO12 *((volatile uint8_t *)(0x42E01B30UL)) +#define bFM_CANFD0_TXBTO_TO13 *((volatile uint8_t *)(0x42E01B34UL)) +#define bFM4_CANFD0_TXBTO_TO13 *((volatile uint8_t *)(0x42E01B34UL)) +#define bFM_CANFD0_TXBTO_TO14 *((volatile uint8_t *)(0x42E01B38UL)) +#define bFM4_CANFD0_TXBTO_TO14 *((volatile uint8_t *)(0x42E01B38UL)) +#define bFM_CANFD0_TXBTO_TO15 *((volatile uint8_t *)(0x42E01B3CUL)) +#define bFM4_CANFD0_TXBTO_TO15 *((volatile uint8_t *)(0x42E01B3CUL)) +#define bFM_CANFD0_TXBTO_TO16 *((volatile uint8_t *)(0x42E01B40UL)) +#define bFM4_CANFD0_TXBTO_TO16 *((volatile uint8_t *)(0x42E01B40UL)) +#define bFM_CANFD0_TXBTO_TO17 *((volatile uint8_t *)(0x42E01B44UL)) +#define bFM4_CANFD0_TXBTO_TO17 *((volatile uint8_t *)(0x42E01B44UL)) +#define bFM_CANFD0_TXBTO_TO18 *((volatile uint8_t *)(0x42E01B48UL)) +#define bFM4_CANFD0_TXBTO_TO18 *((volatile uint8_t *)(0x42E01B48UL)) +#define bFM_CANFD0_TXBTO_TO19 *((volatile uint8_t *)(0x42E01B4CUL)) +#define bFM4_CANFD0_TXBTO_TO19 *((volatile uint8_t *)(0x42E01B4CUL)) +#define bFM_CANFD0_TXBTO_TO20 *((volatile uint8_t *)(0x42E01B50UL)) +#define bFM4_CANFD0_TXBTO_TO20 *((volatile uint8_t *)(0x42E01B50UL)) +#define bFM_CANFD0_TXBTO_TO21 *((volatile uint8_t *)(0x42E01B54UL)) +#define bFM4_CANFD0_TXBTO_TO21 *((volatile uint8_t *)(0x42E01B54UL)) +#define bFM_CANFD0_TXBTO_TO22 *((volatile uint8_t *)(0x42E01B58UL)) +#define bFM4_CANFD0_TXBTO_TO22 *((volatile uint8_t *)(0x42E01B58UL)) +#define bFM_CANFD0_TXBTO_TO23 *((volatile uint8_t *)(0x42E01B5CUL)) +#define bFM4_CANFD0_TXBTO_TO23 *((volatile uint8_t *)(0x42E01B5CUL)) +#define bFM_CANFD0_TXBTO_TO24 *((volatile uint8_t *)(0x42E01B60UL)) +#define bFM4_CANFD0_TXBTO_TO24 *((volatile uint8_t *)(0x42E01B60UL)) +#define bFM_CANFD0_TXBTO_TO25 *((volatile uint8_t *)(0x42E01B64UL)) +#define bFM4_CANFD0_TXBTO_TO25 *((volatile uint8_t *)(0x42E01B64UL)) +#define bFM_CANFD0_TXBTO_TO26 *((volatile uint8_t *)(0x42E01B68UL)) +#define bFM4_CANFD0_TXBTO_TO26 *((volatile uint8_t *)(0x42E01B68UL)) +#define bFM_CANFD0_TXBTO_TO27 *((volatile uint8_t *)(0x42E01B6CUL)) +#define bFM4_CANFD0_TXBTO_TO27 *((volatile uint8_t *)(0x42E01B6CUL)) +#define bFM_CANFD0_TXBTO_TO28 *((volatile uint8_t *)(0x42E01B70UL)) +#define bFM4_CANFD0_TXBTO_TO28 *((volatile uint8_t *)(0x42E01B70UL)) +#define bFM_CANFD0_TXBTO_TO29 *((volatile uint8_t *)(0x42E01B74UL)) +#define bFM4_CANFD0_TXBTO_TO29 *((volatile uint8_t *)(0x42E01B74UL)) +#define bFM_CANFD0_TXBTO_TO30 *((volatile uint8_t *)(0x42E01B78UL)) +#define bFM4_CANFD0_TXBTO_TO30 *((volatile uint8_t *)(0x42E01B78UL)) +#define bFM_CANFD0_TXBTO_TO31 *((volatile uint8_t *)(0x42E01B7CUL)) +#define bFM4_CANFD0_TXBTO_TO31 *((volatile uint8_t *)(0x42E01B7CUL)) + +#define bFM_CANFD0_TXFQS_TFQF *((volatile uint8_t *)(0x42E018D4UL)) +#define bFM4_CANFD0_TXFQS_TFQF *((volatile uint8_t *)(0x42E018D4UL)) + +#define bFM_CANFD0_TXFS_EFF *((volatile uint8_t *)(0x42E01EE0UL)) +#define bFM4_CANFD0_TXFS_EFF *((volatile uint8_t *)(0x42E01EE0UL)) +#define bFM_CANFD0_TXFS_TEFL *((volatile uint8_t *)(0x42E01EE4UL)) +#define bFM4_CANFD0_TXFS_TEFL *((volatile uint8_t *)(0x42E01EE4UL)) + + +/******************************************************************************* +* CANPRES Registers CANPRES +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* CLK_GATING Registers CLK_GATING +* Bitband Section +*******************************************************************************/ +#define bFM_CLK_GATING_CKEN0_MFSCK0 *((volatile uint8_t *)(0x42782000UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK0 *((volatile uint8_t *)(0x42782000UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK1 *((volatile uint8_t *)(0x42782004UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK1 *((volatile uint8_t *)(0x42782004UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK2 *((volatile uint8_t *)(0x42782008UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK2 *((volatile uint8_t *)(0x42782008UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK3 *((volatile uint8_t *)(0x4278200CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK3 *((volatile uint8_t *)(0x4278200CUL)) +#define bFM_CLK_GATING_CKEN0_MFSCK4 *((volatile uint8_t *)(0x42782010UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK4 *((volatile uint8_t *)(0x42782010UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK5 *((volatile uint8_t *)(0x42782014UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK5 *((volatile uint8_t *)(0x42782014UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK6 *((volatile uint8_t *)(0x42782018UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK6 *((volatile uint8_t *)(0x42782018UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK7 *((volatile uint8_t *)(0x4278201CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK7 *((volatile uint8_t *)(0x4278201CUL)) +#define bFM_CLK_GATING_CKEN0_MFSCK8 *((volatile uint8_t *)(0x42782020UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK8 *((volatile uint8_t *)(0x42782020UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK9 *((volatile uint8_t *)(0x42782024UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK9 *((volatile uint8_t *)(0x42782024UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK10 *((volatile uint8_t *)(0x42782028UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK10 *((volatile uint8_t *)(0x42782028UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK11 *((volatile uint8_t *)(0x4278202CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK11 *((volatile uint8_t *)(0x4278202CUL)) +#define bFM_CLK_GATING_CKEN0_MFSCK12 *((volatile uint8_t *)(0x42782030UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK12 *((volatile uint8_t *)(0x42782030UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK13 *((volatile uint8_t *)(0x42782034UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK13 *((volatile uint8_t *)(0x42782034UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK14 *((volatile uint8_t *)(0x42782038UL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK14 *((volatile uint8_t *)(0x42782038UL)) +#define bFM_CLK_GATING_CKEN0_MFSCK15 *((volatile uint8_t *)(0x4278203CUL)) +#define bFM4_CLK_GATING_CKEN0_MFSCK15 *((volatile uint8_t *)(0x4278203CUL)) +#define bFM_CLK_GATING_CKEN0_ADCCK0 *((volatile uint8_t *)(0x42782040UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK0 *((volatile uint8_t *)(0x42782040UL)) +#define bFM_CLK_GATING_CKEN0_ADCCK1 *((volatile uint8_t *)(0x42782044UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK1 *((volatile uint8_t *)(0x42782044UL)) +#define bFM_CLK_GATING_CKEN0_ADCCK2 *((volatile uint8_t *)(0x42782048UL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK2 *((volatile uint8_t *)(0x42782048UL)) +#define bFM_CLK_GATING_CKEN0_ADCCK3 *((volatile uint8_t *)(0x4278204CUL)) +#define bFM4_CLK_GATING_CKEN0_ADCCK3 *((volatile uint8_t *)(0x4278204CUL)) +#define bFM_CLK_GATING_CKEN0_DMACK *((volatile uint8_t *)(0x42782060UL)) +#define bFM4_CLK_GATING_CKEN0_DMACK *((volatile uint8_t *)(0x42782060UL)) +#define bFM_CLK_GATING_CKEN0_EXBCK *((volatile uint8_t *)(0x42782068UL)) +#define bFM4_CLK_GATING_CKEN0_EXBCK *((volatile uint8_t *)(0x42782068UL)) +#define bFM_CLK_GATING_CKEN0_GIOCK *((volatile uint8_t *)(0x42782070UL)) +#define bFM4_CLK_GATING_CKEN0_GIOCK *((volatile uint8_t *)(0x42782070UL)) + +#define bFM_CLK_GATING_CKEN1_BTMCK0 *((volatile uint8_t *)(0x42782200UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK0 *((volatile uint8_t *)(0x42782200UL)) +#define bFM_CLK_GATING_CKEN1_BTMCK1 *((volatile uint8_t *)(0x42782204UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK1 *((volatile uint8_t *)(0x42782204UL)) +#define bFM_CLK_GATING_CKEN1_BTMCK2 *((volatile uint8_t *)(0x42782208UL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK2 *((volatile uint8_t *)(0x42782208UL)) +#define bFM_CLK_GATING_CKEN1_BTMCK3 *((volatile uint8_t *)(0x4278220CUL)) +#define bFM4_CLK_GATING_CKEN1_BTMCK3 *((volatile uint8_t *)(0x4278220CUL)) +#define bFM_CLK_GATING_CKEN1_MFTCK0 *((volatile uint8_t *)(0x42782220UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK0 *((volatile uint8_t *)(0x42782220UL)) +#define bFM_CLK_GATING_CKEN1_MFTCK1 *((volatile uint8_t *)(0x42782224UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK1 *((volatile uint8_t *)(0x42782224UL)) +#define bFM_CLK_GATING_CKEN1_MFTCK2 *((volatile uint8_t *)(0x42782228UL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK2 *((volatile uint8_t *)(0x42782228UL)) +#define bFM_CLK_GATING_CKEN1_MFTCK3 *((volatile uint8_t *)(0x4278222CUL)) +#define bFM4_CLK_GATING_CKEN1_MFTCK3 *((volatile uint8_t *)(0x4278222CUL)) +#define bFM_CLK_GATING_CKEN1_QDUCK0 *((volatile uint8_t *)(0x42782240UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK0 *((volatile uint8_t *)(0x42782240UL)) +#define bFM_CLK_GATING_CKEN1_QDUCK1 *((volatile uint8_t *)(0x42782244UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK1 *((volatile uint8_t *)(0x42782244UL)) +#define bFM_CLK_GATING_CKEN1_QDUCK2 *((volatile uint8_t *)(0x42782248UL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK2 *((volatile uint8_t *)(0x42782248UL)) +#define bFM_CLK_GATING_CKEN1_QDUCK3 *((volatile uint8_t *)(0x4278224CUL)) +#define bFM4_CLK_GATING_CKEN1_QDUCK3 *((volatile uint8_t *)(0x4278224CUL)) + +#define bFM_CLK_GATING_CKEN2_USBCK0 *((volatile uint8_t *)(0x42782400UL)) +#define bFM4_CLK_GATING_CKEN2_USBCK0 *((volatile uint8_t *)(0x42782400UL)) +#define bFM_CLK_GATING_CKEN2_USBCK1 *((volatile uint8_t *)(0x42782404UL)) +#define bFM4_CLK_GATING_CKEN2_USBCK1 *((volatile uint8_t *)(0x42782404UL)) +#define bFM_CLK_GATING_CKEN2_CANCK0 *((volatile uint8_t *)(0x42782410UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK0 *((volatile uint8_t *)(0x42782410UL)) +#define bFM_CLK_GATING_CKEN2_CANCK1 *((volatile uint8_t *)(0x42782414UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK1 *((volatile uint8_t *)(0x42782414UL)) +#define bFM_CLK_GATING_CKEN2_CANCK2 *((volatile uint8_t *)(0x42782418UL)) +#define bFM4_CLK_GATING_CKEN2_CANCK2 *((volatile uint8_t *)(0x42782418UL)) +#define bFM_CLK_GATING_CKEN2_SDCCK *((volatile uint8_t *)(0x42782420UL)) +#define bFM4_CLK_GATING_CKEN2_SDCCK *((volatile uint8_t *)(0x42782420UL)) +#define bFM_CLK_GATING_CKEN2_I2SCK0 *((volatile uint8_t *)(0x42782440UL)) +#define bFM4_CLK_GATING_CKEN2_I2SCK0 *((volatile uint8_t *)(0x42782440UL)) +#define bFM_CLK_GATING_CKEN2_I2SCK1 *((volatile uint8_t *)(0x42782444UL)) +#define bFM4_CLK_GATING_CKEN2_I2SCK1 *((volatile uint8_t *)(0x42782444UL)) +#define bFM_CLK_GATING_CKEN2_PCRCCK *((volatile uint8_t *)(0x42782450UL)) +#define bFM4_CLK_GATING_CKEN2_PCRCCK *((volatile uint8_t *)(0x42782450UL)) +#define bFM_CLK_GATING_CKEN2_CECCK0 *((volatile uint8_t *)(0x42782460UL)) +#define bFM4_CLK_GATING_CKEN2_CECCK0 *((volatile uint8_t *)(0x42782460UL)) +#define bFM_CLK_GATING_CKEN2_CECCK1 *((volatile uint8_t *)(0x42782464UL)) +#define bFM4_CLK_GATING_CKEN2_CECCK1 *((volatile uint8_t *)(0x42782464UL)) +#define bFM_CLK_GATING_CKEN2_HSSPICK *((volatile uint8_t *)(0x42782470UL)) +#define bFM4_CLK_GATING_CKEN2_HSSPICK *((volatile uint8_t *)(0x42782470UL)) + +#define bFM_CLK_GATING_MRST0_MFSRST0 *((volatile uint8_t *)(0x42782080UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST0 *((volatile uint8_t *)(0x42782080UL)) +#define bFM_CLK_GATING_MRST0_MFSRST1 *((volatile uint8_t *)(0x42782084UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST1 *((volatile uint8_t *)(0x42782084UL)) +#define bFM_CLK_GATING_MRST0_MFSRST2 *((volatile uint8_t *)(0x42782088UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST2 *((volatile uint8_t *)(0x42782088UL)) +#define bFM_CLK_GATING_MRST0_MFSRST3 *((volatile uint8_t *)(0x4278208CUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST3 *((volatile uint8_t *)(0x4278208CUL)) +#define bFM_CLK_GATING_MRST0_MFSRST4 *((volatile uint8_t *)(0x42782090UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST4 *((volatile uint8_t *)(0x42782090UL)) +#define bFM_CLK_GATING_MRST0_MFSRST5 *((volatile uint8_t *)(0x42782094UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST5 *((volatile uint8_t *)(0x42782094UL)) +#define bFM_CLK_GATING_MRST0_MFSRST6 *((volatile uint8_t *)(0x42782098UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST6 *((volatile uint8_t *)(0x42782098UL)) +#define bFM_CLK_GATING_MRST0_MFSRST7 *((volatile uint8_t *)(0x4278209CUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST7 *((volatile uint8_t *)(0x4278209CUL)) +#define bFM_CLK_GATING_MRST0_MFSRST8 *((volatile uint8_t *)(0x427820A0UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST8 *((volatile uint8_t *)(0x427820A0UL)) +#define bFM_CLK_GATING_MRST0_MFSRST9 *((volatile uint8_t *)(0x427820A4UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST9 *((volatile uint8_t *)(0x427820A4UL)) +#define bFM_CLK_GATING_MRST0_MFSRST10 *((volatile uint8_t *)(0x427820A8UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST10 *((volatile uint8_t *)(0x427820A8UL)) +#define bFM_CLK_GATING_MRST0_MFSRST11 *((volatile uint8_t *)(0x427820ACUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST11 *((volatile uint8_t *)(0x427820ACUL)) +#define bFM_CLK_GATING_MRST0_MFSRST12 *((volatile uint8_t *)(0x427820B0UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST12 *((volatile uint8_t *)(0x427820B0UL)) +#define bFM_CLK_GATING_MRST0_MFSRST13 *((volatile uint8_t *)(0x427820B4UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST13 *((volatile uint8_t *)(0x427820B4UL)) +#define bFM_CLK_GATING_MRST0_MFSRST14 *((volatile uint8_t *)(0x427820B8UL)) +#define bFM4_CLK_GATING_MRST0_MFSRST14 *((volatile uint8_t *)(0x427820B8UL)) +#define bFM_CLK_GATING_MRST0_MFSRST15 *((volatile uint8_t *)(0x427820BCUL)) +#define bFM4_CLK_GATING_MRST0_MFSRST15 *((volatile uint8_t *)(0x427820BCUL)) +#define bFM_CLK_GATING_MRST0_ADCRST0 *((volatile uint8_t *)(0x427820C0UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST0 *((volatile uint8_t *)(0x427820C0UL)) +#define bFM_CLK_GATING_MRST0_ADCRST1 *((volatile uint8_t *)(0x427820C4UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST1 *((volatile uint8_t *)(0x427820C4UL)) +#define bFM_CLK_GATING_MRST0_ADCRST2 *((volatile uint8_t *)(0x427820C8UL)) +#define bFM4_CLK_GATING_MRST0_ADCRST2 *((volatile uint8_t *)(0x427820C8UL)) +#define bFM_CLK_GATING_MRST0_ADCRST3 *((volatile uint8_t *)(0x427820CCUL)) +#define bFM4_CLK_GATING_MRST0_ADCRST3 *((volatile uint8_t *)(0x427820CCUL)) +#define bFM_CLK_GATING_MRST0_DMARST *((volatile uint8_t *)(0x427820E0UL)) +#define bFM4_CLK_GATING_MRST0_DMARST *((volatile uint8_t *)(0x427820E0UL)) +#define bFM_CLK_GATING_MRST0_EXBRST *((volatile uint8_t *)(0x427820E8UL)) +#define bFM4_CLK_GATING_MRST0_EXBRST *((volatile uint8_t *)(0x427820E8UL)) + +#define bFM_CLK_GATING_MRST1_BTMRST0 *((volatile uint8_t *)(0x42782280UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST0 *((volatile uint8_t *)(0x42782280UL)) +#define bFM_CLK_GATING_MRST1_BTMRST1 *((volatile uint8_t *)(0x42782284UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST1 *((volatile uint8_t *)(0x42782284UL)) +#define bFM_CLK_GATING_MRST1_BTMRST2 *((volatile uint8_t *)(0x42782288UL)) +#define bFM4_CLK_GATING_MRST1_BTMRST2 *((volatile uint8_t *)(0x42782288UL)) +#define bFM_CLK_GATING_MRST1_BTMRST3 *((volatile uint8_t *)(0x4278228CUL)) +#define bFM4_CLK_GATING_MRST1_BTMRST3 *((volatile uint8_t *)(0x4278228CUL)) +#define bFM_CLK_GATING_MRST1_MFTRST0 *((volatile uint8_t *)(0x427822A0UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST0 *((volatile uint8_t *)(0x427822A0UL)) +#define bFM_CLK_GATING_MRST1_MFTRST1 *((volatile uint8_t *)(0x427822A4UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST1 *((volatile uint8_t *)(0x427822A4UL)) +#define bFM_CLK_GATING_MRST1_MFTRST2 *((volatile uint8_t *)(0x427822A8UL)) +#define bFM4_CLK_GATING_MRST1_MFTRST2 *((volatile uint8_t *)(0x427822A8UL)) +#define bFM_CLK_GATING_MRST1_MFTRST3 *((volatile uint8_t *)(0x427822ACUL)) +#define bFM4_CLK_GATING_MRST1_MFTRST3 *((volatile uint8_t *)(0x427822ACUL)) +#define bFM_CLK_GATING_MRST1_QDURST0 *((volatile uint8_t *)(0x427822C0UL)) +#define bFM4_CLK_GATING_MRST1_QDURST0 *((volatile uint8_t *)(0x427822C0UL)) +#define bFM_CLK_GATING_MRST1_QDURST1 *((volatile uint8_t *)(0x427822C4UL)) +#define bFM4_CLK_GATING_MRST1_QDURST1 *((volatile uint8_t *)(0x427822C4UL)) +#define bFM_CLK_GATING_MRST1_QDURST2 *((volatile uint8_t *)(0x427822C8UL)) +#define bFM4_CLK_GATING_MRST1_QDURST2 *((volatile uint8_t *)(0x427822C8UL)) +#define bFM_CLK_GATING_MRST1_QDURST3 *((volatile uint8_t *)(0x427822CCUL)) +#define bFM4_CLK_GATING_MRST1_QDURST3 *((volatile uint8_t *)(0x427822CCUL)) + +#define bFM_CLK_GATING_MRST2_USBRST0 *((volatile uint8_t *)(0x42782480UL)) +#define bFM4_CLK_GATING_MRST2_USBRST0 *((volatile uint8_t *)(0x42782480UL)) +#define bFM_CLK_GATING_MRST2_USBRST1 *((volatile uint8_t *)(0x42782484UL)) +#define bFM4_CLK_GATING_MRST2_USBRST1 *((volatile uint8_t *)(0x42782484UL)) +#define bFM_CLK_GATING_MRST2_CANRST0 *((volatile uint8_t *)(0x42782490UL)) +#define bFM4_CLK_GATING_MRST2_CANRST0 *((volatile uint8_t *)(0x42782490UL)) +#define bFM_CLK_GATING_MRST2_CANRST1 *((volatile uint8_t *)(0x42782494UL)) +#define bFM4_CLK_GATING_MRST2_CANRST1 *((volatile uint8_t *)(0x42782494UL)) +#define bFM_CLK_GATING_MRST2_CANRST2 *((volatile uint8_t *)(0x42782498UL)) +#define bFM4_CLK_GATING_MRST2_CANRST2 *((volatile uint8_t *)(0x42782498UL)) +#define bFM_CLK_GATING_MRST2_SDCRST *((volatile uint8_t *)(0x427824A0UL)) +#define bFM4_CLK_GATING_MRST2_SDCRST *((volatile uint8_t *)(0x427824A0UL)) +#define bFM_CLK_GATING_MRST2_I2SRST0 *((volatile uint8_t *)(0x427824C0UL)) +#define bFM4_CLK_GATING_MRST2_I2SRST0 *((volatile uint8_t *)(0x427824C0UL)) +#define bFM_CLK_GATING_MRST2_I2SRST1 *((volatile uint8_t *)(0x427824C4UL)) +#define bFM4_CLK_GATING_MRST2_I2SRST1 *((volatile uint8_t *)(0x427824C4UL)) +#define bFM_CLK_GATING_MRST2_PCRCRST *((volatile uint8_t *)(0x427824D0UL)) +#define bFM4_CLK_GATING_MRST2_PCRCRST *((volatile uint8_t *)(0x427824D0UL)) +#define bFM_CLK_GATING_MRST2_CECRST0 *((volatile uint8_t *)(0x427824E0UL)) +#define bFM4_CLK_GATING_MRST2_CECRST0 *((volatile uint8_t *)(0x427824E0UL)) +#define bFM_CLK_GATING_MRST2_CECRST1 *((volatile uint8_t *)(0x427824E4UL)) +#define bFM4_CLK_GATING_MRST2_CECRST1 *((volatile uint8_t *)(0x427824E4UL)) +#define bFM_CLK_GATING_MRST2_HSSPIRST *((volatile uint8_t *)(0x427824F0UL)) +#define bFM4_CLK_GATING_MRST2_HSSPIRST *((volatile uint8_t *)(0x427824F0UL)) + + +/******************************************************************************* +* CRC Registers CRC +* Bitband Section +*******************************************************************************/ +#define bFM_CRC_CRCCR_INIT *((volatile uint8_t *)(0x42720000UL)) +#define bFM4_CRC_CRCCR_INIT *((volatile uint8_t *)(0x42720000UL)) +#define bFM_CRC_CRCCR_CRC32 *((volatile uint8_t *)(0x42720004UL)) +#define bFM4_CRC_CRCCR_CRC32 *((volatile uint8_t *)(0x42720004UL)) +#define bFM_CRC_CRCCR_LTLEND *((volatile uint8_t *)(0x42720008UL)) +#define bFM4_CRC_CRCCR_LTLEND *((volatile uint8_t *)(0x42720008UL)) +#define bFM_CRC_CRCCR_LSBFST *((volatile uint8_t *)(0x4272000CUL)) +#define bFM4_CRC_CRCCR_LSBFST *((volatile uint8_t *)(0x4272000CUL)) +#define bFM_CRC_CRCCR_CRCLTE *((volatile uint8_t *)(0x42720010UL)) +#define bFM4_CRC_CRCCR_CRCLTE *((volatile uint8_t *)(0x42720010UL)) +#define bFM_CRC_CRCCR_CRCLSF *((volatile uint8_t *)(0x42720014UL)) +#define bFM4_CRC_CRCCR_CRCLSF *((volatile uint8_t *)(0x42720014UL)) +#define bFM_CRC_CRCCR_FXOR *((volatile uint8_t *)(0x42720018UL)) +#define bFM4_CRC_CRCCR_FXOR *((volatile uint8_t *)(0x42720018UL)) + + +/******************************************************************************* +* CRG Registers CRG +* Bitband Section +*******************************************************************************/ +#define bFM_CRG_APBC1_PSR_APBC1RST *((volatile uint32_t*)(0x42200310UL)) +#define bFM4_CRG_APBC1_PSR_APBC1RST *((volatile uint32_t*)(0x42200310UL)) +#define bFM_CRG_APBC1_PSR_APBC1EN *((volatile uint32_t*)(0x4220031CUL)) +#define bFM4_CRG_APBC1_PSR_APBC1EN *((volatile uint32_t*)(0x4220031CUL)) + +#define bFM_CRG_APBC2_PSR_APBC2RST *((volatile uint32_t*)(0x42200390UL)) +#define bFM4_CRG_APBC2_PSR_APBC2RST *((volatile uint32_t*)(0x42200390UL)) +#define bFM_CRG_APBC2_PSR_APBC2EN *((volatile uint32_t*)(0x4220039CUL)) +#define bFM4_CRG_APBC2_PSR_APBC2EN *((volatile uint32_t*)(0x4220039CUL)) + +#define bFM_CRG_CSV_CTL_MCSVE *((volatile uint32_t*)(0x42200800UL)) +#define bFM4_CRG_CSV_CTL_MCSVE *((volatile uint32_t*)(0x42200800UL)) +#define bFM_CRG_CSV_CTL_SCSVE *((volatile uint32_t*)(0x42200804UL)) +#define bFM4_CRG_CSV_CTL_SCSVE *((volatile uint32_t*)(0x42200804UL)) +#define bFM_CRG_CSV_CTL_FCSDE *((volatile uint32_t*)(0x42200820UL)) +#define bFM4_CRG_CSV_CTL_FCSDE *((volatile uint32_t*)(0x42200820UL)) +#define bFM_CRG_CSV_CTL_FCSRE *((volatile uint32_t*)(0x42200824UL)) +#define bFM4_CRG_CSV_CTL_FCSRE *((volatile uint32_t*)(0x42200824UL)) + +#define bFM_CRG_CSV_STR_MCMF *((volatile uint32_t*)(0x42200880UL)) +#define bFM4_CRG_CSV_STR_MCMF *((volatile uint32_t*)(0x42200880UL)) +#define bFM_CRG_CSV_STR_SCMF *((volatile uint32_t*)(0x42200884UL)) +#define bFM4_CRG_CSV_STR_SCMF *((volatile uint32_t*)(0x42200884UL)) + +#define bFM_CRG_DBWDT_CTL_DPSWBE *((volatile uint32_t*)(0x42200A94UL)) +#define bFM4_CRG_DBWDT_CTL_DPSWBE *((volatile uint32_t*)(0x42200A94UL)) +#define bFM_CRG_DBWDT_CTL_DPHWBE *((volatile uint32_t*)(0x42200A9CUL)) +#define bFM4_CRG_DBWDT_CTL_DPHWBE *((volatile uint32_t*)(0x42200A9CUL)) + +#define bFM_CRG_INT_CLR_MCSC *((volatile uint32_t*)(0x42200D00UL)) +#define bFM4_CRG_INT_CLR_MCSC *((volatile uint32_t*)(0x42200D00UL)) +#define bFM_CRG_INT_CLR_SCSC *((volatile uint32_t*)(0x42200D04UL)) +#define bFM4_CRG_INT_CLR_SCSC *((volatile uint32_t*)(0x42200D04UL)) +#define bFM_CRG_INT_CLR_PCSC *((volatile uint32_t*)(0x42200D08UL)) +#define bFM4_CRG_INT_CLR_PCSC *((volatile uint32_t*)(0x42200D08UL)) +#define bFM_CRG_INT_CLR_FCSC *((volatile uint32_t*)(0x42200D14UL)) +#define bFM4_CRG_INT_CLR_FCSC *((volatile uint32_t*)(0x42200D14UL)) + +#define bFM_CRG_INT_ENR_MCSE *((volatile uint32_t*)(0x42200C00UL)) +#define bFM4_CRG_INT_ENR_MCSE *((volatile uint32_t*)(0x42200C00UL)) +#define bFM_CRG_INT_ENR_SCSE *((volatile uint32_t*)(0x42200C04UL)) +#define bFM4_CRG_INT_ENR_SCSE *((volatile uint32_t*)(0x42200C04UL)) +#define bFM_CRG_INT_ENR_PCSE *((volatile uint32_t*)(0x42200C08UL)) +#define bFM4_CRG_INT_ENR_PCSE *((volatile uint32_t*)(0x42200C08UL)) +#define bFM_CRG_INT_ENR_FCSE *((volatile uint32_t*)(0x42200C14UL)) +#define bFM4_CRG_INT_ENR_FCSE *((volatile uint32_t*)(0x42200C14UL)) + +#define bFM_CRG_INT_STR_MCSI *((volatile uint32_t*)(0x42200C80UL)) +#define bFM4_CRG_INT_STR_MCSI *((volatile uint32_t*)(0x42200C80UL)) +#define bFM_CRG_INT_STR_SCSI *((volatile uint32_t*)(0x42200C84UL)) +#define bFM4_CRG_INT_STR_SCSI *((volatile uint32_t*)(0x42200C84UL)) +#define bFM_CRG_INT_STR_PCSI *((volatile uint32_t*)(0x42200C88UL)) +#define bFM4_CRG_INT_STR_PCSI *((volatile uint32_t*)(0x42200C88UL)) +#define bFM_CRG_INT_STR_FCSI *((volatile uint32_t*)(0x42200C94UL)) +#define bFM4_CRG_INT_STR_FCSI *((volatile uint32_t*)(0x42200C94UL)) + +#define bFM_CRG_PLLCG_CTL_PLLCGEN *((volatile uint32_t*)(0x42200E80UL)) +#define bFM4_CRG_PLLCG_CTL_PLLCGEN *((volatile uint32_t*)(0x42200E80UL)) +#define bFM_CRG_PLLCG_CTL_PLLCGSTR *((volatile uint32_t*)(0x42200E84UL)) +#define bFM4_CRG_PLLCG_CTL_PLLCGSTR *((volatile uint32_t*)(0x42200E84UL)) + +#define bFM_CRG_PSW_TMR_PINC *((volatile uint32_t*)(0x42200690UL)) +#define bFM4_CRG_PSW_TMR_PINC *((volatile uint32_t*)(0x42200690UL)) + +#define bFM_CRG_RST_STR_PONR *((volatile uint32_t*)(0x42200180UL)) +#define bFM4_CRG_RST_STR_PONR *((volatile uint32_t*)(0x42200180UL)) +#define bFM_CRG_RST_STR_INITX *((volatile uint32_t*)(0x42200184UL)) +#define bFM4_CRG_RST_STR_INITX *((volatile uint32_t*)(0x42200184UL)) +#define bFM_CRG_RST_STR_SWDT *((volatile uint32_t*)(0x42200190UL)) +#define bFM4_CRG_RST_STR_SWDT *((volatile uint32_t*)(0x42200190UL)) +#define bFM_CRG_RST_STR_HWDT *((volatile uint32_t*)(0x42200194UL)) +#define bFM4_CRG_RST_STR_HWDT *((volatile uint32_t*)(0x42200194UL)) +#define bFM_CRG_RST_STR_CSVR *((volatile uint32_t*)(0x42200198UL)) +#define bFM4_CRG_RST_STR_CSVR *((volatile uint32_t*)(0x42200198UL)) +#define bFM_CRG_RST_STR_FCSR *((volatile uint32_t*)(0x4220019CUL)) +#define bFM4_CRG_RST_STR_FCSR *((volatile uint32_t*)(0x4220019CUL)) +#define bFM_CRG_RST_STR_SRST *((volatile uint32_t*)(0x422001A0UL)) +#define bFM4_CRG_RST_STR_SRST *((volatile uint32_t*)(0x422001A0UL)) + +#define bFM_CRG_SCM_CTL_MOSCE *((volatile uint32_t*)(0x42200004UL)) +#define bFM4_CRG_SCM_CTL_MOSCE *((volatile uint32_t*)(0x42200004UL)) +#define bFM_CRG_SCM_CTL_SOSCE *((volatile uint32_t*)(0x4220000CUL)) +#define bFM4_CRG_SCM_CTL_SOSCE *((volatile uint32_t*)(0x4220000CUL)) +#define bFM_CRG_SCM_CTL_PLLE *((volatile uint32_t*)(0x42200010UL)) +#define bFM4_CRG_SCM_CTL_PLLE *((volatile uint32_t*)(0x42200010UL)) + +#define bFM_CRG_SCM_STR_MORDY *((volatile uint32_t*)(0x42200084UL)) +#define bFM4_CRG_SCM_STR_MORDY *((volatile uint32_t*)(0x42200084UL)) +#define bFM_CRG_SCM_STR_SORDY *((volatile uint32_t*)(0x4220008CUL)) +#define bFM4_CRG_SCM_STR_SORDY *((volatile uint32_t*)(0x4220008CUL)) +#define bFM_CRG_SCM_STR_PLRDY *((volatile uint32_t*)(0x42200090UL)) +#define bFM4_CRG_SCM_STR_PLRDY *((volatile uint32_t*)(0x42200090UL)) + +#define bFM_CRG_STB_CTL_DSTM *((volatile uint32_t*)(0x42200108UL)) +#define bFM4_CRG_STB_CTL_DSTM *((volatile uint32_t*)(0x42200108UL)) +#define bFM_CRG_STB_CTL_SPL *((volatile uint32_t*)(0x42200110UL)) +#define bFM4_CRG_STB_CTL_SPL *((volatile uint32_t*)(0x42200110UL)) + + +/******************************************************************************* +* CRTRIM Registers CRTRIM +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* DAC Registers DAC0 +* Bitband Section +*******************************************************************************/ +#define bFM_DAC0_DACR_DAE *((volatile uint8_t *)(0x42660000UL)) +#define bFM4_DAC0_DACR_DAE *((volatile uint8_t *)(0x42660000UL)) +#define bFM_DAC0_DACR_DRDY *((volatile uint8_t *)(0x42660004UL)) +#define bFM4_DAC0_DACR_DRDY *((volatile uint8_t *)(0x42660004UL)) +#define bFM_DAC0_DACR_DAC10 *((volatile uint8_t *)(0x42660010UL)) +#define bFM4_DAC0_DACR_DAC10 *((volatile uint8_t *)(0x42660010UL)) +#define bFM_DAC0_DACR_DDAS *((volatile uint8_t *)(0x42660014UL)) +#define bFM4_DAC0_DACR_DDAS *((volatile uint8_t *)(0x42660014UL)) + + +/******************************************************************************* +* DAC Registers DAC1 +* Bitband Section +*******************************************************************************/ +#define bFM_DAC1_DACR_DAE *((volatile uint8_t *)(0x42660100UL)) +#define bFM4_DAC1_DACR_DAE *((volatile uint8_t *)(0x42660100UL)) +#define bFM_DAC1_DACR_DRDY *((volatile uint8_t *)(0x42660104UL)) +#define bFM4_DAC1_DACR_DRDY *((volatile uint8_t *)(0x42660104UL)) +#define bFM_DAC1_DACR_DAC10 *((volatile uint8_t *)(0x42660110UL)) +#define bFM4_DAC1_DACR_DAC10 *((volatile uint8_t *)(0x42660110UL)) +#define bFM_DAC1_DACR_DDAS *((volatile uint8_t *)(0x42660114UL)) +#define bFM4_DAC1_DACR_DDAS *((volatile uint8_t *)(0x42660114UL)) + + +/******************************************************************************* +* DMAC Registers DMAC +* Bitband Section +*******************************************************************************/ +#define bFM_DMAC_DMACA0_ST *((volatile uint8_t *)(0x42C00274UL)) +#define bFM4_DMAC_DMACA0_ST *((volatile uint8_t *)(0x42C00274UL)) +#define bFM_DMAC_DMACA0_PB *((volatile uint8_t *)(0x42C00278UL)) +#define bFM4_DMAC_DMACA0_PB *((volatile uint8_t *)(0x42C00278UL)) +#define bFM_DMAC_DMACA0_EB *((volatile uint8_t *)(0x42C0027CUL)) +#define bFM4_DMAC_DMACA0_EB *((volatile uint8_t *)(0x42C0027CUL)) + +#define bFM_DMAC_DMACA1_ST *((volatile uint8_t *)(0x42C00474UL)) +#define bFM4_DMAC_DMACA1_ST *((volatile uint8_t *)(0x42C00474UL)) +#define bFM_DMAC_DMACA1_PB *((volatile uint8_t *)(0x42C00478UL)) +#define bFM4_DMAC_DMACA1_PB *((volatile uint8_t *)(0x42C00478UL)) +#define bFM_DMAC_DMACA1_EB *((volatile uint8_t *)(0x42C0047CUL)) +#define bFM4_DMAC_DMACA1_EB *((volatile uint8_t *)(0x42C0047CUL)) + +#define bFM_DMAC_DMACA2_ST *((volatile uint8_t *)(0x42C00674UL)) +#define bFM4_DMAC_DMACA2_ST *((volatile uint8_t *)(0x42C00674UL)) +#define bFM_DMAC_DMACA2_PB *((volatile uint8_t *)(0x42C00678UL)) +#define bFM4_DMAC_DMACA2_PB *((volatile uint8_t *)(0x42C00678UL)) +#define bFM_DMAC_DMACA2_EB *((volatile uint8_t *)(0x42C0067CUL)) +#define bFM4_DMAC_DMACA2_EB *((volatile uint8_t *)(0x42C0067CUL)) + +#define bFM_DMAC_DMACA3_ST *((volatile uint8_t *)(0x42C00874UL)) +#define bFM4_DMAC_DMACA3_ST *((volatile uint8_t *)(0x42C00874UL)) +#define bFM_DMAC_DMACA3_PB *((volatile uint8_t *)(0x42C00878UL)) +#define bFM4_DMAC_DMACA3_PB *((volatile uint8_t *)(0x42C00878UL)) +#define bFM_DMAC_DMACA3_EB *((volatile uint8_t *)(0x42C0087CUL)) +#define bFM4_DMAC_DMACA3_EB *((volatile uint8_t *)(0x42C0087CUL)) + +#define bFM_DMAC_DMACA4_ST *((volatile uint8_t *)(0x42C00A74UL)) +#define bFM4_DMAC_DMACA4_ST *((volatile uint8_t *)(0x42C00A74UL)) +#define bFM_DMAC_DMACA4_PB *((volatile uint8_t *)(0x42C00A78UL)) +#define bFM4_DMAC_DMACA4_PB *((volatile uint8_t *)(0x42C00A78UL)) +#define bFM_DMAC_DMACA4_EB *((volatile uint8_t *)(0x42C00A7CUL)) +#define bFM4_DMAC_DMACA4_EB *((volatile uint8_t *)(0x42C00A7CUL)) + +#define bFM_DMAC_DMACA5_ST *((volatile uint8_t *)(0x42C00C74UL)) +#define bFM4_DMAC_DMACA5_ST *((volatile uint8_t *)(0x42C00C74UL)) +#define bFM_DMAC_DMACA5_PB *((volatile uint8_t *)(0x42C00C78UL)) +#define bFM4_DMAC_DMACA5_PB *((volatile uint8_t *)(0x42C00C78UL)) +#define bFM_DMAC_DMACA5_EB *((volatile uint8_t *)(0x42C00C7CUL)) +#define bFM4_DMAC_DMACA5_EB *((volatile uint8_t *)(0x42C00C7CUL)) + +#define bFM_DMAC_DMACA6_ST *((volatile uint8_t *)(0x42C00E74UL)) +#define bFM4_DMAC_DMACA6_ST *((volatile uint8_t *)(0x42C00E74UL)) +#define bFM_DMAC_DMACA6_PB *((volatile uint8_t *)(0x42C00E78UL)) +#define bFM4_DMAC_DMACA6_PB *((volatile uint8_t *)(0x42C00E78UL)) +#define bFM_DMAC_DMACA6_EB *((volatile uint8_t *)(0x42C00E7CUL)) +#define bFM4_DMAC_DMACA6_EB *((volatile uint8_t *)(0x42C00E7CUL)) + +#define bFM_DMAC_DMACA7_ST *((volatile uint8_t *)(0x42C01074UL)) +#define bFM4_DMAC_DMACA7_ST *((volatile uint8_t *)(0x42C01074UL)) +#define bFM_DMAC_DMACA7_PB *((volatile uint8_t *)(0x42C01078UL)) +#define bFM4_DMAC_DMACA7_PB *((volatile uint8_t *)(0x42C01078UL)) +#define bFM_DMAC_DMACA7_EB *((volatile uint8_t *)(0x42C0107CUL)) +#define bFM4_DMAC_DMACA7_EB *((volatile uint8_t *)(0x42C0107CUL)) + +#define bFM_DMAC_DMACB0_EM *((volatile uint8_t *)(0x42C00280UL)) +#define bFM4_DMAC_DMACB0_EM *((volatile uint8_t *)(0x42C00280UL)) +#define bFM_DMAC_DMACB0_CI *((volatile uint8_t *)(0x42C002CCUL)) +#define bFM4_DMAC_DMACB0_CI *((volatile uint8_t *)(0x42C002CCUL)) +#define bFM_DMAC_DMACB0_EI *((volatile uint8_t *)(0x42C002D0UL)) +#define bFM4_DMAC_DMACB0_EI *((volatile uint8_t *)(0x42C002D0UL)) +#define bFM_DMAC_DMACB0_RD *((volatile uint8_t *)(0x42C002D4UL)) +#define bFM4_DMAC_DMACB0_RD *((volatile uint8_t *)(0x42C002D4UL)) +#define bFM_DMAC_DMACB0_RS *((volatile uint8_t *)(0x42C002D8UL)) +#define bFM4_DMAC_DMACB0_RS *((volatile uint8_t *)(0x42C002D8UL)) +#define bFM_DMAC_DMACB0_RC *((volatile uint8_t *)(0x42C002DCUL)) +#define bFM4_DMAC_DMACB0_RC *((volatile uint8_t *)(0x42C002DCUL)) +#define bFM_DMAC_DMACB0_FD *((volatile uint8_t *)(0x42C002E0UL)) +#define bFM4_DMAC_DMACB0_FD *((volatile uint8_t *)(0x42C002E0UL)) +#define bFM_DMAC_DMACB0_FS *((volatile uint8_t *)(0x42C002E4UL)) +#define bFM4_DMAC_DMACB0_FS *((volatile uint8_t *)(0x42C002E4UL)) + +#define bFM_DMAC_DMACB1_EM *((volatile uint8_t *)(0x42C00480UL)) +#define bFM4_DMAC_DMACB1_EM *((volatile uint8_t *)(0x42C00480UL)) +#define bFM_DMAC_DMACB1_CI *((volatile uint8_t *)(0x42C004CCUL)) +#define bFM4_DMAC_DMACB1_CI *((volatile uint8_t *)(0x42C004CCUL)) +#define bFM_DMAC_DMACB1_EI *((volatile uint8_t *)(0x42C004D0UL)) +#define bFM4_DMAC_DMACB1_EI *((volatile uint8_t *)(0x42C004D0UL)) +#define bFM_DMAC_DMACB1_RD *((volatile uint8_t *)(0x42C004D4UL)) +#define bFM4_DMAC_DMACB1_RD *((volatile uint8_t *)(0x42C004D4UL)) +#define bFM_DMAC_DMACB1_RS *((volatile uint8_t *)(0x42C004D8UL)) +#define bFM4_DMAC_DMACB1_RS *((volatile uint8_t *)(0x42C004D8UL)) +#define bFM_DMAC_DMACB1_RC *((volatile uint8_t *)(0x42C004DCUL)) +#define bFM4_DMAC_DMACB1_RC *((volatile uint8_t *)(0x42C004DCUL)) +#define bFM_DMAC_DMACB1_FD *((volatile uint8_t *)(0x42C004E0UL)) +#define bFM4_DMAC_DMACB1_FD *((volatile uint8_t *)(0x42C004E0UL)) +#define bFM_DMAC_DMACB1_FS *((volatile uint8_t *)(0x42C004E4UL)) +#define bFM4_DMAC_DMACB1_FS *((volatile uint8_t *)(0x42C004E4UL)) + +#define bFM_DMAC_DMACB2_EM *((volatile uint8_t *)(0x42C00680UL)) +#define bFM4_DMAC_DMACB2_EM *((volatile uint8_t *)(0x42C00680UL)) +#define bFM_DMAC_DMACB2_CI *((volatile uint8_t *)(0x42C006CCUL)) +#define bFM4_DMAC_DMACB2_CI *((volatile uint8_t *)(0x42C006CCUL)) +#define bFM_DMAC_DMACB2_EI *((volatile uint8_t *)(0x42C006D0UL)) +#define bFM4_DMAC_DMACB2_EI *((volatile uint8_t *)(0x42C006D0UL)) +#define bFM_DMAC_DMACB2_RD *((volatile uint8_t *)(0x42C006D4UL)) +#define bFM4_DMAC_DMACB2_RD *((volatile uint8_t *)(0x42C006D4UL)) +#define bFM_DMAC_DMACB2_RS *((volatile uint8_t *)(0x42C006D8UL)) +#define bFM4_DMAC_DMACB2_RS *((volatile uint8_t *)(0x42C006D8UL)) +#define bFM_DMAC_DMACB2_RC *((volatile uint8_t *)(0x42C006DCUL)) +#define bFM4_DMAC_DMACB2_RC *((volatile uint8_t *)(0x42C006DCUL)) +#define bFM_DMAC_DMACB2_FD *((volatile uint8_t *)(0x42C006E0UL)) +#define bFM4_DMAC_DMACB2_FD *((volatile uint8_t *)(0x42C006E0UL)) +#define bFM_DMAC_DMACB2_FS *((volatile uint8_t *)(0x42C006E4UL)) +#define bFM4_DMAC_DMACB2_FS *((volatile uint8_t *)(0x42C006E4UL)) + +#define bFM_DMAC_DMACB3_EM *((volatile uint8_t *)(0x42C00880UL)) +#define bFM4_DMAC_DMACB3_EM *((volatile uint8_t *)(0x42C00880UL)) +#define bFM_DMAC_DMACB3_CI *((volatile uint8_t *)(0x42C008CCUL)) +#define bFM4_DMAC_DMACB3_CI *((volatile uint8_t *)(0x42C008CCUL)) +#define bFM_DMAC_DMACB3_EI *((volatile uint8_t *)(0x42C008D0UL)) +#define bFM4_DMAC_DMACB3_EI *((volatile uint8_t *)(0x42C008D0UL)) +#define bFM_DMAC_DMACB3_RD *((volatile uint8_t *)(0x42C008D4UL)) +#define bFM4_DMAC_DMACB3_RD *((volatile uint8_t *)(0x42C008D4UL)) +#define bFM_DMAC_DMACB3_RS *((volatile uint8_t *)(0x42C008D8UL)) +#define bFM4_DMAC_DMACB3_RS *((volatile uint8_t *)(0x42C008D8UL)) +#define bFM_DMAC_DMACB3_RC *((volatile uint8_t *)(0x42C008DCUL)) +#define bFM4_DMAC_DMACB3_RC *((volatile uint8_t *)(0x42C008DCUL)) +#define bFM_DMAC_DMACB3_FD *((volatile uint8_t *)(0x42C008E0UL)) +#define bFM4_DMAC_DMACB3_FD *((volatile uint8_t *)(0x42C008E0UL)) +#define bFM_DMAC_DMACB3_FS *((volatile uint8_t *)(0x42C008E4UL)) +#define bFM4_DMAC_DMACB3_FS *((volatile uint8_t *)(0x42C008E4UL)) + +#define bFM_DMAC_DMACB4_EM *((volatile uint8_t *)(0x42C00A80UL)) +#define bFM4_DMAC_DMACB4_EM *((volatile uint8_t *)(0x42C00A80UL)) +#define bFM_DMAC_DMACB4_CI *((volatile uint8_t *)(0x42C00ACCUL)) +#define bFM4_DMAC_DMACB4_CI *((volatile uint8_t *)(0x42C00ACCUL)) +#define bFM_DMAC_DMACB4_EI *((volatile uint8_t *)(0x42C00AD0UL)) +#define bFM4_DMAC_DMACB4_EI *((volatile uint8_t *)(0x42C00AD0UL)) +#define bFM_DMAC_DMACB4_RD *((volatile uint8_t *)(0x42C00AD4UL)) +#define bFM4_DMAC_DMACB4_RD *((volatile uint8_t *)(0x42C00AD4UL)) +#define bFM_DMAC_DMACB4_RS *((volatile uint8_t *)(0x42C00AD8UL)) +#define bFM4_DMAC_DMACB4_RS *((volatile uint8_t *)(0x42C00AD8UL)) +#define bFM_DMAC_DMACB4_RC *((volatile uint8_t *)(0x42C00ADCUL)) +#define bFM4_DMAC_DMACB4_RC *((volatile uint8_t *)(0x42C00ADCUL)) +#define bFM_DMAC_DMACB4_FD *((volatile uint8_t *)(0x42C00AE0UL)) +#define bFM4_DMAC_DMACB4_FD *((volatile uint8_t *)(0x42C00AE0UL)) +#define bFM_DMAC_DMACB4_FS *((volatile uint8_t *)(0x42C00AE4UL)) +#define bFM4_DMAC_DMACB4_FS *((volatile uint8_t *)(0x42C00AE4UL)) + +#define bFM_DMAC_DMACB5_EM *((volatile uint8_t *)(0x42C00C80UL)) +#define bFM4_DMAC_DMACB5_EM *((volatile uint8_t *)(0x42C00C80UL)) +#define bFM_DMAC_DMACB5_CI *((volatile uint8_t *)(0x42C00CCCUL)) +#define bFM4_DMAC_DMACB5_CI *((volatile uint8_t *)(0x42C00CCCUL)) +#define bFM_DMAC_DMACB5_EI *((volatile uint8_t *)(0x42C00CD0UL)) +#define bFM4_DMAC_DMACB5_EI *((volatile uint8_t *)(0x42C00CD0UL)) +#define bFM_DMAC_DMACB5_RD *((volatile uint8_t *)(0x42C00CD4UL)) +#define bFM4_DMAC_DMACB5_RD *((volatile uint8_t *)(0x42C00CD4UL)) +#define bFM_DMAC_DMACB5_RS *((volatile uint8_t *)(0x42C00CD8UL)) +#define bFM4_DMAC_DMACB5_RS *((volatile uint8_t *)(0x42C00CD8UL)) +#define bFM_DMAC_DMACB5_RC *((volatile uint8_t *)(0x42C00CDCUL)) +#define bFM4_DMAC_DMACB5_RC *((volatile uint8_t *)(0x42C00CDCUL)) +#define bFM_DMAC_DMACB5_FD *((volatile uint8_t *)(0x42C00CE0UL)) +#define bFM4_DMAC_DMACB5_FD *((volatile uint8_t *)(0x42C00CE0UL)) +#define bFM_DMAC_DMACB5_FS *((volatile uint8_t *)(0x42C00CE4UL)) +#define bFM4_DMAC_DMACB5_FS *((volatile uint8_t *)(0x42C00CE4UL)) + +#define bFM_DMAC_DMACB6_EM *((volatile uint8_t *)(0x42C00E80UL)) +#define bFM4_DMAC_DMACB6_EM *((volatile uint8_t *)(0x42C00E80UL)) +#define bFM_DMAC_DMACB6_CI *((volatile uint8_t *)(0x42C00ECCUL)) +#define bFM4_DMAC_DMACB6_CI *((volatile uint8_t *)(0x42C00ECCUL)) +#define bFM_DMAC_DMACB6_EI *((volatile uint8_t *)(0x42C00ED0UL)) +#define bFM4_DMAC_DMACB6_EI *((volatile uint8_t *)(0x42C00ED0UL)) +#define bFM_DMAC_DMACB6_RD *((volatile uint8_t *)(0x42C00ED4UL)) +#define bFM4_DMAC_DMACB6_RD *((volatile uint8_t *)(0x42C00ED4UL)) +#define bFM_DMAC_DMACB6_RS *((volatile uint8_t *)(0x42C00ED8UL)) +#define bFM4_DMAC_DMACB6_RS *((volatile uint8_t *)(0x42C00ED8UL)) +#define bFM_DMAC_DMACB6_RC *((volatile uint8_t *)(0x42C00EDCUL)) +#define bFM4_DMAC_DMACB6_RC *((volatile uint8_t *)(0x42C00EDCUL)) +#define bFM_DMAC_DMACB6_FD *((volatile uint8_t *)(0x42C00EE0UL)) +#define bFM4_DMAC_DMACB6_FD *((volatile uint8_t *)(0x42C00EE0UL)) +#define bFM_DMAC_DMACB6_FS *((volatile uint8_t *)(0x42C00EE4UL)) +#define bFM4_DMAC_DMACB6_FS *((volatile uint8_t *)(0x42C00EE4UL)) + +#define bFM_DMAC_DMACB7_EM *((volatile uint8_t *)(0x42C01080UL)) +#define bFM4_DMAC_DMACB7_EM *((volatile uint8_t *)(0x42C01080UL)) +#define bFM_DMAC_DMACB7_CI *((volatile uint8_t *)(0x42C010CCUL)) +#define bFM4_DMAC_DMACB7_CI *((volatile uint8_t *)(0x42C010CCUL)) +#define bFM_DMAC_DMACB7_EI *((volatile uint8_t *)(0x42C010D0UL)) +#define bFM4_DMAC_DMACB7_EI *((volatile uint8_t *)(0x42C010D0UL)) +#define bFM_DMAC_DMACB7_RD *((volatile uint8_t *)(0x42C010D4UL)) +#define bFM4_DMAC_DMACB7_RD *((volatile uint8_t *)(0x42C010D4UL)) +#define bFM_DMAC_DMACB7_RS *((volatile uint8_t *)(0x42C010D8UL)) +#define bFM4_DMAC_DMACB7_RS *((volatile uint8_t *)(0x42C010D8UL)) +#define bFM_DMAC_DMACB7_RC *((volatile uint8_t *)(0x42C010DCUL)) +#define bFM4_DMAC_DMACB7_RC *((volatile uint8_t *)(0x42C010DCUL)) +#define bFM_DMAC_DMACB7_FD *((volatile uint8_t *)(0x42C010E0UL)) +#define bFM4_DMAC_DMACB7_FD *((volatile uint8_t *)(0x42C010E0UL)) +#define bFM_DMAC_DMACB7_FS *((volatile uint8_t *)(0x42C010E4UL)) +#define bFM4_DMAC_DMACB7_FS *((volatile uint8_t *)(0x42C010E4UL)) + +#define bFM_DMAC_DMACR_PR *((volatile uint8_t *)(0x42C00070UL)) +#define bFM4_DMAC_DMACR_PR *((volatile uint8_t *)(0x42C00070UL)) +#define bFM_DMAC_DMACR_DS *((volatile uint8_t *)(0x42C00078UL)) +#define bFM4_DMAC_DMACR_DS *((volatile uint8_t *)(0x42C00078UL)) +#define bFM_DMAC_DMACR_DE *((volatile uint8_t *)(0x42C0007CUL)) +#define bFM4_DMAC_DMACR_DE *((volatile uint8_t *)(0x42C0007CUL)) + + +/******************************************************************************* +* DS Registers DS +* Bitband Section +*******************************************************************************/ +#define bFM_DS_PMD_CTL_RTCE *((volatile uint8_t *)(0x426B0000UL)) +#define bFM4_DS_PMD_CTL_RTCE *((volatile uint8_t *)(0x426B0000UL)) + +#define bFM_DS_RCK_CTL_RTCCKE *((volatile uint8_t *)(0x426A2080UL)) +#define bFM4_DS_RCK_CTL_RTCCKE *((volatile uint8_t *)(0x426A2080UL)) +#define bFM_DS_RCK_CTL_CECCKE *((volatile uint8_t *)(0x426A2084UL)) +#define bFM4_DS_RCK_CTL_CECCKE *((volatile uint8_t *)(0x426A2084UL)) + +#define bFM_DS_WIER_WRTCE *((volatile uint8_t *)(0x426B0180UL)) +#define bFM4_DS_WIER_WRTCE *((volatile uint8_t *)(0x426B0180UL)) +#define bFM_DS_WIER_WLVDE *((volatile uint8_t *)(0x426B0184UL)) +#define bFM4_DS_WIER_WLVDE *((volatile uint8_t *)(0x426B0184UL)) +#define bFM_DS_WIER_WUI1E *((volatile uint8_t *)(0x426B018CUL)) +#define bFM4_DS_WIER_WUI1E *((volatile uint8_t *)(0x426B018CUL)) +#define bFM_DS_WIER_WUI2E *((volatile uint8_t *)(0x426B0190UL)) +#define bFM4_DS_WIER_WUI2E *((volatile uint8_t *)(0x426B0190UL)) +#define bFM_DS_WIER_WUI3E *((volatile uint8_t *)(0x426B0194UL)) +#define bFM4_DS_WIER_WUI3E *((volatile uint8_t *)(0x426B0194UL)) +#define bFM_DS_WIER_WUI4E *((volatile uint8_t *)(0x426B0198UL)) +#define bFM4_DS_WIER_WUI4E *((volatile uint8_t *)(0x426B0198UL)) +#define bFM_DS_WIER_WUI5E *((volatile uint8_t *)(0x426B019CUL)) +#define bFM4_DS_WIER_WUI5E *((volatile uint8_t *)(0x426B019CUL)) + +#define bFM_DS_WIFSR_WRTCI *((volatile uint8_t *)(0x426B0100UL)) +#define bFM4_DS_WIFSR_WRTCI *((volatile uint8_t *)(0x426B0100UL)) +#define bFM_DS_WIFSR_WLVDI *((volatile uint8_t *)(0x426B0104UL)) +#define bFM4_DS_WIFSR_WLVDI *((volatile uint8_t *)(0x426B0104UL)) +#define bFM_DS_WIFSR_WUI0 *((volatile uint8_t *)(0x426B0108UL)) +#define bFM4_DS_WIFSR_WUI0 *((volatile uint8_t *)(0x426B0108UL)) +#define bFM_DS_WIFSR_WUI1 *((volatile uint8_t *)(0x426B010CUL)) +#define bFM4_DS_WIFSR_WUI1 *((volatile uint8_t *)(0x426B010CUL)) +#define bFM_DS_WIFSR_WUI2 *((volatile uint8_t *)(0x426B0110UL)) +#define bFM4_DS_WIFSR_WUI2 *((volatile uint8_t *)(0x426B0110UL)) +#define bFM_DS_WIFSR_WUI3 *((volatile uint8_t *)(0x426B0114UL)) +#define bFM4_DS_WIFSR_WUI3 *((volatile uint8_t *)(0x426B0114UL)) +#define bFM_DS_WIFSR_WUI4 *((volatile uint8_t *)(0x426B0118UL)) +#define bFM4_DS_WIFSR_WUI4 *((volatile uint8_t *)(0x426B0118UL)) +#define bFM_DS_WIFSR_WUI5 *((volatile uint8_t *)(0x426B011CUL)) +#define bFM4_DS_WIFSR_WUI5 *((volatile uint8_t *)(0x426B011CUL)) + +#define bFM_DS_WILVR_WUI1LV *((volatile uint8_t *)(0x426B0200UL)) +#define bFM4_DS_WILVR_WUI1LV *((volatile uint8_t *)(0x426B0200UL)) +#define bFM_DS_WILVR_WUI2LV *((volatile uint8_t *)(0x426B0204UL)) +#define bFM4_DS_WILVR_WUI2LV *((volatile uint8_t *)(0x426B0204UL)) +#define bFM_DS_WILVR_WUI3LV *((volatile uint8_t *)(0x426B0208UL)) +#define bFM4_DS_WILVR_WUI3LV *((volatile uint8_t *)(0x426B0208UL)) +#define bFM_DS_WILVR_WUI4LV *((volatile uint8_t *)(0x426B020CUL)) +#define bFM4_DS_WILVR_WUI4LV *((volatile uint8_t *)(0x426B020CUL)) +#define bFM_DS_WILVR_WUI5LV *((volatile uint8_t *)(0x426B0210UL)) +#define bFM4_DS_WILVR_WUI5LV *((volatile uint8_t *)(0x426B0210UL)) + +#define bFM_DS_WRFSR_WINITX *((volatile uint8_t *)(0x426B0080UL)) +#define bFM4_DS_WRFSR_WINITX *((volatile uint8_t *)(0x426B0080UL)) +#define bFM_DS_WRFSR_WLVDH *((volatile uint8_t *)(0x426B0084UL)) +#define bFM4_DS_WRFSR_WLVDH *((volatile uint8_t *)(0x426B0084UL)) + + +/******************************************************************************* +* DSTC Registers DSTC +* Bitband Section +*******************************************************************************/ +#define bFM_DSTC_CFG_SWINTE *((volatile uint8_t *)(0x42C20120UL)) +#define bFM4_DSTC_CFG_SWINTE *((volatile uint8_t *)(0x42C20120UL)) +#define bFM_DSTC_CFG_ERINTE *((volatile uint8_t *)(0x42C20124UL)) +#define bFM4_DSTC_CFG_ERINTE *((volatile uint8_t *)(0x42C20124UL)) +#define bFM_DSTC_CFG_RBDIS *((volatile uint8_t *)(0x42C20128UL)) +#define bFM4_DSTC_CFG_RBDIS *((volatile uint8_t *)(0x42C20128UL)) +#define bFM_DSTC_CFG_ESTE *((volatile uint8_t *)(0x42C2012CUL)) +#define bFM4_DSTC_CFG_ESTE *((volatile uint8_t *)(0x42C2012CUL)) + +#define bFM_DSTC_MONERS_DER *((volatile uint8_t *)(0x42C2018CUL)) +#define bFM4_DSTC_MONERS_DER *((volatile uint8_t *)(0x42C2018CUL)) +#define bFM_DSTC_MONERS_ESTOP *((volatile uint8_t *)(0x42C20190UL)) +#define bFM4_DSTC_MONERS_ESTOP *((volatile uint8_t *)(0x42C20190UL)) +#define bFM_DSTC_MONERS_EHS *((volatile uint8_t *)(0x42C20198UL)) +#define bFM4_DSTC_MONERS_EHS *((volatile uint8_t *)(0x42C20198UL)) + +#define bFM_DSTC_SWTR_SWREQ *((volatile uint16_t*)(0x42C20178UL)) +#define bFM4_DSTC_SWTR_SWREQ *((volatile uint16_t*)(0x42C20178UL)) +#define bFM_DSTC_SWTR_SWST *((volatile uint16_t*)(0x42C2017CUL)) +#define bFM4_DSTC_SWTR_SWST *((volatile uint16_t*)(0x42C2017CUL)) + + +/******************************************************************************* +* DT Registers DT +* Bitband Section +*******************************************************************************/ +#define bFM_DT_TIMER1CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0100UL)) +#define bFM4_DT_TIMER1CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0100UL)) +#define bFM_DT_TIMER1CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0104UL)) +#define bFM4_DT_TIMER1CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0104UL)) +#define bFM_DT_TIMER1CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0114UL)) +#define bFM4_DT_TIMER1CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0114UL)) +#define bFM_DT_TIMER1CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0118UL)) +#define bFM4_DT_TIMER1CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0118UL)) +#define bFM_DT_TIMER1CONTROL_TIMEREN *((volatile uint32_t*)(0x422A011CUL)) +#define bFM4_DT_TIMER1CONTROL_TIMEREN *((volatile uint32_t*)(0x422A011CUL)) + +#define bFM_DT_TIMER1MIS_TIMER1MIS *((volatile uint32_t*)(0x422A0280UL)) +#define bFM4_DT_TIMER1MIS_TIMER1MIS *((volatile uint32_t*)(0x422A0280UL)) + +#define bFM_DT_TIMER1RIS_TIMER1RIS *((volatile uint32_t*)(0x422A0200UL)) +#define bFM4_DT_TIMER1RIS_TIMER1RIS *((volatile uint32_t*)(0x422A0200UL)) + +#define bFM_DT_TIMER2CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0500UL)) +#define bFM4_DT_TIMER2CONTROL_ONESHOT *((volatile uint32_t*)(0x422A0500UL)) +#define bFM_DT_TIMER2CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0504UL)) +#define bFM4_DT_TIMER2CONTROL_TIMERSIZE *((volatile uint32_t*)(0x422A0504UL)) +#define bFM_DT_TIMER2CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0514UL)) +#define bFM4_DT_TIMER2CONTROL_INTENABLE *((volatile uint32_t*)(0x422A0514UL)) +#define bFM_DT_TIMER2CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0518UL)) +#define bFM4_DT_TIMER2CONTROL_TIMERMODE *((volatile uint32_t*)(0x422A0518UL)) +#define bFM_DT_TIMER2CONTROL_TIMEREN *((volatile uint32_t*)(0x422A051CUL)) +#define bFM4_DT_TIMER2CONTROL_TIMEREN *((volatile uint32_t*)(0x422A051CUL)) + +#define bFM_DT_TIMER2MIS_TIMER2MIS *((volatile uint32_t*)(0x422A0680UL)) +#define bFM4_DT_TIMER2MIS_TIMER2MIS *((volatile uint32_t*)(0x422A0680UL)) + +#define bFM_DT_TIMER2RIS_TIMER2RIS *((volatile uint32_t*)(0x422A0600UL)) +#define bFM4_DT_TIMER2RIS_TIMER2RIS *((volatile uint32_t*)(0x422A0600UL)) + + +/******************************************************************************* +* DUALFLASH_IF Registers DUALFLASH_IF +* Bitband Section +*******************************************************************************/ +#define bFM_DUALFLASH_IF_DFSTR_DFRDY *((volatile uint8_t *)(0x42008100UL)) +#define bFM4_DUALFLASH_IF_DFSTR_DFRDY *((volatile uint8_t *)(0x42008100UL)) +#define bFM_DUALFLASH_IF_DFSTR_DFHNG *((volatile uint8_t *)(0x42008104UL)) +#define bFM4_DUALFLASH_IF_DFSTR_DFHNG *((volatile uint8_t *)(0x42008104UL)) +#define bFM_DUALFLASH_IF_DFSTR_DFERR *((volatile uint8_t *)(0x42008108UL)) +#define bFM4_DUALFLASH_IF_DFSTR_DFERR *((volatile uint8_t *)(0x42008108UL)) + + +/******************************************************************************* +* ECC_CAPTURE Registers ECC_CAPTURE +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* EXTI Registers EXTI +* Bitband Section +*******************************************************************************/ +#define bFM_EXTI_EICL_ECL0 *((volatile uint8_t *)(0x42600100UL)) +#define bFM4_EXTI_EICL_ECL0 *((volatile uint8_t *)(0x42600100UL)) +#define bFM_EXTI_EICL_ECL1 *((volatile uint8_t *)(0x42600104UL)) +#define bFM4_EXTI_EICL_ECL1 *((volatile uint8_t *)(0x42600104UL)) +#define bFM_EXTI_EICL_ECL2 *((volatile uint8_t *)(0x42600108UL)) +#define bFM4_EXTI_EICL_ECL2 *((volatile uint8_t *)(0x42600108UL)) +#define bFM_EXTI_EICL_ECL3 *((volatile uint8_t *)(0x4260010CUL)) +#define bFM4_EXTI_EICL_ECL3 *((volatile uint8_t *)(0x4260010CUL)) +#define bFM_EXTI_EICL_ECL4 *((volatile uint8_t *)(0x42600110UL)) +#define bFM4_EXTI_EICL_ECL4 *((volatile uint8_t *)(0x42600110UL)) +#define bFM_EXTI_EICL_ECL5 *((volatile uint8_t *)(0x42600114UL)) +#define bFM4_EXTI_EICL_ECL5 *((volatile uint8_t *)(0x42600114UL)) +#define bFM_EXTI_EICL_ECL6 *((volatile uint8_t *)(0x42600118UL)) +#define bFM4_EXTI_EICL_ECL6 *((volatile uint8_t *)(0x42600118UL)) +#define bFM_EXTI_EICL_ECL7 *((volatile uint8_t *)(0x4260011CUL)) +#define bFM4_EXTI_EICL_ECL7 *((volatile uint8_t *)(0x4260011CUL)) +#define bFM_EXTI_EICL_ECL8 *((volatile uint8_t *)(0x42600120UL)) +#define bFM4_EXTI_EICL_ECL8 *((volatile uint8_t *)(0x42600120UL)) +#define bFM_EXTI_EICL_ECL9 *((volatile uint8_t *)(0x42600124UL)) +#define bFM4_EXTI_EICL_ECL9 *((volatile uint8_t *)(0x42600124UL)) +#define bFM_EXTI_EICL_ECL10 *((volatile uint8_t *)(0x42600128UL)) +#define bFM4_EXTI_EICL_ECL10 *((volatile uint8_t *)(0x42600128UL)) +#define bFM_EXTI_EICL_ECL11 *((volatile uint8_t *)(0x4260012CUL)) +#define bFM4_EXTI_EICL_ECL11 *((volatile uint8_t *)(0x4260012CUL)) +#define bFM_EXTI_EICL_ECL12 *((volatile uint8_t *)(0x42600130UL)) +#define bFM4_EXTI_EICL_ECL12 *((volatile uint8_t *)(0x42600130UL)) +#define bFM_EXTI_EICL_ECL13 *((volatile uint8_t *)(0x42600134UL)) +#define bFM4_EXTI_EICL_ECL13 *((volatile uint8_t *)(0x42600134UL)) +#define bFM_EXTI_EICL_ECL14 *((volatile uint8_t *)(0x42600138UL)) +#define bFM4_EXTI_EICL_ECL14 *((volatile uint8_t *)(0x42600138UL)) +#define bFM_EXTI_EICL_ECL15 *((volatile uint8_t *)(0x4260013CUL)) +#define bFM4_EXTI_EICL_ECL15 *((volatile uint8_t *)(0x4260013CUL)) +#define bFM_EXTI_EICL_ECL16 *((volatile uint8_t *)(0x42600140UL)) +#define bFM4_EXTI_EICL_ECL16 *((volatile uint8_t *)(0x42600140UL)) +#define bFM_EXTI_EICL_ECL17 *((volatile uint8_t *)(0x42600144UL)) +#define bFM4_EXTI_EICL_ECL17 *((volatile uint8_t *)(0x42600144UL)) +#define bFM_EXTI_EICL_ECL18 *((volatile uint8_t *)(0x42600148UL)) +#define bFM4_EXTI_EICL_ECL18 *((volatile uint8_t *)(0x42600148UL)) +#define bFM_EXTI_EICL_ECL19 *((volatile uint8_t *)(0x4260014CUL)) +#define bFM4_EXTI_EICL_ECL19 *((volatile uint8_t *)(0x4260014CUL)) +#define bFM_EXTI_EICL_ECL20 *((volatile uint8_t *)(0x42600150UL)) +#define bFM4_EXTI_EICL_ECL20 *((volatile uint8_t *)(0x42600150UL)) +#define bFM_EXTI_EICL_ECL21 *((volatile uint8_t *)(0x42600154UL)) +#define bFM4_EXTI_EICL_ECL21 *((volatile uint8_t *)(0x42600154UL)) +#define bFM_EXTI_EICL_ECL22 *((volatile uint8_t *)(0x42600158UL)) +#define bFM4_EXTI_EICL_ECL22 *((volatile uint8_t *)(0x42600158UL)) +#define bFM_EXTI_EICL_ECL23 *((volatile uint8_t *)(0x4260015CUL)) +#define bFM4_EXTI_EICL_ECL23 *((volatile uint8_t *)(0x4260015CUL)) +#define bFM_EXTI_EICL_ECL24 *((volatile uint8_t *)(0x42600160UL)) +#define bFM4_EXTI_EICL_ECL24 *((volatile uint8_t *)(0x42600160UL)) +#define bFM_EXTI_EICL_ECL25 *((volatile uint8_t *)(0x42600164UL)) +#define bFM4_EXTI_EICL_ECL25 *((volatile uint8_t *)(0x42600164UL)) +#define bFM_EXTI_EICL_ECL26 *((volatile uint8_t *)(0x42600168UL)) +#define bFM4_EXTI_EICL_ECL26 *((volatile uint8_t *)(0x42600168UL)) +#define bFM_EXTI_EICL_ECL27 *((volatile uint8_t *)(0x4260016CUL)) +#define bFM4_EXTI_EICL_ECL27 *((volatile uint8_t *)(0x4260016CUL)) +#define bFM_EXTI_EICL_ECL28 *((volatile uint8_t *)(0x42600170UL)) +#define bFM4_EXTI_EICL_ECL28 *((volatile uint8_t *)(0x42600170UL)) +#define bFM_EXTI_EICL_ECL29 *((volatile uint8_t *)(0x42600174UL)) +#define bFM4_EXTI_EICL_ECL29 *((volatile uint8_t *)(0x42600174UL)) +#define bFM_EXTI_EICL_ECL30 *((volatile uint8_t *)(0x42600178UL)) +#define bFM4_EXTI_EICL_ECL30 *((volatile uint8_t *)(0x42600178UL)) +#define bFM_EXTI_EICL_ECL31 *((volatile uint8_t *)(0x4260017CUL)) +#define bFM4_EXTI_EICL_ECL31 *((volatile uint8_t *)(0x4260017CUL)) + +#define bFM_EXTI_EIRR_ER0 *((volatile uint8_t *)(0x42600080UL)) +#define bFM4_EXTI_EIRR_ER0 *((volatile uint8_t *)(0x42600080UL)) +#define bFM_EXTI_EIRR_ER1 *((volatile uint8_t *)(0x42600084UL)) +#define bFM4_EXTI_EIRR_ER1 *((volatile uint8_t *)(0x42600084UL)) +#define bFM_EXTI_EIRR_ER2 *((volatile uint8_t *)(0x42600088UL)) +#define bFM4_EXTI_EIRR_ER2 *((volatile uint8_t *)(0x42600088UL)) +#define bFM_EXTI_EIRR_ER3 *((volatile uint8_t *)(0x4260008CUL)) +#define bFM4_EXTI_EIRR_ER3 *((volatile uint8_t *)(0x4260008CUL)) +#define bFM_EXTI_EIRR_ER4 *((volatile uint8_t *)(0x42600090UL)) +#define bFM4_EXTI_EIRR_ER4 *((volatile uint8_t *)(0x42600090UL)) +#define bFM_EXTI_EIRR_ER5 *((volatile uint8_t *)(0x42600094UL)) +#define bFM4_EXTI_EIRR_ER5 *((volatile uint8_t *)(0x42600094UL)) +#define bFM_EXTI_EIRR_ER6 *((volatile uint8_t *)(0x42600098UL)) +#define bFM4_EXTI_EIRR_ER6 *((volatile uint8_t *)(0x42600098UL)) +#define bFM_EXTI_EIRR_ER7 *((volatile uint8_t *)(0x4260009CUL)) +#define bFM4_EXTI_EIRR_ER7 *((volatile uint8_t *)(0x4260009CUL)) +#define bFM_EXTI_EIRR_ER8 *((volatile uint8_t *)(0x426000A0UL)) +#define bFM4_EXTI_EIRR_ER8 *((volatile uint8_t *)(0x426000A0UL)) +#define bFM_EXTI_EIRR_ER9 *((volatile uint8_t *)(0x426000A4UL)) +#define bFM4_EXTI_EIRR_ER9 *((volatile uint8_t *)(0x426000A4UL)) +#define bFM_EXTI_EIRR_ER10 *((volatile uint8_t *)(0x426000A8UL)) +#define bFM4_EXTI_EIRR_ER10 *((volatile uint8_t *)(0x426000A8UL)) +#define bFM_EXTI_EIRR_ER11 *((volatile uint8_t *)(0x426000ACUL)) +#define bFM4_EXTI_EIRR_ER11 *((volatile uint8_t *)(0x426000ACUL)) +#define bFM_EXTI_EIRR_ER12 *((volatile uint8_t *)(0x426000B0UL)) +#define bFM4_EXTI_EIRR_ER12 *((volatile uint8_t *)(0x426000B0UL)) +#define bFM_EXTI_EIRR_ER13 *((volatile uint8_t *)(0x426000B4UL)) +#define bFM4_EXTI_EIRR_ER13 *((volatile uint8_t *)(0x426000B4UL)) +#define bFM_EXTI_EIRR_ER14 *((volatile uint8_t *)(0x426000B8UL)) +#define bFM4_EXTI_EIRR_ER14 *((volatile uint8_t *)(0x426000B8UL)) +#define bFM_EXTI_EIRR_ER15 *((volatile uint8_t *)(0x426000BCUL)) +#define bFM4_EXTI_EIRR_ER15 *((volatile uint8_t *)(0x426000BCUL)) +#define bFM_EXTI_EIRR_ER16 *((volatile uint8_t *)(0x426000C0UL)) +#define bFM4_EXTI_EIRR_ER16 *((volatile uint8_t *)(0x426000C0UL)) +#define bFM_EXTI_EIRR_ER17 *((volatile uint8_t *)(0x426000C4UL)) +#define bFM4_EXTI_EIRR_ER17 *((volatile uint8_t *)(0x426000C4UL)) +#define bFM_EXTI_EIRR_ER18 *((volatile uint8_t *)(0x426000C8UL)) +#define bFM4_EXTI_EIRR_ER18 *((volatile uint8_t *)(0x426000C8UL)) +#define bFM_EXTI_EIRR_ER19 *((volatile uint8_t *)(0x426000CCUL)) +#define bFM4_EXTI_EIRR_ER19 *((volatile uint8_t *)(0x426000CCUL)) +#define bFM_EXTI_EIRR_ER20 *((volatile uint8_t *)(0x426000D0UL)) +#define bFM4_EXTI_EIRR_ER20 *((volatile uint8_t *)(0x426000D0UL)) +#define bFM_EXTI_EIRR_ER21 *((volatile uint8_t *)(0x426000D4UL)) +#define bFM4_EXTI_EIRR_ER21 *((volatile uint8_t *)(0x426000D4UL)) +#define bFM_EXTI_EIRR_ER22 *((volatile uint8_t *)(0x426000D8UL)) +#define bFM4_EXTI_EIRR_ER22 *((volatile uint8_t *)(0x426000D8UL)) +#define bFM_EXTI_EIRR_ER23 *((volatile uint8_t *)(0x426000DCUL)) +#define bFM4_EXTI_EIRR_ER23 *((volatile uint8_t *)(0x426000DCUL)) +#define bFM_EXTI_EIRR_ER24 *((volatile uint8_t *)(0x426000E0UL)) +#define bFM4_EXTI_EIRR_ER24 *((volatile uint8_t *)(0x426000E0UL)) +#define bFM_EXTI_EIRR_ER25 *((volatile uint8_t *)(0x426000E4UL)) +#define bFM4_EXTI_EIRR_ER25 *((volatile uint8_t *)(0x426000E4UL)) +#define bFM_EXTI_EIRR_ER26 *((volatile uint8_t *)(0x426000E8UL)) +#define bFM4_EXTI_EIRR_ER26 *((volatile uint8_t *)(0x426000E8UL)) +#define bFM_EXTI_EIRR_ER27 *((volatile uint8_t *)(0x426000ECUL)) +#define bFM4_EXTI_EIRR_ER27 *((volatile uint8_t *)(0x426000ECUL)) +#define bFM_EXTI_EIRR_ER28 *((volatile uint8_t *)(0x426000F0UL)) +#define bFM4_EXTI_EIRR_ER28 *((volatile uint8_t *)(0x426000F0UL)) +#define bFM_EXTI_EIRR_ER29 *((volatile uint8_t *)(0x426000F4UL)) +#define bFM4_EXTI_EIRR_ER29 *((volatile uint8_t *)(0x426000F4UL)) +#define bFM_EXTI_EIRR_ER30 *((volatile uint8_t *)(0x426000F8UL)) +#define bFM4_EXTI_EIRR_ER30 *((volatile uint8_t *)(0x426000F8UL)) +#define bFM_EXTI_EIRR_ER31 *((volatile uint8_t *)(0x426000FCUL)) +#define bFM4_EXTI_EIRR_ER31 *((volatile uint8_t *)(0x426000FCUL)) + +#define bFM_EXTI_ELVR_LA0 *((volatile uint8_t *)(0x42600180UL)) +#define bFM4_EXTI_ELVR_LA0 *((volatile uint8_t *)(0x42600180UL)) +#define bFM_EXTI_ELVR_LB0 *((volatile uint8_t *)(0x42600184UL)) +#define bFM4_EXTI_ELVR_LB0 *((volatile uint8_t *)(0x42600184UL)) +#define bFM_EXTI_ELVR_LA1 *((volatile uint8_t *)(0x42600188UL)) +#define bFM4_EXTI_ELVR_LA1 *((volatile uint8_t *)(0x42600188UL)) +#define bFM_EXTI_ELVR_LB1 *((volatile uint8_t *)(0x4260018CUL)) +#define bFM4_EXTI_ELVR_LB1 *((volatile uint8_t *)(0x4260018CUL)) +#define bFM_EXTI_ELVR_LA2 *((volatile uint8_t *)(0x42600190UL)) +#define bFM4_EXTI_ELVR_LA2 *((volatile uint8_t *)(0x42600190UL)) +#define bFM_EXTI_ELVR_LB2 *((volatile uint8_t *)(0x42600194UL)) +#define bFM4_EXTI_ELVR_LB2 *((volatile uint8_t *)(0x42600194UL)) +#define bFM_EXTI_ELVR_LA3 *((volatile uint8_t *)(0x42600198UL)) +#define bFM4_EXTI_ELVR_LA3 *((volatile uint8_t *)(0x42600198UL)) +#define bFM_EXTI_ELVR_LB3 *((volatile uint8_t *)(0x4260019CUL)) +#define bFM4_EXTI_ELVR_LB3 *((volatile uint8_t *)(0x4260019CUL)) +#define bFM_EXTI_ELVR_LA4 *((volatile uint8_t *)(0x426001A0UL)) +#define bFM4_EXTI_ELVR_LA4 *((volatile uint8_t *)(0x426001A0UL)) +#define bFM_EXTI_ELVR_LB4 *((volatile uint8_t *)(0x426001A4UL)) +#define bFM4_EXTI_ELVR_LB4 *((volatile uint8_t *)(0x426001A4UL)) +#define bFM_EXTI_ELVR_LA5 *((volatile uint8_t *)(0x426001A8UL)) +#define bFM4_EXTI_ELVR_LA5 *((volatile uint8_t *)(0x426001A8UL)) +#define bFM_EXTI_ELVR_LB5 *((volatile uint8_t *)(0x426001ACUL)) +#define bFM4_EXTI_ELVR_LB5 *((volatile uint8_t *)(0x426001ACUL)) +#define bFM_EXTI_ELVR_LA6 *((volatile uint8_t *)(0x426001B0UL)) +#define bFM4_EXTI_ELVR_LA6 *((volatile uint8_t *)(0x426001B0UL)) +#define bFM_EXTI_ELVR_LB6 *((volatile uint8_t *)(0x426001B4UL)) +#define bFM4_EXTI_ELVR_LB6 *((volatile uint8_t *)(0x426001B4UL)) +#define bFM_EXTI_ELVR_LA7 *((volatile uint8_t *)(0x426001B8UL)) +#define bFM4_EXTI_ELVR_LA7 *((volatile uint8_t *)(0x426001B8UL)) +#define bFM_EXTI_ELVR_LB7 *((volatile uint8_t *)(0x426001BCUL)) +#define bFM4_EXTI_ELVR_LB7 *((volatile uint8_t *)(0x426001BCUL)) +#define bFM_EXTI_ELVR_LA8 *((volatile uint8_t *)(0x426001C0UL)) +#define bFM4_EXTI_ELVR_LA8 *((volatile uint8_t *)(0x426001C0UL)) +#define bFM_EXTI_ELVR_LB8 *((volatile uint8_t *)(0x426001C4UL)) +#define bFM4_EXTI_ELVR_LB8 *((volatile uint8_t *)(0x426001C4UL)) +#define bFM_EXTI_ELVR_LA9 *((volatile uint8_t *)(0x426001C8UL)) +#define bFM4_EXTI_ELVR_LA9 *((volatile uint8_t *)(0x426001C8UL)) +#define bFM_EXTI_ELVR_LB9 *((volatile uint8_t *)(0x426001CCUL)) +#define bFM4_EXTI_ELVR_LB9 *((volatile uint8_t *)(0x426001CCUL)) +#define bFM_EXTI_ELVR_LA10 *((volatile uint8_t *)(0x426001D0UL)) +#define bFM4_EXTI_ELVR_LA10 *((volatile uint8_t *)(0x426001D0UL)) +#define bFM_EXTI_ELVR_LB10 *((volatile uint8_t *)(0x426001D4UL)) +#define bFM4_EXTI_ELVR_LB10 *((volatile uint8_t *)(0x426001D4UL)) +#define bFM_EXTI_ELVR_LA11 *((volatile uint8_t *)(0x426001D8UL)) +#define bFM4_EXTI_ELVR_LA11 *((volatile uint8_t *)(0x426001D8UL)) +#define bFM_EXTI_ELVR_LB11 *((volatile uint8_t *)(0x426001DCUL)) +#define bFM4_EXTI_ELVR_LB11 *((volatile uint8_t *)(0x426001DCUL)) +#define bFM_EXTI_ELVR_LA12 *((volatile uint8_t *)(0x426001E0UL)) +#define bFM4_EXTI_ELVR_LA12 *((volatile uint8_t *)(0x426001E0UL)) +#define bFM_EXTI_ELVR_LB12 *((volatile uint8_t *)(0x426001E4UL)) +#define bFM4_EXTI_ELVR_LB12 *((volatile uint8_t *)(0x426001E4UL)) +#define bFM_EXTI_ELVR_LA13 *((volatile uint8_t *)(0x426001E8UL)) +#define bFM4_EXTI_ELVR_LA13 *((volatile uint8_t *)(0x426001E8UL)) +#define bFM_EXTI_ELVR_LB13 *((volatile uint8_t *)(0x426001ECUL)) +#define bFM4_EXTI_ELVR_LB13 *((volatile uint8_t *)(0x426001ECUL)) +#define bFM_EXTI_ELVR_LA14 *((volatile uint8_t *)(0x426001F0UL)) +#define bFM4_EXTI_ELVR_LA14 *((volatile uint8_t *)(0x426001F0UL)) +#define bFM_EXTI_ELVR_LB14 *((volatile uint8_t *)(0x426001F4UL)) +#define bFM4_EXTI_ELVR_LB14 *((volatile uint8_t *)(0x426001F4UL)) +#define bFM_EXTI_ELVR_LA15 *((volatile uint8_t *)(0x426001F8UL)) +#define bFM4_EXTI_ELVR_LA15 *((volatile uint8_t *)(0x426001F8UL)) +#define bFM_EXTI_ELVR_LB15 *((volatile uint8_t *)(0x426001FCUL)) +#define bFM4_EXTI_ELVR_LB15 *((volatile uint8_t *)(0x426001FCUL)) + +#define bFM_EXTI_ELVR1_LA16 *((volatile uint8_t *)(0x42600200UL)) +#define bFM4_EXTI_ELVR1_LA16 *((volatile uint8_t *)(0x42600200UL)) +#define bFM_EXTI_ELVR1_LB16 *((volatile uint8_t *)(0x42600204UL)) +#define bFM4_EXTI_ELVR1_LB16 *((volatile uint8_t *)(0x42600204UL)) +#define bFM_EXTI_ELVR1_LA17 *((volatile uint8_t *)(0x42600208UL)) +#define bFM4_EXTI_ELVR1_LA17 *((volatile uint8_t *)(0x42600208UL)) +#define bFM_EXTI_ELVR1_LB17 *((volatile uint8_t *)(0x4260020CUL)) +#define bFM4_EXTI_ELVR1_LB17 *((volatile uint8_t *)(0x4260020CUL)) +#define bFM_EXTI_ELVR1_LA18 *((volatile uint8_t *)(0x42600210UL)) +#define bFM4_EXTI_ELVR1_LA18 *((volatile uint8_t *)(0x42600210UL)) +#define bFM_EXTI_ELVR1_LB18 *((volatile uint8_t *)(0x42600214UL)) +#define bFM4_EXTI_ELVR1_LB18 *((volatile uint8_t *)(0x42600214UL)) +#define bFM_EXTI_ELVR1_LA19 *((volatile uint8_t *)(0x42600218UL)) +#define bFM4_EXTI_ELVR1_LA19 *((volatile uint8_t *)(0x42600218UL)) +#define bFM_EXTI_ELVR1_LB19 *((volatile uint8_t *)(0x4260021CUL)) +#define bFM4_EXTI_ELVR1_LB19 *((volatile uint8_t *)(0x4260021CUL)) +#define bFM_EXTI_ELVR1_LA20 *((volatile uint8_t *)(0x42600220UL)) +#define bFM4_EXTI_ELVR1_LA20 *((volatile uint8_t *)(0x42600220UL)) +#define bFM_EXTI_ELVR1_LB20 *((volatile uint8_t *)(0x42600224UL)) +#define bFM4_EXTI_ELVR1_LB20 *((volatile uint8_t *)(0x42600224UL)) +#define bFM_EXTI_ELVR1_LA21 *((volatile uint8_t *)(0x42600228UL)) +#define bFM4_EXTI_ELVR1_LA21 *((volatile uint8_t *)(0x42600228UL)) +#define bFM_EXTI_ELVR1_LB21 *((volatile uint8_t *)(0x4260022CUL)) +#define bFM4_EXTI_ELVR1_LB21 *((volatile uint8_t *)(0x4260022CUL)) +#define bFM_EXTI_ELVR1_LA22 *((volatile uint8_t *)(0x42600230UL)) +#define bFM4_EXTI_ELVR1_LA22 *((volatile uint8_t *)(0x42600230UL)) +#define bFM_EXTI_ELVR1_LB22 *((volatile uint8_t *)(0x42600234UL)) +#define bFM4_EXTI_ELVR1_LB22 *((volatile uint8_t *)(0x42600234UL)) +#define bFM_EXTI_ELVR1_LA23 *((volatile uint8_t *)(0x42600238UL)) +#define bFM4_EXTI_ELVR1_LA23 *((volatile uint8_t *)(0x42600238UL)) +#define bFM_EXTI_ELVR1_LB23 *((volatile uint8_t *)(0x4260023CUL)) +#define bFM4_EXTI_ELVR1_LB23 *((volatile uint8_t *)(0x4260023CUL)) +#define bFM_EXTI_ELVR1_LA24 *((volatile uint8_t *)(0x42600240UL)) +#define bFM4_EXTI_ELVR1_LA24 *((volatile uint8_t *)(0x42600240UL)) +#define bFM_EXTI_ELVR1_LB24 *((volatile uint8_t *)(0x42600244UL)) +#define bFM4_EXTI_ELVR1_LB24 *((volatile uint8_t *)(0x42600244UL)) +#define bFM_EXTI_ELVR1_LA25 *((volatile uint8_t *)(0x42600248UL)) +#define bFM4_EXTI_ELVR1_LA25 *((volatile uint8_t *)(0x42600248UL)) +#define bFM_EXTI_ELVR1_LB25 *((volatile uint8_t *)(0x4260024CUL)) +#define bFM4_EXTI_ELVR1_LB25 *((volatile uint8_t *)(0x4260024CUL)) +#define bFM_EXTI_ELVR1_LA26 *((volatile uint8_t *)(0x42600250UL)) +#define bFM4_EXTI_ELVR1_LA26 *((volatile uint8_t *)(0x42600250UL)) +#define bFM_EXTI_ELVR1_LB26 *((volatile uint8_t *)(0x42600254UL)) +#define bFM4_EXTI_ELVR1_LB26 *((volatile uint8_t *)(0x42600254UL)) +#define bFM_EXTI_ELVR1_LA27 *((volatile uint8_t *)(0x42600258UL)) +#define bFM4_EXTI_ELVR1_LA27 *((volatile uint8_t *)(0x42600258UL)) +#define bFM_EXTI_ELVR1_LB27 *((volatile uint8_t *)(0x4260025CUL)) +#define bFM4_EXTI_ELVR1_LB27 *((volatile uint8_t *)(0x4260025CUL)) +#define bFM_EXTI_ELVR1_LA28 *((volatile uint8_t *)(0x42600260UL)) +#define bFM4_EXTI_ELVR1_LA28 *((volatile uint8_t *)(0x42600260UL)) +#define bFM_EXTI_ELVR1_LB28 *((volatile uint8_t *)(0x42600264UL)) +#define bFM4_EXTI_ELVR1_LB28 *((volatile uint8_t *)(0x42600264UL)) +#define bFM_EXTI_ELVR1_LA29 *((volatile uint8_t *)(0x42600268UL)) +#define bFM4_EXTI_ELVR1_LA29 *((volatile uint8_t *)(0x42600268UL)) +#define bFM_EXTI_ELVR1_LB29 *((volatile uint8_t *)(0x4260026CUL)) +#define bFM4_EXTI_ELVR1_LB29 *((volatile uint8_t *)(0x4260026CUL)) +#define bFM_EXTI_ELVR1_LA30 *((volatile uint8_t *)(0x42600270UL)) +#define bFM4_EXTI_ELVR1_LA30 *((volatile uint8_t *)(0x42600270UL)) +#define bFM_EXTI_ELVR1_LB30 *((volatile uint8_t *)(0x42600274UL)) +#define bFM4_EXTI_ELVR1_LB30 *((volatile uint8_t *)(0x42600274UL)) +#define bFM_EXTI_ELVR1_LA31 *((volatile uint8_t *)(0x42600278UL)) +#define bFM4_EXTI_ELVR1_LA31 *((volatile uint8_t *)(0x42600278UL)) +#define bFM_EXTI_ELVR1_LB31 *((volatile uint8_t *)(0x4260027CUL)) +#define bFM4_EXTI_ELVR1_LB31 *((volatile uint8_t *)(0x4260027CUL)) + +#define bFM_EXTI_ENIR_EN0 *((volatile uint8_t *)(0x42600000UL)) +#define bFM4_EXTI_ENIR_EN0 *((volatile uint8_t *)(0x42600000UL)) +#define bFM_EXTI_ENIR_EN1 *((volatile uint8_t *)(0x42600004UL)) +#define bFM4_EXTI_ENIR_EN1 *((volatile uint8_t *)(0x42600004UL)) +#define bFM_EXTI_ENIR_EN2 *((volatile uint8_t *)(0x42600008UL)) +#define bFM4_EXTI_ENIR_EN2 *((volatile uint8_t *)(0x42600008UL)) +#define bFM_EXTI_ENIR_EN3 *((volatile uint8_t *)(0x4260000CUL)) +#define bFM4_EXTI_ENIR_EN3 *((volatile uint8_t *)(0x4260000CUL)) +#define bFM_EXTI_ENIR_EN4 *((volatile uint8_t *)(0x42600010UL)) +#define bFM4_EXTI_ENIR_EN4 *((volatile uint8_t *)(0x42600010UL)) +#define bFM_EXTI_ENIR_EN5 *((volatile uint8_t *)(0x42600014UL)) +#define bFM4_EXTI_ENIR_EN5 *((volatile uint8_t *)(0x42600014UL)) +#define bFM_EXTI_ENIR_EN6 *((volatile uint8_t *)(0x42600018UL)) +#define bFM4_EXTI_ENIR_EN6 *((volatile uint8_t *)(0x42600018UL)) +#define bFM_EXTI_ENIR_EN7 *((volatile uint8_t *)(0x4260001CUL)) +#define bFM4_EXTI_ENIR_EN7 *((volatile uint8_t *)(0x4260001CUL)) +#define bFM_EXTI_ENIR_EN8 *((volatile uint8_t *)(0x42600020UL)) +#define bFM4_EXTI_ENIR_EN8 *((volatile uint8_t *)(0x42600020UL)) +#define bFM_EXTI_ENIR_EN9 *((volatile uint8_t *)(0x42600024UL)) +#define bFM4_EXTI_ENIR_EN9 *((volatile uint8_t *)(0x42600024UL)) +#define bFM_EXTI_ENIR_EN10 *((volatile uint8_t *)(0x42600028UL)) +#define bFM4_EXTI_ENIR_EN10 *((volatile uint8_t *)(0x42600028UL)) +#define bFM_EXTI_ENIR_EN11 *((volatile uint8_t *)(0x4260002CUL)) +#define bFM4_EXTI_ENIR_EN11 *((volatile uint8_t *)(0x4260002CUL)) +#define bFM_EXTI_ENIR_EN12 *((volatile uint8_t *)(0x42600030UL)) +#define bFM4_EXTI_ENIR_EN12 *((volatile uint8_t *)(0x42600030UL)) +#define bFM_EXTI_ENIR_EN13 *((volatile uint8_t *)(0x42600034UL)) +#define bFM4_EXTI_ENIR_EN13 *((volatile uint8_t *)(0x42600034UL)) +#define bFM_EXTI_ENIR_EN14 *((volatile uint8_t *)(0x42600038UL)) +#define bFM4_EXTI_ENIR_EN14 *((volatile uint8_t *)(0x42600038UL)) +#define bFM_EXTI_ENIR_EN15 *((volatile uint8_t *)(0x4260003CUL)) +#define bFM4_EXTI_ENIR_EN15 *((volatile uint8_t *)(0x4260003CUL)) +#define bFM_EXTI_ENIR_EN16 *((volatile uint8_t *)(0x42600040UL)) +#define bFM4_EXTI_ENIR_EN16 *((volatile uint8_t *)(0x42600040UL)) +#define bFM_EXTI_ENIR_EN17 *((volatile uint8_t *)(0x42600044UL)) +#define bFM4_EXTI_ENIR_EN17 *((volatile uint8_t *)(0x42600044UL)) +#define bFM_EXTI_ENIR_EN18 *((volatile uint8_t *)(0x42600048UL)) +#define bFM4_EXTI_ENIR_EN18 *((volatile uint8_t *)(0x42600048UL)) +#define bFM_EXTI_ENIR_EN19 *((volatile uint8_t *)(0x4260004CUL)) +#define bFM4_EXTI_ENIR_EN19 *((volatile uint8_t *)(0x4260004CUL)) +#define bFM_EXTI_ENIR_EN20 *((volatile uint8_t *)(0x42600050UL)) +#define bFM4_EXTI_ENIR_EN20 *((volatile uint8_t *)(0x42600050UL)) +#define bFM_EXTI_ENIR_EN21 *((volatile uint8_t *)(0x42600054UL)) +#define bFM4_EXTI_ENIR_EN21 *((volatile uint8_t *)(0x42600054UL)) +#define bFM_EXTI_ENIR_EN22 *((volatile uint8_t *)(0x42600058UL)) +#define bFM4_EXTI_ENIR_EN22 *((volatile uint8_t *)(0x42600058UL)) +#define bFM_EXTI_ENIR_EN23 *((volatile uint8_t *)(0x4260005CUL)) +#define bFM4_EXTI_ENIR_EN23 *((volatile uint8_t *)(0x4260005CUL)) +#define bFM_EXTI_ENIR_EN24 *((volatile uint8_t *)(0x42600060UL)) +#define bFM4_EXTI_ENIR_EN24 *((volatile uint8_t *)(0x42600060UL)) +#define bFM_EXTI_ENIR_EN25 *((volatile uint8_t *)(0x42600064UL)) +#define bFM4_EXTI_ENIR_EN25 *((volatile uint8_t *)(0x42600064UL)) +#define bFM_EXTI_ENIR_EN26 *((volatile uint8_t *)(0x42600068UL)) +#define bFM4_EXTI_ENIR_EN26 *((volatile uint8_t *)(0x42600068UL)) +#define bFM_EXTI_ENIR_EN27 *((volatile uint8_t *)(0x4260006CUL)) +#define bFM4_EXTI_ENIR_EN27 *((volatile uint8_t *)(0x4260006CUL)) +#define bFM_EXTI_ENIR_EN28 *((volatile uint8_t *)(0x42600070UL)) +#define bFM4_EXTI_ENIR_EN28 *((volatile uint8_t *)(0x42600070UL)) +#define bFM_EXTI_ENIR_EN29 *((volatile uint8_t *)(0x42600074UL)) +#define bFM4_EXTI_ENIR_EN29 *((volatile uint8_t *)(0x42600074UL)) +#define bFM_EXTI_ENIR_EN30 *((volatile uint8_t *)(0x42600078UL)) +#define bFM4_EXTI_ENIR_EN30 *((volatile uint8_t *)(0x42600078UL)) +#define bFM_EXTI_ENIR_EN31 *((volatile uint8_t *)(0x4260007CUL)) +#define bFM4_EXTI_ENIR_EN31 *((volatile uint8_t *)(0x4260007CUL)) + +#define bFM_EXTI_NMICL_NCL *((volatile uint8_t *)(0x42600300UL)) +#define bFM4_EXTI_NMICL_NCL *((volatile uint8_t *)(0x42600300UL)) + +#define bFM_EXTI_NMIRR_NR *((volatile uint8_t *)(0x42600280UL)) +#define bFM4_EXTI_NMIRR_NR *((volatile uint8_t *)(0x42600280UL)) + + +/******************************************************************************* +* FLASH_IF Registers FLASH_IF +* Bitband Section +*******************************************************************************/ +#define bFM_FLASH_IF_DFCTRLR_DFE *((volatile uint32_t*)(0x42000600UL)) +#define bFM4_FLASH_IF_DFCTRLR_DFE *((volatile uint32_t*)(0x42000600UL)) +#define bFM_FLASH_IF_DFCTRLR_RME *((volatile uint32_t*)(0x42000604UL)) +#define bFM4_FLASH_IF_DFCTRLR_RME *((volatile uint32_t*)(0x42000604UL)) + +#define bFM_FLASH_IF_FBFCR_BE *((volatile uint8_t *)(0x42000280UL)) +#define bFM4_FLASH_IF_FBFCR_BE *((volatile uint8_t *)(0x42000280UL)) +#define bFM_FLASH_IF_FBFCR_BS *((volatile uint8_t *)(0x42000284UL)) +#define bFM4_FLASH_IF_FBFCR_BS *((volatile uint8_t *)(0x42000284UL)) + +#define bFM_FLASH_IF_FICLR_RDYIC *((volatile uint8_t *)(0x42000500UL)) +#define bFM4_FLASH_IF_FICLR_RDYIC *((volatile uint8_t *)(0x42000500UL)) +#define bFM_FLASH_IF_FICLR_HNGIC *((volatile uint8_t *)(0x42000504UL)) +#define bFM4_FLASH_IF_FICLR_HNGIC *((volatile uint8_t *)(0x42000504UL)) +#define bFM_FLASH_IF_FICLR_ERRIC *((volatile uint8_t *)(0x42000508UL)) +#define bFM4_FLASH_IF_FICLR_ERRIC *((volatile uint8_t *)(0x42000508UL)) + +#define bFM_FLASH_IF_FICR_RDYIE *((volatile uint8_t *)(0x42000400UL)) +#define bFM4_FLASH_IF_FICR_RDYIE *((volatile uint8_t *)(0x42000400UL)) +#define bFM_FLASH_IF_FICR_HNGIE *((volatile uint8_t *)(0x42000404UL)) +#define bFM4_FLASH_IF_FICR_HNGIE *((volatile uint8_t *)(0x42000404UL)) +#define bFM_FLASH_IF_FICR_ERRIE *((volatile uint8_t *)(0x42000408UL)) +#define bFM4_FLASH_IF_FICR_ERRIE *((volatile uint8_t *)(0x42000408UL)) + +#define bFM_FLASH_IF_FISR_RDYIF *((volatile uint8_t *)(0x42000480UL)) +#define bFM4_FLASH_IF_FISR_RDYIF *((volatile uint8_t *)(0x42000480UL)) +#define bFM_FLASH_IF_FISR_HNGIF *((volatile uint8_t *)(0x42000484UL)) +#define bFM4_FLASH_IF_FISR_HNGIF *((volatile uint8_t *)(0x42000484UL)) +#define bFM_FLASH_IF_FISR_ERRIF *((volatile uint8_t *)(0x42000488UL)) +#define bFM4_FLASH_IF_FISR_ERRIF *((volatile uint8_t *)(0x42000488UL)) + +#define bFM_FLASH_IF_FSTR_RDY *((volatile uint8_t *)(0x42000100UL)) +#define bFM4_FLASH_IF_FSTR_RDY *((volatile uint8_t *)(0x42000100UL)) +#define bFM_FLASH_IF_FSTR_HNG *((volatile uint8_t *)(0x42000104UL)) +#define bFM4_FLASH_IF_FSTR_HNG *((volatile uint8_t *)(0x42000104UL)) +#define bFM_FLASH_IF_FSTR_ERR *((volatile uint8_t *)(0x42000108UL)) +#define bFM4_FLASH_IF_FSTR_ERR *((volatile uint8_t *)(0x42000108UL)) + + +/******************************************************************************* +* GPIO Registers GPIO +* Bitband Section +*******************************************************************************/ +#define bFM_GPIO_ADE_AN00 *((volatile uint8_t *)(0x42DEA000UL)) +#define bFM4_GPIO_ADE_AN00 *((volatile uint8_t *)(0x42DEA000UL)) +#define bFM_GPIO_ADE_AN01 *((volatile uint8_t *)(0x42DEA004UL)) +#define bFM4_GPIO_ADE_AN01 *((volatile uint8_t *)(0x42DEA004UL)) +#define bFM_GPIO_ADE_AN02 *((volatile uint8_t *)(0x42DEA008UL)) +#define bFM4_GPIO_ADE_AN02 *((volatile uint8_t *)(0x42DEA008UL)) +#define bFM_GPIO_ADE_AN03 *((volatile uint8_t *)(0x42DEA00CUL)) +#define bFM4_GPIO_ADE_AN03 *((volatile uint8_t *)(0x42DEA00CUL)) +#define bFM_GPIO_ADE_AN04 *((volatile uint8_t *)(0x42DEA010UL)) +#define bFM4_GPIO_ADE_AN04 *((volatile uint8_t *)(0x42DEA010UL)) +#define bFM_GPIO_ADE_AN05 *((volatile uint8_t *)(0x42DEA014UL)) +#define bFM4_GPIO_ADE_AN05 *((volatile uint8_t *)(0x42DEA014UL)) +#define bFM_GPIO_ADE_AN06 *((volatile uint8_t *)(0x42DEA018UL)) +#define bFM4_GPIO_ADE_AN06 *((volatile uint8_t *)(0x42DEA018UL)) +#define bFM_GPIO_ADE_AN07 *((volatile uint8_t *)(0x42DEA01CUL)) +#define bFM4_GPIO_ADE_AN07 *((volatile uint8_t *)(0x42DEA01CUL)) +#define bFM_GPIO_ADE_AN08 *((volatile uint8_t *)(0x42DEA020UL)) +#define bFM4_GPIO_ADE_AN08 *((volatile uint8_t *)(0x42DEA020UL)) +#define bFM_GPIO_ADE_AN09 *((volatile uint8_t *)(0x42DEA024UL)) +#define bFM4_GPIO_ADE_AN09 *((volatile uint8_t *)(0x42DEA024UL)) +#define bFM_GPIO_ADE_AN10 *((volatile uint8_t *)(0x42DEA028UL)) +#define bFM4_GPIO_ADE_AN10 *((volatile uint8_t *)(0x42DEA028UL)) +#define bFM_GPIO_ADE_AN11 *((volatile uint8_t *)(0x42DEA02CUL)) +#define bFM4_GPIO_ADE_AN11 *((volatile uint8_t *)(0x42DEA02CUL)) +#define bFM_GPIO_ADE_AN12 *((volatile uint8_t *)(0x42DEA030UL)) +#define bFM4_GPIO_ADE_AN12 *((volatile uint8_t *)(0x42DEA030UL)) +#define bFM_GPIO_ADE_AN13 *((volatile uint8_t *)(0x42DEA034UL)) +#define bFM4_GPIO_ADE_AN13 *((volatile uint8_t *)(0x42DEA034UL)) +#define bFM_GPIO_ADE_AN14 *((volatile uint8_t *)(0x42DEA038UL)) +#define bFM4_GPIO_ADE_AN14 *((volatile uint8_t *)(0x42DEA038UL)) +#define bFM_GPIO_ADE_AN15 *((volatile uint8_t *)(0x42DEA03CUL)) +#define bFM4_GPIO_ADE_AN15 *((volatile uint8_t *)(0x42DEA03CUL)) +#define bFM_GPIO_ADE_AN16 *((volatile uint8_t *)(0x42DEA040UL)) +#define bFM4_GPIO_ADE_AN16 *((volatile uint8_t *)(0x42DEA040UL)) +#define bFM_GPIO_ADE_AN17 *((volatile uint8_t *)(0x42DEA044UL)) +#define bFM4_GPIO_ADE_AN17 *((volatile uint8_t *)(0x42DEA044UL)) +#define bFM_GPIO_ADE_AN18 *((volatile uint8_t *)(0x42DEA048UL)) +#define bFM4_GPIO_ADE_AN18 *((volatile uint8_t *)(0x42DEA048UL)) +#define bFM_GPIO_ADE_AN19 *((volatile uint8_t *)(0x42DEA04CUL)) +#define bFM4_GPIO_ADE_AN19 *((volatile uint8_t *)(0x42DEA04CUL)) +#define bFM_GPIO_ADE_AN20 *((volatile uint8_t *)(0x42DEA050UL)) +#define bFM4_GPIO_ADE_AN20 *((volatile uint8_t *)(0x42DEA050UL)) +#define bFM_GPIO_ADE_AN21 *((volatile uint8_t *)(0x42DEA054UL)) +#define bFM4_GPIO_ADE_AN21 *((volatile uint8_t *)(0x42DEA054UL)) +#define bFM_GPIO_ADE_AN22 *((volatile uint8_t *)(0x42DEA058UL)) +#define bFM4_GPIO_ADE_AN22 *((volatile uint8_t *)(0x42DEA058UL)) +#define bFM_GPIO_ADE_AN23 *((volatile uint8_t *)(0x42DEA05CUL)) +#define bFM4_GPIO_ADE_AN23 *((volatile uint8_t *)(0x42DEA05CUL)) +#define bFM_GPIO_ADE_AN24 *((volatile uint8_t *)(0x42DEA060UL)) +#define bFM4_GPIO_ADE_AN24 *((volatile uint8_t *)(0x42DEA060UL)) +#define bFM_GPIO_ADE_AN25 *((volatile uint8_t *)(0x42DEA064UL)) +#define bFM4_GPIO_ADE_AN25 *((volatile uint8_t *)(0x42DEA064UL)) +#define bFM_GPIO_ADE_AN26 *((volatile uint8_t *)(0x42DEA068UL)) +#define bFM4_GPIO_ADE_AN26 *((volatile uint8_t *)(0x42DEA068UL)) +#define bFM_GPIO_ADE_AN27 *((volatile uint8_t *)(0x42DEA06CUL)) +#define bFM4_GPIO_ADE_AN27 *((volatile uint8_t *)(0x42DEA06CUL)) +#define bFM_GPIO_ADE_AN28 *((volatile uint8_t *)(0x42DEA070UL)) +#define bFM4_GPIO_ADE_AN28 *((volatile uint8_t *)(0x42DEA070UL)) +#define bFM_GPIO_ADE_AN29 *((volatile uint8_t *)(0x42DEA074UL)) +#define bFM4_GPIO_ADE_AN29 *((volatile uint8_t *)(0x42DEA074UL)) +#define bFM_GPIO_ADE_AN30 *((volatile uint8_t *)(0x42DEA078UL)) +#define bFM4_GPIO_ADE_AN30 *((volatile uint8_t *)(0x42DEA078UL)) +#define bFM_GPIO_ADE_AN31 *((volatile uint8_t *)(0x42DEA07CUL)) +#define bFM4_GPIO_ADE_AN31 *((volatile uint8_t *)(0x42DEA07CUL)) + +#define bFM_GPIO_DDR0_P0 *((volatile uint8_t *)(0x42DE4000UL)) +#define bFM4_GPIO_DDR0_P0 *((volatile uint8_t *)(0x42DE4000UL)) +#define bFM_GPIO_DDR0_P1 *((volatile uint8_t *)(0x42DE4004UL)) +#define bFM4_GPIO_DDR0_P1 *((volatile uint8_t *)(0x42DE4004UL)) +#define bFM_GPIO_DDR0_P2 *((volatile uint8_t *)(0x42DE4008UL)) +#define bFM4_GPIO_DDR0_P2 *((volatile uint8_t *)(0x42DE4008UL)) +#define bFM_GPIO_DDR0_P3 *((volatile uint8_t *)(0x42DE400CUL)) +#define bFM4_GPIO_DDR0_P3 *((volatile uint8_t *)(0x42DE400CUL)) +#define bFM_GPIO_DDR0_P4 *((volatile uint8_t *)(0x42DE4010UL)) +#define bFM4_GPIO_DDR0_P4 *((volatile uint8_t *)(0x42DE4010UL)) +#define bFM_GPIO_DDR0_P8 *((volatile uint8_t *)(0x42DE4020UL)) +#define bFM4_GPIO_DDR0_P8 *((volatile uint8_t *)(0x42DE4020UL)) +#define bFM_GPIO_DDR0_P9 *((volatile uint8_t *)(0x42DE4024UL)) +#define bFM4_GPIO_DDR0_P9 *((volatile uint8_t *)(0x42DE4024UL)) +#define bFM_GPIO_DDR0_PA *((volatile uint8_t *)(0x42DE4028UL)) +#define bFM4_GPIO_DDR0_PA *((volatile uint8_t *)(0x42DE4028UL)) + +#define bFM_GPIO_DDR1_P0 *((volatile uint8_t *)(0x42DE4080UL)) +#define bFM4_GPIO_DDR1_P0 *((volatile uint8_t *)(0x42DE4080UL)) +#define bFM_GPIO_DDR1_P1 *((volatile uint8_t *)(0x42DE4084UL)) +#define bFM4_GPIO_DDR1_P1 *((volatile uint8_t *)(0x42DE4084UL)) +#define bFM_GPIO_DDR1_P2 *((volatile uint8_t *)(0x42DE4088UL)) +#define bFM4_GPIO_DDR1_P2 *((volatile uint8_t *)(0x42DE4088UL)) +#define bFM_GPIO_DDR1_P3 *((volatile uint8_t *)(0x42DE408CUL)) +#define bFM4_GPIO_DDR1_P3 *((volatile uint8_t *)(0x42DE408CUL)) +#define bFM_GPIO_DDR1_P4 *((volatile uint8_t *)(0x42DE4090UL)) +#define bFM4_GPIO_DDR1_P4 *((volatile uint8_t *)(0x42DE4090UL)) +#define bFM_GPIO_DDR1_P5 *((volatile uint8_t *)(0x42DE4094UL)) +#define bFM4_GPIO_DDR1_P5 *((volatile uint8_t *)(0x42DE4094UL)) +#define bFM_GPIO_DDR1_P6 *((volatile uint8_t *)(0x42DE4098UL)) +#define bFM4_GPIO_DDR1_P6 *((volatile uint8_t *)(0x42DE4098UL)) +#define bFM_GPIO_DDR1_P7 *((volatile uint8_t *)(0x42DE409CUL)) +#define bFM4_GPIO_DDR1_P7 *((volatile uint8_t *)(0x42DE409CUL)) +#define bFM_GPIO_DDR1_P8 *((volatile uint8_t *)(0x42DE40A0UL)) +#define bFM4_GPIO_DDR1_P8 *((volatile uint8_t *)(0x42DE40A0UL)) +#define bFM_GPIO_DDR1_P9 *((volatile uint8_t *)(0x42DE40A4UL)) +#define bFM4_GPIO_DDR1_P9 *((volatile uint8_t *)(0x42DE40A4UL)) +#define bFM_GPIO_DDR1_PA *((volatile uint8_t *)(0x42DE40A8UL)) +#define bFM4_GPIO_DDR1_PA *((volatile uint8_t *)(0x42DE40A8UL)) +#define bFM_GPIO_DDR1_PB *((volatile uint8_t *)(0x42DE40ACUL)) +#define bFM4_GPIO_DDR1_PB *((volatile uint8_t *)(0x42DE40ACUL)) +#define bFM_GPIO_DDR1_PC *((volatile uint8_t *)(0x42DE40B0UL)) +#define bFM4_GPIO_DDR1_PC *((volatile uint8_t *)(0x42DE40B0UL)) +#define bFM_GPIO_DDR1_PD *((volatile uint8_t *)(0x42DE40B4UL)) +#define bFM4_GPIO_DDR1_PD *((volatile uint8_t *)(0x42DE40B4UL)) +#define bFM_GPIO_DDR1_PE *((volatile uint8_t *)(0x42DE40B8UL)) +#define bFM4_GPIO_DDR1_PE *((volatile uint8_t *)(0x42DE40B8UL)) +#define bFM_GPIO_DDR1_PF *((volatile uint8_t *)(0x42DE40BCUL)) +#define bFM4_GPIO_DDR1_PF *((volatile uint8_t *)(0x42DE40BCUL)) + +#define bFM_GPIO_DDR2_P0 *((volatile uint8_t *)(0x42DE4100UL)) +#define bFM4_GPIO_DDR2_P0 *((volatile uint8_t *)(0x42DE4100UL)) +#define bFM_GPIO_DDR2_P1 *((volatile uint8_t *)(0x42DE4104UL)) +#define bFM4_GPIO_DDR2_P1 *((volatile uint8_t *)(0x42DE4104UL)) +#define bFM_GPIO_DDR2_P2 *((volatile uint8_t *)(0x42DE4108UL)) +#define bFM4_GPIO_DDR2_P2 *((volatile uint8_t *)(0x42DE4108UL)) +#define bFM_GPIO_DDR2_P3 *((volatile uint8_t *)(0x42DE410CUL)) +#define bFM4_GPIO_DDR2_P3 *((volatile uint8_t *)(0x42DE410CUL)) +#define bFM_GPIO_DDR2_P4 *((volatile uint8_t *)(0x42DE4110UL)) +#define bFM4_GPIO_DDR2_P4 *((volatile uint8_t *)(0x42DE4110UL)) +#define bFM_GPIO_DDR2_P5 *((volatile uint8_t *)(0x42DE4114UL)) +#define bFM4_GPIO_DDR2_P5 *((volatile uint8_t *)(0x42DE4114UL)) +#define bFM_GPIO_DDR2_P6 *((volatile uint8_t *)(0x42DE4118UL)) +#define bFM4_GPIO_DDR2_P6 *((volatile uint8_t *)(0x42DE4118UL)) +#define bFM_GPIO_DDR2_P7 *((volatile uint8_t *)(0x42DE411CUL)) +#define bFM4_GPIO_DDR2_P7 *((volatile uint8_t *)(0x42DE411CUL)) +#define bFM_GPIO_DDR2_P8 *((volatile uint8_t *)(0x42DE4120UL)) +#define bFM4_GPIO_DDR2_P8 *((volatile uint8_t *)(0x42DE4120UL)) +#define bFM_GPIO_DDR2_P9 *((volatile uint8_t *)(0x42DE4124UL)) +#define bFM4_GPIO_DDR2_P9 *((volatile uint8_t *)(0x42DE4124UL)) +#define bFM_GPIO_DDR2_PA *((volatile uint8_t *)(0x42DE4128UL)) +#define bFM4_GPIO_DDR2_PA *((volatile uint8_t *)(0x42DE4128UL)) + +#define bFM_GPIO_DDR3_P0 *((volatile uint8_t *)(0x42DE4180UL)) +#define bFM4_GPIO_DDR3_P0 *((volatile uint8_t *)(0x42DE4180UL)) +#define bFM_GPIO_DDR3_P1 *((volatile uint8_t *)(0x42DE4184UL)) +#define bFM4_GPIO_DDR3_P1 *((volatile uint8_t *)(0x42DE4184UL)) +#define bFM_GPIO_DDR3_P2 *((volatile uint8_t *)(0x42DE4188UL)) +#define bFM4_GPIO_DDR3_P2 *((volatile uint8_t *)(0x42DE4188UL)) +#define bFM_GPIO_DDR3_P3 *((volatile uint8_t *)(0x42DE418CUL)) +#define bFM4_GPIO_DDR3_P3 *((volatile uint8_t *)(0x42DE418CUL)) +#define bFM_GPIO_DDR3_P4 *((volatile uint8_t *)(0x42DE4190UL)) +#define bFM4_GPIO_DDR3_P4 *((volatile uint8_t *)(0x42DE4190UL)) +#define bFM_GPIO_DDR3_P5 *((volatile uint8_t *)(0x42DE4194UL)) +#define bFM4_GPIO_DDR3_P5 *((volatile uint8_t *)(0x42DE4194UL)) +#define bFM_GPIO_DDR3_P6 *((volatile uint8_t *)(0x42DE4198UL)) +#define bFM4_GPIO_DDR3_P6 *((volatile uint8_t *)(0x42DE4198UL)) +#define bFM_GPIO_DDR3_P7 *((volatile uint8_t *)(0x42DE419CUL)) +#define bFM4_GPIO_DDR3_P7 *((volatile uint8_t *)(0x42DE419CUL)) +#define bFM_GPIO_DDR3_P8 *((volatile uint8_t *)(0x42DE41A0UL)) +#define bFM4_GPIO_DDR3_P8 *((volatile uint8_t *)(0x42DE41A0UL)) +#define bFM_GPIO_DDR3_P9 *((volatile uint8_t *)(0x42DE41A4UL)) +#define bFM4_GPIO_DDR3_P9 *((volatile uint8_t *)(0x42DE41A4UL)) +#define bFM_GPIO_DDR3_PA *((volatile uint8_t *)(0x42DE41A8UL)) +#define bFM4_GPIO_DDR3_PA *((volatile uint8_t *)(0x42DE41A8UL)) +#define bFM_GPIO_DDR3_PB *((volatile uint8_t *)(0x42DE41ACUL)) +#define bFM4_GPIO_DDR3_PB *((volatile uint8_t *)(0x42DE41ACUL)) +#define bFM_GPIO_DDR3_PC *((volatile uint8_t *)(0x42DE41B0UL)) +#define bFM4_GPIO_DDR3_PC *((volatile uint8_t *)(0x42DE41B0UL)) +#define bFM_GPIO_DDR3_PD *((volatile uint8_t *)(0x42DE41B4UL)) +#define bFM4_GPIO_DDR3_PD *((volatile uint8_t *)(0x42DE41B4UL)) +#define bFM_GPIO_DDR3_PE *((volatile uint8_t *)(0x42DE41B8UL)) +#define bFM4_GPIO_DDR3_PE *((volatile uint8_t *)(0x42DE41B8UL)) + +#define bFM_GPIO_DDR4_P0 *((volatile uint8_t *)(0x42DE4200UL)) +#define bFM4_GPIO_DDR4_P0 *((volatile uint8_t *)(0x42DE4200UL)) +#define bFM_GPIO_DDR4_P1 *((volatile uint8_t *)(0x42DE4204UL)) +#define bFM4_GPIO_DDR4_P1 *((volatile uint8_t *)(0x42DE4204UL)) +#define bFM_GPIO_DDR4_P2 *((volatile uint8_t *)(0x42DE4208UL)) +#define bFM4_GPIO_DDR4_P2 *((volatile uint8_t *)(0x42DE4208UL)) +#define bFM_GPIO_DDR4_P3 *((volatile uint8_t *)(0x42DE420CUL)) +#define bFM4_GPIO_DDR4_P3 *((volatile uint8_t *)(0x42DE420CUL)) +#define bFM_GPIO_DDR4_P4 *((volatile uint8_t *)(0x42DE4210UL)) +#define bFM4_GPIO_DDR4_P4 *((volatile uint8_t *)(0x42DE4210UL)) +#define bFM_GPIO_DDR4_P5 *((volatile uint8_t *)(0x42DE4214UL)) +#define bFM4_GPIO_DDR4_P5 *((volatile uint8_t *)(0x42DE4214UL)) +#define bFM_GPIO_DDR4_P6 *((volatile uint8_t *)(0x42DE4218UL)) +#define bFM4_GPIO_DDR4_P6 *((volatile uint8_t *)(0x42DE4218UL)) +#define bFM_GPIO_DDR4_P7 *((volatile uint8_t *)(0x42DE421CUL)) +#define bFM4_GPIO_DDR4_P7 *((volatile uint8_t *)(0x42DE421CUL)) +#define bFM_GPIO_DDR4_P8 *((volatile uint8_t *)(0x42DE4220UL)) +#define bFM4_GPIO_DDR4_P8 *((volatile uint8_t *)(0x42DE4220UL)) +#define bFM_GPIO_DDR4_P9 *((volatile uint8_t *)(0x42DE4224UL)) +#define bFM4_GPIO_DDR4_P9 *((volatile uint8_t *)(0x42DE4224UL)) +#define bFM_GPIO_DDR4_PA *((volatile uint8_t *)(0x42DE4228UL)) +#define bFM4_GPIO_DDR4_PA *((volatile uint8_t *)(0x42DE4228UL)) +#define bFM_GPIO_DDR4_PB *((volatile uint8_t *)(0x42DE422CUL)) +#define bFM4_GPIO_DDR4_PB *((volatile uint8_t *)(0x42DE422CUL)) +#define bFM_GPIO_DDR4_PC *((volatile uint8_t *)(0x42DE4230UL)) +#define bFM4_GPIO_DDR4_PC *((volatile uint8_t *)(0x42DE4230UL)) +#define bFM_GPIO_DDR4_PD *((volatile uint8_t *)(0x42DE4234UL)) +#define bFM4_GPIO_DDR4_PD *((volatile uint8_t *)(0x42DE4234UL)) +#define bFM_GPIO_DDR4_PE *((volatile uint8_t *)(0x42DE4238UL)) +#define bFM4_GPIO_DDR4_PE *((volatile uint8_t *)(0x42DE4238UL)) + +#define bFM_GPIO_DDR5_P0 *((volatile uint8_t *)(0x42DE4280UL)) +#define bFM4_GPIO_DDR5_P0 *((volatile uint8_t *)(0x42DE4280UL)) +#define bFM_GPIO_DDR5_P1 *((volatile uint8_t *)(0x42DE4284UL)) +#define bFM4_GPIO_DDR5_P1 *((volatile uint8_t *)(0x42DE4284UL)) +#define bFM_GPIO_DDR5_P2 *((volatile uint8_t *)(0x42DE4288UL)) +#define bFM4_GPIO_DDR5_P2 *((volatile uint8_t *)(0x42DE4288UL)) +#define bFM_GPIO_DDR5_P3 *((volatile uint8_t *)(0x42DE428CUL)) +#define bFM4_GPIO_DDR5_P3 *((volatile uint8_t *)(0x42DE428CUL)) +#define bFM_GPIO_DDR5_P4 *((volatile uint8_t *)(0x42DE4290UL)) +#define bFM4_GPIO_DDR5_P4 *((volatile uint8_t *)(0x42DE4290UL)) +#define bFM_GPIO_DDR5_P5 *((volatile uint8_t *)(0x42DE4294UL)) +#define bFM4_GPIO_DDR5_P5 *((volatile uint8_t *)(0x42DE4294UL)) +#define bFM_GPIO_DDR5_P6 *((volatile uint8_t *)(0x42DE4298UL)) +#define bFM4_GPIO_DDR5_P6 *((volatile uint8_t *)(0x42DE4298UL)) +#define bFM_GPIO_DDR5_P7 *((volatile uint8_t *)(0x42DE429CUL)) +#define bFM4_GPIO_DDR5_P7 *((volatile uint8_t *)(0x42DE429CUL)) +#define bFM_GPIO_DDR5_P8 *((volatile uint8_t *)(0x42DE42A0UL)) +#define bFM4_GPIO_DDR5_P8 *((volatile uint8_t *)(0x42DE42A0UL)) +#define bFM_GPIO_DDR5_P9 *((volatile uint8_t *)(0x42DE42A4UL)) +#define bFM4_GPIO_DDR5_P9 *((volatile uint8_t *)(0x42DE42A4UL)) +#define bFM_GPIO_DDR5_PA *((volatile uint8_t *)(0x42DE42A8UL)) +#define bFM4_GPIO_DDR5_PA *((volatile uint8_t *)(0x42DE42A8UL)) +#define bFM_GPIO_DDR5_PB *((volatile uint8_t *)(0x42DE42ACUL)) +#define bFM4_GPIO_DDR5_PB *((volatile uint8_t *)(0x42DE42ACUL)) +#define bFM_GPIO_DDR5_PC *((volatile uint8_t *)(0x42DE42B0UL)) +#define bFM4_GPIO_DDR5_PC *((volatile uint8_t *)(0x42DE42B0UL)) +#define bFM_GPIO_DDR5_PD *((volatile uint8_t *)(0x42DE42B4UL)) +#define bFM4_GPIO_DDR5_PD *((volatile uint8_t *)(0x42DE42B4UL)) +#define bFM_GPIO_DDR5_PE *((volatile uint8_t *)(0x42DE42B8UL)) +#define bFM4_GPIO_DDR5_PE *((volatile uint8_t *)(0x42DE42B8UL)) +#define bFM_GPIO_DDR5_PF *((volatile uint8_t *)(0x42DE42BCUL)) +#define bFM4_GPIO_DDR5_PF *((volatile uint8_t *)(0x42DE42BCUL)) + +#define bFM_GPIO_DDR6_P0 *((volatile uint8_t *)(0x42DE4300UL)) +#define bFM4_GPIO_DDR6_P0 *((volatile uint8_t *)(0x42DE4300UL)) +#define bFM_GPIO_DDR6_P1 *((volatile uint8_t *)(0x42DE4304UL)) +#define bFM4_GPIO_DDR6_P1 *((volatile uint8_t *)(0x42DE4304UL)) +#define bFM_GPIO_DDR6_P2 *((volatile uint8_t *)(0x42DE4308UL)) +#define bFM4_GPIO_DDR6_P2 *((volatile uint8_t *)(0x42DE4308UL)) +#define bFM_GPIO_DDR6_P3 *((volatile uint8_t *)(0x42DE430CUL)) +#define bFM4_GPIO_DDR6_P3 *((volatile uint8_t *)(0x42DE430CUL)) +#define bFM_GPIO_DDR6_P4 *((volatile uint8_t *)(0x42DE4310UL)) +#define bFM4_GPIO_DDR6_P4 *((volatile uint8_t *)(0x42DE4310UL)) +#define bFM_GPIO_DDR6_P5 *((volatile uint8_t *)(0x42DE4314UL)) +#define bFM4_GPIO_DDR6_P5 *((volatile uint8_t *)(0x42DE4314UL)) +#define bFM_GPIO_DDR6_P6 *((volatile uint8_t *)(0x42DE4318UL)) +#define bFM4_GPIO_DDR6_P6 *((volatile uint8_t *)(0x42DE4318UL)) +#define bFM_GPIO_DDR6_P7 *((volatile uint8_t *)(0x42DE431CUL)) +#define bFM4_GPIO_DDR6_P7 *((volatile uint8_t *)(0x42DE431CUL)) +#define bFM_GPIO_DDR6_P8 *((volatile uint8_t *)(0x42DE4320UL)) +#define bFM4_GPIO_DDR6_P8 *((volatile uint8_t *)(0x42DE4320UL)) +#define bFM_GPIO_DDR6_P9 *((volatile uint8_t *)(0x42DE4324UL)) +#define bFM4_GPIO_DDR6_P9 *((volatile uint8_t *)(0x42DE4324UL)) +#define bFM_GPIO_DDR6_PA *((volatile uint8_t *)(0x42DE4328UL)) +#define bFM4_GPIO_DDR6_PA *((volatile uint8_t *)(0x42DE4328UL)) +#define bFM_GPIO_DDR6_PB *((volatile uint8_t *)(0x42DE432CUL)) +#define bFM4_GPIO_DDR6_PB *((volatile uint8_t *)(0x42DE432CUL)) +#define bFM_GPIO_DDR6_PC *((volatile uint8_t *)(0x42DE4330UL)) +#define bFM4_GPIO_DDR6_PC *((volatile uint8_t *)(0x42DE4330UL)) +#define bFM_GPIO_DDR6_PD *((volatile uint8_t *)(0x42DE4334UL)) +#define bFM4_GPIO_DDR6_PD *((volatile uint8_t *)(0x42DE4334UL)) +#define bFM_GPIO_DDR6_PE *((volatile uint8_t *)(0x42DE4338UL)) +#define bFM4_GPIO_DDR6_PE *((volatile uint8_t *)(0x42DE4338UL)) + +#define bFM_GPIO_DDR7_P0 *((volatile uint8_t *)(0x42DE4380UL)) +#define bFM4_GPIO_DDR7_P0 *((volatile uint8_t *)(0x42DE4380UL)) +#define bFM_GPIO_DDR7_P1 *((volatile uint8_t *)(0x42DE4384UL)) +#define bFM4_GPIO_DDR7_P1 *((volatile uint8_t *)(0x42DE4384UL)) +#define bFM_GPIO_DDR7_P2 *((volatile uint8_t *)(0x42DE4388UL)) +#define bFM4_GPIO_DDR7_P2 *((volatile uint8_t *)(0x42DE4388UL)) +#define bFM_GPIO_DDR7_P3 *((volatile uint8_t *)(0x42DE438CUL)) +#define bFM4_GPIO_DDR7_P3 *((volatile uint8_t *)(0x42DE438CUL)) +#define bFM_GPIO_DDR7_P4 *((volatile uint8_t *)(0x42DE4390UL)) +#define bFM4_GPIO_DDR7_P4 *((volatile uint8_t *)(0x42DE4390UL)) +#define bFM_GPIO_DDR7_P5 *((volatile uint8_t *)(0x42DE4394UL)) +#define bFM4_GPIO_DDR7_P5 *((volatile uint8_t *)(0x42DE4394UL)) +#define bFM_GPIO_DDR7_P6 *((volatile uint8_t *)(0x42DE4398UL)) +#define bFM4_GPIO_DDR7_P6 *((volatile uint8_t *)(0x42DE4398UL)) +#define bFM_GPIO_DDR7_P7 *((volatile uint8_t *)(0x42DE439CUL)) +#define bFM4_GPIO_DDR7_P7 *((volatile uint8_t *)(0x42DE439CUL)) +#define bFM_GPIO_DDR7_P8 *((volatile uint8_t *)(0x42DE43A0UL)) +#define bFM4_GPIO_DDR7_P8 *((volatile uint8_t *)(0x42DE43A0UL)) +#define bFM_GPIO_DDR7_P9 *((volatile uint8_t *)(0x42DE43A4UL)) +#define bFM4_GPIO_DDR7_P9 *((volatile uint8_t *)(0x42DE43A4UL)) +#define bFM_GPIO_DDR7_PA *((volatile uint8_t *)(0x42DE43A8UL)) +#define bFM4_GPIO_DDR7_PA *((volatile uint8_t *)(0x42DE43A8UL)) +#define bFM_GPIO_DDR7_PB *((volatile uint8_t *)(0x42DE43ACUL)) +#define bFM4_GPIO_DDR7_PB *((volatile uint8_t *)(0x42DE43ACUL)) +#define bFM_GPIO_DDR7_PC *((volatile uint8_t *)(0x42DE43B0UL)) +#define bFM4_GPIO_DDR7_PC *((volatile uint8_t *)(0x42DE43B0UL)) +#define bFM_GPIO_DDR7_PD *((volatile uint8_t *)(0x42DE43B4UL)) +#define bFM4_GPIO_DDR7_PD *((volatile uint8_t *)(0x42DE43B4UL)) +#define bFM_GPIO_DDR7_PE *((volatile uint8_t *)(0x42DE43B8UL)) +#define bFM4_GPIO_DDR7_PE *((volatile uint8_t *)(0x42DE43B8UL)) + +#define bFM_GPIO_DDR8_P0 *((volatile uint8_t *)(0x42DE4400UL)) +#define bFM4_GPIO_DDR8_P0 *((volatile uint8_t *)(0x42DE4400UL)) +#define bFM_GPIO_DDR8_P1 *((volatile uint8_t *)(0x42DE4404UL)) +#define bFM4_GPIO_DDR8_P1 *((volatile uint8_t *)(0x42DE4404UL)) +#define bFM_GPIO_DDR8_P2 *((volatile uint8_t *)(0x42DE4408UL)) +#define bFM4_GPIO_DDR8_P2 *((volatile uint8_t *)(0x42DE4408UL)) +#define bFM_GPIO_DDR8_P3 *((volatile uint8_t *)(0x42DE440CUL)) +#define bFM4_GPIO_DDR8_P3 *((volatile uint8_t *)(0x42DE440CUL)) + +#define bFM_GPIO_DDR9_P0 *((volatile uint8_t *)(0x42DE4480UL)) +#define bFM4_GPIO_DDR9_P0 *((volatile uint8_t *)(0x42DE4480UL)) +#define bFM_GPIO_DDR9_P1 *((volatile uint8_t *)(0x42DE4484UL)) +#define bFM4_GPIO_DDR9_P1 *((volatile uint8_t *)(0x42DE4484UL)) +#define bFM_GPIO_DDR9_P2 *((volatile uint8_t *)(0x42DE4488UL)) +#define bFM4_GPIO_DDR9_P2 *((volatile uint8_t *)(0x42DE4488UL)) +#define bFM_GPIO_DDR9_P3 *((volatile uint8_t *)(0x42DE448CUL)) +#define bFM4_GPIO_DDR9_P3 *((volatile uint8_t *)(0x42DE448CUL)) +#define bFM_GPIO_DDR9_P4 *((volatile uint8_t *)(0x42DE4490UL)) +#define bFM4_GPIO_DDR9_P4 *((volatile uint8_t *)(0x42DE4490UL)) +#define bFM_GPIO_DDR9_P5 *((volatile uint8_t *)(0x42DE4494UL)) +#define bFM4_GPIO_DDR9_P5 *((volatile uint8_t *)(0x42DE4494UL)) +#define bFM_GPIO_DDR9_P6 *((volatile uint8_t *)(0x42DE4498UL)) +#define bFM4_GPIO_DDR9_P6 *((volatile uint8_t *)(0x42DE4498UL)) +#define bFM_GPIO_DDR9_P7 *((volatile uint8_t *)(0x42DE449CUL)) +#define bFM4_GPIO_DDR9_P7 *((volatile uint8_t *)(0x42DE449CUL)) + +#define bFM_GPIO_DDRA_P0 *((volatile uint8_t *)(0x42DE4500UL)) +#define bFM4_GPIO_DDRA_P0 *((volatile uint8_t *)(0x42DE4500UL)) +#define bFM_GPIO_DDRA_P1 *((volatile uint8_t *)(0x42DE4504UL)) +#define bFM4_GPIO_DDRA_P1 *((volatile uint8_t *)(0x42DE4504UL)) +#define bFM_GPIO_DDRA_P2 *((volatile uint8_t *)(0x42DE4508UL)) +#define bFM4_GPIO_DDRA_P2 *((volatile uint8_t *)(0x42DE4508UL)) +#define bFM_GPIO_DDRA_P3 *((volatile uint8_t *)(0x42DE450CUL)) +#define bFM4_GPIO_DDRA_P3 *((volatile uint8_t *)(0x42DE450CUL)) +#define bFM_GPIO_DDRA_P4 *((volatile uint8_t *)(0x42DE4510UL)) +#define bFM4_GPIO_DDRA_P4 *((volatile uint8_t *)(0x42DE4510UL)) +#define bFM_GPIO_DDRA_P5 *((volatile uint8_t *)(0x42DE4514UL)) +#define bFM4_GPIO_DDRA_P5 *((volatile uint8_t *)(0x42DE4514UL)) +#define bFM_GPIO_DDRA_P6 *((volatile uint8_t *)(0x42DE4518UL)) +#define bFM4_GPIO_DDRA_P6 *((volatile uint8_t *)(0x42DE4518UL)) +#define bFM_GPIO_DDRA_P7 *((volatile uint8_t *)(0x42DE451CUL)) +#define bFM4_GPIO_DDRA_P7 *((volatile uint8_t *)(0x42DE451CUL)) +#define bFM_GPIO_DDRA_P8 *((volatile uint8_t *)(0x42DE4520UL)) +#define bFM4_GPIO_DDRA_P8 *((volatile uint8_t *)(0x42DE4520UL)) +#define bFM_GPIO_DDRA_P9 *((volatile uint8_t *)(0x42DE4524UL)) +#define bFM4_GPIO_DDRA_P9 *((volatile uint8_t *)(0x42DE4524UL)) +#define bFM_GPIO_DDRA_PA *((volatile uint8_t *)(0x42DE4528UL)) +#define bFM4_GPIO_DDRA_PA *((volatile uint8_t *)(0x42DE4528UL)) +#define bFM_GPIO_DDRA_PB *((volatile uint8_t *)(0x42DE452CUL)) +#define bFM4_GPIO_DDRA_PB *((volatile uint8_t *)(0x42DE452CUL)) +#define bFM_GPIO_DDRA_PC *((volatile uint8_t *)(0x42DE4530UL)) +#define bFM4_GPIO_DDRA_PC *((volatile uint8_t *)(0x42DE4530UL)) +#define bFM_GPIO_DDRA_PD *((volatile uint8_t *)(0x42DE4534UL)) +#define bFM4_GPIO_DDRA_PD *((volatile uint8_t *)(0x42DE4534UL)) +#define bFM_GPIO_DDRA_PE *((volatile uint8_t *)(0x42DE4538UL)) +#define bFM4_GPIO_DDRA_PE *((volatile uint8_t *)(0x42DE4538UL)) +#define bFM_GPIO_DDRA_PF *((volatile uint8_t *)(0x42DE453CUL)) +#define bFM4_GPIO_DDRA_PF *((volatile uint8_t *)(0x42DE453CUL)) + +#define bFM_GPIO_DDRB_P0 *((volatile uint8_t *)(0x42DE4580UL)) +#define bFM4_GPIO_DDRB_P0 *((volatile uint8_t *)(0x42DE4580UL)) +#define bFM_GPIO_DDRB_P1 *((volatile uint8_t *)(0x42DE4584UL)) +#define bFM4_GPIO_DDRB_P1 *((volatile uint8_t *)(0x42DE4584UL)) +#define bFM_GPIO_DDRB_P2 *((volatile uint8_t *)(0x42DE4588UL)) +#define bFM4_GPIO_DDRB_P2 *((volatile uint8_t *)(0x42DE4588UL)) +#define bFM_GPIO_DDRB_P3 *((volatile uint8_t *)(0x42DE458CUL)) +#define bFM4_GPIO_DDRB_P3 *((volatile uint8_t *)(0x42DE458CUL)) +#define bFM_GPIO_DDRB_P4 *((volatile uint8_t *)(0x42DE4590UL)) +#define bFM4_GPIO_DDRB_P4 *((volatile uint8_t *)(0x42DE4590UL)) +#define bFM_GPIO_DDRB_P5 *((volatile uint8_t *)(0x42DE4594UL)) +#define bFM4_GPIO_DDRB_P5 *((volatile uint8_t *)(0x42DE4594UL)) +#define bFM_GPIO_DDRB_P6 *((volatile uint8_t *)(0x42DE4598UL)) +#define bFM4_GPIO_DDRB_P6 *((volatile uint8_t *)(0x42DE4598UL)) +#define bFM_GPIO_DDRB_P7 *((volatile uint8_t *)(0x42DE459CUL)) +#define bFM4_GPIO_DDRB_P7 *((volatile uint8_t *)(0x42DE459CUL)) +#define bFM_GPIO_DDRB_P8 *((volatile uint8_t *)(0x42DE45A0UL)) +#define bFM4_GPIO_DDRB_P8 *((volatile uint8_t *)(0x42DE45A0UL)) +#define bFM_GPIO_DDRB_P9 *((volatile uint8_t *)(0x42DE45A4UL)) +#define bFM4_GPIO_DDRB_P9 *((volatile uint8_t *)(0x42DE45A4UL)) +#define bFM_GPIO_DDRB_PA *((volatile uint8_t *)(0x42DE45A8UL)) +#define bFM4_GPIO_DDRB_PA *((volatile uint8_t *)(0x42DE45A8UL)) +#define bFM_GPIO_DDRB_PB *((volatile uint8_t *)(0x42DE45ACUL)) +#define bFM4_GPIO_DDRB_PB *((volatile uint8_t *)(0x42DE45ACUL)) +#define bFM_GPIO_DDRB_PC *((volatile uint8_t *)(0x42DE45B0UL)) +#define bFM4_GPIO_DDRB_PC *((volatile uint8_t *)(0x42DE45B0UL)) +#define bFM_GPIO_DDRB_PD *((volatile uint8_t *)(0x42DE45B4UL)) +#define bFM4_GPIO_DDRB_PD *((volatile uint8_t *)(0x42DE45B4UL)) +#define bFM_GPIO_DDRB_PE *((volatile uint8_t *)(0x42DE45B8UL)) +#define bFM4_GPIO_DDRB_PE *((volatile uint8_t *)(0x42DE45B8UL)) +#define bFM_GPIO_DDRB_PF *((volatile uint8_t *)(0x42DE45BCUL)) +#define bFM4_GPIO_DDRB_PF *((volatile uint8_t *)(0x42DE45BCUL)) + +#define bFM_GPIO_DDRC_P0 *((volatile uint8_t *)(0x42DE4600UL)) +#define bFM4_GPIO_DDRC_P0 *((volatile uint8_t *)(0x42DE4600UL)) +#define bFM_GPIO_DDRC_P1 *((volatile uint8_t *)(0x42DE4604UL)) +#define bFM4_GPIO_DDRC_P1 *((volatile uint8_t *)(0x42DE4604UL)) +#define bFM_GPIO_DDRC_P2 *((volatile uint8_t *)(0x42DE4608UL)) +#define bFM4_GPIO_DDRC_P2 *((volatile uint8_t *)(0x42DE4608UL)) +#define bFM_GPIO_DDRC_P3 *((volatile uint8_t *)(0x42DE460CUL)) +#define bFM4_GPIO_DDRC_P3 *((volatile uint8_t *)(0x42DE460CUL)) +#define bFM_GPIO_DDRC_P4 *((volatile uint8_t *)(0x42DE4610UL)) +#define bFM4_GPIO_DDRC_P4 *((volatile uint8_t *)(0x42DE4610UL)) +#define bFM_GPIO_DDRC_P5 *((volatile uint8_t *)(0x42DE4614UL)) +#define bFM4_GPIO_DDRC_P5 *((volatile uint8_t *)(0x42DE4614UL)) +#define bFM_GPIO_DDRC_P6 *((volatile uint8_t *)(0x42DE4618UL)) +#define bFM4_GPIO_DDRC_P6 *((volatile uint8_t *)(0x42DE4618UL)) +#define bFM_GPIO_DDRC_P7 *((volatile uint8_t *)(0x42DE461CUL)) +#define bFM4_GPIO_DDRC_P7 *((volatile uint8_t *)(0x42DE461CUL)) +#define bFM_GPIO_DDRC_P8 *((volatile uint8_t *)(0x42DE4620UL)) +#define bFM4_GPIO_DDRC_P8 *((volatile uint8_t *)(0x42DE4620UL)) +#define bFM_GPIO_DDRC_P9 *((volatile uint8_t *)(0x42DE4624UL)) +#define bFM4_GPIO_DDRC_P9 *((volatile uint8_t *)(0x42DE4624UL)) +#define bFM_GPIO_DDRC_PA *((volatile uint8_t *)(0x42DE4628UL)) +#define bFM4_GPIO_DDRC_PA *((volatile uint8_t *)(0x42DE4628UL)) +#define bFM_GPIO_DDRC_PB *((volatile uint8_t *)(0x42DE462CUL)) +#define bFM4_GPIO_DDRC_PB *((volatile uint8_t *)(0x42DE462CUL)) +#define bFM_GPIO_DDRC_PC *((volatile uint8_t *)(0x42DE4630UL)) +#define bFM4_GPIO_DDRC_PC *((volatile uint8_t *)(0x42DE4630UL)) +#define bFM_GPIO_DDRC_PD *((volatile uint8_t *)(0x42DE4634UL)) +#define bFM4_GPIO_DDRC_PD *((volatile uint8_t *)(0x42DE4634UL)) +#define bFM_GPIO_DDRC_PE *((volatile uint8_t *)(0x42DE4638UL)) +#define bFM4_GPIO_DDRC_PE *((volatile uint8_t *)(0x42DE4638UL)) +#define bFM_GPIO_DDRC_PF *((volatile uint8_t *)(0x42DE463CUL)) +#define bFM4_GPIO_DDRC_PF *((volatile uint8_t *)(0x42DE463CUL)) + +#define bFM_GPIO_DDRD_P0 *((volatile uint8_t *)(0x42DE4680UL)) +#define bFM4_GPIO_DDRD_P0 *((volatile uint8_t *)(0x42DE4680UL)) +#define bFM_GPIO_DDRD_P1 *((volatile uint8_t *)(0x42DE4684UL)) +#define bFM4_GPIO_DDRD_P1 *((volatile uint8_t *)(0x42DE4684UL)) +#define bFM_GPIO_DDRD_P2 *((volatile uint8_t *)(0x42DE4688UL)) +#define bFM4_GPIO_DDRD_P2 *((volatile uint8_t *)(0x42DE4688UL)) + +#define bFM_GPIO_DDRE_P0 *((volatile uint8_t *)(0x42DE4700UL)) +#define bFM4_GPIO_DDRE_P0 *((volatile uint8_t *)(0x42DE4700UL)) +#define bFM_GPIO_DDRE_P2 *((volatile uint8_t *)(0x42DE4708UL)) +#define bFM4_GPIO_DDRE_P2 *((volatile uint8_t *)(0x42DE4708UL)) +#define bFM_GPIO_DDRE_P3 *((volatile uint8_t *)(0x42DE470CUL)) +#define bFM4_GPIO_DDRE_P3 *((volatile uint8_t *)(0x42DE470CUL)) + +#define bFM_GPIO_DDRF_P0 *((volatile uint8_t *)(0x42DE4780UL)) +#define bFM4_GPIO_DDRF_P0 *((volatile uint8_t *)(0x42DE4780UL)) +#define bFM_GPIO_DDRF_P1 *((volatile uint8_t *)(0x42DE4784UL)) +#define bFM4_GPIO_DDRF_P1 *((volatile uint8_t *)(0x42DE4784UL)) +#define bFM_GPIO_DDRF_P2 *((volatile uint8_t *)(0x42DE4788UL)) +#define bFM4_GPIO_DDRF_P2 *((volatile uint8_t *)(0x42DE4788UL)) +#define bFM_GPIO_DDRF_P3 *((volatile uint8_t *)(0x42DE478CUL)) +#define bFM4_GPIO_DDRF_P3 *((volatile uint8_t *)(0x42DE478CUL)) +#define bFM_GPIO_DDRF_P4 *((volatile uint8_t *)(0x42DE4790UL)) +#define bFM4_GPIO_DDRF_P4 *((volatile uint8_t *)(0x42DE4790UL)) +#define bFM_GPIO_DDRF_P5 *((volatile uint8_t *)(0x42DE4794UL)) +#define bFM4_GPIO_DDRF_P5 *((volatile uint8_t *)(0x42DE4794UL)) +#define bFM_GPIO_DDRF_P6 *((volatile uint8_t *)(0x42DE4798UL)) +#define bFM4_GPIO_DDRF_P6 *((volatile uint8_t *)(0x42DE4798UL)) +#define bFM_GPIO_DDRF_P7 *((volatile uint8_t *)(0x42DE479CUL)) +#define bFM4_GPIO_DDRF_P7 *((volatile uint8_t *)(0x42DE479CUL)) +#define bFM_GPIO_DDRF_P8 *((volatile uint8_t *)(0x42DE47A0UL)) +#define bFM4_GPIO_DDRF_P8 *((volatile uint8_t *)(0x42DE47A0UL)) +#define bFM_GPIO_DDRF_P9 *((volatile uint8_t *)(0x42DE47A4UL)) +#define bFM4_GPIO_DDRF_P9 *((volatile uint8_t *)(0x42DE47A4UL)) +#define bFM_GPIO_DDRF_PA *((volatile uint8_t *)(0x42DE47A8UL)) +#define bFM4_GPIO_DDRF_PA *((volatile uint8_t *)(0x42DE47A8UL)) +#define bFM_GPIO_DDRF_PB *((volatile uint8_t *)(0x42DE47ACUL)) +#define bFM4_GPIO_DDRF_PB *((volatile uint8_t *)(0x42DE47ACUL)) +#define bFM_GPIO_DDRF_PC *((volatile uint8_t *)(0x42DE47B0UL)) +#define bFM4_GPIO_DDRF_PC *((volatile uint8_t *)(0x42DE47B0UL)) + +#define bFM_GPIO_EPFR00_NMIS *((volatile uint8_t *)(0x42DEC000UL)) +#define bFM4_GPIO_EPFR00_NMIS *((volatile uint8_t *)(0x42DEC000UL)) +#define bFM_GPIO_EPFR00_USBP0E *((volatile uint8_t *)(0x42DEC024UL)) +#define bFM4_GPIO_EPFR00_USBP0E *((volatile uint8_t *)(0x42DEC024UL)) +#define bFM_GPIO_EPFR00_USBP1E *((volatile uint8_t *)(0x42DEC034UL)) +#define bFM4_GPIO_EPFR00_USBP1E *((volatile uint8_t *)(0x42DEC034UL)) +#define bFM_GPIO_EPFR00_JTAGEN0B *((volatile uint8_t *)(0x42DEC040UL)) +#define bFM4_GPIO_EPFR00_JTAGEN0B *((volatile uint8_t *)(0x42DEC040UL)) +#define bFM_GPIO_EPFR00_JTAGEN1S *((volatile uint8_t *)(0x42DEC044UL)) +#define bFM4_GPIO_EPFR00_JTAGEN1S *((volatile uint8_t *)(0x42DEC044UL)) +#define bFM_GPIO_EPFR00_TRC0E *((volatile uint8_t *)(0x42DEC060UL)) +#define bFM4_GPIO_EPFR00_TRC0E *((volatile uint8_t *)(0x42DEC060UL)) +#define bFM_GPIO_EPFR00_TRC1E *((volatile uint8_t *)(0x42DEC064UL)) +#define bFM4_GPIO_EPFR00_TRC1E *((volatile uint8_t *)(0x42DEC064UL)) +#define bFM_GPIO_EPFR00_TRC2E *((volatile uint8_t *)(0x42DEC068UL)) +#define bFM4_GPIO_EPFR00_TRC2E *((volatile uint8_t *)(0x42DEC068UL)) +#define bFM_GPIO_EPFR00_TRC3E *((volatile uint8_t *)(0x42DEC06CUL)) +#define bFM4_GPIO_EPFR00_TRC3E *((volatile uint8_t *)(0x42DEC06CUL)) + +#define bFM_GPIO_EPFR01_DTTI0C *((volatile uint8_t *)(0x42DEC0B0UL)) +#define bFM4_GPIO_EPFR01_DTTI0C *((volatile uint8_t *)(0x42DEC0B0UL)) + +#define bFM_GPIO_EPFR02_DTTI1C *((volatile uint8_t *)(0x42DEC130UL)) +#define bFM4_GPIO_EPFR02_DTTI1C *((volatile uint8_t *)(0x42DEC130UL)) + +#define bFM_GPIO_EPFR03_DTTI2C *((volatile uint8_t *)(0x42DEC1B0UL)) +#define bFM4_GPIO_EPFR03_DTTI2C *((volatile uint8_t *)(0x42DEC1B0UL)) + +#define bFM_GPIO_EPFR10_UEDEFB *((volatile uint8_t *)(0x42DEC500UL)) +#define bFM4_GPIO_EPFR10_UEDEFB *((volatile uint8_t *)(0x42DEC500UL)) +#define bFM_GPIO_EPFR10_UEDTHB *((volatile uint8_t *)(0x42DEC504UL)) +#define bFM4_GPIO_EPFR10_UEDTHB *((volatile uint8_t *)(0x42DEC504UL)) +#define bFM_GPIO_EPFR10_UECLKE *((volatile uint8_t *)(0x42DEC508UL)) +#define bFM4_GPIO_EPFR10_UECLKE *((volatile uint8_t *)(0x42DEC508UL)) +#define bFM_GPIO_EPFR10_UEWEXE *((volatile uint8_t *)(0x42DEC50CUL)) +#define bFM4_GPIO_EPFR10_UEWEXE *((volatile uint8_t *)(0x42DEC50CUL)) +#define bFM_GPIO_EPFR10_UEDQME *((volatile uint8_t *)(0x42DEC510UL)) +#define bFM4_GPIO_EPFR10_UEDQME *((volatile uint8_t *)(0x42DEC510UL)) +#define bFM_GPIO_EPFR10_UEOEXE *((volatile uint8_t *)(0x42DEC514UL)) +#define bFM4_GPIO_EPFR10_UEOEXE *((volatile uint8_t *)(0x42DEC514UL)) +#define bFM_GPIO_EPFR10_UEFLSE *((volatile uint8_t *)(0x42DEC518UL)) +#define bFM4_GPIO_EPFR10_UEFLSE *((volatile uint8_t *)(0x42DEC518UL)) +#define bFM_GPIO_EPFR10_UECS1E *((volatile uint8_t *)(0x42DEC51CUL)) +#define bFM4_GPIO_EPFR10_UECS1E *((volatile uint8_t *)(0x42DEC51CUL)) +#define bFM_GPIO_EPFR10_UECS2E *((volatile uint8_t *)(0x42DEC520UL)) +#define bFM4_GPIO_EPFR10_UECS2E *((volatile uint8_t *)(0x42DEC520UL)) +#define bFM_GPIO_EPFR10_UECS3E *((volatile uint8_t *)(0x42DEC524UL)) +#define bFM4_GPIO_EPFR10_UECS3E *((volatile uint8_t *)(0x42DEC524UL)) +#define bFM_GPIO_EPFR10_UECS4E *((volatile uint8_t *)(0x42DEC528UL)) +#define bFM4_GPIO_EPFR10_UECS4E *((volatile uint8_t *)(0x42DEC528UL)) +#define bFM_GPIO_EPFR10_UECS5E *((volatile uint8_t *)(0x42DEC52CUL)) +#define bFM4_GPIO_EPFR10_UECS5E *((volatile uint8_t *)(0x42DEC52CUL)) +#define bFM_GPIO_EPFR10_UECS6E *((volatile uint8_t *)(0x42DEC530UL)) +#define bFM4_GPIO_EPFR10_UECS6E *((volatile uint8_t *)(0x42DEC530UL)) +#define bFM_GPIO_EPFR10_UECS7E *((volatile uint8_t *)(0x42DEC534UL)) +#define bFM4_GPIO_EPFR10_UECS7E *((volatile uint8_t *)(0x42DEC534UL)) +#define bFM_GPIO_EPFR10_UEAOOE *((volatile uint8_t *)(0x42DEC538UL)) +#define bFM4_GPIO_EPFR10_UEAOOE *((volatile uint8_t *)(0x42DEC538UL)) +#define bFM_GPIO_EPFR10_UEA08E *((volatile uint8_t *)(0x42DEC53CUL)) +#define bFM4_GPIO_EPFR10_UEA08E *((volatile uint8_t *)(0x42DEC53CUL)) +#define bFM_GPIO_EPFR10_UEA09E *((volatile uint8_t *)(0x42DEC540UL)) +#define bFM4_GPIO_EPFR10_UEA09E *((volatile uint8_t *)(0x42DEC540UL)) +#define bFM_GPIO_EPFR10_UEA10E *((volatile uint8_t *)(0x42DEC544UL)) +#define bFM4_GPIO_EPFR10_UEA10E *((volatile uint8_t *)(0x42DEC544UL)) +#define bFM_GPIO_EPFR10_UEA11E *((volatile uint8_t *)(0x42DEC548UL)) +#define bFM4_GPIO_EPFR10_UEA11E *((volatile uint8_t *)(0x42DEC548UL)) +#define bFM_GPIO_EPFR10_UEA12E *((volatile uint8_t *)(0x42DEC54CUL)) +#define bFM4_GPIO_EPFR10_UEA12E *((volatile uint8_t *)(0x42DEC54CUL)) +#define bFM_GPIO_EPFR10_UEA13E *((volatile uint8_t *)(0x42DEC550UL)) +#define bFM4_GPIO_EPFR10_UEA13E *((volatile uint8_t *)(0x42DEC550UL)) +#define bFM_GPIO_EPFR10_UEA14E *((volatile uint8_t *)(0x42DEC554UL)) +#define bFM4_GPIO_EPFR10_UEA14E *((volatile uint8_t *)(0x42DEC554UL)) +#define bFM_GPIO_EPFR10_UEA15E *((volatile uint8_t *)(0x42DEC558UL)) +#define bFM4_GPIO_EPFR10_UEA15E *((volatile uint8_t *)(0x42DEC558UL)) +#define bFM_GPIO_EPFR10_UEA16E *((volatile uint8_t *)(0x42DEC55CUL)) +#define bFM4_GPIO_EPFR10_UEA16E *((volatile uint8_t *)(0x42DEC55CUL)) +#define bFM_GPIO_EPFR10_UEA17E *((volatile uint8_t *)(0x42DEC560UL)) +#define bFM4_GPIO_EPFR10_UEA17E *((volatile uint8_t *)(0x42DEC560UL)) +#define bFM_GPIO_EPFR10_UEA18E *((volatile uint8_t *)(0x42DEC564UL)) +#define bFM4_GPIO_EPFR10_UEA18E *((volatile uint8_t *)(0x42DEC564UL)) +#define bFM_GPIO_EPFR10_UEA19E *((volatile uint8_t *)(0x42DEC568UL)) +#define bFM4_GPIO_EPFR10_UEA19E *((volatile uint8_t *)(0x42DEC568UL)) +#define bFM_GPIO_EPFR10_UEA20E *((volatile uint8_t *)(0x42DEC56CUL)) +#define bFM4_GPIO_EPFR10_UEA20E *((volatile uint8_t *)(0x42DEC56CUL)) +#define bFM_GPIO_EPFR10_UEA21E *((volatile uint8_t *)(0x42DEC570UL)) +#define bFM4_GPIO_EPFR10_UEA21E *((volatile uint8_t *)(0x42DEC570UL)) +#define bFM_GPIO_EPFR10_UEA22E *((volatile uint8_t *)(0x42DEC574UL)) +#define bFM4_GPIO_EPFR10_UEA22E *((volatile uint8_t *)(0x42DEC574UL)) +#define bFM_GPIO_EPFR10_UEA23E *((volatile uint8_t *)(0x42DEC578UL)) +#define bFM4_GPIO_EPFR10_UEA23E *((volatile uint8_t *)(0x42DEC578UL)) +#define bFM_GPIO_EPFR10_UEA24E *((volatile uint8_t *)(0x42DEC57CUL)) +#define bFM4_GPIO_EPFR10_UEA24E *((volatile uint8_t *)(0x42DEC57CUL)) + +#define bFM_GPIO_EPFR11_UEALEE *((volatile uint8_t *)(0x42DEC580UL)) +#define bFM4_GPIO_EPFR11_UEALEE *((volatile uint8_t *)(0x42DEC580UL)) +#define bFM_GPIO_EPFR11_UECS0E *((volatile uint8_t *)(0x42DEC584UL)) +#define bFM4_GPIO_EPFR11_UECS0E *((volatile uint8_t *)(0x42DEC584UL)) +#define bFM_GPIO_EPFR11_UEA01E *((volatile uint8_t *)(0x42DEC588UL)) +#define bFM4_GPIO_EPFR11_UEA01E *((volatile uint8_t *)(0x42DEC588UL)) +#define bFM_GPIO_EPFR11_UEA02E *((volatile uint8_t *)(0x42DEC58CUL)) +#define bFM4_GPIO_EPFR11_UEA02E *((volatile uint8_t *)(0x42DEC58CUL)) +#define bFM_GPIO_EPFR11_UEA03E *((volatile uint8_t *)(0x42DEC590UL)) +#define bFM4_GPIO_EPFR11_UEA03E *((volatile uint8_t *)(0x42DEC590UL)) +#define bFM_GPIO_EPFR11_UEA04E *((volatile uint8_t *)(0x42DEC594UL)) +#define bFM4_GPIO_EPFR11_UEA04E *((volatile uint8_t *)(0x42DEC594UL)) +#define bFM_GPIO_EPFR11_UEA05E *((volatile uint8_t *)(0x42DEC598UL)) +#define bFM4_GPIO_EPFR11_UEA05E *((volatile uint8_t *)(0x42DEC598UL)) +#define bFM_GPIO_EPFR11_UEA06E *((volatile uint8_t *)(0x42DEC59CUL)) +#define bFM4_GPIO_EPFR11_UEA06E *((volatile uint8_t *)(0x42DEC59CUL)) +#define bFM_GPIO_EPFR11_UEA07E *((volatile uint8_t *)(0x42DEC5A0UL)) +#define bFM4_GPIO_EPFR11_UEA07E *((volatile uint8_t *)(0x42DEC5A0UL)) +#define bFM_GPIO_EPFR11_UED00B *((volatile uint8_t *)(0x42DEC5A4UL)) +#define bFM4_GPIO_EPFR11_UED00B *((volatile uint8_t *)(0x42DEC5A4UL)) +#define bFM_GPIO_EPFR11_UED01B *((volatile uint8_t *)(0x42DEC5A8UL)) +#define bFM4_GPIO_EPFR11_UED01B *((volatile uint8_t *)(0x42DEC5A8UL)) +#define bFM_GPIO_EPFR11_UED02B *((volatile uint8_t *)(0x42DEC5ACUL)) +#define bFM4_GPIO_EPFR11_UED02B *((volatile uint8_t *)(0x42DEC5ACUL)) +#define bFM_GPIO_EPFR11_UED03B *((volatile uint8_t *)(0x42DEC5B0UL)) +#define bFM4_GPIO_EPFR11_UED03B *((volatile uint8_t *)(0x42DEC5B0UL)) +#define bFM_GPIO_EPFR11_UED04B *((volatile uint8_t *)(0x42DEC5B4UL)) +#define bFM4_GPIO_EPFR11_UED04B *((volatile uint8_t *)(0x42DEC5B4UL)) +#define bFM_GPIO_EPFR11_UED05B *((volatile uint8_t *)(0x42DEC5B8UL)) +#define bFM4_GPIO_EPFR11_UED05B *((volatile uint8_t *)(0x42DEC5B8UL)) +#define bFM_GPIO_EPFR11_UED06B *((volatile uint8_t *)(0x42DEC5BCUL)) +#define bFM4_GPIO_EPFR11_UED06B *((volatile uint8_t *)(0x42DEC5BCUL)) +#define bFM_GPIO_EPFR11_UED07B *((volatile uint8_t *)(0x42DEC5C0UL)) +#define bFM4_GPIO_EPFR11_UED07B *((volatile uint8_t *)(0x42DEC5C0UL)) +#define bFM_GPIO_EPFR11_UED08B *((volatile uint8_t *)(0x42DEC5C4UL)) +#define bFM4_GPIO_EPFR11_UED08B *((volatile uint8_t *)(0x42DEC5C4UL)) +#define bFM_GPIO_EPFR11_UED09B *((volatile uint8_t *)(0x42DEC5C8UL)) +#define bFM4_GPIO_EPFR11_UED09B *((volatile uint8_t *)(0x42DEC5C8UL)) +#define bFM_GPIO_EPFR11_UED10B *((volatile uint8_t *)(0x42DEC5CCUL)) +#define bFM4_GPIO_EPFR11_UED10B *((volatile uint8_t *)(0x42DEC5CCUL)) +#define bFM_GPIO_EPFR11_UED11B *((volatile uint8_t *)(0x42DEC5D0UL)) +#define bFM4_GPIO_EPFR11_UED11B *((volatile uint8_t *)(0x42DEC5D0UL)) +#define bFM_GPIO_EPFR11_UED12B *((volatile uint8_t *)(0x42DEC5D4UL)) +#define bFM4_GPIO_EPFR11_UED12B *((volatile uint8_t *)(0x42DEC5D4UL)) +#define bFM_GPIO_EPFR11_UED13B *((volatile uint8_t *)(0x42DEC5D8UL)) +#define bFM4_GPIO_EPFR11_UED13B *((volatile uint8_t *)(0x42DEC5D8UL)) +#define bFM_GPIO_EPFR11_UED14B *((volatile uint8_t *)(0x42DEC5DCUL)) +#define bFM4_GPIO_EPFR11_UED14B *((volatile uint8_t *)(0x42DEC5DCUL)) +#define bFM_GPIO_EPFR11_UED15B *((volatile uint8_t *)(0x42DEC5E0UL)) +#define bFM4_GPIO_EPFR11_UED15B *((volatile uint8_t *)(0x42DEC5E0UL)) +#define bFM_GPIO_EPFR11_UERLC *((volatile uint8_t *)(0x42DEC5E4UL)) +#define bFM4_GPIO_EPFR11_UERLC *((volatile uint8_t *)(0x42DEC5E4UL)) + +#define bFM_GPIO_EPFR14_E_TD0E *((volatile uint8_t *)(0x42DEC748UL)) +#define bFM4_GPIO_EPFR14_E_TD0E *((volatile uint8_t *)(0x42DEC748UL)) +#define bFM_GPIO_EPFR14_E_TD1E *((volatile uint8_t *)(0x42DEC74CUL)) +#define bFM4_GPIO_EPFR14_E_TD1E *((volatile uint8_t *)(0x42DEC74CUL)) +#define bFM_GPIO_EPFR14_E_TE0E *((volatile uint8_t *)(0x42DEC750UL)) +#define bFM4_GPIO_EPFR14_E_TE0E *((volatile uint8_t *)(0x42DEC750UL)) +#define bFM_GPIO_EPFR14_E_TE1E *((volatile uint8_t *)(0x42DEC754UL)) +#define bFM4_GPIO_EPFR14_E_TE1E *((volatile uint8_t *)(0x42DEC754UL)) +#define bFM_GPIO_EPFR14_E_MC0E *((volatile uint8_t *)(0x42DEC758UL)) +#define bFM4_GPIO_EPFR14_E_MC0E *((volatile uint8_t *)(0x42DEC758UL)) +#define bFM_GPIO_EPFR14_E_MC1B *((volatile uint8_t *)(0x42DEC75CUL)) +#define bFM4_GPIO_EPFR14_E_MC1B *((volatile uint8_t *)(0x42DEC75CUL)) +#define bFM_GPIO_EPFR14_E_MD0B *((volatile uint8_t *)(0x42DEC760UL)) +#define bFM4_GPIO_EPFR14_E_MD0B *((volatile uint8_t *)(0x42DEC760UL)) +#define bFM_GPIO_EPFR14_E_MD1B *((volatile uint8_t *)(0x42DEC764UL)) +#define bFM4_GPIO_EPFR14_E_MD1B *((volatile uint8_t *)(0x42DEC764UL)) +#define bFM_GPIO_EPFR14_E_CKE *((volatile uint8_t *)(0x42DEC768UL)) +#define bFM4_GPIO_EPFR14_E_CKE *((volatile uint8_t *)(0x42DEC768UL)) +#define bFM_GPIO_EPFR14_E_PSE *((volatile uint8_t *)(0x42DEC76CUL)) +#define bFM4_GPIO_EPFR14_E_PSE *((volatile uint8_t *)(0x42DEC76CUL)) + +#define bFM_GPIO_EPFR16_SFMPAC *((volatile uint8_t *)(0x42DEC870UL)) +#define bFM4_GPIO_EPFR16_SFMPAC *((volatile uint8_t *)(0x42DEC870UL)) +#define bFM_GPIO_EPFR16_SFMPBC *((volatile uint8_t *)(0x42DEC874UL)) +#define bFM4_GPIO_EPFR16_SFMPBC *((volatile uint8_t *)(0x42DEC874UL)) + +#define bFM_GPIO_EPFR20_UESMCKE *((volatile uint8_t *)(0x42DECA00UL)) +#define bFM4_GPIO_EPFR20_UESMCKE *((volatile uint8_t *)(0x42DECA00UL)) +#define bFM_GPIO_EPFR20_UESMCEE *((volatile uint8_t *)(0x42DECA04UL)) +#define bFM4_GPIO_EPFR20_UESMCEE *((volatile uint8_t *)(0x42DECA04UL)) +#define bFM_GPIO_EPFR20_UERASE *((volatile uint8_t *)(0x42DECA08UL)) +#define bFM4_GPIO_EPFR20_UERASE *((volatile uint8_t *)(0x42DECA08UL)) +#define bFM_GPIO_EPFR20_UECASE *((volatile uint8_t *)(0x42DECA0CUL)) +#define bFM4_GPIO_EPFR20_UECASE *((volatile uint8_t *)(0x42DECA0CUL)) +#define bFM_GPIO_EPFR20_UEDWEXE *((volatile uint8_t *)(0x42DECA10UL)) +#define bFM4_GPIO_EPFR20_UEDWEXE *((volatile uint8_t *)(0x42DECA10UL)) +#define bFM_GPIO_EPFR20_UECSXE *((volatile uint8_t *)(0x42DECA14UL)) +#define bFM4_GPIO_EPFR20_UECSXE *((volatile uint8_t *)(0x42DECA14UL)) +#define bFM_GPIO_EPFR20_UEDQM2E *((volatile uint8_t *)(0x42DECA18UL)) +#define bFM4_GPIO_EPFR20_UEDQM2E *((volatile uint8_t *)(0x42DECA18UL)) +#define bFM_GPIO_EPFR20_UEDQM3E *((volatile uint8_t *)(0x42DECA1CUL)) +#define bFM4_GPIO_EPFR20_UEDQM3E *((volatile uint8_t *)(0x42DECA1CUL)) +#define bFM_GPIO_EPFR20_UEDTHHB *((volatile uint8_t *)(0x42DECA20UL)) +#define bFM4_GPIO_EPFR20_UEDTHHB *((volatile uint8_t *)(0x42DECA20UL)) +#define bFM_GPIO_EPFR20_UED16B *((volatile uint8_t *)(0x42DECA24UL)) +#define bFM4_GPIO_EPFR20_UED16B *((volatile uint8_t *)(0x42DECA24UL)) +#define bFM_GPIO_EPFR20_UED17B *((volatile uint8_t *)(0x42DECA28UL)) +#define bFM4_GPIO_EPFR20_UED17B *((volatile uint8_t *)(0x42DECA28UL)) +#define bFM_GPIO_EPFR20_UED18B *((volatile uint8_t *)(0x42DECA2CUL)) +#define bFM4_GPIO_EPFR20_UED18B *((volatile uint8_t *)(0x42DECA2CUL)) +#define bFM_GPIO_EPFR20_UED19B *((volatile uint8_t *)(0x42DECA30UL)) +#define bFM4_GPIO_EPFR20_UED19B *((volatile uint8_t *)(0x42DECA30UL)) +#define bFM_GPIO_EPFR20_UED20B *((volatile uint8_t *)(0x42DECA34UL)) +#define bFM4_GPIO_EPFR20_UED20B *((volatile uint8_t *)(0x42DECA34UL)) +#define bFM_GPIO_EPFR20_UED21B *((volatile uint8_t *)(0x42DECA38UL)) +#define bFM4_GPIO_EPFR20_UED21B *((volatile uint8_t *)(0x42DECA38UL)) +#define bFM_GPIO_EPFR20_UED22B *((volatile uint8_t *)(0x42DECA3CUL)) +#define bFM4_GPIO_EPFR20_UED22B *((volatile uint8_t *)(0x42DECA3CUL)) +#define bFM_GPIO_EPFR20_UED23B *((volatile uint8_t *)(0x42DECA40UL)) +#define bFM4_GPIO_EPFR20_UED23B *((volatile uint8_t *)(0x42DECA40UL)) +#define bFM_GPIO_EPFR20_UED24B *((volatile uint8_t *)(0x42DECA44UL)) +#define bFM4_GPIO_EPFR20_UED24B *((volatile uint8_t *)(0x42DECA44UL)) +#define bFM_GPIO_EPFR20_UED25B *((volatile uint8_t *)(0x42DECA48UL)) +#define bFM4_GPIO_EPFR20_UED25B *((volatile uint8_t *)(0x42DECA48UL)) +#define bFM_GPIO_EPFR20_UED26B *((volatile uint8_t *)(0x42DECA4CUL)) +#define bFM4_GPIO_EPFR20_UED26B *((volatile uint8_t *)(0x42DECA4CUL)) +#define bFM_GPIO_EPFR20_UED27B *((volatile uint8_t *)(0x42DECA50UL)) +#define bFM4_GPIO_EPFR20_UED27B *((volatile uint8_t *)(0x42DECA50UL)) +#define bFM_GPIO_EPFR20_UED28B *((volatile uint8_t *)(0x42DECA54UL)) +#define bFM4_GPIO_EPFR20_UED28B *((volatile uint8_t *)(0x42DECA54UL)) +#define bFM_GPIO_EPFR20_UED29B *((volatile uint8_t *)(0x42DECA58UL)) +#define bFM4_GPIO_EPFR20_UED29B *((volatile uint8_t *)(0x42DECA58UL)) +#define bFM_GPIO_EPFR20_UED30B *((volatile uint8_t *)(0x42DECA5CUL)) +#define bFM4_GPIO_EPFR20_UED30B *((volatile uint8_t *)(0x42DECA5CUL)) +#define bFM_GPIO_EPFR20_UED31B *((volatile uint8_t *)(0x42DECA60UL)) +#define bFM4_GPIO_EPFR20_UED31B *((volatile uint8_t *)(0x42DECA60UL)) + +#define bFM_GPIO_PCR0_P0 *((volatile uint8_t *)(0x42DE2000UL)) +#define bFM4_GPIO_PCR0_P0 *((volatile uint8_t *)(0x42DE2000UL)) +#define bFM_GPIO_PCR0_P1 *((volatile uint8_t *)(0x42DE2004UL)) +#define bFM4_GPIO_PCR0_P1 *((volatile uint8_t *)(0x42DE2004UL)) +#define bFM_GPIO_PCR0_P2 *((volatile uint8_t *)(0x42DE2008UL)) +#define bFM4_GPIO_PCR0_P2 *((volatile uint8_t *)(0x42DE2008UL)) +#define bFM_GPIO_PCR0_P3 *((volatile uint8_t *)(0x42DE200CUL)) +#define bFM4_GPIO_PCR0_P3 *((volatile uint8_t *)(0x42DE200CUL)) +#define bFM_GPIO_PCR0_P4 *((volatile uint8_t *)(0x42DE2010UL)) +#define bFM4_GPIO_PCR0_P4 *((volatile uint8_t *)(0x42DE2010UL)) +#define bFM_GPIO_PCR0_P8 *((volatile uint8_t *)(0x42DE2020UL)) +#define bFM4_GPIO_PCR0_P8 *((volatile uint8_t *)(0x42DE2020UL)) +#define bFM_GPIO_PCR0_P9 *((volatile uint8_t *)(0x42DE2024UL)) +#define bFM4_GPIO_PCR0_P9 *((volatile uint8_t *)(0x42DE2024UL)) +#define bFM_GPIO_PCR0_PA *((volatile uint8_t *)(0x42DE2028UL)) +#define bFM4_GPIO_PCR0_PA *((volatile uint8_t *)(0x42DE2028UL)) + +#define bFM_GPIO_PCR1_P0 *((volatile uint8_t *)(0x42DE2080UL)) +#define bFM4_GPIO_PCR1_P0 *((volatile uint8_t *)(0x42DE2080UL)) +#define bFM_GPIO_PCR1_P1 *((volatile uint8_t *)(0x42DE2084UL)) +#define bFM4_GPIO_PCR1_P1 *((volatile uint8_t *)(0x42DE2084UL)) +#define bFM_GPIO_PCR1_P2 *((volatile uint8_t *)(0x42DE2088UL)) +#define bFM4_GPIO_PCR1_P2 *((volatile uint8_t *)(0x42DE2088UL)) +#define bFM_GPIO_PCR1_P3 *((volatile uint8_t *)(0x42DE208CUL)) +#define bFM4_GPIO_PCR1_P3 *((volatile uint8_t *)(0x42DE208CUL)) +#define bFM_GPIO_PCR1_P4 *((volatile uint8_t *)(0x42DE2090UL)) +#define bFM4_GPIO_PCR1_P4 *((volatile uint8_t *)(0x42DE2090UL)) +#define bFM_GPIO_PCR1_P5 *((volatile uint8_t *)(0x42DE2094UL)) +#define bFM4_GPIO_PCR1_P5 *((volatile uint8_t *)(0x42DE2094UL)) +#define bFM_GPIO_PCR1_P6 *((volatile uint8_t *)(0x42DE2098UL)) +#define bFM4_GPIO_PCR1_P6 *((volatile uint8_t *)(0x42DE2098UL)) +#define bFM_GPIO_PCR1_P7 *((volatile uint8_t *)(0x42DE209CUL)) +#define bFM4_GPIO_PCR1_P7 *((volatile uint8_t *)(0x42DE209CUL)) +#define bFM_GPIO_PCR1_P8 *((volatile uint8_t *)(0x42DE20A0UL)) +#define bFM4_GPIO_PCR1_P8 *((volatile uint8_t *)(0x42DE20A0UL)) +#define bFM_GPIO_PCR1_P9 *((volatile uint8_t *)(0x42DE20A4UL)) +#define bFM4_GPIO_PCR1_P9 *((volatile uint8_t *)(0x42DE20A4UL)) +#define bFM_GPIO_PCR1_PA *((volatile uint8_t *)(0x42DE20A8UL)) +#define bFM4_GPIO_PCR1_PA *((volatile uint8_t *)(0x42DE20A8UL)) +#define bFM_GPIO_PCR1_PB *((volatile uint8_t *)(0x42DE20ACUL)) +#define bFM4_GPIO_PCR1_PB *((volatile uint8_t *)(0x42DE20ACUL)) +#define bFM_GPIO_PCR1_PC *((volatile uint8_t *)(0x42DE20B0UL)) +#define bFM4_GPIO_PCR1_PC *((volatile uint8_t *)(0x42DE20B0UL)) +#define bFM_GPIO_PCR1_PD *((volatile uint8_t *)(0x42DE20B4UL)) +#define bFM4_GPIO_PCR1_PD *((volatile uint8_t *)(0x42DE20B4UL)) +#define bFM_GPIO_PCR1_PE *((volatile uint8_t *)(0x42DE20B8UL)) +#define bFM4_GPIO_PCR1_PE *((volatile uint8_t *)(0x42DE20B8UL)) +#define bFM_GPIO_PCR1_PF *((volatile uint8_t *)(0x42DE20BCUL)) +#define bFM4_GPIO_PCR1_PF *((volatile uint8_t *)(0x42DE20BCUL)) + +#define bFM_GPIO_PCR2_P0 *((volatile uint8_t *)(0x42DE2100UL)) +#define bFM4_GPIO_PCR2_P0 *((volatile uint8_t *)(0x42DE2100UL)) +#define bFM_GPIO_PCR2_P1 *((volatile uint8_t *)(0x42DE2104UL)) +#define bFM4_GPIO_PCR2_P1 *((volatile uint8_t *)(0x42DE2104UL)) +#define bFM_GPIO_PCR2_P2 *((volatile uint8_t *)(0x42DE2108UL)) +#define bFM4_GPIO_PCR2_P2 *((volatile uint8_t *)(0x42DE2108UL)) +#define bFM_GPIO_PCR2_P3 *((volatile uint8_t *)(0x42DE210CUL)) +#define bFM4_GPIO_PCR2_P3 *((volatile uint8_t *)(0x42DE210CUL)) +#define bFM_GPIO_PCR2_P4 *((volatile uint8_t *)(0x42DE2110UL)) +#define bFM4_GPIO_PCR2_P4 *((volatile uint8_t *)(0x42DE2110UL)) +#define bFM_GPIO_PCR2_P5 *((volatile uint8_t *)(0x42DE2114UL)) +#define bFM4_GPIO_PCR2_P5 *((volatile uint8_t *)(0x42DE2114UL)) +#define bFM_GPIO_PCR2_P6 *((volatile uint8_t *)(0x42DE2118UL)) +#define bFM4_GPIO_PCR2_P6 *((volatile uint8_t *)(0x42DE2118UL)) +#define bFM_GPIO_PCR2_P7 *((volatile uint8_t *)(0x42DE211CUL)) +#define bFM4_GPIO_PCR2_P7 *((volatile uint8_t *)(0x42DE211CUL)) +#define bFM_GPIO_PCR2_P8 *((volatile uint8_t *)(0x42DE2120UL)) +#define bFM4_GPIO_PCR2_P8 *((volatile uint8_t *)(0x42DE2120UL)) +#define bFM_GPIO_PCR2_P9 *((volatile uint8_t *)(0x42DE2124UL)) +#define bFM4_GPIO_PCR2_P9 *((volatile uint8_t *)(0x42DE2124UL)) +#define bFM_GPIO_PCR2_PA *((volatile uint8_t *)(0x42DE2128UL)) +#define bFM4_GPIO_PCR2_PA *((volatile uint8_t *)(0x42DE2128UL)) + +#define bFM_GPIO_PCR3_P0 *((volatile uint8_t *)(0x42DE2180UL)) +#define bFM4_GPIO_PCR3_P0 *((volatile uint8_t *)(0x42DE2180UL)) +#define bFM_GPIO_PCR3_P1 *((volatile uint8_t *)(0x42DE2184UL)) +#define bFM4_GPIO_PCR3_P1 *((volatile uint8_t *)(0x42DE2184UL)) +#define bFM_GPIO_PCR3_P2 *((volatile uint8_t *)(0x42DE2188UL)) +#define bFM4_GPIO_PCR3_P2 *((volatile uint8_t *)(0x42DE2188UL)) +#define bFM_GPIO_PCR3_P3 *((volatile uint8_t *)(0x42DE218CUL)) +#define bFM4_GPIO_PCR3_P3 *((volatile uint8_t *)(0x42DE218CUL)) +#define bFM_GPIO_PCR3_P4 *((volatile uint8_t *)(0x42DE2190UL)) +#define bFM4_GPIO_PCR3_P4 *((volatile uint8_t *)(0x42DE2190UL)) +#define bFM_GPIO_PCR3_P5 *((volatile uint8_t *)(0x42DE2194UL)) +#define bFM4_GPIO_PCR3_P5 *((volatile uint8_t *)(0x42DE2194UL)) +#define bFM_GPIO_PCR3_P6 *((volatile uint8_t *)(0x42DE2198UL)) +#define bFM4_GPIO_PCR3_P6 *((volatile uint8_t *)(0x42DE2198UL)) +#define bFM_GPIO_PCR3_P7 *((volatile uint8_t *)(0x42DE219CUL)) +#define bFM4_GPIO_PCR3_P7 *((volatile uint8_t *)(0x42DE219CUL)) +#define bFM_GPIO_PCR3_P8 *((volatile uint8_t *)(0x42DE21A0UL)) +#define bFM4_GPIO_PCR3_P8 *((volatile uint8_t *)(0x42DE21A0UL)) +#define bFM_GPIO_PCR3_P9 *((volatile uint8_t *)(0x42DE21A4UL)) +#define bFM4_GPIO_PCR3_P9 *((volatile uint8_t *)(0x42DE21A4UL)) +#define bFM_GPIO_PCR3_PA *((volatile uint8_t *)(0x42DE21A8UL)) +#define bFM4_GPIO_PCR3_PA *((volatile uint8_t *)(0x42DE21A8UL)) +#define bFM_GPIO_PCR3_PB *((volatile uint8_t *)(0x42DE21ACUL)) +#define bFM4_GPIO_PCR3_PB *((volatile uint8_t *)(0x42DE21ACUL)) +#define bFM_GPIO_PCR3_PC *((volatile uint8_t *)(0x42DE21B0UL)) +#define bFM4_GPIO_PCR3_PC *((volatile uint8_t *)(0x42DE21B0UL)) +#define bFM_GPIO_PCR3_PD *((volatile uint8_t *)(0x42DE21B4UL)) +#define bFM4_GPIO_PCR3_PD *((volatile uint8_t *)(0x42DE21B4UL)) +#define bFM_GPIO_PCR3_PE *((volatile uint8_t *)(0x42DE21B8UL)) +#define bFM4_GPIO_PCR3_PE *((volatile uint8_t *)(0x42DE21B8UL)) + +#define bFM_GPIO_PCR4_P0 *((volatile uint8_t *)(0x42DE2200UL)) +#define bFM4_GPIO_PCR4_P0 *((volatile uint8_t *)(0x42DE2200UL)) +#define bFM_GPIO_PCR4_P1 *((volatile uint8_t *)(0x42DE2204UL)) +#define bFM4_GPIO_PCR4_P1 *((volatile uint8_t *)(0x42DE2204UL)) +#define bFM_GPIO_PCR4_P2 *((volatile uint8_t *)(0x42DE2208UL)) +#define bFM4_GPIO_PCR4_P2 *((volatile uint8_t *)(0x42DE2208UL)) +#define bFM_GPIO_PCR4_P3 *((volatile uint8_t *)(0x42DE220CUL)) +#define bFM4_GPIO_PCR4_P3 *((volatile uint8_t *)(0x42DE220CUL)) +#define bFM_GPIO_PCR4_P4 *((volatile uint8_t *)(0x42DE2210UL)) +#define bFM4_GPIO_PCR4_P4 *((volatile uint8_t *)(0x42DE2210UL)) +#define bFM_GPIO_PCR4_P5 *((volatile uint8_t *)(0x42DE2214UL)) +#define bFM4_GPIO_PCR4_P5 *((volatile uint8_t *)(0x42DE2214UL)) +#define bFM_GPIO_PCR4_P6 *((volatile uint8_t *)(0x42DE2218UL)) +#define bFM4_GPIO_PCR4_P6 *((volatile uint8_t *)(0x42DE2218UL)) +#define bFM_GPIO_PCR4_P7 *((volatile uint8_t *)(0x42DE221CUL)) +#define bFM4_GPIO_PCR4_P7 *((volatile uint8_t *)(0x42DE221CUL)) +#define bFM_GPIO_PCR4_P8 *((volatile uint8_t *)(0x42DE2220UL)) +#define bFM4_GPIO_PCR4_P8 *((volatile uint8_t *)(0x42DE2220UL)) +#define bFM_GPIO_PCR4_P9 *((volatile uint8_t *)(0x42DE2224UL)) +#define bFM4_GPIO_PCR4_P9 *((volatile uint8_t *)(0x42DE2224UL)) +#define bFM_GPIO_PCR4_PA *((volatile uint8_t *)(0x42DE2228UL)) +#define bFM4_GPIO_PCR4_PA *((volatile uint8_t *)(0x42DE2228UL)) +#define bFM_GPIO_PCR4_PB *((volatile uint8_t *)(0x42DE222CUL)) +#define bFM4_GPIO_PCR4_PB *((volatile uint8_t *)(0x42DE222CUL)) +#define bFM_GPIO_PCR4_PC *((volatile uint8_t *)(0x42DE2230UL)) +#define bFM4_GPIO_PCR4_PC *((volatile uint8_t *)(0x42DE2230UL)) +#define bFM_GPIO_PCR4_PD *((volatile uint8_t *)(0x42DE2234UL)) +#define bFM4_GPIO_PCR4_PD *((volatile uint8_t *)(0x42DE2234UL)) +#define bFM_GPIO_PCR4_PE *((volatile uint8_t *)(0x42DE2238UL)) +#define bFM4_GPIO_PCR4_PE *((volatile uint8_t *)(0x42DE2238UL)) + +#define bFM_GPIO_PCR5_P0 *((volatile uint8_t *)(0x42DE2280UL)) +#define bFM4_GPIO_PCR5_P0 *((volatile uint8_t *)(0x42DE2280UL)) +#define bFM_GPIO_PCR5_P1 *((volatile uint8_t *)(0x42DE2284UL)) +#define bFM4_GPIO_PCR5_P1 *((volatile uint8_t *)(0x42DE2284UL)) +#define bFM_GPIO_PCR5_P2 *((volatile uint8_t *)(0x42DE2288UL)) +#define bFM4_GPIO_PCR5_P2 *((volatile uint8_t *)(0x42DE2288UL)) +#define bFM_GPIO_PCR5_P3 *((volatile uint8_t *)(0x42DE228CUL)) +#define bFM4_GPIO_PCR5_P3 *((volatile uint8_t *)(0x42DE228CUL)) +#define bFM_GPIO_PCR5_P4 *((volatile uint8_t *)(0x42DE2290UL)) +#define bFM4_GPIO_PCR5_P4 *((volatile uint8_t *)(0x42DE2290UL)) +#define bFM_GPIO_PCR5_P5 *((volatile uint8_t *)(0x42DE2294UL)) +#define bFM4_GPIO_PCR5_P5 *((volatile uint8_t *)(0x42DE2294UL)) +#define bFM_GPIO_PCR5_P6 *((volatile uint8_t *)(0x42DE2298UL)) +#define bFM4_GPIO_PCR5_P6 *((volatile uint8_t *)(0x42DE2298UL)) +#define bFM_GPIO_PCR5_P7 *((volatile uint8_t *)(0x42DE229CUL)) +#define bFM4_GPIO_PCR5_P7 *((volatile uint8_t *)(0x42DE229CUL)) +#define bFM_GPIO_PCR5_P8 *((volatile uint8_t *)(0x42DE22A0UL)) +#define bFM4_GPIO_PCR5_P8 *((volatile uint8_t *)(0x42DE22A0UL)) +#define bFM_GPIO_PCR5_P9 *((volatile uint8_t *)(0x42DE22A4UL)) +#define bFM4_GPIO_PCR5_P9 *((volatile uint8_t *)(0x42DE22A4UL)) +#define bFM_GPIO_PCR5_PA *((volatile uint8_t *)(0x42DE22A8UL)) +#define bFM4_GPIO_PCR5_PA *((volatile uint8_t *)(0x42DE22A8UL)) +#define bFM_GPIO_PCR5_PB *((volatile uint8_t *)(0x42DE22ACUL)) +#define bFM4_GPIO_PCR5_PB *((volatile uint8_t *)(0x42DE22ACUL)) +#define bFM_GPIO_PCR5_PC *((volatile uint8_t *)(0x42DE22B0UL)) +#define bFM4_GPIO_PCR5_PC *((volatile uint8_t *)(0x42DE22B0UL)) +#define bFM_GPIO_PCR5_PD *((volatile uint8_t *)(0x42DE22B4UL)) +#define bFM4_GPIO_PCR5_PD *((volatile uint8_t *)(0x42DE22B4UL)) +#define bFM_GPIO_PCR5_PE *((volatile uint8_t *)(0x42DE22B8UL)) +#define bFM4_GPIO_PCR5_PE *((volatile uint8_t *)(0x42DE22B8UL)) +#define bFM_GPIO_PCR5_PF *((volatile uint8_t *)(0x42DE22BCUL)) +#define bFM4_GPIO_PCR5_PF *((volatile uint8_t *)(0x42DE22BCUL)) + +#define bFM_GPIO_PCR6_P0 *((volatile uint8_t *)(0x42DE2300UL)) +#define bFM4_GPIO_PCR6_P0 *((volatile uint8_t *)(0x42DE2300UL)) +#define bFM_GPIO_PCR6_P1 *((volatile uint8_t *)(0x42DE2304UL)) +#define bFM4_GPIO_PCR6_P1 *((volatile uint8_t *)(0x42DE2304UL)) +#define bFM_GPIO_PCR6_P2 *((volatile uint8_t *)(0x42DE2308UL)) +#define bFM4_GPIO_PCR6_P2 *((volatile uint8_t *)(0x42DE2308UL)) +#define bFM_GPIO_PCR6_P3 *((volatile uint8_t *)(0x42DE230CUL)) +#define bFM4_GPIO_PCR6_P3 *((volatile uint8_t *)(0x42DE230CUL)) +#define bFM_GPIO_PCR6_P4 *((volatile uint8_t *)(0x42DE2310UL)) +#define bFM4_GPIO_PCR6_P4 *((volatile uint8_t *)(0x42DE2310UL)) +#define bFM_GPIO_PCR6_P5 *((volatile uint8_t *)(0x42DE2314UL)) +#define bFM4_GPIO_PCR6_P5 *((volatile uint8_t *)(0x42DE2314UL)) +#define bFM_GPIO_PCR6_P6 *((volatile uint8_t *)(0x42DE2318UL)) +#define bFM4_GPIO_PCR6_P6 *((volatile uint8_t *)(0x42DE2318UL)) +#define bFM_GPIO_PCR6_P7 *((volatile uint8_t *)(0x42DE231CUL)) +#define bFM4_GPIO_PCR6_P7 *((volatile uint8_t *)(0x42DE231CUL)) +#define bFM_GPIO_PCR6_P8 *((volatile uint8_t *)(0x42DE2320UL)) +#define bFM4_GPIO_PCR6_P8 *((volatile uint8_t *)(0x42DE2320UL)) +#define bFM_GPIO_PCR6_P9 *((volatile uint8_t *)(0x42DE2324UL)) +#define bFM4_GPIO_PCR6_P9 *((volatile uint8_t *)(0x42DE2324UL)) +#define bFM_GPIO_PCR6_PA *((volatile uint8_t *)(0x42DE2328UL)) +#define bFM4_GPIO_PCR6_PA *((volatile uint8_t *)(0x42DE2328UL)) +#define bFM_GPIO_PCR6_PB *((volatile uint8_t *)(0x42DE232CUL)) +#define bFM4_GPIO_PCR6_PB *((volatile uint8_t *)(0x42DE232CUL)) +#define bFM_GPIO_PCR6_PC *((volatile uint8_t *)(0x42DE2330UL)) +#define bFM4_GPIO_PCR6_PC *((volatile uint8_t *)(0x42DE2330UL)) +#define bFM_GPIO_PCR6_PD *((volatile uint8_t *)(0x42DE2334UL)) +#define bFM4_GPIO_PCR6_PD *((volatile uint8_t *)(0x42DE2334UL)) +#define bFM_GPIO_PCR6_PE *((volatile uint8_t *)(0x42DE2338UL)) +#define bFM4_GPIO_PCR6_PE *((volatile uint8_t *)(0x42DE2338UL)) + +#define bFM_GPIO_PCR7_P0 *((volatile uint8_t *)(0x42DE2380UL)) +#define bFM4_GPIO_PCR7_P0 *((volatile uint8_t *)(0x42DE2380UL)) +#define bFM_GPIO_PCR7_P1 *((volatile uint8_t *)(0x42DE2384UL)) +#define bFM4_GPIO_PCR7_P1 *((volatile uint8_t *)(0x42DE2384UL)) +#define bFM_GPIO_PCR7_P2 *((volatile uint8_t *)(0x42DE2388UL)) +#define bFM4_GPIO_PCR7_P2 *((volatile uint8_t *)(0x42DE2388UL)) +#define bFM_GPIO_PCR7_P3 *((volatile uint8_t *)(0x42DE238CUL)) +#define bFM4_GPIO_PCR7_P3 *((volatile uint8_t *)(0x42DE238CUL)) +#define bFM_GPIO_PCR7_P4 *((volatile uint8_t *)(0x42DE2390UL)) +#define bFM4_GPIO_PCR7_P4 *((volatile uint8_t *)(0x42DE2390UL)) +#define bFM_GPIO_PCR7_P5 *((volatile uint8_t *)(0x42DE2394UL)) +#define bFM4_GPIO_PCR7_P5 *((volatile uint8_t *)(0x42DE2394UL)) +#define bFM_GPIO_PCR7_P6 *((volatile uint8_t *)(0x42DE2398UL)) +#define bFM4_GPIO_PCR7_P6 *((volatile uint8_t *)(0x42DE2398UL)) +#define bFM_GPIO_PCR7_P7 *((volatile uint8_t *)(0x42DE239CUL)) +#define bFM4_GPIO_PCR7_P7 *((volatile uint8_t *)(0x42DE239CUL)) +#define bFM_GPIO_PCR7_P8 *((volatile uint8_t *)(0x42DE23A0UL)) +#define bFM4_GPIO_PCR7_P8 *((volatile uint8_t *)(0x42DE23A0UL)) +#define bFM_GPIO_PCR7_P9 *((volatile uint8_t *)(0x42DE23A4UL)) +#define bFM4_GPIO_PCR7_P9 *((volatile uint8_t *)(0x42DE23A4UL)) +#define bFM_GPIO_PCR7_PA *((volatile uint8_t *)(0x42DE23A8UL)) +#define bFM4_GPIO_PCR7_PA *((volatile uint8_t *)(0x42DE23A8UL)) +#define bFM_GPIO_PCR7_PB *((volatile uint8_t *)(0x42DE23ACUL)) +#define bFM4_GPIO_PCR7_PB *((volatile uint8_t *)(0x42DE23ACUL)) +#define bFM_GPIO_PCR7_PC *((volatile uint8_t *)(0x42DE23B0UL)) +#define bFM4_GPIO_PCR7_PC *((volatile uint8_t *)(0x42DE23B0UL)) +#define bFM_GPIO_PCR7_PD *((volatile uint8_t *)(0x42DE23B4UL)) +#define bFM4_GPIO_PCR7_PD *((volatile uint8_t *)(0x42DE23B4UL)) +#define bFM_GPIO_PCR7_PE *((volatile uint8_t *)(0x42DE23B8UL)) +#define bFM4_GPIO_PCR7_PE *((volatile uint8_t *)(0x42DE23B8UL)) + +#define bFM_GPIO_PCR9_P0 *((volatile uint8_t *)(0x42DE2480UL)) +#define bFM4_GPIO_PCR9_P0 *((volatile uint8_t *)(0x42DE2480UL)) +#define bFM_GPIO_PCR9_P1 *((volatile uint8_t *)(0x42DE2484UL)) +#define bFM4_GPIO_PCR9_P1 *((volatile uint8_t *)(0x42DE2484UL)) +#define bFM_GPIO_PCR9_P2 *((volatile uint8_t *)(0x42DE2488UL)) +#define bFM4_GPIO_PCR9_P2 *((volatile uint8_t *)(0x42DE2488UL)) +#define bFM_GPIO_PCR9_P3 *((volatile uint8_t *)(0x42DE248CUL)) +#define bFM4_GPIO_PCR9_P3 *((volatile uint8_t *)(0x42DE248CUL)) +#define bFM_GPIO_PCR9_P4 *((volatile uint8_t *)(0x42DE2490UL)) +#define bFM4_GPIO_PCR9_P4 *((volatile uint8_t *)(0x42DE2490UL)) +#define bFM_GPIO_PCR9_P5 *((volatile uint8_t *)(0x42DE2494UL)) +#define bFM4_GPIO_PCR9_P5 *((volatile uint8_t *)(0x42DE2494UL)) +#define bFM_GPIO_PCR9_P6 *((volatile uint8_t *)(0x42DE2498UL)) +#define bFM4_GPIO_PCR9_P6 *((volatile uint8_t *)(0x42DE2498UL)) +#define bFM_GPIO_PCR9_P7 *((volatile uint8_t *)(0x42DE249CUL)) +#define bFM4_GPIO_PCR9_P7 *((volatile uint8_t *)(0x42DE249CUL)) + +#define bFM_GPIO_PCRA_P0 *((volatile uint8_t *)(0x42DE2500UL)) +#define bFM4_GPIO_PCRA_P0 *((volatile uint8_t *)(0x42DE2500UL)) +#define bFM_GPIO_PCRA_P1 *((volatile uint8_t *)(0x42DE2504UL)) +#define bFM4_GPIO_PCRA_P1 *((volatile uint8_t *)(0x42DE2504UL)) +#define bFM_GPIO_PCRA_P2 *((volatile uint8_t *)(0x42DE2508UL)) +#define bFM4_GPIO_PCRA_P2 *((volatile uint8_t *)(0x42DE2508UL)) +#define bFM_GPIO_PCRA_P3 *((volatile uint8_t *)(0x42DE250CUL)) +#define bFM4_GPIO_PCRA_P3 *((volatile uint8_t *)(0x42DE250CUL)) +#define bFM_GPIO_PCRA_P4 *((volatile uint8_t *)(0x42DE2510UL)) +#define bFM4_GPIO_PCRA_P4 *((volatile uint8_t *)(0x42DE2510UL)) +#define bFM_GPIO_PCRA_P5 *((volatile uint8_t *)(0x42DE2514UL)) +#define bFM4_GPIO_PCRA_P5 *((volatile uint8_t *)(0x42DE2514UL)) +#define bFM_GPIO_PCRA_P6 *((volatile uint8_t *)(0x42DE2518UL)) +#define bFM4_GPIO_PCRA_P6 *((volatile uint8_t *)(0x42DE2518UL)) +#define bFM_GPIO_PCRA_P7 *((volatile uint8_t *)(0x42DE251CUL)) +#define bFM4_GPIO_PCRA_P7 *((volatile uint8_t *)(0x42DE251CUL)) +#define bFM_GPIO_PCRA_P8 *((volatile uint8_t *)(0x42DE2520UL)) +#define bFM4_GPIO_PCRA_P8 *((volatile uint8_t *)(0x42DE2520UL)) +#define bFM_GPIO_PCRA_P9 *((volatile uint8_t *)(0x42DE2524UL)) +#define bFM4_GPIO_PCRA_P9 *((volatile uint8_t *)(0x42DE2524UL)) +#define bFM_GPIO_PCRA_PA *((volatile uint8_t *)(0x42DE2528UL)) +#define bFM4_GPIO_PCRA_PA *((volatile uint8_t *)(0x42DE2528UL)) +#define bFM_GPIO_PCRA_PB *((volatile uint8_t *)(0x42DE252CUL)) +#define bFM4_GPIO_PCRA_PB *((volatile uint8_t *)(0x42DE252CUL)) +#define bFM_GPIO_PCRA_PC *((volatile uint8_t *)(0x42DE2530UL)) +#define bFM4_GPIO_PCRA_PC *((volatile uint8_t *)(0x42DE2530UL)) +#define bFM_GPIO_PCRA_PD *((volatile uint8_t *)(0x42DE2534UL)) +#define bFM4_GPIO_PCRA_PD *((volatile uint8_t *)(0x42DE2534UL)) +#define bFM_GPIO_PCRA_PE *((volatile uint8_t *)(0x42DE2538UL)) +#define bFM4_GPIO_PCRA_PE *((volatile uint8_t *)(0x42DE2538UL)) +#define bFM_GPIO_PCRA_PF *((volatile uint8_t *)(0x42DE253CUL)) +#define bFM4_GPIO_PCRA_PF *((volatile uint8_t *)(0x42DE253CUL)) + +#define bFM_GPIO_PCRB_P0 *((volatile uint8_t *)(0x42DE2580UL)) +#define bFM4_GPIO_PCRB_P0 *((volatile uint8_t *)(0x42DE2580UL)) +#define bFM_GPIO_PCRB_P1 *((volatile uint8_t *)(0x42DE2584UL)) +#define bFM4_GPIO_PCRB_P1 *((volatile uint8_t *)(0x42DE2584UL)) +#define bFM_GPIO_PCRB_P2 *((volatile uint8_t *)(0x42DE2588UL)) +#define bFM4_GPIO_PCRB_P2 *((volatile uint8_t *)(0x42DE2588UL)) +#define bFM_GPIO_PCRB_P3 *((volatile uint8_t *)(0x42DE258CUL)) +#define bFM4_GPIO_PCRB_P3 *((volatile uint8_t *)(0x42DE258CUL)) +#define bFM_GPIO_PCRB_P4 *((volatile uint8_t *)(0x42DE2590UL)) +#define bFM4_GPIO_PCRB_P4 *((volatile uint8_t *)(0x42DE2590UL)) +#define bFM_GPIO_PCRB_P5 *((volatile uint8_t *)(0x42DE2594UL)) +#define bFM4_GPIO_PCRB_P5 *((volatile uint8_t *)(0x42DE2594UL)) +#define bFM_GPIO_PCRB_P6 *((volatile uint8_t *)(0x42DE2598UL)) +#define bFM4_GPIO_PCRB_P6 *((volatile uint8_t *)(0x42DE2598UL)) +#define bFM_GPIO_PCRB_P7 *((volatile uint8_t *)(0x42DE259CUL)) +#define bFM4_GPIO_PCRB_P7 *((volatile uint8_t *)(0x42DE259CUL)) +#define bFM_GPIO_PCRB_P8 *((volatile uint8_t *)(0x42DE25A0UL)) +#define bFM4_GPIO_PCRB_P8 *((volatile uint8_t *)(0x42DE25A0UL)) +#define bFM_GPIO_PCRB_P9 *((volatile uint8_t *)(0x42DE25A4UL)) +#define bFM4_GPIO_PCRB_P9 *((volatile uint8_t *)(0x42DE25A4UL)) +#define bFM_GPIO_PCRB_PA *((volatile uint8_t *)(0x42DE25A8UL)) +#define bFM4_GPIO_PCRB_PA *((volatile uint8_t *)(0x42DE25A8UL)) +#define bFM_GPIO_PCRB_PB *((volatile uint8_t *)(0x42DE25ACUL)) +#define bFM4_GPIO_PCRB_PB *((volatile uint8_t *)(0x42DE25ACUL)) +#define bFM_GPIO_PCRB_PC *((volatile uint8_t *)(0x42DE25B0UL)) +#define bFM4_GPIO_PCRB_PC *((volatile uint8_t *)(0x42DE25B0UL)) +#define bFM_GPIO_PCRB_PD *((volatile uint8_t *)(0x42DE25B4UL)) +#define bFM4_GPIO_PCRB_PD *((volatile uint8_t *)(0x42DE25B4UL)) +#define bFM_GPIO_PCRB_PE *((volatile uint8_t *)(0x42DE25B8UL)) +#define bFM4_GPIO_PCRB_PE *((volatile uint8_t *)(0x42DE25B8UL)) +#define bFM_GPIO_PCRB_PF *((volatile uint8_t *)(0x42DE25BCUL)) +#define bFM4_GPIO_PCRB_PF *((volatile uint8_t *)(0x42DE25BCUL)) + +#define bFM_GPIO_PCRC_P0 *((volatile uint8_t *)(0x42DE2600UL)) +#define bFM4_GPIO_PCRC_P0 *((volatile uint8_t *)(0x42DE2600UL)) +#define bFM_GPIO_PCRC_P1 *((volatile uint8_t *)(0x42DE2604UL)) +#define bFM4_GPIO_PCRC_P1 *((volatile uint8_t *)(0x42DE2604UL)) +#define bFM_GPIO_PCRC_P2 *((volatile uint8_t *)(0x42DE2608UL)) +#define bFM4_GPIO_PCRC_P2 *((volatile uint8_t *)(0x42DE2608UL)) +#define bFM_GPIO_PCRC_P3 *((volatile uint8_t *)(0x42DE260CUL)) +#define bFM4_GPIO_PCRC_P3 *((volatile uint8_t *)(0x42DE260CUL)) +#define bFM_GPIO_PCRC_P4 *((volatile uint8_t *)(0x42DE2610UL)) +#define bFM4_GPIO_PCRC_P4 *((volatile uint8_t *)(0x42DE2610UL)) +#define bFM_GPIO_PCRC_P5 *((volatile uint8_t *)(0x42DE2614UL)) +#define bFM4_GPIO_PCRC_P5 *((volatile uint8_t *)(0x42DE2614UL)) +#define bFM_GPIO_PCRC_P6 *((volatile uint8_t *)(0x42DE2618UL)) +#define bFM4_GPIO_PCRC_P6 *((volatile uint8_t *)(0x42DE2618UL)) +#define bFM_GPIO_PCRC_P7 *((volatile uint8_t *)(0x42DE261CUL)) +#define bFM4_GPIO_PCRC_P7 *((volatile uint8_t *)(0x42DE261CUL)) +#define bFM_GPIO_PCRC_P8 *((volatile uint8_t *)(0x42DE2620UL)) +#define bFM4_GPIO_PCRC_P8 *((volatile uint8_t *)(0x42DE2620UL)) +#define bFM_GPIO_PCRC_P9 *((volatile uint8_t *)(0x42DE2624UL)) +#define bFM4_GPIO_PCRC_P9 *((volatile uint8_t *)(0x42DE2624UL)) +#define bFM_GPIO_PCRC_PA *((volatile uint8_t *)(0x42DE2628UL)) +#define bFM4_GPIO_PCRC_PA *((volatile uint8_t *)(0x42DE2628UL)) +#define bFM_GPIO_PCRC_PB *((volatile uint8_t *)(0x42DE262CUL)) +#define bFM4_GPIO_PCRC_PB *((volatile uint8_t *)(0x42DE262CUL)) +#define bFM_GPIO_PCRC_PC *((volatile uint8_t *)(0x42DE2630UL)) +#define bFM4_GPIO_PCRC_PC *((volatile uint8_t *)(0x42DE2630UL)) +#define bFM_GPIO_PCRC_PD *((volatile uint8_t *)(0x42DE2634UL)) +#define bFM4_GPIO_PCRC_PD *((volatile uint8_t *)(0x42DE2634UL)) +#define bFM_GPIO_PCRC_PE *((volatile uint8_t *)(0x42DE2638UL)) +#define bFM4_GPIO_PCRC_PE *((volatile uint8_t *)(0x42DE2638UL)) +#define bFM_GPIO_PCRC_PF *((volatile uint8_t *)(0x42DE263CUL)) +#define bFM4_GPIO_PCRC_PF *((volatile uint8_t *)(0x42DE263CUL)) + +#define bFM_GPIO_PCRD_P0 *((volatile uint8_t *)(0x42DE2680UL)) +#define bFM4_GPIO_PCRD_P0 *((volatile uint8_t *)(0x42DE2680UL)) +#define bFM_GPIO_PCRD_P1 *((volatile uint8_t *)(0x42DE2684UL)) +#define bFM4_GPIO_PCRD_P1 *((volatile uint8_t *)(0x42DE2684UL)) +#define bFM_GPIO_PCRD_P2 *((volatile uint8_t *)(0x42DE2688UL)) +#define bFM4_GPIO_PCRD_P2 *((volatile uint8_t *)(0x42DE2688UL)) + +#define bFM_GPIO_PCRE_P0 *((volatile uint8_t *)(0x42DE2700UL)) +#define bFM4_GPIO_PCRE_P0 *((volatile uint8_t *)(0x42DE2700UL)) +#define bFM_GPIO_PCRE_P2 *((volatile uint8_t *)(0x42DE2708UL)) +#define bFM4_GPIO_PCRE_P2 *((volatile uint8_t *)(0x42DE2708UL)) +#define bFM_GPIO_PCRE_P3 *((volatile uint8_t *)(0x42DE270CUL)) +#define bFM4_GPIO_PCRE_P3 *((volatile uint8_t *)(0x42DE270CUL)) + +#define bFM_GPIO_PCRF_P0 *((volatile uint8_t *)(0x42DE2780UL)) +#define bFM4_GPIO_PCRF_P0 *((volatile uint8_t *)(0x42DE2780UL)) +#define bFM_GPIO_PCRF_P1 *((volatile uint8_t *)(0x42DE2784UL)) +#define bFM4_GPIO_PCRF_P1 *((volatile uint8_t *)(0x42DE2784UL)) +#define bFM_GPIO_PCRF_P2 *((volatile uint8_t *)(0x42DE2788UL)) +#define bFM4_GPIO_PCRF_P2 *((volatile uint8_t *)(0x42DE2788UL)) +#define bFM_GPIO_PCRF_P3 *((volatile uint8_t *)(0x42DE278CUL)) +#define bFM4_GPIO_PCRF_P3 *((volatile uint8_t *)(0x42DE278CUL)) +#define bFM_GPIO_PCRF_P4 *((volatile uint8_t *)(0x42DE2790UL)) +#define bFM4_GPIO_PCRF_P4 *((volatile uint8_t *)(0x42DE2790UL)) +#define bFM_GPIO_PCRF_P5 *((volatile uint8_t *)(0x42DE2794UL)) +#define bFM4_GPIO_PCRF_P5 *((volatile uint8_t *)(0x42DE2794UL)) +#define bFM_GPIO_PCRF_P6 *((volatile uint8_t *)(0x42DE2798UL)) +#define bFM4_GPIO_PCRF_P6 *((volatile uint8_t *)(0x42DE2798UL)) +#define bFM_GPIO_PCRF_P7 *((volatile uint8_t *)(0x42DE279CUL)) +#define bFM4_GPIO_PCRF_P7 *((volatile uint8_t *)(0x42DE279CUL)) +#define bFM_GPIO_PCRF_P8 *((volatile uint8_t *)(0x42DE27A0UL)) +#define bFM4_GPIO_PCRF_P8 *((volatile uint8_t *)(0x42DE27A0UL)) +#define bFM_GPIO_PCRF_P9 *((volatile uint8_t *)(0x42DE27A4UL)) +#define bFM4_GPIO_PCRF_P9 *((volatile uint8_t *)(0x42DE27A4UL)) +#define bFM_GPIO_PCRF_PA *((volatile uint8_t *)(0x42DE27A8UL)) +#define bFM4_GPIO_PCRF_PA *((volatile uint8_t *)(0x42DE27A8UL)) +#define bFM_GPIO_PCRF_PB *((volatile uint8_t *)(0x42DE27ACUL)) +#define bFM4_GPIO_PCRF_PB *((volatile uint8_t *)(0x42DE27ACUL)) +#define bFM_GPIO_PCRF_PC *((volatile uint8_t *)(0x42DE27B0UL)) +#define bFM4_GPIO_PCRF_PC *((volatile uint8_t *)(0x42DE27B0UL)) + +#define bFM_GPIO_PDIR0_P0 *((volatile uint8_t *)(0x42DE6000UL)) +#define bFM4_GPIO_PDIR0_P0 *((volatile uint8_t *)(0x42DE6000UL)) +#define bFM_GPIO_PDIR0_P1 *((volatile uint8_t *)(0x42DE6004UL)) +#define bFM4_GPIO_PDIR0_P1 *((volatile uint8_t *)(0x42DE6004UL)) +#define bFM_GPIO_PDIR0_P2 *((volatile uint8_t *)(0x42DE6008UL)) +#define bFM4_GPIO_PDIR0_P2 *((volatile uint8_t *)(0x42DE6008UL)) +#define bFM_GPIO_PDIR0_P3 *((volatile uint8_t *)(0x42DE600CUL)) +#define bFM4_GPIO_PDIR0_P3 *((volatile uint8_t *)(0x42DE600CUL)) +#define bFM_GPIO_PDIR0_P4 *((volatile uint8_t *)(0x42DE6010UL)) +#define bFM4_GPIO_PDIR0_P4 *((volatile uint8_t *)(0x42DE6010UL)) +#define bFM_GPIO_PDIR0_P8 *((volatile uint8_t *)(0x42DE6020UL)) +#define bFM4_GPIO_PDIR0_P8 *((volatile uint8_t *)(0x42DE6020UL)) +#define bFM_GPIO_PDIR0_P9 *((volatile uint8_t *)(0x42DE6024UL)) +#define bFM4_GPIO_PDIR0_P9 *((volatile uint8_t *)(0x42DE6024UL)) +#define bFM_GPIO_PDIR0_PA *((volatile uint8_t *)(0x42DE6028UL)) +#define bFM4_GPIO_PDIR0_PA *((volatile uint8_t *)(0x42DE6028UL)) + +#define bFM_GPIO_PDIR1_P0 *((volatile uint8_t *)(0x42DE6080UL)) +#define bFM4_GPIO_PDIR1_P0 *((volatile uint8_t *)(0x42DE6080UL)) +#define bFM_GPIO_PDIR1_P1 *((volatile uint8_t *)(0x42DE6084UL)) +#define bFM4_GPIO_PDIR1_P1 *((volatile uint8_t *)(0x42DE6084UL)) +#define bFM_GPIO_PDIR1_P2 *((volatile uint8_t *)(0x42DE6088UL)) +#define bFM4_GPIO_PDIR1_P2 *((volatile uint8_t *)(0x42DE6088UL)) +#define bFM_GPIO_PDIR1_P3 *((volatile uint8_t *)(0x42DE608CUL)) +#define bFM4_GPIO_PDIR1_P3 *((volatile uint8_t *)(0x42DE608CUL)) +#define bFM_GPIO_PDIR1_P4 *((volatile uint8_t *)(0x42DE6090UL)) +#define bFM4_GPIO_PDIR1_P4 *((volatile uint8_t *)(0x42DE6090UL)) +#define bFM_GPIO_PDIR1_P5 *((volatile uint8_t *)(0x42DE6094UL)) +#define bFM4_GPIO_PDIR1_P5 *((volatile uint8_t *)(0x42DE6094UL)) +#define bFM_GPIO_PDIR1_P6 *((volatile uint8_t *)(0x42DE6098UL)) +#define bFM4_GPIO_PDIR1_P6 *((volatile uint8_t *)(0x42DE6098UL)) +#define bFM_GPIO_PDIR1_P7 *((volatile uint8_t *)(0x42DE609CUL)) +#define bFM4_GPIO_PDIR1_P7 *((volatile uint8_t *)(0x42DE609CUL)) +#define bFM_GPIO_PDIR1_P8 *((volatile uint8_t *)(0x42DE60A0UL)) +#define bFM4_GPIO_PDIR1_P8 *((volatile uint8_t *)(0x42DE60A0UL)) +#define bFM_GPIO_PDIR1_P9 *((volatile uint8_t *)(0x42DE60A4UL)) +#define bFM4_GPIO_PDIR1_P9 *((volatile uint8_t *)(0x42DE60A4UL)) +#define bFM_GPIO_PDIR1_PA *((volatile uint8_t *)(0x42DE60A8UL)) +#define bFM4_GPIO_PDIR1_PA *((volatile uint8_t *)(0x42DE60A8UL)) +#define bFM_GPIO_PDIR1_PB *((volatile uint8_t *)(0x42DE60ACUL)) +#define bFM4_GPIO_PDIR1_PB *((volatile uint8_t *)(0x42DE60ACUL)) +#define bFM_GPIO_PDIR1_PC *((volatile uint8_t *)(0x42DE60B0UL)) +#define bFM4_GPIO_PDIR1_PC *((volatile uint8_t *)(0x42DE60B0UL)) +#define bFM_GPIO_PDIR1_PD *((volatile uint8_t *)(0x42DE60B4UL)) +#define bFM4_GPIO_PDIR1_PD *((volatile uint8_t *)(0x42DE60B4UL)) +#define bFM_GPIO_PDIR1_PE *((volatile uint8_t *)(0x42DE60B8UL)) +#define bFM4_GPIO_PDIR1_PE *((volatile uint8_t *)(0x42DE60B8UL)) +#define bFM_GPIO_PDIR1_PF *((volatile uint8_t *)(0x42DE60BCUL)) +#define bFM4_GPIO_PDIR1_PF *((volatile uint8_t *)(0x42DE60BCUL)) + +#define bFM_GPIO_PDIR2_P0 *((volatile uint8_t *)(0x42DE6100UL)) +#define bFM4_GPIO_PDIR2_P0 *((volatile uint8_t *)(0x42DE6100UL)) +#define bFM_GPIO_PDIR2_P1 *((volatile uint8_t *)(0x42DE6104UL)) +#define bFM4_GPIO_PDIR2_P1 *((volatile uint8_t *)(0x42DE6104UL)) +#define bFM_GPIO_PDIR2_P2 *((volatile uint8_t *)(0x42DE6108UL)) +#define bFM4_GPIO_PDIR2_P2 *((volatile uint8_t *)(0x42DE6108UL)) +#define bFM_GPIO_PDIR2_P3 *((volatile uint8_t *)(0x42DE610CUL)) +#define bFM4_GPIO_PDIR2_P3 *((volatile uint8_t *)(0x42DE610CUL)) +#define bFM_GPIO_PDIR2_P4 *((volatile uint8_t *)(0x42DE6110UL)) +#define bFM4_GPIO_PDIR2_P4 *((volatile uint8_t *)(0x42DE6110UL)) +#define bFM_GPIO_PDIR2_P5 *((volatile uint8_t *)(0x42DE6114UL)) +#define bFM4_GPIO_PDIR2_P5 *((volatile uint8_t *)(0x42DE6114UL)) +#define bFM_GPIO_PDIR2_P6 *((volatile uint8_t *)(0x42DE6118UL)) +#define bFM4_GPIO_PDIR2_P6 *((volatile uint8_t *)(0x42DE6118UL)) +#define bFM_GPIO_PDIR2_P7 *((volatile uint8_t *)(0x42DE611CUL)) +#define bFM4_GPIO_PDIR2_P7 *((volatile uint8_t *)(0x42DE611CUL)) +#define bFM_GPIO_PDIR2_P8 *((volatile uint8_t *)(0x42DE6120UL)) +#define bFM4_GPIO_PDIR2_P8 *((volatile uint8_t *)(0x42DE6120UL)) +#define bFM_GPIO_PDIR2_P9 *((volatile uint8_t *)(0x42DE6124UL)) +#define bFM4_GPIO_PDIR2_P9 *((volatile uint8_t *)(0x42DE6124UL)) +#define bFM_GPIO_PDIR2_PA *((volatile uint8_t *)(0x42DE6128UL)) +#define bFM4_GPIO_PDIR2_PA *((volatile uint8_t *)(0x42DE6128UL)) + +#define bFM_GPIO_PDIR3_P0 *((volatile uint8_t *)(0x42DE6180UL)) +#define bFM4_GPIO_PDIR3_P0 *((volatile uint8_t *)(0x42DE6180UL)) +#define bFM_GPIO_PDIR3_P1 *((volatile uint8_t *)(0x42DE6184UL)) +#define bFM4_GPIO_PDIR3_P1 *((volatile uint8_t *)(0x42DE6184UL)) +#define bFM_GPIO_PDIR3_P2 *((volatile uint8_t *)(0x42DE6188UL)) +#define bFM4_GPIO_PDIR3_P2 *((volatile uint8_t *)(0x42DE6188UL)) +#define bFM_GPIO_PDIR3_P3 *((volatile uint8_t *)(0x42DE618CUL)) +#define bFM4_GPIO_PDIR3_P3 *((volatile uint8_t *)(0x42DE618CUL)) +#define bFM_GPIO_PDIR3_P4 *((volatile uint8_t *)(0x42DE6190UL)) +#define bFM4_GPIO_PDIR3_P4 *((volatile uint8_t *)(0x42DE6190UL)) +#define bFM_GPIO_PDIR3_P5 *((volatile uint8_t *)(0x42DE6194UL)) +#define bFM4_GPIO_PDIR3_P5 *((volatile uint8_t *)(0x42DE6194UL)) +#define bFM_GPIO_PDIR3_P6 *((volatile uint8_t *)(0x42DE6198UL)) +#define bFM4_GPIO_PDIR3_P6 *((volatile uint8_t *)(0x42DE6198UL)) +#define bFM_GPIO_PDIR3_P7 *((volatile uint8_t *)(0x42DE619CUL)) +#define bFM4_GPIO_PDIR3_P7 *((volatile uint8_t *)(0x42DE619CUL)) +#define bFM_GPIO_PDIR3_P8 *((volatile uint8_t *)(0x42DE61A0UL)) +#define bFM4_GPIO_PDIR3_P8 *((volatile uint8_t *)(0x42DE61A0UL)) +#define bFM_GPIO_PDIR3_P9 *((volatile uint8_t *)(0x42DE61A4UL)) +#define bFM4_GPIO_PDIR3_P9 *((volatile uint8_t *)(0x42DE61A4UL)) +#define bFM_GPIO_PDIR3_PA *((volatile uint8_t *)(0x42DE61A8UL)) +#define bFM4_GPIO_PDIR3_PA *((volatile uint8_t *)(0x42DE61A8UL)) +#define bFM_GPIO_PDIR3_PB *((volatile uint8_t *)(0x42DE61ACUL)) +#define bFM4_GPIO_PDIR3_PB *((volatile uint8_t *)(0x42DE61ACUL)) +#define bFM_GPIO_PDIR3_PC *((volatile uint8_t *)(0x42DE61B0UL)) +#define bFM4_GPIO_PDIR3_PC *((volatile uint8_t *)(0x42DE61B0UL)) +#define bFM_GPIO_PDIR3_PD *((volatile uint8_t *)(0x42DE61B4UL)) +#define bFM4_GPIO_PDIR3_PD *((volatile uint8_t *)(0x42DE61B4UL)) +#define bFM_GPIO_PDIR3_PE *((volatile uint8_t *)(0x42DE61B8UL)) +#define bFM4_GPIO_PDIR3_PE *((volatile uint8_t *)(0x42DE61B8UL)) + +#define bFM_GPIO_PDIR4_P0 *((volatile uint8_t *)(0x42DE6200UL)) +#define bFM4_GPIO_PDIR4_P0 *((volatile uint8_t *)(0x42DE6200UL)) +#define bFM_GPIO_PDIR4_P1 *((volatile uint8_t *)(0x42DE6204UL)) +#define bFM4_GPIO_PDIR4_P1 *((volatile uint8_t *)(0x42DE6204UL)) +#define bFM_GPIO_PDIR4_P2 *((volatile uint8_t *)(0x42DE6208UL)) +#define bFM4_GPIO_PDIR4_P2 *((volatile uint8_t *)(0x42DE6208UL)) +#define bFM_GPIO_PDIR4_P3 *((volatile uint8_t *)(0x42DE620CUL)) +#define bFM4_GPIO_PDIR4_P3 *((volatile uint8_t *)(0x42DE620CUL)) +#define bFM_GPIO_PDIR4_P4 *((volatile uint8_t *)(0x42DE6210UL)) +#define bFM4_GPIO_PDIR4_P4 *((volatile uint8_t *)(0x42DE6210UL)) +#define bFM_GPIO_PDIR4_P5 *((volatile uint8_t *)(0x42DE6214UL)) +#define bFM4_GPIO_PDIR4_P5 *((volatile uint8_t *)(0x42DE6214UL)) +#define bFM_GPIO_PDIR4_P6 *((volatile uint8_t *)(0x42DE6218UL)) +#define bFM4_GPIO_PDIR4_P6 *((volatile uint8_t *)(0x42DE6218UL)) +#define bFM_GPIO_PDIR4_P7 *((volatile uint8_t *)(0x42DE621CUL)) +#define bFM4_GPIO_PDIR4_P7 *((volatile uint8_t *)(0x42DE621CUL)) +#define bFM_GPIO_PDIR4_P8 *((volatile uint8_t *)(0x42DE6220UL)) +#define bFM4_GPIO_PDIR4_P8 *((volatile uint8_t *)(0x42DE6220UL)) +#define bFM_GPIO_PDIR4_P9 *((volatile uint8_t *)(0x42DE6224UL)) +#define bFM4_GPIO_PDIR4_P9 *((volatile uint8_t *)(0x42DE6224UL)) +#define bFM_GPIO_PDIR4_PA *((volatile uint8_t *)(0x42DE6228UL)) +#define bFM4_GPIO_PDIR4_PA *((volatile uint8_t *)(0x42DE6228UL)) +#define bFM_GPIO_PDIR4_PB *((volatile uint8_t *)(0x42DE622CUL)) +#define bFM4_GPIO_PDIR4_PB *((volatile uint8_t *)(0x42DE622CUL)) +#define bFM_GPIO_PDIR4_PC *((volatile uint8_t *)(0x42DE6230UL)) +#define bFM4_GPIO_PDIR4_PC *((volatile uint8_t *)(0x42DE6230UL)) +#define bFM_GPIO_PDIR4_PD *((volatile uint8_t *)(0x42DE6234UL)) +#define bFM4_GPIO_PDIR4_PD *((volatile uint8_t *)(0x42DE6234UL)) +#define bFM_GPIO_PDIR4_PE *((volatile uint8_t *)(0x42DE6238UL)) +#define bFM4_GPIO_PDIR4_PE *((volatile uint8_t *)(0x42DE6238UL)) + +#define bFM_GPIO_PDIR5_P0 *((volatile uint8_t *)(0x42DE6280UL)) +#define bFM4_GPIO_PDIR5_P0 *((volatile uint8_t *)(0x42DE6280UL)) +#define bFM_GPIO_PDIR5_P1 *((volatile uint8_t *)(0x42DE6284UL)) +#define bFM4_GPIO_PDIR5_P1 *((volatile uint8_t *)(0x42DE6284UL)) +#define bFM_GPIO_PDIR5_P2 *((volatile uint8_t *)(0x42DE6288UL)) +#define bFM4_GPIO_PDIR5_P2 *((volatile uint8_t *)(0x42DE6288UL)) +#define bFM_GPIO_PDIR5_P3 *((volatile uint8_t *)(0x42DE628CUL)) +#define bFM4_GPIO_PDIR5_P3 *((volatile uint8_t *)(0x42DE628CUL)) +#define bFM_GPIO_PDIR5_P4 *((volatile uint8_t *)(0x42DE6290UL)) +#define bFM4_GPIO_PDIR5_P4 *((volatile uint8_t *)(0x42DE6290UL)) +#define bFM_GPIO_PDIR5_P5 *((volatile uint8_t *)(0x42DE6294UL)) +#define bFM4_GPIO_PDIR5_P5 *((volatile uint8_t *)(0x42DE6294UL)) +#define bFM_GPIO_PDIR5_P6 *((volatile uint8_t *)(0x42DE6298UL)) +#define bFM4_GPIO_PDIR5_P6 *((volatile uint8_t *)(0x42DE6298UL)) +#define bFM_GPIO_PDIR5_P7 *((volatile uint8_t *)(0x42DE629CUL)) +#define bFM4_GPIO_PDIR5_P7 *((volatile uint8_t *)(0x42DE629CUL)) +#define bFM_GPIO_PDIR5_P8 *((volatile uint8_t *)(0x42DE62A0UL)) +#define bFM4_GPIO_PDIR5_P8 *((volatile uint8_t *)(0x42DE62A0UL)) +#define bFM_GPIO_PDIR5_P9 *((volatile uint8_t *)(0x42DE62A4UL)) +#define bFM4_GPIO_PDIR5_P9 *((volatile uint8_t *)(0x42DE62A4UL)) +#define bFM_GPIO_PDIR5_PA *((volatile uint8_t *)(0x42DE62A8UL)) +#define bFM4_GPIO_PDIR5_PA *((volatile uint8_t *)(0x42DE62A8UL)) +#define bFM_GPIO_PDIR5_PB *((volatile uint8_t *)(0x42DE62ACUL)) +#define bFM4_GPIO_PDIR5_PB *((volatile uint8_t *)(0x42DE62ACUL)) +#define bFM_GPIO_PDIR5_PC *((volatile uint8_t *)(0x42DE62B0UL)) +#define bFM4_GPIO_PDIR5_PC *((volatile uint8_t *)(0x42DE62B0UL)) +#define bFM_GPIO_PDIR5_PD *((volatile uint8_t *)(0x42DE62B4UL)) +#define bFM4_GPIO_PDIR5_PD *((volatile uint8_t *)(0x42DE62B4UL)) +#define bFM_GPIO_PDIR5_PE *((volatile uint8_t *)(0x42DE62B8UL)) +#define bFM4_GPIO_PDIR5_PE *((volatile uint8_t *)(0x42DE62B8UL)) +#define bFM_GPIO_PDIR5_PF *((volatile uint8_t *)(0x42DE62BCUL)) +#define bFM4_GPIO_PDIR5_PF *((volatile uint8_t *)(0x42DE62BCUL)) + +#define bFM_GPIO_PDIR6_P0 *((volatile uint8_t *)(0x42DE6300UL)) +#define bFM4_GPIO_PDIR6_P0 *((volatile uint8_t *)(0x42DE6300UL)) +#define bFM_GPIO_PDIR6_P1 *((volatile uint8_t *)(0x42DE6304UL)) +#define bFM4_GPIO_PDIR6_P1 *((volatile uint8_t *)(0x42DE6304UL)) +#define bFM_GPIO_PDIR6_P2 *((volatile uint8_t *)(0x42DE6308UL)) +#define bFM4_GPIO_PDIR6_P2 *((volatile uint8_t *)(0x42DE6308UL)) +#define bFM_GPIO_PDIR6_P3 *((volatile uint8_t *)(0x42DE630CUL)) +#define bFM4_GPIO_PDIR6_P3 *((volatile uint8_t *)(0x42DE630CUL)) +#define bFM_GPIO_PDIR6_P4 *((volatile uint8_t *)(0x42DE6310UL)) +#define bFM4_GPIO_PDIR6_P4 *((volatile uint8_t *)(0x42DE6310UL)) +#define bFM_GPIO_PDIR6_P5 *((volatile uint8_t *)(0x42DE6314UL)) +#define bFM4_GPIO_PDIR6_P5 *((volatile uint8_t *)(0x42DE6314UL)) +#define bFM_GPIO_PDIR6_P6 *((volatile uint8_t *)(0x42DE6318UL)) +#define bFM4_GPIO_PDIR6_P6 *((volatile uint8_t *)(0x42DE6318UL)) +#define bFM_GPIO_PDIR6_P7 *((volatile uint8_t *)(0x42DE631CUL)) +#define bFM4_GPIO_PDIR6_P7 *((volatile uint8_t *)(0x42DE631CUL)) +#define bFM_GPIO_PDIR6_P8 *((volatile uint8_t *)(0x42DE6320UL)) +#define bFM4_GPIO_PDIR6_P8 *((volatile uint8_t *)(0x42DE6320UL)) +#define bFM_GPIO_PDIR6_P9 *((volatile uint8_t *)(0x42DE6324UL)) +#define bFM4_GPIO_PDIR6_P9 *((volatile uint8_t *)(0x42DE6324UL)) +#define bFM_GPIO_PDIR6_PA *((volatile uint8_t *)(0x42DE6328UL)) +#define bFM4_GPIO_PDIR6_PA *((volatile uint8_t *)(0x42DE6328UL)) +#define bFM_GPIO_PDIR6_PB *((volatile uint8_t *)(0x42DE632CUL)) +#define bFM4_GPIO_PDIR6_PB *((volatile uint8_t *)(0x42DE632CUL)) +#define bFM_GPIO_PDIR6_PC *((volatile uint8_t *)(0x42DE6330UL)) +#define bFM4_GPIO_PDIR6_PC *((volatile uint8_t *)(0x42DE6330UL)) +#define bFM_GPIO_PDIR6_PD *((volatile uint8_t *)(0x42DE6334UL)) +#define bFM4_GPIO_PDIR6_PD *((volatile uint8_t *)(0x42DE6334UL)) +#define bFM_GPIO_PDIR6_PE *((volatile uint8_t *)(0x42DE6338UL)) +#define bFM4_GPIO_PDIR6_PE *((volatile uint8_t *)(0x42DE6338UL)) + +#define bFM_GPIO_PDIR7_P0 *((volatile uint8_t *)(0x42DE6380UL)) +#define bFM4_GPIO_PDIR7_P0 *((volatile uint8_t *)(0x42DE6380UL)) +#define bFM_GPIO_PDIR7_P1 *((volatile uint8_t *)(0x42DE6384UL)) +#define bFM4_GPIO_PDIR7_P1 *((volatile uint8_t *)(0x42DE6384UL)) +#define bFM_GPIO_PDIR7_P2 *((volatile uint8_t *)(0x42DE6388UL)) +#define bFM4_GPIO_PDIR7_P2 *((volatile uint8_t *)(0x42DE6388UL)) +#define bFM_GPIO_PDIR7_P3 *((volatile uint8_t *)(0x42DE638CUL)) +#define bFM4_GPIO_PDIR7_P3 *((volatile uint8_t *)(0x42DE638CUL)) +#define bFM_GPIO_PDIR7_P4 *((volatile uint8_t *)(0x42DE6390UL)) +#define bFM4_GPIO_PDIR7_P4 *((volatile uint8_t *)(0x42DE6390UL)) +#define bFM_GPIO_PDIR7_P5 *((volatile uint8_t *)(0x42DE6394UL)) +#define bFM4_GPIO_PDIR7_P5 *((volatile uint8_t *)(0x42DE6394UL)) +#define bFM_GPIO_PDIR7_P6 *((volatile uint8_t *)(0x42DE6398UL)) +#define bFM4_GPIO_PDIR7_P6 *((volatile uint8_t *)(0x42DE6398UL)) +#define bFM_GPIO_PDIR7_P7 *((volatile uint8_t *)(0x42DE639CUL)) +#define bFM4_GPIO_PDIR7_P7 *((volatile uint8_t *)(0x42DE639CUL)) +#define bFM_GPIO_PDIR7_P8 *((volatile uint8_t *)(0x42DE63A0UL)) +#define bFM4_GPIO_PDIR7_P8 *((volatile uint8_t *)(0x42DE63A0UL)) +#define bFM_GPIO_PDIR7_P9 *((volatile uint8_t *)(0x42DE63A4UL)) +#define bFM4_GPIO_PDIR7_P9 *((volatile uint8_t *)(0x42DE63A4UL)) +#define bFM_GPIO_PDIR7_PA *((volatile uint8_t *)(0x42DE63A8UL)) +#define bFM4_GPIO_PDIR7_PA *((volatile uint8_t *)(0x42DE63A8UL)) +#define bFM_GPIO_PDIR7_PB *((volatile uint8_t *)(0x42DE63ACUL)) +#define bFM4_GPIO_PDIR7_PB *((volatile uint8_t *)(0x42DE63ACUL)) +#define bFM_GPIO_PDIR7_PC *((volatile uint8_t *)(0x42DE63B0UL)) +#define bFM4_GPIO_PDIR7_PC *((volatile uint8_t *)(0x42DE63B0UL)) +#define bFM_GPIO_PDIR7_PD *((volatile uint8_t *)(0x42DE63B4UL)) +#define bFM4_GPIO_PDIR7_PD *((volatile uint8_t *)(0x42DE63B4UL)) +#define bFM_GPIO_PDIR7_PE *((volatile uint8_t *)(0x42DE63B8UL)) +#define bFM4_GPIO_PDIR7_PE *((volatile uint8_t *)(0x42DE63B8UL)) + +#define bFM_GPIO_PDIR8_P0 *((volatile uint8_t *)(0x42DE6400UL)) +#define bFM4_GPIO_PDIR8_P0 *((volatile uint8_t *)(0x42DE6400UL)) +#define bFM_GPIO_PDIR8_P1 *((volatile uint8_t *)(0x42DE6404UL)) +#define bFM4_GPIO_PDIR8_P1 *((volatile uint8_t *)(0x42DE6404UL)) +#define bFM_GPIO_PDIR8_P2 *((volatile uint8_t *)(0x42DE6408UL)) +#define bFM4_GPIO_PDIR8_P2 *((volatile uint8_t *)(0x42DE6408UL)) +#define bFM_GPIO_PDIR8_P3 *((volatile uint8_t *)(0x42DE640CUL)) +#define bFM4_GPIO_PDIR8_P3 *((volatile uint8_t *)(0x42DE640CUL)) + +#define bFM_GPIO_PDIR9_P0 *((volatile uint8_t *)(0x42DE6480UL)) +#define bFM4_GPIO_PDIR9_P0 *((volatile uint8_t *)(0x42DE6480UL)) +#define bFM_GPIO_PDIR9_P1 *((volatile uint8_t *)(0x42DE6484UL)) +#define bFM4_GPIO_PDIR9_P1 *((volatile uint8_t *)(0x42DE6484UL)) +#define bFM_GPIO_PDIR9_P2 *((volatile uint8_t *)(0x42DE6488UL)) +#define bFM4_GPIO_PDIR9_P2 *((volatile uint8_t *)(0x42DE6488UL)) +#define bFM_GPIO_PDIR9_P3 *((volatile uint8_t *)(0x42DE648CUL)) +#define bFM4_GPIO_PDIR9_P3 *((volatile uint8_t *)(0x42DE648CUL)) +#define bFM_GPIO_PDIR9_P4 *((volatile uint8_t *)(0x42DE6490UL)) +#define bFM4_GPIO_PDIR9_P4 *((volatile uint8_t *)(0x42DE6490UL)) +#define bFM_GPIO_PDIR9_P5 *((volatile uint8_t *)(0x42DE6494UL)) +#define bFM4_GPIO_PDIR9_P5 *((volatile uint8_t *)(0x42DE6494UL)) +#define bFM_GPIO_PDIR9_P6 *((volatile uint8_t *)(0x42DE6498UL)) +#define bFM4_GPIO_PDIR9_P6 *((volatile uint8_t *)(0x42DE6498UL)) +#define bFM_GPIO_PDIR9_P7 *((volatile uint8_t *)(0x42DE649CUL)) +#define bFM4_GPIO_PDIR9_P7 *((volatile uint8_t *)(0x42DE649CUL)) + +#define bFM_GPIO_PDIRA_P0 *((volatile uint8_t *)(0x42DE6500UL)) +#define bFM4_GPIO_PDIRA_P0 *((volatile uint8_t *)(0x42DE6500UL)) +#define bFM_GPIO_PDIRA_P1 *((volatile uint8_t *)(0x42DE6504UL)) +#define bFM4_GPIO_PDIRA_P1 *((volatile uint8_t *)(0x42DE6504UL)) +#define bFM_GPIO_PDIRA_P2 *((volatile uint8_t *)(0x42DE6508UL)) +#define bFM4_GPIO_PDIRA_P2 *((volatile uint8_t *)(0x42DE6508UL)) +#define bFM_GPIO_PDIRA_P3 *((volatile uint8_t *)(0x42DE650CUL)) +#define bFM4_GPIO_PDIRA_P3 *((volatile uint8_t *)(0x42DE650CUL)) +#define bFM_GPIO_PDIRA_P4 *((volatile uint8_t *)(0x42DE6510UL)) +#define bFM4_GPIO_PDIRA_P4 *((volatile uint8_t *)(0x42DE6510UL)) +#define bFM_GPIO_PDIRA_P5 *((volatile uint8_t *)(0x42DE6514UL)) +#define bFM4_GPIO_PDIRA_P5 *((volatile uint8_t *)(0x42DE6514UL)) +#define bFM_GPIO_PDIRA_P6 *((volatile uint8_t *)(0x42DE6518UL)) +#define bFM4_GPIO_PDIRA_P6 *((volatile uint8_t *)(0x42DE6518UL)) +#define bFM_GPIO_PDIRA_P7 *((volatile uint8_t *)(0x42DE651CUL)) +#define bFM4_GPIO_PDIRA_P7 *((volatile uint8_t *)(0x42DE651CUL)) +#define bFM_GPIO_PDIRA_P8 *((volatile uint8_t *)(0x42DE6520UL)) +#define bFM4_GPIO_PDIRA_P8 *((volatile uint8_t *)(0x42DE6520UL)) +#define bFM_GPIO_PDIRA_P9 *((volatile uint8_t *)(0x42DE6524UL)) +#define bFM4_GPIO_PDIRA_P9 *((volatile uint8_t *)(0x42DE6524UL)) +#define bFM_GPIO_PDIRA_PA *((volatile uint8_t *)(0x42DE6528UL)) +#define bFM4_GPIO_PDIRA_PA *((volatile uint8_t *)(0x42DE6528UL)) +#define bFM_GPIO_PDIRA_PB *((volatile uint8_t *)(0x42DE652CUL)) +#define bFM4_GPIO_PDIRA_PB *((volatile uint8_t *)(0x42DE652CUL)) +#define bFM_GPIO_PDIRA_PC *((volatile uint8_t *)(0x42DE6530UL)) +#define bFM4_GPIO_PDIRA_PC *((volatile uint8_t *)(0x42DE6530UL)) +#define bFM_GPIO_PDIRA_PD *((volatile uint8_t *)(0x42DE6534UL)) +#define bFM4_GPIO_PDIRA_PD *((volatile uint8_t *)(0x42DE6534UL)) +#define bFM_GPIO_PDIRA_PE *((volatile uint8_t *)(0x42DE6538UL)) +#define bFM4_GPIO_PDIRA_PE *((volatile uint8_t *)(0x42DE6538UL)) +#define bFM_GPIO_PDIRA_PF *((volatile uint8_t *)(0x42DE653CUL)) +#define bFM4_GPIO_PDIRA_PF *((volatile uint8_t *)(0x42DE653CUL)) + +#define bFM_GPIO_PDIRB_P0 *((volatile uint8_t *)(0x42DE6580UL)) +#define bFM4_GPIO_PDIRB_P0 *((volatile uint8_t *)(0x42DE6580UL)) +#define bFM_GPIO_PDIRB_P1 *((volatile uint8_t *)(0x42DE6584UL)) +#define bFM4_GPIO_PDIRB_P1 *((volatile uint8_t *)(0x42DE6584UL)) +#define bFM_GPIO_PDIRB_P2 *((volatile uint8_t *)(0x42DE6588UL)) +#define bFM4_GPIO_PDIRB_P2 *((volatile uint8_t *)(0x42DE6588UL)) +#define bFM_GPIO_PDIRB_P3 *((volatile uint8_t *)(0x42DE658CUL)) +#define bFM4_GPIO_PDIRB_P3 *((volatile uint8_t *)(0x42DE658CUL)) +#define bFM_GPIO_PDIRB_P4 *((volatile uint8_t *)(0x42DE6590UL)) +#define bFM4_GPIO_PDIRB_P4 *((volatile uint8_t *)(0x42DE6590UL)) +#define bFM_GPIO_PDIRB_P5 *((volatile uint8_t *)(0x42DE6594UL)) +#define bFM4_GPIO_PDIRB_P5 *((volatile uint8_t *)(0x42DE6594UL)) +#define bFM_GPIO_PDIRB_P6 *((volatile uint8_t *)(0x42DE6598UL)) +#define bFM4_GPIO_PDIRB_P6 *((volatile uint8_t *)(0x42DE6598UL)) +#define bFM_GPIO_PDIRB_P7 *((volatile uint8_t *)(0x42DE659CUL)) +#define bFM4_GPIO_PDIRB_P7 *((volatile uint8_t *)(0x42DE659CUL)) +#define bFM_GPIO_PDIRB_P8 *((volatile uint8_t *)(0x42DE65A0UL)) +#define bFM4_GPIO_PDIRB_P8 *((volatile uint8_t *)(0x42DE65A0UL)) +#define bFM_GPIO_PDIRB_P9 *((volatile uint8_t *)(0x42DE65A4UL)) +#define bFM4_GPIO_PDIRB_P9 *((volatile uint8_t *)(0x42DE65A4UL)) +#define bFM_GPIO_PDIRB_PA *((volatile uint8_t *)(0x42DE65A8UL)) +#define bFM4_GPIO_PDIRB_PA *((volatile uint8_t *)(0x42DE65A8UL)) +#define bFM_GPIO_PDIRB_PB *((volatile uint8_t *)(0x42DE65ACUL)) +#define bFM4_GPIO_PDIRB_PB *((volatile uint8_t *)(0x42DE65ACUL)) +#define bFM_GPIO_PDIRB_PC *((volatile uint8_t *)(0x42DE65B0UL)) +#define bFM4_GPIO_PDIRB_PC *((volatile uint8_t *)(0x42DE65B0UL)) +#define bFM_GPIO_PDIRB_PD *((volatile uint8_t *)(0x42DE65B4UL)) +#define bFM4_GPIO_PDIRB_PD *((volatile uint8_t *)(0x42DE65B4UL)) +#define bFM_GPIO_PDIRB_PE *((volatile uint8_t *)(0x42DE65B8UL)) +#define bFM4_GPIO_PDIRB_PE *((volatile uint8_t *)(0x42DE65B8UL)) +#define bFM_GPIO_PDIRB_PF *((volatile uint8_t *)(0x42DE65BCUL)) +#define bFM4_GPIO_PDIRB_PF *((volatile uint8_t *)(0x42DE65BCUL)) + +#define bFM_GPIO_PDIRC_P0 *((volatile uint8_t *)(0x42DE6600UL)) +#define bFM4_GPIO_PDIRC_P0 *((volatile uint8_t *)(0x42DE6600UL)) +#define bFM_GPIO_PDIRC_P1 *((volatile uint8_t *)(0x42DE6604UL)) +#define bFM4_GPIO_PDIRC_P1 *((volatile uint8_t *)(0x42DE6604UL)) +#define bFM_GPIO_PDIRC_P2 *((volatile uint8_t *)(0x42DE6608UL)) +#define bFM4_GPIO_PDIRC_P2 *((volatile uint8_t *)(0x42DE6608UL)) +#define bFM_GPIO_PDIRC_P3 *((volatile uint8_t *)(0x42DE660CUL)) +#define bFM4_GPIO_PDIRC_P3 *((volatile uint8_t *)(0x42DE660CUL)) +#define bFM_GPIO_PDIRC_P4 *((volatile uint8_t *)(0x42DE6610UL)) +#define bFM4_GPIO_PDIRC_P4 *((volatile uint8_t *)(0x42DE6610UL)) +#define bFM_GPIO_PDIRC_P5 *((volatile uint8_t *)(0x42DE6614UL)) +#define bFM4_GPIO_PDIRC_P5 *((volatile uint8_t *)(0x42DE6614UL)) +#define bFM_GPIO_PDIRC_P6 *((volatile uint8_t *)(0x42DE6618UL)) +#define bFM4_GPIO_PDIRC_P6 *((volatile uint8_t *)(0x42DE6618UL)) +#define bFM_GPIO_PDIRC_P7 *((volatile uint8_t *)(0x42DE661CUL)) +#define bFM4_GPIO_PDIRC_P7 *((volatile uint8_t *)(0x42DE661CUL)) +#define bFM_GPIO_PDIRC_P8 *((volatile uint8_t *)(0x42DE6620UL)) +#define bFM4_GPIO_PDIRC_P8 *((volatile uint8_t *)(0x42DE6620UL)) +#define bFM_GPIO_PDIRC_P9 *((volatile uint8_t *)(0x42DE6624UL)) +#define bFM4_GPIO_PDIRC_P9 *((volatile uint8_t *)(0x42DE6624UL)) +#define bFM_GPIO_PDIRC_PA *((volatile uint8_t *)(0x42DE6628UL)) +#define bFM4_GPIO_PDIRC_PA *((volatile uint8_t *)(0x42DE6628UL)) +#define bFM_GPIO_PDIRC_PB *((volatile uint8_t *)(0x42DE662CUL)) +#define bFM4_GPIO_PDIRC_PB *((volatile uint8_t *)(0x42DE662CUL)) +#define bFM_GPIO_PDIRC_PC *((volatile uint8_t *)(0x42DE6630UL)) +#define bFM4_GPIO_PDIRC_PC *((volatile uint8_t *)(0x42DE6630UL)) +#define bFM_GPIO_PDIRC_PD *((volatile uint8_t *)(0x42DE6634UL)) +#define bFM4_GPIO_PDIRC_PD *((volatile uint8_t *)(0x42DE6634UL)) +#define bFM_GPIO_PDIRC_PE *((volatile uint8_t *)(0x42DE6638UL)) +#define bFM4_GPIO_PDIRC_PE *((volatile uint8_t *)(0x42DE6638UL)) +#define bFM_GPIO_PDIRC_PF *((volatile uint8_t *)(0x42DE663CUL)) +#define bFM4_GPIO_PDIRC_PF *((volatile uint8_t *)(0x42DE663CUL)) + +#define bFM_GPIO_PDIRD_P0 *((volatile uint8_t *)(0x42DE6680UL)) +#define bFM4_GPIO_PDIRD_P0 *((volatile uint8_t *)(0x42DE6680UL)) +#define bFM_GPIO_PDIRD_P1 *((volatile uint8_t *)(0x42DE6684UL)) +#define bFM4_GPIO_PDIRD_P1 *((volatile uint8_t *)(0x42DE6684UL)) +#define bFM_GPIO_PDIRD_P2 *((volatile uint8_t *)(0x42DE6688UL)) +#define bFM4_GPIO_PDIRD_P2 *((volatile uint8_t *)(0x42DE6688UL)) + +#define bFM_GPIO_PDIRE_P0 *((volatile uint8_t *)(0x42DE6700UL)) +#define bFM4_GPIO_PDIRE_P0 *((volatile uint8_t *)(0x42DE6700UL)) +#define bFM_GPIO_PDIRE_P2 *((volatile uint8_t *)(0x42DE6708UL)) +#define bFM4_GPIO_PDIRE_P2 *((volatile uint8_t *)(0x42DE6708UL)) +#define bFM_GPIO_PDIRE_P3 *((volatile uint8_t *)(0x42DE670CUL)) +#define bFM4_GPIO_PDIRE_P3 *((volatile uint8_t *)(0x42DE670CUL)) + +#define bFM_GPIO_PDIRF_P0 *((volatile uint8_t *)(0x42DE6780UL)) +#define bFM4_GPIO_PDIRF_P0 *((volatile uint8_t *)(0x42DE6780UL)) +#define bFM_GPIO_PDIRF_P1 *((volatile uint8_t *)(0x42DE6784UL)) +#define bFM4_GPIO_PDIRF_P1 *((volatile uint8_t *)(0x42DE6784UL)) +#define bFM_GPIO_PDIRF_P2 *((volatile uint8_t *)(0x42DE6788UL)) +#define bFM4_GPIO_PDIRF_P2 *((volatile uint8_t *)(0x42DE6788UL)) +#define bFM_GPIO_PDIRF_P3 *((volatile uint8_t *)(0x42DE678CUL)) +#define bFM4_GPIO_PDIRF_P3 *((volatile uint8_t *)(0x42DE678CUL)) +#define bFM_GPIO_PDIRF_P4 *((volatile uint8_t *)(0x42DE6790UL)) +#define bFM4_GPIO_PDIRF_P4 *((volatile uint8_t *)(0x42DE6790UL)) +#define bFM_GPIO_PDIRF_P5 *((volatile uint8_t *)(0x42DE6794UL)) +#define bFM4_GPIO_PDIRF_P5 *((volatile uint8_t *)(0x42DE6794UL)) +#define bFM_GPIO_PDIRF_P6 *((volatile uint8_t *)(0x42DE6798UL)) +#define bFM4_GPIO_PDIRF_P6 *((volatile uint8_t *)(0x42DE6798UL)) +#define bFM_GPIO_PDIRF_P7 *((volatile uint8_t *)(0x42DE679CUL)) +#define bFM4_GPIO_PDIRF_P7 *((volatile uint8_t *)(0x42DE679CUL)) +#define bFM_GPIO_PDIRF_P8 *((volatile uint8_t *)(0x42DE67A0UL)) +#define bFM4_GPIO_PDIRF_P8 *((volatile uint8_t *)(0x42DE67A0UL)) +#define bFM_GPIO_PDIRF_P9 *((volatile uint8_t *)(0x42DE67A4UL)) +#define bFM4_GPIO_PDIRF_P9 *((volatile uint8_t *)(0x42DE67A4UL)) +#define bFM_GPIO_PDIRF_PA *((volatile uint8_t *)(0x42DE67A8UL)) +#define bFM4_GPIO_PDIRF_PA *((volatile uint8_t *)(0x42DE67A8UL)) +#define bFM_GPIO_PDIRF_PB *((volatile uint8_t *)(0x42DE67ACUL)) +#define bFM4_GPIO_PDIRF_PB *((volatile uint8_t *)(0x42DE67ACUL)) +#define bFM_GPIO_PDIRF_PC *((volatile uint8_t *)(0x42DE67B0UL)) +#define bFM4_GPIO_PDIRF_PC *((volatile uint8_t *)(0x42DE67B0UL)) + +#define bFM_GPIO_PDOR0_P0 *((volatile uint8_t *)(0x42DE8000UL)) +#define bFM4_GPIO_PDOR0_P0 *((volatile uint8_t *)(0x42DE8000UL)) +#define bFM_GPIO_PDOR0_P1 *((volatile uint8_t *)(0x42DE8004UL)) +#define bFM4_GPIO_PDOR0_P1 *((volatile uint8_t *)(0x42DE8004UL)) +#define bFM_GPIO_PDOR0_P2 *((volatile uint8_t *)(0x42DE8008UL)) +#define bFM4_GPIO_PDOR0_P2 *((volatile uint8_t *)(0x42DE8008UL)) +#define bFM_GPIO_PDOR0_P3 *((volatile uint8_t *)(0x42DE800CUL)) +#define bFM4_GPIO_PDOR0_P3 *((volatile uint8_t *)(0x42DE800CUL)) +#define bFM_GPIO_PDOR0_P4 *((volatile uint8_t *)(0x42DE8010UL)) +#define bFM4_GPIO_PDOR0_P4 *((volatile uint8_t *)(0x42DE8010UL)) +#define bFM_GPIO_PDOR0_P8 *((volatile uint8_t *)(0x42DE8020UL)) +#define bFM4_GPIO_PDOR0_P8 *((volatile uint8_t *)(0x42DE8020UL)) +#define bFM_GPIO_PDOR0_P9 *((volatile uint8_t *)(0x42DE8024UL)) +#define bFM4_GPIO_PDOR0_P9 *((volatile uint8_t *)(0x42DE8024UL)) +#define bFM_GPIO_PDOR0_PA *((volatile uint8_t *)(0x42DE8028UL)) +#define bFM4_GPIO_PDOR0_PA *((volatile uint8_t *)(0x42DE8028UL)) + +#define bFM_GPIO_PDOR1_P0 *((volatile uint8_t *)(0x42DE8080UL)) +#define bFM4_GPIO_PDOR1_P0 *((volatile uint8_t *)(0x42DE8080UL)) +#define bFM_GPIO_PDOR1_P1 *((volatile uint8_t *)(0x42DE8084UL)) +#define bFM4_GPIO_PDOR1_P1 *((volatile uint8_t *)(0x42DE8084UL)) +#define bFM_GPIO_PDOR1_P2 *((volatile uint8_t *)(0x42DE8088UL)) +#define bFM4_GPIO_PDOR1_P2 *((volatile uint8_t *)(0x42DE8088UL)) +#define bFM_GPIO_PDOR1_P3 *((volatile uint8_t *)(0x42DE808CUL)) +#define bFM4_GPIO_PDOR1_P3 *((volatile uint8_t *)(0x42DE808CUL)) +#define bFM_GPIO_PDOR1_P4 *((volatile uint8_t *)(0x42DE8090UL)) +#define bFM4_GPIO_PDOR1_P4 *((volatile uint8_t *)(0x42DE8090UL)) +#define bFM_GPIO_PDOR1_P5 *((volatile uint8_t *)(0x42DE8094UL)) +#define bFM4_GPIO_PDOR1_P5 *((volatile uint8_t *)(0x42DE8094UL)) +#define bFM_GPIO_PDOR1_P6 *((volatile uint8_t *)(0x42DE8098UL)) +#define bFM4_GPIO_PDOR1_P6 *((volatile uint8_t *)(0x42DE8098UL)) +#define bFM_GPIO_PDOR1_P7 *((volatile uint8_t *)(0x42DE809CUL)) +#define bFM4_GPIO_PDOR1_P7 *((volatile uint8_t *)(0x42DE809CUL)) +#define bFM_GPIO_PDOR1_P8 *((volatile uint8_t *)(0x42DE80A0UL)) +#define bFM4_GPIO_PDOR1_P8 *((volatile uint8_t *)(0x42DE80A0UL)) +#define bFM_GPIO_PDOR1_P9 *((volatile uint8_t *)(0x42DE80A4UL)) +#define bFM4_GPIO_PDOR1_P9 *((volatile uint8_t *)(0x42DE80A4UL)) +#define bFM_GPIO_PDOR1_PA *((volatile uint8_t *)(0x42DE80A8UL)) +#define bFM4_GPIO_PDOR1_PA *((volatile uint8_t *)(0x42DE80A8UL)) +#define bFM_GPIO_PDOR1_PB *((volatile uint8_t *)(0x42DE80ACUL)) +#define bFM4_GPIO_PDOR1_PB *((volatile uint8_t *)(0x42DE80ACUL)) +#define bFM_GPIO_PDOR1_PC *((volatile uint8_t *)(0x42DE80B0UL)) +#define bFM4_GPIO_PDOR1_PC *((volatile uint8_t *)(0x42DE80B0UL)) +#define bFM_GPIO_PDOR1_PD *((volatile uint8_t *)(0x42DE80B4UL)) +#define bFM4_GPIO_PDOR1_PD *((volatile uint8_t *)(0x42DE80B4UL)) +#define bFM_GPIO_PDOR1_PE *((volatile uint8_t *)(0x42DE80B8UL)) +#define bFM4_GPIO_PDOR1_PE *((volatile uint8_t *)(0x42DE80B8UL)) +#define bFM_GPIO_PDOR1_PF *((volatile uint8_t *)(0x42DE80BCUL)) +#define bFM4_GPIO_PDOR1_PF *((volatile uint8_t *)(0x42DE80BCUL)) + +#define bFM_GPIO_PDOR2_P0 *((volatile uint8_t *)(0x42DE8100UL)) +#define bFM4_GPIO_PDOR2_P0 *((volatile uint8_t *)(0x42DE8100UL)) +#define bFM_GPIO_PDOR2_P1 *((volatile uint8_t *)(0x42DE8104UL)) +#define bFM4_GPIO_PDOR2_P1 *((volatile uint8_t *)(0x42DE8104UL)) +#define bFM_GPIO_PDOR2_P2 *((volatile uint8_t *)(0x42DE8108UL)) +#define bFM4_GPIO_PDOR2_P2 *((volatile uint8_t *)(0x42DE8108UL)) +#define bFM_GPIO_PDOR2_P3 *((volatile uint8_t *)(0x42DE810CUL)) +#define bFM4_GPIO_PDOR2_P3 *((volatile uint8_t *)(0x42DE810CUL)) +#define bFM_GPIO_PDOR2_P4 *((volatile uint8_t *)(0x42DE8110UL)) +#define bFM4_GPIO_PDOR2_P4 *((volatile uint8_t *)(0x42DE8110UL)) +#define bFM_GPIO_PDOR2_P5 *((volatile uint8_t *)(0x42DE8114UL)) +#define bFM4_GPIO_PDOR2_P5 *((volatile uint8_t *)(0x42DE8114UL)) +#define bFM_GPIO_PDOR2_P6 *((volatile uint8_t *)(0x42DE8118UL)) +#define bFM4_GPIO_PDOR2_P6 *((volatile uint8_t *)(0x42DE8118UL)) +#define bFM_GPIO_PDOR2_P7 *((volatile uint8_t *)(0x42DE811CUL)) +#define bFM4_GPIO_PDOR2_P7 *((volatile uint8_t *)(0x42DE811CUL)) +#define bFM_GPIO_PDOR2_P8 *((volatile uint8_t *)(0x42DE8120UL)) +#define bFM4_GPIO_PDOR2_P8 *((volatile uint8_t *)(0x42DE8120UL)) +#define bFM_GPIO_PDOR2_P9 *((volatile uint8_t *)(0x42DE8124UL)) +#define bFM4_GPIO_PDOR2_P9 *((volatile uint8_t *)(0x42DE8124UL)) +#define bFM_GPIO_PDOR2_PA *((volatile uint8_t *)(0x42DE8128UL)) +#define bFM4_GPIO_PDOR2_PA *((volatile uint8_t *)(0x42DE8128UL)) + +#define bFM_GPIO_PDOR3_P0 *((volatile uint8_t *)(0x42DE8180UL)) +#define bFM4_GPIO_PDOR3_P0 *((volatile uint8_t *)(0x42DE8180UL)) +#define bFM_GPIO_PDOR3_P1 *((volatile uint8_t *)(0x42DE8184UL)) +#define bFM4_GPIO_PDOR3_P1 *((volatile uint8_t *)(0x42DE8184UL)) +#define bFM_GPIO_PDOR3_P2 *((volatile uint8_t *)(0x42DE8188UL)) +#define bFM4_GPIO_PDOR3_P2 *((volatile uint8_t *)(0x42DE8188UL)) +#define bFM_GPIO_PDOR3_P3 *((volatile uint8_t *)(0x42DE818CUL)) +#define bFM4_GPIO_PDOR3_P3 *((volatile uint8_t *)(0x42DE818CUL)) +#define bFM_GPIO_PDOR3_P4 *((volatile uint8_t *)(0x42DE8190UL)) +#define bFM4_GPIO_PDOR3_P4 *((volatile uint8_t *)(0x42DE8190UL)) +#define bFM_GPIO_PDOR3_P5 *((volatile uint8_t *)(0x42DE8194UL)) +#define bFM4_GPIO_PDOR3_P5 *((volatile uint8_t *)(0x42DE8194UL)) +#define bFM_GPIO_PDOR3_P6 *((volatile uint8_t *)(0x42DE8198UL)) +#define bFM4_GPIO_PDOR3_P6 *((volatile uint8_t *)(0x42DE8198UL)) +#define bFM_GPIO_PDOR3_P7 *((volatile uint8_t *)(0x42DE819CUL)) +#define bFM4_GPIO_PDOR3_P7 *((volatile uint8_t *)(0x42DE819CUL)) +#define bFM_GPIO_PDOR3_P8 *((volatile uint8_t *)(0x42DE81A0UL)) +#define bFM4_GPIO_PDOR3_P8 *((volatile uint8_t *)(0x42DE81A0UL)) +#define bFM_GPIO_PDOR3_P9 *((volatile uint8_t *)(0x42DE81A4UL)) +#define bFM4_GPIO_PDOR3_P9 *((volatile uint8_t *)(0x42DE81A4UL)) +#define bFM_GPIO_PDOR3_PA *((volatile uint8_t *)(0x42DE81A8UL)) +#define bFM4_GPIO_PDOR3_PA *((volatile uint8_t *)(0x42DE81A8UL)) +#define bFM_GPIO_PDOR3_PB *((volatile uint8_t *)(0x42DE81ACUL)) +#define bFM4_GPIO_PDOR3_PB *((volatile uint8_t *)(0x42DE81ACUL)) +#define bFM_GPIO_PDOR3_PC *((volatile uint8_t *)(0x42DE81B0UL)) +#define bFM4_GPIO_PDOR3_PC *((volatile uint8_t *)(0x42DE81B0UL)) +#define bFM_GPIO_PDOR3_PD *((volatile uint8_t *)(0x42DE81B4UL)) +#define bFM4_GPIO_PDOR3_PD *((volatile uint8_t *)(0x42DE81B4UL)) +#define bFM_GPIO_PDOR3_PE *((volatile uint8_t *)(0x42DE81B8UL)) +#define bFM4_GPIO_PDOR3_PE *((volatile uint8_t *)(0x42DE81B8UL)) + +#define bFM_GPIO_PDOR4_P0 *((volatile uint8_t *)(0x42DE8200UL)) +#define bFM4_GPIO_PDOR4_P0 *((volatile uint8_t *)(0x42DE8200UL)) +#define bFM_GPIO_PDOR4_P1 *((volatile uint8_t *)(0x42DE8204UL)) +#define bFM4_GPIO_PDOR4_P1 *((volatile uint8_t *)(0x42DE8204UL)) +#define bFM_GPIO_PDOR4_P2 *((volatile uint8_t *)(0x42DE8208UL)) +#define bFM4_GPIO_PDOR4_P2 *((volatile uint8_t *)(0x42DE8208UL)) +#define bFM_GPIO_PDOR4_P3 *((volatile uint8_t *)(0x42DE820CUL)) +#define bFM4_GPIO_PDOR4_P3 *((volatile uint8_t *)(0x42DE820CUL)) +#define bFM_GPIO_PDOR4_P4 *((volatile uint8_t *)(0x42DE8210UL)) +#define bFM4_GPIO_PDOR4_P4 *((volatile uint8_t *)(0x42DE8210UL)) +#define bFM_GPIO_PDOR4_P5 *((volatile uint8_t *)(0x42DE8214UL)) +#define bFM4_GPIO_PDOR4_P5 *((volatile uint8_t *)(0x42DE8214UL)) +#define bFM_GPIO_PDOR4_P6 *((volatile uint8_t *)(0x42DE8218UL)) +#define bFM4_GPIO_PDOR4_P6 *((volatile uint8_t *)(0x42DE8218UL)) +#define bFM_GPIO_PDOR4_P7 *((volatile uint8_t *)(0x42DE821CUL)) +#define bFM4_GPIO_PDOR4_P7 *((volatile uint8_t *)(0x42DE821CUL)) +#define bFM_GPIO_PDOR4_P8 *((volatile uint8_t *)(0x42DE8220UL)) +#define bFM4_GPIO_PDOR4_P8 *((volatile uint8_t *)(0x42DE8220UL)) +#define bFM_GPIO_PDOR4_P9 *((volatile uint8_t *)(0x42DE8224UL)) +#define bFM4_GPIO_PDOR4_P9 *((volatile uint8_t *)(0x42DE8224UL)) +#define bFM_GPIO_PDOR4_PA *((volatile uint8_t *)(0x42DE8228UL)) +#define bFM4_GPIO_PDOR4_PA *((volatile uint8_t *)(0x42DE8228UL)) +#define bFM_GPIO_PDOR4_PB *((volatile uint8_t *)(0x42DE822CUL)) +#define bFM4_GPIO_PDOR4_PB *((volatile uint8_t *)(0x42DE822CUL)) +#define bFM_GPIO_PDOR4_PC *((volatile uint8_t *)(0x42DE8230UL)) +#define bFM4_GPIO_PDOR4_PC *((volatile uint8_t *)(0x42DE8230UL)) +#define bFM_GPIO_PDOR4_PD *((volatile uint8_t *)(0x42DE8234UL)) +#define bFM4_GPIO_PDOR4_PD *((volatile uint8_t *)(0x42DE8234UL)) +#define bFM_GPIO_PDOR4_PE *((volatile uint8_t *)(0x42DE8238UL)) +#define bFM4_GPIO_PDOR4_PE *((volatile uint8_t *)(0x42DE8238UL)) + +#define bFM_GPIO_PDOR5_P0 *((volatile uint8_t *)(0x42DE8280UL)) +#define bFM4_GPIO_PDOR5_P0 *((volatile uint8_t *)(0x42DE8280UL)) +#define bFM_GPIO_PDOR5_P1 *((volatile uint8_t *)(0x42DE8284UL)) +#define bFM4_GPIO_PDOR5_P1 *((volatile uint8_t *)(0x42DE8284UL)) +#define bFM_GPIO_PDOR5_P2 *((volatile uint8_t *)(0x42DE8288UL)) +#define bFM4_GPIO_PDOR5_P2 *((volatile uint8_t *)(0x42DE8288UL)) +#define bFM_GPIO_PDOR5_P3 *((volatile uint8_t *)(0x42DE828CUL)) +#define bFM4_GPIO_PDOR5_P3 *((volatile uint8_t *)(0x42DE828CUL)) +#define bFM_GPIO_PDOR5_P4 *((volatile uint8_t *)(0x42DE8290UL)) +#define bFM4_GPIO_PDOR5_P4 *((volatile uint8_t *)(0x42DE8290UL)) +#define bFM_GPIO_PDOR5_P5 *((volatile uint8_t *)(0x42DE8294UL)) +#define bFM4_GPIO_PDOR5_P5 *((volatile uint8_t *)(0x42DE8294UL)) +#define bFM_GPIO_PDOR5_P6 *((volatile uint8_t *)(0x42DE8298UL)) +#define bFM4_GPIO_PDOR5_P6 *((volatile uint8_t *)(0x42DE8298UL)) +#define bFM_GPIO_PDOR5_P7 *((volatile uint8_t *)(0x42DE829CUL)) +#define bFM4_GPIO_PDOR5_P7 *((volatile uint8_t *)(0x42DE829CUL)) +#define bFM_GPIO_PDOR5_P8 *((volatile uint8_t *)(0x42DE82A0UL)) +#define bFM4_GPIO_PDOR5_P8 *((volatile uint8_t *)(0x42DE82A0UL)) +#define bFM_GPIO_PDOR5_P9 *((volatile uint8_t *)(0x42DE82A4UL)) +#define bFM4_GPIO_PDOR5_P9 *((volatile uint8_t *)(0x42DE82A4UL)) +#define bFM_GPIO_PDOR5_PA *((volatile uint8_t *)(0x42DE82A8UL)) +#define bFM4_GPIO_PDOR5_PA *((volatile uint8_t *)(0x42DE82A8UL)) +#define bFM_GPIO_PDOR5_PB *((volatile uint8_t *)(0x42DE82ACUL)) +#define bFM4_GPIO_PDOR5_PB *((volatile uint8_t *)(0x42DE82ACUL)) +#define bFM_GPIO_PDOR5_PC *((volatile uint8_t *)(0x42DE82B0UL)) +#define bFM4_GPIO_PDOR5_PC *((volatile uint8_t *)(0x42DE82B0UL)) +#define bFM_GPIO_PDOR5_PD *((volatile uint8_t *)(0x42DE82B4UL)) +#define bFM4_GPIO_PDOR5_PD *((volatile uint8_t *)(0x42DE82B4UL)) +#define bFM_GPIO_PDOR5_PE *((volatile uint8_t *)(0x42DE82B8UL)) +#define bFM4_GPIO_PDOR5_PE *((volatile uint8_t *)(0x42DE82B8UL)) +#define bFM_GPIO_PDOR5_PF *((volatile uint8_t *)(0x42DE82BCUL)) +#define bFM4_GPIO_PDOR5_PF *((volatile uint8_t *)(0x42DE82BCUL)) + +#define bFM_GPIO_PDOR6_P0 *((volatile uint8_t *)(0x42DE8300UL)) +#define bFM4_GPIO_PDOR6_P0 *((volatile uint8_t *)(0x42DE8300UL)) +#define bFM_GPIO_PDOR6_P1 *((volatile uint8_t *)(0x42DE8304UL)) +#define bFM4_GPIO_PDOR6_P1 *((volatile uint8_t *)(0x42DE8304UL)) +#define bFM_GPIO_PDOR6_P2 *((volatile uint8_t *)(0x42DE8308UL)) +#define bFM4_GPIO_PDOR6_P2 *((volatile uint8_t *)(0x42DE8308UL)) +#define bFM_GPIO_PDOR6_P3 *((volatile uint8_t *)(0x42DE830CUL)) +#define bFM4_GPIO_PDOR6_P3 *((volatile uint8_t *)(0x42DE830CUL)) +#define bFM_GPIO_PDOR6_P4 *((volatile uint8_t *)(0x42DE8310UL)) +#define bFM4_GPIO_PDOR6_P4 *((volatile uint8_t *)(0x42DE8310UL)) +#define bFM_GPIO_PDOR6_P5 *((volatile uint8_t *)(0x42DE8314UL)) +#define bFM4_GPIO_PDOR6_P5 *((volatile uint8_t *)(0x42DE8314UL)) +#define bFM_GPIO_PDOR6_P6 *((volatile uint8_t *)(0x42DE8318UL)) +#define bFM4_GPIO_PDOR6_P6 *((volatile uint8_t *)(0x42DE8318UL)) +#define bFM_GPIO_PDOR6_P7 *((volatile uint8_t *)(0x42DE831CUL)) +#define bFM4_GPIO_PDOR6_P7 *((volatile uint8_t *)(0x42DE831CUL)) +#define bFM_GPIO_PDOR6_P8 *((volatile uint8_t *)(0x42DE8320UL)) +#define bFM4_GPIO_PDOR6_P8 *((volatile uint8_t *)(0x42DE8320UL)) +#define bFM_GPIO_PDOR6_P9 *((volatile uint8_t *)(0x42DE8324UL)) +#define bFM4_GPIO_PDOR6_P9 *((volatile uint8_t *)(0x42DE8324UL)) +#define bFM_GPIO_PDOR6_PA *((volatile uint8_t *)(0x42DE8328UL)) +#define bFM4_GPIO_PDOR6_PA *((volatile uint8_t *)(0x42DE8328UL)) +#define bFM_GPIO_PDOR6_PB *((volatile uint8_t *)(0x42DE832CUL)) +#define bFM4_GPIO_PDOR6_PB *((volatile uint8_t *)(0x42DE832CUL)) +#define bFM_GPIO_PDOR6_PC *((volatile uint8_t *)(0x42DE8330UL)) +#define bFM4_GPIO_PDOR6_PC *((volatile uint8_t *)(0x42DE8330UL)) +#define bFM_GPIO_PDOR6_PD *((volatile uint8_t *)(0x42DE8334UL)) +#define bFM4_GPIO_PDOR6_PD *((volatile uint8_t *)(0x42DE8334UL)) +#define bFM_GPIO_PDOR6_PE *((volatile uint8_t *)(0x42DE8338UL)) +#define bFM4_GPIO_PDOR6_PE *((volatile uint8_t *)(0x42DE8338UL)) + +#define bFM_GPIO_PDOR7_P0 *((volatile uint8_t *)(0x42DE8380UL)) +#define bFM4_GPIO_PDOR7_P0 *((volatile uint8_t *)(0x42DE8380UL)) +#define bFM_GPIO_PDOR7_P1 *((volatile uint8_t *)(0x42DE8384UL)) +#define bFM4_GPIO_PDOR7_P1 *((volatile uint8_t *)(0x42DE8384UL)) +#define bFM_GPIO_PDOR7_P2 *((volatile uint8_t *)(0x42DE8388UL)) +#define bFM4_GPIO_PDOR7_P2 *((volatile uint8_t *)(0x42DE8388UL)) +#define bFM_GPIO_PDOR7_P3 *((volatile uint8_t *)(0x42DE838CUL)) +#define bFM4_GPIO_PDOR7_P3 *((volatile uint8_t *)(0x42DE838CUL)) +#define bFM_GPIO_PDOR7_P4 *((volatile uint8_t *)(0x42DE8390UL)) +#define bFM4_GPIO_PDOR7_P4 *((volatile uint8_t *)(0x42DE8390UL)) +#define bFM_GPIO_PDOR7_P5 *((volatile uint8_t *)(0x42DE8394UL)) +#define bFM4_GPIO_PDOR7_P5 *((volatile uint8_t *)(0x42DE8394UL)) +#define bFM_GPIO_PDOR7_P6 *((volatile uint8_t *)(0x42DE8398UL)) +#define bFM4_GPIO_PDOR7_P6 *((volatile uint8_t *)(0x42DE8398UL)) +#define bFM_GPIO_PDOR7_P7 *((volatile uint8_t *)(0x42DE839CUL)) +#define bFM4_GPIO_PDOR7_P7 *((volatile uint8_t *)(0x42DE839CUL)) +#define bFM_GPIO_PDOR7_P8 *((volatile uint8_t *)(0x42DE83A0UL)) +#define bFM4_GPIO_PDOR7_P8 *((volatile uint8_t *)(0x42DE83A0UL)) +#define bFM_GPIO_PDOR7_P9 *((volatile uint8_t *)(0x42DE83A4UL)) +#define bFM4_GPIO_PDOR7_P9 *((volatile uint8_t *)(0x42DE83A4UL)) +#define bFM_GPIO_PDOR7_PA *((volatile uint8_t *)(0x42DE83A8UL)) +#define bFM4_GPIO_PDOR7_PA *((volatile uint8_t *)(0x42DE83A8UL)) +#define bFM_GPIO_PDOR7_PB *((volatile uint8_t *)(0x42DE83ACUL)) +#define bFM4_GPIO_PDOR7_PB *((volatile uint8_t *)(0x42DE83ACUL)) +#define bFM_GPIO_PDOR7_PC *((volatile uint8_t *)(0x42DE83B0UL)) +#define bFM4_GPIO_PDOR7_PC *((volatile uint8_t *)(0x42DE83B0UL)) +#define bFM_GPIO_PDOR7_PD *((volatile uint8_t *)(0x42DE83B4UL)) +#define bFM4_GPIO_PDOR7_PD *((volatile uint8_t *)(0x42DE83B4UL)) +#define bFM_GPIO_PDOR7_PE *((volatile uint8_t *)(0x42DE83B8UL)) +#define bFM4_GPIO_PDOR7_PE *((volatile uint8_t *)(0x42DE83B8UL)) + +#define bFM_GPIO_PDOR8_P0 *((volatile uint8_t *)(0x42DE8400UL)) +#define bFM4_GPIO_PDOR8_P0 *((volatile uint8_t *)(0x42DE8400UL)) +#define bFM_GPIO_PDOR8_P1 *((volatile uint8_t *)(0x42DE8404UL)) +#define bFM4_GPIO_PDOR8_P1 *((volatile uint8_t *)(0x42DE8404UL)) +#define bFM_GPIO_PDOR8_P2 *((volatile uint8_t *)(0x42DE8408UL)) +#define bFM4_GPIO_PDOR8_P2 *((volatile uint8_t *)(0x42DE8408UL)) +#define bFM_GPIO_PDOR8_P3 *((volatile uint8_t *)(0x42DE840CUL)) +#define bFM4_GPIO_PDOR8_P3 *((volatile uint8_t *)(0x42DE840CUL)) + +#define bFM_GPIO_PDOR9_P0 *((volatile uint8_t *)(0x42DE8480UL)) +#define bFM4_GPIO_PDOR9_P0 *((volatile uint8_t *)(0x42DE8480UL)) +#define bFM_GPIO_PDOR9_P1 *((volatile uint8_t *)(0x42DE8484UL)) +#define bFM4_GPIO_PDOR9_P1 *((volatile uint8_t *)(0x42DE8484UL)) +#define bFM_GPIO_PDOR9_P2 *((volatile uint8_t *)(0x42DE8488UL)) +#define bFM4_GPIO_PDOR9_P2 *((volatile uint8_t *)(0x42DE8488UL)) +#define bFM_GPIO_PDOR9_P3 *((volatile uint8_t *)(0x42DE848CUL)) +#define bFM4_GPIO_PDOR9_P3 *((volatile uint8_t *)(0x42DE848CUL)) +#define bFM_GPIO_PDOR9_P4 *((volatile uint8_t *)(0x42DE8490UL)) +#define bFM4_GPIO_PDOR9_P4 *((volatile uint8_t *)(0x42DE8490UL)) +#define bFM_GPIO_PDOR9_P5 *((volatile uint8_t *)(0x42DE8494UL)) +#define bFM4_GPIO_PDOR9_P5 *((volatile uint8_t *)(0x42DE8494UL)) +#define bFM_GPIO_PDOR9_P6 *((volatile uint8_t *)(0x42DE8498UL)) +#define bFM4_GPIO_PDOR9_P6 *((volatile uint8_t *)(0x42DE8498UL)) +#define bFM_GPIO_PDOR9_P7 *((volatile uint8_t *)(0x42DE849CUL)) +#define bFM4_GPIO_PDOR9_P7 *((volatile uint8_t *)(0x42DE849CUL)) + +#define bFM_GPIO_PDORA_P0 *((volatile uint8_t *)(0x42DE8500UL)) +#define bFM4_GPIO_PDORA_P0 *((volatile uint8_t *)(0x42DE8500UL)) +#define bFM_GPIO_PDORA_P1 *((volatile uint8_t *)(0x42DE8504UL)) +#define bFM4_GPIO_PDORA_P1 *((volatile uint8_t *)(0x42DE8504UL)) +#define bFM_GPIO_PDORA_P2 *((volatile uint8_t *)(0x42DE8508UL)) +#define bFM4_GPIO_PDORA_P2 *((volatile uint8_t *)(0x42DE8508UL)) +#define bFM_GPIO_PDORA_P3 *((volatile uint8_t *)(0x42DE850CUL)) +#define bFM4_GPIO_PDORA_P3 *((volatile uint8_t *)(0x42DE850CUL)) +#define bFM_GPIO_PDORA_P4 *((volatile uint8_t *)(0x42DE8510UL)) +#define bFM4_GPIO_PDORA_P4 *((volatile uint8_t *)(0x42DE8510UL)) +#define bFM_GPIO_PDORA_P5 *((volatile uint8_t *)(0x42DE8514UL)) +#define bFM4_GPIO_PDORA_P5 *((volatile uint8_t *)(0x42DE8514UL)) +#define bFM_GPIO_PDORA_P6 *((volatile uint8_t *)(0x42DE8518UL)) +#define bFM4_GPIO_PDORA_P6 *((volatile uint8_t *)(0x42DE8518UL)) +#define bFM_GPIO_PDORA_P7 *((volatile uint8_t *)(0x42DE851CUL)) +#define bFM4_GPIO_PDORA_P7 *((volatile uint8_t *)(0x42DE851CUL)) +#define bFM_GPIO_PDORA_P8 *((volatile uint8_t *)(0x42DE8520UL)) +#define bFM4_GPIO_PDORA_P8 *((volatile uint8_t *)(0x42DE8520UL)) +#define bFM_GPIO_PDORA_P9 *((volatile uint8_t *)(0x42DE8524UL)) +#define bFM4_GPIO_PDORA_P9 *((volatile uint8_t *)(0x42DE8524UL)) +#define bFM_GPIO_PDORA_PA *((volatile uint8_t *)(0x42DE8528UL)) +#define bFM4_GPIO_PDORA_PA *((volatile uint8_t *)(0x42DE8528UL)) +#define bFM_GPIO_PDORA_PB *((volatile uint8_t *)(0x42DE852CUL)) +#define bFM4_GPIO_PDORA_PB *((volatile uint8_t *)(0x42DE852CUL)) +#define bFM_GPIO_PDORA_PC *((volatile uint8_t *)(0x42DE8530UL)) +#define bFM4_GPIO_PDORA_PC *((volatile uint8_t *)(0x42DE8530UL)) +#define bFM_GPIO_PDORA_PD *((volatile uint8_t *)(0x42DE8534UL)) +#define bFM4_GPIO_PDORA_PD *((volatile uint8_t *)(0x42DE8534UL)) +#define bFM_GPIO_PDORA_PE *((volatile uint8_t *)(0x42DE8538UL)) +#define bFM4_GPIO_PDORA_PE *((volatile uint8_t *)(0x42DE8538UL)) +#define bFM_GPIO_PDORA_PF *((volatile uint8_t *)(0x42DE853CUL)) +#define bFM4_GPIO_PDORA_PF *((volatile uint8_t *)(0x42DE853CUL)) + +#define bFM_GPIO_PDORB_P0 *((volatile uint8_t *)(0x42DE8580UL)) +#define bFM4_GPIO_PDORB_P0 *((volatile uint8_t *)(0x42DE8580UL)) +#define bFM_GPIO_PDORB_P1 *((volatile uint8_t *)(0x42DE8584UL)) +#define bFM4_GPIO_PDORB_P1 *((volatile uint8_t *)(0x42DE8584UL)) +#define bFM_GPIO_PDORB_P2 *((volatile uint8_t *)(0x42DE8588UL)) +#define bFM4_GPIO_PDORB_P2 *((volatile uint8_t *)(0x42DE8588UL)) +#define bFM_GPIO_PDORB_P3 *((volatile uint8_t *)(0x42DE858CUL)) +#define bFM4_GPIO_PDORB_P3 *((volatile uint8_t *)(0x42DE858CUL)) +#define bFM_GPIO_PDORB_P4 *((volatile uint8_t *)(0x42DE8590UL)) +#define bFM4_GPIO_PDORB_P4 *((volatile uint8_t *)(0x42DE8590UL)) +#define bFM_GPIO_PDORB_P5 *((volatile uint8_t *)(0x42DE8594UL)) +#define bFM4_GPIO_PDORB_P5 *((volatile uint8_t *)(0x42DE8594UL)) +#define bFM_GPIO_PDORB_P6 *((volatile uint8_t *)(0x42DE8598UL)) +#define bFM4_GPIO_PDORB_P6 *((volatile uint8_t *)(0x42DE8598UL)) +#define bFM_GPIO_PDORB_P7 *((volatile uint8_t *)(0x42DE859CUL)) +#define bFM4_GPIO_PDORB_P7 *((volatile uint8_t *)(0x42DE859CUL)) +#define bFM_GPIO_PDORB_P8 *((volatile uint8_t *)(0x42DE85A0UL)) +#define bFM4_GPIO_PDORB_P8 *((volatile uint8_t *)(0x42DE85A0UL)) +#define bFM_GPIO_PDORB_P9 *((volatile uint8_t *)(0x42DE85A4UL)) +#define bFM4_GPIO_PDORB_P9 *((volatile uint8_t *)(0x42DE85A4UL)) +#define bFM_GPIO_PDORB_PA *((volatile uint8_t *)(0x42DE85A8UL)) +#define bFM4_GPIO_PDORB_PA *((volatile uint8_t *)(0x42DE85A8UL)) +#define bFM_GPIO_PDORB_PB *((volatile uint8_t *)(0x42DE85ACUL)) +#define bFM4_GPIO_PDORB_PB *((volatile uint8_t *)(0x42DE85ACUL)) +#define bFM_GPIO_PDORB_PC *((volatile uint8_t *)(0x42DE85B0UL)) +#define bFM4_GPIO_PDORB_PC *((volatile uint8_t *)(0x42DE85B0UL)) +#define bFM_GPIO_PDORB_PD *((volatile uint8_t *)(0x42DE85B4UL)) +#define bFM4_GPIO_PDORB_PD *((volatile uint8_t *)(0x42DE85B4UL)) +#define bFM_GPIO_PDORB_PE *((volatile uint8_t *)(0x42DE85B8UL)) +#define bFM4_GPIO_PDORB_PE *((volatile uint8_t *)(0x42DE85B8UL)) +#define bFM_GPIO_PDORB_PF *((volatile uint8_t *)(0x42DE85BCUL)) +#define bFM4_GPIO_PDORB_PF *((volatile uint8_t *)(0x42DE85BCUL)) + +#define bFM_GPIO_PDORC_P0 *((volatile uint8_t *)(0x42DE8600UL)) +#define bFM4_GPIO_PDORC_P0 *((volatile uint8_t *)(0x42DE8600UL)) +#define bFM_GPIO_PDORC_P1 *((volatile uint8_t *)(0x42DE8604UL)) +#define bFM4_GPIO_PDORC_P1 *((volatile uint8_t *)(0x42DE8604UL)) +#define bFM_GPIO_PDORC_P2 *((volatile uint8_t *)(0x42DE8608UL)) +#define bFM4_GPIO_PDORC_P2 *((volatile uint8_t *)(0x42DE8608UL)) +#define bFM_GPIO_PDORC_P3 *((volatile uint8_t *)(0x42DE860CUL)) +#define bFM4_GPIO_PDORC_P3 *((volatile uint8_t *)(0x42DE860CUL)) +#define bFM_GPIO_PDORC_P4 *((volatile uint8_t *)(0x42DE8610UL)) +#define bFM4_GPIO_PDORC_P4 *((volatile uint8_t *)(0x42DE8610UL)) +#define bFM_GPIO_PDORC_P5 *((volatile uint8_t *)(0x42DE8614UL)) +#define bFM4_GPIO_PDORC_P5 *((volatile uint8_t *)(0x42DE8614UL)) +#define bFM_GPIO_PDORC_P6 *((volatile uint8_t *)(0x42DE8618UL)) +#define bFM4_GPIO_PDORC_P6 *((volatile uint8_t *)(0x42DE8618UL)) +#define bFM_GPIO_PDORC_P7 *((volatile uint8_t *)(0x42DE861CUL)) +#define bFM4_GPIO_PDORC_P7 *((volatile uint8_t *)(0x42DE861CUL)) +#define bFM_GPIO_PDORC_P8 *((volatile uint8_t *)(0x42DE8620UL)) +#define bFM4_GPIO_PDORC_P8 *((volatile uint8_t *)(0x42DE8620UL)) +#define bFM_GPIO_PDORC_P9 *((volatile uint8_t *)(0x42DE8624UL)) +#define bFM4_GPIO_PDORC_P9 *((volatile uint8_t *)(0x42DE8624UL)) +#define bFM_GPIO_PDORC_PA *((volatile uint8_t *)(0x42DE8628UL)) +#define bFM4_GPIO_PDORC_PA *((volatile uint8_t *)(0x42DE8628UL)) +#define bFM_GPIO_PDORC_PB *((volatile uint8_t *)(0x42DE862CUL)) +#define bFM4_GPIO_PDORC_PB *((volatile uint8_t *)(0x42DE862CUL)) +#define bFM_GPIO_PDORC_PC *((volatile uint8_t *)(0x42DE8630UL)) +#define bFM4_GPIO_PDORC_PC *((volatile uint8_t *)(0x42DE8630UL)) +#define bFM_GPIO_PDORC_PD *((volatile uint8_t *)(0x42DE8634UL)) +#define bFM4_GPIO_PDORC_PD *((volatile uint8_t *)(0x42DE8634UL)) +#define bFM_GPIO_PDORC_PE *((volatile uint8_t *)(0x42DE8638UL)) +#define bFM4_GPIO_PDORC_PE *((volatile uint8_t *)(0x42DE8638UL)) +#define bFM_GPIO_PDORC_PF *((volatile uint8_t *)(0x42DE863CUL)) +#define bFM4_GPIO_PDORC_PF *((volatile uint8_t *)(0x42DE863CUL)) + +#define bFM_GPIO_PDORD_P0 *((volatile uint8_t *)(0x42DE8680UL)) +#define bFM4_GPIO_PDORD_P0 *((volatile uint8_t *)(0x42DE8680UL)) +#define bFM_GPIO_PDORD_P1 *((volatile uint8_t *)(0x42DE8684UL)) +#define bFM4_GPIO_PDORD_P1 *((volatile uint8_t *)(0x42DE8684UL)) +#define bFM_GPIO_PDORD_P2 *((volatile uint8_t *)(0x42DE8688UL)) +#define bFM4_GPIO_PDORD_P2 *((volatile uint8_t *)(0x42DE8688UL)) + +#define bFM_GPIO_PDORE_P0 *((volatile uint8_t *)(0x42DE8700UL)) +#define bFM4_GPIO_PDORE_P0 *((volatile uint8_t *)(0x42DE8700UL)) +#define bFM_GPIO_PDORE_P2 *((volatile uint8_t *)(0x42DE8708UL)) +#define bFM4_GPIO_PDORE_P2 *((volatile uint8_t *)(0x42DE8708UL)) +#define bFM_GPIO_PDORE_P3 *((volatile uint8_t *)(0x42DE870CUL)) +#define bFM4_GPIO_PDORE_P3 *((volatile uint8_t *)(0x42DE870CUL)) + +#define bFM_GPIO_PDORF_P0 *((volatile uint8_t *)(0x42DE8780UL)) +#define bFM4_GPIO_PDORF_P0 *((volatile uint8_t *)(0x42DE8780UL)) +#define bFM_GPIO_PDORF_P1 *((volatile uint8_t *)(0x42DE8784UL)) +#define bFM4_GPIO_PDORF_P1 *((volatile uint8_t *)(0x42DE8784UL)) +#define bFM_GPIO_PDORF_P2 *((volatile uint8_t *)(0x42DE8788UL)) +#define bFM4_GPIO_PDORF_P2 *((volatile uint8_t *)(0x42DE8788UL)) +#define bFM_GPIO_PDORF_P3 *((volatile uint8_t *)(0x42DE878CUL)) +#define bFM4_GPIO_PDORF_P3 *((volatile uint8_t *)(0x42DE878CUL)) +#define bFM_GPIO_PDORF_P4 *((volatile uint8_t *)(0x42DE8790UL)) +#define bFM4_GPIO_PDORF_P4 *((volatile uint8_t *)(0x42DE8790UL)) +#define bFM_GPIO_PDORF_P5 *((volatile uint8_t *)(0x42DE8794UL)) +#define bFM4_GPIO_PDORF_P5 *((volatile uint8_t *)(0x42DE8794UL)) +#define bFM_GPIO_PDORF_P6 *((volatile uint8_t *)(0x42DE8798UL)) +#define bFM4_GPIO_PDORF_P6 *((volatile uint8_t *)(0x42DE8798UL)) +#define bFM_GPIO_PDORF_P7 *((volatile uint8_t *)(0x42DE879CUL)) +#define bFM4_GPIO_PDORF_P7 *((volatile uint8_t *)(0x42DE879CUL)) +#define bFM_GPIO_PDORF_P8 *((volatile uint8_t *)(0x42DE87A0UL)) +#define bFM4_GPIO_PDORF_P8 *((volatile uint8_t *)(0x42DE87A0UL)) +#define bFM_GPIO_PDORF_P9 *((volatile uint8_t *)(0x42DE87A4UL)) +#define bFM4_GPIO_PDORF_P9 *((volatile uint8_t *)(0x42DE87A4UL)) +#define bFM_GPIO_PDORF_PA *((volatile uint8_t *)(0x42DE87A8UL)) +#define bFM4_GPIO_PDORF_PA *((volatile uint8_t *)(0x42DE87A8UL)) +#define bFM_GPIO_PDORF_PB *((volatile uint8_t *)(0x42DE87ACUL)) +#define bFM4_GPIO_PDORF_PB *((volatile uint8_t *)(0x42DE87ACUL)) +#define bFM_GPIO_PDORF_PC *((volatile uint8_t *)(0x42DE87B0UL)) +#define bFM4_GPIO_PDORF_PC *((volatile uint8_t *)(0x42DE87B0UL)) + +#define bFM_GPIO_PDSR0_P0 *((volatile uint8_t *)(0x42DEE800UL)) +#define bFM4_GPIO_PDSR0_P0 *((volatile uint8_t *)(0x42DEE800UL)) +#define bFM_GPIO_PDSR0_P1 *((volatile uint8_t *)(0x42DEE804UL)) +#define bFM4_GPIO_PDSR0_P1 *((volatile uint8_t *)(0x42DEE804UL)) +#define bFM_GPIO_PDSR0_P2 *((volatile uint8_t *)(0x42DEE808UL)) +#define bFM4_GPIO_PDSR0_P2 *((volatile uint8_t *)(0x42DEE808UL)) +#define bFM_GPIO_PDSR0_P3 *((volatile uint8_t *)(0x42DEE80CUL)) +#define bFM4_GPIO_PDSR0_P3 *((volatile uint8_t *)(0x42DEE80CUL)) +#define bFM_GPIO_PDSR0_P4 *((volatile uint8_t *)(0x42DEE810UL)) +#define bFM4_GPIO_PDSR0_P4 *((volatile uint8_t *)(0x42DEE810UL)) +#define bFM_GPIO_PDSR0_P8 *((volatile uint8_t *)(0x42DEE820UL)) +#define bFM4_GPIO_PDSR0_P8 *((volatile uint8_t *)(0x42DEE820UL)) +#define bFM_GPIO_PDSR0_P9 *((volatile uint8_t *)(0x42DEE824UL)) +#define bFM4_GPIO_PDSR0_P9 *((volatile uint8_t *)(0x42DEE824UL)) +#define bFM_GPIO_PDSR0_PA *((volatile uint8_t *)(0x42DEE828UL)) +#define bFM4_GPIO_PDSR0_PA *((volatile uint8_t *)(0x42DEE828UL)) + +#define bFM_GPIO_PDSR1_P0 *((volatile uint8_t *)(0x42DEE880UL)) +#define bFM4_GPIO_PDSR1_P0 *((volatile uint8_t *)(0x42DEE880UL)) +#define bFM_GPIO_PDSR1_P1 *((volatile uint8_t *)(0x42DEE884UL)) +#define bFM4_GPIO_PDSR1_P1 *((volatile uint8_t *)(0x42DEE884UL)) +#define bFM_GPIO_PDSR1_P2 *((volatile uint8_t *)(0x42DEE888UL)) +#define bFM4_GPIO_PDSR1_P2 *((volatile uint8_t *)(0x42DEE888UL)) +#define bFM_GPIO_PDSR1_P3 *((volatile uint8_t *)(0x42DEE88CUL)) +#define bFM4_GPIO_PDSR1_P3 *((volatile uint8_t *)(0x42DEE88CUL)) +#define bFM_GPIO_PDSR1_P4 *((volatile uint8_t *)(0x42DEE890UL)) +#define bFM4_GPIO_PDSR1_P4 *((volatile uint8_t *)(0x42DEE890UL)) +#define bFM_GPIO_PDSR1_P5 *((volatile uint8_t *)(0x42DEE894UL)) +#define bFM4_GPIO_PDSR1_P5 *((volatile uint8_t *)(0x42DEE894UL)) +#define bFM_GPIO_PDSR1_P6 *((volatile uint8_t *)(0x42DEE898UL)) +#define bFM4_GPIO_PDSR1_P6 *((volatile uint8_t *)(0x42DEE898UL)) +#define bFM_GPIO_PDSR1_P7 *((volatile uint8_t *)(0x42DEE89CUL)) +#define bFM4_GPIO_PDSR1_P7 *((volatile uint8_t *)(0x42DEE89CUL)) +#define bFM_GPIO_PDSR1_P8 *((volatile uint8_t *)(0x42DEE8A0UL)) +#define bFM4_GPIO_PDSR1_P8 *((volatile uint8_t *)(0x42DEE8A0UL)) +#define bFM_GPIO_PDSR1_P9 *((volatile uint8_t *)(0x42DEE8A4UL)) +#define bFM4_GPIO_PDSR1_P9 *((volatile uint8_t *)(0x42DEE8A4UL)) +#define bFM_GPIO_PDSR1_PA *((volatile uint8_t *)(0x42DEE8A8UL)) +#define bFM4_GPIO_PDSR1_PA *((volatile uint8_t *)(0x42DEE8A8UL)) +#define bFM_GPIO_PDSR1_PB *((volatile uint8_t *)(0x42DEE8ACUL)) +#define bFM4_GPIO_PDSR1_PB *((volatile uint8_t *)(0x42DEE8ACUL)) +#define bFM_GPIO_PDSR1_PC *((volatile uint8_t *)(0x42DEE8B0UL)) +#define bFM4_GPIO_PDSR1_PC *((volatile uint8_t *)(0x42DEE8B0UL)) +#define bFM_GPIO_PDSR1_PD *((volatile uint8_t *)(0x42DEE8B4UL)) +#define bFM4_GPIO_PDSR1_PD *((volatile uint8_t *)(0x42DEE8B4UL)) +#define bFM_GPIO_PDSR1_PE *((volatile uint8_t *)(0x42DEE8B8UL)) +#define bFM4_GPIO_PDSR1_PE *((volatile uint8_t *)(0x42DEE8B8UL)) +#define bFM_GPIO_PDSR1_PF *((volatile uint8_t *)(0x42DEE8BCUL)) +#define bFM4_GPIO_PDSR1_PF *((volatile uint8_t *)(0x42DEE8BCUL)) + +#define bFM_GPIO_PDSR2_P0 *((volatile uint8_t *)(0x42DEE900UL)) +#define bFM4_GPIO_PDSR2_P0 *((volatile uint8_t *)(0x42DEE900UL)) +#define bFM_GPIO_PDSR2_P1 *((volatile uint8_t *)(0x42DEE904UL)) +#define bFM4_GPIO_PDSR2_P1 *((volatile uint8_t *)(0x42DEE904UL)) +#define bFM_GPIO_PDSR2_P2 *((volatile uint8_t *)(0x42DEE908UL)) +#define bFM4_GPIO_PDSR2_P2 *((volatile uint8_t *)(0x42DEE908UL)) +#define bFM_GPIO_PDSR2_P3 *((volatile uint8_t *)(0x42DEE90CUL)) +#define bFM4_GPIO_PDSR2_P3 *((volatile uint8_t *)(0x42DEE90CUL)) +#define bFM_GPIO_PDSR2_P4 *((volatile uint8_t *)(0x42DEE910UL)) +#define bFM4_GPIO_PDSR2_P4 *((volatile uint8_t *)(0x42DEE910UL)) +#define bFM_GPIO_PDSR2_P5 *((volatile uint8_t *)(0x42DEE914UL)) +#define bFM4_GPIO_PDSR2_P5 *((volatile uint8_t *)(0x42DEE914UL)) +#define bFM_GPIO_PDSR2_P6 *((volatile uint8_t *)(0x42DEE918UL)) +#define bFM4_GPIO_PDSR2_P6 *((volatile uint8_t *)(0x42DEE918UL)) +#define bFM_GPIO_PDSR2_P7 *((volatile uint8_t *)(0x42DEE91CUL)) +#define bFM4_GPIO_PDSR2_P7 *((volatile uint8_t *)(0x42DEE91CUL)) +#define bFM_GPIO_PDSR2_P8 *((volatile uint8_t *)(0x42DEE920UL)) +#define bFM4_GPIO_PDSR2_P8 *((volatile uint8_t *)(0x42DEE920UL)) +#define bFM_GPIO_PDSR2_P9 *((volatile uint8_t *)(0x42DEE924UL)) +#define bFM4_GPIO_PDSR2_P9 *((volatile uint8_t *)(0x42DEE924UL)) +#define bFM_GPIO_PDSR2_PA *((volatile uint8_t *)(0x42DEE928UL)) +#define bFM4_GPIO_PDSR2_PA *((volatile uint8_t *)(0x42DEE928UL)) + +#define bFM_GPIO_PDSR3_P0 *((volatile uint8_t *)(0x42DEE980UL)) +#define bFM4_GPIO_PDSR3_P0 *((volatile uint8_t *)(0x42DEE980UL)) +#define bFM_GPIO_PDSR3_P1 *((volatile uint8_t *)(0x42DEE984UL)) +#define bFM4_GPIO_PDSR3_P1 *((volatile uint8_t *)(0x42DEE984UL)) +#define bFM_GPIO_PDSR3_P2 *((volatile uint8_t *)(0x42DEE988UL)) +#define bFM4_GPIO_PDSR3_P2 *((volatile uint8_t *)(0x42DEE988UL)) +#define bFM_GPIO_PDSR3_P3 *((volatile uint8_t *)(0x42DEE98CUL)) +#define bFM4_GPIO_PDSR3_P3 *((volatile uint8_t *)(0x42DEE98CUL)) +#define bFM_GPIO_PDSR3_P4 *((volatile uint8_t *)(0x42DEE990UL)) +#define bFM4_GPIO_PDSR3_P4 *((volatile uint8_t *)(0x42DEE990UL)) +#define bFM_GPIO_PDSR3_P5 *((volatile uint8_t *)(0x42DEE994UL)) +#define bFM4_GPIO_PDSR3_P5 *((volatile uint8_t *)(0x42DEE994UL)) +#define bFM_GPIO_PDSR3_P6 *((volatile uint8_t *)(0x42DEE998UL)) +#define bFM4_GPIO_PDSR3_P6 *((volatile uint8_t *)(0x42DEE998UL)) +#define bFM_GPIO_PDSR3_P7 *((volatile uint8_t *)(0x42DEE99CUL)) +#define bFM4_GPIO_PDSR3_P7 *((volatile uint8_t *)(0x42DEE99CUL)) +#define bFM_GPIO_PDSR3_P8 *((volatile uint8_t *)(0x42DEE9A0UL)) +#define bFM4_GPIO_PDSR3_P8 *((volatile uint8_t *)(0x42DEE9A0UL)) +#define bFM_GPIO_PDSR3_P9 *((volatile uint8_t *)(0x42DEE9A4UL)) +#define bFM4_GPIO_PDSR3_P9 *((volatile uint8_t *)(0x42DEE9A4UL)) +#define bFM_GPIO_PDSR3_PA *((volatile uint8_t *)(0x42DEE9A8UL)) +#define bFM4_GPIO_PDSR3_PA *((volatile uint8_t *)(0x42DEE9A8UL)) +#define bFM_GPIO_PDSR3_PB *((volatile uint8_t *)(0x42DEE9ACUL)) +#define bFM4_GPIO_PDSR3_PB *((volatile uint8_t *)(0x42DEE9ACUL)) +#define bFM_GPIO_PDSR3_PC *((volatile uint8_t *)(0x42DEE9B0UL)) +#define bFM4_GPIO_PDSR3_PC *((volatile uint8_t *)(0x42DEE9B0UL)) +#define bFM_GPIO_PDSR3_PD *((volatile uint8_t *)(0x42DEE9B4UL)) +#define bFM4_GPIO_PDSR3_PD *((volatile uint8_t *)(0x42DEE9B4UL)) +#define bFM_GPIO_PDSR3_PE *((volatile uint8_t *)(0x42DEE9B8UL)) +#define bFM4_GPIO_PDSR3_PE *((volatile uint8_t *)(0x42DEE9B8UL)) + +#define bFM_GPIO_PDSR4_P0 *((volatile uint8_t *)(0x42DEEA00UL)) +#define bFM4_GPIO_PDSR4_P0 *((volatile uint8_t *)(0x42DEEA00UL)) +#define bFM_GPIO_PDSR4_P1 *((volatile uint8_t *)(0x42DEEA04UL)) +#define bFM4_GPIO_PDSR4_P1 *((volatile uint8_t *)(0x42DEEA04UL)) +#define bFM_GPIO_PDSR4_P2 *((volatile uint8_t *)(0x42DEEA08UL)) +#define bFM4_GPIO_PDSR4_P2 *((volatile uint8_t *)(0x42DEEA08UL)) +#define bFM_GPIO_PDSR4_P3 *((volatile uint8_t *)(0x42DEEA0CUL)) +#define bFM4_GPIO_PDSR4_P3 *((volatile uint8_t *)(0x42DEEA0CUL)) +#define bFM_GPIO_PDSR4_P4 *((volatile uint8_t *)(0x42DEEA10UL)) +#define bFM4_GPIO_PDSR4_P4 *((volatile uint8_t *)(0x42DEEA10UL)) +#define bFM_GPIO_PDSR4_P5 *((volatile uint8_t *)(0x42DEEA14UL)) +#define bFM4_GPIO_PDSR4_P5 *((volatile uint8_t *)(0x42DEEA14UL)) +#define bFM_GPIO_PDSR4_P6 *((volatile uint8_t *)(0x42DEEA18UL)) +#define bFM4_GPIO_PDSR4_P6 *((volatile uint8_t *)(0x42DEEA18UL)) +#define bFM_GPIO_PDSR4_P7 *((volatile uint8_t *)(0x42DEEA1CUL)) +#define bFM4_GPIO_PDSR4_P7 *((volatile uint8_t *)(0x42DEEA1CUL)) +#define bFM_GPIO_PDSR4_P8 *((volatile uint8_t *)(0x42DEEA20UL)) +#define bFM4_GPIO_PDSR4_P8 *((volatile uint8_t *)(0x42DEEA20UL)) +#define bFM_GPIO_PDSR4_P9 *((volatile uint8_t *)(0x42DEEA24UL)) +#define bFM4_GPIO_PDSR4_P9 *((volatile uint8_t *)(0x42DEEA24UL)) +#define bFM_GPIO_PDSR4_PA *((volatile uint8_t *)(0x42DEEA28UL)) +#define bFM4_GPIO_PDSR4_PA *((volatile uint8_t *)(0x42DEEA28UL)) +#define bFM_GPIO_PDSR4_PB *((volatile uint8_t *)(0x42DEEA2CUL)) +#define bFM4_GPIO_PDSR4_PB *((volatile uint8_t *)(0x42DEEA2CUL)) +#define bFM_GPIO_PDSR4_PC *((volatile uint8_t *)(0x42DEEA30UL)) +#define bFM4_GPIO_PDSR4_PC *((volatile uint8_t *)(0x42DEEA30UL)) +#define bFM_GPIO_PDSR4_PD *((volatile uint8_t *)(0x42DEEA34UL)) +#define bFM4_GPIO_PDSR4_PD *((volatile uint8_t *)(0x42DEEA34UL)) +#define bFM_GPIO_PDSR4_PE *((volatile uint8_t *)(0x42DEEA38UL)) +#define bFM4_GPIO_PDSR4_PE *((volatile uint8_t *)(0x42DEEA38UL)) + +#define bFM_GPIO_PDSR5_P0 *((volatile uint8_t *)(0x42DEEA80UL)) +#define bFM4_GPIO_PDSR5_P0 *((volatile uint8_t *)(0x42DEEA80UL)) +#define bFM_GPIO_PDSR5_P1 *((volatile uint8_t *)(0x42DEEA84UL)) +#define bFM4_GPIO_PDSR5_P1 *((volatile uint8_t *)(0x42DEEA84UL)) +#define bFM_GPIO_PDSR5_P2 *((volatile uint8_t *)(0x42DEEA88UL)) +#define bFM4_GPIO_PDSR5_P2 *((volatile uint8_t *)(0x42DEEA88UL)) +#define bFM_GPIO_PDSR5_P3 *((volatile uint8_t *)(0x42DEEA8CUL)) +#define bFM4_GPIO_PDSR5_P3 *((volatile uint8_t *)(0x42DEEA8CUL)) +#define bFM_GPIO_PDSR5_P4 *((volatile uint8_t *)(0x42DEEA90UL)) +#define bFM4_GPIO_PDSR5_P4 *((volatile uint8_t *)(0x42DEEA90UL)) +#define bFM_GPIO_PDSR5_P5 *((volatile uint8_t *)(0x42DEEA94UL)) +#define bFM4_GPIO_PDSR5_P5 *((volatile uint8_t *)(0x42DEEA94UL)) +#define bFM_GPIO_PDSR5_P6 *((volatile uint8_t *)(0x42DEEA98UL)) +#define bFM4_GPIO_PDSR5_P6 *((volatile uint8_t *)(0x42DEEA98UL)) +#define bFM_GPIO_PDSR5_P7 *((volatile uint8_t *)(0x42DEEA9CUL)) +#define bFM4_GPIO_PDSR5_P7 *((volatile uint8_t *)(0x42DEEA9CUL)) +#define bFM_GPIO_PDSR5_P8 *((volatile uint8_t *)(0x42DEEAA0UL)) +#define bFM4_GPIO_PDSR5_P8 *((volatile uint8_t *)(0x42DEEAA0UL)) +#define bFM_GPIO_PDSR5_P9 *((volatile uint8_t *)(0x42DEEAA4UL)) +#define bFM4_GPIO_PDSR5_P9 *((volatile uint8_t *)(0x42DEEAA4UL)) +#define bFM_GPIO_PDSR5_PA *((volatile uint8_t *)(0x42DEEAA8UL)) +#define bFM4_GPIO_PDSR5_PA *((volatile uint8_t *)(0x42DEEAA8UL)) +#define bFM_GPIO_PDSR5_PB *((volatile uint8_t *)(0x42DEEAACUL)) +#define bFM4_GPIO_PDSR5_PB *((volatile uint8_t *)(0x42DEEAACUL)) +#define bFM_GPIO_PDSR5_PC *((volatile uint8_t *)(0x42DEEAB0UL)) +#define bFM4_GPIO_PDSR5_PC *((volatile uint8_t *)(0x42DEEAB0UL)) +#define bFM_GPIO_PDSR5_PD *((volatile uint8_t *)(0x42DEEAB4UL)) +#define bFM4_GPIO_PDSR5_PD *((volatile uint8_t *)(0x42DEEAB4UL)) +#define bFM_GPIO_PDSR5_PE *((volatile uint8_t *)(0x42DEEAB8UL)) +#define bFM4_GPIO_PDSR5_PE *((volatile uint8_t *)(0x42DEEAB8UL)) +#define bFM_GPIO_PDSR5_PF *((volatile uint8_t *)(0x42DEEABCUL)) +#define bFM4_GPIO_PDSR5_PF *((volatile uint8_t *)(0x42DEEABCUL)) + +#define bFM_GPIO_PDSR6_P0 *((volatile uint8_t *)(0x42DEEB00UL)) +#define bFM4_GPIO_PDSR6_P0 *((volatile uint8_t *)(0x42DEEB00UL)) +#define bFM_GPIO_PDSR6_P1 *((volatile uint8_t *)(0x42DEEB04UL)) +#define bFM4_GPIO_PDSR6_P1 *((volatile uint8_t *)(0x42DEEB04UL)) +#define bFM_GPIO_PDSR6_P2 *((volatile uint8_t *)(0x42DEEB08UL)) +#define bFM4_GPIO_PDSR6_P2 *((volatile uint8_t *)(0x42DEEB08UL)) +#define bFM_GPIO_PDSR6_P3 *((volatile uint8_t *)(0x42DEEB0CUL)) +#define bFM4_GPIO_PDSR6_P3 *((volatile uint8_t *)(0x42DEEB0CUL)) +#define bFM_GPIO_PDSR6_P4 *((volatile uint8_t *)(0x42DEEB10UL)) +#define bFM4_GPIO_PDSR6_P4 *((volatile uint8_t *)(0x42DEEB10UL)) +#define bFM_GPIO_PDSR6_P5 *((volatile uint8_t *)(0x42DEEB14UL)) +#define bFM4_GPIO_PDSR6_P5 *((volatile uint8_t *)(0x42DEEB14UL)) +#define bFM_GPIO_PDSR6_P6 *((volatile uint8_t *)(0x42DEEB18UL)) +#define bFM4_GPIO_PDSR6_P6 *((volatile uint8_t *)(0x42DEEB18UL)) +#define bFM_GPIO_PDSR6_P7 *((volatile uint8_t *)(0x42DEEB1CUL)) +#define bFM4_GPIO_PDSR6_P7 *((volatile uint8_t *)(0x42DEEB1CUL)) +#define bFM_GPIO_PDSR6_P8 *((volatile uint8_t *)(0x42DEEB20UL)) +#define bFM4_GPIO_PDSR6_P8 *((volatile uint8_t *)(0x42DEEB20UL)) +#define bFM_GPIO_PDSR6_P9 *((volatile uint8_t *)(0x42DEEB24UL)) +#define bFM4_GPIO_PDSR6_P9 *((volatile uint8_t *)(0x42DEEB24UL)) +#define bFM_GPIO_PDSR6_PA *((volatile uint8_t *)(0x42DEEB28UL)) +#define bFM4_GPIO_PDSR6_PA *((volatile uint8_t *)(0x42DEEB28UL)) +#define bFM_GPIO_PDSR6_PB *((volatile uint8_t *)(0x42DEEB2CUL)) +#define bFM4_GPIO_PDSR6_PB *((volatile uint8_t *)(0x42DEEB2CUL)) +#define bFM_GPIO_PDSR6_PC *((volatile uint8_t *)(0x42DEEB30UL)) +#define bFM4_GPIO_PDSR6_PC *((volatile uint8_t *)(0x42DEEB30UL)) +#define bFM_GPIO_PDSR6_PD *((volatile uint8_t *)(0x42DEEB34UL)) +#define bFM4_GPIO_PDSR6_PD *((volatile uint8_t *)(0x42DEEB34UL)) +#define bFM_GPIO_PDSR6_PE *((volatile uint8_t *)(0x42DEEB38UL)) +#define bFM4_GPIO_PDSR6_PE *((volatile uint8_t *)(0x42DEEB38UL)) + +#define bFM_GPIO_PDSR7_P0 *((volatile uint8_t *)(0x42DEEB80UL)) +#define bFM4_GPIO_PDSR7_P0 *((volatile uint8_t *)(0x42DEEB80UL)) +#define bFM_GPIO_PDSR7_P1 *((volatile uint8_t *)(0x42DEEB84UL)) +#define bFM4_GPIO_PDSR7_P1 *((volatile uint8_t *)(0x42DEEB84UL)) +#define bFM_GPIO_PDSR7_P2 *((volatile uint8_t *)(0x42DEEB88UL)) +#define bFM4_GPIO_PDSR7_P2 *((volatile uint8_t *)(0x42DEEB88UL)) +#define bFM_GPIO_PDSR7_P3 *((volatile uint8_t *)(0x42DEEB8CUL)) +#define bFM4_GPIO_PDSR7_P3 *((volatile uint8_t *)(0x42DEEB8CUL)) +#define bFM_GPIO_PDSR7_P4 *((volatile uint8_t *)(0x42DEEB90UL)) +#define bFM4_GPIO_PDSR7_P4 *((volatile uint8_t *)(0x42DEEB90UL)) +#define bFM_GPIO_PDSR7_P5 *((volatile uint8_t *)(0x42DEEB94UL)) +#define bFM4_GPIO_PDSR7_P5 *((volatile uint8_t *)(0x42DEEB94UL)) +#define bFM_GPIO_PDSR7_P6 *((volatile uint8_t *)(0x42DEEB98UL)) +#define bFM4_GPIO_PDSR7_P6 *((volatile uint8_t *)(0x42DEEB98UL)) +#define bFM_GPIO_PDSR7_P7 *((volatile uint8_t *)(0x42DEEB9CUL)) +#define bFM4_GPIO_PDSR7_P7 *((volatile uint8_t *)(0x42DEEB9CUL)) +#define bFM_GPIO_PDSR7_P8 *((volatile uint8_t *)(0x42DEEBA0UL)) +#define bFM4_GPIO_PDSR7_P8 *((volatile uint8_t *)(0x42DEEBA0UL)) +#define bFM_GPIO_PDSR7_P9 *((volatile uint8_t *)(0x42DEEBA4UL)) +#define bFM4_GPIO_PDSR7_P9 *((volatile uint8_t *)(0x42DEEBA4UL)) +#define bFM_GPIO_PDSR7_PA *((volatile uint8_t *)(0x42DEEBA8UL)) +#define bFM4_GPIO_PDSR7_PA *((volatile uint8_t *)(0x42DEEBA8UL)) +#define bFM_GPIO_PDSR7_PB *((volatile uint8_t *)(0x42DEEBACUL)) +#define bFM4_GPIO_PDSR7_PB *((volatile uint8_t *)(0x42DEEBACUL)) +#define bFM_GPIO_PDSR7_PC *((volatile uint8_t *)(0x42DEEBB0UL)) +#define bFM4_GPIO_PDSR7_PC *((volatile uint8_t *)(0x42DEEBB0UL)) +#define bFM_GPIO_PDSR7_PD *((volatile uint8_t *)(0x42DEEBB4UL)) +#define bFM4_GPIO_PDSR7_PD *((volatile uint8_t *)(0x42DEEBB4UL)) +#define bFM_GPIO_PDSR7_PE *((volatile uint8_t *)(0x42DEEBB8UL)) +#define bFM4_GPIO_PDSR7_PE *((volatile uint8_t *)(0x42DEEBB8UL)) + +#define bFM_GPIO_PDSR8_P0 *((volatile uint8_t *)(0x42DEEC00UL)) +#define bFM4_GPIO_PDSR8_P0 *((volatile uint8_t *)(0x42DEEC00UL)) +#define bFM_GPIO_PDSR8_P1 *((volatile uint8_t *)(0x42DEEC04UL)) +#define bFM4_GPIO_PDSR8_P1 *((volatile uint8_t *)(0x42DEEC04UL)) +#define bFM_GPIO_PDSR8_P2 *((volatile uint8_t *)(0x42DEEC08UL)) +#define bFM4_GPIO_PDSR8_P2 *((volatile uint8_t *)(0x42DEEC08UL)) +#define bFM_GPIO_PDSR8_P3 *((volatile uint8_t *)(0x42DEEC0CUL)) +#define bFM4_GPIO_PDSR8_P3 *((volatile uint8_t *)(0x42DEEC0CUL)) + +#define bFM_GPIO_PDSR9_P0 *((volatile uint8_t *)(0x42DEEC80UL)) +#define bFM4_GPIO_PDSR9_P0 *((volatile uint8_t *)(0x42DEEC80UL)) +#define bFM_GPIO_PDSR9_P1 *((volatile uint8_t *)(0x42DEEC84UL)) +#define bFM4_GPIO_PDSR9_P1 *((volatile uint8_t *)(0x42DEEC84UL)) +#define bFM_GPIO_PDSR9_P2 *((volatile uint8_t *)(0x42DEEC88UL)) +#define bFM4_GPIO_PDSR9_P2 *((volatile uint8_t *)(0x42DEEC88UL)) +#define bFM_GPIO_PDSR9_P3 *((volatile uint8_t *)(0x42DEEC8CUL)) +#define bFM4_GPIO_PDSR9_P3 *((volatile uint8_t *)(0x42DEEC8CUL)) +#define bFM_GPIO_PDSR9_P4 *((volatile uint8_t *)(0x42DEEC90UL)) +#define bFM4_GPIO_PDSR9_P4 *((volatile uint8_t *)(0x42DEEC90UL)) +#define bFM_GPIO_PDSR9_P5 *((volatile uint8_t *)(0x42DEEC94UL)) +#define bFM4_GPIO_PDSR9_P5 *((volatile uint8_t *)(0x42DEEC94UL)) +#define bFM_GPIO_PDSR9_P6 *((volatile uint8_t *)(0x42DEEC98UL)) +#define bFM4_GPIO_PDSR9_P6 *((volatile uint8_t *)(0x42DEEC98UL)) +#define bFM_GPIO_PDSR9_P7 *((volatile uint8_t *)(0x42DEEC9CUL)) +#define bFM4_GPIO_PDSR9_P7 *((volatile uint8_t *)(0x42DEEC9CUL)) + +#define bFM_GPIO_PDSRA_P0 *((volatile uint8_t *)(0x42DEED00UL)) +#define bFM4_GPIO_PDSRA_P0 *((volatile uint8_t *)(0x42DEED00UL)) +#define bFM_GPIO_PDSRA_P1 *((volatile uint8_t *)(0x42DEED04UL)) +#define bFM4_GPIO_PDSRA_P1 *((volatile uint8_t *)(0x42DEED04UL)) +#define bFM_GPIO_PDSRA_P2 *((volatile uint8_t *)(0x42DEED08UL)) +#define bFM4_GPIO_PDSRA_P2 *((volatile uint8_t *)(0x42DEED08UL)) +#define bFM_GPIO_PDSRA_P3 *((volatile uint8_t *)(0x42DEED0CUL)) +#define bFM4_GPIO_PDSRA_P3 *((volatile uint8_t *)(0x42DEED0CUL)) +#define bFM_GPIO_PDSRA_P4 *((volatile uint8_t *)(0x42DEED10UL)) +#define bFM4_GPIO_PDSRA_P4 *((volatile uint8_t *)(0x42DEED10UL)) +#define bFM_GPIO_PDSRA_P5 *((volatile uint8_t *)(0x42DEED14UL)) +#define bFM4_GPIO_PDSRA_P5 *((volatile uint8_t *)(0x42DEED14UL)) +#define bFM_GPIO_PDSRA_P6 *((volatile uint8_t *)(0x42DEED18UL)) +#define bFM4_GPIO_PDSRA_P6 *((volatile uint8_t *)(0x42DEED18UL)) +#define bFM_GPIO_PDSRA_P7 *((volatile uint8_t *)(0x42DEED1CUL)) +#define bFM4_GPIO_PDSRA_P7 *((volatile uint8_t *)(0x42DEED1CUL)) +#define bFM_GPIO_PDSRA_P8 *((volatile uint8_t *)(0x42DEED20UL)) +#define bFM4_GPIO_PDSRA_P8 *((volatile uint8_t *)(0x42DEED20UL)) +#define bFM_GPIO_PDSRA_P9 *((volatile uint8_t *)(0x42DEED24UL)) +#define bFM4_GPIO_PDSRA_P9 *((volatile uint8_t *)(0x42DEED24UL)) +#define bFM_GPIO_PDSRA_PA *((volatile uint8_t *)(0x42DEED28UL)) +#define bFM4_GPIO_PDSRA_PA *((volatile uint8_t *)(0x42DEED28UL)) +#define bFM_GPIO_PDSRA_PB *((volatile uint8_t *)(0x42DEED2CUL)) +#define bFM4_GPIO_PDSRA_PB *((volatile uint8_t *)(0x42DEED2CUL)) +#define bFM_GPIO_PDSRA_PC *((volatile uint8_t *)(0x42DEED30UL)) +#define bFM4_GPIO_PDSRA_PC *((volatile uint8_t *)(0x42DEED30UL)) +#define bFM_GPIO_PDSRA_PD *((volatile uint8_t *)(0x42DEED34UL)) +#define bFM4_GPIO_PDSRA_PD *((volatile uint8_t *)(0x42DEED34UL)) +#define bFM_GPIO_PDSRA_PE *((volatile uint8_t *)(0x42DEED38UL)) +#define bFM4_GPIO_PDSRA_PE *((volatile uint8_t *)(0x42DEED38UL)) +#define bFM_GPIO_PDSRA_PF *((volatile uint8_t *)(0x42DEED3CUL)) +#define bFM4_GPIO_PDSRA_PF *((volatile uint8_t *)(0x42DEED3CUL)) + +#define bFM_GPIO_PDSRB_P0 *((volatile uint8_t *)(0x42DEED80UL)) +#define bFM4_GPIO_PDSRB_P0 *((volatile uint8_t *)(0x42DEED80UL)) +#define bFM_GPIO_PDSRB_P1 *((volatile uint8_t *)(0x42DEED84UL)) +#define bFM4_GPIO_PDSRB_P1 *((volatile uint8_t *)(0x42DEED84UL)) +#define bFM_GPIO_PDSRB_P2 *((volatile uint8_t *)(0x42DEED88UL)) +#define bFM4_GPIO_PDSRB_P2 *((volatile uint8_t *)(0x42DEED88UL)) +#define bFM_GPIO_PDSRB_P3 *((volatile uint8_t *)(0x42DEED8CUL)) +#define bFM4_GPIO_PDSRB_P3 *((volatile uint8_t *)(0x42DEED8CUL)) +#define bFM_GPIO_PDSRB_P4 *((volatile uint8_t *)(0x42DEED90UL)) +#define bFM4_GPIO_PDSRB_P4 *((volatile uint8_t *)(0x42DEED90UL)) +#define bFM_GPIO_PDSRB_P5 *((volatile uint8_t *)(0x42DEED94UL)) +#define bFM4_GPIO_PDSRB_P5 *((volatile uint8_t *)(0x42DEED94UL)) +#define bFM_GPIO_PDSRB_P6 *((volatile uint8_t *)(0x42DEED98UL)) +#define bFM4_GPIO_PDSRB_P6 *((volatile uint8_t *)(0x42DEED98UL)) +#define bFM_GPIO_PDSRB_P7 *((volatile uint8_t *)(0x42DEED9CUL)) +#define bFM4_GPIO_PDSRB_P7 *((volatile uint8_t *)(0x42DEED9CUL)) +#define bFM_GPIO_PDSRB_P8 *((volatile uint8_t *)(0x42DEEDA0UL)) +#define bFM4_GPIO_PDSRB_P8 *((volatile uint8_t *)(0x42DEEDA0UL)) +#define bFM_GPIO_PDSRB_P9 *((volatile uint8_t *)(0x42DEEDA4UL)) +#define bFM4_GPIO_PDSRB_P9 *((volatile uint8_t *)(0x42DEEDA4UL)) +#define bFM_GPIO_PDSRB_PA *((volatile uint8_t *)(0x42DEEDA8UL)) +#define bFM4_GPIO_PDSRB_PA *((volatile uint8_t *)(0x42DEEDA8UL)) +#define bFM_GPIO_PDSRB_PB *((volatile uint8_t *)(0x42DEEDACUL)) +#define bFM4_GPIO_PDSRB_PB *((volatile uint8_t *)(0x42DEEDACUL)) +#define bFM_GPIO_PDSRB_PC *((volatile uint8_t *)(0x42DEEDB0UL)) +#define bFM4_GPIO_PDSRB_PC *((volatile uint8_t *)(0x42DEEDB0UL)) +#define bFM_GPIO_PDSRB_PD *((volatile uint8_t *)(0x42DEEDB4UL)) +#define bFM4_GPIO_PDSRB_PD *((volatile uint8_t *)(0x42DEEDB4UL)) +#define bFM_GPIO_PDSRB_PE *((volatile uint8_t *)(0x42DEEDB8UL)) +#define bFM4_GPIO_PDSRB_PE *((volatile uint8_t *)(0x42DEEDB8UL)) +#define bFM_GPIO_PDSRB_PF *((volatile uint8_t *)(0x42DEEDBCUL)) +#define bFM4_GPIO_PDSRB_PF *((volatile uint8_t *)(0x42DEEDBCUL)) + +#define bFM_GPIO_PDSRC_P0 *((volatile uint8_t *)(0x42DEEE00UL)) +#define bFM4_GPIO_PDSRC_P0 *((volatile uint8_t *)(0x42DEEE00UL)) +#define bFM_GPIO_PDSRC_P1 *((volatile uint8_t *)(0x42DEEE04UL)) +#define bFM4_GPIO_PDSRC_P1 *((volatile uint8_t *)(0x42DEEE04UL)) +#define bFM_GPIO_PDSRC_P2 *((volatile uint8_t *)(0x42DEEE08UL)) +#define bFM4_GPIO_PDSRC_P2 *((volatile uint8_t *)(0x42DEEE08UL)) +#define bFM_GPIO_PDSRC_P3 *((volatile uint8_t *)(0x42DEEE0CUL)) +#define bFM4_GPIO_PDSRC_P3 *((volatile uint8_t *)(0x42DEEE0CUL)) +#define bFM_GPIO_PDSRC_P4 *((volatile uint8_t *)(0x42DEEE10UL)) +#define bFM4_GPIO_PDSRC_P4 *((volatile uint8_t *)(0x42DEEE10UL)) +#define bFM_GPIO_PDSRC_P5 *((volatile uint8_t *)(0x42DEEE14UL)) +#define bFM4_GPIO_PDSRC_P5 *((volatile uint8_t *)(0x42DEEE14UL)) +#define bFM_GPIO_PDSRC_P6 *((volatile uint8_t *)(0x42DEEE18UL)) +#define bFM4_GPIO_PDSRC_P6 *((volatile uint8_t *)(0x42DEEE18UL)) +#define bFM_GPIO_PDSRC_P7 *((volatile uint8_t *)(0x42DEEE1CUL)) +#define bFM4_GPIO_PDSRC_P7 *((volatile uint8_t *)(0x42DEEE1CUL)) +#define bFM_GPIO_PDSRC_P8 *((volatile uint8_t *)(0x42DEEE20UL)) +#define bFM4_GPIO_PDSRC_P8 *((volatile uint8_t *)(0x42DEEE20UL)) +#define bFM_GPIO_PDSRC_P9 *((volatile uint8_t *)(0x42DEEE24UL)) +#define bFM4_GPIO_PDSRC_P9 *((volatile uint8_t *)(0x42DEEE24UL)) +#define bFM_GPIO_PDSRC_PA *((volatile uint8_t *)(0x42DEEE28UL)) +#define bFM4_GPIO_PDSRC_PA *((volatile uint8_t *)(0x42DEEE28UL)) +#define bFM_GPIO_PDSRC_PB *((volatile uint8_t *)(0x42DEEE2CUL)) +#define bFM4_GPIO_PDSRC_PB *((volatile uint8_t *)(0x42DEEE2CUL)) +#define bFM_GPIO_PDSRC_PC *((volatile uint8_t *)(0x42DEEE30UL)) +#define bFM4_GPIO_PDSRC_PC *((volatile uint8_t *)(0x42DEEE30UL)) +#define bFM_GPIO_PDSRC_PD *((volatile uint8_t *)(0x42DEEE34UL)) +#define bFM4_GPIO_PDSRC_PD *((volatile uint8_t *)(0x42DEEE34UL)) +#define bFM_GPIO_PDSRC_PE *((volatile uint8_t *)(0x42DEEE38UL)) +#define bFM4_GPIO_PDSRC_PE *((volatile uint8_t *)(0x42DEEE38UL)) +#define bFM_GPIO_PDSRC_PF *((volatile uint8_t *)(0x42DEEE3CUL)) +#define bFM4_GPIO_PDSRC_PF *((volatile uint8_t *)(0x42DEEE3CUL)) + +#define bFM_GPIO_PDSRD_P0 *((volatile uint8_t *)(0x42DEEE80UL)) +#define bFM4_GPIO_PDSRD_P0 *((volatile uint8_t *)(0x42DEEE80UL)) +#define bFM_GPIO_PDSRD_P1 *((volatile uint8_t *)(0x42DEEE84UL)) +#define bFM4_GPIO_PDSRD_P1 *((volatile uint8_t *)(0x42DEEE84UL)) +#define bFM_GPIO_PDSRD_P2 *((volatile uint8_t *)(0x42DEEE88UL)) +#define bFM4_GPIO_PDSRD_P2 *((volatile uint8_t *)(0x42DEEE88UL)) + +#define bFM_GPIO_PDSRE_P0 *((volatile uint8_t *)(0x42DEEF00UL)) +#define bFM4_GPIO_PDSRE_P0 *((volatile uint8_t *)(0x42DEEF00UL)) +#define bFM_GPIO_PDSRE_P2 *((volatile uint8_t *)(0x42DEEF08UL)) +#define bFM4_GPIO_PDSRE_P2 *((volatile uint8_t *)(0x42DEEF08UL)) +#define bFM_GPIO_PDSRE_P3 *((volatile uint8_t *)(0x42DEEF0CUL)) +#define bFM4_GPIO_PDSRE_P3 *((volatile uint8_t *)(0x42DEEF0CUL)) + +#define bFM_GPIO_PDSRF_P0 *((volatile uint8_t *)(0x42DEEF80UL)) +#define bFM4_GPIO_PDSRF_P0 *((volatile uint8_t *)(0x42DEEF80UL)) +#define bFM_GPIO_PDSRF_P1 *((volatile uint8_t *)(0x42DEEF84UL)) +#define bFM4_GPIO_PDSRF_P1 *((volatile uint8_t *)(0x42DEEF84UL)) +#define bFM_GPIO_PDSRF_P2 *((volatile uint8_t *)(0x42DEEF88UL)) +#define bFM4_GPIO_PDSRF_P2 *((volatile uint8_t *)(0x42DEEF88UL)) +#define bFM_GPIO_PDSRF_P3 *((volatile uint8_t *)(0x42DEEF8CUL)) +#define bFM4_GPIO_PDSRF_P3 *((volatile uint8_t *)(0x42DEEF8CUL)) +#define bFM_GPIO_PDSRF_P4 *((volatile uint8_t *)(0x42DEEF90UL)) +#define bFM4_GPIO_PDSRF_P4 *((volatile uint8_t *)(0x42DEEF90UL)) +#define bFM_GPIO_PDSRF_P5 *((volatile uint8_t *)(0x42DEEF94UL)) +#define bFM4_GPIO_PDSRF_P5 *((volatile uint8_t *)(0x42DEEF94UL)) +#define bFM_GPIO_PDSRF_P6 *((volatile uint8_t *)(0x42DEEF98UL)) +#define bFM4_GPIO_PDSRF_P6 *((volatile uint8_t *)(0x42DEEF98UL)) +#define bFM_GPIO_PDSRF_P7 *((volatile uint8_t *)(0x42DEEF9CUL)) +#define bFM4_GPIO_PDSRF_P7 *((volatile uint8_t *)(0x42DEEF9CUL)) +#define bFM_GPIO_PDSRF_P8 *((volatile uint8_t *)(0x42DEEFA0UL)) +#define bFM4_GPIO_PDSRF_P8 *((volatile uint8_t *)(0x42DEEFA0UL)) +#define bFM_GPIO_PDSRF_P9 *((volatile uint8_t *)(0x42DEEFA4UL)) +#define bFM4_GPIO_PDSRF_P9 *((volatile uint8_t *)(0x42DEEFA4UL)) +#define bFM_GPIO_PDSRF_PA *((volatile uint8_t *)(0x42DEEFA8UL)) +#define bFM4_GPIO_PDSRF_PA *((volatile uint8_t *)(0x42DEEFA8UL)) +#define bFM_GPIO_PDSRF_PB *((volatile uint8_t *)(0x42DEEFACUL)) +#define bFM4_GPIO_PDSRF_PB *((volatile uint8_t *)(0x42DEEFACUL)) +#define bFM_GPIO_PDSRF_PC *((volatile uint8_t *)(0x42DEEFB0UL)) +#define bFM4_GPIO_PDSRF_PC *((volatile uint8_t *)(0x42DEEFB0UL)) + +#define bFM_GPIO_PFR0_P0 *((volatile uint8_t *)(0x42DE0000UL)) +#define bFM4_GPIO_PFR0_P0 *((volatile uint8_t *)(0x42DE0000UL)) +#define bFM_GPIO_PFR0_P1 *((volatile uint8_t *)(0x42DE0004UL)) +#define bFM4_GPIO_PFR0_P1 *((volatile uint8_t *)(0x42DE0004UL)) +#define bFM_GPIO_PFR0_P2 *((volatile uint8_t *)(0x42DE0008UL)) +#define bFM4_GPIO_PFR0_P2 *((volatile uint8_t *)(0x42DE0008UL)) +#define bFM_GPIO_PFR0_P3 *((volatile uint8_t *)(0x42DE000CUL)) +#define bFM4_GPIO_PFR0_P3 *((volatile uint8_t *)(0x42DE000CUL)) +#define bFM_GPIO_PFR0_P4 *((volatile uint8_t *)(0x42DE0010UL)) +#define bFM4_GPIO_PFR0_P4 *((volatile uint8_t *)(0x42DE0010UL)) +#define bFM_GPIO_PFR0_P8 *((volatile uint8_t *)(0x42DE0020UL)) +#define bFM4_GPIO_PFR0_P8 *((volatile uint8_t *)(0x42DE0020UL)) +#define bFM_GPIO_PFR0_P9 *((volatile uint8_t *)(0x42DE0024UL)) +#define bFM4_GPIO_PFR0_P9 *((volatile uint8_t *)(0x42DE0024UL)) +#define bFM_GPIO_PFR0_PA *((volatile uint8_t *)(0x42DE0028UL)) +#define bFM4_GPIO_PFR0_PA *((volatile uint8_t *)(0x42DE0028UL)) + +#define bFM_GPIO_PFR1_P0 *((volatile uint8_t *)(0x42DE0080UL)) +#define bFM4_GPIO_PFR1_P0 *((volatile uint8_t *)(0x42DE0080UL)) +#define bFM_GPIO_PFR1_P1 *((volatile uint8_t *)(0x42DE0084UL)) +#define bFM4_GPIO_PFR1_P1 *((volatile uint8_t *)(0x42DE0084UL)) +#define bFM_GPIO_PFR1_P2 *((volatile uint8_t *)(0x42DE0088UL)) +#define bFM4_GPIO_PFR1_P2 *((volatile uint8_t *)(0x42DE0088UL)) +#define bFM_GPIO_PFR1_P3 *((volatile uint8_t *)(0x42DE008CUL)) +#define bFM4_GPIO_PFR1_P3 *((volatile uint8_t *)(0x42DE008CUL)) +#define bFM_GPIO_PFR1_P4 *((volatile uint8_t *)(0x42DE0090UL)) +#define bFM4_GPIO_PFR1_P4 *((volatile uint8_t *)(0x42DE0090UL)) +#define bFM_GPIO_PFR1_P5 *((volatile uint8_t *)(0x42DE0094UL)) +#define bFM4_GPIO_PFR1_P5 *((volatile uint8_t *)(0x42DE0094UL)) +#define bFM_GPIO_PFR1_P6 *((volatile uint8_t *)(0x42DE0098UL)) +#define bFM4_GPIO_PFR1_P6 *((volatile uint8_t *)(0x42DE0098UL)) +#define bFM_GPIO_PFR1_P7 *((volatile uint8_t *)(0x42DE009CUL)) +#define bFM4_GPIO_PFR1_P7 *((volatile uint8_t *)(0x42DE009CUL)) +#define bFM_GPIO_PFR1_P8 *((volatile uint8_t *)(0x42DE00A0UL)) +#define bFM4_GPIO_PFR1_P8 *((volatile uint8_t *)(0x42DE00A0UL)) +#define bFM_GPIO_PFR1_P9 *((volatile uint8_t *)(0x42DE00A4UL)) +#define bFM4_GPIO_PFR1_P9 *((volatile uint8_t *)(0x42DE00A4UL)) +#define bFM_GPIO_PFR1_PA *((volatile uint8_t *)(0x42DE00A8UL)) +#define bFM4_GPIO_PFR1_PA *((volatile uint8_t *)(0x42DE00A8UL)) +#define bFM_GPIO_PFR1_PB *((volatile uint8_t *)(0x42DE00ACUL)) +#define bFM4_GPIO_PFR1_PB *((volatile uint8_t *)(0x42DE00ACUL)) +#define bFM_GPIO_PFR1_PC *((volatile uint8_t *)(0x42DE00B0UL)) +#define bFM4_GPIO_PFR1_PC *((volatile uint8_t *)(0x42DE00B0UL)) +#define bFM_GPIO_PFR1_PD *((volatile uint8_t *)(0x42DE00B4UL)) +#define bFM4_GPIO_PFR1_PD *((volatile uint8_t *)(0x42DE00B4UL)) +#define bFM_GPIO_PFR1_PE *((volatile uint8_t *)(0x42DE00B8UL)) +#define bFM4_GPIO_PFR1_PE *((volatile uint8_t *)(0x42DE00B8UL)) +#define bFM_GPIO_PFR1_PF *((volatile uint8_t *)(0x42DE00BCUL)) +#define bFM4_GPIO_PFR1_PF *((volatile uint8_t *)(0x42DE00BCUL)) + +#define bFM_GPIO_PFR2_P0 *((volatile uint8_t *)(0x42DE0100UL)) +#define bFM4_GPIO_PFR2_P0 *((volatile uint8_t *)(0x42DE0100UL)) +#define bFM_GPIO_PFR2_P1 *((volatile uint8_t *)(0x42DE0104UL)) +#define bFM4_GPIO_PFR2_P1 *((volatile uint8_t *)(0x42DE0104UL)) +#define bFM_GPIO_PFR2_P2 *((volatile uint8_t *)(0x42DE0108UL)) +#define bFM4_GPIO_PFR2_P2 *((volatile uint8_t *)(0x42DE0108UL)) +#define bFM_GPIO_PFR2_P3 *((volatile uint8_t *)(0x42DE010CUL)) +#define bFM4_GPIO_PFR2_P3 *((volatile uint8_t *)(0x42DE010CUL)) +#define bFM_GPIO_PFR2_P4 *((volatile uint8_t *)(0x42DE0110UL)) +#define bFM4_GPIO_PFR2_P4 *((volatile uint8_t *)(0x42DE0110UL)) +#define bFM_GPIO_PFR2_P5 *((volatile uint8_t *)(0x42DE0114UL)) +#define bFM4_GPIO_PFR2_P5 *((volatile uint8_t *)(0x42DE0114UL)) +#define bFM_GPIO_PFR2_P6 *((volatile uint8_t *)(0x42DE0118UL)) +#define bFM4_GPIO_PFR2_P6 *((volatile uint8_t *)(0x42DE0118UL)) +#define bFM_GPIO_PFR2_P7 *((volatile uint8_t *)(0x42DE011CUL)) +#define bFM4_GPIO_PFR2_P7 *((volatile uint8_t *)(0x42DE011CUL)) +#define bFM_GPIO_PFR2_P8 *((volatile uint8_t *)(0x42DE0120UL)) +#define bFM4_GPIO_PFR2_P8 *((volatile uint8_t *)(0x42DE0120UL)) +#define bFM_GPIO_PFR2_P9 *((volatile uint8_t *)(0x42DE0124UL)) +#define bFM4_GPIO_PFR2_P9 *((volatile uint8_t *)(0x42DE0124UL)) +#define bFM_GPIO_PFR2_PA *((volatile uint8_t *)(0x42DE0128UL)) +#define bFM4_GPIO_PFR2_PA *((volatile uint8_t *)(0x42DE0128UL)) + +#define bFM_GPIO_PFR3_P0 *((volatile uint8_t *)(0x42DE0180UL)) +#define bFM4_GPIO_PFR3_P0 *((volatile uint8_t *)(0x42DE0180UL)) +#define bFM_GPIO_PFR3_P1 *((volatile uint8_t *)(0x42DE0184UL)) +#define bFM4_GPIO_PFR3_P1 *((volatile uint8_t *)(0x42DE0184UL)) +#define bFM_GPIO_PFR3_P2 *((volatile uint8_t *)(0x42DE0188UL)) +#define bFM4_GPIO_PFR3_P2 *((volatile uint8_t *)(0x42DE0188UL)) +#define bFM_GPIO_PFR3_P3 *((volatile uint8_t *)(0x42DE018CUL)) +#define bFM4_GPIO_PFR3_P3 *((volatile uint8_t *)(0x42DE018CUL)) +#define bFM_GPIO_PFR3_P4 *((volatile uint8_t *)(0x42DE0190UL)) +#define bFM4_GPIO_PFR3_P4 *((volatile uint8_t *)(0x42DE0190UL)) +#define bFM_GPIO_PFR3_P5 *((volatile uint8_t *)(0x42DE0194UL)) +#define bFM4_GPIO_PFR3_P5 *((volatile uint8_t *)(0x42DE0194UL)) +#define bFM_GPIO_PFR3_P6 *((volatile uint8_t *)(0x42DE0198UL)) +#define bFM4_GPIO_PFR3_P6 *((volatile uint8_t *)(0x42DE0198UL)) +#define bFM_GPIO_PFR3_P7 *((volatile uint8_t *)(0x42DE019CUL)) +#define bFM4_GPIO_PFR3_P7 *((volatile uint8_t *)(0x42DE019CUL)) +#define bFM_GPIO_PFR3_P8 *((volatile uint8_t *)(0x42DE01A0UL)) +#define bFM4_GPIO_PFR3_P8 *((volatile uint8_t *)(0x42DE01A0UL)) +#define bFM_GPIO_PFR3_P9 *((volatile uint8_t *)(0x42DE01A4UL)) +#define bFM4_GPIO_PFR3_P9 *((volatile uint8_t *)(0x42DE01A4UL)) +#define bFM_GPIO_PFR3_PA *((volatile uint8_t *)(0x42DE01A8UL)) +#define bFM4_GPIO_PFR3_PA *((volatile uint8_t *)(0x42DE01A8UL)) +#define bFM_GPIO_PFR3_PB *((volatile uint8_t *)(0x42DE01ACUL)) +#define bFM4_GPIO_PFR3_PB *((volatile uint8_t *)(0x42DE01ACUL)) +#define bFM_GPIO_PFR3_PC *((volatile uint8_t *)(0x42DE01B0UL)) +#define bFM4_GPIO_PFR3_PC *((volatile uint8_t *)(0x42DE01B0UL)) +#define bFM_GPIO_PFR3_PD *((volatile uint8_t *)(0x42DE01B4UL)) +#define bFM4_GPIO_PFR3_PD *((volatile uint8_t *)(0x42DE01B4UL)) +#define bFM_GPIO_PFR3_PE *((volatile uint8_t *)(0x42DE01B8UL)) +#define bFM4_GPIO_PFR3_PE *((volatile uint8_t *)(0x42DE01B8UL)) + +#define bFM_GPIO_PFR4_P0 *((volatile uint8_t *)(0x42DE0200UL)) +#define bFM4_GPIO_PFR4_P0 *((volatile uint8_t *)(0x42DE0200UL)) +#define bFM_GPIO_PFR4_P1 *((volatile uint8_t *)(0x42DE0204UL)) +#define bFM4_GPIO_PFR4_P1 *((volatile uint8_t *)(0x42DE0204UL)) +#define bFM_GPIO_PFR4_P2 *((volatile uint8_t *)(0x42DE0208UL)) +#define bFM4_GPIO_PFR4_P2 *((volatile uint8_t *)(0x42DE0208UL)) +#define bFM_GPIO_PFR4_P3 *((volatile uint8_t *)(0x42DE020CUL)) +#define bFM4_GPIO_PFR4_P3 *((volatile uint8_t *)(0x42DE020CUL)) +#define bFM_GPIO_PFR4_P4 *((volatile uint8_t *)(0x42DE0210UL)) +#define bFM4_GPIO_PFR4_P4 *((volatile uint8_t *)(0x42DE0210UL)) +#define bFM_GPIO_PFR4_P5 *((volatile uint8_t *)(0x42DE0214UL)) +#define bFM4_GPIO_PFR4_P5 *((volatile uint8_t *)(0x42DE0214UL)) +#define bFM_GPIO_PFR4_P6 *((volatile uint8_t *)(0x42DE0218UL)) +#define bFM4_GPIO_PFR4_P6 *((volatile uint8_t *)(0x42DE0218UL)) +#define bFM_GPIO_PFR4_P7 *((volatile uint8_t *)(0x42DE021CUL)) +#define bFM4_GPIO_PFR4_P7 *((volatile uint8_t *)(0x42DE021CUL)) +#define bFM_GPIO_PFR4_P8 *((volatile uint8_t *)(0x42DE0220UL)) +#define bFM4_GPIO_PFR4_P8 *((volatile uint8_t *)(0x42DE0220UL)) +#define bFM_GPIO_PFR4_P9 *((volatile uint8_t *)(0x42DE0224UL)) +#define bFM4_GPIO_PFR4_P9 *((volatile uint8_t *)(0x42DE0224UL)) +#define bFM_GPIO_PFR4_PA *((volatile uint8_t *)(0x42DE0228UL)) +#define bFM4_GPIO_PFR4_PA *((volatile uint8_t *)(0x42DE0228UL)) +#define bFM_GPIO_PFR4_PB *((volatile uint8_t *)(0x42DE022CUL)) +#define bFM4_GPIO_PFR4_PB *((volatile uint8_t *)(0x42DE022CUL)) +#define bFM_GPIO_PFR4_PC *((volatile uint8_t *)(0x42DE0230UL)) +#define bFM4_GPIO_PFR4_PC *((volatile uint8_t *)(0x42DE0230UL)) +#define bFM_GPIO_PFR4_PD *((volatile uint8_t *)(0x42DE0234UL)) +#define bFM4_GPIO_PFR4_PD *((volatile uint8_t *)(0x42DE0234UL)) +#define bFM_GPIO_PFR4_PE *((volatile uint8_t *)(0x42DE0238UL)) +#define bFM4_GPIO_PFR4_PE *((volatile uint8_t *)(0x42DE0238UL)) + +#define bFM_GPIO_PFR5_P0 *((volatile uint8_t *)(0x42DE0280UL)) +#define bFM4_GPIO_PFR5_P0 *((volatile uint8_t *)(0x42DE0280UL)) +#define bFM_GPIO_PFR5_P1 *((volatile uint8_t *)(0x42DE0284UL)) +#define bFM4_GPIO_PFR5_P1 *((volatile uint8_t *)(0x42DE0284UL)) +#define bFM_GPIO_PFR5_P2 *((volatile uint8_t *)(0x42DE0288UL)) +#define bFM4_GPIO_PFR5_P2 *((volatile uint8_t *)(0x42DE0288UL)) +#define bFM_GPIO_PFR5_P3 *((volatile uint8_t *)(0x42DE028CUL)) +#define bFM4_GPIO_PFR5_P3 *((volatile uint8_t *)(0x42DE028CUL)) +#define bFM_GPIO_PFR5_P4 *((volatile uint8_t *)(0x42DE0290UL)) +#define bFM4_GPIO_PFR5_P4 *((volatile uint8_t *)(0x42DE0290UL)) +#define bFM_GPIO_PFR5_P5 *((volatile uint8_t *)(0x42DE0294UL)) +#define bFM4_GPIO_PFR5_P5 *((volatile uint8_t *)(0x42DE0294UL)) +#define bFM_GPIO_PFR5_P6 *((volatile uint8_t *)(0x42DE0298UL)) +#define bFM4_GPIO_PFR5_P6 *((volatile uint8_t *)(0x42DE0298UL)) +#define bFM_GPIO_PFR5_P7 *((volatile uint8_t *)(0x42DE029CUL)) +#define bFM4_GPIO_PFR5_P7 *((volatile uint8_t *)(0x42DE029CUL)) +#define bFM_GPIO_PFR5_P8 *((volatile uint8_t *)(0x42DE02A0UL)) +#define bFM4_GPIO_PFR5_P8 *((volatile uint8_t *)(0x42DE02A0UL)) +#define bFM_GPIO_PFR5_P9 *((volatile uint8_t *)(0x42DE02A4UL)) +#define bFM4_GPIO_PFR5_P9 *((volatile uint8_t *)(0x42DE02A4UL)) +#define bFM_GPIO_PFR5_PA *((volatile uint8_t *)(0x42DE02A8UL)) +#define bFM4_GPIO_PFR5_PA *((volatile uint8_t *)(0x42DE02A8UL)) +#define bFM_GPIO_PFR5_PB *((volatile uint8_t *)(0x42DE02ACUL)) +#define bFM4_GPIO_PFR5_PB *((volatile uint8_t *)(0x42DE02ACUL)) +#define bFM_GPIO_PFR5_PC *((volatile uint8_t *)(0x42DE02B0UL)) +#define bFM4_GPIO_PFR5_PC *((volatile uint8_t *)(0x42DE02B0UL)) +#define bFM_GPIO_PFR5_PD *((volatile uint8_t *)(0x42DE02B4UL)) +#define bFM4_GPIO_PFR5_PD *((volatile uint8_t *)(0x42DE02B4UL)) +#define bFM_GPIO_PFR5_PE *((volatile uint8_t *)(0x42DE02B8UL)) +#define bFM4_GPIO_PFR5_PE *((volatile uint8_t *)(0x42DE02B8UL)) +#define bFM_GPIO_PFR5_PF *((volatile uint8_t *)(0x42DE02BCUL)) +#define bFM4_GPIO_PFR5_PF *((volatile uint8_t *)(0x42DE02BCUL)) + +#define bFM_GPIO_PFR6_P0 *((volatile uint8_t *)(0x42DE0300UL)) +#define bFM4_GPIO_PFR6_P0 *((volatile uint8_t *)(0x42DE0300UL)) +#define bFM_GPIO_PFR6_P1 *((volatile uint8_t *)(0x42DE0304UL)) +#define bFM4_GPIO_PFR6_P1 *((volatile uint8_t *)(0x42DE0304UL)) +#define bFM_GPIO_PFR6_P2 *((volatile uint8_t *)(0x42DE0308UL)) +#define bFM4_GPIO_PFR6_P2 *((volatile uint8_t *)(0x42DE0308UL)) +#define bFM_GPIO_PFR6_P3 *((volatile uint8_t *)(0x42DE030CUL)) +#define bFM4_GPIO_PFR6_P3 *((volatile uint8_t *)(0x42DE030CUL)) +#define bFM_GPIO_PFR6_P4 *((volatile uint8_t *)(0x42DE0310UL)) +#define bFM4_GPIO_PFR6_P4 *((volatile uint8_t *)(0x42DE0310UL)) +#define bFM_GPIO_PFR6_P5 *((volatile uint8_t *)(0x42DE0314UL)) +#define bFM4_GPIO_PFR6_P5 *((volatile uint8_t *)(0x42DE0314UL)) +#define bFM_GPIO_PFR6_P6 *((volatile uint8_t *)(0x42DE0318UL)) +#define bFM4_GPIO_PFR6_P6 *((volatile uint8_t *)(0x42DE0318UL)) +#define bFM_GPIO_PFR6_P7 *((volatile uint8_t *)(0x42DE031CUL)) +#define bFM4_GPIO_PFR6_P7 *((volatile uint8_t *)(0x42DE031CUL)) +#define bFM_GPIO_PFR6_P8 *((volatile uint8_t *)(0x42DE0320UL)) +#define bFM4_GPIO_PFR6_P8 *((volatile uint8_t *)(0x42DE0320UL)) +#define bFM_GPIO_PFR6_P9 *((volatile uint8_t *)(0x42DE0324UL)) +#define bFM4_GPIO_PFR6_P9 *((volatile uint8_t *)(0x42DE0324UL)) +#define bFM_GPIO_PFR6_PA *((volatile uint8_t *)(0x42DE0328UL)) +#define bFM4_GPIO_PFR6_PA *((volatile uint8_t *)(0x42DE0328UL)) +#define bFM_GPIO_PFR6_PB *((volatile uint8_t *)(0x42DE032CUL)) +#define bFM4_GPIO_PFR6_PB *((volatile uint8_t *)(0x42DE032CUL)) +#define bFM_GPIO_PFR6_PC *((volatile uint8_t *)(0x42DE0330UL)) +#define bFM4_GPIO_PFR6_PC *((volatile uint8_t *)(0x42DE0330UL)) +#define bFM_GPIO_PFR6_PD *((volatile uint8_t *)(0x42DE0334UL)) +#define bFM4_GPIO_PFR6_PD *((volatile uint8_t *)(0x42DE0334UL)) +#define bFM_GPIO_PFR6_PE *((volatile uint8_t *)(0x42DE0338UL)) +#define bFM4_GPIO_PFR6_PE *((volatile uint8_t *)(0x42DE0338UL)) + +#define bFM_GPIO_PFR7_P0 *((volatile uint8_t *)(0x42DE0380UL)) +#define bFM4_GPIO_PFR7_P0 *((volatile uint8_t *)(0x42DE0380UL)) +#define bFM_GPIO_PFR7_P1 *((volatile uint8_t *)(0x42DE0384UL)) +#define bFM4_GPIO_PFR7_P1 *((volatile uint8_t *)(0x42DE0384UL)) +#define bFM_GPIO_PFR7_P2 *((volatile uint8_t *)(0x42DE0388UL)) +#define bFM4_GPIO_PFR7_P2 *((volatile uint8_t *)(0x42DE0388UL)) +#define bFM_GPIO_PFR7_P3 *((volatile uint8_t *)(0x42DE038CUL)) +#define bFM4_GPIO_PFR7_P3 *((volatile uint8_t *)(0x42DE038CUL)) +#define bFM_GPIO_PFR7_P4 *((volatile uint8_t *)(0x42DE0390UL)) +#define bFM4_GPIO_PFR7_P4 *((volatile uint8_t *)(0x42DE0390UL)) +#define bFM_GPIO_PFR7_P5 *((volatile uint8_t *)(0x42DE0394UL)) +#define bFM4_GPIO_PFR7_P5 *((volatile uint8_t *)(0x42DE0394UL)) +#define bFM_GPIO_PFR7_P6 *((volatile uint8_t *)(0x42DE0398UL)) +#define bFM4_GPIO_PFR7_P6 *((volatile uint8_t *)(0x42DE0398UL)) +#define bFM_GPIO_PFR7_P7 *((volatile uint8_t *)(0x42DE039CUL)) +#define bFM4_GPIO_PFR7_P7 *((volatile uint8_t *)(0x42DE039CUL)) +#define bFM_GPIO_PFR7_P8 *((volatile uint8_t *)(0x42DE03A0UL)) +#define bFM4_GPIO_PFR7_P8 *((volatile uint8_t *)(0x42DE03A0UL)) +#define bFM_GPIO_PFR7_P9 *((volatile uint8_t *)(0x42DE03A4UL)) +#define bFM4_GPIO_PFR7_P9 *((volatile uint8_t *)(0x42DE03A4UL)) +#define bFM_GPIO_PFR7_PA *((volatile uint8_t *)(0x42DE03A8UL)) +#define bFM4_GPIO_PFR7_PA *((volatile uint8_t *)(0x42DE03A8UL)) +#define bFM_GPIO_PFR7_PB *((volatile uint8_t *)(0x42DE03ACUL)) +#define bFM4_GPIO_PFR7_PB *((volatile uint8_t *)(0x42DE03ACUL)) +#define bFM_GPIO_PFR7_PC *((volatile uint8_t *)(0x42DE03B0UL)) +#define bFM4_GPIO_PFR7_PC *((volatile uint8_t *)(0x42DE03B0UL)) +#define bFM_GPIO_PFR7_PD *((volatile uint8_t *)(0x42DE03B4UL)) +#define bFM4_GPIO_PFR7_PD *((volatile uint8_t *)(0x42DE03B4UL)) +#define bFM_GPIO_PFR7_PE *((volatile uint8_t *)(0x42DE03B8UL)) +#define bFM4_GPIO_PFR7_PE *((volatile uint8_t *)(0x42DE03B8UL)) + +#define bFM_GPIO_PFR8_P0 *((volatile uint8_t *)(0x42DE0400UL)) +#define bFM4_GPIO_PFR8_P0 *((volatile uint8_t *)(0x42DE0400UL)) +#define bFM_GPIO_PFR8_P1 *((volatile uint8_t *)(0x42DE0404UL)) +#define bFM4_GPIO_PFR8_P1 *((volatile uint8_t *)(0x42DE0404UL)) +#define bFM_GPIO_PFR8_P2 *((volatile uint8_t *)(0x42DE0408UL)) +#define bFM4_GPIO_PFR8_P2 *((volatile uint8_t *)(0x42DE0408UL)) +#define bFM_GPIO_PFR8_P3 *((volatile uint8_t *)(0x42DE040CUL)) +#define bFM4_GPIO_PFR8_P3 *((volatile uint8_t *)(0x42DE040CUL)) + +#define bFM_GPIO_PFR9_P0 *((volatile uint8_t *)(0x42DE0480UL)) +#define bFM4_GPIO_PFR9_P0 *((volatile uint8_t *)(0x42DE0480UL)) +#define bFM_GPIO_PFR9_P1 *((volatile uint8_t *)(0x42DE0484UL)) +#define bFM4_GPIO_PFR9_P1 *((volatile uint8_t *)(0x42DE0484UL)) +#define bFM_GPIO_PFR9_P2 *((volatile uint8_t *)(0x42DE0488UL)) +#define bFM4_GPIO_PFR9_P2 *((volatile uint8_t *)(0x42DE0488UL)) +#define bFM_GPIO_PFR9_P3 *((volatile uint8_t *)(0x42DE048CUL)) +#define bFM4_GPIO_PFR9_P3 *((volatile uint8_t *)(0x42DE048CUL)) +#define bFM_GPIO_PFR9_P4 *((volatile uint8_t *)(0x42DE0490UL)) +#define bFM4_GPIO_PFR9_P4 *((volatile uint8_t *)(0x42DE0490UL)) +#define bFM_GPIO_PFR9_P5 *((volatile uint8_t *)(0x42DE0494UL)) +#define bFM4_GPIO_PFR9_P5 *((volatile uint8_t *)(0x42DE0494UL)) +#define bFM_GPIO_PFR9_P6 *((volatile uint8_t *)(0x42DE0498UL)) +#define bFM4_GPIO_PFR9_P6 *((volatile uint8_t *)(0x42DE0498UL)) +#define bFM_GPIO_PFR9_P7 *((volatile uint8_t *)(0x42DE049CUL)) +#define bFM4_GPIO_PFR9_P7 *((volatile uint8_t *)(0x42DE049CUL)) + +#define bFM_GPIO_PFRA_P0 *((volatile uint8_t *)(0x42DE0500UL)) +#define bFM4_GPIO_PFRA_P0 *((volatile uint8_t *)(0x42DE0500UL)) +#define bFM_GPIO_PFRA_P1 *((volatile uint8_t *)(0x42DE0504UL)) +#define bFM4_GPIO_PFRA_P1 *((volatile uint8_t *)(0x42DE0504UL)) +#define bFM_GPIO_PFRA_P2 *((volatile uint8_t *)(0x42DE0508UL)) +#define bFM4_GPIO_PFRA_P2 *((volatile uint8_t *)(0x42DE0508UL)) +#define bFM_GPIO_PFRA_P3 *((volatile uint8_t *)(0x42DE050CUL)) +#define bFM4_GPIO_PFRA_P3 *((volatile uint8_t *)(0x42DE050CUL)) +#define bFM_GPIO_PFRA_P4 *((volatile uint8_t *)(0x42DE0510UL)) +#define bFM4_GPIO_PFRA_P4 *((volatile uint8_t *)(0x42DE0510UL)) +#define bFM_GPIO_PFRA_P5 *((volatile uint8_t *)(0x42DE0514UL)) +#define bFM4_GPIO_PFRA_P5 *((volatile uint8_t *)(0x42DE0514UL)) +#define bFM_GPIO_PFRA_P6 *((volatile uint8_t *)(0x42DE0518UL)) +#define bFM4_GPIO_PFRA_P6 *((volatile uint8_t *)(0x42DE0518UL)) +#define bFM_GPIO_PFRA_P7 *((volatile uint8_t *)(0x42DE051CUL)) +#define bFM4_GPIO_PFRA_P7 *((volatile uint8_t *)(0x42DE051CUL)) +#define bFM_GPIO_PFRA_P8 *((volatile uint8_t *)(0x42DE0520UL)) +#define bFM4_GPIO_PFRA_P8 *((volatile uint8_t *)(0x42DE0520UL)) +#define bFM_GPIO_PFRA_P9 *((volatile uint8_t *)(0x42DE0524UL)) +#define bFM4_GPIO_PFRA_P9 *((volatile uint8_t *)(0x42DE0524UL)) +#define bFM_GPIO_PFRA_PA *((volatile uint8_t *)(0x42DE0528UL)) +#define bFM4_GPIO_PFRA_PA *((volatile uint8_t *)(0x42DE0528UL)) +#define bFM_GPIO_PFRA_PB *((volatile uint8_t *)(0x42DE052CUL)) +#define bFM4_GPIO_PFRA_PB *((volatile uint8_t *)(0x42DE052CUL)) +#define bFM_GPIO_PFRA_PC *((volatile uint8_t *)(0x42DE0530UL)) +#define bFM4_GPIO_PFRA_PC *((volatile uint8_t *)(0x42DE0530UL)) +#define bFM_GPIO_PFRA_PD *((volatile uint8_t *)(0x42DE0534UL)) +#define bFM4_GPIO_PFRA_PD *((volatile uint8_t *)(0x42DE0534UL)) +#define bFM_GPIO_PFRA_PE *((volatile uint8_t *)(0x42DE0538UL)) +#define bFM4_GPIO_PFRA_PE *((volatile uint8_t *)(0x42DE0538UL)) +#define bFM_GPIO_PFRA_PF *((volatile uint8_t *)(0x42DE053CUL)) +#define bFM4_GPIO_PFRA_PF *((volatile uint8_t *)(0x42DE053CUL)) + +#define bFM_GPIO_PFRB_P0 *((volatile uint8_t *)(0x42DE0580UL)) +#define bFM4_GPIO_PFRB_P0 *((volatile uint8_t *)(0x42DE0580UL)) +#define bFM_GPIO_PFRB_P1 *((volatile uint8_t *)(0x42DE0584UL)) +#define bFM4_GPIO_PFRB_P1 *((volatile uint8_t *)(0x42DE0584UL)) +#define bFM_GPIO_PFRB_P2 *((volatile uint8_t *)(0x42DE0588UL)) +#define bFM4_GPIO_PFRB_P2 *((volatile uint8_t *)(0x42DE0588UL)) +#define bFM_GPIO_PFRB_P3 *((volatile uint8_t *)(0x42DE058CUL)) +#define bFM4_GPIO_PFRB_P3 *((volatile uint8_t *)(0x42DE058CUL)) +#define bFM_GPIO_PFRB_P4 *((volatile uint8_t *)(0x42DE0590UL)) +#define bFM4_GPIO_PFRB_P4 *((volatile uint8_t *)(0x42DE0590UL)) +#define bFM_GPIO_PFRB_P5 *((volatile uint8_t *)(0x42DE0594UL)) +#define bFM4_GPIO_PFRB_P5 *((volatile uint8_t *)(0x42DE0594UL)) +#define bFM_GPIO_PFRB_P6 *((volatile uint8_t *)(0x42DE0598UL)) +#define bFM4_GPIO_PFRB_P6 *((volatile uint8_t *)(0x42DE0598UL)) +#define bFM_GPIO_PFRB_P7 *((volatile uint8_t *)(0x42DE059CUL)) +#define bFM4_GPIO_PFRB_P7 *((volatile uint8_t *)(0x42DE059CUL)) +#define bFM_GPIO_PFRB_P8 *((volatile uint8_t *)(0x42DE05A0UL)) +#define bFM4_GPIO_PFRB_P8 *((volatile uint8_t *)(0x42DE05A0UL)) +#define bFM_GPIO_PFRB_P9 *((volatile uint8_t *)(0x42DE05A4UL)) +#define bFM4_GPIO_PFRB_P9 *((volatile uint8_t *)(0x42DE05A4UL)) +#define bFM_GPIO_PFRB_PA *((volatile uint8_t *)(0x42DE05A8UL)) +#define bFM4_GPIO_PFRB_PA *((volatile uint8_t *)(0x42DE05A8UL)) +#define bFM_GPIO_PFRB_PB *((volatile uint8_t *)(0x42DE05ACUL)) +#define bFM4_GPIO_PFRB_PB *((volatile uint8_t *)(0x42DE05ACUL)) +#define bFM_GPIO_PFRB_PC *((volatile uint8_t *)(0x42DE05B0UL)) +#define bFM4_GPIO_PFRB_PC *((volatile uint8_t *)(0x42DE05B0UL)) +#define bFM_GPIO_PFRB_PD *((volatile uint8_t *)(0x42DE05B4UL)) +#define bFM4_GPIO_PFRB_PD *((volatile uint8_t *)(0x42DE05B4UL)) +#define bFM_GPIO_PFRB_PE *((volatile uint8_t *)(0x42DE05B8UL)) +#define bFM4_GPIO_PFRB_PE *((volatile uint8_t *)(0x42DE05B8UL)) +#define bFM_GPIO_PFRB_PF *((volatile uint8_t *)(0x42DE05BCUL)) +#define bFM4_GPIO_PFRB_PF *((volatile uint8_t *)(0x42DE05BCUL)) + +#define bFM_GPIO_PFRC_P0 *((volatile uint8_t *)(0x42DE0600UL)) +#define bFM4_GPIO_PFRC_P0 *((volatile uint8_t *)(0x42DE0600UL)) +#define bFM_GPIO_PFRC_P1 *((volatile uint8_t *)(0x42DE0604UL)) +#define bFM4_GPIO_PFRC_P1 *((volatile uint8_t *)(0x42DE0604UL)) +#define bFM_GPIO_PFRC_P2 *((volatile uint8_t *)(0x42DE0608UL)) +#define bFM4_GPIO_PFRC_P2 *((volatile uint8_t *)(0x42DE0608UL)) +#define bFM_GPIO_PFRC_P3 *((volatile uint8_t *)(0x42DE060CUL)) +#define bFM4_GPIO_PFRC_P3 *((volatile uint8_t *)(0x42DE060CUL)) +#define bFM_GPIO_PFRC_P4 *((volatile uint8_t *)(0x42DE0610UL)) +#define bFM4_GPIO_PFRC_P4 *((volatile uint8_t *)(0x42DE0610UL)) +#define bFM_GPIO_PFRC_P5 *((volatile uint8_t *)(0x42DE0614UL)) +#define bFM4_GPIO_PFRC_P5 *((volatile uint8_t *)(0x42DE0614UL)) +#define bFM_GPIO_PFRC_P6 *((volatile uint8_t *)(0x42DE0618UL)) +#define bFM4_GPIO_PFRC_P6 *((volatile uint8_t *)(0x42DE0618UL)) +#define bFM_GPIO_PFRC_P7 *((volatile uint8_t *)(0x42DE061CUL)) +#define bFM4_GPIO_PFRC_P7 *((volatile uint8_t *)(0x42DE061CUL)) +#define bFM_GPIO_PFRC_P8 *((volatile uint8_t *)(0x42DE0620UL)) +#define bFM4_GPIO_PFRC_P8 *((volatile uint8_t *)(0x42DE0620UL)) +#define bFM_GPIO_PFRC_P9 *((volatile uint8_t *)(0x42DE0624UL)) +#define bFM4_GPIO_PFRC_P9 *((volatile uint8_t *)(0x42DE0624UL)) +#define bFM_GPIO_PFRC_PA *((volatile uint8_t *)(0x42DE0628UL)) +#define bFM4_GPIO_PFRC_PA *((volatile uint8_t *)(0x42DE0628UL)) +#define bFM_GPIO_PFRC_PB *((volatile uint8_t *)(0x42DE062CUL)) +#define bFM4_GPIO_PFRC_PB *((volatile uint8_t *)(0x42DE062CUL)) +#define bFM_GPIO_PFRC_PC *((volatile uint8_t *)(0x42DE0630UL)) +#define bFM4_GPIO_PFRC_PC *((volatile uint8_t *)(0x42DE0630UL)) +#define bFM_GPIO_PFRC_PD *((volatile uint8_t *)(0x42DE0634UL)) +#define bFM4_GPIO_PFRC_PD *((volatile uint8_t *)(0x42DE0634UL)) +#define bFM_GPIO_PFRC_PE *((volatile uint8_t *)(0x42DE0638UL)) +#define bFM4_GPIO_PFRC_PE *((volatile uint8_t *)(0x42DE0638UL)) +#define bFM_GPIO_PFRC_PF *((volatile uint8_t *)(0x42DE063CUL)) +#define bFM4_GPIO_PFRC_PF *((volatile uint8_t *)(0x42DE063CUL)) + +#define bFM_GPIO_PFRD_P0 *((volatile uint8_t *)(0x42DE0680UL)) +#define bFM4_GPIO_PFRD_P0 *((volatile uint8_t *)(0x42DE0680UL)) +#define bFM_GPIO_PFRD_P1 *((volatile uint8_t *)(0x42DE0684UL)) +#define bFM4_GPIO_PFRD_P1 *((volatile uint8_t *)(0x42DE0684UL)) +#define bFM_GPIO_PFRD_P2 *((volatile uint8_t *)(0x42DE0688UL)) +#define bFM4_GPIO_PFRD_P2 *((volatile uint8_t *)(0x42DE0688UL)) + +#define bFM_GPIO_PFRE_P0 *((volatile uint8_t *)(0x42DE0700UL)) +#define bFM4_GPIO_PFRE_P0 *((volatile uint8_t *)(0x42DE0700UL)) +#define bFM_GPIO_PFRE_P2 *((volatile uint8_t *)(0x42DE0708UL)) +#define bFM4_GPIO_PFRE_P2 *((volatile uint8_t *)(0x42DE0708UL)) +#define bFM_GPIO_PFRE_P3 *((volatile uint8_t *)(0x42DE070CUL)) +#define bFM4_GPIO_PFRE_P3 *((volatile uint8_t *)(0x42DE070CUL)) + +#define bFM_GPIO_PFRF_P0 *((volatile uint8_t *)(0x42DE0780UL)) +#define bFM4_GPIO_PFRF_P0 *((volatile uint8_t *)(0x42DE0780UL)) +#define bFM_GPIO_PFRF_P1 *((volatile uint8_t *)(0x42DE0784UL)) +#define bFM4_GPIO_PFRF_P1 *((volatile uint8_t *)(0x42DE0784UL)) +#define bFM_GPIO_PFRF_P2 *((volatile uint8_t *)(0x42DE0788UL)) +#define bFM4_GPIO_PFRF_P2 *((volatile uint8_t *)(0x42DE0788UL)) +#define bFM_GPIO_PFRF_P3 *((volatile uint8_t *)(0x42DE078CUL)) +#define bFM4_GPIO_PFRF_P3 *((volatile uint8_t *)(0x42DE078CUL)) +#define bFM_GPIO_PFRF_P4 *((volatile uint8_t *)(0x42DE0790UL)) +#define bFM4_GPIO_PFRF_P4 *((volatile uint8_t *)(0x42DE0790UL)) +#define bFM_GPIO_PFRF_P5 *((volatile uint8_t *)(0x42DE0794UL)) +#define bFM4_GPIO_PFRF_P5 *((volatile uint8_t *)(0x42DE0794UL)) +#define bFM_GPIO_PFRF_P6 *((volatile uint8_t *)(0x42DE0798UL)) +#define bFM4_GPIO_PFRF_P6 *((volatile uint8_t *)(0x42DE0798UL)) +#define bFM_GPIO_PFRF_P7 *((volatile uint8_t *)(0x42DE079CUL)) +#define bFM4_GPIO_PFRF_P7 *((volatile uint8_t *)(0x42DE079CUL)) +#define bFM_GPIO_PFRF_P8 *((volatile uint8_t *)(0x42DE07A0UL)) +#define bFM4_GPIO_PFRF_P8 *((volatile uint8_t *)(0x42DE07A0UL)) +#define bFM_GPIO_PFRF_P9 *((volatile uint8_t *)(0x42DE07A4UL)) +#define bFM4_GPIO_PFRF_P9 *((volatile uint8_t *)(0x42DE07A4UL)) +#define bFM_GPIO_PFRF_PA *((volatile uint8_t *)(0x42DE07A8UL)) +#define bFM4_GPIO_PFRF_PA *((volatile uint8_t *)(0x42DE07A8UL)) +#define bFM_GPIO_PFRF_PB *((volatile uint8_t *)(0x42DE07ACUL)) +#define bFM4_GPIO_PFRF_PB *((volatile uint8_t *)(0x42DE07ACUL)) +#define bFM_GPIO_PFRF_PC *((volatile uint8_t *)(0x42DE07B0UL)) +#define bFM4_GPIO_PFRF_PC *((volatile uint8_t *)(0x42DE07B0UL)) + +#define bFM_GPIO_PZR0_P0 *((volatile uint8_t *)(0x42DEE000UL)) +#define bFM4_GPIO_PZR0_P0 *((volatile uint8_t *)(0x42DEE000UL)) +#define bFM_GPIO_PZR0_P1 *((volatile uint8_t *)(0x42DEE004UL)) +#define bFM4_GPIO_PZR0_P1 *((volatile uint8_t *)(0x42DEE004UL)) +#define bFM_GPIO_PZR0_P2 *((volatile uint8_t *)(0x42DEE008UL)) +#define bFM4_GPIO_PZR0_P2 *((volatile uint8_t *)(0x42DEE008UL)) +#define bFM_GPIO_PZR0_P3 *((volatile uint8_t *)(0x42DEE00CUL)) +#define bFM4_GPIO_PZR0_P3 *((volatile uint8_t *)(0x42DEE00CUL)) +#define bFM_GPIO_PZR0_P4 *((volatile uint8_t *)(0x42DEE010UL)) +#define bFM4_GPIO_PZR0_P4 *((volatile uint8_t *)(0x42DEE010UL)) +#define bFM_GPIO_PZR0_P8 *((volatile uint8_t *)(0x42DEE020UL)) +#define bFM4_GPIO_PZR0_P8 *((volatile uint8_t *)(0x42DEE020UL)) +#define bFM_GPIO_PZR0_P9 *((volatile uint8_t *)(0x42DEE024UL)) +#define bFM4_GPIO_PZR0_P9 *((volatile uint8_t *)(0x42DEE024UL)) +#define bFM_GPIO_PZR0_PA *((volatile uint8_t *)(0x42DEE028UL)) +#define bFM4_GPIO_PZR0_PA *((volatile uint8_t *)(0x42DEE028UL)) + +#define bFM_GPIO_PZR1_P0 *((volatile uint8_t *)(0x42DEE080UL)) +#define bFM4_GPIO_PZR1_P0 *((volatile uint8_t *)(0x42DEE080UL)) +#define bFM_GPIO_PZR1_P1 *((volatile uint8_t *)(0x42DEE084UL)) +#define bFM4_GPIO_PZR1_P1 *((volatile uint8_t *)(0x42DEE084UL)) +#define bFM_GPIO_PZR1_P2 *((volatile uint8_t *)(0x42DEE088UL)) +#define bFM4_GPIO_PZR1_P2 *((volatile uint8_t *)(0x42DEE088UL)) +#define bFM_GPIO_PZR1_P3 *((volatile uint8_t *)(0x42DEE08CUL)) +#define bFM4_GPIO_PZR1_P3 *((volatile uint8_t *)(0x42DEE08CUL)) +#define bFM_GPIO_PZR1_P4 *((volatile uint8_t *)(0x42DEE090UL)) +#define bFM4_GPIO_PZR1_P4 *((volatile uint8_t *)(0x42DEE090UL)) +#define bFM_GPIO_PZR1_P5 *((volatile uint8_t *)(0x42DEE094UL)) +#define bFM4_GPIO_PZR1_P5 *((volatile uint8_t *)(0x42DEE094UL)) +#define bFM_GPIO_PZR1_P6 *((volatile uint8_t *)(0x42DEE098UL)) +#define bFM4_GPIO_PZR1_P6 *((volatile uint8_t *)(0x42DEE098UL)) +#define bFM_GPIO_PZR1_P7 *((volatile uint8_t *)(0x42DEE09CUL)) +#define bFM4_GPIO_PZR1_P7 *((volatile uint8_t *)(0x42DEE09CUL)) +#define bFM_GPIO_PZR1_P8 *((volatile uint8_t *)(0x42DEE0A0UL)) +#define bFM4_GPIO_PZR1_P8 *((volatile uint8_t *)(0x42DEE0A0UL)) +#define bFM_GPIO_PZR1_P9 *((volatile uint8_t *)(0x42DEE0A4UL)) +#define bFM4_GPIO_PZR1_P9 *((volatile uint8_t *)(0x42DEE0A4UL)) +#define bFM_GPIO_PZR1_PA *((volatile uint8_t *)(0x42DEE0A8UL)) +#define bFM4_GPIO_PZR1_PA *((volatile uint8_t *)(0x42DEE0A8UL)) +#define bFM_GPIO_PZR1_PB *((volatile uint8_t *)(0x42DEE0ACUL)) +#define bFM4_GPIO_PZR1_PB *((volatile uint8_t *)(0x42DEE0ACUL)) +#define bFM_GPIO_PZR1_PC *((volatile uint8_t *)(0x42DEE0B0UL)) +#define bFM4_GPIO_PZR1_PC *((volatile uint8_t *)(0x42DEE0B0UL)) +#define bFM_GPIO_PZR1_PD *((volatile uint8_t *)(0x42DEE0B4UL)) +#define bFM4_GPIO_PZR1_PD *((volatile uint8_t *)(0x42DEE0B4UL)) +#define bFM_GPIO_PZR1_PE *((volatile uint8_t *)(0x42DEE0B8UL)) +#define bFM4_GPIO_PZR1_PE *((volatile uint8_t *)(0x42DEE0B8UL)) +#define bFM_GPIO_PZR1_PF *((volatile uint8_t *)(0x42DEE0BCUL)) +#define bFM4_GPIO_PZR1_PF *((volatile uint8_t *)(0x42DEE0BCUL)) + +#define bFM_GPIO_PZR2_P0 *((volatile uint8_t *)(0x42DEE100UL)) +#define bFM4_GPIO_PZR2_P0 *((volatile uint8_t *)(0x42DEE100UL)) +#define bFM_GPIO_PZR2_P1 *((volatile uint8_t *)(0x42DEE104UL)) +#define bFM4_GPIO_PZR2_P1 *((volatile uint8_t *)(0x42DEE104UL)) +#define bFM_GPIO_PZR2_P2 *((volatile uint8_t *)(0x42DEE108UL)) +#define bFM4_GPIO_PZR2_P2 *((volatile uint8_t *)(0x42DEE108UL)) +#define bFM_GPIO_PZR2_P3 *((volatile uint8_t *)(0x42DEE10CUL)) +#define bFM4_GPIO_PZR2_P3 *((volatile uint8_t *)(0x42DEE10CUL)) +#define bFM_GPIO_PZR2_P4 *((volatile uint8_t *)(0x42DEE110UL)) +#define bFM4_GPIO_PZR2_P4 *((volatile uint8_t *)(0x42DEE110UL)) +#define bFM_GPIO_PZR2_P5 *((volatile uint8_t *)(0x42DEE114UL)) +#define bFM4_GPIO_PZR2_P5 *((volatile uint8_t *)(0x42DEE114UL)) +#define bFM_GPIO_PZR2_P6 *((volatile uint8_t *)(0x42DEE118UL)) +#define bFM4_GPIO_PZR2_P6 *((volatile uint8_t *)(0x42DEE118UL)) +#define bFM_GPIO_PZR2_P7 *((volatile uint8_t *)(0x42DEE11CUL)) +#define bFM4_GPIO_PZR2_P7 *((volatile uint8_t *)(0x42DEE11CUL)) +#define bFM_GPIO_PZR2_P8 *((volatile uint8_t *)(0x42DEE120UL)) +#define bFM4_GPIO_PZR2_P8 *((volatile uint8_t *)(0x42DEE120UL)) +#define bFM_GPIO_PZR2_P9 *((volatile uint8_t *)(0x42DEE124UL)) +#define bFM4_GPIO_PZR2_P9 *((volatile uint8_t *)(0x42DEE124UL)) +#define bFM_GPIO_PZR2_PA *((volatile uint8_t *)(0x42DEE128UL)) +#define bFM4_GPIO_PZR2_PA *((volatile uint8_t *)(0x42DEE128UL)) + +#define bFM_GPIO_PZR3_P0 *((volatile uint8_t *)(0x42DEE180UL)) +#define bFM4_GPIO_PZR3_P0 *((volatile uint8_t *)(0x42DEE180UL)) +#define bFM_GPIO_PZR3_P1 *((volatile uint8_t *)(0x42DEE184UL)) +#define bFM4_GPIO_PZR3_P1 *((volatile uint8_t *)(0x42DEE184UL)) +#define bFM_GPIO_PZR3_P2 *((volatile uint8_t *)(0x42DEE188UL)) +#define bFM4_GPIO_PZR3_P2 *((volatile uint8_t *)(0x42DEE188UL)) +#define bFM_GPIO_PZR3_P3 *((volatile uint8_t *)(0x42DEE18CUL)) +#define bFM4_GPIO_PZR3_P3 *((volatile uint8_t *)(0x42DEE18CUL)) +#define bFM_GPIO_PZR3_P4 *((volatile uint8_t *)(0x42DEE190UL)) +#define bFM4_GPIO_PZR3_P4 *((volatile uint8_t *)(0x42DEE190UL)) +#define bFM_GPIO_PZR3_P5 *((volatile uint8_t *)(0x42DEE194UL)) +#define bFM4_GPIO_PZR3_P5 *((volatile uint8_t *)(0x42DEE194UL)) +#define bFM_GPIO_PZR3_P6 *((volatile uint8_t *)(0x42DEE198UL)) +#define bFM4_GPIO_PZR3_P6 *((volatile uint8_t *)(0x42DEE198UL)) +#define bFM_GPIO_PZR3_P7 *((volatile uint8_t *)(0x42DEE19CUL)) +#define bFM4_GPIO_PZR3_P7 *((volatile uint8_t *)(0x42DEE19CUL)) +#define bFM_GPIO_PZR3_P8 *((volatile uint8_t *)(0x42DEE1A0UL)) +#define bFM4_GPIO_PZR3_P8 *((volatile uint8_t *)(0x42DEE1A0UL)) +#define bFM_GPIO_PZR3_P9 *((volatile uint8_t *)(0x42DEE1A4UL)) +#define bFM4_GPIO_PZR3_P9 *((volatile uint8_t *)(0x42DEE1A4UL)) +#define bFM_GPIO_PZR3_PA *((volatile uint8_t *)(0x42DEE1A8UL)) +#define bFM4_GPIO_PZR3_PA *((volatile uint8_t *)(0x42DEE1A8UL)) +#define bFM_GPIO_PZR3_PB *((volatile uint8_t *)(0x42DEE1ACUL)) +#define bFM4_GPIO_PZR3_PB *((volatile uint8_t *)(0x42DEE1ACUL)) +#define bFM_GPIO_PZR3_PC *((volatile uint8_t *)(0x42DEE1B0UL)) +#define bFM4_GPIO_PZR3_PC *((volatile uint8_t *)(0x42DEE1B0UL)) +#define bFM_GPIO_PZR3_PD *((volatile uint8_t *)(0x42DEE1B4UL)) +#define bFM4_GPIO_PZR3_PD *((volatile uint8_t *)(0x42DEE1B4UL)) +#define bFM_GPIO_PZR3_PE *((volatile uint8_t *)(0x42DEE1B8UL)) +#define bFM4_GPIO_PZR3_PE *((volatile uint8_t *)(0x42DEE1B8UL)) + +#define bFM_GPIO_PZR4_P0 *((volatile uint8_t *)(0x42DEE200UL)) +#define bFM4_GPIO_PZR4_P0 *((volatile uint8_t *)(0x42DEE200UL)) +#define bFM_GPIO_PZR4_P1 *((volatile uint8_t *)(0x42DEE204UL)) +#define bFM4_GPIO_PZR4_P1 *((volatile uint8_t *)(0x42DEE204UL)) +#define bFM_GPIO_PZR4_P2 *((volatile uint8_t *)(0x42DEE208UL)) +#define bFM4_GPIO_PZR4_P2 *((volatile uint8_t *)(0x42DEE208UL)) +#define bFM_GPIO_PZR4_P3 *((volatile uint8_t *)(0x42DEE20CUL)) +#define bFM4_GPIO_PZR4_P3 *((volatile uint8_t *)(0x42DEE20CUL)) +#define bFM_GPIO_PZR4_P4 *((volatile uint8_t *)(0x42DEE210UL)) +#define bFM4_GPIO_PZR4_P4 *((volatile uint8_t *)(0x42DEE210UL)) +#define bFM_GPIO_PZR4_P5 *((volatile uint8_t *)(0x42DEE214UL)) +#define bFM4_GPIO_PZR4_P5 *((volatile uint8_t *)(0x42DEE214UL)) +#define bFM_GPIO_PZR4_P6 *((volatile uint8_t *)(0x42DEE218UL)) +#define bFM4_GPIO_PZR4_P6 *((volatile uint8_t *)(0x42DEE218UL)) +#define bFM_GPIO_PZR4_P7 *((volatile uint8_t *)(0x42DEE21CUL)) +#define bFM4_GPIO_PZR4_P7 *((volatile uint8_t *)(0x42DEE21CUL)) +#define bFM_GPIO_PZR4_P8 *((volatile uint8_t *)(0x42DEE220UL)) +#define bFM4_GPIO_PZR4_P8 *((volatile uint8_t *)(0x42DEE220UL)) +#define bFM_GPIO_PZR4_P9 *((volatile uint8_t *)(0x42DEE224UL)) +#define bFM4_GPIO_PZR4_P9 *((volatile uint8_t *)(0x42DEE224UL)) +#define bFM_GPIO_PZR4_PA *((volatile uint8_t *)(0x42DEE228UL)) +#define bFM4_GPIO_PZR4_PA *((volatile uint8_t *)(0x42DEE228UL)) +#define bFM_GPIO_PZR4_PB *((volatile uint8_t *)(0x42DEE22CUL)) +#define bFM4_GPIO_PZR4_PB *((volatile uint8_t *)(0x42DEE22CUL)) +#define bFM_GPIO_PZR4_PC *((volatile uint8_t *)(0x42DEE230UL)) +#define bFM4_GPIO_PZR4_PC *((volatile uint8_t *)(0x42DEE230UL)) +#define bFM_GPIO_PZR4_PD *((volatile uint8_t *)(0x42DEE234UL)) +#define bFM4_GPIO_PZR4_PD *((volatile uint8_t *)(0x42DEE234UL)) +#define bFM_GPIO_PZR4_PE *((volatile uint8_t *)(0x42DEE238UL)) +#define bFM4_GPIO_PZR4_PE *((volatile uint8_t *)(0x42DEE238UL)) + +#define bFM_GPIO_PZR5_P0 *((volatile uint8_t *)(0x42DEE280UL)) +#define bFM4_GPIO_PZR5_P0 *((volatile uint8_t *)(0x42DEE280UL)) +#define bFM_GPIO_PZR5_P1 *((volatile uint8_t *)(0x42DEE284UL)) +#define bFM4_GPIO_PZR5_P1 *((volatile uint8_t *)(0x42DEE284UL)) +#define bFM_GPIO_PZR5_P2 *((volatile uint8_t *)(0x42DEE288UL)) +#define bFM4_GPIO_PZR5_P2 *((volatile uint8_t *)(0x42DEE288UL)) +#define bFM_GPIO_PZR5_P3 *((volatile uint8_t *)(0x42DEE28CUL)) +#define bFM4_GPIO_PZR5_P3 *((volatile uint8_t *)(0x42DEE28CUL)) +#define bFM_GPIO_PZR5_P4 *((volatile uint8_t *)(0x42DEE290UL)) +#define bFM4_GPIO_PZR5_P4 *((volatile uint8_t *)(0x42DEE290UL)) +#define bFM_GPIO_PZR5_P5 *((volatile uint8_t *)(0x42DEE294UL)) +#define bFM4_GPIO_PZR5_P5 *((volatile uint8_t *)(0x42DEE294UL)) +#define bFM_GPIO_PZR5_P6 *((volatile uint8_t *)(0x42DEE298UL)) +#define bFM4_GPIO_PZR5_P6 *((volatile uint8_t *)(0x42DEE298UL)) +#define bFM_GPIO_PZR5_P7 *((volatile uint8_t *)(0x42DEE29CUL)) +#define bFM4_GPIO_PZR5_P7 *((volatile uint8_t *)(0x42DEE29CUL)) +#define bFM_GPIO_PZR5_P8 *((volatile uint8_t *)(0x42DEE2A0UL)) +#define bFM4_GPIO_PZR5_P8 *((volatile uint8_t *)(0x42DEE2A0UL)) +#define bFM_GPIO_PZR5_P9 *((volatile uint8_t *)(0x42DEE2A4UL)) +#define bFM4_GPIO_PZR5_P9 *((volatile uint8_t *)(0x42DEE2A4UL)) +#define bFM_GPIO_PZR5_PA *((volatile uint8_t *)(0x42DEE2A8UL)) +#define bFM4_GPIO_PZR5_PA *((volatile uint8_t *)(0x42DEE2A8UL)) +#define bFM_GPIO_PZR5_PB *((volatile uint8_t *)(0x42DEE2ACUL)) +#define bFM4_GPIO_PZR5_PB *((volatile uint8_t *)(0x42DEE2ACUL)) +#define bFM_GPIO_PZR5_PC *((volatile uint8_t *)(0x42DEE2B0UL)) +#define bFM4_GPIO_PZR5_PC *((volatile uint8_t *)(0x42DEE2B0UL)) +#define bFM_GPIO_PZR5_PD *((volatile uint8_t *)(0x42DEE2B4UL)) +#define bFM4_GPIO_PZR5_PD *((volatile uint8_t *)(0x42DEE2B4UL)) +#define bFM_GPIO_PZR5_PE *((volatile uint8_t *)(0x42DEE2B8UL)) +#define bFM4_GPIO_PZR5_PE *((volatile uint8_t *)(0x42DEE2B8UL)) +#define bFM_GPIO_PZR5_PF *((volatile uint8_t *)(0x42DEE2BCUL)) +#define bFM4_GPIO_PZR5_PF *((volatile uint8_t *)(0x42DEE2BCUL)) + +#define bFM_GPIO_PZR6_P0 *((volatile uint8_t *)(0x42DEE300UL)) +#define bFM4_GPIO_PZR6_P0 *((volatile uint8_t *)(0x42DEE300UL)) +#define bFM_GPIO_PZR6_P1 *((volatile uint8_t *)(0x42DEE304UL)) +#define bFM4_GPIO_PZR6_P1 *((volatile uint8_t *)(0x42DEE304UL)) +#define bFM_GPIO_PZR6_P2 *((volatile uint8_t *)(0x42DEE308UL)) +#define bFM4_GPIO_PZR6_P2 *((volatile uint8_t *)(0x42DEE308UL)) +#define bFM_GPIO_PZR6_P3 *((volatile uint8_t *)(0x42DEE30CUL)) +#define bFM4_GPIO_PZR6_P3 *((volatile uint8_t *)(0x42DEE30CUL)) +#define bFM_GPIO_PZR6_P4 *((volatile uint8_t *)(0x42DEE310UL)) +#define bFM4_GPIO_PZR6_P4 *((volatile uint8_t *)(0x42DEE310UL)) +#define bFM_GPIO_PZR6_P5 *((volatile uint8_t *)(0x42DEE314UL)) +#define bFM4_GPIO_PZR6_P5 *((volatile uint8_t *)(0x42DEE314UL)) +#define bFM_GPIO_PZR6_P6 *((volatile uint8_t *)(0x42DEE318UL)) +#define bFM4_GPIO_PZR6_P6 *((volatile uint8_t *)(0x42DEE318UL)) +#define bFM_GPIO_PZR6_P7 *((volatile uint8_t *)(0x42DEE31CUL)) +#define bFM4_GPIO_PZR6_P7 *((volatile uint8_t *)(0x42DEE31CUL)) +#define bFM_GPIO_PZR6_P8 *((volatile uint8_t *)(0x42DEE320UL)) +#define bFM4_GPIO_PZR6_P8 *((volatile uint8_t *)(0x42DEE320UL)) +#define bFM_GPIO_PZR6_P9 *((volatile uint8_t *)(0x42DEE324UL)) +#define bFM4_GPIO_PZR6_P9 *((volatile uint8_t *)(0x42DEE324UL)) +#define bFM_GPIO_PZR6_PA *((volatile uint8_t *)(0x42DEE328UL)) +#define bFM4_GPIO_PZR6_PA *((volatile uint8_t *)(0x42DEE328UL)) +#define bFM_GPIO_PZR6_PB *((volatile uint8_t *)(0x42DEE32CUL)) +#define bFM4_GPIO_PZR6_PB *((volatile uint8_t *)(0x42DEE32CUL)) +#define bFM_GPIO_PZR6_PC *((volatile uint8_t *)(0x42DEE330UL)) +#define bFM4_GPIO_PZR6_PC *((volatile uint8_t *)(0x42DEE330UL)) +#define bFM_GPIO_PZR6_PD *((volatile uint8_t *)(0x42DEE334UL)) +#define bFM4_GPIO_PZR6_PD *((volatile uint8_t *)(0x42DEE334UL)) +#define bFM_GPIO_PZR6_PE *((volatile uint8_t *)(0x42DEE338UL)) +#define bFM4_GPIO_PZR6_PE *((volatile uint8_t *)(0x42DEE338UL)) + +#define bFM_GPIO_PZR7_P0 *((volatile uint8_t *)(0x42DEE380UL)) +#define bFM4_GPIO_PZR7_P0 *((volatile uint8_t *)(0x42DEE380UL)) +#define bFM_GPIO_PZR7_P1 *((volatile uint8_t *)(0x42DEE384UL)) +#define bFM4_GPIO_PZR7_P1 *((volatile uint8_t *)(0x42DEE384UL)) +#define bFM_GPIO_PZR7_P2 *((volatile uint8_t *)(0x42DEE388UL)) +#define bFM4_GPIO_PZR7_P2 *((volatile uint8_t *)(0x42DEE388UL)) +#define bFM_GPIO_PZR7_P3 *((volatile uint8_t *)(0x42DEE38CUL)) +#define bFM4_GPIO_PZR7_P3 *((volatile uint8_t *)(0x42DEE38CUL)) +#define bFM_GPIO_PZR7_P4 *((volatile uint8_t *)(0x42DEE390UL)) +#define bFM4_GPIO_PZR7_P4 *((volatile uint8_t *)(0x42DEE390UL)) +#define bFM_GPIO_PZR7_P5 *((volatile uint8_t *)(0x42DEE394UL)) +#define bFM4_GPIO_PZR7_P5 *((volatile uint8_t *)(0x42DEE394UL)) +#define bFM_GPIO_PZR7_P6 *((volatile uint8_t *)(0x42DEE398UL)) +#define bFM4_GPIO_PZR7_P6 *((volatile uint8_t *)(0x42DEE398UL)) +#define bFM_GPIO_PZR7_P7 *((volatile uint8_t *)(0x42DEE39CUL)) +#define bFM4_GPIO_PZR7_P7 *((volatile uint8_t *)(0x42DEE39CUL)) +#define bFM_GPIO_PZR7_P8 *((volatile uint8_t *)(0x42DEE3A0UL)) +#define bFM4_GPIO_PZR7_P8 *((volatile uint8_t *)(0x42DEE3A0UL)) +#define bFM_GPIO_PZR7_P9 *((volatile uint8_t *)(0x42DEE3A4UL)) +#define bFM4_GPIO_PZR7_P9 *((volatile uint8_t *)(0x42DEE3A4UL)) +#define bFM_GPIO_PZR7_PA *((volatile uint8_t *)(0x42DEE3A8UL)) +#define bFM4_GPIO_PZR7_PA *((volatile uint8_t *)(0x42DEE3A8UL)) +#define bFM_GPIO_PZR7_PB *((volatile uint8_t *)(0x42DEE3ACUL)) +#define bFM4_GPIO_PZR7_PB *((volatile uint8_t *)(0x42DEE3ACUL)) +#define bFM_GPIO_PZR7_PC *((volatile uint8_t *)(0x42DEE3B0UL)) +#define bFM4_GPIO_PZR7_PC *((volatile uint8_t *)(0x42DEE3B0UL)) +#define bFM_GPIO_PZR7_PD *((volatile uint8_t *)(0x42DEE3B4UL)) +#define bFM4_GPIO_PZR7_PD *((volatile uint8_t *)(0x42DEE3B4UL)) +#define bFM_GPIO_PZR7_PE *((volatile uint8_t *)(0x42DEE3B8UL)) +#define bFM4_GPIO_PZR7_PE *((volatile uint8_t *)(0x42DEE3B8UL)) + +#define bFM_GPIO_PZR8_P0 *((volatile uint8_t *)(0x42DEE400UL)) +#define bFM4_GPIO_PZR8_P0 *((volatile uint8_t *)(0x42DEE400UL)) +#define bFM_GPIO_PZR8_P1 *((volatile uint8_t *)(0x42DEE404UL)) +#define bFM4_GPIO_PZR8_P1 *((volatile uint8_t *)(0x42DEE404UL)) +#define bFM_GPIO_PZR8_P2 *((volatile uint8_t *)(0x42DEE408UL)) +#define bFM4_GPIO_PZR8_P2 *((volatile uint8_t *)(0x42DEE408UL)) +#define bFM_GPIO_PZR8_P3 *((volatile uint8_t *)(0x42DEE40CUL)) +#define bFM4_GPIO_PZR8_P3 *((volatile uint8_t *)(0x42DEE40CUL)) + +#define bFM_GPIO_PZR9_P0 *((volatile uint8_t *)(0x42DEE480UL)) +#define bFM4_GPIO_PZR9_P0 *((volatile uint8_t *)(0x42DEE480UL)) +#define bFM_GPIO_PZR9_P1 *((volatile uint8_t *)(0x42DEE484UL)) +#define bFM4_GPIO_PZR9_P1 *((volatile uint8_t *)(0x42DEE484UL)) +#define bFM_GPIO_PZR9_P2 *((volatile uint8_t *)(0x42DEE488UL)) +#define bFM4_GPIO_PZR9_P2 *((volatile uint8_t *)(0x42DEE488UL)) +#define bFM_GPIO_PZR9_P3 *((volatile uint8_t *)(0x42DEE48CUL)) +#define bFM4_GPIO_PZR9_P3 *((volatile uint8_t *)(0x42DEE48CUL)) +#define bFM_GPIO_PZR9_P4 *((volatile uint8_t *)(0x42DEE490UL)) +#define bFM4_GPIO_PZR9_P4 *((volatile uint8_t *)(0x42DEE490UL)) +#define bFM_GPIO_PZR9_P5 *((volatile uint8_t *)(0x42DEE494UL)) +#define bFM4_GPIO_PZR9_P5 *((volatile uint8_t *)(0x42DEE494UL)) +#define bFM_GPIO_PZR9_P6 *((volatile uint8_t *)(0x42DEE498UL)) +#define bFM4_GPIO_PZR9_P6 *((volatile uint8_t *)(0x42DEE498UL)) +#define bFM_GPIO_PZR9_P7 *((volatile uint8_t *)(0x42DEE49CUL)) +#define bFM4_GPIO_PZR9_P7 *((volatile uint8_t *)(0x42DEE49CUL)) + +#define bFM_GPIO_PZRA_P0 *((volatile uint8_t *)(0x42DEE500UL)) +#define bFM4_GPIO_PZRA_P0 *((volatile uint8_t *)(0x42DEE500UL)) +#define bFM_GPIO_PZRA_P1 *((volatile uint8_t *)(0x42DEE504UL)) +#define bFM4_GPIO_PZRA_P1 *((volatile uint8_t *)(0x42DEE504UL)) +#define bFM_GPIO_PZRA_P2 *((volatile uint8_t *)(0x42DEE508UL)) +#define bFM4_GPIO_PZRA_P2 *((volatile uint8_t *)(0x42DEE508UL)) +#define bFM_GPIO_PZRA_P3 *((volatile uint8_t *)(0x42DEE50CUL)) +#define bFM4_GPIO_PZRA_P3 *((volatile uint8_t *)(0x42DEE50CUL)) +#define bFM_GPIO_PZRA_P4 *((volatile uint8_t *)(0x42DEE510UL)) +#define bFM4_GPIO_PZRA_P4 *((volatile uint8_t *)(0x42DEE510UL)) +#define bFM_GPIO_PZRA_P5 *((volatile uint8_t *)(0x42DEE514UL)) +#define bFM4_GPIO_PZRA_P5 *((volatile uint8_t *)(0x42DEE514UL)) +#define bFM_GPIO_PZRA_P6 *((volatile uint8_t *)(0x42DEE518UL)) +#define bFM4_GPIO_PZRA_P6 *((volatile uint8_t *)(0x42DEE518UL)) +#define bFM_GPIO_PZRA_P7 *((volatile uint8_t *)(0x42DEE51CUL)) +#define bFM4_GPIO_PZRA_P7 *((volatile uint8_t *)(0x42DEE51CUL)) +#define bFM_GPIO_PZRA_P8 *((volatile uint8_t *)(0x42DEE520UL)) +#define bFM4_GPIO_PZRA_P8 *((volatile uint8_t *)(0x42DEE520UL)) +#define bFM_GPIO_PZRA_P9 *((volatile uint8_t *)(0x42DEE524UL)) +#define bFM4_GPIO_PZRA_P9 *((volatile uint8_t *)(0x42DEE524UL)) +#define bFM_GPIO_PZRA_PA *((volatile uint8_t *)(0x42DEE528UL)) +#define bFM4_GPIO_PZRA_PA *((volatile uint8_t *)(0x42DEE528UL)) +#define bFM_GPIO_PZRA_PB *((volatile uint8_t *)(0x42DEE52CUL)) +#define bFM4_GPIO_PZRA_PB *((volatile uint8_t *)(0x42DEE52CUL)) +#define bFM_GPIO_PZRA_PC *((volatile uint8_t *)(0x42DEE530UL)) +#define bFM4_GPIO_PZRA_PC *((volatile uint8_t *)(0x42DEE530UL)) +#define bFM_GPIO_PZRA_PD *((volatile uint8_t *)(0x42DEE534UL)) +#define bFM4_GPIO_PZRA_PD *((volatile uint8_t *)(0x42DEE534UL)) +#define bFM_GPIO_PZRA_PE *((volatile uint8_t *)(0x42DEE538UL)) +#define bFM4_GPIO_PZRA_PE *((volatile uint8_t *)(0x42DEE538UL)) +#define bFM_GPIO_PZRA_PF *((volatile uint8_t *)(0x42DEE53CUL)) +#define bFM4_GPIO_PZRA_PF *((volatile uint8_t *)(0x42DEE53CUL)) + +#define bFM_GPIO_PZRB_P0 *((volatile uint8_t *)(0x42DEE580UL)) +#define bFM4_GPIO_PZRB_P0 *((volatile uint8_t *)(0x42DEE580UL)) +#define bFM_GPIO_PZRB_P1 *((volatile uint8_t *)(0x42DEE584UL)) +#define bFM4_GPIO_PZRB_P1 *((volatile uint8_t *)(0x42DEE584UL)) +#define bFM_GPIO_PZRB_P2 *((volatile uint8_t *)(0x42DEE588UL)) +#define bFM4_GPIO_PZRB_P2 *((volatile uint8_t *)(0x42DEE588UL)) +#define bFM_GPIO_PZRB_P3 *((volatile uint8_t *)(0x42DEE58CUL)) +#define bFM4_GPIO_PZRB_P3 *((volatile uint8_t *)(0x42DEE58CUL)) +#define bFM_GPIO_PZRB_P4 *((volatile uint8_t *)(0x42DEE590UL)) +#define bFM4_GPIO_PZRB_P4 *((volatile uint8_t *)(0x42DEE590UL)) +#define bFM_GPIO_PZRB_P5 *((volatile uint8_t *)(0x42DEE594UL)) +#define bFM4_GPIO_PZRB_P5 *((volatile uint8_t *)(0x42DEE594UL)) +#define bFM_GPIO_PZRB_P6 *((volatile uint8_t *)(0x42DEE598UL)) +#define bFM4_GPIO_PZRB_P6 *((volatile uint8_t *)(0x42DEE598UL)) +#define bFM_GPIO_PZRB_P7 *((volatile uint8_t *)(0x42DEE59CUL)) +#define bFM4_GPIO_PZRB_P7 *((volatile uint8_t *)(0x42DEE59CUL)) +#define bFM_GPIO_PZRB_P8 *((volatile uint8_t *)(0x42DEE5A0UL)) +#define bFM4_GPIO_PZRB_P8 *((volatile uint8_t *)(0x42DEE5A0UL)) +#define bFM_GPIO_PZRB_P9 *((volatile uint8_t *)(0x42DEE5A4UL)) +#define bFM4_GPIO_PZRB_P9 *((volatile uint8_t *)(0x42DEE5A4UL)) +#define bFM_GPIO_PZRB_PA *((volatile uint8_t *)(0x42DEE5A8UL)) +#define bFM4_GPIO_PZRB_PA *((volatile uint8_t *)(0x42DEE5A8UL)) +#define bFM_GPIO_PZRB_PB *((volatile uint8_t *)(0x42DEE5ACUL)) +#define bFM4_GPIO_PZRB_PB *((volatile uint8_t *)(0x42DEE5ACUL)) +#define bFM_GPIO_PZRB_PC *((volatile uint8_t *)(0x42DEE5B0UL)) +#define bFM4_GPIO_PZRB_PC *((volatile uint8_t *)(0x42DEE5B0UL)) +#define bFM_GPIO_PZRB_PD *((volatile uint8_t *)(0x42DEE5B4UL)) +#define bFM4_GPIO_PZRB_PD *((volatile uint8_t *)(0x42DEE5B4UL)) +#define bFM_GPIO_PZRB_PE *((volatile uint8_t *)(0x42DEE5B8UL)) +#define bFM4_GPIO_PZRB_PE *((volatile uint8_t *)(0x42DEE5B8UL)) +#define bFM_GPIO_PZRB_PF *((volatile uint8_t *)(0x42DEE5BCUL)) +#define bFM4_GPIO_PZRB_PF *((volatile uint8_t *)(0x42DEE5BCUL)) + +#define bFM_GPIO_PZRC_P0 *((volatile uint8_t *)(0x42DEE600UL)) +#define bFM4_GPIO_PZRC_P0 *((volatile uint8_t *)(0x42DEE600UL)) +#define bFM_GPIO_PZRC_P1 *((volatile uint8_t *)(0x42DEE604UL)) +#define bFM4_GPIO_PZRC_P1 *((volatile uint8_t *)(0x42DEE604UL)) +#define bFM_GPIO_PZRC_P2 *((volatile uint8_t *)(0x42DEE608UL)) +#define bFM4_GPIO_PZRC_P2 *((volatile uint8_t *)(0x42DEE608UL)) +#define bFM_GPIO_PZRC_P3 *((volatile uint8_t *)(0x42DEE60CUL)) +#define bFM4_GPIO_PZRC_P3 *((volatile uint8_t *)(0x42DEE60CUL)) +#define bFM_GPIO_PZRC_P4 *((volatile uint8_t *)(0x42DEE610UL)) +#define bFM4_GPIO_PZRC_P4 *((volatile uint8_t *)(0x42DEE610UL)) +#define bFM_GPIO_PZRC_P5 *((volatile uint8_t *)(0x42DEE614UL)) +#define bFM4_GPIO_PZRC_P5 *((volatile uint8_t *)(0x42DEE614UL)) +#define bFM_GPIO_PZRC_P6 *((volatile uint8_t *)(0x42DEE618UL)) +#define bFM4_GPIO_PZRC_P6 *((volatile uint8_t *)(0x42DEE618UL)) +#define bFM_GPIO_PZRC_P7 *((volatile uint8_t *)(0x42DEE61CUL)) +#define bFM4_GPIO_PZRC_P7 *((volatile uint8_t *)(0x42DEE61CUL)) +#define bFM_GPIO_PZRC_P8 *((volatile uint8_t *)(0x42DEE620UL)) +#define bFM4_GPIO_PZRC_P8 *((volatile uint8_t *)(0x42DEE620UL)) +#define bFM_GPIO_PZRC_P9 *((volatile uint8_t *)(0x42DEE624UL)) +#define bFM4_GPIO_PZRC_P9 *((volatile uint8_t *)(0x42DEE624UL)) +#define bFM_GPIO_PZRC_PA *((volatile uint8_t *)(0x42DEE628UL)) +#define bFM4_GPIO_PZRC_PA *((volatile uint8_t *)(0x42DEE628UL)) +#define bFM_GPIO_PZRC_PB *((volatile uint8_t *)(0x42DEE62CUL)) +#define bFM4_GPIO_PZRC_PB *((volatile uint8_t *)(0x42DEE62CUL)) +#define bFM_GPIO_PZRC_PC *((volatile uint8_t *)(0x42DEE630UL)) +#define bFM4_GPIO_PZRC_PC *((volatile uint8_t *)(0x42DEE630UL)) +#define bFM_GPIO_PZRC_PD *((volatile uint8_t *)(0x42DEE634UL)) +#define bFM4_GPIO_PZRC_PD *((volatile uint8_t *)(0x42DEE634UL)) +#define bFM_GPIO_PZRC_PE *((volatile uint8_t *)(0x42DEE638UL)) +#define bFM4_GPIO_PZRC_PE *((volatile uint8_t *)(0x42DEE638UL)) +#define bFM_GPIO_PZRC_PF *((volatile uint8_t *)(0x42DEE63CUL)) +#define bFM4_GPIO_PZRC_PF *((volatile uint8_t *)(0x42DEE63CUL)) + +#define bFM_GPIO_PZRD_P0 *((volatile uint8_t *)(0x42DEE680UL)) +#define bFM4_GPIO_PZRD_P0 *((volatile uint8_t *)(0x42DEE680UL)) +#define bFM_GPIO_PZRD_P1 *((volatile uint8_t *)(0x42DEE684UL)) +#define bFM4_GPIO_PZRD_P1 *((volatile uint8_t *)(0x42DEE684UL)) +#define bFM_GPIO_PZRD_P2 *((volatile uint8_t *)(0x42DEE688UL)) +#define bFM4_GPIO_PZRD_P2 *((volatile uint8_t *)(0x42DEE688UL)) + +#define bFM_GPIO_PZRE_P0 *((volatile uint8_t *)(0x42DEE700UL)) +#define bFM4_GPIO_PZRE_P0 *((volatile uint8_t *)(0x42DEE700UL)) +#define bFM_GPIO_PZRE_P2 *((volatile uint8_t *)(0x42DEE708UL)) +#define bFM4_GPIO_PZRE_P2 *((volatile uint8_t *)(0x42DEE708UL)) +#define bFM_GPIO_PZRE_P3 *((volatile uint8_t *)(0x42DEE70CUL)) +#define bFM4_GPIO_PZRE_P3 *((volatile uint8_t *)(0x42DEE70CUL)) + +#define bFM_GPIO_PZRF_P0 *((volatile uint8_t *)(0x42DEE780UL)) +#define bFM4_GPIO_PZRF_P0 *((volatile uint8_t *)(0x42DEE780UL)) +#define bFM_GPIO_PZRF_P1 *((volatile uint8_t *)(0x42DEE784UL)) +#define bFM4_GPIO_PZRF_P1 *((volatile uint8_t *)(0x42DEE784UL)) +#define bFM_GPIO_PZRF_P2 *((volatile uint8_t *)(0x42DEE788UL)) +#define bFM4_GPIO_PZRF_P2 *((volatile uint8_t *)(0x42DEE788UL)) +#define bFM_GPIO_PZRF_P3 *((volatile uint8_t *)(0x42DEE78CUL)) +#define bFM4_GPIO_PZRF_P3 *((volatile uint8_t *)(0x42DEE78CUL)) +#define bFM_GPIO_PZRF_P4 *((volatile uint8_t *)(0x42DEE790UL)) +#define bFM4_GPIO_PZRF_P4 *((volatile uint8_t *)(0x42DEE790UL)) +#define bFM_GPIO_PZRF_P5 *((volatile uint8_t *)(0x42DEE794UL)) +#define bFM4_GPIO_PZRF_P5 *((volatile uint8_t *)(0x42DEE794UL)) +#define bFM_GPIO_PZRF_P6 *((volatile uint8_t *)(0x42DEE798UL)) +#define bFM4_GPIO_PZRF_P6 *((volatile uint8_t *)(0x42DEE798UL)) +#define bFM_GPIO_PZRF_P7 *((volatile uint8_t *)(0x42DEE79CUL)) +#define bFM4_GPIO_PZRF_P7 *((volatile uint8_t *)(0x42DEE79CUL)) +#define bFM_GPIO_PZRF_P8 *((volatile uint8_t *)(0x42DEE7A0UL)) +#define bFM4_GPIO_PZRF_P8 *((volatile uint8_t *)(0x42DEE7A0UL)) +#define bFM_GPIO_PZRF_P9 *((volatile uint8_t *)(0x42DEE7A4UL)) +#define bFM4_GPIO_PZRF_P9 *((volatile uint8_t *)(0x42DEE7A4UL)) +#define bFM_GPIO_PZRF_PA *((volatile uint8_t *)(0x42DEE7A8UL)) +#define bFM4_GPIO_PZRF_PA *((volatile uint8_t *)(0x42DEE7A8UL)) +#define bFM_GPIO_PZRF_PB *((volatile uint8_t *)(0x42DEE7ACUL)) +#define bFM4_GPIO_PZRF_PB *((volatile uint8_t *)(0x42DEE7ACUL)) +#define bFM_GPIO_PZRF_PC *((volatile uint8_t *)(0x42DEE7B0UL)) +#define bFM4_GPIO_PZRF_PC *((volatile uint8_t *)(0x42DEE7B0UL)) + +#define bFM_GPIO_SPSR_USB0C *((volatile uint8_t *)(0x42DEB010UL)) +#define bFM4_GPIO_SPSR_USB0C *((volatile uint8_t *)(0x42DEB010UL)) +#define bFM_GPIO_SPSR_USB1C *((volatile uint8_t *)(0x42DEB014UL)) +#define bFM4_GPIO_SPSR_USB1C *((volatile uint8_t *)(0x42DEB014UL)) + + +/******************************************************************************* +* HSSPI Registers HSSPI +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* HWWDT Registers HWWDT +* Bitband Section +*******************************************************************************/ +#define bFM_HWWDT_WDG_CTL_INTEN *((volatile uint32_t*)(0x42220100UL)) +#define bFM4_HWWDT_WDG_CTL_INTEN *((volatile uint32_t*)(0x42220100UL)) +#define bFM_HWWDT_WDG_CTL_RESEN *((volatile uint32_t*)(0x42220104UL)) +#define bFM4_HWWDT_WDG_CTL_RESEN *((volatile uint32_t*)(0x42220104UL)) + +#define bFM_HWWDT_WDG_RIS_RIS *((volatile uint32_t*)(0x42220200UL)) +#define bFM4_HWWDT_WDG_RIS_RIS *((volatile uint32_t*)(0x42220200UL)) + + +/******************************************************************************* +* I2S Registers I2S0 +* Bitband Section +*******************************************************************************/ +#define bFM_I2S0_CNTREG_FSPL *((volatile uint8_t *)(0x42D80100UL)) +#define bFM4_I2S0_CNTREG_FSPL *((volatile uint8_t *)(0x42D80100UL)) +#define bFM_I2S0_CNTREG_FSLN *((volatile uint8_t *)(0x42D80104UL)) +#define bFM4_I2S0_CNTREG_FSLN *((volatile uint8_t *)(0x42D80104UL)) +#define bFM_I2S0_CNTREG_FSPH *((volatile uint8_t *)(0x42D80108UL)) +#define bFM4_I2S0_CNTREG_FSPH *((volatile uint8_t *)(0x42D80108UL)) +#define bFM_I2S0_CNTREG_CPOL *((volatile uint8_t *)(0x42D8010CUL)) +#define bFM4_I2S0_CNTREG_CPOL *((volatile uint8_t *)(0x42D8010CUL)) +#define bFM_I2S0_CNTREG_SMPL *((volatile uint8_t *)(0x42D80110UL)) +#define bFM4_I2S0_CNTREG_SMPL *((volatile uint8_t *)(0x42D80110UL)) +#define bFM_I2S0_CNTREG_RXDIS *((volatile uint8_t *)(0x42D80114UL)) +#define bFM4_I2S0_CNTREG_RXDIS *((volatile uint8_t *)(0x42D80114UL)) +#define bFM_I2S0_CNTREG_TXDIS *((volatile uint8_t *)(0x42D80118UL)) +#define bFM4_I2S0_CNTREG_TXDIS *((volatile uint8_t *)(0x42D80118UL)) +#define bFM_I2S0_CNTREG_MLSB *((volatile uint8_t *)(0x42D8011CUL)) +#define bFM4_I2S0_CNTREG_MLSB *((volatile uint8_t *)(0x42D8011CUL)) +#define bFM_I2S0_CNTREG_FRUN *((volatile uint8_t *)(0x42D80120UL)) +#define bFM4_I2S0_CNTREG_FRUN *((volatile uint8_t *)(0x42D80120UL)) +#define bFM_I2S0_CNTREG_BEXT *((volatile uint8_t *)(0x42D80124UL)) +#define bFM4_I2S0_CNTREG_BEXT *((volatile uint8_t *)(0x42D80124UL)) +#define bFM_I2S0_CNTREG_ECKM *((volatile uint8_t *)(0x42D80128UL)) +#define bFM4_I2S0_CNTREG_ECKM *((volatile uint8_t *)(0x42D80128UL)) +#define bFM_I2S0_CNTREG_RHLL *((volatile uint8_t *)(0x42D8012CUL)) +#define bFM4_I2S0_CNTREG_RHLL *((volatile uint8_t *)(0x42D8012CUL)) +#define bFM_I2S0_CNTREG_SBFN *((volatile uint8_t *)(0x42D80130UL)) +#define bFM4_I2S0_CNTREG_SBFN *((volatile uint8_t *)(0x42D80130UL)) +#define bFM_I2S0_CNTREG_MSMD *((volatile uint8_t *)(0x42D80134UL)) +#define bFM4_I2S0_CNTREG_MSMD *((volatile uint8_t *)(0x42D80134UL)) +#define bFM_I2S0_CNTREG_MSKB *((volatile uint8_t *)(0x42D80138UL)) +#define bFM4_I2S0_CNTREG_MSKB *((volatile uint8_t *)(0x42D80138UL)) + +#define bFM_I2S0_DMAACT_RDMACT *((volatile uint8_t *)(0x42D80500UL)) +#define bFM4_I2S0_DMAACT_RDMACT *((volatile uint8_t *)(0x42D80500UL)) +#define bFM_I2S0_DMAACT_RL1E0 *((volatile uint8_t *)(0x42D80520UL)) +#define bFM4_I2S0_DMAACT_RL1E0 *((volatile uint8_t *)(0x42D80520UL)) +#define bFM_I2S0_DMAACT_TDMACT *((volatile uint8_t *)(0x42D80540UL)) +#define bFM4_I2S0_DMAACT_TDMACT *((volatile uint8_t *)(0x42D80540UL)) +#define bFM_I2S0_DMAACT_TL1E0 *((volatile uint8_t *)(0x42D80560UL)) +#define bFM4_I2S0_DMAACT_TL1E0 *((volatile uint8_t *)(0x42D80560UL)) + +#define bFM_I2S0_INTCNT_RXFIM *((volatile uint8_t *)(0x42D80440UL)) +#define bFM4_I2S0_INTCNT_RXFIM *((volatile uint8_t *)(0x42D80440UL)) +#define bFM_I2S0_INTCNT_RXFDM *((volatile uint8_t *)(0x42D80444UL)) +#define bFM4_I2S0_INTCNT_RXFDM *((volatile uint8_t *)(0x42D80444UL)) +#define bFM_I2S0_INTCNT_EOPM *((volatile uint8_t *)(0x42D80448UL)) +#define bFM4_I2S0_INTCNT_EOPM *((volatile uint8_t *)(0x42D80448UL)) +#define bFM_I2S0_INTCNT_RXOVM *((volatile uint8_t *)(0x42D8044CUL)) +#define bFM4_I2S0_INTCNT_RXOVM *((volatile uint8_t *)(0x42D8044CUL)) +#define bFM_I2S0_INTCNT_RXUDM *((volatile uint8_t *)(0x42D80450UL)) +#define bFM4_I2S0_INTCNT_RXUDM *((volatile uint8_t *)(0x42D80450UL)) +#define bFM_I2S0_INTCNT_RBERM *((volatile uint8_t *)(0x42D80454UL)) +#define bFM4_I2S0_INTCNT_RBERM *((volatile uint8_t *)(0x42D80454UL)) +#define bFM_I2S0_INTCNT_TXFIM *((volatile uint8_t *)(0x42D80460UL)) +#define bFM4_I2S0_INTCNT_TXFIM *((volatile uint8_t *)(0x42D80460UL)) +#define bFM_I2S0_INTCNT_TXFDM *((volatile uint8_t *)(0x42D80464UL)) +#define bFM4_I2S0_INTCNT_TXFDM *((volatile uint8_t *)(0x42D80464UL)) +#define bFM_I2S0_INTCNT_TXOVM *((volatile uint8_t *)(0x42D80468UL)) +#define bFM4_I2S0_INTCNT_TXOVM *((volatile uint8_t *)(0x42D80468UL)) +#define bFM_I2S0_INTCNT_TXUD0M *((volatile uint8_t *)(0x42D8046CUL)) +#define bFM4_I2S0_INTCNT_TXUD0M *((volatile uint8_t *)(0x42D8046CUL)) +#define bFM_I2S0_INTCNT_FERRM *((volatile uint8_t *)(0x42D80470UL)) +#define bFM4_I2S0_INTCNT_FERRM *((volatile uint8_t *)(0x42D80470UL)) +#define bFM_I2S0_INTCNT_TBERM *((volatile uint8_t *)(0x42D80474UL)) +#define bFM4_I2S0_INTCNT_TBERM *((volatile uint8_t *)(0x42D80474UL)) +#define bFM_I2S0_INTCNT_TXUD1M *((volatile uint8_t *)(0x42D80478UL)) +#define bFM4_I2S0_INTCNT_TXUD1M *((volatile uint8_t *)(0x42D80478UL)) + +#define bFM_I2S0_MCR1REG_S0CH00 *((volatile uint8_t *)(0x42D80200UL)) +#define bFM4_I2S0_MCR1REG_S0CH00 *((volatile uint8_t *)(0x42D80200UL)) +#define bFM_I2S0_MCR1REG_S0CH01 *((volatile uint8_t *)(0x42D80204UL)) +#define bFM4_I2S0_MCR1REG_S0CH01 *((volatile uint8_t *)(0x42D80204UL)) +#define bFM_I2S0_MCR1REG_S0CH02 *((volatile uint8_t *)(0x42D80208UL)) +#define bFM4_I2S0_MCR1REG_S0CH02 *((volatile uint8_t *)(0x42D80208UL)) +#define bFM_I2S0_MCR1REG_S0CH03 *((volatile uint8_t *)(0x42D8020CUL)) +#define bFM4_I2S0_MCR1REG_S0CH03 *((volatile uint8_t *)(0x42D8020CUL)) +#define bFM_I2S0_MCR1REG_S0CH04 *((volatile uint8_t *)(0x42D80210UL)) +#define bFM4_I2S0_MCR1REG_S0CH04 *((volatile uint8_t *)(0x42D80210UL)) +#define bFM_I2S0_MCR1REG_S0CH05 *((volatile uint8_t *)(0x42D80214UL)) +#define bFM4_I2S0_MCR1REG_S0CH05 *((volatile uint8_t *)(0x42D80214UL)) +#define bFM_I2S0_MCR1REG_S0CH06 *((volatile uint8_t *)(0x42D80218UL)) +#define bFM4_I2S0_MCR1REG_S0CH06 *((volatile uint8_t *)(0x42D80218UL)) +#define bFM_I2S0_MCR1REG_S0CH07 *((volatile uint8_t *)(0x42D8021CUL)) +#define bFM4_I2S0_MCR1REG_S0CH07 *((volatile uint8_t *)(0x42D8021CUL)) +#define bFM_I2S0_MCR1REG_S0CH08 *((volatile uint8_t *)(0x42D80220UL)) +#define bFM4_I2S0_MCR1REG_S0CH08 *((volatile uint8_t *)(0x42D80220UL)) +#define bFM_I2S0_MCR1REG_S0CH09 *((volatile uint8_t *)(0x42D80224UL)) +#define bFM4_I2S0_MCR1REG_S0CH09 *((volatile uint8_t *)(0x42D80224UL)) +#define bFM_I2S0_MCR1REG_S0CH10 *((volatile uint8_t *)(0x42D80228UL)) +#define bFM4_I2S0_MCR1REG_S0CH10 *((volatile uint8_t *)(0x42D80228UL)) +#define bFM_I2S0_MCR1REG_S0CH11 *((volatile uint8_t *)(0x42D8022CUL)) +#define bFM4_I2S0_MCR1REG_S0CH11 *((volatile uint8_t *)(0x42D8022CUL)) +#define bFM_I2S0_MCR1REG_S0CH12 *((volatile uint8_t *)(0x42D80230UL)) +#define bFM4_I2S0_MCR1REG_S0CH12 *((volatile uint8_t *)(0x42D80230UL)) +#define bFM_I2S0_MCR1REG_S0CH13 *((volatile uint8_t *)(0x42D80234UL)) +#define bFM4_I2S0_MCR1REG_S0CH13 *((volatile uint8_t *)(0x42D80234UL)) +#define bFM_I2S0_MCR1REG_S0CH14 *((volatile uint8_t *)(0x42D80238UL)) +#define bFM4_I2S0_MCR1REG_S0CH14 *((volatile uint8_t *)(0x42D80238UL)) +#define bFM_I2S0_MCR1REG_S0CH15 *((volatile uint8_t *)(0x42D8023CUL)) +#define bFM4_I2S0_MCR1REG_S0CH15 *((volatile uint8_t *)(0x42D8023CUL)) +#define bFM_I2S0_MCR1REG_S0CH16 *((volatile uint8_t *)(0x42D80240UL)) +#define bFM4_I2S0_MCR1REG_S0CH16 *((volatile uint8_t *)(0x42D80240UL)) +#define bFM_I2S0_MCR1REG_S0CH17 *((volatile uint8_t *)(0x42D80244UL)) +#define bFM4_I2S0_MCR1REG_S0CH17 *((volatile uint8_t *)(0x42D80244UL)) +#define bFM_I2S0_MCR1REG_S0CH18 *((volatile uint8_t *)(0x42D80248UL)) +#define bFM4_I2S0_MCR1REG_S0CH18 *((volatile uint8_t *)(0x42D80248UL)) +#define bFM_I2S0_MCR1REG_S0CH19 *((volatile uint8_t *)(0x42D8024CUL)) +#define bFM4_I2S0_MCR1REG_S0CH19 *((volatile uint8_t *)(0x42D8024CUL)) +#define bFM_I2S0_MCR1REG_S0CH20 *((volatile uint8_t *)(0x42D80250UL)) +#define bFM4_I2S0_MCR1REG_S0CH20 *((volatile uint8_t *)(0x42D80250UL)) +#define bFM_I2S0_MCR1REG_S0CH21 *((volatile uint8_t *)(0x42D80254UL)) +#define bFM4_I2S0_MCR1REG_S0CH21 *((volatile uint8_t *)(0x42D80254UL)) +#define bFM_I2S0_MCR1REG_S0CH22 *((volatile uint8_t *)(0x42D80258UL)) +#define bFM4_I2S0_MCR1REG_S0CH22 *((volatile uint8_t *)(0x42D80258UL)) +#define bFM_I2S0_MCR1REG_S0CH23 *((volatile uint8_t *)(0x42D8025CUL)) +#define bFM4_I2S0_MCR1REG_S0CH23 *((volatile uint8_t *)(0x42D8025CUL)) +#define bFM_I2S0_MCR1REG_S0CH24 *((volatile uint8_t *)(0x42D80260UL)) +#define bFM4_I2S0_MCR1REG_S0CH24 *((volatile uint8_t *)(0x42D80260UL)) +#define bFM_I2S0_MCR1REG_S0CH25 *((volatile uint8_t *)(0x42D80264UL)) +#define bFM4_I2S0_MCR1REG_S0CH25 *((volatile uint8_t *)(0x42D80264UL)) +#define bFM_I2S0_MCR1REG_S0CH26 *((volatile uint8_t *)(0x42D80268UL)) +#define bFM4_I2S0_MCR1REG_S0CH26 *((volatile uint8_t *)(0x42D80268UL)) +#define bFM_I2S0_MCR1REG_S0CH27 *((volatile uint8_t *)(0x42D8026CUL)) +#define bFM4_I2S0_MCR1REG_S0CH27 *((volatile uint8_t *)(0x42D8026CUL)) +#define bFM_I2S0_MCR1REG_S0CH28 *((volatile uint8_t *)(0x42D80270UL)) +#define bFM4_I2S0_MCR1REG_S0CH28 *((volatile uint8_t *)(0x42D80270UL)) +#define bFM_I2S0_MCR1REG_S0CH29 *((volatile uint8_t *)(0x42D80274UL)) +#define bFM4_I2S0_MCR1REG_S0CH29 *((volatile uint8_t *)(0x42D80274UL)) +#define bFM_I2S0_MCR1REG_S0CH30 *((volatile uint8_t *)(0x42D80278UL)) +#define bFM4_I2S0_MCR1REG_S0CH30 *((volatile uint8_t *)(0x42D80278UL)) +#define bFM_I2S0_MCR1REG_S0CH31 *((volatile uint8_t *)(0x42D8027CUL)) +#define bFM4_I2S0_MCR1REG_S0CH31 *((volatile uint8_t *)(0x42D8027CUL)) + +#define bFM_I2S0_MCR2REG_S1CH00 *((volatile uint8_t *)(0x42D80280UL)) +#define bFM4_I2S0_MCR2REG_S1CH00 *((volatile uint8_t *)(0x42D80280UL)) +#define bFM_I2S0_MCR2REG_S1CH01 *((volatile uint8_t *)(0x42D80284UL)) +#define bFM4_I2S0_MCR2REG_S1CH01 *((volatile uint8_t *)(0x42D80284UL)) +#define bFM_I2S0_MCR2REG_S1CH02 *((volatile uint8_t *)(0x42D80288UL)) +#define bFM4_I2S0_MCR2REG_S1CH02 *((volatile uint8_t *)(0x42D80288UL)) +#define bFM_I2S0_MCR2REG_S1CH03 *((volatile uint8_t *)(0x42D8028CUL)) +#define bFM4_I2S0_MCR2REG_S1CH03 *((volatile uint8_t *)(0x42D8028CUL)) +#define bFM_I2S0_MCR2REG_S1CH04 *((volatile uint8_t *)(0x42D80290UL)) +#define bFM4_I2S0_MCR2REG_S1CH04 *((volatile uint8_t *)(0x42D80290UL)) +#define bFM_I2S0_MCR2REG_S1CH05 *((volatile uint8_t *)(0x42D80294UL)) +#define bFM4_I2S0_MCR2REG_S1CH05 *((volatile uint8_t *)(0x42D80294UL)) +#define bFM_I2S0_MCR2REG_S1CH06 *((volatile uint8_t *)(0x42D80298UL)) +#define bFM4_I2S0_MCR2REG_S1CH06 *((volatile uint8_t *)(0x42D80298UL)) +#define bFM_I2S0_MCR2REG_S1CH07 *((volatile uint8_t *)(0x42D8029CUL)) +#define bFM4_I2S0_MCR2REG_S1CH07 *((volatile uint8_t *)(0x42D8029CUL)) +#define bFM_I2S0_MCR2REG_S1CH08 *((volatile uint8_t *)(0x42D802A0UL)) +#define bFM4_I2S0_MCR2REG_S1CH08 *((volatile uint8_t *)(0x42D802A0UL)) +#define bFM_I2S0_MCR2REG_S1CH09 *((volatile uint8_t *)(0x42D802A4UL)) +#define bFM4_I2S0_MCR2REG_S1CH09 *((volatile uint8_t *)(0x42D802A4UL)) +#define bFM_I2S0_MCR2REG_S1CH10 *((volatile uint8_t *)(0x42D802A8UL)) +#define bFM4_I2S0_MCR2REG_S1CH10 *((volatile uint8_t *)(0x42D802A8UL)) +#define bFM_I2S0_MCR2REG_S1CH11 *((volatile uint8_t *)(0x42D802ACUL)) +#define bFM4_I2S0_MCR2REG_S1CH11 *((volatile uint8_t *)(0x42D802ACUL)) +#define bFM_I2S0_MCR2REG_S1CH12 *((volatile uint8_t *)(0x42D802B0UL)) +#define bFM4_I2S0_MCR2REG_S1CH12 *((volatile uint8_t *)(0x42D802B0UL)) +#define bFM_I2S0_MCR2REG_S1CH13 *((volatile uint8_t *)(0x42D802B4UL)) +#define bFM4_I2S0_MCR2REG_S1CH13 *((volatile uint8_t *)(0x42D802B4UL)) +#define bFM_I2S0_MCR2REG_S1CH14 *((volatile uint8_t *)(0x42D802B8UL)) +#define bFM4_I2S0_MCR2REG_S1CH14 *((volatile uint8_t *)(0x42D802B8UL)) +#define bFM_I2S0_MCR2REG_S1CH15 *((volatile uint8_t *)(0x42D802BCUL)) +#define bFM4_I2S0_MCR2REG_S1CH15 *((volatile uint8_t *)(0x42D802BCUL)) +#define bFM_I2S0_MCR2REG_S1CH16 *((volatile uint8_t *)(0x42D802C0UL)) +#define bFM4_I2S0_MCR2REG_S1CH16 *((volatile uint8_t *)(0x42D802C0UL)) +#define bFM_I2S0_MCR2REG_S1CH17 *((volatile uint8_t *)(0x42D802C4UL)) +#define bFM4_I2S0_MCR2REG_S1CH17 *((volatile uint8_t *)(0x42D802C4UL)) +#define bFM_I2S0_MCR2REG_S1CH18 *((volatile uint8_t *)(0x42D802C8UL)) +#define bFM4_I2S0_MCR2REG_S1CH18 *((volatile uint8_t *)(0x42D802C8UL)) +#define bFM_I2S0_MCR2REG_S1CH19 *((volatile uint8_t *)(0x42D802CCUL)) +#define bFM4_I2S0_MCR2REG_S1CH19 *((volatile uint8_t *)(0x42D802CCUL)) +#define bFM_I2S0_MCR2REG_S1CH20 *((volatile uint8_t *)(0x42D802D0UL)) +#define bFM4_I2S0_MCR2REG_S1CH20 *((volatile uint8_t *)(0x42D802D0UL)) +#define bFM_I2S0_MCR2REG_S1CH21 *((volatile uint8_t *)(0x42D802D4UL)) +#define bFM4_I2S0_MCR2REG_S1CH21 *((volatile uint8_t *)(0x42D802D4UL)) +#define bFM_I2S0_MCR2REG_S1CH22 *((volatile uint8_t *)(0x42D802D8UL)) +#define bFM4_I2S0_MCR2REG_S1CH22 *((volatile uint8_t *)(0x42D802D8UL)) +#define bFM_I2S0_MCR2REG_S1CH23 *((volatile uint8_t *)(0x42D802DCUL)) +#define bFM4_I2S0_MCR2REG_S1CH23 *((volatile uint8_t *)(0x42D802DCUL)) +#define bFM_I2S0_MCR2REG_S1CH24 *((volatile uint8_t *)(0x42D802E0UL)) +#define bFM4_I2S0_MCR2REG_S1CH24 *((volatile uint8_t *)(0x42D802E0UL)) +#define bFM_I2S0_MCR2REG_S1CH25 *((volatile uint8_t *)(0x42D802E4UL)) +#define bFM4_I2S0_MCR2REG_S1CH25 *((volatile uint8_t *)(0x42D802E4UL)) +#define bFM_I2S0_MCR2REG_S1CH26 *((volatile uint8_t *)(0x42D802E8UL)) +#define bFM4_I2S0_MCR2REG_S1CH26 *((volatile uint8_t *)(0x42D802E8UL)) +#define bFM_I2S0_MCR2REG_S1CH27 *((volatile uint8_t *)(0x42D802ECUL)) +#define bFM4_I2S0_MCR2REG_S1CH27 *((volatile uint8_t *)(0x42D802ECUL)) +#define bFM_I2S0_MCR2REG_S1CH28 *((volatile uint8_t *)(0x42D802F0UL)) +#define bFM4_I2S0_MCR2REG_S1CH28 *((volatile uint8_t *)(0x42D802F0UL)) +#define bFM_I2S0_MCR2REG_S1CH29 *((volatile uint8_t *)(0x42D802F4UL)) +#define bFM4_I2S0_MCR2REG_S1CH29 *((volatile uint8_t *)(0x42D802F4UL)) +#define bFM_I2S0_MCR2REG_S1CH30 *((volatile uint8_t *)(0x42D802F8UL)) +#define bFM4_I2S0_MCR2REG_S1CH30 *((volatile uint8_t *)(0x42D802F8UL)) +#define bFM_I2S0_MCR2REG_S1CH31 *((volatile uint8_t *)(0x42D802FCUL)) +#define bFM4_I2S0_MCR2REG_S1CH31 *((volatile uint8_t *)(0x42D802FCUL)) + +#define bFM_I2S0_OPRREG_START *((volatile uint8_t *)(0x42D80300UL)) +#define bFM4_I2S0_OPRREG_START *((volatile uint8_t *)(0x42D80300UL)) +#define bFM_I2S0_OPRREG_TXENB *((volatile uint8_t *)(0x42D80340UL)) +#define bFM4_I2S0_OPRREG_TXENB *((volatile uint8_t *)(0x42D80340UL)) +#define bFM_I2S0_OPRREG_RXENB *((volatile uint8_t *)(0x42D80360UL)) +#define bFM4_I2S0_OPRREG_RXENB *((volatile uint8_t *)(0x42D80360UL)) + +#define bFM_I2S0_SRST_SRST *((volatile uint8_t *)(0x42D80380UL)) +#define bFM4_I2S0_SRST_SRST *((volatile uint8_t *)(0x42D80380UL)) + +#define bFM_I2S0_STATUS_RXFI *((volatile uint8_t *)(0x42D804C0UL)) +#define bFM4_I2S0_STATUS_RXFI *((volatile uint8_t *)(0x42D804C0UL)) +#define bFM_I2S0_STATUS_TXFI *((volatile uint8_t *)(0x42D804C4UL)) +#define bFM4_I2S0_STATUS_TXFI *((volatile uint8_t *)(0x42D804C4UL)) +#define bFM_I2S0_STATUS_BSY *((volatile uint8_t *)(0x42D804C8UL)) +#define bFM4_I2S0_STATUS_BSY *((volatile uint8_t *)(0x42D804C8UL)) +#define bFM_I2S0_STATUS_EOPI *((volatile uint8_t *)(0x42D804CCUL)) +#define bFM4_I2S0_STATUS_EOPI *((volatile uint8_t *)(0x42D804CCUL)) +#define bFM_I2S0_STATUS_RXOVR *((volatile uint8_t *)(0x42D804E0UL)) +#define bFM4_I2S0_STATUS_RXOVR *((volatile uint8_t *)(0x42D804E0UL)) +#define bFM_I2S0_STATUS_RXUDR *((volatile uint8_t *)(0x42D804E4UL)) +#define bFM4_I2S0_STATUS_RXUDR *((volatile uint8_t *)(0x42D804E4UL)) +#define bFM_I2S0_STATUS_TXOVR *((volatile uint8_t *)(0x42D804E8UL)) +#define bFM4_I2S0_STATUS_TXOVR *((volatile uint8_t *)(0x42D804E8UL)) +#define bFM_I2S0_STATUS_TXUDR0 *((volatile uint8_t *)(0x42D804ECUL)) +#define bFM4_I2S0_STATUS_TXUDR0 *((volatile uint8_t *)(0x42D804ECUL)) +#define bFM_I2S0_STATUS_TXUDR1 *((volatile uint8_t *)(0x42D804F0UL)) +#define bFM4_I2S0_STATUS_TXUDR1 *((volatile uint8_t *)(0x42D804F0UL)) +#define bFM_I2S0_STATUS_FERR *((volatile uint8_t *)(0x42D804F4UL)) +#define bFM4_I2S0_STATUS_FERR *((volatile uint8_t *)(0x42D804F4UL)) +#define bFM_I2S0_STATUS_RBERR *((volatile uint8_t *)(0x42D804F8UL)) +#define bFM4_I2S0_STATUS_RBERR *((volatile uint8_t *)(0x42D804F8UL)) +#define bFM_I2S0_STATUS_TBERR *((volatile uint8_t *)(0x42D804FCUL)) +#define bFM4_I2S0_STATUS_TBERR *((volatile uint8_t *)(0x42D804FCUL)) + +#define bFM_I2S0_TSTREG_LBMD *((volatile uint8_t *)(0x42D80580UL)) +#define bFM4_I2S0_TSTREG_LBMD *((volatile uint8_t *)(0x42D80580UL)) + + +/******************************************************************************* +* I2SPRE Registers I2SPRE +* Bitband Section +*******************************************************************************/ +#define bFM_I2SPRE_ICCR_I2SEN *((volatile uint8_t *)(0x427A0000UL)) +#define bFM4_I2SPRE_ICCR_I2SEN *((volatile uint8_t *)(0x427A0000UL)) +#define bFM_I2SPRE_ICCR_ICSEL *((volatile uint8_t *)(0x427A0004UL)) +#define bFM4_I2SPRE_ICCR_ICSEL *((volatile uint8_t *)(0x427A0004UL)) + +#define bFM_I2SPRE_IP_STR_IPRDY *((volatile uint8_t *)(0x427A0280UL)) +#define bFM4_I2SPRE_IP_STR_IPRDY *((volatile uint8_t *)(0x427A0280UL)) + +#define bFM_I2SPRE_IPCR1_IPLLEN *((volatile uint8_t *)(0x427A0080UL)) +#define bFM4_I2SPRE_IPCR1_IPLLEN *((volatile uint8_t *)(0x427A0080UL)) + +#define bFM_I2SPRE_IPINT_CLR_IPCSC *((volatile uint8_t *)(0x427A0380UL)) +#define bFM4_I2SPRE_IPINT_CLR_IPCSC *((volatile uint8_t *)(0x427A0380UL)) + +#define bFM_I2SPRE_IPINT_ENR_IPCSE *((volatile uint8_t *)(0x427A0300UL)) +#define bFM4_I2SPRE_IPINT_ENR_IPCSE *((volatile uint8_t *)(0x427A0300UL)) + +#define bFM_I2SPRE_IPINT_STR_IPCSI *((volatile uint8_t *)(0x427A0400UL)) +#define bFM4_I2SPRE_IPINT_STR_IPCSI *((volatile uint8_t *)(0x427A0400UL)) + + +/******************************************************************************* +* INTREQ Registers INTREQ +* Bitband Section +*******************************************************************************/ +#define bFM_INTREQ_DRQSEL_USBEP1 *((volatile uint8_t *)(0x42620000UL)) +#define bFM4_INTREQ_DRQSEL_USBEP1 *((volatile uint8_t *)(0x42620000UL)) +#define bFM_INTREQ_DRQSEL_USBEP2 *((volatile uint8_t *)(0x42620004UL)) +#define bFM4_INTREQ_DRQSEL_USBEP2 *((volatile uint8_t *)(0x42620004UL)) +#define bFM_INTREQ_DRQSEL_USBEP3 *((volatile uint8_t *)(0x42620008UL)) +#define bFM4_INTREQ_DRQSEL_USBEP3 *((volatile uint8_t *)(0x42620008UL)) +#define bFM_INTREQ_DRQSEL_USBEP4 *((volatile uint8_t *)(0x4262000CUL)) +#define bFM4_INTREQ_DRQSEL_USBEP4 *((volatile uint8_t *)(0x4262000CUL)) +#define bFM_INTREQ_DRQSEL_USBEP5 *((volatile uint8_t *)(0x42620010UL)) +#define bFM4_INTREQ_DRQSEL_USBEP5 *((volatile uint8_t *)(0x42620010UL)) +#define bFM_INTREQ_DRQSEL_ADCSCAN0 *((volatile uint8_t *)(0x42620014UL)) +#define bFM4_INTREQ_DRQSEL_ADCSCAN0 *((volatile uint8_t *)(0x42620014UL)) +#define bFM_INTREQ_DRQSEL_ADCSCAN1 *((volatile uint8_t *)(0x42620018UL)) +#define bFM4_INTREQ_DRQSEL_ADCSCAN1 *((volatile uint8_t *)(0x42620018UL)) +#define bFM_INTREQ_DRQSEL_ADCSCAN2 *((volatile uint8_t *)(0x4262001CUL)) +#define bFM4_INTREQ_DRQSEL_ADCSCAN2 *((volatile uint8_t *)(0x4262001CUL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT0 *((volatile uint8_t *)(0x42620020UL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT0 *((volatile uint8_t *)(0x42620020UL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT2 *((volatile uint8_t *)(0x42620024UL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT2 *((volatile uint8_t *)(0x42620024UL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT4 *((volatile uint8_t *)(0x42620028UL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT4 *((volatile uint8_t *)(0x42620028UL)) +#define bFM_INTREQ_DRQSEL_IRQ0BT6 *((volatile uint8_t *)(0x4262002CUL)) +#define bFM4_INTREQ_DRQSEL_IRQ0BT6 *((volatile uint8_t *)(0x4262002CUL)) +#define bFM_INTREQ_DRQSEL_MFS0RX *((volatile uint8_t *)(0x42620030UL)) +#define bFM4_INTREQ_DRQSEL_MFS0RX *((volatile uint8_t *)(0x42620030UL)) +#define bFM_INTREQ_DRQSEL_MFS0TX *((volatile uint8_t *)(0x42620034UL)) +#define bFM4_INTREQ_DRQSEL_MFS0TX *((volatile uint8_t *)(0x42620034UL)) +#define bFM_INTREQ_DRQSEL_MFS1RX *((volatile uint8_t *)(0x42620038UL)) +#define bFM4_INTREQ_DRQSEL_MFS1RX *((volatile uint8_t *)(0x42620038UL)) +#define bFM_INTREQ_DRQSEL_MFS1TX *((volatile uint8_t *)(0x4262003CUL)) +#define bFM4_INTREQ_DRQSEL_MFS1TX *((volatile uint8_t *)(0x4262003CUL)) +#define bFM_INTREQ_DRQSEL_MFS2RX *((volatile uint8_t *)(0x42620040UL)) +#define bFM4_INTREQ_DRQSEL_MFS2RX *((volatile uint8_t *)(0x42620040UL)) +#define bFM_INTREQ_DRQSEL_MFS2TX *((volatile uint8_t *)(0x42620044UL)) +#define bFM4_INTREQ_DRQSEL_MFS2TX *((volatile uint8_t *)(0x42620044UL)) +#define bFM_INTREQ_DRQSEL_MFS3RX *((volatile uint8_t *)(0x42620048UL)) +#define bFM4_INTREQ_DRQSEL_MFS3RX *((volatile uint8_t *)(0x42620048UL)) +#define bFM_INTREQ_DRQSEL_MFS3TX *((volatile uint8_t *)(0x4262004CUL)) +#define bFM4_INTREQ_DRQSEL_MFS3TX *((volatile uint8_t *)(0x4262004CUL)) +#define bFM_INTREQ_DRQSEL_MFS4RX *((volatile uint8_t *)(0x42620050UL)) +#define bFM4_INTREQ_DRQSEL_MFS4RX *((volatile uint8_t *)(0x42620050UL)) +#define bFM_INTREQ_DRQSEL_MFS4TX *((volatile uint8_t *)(0x42620054UL)) +#define bFM4_INTREQ_DRQSEL_MFS4TX *((volatile uint8_t *)(0x42620054UL)) +#define bFM_INTREQ_DRQSEL_MFS5RX *((volatile uint8_t *)(0x42620058UL)) +#define bFM4_INTREQ_DRQSEL_MFS5RX *((volatile uint8_t *)(0x42620058UL)) +#define bFM_INTREQ_DRQSEL_MFS5TX *((volatile uint8_t *)(0x4262005CUL)) +#define bFM4_INTREQ_DRQSEL_MFS5TX *((volatile uint8_t *)(0x4262005CUL)) +#define bFM_INTREQ_DRQSEL_MFS6RX *((volatile uint8_t *)(0x42620060UL)) +#define bFM4_INTREQ_DRQSEL_MFS6RX *((volatile uint8_t *)(0x42620060UL)) +#define bFM_INTREQ_DRQSEL_MFS6TX *((volatile uint8_t *)(0x42620064UL)) +#define bFM4_INTREQ_DRQSEL_MFS6TX *((volatile uint8_t *)(0x42620064UL)) +#define bFM_INTREQ_DRQSEL_MFS7RX *((volatile uint8_t *)(0x42620068UL)) +#define bFM4_INTREQ_DRQSEL_MFS7RX *((volatile uint8_t *)(0x42620068UL)) +#define bFM_INTREQ_DRQSEL_MFS7TX *((volatile uint8_t *)(0x4262006CUL)) +#define bFM4_INTREQ_DRQSEL_MFS7TX *((volatile uint8_t *)(0x4262006CUL)) +#define bFM_INTREQ_DRQSEL_EXINT0 *((volatile uint8_t *)(0x42620070UL)) +#define bFM4_INTREQ_DRQSEL_EXINT0 *((volatile uint8_t *)(0x42620070UL)) +#define bFM_INTREQ_DRQSEL_EXINT1 *((volatile uint8_t *)(0x42620074UL)) +#define bFM4_INTREQ_DRQSEL_EXINT1 *((volatile uint8_t *)(0x42620074UL)) +#define bFM_INTREQ_DRQSEL_EXINT2 *((volatile uint8_t *)(0x42620078UL)) +#define bFM4_INTREQ_DRQSEL_EXINT2 *((volatile uint8_t *)(0x42620078UL)) +#define bFM_INTREQ_DRQSEL_EXINT3 *((volatile uint8_t *)(0x4262007CUL)) +#define bFM4_INTREQ_DRQSEL_EXINT3 *((volatile uint8_t *)(0x4262007CUL)) + +#define bFM_INTREQ_EXC02MON_NMI *((volatile uint8_t *)(0x42624000UL)) +#define bFM4_INTREQ_EXC02MON_NMI *((volatile uint8_t *)(0x42624000UL)) +#define bFM_INTREQ_EXC02MON_HWINT *((volatile uint8_t *)(0x42624004UL)) +#define bFM4_INTREQ_EXC02MON_HWINT *((volatile uint8_t *)(0x42624004UL)) + +#define bFM_INTREQ_IRQ000MON_FCSINT *((volatile uint8_t *)(0x42624080UL)) +#define bFM4_INTREQ_IRQ000MON_FCSINT *((volatile uint8_t *)(0x42624080UL)) + +#define bFM_INTREQ_IRQ001MON_SWWDTINT *((volatile uint8_t *)(0x42624100UL)) +#define bFM4_INTREQ_IRQ001MON_SWWDTINT *((volatile uint8_t *)(0x42624100UL)) + +#define bFM_INTREQ_IRQ002MON_LVDINT *((volatile uint8_t *)(0x42624180UL)) +#define bFM4_INTREQ_IRQ002MON_LVDINT *((volatile uint8_t *)(0x42624180UL)) + +#define bFM_INTREQ_IRQ003MON_IRQBIT0 *((volatile uint8_t *)(0x42624200UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT0 *((volatile uint8_t *)(0x42624200UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT1 *((volatile uint8_t *)(0x42624204UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT1 *((volatile uint8_t *)(0x42624204UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT2 *((volatile uint8_t *)(0x42624208UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT2 *((volatile uint8_t *)(0x42624208UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT3 *((volatile uint8_t *)(0x4262420CUL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT3 *((volatile uint8_t *)(0x4262420CUL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT4 *((volatile uint8_t *)(0x42624210UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT4 *((volatile uint8_t *)(0x42624210UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT5 *((volatile uint8_t *)(0x42624214UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT5 *((volatile uint8_t *)(0x42624214UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT6 *((volatile uint8_t *)(0x42624218UL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT6 *((volatile uint8_t *)(0x42624218UL)) +#define bFM_INTREQ_IRQ003MON_IRQBIT7 *((volatile uint8_t *)(0x4262421CUL)) +#define bFM4_INTREQ_IRQ003MON_IRQBIT7 *((volatile uint8_t *)(0x4262421CUL)) + +#define bFM_INTREQ_IRQ003SEL_SELBIT0 *((volatile uint8_t *)(0x42622240UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT0 *((volatile uint8_t *)(0x42622240UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT1 *((volatile uint8_t *)(0x42622244UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT1 *((volatile uint8_t *)(0x42622244UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT2 *((volatile uint8_t *)(0x42622248UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT2 *((volatile uint8_t *)(0x42622248UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT3 *((volatile uint8_t *)(0x4262224CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT3 *((volatile uint8_t *)(0x4262224CUL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT4 *((volatile uint8_t *)(0x42622250UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT4 *((volatile uint8_t *)(0x42622250UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT5 *((volatile uint8_t *)(0x42622254UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT5 *((volatile uint8_t *)(0x42622254UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT6 *((volatile uint8_t *)(0x42622258UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT6 *((volatile uint8_t *)(0x42622258UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT7 *((volatile uint8_t *)(0x4262225CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT7 *((volatile uint8_t *)(0x4262225CUL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT8 *((volatile uint8_t *)(0x42622260UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT8 *((volatile uint8_t *)(0x42622260UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT9 *((volatile uint8_t *)(0x42622264UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT9 *((volatile uint8_t *)(0x42622264UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT10 *((volatile uint8_t *)(0x42622268UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT10 *((volatile uint8_t *)(0x42622268UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT11 *((volatile uint8_t *)(0x4262226CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT11 *((volatile uint8_t *)(0x4262226CUL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT12 *((volatile uint8_t *)(0x42622270UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT12 *((volatile uint8_t *)(0x42622270UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT13 *((volatile uint8_t *)(0x42622274UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT13 *((volatile uint8_t *)(0x42622274UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT14 *((volatile uint8_t *)(0x42622278UL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT14 *((volatile uint8_t *)(0x42622278UL)) +#define bFM_INTREQ_IRQ003SEL_SELBIT15 *((volatile uint8_t *)(0x4262227CUL)) +#define bFM4_INTREQ_IRQ003SEL_SELBIT15 *((volatile uint8_t *)(0x4262227CUL)) + +#define bFM_INTREQ_IRQ004MON_IRQBIT0 *((volatile uint8_t *)(0x42624280UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT0 *((volatile uint8_t *)(0x42624280UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT1 *((volatile uint8_t *)(0x42624284UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT1 *((volatile uint8_t *)(0x42624284UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT2 *((volatile uint8_t *)(0x42624288UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT2 *((volatile uint8_t *)(0x42624288UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT3 *((volatile uint8_t *)(0x4262428CUL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT3 *((volatile uint8_t *)(0x4262428CUL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT4 *((volatile uint8_t *)(0x42624290UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT4 *((volatile uint8_t *)(0x42624290UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT5 *((volatile uint8_t *)(0x42624294UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT5 *((volatile uint8_t *)(0x42624294UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT6 *((volatile uint8_t *)(0x42624298UL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT6 *((volatile uint8_t *)(0x42624298UL)) +#define bFM_INTREQ_IRQ004MON_IRQBIT7 *((volatile uint8_t *)(0x4262429CUL)) +#define bFM4_INTREQ_IRQ004MON_IRQBIT7 *((volatile uint8_t *)(0x4262429CUL)) + +#define bFM_INTREQ_IRQ004SEL_SELBIT0 *((volatile uint8_t *)(0x426222C0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT0 *((volatile uint8_t *)(0x426222C0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT1 *((volatile uint8_t *)(0x426222C4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT1 *((volatile uint8_t *)(0x426222C4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT2 *((volatile uint8_t *)(0x426222C8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT2 *((volatile uint8_t *)(0x426222C8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT3 *((volatile uint8_t *)(0x426222CCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT3 *((volatile uint8_t *)(0x426222CCUL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT4 *((volatile uint8_t *)(0x426222D0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT4 *((volatile uint8_t *)(0x426222D0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT5 *((volatile uint8_t *)(0x426222D4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT5 *((volatile uint8_t *)(0x426222D4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT6 *((volatile uint8_t *)(0x426222D8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT6 *((volatile uint8_t *)(0x426222D8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT7 *((volatile uint8_t *)(0x426222DCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT7 *((volatile uint8_t *)(0x426222DCUL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT8 *((volatile uint8_t *)(0x426222E0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT8 *((volatile uint8_t *)(0x426222E0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT9 *((volatile uint8_t *)(0x426222E4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT9 *((volatile uint8_t *)(0x426222E4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT10 *((volatile uint8_t *)(0x426222E8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT10 *((volatile uint8_t *)(0x426222E8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT11 *((volatile uint8_t *)(0x426222ECUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT11 *((volatile uint8_t *)(0x426222ECUL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT12 *((volatile uint8_t *)(0x426222F0UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT12 *((volatile uint8_t *)(0x426222F0UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT13 *((volatile uint8_t *)(0x426222F4UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT13 *((volatile uint8_t *)(0x426222F4UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT14 *((volatile uint8_t *)(0x426222F8UL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT14 *((volatile uint8_t *)(0x426222F8UL)) +#define bFM_INTREQ_IRQ004SEL_SELBIT15 *((volatile uint8_t *)(0x426222FCUL)) +#define bFM4_INTREQ_IRQ004SEL_SELBIT15 *((volatile uint8_t *)(0x426222FCUL)) + +#define bFM_INTREQ_IRQ005MON_IRQBIT0 *((volatile uint8_t *)(0x42624300UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT0 *((volatile uint8_t *)(0x42624300UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT1 *((volatile uint8_t *)(0x42624304UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT1 *((volatile uint8_t *)(0x42624304UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT2 *((volatile uint8_t *)(0x42624308UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT2 *((volatile uint8_t *)(0x42624308UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT3 *((volatile uint8_t *)(0x4262430CUL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT3 *((volatile uint8_t *)(0x4262430CUL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT4 *((volatile uint8_t *)(0x42624310UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT4 *((volatile uint8_t *)(0x42624310UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT5 *((volatile uint8_t *)(0x42624314UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT5 *((volatile uint8_t *)(0x42624314UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT6 *((volatile uint8_t *)(0x42624318UL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT6 *((volatile uint8_t *)(0x42624318UL)) +#define bFM_INTREQ_IRQ005MON_IRQBIT7 *((volatile uint8_t *)(0x4262431CUL)) +#define bFM4_INTREQ_IRQ005MON_IRQBIT7 *((volatile uint8_t *)(0x4262431CUL)) + +#define bFM_INTREQ_IRQ005SEL_SELBIT0 *((volatile uint8_t *)(0x42622340UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT0 *((volatile uint8_t *)(0x42622340UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT1 *((volatile uint8_t *)(0x42622344UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT1 *((volatile uint8_t *)(0x42622344UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT2 *((volatile uint8_t *)(0x42622348UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT2 *((volatile uint8_t *)(0x42622348UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT3 *((volatile uint8_t *)(0x4262234CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT3 *((volatile uint8_t *)(0x4262234CUL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT4 *((volatile uint8_t *)(0x42622350UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT4 *((volatile uint8_t *)(0x42622350UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT5 *((volatile uint8_t *)(0x42622354UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT5 *((volatile uint8_t *)(0x42622354UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT6 *((volatile uint8_t *)(0x42622358UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT6 *((volatile uint8_t *)(0x42622358UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT7 *((volatile uint8_t *)(0x4262235CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT7 *((volatile uint8_t *)(0x4262235CUL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT8 *((volatile uint8_t *)(0x42622360UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT8 *((volatile uint8_t *)(0x42622360UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT9 *((volatile uint8_t *)(0x42622364UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT9 *((volatile uint8_t *)(0x42622364UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT10 *((volatile uint8_t *)(0x42622368UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT10 *((volatile uint8_t *)(0x42622368UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT11 *((volatile uint8_t *)(0x4262236CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT11 *((volatile uint8_t *)(0x4262236CUL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT12 *((volatile uint8_t *)(0x42622370UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT12 *((volatile uint8_t *)(0x42622370UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT13 *((volatile uint8_t *)(0x42622374UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT13 *((volatile uint8_t *)(0x42622374UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT14 *((volatile uint8_t *)(0x42622378UL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT14 *((volatile uint8_t *)(0x42622378UL)) +#define bFM_INTREQ_IRQ005SEL_SELBIT15 *((volatile uint8_t *)(0x4262237CUL)) +#define bFM4_INTREQ_IRQ005SEL_SELBIT15 *((volatile uint8_t *)(0x4262237CUL)) + +#define bFM_INTREQ_IRQ006MON_IRQBIT0 *((volatile uint8_t *)(0x42624380UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT0 *((volatile uint8_t *)(0x42624380UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT1 *((volatile uint8_t *)(0x42624384UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT1 *((volatile uint8_t *)(0x42624384UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT2 *((volatile uint8_t *)(0x42624388UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT2 *((volatile uint8_t *)(0x42624388UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT3 *((volatile uint8_t *)(0x4262438CUL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT3 *((volatile uint8_t *)(0x4262438CUL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT4 *((volatile uint8_t *)(0x42624390UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT4 *((volatile uint8_t *)(0x42624390UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT5 *((volatile uint8_t *)(0x42624394UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT5 *((volatile uint8_t *)(0x42624394UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT6 *((volatile uint8_t *)(0x42624398UL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT6 *((volatile uint8_t *)(0x42624398UL)) +#define bFM_INTREQ_IRQ006MON_IRQBIT7 *((volatile uint8_t *)(0x4262439CUL)) +#define bFM4_INTREQ_IRQ006MON_IRQBIT7 *((volatile uint8_t *)(0x4262439CUL)) + +#define bFM_INTREQ_IRQ006SEL_SELBIT0 *((volatile uint8_t *)(0x426223C0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT0 *((volatile uint8_t *)(0x426223C0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT1 *((volatile uint8_t *)(0x426223C4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT1 *((volatile uint8_t *)(0x426223C4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT2 *((volatile uint8_t *)(0x426223C8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT2 *((volatile uint8_t *)(0x426223C8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT3 *((volatile uint8_t *)(0x426223CCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT3 *((volatile uint8_t *)(0x426223CCUL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT4 *((volatile uint8_t *)(0x426223D0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT4 *((volatile uint8_t *)(0x426223D0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT5 *((volatile uint8_t *)(0x426223D4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT5 *((volatile uint8_t *)(0x426223D4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT6 *((volatile uint8_t *)(0x426223D8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT6 *((volatile uint8_t *)(0x426223D8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT7 *((volatile uint8_t *)(0x426223DCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT7 *((volatile uint8_t *)(0x426223DCUL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT8 *((volatile uint8_t *)(0x426223E0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT8 *((volatile uint8_t *)(0x426223E0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT9 *((volatile uint8_t *)(0x426223E4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT9 *((volatile uint8_t *)(0x426223E4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT10 *((volatile uint8_t *)(0x426223E8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT10 *((volatile uint8_t *)(0x426223E8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT11 *((volatile uint8_t *)(0x426223ECUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT11 *((volatile uint8_t *)(0x426223ECUL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT12 *((volatile uint8_t *)(0x426223F0UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT12 *((volatile uint8_t *)(0x426223F0UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT13 *((volatile uint8_t *)(0x426223F4UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT13 *((volatile uint8_t *)(0x426223F4UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT14 *((volatile uint8_t *)(0x426223F8UL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT14 *((volatile uint8_t *)(0x426223F8UL)) +#define bFM_INTREQ_IRQ006SEL_SELBIT15 *((volatile uint8_t *)(0x426223FCUL)) +#define bFM4_INTREQ_IRQ006SEL_SELBIT15 *((volatile uint8_t *)(0x426223FCUL)) + +#define bFM_INTREQ_IRQ007MON_IRQBIT0 *((volatile uint8_t *)(0x42624400UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT0 *((volatile uint8_t *)(0x42624400UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT1 *((volatile uint8_t *)(0x42624404UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT1 *((volatile uint8_t *)(0x42624404UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT2 *((volatile uint8_t *)(0x42624408UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT2 *((volatile uint8_t *)(0x42624408UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT3 *((volatile uint8_t *)(0x4262440CUL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT3 *((volatile uint8_t *)(0x4262440CUL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT4 *((volatile uint8_t *)(0x42624410UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT4 *((volatile uint8_t *)(0x42624410UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT5 *((volatile uint8_t *)(0x42624414UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT5 *((volatile uint8_t *)(0x42624414UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT6 *((volatile uint8_t *)(0x42624418UL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT6 *((volatile uint8_t *)(0x42624418UL)) +#define bFM_INTREQ_IRQ007MON_IRQBIT7 *((volatile uint8_t *)(0x4262441CUL)) +#define bFM4_INTREQ_IRQ007MON_IRQBIT7 *((volatile uint8_t *)(0x4262441CUL)) + +#define bFM_INTREQ_IRQ007SEL_SELBIT0 *((volatile uint8_t *)(0x42622440UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT0 *((volatile uint8_t *)(0x42622440UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT1 *((volatile uint8_t *)(0x42622444UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT1 *((volatile uint8_t *)(0x42622444UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT2 *((volatile uint8_t *)(0x42622448UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT2 *((volatile uint8_t *)(0x42622448UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT3 *((volatile uint8_t *)(0x4262244CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT3 *((volatile uint8_t *)(0x4262244CUL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT4 *((volatile uint8_t *)(0x42622450UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT4 *((volatile uint8_t *)(0x42622450UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT5 *((volatile uint8_t *)(0x42622454UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT5 *((volatile uint8_t *)(0x42622454UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT6 *((volatile uint8_t *)(0x42622458UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT6 *((volatile uint8_t *)(0x42622458UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT7 *((volatile uint8_t *)(0x4262245CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT7 *((volatile uint8_t *)(0x4262245CUL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT8 *((volatile uint8_t *)(0x42622460UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT8 *((volatile uint8_t *)(0x42622460UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT9 *((volatile uint8_t *)(0x42622464UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT9 *((volatile uint8_t *)(0x42622464UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT10 *((volatile uint8_t *)(0x42622468UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT10 *((volatile uint8_t *)(0x42622468UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT11 *((volatile uint8_t *)(0x4262246CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT11 *((volatile uint8_t *)(0x4262246CUL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT12 *((volatile uint8_t *)(0x42622470UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT12 *((volatile uint8_t *)(0x42622470UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT13 *((volatile uint8_t *)(0x42622474UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT13 *((volatile uint8_t *)(0x42622474UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT14 *((volatile uint8_t *)(0x42622478UL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT14 *((volatile uint8_t *)(0x42622478UL)) +#define bFM_INTREQ_IRQ007SEL_SELBIT15 *((volatile uint8_t *)(0x4262247CUL)) +#define bFM4_INTREQ_IRQ007SEL_SELBIT15 *((volatile uint8_t *)(0x4262247CUL)) + +#define bFM_INTREQ_IRQ008MON_IRQBIT0 *((volatile uint8_t *)(0x42624480UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT0 *((volatile uint8_t *)(0x42624480UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT1 *((volatile uint8_t *)(0x42624484UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT1 *((volatile uint8_t *)(0x42624484UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT2 *((volatile uint8_t *)(0x42624488UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT2 *((volatile uint8_t *)(0x42624488UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT3 *((volatile uint8_t *)(0x4262448CUL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT3 *((volatile uint8_t *)(0x4262448CUL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT4 *((volatile uint8_t *)(0x42624490UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT4 *((volatile uint8_t *)(0x42624490UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT5 *((volatile uint8_t *)(0x42624494UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT5 *((volatile uint8_t *)(0x42624494UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT6 *((volatile uint8_t *)(0x42624498UL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT6 *((volatile uint8_t *)(0x42624498UL)) +#define bFM_INTREQ_IRQ008MON_IRQBIT7 *((volatile uint8_t *)(0x4262449CUL)) +#define bFM4_INTREQ_IRQ008MON_IRQBIT7 *((volatile uint8_t *)(0x4262449CUL)) + +#define bFM_INTREQ_IRQ008SEL_SELBIT0 *((volatile uint8_t *)(0x426224C0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT0 *((volatile uint8_t *)(0x426224C0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT1 *((volatile uint8_t *)(0x426224C4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT1 *((volatile uint8_t *)(0x426224C4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT2 *((volatile uint8_t *)(0x426224C8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT2 *((volatile uint8_t *)(0x426224C8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT3 *((volatile uint8_t *)(0x426224CCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT3 *((volatile uint8_t *)(0x426224CCUL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT4 *((volatile uint8_t *)(0x426224D0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT4 *((volatile uint8_t *)(0x426224D0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT5 *((volatile uint8_t *)(0x426224D4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT5 *((volatile uint8_t *)(0x426224D4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT6 *((volatile uint8_t *)(0x426224D8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT6 *((volatile uint8_t *)(0x426224D8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT7 *((volatile uint8_t *)(0x426224DCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT7 *((volatile uint8_t *)(0x426224DCUL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT8 *((volatile uint8_t *)(0x426224E0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT8 *((volatile uint8_t *)(0x426224E0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT9 *((volatile uint8_t *)(0x426224E4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT9 *((volatile uint8_t *)(0x426224E4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT10 *((volatile uint8_t *)(0x426224E8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT10 *((volatile uint8_t *)(0x426224E8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT11 *((volatile uint8_t *)(0x426224ECUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT11 *((volatile uint8_t *)(0x426224ECUL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT12 *((volatile uint8_t *)(0x426224F0UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT12 *((volatile uint8_t *)(0x426224F0UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT13 *((volatile uint8_t *)(0x426224F4UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT13 *((volatile uint8_t *)(0x426224F4UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT14 *((volatile uint8_t *)(0x426224F8UL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT14 *((volatile uint8_t *)(0x426224F8UL)) +#define bFM_INTREQ_IRQ008SEL_SELBIT15 *((volatile uint8_t *)(0x426224FCUL)) +#define bFM4_INTREQ_IRQ008SEL_SELBIT15 *((volatile uint8_t *)(0x426224FCUL)) + +#define bFM_INTREQ_IRQ009MON_IRQBIT0 *((volatile uint8_t *)(0x42624500UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT0 *((volatile uint8_t *)(0x42624500UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT1 *((volatile uint8_t *)(0x42624504UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT1 *((volatile uint8_t *)(0x42624504UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT2 *((volatile uint8_t *)(0x42624508UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT2 *((volatile uint8_t *)(0x42624508UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT3 *((volatile uint8_t *)(0x4262450CUL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT3 *((volatile uint8_t *)(0x4262450CUL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT4 *((volatile uint8_t *)(0x42624510UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT4 *((volatile uint8_t *)(0x42624510UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT5 *((volatile uint8_t *)(0x42624514UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT5 *((volatile uint8_t *)(0x42624514UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT6 *((volatile uint8_t *)(0x42624518UL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT6 *((volatile uint8_t *)(0x42624518UL)) +#define bFM_INTREQ_IRQ009MON_IRQBIT7 *((volatile uint8_t *)(0x4262451CUL)) +#define bFM4_INTREQ_IRQ009MON_IRQBIT7 *((volatile uint8_t *)(0x4262451CUL)) + +#define bFM_INTREQ_IRQ009SEL_SELBIT0 *((volatile uint8_t *)(0x42622540UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT0 *((volatile uint8_t *)(0x42622540UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT1 *((volatile uint8_t *)(0x42622544UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT1 *((volatile uint8_t *)(0x42622544UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT2 *((volatile uint8_t *)(0x42622548UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT2 *((volatile uint8_t *)(0x42622548UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT3 *((volatile uint8_t *)(0x4262254CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT3 *((volatile uint8_t *)(0x4262254CUL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT4 *((volatile uint8_t *)(0x42622550UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT4 *((volatile uint8_t *)(0x42622550UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT5 *((volatile uint8_t *)(0x42622554UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT5 *((volatile uint8_t *)(0x42622554UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT6 *((volatile uint8_t *)(0x42622558UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT6 *((volatile uint8_t *)(0x42622558UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT7 *((volatile uint8_t *)(0x4262255CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT7 *((volatile uint8_t *)(0x4262255CUL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT8 *((volatile uint8_t *)(0x42622560UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT8 *((volatile uint8_t *)(0x42622560UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT9 *((volatile uint8_t *)(0x42622564UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT9 *((volatile uint8_t *)(0x42622564UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT10 *((volatile uint8_t *)(0x42622568UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT10 *((volatile uint8_t *)(0x42622568UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT11 *((volatile uint8_t *)(0x4262256CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT11 *((volatile uint8_t *)(0x4262256CUL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT12 *((volatile uint8_t *)(0x42622570UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT12 *((volatile uint8_t *)(0x42622570UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT13 *((volatile uint8_t *)(0x42622574UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT13 *((volatile uint8_t *)(0x42622574UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT14 *((volatile uint8_t *)(0x42622578UL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT14 *((volatile uint8_t *)(0x42622578UL)) +#define bFM_INTREQ_IRQ009SEL_SELBIT15 *((volatile uint8_t *)(0x4262257CUL)) +#define bFM4_INTREQ_IRQ009SEL_SELBIT15 *((volatile uint8_t *)(0x4262257CUL)) + +#define bFM_INTREQ_IRQ010MON_IRQBIT0 *((volatile uint8_t *)(0x42624580UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT0 *((volatile uint8_t *)(0x42624580UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT1 *((volatile uint8_t *)(0x42624584UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT1 *((volatile uint8_t *)(0x42624584UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT2 *((volatile uint8_t *)(0x42624588UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT2 *((volatile uint8_t *)(0x42624588UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT3 *((volatile uint8_t *)(0x4262458CUL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT3 *((volatile uint8_t *)(0x4262458CUL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT4 *((volatile uint8_t *)(0x42624590UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT4 *((volatile uint8_t *)(0x42624590UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT5 *((volatile uint8_t *)(0x42624594UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT5 *((volatile uint8_t *)(0x42624594UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT6 *((volatile uint8_t *)(0x42624598UL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT6 *((volatile uint8_t *)(0x42624598UL)) +#define bFM_INTREQ_IRQ010MON_IRQBIT7 *((volatile uint8_t *)(0x4262459CUL)) +#define bFM4_INTREQ_IRQ010MON_IRQBIT7 *((volatile uint8_t *)(0x4262459CUL)) + +#define bFM_INTREQ_IRQ010SEL_SELBIT0 *((volatile uint8_t *)(0x426225C0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT0 *((volatile uint8_t *)(0x426225C0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT1 *((volatile uint8_t *)(0x426225C4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT1 *((volatile uint8_t *)(0x426225C4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT2 *((volatile uint8_t *)(0x426225C8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT2 *((volatile uint8_t *)(0x426225C8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT3 *((volatile uint8_t *)(0x426225CCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT3 *((volatile uint8_t *)(0x426225CCUL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT4 *((volatile uint8_t *)(0x426225D0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT4 *((volatile uint8_t *)(0x426225D0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT5 *((volatile uint8_t *)(0x426225D4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT5 *((volatile uint8_t *)(0x426225D4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT6 *((volatile uint8_t *)(0x426225D8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT6 *((volatile uint8_t *)(0x426225D8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT7 *((volatile uint8_t *)(0x426225DCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT7 *((volatile uint8_t *)(0x426225DCUL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT8 *((volatile uint8_t *)(0x426225E0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT8 *((volatile uint8_t *)(0x426225E0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT9 *((volatile uint8_t *)(0x426225E4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT9 *((volatile uint8_t *)(0x426225E4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT10 *((volatile uint8_t *)(0x426225E8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT10 *((volatile uint8_t *)(0x426225E8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT11 *((volatile uint8_t *)(0x426225ECUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT11 *((volatile uint8_t *)(0x426225ECUL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT12 *((volatile uint8_t *)(0x426225F0UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT12 *((volatile uint8_t *)(0x426225F0UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT13 *((volatile uint8_t *)(0x426225F4UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT13 *((volatile uint8_t *)(0x426225F4UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT14 *((volatile uint8_t *)(0x426225F8UL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT14 *((volatile uint8_t *)(0x426225F8UL)) +#define bFM_INTREQ_IRQ010SEL_SELBIT15 *((volatile uint8_t *)(0x426225FCUL)) +#define bFM4_INTREQ_IRQ010SEL_SELBIT15 *((volatile uint8_t *)(0x426225FCUL)) + +#define bFM_INTREQ_IRQ011MON_EXTINT *((volatile uint8_t *)(0x42624600UL)) +#define bFM4_INTREQ_IRQ011MON_EXTINT *((volatile uint8_t *)(0x42624600UL)) + +#define bFM_INTREQ_IRQ012MON_EXTINT *((volatile uint8_t *)(0x42624680UL)) +#define bFM4_INTREQ_IRQ012MON_EXTINT *((volatile uint8_t *)(0x42624680UL)) + +#define bFM_INTREQ_IRQ013MON_EXTINT *((volatile uint8_t *)(0x42624700UL)) +#define bFM4_INTREQ_IRQ013MON_EXTINT *((volatile uint8_t *)(0x42624700UL)) + +#define bFM_INTREQ_IRQ014MON_EXTINT *((volatile uint8_t *)(0x42624780UL)) +#define bFM4_INTREQ_IRQ014MON_EXTINT *((volatile uint8_t *)(0x42624780UL)) + +#define bFM_INTREQ_IRQ015MON_EXTINT *((volatile uint8_t *)(0x42624800UL)) +#define bFM4_INTREQ_IRQ015MON_EXTINT *((volatile uint8_t *)(0x42624800UL)) + +#define bFM_INTREQ_IRQ016MON_EXTINT *((volatile uint8_t *)(0x42624880UL)) +#define bFM4_INTREQ_IRQ016MON_EXTINT *((volatile uint8_t *)(0x42624880UL)) + +#define bFM_INTREQ_IRQ017MON_EXTINT *((volatile uint8_t *)(0x42624900UL)) +#define bFM4_INTREQ_IRQ017MON_EXTINT *((volatile uint8_t *)(0x42624900UL)) + +#define bFM_INTREQ_IRQ018MON_EXTINT *((volatile uint8_t *)(0x42624980UL)) +#define bFM4_INTREQ_IRQ018MON_EXTINT *((volatile uint8_t *)(0x42624980UL)) + +#define bFM_INTREQ_IRQ019MON_QPRCINT0 *((volatile uint8_t *)(0x42624A00UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT0 *((volatile uint8_t *)(0x42624A00UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT1 *((volatile uint8_t *)(0x42624A04UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT1 *((volatile uint8_t *)(0x42624A04UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT2 *((volatile uint8_t *)(0x42624A08UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT2 *((volatile uint8_t *)(0x42624A08UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT3 *((volatile uint8_t *)(0x42624A0CUL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT3 *((volatile uint8_t *)(0x42624A0CUL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT4 *((volatile uint8_t *)(0x42624A10UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT4 *((volatile uint8_t *)(0x42624A10UL)) +#define bFM_INTREQ_IRQ019MON_QPRCINT5 *((volatile uint8_t *)(0x42624A14UL)) +#define bFM4_INTREQ_IRQ019MON_QPRCINT5 *((volatile uint8_t *)(0x42624A14UL)) + +#define bFM_INTREQ_IRQ020MON_QPRCINT0 *((volatile uint8_t *)(0x42624A80UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT0 *((volatile uint8_t *)(0x42624A80UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT1 *((volatile uint8_t *)(0x42624A84UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT1 *((volatile uint8_t *)(0x42624A84UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT2 *((volatile uint8_t *)(0x42624A88UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT2 *((volatile uint8_t *)(0x42624A88UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT3 *((volatile uint8_t *)(0x42624A8CUL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT3 *((volatile uint8_t *)(0x42624A8CUL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT4 *((volatile uint8_t *)(0x42624A90UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT4 *((volatile uint8_t *)(0x42624A90UL)) +#define bFM_INTREQ_IRQ020MON_QPRCINT5 *((volatile uint8_t *)(0x42624A94UL)) +#define bFM4_INTREQ_IRQ020MON_QPRCINT5 *((volatile uint8_t *)(0x42624A94UL)) + +#define bFM_INTREQ_IRQ021MON_WAVEINT0 *((volatile uint8_t *)(0x42624B00UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT0 *((volatile uint8_t *)(0x42624B00UL)) +#define bFM_INTREQ_IRQ021MON_WAVEINT1 *((volatile uint8_t *)(0x42624B04UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT1 *((volatile uint8_t *)(0x42624B04UL)) +#define bFM_INTREQ_IRQ021MON_WAVEINT2 *((volatile uint8_t *)(0x42624B08UL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT2 *((volatile uint8_t *)(0x42624B08UL)) +#define bFM_INTREQ_IRQ021MON_WAVEINT3 *((volatile uint8_t *)(0x42624B0CUL)) +#define bFM4_INTREQ_IRQ021MON_WAVEINT3 *((volatile uint8_t *)(0x42624B0CUL)) + +#define bFM_INTREQ_IRQ022MON_WAVEINT0 *((volatile uint8_t *)(0x42624B80UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT0 *((volatile uint8_t *)(0x42624B80UL)) +#define bFM_INTREQ_IRQ022MON_WAVEINT1 *((volatile uint8_t *)(0x42624B84UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT1 *((volatile uint8_t *)(0x42624B84UL)) +#define bFM_INTREQ_IRQ022MON_WAVEINT2 *((volatile uint8_t *)(0x42624B88UL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT2 *((volatile uint8_t *)(0x42624B88UL)) +#define bFM_INTREQ_IRQ022MON_WAVEINT3 *((volatile uint8_t *)(0x42624B8CUL)) +#define bFM4_INTREQ_IRQ022MON_WAVEINT3 *((volatile uint8_t *)(0x42624B8CUL)) + +#define bFM_INTREQ_IRQ023MON_WAVEINT0 *((volatile uint8_t *)(0x42624C00UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT0 *((volatile uint8_t *)(0x42624C00UL)) +#define bFM_INTREQ_IRQ023MON_WAVEINT1 *((volatile uint8_t *)(0x42624C04UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT1 *((volatile uint8_t *)(0x42624C04UL)) +#define bFM_INTREQ_IRQ023MON_WAVEINT2 *((volatile uint8_t *)(0x42624C08UL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT2 *((volatile uint8_t *)(0x42624C08UL)) +#define bFM_INTREQ_IRQ023MON_WAVEINT3 *((volatile uint8_t *)(0x42624C0CUL)) +#define bFM4_INTREQ_IRQ023MON_WAVEINT3 *((volatile uint8_t *)(0x42624C0CUL)) + +#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624C80UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624C80UL)) +#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624C84UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624C84UL)) +#define bFM_INTREQ_IRQ024MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624C88UL)) +#define bFM4_INTREQ_IRQ024MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624C88UL)) + +#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624D00UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624D00UL)) +#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624D04UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624D04UL)) +#define bFM_INTREQ_IRQ025MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624D08UL)) +#define bFM4_INTREQ_IRQ025MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624D08UL)) + +#define bFM_INTREQ_IRQ026MON_ICUINT0 *((volatile uint8_t *)(0x42624D80UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT0 *((volatile uint8_t *)(0x42624D80UL)) +#define bFM_INTREQ_IRQ026MON_ICUINT1 *((volatile uint8_t *)(0x42624D84UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT1 *((volatile uint8_t *)(0x42624D84UL)) +#define bFM_INTREQ_IRQ026MON_ICUINT2 *((volatile uint8_t *)(0x42624D88UL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT2 *((volatile uint8_t *)(0x42624D88UL)) +#define bFM_INTREQ_IRQ026MON_ICUINT3 *((volatile uint8_t *)(0x42624D8CUL)) +#define bFM4_INTREQ_IRQ026MON_ICUINT3 *((volatile uint8_t *)(0x42624D8CUL)) + +#define bFM_INTREQ_IRQ027MON_OCUINT0 *((volatile uint8_t *)(0x42624E00UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT0 *((volatile uint8_t *)(0x42624E00UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT1 *((volatile uint8_t *)(0x42624E04UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT1 *((volatile uint8_t *)(0x42624E04UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT2 *((volatile uint8_t *)(0x42624E08UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT2 *((volatile uint8_t *)(0x42624E08UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT3 *((volatile uint8_t *)(0x42624E0CUL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT3 *((volatile uint8_t *)(0x42624E0CUL)) +#define bFM_INTREQ_IRQ027MON_OCUINT4 *((volatile uint8_t *)(0x42624E10UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT4 *((volatile uint8_t *)(0x42624E10UL)) +#define bFM_INTREQ_IRQ027MON_OCUINT5 *((volatile uint8_t *)(0x42624E14UL)) +#define bFM4_INTREQ_IRQ027MON_OCUINT5 *((volatile uint8_t *)(0x42624E14UL)) + +#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624E80UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42624E80UL)) +#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624E84UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42624E84UL)) +#define bFM_INTREQ_IRQ028MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624E88UL)) +#define bFM4_INTREQ_IRQ028MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42624E88UL)) + +#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624F00UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42624F00UL)) +#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624F04UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42624F04UL)) +#define bFM_INTREQ_IRQ029MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624F08UL)) +#define bFM4_INTREQ_IRQ029MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42624F08UL)) + +#define bFM_INTREQ_IRQ030MON_ICUINT0 *((volatile uint8_t *)(0x42624F80UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT0 *((volatile uint8_t *)(0x42624F80UL)) +#define bFM_INTREQ_IRQ030MON_ICUINT1 *((volatile uint8_t *)(0x42624F84UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT1 *((volatile uint8_t *)(0x42624F84UL)) +#define bFM_INTREQ_IRQ030MON_ICUINT2 *((volatile uint8_t *)(0x42624F88UL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT2 *((volatile uint8_t *)(0x42624F88UL)) +#define bFM_INTREQ_IRQ030MON_ICUINT3 *((volatile uint8_t *)(0x42624F8CUL)) +#define bFM4_INTREQ_IRQ030MON_ICUINT3 *((volatile uint8_t *)(0x42624F8CUL)) + +#define bFM_INTREQ_IRQ031MON_OCUINT0 *((volatile uint8_t *)(0x42625000UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT0 *((volatile uint8_t *)(0x42625000UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT1 *((volatile uint8_t *)(0x42625004UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT1 *((volatile uint8_t *)(0x42625004UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT2 *((volatile uint8_t *)(0x42625008UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT2 *((volatile uint8_t *)(0x42625008UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT3 *((volatile uint8_t *)(0x4262500CUL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT3 *((volatile uint8_t *)(0x4262500CUL)) +#define bFM_INTREQ_IRQ031MON_OCUINT4 *((volatile uint8_t *)(0x42625010UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT4 *((volatile uint8_t *)(0x42625010UL)) +#define bFM_INTREQ_IRQ031MON_OCUINT5 *((volatile uint8_t *)(0x42625014UL)) +#define bFM4_INTREQ_IRQ031MON_OCUINT5 *((volatile uint8_t *)(0x42625014UL)) + +#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42625080UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT0 *((volatile uint8_t *)(0x42625080UL)) +#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42625084UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT1 *((volatile uint8_t *)(0x42625084UL)) +#define bFM_INTREQ_IRQ032MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42625088UL)) +#define bFM4_INTREQ_IRQ032MON_FRT_PEAK_INT2 *((volatile uint8_t *)(0x42625088UL)) + +#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42625100UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT0 *((volatile uint8_t *)(0x42625100UL)) +#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42625104UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT1 *((volatile uint8_t *)(0x42625104UL)) +#define bFM_INTREQ_IRQ033MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42625108UL)) +#define bFM4_INTREQ_IRQ033MON_FRT_ZERO_INT2 *((volatile uint8_t *)(0x42625108UL)) + +#define bFM_INTREQ_IRQ034MON_ICUINT0 *((volatile uint8_t *)(0x42625180UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT0 *((volatile uint8_t *)(0x42625180UL)) +#define bFM_INTREQ_IRQ034MON_ICUINT1 *((volatile uint8_t *)(0x42625184UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT1 *((volatile uint8_t *)(0x42625184UL)) +#define bFM_INTREQ_IRQ034MON_ICUINT2 *((volatile uint8_t *)(0x42625188UL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT2 *((volatile uint8_t *)(0x42625188UL)) +#define bFM_INTREQ_IRQ034MON_ICUINT3 *((volatile uint8_t *)(0x4262518CUL)) +#define bFM4_INTREQ_IRQ034MON_ICUINT3 *((volatile uint8_t *)(0x4262518CUL)) + +#define bFM_INTREQ_IRQ035MON_OCUINT0 *((volatile uint8_t *)(0x42625200UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT0 *((volatile uint8_t *)(0x42625200UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT1 *((volatile uint8_t *)(0x42625204UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT1 *((volatile uint8_t *)(0x42625204UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT2 *((volatile uint8_t *)(0x42625208UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT2 *((volatile uint8_t *)(0x42625208UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT3 *((volatile uint8_t *)(0x4262520CUL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT3 *((volatile uint8_t *)(0x4262520CUL)) +#define bFM_INTREQ_IRQ035MON_OCUINT4 *((volatile uint8_t *)(0x42625210UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT4 *((volatile uint8_t *)(0x42625210UL)) +#define bFM_INTREQ_IRQ035MON_OCUINT5 *((volatile uint8_t *)(0x42625214UL)) +#define bFM4_INTREQ_IRQ035MON_OCUINT5 *((volatile uint8_t *)(0x42625214UL)) + +#define bFM_INTREQ_IRQ036MON_PPGINT0 *((volatile uint8_t *)(0x42625280UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT0 *((volatile uint8_t *)(0x42625280UL)) +#define bFM_INTREQ_IRQ036MON_PPGINT1 *((volatile uint8_t *)(0x42625284UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT1 *((volatile uint8_t *)(0x42625284UL)) +#define bFM_INTREQ_IRQ036MON_PPGINT2 *((volatile uint8_t *)(0x42625288UL)) +#define bFM4_INTREQ_IRQ036MON_PPGINT2 *((volatile uint8_t *)(0x42625288UL)) + +#define bFM_INTREQ_IRQ037MON_PPGINT0 *((volatile uint8_t *)(0x42625300UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT0 *((volatile uint8_t *)(0x42625300UL)) +#define bFM_INTREQ_IRQ037MON_PPGINT1 *((volatile uint8_t *)(0x42625304UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT1 *((volatile uint8_t *)(0x42625304UL)) +#define bFM_INTREQ_IRQ037MON_PPGINT2 *((volatile uint8_t *)(0x42625308UL)) +#define bFM4_INTREQ_IRQ037MON_PPGINT2 *((volatile uint8_t *)(0x42625308UL)) + +#define bFM_INTREQ_IRQ038MON_PPGINT0 *((volatile uint8_t *)(0x42625380UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT0 *((volatile uint8_t *)(0x42625380UL)) +#define bFM_INTREQ_IRQ038MON_PPGINT1 *((volatile uint8_t *)(0x42625384UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT1 *((volatile uint8_t *)(0x42625384UL)) +#define bFM_INTREQ_IRQ038MON_PPGINT2 *((volatile uint8_t *)(0x42625388UL)) +#define bFM4_INTREQ_IRQ038MON_PPGINT2 *((volatile uint8_t *)(0x42625388UL)) + +#define bFM_INTREQ_IRQ039MON_BTINT0 *((volatile uint8_t *)(0x42625400UL)) +#define bFM4_INTREQ_IRQ039MON_BTINT0 *((volatile uint8_t *)(0x42625400UL)) +#define bFM_INTREQ_IRQ039MON_BTINT1 *((volatile uint8_t *)(0x42625404UL)) +#define bFM4_INTREQ_IRQ039MON_BTINT1 *((volatile uint8_t *)(0x42625404UL)) + +#define bFM_INTREQ_IRQ040MON_BTINT0 *((volatile uint8_t *)(0x42625480UL)) +#define bFM4_INTREQ_IRQ040MON_BTINT0 *((volatile uint8_t *)(0x42625480UL)) +#define bFM_INTREQ_IRQ040MON_BTINT1 *((volatile uint8_t *)(0x42625484UL)) +#define bFM4_INTREQ_IRQ040MON_BTINT1 *((volatile uint8_t *)(0x42625484UL)) + +#define bFM_INTREQ_IRQ041MON_BTINT0 *((volatile uint8_t *)(0x42625500UL)) +#define bFM4_INTREQ_IRQ041MON_BTINT0 *((volatile uint8_t *)(0x42625500UL)) +#define bFM_INTREQ_IRQ041MON_BTINT1 *((volatile uint8_t *)(0x42625504UL)) +#define bFM4_INTREQ_IRQ041MON_BTINT1 *((volatile uint8_t *)(0x42625504UL)) + +#define bFM_INTREQ_IRQ042MON_BTINT0 *((volatile uint8_t *)(0x42625580UL)) +#define bFM4_INTREQ_IRQ042MON_BTINT0 *((volatile uint8_t *)(0x42625580UL)) +#define bFM_INTREQ_IRQ042MON_BTINT1 *((volatile uint8_t *)(0x42625584UL)) +#define bFM4_INTREQ_IRQ042MON_BTINT1 *((volatile uint8_t *)(0x42625584UL)) + +#define bFM_INTREQ_IRQ043MON_BTINT0 *((volatile uint8_t *)(0x42625600UL)) +#define bFM4_INTREQ_IRQ043MON_BTINT0 *((volatile uint8_t *)(0x42625600UL)) +#define bFM_INTREQ_IRQ043MON_BTINT1 *((volatile uint8_t *)(0x42625604UL)) +#define bFM4_INTREQ_IRQ043MON_BTINT1 *((volatile uint8_t *)(0x42625604UL)) + +#define bFM_INTREQ_IRQ044MON_BTINT0 *((volatile uint8_t *)(0x42625680UL)) +#define bFM4_INTREQ_IRQ044MON_BTINT0 *((volatile uint8_t *)(0x42625680UL)) +#define bFM_INTREQ_IRQ044MON_BTINT1 *((volatile uint8_t *)(0x42625684UL)) +#define bFM4_INTREQ_IRQ044MON_BTINT1 *((volatile uint8_t *)(0x42625684UL)) + +#define bFM_INTREQ_IRQ045MON_BTINT0 *((volatile uint8_t *)(0x42625700UL)) +#define bFM4_INTREQ_IRQ045MON_BTINT0 *((volatile uint8_t *)(0x42625700UL)) +#define bFM_INTREQ_IRQ045MON_BTINT1 *((volatile uint8_t *)(0x42625704UL)) +#define bFM4_INTREQ_IRQ045MON_BTINT1 *((volatile uint8_t *)(0x42625704UL)) + +#define bFM_INTREQ_IRQ046MON_BTINT0 *((volatile uint8_t *)(0x42625780UL)) +#define bFM4_INTREQ_IRQ046MON_BTINT0 *((volatile uint8_t *)(0x42625780UL)) +#define bFM_INTREQ_IRQ046MON_BTINT1 *((volatile uint8_t *)(0x42625784UL)) +#define bFM4_INTREQ_IRQ046MON_BTINT1 *((volatile uint8_t *)(0x42625784UL)) + +#define bFM_INTREQ_IRQ047MON_TIMINT1 *((volatile uint8_t *)(0x42625800UL)) +#define bFM4_INTREQ_IRQ047MON_TIMINT1 *((volatile uint8_t *)(0x42625800UL)) +#define bFM_INTREQ_IRQ047MON_TIMINT2 *((volatile uint8_t *)(0x42625804UL)) +#define bFM4_INTREQ_IRQ047MON_TIMINT2 *((volatile uint8_t *)(0x42625804UL)) + +#define bFM_INTREQ_IRQ048MON_WCINT *((volatile uint8_t *)(0x42625880UL)) +#define bFM4_INTREQ_IRQ048MON_WCINT *((volatile uint8_t *)(0x42625880UL)) + +#define bFM_INTREQ_IRQ049MON_BMEMCS *((volatile uint8_t *)(0x42625900UL)) +#define bFM4_INTREQ_IRQ049MON_BMEMCS *((volatile uint8_t *)(0x42625900UL)) + +#define bFM_INTREQ_IRQ050MON_RTCINT *((volatile uint8_t *)(0x42625980UL)) +#define bFM4_INTREQ_IRQ050MON_RTCINT *((volatile uint8_t *)(0x42625980UL)) + +#define bFM_INTREQ_IRQ051MON_EXTINT *((volatile uint8_t *)(0x42625A00UL)) +#define bFM4_INTREQ_IRQ051MON_EXTINT *((volatile uint8_t *)(0x42625A00UL)) + +#define bFM_INTREQ_IRQ052MON_EXTINT *((volatile uint8_t *)(0x42625A80UL)) +#define bFM4_INTREQ_IRQ052MON_EXTINT *((volatile uint8_t *)(0x42625A80UL)) + +#define bFM_INTREQ_IRQ053MON_EXTINT *((volatile uint8_t *)(0x42625B00UL)) +#define bFM4_INTREQ_IRQ053MON_EXTINT *((volatile uint8_t *)(0x42625B00UL)) + +#define bFM_INTREQ_IRQ054MON_EXTINT *((volatile uint8_t *)(0x42625B80UL)) +#define bFM4_INTREQ_IRQ054MON_EXTINT *((volatile uint8_t *)(0x42625B80UL)) + +#define bFM_INTREQ_IRQ055MON_EXTINT *((volatile uint8_t *)(0x42625C00UL)) +#define bFM4_INTREQ_IRQ055MON_EXTINT *((volatile uint8_t *)(0x42625C00UL)) + +#define bFM_INTREQ_IRQ056MON_EXTINT *((volatile uint8_t *)(0x42625C80UL)) +#define bFM4_INTREQ_IRQ056MON_EXTINT *((volatile uint8_t *)(0x42625C80UL)) + +#define bFM_INTREQ_IRQ057MON_EXTINT *((volatile uint8_t *)(0x42625D00UL)) +#define bFM4_INTREQ_IRQ057MON_EXTINT *((volatile uint8_t *)(0x42625D00UL)) + +#define bFM_INTREQ_IRQ058MON_EXTINT *((volatile uint8_t *)(0x42625D80UL)) +#define bFM4_INTREQ_IRQ058MON_EXTINT *((volatile uint8_t *)(0x42625D80UL)) + +#define bFM_INTREQ_IRQ059MON_MOSCINT *((volatile uint8_t *)(0x42625E00UL)) +#define bFM4_INTREQ_IRQ059MON_MOSCINT *((volatile uint8_t *)(0x42625E00UL)) +#define bFM_INTREQ_IRQ059MON_SOSCINT *((volatile uint8_t *)(0x42625E04UL)) +#define bFM4_INTREQ_IRQ059MON_SOSCINT *((volatile uint8_t *)(0x42625E04UL)) +#define bFM_INTREQ_IRQ059MON_MPLLINT *((volatile uint8_t *)(0x42625E08UL)) +#define bFM4_INTREQ_IRQ059MON_MPLLINT *((volatile uint8_t *)(0x42625E08UL)) +#define bFM_INTREQ_IRQ059MON_UPLLINT *((volatile uint8_t *)(0x42625E0CUL)) +#define bFM4_INTREQ_IRQ059MON_UPLLINT *((volatile uint8_t *)(0x42625E0CUL)) +#define bFM_INTREQ_IRQ059MON_IPLLINT *((volatile uint8_t *)(0x42625E10UL)) +#define bFM4_INTREQ_IRQ059MON_IPLLINT *((volatile uint8_t *)(0x42625E10UL)) + +#define bFM_INTREQ_IRQ060MON_MFSINT0_RX *((volatile uint8_t *)(0x42625E80UL)) +#define bFM4_INTREQ_IRQ060MON_MFSINT0_RX *((volatile uint8_t *)(0x42625E80UL)) + +#define bFM_INTREQ_IRQ061MON_MFSINT0_TX *((volatile uint8_t *)(0x42625F00UL)) +#define bFM4_INTREQ_IRQ061MON_MFSINT0_TX *((volatile uint8_t *)(0x42625F00UL)) +#define bFM_INTREQ_IRQ061MON_MFSINT0_STATUS *((volatile uint8_t *)(0x42625F04UL)) +#define bFM4_INTREQ_IRQ061MON_MFSINT0_STATUS *((volatile uint8_t *)(0x42625F04UL)) + +#define bFM_INTREQ_IRQ062MON_MFSINT1_RX *((volatile uint8_t *)(0x42625F80UL)) +#define bFM4_INTREQ_IRQ062MON_MFSINT1_RX *((volatile uint8_t *)(0x42625F80UL)) + +#define bFM_INTREQ_IRQ063MON_MFSINT1_TX *((volatile uint8_t *)(0x42626000UL)) +#define bFM4_INTREQ_IRQ063MON_MFSINT1_TX *((volatile uint8_t *)(0x42626000UL)) +#define bFM_INTREQ_IRQ063MON_MFSINT1_STATUS *((volatile uint8_t *)(0x42626004UL)) +#define bFM4_INTREQ_IRQ063MON_MFSINT1_STATUS *((volatile uint8_t *)(0x42626004UL)) + +#define bFM_INTREQ_IRQ064MON_MFSINT2_RX *((volatile uint8_t *)(0x42626080UL)) +#define bFM4_INTREQ_IRQ064MON_MFSINT2_RX *((volatile uint8_t *)(0x42626080UL)) + +#define bFM_INTREQ_IRQ065MON_MFSINT2_TX *((volatile uint8_t *)(0x42626100UL)) +#define bFM4_INTREQ_IRQ065MON_MFSINT2_TX *((volatile uint8_t *)(0x42626100UL)) +#define bFM_INTREQ_IRQ065MON_MFSINT2_STATUS *((volatile uint8_t *)(0x42626104UL)) +#define bFM4_INTREQ_IRQ065MON_MFSINT2_STATUS *((volatile uint8_t *)(0x42626104UL)) + +#define bFM_INTREQ_IRQ066MON_MFSINT3_RX *((volatile uint8_t *)(0x42626180UL)) +#define bFM4_INTREQ_IRQ066MON_MFSINT3_RX *((volatile uint8_t *)(0x42626180UL)) + +#define bFM_INTREQ_IRQ067MON_MFSINT3_TX *((volatile uint8_t *)(0x42626200UL)) +#define bFM4_INTREQ_IRQ067MON_MFSINT3_TX *((volatile uint8_t *)(0x42626200UL)) +#define bFM_INTREQ_IRQ067MON_MFSINT3_STATUS *((volatile uint8_t *)(0x42626204UL)) +#define bFM4_INTREQ_IRQ067MON_MFSINT3_STATUS *((volatile uint8_t *)(0x42626204UL)) + +#define bFM_INTREQ_IRQ068MON_MFSINT4_RX *((volatile uint8_t *)(0x42626280UL)) +#define bFM4_INTREQ_IRQ068MON_MFSINT4_RX *((volatile uint8_t *)(0x42626280UL)) + +#define bFM_INTREQ_IRQ069MON_MFSINT4_TX *((volatile uint8_t *)(0x42626300UL)) +#define bFM4_INTREQ_IRQ069MON_MFSINT4_TX *((volatile uint8_t *)(0x42626300UL)) +#define bFM_INTREQ_IRQ069MON_MFSINT4_STATUS *((volatile uint8_t *)(0x42626304UL)) +#define bFM4_INTREQ_IRQ069MON_MFSINT4_STATUS *((volatile uint8_t *)(0x42626304UL)) + +#define bFM_INTREQ_IRQ070MON_MFSINT5_RX *((volatile uint8_t *)(0x42626380UL)) +#define bFM4_INTREQ_IRQ070MON_MFSINT5_RX *((volatile uint8_t *)(0x42626380UL)) + +#define bFM_INTREQ_IRQ071MON_MFSINT5_TX *((volatile uint8_t *)(0x42626400UL)) +#define bFM4_INTREQ_IRQ071MON_MFSINT5_TX *((volatile uint8_t *)(0x42626400UL)) +#define bFM_INTREQ_IRQ071MON_MFSINT5_STATUS *((volatile uint8_t *)(0x42626404UL)) +#define bFM4_INTREQ_IRQ071MON_MFSINT5_STATUS *((volatile uint8_t *)(0x42626404UL)) + +#define bFM_INTREQ_IRQ072MON_MFSINT6_RX *((volatile uint8_t *)(0x42626480UL)) +#define bFM4_INTREQ_IRQ072MON_MFSINT6_RX *((volatile uint8_t *)(0x42626480UL)) + +#define bFM_INTREQ_IRQ073MON_MFSINT6_TX *((volatile uint8_t *)(0x42626500UL)) +#define bFM4_INTREQ_IRQ073MON_MFSINT6_TX *((volatile uint8_t *)(0x42626500UL)) +#define bFM_INTREQ_IRQ073MON_MFSINT6_STATUS *((volatile uint8_t *)(0x42626504UL)) +#define bFM4_INTREQ_IRQ073MON_MFSINT6_STATUS *((volatile uint8_t *)(0x42626504UL)) + +#define bFM_INTREQ_IRQ074MON_MFSINT7_RX *((volatile uint8_t *)(0x42626580UL)) +#define bFM4_INTREQ_IRQ074MON_MFSINT7_RX *((volatile uint8_t *)(0x42626580UL)) + +#define bFM_INTREQ_IRQ075MON_MFSINT7_TX *((volatile uint8_t *)(0x42626600UL)) +#define bFM4_INTREQ_IRQ075MON_MFSINT7_TX *((volatile uint8_t *)(0x42626600UL)) +#define bFM_INTREQ_IRQ075MON_MFSINT7_STATUS *((volatile uint8_t *)(0x42626604UL)) +#define bFM4_INTREQ_IRQ075MON_MFSINT7_STATUS *((volatile uint8_t *)(0x42626604UL)) + +#define bFM_INTREQ_IRQ076MON_ADCINT0 *((volatile uint8_t *)(0x42626680UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT0 *((volatile uint8_t *)(0x42626680UL)) +#define bFM_INTREQ_IRQ076MON_ADCINT1 *((volatile uint8_t *)(0x42626684UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT1 *((volatile uint8_t *)(0x42626684UL)) +#define bFM_INTREQ_IRQ076MON_ADCINT2 *((volatile uint8_t *)(0x42626688UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT2 *((volatile uint8_t *)(0x42626688UL)) +#define bFM_INTREQ_IRQ076MON_ADCINT3 *((volatile uint8_t *)(0x4262668CUL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT3 *((volatile uint8_t *)(0x4262668CUL)) +#define bFM_INTREQ_IRQ076MON_ADCINT4 *((volatile uint8_t *)(0x42626690UL)) +#define bFM4_INTREQ_IRQ076MON_ADCINT4 *((volatile uint8_t *)(0x42626690UL)) + +#define bFM_INTREQ_IRQ077MON_ADCINT0 *((volatile uint8_t *)(0x42626700UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT0 *((volatile uint8_t *)(0x42626700UL)) +#define bFM_INTREQ_IRQ077MON_ADCINT1 *((volatile uint8_t *)(0x42626704UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT1 *((volatile uint8_t *)(0x42626704UL)) +#define bFM_INTREQ_IRQ077MON_ADCINT2 *((volatile uint8_t *)(0x42626708UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT2 *((volatile uint8_t *)(0x42626708UL)) +#define bFM_INTREQ_IRQ077MON_ADCINT3 *((volatile uint8_t *)(0x4262670CUL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT3 *((volatile uint8_t *)(0x4262670CUL)) +#define bFM_INTREQ_IRQ077MON_ADCINT4 *((volatile uint8_t *)(0x42626710UL)) +#define bFM4_INTREQ_IRQ077MON_ADCINT4 *((volatile uint8_t *)(0x42626710UL)) + +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42626780UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42626780UL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42626784UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42626784UL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42626788UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42626788UL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262678CUL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262678CUL)) +#define bFM_INTREQ_IRQ078MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42626790UL)) +#define bFM4_INTREQ_IRQ078MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42626790UL)) + +#define bFM_INTREQ_IRQ079MON_USB_INT0 *((volatile uint8_t *)(0x42626800UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT0 *((volatile uint8_t *)(0x42626800UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT1 *((volatile uint8_t *)(0x42626804UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT1 *((volatile uint8_t *)(0x42626804UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT2 *((volatile uint8_t *)(0x42626808UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT2 *((volatile uint8_t *)(0x42626808UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT3 *((volatile uint8_t *)(0x4262680CUL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT3 *((volatile uint8_t *)(0x4262680CUL)) +#define bFM_INTREQ_IRQ079MON_USB_INT4 *((volatile uint8_t *)(0x42626810UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT4 *((volatile uint8_t *)(0x42626810UL)) +#define bFM_INTREQ_IRQ079MON_USB_INT5 *((volatile uint8_t *)(0x42626814UL)) +#define bFM4_INTREQ_IRQ079MON_USB_INT5 *((volatile uint8_t *)(0x42626814UL)) + +#define bFM_INTREQ_IRQ080MON_CANINT *((volatile uint8_t *)(0x42626880UL)) +#define bFM4_INTREQ_IRQ080MON_CANINT *((volatile uint8_t *)(0x42626880UL)) + +#define bFM_INTREQ_IRQ081MON_CANINT *((volatile uint8_t *)(0x42626900UL)) +#define bFM4_INTREQ_IRQ081MON_CANINT *((volatile uint8_t *)(0x42626900UL)) +#define bFM_INTREQ_IRQ081MON_CANDEINT *((volatile uint8_t *)(0x42626904UL)) +#define bFM4_INTREQ_IRQ081MON_CANDEINT *((volatile uint8_t *)(0x42626904UL)) +#define bFM_INTREQ_IRQ081MON_CANSEINT *((volatile uint8_t *)(0x42626908UL)) +#define bFM4_INTREQ_IRQ081MON_CANSEINT *((volatile uint8_t *)(0x42626908UL)) +#define bFM_INTREQ_IRQ081MON_CAN0INT *((volatile uint8_t *)(0x4262690CUL)) +#define bFM4_INTREQ_IRQ081MON_CAN0INT *((volatile uint8_t *)(0x4262690CUL)) +#define bFM_INTREQ_IRQ081MON_CAN1INT *((volatile uint8_t *)(0x42626910UL)) +#define bFM4_INTREQ_IRQ081MON_CAN1INT *((volatile uint8_t *)(0x42626910UL)) + +#define bFM_INTREQ_IRQ082MON_MACSBD *((volatile uint8_t *)(0x42626980UL)) +#define bFM4_INTREQ_IRQ082MON_MACSBD *((volatile uint8_t *)(0x42626980UL)) +#define bFM_INTREQ_IRQ082MON_MACPMT *((volatile uint8_t *)(0x42626984UL)) +#define bFM4_INTREQ_IRQ082MON_MACPMT *((volatile uint8_t *)(0x42626984UL)) +#define bFM_INTREQ_IRQ082MON_MACLPI *((volatile uint8_t *)(0x42626988UL)) +#define bFM4_INTREQ_IRQ082MON_MACLPI *((volatile uint8_t *)(0x42626988UL)) + +#define bFM_INTREQ_IRQ083MON_DMACINT *((volatile uint8_t *)(0x42626A00UL)) +#define bFM4_INTREQ_IRQ083MON_DMACINT *((volatile uint8_t *)(0x42626A00UL)) + +#define bFM_INTREQ_IRQ084MON_DMACINT *((volatile uint8_t *)(0x42626A80UL)) +#define bFM4_INTREQ_IRQ084MON_DMACINT *((volatile uint8_t *)(0x42626A80UL)) + +#define bFM_INTREQ_IRQ085MON_DMACINT *((volatile uint8_t *)(0x42626B00UL)) +#define bFM4_INTREQ_IRQ085MON_DMACINT *((volatile uint8_t *)(0x42626B00UL)) + +#define bFM_INTREQ_IRQ086MON_DMACINT *((volatile uint8_t *)(0x42626B80UL)) +#define bFM4_INTREQ_IRQ086MON_DMACINT *((volatile uint8_t *)(0x42626B80UL)) + +#define bFM_INTREQ_IRQ087MON_DMACINT *((volatile uint8_t *)(0x42626C00UL)) +#define bFM4_INTREQ_IRQ087MON_DMACINT *((volatile uint8_t *)(0x42626C00UL)) + +#define bFM_INTREQ_IRQ088MON_DMACINT *((volatile uint8_t *)(0x42626C80UL)) +#define bFM4_INTREQ_IRQ088MON_DMACINT *((volatile uint8_t *)(0x42626C80UL)) + +#define bFM_INTREQ_IRQ089MON_DMACINT *((volatile uint8_t *)(0x42626D00UL)) +#define bFM4_INTREQ_IRQ089MON_DMACINT *((volatile uint8_t *)(0x42626D00UL)) + +#define bFM_INTREQ_IRQ090MON_DMACINT *((volatile uint8_t *)(0x42626D80UL)) +#define bFM4_INTREQ_IRQ090MON_DMACINT *((volatile uint8_t *)(0x42626D80UL)) + +#define bFM_INTREQ_IRQ091MON_DSTCINT0 *((volatile uint8_t *)(0x42626E00UL)) +#define bFM4_INTREQ_IRQ091MON_DSTCINT0 *((volatile uint8_t *)(0x42626E00UL)) +#define bFM_INTREQ_IRQ091MON_DSTCINT1 *((volatile uint8_t *)(0x42626E04UL)) +#define bFM4_INTREQ_IRQ091MON_DSTCINT1 *((volatile uint8_t *)(0x42626E04UL)) + +#define bFM_INTREQ_IRQ092MON_EXTINT0 *((volatile uint8_t *)(0x42626E80UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT0 *((volatile uint8_t *)(0x42626E80UL)) +#define bFM_INTREQ_IRQ092MON_EXTINT1 *((volatile uint8_t *)(0x42626E84UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT1 *((volatile uint8_t *)(0x42626E84UL)) +#define bFM_INTREQ_IRQ092MON_EXTINT2 *((volatile uint8_t *)(0x42626E88UL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT2 *((volatile uint8_t *)(0x42626E88UL)) +#define bFM_INTREQ_IRQ092MON_EXTINT3 *((volatile uint8_t *)(0x42626E8CUL)) +#define bFM4_INTREQ_IRQ092MON_EXTINT3 *((volatile uint8_t *)(0x42626E8CUL)) + +#define bFM_INTREQ_IRQ093MON_EXTINT0 *((volatile uint8_t *)(0x42626F00UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT0 *((volatile uint8_t *)(0x42626F00UL)) +#define bFM_INTREQ_IRQ093MON_EXTINT1 *((volatile uint8_t *)(0x42626F04UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT1 *((volatile uint8_t *)(0x42626F04UL)) +#define bFM_INTREQ_IRQ093MON_EXTINT2 *((volatile uint8_t *)(0x42626F08UL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT2 *((volatile uint8_t *)(0x42626F08UL)) +#define bFM_INTREQ_IRQ093MON_EXTINT3 *((volatile uint8_t *)(0x42626F0CUL)) +#define bFM4_INTREQ_IRQ093MON_EXTINT3 *((volatile uint8_t *)(0x42626F0CUL)) + +#define bFM_INTREQ_IRQ094MON_EXTINT0 *((volatile uint8_t *)(0x42626F80UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT0 *((volatile uint8_t *)(0x42626F80UL)) +#define bFM_INTREQ_IRQ094MON_EXTINT1 *((volatile uint8_t *)(0x42626F84UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT1 *((volatile uint8_t *)(0x42626F84UL)) +#define bFM_INTREQ_IRQ094MON_EXTINT2 *((volatile uint8_t *)(0x42626F88UL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT2 *((volatile uint8_t *)(0x42626F88UL)) +#define bFM_INTREQ_IRQ094MON_EXTINT3 *((volatile uint8_t *)(0x42626F8CUL)) +#define bFM4_INTREQ_IRQ094MON_EXTINT3 *((volatile uint8_t *)(0x42626F8CUL)) + +#define bFM_INTREQ_IRQ095MON_EXTINT0 *((volatile uint8_t *)(0x42627000UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT0 *((volatile uint8_t *)(0x42627000UL)) +#define bFM_INTREQ_IRQ095MON_EXTINT1 *((volatile uint8_t *)(0x42627004UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT1 *((volatile uint8_t *)(0x42627004UL)) +#define bFM_INTREQ_IRQ095MON_EXTINT2 *((volatile uint8_t *)(0x42627008UL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT2 *((volatile uint8_t *)(0x42627008UL)) +#define bFM_INTREQ_IRQ095MON_EXTINT3 *((volatile uint8_t *)(0x4262700CUL)) +#define bFM4_INTREQ_IRQ095MON_EXTINT3 *((volatile uint8_t *)(0x4262700CUL)) + +#define bFM_INTREQ_IRQ096MON_QPRCINT0 *((volatile uint8_t *)(0x42627080UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT0 *((volatile uint8_t *)(0x42627080UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT1 *((volatile uint8_t *)(0x42627084UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT1 *((volatile uint8_t *)(0x42627084UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT2 *((volatile uint8_t *)(0x42627088UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT2 *((volatile uint8_t *)(0x42627088UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT3 *((volatile uint8_t *)(0x4262708CUL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT3 *((volatile uint8_t *)(0x4262708CUL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT4 *((volatile uint8_t *)(0x42627090UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT4 *((volatile uint8_t *)(0x42627090UL)) +#define bFM_INTREQ_IRQ096MON_QPRCINT5 *((volatile uint8_t *)(0x42627094UL)) +#define bFM4_INTREQ_IRQ096MON_QPRCINT5 *((volatile uint8_t *)(0x42627094UL)) + +#define bFM_INTREQ_IRQ097MON_QPRCINT0 *((volatile uint8_t *)(0x42627100UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT0 *((volatile uint8_t *)(0x42627100UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT1 *((volatile uint8_t *)(0x42627104UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT1 *((volatile uint8_t *)(0x42627104UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT2 *((volatile uint8_t *)(0x42627108UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT2 *((volatile uint8_t *)(0x42627108UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT3 *((volatile uint8_t *)(0x4262710CUL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT3 *((volatile uint8_t *)(0x4262710CUL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT4 *((volatile uint8_t *)(0x42627110UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT4 *((volatile uint8_t *)(0x42627110UL)) +#define bFM_INTREQ_IRQ097MON_QPRCINT5 *((volatile uint8_t *)(0x42627114UL)) +#define bFM4_INTREQ_IRQ097MON_QPRCINT5 *((volatile uint8_t *)(0x42627114UL)) + +#define bFM_INTREQ_IRQ098MON_BTINT0 *((volatile uint8_t *)(0x42627180UL)) +#define bFM4_INTREQ_IRQ098MON_BTINT0 *((volatile uint8_t *)(0x42627180UL)) +#define bFM_INTREQ_IRQ098MON_BTINT1 *((volatile uint8_t *)(0x42627184UL)) +#define bFM4_INTREQ_IRQ098MON_BTINT1 *((volatile uint8_t *)(0x42627184UL)) + +#define bFM_INTREQ_IRQ099MON_BTINT0 *((volatile uint8_t *)(0x42627200UL)) +#define bFM4_INTREQ_IRQ099MON_BTINT0 *((volatile uint8_t *)(0x42627200UL)) +#define bFM_INTREQ_IRQ099MON_BTINT1 *((volatile uint8_t *)(0x42627204UL)) +#define bFM4_INTREQ_IRQ099MON_BTINT1 *((volatile uint8_t *)(0x42627204UL)) + +#define bFM_INTREQ_IRQ100MON_BTINT0 *((volatile uint8_t *)(0x42627280UL)) +#define bFM4_INTREQ_IRQ100MON_BTINT0 *((volatile uint8_t *)(0x42627280UL)) +#define bFM_INTREQ_IRQ100MON_BTINT1 *((volatile uint8_t *)(0x42627284UL)) +#define bFM4_INTREQ_IRQ100MON_BTINT1 *((volatile uint8_t *)(0x42627284UL)) + +#define bFM_INTREQ_IRQ101MON_BTINT0 *((volatile uint8_t *)(0x42627300UL)) +#define bFM4_INTREQ_IRQ101MON_BTINT0 *((volatile uint8_t *)(0x42627300UL)) +#define bFM_INTREQ_IRQ101MON_BTINT1 *((volatile uint8_t *)(0x42627304UL)) +#define bFM4_INTREQ_IRQ101MON_BTINT1 *((volatile uint8_t *)(0x42627304UL)) + +#define bFM_INTREQ_IRQ102MON_BTINT0 *((volatile uint8_t *)(0x42627380UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT0 *((volatile uint8_t *)(0x42627380UL)) +#define bFM_INTREQ_IRQ102MON_BTINT1 *((volatile uint8_t *)(0x42627384UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT1 *((volatile uint8_t *)(0x42627384UL)) +#define bFM_INTREQ_IRQ102MON_BTINT2 *((volatile uint8_t *)(0x42627388UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT2 *((volatile uint8_t *)(0x42627388UL)) +#define bFM_INTREQ_IRQ102MON_BTINT3 *((volatile uint8_t *)(0x4262738CUL)) +#define bFM4_INTREQ_IRQ102MON_BTINT3 *((volatile uint8_t *)(0x4262738CUL)) +#define bFM_INTREQ_IRQ102MON_BTINT4 *((volatile uint8_t *)(0x42627390UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT4 *((volatile uint8_t *)(0x42627390UL)) +#define bFM_INTREQ_IRQ102MON_BTINT5 *((volatile uint8_t *)(0x42627394UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT5 *((volatile uint8_t *)(0x42627394UL)) +#define bFM_INTREQ_IRQ102MON_BTINT6 *((volatile uint8_t *)(0x42627398UL)) +#define bFM4_INTREQ_IRQ102MON_BTINT6 *((volatile uint8_t *)(0x42627398UL)) +#define bFM_INTREQ_IRQ102MON_BTINT7 *((volatile uint8_t *)(0x4262739CUL)) +#define bFM4_INTREQ_IRQ102MON_BTINT7 *((volatile uint8_t *)(0x4262739CUL)) + +#define bFM_INTREQ_IRQ103MON_MFSINT8_RX *((volatile uint8_t *)(0x42627400UL)) +#define bFM4_INTREQ_IRQ103MON_MFSINT8_RX *((volatile uint8_t *)(0x42627400UL)) + +#define bFM_INTREQ_IRQ104MON_MFSINT8_TX *((volatile uint8_t *)(0x42627480UL)) +#define bFM4_INTREQ_IRQ104MON_MFSINT8_TX *((volatile uint8_t *)(0x42627480UL)) +#define bFM_INTREQ_IRQ104MON_MFSINT8_STATUS *((volatile uint8_t *)(0x42627484UL)) +#define bFM4_INTREQ_IRQ104MON_MFSINT8_STATUS *((volatile uint8_t *)(0x42627484UL)) + +#define bFM_INTREQ_IRQ105MON_MFSINT9_RX *((volatile uint8_t *)(0x42627500UL)) +#define bFM4_INTREQ_IRQ105MON_MFSINT9_RX *((volatile uint8_t *)(0x42627500UL)) + +#define bFM_INTREQ_IRQ106MON_MFSINT9_TX *((volatile uint8_t *)(0x42627580UL)) +#define bFM4_INTREQ_IRQ106MON_MFSINT9_TX *((volatile uint8_t *)(0x42627580UL)) +#define bFM_INTREQ_IRQ106MON_MFSINT9_STATUS *((volatile uint8_t *)(0x42627584UL)) +#define bFM4_INTREQ_IRQ106MON_MFSINT9_STATUS *((volatile uint8_t *)(0x42627584UL)) + +#define bFM_INTREQ_IRQ107MON_MFSINT10_RX *((volatile uint8_t *)(0x42627600UL)) +#define bFM4_INTREQ_IRQ107MON_MFSINT10_RX *((volatile uint8_t *)(0x42627600UL)) + +#define bFM_INTREQ_IRQ108MON_MFSINT10_TX *((volatile uint8_t *)(0x42627680UL)) +#define bFM4_INTREQ_IRQ108MON_MFSINT10_TX *((volatile uint8_t *)(0x42627680UL)) +#define bFM_INTREQ_IRQ108MON_MFSINT10_STATUS *((volatile uint8_t *)(0x42627684UL)) +#define bFM4_INTREQ_IRQ108MON_MFSINT10_STATUS *((volatile uint8_t *)(0x42627684UL)) + +#define bFM_INTREQ_IRQ109MON_MFSINT11_RX *((volatile uint8_t *)(0x42627700UL)) +#define bFM4_INTREQ_IRQ109MON_MFSINT11_RX *((volatile uint8_t *)(0x42627700UL)) + +#define bFM_INTREQ_IRQ110MON_MFSINT11_TX *((volatile uint8_t *)(0x42627780UL)) +#define bFM4_INTREQ_IRQ110MON_MFSINT11_TX *((volatile uint8_t *)(0x42627780UL)) +#define bFM_INTREQ_IRQ110MON_MFSINT11_STATUS *((volatile uint8_t *)(0x42627784UL)) +#define bFM4_INTREQ_IRQ110MON_MFSINT11_STATUS *((volatile uint8_t *)(0x42627784UL)) + +#define bFM_INTREQ_IRQ111MON_ADCINT0 *((volatile uint8_t *)(0x42627800UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT0 *((volatile uint8_t *)(0x42627800UL)) +#define bFM_INTREQ_IRQ111MON_ADCINT1 *((volatile uint8_t *)(0x42627804UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT1 *((volatile uint8_t *)(0x42627804UL)) +#define bFM_INTREQ_IRQ111MON_ADCINT2 *((volatile uint8_t *)(0x42627808UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT2 *((volatile uint8_t *)(0x42627808UL)) +#define bFM_INTREQ_IRQ111MON_ADCINT3 *((volatile uint8_t *)(0x4262780CUL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT3 *((volatile uint8_t *)(0x4262780CUL)) +#define bFM_INTREQ_IRQ111MON_ADCINT4 *((volatile uint8_t *)(0x42627810UL)) +#define bFM4_INTREQ_IRQ111MON_ADCINT4 *((volatile uint8_t *)(0x42627810UL)) + +#define bFM_INTREQ_IRQ112MON_I2SDINT0 *((volatile uint8_t *)(0x42627880UL)) +#define bFM4_INTREQ_IRQ112MON_I2SDINT0 *((volatile uint8_t *)(0x42627880UL)) +#define bFM_INTREQ_IRQ112MON_I2SDINT1 *((volatile uint8_t *)(0x42627884UL)) +#define bFM4_INTREQ_IRQ112MON_I2SDINT1 *((volatile uint8_t *)(0x42627884UL)) +#define bFM_INTREQ_IRQ112MON_HSSPIDINT0 *((volatile uint8_t *)(0x42627888UL)) +#define bFM4_INTREQ_IRQ112MON_HSSPIDINT0 *((volatile uint8_t *)(0x42627888UL)) +#define bFM_INTREQ_IRQ112MON_HSSPIDINT1 *((volatile uint8_t *)(0x4262788CUL)) +#define bFM4_INTREQ_IRQ112MON_HSSPIDINT1 *((volatile uint8_t *)(0x4262788CUL)) +#define bFM_INTREQ_IRQ112MON_PCRCDINT *((volatile uint8_t *)(0x42627890UL)) +#define bFM4_INTREQ_IRQ112MON_PCRCDINT *((volatile uint8_t *)(0x42627890UL)) +#define bFM_INTREQ_IRQ112MON_CANDINT *((volatile uint8_t *)(0x42627894UL)) +#define bFM4_INTREQ_IRQ112MON_CANDINT *((volatile uint8_t *)(0x42627894UL)) + +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42627900UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT0 *((volatile uint8_t *)(0x42627900UL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42627904UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT1 *((volatile uint8_t *)(0x42627904UL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42627908UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT2 *((volatile uint8_t *)(0x42627908UL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262790CUL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT3 *((volatile uint8_t *)(0x4262790CUL)) +#define bFM_INTREQ_IRQ113MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42627910UL)) +#define bFM4_INTREQ_IRQ113MON_USB_DRQ_INT4 *((volatile uint8_t *)(0x42627910UL)) +#define bFM_INTREQ_IRQ113MON_RCEC0INT *((volatile uint8_t *)(0x42627914UL)) +#define bFM4_INTREQ_IRQ113MON_RCEC0INT *((volatile uint8_t *)(0x42627914UL)) + +#define bFM_INTREQ_IRQ114MON_USB_INT0 *((volatile uint8_t *)(0x42627980UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT0 *((volatile uint8_t *)(0x42627980UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT1 *((volatile uint8_t *)(0x42627984UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT1 *((volatile uint8_t *)(0x42627984UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT2 *((volatile uint8_t *)(0x42627988UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT2 *((volatile uint8_t *)(0x42627988UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT3 *((volatile uint8_t *)(0x4262798CUL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT3 *((volatile uint8_t *)(0x4262798CUL)) +#define bFM_INTREQ_IRQ114MON_USB_INT4 *((volatile uint8_t *)(0x42627990UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT4 *((volatile uint8_t *)(0x42627990UL)) +#define bFM_INTREQ_IRQ114MON_USB_INT5 *((volatile uint8_t *)(0x42627994UL)) +#define bFM4_INTREQ_IRQ114MON_USB_INT5 *((volatile uint8_t *)(0x42627994UL)) +#define bFM_INTREQ_IRQ114MON_RCEC1INT *((volatile uint8_t *)(0x42627998UL)) +#define bFM4_INTREQ_IRQ114MON_RCEC1INT *((volatile uint8_t *)(0x42627998UL)) + +#define bFM_INTREQ_IRQ115MON_HSSPIINT0 *((volatile uint8_t *)(0x42627A00UL)) +#define bFM4_INTREQ_IRQ115MON_HSSPIINT0 *((volatile uint8_t *)(0x42627A00UL)) +#define bFM_INTREQ_IRQ115MON_HSSPIINT1 *((volatile uint8_t *)(0x42627A04UL)) +#define bFM4_INTREQ_IRQ115MON_HSSPIINT1 *((volatile uint8_t *)(0x42627A04UL)) +#define bFM_INTREQ_IRQ115MON_HSSPIINT2 *((volatile uint8_t *)(0x42627A08UL)) +#define bFM4_INTREQ_IRQ115MON_HSSPIINT2 *((volatile uint8_t *)(0x42627A08UL)) + +#define bFM_INTREQ_IRQ117MON_I2SINT *((volatile uint8_t *)(0x42627B00UL)) +#define bFM4_INTREQ_IRQ117MON_I2SINT *((volatile uint8_t *)(0x42627B00UL)) +#define bFM_INTREQ_IRQ117MON_PCRC *((volatile uint8_t *)(0x42627B04UL)) +#define bFM4_INTREQ_IRQ117MON_PCRC *((volatile uint8_t *)(0x42627B04UL)) + +#define bFM_INTREQ_IRQ118MON_SDINT0 *((volatile uint8_t *)(0x42627B80UL)) +#define bFM4_INTREQ_IRQ118MON_SDINT0 *((volatile uint8_t *)(0x42627B80UL)) +#define bFM_INTREQ_IRQ118MON_SDINT1 *((volatile uint8_t *)(0x42627B84UL)) +#define bFM4_INTREQ_IRQ118MON_SDINT1 *((volatile uint8_t *)(0x42627B84UL)) + +#define bFM_INTREQ_IRQ119MON_FLINT *((volatile uint8_t *)(0x42627C00UL)) +#define bFM4_INTREQ_IRQ119MON_FLINT *((volatile uint8_t *)(0x42627C00UL)) + +#define bFM_INTREQ_IRQ120MON_MFSINT12_RX *((volatile uint8_t *)(0x42627C80UL)) +#define bFM4_INTREQ_IRQ120MON_MFSINT12_RX *((volatile uint8_t *)(0x42627C80UL)) + +#define bFM_INTREQ_IRQ121MON_MFSINT12_TX *((volatile uint8_t *)(0x42627D00UL)) +#define bFM4_INTREQ_IRQ121MON_MFSINT12_TX *((volatile uint8_t *)(0x42627D00UL)) +#define bFM_INTREQ_IRQ121MON_MFSINT12_STATUS *((volatile uint8_t *)(0x42627D04UL)) +#define bFM4_INTREQ_IRQ121MON_MFSINT12_STATUS *((volatile uint8_t *)(0x42627D04UL)) + +#define bFM_INTREQ_IRQ122MON_MFSINT13_RX *((volatile uint8_t *)(0x42627D80UL)) +#define bFM4_INTREQ_IRQ122MON_MFSINT13_RX *((volatile uint8_t *)(0x42627D80UL)) + +#define bFM_INTREQ_IRQ123MON_MFSINT13_TX *((volatile uint8_t *)(0x42627E00UL)) +#define bFM4_INTREQ_IRQ123MON_MFSINT13_TX *((volatile uint8_t *)(0x42627E00UL)) +#define bFM_INTREQ_IRQ123MON_MFSINT13_STATUS *((volatile uint8_t *)(0x42627E04UL)) +#define bFM4_INTREQ_IRQ123MON_MFSINT13_STATUS *((volatile uint8_t *)(0x42627E04UL)) + +#define bFM_INTREQ_IRQ124MON_MFSINT14_RX *((volatile uint8_t *)(0x42627E80UL)) +#define bFM4_INTREQ_IRQ124MON_MFSINT14_RX *((volatile uint8_t *)(0x42627E80UL)) + +#define bFM_INTREQ_IRQ125MON_MFSINT14_TX *((volatile uint8_t *)(0x42627F00UL)) +#define bFM4_INTREQ_IRQ125MON_MFSINT14_TX *((volatile uint8_t *)(0x42627F00UL)) +#define bFM_INTREQ_IRQ125MON_MFSINT14_STATUS *((volatile uint8_t *)(0x42627F04UL)) +#define bFM4_INTREQ_IRQ125MON_MFSINT14_STATUS *((volatile uint8_t *)(0x42627F04UL)) + +#define bFM_INTREQ_IRQ126MON_MFSINT15_RX *((volatile uint8_t *)(0x42627F80UL)) +#define bFM4_INTREQ_IRQ126MON_MFSINT15_RX *((volatile uint8_t *)(0x42627F80UL)) + +#define bFM_INTREQ_IRQ127MON_MFSINT15_TX *((volatile uint8_t *)(0x42628000UL)) +#define bFM4_INTREQ_IRQ127MON_MFSINT15_TX *((volatile uint8_t *)(0x42628000UL)) +#define bFM_INTREQ_IRQ127MON_MFSINT15_STATUS *((volatile uint8_t *)(0x42628004UL)) +#define bFM4_INTREQ_IRQ127MON_MFSINT15_STATUS *((volatile uint8_t *)(0x42628004UL)) + +#define bFM_INTREQ_ODDPKS_ODDPKS0 *((volatile uint8_t *)(0x42620200UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS0 *((volatile uint8_t *)(0x42620200UL)) +#define bFM_INTREQ_ODDPKS_ODDPKS1 *((volatile uint8_t *)(0x42620204UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS1 *((volatile uint8_t *)(0x42620204UL)) +#define bFM_INTREQ_ODDPKS_ODDPKS2 *((volatile uint8_t *)(0x42620208UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS2 *((volatile uint8_t *)(0x42620208UL)) +#define bFM_INTREQ_ODDPKS_ODDPKS3 *((volatile uint8_t *)(0x4262020CUL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS3 *((volatile uint8_t *)(0x4262020CUL)) +#define bFM_INTREQ_ODDPKS_ODDPKS4 *((volatile uint8_t *)(0x42620210UL)) +#define bFM4_INTREQ_ODDPKS_ODDPKS4 *((volatile uint8_t *)(0x42620210UL)) + +#define bFM_INTREQ_ODDPKS1_ODDPKS10 *((volatile uint8_t *)(0x42620280UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS10 *((volatile uint8_t *)(0x42620280UL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS11 *((volatile uint8_t *)(0x42620284UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS11 *((volatile uint8_t *)(0x42620284UL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS12 *((volatile uint8_t *)(0x42620288UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS12 *((volatile uint8_t *)(0x42620288UL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS13 *((volatile uint8_t *)(0x4262028CUL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS13 *((volatile uint8_t *)(0x4262028CUL)) +#define bFM_INTREQ_ODDPKS1_ODDPKS14 *((volatile uint8_t *)(0x42620290UL)) +#define bFM4_INTREQ_ODDPKS1_ODDPKS14 *((volatile uint8_t *)(0x42620290UL)) + + +/******************************************************************************* +* LSCRP Registers LSCRP +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* LVD Registers LVD +* Bitband Section +*******************************************************************************/ +#define bFM_LVD_LVD_CLR_LVDCL *((volatile uint8_t *)(0x426A011CUL)) +#define bFM4_LVD_LVD_CLR_LVDCL *((volatile uint8_t *)(0x426A011CUL)) + +#define bFM_LVD_LVD_CTL_LVDIE *((volatile uint8_t *)(0x426A001CUL)) +#define bFM4_LVD_LVD_CTL_LVDIE *((volatile uint8_t *)(0x426A001CUL)) + +#define bFM_LVD_LVD_STR_LVDIR *((volatile uint8_t *)(0x426A009CUL)) +#define bFM4_LVD_LVD_STR_LVDIR *((volatile uint8_t *)(0x426A009CUL)) + +#define bFM_LVD_LVD_STR2_LVDIRDY *((volatile uint8_t *)(0x426A021CUL)) +#define bFM4_LVD_LVD_STR2_LVDIRDY *((volatile uint8_t *)(0x426A021CUL)) + + +/******************************************************************************* +* MFS Registers MFS0 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS0_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42700094UL)) +#define bFM4_MFS0_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42700094UL)) +#define bFM_MFS0_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42700098UL)) +#define bFM_MFS0_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270009CUL)) +#define bFM4_MFS0_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270009CUL)) + +#define bFM_MFS0_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_CSIO_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_CSIO_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_CSIO_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_CSIO_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_CSIO_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_CSIO_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42700480UL)) +#define bFM4_MFS0_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42700480UL)) +#define bFM_MFS0_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42700498UL)) +#define bFM4_MFS0_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42700498UL)) +#define bFM_MFS0_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270049CUL)) +#define bFM4_MFS0_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270049CUL)) +#define bFM_MFS0_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427004A0UL)) +#define bFM4_MFS0_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427004A0UL)) +#define bFM_MFS0_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427004ACUL)) +#define bFM4_MFS0_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427004ACUL)) +#define bFM_MFS0_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427004B0UL)) +#define bFM4_MFS0_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427004B0UL)) +#define bFM_MFS0_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427004B4UL)) +#define bFM4_MFS0_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427004B4UL)) + +#define bFM_MFS0_CSIO_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_CSIO_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_CSIO_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_CSIO_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_CSIO_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_CSIO_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_CSIO_SCR_SPI *((volatile uint8_t *)(0x42700034UL)) +#define bFM4_MFS0_CSIO_SCR_SPI *((volatile uint8_t *)(0x42700034UL)) +#define bFM_MFS0_CSIO_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM4_MFS0_CSIO_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM_MFS0_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42700600UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42700600UL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42700604UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42700604UL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42700608UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42700608UL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270060CUL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270060CUL)) +#define bFM_MFS0_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42700610UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42700610UL)) +#define bFM_MFS0_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42700614UL)) +#define bFM4_MFS0_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42700614UL)) +#define bFM_MFS0_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42700624UL)) +#define bFM4_MFS0_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42700624UL)) + +#define bFM_MFS0_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42700694UL)) +#define bFM4_MFS0_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42700694UL)) +#define bFM_MFS0_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42700698UL)) +#define bFM4_MFS0_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42700698UL)) +#define bFM_MFS0_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270069CUL)) +#define bFM4_MFS0_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270069CUL)) + +#define bFM_MFS0_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427006B4UL)) +#define bFM4_MFS0_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427006B4UL)) +#define bFM_MFS0_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427006B8UL)) +#define bFM4_MFS0_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427006B8UL)) +#define bFM_MFS0_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427006BCUL)) +#define bFM4_MFS0_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427006BCUL)) + +#define bFM_MFS0_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42700714UL)) +#define bFM4_MFS0_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42700714UL)) +#define bFM_MFS0_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42700718UL)) +#define bFM4_MFS0_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42700718UL)) +#define bFM_MFS0_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270071CUL)) +#define bFM4_MFS0_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270071CUL)) + +#define bFM_MFS0_CSIO_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM4_MFS0_CSIO_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM_MFS0_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42700004UL)) +#define bFM4_MFS0_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42700004UL)) +#define bFM_MFS0_CSIO_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM4_MFS0_CSIO_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM_MFS0_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270000CUL)) + +#define bFM_MFS0_CSIO_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_CSIO_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_CSIO_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_CSIO_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_CSIO_SSR_AWC *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_CSIO_SSR_AWC *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_CSIO_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_CSIO_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + +#define bFM_MFS0_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427003A0UL)) +#define bFM4_MFS0_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427003A0UL)) +#define bFM_MFS0_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427003A4UL)) +#define bFM4_MFS0_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427003A4UL)) +#define bFM_MFS0_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427003A8UL)) +#define bFM4_MFS0_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427003A8UL)) +#define bFM_MFS0_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427003ACUL)) +#define bFM4_MFS0_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427003ACUL)) +#define bFM_MFS0_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427003B0UL)) +#define bFM4_MFS0_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427003B0UL)) +#define bFM_MFS0_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427003B4UL)) +#define bFM4_MFS0_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427003B4UL)) + +#define bFM_MFS0_I2C_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_I2C_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_I2C_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_I2C_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_I2C_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_I2C_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_I2C_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_I2C_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_I2C_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_I2C_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_I2C_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_I2C_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_I2C_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_I2C_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_I2C_IBCR_INT *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_I2C_IBCR_INT *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_I2C_IBCR_BER *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_I2C_IBCR_BER *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_I2C_IBCR_INTE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_I2C_IBCR_INTE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42700034UL)) +#define bFM4_MFS0_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42700034UL)) +#define bFM_MFS0_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42700038UL)) +#define bFM4_MFS0_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42700038UL)) +#define bFM_MFS0_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_I2C_IBSR_BB *((volatile uint8_t *)(0x42700080UL)) +#define bFM4_MFS0_I2C_IBSR_BB *((volatile uint8_t *)(0x42700080UL)) +#define bFM_MFS0_I2C_IBSR_SPC *((volatile uint8_t *)(0x42700084UL)) +#define bFM4_MFS0_I2C_IBSR_SPC *((volatile uint8_t *)(0x42700084UL)) +#define bFM_MFS0_I2C_IBSR_RSC *((volatile uint8_t *)(0x42700088UL)) +#define bFM4_MFS0_I2C_IBSR_RSC *((volatile uint8_t *)(0x42700088UL)) +#define bFM_MFS0_I2C_IBSR_AL *((volatile uint8_t *)(0x4270008CUL)) +#define bFM4_MFS0_I2C_IBSR_AL *((volatile uint8_t *)(0x4270008CUL)) +#define bFM_MFS0_I2C_IBSR_TRX *((volatile uint8_t *)(0x42700090UL)) +#define bFM4_MFS0_I2C_IBSR_TRX *((volatile uint8_t *)(0x42700090UL)) +#define bFM_MFS0_I2C_IBSR_RSA *((volatile uint8_t *)(0x42700094UL)) +#define bFM4_MFS0_I2C_IBSR_RSA *((volatile uint8_t *)(0x42700094UL)) +#define bFM_MFS0_I2C_IBSR_RACK *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_I2C_IBSR_RACK *((volatile uint8_t *)(0x42700098UL)) +#define bFM_MFS0_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270009CUL)) +#define bFM4_MFS0_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270009CUL)) + +#define bFM_MFS0_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270021CUL)) +#define bFM4_MFS0_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270021CUL)) + +#define bFM_MFS0_I2C_ISMK_EN *((volatile uint8_t *)(0x4270023CUL)) +#define bFM4_MFS0_I2C_ISMK_EN *((volatile uint8_t *)(0x4270023CUL)) + +#define bFM_MFS0_I2C_SMR_TIE *((volatile uint8_t *)(0x42700008UL)) +#define bFM4_MFS0_I2C_SMR_TIE *((volatile uint8_t *)(0x42700008UL)) +#define bFM_MFS0_I2C_SMR_RIE *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_I2C_SMR_RIE *((volatile uint8_t *)(0x4270000CUL)) + +#define bFM_MFS0_I2C_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_I2C_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_I2C_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_I2C_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_I2C_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_I2C_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_I2C_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_I2C_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_I2C_SSR_TBIE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_I2C_SSR_TBIE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_I2C_SSR_DMA *((volatile uint8_t *)(0x427000B4UL)) +#define bFM4_MFS0_I2C_SSR_DMA *((volatile uint8_t *)(0x427000B4UL)) +#define bFM_MFS0_I2C_SSR_TSET *((volatile uint8_t *)(0x427000B8UL)) +#define bFM4_MFS0_I2C_SSR_TSET *((volatile uint8_t *)(0x427000B8UL)) +#define bFM_MFS0_I2C_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_I2C_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + +#define bFM_MFS0_LIN_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) +#define bFM4_MFS0_LIN_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) + +#define bFM_MFS0_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42700090UL)) +#define bFM4_MFS0_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42700090UL)) +#define bFM_MFS0_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) + +#define bFM_MFS0_LIN_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_LIN_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_LIN_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_LIN_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_LIN_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_LIN_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_LIN_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_LIN_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_LIN_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_LIN_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_LIN_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_LIN_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_LIN_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_LIN_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_LIN_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_LIN_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_LIN_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_LIN_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_LIN_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_LIN_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_LIN_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_LIN_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_LIN_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_LIN_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_LIN_SCR_LBR *((volatile uint8_t *)(0x42700034UL)) +#define bFM4_MFS0_LIN_SCR_LBR *((volatile uint8_t *)(0x42700034UL)) +#define bFM_MFS0_LIN_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM4_MFS0_LIN_SCR_MS *((volatile uint8_t *)(0x42700038UL)) +#define bFM_MFS0_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_LIN_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM4_MFS0_LIN_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM_MFS0_LIN_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_LIN_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) +#define bFM_MFS0_LIN_SMR_WUCR *((volatile uint8_t *)(0x42700010UL)) +#define bFM4_MFS0_LIN_SMR_WUCR *((volatile uint8_t *)(0x42700010UL)) + +#define bFM_MFS0_LIN_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_LIN_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_LIN_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_LIN_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_LIN_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_LIN_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_LIN_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_LIN_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_LIN_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_LIN_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_LIN_SSR_LBD *((volatile uint8_t *)(0x427000B4UL)) +#define bFM4_MFS0_LIN_SSR_LBD *((volatile uint8_t *)(0x427000B4UL)) +#define bFM_MFS0_LIN_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_LIN_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + +#define bFM_MFS0_UART_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) +#define bFM4_MFS0_UART_BGR_EXT *((volatile uint8_t *)(0x427001BCUL)) + +#define bFM_MFS0_UART_ESCR_P *((volatile uint8_t *)(0x4270008CUL)) +#define bFM4_MFS0_UART_ESCR_P *((volatile uint8_t *)(0x4270008CUL)) +#define bFM_MFS0_UART_ESCR_PEN *((volatile uint8_t *)(0x42700090UL)) +#define bFM4_MFS0_UART_ESCR_PEN *((volatile uint8_t *)(0x42700090UL)) +#define bFM_MFS0_UART_ESCR_INV *((volatile uint8_t *)(0x42700094UL)) +#define bFM4_MFS0_UART_ESCR_INV *((volatile uint8_t *)(0x42700094UL)) +#define bFM_MFS0_UART_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) +#define bFM4_MFS0_UART_ESCR_ESBL *((volatile uint8_t *)(0x42700098UL)) +#define bFM_MFS0_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270009CUL)) +#define bFM4_MFS0_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270009CUL)) + +#define bFM_MFS0_UART_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM4_MFS0_UART_FCR_FE1 *((volatile uint8_t *)(0x42700280UL)) +#define bFM_MFS0_UART_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM4_MFS0_UART_FCR_FE2 *((volatile uint8_t *)(0x42700284UL)) +#define bFM_MFS0_UART_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM4_MFS0_UART_FCR_FCL1 *((volatile uint8_t *)(0x42700288UL)) +#define bFM_MFS0_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM4_MFS0_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270028CUL)) +#define bFM_MFS0_UART_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM4_MFS0_UART_FCR_FSET *((volatile uint8_t *)(0x42700290UL)) +#define bFM_MFS0_UART_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM4_MFS0_UART_FCR_FLD *((volatile uint8_t *)(0x42700294UL)) +#define bFM_MFS0_UART_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM4_MFS0_UART_FCR_FLST *((volatile uint8_t *)(0x42700298UL)) +#define bFM_MFS0_UART_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM4_MFS0_UART_FCR_FSEL *((volatile uint8_t *)(0x427002A0UL)) +#define bFM_MFS0_UART_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM4_MFS0_UART_FCR_FTIE *((volatile uint8_t *)(0x427002A4UL)) +#define bFM_MFS0_UART_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM4_MFS0_UART_FCR_FDRQ *((volatile uint8_t *)(0x427002A8UL)) +#define bFM_MFS0_UART_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM4_MFS0_UART_FCR_FRIIE *((volatile uint8_t *)(0x427002ACUL)) +#define bFM_MFS0_UART_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) +#define bFM4_MFS0_UART_FCR_FLSTE *((volatile uint8_t *)(0x427002B0UL)) + +#define bFM_MFS0_UART_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM4_MFS0_UART_SCR_TXE *((volatile uint8_t *)(0x42700020UL)) +#define bFM_MFS0_UART_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM4_MFS0_UART_SCR_RXE *((volatile uint8_t *)(0x42700024UL)) +#define bFM_MFS0_UART_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM4_MFS0_UART_SCR_TBIE *((volatile uint8_t *)(0x42700028UL)) +#define bFM_MFS0_UART_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM4_MFS0_UART_SCR_TIE *((volatile uint8_t *)(0x4270002CUL)) +#define bFM_MFS0_UART_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM4_MFS0_UART_SCR_RIE *((volatile uint8_t *)(0x42700030UL)) +#define bFM_MFS0_UART_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) +#define bFM4_MFS0_UART_SCR_UPCL *((volatile uint8_t *)(0x4270003CUL)) + +#define bFM_MFS0_UART_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM4_MFS0_UART_SMR_SOE *((volatile uint8_t *)(0x42700000UL)) +#define bFM_MFS0_UART_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM4_MFS0_UART_SMR_BDS *((volatile uint8_t *)(0x42700008UL)) +#define bFM_MFS0_UART_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) +#define bFM4_MFS0_UART_SMR_SBL *((volatile uint8_t *)(0x4270000CUL)) + +#define bFM_MFS0_UART_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM4_MFS0_UART_SSR_TBI *((volatile uint8_t *)(0x427000A0UL)) +#define bFM_MFS0_UART_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM4_MFS0_UART_SSR_TDRE *((volatile uint8_t *)(0x427000A4UL)) +#define bFM_MFS0_UART_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM4_MFS0_UART_SSR_RDRF *((volatile uint8_t *)(0x427000A8UL)) +#define bFM_MFS0_UART_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM4_MFS0_UART_SSR_ORE *((volatile uint8_t *)(0x427000ACUL)) +#define bFM_MFS0_UART_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM4_MFS0_UART_SSR_FRE *((volatile uint8_t *)(0x427000B0UL)) +#define bFM_MFS0_UART_SSR_PE *((volatile uint8_t *)(0x427000B4UL)) +#define bFM4_MFS0_UART_SSR_PE *((volatile uint8_t *)(0x427000B4UL)) +#define bFM_MFS0_UART_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) +#define bFM4_MFS0_UART_SSR_REC *((volatile uint8_t *)(0x427000BCUL)) + + +/******************************************************************************* +* MFS Registers MFS1 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS1_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42702094UL)) +#define bFM4_MFS1_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42702094UL)) +#define bFM_MFS1_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42702098UL)) +#define bFM_MFS1_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270209CUL)) +#define bFM4_MFS1_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270209CUL)) + +#define bFM_MFS1_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_CSIO_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_CSIO_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_CSIO_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_CSIO_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_CSIO_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_CSIO_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42702480UL)) +#define bFM4_MFS1_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42702480UL)) +#define bFM_MFS1_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42702498UL)) +#define bFM4_MFS1_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42702498UL)) +#define bFM_MFS1_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270249CUL)) +#define bFM4_MFS1_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270249CUL)) +#define bFM_MFS1_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427024A0UL)) +#define bFM4_MFS1_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427024A0UL)) +#define bFM_MFS1_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427024ACUL)) +#define bFM4_MFS1_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427024ACUL)) +#define bFM_MFS1_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427024B0UL)) +#define bFM4_MFS1_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427024B0UL)) +#define bFM_MFS1_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427024B4UL)) +#define bFM4_MFS1_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427024B4UL)) + +#define bFM_MFS1_CSIO_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_CSIO_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_CSIO_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_CSIO_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_CSIO_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_CSIO_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_CSIO_SCR_SPI *((volatile uint8_t *)(0x42702034UL)) +#define bFM4_MFS1_CSIO_SCR_SPI *((volatile uint8_t *)(0x42702034UL)) +#define bFM_MFS1_CSIO_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM4_MFS1_CSIO_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM_MFS1_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42702600UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42702600UL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42702604UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42702604UL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42702608UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42702608UL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270260CUL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270260CUL)) +#define bFM_MFS1_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42702610UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42702610UL)) +#define bFM_MFS1_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42702614UL)) +#define bFM4_MFS1_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42702614UL)) +#define bFM_MFS1_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42702624UL)) +#define bFM4_MFS1_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42702624UL)) + +#define bFM_MFS1_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42702694UL)) +#define bFM4_MFS1_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42702694UL)) +#define bFM_MFS1_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42702698UL)) +#define bFM4_MFS1_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42702698UL)) +#define bFM_MFS1_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270269CUL)) +#define bFM4_MFS1_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270269CUL)) + +#define bFM_MFS1_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427026B4UL)) +#define bFM4_MFS1_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427026B4UL)) +#define bFM_MFS1_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427026B8UL)) +#define bFM4_MFS1_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427026B8UL)) +#define bFM_MFS1_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427026BCUL)) +#define bFM4_MFS1_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427026BCUL)) + +#define bFM_MFS1_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42702714UL)) +#define bFM4_MFS1_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42702714UL)) +#define bFM_MFS1_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42702718UL)) +#define bFM4_MFS1_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42702718UL)) +#define bFM_MFS1_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270271CUL)) +#define bFM4_MFS1_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270271CUL)) + +#define bFM_MFS1_CSIO_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM4_MFS1_CSIO_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM_MFS1_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42702004UL)) +#define bFM4_MFS1_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42702004UL)) +#define bFM_MFS1_CSIO_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM4_MFS1_CSIO_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM_MFS1_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270200CUL)) + +#define bFM_MFS1_CSIO_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_CSIO_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_CSIO_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_CSIO_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_CSIO_SSR_AWC *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_CSIO_SSR_AWC *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_CSIO_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_CSIO_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + +#define bFM_MFS1_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427023A0UL)) +#define bFM4_MFS1_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427023A0UL)) +#define bFM_MFS1_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427023A4UL)) +#define bFM4_MFS1_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427023A4UL)) +#define bFM_MFS1_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427023A8UL)) +#define bFM4_MFS1_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427023A8UL)) +#define bFM_MFS1_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427023ACUL)) +#define bFM4_MFS1_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427023ACUL)) +#define bFM_MFS1_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427023B0UL)) +#define bFM4_MFS1_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427023B0UL)) +#define bFM_MFS1_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427023B4UL)) +#define bFM4_MFS1_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427023B4UL)) + +#define bFM_MFS1_I2C_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_I2C_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_I2C_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_I2C_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_I2C_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_I2C_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_I2C_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_I2C_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_I2C_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_I2C_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_I2C_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_I2C_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_I2C_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_I2C_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_I2C_IBCR_INT *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_I2C_IBCR_INT *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_I2C_IBCR_BER *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_I2C_IBCR_BER *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_I2C_IBCR_INTE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_I2C_IBCR_INTE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42702034UL)) +#define bFM4_MFS1_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42702034UL)) +#define bFM_MFS1_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42702038UL)) +#define bFM4_MFS1_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42702038UL)) +#define bFM_MFS1_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_I2C_IBSR_BB *((volatile uint8_t *)(0x42702080UL)) +#define bFM4_MFS1_I2C_IBSR_BB *((volatile uint8_t *)(0x42702080UL)) +#define bFM_MFS1_I2C_IBSR_SPC *((volatile uint8_t *)(0x42702084UL)) +#define bFM4_MFS1_I2C_IBSR_SPC *((volatile uint8_t *)(0x42702084UL)) +#define bFM_MFS1_I2C_IBSR_RSC *((volatile uint8_t *)(0x42702088UL)) +#define bFM4_MFS1_I2C_IBSR_RSC *((volatile uint8_t *)(0x42702088UL)) +#define bFM_MFS1_I2C_IBSR_AL *((volatile uint8_t *)(0x4270208CUL)) +#define bFM4_MFS1_I2C_IBSR_AL *((volatile uint8_t *)(0x4270208CUL)) +#define bFM_MFS1_I2C_IBSR_TRX *((volatile uint8_t *)(0x42702090UL)) +#define bFM4_MFS1_I2C_IBSR_TRX *((volatile uint8_t *)(0x42702090UL)) +#define bFM_MFS1_I2C_IBSR_RSA *((volatile uint8_t *)(0x42702094UL)) +#define bFM4_MFS1_I2C_IBSR_RSA *((volatile uint8_t *)(0x42702094UL)) +#define bFM_MFS1_I2C_IBSR_RACK *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_I2C_IBSR_RACK *((volatile uint8_t *)(0x42702098UL)) +#define bFM_MFS1_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270209CUL)) +#define bFM4_MFS1_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270209CUL)) + +#define bFM_MFS1_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270221CUL)) +#define bFM4_MFS1_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270221CUL)) + +#define bFM_MFS1_I2C_ISMK_EN *((volatile uint8_t *)(0x4270223CUL)) +#define bFM4_MFS1_I2C_ISMK_EN *((volatile uint8_t *)(0x4270223CUL)) + +#define bFM_MFS1_I2C_SMR_TIE *((volatile uint8_t *)(0x42702008UL)) +#define bFM4_MFS1_I2C_SMR_TIE *((volatile uint8_t *)(0x42702008UL)) +#define bFM_MFS1_I2C_SMR_RIE *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_I2C_SMR_RIE *((volatile uint8_t *)(0x4270200CUL)) + +#define bFM_MFS1_I2C_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_I2C_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_I2C_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_I2C_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_I2C_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_I2C_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_I2C_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_I2C_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_I2C_SSR_TBIE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_I2C_SSR_TBIE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_I2C_SSR_DMA *((volatile uint8_t *)(0x427020B4UL)) +#define bFM4_MFS1_I2C_SSR_DMA *((volatile uint8_t *)(0x427020B4UL)) +#define bFM_MFS1_I2C_SSR_TSET *((volatile uint8_t *)(0x427020B8UL)) +#define bFM4_MFS1_I2C_SSR_TSET *((volatile uint8_t *)(0x427020B8UL)) +#define bFM_MFS1_I2C_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_I2C_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + +#define bFM_MFS1_LIN_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) +#define bFM4_MFS1_LIN_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) + +#define bFM_MFS1_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42702090UL)) +#define bFM4_MFS1_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42702090UL)) +#define bFM_MFS1_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) + +#define bFM_MFS1_LIN_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_LIN_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_LIN_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_LIN_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_LIN_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_LIN_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_LIN_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_LIN_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_LIN_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_LIN_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_LIN_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_LIN_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_LIN_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_LIN_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_LIN_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_LIN_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_LIN_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_LIN_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_LIN_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_LIN_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_LIN_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_LIN_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_LIN_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_LIN_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_LIN_SCR_LBR *((volatile uint8_t *)(0x42702034UL)) +#define bFM4_MFS1_LIN_SCR_LBR *((volatile uint8_t *)(0x42702034UL)) +#define bFM_MFS1_LIN_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM4_MFS1_LIN_SCR_MS *((volatile uint8_t *)(0x42702038UL)) +#define bFM_MFS1_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_LIN_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM4_MFS1_LIN_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM_MFS1_LIN_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_LIN_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) +#define bFM_MFS1_LIN_SMR_WUCR *((volatile uint8_t *)(0x42702010UL)) +#define bFM4_MFS1_LIN_SMR_WUCR *((volatile uint8_t *)(0x42702010UL)) + +#define bFM_MFS1_LIN_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_LIN_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_LIN_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_LIN_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_LIN_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_LIN_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_LIN_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_LIN_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_LIN_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_LIN_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_LIN_SSR_LBD *((volatile uint8_t *)(0x427020B4UL)) +#define bFM4_MFS1_LIN_SSR_LBD *((volatile uint8_t *)(0x427020B4UL)) +#define bFM_MFS1_LIN_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_LIN_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + +#define bFM_MFS1_UART_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) +#define bFM4_MFS1_UART_BGR_EXT *((volatile uint8_t *)(0x427021BCUL)) + +#define bFM_MFS1_UART_ESCR_P *((volatile uint8_t *)(0x4270208CUL)) +#define bFM4_MFS1_UART_ESCR_P *((volatile uint8_t *)(0x4270208CUL)) +#define bFM_MFS1_UART_ESCR_PEN *((volatile uint8_t *)(0x42702090UL)) +#define bFM4_MFS1_UART_ESCR_PEN *((volatile uint8_t *)(0x42702090UL)) +#define bFM_MFS1_UART_ESCR_INV *((volatile uint8_t *)(0x42702094UL)) +#define bFM4_MFS1_UART_ESCR_INV *((volatile uint8_t *)(0x42702094UL)) +#define bFM_MFS1_UART_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) +#define bFM4_MFS1_UART_ESCR_ESBL *((volatile uint8_t *)(0x42702098UL)) +#define bFM_MFS1_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270209CUL)) +#define bFM4_MFS1_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270209CUL)) + +#define bFM_MFS1_UART_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM4_MFS1_UART_FCR_FE1 *((volatile uint8_t *)(0x42702280UL)) +#define bFM_MFS1_UART_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM4_MFS1_UART_FCR_FE2 *((volatile uint8_t *)(0x42702284UL)) +#define bFM_MFS1_UART_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM4_MFS1_UART_FCR_FCL1 *((volatile uint8_t *)(0x42702288UL)) +#define bFM_MFS1_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM4_MFS1_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270228CUL)) +#define bFM_MFS1_UART_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM4_MFS1_UART_FCR_FSET *((volatile uint8_t *)(0x42702290UL)) +#define bFM_MFS1_UART_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM4_MFS1_UART_FCR_FLD *((volatile uint8_t *)(0x42702294UL)) +#define bFM_MFS1_UART_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM4_MFS1_UART_FCR_FLST *((volatile uint8_t *)(0x42702298UL)) +#define bFM_MFS1_UART_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM4_MFS1_UART_FCR_FSEL *((volatile uint8_t *)(0x427022A0UL)) +#define bFM_MFS1_UART_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM4_MFS1_UART_FCR_FTIE *((volatile uint8_t *)(0x427022A4UL)) +#define bFM_MFS1_UART_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM4_MFS1_UART_FCR_FDRQ *((volatile uint8_t *)(0x427022A8UL)) +#define bFM_MFS1_UART_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM4_MFS1_UART_FCR_FRIIE *((volatile uint8_t *)(0x427022ACUL)) +#define bFM_MFS1_UART_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) +#define bFM4_MFS1_UART_FCR_FLSTE *((volatile uint8_t *)(0x427022B0UL)) + +#define bFM_MFS1_UART_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM4_MFS1_UART_SCR_TXE *((volatile uint8_t *)(0x42702020UL)) +#define bFM_MFS1_UART_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM4_MFS1_UART_SCR_RXE *((volatile uint8_t *)(0x42702024UL)) +#define bFM_MFS1_UART_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM4_MFS1_UART_SCR_TBIE *((volatile uint8_t *)(0x42702028UL)) +#define bFM_MFS1_UART_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM4_MFS1_UART_SCR_TIE *((volatile uint8_t *)(0x4270202CUL)) +#define bFM_MFS1_UART_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM4_MFS1_UART_SCR_RIE *((volatile uint8_t *)(0x42702030UL)) +#define bFM_MFS1_UART_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) +#define bFM4_MFS1_UART_SCR_UPCL *((volatile uint8_t *)(0x4270203CUL)) + +#define bFM_MFS1_UART_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM4_MFS1_UART_SMR_SOE *((volatile uint8_t *)(0x42702000UL)) +#define bFM_MFS1_UART_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM4_MFS1_UART_SMR_BDS *((volatile uint8_t *)(0x42702008UL)) +#define bFM_MFS1_UART_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) +#define bFM4_MFS1_UART_SMR_SBL *((volatile uint8_t *)(0x4270200CUL)) + +#define bFM_MFS1_UART_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM4_MFS1_UART_SSR_TBI *((volatile uint8_t *)(0x427020A0UL)) +#define bFM_MFS1_UART_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM4_MFS1_UART_SSR_TDRE *((volatile uint8_t *)(0x427020A4UL)) +#define bFM_MFS1_UART_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM4_MFS1_UART_SSR_RDRF *((volatile uint8_t *)(0x427020A8UL)) +#define bFM_MFS1_UART_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM4_MFS1_UART_SSR_ORE *((volatile uint8_t *)(0x427020ACUL)) +#define bFM_MFS1_UART_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM4_MFS1_UART_SSR_FRE *((volatile uint8_t *)(0x427020B0UL)) +#define bFM_MFS1_UART_SSR_PE *((volatile uint8_t *)(0x427020B4UL)) +#define bFM4_MFS1_UART_SSR_PE *((volatile uint8_t *)(0x427020B4UL)) +#define bFM_MFS1_UART_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) +#define bFM4_MFS1_UART_SSR_REC *((volatile uint8_t *)(0x427020BCUL)) + + +/******************************************************************************* +* MFS Registers MFS10 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS10_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42714094UL)) +#define bFM4_MFS10_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42714094UL)) +#define bFM_MFS10_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42714098UL)) +#define bFM_MFS10_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271409CUL)) +#define bFM4_MFS10_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271409CUL)) + +#define bFM_MFS10_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_CSIO_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_CSIO_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_CSIO_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_CSIO_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_CSIO_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_CSIO_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42714480UL)) +#define bFM4_MFS10_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42714480UL)) +#define bFM_MFS10_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42714498UL)) +#define bFM4_MFS10_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42714498UL)) +#define bFM_MFS10_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271449CUL)) +#define bFM4_MFS10_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271449CUL)) +#define bFM_MFS10_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427144A0UL)) +#define bFM4_MFS10_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427144A0UL)) +#define bFM_MFS10_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427144ACUL)) +#define bFM4_MFS10_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427144ACUL)) +#define bFM_MFS10_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427144B0UL)) +#define bFM4_MFS10_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427144B0UL)) +#define bFM_MFS10_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427144B4UL)) +#define bFM4_MFS10_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427144B4UL)) + +#define bFM_MFS10_CSIO_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_CSIO_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_CSIO_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_CSIO_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_CSIO_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_CSIO_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_CSIO_SCR_SPI *((volatile uint8_t *)(0x42714034UL)) +#define bFM4_MFS10_CSIO_SCR_SPI *((volatile uint8_t *)(0x42714034UL)) +#define bFM_MFS10_CSIO_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM4_MFS10_CSIO_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM_MFS10_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42714600UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42714600UL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42714604UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42714604UL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42714608UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42714608UL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271460CUL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271460CUL)) +#define bFM_MFS10_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42714610UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42714610UL)) +#define bFM_MFS10_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42714614UL)) +#define bFM4_MFS10_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42714614UL)) +#define bFM_MFS10_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42714624UL)) +#define bFM4_MFS10_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42714624UL)) + +#define bFM_MFS10_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42714694UL)) +#define bFM4_MFS10_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42714694UL)) +#define bFM_MFS10_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42714698UL)) +#define bFM4_MFS10_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42714698UL)) +#define bFM_MFS10_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271469CUL)) +#define bFM4_MFS10_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271469CUL)) + +#define bFM_MFS10_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427146B4UL)) +#define bFM4_MFS10_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427146B4UL)) +#define bFM_MFS10_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427146B8UL)) +#define bFM4_MFS10_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427146B8UL)) +#define bFM_MFS10_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427146BCUL)) +#define bFM4_MFS10_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427146BCUL)) + +#define bFM_MFS10_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42714714UL)) +#define bFM4_MFS10_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42714714UL)) +#define bFM_MFS10_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42714718UL)) +#define bFM4_MFS10_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42714718UL)) +#define bFM_MFS10_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271471CUL)) +#define bFM4_MFS10_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271471CUL)) + +#define bFM_MFS10_CSIO_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM4_MFS10_CSIO_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM_MFS10_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42714004UL)) +#define bFM4_MFS10_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42714004UL)) +#define bFM_MFS10_CSIO_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM4_MFS10_CSIO_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM_MFS10_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271400CUL)) + +#define bFM_MFS10_CSIO_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_CSIO_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_CSIO_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_CSIO_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_CSIO_SSR_AWC *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_CSIO_SSR_AWC *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_CSIO_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_CSIO_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + +#define bFM_MFS10_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427143A0UL)) +#define bFM4_MFS10_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427143A0UL)) +#define bFM_MFS10_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427143A4UL)) +#define bFM4_MFS10_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427143A4UL)) +#define bFM_MFS10_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427143A8UL)) +#define bFM4_MFS10_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427143A8UL)) +#define bFM_MFS10_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427143ACUL)) +#define bFM4_MFS10_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427143ACUL)) +#define bFM_MFS10_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427143B0UL)) +#define bFM4_MFS10_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427143B0UL)) +#define bFM_MFS10_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427143B4UL)) +#define bFM4_MFS10_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427143B4UL)) + +#define bFM_MFS10_I2C_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_I2C_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_I2C_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_I2C_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_I2C_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_I2C_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_I2C_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_I2C_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_I2C_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_I2C_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_I2C_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_I2C_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_I2C_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_I2C_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_I2C_IBCR_INT *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_I2C_IBCR_INT *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_I2C_IBCR_BER *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_I2C_IBCR_BER *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_I2C_IBCR_INTE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_I2C_IBCR_INTE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42714034UL)) +#define bFM4_MFS10_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42714034UL)) +#define bFM_MFS10_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42714038UL)) +#define bFM4_MFS10_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42714038UL)) +#define bFM_MFS10_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_I2C_IBSR_BB *((volatile uint8_t *)(0x42714080UL)) +#define bFM4_MFS10_I2C_IBSR_BB *((volatile uint8_t *)(0x42714080UL)) +#define bFM_MFS10_I2C_IBSR_SPC *((volatile uint8_t *)(0x42714084UL)) +#define bFM4_MFS10_I2C_IBSR_SPC *((volatile uint8_t *)(0x42714084UL)) +#define bFM_MFS10_I2C_IBSR_RSC *((volatile uint8_t *)(0x42714088UL)) +#define bFM4_MFS10_I2C_IBSR_RSC *((volatile uint8_t *)(0x42714088UL)) +#define bFM_MFS10_I2C_IBSR_AL *((volatile uint8_t *)(0x4271408CUL)) +#define bFM4_MFS10_I2C_IBSR_AL *((volatile uint8_t *)(0x4271408CUL)) +#define bFM_MFS10_I2C_IBSR_TRX *((volatile uint8_t *)(0x42714090UL)) +#define bFM4_MFS10_I2C_IBSR_TRX *((volatile uint8_t *)(0x42714090UL)) +#define bFM_MFS10_I2C_IBSR_RSA *((volatile uint8_t *)(0x42714094UL)) +#define bFM4_MFS10_I2C_IBSR_RSA *((volatile uint8_t *)(0x42714094UL)) +#define bFM_MFS10_I2C_IBSR_RACK *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_I2C_IBSR_RACK *((volatile uint8_t *)(0x42714098UL)) +#define bFM_MFS10_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271409CUL)) +#define bFM4_MFS10_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271409CUL)) + +#define bFM_MFS10_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271421CUL)) +#define bFM4_MFS10_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271421CUL)) + +#define bFM_MFS10_I2C_ISMK_EN *((volatile uint8_t *)(0x4271423CUL)) +#define bFM4_MFS10_I2C_ISMK_EN *((volatile uint8_t *)(0x4271423CUL)) + +#define bFM_MFS10_I2C_SMR_TIE *((volatile uint8_t *)(0x42714008UL)) +#define bFM4_MFS10_I2C_SMR_TIE *((volatile uint8_t *)(0x42714008UL)) +#define bFM_MFS10_I2C_SMR_RIE *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_I2C_SMR_RIE *((volatile uint8_t *)(0x4271400CUL)) + +#define bFM_MFS10_I2C_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_I2C_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_I2C_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_I2C_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_I2C_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_I2C_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_I2C_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_I2C_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_I2C_SSR_TBIE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_I2C_SSR_TBIE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_I2C_SSR_DMA *((volatile uint8_t *)(0x427140B4UL)) +#define bFM4_MFS10_I2C_SSR_DMA *((volatile uint8_t *)(0x427140B4UL)) +#define bFM_MFS10_I2C_SSR_TSET *((volatile uint8_t *)(0x427140B8UL)) +#define bFM4_MFS10_I2C_SSR_TSET *((volatile uint8_t *)(0x427140B8UL)) +#define bFM_MFS10_I2C_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_I2C_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + +#define bFM_MFS10_LIN_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) +#define bFM4_MFS10_LIN_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) + +#define bFM_MFS10_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42714090UL)) +#define bFM4_MFS10_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42714090UL)) +#define bFM_MFS10_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) + +#define bFM_MFS10_LIN_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_LIN_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_LIN_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_LIN_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_LIN_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_LIN_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_LIN_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_LIN_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_LIN_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_LIN_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_LIN_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_LIN_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_LIN_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_LIN_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_LIN_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_LIN_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_LIN_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_LIN_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_LIN_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_LIN_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_LIN_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_LIN_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_LIN_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_LIN_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_LIN_SCR_LBR *((volatile uint8_t *)(0x42714034UL)) +#define bFM4_MFS10_LIN_SCR_LBR *((volatile uint8_t *)(0x42714034UL)) +#define bFM_MFS10_LIN_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM4_MFS10_LIN_SCR_MS *((volatile uint8_t *)(0x42714038UL)) +#define bFM_MFS10_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_LIN_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM4_MFS10_LIN_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM_MFS10_LIN_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_LIN_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) +#define bFM_MFS10_LIN_SMR_WUCR *((volatile uint8_t *)(0x42714010UL)) +#define bFM4_MFS10_LIN_SMR_WUCR *((volatile uint8_t *)(0x42714010UL)) + +#define bFM_MFS10_LIN_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_LIN_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_LIN_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_LIN_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_LIN_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_LIN_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_LIN_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_LIN_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_LIN_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_LIN_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_LIN_SSR_LBD *((volatile uint8_t *)(0x427140B4UL)) +#define bFM4_MFS10_LIN_SSR_LBD *((volatile uint8_t *)(0x427140B4UL)) +#define bFM_MFS10_LIN_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_LIN_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + +#define bFM_MFS10_UART_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) +#define bFM4_MFS10_UART_BGR_EXT *((volatile uint8_t *)(0x427141BCUL)) + +#define bFM_MFS10_UART_ESCR_P *((volatile uint8_t *)(0x4271408CUL)) +#define bFM4_MFS10_UART_ESCR_P *((volatile uint8_t *)(0x4271408CUL)) +#define bFM_MFS10_UART_ESCR_PEN *((volatile uint8_t *)(0x42714090UL)) +#define bFM4_MFS10_UART_ESCR_PEN *((volatile uint8_t *)(0x42714090UL)) +#define bFM_MFS10_UART_ESCR_INV *((volatile uint8_t *)(0x42714094UL)) +#define bFM4_MFS10_UART_ESCR_INV *((volatile uint8_t *)(0x42714094UL)) +#define bFM_MFS10_UART_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) +#define bFM4_MFS10_UART_ESCR_ESBL *((volatile uint8_t *)(0x42714098UL)) +#define bFM_MFS10_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271409CUL)) +#define bFM4_MFS10_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271409CUL)) + +#define bFM_MFS10_UART_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM4_MFS10_UART_FCR_FE1 *((volatile uint8_t *)(0x42714280UL)) +#define bFM_MFS10_UART_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM4_MFS10_UART_FCR_FE2 *((volatile uint8_t *)(0x42714284UL)) +#define bFM_MFS10_UART_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM4_MFS10_UART_FCR_FCL1 *((volatile uint8_t *)(0x42714288UL)) +#define bFM_MFS10_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM4_MFS10_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271428CUL)) +#define bFM_MFS10_UART_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM4_MFS10_UART_FCR_FSET *((volatile uint8_t *)(0x42714290UL)) +#define bFM_MFS10_UART_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM4_MFS10_UART_FCR_FLD *((volatile uint8_t *)(0x42714294UL)) +#define bFM_MFS10_UART_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM4_MFS10_UART_FCR_FLST *((volatile uint8_t *)(0x42714298UL)) +#define bFM_MFS10_UART_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM4_MFS10_UART_FCR_FSEL *((volatile uint8_t *)(0x427142A0UL)) +#define bFM_MFS10_UART_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM4_MFS10_UART_FCR_FTIE *((volatile uint8_t *)(0x427142A4UL)) +#define bFM_MFS10_UART_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM4_MFS10_UART_FCR_FDRQ *((volatile uint8_t *)(0x427142A8UL)) +#define bFM_MFS10_UART_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM4_MFS10_UART_FCR_FRIIE *((volatile uint8_t *)(0x427142ACUL)) +#define bFM_MFS10_UART_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) +#define bFM4_MFS10_UART_FCR_FLSTE *((volatile uint8_t *)(0x427142B0UL)) + +#define bFM_MFS10_UART_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM4_MFS10_UART_SCR_TXE *((volatile uint8_t *)(0x42714020UL)) +#define bFM_MFS10_UART_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM4_MFS10_UART_SCR_RXE *((volatile uint8_t *)(0x42714024UL)) +#define bFM_MFS10_UART_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM4_MFS10_UART_SCR_TBIE *((volatile uint8_t *)(0x42714028UL)) +#define bFM_MFS10_UART_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM4_MFS10_UART_SCR_TIE *((volatile uint8_t *)(0x4271402CUL)) +#define bFM_MFS10_UART_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM4_MFS10_UART_SCR_RIE *((volatile uint8_t *)(0x42714030UL)) +#define bFM_MFS10_UART_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) +#define bFM4_MFS10_UART_SCR_UPCL *((volatile uint8_t *)(0x4271403CUL)) + +#define bFM_MFS10_UART_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM4_MFS10_UART_SMR_SOE *((volatile uint8_t *)(0x42714000UL)) +#define bFM_MFS10_UART_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM4_MFS10_UART_SMR_BDS *((volatile uint8_t *)(0x42714008UL)) +#define bFM_MFS10_UART_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) +#define bFM4_MFS10_UART_SMR_SBL *((volatile uint8_t *)(0x4271400CUL)) + +#define bFM_MFS10_UART_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM4_MFS10_UART_SSR_TBI *((volatile uint8_t *)(0x427140A0UL)) +#define bFM_MFS10_UART_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM4_MFS10_UART_SSR_TDRE *((volatile uint8_t *)(0x427140A4UL)) +#define bFM_MFS10_UART_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM4_MFS10_UART_SSR_RDRF *((volatile uint8_t *)(0x427140A8UL)) +#define bFM_MFS10_UART_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM4_MFS10_UART_SSR_ORE *((volatile uint8_t *)(0x427140ACUL)) +#define bFM_MFS10_UART_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM4_MFS10_UART_SSR_FRE *((volatile uint8_t *)(0x427140B0UL)) +#define bFM_MFS10_UART_SSR_PE *((volatile uint8_t *)(0x427140B4UL)) +#define bFM4_MFS10_UART_SSR_PE *((volatile uint8_t *)(0x427140B4UL)) +#define bFM_MFS10_UART_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) +#define bFM4_MFS10_UART_SSR_REC *((volatile uint8_t *)(0x427140BCUL)) + + +/******************************************************************************* +* MFS Registers MFS11 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS11_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42716094UL)) +#define bFM4_MFS11_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42716094UL)) +#define bFM_MFS11_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42716098UL)) +#define bFM_MFS11_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271609CUL)) +#define bFM4_MFS11_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271609CUL)) + +#define bFM_MFS11_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_CSIO_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_CSIO_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_CSIO_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_CSIO_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_CSIO_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_CSIO_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42716480UL)) +#define bFM4_MFS11_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42716480UL)) +#define bFM_MFS11_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42716498UL)) +#define bFM4_MFS11_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42716498UL)) +#define bFM_MFS11_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271649CUL)) +#define bFM4_MFS11_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271649CUL)) +#define bFM_MFS11_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427164A0UL)) +#define bFM4_MFS11_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427164A0UL)) +#define bFM_MFS11_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427164ACUL)) +#define bFM4_MFS11_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427164ACUL)) +#define bFM_MFS11_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427164B0UL)) +#define bFM4_MFS11_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427164B0UL)) +#define bFM_MFS11_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427164B4UL)) +#define bFM4_MFS11_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427164B4UL)) + +#define bFM_MFS11_CSIO_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_CSIO_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_CSIO_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_CSIO_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_CSIO_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_CSIO_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_CSIO_SCR_SPI *((volatile uint8_t *)(0x42716034UL)) +#define bFM4_MFS11_CSIO_SCR_SPI *((volatile uint8_t *)(0x42716034UL)) +#define bFM_MFS11_CSIO_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM4_MFS11_CSIO_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM_MFS11_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42716600UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42716600UL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42716604UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42716604UL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42716608UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42716608UL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271660CUL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271660CUL)) +#define bFM_MFS11_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42716610UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42716610UL)) +#define bFM_MFS11_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42716614UL)) +#define bFM4_MFS11_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42716614UL)) +#define bFM_MFS11_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42716624UL)) +#define bFM4_MFS11_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42716624UL)) + +#define bFM_MFS11_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42716694UL)) +#define bFM4_MFS11_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42716694UL)) +#define bFM_MFS11_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42716698UL)) +#define bFM4_MFS11_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42716698UL)) +#define bFM_MFS11_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271669CUL)) +#define bFM4_MFS11_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271669CUL)) + +#define bFM_MFS11_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427166B4UL)) +#define bFM4_MFS11_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427166B4UL)) +#define bFM_MFS11_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427166B8UL)) +#define bFM4_MFS11_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427166B8UL)) +#define bFM_MFS11_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427166BCUL)) +#define bFM4_MFS11_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427166BCUL)) + +#define bFM_MFS11_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42716714UL)) +#define bFM4_MFS11_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42716714UL)) +#define bFM_MFS11_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42716718UL)) +#define bFM4_MFS11_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42716718UL)) +#define bFM_MFS11_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271671CUL)) +#define bFM4_MFS11_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271671CUL)) + +#define bFM_MFS11_CSIO_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM4_MFS11_CSIO_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM_MFS11_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42716004UL)) +#define bFM4_MFS11_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42716004UL)) +#define bFM_MFS11_CSIO_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM4_MFS11_CSIO_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM_MFS11_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271600CUL)) + +#define bFM_MFS11_CSIO_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_CSIO_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_CSIO_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_CSIO_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_CSIO_SSR_AWC *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_CSIO_SSR_AWC *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_CSIO_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_CSIO_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + +#define bFM_MFS11_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427163A0UL)) +#define bFM4_MFS11_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427163A0UL)) +#define bFM_MFS11_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427163A4UL)) +#define bFM4_MFS11_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427163A4UL)) +#define bFM_MFS11_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427163A8UL)) +#define bFM4_MFS11_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427163A8UL)) +#define bFM_MFS11_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427163ACUL)) +#define bFM4_MFS11_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427163ACUL)) +#define bFM_MFS11_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427163B0UL)) +#define bFM4_MFS11_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427163B0UL)) +#define bFM_MFS11_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427163B4UL)) +#define bFM4_MFS11_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427163B4UL)) + +#define bFM_MFS11_I2C_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_I2C_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_I2C_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_I2C_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_I2C_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_I2C_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_I2C_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_I2C_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_I2C_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_I2C_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_I2C_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_I2C_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_I2C_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_I2C_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_I2C_IBCR_INT *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_I2C_IBCR_INT *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_I2C_IBCR_BER *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_I2C_IBCR_BER *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_I2C_IBCR_INTE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_I2C_IBCR_INTE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42716034UL)) +#define bFM4_MFS11_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42716034UL)) +#define bFM_MFS11_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42716038UL)) +#define bFM4_MFS11_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42716038UL)) +#define bFM_MFS11_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_I2C_IBSR_BB *((volatile uint8_t *)(0x42716080UL)) +#define bFM4_MFS11_I2C_IBSR_BB *((volatile uint8_t *)(0x42716080UL)) +#define bFM_MFS11_I2C_IBSR_SPC *((volatile uint8_t *)(0x42716084UL)) +#define bFM4_MFS11_I2C_IBSR_SPC *((volatile uint8_t *)(0x42716084UL)) +#define bFM_MFS11_I2C_IBSR_RSC *((volatile uint8_t *)(0x42716088UL)) +#define bFM4_MFS11_I2C_IBSR_RSC *((volatile uint8_t *)(0x42716088UL)) +#define bFM_MFS11_I2C_IBSR_AL *((volatile uint8_t *)(0x4271608CUL)) +#define bFM4_MFS11_I2C_IBSR_AL *((volatile uint8_t *)(0x4271608CUL)) +#define bFM_MFS11_I2C_IBSR_TRX *((volatile uint8_t *)(0x42716090UL)) +#define bFM4_MFS11_I2C_IBSR_TRX *((volatile uint8_t *)(0x42716090UL)) +#define bFM_MFS11_I2C_IBSR_RSA *((volatile uint8_t *)(0x42716094UL)) +#define bFM4_MFS11_I2C_IBSR_RSA *((volatile uint8_t *)(0x42716094UL)) +#define bFM_MFS11_I2C_IBSR_RACK *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_I2C_IBSR_RACK *((volatile uint8_t *)(0x42716098UL)) +#define bFM_MFS11_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271609CUL)) +#define bFM4_MFS11_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271609CUL)) + +#define bFM_MFS11_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271621CUL)) +#define bFM4_MFS11_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271621CUL)) + +#define bFM_MFS11_I2C_ISMK_EN *((volatile uint8_t *)(0x4271623CUL)) +#define bFM4_MFS11_I2C_ISMK_EN *((volatile uint8_t *)(0x4271623CUL)) + +#define bFM_MFS11_I2C_SMR_TIE *((volatile uint8_t *)(0x42716008UL)) +#define bFM4_MFS11_I2C_SMR_TIE *((volatile uint8_t *)(0x42716008UL)) +#define bFM_MFS11_I2C_SMR_RIE *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_I2C_SMR_RIE *((volatile uint8_t *)(0x4271600CUL)) + +#define bFM_MFS11_I2C_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_I2C_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_I2C_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_I2C_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_I2C_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_I2C_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_I2C_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_I2C_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_I2C_SSR_TBIE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_I2C_SSR_TBIE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_I2C_SSR_DMA *((volatile uint8_t *)(0x427160B4UL)) +#define bFM4_MFS11_I2C_SSR_DMA *((volatile uint8_t *)(0x427160B4UL)) +#define bFM_MFS11_I2C_SSR_TSET *((volatile uint8_t *)(0x427160B8UL)) +#define bFM4_MFS11_I2C_SSR_TSET *((volatile uint8_t *)(0x427160B8UL)) +#define bFM_MFS11_I2C_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_I2C_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + +#define bFM_MFS11_LIN_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) +#define bFM4_MFS11_LIN_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) + +#define bFM_MFS11_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42716090UL)) +#define bFM4_MFS11_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42716090UL)) +#define bFM_MFS11_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) + +#define bFM_MFS11_LIN_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_LIN_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_LIN_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_LIN_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_LIN_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_LIN_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_LIN_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_LIN_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_LIN_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_LIN_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_LIN_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_LIN_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_LIN_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_LIN_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_LIN_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_LIN_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_LIN_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_LIN_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_LIN_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_LIN_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_LIN_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_LIN_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_LIN_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_LIN_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_LIN_SCR_LBR *((volatile uint8_t *)(0x42716034UL)) +#define bFM4_MFS11_LIN_SCR_LBR *((volatile uint8_t *)(0x42716034UL)) +#define bFM_MFS11_LIN_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM4_MFS11_LIN_SCR_MS *((volatile uint8_t *)(0x42716038UL)) +#define bFM_MFS11_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_LIN_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM4_MFS11_LIN_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM_MFS11_LIN_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_LIN_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) +#define bFM_MFS11_LIN_SMR_WUCR *((volatile uint8_t *)(0x42716010UL)) +#define bFM4_MFS11_LIN_SMR_WUCR *((volatile uint8_t *)(0x42716010UL)) + +#define bFM_MFS11_LIN_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_LIN_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_LIN_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_LIN_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_LIN_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_LIN_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_LIN_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_LIN_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_LIN_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_LIN_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_LIN_SSR_LBD *((volatile uint8_t *)(0x427160B4UL)) +#define bFM4_MFS11_LIN_SSR_LBD *((volatile uint8_t *)(0x427160B4UL)) +#define bFM_MFS11_LIN_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_LIN_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + +#define bFM_MFS11_UART_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) +#define bFM4_MFS11_UART_BGR_EXT *((volatile uint8_t *)(0x427161BCUL)) + +#define bFM_MFS11_UART_ESCR_P *((volatile uint8_t *)(0x4271608CUL)) +#define bFM4_MFS11_UART_ESCR_P *((volatile uint8_t *)(0x4271608CUL)) +#define bFM_MFS11_UART_ESCR_PEN *((volatile uint8_t *)(0x42716090UL)) +#define bFM4_MFS11_UART_ESCR_PEN *((volatile uint8_t *)(0x42716090UL)) +#define bFM_MFS11_UART_ESCR_INV *((volatile uint8_t *)(0x42716094UL)) +#define bFM4_MFS11_UART_ESCR_INV *((volatile uint8_t *)(0x42716094UL)) +#define bFM_MFS11_UART_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) +#define bFM4_MFS11_UART_ESCR_ESBL *((volatile uint8_t *)(0x42716098UL)) +#define bFM_MFS11_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271609CUL)) +#define bFM4_MFS11_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271609CUL)) + +#define bFM_MFS11_UART_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM4_MFS11_UART_FCR_FE1 *((volatile uint8_t *)(0x42716280UL)) +#define bFM_MFS11_UART_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM4_MFS11_UART_FCR_FE2 *((volatile uint8_t *)(0x42716284UL)) +#define bFM_MFS11_UART_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM4_MFS11_UART_FCR_FCL1 *((volatile uint8_t *)(0x42716288UL)) +#define bFM_MFS11_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM4_MFS11_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271628CUL)) +#define bFM_MFS11_UART_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM4_MFS11_UART_FCR_FSET *((volatile uint8_t *)(0x42716290UL)) +#define bFM_MFS11_UART_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM4_MFS11_UART_FCR_FLD *((volatile uint8_t *)(0x42716294UL)) +#define bFM_MFS11_UART_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM4_MFS11_UART_FCR_FLST *((volatile uint8_t *)(0x42716298UL)) +#define bFM_MFS11_UART_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM4_MFS11_UART_FCR_FSEL *((volatile uint8_t *)(0x427162A0UL)) +#define bFM_MFS11_UART_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM4_MFS11_UART_FCR_FTIE *((volatile uint8_t *)(0x427162A4UL)) +#define bFM_MFS11_UART_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM4_MFS11_UART_FCR_FDRQ *((volatile uint8_t *)(0x427162A8UL)) +#define bFM_MFS11_UART_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM4_MFS11_UART_FCR_FRIIE *((volatile uint8_t *)(0x427162ACUL)) +#define bFM_MFS11_UART_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) +#define bFM4_MFS11_UART_FCR_FLSTE *((volatile uint8_t *)(0x427162B0UL)) + +#define bFM_MFS11_UART_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM4_MFS11_UART_SCR_TXE *((volatile uint8_t *)(0x42716020UL)) +#define bFM_MFS11_UART_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM4_MFS11_UART_SCR_RXE *((volatile uint8_t *)(0x42716024UL)) +#define bFM_MFS11_UART_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM4_MFS11_UART_SCR_TBIE *((volatile uint8_t *)(0x42716028UL)) +#define bFM_MFS11_UART_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM4_MFS11_UART_SCR_TIE *((volatile uint8_t *)(0x4271602CUL)) +#define bFM_MFS11_UART_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM4_MFS11_UART_SCR_RIE *((volatile uint8_t *)(0x42716030UL)) +#define bFM_MFS11_UART_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) +#define bFM4_MFS11_UART_SCR_UPCL *((volatile uint8_t *)(0x4271603CUL)) + +#define bFM_MFS11_UART_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM4_MFS11_UART_SMR_SOE *((volatile uint8_t *)(0x42716000UL)) +#define bFM_MFS11_UART_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM4_MFS11_UART_SMR_BDS *((volatile uint8_t *)(0x42716008UL)) +#define bFM_MFS11_UART_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) +#define bFM4_MFS11_UART_SMR_SBL *((volatile uint8_t *)(0x4271600CUL)) + +#define bFM_MFS11_UART_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM4_MFS11_UART_SSR_TBI *((volatile uint8_t *)(0x427160A0UL)) +#define bFM_MFS11_UART_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM4_MFS11_UART_SSR_TDRE *((volatile uint8_t *)(0x427160A4UL)) +#define bFM_MFS11_UART_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM4_MFS11_UART_SSR_RDRF *((volatile uint8_t *)(0x427160A8UL)) +#define bFM_MFS11_UART_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM4_MFS11_UART_SSR_ORE *((volatile uint8_t *)(0x427160ACUL)) +#define bFM_MFS11_UART_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM4_MFS11_UART_SSR_FRE *((volatile uint8_t *)(0x427160B0UL)) +#define bFM_MFS11_UART_SSR_PE *((volatile uint8_t *)(0x427160B4UL)) +#define bFM4_MFS11_UART_SSR_PE *((volatile uint8_t *)(0x427160B4UL)) +#define bFM_MFS11_UART_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) +#define bFM4_MFS11_UART_SSR_REC *((volatile uint8_t *)(0x427160BCUL)) + + +/******************************************************************************* +* MFS Registers MFS12 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS12_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42718094UL)) +#define bFM4_MFS12_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42718094UL)) +#define bFM_MFS12_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42718098UL)) +#define bFM_MFS12_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271809CUL)) +#define bFM4_MFS12_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271809CUL)) + +#define bFM_MFS12_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_CSIO_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_CSIO_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_CSIO_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_CSIO_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_CSIO_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_CSIO_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42718480UL)) +#define bFM4_MFS12_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42718480UL)) +#define bFM_MFS12_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42718498UL)) +#define bFM4_MFS12_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42718498UL)) +#define bFM_MFS12_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271849CUL)) +#define bFM4_MFS12_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271849CUL)) +#define bFM_MFS12_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427184A0UL)) +#define bFM4_MFS12_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427184A0UL)) +#define bFM_MFS12_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427184ACUL)) +#define bFM4_MFS12_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427184ACUL)) +#define bFM_MFS12_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427184B0UL)) +#define bFM4_MFS12_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427184B0UL)) +#define bFM_MFS12_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427184B4UL)) +#define bFM4_MFS12_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427184B4UL)) + +#define bFM_MFS12_CSIO_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_CSIO_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_CSIO_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_CSIO_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_CSIO_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_CSIO_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_CSIO_SCR_SPI *((volatile uint8_t *)(0x42718034UL)) +#define bFM4_MFS12_CSIO_SCR_SPI *((volatile uint8_t *)(0x42718034UL)) +#define bFM_MFS12_CSIO_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM4_MFS12_CSIO_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM_MFS12_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42718600UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42718600UL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42718604UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42718604UL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42718608UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42718608UL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271860CUL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271860CUL)) +#define bFM_MFS12_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42718610UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42718610UL)) +#define bFM_MFS12_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42718614UL)) +#define bFM4_MFS12_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42718614UL)) +#define bFM_MFS12_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42718624UL)) +#define bFM4_MFS12_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42718624UL)) + +#define bFM_MFS12_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42718694UL)) +#define bFM4_MFS12_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42718694UL)) +#define bFM_MFS12_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42718698UL)) +#define bFM4_MFS12_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42718698UL)) +#define bFM_MFS12_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271869CUL)) +#define bFM4_MFS12_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271869CUL)) + +#define bFM_MFS12_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427186B4UL)) +#define bFM4_MFS12_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427186B4UL)) +#define bFM_MFS12_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427186B8UL)) +#define bFM4_MFS12_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427186B8UL)) +#define bFM_MFS12_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427186BCUL)) +#define bFM4_MFS12_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427186BCUL)) + +#define bFM_MFS12_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42718714UL)) +#define bFM4_MFS12_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42718714UL)) +#define bFM_MFS12_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42718718UL)) +#define bFM4_MFS12_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42718718UL)) +#define bFM_MFS12_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271871CUL)) +#define bFM4_MFS12_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271871CUL)) + +#define bFM_MFS12_CSIO_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM4_MFS12_CSIO_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM_MFS12_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42718004UL)) +#define bFM4_MFS12_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42718004UL)) +#define bFM_MFS12_CSIO_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM4_MFS12_CSIO_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM_MFS12_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271800CUL)) + +#define bFM_MFS12_CSIO_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_CSIO_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_CSIO_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_CSIO_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_CSIO_SSR_AWC *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_CSIO_SSR_AWC *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_CSIO_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_CSIO_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + +#define bFM_MFS12_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427183A0UL)) +#define bFM4_MFS12_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427183A0UL)) +#define bFM_MFS12_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427183A4UL)) +#define bFM4_MFS12_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427183A4UL)) +#define bFM_MFS12_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427183A8UL)) +#define bFM4_MFS12_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427183A8UL)) +#define bFM_MFS12_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427183ACUL)) +#define bFM4_MFS12_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427183ACUL)) +#define bFM_MFS12_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427183B0UL)) +#define bFM4_MFS12_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427183B0UL)) +#define bFM_MFS12_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427183B4UL)) +#define bFM4_MFS12_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427183B4UL)) + +#define bFM_MFS12_I2C_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_I2C_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_I2C_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_I2C_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_I2C_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_I2C_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_I2C_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_I2C_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_I2C_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_I2C_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_I2C_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_I2C_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_I2C_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_I2C_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_I2C_IBCR_INT *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_I2C_IBCR_INT *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_I2C_IBCR_BER *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_I2C_IBCR_BER *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_I2C_IBCR_INTE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_I2C_IBCR_INTE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42718034UL)) +#define bFM4_MFS12_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42718034UL)) +#define bFM_MFS12_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42718038UL)) +#define bFM4_MFS12_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42718038UL)) +#define bFM_MFS12_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_I2C_IBSR_BB *((volatile uint8_t *)(0x42718080UL)) +#define bFM4_MFS12_I2C_IBSR_BB *((volatile uint8_t *)(0x42718080UL)) +#define bFM_MFS12_I2C_IBSR_SPC *((volatile uint8_t *)(0x42718084UL)) +#define bFM4_MFS12_I2C_IBSR_SPC *((volatile uint8_t *)(0x42718084UL)) +#define bFM_MFS12_I2C_IBSR_RSC *((volatile uint8_t *)(0x42718088UL)) +#define bFM4_MFS12_I2C_IBSR_RSC *((volatile uint8_t *)(0x42718088UL)) +#define bFM_MFS12_I2C_IBSR_AL *((volatile uint8_t *)(0x4271808CUL)) +#define bFM4_MFS12_I2C_IBSR_AL *((volatile uint8_t *)(0x4271808CUL)) +#define bFM_MFS12_I2C_IBSR_TRX *((volatile uint8_t *)(0x42718090UL)) +#define bFM4_MFS12_I2C_IBSR_TRX *((volatile uint8_t *)(0x42718090UL)) +#define bFM_MFS12_I2C_IBSR_RSA *((volatile uint8_t *)(0x42718094UL)) +#define bFM4_MFS12_I2C_IBSR_RSA *((volatile uint8_t *)(0x42718094UL)) +#define bFM_MFS12_I2C_IBSR_RACK *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_I2C_IBSR_RACK *((volatile uint8_t *)(0x42718098UL)) +#define bFM_MFS12_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271809CUL)) +#define bFM4_MFS12_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271809CUL)) + +#define bFM_MFS12_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271821CUL)) +#define bFM4_MFS12_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271821CUL)) + +#define bFM_MFS12_I2C_ISMK_EN *((volatile uint8_t *)(0x4271823CUL)) +#define bFM4_MFS12_I2C_ISMK_EN *((volatile uint8_t *)(0x4271823CUL)) + +#define bFM_MFS12_I2C_SMR_TIE *((volatile uint8_t *)(0x42718008UL)) +#define bFM4_MFS12_I2C_SMR_TIE *((volatile uint8_t *)(0x42718008UL)) +#define bFM_MFS12_I2C_SMR_RIE *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_I2C_SMR_RIE *((volatile uint8_t *)(0x4271800CUL)) + +#define bFM_MFS12_I2C_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_I2C_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_I2C_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_I2C_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_I2C_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_I2C_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_I2C_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_I2C_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_I2C_SSR_TBIE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_I2C_SSR_TBIE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_I2C_SSR_DMA *((volatile uint8_t *)(0x427180B4UL)) +#define bFM4_MFS12_I2C_SSR_DMA *((volatile uint8_t *)(0x427180B4UL)) +#define bFM_MFS12_I2C_SSR_TSET *((volatile uint8_t *)(0x427180B8UL)) +#define bFM4_MFS12_I2C_SSR_TSET *((volatile uint8_t *)(0x427180B8UL)) +#define bFM_MFS12_I2C_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_I2C_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + +#define bFM_MFS12_LIN_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) +#define bFM4_MFS12_LIN_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) + +#define bFM_MFS12_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42718090UL)) +#define bFM4_MFS12_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42718090UL)) +#define bFM_MFS12_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) + +#define bFM_MFS12_LIN_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_LIN_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_LIN_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_LIN_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_LIN_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_LIN_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_LIN_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_LIN_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_LIN_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_LIN_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_LIN_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_LIN_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_LIN_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_LIN_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_LIN_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_LIN_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_LIN_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_LIN_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_LIN_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_LIN_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_LIN_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_LIN_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_LIN_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_LIN_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_LIN_SCR_LBR *((volatile uint8_t *)(0x42718034UL)) +#define bFM4_MFS12_LIN_SCR_LBR *((volatile uint8_t *)(0x42718034UL)) +#define bFM_MFS12_LIN_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM4_MFS12_LIN_SCR_MS *((volatile uint8_t *)(0x42718038UL)) +#define bFM_MFS12_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_LIN_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM4_MFS12_LIN_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM_MFS12_LIN_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_LIN_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) +#define bFM_MFS12_LIN_SMR_WUCR *((volatile uint8_t *)(0x42718010UL)) +#define bFM4_MFS12_LIN_SMR_WUCR *((volatile uint8_t *)(0x42718010UL)) + +#define bFM_MFS12_LIN_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_LIN_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_LIN_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_LIN_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_LIN_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_LIN_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_LIN_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_LIN_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_LIN_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_LIN_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_LIN_SSR_LBD *((volatile uint8_t *)(0x427180B4UL)) +#define bFM4_MFS12_LIN_SSR_LBD *((volatile uint8_t *)(0x427180B4UL)) +#define bFM_MFS12_LIN_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_LIN_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + +#define bFM_MFS12_UART_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) +#define bFM4_MFS12_UART_BGR_EXT *((volatile uint8_t *)(0x427181BCUL)) + +#define bFM_MFS12_UART_ESCR_P *((volatile uint8_t *)(0x4271808CUL)) +#define bFM4_MFS12_UART_ESCR_P *((volatile uint8_t *)(0x4271808CUL)) +#define bFM_MFS12_UART_ESCR_PEN *((volatile uint8_t *)(0x42718090UL)) +#define bFM4_MFS12_UART_ESCR_PEN *((volatile uint8_t *)(0x42718090UL)) +#define bFM_MFS12_UART_ESCR_INV *((volatile uint8_t *)(0x42718094UL)) +#define bFM4_MFS12_UART_ESCR_INV *((volatile uint8_t *)(0x42718094UL)) +#define bFM_MFS12_UART_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) +#define bFM4_MFS12_UART_ESCR_ESBL *((volatile uint8_t *)(0x42718098UL)) +#define bFM_MFS12_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271809CUL)) +#define bFM4_MFS12_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271809CUL)) + +#define bFM_MFS12_UART_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM4_MFS12_UART_FCR_FE1 *((volatile uint8_t *)(0x42718280UL)) +#define bFM_MFS12_UART_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM4_MFS12_UART_FCR_FE2 *((volatile uint8_t *)(0x42718284UL)) +#define bFM_MFS12_UART_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM4_MFS12_UART_FCR_FCL1 *((volatile uint8_t *)(0x42718288UL)) +#define bFM_MFS12_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM4_MFS12_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271828CUL)) +#define bFM_MFS12_UART_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM4_MFS12_UART_FCR_FSET *((volatile uint8_t *)(0x42718290UL)) +#define bFM_MFS12_UART_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM4_MFS12_UART_FCR_FLD *((volatile uint8_t *)(0x42718294UL)) +#define bFM_MFS12_UART_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM4_MFS12_UART_FCR_FLST *((volatile uint8_t *)(0x42718298UL)) +#define bFM_MFS12_UART_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM4_MFS12_UART_FCR_FSEL *((volatile uint8_t *)(0x427182A0UL)) +#define bFM_MFS12_UART_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM4_MFS12_UART_FCR_FTIE *((volatile uint8_t *)(0x427182A4UL)) +#define bFM_MFS12_UART_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM4_MFS12_UART_FCR_FDRQ *((volatile uint8_t *)(0x427182A8UL)) +#define bFM_MFS12_UART_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM4_MFS12_UART_FCR_FRIIE *((volatile uint8_t *)(0x427182ACUL)) +#define bFM_MFS12_UART_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) +#define bFM4_MFS12_UART_FCR_FLSTE *((volatile uint8_t *)(0x427182B0UL)) + +#define bFM_MFS12_UART_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM4_MFS12_UART_SCR_TXE *((volatile uint8_t *)(0x42718020UL)) +#define bFM_MFS12_UART_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM4_MFS12_UART_SCR_RXE *((volatile uint8_t *)(0x42718024UL)) +#define bFM_MFS12_UART_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM4_MFS12_UART_SCR_TBIE *((volatile uint8_t *)(0x42718028UL)) +#define bFM_MFS12_UART_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM4_MFS12_UART_SCR_TIE *((volatile uint8_t *)(0x4271802CUL)) +#define bFM_MFS12_UART_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM4_MFS12_UART_SCR_RIE *((volatile uint8_t *)(0x42718030UL)) +#define bFM_MFS12_UART_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) +#define bFM4_MFS12_UART_SCR_UPCL *((volatile uint8_t *)(0x4271803CUL)) + +#define bFM_MFS12_UART_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM4_MFS12_UART_SMR_SOE *((volatile uint8_t *)(0x42718000UL)) +#define bFM_MFS12_UART_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM4_MFS12_UART_SMR_BDS *((volatile uint8_t *)(0x42718008UL)) +#define bFM_MFS12_UART_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) +#define bFM4_MFS12_UART_SMR_SBL *((volatile uint8_t *)(0x4271800CUL)) + +#define bFM_MFS12_UART_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM4_MFS12_UART_SSR_TBI *((volatile uint8_t *)(0x427180A0UL)) +#define bFM_MFS12_UART_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM4_MFS12_UART_SSR_TDRE *((volatile uint8_t *)(0x427180A4UL)) +#define bFM_MFS12_UART_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM4_MFS12_UART_SSR_RDRF *((volatile uint8_t *)(0x427180A8UL)) +#define bFM_MFS12_UART_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM4_MFS12_UART_SSR_ORE *((volatile uint8_t *)(0x427180ACUL)) +#define bFM_MFS12_UART_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM4_MFS12_UART_SSR_FRE *((volatile uint8_t *)(0x427180B0UL)) +#define bFM_MFS12_UART_SSR_PE *((volatile uint8_t *)(0x427180B4UL)) +#define bFM4_MFS12_UART_SSR_PE *((volatile uint8_t *)(0x427180B4UL)) +#define bFM_MFS12_UART_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) +#define bFM4_MFS12_UART_SSR_REC *((volatile uint8_t *)(0x427180BCUL)) + + +/******************************************************************************* +* MFS Registers MFS13 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS13_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271A094UL)) +#define bFM4_MFS13_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271A094UL)) +#define bFM_MFS13_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271A098UL)) +#define bFM_MFS13_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271A09CUL)) +#define bFM4_MFS13_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271A09CUL)) + +#define bFM_MFS13_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271A480UL)) +#define bFM4_MFS13_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271A480UL)) +#define bFM_MFS13_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271A498UL)) +#define bFM4_MFS13_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271A498UL)) +#define bFM_MFS13_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271A49CUL)) +#define bFM4_MFS13_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271A49CUL)) +#define bFM_MFS13_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271A4A0UL)) +#define bFM4_MFS13_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271A4A0UL)) +#define bFM_MFS13_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271A4ACUL)) +#define bFM4_MFS13_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271A4ACUL)) +#define bFM_MFS13_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271A4B0UL)) +#define bFM4_MFS13_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271A4B0UL)) +#define bFM_MFS13_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271A4B4UL)) +#define bFM4_MFS13_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271A4B4UL)) + +#define bFM_MFS13_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271A034UL)) +#define bFM4_MFS13_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271A034UL)) +#define bFM_MFS13_CSIO_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM4_MFS13_CSIO_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM_MFS13_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271A600UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271A600UL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271A604UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271A604UL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271A608UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271A608UL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271A60CUL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271A60CUL)) +#define bFM_MFS13_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271A610UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271A610UL)) +#define bFM_MFS13_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271A614UL)) +#define bFM4_MFS13_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271A614UL)) +#define bFM_MFS13_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271A624UL)) +#define bFM4_MFS13_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271A624UL)) + +#define bFM_MFS13_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271A694UL)) +#define bFM4_MFS13_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271A694UL)) +#define bFM_MFS13_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271A698UL)) +#define bFM4_MFS13_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271A698UL)) +#define bFM_MFS13_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271A69CUL)) +#define bFM4_MFS13_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271A69CUL)) + +#define bFM_MFS13_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271A6B4UL)) +#define bFM4_MFS13_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271A6B4UL)) +#define bFM_MFS13_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271A6B8UL)) +#define bFM4_MFS13_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271A6B8UL)) +#define bFM_MFS13_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271A6BCUL)) +#define bFM4_MFS13_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271A6BCUL)) + +#define bFM_MFS13_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271A714UL)) +#define bFM4_MFS13_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271A714UL)) +#define bFM_MFS13_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271A718UL)) +#define bFM4_MFS13_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271A718UL)) +#define bFM_MFS13_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271A71CUL)) +#define bFM4_MFS13_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271A71CUL)) + +#define bFM_MFS13_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM4_MFS13_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM_MFS13_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271A004UL)) +#define bFM4_MFS13_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271A004UL)) +#define bFM_MFS13_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM4_MFS13_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM_MFS13_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271A00CUL)) + +#define bFM_MFS13_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_CSIO_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_CSIO_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + +#define bFM_MFS13_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271A3A0UL)) +#define bFM4_MFS13_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271A3A0UL)) +#define bFM_MFS13_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271A3A4UL)) +#define bFM4_MFS13_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271A3A4UL)) +#define bFM_MFS13_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271A3A8UL)) +#define bFM4_MFS13_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271A3A8UL)) +#define bFM_MFS13_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271A3ACUL)) +#define bFM4_MFS13_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271A3ACUL)) +#define bFM_MFS13_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271A3B0UL)) +#define bFM4_MFS13_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271A3B0UL)) +#define bFM_MFS13_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271A3B4UL)) +#define bFM4_MFS13_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271A3B4UL)) + +#define bFM_MFS13_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_I2C_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_I2C_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_I2C_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_I2C_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_I2C_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_I2C_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_I2C_IBCR_INT *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_I2C_IBCR_INT *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_I2C_IBCR_BER *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_I2C_IBCR_BER *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271A034UL)) +#define bFM4_MFS13_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271A034UL)) +#define bFM_MFS13_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271A038UL)) +#define bFM4_MFS13_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271A038UL)) +#define bFM_MFS13_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_I2C_IBSR_BB *((volatile uint8_t *)(0x4271A080UL)) +#define bFM4_MFS13_I2C_IBSR_BB *((volatile uint8_t *)(0x4271A080UL)) +#define bFM_MFS13_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271A084UL)) +#define bFM4_MFS13_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271A084UL)) +#define bFM_MFS13_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271A088UL)) +#define bFM4_MFS13_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271A088UL)) +#define bFM_MFS13_I2C_IBSR_AL *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM4_MFS13_I2C_IBSR_AL *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM_MFS13_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271A090UL)) +#define bFM4_MFS13_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271A090UL)) +#define bFM_MFS13_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271A094UL)) +#define bFM4_MFS13_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271A094UL)) +#define bFM_MFS13_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271A098UL)) +#define bFM_MFS13_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271A09CUL)) +#define bFM4_MFS13_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271A09CUL)) + +#define bFM_MFS13_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271A21CUL)) +#define bFM4_MFS13_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271A21CUL)) + +#define bFM_MFS13_I2C_ISMK_EN *((volatile uint8_t *)(0x4271A23CUL)) +#define bFM4_MFS13_I2C_ISMK_EN *((volatile uint8_t *)(0x4271A23CUL)) + +#define bFM_MFS13_I2C_SMR_TIE *((volatile uint8_t *)(0x4271A008UL)) +#define bFM4_MFS13_I2C_SMR_TIE *((volatile uint8_t *)(0x4271A008UL)) +#define bFM_MFS13_I2C_SMR_RIE *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_I2C_SMR_RIE *((volatile uint8_t *)(0x4271A00CUL)) + +#define bFM_MFS13_I2C_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_I2C_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_I2C_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_I2C_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_I2C_SSR_DMA *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM4_MFS13_I2C_SSR_DMA *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM_MFS13_I2C_SSR_TSET *((volatile uint8_t *)(0x4271A0B8UL)) +#define bFM4_MFS13_I2C_SSR_TSET *((volatile uint8_t *)(0x4271A0B8UL)) +#define bFM_MFS13_I2C_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_I2C_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + +#define bFM_MFS13_LIN_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) +#define bFM4_MFS13_LIN_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) + +#define bFM_MFS13_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271A090UL)) +#define bFM4_MFS13_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271A090UL)) +#define bFM_MFS13_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) + +#define bFM_MFS13_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_LIN_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_LIN_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_LIN_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_LIN_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_LIN_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_LIN_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_LIN_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_LIN_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_LIN_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_LIN_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_LIN_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_LIN_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_LIN_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_LIN_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_LIN_SCR_LBR *((volatile uint8_t *)(0x4271A034UL)) +#define bFM4_MFS13_LIN_SCR_LBR *((volatile uint8_t *)(0x4271A034UL)) +#define bFM_MFS13_LIN_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM4_MFS13_LIN_SCR_MS *((volatile uint8_t *)(0x4271A038UL)) +#define bFM_MFS13_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_LIN_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM4_MFS13_LIN_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM_MFS13_LIN_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_LIN_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM_MFS13_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271A010UL)) +#define bFM4_MFS13_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271A010UL)) + +#define bFM_MFS13_LIN_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_LIN_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_LIN_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_LIN_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_LIN_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_LIN_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_LIN_SSR_LBD *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM4_MFS13_LIN_SSR_LBD *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM_MFS13_LIN_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_LIN_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + +#define bFM_MFS13_UART_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) +#define bFM4_MFS13_UART_BGR_EXT *((volatile uint8_t *)(0x4271A1BCUL)) + +#define bFM_MFS13_UART_ESCR_P *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM4_MFS13_UART_ESCR_P *((volatile uint8_t *)(0x4271A08CUL)) +#define bFM_MFS13_UART_ESCR_PEN *((volatile uint8_t *)(0x4271A090UL)) +#define bFM4_MFS13_UART_ESCR_PEN *((volatile uint8_t *)(0x4271A090UL)) +#define bFM_MFS13_UART_ESCR_INV *((volatile uint8_t *)(0x4271A094UL)) +#define bFM4_MFS13_UART_ESCR_INV *((volatile uint8_t *)(0x4271A094UL)) +#define bFM_MFS13_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) +#define bFM4_MFS13_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271A098UL)) +#define bFM_MFS13_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271A09CUL)) +#define bFM4_MFS13_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271A09CUL)) + +#define bFM_MFS13_UART_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM4_MFS13_UART_FCR_FE1 *((volatile uint8_t *)(0x4271A280UL)) +#define bFM_MFS13_UART_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM4_MFS13_UART_FCR_FE2 *((volatile uint8_t *)(0x4271A284UL)) +#define bFM_MFS13_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM4_MFS13_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271A288UL)) +#define bFM_MFS13_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM4_MFS13_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271A28CUL)) +#define bFM_MFS13_UART_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM4_MFS13_UART_FCR_FSET *((volatile uint8_t *)(0x4271A290UL)) +#define bFM_MFS13_UART_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM4_MFS13_UART_FCR_FLD *((volatile uint8_t *)(0x4271A294UL)) +#define bFM_MFS13_UART_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM4_MFS13_UART_FCR_FLST *((volatile uint8_t *)(0x4271A298UL)) +#define bFM_MFS13_UART_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM4_MFS13_UART_FCR_FSEL *((volatile uint8_t *)(0x4271A2A0UL)) +#define bFM_MFS13_UART_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM4_MFS13_UART_FCR_FTIE *((volatile uint8_t *)(0x4271A2A4UL)) +#define bFM_MFS13_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM4_MFS13_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271A2A8UL)) +#define bFM_MFS13_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM4_MFS13_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271A2ACUL)) +#define bFM_MFS13_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) +#define bFM4_MFS13_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271A2B0UL)) + +#define bFM_MFS13_UART_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM4_MFS13_UART_SCR_TXE *((volatile uint8_t *)(0x4271A020UL)) +#define bFM_MFS13_UART_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM4_MFS13_UART_SCR_RXE *((volatile uint8_t *)(0x4271A024UL)) +#define bFM_MFS13_UART_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM4_MFS13_UART_SCR_TBIE *((volatile uint8_t *)(0x4271A028UL)) +#define bFM_MFS13_UART_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM4_MFS13_UART_SCR_TIE *((volatile uint8_t *)(0x4271A02CUL)) +#define bFM_MFS13_UART_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM4_MFS13_UART_SCR_RIE *((volatile uint8_t *)(0x4271A030UL)) +#define bFM_MFS13_UART_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) +#define bFM4_MFS13_UART_SCR_UPCL *((volatile uint8_t *)(0x4271A03CUL)) + +#define bFM_MFS13_UART_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM4_MFS13_UART_SMR_SOE *((volatile uint8_t *)(0x4271A000UL)) +#define bFM_MFS13_UART_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM4_MFS13_UART_SMR_BDS *((volatile uint8_t *)(0x4271A008UL)) +#define bFM_MFS13_UART_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) +#define bFM4_MFS13_UART_SMR_SBL *((volatile uint8_t *)(0x4271A00CUL)) + +#define bFM_MFS13_UART_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM4_MFS13_UART_SSR_TBI *((volatile uint8_t *)(0x4271A0A0UL)) +#define bFM_MFS13_UART_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM4_MFS13_UART_SSR_TDRE *((volatile uint8_t *)(0x4271A0A4UL)) +#define bFM_MFS13_UART_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM4_MFS13_UART_SSR_RDRF *((volatile uint8_t *)(0x4271A0A8UL)) +#define bFM_MFS13_UART_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM4_MFS13_UART_SSR_ORE *((volatile uint8_t *)(0x4271A0ACUL)) +#define bFM_MFS13_UART_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM4_MFS13_UART_SSR_FRE *((volatile uint8_t *)(0x4271A0B0UL)) +#define bFM_MFS13_UART_SSR_PE *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM4_MFS13_UART_SSR_PE *((volatile uint8_t *)(0x4271A0B4UL)) +#define bFM_MFS13_UART_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) +#define bFM4_MFS13_UART_SSR_REC *((volatile uint8_t *)(0x4271A0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS14 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS14_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271C094UL)) +#define bFM4_MFS14_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271C094UL)) +#define bFM_MFS14_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271C098UL)) +#define bFM_MFS14_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271C09CUL)) +#define bFM4_MFS14_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271C09CUL)) + +#define bFM_MFS14_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271C480UL)) +#define bFM4_MFS14_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271C480UL)) +#define bFM_MFS14_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271C498UL)) +#define bFM4_MFS14_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271C498UL)) +#define bFM_MFS14_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271C49CUL)) +#define bFM4_MFS14_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271C49CUL)) +#define bFM_MFS14_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271C4A0UL)) +#define bFM4_MFS14_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271C4A0UL)) +#define bFM_MFS14_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271C4ACUL)) +#define bFM4_MFS14_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271C4ACUL)) +#define bFM_MFS14_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271C4B0UL)) +#define bFM4_MFS14_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271C4B0UL)) +#define bFM_MFS14_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271C4B4UL)) +#define bFM4_MFS14_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271C4B4UL)) + +#define bFM_MFS14_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271C034UL)) +#define bFM4_MFS14_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271C034UL)) +#define bFM_MFS14_CSIO_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM4_MFS14_CSIO_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM_MFS14_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271C600UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271C600UL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271C604UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271C604UL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271C608UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271C608UL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271C60CUL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271C60CUL)) +#define bFM_MFS14_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271C610UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271C610UL)) +#define bFM_MFS14_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271C614UL)) +#define bFM4_MFS14_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271C614UL)) +#define bFM_MFS14_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271C624UL)) +#define bFM4_MFS14_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271C624UL)) + +#define bFM_MFS14_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271C694UL)) +#define bFM4_MFS14_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271C694UL)) +#define bFM_MFS14_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271C698UL)) +#define bFM4_MFS14_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271C698UL)) +#define bFM_MFS14_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271C69CUL)) +#define bFM4_MFS14_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271C69CUL)) + +#define bFM_MFS14_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271C6B4UL)) +#define bFM4_MFS14_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271C6B4UL)) +#define bFM_MFS14_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271C6B8UL)) +#define bFM4_MFS14_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271C6B8UL)) +#define bFM_MFS14_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271C6BCUL)) +#define bFM4_MFS14_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271C6BCUL)) + +#define bFM_MFS14_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271C714UL)) +#define bFM4_MFS14_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271C714UL)) +#define bFM_MFS14_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271C718UL)) +#define bFM4_MFS14_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271C718UL)) +#define bFM_MFS14_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271C71CUL)) +#define bFM4_MFS14_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271C71CUL)) + +#define bFM_MFS14_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM4_MFS14_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM_MFS14_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271C004UL)) +#define bFM4_MFS14_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271C004UL)) +#define bFM_MFS14_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM4_MFS14_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM_MFS14_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271C00CUL)) + +#define bFM_MFS14_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_CSIO_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_CSIO_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + +#define bFM_MFS14_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271C3A0UL)) +#define bFM4_MFS14_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271C3A0UL)) +#define bFM_MFS14_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271C3A4UL)) +#define bFM4_MFS14_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271C3A4UL)) +#define bFM_MFS14_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271C3A8UL)) +#define bFM4_MFS14_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271C3A8UL)) +#define bFM_MFS14_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271C3ACUL)) +#define bFM4_MFS14_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271C3ACUL)) +#define bFM_MFS14_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271C3B0UL)) +#define bFM4_MFS14_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271C3B0UL)) +#define bFM_MFS14_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271C3B4UL)) +#define bFM4_MFS14_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271C3B4UL)) + +#define bFM_MFS14_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_I2C_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_I2C_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_I2C_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_I2C_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_I2C_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_I2C_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_I2C_IBCR_INT *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_I2C_IBCR_INT *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_I2C_IBCR_BER *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_I2C_IBCR_BER *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271C034UL)) +#define bFM4_MFS14_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271C034UL)) +#define bFM_MFS14_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271C038UL)) +#define bFM4_MFS14_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271C038UL)) +#define bFM_MFS14_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_I2C_IBSR_BB *((volatile uint8_t *)(0x4271C080UL)) +#define bFM4_MFS14_I2C_IBSR_BB *((volatile uint8_t *)(0x4271C080UL)) +#define bFM_MFS14_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271C084UL)) +#define bFM4_MFS14_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271C084UL)) +#define bFM_MFS14_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271C088UL)) +#define bFM4_MFS14_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271C088UL)) +#define bFM_MFS14_I2C_IBSR_AL *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM4_MFS14_I2C_IBSR_AL *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM_MFS14_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271C090UL)) +#define bFM4_MFS14_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271C090UL)) +#define bFM_MFS14_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271C094UL)) +#define bFM4_MFS14_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271C094UL)) +#define bFM_MFS14_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271C098UL)) +#define bFM_MFS14_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271C09CUL)) +#define bFM4_MFS14_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271C09CUL)) + +#define bFM_MFS14_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271C21CUL)) +#define bFM4_MFS14_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271C21CUL)) + +#define bFM_MFS14_I2C_ISMK_EN *((volatile uint8_t *)(0x4271C23CUL)) +#define bFM4_MFS14_I2C_ISMK_EN *((volatile uint8_t *)(0x4271C23CUL)) + +#define bFM_MFS14_I2C_SMR_TIE *((volatile uint8_t *)(0x4271C008UL)) +#define bFM4_MFS14_I2C_SMR_TIE *((volatile uint8_t *)(0x4271C008UL)) +#define bFM_MFS14_I2C_SMR_RIE *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_I2C_SMR_RIE *((volatile uint8_t *)(0x4271C00CUL)) + +#define bFM_MFS14_I2C_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_I2C_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_I2C_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_I2C_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_I2C_SSR_DMA *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM4_MFS14_I2C_SSR_DMA *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM_MFS14_I2C_SSR_TSET *((volatile uint8_t *)(0x4271C0B8UL)) +#define bFM4_MFS14_I2C_SSR_TSET *((volatile uint8_t *)(0x4271C0B8UL)) +#define bFM_MFS14_I2C_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_I2C_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + +#define bFM_MFS14_LIN_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) +#define bFM4_MFS14_LIN_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) + +#define bFM_MFS14_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271C090UL)) +#define bFM4_MFS14_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271C090UL)) +#define bFM_MFS14_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) + +#define bFM_MFS14_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_LIN_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_LIN_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_LIN_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_LIN_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_LIN_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_LIN_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_LIN_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_LIN_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_LIN_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_LIN_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_LIN_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_LIN_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_LIN_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_LIN_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_LIN_SCR_LBR *((volatile uint8_t *)(0x4271C034UL)) +#define bFM4_MFS14_LIN_SCR_LBR *((volatile uint8_t *)(0x4271C034UL)) +#define bFM_MFS14_LIN_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM4_MFS14_LIN_SCR_MS *((volatile uint8_t *)(0x4271C038UL)) +#define bFM_MFS14_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_LIN_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM4_MFS14_LIN_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM_MFS14_LIN_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_LIN_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM_MFS14_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271C010UL)) +#define bFM4_MFS14_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271C010UL)) + +#define bFM_MFS14_LIN_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_LIN_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_LIN_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_LIN_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_LIN_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_LIN_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_LIN_SSR_LBD *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM4_MFS14_LIN_SSR_LBD *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM_MFS14_LIN_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_LIN_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + +#define bFM_MFS14_UART_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) +#define bFM4_MFS14_UART_BGR_EXT *((volatile uint8_t *)(0x4271C1BCUL)) + +#define bFM_MFS14_UART_ESCR_P *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM4_MFS14_UART_ESCR_P *((volatile uint8_t *)(0x4271C08CUL)) +#define bFM_MFS14_UART_ESCR_PEN *((volatile uint8_t *)(0x4271C090UL)) +#define bFM4_MFS14_UART_ESCR_PEN *((volatile uint8_t *)(0x4271C090UL)) +#define bFM_MFS14_UART_ESCR_INV *((volatile uint8_t *)(0x4271C094UL)) +#define bFM4_MFS14_UART_ESCR_INV *((volatile uint8_t *)(0x4271C094UL)) +#define bFM_MFS14_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) +#define bFM4_MFS14_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271C098UL)) +#define bFM_MFS14_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271C09CUL)) +#define bFM4_MFS14_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271C09CUL)) + +#define bFM_MFS14_UART_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM4_MFS14_UART_FCR_FE1 *((volatile uint8_t *)(0x4271C280UL)) +#define bFM_MFS14_UART_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM4_MFS14_UART_FCR_FE2 *((volatile uint8_t *)(0x4271C284UL)) +#define bFM_MFS14_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM4_MFS14_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271C288UL)) +#define bFM_MFS14_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM4_MFS14_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271C28CUL)) +#define bFM_MFS14_UART_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM4_MFS14_UART_FCR_FSET *((volatile uint8_t *)(0x4271C290UL)) +#define bFM_MFS14_UART_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM4_MFS14_UART_FCR_FLD *((volatile uint8_t *)(0x4271C294UL)) +#define bFM_MFS14_UART_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM4_MFS14_UART_FCR_FLST *((volatile uint8_t *)(0x4271C298UL)) +#define bFM_MFS14_UART_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM4_MFS14_UART_FCR_FSEL *((volatile uint8_t *)(0x4271C2A0UL)) +#define bFM_MFS14_UART_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM4_MFS14_UART_FCR_FTIE *((volatile uint8_t *)(0x4271C2A4UL)) +#define bFM_MFS14_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM4_MFS14_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271C2A8UL)) +#define bFM_MFS14_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM4_MFS14_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271C2ACUL)) +#define bFM_MFS14_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) +#define bFM4_MFS14_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271C2B0UL)) + +#define bFM_MFS14_UART_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM4_MFS14_UART_SCR_TXE *((volatile uint8_t *)(0x4271C020UL)) +#define bFM_MFS14_UART_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM4_MFS14_UART_SCR_RXE *((volatile uint8_t *)(0x4271C024UL)) +#define bFM_MFS14_UART_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM4_MFS14_UART_SCR_TBIE *((volatile uint8_t *)(0x4271C028UL)) +#define bFM_MFS14_UART_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM4_MFS14_UART_SCR_TIE *((volatile uint8_t *)(0x4271C02CUL)) +#define bFM_MFS14_UART_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM4_MFS14_UART_SCR_RIE *((volatile uint8_t *)(0x4271C030UL)) +#define bFM_MFS14_UART_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) +#define bFM4_MFS14_UART_SCR_UPCL *((volatile uint8_t *)(0x4271C03CUL)) + +#define bFM_MFS14_UART_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM4_MFS14_UART_SMR_SOE *((volatile uint8_t *)(0x4271C000UL)) +#define bFM_MFS14_UART_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM4_MFS14_UART_SMR_BDS *((volatile uint8_t *)(0x4271C008UL)) +#define bFM_MFS14_UART_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) +#define bFM4_MFS14_UART_SMR_SBL *((volatile uint8_t *)(0x4271C00CUL)) + +#define bFM_MFS14_UART_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM4_MFS14_UART_SSR_TBI *((volatile uint8_t *)(0x4271C0A0UL)) +#define bFM_MFS14_UART_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM4_MFS14_UART_SSR_TDRE *((volatile uint8_t *)(0x4271C0A4UL)) +#define bFM_MFS14_UART_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM4_MFS14_UART_SSR_RDRF *((volatile uint8_t *)(0x4271C0A8UL)) +#define bFM_MFS14_UART_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM4_MFS14_UART_SSR_ORE *((volatile uint8_t *)(0x4271C0ACUL)) +#define bFM_MFS14_UART_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM4_MFS14_UART_SSR_FRE *((volatile uint8_t *)(0x4271C0B0UL)) +#define bFM_MFS14_UART_SSR_PE *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM4_MFS14_UART_SSR_PE *((volatile uint8_t *)(0x4271C0B4UL)) +#define bFM_MFS14_UART_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) +#define bFM4_MFS14_UART_SSR_REC *((volatile uint8_t *)(0x4271C0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS15 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS15_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271E094UL)) +#define bFM4_MFS15_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4271E094UL)) +#define bFM_MFS15_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4271E098UL)) +#define bFM_MFS15_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271E09CUL)) +#define bFM4_MFS15_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271E09CUL)) + +#define bFM_MFS15_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_CSIO_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_CSIO_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_CSIO_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271E480UL)) +#define bFM4_MFS15_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4271E480UL)) +#define bFM_MFS15_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271E498UL)) +#define bFM4_MFS15_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4271E498UL)) +#define bFM_MFS15_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271E49CUL)) +#define bFM4_MFS15_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271E49CUL)) +#define bFM_MFS15_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271E4A0UL)) +#define bFM4_MFS15_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4271E4A0UL)) +#define bFM_MFS15_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271E4ACUL)) +#define bFM4_MFS15_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4271E4ACUL)) +#define bFM_MFS15_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271E4B0UL)) +#define bFM4_MFS15_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4271E4B0UL)) +#define bFM_MFS15_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271E4B4UL)) +#define bFM4_MFS15_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4271E4B4UL)) + +#define bFM_MFS15_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_CSIO_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_CSIO_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_CSIO_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271E034UL)) +#define bFM4_MFS15_CSIO_SCR_SPI *((volatile uint8_t *)(0x4271E034UL)) +#define bFM_MFS15_CSIO_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM4_MFS15_CSIO_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM_MFS15_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271E600UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4271E600UL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271E604UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4271E604UL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271E608UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4271E608UL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271E60CUL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271E60CUL)) +#define bFM_MFS15_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271E610UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4271E610UL)) +#define bFM_MFS15_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271E614UL)) +#define bFM4_MFS15_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4271E614UL)) +#define bFM_MFS15_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271E624UL)) +#define bFM4_MFS15_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4271E624UL)) + +#define bFM_MFS15_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271E694UL)) +#define bFM4_MFS15_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4271E694UL)) +#define bFM_MFS15_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271E698UL)) +#define bFM4_MFS15_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4271E698UL)) +#define bFM_MFS15_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271E69CUL)) +#define bFM4_MFS15_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271E69CUL)) + +#define bFM_MFS15_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271E6B4UL)) +#define bFM4_MFS15_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4271E6B4UL)) +#define bFM_MFS15_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271E6B8UL)) +#define bFM4_MFS15_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4271E6B8UL)) +#define bFM_MFS15_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271E6BCUL)) +#define bFM4_MFS15_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4271E6BCUL)) + +#define bFM_MFS15_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271E714UL)) +#define bFM4_MFS15_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4271E714UL)) +#define bFM_MFS15_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271E718UL)) +#define bFM4_MFS15_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4271E718UL)) +#define bFM_MFS15_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271E71CUL)) +#define bFM4_MFS15_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271E71CUL)) + +#define bFM_MFS15_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM4_MFS15_CSIO_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM_MFS15_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271E004UL)) +#define bFM4_MFS15_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4271E004UL)) +#define bFM_MFS15_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM4_MFS15_CSIO_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM_MFS15_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271E00CUL)) + +#define bFM_MFS15_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_CSIO_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_CSIO_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_CSIO_SSR_AWC *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_CSIO_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_CSIO_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + +#define bFM_MFS15_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271E3A0UL)) +#define bFM4_MFS15_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4271E3A0UL)) +#define bFM_MFS15_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271E3A4UL)) +#define bFM4_MFS15_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4271E3A4UL)) +#define bFM_MFS15_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271E3A8UL)) +#define bFM4_MFS15_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4271E3A8UL)) +#define bFM_MFS15_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271E3ACUL)) +#define bFM4_MFS15_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4271E3ACUL)) +#define bFM_MFS15_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271E3B0UL)) +#define bFM4_MFS15_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4271E3B0UL)) +#define bFM_MFS15_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271E3B4UL)) +#define bFM4_MFS15_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4271E3B4UL)) + +#define bFM_MFS15_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_I2C_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_I2C_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_I2C_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_I2C_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_I2C_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_I2C_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_I2C_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_I2C_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_I2C_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_I2C_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_I2C_IBCR_INT *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_I2C_IBCR_INT *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_I2C_IBCR_BER *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_I2C_IBCR_BER *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_I2C_IBCR_INTE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271E034UL)) +#define bFM4_MFS15_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4271E034UL)) +#define bFM_MFS15_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271E038UL)) +#define bFM4_MFS15_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4271E038UL)) +#define bFM_MFS15_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_I2C_IBSR_BB *((volatile uint8_t *)(0x4271E080UL)) +#define bFM4_MFS15_I2C_IBSR_BB *((volatile uint8_t *)(0x4271E080UL)) +#define bFM_MFS15_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271E084UL)) +#define bFM4_MFS15_I2C_IBSR_SPC *((volatile uint8_t *)(0x4271E084UL)) +#define bFM_MFS15_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271E088UL)) +#define bFM4_MFS15_I2C_IBSR_RSC *((volatile uint8_t *)(0x4271E088UL)) +#define bFM_MFS15_I2C_IBSR_AL *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM4_MFS15_I2C_IBSR_AL *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM_MFS15_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271E090UL)) +#define bFM4_MFS15_I2C_IBSR_TRX *((volatile uint8_t *)(0x4271E090UL)) +#define bFM_MFS15_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271E094UL)) +#define bFM4_MFS15_I2C_IBSR_RSA *((volatile uint8_t *)(0x4271E094UL)) +#define bFM_MFS15_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_I2C_IBSR_RACK *((volatile uint8_t *)(0x4271E098UL)) +#define bFM_MFS15_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271E09CUL)) +#define bFM4_MFS15_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271E09CUL)) + +#define bFM_MFS15_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271E21CUL)) +#define bFM4_MFS15_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271E21CUL)) + +#define bFM_MFS15_I2C_ISMK_EN *((volatile uint8_t *)(0x4271E23CUL)) +#define bFM4_MFS15_I2C_ISMK_EN *((volatile uint8_t *)(0x4271E23CUL)) + +#define bFM_MFS15_I2C_SMR_TIE *((volatile uint8_t *)(0x4271E008UL)) +#define bFM4_MFS15_I2C_SMR_TIE *((volatile uint8_t *)(0x4271E008UL)) +#define bFM_MFS15_I2C_SMR_RIE *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_I2C_SMR_RIE *((volatile uint8_t *)(0x4271E00CUL)) + +#define bFM_MFS15_I2C_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_I2C_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_I2C_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_I2C_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_I2C_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_I2C_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_I2C_SSR_TBIE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_I2C_SSR_DMA *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM4_MFS15_I2C_SSR_DMA *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM_MFS15_I2C_SSR_TSET *((volatile uint8_t *)(0x4271E0B8UL)) +#define bFM4_MFS15_I2C_SSR_TSET *((volatile uint8_t *)(0x4271E0B8UL)) +#define bFM_MFS15_I2C_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_I2C_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + +#define bFM_MFS15_LIN_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) +#define bFM4_MFS15_LIN_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) + +#define bFM_MFS15_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271E090UL)) +#define bFM4_MFS15_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4271E090UL)) +#define bFM_MFS15_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) + +#define bFM_MFS15_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_LIN_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_LIN_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_LIN_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_LIN_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_LIN_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_LIN_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_LIN_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_LIN_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_LIN_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_LIN_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_LIN_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_LIN_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_LIN_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_LIN_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_LIN_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_LIN_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_LIN_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_LIN_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_LIN_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_LIN_SCR_LBR *((volatile uint8_t *)(0x4271E034UL)) +#define bFM4_MFS15_LIN_SCR_LBR *((volatile uint8_t *)(0x4271E034UL)) +#define bFM_MFS15_LIN_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM4_MFS15_LIN_SCR_MS *((volatile uint8_t *)(0x4271E038UL)) +#define bFM_MFS15_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_LIN_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM4_MFS15_LIN_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM_MFS15_LIN_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_LIN_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM_MFS15_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271E010UL)) +#define bFM4_MFS15_LIN_SMR_WUCR *((volatile uint8_t *)(0x4271E010UL)) + +#define bFM_MFS15_LIN_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_LIN_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_LIN_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_LIN_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_LIN_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_LIN_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_LIN_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_LIN_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_LIN_SSR_LBD *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM4_MFS15_LIN_SSR_LBD *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM_MFS15_LIN_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_LIN_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + +#define bFM_MFS15_UART_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) +#define bFM4_MFS15_UART_BGR_EXT *((volatile uint8_t *)(0x4271E1BCUL)) + +#define bFM_MFS15_UART_ESCR_P *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM4_MFS15_UART_ESCR_P *((volatile uint8_t *)(0x4271E08CUL)) +#define bFM_MFS15_UART_ESCR_PEN *((volatile uint8_t *)(0x4271E090UL)) +#define bFM4_MFS15_UART_ESCR_PEN *((volatile uint8_t *)(0x4271E090UL)) +#define bFM_MFS15_UART_ESCR_INV *((volatile uint8_t *)(0x4271E094UL)) +#define bFM4_MFS15_UART_ESCR_INV *((volatile uint8_t *)(0x4271E094UL)) +#define bFM_MFS15_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) +#define bFM4_MFS15_UART_ESCR_ESBL *((volatile uint8_t *)(0x4271E098UL)) +#define bFM_MFS15_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271E09CUL)) +#define bFM4_MFS15_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271E09CUL)) + +#define bFM_MFS15_UART_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM4_MFS15_UART_FCR_FE1 *((volatile uint8_t *)(0x4271E280UL)) +#define bFM_MFS15_UART_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM4_MFS15_UART_FCR_FE2 *((volatile uint8_t *)(0x4271E284UL)) +#define bFM_MFS15_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM4_MFS15_UART_FCR_FCL1 *((volatile uint8_t *)(0x4271E288UL)) +#define bFM_MFS15_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM4_MFS15_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271E28CUL)) +#define bFM_MFS15_UART_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM4_MFS15_UART_FCR_FSET *((volatile uint8_t *)(0x4271E290UL)) +#define bFM_MFS15_UART_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM4_MFS15_UART_FCR_FLD *((volatile uint8_t *)(0x4271E294UL)) +#define bFM_MFS15_UART_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM4_MFS15_UART_FCR_FLST *((volatile uint8_t *)(0x4271E298UL)) +#define bFM_MFS15_UART_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM4_MFS15_UART_FCR_FSEL *((volatile uint8_t *)(0x4271E2A0UL)) +#define bFM_MFS15_UART_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM4_MFS15_UART_FCR_FTIE *((volatile uint8_t *)(0x4271E2A4UL)) +#define bFM_MFS15_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM4_MFS15_UART_FCR_FDRQ *((volatile uint8_t *)(0x4271E2A8UL)) +#define bFM_MFS15_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM4_MFS15_UART_FCR_FRIIE *((volatile uint8_t *)(0x4271E2ACUL)) +#define bFM_MFS15_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) +#define bFM4_MFS15_UART_FCR_FLSTE *((volatile uint8_t *)(0x4271E2B0UL)) + +#define bFM_MFS15_UART_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM4_MFS15_UART_SCR_TXE *((volatile uint8_t *)(0x4271E020UL)) +#define bFM_MFS15_UART_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM4_MFS15_UART_SCR_RXE *((volatile uint8_t *)(0x4271E024UL)) +#define bFM_MFS15_UART_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM4_MFS15_UART_SCR_TBIE *((volatile uint8_t *)(0x4271E028UL)) +#define bFM_MFS15_UART_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM4_MFS15_UART_SCR_TIE *((volatile uint8_t *)(0x4271E02CUL)) +#define bFM_MFS15_UART_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM4_MFS15_UART_SCR_RIE *((volatile uint8_t *)(0x4271E030UL)) +#define bFM_MFS15_UART_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) +#define bFM4_MFS15_UART_SCR_UPCL *((volatile uint8_t *)(0x4271E03CUL)) + +#define bFM_MFS15_UART_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM4_MFS15_UART_SMR_SOE *((volatile uint8_t *)(0x4271E000UL)) +#define bFM_MFS15_UART_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM4_MFS15_UART_SMR_BDS *((volatile uint8_t *)(0x4271E008UL)) +#define bFM_MFS15_UART_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) +#define bFM4_MFS15_UART_SMR_SBL *((volatile uint8_t *)(0x4271E00CUL)) + +#define bFM_MFS15_UART_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM4_MFS15_UART_SSR_TBI *((volatile uint8_t *)(0x4271E0A0UL)) +#define bFM_MFS15_UART_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM4_MFS15_UART_SSR_TDRE *((volatile uint8_t *)(0x4271E0A4UL)) +#define bFM_MFS15_UART_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM4_MFS15_UART_SSR_RDRF *((volatile uint8_t *)(0x4271E0A8UL)) +#define bFM_MFS15_UART_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM4_MFS15_UART_SSR_ORE *((volatile uint8_t *)(0x4271E0ACUL)) +#define bFM_MFS15_UART_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM4_MFS15_UART_SSR_FRE *((volatile uint8_t *)(0x4271E0B0UL)) +#define bFM_MFS15_UART_SSR_PE *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM4_MFS15_UART_SSR_PE *((volatile uint8_t *)(0x4271E0B4UL)) +#define bFM_MFS15_UART_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) +#define bFM4_MFS15_UART_SSR_REC *((volatile uint8_t *)(0x4271E0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS2 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS2_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42704094UL)) +#define bFM4_MFS2_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42704094UL)) +#define bFM_MFS2_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42704098UL)) +#define bFM_MFS2_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270409CUL)) +#define bFM4_MFS2_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270409CUL)) + +#define bFM_MFS2_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_CSIO_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_CSIO_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_CSIO_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_CSIO_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_CSIO_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_CSIO_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42704480UL)) +#define bFM4_MFS2_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42704480UL)) +#define bFM_MFS2_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42704498UL)) +#define bFM4_MFS2_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42704498UL)) +#define bFM_MFS2_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270449CUL)) +#define bFM4_MFS2_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270449CUL)) +#define bFM_MFS2_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427044A0UL)) +#define bFM4_MFS2_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427044A0UL)) +#define bFM_MFS2_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427044ACUL)) +#define bFM4_MFS2_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427044ACUL)) +#define bFM_MFS2_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427044B0UL)) +#define bFM4_MFS2_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427044B0UL)) +#define bFM_MFS2_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427044B4UL)) +#define bFM4_MFS2_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427044B4UL)) + +#define bFM_MFS2_CSIO_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_CSIO_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_CSIO_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_CSIO_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_CSIO_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_CSIO_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_CSIO_SCR_SPI *((volatile uint8_t *)(0x42704034UL)) +#define bFM4_MFS2_CSIO_SCR_SPI *((volatile uint8_t *)(0x42704034UL)) +#define bFM_MFS2_CSIO_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM4_MFS2_CSIO_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM_MFS2_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42704600UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42704600UL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42704604UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42704604UL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42704608UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42704608UL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270460CUL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270460CUL)) +#define bFM_MFS2_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42704610UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42704610UL)) +#define bFM_MFS2_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42704614UL)) +#define bFM4_MFS2_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42704614UL)) +#define bFM_MFS2_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42704624UL)) +#define bFM4_MFS2_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42704624UL)) + +#define bFM_MFS2_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42704694UL)) +#define bFM4_MFS2_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42704694UL)) +#define bFM_MFS2_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42704698UL)) +#define bFM4_MFS2_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42704698UL)) +#define bFM_MFS2_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270469CUL)) +#define bFM4_MFS2_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270469CUL)) + +#define bFM_MFS2_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427046B4UL)) +#define bFM4_MFS2_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427046B4UL)) +#define bFM_MFS2_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427046B8UL)) +#define bFM4_MFS2_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427046B8UL)) +#define bFM_MFS2_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427046BCUL)) +#define bFM4_MFS2_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427046BCUL)) + +#define bFM_MFS2_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42704714UL)) +#define bFM4_MFS2_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42704714UL)) +#define bFM_MFS2_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42704718UL)) +#define bFM4_MFS2_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42704718UL)) +#define bFM_MFS2_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270471CUL)) +#define bFM4_MFS2_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270471CUL)) + +#define bFM_MFS2_CSIO_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM4_MFS2_CSIO_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM_MFS2_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42704004UL)) +#define bFM4_MFS2_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42704004UL)) +#define bFM_MFS2_CSIO_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM4_MFS2_CSIO_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM_MFS2_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270400CUL)) + +#define bFM_MFS2_CSIO_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_CSIO_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_CSIO_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_CSIO_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_CSIO_SSR_AWC *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_CSIO_SSR_AWC *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_CSIO_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_CSIO_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + +#define bFM_MFS2_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427043A0UL)) +#define bFM4_MFS2_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427043A0UL)) +#define bFM_MFS2_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427043A4UL)) +#define bFM4_MFS2_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427043A4UL)) +#define bFM_MFS2_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427043A8UL)) +#define bFM4_MFS2_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427043A8UL)) +#define bFM_MFS2_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427043ACUL)) +#define bFM4_MFS2_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427043ACUL)) +#define bFM_MFS2_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427043B0UL)) +#define bFM4_MFS2_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427043B0UL)) +#define bFM_MFS2_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427043B4UL)) +#define bFM4_MFS2_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427043B4UL)) + +#define bFM_MFS2_I2C_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_I2C_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_I2C_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_I2C_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_I2C_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_I2C_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_I2C_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_I2C_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_I2C_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_I2C_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_I2C_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_I2C_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_I2C_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_I2C_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_I2C_IBCR_INT *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_I2C_IBCR_INT *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_I2C_IBCR_BER *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_I2C_IBCR_BER *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_I2C_IBCR_INTE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_I2C_IBCR_INTE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42704034UL)) +#define bFM4_MFS2_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42704034UL)) +#define bFM_MFS2_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42704038UL)) +#define bFM4_MFS2_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42704038UL)) +#define bFM_MFS2_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_I2C_IBSR_BB *((volatile uint8_t *)(0x42704080UL)) +#define bFM4_MFS2_I2C_IBSR_BB *((volatile uint8_t *)(0x42704080UL)) +#define bFM_MFS2_I2C_IBSR_SPC *((volatile uint8_t *)(0x42704084UL)) +#define bFM4_MFS2_I2C_IBSR_SPC *((volatile uint8_t *)(0x42704084UL)) +#define bFM_MFS2_I2C_IBSR_RSC *((volatile uint8_t *)(0x42704088UL)) +#define bFM4_MFS2_I2C_IBSR_RSC *((volatile uint8_t *)(0x42704088UL)) +#define bFM_MFS2_I2C_IBSR_AL *((volatile uint8_t *)(0x4270408CUL)) +#define bFM4_MFS2_I2C_IBSR_AL *((volatile uint8_t *)(0x4270408CUL)) +#define bFM_MFS2_I2C_IBSR_TRX *((volatile uint8_t *)(0x42704090UL)) +#define bFM4_MFS2_I2C_IBSR_TRX *((volatile uint8_t *)(0x42704090UL)) +#define bFM_MFS2_I2C_IBSR_RSA *((volatile uint8_t *)(0x42704094UL)) +#define bFM4_MFS2_I2C_IBSR_RSA *((volatile uint8_t *)(0x42704094UL)) +#define bFM_MFS2_I2C_IBSR_RACK *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_I2C_IBSR_RACK *((volatile uint8_t *)(0x42704098UL)) +#define bFM_MFS2_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270409CUL)) +#define bFM4_MFS2_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270409CUL)) + +#define bFM_MFS2_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270421CUL)) +#define bFM4_MFS2_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270421CUL)) + +#define bFM_MFS2_I2C_ISMK_EN *((volatile uint8_t *)(0x4270423CUL)) +#define bFM4_MFS2_I2C_ISMK_EN *((volatile uint8_t *)(0x4270423CUL)) + +#define bFM_MFS2_I2C_SMR_TIE *((volatile uint8_t *)(0x42704008UL)) +#define bFM4_MFS2_I2C_SMR_TIE *((volatile uint8_t *)(0x42704008UL)) +#define bFM_MFS2_I2C_SMR_RIE *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_I2C_SMR_RIE *((volatile uint8_t *)(0x4270400CUL)) + +#define bFM_MFS2_I2C_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_I2C_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_I2C_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_I2C_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_I2C_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_I2C_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_I2C_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_I2C_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_I2C_SSR_TBIE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_I2C_SSR_TBIE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_I2C_SSR_DMA *((volatile uint8_t *)(0x427040B4UL)) +#define bFM4_MFS2_I2C_SSR_DMA *((volatile uint8_t *)(0x427040B4UL)) +#define bFM_MFS2_I2C_SSR_TSET *((volatile uint8_t *)(0x427040B8UL)) +#define bFM4_MFS2_I2C_SSR_TSET *((volatile uint8_t *)(0x427040B8UL)) +#define bFM_MFS2_I2C_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_I2C_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + +#define bFM_MFS2_LIN_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) +#define bFM4_MFS2_LIN_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) + +#define bFM_MFS2_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42704090UL)) +#define bFM4_MFS2_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42704090UL)) +#define bFM_MFS2_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) + +#define bFM_MFS2_LIN_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_LIN_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_LIN_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_LIN_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_LIN_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_LIN_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_LIN_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_LIN_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_LIN_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_LIN_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_LIN_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_LIN_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_LIN_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_LIN_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_LIN_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_LIN_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_LIN_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_LIN_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_LIN_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_LIN_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_LIN_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_LIN_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_LIN_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_LIN_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_LIN_SCR_LBR *((volatile uint8_t *)(0x42704034UL)) +#define bFM4_MFS2_LIN_SCR_LBR *((volatile uint8_t *)(0x42704034UL)) +#define bFM_MFS2_LIN_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM4_MFS2_LIN_SCR_MS *((volatile uint8_t *)(0x42704038UL)) +#define bFM_MFS2_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_LIN_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM4_MFS2_LIN_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM_MFS2_LIN_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_LIN_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) +#define bFM_MFS2_LIN_SMR_WUCR *((volatile uint8_t *)(0x42704010UL)) +#define bFM4_MFS2_LIN_SMR_WUCR *((volatile uint8_t *)(0x42704010UL)) + +#define bFM_MFS2_LIN_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_LIN_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_LIN_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_LIN_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_LIN_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_LIN_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_LIN_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_LIN_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_LIN_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_LIN_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_LIN_SSR_LBD *((volatile uint8_t *)(0x427040B4UL)) +#define bFM4_MFS2_LIN_SSR_LBD *((volatile uint8_t *)(0x427040B4UL)) +#define bFM_MFS2_LIN_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_LIN_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + +#define bFM_MFS2_UART_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) +#define bFM4_MFS2_UART_BGR_EXT *((volatile uint8_t *)(0x427041BCUL)) + +#define bFM_MFS2_UART_ESCR_P *((volatile uint8_t *)(0x4270408CUL)) +#define bFM4_MFS2_UART_ESCR_P *((volatile uint8_t *)(0x4270408CUL)) +#define bFM_MFS2_UART_ESCR_PEN *((volatile uint8_t *)(0x42704090UL)) +#define bFM4_MFS2_UART_ESCR_PEN *((volatile uint8_t *)(0x42704090UL)) +#define bFM_MFS2_UART_ESCR_INV *((volatile uint8_t *)(0x42704094UL)) +#define bFM4_MFS2_UART_ESCR_INV *((volatile uint8_t *)(0x42704094UL)) +#define bFM_MFS2_UART_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) +#define bFM4_MFS2_UART_ESCR_ESBL *((volatile uint8_t *)(0x42704098UL)) +#define bFM_MFS2_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270409CUL)) +#define bFM4_MFS2_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270409CUL)) + +#define bFM_MFS2_UART_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM4_MFS2_UART_FCR_FE1 *((volatile uint8_t *)(0x42704280UL)) +#define bFM_MFS2_UART_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM4_MFS2_UART_FCR_FE2 *((volatile uint8_t *)(0x42704284UL)) +#define bFM_MFS2_UART_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM4_MFS2_UART_FCR_FCL1 *((volatile uint8_t *)(0x42704288UL)) +#define bFM_MFS2_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM4_MFS2_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270428CUL)) +#define bFM_MFS2_UART_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM4_MFS2_UART_FCR_FSET *((volatile uint8_t *)(0x42704290UL)) +#define bFM_MFS2_UART_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM4_MFS2_UART_FCR_FLD *((volatile uint8_t *)(0x42704294UL)) +#define bFM_MFS2_UART_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM4_MFS2_UART_FCR_FLST *((volatile uint8_t *)(0x42704298UL)) +#define bFM_MFS2_UART_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM4_MFS2_UART_FCR_FSEL *((volatile uint8_t *)(0x427042A0UL)) +#define bFM_MFS2_UART_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM4_MFS2_UART_FCR_FTIE *((volatile uint8_t *)(0x427042A4UL)) +#define bFM_MFS2_UART_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM4_MFS2_UART_FCR_FDRQ *((volatile uint8_t *)(0x427042A8UL)) +#define bFM_MFS2_UART_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM4_MFS2_UART_FCR_FRIIE *((volatile uint8_t *)(0x427042ACUL)) +#define bFM_MFS2_UART_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) +#define bFM4_MFS2_UART_FCR_FLSTE *((volatile uint8_t *)(0x427042B0UL)) + +#define bFM_MFS2_UART_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM4_MFS2_UART_SCR_TXE *((volatile uint8_t *)(0x42704020UL)) +#define bFM_MFS2_UART_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM4_MFS2_UART_SCR_RXE *((volatile uint8_t *)(0x42704024UL)) +#define bFM_MFS2_UART_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM4_MFS2_UART_SCR_TBIE *((volatile uint8_t *)(0x42704028UL)) +#define bFM_MFS2_UART_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM4_MFS2_UART_SCR_TIE *((volatile uint8_t *)(0x4270402CUL)) +#define bFM_MFS2_UART_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM4_MFS2_UART_SCR_RIE *((volatile uint8_t *)(0x42704030UL)) +#define bFM_MFS2_UART_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) +#define bFM4_MFS2_UART_SCR_UPCL *((volatile uint8_t *)(0x4270403CUL)) + +#define bFM_MFS2_UART_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM4_MFS2_UART_SMR_SOE *((volatile uint8_t *)(0x42704000UL)) +#define bFM_MFS2_UART_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM4_MFS2_UART_SMR_BDS *((volatile uint8_t *)(0x42704008UL)) +#define bFM_MFS2_UART_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) +#define bFM4_MFS2_UART_SMR_SBL *((volatile uint8_t *)(0x4270400CUL)) + +#define bFM_MFS2_UART_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM4_MFS2_UART_SSR_TBI *((volatile uint8_t *)(0x427040A0UL)) +#define bFM_MFS2_UART_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM4_MFS2_UART_SSR_TDRE *((volatile uint8_t *)(0x427040A4UL)) +#define bFM_MFS2_UART_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM4_MFS2_UART_SSR_RDRF *((volatile uint8_t *)(0x427040A8UL)) +#define bFM_MFS2_UART_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM4_MFS2_UART_SSR_ORE *((volatile uint8_t *)(0x427040ACUL)) +#define bFM_MFS2_UART_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM4_MFS2_UART_SSR_FRE *((volatile uint8_t *)(0x427040B0UL)) +#define bFM_MFS2_UART_SSR_PE *((volatile uint8_t *)(0x427040B4UL)) +#define bFM4_MFS2_UART_SSR_PE *((volatile uint8_t *)(0x427040B4UL)) +#define bFM_MFS2_UART_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) +#define bFM4_MFS2_UART_SSR_REC *((volatile uint8_t *)(0x427040BCUL)) + + +/******************************************************************************* +* MFS Registers MFS3 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS3_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42706094UL)) +#define bFM4_MFS3_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42706094UL)) +#define bFM_MFS3_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42706098UL)) +#define bFM_MFS3_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270609CUL)) +#define bFM4_MFS3_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270609CUL)) + +#define bFM_MFS3_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_CSIO_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_CSIO_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_CSIO_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_CSIO_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_CSIO_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_CSIO_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42706480UL)) +#define bFM4_MFS3_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42706480UL)) +#define bFM_MFS3_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42706498UL)) +#define bFM4_MFS3_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42706498UL)) +#define bFM_MFS3_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270649CUL)) +#define bFM4_MFS3_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270649CUL)) +#define bFM_MFS3_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427064A0UL)) +#define bFM4_MFS3_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427064A0UL)) +#define bFM_MFS3_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427064ACUL)) +#define bFM4_MFS3_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427064ACUL)) +#define bFM_MFS3_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427064B0UL)) +#define bFM4_MFS3_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427064B0UL)) +#define bFM_MFS3_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427064B4UL)) +#define bFM4_MFS3_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427064B4UL)) + +#define bFM_MFS3_CSIO_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_CSIO_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_CSIO_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_CSIO_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_CSIO_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_CSIO_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_CSIO_SCR_SPI *((volatile uint8_t *)(0x42706034UL)) +#define bFM4_MFS3_CSIO_SCR_SPI *((volatile uint8_t *)(0x42706034UL)) +#define bFM_MFS3_CSIO_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM4_MFS3_CSIO_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM_MFS3_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42706600UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42706600UL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42706604UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42706604UL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42706608UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42706608UL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270660CUL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270660CUL)) +#define bFM_MFS3_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42706610UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42706610UL)) +#define bFM_MFS3_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42706614UL)) +#define bFM4_MFS3_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42706614UL)) +#define bFM_MFS3_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42706624UL)) +#define bFM4_MFS3_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42706624UL)) + +#define bFM_MFS3_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42706694UL)) +#define bFM4_MFS3_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42706694UL)) +#define bFM_MFS3_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42706698UL)) +#define bFM4_MFS3_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42706698UL)) +#define bFM_MFS3_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270669CUL)) +#define bFM4_MFS3_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270669CUL)) + +#define bFM_MFS3_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427066B4UL)) +#define bFM4_MFS3_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427066B4UL)) +#define bFM_MFS3_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427066B8UL)) +#define bFM4_MFS3_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427066B8UL)) +#define bFM_MFS3_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427066BCUL)) +#define bFM4_MFS3_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427066BCUL)) + +#define bFM_MFS3_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42706714UL)) +#define bFM4_MFS3_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42706714UL)) +#define bFM_MFS3_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42706718UL)) +#define bFM4_MFS3_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42706718UL)) +#define bFM_MFS3_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270671CUL)) +#define bFM4_MFS3_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270671CUL)) + +#define bFM_MFS3_CSIO_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM4_MFS3_CSIO_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM_MFS3_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42706004UL)) +#define bFM4_MFS3_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42706004UL)) +#define bFM_MFS3_CSIO_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM4_MFS3_CSIO_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM_MFS3_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270600CUL)) + +#define bFM_MFS3_CSIO_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_CSIO_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_CSIO_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_CSIO_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_CSIO_SSR_AWC *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_CSIO_SSR_AWC *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_CSIO_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_CSIO_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + +#define bFM_MFS3_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427063A0UL)) +#define bFM4_MFS3_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427063A0UL)) +#define bFM_MFS3_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427063A4UL)) +#define bFM4_MFS3_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427063A4UL)) +#define bFM_MFS3_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427063A8UL)) +#define bFM4_MFS3_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427063A8UL)) +#define bFM_MFS3_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427063ACUL)) +#define bFM4_MFS3_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427063ACUL)) +#define bFM_MFS3_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427063B0UL)) +#define bFM4_MFS3_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427063B0UL)) +#define bFM_MFS3_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427063B4UL)) +#define bFM4_MFS3_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427063B4UL)) + +#define bFM_MFS3_I2C_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_I2C_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_I2C_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_I2C_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_I2C_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_I2C_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_I2C_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_I2C_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_I2C_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_I2C_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_I2C_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_I2C_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_I2C_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_I2C_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_I2C_IBCR_INT *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_I2C_IBCR_INT *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_I2C_IBCR_BER *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_I2C_IBCR_BER *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_I2C_IBCR_INTE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_I2C_IBCR_INTE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42706034UL)) +#define bFM4_MFS3_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42706034UL)) +#define bFM_MFS3_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42706038UL)) +#define bFM4_MFS3_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42706038UL)) +#define bFM_MFS3_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_I2C_IBSR_BB *((volatile uint8_t *)(0x42706080UL)) +#define bFM4_MFS3_I2C_IBSR_BB *((volatile uint8_t *)(0x42706080UL)) +#define bFM_MFS3_I2C_IBSR_SPC *((volatile uint8_t *)(0x42706084UL)) +#define bFM4_MFS3_I2C_IBSR_SPC *((volatile uint8_t *)(0x42706084UL)) +#define bFM_MFS3_I2C_IBSR_RSC *((volatile uint8_t *)(0x42706088UL)) +#define bFM4_MFS3_I2C_IBSR_RSC *((volatile uint8_t *)(0x42706088UL)) +#define bFM_MFS3_I2C_IBSR_AL *((volatile uint8_t *)(0x4270608CUL)) +#define bFM4_MFS3_I2C_IBSR_AL *((volatile uint8_t *)(0x4270608CUL)) +#define bFM_MFS3_I2C_IBSR_TRX *((volatile uint8_t *)(0x42706090UL)) +#define bFM4_MFS3_I2C_IBSR_TRX *((volatile uint8_t *)(0x42706090UL)) +#define bFM_MFS3_I2C_IBSR_RSA *((volatile uint8_t *)(0x42706094UL)) +#define bFM4_MFS3_I2C_IBSR_RSA *((volatile uint8_t *)(0x42706094UL)) +#define bFM_MFS3_I2C_IBSR_RACK *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_I2C_IBSR_RACK *((volatile uint8_t *)(0x42706098UL)) +#define bFM_MFS3_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270609CUL)) +#define bFM4_MFS3_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270609CUL)) + +#define bFM_MFS3_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270621CUL)) +#define bFM4_MFS3_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270621CUL)) + +#define bFM_MFS3_I2C_ISMK_EN *((volatile uint8_t *)(0x4270623CUL)) +#define bFM4_MFS3_I2C_ISMK_EN *((volatile uint8_t *)(0x4270623CUL)) + +#define bFM_MFS3_I2C_SMR_TIE *((volatile uint8_t *)(0x42706008UL)) +#define bFM4_MFS3_I2C_SMR_TIE *((volatile uint8_t *)(0x42706008UL)) +#define bFM_MFS3_I2C_SMR_RIE *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_I2C_SMR_RIE *((volatile uint8_t *)(0x4270600CUL)) + +#define bFM_MFS3_I2C_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_I2C_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_I2C_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_I2C_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_I2C_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_I2C_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_I2C_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_I2C_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_I2C_SSR_TBIE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_I2C_SSR_TBIE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_I2C_SSR_DMA *((volatile uint8_t *)(0x427060B4UL)) +#define bFM4_MFS3_I2C_SSR_DMA *((volatile uint8_t *)(0x427060B4UL)) +#define bFM_MFS3_I2C_SSR_TSET *((volatile uint8_t *)(0x427060B8UL)) +#define bFM4_MFS3_I2C_SSR_TSET *((volatile uint8_t *)(0x427060B8UL)) +#define bFM_MFS3_I2C_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_I2C_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + +#define bFM_MFS3_LIN_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) +#define bFM4_MFS3_LIN_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) + +#define bFM_MFS3_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42706090UL)) +#define bFM4_MFS3_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42706090UL)) +#define bFM_MFS3_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) + +#define bFM_MFS3_LIN_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_LIN_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_LIN_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_LIN_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_LIN_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_LIN_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_LIN_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_LIN_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_LIN_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_LIN_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_LIN_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_LIN_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_LIN_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_LIN_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_LIN_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_LIN_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_LIN_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_LIN_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_LIN_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_LIN_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_LIN_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_LIN_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_LIN_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_LIN_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_LIN_SCR_LBR *((volatile uint8_t *)(0x42706034UL)) +#define bFM4_MFS3_LIN_SCR_LBR *((volatile uint8_t *)(0x42706034UL)) +#define bFM_MFS3_LIN_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM4_MFS3_LIN_SCR_MS *((volatile uint8_t *)(0x42706038UL)) +#define bFM_MFS3_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_LIN_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM4_MFS3_LIN_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM_MFS3_LIN_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_LIN_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) +#define bFM_MFS3_LIN_SMR_WUCR *((volatile uint8_t *)(0x42706010UL)) +#define bFM4_MFS3_LIN_SMR_WUCR *((volatile uint8_t *)(0x42706010UL)) + +#define bFM_MFS3_LIN_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_LIN_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_LIN_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_LIN_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_LIN_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_LIN_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_LIN_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_LIN_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_LIN_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_LIN_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_LIN_SSR_LBD *((volatile uint8_t *)(0x427060B4UL)) +#define bFM4_MFS3_LIN_SSR_LBD *((volatile uint8_t *)(0x427060B4UL)) +#define bFM_MFS3_LIN_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_LIN_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + +#define bFM_MFS3_UART_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) +#define bFM4_MFS3_UART_BGR_EXT *((volatile uint8_t *)(0x427061BCUL)) + +#define bFM_MFS3_UART_ESCR_P *((volatile uint8_t *)(0x4270608CUL)) +#define bFM4_MFS3_UART_ESCR_P *((volatile uint8_t *)(0x4270608CUL)) +#define bFM_MFS3_UART_ESCR_PEN *((volatile uint8_t *)(0x42706090UL)) +#define bFM4_MFS3_UART_ESCR_PEN *((volatile uint8_t *)(0x42706090UL)) +#define bFM_MFS3_UART_ESCR_INV *((volatile uint8_t *)(0x42706094UL)) +#define bFM4_MFS3_UART_ESCR_INV *((volatile uint8_t *)(0x42706094UL)) +#define bFM_MFS3_UART_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) +#define bFM4_MFS3_UART_ESCR_ESBL *((volatile uint8_t *)(0x42706098UL)) +#define bFM_MFS3_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270609CUL)) +#define bFM4_MFS3_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270609CUL)) + +#define bFM_MFS3_UART_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM4_MFS3_UART_FCR_FE1 *((volatile uint8_t *)(0x42706280UL)) +#define bFM_MFS3_UART_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM4_MFS3_UART_FCR_FE2 *((volatile uint8_t *)(0x42706284UL)) +#define bFM_MFS3_UART_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM4_MFS3_UART_FCR_FCL1 *((volatile uint8_t *)(0x42706288UL)) +#define bFM_MFS3_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM4_MFS3_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270628CUL)) +#define bFM_MFS3_UART_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM4_MFS3_UART_FCR_FSET *((volatile uint8_t *)(0x42706290UL)) +#define bFM_MFS3_UART_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM4_MFS3_UART_FCR_FLD *((volatile uint8_t *)(0x42706294UL)) +#define bFM_MFS3_UART_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM4_MFS3_UART_FCR_FLST *((volatile uint8_t *)(0x42706298UL)) +#define bFM_MFS3_UART_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM4_MFS3_UART_FCR_FSEL *((volatile uint8_t *)(0x427062A0UL)) +#define bFM_MFS3_UART_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM4_MFS3_UART_FCR_FTIE *((volatile uint8_t *)(0x427062A4UL)) +#define bFM_MFS3_UART_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM4_MFS3_UART_FCR_FDRQ *((volatile uint8_t *)(0x427062A8UL)) +#define bFM_MFS3_UART_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM4_MFS3_UART_FCR_FRIIE *((volatile uint8_t *)(0x427062ACUL)) +#define bFM_MFS3_UART_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) +#define bFM4_MFS3_UART_FCR_FLSTE *((volatile uint8_t *)(0x427062B0UL)) + +#define bFM_MFS3_UART_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM4_MFS3_UART_SCR_TXE *((volatile uint8_t *)(0x42706020UL)) +#define bFM_MFS3_UART_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM4_MFS3_UART_SCR_RXE *((volatile uint8_t *)(0x42706024UL)) +#define bFM_MFS3_UART_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM4_MFS3_UART_SCR_TBIE *((volatile uint8_t *)(0x42706028UL)) +#define bFM_MFS3_UART_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM4_MFS3_UART_SCR_TIE *((volatile uint8_t *)(0x4270602CUL)) +#define bFM_MFS3_UART_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM4_MFS3_UART_SCR_RIE *((volatile uint8_t *)(0x42706030UL)) +#define bFM_MFS3_UART_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) +#define bFM4_MFS3_UART_SCR_UPCL *((volatile uint8_t *)(0x4270603CUL)) + +#define bFM_MFS3_UART_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM4_MFS3_UART_SMR_SOE *((volatile uint8_t *)(0x42706000UL)) +#define bFM_MFS3_UART_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM4_MFS3_UART_SMR_BDS *((volatile uint8_t *)(0x42706008UL)) +#define bFM_MFS3_UART_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) +#define bFM4_MFS3_UART_SMR_SBL *((volatile uint8_t *)(0x4270600CUL)) + +#define bFM_MFS3_UART_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM4_MFS3_UART_SSR_TBI *((volatile uint8_t *)(0x427060A0UL)) +#define bFM_MFS3_UART_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM4_MFS3_UART_SSR_TDRE *((volatile uint8_t *)(0x427060A4UL)) +#define bFM_MFS3_UART_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM4_MFS3_UART_SSR_RDRF *((volatile uint8_t *)(0x427060A8UL)) +#define bFM_MFS3_UART_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM4_MFS3_UART_SSR_ORE *((volatile uint8_t *)(0x427060ACUL)) +#define bFM_MFS3_UART_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM4_MFS3_UART_SSR_FRE *((volatile uint8_t *)(0x427060B0UL)) +#define bFM_MFS3_UART_SSR_PE *((volatile uint8_t *)(0x427060B4UL)) +#define bFM4_MFS3_UART_SSR_PE *((volatile uint8_t *)(0x427060B4UL)) +#define bFM_MFS3_UART_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) +#define bFM4_MFS3_UART_SSR_REC *((volatile uint8_t *)(0x427060BCUL)) + + +/******************************************************************************* +* MFS Registers MFS4 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS4_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42708094UL)) +#define bFM4_MFS4_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42708094UL)) +#define bFM_MFS4_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42708098UL)) +#define bFM_MFS4_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270809CUL)) +#define bFM4_MFS4_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270809CUL)) + +#define bFM_MFS4_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_CSIO_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_CSIO_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_CSIO_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_CSIO_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_CSIO_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_CSIO_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42708480UL)) +#define bFM4_MFS4_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42708480UL)) +#define bFM_MFS4_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42708498UL)) +#define bFM4_MFS4_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42708498UL)) +#define bFM_MFS4_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270849CUL)) +#define bFM4_MFS4_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270849CUL)) +#define bFM_MFS4_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427084A0UL)) +#define bFM4_MFS4_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427084A0UL)) +#define bFM_MFS4_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427084ACUL)) +#define bFM4_MFS4_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427084ACUL)) +#define bFM_MFS4_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427084B0UL)) +#define bFM4_MFS4_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427084B0UL)) +#define bFM_MFS4_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427084B4UL)) +#define bFM4_MFS4_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427084B4UL)) + +#define bFM_MFS4_CSIO_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_CSIO_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_CSIO_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_CSIO_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_CSIO_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_CSIO_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_CSIO_SCR_SPI *((volatile uint8_t *)(0x42708034UL)) +#define bFM4_MFS4_CSIO_SCR_SPI *((volatile uint8_t *)(0x42708034UL)) +#define bFM_MFS4_CSIO_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM4_MFS4_CSIO_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM_MFS4_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42708600UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42708600UL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42708604UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42708604UL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42708608UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42708608UL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270860CUL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270860CUL)) +#define bFM_MFS4_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42708610UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42708610UL)) +#define bFM_MFS4_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42708614UL)) +#define bFM4_MFS4_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42708614UL)) +#define bFM_MFS4_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42708624UL)) +#define bFM4_MFS4_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42708624UL)) + +#define bFM_MFS4_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42708694UL)) +#define bFM4_MFS4_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42708694UL)) +#define bFM_MFS4_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42708698UL)) +#define bFM4_MFS4_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42708698UL)) +#define bFM_MFS4_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270869CUL)) +#define bFM4_MFS4_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270869CUL)) + +#define bFM_MFS4_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427086B4UL)) +#define bFM4_MFS4_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427086B4UL)) +#define bFM_MFS4_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427086B8UL)) +#define bFM4_MFS4_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427086B8UL)) +#define bFM_MFS4_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427086BCUL)) +#define bFM4_MFS4_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427086BCUL)) + +#define bFM_MFS4_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42708714UL)) +#define bFM4_MFS4_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42708714UL)) +#define bFM_MFS4_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42708718UL)) +#define bFM4_MFS4_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42708718UL)) +#define bFM_MFS4_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270871CUL)) +#define bFM4_MFS4_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270871CUL)) + +#define bFM_MFS4_CSIO_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM4_MFS4_CSIO_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM_MFS4_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42708004UL)) +#define bFM4_MFS4_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42708004UL)) +#define bFM_MFS4_CSIO_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM4_MFS4_CSIO_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM_MFS4_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270800CUL)) + +#define bFM_MFS4_CSIO_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_CSIO_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_CSIO_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_CSIO_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_CSIO_SSR_AWC *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_CSIO_SSR_AWC *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_CSIO_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_CSIO_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + +#define bFM_MFS4_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427083A0UL)) +#define bFM4_MFS4_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427083A0UL)) +#define bFM_MFS4_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427083A4UL)) +#define bFM4_MFS4_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427083A4UL)) +#define bFM_MFS4_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427083A8UL)) +#define bFM4_MFS4_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427083A8UL)) +#define bFM_MFS4_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427083ACUL)) +#define bFM4_MFS4_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427083ACUL)) +#define bFM_MFS4_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427083B0UL)) +#define bFM4_MFS4_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427083B0UL)) +#define bFM_MFS4_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427083B4UL)) +#define bFM4_MFS4_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427083B4UL)) + +#define bFM_MFS4_I2C_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_I2C_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_I2C_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_I2C_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_I2C_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_I2C_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_I2C_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_I2C_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_I2C_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_I2C_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_I2C_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_I2C_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_I2C_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_I2C_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_I2C_IBCR_INT *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_I2C_IBCR_INT *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_I2C_IBCR_BER *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_I2C_IBCR_BER *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_I2C_IBCR_INTE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_I2C_IBCR_INTE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42708034UL)) +#define bFM4_MFS4_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42708034UL)) +#define bFM_MFS4_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42708038UL)) +#define bFM4_MFS4_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42708038UL)) +#define bFM_MFS4_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_I2C_IBSR_BB *((volatile uint8_t *)(0x42708080UL)) +#define bFM4_MFS4_I2C_IBSR_BB *((volatile uint8_t *)(0x42708080UL)) +#define bFM_MFS4_I2C_IBSR_SPC *((volatile uint8_t *)(0x42708084UL)) +#define bFM4_MFS4_I2C_IBSR_SPC *((volatile uint8_t *)(0x42708084UL)) +#define bFM_MFS4_I2C_IBSR_RSC *((volatile uint8_t *)(0x42708088UL)) +#define bFM4_MFS4_I2C_IBSR_RSC *((volatile uint8_t *)(0x42708088UL)) +#define bFM_MFS4_I2C_IBSR_AL *((volatile uint8_t *)(0x4270808CUL)) +#define bFM4_MFS4_I2C_IBSR_AL *((volatile uint8_t *)(0x4270808CUL)) +#define bFM_MFS4_I2C_IBSR_TRX *((volatile uint8_t *)(0x42708090UL)) +#define bFM4_MFS4_I2C_IBSR_TRX *((volatile uint8_t *)(0x42708090UL)) +#define bFM_MFS4_I2C_IBSR_RSA *((volatile uint8_t *)(0x42708094UL)) +#define bFM4_MFS4_I2C_IBSR_RSA *((volatile uint8_t *)(0x42708094UL)) +#define bFM_MFS4_I2C_IBSR_RACK *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_I2C_IBSR_RACK *((volatile uint8_t *)(0x42708098UL)) +#define bFM_MFS4_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270809CUL)) +#define bFM4_MFS4_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270809CUL)) + +#define bFM_MFS4_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270821CUL)) +#define bFM4_MFS4_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270821CUL)) + +#define bFM_MFS4_I2C_ISMK_EN *((volatile uint8_t *)(0x4270823CUL)) +#define bFM4_MFS4_I2C_ISMK_EN *((volatile uint8_t *)(0x4270823CUL)) + +#define bFM_MFS4_I2C_SMR_TIE *((volatile uint8_t *)(0x42708008UL)) +#define bFM4_MFS4_I2C_SMR_TIE *((volatile uint8_t *)(0x42708008UL)) +#define bFM_MFS4_I2C_SMR_RIE *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_I2C_SMR_RIE *((volatile uint8_t *)(0x4270800CUL)) + +#define bFM_MFS4_I2C_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_I2C_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_I2C_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_I2C_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_I2C_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_I2C_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_I2C_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_I2C_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_I2C_SSR_TBIE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_I2C_SSR_TBIE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_I2C_SSR_DMA *((volatile uint8_t *)(0x427080B4UL)) +#define bFM4_MFS4_I2C_SSR_DMA *((volatile uint8_t *)(0x427080B4UL)) +#define bFM_MFS4_I2C_SSR_TSET *((volatile uint8_t *)(0x427080B8UL)) +#define bFM4_MFS4_I2C_SSR_TSET *((volatile uint8_t *)(0x427080B8UL)) +#define bFM_MFS4_I2C_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_I2C_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + +#define bFM_MFS4_LIN_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) +#define bFM4_MFS4_LIN_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) + +#define bFM_MFS4_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42708090UL)) +#define bFM4_MFS4_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42708090UL)) +#define bFM_MFS4_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) + +#define bFM_MFS4_LIN_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_LIN_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_LIN_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_LIN_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_LIN_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_LIN_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_LIN_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_LIN_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_LIN_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_LIN_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_LIN_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_LIN_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_LIN_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_LIN_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_LIN_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_LIN_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_LIN_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_LIN_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_LIN_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_LIN_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_LIN_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_LIN_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_LIN_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_LIN_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_LIN_SCR_LBR *((volatile uint8_t *)(0x42708034UL)) +#define bFM4_MFS4_LIN_SCR_LBR *((volatile uint8_t *)(0x42708034UL)) +#define bFM_MFS4_LIN_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM4_MFS4_LIN_SCR_MS *((volatile uint8_t *)(0x42708038UL)) +#define bFM_MFS4_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_LIN_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM4_MFS4_LIN_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM_MFS4_LIN_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_LIN_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) +#define bFM_MFS4_LIN_SMR_WUCR *((volatile uint8_t *)(0x42708010UL)) +#define bFM4_MFS4_LIN_SMR_WUCR *((volatile uint8_t *)(0x42708010UL)) + +#define bFM_MFS4_LIN_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_LIN_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_LIN_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_LIN_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_LIN_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_LIN_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_LIN_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_LIN_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_LIN_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_LIN_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_LIN_SSR_LBD *((volatile uint8_t *)(0x427080B4UL)) +#define bFM4_MFS4_LIN_SSR_LBD *((volatile uint8_t *)(0x427080B4UL)) +#define bFM_MFS4_LIN_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_LIN_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + +#define bFM_MFS4_UART_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) +#define bFM4_MFS4_UART_BGR_EXT *((volatile uint8_t *)(0x427081BCUL)) + +#define bFM_MFS4_UART_ESCR_P *((volatile uint8_t *)(0x4270808CUL)) +#define bFM4_MFS4_UART_ESCR_P *((volatile uint8_t *)(0x4270808CUL)) +#define bFM_MFS4_UART_ESCR_PEN *((volatile uint8_t *)(0x42708090UL)) +#define bFM4_MFS4_UART_ESCR_PEN *((volatile uint8_t *)(0x42708090UL)) +#define bFM_MFS4_UART_ESCR_INV *((volatile uint8_t *)(0x42708094UL)) +#define bFM4_MFS4_UART_ESCR_INV *((volatile uint8_t *)(0x42708094UL)) +#define bFM_MFS4_UART_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) +#define bFM4_MFS4_UART_ESCR_ESBL *((volatile uint8_t *)(0x42708098UL)) +#define bFM_MFS4_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270809CUL)) +#define bFM4_MFS4_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270809CUL)) + +#define bFM_MFS4_UART_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM4_MFS4_UART_FCR_FE1 *((volatile uint8_t *)(0x42708280UL)) +#define bFM_MFS4_UART_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM4_MFS4_UART_FCR_FE2 *((volatile uint8_t *)(0x42708284UL)) +#define bFM_MFS4_UART_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM4_MFS4_UART_FCR_FCL1 *((volatile uint8_t *)(0x42708288UL)) +#define bFM_MFS4_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM4_MFS4_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270828CUL)) +#define bFM_MFS4_UART_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM4_MFS4_UART_FCR_FSET *((volatile uint8_t *)(0x42708290UL)) +#define bFM_MFS4_UART_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM4_MFS4_UART_FCR_FLD *((volatile uint8_t *)(0x42708294UL)) +#define bFM_MFS4_UART_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM4_MFS4_UART_FCR_FLST *((volatile uint8_t *)(0x42708298UL)) +#define bFM_MFS4_UART_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM4_MFS4_UART_FCR_FSEL *((volatile uint8_t *)(0x427082A0UL)) +#define bFM_MFS4_UART_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM4_MFS4_UART_FCR_FTIE *((volatile uint8_t *)(0x427082A4UL)) +#define bFM_MFS4_UART_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM4_MFS4_UART_FCR_FDRQ *((volatile uint8_t *)(0x427082A8UL)) +#define bFM_MFS4_UART_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM4_MFS4_UART_FCR_FRIIE *((volatile uint8_t *)(0x427082ACUL)) +#define bFM_MFS4_UART_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) +#define bFM4_MFS4_UART_FCR_FLSTE *((volatile uint8_t *)(0x427082B0UL)) + +#define bFM_MFS4_UART_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM4_MFS4_UART_SCR_TXE *((volatile uint8_t *)(0x42708020UL)) +#define bFM_MFS4_UART_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM4_MFS4_UART_SCR_RXE *((volatile uint8_t *)(0x42708024UL)) +#define bFM_MFS4_UART_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM4_MFS4_UART_SCR_TBIE *((volatile uint8_t *)(0x42708028UL)) +#define bFM_MFS4_UART_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM4_MFS4_UART_SCR_TIE *((volatile uint8_t *)(0x4270802CUL)) +#define bFM_MFS4_UART_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM4_MFS4_UART_SCR_RIE *((volatile uint8_t *)(0x42708030UL)) +#define bFM_MFS4_UART_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) +#define bFM4_MFS4_UART_SCR_UPCL *((volatile uint8_t *)(0x4270803CUL)) + +#define bFM_MFS4_UART_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM4_MFS4_UART_SMR_SOE *((volatile uint8_t *)(0x42708000UL)) +#define bFM_MFS4_UART_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM4_MFS4_UART_SMR_BDS *((volatile uint8_t *)(0x42708008UL)) +#define bFM_MFS4_UART_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) +#define bFM4_MFS4_UART_SMR_SBL *((volatile uint8_t *)(0x4270800CUL)) + +#define bFM_MFS4_UART_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM4_MFS4_UART_SSR_TBI *((volatile uint8_t *)(0x427080A0UL)) +#define bFM_MFS4_UART_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM4_MFS4_UART_SSR_TDRE *((volatile uint8_t *)(0x427080A4UL)) +#define bFM_MFS4_UART_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM4_MFS4_UART_SSR_RDRF *((volatile uint8_t *)(0x427080A8UL)) +#define bFM_MFS4_UART_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM4_MFS4_UART_SSR_ORE *((volatile uint8_t *)(0x427080ACUL)) +#define bFM_MFS4_UART_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM4_MFS4_UART_SSR_FRE *((volatile uint8_t *)(0x427080B0UL)) +#define bFM_MFS4_UART_SSR_PE *((volatile uint8_t *)(0x427080B4UL)) +#define bFM4_MFS4_UART_SSR_PE *((volatile uint8_t *)(0x427080B4UL)) +#define bFM_MFS4_UART_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) +#define bFM4_MFS4_UART_SSR_REC *((volatile uint8_t *)(0x427080BCUL)) + + +/******************************************************************************* +* MFS Registers MFS5 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS5_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270A094UL)) +#define bFM4_MFS5_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270A094UL)) +#define bFM_MFS5_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270A098UL)) +#define bFM_MFS5_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270A09CUL)) +#define bFM4_MFS5_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270A09CUL)) + +#define bFM_MFS5_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270A480UL)) +#define bFM4_MFS5_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270A480UL)) +#define bFM_MFS5_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270A498UL)) +#define bFM4_MFS5_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270A498UL)) +#define bFM_MFS5_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270A49CUL)) +#define bFM4_MFS5_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270A49CUL)) +#define bFM_MFS5_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270A4A0UL)) +#define bFM4_MFS5_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270A4A0UL)) +#define bFM_MFS5_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270A4ACUL)) +#define bFM4_MFS5_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270A4ACUL)) +#define bFM_MFS5_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270A4B0UL)) +#define bFM4_MFS5_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270A4B0UL)) +#define bFM_MFS5_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270A4B4UL)) +#define bFM4_MFS5_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270A4B4UL)) + +#define bFM_MFS5_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270A034UL)) +#define bFM4_MFS5_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270A034UL)) +#define bFM_MFS5_CSIO_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM4_MFS5_CSIO_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM_MFS5_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270A600UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270A600UL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270A604UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270A604UL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270A608UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270A608UL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270A60CUL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270A60CUL)) +#define bFM_MFS5_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270A610UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270A610UL)) +#define bFM_MFS5_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270A614UL)) +#define bFM4_MFS5_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270A614UL)) +#define bFM_MFS5_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270A624UL)) +#define bFM4_MFS5_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270A624UL)) + +#define bFM_MFS5_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270A694UL)) +#define bFM4_MFS5_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270A694UL)) +#define bFM_MFS5_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270A698UL)) +#define bFM4_MFS5_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270A698UL)) +#define bFM_MFS5_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270A69CUL)) +#define bFM4_MFS5_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270A69CUL)) + +#define bFM_MFS5_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270A6B4UL)) +#define bFM4_MFS5_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270A6B4UL)) +#define bFM_MFS5_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270A6B8UL)) +#define bFM4_MFS5_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270A6B8UL)) +#define bFM_MFS5_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270A6BCUL)) +#define bFM4_MFS5_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270A6BCUL)) + +#define bFM_MFS5_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270A714UL)) +#define bFM4_MFS5_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270A714UL)) +#define bFM_MFS5_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270A718UL)) +#define bFM4_MFS5_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270A718UL)) +#define bFM_MFS5_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270A71CUL)) +#define bFM4_MFS5_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270A71CUL)) + +#define bFM_MFS5_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM4_MFS5_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM_MFS5_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270A004UL)) +#define bFM4_MFS5_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270A004UL)) +#define bFM_MFS5_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM4_MFS5_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM_MFS5_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270A00CUL)) + +#define bFM_MFS5_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_CSIO_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_CSIO_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + +#define bFM_MFS5_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270A3A0UL)) +#define bFM4_MFS5_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270A3A0UL)) +#define bFM_MFS5_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270A3A4UL)) +#define bFM4_MFS5_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270A3A4UL)) +#define bFM_MFS5_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270A3A8UL)) +#define bFM4_MFS5_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270A3A8UL)) +#define bFM_MFS5_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270A3ACUL)) +#define bFM4_MFS5_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270A3ACUL)) +#define bFM_MFS5_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270A3B0UL)) +#define bFM4_MFS5_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270A3B0UL)) +#define bFM_MFS5_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270A3B4UL)) +#define bFM4_MFS5_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270A3B4UL)) + +#define bFM_MFS5_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_I2C_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_I2C_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_I2C_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_I2C_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_I2C_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_I2C_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_I2C_IBCR_INT *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_I2C_IBCR_INT *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_I2C_IBCR_BER *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_I2C_IBCR_BER *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270A034UL)) +#define bFM4_MFS5_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270A034UL)) +#define bFM_MFS5_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270A038UL)) +#define bFM4_MFS5_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270A038UL)) +#define bFM_MFS5_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_I2C_IBSR_BB *((volatile uint8_t *)(0x4270A080UL)) +#define bFM4_MFS5_I2C_IBSR_BB *((volatile uint8_t *)(0x4270A080UL)) +#define bFM_MFS5_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270A084UL)) +#define bFM4_MFS5_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270A084UL)) +#define bFM_MFS5_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270A088UL)) +#define bFM4_MFS5_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270A088UL)) +#define bFM_MFS5_I2C_IBSR_AL *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM4_MFS5_I2C_IBSR_AL *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM_MFS5_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270A090UL)) +#define bFM4_MFS5_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270A090UL)) +#define bFM_MFS5_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270A094UL)) +#define bFM4_MFS5_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270A094UL)) +#define bFM_MFS5_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270A098UL)) +#define bFM_MFS5_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270A09CUL)) +#define bFM4_MFS5_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270A09CUL)) + +#define bFM_MFS5_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270A21CUL)) +#define bFM4_MFS5_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270A21CUL)) + +#define bFM_MFS5_I2C_ISMK_EN *((volatile uint8_t *)(0x4270A23CUL)) +#define bFM4_MFS5_I2C_ISMK_EN *((volatile uint8_t *)(0x4270A23CUL)) + +#define bFM_MFS5_I2C_SMR_TIE *((volatile uint8_t *)(0x4270A008UL)) +#define bFM4_MFS5_I2C_SMR_TIE *((volatile uint8_t *)(0x4270A008UL)) +#define bFM_MFS5_I2C_SMR_RIE *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_I2C_SMR_RIE *((volatile uint8_t *)(0x4270A00CUL)) + +#define bFM_MFS5_I2C_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_I2C_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_I2C_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_I2C_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_I2C_SSR_DMA *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM4_MFS5_I2C_SSR_DMA *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM_MFS5_I2C_SSR_TSET *((volatile uint8_t *)(0x4270A0B8UL)) +#define bFM4_MFS5_I2C_SSR_TSET *((volatile uint8_t *)(0x4270A0B8UL)) +#define bFM_MFS5_I2C_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_I2C_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + +#define bFM_MFS5_LIN_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) +#define bFM4_MFS5_LIN_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) + +#define bFM_MFS5_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270A090UL)) +#define bFM4_MFS5_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270A090UL)) +#define bFM_MFS5_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) + +#define bFM_MFS5_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_LIN_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_LIN_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_LIN_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_LIN_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_LIN_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_LIN_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_LIN_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_LIN_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_LIN_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_LIN_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_LIN_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_LIN_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_LIN_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_LIN_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_LIN_SCR_LBR *((volatile uint8_t *)(0x4270A034UL)) +#define bFM4_MFS5_LIN_SCR_LBR *((volatile uint8_t *)(0x4270A034UL)) +#define bFM_MFS5_LIN_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM4_MFS5_LIN_SCR_MS *((volatile uint8_t *)(0x4270A038UL)) +#define bFM_MFS5_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_LIN_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM4_MFS5_LIN_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM_MFS5_LIN_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_LIN_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM_MFS5_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270A010UL)) +#define bFM4_MFS5_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270A010UL)) + +#define bFM_MFS5_LIN_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_LIN_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_LIN_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_LIN_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_LIN_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_LIN_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_LIN_SSR_LBD *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM4_MFS5_LIN_SSR_LBD *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM_MFS5_LIN_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_LIN_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + +#define bFM_MFS5_UART_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) +#define bFM4_MFS5_UART_BGR_EXT *((volatile uint8_t *)(0x4270A1BCUL)) + +#define bFM_MFS5_UART_ESCR_P *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM4_MFS5_UART_ESCR_P *((volatile uint8_t *)(0x4270A08CUL)) +#define bFM_MFS5_UART_ESCR_PEN *((volatile uint8_t *)(0x4270A090UL)) +#define bFM4_MFS5_UART_ESCR_PEN *((volatile uint8_t *)(0x4270A090UL)) +#define bFM_MFS5_UART_ESCR_INV *((volatile uint8_t *)(0x4270A094UL)) +#define bFM4_MFS5_UART_ESCR_INV *((volatile uint8_t *)(0x4270A094UL)) +#define bFM_MFS5_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) +#define bFM4_MFS5_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270A098UL)) +#define bFM_MFS5_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270A09CUL)) +#define bFM4_MFS5_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270A09CUL)) + +#define bFM_MFS5_UART_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM4_MFS5_UART_FCR_FE1 *((volatile uint8_t *)(0x4270A280UL)) +#define bFM_MFS5_UART_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM4_MFS5_UART_FCR_FE2 *((volatile uint8_t *)(0x4270A284UL)) +#define bFM_MFS5_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM4_MFS5_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270A288UL)) +#define bFM_MFS5_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM4_MFS5_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270A28CUL)) +#define bFM_MFS5_UART_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM4_MFS5_UART_FCR_FSET *((volatile uint8_t *)(0x4270A290UL)) +#define bFM_MFS5_UART_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM4_MFS5_UART_FCR_FLD *((volatile uint8_t *)(0x4270A294UL)) +#define bFM_MFS5_UART_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM4_MFS5_UART_FCR_FLST *((volatile uint8_t *)(0x4270A298UL)) +#define bFM_MFS5_UART_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM4_MFS5_UART_FCR_FSEL *((volatile uint8_t *)(0x4270A2A0UL)) +#define bFM_MFS5_UART_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM4_MFS5_UART_FCR_FTIE *((volatile uint8_t *)(0x4270A2A4UL)) +#define bFM_MFS5_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM4_MFS5_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270A2A8UL)) +#define bFM_MFS5_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM4_MFS5_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270A2ACUL)) +#define bFM_MFS5_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) +#define bFM4_MFS5_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270A2B0UL)) + +#define bFM_MFS5_UART_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM4_MFS5_UART_SCR_TXE *((volatile uint8_t *)(0x4270A020UL)) +#define bFM_MFS5_UART_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM4_MFS5_UART_SCR_RXE *((volatile uint8_t *)(0x4270A024UL)) +#define bFM_MFS5_UART_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM4_MFS5_UART_SCR_TBIE *((volatile uint8_t *)(0x4270A028UL)) +#define bFM_MFS5_UART_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM4_MFS5_UART_SCR_TIE *((volatile uint8_t *)(0x4270A02CUL)) +#define bFM_MFS5_UART_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM4_MFS5_UART_SCR_RIE *((volatile uint8_t *)(0x4270A030UL)) +#define bFM_MFS5_UART_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) +#define bFM4_MFS5_UART_SCR_UPCL *((volatile uint8_t *)(0x4270A03CUL)) + +#define bFM_MFS5_UART_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM4_MFS5_UART_SMR_SOE *((volatile uint8_t *)(0x4270A000UL)) +#define bFM_MFS5_UART_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM4_MFS5_UART_SMR_BDS *((volatile uint8_t *)(0x4270A008UL)) +#define bFM_MFS5_UART_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) +#define bFM4_MFS5_UART_SMR_SBL *((volatile uint8_t *)(0x4270A00CUL)) + +#define bFM_MFS5_UART_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM4_MFS5_UART_SSR_TBI *((volatile uint8_t *)(0x4270A0A0UL)) +#define bFM_MFS5_UART_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM4_MFS5_UART_SSR_TDRE *((volatile uint8_t *)(0x4270A0A4UL)) +#define bFM_MFS5_UART_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM4_MFS5_UART_SSR_RDRF *((volatile uint8_t *)(0x4270A0A8UL)) +#define bFM_MFS5_UART_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM4_MFS5_UART_SSR_ORE *((volatile uint8_t *)(0x4270A0ACUL)) +#define bFM_MFS5_UART_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM4_MFS5_UART_SSR_FRE *((volatile uint8_t *)(0x4270A0B0UL)) +#define bFM_MFS5_UART_SSR_PE *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM4_MFS5_UART_SSR_PE *((volatile uint8_t *)(0x4270A0B4UL)) +#define bFM_MFS5_UART_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) +#define bFM4_MFS5_UART_SSR_REC *((volatile uint8_t *)(0x4270A0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS6 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS6_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270C094UL)) +#define bFM4_MFS6_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270C094UL)) +#define bFM_MFS6_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270C098UL)) +#define bFM_MFS6_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270C09CUL)) +#define bFM4_MFS6_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270C09CUL)) + +#define bFM_MFS6_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270C480UL)) +#define bFM4_MFS6_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270C480UL)) +#define bFM_MFS6_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270C498UL)) +#define bFM4_MFS6_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270C498UL)) +#define bFM_MFS6_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270C49CUL)) +#define bFM4_MFS6_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270C49CUL)) +#define bFM_MFS6_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270C4A0UL)) +#define bFM4_MFS6_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270C4A0UL)) +#define bFM_MFS6_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270C4ACUL)) +#define bFM4_MFS6_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270C4ACUL)) +#define bFM_MFS6_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270C4B0UL)) +#define bFM4_MFS6_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270C4B0UL)) +#define bFM_MFS6_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270C4B4UL)) +#define bFM4_MFS6_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270C4B4UL)) + +#define bFM_MFS6_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270C034UL)) +#define bFM4_MFS6_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270C034UL)) +#define bFM_MFS6_CSIO_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM4_MFS6_CSIO_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM_MFS6_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270C600UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270C600UL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270C604UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270C604UL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270C608UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270C608UL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270C60CUL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270C60CUL)) +#define bFM_MFS6_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270C610UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270C610UL)) +#define bFM_MFS6_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270C614UL)) +#define bFM4_MFS6_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270C614UL)) +#define bFM_MFS6_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270C624UL)) +#define bFM4_MFS6_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270C624UL)) + +#define bFM_MFS6_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270C694UL)) +#define bFM4_MFS6_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270C694UL)) +#define bFM_MFS6_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270C698UL)) +#define bFM4_MFS6_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270C698UL)) +#define bFM_MFS6_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270C69CUL)) +#define bFM4_MFS6_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270C69CUL)) + +#define bFM_MFS6_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270C6B4UL)) +#define bFM4_MFS6_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270C6B4UL)) +#define bFM_MFS6_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270C6B8UL)) +#define bFM4_MFS6_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270C6B8UL)) +#define bFM_MFS6_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270C6BCUL)) +#define bFM4_MFS6_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270C6BCUL)) + +#define bFM_MFS6_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270C714UL)) +#define bFM4_MFS6_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270C714UL)) +#define bFM_MFS6_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270C718UL)) +#define bFM4_MFS6_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270C718UL)) +#define bFM_MFS6_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270C71CUL)) +#define bFM4_MFS6_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270C71CUL)) + +#define bFM_MFS6_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM4_MFS6_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM_MFS6_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270C004UL)) +#define bFM4_MFS6_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270C004UL)) +#define bFM_MFS6_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM4_MFS6_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM_MFS6_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270C00CUL)) + +#define bFM_MFS6_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_CSIO_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_CSIO_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + +#define bFM_MFS6_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270C3A0UL)) +#define bFM4_MFS6_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270C3A0UL)) +#define bFM_MFS6_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270C3A4UL)) +#define bFM4_MFS6_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270C3A4UL)) +#define bFM_MFS6_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270C3A8UL)) +#define bFM4_MFS6_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270C3A8UL)) +#define bFM_MFS6_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270C3ACUL)) +#define bFM4_MFS6_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270C3ACUL)) +#define bFM_MFS6_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270C3B0UL)) +#define bFM4_MFS6_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270C3B0UL)) +#define bFM_MFS6_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270C3B4UL)) +#define bFM4_MFS6_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270C3B4UL)) + +#define bFM_MFS6_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_I2C_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_I2C_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_I2C_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_I2C_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_I2C_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_I2C_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_I2C_IBCR_INT *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_I2C_IBCR_INT *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_I2C_IBCR_BER *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_I2C_IBCR_BER *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270C034UL)) +#define bFM4_MFS6_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270C034UL)) +#define bFM_MFS6_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270C038UL)) +#define bFM4_MFS6_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270C038UL)) +#define bFM_MFS6_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_I2C_IBSR_BB *((volatile uint8_t *)(0x4270C080UL)) +#define bFM4_MFS6_I2C_IBSR_BB *((volatile uint8_t *)(0x4270C080UL)) +#define bFM_MFS6_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270C084UL)) +#define bFM4_MFS6_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270C084UL)) +#define bFM_MFS6_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270C088UL)) +#define bFM4_MFS6_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270C088UL)) +#define bFM_MFS6_I2C_IBSR_AL *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM4_MFS6_I2C_IBSR_AL *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM_MFS6_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270C090UL)) +#define bFM4_MFS6_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270C090UL)) +#define bFM_MFS6_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270C094UL)) +#define bFM4_MFS6_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270C094UL)) +#define bFM_MFS6_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270C098UL)) +#define bFM_MFS6_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270C09CUL)) +#define bFM4_MFS6_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270C09CUL)) + +#define bFM_MFS6_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270C21CUL)) +#define bFM4_MFS6_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270C21CUL)) + +#define bFM_MFS6_I2C_ISMK_EN *((volatile uint8_t *)(0x4270C23CUL)) +#define bFM4_MFS6_I2C_ISMK_EN *((volatile uint8_t *)(0x4270C23CUL)) + +#define bFM_MFS6_I2C_SMR_TIE *((volatile uint8_t *)(0x4270C008UL)) +#define bFM4_MFS6_I2C_SMR_TIE *((volatile uint8_t *)(0x4270C008UL)) +#define bFM_MFS6_I2C_SMR_RIE *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_I2C_SMR_RIE *((volatile uint8_t *)(0x4270C00CUL)) + +#define bFM_MFS6_I2C_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_I2C_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_I2C_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_I2C_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_I2C_SSR_DMA *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM4_MFS6_I2C_SSR_DMA *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM_MFS6_I2C_SSR_TSET *((volatile uint8_t *)(0x4270C0B8UL)) +#define bFM4_MFS6_I2C_SSR_TSET *((volatile uint8_t *)(0x4270C0B8UL)) +#define bFM_MFS6_I2C_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_I2C_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + +#define bFM_MFS6_LIN_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) +#define bFM4_MFS6_LIN_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) + +#define bFM_MFS6_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270C090UL)) +#define bFM4_MFS6_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270C090UL)) +#define bFM_MFS6_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) + +#define bFM_MFS6_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_LIN_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_LIN_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_LIN_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_LIN_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_LIN_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_LIN_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_LIN_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_LIN_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_LIN_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_LIN_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_LIN_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_LIN_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_LIN_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_LIN_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_LIN_SCR_LBR *((volatile uint8_t *)(0x4270C034UL)) +#define bFM4_MFS6_LIN_SCR_LBR *((volatile uint8_t *)(0x4270C034UL)) +#define bFM_MFS6_LIN_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM4_MFS6_LIN_SCR_MS *((volatile uint8_t *)(0x4270C038UL)) +#define bFM_MFS6_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_LIN_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM4_MFS6_LIN_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM_MFS6_LIN_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_LIN_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM_MFS6_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270C010UL)) +#define bFM4_MFS6_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270C010UL)) + +#define bFM_MFS6_LIN_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_LIN_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_LIN_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_LIN_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_LIN_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_LIN_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_LIN_SSR_LBD *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM4_MFS6_LIN_SSR_LBD *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM_MFS6_LIN_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_LIN_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + +#define bFM_MFS6_UART_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) +#define bFM4_MFS6_UART_BGR_EXT *((volatile uint8_t *)(0x4270C1BCUL)) + +#define bFM_MFS6_UART_ESCR_P *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM4_MFS6_UART_ESCR_P *((volatile uint8_t *)(0x4270C08CUL)) +#define bFM_MFS6_UART_ESCR_PEN *((volatile uint8_t *)(0x4270C090UL)) +#define bFM4_MFS6_UART_ESCR_PEN *((volatile uint8_t *)(0x4270C090UL)) +#define bFM_MFS6_UART_ESCR_INV *((volatile uint8_t *)(0x4270C094UL)) +#define bFM4_MFS6_UART_ESCR_INV *((volatile uint8_t *)(0x4270C094UL)) +#define bFM_MFS6_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) +#define bFM4_MFS6_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270C098UL)) +#define bFM_MFS6_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270C09CUL)) +#define bFM4_MFS6_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270C09CUL)) + +#define bFM_MFS6_UART_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM4_MFS6_UART_FCR_FE1 *((volatile uint8_t *)(0x4270C280UL)) +#define bFM_MFS6_UART_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM4_MFS6_UART_FCR_FE2 *((volatile uint8_t *)(0x4270C284UL)) +#define bFM_MFS6_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM4_MFS6_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270C288UL)) +#define bFM_MFS6_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM4_MFS6_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270C28CUL)) +#define bFM_MFS6_UART_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM4_MFS6_UART_FCR_FSET *((volatile uint8_t *)(0x4270C290UL)) +#define bFM_MFS6_UART_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM4_MFS6_UART_FCR_FLD *((volatile uint8_t *)(0x4270C294UL)) +#define bFM_MFS6_UART_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM4_MFS6_UART_FCR_FLST *((volatile uint8_t *)(0x4270C298UL)) +#define bFM_MFS6_UART_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM4_MFS6_UART_FCR_FSEL *((volatile uint8_t *)(0x4270C2A0UL)) +#define bFM_MFS6_UART_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM4_MFS6_UART_FCR_FTIE *((volatile uint8_t *)(0x4270C2A4UL)) +#define bFM_MFS6_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM4_MFS6_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270C2A8UL)) +#define bFM_MFS6_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM4_MFS6_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270C2ACUL)) +#define bFM_MFS6_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) +#define bFM4_MFS6_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270C2B0UL)) + +#define bFM_MFS6_UART_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM4_MFS6_UART_SCR_TXE *((volatile uint8_t *)(0x4270C020UL)) +#define bFM_MFS6_UART_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM4_MFS6_UART_SCR_RXE *((volatile uint8_t *)(0x4270C024UL)) +#define bFM_MFS6_UART_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM4_MFS6_UART_SCR_TBIE *((volatile uint8_t *)(0x4270C028UL)) +#define bFM_MFS6_UART_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM4_MFS6_UART_SCR_TIE *((volatile uint8_t *)(0x4270C02CUL)) +#define bFM_MFS6_UART_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM4_MFS6_UART_SCR_RIE *((volatile uint8_t *)(0x4270C030UL)) +#define bFM_MFS6_UART_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) +#define bFM4_MFS6_UART_SCR_UPCL *((volatile uint8_t *)(0x4270C03CUL)) + +#define bFM_MFS6_UART_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM4_MFS6_UART_SMR_SOE *((volatile uint8_t *)(0x4270C000UL)) +#define bFM_MFS6_UART_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM4_MFS6_UART_SMR_BDS *((volatile uint8_t *)(0x4270C008UL)) +#define bFM_MFS6_UART_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) +#define bFM4_MFS6_UART_SMR_SBL *((volatile uint8_t *)(0x4270C00CUL)) + +#define bFM_MFS6_UART_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM4_MFS6_UART_SSR_TBI *((volatile uint8_t *)(0x4270C0A0UL)) +#define bFM_MFS6_UART_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM4_MFS6_UART_SSR_TDRE *((volatile uint8_t *)(0x4270C0A4UL)) +#define bFM_MFS6_UART_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM4_MFS6_UART_SSR_RDRF *((volatile uint8_t *)(0x4270C0A8UL)) +#define bFM_MFS6_UART_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM4_MFS6_UART_SSR_ORE *((volatile uint8_t *)(0x4270C0ACUL)) +#define bFM_MFS6_UART_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM4_MFS6_UART_SSR_FRE *((volatile uint8_t *)(0x4270C0B0UL)) +#define bFM_MFS6_UART_SSR_PE *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM4_MFS6_UART_SSR_PE *((volatile uint8_t *)(0x4270C0B4UL)) +#define bFM_MFS6_UART_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) +#define bFM4_MFS6_UART_SSR_REC *((volatile uint8_t *)(0x4270C0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS7 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS7_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270E094UL)) +#define bFM4_MFS7_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x4270E094UL)) +#define bFM_MFS7_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_CSIO_ESCR_L3 *((volatile uint8_t *)(0x4270E098UL)) +#define bFM_MFS7_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270E09CUL)) +#define bFM4_MFS7_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4270E09CUL)) + +#define bFM_MFS7_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_CSIO_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_CSIO_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_CSIO_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_CSIO_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_CSIO_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_CSIO_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_CSIO_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270E480UL)) +#define bFM4_MFS7_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x4270E480UL)) +#define bFM_MFS7_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270E498UL)) +#define bFM4_MFS7_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x4270E498UL)) +#define bFM_MFS7_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270E49CUL)) +#define bFM4_MFS7_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4270E49CUL)) +#define bFM_MFS7_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270E4A0UL)) +#define bFM4_MFS7_CSIO_SACSR_TINT *((volatile uint8_t *)(0x4270E4A0UL)) +#define bFM_MFS7_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270E4ACUL)) +#define bFM4_MFS7_CSIO_SACSR_CSE *((volatile uint8_t *)(0x4270E4ACUL)) +#define bFM_MFS7_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270E4B0UL)) +#define bFM4_MFS7_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x4270E4B0UL)) +#define bFM_MFS7_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270E4B4UL)) +#define bFM4_MFS7_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x4270E4B4UL)) + +#define bFM_MFS7_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_CSIO_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_CSIO_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_CSIO_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_CSIO_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_CSIO_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270E034UL)) +#define bFM4_MFS7_CSIO_SCR_SPI *((volatile uint8_t *)(0x4270E034UL)) +#define bFM_MFS7_CSIO_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM4_MFS7_CSIO_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM_MFS7_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270E600UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x4270E600UL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270E604UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x4270E604UL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270E608UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x4270E608UL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270E60CUL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4270E60CUL)) +#define bFM_MFS7_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270E610UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x4270E610UL)) +#define bFM_MFS7_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270E614UL)) +#define bFM4_MFS7_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x4270E614UL)) +#define bFM_MFS7_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270E624UL)) +#define bFM4_MFS7_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x4270E624UL)) + +#define bFM_MFS7_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270E694UL)) +#define bFM4_MFS7_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x4270E694UL)) +#define bFM_MFS7_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270E698UL)) +#define bFM4_MFS7_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x4270E698UL)) +#define bFM_MFS7_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270E69CUL)) +#define bFM4_MFS7_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4270E69CUL)) + +#define bFM_MFS7_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270E6B4UL)) +#define bFM4_MFS7_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x4270E6B4UL)) +#define bFM_MFS7_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270E6B8UL)) +#define bFM4_MFS7_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x4270E6B8UL)) +#define bFM_MFS7_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270E6BCUL)) +#define bFM4_MFS7_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x4270E6BCUL)) + +#define bFM_MFS7_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270E714UL)) +#define bFM4_MFS7_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x4270E714UL)) +#define bFM_MFS7_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270E718UL)) +#define bFM4_MFS7_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x4270E718UL)) +#define bFM_MFS7_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270E71CUL)) +#define bFM4_MFS7_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4270E71CUL)) + +#define bFM_MFS7_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM4_MFS7_CSIO_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM_MFS7_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270E004UL)) +#define bFM4_MFS7_CSIO_SMR_SCKE *((volatile uint8_t *)(0x4270E004UL)) +#define bFM_MFS7_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM4_MFS7_CSIO_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM_MFS7_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4270E00CUL)) + +#define bFM_MFS7_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_CSIO_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_CSIO_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_CSIO_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_CSIO_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_CSIO_SSR_AWC *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_CSIO_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_CSIO_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + +#define bFM_MFS7_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270E3A0UL)) +#define bFM4_MFS7_I2C_EIBCR_BEC *((volatile uint8_t *)(0x4270E3A0UL)) +#define bFM_MFS7_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270E3A4UL)) +#define bFM4_MFS7_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x4270E3A4UL)) +#define bFM_MFS7_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270E3A8UL)) +#define bFM4_MFS7_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x4270E3A8UL)) +#define bFM_MFS7_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270E3ACUL)) +#define bFM4_MFS7_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x4270E3ACUL)) +#define bFM_MFS7_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270E3B0UL)) +#define bFM4_MFS7_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x4270E3B0UL)) +#define bFM_MFS7_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270E3B4UL)) +#define bFM4_MFS7_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x4270E3B4UL)) + +#define bFM_MFS7_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_I2C_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_I2C_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_I2C_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_I2C_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_I2C_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_I2C_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_I2C_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_I2C_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_I2C_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_I2C_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_I2C_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_I2C_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_I2C_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_I2C_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_I2C_IBCR_INT *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_I2C_IBCR_INT *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_I2C_IBCR_BER *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_I2C_IBCR_BER *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_I2C_IBCR_INTE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_I2C_IBCR_WSEL *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270E034UL)) +#define bFM4_MFS7_I2C_IBCR_ACKE *((volatile uint8_t *)(0x4270E034UL)) +#define bFM_MFS7_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270E038UL)) +#define bFM4_MFS7_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x4270E038UL)) +#define bFM_MFS7_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_I2C_IBCR_MSS *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_I2C_IBSR_BB *((volatile uint8_t *)(0x4270E080UL)) +#define bFM4_MFS7_I2C_IBSR_BB *((volatile uint8_t *)(0x4270E080UL)) +#define bFM_MFS7_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270E084UL)) +#define bFM4_MFS7_I2C_IBSR_SPC *((volatile uint8_t *)(0x4270E084UL)) +#define bFM_MFS7_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270E088UL)) +#define bFM4_MFS7_I2C_IBSR_RSC *((volatile uint8_t *)(0x4270E088UL)) +#define bFM_MFS7_I2C_IBSR_AL *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM4_MFS7_I2C_IBSR_AL *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM_MFS7_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270E090UL)) +#define bFM4_MFS7_I2C_IBSR_TRX *((volatile uint8_t *)(0x4270E090UL)) +#define bFM_MFS7_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270E094UL)) +#define bFM4_MFS7_I2C_IBSR_RSA *((volatile uint8_t *)(0x4270E094UL)) +#define bFM_MFS7_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_I2C_IBSR_RACK *((volatile uint8_t *)(0x4270E098UL)) +#define bFM_MFS7_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270E09CUL)) +#define bFM4_MFS7_I2C_IBSR_FBT *((volatile uint8_t *)(0x4270E09CUL)) + +#define bFM_MFS7_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270E21CUL)) +#define bFM4_MFS7_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4270E21CUL)) + +#define bFM_MFS7_I2C_ISMK_EN *((volatile uint8_t *)(0x4270E23CUL)) +#define bFM4_MFS7_I2C_ISMK_EN *((volatile uint8_t *)(0x4270E23CUL)) + +#define bFM_MFS7_I2C_SMR_TIE *((volatile uint8_t *)(0x4270E008UL)) +#define bFM4_MFS7_I2C_SMR_TIE *((volatile uint8_t *)(0x4270E008UL)) +#define bFM_MFS7_I2C_SMR_RIE *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_I2C_SMR_RIE *((volatile uint8_t *)(0x4270E00CUL)) + +#define bFM_MFS7_I2C_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_I2C_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_I2C_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_I2C_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_I2C_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_I2C_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_I2C_SSR_TBIE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_I2C_SSR_DMA *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM4_MFS7_I2C_SSR_DMA *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM_MFS7_I2C_SSR_TSET *((volatile uint8_t *)(0x4270E0B8UL)) +#define bFM4_MFS7_I2C_SSR_TSET *((volatile uint8_t *)(0x4270E0B8UL)) +#define bFM_MFS7_I2C_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_I2C_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + +#define bFM_MFS7_LIN_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) +#define bFM4_MFS7_LIN_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) + +#define bFM_MFS7_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270E090UL)) +#define bFM4_MFS7_LIN_ESCR_LBIE *((volatile uint8_t *)(0x4270E090UL)) +#define bFM_MFS7_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_LIN_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) + +#define bFM_MFS7_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_LIN_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_LIN_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_LIN_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_LIN_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_LIN_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_LIN_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_LIN_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_LIN_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_LIN_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_LIN_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_LIN_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_LIN_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_LIN_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_LIN_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_LIN_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_LIN_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_LIN_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_LIN_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_LIN_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_LIN_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_LIN_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_LIN_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_LIN_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_LIN_SCR_LBR *((volatile uint8_t *)(0x4270E034UL)) +#define bFM4_MFS7_LIN_SCR_LBR *((volatile uint8_t *)(0x4270E034UL)) +#define bFM_MFS7_LIN_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM4_MFS7_LIN_SCR_MS *((volatile uint8_t *)(0x4270E038UL)) +#define bFM_MFS7_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_LIN_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_LIN_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM4_MFS7_LIN_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM_MFS7_LIN_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_LIN_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM_MFS7_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270E010UL)) +#define bFM4_MFS7_LIN_SMR_WUCR *((volatile uint8_t *)(0x4270E010UL)) + +#define bFM_MFS7_LIN_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_LIN_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_LIN_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_LIN_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_LIN_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_LIN_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_LIN_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_LIN_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_LIN_SSR_LBD *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM4_MFS7_LIN_SSR_LBD *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM_MFS7_LIN_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_LIN_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + +#define bFM_MFS7_UART_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) +#define bFM4_MFS7_UART_BGR_EXT *((volatile uint8_t *)(0x4270E1BCUL)) + +#define bFM_MFS7_UART_ESCR_P *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM4_MFS7_UART_ESCR_P *((volatile uint8_t *)(0x4270E08CUL)) +#define bFM_MFS7_UART_ESCR_PEN *((volatile uint8_t *)(0x4270E090UL)) +#define bFM4_MFS7_UART_ESCR_PEN *((volatile uint8_t *)(0x4270E090UL)) +#define bFM_MFS7_UART_ESCR_INV *((volatile uint8_t *)(0x4270E094UL)) +#define bFM4_MFS7_UART_ESCR_INV *((volatile uint8_t *)(0x4270E094UL)) +#define bFM_MFS7_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) +#define bFM4_MFS7_UART_ESCR_ESBL *((volatile uint8_t *)(0x4270E098UL)) +#define bFM_MFS7_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270E09CUL)) +#define bFM4_MFS7_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4270E09CUL)) + +#define bFM_MFS7_UART_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM4_MFS7_UART_FCR_FE1 *((volatile uint8_t *)(0x4270E280UL)) +#define bFM_MFS7_UART_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM4_MFS7_UART_FCR_FE2 *((volatile uint8_t *)(0x4270E284UL)) +#define bFM_MFS7_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM4_MFS7_UART_FCR_FCL1 *((volatile uint8_t *)(0x4270E288UL)) +#define bFM_MFS7_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM4_MFS7_UART_FCR_FCL2 *((volatile uint8_t *)(0x4270E28CUL)) +#define bFM_MFS7_UART_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM4_MFS7_UART_FCR_FSET *((volatile uint8_t *)(0x4270E290UL)) +#define bFM_MFS7_UART_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM4_MFS7_UART_FCR_FLD *((volatile uint8_t *)(0x4270E294UL)) +#define bFM_MFS7_UART_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM4_MFS7_UART_FCR_FLST *((volatile uint8_t *)(0x4270E298UL)) +#define bFM_MFS7_UART_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM4_MFS7_UART_FCR_FSEL *((volatile uint8_t *)(0x4270E2A0UL)) +#define bFM_MFS7_UART_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM4_MFS7_UART_FCR_FTIE *((volatile uint8_t *)(0x4270E2A4UL)) +#define bFM_MFS7_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM4_MFS7_UART_FCR_FDRQ *((volatile uint8_t *)(0x4270E2A8UL)) +#define bFM_MFS7_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM4_MFS7_UART_FCR_FRIIE *((volatile uint8_t *)(0x4270E2ACUL)) +#define bFM_MFS7_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) +#define bFM4_MFS7_UART_FCR_FLSTE *((volatile uint8_t *)(0x4270E2B0UL)) + +#define bFM_MFS7_UART_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM4_MFS7_UART_SCR_TXE *((volatile uint8_t *)(0x4270E020UL)) +#define bFM_MFS7_UART_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM4_MFS7_UART_SCR_RXE *((volatile uint8_t *)(0x4270E024UL)) +#define bFM_MFS7_UART_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM4_MFS7_UART_SCR_TBIE *((volatile uint8_t *)(0x4270E028UL)) +#define bFM_MFS7_UART_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM4_MFS7_UART_SCR_TIE *((volatile uint8_t *)(0x4270E02CUL)) +#define bFM_MFS7_UART_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM4_MFS7_UART_SCR_RIE *((volatile uint8_t *)(0x4270E030UL)) +#define bFM_MFS7_UART_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) +#define bFM4_MFS7_UART_SCR_UPCL *((volatile uint8_t *)(0x4270E03CUL)) + +#define bFM_MFS7_UART_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM4_MFS7_UART_SMR_SOE *((volatile uint8_t *)(0x4270E000UL)) +#define bFM_MFS7_UART_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM4_MFS7_UART_SMR_BDS *((volatile uint8_t *)(0x4270E008UL)) +#define bFM_MFS7_UART_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) +#define bFM4_MFS7_UART_SMR_SBL *((volatile uint8_t *)(0x4270E00CUL)) + +#define bFM_MFS7_UART_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM4_MFS7_UART_SSR_TBI *((volatile uint8_t *)(0x4270E0A0UL)) +#define bFM_MFS7_UART_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM4_MFS7_UART_SSR_TDRE *((volatile uint8_t *)(0x4270E0A4UL)) +#define bFM_MFS7_UART_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM4_MFS7_UART_SSR_RDRF *((volatile uint8_t *)(0x4270E0A8UL)) +#define bFM_MFS7_UART_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM4_MFS7_UART_SSR_ORE *((volatile uint8_t *)(0x4270E0ACUL)) +#define bFM_MFS7_UART_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM4_MFS7_UART_SSR_FRE *((volatile uint8_t *)(0x4270E0B0UL)) +#define bFM_MFS7_UART_SSR_PE *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM4_MFS7_UART_SSR_PE *((volatile uint8_t *)(0x4270E0B4UL)) +#define bFM_MFS7_UART_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) +#define bFM4_MFS7_UART_SSR_REC *((volatile uint8_t *)(0x4270E0BCUL)) + + +/******************************************************************************* +* MFS Registers MFS8 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS8_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42710094UL)) +#define bFM4_MFS8_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42710094UL)) +#define bFM_MFS8_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42710098UL)) +#define bFM_MFS8_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271009CUL)) +#define bFM4_MFS8_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271009CUL)) + +#define bFM_MFS8_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_CSIO_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_CSIO_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_CSIO_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_CSIO_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_CSIO_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_CSIO_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42710480UL)) +#define bFM4_MFS8_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42710480UL)) +#define bFM_MFS8_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42710498UL)) +#define bFM4_MFS8_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42710498UL)) +#define bFM_MFS8_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271049CUL)) +#define bFM4_MFS8_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271049CUL)) +#define bFM_MFS8_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427104A0UL)) +#define bFM4_MFS8_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427104A0UL)) +#define bFM_MFS8_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427104ACUL)) +#define bFM4_MFS8_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427104ACUL)) +#define bFM_MFS8_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427104B0UL)) +#define bFM4_MFS8_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427104B0UL)) +#define bFM_MFS8_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427104B4UL)) +#define bFM4_MFS8_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427104B4UL)) + +#define bFM_MFS8_CSIO_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_CSIO_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_CSIO_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_CSIO_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_CSIO_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_CSIO_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_CSIO_SCR_SPI *((volatile uint8_t *)(0x42710034UL)) +#define bFM4_MFS8_CSIO_SCR_SPI *((volatile uint8_t *)(0x42710034UL)) +#define bFM_MFS8_CSIO_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM4_MFS8_CSIO_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM_MFS8_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42710600UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42710600UL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42710604UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42710604UL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42710608UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42710608UL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271060CUL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271060CUL)) +#define bFM_MFS8_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42710610UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42710610UL)) +#define bFM_MFS8_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42710614UL)) +#define bFM4_MFS8_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42710614UL)) +#define bFM_MFS8_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42710624UL)) +#define bFM4_MFS8_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42710624UL)) + +#define bFM_MFS8_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42710694UL)) +#define bFM4_MFS8_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42710694UL)) +#define bFM_MFS8_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42710698UL)) +#define bFM4_MFS8_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42710698UL)) +#define bFM_MFS8_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271069CUL)) +#define bFM4_MFS8_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271069CUL)) + +#define bFM_MFS8_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427106B4UL)) +#define bFM4_MFS8_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427106B4UL)) +#define bFM_MFS8_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427106B8UL)) +#define bFM4_MFS8_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427106B8UL)) +#define bFM_MFS8_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427106BCUL)) +#define bFM4_MFS8_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427106BCUL)) + +#define bFM_MFS8_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42710714UL)) +#define bFM4_MFS8_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42710714UL)) +#define bFM_MFS8_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42710718UL)) +#define bFM4_MFS8_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42710718UL)) +#define bFM_MFS8_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271071CUL)) +#define bFM4_MFS8_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271071CUL)) + +#define bFM_MFS8_CSIO_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM4_MFS8_CSIO_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM_MFS8_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42710004UL)) +#define bFM4_MFS8_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42710004UL)) +#define bFM_MFS8_CSIO_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM4_MFS8_CSIO_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM_MFS8_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271000CUL)) + +#define bFM_MFS8_CSIO_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_CSIO_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_CSIO_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_CSIO_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_CSIO_SSR_AWC *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_CSIO_SSR_AWC *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_CSIO_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_CSIO_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + +#define bFM_MFS8_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427103A0UL)) +#define bFM4_MFS8_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427103A0UL)) +#define bFM_MFS8_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427103A4UL)) +#define bFM4_MFS8_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427103A4UL)) +#define bFM_MFS8_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427103A8UL)) +#define bFM4_MFS8_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427103A8UL)) +#define bFM_MFS8_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427103ACUL)) +#define bFM4_MFS8_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427103ACUL)) +#define bFM_MFS8_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427103B0UL)) +#define bFM4_MFS8_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427103B0UL)) +#define bFM_MFS8_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427103B4UL)) +#define bFM4_MFS8_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427103B4UL)) + +#define bFM_MFS8_I2C_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_I2C_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_I2C_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_I2C_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_I2C_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_I2C_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_I2C_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_I2C_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_I2C_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_I2C_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_I2C_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_I2C_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_I2C_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_I2C_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_I2C_IBCR_INT *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_I2C_IBCR_INT *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_I2C_IBCR_BER *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_I2C_IBCR_BER *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_I2C_IBCR_INTE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_I2C_IBCR_INTE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42710034UL)) +#define bFM4_MFS8_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42710034UL)) +#define bFM_MFS8_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42710038UL)) +#define bFM4_MFS8_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42710038UL)) +#define bFM_MFS8_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_I2C_IBSR_BB *((volatile uint8_t *)(0x42710080UL)) +#define bFM4_MFS8_I2C_IBSR_BB *((volatile uint8_t *)(0x42710080UL)) +#define bFM_MFS8_I2C_IBSR_SPC *((volatile uint8_t *)(0x42710084UL)) +#define bFM4_MFS8_I2C_IBSR_SPC *((volatile uint8_t *)(0x42710084UL)) +#define bFM_MFS8_I2C_IBSR_RSC *((volatile uint8_t *)(0x42710088UL)) +#define bFM4_MFS8_I2C_IBSR_RSC *((volatile uint8_t *)(0x42710088UL)) +#define bFM_MFS8_I2C_IBSR_AL *((volatile uint8_t *)(0x4271008CUL)) +#define bFM4_MFS8_I2C_IBSR_AL *((volatile uint8_t *)(0x4271008CUL)) +#define bFM_MFS8_I2C_IBSR_TRX *((volatile uint8_t *)(0x42710090UL)) +#define bFM4_MFS8_I2C_IBSR_TRX *((volatile uint8_t *)(0x42710090UL)) +#define bFM_MFS8_I2C_IBSR_RSA *((volatile uint8_t *)(0x42710094UL)) +#define bFM4_MFS8_I2C_IBSR_RSA *((volatile uint8_t *)(0x42710094UL)) +#define bFM_MFS8_I2C_IBSR_RACK *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_I2C_IBSR_RACK *((volatile uint8_t *)(0x42710098UL)) +#define bFM_MFS8_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271009CUL)) +#define bFM4_MFS8_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271009CUL)) + +#define bFM_MFS8_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271021CUL)) +#define bFM4_MFS8_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271021CUL)) + +#define bFM_MFS8_I2C_ISMK_EN *((volatile uint8_t *)(0x4271023CUL)) +#define bFM4_MFS8_I2C_ISMK_EN *((volatile uint8_t *)(0x4271023CUL)) + +#define bFM_MFS8_I2C_SMR_TIE *((volatile uint8_t *)(0x42710008UL)) +#define bFM4_MFS8_I2C_SMR_TIE *((volatile uint8_t *)(0x42710008UL)) +#define bFM_MFS8_I2C_SMR_RIE *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_I2C_SMR_RIE *((volatile uint8_t *)(0x4271000CUL)) + +#define bFM_MFS8_I2C_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_I2C_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_I2C_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_I2C_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_I2C_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_I2C_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_I2C_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_I2C_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_I2C_SSR_TBIE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_I2C_SSR_TBIE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_I2C_SSR_DMA *((volatile uint8_t *)(0x427100B4UL)) +#define bFM4_MFS8_I2C_SSR_DMA *((volatile uint8_t *)(0x427100B4UL)) +#define bFM_MFS8_I2C_SSR_TSET *((volatile uint8_t *)(0x427100B8UL)) +#define bFM4_MFS8_I2C_SSR_TSET *((volatile uint8_t *)(0x427100B8UL)) +#define bFM_MFS8_I2C_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_I2C_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + +#define bFM_MFS8_LIN_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) +#define bFM4_MFS8_LIN_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) + +#define bFM_MFS8_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42710090UL)) +#define bFM4_MFS8_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42710090UL)) +#define bFM_MFS8_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) + +#define bFM_MFS8_LIN_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_LIN_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_LIN_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_LIN_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_LIN_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_LIN_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_LIN_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_LIN_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_LIN_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_LIN_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_LIN_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_LIN_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_LIN_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_LIN_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_LIN_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_LIN_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_LIN_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_LIN_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_LIN_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_LIN_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_LIN_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_LIN_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_LIN_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_LIN_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_LIN_SCR_LBR *((volatile uint8_t *)(0x42710034UL)) +#define bFM4_MFS8_LIN_SCR_LBR *((volatile uint8_t *)(0x42710034UL)) +#define bFM_MFS8_LIN_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM4_MFS8_LIN_SCR_MS *((volatile uint8_t *)(0x42710038UL)) +#define bFM_MFS8_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_LIN_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM4_MFS8_LIN_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM_MFS8_LIN_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_LIN_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) +#define bFM_MFS8_LIN_SMR_WUCR *((volatile uint8_t *)(0x42710010UL)) +#define bFM4_MFS8_LIN_SMR_WUCR *((volatile uint8_t *)(0x42710010UL)) + +#define bFM_MFS8_LIN_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_LIN_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_LIN_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_LIN_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_LIN_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_LIN_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_LIN_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_LIN_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_LIN_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_LIN_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_LIN_SSR_LBD *((volatile uint8_t *)(0x427100B4UL)) +#define bFM4_MFS8_LIN_SSR_LBD *((volatile uint8_t *)(0x427100B4UL)) +#define bFM_MFS8_LIN_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_LIN_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + +#define bFM_MFS8_UART_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) +#define bFM4_MFS8_UART_BGR_EXT *((volatile uint8_t *)(0x427101BCUL)) + +#define bFM_MFS8_UART_ESCR_P *((volatile uint8_t *)(0x4271008CUL)) +#define bFM4_MFS8_UART_ESCR_P *((volatile uint8_t *)(0x4271008CUL)) +#define bFM_MFS8_UART_ESCR_PEN *((volatile uint8_t *)(0x42710090UL)) +#define bFM4_MFS8_UART_ESCR_PEN *((volatile uint8_t *)(0x42710090UL)) +#define bFM_MFS8_UART_ESCR_INV *((volatile uint8_t *)(0x42710094UL)) +#define bFM4_MFS8_UART_ESCR_INV *((volatile uint8_t *)(0x42710094UL)) +#define bFM_MFS8_UART_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) +#define bFM4_MFS8_UART_ESCR_ESBL *((volatile uint8_t *)(0x42710098UL)) +#define bFM_MFS8_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271009CUL)) +#define bFM4_MFS8_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271009CUL)) + +#define bFM_MFS8_UART_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM4_MFS8_UART_FCR_FE1 *((volatile uint8_t *)(0x42710280UL)) +#define bFM_MFS8_UART_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM4_MFS8_UART_FCR_FE2 *((volatile uint8_t *)(0x42710284UL)) +#define bFM_MFS8_UART_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM4_MFS8_UART_FCR_FCL1 *((volatile uint8_t *)(0x42710288UL)) +#define bFM_MFS8_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM4_MFS8_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271028CUL)) +#define bFM_MFS8_UART_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM4_MFS8_UART_FCR_FSET *((volatile uint8_t *)(0x42710290UL)) +#define bFM_MFS8_UART_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM4_MFS8_UART_FCR_FLD *((volatile uint8_t *)(0x42710294UL)) +#define bFM_MFS8_UART_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM4_MFS8_UART_FCR_FLST *((volatile uint8_t *)(0x42710298UL)) +#define bFM_MFS8_UART_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM4_MFS8_UART_FCR_FSEL *((volatile uint8_t *)(0x427102A0UL)) +#define bFM_MFS8_UART_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM4_MFS8_UART_FCR_FTIE *((volatile uint8_t *)(0x427102A4UL)) +#define bFM_MFS8_UART_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM4_MFS8_UART_FCR_FDRQ *((volatile uint8_t *)(0x427102A8UL)) +#define bFM_MFS8_UART_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM4_MFS8_UART_FCR_FRIIE *((volatile uint8_t *)(0x427102ACUL)) +#define bFM_MFS8_UART_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) +#define bFM4_MFS8_UART_FCR_FLSTE *((volatile uint8_t *)(0x427102B0UL)) + +#define bFM_MFS8_UART_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM4_MFS8_UART_SCR_TXE *((volatile uint8_t *)(0x42710020UL)) +#define bFM_MFS8_UART_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM4_MFS8_UART_SCR_RXE *((volatile uint8_t *)(0x42710024UL)) +#define bFM_MFS8_UART_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM4_MFS8_UART_SCR_TBIE *((volatile uint8_t *)(0x42710028UL)) +#define bFM_MFS8_UART_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM4_MFS8_UART_SCR_TIE *((volatile uint8_t *)(0x4271002CUL)) +#define bFM_MFS8_UART_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM4_MFS8_UART_SCR_RIE *((volatile uint8_t *)(0x42710030UL)) +#define bFM_MFS8_UART_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) +#define bFM4_MFS8_UART_SCR_UPCL *((volatile uint8_t *)(0x4271003CUL)) + +#define bFM_MFS8_UART_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM4_MFS8_UART_SMR_SOE *((volatile uint8_t *)(0x42710000UL)) +#define bFM_MFS8_UART_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM4_MFS8_UART_SMR_BDS *((volatile uint8_t *)(0x42710008UL)) +#define bFM_MFS8_UART_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) +#define bFM4_MFS8_UART_SMR_SBL *((volatile uint8_t *)(0x4271000CUL)) + +#define bFM_MFS8_UART_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM4_MFS8_UART_SSR_TBI *((volatile uint8_t *)(0x427100A0UL)) +#define bFM_MFS8_UART_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM4_MFS8_UART_SSR_TDRE *((volatile uint8_t *)(0x427100A4UL)) +#define bFM_MFS8_UART_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM4_MFS8_UART_SSR_RDRF *((volatile uint8_t *)(0x427100A8UL)) +#define bFM_MFS8_UART_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM4_MFS8_UART_SSR_ORE *((volatile uint8_t *)(0x427100ACUL)) +#define bFM_MFS8_UART_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM4_MFS8_UART_SSR_FRE *((volatile uint8_t *)(0x427100B0UL)) +#define bFM_MFS8_UART_SSR_PE *((volatile uint8_t *)(0x427100B4UL)) +#define bFM4_MFS8_UART_SSR_PE *((volatile uint8_t *)(0x427100B4UL)) +#define bFM_MFS8_UART_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) +#define bFM4_MFS8_UART_SSR_REC *((volatile uint8_t *)(0x427100BCUL)) + + +/******************************************************************************* +* MFS Registers MFS9 +* Bitband Section +*******************************************************************************/ +#define bFM_MFS9_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42712094UL)) +#define bFM4_MFS9_CSIO_ESCR_CSFE *((volatile uint8_t *)(0x42712094UL)) +#define bFM_MFS9_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_CSIO_ESCR_L3 *((volatile uint8_t *)(0x42712098UL)) +#define bFM_MFS9_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271209CUL)) +#define bFM4_MFS9_CSIO_ESCR_SOP *((volatile uint8_t *)(0x4271209CUL)) + +#define bFM_MFS9_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_CSIO_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_CSIO_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_CSIO_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_CSIO_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_CSIO_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_CSIO_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_CSIO_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_CSIO_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_CSIO_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_CSIO_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_CSIO_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_CSIO_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_CSIO_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_CSIO_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_CSIO_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42712480UL)) +#define bFM4_MFS9_CSIO_SACSR_TMRE *((volatile uint8_t *)(0x42712480UL)) +#define bFM_MFS9_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42712498UL)) +#define bFM4_MFS9_CSIO_SACSR_TSYNE *((volatile uint8_t *)(0x42712498UL)) +#define bFM_MFS9_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271249CUL)) +#define bFM4_MFS9_CSIO_SACSR_TINTE *((volatile uint8_t *)(0x4271249CUL)) +#define bFM_MFS9_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427124A0UL)) +#define bFM4_MFS9_CSIO_SACSR_TINT *((volatile uint8_t *)(0x427124A0UL)) +#define bFM_MFS9_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427124ACUL)) +#define bFM4_MFS9_CSIO_SACSR_CSE *((volatile uint8_t *)(0x427124ACUL)) +#define bFM_MFS9_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427124B0UL)) +#define bFM4_MFS9_CSIO_SACSR_CSEIE *((volatile uint8_t *)(0x427124B0UL)) +#define bFM_MFS9_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427124B4UL)) +#define bFM4_MFS9_CSIO_SACSR_TBEEN *((volatile uint8_t *)(0x427124B4UL)) + +#define bFM_MFS9_CSIO_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_CSIO_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_CSIO_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_CSIO_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_CSIO_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_CSIO_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_CSIO_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_CSIO_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_CSIO_SCR_SPI *((volatile uint8_t *)(0x42712034UL)) +#define bFM4_MFS9_CSIO_SCR_SPI *((volatile uint8_t *)(0x42712034UL)) +#define bFM_MFS9_CSIO_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM4_MFS9_CSIO_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM_MFS9_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_CSIO_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42712600UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSOE *((volatile uint8_t *)(0x42712600UL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42712604UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN0 *((volatile uint8_t *)(0x42712604UL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42712608UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN1 *((volatile uint8_t *)(0x42712608UL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271260CUL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN2 *((volatile uint8_t *)(0x4271260CUL)) +#define bFM_MFS9_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42712610UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSEN3 *((volatile uint8_t *)(0x42712610UL)) +#define bFM_MFS9_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42712614UL)) +#define bFM4_MFS9_CSIO_SCSCR_CSLVL *((volatile uint8_t *)(0x42712614UL)) +#define bFM_MFS9_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42712624UL)) +#define bFM4_MFS9_CSIO_SCSCR_SCAM *((volatile uint8_t *)(0x42712624UL)) + +#define bFM_MFS9_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42712694UL)) +#define bFM4_MFS9_CSIO_SCSFR0_CS1SPI *((volatile uint8_t *)(0x42712694UL)) +#define bFM_MFS9_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42712698UL)) +#define bFM4_MFS9_CSIO_SCSFR0_CS1SCINV *((volatile uint8_t *)(0x42712698UL)) +#define bFM_MFS9_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271269CUL)) +#define bFM4_MFS9_CSIO_SCSFR0_CS1CSLVL *((volatile uint8_t *)(0x4271269CUL)) + +#define bFM_MFS9_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427126B4UL)) +#define bFM4_MFS9_CSIO_SCSFR1_CS2SPI *((volatile uint8_t *)(0x427126B4UL)) +#define bFM_MFS9_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427126B8UL)) +#define bFM4_MFS9_CSIO_SCSFR1_CS2SCINV *((volatile uint8_t *)(0x427126B8UL)) +#define bFM_MFS9_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427126BCUL)) +#define bFM4_MFS9_CSIO_SCSFR1_CS2CSLVL *((volatile uint8_t *)(0x427126BCUL)) + +#define bFM_MFS9_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42712714UL)) +#define bFM4_MFS9_CSIO_SCSFR2_CS3SPI *((volatile uint8_t *)(0x42712714UL)) +#define bFM_MFS9_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42712718UL)) +#define bFM4_MFS9_CSIO_SCSFR2_CS3SCINV *((volatile uint8_t *)(0x42712718UL)) +#define bFM_MFS9_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271271CUL)) +#define bFM4_MFS9_CSIO_SCSFR2_CS3CSLVL *((volatile uint8_t *)(0x4271271CUL)) + +#define bFM_MFS9_CSIO_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM4_MFS9_CSIO_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM_MFS9_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42712004UL)) +#define bFM4_MFS9_CSIO_SMR_SCKE *((volatile uint8_t *)(0x42712004UL)) +#define bFM_MFS9_CSIO_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM4_MFS9_CSIO_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM_MFS9_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_CSIO_SMR_SCINV *((volatile uint8_t *)(0x4271200CUL)) + +#define bFM_MFS9_CSIO_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_CSIO_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_CSIO_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_CSIO_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_CSIO_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_CSIO_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_CSIO_SSR_AWC *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_CSIO_SSR_AWC *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_CSIO_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_CSIO_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + +#define bFM_MFS9_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427123A0UL)) +#define bFM4_MFS9_I2C_EIBCR_BEC *((volatile uint8_t *)(0x427123A0UL)) +#define bFM_MFS9_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427123A4UL)) +#define bFM4_MFS9_I2C_EIBCR_SOCE *((volatile uint8_t *)(0x427123A4UL)) +#define bFM_MFS9_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427123A8UL)) +#define bFM4_MFS9_I2C_EIBCR_SCLC *((volatile uint8_t *)(0x427123A8UL)) +#define bFM_MFS9_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427123ACUL)) +#define bFM4_MFS9_I2C_EIBCR_SDAC *((volatile uint8_t *)(0x427123ACUL)) +#define bFM_MFS9_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427123B0UL)) +#define bFM4_MFS9_I2C_EIBCR_SCLS *((volatile uint8_t *)(0x427123B0UL)) +#define bFM_MFS9_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427123B4UL)) +#define bFM4_MFS9_I2C_EIBCR_SDAS *((volatile uint8_t *)(0x427123B4UL)) + +#define bFM_MFS9_I2C_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_I2C_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_I2C_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_I2C_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_I2C_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_I2C_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_I2C_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_I2C_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_I2C_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_I2C_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_I2C_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_I2C_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_I2C_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_I2C_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_I2C_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_I2C_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_I2C_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_I2C_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_I2C_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_I2C_IBCR_INT *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_I2C_IBCR_INT *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_I2C_IBCR_BER *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_I2C_IBCR_BER *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_I2C_IBCR_INTE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_I2C_IBCR_INTE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_I2C_IBCR_CNDE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_I2C_IBCR_WSEL *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42712034UL)) +#define bFM4_MFS9_I2C_IBCR_ACKE *((volatile uint8_t *)(0x42712034UL)) +#define bFM_MFS9_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42712038UL)) +#define bFM4_MFS9_I2C_IBCR_ACT_SCC *((volatile uint8_t *)(0x42712038UL)) +#define bFM_MFS9_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_I2C_IBCR_MSS *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_I2C_IBSR_BB *((volatile uint8_t *)(0x42712080UL)) +#define bFM4_MFS9_I2C_IBSR_BB *((volatile uint8_t *)(0x42712080UL)) +#define bFM_MFS9_I2C_IBSR_SPC *((volatile uint8_t *)(0x42712084UL)) +#define bFM4_MFS9_I2C_IBSR_SPC *((volatile uint8_t *)(0x42712084UL)) +#define bFM_MFS9_I2C_IBSR_RSC *((volatile uint8_t *)(0x42712088UL)) +#define bFM4_MFS9_I2C_IBSR_RSC *((volatile uint8_t *)(0x42712088UL)) +#define bFM_MFS9_I2C_IBSR_AL *((volatile uint8_t *)(0x4271208CUL)) +#define bFM4_MFS9_I2C_IBSR_AL *((volatile uint8_t *)(0x4271208CUL)) +#define bFM_MFS9_I2C_IBSR_TRX *((volatile uint8_t *)(0x42712090UL)) +#define bFM4_MFS9_I2C_IBSR_TRX *((volatile uint8_t *)(0x42712090UL)) +#define bFM_MFS9_I2C_IBSR_RSA *((volatile uint8_t *)(0x42712094UL)) +#define bFM4_MFS9_I2C_IBSR_RSA *((volatile uint8_t *)(0x42712094UL)) +#define bFM_MFS9_I2C_IBSR_RACK *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_I2C_IBSR_RACK *((volatile uint8_t *)(0x42712098UL)) +#define bFM_MFS9_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271209CUL)) +#define bFM4_MFS9_I2C_IBSR_FBT *((volatile uint8_t *)(0x4271209CUL)) + +#define bFM_MFS9_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271221CUL)) +#define bFM4_MFS9_I2C_ISBA_SAEN *((volatile uint8_t *)(0x4271221CUL)) + +#define bFM_MFS9_I2C_ISMK_EN *((volatile uint8_t *)(0x4271223CUL)) +#define bFM4_MFS9_I2C_ISMK_EN *((volatile uint8_t *)(0x4271223CUL)) + +#define bFM_MFS9_I2C_SMR_TIE *((volatile uint8_t *)(0x42712008UL)) +#define bFM4_MFS9_I2C_SMR_TIE *((volatile uint8_t *)(0x42712008UL)) +#define bFM_MFS9_I2C_SMR_RIE *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_I2C_SMR_RIE *((volatile uint8_t *)(0x4271200CUL)) + +#define bFM_MFS9_I2C_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_I2C_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_I2C_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_I2C_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_I2C_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_I2C_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_I2C_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_I2C_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_I2C_SSR_TBIE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_I2C_SSR_TBIE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_I2C_SSR_DMA *((volatile uint8_t *)(0x427120B4UL)) +#define bFM4_MFS9_I2C_SSR_DMA *((volatile uint8_t *)(0x427120B4UL)) +#define bFM_MFS9_I2C_SSR_TSET *((volatile uint8_t *)(0x427120B8UL)) +#define bFM4_MFS9_I2C_SSR_TSET *((volatile uint8_t *)(0x427120B8UL)) +#define bFM_MFS9_I2C_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_I2C_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + +#define bFM_MFS9_LIN_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) +#define bFM4_MFS9_LIN_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) + +#define bFM_MFS9_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42712090UL)) +#define bFM4_MFS9_LIN_ESCR_LBIE *((volatile uint8_t *)(0x42712090UL)) +#define bFM_MFS9_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_LIN_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) + +#define bFM_MFS9_LIN_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_LIN_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_LIN_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_LIN_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_LIN_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_LIN_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_LIN_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_LIN_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_LIN_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_LIN_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_LIN_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_LIN_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_LIN_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_LIN_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_LIN_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_LIN_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_LIN_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_LIN_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_LIN_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_LIN_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_LIN_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_LIN_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_LIN_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_LIN_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_LIN_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_LIN_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_LIN_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_LIN_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_LIN_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_LIN_SCR_LBR *((volatile uint8_t *)(0x42712034UL)) +#define bFM4_MFS9_LIN_SCR_LBR *((volatile uint8_t *)(0x42712034UL)) +#define bFM_MFS9_LIN_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM4_MFS9_LIN_SCR_MS *((volatile uint8_t *)(0x42712038UL)) +#define bFM_MFS9_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_LIN_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_LIN_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM4_MFS9_LIN_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM_MFS9_LIN_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_LIN_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) +#define bFM_MFS9_LIN_SMR_WUCR *((volatile uint8_t *)(0x42712010UL)) +#define bFM4_MFS9_LIN_SMR_WUCR *((volatile uint8_t *)(0x42712010UL)) + +#define bFM_MFS9_LIN_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_LIN_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_LIN_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_LIN_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_LIN_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_LIN_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_LIN_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_LIN_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_LIN_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_LIN_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_LIN_SSR_LBD *((volatile uint8_t *)(0x427120B4UL)) +#define bFM4_MFS9_LIN_SSR_LBD *((volatile uint8_t *)(0x427120B4UL)) +#define bFM_MFS9_LIN_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_LIN_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + +#define bFM_MFS9_UART_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) +#define bFM4_MFS9_UART_BGR_EXT *((volatile uint8_t *)(0x427121BCUL)) + +#define bFM_MFS9_UART_ESCR_P *((volatile uint8_t *)(0x4271208CUL)) +#define bFM4_MFS9_UART_ESCR_P *((volatile uint8_t *)(0x4271208CUL)) +#define bFM_MFS9_UART_ESCR_PEN *((volatile uint8_t *)(0x42712090UL)) +#define bFM4_MFS9_UART_ESCR_PEN *((volatile uint8_t *)(0x42712090UL)) +#define bFM_MFS9_UART_ESCR_INV *((volatile uint8_t *)(0x42712094UL)) +#define bFM4_MFS9_UART_ESCR_INV *((volatile uint8_t *)(0x42712094UL)) +#define bFM_MFS9_UART_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) +#define bFM4_MFS9_UART_ESCR_ESBL *((volatile uint8_t *)(0x42712098UL)) +#define bFM_MFS9_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271209CUL)) +#define bFM4_MFS9_UART_ESCR_FLWEN *((volatile uint8_t *)(0x4271209CUL)) + +#define bFM_MFS9_UART_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM4_MFS9_UART_FCR_FE1 *((volatile uint8_t *)(0x42712280UL)) +#define bFM_MFS9_UART_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM4_MFS9_UART_FCR_FE2 *((volatile uint8_t *)(0x42712284UL)) +#define bFM_MFS9_UART_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM4_MFS9_UART_FCR_FCL1 *((volatile uint8_t *)(0x42712288UL)) +#define bFM_MFS9_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM4_MFS9_UART_FCR_FCL2 *((volatile uint8_t *)(0x4271228CUL)) +#define bFM_MFS9_UART_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM4_MFS9_UART_FCR_FSET *((volatile uint8_t *)(0x42712290UL)) +#define bFM_MFS9_UART_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM4_MFS9_UART_FCR_FLD *((volatile uint8_t *)(0x42712294UL)) +#define bFM_MFS9_UART_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM4_MFS9_UART_FCR_FLST *((volatile uint8_t *)(0x42712298UL)) +#define bFM_MFS9_UART_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM4_MFS9_UART_FCR_FSEL *((volatile uint8_t *)(0x427122A0UL)) +#define bFM_MFS9_UART_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM4_MFS9_UART_FCR_FTIE *((volatile uint8_t *)(0x427122A4UL)) +#define bFM_MFS9_UART_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM4_MFS9_UART_FCR_FDRQ *((volatile uint8_t *)(0x427122A8UL)) +#define bFM_MFS9_UART_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM4_MFS9_UART_FCR_FRIIE *((volatile uint8_t *)(0x427122ACUL)) +#define bFM_MFS9_UART_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) +#define bFM4_MFS9_UART_FCR_FLSTE *((volatile uint8_t *)(0x427122B0UL)) + +#define bFM_MFS9_UART_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM4_MFS9_UART_SCR_TXE *((volatile uint8_t *)(0x42712020UL)) +#define bFM_MFS9_UART_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM4_MFS9_UART_SCR_RXE *((volatile uint8_t *)(0x42712024UL)) +#define bFM_MFS9_UART_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM4_MFS9_UART_SCR_TBIE *((volatile uint8_t *)(0x42712028UL)) +#define bFM_MFS9_UART_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM4_MFS9_UART_SCR_TIE *((volatile uint8_t *)(0x4271202CUL)) +#define bFM_MFS9_UART_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM4_MFS9_UART_SCR_RIE *((volatile uint8_t *)(0x42712030UL)) +#define bFM_MFS9_UART_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) +#define bFM4_MFS9_UART_SCR_UPCL *((volatile uint8_t *)(0x4271203CUL)) + +#define bFM_MFS9_UART_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM4_MFS9_UART_SMR_SOE *((volatile uint8_t *)(0x42712000UL)) +#define bFM_MFS9_UART_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM4_MFS9_UART_SMR_BDS *((volatile uint8_t *)(0x42712008UL)) +#define bFM_MFS9_UART_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) +#define bFM4_MFS9_UART_SMR_SBL *((volatile uint8_t *)(0x4271200CUL)) + +#define bFM_MFS9_UART_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM4_MFS9_UART_SSR_TBI *((volatile uint8_t *)(0x427120A0UL)) +#define bFM_MFS9_UART_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM4_MFS9_UART_SSR_TDRE *((volatile uint8_t *)(0x427120A4UL)) +#define bFM_MFS9_UART_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM4_MFS9_UART_SSR_RDRF *((volatile uint8_t *)(0x427120A8UL)) +#define bFM_MFS9_UART_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM4_MFS9_UART_SSR_ORE *((volatile uint8_t *)(0x427120ACUL)) +#define bFM_MFS9_UART_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM4_MFS9_UART_SSR_FRE *((volatile uint8_t *)(0x427120B0UL)) +#define bFM_MFS9_UART_SSR_PE *((volatile uint8_t *)(0x427120B4UL)) +#define bFM4_MFS9_UART_SSR_PE *((volatile uint8_t *)(0x427120B4UL)) +#define bFM_MFS9_UART_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) +#define bFM4_MFS9_UART_SSR_REC *((volatile uint8_t *)(0x427120BCUL)) + + +/******************************************************************************* +* MFT_PPG Registers MFT_PPG +* Bitband Section +*******************************************************************************/ +#define bFM_MFT_PPG_GATEC0_EDGE0 *((volatile uint8_t *)(0x42484300UL)) +#define bFM4_MFT_PPG_GATEC0_EDGE0 *((volatile uint8_t *)(0x42484300UL)) +#define bFM_MFT_PPG_GATEC0_STRG0 *((volatile uint8_t *)(0x42484304UL)) +#define bFM4_MFT_PPG_GATEC0_STRG0 *((volatile uint8_t *)(0x42484304UL)) +#define bFM_MFT_PPG_GATEC0_EDGE2 *((volatile uint8_t *)(0x42484310UL)) +#define bFM4_MFT_PPG_GATEC0_EDGE2 *((volatile uint8_t *)(0x42484310UL)) +#define bFM_MFT_PPG_GATEC0_STRG2 *((volatile uint8_t *)(0x42484314UL)) +#define bFM4_MFT_PPG_GATEC0_STRG2 *((volatile uint8_t *)(0x42484314UL)) + +#define bFM_MFT_PPG_GATEC12_EDGE12 *((volatile uint8_t *)(0x42485B00UL)) +#define bFM4_MFT_PPG_GATEC12_EDGE12 *((volatile uint8_t *)(0x42485B00UL)) +#define bFM_MFT_PPG_GATEC12_STRG12 *((volatile uint8_t *)(0x42485B04UL)) +#define bFM4_MFT_PPG_GATEC12_STRG12 *((volatile uint8_t *)(0x42485B04UL)) +#define bFM_MFT_PPG_GATEC12_EDGE14 *((volatile uint8_t *)(0x42485B10UL)) +#define bFM4_MFT_PPG_GATEC12_EDGE14 *((volatile uint8_t *)(0x42485B10UL)) +#define bFM_MFT_PPG_GATEC12_STRG14 *((volatile uint8_t *)(0x42485B14UL)) +#define bFM4_MFT_PPG_GATEC12_STRG14 *((volatile uint8_t *)(0x42485B14UL)) + +#define bFM_MFT_PPG_GATEC16_EDGE16 *((volatile uint8_t *)(0x42486300UL)) +#define bFM4_MFT_PPG_GATEC16_EDGE16 *((volatile uint8_t *)(0x42486300UL)) +#define bFM_MFT_PPG_GATEC16_STRG16 *((volatile uint8_t *)(0x42486304UL)) +#define bFM4_MFT_PPG_GATEC16_STRG16 *((volatile uint8_t *)(0x42486304UL)) +#define bFM_MFT_PPG_GATEC16_EDGE18 *((volatile uint8_t *)(0x42486310UL)) +#define bFM4_MFT_PPG_GATEC16_EDGE18 *((volatile uint8_t *)(0x42486310UL)) +#define bFM_MFT_PPG_GATEC16_STRG18 *((volatile uint8_t *)(0x42486314UL)) +#define bFM4_MFT_PPG_GATEC16_STRG18 *((volatile uint8_t *)(0x42486314UL)) + +#define bFM_MFT_PPG_GATEC20_EDGE20 *((volatile uint8_t *)(0x42486B00UL)) +#define bFM4_MFT_PPG_GATEC20_EDGE20 *((volatile uint8_t *)(0x42486B00UL)) +#define bFM_MFT_PPG_GATEC20_STRG20 *((volatile uint8_t *)(0x42486B04UL)) +#define bFM4_MFT_PPG_GATEC20_STRG20 *((volatile uint8_t *)(0x42486B04UL)) +#define bFM_MFT_PPG_GATEC20_EDGE22 *((volatile uint8_t *)(0x42486B10UL)) +#define bFM4_MFT_PPG_GATEC20_EDGE22 *((volatile uint8_t *)(0x42486B10UL)) +#define bFM_MFT_PPG_GATEC20_STRG22 *((volatile uint8_t *)(0x42486B14UL)) +#define bFM4_MFT_PPG_GATEC20_STRG22 *((volatile uint8_t *)(0x42486B14UL)) + +#define bFM_MFT_PPG_GATEC4_EDGE4 *((volatile uint8_t *)(0x42484B00UL)) +#define bFM4_MFT_PPG_GATEC4_EDGE4 *((volatile uint8_t *)(0x42484B00UL)) +#define bFM_MFT_PPG_GATEC4_STRG4 *((volatile uint8_t *)(0x42484B04UL)) +#define bFM4_MFT_PPG_GATEC4_STRG4 *((volatile uint8_t *)(0x42484B04UL)) +#define bFM_MFT_PPG_GATEC4_EDGE6 *((volatile uint8_t *)(0x42484B10UL)) +#define bFM4_MFT_PPG_GATEC4_EDGE6 *((volatile uint8_t *)(0x42484B10UL)) +#define bFM_MFT_PPG_GATEC4_STRG6 *((volatile uint8_t *)(0x42484B14UL)) +#define bFM4_MFT_PPG_GATEC4_STRG6 *((volatile uint8_t *)(0x42484B14UL)) + +#define bFM_MFT_PPG_GATEC8_EDGE8 *((volatile uint8_t *)(0x42485300UL)) +#define bFM4_MFT_PPG_GATEC8_EDGE8 *((volatile uint8_t *)(0x42485300UL)) +#define bFM_MFT_PPG_GATEC8_STRG8 *((volatile uint8_t *)(0x42485304UL)) +#define bFM4_MFT_PPG_GATEC8_STRG8 *((volatile uint8_t *)(0x42485304UL)) +#define bFM_MFT_PPG_GATEC8_EDGE10 *((volatile uint8_t *)(0x42485310UL)) +#define bFM4_MFT_PPG_GATEC8_EDGE10 *((volatile uint8_t *)(0x42485310UL)) +#define bFM_MFT_PPG_GATEC8_STRG10 *((volatile uint8_t *)(0x42485314UL)) +#define bFM4_MFT_PPG_GATEC8_STRG10 *((volatile uint8_t *)(0x42485314UL)) + +#define bFM_MFT_PPG_PPGC0_TTRG *((volatile uint8_t *)(0x42484020UL)) +#define bFM4_MFT_PPG_PPGC0_TTRG *((volatile uint8_t *)(0x42484020UL)) +#define bFM_MFT_PPG_PPGC0_INTM *((volatile uint8_t *)(0x42484034UL)) +#define bFM4_MFT_PPG_PPGC0_INTM *((volatile uint8_t *)(0x42484034UL)) +#define bFM_MFT_PPG_PPGC0_PUF *((volatile uint8_t *)(0x42484038UL)) +#define bFM4_MFT_PPG_PPGC0_PUF *((volatile uint8_t *)(0x42484038UL)) +#define bFM_MFT_PPG_PPGC0_PIE *((volatile uint8_t *)(0x4248403CUL)) +#define bFM4_MFT_PPG_PPGC0_PIE *((volatile uint8_t *)(0x4248403CUL)) + +#define bFM_MFT_PPG_PPGC1_INTM *((volatile uint8_t *)(0x42484014UL)) +#define bFM4_MFT_PPG_PPGC1_INTM *((volatile uint8_t *)(0x42484014UL)) +#define bFM_MFT_PPG_PPGC1_PUF *((volatile uint8_t *)(0x42484018UL)) +#define bFM4_MFT_PPG_PPGC1_PUF *((volatile uint8_t *)(0x42484018UL)) +#define bFM_MFT_PPG_PPGC1_PIE *((volatile uint8_t *)(0x4248401CUL)) +#define bFM4_MFT_PPG_PPGC1_PIE *((volatile uint8_t *)(0x4248401CUL)) + +#define bFM_MFT_PPG_PPGC10_TTRG *((volatile uint8_t *)(0x424850A0UL)) +#define bFM4_MFT_PPG_PPGC10_TTRG *((volatile uint8_t *)(0x424850A0UL)) +#define bFM_MFT_PPG_PPGC10_INTM *((volatile uint8_t *)(0x424850B4UL)) +#define bFM4_MFT_PPG_PPGC10_INTM *((volatile uint8_t *)(0x424850B4UL)) +#define bFM_MFT_PPG_PPGC10_PUF *((volatile uint8_t *)(0x424850B8UL)) +#define bFM4_MFT_PPG_PPGC10_PUF *((volatile uint8_t *)(0x424850B8UL)) +#define bFM_MFT_PPG_PPGC10_PIE *((volatile uint8_t *)(0x424850BCUL)) +#define bFM4_MFT_PPG_PPGC10_PIE *((volatile uint8_t *)(0x424850BCUL)) + +#define bFM_MFT_PPG_PPGC11_INTM *((volatile uint8_t *)(0x42485094UL)) +#define bFM4_MFT_PPG_PPGC11_INTM *((volatile uint8_t *)(0x42485094UL)) +#define bFM_MFT_PPG_PPGC11_PUF *((volatile uint8_t *)(0x42485098UL)) +#define bFM4_MFT_PPG_PPGC11_PUF *((volatile uint8_t *)(0x42485098UL)) +#define bFM_MFT_PPG_PPGC11_PIE *((volatile uint8_t *)(0x4248509CUL)) +#define bFM4_MFT_PPG_PPGC11_PIE *((volatile uint8_t *)(0x4248509CUL)) + +#define bFM_MFT_PPG_PPGC12_TTRG *((volatile uint8_t *)(0x42485820UL)) +#define bFM4_MFT_PPG_PPGC12_TTRG *((volatile uint8_t *)(0x42485820UL)) +#define bFM_MFT_PPG_PPGC12_INTM *((volatile uint8_t *)(0x42485834UL)) +#define bFM4_MFT_PPG_PPGC12_INTM *((volatile uint8_t *)(0x42485834UL)) +#define bFM_MFT_PPG_PPGC12_PUF *((volatile uint8_t *)(0x42485838UL)) +#define bFM4_MFT_PPG_PPGC12_PUF *((volatile uint8_t *)(0x42485838UL)) +#define bFM_MFT_PPG_PPGC12_PIE *((volatile uint8_t *)(0x4248583CUL)) +#define bFM4_MFT_PPG_PPGC12_PIE *((volatile uint8_t *)(0x4248583CUL)) + +#define bFM_MFT_PPG_PPGC13_INTM *((volatile uint8_t *)(0x42485814UL)) +#define bFM4_MFT_PPG_PPGC13_INTM *((volatile uint8_t *)(0x42485814UL)) +#define bFM_MFT_PPG_PPGC13_PUF *((volatile uint8_t *)(0x42485818UL)) +#define bFM4_MFT_PPG_PPGC13_PUF *((volatile uint8_t *)(0x42485818UL)) +#define bFM_MFT_PPG_PPGC13_PIE *((volatile uint8_t *)(0x4248581CUL)) +#define bFM4_MFT_PPG_PPGC13_PIE *((volatile uint8_t *)(0x4248581CUL)) + +#define bFM_MFT_PPG_PPGC14_TTRG *((volatile uint8_t *)(0x424858A0UL)) +#define bFM4_MFT_PPG_PPGC14_TTRG *((volatile uint8_t *)(0x424858A0UL)) +#define bFM_MFT_PPG_PPGC14_INTM *((volatile uint8_t *)(0x424858B4UL)) +#define bFM4_MFT_PPG_PPGC14_INTM *((volatile uint8_t *)(0x424858B4UL)) +#define bFM_MFT_PPG_PPGC14_PUF *((volatile uint8_t *)(0x424858B8UL)) +#define bFM4_MFT_PPG_PPGC14_PUF *((volatile uint8_t *)(0x424858B8UL)) +#define bFM_MFT_PPG_PPGC14_PIE *((volatile uint8_t *)(0x424858BCUL)) +#define bFM4_MFT_PPG_PPGC14_PIE *((volatile uint8_t *)(0x424858BCUL)) + +#define bFM_MFT_PPG_PPGC15_INTM *((volatile uint8_t *)(0x42485894UL)) +#define bFM4_MFT_PPG_PPGC15_INTM *((volatile uint8_t *)(0x42485894UL)) +#define bFM_MFT_PPG_PPGC15_PUF *((volatile uint8_t *)(0x42485898UL)) +#define bFM4_MFT_PPG_PPGC15_PUF *((volatile uint8_t *)(0x42485898UL)) +#define bFM_MFT_PPG_PPGC15_PIE *((volatile uint8_t *)(0x4248589CUL)) +#define bFM4_MFT_PPG_PPGC15_PIE *((volatile uint8_t *)(0x4248589CUL)) + +#define bFM_MFT_PPG_PPGC16_TTRG *((volatile uint8_t *)(0x42486020UL)) +#define bFM4_MFT_PPG_PPGC16_TTRG *((volatile uint8_t *)(0x42486020UL)) +#define bFM_MFT_PPG_PPGC16_INTM *((volatile uint8_t *)(0x42486034UL)) +#define bFM4_MFT_PPG_PPGC16_INTM *((volatile uint8_t *)(0x42486034UL)) +#define bFM_MFT_PPG_PPGC16_PUF *((volatile uint8_t *)(0x42486038UL)) +#define bFM4_MFT_PPG_PPGC16_PUF *((volatile uint8_t *)(0x42486038UL)) +#define bFM_MFT_PPG_PPGC16_PIE *((volatile uint8_t *)(0x4248603CUL)) +#define bFM4_MFT_PPG_PPGC16_PIE *((volatile uint8_t *)(0x4248603CUL)) + +#define bFM_MFT_PPG_PPGC17_INTM *((volatile uint8_t *)(0x42486014UL)) +#define bFM4_MFT_PPG_PPGC17_INTM *((volatile uint8_t *)(0x42486014UL)) +#define bFM_MFT_PPG_PPGC17_PUF *((volatile uint8_t *)(0x42486018UL)) +#define bFM4_MFT_PPG_PPGC17_PUF *((volatile uint8_t *)(0x42486018UL)) +#define bFM_MFT_PPG_PPGC17_PIE *((volatile uint8_t *)(0x4248601CUL)) +#define bFM4_MFT_PPG_PPGC17_PIE *((volatile uint8_t *)(0x4248601CUL)) + +#define bFM_MFT_PPG_PPGC18_TTRG *((volatile uint8_t *)(0x424860A0UL)) +#define bFM4_MFT_PPG_PPGC18_TTRG *((volatile uint8_t *)(0x424860A0UL)) +#define bFM_MFT_PPG_PPGC18_INTM *((volatile uint8_t *)(0x424860B4UL)) +#define bFM4_MFT_PPG_PPGC18_INTM *((volatile uint8_t *)(0x424860B4UL)) +#define bFM_MFT_PPG_PPGC18_PUF *((volatile uint8_t *)(0x424860B8UL)) +#define bFM4_MFT_PPG_PPGC18_PUF *((volatile uint8_t *)(0x424860B8UL)) +#define bFM_MFT_PPG_PPGC18_PIE *((volatile uint8_t *)(0x424860BCUL)) +#define bFM4_MFT_PPG_PPGC18_PIE *((volatile uint8_t *)(0x424860BCUL)) + +#define bFM_MFT_PPG_PPGC19_INTM *((volatile uint8_t *)(0x42486094UL)) +#define bFM4_MFT_PPG_PPGC19_INTM *((volatile uint8_t *)(0x42486094UL)) +#define bFM_MFT_PPG_PPGC19_PUF *((volatile uint8_t *)(0x42486098UL)) +#define bFM4_MFT_PPG_PPGC19_PUF *((volatile uint8_t *)(0x42486098UL)) +#define bFM_MFT_PPG_PPGC19_PIE *((volatile uint8_t *)(0x4248609CUL)) +#define bFM4_MFT_PPG_PPGC19_PIE *((volatile uint8_t *)(0x4248609CUL)) + +#define bFM_MFT_PPG_PPGC2_TTRG *((volatile uint8_t *)(0x424840A0UL)) +#define bFM4_MFT_PPG_PPGC2_TTRG *((volatile uint8_t *)(0x424840A0UL)) +#define bFM_MFT_PPG_PPGC2_INTM *((volatile uint8_t *)(0x424840B4UL)) +#define bFM4_MFT_PPG_PPGC2_INTM *((volatile uint8_t *)(0x424840B4UL)) +#define bFM_MFT_PPG_PPGC2_PUF *((volatile uint8_t *)(0x424840B8UL)) +#define bFM4_MFT_PPG_PPGC2_PUF *((volatile uint8_t *)(0x424840B8UL)) +#define bFM_MFT_PPG_PPGC2_PIE *((volatile uint8_t *)(0x424840BCUL)) +#define bFM4_MFT_PPG_PPGC2_PIE *((volatile uint8_t *)(0x424840BCUL)) + +#define bFM_MFT_PPG_PPGC20_TTRG *((volatile uint8_t *)(0x42486820UL)) +#define bFM4_MFT_PPG_PPGC20_TTRG *((volatile uint8_t *)(0x42486820UL)) +#define bFM_MFT_PPG_PPGC20_INTM *((volatile uint8_t *)(0x42486834UL)) +#define bFM4_MFT_PPG_PPGC20_INTM *((volatile uint8_t *)(0x42486834UL)) +#define bFM_MFT_PPG_PPGC20_PUF *((volatile uint8_t *)(0x42486838UL)) +#define bFM4_MFT_PPG_PPGC20_PUF *((volatile uint8_t *)(0x42486838UL)) +#define bFM_MFT_PPG_PPGC20_PIE *((volatile uint8_t *)(0x4248683CUL)) +#define bFM4_MFT_PPG_PPGC20_PIE *((volatile uint8_t *)(0x4248683CUL)) + +#define bFM_MFT_PPG_PPGC21_INTM *((volatile uint8_t *)(0x42486814UL)) +#define bFM4_MFT_PPG_PPGC21_INTM *((volatile uint8_t *)(0x42486814UL)) +#define bFM_MFT_PPG_PPGC21_PUF *((volatile uint8_t *)(0x42486818UL)) +#define bFM4_MFT_PPG_PPGC21_PUF *((volatile uint8_t *)(0x42486818UL)) +#define bFM_MFT_PPG_PPGC21_PIE *((volatile uint8_t *)(0x4248681CUL)) +#define bFM4_MFT_PPG_PPGC21_PIE *((volatile uint8_t *)(0x4248681CUL)) + +#define bFM_MFT_PPG_PPGC22_TTRG *((volatile uint8_t *)(0x424868A0UL)) +#define bFM4_MFT_PPG_PPGC22_TTRG *((volatile uint8_t *)(0x424868A0UL)) +#define bFM_MFT_PPG_PPGC22_INTM *((volatile uint8_t *)(0x424868B4UL)) +#define bFM4_MFT_PPG_PPGC22_INTM *((volatile uint8_t *)(0x424868B4UL)) +#define bFM_MFT_PPG_PPGC22_PUF *((volatile uint8_t *)(0x424868B8UL)) +#define bFM4_MFT_PPG_PPGC22_PUF *((volatile uint8_t *)(0x424868B8UL)) +#define bFM_MFT_PPG_PPGC22_PIE *((volatile uint8_t *)(0x424868BCUL)) +#define bFM4_MFT_PPG_PPGC22_PIE *((volatile uint8_t *)(0x424868BCUL)) + +#define bFM_MFT_PPG_PPGC23_INTM *((volatile uint8_t *)(0x42486894UL)) +#define bFM4_MFT_PPG_PPGC23_INTM *((volatile uint8_t *)(0x42486894UL)) +#define bFM_MFT_PPG_PPGC23_PUF *((volatile uint8_t *)(0x42486898UL)) +#define bFM4_MFT_PPG_PPGC23_PUF *((volatile uint8_t *)(0x42486898UL)) +#define bFM_MFT_PPG_PPGC23_PIE *((volatile uint8_t *)(0x4248689CUL)) +#define bFM4_MFT_PPG_PPGC23_PIE *((volatile uint8_t *)(0x4248689CUL)) + +#define bFM_MFT_PPG_PPGC3_INTM *((volatile uint8_t *)(0x42484094UL)) +#define bFM4_MFT_PPG_PPGC3_INTM *((volatile uint8_t *)(0x42484094UL)) +#define bFM_MFT_PPG_PPGC3_PUF *((volatile uint8_t *)(0x42484098UL)) +#define bFM4_MFT_PPG_PPGC3_PUF *((volatile uint8_t *)(0x42484098UL)) +#define bFM_MFT_PPG_PPGC3_PIE *((volatile uint8_t *)(0x4248409CUL)) +#define bFM4_MFT_PPG_PPGC3_PIE *((volatile uint8_t *)(0x4248409CUL)) + +#define bFM_MFT_PPG_PPGC4_TTRG *((volatile uint8_t *)(0x42484820UL)) +#define bFM4_MFT_PPG_PPGC4_TTRG *((volatile uint8_t *)(0x42484820UL)) +#define bFM_MFT_PPG_PPGC4_INTM *((volatile uint8_t *)(0x42484834UL)) +#define bFM4_MFT_PPG_PPGC4_INTM *((volatile uint8_t *)(0x42484834UL)) +#define bFM_MFT_PPG_PPGC4_PUF *((volatile uint8_t *)(0x42484838UL)) +#define bFM4_MFT_PPG_PPGC4_PUF *((volatile uint8_t *)(0x42484838UL)) +#define bFM_MFT_PPG_PPGC4_PIE *((volatile uint8_t *)(0x4248483CUL)) +#define bFM4_MFT_PPG_PPGC4_PIE *((volatile uint8_t *)(0x4248483CUL)) + +#define bFM_MFT_PPG_PPGC5_INTM *((volatile uint8_t *)(0x42484814UL)) +#define bFM4_MFT_PPG_PPGC5_INTM *((volatile uint8_t *)(0x42484814UL)) +#define bFM_MFT_PPG_PPGC5_PUF *((volatile uint8_t *)(0x42484818UL)) +#define bFM4_MFT_PPG_PPGC5_PUF *((volatile uint8_t *)(0x42484818UL)) +#define bFM_MFT_PPG_PPGC5_PIE *((volatile uint8_t *)(0x4248481CUL)) +#define bFM4_MFT_PPG_PPGC5_PIE *((volatile uint8_t *)(0x4248481CUL)) + +#define bFM_MFT_PPG_PPGC6_TTRG *((volatile uint8_t *)(0x424848A0UL)) +#define bFM4_MFT_PPG_PPGC6_TTRG *((volatile uint8_t *)(0x424848A0UL)) +#define bFM_MFT_PPG_PPGC6_INTM *((volatile uint8_t *)(0x424848B4UL)) +#define bFM4_MFT_PPG_PPGC6_INTM *((volatile uint8_t *)(0x424848B4UL)) +#define bFM_MFT_PPG_PPGC6_PUF *((volatile uint8_t *)(0x424848B8UL)) +#define bFM4_MFT_PPG_PPGC6_PUF *((volatile uint8_t *)(0x424848B8UL)) +#define bFM_MFT_PPG_PPGC6_PIE *((volatile uint8_t *)(0x424848BCUL)) +#define bFM4_MFT_PPG_PPGC6_PIE *((volatile uint8_t *)(0x424848BCUL)) + +#define bFM_MFT_PPG_PPGC7_INTM *((volatile uint8_t *)(0x42484894UL)) +#define bFM4_MFT_PPG_PPGC7_INTM *((volatile uint8_t *)(0x42484894UL)) +#define bFM_MFT_PPG_PPGC7_PUF *((volatile uint8_t *)(0x42484898UL)) +#define bFM4_MFT_PPG_PPGC7_PUF *((volatile uint8_t *)(0x42484898UL)) +#define bFM_MFT_PPG_PPGC7_PIE *((volatile uint8_t *)(0x4248489CUL)) +#define bFM4_MFT_PPG_PPGC7_PIE *((volatile uint8_t *)(0x4248489CUL)) + +#define bFM_MFT_PPG_PPGC8_TTRG *((volatile uint8_t *)(0x42485020UL)) +#define bFM4_MFT_PPG_PPGC8_TTRG *((volatile uint8_t *)(0x42485020UL)) +#define bFM_MFT_PPG_PPGC8_INTM *((volatile uint8_t *)(0x42485034UL)) +#define bFM4_MFT_PPG_PPGC8_INTM *((volatile uint8_t *)(0x42485034UL)) +#define bFM_MFT_PPG_PPGC8_PUF *((volatile uint8_t *)(0x42485038UL)) +#define bFM4_MFT_PPG_PPGC8_PUF *((volatile uint8_t *)(0x42485038UL)) +#define bFM_MFT_PPG_PPGC8_PIE *((volatile uint8_t *)(0x4248503CUL)) +#define bFM4_MFT_PPG_PPGC8_PIE *((volatile uint8_t *)(0x4248503CUL)) + +#define bFM_MFT_PPG_PPGC9_INTM *((volatile uint8_t *)(0x42485014UL)) +#define bFM4_MFT_PPG_PPGC9_INTM *((volatile uint8_t *)(0x42485014UL)) +#define bFM_MFT_PPG_PPGC9_PUF *((volatile uint8_t *)(0x42485018UL)) +#define bFM4_MFT_PPG_PPGC9_PUF *((volatile uint8_t *)(0x42485018UL)) +#define bFM_MFT_PPG_PPGC9_PIE *((volatile uint8_t *)(0x4248501CUL)) +#define bFM4_MFT_PPG_PPGC9_PIE *((volatile uint8_t *)(0x4248501CUL)) + +#define bFM_MFT_PPG_REVC0_REV00 *((volatile uint8_t *)(0x42482080UL)) +#define bFM4_MFT_PPG_REVC0_REV00 *((volatile uint8_t *)(0x42482080UL)) +#define bFM_MFT_PPG_REVC0_REV01 *((volatile uint8_t *)(0x42482084UL)) +#define bFM4_MFT_PPG_REVC0_REV01 *((volatile uint8_t *)(0x42482084UL)) +#define bFM_MFT_PPG_REVC0_REV02 *((volatile uint8_t *)(0x42482088UL)) +#define bFM4_MFT_PPG_REVC0_REV02 *((volatile uint8_t *)(0x42482088UL)) +#define bFM_MFT_PPG_REVC0_REV03 *((volatile uint8_t *)(0x4248208CUL)) +#define bFM4_MFT_PPG_REVC0_REV03 *((volatile uint8_t *)(0x4248208CUL)) +#define bFM_MFT_PPG_REVC0_REV04 *((volatile uint8_t *)(0x42482090UL)) +#define bFM4_MFT_PPG_REVC0_REV04 *((volatile uint8_t *)(0x42482090UL)) +#define bFM_MFT_PPG_REVC0_REV05 *((volatile uint8_t *)(0x42482094UL)) +#define bFM4_MFT_PPG_REVC0_REV05 *((volatile uint8_t *)(0x42482094UL)) +#define bFM_MFT_PPG_REVC0_REV06 *((volatile uint8_t *)(0x42482098UL)) +#define bFM4_MFT_PPG_REVC0_REV06 *((volatile uint8_t *)(0x42482098UL)) +#define bFM_MFT_PPG_REVC0_REV07 *((volatile uint8_t *)(0x4248209CUL)) +#define bFM4_MFT_PPG_REVC0_REV07 *((volatile uint8_t *)(0x4248209CUL)) +#define bFM_MFT_PPG_REVC0_REV08 *((volatile uint8_t *)(0x424820A0UL)) +#define bFM4_MFT_PPG_REVC0_REV08 *((volatile uint8_t *)(0x424820A0UL)) +#define bFM_MFT_PPG_REVC0_REV09 *((volatile uint8_t *)(0x424820A4UL)) +#define bFM4_MFT_PPG_REVC0_REV09 *((volatile uint8_t *)(0x424820A4UL)) +#define bFM_MFT_PPG_REVC0_REV10 *((volatile uint8_t *)(0x424820A8UL)) +#define bFM4_MFT_PPG_REVC0_REV10 *((volatile uint8_t *)(0x424820A8UL)) +#define bFM_MFT_PPG_REVC0_REV11 *((volatile uint8_t *)(0x424820ACUL)) +#define bFM4_MFT_PPG_REVC0_REV11 *((volatile uint8_t *)(0x424820ACUL)) +#define bFM_MFT_PPG_REVC0_REV12 *((volatile uint8_t *)(0x424820B0UL)) +#define bFM4_MFT_PPG_REVC0_REV12 *((volatile uint8_t *)(0x424820B0UL)) +#define bFM_MFT_PPG_REVC0_REV13 *((volatile uint8_t *)(0x424820B4UL)) +#define bFM4_MFT_PPG_REVC0_REV13 *((volatile uint8_t *)(0x424820B4UL)) +#define bFM_MFT_PPG_REVC0_REV14 *((volatile uint8_t *)(0x424820B8UL)) +#define bFM4_MFT_PPG_REVC0_REV14 *((volatile uint8_t *)(0x424820B8UL)) +#define bFM_MFT_PPG_REVC0_REV15 *((volatile uint8_t *)(0x424820BCUL)) +#define bFM4_MFT_PPG_REVC0_REV15 *((volatile uint8_t *)(0x424820BCUL)) + +#define bFM_MFT_PPG_REVC1_REV16 *((volatile uint8_t *)(0x42482880UL)) +#define bFM4_MFT_PPG_REVC1_REV16 *((volatile uint8_t *)(0x42482880UL)) +#define bFM_MFT_PPG_REVC1_REV17 *((volatile uint8_t *)(0x42482884UL)) +#define bFM4_MFT_PPG_REVC1_REV17 *((volatile uint8_t *)(0x42482884UL)) +#define bFM_MFT_PPG_REVC1_REV18 *((volatile uint8_t *)(0x42482888UL)) +#define bFM4_MFT_PPG_REVC1_REV18 *((volatile uint8_t *)(0x42482888UL)) +#define bFM_MFT_PPG_REVC1_REV19 *((volatile uint8_t *)(0x4248288CUL)) +#define bFM4_MFT_PPG_REVC1_REV19 *((volatile uint8_t *)(0x4248288CUL)) +#define bFM_MFT_PPG_REVC1_REV20 *((volatile uint8_t *)(0x42482890UL)) +#define bFM4_MFT_PPG_REVC1_REV20 *((volatile uint8_t *)(0x42482890UL)) +#define bFM_MFT_PPG_REVC1_REV21 *((volatile uint8_t *)(0x42482894UL)) +#define bFM4_MFT_PPG_REVC1_REV21 *((volatile uint8_t *)(0x42482894UL)) +#define bFM_MFT_PPG_REVC1_REV22 *((volatile uint8_t *)(0x42482898UL)) +#define bFM4_MFT_PPG_REVC1_REV22 *((volatile uint8_t *)(0x42482898UL)) +#define bFM_MFT_PPG_REVC1_REV23 *((volatile uint8_t *)(0x4248289CUL)) +#define bFM4_MFT_PPG_REVC1_REV23 *((volatile uint8_t *)(0x4248289CUL)) + +#define bFM_MFT_PPG_TRG0_PEN00 *((volatile uint8_t *)(0x42482000UL)) +#define bFM4_MFT_PPG_TRG0_PEN00 *((volatile uint8_t *)(0x42482000UL)) +#define bFM_MFT_PPG_TRG0_PEN01 *((volatile uint8_t *)(0x42482004UL)) +#define bFM4_MFT_PPG_TRG0_PEN01 *((volatile uint8_t *)(0x42482004UL)) +#define bFM_MFT_PPG_TRG0_PEN02 *((volatile uint8_t *)(0x42482008UL)) +#define bFM4_MFT_PPG_TRG0_PEN02 *((volatile uint8_t *)(0x42482008UL)) +#define bFM_MFT_PPG_TRG0_PEN03 *((volatile uint8_t *)(0x4248200CUL)) +#define bFM4_MFT_PPG_TRG0_PEN03 *((volatile uint8_t *)(0x4248200CUL)) +#define bFM_MFT_PPG_TRG0_PEN04 *((volatile uint8_t *)(0x42482010UL)) +#define bFM4_MFT_PPG_TRG0_PEN04 *((volatile uint8_t *)(0x42482010UL)) +#define bFM_MFT_PPG_TRG0_PEN05 *((volatile uint8_t *)(0x42482014UL)) +#define bFM4_MFT_PPG_TRG0_PEN05 *((volatile uint8_t *)(0x42482014UL)) +#define bFM_MFT_PPG_TRG0_PEN06 *((volatile uint8_t *)(0x42482018UL)) +#define bFM4_MFT_PPG_TRG0_PEN06 *((volatile uint8_t *)(0x42482018UL)) +#define bFM_MFT_PPG_TRG0_PEN07 *((volatile uint8_t *)(0x4248201CUL)) +#define bFM4_MFT_PPG_TRG0_PEN07 *((volatile uint8_t *)(0x4248201CUL)) +#define bFM_MFT_PPG_TRG0_PEN08 *((volatile uint8_t *)(0x42482020UL)) +#define bFM4_MFT_PPG_TRG0_PEN08 *((volatile uint8_t *)(0x42482020UL)) +#define bFM_MFT_PPG_TRG0_PEN09 *((volatile uint8_t *)(0x42482024UL)) +#define bFM4_MFT_PPG_TRG0_PEN09 *((volatile uint8_t *)(0x42482024UL)) +#define bFM_MFT_PPG_TRG0_PEN10 *((volatile uint8_t *)(0x42482028UL)) +#define bFM4_MFT_PPG_TRG0_PEN10 *((volatile uint8_t *)(0x42482028UL)) +#define bFM_MFT_PPG_TRG0_PEN11 *((volatile uint8_t *)(0x4248202CUL)) +#define bFM4_MFT_PPG_TRG0_PEN11 *((volatile uint8_t *)(0x4248202CUL)) +#define bFM_MFT_PPG_TRG0_PEN12 *((volatile uint8_t *)(0x42482030UL)) +#define bFM4_MFT_PPG_TRG0_PEN12 *((volatile uint8_t *)(0x42482030UL)) +#define bFM_MFT_PPG_TRG0_PEN13 *((volatile uint8_t *)(0x42482034UL)) +#define bFM4_MFT_PPG_TRG0_PEN13 *((volatile uint8_t *)(0x42482034UL)) +#define bFM_MFT_PPG_TRG0_PEN14 *((volatile uint8_t *)(0x42482038UL)) +#define bFM4_MFT_PPG_TRG0_PEN14 *((volatile uint8_t *)(0x42482038UL)) +#define bFM_MFT_PPG_TRG0_PEN15 *((volatile uint8_t *)(0x4248203CUL)) +#define bFM4_MFT_PPG_TRG0_PEN15 *((volatile uint8_t *)(0x4248203CUL)) + +#define bFM_MFT_PPG_TRG1_PEN16 *((volatile uint8_t *)(0x42482800UL)) +#define bFM4_MFT_PPG_TRG1_PEN16 *((volatile uint8_t *)(0x42482800UL)) +#define bFM_MFT_PPG_TRG1_PEN17 *((volatile uint8_t *)(0x42482804UL)) +#define bFM4_MFT_PPG_TRG1_PEN17 *((volatile uint8_t *)(0x42482804UL)) +#define bFM_MFT_PPG_TRG1_PEN18 *((volatile uint8_t *)(0x42482808UL)) +#define bFM4_MFT_PPG_TRG1_PEN18 *((volatile uint8_t *)(0x42482808UL)) +#define bFM_MFT_PPG_TRG1_PEN19 *((volatile uint8_t *)(0x4248280CUL)) +#define bFM4_MFT_PPG_TRG1_PEN19 *((volatile uint8_t *)(0x4248280CUL)) +#define bFM_MFT_PPG_TRG1_PEN20 *((volatile uint8_t *)(0x42482810UL)) +#define bFM4_MFT_PPG_TRG1_PEN20 *((volatile uint8_t *)(0x42482810UL)) +#define bFM_MFT_PPG_TRG1_PEN21 *((volatile uint8_t *)(0x42482814UL)) +#define bFM4_MFT_PPG_TRG1_PEN21 *((volatile uint8_t *)(0x42482814UL)) +#define bFM_MFT_PPG_TRG1_PEN22 *((volatile uint8_t *)(0x42482818UL)) +#define bFM4_MFT_PPG_TRG1_PEN22 *((volatile uint8_t *)(0x42482818UL)) +#define bFM_MFT_PPG_TRG1_PEN23 *((volatile uint8_t *)(0x4248281CUL)) +#define bFM4_MFT_PPG_TRG1_PEN23 *((volatile uint8_t *)(0x4248281CUL)) + +#define bFM_MFT_PPG_TTCR0_STR0 *((volatile uint8_t *)(0x42480020UL)) +#define bFM4_MFT_PPG_TTCR0_STR0 *((volatile uint8_t *)(0x42480020UL)) +#define bFM_MFT_PPG_TTCR0_MONI0 *((volatile uint8_t *)(0x42480024UL)) +#define bFM4_MFT_PPG_TTCR0_MONI0 *((volatile uint8_t *)(0x42480024UL)) +#define bFM_MFT_PPG_TTCR0_TRG0O *((volatile uint8_t *)(0x42480030UL)) +#define bFM4_MFT_PPG_TTCR0_TRG0O *((volatile uint8_t *)(0x42480030UL)) +#define bFM_MFT_PPG_TTCR0_TRG2O *((volatile uint8_t *)(0x42480034UL)) +#define bFM4_MFT_PPG_TTCR0_TRG2O *((volatile uint8_t *)(0x42480034UL)) +#define bFM_MFT_PPG_TTCR0_TRG4O *((volatile uint8_t *)(0x42480038UL)) +#define bFM4_MFT_PPG_TTCR0_TRG4O *((volatile uint8_t *)(0x42480038UL)) +#define bFM_MFT_PPG_TTCR0_TRG6O *((volatile uint8_t *)(0x4248003CUL)) +#define bFM4_MFT_PPG_TTCR0_TRG6O *((volatile uint8_t *)(0x4248003CUL)) + +#define bFM_MFT_PPG_TTCR1_STR1 *((volatile uint8_t *)(0x42480420UL)) +#define bFM4_MFT_PPG_TTCR1_STR1 *((volatile uint8_t *)(0x42480420UL)) +#define bFM_MFT_PPG_TTCR1_MONI1 *((volatile uint8_t *)(0x42480424UL)) +#define bFM4_MFT_PPG_TTCR1_MONI1 *((volatile uint8_t *)(0x42480424UL)) +#define bFM_MFT_PPG_TTCR1_TRG1O *((volatile uint8_t *)(0x42480430UL)) +#define bFM4_MFT_PPG_TTCR1_TRG1O *((volatile uint8_t *)(0x42480430UL)) +#define bFM_MFT_PPG_TTCR1_TRG3O *((volatile uint8_t *)(0x42480434UL)) +#define bFM4_MFT_PPG_TTCR1_TRG3O *((volatile uint8_t *)(0x42480434UL)) +#define bFM_MFT_PPG_TTCR1_TRG5O *((volatile uint8_t *)(0x42480438UL)) +#define bFM4_MFT_PPG_TTCR1_TRG5O *((volatile uint8_t *)(0x42480438UL)) +#define bFM_MFT_PPG_TTCR1_TRG7O *((volatile uint8_t *)(0x4248043CUL)) +#define bFM4_MFT_PPG_TTCR1_TRG7O *((volatile uint8_t *)(0x4248043CUL)) + +#define bFM_MFT_PPG_TTCR2_STR2 *((volatile uint8_t *)(0x42480820UL)) +#define bFM4_MFT_PPG_TTCR2_STR2 *((volatile uint8_t *)(0x42480820UL)) +#define bFM_MFT_PPG_TTCR2_MONI2 *((volatile uint8_t *)(0x42480824UL)) +#define bFM4_MFT_PPG_TTCR2_MONI2 *((volatile uint8_t *)(0x42480824UL)) +#define bFM_MFT_PPG_TTCR2_TRG16O *((volatile uint8_t *)(0x42480830UL)) +#define bFM4_MFT_PPG_TTCR2_TRG16O *((volatile uint8_t *)(0x42480830UL)) +#define bFM_MFT_PPG_TTCR2_TRG18O *((volatile uint8_t *)(0x42480834UL)) +#define bFM4_MFT_PPG_TTCR2_TRG18O *((volatile uint8_t *)(0x42480834UL)) +#define bFM_MFT_PPG_TTCR2_TRG20O *((volatile uint8_t *)(0x42480838UL)) +#define bFM4_MFT_PPG_TTCR2_TRG20O *((volatile uint8_t *)(0x42480838UL)) +#define bFM_MFT_PPG_TTCR2_TRG22O *((volatile uint8_t *)(0x4248083CUL)) +#define bFM4_MFT_PPG_TTCR2_TRG22O *((volatile uint8_t *)(0x4248083CUL)) + + +/******************************************************************************* +* MFT Registers MFT0 +* Bitband Section +*******************************************************************************/ +#define bFM_MFT0_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42403AD8UL)) +#define bFM4_MFT0_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42403AD8UL)) +#define bFM_MFT0_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42403ADCUL)) +#define bFM4_MFT0_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42403ADCUL)) + +#define bFM_MFT0_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42403B58UL)) +#define bFM4_MFT0_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42403B58UL)) +#define bFM_MFT0_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42403B5CUL)) +#define bFM4_MFT0_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42403B5CUL)) + +#define bFM_MFT0_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42403BD8UL)) +#define bFM4_MFT0_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42403BD8UL)) +#define bFM_MFT0_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42403BDCUL)) +#define bFM4_MFT0_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42403BDCUL)) + +#define bFM_MFT0_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42403C58UL)) +#define bFM4_MFT0_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42403C58UL)) +#define bFM_MFT0_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42403C5CUL)) +#define bFM4_MFT0_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42403C5CUL)) + +#define bFM_MFT0_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42403CD8UL)) +#define bFM4_MFT0_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42403CD8UL)) +#define bFM_MFT0_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42403CDCUL)) +#define bFM4_MFT0_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42403CDCUL)) + +#define bFM_MFT0_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42403D58UL)) +#define bFM4_MFT0_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42403D58UL)) +#define bFM_MFT0_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42403D5CUL)) +#define bFM4_MFT0_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42403D5CUL)) + +#define bFM_MFT0_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42403A94UL)) +#define bFM4_MFT0_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42403A94UL)) + +#define bFM_MFT0_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42403B14UL)) +#define bFM4_MFT0_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42403B14UL)) + +#define bFM_MFT0_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42403B94UL)) +#define bFM4_MFT0_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42403B94UL)) + +#define bFM_MFT0_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42403C14UL)) +#define bFM4_MFT0_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42403C14UL)) + +#define bFM_MFT0_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42403C94UL)) +#define bFM4_MFT0_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42403C94UL)) + +#define bFM_MFT0_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42403D14UL)) +#define bFM4_MFT0_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42403D14UL)) + +#define bFM_MFT0_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42403AA0UL)) +#define bFM4_MFT0_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42403AA0UL)) +#define bFM_MFT0_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42403AA4UL)) +#define bFM4_MFT0_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42403AA4UL)) +#define bFM_MFT0_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42403AB0UL)) +#define bFM4_MFT0_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42403AB0UL)) +#define bFM_MFT0_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42403AB4UL)) +#define bFM4_MFT0_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42403AB4UL)) +#define bFM_MFT0_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42403AB8UL)) +#define bFM4_MFT0_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42403AB8UL)) +#define bFM_MFT0_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42403ABCUL)) +#define bFM4_MFT0_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42403ABCUL)) + +#define bFM_MFT0_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42403B20UL)) +#define bFM4_MFT0_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42403B20UL)) +#define bFM_MFT0_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42403B24UL)) +#define bFM4_MFT0_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42403B24UL)) +#define bFM_MFT0_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42403B30UL)) +#define bFM4_MFT0_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42403B30UL)) +#define bFM_MFT0_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42403B34UL)) +#define bFM4_MFT0_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42403B34UL)) +#define bFM_MFT0_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42403B38UL)) +#define bFM4_MFT0_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42403B38UL)) +#define bFM_MFT0_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42403B3CUL)) +#define bFM4_MFT0_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42403B3CUL)) + +#define bFM_MFT0_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42403BA0UL)) +#define bFM4_MFT0_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42403BA0UL)) +#define bFM_MFT0_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42403BA4UL)) +#define bFM4_MFT0_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42403BA4UL)) +#define bFM_MFT0_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42403BB0UL)) +#define bFM4_MFT0_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42403BB0UL)) +#define bFM_MFT0_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42403BB4UL)) +#define bFM4_MFT0_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42403BB4UL)) +#define bFM_MFT0_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42403BB8UL)) +#define bFM4_MFT0_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42403BB8UL)) +#define bFM_MFT0_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42403BBCUL)) +#define bFM4_MFT0_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42403BBCUL)) + +#define bFM_MFT0_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42403C20UL)) +#define bFM4_MFT0_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42403C20UL)) +#define bFM_MFT0_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42403C24UL)) +#define bFM4_MFT0_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42403C24UL)) +#define bFM_MFT0_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42403C30UL)) +#define bFM4_MFT0_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42403C30UL)) +#define bFM_MFT0_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42403C34UL)) +#define bFM4_MFT0_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42403C34UL)) +#define bFM_MFT0_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42403C38UL)) +#define bFM4_MFT0_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42403C38UL)) +#define bFM_MFT0_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42403C3CUL)) +#define bFM4_MFT0_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42403C3CUL)) + +#define bFM_MFT0_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42403CA0UL)) +#define bFM4_MFT0_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42403CA0UL)) +#define bFM_MFT0_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42403CA4UL)) +#define bFM4_MFT0_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42403CA4UL)) +#define bFM_MFT0_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42403CB0UL)) +#define bFM4_MFT0_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42403CB0UL)) +#define bFM_MFT0_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42403CB4UL)) +#define bFM4_MFT0_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42403CB4UL)) +#define bFM_MFT0_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42403CB8UL)) +#define bFM4_MFT0_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42403CB8UL)) +#define bFM_MFT0_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42403CBCUL)) +#define bFM4_MFT0_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42403CBCUL)) + +#define bFM_MFT0_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42403D20UL)) +#define bFM4_MFT0_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42403D20UL)) +#define bFM_MFT0_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42403D24UL)) +#define bFM4_MFT0_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42403D24UL)) +#define bFM_MFT0_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42403D30UL)) +#define bFM4_MFT0_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42403D30UL)) +#define bFM_MFT0_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42403D34UL)) +#define bFM4_MFT0_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42403D34UL)) +#define bFM_MFT0_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42403D38UL)) +#define bFM4_MFT0_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42403D38UL)) +#define bFM_MFT0_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42403D3CUL)) +#define bFM4_MFT0_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42403D3CUL)) + +#define bFM_MFT0_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42402C80UL)) +#define bFM4_MFT0_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42402C80UL)) +#define bFM_MFT0_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42402C84UL)) +#define bFM4_MFT0_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42402C84UL)) +#define bFM_MFT0_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42402C88UL)) +#define bFM4_MFT0_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42402C88UL)) +#define bFM_MFT0_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42402C8CUL)) +#define bFM4_MFT0_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42402C8CUL)) +#define bFM_MFT0_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42402C90UL)) +#define bFM4_MFT0_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42402C90UL)) +#define bFM_MFT0_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42402C94UL)) +#define bFM4_MFT0_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42402C94UL)) +#define bFM_MFT0_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42402C98UL)) +#define bFM4_MFT0_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42402C98UL)) +#define bFM_MFT0_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42402C9CUL)) +#define bFM4_MFT0_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42402C9CUL)) +#define bFM_MFT0_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42402CA0UL)) +#define bFM4_MFT0_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42402CA0UL)) +#define bFM_MFT0_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42402CC0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42402CC0UL)) +#define bFM_MFT0_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42402CC4UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42402CC4UL)) +#define bFM_MFT0_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42402CC8UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42402CC8UL)) +#define bFM_MFT0_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42402CCCUL)) +#define bFM4_MFT0_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42402CCCUL)) +#define bFM_MFT0_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42402CD0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42402CD0UL)) +#define bFM_MFT0_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42402CD4UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42402CD4UL)) +#define bFM_MFT0_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42402CD8UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42402CD8UL)) +#define bFM_MFT0_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42402CDCUL)) +#define bFM4_MFT0_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42402CDCUL)) +#define bFM_MFT0_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42402CE0UL)) +#define bFM4_MFT0_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42402CE0UL)) + +#define bFM_MFT0_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42402910UL)) +#define bFM4_MFT0_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42402910UL)) +#define bFM_MFT0_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42402914UL)) +#define bFM4_MFT0_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42402914UL)) +#define bFM_MFT0_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42402918UL)) +#define bFM4_MFT0_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42402918UL)) +#define bFM_MFT0_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4240291CUL)) +#define bFM4_MFT0_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4240291CUL)) +#define bFM_MFT0_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42402920UL)) +#define bFM4_MFT0_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42402920UL)) +#define bFM_MFT0_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42402924UL)) +#define bFM4_MFT0_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42402924UL)) +#define bFM_MFT0_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42402934UL)) +#define bFM4_MFT0_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42402934UL)) +#define bFM_MFT0_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42402938UL)) +#define bFM4_MFT0_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42402938UL)) +#define bFM_MFT0_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4240293CUL)) +#define bFM4_MFT0_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4240293CUL)) + +#define bFM_MFT0_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42402A90UL)) +#define bFM4_MFT0_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42402A90UL)) +#define bFM_MFT0_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42402A94UL)) +#define bFM4_MFT0_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42402A94UL)) +#define bFM_MFT0_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42402A98UL)) +#define bFM4_MFT0_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42402A98UL)) +#define bFM_MFT0_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42402A9CUL)) +#define bFM4_MFT0_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42402A9CUL)) +#define bFM_MFT0_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42402AA0UL)) +#define bFM4_MFT0_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42402AA0UL)) +#define bFM_MFT0_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42402AA4UL)) +#define bFM4_MFT0_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42402AA4UL)) +#define bFM_MFT0_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42402AB4UL)) +#define bFM4_MFT0_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42402AB4UL)) +#define bFM_MFT0_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42402AB8UL)) +#define bFM4_MFT0_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42402AB8UL)) +#define bFM_MFT0_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42402ABCUL)) +#define bFM4_MFT0_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42402ABCUL)) + +#define bFM_MFT0_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42402C10UL)) +#define bFM4_MFT0_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42402C10UL)) +#define bFM_MFT0_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42402C14UL)) +#define bFM4_MFT0_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42402C14UL)) +#define bFM_MFT0_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42402C18UL)) +#define bFM4_MFT0_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42402C18UL)) +#define bFM_MFT0_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42402C1CUL)) +#define bFM4_MFT0_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42402C1CUL)) +#define bFM_MFT0_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42402C20UL)) +#define bFM4_MFT0_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42402C20UL)) +#define bFM_MFT0_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42402C24UL)) +#define bFM4_MFT0_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42402C24UL)) +#define bFM_MFT0_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42402C34UL)) +#define bFM4_MFT0_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42402C34UL)) +#define bFM_MFT0_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42402C38UL)) +#define bFM4_MFT0_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42402C38UL)) +#define bFM_MFT0_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42402C3CUL)) +#define bFM4_MFT0_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42402C3CUL)) + +#define bFM_MFT0_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42403D80UL)) +#define bFM4_MFT0_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42403D80UL)) +#define bFM_MFT0_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42403D84UL)) +#define bFM4_MFT0_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42403D84UL)) + +#define bFM_MFT0_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42403090UL)) +#define bFM4_MFT0_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42403090UL)) +#define bFM_MFT0_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42403094UL)) +#define bFM4_MFT0_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42403094UL)) +#define bFM_MFT0_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42403098UL)) +#define bFM4_MFT0_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42403098UL)) +#define bFM_MFT0_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4240309CUL)) +#define bFM4_MFT0_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4240309CUL)) + +#define bFM_MFT0_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42403110UL)) +#define bFM4_MFT0_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42403110UL)) +#define bFM_MFT0_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42403114UL)) +#define bFM4_MFT0_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42403114UL)) +#define bFM_MFT0_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42403118UL)) +#define bFM4_MFT0_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42403118UL)) +#define bFM_MFT0_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4240311CUL)) +#define bFM4_MFT0_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4240311CUL)) + +#define bFM_MFT0_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424030A0UL)) +#define bFM4_MFT0_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424030A0UL)) +#define bFM_MFT0_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424030A4UL)) +#define bFM4_MFT0_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424030A4UL)) + +#define bFM_MFT0_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42403120UL)) +#define bFM4_MFT0_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42403120UL)) +#define bFM_MFT0_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42403124UL)) +#define bFM4_MFT0_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42403124UL)) + +#define bFM_MFT0_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42402300UL)) +#define bFM4_MFT0_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42402300UL)) +#define bFM_MFT0_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42402304UL)) +#define bFM4_MFT0_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42402304UL)) +#define bFM_MFT0_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42402310UL)) +#define bFM4_MFT0_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42402310UL)) +#define bFM_MFT0_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42402314UL)) +#define bFM4_MFT0_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42402314UL)) +#define bFM_MFT0_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42402318UL)) +#define bFM4_MFT0_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42402318UL)) +#define bFM_MFT0_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4240231CUL)) +#define bFM4_MFT0_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4240231CUL)) + +#define bFM_MFT0_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42402380UL)) +#define bFM4_MFT0_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42402380UL)) +#define bFM_MFT0_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42402384UL)) +#define bFM4_MFT0_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42402384UL)) +#define bFM_MFT0_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42402390UL)) +#define bFM4_MFT0_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42402390UL)) +#define bFM_MFT0_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42402394UL)) +#define bFM4_MFT0_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42402394UL)) +#define bFM_MFT0_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42402398UL)) +#define bFM4_MFT0_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42402398UL)) +#define bFM_MFT0_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4240239CUL)) +#define bFM4_MFT0_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4240239CUL)) + +#define bFM_MFT0_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42402400UL)) +#define bFM4_MFT0_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42402400UL)) +#define bFM_MFT0_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42402404UL)) +#define bFM4_MFT0_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42402404UL)) +#define bFM_MFT0_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42402410UL)) +#define bFM4_MFT0_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42402410UL)) +#define bFM_MFT0_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42402414UL)) +#define bFM4_MFT0_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42402414UL)) +#define bFM_MFT0_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42402418UL)) +#define bFM4_MFT0_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42402418UL)) +#define bFM_MFT0_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4240241CUL)) +#define bFM4_MFT0_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4240241CUL)) + +#define bFM_MFT0_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42402320UL)) +#define bFM4_MFT0_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42402320UL)) +#define bFM_MFT0_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42402324UL)) +#define bFM4_MFT0_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42402324UL)) +#define bFM_MFT0_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42402330UL)) +#define bFM4_MFT0_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42402330UL)) +#define bFM_MFT0_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4240233CUL)) +#define bFM4_MFT0_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4240233CUL)) + +#define bFM_MFT0_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424023A0UL)) +#define bFM4_MFT0_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424023A0UL)) +#define bFM_MFT0_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424023A4UL)) +#define bFM4_MFT0_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424023A4UL)) +#define bFM_MFT0_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424023B0UL)) +#define bFM4_MFT0_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424023B0UL)) +#define bFM_MFT0_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424023BCUL)) +#define bFM4_MFT0_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424023BCUL)) + +#define bFM_MFT0_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42402420UL)) +#define bFM4_MFT0_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42402420UL)) +#define bFM_MFT0_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42402424UL)) +#define bFM4_MFT0_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42402424UL)) +#define bFM_MFT0_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42402430UL)) +#define bFM4_MFT0_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42402430UL)) +#define bFM_MFT0_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4240243CUL)) +#define bFM4_MFT0_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4240243CUL)) + +#define bFM_MFT0_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424024A0UL)) +#define bFM4_MFT0_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424024A0UL)) +#define bFM_MFT0_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424024A4UL)) +#define bFM4_MFT0_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424024A4UL)) +#define bFM_MFT0_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424024A8UL)) +#define bFM4_MFT0_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424024A8UL)) +#define bFM_MFT0_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424024ACUL)) +#define bFM4_MFT0_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424024ACUL)) +#define bFM_MFT0_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424024B0UL)) +#define bFM4_MFT0_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424024B0UL)) +#define bFM_MFT0_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424024B4UL)) +#define bFM4_MFT0_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424024B4UL)) + +#define bFM_MFT0_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42402360UL)) +#define bFM4_MFT0_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42402360UL)) +#define bFM_MFT0_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42402364UL)) +#define bFM4_MFT0_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42402364UL)) +#define bFM_MFT0_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42402368UL)) +#define bFM4_MFT0_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42402368UL)) +#define bFM_MFT0_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4240236CUL)) +#define bFM4_MFT0_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4240236CUL)) +#define bFM_MFT0_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42402370UL)) +#define bFM4_MFT0_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42402370UL)) +#define bFM_MFT0_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42402374UL)) +#define bFM4_MFT0_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42402374UL)) + +#define bFM_MFT0_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424023E0UL)) +#define bFM4_MFT0_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424023E0UL)) +#define bFM_MFT0_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424023E4UL)) +#define bFM4_MFT0_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424023E4UL)) +#define bFM_MFT0_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424023E8UL)) +#define bFM4_MFT0_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424023E8UL)) +#define bFM_MFT0_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424023ECUL)) +#define bFM4_MFT0_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424023ECUL)) +#define bFM_MFT0_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424023F0UL)) +#define bFM4_MFT0_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424023F0UL)) +#define bFM_MFT0_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424023F4UL)) +#define bFM4_MFT0_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424023F4UL)) + +#define bFM_MFT0_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42402460UL)) +#define bFM4_MFT0_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42402460UL)) +#define bFM_MFT0_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42402464UL)) +#define bFM4_MFT0_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42402464UL)) +#define bFM_MFT0_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42402468UL)) +#define bFM4_MFT0_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42402468UL)) +#define bFM_MFT0_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4240246CUL)) +#define bFM4_MFT0_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4240246CUL)) +#define bFM_MFT0_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42402470UL)) +#define bFM4_MFT0_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42402470UL)) +#define bFM_MFT0_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42402474UL)) +#define bFM4_MFT0_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42402474UL)) + +#define bFM_MFT0_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42403680UL)) +#define bFM4_MFT0_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42403680UL)) +#define bFM_MFT0_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42403690UL)) +#define bFM4_MFT0_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42403690UL)) +#define bFM_MFT0_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42403694UL)) +#define bFM4_MFT0_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42403694UL)) +#define bFM_MFT0_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4240369CUL)) +#define bFM4_MFT0_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4240369CUL)) +#define bFM_MFT0_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424036A0UL)) +#define bFM4_MFT0_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424036A0UL)) +#define bFM_MFT0_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424036A4UL)) +#define bFM4_MFT0_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424036A4UL)) +#define bFM_MFT0_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424036B0UL)) +#define bFM4_MFT0_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424036B0UL)) +#define bFM_MFT0_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424036B4UL)) +#define bFM4_MFT0_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424036B4UL)) +#define bFM_MFT0_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424036B8UL)) +#define bFM4_MFT0_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424036B8UL)) + +#define bFM_MFT0_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42403600UL)) +#define bFM4_MFT0_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42403600UL)) +#define bFM_MFT0_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42403604UL)) +#define bFM4_MFT0_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42403604UL)) +#define bFM_MFT0_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42403608UL)) +#define bFM4_MFT0_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42403608UL)) +#define bFM_MFT0_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4240360CUL)) +#define bFM4_MFT0_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4240360CUL)) +#define bFM_MFT0_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42403610UL)) +#define bFM4_MFT0_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42403610UL)) +#define bFM_MFT0_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42403614UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42403614UL)) +#define bFM_MFT0_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42403618UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42403618UL)) +#define bFM_MFT0_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4240361CUL)) +#define bFM4_MFT0_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4240361CUL)) +#define bFM_MFT0_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42403620UL)) +#define bFM4_MFT0_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42403620UL)) +#define bFM_MFT0_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42403624UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42403624UL)) +#define bFM_MFT0_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42403628UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42403628UL)) +#define bFM_MFT0_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4240362CUL)) +#define bFM4_MFT0_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4240362CUL)) +#define bFM_MFT0_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42403630UL)) +#define bFM4_MFT0_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42403630UL)) +#define bFM_MFT0_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42403634UL)) +#define bFM4_MFT0_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42403634UL)) +#define bFM_MFT0_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42403638UL)) +#define bFM4_MFT0_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42403638UL)) +#define bFM_MFT0_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4240363CUL)) +#define bFM4_MFT0_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4240363CUL)) + + +/******************************************************************************* +* MFT Registers MFT1 +* Bitband Section +*******************************************************************************/ +#define bFM_MFT1_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42423AD8UL)) +#define bFM4_MFT1_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42423AD8UL)) +#define bFM_MFT1_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42423ADCUL)) +#define bFM4_MFT1_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42423ADCUL)) + +#define bFM_MFT1_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42423B58UL)) +#define bFM4_MFT1_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42423B58UL)) +#define bFM_MFT1_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42423B5CUL)) +#define bFM4_MFT1_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42423B5CUL)) + +#define bFM_MFT1_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42423BD8UL)) +#define bFM4_MFT1_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42423BD8UL)) +#define bFM_MFT1_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42423BDCUL)) +#define bFM4_MFT1_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42423BDCUL)) + +#define bFM_MFT1_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42423C58UL)) +#define bFM4_MFT1_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42423C58UL)) +#define bFM_MFT1_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42423C5CUL)) +#define bFM4_MFT1_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42423C5CUL)) + +#define bFM_MFT1_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42423CD8UL)) +#define bFM4_MFT1_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42423CD8UL)) +#define bFM_MFT1_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42423CDCUL)) +#define bFM4_MFT1_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42423CDCUL)) + +#define bFM_MFT1_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42423D58UL)) +#define bFM4_MFT1_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42423D58UL)) +#define bFM_MFT1_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42423D5CUL)) +#define bFM4_MFT1_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42423D5CUL)) + +#define bFM_MFT1_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42423A94UL)) +#define bFM4_MFT1_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42423A94UL)) + +#define bFM_MFT1_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42423B14UL)) +#define bFM4_MFT1_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42423B14UL)) + +#define bFM_MFT1_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42423B94UL)) +#define bFM4_MFT1_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42423B94UL)) + +#define bFM_MFT1_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42423C14UL)) +#define bFM4_MFT1_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42423C14UL)) + +#define bFM_MFT1_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42423C94UL)) +#define bFM4_MFT1_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42423C94UL)) + +#define bFM_MFT1_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42423D14UL)) +#define bFM4_MFT1_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42423D14UL)) + +#define bFM_MFT1_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42423AA0UL)) +#define bFM4_MFT1_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42423AA0UL)) +#define bFM_MFT1_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42423AA4UL)) +#define bFM4_MFT1_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42423AA4UL)) +#define bFM_MFT1_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42423AB0UL)) +#define bFM4_MFT1_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42423AB0UL)) +#define bFM_MFT1_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42423AB4UL)) +#define bFM4_MFT1_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42423AB4UL)) +#define bFM_MFT1_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42423AB8UL)) +#define bFM4_MFT1_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42423AB8UL)) +#define bFM_MFT1_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42423ABCUL)) +#define bFM4_MFT1_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42423ABCUL)) + +#define bFM_MFT1_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42423B20UL)) +#define bFM4_MFT1_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42423B20UL)) +#define bFM_MFT1_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42423B24UL)) +#define bFM4_MFT1_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42423B24UL)) +#define bFM_MFT1_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42423B30UL)) +#define bFM4_MFT1_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42423B30UL)) +#define bFM_MFT1_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42423B34UL)) +#define bFM4_MFT1_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42423B34UL)) +#define bFM_MFT1_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42423B38UL)) +#define bFM4_MFT1_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42423B38UL)) +#define bFM_MFT1_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42423B3CUL)) +#define bFM4_MFT1_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42423B3CUL)) + +#define bFM_MFT1_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42423BA0UL)) +#define bFM4_MFT1_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42423BA0UL)) +#define bFM_MFT1_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42423BA4UL)) +#define bFM4_MFT1_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42423BA4UL)) +#define bFM_MFT1_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42423BB0UL)) +#define bFM4_MFT1_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42423BB0UL)) +#define bFM_MFT1_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42423BB4UL)) +#define bFM4_MFT1_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42423BB4UL)) +#define bFM_MFT1_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42423BB8UL)) +#define bFM4_MFT1_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42423BB8UL)) +#define bFM_MFT1_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42423BBCUL)) +#define bFM4_MFT1_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42423BBCUL)) + +#define bFM_MFT1_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42423C20UL)) +#define bFM4_MFT1_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42423C20UL)) +#define bFM_MFT1_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42423C24UL)) +#define bFM4_MFT1_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42423C24UL)) +#define bFM_MFT1_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42423C30UL)) +#define bFM4_MFT1_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42423C30UL)) +#define bFM_MFT1_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42423C34UL)) +#define bFM4_MFT1_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42423C34UL)) +#define bFM_MFT1_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42423C38UL)) +#define bFM4_MFT1_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42423C38UL)) +#define bFM_MFT1_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42423C3CUL)) +#define bFM4_MFT1_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42423C3CUL)) + +#define bFM_MFT1_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42423CA0UL)) +#define bFM4_MFT1_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42423CA0UL)) +#define bFM_MFT1_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42423CA4UL)) +#define bFM4_MFT1_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42423CA4UL)) +#define bFM_MFT1_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42423CB0UL)) +#define bFM4_MFT1_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42423CB0UL)) +#define bFM_MFT1_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42423CB4UL)) +#define bFM4_MFT1_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42423CB4UL)) +#define bFM_MFT1_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42423CB8UL)) +#define bFM4_MFT1_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42423CB8UL)) +#define bFM_MFT1_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42423CBCUL)) +#define bFM4_MFT1_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42423CBCUL)) + +#define bFM_MFT1_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42423D20UL)) +#define bFM4_MFT1_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42423D20UL)) +#define bFM_MFT1_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42423D24UL)) +#define bFM4_MFT1_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42423D24UL)) +#define bFM_MFT1_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42423D30UL)) +#define bFM4_MFT1_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42423D30UL)) +#define bFM_MFT1_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42423D34UL)) +#define bFM4_MFT1_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42423D34UL)) +#define bFM_MFT1_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42423D38UL)) +#define bFM4_MFT1_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42423D38UL)) +#define bFM_MFT1_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42423D3CUL)) +#define bFM4_MFT1_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42423D3CUL)) + +#define bFM_MFT1_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42422C80UL)) +#define bFM4_MFT1_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42422C80UL)) +#define bFM_MFT1_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42422C84UL)) +#define bFM4_MFT1_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42422C84UL)) +#define bFM_MFT1_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42422C88UL)) +#define bFM4_MFT1_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42422C88UL)) +#define bFM_MFT1_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42422C8CUL)) +#define bFM4_MFT1_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42422C8CUL)) +#define bFM_MFT1_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42422C90UL)) +#define bFM4_MFT1_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42422C90UL)) +#define bFM_MFT1_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42422C94UL)) +#define bFM4_MFT1_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42422C94UL)) +#define bFM_MFT1_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42422C98UL)) +#define bFM4_MFT1_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42422C98UL)) +#define bFM_MFT1_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42422C9CUL)) +#define bFM4_MFT1_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42422C9CUL)) +#define bFM_MFT1_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42422CA0UL)) +#define bFM4_MFT1_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42422CA0UL)) +#define bFM_MFT1_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42422CC0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42422CC0UL)) +#define bFM_MFT1_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42422CC4UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42422CC4UL)) +#define bFM_MFT1_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42422CC8UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42422CC8UL)) +#define bFM_MFT1_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42422CCCUL)) +#define bFM4_MFT1_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42422CCCUL)) +#define bFM_MFT1_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42422CD0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42422CD0UL)) +#define bFM_MFT1_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42422CD4UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42422CD4UL)) +#define bFM_MFT1_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42422CD8UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42422CD8UL)) +#define bFM_MFT1_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42422CDCUL)) +#define bFM4_MFT1_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42422CDCUL)) +#define bFM_MFT1_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42422CE0UL)) +#define bFM4_MFT1_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42422CE0UL)) + +#define bFM_MFT1_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42422910UL)) +#define bFM4_MFT1_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42422910UL)) +#define bFM_MFT1_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42422914UL)) +#define bFM4_MFT1_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42422914UL)) +#define bFM_MFT1_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42422918UL)) +#define bFM4_MFT1_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42422918UL)) +#define bFM_MFT1_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4242291CUL)) +#define bFM4_MFT1_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4242291CUL)) +#define bFM_MFT1_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42422920UL)) +#define bFM4_MFT1_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42422920UL)) +#define bFM_MFT1_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42422924UL)) +#define bFM4_MFT1_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42422924UL)) +#define bFM_MFT1_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42422934UL)) +#define bFM4_MFT1_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42422934UL)) +#define bFM_MFT1_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42422938UL)) +#define bFM4_MFT1_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42422938UL)) +#define bFM_MFT1_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4242293CUL)) +#define bFM4_MFT1_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4242293CUL)) + +#define bFM_MFT1_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42422A90UL)) +#define bFM4_MFT1_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42422A90UL)) +#define bFM_MFT1_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42422A94UL)) +#define bFM4_MFT1_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42422A94UL)) +#define bFM_MFT1_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42422A98UL)) +#define bFM4_MFT1_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42422A98UL)) +#define bFM_MFT1_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42422A9CUL)) +#define bFM4_MFT1_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42422A9CUL)) +#define bFM_MFT1_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42422AA0UL)) +#define bFM4_MFT1_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42422AA0UL)) +#define bFM_MFT1_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42422AA4UL)) +#define bFM4_MFT1_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42422AA4UL)) +#define bFM_MFT1_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42422AB4UL)) +#define bFM4_MFT1_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42422AB4UL)) +#define bFM_MFT1_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42422AB8UL)) +#define bFM4_MFT1_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42422AB8UL)) +#define bFM_MFT1_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42422ABCUL)) +#define bFM4_MFT1_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42422ABCUL)) + +#define bFM_MFT1_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42422C10UL)) +#define bFM4_MFT1_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42422C10UL)) +#define bFM_MFT1_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42422C14UL)) +#define bFM4_MFT1_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42422C14UL)) +#define bFM_MFT1_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42422C18UL)) +#define bFM4_MFT1_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42422C18UL)) +#define bFM_MFT1_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42422C1CUL)) +#define bFM4_MFT1_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42422C1CUL)) +#define bFM_MFT1_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42422C20UL)) +#define bFM4_MFT1_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42422C20UL)) +#define bFM_MFT1_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42422C24UL)) +#define bFM4_MFT1_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42422C24UL)) +#define bFM_MFT1_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42422C34UL)) +#define bFM4_MFT1_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42422C34UL)) +#define bFM_MFT1_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42422C38UL)) +#define bFM4_MFT1_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42422C38UL)) +#define bFM_MFT1_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42422C3CUL)) +#define bFM4_MFT1_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42422C3CUL)) + +#define bFM_MFT1_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42423D80UL)) +#define bFM4_MFT1_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42423D80UL)) +#define bFM_MFT1_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42423D84UL)) +#define bFM4_MFT1_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42423D84UL)) + +#define bFM_MFT1_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42423090UL)) +#define bFM4_MFT1_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42423090UL)) +#define bFM_MFT1_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42423094UL)) +#define bFM4_MFT1_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42423094UL)) +#define bFM_MFT1_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42423098UL)) +#define bFM4_MFT1_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42423098UL)) +#define bFM_MFT1_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4242309CUL)) +#define bFM4_MFT1_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4242309CUL)) + +#define bFM_MFT1_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42423110UL)) +#define bFM4_MFT1_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42423110UL)) +#define bFM_MFT1_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42423114UL)) +#define bFM4_MFT1_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42423114UL)) +#define bFM_MFT1_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42423118UL)) +#define bFM4_MFT1_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42423118UL)) +#define bFM_MFT1_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4242311CUL)) +#define bFM4_MFT1_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4242311CUL)) + +#define bFM_MFT1_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424230A0UL)) +#define bFM4_MFT1_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424230A0UL)) +#define bFM_MFT1_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424230A4UL)) +#define bFM4_MFT1_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424230A4UL)) + +#define bFM_MFT1_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42423120UL)) +#define bFM4_MFT1_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42423120UL)) +#define bFM_MFT1_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42423124UL)) +#define bFM4_MFT1_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42423124UL)) + +#define bFM_MFT1_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42422300UL)) +#define bFM4_MFT1_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42422300UL)) +#define bFM_MFT1_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42422304UL)) +#define bFM4_MFT1_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42422304UL)) +#define bFM_MFT1_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42422310UL)) +#define bFM4_MFT1_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42422310UL)) +#define bFM_MFT1_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42422314UL)) +#define bFM4_MFT1_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42422314UL)) +#define bFM_MFT1_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42422318UL)) +#define bFM4_MFT1_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42422318UL)) +#define bFM_MFT1_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4242231CUL)) +#define bFM4_MFT1_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4242231CUL)) + +#define bFM_MFT1_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42422380UL)) +#define bFM4_MFT1_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42422380UL)) +#define bFM_MFT1_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42422384UL)) +#define bFM4_MFT1_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42422384UL)) +#define bFM_MFT1_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42422390UL)) +#define bFM4_MFT1_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42422390UL)) +#define bFM_MFT1_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42422394UL)) +#define bFM4_MFT1_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42422394UL)) +#define bFM_MFT1_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42422398UL)) +#define bFM4_MFT1_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42422398UL)) +#define bFM_MFT1_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4242239CUL)) +#define bFM4_MFT1_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4242239CUL)) + +#define bFM_MFT1_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42422400UL)) +#define bFM4_MFT1_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42422400UL)) +#define bFM_MFT1_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42422404UL)) +#define bFM4_MFT1_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42422404UL)) +#define bFM_MFT1_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42422410UL)) +#define bFM4_MFT1_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42422410UL)) +#define bFM_MFT1_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42422414UL)) +#define bFM4_MFT1_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42422414UL)) +#define bFM_MFT1_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42422418UL)) +#define bFM4_MFT1_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42422418UL)) +#define bFM_MFT1_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4242241CUL)) +#define bFM4_MFT1_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4242241CUL)) + +#define bFM_MFT1_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42422320UL)) +#define bFM4_MFT1_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42422320UL)) +#define bFM_MFT1_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42422324UL)) +#define bFM4_MFT1_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42422324UL)) +#define bFM_MFT1_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42422330UL)) +#define bFM4_MFT1_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42422330UL)) +#define bFM_MFT1_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4242233CUL)) +#define bFM4_MFT1_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4242233CUL)) + +#define bFM_MFT1_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424223A0UL)) +#define bFM4_MFT1_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424223A0UL)) +#define bFM_MFT1_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424223A4UL)) +#define bFM4_MFT1_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424223A4UL)) +#define bFM_MFT1_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424223B0UL)) +#define bFM4_MFT1_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424223B0UL)) +#define bFM_MFT1_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424223BCUL)) +#define bFM4_MFT1_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424223BCUL)) + +#define bFM_MFT1_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42422420UL)) +#define bFM4_MFT1_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42422420UL)) +#define bFM_MFT1_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42422424UL)) +#define bFM4_MFT1_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42422424UL)) +#define bFM_MFT1_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42422430UL)) +#define bFM4_MFT1_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42422430UL)) +#define bFM_MFT1_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4242243CUL)) +#define bFM4_MFT1_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4242243CUL)) + +#define bFM_MFT1_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424224A0UL)) +#define bFM4_MFT1_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424224A0UL)) +#define bFM_MFT1_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424224A4UL)) +#define bFM4_MFT1_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424224A4UL)) +#define bFM_MFT1_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424224A8UL)) +#define bFM4_MFT1_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424224A8UL)) +#define bFM_MFT1_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424224ACUL)) +#define bFM4_MFT1_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424224ACUL)) +#define bFM_MFT1_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424224B0UL)) +#define bFM4_MFT1_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424224B0UL)) +#define bFM_MFT1_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424224B4UL)) +#define bFM4_MFT1_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424224B4UL)) + +#define bFM_MFT1_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42422360UL)) +#define bFM4_MFT1_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42422360UL)) +#define bFM_MFT1_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42422364UL)) +#define bFM4_MFT1_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42422364UL)) +#define bFM_MFT1_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42422368UL)) +#define bFM4_MFT1_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42422368UL)) +#define bFM_MFT1_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4242236CUL)) +#define bFM4_MFT1_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4242236CUL)) +#define bFM_MFT1_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42422370UL)) +#define bFM4_MFT1_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42422370UL)) +#define bFM_MFT1_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42422374UL)) +#define bFM4_MFT1_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42422374UL)) + +#define bFM_MFT1_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424223E0UL)) +#define bFM4_MFT1_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424223E0UL)) +#define bFM_MFT1_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424223E4UL)) +#define bFM4_MFT1_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424223E4UL)) +#define bFM_MFT1_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424223E8UL)) +#define bFM4_MFT1_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424223E8UL)) +#define bFM_MFT1_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424223ECUL)) +#define bFM4_MFT1_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424223ECUL)) +#define bFM_MFT1_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424223F0UL)) +#define bFM4_MFT1_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424223F0UL)) +#define bFM_MFT1_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424223F4UL)) +#define bFM4_MFT1_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424223F4UL)) + +#define bFM_MFT1_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42422460UL)) +#define bFM4_MFT1_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42422460UL)) +#define bFM_MFT1_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42422464UL)) +#define bFM4_MFT1_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42422464UL)) +#define bFM_MFT1_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42422468UL)) +#define bFM4_MFT1_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42422468UL)) +#define bFM_MFT1_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4242246CUL)) +#define bFM4_MFT1_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4242246CUL)) +#define bFM_MFT1_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42422470UL)) +#define bFM4_MFT1_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42422470UL)) +#define bFM_MFT1_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42422474UL)) +#define bFM4_MFT1_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42422474UL)) + +#define bFM_MFT1_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42423680UL)) +#define bFM4_MFT1_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42423680UL)) +#define bFM_MFT1_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42423690UL)) +#define bFM4_MFT1_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42423690UL)) +#define bFM_MFT1_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42423694UL)) +#define bFM4_MFT1_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42423694UL)) +#define bFM_MFT1_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4242369CUL)) +#define bFM4_MFT1_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4242369CUL)) +#define bFM_MFT1_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424236A0UL)) +#define bFM4_MFT1_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424236A0UL)) +#define bFM_MFT1_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424236A4UL)) +#define bFM4_MFT1_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424236A4UL)) +#define bFM_MFT1_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424236B0UL)) +#define bFM4_MFT1_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424236B0UL)) +#define bFM_MFT1_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424236B4UL)) +#define bFM4_MFT1_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424236B4UL)) +#define bFM_MFT1_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424236B8UL)) +#define bFM4_MFT1_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424236B8UL)) + +#define bFM_MFT1_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42423600UL)) +#define bFM4_MFT1_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42423600UL)) +#define bFM_MFT1_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42423604UL)) +#define bFM4_MFT1_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42423604UL)) +#define bFM_MFT1_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42423608UL)) +#define bFM4_MFT1_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42423608UL)) +#define bFM_MFT1_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4242360CUL)) +#define bFM4_MFT1_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4242360CUL)) +#define bFM_MFT1_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42423610UL)) +#define bFM4_MFT1_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42423610UL)) +#define bFM_MFT1_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42423614UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42423614UL)) +#define bFM_MFT1_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42423618UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42423618UL)) +#define bFM_MFT1_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4242361CUL)) +#define bFM4_MFT1_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4242361CUL)) +#define bFM_MFT1_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42423620UL)) +#define bFM4_MFT1_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42423620UL)) +#define bFM_MFT1_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42423624UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42423624UL)) +#define bFM_MFT1_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42423628UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42423628UL)) +#define bFM_MFT1_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4242362CUL)) +#define bFM4_MFT1_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4242362CUL)) +#define bFM_MFT1_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42423630UL)) +#define bFM4_MFT1_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42423630UL)) +#define bFM_MFT1_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42423634UL)) +#define bFM4_MFT1_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42423634UL)) +#define bFM_MFT1_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42423638UL)) +#define bFM4_MFT1_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42423638UL)) +#define bFM_MFT1_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4242363CUL)) +#define bFM4_MFT1_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4242363CUL)) + + +/******************************************************************************* +* MFT Registers MFT2 +* Bitband Section +*******************************************************************************/ +#define bFM_MFT2_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42443AD8UL)) +#define bFM4_MFT2_ADCMP_ACMC0_MZCE *((volatile uint8_t *)(0x42443AD8UL)) +#define bFM_MFT2_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42443ADCUL)) +#define bFM4_MFT2_ADCMP_ACMC0_MPCE *((volatile uint8_t *)(0x42443ADCUL)) + +#define bFM_MFT2_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42443B58UL)) +#define bFM4_MFT2_ADCMP_ACMC1_MZCE *((volatile uint8_t *)(0x42443B58UL)) +#define bFM_MFT2_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42443B5CUL)) +#define bFM4_MFT2_ADCMP_ACMC1_MPCE *((volatile uint8_t *)(0x42443B5CUL)) + +#define bFM_MFT2_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42443BD8UL)) +#define bFM4_MFT2_ADCMP_ACMC2_MZCE *((volatile uint8_t *)(0x42443BD8UL)) +#define bFM_MFT2_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42443BDCUL)) +#define bFM4_MFT2_ADCMP_ACMC2_MPCE *((volatile uint8_t *)(0x42443BDCUL)) + +#define bFM_MFT2_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42443C58UL)) +#define bFM4_MFT2_ADCMP_ACMC3_MZCE *((volatile uint8_t *)(0x42443C58UL)) +#define bFM_MFT2_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42443C5CUL)) +#define bFM4_MFT2_ADCMP_ACMC3_MPCE *((volatile uint8_t *)(0x42443C5CUL)) + +#define bFM_MFT2_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42443CD8UL)) +#define bFM4_MFT2_ADCMP_ACMC4_MZCE *((volatile uint8_t *)(0x42443CD8UL)) +#define bFM_MFT2_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42443CDCUL)) +#define bFM4_MFT2_ADCMP_ACMC4_MPCE *((volatile uint8_t *)(0x42443CDCUL)) + +#define bFM_MFT2_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42443D58UL)) +#define bFM4_MFT2_ADCMP_ACMC5_MZCE *((volatile uint8_t *)(0x42443D58UL)) +#define bFM_MFT2_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42443D5CUL)) +#define bFM4_MFT2_ADCMP_ACMC5_MPCE *((volatile uint8_t *)(0x42443D5CUL)) + +#define bFM_MFT2_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42443A94UL)) +#define bFM4_MFT2_ADCMP_ACSC0_APBM *((volatile uint8_t *)(0x42443A94UL)) + +#define bFM_MFT2_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42443B14UL)) +#define bFM4_MFT2_ADCMP_ACSC1_APBM *((volatile uint8_t *)(0x42443B14UL)) + +#define bFM_MFT2_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42443B94UL)) +#define bFM4_MFT2_ADCMP_ACSC2_APBM *((volatile uint8_t *)(0x42443B94UL)) + +#define bFM_MFT2_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42443C14UL)) +#define bFM4_MFT2_ADCMP_ACSC3_APBM *((volatile uint8_t *)(0x42443C14UL)) + +#define bFM_MFT2_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42443C94UL)) +#define bFM4_MFT2_ADCMP_ACSC4_APBM *((volatile uint8_t *)(0x42443C94UL)) + +#define bFM_MFT2_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42443D14UL)) +#define bFM4_MFT2_ADCMP_ACSC5_APBM *((volatile uint8_t *)(0x42443D14UL)) + +#define bFM_MFT2_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42443AA0UL)) +#define bFM4_MFT2_ADCMP_ACSD0_AMOD *((volatile uint8_t *)(0x42443AA0UL)) +#define bFM_MFT2_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42443AA4UL)) +#define bFM4_MFT2_ADCMP_ACSD0_OCUS *((volatile uint8_t *)(0x42443AA4UL)) +#define bFM_MFT2_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42443AB0UL)) +#define bFM4_MFT2_ADCMP_ACSD0_DE *((volatile uint8_t *)(0x42443AB0UL)) +#define bFM_MFT2_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42443AB4UL)) +#define bFM4_MFT2_ADCMP_ACSD0_PE *((volatile uint8_t *)(0x42443AB4UL)) +#define bFM_MFT2_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42443AB8UL)) +#define bFM4_MFT2_ADCMP_ACSD0_UE *((volatile uint8_t *)(0x42443AB8UL)) +#define bFM_MFT2_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42443ABCUL)) +#define bFM4_MFT2_ADCMP_ACSD0_ZE *((volatile uint8_t *)(0x42443ABCUL)) + +#define bFM_MFT2_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42443B20UL)) +#define bFM4_MFT2_ADCMP_ACSD1_AMOD *((volatile uint8_t *)(0x42443B20UL)) +#define bFM_MFT2_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42443B24UL)) +#define bFM4_MFT2_ADCMP_ACSD1_OCUS *((volatile uint8_t *)(0x42443B24UL)) +#define bFM_MFT2_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42443B30UL)) +#define bFM4_MFT2_ADCMP_ACSD1_DE *((volatile uint8_t *)(0x42443B30UL)) +#define bFM_MFT2_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42443B34UL)) +#define bFM4_MFT2_ADCMP_ACSD1_PE *((volatile uint8_t *)(0x42443B34UL)) +#define bFM_MFT2_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42443B38UL)) +#define bFM4_MFT2_ADCMP_ACSD1_UE *((volatile uint8_t *)(0x42443B38UL)) +#define bFM_MFT2_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42443B3CUL)) +#define bFM4_MFT2_ADCMP_ACSD1_ZE *((volatile uint8_t *)(0x42443B3CUL)) + +#define bFM_MFT2_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42443BA0UL)) +#define bFM4_MFT2_ADCMP_ACSD2_AMOD *((volatile uint8_t *)(0x42443BA0UL)) +#define bFM_MFT2_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42443BA4UL)) +#define bFM4_MFT2_ADCMP_ACSD2_OCUS *((volatile uint8_t *)(0x42443BA4UL)) +#define bFM_MFT2_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42443BB0UL)) +#define bFM4_MFT2_ADCMP_ACSD2_DE *((volatile uint8_t *)(0x42443BB0UL)) +#define bFM_MFT2_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42443BB4UL)) +#define bFM4_MFT2_ADCMP_ACSD2_PE *((volatile uint8_t *)(0x42443BB4UL)) +#define bFM_MFT2_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42443BB8UL)) +#define bFM4_MFT2_ADCMP_ACSD2_UE *((volatile uint8_t *)(0x42443BB8UL)) +#define bFM_MFT2_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42443BBCUL)) +#define bFM4_MFT2_ADCMP_ACSD2_ZE *((volatile uint8_t *)(0x42443BBCUL)) + +#define bFM_MFT2_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42443C20UL)) +#define bFM4_MFT2_ADCMP_ACSD3_AMOD *((volatile uint8_t *)(0x42443C20UL)) +#define bFM_MFT2_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42443C24UL)) +#define bFM4_MFT2_ADCMP_ACSD3_OCUS *((volatile uint8_t *)(0x42443C24UL)) +#define bFM_MFT2_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42443C30UL)) +#define bFM4_MFT2_ADCMP_ACSD3_DE *((volatile uint8_t *)(0x42443C30UL)) +#define bFM_MFT2_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42443C34UL)) +#define bFM4_MFT2_ADCMP_ACSD3_PE *((volatile uint8_t *)(0x42443C34UL)) +#define bFM_MFT2_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42443C38UL)) +#define bFM4_MFT2_ADCMP_ACSD3_UE *((volatile uint8_t *)(0x42443C38UL)) +#define bFM_MFT2_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42443C3CUL)) +#define bFM4_MFT2_ADCMP_ACSD3_ZE *((volatile uint8_t *)(0x42443C3CUL)) + +#define bFM_MFT2_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42443CA0UL)) +#define bFM4_MFT2_ADCMP_ACSD4_AMOD *((volatile uint8_t *)(0x42443CA0UL)) +#define bFM_MFT2_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42443CA4UL)) +#define bFM4_MFT2_ADCMP_ACSD4_OCUS *((volatile uint8_t *)(0x42443CA4UL)) +#define bFM_MFT2_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42443CB0UL)) +#define bFM4_MFT2_ADCMP_ACSD4_DE *((volatile uint8_t *)(0x42443CB0UL)) +#define bFM_MFT2_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42443CB4UL)) +#define bFM4_MFT2_ADCMP_ACSD4_PE *((volatile uint8_t *)(0x42443CB4UL)) +#define bFM_MFT2_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42443CB8UL)) +#define bFM4_MFT2_ADCMP_ACSD4_UE *((volatile uint8_t *)(0x42443CB8UL)) +#define bFM_MFT2_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42443CBCUL)) +#define bFM4_MFT2_ADCMP_ACSD4_ZE *((volatile uint8_t *)(0x42443CBCUL)) + +#define bFM_MFT2_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42443D20UL)) +#define bFM4_MFT2_ADCMP_ACSD5_AMOD *((volatile uint8_t *)(0x42443D20UL)) +#define bFM_MFT2_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42443D24UL)) +#define bFM4_MFT2_ADCMP_ACSD5_OCUS *((volatile uint8_t *)(0x42443D24UL)) +#define bFM_MFT2_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42443D30UL)) +#define bFM4_MFT2_ADCMP_ACSD5_DE *((volatile uint8_t *)(0x42443D30UL)) +#define bFM_MFT2_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42443D34UL)) +#define bFM4_MFT2_ADCMP_ACSD5_PE *((volatile uint8_t *)(0x42443D34UL)) +#define bFM_MFT2_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42443D38UL)) +#define bFM4_MFT2_ADCMP_ACSD5_UE *((volatile uint8_t *)(0x42443D38UL)) +#define bFM_MFT2_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42443D3CUL)) +#define bFM4_MFT2_ADCMP_ACSD5_ZE *((volatile uint8_t *)(0x42443D3CUL)) + +#define bFM_MFT2_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42442C80UL)) +#define bFM4_MFT2_FRT_TCAL_STOP00 *((volatile uint32_t*)(0x42442C80UL)) +#define bFM_MFT2_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42442C84UL)) +#define bFM4_MFT2_FRT_TCAL_STOP01 *((volatile uint32_t*)(0x42442C84UL)) +#define bFM_MFT2_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42442C88UL)) +#define bFM4_MFT2_FRT_TCAL_STOP02 *((volatile uint32_t*)(0x42442C88UL)) +#define bFM_MFT2_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42442C8CUL)) +#define bFM4_MFT2_FRT_TCAL_STOP10 *((volatile uint32_t*)(0x42442C8CUL)) +#define bFM_MFT2_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42442C90UL)) +#define bFM4_MFT2_FRT_TCAL_STOP11 *((volatile uint32_t*)(0x42442C90UL)) +#define bFM_MFT2_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42442C94UL)) +#define bFM4_MFT2_FRT_TCAL_STOP12 *((volatile uint32_t*)(0x42442C94UL)) +#define bFM_MFT2_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42442C98UL)) +#define bFM4_MFT2_FRT_TCAL_STOP20 *((volatile uint32_t*)(0x42442C98UL)) +#define bFM_MFT2_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42442C9CUL)) +#define bFM4_MFT2_FRT_TCAL_STOP21 *((volatile uint32_t*)(0x42442C9CUL)) +#define bFM_MFT2_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42442CA0UL)) +#define bFM4_MFT2_FRT_TCAL_STOP22 *((volatile uint32_t*)(0x42442CA0UL)) +#define bFM_MFT2_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42442CC0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR00 *((volatile uint32_t*)(0x42442CC0UL)) +#define bFM_MFT2_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42442CC4UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR01 *((volatile uint32_t*)(0x42442CC4UL)) +#define bFM_MFT2_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42442CC8UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR02 *((volatile uint32_t*)(0x42442CC8UL)) +#define bFM_MFT2_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42442CCCUL)) +#define bFM4_MFT2_FRT_TCAL_SCLR10 *((volatile uint32_t*)(0x42442CCCUL)) +#define bFM_MFT2_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42442CD0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR11 *((volatile uint32_t*)(0x42442CD0UL)) +#define bFM_MFT2_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42442CD4UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR12 *((volatile uint32_t*)(0x42442CD4UL)) +#define bFM_MFT2_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42442CD8UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR20 *((volatile uint32_t*)(0x42442CD8UL)) +#define bFM_MFT2_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42442CDCUL)) +#define bFM4_MFT2_FRT_TCAL_SCLR21 *((volatile uint32_t*)(0x42442CDCUL)) +#define bFM_MFT2_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42442CE0UL)) +#define bFM4_MFT2_FRT_TCAL_SCLR22 *((volatile uint32_t*)(0x42442CE0UL)) + +#define bFM_MFT2_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42442910UL)) +#define bFM4_MFT2_FRT_TCSA0_SCLR *((volatile uint8_t *)(0x42442910UL)) +#define bFM_MFT2_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42442914UL)) +#define bFM4_MFT2_FRT_TCSA0_MODE *((volatile uint8_t *)(0x42442914UL)) +#define bFM_MFT2_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42442918UL)) +#define bFM4_MFT2_FRT_TCSA0_STOP *((volatile uint8_t *)(0x42442918UL)) +#define bFM_MFT2_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4244291CUL)) +#define bFM4_MFT2_FRT_TCSA0_BFE *((volatile uint8_t *)(0x4244291CUL)) +#define bFM_MFT2_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42442920UL)) +#define bFM4_MFT2_FRT_TCSA0_ICRE *((volatile uint8_t *)(0x42442920UL)) +#define bFM_MFT2_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42442924UL)) +#define bFM4_MFT2_FRT_TCSA0_ICLR *((volatile uint8_t *)(0x42442924UL)) +#define bFM_MFT2_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42442934UL)) +#define bFM4_MFT2_FRT_TCSA0_IRQZE *((volatile uint8_t *)(0x42442934UL)) +#define bFM_MFT2_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42442938UL)) +#define bFM4_MFT2_FRT_TCSA0_IRQZF *((volatile uint8_t *)(0x42442938UL)) +#define bFM_MFT2_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4244293CUL)) +#define bFM4_MFT2_FRT_TCSA0_ECKE *((volatile uint8_t *)(0x4244293CUL)) + +#define bFM_MFT2_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42442A90UL)) +#define bFM4_MFT2_FRT_TCSA1_SCLR *((volatile uint8_t *)(0x42442A90UL)) +#define bFM_MFT2_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42442A94UL)) +#define bFM4_MFT2_FRT_TCSA1_MODE *((volatile uint8_t *)(0x42442A94UL)) +#define bFM_MFT2_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42442A98UL)) +#define bFM4_MFT2_FRT_TCSA1_STOP *((volatile uint8_t *)(0x42442A98UL)) +#define bFM_MFT2_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42442A9CUL)) +#define bFM4_MFT2_FRT_TCSA1_BFE *((volatile uint8_t *)(0x42442A9CUL)) +#define bFM_MFT2_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42442AA0UL)) +#define bFM4_MFT2_FRT_TCSA1_ICRE *((volatile uint8_t *)(0x42442AA0UL)) +#define bFM_MFT2_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42442AA4UL)) +#define bFM4_MFT2_FRT_TCSA1_ICLR *((volatile uint8_t *)(0x42442AA4UL)) +#define bFM_MFT2_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42442AB4UL)) +#define bFM4_MFT2_FRT_TCSA1_IRQZE *((volatile uint8_t *)(0x42442AB4UL)) +#define bFM_MFT2_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42442AB8UL)) +#define bFM4_MFT2_FRT_TCSA1_IRQZF *((volatile uint8_t *)(0x42442AB8UL)) +#define bFM_MFT2_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42442ABCUL)) +#define bFM4_MFT2_FRT_TCSA1_ECKE *((volatile uint8_t *)(0x42442ABCUL)) + +#define bFM_MFT2_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42442C10UL)) +#define bFM4_MFT2_FRT_TCSA2_SCLR *((volatile uint8_t *)(0x42442C10UL)) +#define bFM_MFT2_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42442C14UL)) +#define bFM4_MFT2_FRT_TCSA2_MODE *((volatile uint8_t *)(0x42442C14UL)) +#define bFM_MFT2_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42442C18UL)) +#define bFM4_MFT2_FRT_TCSA2_STOP *((volatile uint8_t *)(0x42442C18UL)) +#define bFM_MFT2_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42442C1CUL)) +#define bFM4_MFT2_FRT_TCSA2_BFE *((volatile uint8_t *)(0x42442C1CUL)) +#define bFM_MFT2_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42442C20UL)) +#define bFM4_MFT2_FRT_TCSA2_ICRE *((volatile uint8_t *)(0x42442C20UL)) +#define bFM_MFT2_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42442C24UL)) +#define bFM4_MFT2_FRT_TCSA2_ICLR *((volatile uint8_t *)(0x42442C24UL)) +#define bFM_MFT2_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42442C34UL)) +#define bFM4_MFT2_FRT_TCSA2_IRQZE *((volatile uint8_t *)(0x42442C34UL)) +#define bFM_MFT2_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42442C38UL)) +#define bFM4_MFT2_FRT_TCSA2_IRQZF *((volatile uint8_t *)(0x42442C38UL)) +#define bFM_MFT2_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42442C3CUL)) +#define bFM4_MFT2_FRT_TCSA2_ECKE *((volatile uint8_t *)(0x42442C3CUL)) + +#define bFM_MFT2_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42443D80UL)) +#define bFM4_MFT2_FRT_TCSD_OFMD1 *((volatile uint8_t *)(0x42443D80UL)) +#define bFM_MFT2_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42443D84UL)) +#define bFM4_MFT2_FRT_TCSD_OFMD2 *((volatile uint8_t *)(0x42443D84UL)) + +#define bFM_MFT2_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42443090UL)) +#define bFM4_MFT2_ICU_ICSA10_ICE0 *((volatile uint8_t *)(0x42443090UL)) +#define bFM_MFT2_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42443094UL)) +#define bFM4_MFT2_ICU_ICSA10_ICE1 *((volatile uint8_t *)(0x42443094UL)) +#define bFM_MFT2_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42443098UL)) +#define bFM4_MFT2_ICU_ICSA10_ICP0 *((volatile uint8_t *)(0x42443098UL)) +#define bFM_MFT2_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4244309CUL)) +#define bFM4_MFT2_ICU_ICSA10_ICP1 *((volatile uint8_t *)(0x4244309CUL)) + +#define bFM_MFT2_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42443110UL)) +#define bFM4_MFT2_ICU_ICSA32_ICE2 *((volatile uint8_t *)(0x42443110UL)) +#define bFM_MFT2_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42443114UL)) +#define bFM4_MFT2_ICU_ICSA32_ICE3 *((volatile uint8_t *)(0x42443114UL)) +#define bFM_MFT2_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42443118UL)) +#define bFM4_MFT2_ICU_ICSA32_ICP2 *((volatile uint8_t *)(0x42443118UL)) +#define bFM_MFT2_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4244311CUL)) +#define bFM4_MFT2_ICU_ICSA32_ICP3 *((volatile uint8_t *)(0x4244311CUL)) + +#define bFM_MFT2_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424430A0UL)) +#define bFM4_MFT2_ICU_ICSB10_IEI0 *((volatile uint8_t *)(0x424430A0UL)) +#define bFM_MFT2_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424430A4UL)) +#define bFM4_MFT2_ICU_ICSB10_IEI1 *((volatile uint8_t *)(0x424430A4UL)) + +#define bFM_MFT2_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42443120UL)) +#define bFM4_MFT2_ICU_ICSB32_IEI2 *((volatile uint8_t *)(0x42443120UL)) +#define bFM_MFT2_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42443124UL)) +#define bFM4_MFT2_ICU_ICSB32_IEI3 *((volatile uint8_t *)(0x42443124UL)) + +#define bFM_MFT2_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42442300UL)) +#define bFM4_MFT2_OCU_OCSA10_CST0 *((volatile uint8_t *)(0x42442300UL)) +#define bFM_MFT2_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42442304UL)) +#define bFM4_MFT2_OCU_OCSA10_CST1 *((volatile uint8_t *)(0x42442304UL)) +#define bFM_MFT2_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42442310UL)) +#define bFM4_MFT2_OCU_OCSA10_IOE0 *((volatile uint8_t *)(0x42442310UL)) +#define bFM_MFT2_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42442314UL)) +#define bFM4_MFT2_OCU_OCSA10_IOE1 *((volatile uint8_t *)(0x42442314UL)) +#define bFM_MFT2_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42442318UL)) +#define bFM4_MFT2_OCU_OCSA10_IOP0 *((volatile uint8_t *)(0x42442318UL)) +#define bFM_MFT2_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4244231CUL)) +#define bFM4_MFT2_OCU_OCSA10_IOP1 *((volatile uint8_t *)(0x4244231CUL)) + +#define bFM_MFT2_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42442380UL)) +#define bFM4_MFT2_OCU_OCSA32_CST2 *((volatile uint8_t *)(0x42442380UL)) +#define bFM_MFT2_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42442384UL)) +#define bFM4_MFT2_OCU_OCSA32_CST3 *((volatile uint8_t *)(0x42442384UL)) +#define bFM_MFT2_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42442390UL)) +#define bFM4_MFT2_OCU_OCSA32_IOE2 *((volatile uint8_t *)(0x42442390UL)) +#define bFM_MFT2_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42442394UL)) +#define bFM4_MFT2_OCU_OCSA32_IOE3 *((volatile uint8_t *)(0x42442394UL)) +#define bFM_MFT2_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42442398UL)) +#define bFM4_MFT2_OCU_OCSA32_IOP2 *((volatile uint8_t *)(0x42442398UL)) +#define bFM_MFT2_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4244239CUL)) +#define bFM4_MFT2_OCU_OCSA32_IOP3 *((volatile uint8_t *)(0x4244239CUL)) + +#define bFM_MFT2_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42442400UL)) +#define bFM4_MFT2_OCU_OCSA54_CST4 *((volatile uint8_t *)(0x42442400UL)) +#define bFM_MFT2_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42442404UL)) +#define bFM4_MFT2_OCU_OCSA54_CST5 *((volatile uint8_t *)(0x42442404UL)) +#define bFM_MFT2_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42442410UL)) +#define bFM4_MFT2_OCU_OCSA54_IOE4 *((volatile uint8_t *)(0x42442410UL)) +#define bFM_MFT2_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42442414UL)) +#define bFM4_MFT2_OCU_OCSA54_IOE5 *((volatile uint8_t *)(0x42442414UL)) +#define bFM_MFT2_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42442418UL)) +#define bFM4_MFT2_OCU_OCSA54_IOP4 *((volatile uint8_t *)(0x42442418UL)) +#define bFM_MFT2_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4244241CUL)) +#define bFM4_MFT2_OCU_OCSA54_IOP5 *((volatile uint8_t *)(0x4244241CUL)) + +#define bFM_MFT2_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42442320UL)) +#define bFM4_MFT2_OCU_OCSB10_OTD0 *((volatile uint8_t *)(0x42442320UL)) +#define bFM_MFT2_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42442324UL)) +#define bFM4_MFT2_OCU_OCSB10_OTD1 *((volatile uint8_t *)(0x42442324UL)) +#define bFM_MFT2_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42442330UL)) +#define bFM4_MFT2_OCU_OCSB10_CMOD *((volatile uint8_t *)(0x42442330UL)) +#define bFM_MFT2_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4244233CUL)) +#define bFM4_MFT2_OCU_OCSB10_FM4 *((volatile uint8_t *)(0x4244233CUL)) + +#define bFM_MFT2_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424423A0UL)) +#define bFM4_MFT2_OCU_OCSB32_OTD2 *((volatile uint8_t *)(0x424423A0UL)) +#define bFM_MFT2_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424423A4UL)) +#define bFM4_MFT2_OCU_OCSB32_OTD3 *((volatile uint8_t *)(0x424423A4UL)) +#define bFM_MFT2_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424423B0UL)) +#define bFM4_MFT2_OCU_OCSB32_CMOD *((volatile uint8_t *)(0x424423B0UL)) +#define bFM_MFT2_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424423BCUL)) +#define bFM4_MFT2_OCU_OCSB32_FM4 *((volatile uint8_t *)(0x424423BCUL)) + +#define bFM_MFT2_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42442420UL)) +#define bFM4_MFT2_OCU_OCSB54_OTD4 *((volatile uint8_t *)(0x42442420UL)) +#define bFM_MFT2_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42442424UL)) +#define bFM4_MFT2_OCU_OCSB54_OTD5 *((volatile uint8_t *)(0x42442424UL)) +#define bFM_MFT2_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42442430UL)) +#define bFM4_MFT2_OCU_OCSB54_CMOD *((volatile uint8_t *)(0x42442430UL)) +#define bFM_MFT2_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4244243CUL)) +#define bFM4_MFT2_OCU_OCSB54_FM4 *((volatile uint8_t *)(0x4244243CUL)) + +#define bFM_MFT2_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424424A0UL)) +#define bFM4_MFT2_OCU_OCSC_MOD0 *((volatile uint8_t *)(0x424424A0UL)) +#define bFM_MFT2_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424424A4UL)) +#define bFM4_MFT2_OCU_OCSC_MOD1 *((volatile uint8_t *)(0x424424A4UL)) +#define bFM_MFT2_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424424A8UL)) +#define bFM4_MFT2_OCU_OCSC_MOD2 *((volatile uint8_t *)(0x424424A8UL)) +#define bFM_MFT2_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424424ACUL)) +#define bFM4_MFT2_OCU_OCSC_MOD3 *((volatile uint8_t *)(0x424424ACUL)) +#define bFM_MFT2_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424424B0UL)) +#define bFM4_MFT2_OCU_OCSC_MOD4 *((volatile uint8_t *)(0x424424B0UL)) +#define bFM_MFT2_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424424B4UL)) +#define bFM4_MFT2_OCU_OCSC_MOD5 *((volatile uint8_t *)(0x424424B4UL)) + +#define bFM_MFT2_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42442360UL)) +#define bFM4_MFT2_OCU_OCSD10_OPBM0 *((volatile uint8_t *)(0x42442360UL)) +#define bFM_MFT2_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42442364UL)) +#define bFM4_MFT2_OCU_OCSD10_OPBM1 *((volatile uint8_t *)(0x42442364UL)) +#define bFM_MFT2_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42442368UL)) +#define bFM4_MFT2_OCU_OCSD10_OEBM0 *((volatile uint8_t *)(0x42442368UL)) +#define bFM_MFT2_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4244236CUL)) +#define bFM4_MFT2_OCU_OCSD10_OEBM1 *((volatile uint8_t *)(0x4244236CUL)) +#define bFM_MFT2_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42442370UL)) +#define bFM4_MFT2_OCU_OCSD10_OFEX0 *((volatile uint8_t *)(0x42442370UL)) +#define bFM_MFT2_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42442374UL)) +#define bFM4_MFT2_OCU_OCSD10_OFEX1 *((volatile uint8_t *)(0x42442374UL)) + +#define bFM_MFT2_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424423E0UL)) +#define bFM4_MFT2_OCU_OCSD32_OPBM2 *((volatile uint8_t *)(0x424423E0UL)) +#define bFM_MFT2_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424423E4UL)) +#define bFM4_MFT2_OCU_OCSD32_OPBM3 *((volatile uint8_t *)(0x424423E4UL)) +#define bFM_MFT2_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424423E8UL)) +#define bFM4_MFT2_OCU_OCSD32_OEBM2 *((volatile uint8_t *)(0x424423E8UL)) +#define bFM_MFT2_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424423ECUL)) +#define bFM4_MFT2_OCU_OCSD32_OEBM3 *((volatile uint8_t *)(0x424423ECUL)) +#define bFM_MFT2_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424423F0UL)) +#define bFM4_MFT2_OCU_OCSD32_OFEX2 *((volatile uint8_t *)(0x424423F0UL)) +#define bFM_MFT2_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424423F4UL)) +#define bFM4_MFT2_OCU_OCSD32_OFEX3 *((volatile uint8_t *)(0x424423F4UL)) + +#define bFM_MFT2_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42442460UL)) +#define bFM4_MFT2_OCU_OCSD54_OPBM4 *((volatile uint8_t *)(0x42442460UL)) +#define bFM_MFT2_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42442464UL)) +#define bFM4_MFT2_OCU_OCSD54_OPBM5 *((volatile uint8_t *)(0x42442464UL)) +#define bFM_MFT2_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42442468UL)) +#define bFM4_MFT2_OCU_OCSD54_OEBM4 *((volatile uint8_t *)(0x42442468UL)) +#define bFM_MFT2_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4244246CUL)) +#define bFM4_MFT2_OCU_OCSD54_OEBM5 *((volatile uint8_t *)(0x4244246CUL)) +#define bFM_MFT2_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42442470UL)) +#define bFM4_MFT2_OCU_OCSD54_OFEX4 *((volatile uint8_t *)(0x42442470UL)) +#define bFM_MFT2_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42442474UL)) +#define bFM4_MFT2_OCU_OCSD54_OFEX5 *((volatile uint8_t *)(0x42442474UL)) + +#define bFM_MFT2_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42443680UL)) +#define bFM4_MFT2_WFG_NZCL_DTIEA *((volatile uint16_t*)(0x42443680UL)) +#define bFM_MFT2_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42443690UL)) +#define bFM4_MFT2_WFG_NZCL_SDTI *((volatile uint16_t*)(0x42443690UL)) +#define bFM_MFT2_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42443694UL)) +#define bFM4_MFT2_WFG_NZCL_DTIEB *((volatile uint16_t*)(0x42443694UL)) +#define bFM_MFT2_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4244369CUL)) +#define bFM4_MFT2_WFG_NZCL_DHOLD *((volatile uint16_t*)(0x4244369CUL)) +#define bFM_MFT2_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424436A0UL)) +#define bFM4_MFT2_WFG_NZCL_DIMA *((volatile uint16_t*)(0x424436A0UL)) +#define bFM_MFT2_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424436A4UL)) +#define bFM4_MFT2_WFG_NZCL_DIMB *((volatile uint16_t*)(0x424436A4UL)) +#define bFM_MFT2_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424436B0UL)) +#define bFM4_MFT2_WFG_NZCL_WIM10 *((volatile uint16_t*)(0x424436B0UL)) +#define bFM_MFT2_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424436B4UL)) +#define bFM4_MFT2_WFG_NZCL_WIM32 *((volatile uint16_t*)(0x424436B4UL)) +#define bFM_MFT2_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424436B8UL)) +#define bFM4_MFT2_WFG_NZCL_WIM54 *((volatile uint16_t*)(0x424436B8UL)) + +#define bFM_MFT2_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42443600UL)) +#define bFM4_MFT2_WFG_WFIR_DTIFA *((volatile uint16_t*)(0x42443600UL)) +#define bFM_MFT2_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42443604UL)) +#define bFM4_MFT2_WFG_WFIR_DTICA *((volatile uint16_t*)(0x42443604UL)) +#define bFM_MFT2_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42443608UL)) +#define bFM4_MFT2_WFG_WFIR_DTIFB *((volatile uint16_t*)(0x42443608UL)) +#define bFM_MFT2_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4244360CUL)) +#define bFM4_MFT2_WFG_WFIR_DTICB *((volatile uint16_t*)(0x4244360CUL)) +#define bFM_MFT2_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42443610UL)) +#define bFM4_MFT2_WFG_WFIR_TMIF10 *((volatile uint16_t*)(0x42443610UL)) +#define bFM_MFT2_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42443614UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC10 *((volatile uint16_t*)(0x42443614UL)) +#define bFM_MFT2_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42443618UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE10 *((volatile uint16_t*)(0x42443618UL)) +#define bFM_MFT2_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4244361CUL)) +#define bFM4_MFT2_WFG_WFIR_TMIS10 *((volatile uint16_t*)(0x4244361CUL)) +#define bFM_MFT2_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42443620UL)) +#define bFM4_MFT2_WFG_WFIR_TMIF32 *((volatile uint16_t*)(0x42443620UL)) +#define bFM_MFT2_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42443624UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC32 *((volatile uint16_t*)(0x42443624UL)) +#define bFM_MFT2_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42443628UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE32 *((volatile uint16_t*)(0x42443628UL)) +#define bFM_MFT2_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4244362CUL)) +#define bFM4_MFT2_WFG_WFIR_TMIS32 *((volatile uint16_t*)(0x4244362CUL)) +#define bFM_MFT2_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42443630UL)) +#define bFM4_MFT2_WFG_WFIR_TMIF54 *((volatile uint16_t*)(0x42443630UL)) +#define bFM_MFT2_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42443634UL)) +#define bFM4_MFT2_WFG_WFIR_TMIC54 *((volatile uint16_t*)(0x42443634UL)) +#define bFM_MFT2_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42443638UL)) +#define bFM4_MFT2_WFG_WFIR_TMIE54 *((volatile uint16_t*)(0x42443638UL)) +#define bFM_MFT2_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4244363CUL)) +#define bFM4_MFT2_WFG_WFIR_TMIS54 *((volatile uint16_t*)(0x4244363CUL)) + + +/******************************************************************************* +* PCRC Registers PCRC +* Bitband Section +*******************************************************************************/ +#define bFM_PCRC_PCRC_CFG_CIRQCLR *((volatile uint8_t *)(0x43000180UL)) +#define bFM4_PCRC_PCRC_CFG_CIRQCLR *((volatile uint8_t *)(0x43000180UL)) +#define bFM_PCRC_PCRC_CFG_CIRQ *((volatile uint8_t *)(0x430001E0UL)) +#define bFM4_PCRC_PCRC_CFG_CIRQ *((volatile uint8_t *)(0x430001E0UL)) +#define bFM_PCRC_PCRC_CFG_CIEN *((volatile uint8_t *)(0x430001E4UL)) +#define bFM4_PCRC_PCRC_CFG_CIEN *((volatile uint8_t *)(0x430001E4UL)) +#define bFM_PCRC_PCRC_CFG_CDEN *((volatile uint8_t *)(0x430001E8UL)) +#define bFM4_PCRC_PCRC_CFG_CDEN *((volatile uint8_t *)(0x430001E8UL)) +#define bFM_PCRC_PCRC_CFG_LOCK *((volatile uint8_t *)(0x430001F0UL)) +#define bFM4_PCRC_PCRC_CFG_LOCK *((volatile uint8_t *)(0x430001F0UL)) + + +/******************************************************************************* +* QPRC Registers QPRC0 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC0_QCR_PSTP *((volatile uint8_t *)(0x424C0310UL)) +#define bFM4_QPRC0_QCR_PSTP *((volatile uint8_t *)(0x424C0310UL)) +#define bFM_QPRC0_QCR_CGSC *((volatile uint8_t *)(0x424C0314UL)) +#define bFM4_QPRC0_QCR_CGSC *((volatile uint8_t *)(0x424C0314UL)) +#define bFM_QPRC0_QCR_RSEL *((volatile uint8_t *)(0x424C0318UL)) +#define bFM4_QPRC0_QCR_RSEL *((volatile uint8_t *)(0x424C0318UL)) +#define bFM_QPRC0_QCR_SWAP *((volatile uint8_t *)(0x424C031CUL)) +#define bFM4_QPRC0_QCR_SWAP *((volatile uint8_t *)(0x424C031CUL)) + +#define bFM_QPRC0_QECR_ORNGMD *((volatile uint8_t *)(0x424C0380UL)) +#define bFM4_QPRC0_QECR_ORNGMD *((volatile uint8_t *)(0x424C0380UL)) +#define bFM_QPRC0_QECR_ORNGF *((volatile uint8_t *)(0x424C0384UL)) +#define bFM4_QPRC0_QECR_ORNGF *((volatile uint8_t *)(0x424C0384UL)) +#define bFM_QPRC0_QECR_ORNGIE *((volatile uint8_t *)(0x424C0388UL)) +#define bFM4_QPRC0_QECR_ORNGIE *((volatile uint8_t *)(0x424C0388UL)) +#define bFM_QPRC0_QECR_PEC *((volatile uint8_t *)(0x424C038CUL)) +#define bFM4_QPRC0_QECR_PEC *((volatile uint8_t *)(0x424C038CUL)) + +#define bFM_QPRC0_QICRH_CDCIE *((volatile uint8_t *)(0x424C02A0UL)) +#define bFM4_QPRC0_QICRH_CDCIE *((volatile uint8_t *)(0x424C02A0UL)) +#define bFM_QPRC0_QICRH_CDCF *((volatile uint8_t *)(0x424C02A4UL)) +#define bFM4_QPRC0_QICRH_CDCF *((volatile uint8_t *)(0x424C02A4UL)) +#define bFM_QPRC0_QICRH_DIRPC *((volatile uint8_t *)(0x424C02A8UL)) +#define bFM4_QPRC0_QICRH_DIRPC *((volatile uint8_t *)(0x424C02A8UL)) +#define bFM_QPRC0_QICRH_DIROU *((volatile uint8_t *)(0x424C02ACUL)) +#define bFM4_QPRC0_QICRH_DIROU *((volatile uint8_t *)(0x424C02ACUL)) +#define bFM_QPRC0_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C02B0UL)) +#define bFM4_QPRC0_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C02B0UL)) +#define bFM_QPRC0_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C02B4UL)) +#define bFM4_QPRC0_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C02B4UL)) + +#define bFM_QPRC0_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0280UL)) +#define bFM4_QPRC0_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0280UL)) +#define bFM_QPRC0_QICRL_QPCMF *((volatile uint8_t *)(0x424C0284UL)) +#define bFM4_QPRC0_QICRL_QPCMF *((volatile uint8_t *)(0x424C0284UL)) +#define bFM_QPRC0_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0288UL)) +#define bFM4_QPRC0_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0288UL)) +#define bFM_QPRC0_QICRL_QPRCMF *((volatile uint8_t *)(0x424C028CUL)) +#define bFM4_QPRC0_QICRL_QPRCMF *((volatile uint8_t *)(0x424C028CUL)) +#define bFM_QPRC0_QICRL_OUZIE *((volatile uint8_t *)(0x424C0290UL)) +#define bFM4_QPRC0_QICRL_OUZIE *((volatile uint8_t *)(0x424C0290UL)) +#define bFM_QPRC0_QICRL_UFDF *((volatile uint8_t *)(0x424C0294UL)) +#define bFM4_QPRC0_QICRL_UFDF *((volatile uint8_t *)(0x424C0294UL)) +#define bFM_QPRC0_QICRL_OFDF *((volatile uint8_t *)(0x424C0298UL)) +#define bFM4_QPRC0_QICRL_OFDF *((volatile uint8_t *)(0x424C0298UL)) +#define bFM_QPRC0_QICRL_ZIIF *((volatile uint8_t *)(0x424C029CUL)) +#define bFM4_QPRC0_QICRL_ZIIF *((volatile uint8_t *)(0x424C029CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC0_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC0_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2010UL)) +#define bFM4_QPRC0_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2010UL)) +#define bFM_QPRC0_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2014UL)) +#define bFM4_QPRC0_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2014UL)) + +#define bFM_QPRC0_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2090UL)) +#define bFM4_QPRC0_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2090UL)) +#define bFM_QPRC0_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2094UL)) +#define bFM4_QPRC0_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2094UL)) + +#define bFM_QPRC0_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2110UL)) +#define bFM4_QPRC0_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2110UL)) +#define bFM_QPRC0_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2114UL)) +#define bFM4_QPRC0_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2114UL)) + + +/******************************************************************************* +* QPRC Registers QPRC1 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC1_QCR_PSTP *((volatile uint8_t *)(0x424C0B10UL)) +#define bFM4_QPRC1_QCR_PSTP *((volatile uint8_t *)(0x424C0B10UL)) +#define bFM_QPRC1_QCR_CGSC *((volatile uint8_t *)(0x424C0B14UL)) +#define bFM4_QPRC1_QCR_CGSC *((volatile uint8_t *)(0x424C0B14UL)) +#define bFM_QPRC1_QCR_RSEL *((volatile uint8_t *)(0x424C0B18UL)) +#define bFM4_QPRC1_QCR_RSEL *((volatile uint8_t *)(0x424C0B18UL)) +#define bFM_QPRC1_QCR_SWAP *((volatile uint8_t *)(0x424C0B1CUL)) +#define bFM4_QPRC1_QCR_SWAP *((volatile uint8_t *)(0x424C0B1CUL)) + +#define bFM_QPRC1_QECR_ORNGMD *((volatile uint8_t *)(0x424C0B80UL)) +#define bFM4_QPRC1_QECR_ORNGMD *((volatile uint8_t *)(0x424C0B80UL)) +#define bFM_QPRC1_QECR_ORNGF *((volatile uint8_t *)(0x424C0B84UL)) +#define bFM4_QPRC1_QECR_ORNGF *((volatile uint8_t *)(0x424C0B84UL)) +#define bFM_QPRC1_QECR_ORNGIE *((volatile uint8_t *)(0x424C0B88UL)) +#define bFM4_QPRC1_QECR_ORNGIE *((volatile uint8_t *)(0x424C0B88UL)) +#define bFM_QPRC1_QECR_PEC *((volatile uint8_t *)(0x424C0B8CUL)) +#define bFM4_QPRC1_QECR_PEC *((volatile uint8_t *)(0x424C0B8CUL)) + +#define bFM_QPRC1_QICRH_CDCIE *((volatile uint8_t *)(0x424C0AA0UL)) +#define bFM4_QPRC1_QICRH_CDCIE *((volatile uint8_t *)(0x424C0AA0UL)) +#define bFM_QPRC1_QICRH_CDCF *((volatile uint8_t *)(0x424C0AA4UL)) +#define bFM4_QPRC1_QICRH_CDCF *((volatile uint8_t *)(0x424C0AA4UL)) +#define bFM_QPRC1_QICRH_DIRPC *((volatile uint8_t *)(0x424C0AA8UL)) +#define bFM4_QPRC1_QICRH_DIRPC *((volatile uint8_t *)(0x424C0AA8UL)) +#define bFM_QPRC1_QICRH_DIROU *((volatile uint8_t *)(0x424C0AACUL)) +#define bFM4_QPRC1_QICRH_DIROU *((volatile uint8_t *)(0x424C0AACUL)) +#define bFM_QPRC1_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C0AB0UL)) +#define bFM4_QPRC1_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C0AB0UL)) +#define bFM_QPRC1_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C0AB4UL)) +#define bFM4_QPRC1_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C0AB4UL)) + +#define bFM_QPRC1_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0A80UL)) +#define bFM4_QPRC1_QICRL_QPCMIE *((volatile uint8_t *)(0x424C0A80UL)) +#define bFM_QPRC1_QICRL_QPCMF *((volatile uint8_t *)(0x424C0A84UL)) +#define bFM4_QPRC1_QICRL_QPCMF *((volatile uint8_t *)(0x424C0A84UL)) +#define bFM_QPRC1_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0A88UL)) +#define bFM4_QPRC1_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C0A88UL)) +#define bFM_QPRC1_QICRL_QPRCMF *((volatile uint8_t *)(0x424C0A8CUL)) +#define bFM4_QPRC1_QICRL_QPRCMF *((volatile uint8_t *)(0x424C0A8CUL)) +#define bFM_QPRC1_QICRL_OUZIE *((volatile uint8_t *)(0x424C0A90UL)) +#define bFM4_QPRC1_QICRL_OUZIE *((volatile uint8_t *)(0x424C0A90UL)) +#define bFM_QPRC1_QICRL_UFDF *((volatile uint8_t *)(0x424C0A94UL)) +#define bFM4_QPRC1_QICRL_UFDF *((volatile uint8_t *)(0x424C0A94UL)) +#define bFM_QPRC1_QICRL_OFDF *((volatile uint8_t *)(0x424C0A98UL)) +#define bFM4_QPRC1_QICRL_OFDF *((volatile uint8_t *)(0x424C0A98UL)) +#define bFM_QPRC1_QICRL_ZIIF *((volatile uint8_t *)(0x424C0A9CUL)) +#define bFM4_QPRC1_QICRL_ZIIF *((volatile uint8_t *)(0x424C0A9CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC1_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC1_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2210UL)) +#define bFM4_QPRC1_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2210UL)) +#define bFM_QPRC1_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2214UL)) +#define bFM4_QPRC1_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2214UL)) + +#define bFM_QPRC1_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2290UL)) +#define bFM4_QPRC1_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2290UL)) +#define bFM_QPRC1_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2294UL)) +#define bFM4_QPRC1_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2294UL)) + +#define bFM_QPRC1_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2310UL)) +#define bFM4_QPRC1_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2310UL)) +#define bFM_QPRC1_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2314UL)) +#define bFM4_QPRC1_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2314UL)) + + +/******************************************************************************* +* QPRC Registers QPRC2 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC2_QCR_PSTP *((volatile uint8_t *)(0x424C1310UL)) +#define bFM4_QPRC2_QCR_PSTP *((volatile uint8_t *)(0x424C1310UL)) +#define bFM_QPRC2_QCR_CGSC *((volatile uint8_t *)(0x424C1314UL)) +#define bFM4_QPRC2_QCR_CGSC *((volatile uint8_t *)(0x424C1314UL)) +#define bFM_QPRC2_QCR_RSEL *((volatile uint8_t *)(0x424C1318UL)) +#define bFM4_QPRC2_QCR_RSEL *((volatile uint8_t *)(0x424C1318UL)) +#define bFM_QPRC2_QCR_SWAP *((volatile uint8_t *)(0x424C131CUL)) +#define bFM4_QPRC2_QCR_SWAP *((volatile uint8_t *)(0x424C131CUL)) + +#define bFM_QPRC2_QECR_ORNGMD *((volatile uint8_t *)(0x424C1380UL)) +#define bFM4_QPRC2_QECR_ORNGMD *((volatile uint8_t *)(0x424C1380UL)) +#define bFM_QPRC2_QECR_ORNGF *((volatile uint8_t *)(0x424C1384UL)) +#define bFM4_QPRC2_QECR_ORNGF *((volatile uint8_t *)(0x424C1384UL)) +#define bFM_QPRC2_QECR_ORNGIE *((volatile uint8_t *)(0x424C1388UL)) +#define bFM4_QPRC2_QECR_ORNGIE *((volatile uint8_t *)(0x424C1388UL)) +#define bFM_QPRC2_QECR_PEC *((volatile uint8_t *)(0x424C138CUL)) +#define bFM4_QPRC2_QECR_PEC *((volatile uint8_t *)(0x424C138CUL)) + +#define bFM_QPRC2_QICRH_CDCIE *((volatile uint8_t *)(0x424C12A0UL)) +#define bFM4_QPRC2_QICRH_CDCIE *((volatile uint8_t *)(0x424C12A0UL)) +#define bFM_QPRC2_QICRH_CDCF *((volatile uint8_t *)(0x424C12A4UL)) +#define bFM4_QPRC2_QICRH_CDCF *((volatile uint8_t *)(0x424C12A4UL)) +#define bFM_QPRC2_QICRH_DIRPC *((volatile uint8_t *)(0x424C12A8UL)) +#define bFM4_QPRC2_QICRH_DIRPC *((volatile uint8_t *)(0x424C12A8UL)) +#define bFM_QPRC2_QICRH_DIROU *((volatile uint8_t *)(0x424C12ACUL)) +#define bFM4_QPRC2_QICRH_DIROU *((volatile uint8_t *)(0x424C12ACUL)) +#define bFM_QPRC2_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C12B0UL)) +#define bFM4_QPRC2_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C12B0UL)) +#define bFM_QPRC2_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C12B4UL)) +#define bFM4_QPRC2_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C12B4UL)) + +#define bFM_QPRC2_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1280UL)) +#define bFM4_QPRC2_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1280UL)) +#define bFM_QPRC2_QICRL_QPCMF *((volatile uint8_t *)(0x424C1284UL)) +#define bFM4_QPRC2_QICRL_QPCMF *((volatile uint8_t *)(0x424C1284UL)) +#define bFM_QPRC2_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1288UL)) +#define bFM4_QPRC2_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1288UL)) +#define bFM_QPRC2_QICRL_QPRCMF *((volatile uint8_t *)(0x424C128CUL)) +#define bFM4_QPRC2_QICRL_QPRCMF *((volatile uint8_t *)(0x424C128CUL)) +#define bFM_QPRC2_QICRL_OUZIE *((volatile uint8_t *)(0x424C1290UL)) +#define bFM4_QPRC2_QICRL_OUZIE *((volatile uint8_t *)(0x424C1290UL)) +#define bFM_QPRC2_QICRL_UFDF *((volatile uint8_t *)(0x424C1294UL)) +#define bFM4_QPRC2_QICRL_UFDF *((volatile uint8_t *)(0x424C1294UL)) +#define bFM_QPRC2_QICRL_OFDF *((volatile uint8_t *)(0x424C1298UL)) +#define bFM4_QPRC2_QICRL_OFDF *((volatile uint8_t *)(0x424C1298UL)) +#define bFM_QPRC2_QICRL_ZIIF *((volatile uint8_t *)(0x424C129CUL)) +#define bFM4_QPRC2_QICRL_ZIIF *((volatile uint8_t *)(0x424C129CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC2_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC2_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2410UL)) +#define bFM4_QPRC2_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2410UL)) +#define bFM_QPRC2_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2414UL)) +#define bFM4_QPRC2_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2414UL)) + +#define bFM_QPRC2_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2490UL)) +#define bFM4_QPRC2_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2490UL)) +#define bFM_QPRC2_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2494UL)) +#define bFM4_QPRC2_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2494UL)) + +#define bFM_QPRC2_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2510UL)) +#define bFM4_QPRC2_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2510UL)) +#define bFM_QPRC2_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2514UL)) +#define bFM4_QPRC2_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2514UL)) + + +/******************************************************************************* +* QPRC Registers QPRC3 +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC3_QCR_PSTP *((volatile uint8_t *)(0x424C1B10UL)) +#define bFM4_QPRC3_QCR_PSTP *((volatile uint8_t *)(0x424C1B10UL)) +#define bFM_QPRC3_QCR_CGSC *((volatile uint8_t *)(0x424C1B14UL)) +#define bFM4_QPRC3_QCR_CGSC *((volatile uint8_t *)(0x424C1B14UL)) +#define bFM_QPRC3_QCR_RSEL *((volatile uint8_t *)(0x424C1B18UL)) +#define bFM4_QPRC3_QCR_RSEL *((volatile uint8_t *)(0x424C1B18UL)) +#define bFM_QPRC3_QCR_SWAP *((volatile uint8_t *)(0x424C1B1CUL)) +#define bFM4_QPRC3_QCR_SWAP *((volatile uint8_t *)(0x424C1B1CUL)) + +#define bFM_QPRC3_QECR_ORNGMD *((volatile uint8_t *)(0x424C1B80UL)) +#define bFM4_QPRC3_QECR_ORNGMD *((volatile uint8_t *)(0x424C1B80UL)) +#define bFM_QPRC3_QECR_ORNGF *((volatile uint8_t *)(0x424C1B84UL)) +#define bFM4_QPRC3_QECR_ORNGF *((volatile uint8_t *)(0x424C1B84UL)) +#define bFM_QPRC3_QECR_ORNGIE *((volatile uint8_t *)(0x424C1B88UL)) +#define bFM4_QPRC3_QECR_ORNGIE *((volatile uint8_t *)(0x424C1B88UL)) +#define bFM_QPRC3_QECR_PEC *((volatile uint8_t *)(0x424C1B8CUL)) +#define bFM4_QPRC3_QECR_PEC *((volatile uint8_t *)(0x424C1B8CUL)) + +#define bFM_QPRC3_QICRH_CDCIE *((volatile uint8_t *)(0x424C1AA0UL)) +#define bFM4_QPRC3_QICRH_CDCIE *((volatile uint8_t *)(0x424C1AA0UL)) +#define bFM_QPRC3_QICRH_CDCF *((volatile uint8_t *)(0x424C1AA4UL)) +#define bFM4_QPRC3_QICRH_CDCF *((volatile uint8_t *)(0x424C1AA4UL)) +#define bFM_QPRC3_QICRH_DIRPC *((volatile uint8_t *)(0x424C1AA8UL)) +#define bFM4_QPRC3_QICRH_DIRPC *((volatile uint8_t *)(0x424C1AA8UL)) +#define bFM_QPRC3_QICRH_DIROU *((volatile uint8_t *)(0x424C1AACUL)) +#define bFM4_QPRC3_QICRH_DIROU *((volatile uint8_t *)(0x424C1AACUL)) +#define bFM_QPRC3_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C1AB0UL)) +#define bFM4_QPRC3_QICRH_QPCNRCMIE *((volatile uint8_t *)(0x424C1AB0UL)) +#define bFM_QPRC3_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C1AB4UL)) +#define bFM4_QPRC3_QICRH_QPCNRCMF *((volatile uint8_t *)(0x424C1AB4UL)) + +#define bFM_QPRC3_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1A80UL)) +#define bFM4_QPRC3_QICRL_QPCMIE *((volatile uint8_t *)(0x424C1A80UL)) +#define bFM_QPRC3_QICRL_QPCMF *((volatile uint8_t *)(0x424C1A84UL)) +#define bFM4_QPRC3_QICRL_QPCMF *((volatile uint8_t *)(0x424C1A84UL)) +#define bFM_QPRC3_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1A88UL)) +#define bFM4_QPRC3_QICRL_QPRCMIE *((volatile uint8_t *)(0x424C1A88UL)) +#define bFM_QPRC3_QICRL_QPRCMF *((volatile uint8_t *)(0x424C1A8CUL)) +#define bFM4_QPRC3_QICRL_QPRCMF *((volatile uint8_t *)(0x424C1A8CUL)) +#define bFM_QPRC3_QICRL_OUZIE *((volatile uint8_t *)(0x424C1A90UL)) +#define bFM4_QPRC3_QICRL_OUZIE *((volatile uint8_t *)(0x424C1A90UL)) +#define bFM_QPRC3_QICRL_UFDF *((volatile uint8_t *)(0x424C1A94UL)) +#define bFM4_QPRC3_QICRL_UFDF *((volatile uint8_t *)(0x424C1A94UL)) +#define bFM_QPRC3_QICRL_OFDF *((volatile uint8_t *)(0x424C1A98UL)) +#define bFM4_QPRC3_QICRL_OFDF *((volatile uint8_t *)(0x424C1A98UL)) +#define bFM_QPRC3_QICRL_ZIIF *((volatile uint8_t *)(0x424C1A9CUL)) +#define bFM4_QPRC3_QICRL_ZIIF *((volatile uint8_t *)(0x424C1A9CUL)) + + +/******************************************************************************* +* QPRC_NF Registers QPRC3_NF +* Bitband Section +*******************************************************************************/ +#define bFM_QPRC3_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2610UL)) +#define bFM4_QPRC3_NF_NFCTLA_AINLV *((volatile uint8_t *)(0x424C2610UL)) +#define bFM_QPRC3_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2614UL)) +#define bFM4_QPRC3_NF_NFCTLA_AINMD *((volatile uint8_t *)(0x424C2614UL)) + +#define bFM_QPRC3_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2690UL)) +#define bFM4_QPRC3_NF_NFCTLB_BINLV *((volatile uint8_t *)(0x424C2690UL)) +#define bFM_QPRC3_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2694UL)) +#define bFM4_QPRC3_NF_NFCTLB_BINMD *((volatile uint8_t *)(0x424C2694UL)) + +#define bFM_QPRC3_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2710UL)) +#define bFM4_QPRC3_NF_NFCTLZ_ZINLV *((volatile uint8_t *)(0x424C2710UL)) +#define bFM_QPRC3_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2714UL)) +#define bFM4_QPRC3_NF_NFCTLZ_ZINMD *((volatile uint8_t *)(0x424C2714UL)) + + +/******************************************************************************* +* RTC Registers RTC +* Bitband Section +*******************************************************************************/ +#define bFM_RTC_ALMOR_TAMO *((volatile uint8_t *)(0x42762890UL)) +#define bFM4_RTC_ALMOR_TAMO *((volatile uint8_t *)(0x42762890UL)) + +#define bFM_RTC_EWKUP_WUP0 *((volatile uint8_t *)(0x42763180UL)) +#define bFM4_RTC_EWKUP_WUP0 *((volatile uint8_t *)(0x42763180UL)) + +#define bFM_RTC_HIBRST_HIBRST *((volatile uint8_t *)(0x42763300UL)) +#define bFM4_RTC_HIBRST_HIBRST *((volatile uint8_t *)(0x42763300UL)) + +#define bFM_RTC_VBDDR_VDDR0 *((volatile uint8_t *)(0x42763480UL)) +#define bFM4_RTC_VBDDR_VDDR0 *((volatile uint8_t *)(0x42763480UL)) +#define bFM_RTC_VBDDR_VDDR1 *((volatile uint8_t *)(0x42763484UL)) +#define bFM4_RTC_VBDDR_VDDR1 *((volatile uint8_t *)(0x42763484UL)) +#define bFM_RTC_VBDDR_VDDR2 *((volatile uint8_t *)(0x42763488UL)) +#define bFM4_RTC_VBDDR_VDDR2 *((volatile uint8_t *)(0x42763488UL)) +#define bFM_RTC_VBDDR_VDDR3 *((volatile uint8_t *)(0x4276348CUL)) +#define bFM4_RTC_VBDDR_VDDR3 *((volatile uint8_t *)(0x4276348CUL)) + +#define bFM_RTC_VBDIR_VDIR0 *((volatile uint8_t *)(0x42763500UL)) +#define bFM4_RTC_VBDIR_VDIR0 *((volatile uint8_t *)(0x42763500UL)) +#define bFM_RTC_VBDIR_VDIR1 *((volatile uint8_t *)(0x42763504UL)) +#define bFM4_RTC_VBDIR_VDIR1 *((volatile uint8_t *)(0x42763504UL)) +#define bFM_RTC_VBDIR_VDIR2 *((volatile uint8_t *)(0x42763508UL)) +#define bFM4_RTC_VBDIR_VDIR2 *((volatile uint8_t *)(0x42763508UL)) +#define bFM_RTC_VBDIR_VDIR3 *((volatile uint8_t *)(0x4276350CUL)) +#define bFM4_RTC_VBDIR_VDIR3 *((volatile uint8_t *)(0x4276350CUL)) + +#define bFM_RTC_VBDOR_VDOR0 *((volatile uint8_t *)(0x42763580UL)) +#define bFM4_RTC_VBDOR_VDOR0 *((volatile uint8_t *)(0x42763580UL)) +#define bFM_RTC_VBDOR_VDOR1 *((volatile uint8_t *)(0x42763584UL)) +#define bFM4_RTC_VBDOR_VDOR1 *((volatile uint8_t *)(0x42763584UL)) +#define bFM_RTC_VBDOR_VDOR2 *((volatile uint8_t *)(0x42763588UL)) +#define bFM4_RTC_VBDOR_VDOR2 *((volatile uint8_t *)(0x42763588UL)) +#define bFM_RTC_VBDOR_VDOR3 *((volatile uint8_t *)(0x4276358CUL)) +#define bFM4_RTC_VBDOR_VDOR3 *((volatile uint8_t *)(0x4276358CUL)) + +#define bFM_RTC_VBPCR_VPCR0 *((volatile uint8_t *)(0x42763400UL)) +#define bFM4_RTC_VBPCR_VPCR0 *((volatile uint8_t *)(0x42763400UL)) +#define bFM_RTC_VBPCR_VPCR1 *((volatile uint8_t *)(0x42763404UL)) +#define bFM4_RTC_VBPCR_VPCR1 *((volatile uint8_t *)(0x42763404UL)) +#define bFM_RTC_VBPCR_VPCR2 *((volatile uint8_t *)(0x42763408UL)) +#define bFM4_RTC_VBPCR_VPCR2 *((volatile uint8_t *)(0x42763408UL)) +#define bFM_RTC_VBPCR_VPCR3 *((volatile uint8_t *)(0x4276340CUL)) +#define bFM4_RTC_VBPCR_VPCR3 *((volatile uint8_t *)(0x4276340CUL)) + +#define bFM_RTC_VBPFR_VPFR0 *((volatile uint8_t *)(0x42763380UL)) +#define bFM4_RTC_VBPFR_VPFR0 *((volatile uint8_t *)(0x42763380UL)) +#define bFM_RTC_VBPFR_VPFR1 *((volatile uint8_t *)(0x42763384UL)) +#define bFM4_RTC_VBPFR_VPFR1 *((volatile uint8_t *)(0x42763384UL)) +#define bFM_RTC_VBPFR_VPFR2 *((volatile uint8_t *)(0x42763388UL)) +#define bFM4_RTC_VBPFR_VPFR2 *((volatile uint8_t *)(0x42763388UL)) +#define bFM_RTC_VBPFR_VPFR3 *((volatile uint8_t *)(0x4276338CUL)) +#define bFM4_RTC_VBPFR_VPFR3 *((volatile uint8_t *)(0x4276338CUL)) + +#define bFM_RTC_VBPZR_VPZR0 *((volatile uint8_t *)(0x42763600UL)) +#define bFM4_RTC_VBPZR_VPZR0 *((volatile uint8_t *)(0x42763600UL)) +#define bFM_RTC_VBPZR_VPZR1 *((volatile uint8_t *)(0x42763604UL)) +#define bFM4_RTC_VBPZR_VPZR1 *((volatile uint8_t *)(0x42763604UL)) + +#define bFM_RTC_VDET_PON *((volatile uint8_t *)(0x4276321CUL)) +#define bFM4_RTC_VDET_PON *((volatile uint8_t *)(0x4276321CUL)) + +#define bFM_RTC_WTCALEN_WTCALEN *((volatile uint8_t *)(0x42762C00UL)) +#define bFM4_RTC_WTCALEN_WTCALEN *((volatile uint8_t *)(0x42762C00UL)) + +#define bFM_RTC_WTCOSEL_WTCOSEL *((volatile uint8_t *)(0x42762E00UL)) +#define bFM4_RTC_WTCOSEL_WTCOSEL *((volatile uint8_t *)(0x42762E00UL)) + +#define bFM_RTC_WTCR10_ST *((volatile uint8_t *)(0x42762000UL)) +#define bFM4_RTC_WTCR10_ST *((volatile uint8_t *)(0x42762000UL)) +#define bFM_RTC_WTCR10_RUN *((volatile uint8_t *)(0x42762008UL)) +#define bFM4_RTC_WTCR10_RUN *((volatile uint8_t *)(0x42762008UL)) +#define bFM_RTC_WTCR10_SRST *((volatile uint8_t *)(0x4276200CUL)) +#define bFM4_RTC_WTCR10_SRST *((volatile uint8_t *)(0x4276200CUL)) +#define bFM_RTC_WTCR10_SCST *((volatile uint8_t *)(0x42762010UL)) +#define bFM4_RTC_WTCR10_SCST *((volatile uint8_t *)(0x42762010UL)) +#define bFM_RTC_WTCR10_SCRST *((volatile uint8_t *)(0x42762014UL)) +#define bFM4_RTC_WTCR10_SCRST *((volatile uint8_t *)(0x42762014UL)) +#define bFM_RTC_WTCR10_BUSY *((volatile uint8_t *)(0x42762018UL)) +#define bFM4_RTC_WTCR10_BUSY *((volatile uint8_t *)(0x42762018UL)) +#define bFM_RTC_WTCR10_TRANS *((volatile uint8_t *)(0x4276201CUL)) +#define bFM4_RTC_WTCR10_TRANS *((volatile uint8_t *)(0x4276201CUL)) + +#define bFM_RTC_WTCR11_MIEN *((volatile uint8_t *)(0x42762080UL)) +#define bFM4_RTC_WTCR11_MIEN *((volatile uint8_t *)(0x42762080UL)) +#define bFM_RTC_WTCR11_HEN *((volatile uint8_t *)(0x42762084UL)) +#define bFM4_RTC_WTCR11_HEN *((volatile uint8_t *)(0x42762084UL)) +#define bFM_RTC_WTCR11_DEN *((volatile uint8_t *)(0x42762088UL)) +#define bFM4_RTC_WTCR11_DEN *((volatile uint8_t *)(0x42762088UL)) +#define bFM_RTC_WTCR11_MOEN *((volatile uint8_t *)(0x4276208CUL)) +#define bFM4_RTC_WTCR11_MOEN *((volatile uint8_t *)(0x4276208CUL)) +#define bFM_RTC_WTCR11_YEN *((volatile uint8_t *)(0x42762090UL)) +#define bFM4_RTC_WTCR11_YEN *((volatile uint8_t *)(0x42762090UL)) + +#define bFM_RTC_WTCR12_INTSSI *((volatile uint8_t *)(0x42762100UL)) +#define bFM4_RTC_WTCR12_INTSSI *((volatile uint8_t *)(0x42762100UL)) +#define bFM_RTC_WTCR12_INTSI *((volatile uint8_t *)(0x42762104UL)) +#define bFM4_RTC_WTCR12_INTSI *((volatile uint8_t *)(0x42762104UL)) +#define bFM_RTC_WTCR12_INTMI *((volatile uint8_t *)(0x42762108UL)) +#define bFM4_RTC_WTCR12_INTMI *((volatile uint8_t *)(0x42762108UL)) +#define bFM_RTC_WTCR12_INTHI *((volatile uint8_t *)(0x4276210CUL)) +#define bFM4_RTC_WTCR12_INTHI *((volatile uint8_t *)(0x4276210CUL)) +#define bFM_RTC_WTCR12_INTTMI *((volatile uint8_t *)(0x42762110UL)) +#define bFM4_RTC_WTCR12_INTTMI *((volatile uint8_t *)(0x42762110UL)) +#define bFM_RTC_WTCR12_INTALI *((volatile uint8_t *)(0x42762114UL)) +#define bFM4_RTC_WTCR12_INTALI *((volatile uint8_t *)(0x42762114UL)) +#define bFM_RTC_WTCR12_INTERI *((volatile uint8_t *)(0x42762118UL)) +#define bFM4_RTC_WTCR12_INTERI *((volatile uint8_t *)(0x42762118UL)) +#define bFM_RTC_WTCR12_INTCRI *((volatile uint8_t *)(0x4276211CUL)) +#define bFM4_RTC_WTCR12_INTCRI *((volatile uint8_t *)(0x4276211CUL)) + +#define bFM_RTC_WTCR13_INTSSIE *((volatile uint8_t *)(0x42762180UL)) +#define bFM4_RTC_WTCR13_INTSSIE *((volatile uint8_t *)(0x42762180UL)) +#define bFM_RTC_WTCR13_INTSIE *((volatile uint8_t *)(0x42762184UL)) +#define bFM4_RTC_WTCR13_INTSIE *((volatile uint8_t *)(0x42762184UL)) +#define bFM_RTC_WTCR13_INTMIE *((volatile uint8_t *)(0x42762188UL)) +#define bFM4_RTC_WTCR13_INTMIE *((volatile uint8_t *)(0x42762188UL)) +#define bFM_RTC_WTCR13_INTHIE *((volatile uint8_t *)(0x4276218CUL)) +#define bFM4_RTC_WTCR13_INTHIE *((volatile uint8_t *)(0x4276218CUL)) +#define bFM_RTC_WTCR13_INTTMIE *((volatile uint8_t *)(0x42762190UL)) +#define bFM4_RTC_WTCR13_INTTMIE *((volatile uint8_t *)(0x42762190UL)) +#define bFM_RTC_WTCR13_INTALIE *((volatile uint8_t *)(0x42762194UL)) +#define bFM4_RTC_WTCR13_INTALIE *((volatile uint8_t *)(0x42762194UL)) +#define bFM_RTC_WTCR13_INTERIE *((volatile uint8_t *)(0x42762198UL)) +#define bFM4_RTC_WTCR13_INTERIE *((volatile uint8_t *)(0x42762198UL)) +#define bFM_RTC_WTCR13_INTCRIE *((volatile uint8_t *)(0x4276219CUL)) +#define bFM4_RTC_WTCR13_INTCRIE *((volatile uint8_t *)(0x4276219CUL)) + +#define bFM_RTC_WTCR20_CREAD *((volatile uint8_t *)(0x42762200UL)) +#define bFM4_RTC_WTCR20_CREAD *((volatile uint8_t *)(0x42762200UL)) +#define bFM_RTC_WTCR20_CWRITE *((volatile uint8_t *)(0x42762204UL)) +#define bFM4_RTC_WTCR20_CWRITE *((volatile uint8_t *)(0x42762204UL)) +#define bFM_RTC_WTCR20_BREAD *((volatile uint8_t *)(0x42762208UL)) +#define bFM4_RTC_WTCR20_BREAD *((volatile uint8_t *)(0x42762208UL)) +#define bFM_RTC_WTCR20_BWRITE *((volatile uint8_t *)(0x4276220CUL)) +#define bFM4_RTC_WTCR20_BWRITE *((volatile uint8_t *)(0x4276220CUL)) +#define bFM_RTC_WTCR20_PREAD *((volatile uint8_t *)(0x42762210UL)) +#define bFM4_RTC_WTCR20_PREAD *((volatile uint8_t *)(0x42762210UL)) +#define bFM_RTC_WTCR20_PWRITE *((volatile uint8_t *)(0x42762214UL)) +#define bFM4_RTC_WTCR20_PWRITE *((volatile uint8_t *)(0x42762214UL)) + +#define bFM_RTC_WTCR21_TMST *((volatile uint8_t *)(0x42762280UL)) +#define bFM4_RTC_WTCR21_TMST *((volatile uint8_t *)(0x42762280UL)) +#define bFM_RTC_WTCR21_TMEN *((volatile uint8_t *)(0x42762284UL)) +#define bFM4_RTC_WTCR21_TMEN *((volatile uint8_t *)(0x42762284UL)) +#define bFM_RTC_WTCR21_TMRUN *((volatile uint8_t *)(0x42762288UL)) +#define bFM4_RTC_WTCR21_TMRUN *((volatile uint8_t *)(0x42762288UL)) + +#define bFM_RTC_WTDIVEN_WTDIVEN *((volatile uint8_t *)(0x42762D00UL)) +#define bFM4_RTC_WTDIVEN_WTDIVEN *((volatile uint8_t *)(0x42762D00UL)) +#define bFM_RTC_WTDIVEN_WTDIVRDY *((volatile uint8_t *)(0x42762D04UL)) +#define bFM4_RTC_WTDIVEN_WTDIVRDY *((volatile uint8_t *)(0x42762D04UL)) + +#define bFM_RTC_WTMOR_TMO *((volatile uint8_t *)(0x42762610UL)) +#define bFM4_RTC_WTMOR_TMO *((volatile uint8_t *)(0x42762610UL)) + +#define bFM_RTC_WTOSCCNT_SOSCEX *((volatile uint8_t *)(0x42762F00UL)) +#define bFM4_RTC_WTOSCCNT_SOSCEX *((volatile uint8_t *)(0x42762F00UL)) +#define bFM_RTC_WTOSCCNT_SOSCNTL *((volatile uint8_t *)(0x42762F04UL)) +#define bFM4_RTC_WTOSCCNT_SOSCNTL *((volatile uint8_t *)(0x42762F04UL)) + + +/******************************************************************************* +* SBSSR Registers SBSSR +* Bitband Section +*******************************************************************************/ +#define bFM_SBSSR_BTSSSR_SSSR0 *((volatile uint8_t *)(0x424BFF80UL)) +#define bFM4_SBSSR_BTSSSR_SSSR0 *((volatile uint8_t *)(0x424BFF80UL)) +#define bFM_SBSSR_BTSSSR_SSSR1 *((volatile uint8_t *)(0x424BFF84UL)) +#define bFM4_SBSSR_BTSSSR_SSSR1 *((volatile uint8_t *)(0x424BFF84UL)) +#define bFM_SBSSR_BTSSSR_SSSR2 *((volatile uint8_t *)(0x424BFF88UL)) +#define bFM4_SBSSR_BTSSSR_SSSR2 *((volatile uint8_t *)(0x424BFF88UL)) +#define bFM_SBSSR_BTSSSR_SSSR3 *((volatile uint8_t *)(0x424BFF8CUL)) +#define bFM4_SBSSR_BTSSSR_SSSR3 *((volatile uint8_t *)(0x424BFF8CUL)) +#define bFM_SBSSR_BTSSSR_SSSR4 *((volatile uint8_t *)(0x424BFF90UL)) +#define bFM4_SBSSR_BTSSSR_SSSR4 *((volatile uint8_t *)(0x424BFF90UL)) +#define bFM_SBSSR_BTSSSR_SSSR5 *((volatile uint8_t *)(0x424BFF94UL)) +#define bFM4_SBSSR_BTSSSR_SSSR5 *((volatile uint8_t *)(0x424BFF94UL)) +#define bFM_SBSSR_BTSSSR_SSSR6 *((volatile uint8_t *)(0x424BFF98UL)) +#define bFM4_SBSSR_BTSSSR_SSSR6 *((volatile uint8_t *)(0x424BFF98UL)) +#define bFM_SBSSR_BTSSSR_SSSR7 *((volatile uint8_t *)(0x424BFF9CUL)) +#define bFM4_SBSSR_BTSSSR_SSSR7 *((volatile uint8_t *)(0x424BFF9CUL)) +#define bFM_SBSSR_BTSSSR_SSSR8 *((volatile uint8_t *)(0x424BFFA0UL)) +#define bFM4_SBSSR_BTSSSR_SSSR8 *((volatile uint8_t *)(0x424BFFA0UL)) +#define bFM_SBSSR_BTSSSR_SSSR9 *((volatile uint8_t *)(0x424BFFA4UL)) +#define bFM4_SBSSR_BTSSSR_SSSR9 *((volatile uint8_t *)(0x424BFFA4UL)) +#define bFM_SBSSR_BTSSSR_SSSR10 *((volatile uint8_t *)(0x424BFFA8UL)) +#define bFM4_SBSSR_BTSSSR_SSSR10 *((volatile uint8_t *)(0x424BFFA8UL)) +#define bFM_SBSSR_BTSSSR_SSSR11 *((volatile uint8_t *)(0x424BFFACUL)) +#define bFM4_SBSSR_BTSSSR_SSSR11 *((volatile uint8_t *)(0x424BFFACUL)) +#define bFM_SBSSR_BTSSSR_SSSR12 *((volatile uint8_t *)(0x424BFFB0UL)) +#define bFM4_SBSSR_BTSSSR_SSSR12 *((volatile uint8_t *)(0x424BFFB0UL)) +#define bFM_SBSSR_BTSSSR_SSSR13 *((volatile uint8_t *)(0x424BFFB4UL)) +#define bFM4_SBSSR_BTSSSR_SSSR13 *((volatile uint8_t *)(0x424BFFB4UL)) +#define bFM_SBSSR_BTSSSR_SSSR14 *((volatile uint8_t *)(0x424BFFB8UL)) +#define bFM4_SBSSR_BTSSSR_SSSR14 *((volatile uint8_t *)(0x424BFFB8UL)) +#define bFM_SBSSR_BTSSSR_SSSR15 *((volatile uint8_t *)(0x424BFFBCUL)) +#define bFM4_SBSSR_BTSSSR_SSSR15 *((volatile uint8_t *)(0x424BFFBCUL)) + + +/******************************************************************************* +* SDIF Registers SDIF +* Bitband Section +*******************************************************************************/ +#define bFM_SDIF_ADMAEST_ADMALENME *((volatile uint8_t *)(0x42DC0A88UL)) +#define bFM4_SDIF_ADMAEST_ADMALENME *((volatile uint8_t *)(0x42DC0A88UL)) + +#define bFM_SDIF_AHBCFGL_SINEN *((volatile uint8_t *)(0x42DC200CUL)) +#define bFM4_SDIF_AHBCFGL_SINEN *((volatile uint8_t *)(0x42DC200CUL)) +#define bFM_SDIF_AHBCFGL_BSLOCK *((volatile uint8_t *)(0x42DC2010UL)) +#define bFM4_SDIF_AHBCFGL_BSLOCK *((volatile uint8_t *)(0x42DC2010UL)) +#define bFM_SDIF_AHBCFGL_BSLOCKSEL *((volatile uint8_t *)(0x42DC2014UL)) +#define bFM4_SDIF_AHBCFGL_BSLOCKSEL *((volatile uint8_t *)(0x42DC2014UL)) +#define bFM_SDIF_AHBCFGL_ENDIANSEL *((volatile uint8_t *)(0x42DC2018UL)) +#define bFM4_SDIF_AHBCFGL_ENDIANSEL *((volatile uint8_t *)(0x42DC2018UL)) + +#define bFM_SDIF_CAPBLTY0_TOCLKUNIT *((volatile uint8_t *)(0x42DC081CUL)) +#define bFM4_SDIF_CAPBLTY0_TOCLKUNIT *((volatile uint8_t *)(0x42DC081CUL)) + +#define bFM_SDIF_CAPBLTY1_EMBD8BIT *((volatile uint8_t *)(0x42DC0848UL)) +#define bFM4_SDIF_CAPBLTY1_EMBD8BIT *((volatile uint8_t *)(0x42DC0848UL)) +#define bFM_SDIF_CAPBLTY1_ADMA2SPT *((volatile uint8_t *)(0x42DC084CUL)) +#define bFM4_SDIF_CAPBLTY1_ADMA2SPT *((volatile uint8_t *)(0x42DC084CUL)) +#define bFM_SDIF_CAPBLTY1_HGHSPDSPT *((volatile uint8_t *)(0x42DC0854UL)) +#define bFM4_SDIF_CAPBLTY1_HGHSPDSPT *((volatile uint8_t *)(0x42DC0854UL)) +#define bFM_SDIF_CAPBLTY1_SDMASPT *((volatile uint8_t *)(0x42DC0858UL)) +#define bFM4_SDIF_CAPBLTY1_SDMASPT *((volatile uint8_t *)(0x42DC0858UL)) +#define bFM_SDIF_CAPBLTY1_LWPWRSPT *((volatile uint8_t *)(0x42DC085CUL)) +#define bFM4_SDIF_CAPBLTY1_LWPWRSPT *((volatile uint8_t *)(0x42DC085CUL)) +#define bFM_SDIF_CAPBLTY1_V33SPT *((volatile uint8_t *)(0x42DC0860UL)) +#define bFM4_SDIF_CAPBLTY1_V33SPT *((volatile uint8_t *)(0x42DC0860UL)) +#define bFM_SDIF_CAPBLTY1_V30SPT *((volatile uint8_t *)(0x42DC0864UL)) +#define bFM4_SDIF_CAPBLTY1_V30SPT *((volatile uint8_t *)(0x42DC0864UL)) +#define bFM_SDIF_CAPBLTY1_V18SPT *((volatile uint8_t *)(0x42DC0868UL)) +#define bFM4_SDIF_CAPBLTY1_V18SPT *((volatile uint8_t *)(0x42DC0868UL)) +#define bFM_SDIF_CAPBLTY1_BUS64SPT *((volatile uint8_t *)(0x42DC0870UL)) +#define bFM4_SDIF_CAPBLTY1_BUS64SPT *((volatile uint8_t *)(0x42DC0870UL)) +#define bFM_SDIF_CAPBLTY1_ASYINTSPT *((volatile uint8_t *)(0x42DC0874UL)) +#define bFM4_SDIF_CAPBLTY1_ASYINTSPT *((volatile uint8_t *)(0x42DC0874UL)) + +#define bFM_SDIF_CAPBLTY2_SDR50SPT *((volatile uint8_t *)(0x42DC0880UL)) +#define bFM4_SDIF_CAPBLTY2_SDR50SPT *((volatile uint8_t *)(0x42DC0880UL)) +#define bFM_SDIF_CAPBLTY2_SDR104SPT *((volatile uint8_t *)(0x42DC0884UL)) +#define bFM4_SDIF_CAPBLTY2_SDR104SPT *((volatile uint8_t *)(0x42DC0884UL)) +#define bFM_SDIF_CAPBLTY2_DDR50SPT *((volatile uint8_t *)(0x42DC0888UL)) +#define bFM4_SDIF_CAPBLTY2_DDR50SPT *((volatile uint8_t *)(0x42DC0888UL)) +#define bFM_SDIF_CAPBLTY2_DRVTPASPT *((volatile uint8_t *)(0x42DC0890UL)) +#define bFM4_SDIF_CAPBLTY2_DRVTPASPT *((volatile uint8_t *)(0x42DC0890UL)) +#define bFM_SDIF_CAPBLTY2_DRVTPCSPT *((volatile uint8_t *)(0x42DC0894UL)) +#define bFM4_SDIF_CAPBLTY2_DRVTPCSPT *((volatile uint8_t *)(0x42DC0894UL)) +#define bFM_SDIF_CAPBLTY2_DRVTPDSPT *((volatile uint8_t *)(0x42DC0898UL)) +#define bFM4_SDIF_CAPBLTY2_DRVTPDSPT *((volatile uint8_t *)(0x42DC0898UL)) +#define bFM_SDIF_CAPBLTY2_USETNSDR50 *((volatile uint8_t *)(0x42DC08B4UL)) +#define bFM4_SDIF_CAPBLTY2_USETNSDR50 *((volatile uint8_t *)(0x42DC08B4UL)) + +#define bFM_SDIF_FEACEST_FEVNT12ND *((volatile uint8_t *)(0x42DC0A00UL)) +#define bFM4_SDIF_FEACEST_FEVNT12ND *((volatile uint8_t *)(0x42DC0A00UL)) +#define bFM_SDIF_FEACEST_FEVNTTO *((volatile uint8_t *)(0x42DC0A04UL)) +#define bFM4_SDIF_FEACEST_FEVNTTO *((volatile uint8_t *)(0x42DC0A04UL)) +#define bFM_SDIF_FEACEST_FEVNTCRC *((volatile uint8_t *)(0x42DC0A08UL)) +#define bFM4_SDIF_FEACEST_FEVNTCRC *((volatile uint8_t *)(0x42DC0A08UL)) +#define bFM_SDIF_FEACEST_FEVNTEB *((volatile uint8_t *)(0x42DC0A0CUL)) +#define bFM4_SDIF_FEACEST_FEVNTEB *((volatile uint8_t *)(0x42DC0A0CUL)) +#define bFM_SDIF_FEACEST_FEVNTIDX *((volatile uint8_t *)(0x42DC0A10UL)) +#define bFM4_SDIF_FEACEST_FEVNTIDX *((volatile uint8_t *)(0x42DC0A10UL)) +#define bFM_SDIF_FEACEST_FEVNTCMD12 *((volatile uint8_t *)(0x42DC0A1CUL)) +#define bFM4_SDIF_FEACEST_FEVNTCMD12 *((volatile uint8_t *)(0x42DC0A1CUL)) + +#define bFM_SDIF_MCWIRQC0_WTIRQEN *((volatile uint8_t *)(0x42DC2500UL)) +#define bFM4_SDIF_MCWIRQC0_WTIRQEN *((volatile uint8_t *)(0x42DC2500UL)) +#define bFM_SDIF_MCWIRQC0_WTIRQST *((volatile uint8_t *)(0x42DC2504UL)) +#define bFM4_SDIF_MCWIRQC0_WTIRQST *((volatile uint8_t *)(0x42DC2504UL)) + +#define bFM_SDIF_MMCSDCH_BTACKENMMC *((volatile uint8_t *)(0x42DC24C0UL)) +#define bFM4_SDIF_MMCSDCH_BTACKENMMC *((volatile uint8_t *)(0x42DC24C0UL)) +#define bFM_SDIF_MMCSDCH_BTABTENMMC *((volatile uint8_t *)(0x42DC24C4UL)) +#define bFM4_SDIF_MMCSDCH_BTABTENMMC *((volatile uint8_t *)(0x42DC24C4UL)) +#define bFM_SDIF_MMCSDCH_BTMDENMMC *((volatile uint8_t *)(0x42DC24C8UL)) +#define bFM4_SDIF_MMCSDCH_BTMDENMMC *((volatile uint8_t *)(0x42DC24C8UL)) + +#define bFM_SDIF_MMCSDCL_LCKRSTESD *((volatile uint8_t *)(0x42DC2480UL)) +#define bFM4_SDIF_MMCSDCL_LCKRSTESD *((volatile uint8_t *)(0x42DC2480UL)) +#define bFM_SDIF_MMCSDCL_RSTMMC *((volatile uint8_t *)(0x42DC2484UL)) +#define bFM4_SDIF_MMCSDCL_RSTMMC *((volatile uint8_t *)(0x42DC2484UL)) +#define bFM_SDIF_MMCSDCL_VCCCTLMMC *((volatile uint8_t *)(0x42DC2488UL)) +#define bFM4_SDIF_MMCSDCL_VCCCTLMMC *((volatile uint8_t *)(0x42DC2488UL)) +#define bFM_SDIF_MMCSDCL_VCCQCTLMMC *((volatile uint8_t *)(0x42DC248CUL)) +#define bFM4_SDIF_MMCSDCL_VCCQCTLMMC *((volatile uint8_t *)(0x42DC248CUL)) +#define bFM_SDIF_MMCSDCL_MMCDDRSEL *((volatile uint8_t *)(0x42DC24A0UL)) +#define bFM4_SDIF_MMCSDCL_MMCDDRSEL *((volatile uint8_t *)(0x42DC24A0UL)) +#define bFM_SDIF_MMCSDCL_CMDDATDLY *((volatile uint8_t *)(0x42DC24A4UL)) +#define bFM4_SDIF_MMCSDCL_CMDDATDLY *((volatile uint8_t *)(0x42DC24A4UL)) + +#define bFM_SDIF_PSWISGEL_INT5MSSGEN *((volatile uint8_t *)(0x42DC2400UL)) +#define bFM4_SDIF_PSWISGEL_INT5MSSGEN *((volatile uint8_t *)(0x42DC2400UL)) +#define bFM_SDIF_PSWISGEL_INT1MSSGEN *((volatile uint8_t *)(0x42DC2404UL)) +#define bFM4_SDIF_PSWISGEL_INT1MSSGEN *((volatile uint8_t *)(0x42DC2404UL)) + +#define bFM_SDIF_PSWISTEL_INT5MSSTS *((volatile uint8_t *)(0x42DC2380UL)) +#define bFM4_SDIF_PSWISTEL_INT5MSSTS *((volatile uint8_t *)(0x42DC2380UL)) +#define bFM_SDIF_PSWISTEL_INT1MSSTS *((volatile uint8_t *)(0x42DC2384UL)) +#define bFM4_SDIF_PSWISTEL_INT1MSSTS *((volatile uint8_t *)(0x42DC2384UL)) + +#define bFM_SDIF_PSWISTL_INT5MS *((volatile uint8_t *)(0x42DC2300UL)) +#define bFM4_SDIF_PSWISTL_INT5MS *((volatile uint8_t *)(0x42DC2300UL)) +#define bFM_SDIF_PSWISTL_INT1MS *((volatile uint8_t *)(0x42DC2304UL)) +#define bFM4_SDIF_PSWISTL_INT1MS *((volatile uint8_t *)(0x42DC2304UL)) + +#define bFM_SDIF_SACMDEST_ACMD12NOEX *((volatile uint8_t *)(0x42DC0780UL)) +#define bFM4_SDIF_SACMDEST_ACMD12NOEX *((volatile uint8_t *)(0x42DC0780UL)) +#define bFM_SDIF_SACMDEST_ACMDTOERR *((volatile uint8_t *)(0x42DC0784UL)) +#define bFM4_SDIF_SACMDEST_ACMDTOERR *((volatile uint8_t *)(0x42DC0784UL)) +#define bFM_SDIF_SACMDEST_ACMDCRCERR *((volatile uint8_t *)(0x42DC0788UL)) +#define bFM4_SDIF_SACMDEST_ACMDCRCERR *((volatile uint8_t *)(0x42DC0788UL)) +#define bFM_SDIF_SACMDEST_ACMDEBERR *((volatile uint8_t *)(0x42DC078CUL)) +#define bFM4_SDIF_SACMDEST_ACMDEBERR *((volatile uint8_t *)(0x42DC078CUL)) +#define bFM_SDIF_SACMDEST_ACMDIDXERR *((volatile uint8_t *)(0x42DC0790UL)) +#define bFM4_SDIF_SACMDEST_ACMDIDXERR *((volatile uint8_t *)(0x42DC0790UL)) +#define bFM_SDIF_SACMDEST_CMDND12ERR *((volatile uint8_t *)(0x42DC079CUL)) +#define bFM4_SDIF_SACMDEST_CMDND12ERR *((volatile uint8_t *)(0x42DC079CUL)) + +#define bFM_SDIF_SBLKGPCTL_BLCKGSTPREQ *((volatile uint8_t *)(0x42DC0540UL)) +#define bFM4_SDIF_SBLKGPCTL_BLCKGSTPREQ *((volatile uint8_t *)(0x42DC0540UL)) +#define bFM_SDIF_SBLKGPCTL_CONTREQ *((volatile uint8_t *)(0x42DC0544UL)) +#define bFM4_SDIF_SBLKGPCTL_CONTREQ *((volatile uint8_t *)(0x42DC0544UL)) +#define bFM_SDIF_SBLKGPCTL_RDWAITCTL *((volatile uint8_t *)(0x42DC0548UL)) +#define bFM4_SDIF_SBLKGPCTL_RDWAITCTL *((volatile uint8_t *)(0x42DC0548UL)) +#define bFM_SDIF_SBLKGPCTL_BLCKGAPINT *((volatile uint8_t *)(0x42DC054CUL)) +#define bFM4_SDIF_SBLKGPCTL_BLCKGAPINT *((volatile uint8_t *)(0x42DC054CUL)) + +#define bFM_SDIF_SCLKCTL_INTLCLCKEN *((volatile uint8_t *)(0x42DC0580UL)) +#define bFM4_SDIF_SCLKCTL_INTLCLCKEN *((volatile uint8_t *)(0x42DC0580UL)) +#define bFM_SDIF_SCLKCTL_INTLCLCKST *((volatile uint8_t *)(0x42DC0584UL)) +#define bFM4_SDIF_SCLKCTL_INTLCLCKST *((volatile uint8_t *)(0x42DC0584UL)) +#define bFM_SDIF_SCLKCTL_SDCLCKEN *((volatile uint8_t *)(0x42DC0588UL)) +#define bFM4_SDIF_SCLKCTL_SDCLCKEN *((volatile uint8_t *)(0x42DC0588UL)) +#define bFM_SDIF_SCLKCTL_CLCKGENSEL *((volatile uint8_t *)(0x42DC0594UL)) +#define bFM4_SDIF_SCLKCTL_CLCKGENSEL *((volatile uint8_t *)(0x42DC0594UL)) + +#define bFM_SDIF_SCMMD_CMDCRCCHKE *((volatile uint8_t *)(0x42DC01CCUL)) +#define bFM4_SDIF_SCMMD_CMDCRCCHKE *((volatile uint8_t *)(0x42DC01CCUL)) +#define bFM_SDIF_SCMMD_CMDIDXCHKE *((volatile uint8_t *)(0x42DC01D0UL)) +#define bFM4_SDIF_SCMMD_CMDIDXCHKE *((volatile uint8_t *)(0x42DC01D0UL)) +#define bFM_SDIF_SCMMD_DATPRESSEL *((volatile uint8_t *)(0x42DC01D4UL)) +#define bFM4_SDIF_SCMMD_DATPRESSEL *((volatile uint8_t *)(0x42DC01D4UL)) + +#define bFM_SDIF_SEINTSGE_CMDTOERRG *((volatile uint8_t *)(0x42DC0740UL)) +#define bFM4_SDIF_SEINTSGE_CMDTOERRG *((volatile uint8_t *)(0x42DC0740UL)) +#define bFM_SDIF_SEINTSGE_CMDCRCERRG *((volatile uint8_t *)(0x42DC0744UL)) +#define bFM4_SDIF_SEINTSGE_CMDCRCERRG *((volatile uint8_t *)(0x42DC0744UL)) +#define bFM_SDIF_SEINTSGE_CMDEBERRG *((volatile uint8_t *)(0x42DC0748UL)) +#define bFM4_SDIF_SEINTSGE_CMDEBERRG *((volatile uint8_t *)(0x42DC0748UL)) +#define bFM_SDIF_SEINTSGE_CMDIDXERRG *((volatile uint8_t *)(0x42DC074CUL)) +#define bFM4_SDIF_SEINTSGE_CMDIDXERRG *((volatile uint8_t *)(0x42DC074CUL)) +#define bFM_SDIF_SEINTSGE_DTTOERRG *((volatile uint8_t *)(0x42DC0750UL)) +#define bFM4_SDIF_SEINTSGE_DTTOERRG *((volatile uint8_t *)(0x42DC0750UL)) +#define bFM_SDIF_SEINTSGE_DTCRCERRG *((volatile uint8_t *)(0x42DC0754UL)) +#define bFM4_SDIF_SEINTSGE_DTCRCERRG *((volatile uint8_t *)(0x42DC0754UL)) +#define bFM_SDIF_SEINTSGE_DTEBERRG *((volatile uint8_t *)(0x42DC0758UL)) +#define bFM4_SDIF_SEINTSGE_DTEBERRG *((volatile uint8_t *)(0x42DC0758UL)) +#define bFM_SDIF_SEINTSGE_CRTLMTERRG *((volatile uint8_t *)(0x42DC075CUL)) +#define bFM4_SDIF_SEINTSGE_CRTLMTERRG *((volatile uint8_t *)(0x42DC075CUL)) +#define bFM_SDIF_SEINTSGE_ACMD12ERRG *((volatile uint8_t *)(0x42DC0760UL)) +#define bFM4_SDIF_SEINTSGE_ACMD12ERRG *((volatile uint8_t *)(0x42DC0760UL)) +#define bFM_SDIF_SEINTSGE_ADMAERRG *((volatile uint8_t *)(0x42DC0764UL)) +#define bFM4_SDIF_SEINTSGE_ADMAERRG *((volatile uint8_t *)(0x42DC0764UL)) +#define bFM_SDIF_SEINTSGE_TUNINGERRG *((volatile uint8_t *)(0x42DC0768UL)) +#define bFM4_SDIF_SEINTSGE_TUNINGERRG *((volatile uint8_t *)(0x42DC0768UL)) +#define bFM_SDIF_SEINTSGE_BTACKERRG *((volatile uint8_t *)(0x42DC0770UL)) +#define bFM4_SDIF_SEINTSGE_BTACKERRG *((volatile uint8_t *)(0x42DC0770UL)) +#define bFM_SDIF_SEINTSGE_ACMD19ERRG *((volatile uint8_t *)(0x42DC0774UL)) +#define bFM4_SDIF_SEINTSGE_ACMD19ERRG *((volatile uint8_t *)(0x42DC0774UL)) +#define bFM_SDIF_SEINTSGE_AHBMSTERRG *((volatile uint8_t *)(0x42DC0778UL)) +#define bFM4_SDIF_SEINTSGE_AHBMSTERRG *((volatile uint8_t *)(0x42DC0778UL)) + +#define bFM_SDIF_SEINTST_CMDTOERR *((volatile uint8_t *)(0x42DC0640UL)) +#define bFM4_SDIF_SEINTST_CMDTOERR *((volatile uint8_t *)(0x42DC0640UL)) +#define bFM_SDIF_SEINTST_CMDCRCERR *((volatile uint8_t *)(0x42DC0644UL)) +#define bFM4_SDIF_SEINTST_CMDCRCERR *((volatile uint8_t *)(0x42DC0644UL)) +#define bFM_SDIF_SEINTST_CMDEBERR *((volatile uint8_t *)(0x42DC0648UL)) +#define bFM4_SDIF_SEINTST_CMDEBERR *((volatile uint8_t *)(0x42DC0648UL)) +#define bFM_SDIF_SEINTST_CMDIDXERR *((volatile uint8_t *)(0x42DC064CUL)) +#define bFM4_SDIF_SEINTST_CMDIDXERR *((volatile uint8_t *)(0x42DC064CUL)) +#define bFM_SDIF_SEINTST_DTTOERR *((volatile uint8_t *)(0x42DC0650UL)) +#define bFM4_SDIF_SEINTST_DTTOERR *((volatile uint8_t *)(0x42DC0650UL)) +#define bFM_SDIF_SEINTST_DTCRCERR *((volatile uint8_t *)(0x42DC0654UL)) +#define bFM4_SDIF_SEINTST_DTCRCERR *((volatile uint8_t *)(0x42DC0654UL)) +#define bFM_SDIF_SEINTST_DTEBERR *((volatile uint8_t *)(0x42DC0658UL)) +#define bFM4_SDIF_SEINTST_DTEBERR *((volatile uint8_t *)(0x42DC0658UL)) +#define bFM_SDIF_SEINTST_CRTLMTERR *((volatile uint8_t *)(0x42DC065CUL)) +#define bFM4_SDIF_SEINTST_CRTLMTERR *((volatile uint8_t *)(0x42DC065CUL)) +#define bFM_SDIF_SEINTST_ACMD12ERR *((volatile uint8_t *)(0x42DC0660UL)) +#define bFM4_SDIF_SEINTST_ACMD12ERR *((volatile uint8_t *)(0x42DC0660UL)) +#define bFM_SDIF_SEINTST_ADMAERR *((volatile uint8_t *)(0x42DC0664UL)) +#define bFM4_SDIF_SEINTST_ADMAERR *((volatile uint8_t *)(0x42DC0664UL)) +#define bFM_SDIF_SEINTST_TUNINGERR *((volatile uint8_t *)(0x42DC0668UL)) +#define bFM4_SDIF_SEINTST_TUNINGERR *((volatile uint8_t *)(0x42DC0668UL)) +#define bFM_SDIF_SEINTST_BTACKERR *((volatile uint8_t *)(0x42DC0670UL)) +#define bFM4_SDIF_SEINTST_BTACKERR *((volatile uint8_t *)(0x42DC0670UL)) +#define bFM_SDIF_SEINTST_ACMD19ERR *((volatile uint8_t *)(0x42DC0674UL)) +#define bFM4_SDIF_SEINTST_ACMD19ERR *((volatile uint8_t *)(0x42DC0674UL)) +#define bFM_SDIF_SEINTST_AHBMSTERR *((volatile uint8_t *)(0x42DC0678UL)) +#define bFM4_SDIF_SEINTST_AHBMSTERR *((volatile uint8_t *)(0x42DC0678UL)) + +#define bFM_SDIF_SEINTSTE_CMDTOERRS *((volatile uint8_t *)(0x42DC06C0UL)) +#define bFM4_SDIF_SEINTSTE_CMDTOERRS *((volatile uint8_t *)(0x42DC06C0UL)) +#define bFM_SDIF_SEINTSTE_CMDCRCERRS *((volatile uint8_t *)(0x42DC06C4UL)) +#define bFM4_SDIF_SEINTSTE_CMDCRCERRS *((volatile uint8_t *)(0x42DC06C4UL)) +#define bFM_SDIF_SEINTSTE_CMDEBERRS *((volatile uint8_t *)(0x42DC06C8UL)) +#define bFM4_SDIF_SEINTSTE_CMDEBERRS *((volatile uint8_t *)(0x42DC06C8UL)) +#define bFM_SDIF_SEINTSTE_CMDIDXERRS *((volatile uint8_t *)(0x42DC06CCUL)) +#define bFM4_SDIF_SEINTSTE_CMDIDXERRS *((volatile uint8_t *)(0x42DC06CCUL)) +#define bFM_SDIF_SEINTSTE_DTTOERRS *((volatile uint8_t *)(0x42DC06D0UL)) +#define bFM4_SDIF_SEINTSTE_DTTOERRS *((volatile uint8_t *)(0x42DC06D0UL)) +#define bFM_SDIF_SEINTSTE_DTCRCERRS *((volatile uint8_t *)(0x42DC06D4UL)) +#define bFM4_SDIF_SEINTSTE_DTCRCERRS *((volatile uint8_t *)(0x42DC06D4UL)) +#define bFM_SDIF_SEINTSTE_DTEBERRS *((volatile uint8_t *)(0x42DC06D8UL)) +#define bFM4_SDIF_SEINTSTE_DTEBERRS *((volatile uint8_t *)(0x42DC06D8UL)) +#define bFM_SDIF_SEINTSTE_CRTLMTERRS *((volatile uint8_t *)(0x42DC06DCUL)) +#define bFM4_SDIF_SEINTSTE_CRTLMTERRS *((volatile uint8_t *)(0x42DC06DCUL)) +#define bFM_SDIF_SEINTSTE_ACMD12ERRS *((volatile uint8_t *)(0x42DC06E0UL)) +#define bFM4_SDIF_SEINTSTE_ACMD12ERRS *((volatile uint8_t *)(0x42DC06E0UL)) +#define bFM_SDIF_SEINTSTE_ADMAERRS *((volatile uint8_t *)(0x42DC06E4UL)) +#define bFM4_SDIF_SEINTSTE_ADMAERRS *((volatile uint8_t *)(0x42DC06E4UL)) +#define bFM_SDIF_SEINTSTE_TUNINGERRS *((volatile uint8_t *)(0x42DC06E8UL)) +#define bFM4_SDIF_SEINTSTE_TUNINGERRS *((volatile uint8_t *)(0x42DC06E8UL)) +#define bFM_SDIF_SEINTSTE_BTACKERRS *((volatile uint8_t *)(0x42DC06F0UL)) +#define bFM4_SDIF_SEINTSTE_BTACKERRS *((volatile uint8_t *)(0x42DC06F0UL)) +#define bFM_SDIF_SEINTSTE_ACMD19ERRS *((volatile uint8_t *)(0x42DC06F4UL)) +#define bFM4_SDIF_SEINTSTE_ACMD19ERRS *((volatile uint8_t *)(0x42DC06F4UL)) +#define bFM_SDIF_SEINTSTE_AHBMSTERRS *((volatile uint8_t *)(0x42DC06F8UL)) +#define bFM4_SDIF_SEINTSTE_AHBMSTERRS *((volatile uint8_t *)(0x42DC06F8UL)) + +#define bFM_SDIF_SFEEIST_FETOERR *((volatile uint8_t *)(0x42DC0A40UL)) +#define bFM4_SDIF_SFEEIST_FETOERR *((volatile uint8_t *)(0x42DC0A40UL)) +#define bFM_SDIF_SFEEIST_FECRCERR *((volatile uint8_t *)(0x42DC0A44UL)) +#define bFM4_SDIF_SFEEIST_FECRCERR *((volatile uint8_t *)(0x42DC0A44UL)) +#define bFM_SDIF_SFEEIST_FEEBERR *((volatile uint8_t *)(0x42DC0A48UL)) +#define bFM4_SDIF_SFEEIST_FEEBERR *((volatile uint8_t *)(0x42DC0A48UL)) +#define bFM_SDIF_SFEEIST_FEIDXERR *((volatile uint8_t *)(0x42DC0A4CUL)) +#define bFM4_SDIF_SFEEIST_FEIDXERR *((volatile uint8_t *)(0x42DC0A4CUL)) +#define bFM_SDIF_SFEEIST_FEDTOTERR *((volatile uint8_t *)(0x42DC0A50UL)) +#define bFM4_SDIF_SFEEIST_FEDTOTERR *((volatile uint8_t *)(0x42DC0A50UL)) +#define bFM_SDIF_SFEEIST_FEDTCRCERR *((volatile uint8_t *)(0x42DC0A54UL)) +#define bFM4_SDIF_SFEEIST_FEDTCRCERR *((volatile uint8_t *)(0x42DC0A54UL)) +#define bFM_SDIF_SFEEIST_FEDTEBERR *((volatile uint8_t *)(0x42DC0A58UL)) +#define bFM4_SDIF_SFEEIST_FEDTEBERR *((volatile uint8_t *)(0x42DC0A58UL)) +#define bFM_SDIF_SFEEIST_FECRLTERR *((volatile uint8_t *)(0x42DC0A5CUL)) +#define bFM4_SDIF_SFEEIST_FECRLTERR *((volatile uint8_t *)(0x42DC0A5CUL)) +#define bFM_SDIF_SFEEIST_FEA12ERR *((volatile uint8_t *)(0x42DC0A60UL)) +#define bFM4_SDIF_SFEEIST_FEA12ERR *((volatile uint8_t *)(0x42DC0A60UL)) +#define bFM_SDIF_SFEEIST_FEADMAERR *((volatile uint8_t *)(0x42DC0A64UL)) +#define bFM4_SDIF_SFEEIST_FEADMAERR *((volatile uint8_t *)(0x42DC0A64UL)) +#define bFM_SDIF_SFEEIST_FETUNEERR *((volatile uint8_t *)(0x42DC0A68UL)) +#define bFM4_SDIF_SFEEIST_FETUNEERR *((volatile uint8_t *)(0x42DC0A68UL)) +#define bFM_SDIF_SFEEIST_FEACKERR *((volatile uint8_t *)(0x42DC0A70UL)) +#define bFM4_SDIF_SFEEIST_FEACKERR *((volatile uint8_t *)(0x42DC0A70UL)) +#define bFM_SDIF_SFEEIST_FEA19ERR *((volatile uint8_t *)(0x42DC0A74UL)) +#define bFM4_SDIF_SFEEIST_FEA19ERR *((volatile uint8_t *)(0x42DC0A74UL)) +#define bFM_SDIF_SFEEIST_FEAHBMSERR *((volatile uint8_t *)(0x42DC0A78UL)) +#define bFM4_SDIF_SFEEIST_FEAHBMSERR *((volatile uint8_t *)(0x42DC0A78UL)) + +#define bFM_SDIF_SHCTL1_LEDCTRL *((volatile uint8_t *)(0x42DC0500UL)) +#define bFM4_SDIF_SHCTL1_LEDCTRL *((volatile uint8_t *)(0x42DC0500UL)) +#define bFM_SDIF_SHCTL1_DATAWIDTH *((volatile uint8_t *)(0x42DC0504UL)) +#define bFM4_SDIF_SHCTL1_DATAWIDTH *((volatile uint8_t *)(0x42DC0504UL)) +#define bFM_SDIF_SHCTL1_HIGHSPDEN *((volatile uint8_t *)(0x42DC0508UL)) +#define bFM4_SDIF_SHCTL1_HIGHSPDEN *((volatile uint8_t *)(0x42DC0508UL)) +#define bFM_SDIF_SHCTL1_EXTDTWIDTH *((volatile uint8_t *)(0x42DC0514UL)) +#define bFM4_SDIF_SHCTL1_EXTDTWIDTH *((volatile uint8_t *)(0x42DC0514UL)) +#define bFM_SDIF_SHCTL1_CDTSTLVL *((volatile uint8_t *)(0x42DC0518UL)) +#define bFM4_SDIF_SHCTL1_CDTSTLVL *((volatile uint8_t *)(0x42DC0518UL)) +#define bFM_SDIF_SHCTL1_CDSGNSEL *((volatile uint8_t *)(0x42DC051CUL)) +#define bFM4_SDIF_SHCTL1_CDSGNSEL *((volatile uint8_t *)(0x42DC051CUL)) + +#define bFM_SDIF_SHCTL2_V18SGNEN *((volatile uint8_t *)(0x42DC07CCUL)) +#define bFM4_SDIF_SHCTL2_V18SGNEN *((volatile uint8_t *)(0x42DC07CCUL)) +#define bFM_SDIF_SHCTL2_DOTUING *((volatile uint8_t *)(0x42DC07D8UL)) +#define bFM4_SDIF_SHCTL2_DOTUING *((volatile uint8_t *)(0x42DC07D8UL)) +#define bFM_SDIF_SHCTL2_SMPCLKSEL *((volatile uint8_t *)(0x42DC07DCUL)) +#define bFM4_SDIF_SHCTL2_SMPCLKSEL *((volatile uint8_t *)(0x42DC07DCUL)) +#define bFM_SDIF_SHCTL2_ASYINTEN *((volatile uint8_t *)(0x42DC07F8UL)) +#define bFM4_SDIF_SHCTL2_ASYINTEN *((volatile uint8_t *)(0x42DC07F8UL)) +#define bFM_SDIF_SHCTL2_PREVALEN *((volatile uint8_t *)(0x42DC07FCUL)) +#define bFM4_SDIF_SHCTL2_PREVALEN *((volatile uint8_t *)(0x42DC07FCUL)) + +#define bFM_SDIF_SNINTSGE_CMDCMPLTG *((volatile uint8_t *)(0x42DC0700UL)) +#define bFM4_SDIF_SNINTSGE_CMDCMPLTG *((volatile uint8_t *)(0x42DC0700UL)) +#define bFM_SDIF_SNINTSGE_TRSFCMPLTG *((volatile uint8_t *)(0x42DC0704UL)) +#define bFM4_SDIF_SNINTSGE_TRSFCMPLTG *((volatile uint8_t *)(0x42DC0704UL)) +#define bFM_SDIF_SNINTSGE_BLCKGEVNTG *((volatile uint8_t *)(0x42DC0708UL)) +#define bFM4_SDIF_SNINTSGE_BLCKGEVNTG *((volatile uint8_t *)(0x42DC0708UL)) +#define bFM_SDIF_SNINTSGE_DMAINTG *((volatile uint8_t *)(0x42DC070CUL)) +#define bFM4_SDIF_SNINTSGE_DMAINTG *((volatile uint8_t *)(0x42DC070CUL)) +#define bFM_SDIF_SNINTSGE_BUFWRRDYG *((volatile uint8_t *)(0x42DC0710UL)) +#define bFM4_SDIF_SNINTSGE_BUFWRRDYG *((volatile uint8_t *)(0x42DC0710UL)) +#define bFM_SDIF_SNINTSGE_BUFRDRDYG *((volatile uint8_t *)(0x42DC0714UL)) +#define bFM4_SDIF_SNINTSGE_BUFRDRDYG *((volatile uint8_t *)(0x42DC0714UL)) +#define bFM_SDIF_SNINTSGE_CARDINSG *((volatile uint8_t *)(0x42DC0718UL)) +#define bFM4_SDIF_SNINTSGE_CARDINSG *((volatile uint8_t *)(0x42DC0718UL)) +#define bFM_SDIF_SNINTSGE_CARDRMVG *((volatile uint8_t *)(0x42DC071CUL)) +#define bFM4_SDIF_SNINTSGE_CARDRMVG *((volatile uint8_t *)(0x42DC071CUL)) +#define bFM_SDIF_SNINTSGE_CARDINTG *((volatile uint8_t *)(0x42DC0720UL)) +#define bFM4_SDIF_SNINTSGE_CARDINTG *((volatile uint8_t *)(0x42DC0720UL)) +#define bFM_SDIF_SNINTSGE_INT_AG *((volatile uint8_t *)(0x42DC0724UL)) +#define bFM4_SDIF_SNINTSGE_INT_AG *((volatile uint8_t *)(0x42DC0724UL)) +#define bFM_SDIF_SNINTSGE_INT_BG *((volatile uint8_t *)(0x42DC0728UL)) +#define bFM4_SDIF_SNINTSGE_INT_BG *((volatile uint8_t *)(0x42DC0728UL)) +#define bFM_SDIF_SNINTSGE_INT_CG *((volatile uint8_t *)(0x42DC072CUL)) +#define bFM4_SDIF_SNINTSGE_INT_CG *((volatile uint8_t *)(0x42DC072CUL)) +#define bFM_SDIF_SNINTSGE_RETUNEEVTG *((volatile uint8_t *)(0x42DC0730UL)) +#define bFM4_SDIF_SNINTSGE_RETUNEEVTG *((volatile uint8_t *)(0x42DC0730UL)) + +#define bFM_SDIF_SNINTST_CMDCMPLT *((volatile uint8_t *)(0x42DC0600UL)) +#define bFM4_SDIF_SNINTST_CMDCMPLT *((volatile uint8_t *)(0x42DC0600UL)) +#define bFM_SDIF_SNINTST_TRSFCMPLT *((volatile uint8_t *)(0x42DC0604UL)) +#define bFM4_SDIF_SNINTST_TRSFCMPLT *((volatile uint8_t *)(0x42DC0604UL)) +#define bFM_SDIF_SNINTST_BLCKGEVNT *((volatile uint8_t *)(0x42DC0608UL)) +#define bFM4_SDIF_SNINTST_BLCKGEVNT *((volatile uint8_t *)(0x42DC0608UL)) +#define bFM_SDIF_SNINTST_DMAINT *((volatile uint8_t *)(0x42DC060CUL)) +#define bFM4_SDIF_SNINTST_DMAINT *((volatile uint8_t *)(0x42DC060CUL)) +#define bFM_SDIF_SNINTST_BUFWRRDY *((volatile uint8_t *)(0x42DC0610UL)) +#define bFM4_SDIF_SNINTST_BUFWRRDY *((volatile uint8_t *)(0x42DC0610UL)) +#define bFM_SDIF_SNINTST_BUFRDRDY *((volatile uint8_t *)(0x42DC0614UL)) +#define bFM4_SDIF_SNINTST_BUFRDRDY *((volatile uint8_t *)(0x42DC0614UL)) +#define bFM_SDIF_SNINTST_CARDINS *((volatile uint8_t *)(0x42DC0618UL)) +#define bFM4_SDIF_SNINTST_CARDINS *((volatile uint8_t *)(0x42DC0618UL)) +#define bFM_SDIF_SNINTST_CARDRMV *((volatile uint8_t *)(0x42DC061CUL)) +#define bFM4_SDIF_SNINTST_CARDRMV *((volatile uint8_t *)(0x42DC061CUL)) +#define bFM_SDIF_SNINTST_CARDINT *((volatile uint8_t *)(0x42DC0620UL)) +#define bFM4_SDIF_SNINTST_CARDINT *((volatile uint8_t *)(0x42DC0620UL)) +#define bFM_SDIF_SNINTST_INT_A *((volatile uint8_t *)(0x42DC0624UL)) +#define bFM4_SDIF_SNINTST_INT_A *((volatile uint8_t *)(0x42DC0624UL)) +#define bFM_SDIF_SNINTST_INT_B *((volatile uint8_t *)(0x42DC0628UL)) +#define bFM4_SDIF_SNINTST_INT_B *((volatile uint8_t *)(0x42DC0628UL)) +#define bFM_SDIF_SNINTST_INT_C *((volatile uint8_t *)(0x42DC062CUL)) +#define bFM4_SDIF_SNINTST_INT_C *((volatile uint8_t *)(0x42DC062CUL)) +#define bFM_SDIF_SNINTST_RETUNEEVT *((volatile uint8_t *)(0x42DC0630UL)) +#define bFM4_SDIF_SNINTST_RETUNEEVT *((volatile uint8_t *)(0x42DC0630UL)) +#define bFM_SDIF_SNINTST_ERRORINT *((volatile uint8_t *)(0x42DC063CUL)) +#define bFM4_SDIF_SNINTST_ERRORINT *((volatile uint8_t *)(0x42DC063CUL)) + +#define bFM_SDIF_SNINTSTE_CMDCMPLTS *((volatile uint8_t *)(0x42DC0680UL)) +#define bFM4_SDIF_SNINTSTE_CMDCMPLTS *((volatile uint8_t *)(0x42DC0680UL)) +#define bFM_SDIF_SNINTSTE_TRSFCMPLTS *((volatile uint8_t *)(0x42DC0684UL)) +#define bFM4_SDIF_SNINTSTE_TRSFCMPLTS *((volatile uint8_t *)(0x42DC0684UL)) +#define bFM_SDIF_SNINTSTE_BLCKGEVNTS *((volatile uint8_t *)(0x42DC0688UL)) +#define bFM4_SDIF_SNINTSTE_BLCKGEVNTS *((volatile uint8_t *)(0x42DC0688UL)) +#define bFM_SDIF_SNINTSTE_DMAINTS *((volatile uint8_t *)(0x42DC068CUL)) +#define bFM4_SDIF_SNINTSTE_DMAINTS *((volatile uint8_t *)(0x42DC068CUL)) +#define bFM_SDIF_SNINTSTE_BUFWRRDYS *((volatile uint8_t *)(0x42DC0690UL)) +#define bFM4_SDIF_SNINTSTE_BUFWRRDYS *((volatile uint8_t *)(0x42DC0690UL)) +#define bFM_SDIF_SNINTSTE_BUFRDRDYS *((volatile uint8_t *)(0x42DC0694UL)) +#define bFM4_SDIF_SNINTSTE_BUFRDRDYS *((volatile uint8_t *)(0x42DC0694UL)) +#define bFM_SDIF_SNINTSTE_CARDINSS *((volatile uint8_t *)(0x42DC0698UL)) +#define bFM4_SDIF_SNINTSTE_CARDINSS *((volatile uint8_t *)(0x42DC0698UL)) +#define bFM_SDIF_SNINTSTE_CARDRMVS *((volatile uint8_t *)(0x42DC069CUL)) +#define bFM4_SDIF_SNINTSTE_CARDRMVS *((volatile uint8_t *)(0x42DC069CUL)) +#define bFM_SDIF_SNINTSTE_CARDINTS *((volatile uint8_t *)(0x42DC06A0UL)) +#define bFM4_SDIF_SNINTSTE_CARDINTS *((volatile uint8_t *)(0x42DC06A0UL)) +#define bFM_SDIF_SNINTSTE_INT_AS *((volatile uint8_t *)(0x42DC06A4UL)) +#define bFM4_SDIF_SNINTSTE_INT_AS *((volatile uint8_t *)(0x42DC06A4UL)) +#define bFM_SDIF_SNINTSTE_INT_BS *((volatile uint8_t *)(0x42DC06A8UL)) +#define bFM4_SDIF_SNINTSTE_INT_BS *((volatile uint8_t *)(0x42DC06A8UL)) +#define bFM_SDIF_SNINTSTE_INT_CS *((volatile uint8_t *)(0x42DC06ACUL)) +#define bFM4_SDIF_SNINTSTE_INT_CS *((volatile uint8_t *)(0x42DC06ACUL)) +#define bFM_SDIF_SNINTSTE_RETUNEEVTS *((volatile uint8_t *)(0x42DC06B0UL)) +#define bFM4_SDIF_SNINTSTE_RETUNEEVTS *((volatile uint8_t *)(0x42DC06B0UL)) + +#define bFM_SDIF_SPRSTAT_CMDINH *((volatile uint8_t *)(0x42DC0480UL)) +#define bFM4_SDIF_SPRSTAT_CMDINH *((volatile uint8_t *)(0x42DC0480UL)) +#define bFM_SDIF_SPRSTAT_CMDDATINH *((volatile uint8_t *)(0x42DC0484UL)) +#define bFM4_SDIF_SPRSTAT_CMDDATINH *((volatile uint8_t *)(0x42DC0484UL)) +#define bFM_SDIF_SPRSTAT_DATLNACT *((volatile uint8_t *)(0x42DC0488UL)) +#define bFM4_SDIF_SPRSTAT_DATLNACT *((volatile uint8_t *)(0x42DC0488UL)) +#define bFM_SDIF_SPRSTAT_RETUNEREQ *((volatile uint8_t *)(0x42DC048CUL)) +#define bFM4_SDIF_SPRSTAT_RETUNEREQ *((volatile uint8_t *)(0x42DC048CUL)) +#define bFM_SDIF_SPRSTAT_WRTRSFACT *((volatile uint8_t *)(0x42DC04A0UL)) +#define bFM4_SDIF_SPRSTAT_WRTRSFACT *((volatile uint8_t *)(0x42DC04A0UL)) +#define bFM_SDIF_SPRSTAT_RDTRSFACT *((volatile uint8_t *)(0x42DC04A4UL)) +#define bFM4_SDIF_SPRSTAT_RDTRSFACT *((volatile uint8_t *)(0x42DC04A4UL)) +#define bFM_SDIF_SPRSTAT_BUFWREN *((volatile uint8_t *)(0x42DC04A8UL)) +#define bFM4_SDIF_SPRSTAT_BUFWREN *((volatile uint8_t *)(0x42DC04A8UL)) +#define bFM_SDIF_SPRSTAT_BUFRDEN *((volatile uint8_t *)(0x42DC04ACUL)) +#define bFM4_SDIF_SPRSTAT_BUFRDEN *((volatile uint8_t *)(0x42DC04ACUL)) +#define bFM_SDIF_SPRSTAT_CARDINS *((volatile uint8_t *)(0x42DC04C0UL)) +#define bFM4_SDIF_SPRSTAT_CARDINS *((volatile uint8_t *)(0x42DC04C0UL)) +#define bFM_SDIF_SPRSTAT_CARDSTB *((volatile uint8_t *)(0x42DC04C4UL)) +#define bFM4_SDIF_SPRSTAT_CARDSTB *((volatile uint8_t *)(0x42DC04C4UL)) +#define bFM_SDIF_SPRSTAT_CARDDET *((volatile uint8_t *)(0x42DC04C8UL)) +#define bFM4_SDIF_SPRSTAT_CARDDET *((volatile uint8_t *)(0x42DC04C8UL)) +#define bFM_SDIF_SPRSTAT_WPPINLVL *((volatile uint8_t *)(0x42DC04CCUL)) +#define bFM4_SDIF_SPRSTAT_WPPINLVL *((volatile uint8_t *)(0x42DC04CCUL)) +#define bFM_SDIF_SPRSTAT_CMDLNSGN *((volatile uint8_t *)(0x42DC04E0UL)) +#define bFM4_SDIF_SPRSTAT_CMDLNSGN *((volatile uint8_t *)(0x42DC04E0UL)) + +#define bFM_SDIF_SPRVAL0_CGSELVAL *((volatile uint8_t *)(0x42DC0C28UL)) +#define bFM4_SDIF_SPRVAL0_CGSELVAL *((volatile uint8_t *)(0x42DC0C28UL)) + +#define bFM_SDIF_SPRVAL1_CGSELVAL *((volatile uint8_t *)(0x42DC0C68UL)) +#define bFM4_SDIF_SPRVAL1_CGSELVAL *((volatile uint8_t *)(0x42DC0C68UL)) + +#define bFM_SDIF_SPRVAL2_CGSELVAL *((volatile uint8_t *)(0x42DC0CA8UL)) +#define bFM4_SDIF_SPRVAL2_CGSELVAL *((volatile uint8_t *)(0x42DC0CA8UL)) + +#define bFM_SDIF_SPRVAL3_CGSELVAL *((volatile uint8_t *)(0x42DC0CE8UL)) +#define bFM4_SDIF_SPRVAL3_CGSELVAL *((volatile uint8_t *)(0x42DC0CE8UL)) + +#define bFM_SDIF_SPRVAL4_CGSELVAL *((volatile uint8_t *)(0x42DC0D28UL)) +#define bFM4_SDIF_SPRVAL4_CGSELVAL *((volatile uint8_t *)(0x42DC0D28UL)) + +#define bFM_SDIF_SPRVAL5_CGSELVAL *((volatile uint8_t *)(0x42DC0D68UL)) +#define bFM4_SDIF_SPRVAL5_CGSELVAL *((volatile uint8_t *)(0x42DC0D68UL)) + +#define bFM_SDIF_SPRVAL6_CGSELVAL *((volatile uint8_t *)(0x42DC0DA8UL)) +#define bFM4_SDIF_SPRVAL6_CGSELVAL *((volatile uint8_t *)(0x42DC0DA8UL)) + +#define bFM_SDIF_SPRVAL7_CGSELVAL *((volatile uint8_t *)(0x42DC0DE8UL)) +#define bFM4_SDIF_SPRVAL7_CGSELVAL *((volatile uint8_t *)(0x42DC0DE8UL)) + +#define bFM_SDIF_SPWRCTL_SDBUSPWR *((volatile uint8_t *)(0x42DC0520UL)) +#define bFM4_SDIF_SPWRCTL_SDBUSPWR *((volatile uint8_t *)(0x42DC0520UL)) + +#define bFM_SDIF_SPWSWCL_ATPWRSWEN *((volatile uint8_t *)(0x42DC2080UL)) +#define bFM4_SDIF_SPWSWCL_ATPWRSWEN *((volatile uint8_t *)(0x42DC2080UL)) +#define bFM_SDIF_SPWSWCL_IOREGSEL *((volatile uint8_t *)(0x42DC2084UL)) +#define bFM4_SDIF_SPWSWCL_IOREGSEL *((volatile uint8_t *)(0x42DC2084UL)) + +#define bFM_SDIF_SSRST_SWRSTALL *((volatile uint8_t *)(0x42DC05E0UL)) +#define bFM4_SDIF_SSRST_SWRSTALL *((volatile uint8_t *)(0x42DC05E0UL)) +#define bFM_SDIF_SSRST_SWRSTCMDLN *((volatile uint8_t *)(0x42DC05E4UL)) +#define bFM4_SDIF_SSRST_SWRSTCMDLN *((volatile uint8_t *)(0x42DC05E4UL)) +#define bFM_SDIF_SSRST_SWRSTDATLN *((volatile uint8_t *)(0x42DC05E8UL)) +#define bFM4_SDIF_SSRST_SWRSTDATLN *((volatile uint8_t *)(0x42DC05E8UL)) + +#define bFM_SDIF_STRSFMD_DMAEN *((volatile uint8_t *)(0x42DC0180UL)) +#define bFM4_SDIF_STRSFMD_DMAEN *((volatile uint8_t *)(0x42DC0180UL)) +#define bFM_SDIF_STRSFMD_BLCKCNTEN *((volatile uint8_t *)(0x42DC0184UL)) +#define bFM4_SDIF_STRSFMD_BLCKCNTEN *((volatile uint8_t *)(0x42DC0184UL)) +#define bFM_SDIF_STRSFMD_DTTRSFDIR *((volatile uint8_t *)(0x42DC0190UL)) +#define bFM4_SDIF_STRSFMD_DTTRSFDIR *((volatile uint8_t *)(0x42DC0190UL)) +#define bFM_SDIF_STRSFMD_BLCKCNTSEL *((volatile uint8_t *)(0x42DC0194UL)) +#define bFM4_SDIF_STRSFMD_BLCKCNTSEL *((volatile uint8_t *)(0x42DC0194UL)) + +#define bFM_SDIF_STUNSETH_CMDCFCHKDS *((volatile uint8_t *)(0x42DC2140UL)) +#define bFM4_SDIF_STUNSETH_CMDCFCHKDS *((volatile uint8_t *)(0x42DC2140UL)) + +#define bFM_SDIF_STUNSETL_TNPHSELEN *((volatile uint8_t *)(0x42DC2120UL)) +#define bFM4_SDIF_STUNSETL_TNPHSELEN *((volatile uint8_t *)(0x42DC2120UL)) +#define bFM_SDIF_STUNSETL_TNERRBDSEL *((volatile uint8_t *)(0x42DC2124UL)) +#define bFM4_SDIF_STUNSETL_TNERRBDSEL *((volatile uint8_t *)(0x42DC2124UL)) +#define bFM_SDIF_STUNSETL_RETNTAPSEL *((volatile uint8_t *)(0x42DC2128UL)) +#define bFM4_SDIF_STUNSETL_RETNTAPSEL *((volatile uint8_t *)(0x42DC2128UL)) + +#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN0 *((volatile uint8_t *)(0x42DC0560UL)) +#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN0 *((volatile uint8_t *)(0x42DC0560UL)) +#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN1 *((volatile uint8_t *)(0x42DC0564UL)) +#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN1 *((volatile uint8_t *)(0x42DC0564UL)) +#define bFM_SDIF_SWKUPCTL_WKUPEVNTEN2 *((volatile uint8_t *)(0x42DC0568UL)) +#define bFM4_SDIF_SWKUPCTL_WKUPEVNTEN2 *((volatile uint8_t *)(0x42DC0568UL)) + + +/******************************************************************************* +* SWWDT Registers SWWDT +* Bitband Section +*******************************************************************************/ +#define bFM_SWWDT_WDOGCONTROL_INTEN *((volatile uint32_t*)(0x42240100UL)) +#define bFM4_SWWDT_WDOGCONTROL_INTEN *((volatile uint32_t*)(0x42240100UL)) +#define bFM_SWWDT_WDOGCONTROL_RESEN *((volatile uint32_t*)(0x42240104UL)) +#define bFM4_SWWDT_WDOGCONTROL_RESEN *((volatile uint32_t*)(0x42240104UL)) +#define bFM_SWWDT_WDOGCONTROL_SPM *((volatile uint32_t*)(0x42240110UL)) +#define bFM4_SWWDT_WDOGCONTROL_SPM *((volatile uint32_t*)(0x42240110UL)) + +#define bFM_SWWDT_WDOGRIS_RIS *((volatile uint32_t*)(0x42240200UL)) +#define bFM4_SWWDT_WDOGRIS_RIS *((volatile uint32_t*)(0x42240200UL)) + +#define bFM_SWWDT_WDOGSPMC_TGR *((volatile uint32_t*)(0x42240300UL)) +#define bFM4_SWWDT_WDOGSPMC_TGR *((volatile uint32_t*)(0x42240300UL)) + + +/******************************************************************************* +* UNIQUE_ID Registers UNIQUE_ID +* Bitband Section +*******************************************************************************/ + +/******************************************************************************* +* USB Registers USB0 +* Bitband Section +*******************************************************************************/ +#define bFM_USB0_EP0C_STAL *((volatile uint16_t*)(0x428424A4UL)) +#define bFM4_USB0_EP0C_STAL *((volatile uint16_t*)(0x428424A4UL)) + +#define bFM_USB0_EP0IS_DRQI *((volatile uint16_t*)(0x428428A8UL)) +#define bFM4_USB0_EP0IS_DRQI *((volatile uint16_t*)(0x428428A8UL)) +#define bFM_USB0_EP0IS_DRQIIE *((volatile uint16_t*)(0x428428B8UL)) +#define bFM4_USB0_EP0IS_DRQIIE *((volatile uint16_t*)(0x428428B8UL)) +#define bFM_USB0_EP0IS_BFINI *((volatile uint16_t*)(0x428428BCUL)) +#define bFM4_USB0_EP0IS_BFINI *((volatile uint16_t*)(0x428428BCUL)) + +#define bFM_USB0_EP0OS_SPK *((volatile uint16_t*)(0x42842924UL)) +#define bFM4_USB0_EP0OS_SPK *((volatile uint16_t*)(0x42842924UL)) +#define bFM_USB0_EP0OS_DRQO *((volatile uint16_t*)(0x42842928UL)) +#define bFM4_USB0_EP0OS_DRQO *((volatile uint16_t*)(0x42842928UL)) +#define bFM_USB0_EP0OS_SPKIE *((volatile uint16_t*)(0x42842934UL)) +#define bFM4_USB0_EP0OS_SPKIE *((volatile uint16_t*)(0x42842934UL)) +#define bFM_USB0_EP0OS_DRQOIE *((volatile uint16_t*)(0x42842938UL)) +#define bFM4_USB0_EP0OS_DRQOIE *((volatile uint16_t*)(0x42842938UL)) +#define bFM_USB0_EP0OS_BFINI *((volatile uint16_t*)(0x4284293CUL)) +#define bFM4_USB0_EP0OS_BFINI *((volatile uint16_t*)(0x4284293CUL)) + +#define bFM_USB0_EP1C_STAL *((volatile uint16_t*)(0x42842524UL)) +#define bFM4_USB0_EP1C_STAL *((volatile uint16_t*)(0x42842524UL)) +#define bFM_USB0_EP1C_NULE *((volatile uint16_t*)(0x42842528UL)) +#define bFM4_USB0_EP1C_NULE *((volatile uint16_t*)(0x42842528UL)) +#define bFM_USB0_EP1C_DMAE *((volatile uint16_t*)(0x4284252CUL)) +#define bFM4_USB0_EP1C_DMAE *((volatile uint16_t*)(0x4284252CUL)) +#define bFM_USB0_EP1C_DIR *((volatile uint16_t*)(0x42842530UL)) +#define bFM4_USB0_EP1C_DIR *((volatile uint16_t*)(0x42842530UL)) +#define bFM_USB0_EP1C_EPEN *((volatile uint16_t*)(0x4284253CUL)) +#define bFM4_USB0_EP1C_EPEN *((volatile uint16_t*)(0x4284253CUL)) + +#define bFM_USB0_EP1S_SPK *((volatile uint16_t*)(0x428429A4UL)) +#define bFM4_USB0_EP1S_SPK *((volatile uint16_t*)(0x428429A4UL)) +#define bFM_USB0_EP1S_DRQ *((volatile uint16_t*)(0x428429A8UL)) +#define bFM4_USB0_EP1S_DRQ *((volatile uint16_t*)(0x428429A8UL)) +#define bFM_USB0_EP1S_BUSY *((volatile uint16_t*)(0x428429ACUL)) +#define bFM4_USB0_EP1S_BUSY *((volatile uint16_t*)(0x428429ACUL)) +#define bFM_USB0_EP1S_SPKIE *((volatile uint16_t*)(0x428429B4UL)) +#define bFM4_USB0_EP1S_SPKIE *((volatile uint16_t*)(0x428429B4UL)) +#define bFM_USB0_EP1S_DRQIE *((volatile uint16_t*)(0x428429B8UL)) +#define bFM4_USB0_EP1S_DRQIE *((volatile uint16_t*)(0x428429B8UL)) +#define bFM_USB0_EP1S_BFINI *((volatile uint16_t*)(0x428429BCUL)) +#define bFM4_USB0_EP1S_BFINI *((volatile uint16_t*)(0x428429BCUL)) + +#define bFM_USB0_EP2C_STAL *((volatile uint16_t*)(0x428425A4UL)) +#define bFM4_USB0_EP2C_STAL *((volatile uint16_t*)(0x428425A4UL)) +#define bFM_USB0_EP2C_NULE *((volatile uint16_t*)(0x428425A8UL)) +#define bFM4_USB0_EP2C_NULE *((volatile uint16_t*)(0x428425A8UL)) +#define bFM_USB0_EP2C_DMAE *((volatile uint16_t*)(0x428425ACUL)) +#define bFM4_USB0_EP2C_DMAE *((volatile uint16_t*)(0x428425ACUL)) +#define bFM_USB0_EP2C_DIR *((volatile uint16_t*)(0x428425B0UL)) +#define bFM4_USB0_EP2C_DIR *((volatile uint16_t*)(0x428425B0UL)) +#define bFM_USB0_EP2C_EPEN *((volatile uint16_t*)(0x428425BCUL)) +#define bFM4_USB0_EP2C_EPEN *((volatile uint16_t*)(0x428425BCUL)) + +#define bFM_USB0_EP2S_SPK *((volatile uint16_t*)(0x42842A24UL)) +#define bFM4_USB0_EP2S_SPK *((volatile uint16_t*)(0x42842A24UL)) +#define bFM_USB0_EP2S_DRQ *((volatile uint16_t*)(0x42842A28UL)) +#define bFM4_USB0_EP2S_DRQ *((volatile uint16_t*)(0x42842A28UL)) +#define bFM_USB0_EP2S_BUSY *((volatile uint16_t*)(0x42842A2CUL)) +#define bFM4_USB0_EP2S_BUSY *((volatile uint16_t*)(0x42842A2CUL)) +#define bFM_USB0_EP2S_SPKIE *((volatile uint16_t*)(0x42842A34UL)) +#define bFM4_USB0_EP2S_SPKIE *((volatile uint16_t*)(0x42842A34UL)) +#define bFM_USB0_EP2S_DRQIE *((volatile uint16_t*)(0x42842A38UL)) +#define bFM4_USB0_EP2S_DRQIE *((volatile uint16_t*)(0x42842A38UL)) +#define bFM_USB0_EP2S_BFINI *((volatile uint16_t*)(0x42842A3CUL)) +#define bFM4_USB0_EP2S_BFINI *((volatile uint16_t*)(0x42842A3CUL)) + +#define bFM_USB0_EP3C_STAL *((volatile uint16_t*)(0x42842624UL)) +#define bFM4_USB0_EP3C_STAL *((volatile uint16_t*)(0x42842624UL)) +#define bFM_USB0_EP3C_NULE *((volatile uint16_t*)(0x42842628UL)) +#define bFM4_USB0_EP3C_NULE *((volatile uint16_t*)(0x42842628UL)) +#define bFM_USB0_EP3C_DMAE *((volatile uint16_t*)(0x4284262CUL)) +#define bFM4_USB0_EP3C_DMAE *((volatile uint16_t*)(0x4284262CUL)) +#define bFM_USB0_EP3C_DIR *((volatile uint16_t*)(0x42842630UL)) +#define bFM4_USB0_EP3C_DIR *((volatile uint16_t*)(0x42842630UL)) +#define bFM_USB0_EP3C_EPEN *((volatile uint16_t*)(0x4284263CUL)) +#define bFM4_USB0_EP3C_EPEN *((volatile uint16_t*)(0x4284263CUL)) + +#define bFM_USB0_EP3S_SPK *((volatile uint16_t*)(0x42842AA4UL)) +#define bFM4_USB0_EP3S_SPK *((volatile uint16_t*)(0x42842AA4UL)) +#define bFM_USB0_EP3S_DRQ *((volatile uint16_t*)(0x42842AA8UL)) +#define bFM4_USB0_EP3S_DRQ *((volatile uint16_t*)(0x42842AA8UL)) +#define bFM_USB0_EP3S_BUSY *((volatile uint16_t*)(0x42842AACUL)) +#define bFM4_USB0_EP3S_BUSY *((volatile uint16_t*)(0x42842AACUL)) +#define bFM_USB0_EP3S_SPKIE *((volatile uint16_t*)(0x42842AB4UL)) +#define bFM4_USB0_EP3S_SPKIE *((volatile uint16_t*)(0x42842AB4UL)) +#define bFM_USB0_EP3S_DRQIE *((volatile uint16_t*)(0x42842AB8UL)) +#define bFM4_USB0_EP3S_DRQIE *((volatile uint16_t*)(0x42842AB8UL)) +#define bFM_USB0_EP3S_BFINI *((volatile uint16_t*)(0x42842ABCUL)) +#define bFM4_USB0_EP3S_BFINI *((volatile uint16_t*)(0x42842ABCUL)) + +#define bFM_USB0_EP4C_STAL *((volatile uint16_t*)(0x428426A4UL)) +#define bFM4_USB0_EP4C_STAL *((volatile uint16_t*)(0x428426A4UL)) +#define bFM_USB0_EP4C_NULE *((volatile uint16_t*)(0x428426A8UL)) +#define bFM4_USB0_EP4C_NULE *((volatile uint16_t*)(0x428426A8UL)) +#define bFM_USB0_EP4C_DMAE *((volatile uint16_t*)(0x428426ACUL)) +#define bFM4_USB0_EP4C_DMAE *((volatile uint16_t*)(0x428426ACUL)) +#define bFM_USB0_EP4C_DIR *((volatile uint16_t*)(0x428426B0UL)) +#define bFM4_USB0_EP4C_DIR *((volatile uint16_t*)(0x428426B0UL)) +#define bFM_USB0_EP4C_EPEN *((volatile uint16_t*)(0x428426BCUL)) +#define bFM4_USB0_EP4C_EPEN *((volatile uint16_t*)(0x428426BCUL)) + +#define bFM_USB0_EP4S_SPK *((volatile uint16_t*)(0x42842B24UL)) +#define bFM4_USB0_EP4S_SPK *((volatile uint16_t*)(0x42842B24UL)) +#define bFM_USB0_EP4S_DRQ *((volatile uint16_t*)(0x42842B28UL)) +#define bFM4_USB0_EP4S_DRQ *((volatile uint16_t*)(0x42842B28UL)) +#define bFM_USB0_EP4S_BUSY *((volatile uint16_t*)(0x42842B2CUL)) +#define bFM4_USB0_EP4S_BUSY *((volatile uint16_t*)(0x42842B2CUL)) +#define bFM_USB0_EP4S_SPKIE *((volatile uint16_t*)(0x42842B34UL)) +#define bFM4_USB0_EP4S_SPKIE *((volatile uint16_t*)(0x42842B34UL)) +#define bFM_USB0_EP4S_DRQIE *((volatile uint16_t*)(0x42842B38UL)) +#define bFM4_USB0_EP4S_DRQIE *((volatile uint16_t*)(0x42842B38UL)) +#define bFM_USB0_EP4S_BFINI *((volatile uint16_t*)(0x42842B3CUL)) +#define bFM4_USB0_EP4S_BFINI *((volatile uint16_t*)(0x42842B3CUL)) + +#define bFM_USB0_EP5C_STAL *((volatile uint16_t*)(0x42842724UL)) +#define bFM4_USB0_EP5C_STAL *((volatile uint16_t*)(0x42842724UL)) +#define bFM_USB0_EP5C_NULE *((volatile uint16_t*)(0x42842728UL)) +#define bFM4_USB0_EP5C_NULE *((volatile uint16_t*)(0x42842728UL)) +#define bFM_USB0_EP5C_DMAE *((volatile uint16_t*)(0x4284272CUL)) +#define bFM4_USB0_EP5C_DMAE *((volatile uint16_t*)(0x4284272CUL)) +#define bFM_USB0_EP5C_DIR *((volatile uint16_t*)(0x42842730UL)) +#define bFM4_USB0_EP5C_DIR *((volatile uint16_t*)(0x42842730UL)) +#define bFM_USB0_EP5C_EPEN *((volatile uint16_t*)(0x4284273CUL)) +#define bFM4_USB0_EP5C_EPEN *((volatile uint16_t*)(0x4284273CUL)) + +#define bFM_USB0_EP5S_SPK *((volatile uint16_t*)(0x42842BA4UL)) +#define bFM4_USB0_EP5S_SPK *((volatile uint16_t*)(0x42842BA4UL)) +#define bFM_USB0_EP5S_DRQ *((volatile uint16_t*)(0x42842BA8UL)) +#define bFM4_USB0_EP5S_DRQ *((volatile uint16_t*)(0x42842BA8UL)) +#define bFM_USB0_EP5S_BUSY *((volatile uint16_t*)(0x42842BACUL)) +#define bFM4_USB0_EP5S_BUSY *((volatile uint16_t*)(0x42842BACUL)) +#define bFM_USB0_EP5S_SPKIE *((volatile uint16_t*)(0x42842BB4UL)) +#define bFM4_USB0_EP5S_SPKIE *((volatile uint16_t*)(0x42842BB4UL)) +#define bFM_USB0_EP5S_DRQIE *((volatile uint16_t*)(0x42842BB8UL)) +#define bFM4_USB0_EP5S_DRQIE *((volatile uint16_t*)(0x42842BB8UL)) +#define bFM_USB0_EP5S_BFINI *((volatile uint16_t*)(0x42842BBCUL)) +#define bFM4_USB0_EP5S_BFINI *((volatile uint16_t*)(0x42842BBCUL)) + +#define bFM_USB0_HCNT_HOST *((volatile uint8_t *)(0x42842000UL)) +#define bFM4_USB0_HCNT_HOST *((volatile uint8_t *)(0x42842000UL)) +#define bFM_USB0_HCNT_URST *((volatile uint8_t *)(0x42842004UL)) +#define bFM4_USB0_HCNT_URST *((volatile uint8_t *)(0x42842004UL)) +#define bFM_USB0_HCNT_SOFIRE *((volatile uint8_t *)(0x42842008UL)) +#define bFM4_USB0_HCNT_SOFIRE *((volatile uint8_t *)(0x42842008UL)) +#define bFM_USB0_HCNT_DIRE *((volatile uint8_t *)(0x4284200CUL)) +#define bFM4_USB0_HCNT_DIRE *((volatile uint8_t *)(0x4284200CUL)) +#define bFM_USB0_HCNT_CNNIRE *((volatile uint8_t *)(0x42842010UL)) +#define bFM4_USB0_HCNT_CNNIRE *((volatile uint8_t *)(0x42842010UL)) +#define bFM_USB0_HCNT_CMPIRE *((volatile uint8_t *)(0x42842014UL)) +#define bFM4_USB0_HCNT_CMPIRE *((volatile uint8_t *)(0x42842014UL)) +#define bFM_USB0_HCNT_URIRE *((volatile uint8_t *)(0x42842018UL)) +#define bFM4_USB0_HCNT_URIRE *((volatile uint8_t *)(0x42842018UL)) +#define bFM_USB0_HCNT_RWKIRE *((volatile uint8_t *)(0x4284201CUL)) +#define bFM4_USB0_HCNT_RWKIRE *((volatile uint8_t *)(0x4284201CUL)) +#define bFM_USB0_HCNT_RETRY *((volatile uint8_t *)(0x42842020UL)) +#define bFM4_USB0_HCNT_RETRY *((volatile uint8_t *)(0x42842020UL)) +#define bFM_USB0_HCNT_CANCEL *((volatile uint8_t *)(0x42842024UL)) +#define bFM4_USB0_HCNT_CANCEL *((volatile uint8_t *)(0x42842024UL)) +#define bFM_USB0_HCNT_SOFSTEP *((volatile uint8_t *)(0x42842028UL)) +#define bFM4_USB0_HCNT_SOFSTEP *((volatile uint8_t *)(0x42842028UL)) + +#define bFM_USB0_HERR_STUFF *((volatile uint8_t *)(0x428420A8UL)) +#define bFM4_USB0_HERR_STUFF *((volatile uint8_t *)(0x428420A8UL)) +#define bFM_USB0_HERR_TGERR *((volatile uint8_t *)(0x428420ACUL)) +#define bFM4_USB0_HERR_TGERR *((volatile uint8_t *)(0x428420ACUL)) +#define bFM_USB0_HERR_CRC *((volatile uint8_t *)(0x428420B0UL)) +#define bFM4_USB0_HERR_CRC *((volatile uint8_t *)(0x428420B0UL)) +#define bFM_USB0_HERR_TOUT *((volatile uint8_t *)(0x428420B4UL)) +#define bFM4_USB0_HERR_TOUT *((volatile uint8_t *)(0x428420B4UL)) +#define bFM_USB0_HERR_RERR *((volatile uint8_t *)(0x428420B8UL)) +#define bFM4_USB0_HERR_RERR *((volatile uint8_t *)(0x428420B8UL)) +#define bFM_USB0_HERR_LSTSOF *((volatile uint8_t *)(0x428420BCUL)) +#define bFM4_USB0_HERR_LSTSOF *((volatile uint8_t *)(0x428420BCUL)) + +#define bFM_USB0_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42842080UL)) +#define bFM4_USB0_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42842080UL)) +#define bFM_USB0_HIRQ_DIRQ *((volatile uint8_t *)(0x42842084UL)) +#define bFM4_USB0_HIRQ_DIRQ *((volatile uint8_t *)(0x42842084UL)) +#define bFM_USB0_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42842088UL)) +#define bFM4_USB0_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42842088UL)) +#define bFM_USB0_HIRQ_CMPIRQ *((volatile uint8_t *)(0x4284208CUL)) +#define bFM4_USB0_HIRQ_CMPIRQ *((volatile uint8_t *)(0x4284208CUL)) +#define bFM_USB0_HIRQ_URIRQ *((volatile uint8_t *)(0x42842090UL)) +#define bFM4_USB0_HIRQ_URIRQ *((volatile uint8_t *)(0x42842090UL)) +#define bFM_USB0_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42842094UL)) +#define bFM4_USB0_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42842094UL)) +#define bFM_USB0_HIRQ_TCAN *((volatile uint8_t *)(0x4284209CUL)) +#define bFM4_USB0_HIRQ_TCAN *((volatile uint8_t *)(0x4284209CUL)) + +#define bFM_USB0_HSTATE_CSTAT *((volatile uint8_t *)(0x42842100UL)) +#define bFM4_USB0_HSTATE_CSTAT *((volatile uint8_t *)(0x42842100UL)) +#define bFM_USB0_HSTATE_TMODE *((volatile uint8_t *)(0x42842104UL)) +#define bFM4_USB0_HSTATE_TMODE *((volatile uint8_t *)(0x42842104UL)) +#define bFM_USB0_HSTATE_SUSP *((volatile uint8_t *)(0x42842108UL)) +#define bFM4_USB0_HSTATE_SUSP *((volatile uint8_t *)(0x42842108UL)) +#define bFM_USB0_HSTATE_SOFBUSY *((volatile uint8_t *)(0x4284210CUL)) +#define bFM4_USB0_HSTATE_SOFBUSY *((volatile uint8_t *)(0x4284210CUL)) +#define bFM_USB0_HSTATE_CLKSEL *((volatile uint8_t *)(0x42842110UL)) +#define bFM4_USB0_HSTATE_CLKSEL *((volatile uint8_t *)(0x42842110UL)) +#define bFM_USB0_HSTATE_ALIVE *((volatile uint8_t *)(0x42842114UL)) +#define bFM4_USB0_HSTATE_ALIVE *((volatile uint8_t *)(0x42842114UL)) + +#define bFM_USB0_HTOKEN_TGGL *((volatile uint8_t *)(0x4284239CUL)) +#define bFM4_USB0_HTOKEN_TGGL *((volatile uint8_t *)(0x4284239CUL)) + +#define bFM_USB0_UDCC_PWC *((volatile uint8_t *)(0x42842400UL)) +#define bFM4_USB0_UDCC_PWC *((volatile uint8_t *)(0x42842400UL)) +#define bFM_USB0_UDCC_RFBK *((volatile uint8_t *)(0x42842404UL)) +#define bFM4_USB0_UDCC_RFBK *((volatile uint8_t *)(0x42842404UL)) +#define bFM_USB0_UDCC_STALCLREN *((volatile uint8_t *)(0x4284240CUL)) +#define bFM4_USB0_UDCC_STALCLREN *((volatile uint8_t *)(0x4284240CUL)) +#define bFM_USB0_UDCC_USTP *((volatile uint8_t *)(0x42842410UL)) +#define bFM4_USB0_UDCC_USTP *((volatile uint8_t *)(0x42842410UL)) +#define bFM_USB0_UDCC_HCONX *((volatile uint8_t *)(0x42842414UL)) +#define bFM4_USB0_UDCC_HCONX *((volatile uint8_t *)(0x42842414UL)) +#define bFM_USB0_UDCC_RESUM *((volatile uint8_t *)(0x42842418UL)) +#define bFM4_USB0_UDCC_RESUM *((volatile uint8_t *)(0x42842418UL)) +#define bFM_USB0_UDCC_RST *((volatile uint8_t *)(0x4284241CUL)) +#define bFM4_USB0_UDCC_RST *((volatile uint8_t *)(0x4284241CUL)) + +#define bFM_USB0_UDCIE_CONFIE *((volatile uint8_t *)(0x42842820UL)) +#define bFM4_USB0_UDCIE_CONFIE *((volatile uint8_t *)(0x42842820UL)) +#define bFM_USB0_UDCIE_CONFN *((volatile uint8_t *)(0x42842824UL)) +#define bFM4_USB0_UDCIE_CONFN *((volatile uint8_t *)(0x42842824UL)) +#define bFM_USB0_UDCIE_WKUPIE *((volatile uint8_t *)(0x42842828UL)) +#define bFM4_USB0_UDCIE_WKUPIE *((volatile uint8_t *)(0x42842828UL)) +#define bFM_USB0_UDCIE_BRSTIE *((volatile uint8_t *)(0x4284282CUL)) +#define bFM4_USB0_UDCIE_BRSTIE *((volatile uint8_t *)(0x4284282CUL)) +#define bFM_USB0_UDCIE_SOFIE *((volatile uint8_t *)(0x42842830UL)) +#define bFM4_USB0_UDCIE_SOFIE *((volatile uint8_t *)(0x42842830UL)) +#define bFM_USB0_UDCIE_SUSPIE *((volatile uint8_t *)(0x42842834UL)) +#define bFM4_USB0_UDCIE_SUSPIE *((volatile uint8_t *)(0x42842834UL)) + +#define bFM_USB0_UDCS_CONF *((volatile uint8_t *)(0x42842800UL)) +#define bFM4_USB0_UDCS_CONF *((volatile uint8_t *)(0x42842800UL)) +#define bFM_USB0_UDCS_SETP *((volatile uint8_t *)(0x42842804UL)) +#define bFM4_USB0_UDCS_SETP *((volatile uint8_t *)(0x42842804UL)) +#define bFM_USB0_UDCS_WKUP *((volatile uint8_t *)(0x42842808UL)) +#define bFM4_USB0_UDCS_WKUP *((volatile uint8_t *)(0x42842808UL)) +#define bFM_USB0_UDCS_BRST *((volatile uint8_t *)(0x4284280CUL)) +#define bFM4_USB0_UDCS_BRST *((volatile uint8_t *)(0x4284280CUL)) +#define bFM_USB0_UDCS_SOF *((volatile uint8_t *)(0x42842810UL)) +#define bFM4_USB0_UDCS_SOF *((volatile uint8_t *)(0x42842810UL)) +#define bFM_USB0_UDCS_SUSP *((volatile uint8_t *)(0x42842814UL)) +#define bFM4_USB0_UDCS_SUSP *((volatile uint8_t *)(0x42842814UL)) + + +/******************************************************************************* +* USB Registers USB1 +* Bitband Section +*******************************************************************************/ +#define bFM_USB1_EP0C_STAL *((volatile uint16_t*)(0x42A844A4UL)) +#define bFM4_USB1_EP0C_STAL *((volatile uint16_t*)(0x42A844A4UL)) + +#define bFM_USB1_EP0IS_DRQI *((volatile uint16_t*)(0x42A848A8UL)) +#define bFM4_USB1_EP0IS_DRQI *((volatile uint16_t*)(0x42A848A8UL)) +#define bFM_USB1_EP0IS_DRQIIE *((volatile uint16_t*)(0x42A848B8UL)) +#define bFM4_USB1_EP0IS_DRQIIE *((volatile uint16_t*)(0x42A848B8UL)) +#define bFM_USB1_EP0IS_BFINI *((volatile uint16_t*)(0x42A848BCUL)) +#define bFM4_USB1_EP0IS_BFINI *((volatile uint16_t*)(0x42A848BCUL)) + +#define bFM_USB1_EP0OS_SPK *((volatile uint16_t*)(0x42A84924UL)) +#define bFM4_USB1_EP0OS_SPK *((volatile uint16_t*)(0x42A84924UL)) +#define bFM_USB1_EP0OS_DRQO *((volatile uint16_t*)(0x42A84928UL)) +#define bFM4_USB1_EP0OS_DRQO *((volatile uint16_t*)(0x42A84928UL)) +#define bFM_USB1_EP0OS_SPKIE *((volatile uint16_t*)(0x42A84934UL)) +#define bFM4_USB1_EP0OS_SPKIE *((volatile uint16_t*)(0x42A84934UL)) +#define bFM_USB1_EP0OS_DRQOIE *((volatile uint16_t*)(0x42A84938UL)) +#define bFM4_USB1_EP0OS_DRQOIE *((volatile uint16_t*)(0x42A84938UL)) +#define bFM_USB1_EP0OS_BFINI *((volatile uint16_t*)(0x42A8493CUL)) +#define bFM4_USB1_EP0OS_BFINI *((volatile uint16_t*)(0x42A8493CUL)) + +#define bFM_USB1_EP1C_STAL *((volatile uint16_t*)(0x42A84524UL)) +#define bFM4_USB1_EP1C_STAL *((volatile uint16_t*)(0x42A84524UL)) +#define bFM_USB1_EP1C_NULE *((volatile uint16_t*)(0x42A84528UL)) +#define bFM4_USB1_EP1C_NULE *((volatile uint16_t*)(0x42A84528UL)) +#define bFM_USB1_EP1C_DMAE *((volatile uint16_t*)(0x42A8452CUL)) +#define bFM4_USB1_EP1C_DMAE *((volatile uint16_t*)(0x42A8452CUL)) +#define bFM_USB1_EP1C_DIR *((volatile uint16_t*)(0x42A84530UL)) +#define bFM4_USB1_EP1C_DIR *((volatile uint16_t*)(0x42A84530UL)) +#define bFM_USB1_EP1C_EPEN *((volatile uint16_t*)(0x42A8453CUL)) +#define bFM4_USB1_EP1C_EPEN *((volatile uint16_t*)(0x42A8453CUL)) + +#define bFM_USB1_EP1S_SPK *((volatile uint16_t*)(0x42A849A4UL)) +#define bFM4_USB1_EP1S_SPK *((volatile uint16_t*)(0x42A849A4UL)) +#define bFM_USB1_EP1S_DRQ *((volatile uint16_t*)(0x42A849A8UL)) +#define bFM4_USB1_EP1S_DRQ *((volatile uint16_t*)(0x42A849A8UL)) +#define bFM_USB1_EP1S_BUSY *((volatile uint16_t*)(0x42A849ACUL)) +#define bFM4_USB1_EP1S_BUSY *((volatile uint16_t*)(0x42A849ACUL)) +#define bFM_USB1_EP1S_SPKIE *((volatile uint16_t*)(0x42A849B4UL)) +#define bFM4_USB1_EP1S_SPKIE *((volatile uint16_t*)(0x42A849B4UL)) +#define bFM_USB1_EP1S_DRQIE *((volatile uint16_t*)(0x42A849B8UL)) +#define bFM4_USB1_EP1S_DRQIE *((volatile uint16_t*)(0x42A849B8UL)) +#define bFM_USB1_EP1S_BFINI *((volatile uint16_t*)(0x42A849BCUL)) +#define bFM4_USB1_EP1S_BFINI *((volatile uint16_t*)(0x42A849BCUL)) + +#define bFM_USB1_EP2C_STAL *((volatile uint16_t*)(0x42A845A4UL)) +#define bFM4_USB1_EP2C_STAL *((volatile uint16_t*)(0x42A845A4UL)) +#define bFM_USB1_EP2C_NULE *((volatile uint16_t*)(0x42A845A8UL)) +#define bFM4_USB1_EP2C_NULE *((volatile uint16_t*)(0x42A845A8UL)) +#define bFM_USB1_EP2C_DMAE *((volatile uint16_t*)(0x42A845ACUL)) +#define bFM4_USB1_EP2C_DMAE *((volatile uint16_t*)(0x42A845ACUL)) +#define bFM_USB1_EP2C_DIR *((volatile uint16_t*)(0x42A845B0UL)) +#define bFM4_USB1_EP2C_DIR *((volatile uint16_t*)(0x42A845B0UL)) +#define bFM_USB1_EP2C_EPEN *((volatile uint16_t*)(0x42A845BCUL)) +#define bFM4_USB1_EP2C_EPEN *((volatile uint16_t*)(0x42A845BCUL)) + +#define bFM_USB1_EP2S_SPK *((volatile uint16_t*)(0x42A84A24UL)) +#define bFM4_USB1_EP2S_SPK *((volatile uint16_t*)(0x42A84A24UL)) +#define bFM_USB1_EP2S_DRQ *((volatile uint16_t*)(0x42A84A28UL)) +#define bFM4_USB1_EP2S_DRQ *((volatile uint16_t*)(0x42A84A28UL)) +#define bFM_USB1_EP2S_BUSY *((volatile uint16_t*)(0x42A84A2CUL)) +#define bFM4_USB1_EP2S_BUSY *((volatile uint16_t*)(0x42A84A2CUL)) +#define bFM_USB1_EP2S_SPKIE *((volatile uint16_t*)(0x42A84A34UL)) +#define bFM4_USB1_EP2S_SPKIE *((volatile uint16_t*)(0x42A84A34UL)) +#define bFM_USB1_EP2S_DRQIE *((volatile uint16_t*)(0x42A84A38UL)) +#define bFM4_USB1_EP2S_DRQIE *((volatile uint16_t*)(0x42A84A38UL)) +#define bFM_USB1_EP2S_BFINI *((volatile uint16_t*)(0x42A84A3CUL)) +#define bFM4_USB1_EP2S_BFINI *((volatile uint16_t*)(0x42A84A3CUL)) + +#define bFM_USB1_EP3C_STAL *((volatile uint16_t*)(0x42A84624UL)) +#define bFM4_USB1_EP3C_STAL *((volatile uint16_t*)(0x42A84624UL)) +#define bFM_USB1_EP3C_NULE *((volatile uint16_t*)(0x42A84628UL)) +#define bFM4_USB1_EP3C_NULE *((volatile uint16_t*)(0x42A84628UL)) +#define bFM_USB1_EP3C_DMAE *((volatile uint16_t*)(0x42A8462CUL)) +#define bFM4_USB1_EP3C_DMAE *((volatile uint16_t*)(0x42A8462CUL)) +#define bFM_USB1_EP3C_DIR *((volatile uint16_t*)(0x42A84630UL)) +#define bFM4_USB1_EP3C_DIR *((volatile uint16_t*)(0x42A84630UL)) +#define bFM_USB1_EP3C_EPEN *((volatile uint16_t*)(0x42A8463CUL)) +#define bFM4_USB1_EP3C_EPEN *((volatile uint16_t*)(0x42A8463CUL)) + +#define bFM_USB1_EP3S_SPK *((volatile uint16_t*)(0x42A84AA4UL)) +#define bFM4_USB1_EP3S_SPK *((volatile uint16_t*)(0x42A84AA4UL)) +#define bFM_USB1_EP3S_DRQ *((volatile uint16_t*)(0x42A84AA8UL)) +#define bFM4_USB1_EP3S_DRQ *((volatile uint16_t*)(0x42A84AA8UL)) +#define bFM_USB1_EP3S_BUSY *((volatile uint16_t*)(0x42A84AACUL)) +#define bFM4_USB1_EP3S_BUSY *((volatile uint16_t*)(0x42A84AACUL)) +#define bFM_USB1_EP3S_SPKIE *((volatile uint16_t*)(0x42A84AB4UL)) +#define bFM4_USB1_EP3S_SPKIE *((volatile uint16_t*)(0x42A84AB4UL)) +#define bFM_USB1_EP3S_DRQIE *((volatile uint16_t*)(0x42A84AB8UL)) +#define bFM4_USB1_EP3S_DRQIE *((volatile uint16_t*)(0x42A84AB8UL)) +#define bFM_USB1_EP3S_BFINI *((volatile uint16_t*)(0x42A84ABCUL)) +#define bFM4_USB1_EP3S_BFINI *((volatile uint16_t*)(0x42A84ABCUL)) + +#define bFM_USB1_EP4C_STAL *((volatile uint16_t*)(0x42A846A4UL)) +#define bFM4_USB1_EP4C_STAL *((volatile uint16_t*)(0x42A846A4UL)) +#define bFM_USB1_EP4C_NULE *((volatile uint16_t*)(0x42A846A8UL)) +#define bFM4_USB1_EP4C_NULE *((volatile uint16_t*)(0x42A846A8UL)) +#define bFM_USB1_EP4C_DMAE *((volatile uint16_t*)(0x42A846ACUL)) +#define bFM4_USB1_EP4C_DMAE *((volatile uint16_t*)(0x42A846ACUL)) +#define bFM_USB1_EP4C_DIR *((volatile uint16_t*)(0x42A846B0UL)) +#define bFM4_USB1_EP4C_DIR *((volatile uint16_t*)(0x42A846B0UL)) +#define bFM_USB1_EP4C_EPEN *((volatile uint16_t*)(0x42A846BCUL)) +#define bFM4_USB1_EP4C_EPEN *((volatile uint16_t*)(0x42A846BCUL)) + +#define bFM_USB1_EP4S_SPK *((volatile uint16_t*)(0x42A84B24UL)) +#define bFM4_USB1_EP4S_SPK *((volatile uint16_t*)(0x42A84B24UL)) +#define bFM_USB1_EP4S_DRQ *((volatile uint16_t*)(0x42A84B28UL)) +#define bFM4_USB1_EP4S_DRQ *((volatile uint16_t*)(0x42A84B28UL)) +#define bFM_USB1_EP4S_BUSY *((volatile uint16_t*)(0x42A84B2CUL)) +#define bFM4_USB1_EP4S_BUSY *((volatile uint16_t*)(0x42A84B2CUL)) +#define bFM_USB1_EP4S_SPKIE *((volatile uint16_t*)(0x42A84B34UL)) +#define bFM4_USB1_EP4S_SPKIE *((volatile uint16_t*)(0x42A84B34UL)) +#define bFM_USB1_EP4S_DRQIE *((volatile uint16_t*)(0x42A84B38UL)) +#define bFM4_USB1_EP4S_DRQIE *((volatile uint16_t*)(0x42A84B38UL)) +#define bFM_USB1_EP4S_BFINI *((volatile uint16_t*)(0x42A84B3CUL)) +#define bFM4_USB1_EP4S_BFINI *((volatile uint16_t*)(0x42A84B3CUL)) + +#define bFM_USB1_EP5C_STAL *((volatile uint16_t*)(0x42A84724UL)) +#define bFM4_USB1_EP5C_STAL *((volatile uint16_t*)(0x42A84724UL)) +#define bFM_USB1_EP5C_NULE *((volatile uint16_t*)(0x42A84728UL)) +#define bFM4_USB1_EP5C_NULE *((volatile uint16_t*)(0x42A84728UL)) +#define bFM_USB1_EP5C_DMAE *((volatile uint16_t*)(0x42A8472CUL)) +#define bFM4_USB1_EP5C_DMAE *((volatile uint16_t*)(0x42A8472CUL)) +#define bFM_USB1_EP5C_DIR *((volatile uint16_t*)(0x42A84730UL)) +#define bFM4_USB1_EP5C_DIR *((volatile uint16_t*)(0x42A84730UL)) +#define bFM_USB1_EP5C_EPEN *((volatile uint16_t*)(0x42A8473CUL)) +#define bFM4_USB1_EP5C_EPEN *((volatile uint16_t*)(0x42A8473CUL)) + +#define bFM_USB1_EP5S_SPK *((volatile uint16_t*)(0x42A84BA4UL)) +#define bFM4_USB1_EP5S_SPK *((volatile uint16_t*)(0x42A84BA4UL)) +#define bFM_USB1_EP5S_DRQ *((volatile uint16_t*)(0x42A84BA8UL)) +#define bFM4_USB1_EP5S_DRQ *((volatile uint16_t*)(0x42A84BA8UL)) +#define bFM_USB1_EP5S_BUSY *((volatile uint16_t*)(0x42A84BACUL)) +#define bFM4_USB1_EP5S_BUSY *((volatile uint16_t*)(0x42A84BACUL)) +#define bFM_USB1_EP5S_SPKIE *((volatile uint16_t*)(0x42A84BB4UL)) +#define bFM4_USB1_EP5S_SPKIE *((volatile uint16_t*)(0x42A84BB4UL)) +#define bFM_USB1_EP5S_DRQIE *((volatile uint16_t*)(0x42A84BB8UL)) +#define bFM4_USB1_EP5S_DRQIE *((volatile uint16_t*)(0x42A84BB8UL)) +#define bFM_USB1_EP5S_BFINI *((volatile uint16_t*)(0x42A84BBCUL)) +#define bFM4_USB1_EP5S_BFINI *((volatile uint16_t*)(0x42A84BBCUL)) + +#define bFM_USB1_HCNT_HOST *((volatile uint8_t *)(0x42A84000UL)) +#define bFM4_USB1_HCNT_HOST *((volatile uint8_t *)(0x42A84000UL)) +#define bFM_USB1_HCNT_URST *((volatile uint8_t *)(0x42A84004UL)) +#define bFM4_USB1_HCNT_URST *((volatile uint8_t *)(0x42A84004UL)) +#define bFM_USB1_HCNT_SOFIRE *((volatile uint8_t *)(0x42A84008UL)) +#define bFM4_USB1_HCNT_SOFIRE *((volatile uint8_t *)(0x42A84008UL)) +#define bFM_USB1_HCNT_DIRE *((volatile uint8_t *)(0x42A8400CUL)) +#define bFM4_USB1_HCNT_DIRE *((volatile uint8_t *)(0x42A8400CUL)) +#define bFM_USB1_HCNT_CNNIRE *((volatile uint8_t *)(0x42A84010UL)) +#define bFM4_USB1_HCNT_CNNIRE *((volatile uint8_t *)(0x42A84010UL)) +#define bFM_USB1_HCNT_CMPIRE *((volatile uint8_t *)(0x42A84014UL)) +#define bFM4_USB1_HCNT_CMPIRE *((volatile uint8_t *)(0x42A84014UL)) +#define bFM_USB1_HCNT_URIRE *((volatile uint8_t *)(0x42A84018UL)) +#define bFM4_USB1_HCNT_URIRE *((volatile uint8_t *)(0x42A84018UL)) +#define bFM_USB1_HCNT_RWKIRE *((volatile uint8_t *)(0x42A8401CUL)) +#define bFM4_USB1_HCNT_RWKIRE *((volatile uint8_t *)(0x42A8401CUL)) +#define bFM_USB1_HCNT_RETRY *((volatile uint8_t *)(0x42A84020UL)) +#define bFM4_USB1_HCNT_RETRY *((volatile uint8_t *)(0x42A84020UL)) +#define bFM_USB1_HCNT_CANCEL *((volatile uint8_t *)(0x42A84024UL)) +#define bFM4_USB1_HCNT_CANCEL *((volatile uint8_t *)(0x42A84024UL)) +#define bFM_USB1_HCNT_SOFSTEP *((volatile uint8_t *)(0x42A84028UL)) +#define bFM4_USB1_HCNT_SOFSTEP *((volatile uint8_t *)(0x42A84028UL)) + +#define bFM_USB1_HERR_STUFF *((volatile uint8_t *)(0x42A840A8UL)) +#define bFM4_USB1_HERR_STUFF *((volatile uint8_t *)(0x42A840A8UL)) +#define bFM_USB1_HERR_TGERR *((volatile uint8_t *)(0x42A840ACUL)) +#define bFM4_USB1_HERR_TGERR *((volatile uint8_t *)(0x42A840ACUL)) +#define bFM_USB1_HERR_CRC *((volatile uint8_t *)(0x42A840B0UL)) +#define bFM4_USB1_HERR_CRC *((volatile uint8_t *)(0x42A840B0UL)) +#define bFM_USB1_HERR_TOUT *((volatile uint8_t *)(0x42A840B4UL)) +#define bFM4_USB1_HERR_TOUT *((volatile uint8_t *)(0x42A840B4UL)) +#define bFM_USB1_HERR_RERR *((volatile uint8_t *)(0x42A840B8UL)) +#define bFM4_USB1_HERR_RERR *((volatile uint8_t *)(0x42A840B8UL)) +#define bFM_USB1_HERR_LSTSOF *((volatile uint8_t *)(0x42A840BCUL)) +#define bFM4_USB1_HERR_LSTSOF *((volatile uint8_t *)(0x42A840BCUL)) + +#define bFM_USB1_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42A84080UL)) +#define bFM4_USB1_HIRQ_SOFIRQ *((volatile uint8_t *)(0x42A84080UL)) +#define bFM_USB1_HIRQ_DIRQ *((volatile uint8_t *)(0x42A84084UL)) +#define bFM4_USB1_HIRQ_DIRQ *((volatile uint8_t *)(0x42A84084UL)) +#define bFM_USB1_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42A84088UL)) +#define bFM4_USB1_HIRQ_CNNIRQ *((volatile uint8_t *)(0x42A84088UL)) +#define bFM_USB1_HIRQ_CMPIRQ *((volatile uint8_t *)(0x42A8408CUL)) +#define bFM4_USB1_HIRQ_CMPIRQ *((volatile uint8_t *)(0x42A8408CUL)) +#define bFM_USB1_HIRQ_URIRQ *((volatile uint8_t *)(0x42A84090UL)) +#define bFM4_USB1_HIRQ_URIRQ *((volatile uint8_t *)(0x42A84090UL)) +#define bFM_USB1_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42A84094UL)) +#define bFM4_USB1_HIRQ_RWKIRQ *((volatile uint8_t *)(0x42A84094UL)) +#define bFM_USB1_HIRQ_TCAN *((volatile uint8_t *)(0x42A8409CUL)) +#define bFM4_USB1_HIRQ_TCAN *((volatile uint8_t *)(0x42A8409CUL)) + +#define bFM_USB1_HSTATE_CSTAT *((volatile uint8_t *)(0x42A84100UL)) +#define bFM4_USB1_HSTATE_CSTAT *((volatile uint8_t *)(0x42A84100UL)) +#define bFM_USB1_HSTATE_TMODE *((volatile uint8_t *)(0x42A84104UL)) +#define bFM4_USB1_HSTATE_TMODE *((volatile uint8_t *)(0x42A84104UL)) +#define bFM_USB1_HSTATE_SUSP *((volatile uint8_t *)(0x42A84108UL)) +#define bFM4_USB1_HSTATE_SUSP *((volatile uint8_t *)(0x42A84108UL)) +#define bFM_USB1_HSTATE_SOFBUSY *((volatile uint8_t *)(0x42A8410CUL)) +#define bFM4_USB1_HSTATE_SOFBUSY *((volatile uint8_t *)(0x42A8410CUL)) +#define bFM_USB1_HSTATE_CLKSEL *((volatile uint8_t *)(0x42A84110UL)) +#define bFM4_USB1_HSTATE_CLKSEL *((volatile uint8_t *)(0x42A84110UL)) +#define bFM_USB1_HSTATE_ALIVE *((volatile uint8_t *)(0x42A84114UL)) +#define bFM4_USB1_HSTATE_ALIVE *((volatile uint8_t *)(0x42A84114UL)) + +#define bFM_USB1_HTOKEN_TGGL *((volatile uint8_t *)(0x42A8439CUL)) +#define bFM4_USB1_HTOKEN_TGGL *((volatile uint8_t *)(0x42A8439CUL)) + +#define bFM_USB1_UDCC_PWC *((volatile uint8_t *)(0x42A84400UL)) +#define bFM4_USB1_UDCC_PWC *((volatile uint8_t *)(0x42A84400UL)) +#define bFM_USB1_UDCC_RFBK *((volatile uint8_t *)(0x42A84404UL)) +#define bFM4_USB1_UDCC_RFBK *((volatile uint8_t *)(0x42A84404UL)) +#define bFM_USB1_UDCC_STALCLREN *((volatile uint8_t *)(0x42A8440CUL)) +#define bFM4_USB1_UDCC_STALCLREN *((volatile uint8_t *)(0x42A8440CUL)) +#define bFM_USB1_UDCC_USTP *((volatile uint8_t *)(0x42A84410UL)) +#define bFM4_USB1_UDCC_USTP *((volatile uint8_t *)(0x42A84410UL)) +#define bFM_USB1_UDCC_HCONX *((volatile uint8_t *)(0x42A84414UL)) +#define bFM4_USB1_UDCC_HCONX *((volatile uint8_t *)(0x42A84414UL)) +#define bFM_USB1_UDCC_RESUM *((volatile uint8_t *)(0x42A84418UL)) +#define bFM4_USB1_UDCC_RESUM *((volatile uint8_t *)(0x42A84418UL)) +#define bFM_USB1_UDCC_RST *((volatile uint8_t *)(0x42A8441CUL)) +#define bFM4_USB1_UDCC_RST *((volatile uint8_t *)(0x42A8441CUL)) + +#define bFM_USB1_UDCIE_CONFIE *((volatile uint8_t *)(0x42A84820UL)) +#define bFM4_USB1_UDCIE_CONFIE *((volatile uint8_t *)(0x42A84820UL)) +#define bFM_USB1_UDCIE_CONFN *((volatile uint8_t *)(0x42A84824UL)) +#define bFM4_USB1_UDCIE_CONFN *((volatile uint8_t *)(0x42A84824UL)) +#define bFM_USB1_UDCIE_WKUPIE *((volatile uint8_t *)(0x42A84828UL)) +#define bFM4_USB1_UDCIE_WKUPIE *((volatile uint8_t *)(0x42A84828UL)) +#define bFM_USB1_UDCIE_BRSTIE *((volatile uint8_t *)(0x42A8482CUL)) +#define bFM4_USB1_UDCIE_BRSTIE *((volatile uint8_t *)(0x42A8482CUL)) +#define bFM_USB1_UDCIE_SOFIE *((volatile uint8_t *)(0x42A84830UL)) +#define bFM4_USB1_UDCIE_SOFIE *((volatile uint8_t *)(0x42A84830UL)) +#define bFM_USB1_UDCIE_SUSPIE *((volatile uint8_t *)(0x42A84834UL)) +#define bFM4_USB1_UDCIE_SUSPIE *((volatile uint8_t *)(0x42A84834UL)) + +#define bFM_USB1_UDCS_CONF *((volatile uint8_t *)(0x42A84800UL)) +#define bFM4_USB1_UDCS_CONF *((volatile uint8_t *)(0x42A84800UL)) +#define bFM_USB1_UDCS_SETP *((volatile uint8_t *)(0x42A84804UL)) +#define bFM4_USB1_UDCS_SETP *((volatile uint8_t *)(0x42A84804UL)) +#define bFM_USB1_UDCS_WKUP *((volatile uint8_t *)(0x42A84808UL)) +#define bFM4_USB1_UDCS_WKUP *((volatile uint8_t *)(0x42A84808UL)) +#define bFM_USB1_UDCS_BRST *((volatile uint8_t *)(0x42A8480CUL)) +#define bFM4_USB1_UDCS_BRST *((volatile uint8_t *)(0x42A8480CUL)) +#define bFM_USB1_UDCS_SOF *((volatile uint8_t *)(0x42A84810UL)) +#define bFM4_USB1_UDCS_SOF *((volatile uint8_t *)(0x42A84810UL)) +#define bFM_USB1_UDCS_SUSP *((volatile uint8_t *)(0x42A84814UL)) +#define bFM4_USB1_UDCS_SUSP *((volatile uint8_t *)(0x42A84814UL)) + + +/******************************************************************************* +* USBCLK Registers USBCLK +* Bitband Section +*******************************************************************************/ +#define bFM_USBCLK_UCCR_UCEN0 *((volatile uint8_t *)(0x426C0000UL)) +#define bFM4_USBCLK_UCCR_UCEN0 *((volatile uint8_t *)(0x426C0000UL)) +#define bFM_USBCLK_UCCR_UCSEL *((volatile uint8_t *)(0x426C0004UL)) +#define bFM4_USBCLK_UCCR_UCSEL *((volatile uint8_t *)(0x426C0004UL)) +#define bFM_USBCLK_UCCR_UCEN1 *((volatile uint8_t *)(0x426C000CUL)) +#define bFM4_USBCLK_UCCR_UCEN1 *((volatile uint8_t *)(0x426C000CUL)) + +#define bFM_USBCLK_UP_STR_UPRDY *((volatile uint8_t *)(0x426C0280UL)) +#define bFM4_USBCLK_UP_STR_UPRDY *((volatile uint8_t *)(0x426C0280UL)) + +#define bFM_USBCLK_UPCR1_UPLLEN *((volatile uint8_t *)(0x426C0080UL)) +#define bFM4_USBCLK_UPCR1_UPLLEN *((volatile uint8_t *)(0x426C0080UL)) +#define bFM_USBCLK_UPCR1_UPINC *((volatile uint8_t *)(0x426C0084UL)) +#define bFM4_USBCLK_UPCR1_UPINC *((volatile uint8_t *)(0x426C0084UL)) + +#define bFM_USBCLK_UPINT_CLR_UPCSC *((volatile uint8_t *)(0x426C0380UL)) +#define bFM4_USBCLK_UPINT_CLR_UPCSC *((volatile uint8_t *)(0x426C0380UL)) + +#define bFM_USBCLK_UPINT_ENR_UPCSE *((volatile uint8_t *)(0x426C0300UL)) +#define bFM4_USBCLK_UPINT_ENR_UPCSE *((volatile uint8_t *)(0x426C0300UL)) + +#define bFM_USBCLK_UPINT_STR_UPCSI *((volatile uint8_t *)(0x426C0400UL)) +#define bFM4_USBCLK_UPINT_STR_UPCSI *((volatile uint8_t *)(0x426C0400UL)) + +#define bFM_USBCLK_USBEN0_USBEN0 *((volatile uint8_t *)(0x426C0600UL)) +#define bFM4_USBCLK_USBEN0_USBEN0 *((volatile uint8_t *)(0x426C0600UL)) + +#define bFM_USBCLK_USBEN1_USBEN1 *((volatile uint8_t *)(0x426C0680UL)) +#define bFM4_USBCLK_USBEN1_USBEN1 *((volatile uint8_t *)(0x426C0680UL)) + + +/******************************************************************************* +* WC Registers WC +* Bitband Section +*******************************************************************************/ +#define bFM_WC_CLK_EN_CLK_EN *((volatile uint8_t *)(0x42740280UL)) +#define bFM4_WC_CLK_EN_CLK_EN *((volatile uint8_t *)(0x42740280UL)) +#define bFM_WC_CLK_EN_CLK_EN_R *((volatile uint8_t *)(0x42740284UL)) +#define bFM4_WC_CLK_EN_CLK_EN_R *((volatile uint8_t *)(0x42740284UL)) + +#define bFM_WC_WCCR_WCIF *((volatile uint8_t *)(0x42740040UL)) +#define bFM4_WC_WCCR_WCIF *((volatile uint8_t *)(0x42740040UL)) +#define bFM_WC_WCCR_WCIE *((volatile uint8_t *)(0x42740044UL)) +#define bFM4_WC_WCCR_WCIE *((volatile uint8_t *)(0x42740044UL)) +#define bFM_WC_WCCR_WCOP *((volatile uint8_t *)(0x42740058UL)) +#define bFM4_WC_WCCR_WCOP *((volatile uint8_t *)(0x42740058UL)) +#define bFM_WC_WCCR_WCEN *((volatile uint8_t *)(0x4274005CUL)) +#define bFM4_WC_WCCR_WCEN *((volatile uint8_t *)(0x4274005CUL)) + + +#if defined __cplusplus +} +#endif + +#endif /* _S6E2C5XL_H_ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/system_s6e2c5.h b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/system_s6e2c5.h new file mode 100644 index 0000000000..cc13a29d65 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/ext/CMSIS/S6E2CxAH/system_s6e2c5.h @@ -0,0 +1,753 @@ +/******************************************************************************* +* Copyright (C) 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* +* This software, including source code, documentation and related +* materials ( "Software" ), is owned by Cypress Semiconductor +* Corporation ( "Cypress" ) and is protected by and subject to worldwide +* patent protection (United States and foreign), United States copyright +* laws and international treaty provisions. Therefore, you may use this +* Software only as provided in the license agreement accompanying the +* software package from which you obtained this Software ( "EULA" ). +* If no EULA applies, Cypress hereby grants you a personal, nonexclusive, +* non-transferable license to copy, modify, and compile the +* Software source code solely for use in connection with Cypress's +* integrated circuit products. Any reproduction, modification, translation, +* compilation, or representation of this Software except as specified +* above is prohibited without the express written permission of Cypress. +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE. Cypress reserves the right to make +* changes to the Software without notice. Cypress does not assume any +* liability arising out of the application or use of the Software or any +* product or circuit described in the Software. Cypress does not +* authorize its products for use in any products where a malfunction or +* failure of the Cypress product may reasonably be expected to result in +* significant property damage, injury or death ( "High Risk Product" ). By +* including Cypress's product in a High Risk Product, the manufacturer +* of such system or application assumes all risk of such use and in doing +* so agrees to indemnify Cypress against all liability. +*/ +/******************************************************************************/ +/** \file system_s6e2c5.h + ** + ** Headerfile for FM4 system parameters + ** + ** History: + ** 16.12.2015 18:31:31 2.0 MISH Auto created by make header script + ** + ** + ** User clock definitions can be done for the following clock settings: + ** - CLOCK_SETUP : Execute the clock settings form the settings below in + ** SystemInit() + ** - __CLKMO : External clock frequency for main oscillion + ** - __CLKSO : External clock frequency for sub oscillion + ** - SCM_CTL : System Clock Mode Control Register + ** - BSC_PSR : Base Clock Prescaler Register + ** - APBC0_PSR : APB0 Prescaler Register + ** - APBC1_PSR : APB1 Prescaler Register + ** - APBC2_PSR : APB2 Prescaler Register + ** - SWC_PSR : Software Watchdog Clock Prescaler Register + ** - TTC_PSR : Trace Clock Prescaler Register + ** - CSW_TMR : Clock Stabilization Wait Time Register + ** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register + ** - PLL_CTL1 : PLL Control Register 1 + ** - PLL_CTL2 : PLL Control Register 2 + ** + ** The register settings are check for correct values of reserved bits. + ** Otherwise a preprocessor error is output and stops the build process. + ** Furthermore the 'master clock' is retrieved from the register settings + ** and the system clock (HCLK) is calculated from the Base Clock Prescaler + ** Register (BSC_PSR). This value is used for the global CMSIS variable + ** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is + ** is checked. Note that not all possible wrong setting are checked! The + ** user has to take care to fulfill the settings stated in the according + ** device's data sheet! + ** + ** User definition for Hardware Watchdog: + ** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit() + ** + ** User definition for CR Trimming: + ** - CR_TRIM_SETUP : Enables CR trimming in SystemInit() + ** + ******************************************************************************/ + +#ifndef _SYSTEM_S6E2C5_H_ +#define _SYSTEM_S6E2C5_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* START OF USER SETTINGS HERE */ +/* =========================== */ +/* */ +/* All lines with '<<<' can be set by user. */ +/* */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Setup macro definition + ** + ** - 0: CLOCK_SETTING_NONE - User provides own clock setting in application + ** - 1: CLOCK_SETTING_CMSIS - Clock setting done in system_s6e2c5.h like in + ** FM4 template projects + ******************************************************************************/ +#define CLOCK_SETTING_NONE 0u +#define CLOCK_SETTING_CMSIS 1u + +/** + ****************************************************************************** + ** \brief Clock Setup Enable + ** (USER SETTING) + ** + ** Possible settings: + ** - CLOCK_SETTING_NONE - User provides own clock setting in application + ** - CLOCK_SETTING_CMSIS - Clock setting done in system_s6e2c5.h like in + ** FM4 template projects + ******************************************************************************/ +#define CLOCK_SETUP CLOCK_SETTING_CMSIS // <<< Define clock setup macro here + +/** + ****************************************************************************** + ** \brief External Main Clock Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +// [andreika]: Use 8MHz crystal +#define __CLKMO ( 8000000ul) // <<< External 8MHz Crystal +//#define __CLKMO ( 4000000ul) // <<< External 4MHz Crystal + +/** + ****************************************************************************** + ** \brief External Sub Clock Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKSO ( 32768ul) // <<< External 32768HzCR Crystal + +/** + ****************************************************************************** + ** \brief System Clock Mode Control Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS is set) + ** + ** SCM_CTL + ** + ** Bit#7-5 : RCS[2:0] + ** - 0 = Internal high-speed CR oscillation (default) + ** - 1 = Main oscillation clock + ** - 2 = PLL oscillation clock + ** - 3 = (not allowed) + ** - 4 = Internal low-speed CR oscillation + ** - 5 = Sub clock oscillation + ** - 6 = (not allowed) + ** - 7 = (not allowed) + ** + ** Bit#4 : PLLE + ** - 0 = Disable PLL (default) + ** - 1 = Enable PLL + ** + ** Bit#3 : SOSCE + ** - 0 = Disable sub oscillation (default) + ** - 1 = Enable sub oscillation + ** + ** Bit#2 : (reserved) + ** + ** Bit#1 : MOSCE + ** - 0 = Disable main oscillation (default) + ** - 1 = Enable main oscillation + ** + ** Bit#0 : (reserved) + ******************************************************************************/ +#define SCM_CTL_Val ( 0x00000052ul) // <<< Define SCM_CTL here + +/** + ****************************************************************************** + ** \brief Base Clock Prescaler Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** BSC_PSR + ** + ** Bit#7-3 : (reserved) + ** + ** Bit#2-0 : BSR[2:0] + ** - 0 = HCLK = Master Clock + ** - 1 = HCLK = Master Clock / 2 + ** - 2 = HCLK = Master Clock / 3 + ** - 3 = HCLK = Master Clock / 4 + ** - 4 = HCLK = Master Clock / 6 + ** - 5 = HCLK = Master Clock / 8 + ** - 6 = HCLK = Master Clock / 16 + ** - 7 = (reserved) + ******************************************************************************/ +#define BSC_PSR_Val 0x00000000ul // <<< Define BSC_PSR here + +/** + ****************************************************************************** + ** \brief APB0 Prescaler Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** APBC0_PSR + ** + ** Bit#7-2 : (reserved) + ** + ** Bit#1-0 : BSR[2:0] + ** - 0 = PCLK0 = HCLK + ** - 1 = PCLK0 = HCLK / 2 + ** - 2 = PCLK0 = HCLK / 4 + ** - 3 = PCLK0 = HCLK / 8 + ******************************************************************************/ +#define APBC0_PSR_Val ( 0x00000000ul) // <<< Define APBC0_PSR here +//#define APBC0_PSR_Val ( 0x00000001ul) // <<< Define APBC0_PSR here + +/** + ****************************************************************************** + ** \brief APB1 Prescaler Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** APBC1_PSR + ** + ** Bit#7 : APBC1EN + ** - 0 = Disable PCLK1 output + ** - 1 = Enables PCLK1 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC1RST + ** - 0 = APB1 bus reset, inactive (default) + ** - 1 = APB1 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC1[2:0] + ** - 0 = PCLK1 = HCLK + ** - 1 = PCLK1 = HCLK / 2 + ** - 2 = PCLK1 = HCLK / 4 + ** - 3 = PCLK1 = HCLK / 8 + ******************************************************************************/ +#define APBC1_PSR_Val ( 0x00000082ul) // <<< Define APBC1_PSR here +//#define APBC1_PSR_Val ( 0x00000080ul) // <<< Define APBC1_PSR here + +/** + ****************************************************************************** + ** \brief APB2 Prescaler Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** APBC2_PSR + ** + ** Bit#7 : APBC2EN + ** - 0 = Disable PCLK2 output + ** - 1 = Enables PCLK2 (default) + ** + ** Bit#6-5 : (reserved) + ** + ** Bit#4 : APBC2RST + ** - 0 = APB2 bus reset, inactive (default) + ** - 1 = APB2 bus reset, active + ** + ** Bit#3-2 : (reserved) + ** + ** Bit#1-0 : APBC2[1:0] + ** - 0 = PCLK2 = HCLK + ** - 1 = PCLK2 = HCLK / 2 + ** - 2 = PCLK2 = HCLK / 4 + ** - 3 = PCLK2 = HCLK / 8 + ******************************************************************************/ +#define APBC2_PSR_Val ( 0x00000081ul) // <<< Define APBC2_PSR here + +/** + ****************************************************************************** + ** \brief Software Watchdog Clock Prescaler Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** SWC_PSR + ** + ** Bit#7 : TESTB + ** - 0 = (not allowed) + ** - 1 = (Bit is set in start-up code, do not set it below!) + ** + ** Bit#6-2 : (reserved) + ** + ** Bit#1-0 : SWDS[2:0] + ** - 0 = SWDGOGCLK = PCLK0 + ** - 1 = SWDGOGCLK = PCLK0 / 2 + ** - 2 = SWDGOGCLK = PCLK0 / 4 + ** - 3 = SWDGOGCLK = PCLK0 / 8 + ******************************************************************************/ +#define SWC_PSR_Val 0x00000003ul // <<< Define SWC_PSR here + +/** + ****************************************************************************** + ** \brief Trace Clock Prescaler Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** TTC_PSR + ** + ** Bit#7-1 : (reserved) + ** + ** Bit#0 : TTC + ** - 0 = TPIUCLK = HCLK + ** - 1 = TPIUCLK = HCLK / 2 + ******************************************************************************/ +#define TTC_PSR_Val 0x00000000ul // <<< Define TTC_PSR here + +/** + ****************************************************************************** + ** \brief Clock Stabilization Wait Time Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS is set) + ** + ** CSW_TMR + ** + ** Bit#7 : (reserved) + ** + ** Bit#6-4 : SOWT[2:0] + ** - 0 = ~10.3 ms (default) + ** - 1 = ~20.5 ms + ** - 2 = ~41 ms + ** - 3 = ~82 ms + ** - 4 = ~164 ms + ** - 5 = ~327 ms + ** - 6 = ~655 ms + ** - 7 = ~1.31 s + ** - 8 = ~2.62 s + ** - 9 = ~5.24 s + ** - 10 = ~10.49 s + ** - 11 = ~20.97 s + ** - 12 = ~0.02 ms + ** - 13 = ~0.04 ms + ** - 14 = ~0.08 ms + ** - 15 = ~0.16 ms + ** + ** Bit#3-0 : MOWT[3:0] + ** - 0 = ~500 ns (default) + ** - 1 = ~8 us + ** - 2 = ~16 us + ** - 3 = ~32 us + ** - 4 = ~64 us + ** - 5 = ~128 us + ** - 6 = ~256 us + ** - 7 = ~512 us + ** - 8 = ~1.0 ms + ** - 9 = ~2.0 ms + ** - 10 = ~4.0 ms + ** - 11 = ~8.0 ms + ** - 12 = ~33.0 ms + ** - 13 = ~131 ms + ** - 14 = ~524 ms + ** - 15 = ~2.0 s + ******************************************************************************/ +#define CSW_TMR_Val 0x0000005Cul // <<< Define CSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Clock Stabilization Wait Time Setup Register value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS is set) + ** + ** PSW_TMR + ** + ** Bit#7-5 : (reserved) + ** + ** Bit#4 : PINC + ** - 0 = Selects CLKMO (main oscillation) (default) + ** - 1 = (setting diabled) + ** + ** Bit#3 : (reserved) + ** + ** Bit#2-0 : POWT[2:0] + ** - 0 = ~128 us (default) + ** - 1 = ~256 us + ** - 2 = ~512 us + ** - 3 = ~1.02 ms + ** - 4 = ~2.05 ms + ** - 5 = ~4.10 ms + ** - 6 = ~8.20 ms + ** - 7 = ~16.40 ms + ******************************************************************************/ +#define PSW_TMR_Val 0x00000000ul // <<< Define PSW_TMR here + +/** + ****************************************************************************** + ** \brief PLL Control Register 1 value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** PLL_CTL1 + ** + ** Bit#7-4 : PLLK[3:0] + ** - 0 = Division(PLLK) = 1/1 (default) + ** - 1 = Division(PLLK) = 1/2 + ** - 2 = Division(PLLK) = 1/3 + ** - . . . + ** - 15 = Division(PLLK) = 1/16 + ** + ** Bit#3-0 : PLLM[3:0] + ** - 0 = Division(PLLM) = 1/1 (default) + ** - 1 = Division(PLLM) = 1/2 + ** - 2 = Division(PLLM) = 1/3 + ** - . . . + ** - 15 = Division(PLLM) = 1/16 + ******************************************************************************/ +#define PLL_CTL1_Val ( 0x00000001ul) // <<< Define PLL_CTL1 here + +/** + ****************************************************************************** + ** \brief PLL Control Register 2 value definition + ** (USER SETTING if CLOCK_SETTING_CMSIS or CLOCK_SETTING_PDL is set) + ** + ** PLL_CTL2 + ** + ** Bit#7-6 : (reserved) + ** + ** Bit#5-0 : PLLN[5:0] + ** - 0 = Division(PLLN) = 1/1 (default) + ** - 1 = Division(PLLN) = 1/2 + ** - 2 = Division(PLLN) = 1/3 + ** - . . . + ** - 63 = Division(PLLN) = 1/64 + ******************************************************************************/ +// [andreika]: 31h->17h for 8MHz crystal -> 192 MHz +#define PLL_CTL2_Val (0x00000017ul) +//#define PLL_CTL2_Val ( 0x00000031ul) // <<< Define PLL_CTL2 here + +/** + ****************************************************************************** + ** \brief Hardware Watchdog disable definition + ** (USER SETTING) + ** + ** - 0 = Hardware Watchdog enable + ** - 1 = Hardware Watchdog disable + ******************************************************************************/ +#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here + +/** + ****************************************************************************** + ** \brief Trimming CR + ** (USER SETTING) + ** + ** - 0 = CR is not trimmed at startup + ** - 1 = CR is trimmed at startup + ******************************************************************************/ +#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here + +/** + ****************************************************************************** + ** brief Trace Buffer enable definition + ** (USER SETTING) + ** + ** - 0 = Trace Buffer disable + ** - 1 = Trace Buffer enable + ******************************************************************************/ +#define TRACE_BUFFER_ENABLE 1 // <<< Define Trace Buffer enable here + +/** + ****************************************************************************** + ** brief Low-speed CR Prescaler Control Register value definition + ** (USER SETTING) + ******************************************************************************/ +#define LCR_PRSLD_Val 0x00000000ul // <<< Define LCR_PRSLD here + + +/******************************************************************************/ +/* */ +/* END OF USER SETTINGS HERE */ +/* ========================= */ +/* */ +/******************************************************************************/ + +/******************************************************************************/ +/* Device dependent System Clock absolute maximum ranges */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKHC ( 4000000ul) // Internal 4MHzCR Oscillator + +/** + ****************************************************************************** + ** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]ul) + ** (USER SETTING) + ******************************************************************************/ +#define __CLKLC ( 100000ul) // Internal 100KHzCR Oscillator + +/** + ****************************************************************************** + ** \brief Any case minimum Main Clock frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMIN ( 4000000ul) + +/** + ****************************************************************************** + ** \brief Maximum Main Clock frequency using external clock (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKMOMAX ( 48000000ul) + +/** + ****************************************************************************** + ** \brief Any case minimum Sub Clock frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMIN ( 32000ul) + +/** + ****************************************************************************** + ** \brief Maximum Sub Clock frequency using external clock (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __CLKSOMAX ( 100000ul) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL input frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMIN ( 4000000ul) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL input frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKINMAX ( 16000000ul) + +/** + ****************************************************************************** + ** \brief Absolute minimum PLL output oscillation frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKOUTMIN ( 200000000ul) + +/** + ****************************************************************************** + ** \brief Absolute maximum PLL output oscillation frequency (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __PLLCLKOUTMAX ( 400000000ul) + +/** + ****************************************************************************** + ** \brief Absolute maximum System Clock frequency (HCLK) (in Hz, [value]ul) + ** (DEVICE DEPENDENT SETTING) + ******************************************************************************/ +#define __HCLKMAX ( 200000000ul) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking range (clock settings). + ** + ** \return 0 Within range + ** \return 1 Out of range + ******************************************************************************/ +#define CHECK_RANGE(val, min, max) (((val) < (min)) || ((val) > (max))) + +/** + ****************************************************************************** + ** \brief Preprocessor macro for checking bits with mask (clock settings). + ** Prevents from setting reserved bits by mistake. + ** + ** \return 0 All bits within mask + ** \return 1 One or more bits out of mask + ******************************************************************************/ +#define CHECK_RSVD(val, mask) ((val) & (mask)) + + +/******************************************************************************/ +/* Check register settings */ +/******************************************************************************/ +#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FAul)) +#error "SCM_CTL: Invalid values of reserved bits!" +#endif + + +#if ((SCM_CTL_Val & 0xE0ul) == 0x20ul) && ((SCM_CTL_Val & 0x02ul) != 0x02ul) + #error "SCM_CTL: Main ocsillator mode is selected but MOSC is not enabled!" +#endif + +#if ((SCM_CTL_Val & 0xE0ul) == 0xA0ul) && ((SCM_CTL_Val & 0x08ul) != 0x08ul) + #error "SCM_CTL: sub ocsillator mode is selected but SOSC is not enabled!" +#endif + +#if ((SCM_CTL_Val & 0xE0ul) == 0x40ul) && ((SCM_CTL_Val & 0x03ul) == 0x00ul) + #error "SCM_CTL: CLKPLL is selected but MOSC or HCR is not enabled!" +#endif + +#if ((SCM_CTL_Val & 0xE0ul) == 0x40ul) && ((SCM_CTL_Val & 0x10ul) != 0x10ul) + #error "SCM_CTL: CLKPLL is selected but PLL is not enabled!" +#endif + +#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007Ful)) + #error "CSW_TMR: Invalid values of reserved bits!" +#endif + +#if ((SCM_CTL_Val & 0x10ul)) /* if PLL is used */ + #if (CHECK_RSVD((PSW_TMR_Val), ~0x00000017ul)) + #error "PSW_TMR: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FFul)) + #error "PLL_CTL1: Invalid values of reserved bits!" + #endif + + #if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003Ful)) + #error "PLL_CTL2: Invalid values of reserved bits!" + #endif +#endif + +#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007ul)) + #error "BSC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003ul)) + #error "APBC0_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000093ul)) + #error "APBC1_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003ul)) + #error "SWC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000093ul)) + #error "APBC2_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000003ul)) + #error "TTC_PSR: Invalid values of reserved bits!" +#endif + +#if (CHECK_RSVD((LCR_PRSLD_Val), ~0x0000003Ful)) + #error "LCR_PRSLD: Invalid values of reserved bits!" +#endif + +/******************************************************************************/ +/* Define clocks with checking settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Calculate PLL K factor from settings + ******************************************************************************/ +#define __PLLK (((PLL_CTL1_Val >> 4ul) & 0x0Ful) + 1ul) + +/** + ****************************************************************************** + ** \brief Calculate PLL N factor from settings + ******************************************************************************/ +#define __PLLN (((PLL_CTL2_Val ) & 0x3Ful) + 1ul) + +/** + ****************************************************************************** + ** \brief Calculate PLL M factor from settings + ******************************************************************************/ +#define __PLLM (((PLL_CTL1_Val ) & 0x0Ful) + 1ul) + +/** + ****************************************************************************** + ** \brief Calculate PLL output frequency from settings + ******************************************************************************/ +#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK) + +/******************************************************************************/ +/* Determine core clock frequency according to settings */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Define Master Clock from settings + ******************************************************************************/ +#if (((SCM_CTL_Val >> 5ul) & 0x07UL) == 0ul) + #define __MASTERCLK (__CLKHC) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 1ul) + #define __MASTERCLK (__CLKMO) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 2ul) + #define __MASTERCLK (__PLLCLK) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 4ul) + #define __MASTERCLK (__CLKLC) +#elif (((SCM_CTL_Val >> 5ul) & 0x07UL) == 5ul) + #define __MASTERCLK (__CLKSO) +#else + #define __MASTERCLK (0UL) +#endif + +/** + ****************************************************************************** + ** \brief Define System Clock Frequency (Core Clock) from settings + ******************************************************************************/ +#if ((BSC_PSR_Val & 0x07UL) == 0ul) + #define __HCLK (__MASTERCLK / 1ul) +#elif ((BSC_PSR_Val & 0x07UL) == 1ul) + #define __HCLK (__MASTERCLK / 2ul) +#elif ((BSC_PSR_Val & 0x07UL) == 2ul) + #define __HCLK (__MASTERCLK / 3ul) +#elif ((BSC_PSR_Val & 0x07UL) == 3ul) + #define __HCLK (__MASTERCLK / 4ul) +#elif ((BSC_PSR_Val & 0x07UL) == 4ul) + #define __HCLK (__MASTERCLK / 6ul) +#elif ((BSC_PSR_Val & 0x07UL) == 5ul) + #define __HCLK (__MASTERCLK / 8ul) +#elif ((BSC_PSR_Val & 0x07UL) == 6ul) + #define __HCLK (__MASTERCLK /16ul) +#else + #define __HCLK (0ul) +#endif + +/******************************************************************************/ +/* HCLK range check */ +/******************************************************************************/ +#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX)) + #error "Main Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX)) + #error "Sub Oscillator Clock (CLKMO) out of range!" +#endif + +#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX)) + #error "PLL input frequency out of range!" +#endif + +#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKOUTMIN, __PLLCLKOUTMAX)) + #error "PLL oscillation frequency out of range!" +#endif + +#if (CHECK_RANGE(__HCLK, 0UL, __HCLKMAX)) + #error "System Clock (HCLK) out of range!" +#endif + + + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock) + +extern void SystemInit (void); // Initialize the system + +extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable + +// [andreika]: Core IRQ vector mappings in ChibiOS style +#include "chibios_pdl_vectors.h" + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/ld/cypress_S6E2CxAH.ld b/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/ld/cypress_S6E2CxAH.ld new file mode 100644 index 0000000000..de7f3a0fd5 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/ld/cypress_S6E2CxAH.ld @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com + * (C) 2016 flabbergast + * (C) 2019 andreika + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +/* + * S6E2CxAH memory setup. + */ +MEMORY +{ + flash0 : org = 0x00000000, len = 0x200000 + flash1 : org = 0x00406000, len = 0xA000 + flash2 : org = 0x00000000, len = 0 + flash3 : org = 0x00000000, len = 0 + flash4 : org = 0x00000000, len = 0 + flash5 : org = 0x00000000, len = 0 + flash6 : org = 0x00000000, len = 0 + flash7 : org = 0x00000000, len = 0 + ram0 : org = 0x1FFD0000, len = 192k + ram1 : org = 0x20038000, len = 32k + ram2 : org = 0x20040000, len = 32k + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* For each data/text section two region are defined, a virtual region + and a load region (_LMA suffix).*/ + +/* Flash region to be used for exception vectors.*/ +REGION_ALIAS("VECTORS_FLASH", flash0); +REGION_ALIAS("VECTORS_FLASH_LMA", flash0); + +/* Flash region to be used for constructors and destructors.*/ +REGION_ALIAS("XTORS_FLASH", flash0); +REGION_ALIAS("XTORS_FLASH_LMA", flash0); + +/* Flash region to be used for code text.*/ +REGION_ALIAS("TEXT_FLASH", flash0); +REGION_ALIAS("TEXT_FLASH_LMA", flash0); + +/* Flash region to be used for read only data.*/ +REGION_ALIAS("RODATA_FLASH", flash0); +REGION_ALIAS("RODATA_FLASH_LMA", flash0); + +/* Flash region to be used for various.*/ +REGION_ALIAS("VARIOUS_FLASH", flash0); +REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); + +/* Flash region to be used for RAM(n) initialization data.*/ +REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts.*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); +REGION_ALIAS("DATA_RAM_LMA", flash0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +/* Generic rules inclusion.*/ +INCLUDE rules.ld diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk b/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk new file mode 100644 index 0000000000..c0374f7dd9 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk @@ -0,0 +1,23 @@ + +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +# List of the ChibiOS generic KE1xF startup and CMSIS files. +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c + +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S + +STARTUPINC = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/devices/S6E2CxAH \ + $(CYPRESS_CONTRIB)/os/common/ext/CMSIS/S6E2CxAH \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ + $(CHIBIOS)/os/common/ext/CMSIS/include \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include + +STARTUPLD = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/devices/S6E2CxAH/cmparams.h b/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/devices/S6E2CxAH/cmparams.h new file mode 100644 index 0000000000..e8b9f0303b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/common/startup/ARMCMx/devices/S6E2CxAH/cmparams.h @@ -0,0 +1,81 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio. + (C) 2015 RedoX https://github.com/RedoXyde + (C) 2016 flabbergast + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file cmparams.h + * @brief ARM Cortex-M4 parameters for the Cypress S6E2CxAH. + * + * @details This file contains the Cortex-M4 specific parameters for the + * Cypress S6E2CxAH platform. + * @{ + */ + +#ifndef _CMPARAMS_H_ +#define _CMPARAMS_H_ + +/** + * @brief Cortex core model. + */ +#define CORTEX_MODEL 4 + +/** + * @brief Systick unit presence. + */ +#define CORTEX_HAS_ST TRUE + +/** + * @brief Floating Point unit presence. + */ +#define CORTEX_HAS_FPU 1 + +/** + * @brief Number of bits in priority masks. + */ +#define CORTEX_PRIORITY_BITS 4 + +/** + * @brief Number of interrupt vectors. + * @note This number does not include the 16 system vectors and must be + * rounded to a multiple of 8. + */ +#define CORTEX_NUM_VECTORS 128 + +/* The following code is not processed when the file is included from an + asm module.*/ +#if !defined(_FROM_ASM_) + +/* Including the device CMSIS header. Note, we are not using the definitions + from this header because we need this file to be usable also from + assembler source files. We verify that the info matches instead.*/ +#include "s6e2c5xh.h" +//#include "s6e2c5xl.h" + +#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS +#error "CMSIS __NVIC_PRIO_BITS mismatch" +#endif + +#endif /* !defined(_FROM_ASM_) */ + +#define SVCall_IRQn SVC_IRQn + +#endif /* _CMPARAMS_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/driver.mk b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/driver.mk new file mode 100644 index 0000000000..8162a858c2 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/driver.mk @@ -0,0 +1,6 @@ +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +PLATFORMSRC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.c +PLATFORMINC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/ADCv2 diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.c new file mode 100644 index 0000000000..3bd18fa775 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.c @@ -0,0 +1,371 @@ +/* + ChibiOS - Copyright (C) 2014 Derek Mulcahy + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADCv1/hal_adc_lld.c + * @brief Cypress S6E2Cx ADC subsystem low level driver source. + * @author andreika + * + * @addtogroup ADC + * @{ + */ + +#include +#include "hal.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief ADC1 driver identifier.*/ +#if CYPRESS_ADC_USE_ADC0 || defined(__DOXYGEN__) +ADCDriver ADCD1; +#endif + +/** @brief ADC2 driver identifier.*/ +#if CYPRESS_ADC_USE_ADC1 || defined(__DOXYGEN__) +ADCDriver ADCD2; +#endif + +/** @brief ADC3 driver identifier.*/ +#if CYPRESS_ADC_USE_ADC2 || defined(__DOXYGEN__) +ADCDriver ADCD3; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +//!!!!!!!!!! +#define BOARD_MOD1_PORT GPIOD +#define BOARD_MOD1_PIN 5 + +static void adc_result_callback(ADCDriver *adcp, volatile uint32_t* pu32AdcArgument) { + + // if the interrupt is 'late' (called after the conversion is aborted) + if (adcp->grpp == NULL) { + Adc_ClrScanFifo(adcp->adc); + return; + } + + int i = adcp->fifoSize; + + chSysLockFromISR(); + while (i-- > 0) { + uint32_t u32AdcResult = Adc_ReadScanFifo(adcp->adc); // *pu32AdcArgument; + if (u32AdcResult == 0xFFFFFFFF || Adc_GetScanDataValid(adcp->adc, u32AdcResult) != AdcFifoDataValid) + continue; + + uint16_t u16AdcValue = Adc_GetScanData(adcp->adc, u32AdcResult); + // todo: we don't know the exact order of the HW channels - if it's always ascending, we could use more efficient LUT + uint8_t hwChannelIdx = Adc_GetScanChannel(adcp->adc, u32AdcResult); + int logicChannelIdx = adcp->channelLogicIndices[hwChannelIdx]; + int currentStartIndex = (adcp->current_index / adcp->grpp->num_channels) * adcp->grpp->num_channels; + + /* Read the sample into the buffer */ + adcp->samples[currentStartIndex + logicChannelIdx] = u16AdcValue; + adcp->current_index++; + } + chSysUnlockFromISR(); + + bool more = true; + + /* At the end of the buffer then we may be finished */ + if (adcp->current_index >= adcp->number_of_samples) { + /* We are never finished in circular mode */ + more = adcp->grpp->circular; + + _adc_isr_full_code(adcp); + + adcp->current_index = 0; + } + + if (more) { + /* Signal half completion in circular mode. */ + if (adcp->grpp->circular && (adcp->current_index == (adcp->number_of_samples / 2))) { + _adc_isr_half_code(adcp); + } + //if ((adcp->current_index % adcp->grpp->num_channels) == (adcp->grpp->num_channels - 1)) { + Adc_SwTriggerScan(adcp->adc); + //break; + //} + } +} + +static void adc_error_callback(ADCDriver *adcp) { + adcp->current_index = 0; + Adc_ClrScanFifo(adcp->adc); + _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW); + if (adcp->grpp->circular) + Adc_SwTriggerScan(adcp->adc); +} + +///////////////////////////////////////////////////////////////////////// + +static void adc_result_callback1(volatile uint32_t* pu32AdcArgument) { + adc_result_callback(&ADCD1, pu32AdcArgument); +} + +static void adc_result_callback2(volatile uint32_t* pu32AdcArgument) { + adc_result_callback(&ADCD2, pu32AdcArgument); +} + +static void adc_result_callback3(volatile uint32_t* pu32AdcArgument) { + adc_result_callback(&ADCD3, pu32AdcArgument); +} + +static void adc_error_callback1(void) { + adc_error_callback(&ADCD1); +} + +static void adc_error_callback2(void) { + adc_error_callback(&ADCD2); +} + +static void adc_error_callback3(void) { + adc_error_callback(&ADCD3); +} + +/** + * @brief ADC interrupt handler. + * + * @isr + */ +static bool initAdc(ADCDriver *adcp) { + int chn; + PDL_ZERO_STRUCT(adcp->stcAdcConfig); // Clear local configuration to zero. + PDL_ZERO_STRUCT(adcp->stcScanCfg); + + if (adcp->grpp->num_channels < 1) { + // we need to return otherwise we never get an interrupt, and the whole process halts + // todo: is it enough to say the HAL driver to abort? + adcp->state = ADC_STOP; + return false; + } + + adcp->stcScanCfg.u32ScanCannelSelect.u32AD_CHn = 0; + adcp->stcAdcConfig.u32SamplingTimeSelect.u32AD_CHn = 0; + for (chn = 0; chn < adcp->grpp->num_channels; chn++) { + adcp->stcScanCfg.u32ScanCannelSelect.u32AD_CHn |= 1u << adcp->channelHwIndices[chn]; + //adcp->stcAdcConfig.u32SamplingTimeSelect.u32AD_CHn |= 1u << adcp->channelHwIndices[chn]; + } + + adcp->fifoSize = (adcp->grpp->num_channels < CYPRESS_ADC_FIFO_SIZE) ? adcp->grpp->num_channels : CYPRESS_ADC_FIFO_SIZE; + + adcp->stcScanCfg.enScanMode = ScanSingleConversion; // ScanRepeatConversion + adcp->stcScanCfg.enScanTimerTrigger = AdcNoTimer; + adcp->stcScanCfg.bScanTimerStartEnable = FALSE; + adcp->stcScanCfg.u8ScanFifoDepth = adcp->fifoSize - 1; + + adcp->stcAdcConfig.bLsbAlignment = TRUE; + adcp->stcAdcConfig.enSamplingTimeN0 = Value8; // Value32 + adcp->stcAdcConfig.u8SamplingTime0 = 8u; // 30u + adcp->stcAdcConfig.enSamplingTimeN1 = Value8; // Value32 + adcp->stcAdcConfig.u8SamplingTime1 = 8u;//30u; + adcp->stcAdcConfig.u8ComparingClockDiv = 3u; // Frequency division ratio: 5, 0:Ratio 2, 1:Ratio 3, ... + adcp->stcAdcConfig.pstcScanInit = &adcp->stcScanCfg; + adcp->stcAdcConfig.u8EnableTime = 10u;//0x80; + + memset(&adcp->stcIrqEn, 0, sizeof(adcp->stcIrqEn)); + adcp->stcIrqEn.bScanIrq = TRUE; + adcp->stcIrqEn.bFifoOverrunIrq = TRUE; + + adcp->stcAdcConfig.pstcIrqEn = &adcp->stcIrqEn; + adcp->stcAdcConfig.pstcIrqCb = &adcp->stcIrqCb; + + adcp->stcAdcConfig.bTouchNvic = TRUE; + + if (Adc_Init((volatile stc_adcn_t*)adcp->adc, &adcp->stcAdcConfig) == Ok) { + Adc_EnableWaitReady(adcp->adc); + return true; + } + return false; +} + +static void adc_init_structures(ADCDriver *adcp) { + adcObjectInit(adcp); + memset(&adcp->stcIrqCb, 0, sizeof(adcp->stcIrqCb)); + memset(adcp->oldChannelHwIndices, 0, sizeof(adcp->oldChannelHwIndices)); + ADCD1.oldNumChannels = 0; + ADCD1.oldDepth = 0; + adcp->wasInit = false; +} + + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ADC driver initialization. + * + * @notapi + */ +void adc_lld_init(void) { + +#if CYPRESS_ADC_USE_ADC0 + /* Driver initialization.*/ + adc_init_structures(&ADCD1); + ADCD1.adc = (stc_adcn_t *)&ADC0; + ADCD1.stcIrqCb.pfnScanIrqCb = &adc_result_callback1; + ADCD1.stcIrqCb.pfnScanErrIrqCb = &adc_error_callback1; +#endif + +#if CYPRESS_ADC_USE_ADC1 + /* Driver initialization.*/ + adc_init_structures(&ADCD2); + ADCD2.adc = (stc_adcn_t *)&ADC1; + ADCD2.stcIrqCb.pfnScanIrqCb = &adc_result_callback2; + ADCD2.stcIrqCb.pfnScanErrIrqCb = &adc_error_callback2; +#endif + +#if CYPRESS_ADC_USE_ADC2 + /* Driver initialization.*/ + adc_init_structures(&ADCD3); + ADCD3.adc = (stc_adcn_t *)&ADC2; + ADCD3.stcIrqCb.pfnScanIrqCb = &adc_result_callback3; + ADCD3.stcIrqCb.pfnScanErrIrqCb = &adc_error_callback3; +#endif + +} + +/** + * @brief Configures and activates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start(ADCDriver *adcp) { + + /* If in stopped state then enables the ADC clock.*/ + if (adcp->state == ADC_STOP) { + } +} + +/** + * @brief Deactivates the ADC peripheral. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop(ADCDriver *adcp) { + + /* If in ready state then disables the ADC clock.*/ + if (adcp->state == ADC_READY) { + } +} + +/** + * @brief Starts an ADC conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_start_conversion(ADCDriver *adcp) { + const ADCConversionGroup *grpp = adcp->grpp; + + int chn; + adcp->channelHwIndices[0] = ADCx_SC1n_ADCH_DISABLED; + for (chn = 0; chn < grpp->num_channels; chn++) { + if (chn < 6) { + adcp->channelHwIndices[chn] = (grpp->sqr3 >> (chn * 5)) & 31; + } else if (chn < 12) { + adcp->channelHwIndices[chn] = (grpp->sqr2 >> ((chn - 6) * 5)) & 31; + } else if (chn < 18) { // actually, it's 16 + adcp->channelHwIndices[chn] = (grpp->sqr1 >> ((chn - 12) * 5)) & 31; + } else if (chn < 24) { + adcp->channelHwIndices[chn] = (grpp->sqr4 >> ((chn - 18) * 5)) & 31; + } else if (chn < 30) { + adcp->channelHwIndices[chn] = (grpp->sqr5 >> ((chn - 24) * 5)) & 31; + } + // we need to restore the correct order of the channels in the IRQ handler + adcp->channelLogicIndices[adcp->channelHwIndices[chn]] = chn; + } + + adcp->number_of_samples = adcp->depth * grpp->num_channels; + adcp->current_index = 0; + + bool isChanged = true; + // check if the config is changed + if (grpp->num_channels == adcp->oldNumChannels && adcp->depth == adcp->oldDepth) { + // we can store bitmask and compare but we cannot be sure about the order of the channels. + if (memcmp(adcp->channelHwIndices, adcp->oldChannelHwIndices, sizeof(adcp->channelHwIndices[0]) * grpp->num_channels) == 0) { + isChanged = false; + } + } + // config has changed, we need to re-initialize the ADC driver + if (isChanged) { + if (adcp->wasInit) { + Adc_DeInit(adcp->adc, TRUE); + adcp->wasInit = false; + } + // store new config + adcp->oldNumChannels = grpp->num_channels; + adcp->oldDepth = adcp->depth; + memcpy(adcp->oldChannelHwIndices, adcp->channelHwIndices, sizeof(adcp->channelHwIndices[0]) * grpp->num_channels); + } + + // late init - only when we know the channel configuration + if (!adcp->wasInit) { + adcp->wasInit = true; + initAdc(adcp); + } else { + //Adc_EnableWaitReady(adcp->adc); + } + //Adc_EnableIrq(adcp->adc, &adcp->stcIrqEn); + //Adc_StartScanRepeat(adcp->adc); + Adc_SwTriggerScan(adcp->adc); + +} + +/** + * @brief Stops an ongoing conversion. + * + * @param[in] adcp pointer to the @p ADCDriver object + * + * @notapi + */ +void adc_lld_stop_conversion(ADCDriver *adcp) { + // we stop the repeative scan and wait for the next adc_lld_start_conversion() call + //Adc_StopScanRepeat(adcp->adc); + // abort pending interrupt + //Adc_ClrIrqFlag(adcp->adc, AdcScanIrq); + //Adc_DisableIrq(adcp->adc, &adcp->stcIrqEn); + //Adc_Disable(adcp->adc); + + //Adc_DeInit(adcp->adc, TRUE); +} + +#endif /* HAL_USE_ADC */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.h new file mode 100644 index 0000000000..728a58fdfc --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/ADCv2/hal_adc_lld.h @@ -0,0 +1,445 @@ +/* + ChibiOS - Copyright (C) 2014 Derek Mulcahy + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file ADCv1/hal_adc_lld.h + * @brief Cypress S6E2x ADC subsystem low level driver header. + * @author andreika + * + * @addtogroup ADC + * @{ + */ + +#ifndef HAL_ADC_LLD_H_ +#define HAL_ADC_LLD_H_ + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +#include "pdl_header.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Minimum ADC clock frequency. + */ +#define CYPRESS_ADCCLK_MIN 600000 + +/** + * @brief Maximum ADC clock frequency. + */ +#define CYPRESS_ADCCLK_MAX 36000000 + +#define CYPRESS_ADC_FIFO_SIZE 16 + +#define ADCx_SC1n_ADCH_DISABLED 31 + +#define ADC_CR2_SWSTART (0x1U << 30U) /*! + * + * @addtogroup CAN + * @{ + */ + +#include + +#include "hal.h" + +//!!!!!!!!!!!!!!!!!!!!!!! +extern void toggleLed(int led, int mode); + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define CAN_BUFFER_NOT_FOUND 0xff + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief CAN0 driver identifier.*/ +#if CYPRESS_CAN_USE_CAN0 || defined(__DOXYGEN__) +CANDriver CAND1; +#endif + +/** @brief CAN1 driver identifier.*/ +#if CYPRESS_CAN_USE_CAN1 || defined(__DOXYGEN__) +CANDriver CAND2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static uint8_t can_get_mailbox(canmbx_t mailbox, const bool *isOccupiedBuf, size_t bufSize, bool isFree) { + uint8_t i; + if (mailbox == CAN_ANY_MAILBOX) { + for (i = 0; i < bufSize; i++) { + // return the first unoccupied mailbox + if ((!isOccupiedBuf[i] && isFree) || (isOccupiedBuf[i] && !isFree)) { + return i; + } + } + return CAN_BUFFER_NOT_FOUND; + } + return (uint8_t)mailbox - 1; +} + +// called from interrupt +static void can_occupy_rx_mailboxI(CANDriver *can, uint8_t idx) { + chSysLockFromISR(); + can->is_rx_mailbox_occupied[idx] = true; + chSysUnlockFromISR(); +} + +// called from already locked PAL function +static uint8_t can_get_and_free_rx_mailbox(CANDriver *can, canmbx_t mailbox) { + uint8_t idx = can_get_mailbox(mailbox, can->is_rx_mailbox_occupied, sizeof(can->is_rx_mailbox_occupied), false); + if (idx != CAN_BUFFER_NOT_FOUND) { + can->is_rx_mailbox_occupied[idx] = false; + } + return idx; +} + +// called from already locked PAL function +static uint8_t can_get_tx_mailbox_and_occupy(CANDriver *can, canmbx_t mailbox) { + uint8_t idx = can_get_mailbox(mailbox, can->is_tx_mailbox_occupied, sizeof(can->is_tx_mailbox_occupied), true); + if (idx != CAN_BUFFER_NOT_FOUND) { + can->is_tx_mailbox_occupied[idx] = true; + } + return idx; +} + +// called from interrupt +static void can_free_tx_mailboxI(CANDriver *can, uint8_t u8MsgBuf) { + chSysLockFromISR(); + can->is_tx_mailbox_occupied[u8MsgBuf] = false; + chSysUnlockFromISR(); +} + +static void can_copy_message(stc_canfd_msg_t *pstcSrc, stc_canfd_msg_t *pstcDst) { + uint8_t u8Idx; + + // Copy if both source and destination pointers are valid. + if (pstcSrc != NULL && pstcDst != NULL) { + // Copy ID members. + pstcDst->stcIdentifier.u32Identifier = pstcSrc->stcIdentifier.u32Identifier; + pstcDst->stcIdentifier.bExtended = pstcSrc->stcIdentifier.bExtended; + + // Copy data members. + for (u8Idx = 0; u8Idx < CANFD_MESSAGE_DATA_BUFFER_SIZEW; u8Idx++) { + pstcDst->stcData.au32Data[u8Idx] = pstcSrc->stcData.au32Data[u8Idx]; + } + pstcDst->stcData.u8DataLengthCode = pstcSrc->stcData.u8DataLengthCode; + + // Copy extended DLC flag. + pstcDst->bCanfd = pstcSrc->bCanfd; + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if CYPRESS_CAN_USE_CAN0 || defined(__DOXYGEN__) + +static void can_tx_complete_callback0(uint8_t u8MsgBuf) { + + //!!!!!!!!!!!! + toggleLed(3, 1); + + can_free_tx_mailboxI(&CAND1, u8MsgBuf); + /* Signaling flags and waking up threads waiting for a transmission slot.*/ + _can_tx_empty_isr(&CAND1, 0); +} + +static void can_rx_received_callback0(uint8_t u8MsgBuf, stc_canfd_msg_t* pstcRxMsg) { + + //!!!!!!!!!!!! + toggleLed(2, 1); + + can_occupy_rx_mailboxI(&CAND1, u8MsgBuf); + can_copy_message(pstcRxMsg, &CAND1.stcRxMsg[u8MsgBuf]); + + _can_rx_full_isr(&CAND1, /*flags*/0); +} + +static void can_status_callback0(en_canfd_status_t enCanfdStatus) { + // BusOff state. + if (enCanfdStatus == CanfdBusOff) { + Canfd_Restart((volatile stc_canfdn_t*)(&CANFD0)); + } +} + +static void can_error_callback0(uint32_t u32CanfdErrorFlags) { + // todo: use u32CanfdErrorFlags + (void)u32CanfdErrorFlags; + + //!!!!!!!!!!!! + toggleLed(4, 1); + + _can_error_isr(&CAND1, CAN_OVERFLOW_ERROR); + + Canfd_Restart((volatile stc_canfdn_t*)(&CANFD0)); +} + +#endif /* CYPRESS_CAN_USE_CAN0 */ + +#if CYPRESS_CAN_USE_CAN1 || defined(__DOXYGEN__) + +static void can_tx_complete_callback1(uint8_t u8MsgBuf) { + can_free_tx_mailboxI(&CAND2, u8MsgBuf); + /* Signaling flags and waking up threads waiting for a transmission slot.*/ + _can_tx_empty_isr(&CAND2, 0); +} + +static void can_rx_received_callback1(uint8_t u8MsgBuf, stc_canfd_msg_t* pstcRxMsg) { + can_occupy_rx_mailboxI(&CAND2, u8MsgBuf); + can_copy_message(pstcRxMsg, &CAND2.stcRxMsg[u8MsgBuf]); + + _can_rx_full_isr(&CAND2, /*flags*/0); +} + +static void can_status_callback1(en_canfd_status_t enCanfdStatus) { + // BusOff state. + if (enCanfdStatus == CanfdBusOff) { + Canfd_Restart((volatile stc_canfdn_t*)(&CANFD1)); + } +} + +static void can_error_callback1(uint32_t u32CanfdErrorFlags) { + // todo: use u32CanfdErrorFlags + (void)u32CanfdErrorFlags; + + _can_error_isr(&CAND2, CAN_OVERFLOW_ERROR); + + Canfd_Restart((volatile stc_canfdn_t*)(&CANFD1)); +} + +#endif /* CYPRESS_CAN_USE_CAN1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level CAN driver initialization. + * + * @notapi + */ +void can_lld_init(void) { + +#if CYPRESS_CAN_USE_CAN0 + /* Driver initialization.*/ + canObjectInit(&CAND1); + CAND1.can = (stc_canfdn_t *)(&CANFD0); +#endif + +#if CYPRESS_CAN_USE_CAN1 + /* Driver initialization.*/ + canObjectInit(&CAND2); + CAND2.can = (stc_canfdn_t *)(&CANFD1); +#endif +} + +/** + * @brief Configures and activates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_start(CANDriver *canp) { + + memset(&canp->stcCanfdConfig, 0, sizeof(canp->stcCanfdConfig)); + +#if CYPRESS_CAN_USE_CAN0 + if (&CAND1 == canp) { + canp->can = (stc_canfdn_t*)&CANFD0; + canp->stcCanfdConfig.pfnReceiveMsgCallback = can_rx_received_callback0; + canp->stcCanfdConfig.pfnTransmitMsgCallback = can_tx_complete_callback0; + canp->stcCanfdConfig.pfnStatusCallback = can_status_callback0; + canp->stcCanfdConfig.pfnErrorCallback = can_error_callback0; + } +#endif + +#if CYPRESS_CAN_USE_CAN1 + if (&CAND2 == canp) { + canp->can = (stc_canfdn_t*)&CANFD1; + canp->stcCanfdConfig.pfnReceiveMsgCallback = can_rx_received_callback1; + canp->stcCanfdConfig.pfnTransmitMsgCallback = can_tx_complete_callback1; + canp->stcCanfdConfig.pfnStatusCallback = can_status_callback1; + canp->stcCanfdConfig.pfnErrorCallback = can_error_callback1; + } +#endif + + memset(canp->is_rx_mailbox_occupied, 0, sizeof(canp->is_rx_mailbox_occupied)); + memset(canp->is_tx_mailbox_occupied, 0, sizeof(canp->is_tx_mailbox_occupied)); + + // Configuring CAN + Canpre_Init(CanfdPreDiv16); // =1/6 (192MHz / 6 = 32MHz), see CYPRESS_PLL_FREQ + + // Set configuration parameters of CAN FD. + canp->stcCanfdConfig.enCanfdMode = CanfdModeClassic; + canp->stcCanfdConfig.enCanfdClock = CanfdClock32MHz; // CAN operation clock: 32MHz + + // Initialize CAN FD. + en_result_t res = Canfd_Init(canp->can, &canp->stcCanfdConfig); + + osalDbgAssert(res == Ok, "CAN: Canfd_Init failed"); + + Canfd_Start(canp->can); +} + +/** + * @brief Deactivates the CAN peripheral. + * + * @param[in] canp pointer to the @p CANDriver object + * + * @notapi + */ +void can_lld_stop(CANDriver *canp) { + /* If in ready state then disables the CAN peripheral.*/ + if (canp->state == CAN_READY) { + Canfd_Stop(canp->can); + } +} + +/** + * @brief Determines whether a frame can be transmitted. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval false no space in the transmit queue. + * @retval true transmit slot available. + * + * @notapi + */ +bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) { + uint8_t idx = can_get_mailbox(mailbox, canp->is_tx_mailbox_occupied, sizeof(canp->is_tx_mailbox_occupied), true); + if (idx == CAN_BUFFER_NOT_FOUND) + return false; + return !canp->is_tx_mailbox_occupied[idx]; +} + +/** + * @brief Inserts a frame into the transmit queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] ctfp pointer to the CAN frame to be transmitted + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @notapi + */ +void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *ctfp) { + int i; + + // Request to send + uint8_t bufIdx = can_get_tx_mailbox_and_occupy(canp, mailbox); + // if all buffers are occupied, we cannot send + if (bufIdx == CAN_BUFFER_NOT_FOUND) + return; + + canp->stcTxMsg.stcIdentifier.bExtended = ctfp->IDE; + canp->stcTxMsg.stcIdentifier.u32Identifier = ctfp->IDE ? ctfp->EID : ctfp->SID; + // copy the data + for (i = 0; i < ctfp->DLC; i++) + canp->stcTxMsg.stcData.au8Data[i] = ctfp->data8[i]; + // CanfdModeClassic + canp->stcTxMsg.stcData.u8DataLengthCode = ctfp->DLC; + canp->stcTxMsg.bCanfd = FALSE; + + Canfd_TransmitMsg(canp->can, bufIdx, &canp->stcTxMsg); +} + +/** + * @brief Determines whether a frame has been received. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * + * @return The queue space availability. + * @retval false no space in the transmit queue. + * @retval true transmit slot available. + * + * @notapi + */ +bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) { + uint8_t idx = can_get_mailbox(mailbox, canp->is_rx_mailbox_occupied, sizeof(canp->is_rx_mailbox_occupied), false); + if (idx == CAN_BUFFER_NOT_FOUND) + return false; + return canp->is_rx_mailbox_occupied[idx]; + +} + +/** + * @brief Receives a frame from the input queue. + * + * @param[in] canp pointer to the @p CANDriver object + * @param[in] mailbox mailbox number, @p CAN_ANY_MAILBOX for any mailbox + * @param[out] crfp pointer to the buffer where the CAN frame is copied + * + * @notapi + */ +void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *crfp) { + int i; + // we receive all messages from all mailboxes + Canfd_ReceiveMsg(canp->can); + Canfd_GetBusStatus(canp->can); + + uint8_t bufIdx = can_get_and_free_rx_mailbox(canp, mailbox); + // no occupied buffers left + if (bufIdx == CAN_BUFFER_NOT_FOUND) + return; + + stc_canfd_msg_t *stcRxMsg = &canp->stcRxMsg[bufIdx]; + + // copy the frame + crfp->IDE = stcRxMsg->stcIdentifier.bExtended; + if (crfp->IDE) + crfp->EID = stcRxMsg->stcIdentifier.u32Identifier; + else + crfp->SID = stcRxMsg->stcIdentifier.u32Identifier; + crfp->DLC = stcRxMsg->stcData.u8DataLengthCode; + // copy the data + for (i = 0; i < crfp->DLC; i++) + crfp->data8[i] = stcRxMsg->stcData.au8Data[i]; + + // todo: +} + +#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__) +/** + * @brief Enters the sleep mode. + * @param[in] canp pointer to the @p CANDriver object + */ +void can_lld_sleep(CANDriver *canp) { +} + +/** + * @brief Enforces leaving the sleep mode. + * @param[in] canp pointer to the @p CANDriver object + */ +void can_lld_wakeup(CANDriver *canp) { +} +#endif /* CAN_USE_SLEEP_MODE */ + +#endif /* HAL_USE_CAN */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.h new file mode 100644 index 0000000000..0d428d81be --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/CANv2/hal_can_lld.h @@ -0,0 +1,369 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file CANv2/hal_can_lld.h + * @brief Cypress S6E2Cx CAN subsystem low level driver header. + * @author andreika + * + * @addtogroup CAN + * @{ + */ + +#ifndef HAL_CAN_LLD_H +#define HAL_CAN_LLD_H + +#if HAL_USE_CAN || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This switch defines whether the driver implementation supports + * a low power switch mode with automatic an wakeup feature. + */ +#define CAN_SUPPORTS_SLEEP TRUE + +/** + * @brief This implementation supports three transmit mailboxes. + */ +#define CAN_TX_MAILBOXES 3 // < CANFD_MESSAGE_TXBUFFER_COUNT + +/** + * @brief This implementation supports two receive mailboxes. + */ +#define CAN_RX_MAILBOXES 3 // < CANFD_MESSAGE_RXBUFFER_COUNT + +// check mailbox counts +#if CAN_TX_MAILBOXES > CANFD_MESSAGE_TXBUFFER_COUNT +#error CAN_TX_MAILBOXES > CANFD_MESSAGE_TXBUFFER_COUNT +#endif + +#if CAN_RX_MAILBOXES > CANFD_MESSAGE_RXBUFFER_COUNT +#error CAN_RX_MAILBOXES > CANFD_MESSAGE_RXBUFFER_COUNT +#endif + +#define CAN_IDE_STD 0 /**< @brief Standard id. */ +#define CAN_IDE_EXT 1 /**< @brief Extended id. */ + +#define CAN_RTR_DATA 0 /**< @brief Data frame. */ +#define CAN_RTR_REMOTE 1 /**< @brief Remote frame. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief CAN pedantic errors report. + * @details Use of this option is IRQ-intensive. + */ +#if !defined(CYPRESS_CAN_REPORT_ALL_ERRORS) || defined(__DOXYGEN__) +#define CYPRESS_CAN_REPORT_ALL_ERRORS FALSE +#endif + +/** + * @brief CAN0 driver enable switch. + * @details If set to @p TRUE the support for CAN0 is included. + */ +#if !defined(CYPRESS_CAN_USE_CAN0) || defined(__DOXYGEN__) +#define CYPRESS_CAN_USE_CAN0 FALSE +#endif + +/** + * @brief CAN1 driver enable switch. + * @details If set to @p TRUE the support for CAN1 is included. + */ +#if !defined(CYPRESS_CAN_USE_CAN1) || defined(__DOXYGEN__) +#define CYPRESS_CAN_USE_CAN1 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CYPRESS_CAN_USE_CAN0 && !CYPRESS_CAN_USE_CAN1 +#error "CAN driver activated but no CAN peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an CAN driver. + */ +typedef struct CANDriver CANDriver; + +/** + * @brief Type of a transmission mailbox index. + */ +typedef uint32_t canmbx_t; + +#if (CAN_ENFORCE_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Type of a CAN notification callback. + * + * @param[in] canp pointer to the @p CANDriver object triggering the + * callback + * @param[in] flags flags associated to the mailbox callback + */ +typedef void (*can_callback_t)(CANDriver *canp, uint32_t flags); +#endif + +/** + * @brief CAN transmission frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + uint64_t data64[1]; /**< @brief Frame data. */ + }; +} CANTxFrame; + +/** + * @brief CAN received frame. + * @note Accessing the frame data as word16 or word32 is not portable because + * machine data endianness, it can be still useful for a quick filling. + */ +typedef struct { + struct { + uint8_t FMI; /**< @brief Filter id. */ + uint16_t TIME; /**< @brief Time stamp. */ + }; + struct { + uint8_t DLC:4; /**< @brief Data length. */ + uint8_t RTR:1; /**< @brief Frame type. */ + uint8_t IDE:1; /**< @brief Identifier type. */ + }; + union { + struct { + uint32_t SID:11; /**< @brief Standard identifier.*/ + }; + struct { + uint32_t EID:29; /**< @brief Extended identifier.*/ + }; + }; + union { + uint8_t data8[8]; /**< @brief Frame data. */ + uint16_t data16[4]; /**< @brief Frame data. */ + uint32_t data32[2]; /**< @brief Frame data. */ + uint64_t data64[1]; /**< @brief Frame data. */ + }; +} CANRxFrame; + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief CAN MCR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t mcr; + /** + * @brief CAN BTR register initialization data. + * @note Some bits in this register are enforced by the driver regardless + * their status in this field. + */ + uint32_t btr; +} CANConfig; + +/** + * @brief Structure representing an CAN driver. + */ +struct CANDriver { + /** + * @brief Driver state. + */ + canstate_t state; + /** + * @brief Current configuration data. + */ + const CANConfig *config; + /** + * @brief Transmission threads queue. + */ + threads_queue_t txqueue; + /** + * @brief Receive threads queue. + */ + threads_queue_t rxqueue; +#if (CAN_ENFORCE_USE_CALLBACKS == FALSE) || defined(__DOXYGEN__) + /** + * @brief One or more frames become available. + * @note After broadcasting this event it will not be broadcasted again + * until the received frames queue has been completely emptied. It + * is not broadcasted for each received frame. It is + * responsibility of the application to empty the queue by + * repeatedly invoking @p canReceive() when listening to this event. + * This behavior minimizes the interrupt served by the system + * because CAN traffic. + * @note The flags associated to the listeners will indicate which + * receive mailboxes become non-empty. + */ + event_source_t rxfull_event; + /** + * @brief One or more transmission mailbox become available. + * @note The flags associated to the listeners will indicate which + * transmit mailboxes become empty. + * @note The upper 16 bits are transmission error flags associated + * to the transmit mailboxes. + */ + event_source_t txempty_event; + /** + * @brief A CAN bus error happened. + * @note The flags associated to the listeners will indicate that + * receive error(s) have occurred. + * @note In this implementation the upper 16 bits are filled with the + * unprocessed content of the ESR register. + */ + event_source_t error_event; +#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__) + /** + * @brief Entering sleep state event. + */ + event_source_t sleep_event; + /** + * @brief Exiting sleep state event. + */ + event_source_t wakeup_event; +#endif /* CAN_USE_SLEEP_MODE */ +#else /* CAN_ENFORCE_USE_CALLBACKS == TRUE */ + /** + * @brief One or more frames become available. + * @note After calling this function it will not be called again + * until the received frames queue has been completely emptied. It + * is not called for each received frame. It is + * responsibility of the application to empty the queue by + * repeatedly invoking @p chTryReceiveI(). + * This behavior minimizes the interrupt served by the system + * because CAN traffic. + */ + can_callback_t rxfull_cb; + /** + * @brief One or more transmission mailbox become available. + * @note The flags associated to the callback will indicate which + * transmit mailboxes become empty. + */ + can_callback_t txempty_cb; + /** + * @brief A CAN bus error happened. + */ + can_callback_t error_cb; +#if (CAN_USE_SLEEP_MODE == TRUE) || defined (__DOXYGEN__) + /** + * @brief Exiting sleep state. + */ + can_callback_t wakeup_cb; +#endif +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CAN registers. + */ + stc_canfdn_t *can; + + /** + * @brief PDL CAN config structure. + */ + stc_canfd_config_t stcCanfdConfig; + + /** + * @brief Used to control the buffers' emptiness. + */ + bool is_rx_mailbox_occupied[CAN_RX_MAILBOXES]; + bool is_tx_mailbox_occupied[CAN_TX_MAILBOXES]; + + /** + * @brief Temporary used to copy the received message from the interrupt handler to the caller (under the sys-lock). + */ + stc_canfd_msg_t stcRxMsg[CAN_RX_MAILBOXES]; + /** + * @brief Temporary used to send the message + */ + stc_canfd_msg_t stcTxMsg; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if CYPRESS_CAN_USE_CAN0 || defined(__DOXYGEN__) +extern CANDriver CAND1; +#endif + +#if CYPRESS_CAN_USE_CAN1 || defined(__DOXYGEN__) +extern CANDriver CAND2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void can_lld_init(void); + void can_lld_start(CANDriver *canp); + void can_lld_stop(CANDriver *canp); + bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox); + void can_lld_transmit(CANDriver *canp, + canmbx_t mailbox, + const CANTxFrame *crfp); + bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox); + void can_lld_receive(CANDriver *canp, + canmbx_t mailbox, + CANRxFrame *ctfp); +#if CAN_USE_SLEEP_MODE + void can_lld_sleep(CANDriver *canp); + void can_lld_wakeup(CANDriver *canp); +#endif /* CAN_USE_SLEEP_MODE */ + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_CAN */ + +#endif /* HAL_CAN_LLD_H */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/driver.mk b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/driver.mk new file mode 100644 index 0000000000..18b1261123 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/driver.mk @@ -0,0 +1,13 @@ +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +ifeq ($(USE_SMART_BUILD),yes) +ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.c +endif +else +PLATFORMSRC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.c +endif + +PLATFORMINC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/GPIOv2 diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/gpio_s6e2_common.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/gpio_s6e2_common.h new file mode 100644 index 0000000000..8ff0076c70 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/gpio_s6e2_common.h @@ -0,0 +1,66 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv2/gpio_s6e2_common.h + * @author andreika + * + * @addtogroup PAL + * @{ + */ + +#pragma once + +// copied from s6e2c5xl.h +#ifndef bFM4_GPIO_PDIR3_P0 +#define bFM4_GPIO_PDIR3_P0 *((volatile uint8_t *)(0x42DE6180UL)) +#endif + +#ifndef bFM4_GPIO_PDOR3_P0 +#define bFM4_GPIO_PDOR3_P0 *((volatile uint8_t *)(0x42DE8180UL)) +#endif + +#ifndef bFM4_GPIO_PDIR5_P0 +#define bFM4_GPIO_PDIR5_P0 *((volatile uint8_t *)(0x42DE6280UL)) +#endif + +#ifndef bFM4_GPIO_PDOR5_P0 +#define bFM4_GPIO_PDOR5_P0 *((volatile uint8_t *)(0x42DE8280UL)) +#endif + +#ifndef bFM4_GPIO_PDIR9_P0 +#define bFM4_GPIO_PDIR9_P0 *((volatile uint8_t *)(0x42DE6480UL)) +#endif + +#ifndef bFM4_GPIO_PDOR9_P0 +#define bFM4_GPIO_PDOR9_P0 *((volatile uint8_t *)(0x42DE8480UL)) +#endif + +#ifndef bFM4_GPIO_PDIRB_P0 +#define bFM4_GPIO_PDIRB_P0 *((volatile uint8_t *)(0x42DE6580UL)) +#endif + +#ifndef bFM4_GPIO_PDORB_P0 +#define bFM4_GPIO_PDORB_P0 *((volatile uint8_t *)(0x42DE8580UL)) +#endif + +#ifndef bFM4_GPIO_PDIRF_P0 +#define bFM4_GPIO_PDIRF_P0 *((volatile uint8_t *)(0x42DE6780UL)) +#endif + +#ifndef bFM4_GPIO_PDORF_P0 +#define bFM4_GPIO_PDORF_P0 *((volatile uint8_t *)(0x42DE8780UL)) +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.c new file mode 100644 index 0000000000..9d748a7a45 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.c @@ -0,0 +1,669 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv2/hal_pal_lld.c + * @brief PAL subsystem low level driver. + * @author andreika + * + * @addtogroup PAL + * @{ + */ + +#include "osal.h" +#include "hal.h" + +#include + + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#include "gpio_s6e2_common.h" + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +// port P8x doesn't have PCR register, so we fake it for 'fm4_gpio_ports' table consistency. +static __IO uint32_t FM4_FAKE_REG = 0; + +static uint16_t defMask0[PADS_PER_PORT] = { 0 }; +static uint16_t defMask1[PADS_PER_PORT] = { 1<<0, 1<<1, 1<<2, 1<<3, 1<<4, 1<<5, 1<<6, 1<<7, 1<<8, 1<<9, 1<<10, 1<<11, 1<<12, 1<<13, 1<<14, 1<<15, }; + +// special bitmasks for paralleled power pins on Hellen-cypress board +#if HAL_USE_PAL_POWER_PINS +static uint16_t pc3PowerMask1[PADS_PER_PORT] = { 1<<0, 1<<1, 1<<2, 1<<3, 1<<4, 1<<5, 1<<6, 1<<7, 1<<8, + (1<<9)|(1<<10), (1<<9)|(1<<10), // P39 || P3A + (1<<11)|(1<<12), (1<<11)|(1<<12),// P3B || P3C + (1<<13)|(1<<14), (1<<13)|(1<<14),// P3D || P3E + 1<<15, }; +static uint16_t pc4PowerMask1[PADS_PER_PORT] = { (1<<0)|(1<<1), (1<<0)|(1<<1), // P40 || P41 + (1<<2)|(1<<3), (1<<2)|(1<<3), // P42 || P43 + (1<<4)|(1<<5), (1<<4)|(1<<5), // P44 || P45 + 1<<6, 1<<7, 1<<8, 1<<9, 1<<10, 1<<11, 1<<12, 1<<13, 1<<14, 1<<15,}; +#else +#error Are you sure you are using the right halconf.h config? +#define pc3PowerMask1 defMask1 +#define pc4PowerMask1 defMask1 +#endif + +// we store it as a pre-defined const table to save some RAM +const GPIO_TypeDef fm4_gpio_ports[TOTAL_PORTS] = { +// port 0x0 + { 0, &FM4_GPIO_PFR0, &FM4_GPIO_PCR0, &FM4_GPIO_PZR0, &FM4_GPIO_DDR0, &FM4_GPIO_PDIR0, &FM4_GPIO_PDOR0, &bFM4_GPIO_PDIR0_P0, &bFM4_GPIO_PDOR0_P0, { defMask0, defMask1 } }, +// port 0x1 + { 1, &FM4_GPIO_PFR1, &FM4_GPIO_PCR1, &FM4_GPIO_PZR1, &FM4_GPIO_DDR1, &FM4_GPIO_PDIR1, &FM4_GPIO_PDOR1, &bFM4_GPIO_PDIR1_P0, &bFM4_GPIO_PDOR1_P0, { defMask0, defMask1 } }, +// port 0x2 + { 2, &FM4_GPIO_PFR2, &FM4_GPIO_PCR2, &FM4_GPIO_PZR2, &FM4_GPIO_DDR2, &FM4_GPIO_PDIR2, &FM4_GPIO_PDOR2, &bFM4_GPIO_PDIR2_P0, &bFM4_GPIO_PDOR2_P0, { defMask0, defMask1 } }, +// port 0x3 + { 3, &FM4_GPIO_PFR3, &FM4_GPIO_PCR3, &FM4_GPIO_PZR3, &FM4_GPIO_DDR3, &FM4_GPIO_PDIR3, &FM4_GPIO_PDOR3, &bFM4_GPIO_PDIR3_P0, &bFM4_GPIO_PDOR3_P0, { defMask0, pc3PowerMask1 } }, +// port 0x4 + { 4, &FM4_GPIO_PFR4, &FM4_GPIO_PCR4, &FM4_GPIO_PZR4, &FM4_GPIO_DDR4, &FM4_GPIO_PDIR4, &FM4_GPIO_PDOR4, &bFM4_GPIO_PDIR4_P0, &bFM4_GPIO_PDOR4_P0, { defMask0, pc4PowerMask1 } }, +// port 0x5 + { 5, &FM4_GPIO_PFR5, &FM4_GPIO_PCR5, &FM4_GPIO_PZR5, &FM4_GPIO_DDR5, &FM4_GPIO_PDIR5, &FM4_GPIO_PDOR5, &bFM4_GPIO_PDIR5_P0, &bFM4_GPIO_PDOR5_P0, { defMask0, defMask1 } }, +// port 0x6 + { 6, &FM4_GPIO_PFR6, &FM4_GPIO_PCR6, &FM4_GPIO_PZR6, &FM4_GPIO_DDR6, &FM4_GPIO_PDIR6, &FM4_GPIO_PDOR6, &bFM4_GPIO_PDIR6_P0, &bFM4_GPIO_PDOR6_P0, { defMask0, defMask1 } }, +// port 0x7 + { 7, &FM4_GPIO_PFR7, &FM4_GPIO_PCR7, &FM4_GPIO_PZR7, &FM4_GPIO_DDR7, &FM4_GPIO_PDIR7, &FM4_GPIO_PDOR7, &bFM4_GPIO_PDIR7_P0, &bFM4_GPIO_PDOR7_P0, { defMask0, defMask1 } }, +// port 0x8 + { 8, &FM4_GPIO_PFR8, &FM4_FAKE_REG, &FM4_GPIO_PZR8, &FM4_GPIO_DDR8, &FM4_GPIO_PDIR8, &FM4_GPIO_PDOR8, &bFM4_GPIO_PDIR8_P0, &bFM4_GPIO_PDOR8_P0, { defMask0, defMask1 } }, +// port 0x9 + { 9, &FM4_GPIO_PFR9, &FM4_GPIO_PCR9, &FM4_GPIO_PZR9, &FM4_GPIO_DDR9, &FM4_GPIO_PDIR9, &FM4_GPIO_PDOR9, &bFM4_GPIO_PDIR9_P0, &bFM4_GPIO_PDOR9_P0, { defMask0, defMask1 } }, +// port 0xA + { 10, &FM4_GPIO_PFRA, &FM4_GPIO_PCRA, &FM4_GPIO_PZRA, &FM4_GPIO_DDRA, &FM4_GPIO_PDIRA, &FM4_GPIO_PDORA, &bFM4_GPIO_PDIRA_P0, &bFM4_GPIO_PDORA_P0, { defMask0, defMask1 } }, +// port 0xB + { 11, &FM4_GPIO_PFRB, &FM4_GPIO_PCRB, &FM4_GPIO_PZRB, &FM4_GPIO_DDRB, &FM4_GPIO_PDIRB, &FM4_GPIO_PDORB, &bFM4_GPIO_PDIRB_P0, &bFM4_GPIO_PDORB_P0, { defMask0, defMask1 } }, +// port 0xC + { 12, &FM4_GPIO_PFRC, &FM4_GPIO_PCRC, &FM4_GPIO_PZRC, &FM4_GPIO_DDRC, &FM4_GPIO_PDIRC, &FM4_GPIO_PDORC, &bFM4_GPIO_PDIRC_P0, &bFM4_GPIO_PDORC_P0, { defMask0, defMask1 } }, +// port 0xD + { 13, &FM4_GPIO_PFRD, &FM4_GPIO_PCRD, &FM4_GPIO_PZRD, &FM4_GPIO_DDRD, &FM4_GPIO_PDIRD, &FM4_GPIO_PDORD, &bFM4_GPIO_PDIRD_P0, &bFM4_GPIO_PDORD_P0, { defMask0, defMask1 } }, +// port 0xE + { 14, &FM4_GPIO_PFRE, &FM4_GPIO_PCRE, &FM4_GPIO_PZRE, &FM4_GPIO_DDRE, &FM4_GPIO_PDIRE, &FM4_GPIO_PDORE, &bFM4_GPIO_PDIRE_P0, &bFM4_GPIO_PDORE_P0, { defMask0, defMask1 } }, +// port 0xF + { 15, &FM4_GPIO_PFRF, &FM4_GPIO_PCRF, &FM4_GPIO_PZRF, &FM4_GPIO_DDRF, &FM4_GPIO_PDIRF, &FM4_GPIO_PDORF, &bFM4_GPIO_PDIRF_P0, &bFM4_GPIO_PDORF_P0, { defMask0, defMask1 } }, +}; + +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__) +/** + * @brief Event records for the 16 GPIO EXTI channels. + */ +palevent_t _pal_events[CYPRESS_GPIO_NUM_LINES]; + +#define ExintNone ExintInstanceIndexMax + +// todo: The tables below must match the PDL_PERIPHERAL_ENABLE_EXINTx definitions inside pdl_user.h! Maybe add the compile-time checks? +#if 0 +#if (PDL_EXINT_INSTANCE_COUNT != 11) +#error Please update the tables below if you changed the PDL_PERIPHERAL_ENABLE_EXINTx settings! +#endif +#endif +static en_exint_instance_index_t instanceIdxFromLine[CYPRESS_GPIO_NUM_LINES] = { + /* 0 */ ExintNone, ExintNone, ExintNone, ExintNone, ExintNone, ExintNone, ExintNone, ExintNone, + /* 8 */ ExintInstanceIndexExint8, ExintInstanceIndexExint9, ExintInstanceIndexExint10, ExintInstanceIndexExint11, ExintNone, ExintInstanceIndexExint13, ExintNone, ExintNone, + /* 16*/ ExintNone, ExintNone, ExintNone, ExintInstanceIndexExint19, ExintNone, ExintNone, ExintNone, ExintNone, + /* 24*/ ExintInstanceIndexExint24, ExintInstanceIndexExint25, ExintInstanceIndexExint26, ExintInstanceIndexExint27, ExintNone, ExintNone, ExintNone, ExintInstanceIndexExint31, +}; + +static const uint8_t P1xLines[] = { + 8, PAL_NOLINE, PAL_NOLINE, PAL_NOLINE, PAL_NOLINE, PAL_NOLINE, PAL_NOLINE, PAL_NOLINE, + 10, 24, PAL_NOLINE, 11, PAL_NOLINE, PAL_NOLINE, 26, 27 +}; + +ioportid_t _pal_linePorts[CYPRESS_GPIO_NUM_LINES] = { + /* 0 */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + /* 8 */ GPIOB, GPIOC, GPIOB, GPIOB, NULL, GPIOJ, NULL, NULL, + /* 16*/ NULL, NULL, NULL, GPIOD, NULL, NULL, NULL, NULL, + /* 24*/ GPIOB, GPIOC, GPIOB, GPIOB, NULL, NULL, NULL, NULL, +}; + +iopadid_t _pal_linePads[CYPRESS_GPIO_NUM_LINES] = { + /* 0 */ 0, 0, 0, 0, 0, 0, 0, 0, + /* 8 */ 0, 9, 8, 11, 0, 7, 0, 0, + /* 16 */ 0, 0, 0, 2, 0, 0, 0, 0, + /* 24 */ 9, 5, 14, 15, 0, 0, 0, 0, +}; + +static en_exint_level_t bothEdges[CYPRESS_GPIO_NUM_LINES]; + +stc_exint_config_t stcExtIntConfig; +bool wasExtIntInit = false; + +static void _pal_lld_irq_handler(uint8_t channel) { + // change the polarity if needed + if (bothEdges[channel] != 0) { + int isHigh = pal_lld_readpad(_pal_linePorts[channel], _pal_linePads[channel]); + + if (isHigh && bothEdges[channel] == ExIntRisingEdge) { + bothEdges[channel] = ExIntFallingEdge; + Exint_SetDetectMode(channel, bothEdges[channel]); + + _pal_isr_code(channel); + } + else if (!isHigh && bothEdges[channel] == ExIntFallingEdge) { + bothEdges[channel] = ExIntRisingEdge; + Exint_SetDetectMode(channel, bothEdges[channel]); + + _pal_isr_code(channel); + } + } else { + _pal_isr_code(channel); + } +} + +ioline_t _pal_lld_getpadline(ioportid_t port, iopadid_t pad) { + if (port == GPIOB) /* P1x */ { + return P1xLines[pad]; + } + else if (port == GPIOC) /* P2x */ { + if (pad == 5) + return 25; + else if (pad == 9) + return 9; + } + else if (port == GPIOD) /* P3x */ { + if (pad == 2) + return 19; + } + else if (port == GPIOJ) /* PCx */ { + if (pad == 7) + return 13; + } + return PAL_NOLINE; +} + +#endif + +#define AN_NONE -1 + +static int8_t P1xAnalogChannels[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 +}; + +static int8_t P2xAnalogChannels[] = { + AN_NONE, AN_NONE, 31, 30, 29, 28, 27, 26, 25, 24, AN_NONE, AN_NONE, AN_NONE, AN_NONE, AN_NONE, AN_NONE +}; + +static int8_t getAnalogChannel(ioportid_t port, iopadid_t pad) { + if (port == GPIOB) /* P1x */ { + return P1xAnalogChannels[pad]; + } + else if (port == GPIOC) /* P2x */ { + return P2xAnalogChannels[pad]; + } + // todo: add more cases + return AN_NONE; +} + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void resetAnalogChannel(int adcChannel) { + if (adcChannel >= 0 && adcChannel < 32) + *(&bFM4_GPIO_ADE_AN00 + 4 * adcChannel) = 0; +} + +// todo: Is there a better way to configure pins? The Cypress PDL leaves us no choice with those SetPinFunc_XXX() macros? +// this is based on gpio_s6e2c5xl.h +static void setPadModeAlternate(ioportid_t port, uint8_t pad, iomode_t mode) { + switch (mode) { + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_ANALOG): + if (port == GPIOB) { // P1x + switch (pad) { + case 0: // P10 + SetPinFunc_AN00(); + break; + case 1: // P11 + SetPinFunc_AN01(); + break; + case 2: // P12 + SetPinFunc_AN02(); + break; + case 3: // P13 + SetPinFunc_AN03(); + break; + case 4: // P14 + SetPinFunc_AN04(); + break; + case 5: // P15 + SetPinFunc_AN05(); + break; + case 6: // P16 + SetPinFunc_AN06(); + break; + case 7: // P17 + SetPinFunc_AN07(); + break; + case 8: // P18 + SetPinFunc_AN08(); + break; + case 9: // P19 + SetPinFunc_AN09(); + break; + case 10:// P1A + SetPinFunc_AN10(); + break; + case 11:// P1B + SetPinFunc_AN11(); + break; + case 12:// P1C + SetPinFunc_AN12(); + break; + case 13:// P1D + SetPinFunc_AN13(); + break; + case 14:// P1E + SetPinFunc_AN14(); + break; + case 15:// P1F + SetPinFunc_AN15(); + break; + } + break; + } + else if (port == GPIOC) { // P2x + switch (pad) { + case 2: // P22 + SetPinFunc_AN31(); + break; + case 3: // P23 + SetPinFunc_AN30(); + break; + case 4: // P24 + SetPinFunc_AN29(); + break; + case 5: // P25 + SetPinFunc_AN28(); + break; + case 7: // P27 + SetPinFunc_AN27(); + break; + case 8: // P28 + SetPinFunc_AN26(); + break; + case 9: // P29 + SetPinFunc_AN25(); + break; + case 10:// P2A + SetPinFunc_AN24(); + break; + } + } + break; + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_SPI): + if (port == GPIOG) { // P7x + switch (pad) { + case 8: // P78 (SPI6_MISO) + SetPinFunc_SIN6_0(); + break; + case 9: // P79 (SPI6_MOSI) + SetPinFunc_SOT6_0(); + break; + case 10:// P7A (SPI6_SCK) + SetPinFunc_SCK6_0(); + break; + case 11:// P7B (SPI6_CS0) + SetPinFunc_SCS60_0(); + break; + } + } + else if (port == GPIOH) { // PAx + switch (pad) { + case 8: // PA8 (SPI7_MISO) + SetPinFunc_SIN7_0(); + break; + case 9: // PA9 (SPI7_MOSI) + SetPinFunc_SOT7_0(); + break; + case 10:// PAA (SPI7_SCK) + SetPinFunc_SCK7_0(); + break; + case 11:// PAB (SPI7_CS0) + SetPinFunc_SCS70_0(); + break; + case 12:// PAC (SPI7_CS1) + SetPinFunc_SCS71_0(); + break; + } + } + break; + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_I2C): + if (port == GPIOH) { // PAx + switch (pad) { + case 13:// PAD (I2C3_SCL) + SetPinFunc_SCK3_0(); + break; + case 14:// PAE (I2C3_SDA) + SetPinFunc_SOT3_0(); + break; + } + } + break; + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_UART): + if (port == GPIOC) { // P2x + switch (pad) { + case 1: // P21 (UART0_RX) + SetPinFunc_SIN0_0(); + break; + case 2: // P22 (UART0_TX) + SetPinFunc_SOT0_0(); + break; + } + } + break; + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_CAN): + // this is S6E2Gx version + if (port == GPIOB) { // P1x + switch (pad) { + case 6: // P16 (CAN0_RX) + SetPinFunc_RX0_0(); + break; + case 7: // P17 (CAN0_TX) + SetPinFunc_TX0_0(); + break; + } + } + // this is S6E2Cx version + else if (port == GPIOG) { // P7x + switch (pad) { + case 13:// P7D (CAN2_RX) + SetPinFunc_RX2_0(); + break; + case 14:// P7E (CAN2_TX) + SetPinFunc_TX2_0(); + break; + } + } + break; + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_EXTINT): + if (port == GPIOB) { // P1x + switch (pad) { + case 0:// P10 (CRANK) + SetPinFunc_INT08_0(0u); + break; + case 8:// P18 (CAM) + SetPinFunc_INT10_0(0u); + break; + case 9:// P19 (VSS) + SetPinFunc_INT24_1(0u); + break; + case 11:// P1B (AUX1) + SetPinFunc_INT11_0(0u); + break; + case 14:// P1E (AUX2) + SetPinFunc_INT26_1(0u); + break; + case 15:// P1F (AUX3) + SetPinFunc_INT27_1(0u); + break; + } + } + else if (port == GPIOC) { // P2x + switch (pad) { + case 5:// P25 (AUX4) + SetPinFunc_INT25_0(0u); + break; + case 9:// P29 (RES_IN) +#ifdef SetPinFunc_INT09_2 + SetPinFunc_INT09_2(0u); +#endif + break; + } + } + else if (port == GPIOD) { // P3x + switch (pad) { + case 2:// P32 (DRV_MISO) + SetPinFunc_INT19_0(0u); + break; + } + } + else if (port == GPIOJ) { // PCx + switch (pad) { + case 7:// PC7 (RES2) + SetPinFunc_INT13_0(0u); + break; + } + } + + // we need to re-configure the edge interrupt + int line = PAL_LINE(port, pad); + if (bothEdges[line] != 0) { + int isHigh = pal_lld_readpad(port, pad); + bothEdges[line] = (isHigh != 0) ? ExIntFallingEdge : ExIntRisingEdge; + Exint_SetDetectMode(line, bothEdges[line]); + } + break; + } +} + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +void _pal_lld_setpadmode(ioportid_t port, + uint8_t pad, + iomode_t mode) { + + osalDbgAssert(pad < PADS_PER_PORT, "pal_lld_setpadmode() #1, invalid pad"); + + uint32_t padMask = port->padMask[1][pad]; + + switch (mode) { + case PAL_MODE_RESET: + case PAL_MODE_INPUT: + case PAL_MODE_INPUT_PULLDOWN: // todo: we have no pulldown, is it ok to be here? + *port->PCR &= ~padMask; // no pull-up + *port->DDR &= ~padMask; // dir=input + *port->PFR &= ~padMask; // gpio + resetAnalogChannel(getAnalogChannel(port, pad)); + break; + case PAL_MODE_OUTPUT_PUSHPULL: + *port->PZR &= ~padMask; // no open-drain + *port->DDR |= padMask; // dir=output + *port->PFR &= ~padMask; // gpio + resetAnalogChannel(getAnalogChannel(port, pad)); + break; + case PAL_MODE_OUTPUT_OPENDRAIN: + *port->PZR |= padMask; // open-drain (and no-pullup) + *port->DDR |= padMask; // dir=output + *port->PFR &= ~padMask; // gpio + resetAnalogChannel(getAnalogChannel(port, pad)); + break; + case PAL_MODE_INPUT_PULLUP: + *port->PCR |= padMask; // pull-up + *port->DDR &= ~padMask; // dir=input + *port->PFR &= ~padMask; // gpio + resetAnalogChannel(getAnalogChannel(port, pad)); + break; + case PAL_MODE_UNCONNECTED: + case PAL_MODE_INPUT_ANALOG: + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_ANALOG): + setPadModeAlternate(port, pad, PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_ANALOG)); + break; + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_SPI): + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_I2C): + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_UART): + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_CAN): + case PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_EXTINT): + setPadModeAlternate(port, pad, mode); + break; + } + + // a little 'hack' for complex pin modes like MISO+PULLUP + if (mode & PAL_STM32_PUPDR_PULLUP) { + *port->PCR |= padMask; // pull-up + } + +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Kinetis I/O ports configuration. + * @details Ports A-E clocks enabled. + * + * @param[in] config the Kinetis ports configuration + * + * @notapi + */ +void _pal_lld_init(void) { + PDL_ZERO_STRUCT(stcExtIntConfig); + stcExtIntConfig.bTouchNvic = TRUE; + + memset(bothEdges, 0, sizeof(bothEdges)); + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < CYPRESS_GPIO_NUM_LINES; i++) { + _pal_init_event(i); + } +#endif + + wasExtIntInit = false; +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode) { + + int i; + + (void)mask; + + for (i = 0; i < PADS_PER_PORT; i++) { + pal_lld_setpadmode(port, i, mode); + } +} + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + +void _pal_lld_setpadeventhandler(ioline_t line, int edgeLevel, pal_padeventhandler_t handler) { + // add a new line to the extint config + stcExtIntConfig.abEnable[instanceIdxFromLine[line]] = TRUE; // INT00 + stcExtIntConfig.aenLevel[instanceIdxFromLine[line]] = (en_exint_level_t)edgeLevel; + stcExtIntConfig.apfnExintCallback[instanceIdxFromLine[line]] = (func_ptr_arg1_t)handler; + + if (wasExtIntInit) { + Exint_DeInit(); + wasExtIntInit = false; + } + + if (!wasExtIntInit) { + Exint_Init(&stcExtIntConfig); + wasExtIntInit = true; + } + + Exint_EnableChannel(line); +} + +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) { + en_exint_level_t cfg; + + ioline_t line = PAL_LINE(port, pad); + if (line == PAL_NOLINE) + return; + if (instanceIdxFromLine[line] == ExintNone) + return; + + bothEdges[line] = 0; + + switch (mode) { + case PAL_EVENT_MODE_RISING_EDGE: + cfg = ExIntRisingEdge; + break; + case PAL_EVENT_MODE_FALLING_EDGE: + cfg = ExIntFallingEdge; + break; + case PAL_EVENT_MODE_BOTH_EDGES: +#if 0 // [andreika]: unfortunately our FM4 doesn't support it :( + cfg = ExIntBothEdge; +#else + _pal_lld_setpadmode(port, pad, PAL_MODE_INPUT); + cfg = pal_lld_readpad(port, pad) != 0 ? ExIntFallingEdge : ExIntRisingEdge; + // save the initial edge state so we can change it in IRQ handler + bothEdges[line] = cfg; +#endif + break; + case PAL_EVENT_MODE_DISABLED: + default: + _pal_lld_disablepadevent(port, pad); + return; + } + + // Set pin function before enabling external interrupt channel! + _pal_lld_setpadmode(port, pad, PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_EXTINT)); + + _pal_lld_setpadeventhandler(line, cfg, _pal_lld_irq_handler); +} + +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) { + ioline_t line = PAL_LINE(port, pad); + if (line == PAL_NOLINE) + return; + stcExtIntConfig.abEnable[instanceIdxFromLine[line]] = FALSE; + bothEdges[line] = 0; + + Exint_DisableChannel(line); + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(pad); +#endif +} + +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ + +#endif /* HAL_USE_PAL */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.h new file mode 100644 index 0000000000..80478dcda9 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/GPIOv2/hal_pal_lld.h @@ -0,0 +1,453 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file GPIOv2/hal_pal_lld.h + * @brief PAL subsystem low level driver header. + * @author andreika + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H_ +#define HAL_PAL_LLD_H_ + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Unsupported modes and specific modes */ +/*===========================================================================*/ + +// STM32-compatible macro +#define PAL_MODE_ALTERNATE(x) (0x10 + x) + +/*===========================================================================*/ +/* I/O Ports Types and constants. */ +/*===========================================================================*/ + +#define TOTAL_PORTS 16 +#define PADS_PER_PORT 16 + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 16 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFFFFFFFF) + +/* Specifies palInit() without parameter, required until all platforms will + be updated to the new style.*/ +#define PAL_NEW_INIT + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Type of an I/O line. + */ +typedef uint32_t ioline_t; + +/** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + + +/** + * @brief Port Identifier. + * @details This type can be a scalar or some kind of pointer, do not make + * any assumption about it, use the provided macros when populating + * variables of this type. + */ + + #ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ +// Parts taken from FM4_GPIO_TypeDef +typedef struct { + uint8_t idx; + __IO uint32_t * const PFR; // port function + __IO uint32_t * const PCR; // pull-up + __IO uint32_t * const PZR; // open-drain + __IO uint32_t * const DDR; // direction (input/output) + __IO uint32_t * const portDIR; // read port input + __IO uint32_t * const portDOR; // write port output + __IO uint8_t * const padDIR; // read pad + __IO uint8_t * const padDOR; // write pad + uint16_t *padMask[2]; // write mask for pal_lld_writepad() [PADS_PER_PORT] +} GPIO_TypeDef; + +extern const GPIO_TypeDef fm4_gpio_ports[TOTAL_PORTS]; +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +typedef GPIO_TypeDef *ioportid_t; + +// port 0x0 +#define GPIOA ((GPIO_TypeDef *)&fm4_gpio_ports[0x0]) +// port 0x1 +#define GPIOB ((GPIO_TypeDef *)&fm4_gpio_ports[0x1]) +// port 0x2 +#define GPIOC ((GPIO_TypeDef *)&fm4_gpio_ports[0x2]) +// port 0x3 +#define GPIOD ((GPIO_TypeDef *)&fm4_gpio_ports[0x3]) +// port 0x4 +#define GPIOE ((GPIO_TypeDef *)&fm4_gpio_ports[0x4]) +// port 0x5 +#define GPIOF ((GPIO_TypeDef *)&fm4_gpio_ports[0x5]) +// port 0x6 +// --- skip port 0x6 +// port 0x7 +#define GPIOG ((GPIO_TypeDef *)&fm4_gpio_ports[0x7]) +// port 0x8 +// --- skip port 0x8 +// port 0x9 +// --- skip port 0x9 +// port 0xa +#define GPIOH ((GPIO_TypeDef *)&fm4_gpio_ports[0xa]) +// port 0xb +#define GPIOI ((GPIO_TypeDef *)&fm4_gpio_ports[0xb]) +// port 0xc +#define GPIOJ ((GPIO_TypeDef *)&fm4_gpio_ports[0xc]) +// port 0xd +// --- skip port 0xd +// port 0xe +// --- skip port 0xe +// port 0xf +#define GPIOK ((GPIO_TypeDef *)&fm4_gpio_ports[0xf]) + +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + +/** + * @brief Handler used by _pal_lld_setpadeventhandler(). + */ +typedef void (*pal_padeventhandler_t)(uint8_t); + +/*===========================================================================*/ +/* I/O Ports Identifiers. */ +/*===========================================================================*/ + +/** + * @brief GPIO port identifiers. + */ +#define IOPORT1 GPIOA +#define IOPORT2 GPIOB +#define IOPORT3 GPIOC +#define IOPORT4 GPIOD +#define IOPORT5 GPIOE +#define IOPORT6 GPIOF +#define IOPORT7 GPIOG +#define IOPORT8 GPIOH +#define IOPORT9 GPIOI +#define IOPORT10 GPIOJ +#define IOPORT11 GPIOK + +/** + * @name Line handling macros + * @{ + */ +/** + * @brief Forms a line identifier. + * @details A port/pad pair are encoded into an @p ioline_t type. The encoding + * of this type is platform-dependent. + */ +#define PAL_LINE(port, pad) ((ioline_t)_pal_lld_getpadline((port), (pad))) + +/** + * @brief Decodes a port identifier from a line identifier. + */ +#define PAL_PORT(line) (_pal_linePorts[(line)]) + +/** + * @brief Decodes a pad identifier from a line identifier. + */ +#define PAL_PAD(line) (_pal_linePads[(line)]) + +/** + * @brief Decodes a port index (0..4) from a port identifier. + */ +#define PAL_PORT_INDEX(port) ((uint32_t)(port->idx)) + +/** + * @brief Value identifying an invalid line. + */ +#define PAL_NOLINE 0U +/** @} */ + +/*===========================================================================*/ +/* Implementation, some of the following macros could be implemented as */ +/* functions, if so please put them in pal_lld.c. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) 0 + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) (void)bits + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) *((port)->padDIR + pad * 4) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +// [andreika]: We use portDOR instead of padDOR because we have twin power pads (connected on board for more current) +// [andreika]: For twin power pads, we use combined mask with 2 bits set simultaneously. +#define pal_lld_writepad(port, pad, bit) *((port)->portDOR) = ((*((port)->portDIR) & ~((port)->padMask[1][pad])) | (port)->padMask[bit][pad]) +//#define pal_lld_writepad(port, pad, bit) *((port)->padDOR + pad * 4) = bit + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +//#define pal_lld_setpad(port, pad) *((port)->padDOR + pad * 4) = 1 +#define pal_lld_setpad(port, pad) pal_lld_writepad(port, pad, 1) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +//#define pal_lld_clearpad(port, pad) *((port)->padDOR + pad * 4) = 0 +#define pal_lld_clearpad(port, pad) pal_lld_writepad(port, pad, 0) + +/** + * @brief Toggles a pad logical state. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_togglepad(port, pad) pal_lld_writepad(port, pad, ~(pal_lld_readpad(port, pad))) + +/** + * @brief Pad mode setup. + * @details This function programs a pad with the specified mode. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad mode + * + * @notapi + */ +#define pal_lld_setpadmode(port, pad, mode) \ + _pal_lld_setpadmode(port, pad, mode) + + +#if (PAL_USE_WAIT == TRUE) || (PAL_USE_CALLBACKS == TRUE) + +#define CYPRESS_GPIO_NUM_PORTS 16 +#define CYPRESS_GPIO_NUM_PADS 16 +#define CYPRESS_GPIO_NUM_LINES 32 + +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[PAL_LINE((port), (pad))] + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[(line)] + +extern palevent_t _pal_events[CYPRESS_GPIO_NUM_LINES]; +extern ioportid_t _pal_linePorts[CYPRESS_GPIO_NUM_LINES]; +extern iopadid_t _pal_linePads[CYPRESS_GPIO_NUM_LINES]; +#endif /* PAL_USE_WAIT */ + + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(void); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); + void _pal_lld_setpadmode(ioportid_t port, + uint8_t pad, + iomode_t mode); + uint8_t _pal_lld_readpad(ioportid_t port, + uint8_t pad); + void _pal_lld_writepad(ioportid_t port, + uint8_t pad, + uint8_t bit); +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + ioline_t _pal_lld_getpadline(ioportid_t port, iopadid_t pad); + + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); + + void _pal_lld_setpadeventhandler(ioline_t line, int edgeLevel, pal_padeventhandler_t handler); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/driver.mk b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/driver.mk new file mode 100644 index 0000000000..0fa9056969 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/driver.mk @@ -0,0 +1,7 @@ +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +PLATFORMSRC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.c + +PLATFORMINC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/PITv2 diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.c new file mode 100644 index 0000000000..00fb5aa4af --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.c @@ -0,0 +1,337 @@ +/* + ChibiOS - Copyright (C) 2014 Derek Mulcahy + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file PITv1/hal_gpt_lld.c + * @brief CYPRESS GPT subsystem low level driver source. + * @author andreika + * + * @addtogroup GPT + * @{ + */ + +#include +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +#include "pdl.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +// todo: fix 32-bit timer +#define USE_16BIT_TIMER +#define BT_16BIT_MAX_COUNT_VALUE 60000 // should be < 0xffff to fit the 16-bit register + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + * @note The driver GPTD1 allocates the complex timer PIT0 when enabled. + */ +#if CYPRESS_GPT_USE_BT0_BT1 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPTD2 driver identifier. + * @note The driver GPTD2 allocates the timer PIT1 when enabled. + */ +#if CYPRESS_GPT_USE_BT2_BT3 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPTD3 driver identifier. + * @note The driver GPTD3 allocates the timer PIT2 when enabled. + */ +#if CYPRESS_GPT_USE_BT4_BT5 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPTD4 driver identifier. + * @note The driver GPTD4 allocates the timer PIT3 when enabled. + */ +#if CYPRESS_GPT_USE_BT6_BT7 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +// [andreika]: IRQ handlers declared inside interrupts_fm4_type_b.c + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ + +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { +#ifdef USE_16BIT_TIMER + gptp->counter -= BT_16BIT_MAX_COUNT_VALUE; + if (gptp->counter > 0) { + // this is the last iteration, set the leftover + if (gptp->counter < BT_16BIT_MAX_COUNT_VALUE) { + // a little accuracy loss here, but it's ok + // (measured ~1ms drift on 1 minute interval, it's < 0.002%) + // todo: use Bt_Rt_ReadCurCnt()? + Bt_Rt_WriteCycleVal(gptp->bt, (uint16_t)gptp->counter); + // restart the timer + Bt_Rt_EnableSwTrig(gptp->bt); + } + return; + } else { + gptp->counter = 0; + } +#endif /* USE_16BIT_TIMER */ + + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +#if CYPRESS_GPT_USE_BT0_BT1 +static void gpt_lld_serve_interrupt0(void) { + gpt_lld_serve_interrupt(&GPTD1); +} +#endif /* CYPRESS_GPT_USE_BT0 */ + +#if CYPRESS_GPT_USE_BT2_BT3 +static void gpt_lld_serve_interrupt1(void) { + gpt_lld_serve_interrupt(&GPTD2); +} +#endif /* CYPRESS_GPT_USE_BT1 */ + +#if CYPRESS_GPT_USE_BT4_BT5 +static void gpt_lld_serve_interrupt2(void) { + gpt_lld_serve_interrupt(&GPTD3); +} +#endif /* CYPRESS_GPT_USE_BT2 */ + +#if CYPRESS_GPT_USE_BT6_BT7 +static void gpt_lld_serve_interrupt3(void) { + gpt_lld_serve_interrupt(&GPTD4); +} +#endif /* CYPRESS_GPT_USE_BT3 */ + + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if CYPRESS_GPT_USE_BT0_BT1 + /* Driver initialization.*/ + gptObjectInit(&GPTD1); + GPTD1.bt = &BT0; + GPTD1.bt2 = &BT1; // needed for 32-bit mode + GPTD1.serve_interrupt = gpt_lld_serve_interrupt0; +#endif + +#if CYPRESS_GPT_USE_BT2_BT3 + /* Driver initialization.*/ + gptObjectInit(&GPTD2); + GPTD2.bt = &BT2; + GPTD1.bt2 = &BT3; // needed for 32-bit mode + GPTD2.serve_interrupt = gpt_lld_serve_interrupt1; +#endif + +#if CYPRESS_GPT_USE_BT4_BT5 + /* Driver initialization.*/ + gptObjectInit(&GPTD3); + GPTD3.bt = &BT4; + GPTD1.bt2 = &BT5; // needed for 32-bit mode + GPTD3.serve_interrupt = gpt_lld_serve_interrupt2; +#endif + +#if CYPRESS_GPT_USE_BT6_BT7 + /* Driver initialization.*/ + gptObjectInit(&GPTD4); + GPTD4.bt = &BT6; + GPTD1.bt2 = &BT7; // needed for 32-bit mode + GPTD4.serve_interrupt = gpt_lld_serve_interrupt3; +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + en_result_t res; + + // [andreika]: these two should match: + en_rt_clock_pres_t psc = RtPres1Div16; + uint32_t prescaler = 16; + + if (gptp->state != GPT_STOP) + return; + gptp->clock = CYPRESS_PCLK1_FREQENCY / prescaler; + + // Check if the prescaler is correct and frequency is supported + osalDbgAssert((uint32_t)(gptp->clock / gptp->config->frequency) * gptp->config->frequency == gptp->clock, "BT: invalid frequency or prescaler"); + + // Set BT IO mode + Bt_ConfigIOMode(gptp->bt, BtIoMode0); + + // Initialize BT + memset(&gptp->stcRtConfig, 0, sizeof(gptp->stcRtConfig)); + gptp->stcRtConfig.enPres = psc; +#ifdef USE_16BIT_TIMER + gptp->stcRtConfig.enSize = RtSize16Bit; +#else + gptp->stcRtConfig.enSize = RtSize32Bit; // we use dual 16-bit timers (odd+even) for 32-bit mode +#endif + + // We don't know what kind of timer would be needed. + // So we always use a continuous 'Reload' mode, and emulate 'RtOneshot' mode by stopping it manually inside the IRQ handler + gptp->stcRtConfig.enMode = RtReload; + + gptp->stcRtConfig.enOutputPolarity = RtPolarityLow; + gptp->stcRtConfig.enExtTrig = RtExtTiggerDisable; + gptp->stcRtConfig.bTouchNvic = TRUE; + + // BT timer is a count-down timer so we use "Underflow" interrupts (when the counter reaches 0) + memset(&gptp->stcRtIrqEn, 0, sizeof(gptp->stcRtIrqEn)); + gptp->stcRtIrqEn.bRtUnderflowIrq = TRUE; + memset(&gptp->stcRtIrqCb, 0, sizeof(gptp->stcRtIrqCb)); + gptp->stcRtIrqCb.pfnRtUnderflowIrqCb = gptp->serve_interrupt; + + gptp->stcRtConfig.pstcRtIrqEn = &gptp->stcRtIrqEn; + gptp->stcRtConfig.pstcRtIrqCb = &gptp->stcRtIrqCb; + + res = Bt_Rt_Init(gptp->bt, &gptp->stcRtConfig); + osalDbgAssert(res == Ok, "Bt_Rt_Init failed"); +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + Bt_Rt_DeInit(gptp->bt, TRUE); + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + gpt_lld_change_interval(gptp, interval); + Bt_Rt_EnableCount(gptp->bt); + Bt_Rt_EnableSwTrig(gptp->bt); +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + Bt_Rt_DisableCount(gptp->bt); + gptp->counter = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + // todo: is it correct? not tested! + gpt_lld_start_timer(gptp, interval); + // wait + while (Bt_Rt_GetIrqFlag(gptp->bt, RtUnderflowIrq) != PdlSet) { + Bt_Rt_ClrIrqFlag(gptp->bt, RtUnderflowIrq); + break; + } + gpt_lld_stop_timer(gptp); +} + +void gpt_lld_change_interval(GPTDriver *gptp, gptcnt_t interval) { + if (interval == 0) + return; + // we multiply the interval because the timer clock is N times faster than the user-set frequency + int64_t val = (int32_t)((gptp->clock / gptp->config->frequency) * interval - 1); +#ifdef USE_16BIT_TIMER + gptp->counter = val; + if (val > BT_16BIT_MAX_COUNT_VALUE) { + val = BT_16BIT_MAX_COUNT_VALUE; + } +#else + // first, set HIWORD(val) to the odd channel + // todo: it seems it doesn't work? :( + Bt_Rt_WriteCycleVal(gptp->bt2, (uint16_t)(val >> 16)); +#endif + // then, set LOWORD(val) to the even channel + Bt_Rt_WriteCycleVal(gptp->bt, (uint16_t)(val & 0xffff)); +} + +gptcnt_t gpt_lld_get_interval(GPTDriver *gptp) { + // todo: test if it works + uint32_t loword = Bt_Rt_ReadCurCnt(gptp->bt); + uint32_t hiword = Bt_Rt_ReadCurCnt(gptp->bt2); + uint64_t val = (hiword << 16) | loword; + return (uint32_t)((val * gptp->config->frequency) / ((uint32_t)gptp->clock) + 1); +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.h new file mode 100644 index 0000000000..5327f2be7a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_gpt_lld.h @@ -0,0 +1,250 @@ +/* + ChibiOS - Copyright (C) 2014 Derek Mulcahy + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file PITv1/hal_gpt_lld.h + * @brief Cypress GPT subsystem low level driver header. + * @author andreika + * + * @addtogroup GPT + * @{ + */ + +#ifndef HAL_GPT_LLD_H_ +#define HAL_GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +#include "pdl_header.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p TRUE. + */ +#if !defined(CYPRESS_GPT_USE_BT0_BT1) || defined(__DOXYGEN__) +#define CYPRESS_GPT_USE_BT0_BT1 FALSE +#endif + +/** + * @brief GPTD2 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p TRUE. + */ +#if !defined(CYPRESS_GPT_USE_BT2_BT3) || defined(__DOXYGEN__) +#define CYPRESS_GPT_USE_BT2_BT3 FALSE +#endif + +/** + * @brief GPTD3 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p TRUE. + */ +#if !defined(CYPRESS_GPT_USE_BT4_BT5) || defined(__DOXYGEN__) +#define CYPRESS_GPT_USE_BT4_BT5 FALSE +#endif + +/** + * @brief GPTD4 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p TRUE. + */ +#if !defined(CYPRESS_GPT_USE_BT6_BT7) || defined(__DOXYGEN__) +#define CYPRESS_GPT_USE_BT6_BT7 FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !CYPRESS_GPT_USE_BT0_BT1 && !CYPRESS_GPT_USE_BT2_BT3 && \ + !CYPRESS_GPT_USE_BT4_BT5 && !CYPRESS_GPT_USE_BT6_BT7 +#error "GPT driver activated but no BT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + * @note This callback can be set to @p NULL but in that case the + * one-shot mode cannot be used. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ + /* [andreika]: STM32-compatible fields */ + /** + * @brief TIM CR2 register initialization data. + * @note The value of this field should normally be equal to zero. + */ + uint32_t cr2; + /** + * @brief TIM DIER register initialization data. + * @note The value of this field should normally be equal to zero. + * @note Only the DMA-related bits can be specified in this field. + */ + uint32_t dier; +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Timer base clock. + */ + uint32_t clock; + + // PDL internals + volatile stc_btn_t *bt; + volatile stc_btn_t *bt2; + stc_bt_rt_config_t stcRtConfig; + stc_rt_irq_en_t stcRtIrqEn; + stc_rt_irq_cb_t stcRtIrqCb; + + + func_ptr_t serve_interrupt; + + /** + * @brief Used for 16-bit Timer mode. + */ + volatile int32_t counter; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the counter value of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * @note The nature of the counter is not defined, it may count upward + * or downward, it could be continuously running or not. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current counter value. + * + * @notapi + */ +#define gpt_lld_get_counter(gptp) 0 // TODO: ? // ((gptcnt_t)PIT->CHANNEL[(gptp)->channelIndex].CVAL) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if CYPRESS_GPT_USE_BT0_BT1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if CYPRESS_GPT_USE_BT2_BT3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if CYPRESS_GPT_USE_BT4_BT5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if CYPRESS_GPT_USE_BT6_BT7 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); + + /** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must be running in continuous mode. + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + */ + void gpt_lld_change_interval(GPTDriver *gptp, gptcnt_t interval); + + /** + * @brief Returns the interval of GPT peripheral. + * @pre The GPT unit must be running in continuous mode. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @return The current interval. + */ + gptcnt_t gpt_lld_get_interval(GPTDriver *gptp); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* HAL_GPT_LLD_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.c new file mode 100644 index 0000000000..9d953a3618 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.c @@ -0,0 +1,99 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file PITv1/hal_st_lld.c + * @brief ST Driver subsystem low level driver code. + * @author andreika + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(SysTick_Handler) { + + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) { +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (CYPRESS_SYSCLK_FREQUENCY / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, CYPRESS_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.h new file mode 100644 index 0000000000..92518565c2 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.h @@ -0,0 +1,157 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file PITv1/hal_st_lld.h + * @brief ST Driver subsystem low level driver header. + * @author andreika + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H_ +#define HAL_ST_LLD_H_ + +#include "mcuconf.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(CYPRESS_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define CYPRESS_ST_IRQ_PRIORITY 8 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) { + + return (systime_t)0; +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] time the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t time) { + + (void)time; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) { + +} + +/** + * @brief Sets the alarm time. + * + * @param[in] time the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t time) { + + (void)time; +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) { + + return (systime_t)0; +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) { + + return false; +} + +#endif /* HAL_ST_LLD_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/driver.mk b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/driver.mk new file mode 100644 index 0000000000..b22d94b929 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/driver.mk @@ -0,0 +1,6 @@ +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +PLATFORMSRC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c +PLATFORMINC_CONTRIB += ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/SPIv2 diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c new file mode 100644 index 0000000000..8f228bff41 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.c @@ -0,0 +1,467 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPIv1/hal_spi_lld.c + * @brief Cypress SPI subsystem low level driver source. + * @author andreika + * + * @addtogroup SPI + * @{ + */ + +#include +#include "hal.h" + +//_spi_isr_code + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** @brief SPI0 driver identifier.*/ +#if CYPRESS_SPI_USE_SPI0 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** @brief SPI1 driver identifier.*/ +#if CYPRESS_SPI_USE_SPI1 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +static en_cs_pin_sel_t spi_detectPCS(bool isMaster, ioportid_t ssport, uint16_t sspad, int *alt) { + *alt = PAL_MODE_ALTERNATIVE_SPI; + // todo: check if PCS corresponds to SPI number + if (ssport == GPIOG && sspad == 11) // P7B + return CsPinScs0; + if (ssport == GPIOH && sspad == 11) // PAB + return CsPinScs0; + if (ssport == GPIOH && sspad == 12) // PAC + return CsPinScs1; + // wrong/unrecognized PCS! + *alt = 0; + return -1; +} + +static int32_t spi_detectBaudRate(SPIDriver *spip) { + static const int baudRates[] = { 21000000, 10500000, 5250000, 2626000, 1312500, 656250, 328125, 164060 }; + int flags = 0; + if (spip->config->cr1 & SPI_CR1_BR_0) + flags |= 1; + if (spip->config->cr1 & SPI_CR1_BR_1) + flags |= 2; + if (spip->config->cr1 & SPI_CR1_BR_2) + flags |= 4; + int br = baudRates[flags]; + // SPI1 is faster on STM32 (42 MHz max) so we imitate this behavior + if (spip == &SPID1) + br *= 2; + return br; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +static void spi_lld_master_tx_callback(SPIDriver *spip) { +//!!!!!!!!!!!!! +#if 0 + if (spip->csioSendCnt >= spip->csioTxBufSize) { + /* Disable interrupt */ + Mfs_Csio_DisableIrq(spip->spi, CsioTxIrq); + return; + } + + if (spip->csioTxBuf != NULL) { + Mfs_Csio_SendData(spip->spi, spip->csioTxBuf[spip->csioSendCnt++], TRUE); + } +#endif +} + +static void spi_lld_master_rx_callback(SPIDriver *spip) { +//!!!!!!!!!!!!! +#if 0 + if (spip->csioRxBuf != NULL) { + spip->csioRxBuf[spip->csioReceiveCnt++] = Mfs_Csio_ReceiveData(spip->spi); + } + + if (spip->csioReceiveCnt >= spip->csioRxBufSize) { + /* Disable interrupt */ + Mfs_Csio_DisableIrq(spip->spi, CsioRxIrq); + return; + } +#endif +} + +/*===========================================================================*/ + +#if CYPRESS_SPI_USE_SPI0 +static void spi_lld_master_tx1_callback(void) { + spi_lld_master_tx_callback(&SPID1); +} + +static void spi_lld_master_rx1_callback(void) { + spi_lld_master_rx_callback(&SPID1); +} +#endif /* CYPRESS_SPI_USE_SPI0 */ + +#if CYPRESS_SPI_USE_SPI1 +static void spi_lld_master_tx2_callback(void) { + spi_lld_master_tx_callback(&SPID2); +} + +static void spi_lld_master_rx2_callback(void) { + spi_lld_master_rx_callback(&SPID2); +} +#endif /* CYPRESS_SPI_USE_SPI1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { +#if CYPRESS_SPI_USE_SPI0 + spiObjectInit(&SPID1); + SPID1.spi = &(CYPRESS_SPI_SPI0_CHANNEL); + memset(&SPID1.stcCsioIrqCb, 0, sizeof(SPID1.stcCsioIrqCb)); + SPID1.stcCsioIrqCb.pfnTxIrqCb = spi_lld_master_tx1_callback; + SPID1.stcCsioIrqCb.pfnRxIrqCb = spi_lld_master_rx1_callback; +#endif +#if CYPRESS_SPI_USE_SPI1 + spiObjectInit(&SPID2); + SPID2.spi = &(CYPRESS_SPI_SPI1_CHANNEL); + memset(&SPID2.stcCsioIrqCb, 0, sizeof(SPID2.stcCsioIrqCb)); + SPID2.stcCsioIrqCb.pfnTxIrqCb = spi_lld_master_tx2_callback; + SPID2.stcCsioIrqCb.pfnRxIrqCb = spi_lld_master_rx2_callback; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + /* If in stopped state then enables the SPI and DMA clocks.*/ + if (spip->state == SPI_STOP) { + + spip->isMaster = (spip->config->cr1 & SPI_CR1_MSTR) != 0; + spip->flags = 0; // kLPSPI_MasterByteSwap; + if (spip->config->circular) + spip->flags |= SPI_CIRCULAR_FLAG; + int pcsAlt = 0; + //!!!!!!!!!!!!!!!!!!!!!!!!!! + spip->stcCsioCsPin = -1; //spi_detectPCS(spip->isMaster, spip->config->ssport, spip->config->sspad, &pcsAlt); + + if (spip->stcCsioCsPin != (en_cs_pin_sel_t)-1) { + // enable corresponding alt.mode for hardware PCS control + palSetPadMode(spip->config->ssport, spip->config->sspad, PAL_MODE_ALTERNATE(pcsAlt)); + + memset(&spip->stcCsioCsConfig, 0, sizeof(spip->stcCsioCsConfig)); + + spip->stcCsioCsConfig.enCsStartPin = spip->stcCsioCsPin; + spip->stcCsioCsConfig.enCsEndPin = spip->stcCsioCsPin; + spip->stcCsioCsConfig.enClkDiv = CsClkNoDiv; + spip->stcCsioCsConfig.bActiveHold = FALSE; + spip->stcCsioCsConfig.enLevel = CsLowActive; + // todo: make it baudRate-dependent? + spip->stcCsioCsConfig.u8CsSetupDelayTime = 200u; + spip->stcCsioCsConfig.u8CsHoldDelayTime = 200u; + spip->stcCsioCsConfig.u16CsDeselectTime = 2000u; + + switch (spip->stcCsioCsPin) { + case CsPinScs0: + spip->stcCsioCsConfig.bScs0En = TRUE; + break; + case CsPinScs1: + spip->stcCsioCsConfig.bScs1En = TRUE; + break; + case CsPinScs2: + spip->stcCsioCsConfig.bScs2En = TRUE; + break; + case CsPinScs3: + spip->stcCsioCsConfig.bScs3En = TRUE; + break; + } + } else if (spip->config->ssport != NULL) { + spip->flags |= SPI_SOFTWARE_CS_FLAG; + // software PCS control for non-standard pins + palSetPadMode(spip->config->ssport, spip->config->sspad, /*PAL_MODE_OUTPUT_PUSHPULL*/PAL_MODE_OUTPUT_OPENDRAIN); + } + memset(&spip->stcMfsCsioCfg, 0, sizeof(spip->stcMfsCsioCfg)); + spip->stcMfsCsioCfg.enMsMode = (spip->isMaster) ? CsioMaster : CsioSlave; + spip->stcMfsCsioCfg.enActMode = (spip->config->cr1 & SPI_CR1_CPHA) ? CsioActNormalMode : CsioActSpiMode; + spip->stcMfsCsioCfg.bInvertClk = (spip->config->cr1 & SPI_CR1_CPOL) ? FALSE : TRUE; + spip->stcMfsCsioCfg.u32BaudRate = spi_detectBaudRate(spip); + spip->stcMfsCsioCfg.enDataLength = (spip->config->cr1 & SPI_CR1_DFF) ? CsioSixteenBits : CsioEightBits; + spip->stcMfsCsioCfg.enBitDirection = (spip->config->cr1 & SPI_CR1_LSBFIRST) ? CsioDataLsbFirst : CsioDataMsbFirst; + spip->stcMfsCsioCfg.enSyncWaitTime = CsioSyncWaitZero; + spip->stcMfsCsioCfg.pstcFifoConfig = NULL; + spip->stcMfsCsioCfg.pstcCsConfig = (spip->stcCsioCsPin != (en_cs_pin_sel_t)-1) ? &spip->stcCsioCsConfig : NULL; + spip->stcMfsCsioCfg.pstcSerialTimer = NULL; + spip->stcMfsCsioCfg.pstcIrqEn = NULL; + spip->stcMfsCsioCfg.pstcIrqCb = &spip->stcCsioIrqCb; + spip->stcMfsCsioCfg.bTouchNvic = TRUE; + + en_result_t res = Mfs_Csio_Init(spip->spi, &spip->stcMfsCsioCfg); + + //debugLog("***spi_detectPCS() = %d baud=%d res=%d\r\n", pcsIdx, spip->stcMfsCsioCfg.u32BaudRate, res); //!!!!!!!!!!!!!!!!!! + + + osalDbgAssert(res == Ok, "SPI driver init failed"); + } +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + /* If in ready state then disables the SPI clock.*/ + if (spip->state == SPI_READY) { +#if CYPRESS_SPI_USE_SPI0 + if (&SPID1 == spip) { + Mfs_Csio_DeInit(spip->spi, TRUE); + } +#endif + +#if CYPRESS_SPI_USE_SPI1 + if (&SPID2 == spip) { + Mfs_Csio_DeInit(spip->spi, TRUE); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + // software PCS control for non-standard pins + if (spip->flags & SPI_SOFTWARE_CS_FLAG) { + palClearPad(spip->config->ssport, spip->config->sspad); + } +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + // software PCS control for non-standard pins + if (spip->flags & SPI_SOFTWARE_CS_FLAG) { + palSetPad(spip->config->ssport, spip->config->sspad); + } +} + +/** + * @brief Ignores data on the SPI bus. + * @details This asynchronous function starts the transmission of a series of + * idle words on the SPI bus and ignores the received data. + * @post At the end of the operation the configured callback is invoked. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + // todo: implement +/* + spip->count = n; + spip->rxbuf = NULL; + spip->txbuf = NULL; + + spi_start_xfer(spip, false); +*/ +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + spip->csioTxBuf = (uint8_t *)txbuf; + spip->csioTxBufSize = (txbuf != NULL) ? n : 0; + spip->csioSendCnt = 0; + + spip->csioRxBuf = (uint8_t *)rxbuf; + spip->csioRxBufSize = (rxbuf != NULL) ? n : 0; + spip->csioReceiveCnt = 0; + + if (txbuf != NULL) { + /* Enable TX function of CSIO */ + Mfs_Csio_EnableFunc(spip->spi, CsioTx); + + Mfs_Csio_SetCsTransferByteCount(spip->spi, spip->stcCsioCsPin, n); + + /* Configure interrupt */ + Mfs_Csio_EnableIrq(spip->spi, CsioTxIrq); + } + + if (rxbuf != NULL) { + /* Enable RX function of CSIO */ + Mfs_Csio_EnableFunc(spip->spi, CsioRx); + /* Configure interrupt */ + Mfs_Csio_EnableIrq(spip->spi, CsioRxIrq); + } +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + spi_lld_exchange(spip, n, txbuf, NULL); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + spi_lld_exchange(spip, n, NULL, rxbuf); +} + +#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__) +/** + * @brief Aborts the ongoing SPI operation, if any. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_abort(SPIDriver *spip) { + // todo: implement +#if 0 + //SPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable); + /* Stopping DMAs.*/ + dmaStreamDisable(spip->dmatx); + dmaStreamDisable(spip->dmarx); +#endif +} +#endif /* SPI_SUPPORTS_CIRCULAR == TRUE */ + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + int numBytes; + uint16_t rxFrame; + + Mfs_Csio_EnableFunc(spip->spi, CsioTx); + Mfs_Csio_EnableFunc(spip->spi, CsioRx); + /* wait until TX buffer empty */ + while (TRUE != Mfs_Csio_GetStatus(spip->spi, CsioTxEmpty)) + ; + + numBytes = (spip->stcMfsCsioCfg.enDataLength == CsioSixteenBits) ? 2 : 1; + Mfs_Csio_SetCsTransferByteCount(spip->spi, spip->stcCsioCsPin, numBytes); + + /* Master sends data */ + Mfs_Csio_SendData(spip->spi, frame, TRUE); + + /* Wait until master TX bus idle */ + while (TRUE != Mfs_Csio_GetStatus(spip->spi, CsioTxIdle)) + ; + + /* wait until RX buffer full */ + while(TRUE != Mfs_Csio_GetStatus(spip->spi, CsioRxFull)) + ; + + /* Master receives data */ + rxFrame = Mfs_Csio_ReceiveData(spip->spi); + + Mfs_Csio_DisableFunc(spip->spi, CsioTx); + Mfs_Csio_DisableFunc(spip->spi, CsioRx); + + return rxFrame; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.h new file mode 100644 index 0000000000..800e2aba33 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/LLD/SPIv2/hal_spi_lld.h @@ -0,0 +1,241 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file SPIv1/hal_spi_lld.h + * @brief CYPRESS SPI subsystem low level driver header. + * @author andreika + * + * @addtogroup SPI + * @{ + */ + +#ifndef HAL_SPI_LLD_H_ +#define HAL_SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +#include "pdl_header.h" +//#include "mfs/mfs.h" +//#include "mfs/mfs_hl.h" + +#define SPI_TX_BUFFSIZE (64) +#define SPI_RX_BUFFSIZE (64) +#define SPI_RX_BUFF_FILL_LVL (1) + + + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Circular mode support flag. + */ +#define SPI_SUPPORTS_CIRCULAR TRUE + +#define SPI_CIRCULAR_FLAG 0x010 +#define SPI_SOFTWARE_CS_FLAG 0x100 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief SPI0 driver enable switch. + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p FALSE. + */ +#if !defined(CYPRESS_SPI_USE_SPI0) || defined(__DOXYGEN__) +#define CYPRESS_SPI_USE_SPI0 FALSE +#endif + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for SPI0 is included. + * @note The default is @p FALSE. + */ +#if !defined(CYPRESS_SPI_USE_SPI1) || defined(__DOXYGEN__) +#define CYPRESS_SPI_USE_SPI1 FALSE +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !(CYPRESS_SPI_USE_SPI0 || CYPRESS_SPI_USE_SPI1) +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { +#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__) + /** + * @brief Enables the circular buffer mode. + */ + bool circular; +#endif + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port - when not using pcs. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number - when not using pcs. + */ + uint16_t sspad; + /** + * @brief SPI CR1 register initialization data. + */ + uint16_t cr1; + /** + * @brief SPI CR2 register initialization data. + */ + uint16_t cr2; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + + /** + * @brief Pointer to the SPIx registers block. + */ + volatile stc_mfsn_csio_t *spi; + + /** + * PDL internal structures. + */ + stc_mfs_csio_config_t stcMfsCsioCfg; + stc_csio_cs_t stcCsioCsConfig; + stc_csio_irq_cb_t stcCsioIrqCb; + en_cs_pin_sel_t stcCsioCsPin; + + /** + * @brief Master or Slave. + */ + bool isMaster; + + /** + * @brief Transfer flags (including kLPSPI_MasterPcs*) for this SPI config. + */ + int32_t flags; + + /** + * @brief Transfer buffers. + */ + uint8_t *csioTxBuf; + uint8_t *csioRxBuf; + uint32_t csioTxBufSize, csioRxBufSize; + uint32_t csioReceiveCnt, csioSendCnt; + + volatile uint16_t u16RxBufFillCnt; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if CYPRESS_SPI_USE_SPI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if CYPRESS_SPI_USE_SPI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); +#if (SPI_SUPPORTS_CIRCULAR == TRUE) || defined(__DOXYGEN__) + void spi_lld_abort(SPIDriver *spip); +#endif + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* HAL_SPI_LLD_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.c new file mode 100644 index 0000000000..3cf8746474 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.c @@ -0,0 +1,1607 @@ +/****************************************************************************** +* \file adc.c +* +* \version 1.20 +* +* \brief 12 bit ADC (ADC) driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "adc/adc.h" + +#if (defined(PDL_PERIPHERAL_ADC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled ADC instances and their internal data +stc_adc_instance_data_t m_astcAdcInstanceDataLut[ADC_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_ADC0 == PDL_ON) + { + &ADC0, // pstcInstance + { + 0u, 0u ,0u, 0u, 0u , + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + 0u + #endif + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_ADC1 == PDL_ON) + { + &ADC1, // pstcInstance + { + 0u, 0u , 0u, 0u, 0u, + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + 0u + #endif + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_ADC2 == PDL_ON) + { + &ADC2, // pstcInstance + { + 0u, 0u, 0u, 0u, 0u , + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + 0u + #endif + } + } +#endif +}; + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) +static void Adc_InitNvic(volatile stc_adcn_t* pstcAdc); +static void Adc_DeInitNvic(volatile stc_adcn_t* pstcAdc); +static stc_adc_intern_data_t* AdcGetInternDataPtr(volatile stc_adcn_t* pstcAdc); +#endif + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) +/** + ****************************************************************************** + ** \brief ADC instance interrupt service routine + ** + ** ADC instance interrupt service routine, clear interrupt cause and + ** implement interrupt callback function. + ** + ** \param pstcAdc Pointer to ADC instance + ** \param pstcAdcInternData Pointer to ADC intern data + ** + ******************************************************************************/ +void AdcIrqHandler( volatile stc_adcn_t* pstcAdc, + stc_adc_intern_data_t* pstcAdcInternData) +{ + if (1u == pstcAdc->SCCR_f.SOVR) // Error case (FIFO overflow) + { + pstcAdc->SCCR_f.SOVR = 0u; + + if (pstcAdcInternData->pfnScanErrIrqCb != NULL) + { + pstcAdcInternData->pfnScanErrIrqCb(); + } + } + + if (1u == pstcAdc->PCCR_f.POVR) // Error case (Priority FIFO overflow) + { + pstcAdc->PCCR_f.POVR = 0u; + + if (pstcAdcInternData->pfnPrioErrIrqCb != NULL) + { + pstcAdcInternData->pfnPrioErrIrqCb(); + } + } + + if (1u == pstcAdc->ADCR_f.PCIF) // Priority Conversion + { + pstcAdc->ADCR_f.PCIF = 0u; + + if (pstcAdcInternData->pfnPrioIrqCb != NULL) + { + // Callback argument points to priority FIFO. User has to empty it in + // the callback function, because the FIFO depth is known. + pstcAdcInternData->pfnPrioIrqCb((volatile uint32_t*)&pstcAdc->PCFD); + } + } + + if (1u == pstcAdc->ADCR_f.SCIF) // Scan conversion interrupt request? + { + pstcAdc->ADCR_f.SCIF = 0u; + + if (pstcAdcInternData->pfnScanIrqCb != NULL) + { + // Callback argument points to scan FIFO. User has to empty it in + // the callback function, because the FIFO depth is known. + pstcAdcInternData->pfnScanIrqCb((volatile uint32_t*)&pstcAdc->SCFD); + } + } + + if (1u == pstcAdc->ADCR_f.CMPIF) // Compare result interrupt request? + { + pstcAdc->ADCR_f.CMPIF = 0u; + + if (pstcAdcInternData->pfnComparisonIrqCb != NULL) + { + pstcAdcInternData->pfnComparisonIrqCb(); + } + } +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if (1u == pstcAdc->WCMRCIF_f.RCINT) // Range result interrupt request? + { + pstcAdc->WCMRCIF_f.RCINT = 0u; + + if (pstcAdcInternData->pfnRangeComparisonIrqCb != NULL) + { + pstcAdcInternData->pfnRangeComparisonIrqCb(); + } + } +#endif + return; +} // AdcIrqHandler + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on ADC instance + ** + ** \param pstcAdc Pointer to ADC instance + ** + ******************************************************************************/ +static void Adc_InitNvic(volatile stc_adcn_t* pstcAdc) +{ +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) + if (pstcAdc == (volatile stc_adcn_t*)(&ADC0)) + { + NVIC_ClearPendingIRQ(ADC0_IRQn); + NVIC_EnableIRQ(ADC0_IRQn); + NVIC_SetPriority(ADC0_IRQn, PDL_IRQ_LEVEL_ADC0); + } +#endif +#if (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) + if (pstcAdc == (volatile stc_adcn_t*)(&ADC1)) + { + NVIC_ClearPendingIRQ(ADC1_IRQn); + NVIC_EnableIRQ(ADC1_IRQn); + NVIC_SetPriority(ADC1_IRQn, PDL_IRQ_LEVEL_ADC1); + } +#endif +#if (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) + if (pstcAdc == (volatile stc_adcn_t*)(&ADC2)) + { + NVIC_ClearPendingIRQ(ADC2_IRQn); + NVIC_EnableIRQ(ADC2_IRQn); + NVIC_SetPriority(ADC2_IRQn, PDL_IRQ_LEVEL_ADC2); + } +#endif +} // Adc_InitInterrupt + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on ADC instance + ** + ** \param pstcAdc Pointer to ADC instance + ** + ******************************************************************************/ +static void Adc_DeInitNvic(volatile stc_adcn_t* pstcAdc) +{ + /* Only when all of ADC interrupt sources are disable, disable ADC IRQ */ +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) + if (pstcAdc == (volatile stc_adcn_t*)(&ADC0)) + { + NVIC_ClearPendingIRQ(ADC0_IRQn); + NVIC_DisableIRQ(ADC0_IRQn); + NVIC_SetPriority(ADC0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) + if (pstcAdc == (volatile stc_adcn_t*)(&ADC1)) + { + NVIC_ClearPendingIRQ(ADC1_IRQn); + NVIC_DisableIRQ(ADC1_IRQn); + NVIC_SetPriority(ADC1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) + if (pstcAdc == (volatile stc_adcn_t*)(&ADC2)) + { + NVIC_ClearPendingIRQ(ADC2_IRQn); + NVIC_DisableIRQ(ADC2_IRQn); + NVIC_SetPriority(ADC2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +} // Adc_DeInitInterrupt +#endif // #if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_ADC2_LCD == PDL_ON) + + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain ADC instance. + ** + ** \param pstcAdc Pointer to ADC instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_adc_intern_data_t* AdcGetInternDataPtr(volatile stc_adcn_t* pstcAdc) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < ADC_INSTANCE_COUNT; u8Instance++) + { + if (pstcAdc == m_astcAdcInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcAdcInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} + + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Initialize ADC + ** + ** This function initializes an ADC module + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] pstcConfig ADC module configuration + ** + ** \retval Ok ADC initialized normally + ** \retval ErrorInvalidParameter if one of following case matches: + ** - pstcAdc == NULL + ** - pstcConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Adc_Init( volatile stc_adcn_t* pstcAdc, + const stc_adc_config_t* pstcConfig ) +{ + //stc_adc0_pcis_field_t stcPCIS; + uint8_t u8PCIS = 0u; + uint8_t u8CMPCR = 0u; + + // Pointer to internal data + stc_adc_intern_data_t* pstcAdcInternData ; + + // Registers bit field structure + stc_adc_sccr_field_t stcSCCR; + stc_adc_pccr_field_t stcPCCR; + stc_adc_adst01_field_t stcADST01; + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + stc_adc_wcmpcr_field_t stcWCMPCR; +#endif + + // Check for NULL pointer + if ((NULL == pstcAdc ) || + (NULL == pstcConfig )) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcAdcInternData = AdcGetInternDataPtr( pstcAdc ) ; + + // Check for instance available or not + if(pstcAdcInternData == NULL) + { + return ErrorInvalidParameter ; + } + + PDL_ZERO_STRUCT(stcSCCR); + PDL_ZERO_STRUCT(stcPCCR); + PDL_ZERO_STRUCT(stcADST01); + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + PDL_ZERO_STRUCT(stcWCMPCR); +#endif + + // Disable ADC in any case first + pstcAdc->ADCEN_f.ENBL = 0u; + + // Clear all relevant registers + pstcAdc->ADCR = 0u; + pstcAdc->ADSR = 0u; + pstcAdc->SCCR = 0u; + + // Set Sampling Time Selection Register + pstcAdc->ADSS01 = (uint16_t)(0x0000FFFFul & pstcConfig->u32SamplingTimeSelect.u32AD_CHn); + + pstcAdc->ADSS23 = (uint16_t)((0xFFFF0000ul & pstcConfig->u32SamplingTimeSelect.u32AD_CHn) >> 16u); + + + // Set Sampling Times Config. 0 + switch (pstcConfig->enSamplingTimeN0) + { + case Value1: + stcADST01.STX0 = 0u; + break; + case Value4: + stcADST01.STX0 = 1u; + break; + case Value8: + stcADST01.STX0 = 2u; + break; + case Value16: + stcADST01.STX0 = 3u; + break; + case Value32: + stcADST01.STX0 = 4u; + break; + case Value64: + stcADST01.STX0 = 5u; + break; + case Value128: + stcADST01.STX0 = 6u; + break; + case Value256: + stcADST01.STX0 = 7u; + break; + default: + return ErrorInvalidParameter; + } + + if (pstcConfig->u8SamplingTime0 > 31u) + { + return ErrorInvalidParameter; + } + + stcADST01.ST0 = pstcConfig->u8SamplingTime0; + + + + // Set Sampling Times Config. 1 + switch (pstcConfig->enSamplingTimeN1) + { + case Value1: + stcADST01.STX1 = 0u; + break; + case Value4: + stcADST01.STX1 = 1u; + break; + case Value8: + stcADST01.STX1 = 2u; + break; + case Value16: + stcADST01.STX1 = 3u; + break; + case Value32: + stcADST01.STX1 = 4u; + break; + case Value64: + stcADST01.STX1 = 5u; + break; + case Value128: + stcADST01.STX1 = 6u; + break; + case Value256: + stcADST01.STX1 = 7u; + break; + default: + return ErrorInvalidParameter; + } + + if (pstcConfig->u8SamplingTime1 > 31u) + { + return ErrorInvalidParameter; + } + + stcADST01.ST1 = pstcConfig->u8SamplingTime1; + + pstcAdc->ADST01_f = stcADST01; + + // Frequency Division for ADC Instance + pstcAdc->ADCT = pstcConfig->u8ComparingClockDiv; + + // MSB, LSB alignment + pstcAdc->ADSR_f.FDAS = (TRUE == pstcConfig->bLsbAlignment) ? 1u : 0u; + +#if (PDL_ADC_TYPE == PDL_ADC_A) + #if((PDL_MCU_TYPE != PDL_FM3_TYPE0)) + switch (pstcConfig->enEnableCycle) + { + case AdcEnableCycle36: + pstcAdc->ADCEN_f.CYCLSL = 0u; + break; + case AdcEnableCycle20: + pstcAdc->ADCEN_f.CYCLSL = 1u; + break; + case AdcEnableCycle9: + pstcAdc->ADCEN_f.CYCLSL = 2u; + break; + case AdcEnableCycle44: + pstcAdc->ADCEN_f.CYCLSL = 3u; + break; + default: + return ErrorInvalidParameter; + } + #endif +#elif (PDL_ADC_TYPE == PDL_ADC_B) + // Set enable time + pstcAdc->ADCEN &= 0x00FFu; + pstcAdc->ADCEN |= (uint16_t)((uint16_t)pstcConfig->u8EnableTime << 8u); +#endif + // Initialize scan fucntion + if(NULL != pstcConfig->pstcScanInit) + { + // Set Scan Conversion Input Selection Register + // [andreika]: fix! uint8_t->uint16_t + pstcAdc->SCIS01 = (uint16_t)(0x0000FFFFul & pstcConfig->pstcScanInit->u32ScanCannelSelect.u32AD_CHn); + + pstcAdc->SCIS23 = (uint16_t)((0xFFFF0000ul & pstcConfig->pstcScanInit->u32ScanCannelSelect.u32AD_CHn) >> 16u); + + + // Conversion mode single, repeated + switch (pstcConfig->pstcScanInit->enScanMode) + { + case ScanSingleConversion: + stcSCCR.RPT = 0u; + break; + case ScanRepeatConversion: + stcSCCR.RPT = 1u; + break; + default: + return ErrorInvalidParameter; + } + + #if defined(FM_ADC0_SCTSL_AVAILABLE) + // Scan Conversion Timer Start Enable and Timer Source + if (TRUE == pstcConfig->pstcScanInit->bScanTimerStartEnable) + { + stcSCCR.SHEN = 1u; + pstcAdc->SCTSL = (uint8_t) pstcConfig->pstcScanInit->enScanTimerTrigger; + } + #endif + + // Update hardware + pstcAdc->SCCR_f = stcSCCR; + + // Scan Conversion FIFO Depth + if (pstcConfig->pstcScanInit->u8ScanFifoDepth > 15u) + { + return ErrorInvalidParameter; + } + + pstcAdc->SFNS = pstcConfig->pstcScanInit->u8ScanFifoDepth; + + } + + // Initialize priority fucntion + if(NULL != pstcConfig->pstcPrioInit) + { + // Priority external Trigger Analog Input + stcPCCR.ESCE = 0u; + + // Priority external Trigger Start Enable + stcPCCR.PEEN = (TRUE == pstcConfig->pstcPrioInit->bPrioExtTrigStartEnable) ? 1u : 0u; + + #if defined(FM_ADC0_PRTSL_AVAILABLE) + // Priority Conversion Timer Start Enable and Timer Source + if (TRUE == pstcConfig->pstcPrioInit->bPrioTimerStartEnable) + { + stcPCCR.PHEN = 1u; + pstcAdc->PRTSL = (uint8_t) pstcConfig->pstcPrioInit->enPrioTimerTrigger; + } + #endif + + // Update Hardware + pstcAdc->PCCR_f = stcPCCR; + + // Priority Conversion FIFO Stage Count Setup + pstcAdc->PFNS = pstcConfig->pstcPrioInit->u8PrioFifoDepth; + + // Priority Conversion Input Selection + if (pstcConfig->pstcPrioInit->u8PrioLevel1AnalogChSel > 7u) + { + return ErrorInvalidParameter; + } + u8PCIS = pstcConfig->pstcPrioInit->u8PrioLevel1AnalogChSel & 0x07u; + + if (pstcConfig->pstcPrioInit->u8PrioLevel2AnalogChSel > 31u) + { + return ErrorInvalidParameter; + } + u8PCIS |= (uint8_t)((uint8_t)(0x1Fu & pstcConfig->pstcPrioInit->u8PrioLevel2AnalogChSel) << 3u); + + pstcAdc->PCIS = u8PCIS; + } + + // Initialize comparison fucntion + if(NULL != pstcConfig->pstcComparisonInit) + { + // Comparison Value + pstcAdc->CMPD = (((pstcConfig->pstcComparisonInit->u16CompareValue >> 2u)) << 6u); + + if (pstcConfig->pstcComparisonInit->u8CompareChannel > 31u) + { + return ErrorInvalidParameter; + } + + // Comparison Control + if(pstcConfig->pstcComparisonInit->bCompIrqEqualGreater == TRUE) + { + u8CMPCR |= 0x40u; + } + + if(TRUE == pstcConfig->pstcComparisonInit->bCompareAllChannels) + { + u8CMPCR |= 0x20u; + } + + u8CMPCR |= 0x80u; // Enable comparison function + u8CMPCR |= (0x1Fu & pstcConfig->pstcComparisonInit->u8CompareChannel); + + pstcAdc->CMPCR = u8CMPCR; + } + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if (NULL != pstcConfig->pstcRangeComparisonInit) + { + // Set lower and upper value of the range + pstcAdc->WCMPDH = ((pstcConfig->pstcRangeComparisonInit->u16UpperLimitRangeValue >> 2u) << 6u); + pstcAdc->WCMPDL = ((pstcConfig->pstcRangeComparisonInit->u16LowerLimitRangeValue >> 2u) << 6u); + + if (pstcConfig->pstcRangeComparisonInit->u8RangeCountValue > 7u) + { + return ErrorInvalidParameter; + } + + // Set compare times + stcWCMPCR.RCOCD = pstcConfig->pstcRangeComparisonInit->u8RangeCountValue; + // In-range compare or out-range compare + stcWCMPCR.RCOIRS = pstcConfig->pstcRangeComparisonInit->bWithinRange; + // Enable range compare function + stcWCMPCR.RCOE = 1; + // Compare 1 channel or all + pstcAdc->WCMPSR_f.WCMD = pstcConfig->pstcRangeComparisonInit->bRangeCompareAllChannels; + + if (pstcConfig->pstcRangeComparisonInit->u8RangeCompareChannel > 31u) + { + return ErrorInvalidParameter; + } + + // Set the channel compared (according to single channel compare mode) + pstcAdc->WCMPSR_f.WCCH |= pstcConfig->pstcRangeComparisonInit->u8RangeCompareChannel; + + // update hardware + pstcAdc->WCMPCR_f = stcWCMPCR; + } +#endif + +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) + // Initialize interrupts + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bScanIrq) + { + pstcAdc->ADCR_f.SCIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bPrioIrq) + { + pstcAdc->ADCR_f.PCIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bComparisonIrq) + { + pstcAdc->ADCR_f.CMPIE = 1u; + } + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if(TRUE == pstcConfig->pstcIrqEn->bRangeComparisonIrq) + { + pstcAdc->WCMPCR_f.RCOIE = 1u; + } + #endif + if(TRUE == pstcConfig->pstcIrqEn->bFifoOverrunIrq) + { + pstcAdc->ADCR_f.OVRIE = 1u; + } + } + + // Initialize interrupt callback functions + if (NULL != pstcConfig->pstcIrqCb) + { + pstcAdcInternData->pfnScanIrqCb = pstcConfig->pstcIrqCb->pfnScanIrqCb; + pstcAdcInternData->pfnPrioIrqCb = pstcConfig->pstcIrqCb->pfnPrioIrqCb; + pstcAdcInternData->pfnScanErrIrqCb = pstcConfig->pstcIrqCb->pfnScanErrIrqCb; + pstcAdcInternData->pfnPrioErrIrqCb = pstcConfig->pstcIrqCb->pfnPrioErrIrqCb; + pstcAdcInternData->pfnComparisonIrqCb = pstcConfig->pstcIrqCb->pfnComparisonIrqCb; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcAdcInternData->pfnRangeComparisonIrqCb = pstcConfig->pstcIrqCb->pfnRangeComparisonIrqCb; + #endif + } + + // Initialize NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + Adc_InitNvic(pstcAdc); + } +#endif + + return Ok; +} // Adc_Init + +/** + ****************************************************************************** + ** \brief De-Initialize ADC + ** + ** This function deinitializes an ADC module + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok ADC instance fully disabled and reset + ** \retval ErrorInvalidParameter If one of following case matches: + ** - pstcAdc == NULL + ** - pstcAdcInternData == NULL + ** + ******************************************************************************/ +en_result_t Adc_DeInit( volatile stc_adcn_t* pstcAdc, boolean_t bTouchNvic ) +{ + // Pointer to internal data + stc_adc_intern_data_t* pstcAdcInternData ; + + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcAdcInternData = AdcGetInternDataPtr( pstcAdc ) ; + + // Check for instance available or not + if(NULL == pstcAdcInternData) + { + return ErrorInvalidParameter ; + } + + pstcAdc->ADCEN = 0u; // Diasble ADC (including ENBL bit) + pstcAdc->ADCR = 0u; + pstcAdc->ADSR = 0u; + pstcAdc->SCCR = 0u; + pstcAdc->SFNS = 0u; + pstcAdc->SCIS01 = 0u; + + pstcAdc->SCIS23 = 0u; + + pstcAdc->PCCR = 0u; + pstcAdc->PFNS = 0u; + pstcAdc->PCFD = 0u; + pstcAdc->PCIS = 0u; + pstcAdc->CMPD = 0u; + pstcAdc->CMPCR = 0u; + pstcAdc->ADSS01 = 0u; + + pstcAdc->ADSS23 = 0u; + + pstcAdc->ADST01 = 0u; + + pstcAdc->ADCEN = 0u; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcAdc->WCMPDH = 0u; + pstcAdc->WCMPCR = 0u; + pstcAdc->WCMPDL = 0u; + pstcAdc->WCMPSR = 0u; + pstcAdc->WCMRCOT = 0u; + pstcAdc->WCMRCIF = 0u; +#endif +#if defined(FM_ADC0_SCTSL_AVAILABLE) && defined(FM_ADC0_PRTSL_AVAILABLE) + pstcAdc->SCTSL = 0u; + pstcAdc->PRTSL = 0u; +#endif + +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) + pstcAdcInternData->pfnScanIrqCb = NULL; + pstcAdcInternData->pfnPrioIrqCb = NULL; + pstcAdcInternData->pfnScanErrIrqCb = NULL; + pstcAdcInternData->pfnPrioErrIrqCb = NULL; + pstcAdcInternData->pfnComparisonIrqCb = NULL; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcAdcInternData->pfnRangeComparisonIrqCb = NULL; +#endif + + if(TRUE == bTouchNvic) + { + Adc_DeInitNvic(pstcAdc); + } +#endif + + return Ok; +} // Adc_DeInit + +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable ADC interrupt + ** + ** This function enable the ADC interrupts which are selected. + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] pstcIrqSel ADC interrupt selection + ** + ** \retval Ok Enable interrupt normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcAdc == NULL + ** - pstcIrqSel == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Adc_EnableIrq( volatile stc_adcn_t* pstcAdc, + stc_adc_irq_sel_t* pstcIrqSel) +{ + // Check for NULL pointer + if ((NULL == pstcAdc) || (NULL == pstcIrqSel)) + { + return ErrorInvalidParameter ; + } + + if(TRUE == pstcIrqSel->bScanIrq) + { + pstcAdc->ADCR_f.SCIE = 1u; + } + + if(TRUE == pstcIrqSel->bPrioIrq) + { + pstcAdc->ADCR_f.PCIE = 1u; + } + + if(TRUE == pstcIrqSel->bComparisonIrq) + { + pstcAdc->ADCR_f.CMPIE = 1u; + } +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if(TRUE == pstcIrqSel->bRangeComparisonIrq) + { + pstcAdc->WCMPCR_f.RCOIE = 1u; + } +#endif + if(TRUE == pstcIrqSel->bFifoOverrunIrq) + { + pstcAdc->ADCR_f.OVRIE = 1u; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable ADC interrupt + ** + ** This function disable the ADC interrupts which are selected. + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] pstcIrqSel ADC interrupt selection + ** + ** \retval Ok Disable interrupt normally + ** \retval ErrorInvalidParameter If one of following cases matches: + ** - pstcAdc == NULL + ** - pstcIrqSel == NULL + ******************************************************************************/ +en_result_t Adc_DisableIrq( volatile stc_adcn_t* pstcAdc, + stc_adc_irq_sel_t* pstcIrqSel) +{ + // Check for NULL pointer + if ((NULL == pstcAdc) || (NULL == pstcIrqSel)) + { + return ErrorInvalidParameter ; + } + + if(TRUE == pstcIrqSel->bScanIrq) + { + pstcAdc->ADCR_f.SCIE = 0u; + } + + if(TRUE == pstcIrqSel->bPrioIrq) + { + pstcAdc->ADCR_f.PCIE = 0u; + } + + if(TRUE == pstcIrqSel->bComparisonIrq) + { + pstcAdc->ADCR_f.CMPIE = 0u; + } +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if(TRUE == pstcIrqSel->bRangeComparisonIrq) + { + pstcAdc->WCMPCR_f.RCOIE = 0u; + } +#endif + if(TRUE == pstcIrqSel->bFifoOverrunIrq) + { + pstcAdc->ADCR_f.OVRIE = 0u; + } + + return Ok; +} +#endif + +/** + ****************************************************************************** + ** \brief Get ADC interrupt flag + ** + ** This function gets the ADC interrupt flag which is selected. + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] enIrq ADC interrupt type + ** \arg AdcScanIrq Scan conversion interrupt flag + ** \arg AdcPrioIrq Priority scan conversion interrupt flag + ** \arg AdcScanFifoOverrunIrq Scan FIFO overrun interrupt flag + ** \arg AdcPrioFifoOverrunIrq Priority FIFO overrun interrupt flag + ** \arg AdcComparisonIrq Comparison interrupt flag + ** \arg AdcRangeComparisonIrq Range comparison interrupt flag + ** + ** \retval TRUE The data count in scan FIFO match scan FIFO stage [AdcScanInt] + ** The data count in priority FIFO match priority FIFO stage [AdcPrioInt] + ** Scan FIFO overruns [AdcScanFifoOverrunInt] + ** Priority FIFO overruns [AdcPrioFifoOverrunInt] + ** The comparison result match the condition set in the Adc_Init() [AdcComparisonInt] + ** The range comparison result match the condition set in the Adc_Init() [AdcRangeComparisonInt] + ** \retval FALSE The data count in scan FIFO don't match scan FIFO stage [AdcScanInt] + ** The data count in priority FIFO don't match priority FIFO stage [AdcPrioInt] + ** Scan FIFO don't overrun [AdcScanFifoOverrunInt] + ** Priority FIFO don't overrun [AdcPrioFifoOverrunInt] + ** The comparison result don't match the condition set in the Adc_Init() [AdcComparisonInt] + ** The range comparison result don't match the condition set in the Adc_Init() [AdcRangeComparisonInt] + ** + ******************************************************************************/ +boolean_t Adc_GetIrqFlag(volatile stc_adcn_t* pstcAdc, en_adc_irq_t enIrq) +{ + boolean_t bRet = FALSE; + switch(enIrq) + { + case AdcScanIrq: + bRet = (pstcAdc->ADCR_f.SCIF == 1u) ? TRUE : FALSE; + break; + case AdcPrioIrq: + bRet = (pstcAdc->ADCR_f.PCIF == 1u) ? TRUE : FALSE; + break; + case AdcScanFifoOverrunIrq: + bRet = (pstcAdc->SCCR_f.SOVR == 1u) ? TRUE : FALSE; + break; + case AdcPrioFifoOverrunIrq: + bRet = (pstcAdc->PCCR_f.POVR == 1u) ? TRUE : FALSE; + break; + case AdcComparisonIrq: + bRet = (pstcAdc->ADCR_f.CMPIF == 1u) ? TRUE : FALSE; + break; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case AdcRangeComparisonIrq: + bRet = (pstcAdc->WCMRCIF_f.RCINT == 1u) ? TRUE : FALSE; + break; +#endif + default: + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear ADC interrupt flag + ** + ** This function clears the ADC interrupt which is selected. + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] enIrq Interrupt type + ** \arg AdcScanIrq Scan conversion interrupt flag + ** \arg AdcPrioIrq Priority scan conversion interrupt flag + ** \arg AdcScanFifoOverrunIrq Scan FIFO overrun interrupt flag + ** \arg AdcPrioFifoOverrunIrq Priority FIFO overrun interrupt flag + ** \arg AdcComparisonIrq Comparison interrupt flag + ** \arg AdcRangeComparisonIrq Range comparison interrupt flag + ** + ** \retval Ok Disable interrupt normally + ** \retval ErrorInvalidParameter pstcAdc == NULL + ** Other invalid configuration + ******************************************************************************/ +en_result_t Adc_ClrIrqFlag(volatile stc_adcn_t* pstcAdc, en_adc_irq_t enIrq) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + switch(enIrq) + { + case AdcScanIrq: + pstcAdc->ADCR_f.SCIF = 0u; + break; + case AdcPrioIrq: + pstcAdc->ADCR_f.PCIF = 0u; + break; + case AdcScanFifoOverrunIrq: + pstcAdc->SCCR_f.SOVR = 0u; + break; + case AdcPrioFifoOverrunIrq: + pstcAdc->PCCR_f.POVR = 0u; + break; + case AdcComparisonIrq: + pstcAdc->ADCR_f.CMPIF = 0u; + break; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case AdcRangeComparisonIrq: + pstcAdc->WCMRCIF_f.RCINT = 0u; + break; +#endif + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable ADC + ** + ** This function enables an ADC instance (Does not wait for readiness) + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC enable bit set (does not indicate readiness!) + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_Enable( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + // Enable ADC + pstcAdc->ADCEN_f.ENBL = 1u; + + return Ok; +} // Adc_Enable + +/** + ****************************************************************************** + ** \brief Check ADC Readiness + ** + ** This function checks for ADC instance readiness + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC instance ready + ** \retval ErrorNotReady ADC instance not ready + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_Ready( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + if (FALSE == pstcAdc->ADCEN_f.READY) + { + return ErrorNotReady; + } + + return Ok; +} // Adc_Ready + +/** + ****************************************************************************** + ** \brief Enable ADC and wait for Readiness + ** + ** This function enables an ADC instance and waits for readiness + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC instance enabled and ready + ** \retval ErrorTimeout ADC instance not ready + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_EnableWaitReady( volatile stc_adcn_t* pstcAdc ) +{ + uint32_t u32TimeOutCounter = PDL_ADC_READY_WAIT_COUNT; + + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + // Enable ADC + pstcAdc->ADCEN_f.ENBL = 1u; + + // Polling for readiness + while (u32TimeOutCounter) + { + if (TRUE == pstcAdc->ADCEN_f.READY) + { + return Ok; + } + + u32TimeOutCounter--; + } + + return ErrorTimeout; +} // Adc_EnableWaitReady + +/** + ****************************************************************************** + ** \brief Disable ADC + ** + ** This function disables an ADC operation + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC instance disabled + ** \retval ErrorTimeout ADC instance not ready + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_Disable( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + // Disable ADC + pstcAdc->ADCEN_f.ENBL = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief ADC Scan Software Start Trigger + ** + ** This function starts an AD Scan Conversion by Software trigger + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC instance triggered (or re-triggered) + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_SwTriggerScan( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->SCCR_f.SSTR = 1u; // Trigger AD Conversion + + return Ok; +} // Adc_SwStart + +/** + ****************************************************************************** + ** \brief Stop Scan conversion with repeat mode + ** + ** This function stops an AD Scan Conversion with repeat mode + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC scan conversion stopped + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_StopScanRepeat( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->SCCR_f.RPT = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start Scan conversion with repeat mode + ** + ** This function starts an AD Scan Conversion with repeat mode + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC scan conversion started + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_StartScanRepeat( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->SCCR_f.RPT = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief ADC Priority Software Start Trigger + ** + ** This function starts an AD Priority Conversion by Software trigger + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC instance triggered (or re-triggered) + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_SwTriggerPrio( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->PCCR_f.PSTR = 1u; // Trigger AD Conversion + + return Ok; +} + +/** + ****************************************************************************** + ** \brief ADC Software Stop + ** + ** This function requests a stop of the ADC + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok ADC instance stop request + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_ForceStop( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->ADSR_f.ADSTP = 1u; + + return Ok; +} // Adc_SwStop + +/** + ****************************************************************************** + ** \brief Get ADC conversion status + ** + ** This function gets the status when ADC is in conversion + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] enStatus ADC status type + ** \arg ScanFifoEmptyStatus Scan FIFO empty status + ** \arg ScanFifoFullStatus Scan FIFO full status + ** \arg PrioFifoEmptyStatus Priority FIFO empty status + ** \arg PrioFifoFullStatus Priority FIFO full status + ** \arg Prio2PendingStatus Priority conversion (level 2) pending status + ** \arg PrioStatus Priority conversion status + ** \arg ScanStatus Scan conversion status + ** \arg RangeThresholdExcessFlag Range comparison threshold exceed status + ** + ** \retval TRUE The Scan FIFO is empty [ScanFifoEmptyStatus] + ** The Scan FIFO is full [ScanFifoFullStatus] + ** Priority FIFO is empty [PrioFifoEmptyStatus] + ** Priority FIFO is full [PrioFifoFullStatus] + ** Priority level 2 conversion is pending [Prio2PendingStatus] + ** Priority conversion is in progress [PrioStatus] + ** Scan conversion is in progress [ScanStatus] + ** The sample data beyond the upper limit threshold [RangeThresholdExcessFlag] + ** \retval FALSE The Scan FIFO isn't empty [ScanFifoEmptyStatus] + ** The Scan FIFO isn't full [ScanFifoFullStatus] + ** Priority FIFO isn't empty [PrioFifoEmptyStatus] + ** Priority FIFO isn't full [PrioFifoFullStatus] + ** Priority level 2 conversion isn't pending [Prio2PendingStatus] + ** Priority conversion isn't in progress [PrioStatus] + ** The sample data below the lower limit threshold [RangeThresholdExcessFlag] + ******************************************************************************/ +boolean_t Adc_GetStatus(volatile stc_adcn_t* pstcAdc, en_adc_status_t enStatus) +{ + boolean_t bRet = FALSE; + switch (enStatus) + { + case ScanFifoEmptyStatus: + bRet = (1u == pstcAdc->SCCR_f.SEMP) ? TRUE : FALSE; + break; + case ScanFifoFullStatus: + bRet = (1u == pstcAdc->SCCR_f.SFUL) ? TRUE : FALSE; + break; + case PrioFifoEmptyStatus: + bRet = (1u == pstcAdc->PCCR_f.PEMP) ? TRUE : FALSE; + break; + case PrioFifoFullStatus: + bRet = (1u == pstcAdc->PCCR_f.PFUL) ? TRUE : FALSE; + break; + case Prio2PendingStatus: + bRet = (1u == pstcAdc->ADSR_f.PCNS) ? TRUE : FALSE; + break; + case PrioStatus: + bRet = (1u == pstcAdc->ADSR_f.PCS) ? TRUE : FALSE; + break; + case ScanStatus: + bRet = (1u == pstcAdc->ADSR_f.SCS) ? TRUE : FALSE; + break; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case RangeThresholdExcessFlag: + bRet = (1u == pstcAdc->WCMRCOT_f.RCOOF) ? TRUE : FALSE; + break; +#endif + default: + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Reads out Scan Conversion FIFO + ** + ** This function reads out the Scan Conversion FIFO. + ** + ** \pre Adc_ScanFifioStatus() should be called before + ** + ** \param [in] pstcAdc ADC instance + ** + ** \return Recent Scan Conversion FIFO value including + ** INVL, RS1, RS0, and Channel data as is. + ** If pstcAdc == NULL 0xFFFFFFFF is returned. + ******************************************************************************/ +uint32_t Adc_ReadScanFifo( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return 0xFFFFFFFFu; + } + + return pstcAdc->SCFD; +} // Adc_ReadScanFifo + + +/** + ****************************************************************************** + ** \brief Clear scan FIFO + ** + ** This function clears the FIFO for scan conversion + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok Scan FIFO cleared + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_ClrScanFifo(volatile stc_adcn_t* pstcAdc) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->SCCR_f.SFCLR = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get Channel Number from FIFO data + ** + ** This function returns the Channel data from input data from Scan Conversion + ** FIFO + ** + ** \pre Adc_ReadScanFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData FIFO data + ** + ** \return Recent Scan Conversion Channel value. + ******************************************************************************/ +uint8_t Adc_GetScanChannel(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + return (uint8_t) (0x0000001Fu & u32FifoData); +} // Adc_GetScanChannel + +/** + ****************************************************************************** + ** \brief Get Valid Data Flag from FIFO data + ** + ** This function checks the validity of scan conversion data from FIFO + ** + ** \pre Adc_ReadScanFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData FIFO data + ** + ** \retval AdcFifoDataValid Recent FIFO data valid + ** \retval AdcFifoDataInvalid Recent FIFO data invalid + ******************************************************************************/ +en_adc_fifo_data_valid_t Adc_GetScanDataValid(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + if (0u == (0x00001000u & u32FifoData)) + { + return AdcFifoDataValid; + } + + return AdcFifoDataInvalid; +} // Adc_GetScanDataValid + +/** + ****************************************************************************** + ** \brief Get Scan Conversion Start Cause from FIFO data + ** + ** This function returns the Scan Conversion Start Cause from FIFO Data + ** + ** \pre Adc_ReadScanFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData FIFO data + ** + ** \retval AdcFifoSoftwareStart Recent FIFO data cuased by Software Start + ** \retval AdcFifoTimerStart Recent FIFO data caused by Timer Start + ** \retval AdcFifoErrorStart Recent FIFO data caused by unknown factor + ******************************************************************************/ +en_adc_fifo_start_cause_t Adc_GetScanDataCause(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + if (0x00000100u == (0x00000300u & u32FifoData)) + { + return AdcFifoSoftwareStart; + } + + if (0x00000200u == (0x00000300u & u32FifoData)) + { + return AdcFifoTimerStart; + } + + return AdcFifoErrorStart; +} // Adc_GetPDataCause + +/** + ****************************************************************************** + ** \brief Get Scan Conversion FIFO data + ** + ** This function returns the Scan Conversion FIFO Data + ** + ** \pre Adc_ReadScanFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData FIFO data + ** + ** \retval FIFO data value + ******************************************************************************/ +uint16_t Adc_GetScanData(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + if(0u == pstcAdc->ADSR_f.FDAS) + { + return ((u32FifoData >> 20u) & 0xFFFu); + } + else + { + return ((u32FifoData >> 16u) & 0xFFFu); + } + +} + +/** + ****************************************************************************** + ** \brief Reads out Priority Conversion FIFO + ** + ** This function reads out the Priority Conversion FIFO. + ** + ** \pre Adc_PrioFifioStatus() should be called before + ** + ** \param [in] pstcAdc ADC instance + ** + ** \return Recent Priority Conversion FIFO value including + ** INVL, RS2, RS1, RS0, and Channel data as is. + ** If pstcAdc == NULL 0xFFFFFFFF is returned. + ******************************************************************************/ +uint32_t Adc_ReadPrioFifo( volatile stc_adcn_t* pstcAdc ) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return 0xFFFFFFFFu; + } + + return pstcAdc->PCFD; +} // Adc_ReadPrioFifo + +/** + ****************************************************************************** + ** \brief Clear priority FIFO + ** + ** This function clears the FIFO for priority conversion + ** + ** \param [in] pstcAdc ADC instance + ** + ** \retval Ok Priority FIFO cleared + ** \retval ErrorInvalidParameter pstcAdc == NULL + ******************************************************************************/ +en_result_t Adc_ClrPrioFifo(volatile stc_adcn_t* pstcAdc) +{ + // Check for NULL pointer + if (NULL == pstcAdc) + { + return ErrorInvalidParameter ; + } + + pstcAdc->PCCR_f.PFCLR = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get Channel Number from Priority FIFO data + ** + ** This function returns the Channel data from input data from Priority + ** Conversion FIFO + ** + ** \pre Adc_ReadPrioFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData Priority FIFO data + ** + ** \return Recent Priority Conversion Channel value. + ******************************************************************************/ +uint8_t Adc_GetPrioChannel(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + return (uint8_t) (0x0000001Fu & u32FifoData); +} // Adc_GetPrioChannel + +/** + ****************************************************************************** + ** \brief Get Valid Data Flag from Priority FIFO data + ** + ** This function checks the validity of priority conversion from FIFO + ** + ** \pre Adc_ReadPrioFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData Priority FIFO data + ** + ** \retval AdcFifoDataValid Recent FIFO data valid + ** \retval AdcFifoDataInvalid Recent FIFO data invalid + ******************************************************************************/ +en_adc_fifo_data_valid_t Adc_GetPrioDataValid(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + if (0u == (0x00001000u & u32FifoData)) + { + return AdcFifoDataValid; + } + + return AdcFifoDataInvalid; +} // Adc_GetPrioDataValid + +/** + ****************************************************************************** + ** \brief Get Priority Conversion Start Cause from FIFO data + ** + ** This function returns the Priority Conversion Start Cause from FIFO Data + ** + ** \pre Adc_ReadPrioFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData Priority FIFO data + ** + ** \retval AdcFifoSoftwareStart Recent FIFO data cuased by Software Start + ** \retval AdcFifoTimerStart Recent FIFO data causde by Timer Start + ** \retval AdcFifoExternalTrigger Recent FIFO data causde by External Trigger + ** \retval AdcFifoErrorStart Recent FIFO data causde by unknown factor + ******************************************************************************/ +en_adc_fifo_start_cause_t Adc_GetPrioDataCause(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + if (0x00000100u == (0x00000700u & u32FifoData)) + { + return AdcFifoSoftwareStart; + } + + if (0x00000200u == (0x00000700u & u32FifoData)) + { + return AdcFifoTimerStart; + } + + if (0x00000400u == (0x00000700u & u32FifoData)) + { + return AdcFifoExternalTrigger; + } + + return AdcFifoErrorStart; +} // Adc_GetPrioDataCause + +/** + ****************************************************************************** + ** \brief Get Priority Conversion FIFO data + ** + ** This function returns the Priority Conversion FIFO Data + ** + ** \pre Adc_ReadPrioFifo() must be called before + ** + ** \param [in] pstcAdc ADC instance + ** \param [in] u32FifoData FIFO data + ** + ** \retval FIFO data value + ******************************************************************************/ +uint16_t Adc_GetPrioData(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ) +{ + if(0u == pstcAdc->ADSR_f.FDAS) + { + return ((u32FifoData >> 20u) & 0xFFFu); + } + else + { + return ((u32FifoData >> 16u) & 0xFFFu); + } + +} + +#endif // #if (defined(PDL_PERIPHERAL_ADC_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.h new file mode 100644 index 0000000000..a8d7f95849 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/adc/adc.h @@ -0,0 +1,576 @@ +/****************************************************************************** +* \file adc.h +* +* \version 1.20 +* +* \brief Header file of 12 bit ADC (ADC) driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ +#ifndef __ADC_H__ +#define __ADC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_ADC_ACTIVE)) + +#if defined (__CC_ARM) + #pragma anon_unions +#endif + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupADC 12-Bit Analog Digital Converter (ADC) +* \{ +* \defgroup GroupADC_Macros Macros +* \defgroup GroupADC_Functions Functions +* \defgroup GroupADC_GlobalVariables Global Variables +* \defgroup GroupADC_DataStructures Data Structures +* \defgroup GroupADC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupADC +* \{ +* 12 bit Analog-Digital Convertor (ADC) converts analog input voltage +* from an external pin to a digital value.
+* The FM Family MCU hardware supports up to three ADC units. Each ADC:
+* - has 12 bit resolution +* - can receive a signal from any of up to 32 analog input channels +* - has two independently-configured sampling rates +* - has a FIFO buffer to store results +* You can configure the ADC to start a conversion based on:
+* - trigger input from an external pin +* - timer trigger input using base timer or multifunction timer +* - a software function call +* +* \section SectionADC_ConfigurationConsideration Configuration Consideration +* There are two structures you need to set up:
+* - stc_adc_config_t
+* - stc_adc_scan_t
+* +* Provide configuration parameters such as the number of ADC channels, trigger +* signals for scan conversion, and interrupt sources.
+* The ADC supports two sampling rates per instance. You set values in the +* configuration structure to specify the two sampling rates.
+* The sampling rate is determined by this formula:
+* Sampling Time = HCLK cycles x Clock Divisor x (Base Sampling Time +1) x Sampling Multiplier + 3
+* +* - clock divisor (u8ComparingClockDiv) +* - sampling time for each sampling rate (u8SamplingTime0, u8SamplingTime1) +* - the sampling rate multiplier (enSamplingTimeN0, enSamplingTimeN1) +* +* Based on the formula and the clock (HCLK) these values determine the samples-per-second (SPS).
+* +* You also configure which of the two sampling rates to use for an analog channel. +* You can change which sampling rate you use at runtime. For example, you may have a sensor that +* you sample slowly in certain conditions, and quickly in other conditions.
+* +* Notes: +* - For setting the sampling time, refer to the "Electrical Characteristics" in the +* "Data Sheet" to make sure that you set an appropriate time in +* accordance with the external impedance of an input channel, an analog power +* supply voltage (AVCC), and a base clock (HCLK) cycle.
+* +* \section SectionADC_MoreInfo More Information +* For more information on the ADC peripheral, refer to:
+* FM0+ Peripheral Manual - Analog Subsystem TRM.pdf
+* FM4 Peripheral Manual - Analog Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + + +/** +* \addtogroup GroupADC_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_adcn_t FM_ADC_TypeDef +#define ADC0 (*((volatile stc_adcn_t *) FM_ADC0_BASE)) +#define ADC1 (*((volatile stc_adcn_t *) FM_ADC1_BASE)) +#define ADC2 (*((volatile stc_adcn_t *) FM_ADC2_BASE)) + +#define PDL_ADC_READY_WAIT_COUNT 1000000u /* Time-out counter value for ADC ready bit polling */ + +#define ADC_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_ADC0 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_ADC1 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_ADC2 == PDL_ON) + +#define ADC0_SCAN_FIFO_ADDR (uint32_t)(&FM_ADC0->SCFD) +#define ADC1_SCAN_FIFO_ADDR (uint32_t)(&FM_ADC1->SCFD) +#define ADC2_SCAN_FIFO_ADDR (uint32_t)(&FM_ADC2->SCFD) + +// ADC types +#define PDL_ADC_A 0u +#define PDL_ADC_B 1u + +// Check the ADC type according to a certain device +#if (PDL_MCU_TYPE == PDL_FM3_TYPE0) || (PDL_MCU_TYPE == PDL_FM3_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE2) || (PDL_MCU_TYPE == PDL_FM3_TYPE4) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE5) +#define PDL_ADC_TYPE PDL_ADC_A +#else +#define PDL_ADC_TYPE PDL_ADC_B +#endif + +/** \} GroupADC_Macros */ + +/** +* \addtogroup GroupADC_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Scan Conversion Mode + ******************************************************************************/ +typedef enum en_adc_scan_mode +{ + ScanSingleConversion = 0u, ///< Single mode of scan conversion + ScanRepeatConversion = 1u ///< Repeat mode of scan conversion +} en_adc_scan_mode_t; + +/** + ****************************************************************************** + ** \brief Priority Conversion Stage Count + ******************************************************************************/ +typedef enum en_adc_sample_time_n +{ + Value1 = 0u, ///< Set value * 1 + Value4 = 1u, ///< Set value * 4 + Value8 = 2u, ///< Set value * 8 + Value16 = 3u, ///< Set value * 16 + Value32 = 4u, ///< Set value * 32 + Value64 = 5u, ///< Set value * 64 + Value128 = 6u, ///< Set value * 128 + Value256 = 7u, ///< Set value * 256 +} en_adc_sample_time_n_t; + +#if (PDL_ADC_TYPE == PDL_ADC_A) +#if((PDL_MCU_TYPE != PDL_FM3_TYPE0)) +/** + ****************************************************************************** + ** \brief The basic cycle selection of enable state transition + ** + ** \note This setting is only available for TYPE 0,1,2,5 of FM3 products. + ** The final enable state transition time is also related with comparing + ** clock division setting, see peripheral manual for details. + ******************************************************************************/ +typedef enum en_adc_enable_cycle +{ + AdcEnableCycle36 = 0u, ///< Set basic cycle to 36 + AdcEnableCycle20 = 1u, ///< Set basic cycle to 20 + AdcEnableCycle9 = 2u, ///< Set basic cycle to 9 + AdcEnableCycle44 = 3u, ///< Set basic cycle to 44 + +}en_adc_enable_cycle_t; +#endif +#endif + +/** + ****************************************************************************** + ** \brief ADC scan/priority conversion timer trigger selection + ** \note Do not change the numbering. + ******************************************************************************/ +typedef enum en_adc_timer_select +{ + AdcNoTimer = 0u, ///< No selected trigger + AdcMft = 1u, ///< Trigger by Multifunction Timer + AdcBt0 = 2u, ///< Trigger with Base Timer 0 + AdcBt1 = 3u, ///< Trigger with Base Timer 1 + AdcBt2 = 4u, ///< Trigger with Base Timer 2 + AdcBt3 = 5u, ///< Trigger with Base Timer 3 + AdcBt4 = 6u, ///< Trigger with Base Timer 4 + AdcBt5 = 7u, ///< Trigger with Base Timer 5 + AdcBt6 = 8u, ///< Trigger with Base Timer 6 + AdcBt7 = 9u, ///< Trigger with Base Timer 7 + +} en_adc_timer_select_t; + +/** + ****************************************************************************** + ** \brief FIFO valid data result (Scan, Priority Conversion) + ******************************************************************************/ +typedef enum en_adc_fifo_data_valid +{ + AdcFifoDataInvalid = 0u, ///< FIFO data invalid + AdcFifoDataValid = 1u ///< FIFO data valid +} en_adc_fifo_data_valid_t; + +/** + ****************************************************************************** + ** \brief FIFO data start cause + ******************************************************************************/ +typedef enum en_adc_fifo_start_cause +{ + AdcFifoSoftwareStart = 0u, ///< FIFO data software start cause (Scan & Prio2 Conversion) + AdcFifoTimerStart = 1u, ///< FIFO data timer start cause (Scan & Prio2 Conversion) + AdcFifoExternalTrigger = 2u, ///< FIFO data external trigger cause (Prio1 Conversion) + AdcFifoErrorStart = 3u ///< FIFO data caused by unknown factor (Scan & Prio2 Conversion) +} en_adc_fifo_start_cause_t; + +/** + ****************************************************************************** + ** \brief ADC status list + ******************************************************************************/ +typedef enum en_adc_status +{ + ScanFifoEmptyStatus = 0u, ///< Scan FIFO empty status + ScanFifoFullStatus = 1u, ///< Scan FIFO full status + PrioFifoEmptyStatus = 2u, ///< Priority FIFO empty status + PrioFifoFullStatus = 3u, ///< Priority FIFO full status + Prio2PendingStatus = 4u, ///< Priority conversion (level 2) pending status + PrioStatus = 5u, ///< Priority conversion status + ScanStatus = 6u, ///< Scan conversion status +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + RangeThresholdExcessFlag = 7u, ///< Range comparison threshold exceed status +#endif + +}en_adc_status_t; + +/** + ****************************************************************************** + ** \brief ADC interrupt type + ******************************************************************************/ +typedef enum en_adc_irq +{ + AdcScanIrq = 0u, ///< Scan conversion interrupt request + AdcPrioIrq = 1u, ///< Priority conversion interrupt request + AdcScanFifoOverrunIrq = 2u, ///< Scan FIFO overrun interrupt request + AdcPrioFifoOverrunIrq = 3u, ///< Priority FIFO overrun interrupt request + AdcComparisonIrq = 4u, ///< ADC comparison interrupt request +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + AdcRangeComparisonIrq = 5u, ///< ADC range comparison interrupt request +#endif +}en_adc_irq_t; + +/// Enumeration to define an index for each enabled ADC instance +typedef enum en_adc_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_ADC0 == PDL_ON) + AdcInstanceIndexAdc0, + #endif + #if (PDL_PERIPHERAL_ENABLE_ADC1 == PDL_ON) + AdcInstanceIndexAdc1, + #endif + #if (PDL_PERIPHERAL_ENABLE_ADC2 == PDL_ON) + AdcInstanceIndexAdc2, + #endif + AdcInstanceIndexMax +} en_adc_instance_index_t; + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + +/** \}GroupADC_Types */ + +/** +* \addtogroup GroupADC_DataStructures +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +typedef void (*func_ptr_adc_parg32_t)(volatile uint32_t* pu32Argument); + +/** + ****************************************************************************** + ** \brief ADC Channel list with same sort order as the ER32 registers + ******************************************************************************/ +typedef struct stc_ad_channel_list +{ + union + { + uint32_t u32AD_CHn; + struct /* stcChannelBits */ + { + uint32_t AD_CH_0 : 1 ; + uint32_t AD_CH_1 : 1 ; + uint32_t AD_CH_2 : 1 ; + uint32_t AD_CH_3 : 1 ; + uint32_t AD_CH_4 : 1 ; + uint32_t AD_CH_5 : 1 ; + uint32_t AD_CH_6 : 1 ; + uint32_t AD_CH_7 : 1 ; + uint32_t AD_CH_8 : 1 ; + uint32_t AD_CH_9 : 1 ; + uint32_t AD_CH_10 : 1 ; + uint32_t AD_CH_11 : 1 ; + uint32_t AD_CH_12 : 1 ; + uint32_t AD_CH_13 : 1 ; + uint32_t AD_CH_14 : 1 ; + uint32_t AD_CH_15 : 1 ; + uint32_t AD_CH_16 : 1 ; + uint32_t AD_CH_17 : 1 ; + uint32_t AD_CH_18 : 1 ; + uint32_t AD_CH_19 : 1 ; + uint32_t AD_CH_20 : 1 ; + uint32_t AD_CH_21 : 1 ; + uint32_t AD_CH_22 : 1 ; + uint32_t AD_CH_23 : 1 ; + uint32_t AD_CH_24 : 1 ; + uint32_t AD_CH_25 : 1 ; + uint32_t AD_CH_26 : 1 ; + uint32_t AD_CH_27 : 1 ; + uint32_t AD_CH_28 : 1 ; + uint32_t AD_CH_29 : 1 ; + uint32_t AD_CH_30 : 1 ; + uint32_t AD_CH_31 : 1 ; + }; + }; +} stc_ad_channel_list_t ; + +/** + ****************************************************************************** + ** \brief Scan Conversion configuration + ******************************************************************************/ +typedef struct stc_adc_scan +{ + en_adc_scan_mode_t enScanMode; ///< Conversion Mode. See #en_adc_scan_mode_t for details + stc_ad_channel_list_t u32ScanCannelSelect; ///< Selects scan channels for ADC (1 = active) + boolean_t bScanTimerStartEnable; ///< TRUE: Triggers Scan Conversion by Timer + en_adc_timer_select_t enScanTimerTrigger; ///< See #en_adc_timer_select_t for details + uint8_t u8ScanFifoDepth; ///< Depth of the Scan Conversion FIFO 0...15 + +}stc_adc_scan_t; + +/** + ****************************************************************************** + ** \brief Priority Conversion configuration + ******************************************************************************/ +typedef struct stc_adc_prio +{ + boolean_t bPrioExtTrigStartEnable; ///< TRUE: Triggers Prioritys Conversion on falling edge of external signal + boolean_t bPrioTimerStartEnable; ///< TRUE: Triggers Priority Conversion by Timer + en_adc_timer_select_t enPrioTimerTrigger; ///< See #en_adc_timer_select_t for details + uint8_t u8PrioFifoDepth; ///< Depth of the Priority Conversion FIFO 0...3 + uint8_t u8PrioLevel1AnalogChSel; ///< Priority Level 1 Analog Channel Selector Ch. 0...7 + uint8_t u8PrioLevel2AnalogChSel; ///< Priority Level 2 Analog Channel Selector Ch. 0...31 + +}stc_adc_prio_t; + +/** + ****************************************************************************** + ** \brief Comparison configuration + ******************************************************************************/ +typedef struct stc_adc_compare +{ + uint16_t u16CompareValue; ///< ADC Comparison Value (CMPD) + boolean_t bCompareAllChannels; ///< TRUE: Compare all selected Channels, FALSE: Compare CCH-Channel + uint8_t u8CompareChannel; ///< CCH-Channel to be compared, if selected Ch. 0...31 + boolean_t bCompIrqEqualGreater; ///< TRUE: Generate Interrupt, if CMPD most significant 10 bis >= current ADC value + ///< FALSE: Generate Interrupt, if CMPD most significant 10 bis < current ADC value +}stc_adc_comapre_t, stc_adc_compare_t; + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Range comparison configuration + ******************************************************************************/ +typedef struct stc_adc_range_compare +{ + uint16_t u16UpperLimitRangeValue; ///< Upper Limit Value for Range Comparison + uint16_t u16LowerLimitRangeValue; ///< Lower limit Value for Range Comparison + uint8_t u8RangeCountValue; ///< Range Count Value 1...7 + boolean_t bWithinRange; ///< TRUE: Value within Range, FALSE: Value out of Range + boolean_t bRangeCompareAllChannels; ///< TRUE: Range compare all selected Channels, FALSE: Compare WCCH-Channel + uint8_t u8RangeCompareChannel; ///< WCCH-Channel to be Range compared, if selected Ch. 0...31 + +}stc_adc_range_compare_t; +#endif + +/** + ****************************************************************************** + ** \brief ADC interrupt selection. + ******************************************************************************/ +typedef struct stc_adc_irq_sel +{ + boolean_t bScanIrq; ///< TRUE: Enable Scan Conversion Interrupt + boolean_t bPrioIrq; ///< TRUE: Enable Priority Conversion Interrupt + boolean_t bFifoOverrunIrq; ///< TRUE: Enable FIFO Overrun Interrupt + boolean_t bComparisonIrq; ///< TRUE: Enable Conversion Comparison Interrupt +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bRangeComparisonIrq; ///< TRUE: Enable Range Comparison Interrupt +#endif +}stc_adc_irq_sel_t, stc_adc_irq_en_t; + +/** + ****************************************************************************** + ** \brief ADC interrupt callback function & internal data structure. + ******************************************************************************/ +typedef struct stc_adc_irq_cb +{ + func_ptr_adc_parg32_t pfnScanIrqCb; ///< Scan conversion interrupt callback pointer + func_ptr_adc_parg32_t pfnPrioIrqCb; ///< Priority conversion interrupt callback + func_ptr_t pfnScanErrIrqCb; ///< Scan FIFO overrun error callback pointer + func_ptr_t pfnPrioErrIrqCb; ///< Priority FIFO overrun error callback pointer + func_ptr_t pfnComparisonIrqCb; ///< Comparison interrupt callback pointer +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + func_ptr_t pfnRangeComparisonIrqCb; ///< Range condition interrupt callback pointer +#endif + +}stc_adc_irq_cb_t, stc_adc_intern_data_t; + +/** + ****************************************************************************** + ** \brief ADC configuration. + ******************************************************************************/ +typedef struct stc_adc_config +{ + boolean_t bLsbAlignment; ///< TURE: Result is LSB aligned + stc_ad_channel_list_t u32SamplingTimeSelect; ///< Selects channels for Sampling time 0 or 1 setting + en_adc_sample_time_n_t enSamplingTimeN0; ///< Sampling Time N0 Time Setting Bits, see #en_adc_sample_time_n_t for details + uint8_t u8SamplingTime0; ///< Sampling Time 0 0...15 + en_adc_sample_time_n_t enSamplingTimeN1; ///< Sampling Time N1 Time Setting Bits, see #en_adc_sample_time_n_t for details + uint8_t u8SamplingTime1; ///< Sampling Time 1 0...15 + uint8_t u8ComparingClockDiv; ///< Multiplier of N, see Peripheral Manual for Details! +#if (PDL_ADC_TYPE == PDL_ADC_A) + #if((PDL_MCU_TYPE != PDL_FM3_TYPE0)) + en_adc_enable_cycle_t enEnableCycle; ///< Set the basic cycle of operation enable state transitions, see Peripheral Manual for Details! + #endif +#elif (PDL_ADC_TYPE == PDL_ADC_B) + uint8_t u8EnableTime; ///< Enable Time +#endif + stc_adc_scan_t* pstcScanInit; ///< Pointer to scan coversion configuration structure, scan coversion won't be intialized when it is set to NULL. + stc_adc_prio_t* pstcPrioInit; ///< Pointer to priority coversion configuration structure, priority coversion won't be intialized when it is set to NULL. + stc_adc_compare_t* pstcComparisonInit; ///< Pointer to comparison structure, comparison function won't be intialized when it is set to NULL. +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + stc_adc_range_compare_t* pstcRangeComparisonInit; ///< Pointer to range comparison structure, range comparison function won't be intialized when it is set to NULL. +#endif + + stc_adc_irq_en_t* pstcIrqEn; ///< Pointer to ADC interrupts enable structure + stc_adc_irq_cb_t* pstcIrqCb; ///< Pointer to the structure of ADC interrupt request callback functions + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC + +} stc_adc_config_t; + +/// ADC instance data type +typedef struct stc_adc_instance_data +{ + volatile stc_adcn_t* pstcInstance; ///< pointer to registers of an instance + stc_adc_intern_data_t stcInternData; ///< module internal data of instance +} stc_adc_instance_data_t; + +/** \} GroupADC_DataStructures */ + +/** +* \addtogroup GroupADC_GlobalVariables +* \{ +*/ + +/// Look-up table for all enabled ADC instances and their internal data +extern stc_adc_instance_data_t m_astcAdcInstanceDataLut[ADC_INSTANCE_COUNT]; + +/** \} GroupADC_GlobalVariables */ + +/** +* \addtogroup GroupADC_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +/* Init/De-Init */ +en_result_t Adc_Init( volatile stc_adcn_t* pstcAdc, + const stc_adc_config_t* pstcConfig ); +en_result_t Adc_DeInit( volatile stc_adcn_t* pstcAdc, + boolean_t bTouchNvic); + +#if (PDL_INTERRUPT_ENABLE_ADC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ADC2 == PDL_ON) +/* Int Enable/Disable */ +en_result_t Adc_EnableIrq(volatile stc_adcn_t* pstcAdc, + stc_adc_irq_sel_t* pstcIrqSel); +en_result_t Adc_DisableIrq(volatile stc_adcn_t* pstcAdc, + stc_adc_irq_sel_t* pstcIrqSel); +/* ADC IRQ */ +void AdcIrqHandler( volatile stc_adcn_t* pstcAdc, + stc_adc_intern_data_t* pstcAdcInternData ); +#endif +/* Int Flag get/clear */ +boolean_t Adc_GetIrqFlag(volatile stc_adcn_t* pstcAdc, + en_adc_irq_t enIrq); +en_result_t Adc_ClrIrqFlag(volatile stc_adcn_t* pstcAdc, + en_adc_irq_t enIrq); + +/* ADC enable/disable */ +en_result_t Adc_Enable( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_Ready( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_EnableWaitReady( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_Disable( volatile stc_adcn_t* pstcAdc ); + +/* ADC conversion start/stop */ +en_result_t Adc_SwTriggerScan( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_StopScanRepeat( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_StartScanRepeat( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_SwTriggerPrio( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_ForceStop( volatile stc_adcn_t* pstcAdc ); +/* Status */ +boolean_t Adc_GetStatus(volatile stc_adcn_t* pstcAdc, + en_adc_status_t enStatus); +/* FIFO read/clear */ +uint32_t Adc_ReadScanFifo( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_ClrScanFifo(volatile stc_adcn_t* pstcAdc); +uint8_t Adc_GetScanChannel( volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); +en_adc_fifo_data_valid_t Adc_GetScanDataValid( volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); +en_adc_fifo_start_cause_t Adc_GetScanDataCause( volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); +uint16_t Adc_GetScanData( volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); + +uint32_t Adc_ReadPrioFifo( volatile stc_adcn_t* pstcAdc ); +en_result_t Adc_ClrPrioFifo(volatile stc_adcn_t* pstcAdc); +uint8_t Adc_GetPrioChannel(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); +en_adc_fifo_data_valid_t Adc_GetPrioDataValid(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); +en_adc_fifo_start_cause_t Adc_GetPrioDataCause(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); +uint16_t Adc_GetPrioData(volatile stc_adcn_t* pstcAdc, + uint32_t u32FifoData ); + +/** \} GroupADC_Functions */ +/** \} GroupADC */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_ADC_ACTIVE)) + +#endif /* __ADC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/base_types.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/base_types.h new file mode 100644 index 0000000000..29ca887887 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/base_types.h @@ -0,0 +1,103 @@ +/******************************************************************************* +* \file base_types.h +* +* \version 1.0 +* +* \brief Additional base type definitions to stddef.h and stdint.h. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __BASE_TYPES_H__ +#define __BASE_TYPES_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include +#include "stdint.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#ifndef TRUE + /** Value is true (boolean_t type) */ + #define TRUE ((boolean_t) 1) +#endif + +#ifndef FALSE + /** Value is false (boolean_t type) */ + #define FALSE ((boolean_t) 0) +#endif + +/** Returns the minimum value out of two values */ +#define MIN( X, Y ) ((X) < (Y) ? (X) : (Y)) + +/** Returns the maximum value out of two values */ +#define MAX( X, Y ) ((X) > (Y) ? (X) : (Y)) + +/** Returns the dimension of an array */ +#define DIM( X ) (sizeof(X) / sizeof(X[0])) + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** logical datatype (only values are TRUE and FALSE) */ +typedef uint8_t boolean_t; + +/** single precision floating point number (4 byte) */ +typedef float float32_t; + +/** double precision floating point number (8 byte) */ +typedef double float64_t; + +/** ASCCI character for string generation (8 bit) */ +typedef char char_t; + +/** function pointer type to void/void function */ +typedef void (*func_ptr_t)(void); + +/** function pointer type to void/uint8_t function */ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** generic error codes */ +typedef enum en_result +{ + Ok = 0, ///< No error + Error = 1, ///< Non-specific error code + ErrorAddressAlignment = 2, ///< Address alignment does not match + ErrorAccessRights = 3, ///< Wrong mode (e.g. user/system) mode is set + ErrorInvalidParameter = 4, ///< Provided parameter is not valid + ErrorOperationInProgress = 5, ///< A conflicting or requested operation is still in progress + ErrorInvalidMode = 6, ///< Operation not allowed in current mode + ErrorUninitialized = 7, ///< Module (or part of it) was not initialized properly + ErrorBufferFull = 8, ///< Circular buffer can not be written because the buffer is full + ErrorTimeout = 9, ///< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) + ErrorNotReady = 10, ///< A requested final state is not reached + OperationInProgress = 11 ///< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) +} en_result_t; + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#endif /* __BASE_TYPES_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.c new file mode 100644 index 0000000000..bfa6f878cf --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.c @@ -0,0 +1,2481 @@ +/****************************************************************************** +* \file bt.c +* +* \version 1.20 +* +* \brief Base Timer (BT) driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "bt/bt.h" + +#if (defined(PDL_PERIPHERAL_BT_ACTIVE)) +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled BT instances and their internal data +stc_bt_instance_data_t m_astcBtInstanceDataLut[BT_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) + { + &BT0, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) + { + &BT1, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) + { + &BT2, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) + { + &BT3, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) + { + &BT4, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) + { + &BT5, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) + { + &BT6, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) + { + &BT7, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT8 == PDL_ON) + { + &BT8, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT9 == PDL_ON) + { + &BT9, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT10 == PDL_ON) + { + &BT10, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT11 == PDL_ON) + { + &BT11, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT12 == PDL_ON) + { + &BT12, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT13 == PDL_ON) + { + &BT13, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT14 == PDL_ON) + { + &BT14, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_BT15 == PDL_ON) + { + &BT15, // pstcInstance + {0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +}; + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain BT instance. + ** + ** \param pstcBt Pointer to BT instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_bt_intern_data_t* BtGetInternDataPtr(volatile stc_btn_t* pstcBt) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < BT_INSTANCE_COUNT; u32Instance++) + { + if (pstcBt == m_astcBtInstanceDataLut[u32Instance].pstcInstance) + { + return &m_astcBtInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +#if defined(PDL_INTERRUPT_BT_ACTIVE) +/** + ****************************************************************************** + ** \brief BT interrupt service routine + ** + ** \param pstcBt BT instance + ** \param pstcBtInternData Pointer to BT internal data + ** + ******************************************************************************/ +void Bt_IrqHandler( volatile stc_btn_t* pstcBt, + stc_bt_intern_data_t* pstcBtInternData) +{ + uint8_t u8Irq; + + // Get Interrupt Request + u8Irq = pstcBt->STC; + /* + * Trigger Interrupt (PWM,PPG,Reload timer) + * Measurement completion Interrupt (PWC) + */ + if ((1ul << 2u) == (u8Irq & (1ul << 2u))) + { + // Clear Interrupt + pstcBt->STC &= ~(1ul << 2u); + + if (pstcBtInternData->pfnBit2IrqCb != NULL) + { + // Call CallBackIrq + pstcBtInternData->pfnBit2IrqCb(); + } + } + + // Duty Match Interrupt (PWM) + if ((1ul << 1u) == (u8Irq & (1ul << 1u))) + { + // Clear Interrupt + pstcBt->STC &= ~(1ul << 1u); + + if (pstcBtInternData->pfnBit1IrqCb != NULL) + { + // Call CallBackIrq + pstcBtInternData->pfnBit1IrqCb(); + } + } + + /* + * Underflow Interrupt (PWM,PPG,Reload timer) + * Overflow Interrupt (PWC) + */ + if (1ul == (u8Irq & 1ul)) + { + // Clear Interrupt + pstcBt->STC &= ~1ul; + + if (pstcBtInternData->pfnBit0IrqCb != NULL) + { + // Call CallBackIrq + pstcBtInternData->pfnBit0IrqCb(); + } + } + +} + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on BT instance + ** + ** \param pstcBt Pointer to BT instance + ** + ******************************************************************************/ +static void BtInitNvic(volatile stc_btn_t* pstcBt) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) + NVIC_ClearPendingIRQ(BT0_3_FLASHIF_IRQn); + NVIC_EnableIRQ(BT0_3_FLASHIF_IRQn); + NVIC_SetPriority(BT0_3_FLASHIF_IRQn, PDL_IRQ_LEVEL_BT0_7_FLASHIF); +#elif (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) + if((pstcBt == &BT0) || (pstcBt == &BT4)) + { + NVIC_ClearPendingIRQ(BT0_4_IRQn); + NVIC_EnableIRQ(BT0_4_IRQn); + NVIC_SetPriority(BT0_4_IRQn, PDL_IRQ_LEVEL_BT0_4); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) + if((pstcBt == &BT1) || (pstcBt == &BT5)) + { + NVIC_ClearPendingIRQ(BT1_5_IRQn); + NVIC_EnableIRQ(BT1_5_IRQn); + NVIC_SetPriority(BT1_5_IRQn, PDL_IRQ_LEVEL_BT1_5); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) + if((pstcBt == &BT2) || (pstcBt == &BT6)) + { + NVIC_ClearPendingIRQ(BT2_6_IRQn); + NVIC_EnableIRQ(BT2_6_IRQn); + NVIC_SetPriority(BT2_6_IRQn, PDL_IRQ_LEVEL_BT2_6); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) + if((pstcBt == &BT3) || (pstcBt == &BT7)) + { + NVIC_ClearPendingIRQ(BT3_7_IRQn); + NVIC_EnableIRQ(BT3_7_IRQn); + NVIC_SetPriority(BT3_7_IRQn, PDL_IRQ_LEVEL_BT3_7); + } + #endif +#else + NVIC_ClearPendingIRQ(BT0_7_FLASHIF_IRQn); + NVIC_EnableIRQ(BT0_7_FLASHIF_IRQn); + NVIC_SetPriority(BT0_7_FLASHIF_IRQn, PDL_IRQ_LEVEL_BT0_7_FLASHIF); +#endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(BT0_7_IRQn); + NVIC_EnableIRQ(BT0_7_IRQn); + NVIC_SetPriority(BT0_7_IRQn, PDL_IRQ_LEVEL_BT0_7); +#elif (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) + if(pstcBt == &BT0) + { + NVIC_ClearPendingIRQ(BT0_IRQn); + NVIC_EnableIRQ(BT0_IRQn); + NVIC_SetPriority(BT0_IRQn, PDL_IRQ_LEVEL_BT0); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) + if(pstcBt == &BT1) + { + NVIC_ClearPendingIRQ(BT1_IRQn); + NVIC_EnableIRQ(BT1_IRQn); + NVIC_SetPriority(BT1_IRQn, PDL_IRQ_LEVEL_BT1); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) + if(pstcBt == &BT2) + { + NVIC_ClearPendingIRQ(BT2_IRQn); + NVIC_EnableIRQ(BT2_IRQn); + NVIC_SetPriority(BT2_IRQn, PDL_IRQ_LEVEL_BT2); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) + if(pstcBt == &BT3) + { + NVIC_ClearPendingIRQ(BT3_IRQn); + NVIC_EnableIRQ(BT3_IRQn); + NVIC_SetPriority(BT3_IRQn, PDL_IRQ_LEVEL_BT3); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) + if(pstcBt == &BT4) + { + NVIC_ClearPendingIRQ(BT4_IRQn); + NVIC_EnableIRQ(BT4_IRQn); + NVIC_SetPriority(BT4_IRQn, PDL_IRQ_LEVEL_BT4); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) + if(pstcBt == &BT5) + { + NVIC_ClearPendingIRQ(BT5_IRQn); + NVIC_EnableIRQ(BT5_IRQn); + NVIC_SetPriority(BT5_IRQn, PDL_IRQ_LEVEL_BT5); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) + if(pstcBt == &BT6) + { + NVIC_ClearPendingIRQ(BT6_IRQn); + NVIC_EnableIRQ(BT6_IRQn); + NVIC_SetPriority(BT6_IRQn, PDL_IRQ_LEVEL_BT6); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) + if(pstcBt == &BT7) + { + NVIC_ClearPendingIRQ(BT7_IRQn); + NVIC_EnableIRQ(BT7_IRQn); + NVIC_SetPriority(BT7_IRQn, PDL_IRQ_LEVEL_BT7); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT8 == PDL_ON) + if(pstcBt == &BT8) + { + NVIC_ClearPendingIRQ(BT8_IRQn); + NVIC_EnableIRQ(BT8_IRQn); + NVIC_SetPriority(BT8_IRQn, PDL_IRQ_LEVEL_BT8); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT9 == PDL_ON) + if(pstcBt == &BT9) + { + NVIC_ClearPendingIRQ(BT9_IRQn); + NVIC_EnableIRQ(BT9_IRQn); + NVIC_SetPriority(BT9_IRQn, PDL_IRQ_LEVEL_BT9); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT10 == PDL_ON) + if(pstcBt == &BT10) + { + NVIC_ClearPendingIRQ(BT10_IRQn); + NVIC_EnableIRQ(BT10_IRQn); + NVIC_SetPriority(BT10_IRQn, PDL_IRQ_LEVEL_BT10); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT11 == PDL_ON) + if(pstcBt == &BT11) + { + NVIC_ClearPendingIRQ(BT11_IRQn); + NVIC_EnableIRQ(BT11_IRQn); + NVIC_SetPriority(BT11_IRQn, PDL_IRQ_LEVEL_BT11); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT15 == PDL_ON) + if((pstcBt == &BT12) || (pstcBt == &BT13) || (pstcBt == &BT14) || (pstcBt == &BT15)) + { + NVIC_ClearPendingIRQ(BT12_15_IRQn); + NVIC_EnableIRQ(BT12_15_IRQn); + NVIC_SetPriority(BT12_15_IRQn, PDL_IRQ_LEVEL_BT12_13_14_15); + } + #endif + +#endif +} + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on BT instance + ** + ** \param pstcBt Pointer to BT instance + ** + ******************************************************************************/ +static void BtDeInitNvic(volatile stc_btn_t* pstcBt) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) + NVIC_ClearPendingIRQ(BT0_3_FLASHIF_IRQn); + NVIC_DisableIRQ(BT0_3_FLASHIF_IRQn); + NVIC_SetPriority(BT0_3_FLASHIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) + NVIC_ClearPendingIRQ(BT0_4_IRQn); + NVIC_DisableIRQ(BT0_4_IRQn); + NVIC_SetPriority(BT0_4_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #if (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) + NVIC_ClearPendingIRQ(BT1_5_IRQn); + NVIC_DisableIRQ(BT1_5_IRQn); + NVIC_SetPriority(BT1_5_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #if (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) + NVIC_ClearPendingIRQ(BT2_6_IRQn); + NVIC_DisableIRQ(BT2_6_IRQn); + NVIC_SetPriority(BT2_6_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #if (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) + NVIC_ClearPendingIRQ(BT3_7_IRQn); + NVIC_DisableIRQ(BT3_7_IRQn); + NVIC_SetPriority(BT3_7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#else + NVIC_ClearPendingIRQ(BT0_7_FLASHIF_IRQn); + NVIC_DisableIRQ(BT0_7_FLASHIF_IRQn); + NVIC_SetPriority(BT0_7_FLASHIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(BT0_7_IRQn); + NVIC_DisableIRQ(BT0_7_IRQn); + NVIC_SetPriority(BT0_7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) + if(&BT0 == pstcBt) + { + NVIC_ClearPendingIRQ(BT0_IRQn); + NVIC_DisableIRQ(BT0_IRQn); + NVIC_SetPriority(BT0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) + if(&BT1 == pstcBt) + { + NVIC_ClearPendingIRQ(BT1_IRQn); + NVIC_DisableIRQ(BT1_IRQn); + NVIC_SetPriority(BT1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) + if(&BT2 == pstcBt) + { + NVIC_ClearPendingIRQ(BT2_IRQn); + NVIC_DisableIRQ(BT2_IRQn); + NVIC_SetPriority(BT2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) + if(&BT3 == pstcBt) + { + NVIC_ClearPendingIRQ(BT3_IRQn); + NVIC_DisableIRQ(BT3_IRQn); + NVIC_SetPriority(BT3_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) + if(&BT4 == pstcBt) + { + NVIC_ClearPendingIRQ(BT4_IRQn); + NVIC_DisableIRQ(BT4_IRQn); + NVIC_SetPriority(BT4_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) + if(&BT5 == pstcBt) + { + NVIC_ClearPendingIRQ(BT5_IRQn); + NVIC_DisableIRQ(BT5_IRQn); + NVIC_SetPriority(BT5_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) + if(&BT6 == pstcBt) + { + NVIC_ClearPendingIRQ(BT6_IRQn); + NVIC_DisableIRQ(BT6_IRQn); + NVIC_SetPriority(BT6_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) + if(&BT7 == pstcBt) + { + NVIC_ClearPendingIRQ(BT7_IRQn); + NVIC_DisableIRQ(BT7_IRQn); + NVIC_SetPriority(BT7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT8 == PDL_ON) + if(&BT8 == pstcBt) + { + NVIC_ClearPendingIRQ(BT8_IRQn); + NVIC_DisableIRQ(BT8_IRQn); + NVIC_SetPriority(BT8_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT9 == PDL_ON) + if(&BT9 == pstcBt) + { + NVIC_ClearPendingIRQ(BT9_IRQn); + NVIC_DisableIRQ(BT9_IRQn); + NVIC_SetPriority(BT9_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT10 == PDL_ON) + if(&BT10 == pstcBt) + { + NVIC_ClearPendingIRQ(BT10_IRQn); + NVIC_DisableIRQ(BT10_IRQn); + NVIC_SetPriority(BT10_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT11 == PDL_ON) + if(&BT11 == pstcBt) + { + NVIC_ClearPendingIRQ(BT11_IRQn); + NVIC_DisableIRQ(BT11_IRQn); + NVIC_SetPriority(BT11_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_BT12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT15 == PDL_ON) + if ((&BT12 == pstcBt) || (&BT13 == pstcBt) || (&BT14 == pstcBt) || (&BT15 == pstcBt)) + { + NVIC_ClearPendingIRQ(BT12_15_IRQn); + NVIC_DisableIRQ(BT12_15_IRQn); + NVIC_SetPriority(BT12_15_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif +#endif + + return; +} + +#endif + +/** + ****************************************************************************** + ** \brief Configure BT IO mode + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIoMode BT IO mode + ** \arg BtIoMode0 BT IO mode 0 + ** \arg BtIoMode1 BT IO mode 1 + ** \arg BtIoMode2 BT IO mode 2 + ** \arg BtIoMode3 BT IO mode 3 + ** \arg BtIoMode4 BT IO mode 4 + ** \arg BtIoMode5 BT IO mode 5 + ** \arg BtIoMode6 BT IO mode 6 + ** \arg BtIoMode7 BT IO mode 7 + ** \arg BtIoMode8 BT IO mode 8 + ** + ** \retval Ok BT IO mode has been set successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_ConfigIOMode(volatile stc_btn_t* pstcBt, en_bt_io_mode_t enIoMode) +{ + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + // Check for NULL pointer + if ((NULL == pstcBt) || (enIoMode > BtIoMode8)) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + if((&BT0 == pstcBt) || (&BT1 == pstcBt)) + { + FM_BTIOSEL03->BTSEL0123_f.SEL01 = (uint8_t)enIoMode; + } + else if((&BT2 == pstcBt) || (&BT3 == pstcBt)) + { + FM_BTIOSEL03->BTSEL0123_f.SEL23 = (uint8_t)enIoMode; + } +#if (defined(FM_BTIOSEL47_AVAILABLE)) + else if((&BT4 == pstcBt) || (&BT5 == pstcBt)) + { + FM_BTIOSEL47->BTSEL4567_f.SEL45 = (uint8_t)enIoMode; + } + else if((&BT6 == pstcBt) || (&BT7 == pstcBt)) + { + FM_BTIOSEL47->BTSEL4567_f.SEL67 = (uint8_t)enIoMode; + } +#endif + + return Ok; +} + +#if (PDL_PERIPHERAL_ENABLE_BT_PWM_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize PWM function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] pstcPwmConfig Pointer to PWM configuration + ** + ** \retval Ok PWM function has been configured successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwm_Init(volatile stc_btn_t* pstcBt, const stc_bt_pwm_config_t* pstcPwmConfig) +{ + volatile FM_BT_PWM_TypeDef* pRegBt = (volatile FM_BT_PWM_TypeDef*)pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + uint16_t u16Pres; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + // Reset Base Timer mode + pRegBt->TMCR_f.FMD = BtResetMode; + // Set Base Timer to PWM mode + pRegBt->TMCR_f.FMD = BtPwmMode; + + // Clock prescaler setting + u16Pres = pstcPwmConfig->enPres; // Workaround for MISRA-C 2004 rule 12.7 + switch (pstcPwmConfig->enPres) + { + case PwmPresNone: + case PwmPres1Div4: + case PwmPres1Div16: + case PwmPres1Div128: + case PwmPres1Div256: + case PwmPres1ExtClkRising: + case PwmPres1ExtClkFalling: + case PwmPres1ExtClkBoth: + pRegBt->TMCR2_f.CKS3 = 0u; + pRegBt->TMCR_f.CKS = u16Pres; + break; + case PwmPres1Div512: + case PwmPres1Div1024: + case PwmPres1Div2048: + pRegBt->TMCR2_f.CKS3 = 1u; + pRegBt->TMCR_f.CKS = (u16Pres & 0x07u); + break; + } + // Restart enable setting + switch (pstcPwmConfig->enRestartEn) + { + case PwmRestartDisable: + pRegBt->TMCR_f.RTGEN = 0u; + break; + case PwmRestartEnable: + pRegBt->TMCR_f.RTGEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + // Output Mask setting + switch (pstcPwmConfig->enOutputMask) + { + case PwmOutputNormal: + pRegBt->TMCR_f.PMSK = 0u; + break; + case PwmOutputMask: + pRegBt->TMCR_f.PMSK = 1u; + break; + default: + return ErrorInvalidParameter; + } + // Output polarity setting + switch (pstcPwmConfig->enOutputPolarity) + { + case PwmPolarityLow: + pRegBt->TMCR_f.OSEL = 0u; + break; + case PwmPolarityHigh: + pRegBt->TMCR_f.OSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + // External trigger setting + switch (pstcPwmConfig->enExtTrig) + { + case PwmExtTrigDisable: + pRegBt->TMCR_f.EGS = 0u; + break; + case PwmExtTrigRising: + pRegBt->TMCR_f.EGS = 1u; + break; + case PwmExtTrigFalling: + pRegBt->TMCR_f.EGS = 2u; + break; + case PwmExtTrigBoth: + pRegBt->TMCR_f.EGS = 3u; + break; + default: + return ErrorInvalidParameter; + } + // Mode setting + switch (pstcPwmConfig->enMode) + { + case PwmContinuous: + pRegBt->TMCR_f.MDSE = 0u; + break; + case PwmOneshot: + pRegBt->TMCR_f.MDSE = 1u; + break; + default: + return ErrorInvalidParameter; + } + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + // Interrupt enable setting + if(NULL != pstcPwmConfig->pstcPwmIrqEn) + { + if(TRUE == pstcPwmConfig->pstcPwmIrqEn->bPwmTrigIrq) + { + pRegBt->STC_f.TGIE = 1u; + } + + if(TRUE == pstcPwmConfig->pstcPwmIrqEn->bPwmDutyMatchIrq) + { + pRegBt->STC_f.DTIE = 1u; + } + + if(TRUE == pstcPwmConfig->pstcPwmIrqEn->bPwmUnderflowIrq) + { + pRegBt->STC_f.UDIE = 1u; + } + } + + // Interrupt callback functions + if(NULL != pstcPwmConfig->pstcPwmIrqCb) + { + pstcBtInternData->pfnBit2IrqCb = pstcPwmConfig->pstcPwmIrqCb->pfnPwmTrigIrqCb; + pstcBtInternData->pfnBit1IrqCb = pstcPwmConfig->pstcPwmIrqCb->pfnPwmDutyMatchIrqCb; + pstcBtInternData->pfnBit0IrqCb = pstcPwmConfig->pstcPwmIrqCb->pfnPwmUnderflowIrqCb; + } + + // NVIC setting + if(TRUE == pstcPwmConfig->bTouchNvic) + { + BtInitNvic(pstcBt); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize PWM function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok PWM function has been de-initialized successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwm_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic) +{ + volatile FM_BT_PWM_TypeDef* pRegBt = (volatile FM_BT_PWM_TypeDef*)pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + pRegBt->TMCR = 0x0000u; + pRegBt->TMCR2 = 0x0000u; + pRegBt->PCSR = 0x0000u; + pRegBt->STC = 0x0000u; + pRegBt->PDUT = 0x0000u; +#if defined(PDL_INTERRUPT_BT_ACTIVE) + if(TRUE == bTouchNvic) + { + BtDeInitNvic(pstcBt); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable PWM timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Enable PWM timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Pwm_EnableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->TMCR_f.CTEN = 1u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PWM timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Disable PWM timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Pwm_DisableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->TMCR_f.CTEN = 0u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start PWM timer by software + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Start PWM timer successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Pwm_EnableSwTrig(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->TMCR_f.STRG = 1u; + return Ok; +} + +#if defined(PDL_INTERRUPT_BT_ACTIVE) +/** + ****************************************************************************** + ** \brief Enable PWM timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWM timer interrupt type + ** \arg PwmTrigIrq PWM trigger detection interrupt + ** \arg PwmDutyMatchIrq PWM duty match interrupt + ** \arg PwmUnderflowIrq PWM underflow interrupt + ** + ** \retval Ok Enable PWM timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwm_EnableIrq(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PwmTrigIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.TGIE = 1u; + break; + case PwmDutyMatchIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.DTIE = 1u; + break; + case PwmUnderflowIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.UDIE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PWM timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWM timer interrupt type + ** \arg PwmTrigIrq PWM trigger detection interrupt + ** \arg PwmDutyMatchIrq PWM duty match interrupt + ** \arg PwmUnderflowIrq PWM underflow interrupt + ** + ** \retval Ok Disable PWM timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwm_DisableIrq(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PwmTrigIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.TGIE = 0u; + break; + case PwmDutyMatchIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.DTIE = 0u; + break; + case PwmUnderflowIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.UDIE = 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of PWM timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWM timer interrupt type + ** \arg PwmTrigIrq PWM trigger detection interrupt + ** \arg PwmDutyMatchIrq PWM duty match interrupt + ** \arg PwmUnderflowIrq PWM underflow interrupt + ** + ** \retval PdlSet Interrupt flag is set + ** \retval PdlClr Interrupt flag is clear + ******************************************************************************/ +en_irq_flag_t Bt_Pwm_GetIrqFlag(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel) +{ + en_irq_flag_t enFlag = PdlClr; + + switch (enIrqSel) + { + case PwmTrigIrq: + enFlag = ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.TGIR ? PdlSet : PdlClr; + break; + case PwmDutyMatchIrq: + enFlag = ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.DTIR ? PdlSet : PdlClr; + break; + case PwmUnderflowIrq: + enFlag = ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.UDIR ? PdlSet : PdlClr; + break; + default: + break; + } + + return enFlag; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of PWM timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWM timer interrupt type + ** \arg PwmTrigIrq PWM trigger detection interrupt + ** \arg PwmDutyMatchIrq PWM duty match interrupt + ** \arg PwmUnderflowIrq PWM underflow interrupt + ** + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - enIntType > PwmUnderflowInt + ** \retval Ok Clear interrupt flag successfully + ******************************************************************************/ +en_result_t Bt_Pwm_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel) +{ + if(NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PwmTrigIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.TGIR = 0u; + break; + case PwmDutyMatchIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.DTIR = 0u; + break; + case PwmUnderflowIrq: + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->STC_f.UDIR = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write Cycle value of PWM timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] u16Cycle Cycle value + ** + ** \retval Ok Write Cycle value successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Pwm_WriteCycleVal(volatile stc_btn_t* pstcBt, uint16_t u16Cycle) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->PCSR = u16Cycle; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write duty value of PWM timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] u16Duty Duty value + ** + ** \retval Ok Write duty value successfully + ** \retval ErrorInvalidParameter pstcBt == NUL + ******************************************************************************/ +en_result_t Bt_Pwm_WriteDutyVal(volatile stc_btn_t* pstcBt, uint16_t u16Duty) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWM_TypeDef*)pstcBt)->PDUT = u16Duty; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read current count value of PWM timer + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Current count value + ******************************************************************************/ +uint16_t Bt_Pwm_ReadCurCnt(volatile stc_btn_t* pstcBt) +{ + return ((volatile FM_BT_PWM_TypeDef*)pstcBt)->TMR; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_BT_PPG_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize PPG function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] pstcPpgConfig Pointer to PPG configuration + ** + ** \retval Ok PPG function has been configured successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Ppg_Init(volatile stc_btn_t* pstcBt, const stc_bt_ppg_config_t* pstcPpgConfig) +{ + volatile FM_BT_PPG_TypeDef* pRegBt = (volatile FM_BT_PPG_TypeDef*)pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + uint16_t u16Pres; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + // Reset Base Timer mode + pRegBt->TMCR_f.FMD = BtResetMode; + // Set Base Timer to PPG mode + pRegBt->TMCR_f.FMD = BtPpgMode; + + // Clock prescaler setting + u16Pres = pstcPpgConfig->enPres; // Workaround for MISRA-C 2004 rule 12.7 + switch (pstcPpgConfig->enPres) + { + case PpgPresNone: + case PpgPres1Div4: + case PpgPres1Div16: + case PpgPres1Div128: + case PpgPres1Div256: + case PpgPres1ExtClkRising: + case PpgPres1ExtClkFalling: + case PpgPres1ExtClkBoth: + pRegBt->TMCR2_f.CKS3 = 0u; + pRegBt->TMCR_f.CKS = u16Pres; + break; + case PpgPres1Div512: + case PpgPres1Div1024: + case PpgPres1Div2048: + pRegBt->TMCR2_f.CKS3 = 1u; + pRegBt->TMCR_f.CKS = (u16Pres & 0x7u); + break; + default: + return ErrorInvalidParameter ; + } + // Restart enable setting + switch (pstcPpgConfig->enRestartEn) + { + case PpgRestartDisable: + pRegBt->TMCR_f.RTGEN = 0u; + break; + case PpgRestartEnable: + pRegBt->TMCR_f.RTGEN = 1u; + break; + default: + return ErrorInvalidParameter ; + } + // Output Mask setting + pRegBt->TMCR_f.PMSK = (uint8_t)pstcPpgConfig->enOutputMask; + switch (pstcPpgConfig->enOutputMask) + { + case PpgOutputNormal: + pRegBt->TMCR_f.PMSK = 0u; + break; + case PpgOutputMask: + pRegBt->TMCR_f.PMSK = 1u; + break; + default: + return ErrorInvalidParameter ; + } + // Output polarity setting + switch (pstcPpgConfig->enOutputPolarity) + { + case PpgPolarityLow: + pRegBt->TMCR_f.OSEL = 0u; + break; + case PpgPolarityHigh: + pRegBt->TMCR_f.OSEL = 1u; + break; + default: + return ErrorInvalidParameter ; + } + // External trigger setting + switch (pstcPpgConfig->enExtTrig) + { + case PpgExtTrigDisable: + pRegBt->TMCR_f.EGS = 0u; + break; + case PpgExtTrigRising: + pRegBt->TMCR_f.EGS = 1u; + break; + case PpgExtTrigFalling: + pRegBt->TMCR_f.EGS = 2u; + break; + case PpgExtTrigBoth: + pRegBt->TMCR_f.EGS = 3u; + break; + default: + return ErrorInvalidParameter ; + } + // Mode setting + switch (pstcPpgConfig->enMode) + { + case PpgContinuous: + pRegBt->TMCR_f.MDSE = 0u; + break; + case PpgOneshot: + pRegBt->TMCR_f.MDSE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + // Interrupt enable setting + if (NULL != pstcPpgConfig->pstcPpgIrqEn) + { + if(pstcPpgConfig->pstcPpgIrqEn->bPpgTrigIrq == TRUE) + { + pRegBt->STC_f.TGIE = 1; + } + if(pstcPpgConfig->pstcPpgIrqEn->bPpgUnderflowIrq == TRUE) + { + pRegBt->STC_f.UDIE = 1; + } + } + + // Interrupt callback functions + if (NULL != pstcPpgConfig->pstcPpgIrqCb) + { + pstcBtInternData->pfnBit2IrqCb = pstcPpgConfig->pstcPpgIrqCb->pfnPpgTrigIrqCb; + pstcBtInternData->pfnBit0IrqCb = pstcPpgConfig->pstcPpgIrqCb->pfnPpgUnderflowIrqCb; + } + // NVIC setting + if(pstcPpgConfig->bTouchNvic == TRUE) + { + BtInitNvic(pstcBt); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize PPG function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok PPG function has been de-initialized successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Ppg_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic) +{ + volatile FM_BT_PPG_TypeDef* pRegBt = (volatile FM_BT_PPG_TypeDef*)pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + pRegBt->TMCR = 0x0000u; + pRegBt->TMCR2 = 0x0000u; + pRegBt->STC = 0x0000u; + pRegBt->PRLL = 0x0000u; + pRegBt->PRLH = 0x0000u; + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + if(TRUE == bTouchNvic) + { + BtDeInitNvic(pstcBt); + } +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable PPG timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Enable PPG timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Ppg_EnableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->TMCR_f.CTEN = 1u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PPG timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Disable PPG timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Ppg_DisableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->TMCR_f.CTEN = 0u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start PPG timer by software + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Start PPG timer successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Ppg_EnableSwTrig(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->TMCR_f.STRG = 1u; + return Ok; +} + +#if defined(PDL_INTERRUPT_BT_ACTIVE) +/** + ****************************************************************************** + ** \brief Enable PPG timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PPG timer interrupt type + ** \arg PpgTrigIrq PPG trigger detection interrupt + ** \arg PpgUnderflowIrq PPG underflow interrupt + ** + ** \retval Ok Enable PPG timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Ppg_EnableIrq(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel) +{ + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PpgTrigIrq: + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.TGIE = 1u; + break; + case PpgUnderflowIrq: + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.UDIE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PPG timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PPG timer interrupt type + ** \arg PpgTrigIrq PPG trigger detection interrupt + ** \arg PpgUnderflowIrq PPG underflow interrupt + ** + ** \retval Ok Disable PPG timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Ppg_DisableIrq(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PpgTrigIrq: + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.TGIE = 0u; + break; + case PpgUnderflowIrq: + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.UDIE = 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of PPG timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PPG timer interrupt type + ** \arg PpgTrigIrq PPG trigger detection interrupt + ** \arg PpgUnderflowIrq PPG underflow interrupt + ** + ** \retval PdlSet Interrupt flag is set + ** \retval PdlClr Interrupt flag is clear + ******************************************************************************/ +en_irq_flag_t Bt_Ppg_GetIrqFlag(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel) +{ + en_irq_flag_t enFlag = PdlClr; + + switch (enIrqSel) + { + case PpgTrigIrq: + enFlag = ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.TGIR ? PdlSet : PdlClr; + break; + case PpgUnderflowIrq: + enFlag = ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.UDIR ? PdlSet : PdlClr; + break; + default: + break; + } + + return enFlag; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of PPG timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PPG timer interrupt type + ** \arg PpgTrigIrq PPG trigger detection interrupt + ** \arg PpgUnderflowIrq PPG underflow interrupt + ** + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - enIntType > PwmUnderflowInt + ** \retval Ok Clear interrupt flag successfully + ******************************************************************************/ +en_result_t Bt_Ppg_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel) +{ + if(NULL == pstcBt) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case PpgTrigIrq: + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.TGIR = 0u; + break; + case PpgUnderflowIrq: + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->STC_f.UDIR = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write low width count value of PPG timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] u16Val Low width count value + ** + ** \retval Ok Write low width count value successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Ppg_WriteLowWidthVal(volatile stc_btn_t* pstcBt, uint16_t u16Val) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->PRLL = u16Val; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write high width count value of PPG timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] u16Val High width count value + ** + ** \retval Ok Write high width count value successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Ppg_WriteHighWidthVal(volatile stc_btn_t* pstcBt, uint16_t u16Val) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PPG_TypeDef*)pstcBt)->PRLH = u16Val; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read current count value of PPG timer + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Current count value + ******************************************************************************/ +uint16_t Bt_Ppg_ReadCurCnt(volatile stc_btn_t* pstcBt) +{ + return ((volatile FM_BT_PPG_TypeDef*)pstcBt)->TMR; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_BT_RT_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize RT function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] pstcRtConfig Pointer to RT configuration + ** + ** \retval Ok RT function has been configured successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Rt_Init(volatile stc_btn_t* pstcBt, const stc_bt_rt_config_t* pstcRtConfig) +{ + volatile FM_BT_RT_TypeDef* pRegBt = (volatile FM_BT_RT_TypeDef*) pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + uint16_t u16Pres, u16ExtTrig; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + // Reset Base Timer mode + pRegBt->TMCR_f.FMD = BtResetMode; + // Set Base Timer to Reload Timer mode + pRegBt->TMCR_f.FMD = BtRtMode; + + // Clock prescaler setting + u16Pres = pstcRtConfig->enPres; // Workaround for MISRA-C 2004 rule 12.7 + switch (pstcRtConfig->enPres) + { + case RtPresNone: + case RtPres1Div4: + case RtPres1Div16: + case RtPres1Div128: + case RtPres1Div256: + case RtPres1ExtClkRising: + case RtPres1ExtClkFalling: + case RtPres1ExtClkBoth: + pRegBt->TMCR2_f.CKS3 = 0u; + pRegBt->TMCR_f.CKS = u16Pres; + break; + case RtPres1Div512: + case RtPres1Div1024: + case RtPres1Div2048: + pRegBt->TMCR2_f.CKS3 = 1u; + pRegBt->TMCR_f.CKS = (u16Pres & 0x7u); + break; + default: + return ErrorInvalidParameter ; + } + // Timer size setting + switch (pstcRtConfig->enSize) + { + case RtSize16Bit: + pRegBt->TMCR_f.T32 = 0u; + break; + case RtSize32Bit: + pRegBt->TMCR_f.T32 = 1u; + break; + default: + return ErrorInvalidParameter ; + } + // Output polarity setting + switch (pstcRtConfig->enOutputPolarity) + { + case RtPolarityLow: + pRegBt->TMCR_f.OSEL = 0u; + break; + case RtPolarityHigh: + pRegBt->TMCR_f.OSEL = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + // External trigger setting + u16ExtTrig = pstcRtConfig->enExtTrig; // Workaround for MISRA-C 2004 rule 12.7 + switch (pstcRtConfig->enExtTrig) + { + case RtExtTiggerDisable: + case RtExtTiggerRisingEdge: + case RtExtTiggerFallingEdge: + pRegBt->TMCR_f.EGS = u16ExtTrig; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case RtExtTiggerBothEdge: + pRegBt->TMCR2_f.GATE = 0u; + pRegBt->TMCR_f.EGS = u16ExtTrig; + break; + case RtExtTiggerLowLevel: + pRegBt->TMCR2_f.GATE = 1u; + pRegBt->TMCR_f.EGS = 0u; + break; + case RtExtTiggerHighLevel: + pRegBt->TMCR2_f.GATE = 1u; + pRegBt->TMCR_f.EGS = 1u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + // Mode setting + switch (pstcRtConfig->enMode) + { + case RtReload: + pRegBt->TMCR_f.MDSE = 0u; + break; + case RtOneshot: + pRegBt->TMCR_f.MDSE = 1u; + break; + default: + return ErrorInvalidParameter; + } + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + // Interrupt enable setting + if(NULL != pstcRtConfig->pstcRtIrqEn) + { + if(pstcRtConfig->pstcRtIrqEn->bRtTrigIrq == TRUE) + { + pRegBt->STC_f.TGIE = 1u; + } + + if(pstcRtConfig->pstcRtIrqEn->bRtUnderflowIrq == TRUE) + { + pRegBt->STC_f.UDIE = 1u; + } + } + // Interrupt callback functions setting + if(NULL != pstcRtConfig->pstcRtIrqCb) + { + pstcBtInternData->pfnBit2IrqCb = pstcRtConfig->pstcRtIrqCb->pfnRtTrigIrqCb; + pstcBtInternData->pfnBit0IrqCb = pstcRtConfig->pstcRtIrqCb->pfnRtUnderflowIrqCb; + } + // NVIC setting + if(TRUE == pstcRtConfig->bTouchNvic) + { + BtInitNvic(pstcBt); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize RT function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok RT function has been de-initialized successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Rt_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic) +{ + volatile FM_BT_RT_TypeDef* pRegBt = (volatile FM_BT_RT_TypeDef*)pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + pRegBt->TMCR = 0x0000u; + pRegBt->TMCR2 = 0x0000u; + pRegBt->STC = 0x0000u; + pRegBt->PCSR = 0x0000u; + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + if(TRUE == bTouchNvic) + { + BtDeInitNvic(pstcBt); + } +#endif + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Enable Reload timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Enable RT timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Rt_EnableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_RT_TypeDef*)pstcBt)->TMCR_f.CTEN = 1u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable Reload timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Disable RT timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Rt_DisableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_RT_TypeDef*)pstcBt)->TMCR_f.CTEN = 0u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start Reload timer by software + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Start Reload timer successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Rt_EnableSwTrig(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_RT_TypeDef*)pstcBt)->TMCR_f.STRG = 1u; + return Ok; +} + +#if defined(PDL_INTERRUPT_BT_ACTIVE) +/** + ****************************************************************************** + ** \brief Enable Reload timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel Reload Timer interrupt type + ** \arg RtTrigIrq Reload timer trigger detection flag + ** \arg RtUnderflowIrq Reload timer underflow interrupt flag + ** + ** \retval Ok Enable Reload timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Rt_EnableIrq(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case RtTrigIrq: + ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.TGIE = 1u; + break; + case RtUnderflowIrq: + ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.UDIE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable Reload timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel Reload Timer interrupt type + ** \arg RtTrigIrq Reload timer trigger detection flag + ** \arg RtUnderflowIrq Reload timer underflow interrupt flag + ** + ** \retval Ok Disable Reload timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Rt_DisableIrq(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case RtTrigIrq: + ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.TGIE = 0u; + break; + case RtUnderflowIrq: + ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.UDIE = 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of Reload timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel Reload timer interrupt type + ** \arg RtTrigIrq Reload timer trigger detection flag + ** \arg RtUnderflowIrq Reload timer underflow interrupt flag + ** + ** \retval PdlSet Interrupt flag is set + ** \retval PdlClr Interrupt flag is clear + ******************************************************************************/ +en_irq_flag_t Bt_Rt_GetIrqFlag(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel) +{ + en_irq_flag_t enFlag = PdlClr; + + switch (enIrqSel) + { + case RtTrigIrq: + enFlag = ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.TGIR ? PdlSet : PdlClr; + break; + case RtUnderflowIrq: + enFlag = ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.UDIR ? PdlSet : PdlClr; + break; + default: + break; + } + + return enFlag; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of Reload timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel Reload timer interrupt type + ** \arg RtTrigIrq Reload timer trigger detection flag + ** \arg RtUnderflowIrq Reload timer underflow interrupt flag + ** + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - enIntType > RtUnderflowIrq + ** \retval Ok Clear interrupt flag successfully + ******************************************************************************/ +en_result_t Bt_Rt_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel) +{ + if(NULL == pstcBt) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RtTrigIrq: + ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.TGIR = 0u; + break; + case RtUnderflowIrq: + ((volatile FM_BT_RT_TypeDef*)pstcBt)->STC_f.UDIR = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief Write count cycle of Reload timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] u16Val Cycle value + ** + ** \retval Ok Write count cycle successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Rt_WriteCycleVal(volatile stc_btn_t* pstcBt, uint16_t u16Val) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_RT_TypeDef*)pstcBt)->PCSR = u16Val; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read current count value of Reload timer + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Current count value + ******************************************************************************/ +uint16_t Bt_Rt_ReadCurCnt(volatile stc_btn_t* pstcBt) +{ + return ((volatile FM_BT_RT_TypeDef*)pstcBt)->TMR; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_BT_PWC_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize PWC function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] pstcPwcConfig Pointer to PWC configuration + ** + ** \retval Ok PWC function has been configured successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwc_Init(volatile stc_btn_t* pstcBt, const stc_bt_pwc_config_t* pstcPwcConfig) +{ + volatile FM_BT_PWC_TypeDef* pRegBt = (volatile FM_BT_PWC_TypeDef*) pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + uint16_t u16Pres; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + // Reset Base Timer mode + pRegBt->TMCR_f.FMD = BtResetMode; + // Set Base Timer to Reload Timer mode + pRegBt->TMCR_f.FMD = BtPwcMode; + + // Clock prescaler setting + u16Pres = pstcPwcConfig->enPres; // workaround for MISRA-C 2004 rule 12.7 + switch (pstcPwcConfig->enPres) + { + case PwcPresNone: + case PwcPres1Div4: + case PwcPres1Div16: + case PwcPres1Div128: + case PwcPres1Div256: + pRegBt->TMCR2_f.CKS3 = 0u; + pRegBt->TMCR_f.CKS = u16Pres; + break; + case PwcPres1Div512: + case PwcPres1Div1024: + case PwcPres1Div2048: + pRegBt->TMCR2_f.CKS3 = 1u; + pRegBt->TMCR_f.CKS = (u16Pres & 0x07u); + break; + default: + return ErrorInvalidParameter ; + } + // Timer size setting + switch (pstcPwcConfig->enSize) + { + case PwcSize16Bit: + pRegBt->TMCR_f.T32 = 0u; + break; + case PwcSize32Bit: + pRegBt->TMCR_f.T32 = 1u; + break; + default: + return ErrorInvalidParameter ; + } + // Measurement mode setting + switch (pstcPwcConfig->enMeasureEdge) + { + case PwcMeasureRisingToFalling: + pRegBt->TMCR_f.EGS = 0u; + break; + case PwcMeasureRisingToRising: + pRegBt->TMCR_f.EGS = 1u; + break; + case PwcMeasureFallingToFalling: + pRegBt->TMCR_f.EGS = 2u; + break; + case PwcMeasureEitherToEither: + pRegBt->TMCR_f.EGS = 3u; + break; + case PwcMeasureFallingToRising: + pRegBt->TMCR_f.EGS = 4u; + break; + default: + return ErrorInvalidParameter ; + } + // Mode setting + switch (pstcPwcConfig->enMode) + { + case PwcContinuous: + pRegBt->TMCR_f.MDSE = 0u; + break; + case PwcOneshot: + pRegBt->TMCR_f.MDSE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + // Interrupt enable setting + if(NULL != pstcPwcConfig->pstcPwcIrqEn) + { + if(pstcPwcConfig->pstcPwcIrqEn->bPwcMeasureCompleteIrq == TRUE) + { + pRegBt->STC_f.EDIE = 1u; + } + + if(pstcPwcConfig->pstcPwcIrqEn->bPwcMeasureOverflowIrq == TRUE) + { + pRegBt->STC_f.OVIE = 1u; + } + } + + // Interrupt callback functions + if (NULL != pstcPwcConfig->pstcPwcIrqCb) + { + pstcBtInternData->pfnBit2IrqCb = pstcPwcConfig->pstcPwcIrqCb->pfnPwcMeasureCompleteIrqCb; + pstcBtInternData->pfnBit0IrqCb = pstcPwcConfig->pstcPwcIrqCb->pfnPwcMeasureOverflowIrqCb; + } + + // NVIC setting + if(pstcPwcConfig->bTouchNvic == TRUE) + { + BtInitNvic(pstcBt); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize PWC function of BT + ** + ** \param [in] pstcBt BT instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok PWC function has been de-initialized successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwc_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic) +{ + volatile FM_BT_PWC_TypeDef* pRegBt = (volatile FM_BT_PWC_TypeDef*)pstcBt; + // Pointer to internal data + stc_bt_intern_data_t* pstcBtInternData ; + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcBtInternData = BtGetInternDataPtr( pstcBt ) ; + + if(NULL == pstcBtInternData) + { + return ErrorInvalidParameter ; + } + + pRegBt->TMCR = 0x0000u; + pRegBt->TMCR2 = 0x0000u; + pRegBt->STC = 0x0000u; + +#if defined(PDL_INTERRUPT_BT_ACTIVE) + if(TRUE == bTouchNvic) + { + BtDeInitNvic(pstcBt); + } +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable PWC timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Enable PWC timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Pwc_EnableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->TMCR_f.CTEN = 1u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PWC timer counting + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Ok Disable PWC timer counting successfully + ** \retval ErrorInvalidParameter pstcBt == NULL + ******************************************************************************/ +en_result_t Bt_Pwc_DisableCount(volatile stc_btn_t* pstcBt) +{ + // Check for NULL pointer + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->TMCR_f.CTEN = 0u; + return Ok; +} + +#if defined(PDL_INTERRUPT_BT_ACTIVE) +/** + ****************************************************************************** + ** \brief Enable PWC timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWC timer interrupt type + ** \arg PwcMeasureCompleteIrq PWC measure complete interrupt + ** \arg PwcMeasureOverflowIrq PWC overflow interrupt + ** + ** \retval Ok Enable PWC timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwc_EnableIrq(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PwcMeasureCompleteIrq: + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.EDIE = 1u; + break; + case PwcMeasureOverflowIrq: + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.OVIE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PWC timer interrupt + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWC timer interrupt type + ** \arg PwcMeasureCompleteIrq PWC measure complete interrupt + ** \arg PwcMeasureOverflowIrq PWC overflow interrupt + ** + ** \retval Ok Disable PWC timer interrupt successfully + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Bt_Pwc_DisableIrq(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel) +{ + // Check parameter + if (NULL == pstcBt) + { + return ErrorInvalidParameter ; + } + + switch (enIrqSel) + { + case PwcMeasureCompleteIrq: + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.EDIE = 0u; + break; + case PwcMeasureOverflowIrq: + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.OVIE = 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of PWC timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWC timer interrupt type + ** \arg PwcMeasureCompleteIrq PWC measure complete interrupt + ** \arg PwcMeasureOverflowIrq PWC overflow interrupt + ** + ** \retval PdlSet Interrupt flag is set + ** \retval PdlClr Interrupt flag is clear + ******************************************************************************/ +en_irq_flag_t Bt_Pwc_GetIrqFlag(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel) +{ + en_irq_flag_t enFlag = PdlClr; + + switch (enIrqSel) + { + case PwcMeasureCompleteIrq: + enFlag = ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.EDIR ? PdlSet : PdlClr; + break; + case PwcMeasureOverflowIrq: + enFlag = ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.OVIR ? PdlSet : PdlClr; + break; + default: + break; + } + + return enFlag; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of PWC timer + ** + ** \param [in] pstcBt BT instance + ** \param [in] enIrqSel PWC timer interrupt type + ** \arg PwcMeasureCompleteIrq PWC measure complete interrupt + ** \arg PwcMeasureOverflowIrq PWC overflow interrupt + ** + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcBt == NULL + ** - enIntType > PwcMeasureOverflowIrq + ** \retval Ok Clear interrupt flag successfully + ******************************************************************************/ +en_result_t Bt_Pwc_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel) +{ + if(NULL == pstcBt) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case PwcMeasureCompleteIrq: + break; + case PwcMeasureOverflowIrq: + ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.OVIR = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get error flag of PWC timer + ** + ** If the measured data is not read out when the next data is coming, + ** the error flag will be set. + ** + ** \param [in] pstcBt BT instance + ** + ** \retval PdlSet Error flag is set + ** \retval PdlClr Error flag is clear + ******************************************************************************/ +en_stat_flag_t Bt_Pwc_GetErrorFlag(volatile stc_btn_t* pstcBt) +{ + en_irq_flag_t enFlag; + + enFlag = ((volatile FM_BT_PWC_TypeDef*)pstcBt)->STC_f.ERR ? PdlSet : PdlClr; + + return enFlag; +} + +/** + ****************************************************************************** + ** \brief Get 16 bits measure data of PWC timer + ** + ** This function reads measure data in 16-bit timer mode. + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Measure data + ******************************************************************************/ +uint16_t Bt_Pwc_Get16BitMeasureData(volatile stc_btn_t* pstcBt) +{ + uint16_t u16RegDtbf; + u16RegDtbf = ((volatile FM_BT_PWC_TypeDef*)pstcBt)->DTBF; + return u16RegDtbf; +} + +/** + ****************************************************************************** + ** \brief Get 32 bits measure data of PWC timer + ** + ** This function reads measure data in 32-bit timer mode, the input BT instance + ** should point to register base address of even channel. + ** + ** \param [in] pstcBt BT instance + ** + ** \retval Measure data + ******************************************************************************/ +uint32_t Bt_Pwc_Get32BitMeasureData(volatile stc_btn_t* pstcBt) +{ + uint16_t u16RegLow, u16RegHigh; + +#if (defined(FM_BTIOSEL47_AVAILABLE)) + if((&BT1 == pstcBt) || (&BT3 == pstcBt) || (&BT5 == pstcBt) || (&BT7 == pstcBt)) + { + return 0ul; + } +#else + if((&BT1 == pstcBt) || (&BT3 == pstcBt)) + { + return 0ul; + } +#endif + u16RegLow = ((volatile FM_BT_PWC_TypeDef*)pstcBt)->DTBF; + u16RegHigh = ((volatile FM_BT_PWC_TypeDef*)((volatile uint8_t*)pstcBt + 0x40u))->DTBF; + return (((uint32_t)u16RegHigh<<16) | (uint32_t)u16RegLow); +} +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Set the Simultaneous Start register of Base timer + ** + ** This function is only valid in BTIO mode 5 and mode 6, otherwise don't + ** use this function! + ** + ** \param [in] u16Value Bit0 ----- Ch.0 + ** Bit1 ----- Ch.1 + ** ... + ** Bit15 ----- Ch.15 + ** + ** \retval None + ******************************************************************************/ +void Bt_SetSimultaneousStart(uint16_t u16Value) +{ + FM_SBSSR->BTSSSR = u16Value; +} +#endif + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.h new file mode 100644 index 0000000000..7f5c74fc95 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/bt/bt.h @@ -0,0 +1,959 @@ +/****************************************************************************** +* \file bt.h +* +* \version 1.20 +* +* \brief Header file of Base Timer (BT) driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __BT_H__ +#define __BT_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_BT_ACTIVE)) + +/** +* \defgroup GroupBT Base Timer (BT) +* \{ +* \defgroup GroupBT_Macros Macros +* \defgroup GroupBT_Functions Functions +* \defgroup GroupBT_GlobalVariables Globals Variables +* \defgroup GroupBT_DataStructures Data Structures +* \defgroup GroupBT_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupBT +* \{ GroupBT +* The Base Timer provides basic timer/counter capabilities. +* The Base Timer (BT) can operate in any of four modes:
+* - 16-bit PWM timer
+* - 16-bit PPG timer
+* - 16-/32-bit reload timer
+* - 16-/32-bit PWC timer
+* For each mode you can start the timer by software control or interrupts, +* get and clear interrupt flags, and get or set the count value.
+* +* \section SectionBT_ConfigurationConsideration Configuration Consideration +* +* To set up the BT peripheral, you first call Bt_ConfigIOMode() to configure the IO mode for the peripheral. +* Each mode has a configuration structure, init function, and enable function.
+* Depending on IO mode, you set the value of fields in the structure. +* Call to initialize the peripheral. Call to start the peripheral, +* where XXX is Ppg, Pwc, Pwm, or Rt.
+* The mode choices are:
+* - Reset Mode
+* The reset mode is a status where the base timer macros are reset (with each register set to the initial value). +* Be sure to set this mode before switching to a different timer function or T32 bit setting. However, it is not +* necessary to set this mode before setting the timer function or T32 bit immediately after the macros are +* reset.
+* +* - 16-bit PWM Timer
+* This timer consists of:
+* - a 16-bit down counter
+* - a 16-bit data register with a cycle set buffer
+* - a 16-bit compare register with a duty set buffer
+* - a pin controller
+* The cycle and duty data is stored in a buffered register and thus can be rewritten while the timer is in +* operation. +* The counter clock of the 16-bit down counter can be selected from eight internal clocks (1, 4, 16, 128, 256, +* 512, 1024, and 2048 frequency divisions of the machine clock). It can also be selected from three external events (detection of a +* rising edge, a falling edge, or both). +* The one-shot mode where the counting stops at an underflow or the continuous mode where the counting is +* repeated after reloading can be selected. +* The start event of the 16-bit PWM timer can be selected from a software trigger and three external events +* (detection of a rising edge, a falling edge, or both).
+* +* - 16-bit PPG Timer
+* This timer consists of:
+* - a 16-bit down counter
+* - a 16-bit data register for setting the HIGH width
+* - a 16-bit data register for setting the LOW width
+* - a pin controller
+* The count clock of the 16-bit down counter can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, +* 1024, and 2048 frequency divisions of the machine clock) and three external events (detection of a rising +* edge, a falling edge, or both). +* Two modes can be selected:
+* - the one-shot mode where the counting stops at an underflow
+* - the continuous mode where the counting is repeated after reloading.
+* The start event of the 16-bit PPG timer can be selected from a software trigger and three external events +* (detection of a rising edge, a falling edge, or both).
+ +* - 16/32-bit Reload Timer
+* This timer consists of:
+* - a 16-bit down counter
+* - a 16-bit reload register
+* - a pin controller
+* The count clock of the 16-bit down counter can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, +* 1024, and 2048 frequency divisions of the machine clock) and three external events (detection of a rising +* edge, a falling edge, or both). +* Two modes can be selected:
+* - the one-shot mode where the counting stops at an underflow
+* - the continuous mode where the counting is repeated after reloading.
+* The start event of the 16-/32-bit reload timer can be selected from a software trigger and three external +* events (detection of a rising edge, a falling edge, or both). +* The provided gate function executes the down count only at the effective level input from external. +* The effective level can be selected from two levels (High level or Low level).
+* +* - 16/32-bit PWC Timer
+* This timer consists of:
+* - a 16-bit up counter
+* - a measurement input pin
+* - a control register
+* This timer measures the time between any events using an external pulse input. +* The reference count clock can be selected from eight internal clocks (1, 4, 16, 128, 256, 512, 1024, and +* 2048 frequency divisions). +* Measurement modes HIGH pulse width (↑ to ↓) / LOW pulse width (↓ to ↑) +* Rising cycle (↑ to ↑) / Falling cycle (↓ to ↓) +* Edge interval measurement (↑ or ↓ to ↓ or ↑) +* An interrupt request can be generated when the measurement is completed. +* Two modes can be selected:
+* - one-time +* - continuous measurement
+* +* \section SectionBT_MoreInfo More Information +* For more information on the BT peripheral, refer to:
+* FM0+ Family 32-Bit MICROCONTROLLER PERIPHERAL MANUAL Timer Part
+* FM4 Family 32-Bit MICROCONTROLLER PERIPHERAL MANUAL Timer Part
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/* +****************************************************************************** +** + +** +******************************************************************************/ + +/** +* \addtogroup GroupBT_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_btn_t FM_BT_PWM_TypeDef + +#define BT0 (*((volatile stc_btn_t *) FM_BT0_PWM_BASE)) +#define BT1 (*((volatile stc_btn_t *) FM_BT1_PWM_BASE)) +#define BT2 (*((volatile stc_btn_t *) FM_BT2_PWM_BASE)) +#define BT3 (*((volatile stc_btn_t *) FM_BT3_PWM_BASE)) +#define BT4 (*((volatile stc_btn_t *) FM_BT4_PWM_BASE)) +#define BT5 (*((volatile stc_btn_t *) FM_BT5_PWM_BASE)) +#define BT6 (*((volatile stc_btn_t *) FM_BT6_PWM_BASE)) +#define BT7 (*((volatile stc_btn_t *) FM_BT7_PWM_BASE)) +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +#define BT8 (*((volatile stc_btn_t *) FM_BT8_PWM_BASE)) +#define BT9 (*((volatile stc_btn_t *) FM_BT9_PWM_BASE)) +#define BT10 (*((volatile stc_btn_t *) FM_BT10_PWM_BASE)) +#define BT11 (*((volatile stc_btn_t *) FM_BT11_PWM_BASE)) +#define BT12 (*((volatile stc_btn_t *) FM_BT12_PWM_BASE)) +#define BT13 (*((volatile stc_btn_t *) FM_BT13_PWM_BASE)) +#define BT14 (*((volatile stc_btn_t *) FM_BT14_PWM_BASE)) +#define BT15 (*((volatile stc_btn_t *) FM_BT15_PWM_BASE)) +#endif + +#define BT_INSTANCE_COUNT ((PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT8 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT9 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT10 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT11 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT12 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT13 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT14 == PDL_ON) ? 1u : 0u) + \ + ((PDL_PERIPHERAL_ENABLE_BT15 == PDL_ON) ? 1u : 0u) + + +#if (PDL_INTERRUPT_ENABLE_BT0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT7 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT8 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT10 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT12 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_BT14 == PDL_ON) || (PDL_INTERRUPT_ENABLE_BT15 == PDL_ON) + #define PDL_INTERRUPT_BT_ACTIVE +#endif + +/** \} GroupBT_Macros */ + +/** +* \addtogroup GroupBT_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each BT instance + ******************************************************************************/ +typedef enum en_bt_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) + BtInstanceIndexBt0, ///< Instance index of BT0 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) + BtInstanceIndexBt1, ///< Instance index of BT1 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) + BtInstanceIndexBt2, ///< Instance index of BT2 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) + BtInstanceIndexBt3, ///< Instance index of BT3 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) + BtInstanceIndexBt4, ///< Instance index of BT4 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) + BtInstanceIndexBt5, ///< Instance index of BT5 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) + BtInstanceIndexBt6, ///< Instance index of BT6 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) + BtInstanceIndexBt7, ///< Instance index of BT7 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT8 == PDL_ON) + BtInstanceIndexBt8, ///< Instance index of BT8 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT9 == PDL_ON) + BtInstanceIndexBt9, ///< Instance index of BT9 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT10 == PDL_ON) + BtInstanceIndexBt10, ///< Instance index of BT10 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT11 == PDL_ON) + BtInstanceIndexBt11, ///< Instance index of BT11 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT12 == PDL_ON) + BtInstanceIndexBt12, ///< Instance index of BT12 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT13 == PDL_ON) + BtInstanceIndexBt13, ///< Instance index of BT13 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT14 == PDL_ON) + BtInstanceIndexBt14, ///< Instance index of BT14 +#endif +#if (PDL_PERIPHERAL_ENABLE_BT15 == PDL_ON) + BtInstanceIndexBt15, ///< Instance index of BT15 +#endif + BtInstanceIndexMax ///< Maximum instance index +} en_bt_instance_index_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define BT IO mode + ******************************************************************************/ +typedef enum en_bt_io_mode +{ + BtIoMode0 = 0u, ///< BT IO mode 0 + BtIoMode1 = 1u, ///< BT IO mode 1 + BtIoMode2 = 2u, ///< BT IO mode 2 + BtIoMode3 = 3u, ///< BT IO mode 3 + BtIoMode4 = 4u, ///< BT IO mode 4 + BtIoMode5 = 5u, ///< BT IO mode 5 + BtIoMode6 = 6u, ///< BT IO mode 6 + BtIoMode7 = 7u, ///< BT IO mode 7 + BtIoMode8 = 8u, ///< BT IO mode 8 + +}en_bt_io_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define timer mode of BT + ******************************************************************************/ +typedef enum en_bt_timer_mode +{ + BtResetMode = 0u, ///< Reset mode + BtPwmMode = 1u, ///< PWM timer mode + BtPpgMode = 2u, ///< PPG timer mode + BtRtMode = 3u, ///< Reload timer mode + BtPwcMode = 4u, ///< PWC timer mode + +}en_bt_timer_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define clock prescaler of PWM timer + ******************************************************************************/ +typedef enum en_pwm_clock_pres +{ + PwmPresNone = 0u, ///< PWM prescaler clock: no division + PwmPres1Div4 = 1u, ///< PWM prescaler clock: 1/4 + PwmPres1Div16 = 2u, ///< PWM prescaler clock: 1/16 + PwmPres1Div128 = 3u, ///< PWM prescaler clock: 1/128 + PwmPres1Div256 = 4u, ///< PWM prescaler clock: 1/256 + PwmPres1ExtClkRising = 5u, ///< Use external clock and count at rising edge + PwmPres1ExtClkFalling = 6u, ///< Use external clock and count at falling edge + PwmPres1ExtClkBoth = 7u, ///< Use external clock and count at both edge + PwmPres1Div512 = 8u, ///< PWM prescaler clock: 1/512 + PwmPres1Div1024 = 9u, ///< PWM prescaler clock: 1/1024 + PwmPres1Div2048 = 10u, ///< PWM prescaler clock: 1/2048 + +}en_pwm_clock_pres_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define the configuration of PWM restart option + ******************************************************************************/ +typedef enum en_pwm_restart_enable +{ + PwmRestartDisable = 0u, ///< Disable PWM restart + PwmRestartEnable = 1u, ///< Enable PWM restart + +}en_pwm_restart_enable_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define the configuration of PWM output mask + ******************************************************************************/ +typedef enum en_pwm_output_mask +{ + PwmOutputNormal = 0u, ///< Output normal PWM wave + PwmOutputMask = 1u, ///< Mask PWM wave + +}en_pwm_output_mask_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define external trigger of PWM + ******************************************************************************/ +typedef enum en_pwm_ext_trig +{ + PwmExtTrigDisable = 0u, ///< Disable external trigger + PwmExtTrigRising = 1u, ///< Enable external trigger with rising edge + PwmExtTrigFalling = 2u, ///< Enable external trigger with falling edge + PwmExtTrigBoth = 3u, ///< Enable external trigger with both edge + +}en_pwm_ext_trig_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PWM initial polarity + ******************************************************************************/ +typedef enum en_pwm_output_polarity +{ + PwmPolarityLow = 0u, ///< Initial polarity: low + PwmPolarityHigh = 1u, ///< Initial polarity: high + +}en_pwm_output_polarity_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PWM timer mode + ******************************************************************************/ +typedef enum en_pwm_mode +{ + PwmContinuous = 0u, ///< Continuous mode + PwmOneshot = 1u, ///< One-shot mode + +}en_pwm_mode_t; + +/** + ****************************************************************************** + ** \brief enumeration to select the PWM interrupt + ******************************************************************************/ +typedef enum en_pwm_irq_sel +{ + PwmTrigIrq = 0u, ///< PWM trigger interrupt + PwmDutyMatchIrq = 1u, ///< PWM duty match interrupt + PwmUnderflowIrq = 2u, ///< PWM underflow interrupt + +} en_pwm_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define clock prescaler of PPG timer + ******************************************************************************/ +typedef enum en_ppg_clock_pres +{ + PpgPresNone = 0u, ///< PPG prescaler clock: no division + PpgPres1Div4 = 1u, ///< PPG prescaler clock: 1/4 + PpgPres1Div16 = 2u, ///< PPG prescaler clock: 1/16 + PpgPres1Div128 = 3u, ///< PPG prescaler clock: 1/128 + PpgPres1Div256 = 4u, ///< PPG prescaler clock: 1/256 + PpgPres1ExtClkRising = 5u, ///< Use external clock and count at rising edge + PpgPres1ExtClkFalling = 6u, ///< Use external clock and count at falling edge + PpgPres1ExtClkBoth = 7u, ///< Use external clock and count at both edge + PpgPres1Div512 = 8u, ///< PPG prescaler clock: 1/512 + PpgPres1Div1024 = 9u, ///< PPG prescaler clock: 1/1024 + PpgPres1Div2048 = 10u, ///< PPG prescaler clock: 1/2048 + +}en_ppg_clock_pres_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define the configuration of PPG restart option + ******************************************************************************/ +typedef enum en_ppg_restart_enable +{ + PpgRestartDisable = 0u, ///< Disable PPG restart + PpgRestartEnable = 1u, ///< Enable PPG restart + +}en_ppg_restart_enable_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define the configuration of PPG output mask + ******************************************************************************/ +typedef enum en_ppg_output_mask +{ + PpgOutputNormal = 0u, ///< Output normal PPG wave + PpgOutputMask = 1u, ///< Mask PPG wave + +}en_ppg_output_mask_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define external trigger of PPG + ******************************************************************************/ +typedef enum en_ppg_ext_trig +{ + PpgExtTrigDisable = 0u, ///< Disable external trigger + PpgExtTrigRising = 1u, ///< Enable external trigger with rising edge + PpgExtTrigFalling = 2u, ///< Enable external trigger with falling edge + PpgExtTrigBoth = 3u, ///< Enable external trigger with both edge + +}en_ppg_ext_trig_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PWM initial polarity + ******************************************************************************/ +typedef enum en_ppg_output_polarity +{ + PpgPolarityLow = 0u, ///< Initial polarity: low + PpgPolarityHigh = 1u, ///< Initial polarity: high + +}en_ppg_output_polarity_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PWM timer mode + ******************************************************************************/ +typedef enum en_ppg_mode +{ + PpgContinuous = 0u, ///< Continuous mode + PpgOneshot = 1u, ///< One-shot mode + +}en_ppg_mode_t; + +/** + ****************************************************************************** + ** \brief enumeration to select the PPG interrupt + ******************************************************************************/ +typedef enum en_ppg_irq_sel +{ + PpgTrigIrq = 0u, ///< PPG trigger interrupt + PpgUnderflowIrq = 1u, ///< PPG underflow interrupt + +} en_ppg_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define clock prescaler of Reload timer + ******************************************************************************/ +typedef enum en_rt_clock_pres +{ + RtPresNone = 0u, ///< Reload timer prescaler clock: no division + RtPres1Div4 = 1u, ///< Reload timer prescaler clock: 1/4 + RtPres1Div16 = 2u, ///< Reload timer prescaler clock: 1/16 + RtPres1Div128 = 3u, ///< Reload timer prescaler clock: 1/128 + RtPres1Div256 = 4u, ///< Reload timer prescaler clock: 1/256 + RtPres1ExtClkRising = 5u, ///< Use external clock and count at rising edge + RtPres1ExtClkFalling = 6u, ///< Use external clock and count at falling edge + RtPres1ExtClkBoth = 7u, ///< Use external clock and count at both edge + RtPres1Div512 = 8u, ///< Reload timer prescaler clock: 1/512 + RtPres1Div1024 = 9u, ///< Reload timer prescaler clock: 1/1024 + RtPres1Div2048 = 10u, ///< Reload timer prescaler clock: 1/2048 + +}en_rt_clock_pres_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define external trigger of Reload timer + ******************************************************************************/ +typedef enum en_rt_ext_trigger +{ + RtExtTiggerDisable = 0u, ///< Disable external trigger + RtExtTiggerRisingEdge = 1u, ///< Enable external trigger with rising edge + RtExtTiggerFallingEdge = 2u, ///< Enable external trigger with falling edge +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + RtExtTiggerBothEdge = 3u, ///< Enable external trigger with both edge + RtExtTiggerLowLevel = 4u, ///< Enable external trigger with low level + RtExtTiggerHighLevel = 5u, ///< Enable external trigger with high level +#endif +}en_rt_ext_trigger_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define Reload timer output initial polarity + ******************************************************************************/ +typedef enum en_rt_output_polarity +{ + RtPolarityLow = 0u, ///< Initial polarity: low + RtPolarityHigh = 1u, ///< Initial polarity: high + +}en_rt_output_polarity_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define Reload timer mode + ******************************************************************************/ +typedef enum en_rt_mode +{ + RtReload = 0u, ///< Reload mode + RtOneshot = 1u, ///< One-shot mode + +}en_rt_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define Reload timer size + ******************************************************************************/ +typedef enum en_rt_timer_size +{ + RtSize16Bit = 0u, ///< 16-bit mode + RtSize32Bit = 1u, ///< 32-bit mode + +}en_rt_timer_size_t; + +/** + ****************************************************************************** + ** \brief enumeration to select the Reload timer interrupt + ******************************************************************************/ +typedef enum en_rt_irq_sel +{ + RtTrigIrq = 0u, ///< Reload Timer trigger interrupt + RtUnderflowIrq = 1u, ///< Reload Timer underflow interrupt + +} en_rt_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define clock prescaler of PWC timer + ******************************************************************************/ +typedef enum en_pwc_clock_pres +{ + PwcPresNone = 0u, ///< PWC timer prescaler clock: no division + PwcPres1Div4 = 1u, ///< PWC timer prescaler clock: 1/4 + PwcPres1Div16 = 2u, ///< PWC timer prescaler clock: 1/16 + PwcPres1Div128 = 3u, ///< PWC timer prescaler clock: 1/128 + PwcPres1Div256 = 4u, ///< PWC timer prescaler clock: 1/256 + PwcPres1Div512 = 8u, ///< PWC timer prescaler clock: 1/512 + PwcPres1Div1024 = 9u, ///< PWC timer prescaler clock: 1/1024 + PwcPres1Div2048 = 10u, ///< PWC timer prescaler clock: 1/2048 + +}en_pwc_clock_pres_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define measure mode of PWC timer + ******************************************************************************/ +typedef enum en_pwc_measure_edge +{ + PwcMeasureRisingToFalling = 0u, ///< Measure between rising edge with falling edge + PwcMeasureRisingToRising = 1u, ///< Measure between rising edge with rising edge + PwcMeasureFallingToFalling = 2u, ///< Measure between falling edge with falling edge + PwcMeasureEitherToEither = 3u, ///< Measure between either edge with either edge + PwcMeasureFallingToRising = 4u, ///< Measure between falling edge with falling edge + +}en_pwc_measure_edge_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PWC timer mode + ******************************************************************************/ +typedef enum en_pwc_mode +{ + PwcContinuous = 0u, ///< Continuous mode + PwcOneshot = 1u, ///< One-shot mode + +}en_pwc_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define Reload timer size + ******************************************************************************/ +typedef enum en_pwc_timer_size +{ + PwcSize16Bit = 0u, ///< 16-bit mode + PwcSize32Bit = 1u, ///< 32-bit mode + +}en_pwc_timer_size_t; + +/** + ****************************************************************************** + ** \brief structure to select the PWC timer interrupt + ******************************************************************************/ +typedef enum en_pwc_irq_sel +{ + PwcMeasureCompleteIrq = 0u, ///< PWC measure completion IRQ + PwcMeasureOverflowIrq = 1u, ///< PWC measure overflow IRQ + +} en_pwc_irq_sel_t; + +/** \}GroupBT_Types */ + +/** +* \addtogroup GroupBT_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief structure to enable the PPG interrupts + ******************************************************************************/ +typedef struct stc_ppg_irq_en +{ + boolean_t bPpgTrigIrq; ///< PPG trigger interrupt selection + boolean_t bPpgUnderflowIrq; ///< PPG underflow interrupt selection + +} stc_ppg_irq_en_t; + +/** + ****************************************************************************** + ** \brief structure to enable the PWM interrupts + ******************************************************************************/ +typedef struct stc_pwm_irq_en +{ + boolean_t bPwmTrigIrq; ///< Trigger interrupt selection + boolean_t bPwmDutyMatchIrq; ///< Duty match interrupt selection + boolean_t bPwmUnderflowIrq; ///< Underflow interrupt selection + +} stc_pwm_irq_en_t; + +/** + ****************************************************************************** + ** \brief structure to set the PWM interrupt callback function + ******************************************************************************/ +typedef struct stc_pwm_int_cb +{ + func_ptr_t pfnPwmTrigIrqCb; ///< Pointer to trigger interrupt callback function + func_ptr_t pfnPwmDutyMatchIrqCb; ///< Pointer to duty match interrupt callback function + func_ptr_t pfnPwmUnderflowIrqCb; ///< Pointer to underflow interrupt callback function + +}stc_pwm_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Structure of PWM configuration + ******************************************************************************/ +typedef struct stc_bt_pwm_config +{ + en_pwm_clock_pres_t enPres; ///< Clock prescaler + en_pwm_restart_enable_t enRestartEn; ///< Restart enable setting + en_pwm_output_mask_t enOutputMask; ///< PWM output mask setting + en_pwm_ext_trig_t enExtTrig; ///< PWM external trigger setting + en_pwm_output_polarity_t enOutputPolarity; ///< PWM output polarity setting + en_pwm_mode_t enMode; ///< Continuous mode or one-shot mode +#if defined(PDL_INTERRUPT_BT_ACTIVE) + stc_pwm_irq_en_t* pstcPwmIrqEn; ///< Pointer to interrupt request enable setting structure of Base Timer with PWM mode + stc_pwm_irq_cb_t* pstcPwmIrqCb; ///< Pointer to interrupt request callback functions structure of Base Timer with PWM mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif + +}stc_bt_pwm_config_t; + +/** + ****************************************************************************** + ** \brief structure to set the PPG interrupt callback function + ******************************************************************************/ +typedef struct stc_ppg_int_cb +{ + func_ptr_t pfnPpgTrigIrqCb; ///< Pointer to PPG trigger interrupt callback function + func_ptr_t pfnPpgUnderflowIrqCb; ///< Pointer to PPG underflow interrupt callback function + +}stc_ppg_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Structure of PPG configuration + ******************************************************************************/ +typedef struct stc_bt_ppg_config +{ + en_ppg_clock_pres_t enPres; ///< Clock prescaler + en_ppg_restart_enable_t enRestartEn; ///< Restart enable setting + en_ppg_output_mask_t enOutputMask; ///< PPG output mask setting + en_ppg_ext_trig_t enExtTrig; ///< PPG external trigger setting + en_ppg_output_polarity_t enOutputPolarity; ///< PPG output polarity setting + en_ppg_mode_t enMode; ///< Continuous mode or one-shot mode +#if defined(PDL_INTERRUPT_BT_ACTIVE) + stc_ppg_irq_en_t* pstcPpgIrqEn; ///< Pointer to interrupt request enable setting structure of Base Timer with PPG mode + stc_ppg_irq_cb_t* pstcPpgIrqCb; ///< Pointer to interrupt request callback functions structure of Base Timer with PPG mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_bt_ppg_config_t; + +/** + ****************************************************************************** + ** \brief structure to enable the Reload timer interrupts + ******************************************************************************/ +typedef struct stc_rt_irq_en +{ + boolean_t bRtTrigIrq; ///< Trigger interrupt selection + boolean_t bRtUnderflowIrq; ///< Underflow interrupt selection + +} stc_rt_irq_en_t; + +/** + ****************************************************************************** + ** \brief structure to set the Reload timer interrupt callback function + ******************************************************************************/ +typedef struct stc_rt_irq_cb +{ + func_ptr_t pfnRtTrigIrqCb; ///< Pointer to trigger interrupt callback function + func_ptr_t pfnRtUnderflowIrqCb; ///< Pointer to underflow interrupt callback function + +}stc_rt_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Structure of Reload timer configuration + ******************************************************************************/ +typedef struct stc_bt_rt_config +{ + en_rt_clock_pres_t enPres; ///< Clock prescaler + en_rt_timer_size_t enSize; ///< 16-bit or 32-bit + en_rt_ext_trigger_t enExtTrig; ///< External trigger setting + en_rt_output_polarity_t enOutputPolarity; ///< Output polarity setting + en_rt_mode_t enMode; ///< Reload mode or one-shot mode +#if defined(PDL_INTERRUPT_BT_ACTIVE) + stc_rt_irq_en_t* pstcRtIrqEn; ///< Pointer to interrupt request enable setting structure of Base Timer with Reload TImer mode + stc_rt_irq_cb_t* pstcRtIrqCb; ///< Pointer to interrupt request callback functions structure of Base Timer with Reload TImer mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_bt_rt_config_t; + +/** + ****************************************************************************** + ** \brief structure to enable the PWC timer interrupts + ******************************************************************************/ +typedef struct stc_pwc_irq_en +{ + boolean_t bPwcMeasureCompleteIrq; ///< PWC measure completion IRQ + boolean_t bPwcMeasureOverflowIrq; ///< PWC measure overflow IRQ + +}stc_pwc_irq_en_t; + + +/** + ****************************************************************************** + ** \brief structure to set the PWC timer interrupt callback function + ******************************************************************************/ +typedef struct stc_pwc_int_cb +{ + func_ptr_t pfnPwcMeasureCompleteIrqCb; ///< Poiter to PWC measure completion callback function + func_ptr_t pfnPwcMeasureOverflowIrqCb; ///< Poiter to PWC measure overflow callback function +}stc_pwc_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Structure of PWC timer configuration + ******************************************************************************/ +typedef struct stc_bt_pwc_config +{ + en_pwc_clock_pres_t enPres; ///< Clock prescaler + en_pwc_timer_size_t enSize; ///< 16-bit or 32-bit + en_pwc_measure_edge_t enMeasureEdge; ///< Measure mode setting + en_pwc_mode_t enMode; ///< Continuous mode or one-shot mode +#if defined(PDL_INTERRUPT_BT_ACTIVE) + stc_pwc_irq_en_t* pstcPwcIrqEn; ///< Pointer to interrupt request enable setting structure of Base Timer with PWC mode + stc_pwc_irq_cb_t* pstcPwcIrqCb; ///< Pointer to interrupt request callback functions structure of Base Timer with PWC mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_bt_pwc_config_t; + +/** + ****************************************************************************** + ** \brief BT internal data + ******************************************************************************/ +typedef struct stc_bt_intern_data +{ + func_ptr_t pfnBit0IrqCb; ///< Pointer to callback function the interrupt reflected by bit0 of STC + func_ptr_t pfnBit1IrqCb; ///< Pointer to callback function the interrupt reflected by bit1 of STC + func_ptr_t pfnBit2IrqCb; ///< Pointer to callback function the interrupt reflected by bit2 of STC +} stc_bt_intern_data_t ; + +/** + ****************************************************************************** + ** \brief BT instance data + ******************************************************************************/ +typedef struct stc_bt_instance_data +{ + volatile stc_btn_t* pstcInstance; ///< pointer to registers of an instance + stc_bt_intern_data_t stcInternData; ///< module internal data of instance +} stc_bt_instance_data_t; + +/** \} GroupBT_DataStructures */ + +/** +* \addtogroup GroupBT_GlobalVariables +* \{ +*/ +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/// Look-up table for all enabled BT instances and their internal data +extern stc_bt_instance_data_t m_astcBtInstanceDataLut[BT_INSTANCE_COUNT]; +/** \} GroupBT_GlobalVariables */ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \addtogroup GroupBT_Functions +* \{ +*/ + +/* 1. Configure BT IO mode */ +en_result_t Bt_ConfigIOMode(volatile stc_btn_t* pstcBt, en_bt_io_mode_t enIoMode); + +#if (PDL_PERIPHERAL_ENABLE_BT_PWM_MODE == PDL_ON) +/* 2. Timer configuration */ +/* 2.1 PWM timer */ +/* Init */ +en_result_t Bt_Pwm_Init(volatile stc_btn_t* pstcBt, const stc_bt_pwm_config_t* pstcPwmConfig); +en_result_t Bt_Pwm_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic); +/* Func/Irq Enable/Disable */ +en_result_t Bt_Pwm_EnableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Pwm_DisableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Pwm_EnableSwTrig(volatile stc_btn_t* pstcBt); +#if defined(PDL_INTERRUPT_BT_ACTIVE) +en_result_t Bt_Pwm_EnableIrq(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel); +en_result_t Bt_Pwm_DisableIrq(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel); +#endif +/* Interrupt flag read/clear */ +en_irq_flag_t Bt_Pwm_GetIrqFlag(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel); +en_result_t Bt_Pwm_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_pwm_irq_sel_t enIrqSel); +/* Write/read count */ +en_result_t Bt_Pwm_WriteCycleVal(volatile stc_btn_t* pstcBt, uint16_t u16Cycle); +en_result_t Bt_Pwm_WriteDutyVal(volatile stc_btn_t* pstcBt, uint16_t u16Duty); +uint16_t Bt_Pwm_ReadCurCnt(volatile stc_btn_t* pstcBt); +#endif + +#if (PDL_PERIPHERAL_ENABLE_BT_PPG_MODE == PDL_ON) +/* 2.2 PPG timer */ +/* Init */ +en_result_t Bt_Ppg_Init(volatile stc_btn_t* pstcBt, const stc_bt_ppg_config_t* pstcPpgConfig); +en_result_t Bt_Ppg_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic); +/* Func/Int Enable/Disable */ +en_result_t Bt_Ppg_EnableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Ppg_DisableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Ppg_EnableSwTrig(volatile stc_btn_t* pstcBt); +#if defined(PDL_INTERRUPT_BT_ACTIVE) +en_result_t Bt_Ppg_EnableIrq(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel); +en_result_t Bt_Ppg_DisableIrq(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel); +#endif +/* Interrupt flag read/clear */ +en_irq_flag_t Bt_Ppg_GetIrqFlag(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel); +en_result_t Bt_Ppg_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_ppg_irq_sel_t enIrqSel); +/* Write/read count */ +en_result_t Bt_Ppg_WriteLowWidthVal(volatile stc_btn_t* pstcBt, uint16_t u16Val); +en_result_t Bt_Ppg_WriteHighWidthVal(volatile stc_btn_t* pstcBt, uint16_t u16Val); +uint16_t Bt_Ppg_ReadCurCnt(volatile stc_btn_t* pstcBt); +#endif + +#if (PDL_PERIPHERAL_ENABLE_BT_RT_MODE == PDL_ON) +/* 2.3 RT timer */ +/* Init */ +en_result_t Bt_Rt_Init(volatile stc_btn_t* pstcBt, const stc_bt_rt_config_t* pstcRtConfig); +en_result_t Bt_Rt_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic); +/* Func/Int Enable/Disable */ +en_result_t Bt_Rt_EnableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Rt_DisableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Rt_EnableSwTrig(volatile stc_btn_t* pstcBt); +#if defined(PDL_INTERRUPT_BT_ACTIVE) +en_result_t Bt_Rt_EnableIrq(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel); +en_result_t Bt_Rt_DisableIrq(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel); +#endif +/* Interrupt flag read/clear */ +en_irq_flag_t Bt_Rt_GetIrqFlag(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel); +en_result_t Bt_Rt_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_rt_irq_sel_t enIrqSel); +/* Write/read count */ +en_result_t Bt_Rt_WriteCycleVal(volatile stc_btn_t* pstcBt, uint16_t u16Val); +uint16_t Bt_Rt_ReadCurCnt(volatile stc_btn_t* pstcBt); +#endif + +#if (PDL_PERIPHERAL_ENABLE_BT_PWC_MODE == PDL_ON) +/* 2.4 PWC timer */ +/* Init */ +en_result_t Bt_Pwc_Init(volatile stc_btn_t* pstcBt, const stc_bt_pwc_config_t* pstcPwcConfig); +en_result_t Bt_Pwc_DeInit(volatile stc_btn_t* pstcBt, boolean_t bTouchNvic); +/* Func/Int Enable/Disable */ +en_result_t Bt_Pwc_EnableCount(volatile stc_btn_t* pstcBt); +en_result_t Bt_Pwc_DisableCount(volatile stc_btn_t* pstcBt); +#if defined(PDL_INTERRUPT_BT_ACTIVE) +en_result_t Bt_Pwc_EnableIrq(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel); +en_result_t Bt_Pwc_DisableIrq(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel); +#endif +/* Interrupt flag read/clear */ +en_irq_flag_t Bt_Pwc_GetIrqFlag(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel); +en_result_t Bt_Pwc_ClrIrqFlag(volatile stc_btn_t* pstcBt, en_pwc_irq_sel_t enIrqSel); +en_stat_flag_t Bt_Pwc_GetErrorFlag(volatile stc_btn_t* pstcBt); +/* Write/read count */ +uint16_t Bt_Pwc_Get16BitMeasureData(volatile stc_btn_t* pstcBt); +uint32_t Bt_Pwc_Get32BitMeasureData(volatile stc_btn_t* pstcBt); +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/* 4. Start/stop BT simultaneously */ +void Bt_SetSimultaneousStart(uint16_t u16Value); +#endif + +/* 5. IRQ handler */ +void Bt_IrqHandler( volatile stc_btn_t* pstcBt, + stc_bt_intern_data_t* pstcBtInternData) ; + +/** \} GroupBT_Functions */ + +#ifdef __cplusplus +} +#endif + +/* \} GroupBT Base Timer (BT) */ + +#endif // #if (defined(PDL_PERIPHERAL_BT_ACTIVE)) + +#endif // #if __BT_H__ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.c new file mode 100644 index 0000000000..6f6faae785 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.c @@ -0,0 +1,1396 @@ +/****************************************************************************** +* \file can.c +* +* \version 1.30 +* +* \brief Controller Area Network (CAN) driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "can/can.h" + +#if (defined(PDL_PERIPHERAL_CAN_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/// Macro to return the number of enabled CAN instances +#define CAN_INSTANCE_COUNT (uint32_t)(sizeof(m_astcCanInstanceDataLut) / sizeof(m_astcCanInstanceDataLut[0])) + +/// Status interrupt detected +#define CAN_STATUS_INTERRUPT (1 << 15) + +/** LEC (Last Error Code) special value indicating that no changes happened + after the CPU has written this special value to LEC */ +#define CAN_NO_LEC_CHANGE 7 + +#define CAN_MSG_DIR_RX 0 ///< WRRD bit indicating read direction +#define CAN_MSG_DIR_TX 1 ///< WRRD bit indicating write direction +#define CAN_MSG_ID_EXTENDED 1 ///< Extended msg id is used + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled CAN instances and their internal data +stc_can_instance_data_t m_astcCanInstanceDataLut[] = +{ + #if (PDL_PERIPHERAL_ENABLE_CAN0 == PDL_ON) + { + &CAN0, // pstcInstance + { + {{0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}}, + {0}, + 0 + } // stcInternData (not initialized yet) + }, + #endif + #if (PDL_PERIPHERAL_ENABLE_CAN1 == PDL_ON) + { + &CAN1, // pstcInstance + { + {{0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}}, + {0}, + 0 + } // stcInternData (not initialized yet) + }, + #endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain CAN instance. + ** + ** \param pstcCan Pointer to CAN instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_can_intern_data_t* CanGetInternDataPtr(volatile stc_cann_t* pstcCan) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < CAN_INSTANCE_COUNT; u32Instance++) + { + if (pstcCan == m_astcCanInstanceDataLut[u32Instance].pstcInstance) + { + return &m_astcCanInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on CAN instance + ** + ** \param pstcCan Pointer to CAN instance + ** + ******************************************************************************/ +static void Can_InitInterrupt(volatile stc_cann_t* pstcCan) +{ +#if (PDL_INTERRUPT_ENABLE_CAN0 == PDL_ON) + if (pstcCan == (stc_cann_t*)(&CAN0)) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(CAN0_IRQn); + NVIC_EnableIRQ(CAN0_IRQn); + NVIC_SetPriority(CAN0_IRQn, PDL_IRQ_LEVEL_CAN0); + #elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(ETHER0_CAN0_IRQn); + NVIC_EnableIRQ(ETHER0_CAN0_IRQn); + NVIC_SetPriority(ETHER0_CAN0_IRQn, PDL_IRQ_LEVEL_CAN0_ETHER0); + #endif + } +#endif +#if (PDL_INTERRUPT_ENABLE_CAN1 == PDL_ON) + if (pstcCan == (stc_cann_t*)(&CAN1)) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_MCU_TYPE == PDL_FM4_TYPE1 || PDL_MCU_TYPE == PDL_FM4_TYPE6) + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_EnableIRQ(CAN1_IRQn); + NVIC_SetPriority(CAN1_IRQn, PDL_IRQ_LEVEL_CAN1); + #else + NVIC_ClearPendingIRQ(CAN1_CANFD0_IRQn); + NVIC_EnableIRQ(CAN1_CANFD0_IRQn); + NVIC_SetPriority(CAN1_CANFD0_IRQn, PDL_IRQ_LEVEL_CAN1_CANFD0); + #endif + #elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(ETHER1_CAN1_IRQn); + NVIC_EnableIRQ(ETHER1_CAN1_IRQn); + NVIC_SetPriority(ETHER1_CAN1_IRQn, PDL_IRQ_LEVEL_CAN1_ETHER1); + #endif + } +#endif +} + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on CAN instance + ** + ** \param pstcCan Pointer to CAN instance + ** + ******************************************************************************/ +static void Can_DeInitInterrupt(volatile stc_cann_t* pstcCan) +{ +#if (PDL_INTERRUPT_ENABLE_CAN0 == PDL_ON) + if ((stc_cann_t*)(&CAN0) == pstcCan) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(CAN0_IRQn); + NVIC_DisableIRQ(CAN0_IRQn); + NVIC_SetPriority(CAN0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(ETHER0_CAN0_IRQn); + NVIC_DisableIRQ(ETHER0_CAN0_IRQn); + NVIC_SetPriority(ETHER0_CAN0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + } +#endif +#if (PDL_INTERRUPT_ENABLE_CAN1 == PDL_ON) + if ((stc_cann_t*)(&CAN1) == pstcCan) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_MCU_TYPE == PDL_FM4_TYPE1 || PDL_MCU_TYPE == PDL_FM4_TYPE6) + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_DisableIRQ(CAN1_IRQn); + NVIC_SetPriority(CAN1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #else + NVIC_ClearPendingIRQ(CAN1_CANFD0_IRQn); + NVIC_DisableIRQ(CAN1_CANFD0_IRQn); + NVIC_SetPriority(CAN1_CANFD0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(ETHER1_CAN1_IRQn); + NVIC_DisableIRQ(ETHER1_CAN1_IRQn); + NVIC_SetPriority(ETHER1_CAN1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + } +#endif +} + + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CAN (Status/Error/Rx/Tx) interrupt ISR + ** + ** Check for any pending interrupt source and process until no more INTs are + ** active. + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] pstcCanInternData Pointer to internal data. + ** + ** Description of flow: + ** - write new data any time into user buffer + ** - check bNew, if TRUE (user buffer not released yet) + ** > set bOverflow + ** - set bNew + ** - call callback function + ** - the MSGLST flag of the HW message buffer + ** should be OR-mirrored into bOverflow, too + *****************************************************************************/ +void CanIrqHandler( volatile stc_cann_t* pstcCan, + stc_can_intern_data_t* pstcCanInternData + ) +{ + uint16_t u16MessageBufferNumber ; + boolean_t bDone ; + stc_can_statr_field_t unCanStatusRegister ; + stc_can_if2cmsk_field_t unCanIf2Cmsk; + + bDone = FALSE ; + + while( FALSE == bDone) + { + u16MessageBufferNumber = pstcCan->INTR ; + + switch ( u16MessageBufferNumber ) + { + // nothing more to do + case 0u: + bDone = TRUE ; + break ; + + // Check for status interrupt + case CAN_STATUS_INTERRUPT: + // Get status register, clear of status Irq is done automatically by readout + unCanStatusRegister = pstcCan->STATR_f; + + // Check for error if the error callback function is defined. + if (pstcCanInternData->stcCanNotificationCb.pfnCanErrorInterruptFunction != NULL) + { + // Check if bus off error was set (transmit error counter > 255) + if (unCanStatusRegister.BOFF != 0) + { + // Bus off + pstcCanInternData->stcCanNotificationCb.pfnCanErrorInterruptFunction(CanBusOff); + } + + // Check if error warning level is reached (receive and/or transmit error counter >= 96). + if (unCanStatusRegister.EWARN != 0) + { + // Warning level reached. + pstcCanInternData->stcCanNotificationCb.pfnCanErrorInterruptFunction(CanWarning); + } + } + + // Check for status if the status change callback function is defined. + if (pstcCanInternData->stcCanNotificationCb.pfnCanStatusInterruptFunction != NULL) + { + // LEC different to CAN_NO_LEC_CHANGE, report last error. + if (unCanStatusRegister.LEC != CAN_NO_LEC_CHANGE) + { + pstcCanInternData->stcCanNotificationCb.pfnCanStatusInterruptFunction((en_can_status_t)(unCanStatusRegister.LEC)); + + // Now reset LEC to special value CAN_NO_LEC_CHANGE + pstcCan->STATR_f.LEC = CAN_NO_LEC_CHANGE; + } + } + break ; + + // Default path is message buffer handling + default: + // Write command mask register to perform a selective read based on the bits set + unCanIf2Cmsk.WR_RD = CAN_MSG_DIR_RX; // Set direction to rx + unCanIf2Cmsk.MASK = 1u; // Transfer Identifier Mask + MDir + MXtd to Message Object + unCanIf2Cmsk.ARB = 1u; // Transfer Identifier + Dir + Xtd + MsgVal to Message Object + unCanIf2Cmsk.CONTROL = 1u; // Transfer Control Bits to Message Object + unCanIf2Cmsk.CIP = 1u; // Clear Interrupt Pending Bit + unCanIf2Cmsk.NEWDAT = 1u; // Set TXRQST/NEWDAT bit + unCanIf2Cmsk.DATAA = 1u; // Transfer Data Bytes 0-3 to Mesage Object + unCanIf2Cmsk.DATAB = 1u; // Transfer Data Bytes 4-7 to Mesage Object + pstcCan->IF2CMSK_f = unCanIf2Cmsk; + + // Write message buffer number to request reading + // the message buffer into the interface registers + // We can write full 16bit here because BUSY bit is not used in this mode + pstcCan->IF2CREQ = u16MessageBufferNumber ; + + // Check if message object is configured for reception or transmission + if (CAN_MSG_DIR_RX == pstcCan->IF2ARB_f.DIR) + { + // CAN message received, check if there is a callback function + // for this message buffer registered + if (NULL != pstcCanInternData->stcCanInterruptHandling[u16MessageBufferNumber - 1].pstcMsgBuffer) + { + stc_can_msg_t* pstcMsgBuffer = pstcCanInternData->stcCanInterruptHandling[u16MessageBufferNumber - 1].pstcMsgBuffer; + uint32_t* pu32Data = (uint32_t*)&pstcMsgBuffer->stcData.au8Data[0] ; + + // Check if 11- or 29-bit identifier was used for message. + if ( CAN_MSG_ID_EXTENDED != pstcCan->IF2ARB_f.XTD ) + { + // 11-bit identifier was used. + pstcMsgBuffer->stcIdentifier.bExtended = FALSE; + pstcMsgBuffer->stcIdentifier.u32Identifier = (pstcCan->IF2ARB_f.ID >> 18); + } + else + { + // 29-bit identifier was used. + pstcMsgBuffer->stcIdentifier.bExtended = TRUE; + pstcMsgBuffer->stcIdentifier.u32Identifier = pstcCan->IF2ARB_f.ID; + } + + // Get data bytes + pu32Data[0] = pstcCan->IF2DTA_L; + + pu32Data[1] = pstcCan->IF2DTB_L; + + + // Set data length of received data bytes. + pstcMsgBuffer->stcData.u8DataLengthCode = pstcCan->IF2MCTR_f.DLC; + + // Check if message lost flag is set in receive message buffer. + if ( 1u == pstcCan->IF2MCTR_f.MSGLST ) + { + pstcMsgBuffer->bOverflow = TRUE ; + + // Reset message lost flag. + pstcCan->IF2MCTR_f.MSGLST = 0 ; + + // Write command mask register to perform a write to CAN control register. + // Pls. note that INTPND and NEWDAT are left unchanged if written with '0' + unCanIf2Cmsk = pstcCan->IF2CMSK_f; + unCanIf2Cmsk.WR_RD = CAN_MSG_DIR_RX; // Set direction to tx + unCanIf2Cmsk.CONTROL = 1; // Transfer control bits + pstcCan->IF2CMSK_f = unCanIf2Cmsk; + + // Set message buffer number to update message buffer. + // We can write full 16bit here because BUSY bit is not used in this mode + pstcCan->IF2CREQ = u16MessageBufferNumber; + } + + // Check if data new flag is already set. + if ( TRUE == pstcMsgBuffer->bNew ) + { + // New data flag was already set, that means that + // at least one message is lost, so overflow flag + // must be set. + pstcMsgBuffer->bOverflow = TRUE ; + } + else + { + // Set new data flag. + pstcMsgBuffer->bNew = TRUE ; + } + + // Call callback function if it was set previously. + if (NULL != pstcCanInternData->stcCanInterruptHandling[u16MessageBufferNumber - 1].pfnCanRxInterruptFunction) + { + pstcCanInternData->stcCanInterruptHandling[u16MessageBufferNumber - 1].pfnCanRxInterruptFunction((uint8_t)u16MessageBufferNumber, pstcMsgBuffer); + } + } + } + else // if (pstcCan->u32IF2ARB.DIR == CAN_MSG_DIR_RX) + { + // CAN message succesfully transmitted. + // Call callback function if it was set previously. + if (NULL != pstcCanInternData->stcCanInterruptHandling[u16MessageBufferNumber - 1].pfnCanTxInterruptFunction) + { + pstcCanInternData->stcCanInterruptHandling[u16MessageBufferNumber - 1].pfnCanTxInterruptFunction((uint8_t)u16MessageBufferNumber); + } + } + break ; + } // switch ( u16MessageBufferNumber ) + } // while ( !bDone ) +} // CanIrqHandler + +/** + ***************************************************************************** + ** \brief Initializes the CAN module. + ** + ** This function initializes one specific CAN module with the parameters + ** provided in the given config structure. + ** After initialization the CAN module has Error, Status and Module-Interrupt + ** enabled and is ready to use. + ** + ** Can_Init() has to be called with the parameter pstcConfig of type + ** stc_can_config_t the basic CAN settings automatic retransmission, the CAN + ** baudrate, and the error and status change callback function can be set. + ** + ** All values in pstcConfig have to be in valid range (see can.h for allowed + ** ranges of dedicated parameters). The error and status change callback + ** functions can be NULL. In this case no information of error or status + ** changes will be reported to the API. + ** + ** To reset and disable the CAN module the function Can_DeInit() has to be used. + ** + ** The resulting CAN presecaler value is checked, if it is within CAN_MAX_CLK + ** (normally 16 MHz). + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] pstcConfig CAN configuration parameters. + ** + ** \retval Ok CAN module has been successfully initialized. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcConfig == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDL_PERIPHERAL_ENABLE_CAN)) + ** - pstcConfig->stcBitrate.u8TimeSegment1 out of range + ** - pstcConfig->stcBitrate.u8TimeSegment2 out of range + ** - pstcConfig->stcBitrate.u8SyncJumpWidth out of range + ** - pstcConfig->stcBitrate.u16Prescaler out of range + ** - pstcConfig->stcBitrate.enCanPrescaler wrong enumerator + ** - pstcConfig->stcBitrate.enCanPrescaler CAN_MAX_CLK violated + *****************************************************************************/ +en_result_t Can_Init( volatile stc_cann_t* pstcCan, const stc_can_config_t* pstcConfig ) +{ + stc_can_intern_data_t* pstcCanInternData; + stc_can_btr_field_t unBTR; + stc_can_if1cmsk_field_t unIF1CMSK; + stc_can_ctrlr_field_t unCTRLR; + uint8_t u8MessageNumber; + uint8_t u8HclkDiv; + uint8_t u8HclkMul; + + PDL_ZERO_STRUCT(unBTR); + PDL_ZERO_STRUCT(unIF1CMSK); + PDL_ZERO_STRUCT(unCTRLR); + + // Check for NULL pointers + if ( (NULL == pstcCan) || + (NULL == pstcConfig) + ) + { + return ErrorInvalidParameter; + } + + // Check range of input parameters..... + if ( ((pstcConfig->stcBitrate.u8TimeSegment1 < CAN_BITRATE_TSEG1_MIN) || (pstcConfig->stcBitrate.u8TimeSegment1 > CAN_BITRATE_TSEG1_MAX)) || + ((pstcConfig->stcBitrate.u8TimeSegment2 < CAN_BITRATE_TSEG2_MIN) || (pstcConfig->stcBitrate.u8TimeSegment2 > CAN_BITRATE_TSEG2_MAX)) || + ((pstcConfig->stcBitrate.u8SyncJumpWidth < CAN_BITRATE_SYNC_JUMP_WIDTH_MIN) || (pstcConfig->stcBitrate.u8SyncJumpWidth > CAN_BITRATE_SYNC_JUMP_WIDTH_MAX)) || + ((pstcConfig->stcBitrate.u16Prescaler < CAN_BITRATE_PRESCALER_MIN) || (pstcConfig->stcBitrate.u16Prescaler > CAN_BITRATE_PRESCALER_MAX)) + ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if (NULL == pstcCanInternData) + { + return ErrorInvalidParameter; + } + + if (TRUE == (pstcConfig->bTouchPrescaler)) + { + // CAN dedicated clock prescaler + SystemCoreClockUpdate(); + switch(pstcConfig->stcBitrate.enCanPrescaler) + { + case CanPreDiv11: + FM_CANPRES->CANPRE = 0x00u; + u8HclkDiv = 1u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv12: + FM_CANPRES->CANPRE = 0x01u; + u8HclkDiv = 2u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv14: + FM_CANPRES->CANPRE = 0x02u; + u8HclkDiv = 4u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv18: + FM_CANPRES->CANPRE = 0x04u; + u8HclkDiv = 8u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv23: + FM_CANPRES->CANPRE = 0x08u; + u8HclkMul = 2u; + u8HclkDiv = 3u; + if (((SystemCoreClock * u8HclkMul) / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv13: + FM_CANPRES->CANPRE = 0x09u; + u8HclkDiv = 3u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv16: + FM_CANPRES->CANPRE = 0x0Au; + u8HclkDiv = 6u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv112: + FM_CANPRES->CANPRE = 0x0Bu; + u8HclkDiv = 12u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv15: + FM_CANPRES->CANPRE = 0x0Cu; + u8HclkDiv = 5u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + case CanPreDiv110: + FM_CANPRES->CANPRE = 0x0Eu; + u8HclkDiv = 10u; + if ((SystemCoreClock / u8HclkDiv) > CAN_MAX_CLK) + { + return ErrorInvalidParameter; + } + break; + default: + return ErrorInvalidParameter; + } + } + + // Enable access to init and bit timing register. + pstcCan->CTRLR_f.INIT = 1u; + pstcCan->CTRLR_f.CCE = 1u; + + unBTR.BRP = pstcConfig->stcBitrate.u16Prescaler - 1u ; + unBTR.SJW = pstcConfig->stcBitrate.u8SyncJumpWidth - 1u ; + unBTR.TSEG1 = pstcConfig->stcBitrate.u8TimeSegment1 - 1u ; + unBTR.TSEG2 = pstcConfig->stcBitrate.u8TimeSegment2 - 1u ; + pstcCan->BTR_f = unBTR ; // Write to Hardware + + pstcCan->BRPER = ((pstcConfig->stcBitrate.u16Prescaler - 1u) >> 6u); + + // Now disable access to bit timing register + pstcCan->CTRLR_f.CCE = 0u; + + // Reset status register. + pstcCan->STATR = 0x0000u; + + // Reset message valid bit of each message to invalid. + pstcCan->IF1ARB = 0u ; + + // Reset message control register. + pstcCan->IF1MCTR = 0x0000u; + + // Write command mask register to for update arbitration and control part of message object. + unIF1CMSK.WR_RD = CAN_MSG_DIR_TX; + unIF1CMSK.ARB = 1u; + unIF1CMSK.CONTROL = 1u; + pstcCan->IF1CMSK_f = unIF1CMSK; + + // Set each message buffer number to update message buffer with reset message valid bit. + for (u8MessageNumber = 1u; u8MessageNumber <= CAN_MESSAGE_BUFFER_COUNT; u8MessageNumber++) + { + pstcCan->IF1CREQ = u8MessageNumber ; + } + + // Set notification callback functions + pstcCanInternData->stcCanNotificationCb.pfnCanStatusInterruptFunction = pstcConfig->pfnStatusCallback; + pstcCanInternData->stcCanNotificationCb.pfnCanErrorInterruptFunction = pstcConfig->pfnErrorCallback; + + // Enable interrupts + unCTRLR.EIE = 1u; // Error interrupt enable + unCTRLR.SIE = 1u; // Status change interrupt enable + unCTRLR.IE = 1u; // Module interrupt enable + + // Set automatic retransmission field. + if (TRUE == pstcConfig->bDisableAutomaticRetransmission) + { + unCTRLR.DAR = 1u; // Disable automatic retransmission + } + + pstcCan->CTRLR_f = unCTRLR; + + Can_InitInterrupt(pstcCan); + + // At last leave init phase ... + pstcCan->CTRLR_f.INIT = 0u ; + + return Ok; +} // Can_Init + +/** + ***************************************************************************** + ** \brief Deinitializes the CAN module. + ** Any pending transmission or receiption will be aborted and all CAN related + ** registers are reset to their default values. + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** + ** \retval Ok CAN module has been successfully deinitialized + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit + ** (PDL_PERIPHERAL_ENABLE_CAN)) + *****************************************************************************/ +en_result_t Can_DeInit( volatile stc_cann_t* pstcCan ) +{ + stc_can_intern_data_t* pstcCanInternData; // Pointer to internal data + uint8_t u8MessageNumber; + + // Check for NULL pointer + if ( NULL == pstcCan ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if (NULL == pstcCanInternData) + { + return ErrorInvalidParameter; + } + + Can_DeInitInterrupt(pstcCan); + + // Reset CAN control register. + pstcCan->CTRLR = 0x0000u; + + pstcCan->CTRLR_f.INIT = 1u; // Enter INIT phase + pstcCan->CTRLR_f.CCE = 1u; // Enable access to bit timing register. + + // Reset CAN bit timing register (0x2301). + pstcCan->BTR_f.BRP = 1u; + pstcCan->BTR_f.SJW = 0u; + pstcCan->BTR_f.TSEG1 = 3u; + pstcCan->BTR_f.TSEG2 = 2u; + + // Reset CAN baud rate prescaler extension register. + pstcCan->BRPER = 0x00u; + + // Disable access to bit timing register. + pstcCan->CTRLR_f.CCE = 0u; + + // Reset CAN status register. + pstcCan->STATR = 0x00u; + + // Reset CAN test register. + pstcCan->TESTR = 0x00u; + + // Reset CAN IFx command mask register. + pstcCan->IF1CMSK = 0x00u; + pstcCan->IF2CMSK = 0x00u; + + // Reset CAN IFx mask register. + pstcCan->IF1MSK = UINT32_MAX ; + pstcCan->IF2MSK = UINT32_MAX ; + + // Reset CAN IFx arbitration register. + pstcCan->IF1ARB = 0x00u; + pstcCan->IF2ARB = 0x00u; + + // Reset CAN IFx message control register. + pstcCan->IF1MCTR = 0x00u; + pstcCan->IF2MCTR = 0x00u; + + // Reset CAN IFx data A and Data B register. + pstcCan->IF1DTA_L = 0x00u; + + pstcCan->IF1DTB_L = 0x00u; + + pstcCan->IF2DTA_L = 0x00u; + + pstcCan->IF2DTB_L = 0x00u; + + + // Reset CAN prescaler + FM_CANPRES->CANPRE = 0x00u; + + // Set each message buffer number to update message buffer with reset message valid bit. + for (u8MessageNumber = 0; u8MessageNumber < CAN_MESSAGE_BUFFER_COUNT; u8MessageNumber++) + { + // Reset transmit callback function. + pstcCanInternData->stcCanInterruptHandling[u8MessageNumber].pstcMsgBuffer = NULL; + pstcCanInternData->stcCanInterruptHandling[u8MessageNumber].pfnCanTxInterruptFunction = NULL; + pstcCanInternData->stcCanInterruptHandling[u8MessageNumber].pfnCanRxInterruptFunction = NULL; + } + + // Reset notification callback functions + pstcCanInternData->stcCanNotificationCb.pfnCanStatusInterruptFunction = NULL; + pstcCanInternData->stcCanNotificationCb.pfnCanErrorInterruptFunction = NULL; + + return Ok; +} // Can_DeInit + +/** + ***************************************************************************** + ** \brief Check if the given Message Buffer can be updated. + ** + ** Updating is not possible if a transmission is pending, except we are in + ** remote transmission mode. + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** + ** \retval Ok Message buffer can be updated + ** \retval ErrorOperationInProgress A transmission is pending + *****************************************************************************/ +static en_result_t CanIsMbUpdatePossible( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf + ) +{ + uint32_t u32CmpMask ; + + // No parameter checking is necessary here because this has been done + // by the caller already. + + // Check if a transmission is pending + // Get bit mask + u32CmpMask = (1u << u8MsgBuf); + + // If Remote-Frames are active ... + if( 1u == pstcCan->IF1MCTR_f.RMTEN ) + { + return Ok ; // Update of Message Buffer is safe now + } + + if (32 <= u8MsgBuf) + { + // hope this will never see the daylight + return ErrorInvalidParameter ; + } + + if ( pstcCan->TREQR & u32CmpMask ) + { + return ErrorOperationInProgress ; + } + + return Ok ; // Update of Message Buffer is safe now +} // CanIsMbUpdatePossible + +/** + ***************************************************************************** + ** \brief Configures a message buffer for transmission. + ** Setting of new values is not possible if a transmission is pending, except + ** remote transmission mode. The callback function pfnCallback can be NULL, but + ** there will be no notification of a successful transmission. This function + ** has to be called at least once before function + ** Can_UpdateAndTransmitMsgBuffer() can be used with the same message buffer + ** index. + ** + ** With the parameter stc_can_msg_id_t#pstcMsgId of type stc_can_msg_id_t + ** the API can set the identifier (11 bit or 29 bit length) of the CAN transmit + ** message. It is possible to set a callback function to get notified when a + ** transmission is successfully finished. + ** Can_SetTransmitMsgBuffer() must be called before calling + ** Can_UpdateAndTransmitMsgBuffer(). Update or setting of new values of + ** function Can_SetTransmitMsgBuffer() or Can_UpdateAndTransmitMsgBuffer() is + ** not possible if a transmission is pending or ongoing, except remote + ** transmission mode is used. + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** \param [in] pstcMsgId CAN message identifier. + ** \param [in] pfnCallback Callback function to be called after successful transmission, can be NULL. + ** + ** \retval Ok Message buffer has been successfully initialized. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDL_PERIPHERAL_ENABLE_CAN)) + ** - pstcMsgId == NULL + ** - u8MsgBuf out of range + ** \retval ErrorOperationInProgress If following condition is met: + ** - A transmission is pending (either wait or call Can_ResetMsgBuffer() ). + *****************************************************************************/ +en_result_t Can_SetTransmitMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + const stc_can_msg_id_t* pstcMsgId, + can_tx_msg_func_ptr_t pfnCallback + ) +{ + stc_can_intern_data_t* pstcCanInternData ; // Pointer to internal data + + // Check for NULL pointer + if ( (NULL == pstcCan) || + (NULL == pstcMsgId) + ) + { + return ErrorInvalidParameter; + } + + // Check for message buffer index in range + if ( u8MsgBuf >= CAN_MESSAGE_BUFFER_COUNT ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if (NULL == pstcCanInternData) + { + return ErrorInvalidParameter; + } + + if ( Ok != CanIsMbUpdatePossible( pstcCan, u8MsgBuf ) ) + { + return ErrorOperationInProgress ; + } + + // Set message valid bit to 0, afterwards message objects can be updated... + pstcCan->IF1ARB_f.MSGVAL = 0u ; + + // Write command mask register for updating arbitration register. + pstcCan->IF1CMSK_f.WR_RD = CAN_MSG_DIR_TX; + pstcCan->IF1CMSK_f.ARB = 1u; // Write Arbitraion + + // Set transmit callback function. + pstcCanInternData->stcCanInterruptHandling[u8MsgBuf].pfnCanTxInterruptFunction = pfnCallback; + + // Write configuration to IFx arbitration1/2 + if (CAN_MSG_ID_EXTENDED != pstcMsgId->bExtended) + { + // Just 11 bit identifier. + pstcCan->IF1ARB_f.ID = pstcMsgId->u32Identifier << (2u + 16u) ; + pstcCan->IF1ARB_f.XTD = 0u ; + } + else + { + // Write 29 bit identifier. + pstcCan->IF1ARB_f.ID = pstcMsgId->u32Identifier ; + pstcCan->IF1ARB_f.XTD = 1u ; + } + + // We can NOT use a combined register write here because this would destroy + // the u29ID bit field! + // Set message direction to transmit. + pstcCan->IF1ARB_f.DIR = CAN_MSG_DIR_TX ; + // Set message buffer valid. + pstcCan->IF1ARB_f.MSGVAL = 1u ; + + + // --------- + pstcCan->IF1CMSK_f.NEWDAT = 0u; + + // Set message buffer number to update message buffer. + pstcCan->IF1CREQ = u8MsgBuf + 1u ; + + return Ok; +} // Can_SetTransmitMsgBuffer + +/** + ***************************************************************************** + ** \brief Updates the message data of a message buffer and/or start transmission. + ** Transmits the message immediately (immediate transmission mode) or on + ** reception of a matching remote frame (remote transmission mode). + ** Function Can_SetTransmitMsgBuffer() must be called before setup the + ** identifier and enable this message buffer. + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** \param [in] pstcMsgData CAN message data + ** \param [in] enTxMode Transmission mode (immediately or remote) + ** + ** \retval Ok Message buffer has been successfully updated. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDl_PERIPHERAL_ENABLE_CAN)) + ** - pstcMsgData == NULL + ** - u8MsgBuf out of range + ** \retval ErrorUninitialized If Can_SetTransmitMsgBuffer() was not + ** called before. + ** \retval ErrorOperationInProgress If a transmission is pending (either wait + ** or call Can_ResetMsgBuffer() ). + *****************************************************************************/ +en_result_t Can_UpdateAndTransmitMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + const stc_can_msg_data_t* pstcMsgData, + en_can_tx_mode_t enTxMode + ) +{ + stc_can_intern_data_t* pstcCanInternData; // Pointer to internal data + uint16_t u16Data; + uint8_t u8DataLengthCode; + + // Check for NULL pointers + if ( (NULL == pstcCan) || + (NULL == pstcMsgData) + ) + { + return ErrorInvalidParameter; + } + + // Check for message buffer index in range + if ( u8MsgBuf >= CAN_MESSAGE_BUFFER_COUNT ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if ( NULL == pstcCanInternData ) + { + return ErrorInvalidParameter; + } + + if ( Ok != CanIsMbUpdatePossible( pstcCan, u8MsgBuf ) ) + { + return ErrorOperationInProgress ; + } + + // Write command mask register to read arbitration + pstcCan->IF1CMSK_f.WR_RD = CAN_MSG_DIR_RX; + pstcCan->IF1CMSK_f.ARB = 1u; // Write Arbitration + + // Set message buffer number to update message buffer. + pstcCan->IF1CREQ = u8MsgBuf + 1u ; + + // Check if setup was done previously. + if ( 0u == pstcCan->IF1ARB_f.MSGVAL ) + { + return ErrorUninitialized; + } + + u8DataLengthCode = (pstcMsgData->u8DataLengthCode > 8u) + ? 8u + : pstcMsgData->u8DataLengthCode ; + + + // Set message valid bit to 0, afterwards message objects can be updated... + pstcCan->IF1ARB_f.MSGVAL = 0u ; + + // Write command mask register to update arbitration register. + pstcCan->IF1CMSK_f.WR_RD = CAN_MSG_DIR_TX; + pstcCan->IF1CMSK_f.ARB = 1u; // Write Arbitration + + // Set message buffer number to update message buffer. + pstcCan->IF1CREQ = u8MsgBuf + 1u ; + + // Set message control register. + pstcCan->IF1MCTR_f.NEWDAT = 1u; // New data has been written + + if (TRUE == pstcCanInternData->bEobZero) + { + pstcCan->IF1MCTR_f.EOB = 0u; // Use as FIFO message buffer + } + else + { + pstcCan->IF1MCTR_f.EOB = 1u; // Use as single message buffer + } + + pstcCan->IF1MCTR_f.TXIE = 1u; // Transmit interrrupt enable + + pstcCan->IF1MCTR_f.DLC = u8DataLengthCode; + + if ( CanImmediateTransmit == enTxMode ) + { + pstcCan->IF1MCTR_f.RMTEN = 0u ; // Remote frame ignored + } + else + { + pstcCan->IF1MCTR_f.RMTEN = 1u ; // TXRQST is set on recv of a remote frame + } + + u16Data = 0; + + // Update of data bytes. + switch (u8DataLengthCode) + { + case 8u: + u16Data = pstcMsgData->au8Data[7] << 8u; + // ... fall through to process remaining bytes + case 7u: + u16Data |= pstcMsgData->au8Data[6]; + pstcCan->IF1DTB_LH = u16Data; + // ... fall through to process remaining bytes + case 6u: + u16Data = pstcMsgData->au8Data[5] << 8u; + // ... fall through to process remaining bytes + case 5u: + u16Data |= pstcMsgData->au8Data[4]; + pstcCan->IF1DTB_LL = u16Data; + // ... fall through to process remaining bytes + case 4u: + u16Data = pstcMsgData->au8Data[3] << 8u; + // ... fall through to process remaining bytes + case 3u: + u16Data |= pstcMsgData->au8Data[2]; + pstcCan->IF1DTA_LH = u16Data ; + // ... fall through to process remaining bytes + case 2u: + u16Data = pstcMsgData->au8Data[1] << 8u; + // ... fall through to process remaining bytes + case 1u: + u16Data |= pstcMsgData->au8Data[0]; + pstcCan->IF1DTA_LL = u16Data ; + + break ; + default: + break ; + } + + // Set message valid bit to 1, afterwards message object is ready to transmit. + pstcCan->IF1ARB_f.MSGVAL = 1 ; + + // Write command mask register to update arbitration, control, + // transmit request and data register. + pstcCan->IF1CMSK_f.WR_RD = CAN_MSG_DIR_TX; + pstcCan->IF1CMSK_f.ARB = 1u; // Write Arbitration + pstcCan->IF1CMSK_f.CONTROL = 1u; // Write Control + pstcCan->IF1CMSK_f.NEWDAT = 1u; // Write TXREQ/NEWDAT + pstcCan->IF1CMSK_f.DATAA = 1u; // Write Data A + pstcCan->IF1CMSK_f.DATAB = 1u; // Write Data B + + // Set message buffer number to update message buffer + // This will send the msg out ... + pstcCan->IF1CREQ = u8MsgBuf + 1u ; + + return Ok; +} // Can_UpdateAndTransmitMsgBuffer + +/** + ***************************************************************************** + ** \brief Updates the message data of a message buffer and/or start + ** with EOB = 0 (Msg Buffer as FIFO) transmission. + ** The function calls Can_UpdateAndTransmitMsgBuffer() + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** \param [in] pstcMsgData CAN message data + ** \param [in] enTxMode Transmission mode (immediately or remote) + ** + ** \retval Ok Message buffer has been successfully updated. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDL_PERIPHERAL_ENABLE_CAN)) + ** - pstcMsgData == NULL + ** - u8MsgBuf out of range + ** \retval ErrorUninitialized If Can_SetTransmitMsgBuffer() was not + ** called before. + ** \retval ErrorOperationInProgress If a transmission is pending (either wait + ** or call Can_ResetMsgBuffer() ). + *****************************************************************************/ +en_result_t Can_UpdateAndTransmitFifoMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + const stc_can_msg_data_t* pstcMsgData, + en_can_tx_mode_t enTxMode + ) +{ + stc_can_intern_data_t* pstcCanInternData; // Pointer to internal data + en_result_t enFuncResult; + + // Check for NULL pointers + if ( (NULL == pstcCan) || + (NULL == pstcMsgData ) + ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if ( NULL == pstcCanInternData ) + { + return ErrorInvalidParameter; + } + + // Preapare EOB = 0 + pstcCanInternData->bEobZero = TRUE; + + enFuncResult = Can_UpdateAndTransmitMsgBuffer(pstcCan, u8MsgBuf, pstcMsgData, enTxMode); + + // Reset EOB to '1' + pstcCanInternData->bEobZero = FALSE; + + return enFuncResult; +} // Can_UpdateAndTransmitFifoMsgBuffer + +/** + ***************************************************************************** + ** \brief Configure a message buffer for reception. + ** Configure and enable a message buffer for reception. The acceptance filter is set + ** by pstcMsgBuffer->stcIdentifier and u32MsgIdMask. Each '0' bit in + ** u32MsgIdMask masks the corresponding bit of the received message ID before + ** comparing it to the configured identifier (set by + ** pstcMsgBuffer->stcIdentifier). This allows receiving messages with + ** different identifier. Setting all bits of u32MsgIdMask to '1' will only + ** accept messages that match the configured identifier. + ** If extended identifier is used, the + ** u32MsgIdMask will also be interpreted as extended mask identifier. If 11 bit + ** identifier is used, than u32MsgIdMask will be used as 11 bit mask identifier. + ** The application must provide a message buffer object (pstcMsgBuffer) to be + ** filled with received data. + ** After reception of a message that passed the acceptance filter, + ** the message's identifier, data and data length is copied into the provided + ** message buffer and its bNew flag is set to TRUE. + ** The message buffer + ** has to be kept valid until this message buffer is reset (Can_ResetMsgBuffer()). + ** + ** A mask identifier has to be set when calling Can_SetReceiveMsgBuffer(), the length + ** for the mask identifier will be the same like the one used in pstcMsgBuffer (11-bit or + ** 29-bit identifier mask). The extended identification mask bit and the direction mask bit are + ** always set to 1. + ** + ** The API has + ** to check the bNew flag of parameter pstcMsgBuffer to get information about if a message + ** has already been received or not. If a new message has been received while bNew flag + ** is set (the last received message was not read out by API so far) than the bOverflow flag + ** will be set. So, if callback function is not used, the API has to reset the bNew flag when + ** the received message is read out (also the bOverflow flag has to be reset) and furthermore. + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** \param [in,out] pstcMsgBuffer CAN message object which defines identifier for acceptance filter. + ** \param [in] u32MsgIdMask Mask for identifier acceptance filter and later receives the received message (all '1' disables masking). + ** \param [in] pfnCallback Callback function which is called when new CAN message was received and accepted by this message buffer. + ** + ** \retval Ok Message buffer for reception has been succesfully set. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDL_PERIPHERAL_ENABLE_CAN)) + ** - pstcMsgBuffer == NULL + ** - u8MsgBuf out of range + *****************************************************************************/ +en_result_t Can_SetReceiveMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + stc_can_msg_t* pstcMsgBuffer, + uint32_t u32MsgIdMask, + can_rx_msg_func_ptr_t pfnCallback + ) +{ + stc_can_intern_data_t* pstcCanInternData; // Pointer to internal data + stc_can_if1cmsk_field_t unIF1CMSK; + stc_can_if1arb_field_t unIF1ARB; + + PDL_ZERO_STRUCT(unIF1CMSK); + PDL_ZERO_STRUCT(unIF1ARB); + + // Check for NULL pointers + if ( (NULL == pstcCan ) || + (NULL == pstcMsgBuffer ) + ) + { + return ErrorInvalidParameter; + } + + // Check for message buffer index in range + if ( u8MsgBuf >= CAN_MESSAGE_BUFFER_COUNT ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if ( NULL == pstcCanInternData ) + { + return ErrorInvalidParameter; + } + + // Disable message buffer at first (MSGVAL = 0) (otherwise a pending + // reception on this MB could cause an interrupt, using inconsistent data) + pstcCan->IF1ARB_f.MSGVAL = 0u ; + + // Set receive callback function and message buffer. + pstcCanInternData->stcCanInterruptHandling[u8MsgBuf].pfnCanRxInterruptFunction = pfnCallback; + pstcCanInternData->stcCanInterruptHandling[u8MsgBuf].pstcMsgBuffer = pstcMsgBuffer; + + // Configure mask register. + pstcCan->IF1MSK = 0u ; + + // Set direction to read and message valid bit to 1. + unIF1ARB.DIR = CAN_MSG_DIR_RX; // Set direction read + unIF1ARB.MSGVAL = 1u; // Set message valid bit to 1 + + // Update arbitration register and mask identifier. + if ( CAN_MSG_ID_EXTENDED != pstcMsgBuffer->stcIdentifier.bExtended ) + { + // Just 11-bit identifier. + unIF1ARB.ID = ((pstcMsgBuffer->stcIdentifier.u32Identifier) << 18u) ; + unIF1ARB.XTD = 0u; // Clear extended bit + pstcCan->IF1MSK_f.MSK = (u32MsgIdMask << 18) ; + } + else + { + // Write 29-bit identifier. + unIF1ARB.ID = pstcMsgBuffer->stcIdentifier.u32Identifier ; + unIF1ARB.XTD = 1u ; // Set extended bit + pstcCan->IF1MSK_f.MSK = u32MsgIdMask ; + } + + // Setup IF1ARB in hardware + pstcCan->IF1ARB_f = unIF1ARB; + pstcCan->IF1MSK_f.MXTD = 1u; + + // Update message control register, enable receive interrupt and mask flag. + pstcCan->IF1MCTR = 0x0000u; + pstcCan->IF1MCTR_f.RXIE = 1u; // Receive interrupt enable + pstcCan->IF1MCTR_f.UMASK = 1u; // Use acceptance mask + + if (TRUE == pstcCanInternData->bEobZero) + { + pstcCan->IF1MCTR_f.EOB = 0u; // Use as FIFO message buffer + } + else + { + pstcCan->IF1MCTR_f.EOB = 1u; // Use as single message buffer + } + + // Write command mask register + unIF1CMSK.WR_RD = CAN_MSG_DIR_TX; // Write to message RAM + unIF1CMSK.MASK = 1u; // Update mask + unIF1CMSK.ARB = 1u; // Update arbitration + unIF1CMSK.CONTROL = 1u; // Update control + pstcCan->IF1CMSK_f = unIF1CMSK; + + // Set message buffer number to update message buffer. + pstcCan->IF1CREQ = u8MsgBuf + 1u ; + + pstcMsgBuffer->bNew = FALSE ; // Preset to default + pstcMsgBuffer->bOverflow = FALSE ; // Preset to default + + return Ok; +} // Can_SetReceiveMsgBuffer + +/** + ***************************************************************************** + ** \brief Configure a message buffer for reception with EOB = 0 (FIFO mode). + ** This function calls Can_SetReceiveMsgBuffer() + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** \param [in,out] pstcMsgBuffer CAN message object which defines identifier for acceptance filter. + ** \param [in] u32MsgIdMask Mask for identifier acceptance filter and later receives the received message (all '1' disables masking). + ** \param [in] pfnCallback Callback function which is called when new CAN message was received and accepted by this message buffer. + ** + ** \retval Ok Message buffer for reception has been succesfully set. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDL_PERIPHERAL_ENABLE_CAN)) + ** - pstcMsgBuffer == NULL + ** - u8MsgBuf out of range + *****************************************************************************/ +en_result_t Can_SetReceiveFifoMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + stc_can_msg_t* pstcMsgBuffer, + uint32_t u32MsgIdMask, + can_rx_msg_func_ptr_t pfnCallback + ) +{ + stc_can_intern_data_t* pstcCanInternData; // Pointer to internal data + + en_result_t enFuncResult; + + // Check for NULL pointers + if ( (NULL == pstcCan ) || + (NULL == pstcMsgBuffer) + ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if ( NULL == pstcCanInternData ) + { + return ErrorInvalidParameter; + } + + // Preapare EOB = 0 + pstcCanInternData->bEobZero = TRUE; + + enFuncResult = Can_SetReceiveMsgBuffer(pstcCan, u8MsgBuf, pstcMsgBuffer, u32MsgIdMask, pfnCallback); + + // Reset EOB to '1' + pstcCanInternData->bEobZero = FALSE; + + return enFuncResult; +} // Can_SetReceiveFifoMsgBuffer + +/** + ***************************************************************************** + ** \brief Stop any message buffer operation i.e. disable it + ** + ** - stop pending transmission (reset TXRQST and NEWDAT flag): + ** - stop reception operation (reset MSGVAL flag) + ** - reset RXIE and TXIE + ** - clear pointers to external buffers and callback functions + ** + ** \param [in] pstcCan Pointer to register area of a CAN unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CAN_MESSAGE_BUFFER_COUNT - 1) + ** + ** \retval Ok Message buffer operations have been stoped + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCan == NULL + ** - pstcCanInternData == NULL (invalid or disabled CAN unit (PDL_PERIPHERAL_ENABLE_CAN)) + ** - u8MsgBuf out of range + *****************************************************************************/ +en_result_t Can_ResetMsgBuffer( volatile stc_cann_t* pstcCan, uint8_t u8MsgBuf ) +{ + stc_can_intern_data_t* pstcCanInternData ; // Pointer to internal data + + // Check for NULL pointer + if ( NULL == pstcCan ) + { + return ErrorInvalidParameter ; + } + + // Check for message buffer number in range + if ( u8MsgBuf >= CAN_MESSAGE_BUFFER_COUNT ) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure + pstcCanInternData = CanGetInternDataPtr( pstcCan ) ; + + // Check for NULL + if ( NULL == pstcCanInternData ) + { + return ErrorInvalidParameter ; + } + + // Reset message control register. + pstcCan->IF1MCTR = 0u ; + + // Reset message valid bit + pstcCan->IF1ARB_f.MSGVAL = 0u ; + + // Reset msg buffer and callback functions + pstcCanInternData->stcCanInterruptHandling[u8MsgBuf].pstcMsgBuffer = NULL ; + pstcCanInternData->stcCanInterruptHandling[u8MsgBuf].pfnCanTxInterruptFunction = NULL ; + pstcCanInternData->stcCanInterruptHandling[u8MsgBuf].pfnCanRxInterruptFunction = NULL ; + + return Ok ; +} // Can_ResetMsgBuffer + + +#endif // #if (defined(PDL_PERIPHERAL_CAN_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.h new file mode 100644 index 0000000000..bd5cb20e46 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can.h @@ -0,0 +1,478 @@ +/****************************************************************************** +* \file can.h +* +* \version 1.30 +* +* \brief Header file for Controller Area Network (CAN) functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __CAN_H__ +#define __CAN_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_CAN_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupCAN Controller Area Network (CAN) +* \{ +* \defgroup GroupCAN_Macros Macros +* \defgroup GroupCAN_Functions Functions +* \defgroup GroupCAN_GlobalVariables Global Variables +* \defgroup GroupCAN_DataStructures Data Structures +* \defgroup GroupCAN_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupCAN +* \{ +* Control Area Network (CAN) is a standard protocol for serial communication. It is +* widely used in various industries such +* as automobile and factory automation. The CAN controller complies with CAN +* protocol version 2.0A/B.
+* The CAN controller has the following features: +* - Supports a bit rate up to 1 Mbit/s
+* - Identifier mask for each message object
+* - Supports programmable FIFO mode
+* - Maskable interrupt
+* - Supports 32 message buffers
+* - Supports programmable loop-back mode for self-test operation
+* - Read and write from/to the message buffers
+* +* \section SectionCAN_ConfigurationConsideration Configuration Consideration +* You set fields in the stc_can_config_t structure to configure the peripheral. +* One field is the address of an stc_can_bitrate_t structure. You must set the fields in that structure as well. +* For example, use stcBitrate.enCanPrescaler to set the CAN clock prescaler.
+* After setting the configuration structure to the desired values, Call Can_Init() +* to configure the CAN peripheral.
+* To implement error handling, you must provide a function pointer +* pfnErrorCallback in stc_can_config_t. The callback functions are optional, but recommended, +* otherwise there is no report to the API in case of any error.
+* Similarly, to receive and handle status information, provide a callback +* function pointer pfnStatusCallback in stc_can_config_t.
+* To change CAN settings at runtime, call Can_DeInit(). Then set up the +* configuration structure with the new values, and call Can_Init(). +* Can_DeInit() completely disables the CAN module. It resets all setting to +* default values. All pending or ongoing transmission or reception is +* aborted.
+* +* Each CAN module has #CAN_MESSAGE_BUFFER_COUNT number of message buffers. You +* can use any buffer for reception or transmission of CAN messages.
+* To set up a message buffer for transmission call Can_SetTransmitMsgBuffer(). +* To use a message buffer for receiving CAN messages call +* Can_SetReceiveMsgBuffer(). You can specify a callback function that will be +* called whenever a message has been received.
+* The numbers of the message buffers used in this driver are +* indexed from 0 to 31 although the 'physical addresses' of these buffers are +* indexed from 1 to 32
+* \section SectionCAN_MoreInfo More Information +* For more information on the CAN peripheral, refer to
+* FM0+ Family 32-Bit MICROCONTROLLER PERIPHERAL MANUAL Communication Macro Part
+* FM4 Family 32-Bit MICROCONTROLLER PERIPHERAL MANUAL Communication Macro Part
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* FM0+ Family 32-Bit +* Microcontrollers Peripheral Manuals, and Errata Sheets
+* FM4 Family 32-Bit +* Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupCAN_Macros +* \{ +*/ +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_cann_t FM_CAN_TypeDef +#define CAN0 (*((volatile stc_cann_t *) FM_CAN0_BASE)) +#define CAN1 (*((volatile stc_cann_t *) FM_CAN1_BASE)) + +/// Size of data bytes in a receive or transmit operation (usually 8) +#define CAN_MESSAGE_DATA_BUFFER_SIZE 8u + +/// Number of possible message buffer for receive and transmit messages (usually 32) +#define CAN_MESSAGE_BUFFER_COUNT 32u + +/// Lower limit for TSEG1 in structure stc_can_bitrate_t +#define CAN_BITRATE_TSEG1_MIN 2u +/// Upper limit for TSEG1 in structure stc_can_bitrate_t +#define CAN_BITRATE_TSEG1_MAX 16u + +/// Lower limit for TSEG2 in structure stc_can_bitrate_t +#define CAN_BITRATE_TSEG2_MIN 1u +/// Upper limit for TSEG2 in structure stc_can_bitrate_t +#define CAN_BITRATE_TSEG2_MAX 8u + +/// Lower limit for Sync Jump Width in structure stc_can_bitrate_t +#define CAN_BITRATE_SYNC_JUMP_WIDTH_MIN 1u +/// Upper limit for Sync Jump Width in structure stc_can_bitrate_t +#define CAN_BITRATE_SYNC_JUMP_WIDTH_MAX 4u + +/// Lower limit for Prescaler in structure stc_can_bitrate_t +#define CAN_BITRATE_PRESCALER_MIN 1u +/// Upper limit for Prescaler in structure stc_can_bitrate_t +#define CAN_BITRATE_PRESCALER_MAX 64u + +/// Maximum CAN clock frequency (after prescaler) +#if (PDL_MCU_TYPE == PDL_FM4_TYPE3) || (PDL_MCU_TYPE == PDL_FM4_TYPE4) || (PDL_MCU_TYPE == PDL_FM4_TYPE5) +#define CAN_MAX_CLK 40000000u +#else +#define CAN_MAX_CLK 16000000u +#endif + +/** \} GroupCAN_Macros */ + +/** +* \addtogroup GroupCAN_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief CAN Unit configuration structures + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief CAN Prescaler + ******************************************************************************/ +typedef enum en_can_prescaler +{ + CanPreDiv11 = 0u, ///< CAN prescaler clock: no division + CanPreDiv12 = 1u, ///< CAN prescaler clock: 1/2 + CanPreDiv14 = 2u, ///< CAN prescaler clock: 1/4 + CanPreDiv18 = 3u, ///< CAN prescaler clock: 1/8 + CanPreDiv23 = 4u, ///< CAN prescaler clock: 2/3 + CanPreDiv13 = 5u, ///< CAN prescaler clock: 1/3 + CanPreDiv16 = 6u, ///< CAN prescaler clock: 1/6 + CanPreDiv112 = 7u, ///< CAN prescaler clock: 1/12 + CanPreDiv15 = 8u, ///< CAN prescaler clock: 1/5 + CanPreDiv110 = 9u ///< CAN prescaler clock: 1/10 +} en_can_prescaler_t; + +/** + ****************************************************************************** + ** \brief CAN transmit mode. + ** + ** To select how transmit data should be processed. + ******************************************************************************/ +typedef enum en_can_tx_mode +{ + CanImmediateTransmit = 0u, ///< Transmit message immediately + CanRemoteTransmit = 1u ///< Transmit message on reception of remote frame +} en_can_tx_mode_t; + +/** + ****************************************************************************** + ** \brief CAN status. + ** + ** These state values represent the current CAN state, and are used in the + ** CAN status changed callback function (can_status_chg_func_ptr_t). + ******************************************************************************/ +typedef enum en_can_status +{ + CanNoError = 0u, ///< No error pending. + CanStuffError = 1u, ///< More than 5 equal bits in a sequence have occurred in a part of a received message. + CanFormError = 2u, ///< A fixed format part of a received frame has the wrong format. + CanAckError = 3u, ///< The message this CAN Core transmitted was not acknowledged by another node. + CanBit1Error = 4u, ///< While trying to send a recessive bit (1) a dominant level (0) was sampled. + CanBit0Error = 5u, ///< While trying to send a dominant bit (0) a recessive level (1) was sampled. + CanCRCError = 6u ///< The CRC checksum was incorrect. +} en_can_status_t; + +/** + ****************************************************************************** + ** \brief CAN error. + ** + ** These error values are used to report any CAN related error to the API via + ** the CAN error callback function (can_error_func_ptr_t). + ******************************************************************************/ +typedef enum en_can_error +{ + CanBusOff = 0u, ///< The CAN module is in busoff state. + CanWarning = 1u ///< At least one error counter has reached error warning limit of 96. +} en_can_error_t; + +/// Enumeration to define an index for each enabled CAN instance +typedef enum en_can_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_CAN0 == PDL_ON) + CanInstanceIndexCan0, + #endif + #if (PDL_PERIPHERAL_ENABLE_CAN1 == PDL_ON) + CanInstanceIndexCan1, + #endif + CanInstanceIndexMax +} en_can_instance_index_t; + +/** \}GroupCAN_Types */ + +/** +* \addtogroup GroupCAN_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief CAN bitrate. + ** + ** This structure is used to set the bitrate register. All values are + ** decremented by 1 before writing to the CANn_BTR register + ** (see HW manual for more details). + ******************************************************************************/ +typedef struct stc_can_bitrate +{ + uint8_t u8TimeSegment1; ///< Range CAN_BITRATE_TSEG1_MIN to CAN_BITRATE_TSEG1_MAX (see define section) + uint8_t u8TimeSegment2; ///< Range CAN_BITRATE_TSEG2_MIN to CAN_BITRATE_TSEG2_MAX (see define section) + uint8_t u8SyncJumpWidth; ///< Range CAN_BITRATE_SYNC_JUMP_WIDTH_MIN to CAN_BITRATE_SYNC_JUMP_WIDTH_MAX (see define section) + uint16_t u16Prescaler; ///< Range PRESCALER_MIN to CAN_BITRATE_PRESCALER_MAX (see define section, divider for the peripheral clock CLKP2) + en_can_prescaler_t enCanPrescaler; ///< CAN PRESCALER setting. See #en_can_prescaler_t for details +} stc_can_bitrate_t; + +/** + ****************************************************************************** + ** \brief CAN message identifier + ** + ** This structure is used to set the CAN message identifier for transmit and + ** receive operations. The identifiction is needed when setting the CAN + ** arbitration register. On the one side this structure is used in the + ** Can_SetTransmitMsgBuffer() function, on the other side same structure is + ** used in the structure stc_can_msg_t which is used for receive data in + ** Can_SetReceiveMsgBuffer(...) function. + ******************************************************************************/ +typedef struct stc_can_msg_id +{ + uint32_t u32Identifier; ///< 11- or 29-bit identifier. The valid bit length depends on bExtended. + boolean_t bExtended; ///< TRUE: 29-bit identifier, FALSE: 11-bit identifier. +} stc_can_msg_id_t; + +/** + ****************************************************************************** + ** \brief CAN message data. + ** + ** Data structure for transmit and receive operations, maximum value for + ** parameter u8DataLengthCode is CAN_MESSAGE_DATA_BUFFER_SIZE. + ******************************************************************************/ +typedef struct stc_can_msg_data +{ + uint8_t au8Data[CAN_MESSAGE_DATA_BUFFER_SIZE]; ///< Data of CAN message. + uint8_t u8DataLengthCode; ///< Number of valid bytes in au8Data and DLC of CAN message. +} stc_can_msg_data_t; + +/** + ****************************************************************************** + ** \brief CAN message. + ** + ** This structure stores a CAN message, including the identifier, data + ** and data length code (DLC). It also contains an overflow and new flag + ** which indicates the message state for received messages. + ******************************************************************************/ +typedef struct stc_can_msg +{ + stc_can_msg_id_t stcIdentifier; ///< 11- or 29-bit identifier (ID). + stc_can_msg_data_t stcData; ///< Data and DLC. + volatile boolean_t bOverflow; ///< TRUE if new message was received while bNew still TRUE + volatile boolean_t bNew; ///< TRUE if new message received (must be reset to FALSE by application to release message object). +} stc_can_msg_t; + +/** + ***************************************************************************** + ** \brief Message transmission complete callback function (can_tx_msg_func_ptr_t). + ** + ** Signals a successful completed transmission. + *****************************************************************************/ +typedef void (*can_tx_msg_func_ptr_t)(uint8_t u8MsgBuf); + +/** + ***************************************************************************** + ** \brief Message reception callback function (can_rx_msg_func_ptr_t). + ** + ** Signals that CAN has received a new message. + *****************************************************************************/ +typedef void (*can_rx_msg_func_ptr_t)(uint8_t u8MsgBuf, stc_can_msg_t* pstcRxMsg); + + +/** + ***************************************************************************** + ** \brief Status changed callback function (can_status_chg_func_ptr_t). + ** + ** Any status change will be reported to the API (see #en_can_status_t for + ** possible status change codes). + *****************************************************************************/ +typedef void (*can_status_chg_func_ptr_t)(en_can_status_t enCanStatus); + + +/** + ***************************************************************************** + ** \brief Error callback function (can_error_func_ptr_t). + ** + ** Any error will be reported to the API (see #en_can_error_t for + ** possible error codes). + *****************************************************************************/ +typedef void (*can_error_func_ptr_t)(en_can_error_t enCanError); + +/** + ***************************************************************************** + ** \brief CAN interrupt pointer structure + ** + ** Holds some pointers to callback functions and buffer + *****************************************************************************/ +typedef struct stc_can_interrupt_handling +{ + stc_can_msg_t* pstcMsgBuffer; ///< pointer to message buffer + can_tx_msg_func_ptr_t pfnCanTxInterruptFunction; ///< pointer to transmit interrupt callback + can_rx_msg_func_ptr_t pfnCanRxInterruptFunction; ///< pointer to receive interrupt callback +} stc_can_interrupt_handling_t; + +/** + ***************************************************************************** + ** \brief CAN notification pointer structure + ** + ** Holds some pointers to callback functions for status and error notification + *****************************************************************************/ +typedef struct stc_can_notification +{ + can_status_chg_func_ptr_t pfnCanStatusInterruptFunction ; + can_error_func_ptr_t pfnCanErrorInterruptFunction ; +} stc_can_notification_t; + +/** + ****************************************************************************** + ** \brief CAN configuration. + ** + ** Is used to set the CAN bitrate and allows deactivating of automatic + ** retransmission in case of a transmission error. Optionally error and + ** status changed notification can be set. + ******************************************************************************/ +typedef struct stc_can_config +{ + can_status_chg_func_ptr_t pfnStatusCallback; ///< Callback function for CAN status changes, can be NULL. + can_error_func_ptr_t pfnErrorCallback; ///< Callback function for CAN related errors, can be NULL. + boolean_t bDisableAutomaticRetransmission; ///< TRUE: Automatic retransmission is disabled, FALSE: Automatic retransmission is enabled. + stc_can_bitrate_t stcBitrate; ///< CAN bitrate setting. + boolean_t bTouchPrescaler; ///< TRUE: Can_Init() initializes CANPRES, FALSE: CANPRES not touched +} stc_can_config_t; + + +/// CAN instance internal data, storing internal information for each enabled CAN instance. +typedef struct stc_can_intern_data +{ + stc_can_interrupt_handling_t stcCanInterruptHandling[CAN_MESSAGE_BUFFER_COUNT]; + stc_can_notification_t stcCanNotificationCb; + boolean_t bEobZero; +} stc_can_intern_data_t; + +/// CAN instance data type +typedef struct stc_can_instance_data +{ + volatile stc_cann_t* pstcInstance; ///< pointer to registers of an instance + stc_can_intern_data_t stcInternData; ///< module internal data of instance +} stc_can_instance_data_t; + +/** \} GroupCAN_DataStructures */ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + + +/** +* \addtogroup GroupCAN_GlobalVariables +* \{ +*/ +/// Look-up table for all enabled CAN instances and their internal data +extern stc_can_instance_data_t m_astcCanInstanceDataLut[]; + +/** \}GroupCAN_GlobalVariables */ + +/** +* \addtogroup GroupCAN_Functions +* \{ +*/ + + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +extern void CanIrqHandler( volatile stc_cann_t* pstcCan, + stc_can_intern_data_t* pstcCanInternData + ) ; + +extern en_result_t Can_Init( volatile stc_cann_t* pstcCan, + const stc_can_config_t* pstcConfig + ) ; + +extern en_result_t Can_DeInit( volatile stc_cann_t* pstcCan ) ; + +extern en_result_t Can_SetTransmitMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + const stc_can_msg_id_t* pstcMsgId, + can_tx_msg_func_ptr_t pfnCallback + ) ; + +extern en_result_t Can_UpdateAndTransmitMsgBuffer( + volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + const stc_can_msg_data_t* pstcMsgData, + en_can_tx_mode_t enTxMode + ) ; + +extern en_result_t Can_UpdateAndTransmitFifoMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + const stc_can_msg_data_t* pstcMsgData, + en_can_tx_mode_t enTxMode + ) ; + +extern en_result_t Can_SetReceiveMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + stc_can_msg_t* pstcMsgBuffer, + uint32_t u32MsgIdMask, + can_rx_msg_func_ptr_t pfnCallback + ) ; + +extern en_result_t Can_SetReceiveFifoMsgBuffer( volatile stc_cann_t* pstcCan, + uint8_t u8MsgBuf, + stc_can_msg_t* pstcMsgBuffer, + uint32_t u32MsgIdMask, + can_rx_msg_func_ptr_t pfnCallback + ) ; + +extern en_result_t Can_ResetMsgBuffer( volatile stc_cann_t* pstcCan, uint8_t u8MsgBuf ) ; + +/** \}GroupCAN_Functions */ +/** \} GroupCAN */ +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_CAN_ACTIVE)) + +#endif /* __CAN_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.c new file mode 100644 index 0000000000..70eeaf85c9 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.c @@ -0,0 +1,117 @@ +/****************************************************************************** +* \file can_pre.c +* +* \version 1.20 +* +* \brief CAN prescaler function +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "can/can_pre.h" + +#if (defined(PDL_PERIPHERAL_CANFD_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global (no 'static') and local ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Initialize CAN prescaler + ** + ** Setup CAN prescaler for CANFD. If the CAN module was activated, use + ** Can_Init() API to initialize the CAN prescaler instead. + ** + ** \param [in] enPrescale Prescaler divisor. + ** + ** \retval Ok CAN prescaler has been successfully setup. + ** \retval ErrorInvalidParameter Invalid divisor. + *****************************************************************************/ +en_result_t Canpre_Init( en_canfd_prescaler_t enPrescale ) +{ + en_result_t enResult; + + // Initialize result value (as 'Ok'). + enResult = Ok; + + // CAN dedicated clock prescaler. + switch ( enPrescale ) + { + case CanfdPreDiv11: + FM_CANPRES->CANPRE = 0x00u; + break; + case CanfdPreDiv12: + FM_CANPRES->CANPRE = 0x01u; + break; + case CanfdPreDiv14: + FM_CANPRES->CANPRE = 0x02u; + break; + case CanfdPreDiv18: + FM_CANPRES->CANPRE = 0x04u; + break; + case CanfdPreDiv23: + FM_CANPRES->CANPRE = 0x08u; + break; + case CanfdPreDiv13: + FM_CANPRES->CANPRE = 0x09u; + break; + case CanfdPreDiv16: + FM_CANPRES->CANPRE = 0x0Au; + break; + case CanfdPreDiv112: + FM_CANPRES->CANPRE = 0x0Bu; + break; + case CanfdPreDiv15: + FM_CANPRES->CANPRE = 0x0Cu; + break; + case CanfdPreDiv110: + FM_CANPRES->CANPRE = 0x0Eu; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + + // Return result. + return enResult; +} + +#endif // if (defined(PDL_PERIPHERAL_CANPRE_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.h new file mode 100644 index 0000000000..b44ee6713c --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/can_pre.h @@ -0,0 +1,98 @@ +/****************************************************************************** +* \file can_pre.h +* +* \version 1.20 +* +* \brief Header file for CAN prescaler functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __CAN_PRE_H__ +#define __CAN_PRE_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_CANFD_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \addtogroup GroupCANFD +* \{ +*/ +/****************************************************************************** + * Global definitions + ******************************************************************************/ +/** +* \addtogroup GroupCANFD_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief CAN Prescaler + ******************************************************************************/ +typedef enum en_canfd_prescaler +{ + CanfdPreDiv11 = 0, // CAN prescaler clock: no division + CanfdPreDiv12 = 1, // CAN prescaler clock: 1/2 + CanfdPreDiv14 = 2, // CAN prescaler clock: 1/4 + CanfdPreDiv18 = 3, // CAN prescaler clock: 1/8 + CanfdPreDiv23 = 4, // CAN prescaler clock: 2/3 + CanfdPreDiv13 = 5, // CAN prescaler clock: 1/3 + CanfdPreDiv16 = 6, // CAN prescaler clock: 1/6 + CanfdPreDiv112 = 7, // CAN prescaler clock: 1/12 + CanfdPreDiv15 = 8, // CAN prescaler clock: 1/5 + CanfdPreDiv110 = 9 // CAN prescaler clock: 1/10 +} en_canfd_prescaler_t; + +/** \}GroupCANFD_Types */ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/** +* \addtogroup GroupCANFD_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +en_result_t Canpre_Init( en_canfd_prescaler_t enPrescale ); + +/** \}GroupCANFD_Functions */ +/** \} GroupCANFD */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_CANPRE_ACTIVE)) + +#endif /* __CAN_PRE_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.c new file mode 100644 index 0000000000..198ae5bfb1 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.c @@ -0,0 +1,1929 @@ +/****************************************************************************** +* \file canfd.c +* +* \version 1.20 +* +* \brief Controller Area Network with Flexible Data Rate(CANFD) driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "can/canfd.h" + +// [andreika]: fix #elseif -> #elif for GCC + +#if (defined(PDL_PERIPHERAL_CANFD_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/// Macro to return the number of enabled CAN FD instances +#define CANFD_INSTANCE_COUNT (uint32_t)(sizeof(m_astcCanfdInstanceDataLut) / sizeof(m_astcCanfdInstanceDataLut[0])) + +/// Controller dependent constants. + +/// Message RAM +#define CANFD_MSGRAM_OFFSET (0x00008000UL) // Message RAM address offset from the base address of related controller +#define CANFD_MSGRAM_SIZEB (16384) // Byte size of message RAM. +#define CANFD_MSGRAM_SIZEW (CANFD_MSGRAM_SIZEB >> 2) // Word size of message RAM. + +/// Tx buffer transmission requested marks +#define CANFD_TX_NOT_REQUESTED (0x00U) // not requested +#define CANFD_TX_REQUESTED (0x96U) // requested + +/// Bit masks for IR register + // error bits +#define CANFD_IR_MASK_ERROR (CANFD_ERROR_STE | \ + CANFD_ERROR_FOE | \ + CANFD_ERROR_ACKE | \ + CANFD_ERROR_BE | \ + CANFD_ERROR_CRCE | \ + CANFD_ERROR_WDI | \ + CANFD_ERROR_ELO | \ + CANFD_ERROR_BEU | \ + CANFD_ERROR_BEC | \ + CANFD_ERROR_TOO | \ + CANFD_ERROR_MRAF | \ + CANFD_ERROR_TEFL | \ + CANFD_ERROR_RF1L | \ + CANFD_ERROR_RF0L) +#define CANFD_IR_MASK_STATUS (0x03800000UL) // bus status bits +#define CANFD_IR_MASK_RXBUF (0x00080000UL) // dedicated Rx buffer related bits +#define CANFD_IR_MASK_RXFIFO0 (0x00000001UL) // Rx FIFO0 related bits +#define CANFD_IR_MASK_RXFIFO1 (0x00000010UL) // Rx FIFO1 related bits + // all of reception related bits +#define CANFD_IR_MASK_RX (CANFD_IR_MASK_RXBUF | CANFD_IR_MASK_RXFIFO0 | CANFD_IR_MASK_RXFIFO1) +#define CANFD_IR_MASK_TX (0x00000200UL) // transmission related bits + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CAN FD Rx buffer and FIFO element. + ** + ** This structure defines a dedicated Rx buffer and Rx FIFO element placed on + ** the message RAM. + *****************************************************************************/ +#define CANFD_RXBUF_INFOSIZE (2) // Rx buffer header size +typedef struct stc_canfd_rx_buffer +{ + union { + struct { + uint32_t id : 29; // Identifier + uint32_t rtr : 1; // Remote Transmission Request + uint32_t xtd : 1; // Extended Identifier + uint32_t esi : 1; // Error State Indicator + uint32_t rxts : 16; // Rx Timestamp + uint32_t dlc : 4; // Data Length Code + uint32_t brs : 1; // Bit Rate Switch + uint32_t edl : 1; // Extended Data Length + uint32_t rsv : 2; // (reserved) + uint32_t fidx : 7; // Filter Index + uint32_t anmf : 1; // Accepted Non-matching Frame + }; + uint32_t w[2]; // to access as word + }; + uint32_t data[16]; // data buffer (defined by maximum size) +} stc_canfd_rx_buffer_t; + +/** + ***************************************************************************** + ** \brief CAN FD Tx buffer element. + ** + ** This structure defines a dedicated Tx buffer, queue and FIFO element + ** placed on the message RAM. + *****************************************************************************/ +#define CANFD_TXBUF_INFOSIZE (2) // Tx buffer header size +typedef struct stc_canfd_tx_buffer +{ + union { + struct { + uint32_t id : 29; // Identifier + uint32_t rtr : 1; // Remote Transmission Request + uint32_t xtd : 1; // Extended Identifier + uint32_t rsv1 : 1; // (reserved) + uint32_t rsv3 : 16; // (reserved) + uint32_t dlc : 4; // Data Length Code + uint32_t rsv2 : 3; // (reserved) + uint32_t efc : 1; // Event FIFO Control + uint32_t mm : 8; // Message Marker + }; + uint32_t w[2]; // to access as word + }; + uint32_t data[16]; // data buffer (defined by maximum size) +} stc_canfd_tx_buffer_t; + +/** + ***************************************************************************** + ** \brief CAN FD Tx event FIFO element. + ** + ** This structure defines a dedicated Tx event FIFO element placed on the + ** message RAM. + *****************************************************************************/ +typedef struct stc_canfd_tx_event +{ + union { + struct { + uint32_t id : 29; // Identifier + uint32_t rtr : 1; // Remote Transmission Request + uint32_t xtd : 1; // Extended Identifier + uint32_t esi : 1; // Error State Indicator + uint32_t txts : 16; // Tx Timestamp + uint32_t dlc : 4; // Data Length Code + uint32_t brs : 1; // Bit Rate Switch + uint32_t edl : 1; // Extended Data Length + uint32_t et : 2; // Event Type + uint32_t mm : 16; // Message Marker + }; + uint32_t w[2]; // to access as word + }; +} stc_canfd_tx_event_t; + +/** + ***************************************************************************** + ** \brief CAN FD standard message ID filter element. + ** + ** This structure defines a standard ID filtering element placed on the + ** message RAM. + *****************************************************************************/ +#define CANFD_STDID_INFOSIZE (1) +typedef struct stc_canfd_stdid_filter +{ + union { + struct { + uint32_t sfid2 : 11; // Standard Filter ID 2 + uint32_t rsv : 5; // (reserved) + uint32_t sfid1 : 11; // Standard Filter ID 1 + uint32_t sfec : 3; // Standard Filter Element Configuration + uint32_t sft : 2; // Standard Filter Type + }; + uint32_t w; // to access as word + }; +} stc_canfd_stdid_filter_t; + +/** + ***************************************************************************** + ** \brief CAN FD extended message ID filter element. + ** + ** This structure defines an extended ID filtering element placed on the + ** message RAM. + *****************************************************************************/ +#define CANFD_EXTID_INFOSIZE (2) +typedef struct stc_canfd_extid_filter +{ + union { + struct { + uint32_t efid1 : 29; // Extended Filter ID 1 + uint32_t efec : 3; // Extended Filter Element Configuration + uint32_t efid2 : 29; // Extended Filter ID 2 + uint32_t rsv : 1; // (reserved) + uint32_t eft : 2; // Extended Filter Type + }; + uint32_t w[2]; // to access as word + }; +} stc_canfd_extid_filter_t; + + +/** + ***************************************************************************** + ** \brief CAN FD internal data + ** + ** This structure defines an extended ID filtering element placed on the + ** message RAM. + *****************************************************************************/ +/// +typedef enum en_canfd_confirmation_method +{ + CanfdConfirmPolling = 0, // Confirm by polling. + CanfdConfirmInterrupt = 1 // Confirm by interrupt. +} en_canfd_confirmation_method_t; + +/// +typedef struct stc_canfd_rx_confirmation +{ + en_canfd_confirmation_method_t enRxBuffer; + en_canfd_confirmation_method_t enRxFIFO0; + en_canfd_confirmation_method_t enRxFIFO1; + en_canfd_confirmation_method_t enTxBuffer; + en_canfd_confirmation_method_t enBusStatus; + en_canfd_confirmation_method_t enErrorStatus; +} stc_canfd_rx_confirmation_t; + +/// CAN FD instance internal data, storing internal information for each enabled CAN FD instance. +typedef struct stc_canfd_intern_data +{ + en_canfd_mode_t enCanfdMode; + en_canfd_clock_t enCanfdClock; + stc_canfd_interrupt_handling_t stcCanfdInterruptHandling; + stc_canfd_notification_t stcCanfdNotificationCb; + stc_canfd_rx_confirmation_t stcCanfdRxConfirmation; + uint8_t u8TxReqMarker[CANFD_MESSAGE_TXBUFFER_COUNT]; +} stc_canfd_intern_data_t; + +/// CAN FD instance data type +typedef struct stc_canfd_instance_data +{ + volatile stc_canfdn_t* pstcInstance; // pointer to registers of an instance + stc_canfd_intern_data_t stcInternData; // module internal data of instance +} stc_canfd_instance_data_t; + + +/** + ***************************************************************************** + ** \brief Rx FIFO ID. + *****************************************************************************/ +typedef enum en_canfd_rxfifo_number +{ + CanfdRxFIFO0 = 0, // Rx FIFO0 + CanfdRxFIFO1 = 1 // Rx FIFO1 +} en_canfd_rxfifo_number_t; + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +static stc_canfd_intern_data_t* CanfdGetInternDataPtr( volatile stc_canfdn_t* pstcCanfd ); + +static void CanfdInitInterrupt( volatile stc_canfdn_t* pstcCanfd ); +static void CanfdDeInitInterrupt( volatile stc_canfdn_t* pstcCanfd ); + +static en_result_t CanfdCheckAndNotifyRxMsg( volatile stc_canfdn_t* pstcCanfd, en_canfd_confirmation_method_t enMethod, uint32_t* pu32Accepted ); +static stc_canfd_stdid_filter_t* CanfdCalcStdIdFilterAddress( volatile stc_canfdn_t* pstcCanfd, uint8_t u8Index ); +static stc_canfd_extid_filter_t* CanfdCalcExtIdFilterAddress( volatile stc_canfdn_t* pstcCanfd, uint8_t u8Index ); +static stc_canfd_rx_buffer_t* CanfdCalcRxBufferAddress( volatile stc_canfdn_t* pstcCanfd, uint8_t u8Index ); +static en_result_t CanfdGetRxFIFO( volatile stc_canfdn_t* pstcCanfd, en_canfd_rxfifo_number_t enNumber, stc_canfd_rx_buffer_t* pstcRxMsg ); +static en_result_t CanfdConvRxBuffer( stc_canfd_rx_buffer_t* pstcRxBuffer, stc_canfd_msg_t* pstcRxMsg ); +static stc_canfd_tx_buffer_t* CanfdCalcTxBufferAddress( volatile stc_canfdn_t* pstcCanfd, uint8_t u8Index ); +static en_result_t CanfdClearTxRequestMarker( volatile stc_canfdn_t* pstcCanfd ); + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +// Look-up table for all enabled CAN FD instances and their internal data +static stc_canfd_instance_data_t m_astcCanfdInstanceDataLut[] = +{ + #if (PDL_PERIPHERAL_ENABLE_CANFD0 == PDL_ON) + { + &CANFD0 // pstcInstance + // [andreika]: fix gcc + ,{ 0 } // stcInternData (not initialized yet) + }, + #endif +}; + +// convert Rx/Tx buffer size parameter to real buffer size in word +static const uint8_t u8BufSizeInWord[] = { + 2, // 2 words ( 8 bytes) + 3, // 3 words (12 bytes) + 4, // 4 words (16 bytes) + 5, // 5 words (20 bytes) + 6, // 6 words (24 bytes) + 8, // 8 words (32 bytes) + 12, // 12 words (48 bytes) + 16 // 16 words (64 bytes) +}; + +// convert DLC to data size in byte +static const uint8_t u8DlcInByte[] = { + 0, // 0 byte + 1, // 1 byte + 2, // 2 bytes + 3, // 3 bytes + 4, // 4 bytes + 5, // 5 bytes + 6, // 6 bytes + 7, // 7 bytes + 8, // 8 bytes + 12, // 12 bytes + 16, // 16 bytes + 20, // 20 bytes + 24, // 24 bytes + 32, // 32 bytes + 48, // 48 bytes + 64, // 64 bytes +}; + +/******************************************************************************/ +/* Function implementation - global (no 'static') and local ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain CAN FD instance. + ** + ** \param pstcCanfd Pointer to CAN FD instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_canfd_intern_data_t* CanfdGetInternDataPtr( volatile stc_canfdn_t* pstcCanfd ) +{ + uint32_t u32Instance; + stc_canfd_intern_data_t* pstcIntarnData; + + // Initialize address of corresponding intarnal data (NULL). + pstcIntarnData = NULL; + + // Search internal data. + for (u32Instance = 0; NULL == pstcIntarnData && CANFD_INSTANCE_COUNT > u32Instance; u32Instance++) + { + // If corresponding data was found, ... + if (pstcCanfd == m_astcCanfdInstanceDataLut[u32Instance].pstcInstance) + { + // Set valid address to result pointer. + pstcIntarnData = &m_astcCanfdInstanceDataLut[u32Instance].stcInternData; + } + } + + // Return result. + return pstcIntarnData; +} + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on CAN FD instance + ** + ** \param pstcCanfd Pointer to CAN FD instance + ** + ******************************************************************************/ + +static void CanfdInitInterrupt( volatile stc_canfdn_t* pstcCanfd ) +{ +#if(defined(IRQ_CAN1_AVAILABLE)) + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_EnableIRQ(CAN1_IRQn); + NVIC_SetPriority(CAN1_IRQn, PDL_IRQ_LEVEL_CAN1_CANFD0); +#elif(defined(IRQ_CAN1_CANFD0_AVAILABLE)) + NVIC_ClearPendingIRQ(CAN1_CANFD0_IRQn); + NVIC_EnableIRQ(CAN1_CANFD0_IRQn); + NVIC_SetPriority(CAN1_CANFD0_IRQn, PDL_IRQ_LEVEL_CAN1_CANFD0); +#elif(defined(IRQ_CANFD0_AVAILABLE)) + NVIC_ClearPendingIRQ(CANFD0_IRQn); + NVIC_EnableIRQ(CANFD0_IRQn); + NVIC_SetPriority(CANFD0_IRQn, PDL_IRQ_LEVEL_CAN1_CANFD0); +#endif +} + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on CAN FD instance + ** + ** \param pstcCanfd Pointer to CAN FD instance + ** + ******************************************************************************/ +static void CanfdDeInitInterrupt( volatile stc_canfdn_t* pstcCanfd ) +{ +#if(defined(IRQ_CAN1_AVAILABLE)) + NVIC_ClearPendingIRQ(CAN1_IRQn); + NVIC_DisableIRQ(CAN1_IRQn); + NVIC_SetPriority(CAN1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif(defined(IRQ_CAN1_CANFD0_AVAILABLE)) + NVIC_ClearPendingIRQ(CAN1_CANFD0_IRQn); + NVIC_DisableIRQ(CAN1_CANFD0_IRQn); + NVIC_SetPriority(CAN1_CANFD0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif(defined(IRQ_CANFD0_AVAILABLE)) + NVIC_ClearPendingIRQ(CANFD0_IRQn); + NVIC_DisableIRQ(CANFD0_IRQn); + NVIC_SetPriority(CANFD0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +} + + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ + +/** + ***************************************************************************** + ** \brief CAN FD (Status/Error/Rx/Tx) interrupt ISR + ** + ** Check for any pending interrupt source and process until no more INTs are + ** active. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN unit. + *****************************************************************************/ +void CanfdIrqHandler( volatile stc_canfdn_t* pstcCanfd ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; + uint8_t u8MsgNumber; + uint32_t u32IR; + uint32_t u32TXBRP; + uint32_t u32AccInt; + uint32_t u32AccRx; + en_result_t enResult; + + // Get pointer to internal data structure. + pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ); + + // Perform interrupt process if specified CAN FD base address was recognized. + if ( NULL != pstcCanfdInternData ) + { + // Get interrupt flag register. + u32IR = pstcCanfd->IR; + + // Clear variables that hold accepted interrupt flags. + u32AccInt = 0; + u32AccRx = 0; + + // Check error flags. + if ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enErrorStatus && + NULL != pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdErrorInterruptFunction && + 0UL != ( u32IR & CANFD_IR_MASK_ERROR ) ) + { + // Nortify error status. + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdErrorInterruptFunction( u32IR & CANFD_IR_MASK_ERROR ); + + // Set value to clear error status change interrupt bit. + u32AccInt |= CANFD_IR_MASK_ERROR; + } + + // Check status flags. + if ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enBusStatus && + NULL != pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdStatusInterruptFunction && + 0UL != ( u32IR & CANFD_IR_MASK_STATUS ) ) + { + // Check bus status. + Canfd_GetBusStatus( pstcCanfd ); + + // Set value to clear bus status change interrupt bit. + u32AccInt |= CANFD_IR_MASK_STATUS; + } + + // Check reception interrupt. + if ( 0UL != ( u32IR & CANFD_IR_MASK_RX ) ) + { + // Check and notify received messages by polling. + enResult = CanfdCheckAndNotifyRxMsg( pstcCanfd, CanfdConfirmInterrupt, &u32AccRx ); + + // If process was done successfully, ... + if ( Ok == enResult ) + { + // Set value to clear accepted Rx buffer/FIFO0/FIFO1 new data interrupt bit. + u32AccInt |= u32AccRx; + } + } + + // Check transmission related interrupts. + if ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enTxBuffer ) + { + // Check transmission finished interrput. + if ( 0UL != ( u32IR & CANFD_IR_MASK_TX) ) + { + // Get Tx buffer transmission request pending register to check whether requested transmissions were finished. + u32TXBRP = pstcCanfd->TXBRP; + + // Loop to check and notify all Tx buffers. + for ( u8MsgNumber = 0; CANFD_MESSAGE_TXBUFFER_COUNT > u8MsgNumber; u8MsgNumber++ ) + { + // Check requested transmission state. + if ( CANFD_TX_REQUESTED == pstcCanfdInternData->u8TxReqMarker[u8MsgNumber] && + 0UL == ( u32TXBRP & 1UL ) ) + { + // Callback if the pointer is valid. + if ( NULL != pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdTxInterruptFunction ) + { + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdTxInterruptFunction( u8MsgNumber ); + } + + // Clear marker. + pstcCanfdInternData->u8TxReqMarker[u8MsgNumber] = CANFD_TX_NOT_REQUESTED; + } + + // Shift TXBRP 1bit right to check next Tx buffer. + u32TXBRP >>= 1; + } + + // Set value to clear Tx done interrupt bit. + u32AccInt |= CANFD_IR_MASK_TX; + } + } + + // Clear accepted interrupt flags all. + pstcCanfd->IR = u32AccInt; + } +} // CanfdIrqHandler + +/** + ***************************************************************************** + ** \brief Initializes the CAN FD module. + ** + ** This function initializes one specific CAN FD module with the parameters + ** provided in the given config structure. + ** After initialization the CAN FD module has Error, Status and Module-Interrupt + ** enabled and is ready to use. + ** + ** Canfd_Init() has to be called with the parameter pstcConfig of type + ** stc_canfd_config_t the basic CAN settings the CAN operation mode, the CAN + ** baudrate, and the error and status change callback function can be set. + ** + ** All values in pstcConfig have to be in valid range (see can.h for allowed + ** ranges of dedicated parameters). The error and status change callback + ** functions can be NULL. In this case no information of error or status + ** changes will be reported to the API. + ** + ** To reset and disable the CAN FD module the function Canfd_DeInit() has to + ** be used. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] pstcConfig CAN FD configuration parameters. + ** + ** \retval Ok CAN FD module has been successfully initialized. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - pstcConfig == NULL + ** - pstcCanfdInternData == NULL (invalid or disabled CAN FD unit (PDL_PERIPHERAL_ENABLE_CANFD)) + ** - pstcConfig->enCanfdMode parameter out of range + ** - pstcConfig->enCanfdClock parameter out of range + *****************************************************************************/ +en_result_t Canfd_Init( volatile stc_canfdn_t* pstcCanfd, const stc_canfd_config_t* pstcConfig ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; + uint32_t* pu32Adrs; + stc_canfd_stdid_filter_t stcCanfdStdID; + uint16_t u16BRP; // CAN bit rate prescaler + uint16_t u16TSEG1; // CAN Time segment 1 + uint16_t u16TSEG2; // CAN Time segment 2 + uint16_t u16SJW; // CAN (Re)synchronization jump width + uint16_t u16FBRP = 0u; // CAN FD bit rate prescaler + uint16_t u16TDCO; // CAN FD transceiver delay compensation offset + uint16_t u16TDC; // CAN FD transceiver delay compensation enable + uint16_t u16FTSEG1 = 0u; // CAN FD Time segment 1 + uint16_t u16FTSEG2 = 0u; // CAN FD Time segment 2 + uint16_t u16FSJW = 0u; // CAN FD (Re)synchronization jump width + uint16_t u16Count; + en_result_t enResult; + + // Initialize result value (as 'Ok'). + enResult = Ok; + + // Check for NULL pointers. + if ( NULL == pstcCanfd || + NULL == pstcConfig + ) + { + enResult = ErrorInvalidParameter; + } + // Check CAN operation mode. + else if ( CanfdModeClassic != pstcConfig->enCanfdMode && + CanfdModeFDFixed != pstcConfig->enCanfdMode && + CanfdModeFDFlex != pstcConfig->enCanfdMode + ) + { + enResult = ErrorInvalidParameter; + } + // Check CAN prescaler output clock frequency. + else if ( CanfdClock32MHz != pstcConfig->enCanfdClock && + CanfdClock40MHz != pstcConfig->enCanfdClock + ) + { + enResult = ErrorInvalidParameter; + } + // No parameter error. + else + { + // Noting to do. + } + + // If all parameters are correct, ... + if ( Ok == enResult ) + { + // Get pointer to internal data structure. + pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ); + + // Check for NULL. + if ( NULL == pstcCanfdInternData ) + { + enResult = ErrorInvalidParameter; + } + } + + // If it had been prepared to initialize the CAN FD controller completely, ... + if ( Ok == enResult ) + { + // Save CAN operation mode. + pstcCanfdInternData->enCanfdMode = pstcConfig->enCanfdMode; + + // Initialize Rx confirmation method of Rx buffers and Rx FIFOs (polling). + pstcCanfdInternData->stcCanfdRxConfirmation.enRxBuffer = CanfdConfirmPolling; + pstcCanfdInternData->stcCanfdRxConfirmation.enRxFIFO0 = CanfdConfirmPolling; + pstcCanfdInternData->stcCanfdRxConfirmation.enRxFIFO1 = CanfdConfirmPolling; + pstcCanfdInternData->stcCanfdRxConfirmation.enTxBuffer = CanfdConfirmPolling; + pstcCanfdInternData->stcCanfdRxConfirmation.enBusStatus = CanfdConfirmPolling; + pstcCanfdInternData->stcCanfdRxConfirmation.enErrorStatus = CanfdConfirmPolling; + + // Set receive and transmit callback function. + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdTxInterruptFunction = pstcConfig->pfnTransmitMsgCallback; + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction = pstcConfig->pfnReceiveMsgCallback; + // Set notification callback functions + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdStatusInterruptFunction = pstcConfig->pfnStatusCallback; + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdErrorInterruptFunction = pstcConfig->pfnErrorCallback; + + // Transit CAN FD controller to initial state. + pstcCanfd->CCCR_f.INIT = PDL_ON; + while ( PDL_OFF == pstcCanfd->CCCR_f.INIT ) + { + } + + // Reset value of configuration registers and enable editing. + pstcCanfd->CCCR_f.CCE = PDL_ON; + + // Initialize basic controller settings. + pstcCanfd->CCCR_f.TXP = 0; // disable pending transmission + pstcCanfd->CCCR_f.CME = 2; // 10�Fenable full CAN FD operation (long data, flexible Rx/Tx data rate) + pstcCanfd->CCCR_f.TEST = 0; // normal operation (not in TEST mode) + pstcCanfd->CCCR_f.DAR = 0; // enable automatic retransmission + pstcCanfd->CCCR_f.MON = 0; // disable bus monitor mode + pstcCanfd->CCCR_f.CSR = 0; // disable stopping CAN FD clock + pstcCanfd->CCCR_f.ASM = 0; // not in restricted operation mode + + // Setup bit configuration parameters. + // Currently, the bit configuration is applied with constant configuration as follows; + // + // CAN, CAN FD arbitration bits and CAN FD fixed rate data bits configuration: + // 32MHz 40MHz + // Tq frequency 8MHz <- + // PropSeg+Tseg1 12Tq <- + // Tseg2 4Tq <- + // SJW 4Tq <- + // Bit rate 500kHz <- + // Sampling point 75.0% <- + // + // CAN FD flexible rate data bits configuration: + // 32MHz 40MHz + // Tq frequency 32MHz 40MHz + // PropSeg+Tseg1 6Tq 8Tq + // Tseg2 2Tq <- + // SJW 2Tq <- + // Bit rate 4MHz <- + // Sampling point 75.0% 80.0% + // + if ( CanfdClock32MHz == pstcConfig->enCanfdClock ) + { + u16BRP = (4 - 1); // CAN bit rate prescaler + u16TSEG1 = (11 - 1); // CAN Tseg1 + u16TSEG2 = (4 - 1); // CAN Tseg2 + u16SJW = (4 - 1); // CAN SJW + if ( CanfdModeFDFixed == pstcConfig->enCanfdMode ) + { + u16FBRP = (4 - 1); // CAN FD bit rate prescaler + u16TDCO = 2; // Transceiver Delay Compensation Offset + u16TDC = (0 == u16TDCO) ? 0 : 1; // Transceiver Delay Compensation enable + u16FTSEG1 = (11 - 1); // CAN FD Tseg1 + u16FTSEG2 = (4 - 1); // CAN FD Tseg2 + u16FSJW = (4 - 1); // CAN FD SJW + } + else if ( CanfdModeFDFlex == pstcConfig->enCanfdMode ) + { + u16FBRP = (1 - 1); // CAN FD bit rate prescaler + u16TDCO = 2; // Transceiver Delay Compensation Offset + u16TDC = (0 == u16TDCO) ? 0 : 1; // Transceiver Delay Compensation enable + u16FTSEG1 = (5 - 1); // CAN FD Tseg1 + u16FTSEG2 = (2 - 1); // CAN FD Tseg2 + u16FSJW = (2 - 1); // CAN FD SJW + } + } + else // if ( CanfdClock40MHz == pstcConfig->enCanfdClock ) + { + u16BRP = (5 - 1); // CAN bit rate prescaler + u16TSEG1 = (11 - 1); // CAN Tseg1 + u16TSEG2 = (4 - 1); // CAN Tseg2 + u16SJW = (4 - 1); // CAN SJW + if ( CanfdModeFDFixed == pstcConfig->enCanfdMode ) + { + u16FBRP = (5 - 1); // CAN FD bit rate prescaler + u16TDCO = 2; // Transceiver Delay Compensation Offset + u16TDC = (0 == u16TDCO) ? 0 : 1; // Transceiver Delay Compensation enable + u16FTSEG1 = (11 - 1); // CAN FD Tseg1 + u16FTSEG2 = (4 - 1); // CAN FD Tseg2 + u16FSJW = (4 - 1); // CAN FD SJW + } + else if ( CanfdModeFDFlex == pstcConfig->enCanfdMode ) + { + u16FBRP = (1 - 1); // CAN FD bit rate prescaler + u16TDCO = 2; // Transceiver Delay Compensation Offset + u16TDC = (0 == u16TDCO) ? 0 : 1; // Transceiver Delay Compensation enable + u16FTSEG1 = (7 - 1); // CAN FD Tseg1 + u16FTSEG2 = (2 - 1); // CAN FD Tseg2 + u16FSJW = (2 - 1); // CAN FD SJW + } + } + + // Setup bit configuration. + // (common parameters) + pstcCanfd->BTP_f.BRP = u16BRP; // bit rate prescaler + pstcCanfd->BTP_f.TSEG1 = u16TSEG1; // Tseg1 + pstcCanfd->BTP_f.TSEG2 = u16TSEG2; // Tseg2 + pstcCanfd->BTP_f.SJW = u16SJW; // SJW + // (CAN FD parameters) + if ( CanfdModeFDFixed == pstcConfig->enCanfdMode || CanfdModeFDFlex == pstcConfig->enCanfdMode ) + { + pstcCanfd->FBTP_f.FBRP = u16FBRP; // bit rate prescaler + pstcCanfd->FBTP_f.TDCO = u16TDCO; // Transceiver Delay Compensation Offset + pstcCanfd->FBTP_f.TDC = u16TDC; // Transceiver Delay Compensation enable + pstcCanfd->FBTP_f.FTSEG1 = u16FTSEG1; // Tseg1 + pstcCanfd->FBTP_f.FTSEG2 = u16FTSEG2; // Tseg2 + pstcCanfd->FBTP_f.FSJW = u16FSJW; // SJW + } + + // interrupt configuration. + pstcCanfd->IE = 0x00000000UL; // disable CAN FD interrupts all + pstcCanfd->ILE = 0x00000000UL; // disable CAN FD line interrupts all + pstcCanfd->ILS = 0x00000000UL; // assign all CAN FD interrupts to the interrupt line #0 + + // global filter configuration. + pstcCanfd->GFC = 0x00000000UL; + pstcCanfd->GFC_f.ANFS = 3; // discard message if its standard ID doesn't match any filters. + pstcCanfd->GFC_f.ANFE = 3; // discard message if its extended ID doesn't match any filters. + pstcCanfd->GFC_f.RRFS = 1; // discard remote frame with standard ID. + pstcCanfd->GFC_f.RRFE = 1; // discard remote frame with extended ID. + + // standard ID filter basic configuration. + pstcCanfd->SIDFC = 0x00000000UL; + pstcCanfd->SIDFC_f.LSS = 2; // number of standard ID filter. + pstcCanfd->SIDFC_f.FLSSA = 0x0000; // offset address of standard ID filter section. + + // extended ID filter basic configuration. + pstcCanfd->XIDFC = 0x00000000UL; + pstcCanfd->XIDFC_f.LSE = 0; // number of standard ID filter. + pstcCanfd->XIDFC_f.FLESA = 0x0010; // offset address of extended ID filter section. + pstcCanfd->XIDAM_f.EIDM = 0x1fffffff; // no pre-filtering + + // Rx FIFO0 basic configration. + pstcCanfd->RXF0C = 0x00000000UL; + pstcCanfd->RXF0C_f.F0OM = 0; // blocking mode. + pstcCanfd->RXF0C_f.F0WM = 0; // disable watermark interrupt. + pstcCanfd->RXF0C_f.F0S = 2; // number of elements. + pstcCanfd->RXF0C_f.F0SA = 0x0100; // offset address of Rx FIFO0 section. + + // Rx FIFO1 basic configration. + pstcCanfd->RXF1C = 0x00000000UL; + pstcCanfd->RXF1C_f.F1OM = 0; // blocking mode. + pstcCanfd->RXF1C_f.F1WM = 0; // disable watermark interrupt. + pstcCanfd->RXF1C_f.F1S = 0; // number of elements. + pstcCanfd->RXF1C_f.F1SA = 0x0200; // offset address of Rx FIFO0 section. + + // dedicated Rx buffer basic configration. + pstcCanfd->RXBC = 0x00000000UL; + pstcCanfd->RXBC_f.RBSA = 0x0300; // offset address of Rx buffer section. + + // received data size. + pstcCanfd->RXESC = 0x00000000UL; + pstcCanfd->RXESC_f.RBDS = 7; // Rx data maximum length (64bytes). + pstcCanfd->RXESC_f.F0DS = 7; // Rx FIFO0 data maximum length (64bytes). + pstcCanfd->RXESC_f.F1DS = 7; // Rx FIFO1 data maximum length (64bytes). + + // Tx FIFO/QUEUE configration. + pstcCanfd->TXEFC = 0x00000000UL; + pstcCanfd->TXEFC_f.EFWM = 0; // disable watermark interrupt. + pstcCanfd->TXEFC_f.EFS = 0; // number of elements. + pstcCanfd->TXEFC_f.EFSA = 0x0400; // offset address of Tx FIFO/QUEUE. + + // Tx buffer configration. + pstcCanfd->TXBC = 0x00000000UL; + pstcCanfd->TXBC_f.TFQM = 0; // select FIFO or QUEUE (refer to TFQS). + pstcCanfd->TXBC_f.TFQS = 0; // use Tx FIFO/QUEUE or not. + pstcCanfd->TXBC_f.NDTB = 1; // number of Tx buffer elements. + pstcCanfd->TXBC_f.TBSA = 0x0500; // offset address of Tx byffer section. + + // Tx buffer/FIFO/QUEUE configration. + pstcCanfd->TXESC = 0x00000000UL; + pstcCanfd->TXESC_f.TBDS = 7; // maximum length of Tx buffer/FIFO/QUEUE (64bytes) + + // Clear whole of message RAM (by zero). + // Note; Message RAM must be initialized by writing before accessing. Or ECC error was detected. + pu32Adrs = (uint32_t*)((uint8_t*)pstcCanfd + CANFD_MSGRAM_OFFSET); + for ( u16Count = 0; CANFD_MSGRAM_SIZEW > u16Count; u16Count++ ) + { + *pu32Adrs++ = 0UL; + } + + // Driver special configuration. + // This driver accepts messages only that has identifier 0x100 or 0x200. + // The message that has ID 0x100 is stored into dedicated Rx buffer #0, and it is obtained by interrupt. + // The message that has ID 0x200 is stored into Rx FIFO0, and it is obtained by polling. + + // Clear transmission request marker all. + CanfdClearTxRequestMarker( pstcCanfd ); + + // Rx message confiramtion method (interrupt). + pstcCanfdInternData->stcCanfdRxConfirmation.enRxBuffer = CanfdConfirmInterrupt; + // [andreika]: fix TX buffer interrupts + pstcCanfdInternData->stcCanfdRxConfirmation.enTxBuffer = CanfdConfirmInterrupt; + + // Setup ID filters. + // [andreika]: todo: the following should be controlled externally! + + // (standard ID : message #0) + stcCanfdStdID.w = 0UL; + stcCanfdStdID.sft = 2; // filter typr : classic (ignored, see SFEC) + stcCanfdStdID.sfec = 7; // stored to : dedicated Rx buffer or debug message + stcCanfdStdID.sfid1 = 0x100; // ID : 0x100 + stcCanfdStdID.sfid2 = (0 << 9) // storage detail : dedicated Rx buffer, index 0 + | 0; + pu32Adrs = (uint32_t*)CanfdCalcStdIdFilterAddress( pstcCanfd, 0 ); + pu32Adrs[0] = stcCanfdStdID.w; + + // (standard ID : message #1) + stcCanfdStdID.w = 0UL; + stcCanfdStdID.sft = 2; // filter typr : classic + stcCanfdStdID.sfec = 1; // stored to : Rx FIFO0 + stcCanfdStdID.sfid1 = 0x200; // ID : 0x200 + stcCanfdStdID.sfid2 = 0x7FF; // MASK : 0x7FF (accept 0x200 only) + pu32Adrs = (uint32_t*)CanfdCalcStdIdFilterAddress( pstcCanfd, 1 ); + pu32Adrs[0] = stcCanfdStdID.w; + + // Initialize CAN FD related interrupt. + CanfdInitInterrupt(pstcCanfd); + } + + // Return result. + return enResult; +} // Canfd_Init + +/** + ***************************************************************************** + ** \brief Deinitializes the CAN FD module. + ** Any pending transmission or receiption will be aborted and all CAN FD related + ** registers are reset to their default values. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok CAN FD module has been successfully deinitialized. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - pstcCanfdInternData == NULL (invalid or disabled CAN FD unit + ** (PDL_PERIPHERAL_ENABLE_CANFD)) + *****************************************************************************/ +en_result_t Canfd_DeInit( volatile stc_canfdn_t* pstcCanfd ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; // Pointer to internal data + en_result_t enResult; + + // Check for NULL pointer. + if ( NULL == pstcCanfd ) + { + enResult = ErrorInvalidParameter; + } + // Get pointer to internal data structure. + else if ( NULL == ( pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ) ) ) + { + enResult = ErrorInvalidParameter; + } + // If it had been prepared to initialize, ... + else + { + // Transit CAN FD controller to initial state. + pstcCanfd->CCCR_f.INIT = PDL_ON; + while ( PDL_OFF == pstcCanfd->CCCR_f.INIT ) + { + } + + // Deinitialize CAN FD related interrupt. + CanfdDeInitInterrupt(pstcCanfd); + + // Reset value of configuration registers and enable editing. + pstcCanfd->CCCR_f.CCE = PDL_ON; + + // Set initial value to all registers included to the CAN FD controller. + pstcCanfd->CCCR &= ~0x00000003UL; // CCR (initialize except for INIT and CCE) + // CREL (read only) + // ENDN (read only) + // CUST (not present) + pstcCanfd->FBTP = 0x00000A33UL; // FBTP + pstcCanfd->TEST = 0x00000000UL; // TEST + pstcCanfd->RWD = 0x00000000UL; // RWD + pstcCanfd->BTP = 0x00000A33UL; // BTP + pstcCanfd->TSCC = 0x00000000UL; // TSCC + pstcCanfd->TSCV = 0x00000000UL; // TSCV + pstcCanfd->TOCC = 0x00000000UL; // TOCC + pstcCanfd->TOCV = 0x00000000UL; // TOCV + // ECR (read only) + // PSR (read only) + pstcCanfd->IE = 0x00000000UL; // IE (initialize before IR) + pstcCanfd->IR = 0xFFFFFFFFUL; // IR (write '1' to clear) + pstcCanfd->ILS = 0x00000000UL; // ILS + pstcCanfd->ILE = 0x00000000UL; // ILE + pstcCanfd->GFC = 0x00000000UL; // GFC + pstcCanfd->SIDFC = 0x00000000UL; // SIDFC + pstcCanfd->XIDFC = 0x00000000UL; // XIDFC + pstcCanfd->XIDAM = 0x1FFFFFFFUL; // XIDAM + // HPMS (read only) + pstcCanfd->NDAT1 = 0xFFFFFFFFUL; // NDAT1 (write '1' to clear) + pstcCanfd->NDAT2 = 0xFFFFFFFFUL; // NDAT2 (write '1' to clear) + pstcCanfd->RXF0C = 0x00000000UL; // RXF0C + // RXF0S (read only) + // RXF0A (to write to this affects other registers) + pstcCanfd->RXBC = 0x00000000UL; // RXBC + pstcCanfd->RXF1C = 0x00000000UL; // RXF1C + // RXF1S (read only) + // RXF1A (to write to this affects other registers) + pstcCanfd->RXESC = 0x00000000UL; // RXESC + pstcCanfd->TXBC = 0x00000000UL; // TXBC + // TXFQS (read only) + pstcCanfd->TXESC = 0x00000000UL; // TXESC + // TXBRP (read only) + // TXBAR (to write to this triggers the function) + // TXBCR (to write to this triggers the function) + // TXBTO (read only) + // TXBCF (read only) + pstcCanfd->TXBTIE = 0x00000000UL; // TXBTIE + pstcCanfd->TXBCIE = 0x00000000UL; // TXBCIE + pstcCanfd->TXEFC = 0x00000000UL; // TXEFC + // TXEFS (read only) + // TXEFA (to write to this affects other registers) + pstcCanfd->FDECR = 0x00UL; // FDECR + // FDESR (read only) + // FDSEAR (read only) + // FDESCR (to write to this affects other registers) + // FDDEAR (read only) + + // Disable access to any configuration registers. + pstcCanfd->CCCR_f.CCE = PDL_OFF; + + // Reset receive and transmit callback function. + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdTxInterruptFunction = NULL; + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction = NULL; + + // Reset notification callback functions + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdStatusInterruptFunction = NULL; + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdErrorInterruptFunction = NULL; + + // Clear transmission request marker all. + CanfdClearTxRequestMarker( pstcCanfd ); + + // Set 'Ok' to result. + enResult = Ok; + } + + // Return result + return enResult; +} // Canfd_DeInit + +/** + ***************************************************************************** + ** \brief Start communication. + ** Start (enable) CAN communication. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok CAN FD module has been successfully started. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - pstcCanfdInternData == NULL + *****************************************************************************/ +en_result_t Canfd_Start( volatile stc_canfdn_t* pstcCanfd ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; // Pointer to internal data + uint32_t u32ActiveInt; + en_result_t enResult; + + // Check for NULL pointer. + if ( NULL == pstcCanfd ) + { + enResult = ErrorInvalidParameter; + } + // Get pointer to internal data structure. + else if ( NULL == ( pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ) ) ) + { + enResult = ErrorInvalidParameter; + } + // Start communication. + else + { + // Leave from initial state. + pstcCanfd->CCCR_f.INIT = PDL_OFF; + while ( PDL_ON == pstcCanfd->CCCR_f.INIT ) + { + } + + // Change CAN operation mode to desired one. + // (classic CAN (CAN2.0)) + if ( CanfdModeClassic == pstcCanfdInternData->enCanfdMode ) + { + // 11�FISO11898-1 standard operation. + pstcCanfd->CCCR_f.CMR = 3; + } + // (CAN FD with fixed data rate) + else if ( CanfdModeFDFixed == pstcCanfdInternData->enCanfdMode ) + { + // 01�FCAN FD (fixed data rate) operation. + pstcCanfd->CCCR_f.CMR = 1; + } + // (CAN FD with flexible data rate) + else if ( CanfdModeFDFlex == pstcCanfdInternData->enCanfdMode ) + { + // 10�FCAN FD (flexible data rate) operation. + pstcCanfd->CCCR_f.CMR = 2; + } + // (others (invalid parameters)) + else + { + // 11�FISO11898-1 standard operation. + pstcCanfd->CCCR_f.CMR = 3; + } + // (Wait until the operation mode is changed to specified mode) + while ( 0 != pstcCanfd->CCCR_f.CMR ) + { + } + + // Enable CAN FD interrupts. + u32ActiveInt = ( ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enRxBuffer ) ? CANFD_IR_MASK_RXBUF : 0UL ) + | ( ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enRxFIFO0 ) ? CANFD_IR_MASK_RXFIFO0 : 0UL ) + | ( ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enRxFIFO1 ) ? CANFD_IR_MASK_RXFIFO1 : 0UL ) + | ( ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enTxBuffer ) ? CANFD_IR_MASK_TX : 0UL ) + | ( ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enBusStatus ) ? CANFD_IR_MASK_STATUS : 0UL ) + | ( ( CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enErrorStatus ) ? CANFD_IR_MASK_ERROR : 0UL ); + pstcCanfd->IE = u32ActiveInt; // enable CAN interrupts + pstcCanfd->ILE = 0x00000001UL; // enable CAN line 0 interrupts + + // [andreika]: fix TX interrupts + if (CanfdConfirmInterrupt == pstcCanfdInternData->stcCanfdRxConfirmation.enTxBuffer) { + pstcCanfd->TXBTIE = 0xffffffffUL; // Tx Buffer Transmission Interrupt Enable + pstcCanfd->TXBCIE = 0xffffffffUL; // Tx Buffer Cancellation Finished Interrupt Enable (TXBCIE) + } + + // Set 'Ok' to result. + enResult = Ok; + } + + // Return result. + return enResult; +} // Canfd_Start + +/** + ***************************************************************************** + ** \brief Stop communication. + ** Stop (disable) CAN communication. + ** Any pending transmission or receiption will be aborted and all CAN FD statuses + ** are reset (cleared). + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok CAN FD module has been successfully stopped. + ** \retval ErrorInvalidParameter If following condition is met: + ** - pstcCanfd == NULL + *****************************************************************************/ +en_result_t Canfd_Stop( volatile stc_canfdn_t* pstcCanfd ) +{ + en_result_t enResult; + + // Check for NULL pointer. + if ( NULL == pstcCanfd ) + { + enResult = ErrorInvalidParameter; + } + // Stop communication. + else + { + // Transit CAN FD controller to initial state. + pstcCanfd->CCCR_f.INIT = PDL_ON; + while ( PDL_OFF == pstcCanfd->CCCR_f.INIT ) + { + } + + // Set CCE to clear current status and to prepare to restart correctly. + pstcCanfd->CCCR_f.CCE = PDL_ON; + + // Clear ASM to leave from the restricted operation mode if CAN FD controller was in that mode. + pstcCanfd->CCCR_f.ASM = PDL_OFF; + + // disable CAN FD interrupts. + pstcCanfd->IE = 0x00000000UL; // disable CAN FD interrupts all + pstcCanfd->ILE = 0x00000000UL; // disable CAN FD line interrupts all + + // Set 'Ok' to result. + enResult = Ok; + } + + // Return result. + return enResult; +} // Canfd_Stop + +/** + ***************************************************************************** + ** \brief Restart communication. + ** Restart CAN communication. + ** This funnction stops and starts communication. + ** Any pending transmission or receiption will be aborted and all CAN FD statuses + ** are reset (cleared) in the stop process. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok CAN FD module has been successfully restarted. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL (Canfd_Stop) + ** - pstcCanfdInternData == NULL (Canfd_Start) + *****************************************************************************/ +en_result_t Canfd_Restart( volatile stc_canfdn_t* pstcCanfd ) +{ + en_result_t enResult; + + // Stop communication. + enResult = Canfd_Stop( pstcCanfd ); + + // If communication was stopped successfully, ... + if ( Ok == enResult ) + { + // Clear interrupt flags and new data arrival flags all. + pstcCanfd->IR = 0xFFFFFFFFUL; // IR (write '1' to clear) + pstcCanfd->NDAT1 = 0xFFFFFFFFUL; // NDAT1 (write '1' to clear) + pstcCanfd->NDAT2 = 0xFFFFFFFFUL; // NDAT2 (write '1' to clear) + + // Clear transmission request marker all. + CanfdClearTxRequestMarker( pstcCanfd ); + + // (Re)Start communication. + enResult = Canfd_Start( pstcCanfd ); + } + + // Return result + return enResult; +} // Canfd_Restart + +/** + ***************************************************************************** + ** \brief Configures a message buffer for transmission. + ** Setting of new values is not possible if a transmission is pending. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] u8MsgBuf Message buffer index (0 .. CANFD_MESSAGE_TXBUFFER_COUNT - 1) + ** \param [in] pstcMsg CAN message to be transmitted. + ** + ** \retval Ok Transmission request has been successfully accepted. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - u8MsgBuf out of range + ** - pstcMsg == NULL + ** - pstcCanfdInternData == NULL (invalid or disabled CAN FD unit (PDL_PERIPHERAL_ENABLE_CANFD)) + ** \retval ErrorOperationInProgress If following condition is met: + ** - A transmission is pending. + *****************************************************************************/ +en_result_t Canfd_TransmitMsg( volatile stc_canfdn_t* pstcCanfd, + uint8_t u8MsgBuf, + stc_canfd_msg_t* pstcMsg + ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; // Pointer to internal data + stc_canfd_tx_buffer_t* pstcTxBuffer; + uint8_t u8DataSize; + uint8_t u8Count; + en_result_t enResult; + + // Initialize result value (as 'Ok') + enResult = Ok; + + // Check parameters. + if ( NULL == pstcCanfd || + CANFD_MESSAGE_TXBUFFER_COUNT <= u8MsgBuf || + NULL == pstcMsg + ) + { + enResult = ErrorInvalidParameter; + } + // Get pointer to internal data structure. + else if ( NULL == ( pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ) ) ) + { + enResult = ErrorInvalidParameter; + } + // Check whether the target Tx buffer is ready to accept new request. + else if ( 0UL != ( pstcCanfd->TXBRP & (1UL << u8MsgBuf) ) ) + { + enResult = ErrorOperationInProgress; + } + // If all parameters are correct and Tx buffer is ready to accept new transmission request, ... + else + { + // Get Tx Buffer address + pstcTxBuffer = CanfdCalcTxBufferAddress( pstcCanfd, u8MsgBuf ); + + // If obtained Tx buffer address is invalid, set error to result. + if ( NULL == pstcTxBuffer ) + { + enResult = Error; + } + // Otherwise, ... + else + { + // Set marker. + pstcCanfdInternData->u8TxReqMarker[u8MsgBuf] = CANFD_TX_REQUESTED; + + // Set message attributes to Tx buffer. + pstcTxBuffer->rtr = 0; + pstcTxBuffer->xtd = ( TRUE == pstcMsg->stcIdentifier.bExtended ) ? 1 : 0; + pstcTxBuffer->id = ( 0 == pstcTxBuffer->xtd ) ? ( pstcMsg->stcIdentifier.u32Identifier << 18 ) + : pstcMsg->stcIdentifier.u32Identifier; + pstcTxBuffer->efc = 0; + pstcTxBuffer->mm = 0; + pstcTxBuffer->dlc = pstcMsg->stcData.u8DataLengthCode; + + // Convert the DLC to word size. + u8DataSize = u8DlcInByte[pstcTxBuffer->dlc]; + if ( CanfdModeClassic == pstcCanfdInternData->enCanfdMode && + CANFD_MAX_STDDLC < u8DataSize ) + { + u8DataSize = CANFD_MAX_STDDLC; + } + u8DataSize = ( u8DataSize + 3 ) >> 2; + + // Copy data to Tx buffer. + for ( u8Count = 0; u8Count < u8DataSize; u8Count++ ) + { + pstcTxBuffer->data[u8Count] = pstcMsg->stcData.au32Data[u8Count]; + } + + // Request to transmit + pstcCanfd->TXBAR |= ( 1UL << u8MsgBuf ); + } + } + + // Return result. + return enResult; +} + +/** + ***************************************************************************** + ** \brief Get all received messages by polling. + ** Check and notify all received messages by polling. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok Message buffer for reception has been succesfully set. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - pstcCanfdInternData == NULL (invalid or disabled CAN FD unit (PDL_PERIPHERAL_ENABLE_CANFD)) + *****************************************************************************/ +en_result_t Canfd_ReceiveMsg( volatile stc_canfdn_t* pstcCanfd ) +{ + uint32_t u32Accepted; + en_result_t enResult; + + // Check and notify received messages by polling. + enResult = CanfdCheckAndNotifyRxMsg( pstcCanfd, CanfdConfirmPolling, &u32Accepted ); + + // If process was done successfully, ... + if ( Ok == enResult ) + { + // Clear Rx FIFO1 new data interrupt bit. + pstcCanfd->IR = u32Accepted; + } + + // Return result. + return enResult; +} + +/** + ***************************************************************************** + ** \brief Get current bus status. + ** + ** Calculate the top of address of standard ID filter element that is + ** corresponding to specified index. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok Process succeeded. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - pstcCanfdInternData == NULL + *****************************************************************************/ +en_result_t Canfd_GetBusStatus( volatile stc_canfdn_t* pstcCanfd ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; // Pointer to internal data + en_result_t enResult; + + // Check parameters; if parameter error was detected, ... + if ( NULL == pstcCanfd ) + { + // Invalid parameter. + enResult = ErrorInvalidParameter; + } + // Otherwise, ... + else + { + // Get pointer to internal data structure. + pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ); + + // If the internal data pointer was gotten, ... + if ( NULL != pstcCanfdInternData ) + { + // Notify current bus status by calling user hook function if it is available. + if ( NULL != pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdStatusInterruptFunction ) + { + // Check and notify current bus status by calling user hook function. + if ( PDL_ON == pstcCanfd->IR_f.BO ) + { + // BusOff status. + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdStatusInterruptFunction(CanfdBusOff); + } + else if ( PDL_ON == pstcCanfd->IR_f.EW ) + { + // ErrorWarning status. + pstcCanfdInternData->stcCanfdNotificationCb.pfnCanfdStatusInterruptFunction(CanfdWarning); + } + else + { + // Do nothing. + } + } + + // Finish process successfully. + enResult = Ok; + } + // Otherwise, ... + else + { + // Invalid parameter. + enResult = ErrorInvalidParameter; + } + + // Clear bus status related bits in IR. + pstcCanfd->IR = CANFD_IR_MASK_STATUS; + } + + // Return result + return enResult; +} + + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Check and notify received messages. + ** + ** Check and notify received messages via Rx buffer, FIFO0 and FIFO1. + ** The target is the object that its confirmation method is same as the + ** parameter 'enMethod'. + ** Note that the value of the parameter 'pstcCanfd' is not checked. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] enMethod Confirmation method. + ** \param [in] pu32Accepted Address to store flags that were accepted in this function. + ** + ** \retval Ok Process was done successfully. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfdInternData == NULL + ** - pu32Accepted == NULL + *****************************************************************************/ +static en_result_t CanfdCheckAndNotifyRxMsg( volatile stc_canfdn_t* pstcCanfd, + en_canfd_confirmation_method_t enMethod, + uint32_t* pu32Accepted ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; + uint8_t u8MsgNumber; + stc_canfd_rx_buffer_t* pstcRxBuffer; + stc_canfd_rx_buffer_t stcRxBufTemp; + union { + uint32_t IR; + stc_canfd_ir_field_t IR_f; + } unCanfdIrRegister; + uint32_t u32ND1; + uint32_t u32ND2; + uint32_t u32NDMask; + stc_canfd_msg_t stcRxMsg; + uint32_t u32AccInt; + en_result_t enResult; + + // Get pointer to internal data structure. + pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ); + + // Return immediately when specified CAN FD base address could not be recognized. + if ( NULL == pstcCanfdInternData || + NULL == pu32Accepted ) + { + enResult = ErrorInvalidParameter; + } + // Otherwise, ... + else + { + // Get interrupt flag register. + unCanfdIrRegister.IR = pstcCanfd->IR; + + // Clear accepted interrupt flags. + u32AccInt = 0UL; + + // If some messages were received and stored into dedicated Rx buffer, ... + if ( enMethod == pstcCanfdInternData->stcCanfdRxConfirmation.enRxBuffer && + 0 != unCanfdIrRegister.IR_f.DRX ) + { + // Get new data arrived flags. + u32ND1 = pstcCanfd->NDAT1; + u32ND2 = pstcCanfd->NDAT2; + + // Check dedicated Rx buffer #0 to #31. + for ( u8MsgNumber = 0, u32NDMask = 1UL; 0UL != u32NDMask; u8MsgNumber++, u32NDMask <<= 1 ) + { + // Check one buffer + if ( 0UL != ( u32ND1 & u32NDMask ) ) + { + // If reception event collback is available, ... + if ( NULL != pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction ) + { + // Get address of target message. + pstcRxBuffer = CanfdCalcRxBufferAddress( pstcCanfd, u8MsgNumber ); + // Convert raw Rx buffer content to common CAN message content. + CanfdConvRxBuffer( pstcRxBuffer, &stcRxMsg ); + // Notify message reception event. + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction( u8MsgNumber, &stcRxMsg ); + } + + // Clear new data bit. + pstcCanfd->NDAT1 |= u32NDMask; + } + } + + // Check dedicated Rx buffer #32 to #63. + for ( u32NDMask = 1UL; 0UL != u32NDMask; u8MsgNumber++, u32NDMask <<= 1 ) + { + // Check one buffer. + if ( 0UL != ( u32ND2 & u32NDMask ) ) + { + // If reception event collback is available, ... + if ( NULL != pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction ) + { + // Get address of target message. + pstcRxBuffer = CanfdCalcRxBufferAddress( pstcCanfd, u8MsgNumber ); + // Convert raw Rx buffer content to common CAN message content. + CanfdConvRxBuffer( pstcRxBuffer, &stcRxMsg ); + // Notify message reception event. + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction( u8MsgNumber, &stcRxMsg ); + } + + // Clear new data bit. + pstcCanfd->NDAT2 |= u32NDMask; + } + } + + // Set accepted flag to clear dedicated Rx biffer new data bit. + u32AccInt |= CANFD_IR_MASK_RXBUF; + } + + // Check and notify Rx FIFO0 messages. + if ( enMethod == pstcCanfdInternData->stcCanfdRxConfirmation.enRxFIFO0 && + 0 != unCanfdIrRegister.IR_f.RF0N ) + { + // If reception event collback is available, ... + if ( NULL != pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction ) + { + // Get all received messages. + while ( Ok == CanfdGetRxFIFO( pstcCanfd, CanfdRxFIFO0, &stcRxBufTemp ) ) + { + // Convert raw Rx FIFO content to common CAN message content. + CanfdConvRxBuffer( &stcRxBufTemp, &stcRxMsg ); + // Notify message reception event. + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction( CANFD_MSGIDX_FIFO0, &stcRxMsg ); + } + } + + // Set accepted flag to clear Rx FIFO0 new data interrupt bit. + u32AccInt |= CANFD_IR_MASK_RXFIFO0; + } + + // Check and notify Rx FIFO1 messages. + if ( enMethod == pstcCanfdInternData->stcCanfdRxConfirmation.enRxFIFO1 && + 0 != unCanfdIrRegister.IR_f.RF1N ) + { + // If reception event collback is available, ... + if ( NULL != pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction ) + { + // Get all received messages. + while ( Ok == CanfdGetRxFIFO( pstcCanfd, CanfdRxFIFO1, &stcRxBufTemp ) ) + { + // Convert raw Rx FIFO content to common CAN message content. + CanfdConvRxBuffer( &stcRxBufTemp, &stcRxMsg ); + // Notify message reception event. + pstcCanfdInternData->stcCanfdInterruptHandling.pfnCanfdRxInterruptFunction( CANFD_MSGIDX_FIFO1, &stcRxMsg ); + } + } + + // Set accepted flag to clear Rx FIFO1 new data interrupt bit. + u32AccInt |= CANFD_IR_MASK_RXFIFO1; + } + + // Store value of accepted flags to specified address. + *pu32Accepted = u32AccInt; + + // Set result : Ok. + enResult = Ok; + } + + // Return result. + return enResult; +} + +/** + ***************************************************************************** + ** \brief Calculate address of the element of specified standard ID filter. + ** + ** Calculate the top of address of standard ID filter element that is + ** corresponding to specified index. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] u8Index Standard ID filter index. + ** + ** \retval NULL Invalid parameter(s). + ** \retval not NULL Address of specified filter element + *****************************************************************************/ +static stc_canfd_stdid_filter_t* CanfdCalcStdIdFilterAddress( volatile stc_canfdn_t* pstcCanfd, + uint8_t u8Index ) +{ + stc_canfd_stdid_filter_t* pstcFilter; + + // Check parameters; if parameter error was detected, ... + if ( NULL == pstcCanfd ) + { + pstcFilter = NULL; + } + // Otherwise, ... + else + { + // Calculate address of specified standard ID element. + pstcFilter = (stc_canfd_stdid_filter_t*)((uint8_t*)pstcCanfd + CANFD_MSGRAM_OFFSET + + ((pstcCanfd->SIDFC_f.FLSSA + CANFD_STDID_INFOSIZE * u8Index) << 2)); + } + + // Return result + return pstcFilter; +} // CanfdCalcStdIdFilterAddress + +/** + ***************************************************************************** + ** \brief Calculate address of the element of specified extended ID filter. + ** + ** Calculate the top of address of exended ID filter element that is + ** corresponding to specified index. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] u8Index Extended ID filter index. + ** + ** \retval NULL Invalid parameter(s). + ** \retval not NULL Address of specified filter element + *****************************************************************************/ +static stc_canfd_extid_filter_t* CanfdCalcExtIdFilterAddress( volatile stc_canfdn_t* pstcCanfd, + uint8_t u8Index ) +{ + stc_canfd_extid_filter_t* pstcFilter; + + // Check parameters; if parameter error was detected, ... + if ( NULL == pstcCanfd ) + { + pstcFilter = NULL; + } + // Otherwise, ... + else + { + // Calculate address of specified extended ID element. + pstcFilter = (stc_canfd_extid_filter_t*)((uint8_t*)pstcCanfd + CANFD_MSGRAM_OFFSET + + ((pstcCanfd->XIDFC_f.FLESA + CANFD_EXTID_INFOSIZE * u8Index) << 2)); + } + + // Return result + return pstcFilter; +} // CanfdCalcExtIdFilterAddress + +/** + ***************************************************************************** + ** \brief Calculate address of the element of specified dedicated Rx Buffer. + ** + ** Calculate the top of address of dedicated Rx buffer element that is + ** corresponding to specified index. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] u8Index Rx buffer index. + ** + ** \retval NULL Invalid parameter(s). + ** \retval not NULL Address of specified Rx buffer element + *****************************************************************************/ +static stc_canfd_rx_buffer_t* CanfdCalcRxBufferAddress( volatile stc_canfdn_t* pstcCanfd, + uint8_t u8Index ) +{ + stc_canfd_rx_buffer_t* pstcRxBuf; + uint8_t u8RBDS; + + // Check parameters; if parameter error was detected, ... + if ( NULL == pstcCanfd ) + { + pstcRxBuf = NULL; + } + // Otherwise, ... + else + { + // Calculate address of specified Rx buffer. + u8RBDS = pstcCanfd->RXESC_f.RBDS; + pstcRxBuf = (stc_canfd_rx_buffer_t*)((uint8_t*)pstcCanfd + CANFD_MSGRAM_OFFSET + + ((pstcCanfd->RXBC_f.RBSA + + (CANFD_RXBUF_INFOSIZE + u8BufSizeInWord[u8RBDS]) * u8Index) << 2)); + } + + // Return result. + return pstcRxBuf; +} // CanfdCalcRxBufferAddress + +/** + ***************************************************************************** + ** \brief Get one received message from specified Rx FIFO. + ** + ** Get one received message from specified Rx FIFO. + ** The 'GetIndex' is updated by this process if it was done successfully. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] enNumber Rx FIFO number (FIFO0/1). + ** \param [in] pstcRxBuffer Address of Rx (FIFO) buffer element. + ** + ** \retval Ok Get Rx FIFO message succesfully. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfdInternData == NULL + ** - enNumber out of range + ** - pstcRxBuffer == NULL + ** \retval Error FIFO is not available or has no message. + *****************************************************************************/ +static en_result_t CanfdGetRxFIFO( volatile stc_canfdn_t* pstcCanfd, + en_canfd_rxfifo_number_t enNumber, + stc_canfd_rx_buffer_t* pstcRxBuffer ) +{ + union { + uint32_t RXFC; + stc_canfd_rxf0c_field_t RXFC_f; + } unRXFC; + union { + uint32_t RXFS; + stc_canfd_rxf0s_field_t RXFS_f; + } unRXFS; + stc_canfd_rx_buffer_t* pstcMsg; + uint8_t u8Size; + uint8_t u8Idx; + en_result_t enResult; + uint8_t F0GI; + uint8_t F0PI; + + // Check parameters; if parameter error was detected, ... + if ( NULL == pstcCanfd || + ( CanfdRxFIFO0 != enNumber && CanfdRxFIFO1 != enNumber ) || + NULL== pstcRxBuffer ) + { + enResult = ErrorInvalidParameter; + } + // Otherwise, ... + else + { + // Get specified FIFO information. + if ( CanfdRxFIFO0 == enNumber ) + { + // Rx FIFO0 information + unRXFC.RXFC = pstcCanfd->RXF0C; + unRXFS.RXFS = pstcCanfd->RXF0S; + u8Size = u8BufSizeInWord[pstcCanfd->RXESC_f.F0DS]; + } + else + { + // Rx FIFO1 information + unRXFC.RXFC = pstcCanfd->RXF1C; + unRXFS.RXFS = pstcCanfd->RXF1S; + u8Size = u8BufSizeInWord[pstcCanfd->RXESC_f.F1DS]; + } + + // If FIFO is not active or has no message, ... + F0GI = unRXFS.RXFS_f.F0GI; + F0PI = unRXFS.RXFS_f.F0PI; + if ((0 == unRXFC.RXFC_f.F0S) || + ((PDL_OFF == unRXFS.RXFS_f.F0F) && (F0GI == F0PI))) + {// + enResult = Error; + } + // Otherwise, ... + else + { + // Get a message at the top of the FIFO. + // (Calculate element address) + pstcMsg = (stc_canfd_rx_buffer_t*)((uint8_t*)pstcCanfd + + CANFD_MSGRAM_OFFSET + + ((unRXFC.RXFC_f.F0SA + (CANFD_RXBUF_INFOSIZE + u8Size) * F0GI) << 2)); + + // (Get message information header) + pstcRxBuffer->w[0] = pstcMsg->w[0]; + pstcRxBuffer->w[1] = pstcMsg->w[1]; + // (Get message data) + for ( u8Idx = 0; u8Idx < u8Size; u8Idx++ ) + { + pstcRxBuffer->data[u8Idx] = pstcMsg->data[u8Idx]; + } + + // Acknowledge a message. + if ( CanfdRxFIFO0 == enNumber ) + { + pstcCanfd->RXF0A_f.F0AI = unRXFS.RXFS_f.F0GI; + } + else + { + pstcCanfd->RXF1A_f.F1AI = unRXFS.RXFS_f.F0GI; + } + + // Finish process successfully. + enResult = Ok; + } + } + + // Return result. + return enResult; +} // CanfdGetRxFIFO + +/** + ***************************************************************************** + ** \brief Convert MCAN Rx buffer to driver message. + ** + ** Convert contents of MCAN Rx buffer on the message RAM to the driver defined + ** message structure. + ** + ** \param [in] pstcRxBuffer Pointer to Rx buffer/FIFO element + ** \param [in] pstcRxMsg Pointer to message structure + ** + ** \retval Ok Done conversion successfully. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcRxBuffer == NULL + ** - pstcRxMsg == NULL + ** + ** Note: This function premises that the byte order is 'little endian'. + *****************************************************************************/ +static en_result_t CanfdConvRxBuffer( stc_canfd_rx_buffer_t* pstcRxBuffer, + stc_canfd_msg_t* pstcRxMsg ) +{ + uint8_t u8DataSize; + uint8_t u8Count; + uint32_t u32Data; + en_result_t enResult; + + // Check parameters. + if ( NULL == pstcRxBuffer || NULL == pstcRxMsg ) + { + enResult = ErrorInvalidParameter; + } + // If all parameters are valid, ... + else + { + // XTD : Extended Identifier. + pstcRxMsg->stcIdentifier.bExtended = pstcRxBuffer->xtd; + + // ID : RxID. + if ( 0 == pstcRxMsg->stcIdentifier.bExtended ) + { + pstcRxMsg->stcIdentifier.u32Identifier = pstcRxBuffer->id >> 18; + } + else + { + pstcRxMsg->stcIdentifier.u32Identifier = pstcRxBuffer->id; + } + + // EDL : Extended Data Length. + pstcRxMsg->bCanfd = ( 0 == pstcRxBuffer->edl ) ? FALSE : TRUE; + + // DLC : Data Length Code. + pstcRxMsg->stcData.u8DataLengthCode = pstcRxBuffer->dlc; + + // Copy 0-64 byte of data area. + u8DataSize = u8DlcInByte[pstcRxMsg->stcData.u8DataLengthCode]; + + if ( FALSE == pstcRxMsg->bCanfd && CANFD_MAX_STDDLC < u8DataSize ) + { + u8DataSize = CANFD_MAX_STDDLC; + } + for ( u8Count = 0; 4 <= u8DataSize; u8Count++, u8DataSize -= 4 ) + { + pstcRxMsg->stcData.au32Data[u8Count] = pstcRxBuffer->data[u8Count]; + } + if ( 0 < u8DataSize ) + { + u32Data = pstcRxBuffer->data[u8Count]; + for ( u8Count *= 4; 0 < u8DataSize; u8Count++, u8DataSize-- ) + { + pstcRxMsg->stcData.au8Data[u8Count] = (uint8_t)u32Data; + u32Data >>= 8; + } + } + + // Set 'Ok' to result. + enResult = Ok; + } + + // Return result. + return enResult; +} + + +/** + ***************************************************************************** + ** \brief Calculate address of the element of specified Tx Buffer. + ** + ** Calculate the top of address of Tx buffer element that is corresponding + ** to specified index. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** \param [in] u8Index Tx buffer index. + ** + ** \retval NULL Invalid parameter(s). + ** \retval not NULL Address of specified Tx buffer element + *****************************************************************************/ +static stc_canfd_tx_buffer_t* CanfdCalcTxBufferAddress( volatile stc_canfdn_t* pstcCanfd, + uint8_t u8Index ) +{ + stc_canfd_tx_buffer_t* pstcTxBuf; + uint8_t u8TBDS; + + // Check parameters; if parameter error was detected, ... + if ( NULL == pstcCanfd ) + { + pstcTxBuf = NULL; + } + // Otherwise, ... + else + { + // Calculate address of specified Tx buffer. + u8TBDS = pstcCanfd->TXESC_f.TBDS; + pstcTxBuf = (stc_canfd_tx_buffer_t*)((uint8_t*)pstcCanfd + CANFD_MSGRAM_OFFSET + + ((pstcCanfd->TXBC_f.TBSA + + (CANFD_TXBUF_INFOSIZE + u8BufSizeInWord[u8TBDS]) * u8Index) << 2)); + } + + // Return result. + return pstcTxBuf; +} // CanfdCalcTxBufferAddress + + +/** + ***************************************************************************** + ** \brief Clear transmission request marker. + ** + ** Clear transmission request marker of all Tx buffers. + ** Transmission request marker holds in the MM field of Tx buffer. + ** + ** \param [in] pstcCanfd Pointer to register area of a CAN FD unit. + ** + ** \retval Ok Done process successfully. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcCanfd == NULL + ** - pstcCanfdInternData == NULL + *****************************************************************************/ +static en_result_t CanfdClearTxRequestMarker( volatile stc_canfdn_t* pstcCanfd ) +{ + stc_canfd_intern_data_t* pstcCanfdInternData; // Pointer to internal data + uint8_t u8Num; + en_result_t enResult; + + // Check parameter. + if ( NULL == pstcCanfd ) + { + enResult = ErrorInvalidParameter; + } + // Get pointer to internal data structure. + else if ( NULL == ( pstcCanfdInternData = CanfdGetInternDataPtr( pstcCanfd ) ) ) + { + enResult = ErrorInvalidParameter; + } + // If parameter is valid, ... + else + { + // Loop to clear all markers. + for ( u8Num = 0; CANFD_MESSAGE_TXBUFFER_COUNT > u8Num; u8Num++ ) + { + // Clear marker. + pstcCanfdInternData->u8TxReqMarker[u8Num] = CANFD_TX_NOT_REQUESTED; + } + + // Set 'Ok' to result. + enResult = Ok; + } + + //Return result. + return enResult; +} + +#endif + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.h new file mode 100644 index 0000000000..b87421ff4b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/can/canfd.h @@ -0,0 +1,436 @@ +/****************************************************************************** +* \file canfd.h +* +* \version 1.20 +* +* \brief Header file for Controller Area Network with Flexible Data Rate(CANFD) functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __CANFD_H__ +#define __CANFD_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_CANFD_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupCANFD Controller Area Network with Flexible Data Rate(CANFD) +* \{ +* \defgroup GroupCANFD_Macros Macros +* \defgroup GroupCANFD_Functions Functions +* \defgroup GroupCANFD_DataStructures Data Structures +* \defgroup GroupCANFD_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupCANFD +* \{ +* Controller Area Network (CAN) is widely used in various industries +* such as automobile and factory automation. CAN with Flexible Data Rate(CANFD) +* complies with ISO11898-1 (CAN specification +* Rev. 2.0 part A, B) and with CAN FD specification V1.0 (Bosch CAN FD +* Specification V1.0). It doesn't comply with ISO11898-1 +* (CAN FD specification).
+* +* You can configure the CAN FD Controller to support 8-, 16-, and 32-bit wide +* data. The CAN FD Controller's clock domain concept allows the separation +* between the two input clocks, the CAN clock and the Bus clock.
+* +* Features of the CAN FD Controller
+* - Conforms with ISO11898-1 (CAN specification Rev. 2.0 part A, B) and the CAN FD specification V1.0 +* （Bosch CAN FD Specification V1.0）
+* - CAN FD with up to 64 data bytes supported
+* - CAN Error Logging
+* - Acceptance filtering
+* - Two configurable Receive FIFOs
+* - Separate signaling on reception of High Priority Messages
+* - Up to 64 dedicated Receive Buffers
+* - Up to 32 dedicated Transmit Buffers
+* - Configurable Transmit FIFO
+* - Configurable Transmit Queue
+* - Configurable Transmit Event FIFO
+* - Direct Message RAM access for CPU
+* - Programmable loop-back test mode
+* - Maskable interrupts
+* - Two clock domains (CAN clock and Bus clock)
+* - Power-down support
+* - Debug on CAN support
+* +* \section SectionCANFD_ConfigurationConsideration Configuration Consideration +* Before initializing the CANFD module, call Canpre_Init(). You must set the value of the divider for +* the CAN prescaler clock. This is supplied to the CANFD as a CANFD +* system clock.
+* +* Set fields in the stc_canfd_config_t structure to configure the peripheral. +* For example, set the CAN operation mode in enCanfdMode, and the clock frequency in enCanfdClock.
+* After setting the configuration structure to the desired values, call Canfd_Init() +* to configure the CANFD peripheral.
+* The callback functions pfnStatusCallback and pfnErrorCallback are optional, but recommended. Otherwise there is no +* report to the API in case of any reception, transmission, bus state and error +* event.
+* Use Canfd_DeInit() if you need to change any configuration settings. +* Make the required changes and then call Canfd_Init() again. +* Canfd_DeInit() completely disables the CAN FD module. +* All CAN FD related register values are reset to their default +* values. Any pending or ongoing transmission or reception will be +* aborted.
+* Call Canfd_Start() to start communication. You typically use Canfd_Restart() to recover +* after an error. Use Canfd_TransmitMsg() and Canfd_ReceiveMsg() for sending and receiving messages. +* The stc_canfd_msg_t structure contains the message and message identifier.
+* Each CAN FD module has dedicated message buffers for receiving and transmitting. +* You identify the buffer number to use when you transmit a message.
+* The receiving buffer consists of dedicated Rx buffer, Rx FIFO0 and Rx FIFO1. +* In the same way, the transmission buffer consists of dedicated Tx buffer and +* Tx FIFO/QUEUE.
+* +* \note The numbers of the message buffers used in this driver are shown as +* follows:
+* - dedicated Rx buffer : 1 element, indexed 0.
+* - Rx FIFO0 : 2 elements.
+* - Rx FIFO1 : not used.
+* - Tx buffer : 1 element, indexed 0.
+* - Tx FIFO/QUEUE : not used.
+* +* \section SectionCANFD_MoreInfo More Information +* For more information on the CANFD Controller, refer to:
+* FM4 Family 32-Bit MICROCONTROLLER PERIPHERAL MANUAL Communication Macro Part
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets can be downloaded +*/ + +/** +* \addtogroup GroupCANFD_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + +// CANFD controller +#define stc_canfdn_t FM_CANFD_TypeDef +#define CANFD0 (*((volatile stc_canfdn_t *)FM_CANFD0_BASE)) + +/// Size of data bytes in a receive or transmit operation +#define CANFD_MESSAGE_DATA_BUFFER_SIZE 64 +/// Size of data word in a receive or transmit operation +#define CANFD_MESSAGE_DATA_BUFFER_SIZEW (CANFD_MESSAGE_DATA_BUFFER_SIZE / 4) + +/// Number of possible dedicated Rx buffer for receive +#define CANFD_MESSAGE_RXBUFFER_COUNT 64 + +/// Number of possible Rx FIFO for receive messages +#define CANFD_MESSAGE_RXFIFO_COUNT 32 + +/// Number of possible dedicated Tx buffer, Tx Queue and Tx FIFO for transmit messages +#define CANFD_MESSAGE_TXBUFFER_COUNT 32 + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief The CAN FD driver uses definitions of the structure of registers on + ** the CAN FD controller that were defined in the "REGISTER DEFINITION HEADER" + ** for the target MCU. + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief CAN FD Unit configuration structures + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief CAN FD received message index. + ** + ** These are used to specify CAN operation mode. + ******************************************************************************/ +#define CANFD_MSGIDX_MIN (0U) // minimum index of dedicated Rx buffer. +#define CANFD_MSGIDX_MAX (63U) // maximum index of dedicated Rx buffer. +#define CANFD_MSGIDX_FIFO0 (254U) // received message stored into Rx FIFO0. +#define CANFD_MSGIDX_FIFO1 (255U) // received message stored into Rx FIFO1. + +#define CANFD_MAX_STDDLC (8) // maximum data length in standard CAN operation. + +/** + ****************************************************************************** + ** \brief CAN FD error. + ** + ** These error values are used to report any CAN FD related error to the API via + ** the CAN FD error callback function. + ** The parameter of this callback function is uint32_t type, and it includes + ** all of detected error flags as shown below; + ******************************************************************************/ +#define CANFD_ERROR_STE (1UL << 31) // [bit31] STE : Stuff Error / More than 5 equal bits in a sequence occurred. +#define CANFD_ERROR_FOE (1UL << 30) // [bit30] FOE : Format Error / A fixed format part of a received frame has the wrong format. +#define CANFD_ERROR_ACKE (1UL << 29) // [bit29] ACKE: Acknowledge Error / A transmitted message was not acknowledged by another node. +#define CANFD_ERROR_BE (1UL << 28) // [bit28] BE : Bit Error / CAN FD Controller wanted to send a recessive/dominant level, but monitored bus level was dominant/recessive. +#define CANFD_ERROR_CRCE (1UL << 27) // [bit27] CRCE: CRC Error / Received CRC did not match the calculated CRC. +#define CANFD_ERROR_WDI (1UL << 26) // [bit26] WDI : Watchdog Interrupt / Message RAM Watchdog event due to missing READY from Message RAM. +#define CANFD_ERROR_ELO (1UL << 22) // [bit22] ELO : Error Logging Overflow / Overflow of CAN Error Logging Counter (ECR.CEL[7:0]) occurred. +#define CANFD_ERROR_BEU (1UL << 21) // [bit21] BEU : Bit Error Uncorrected / Bit error detected, but could not be corrected. +#define CANFD_ERROR_BEC (1UL << 20) // [bit20] BEC : Bit Error Corrected / Bit error detected and corrected by ECC logic. +#define CANFD_ERROR_TOO (1UL << 18) // [bit18] TOO : Timeout Occurred / Timeout reached. +#define CANFD_ERROR_MRAF (1UL << 17) // [bit17] MRAF: Message RAM Access Failure / Message RAM access failure occurred. +#define CANFD_ERROR_TEFL (1UL << 15) // [bit15] TEFL: Tx Event FIFO Element Lost / Tx Event FIFO element lost. Also set after write attempt to Tx Event FIFO of size zero. +#define CANFD_ERROR_RF1L (1UL << 7) // [bit7] RF1L: Rx FIFO 1 Message Lost / Rx FIFO 1 message lost. Also set after write attempt to Rx FIFO 1 of size zero. +#define CANFD_ERROR_RF0L (1UL << 3) // [bit3] RF0L: Rx FIFO 0 Message Lost / Rx FIFO 0 message lost. Also set after write attempt to Rx FIFO 0 of size zero. + +/** \} GroupCANFD_Macros */ + +/** +* \addtogroup GroupCANFD_Types +* \{ +*/ +/** + ****************************************************************************** + ** \brief CAN operation mode. + ** + ** These are used to specify CAN operation mode. + ******************************************************************************/ +typedef enum en_canfd_mode +{ + CanfdModeClassic = 0, // classic CAN (CAN2.0) + CanfdModeFDFixed = 1, // CAN-FD with fixed data rate + CanfdModeFDFlex = 2 // CAN-FD with flexible data rate +} en_canfd_mode_t; + +/** + ****************************************************************************** + ** \brief CAN FD operation clock frequency. + ** + ** These are used to determin clock frequency of CAN FD controller. + ******************************************************************************/ +typedef enum en_canfd_clock +{ + CanfdClock32MHz = 0, // 32MHz + CanfdClock40MHz = 1 // 40MHz +} en_canfd_clock_t; + + +/** + ****************************************************************************** + ** \brief CAN FD module status. + ** + ** These state values represent the current CAN FD module state, and are used + ** in the CAN FD status changed callback function (canfd_status_chg_func_ptr_t). + ******************************************************************************/ +typedef enum en_canfd_status +{ + CanfdBusOff = 0, // The CAN FD module is in busoff state. + CanfdWarning = 1 // At least one error counter has reached error warning limit of 96. +} en_canfd_status_t; + +/** + ***************************************************************************** + ** \brief Message transmission complete callback function (canfd_tx_msg_func_ptr_t). + ** + ** Signals a successful completed transmission. + *****************************************************************************/ +typedef void (*canfd_tx_msg_func_ptr_t)( uint8_t u8MsgBuf ); + + +/** + ***************************************************************************** + ** \brief Status changed callback function (canfd_status_chg_func_ptr_t). + ** + ** Any status change will be reported to the API (see #en_canfd_status_t for + ** possible status change codes). + *****************************************************************************/ +typedef void (*canfd_status_chg_func_ptr_t)( en_canfd_status_t enCanfdStatus ); + + +/** + ***************************************************************************** + ** \brief Error callback function (canfd_error_func_ptr_t). + ** + ** Any error will be reported to the API + *****************************************************************************/ +typedef void (*canfd_error_func_ptr_t)( uint32_t u32CanfdError ); + + +/** \}GroupCANFD_Types */ + +/** +* \addtogroup GroupCANFD_DataStructures +* \{ +*/ +/** + ****************************************************************************** + ** \brief CAN message identifier + ** + ** This structure is used to set the CAN message identifier for transmit and + ** receive operations. + ******************************************************************************/ +typedef struct stc_canfd_msg_id +{ + uint32_t u32Identifier; // 11- or 29-bit identifier. The valid bit length depends on bExtended. + boolean_t bExtended; // TRUE: 29-bit identifier, FALSE: 11-bit identifier. +} stc_canfd_msg_id_t; + + +/** + ****************************************************************************** + ** \brief CAN message data. + ** + ** Data structure for transmit and receive operations, maximum value for + ** parameter u8DataLengthCode is CANFD_MESSAGE_DATA_BUFFER_SIZE. + ******************************************************************************/ +typedef struct stc_canfd_msg_data +{ + union + { + uint32_t au32Data[CANFD_MESSAGE_DATA_BUFFER_SIZEW]; // Data of CAN message. + uint8_t au8Data[CANFD_MESSAGE_DATA_BUFFER_SIZE]; // Data of CAN message. + }; + uint8_t u8DataLengthCode; // Number of valid bytes in au8Data and DLC of CAN message. +} stc_canfd_msg_data_t; + + +/** + ****************************************************************************** + ** \brief CAN message. + ** + ** This structure stores a CAN or CAN FD message, including the identifier, + ** data and data length code (DLC). It also contains an overflow and new flag + ** which indicates the message state for received messages. + ******************************************************************************/ +typedef struct stc_canfd_msg +{ + stc_canfd_msg_id_t stcIdentifier; // 11- or 29-bit identifier (ID). + stc_canfd_msg_data_t stcData; // Data and DLC. + boolean_t bCanfd; // TRUE : DLC is extended, FALSE : Normal DLC + // (valid received message only.) +} stc_canfd_msg_t; + +/** + ***************************************************************************** + ** \brief Message reception callback function (canfd_rx_msg_func_ptr_t). + ** + ** Signals that CAN has received a new message. + *****************************************************************************/ +typedef void (*canfd_rx_msg_func_ptr_t)( uint8_t u8MsgBuf, stc_canfd_msg_t* pstcRxMsg ); + + +/** + ***************************************************************************** + ** \brief CAN FD interrupt pointer structure + ** + ** Holds some pointers that point to callback functions for message reception + ** and transmission. + *****************************************************************************/ +typedef struct stc_canfd_interrupt_handling +{ + canfd_tx_msg_func_ptr_t pfnCanfdTxInterruptFunction; // pointer to transmit interrupt callback + canfd_rx_msg_func_ptr_t pfnCanfdRxInterruptFunction; // pointer to receive interrupt callback +} stc_canfd_interrupt_handling_t; + + +/** + ***************************************************************************** + ** \brief CAN FD notification pointer structure + ** + ** Holds some pointers to callback functions for status and error notification + *****************************************************************************/ +typedef struct stc_canfd_notification +{ + canfd_status_chg_func_ptr_t pfnCanfdStatusInterruptFunction ; + canfd_error_func_ptr_t pfnCanfdErrorInterruptFunction ; +} stc_canfd_notification_t; + + +/** + ****************************************************************************** + ** \brief CAN FD configuration. + ** + ** Is used to set the CAN operation mode and CAN FD clock frequency. + ** Optionally reception, transmission, error and status notification callback + ** functions can be set. + ******************************************************************************/ +typedef struct stc_canfd_config +{ + en_canfd_mode_t enCanfdMode; // CAN operation mode. + en_canfd_clock_t enCanfdClock; // CAN FD operation clock (prescaler output). + canfd_rx_msg_func_ptr_t pfnReceiveMsgCallback; // Callback function for receive message, can be NULL. + canfd_tx_msg_func_ptr_t pfnTransmitMsgCallback; // Callback function for transmit message, can be NULL. + canfd_status_chg_func_ptr_t pfnStatusCallback; // Callback function for CAN FD status changes, can be NULL. + canfd_error_func_ptr_t pfnErrorCallback; // Callback function for CAN FD related errors, can be NULL. +} stc_canfd_config_t; + +/** \} GroupCANFD_DataStructures */ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ + +/** +* \addtogroup GroupCANFD_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +extern void CanfdIrqHandler( volatile stc_canfdn_t* pstcCanfd ); + +extern en_result_t Canfd_Init( volatile stc_canfdn_t* pstcCanfd, + const stc_canfd_config_t* pstcConfig + ); + +extern en_result_t Canfd_DeInit( volatile stc_canfdn_t* pstcCanfd ); + +extern en_result_t Canfd_Start( volatile stc_canfdn_t* pstcCanfd ); + +extern en_result_t Canfd_Stop( volatile stc_canfdn_t* pstcCanfd ); + +extern en_result_t Canfd_Restart( volatile stc_canfdn_t* pstcCanfd ); + +extern en_result_t Canfd_TransmitMsg( volatile stc_canfdn_t* pstcCanfd, + uint8_t u8MsgBuf, + stc_canfd_msg_t* pstcMsg + ); + +extern en_result_t Canfd_ReceiveMsg( volatile stc_canfdn_t* pstcCanfd ); + +extern en_result_t Canfd_GetBusStatus( volatile stc_canfdn_t* pstcCanfd ); + +/** \}GroupCANFD_Functions */ +/** \} GroupCANFD */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_CANFD_ACTIVE)) + +#endif /* __CANFD_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.c new file mode 100644 index 0000000000..a1281d6447 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.c @@ -0,0 +1,2031 @@ +/****************************************************************************** +* \file clk.c +* +* \version 1.20 +* +* \brief Clock driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "clk/clk.h" + +#if (defined(PDL_PERIPHERAL_CLK_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) +stc_clk_intern_data_t stcClkInternData; +#endif + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Clock Stabilization Interrupt Handler + ******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) +void Clk_IrqHandler(void) +{ + uint8_t u8IntStrReadOut; + + u8IntStrReadOut = FM_CRG->INT_STR; + + // PLL stabilization ready? + if (0u != (u8IntStrReadOut & FM_INT_STR_PCSI_BITPOS)) + { + FM_CRG->INT_CLR |= FM_INT_CLR_PCSC_BITPOS; // Clear Irq + + // PLL ready callback if defined + if (NULL != stcClkInternData.pfnPllStabCb) + { + stcClkInternData.pfnPllStabCb(); + } + } + + // Sub Clock stabilization ready? + if (0u != (u8IntStrReadOut & FM_INT_STR_SCSI_BITPOS)) + { + FM_CRG->INT_CLR |= FM_INT_CLR_SCSC_BITPOS; // Clear Irq + + // Sub Clock ready callback if defined + if (NULL != stcClkInternData.pfnScoStabCb) + { + stcClkInternData.pfnScoStabCb(); + } + } + + // Main Clock stabilization ready? + if (0u != (u8IntStrReadOut & FM_INT_STR_MCSI_BITPOS)) + { + FM_CRG->INT_CLR |= FM_INT_CLR_MCSC_BITPOS; // Clear Irq + + // Main Clock ready callback if defined + if (NULL != stcClkInternData.pfnMcoStabCb) + { + stcClkInternData.pfnMcoStabCb(); + } + } +} +#endif + +/** + ****************************************************************************** + ** \brief Initialize system clock according to user configuration + ** + ** Set the definition CLOCK_SETUP to "CLOCK_SETTING_NONE" when using this + ** function to initialize system clock. + ** + ** \param [in] pstcClk Pointer to clock configuration structure + ** + ** \retval Ok Clock initialized normally + ** \retval ErrorInvalidParameter The paramter is set to error range + ******************************************************************************/ +en_result_t Clk_Init(const stc_clk_config_t* pstcClk) +{ + if(pstcClk == NULL) + { + return ErrorInvalidParameter; + } + + /* Set base clock dividor */ + switch(pstcClk->enBaseClkDiv) + { + case BaseClkDiv1: + FM_CRG->BSC_PSR_f.BSR = 0u; + break; + case BaseClkDiv2: + FM_CRG->BSC_PSR_f.BSR = 1u; + break; + case BaseClkDiv3: + FM_CRG->BSC_PSR_f.BSR = 2u; + break; + case BaseClkDiv4: + FM_CRG->BSC_PSR_f.BSR = 3u; + break; + case BaseClkDiv6: + FM_CRG->BSC_PSR_f.BSR = 4u; + break; + case BaseClkDiv8: + FM_CRG->BSC_PSR_f.BSR = 5u; + break; + case BaseClkDiv16: + FM_CRG->BSC_PSR_f.BSR = 6u; + break; + default: + return ErrorInvalidParameter; + + } + + /* Set APB0 bus clock dividor */ + switch(pstcClk->enAPB0Div) + { + case Apb0Div1: + FM_CRG->APBC0_PSR_f.APBC0 = 0u; + break; + case Apb0Div2: + FM_CRG->APBC0_PSR_f.APBC0 = 1u; + break; + case Apb0Div4: + FM_CRG->APBC0_PSR_f.APBC0 = 2u; + break; + case Apb0Div8: + FM_CRG->APBC0_PSR_f.APBC0 = 3u; + break; + default: + return ErrorInvalidParameter; + } + + /* Set APB1 bus clock dividor */ + switch(pstcClk->enAPB1Div) + { + case Apb1Div1: + FM_CRG->APBC1_PSR_f.APBC1 = 0u; + break; + case Apb1Div2: + FM_CRG->APBC1_PSR_f.APBC1 = 1u; + break; + case Apb1Div4: + FM_CRG->APBC1_PSR_f.APBC1 = 2u; + break; + case Apb1Div8: + FM_CRG->APBC1_PSR_f.APBC1 = 3u; + break; + default: + return ErrorInvalidParameter; + } + + if(TRUE == pstcClk->bAPB1Disable) + { + FM_CRG->APBC1_PSR_f.APBC1EN = 0; + } + + /* Configure stability wait time */ + FM_CRG->CSW_TMR_f.MOWT = pstcClk->enMCOWaitTime; + FM_CRG->CSW_TMR_f.SOWT = pstcClk->enSCOWaitTime; + FM_CRG->PSW_TMR_f.POWT = pstcClk->enPLLOWaitTime; + +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) + /* Configure interrupt */ + if(TRUE == pstcClk->bMcoIrq) + { + if(NULL == pstcClk->pfnMcoStabCb) + { + return ErrorInvalidParameter; + } + + FM_CRG->INT_ENR_f.MCSE = 1; + stcClkInternData.pfnMcoStabCb = pstcClk->pfnMcoStabCb; + } + + if(TRUE == pstcClk->bScoIrq) + { + if(NULL == pstcClk->pfnScoStabCb) + { + return ErrorInvalidParameter; + } + + FM_CRG->INT_ENR_f.SCSE = 1; + stcClkInternData.pfnScoStabCb = pstcClk->pfnScoStabCb; + } + + if(TRUE == pstcClk->bPllIrq) + { + if(NULL == pstcClk->pfnPllStabCb) + { + return ErrorInvalidParameter; + } + + FM_CRG->INT_ENR_f.PCSE = 1; + stcClkInternData.pfnPllStabCb = pstcClk->pfnPllStabCb; + } + + #if (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(TIM_WC_RTC_IRQn); + NVIC_EnableIRQ(TIM_WC_RTC_IRQn); + NVIC_SetPriority(TIM_WC_RTC_IRQn, PDL_IRQ_LEVEL_CLK_WC_RTC); + #elif (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_EnableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_IRQ_LEVEL_WC0); + #else + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_EnableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_IRQ_LEVEL_CLK); + #elif (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_EnableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #else + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_EnableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #endif + #endif + +#endif + + /* Set PLL K, M, N */ + FM_CRG->PLL_CTL1_f.PLLK = pstcClk->u8PllK - 1u; + FM_CRG->PLL_CTL1_f.PLLM = pstcClk->u8PllM - 1u; + FM_CRG->PLL_CTL2 = pstcClk->u8PllN - 1u; + + return Ok; +} + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Enable high speed CR + ** + ** This function easily enables the high speed CR. No configuration is needed. + ** + ** \param bBlock Wait until CR stability or not + ** \arg FALSE Return immediately after enable high speed CR + ** \arg TRUE Wait until CR stability after enable high speed CR + ** + ** \retval Ok high speed CR enabled + ******************************************************************************/ +en_result_t Clk_EnableHscr(boolean_t bBlock) +{ + FM_CRG->SCM_CTL_f.HCRE = 1u; + + if(TRUE == bBlock) + { + while(FM_CRG->SCM_STR_f.HCRDY != 1u); + } + + return Ok; +} // Clk_EnableMainClock + +/** + ****************************************************************************** + ** \brief Disable Main Clock + ** + ** This function easily disables the Main Clock. No configuration is needed. + ** + ** \retval Ok Main Clock disabled + ******************************************************************************/ +en_result_t Clk_DisableHscr(void) +{ + FM_CRG->SCM_CTL_f.HCRE = 0u; + + return Ok; +} // Clk_DisableMainClock +#endif + +/** + ****************************************************************************** + ** \brief Enable Main Clock and wait until it is stable + ** + ** This function easily enables the Main Clock. No configuration is needed. + ** + ** \param bBlock Wait until Main Clock stability or not + ** \arg FALSE Return immediately after enable Main Clock + ** \arg TRUE Wait until Main Clock stability after enable Main Clock + ** + ** \retval Ok Main Clock enabled + ******************************************************************************/ +en_result_t Clk_EnableMainClock(boolean_t bBlock) +{ + FM_CRG->SCM_CTL_f.MOSCE = 1u; + + if(TRUE == bBlock) + { + while(1u != FM_CRG->SCM_STR_f.MORDY); + } + + return Ok; +} // Clk_EnableMainClock + +/** + ****************************************************************************** + ** \brief Disable Main Clock + ** + ** This function easily disables the Main Clock. No configuration is needed. + ** + ** \retval Ok Main Clock disabled + ******************************************************************************/ +en_result_t Clk_DisableMainClock(void) +{ + FM_CRG->SCM_CTL_f.MOSCE = 0u; + + return Ok; +} // Clk_DisableMainClock + + +/** + ****************************************************************************** + ** \brief Enable Sub Clock + ** + ** This function easily enables the Sub Clock. No configuration is needed. + ** + ** \param bBlock Wait until Sub Clock stability or not + ** \arg FALSE Return immediately after enable Sub Clock + ** \arg TRUE Wait until Sub Clock stability after enable Sub Clock + ** + ** \retval Ok Sub Clock enabled + ******************************************************************************/ +en_result_t Clk_EnableSubClock(boolean_t bBlock) +{ + FM_CRG->SCM_CTL_f.SOSCE = 1u; + + if(TRUE == bBlock) + { + while(1u != FM_CRG->SCM_STR_f.SORDY); + } + + return Ok; +} // Clk_EnableSubClock + +/** + ****************************************************************************** + ** \brief Disable Sub Clock + ** + ** This function easily disables the Sub Clock. No configuration is needed. + ** + ** \retval Ok Sub Clock disabled + ******************************************************************************/ +en_result_t Clk_DisableSubClock(void) +{ + FM_CRG->SCM_CTL_f.SOSCE = 0u; + + return Ok; +} // Clk_DisableSubClock + + +/** + ****************************************************************************** + ** \brief Enable PLL Clock + ** + ** This function easily enables the PLL Clock. No configuration is needed. + ** + ** \param bBlock Wait until PLL Clock stability or not + ** \arg FALSE Return immediately after enable PLL Clock + ** \arg TRUE Wait until PLL Clock stability after enable PLL Clock + ** + ** \retval Ok PLL Clock enabled + ******************************************************************************/ +en_result_t Clk_EnablePllClock(boolean_t bBlock) +{ + FM_CRG->SCM_CTL_f.PLLE = 1u; + + if(bBlock == TRUE) + { + while(1u != FM_CRG->SCM_STR_f.PLRDY); + } + + return Ok; +} // Clk_EnablePllClock + +/** + ****************************************************************************** + ** \brief Disable PLL Clock + ** + ** This function easily disables the PLL Clock. No configuration is needed. + ** + ** \retval Ok PLL Clock disabled + ******************************************************************************/ +en_result_t Clk_DisablePllClock(void) +{ + FM_CRG->SCM_CTL_f.PLLE = 0u; + + return Ok; +} // Clk_DisableSubClock + +/** + ****************************************************************************** + ** \brief Set Clock Source + ** + ** This function sets the clock source and performs transition, if wanted. + ** + ** \param [in] enSource System source clock + ** \arg ClkMain Set Main Clock as system source clock + ** \arg ClkSub Set Sub Clock as system source clock + ** \arg ClkHsCr Set High-speed CR as system source clock + ** \arg ClkLsCr Set Low-speed CR as system source clock + ** \arg ClkPll Set Main PLL clock as system source clock + ** \arg ClkHsCrPll Set High-speed CR PLL clock as system source clock + ** + ** \retval Ok Clock source set + ** \retval ErrorInvalidParameter pstcConfig == NULL or Illegal mode + ** \retval ErrorInvalidMode Clock setting not possible + ******************************************************************************/ +en_result_t Clk_SetSource(en_clk_source_t enSource) +{ + uint8_t u8Rcs, u8Rcm; + switch(enSource) + { + case ClkMain: + if ((TRUE != FM_CRG->SCM_CTL_f.MOSCE) || // Main Oscillator ready? + (TRUE != FM_CRG->SCM_STR_f.MORDY)) + { + return ErrorInvalidMode ; + } + FM_CRG->SCM_CTL_f.RCS = 0x1u; + break; + case ClkSub: + if ((TRUE != FM_CRG->SCM_CTL_f.SOSCE) || // Sub Oscillator ready? + (TRUE != FM_CRG->SCM_STR_f.SORDY)) + { + return ErrorInvalidMode ; + } + FM_CRG->SCM_CTL_f.RCS = 0x5u; + break; + case ClkHsCr: // Always possible + FM_CRG->SCM_CTL_f.RCS = 0x0u; + break; + case ClkLsCr: // Always possible + FM_CRG->SCM_CTL_f.RCS = 0x4u; + break; + case ClkHsCrPll: + FM_CRG->PSW_TMR_f.PINC = 1u; + FM_CRG->SCM_CTL_f.RCS = 0x2u; + break; + case ClkPll: + if ((TRUE != FM_CRG->SCM_STR_f.MORDY) || // PLL ready? + (TRUE != FM_CRG->SCM_STR_f.PLRDY)) + { + return ErrorInvalidMode ; + } + + FM_CRG->PSW_TMR_f.PINC = 0u; + FM_CRG->SCM_CTL_f.RCS = 0x2u; + break; + default: + return ErrorInvalidParameter ; + } + + /* Wait until switch stable */ + while(1) + { + u8Rcs = FM_CRG->SCM_CTL_f.RCS; + u8Rcm = FM_CRG->SCM_STR_f.RCM; + if(u8Rcs == u8Rcm) + { + break; + } + } + + return Ok; +} // Clk_SetSource + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +/** + ****************************************************************************** + ** \brief Enables the clock gate of a peripheral + ** + ** This function sets the corresponding bit in the CKENn register to enable + ** the clock of a peripheral. + ** + ** \param enPeripheral Enumerator of a peripheral, see + ** #en_clk_gate_peripheral_t for details + ** + ** \retval Ok Peripheral clock enabled + ** \retval ErrorInvalidParameter Peripheral enumerator does not exist + ******************************************************************************/ +en_result_t Clk_PeripheralClockEnable(en_clk_gate_peripheral_t enPeripheral) +{ + switch (enPeripheral) + { + case ClkGateGpio: +#if defined(bFM_CLK_GATING_CKEN0_GIOCK) + bFM_CLK_GATING_CKEN0_GIOCK = 1u; +#endif + break; + case ClkGateDma: +#if defined(bFM_CLK_GATING_CKEN0_DMACK) + bFM_CLK_GATING_CKEN0_DMACK = 1u; +#endif + break; + case ClkGateAdc0: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK0) + bFM_CLK_GATING_CKEN0_ADCCK0 = 1u; +#endif + break; + case ClkGateAdc1: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK1) + bFM_CLK_GATING_CKEN0_ADCCK1 = 1u; +#endif + break; + case ClkGateAdc2: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK2) + bFM_CLK_GATING_CKEN0_ADCCK2 = 1u; +#endif + break; + case ClkGateAdc3: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK3) + bFM_CLK_GATING_CKEN0_ADCCK3 = 1u; +#endif + break; + case ClkGateMfs0: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK0) + bFM_CLK_GATING_CKEN0_MFSCK0 = 1u; +#endif + break; + case ClkGateMfs1: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK1) + bFM_CLK_GATING_CKEN0_MFSCK1 = 1u; +#endif + break; + case ClkGateMfs2: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK2) + bFM_CLK_GATING_CKEN0_MFSCK2 = 1u; +#endif + break; + case ClkGateMfs3: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK3) + bFM_CLK_GATING_CKEN0_MFSCK3 = 1u; +#endif + break; + case ClkGateMfs4: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK4) + bFM_CLK_GATING_CKEN0_MFSCK4 = 1u; +#endif + break; + case ClkGateMfs5: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK5) + bFM_CLK_GATING_CKEN0_MFSCK5 = 1u; +#endif + break; + case ClkGateMfs6: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK6) + bFM_CLK_GATING_CKEN0_MFSCK6 = 1u; +#endif + break; + case ClkGateMfs7: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK7) + bFM_CLK_GATING_CKEN0_MFSCK7 = 1u; +#endif + break; + case ClkGateMfs8: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK8) + bFM_CLK_GATING_CKEN0_MFSCK8 = 1u; +#endif + break; + case ClkGateMfs9: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK9) + bFM_CLK_GATING_CKEN0_MFSCK9 = 1u; +#endif + break; + case ClkGateMfs10: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK10) + bFM_CLK_GATING_CKEN0_MFSCK10 = 1u; +#endif + break; + case ClkGateMfs11: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK11) + bFM_CLK_GATING_CKEN0_MFSCK11 = 1u; +#endif + break; + case ClkGateMfs12: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK12) + bFM_CLK_GATING_CKEN0_MFSCK12 = 1u; +#endif + break; + case ClkGateMfs13: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK13) + bFM_CLK_GATING_CKEN0_MFSCK13 = 1u; +#endif + break; + case ClkGateMfs14: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK14) + bFM_CLK_GATING_CKEN0_MFSCK14 = 1u; +#endif + break; + case ClkGateMfs15: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK15) + bFM_CLK_GATING_CKEN0_MFSCK15 = 1u; +#endif + break; + case ClkGateQprc0: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK0) + bFM_CLK_GATING_CKEN1_QDUCK0 = 1u; +#endif + break; + case ClkGateQprc1: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK1) + bFM_CLK_GATING_CKEN1_QDUCK1 = 1u; +#endif + break; + case ClkGateQprc2: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK2) + bFM_CLK_GATING_CKEN1_QDUCK2 = 1u; +#endif + break; + case ClkGateQprc3: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK3) + bFM_CLK_GATING_CKEN1_QDUCK3 = 1u; +#endif + break; + case ClkGateMft0: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK0) + bFM_CLK_GATING_CKEN1_MFTCK0 = 1u; +#endif + break; + case ClkGateMft1: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK1) + bFM_CLK_GATING_CKEN1_MFTCK1 = 1u; +#endif + break; + case ClkGateMft2: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK2) + bFM_CLK_GATING_CKEN1_MFTCK2 = 1u; +#endif + break; + case ClkGateMft3: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK3) + bFM_CLK_GATING_CKEN1_MFTCK3 = 1u; +#endif + break; + case ClkGateBt0123: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK0) + bFM_CLK_GATING_CKEN1_BTMCK0 = 1u; +#endif + break; + case ClkGateBt4567: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK1) + bFM_CLK_GATING_CKEN1_BTMCK1 = 1u; +#endif + break; + case ClkGateBt891011: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK2) + bFM_CLK_GATING_CKEN1_BTMCK2 = 1u; +#endif + break; + case ClkGateBt12131415: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK3) + bFM_CLK_GATING_CKEN1_BTMCK3 = 1u; +#endif + break; + case ClkGateExtif: +#if defined(bFM_CLK_GATING_CKEN0_EXBCK) + bFM_CLK_GATING_CKEN0_EXBCK = 1u; +#endif + break; + case ClkGateUsb0: +#if defined(bFM_CLK_GATING_CKEN2_USBCK0 ) + bFM_CLK_GATING_CKEN2_USBCK0 = 1u; +#endif + break; + case ClkGateUsb1: +#if defined(bFM_CLK_GATING_CKEN2_USBCK1 ) + bFM_CLK_GATING_CKEN2_USBCK1 = 1u; +#endif + break; + case ClkGateCan0: +#if defined(bFM_CLK_GATING_CKEN2_CANCK0 ) + bFM_CLK_GATING_CKEN2_CANCK0 = 1u; +#endif + break; + case ClkGateCan1: +#if defined(bFM_CLK_GATING_CKEN2_CANCK1 ) + bFM_CLK_GATING_CKEN2_CANCK1 = 1u; +#endif + break; + case ClkGateCan2: +#if defined(bFM_CLK_GATING_CKEN2_CANCK2 ) + bFM_CLK_GATING_CKEN2_CANCK2 = 1u; +#endif + break; + case ClkGateSd: +#if defined(bFM_CLK_GATING_CKEN2_SDCCK ) + bFM_CLK_GATING_CKEN2_SDCCK = 1u; +#endif + break; + case ClkGateI2s0: +#if defined(bFM_CLK_GATING_CKEN2_I2SCK0 ) + bFM_CLK_GATING_CKEN2_I2SCK0 = 1u; +#endif + break; + case ClkGateI2s1: +#if defined(bFM_CLK_GATING_CKEN2_I2SCK1 ) + bFM_CLK_GATING_CKEN2_I2SCK1 = 1u; +#endif + break; + case ClkGatePcrc: +#if defined(bFM_CLK_GATING_CKEN2_PCRCCK ) + bFM_CLK_GATING_CKEN2_PCRCCK = 1u; +#endif + break; + case ClkGateQspi: +#if defined(bFM_CLK_GATING_CKEN2_QSPICK ) + bFM_CLK_GATING_CKEN2_QSPICK = 1u; +#endif + break; +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + case ClkGateCec0: + case ClkGateCec1: +#if defined(bFM_CLK_GATING_CKEN2_CECCK ) + bFM_CLK_GATING_CKEN2_CECCK = 1u; +#endif + break; +#else + case ClkGateCec0: +#if defined(bFM_CLK_GATING_CKEN2_CECCK0) + bFM_CLK_GATING_CKEN2_CECCK0 = 1u; +#endif + break; + case ClkGateCec1: +#if defined(bFM_CLK_GATING_CKEN2_CECCK1) + bFM_CLK_GATING_CKEN2_CECCK1 = 1u; +#endif + break; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case ClkGateIcc0: +#if defined(bFM_CLK_GATING_CKEN2_ICCCK0) + bFM_CLK_GATING_CKEN2_ICCCK0 = 1u; +#endif + break; + case ClkGateIcc1: +#if defined(bFM_CLK_GATING_CKEN2_ICCCK1) + bFM_CLK_GATING_CKEN2_ICCCK1 = 1u; +#endif + break; + case ClkGateI2sl0: +#if defined(bFM_CLK_GATING_CKEN2_IISCCK0) + bFM_CLK_GATING_CKEN2_IISCCK0 = 1u; +#endif + break; + case ClkGateI2sl1: +#if defined(bFM_CLK_GATING_CKEN2_IISCCK1) + bFM_CLK_GATING_CKEN2_IISCCK1 = 1u; +#endif + break; +#endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} // Clk_PeripheralClockDisable + +/** + ****************************************************************************** + ** \brief Read the clock gate state of a peripheral + ** + ** This function reads out the corresponding bit in the CKENn register. + ** + ** \param enPeripheral Enumerator of a peripheral, see + ** #en_clk_gate_peripheral_t for details + ** + ** \retval TRUE Peripheral clock enabled + ** \retval FALSE Peripheral clock not enabled, peripheral + ** not existing + ******************************************************************************/ +boolean_t Clk_PeripheralGetClockState(en_clk_gate_peripheral_t enPeripheral) +{ + switch (enPeripheral) + { + case ClkGateGpio: +#if defined(bFM_CLK_GATING_CKEN0_GIOCK) + return ((1u == bFM_CLK_GATING_CKEN0_GIOCK) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateDma: +#if defined(bFM_CLK_GATING_CKEN0_DMACK) + return ((1u == bFM_CLK_GATING_CKEN0_DMACK) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateAdc0: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK0) + return ((1u == bFM_CLK_GATING_CKEN0_ADCCK0) ? TRUE: FALSE); +#else + break; +#endif + case ClkGateAdc1: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK1) + return ((1u == bFM_CLK_GATING_CKEN0_ADCCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateAdc2: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK2) + return ((1u == bFM_CLK_GATING_CKEN0_ADCCK2) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateAdc3: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK3) + return ((1u == bFM_CLK_GATING_CKEN0_ADCCK3) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs0: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK0) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs1: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK1) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs2: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK2) + return (1u == bFM_CLK_GATING_CKEN0_MFSCK2) ? TRUE : FALSE; +#else + break; +#endif + case ClkGateMfs3: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK3) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK3) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs4: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK4) + return (1u == bFM_CLK_GATING_CKEN0_MFSCK4) ? TRUE : FALSE; +#else + break; +#endif + case ClkGateMfs5: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK5) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK5) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs6: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK6) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK6) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs7: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK7) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK7) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs8: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK8) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK8) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs9: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK9) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK9) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs10: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK10) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK10) ? TRUE: FALSE); +#else + break; +#endif + case ClkGateMfs11: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK11) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK11) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs12: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK12) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK12) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs13: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK13) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK13) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs14: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK14) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK14) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMfs15: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK15) + return ((1u == bFM_CLK_GATING_CKEN0_MFSCK15) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateQprc0: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK0) + return ((1u == bFM_CLK_GATING_CKEN1_QDUCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateQprc1: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK1) + return ((1u == bFM_CLK_GATING_CKEN1_QDUCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateQprc2: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK2) + return ((1u == bFM_CLK_GATING_CKEN1_QDUCK2) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateQprc3: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK3) + return ((1u == bFM_CLK_GATING_CKEN1_QDUCK3) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMft0: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK0) + return ((1u == bFM_CLK_GATING_CKEN1_MFTCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMft1: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK1) + return ((1u == bFM_CLK_GATING_CKEN1_MFTCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMft2: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK2) + return ((1u == bFM_CLK_GATING_CKEN1_MFTCK2) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateMft3: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK3) + return ((1u == bFM_CLK_GATING_CKEN1_MFTCK3) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateBt0123: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK0) + return ((1u == bFM_CLK_GATING_CKEN1_BTMCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateBt4567: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK1) + return ((1u == bFM_CLK_GATING_CKEN1_BTMCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateBt891011: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK2) + return ((1u == bFM_CLK_GATING_CKEN1_BTMCK2) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateBt12131415: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK3) + return ((1u == bFM_CLK_GATING_CKEN1_BTMCK3) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateExtif: +#if defined(bFM_CLK_GATING_CKEN0_EXBCK) + return ((1u == bFM_CLK_GATING_CKEN0_EXBCK) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateUsb0: +#if defined(bFM_CLK_GATING_CKEN2_USBCK0 ) + return ((1u == bFM_CLK_GATING_CKEN2_USBCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateUsb1: +#if defined(bFM_CLK_GATING_CKEN2_USBCK1 ) + return ((1u == bFM_CLK_GATING_CKEN2_USBCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateCan0: +#if defined(bFM_CLK_GATING_CKEN2_CANCK0 ) + return ((1u == bFM_CLK_GATING_CKEN2_CANCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateCan1: +#if defined(bFM_CLK_GATING_CKEN2_CANCK1 ) + return ((1u == bFM_CLK_GATING_CKEN2_CANCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateCan2: +#if defined(bFM_CLK_GATING_CKEN2_CANCK2 ) + return ((1u == bFM_CLK_GATING_CKEN2_CANCK2) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateSd: +#if defined(bFM_CLK_GATING_CKEN2_SDCCK ) + return (1u == bFM_CLK_GATING_CKEN2_SDCCK); +#else + break; +#endif + case ClkGateI2s0: +#if defined(bFM_CLK_GATING_CKEN2_I2SCK0 ) + return ((1u == bFM_CLK_GATING_CKEN2_I2SCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateI2s1: +#if defined(bFM_CLK_GATING_CKEN2_I2SCK1 ) + return ((1u == bFM_CLK_GATING_CKEN2_I2SCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGatePcrc: +#if defined(bFM_CLK_GATING_CKEN2_PCRCCK ) + return ((1u == bFM_CLK_GATING_CKEN2_PCRCCK) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateQspi: +#if defined(bFM_CLK_GATING_CKEN2_QSPICK ) + return ((1u == bFM_CLK_GATING_CKEN2_QSPICK) ? TRUE : FALSE); +#else + break; +#endif +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + case ClkGateCec0: + case ClkGateCec1: +#if defined(bFM_CLK_GATING_CKEN2_CECCK ) + return ((1u == bFM_CLK_GATING_CKEN2_CECCK) ? TRUE : FALSE); +#else + break; +#endif +#else + case ClkGateCec0: +#if defined(bFM_CLK_GATING_CKEN2_CECCK0) + return ((1u == bFM_CLK_GATING_CKEN2_CECCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateCec1: +#if defined(bFM_CLK_GATING_CKEN2_CECCK1) + return ((1u == bFM_CLK_GATING_CKEN2_CECCK1) ? TRUE : FALSE); +#else + break; +#endif +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case ClkGateIcc0: +#if defined(bFM_CLK_GATING_CKEN2_ICCCK0) + return ((1u == bFM_CLK_GATING_CKEN2_ICCCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateIcc1: +#if defined(bFM_CLK_GATING_CKEN2_ICCCK1) + return ((1u == bFM_CLK_GATING_CKEN2_ICCCK1) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateI2sl0: +#if defined(bFM_CLK_GATING_CKEN2_IISCCK0) + return ((1u == bFM_CLK_GATING_CKEN2_IISCCK0) ? TRUE : FALSE); +#else + break; +#endif + case ClkGateI2sl1: +#if defined(bFM_CLK_GATING_CKEN2_IISCCK1) + return ((1u == bFM_CLK_GATING_CKEN2_IISCCK1) ? TRUE : FALSE); +#else + break; +#endif +#endif + default: + break; + } + + return FALSE; // Peripheral not found -> always FALSE +} // Clk_PeripheralGetClockState + +/** + ****************************************************************************** + ** \brief Disables the clock gate of a peripheral + ** + ** This function clears the corresponding bit in the CKENn register to enable + ** the clock of a peripheral. + ** + ** \param enPeripheral Enumerator of a peripheral, see + ** #en_clk_gate_peripheral_t for details + ** + ** \retval Ok Peripheral clock disabled + ** \retval ErrorInvalidParameter Peripheral enumerator does not exist + ******************************************************************************/ +en_result_t Clk_PeripheralClockDisable(en_clk_gate_peripheral_t enPeripheral) +{ + switch (enPeripheral) + { + case ClkGateGpio: +#if defined(bFM_CLK_GATING_CKEN0_GIOCK) + bFM_CLK_GATING_CKEN0_GIOCK = 0u; +#endif + break; + case ClkGateDma: +#if defined(bFM_CLK_GATING_CKEN0_DMACK) + bFM_CLK_GATING_CKEN0_DMACK = 0u; +#endif + break; + case ClkGateAdc0: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK0) + bFM_CLK_GATING_CKEN0_ADCCK0 = 0u; +#endif + break; + case ClkGateAdc1: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK1) + bFM_CLK_GATING_CKEN0_ADCCK1 = 0u; +#endif + break; + case ClkGateAdc2: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK2) + bFM_CLK_GATING_CKEN0_ADCCK2 = 0u; +#endif + break; + case ClkGateAdc3: +#if defined(bFM_CLK_GATING_CKEN0_ADCCK3) + bFM_CLK_GATING_CKEN0_ADCCK3 = 0u; +#endif + break; + case ClkGateMfs0: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK0) + bFM_CLK_GATING_CKEN0_MFSCK0 = 0u; +#endif + break; + case ClkGateMfs1: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK1) + bFM_CLK_GATING_CKEN0_MFSCK1 = 0u; +#endif + break; + case ClkGateMfs2: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK2) + bFM_CLK_GATING_CKEN0_MFSCK2 = 0u; +#endif + break; + case ClkGateMfs3: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK3) + bFM_CLK_GATING_CKEN0_MFSCK3 = 0u; +#endif + break; + case ClkGateMfs4: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK4) + bFM_CLK_GATING_CKEN0_MFSCK4 = 0u; +#endif + break; + case ClkGateMfs5: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK5) + bFM_CLK_GATING_CKEN0_MFSCK5 = 0u; +#endif + break; + case ClkGateMfs6: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK6) + bFM_CLK_GATING_CKEN0_MFSCK6 = 0u; +#endif + break; + case ClkGateMfs7: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK7) + bFM_CLK_GATING_CKEN0_MFSCK7 = 0u; +#endif + break; + case ClkGateMfs8: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK8) + bFM_CLK_GATING_CKEN0_MFSCK8 = 0u; +#endif + break; + case ClkGateMfs9: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK9) + bFM_CLK_GATING_CKEN0_MFSCK9 = 0u; +#endif + break; + case ClkGateMfs10: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK10) + bFM_CLK_GATING_CKEN0_MFSCK10 = 0u; +#endif + break; + case ClkGateMfs11: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK11) + bFM_CLK_GATING_CKEN0_MFSCK11 = 0u; +#endif + break; + case ClkGateMfs12: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK12) + bFM_CLK_GATING_CKEN0_MFSCK12 = 0u; +#endif + break; + case ClkGateMfs13: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK13) + bFM_CLK_GATING_CKEN0_MFSCK13 = 0u; +#endif + break; + case ClkGateMfs14: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK14) + bFM_CLK_GATING_CKEN0_MFSCK14 = 0u; +#endif + break; + case ClkGateMfs15: +#if defined(bFM_CLK_GATING_CKEN0_MFSCK15) + bFM_CLK_GATING_CKEN0_MFSCK15 = 0u; +#endif + break; + case ClkGateQprc0: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK0) + bFM_CLK_GATING_CKEN1_QDUCK0 = 0u; +#endif + break; + case ClkGateQprc1: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK1) + bFM_CLK_GATING_CKEN1_QDUCK1 = 0u; +#endif + break; + case ClkGateQprc2: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK2) + bFM_CLK_GATING_CKEN1_QDUCK2 = 0u; +#endif + break; + case ClkGateQprc3: +#if defined(bFM_CLK_GATING_CKEN1_QDUCK3) + bFM_CLK_GATING_CKEN1_QDUCK3 = 0u; +#endif + break; + case ClkGateMft0: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK0) + bFM_CLK_GATING_CKEN1_MFTCK0 = 0u; +#endif + break; + case ClkGateMft1: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK1) + bFM_CLK_GATING_CKEN1_MFTCK1 = 0u; +#endif + break; + case ClkGateMft2: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK2) + bFM_CLK_GATING_CKEN1_MFTCK2 = 0u; +#endif + break; + case ClkGateMft3: +#if defined(bFM_CLK_GATING_CKEN1_MFTCK3) + bFM_CLK_GATING_CKEN1_MFTCK3 = 0u; +#endif + break; + case ClkGateBt0123: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK0) + bFM_CLK_GATING_CKEN1_BTMCK0 = 0u; +#endif + break; + case ClkGateBt4567: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK1) + bFM_CLK_GATING_CKEN1_BTMCK1 = 0u; +#endif + break; + case ClkGateBt891011: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK2) + bFM_CLK_GATING_CKEN1_BTMCK2 = 0u; +#endif + break; + case ClkGateBt12131415: +#if defined(bFM_CLK_GATING_CKEN1_BTMCK3) + bFM_CLK_GATING_CKEN1_BTMCK3 = 0u; +#endif + break; + case ClkGateExtif: +#if defined(bFM_CLK_GATING_CKEN0_EXBCK) + bFM_CLK_GATING_CKEN0_EXBCK = 0u; +#endif + break; + case ClkGateUsb0: +#if defined(bFM_CLK_GATING_CKEN2_USBCK0 ) + bFM_CLK_GATING_CKEN2_USBCK0 = 0u; +#endif + break; + case ClkGateUsb1: +#if defined(bFM_CLK_GATING_CKEN2_USBCK1 ) + bFM_CLK_GATING_CKEN2_USBCK1 = 0u; +#endif + break; + case ClkGateCan0: +#if defined(bFM_CLK_GATING_CKEN2_CANCK0 ) + bFM_CLK_GATING_CKEN2_CANCK0 = 0u; +#endif + break; + case ClkGateCan1: +#if defined(bFM_CLK_GATING_CKEN2_CANCK1 ) + bFM_CLK_GATING_CKEN2_CANCK1 = 0u; +#endif + break; + case ClkGateCan2: +#if defined(bFM_CLK_GATING_CKEN2_CANCK2 ) + bFM_CLK_GATING_CKEN2_CANCK2 = 0u; +#endif + break; + case ClkGateSd: +#if defined(bFM_CLK_GATING_CKEN2_SDCCK ) + bFM_CLK_GATING_CKEN2_SDCCK = 0u; +#endif + break; + case ClkGateI2s0: +#if defined(bFM_CLK_GATING_CKEN2_I2SCK0 ) + bFM_CLK_GATING_CKEN2_I2SCK0 = 0u; +#endif + break; + case ClkGateI2s1: +#if defined(bFM_CLK_GATING_CKEN2_I2SCK1 ) + bFM_CLK_GATING_CKEN2_I2SCK1 = 0u; +#endif + break; + case ClkGatePcrc: +#if defined(bFM_CLK_GATING_CKEN2_PCRCCK ) + bFM_CLK_GATING_CKEN2_PCRCCK = 0u; +#endif + break; + case ClkGateQspi: +#if defined(bFM_CLK_GATING_CKEN2_QSPICK ) + bFM_CLK_GATING_CKEN2_QSPICK = 0u; +#endif + break; +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + case ClkGateCec0: + case ClkGateCec1: +#if defined(bFM_CLK_GATING_CKEN2_CECCK ) + bFM_CLK_GATING_CKEN2_CECCK = 0u; +#endif + break; +#else + case ClkGateCec0: +#if defined(bFM_CLK_GATING_CKEN2_CECCK0) + bFM_CLK_GATING_CKEN2_CECCK0 = 0u; +#endif + break; + case ClkGateCec1: +#if defined(bFM_CLK_GATING_CKEN2_CECCK1) + bFM_CLK_GATING_CKEN2_CECCK1 = 0u; +#endif + break; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case ClkGateIcc0: +#if defined(bFM_CLK_GATING_CKEN2_ICCCK0) + bFM_CLK_GATING_CKEN2_ICCCK0 = 0u; +#endif + break; + case ClkGateIcc1: +#if defined(bFM_CLK_GATING_CKEN2_ICCCK1) + bFM_CLK_GATING_CKEN2_ICCCK1 = 0u; +#endif + break; + case ClkGateI2sl0: +#if defined(bFM_CLK_GATING_CKEN2_IISCCK0) + bFM_CLK_GATING_CKEN2_IISCCK0 = 0u; +#endif + break; + case ClkGateI2sl1: +#if defined(bFM_CLK_GATING_CKEN2_IISCCK1) + bFM_CLK_GATING_CKEN2_IISCCK1 = 0u; +#endif + break; +#endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} // Clk_PeripheralClockDisable + +/** + ****************************************************************************** + ** \brief Enable the clock gate of all peripherals + ** + ** This function enable the clock of all peripherals. + ** + ** \retval Ok All peripheral clock enabled + ******************************************************************************/ +en_result_t Clk_PeripheralClockEnableAll(void) +{ + FM_CLK_GATING->CKEN0 = 0xFFFFFFFFu; + FM_CLK_GATING->CKEN1 = 0xFFFFFFFFu; + FM_CLK_GATING->CKEN2 = 0xFFFFFFFFu; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable the clock gate of all peripherals + ** + ** This function disables the clock of all peripherals. + ** + ** \retval Ok All peripheral clock disabled + ******************************************************************************/ +en_result_t Clk_PeripheralClockDisableAll(void) +{ + FM_CLK_GATING->CKEN0 = 0u; + FM_CLK_GATING->CKEN1 = 0u; + FM_CLK_GATING->CKEN2 = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set reset bit a peripheral + ** + ** This function sets the corresponding bit in the MRSTn register to set + ** a peripheral in reset state. + ** + ** \param enPeripheral Enumerator of a peripheral, see + ** #en_clk_reset_peripheral_t for details + ** + ** \retval Ok Peripheral clock enabled + ** \retval ErrorInvalidParameter Peripheral enumerator does not exist + ******************************************************************************/ +en_result_t Clk_PeripheralSetReset(en_clk_reset_peripheral_t enPeripheral) +{ + switch (enPeripheral) + { + case ClkResetDma: +#if defined(bFM_CLK_GATING_MRST0_DMARST) + bFM_CLK_GATING_MRST0_DMARST = 1u; +#endif + break; + case ClkResetAdc0: +#if defined(bFM_CLK_GATING_MRST0_ADCRST0) + bFM_CLK_GATING_MRST0_ADCRST0 = 1u; +#endif + break; + case ClkResetAdc1: +#if defined(bFM_CLK_GATING_MRST0_ADCRST1) + bFM_CLK_GATING_MRST0_ADCRST1 = 1u; +#endif + break; + case ClkResetAdc2: +#if defined(bFM_CLK_GATING_MRST0_ADCRST2) + bFM_CLK_GATING_MRST0_ADCRST2 = 1u; +#endif + break; + case ClkResetAdc3: +#if defined(bFM_CLK_GATING_MRST0_ADCRST3) + bFM_CLK_GATING_MRST0_ADCRST3 = 1u; +#endif + break; + case ClkResetMfs0: +#if defined(bFM_CLK_GATING_MRST0_MFSRST0) + bFM_CLK_GATING_MRST0_MFSRST0 = 1u; +#endif + break; + case ClkResetMfs1: +#if defined(bFM_CLK_GATING_MRST0_MFSRST1) + bFM_CLK_GATING_MRST0_MFSRST1 = 1u; +#endif + break; + case ClkResetMfs2: +#if defined(bFM_CLK_GATING_MRST0_MFSRST2) + bFM_CLK_GATING_MRST0_MFSRST2 = 1u; +#endif + break; + case ClkResetMfs3: +#if defined(bFM_CLK_GATING_MRST0_MFSRST3) + bFM_CLK_GATING_MRST0_MFSRST3 = 1u; +#endif + break; + case ClkResetMfs4: +#if defined(bFM_CLK_GATING_MRST0_MFSRST4) + bFM_CLK_GATING_MRST0_MFSRST4 = 1u; +#endif + break; + case ClkResetMfs5: +#if defined(bFM_CLK_GATING_MRST0_MFSRST5) + bFM_CLK_GATING_MRST0_MFSRST5 = 1u; +#endif + break; + case ClkResetMfs6: +#if defined(bFM_CLK_GATING_MRST0_MFSRST6) + bFM_CLK_GATING_MRST0_MFSRST6 = 1u; +#endif + break; + case ClkResetMfs7: +#if defined(bFM_CLK_GATING_MRST0_MFSRST7) + bFM_CLK_GATING_MRST0_MFSRST7 = 1u; +#endif + break; + case ClkResetMfs8: +#if defined(bFM_CLK_GATING_MRST0_MFSRST8) + bFM_CLK_GATING_MRST0_MFSRST8 = 1u; +#endif + break; + case ClkResetMfs9: +#if defined(bFM_CLK_GATING_MRST0_MFSRST9) + bFM_CLK_GATING_MRST0_MFSRST9 = 1u; +#endif + break; + case ClkResetMfs10: +#if defined(bFM_CLK_GATING_MRST0_MFSRST10) + bFM_CLK_GATING_MRST0_MFSRST10 = 1u; +#endif + break; + case ClkResetMfs11: +#if defined(bFM_CLK_GATING_MRST0_MFSRST11) + bFM_CLK_GATING_MRST0_MFSRST11 = 1u; +#endif + break; + case ClkResetMfs12: +#if defined(bFM_CLK_GATING_MRST0_MFSRST12) + bFM_CLK_GATING_MRST0_MFSRST12 = 1u; +#endif + break; + case ClkResetMfs13: +#if defined(bFM_CLK_GATING_MRST0_MFSRST13) + bFM_CLK_GATING_MRST0_MFSRST13 = 1u; +#endif + break; + case ClkResetMfs14: +#if defined(bFM_CLK_GATING_MRST0_MFSRST14) + bFM_CLK_GATING_MRST0_MFSRST14 = 1u; +#endif + break; + case ClkResetMfs15: +#if defined(bFM_CLK_GATING_MRST0_MFSRST15) + bFM_CLK_GATING_MRST0_MFSRST15 = 1u; +#endif + break; + case ClkResetQprc0: +#if defined(bFM_CLK_GATING_MRST1_QDURST0) + bFM_CLK_GATING_MRST1_QDURST0 = 1u; +#endif + break; + case ClkResetQprc1: +#if defined(bFM_CLK_GATING_MRST1_QDURST1) + bFM_CLK_GATING_MRST1_QDURST1 = 1u; +#endif + break; + case ClkResetQprc2: +#if defined(bFM_CLK_GATING_MRST1_QDURST2) + bFM_CLK_GATING_MRST1_QDURST2 = 1u; +#endif + break; + case ClkResetQprc3: +#if defined(bFM_CLK_GATING_MRST1_QDURST3) + bFM_CLK_GATING_MRST1_QDURST3 = 1u; +#endif + break; + case ClkResetMft0: +#if defined(bFM_CLK_GATING_MRST1_MFTRST0) + bFM_CLK_GATING_MRST1_MFTRST0 = 1u; +#endif + break; + case ClkResetMft1: +#if defined(bFM_CLK_GATING_MRST1_MFTRST1) + bFM_CLK_GATING_MRST1_MFTRST1 = 1u; +#endif + break; + case ClkResetMft2: +#if defined(bFM_CLK_GATING_MRST1_MFTRST2) + bFM_CLK_GATING_MRST1_MFTRST2 = 1u; +#endif + break; + case ClkResetMft3: +#if defined(bFM_CLK_GATING_MRST1_MFTRST3) + bFM_CLK_GATING_MRST1_MFTRST3 = 1u; +#endif + break; + case ClkResetBt0123: +#if defined(bFM_CLK_GATING_MRST1_BTMRST0) + bFM_CLK_GATING_MRST1_BTMRST0 = 1u; +#endif + break; + case ClkResetBt4567: +#if defined(bFM_CLK_GATING_MRST1_BTMRST1) + bFM_CLK_GATING_MRST1_BTMRST1 = 1u; +#endif + break; + case ClkResetBt891011: +#if defined(bFM_CLK_GATING_MRST1_BTMRST2) + bFM_CLK_GATING_MRST1_BTMRST2 = 1u; +#endif + break; + case ClkResetBt12131415: +#if defined(bFM_CLK_GATING_MRST1_BTMRST3) + bFM_CLK_GATING_MRST1_BTMRST3 = 1u; +#endif + break; + case ClkResetExtif: +#if defined(bFM_CLK_GATING_MRST0_EXBRST) + FM_CLK_GATING->MRST0_f.EXBRST = 1u; +#endif + break; + case ClkResetUsb0: +#if defined(bFM_CLK_GATING_MRST2_USBRST0) + bFM_CLK_GATING_MRST2_USBRST0 = 1u; +#endif + break; + case ClkResetUsb1: +#if defined(bFM_CLK_GATING_MRST2_USBRST1) + bFM_CLK_GATING_MRST2_USBRST1 = 1u; +#endif + break; + case ClkResetSd: +#if defined(bFM_CLK_GATING_MRST2_SDCRST) + bFM_CLK_GATING_MRST2_SDCRST = 1u; +#endif + break; + case ClkResetI2s0: +#if defined(bFM_CLK_GATING_MRST2_I2SRST0) + bFM_CLK_GATING_MRST2_I2SRST0 = 1u; +#endif + break; + case ClkResetI2s1: +#if defined(bFM_CLK_GATING_MRST2_I2SRST1) + bFM_CLK_GATING_MRST2_I2SRST1 = 1u; +#endif + break; + case ClkResetPcrc: +#if defined(bFM_CLK_GATING_MRST2_PCRCRST) + bFM_CLK_GATING_MRST2_PCRCRST = 1u; +#endif + break; + case ClkResetQspi: +#if defined(bFM_CLK_GATING_MRST2_HSSPIRST) + bFM_CLK_GATING_MRST2_HSSPIRST = 1u; +#endif + break; + case ClkResetCan0: +#if defined(bFM_CLK_GATING_MRST2_CANRST0) + bFM_CLK_GATING_MRST2_CANRST0 = 1u; +#endif + break; + case ClkResetCan1: +#if defined(bFM_CLK_GATING_MRST2_CANRST1) + bFM_CLK_GATING_MRST2_CANRST1 = 1u; +#endif + break; + case ClkResetCan2: +#if defined(bFM_CLK_GATING_MRST2_CANRST2) + bFM_CLK_GATING_MRST2_CANRST2 = 1u; +#endif + break; +#if defined(bFM_CLK_GATING_MRST2_CECRST) + case ClkResetCec0: + case ClkResetCec1: + bFM_CLK_GATING_MRST2_CECRST = 1u; + break; +#else + case ClkResetCec0: +#if defined(bFM_CLK_GATING_MRST2_CECRST0) + bFM_CLK_GATING_MRST2_CECRST0 = 1u; +#endif + break; + case ClkResetCec1: +#if defined(bFM_CLK_GATING_MRST2_CECRST1) + bFM_CLK_GATING_MRST2_CECRST1 = 1u; +#endif + break; +#endif + case ClkResetIcc0: +#if defined(bFM_CLK_GATING_MRST2_ICCRST0) + bFM_CLK_GATING_MRST2_ICCRST0 = 1u; +#endif + break; + case ClkResetIcc1: +#if defined(bFM_CLK_GATING_MRST2_ICCRST1) + bFM_CLK_GATING_MRST2_ICCRST1 = 1u; +#endif + break; + case ClkResetI2sl0: +#if defined(bFM_CLK_GATING_MRST2_IISCRST0) + bFM_CLK_GATING_MRST2_IISCRST0 = 1u; +#endif + break; + case ClkResetI2sl1: +#if defined(bFM_CLK_GATING_MRST2_IISCRST1) + FM_CLK_GATING->MRST2_f.IISCRST1 = 1u; +#endif + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} // Clk_PeripheralSetReset + +/** + ****************************************************************************** + ** \brief Clear reset bit a peripheral + ** + ** This function clears the corresponding bit in the MRSTn register to release + ** a peripheral from reset state. + ** + ** \param enPeripheral Enumerator of a peripheral, see + ** #en_clk_reset_peripheral_t for details + ** + ** \retval Ok Peripheral clock enabled + ** \retval ErrorInvalidParameter Peripheral enumerator does not exist + ******************************************************************************/ +en_result_t Clk_PeripheralClearReset(en_clk_reset_peripheral_t enPeripheral) +{ + switch (enPeripheral) + { + case ClkResetDma: +#if defined(bFM_CLK_GATING_MRST0_DMARST) + bFM_CLK_GATING_MRST0_DMARST = 0u; +#endif + break; + case ClkResetAdc0: +#if defined(bFM_CLK_GATING_MRST0_ADCRST0) + bFM_CLK_GATING_MRST0_ADCRST0 = 0u; +#endif + break; + case ClkResetAdc1: +#if defined(bFM_CLK_GATING_MRST0_ADCRST1) + bFM_CLK_GATING_MRST0_ADCRST1 = 0u; +#endif + break; + case ClkResetAdc2: +#if defined(bFM_CLK_GATING_MRST0_ADCRST2) + bFM_CLK_GATING_MRST0_ADCRST2 = 0u; +#endif + break; + case ClkResetAdc3: +#if defined(bFM_CLK_GATING_MRST0_ADCRST3) + bFM_CLK_GATING_MRST0_ADCRST3 = 0u; +#endif + break; + case ClkResetMfs0: +#if defined(bFM_CLK_GATING_MRST0_MFSRST0) + bFM_CLK_GATING_MRST0_MFSRST0 = 0u; +#endif + break; + case ClkResetMfs1: +#if defined(bFM_CLK_GATING_MRST0_MFSRST1) + bFM_CLK_GATING_MRST0_MFSRST1 = 0u; +#endif + break; + case ClkResetMfs2: +#if defined(bFM_CLK_GATING_MRST0_MFSRST2) + bFM_CLK_GATING_MRST0_MFSRST2 = 0u; +#endif + break; + case ClkResetMfs3: +#if defined(bFM_CLK_GATING_MRST0_MFSRST3) + bFM_CLK_GATING_MRST0_MFSRST3 = 0u; +#endif + break; + case ClkResetMfs4: +#if defined(bFM_CLK_GATING_MRST0_MFSRST4) + bFM_CLK_GATING_MRST0_MFSRST4 = 0u; +#endif + break; + case ClkResetMfs5: +#if defined(bFM_CLK_GATING_MRST0_MFSRST5) + bFM_CLK_GATING_MRST0_MFSRST5 = 0u; +#endif + break; + case ClkResetMfs6: +#if defined(bFM_CLK_GATING_MRST0_MFSRST6) + bFM_CLK_GATING_MRST0_MFSRST6 = 0u; +#endif + break; + case ClkResetMfs7: +#if defined(bFM_CLK_GATING_MRST0_MFSRST7) + bFM_CLK_GATING_MRST0_MFSRST7 = 0u; +#endif + break; + case ClkResetMfs8: +#if defined(bFM_CLK_GATING_MRST0_MFSRST8) + bFM_CLK_GATING_MRST0_MFSRST8 = 0u; +#endif + break; + case ClkResetMfs9: +#if defined(bFM_CLK_GATING_MRST0_MFSRST9) + bFM_CLK_GATING_MRST0_MFSRST9 = 0u; +#endif + break; + case ClkResetMfs10: +#if defined(bFM_CLK_GATING_MRST0_MFSRST10) + bFM_CLK_GATING_MRST0_MFSRST10 = 0u; +#endif + break; + case ClkResetMfs11: +#if defined(bFM_CLK_GATING_MRST0_MFSRST11) + bFM_CLK_GATING_MRST0_MFSRST11 = 0u; +#endif + break; + case ClkResetMfs12: +#if defined(bFM_CLK_GATING_MRST0_MFSRST12) + bFM_CLK_GATING_MRST0_MFSRST12 = 0u; +#endif + break; + case ClkResetMfs13: +#if defined(bFM_CLK_GATING_MRST0_MFSRST13) + bFM_CLK_GATING_MRST0_MFSRST13 = 0u; +#endif + break; + case ClkResetMfs14: +#if defined(bFM_CLK_GATING_MRST0_MFSRST14) + bFM_CLK_GATING_MRST0_MFSRST14 = 0u; +#endif + break; + case ClkResetMfs15: +#if defined(bFM_CLK_GATING_MRST0_MFSRST15) + bFM_CLK_GATING_MRST0_MFSRST15 = 0u; +#endif + break; + case ClkResetQprc0: +#if defined(bFM_CLK_GATING_MRST1_QDURST0) + bFM_CLK_GATING_MRST1_QDURST0 = 0u; +#endif + break; + case ClkResetQprc1: +#if defined(bFM_CLK_GATING_MRST1_QDURST1) + bFM_CLK_GATING_MRST1_QDURST1 = 0u; +#endif + break; + case ClkResetQprc2: +#if defined(bFM_CLK_GATING_MRST1_QDURST2) + bFM_CLK_GATING_MRST1_QDURST2 = 0u; +#endif + break; + case ClkResetQprc3: +#if defined(bFM_CLK_GATING_MRST1_QDURST3) + bFM_CLK_GATING_MRST1_QDURST3 = 0u; +#endif + break; + case ClkResetMft0: +#if defined(bFM_CLK_GATING_MRST1_MFTRST0) + bFM_CLK_GATING_MRST1_MFTRST0 = 0u; +#endif + break; + case ClkResetMft1: +#if defined(bFM_CLK_GATING_MRST1_MFTRST1) + bFM_CLK_GATING_MRST1_MFTRST1 = 0u; +#endif + break; + case ClkResetMft2: +#if defined(bFM_CLK_GATING_MRST1_MFTRST2) + bFM_CLK_GATING_MRST1_MFTRST2 = 0u; +#endif + break; + case ClkResetMft3: +#if defined(bFM_CLK_GATING_MRST1_MFTRST3) + bFM_CLK_GATING_MRST1_MFTRST3 = 0u; +#endif + break; + case ClkResetBt0123: +#if defined(bFM_CLK_GATING_MRST1_BTMRST0) + bFM_CLK_GATING_MRST1_BTMRST0 = 0u; +#endif + break; + case ClkResetBt4567: +#if defined(bFM_CLK_GATING_MRST1_BTMRST1) + bFM_CLK_GATING_MRST1_BTMRST1 = 0u; +#endif + break; + case ClkResetBt891011: +#if defined(bFM_CLK_GATING_MRST1_BTMRST2) + bFM_CLK_GATING_MRST1_BTMRST2 = 0u; +#endif + break; + case ClkResetBt12131415: +#if defined(bFM_CLK_GATING_MRST1_BTMRST3) + bFM_CLK_GATING_MRST1_BTMRST3 = 0u; +#endif + break; + case ClkResetExtif: +#if defined(bFM_CLK_GATING_MRST0_EXBRST) + FM_CLK_GATING->MRST0_f.EXBRST = 0u; +#endif + break; + case ClkResetUsb0: +#if defined(bFM_CLK_GATING_MRST2_USBRST0) + bFM_CLK_GATING_MRST2_USBRST0 = 0u; +#endif + break; + case ClkResetUsb1: +#if defined(bFM_CLK_GATING_MRST2_USBRST1) + bFM_CLK_GATING_MRST2_USBRST1 = 0u; +#endif + break; + case ClkResetSd: +#if defined(bFM_CLK_GATING_MRST2_SDCRST) + bFM_CLK_GATING_MRST2_SDCRST = 0u; +#endif + break; + case ClkResetI2s0: +#if defined(bFM_CLK_GATING_MRST2_I2SRST0) + bFM_CLK_GATING_MRST2_I2SRST0 = 0u; +#endif + break; + case ClkResetI2s1: +#if defined(bFM_CLK_GATING_MRST2_I2SRST1) + bFM_CLK_GATING_MRST2_I2SRST1 = 0u; +#endif + break; + case ClkResetPcrc: +#if defined(bFM_CLK_GATING_MRST2_PCRCRST) + bFM_CLK_GATING_MRST2_PCRCRST = 0u; +#endif + break; + case ClkResetQspi: +#if defined(bFM_CLK_GATING_MRST2_HSSPIRST) + bFM_CLK_GATING_MRST2_HSSPIRST = 0u; +#endif + break; + case ClkResetCan0: +#if defined(bFM_CLK_GATING_MRST2_CANRST0) + bFM_CLK_GATING_MRST2_CANRST0 = 0u; +#endif + break; + case ClkResetCan1: +#if defined(bFM_CLK_GATING_MRST2_CANRST1) + bFM_CLK_GATING_MRST2_CANRST1 = 0u; +#endif + break; + case ClkResetCan2: +#if defined(bFM_CLK_GATING_MRST2_CANRST2) + bFM_CLK_GATING_MRST2_CANRST2 = 0u; +#endif + break; +#if defined(bFM_CLK_GATING_MRST2_CECRST) + case ClkResetCec0: + case ClkResetCec1: + bFM_CLK_GATING_MRST2_CECRST = 0u; + break; +#else + case ClkResetCec0: +#if defined(bFM_CLK_GATING_MRST2_CECRST0) + bFM_CLK_GATING_MRST2_CECRST0 = 0u; +#endif + break; + case ClkResetCec1: +#if defined(bFM_CLK_GATING_MRST2_CECRST1) + bFM_CLK_GATING_MRST2_CECRST1 = 0u; +#endif + break; +#endif + case ClkResetIcc0: +#if defined(bFM_CLK_GATING_MRST2_ICCRST0) + bFM_CLK_GATING_MRST2_ICCRST0 = 0u; +#endif + break; + case ClkResetIcc1: +#if defined(bFM_CLK_GATING_MRST2_ICCRST1) + bFM_CLK_GATING_MRST2_ICCRST1 = 0u; +#endif + break; + case ClkResetI2sl0: +#if defined(bFM_CLK_GATING_MRST2_IISCRST0) + bFM_CLK_GATING_MRST2_IISCRST0 = 0u; +#endif + break; + case ClkResetI2sl1: +#if defined(bFM_CLK_GATING_MRST2_IISCRST1) + FM_CLK_GATING->MRST2_f.IISCRST1 = 0u; +#endif + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} // Clk_PeripheralClearReset + +#endif + +#endif // #if (defined(PDL_PERIPHERAL_ENABLE_CLK)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.h new file mode 100644 index 0000000000..760cfc034a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/clk/clk.h @@ -0,0 +1,557 @@ +/****************************************************************************** +* \file clk.h +* +* \version 1.20 +* +* \brief Header file of Clock functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __CLK_H__ +#define __CLK_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_CLK_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupCLK Clock Functions (CLK) +* \{ +* \defgroup GroupCLK_Macros Macros +* \defgroup GroupCLK_Types Enumerated Types +* \defgroup GroupCLK_DataStructures Data Structures +* \defgroup GroupCLK_GlobalVariables Global Variables +* \defgroup GroupCLK_Functions Functions +* \} +*/ + +/** +* \addtogroup GroupCLK +* The clock generation unit generates various types of clocks that can be used +* to operate the MCU. There are five possible source clocks:
+* - Main clock (CLKMO)
+* - Sub clock (CLKSO)
+* - High-speed CR clock (CLKHC)
+* - Low-speed CR clock (CLKLC)
+* - Main PLL clock (CLKPLL)
+* Select one of the source clocks to be the master clock. You divide the master clock frequency to +* generate internal bus clocks. There are five internal bus clocks:
+* - Base clock (FCLK/HCLK)
+* - APB0 bus clock (PCLK0)
+* - APB1 bus clock (PCLK1)
+* - APB2 bus clock (PCLK2)
+* - TRACE clock (TPIUCLK)
+* +* \section SectionCLK_ConfigurationConsideration Configuration Consideration +* The data sheet for a particular series specifies the +* "Internal operating clock frequency: Fcc (Base clock HCLK/FCLK)" +* for a CPU. The master clock value should not be larger than the maximum value of the Internal operating clock frequency.
+* Specify the source clock by calling Clk_SetSource(). You can use API function calls to enable or disable any source clock.
+* To set up bus clocks, provide configuration parameters in the stc_clk_config_t structure. For example, you specify dividers for +* each of the internal bus clocks, including the base clock. You also set values for the main PLL clock. Then call Clk_Init().
+* +* Detailed information for each of the internal bus clocks:
+* - Base clock (HCLK/FCLK) +* HCLK and FCLK are collectively called the base clock. Both HCLK and FCLK are +* supplied to the CPU. +* HCLK is the clock for peripherals connected to the AHB bus. +* The clock frequency can be set to between 1/1 and 1/16 frequency of the +* master clock. This clock stops in timer mode, RTC mode, stop mode, deep +* standby RTC mode, and deep standby stop mode. In sleep mode, the CPU stops +* the supply of HCLK while continuing the supply of FCLK.
+* - APB0 bus clock (PCLK0) +* PCLK0 is the clock for peripherals connected to the APB0 bus. +* The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. +* This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, +* and deep standby stop mode.
+* - APB1 bus clock (PCLK1) +* PCLK1 is the clock for peripherals connected to the APB1 bus. +* The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. +* This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, +* and deep standby stop mode.
+* - APB2 bus clock (PLCK2) +* PCLK2 is the clock for peripherals connected to the APB2 bus. +* The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. +* This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode, and deep standby stop mode.
+* - TRACE clock (TPIUCLK) +* This is the clock for TRACE. +* The clock frequency can be set to between 1/1 and 1/8 frequency of the base clock. +* This clock stops in timer mode, RTC mode, stop mode, deep standby RTC mode and deep standby stop mode. +* This clock output is enabled only for products equipped with Embedded Trace Macrocell.
+* +* \section SectionCLK_MoreInfo More Information +For more information on the CLK peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem
+* FM4 Peripheral Manual Core Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupCLK_Macros +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +// PLL Input Clock Select (PINC) Bit Position +#define FM_PSW_TMR_PINC_BITPOS 0x10u + +// Interrupt enable bitpositions in INT_ENR +#define FM_INT_ENR_PCSE_BITPOS 0x04u +#define FM_INT_ENR_SCSE_BITPOS 0x02u +#define FM_INT_ENR_MCSE_BITPOS 0x01u + +// Interrupt status bitpositions in INT_STR +#define FM_INT_STR_PCSI_BITPOS 0x04u +#define FM_INT_STR_SCSI_BITPOS 0x02u +#define FM_INT_STR_MCSI_BITPOS 0x01u + +// Interrupt ckear bitpositions in INT_CLR +#define FM_INT_CLR_PCSC_BITPOS 0x04u +#define FM_INT_CLR_SCSC_BITPOS 0x02u +#define FM_INT_CLR_MCSC_BITPOS 0x01u + +/** \} GroupCLK_Macros */ + +/** +* \addtogroup GroupCLK_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Clock Source + ** + ** Differentiator for the different clock sources + ** + ** \note The enumerated values do not correspond to the RCS/RCM bits of the + ** clock control and status registers due to having upward compatibility, + ** if this bit coding may change in future devices. The correct bit + ** patterns are set by switch(en_clk_source)/case statements individually + ** in the corresponding function(s). + ******************************************************************************/ +typedef enum en_clk_source +{ + ClkMain = 0u, ///< Main Clock Oscillator + ClkSub = 1u, ///< Sub Clock Oscillator + ClkHsCr = 2u, ///< High-Speed CR Clock Oscillator + ClkLsCr = 3u, ///< Low-Speed CR Clock Oscillator + ClkPll = 4u, ///< PLL Clock + ClkHsCrPll = 5u ///< High-Speed CR PLL Clock +} en_clk_source_t; + +/** + ****************************************************************************** + ** \brief Base Clock Prescaler Settings + ** + ** Enumeration of the dividers of the Base Clock (HCLK) + ******************************************************************************/ +typedef enum en_clk_baseclkdiv +{ + BaseClkDiv1 = 0u, ///< HCLK Division 1/1 + BaseClkDiv2 = 1u, ///< HCLK Division 1/2 + BaseClkDiv3 = 2u, ///< HCLK Division 1/3 + BaseClkDiv4 = 3u, ///< HCLK Division 1/4 + BaseClkDiv6 = 4u, ///< HCLK Division 1/6 + BaseClkDiv8 = 5u, ///< HCLK Division 1/8 + BaseClkDiv16 = 6u, ///< HCLK Division 1/16 + BaseClkErr = 7u ///< HCLK prohibited setting +} en_clk_baseclkdiv_t; + +/** + ****************************************************************************** + ** \brief APB0 Prescaler Settings + ** + ** Enumeration of the dividers of the APB0 (PCLK0) + ******************************************************************************/ +typedef enum en_clk_apb0div +{ + Apb0Div1 = 0u, ///< PCLK0 Division 1/1 + Apb0Div2 = 1u, ///< PCLK0 Division 1/2 + Apb0Div4 = 2u, ///< PCLK0 Division 1/4 + Apb0Div8 = 3u ///< PCLK0 Division 1/8 +} en_clk_apb0div_t; + +/** + ****************************************************************************** + ** \brief APB1 Prescaler Settings + ** + ** Enumeration of the dividers of the APB0 (PCLK1) + ******************************************************************************/ +typedef enum en_clk_apb1div +{ + Apb1Div1 = 0u, ///< PCLK1 Division 1/1 + Apb1Div2 = 1u, ///< PCLK1 Division 1/2 + Apb1Div4 = 2u, ///< PCLK1 Division 1/4 + Apb1Div8 = 3u ///< PCLK1 Division 1/8 +} en_clk_apb1div_t; + +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +/** + ****************************************************************************** + ** \brief APB2 Prescaler Settings + ** + ** Enumeration of the dividers of the APB0 (PCLK2) + ******************************************************************************/ +typedef enum en_clk_apb2div +{ + Apb2Div1 = 0u, ///< PCLK2 Division 1/1 + Apb2Div2 = 1u, ///< PCLK2 Division 1/2 + Apb2Div4 = 2u, ///< PCLK2 Division 1/4 + Apb2Div8 = 3u ///< PCLK2 Division 1/8 +} en_clk_apb2div_t; +#endif + +/** + ****************************************************************************** + ** \brief Sub Clock oscillation stablilization wait time + ** + ** Enumeration for the Sub Clock oscillation stabilization wait time settings + ******************************************************************************/ +typedef enum en_clk_scowaittime +{ + ScoWaitExp10 = 0u, ///< 2^10 / F(CL) => ~10.3 ms + ScoWaitExp11 = 1u, ///< 2^11 / F(CL) => ~20.5 ms + ScoWaitExp12 = 2u, ///< 2^12 / F(CL) => ~41 ms + ScoWaitExp13 = 3u, ///< 2^13 / F(CL) => ~82 ms + ScoWaitExp14 = 4u, ///< 2^14 / F(CL) => ~164 ms + ScoWaitExp15 = 5u, ///< 2^15 / F(CL) => ~327 ms + ScoWaitExp16 = 6u, ///< 2^16 / F(CL) => ~655 ms + ScoWaitExp17 = 7u, ///< 2^17 / F(CL) => ~1.31 s + ScoWaitExp18 = 8u, ///< 2^17 / F(CL) => ~2.62 s + ScoWaitExp19 = 9u, ///< 2^17 / F(CL) => ~5.24 s + ScoWaitExp20 = 10u, ///< 2^17 / F(CL) => ~10.48 s + ScoWaitExp21 = 11u, ///< 2^17 / F(CL) => ~20.96 s + ScoWaitErr = 12u ///< Prohibited Setting +} en_clk_scowaittime_t; + +/** + ****************************************************************************** + ** \brief Main Clock oscillation stablilization wait time + ** + ** Enumeration for the Main Clock oscillation stabilization wait time settings + ******************************************************************************/ +typedef enum en_clk_mcowaittime +{ + McoWaitExp11 = 0u, ///< 2^1 / F(CH) => ~500 ns (F(CH) = 4 MHz) + McoWaitExp15 = 1u, ///< 2^5 / F(CH) => ~8 us (F(CH) = 4 MHz) + McoWaitExp16 = 2u, ///< 2^6 / F(CH) => ~16 us (F(CH) = 4 MHz) + McoWaitExp17 = 3u, ///< 2^7 / F(CH) => ~32 us (F(CH) = 4 MHz) + McoWaitExp18 = 4u, ///< 2^8 / F(CH) => ~64 us (F(CH) = 4 MHz) + McoWaitExp19 = 5u, ///< 2^9 / F(CH) => ~128 us (F(CH) = 4 MHz) + McoWaitExp110 = 6u, ///< 2^10 / F(CH) => ~256 us (F(CH) = 4 MHz) + McoWaitExp111 = 7u, ///< 2^11 / F(CH) => ~512 us (F(CH) = 4 MHz) + McoWaitExp112 = 8u, ///< 2^12 / F(CH) => ~1.0 ms (F(CH) = 4 MHz) + McoWaitExp113 = 9u, ///< 2^13 / F(CH) => ~2.0 ms (F(CH) = 4 MHz) + McoWaitExp114 = 10u, ///< 2^14 / F(CH) => ~4.0 ms (F(CH) = 4 MHz) + McoWaitExp115 = 11u, ///< 2^15 / F(CH) => ~8.0 ms (F(CH) = 4 MHz) + McoWaitExp117 = 12u, ///< 2^17 / F(CH) => ~33.0 ms (F(CH) = 4 MHz) + McoWaitExp119 = 13u, ///< 2^18 / F(CH) => ~131 ms (F(CH) = 4 MHz) + McoWaitExp121 = 14u, ///< 2^21 / F(CH) => ~524 ms (F(CH) = 4 MHz) + McoWaitExp123 = 15u ///< 2^23 / F(CH) => ~2.0 s (F(CH) = 4 MHz) +} en_clk_mcowaittime_t; + +/** + ****************************************************************************** + ** \brief PLL Clock oscillation stablilization wait time + ** + ** Enumeration for the PLL Clock oscillation stabilization wait time settings + ******************************************************************************/ +typedef enum en_clk_pllowaittime +{ + PlloWaitExp19 = 0u, ///< 2^9 / F(CH) => ~128 us (F(CH) = 4 MHz) + PlloWaitExp110 = 1u, ///< 2^10 / F(CH) => ~256 us (F(CH) = 4 MHz) + PlloWaitExp111 = 2u, ///< 2^11 / F(CH) => ~512 us (F(CH) = 4 MHz) + PlloWaitExp112 = 3u, ///< 2^12 / F(CH) => ~1.02 ms (F(CH) = 4 MHz) + PlloWaitExp113 = 4u, ///< 2^13 / F(CH) => ~2.05 ms (F(CH) = 4 MHz) + PlloWaitExp114 = 5u, ///< 2^14 / F(CH) => ~4.10 ms (F(CH) = 4 MHz) + PlloWaitExp115 = 6u, ///< 2^15 / F(CH) => ~8.20 ms (F(CH) = 4 MHz) + PlloWaitExp116 = 7u ///< 2^16 / F(CH) => ~16.4 ms (F(CH) = 4 MHz) +} en_clk_pllowaittime_t; + +/** + ****************************************************************************** + ** \brief PLL SourceClock (PINC bit of PSW_TMR) + ** + ** Enumeration for the PLL Clock Source. + ** + ** \attention HS-RC source only available, if used device supports PLL-CLKHC + ** setting! PINC bit availability is not checked in this + ** driver! + ******************************************************************************/ +typedef enum en_clk_pll_src +{ + PllSrcClkMo = 0u, ///< Use Main Clock as PLL source (always available, default) + PllSrcClkHc = 123u ///< Use HS-RC Clock as PLL source (only if available!) +} en_clk_pll_src_t; + +/** + ****************************************************************************** + ** \brief Clock Gate peripheral enumerators + ** + ** \note Though all peripherals are listed here, it doesn't mean a certain + ** product has all these peripheral, please check the at "product lineup" + ** section in the product data sheet for which peripheral are available. + ******************************************************************************/ +typedef enum en_clk_gate_peripheral +{ + ClkGateGpio = 0u, ///< GPIO clock gate + ClkGateExtif = 1u, ///< External bus clock gate + ClkGateDma = 2u, ///< DMA clock gate + ClkGateAdc0 = 3u, ///< ADC0 clock gate + ClkGateAdc1 = 4u, ///< ADC1 clock gate + ClkGateAdc2 = 5u, ///< ADC2 clock gate + ClkGateAdc3 = 6u, ///< ADC3 clock gate + ClkGateMfs0 = 7u, ///< MFS0 clock gate + ClkGateMfs1 = 8u, ///< MFS1 clock gate + ClkGateMfs2 = 9u, ///< MFS2 clock gate + ClkGateMfs3 = 10u, ///< MFS3 clock gate + ClkGateMfs4 = 11u, ///< MFS4 clock gate + ClkGateMfs5 = 12u, ///< MFS5 clock gate + ClkGateMfs6 = 13u, ///< MFS6 clock gate + ClkGateMfs7 = 14u, ///< MFS7 clock gate + ClkGateMfs8 = 15u, ///< MFS8 clock gate + ClkGateMfs9 = 16u, ///< MFS9 clock gate + ClkGateMfs10 = 17u, ///< MFS10 clock gate + ClkGateMfs11 = 18u, ///< MFS11 clock gate + ClkGateMfs12 = 19u, ///< MFS12 clock gate + ClkGateMfs13 = 20u, ///< MFS13 clock gate + ClkGateMfs14 = 21u, ///< MFS14 clock gate + ClkGateMfs15 = 22u, ///< MFS15 clock gate + ClkGateQprc0 = 23u, ///< QPRC0 clock gate + ClkGateQprc1 = 24u, ///< QPRC1 clock gate + ClkGateQprc2 = 25u, ///< QPRC2 clock gate + ClkGateQprc3 = 26u, ///< QPRC3 clock gate + ClkGateMft0 = 27u, ///< MFT0, PPG0/2/4/6 clock gate + ClkGateMft1 = 28u, ///< MFT1, PPG8/10/12/14 clock gate + ClkGateMft2 = 29u, ///< MFT2, PPG16/18/20/22 clock gate + ClkGateMft3 = 30u, ///< MFT3, PPG24/26/28/30 clock gate + ClkGateBt0123 = 31u, ///< BT0/1/2/3 clock gate + ClkGateBt4567 = 32u, ///< BT4/5/6/7 clock gate + ClkGateBt891011 = 33u, ///< BT8/9/10/11 clock gate + ClkGateBt12131415 = 34u, ///< BT12/13/14/15 clock gate + ClkGateQspi = 35u, ///< Quad SPI clock gate + ClkGateCec0 = 36u, ///< HDMI-CEC0 clock gate + ClkGateCec1 = 37u, ///< HDMI-CEC1 clock gate + ClkGatePcrc = 38u, ///< CRC clock gate + ClkGateI2s0 = 39u, ///< I2S0 clock gate + ClkGateI2s1 = 40u, ///< I2S1 clock gate + ClkGateSd = 41u, ///< SD clock gate + ClkGateCan0 = 42u, ///< CAN0 clock gate + ClkGateCan1 = 43u, ///< CAN1 clock gate + ClkGateCan2 = 44u, ///< CAN2 clock gate + ClkGateUsb0 = 45u, ///< USB0 clock gate + ClkGateUsb1 = 46u, ///< USB1 clock gate + ClkGateIcc0 = 47u, ///< IC-Card interface 0 + ClkGateIcc1 = 48u, ///< IC-Card interface 1 + ClkGateI2sl0 = 49u, ///< I2S-Lite 0 + ClkGateI2sl1 = 50u, ///< I2S-Lite 1 +} en_clk_gate_peripheral_t; + +/** + ****************************************************************************** + ** \brief Reset peripheral enumerators + ** + ** \note Though all peripherals are listed here, it doesn't mean a certain + ** product has all these peripheral, please check the at "product lineup" + ** section in the product data sheet for which peripheral are available. + ******************************************************************************/ +typedef enum en_clk_reset_peripheral +{ + ClkResetExtif = 1u, ///< External bus Reset + ClkResetDma = 2u, ///< DMA Reset + ClkResetAdc0 = 3u, ///< ADC0 Reset + ClkResetAdc1 = 4u, ///< ADC1 Reset + ClkResetAdc2 = 5u, ///< ADC2 Reset + ClkResetAdc3 = 6u, ///< ADC3 Reset + ClkResetMfs0 = 7u, ///< MFS0 Reset + ClkResetMfs1 = 8u, ///< MFS1 Reset + ClkResetMfs2 = 9u, ///< MFS2 Reset + ClkResetMfs3 = 10u, ///< MFS3 Reset + ClkResetMfs4 = 11u, ///< MFS4 Reset + ClkResetMfs5 = 12u, ///< MFS5 Reset + ClkResetMfs6 = 13u, ///< MFS6 Reset + ClkResetMfs7 = 14u, ///< MFS7 Reset + ClkResetMfs8 = 15u, ///< MFS8 Reset + ClkResetMfs9 = 16u, ///< MFS9 Reset + ClkResetMfs10 = 17u, ///< MFS10 Reset + ClkResetMfs11 = 18u, ///< MFS11 Reset + ClkResetMfs12 = 19u, ///< MFS12 Reset + ClkResetMfs13 = 20u, ///< MFS13 Reset + ClkResetMfs14 = 21u, ///< MFS14 Reset + ClkResetMfs15 = 22u, ///< MFS15 Reset + ClkResetQprc0 = 23u, ///< QPRC0 Reset + ClkResetQprc1 = 24u, ///< QPRC1 Reset + ClkResetQprc2 = 25u, ///< QPRC2 Reset + ClkResetQprc3 = 26u, ///< QPRC3 Reset + ClkResetMft0 = 27u, ///< MFT0, PPG0/2/4/6 Reset + ClkResetMft1 = 28u, ///< MFT1, PPG8/10/12/14 Reset + ClkResetMft2 = 29u, ///< MFT2, PPG16/18/20/22 Reset + ClkResetMft3 = 30u, ///< MFT3, PPG24/26/28/30 Reset + ClkResetBt0123 = 31u, ///< BT0/1/2/3 Reset + ClkResetBt4567 = 32u, ///< BT4/5/6/7 Reset + ClkResetBt891011 = 33u, ///< BT8/9/19/11 Reset + ClkResetBt12131415 = 34u, ///< BT12/13/14/15 Reset + ClkResetQspi = 35u, ///< Quad SPI Reset + ClkResetCec0 = 36u, ///< CEC0 Reset + ClkResetCec1 = 37u, ///< CEC1 Reset + ClkResetPcrc = 38u, ///< Programmable CRC Reset + ClkResetI2s0 = 39u, ///< I2S0 Reset + ClkResetI2s1 = 40u, ///< I2S1 Reset + ClkResetSd = 41u, ///< SD Card I/F Reset + ClkResetCan0 = 42u, ///< CAN0 Reset + ClkResetCan1 = 43u, ///< CAN1 Reset + ClkResetCan2 = 44u, ///< CAN2 Reset + ClkResetUsb0 = 45u, ///< USB0 Reset + ClkResetUsb1 = 46u, ///< USB1 Reset + ClkResetIcc0 = 47u, ///< IC-Card interface 0 + ClkResetIcc1 = 48u, ///< IC-Card interface 1 + ClkResetI2sl0 = 49u, ///< I2S-Lite 0 + ClkResetI2sl1 = 50u, ///< I2S-Lite 1 +} en_clk_reset_peripheral_t; + +/** \}GroupCLK_Types */ + +/** +* \addtogroup GroupCLK_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Datatype for holding internal data needed for CLK + ******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) +typedef struct stc_clk_intern_data +{ + func_ptr_t pfnPllStabCb; ///< PLL stabilization callback function pointer + func_ptr_t pfnScoStabCb; ///< Sub Clock stabilization callback function pointer + func_ptr_t pfnMcoStabCb; ///< Main Clock stabilization callback function pointer +} stc_clk_intern_data_t ; +#endif + +/** + ****************************************************************************** + ** \brief Clock configuration + ** + ** The Clock configuration settings + ******************************************************************************/ +typedef struct stc_clk_config +{ + en_clk_baseclkdiv_t enBaseClkDiv; ///< See description of #en_clk_baseclkdiv_t + en_clk_apb0div_t enAPB0Div; ///< See description of #en_clk_apb0div_t + en_clk_apb1div_t enAPB1Div; ///< See description of #en_clk_apb1div_t +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + en_clk_apb2div_t enAPB2Div; ///< See description of #en_clk_apb2div_t +#endif + boolean_t bAPB1Disable; ///< TRUE: Disables APB1 regardless of divider settings +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + boolean_t bAPB2Disable; ///< TRUE: Disables APB2 regardless of divider settings +#endif + en_clk_mcowaittime_t enMCOWaitTime; ///< See description of #en_clk_mcowaittime_t + en_clk_scowaittime_t enSCOWaitTime; ///< See description of #en_clk_scowaittime_t + en_clk_pllowaittime_t enPLLOWaitTime; ///< See description of #en_clk_pllowaittime_t + uint8_t u8PllK; ///< PLL input clock frequency division ratio, PLLK + uint8_t u8PllM; ///< PLL VCO clock frequency division ratio, PLLM + uint8_t u8PllN; ///< PLL feedback frequency division ration, PLLN +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) + boolean_t bPllIrq; ///< TRUE: enable PLL oscillation stabilization completion interrupt + boolean_t bMcoIrq; ///< TRUE: enable Main Clock oscillation stabilization completion interrupt + boolean_t bScoIrq; ///< TRUE: enable Sub Clock oscillation stabilization completion interrupt + func_ptr_t pfnPllStabCb; ///< PLL stabilization callback function pointer + func_ptr_t pfnMcoStabCb; ///< Main Clock stabilization callback function pointer + func_ptr_t pfnScoStabCb; ///< Sub Clock stabilization callback function pointer +#endif +} stc_clk_config_t; + +/** \} GroupCLK_DataStructures */ + +/** +* \addtogroup GroupCLK_GlobalVariables +* \{ +*/ +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) +extern stc_clk_intern_data_t stcClkInternData; +#endif + +/** \} GroupCLK_GlobalVariables */ +/** +* \addtogroup GroupCLK_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +#if (PDL_INTERRUPT_ENABLE_CLK == PDL_ON) +void Clk_IrqHandler(void) ; +#endif +/* Set clock dividor, wait time, interrupt */ +en_result_t Clk_Init(const stc_clk_config_t* pstcClk) ; +/* Clock enable/disable */ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +en_result_t Clk_EnableHscr(boolean_t bBlock); +en_result_t Clk_DisableHscr(void); +#endif +en_result_t Clk_EnableMainClock(boolean_t bBlock); +en_result_t Clk_DisableMainClock(void); +en_result_t Clk_EnableSubClock(boolean_t bBlock); +en_result_t Clk_DisableSubClock(void); +en_result_t Clk_EnablePllClock(boolean_t bBlock); +en_result_t Clk_DisablePllClock(void); +/* Set the source clock */ +en_result_t Clk_SetSource(en_clk_source_t enSource); +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +/* Peripheral clock enable/disable/status read */ +en_result_t Clk_PeripheralClockEnable(en_clk_gate_peripheral_t enPeripheral) ; +en_result_t Clk_PeripheralClockDisable(en_clk_gate_peripheral_t enPeripheral) ; +boolean_t Clk_PeripheralGetClockState(en_clk_gate_peripheral_t enPeripheral) ; +en_result_t Clk_PeripheralClockEnableAll(void) ; +en_result_t Clk_PeripheralClockDisableAll(void) ; +/* Peripheral set reset/release reset */ +en_result_t Clk_PeripheralSetReset(en_clk_reset_peripheral_t enPeripheral) ; +en_result_t Clk_PeripheralClearReset(en_clk_reset_peripheral_t enPeripheral) ; +#endif + +/** \} GroupCLK_Functions */ +/** \} GroupCLK */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_CLK_ACTIVE)) + +#endif /* __CLK_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.c new file mode 100644 index 0000000000..f75da87dcb --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.c @@ -0,0 +1,197 @@ +/****************************************************************************** +* \file cr.c +* +* \version 1.20 +* +* \brief High-speed Clock Rate driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "cr/cr.h" + +#if (defined(PDL_PERIPHERAL_CR_ACTIVE)) + + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define CR_REG_UNLOCK_CODE 0x1ACCE554u +#define CR_REG_LOCK_CODE 0u + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Set the frequency division of CR output to Base timer + ** + ** \param [in] enCrDiv CR division + ** \arg CrFreqDivBy4 + ** \arg CrFreqDivBy8 + ** \arg CrFreqDivBy16 + ** \arg CrFreqDivBy32 + ** \arg CrFreqDivBy64 + ** \arg CrFreqDivBy128 + ** \arg CrFreqDivBy256 + ** \arg CrFreqDivBy512 + ** + ** \retval Ok Set the frequency division successfully + ** \retval ErrorInvalidParameter enCrDiv > CrFreqDivBy512 + ** + ** \note The division values of 64,128,256,512 are only supported by FM3 TYPE3, + ** TYPE7, FM4 and FM0+ products. + ** + ******************************************************************************/ +en_result_t Cr_SetFreqDiv(en_cr_freq_div_t enCrDiv) +{ + switch (enCrDiv) + { + case CrFreqDivBy4: + FM_CRTRIM->MCR_PSR = 0u; + break; + case CrFreqDivBy8: + FM_CRTRIM->MCR_PSR = 1u; + break; + case CrFreqDivBy16: + FM_CRTRIM->MCR_PSR = 2u; + break; + case CrFreqDivBy32: + FM_CRTRIM->MCR_PSR = 3u; + break; +#if (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case CrFreqDivBy64: + FM_CRTRIM->MCR_PSR = 4u; + break; + case CrFreqDivBy128: + FM_CRTRIM->MCR_PSR = 5u; + break; + case CrFreqDivBy256: + FM_CRTRIM->MCR_PSR = 6u; + break; + case CrFreqDivBy512: + FM_CRTRIM->MCR_PSR = 7u; + break; +#endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#if (PDL_MCU_TYPE == PDL_FM3_TYPE8) || (PDL_MCU_TYPE == PDL_FM3_TYPE9) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE10) || (PDL_MCU_TYPE == PDL_FM3_TYPE11) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE12) || (PDL_MCU_CORE == PDL_FM0P_CORE) || \ + (PDL_MCU_CORE == PDL_FM4_CORE) +/** + ****************************************************************************** + ** \brief Set CR temperature trimming register + ** + ** \param [in] u8Data temperature trimming value, only Bit[4:0] + ** is valid. + ** + ** \retval Ok Set the frequency division successfully + ** + ******************************************************************************/ +en_result_t Cr_SetTempTrimmingData(uint8_t u8Data) +{ + FM_CRTRIM->MCR_RLR = CR_REG_UNLOCK_CODE; + FM_CRTRIM->MCR_TTRM = u8Data & 0x1Fu; + FM_CRTRIM->MCR_RLR = CR_REG_LOCK_CODE; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get CR temperature trimming register + ** + ** \retval temperature trimming value, only Bit[4:0] is valid. + ** + ******************************************************************************/ +uint8_t Cr_GetTempTrimmingData(void) +{ + uint8_t u8CrTempData; + u8CrTempData = FM_CRTRIM->MCR_TTRM & 0x1Fu; + return u8CrTempData; +} + +#endif + +/** + ****************************************************************************** + ** \brief Set CR frequency trimming register + ** + ** \param [in] u16Data temperature trimming value, only Bit[9:0] + ** is valid. + ** + ** \retval Ok Set CR frequency trimming successfully + ** + ** \note The meaning of bit field of CR data is different among devices, see + ** peripheral manual for the details. + ** + ******************************************************************************/ +en_result_t Cr_SetFreqTrimmingData(uint16_t u16Data) +{ + FM_CRTRIM->MCR_RLR = CR_REG_UNLOCK_CODE; +#if (PDL_MCU_TYPE == PDL_FM3_TYPE1) || (PDL_MCU_TYPE == PDL_FM3_TYPE2) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE4) || (PDL_MCU_TYPE == PDL_FM3_TYPE5) + FM_CRTRIM->MCR_FTRM = u16Data & 0xFFu; +#else + FM_CRTRIM->MCR_FTRM = u16Data & 0x3FFu; +#endif + FM_CRTRIM->MCR_RLR = CR_REG_LOCK_CODE; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get frequency trimming register + ** + ** \retval temperature trimming value, only Bit[9:0] + ** is valid. + ** + ******************************************************************************/ +uint16_t Cr_GetFreqTrimmingData(void) +{ + uint16_t u16CrFreqData; +#if (PDL_MCU_TYPE == PDL_FM3_TYPE1) || (PDL_MCU_TYPE == PDL_FM3_TYPE2) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE4) || (PDL_MCU_TYPE == PDL_FM3_TYPE5) + u16CrFreqData = FM_CRTRIM->MCR_FTRM & 0xFFu; +#else + u16CrFreqData = FM_CRTRIM->MCR_FTRM & 0x3FFu; +#endif + return u16CrFreqData; +} + +#endif /* #if (defined(PDL_PERIPHERAL_CR_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.h new file mode 100644 index 0000000000..5cc6f71aec --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/cr/cr.h @@ -0,0 +1,147 @@ +/****************************************************************************** +* \file cr.h +* +* \version 1.20 +* +* \brief Headerfile for Clock Rate functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __CR_H__ +#define __CR_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_CR_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupCR High Speed Clock Rate Trimming (CR) +* \{ +* \defgroup GroupCR_Functions Functions +* \defgroup GroupCR_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupCR +* \{ +* The high-speed Clock Rate(CR) oscillators privides frequency trimming +* and oscillation temperature trimming.
+* CR oscillators may fluctuate because of process variation or temperature changes. +* You can reduce the impact of that fluctuation by using trimming functions. +* The High-Speed Clock Rate Trimming (CR) functions enable trimming for both frequency and temperature.
+* \section SectionCR_ConfigurationConsideration Configuration Consideration +* Use the functions in this peripheral to set or get either the frequency or temperature trimming values.
+* Trimming values are stored in flash memory. Erasing the flash memory also erases the CR trimming area inside the flash memory. +* If you use a value in the CR trimming area, save the data to other area (such as RAM) before erasing the flash memory, +* or only erase sectors other than in the CR trimming area. For the address of the CR trimming area, see the +* Flash Programming Manual for the product.
+* +* Cr_SetFreqDiv() is used to divde CR input signal, which outputs to base +* timer from dividor output.
+* +* Cr_SetTempTrimmingData() sets the CR temperature trimming data, and +* Cr_GetTempTrimmingData() gets the CR temperature trimming data. +* Not all devices has the temperature trimming register.
+* +* Cr_SetFreqTrimmingData() sets the CR frequency trimming data, and +* Cr_GetFreqTrimmingData() gets the CR frequency trimming data. +* \section SectionCR_MoreInfo More Information +* For more information on the high speed CR trimming peripheral, refer to:
+* FM0+ PERIPHERAL MANUAL Core Subsystem
+* FM4 PERIPHERAL MANUAL Core Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + + /** +* \addtogroup GroupCR_Types +* \{ +*/ +/** + ****************************************************************************** + ** \brief CR frequency division values + ** + ** \note The division signal is output to internal Base Timer or Multi-Function + ** Timer. The division values of 64,128,256,512 are only supported by + ** FM3 TYPE3, TYPE7, FM4 and FM0+ products. + ******************************************************************************/ +typedef enum en_cr_freq_div +{ + CrFreqDivBy4 = 0u, ///< CR output (to Base Timer) prescaler: 4 + CrFreqDivBy8 = 1u, ///< CR output (to Base Timer) prescaler: 8 + CrFreqDivBy16 = 2u, ///< CR output (to Base Timer) prescaler: 16 + CrFreqDivBy32 = 3u, ///< CR output (to Base Timer) prescaler: 32 +#if (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + CrFreqDivBy64 = 4u, ///< CR output (to Base Timer) prescaler: 64 + CrFreqDivBy128 = 5u, ///< CR output (to Base Timer) prescaler: 128 + CrFreqDivBy256 = 6u, ///< CR output (to Base Timer) prescaler: 256 + CrFreqDivBy512 = 7u, ///< CR output (to Base Timer) prescaler: 512 +#endif +}en_cr_freq_div_t; + +/** \}GroupCR_Types */ + +/** +* \addtogroup GroupCR_Functions +* \{ +*/ +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +en_result_t Cr_SetFreqDiv(en_cr_freq_div_t enCrDiv); +#if (PDL_MCU_TYPE == PDL_FM3_TYPE8) || (PDL_MCU_TYPE == PDL_FM3_TYPE9) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE10) || (PDL_MCU_TYPE == PDL_FM3_TYPE11) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE12) || (PDL_MCU_CORE == PDL_FM0P_CORE) || \ + (PDL_MCU_CORE == PDL_FM4_CORE) +en_result_t Cr_SetTempTrimmingData(uint8_t u8Data); +uint8_t Cr_GetTempTrimmingData(void); +#endif +en_result_t Cr_SetFreqTrimmingData(uint16_t u16Data); +uint16_t Cr_GetFreqTrimmingData(void); + +/** \} GroupCR_Functions */ +/** \} GroupCR */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_CR_ACTIVE)) */ + +#endif /* __CR_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.c new file mode 100644 index 0000000000..217cf60d0b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.c @@ -0,0 +1,231 @@ +/****************************************************************************** +* \file crc.C +* +* \version 1.20 +* +* \brief Cyclic Redundancy Check driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "crc/crc.h" + +#if (defined(PDL_PERIPHERAL_CRC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Initialisation of a CRC module. + ** + ** \param [in] pstcConfig CRC module configuration + ** + ** \retval Ok Initializiation of CRC module successfully + ** done. + ** \retval ErrorInvalidParameter pstcConfig == NULL, + ** parameter out of range + ******************************************************************************/ +en_result_t Crc_Init(const stc_crc_config_t* pstcConfig) +{ + en_result_t enResult; + stc_crc_crccr_field_t stcCRCCR; /* local preset of CRCCR */ + + /* Check for valid pointers */ + if (NULL == pstcConfig) + { + enResult = ErrorInvalidParameter; + } + else + { + enResult = Ok; + /* Check CRC mode select and setting */ + switch (pstcConfig->enMode) + { + case Crc16: + stcCRCCR.CRC32 = FALSE; + /* Mask the initial value for 16 bits */ + FM_CRC->CRCINIT = pstcConfig->u32CrcInitValue & 0x0000FFFFul; + break; + case Crc32: + stcCRCCR.CRC32 = TRUE; + FM_CRC->CRCINIT = pstcConfig->u32CrcInitValue; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + + if (Ok == enResult) + { + /* XOR is executed finaly or not */ + if (TRUE == pstcConfig->bFinalXor) + { + stcCRCCR.FXOR = TRUE; + } + else + { + stcCRCCR.FXOR = FALSE; + } + /* Bit order for CRC result */ + if (TRUE == pstcConfig->bResultLsbFirst) + { + stcCRCCR.CRCLSF = TRUE; + } + else + { + stcCRCCR.CRCLSF = FALSE; + } + /* Byte order for CRC result */ + if (TRUE == pstcConfig->bResultLittleEndian) + { + stcCRCCR.CRCLTE = TRUE; + } + else + { + stcCRCCR.CRCLTE = FALSE; + } + /* Bit order for DATA */ + if (TRUE == pstcConfig->bDataLsbFirst) + { + stcCRCCR.LSBFST = TRUE; + } + else + { + stcCRCCR.LSBFST = FALSE; + } + /* Byte order for DATA */ + if (TRUE == pstcConfig->bDataLittleEndian) + { + stcCRCCR.LTLEND = TRUE; + } + else + { + stcCRCCR.LTLEND = FALSE; + } + /* Initialize CRC configuration */ + stcCRCCR.INIT = TRUE; + + /* Write setting to CRC control register */ + FM_CRC->CRCCR_f = stcCRCCR; + } + } + + return (enResult); +} /* Crc_Init */ + + +/** + ****************************************************************************** + ** \brief De-Initialisation of a CRC module. + ** + ******************************************************************************/ +void Crc_DeInit(void) +{ + /* clear hardware */ + FM_CRC->CRCIN = 0u; + FM_CRC->CRCCR = 0u; + +} /* Crc_DeInit */ + +/** + ****************************************************************************** + ** \brief Push 8-bit integer data to a CRC module with if no DMA is used. + ** + ** \param [in] u8DataToPush 8-Bit data to be pushed to CRC + ** + ******************************************************************************/ +void Crc_Push8(uint8_t u8DataToPush) +{ + /* Caluculate CRC (Push 8bit data) */ + FM_CRC->CRCINLL = u8DataToPush; + +} /* Crc_Push8 */ + +/** + ****************************************************************************** + ** \brief Push 16-bit integer data to a CRC module with if no DMA is used. + ** + ** \note Be careful with the endianess. Byte swapping might have to be + ** performed before pushing 16-bit data. + ** + ** \param [in] u16DataToPush 16-Bit data to be pushed to CRC + ** + ******************************************************************************/ +void Crc_Push16(uint16_t u16DataToPush) +{ + /* Caluculate CRC (Push 16bit data) */ + FM_CRC->CRCINL = u16DataToPush; + +} /* Crc_Push16 */ + +/** + ****************************************************************************** + ** \brief Push 32-bit integer data to a CRC module with if no DMA is used. + ** + ** \param [in] u32DataToPush 32-Bit data to be pushed to CRC + ** + ******************************************************************************/ +void Crc_Push32(uint32_t u32DataToPush) +{ + /* Caluculate CRC (Push 32bit data) */ + FM_CRC->CRCIN = u32DataToPush; + +} /* Crc_Push32 */ + +/** + ****************************************************************************** + ** \brief Read CRC result register + ** + ** \note This function returns a 32-bit value regardless of a valid + ** pointer to the CRC instance anyhow. + ** + ** \retval value of CRC result + ** + ******************************************************************************/ +uint32_t Crc_ReadResult(void) +{ + /* Return value of CRC result register */ + return (FM_CRC->CRCR); +} /* Crc_ReadResult */ + + +#endif /* #if (defined(PDL_PERIPHERAL_CRC_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.h new file mode 100644 index 0000000000..e7b4a2d84e --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/crc/crc.h @@ -0,0 +1,176 @@ +/****************************************************************************** +* \file crc.h +* +* \version 1.20 +* +* \brief Headerfile for Cyclic Redundancy Check functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __CRC_H__ +#define __CRC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (FM_CRC_AVAILABLE == PDL_OFF) + #if (defined(PDL_PERIPHERAL_CRC_ACTIVE)) + #error "Don't enable CRC, as it is not available on this device" + #endif +#endif + +#if (defined(PDL_PERIPHERAL_CRC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/** +* \defgroup GroupCRC Cyclic Redundancy Check(CRC) +* \{ +* \defgroup GroupCRC_Functions Functions +* \defgroup GroupCRC_DataStructures Data Structures +* \defgroup GroupCRC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupCRC +* \{ +* Cyclic Redundancy Check(CRC)is an error detection system. The CRC code is a +* remainder after dividing an input data string by a pre-defined generator +* polynomial, assuming the input data string is a high order polynomial. +* Ordinarily, the CRC code is added to the end of a data string when +* transmitted. You divide the received data by the generator polynomial. +* If the received data is dividable, it is judged that the data is correctly +* received.
+* The CRC module supports both CCITT CRC16 and IEEE-802.3 CRC32. The generator +* polynomial is fixed to the numeric values for those two modes for each mode, +* and cannot be changed. You cannot generate a CRC value based on other +* generator polynomials.
+* - CCITT CRC16 generator polynomial: 0x1021
+* - IEEE-802.3 CRC32 generator polynomial: 0x04C11DB7
+* \section SectionCRC_ConfigurationConsideration Configuration Consideration +* To set up the CRC, provide configuration parameters in the stc_crc_config_t +* structure. For example, specify whether you are working in 16-bit or 32-bit +* mode, the bit order, and byte order. Then call Crc_Init(). The results of +* the CRC calculation will vary based on byte and bit order. The code that +* confirms the CRC checksum must use the same configuration as the code that +* created the checksum.
+* You can use PDL function calls Crc_PushX() to write data, 8-, 16-, or 32-bits +* at a time or use DMA. When done, call Crc_ReadResult() to get the result of +* the CRC calculation.
+* Be careful with the endian. +* \section SectionCRC_MoreInfo More Information +* For more information on the CRC peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem
+* FM4 Peripheral Manual Core Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +/** +* \addtogroup GroupCRC_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Crc mode + ** + ** To select between CRC16 and CRC32 + ******************************************************************************/ +typedef enum en_crc_mode +{ + Crc16 = 0, ///< CCITT CRC16 standard + Crc32 = 1 ///< IEEE-802.3 CRC32 Ethernet standard +} en_crc_mode_t; + +/** \}GroupCRC_Types */ + +/** +* \addtogroup GroupCRC_DataStructures +* \{ +*/ +/** + ***************************************************************************** + ** \brief Crc configuration + *****************************************************************************/ +typedef struct stc_crc_config +{ + en_crc_mode_t enMode; ///< See description of #en_crc_mode_t + boolean_t bUseDma; ///< TRUE: DMA usage, needs DMA driver + boolean_t bFinalXor; ///< TRUE: CRC result as XOR value + boolean_t bResultLsbFirst; ///< CRC result bit order: TRUE: LSB first, FALSE MSB first + boolean_t bResultLittleEndian; ///< CRC result byte order: TRUE: Litte endian, FLASE: big endian + boolean_t bDataLsbFirst; ///< CRC feed data bit order: TRUE: LSB first, FALSE MSB first + boolean_t bDataLittleEndian; ///< CRC feed data byte order: TRUE: Litte endian, FLASE: big endian + uint32_t u32CrcInitValue; ///< Initial value, upper 16 bit ignored using CRC16 +} stc_crc_config_t; + +/** \} GroupCRC_DataStructures */ +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupCRC_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/* Init/DeInit */ +extern en_result_t Crc_Init(const stc_crc_config_t* pstcConfig); +extern void Crc_DeInit(void); + +/* Calucuration */ +extern void Crc_Push8 (uint8_t u8DataToPush); +extern void Crc_Push16(uint16_t u16DataToPush); +extern void Crc_Push32(uint32_t u32DataToPush); + +/* Get result */ +extern uint32_t Crc_ReadResult(void); + +/** \} GroupCRC_Functions */ +/** \} GroupCRC */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_CRC_ACTIVE)) */ + +#endif /* __CRC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.c new file mode 100644 index 0000000000..e28414fb38 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.c @@ -0,0 +1,296 @@ +/****************************************************************************** +* \file csv.c +* +* \version 1.20 +* +* \brief Clock Supervisor driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/*---------------------------------------------------------------------------*/ +/* include files */ +/*---------------------------------------------------------------------------*/ +#include "csv/csv.h" + +#if (defined(PDL_PERIPHERAL_CSV_ACTIVE)) +/*---------------------------------------------------------------------------*/ +/* local defines */ +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* local datatypes */ +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* local data */ +/*---------------------------------------------------------------------------*/ +#if (PDL_INTERRUPT_ENABLE_CSV == PDL_ON) +static fn_fcs_int_callback *m_pfnIrqCb = NULL; +#endif + +/*---------------------------------------------------------------------------*/ +/* local functions prototypes */ +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* global data */ +/*---------------------------------------------------------------------------*/ +/*---------------------------------------------------------------------------*/ +/* global functions */ +/*---------------------------------------------------------------------------*/ + +#if (PDL_INTERRUPT_ENABLE_CSV == PDL_ON) +/** + ****************************************************************************** + ** \brief CSV interrupt handler + ******************************************************************************/ +void Csv_IrqHandler(void) +{ + bFM_CRG_INT_CLR_FCSC = 1; + m_pfnIrqCb(); +} + +/** + ****************************************************************************** + ** \brief Enables FCS interrupts + ******************************************************************************/ +en_result_t Csv_EnableFcsIrq(fn_fcs_int_callback* pfnIrqCb) +{ + if(NULL == pfnIrqCb) + { + return ErrorInvalidParameter; + } + + m_pfnIrqCb = pfnIrqCb; + bFM_CRG_INT_ENR_FCSE = 1u; + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(CSV_SWDT_LVD_IRQn); + NVIC_EnableIRQ(CSV_SWDT_LVD_IRQn); + NVIC_SetPriority(CSV_SWDT_LVD_IRQn, PDL_IRQ_LEVEL_CSV_SWDT_LVD); +#else + NVIC_ClearPendingIRQ(CSV_IRQn); + NVIC_EnableIRQ(CSV_IRQn); + NVIC_SetPriority(CSV_IRQn, PDL_IRQ_LEVEL_CSV); +#endif + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Disables FCS interrupts + ****************************************************************************** + */ +void Csv_DisableFcsIrq(void) +{ + bFM_CRG_INT_ENR_FCSE = 0u; +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(CSV_SWDT_LVD_IRQn); + NVIC_DisableIRQ(CSV_SWDT_LVD_IRQn); + NVIC_SetPriority(CSV_SWDT_LVD_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + NVIC_ClearPendingIRQ(CSV_IRQn); + NVIC_DisableIRQ(CSV_IRQn); + NVIC_SetPriority(CSV_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +} +#endif + +/*! + ****************************************************************************** + ** \brief The main CSV function is enabled + ****************************************************************************** + */ +void Csv_EnableMainCsv(void) +{ + bFM_CRG_CSV_CTL_MCSVE = 1u; +} + +/*! + ****************************************************************************** + ** \brief The main CSV function is disabled + ****************************************************************************** + */ +void Csv_DisableMainCsv(void) +{ + bFM_CRG_CSV_CTL_MCSVE = 0u; +} + +/*! + ****************************************************************************** + ** \brief The sub CSV function is enabled. + ****************************************************************************** + */ +void Csv_EnableSubCsv(void) +{ + bFM_CRG_CSV_CTL_SCSVE = 1u; +} + +/*! + ****************************************************************************** + ** \brief The sub CSV function is disabled + ****************************************************************************** + */ +void Csv_DisableSubCsv(void) +{ + bFM_CRG_CSV_CTL_SCSVE = 0u; +} + +/*! + ****************************************************************************** + ** \brief Get CSV status + ** + ** \param pstcCsvStatus Pointer to status information struture of CSV + ** + ** \retval Ok + ****************************************************************************** + */ +uint8_t Csv_GetCsvFailCause(stc_csv_status_t* pstcCsvStatus) +{ + uint8_t u8Status; + + u8Status = FM_CRG->CSV_STR; + + if(0x01u == (u8Status & 0x01u)) + { + pstcCsvStatus->bCsvMainClockStatus = TRUE; + } + else + { + pstcCsvStatus->bCsvMainClockStatus = FALSE; + } + + if(0x02u == (u8Status & 0x02u)) + { + pstcCsvStatus->bCsvSubClockStatus = TRUE; + } + else + { + pstcCsvStatus->bCsvSubClockStatus = FALSE; + } + + return Ok;; +} + +/** + ****************************************************************************** + ** \brief The FCS function is enabled. + ******************************************************************************/ +void Csv_EnableFcs(void) +{ + bFM_CRG_CSV_CTL_FCSDE = 1u; +} + +/** + ****************************************************************************** + ** \brief The FCS function is disabled + ******************************************************************************/ +void Csv_DisableFcs(void) +{ + bFM_CRG_CSV_CTL_FCSDE = 0u; +} + +/** + ****************************************************************************** + ** \brief The FCS reset is enabled. + ******************************************************************************/ +void Csv_EnableFcsReset(void) +{ + bFM_CRG_CSV_CTL_FCSRE = 1u; +} + + +/** + ****************************************************************************** + ** \brief The FCS reset is disabled. + ******************************************************************************/ +void Csv_DisableFcsReset(void) +{ + bFM_CRG_CSV_CTL_FCSRE = 0u; +} + +/** + ****************************************************************************** + ** \brief Clears the FCS interrupt cause. + ******************************************************************************/ +void Csv_ClrFcsIrqFlag(void) +{ + bFM_CRG_INT_CLR_FCSC = 1u; +} + +/** + ****************************************************************************** + ** \brief Get Anomalous frequency detection interrupt status + ** + ** \return interrupt status + ** \retval 0 No FCS interrupt has been asserted. + ** \retval 1 An FCS interrupt has been asserted. + ******************************************************************************/ +uint8_t Csv_GetFcsIrqFlag(void) +{ + return bFM_CRG_INT_STR_FCSI; +} + +/** + ****************************************************************************** + ** \brief FCS count cycle setting + ** + ** \param enDiv High-speed CR division + ** \arg FcsCrDiv256 1/256 frequency of high-speed CR oscillation + ** \arg FcsCrDiv512 1/512 frequency of high-speed CR oscillation + ** \arg FcsCrDiv1024 1/1024 frequency of high-speed CR oscillation + ** + ** \retval Ok + ******************************************************************************/ +en_result_t Csv_SetFcsCrDiv(en_fcs_cr_div_t enDiv) +{ + if ((FcsCrDiv256 != enDiv) && + (FcsCrDiv512 != enDiv) && + (FcsCrDiv1024 != enDiv)) + { + return ErrorInvalidParameter; + } + + FM_CRG->CSV_CTL &= 0x0fffu; + FM_CRG->CSV_CTL |= ((uint16_t)enDiv << 12u); + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Frequency lower detection window setting + ** + ** \param u16LowerVal Lower value + ** \param u16UpperVal limit value + ******************************************************************************/ +void Csv_SetFcsDetectRange(uint16_t u16LowerVal, uint16_t u16UpperVal) +{ + FM_CRG->FCSWL_CTL = u16LowerVal; + FM_CRG->FCSWH_CTL = u16UpperVal; +} + +/** + ****************************************************************************** + ** \brief Get the counter value of frequency detection using the main clock. + ** + ** \return Frequency detection counter value + ******************************************************************************/ +uint16_t Csv_GetFcsDetectCount(void) +{ + return FM_CRG->FCSWD_CTL; +} + +#endif + +/*****************************************************************************/ +/* END OF FILE */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.h new file mode 100644 index 0000000000..b069fd6601 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/csv/csv.h @@ -0,0 +1,183 @@ +/****************************************************************************** +* \file csv.h +* +* \version 1.20 +* +* \brief Headerfile for Clock Supervisor functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef _CSV_H_ +#define _CSV_H_ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_CSV_ACTIVE)) +/** +* \defgroup GroupCSV Clock Supervisor(CSV) +* \{ +* \defgroup GroupCSV_Functions Functions +* \defgroup GroupCSV_DataStructures Data Structures +* \defgroup GroupCSV_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupCSV +* \{ +* The Clock Supervisor peripheral monitors particular clocks for failure or +* anomalous frequency.
+* Clock Failure Detection
+* The clock failure detection function monitors the main and sub clocks +* independently. If a rising edge of the monitored clock is not detected within +* the specified period, this function determines that the oscillator has +* failed, and outputs a system reset request.
+* - it stops monitoring when the main and sub oscillators stop oscillating
+* - it stops monitoring while waiting for oscillation stabilization wait +* time
+* - is automatically enabled when the wait time ends
+* +* Anomalous Frequency Detection by Clock (FCS)
+* The anomalous frequency detection function monitors the main clock. Within +* the specified period between a rising edge and the next rising edge of the +* divided high-speed CR clock, this function counts up the internal counter +* using the main clock. If the count value is outside of a set range, the +* function determines that the main clock frequency is anomalous, +* and outputs an interrupt request or a system reset request to the CPU.
+* - it monitors frequency of the main clock only
+* - it stops monitoring when the main oscillator stops oscillating
+* - it stops monitoring while waiting for oscillation stabilization wait +* time
+* - is not automatically enabled
+* +* \section SectionCSV_ConfigurationConsideration Configuration Consideration +* There is no configuration required. Use PDL function calls to enable, +* disable, and get status for the clock failure detection. +* To get CSV status, declare a structure of type stc_csv_status_t, and call +* Csv_GetCsvFailCause().
+* Similarly, use function calls to manage the FCS features. Note that FCS is +* not automatically enabled. Call Csv_EnableFcs() to +* start this feature. You set the FCS range with Csv_SetFcsDetectRange().
+* You can enable or disable the FCS interrupt or reset request. If you enable +* the FCS interrupt, you provide a function pointer to a callback routine to +* handle the interrupt.
+* +* \section SectionCSV_MoreInfo More Information +* For more information on the CSV peripheral, refer to:
+* FM0+ Peripheral Manual - Core Subsystem TRM.pdf
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupCSV_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each BT instance + ******************************************************************************/ +typedef enum en_fcs_cr_div +{ + FcsCrDiv256 = 5u, ///< 1/256 frequency of high-speed CR oscillation + FcsCrDiv512 = 6u, ///< 1/512 frequency of high-speed CR oscillation + FcsCrDiv1024 = 7u, ///< 1/1024 frequency of high-speed CR oscillation + +}en_fcs_cr_div_t; + +/** \}GroupCSV_Types */ + +/** +* \addtogroup GroupCSV_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Structure of CSV status + ******************************************************************************/ +typedef struct stc_csv_status +{ + boolean_t bCsvMainClockStatus; + boolean_t bCsvSubClockStatus; + +}stc_csv_status_t; + +/** \} GroupCSV_DataStructures */ + +/** +* \addtogroup GroupCSV_Functions +* \{ +*/ + +/** + ****************************************************************************** + ** \brief FCS interrupt callback function type + ******************************************************************************/ +typedef void fn_fcs_int_callback(void); + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif +/* CSV */ +void Csv_EnableMainCsv(void); +void Csv_DisableMainCsv(void); +void Csv_EnableSubCsv(void); +void Csv_DisableSubCsv(void); +uint8_t Csv_GetCsvFailCause(stc_csv_status_t* pstcCsvStatus); +/* FCS */ +void Csv_EnableFcs(void); +void Csv_DisableFcs(void); +void Csv_EnableFcsReset(void); +void Csv_DisableFcsReset(void); +#if (PDL_INTERRUPT_ENABLE_CSV == PDL_ON) +en_result_t Csv_EnableFcsIrq(fn_fcs_int_callback* pfnIrqCb); +void Csv_DisableFcsIrq(void); +#endif +void Csv_ClrFcsIrqFlag(void); +uint8_t Csv_GetFcsIrqFlag(void); +en_result_t Csv_SetFcsCrDiv(en_fcs_cr_div_t enDiv) ; +void Csv_SetFcsDetectRange(uint16_t u16LowerVal, uint16_t u16UpperVal); +uint16_t Csv_GetFcsDetectCount(void); +/* IRQ */ +void Csv_IrqHandler(void); + +/** \} GroupCSV_Functions */ +/** \} GroupCSV */ + +#ifdef __cplusplus +} +#endif + + +#endif + +#endif /* _CLOCK_FM3_H_ */ +/*****************************************************************************/ +/* END OF FILE */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.c new file mode 100644 index 0000000000..ca4a10b38e --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.c @@ -0,0 +1,218 @@ +/****************************************************************************** +* \file dac.c +* +* \version 1.20 +* +* \brief Digital Analog Converter driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "dac/dac.h" + +#if (defined(PDL_PERIPHERAL_DAC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief DAC Initialization + ** + ** \param [in] pstcDac Pointer to DAC instance + ** \param [in] pstcConfig Pointer to DAC configuration strucutre + ** + ** \retval Ok DAC Instance sucessfully initialized + ** \retval ErrorInvalidParameter pstcDac == NULL or pstcConfig == NULL + ******************************************************************************/ +en_result_t Dac_Init( stc_dacn_t* pstcDac, + const stc_dac_config_t* pstcConfig + ) +{ + // Check for NULL pointers + if ((NULL == pstcDac) || + (NULL == pstcConfig) || + (DacTypeUndefined == pstcConfig->dac_type) || + (DacMaxChannel <= pstcConfig->dac_channel) + ) + { + return ErrorInvalidParameter; + } + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + pstcDac->DACR_f.DAC10 = (DacType12Bit == pstcConfig->dac_type) ? 0u : 1u ; + pstcDac->DACR_f.DAC10 = (DacType10BitLeftAligned == pstcConfig->dac_type) ? 0u : 1u ; +#endif + + return Ok; +} // Dac_Init + + +/** + ****************************************************************************** + ** \brief DAC De-Initialization + ** + ** \param [in] pstcDac Pointer to DAC instance + ** + ** \retval Ok DAC Instance sucessfully de-initialized + ** \retval ErrorInvalidParameter pstcDac == NULL or pstcConfig == NULL + ******************************************************************************/ +en_result_t Dac_DeInit( stc_dacn_t* pstcDac ) +{ + en_result_t enResult; + + enResult = Dac_DeInitChannel( pstcDac, DacChannel0 ); + enResult |= Dac_DeInitChannel( pstcDac, DacChannel1 ); + + return enResult; +} // Dac_DeInit + + +/** + ****************************************************************************** + ** \brief DAC De-Initialization + ** + ** \param [in] pstcDac Pointer to DAC instance + ** \param [in] enChannel Pointer to DAC configuration strucutre + ** + ** \retval Ok DAC Channel sucessfully de-initialized + ** \retval ErrorInvalidParameter pstcDac == NULL or pstcConfig == NULL + ******************************************************************************/ +en_result_t Dac_DeInitChannel( stc_dacn_t* pstcDac, en_dac_channel_t enChannel ) +{ + // Check for NULL pointers + if ( (NULL == pstcDac) || + (DacMaxChannel <= enChannel) + ) + { + return ErrorInvalidParameter; + } + + if( DacChannel0 == enChannel) + { + pstcDac->DACR = 0u; + pstcDac->DADR = 0u; + } + + return Ok; +} // Dac_DeInitChannel + + +/** + ****************************************************************************** + ** \brief Set DAC Channel 0 12-bit value + ** + ** \param [in] pstcDac Pointer to DAC instance + ** \param [in] u16DacValue DAC Channel value to be output + ** + ** \retval Ok Value written. + ** \retval ErrorInvalidParameter pstcDac == NULL or pstcConfig == NULL + ******************************************************************************/ +en_result_t Dac_SetValue( stc_dacn_t* pstcDac, + en_dac_channel_t enChannel, + uint16_t u16DacValue + ) +{ + if ( (NULL == pstcDac) || + (DacMaxChannel <= enChannel) + ) + { + return ErrorInvalidParameter; + } + + pstcDac->DADR_f.DA = u16DacValue; + + return Ok; +} // Dac_SetValue + + +/** + ****************************************************************************** + ** \brief Enable DAC Channel + ** + ** \param [in] pstcDac Pointer to DAC instance + ** \param [in] u8Channel DAC Channel number + ** + ** \retval Ok DAC Channel enabled + ** \retval ErrorInvalidParameter pstcDac == NULL or pstcConfig == NULL + ******************************************************************************/ + +en_result_t Dac_Enable( stc_dacn_t* pstcDac, en_dac_channel_t enChannel) +{ + if ( (NULL == pstcDac) || + (DacMaxChannel <= enChannel) + ) + { + return ErrorInvalidParameter; + } + + pstcDac->DACR_f.DAE = 1u; + + return Ok; +} // Dac_Enable + + +/** + ****************************************************************************** + ** \brief Disable DAC Channel + ** + ** \param [in] pstcDac Pointer to DAC instance + ** \param [in] u8Channel DAC Channel number + ** + ** \retval Ok DAC Channel disabled + ** \retval ErrorInvalidParameter pstcDac == NULL or pstcConfig == NULL + ******************************************************************************/ +en_result_t Dac_Disable( stc_dacn_t* pstcDac, en_dac_channel_t enChannel ) +{ + if ( (NULL == pstcDac) || + (DacMaxChannel <= enChannel) + ) + { + return ErrorInvalidParameter; + } + + pstcDac->DACR_f.DAE = 0u; + + return Ok; +} // Dac_Disable + + +#endif // #if (defined(PDL_PERIPHERAL_DAC_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.h new file mode 100644 index 0000000000..2148466e2d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dac/dac.h @@ -0,0 +1,197 @@ +/****************************************************************************** +* \file dac.h +* +* \version 1.20 +* +* \brief Headerfile for Digital Analog Converter functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __DAC_H__ +#define __DAC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if !defined(FM_DAC_AVAILABLE) && defined(PDL_PERIPHERAL_DAC_ACTIVE) + #error "Do not enable DAC, as it is not available on this device" +#endif + +#if (defined(PDL_PERIPHERAL_DAC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupDAC Digital Analog Converter (DAC) +* \{ +* \defgroup GroupDAC_Macros Macros +* \defgroup GroupDAC_Functions Functions +* \defgroup GroupDAC_DataStructures Data Structures +* \defgroup GroupDAC_Types Enumerated Types +* \} +*/ +/** +* \addtogroup GroupDAC +* \{ +* The 12-bit Digital Analog Converter (DAC) converts 10- or 12-bit digital values to analog output values.
+* Features of 12-bit D/A Converter:
+* - 12-bits or 10-bits mode
+* - R-2R method
+* - stops operating in following low power consumption modes:
+* -- RTC mode
+* -- Stop mode
+* -- Deep standby RTC mode
+* -- Deep standby stop mode
+* \section SectionDAC_ConfigurationConsideration Configuration Consideration +* To set up the DAC, provide configuration parameters in the stc_dac_config_t structure. For example, +* specify the operating mode: 12-bit, 10-bit left aligned, or 10-bit right-aligned. Then call Dac_Init().
+* You must also call Dac_Enable() to start the peripheral before beginning conversions. There are two possible +* DAC channels. You can enable or disable either of them independently. Note that in low power modes, +* the DAC is stopped, regardless of whether you have enabled it.
+* Use Dac_SetValue() to set the digital value to be converted into analog signal.
+* +* \section SectionDAC_MoreInfo More Information +* For more information on the DAC peripheral, refer to:
+* FM0+ Peripheral Manual - Analog Subsystem TRM.pdf
+* FM4 Peripheral Manual - Analog Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupDAC_Macros +* \{ +*/ +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + #define stc_dacn_t FM_DAC_TypeDef +#ifdef FM_DAC0_BASE + #define DAC0 (*(( stc_dacn_t *) FM_DAC0_BASE)) +#endif +#ifdef FM_DAC1_BASE + #define DAC1 (*(( stc_dacn_t *) FM_DAC1_BASE)) +#endif + + + #define Dac_SetValue0( pstcDac, u16DacValue ) Dac_SetValue(pstcDac, DacChannel0, u16DacValue) + #define Dac_SetValue1( pstcDac, u16DacValue ) Dac_SetValue(pstcDac, DacChannel1, u16DacValue) + #define Dac_Enable0( pstcDac ) Dac_Enable(pstcDac, DacChannel0) + #define Dac_Enable1( pstcDac ) Dac_Enable(pstcDac, DacChannel1) + #define Dac_Disable0( pstcDac ) Dac_Disable(pstcDac, DacChannel0) + #define Dac_Disable1( pstcDac ) Dac_Disable(pstcDac, DacChannel1) + +/** \} GroupDAC_Macros */ + +/** +* \addtogroup GroupDAC_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +typedef enum en_dac_type +{ + DacTypeUndefined = 0u, + DacType12Bit = 1u, + DacType10BitLeftAligned = 2u, + DacType10BitRightAligned = 3u +}en_dac_type_t; + +typedef enum en_dac_channel +{ + DacChannel0 = 0u, + DacChannel1 = 1u, + DacMaxChannel = 2u +}en_dac_channel_t; + +/** \}GroupDAC_Types */ + +/** +* \addtogroup GroupDAC_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief DAC configuration. + ******************************************************************************/ +typedef struct stc_dac_config +{ + en_dac_channel_t dac_channel; + en_dac_type_t dac_type; +} stc_dac_config_t; +/** \} GroupDAC_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupDAC_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +en_result_t Dac_Init( stc_dacn_t* pstcDac, + const stc_dac_config_t* pstcConfig + ); + +en_result_t Dac_DeInit( stc_dacn_t* pstcDac ); + +en_result_t Dac_DeInitChannel( stc_dacn_t* pstcDac, + en_dac_channel_t enChannel + ); + +en_result_t Dac_SetValue( stc_dacn_t* pstcDac, + en_dac_channel_t enChannel, + uint16_t u16DacValue + ); + +en_result_t Dac_Enable( stc_dacn_t* pstcDac, + en_dac_channel_t enChannel + ); + +en_result_t Dac_Disable( stc_dacn_t* pstcDac, + en_dac_channel_t enChannel + ); + + +/** \} GroupDAC_Functions */ +/** \} GroupDAC */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_DAC_ACTIVE)) + +#endif /* __DAC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/description.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/description.h new file mode 100644 index 0000000000..af29143524 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/description.h @@ -0,0 +1,212 @@ +/* + *** THIS IS A FILE FOR DOXYGEN AND NOT A C HEADER FILE *** +*/ + +/** + ******************************************************************************* + ** \mainpage + ** \{ + ******************************************************************************* + ** \image html cypress_logo.png + ** + **

Copyright

+ ** + ** Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. + ** You may use this file only in accordance with the license, terms, conditions, + ** disclaimers, and limitations in the end user license agreement accompanying + ** the software package with which this file was provided. + ** CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY + ** OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, + ** INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + ** MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR + ** PURPOSE. + ** + **

Overview

+ ** + ** Cypress provides the Peripheral Driver Library (PDL) to simplify software + ** development for the FM0+, and FM4 MCU families. The PDL reduces the need to + ** understand register usage and bit structures, thus easing software development + ** for the extensive set of peripherals in the FM families. You configure the + ** library for the particular device, and then use API calls to initialize and + ** use a peripheral. Using the PDL makes it easier to port code from one family + ** to the other, because the same code supports all FM families.
+ ** This documentation provides technical information on each supported peripheral + ** driver, including:
+ ** * Configuration considerations + ** * Macros + ** * Functions + ** * Global variables + ** * Data structures + ** * Enumerated types + ** + ** For a general introduction to the PDL, read + ** Peripheral Driver Library Quick Start Guide. + ** + **

PDL Example Code

+ ** + ** The PDL installation includes code examples with IDE project files configured + ** for particular FM portfolio starter kits. You find the code examples in the + ** /examples folder.
+ ** Each example demonstrates how to configure, initialize, and use a peripheral. + ** Some peripherals have multiple examples.
+ ** Each code example project uses two files that implement the example: main.c + ** and pdl_user.h. The main.c file has code that implements the example. The + ** pdl_user.h file enables or disables the PDL capabilities required for the + ** example. Each example also has a readme file that explains the example. + ** + ** To use an example, open the project file for your preferred IDE. See the + ** PDL Quick Start Guide section “Build and Run a PDL Project” for details. + ** + ** + ** + **
Example Code Support
Code example Associated Peripheral Development Kit + **
SK_S6E1B8 SK_S6E2GM + **
adc_scan_dma ADC - + + **
adc_scan_multich_polling_sw ADC + + + **
adc_scan_onech_polling_sw ADC + + + **
bt_ppg BT + + + **
bt_pwc BT + + + **
bt_pwm BT + + + **
bt_rt BT + + + **
can_simple CAN - + + **
clk_gating CLK + + + **
clk_init CLK + + + **
cr_trimming CRC + + + **
crc_16_32 CRC + + + **
csv_reset CSV + + + **
fcs_int CSV + + + **
fcs_reset CSV + + + **
dma_software DMA - + + **
dstc_hw_transfer DSTC + + + **
dstc_sw_transfer DSTC + + + **
dt_unuse_int DT + + + **
dt_use_int DT + + + **
exint_simple EXINT + + + **
toggling_led GPIO + + + **
lpm_deep_standby_rtc_mode LPM + + + **
lpm_rtc_mode LPM + + + **
lpm_sleep_mode LPM + + + **
lvd_interrupt LVD + + + **
lvd_polling LVD + + + **
csio_interrupt MFS + + + **
csio_polling MFS + + + **
csio_using_cs MFS + + + **
i2c_master_polling MFS + + + **
i2c_slave_polling MFS + + + **
uart_dma MFS - + + **
uart_fifo_interrupt MFS + + + **
uart_interrupt MFS + + + **
uart_polling MFS + + + **
uart_printf MFS + + + **
frt_interrupt MFT + + + **
icu_interrupt MFT + + + **
wfg_rt_ppg_mode MFT + + + **
rtc_calibration RTC + + + **
rtc_count RTC + + + **
rtc_timer RTC + + + **
uid_read UID + + + **
vbat_gpio VBAT + - + **
hwwdg WDG + + + **
swwdg_normal WDG + + + **
swwdg_window_mode WDG + + + **
+ ** + **

Utility

+ ** The PDL provides various utility files such as redirecting standard I/O to + ** serial terminal and interfacing to different on-board devices. + ** + ** + **
NameDetails + **
EEPROM I2C interface EEPROM + **
HYPER_FLASH Hyper Bus Flash + **
I2S_CODEC I2S codec + **
NAND_FLASH Access Nand Flash via External Bus Interface + **
PRINTF Printf via UART + **
QSPI_FLASH Access Quad-SPI Flash via High speed Quad-SPI + **
SD_CARD Access SD card via SDIO interface + **
SDRAM Access SDRAM via External Bus Interface + **
SEG_LCD Control Segment LCD via LCD controller + **
+ ** + ** + **

Mapping Peripheral Signals to Physical I/O Pins

+ ** + ** + ** Most peripherals can be connected to two or more device I/O ports. You + ** control which port to use (called “pin relocation”) by software. + ** + ** After device reset each I/O is configured to its default function as shown + ** in the following table. + ** + ** + ** + **
Initially Selected Functions for Each I/O Port after Reset Is Released
Pin name Initial pin function + **
SWCLK, SWDIO Serial Wire Debug (SWD) pin is selected. Pull-up is enabled. + **
ANxx Can be used as an analog input pin. Digital input is cut off and ‘0’ is input. + **
X0,X1,X0A, X1A Can be used as an oscillation pin. Digital input is cut off and ‘0’ is input. + **
All GPIO pins other than the above pins Digital input. Output is Hi-Z. + **
+ ** + ** The supported pin functions for each I/O vary among products and packages. + ** Consult the “Pin Assignment” and “List of Pin Functions” sections of the + ** device-specific datasheet to determine which pin can be assigned to which + ** peripheral signal. + ** + ** For example, the following figure shows an excerpt from the LQFP-80 package + ** view in the S6E1B8 Series device datasheet. For each I/O there is a list of + ** pin names provided. The number after the underscore ("_") in pin names such + ** as XXX_0 and XXX_1 indicates the relocated port number. These signals can be + ** connected to several device pins. + ** + ** \image html pin_relocation.png + ** + ** To determine the pin functions for a specific pin search for the pin name in + ** the “List of Pin Functions” table of the device datasheet. For example, pin + ** 60 can be used as: + ** * P21 – General-purpose I/O port 2[pin 1] + ** * AN18 – ADC input channel 18 + ** * SIN0_0 – MFS channel 0 input pin + ** * INT06_1 – external interrupt request 6 input pin + ** * WKUP2 – deep standby mode return signal input pin + ** * SEG11 – LCD controller segment 11 output pin + ** + ** To assign a pin function use the appropriate macro. The file gpio_.h + ** defines macro names, in the form: SetPinFunc_. + ** + ** So, to assign pin 60 as SIN0_0, the macro name is SetPinFunc_SIN0_0, and the + ** code would be SetPinFunc_SIN0_0(); + ** + ** The gpio_.h file is device-specific. + ** + ** For FM0+ portfolio the files are located: /devices/fm0p//common/ + ** + ** For FM4 portfolio the location is: /devices/fm4//common/ + **

Revision History

+ ** + ** The following table shows the overall high-level updates. Refer to the PDL Release Notes for more details. + ** + **
VersionDescription + **
2.1.0 + ** * Code Examples - PDL now includes ready to use project file for + ** each IDE as a part of every code example, no need to reconfigure.
+ ** * Low-level programming - Preconfigured project file for each IDE provided + ** for every device package.
+ ** * Added support for iSYSTEM winIDEA v9.12, Atollic TrueSTUDIO v5.5, and Makefile + ** support with GCC from ARM Embedded.
+ ** * Peripherals - various enhancements and corrections.
+ ** * Device support – Now CMSIS v4.5 compliant dedicated device header file and startup code + ** for every device package. + **
+ ** + **

More Information

+ ** + ** For more information on the pin relocation, refer to:
+ ** FM0+ PERIPHERAL MANUAL - Core Subsystem
+ ** FM4 PERIPHERAL MANUAL - Core Subsystem
+ ** The Peripheral Manual is divided into several subsystems. Click the link to see:
+ ** all + ** FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+ ** all + ** FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+ ** \} + ******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.c new file mode 100644 index 0000000000..a6cb686bc6 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.c @@ -0,0 +1,1144 @@ +/****************************************************************************** +* \file dma.c +* +* \version 1.20 +* +* \brief Direct Memory Access Controller driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "dma/dma.h" + +#if (defined(PDL_PERIPHERAL_DMA_ACTIVE)) + +const uint8_t cau8DmaReferenceLut[PDL_DMA_INSTANCE_COUNT + 1] = +{ +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) + 0, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) + 1, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) + 2, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) + 3, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) + 4, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) + 5, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) + 6, +#endif +#if (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) + 7, +#endif + 255 // End of table +}; + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +// DMACAn => FM3_DMAC_BASE + size of register set + offset of DMACA0 +// DMACAn => 0x40060000 + 0x10 * n + 0x10 +#define GET_DMA_ADDRESS(x) (FM_DMAC_BASE + (0x10ul * (x)) + 0x10ul) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) +stc_dma_intern_data_t stcDmaInternData; +#endif + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +typedef union +{ + uint32_t u32DMACA; + stc_dmac_dmaca0_field_t stcDMACA; + +}un_dmac_dmaca_t; + +typedef union +{ + stc_dmac_dmacb0_field_t stcDMACB; + uint32_t u32DMACB; + +}un_dmac_dmacb_t; + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +static en_result_t DmaInitNvic(uint8_t u8DmaChannel); +static en_result_t DmaDeInitNvic(uint8_t u8DmaChannel); +static uint8_t DmaGetInternDataIdx(uint8_t u8Channel); +#endif + +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) +/** + ****************************************************************************** + ** \brief DMA interrupt handler + ** + ** \param [in] u8DmaChannel Channel number + ** + ** \note depending on the DMA stop status the DmaCallback function is called + ** on successful transfer or DmaErrorCallback function on errornous + ** transfer. The ErrorCallback has the error code as an (uint8_t) + ** argument which reflects the 3 bits of the stop status. + ******************************************************************************/ +void DmaIrqHandler(uint8_t u8DmaChannel) +{ + uint32_t u32DmaRegisterBaseAddress; + uint32_t u32RegisterReadOut; + uint8_t u8StopStatus; + uint8_t u8InstanceIdx; + + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // Readout DMACB and update + u32RegisterReadOut = *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)); + + u8StopStatus = (uint8_t)((u32RegisterReadOut & 0x00070000ul)>> 16u); + + u8InstanceIdx = DmaGetInternDataIdx(u8DmaChannel); // Get DMA instance index + if(255u == u8InstanceIdx) // Instance not found. + { + return; + } + + // Clear interrupt cause + u32RegisterReadOut &= 0xFFF8FFFFu; + *(uint32_t*)(uint32_t)((u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) + = u32RegisterReadOut; + + if (0x5u == u8StopStatus) // Successful DMA transfer + { + stcDmaInternData.apfnDmaIrqCompletionCb[u8InstanceIdx](); + } + else // Errornous DMA transfer + { + stcDmaInternData.apfnDmaErrorIrqCb[u8InstanceIdx](u8StopStatus); + } +} + +/** + ****************************************************************************** + ** \brief Init DMA interrupt IRQ + ** + ** \param [in] u8DmaChannel Channel number + ** + ** \retval Ok init successful + ** + ******************************************************************************/ +static en_result_t DmaInitNvic(uint8_t u8DmaChannel) +{ + switch(u8DmaChannel) + { + case 0u: + NVIC_ClearPendingIRQ(DMAC0_IRQn); + NVIC_EnableIRQ(DMAC0_IRQn); + NVIC_SetPriority(DMAC0_IRQn, PDL_IRQ_LEVEL_DMA0); + break; + case 1u: + NVIC_ClearPendingIRQ(DMAC1_IRQn); + NVIC_EnableIRQ(DMAC1_IRQn); + NVIC_SetPriority(DMAC1_IRQn, PDL_IRQ_LEVEL_DMA1); + break; +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case 2u: + NVIC_ClearPendingIRQ(DMAC2_IRQn); + NVIC_EnableIRQ(DMAC2_IRQn); + NVIC_SetPriority(DMAC2_IRQn, PDL_IRQ_LEVEL_DMA2); + break; + case 3u: + NVIC_ClearPendingIRQ(DMAC3_IRQn); + NVIC_EnableIRQ(DMAC3_IRQn); + NVIC_SetPriority(DMAC3_IRQn, PDL_IRQ_LEVEL_DMA3); + break; + case 4u: + NVIC_ClearPendingIRQ(DMAC4_IRQn); + NVIC_EnableIRQ(DMAC4_IRQn); + NVIC_SetPriority(DMAC4_IRQn, PDL_IRQ_LEVEL_DMA4); + break; + case 5u: + NVIC_ClearPendingIRQ(DMAC5_IRQn); + NVIC_EnableIRQ(DMAC5_IRQn); + NVIC_SetPriority(DMAC5_IRQn, PDL_IRQ_LEVEL_DMA5); + break; + case 6u: + NVIC_ClearPendingIRQ(DMAC6_IRQn); + NVIC_EnableIRQ(DMAC6_IRQn); + NVIC_SetPriority(DMAC6_IRQn, PDL_IRQ_LEVEL_DMA6); + break; + case 7u: + NVIC_ClearPendingIRQ(DMAC7_IRQn); + NVIC_EnableIRQ(DMAC7_IRQn); + NVIC_SetPriority(DMAC7_IRQn, PDL_IRQ_LEVEL_DMA7); + break; +#endif + default: + break; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Init DMA interrupt + ** + ** \param [in] u8DmaChannel Channel number + ** + ** \retval Ok de-init successful + ** + ******************************************************************************/ +static en_result_t DmaDeInitNvic(uint8_t u8DmaChannel) +{ + switch(u8DmaChannel) + { + case 0u: + NVIC_ClearPendingIRQ(DMAC0_IRQn); + NVIC_EnableIRQ(DMAC0_IRQn); + NVIC_SetPriority(DMAC0_IRQn, PDL_IRQ_LEVEL_DMA0); + break; + case 1u: + NVIC_ClearPendingIRQ(DMAC1_IRQn); + NVIC_EnableIRQ(DMAC1_IRQn); + NVIC_SetPriority(DMAC1_IRQn, PDL_IRQ_LEVEL_DMA1); + break; +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case 2u: + NVIC_ClearPendingIRQ(DMAC2_IRQn); + NVIC_EnableIRQ(DMAC2_IRQn); + NVIC_SetPriority(DMAC2_IRQn, PDL_IRQ_LEVEL_DMA2); + break; + case 3u: + NVIC_ClearPendingIRQ(DMAC3_IRQn); + NVIC_EnableIRQ(DMAC3_IRQn); + NVIC_SetPriority(DMAC3_IRQn, PDL_IRQ_LEVEL_DMA3); + break; + case 4u: + NVIC_ClearPendingIRQ(DMAC4_IRQn); + NVIC_EnableIRQ(DMAC4_IRQn); + NVIC_SetPriority(DMAC4_IRQn, PDL_IRQ_LEVEL_DMA4); + break; + case 5u: + NVIC_ClearPendingIRQ(DMAC5_IRQn); + NVIC_EnableIRQ(DMAC5_IRQn); + NVIC_SetPriority(DMAC5_IRQn, PDL_IRQ_LEVEL_DMA5); + break; + case 6u: + NVIC_ClearPendingIRQ(DMAC6_IRQn); + NVIC_EnableIRQ(DMAC6_IRQn); + NVIC_SetPriority(DMAC6_IRQn, PDL_IRQ_LEVEL_DMA6); + break; + case 7u: + NVIC_ClearPendingIRQ(DMAC7_IRQn); + NVIC_EnableIRQ(DMAC7_IRQn); + NVIC_SetPriority(DMAC7_IRQn, PDL_IRQ_LEVEL_DMA7); + break; +#endif + default: + break; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Return the internal reference index of an DMA channel + ** + ** \param u8Channel DMA channel number + ** + ** \return uint8_t Reference index (255 if not found or u8Channel > PDL_DMA_CHANNELS) + ** + ******************************************************************************/ +static uint8_t DmaGetInternDataIdx(uint8_t u8Channel) +{ + uint8_t u8Index; + + if ((u8Channel + 1u) > PDL_DMA_CHANNELS) + { + return 255u; + } + + for (u8Index = 0u; u8Index < PDL_DMA_INSTANCE_COUNT; u8Index++) + { + if (u8Channel == cau8DmaReferenceLut[u8Index]) + { + return u8Index; + } + } + + return 255; // Should never happen ... +} + +/** + ****************************************************************************** + ** \brief Enable interrupt of a DMA channel + ** + ** Enable interrupt and set interrupt callback function of a DMA channel + ** + ** \param [in] u8DmaChannel DMA channel index + ** \param [in] pstcIrqSel DMA interrupt selection structure + ** + ** \retval Ok Interrupt enabled normally + ** \retval ErrorInvalidParameter u8DmaChannel > DMA_MAX_CH_INDEX + ** Other invalid configuration + ** + ******************************************************************************/ +en_result_t Dma_EnableIrq(uint8_t u8DmaChannel, + stc_dma_irq_sel_t* pstcIrqSel) +{ + uint32_t u32DmaRegisterBaseAddress; + un_dmac_dmacb_t unDmacDmacb; + + if((u8DmaChannel + 1u) > PDL_DMA_CHANNELS) + { + return ErrorInvalidParameter; + } + + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // Readout original DMACB + unDmacDmacb.u32DMACB = *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) ; + + // Update EI and CI bit + if(pstcIrqSel->bCompleteIrq == TRUE) + { + unDmacDmacb.stcDMACB.CI = 1u; + } + + if(pstcIrqSel->bErrorIrq == TRUE) + { + unDmacDmacb.stcDMACB.EI = 1u; + } + + // Write back to DMACB + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) = unDmacDmacb.u32DMACB; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable interrupt of a DMA channel + ** + ** \param [in] u8DmaChannel DMA channel index + ** \param [in] pstcIntSel DMA interrupt selection structure + ** + ** \retval Ok Interrupt disabled normally + ** \retval ErrorInvalidParameter u8DmaChannel > DMA_MAX_CH_INDEX + ** Other invalid configuration + ** + ******************************************************************************/ +en_result_t Dma_DisableIrq(uint8_t u8DmaChannel, + stc_dma_irq_sel_t* pstcIntSel ) +{ + uint32_t u32DmaRegisterBaseAddress; + un_dmac_dmacb_t unDmacDmacb; + + if((u8DmaChannel + 1u) > PDL_DMA_CHANNELS) + { + return ErrorInvalidParameter; + } + + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // Readout original DMACB + unDmacDmacb.u32DMACB = *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) ; + + // Update EI and CI bit + if(pstcIntSel->bCompleteIrq == TRUE) + { + unDmacDmacb.stcDMACB.CI = 0u; + } + + if(pstcIntSel->bErrorIrq == TRUE) + { + unDmacDmacb.stcDMACB.EI = 0u; + } + + // Write back to DMACB + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) = unDmacDmacb.u32DMACB; + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initializes a DMA channel + ** + ** Sets up an DMA channel without starting immediate DMA transfer. + ** Set_Dma_Channel() is used for starting DMA transfer. + ** + ** \param [in] u8DmaChannel DMA channel number + ** \param [in] pstcConfig DMA module configuration + ** + ** \retval Ok init successful + ** \retval ErrorInvalidParameter pstcAdc == NULL or other invalid configuration + ** \retval OperationInProgress DMA channel already in use + ** + ******************************************************************************/ +en_result_t Dma_InitChannel(uint8_t u8DmaChannel, const stc_dma_config_t* pstcConfig) +{ + un_dmac_dmaca_t unDmacDmaca; + un_dmac_dmacb_t unDmacDmacb; + uint32_t u32DmaRegisterBaseAddress; + uint32_t u32DrqselBit; + +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) + uint8_t u8InstanceIdx; + u8InstanceIdx = DmaGetInternDataIdx(u8DmaChannel); // Get DMA instance index + + if(0xFFu == u8InstanceIdx) // instance not fould + { + return ErrorInvalidParameter; + } +#endif + + // Check for NULL pointer + if (NULL == pstcConfig) + { + return ErrorInvalidParameter ; + } + + unDmacDmaca.u32DMACA = 0u; + unDmacDmacb.u32DMACB = 0u; + + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // Setup DMACA ... + // + // Block Count + unDmacDmaca.stcDMACA.BC = 0x0Fu & (uint32_t)(pstcConfig->u8BlockCount - 1u); + + // Transfer Count + unDmacDmaca.stcDMACA.TC = 0xFFFFu & (uint32_t)(pstcConfig->u16TransferCount - 1u); + + // Interrupt Request Channel + if (Software == pstcConfig->enDmaIdrq) + { + unDmacDmaca.stcDMACA.IS = 0u; + } + else + { + unDmacDmaca.stcDMACA.IS = 0x20u | (0x1Fu & (uint32_t)(pstcConfig->enDmaIdrq)); + } + + // ... and update hardware + *(uint32_t*)(uint32_t)((u32DmaRegisterBaseAddress + DMA_DMACA_OFFSET)) = unDmacDmaca.u32DMACA ; + + // Setup DMACB ... + // + // First Transfer mode + switch (pstcConfig->enTransferMode) + { + case DmaBlockTransfer: + unDmacDmacb.stcDMACB.MS = 0u; + break; + case DmaBurstTransfer: + unDmacDmacb.stcDMACB.MS = 1u; + break; + case DmaDemandTransfer: + unDmacDmacb.stcDMACB.MS = 2u; + break; + default : + return ErrorInvalidParameter; + } + + // Transfer width + switch (pstcConfig->enTransferWidth) + { + case Dma8Bit: + unDmacDmacb.stcDMACB.TW = 0u; + break; + case Dma16Bit: + unDmacDmacb.stcDMACB.TW = 1u; + break; + case Dma32Bit: + unDmacDmacb.stcDMACB.TW = 2u; + break; + default : + return ErrorInvalidParameter; + } + + // Fixed source + unDmacDmacb.stcDMACB.FS = (uint8_t)((pstcConfig->bFixedSource == TRUE) ? 1u : 0u); + + // Fixed destination + unDmacDmacb.stcDMACB.FD = (uint8_t)((pstcConfig->bFixedDestination == TRUE) ? 1u : 0u); + + // Reload Count (BC/TC reload) + unDmacDmacb.stcDMACB.RC = (uint8_t)((pstcConfig->bReloadCount == TRUE) ? 1u : 0u); + + // Reload Source + unDmacDmacb.stcDMACB.RS = (uint8_t)((pstcConfig->bReloadSource == TRUE) ? 1u : 0u); + + // Reload Destination + unDmacDmacb.stcDMACB.RD = (uint8_t)((pstcConfig->bReloadDestination == TRUE) ? 1u : 0u); + + // Enable bit mask + unDmacDmacb.stcDMACB.EM = (uint8_t)((pstcConfig->bEnableBitMask == TRUE) ? 1u : 0u); + +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) + // Set interrupt + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bCompleteIrq) + { + unDmacDmacb.stcDMACB.CI = 1; + } + + if(TRUE == pstcConfig->pstcIrqEn->bErrorIrq) + { + unDmacDmacb.stcDMACB.EI = 1; + } + } +#endif + + // ... and update hardware + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) + = unDmacDmacb.u32DMACB ; + + // Setup source address + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMASA_OFFSET)) + = pstcConfig->u32SourceAddress; + + // Setup destination address + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMADA_OFFSET)) + = pstcConfig->u32DestinationAddress; + + // Switch resource interrupt to DMA (except software DMA) + if (pstcConfig->enDmaIdrq != Software) + { + u32DrqselBit = 1ul << (uint32_t)(pstcConfig->enDmaIdrq); + FM_INTREQ->DRQSEL |= u32DrqselBit; + } + +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) + // Set interrupt callback functions + if(NULL != pstcConfig->pstcIrqCb) + { + stcDmaInternData.apfnDmaIrqCompletionCb[u8InstanceIdx] = pstcConfig->pstcIrqCb->pfnDmaCompletionIrqCb; + stcDmaInternData.apfnDmaErrorIrqCb[u8InstanceIdx] = pstcConfig->pstcIrqCb->pfnDmaErrorIrqCb; + } + + // Set NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + DmaInitNvic(u8DmaChannel); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initializes a DMA channel + ** + ** Clears an DMA channel. + ** + ** \param [in] u8DmaChannel DMA channel number + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok init successful + ** \retval ErrorInvalidParameter pstcAdc == NULL or other invalid configuration + ** + ******************************************************************************/ +en_result_t Dma_DeInitChannel(uint8_t u8DmaChannel, boolean_t bTouchNvic) +{ + uint32_t u32DmaRegisterBaseAddress; + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // clear all registers of DMA channel + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACA_OFFSET)) = 0u; + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) = 0u; + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMASA_OFFSET)) = 0u; + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMADA_OFFSET)) = 0u; + +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) + if (TRUE == bTouchNvic) + { + DmaDeInitNvic(u8DmaChannel); + } +#endif + + return Ok; +} // Dma_DeInit_Channel + +/** + ****************************************************************************** + ** \brief Enable, disable, pause, or trigger a DMA channel via configuration + ** + ** This function enables, disables, pauses or triggers a DMA transfer according + ** to the settings in the configuration bits for EB (Enable), PB (Pause) and + ** ST (Software Trigger) + ** + ** \param [in] u8DmaChannel DMA channel number + ** \param [in] bEnable Enable the channel or not + ** \param [in] bPause Pause the channel or not + ** \param [in] bSoftwareTrigger Trigger DMA by software or not + ** + ** \retval Ok Setting finished + ** + ******************************************************************************/ +en_result_t Dma_SetChannel (uint8_t u8DmaChannel, + boolean_t bEnable, + boolean_t bPause, + boolean_t bSoftwareTrigger) +{ + un_dmac_dmaca_t unDmacDmaca; + uint32_t u32RegisterReadOut ; + uint32_t u32DmaRegisterBaseAddress ; + + unDmacDmaca.u32DMACA = 0u; + unDmacDmaca.stcDMACA.EB = (uint8_t)((bEnable == TRUE) ? 1u : 0u); + unDmacDmaca.stcDMACA.PB = (uint8_t)((bPause == TRUE) ? 1u : 0u); + unDmacDmaca.stcDMACA.ST = (uint8_t)((bSoftwareTrigger == TRUE) ? 1u : 0u); + + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // Readout DMACA and update + u32RegisterReadOut = *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACA_OFFSET)) ; + unDmacDmaca.u32DMACA |= (u32RegisterReadOut & 0x1FFFFFFFu); // masking EB, PB, ST ... + *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACA_OFFSET)) = unDmacDmaca.u32DMACA ; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read stop cause of a DMA channel + ** + ** \param [in] u8DmaChannel DMA channel + ** + ** \retval DmaStopByAddrOverflow DMA stops by address overflow + ** \retval DmaStopByTransferStopRqst DMA stops by transfer stop request + ** \retval DmaStopBySrcAccessError DMA stops by source access error + ** \retval DmaStopByDstAccessError DMA stops by destination access error + ** \retval DmaStopByTransferComplete DMA stops by transfer completion + ** \retval DmaStopByTransferPause DMA stops by transfer pause + ** + ******************************************************************************/ +dma_stop_cause_t Dma_GetStopCause(uint8_t u8DmaChannel) +{ + un_dmac_dmacb_t unDmacDmacb; + uint32_t u32DmaRegisterBaseAddress; + + u32DmaRegisterBaseAddress = GET_DMA_ADDRESS(u8DmaChannel); + + // Readout original DMACB + unDmacDmacb.u32DMACB = *(uint32_t*)((uint32_t)(u32DmaRegisterBaseAddress + DMA_DMACB_OFFSET)) ; + + return (dma_stop_cause_t) (unDmacDmacb.stcDMACB.SS); +} + +/** + ****************************************************************************** + ** \brief Enable DMA globally + ** + ** \retval Ok Enable finished + ** + ******************************************************************************/ +en_result_t Dma_Enable(void) +{ + FM_DMAC->DMACR = 0x80000000ul; // Set DE Bit (DMA enable all channels) + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable DMA globally + ** + ** \retval Ok Disable finished + ** + ******************************************************************************/ +en_result_t Dma_Disable(void) +{ + FM_DMAC->DMACR = 0u; // Clear everything + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Pause DMA globally + ** + ** \retval Ok Pause finished + ** + ******************************************************************************/ +en_result_t Dma_Pause(void) +{ + FM_DMAC->DMACR_f.DH = 0x0Fu; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Resume DMA globally + ** + ** \retval Ok Resume from pause status finished + ** + ******************************************************************************/ +en_result_t Dma_Resume(void) +{ + FM_DMAC->DMACR_f.DH = 0x0000u; + + return Ok; +} + +#if (PDL_MCU_TYPE == PDL_FM3_TYPE2) +/** + ****************************************************************************** + ** \brief Select a source for the IRQ10 input of DMA + ** + ** Re-select the DMA IRQ10 source + ** + ** \param [in] enDmaIrq10Sel The sources which can be selected, see + ** #en_dma_irq10_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq10Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq10Selector(en_dma_irq10_sel_t enDmaIrq10Sel) +{ + switch (enDmaIrq10Sel) + { + case DmaIrq10Bt4Irq0: + FM_INTREQ->DQESEL_f.ESEL10 = 0u; + break; + case DmaIrq10Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL10 = 1u; + break; + case DmaIrq10Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL10 = 2u; + break; + case DmaIrq10Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL10 = 3u; + break; + case DmaIrq10Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL10 = 4u; + break; + case DmaIrq10Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL10 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ11 input of DMA + ** + ** Re-select the DMA IRQ11 source + ** + ** \param [in] enDmaIrq11Sel The sources which can be selected, see + ** #en_dma_irq11_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq11Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq11Selector(en_dma_irq11_sel_t enDmaIrq11Sel) +{ + switch (enDmaIrq11Sel) + { + case DmaIrq11Bt6Irq0: + FM_INTREQ->DQESEL_f.ESEL11 = 0u; + break; + case DmaIrq11Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL11 = 1u; + break; + case DmaIrq11Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL11 = 2u; + break; + case DmaIrq11Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL11 = 3u; + break; + case DmaIrq11Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL11 = 4u; + break; + case DmaIrq11Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL11 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ24 input of DMA + ** + ** Re-select the DMA IRQ24 source + ** + ** \param [in] enDmaIrq24Sel The sources which can be selected, see + ** #en_dma_irq24_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq24Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq24Selector(en_dma_irq24_sel_t enDmaIrq24Sel) +{ + switch (enDmaIrq24Sel) + { + case DmaIrq24Mfs6Rx: + FM_INTREQ->DQESEL_f.ESEL24 = 0u; + break; + case DmaIrq24Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL24 = 1u; + break; + case DmaIrq24Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL24 = 2u; + break; + case DmaIrq24Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL24 = 3u; + break; + case DmaIrq24Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL24 = 4u; + break; + case DmaIrq24Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL24 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ25 input of DMA + ** + ** Re-select the DMA IRQ25 source + ** + ** \param [in] enDmaIrq25Sel The sources which can be selected, see + ** #en_dma_irq25_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq25Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq25Selector(en_dma_irq25_sel_t enDmaIrq25Sel) +{ + switch (enDmaIrq25Sel) + { + case DmaIrq25Mfs6Tx: + FM_INTREQ->DQESEL_f.ESEL25 = 0u; + break; + case DmaIrq24Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL25 = 1u; + break; + case DmaIrq24Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL25 = 2u; + break; + case DmaIrq24Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL25 = 3u; + break; + case DmaIrq24Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL25 = 4u; + break; + case DmaIrq24Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL25 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ26 input of DMA + ** + ** Re-select the DMA IRQ26 source + ** + ** \param [in] enDmaIrq26Sel The sources which can be selected, see + ** #en_dma_irq26_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq26Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq26Selector(en_dma_irq26_sel_t enDmaIrq26Sel) +{ + switch (enDmaIrq26Sel) + { + case DmaIrq26Mfs7Rx: + FM_INTREQ->DQESEL_f.ESEL26 = 0u; + break; + case DmaIrq26Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL26 = 1u; + break; + case DmaIrq26Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL26 = 2u; + break; + case DmaIrq26Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL26 = 3u; + break; + case DmaIrq26Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL26 = 4u; + break; + case DmaIrq26Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL26 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ27 input of DMA + ** + ** Re-select the DMA IRQ27 source + ** + ** \param [in] enDmaIrq27Sel The sources which can be selected, see + ** #en_dma_irq27_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq27Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq27Selector(en_dma_irq27_sel_t enDmaIrq27Sel) +{ + switch (enDmaIrq27Sel) + { + case DmaIrq27Mfs7Tx: + FM_INTREQ->DQESEL_f.ESEL27 = 0u; + break; + case DmaIrq27Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL27 = 1u; + break; + case DmaIrq27Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL27 = 2u; + break; + case DmaIrq27Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL27 = 3u; + break; + case DmaIrq27Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL27 = 4u; + break; + case DmaIrq27Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL27 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ30 input of DMA + ** + ** Re-select the DMA IRQ30 source + ** + ** \param [in] enDmaIrq30Sel The sources which can be selected, see + ** #en_dma_irq30_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq30Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq30Selector(en_dma_irq30_sel_t enDmaIrq30Sel) +{ + switch (enDmaIrq30Sel) + { + case DmaIrq30ExtIrq2: + FM_INTREQ->DQESEL_f.ESEL30 = 0u; + break; + case DmaIrq30Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL30 = 1u; + break; + case DmaIrq30Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL30 = 2u; + break; + case DmaIrq30Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL30 = 3u; + break; + case DmaIrq30Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL30 = 4u; + break; + case DmaIrq30Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL30 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select a source for the IRQ31 input of DMA + ** + ** Re-select the DMA IRQ31 source + ** + ** \param [in] enDmaIrq31Sel The sources which can be selected, see + ** #en_dma_irq31_sel_t for the details. + ** + ** \retval Ok Selected normally + ** \retval ErrorInvalidParameter enDmaIrq31Sel is out of range + ** + ** \note This function is only avaible for FM3 TYPE2 product + ** + ******************************************************************************/ +en_result_t Dma_SetIrq31Selector(en_dma_irq31_sel_t enDmaIrq31Sel) +{ + switch (enDmaIrq31Sel) + { + case DmaIrq31ExtIrq3: + FM_INTREQ->DQESEL_f.ESEL31 = 0u; + break; + case DmaIrq31Usb1Ep1: + FM_INTREQ->DRQSEL1_f.USB1EP1 = 1u; + FM_INTREQ->DQESEL_f.ESEL31 = 1u; + break; + case DmaIrq31Usb1Ep2: + FM_INTREQ->DRQSEL1_f.USB1EP2 = 1u; + FM_INTREQ->DQESEL_f.ESEL31 = 2u; + break; + case DmaIrq31Usb1Ep3: + FM_INTREQ->DRQSEL1_f.USB1EP3 = 1u; + FM_INTREQ->DQESEL_f.ESEL31 = 3u; + break; + case DmaIrq31Usb1Ep4: + FM_INTREQ->DRQSEL1_f.USB1EP4 = 1u; + FM_INTREQ->DQESEL_f.ESEL31 = 4u; + break; + case DmaIrq31Usb1Ep5: + FM_INTREQ->DRQSEL1_f.USB1EP5 = 1u; + FM_INTREQ->DQESEL_f.ESEL31 = 5u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#endif + +#endif // #if (defined(PDL_PERIPHERAL_DMA_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.h new file mode 100644 index 0000000000..4ffa234fa1 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dma/dma.h @@ -0,0 +1,490 @@ +/****************************************************************************** +* \file dma.h +* +* \version 1.20 +* +* \brief Header file of Direct Memory Access Controller function +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __DMA_H__ +#define __DMA_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_DMA_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/** +* \defgroup GroupDMA Direct Memory Access Controller (DMA) +* \{ +* \defgroup GroupDMA_Macros Macros +* \defgroup GroupDMA_Functions Functions +* \defgroup GroupDMA_GlobalVariables Global Variables +* \defgroup GroupDMA_DataStructures Data Structures +* \defgroup GroupDMA_Types Enumerated Types +* \} +*/ +/** +* \addtogroup GroupDMA +* \{ +* The Direct Memory Access Controller (DMA) transfers data at high speed without +* using the CPU. DMA has an independent bus, so memory transfers are not affected by +* CPU bus access.
+* - DMA supports a maximum of eight channels, so eight different +* DMA transfers can occur independently
+* - You set the address of the transfer destination, the address of the +* transfer source, the size of transfer data, the source of transfer request, +* and the transfer mode
+* You control the start of transfer operation, the +* forced termination of a transfer, and can pause the transfer for each channel
+* - You can control DMA channels individually, or as a batch
+* - You can use BT, EXINT, MFS or ADC peripheral as an interrupt source
+* - DMA complies with the system bus (AHB), supporting 32-bit address space +* (up to 4 Gbytes).
+* There are three transfer modes:
+* - Block – a number of data elements of the specified width, with a +* timing gap between blocks; this enables the DMA controller to switch among multiple channels
+* - Burst – a number of data elements of the specified width, with no timing gap; +* this enables the channel to have priority and complete transfer before another channel is enabled
+* - Demand – for interrupt-driven transfers; DMA receives a transfer request from the peripheral
+* +* \section SectionDMA_ConfigurationConsideration Configuration Consideration +* You specify configuration options in the stc_dma_config_t structure. Each channel has its +* own configuration. As noted in the General Description there are several options, including:
+* - The interrupt source (including software as the trigger)
+* - The source and destination addresses
+* - Whether to reload the original source and destination addresses upon completion of the transfer
+* - Data width (8-, 16-, or 32-bit)
+* - Transfer mode (block, burst, demand)
+* If you use interrupt-driven DMA, you also provide configuration structures to enable and identify +* the required callback functions for the channel.
+* Call Dma_InitChannel() to initialize a DMA channel. Use Use Dma_SetChannel() to enable, disable, +* pause, or trigger a data transfer by software control. As noted, the configuration structure sets +* up interrupts for the channel. After initializing, you can enable and disable interrupts +* for a single channel with Dma_EnableIrq() and Dma_DisableIrq() with Dma_EnableIrq() and Dma_DisableIrq().
+* For batch control, use Dma_Enable(), Dma_Disable(), Dma-Pause(), or Dma_Resume() to control all channels.
+* For FM3 Type 2 parts only, the Dma_SetIrqXXSelector() sets the source selection of IRQXX which is used to +* trigger DMA, where XX is 10, 11, 24, 25, 26, 27, 30, 31.
+* +* \section SectionDMA_MoreInfo More Information +* For more information on the DMA peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem TRM.pdf
+* FM4 Peripheral Manual Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupDMA_Macros +* \{ +*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define PDL_DMA_CHANNELS 8u +#define PDL_DMA_INSTANCE_COUNT (PDL_PERIPHERAL_ENABLE_DMA0 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA1 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA2 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA3 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA4 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA5 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA6 == PDL_ON) + \ + (PDL_PERIPHERAL_ENABLE_DMA7 == PDL_ON) + +// register address offset +#define DMA_DMACA_OFFSET 0x00ul +#define DMA_DMACB_OFFSET 0x04ul +#define DMA_DMASA_OFFSET 0x08ul +#define DMA_DMADA_OFFSET 0x0Cul + +/** \} GroupDMA_Macros */ + +/** +* \addtogroup GroupDMA_Types +* \{ +*/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief DMA transfer data width + ******************************************************************************/ +typedef enum en_dma_transfermode +{ + DmaBlockTransfer = 0u, ///< Block Transfer + DmaBurstTransfer = 1u, ///< Burst transfer + DmaDemandTransfer = 2u ///< Demand transfer +} en_dma_transfermode_t ; + +/** + ****************************************************************************** + ** \brief DMA transfer data width + ******************************************************************************/ +typedef enum en_dma_transferwidth +{ + Dma8Bit = 0u, ///< 8 bit transfer via DMA + Dma16Bit = 1u, ///< 16 bit transfer via DMA + Dma32Bit = 2u ///< 32 bit transfer via DMA +} en_dma_transferwidth_t ; + +#if (PDL_MCU_TYPE == PDL_FM3_TYPE2) +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ10 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq10_sel +{ + DmaIrq10Bt4Irq0 = 0u, ///< Base timer ch.4 Interrupt signal of IRQ0 + DmaIrq10Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq10Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq10Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq10Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq10Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq10_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ11 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq11_sel +{ + DmaIrq11Bt6Irq0 = 0u, ///< Base timer ch.6 Interrupt signal of IRQ0 + DmaIrq11Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq11Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq11Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq11Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq11Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq11_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ24 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq24_sel +{ + DmaIrq24Mfs6Rx = 0u, ///< MFS ch.6 Receive interrupt signal + DmaIrq24Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq24Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq24Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq24Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq24Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq24_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ25 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq25_sel +{ + DmaIrq25Mfs6Tx = 0u, ///< MFS ch.6 Send interrupt signal + DmaIrq25Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq25Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq25Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq25Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq25Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq25_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ26 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq26_sel +{ + DmaIrq26Mfs7Rx = 0u, ///< MFS ch.7 Receive interrupt signal + DmaIrq26Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq26Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq26Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq26Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq26Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq26_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ27 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq27_sel +{ + DmaIrq27Mfs7Tx = 0u, ///< MFS ch.7 Send interrupt signal + DmaIrq27Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq27Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq27Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq27Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq27Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq27_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ30 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq30_sel +{ + DmaIrq30ExtIrq2 = 0u, ///< External interrupt ch.2 signal + DmaIrq30Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq30Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq30Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq30Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq30Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq30_sel_t; + +/** + ****************************************************************************** + ** \brief DMA source selection of IRQ31 + ** + ** \note Only available for FM3 TYPE2 products + ******************************************************************************/ +typedef enum en_dma_irq31_sel +{ + DmaIrq31ExtIrq3 = 0u, ///< External interrupt ch.3 signal + DmaIrq31Usb1Ep1 = 1u, ///< USB ch.1 EP1 DRQ interrupt signal + DmaIrq31Usb1Ep2 = 2u, ///< USB ch.1 EP2 DRQ interrupt signal + DmaIrq31Usb1Ep3 = 3u, ///< USB ch.1 EP3 DRQ interrupt signal + DmaIrq31Usb1Ep4 = 4u, ///< USB ch.1 EP4 DRQ interrupt signal + DmaIrq31Usb1Ep5 = 5u, ///< USB ch.1 EP5 DRQ interrupt signal + +}en_dma_irq31_sel_t; +#endif + +/** + ****************************************************************************** + ** \brief DMA IDREQ number + ******************************************************************************/ +typedef enum en_dma_idreq +{ + Usb0Ep1 = 0u, ///< Interrupt signal from EP1 DRQ of USB ch.0 + Usb0Ep2 = 1u, ///< Interrupt signal from EP2 DRQ of USB ch.0 + Usb0Ep3 = 2u, ///< Interrupt signal from EP3 DRQ of USB ch.0 + Usb0Ep4 = 3u, ///< Interrupt signal from EP4 DRQ of USB ch.0 + Usb0Ep5 = 4u, ///< Interrupt signal from EP5 DRQ of USB ch.0 + Adc0 = 5u, ///< Scan conversion interrupt signal from A/D converter unit0 + Adc1 = 6u, ///< Scan conversion interrupt signal from A/D converter unit1 + Adc2 = 7u, ///< Scan conversion interrupt signal from A/D converter unit2 + Bt0Irq0 = 8u, ///< Interrupt signal from IRQ0 of base timer ch.0 + Bt2Irq0 = 9u, ///< Interrupt signal from IRQ0 of base timer ch.2 + Bt4Irq0Sel10 = 10u, ///< Default: Interrupt signal from IRQ0 of base timer ch.4, it can also be selected by Dma_SetIrq10Selector() + Bt6Irq0Sel11 = 11u, ///< Default: Interrupt signal from IRQ0 of base timer ch.6, it can also be selected by Dma_SetIrq11Selector() + MfsRx0 = 12u, ///< Receiving interrupt signal from MFS ch.0 + MfsTx0 = 13u, ///< Sending interrupt signal from MFS ch.0 + MfsRx1 = 14u, ///< Receiving interrupt signal from MFS ch.1 + MfsTx1 = 15u, ///< Sending interrupt signal from MFS ch.1 + MfsRx2 = 16u, ///< Receiving interrupt signal from MFS ch.2 + MfsTx2 = 17u, ///< Sending interrupt signal from MFS ch.2 + MfsRx3 = 18u, ///< Receiving interrupt signal from MFS ch.3 + MfsTx3 = 19u, ///< Sending interrupt signal from MFS ch.3 + MfsRx4 = 20u, ///< Receiving interrupt signal from MFS ch.4 + MfsTx4 = 21u, ///< Sending interrupt signal from MFS ch.4 + MfsRx5 = 22u, ///< Receiving interrupt signal from MFS ch.5 + MfsTx5 = 23u, ///< Sending interrupt signal from MFS ch.5 + MfsRx6Sel24 = 24u, ///< Default: Receiving interrupt signal from MFS ch.6, it can also be selected by Dma_SetIrq24Selector() + MfsTx6Sel25 = 25u, ///< Default: Sending interrupt signal from MFS ch.6, it can also be selected by Dma_SetIrq25Selector() + MfsRx7Sel26 = 26u, ///< Default: Receiving interrupt signal from MFS ch.7, it can also be selected by Dma_SetIrq26Selector() + MfsTx7Sel27 = 27u, ///< Default: Sending interrupt signal from MFS ch.7, it can also be selected by Dma_SetIrq27Selector() + ExtIrq0 = 28u, ///< Interrupt signal from external interrupt unit ch.0 + ExtIrq1 = 29u, ///< Interrupt signal from external interrupt unit ch.1 + ExtIrq2Sel30 = 30u, ///< Default: Interrupt signal from external interrupt unit ch.2, it can also be selected by Dma_SetIrq30Selector() + ExtIrq3Sel31 = 31u, ///< Interrupt signal from external interrupt unit ch.3, it can also be selected by Dma_SetIrq31Selector() + Software = 1234u ///< Software Demand (just a high number) +} en_dma_idreq_t ; + +/** + ****************************************************************************** + ** \brief DMA stop cause + ******************************************************************************/ +typedef enum dma_stop_cause +{ + DmaStopByAddrOverflow = 0u, ///< DMA stops by address overflow + DmaStopByTransferStopRqst = 1u, ///< DMA stops by transfer stop request + DmaStopBySrcAccessError = 2u, ///< DMA stops by source access error + DmaStopByDstAccessError = 3u, ///< DMA stops by destination access error + DmaStopByTransferComplete = 4u, ///< DMA stops by transfer completion + DmaStopByTransferPause = 5u, ///< DMA stops by transfer pause + +}dma_stop_cause_t; + +/** \}GroupDMA_Types */ + +/** +* \addtogroup GroupDMA_DataStructures +* \{ +*/ +/** + ****************************************************************************** + ** \brief DMA interrupt selection + ******************************************************************************/ +typedef struct stc_dma_irq_sel +{ + boolean_t bCompleteIrq; ///< Select DMA transfer completion interrupt + boolean_t bErrorIrq; ///< Select DMA transfer error interrupt + +}stc_dma_irq_sel_t, stc_dma_irq_en_t; + +/** + ****************************************************************************** + ** \brief DMA interrupt callback function + ******************************************************************************/ +typedef struct stc_dma_irq_cb +{ + func_ptr_t pfnDmaCompletionIrqCb; ///< Pointer to DMA transfer completion interrupt callback function + func_ptr_arg1_t pfnDmaErrorIrqCb; ///< Pointer to DMA transfer error interrupt callback function + +}stc_dma_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Datatype for holding internal data needed for DMA + ******************************************************************************/ +typedef struct stc_dma_intern_data +{ + func_ptr_t apfnDmaIrqCompletionCb[PDL_DMA_INSTANCE_COUNT]; ///< DMA transfer completion callback pointer array + func_ptr_arg1_t apfnDmaErrorIrqCb[PDL_DMA_INSTANCE_COUNT]; ///< DMA error callback pointer array + +} stc_dma_intern_data_t; + +/** + ****************************************************************************** + ** \brief DMA configuration + ******************************************************************************/ +typedef struct stc_dma_config +{ + en_dma_idreq_t enDmaIdrq ; ///< ID Request number (see #en_dma_idreq_t for details) + uint8_t u8BlockCount ; ///< Block counter + uint16_t u16TransferCount ; ///< Transfer counter + en_dma_transfermode_t enTransferMode ; ///< DMA transfer mode (see #en_dma_transfermode_t for details) + en_dma_transferwidth_t enTransferWidth ; ///< DMA transfer width (see #en_dma_transferwidth_t for details) + uint32_t u32SourceAddress; ///< Source address + uint32_t u32DestinationAddress ; ///< Destination address + boolean_t bFixedSource ; ///< TRUE = source address not increased + boolean_t bFixedDestination ; ///< TRUE = destiantion address not increased + boolean_t bReloadCount ; ///< TRUE = count is reloaded + boolean_t bReloadSource ; ///< TRUE = source address is reloaded + boolean_t bReloadDestination ; ///< TRUE = destination address is reloaded + boolean_t bEnableBitMask ; ///< FALSE = Clear EB (bEnable) bit on completion (mandatory for transfer end!) +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) + stc_dma_irq_en_t* pstcIrqEn; ///< Pointer to DMA interrupt enable structure + stc_dma_irq_cb_t* pstcIrqCb; ///< Pointer to DMA interrupt callback function structure + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: disable NVIC +#endif + +} stc_dma_config_t ; + +/** \} GroupDMA_DataStructures */ + +/** +* \addtogroup GroupDMA_GlobalVariables +* \{ +*/ +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +extern stc_dma_intern_data_t stcDmaInternData; +/** \} GroupDMA_GlobalVariables*/ + +/** +* \addtogroup GroupDMA_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_DMA0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA3 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA5 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_DMA6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_DMA7 == PDL_ON) +void DmaIrqHandler(uint8_t u8DmaChannel) ; +en_result_t Dma_EnableIrq(uint8_t u8DmaChannel, + stc_dma_irq_sel_t* pstcIrqSel); +en_result_t Dma_DisableIrq(uint8_t u8DmaChannel, + stc_dma_irq_sel_t* pstcIrqSel); +#endif +/* Init/DeInit a DMA channel */ +en_result_t Dma_InitChannel(uint8_t u8DmaChannel, const stc_dma_config_t* pstcConfig); +en_result_t Dma_DeInitChannel(uint8_t u8DmaChannel, boolean_t bTouchNvic); +/* Irq 10,11,24,25,26,27,30,31 Selection */ +#if (PDL_MCU_TYPE == PDL_FM3_TYPE2) +en_result_t Dma_SetIrq10Selector(en_dma_irq10_sel_t enDmaIrq10Sel); +en_result_t Dma_SetIrq11Selector(en_dma_irq11_sel_t enDmaIrq11Sel); +en_result_t Dma_SetIrq24Selector(en_dma_irq24_sel_t enDmaIrq24Sel); +en_result_t Dma_SetIrq25Selector(en_dma_irq25_sel_t enDmaIrq25Sel); +en_result_t Dma_SetIrq26Selector(en_dma_irq26_sel_t enDmaIrq26Sel); +en_result_t Dma_SetIrq27Selector(en_dma_irq27_sel_t enDmaIrq27Sel); +en_result_t Dma_SetIrq30Selector(en_dma_irq30_sel_t enDmaIrq30Sel); +en_result_t Dma_SetIrq31Selector(en_dma_irq31_sel_t enDmaIrq30Sel); +#endif +/* Activate a DMA channel */ +en_result_t Dma_SetChannel (uint8_t u8DmaChannel, + boolean_t bEnable, + boolean_t bPause, + boolean_t bSoftwareTrigger) ; +/* Stop casue read/clear */ +dma_stop_cause_t Dma_GetStopCause(uint8_t u8DmaChannel); +en_result_t Dma_ClrStopCause (uint8_t u8DmaChannel); +/* Globally enable/disable all channels */ +en_result_t Dma_Enable(void) ; +en_result_t Dma_Disable(void) ; +/* Globally pause/resume all channels */ +en_result_t Dma_Pause(void) ; +en_result_t Dma_Resume(void) ; + +/** \} GroupDMA_Functions */ +/** \} GroupDMA */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_DMA_ACTIVE)) + +#endif /* __DMA_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.c new file mode 100644 index 0000000000..fbee0f8e8a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.c @@ -0,0 +1,2848 @@ +/****************************************************************************** +* \file dstc.c +* +* \version 1.40 +* +* \brief Descriptor System Data Transfer Controller driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "dstc/dstc.h" + +#if (defined(PDL_PERIPHERAL_DSTC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static stc_dstc_intern_data_t stcDstcInternData; + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Interrupt Service Routine of DSTC + ******************************************************************************/ +void Dstc_IrqHandler(void) +{ + en_dstc_est_error_t enEstError = NoError; + uint8_t u8ErrorStatus; + uint16_t u16ErrorChannel; ///< Error channel, if HS == 1; 0xFFFF, if HS == 0 + uint16_t u16ErrorDesPointer; + boolean_t bSoftwareError; + boolean_t bDoubleError = FALSE; + boolean_t bErrorStop = FALSE; + boolean_t bError = FALSE; + + // Check for SW transfer flag + if (TRUE == (FM_DSTC->SWTR_f.SWST)) + { + Dstc_SetCommand(CmdSwclr); // SW transfer interrupt clear + } + + if (0u != FM_DSTC->MONERS_f.EST) // Error Status + { + bError = TRUE; + + u8ErrorStatus = (uint8_t)FM_DSTC->MONERS_f.EST; // Read Error Status + + switch (u8ErrorStatus) + { + case 1: + enEstError = SourceAccessError; + break; + case 2: + enEstError = DestinationAccessError; + break; + case 3: + enEstError = ForcedTransferStop; + break; + case 4: + enEstError = DesAccessError; + break; + case 5: + enEstError = DesOpenError; + break; + default: + enEstError = UnknownError; + } + + if (TRUE == FM_DSTC->MONERS_f.EHS) + { + u16ErrorChannel = (uint16_t) (0x00FFu & FM_DSTC->MONERS_f.ECH); // Error Channel + } + else + { + u16ErrorChannel = 0xFFFFu; // '-1' + } + + u16ErrorDesPointer = (uint16_t)(0x3FFu & FM_DSTC->MONERS_f.EDESP); // Error DES Pointer + + bSoftwareError = (FALSE == FM_DSTC->MONERS_f.EHS) ? TRUE : FALSE; + bDoubleError = (TRUE == FM_DSTC->MONERS_f.DER) ? TRUE : FALSE; + bErrorStop = (TRUE == FM_DSTC->MONERS_f.ESTOP) ? TRUE : FALSE; + + Dstc_SetCommand(CmdErclr); // Clear Error + + if (NULL != stcDstcInternData.pfnErrorCallback) + { + stcDstcInternData.pfnErrorCallback( enEstError, + u16ErrorChannel, + u16ErrorDesPointer, + bSoftwareError, + bDoubleError, + bErrorStop); + } + } + + if (FALSE == bError) + { + if (stcDstcInternData.pfnNotifySwCallback != NULL) + { + stcDstcInternData.pfnNotifySwCallback(); + } + } +} + +/** + ****************************************************************************** + ** \brief Release DSTC from Standby State + ** + ** \retval Ok DSTC released from standby mode + ** \retval ErrorNotReady DSTC standby release failed + ******************************************************************************/ +en_result_t Dstc_ReleaseStandBy(void) +{ + uint32_t u32DstcTimeOut; + + Dstc_SetCommand(CmdStandyRelease); + + u32DstcTimeOut = DSTC_TRANSITION_TIMEOUT; + while ((0x02u == FM_DSTC->CMD) && (0u != u32DstcTimeOut)) + { + u32DstcTimeOut--; + } + + if ((0u == u32DstcTimeOut) || (0u != FM_DSTC->CMD)) + { + return ErrorNotReady; + } + + return Ok; +} // Dstc_ReleaseStandBy + +/** + ****************************************************************************** + ** \brief Initializes the DSTC according the Configuration + ** + ** \param [in] pstcConfig Pointer to DSTC Configuration + ** + ** \retval Ok DSTC Initialized + ** \retval ErrorNotReady DSTC standby initialization failed + ** \retval ErrorInvalidParameter pstcConfig == NULL or other configuration wrong + ** \retval ErrorAddressAlignment DES Base Address not aligned to 32 Bit + ******************************************************************************/ +en_result_t Dstc_Init( const stc_dstc_config_t* pstcConfig ) +{ + stc_dstc_cfg_field_t stcCfg; + + if (NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + + if (0u != ((pstcConfig->u32Destp) & 0x00000003ul)) + { + return ErrorAddressAlignment; + } + + if (Ok != Dstc_ReleaseStandBy()) + { + return ErrorNotReady; + } + + stcDstcInternData.pfnNotifySwCallback = pstcConfig->pfnNotifySwCallback; + stcDstcInternData.pfnErrorCallback = pstcConfig->pfnErrorCallback; + +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + stcDstcInternData.pfnDstcAdc0PrioCallback = pstcConfig->pfnDstcAdc0PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) + stcDstcInternData.pfnDstcAdc0ScanCallback = pstcConfig->pfnDstcAdc0ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + stcDstcInternData.pfnDstcAdc1PrioCallback = pstcConfig->pfnDstcAdc1PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) + stcDstcInternData.pfnDstcAdc1ScanCallback = pstcConfig->pfnDstcAdc1ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + stcDstcInternData.pfnDstcAdc2PrioCallback = pstcConfig->pfnDstcAdc2PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) + stcDstcInternData.pfnDstcAdc2ScanCallback = pstcConfig->pfnDstcAdc2ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + stcDstcInternData.pfnDstcBt0Irq0Callback = pstcConfig->pfnDstcBt0Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) + stcDstcInternData.pfnDstcBt0Irq1Callback = pstcConfig->pfnDstcBt0Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + stcDstcInternData.pfnDstcBt1Irq0Callback = pstcConfig->pfnDstcBt1Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) + stcDstcInternData.pfnDstcBt1Irq1Callback = pstcConfig->pfnDstcBt1Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + stcDstcInternData.pfnDstcBt2Irq0Callback = pstcConfig->pfnDstcBt2Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) + stcDstcInternData.pfnDstcBt2Irq1Callback = pstcConfig->pfnDstcBt2Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + stcDstcInternData.pfnDstcBt3Irq0Callback = pstcConfig->pfnDstcBt3Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) + stcDstcInternData.pfnDstcBt3Irq1Callback = pstcConfig->pfnDstcBt3Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + stcDstcInternData.pfnDstcBt4Irq0Callback = pstcConfig->pfnDstcBt4Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) + stcDstcInternData.pfnDstcBt4Irq1Callback = pstcConfig->pfnDstcBt4Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + stcDstcInternData.pfnDstcBt5Irq0Callback = pstcConfig->pfnDstcBt5Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) + stcDstcInternData.pfnDstcBt5Irq1Callback = pstcConfig->pfnDstcBt5Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + stcDstcInternData.pfnDstcBt6Irq0Callback = pstcConfig->pfnDstcBt6Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) + stcDstcInternData.pfnDstcBt6Irq1Callback = pstcConfig->pfnDstcBt6Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + stcDstcInternData.pfnDstcBt7Irq0Callback = pstcConfig->pfnDstcBt7Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) + stcDstcInternData.pfnDstcBt7Irq1Callback = pstcConfig->pfnDstcBt7Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) + stcDstcInternData.pfnDstcBt8Irq0Callback = pstcConfig->pfnDstcBt8Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) + stcDstcInternData.pfnDstcBt8Irq1Callback = pstcConfig->pfnDstcBt8Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) + stcDstcInternData.pfnDstcBt9Irq0Callback = pstcConfig->pfnDstcBt9Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) + stcDstcInternData.pfnDstcBt9Irq1Callback = pstcConfig->pfnDstcBt9Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) + stcDstcInternData.pfnDstcBt10Irq0Callback = pstcConfig->pfnDstcBt10Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) + stcDstcInternData.pfnDstcBt10Irq1Callback = pstcConfig->pfnDstcBt10Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) + stcDstcInternData.pfnDstcBt11Irq0Callback = pstcConfig->pfnDstcBt11Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) + stcDstcInternData.pfnDstcBt11Irq1Callback = pstcConfig->pfnDstcBt11Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) + stcDstcInternData.pfnDstcBt12Irq0Callback = pstcConfig->pfnDstcBt12Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) + stcDstcInternData.pfnDstcBt12Irq1Callback = pstcConfig->pfnDstcBt12Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) + stcDstcInternData.pfnDstcBt13Irq0Callback = pstcConfig->pfnDstcBt13Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) + stcDstcInternData.pfnDstcBt13Irq1Callback = pstcConfig->pfnDstcBt13Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) + stcDstcInternData.pfnDstcBt14Irq0Callback = pstcConfig->pfnDstcBt14Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) + stcDstcInternData.pfnDstcBt14Irq1Callback = pstcConfig->pfnDstcBt14Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ0) + stcDstcInternData.pfnDstcBt15Irq0Callback = pstcConfig->pfnDstcBt15Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ1) + stcDstcInternData.pfnDstcBt15Irq1Callback = pstcConfig->pfnDstcBt15Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + stcDstcInternData.pfnDstcExint0Callback = pstcConfig->pfnDstcExint0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + stcDstcInternData.pfnDstcExint1Callback = pstcConfig->pfnDstcExint1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + stcDstcInternData.pfnDstcExint2Callback = pstcConfig->pfnDstcExint2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + stcDstcInternData.pfnDstcExint3Callback = pstcConfig->pfnDstcExint3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + stcDstcInternData.pfnDstcExint4Callback = pstcConfig->pfnDstcExint4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + stcDstcInternData.pfnDstcExint5Callback = pstcConfig->pfnDstcExint5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + stcDstcInternData.pfnDstcExint6Callback = pstcConfig->pfnDstcExint6Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + stcDstcInternData.pfnDstcExint7Callback = pstcConfig->pfnDstcExint7Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + stcDstcInternData.pfnDstcExint8Callback = pstcConfig->pfnDstcExint8Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + stcDstcInternData.pfnDstcExint9Callback = pstcConfig->pfnDstcExint9Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + stcDstcInternData.pfnDstcExint10Callback = pstcConfig->pfnDstcExint10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + stcDstcInternData.pfnDstcExint11Callback = pstcConfig->pfnDstcExint11Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + stcDstcInternData.pfnDstcExint12Callback = pstcConfig->pfnDstcExint12Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + stcDstcInternData.pfnDstcExint13Callback = pstcConfig->pfnDstcExint13Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + stcDstcInternData.pfnDstcExint14Callback = pstcConfig->pfnDstcExint14Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + stcDstcInternData.pfnDstcExint15Callback = pstcConfig->pfnDstcExint15Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT16) + stcDstcInternData.pfnDstcExint16Callback = pstcConfig->pfnDstcExint16Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT17) + stcDstcInternData.pfnDstcExint17Callback = pstcConfig->pfnDstcExint17Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT18) + stcDstcInternData.pfnDstcExint18Callback = pstcConfig->pfnDstcExint18Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT19) + stcDstcInternData.pfnDstcExint19Callback = pstcConfig->pfnDstcExint19Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT20) + stcDstcInternData.pfnDstcExint20Callback = pstcConfig->pfnDstcExint20Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT21) + stcDstcInternData.pfnDstcExint21Callback = pstcConfig->pfnDstcExint21Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT22) + stcDstcInternData.pfnDstcExint22Callback = pstcConfig->pfnDstcExint22Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT23) + stcDstcInternData.pfnDstcExint23Callback = pstcConfig->pfnDstcExint23Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT24) + stcDstcInternData.pfnDstcExint24Callback = pstcConfig->pfnDstcExint24Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT25) + stcDstcInternData.pfnDstcExint25Callback = pstcConfig->pfnDstcExint25Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT26) + stcDstcInternData.pfnDstcExint26Callback = pstcConfig->pfnDstcExint26Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT27) + stcDstcInternData.pfnDstcExint27Callback = pstcConfig->pfnDstcExint27Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT28) + stcDstcInternData.pfnDstcExint28Callback = pstcConfig->pfnDstcExint28Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT29) + stcDstcInternData.pfnDstcExint29Callback = pstcConfig->pfnDstcExint29Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT30) + stcDstcInternData.pfnDstcExint30Callback = pstcConfig->pfnDstcExint30Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT31) + stcDstcInternData.pfnDstcExint31Callback = pstcConfig->pfnDstcExint31Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + stcDstcInternData.pfnDstcMfs0RxCallback = pstcConfig->pfnDstcMfs0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + stcDstcInternData.pfnDstcMfs0TxCallback = pstcConfig->pfnDstcMfs0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + stcDstcInternData.pfnDstcMfs1RxCallback = pstcConfig->pfnDstcMfs1RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + stcDstcInternData.pfnDstcMfs1TxCallback = pstcConfig->pfnDstcMfs1TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + stcDstcInternData.pfnDstcMfs2RxCallback = pstcConfig->pfnDstcMfs2RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + stcDstcInternData.pfnDstcMfs2TxCallback = pstcConfig->pfnDstcMfs2TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + stcDstcInternData.pfnDstcMfs3RxCallback = pstcConfig->pfnDstcMfs3RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + stcDstcInternData.pfnDstcMfs3TxCallback = pstcConfig->pfnDstcMfs3TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + stcDstcInternData.pfnDstcMfs4RxCallback = pstcConfig->pfnDstcMfs4RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + stcDstcInternData.pfnDstcMfs4TxCallback = pstcConfig->pfnDstcMfs4TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + stcDstcInternData.pfnDstcMfs5RxCallback = pstcConfig->pfnDstcMfs5RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + stcDstcInternData.pfnDstcMfs5TxCallback = pstcConfig->pfnDstcMfs5TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + stcDstcInternData.pfnDstcMfs6RxCallback = pstcConfig->pfnDstcMfs6RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + stcDstcInternData.pfnDstcMfs6TxCallback = pstcConfig->pfnDstcMfs6TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + stcDstcInternData.pfnDstcMfs7RxCallback = pstcConfig->pfnDstcMfs7RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + stcDstcInternData.pfnDstcMfs7TxCallback = pstcConfig->pfnDstcMfs7TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) + stcDstcInternData.pfnDstcMfs8RxCallback = pstcConfig->pfnDstcMfs8RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) + stcDstcInternData.pfnDstcMfs8TxCallback = pstcConfig->pfnDstcMfs8TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) + stcDstcInternData.pfnDstcMfs9RxCallback = pstcConfig->pfnDstcMfs9RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) + stcDstcInternData.pfnDstcMfs9TxCallback = pstcConfig->pfnDstcMfs9TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) + stcDstcInternData.pfnDstcMfs10RxCallback = pstcConfig->pfnDstcMfs10RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) + stcDstcInternData.pfnDstcMfs10TxCallback = pstcConfig->pfnDstcMfs10TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) + stcDstcInternData.pfnDstcMfs11RxCallback = pstcConfig->pfnDstcMfs11RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) + stcDstcInternData.pfnDstcMfs11TxCallback = pstcConfig->pfnDstcMfs11TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) + stcDstcInternData.pfnDstcMfs12RxCallback = pstcConfig->pfnDstcMfs12RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) + stcDstcInternData.pfnDstcMfs12TxCallback = pstcConfig->pfnDstcMfs12TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) + stcDstcInternData.pfnDstcMfs13RxCallback = pstcConfig->pfnDstcMfs13RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) + stcDstcInternData.pfnDstcMfs13TxCallback = pstcConfig->pfnDstcMfs13TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) + stcDstcInternData.pfnDstcMfs14RxCallback = pstcConfig->pfnDstcMfs14RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) + stcDstcInternData.pfnDstcMfs14TxCallback = pstcConfig->pfnDstcMfs14TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) + stcDstcInternData.pfnDstcMfs15RxCallback = pstcConfig->pfnDstcMfs15RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) + stcDstcInternData.pfnDstcMfs15TxCallback = pstcConfig->pfnDstcMfs15TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + stcDstcInternData.pfnDstcMft0Frt0PeakCallback = pstcConfig->pfnDstcMft0Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + stcDstcInternData.pfnDstcMft0Frt0ZeroCallback = pstcConfig->pfnDstcMft0Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + stcDstcInternData.pfnDstcMft0Frt1PeakCallback = pstcConfig->pfnDstcMft0Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + stcDstcInternData.pfnDstcMft0Frt1ZeroCallback = pstcConfig->pfnDstcMft0Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + stcDstcInternData.pfnDstcMft0Frt2PeakCallback = pstcConfig->pfnDstcMft0Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + stcDstcInternData.pfnDstcMft0Frt2ZeroCallback = pstcConfig->pfnDstcMft0Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + stcDstcInternData.pfnDstcMft0Icu0Callback = pstcConfig->pfnDstcMft0Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + stcDstcInternData.pfnDstcMft0Icu1Callback = pstcConfig->pfnDstcMft0Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + stcDstcInternData.pfnDstcMft0Icu2Callback = pstcConfig->pfnDstcMft0Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + stcDstcInternData.pfnDstcMft0Icu3Callback = pstcConfig->pfnDstcMft0Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + stcDstcInternData.pfnDstcMft0Ocu0Callback = pstcConfig->pfnDstcMft0Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + stcDstcInternData.pfnDstcMft0Ocu1Callback = pstcConfig->pfnDstcMft0Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + stcDstcInternData.pfnDstcMft0Ocu2Callback = pstcConfig->pfnDstcMft0Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + stcDstcInternData.pfnDstcMft0Ocu3Callback = pstcConfig->pfnDstcMft0Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + stcDstcInternData.pfnDstcMft0Ocu4Callback = pstcConfig->pfnDstcMft0Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + stcDstcInternData.pfnDstcMft0Ocu5Callback = pstcConfig->pfnDstcMft0Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + stcDstcInternData.pfnDstcMft0Wfg10Callback = pstcConfig->pfnDstcMft0Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + stcDstcInternData.pfnDstcMft0Wfg32Callback = pstcConfig->pfnDstcMft0Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + stcDstcInternData.pfnDstcMft0Wfg54Callback = pstcConfig->pfnDstcMft0Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) + stcDstcInternData.pfnDstcMft1Frt0PeakCallback = pstcConfig->pfnDstcMft1Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) + stcDstcInternData.pfnDstcMft1Frt0ZeroCallback = pstcConfig->pfnDstcMft1Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) + stcDstcInternData.pfnDstcMft1Frt1PeakCallback = pstcConfig->pfnDstcMft1Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) + stcDstcInternData.pfnDstcMft1Frt1ZeroCallback = pstcConfig->pfnDstcMft1Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + stcDstcInternData.pfnDstcMft1Frt2PeakCallback = pstcConfig->pfnDstcMft1Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + stcDstcInternData.pfnDstcMft1Frt2ZeroCallback = pstcConfig->pfnDstcMft1Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) + stcDstcInternData.pfnDstcMft1Icu0Callback = pstcConfig->pfnDstcMft1Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) + stcDstcInternData.pfnDstcMft1Icu1Callback = pstcConfig->pfnDstcMft1Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) + stcDstcInternData.pfnDstcMft1Icu2Callback = pstcConfig->pfnDstcMft1Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) + stcDstcInternData.pfnDstcMft1Icu3Callback = pstcConfig->pfnDstcMft1Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) + stcDstcInternData.pfnDstcMft1Ocu0Callback = pstcConfig->pfnDstcMft1Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) + stcDstcInternData.pfnDstcMft1Ocu1Callback = pstcConfig->pfnDstcMft1Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) + stcDstcInternData.pfnDstcMft1Ocu2Callback = pstcConfig->pfnDstcMft1Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) + stcDstcInternData.pfnDstcMft1Ocu3Callback = pstcConfig->pfnDstcMft1Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) + stcDstcInternData.pfnDstcMft1Ocu4Callback = pstcConfig->pfnDstcMft1Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) + stcDstcInternData.pfnDstcMft1Ocu5Callback = pstcConfig->pfnDstcMft1Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) + stcDstcInternData.pfnDstcMft1Wfg10Callback = pstcConfig->pfnDstcMft1Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) + stcDstcInternData.pfnDstcMft1Wfg32Callback = pstcConfig->pfnDstcMft1Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) + stcDstcInternData.pfnDstcMft1Wfg54Callback = pstcConfig->pfnDstcMft1Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) + stcDstcInternData.pfnDstcMft2Frt0PeakCallback = pstcConfig->pfnDstcMft2Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) + stcDstcInternData.pfnDstcMft2Frt0ZeroCallback = pstcConfig->pfnDstcMft2Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) + stcDstcInternData.pfnDstcMft2Frt1PeakCallback = pstcConfig->pfnDstcMft2Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) + stcDstcInternData.pfnDstcMft2Frt1ZeroCallback = pstcConfig->pfnDstcMft2Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + stcDstcInternData.pfnDstcMft2Frt2PeakCallback = pstcConfig->pfnDstcMft2Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + stcDstcInternData.pfnDstcMft2Frt2ZeroCallback = pstcConfig->pfnDstcMft2Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) + stcDstcInternData.pfnDstcMft2Icu0Callback = pstcConfig->pfnDstcMft2Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) + stcDstcInternData.pfnDstcMft2Icu1Callback = pstcConfig->pfnDstcMft2Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) + stcDstcInternData.pfnDstcMft2Icu2Callback = pstcConfig->pfnDstcMft2Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) + stcDstcInternData.pfnDstcMft2Icu3Callback = pstcConfig->pfnDstcMft2Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) + stcDstcInternData.pfnDstcMft2Ocu0Callback = pstcConfig->pfnDstcMft2Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) + stcDstcInternData.pfnDstcMft2Ocu1Callback = pstcConfig->pfnDstcMft2Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) + stcDstcInternData.pfnDstcMft2Ocu2Callback = pstcConfig->pfnDstcMft2Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) + stcDstcInternData.pfnDstcMft2Ocu3Callback = pstcConfig->pfnDstcMft2Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) + stcDstcInternData.pfnDstcMft2Ocu4Callback = pstcConfig->pfnDstcMft2Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) + stcDstcInternData.pfnDstcMft2Ocu5Callback = pstcConfig->pfnDstcMft2Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) + stcDstcInternData.pfnDstcMft2Wfg10Callback = pstcConfig->pfnDstcMft2Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) + stcDstcInternData.pfnDstcMft2Wfg32Callback = pstcConfig->pfnDstcMft2Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) + stcDstcInternData.pfnDstcMft2Wfg54Callback = pstcConfig->pfnDstcMft2Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + stcDstcInternData.pfnDstcPpg0Callback = pstcConfig->pfnDstcPpg0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + stcDstcInternData.pfnDstcPpg2Callback = pstcConfig->pfnDstcPpg2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + stcDstcInternData.pfnDstcPpg4Callback = pstcConfig->pfnDstcPpg4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG8) + stcDstcInternData.pfnDstcPpg8Callback = pstcConfig->pfnDstcPpg8Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG10) + stcDstcInternData.pfnDstcPpg10Callback = pstcConfig->pfnDstcPpg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG12) + stcDstcInternData.pfnDstcPpg12Callback = pstcConfig->pfnDstcPpg12Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG16) + stcDstcInternData.pfnDstcPpg16Callback = pstcConfig->pfnDstcPpg16Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG18) + stcDstcInternData.pfnDstcPpg18Callback = pstcConfig->pfnDstcPpg18Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG20) + stcDstcInternData.pfnDstcPpg20Callback = pstcConfig->pfnDstcPpg20Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + stcDstcInternData.pfnDstcQprc0CountInversionCallback = pstcConfig->pfnDstcQprc0CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + stcDstcInternData.pfnDstcQprc0OutOfRangeCallback = pstcConfig->pfnDstcQprc0OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + stcDstcInternData.pfnDstcQprc0PcMatchCallback = pstcConfig->pfnDstcQprc0PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + stcDstcInternData.pfnDstcQprc0PcMatchRcMatchCallback = pstcConfig->pfnDstcQprc0PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + stcDstcInternData.pfnDstcQprc0PcRcMatchCallback = pstcConfig->pfnDstcQprc0PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + stcDstcInternData.pfnDstcQprc0UflOflZCallback = pstcConfig->pfnDstcQprc0UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION) + stcDstcInternData.pfnDstcQprc1CountInversionCallback = pstcConfig->pfnDstcQprc1CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE) + stcDstcInternData.pfnDstcQprc1OutOfRangeCallback = pstcConfig->pfnDstcQprc1OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH) + stcDstcInternData.pfnDstcQprc1PcMatchCallback = pstcConfig->pfnDstcQprc1PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH) + stcDstcInternData.pfnDstcQprc1PcMatchRcMatchCallback = pstcConfig->pfnDstcQprc1PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH) + stcDstcInternData.pfnDstcQprc1PcRcMatchCallback = pstcConfig->pfnDstcQprc1PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z) + stcDstcInternData.pfnDstcQprc1UflOflZCallback = pstcConfig->pfnDstcQprc1UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION) + stcDstcInternData.pfnDstcQprc2CountInversionCallback = pstcConfig->pfnDstcQprc2CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE) + stcDstcInternData.pfnDstcQprc2OutOfRangeCallback = pstcConfig->pfnDstcQprc2OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH) + stcDstcInternData.pfnDstcQprc2PcMatchCallback = pstcConfig->pfnDstcQprc2PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH) + stcDstcInternData.pfnDstcQprc2PcMatchRcMatchCallback = pstcConfig->pfnDstcQprc2PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH) + stcDstcInternData.pfnDstcQprc2PcRcMatchCallback = pstcConfig->pfnDstcQprc2PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z) + stcDstcInternData.pfnDstcQprc2UflOflZCallback = pstcConfig->pfnDstcQprc2UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_COUNT_INVERSION) + stcDstcInternData.pfnDstcQprc3CountInversionCallback = pstcConfig->pfnDstcQprc3CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_OUT_OF_RANGE) + stcDstcInternData.pfnDstcQprc3OutOfRangeCallback = pstcConfig->pfnDstcQprc3OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_MATCH) + stcDstcInternData.pfnDstcQprc3PcMatchCallback = pstcConfig->pfnDstcQprc3PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_MATCH_RC_MATCH) + stcDstcInternData.pfnDstcQprc3PcMatchRcMatchCallback = pstcConfig->pfnDstcQprc3PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_RC_MATCH) + stcDstcInternData.pfnDstcQprc3PcRcMatchCallback = pstcConfig->pfnDstcQprc3PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_UFL_OFL_Z) + stcDstcInternData.pfnDstcQprc3UflOflZCallback = pstcConfig->pfnDstcQprc3UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP1) + stcDstcInternData.pfnDstcUsb0Ep1Callback = pstcConfig->pfnDstcUsb0Ep1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP2) + stcDstcInternData.pfnDstcUsb0Ep2Callback = pstcConfig->pfnDstcUsb0Ep2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP3) + stcDstcInternData.pfnDstcUsb0Ep3Callback = pstcConfig->pfnDstcUsb0Ep3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP4) + stcDstcInternData.pfnDstcUsb0Ep4Callback = pstcConfig->pfnDstcUsb0Ep4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP5) + stcDstcInternData.pfnDstcUsb0Ep5Callback = pstcConfig->pfnDstcUsb0Ep5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP1) + stcDstcInternData.pfnDstcUsb1Ep1Callback = pstcConfig->pfnDstcUsb1Ep1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP2) + stcDstcInternData.pfnDstcUsb1Ep2Callback = pstcConfig->pfnDstcUsb1Ep2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP3) + stcDstcInternData.pfnDstcUsb1Ep3Callback = pstcConfig->pfnDstcUsb1Ep3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP4) + stcDstcInternData.pfnDstcUsb1Ep4Callback = pstcConfig->pfnDstcUsb1Ep4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP5) + stcDstcInternData.pfnDstcUsb1Ep5Callback = pstcConfig->pfnDstcUsb1Ep5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_WC) + stcDstcInternData.pfnDstcWcCallback = pstcConfig->pfnDstcWcCallback; +#endif + + if ((NULL != pstcConfig->pfnNotifySwCallback) || + (NULL != pstcConfig->pfnErrorCallback)) + { + if (TRUE == pstcConfig->bTouchNvic) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(DSTC_IRQn); + NVIC_EnableIRQ(DSTC_IRQn); + NVIC_SetPriority(DSTC_IRQn, PDL_IRQ_LEVEL_DSTC); + #elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(DSTC_IRQn); + NVIC_EnableIRQ(DSTC_IRQn); + NVIC_SetPriority(DSTC_IRQn, PDL_IRQ_LEVEL_DSTC); + #else + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_EnableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_IRQ_LEVEL_PPG00_02_20_DSTC_SMCIF0_HDMICEC0); + #endif + #else + #endif + } + } + + FM_DSTC->DESTP = (pstcConfig->u32Destp); + + stcCfg.SWINTE = (TRUE == (pstcConfig->bSwInterruptEnable)) ? 1u : 0u; + stcCfg.ERINTE = (TRUE == (pstcConfig->bErInterruptEnable)) ? 1u : 0u; + stcCfg.RBDIS = (TRUE == (pstcConfig->bReadSkipBufferDisable)) ? 1u : 0u; + stcCfg.ESTE = (TRUE == (pstcConfig->bErrorStopEnable)) ? 1u : 0u; + + switch (pstcConfig->enSwTransferPriority) + { + case PriorityHighest: + stcCfg.SWPR = 0u; + break; + case Priority1_2: + stcCfg.SWPR = 1u; + break; + case Priority1_3: + stcCfg.SWPR = 2u; + break; + case Priority1_7: + stcCfg.SWPR = 3u; + break; + case Priority1_15: + stcCfg.SWPR = 4u; + break; + case Priority1_31: + stcCfg.SWPR = 5u; + break; + case Priority1_63: + stcCfg.SWPR = 6u; + break; + case PriorityLowest: + stcCfg.SWPR = 7u; + break; + default: + return ErrorInvalidParameter; + } + + // Update Hardware + FM_DSTC->CFG_f = stcCfg; + + return Ok; +} // Dsct_Init + +/** + ****************************************************************************** + ** \brief De-Initializes the the DSTC + ** + ** \retval Ok DSTC de-initialized and in standby mode + ******************************************************************************/ +en_result_t Dstc_DeInit(boolean_t bTouchNvic) +{ + if (TRUE == bTouchNvic) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(DSTC_IRQn); + NVIC_DisableIRQ(DSTC_IRQn); + NVIC_SetPriority(DSTC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(DSTC_IRQn); + NVIC_DisableIRQ(DSTC_IRQn); + NVIC_SetPriority(DSTC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #else + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_DisableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #else + #endif + } + + stcDstcInternData.pfnNotifySwCallback = NULL; + stcDstcInternData.pfnErrorCallback = NULL; + + Dstc_SetCommand(CmdStandyTransition); // Switch to standy mode + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Initializes a DSTC channel + ** + ** \param [in] u8Channel DSTC Channel to be initialized + ** \param [in] u16HwDesp Offset to Channel Configuration + ** + ** \retval Ok DSTC Initialized + ** \retval ErrorInvalidParameter DES Address > 16K Bytes + ** \retval ErrorAddressAlignment DES Address not aligned to 32 Bit + ******************************************************************************/ +en_result_t Dstc_SetHwdesp( uint8_t u8Channel, + uint16_t u16HwDesp ) +{ + if (u16HwDesp >= 0x4000u) + { + return ErrorInvalidParameter; + } + + if (0u != (u16HwDesp & 0x0003u)) + { + return ErrorAddressAlignment; + } + + // 32-Bit access to HWDESP + FM_DSTC->HWDESP = (uint32_t)u8Channel | (uint32_t)(u16HwDesp << 16u); + + return Ok; +} // Dsct_ChannelInit + +/** + ****************************************************************************** + ** \brief Read the HWDESP Address Offset of a Channel + ** + ** \param [in] u8Channel DSTC Channel to be initialized + ** + ** \return uint16_t Current HWDESP DES Offset + ******************************************************************************/ +uint16_t Dstc_ReadHwdesp( uint8_t u8Channel ) +{ + FM_DSTC->HWDESP_f.CHANNEL = u8Channel; + + return (uint16_t)(0x0000FFFFul & FM_DSTC->HWDESP_f.HWDESP); +} // Dstc_ReadHwdesp + +/** + ****************************************************************************** + ** \brief Set a Command to CMD Register + ** + ** \param [in] enCommand Command of type of #en_dstc_cmd_t + ** + ** \retval Ok Command Set + ** \retval ErrorInvalidParameter Wrong Command Enumerator used + ******************************************************************************/ +en_result_t Dstc_SetCommand( en_dstc_cmd_t enCommand ) +{ + switch (enCommand) + { + case CmdStandyRelease: + FM_DSTC->CMD = 0x04u; + break; + case CmdStandyTransition: + FM_DSTC->CMD = 0x08u; + break; + case CmdSwclr: + FM_DSTC->CMD = 0x10u; + break; + case CmdErclr: + FM_DSTC->CMD = 0x20u; + break; + case CmdRbclr: + FM_DSTC->CMD = 0x40u; + break; + case CmdMkclr: + FM_DSTC->CMD = 0x80u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} // Dstc_SetCommand + +/** + ****************************************************************************** + ** \brief Set SWDESP offset and trigger SW transfer + ** + ** \param [in] u16SwDesPointer Address offset to DES + ** + ** \retval Ok SWDESP set + ** \retval ErrorInvalidParameter Offset > 16K Bytes + ** \retval ErrorAddressAlignment Offset not 32-bit aligned + ******************************************************************************/ +en_result_t Dstc_SwTrigger( uint16_t u16SwDesPointer ) +{ + if (u16SwDesPointer >= 0x4000u) + { + return ErrorInvalidParameter; + } + + if (0u != (u16SwDesPointer & 0x0003u)) + { + return ErrorAddressAlignment; + } + + FM_DSTC->SWTR_f.SWDESP = (0x3FFFu & u16SwDesPointer); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Check Software Trigger Start State + ** + ** \retval Ok SW Transfer ended + ** \retval OperationInProgress SW Transfer pending + ******************************************************************************/ +en_result_t Dstc_SwTrqansferStartStatus( void ) +{ + if (TRUE == FM_DSTC->SWTR_f.SWREQ) + { + return Ok; + } + + return OperationInProgress; +} + +/** + ****************************************************************************** + ** \brief Set DREQENB Register + ** + ** \param [in] pstcDreqenb Pointer to DREQENB Structure + ** + ** \retval Ok DREQENB setting successful + ******************************************************************************/ +en_result_t Dstc_SetDreqenb( stc_dstc_dreqenb_t* pstcDreqenb ) +{ + FM_DSTC->DREQENB0 = pstcDreqenb->u32Dreqenb0; + FM_DSTC->DREQENB1 = pstcDreqenb->u32Dreqenb1; +#if(defined(FM_DSTC_DREQENB2)) + FM_DSTC->DREQENB2 = pstcDreqenb->u32Dreqenb2; + FM_DSTC->DREQENB3 = pstcDreqenb->u32Dreqenb3; +#if(defined(FM_DSTC_DREQENB4)) + FM_DSTC->DREQENB4 = pstcDreqenb->u32Dreqenb4; + FM_DSTC->DREQENB5 = pstcDreqenb->u32Dreqenb5; + FM_DSTC->DREQENB6 = pstcDreqenb->u32Dreqenb6; + FM_DSTC->DREQENB7 = pstcDreqenb->u32Dreqenb7; +#endif +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read DREQENB Register + ** + ** \param [out] pstcDreqenb Pointer to DREQENB Structure + ** + ** \retval Ok DREQENB read-out successful + ******************************************************************************/ +en_result_t Dstc_ReadDreqenb( stc_dstc_dreqenb_t* pstcDreqenb ) +{ + pstcDreqenb->u32Dreqenb0 = FM_DSTC->DREQENB0; + pstcDreqenb->u32Dreqenb1 = FM_DSTC->DREQENB1; +#if(defined(FM_DSTC_DREQENB2)) + pstcDreqenb->u32Dreqenb2 = FM_DSTC->DREQENB2; + pstcDreqenb->u32Dreqenb3 = FM_DSTC->DREQENB3; +#if(defined(FM_DSTC_DREQENB4)) + pstcDreqenb->u32Dreqenb4 = FM_DSTC->DREQENB4; + pstcDreqenb->u32Dreqenb5 = FM_DSTC->DREQENB5; + pstcDreqenb->u32Dreqenb6 = FM_DSTC->DREQENB6; + pstcDreqenb->u32Dreqenb7 = FM_DSTC->DREQENB7; +#endif +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set DREQENB Register Bit + ** + ** \param [in] u8BitPos Bit Position (IRQ Number) + ** + ** \retval Ok DREQENB Bit set successfully + ******************************************************************************/ +en_result_t Dstc_SetDreqenbBit( uint8_t u8BitPos ) +{ + uint8_t u8BitPosValue = (u8BitPos % 32u); + uint32_t u32BitPosRelative = (1ul << u8BitPosValue); + uint8_t u8WordPos = (u8BitPos / 32u); + + *(uint32_t*)(uint32_t)(((uint32_t)(&FM_DSTC->DREQENB0)) + ((4ul * (uint32_t)u8WordPos))) |= u32BitPosRelative; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Clear DREQENB Register Bit + ** + ** \param [in] u8BitPos Bit Position (IRQ Number) + ** + ** \retval Ok DREQENB Bit set successfully + ******************************************************************************/ +en_result_t Dstc_ClearDreqenbBit( uint8_t u8BitPos ) +{ + uint8_t u8BitPosValue = (u8BitPos % 32u); + uint32_t u32BitPosRelative = (1ul << u8BitPosValue); + uint8_t u8WordPos = (u8BitPos / 32u); + + *(uint32_t*)(uint32_t)(((uint32_t)(&FM_DSTC->DREQENB0)) + ((4ul * (uint32_t)u8WordPos))) |= u32BitPosRelative; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read HWINT Register + ** + ** \param [out] pstcHwint Pointer to HWINT Structure + ** + ** \retval Ok HWINT read-out successful + ******************************************************************************/ +en_result_t Dstc_ReadHwint( stc_dstc_hwint_t* pstcHwint ) +{ + pstcHwint->u32Hwint0 = FM_DSTC->HWINT0; + pstcHwint->u32Hwint1 = FM_DSTC->HWINT1; +#if(defined(FM_DSTC_HWINT2)) + pstcHwint->u32Hwint2 = FM_DSTC->HWINT2; + pstcHwint->u32Hwint3 = FM_DSTC->HWINT3; +#if(defined(FM_DSTC_HWINT4)) + pstcHwint->u32Hwint4 = FM_DSTC->HWINT4; + pstcHwint->u32Hwint5 = FM_DSTC->HWINT5; + pstcHwint->u32Hwint6 = FM_DSTC->HWINT6; + pstcHwint->u32Hwint7 = FM_DSTC->HWINT7; +#endif +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set HWINTCLR Register + ** + ** \param [in] pstcHwintclr Pointer to HWINTCLR Structure + ** + ** \retval Ok HWINTCLR setting successful + ******************************************************************************/ +en_result_t Dstc_SetHwintclr( stc_dstc_hwintclr_t* pstcHwintclr ) +{ + FM_DSTC->HWINTCLR0 = pstcHwintclr->u32Hwintclr0; + FM_DSTC->HWINTCLR1 = pstcHwintclr->u32Hwintclr1; +#if(defined(FM_DSTC_HWINT2)) + FM_DSTC->HWINTCLR2 = pstcHwintclr->u32Hwintclr2; + FM_DSTC->HWINTCLR3 = pstcHwintclr->u32Hwintclr3; +#if(defined(FM_DSTC_HWINT4)) + FM_DSTC->HWINTCLR4 = pstcHwintclr->u32Hwintclr4; + FM_DSTC->HWINTCLR5 = pstcHwintclr->u32Hwintclr5; + FM_DSTC->HWINTCLR6 = pstcHwintclr->u32Hwintclr6; + FM_DSTC->HWINTCLR7 = pstcHwintclr->u32Hwintclr7; +#endif +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read HWINT Register Bit + ** + ** \param [in] u8BitPos Bit Position (IRQ Number) + ** + ** \retval TRUE HWINT bit set + ** \retval FALSE HWINT bit not set + ******************************************************************************/ +boolean_t Dstc_ReadHwintBit( uint8_t u8BitPos ) +{ + uint8_t u8BitPosValue = (u8BitPos % 32u); + uint32_t u32BitPosRelative = (1ul << u8BitPosValue); + uint8_t u8WordPos = (u8BitPos / 32u); + + if(((*(uint32_t*)(uint32_t)(((uint32_t)(&FM_DSTC->HWINT0)) + ((4ul * (uint32_t)u8WordPos)))) & u32BitPosRelative) == u32BitPosRelative) + { + return TRUE; + } + + return FALSE; +} + +/** + ****************************************************************************** + ** \brief Set HWINTCLR Register Bit + ** + ** \param [in] u8BitPos Bit Position (IRQ Number) + ** + ** \retval Ok HWINTCLR Bit set successfully + ******************************************************************************/ +en_result_t Dstc_SetHwintclrBit( uint8_t u8BitPos ) +{ + uint8_t u8BitPosValue = (u8BitPos % 32u); + uint32_t u32BitPosRelative = (1ul << u8BitPosValue); + uint8_t u8WordPos = (u8BitPos / 32u); + + *(uint32_t*)(uint32_t)(((uint32_t)(&FM_DSTC->HWINTCLR0)) + ((4ul * (uint32_t)u8WordPos))) = u32BitPosRelative; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read DQMSK Register + ** + ** \param [out] pstcDqmsk Pointer to DQMSK Structure + ** + ** \retval Ok HWINT read-out successful + ******************************************************************************/ +en_result_t Dstc_ReadDqmsk( stc_dstc_dqmsk_t* pstcDqmsk ) +{ + pstcDqmsk->u32Dqmsk0 = FM_DSTC->DQMSK0; + pstcDqmsk->u32Dqmsk1 = FM_DSTC->DQMSK1; +#if(defined(FM_DSTC_DQMSK2)) + pstcDqmsk->u32Dqmsk2 = FM_DSTC->DQMSK2; + pstcDqmsk->u32Dqmsk3 = FM_DSTC->DQMSK3; +#if(defined(FM_DSTC_DQMSK4)) + pstcDqmsk->u32Dqmsk4 = FM_DSTC->DQMSK4; + pstcDqmsk->u32Dqmsk5 = FM_DSTC->DQMSK5; + pstcDqmsk->u32Dqmsk6 = FM_DSTC->DQMSK6; + pstcDqmsk->u32Dqmsk7 = FM_DSTC->DQMSK7; +#endif +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set DQMSKCLR Register + ** + ** \param [in] pstcDqmskclr Pointer to DQMSKCLR Structure + ** + ** \retval Ok DQMSKCLR setting successful + ******************************************************************************/ +en_result_t Dstc_SetDqmskclr( stc_dstc_dqmskclr_t* pstcDqmskclr ) +{ + FM_DSTC->DQMSKCLR0 = pstcDqmskclr->u32Dqmskclr0; + FM_DSTC->DQMSKCLR1 = pstcDqmskclr->u32Dqmskclr1; +#if(defined(FM_DSTC_DQMSK2)) + FM_DSTC->DQMSKCLR2 = pstcDqmskclr->u32Dqmskclr2; + FM_DSTC->DQMSKCLR3 = pstcDqmskclr->u32Dqmskclr3; +#if(defined(FM_DSTC_DQMSK4)) + FM_DSTC->DQMSKCLR4 = pstcDqmskclr->u32Dqmskclr4; + FM_DSTC->DQMSKCLR5 = pstcDqmskclr->u32Dqmskclr5; + FM_DSTC->DQMSKCLR6 = pstcDqmskclr->u32Dqmskclr6; + FM_DSTC->DQMSKCLR7 = pstcDqmskclr->u32Dqmskclr7; +#endif +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set DQMSKCLR Register Bit + ** + ** \param [in] u8BitPos Bit Position (IRQ Number) + ** + ** \retval Ok DQMSKCLR Bit set successfully + ******************************************************************************/ +en_result_t Dstc_SetDqmskclrBit( uint8_t u8BitPos ) +{ + uint8_t u8BitPosValue = (u8BitPos % 32u); + uint32_t u32BitPosRelative = (1ul << u8BitPosValue); + uint8_t u8WordPos = (u8BitPos / 32u); + + *(uint32_t*)(uint32_t)(((uint32_t)(&FM_DSTC->DQMSKCLR0)) + ((4ul * (uint32_t)u8WordPos))) &= (0xFFFFFFFFul ^ u32BitPosRelative); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief DSTC Peripheral Interrupt Service Routines + ******************************************************************************/ +/// ADC +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) || (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) || (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) || (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) +void Dstc_AdcIrqHandler(uint8_t u8IrqChannel0, uint8_t u8IrqChannel1) +{ + func_ptr_t pfnCallback; + + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + switch (u8IrqChannel0) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + case DSTC_IRQ_NUMBER_ADC0_PRIO: + pfnCallback = stcDstcInternData.pfnDstcAdc0PrioCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + case DSTC_IRQ_NUMBER_ADC1_PRIO: + pfnCallback = stcDstcInternData.pfnDstcAdc1PrioCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + case DSTC_IRQ_NUMBER_ADC2_PRIO: + pfnCallback = stcDstcInternData.pfnDstcAdc2PrioCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel0)) + { + Dstc_SetHwintclrBit(u8IrqChannel0); + + if (pfnCallback != NULL) + { + pfnCallback(); + } + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) + switch (u8IrqChannel1) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) + case DSTC_IRQ_NUMBER_ADC0_SCAN: + pfnCallback = stcDstcInternData.pfnDstcAdc0ScanCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) + case DSTC_IRQ_NUMBER_ADC1_SCAN: + pfnCallback = stcDstcInternData.pfnDstcAdc1ScanCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) + case DSTC_IRQ_NUMBER_ADC2_SCAN: + pfnCallback = stcDstcInternData.pfnDstcAdc2ScanCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel1)) + { + Dstc_SetHwintclrBit(u8IrqChannel1); + + if (pfnCallback != NULL) + { + pfnCallback(); + } + } + #endif +} +#endif + +/// BT +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) +void Dstc_BtIrqHandler(uint8_t u8IrqChannel0, uint8_t u8IrqChannel1) +{ + func_ptr_t pfnCallback; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) + switch (u8IrqChannel0) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + case DSTC_IRQ_NUMBER_BT0_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt0Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + case DSTC_IRQ_NUMBER_BT1_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt1Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + case DSTC_IRQ_NUMBER_BT2_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt2Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + case DSTC_IRQ_NUMBER_BT3_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt3Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + case DSTC_IRQ_NUMBER_BT4_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt4Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + case DSTC_IRQ_NUMBER_BT5_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt5Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + case DSTC_IRQ_NUMBER_BT6_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt6Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + case DSTC_IRQ_NUMBER_BT7_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt7Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) + case DSTC_IRQ_NUMBER_BT8_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt8Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) + case DSTC_IRQ_NUMBER_BT9_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt9Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) + case DSTC_IRQ_NUMBER_BT10_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt10Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) + case DSTC_IRQ_NUMBER_BT11_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt11Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) + case DSTC_IRQ_NUMBER_BT12_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt12Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) + case DSTC_IRQ_NUMBER_BT13_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt13Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) + case DSTC_IRQ_NUMBER_BT14_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt14Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ0) + case DSTC_IRQ_NUMBER_BT15_IRQ0: + pfnCallback = stcDstcInternData.pfnDstcBt15Irq0Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel0)) + { + Dstc_SetHwintclrBit(u8IrqChannel0); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) + switch (u8IrqChannel1) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) + case DSTC_IRQ_NUMBER_BT0_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt0Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) + case DSTC_IRQ_NUMBER_BT1_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt1Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) + case DSTC_IRQ_NUMBER_BT2_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt2Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) + case DSTC_IRQ_NUMBER_BT3_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt3Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) + case DSTC_IRQ_NUMBER_BT4_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt4Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) + case DSTC_IRQ_NUMBER_BT5_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt5Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) + case DSTC_IRQ_NUMBER_BT6_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt6Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) + case DSTC_IRQ_NUMBER_BT7_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt7Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) + case DSTC_IRQ_NUMBER_BT8_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt8Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) + case DSTC_IRQ_NUMBER_BT9_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt9Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) + case DSTC_IRQ_NUMBER_BT10_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt11Irq0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) + case DSTC_IRQ_NUMBER_BT11_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt11Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) + case DSTC_IRQ_NUMBER_BT12_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt12Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) + case DSTC_IRQ_NUMBER_BT13_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt13Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) + case DSTC_IRQ_NUMBER_BT14_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt14Irq1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ1) + case DSTC_IRQ_NUMBER_BT15_IRQ1: + pfnCallback = stcDstcInternData.pfnDstcBt15Irq1Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel0)) + { + Dstc_SetHwintclrBit(u8IrqChannel0); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } + #endif +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_BTn_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BTn_IRQ1) ... + +/// CAN-FD +#if (PDL_ON == PDL_DSTC_ENABLE_CANFD) +void Dstc_CanfdIrqHandler(uint8_t u8IrqChannel0) +{ + func_ptr_t pfnCallback = NULL; + + pfnCallback = stcDstcInternData.pfnDstcCanfdCallback; + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel0)) + { + Dstc_SetHwintclrBit(u8IrqChannel0); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif + +/// EXT INT +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) || (PDL_ON == PDL_DSTC_ENABLE_EXINT1) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT2) || (PDL_ON == PDL_DSTC_ENABLE_EXINT3) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT4) || (PDL_ON == PDL_DSTC_ENABLE_EXINT5) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT6) || (PDL_ON == PDL_DSTC_ENABLE_EXINT7) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT8) || (PDL_ON == PDL_DSTC_ENABLE_EXINT9) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT10) || (PDL_ON == PDL_DSTC_ENABLE_EXINT11) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT12) || (PDL_ON == PDL_DSTC_ENABLE_EXINT13) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT14) || (PDL_ON == PDL_DSTC_ENABLE_EXINT15) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT16) || (PDL_ON == PDL_DSTC_ENABLE_EXINT17) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT18) || (PDL_ON == PDL_DSTC_ENABLE_EXINT19) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT20) || (PDL_ON == PDL_DSTC_ENABLE_EXINT21) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT22) || (PDL_ON == PDL_DSTC_ENABLE_EXINT23) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT24) || (PDL_ON == PDL_DSTC_ENABLE_EXINT25) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT26) || (PDL_ON == PDL_DSTC_ENABLE_EXINT27) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT28) || (PDL_ON == PDL_DSTC_ENABLE_EXINT29) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT30) || (PDL_ON == PDL_DSTC_ENABLE_EXINT31) +void Dstc_ExintIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + case DSTC_IRQ_NUMBER_EXINT0: + pfnCallback = stcDstcInternData.pfnDstcExint0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + case DSTC_IRQ_NUMBER_EXINT1: + pfnCallback = stcDstcInternData.pfnDstcExint1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + case DSTC_IRQ_NUMBER_EXINT2: + pfnCallback = stcDstcInternData.pfnDstcExint2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + case DSTC_IRQ_NUMBER_EXINT3: + pfnCallback = stcDstcInternData.pfnDstcExint3Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + case DSTC_IRQ_NUMBER_EXINT4: + pfnCallback = stcDstcInternData.pfnDstcExint4Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + case DSTC_IRQ_NUMBER_EXINT5: + pfnCallback = stcDstcInternData.pfnDstcExint5Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + case DSTC_IRQ_NUMBER_EXINT6: + pfnCallback = stcDstcInternData.pfnDstcExint6Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + case DSTC_IRQ_NUMBER_EXINT7: + pfnCallback = stcDstcInternData.pfnDstcExint7Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + case DSTC_IRQ_NUMBER_EXINT8: + pfnCallback = stcDstcInternData.pfnDstcExint8Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + case DSTC_IRQ_NUMBER_EXINT9: + pfnCallback = stcDstcInternData.pfnDstcExint9Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + case DSTC_IRQ_NUMBER_EXINT10: + pfnCallback = stcDstcInternData.pfnDstcExint10Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + case DSTC_IRQ_NUMBER_EXINT11: + pfnCallback = stcDstcInternData.pfnDstcExint11Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + case DSTC_IRQ_NUMBER_EXINT12: + pfnCallback = stcDstcInternData.pfnDstcExint12Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + case DSTC_IRQ_NUMBER_EXINT13: + pfnCallback = stcDstcInternData.pfnDstcExint13Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + case DSTC_IRQ_NUMBER_EXINT14: + pfnCallback = stcDstcInternData.pfnDstcExint14Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + case DSTC_IRQ_NUMBER_EXINT15: + pfnCallback = stcDstcInternData.pfnDstcExint15Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT16) + case DSTC_IRQ_NUMBER_EXINT16: + pfnCallback = stcDstcInternData.pfnDstcExint16Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT17) + case DSTC_IRQ_NUMBER_EXINT17: + pfnCallback = stcDstcInternData.pfnDstcExint17Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT18) + case DSTC_IRQ_NUMBER_EXINT18: + pfnCallback = stcDstcInternData.pfnDstcExint18Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT19) + case DSTC_IRQ_NUMBER_EXINT19: + pfnCallback = stcDstcInternData.pfnDstcExint19Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT20) + case DSTC_IRQ_NUMBER_EXINT20: + pfnCallback = stcDstcInternData.pfnDstcExint20Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT21) + case DSTC_IRQ_NUMBER_EXINT21: + pfnCallback = stcDstcInternData.pfnDstcExint21Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT22) + case DSTC_IRQ_NUMBER_EXINT22: + pfnCallback = stcDstcInternData.pfnDstcExint22Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT23) + case DSTC_IRQ_NUMBER_EXINT23: + pfnCallback = stcDstcInternData.pfnDstcExint23Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT24) + case DSTC_IRQ_NUMBER_EXINT24: + pfnCallback = stcDstcInternData.pfnDstcExint24Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT25) + case DSTC_IRQ_NUMBER_EXINT25: + pfnCallback = stcDstcInternData.pfnDstcExint25Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT26) + case DSTC_IRQ_NUMBER_EXINT26: + pfnCallback = stcDstcInternData.pfnDstcExint26Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT27) + case DSTC_IRQ_NUMBER_EXINT27: + pfnCallback = stcDstcInternData.pfnDstcExint27Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT28) + case DSTC_IRQ_NUMBER_EXINT28: + pfnCallback = stcDstcInternData.pfnDstcExint28Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT29) + case DSTC_IRQ_NUMBER_EXINT29: + pfnCallback = stcDstcInternData.pfnDstcExint29Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT30) + case DSTC_IRQ_NUMBER_EXINT30: + pfnCallback = stcDstcInternData.pfnDstcExint30Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT31) + case DSTC_IRQ_NUMBER_EXINT31: + pfnCallback = stcDstcInternData.pfnDstcExint31Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_EXINTn) || ... + +#if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) || (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_RX) +void Dstc_HsspiIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) + case DSTC_IRQ_NUMBER_HSSPI0_TX: + pfnCallback = stcDstcInternData.pfnDstcHsspi0TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_RX) + case DSTC_IRQ_NUMBER_HSSPI0_RX: + pfnCallback = stcDstcInternData.pfnDstcHsspi0RxCallback; + break; + #endif + default: + pfnCallback = NULL; + break; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) ... + +#if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_TX) || (PDL_ON == PDL_DSTC_ENABLE_I2CS0_RX) +/// I2C SLAVE +void Dstc_I2csIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_TX) + case DSTC_IRQ_NUMBER_I2CS0_TX: + pfnCallback = stcDstcInternData.pfnDstcI2cs0TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_RX) + case DSTC_IRQ_NUMBER_I2CS0_RX: + pfnCallback = stcDstcInternData.pfnDstcI2cs0RxCallback; + break; + #endif + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX) || (PDL_ON == PDL_DSTC_ENABLE_I2S0_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_I2S1_TX) || (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) +void Dstc_I2sIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX) + case DSTC_IRQ_NUMBER_I2S0_TX: + pfnCallback = stcDstcInternData.pfnDstcI2s0TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_I2S0_RX) + case DSTC_IRQ_NUMBER_I2S0_RX: + pfnCallback = stcDstcInternData.pfnDstcI2s0RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_I2S1_TX) + case DSTC_IRQ_NUMBER_I2S1_TX: + pfnCallback = stcDstcInternData.pfnDstcI2s1TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) + case DSTC_IRQ_NUMBER_I2S1_RX: + pfnCallback = stcDstcInternData.pfnDstcI2s1RxCallback; + break; + #endif + default: + pfnCallback = NULL; + break; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX)... + +/// MFS +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) +extern void Dstc_MfsRxIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + case DSTC_IRQ_NUMBER_MFS0_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs0RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + case DSTC_IRQ_NUMBER_MFS1_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs1RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + case DSTC_IRQ_NUMBER_MFS2_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs2RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + case DSTC_IRQ_NUMBER_MFS3_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs3RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + case DSTC_IRQ_NUMBER_MFS4_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs4RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + case DSTC_IRQ_NUMBER_MFS5_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs5RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + case DSTC_IRQ_NUMBER_MFS6_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs6RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + case DSTC_IRQ_NUMBER_MFS7_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs7RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) + case DSTC_IRQ_NUMBER_MFS8_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs8RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) + case DSTC_IRQ_NUMBER_MFS9_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs9RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) + case DSTC_IRQ_NUMBER_MFS10_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs10RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) + case DSTC_IRQ_NUMBER_MFS11_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs11RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) + case DSTC_IRQ_NUMBER_MFS12_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs12RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) + case DSTC_IRQ_NUMBER_MFS13_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs13RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) + case DSTC_IRQ_NUMBER_MFS14_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs14RxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) + case DSTC_IRQ_NUMBER_MFS15_RX: + pfnCallback = stcDstcInternData.pfnDstcMfs15RxCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) || ... + +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) +void Dstc_MfsTxIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + case DSTC_IRQ_NUMBER_MFS0_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs0TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + case DSTC_IRQ_NUMBER_MFS1_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs1TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + case DSTC_IRQ_NUMBER_MFS2_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs2TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + case DSTC_IRQ_NUMBER_MFS3_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs3TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + case DSTC_IRQ_NUMBER_MFS4_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs4TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + case DSTC_IRQ_NUMBER_MFS5_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs5TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + case DSTC_IRQ_NUMBER_MFS6_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs6TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + case DSTC_IRQ_NUMBER_MFS7_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs7TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) + case DSTC_IRQ_NUMBER_MFS8_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs8TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) + case DSTC_IRQ_NUMBER_MFS9_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs9TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) + case DSTC_IRQ_NUMBER_MFS10_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs10TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) + case DSTC_IRQ_NUMBER_MFS11_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs11TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) + case DSTC_IRQ_NUMBER_MFS12_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs12TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) + case DSTC_IRQ_NUMBER_MFS13_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs13TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) + case DSTC_IRQ_NUMBER_MFS14_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs14TxCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) + case DSTC_IRQ_NUMBER_MFS15_TX: + pfnCallback = stcDstcInternData.pfnDstcMfs15TxCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) || ... + +/// MFT FRT +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) +void Dstc_MftFrtPeakIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + case DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft0Frt0PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + case DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft0Frt1PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + case DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft0Frt2PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) + case DSTC_IRQ_NUMBER_MFT1_FRT0_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft1Frt0PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) + case DSTC_IRQ_NUMBER_MFT1_FRT1_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft1Frt1PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + case DSTC_IRQ_NUMBER_MFT1_FRT2_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft1Frt2PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) + case DSTC_IRQ_NUMBER_MFT2_FRT0_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft2Frt0PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) + case DSTC_IRQ_NUMBER_MFT2_FRT1_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft2Frt1PeakCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + case DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK: + pfnCallback = stcDstcInternData.pfnDstcMft2Frt2PeakCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) || (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) || ... + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) +void Dstc_MftFrtZeroIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + case DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft0Frt0ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + case DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft0Frt1ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + case DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft0Frt2ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) + case DSTC_IRQ_NUMBER_MFT1_FRT0_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft1Frt0ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) + case DSTC_IRQ_NUMBER_MFT1_FRT1_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft1Frt1ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + case DSTC_IRQ_NUMBER_MFT1_FRT2_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft1Frt2ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) + case DSTC_IRQ_NUMBER_MFT2_FRT0_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft2Frt0ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) + case DSTC_IRQ_NUMBER_MFT2_FRT1_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft2Frt1ZeroCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + case DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO: + pfnCallback = stcDstcInternData.pfnDstcMft2Frt2ZeroCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) || (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) || ... + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) +void Dstc_MftOcuIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + case DSTC_IRQ_NUMBER_MFT0_OCU0: + pfnCallback = stcDstcInternData.pfnDstcMft0Ocu0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + case DSTC_IRQ_NUMBER_MFT0_OCU1: + pfnCallback = stcDstcInternData.pfnDstcMft0Ocu1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + case DSTC_IRQ_NUMBER_MFT0_OCU2: + pfnCallback = stcDstcInternData.pfnDstcMft0Ocu2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + case DSTC_IRQ_NUMBER_MFT0_OCU3: + pfnCallback = stcDstcInternData.pfnDstcMft0Ocu3Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + case DSTC_IRQ_NUMBER_MFT0_OCU4: + pfnCallback = stcDstcInternData.pfnDstcMft0Ocu4Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + case DSTC_IRQ_NUMBER_MFT0_OCU5: + pfnCallback = stcDstcInternData.pfnDstcMft0Ocu5Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) + case DSTC_IRQ_NUMBER_MFT1_OCU0: + pfnCallback = stcDstcInternData.pfnDstcMft1Ocu0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) + case DSTC_IRQ_NUMBER_MFT1_OCU1: + pfnCallback = stcDstcInternData.pfnDstcMft1Ocu1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) + case DSTC_IRQ_NUMBER_MFT1_OCU2: + pfnCallback = stcDstcInternData.pfnDstcMft1Ocu2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) + case DSTC_IRQ_NUMBER_MFT1_OCU3: + pfnCallback = stcDstcInternData.pfnDstcMft1Ocu3Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) + case DSTC_IRQ_NUMBER_MFT1_OCU4: + pfnCallback = stcDstcInternData.pfnDstcMft1Ocu4Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) + case DSTC_IRQ_NUMBER_MFT1_OCU5: + pfnCallback = stcDstcInternData.pfnDstcMft1Ocu5Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) + case DSTC_IRQ_NUMBER_MFT2_OCU0: + pfnCallback = stcDstcInternData.pfnDstcMft2Ocu0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) + case DSTC_IRQ_NUMBER_MFT2_OCU1: + pfnCallback = stcDstcInternData.pfnDstcMft2Ocu1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) + case DSTC_IRQ_NUMBER_MFT2_OCU2: + pfnCallback = stcDstcInternData.pfnDstcMft2Ocu2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) + case DSTC_IRQ_NUMBER_MFT2_OCU3: + pfnCallback = stcDstcInternData.pfnDstcMft2Ocu3Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) + case DSTC_IRQ_NUMBER_MFT2_OCU4: + pfnCallback = stcDstcInternData.pfnDstcMft2Ocu4Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) + case DSTC_IRQ_NUMBER_MFT2_OCU5: + pfnCallback = stcDstcInternData.pfnDstcMft2Ocu5Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) || ... + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) +void Dstc_MftWfgIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + case DSTC_IRQ_NUMBER_MFT0_WFG10: + pfnCallback = stcDstcInternData.pfnDstcMft0Wfg10Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + case DSTC_IRQ_NUMBER_MFT0_WFG32: + pfnCallback = stcDstcInternData.pfnDstcMft0Wfg32Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + case DSTC_IRQ_NUMBER_MFT0_WFG54: + pfnCallback = stcDstcInternData.pfnDstcMft0Wfg54Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) + case DSTC_IRQ_NUMBER_MFT1_WFG10: + pfnCallback = stcDstcInternData.pfnDstcMft1Wfg10Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) + case DSTC_IRQ_NUMBER_MFT1_WFG32: + pfnCallback = stcDstcInternData.pfnDstcMft1Wfg32Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) + case DSTC_IRQ_NUMBER_MFT1_WFG54: + pfnCallback = stcDstcInternData.pfnDstcMft1Wfg54Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) + case DSTC_IRQ_NUMBER_MFT2_WFG10: + pfnCallback = stcDstcInternData.pfnDstcMft2Wfg10Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) + case DSTC_IRQ_NUMBER_MFT2_WFG32: + pfnCallback = stcDstcInternData.pfnDstcMft2Wfg32Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) + case DSTC_IRQ_NUMBER_MFT2_WFG54: + pfnCallback = stcDstcInternData.pfnDstcMft2Wfg54Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) ... + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) +void Dstc_MftIcuIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + case DSTC_IRQ_NUMBER_MFT0_ICU0: + pfnCallback = stcDstcInternData.pfnDstcMft0Icu0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + case DSTC_IRQ_NUMBER_MFT0_ICU1: + pfnCallback = stcDstcInternData.pfnDstcMft0Icu1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + case DSTC_IRQ_NUMBER_MFT0_ICU2: + pfnCallback = stcDstcInternData.pfnDstcMft0Icu2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + case DSTC_IRQ_NUMBER_MFT0_ICU3: + pfnCallback = stcDstcInternData.pfnDstcMft0Icu3Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) + case DSTC_IRQ_NUMBER_MFT1_ICU0: + pfnCallback = stcDstcInternData.pfnDstcMft1Icu0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) + case DSTC_IRQ_NUMBER_MFT1_ICU1: + pfnCallback = stcDstcInternData.pfnDstcMft1Icu1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) + case DSTC_IRQ_NUMBER_MFT1_ICU2: + pfnCallback = stcDstcInternData.pfnDstcMft1Icu2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) + case DSTC_IRQ_NUMBER_MFT1_ICU3: + pfnCallback = stcDstcInternData.pfnDstcMft1Icu3Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) + case DSTC_IRQ_NUMBER_MFT2_ICU0: + pfnCallback = stcDstcInternData.pfnDstcMft2Icu0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) + case DSTC_IRQ_NUMBER_MFT2_ICU1: + pfnCallback = stcDstcInternData.pfnDstcMft2Icu1Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) + case DSTC_IRQ_NUMBER_MFT2_ICU2: + pfnCallback = stcDstcInternData.pfnDstcMft2Icu2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) + case DSTC_IRQ_NUMBER_MFT2_ICU3: + pfnCallback = stcDstcInternData.pfnDstcMft2Icu3Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) ... + +/// PCRC +#if (PDL_ON == PDL_DSTC_ENABLE_PCRC) +void Dstc_PcrcIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback = NULL; + + pfnCallback = stcDstcInternData.pfnDstcPcrcCallback; + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_PCRC) + + + +/// PPG +#if (PDL_ON == PDL_DSTC_ENABLE_PPG0) || (PDL_ON == PDL_DSTC_ENABLE_PPG2) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG4) || (PDL_ON == PDL_DSTC_ENABLE_PPG8) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG4) || (PDL_ON == PDL_DSTC_ENABLE_PPG8) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG10) || (PDL_ON == PDL_DSTC_ENABLE_PPG12) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG16) || (PDL_ON == PDL_DSTC_ENABLE_PPG18) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG20) +void Dstc_PpgIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + case DSTC_IRQ_NUMBER_PPG0: + pfnCallback = stcDstcInternData.pfnDstcPpg0Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + case DSTC_IRQ_NUMBER_PPG2: + pfnCallback = stcDstcInternData.pfnDstcPpg2Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + case DSTC_IRQ_NUMBER_PPG4: + pfnCallback = stcDstcInternData.pfnDstcPpg4Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG8) + case DSTC_IRQ_NUMBER_PPG8: + pfnCallback = stcDstcInternData.pfnDstcPpg8Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG10) + case DSTC_IRQ_NUMBER_PPG10: + pfnCallback = stcDstcInternData.pfnDstcPpg10Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG12) + case DSTC_IRQ_NUMBER_PPG12: + pfnCallback = stcDstcInternData.pfnDstcPpg12Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG16) + case DSTC_IRQ_NUMBER_PPG16: + pfnCallback = stcDstcInternData.pfnDstcPpg16Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG18) + case DSTC_IRQ_NUMBER_PPG18: + pfnCallback = stcDstcInternData.pfnDstcPpg18Callback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_PPG20) + case DSTC_IRQ_NUMBER_PPG20: + pfnCallback = stcDstcInternData.pfnDstcPpg20Callback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_PPG0) || (PDL_ON == PDL_DSTC_ENABLE_PPG2) ... + +/// QPRC +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z) +void Dstc_QprcIrqHandler(uint8_t u8IrqChannel) +{ + func_ptr_t pfnCallback; + + switch (u8IrqChannel) + { + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + case DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION: + pfnCallback = stcDstcInternData.pfnDstcQprc0CountInversionCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + case DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE: + pfnCallback = stcDstcInternData.pfnDstcQprc0OutOfRangeCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + case DSTC_IRQ_NUMBER_QPRC0_PC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc0PcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + case DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc0PcMatchRcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + case DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc0PcRcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + case DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z: + pfnCallback = stcDstcInternData.pfnDstcQprc0UflOflZCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION) + case DSTC_IRQ_NUMBER_QPRC1_COUNT_INVERSION: + pfnCallback = stcDstcInternData.pfnDstcQprc1CountInversionCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE) + case DSTC_IRQ_NUMBER_QPRC1_OUT_OF_RANGE: + pfnCallback = stcDstcInternData.pfnDstcQprc1OutOfRangeCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH) + case DSTC_IRQ_NUMBER_QPRC1_PC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc1PcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH) + case DSTC_IRQ_NUMBER_QPRC1_PC_MATCH_RC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc1PcMatchRcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH) + case DSTC_IRQ_NUMBER_QPRC1_PC_RC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc1PcRcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z) + case DSTC_IRQ_NUMBER_QPRC1_UFL_OFL_Z: + pfnCallback = stcDstcInternData.pfnDstcQprc1UflOflZCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION) + case DSTC_IRQ_NUMBER_QPRC2_COUNT_INVERSION: + pfnCallback = stcDstcInternData.pfnDstcQprc2CountInversionCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE) + case DSTC_IRQ_NUMBER_QPRC2_OUT_OF_RANGE: + pfnCallback = stcDstcInternData.pfnDstcQprc2OutOfRangeCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH) + case DSTC_IRQ_NUMBER_QPRC2_PC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc2PcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH) + case DSTC_IRQ_NUMBER_QPRC2_PC_MATCH_RC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc2PcMatchRcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH) + case DSTC_IRQ_NUMBER_QPRC2_PC_RC_MATCH: + pfnCallback = stcDstcInternData.pfnDstcQprc2PcRcMatchCallback; + break; + #endif + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z) + case DSTC_IRQ_NUMBER_QPRC2_UFL_OFL_Z: + pfnCallback = stcDstcInternData.pfnDstcQprc2UflOflZCallback; + break; + #endif + default: + pfnCallback = NULL; + } + + if (TRUE == Dstc_ReadHwintBit(u8IrqChannel)) + { + Dstc_SetHwintclrBit(u8IrqChannel); + + if (NULL != pfnCallback) + { + pfnCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) ... + +#if (PDL_ON == PDL_DSTC_ENABLE_WC) +void Dstc_WcIrqHandler(void) +{ + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC)) + { + Dstc_SetHwintclrBit(DSTC_IRQ_NUMBER_WC); + + if (NULL != stcDstcInternData.pfnDstcWcCallback) + { + stcDstcInternData.pfnDstcWcCallback(); + } + } +} +#endif // #if (PDL_ON == PDL_DSTC_ENABLE_WC) + +#endif // #if (defined(PDL_PERIPHERAL_DSTC_ACTIVE) +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.h new file mode 100644 index 0000000000..a46fc53327 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dstc/dstc.h @@ -0,0 +1,2516 @@ +/****************************************************************************** +* \file dstc.h +* +* \version 1.40 +* +* \brief Header file of Descriptor System Data Transfer Controller driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __DSTC_H__ +#define __DSTC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_DSTC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/** +* \defgroup GroupDSTC Descriptor System Data Transfer Controller (DSTC) +* \{ +* \defgroup GroupDSTC_Macros Macros +* \defgroup GroupDSTC_Functions Functions +* \defgroup GroupDSTC_DataStructures Data Structures +* \defgroup GroupDSTC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupDSTC +* \{ +* The Descriptor System data Transfer Controller (DSTC), like the DMAC, +* is a function block that can transfer data at high speed, bypassing the +* CPU. Unlike a DMAC, it uses a Descriptor (DES) System Model, where descriptors +* located in the memory are used to describe the data transfers.
+* * Up to 256 transfer channels (device dependent) +* * Descriptors are placed consecutively in memory +* - - Up to 1024 DES can be stored +* * The DSTC has its own CPU-independent bus +* - - Transfer operations possible when CPU bus is accessed +* * Supports two trigger start modes: +* - - Software-Start +* - - Hardware-Start +* * Chain multiple DES to be executed by a single trigger (Chain Start) +* * Interrupt on completion or error
+* A DES describing a data transfer consists of 4 to 7 settings (DES0 to DES6) +* depending on its complexity. One set of transfer control details (basic +* transfer settings, number of transfers, transfer source address, transfer +* destination address) is specified in one DES. Multiple DES can be allocated +* to a 4096-word (16 Kbyte) area starting from the DESTP. The DSTC supports up +* to 1024 individual DES.
+* +*
NameDetails +*
DES0This sets the basic settings of a transfer. +*
DES1This sets the number of transfers. +*
DES2This sets the transfer source address (SA) at which a transfer starts. +*
DES3This sets the transfer destination address (DA) at which a transfer ends. +*
DES4DES1 reload value (OuterReload) - optional +*
DES5DES2 reload value (OuterReload) - optional +*
DES6DES3 reload value (OuterReload) - optional +*
+* The DSTC can generate an interrupt to notify the CPU of the normal or abnormal end +* of a transfer operation. It can control how an internal clock is stopped in a standby +* mode (low power consumption mode).
+* The DSTC allows the use of two reload functions. The InnerReload function is used +* for the transfer count and is described in DES1, whereas the OuterReload functions +* are used for resetting the Addresses and the transfer count and are described in DES4 +* to DES6.
+* Setting DES0 defines the basic functionality of the data transfer. The transfer width, +* if the addresses fixed or incremented, if the reload functions shall be used, if an +* interrupt flag will be set and if it is a descriptor chain. The descriptor is validated +* with a parity checksum and there are also status register included that indicate the +* current transfer state of the descriptor. The source and destination addresses are +* defined in the descriptors DES2 in DES3.
+* The DSTC can support up to 256 channels, for the exact number of supported +* channels refer to the device data sheet. +* \section SectionDSTC_ConfigurationConsideration Configuration Consideration +* To set up the DSTC, provide configuration parameters such as the address of +* the descriptors, interrupt sources and software callbacks for errors and notifications. +* Set fields in stc_dstc_config_t structure accordingly.
+* For the initialization there are predefined DES structure types for every combination +* of the descriptors. Note that for DES1 two different structures are existing for mode0 +* and mode1. You should use these structures within an enclosing structure, so that the +* descriptors are located on consecutive addresses. For calculating the parity checksum +* located in descriptor DES0 the macro DSTC_PCHK_CALC() can be used. The address of this +* structure then should be used for stc_dstc_config_t::u32Destp and passed to the +* initialization function Dstc_Init().
+* Example:
+* +* +* +* +* +* +* +* +* +*
struct stc_dstc_des_area
{
  stc_dstc_des01236_t   stcDesList0;
  stc_dstc_des0123_t    stcDesList1;
  stc_dstc_des0123_t    stcDesList2;
  stc_dstc_des0123456_t stcDesList3;
  . . .
};
+* +* To enable a Hardware channel set the corresponding bit in the register DREQENB either +* with the function Dstc_SetDreqenbBit() for a single channel or with Dstc_SetDreqenb() +* and the structure stc_dstc_dreqenb_t for the complete register. A list of the hardware +* trigger sources and the corresponding channels can be found in the FM0+/FM4 Peripheral +* Manual - Core Subsystem TRM in the Chapter “Lists of Interrupts”. For disabling a single +* hardware trigger clear the corresponding bit with the function Dstc_ClearDreqenbBit(). +* The status of the DREQENB register can be checked with the function Dstc_ReadDreqenb().
+* To start a transfer via software trigger, use the Dstc_SwTrigger() routine and pass +* the address offset from DESTP to the requested DES as parameter u16SwDesPointer. To +* check the status of a recently triggered software transfer use the function +* Dstc_SwTrqansferStartStatus(). +* +* \section SectionDSTC_MoreInfo More Information +* For more information on the DSTC peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem
+* FM4 Peripheral Manual Core Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupDSTC_Macros +* \{ +*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define DSTC_TRANSITION_TIMEOUT 100000u ///< Timeout counter for DSTC mode transition + +/// Parity checksum for DES0 PCHKS bits +#define DSTC_PCHK_CALC(x) ((((x) & 0x0F000000ul) >> 24u) ^ \ + (((x) & 0x00F00000ul) >> 20u) ^ \ + (((x) & 0x000F0000ul) >> 16u) ^ \ + (((x) & 0x0000F000ul) >> 12u) ^ \ + (((x) & 0x00000F00ul) >> 8u) ^ \ + (((x) & 0x000000F0ul) >> 4u)) + +/// DSTC interrupt numbers +#if (PDL_MCU_CORE == PDL_FM4_CORE) +#if (PDL_MCU_TYPE != PDL_FM4_TYPE4) +#define DSTC_IRQ_NUMBER_ADC0_PRIO 110u +#define DSTC_IRQ_NUMBER_ADC0_SCAN 111u +#define DSTC_IRQ_NUMBER_ADC1_PRIO 112u +#define DSTC_IRQ_NUMBER_ADC1_SCAN 113u +#define DSTC_IRQ_NUMBER_ADC2_PRIO 114u +#define DSTC_IRQ_NUMBER_ADC2_SCAN 115u +#define DSTC_IRQ_NUMBER_BT0_IRQ0 16u +#define DSTC_IRQ_NUMBER_BT0_IRQ1 17u +#define DSTC_IRQ_NUMBER_BT1_IRQ0 18u +#define DSTC_IRQ_NUMBER_BT1_IRQ1 19u +#define DSTC_IRQ_NUMBER_BT2_IRQ0 20u +#define DSTC_IRQ_NUMBER_BT2_IRQ1 21u +#define DSTC_IRQ_NUMBER_BT3_IRQ0 22u +#define DSTC_IRQ_NUMBER_BT3_IRQ1 23u +#define DSTC_IRQ_NUMBER_BT4_IRQ0 24u +#define DSTC_IRQ_NUMBER_BT4_IRQ1 25u +#define DSTC_IRQ_NUMBER_BT5_IRQ0 26u +#define DSTC_IRQ_NUMBER_BT5_IRQ1 27u +#define DSTC_IRQ_NUMBER_BT6_IRQ0 28u +#define DSTC_IRQ_NUMBER_BT6_IRQ1 29u +#define DSTC_IRQ_NUMBER_BT7_IRQ0 30u +#define DSTC_IRQ_NUMBER_BT7_IRQ1 31u +#define DSTC_IRQ_NUMBER_BT8_IRQ0 144u +#define DSTC_IRQ_NUMBER_BT8_IRQ1 145u +#define DSTC_IRQ_NUMBER_BT9_IRQ0 146u +#define DSTC_IRQ_NUMBER_BT9_IRQ1 147u +#define DSTC_IRQ_NUMBER_BT10_IRQ0 148u +#define DSTC_IRQ_NUMBER_BT10_IRQ1 149u +#define DSTC_IRQ_NUMBER_BT11_IRQ0 150u +#define DSTC_IRQ_NUMBER_BT11_IRQ1 151u +#define DSTC_IRQ_NUMBER_BT12_IRQ0 152u +#define DSTC_IRQ_NUMBER_BT12_IRQ1 153u +#define DSTC_IRQ_NUMBER_BT13_IRQ0 154u +#define DSTC_IRQ_NUMBER_BT13_IRQ1 155u +#define DSTC_IRQ_NUMBER_BT14_IRQ0 156u +#define DSTC_IRQ_NUMBER_BT14_IRQ1 157u +#define DSTC_IRQ_NUMBER_BT15_IRQ0 158u +#define DSTC_IRQ_NUMBER_BT15_IRQ1 159u +#define DSTC_IRQ_NUMBER_CANFD 223u +#define DSTC_IRQ_NUMBER_EXINT0 0u +#define DSTC_IRQ_NUMBER_EXINT1 1u +#define DSTC_IRQ_NUMBER_EXINT2 2u +#define DSTC_IRQ_NUMBER_EXINT3 3u +#define DSTC_IRQ_NUMBER_EXINT4 4u +#define DSTC_IRQ_NUMBER_EXINT5 5u +#define DSTC_IRQ_NUMBER_EXINT6 6u +#define DSTC_IRQ_NUMBER_EXINT7 7u +#define DSTC_IRQ_NUMBER_EXINT8 8u +#define DSTC_IRQ_NUMBER_EXINT9 9u +#define DSTC_IRQ_NUMBER_EXINT10 10u +#define DSTC_IRQ_NUMBER_EXINT11 11u +#define DSTC_IRQ_NUMBER_EXINT12 12u +#define DSTC_IRQ_NUMBER_EXINT13 13u +#define DSTC_IRQ_NUMBER_EXINT14 14u +#define DSTC_IRQ_NUMBER_EXINT15 15u +#define DSTC_IRQ_NUMBER_EXINT16 128u +#define DSTC_IRQ_NUMBER_EXINT17 129u +#define DSTC_IRQ_NUMBER_EXINT18 130u +#define DSTC_IRQ_NUMBER_EXINT19 131u +#define DSTC_IRQ_NUMBER_EXINT20 132u +#define DSTC_IRQ_NUMBER_EXINT21 133u +#define DSTC_IRQ_NUMBER_EXINT22 134u +#define DSTC_IRQ_NUMBER_EXINT23 135u +#define DSTC_IRQ_NUMBER_EXINT24 136u +#define DSTC_IRQ_NUMBER_EXINT25 137u +#define DSTC_IRQ_NUMBER_EXINT26 138u +#define DSTC_IRQ_NUMBER_EXINT27 139u +#define DSTC_IRQ_NUMBER_EXINT28 140u +#define DSTC_IRQ_NUMBER_EXINT29 141u +#define DSTC_IRQ_NUMBER_EXINT30 142u +#define DSTC_IRQ_NUMBER_EXINT31 143u +#define DSTC_IRQ_NUMBER_HSSPI0_TX 221u +#define DSTC_IRQ_NUMBER_HSSPI0_RX 220u +#define DSTC_IRQ_NUMBER_I2S0_TX 219u +#define DSTC_IRQ_NUMBER_I2S0_RX 218u +#define DSTC_IRQ_NUMBER_MFS0_RX 89u +#define DSTC_IRQ_NUMBER_MFS0_TX 90u +#define DSTC_IRQ_NUMBER_MFS1_RX 91u +#define DSTC_IRQ_NUMBER_MFS1_TX 92u +#define DSTC_IRQ_NUMBER_MFS2_RX 93u +#define DSTC_IRQ_NUMBER_MFS2_TX 94u +#define DSTC_IRQ_NUMBER_MFS3_RX 95u +#define DSTC_IRQ_NUMBER_MFS3_TX 96u +#define DSTC_IRQ_NUMBER_MFS4_RX 97u +#define DSTC_IRQ_NUMBER_MFS4_TX 98u +#define DSTC_IRQ_NUMBER_MFS5_RX 99u +#define DSTC_IRQ_NUMBER_MFS5_TX 100u +#define DSTC_IRQ_NUMBER_MFS6_RX 101u +#define DSTC_IRQ_NUMBER_MFS6_TX 102u +#define DSTC_IRQ_NUMBER_MFS7_RX 103u +#define DSTC_IRQ_NUMBER_MFS7_TX 104u +#define DSTC_IRQ_NUMBER_MFS8_RX 194u +#define DSTC_IRQ_NUMBER_MFS8_TX 195u +#define DSTC_IRQ_NUMBER_MFS9_RX 196u +#define DSTC_IRQ_NUMBER_MFS9_TX 197u +#define DSTC_IRQ_NUMBER_MFS10_RX 198u +#define DSTC_IRQ_NUMBER_MFS10_TX 199u +#define DSTC_IRQ_NUMBER_MFS11_RX 200u +#define DSTC_IRQ_NUMBER_MFS11_TX 201u +#define DSTC_IRQ_NUMBER_MFS12_RX 209u +#define DSTC_IRQ_NUMBER_MFS12_TX 210u +#define DSTC_IRQ_NUMBER_MFS13_RX 211u +#define DSTC_IRQ_NUMBER_MFS13_TX 212u +#define DSTC_IRQ_NUMBER_MFS14_RX 213u +#define DSTC_IRQ_NUMBER_MFS14_TX 214u +#define DSTC_IRQ_NUMBER_MFS15_RX 215u +#define DSTC_IRQ_NUMBER_MFS15_TX 216u +#define DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK 35u +#define DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO 38u +#define DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK 36u +#define DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO 39u +#define DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK 37u +#define DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO 40u +#define DSTC_IRQ_NUMBER_MFT0_ICU0 41u +#define DSTC_IRQ_NUMBER_MFT0_ICU1 42u +#define DSTC_IRQ_NUMBER_MFT0_ICU2 43u +#define DSTC_IRQ_NUMBER_MFT0_ICU3 44u +#define DSTC_IRQ_NUMBER_MFT0_OCU0 45u +#define DSTC_IRQ_NUMBER_MFT0_OCU1 46u +#define DSTC_IRQ_NUMBER_MFT0_OCU2 47u +#define DSTC_IRQ_NUMBER_MFT0_OCU3 48u +#define DSTC_IRQ_NUMBER_MFT0_OCU4 49u +#define DSTC_IRQ_NUMBER_MFT0_OCU5 50u +#define DSTC_IRQ_NUMBER_MFT0_WFG10 32u +#define DSTC_IRQ_NUMBER_MFT0_WFG32 33u +#define DSTC_IRQ_NUMBER_MFT0_WFG54 34u +#define DSTC_IRQ_NUMBER_MFT1_FRT0_PEAK 54u +#define DSTC_IRQ_NUMBER_MFT1_FRT0_ZERO 57u +#define DSTC_IRQ_NUMBER_MFT1_FRT1_PEAK 55u +#define DSTC_IRQ_NUMBER_MFT1_FRT1_ZERO 58u +#define DSTC_IRQ_NUMBER_MFT1_FRT2_PEAK 56u +#define DSTC_IRQ_NUMBER_MFT1_FRT2_ZERO 59u +#define DSTC_IRQ_NUMBER_MFT1_ICU0 60u +#define DSTC_IRQ_NUMBER_MFT1_ICU1 61u +#define DSTC_IRQ_NUMBER_MFT1_ICU2 62u +#define DSTC_IRQ_NUMBER_MFT1_ICU3 63u +#define DSTC_IRQ_NUMBER_MFT1_OCU0 64u +#define DSTC_IRQ_NUMBER_MFT1_OCU1 65u +#define DSTC_IRQ_NUMBER_MFT1_OCU2 66u +#define DSTC_IRQ_NUMBER_MFT1_OCU3 67u +#define DSTC_IRQ_NUMBER_MFT1_OCU4 68u +#define DSTC_IRQ_NUMBER_MFT1_OCU5 69u +#define DSTC_IRQ_NUMBER_MFT1_WFG10 51u +#define DSTC_IRQ_NUMBER_MFT1_WFG32 52u +#define DSTC_IRQ_NUMBER_MFT1_WFG54 53u +#define DSTC_IRQ_NUMBER_MFT2_FRT0_PEAK 163u +#define DSTC_IRQ_NUMBER_MFT2_FRT0_ZERO 166u +#define DSTC_IRQ_NUMBER_MFT2_FRT1_PEAK 164u +#define DSTC_IRQ_NUMBER_MFT2_FRT1_ZERO 167u +#define DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK 165u +#define DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO 168u +#define DSTC_IRQ_NUMBER_MFT2_ICU0 169u +#define DSTC_IRQ_NUMBER_MFT2_ICU1 170u +#define DSTC_IRQ_NUMBER_MFT2_ICU2 171u +#define DSTC_IRQ_NUMBER_MFT2_ICU3 172u +#define DSTC_IRQ_NUMBER_MFT2_OCU0 173u +#define DSTC_IRQ_NUMBER_MFT2_OCU1 174u +#define DSTC_IRQ_NUMBER_MFT2_OCU2 175u +#define DSTC_IRQ_NUMBER_MFT2_OCU3 176u +#define DSTC_IRQ_NUMBER_MFT2_OCU4 177u +#define DSTC_IRQ_NUMBER_MFT2_OCU5 178u +#define DSTC_IRQ_NUMBER_MFT2_WFG10 160u +#define DSTC_IRQ_NUMBER_MFT2_WFG32 161u +#define DSTC_IRQ_NUMBER_MFT2_WFG54 162u +#define DSTC_IRQ_NUMBER_PCRC 222u +#define DSTC_IRQ_NUMBER_PPG0 70u +#define DSTC_IRQ_NUMBER_PPG10 74u +#define DSTC_IRQ_NUMBER_PPG12 75u +#define DSTC_IRQ_NUMBER_PPG16 179u +#define DSTC_IRQ_NUMBER_PPG18 180u +#define DSTC_IRQ_NUMBER_PPG2 71u +#define DSTC_IRQ_NUMBER_PPG20 181u +#define DSTC_IRQ_NUMBER_PPG4 72u +#define DSTC_IRQ_NUMBER_PPG8 73u +#define DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION 79u +#define DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE 80u +#define DSTC_IRQ_NUMBER_QPRC0_PC_MATCH 76u +#define DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH 81u +#define DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH 77u +#define DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z 78u +#define DSTC_IRQ_NUMBER_QPRC1_COUNT_INVERSION 85u +#define DSTC_IRQ_NUMBER_QPRC1_OUT_OF_RANGE 86u +#define DSTC_IRQ_NUMBER_QPRC1_PC_MATCH 82u +#define DSTC_IRQ_NUMBER_QPRC1_PC_MATCH_RC_MATCH 87u +#define DSTC_IRQ_NUMBER_QPRC1_PC_RC_MATCH 83u +#define DSTC_IRQ_NUMBER_QPRC1_UFL_OFL_Z 84u +#define DSTC_IRQ_NUMBER_QPRC2_COUNT_INVERSION 185u +#define DSTC_IRQ_NUMBER_QPRC2_OUT_OF_RANGE 186u +#define DSTC_IRQ_NUMBER_QPRC2_PC_MATCH 182u +#define DSTC_IRQ_NUMBER_QPRC2_PC_MATCH_RC_MATCH 187u +#define DSTC_IRQ_NUMBER_QPRC2_PC_RC_MATCH 183u +#define DSTC_IRQ_NUMBER_QPRC2_UFL_OFL_Z 184u +#define DSTC_IRQ_NUMBER_QPRC3_COUNT_INVERSION 191u +#define DSTC_IRQ_NUMBER_QPRC3_OUT_OF_RANGE 192u +#define DSTC_IRQ_NUMBER_QPRC3_PC_MATCH 188u +#define DSTC_IRQ_NUMBER_QPRC3_PC_MATCH_RC_MATCH 193u +#define DSTC_IRQ_NUMBER_QPRC3_PC_RC_MATCH 189u +#define DSTC_IRQ_NUMBER_QPRC3_UFL_OFL_Z 190u +#define DSTC_IRQ_NUMBER_USB0_EP1 105u +#define DSTC_IRQ_NUMBER_USB0_EP2 106u +#define DSTC_IRQ_NUMBER_USB0_EP3 107u +#define DSTC_IRQ_NUMBER_USB0_EP4 108u +#define DSTC_IRQ_NUMBER_USB0_EP5 109u +#define DSTC_IRQ_NUMBER_USB1_EP1 202u +#define DSTC_IRQ_NUMBER_USB1_EP2 203u +#define DSTC_IRQ_NUMBER_USB1_EP3 204u +#define DSTC_IRQ_NUMBER_USB1_EP4 205u +#define DSTC_IRQ_NUMBER_USB1_EP5 206u +#define DSTC_IRQ_NUMBER_WC 88u +#else +#define DSTC_IRQ_NUMBER_ADC0_PRIO 110u +#define DSTC_IRQ_NUMBER_ADC0_SCAN 111u +#define DSTC_IRQ_NUMBER_ADC1_PRIO 112u +#define DSTC_IRQ_NUMBER_ADC1_SCAN 113u +#define DSTC_IRQ_NUMBER_BT0_IRQ0 16u +#define DSTC_IRQ_NUMBER_BT0_IRQ1 17u +#define DSTC_IRQ_NUMBER_BT1_IRQ0 18u +#define DSTC_IRQ_NUMBER_BT1_IRQ1 19u +#define DSTC_IRQ_NUMBER_BT2_IRQ0 20u +#define DSTC_IRQ_NUMBER_BT2_IRQ1 21u +#define DSTC_IRQ_NUMBER_BT3_IRQ0 22u +#define DSTC_IRQ_NUMBER_BT3_IRQ1 23u +#define DSTC_IRQ_NUMBER_BT4_IRQ0 24u +#define DSTC_IRQ_NUMBER_BT4_IRQ1 25u +#define DSTC_IRQ_NUMBER_BT5_IRQ0 26u +#define DSTC_IRQ_NUMBER_BT5_IRQ1 27u +#define DSTC_IRQ_NUMBER_BT6_IRQ0 28u +#define DSTC_IRQ_NUMBER_BT6_IRQ1 29u +#define DSTC_IRQ_NUMBER_BT7_IRQ0 30u +#define DSTC_IRQ_NUMBER_BT7_IRQ1 31u +#define DSTC_IRQ_NUMBER_CANFD 127u +#define DSTC_IRQ_NUMBER_EXINT0 0u +#define DSTC_IRQ_NUMBER_EXINT1 1u +#define DSTC_IRQ_NUMBER_EXINT2 2u +#define DSTC_IRQ_NUMBER_EXINT3 3u +#define DSTC_IRQ_NUMBER_EXINT4 4u +#define DSTC_IRQ_NUMBER_EXINT5 5u +#define DSTC_IRQ_NUMBER_EXINT6 6u +#define DSTC_IRQ_NUMBER_EXINT7 7u +#define DSTC_IRQ_NUMBER_EXINT8 8u +#define DSTC_IRQ_NUMBER_EXINT9 9u +#define DSTC_IRQ_NUMBER_EXINT10 10u +#define DSTC_IRQ_NUMBER_EXINT11 11u +#define DSTC_IRQ_NUMBER_EXINT12 12u +#define DSTC_IRQ_NUMBER_EXINT13 13u +#define DSTC_IRQ_NUMBER_EXINT14 14u +#define DSTC_IRQ_NUMBER_EXINT15 15u +#define DSTC_IRQ_NUMBER_HSSPI0_TX 125u +#define DSTC_IRQ_NUMBER_HSSPI0_RX 124u +#define DSTC_IRQ_NUMBER_I2S0_TX 121u +#define DSTC_IRQ_NUMBER_I2S0_RX 120u +#define DSTC_IRQ_NUMBER_I2S1_TX 123u +#define DSTC_IRQ_NUMBER_I2S1_RX 122u +#define DSTC_IRQ_NUMBER_MFS0_RX 89u +#define DSTC_IRQ_NUMBER_MFS0_TX 90u +#define DSTC_IRQ_NUMBER_MFS1_RX 91u +#define DSTC_IRQ_NUMBER_MFS1_TX 92u +#define DSTC_IRQ_NUMBER_MFS2_RX 93u +#define DSTC_IRQ_NUMBER_MFS2_TX 94u +#define DSTC_IRQ_NUMBER_MFS3_RX 95u +#define DSTC_IRQ_NUMBER_MFS3_TX 96u +#define DSTC_IRQ_NUMBER_MFS4_RX 97u +#define DSTC_IRQ_NUMBER_MFS4_TX 98u +#define DSTC_IRQ_NUMBER_MFS5_RX 99u +#define DSTC_IRQ_NUMBER_MFS5_TX 100u +#define DSTC_IRQ_NUMBER_MFS6_RX 101u +#define DSTC_IRQ_NUMBER_MFS6_TX 102u +#define DSTC_IRQ_NUMBER_MFS7_RX 103u +#define DSTC_IRQ_NUMBER_MFS7_TX 104u +#define DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK 35u +#define DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO 38u +#define DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK 36u +#define DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO 39u +#define DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK 37u +#define DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO 40u +#define DSTC_IRQ_NUMBER_MFT0_ICU0 41u +#define DSTC_IRQ_NUMBER_MFT0_ICU1 42u +#define DSTC_IRQ_NUMBER_MFT0_ICU2 43u +#define DSTC_IRQ_NUMBER_MFT0_ICU3 44u +#define DSTC_IRQ_NUMBER_MFT0_OCU0 45u +#define DSTC_IRQ_NUMBER_MFT0_OCU1 46u +#define DSTC_IRQ_NUMBER_MFT0_OCU2 47u +#define DSTC_IRQ_NUMBER_MFT0_OCU3 48u +#define DSTC_IRQ_NUMBER_MFT0_OCU4 49u +#define DSTC_IRQ_NUMBER_MFT0_OCU5 50u +#define DSTC_IRQ_NUMBER_MFT0_WFG10 32u +#define DSTC_IRQ_NUMBER_MFT0_WFG32 33u +#define DSTC_IRQ_NUMBER_MFT0_WFG54 34u +#define DSTC_IRQ_NUMBER_PCRC 126u +#define DSTC_IRQ_NUMBER_PPG0 70u +#define DSTC_IRQ_NUMBER_PPG2 71u +#define DSTC_IRQ_NUMBER_PPG4 72u +#define DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION 79u +#define DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE 80u +#define DSTC_IRQ_NUMBER_QPRC0_PC_MATCH 76u +#define DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH 81u +#define DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH 77u +#define DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z 78u +#define DSTC_IRQ_NUMBER_USB0_EP1 105u +#define DSTC_IRQ_NUMBER_USB0_EP2 106u +#define DSTC_IRQ_NUMBER_USB0_EP3 107u +#define DSTC_IRQ_NUMBER_USB0_EP4 108u +#define DSTC_IRQ_NUMBER_USB0_EP5 109u +#define DSTC_IRQ_NUMBER_WC 88u +#endif +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +#define DSTC_IRQ_NUMBER_ADC0_PRIO 62u +#define DSTC_IRQ_NUMBER_ADC0_SCAN 63u +#define DSTC_IRQ_NUMBER_BT0_IRQ0 13u +#define DSTC_IRQ_NUMBER_BT0_IRQ1 14u +#define DSTC_IRQ_NUMBER_BT1_IRQ0 15u +#define DSTC_IRQ_NUMBER_BT1_IRQ1 16u +#define DSTC_IRQ_NUMBER_BT2_IRQ0 17u +#define DSTC_IRQ_NUMBER_BT2_IRQ1 18u +#define DSTC_IRQ_NUMBER_BT3_IRQ0 19u +#define DSTC_IRQ_NUMBER_BT3_IRQ1 20u +#define DSTC_IRQ_NUMBER_BT4_IRQ0 21u +#define DSTC_IRQ_NUMBER_BT6_IRQ0 22u +#define DSTC_IRQ_NUMBER_EXINT0 0u +#define DSTC_IRQ_NUMBER_EXINT1 1u +#define DSTC_IRQ_NUMBER_EXINT2 2u +#define DSTC_IRQ_NUMBER_EXINT3 3u +#define DSTC_IRQ_NUMBER_EXINT4 4u +#define DSTC_IRQ_NUMBER_EXINT5 5u +#define DSTC_IRQ_NUMBER_EXINT6 6u +#define DSTC_IRQ_NUMBER_EXINT7 7u +#define DSTC_IRQ_NUMBER_EXINT8 8u +#define DSTC_IRQ_NUMBER_EXINT9 9u +#define DSTC_IRQ_NUMBER_EXINT10 10u +#define DSTC_IRQ_NUMBER_EXINT11 11u +#define DSTC_IRQ_NUMBER_EXINT12 12u +#define DSTC_IRQ_NUMBER_MFS0_RX 46u +#define DSTC_IRQ_NUMBER_MFS0_TX 47u +#define DSTC_IRQ_NUMBER_MFS1_RX 48u +#define DSTC_IRQ_NUMBER_MFS1_TX 49u +#define DSTC_IRQ_NUMBER_MFS2_RX 50u +#define DSTC_IRQ_NUMBER_MFS2_TX 51u +#define DSTC_IRQ_NUMBER_MFS3_RX 52u +#define DSTC_IRQ_NUMBER_MFS3_TX 53u +#define DSTC_IRQ_NUMBER_MFS4_RX 54u +#define DSTC_IRQ_NUMBER_MFS4_TX 55u +#define DSTC_IRQ_NUMBER_MFS5_RX 56u +#define DSTC_IRQ_NUMBER_MFS5_TX 57u +#define DSTC_IRQ_NUMBER_MFS6_RX 58u +#define DSTC_IRQ_NUMBER_MFS6_TX 59u +#define DSTC_IRQ_NUMBER_MFS7_RX 60u +#define DSTC_IRQ_NUMBER_MFS7_TX 61u +#define DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK 26u +#define DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO 29u +#define DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK 27u +#define DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO 30u +#define DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK 28u +#define DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO 31u +#define DSTC_IRQ_NUMBER_MFT0_ICU0 32u +#define DSTC_IRQ_NUMBER_MFT0_ICU1 33u +#define DSTC_IRQ_NUMBER_MFT0_ICU2 34u +#define DSTC_IRQ_NUMBER_MFT0_ICU3 35u +#define DSTC_IRQ_NUMBER_MFT0_OCU0 36u +#define DSTC_IRQ_NUMBER_MFT0_OCU1 37u +#define DSTC_IRQ_NUMBER_MFT0_OCU2 38u +#define DSTC_IRQ_NUMBER_MFT0_OCU3 39u +#define DSTC_IRQ_NUMBER_MFT0_OCU4 40u +#define DSTC_IRQ_NUMBER_MFT0_OCU5 41u +#define DSTC_IRQ_NUMBER_MFT0_WFG10 23u +#define DSTC_IRQ_NUMBER_MFT0_WFG32 24u +#define DSTC_IRQ_NUMBER_MFT0_WFG54 25u +#define DSTC_IRQ_NUMBER_PPG0 42u +#define DSTC_IRQ_NUMBER_PPG2 43u +#define DSTC_IRQ_NUMBER_PPG4 44u +#define DSTC_IRQ_NUMBER_WC 45u +#elif (PDL_MCU_TYPE == PDL_FM0P_TYPE3) +#define DSTC_IRQ_NUMBER_ADC0_PRIO 50u +#define DSTC_IRQ_NUMBER_ADC0_SCAN 51u +#define DSTC_IRQ_NUMBER_BT0_IRQ0 32u +#define DSTC_IRQ_NUMBER_BT0_IRQ1 33u +#define DSTC_IRQ_NUMBER_BT1_IRQ0 36u +#define DSTC_IRQ_NUMBER_BT1_IRQ1 37u +#define DSTC_IRQ_NUMBER_BT2_IRQ0 40u +#define DSTC_IRQ_NUMBER_BT2_IRQ1 41u +#define DSTC_IRQ_NUMBER_BT3_IRQ0 44u +#define DSTC_IRQ_NUMBER_BT3_IRQ1 45u +#define DSTC_IRQ_NUMBER_BT4_IRQ0 34u +#define DSTC_IRQ_NUMBER_BT4_IRQ1 35u +#define DSTC_IRQ_NUMBER_BT5_IRQ0 34u +#define DSTC_IRQ_NUMBER_BT5_IRQ1 35u +#define DSTC_IRQ_NUMBER_BT6_IRQ0 42u +#define DSTC_IRQ_NUMBER_BT6_IRQ1 43u +#define DSTC_IRQ_NUMBER_BT7_IRQ0 46u +#define DSTC_IRQ_NUMBER_BT7_IRQ1 47u +#define DSTC_IRQ_NUMBER_EXINT0 16u +#define DSTC_IRQ_NUMBER_EXINT1 17u +#define DSTC_IRQ_NUMBER_EXINT2 18u +#define DSTC_IRQ_NUMBER_EXINT3 19u +#define DSTC_IRQ_NUMBER_EXINT4 20u +#define DSTC_IRQ_NUMBER_EXINT5 21u +#define DSTC_IRQ_NUMBER_EXINT6 22u +#define DSTC_IRQ_NUMBER_EXINT7 23u +#define DSTC_IRQ_NUMBER_EXINT8 24u +#define DSTC_IRQ_NUMBER_EXINT12 28u +#define DSTC_IRQ_NUMBER_EXINT13 29u +#define DSTC_IRQ_NUMBER_EXINT15 31u +#define DSTC_IRQ_NUMBER_I2CSLAVE_RX 48 +#define DSTC_IRQ_NUMBER_I2CSLAVE_TX 49 +#define DSTC_IRQ_NUMBER_MFS0_RX 0u +#define DSTC_IRQ_NUMBER_MFS0_TX 1u +#define DSTC_IRQ_NUMBER_MFS1_RX 2u +#define DSTC_IRQ_NUMBER_MFS1_TX 3u +#define DSTC_IRQ_NUMBER_MFS3_RX 6u +#define DSTC_IRQ_NUMBER_MFS3_TX 7u +#define DSTC_IRQ_NUMBER_MFS4_RX 8u +#define DSTC_IRQ_NUMBER_MFS4_TX 9u +#define DSTC_IRQ_NUMBER_MFS6_RX 12u +#define DSTC_IRQ_NUMBER_MFS6_TX 13u +#define DSTC_IRQ_NUMBER_MFS7_RX 14u +#define DSTC_IRQ_NUMBER_MFS7_TX 15u +#define DSTC_IRQ_NUMBER_MFS7_TX 15u +#define DSTC_IRQ_NUMBER_USB0_EP1 52u +#define DSTC_IRQ_NUMBER_USB0_EP2 53u +#define DSTC_IRQ_NUMBER_USB0_EP3 54u +#define DSTC_IRQ_NUMBER_USB0_EP4 55u +#define DSTC_IRQ_NUMBER_USB0_EP5 56u +#define DSTC_IRQ_NUMBER_WC 57u +#endif +#else +#error DSTC is not available in this product! +#endif +/** \} GroupDSTC_Macros */ + +/** +* \addtogroup GroupDSTC_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief DSTC Commands + ******************************************************************************/ +typedef enum en_dstc_cmd +{ + CmdStandyRelease = 0u, ///< Instructs DSTC to return from standby state into normal state + CmdStandyTransition = 1u, ///< Instructs DSTC to standby state + CmdSwclr = 2u, ///< Clears SWTR:SWST to '0'; negates SWINT interrupt signal + CmdErclr = 3u, ///< Clears MONERS:EST, MONERS:DER, and MONERS:ESTOP + CmdRbclr = 4u, ///< Clears DESP to which DSTP refers in previous transfer; Sets next DES; Clears HWDESP[n] + CmdMkclr = 5u ///< Clears all DQMSK[n] +} en_dstc_cmd_t; + +/** + ****************************************************************************** + ** \brief Software Transfer Priority + ******************************************************************************/ +typedef enum en_dstc_swpr +{ + PriorityHighest = 0u, ///< Highest Priority + Priority1_2 = 1u, ///< Priority 1/2 Transfer Right + Priority1_3 = 2u, ///< Priority 1/3 Transfer Right + Priority1_7 = 3u, ///< Priority 1/7 Transfer Right + Priority1_15 = 4u, ///< Priority 1/15 Transfer Right. Initial Value + Priority1_31 = 5u, ///< Priority 1/31 Transfer Right + Priority1_63 = 6u, ///< Priority 1/63 Transfer Right + PriorityLowest = 7u ///< Lowest Priority +} en_dstc_swpr_t; + +/** + ****************************************************************************** + ** \brief MONERS EST Error Code + ******************************************************************************/ +typedef enum en_dstc_est_error +{ + NoError = 0u, ///< No error occurred + SourceAccessError = 1u, ///< Source access error + DestinationAccessError = 2u, ///< Destination access error + ForcedTransferStop = 3u, ///< Transfer has been stopped compulsorily + DesAccessError = 4u, ///< DES access error + DesOpenError = 5u, ///< DES open error + UnknownError = 6u ///< Undefined state, should never happen +} en_dstc_est_error_t; + +/** + ****************************************************************************** + ** \brief Error Status Callback + ******************************************************************************/ +typedef void (*func_ptr_dstc_args_t)(en_dstc_est_error_t enEstError, + uint16_t u16ErrorChannel, + uint16_t u16ErrorDesPointer, + boolean_t bSoftwareError, + boolean_t bDoubleError, + boolean_t bErrorStop); + +/** \}GroupDSTC_Types */ + +/** +* \addtogroup GroupDSTC_DataStructures +* \{ +*/ +/** + ****************************************************************************** + ** \brief DREQENB structure + ******************************************************************************/ +typedef struct stc_dstc_dreqenb +{ + uint32_t u32Dreqenb0; ///< DREQENB[31:0] + uint32_t u32Dreqenb1; ///< DREQENB[63:32] + uint32_t u32Dreqenb2; ///< DREQENB[95:64] + uint32_t u32Dreqenb3; ///< DREQENB[127:96] + uint32_t u32Dreqenb4; ///< DREQENB[159:128] + uint32_t u32Dreqenb5; ///< DREQENB[191:160] + uint32_t u32Dreqenb6; ///< DREQENB[223:192] + uint32_t u32Dreqenb7; ///< DREQENB[255:224] +} stc_dstc_dreqenb_t; + +/** + ****************************************************************************** + ** \brief HWINT structure + ******************************************************************************/ +typedef struct stc_dstc_hwint +{ + uint32_t u32Hwint0; ///< HWINT[31:0] + uint32_t u32Hwint1; ///< HWINT[63:32] + uint32_t u32Hwint2; ///< HWINT[95:64] + uint32_t u32Hwint3; ///< HWINT[127:96] + uint32_t u32Hwint4; ///< HWINT[159:128] + uint32_t u32Hwint5; ///< HWINT[191:160] + uint32_t u32Hwint6; ///< HWINT[223:192] + uint32_t u32Hwint7; ///< HWINT[255:224] +} stc_dstc_hwint_t; + +/** + ****************************************************************************** + ** \brief HWINTCLR structure + ******************************************************************************/ +typedef struct stc_dstc_hwintclr +{ + uint32_t u32Hwintclr0; ///< HWINTCLR[31:0] + uint32_t u32Hwintclr1; ///< HWINTCLR[63:32] + uint32_t u32Hwintclr2; ///< HWINTCLR[95:64] + uint32_t u32Hwintclr3; ///< HWINTCLR[127:96] + uint32_t u32Hwintclr4; ///< HWINTCLR[159:128] + uint32_t u32Hwintclr5; ///< HWINTCLR[191:160] + uint32_t u32Hwintclr6; ///< HWINTCLR[223:192] + uint32_t u32Hwintclr7; ///< HWINTCLR[255:224] +} stc_dstc_hwintclr_t; + +/** + ****************************************************************************** + ** \brief DQMSK structure + ******************************************************************************/ +typedef struct stc_dstc_dqmsk +{ + uint32_t u32Dqmsk0; ///< DQMSK[31:0] + uint32_t u32Dqmsk1; ///< DQMSK[63:32] + uint32_t u32Dqmsk2; ///< DQMSK[95:64] + uint32_t u32Dqmsk3; ///< DQMSK[127:96] + uint32_t u32Dqmsk4; ///< DQMSK[159:128] + uint32_t u32Dqmsk5; ///< DQMSK[191:160] + uint32_t u32Dqmsk6; ///< DQMSK[223:192] + uint32_t u32Dqmsk7; ///< DQMSK[255:224] +} stc_dstc_dqmsk_t; + +/** + ****************************************************************************** + ** \brief DQMSKCLR structure + ******************************************************************************/ +typedef struct stc_dstc_dqmskclr +{ + uint32_t u32Dqmskclr0; ///< DQMSKCLR[31:0] + uint32_t u32Dqmskclr1; ///< DQMSKCLR[63:32] + uint32_t u32Dqmskclr2; ///< DQMSKCLR[95:64] + uint32_t u32Dqmskclr3; ///< DQMSKCLR[127:96] + uint32_t u32Dqmskclr4; ///< DQMSKCLR[159:128] + uint32_t u32Dqmskclr5; ///< DQMSKCLR[191:160] + uint32_t u32Dqmskclr6; ///< DQMSKCLR[223:192] + uint32_t u32Dqmskclr7; ///< DQMSKCLR[255:224] +} stc_dstc_dqmskclr_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor 0 (DES0 - Transfer Basic Setting) + ******************************************************************************/ +typedef struct stc_dstc_des0 +{ + uint32_t DV : 2; + uint32_t ST : 2; + uint32_t MODE : 1; + uint32_t ORL : 3; + uint32_t TW : 2; + uint32_t SAC : 3; + uint32_t DAC : 3; + uint32_t CHRS : 6; + uint32_t DMSET : 1; + uint32_t CHLK : 1; + uint32_t ACK : 2; + uint32_t RESERVED : 2; + uint32_t PCHK : 4; +} stc_dstc_des0_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor 1 (DES1 - Number of Transfers) in Mode 0 + ******************************************************************************/ +typedef struct stc_dstc_des1_mode0 +{ + uint32_t IIN : 16; + uint32_t ORM : 16; +} stc_dstc_des1_mode0_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor 1 (DES1 - Number of Transfers) in Mode 1 + ******************************************************************************/ +typedef struct stc_dstc_des1_mode1 +{ + uint32_t IIN : 8; + uint32_t IRM : 8; + uint32_t ORM : 16; +} stc_dstc_des1_mode1_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES3 + ******************************************************************************/ +typedef struct stc_dstc_des0123 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address +} stc_dstc_des0123_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES4 + ******************************************************************************/ +typedef struct stc_dstc_des01234 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + union + { + stc_dstc_des1_mode0_t DES4_mode0; // Number of Transfers in Mode 0 for OuterReload (copied in DES1 Mode 0) + stc_dstc_des1_mode1_t DES4_mode1; // Number of Transfers in Mode 1 for OuterReload (copied in DES1 Mode 1) + }; +} stc_dstc_des01234_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES5 + ******************************************************************************/ +typedef struct stc_dstc_des012345 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + union + { + stc_dstc_des1_mode0_t DES4_mode0; // Number of Transfers in Mode 0 for OuterReload (copied in DES1 Mode 0) + stc_dstc_des1_mode1_t DES4_mode1; // Number of Transfers in Mode 1 for OuterReload (copied in DES1 Mode 1) + }; + uint32_t DES5; // Source Address in OuterReload (copied in DES2) +} stc_dstc_des012345_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES6 + ******************************************************************************/ +typedef struct stc_dstc_des0123456 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + union + { + stc_dstc_des1_mode0_t DES4_mode0; // Number of Transfers in Mode 0 for OuterReload (copied in DES1 Mode 0) + stc_dstc_des1_mode1_t DES4_mode1; // Number of Transfers in Mode 1 for OuterReload (copied in DES1 Mode 1) + }; + uint32_t DES5; // Source Address in OuterReload (copied in DES2) + uint32_t DES6; // Destination Address in OuterReload (copied in DES3) +} stc_dstc_des0123456_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES3, DES5 + ******************************************************************************/ +typedef struct stc_dstc_des01235 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + uint32_t DES5; // Source Address in OuterReload (copied in DES2) +} stc_dstc_des01235_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES3, DES6 + ******************************************************************************/ +typedef struct stc_dstc_des01236 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + uint32_t DES6; // Destination Address in OuterReload (copied in DES3) +} stc_dstc_des01236_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES4, DES6 + ******************************************************************************/ +typedef struct stc_dstc_des012346 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + union + { + stc_dstc_des1_mode0_t DES4_mode0; // Number of Transfers in Mode 0 for OuterReload (copied in DES1 Mode 0) + stc_dstc_des1_mode1_t DES4_mode1; // Number of Transfers in Mode 1 for OuterReload (copied in DES1 Mode 1) + }; + uint32_t DES6; // Destination Address in OuterReload (copied in DES3) +} stc_dstc_des012346_t; + +/** + ****************************************************************************** + ** \brief Definition of Descriptor Group DES0 - DES3, DES5, DES6 + ******************************************************************************/ +typedef struct stc_dstc_des012356 +{ + union + { + uint32_t u32DES0; // Needed for PCHK calculation + stc_dstc_des0_t DES0; // Transfer basic setting + }; + union + { + stc_dstc_des1_mode0_t DES1_mode0; // Number of Transfers in Mode 0 + stc_dstc_des1_mode1_t DES1_mode1; // Number of Transfers in Mode 1 + }; + uint32_t DES2; // Source Address + uint32_t DES3; // Destination Address + uint32_t DES5; // Source Address in OuterReload (copied in DES2) + uint32_t DES6; // Destination Address in OuterReload (copied in DES3) +} stc_dstc_des012356_t; + +/** + ****************************************************************************** + ** \brief DSTC configuration. + ******************************************************************************/ +typedef struct stc_dstc_config +{ + uint32_t u32Destp; ///< Start Address of DES Area (must be aligned to 32 Bit!) + boolean_t bSwInterruptEnable; ///< TRUE: Software Interrupt enabled + boolean_t bErInterruptEnable; ///< TRUE: Error Interrupt enabled + boolean_t bReadSkipBufferDisable; ///< TRUE: Read Skip Buffer disabled + boolean_t bErrorStopEnable; ///< TRUE: Enables Error Stop + en_dstc_swpr_t enSwTransferPriority; ///< see #en_dstc_swpr_t for details + boolean_t bTouchNvic; ///< TRUE: enable NVIC + func_ptr_t pfnNotifySwCallback; ///< Notification SW Callback Function Pointer + func_ptr_dstc_args_t pfnErrorCallback; ///< Error Status Callback + +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + func_ptr_t pfnDstcAdc0PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) + func_ptr_t pfnDstcAdc0ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + func_ptr_t pfnDstcAdc1PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) + func_ptr_t pfnDstcAdc1ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + func_ptr_t pfnDstcAdc2PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) + func_ptr_t pfnDstcAdc2ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + func_ptr_t pfnDstcBt0Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) + func_ptr_t pfnDstcBt0Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + func_ptr_t pfnDstcBt1Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) + func_ptr_t pfnDstcBt1Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + func_ptr_t pfnDstcBt2Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) + func_ptr_t pfnDstcBt2Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + func_ptr_t pfnDstcBt3Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) + func_ptr_t pfnDstcBt3Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + func_ptr_t pfnDstcBt4Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) + func_ptr_t pfnDstcBt4Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + func_ptr_t pfnDstcBt5Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) + func_ptr_t pfnDstcBt5Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + func_ptr_t pfnDstcBt6Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) + func_ptr_t pfnDstcBt6Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + func_ptr_t pfnDstcBt7Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) + func_ptr_t pfnDstcBt7Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) + func_ptr_t pfnDstcBt8Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) + func_ptr_t pfnDstcBt8Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) + func_ptr_t pfnDstcBt9Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) + func_ptr_t pfnDstcBt9Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) + func_ptr_t pfnDstcBt10Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) + func_ptr_t pfnDstcBt10Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) + func_ptr_t pfnDstcBt11Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) + func_ptr_t pfnDstcBt11Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) + func_ptr_t pfnDstcBt12Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) + func_ptr_t pfnDstcBt12Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) + func_ptr_t pfnDstcBt13Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) + func_ptr_t pfnDstcBt13Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) + func_ptr_t pfnDstcBt14Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) + func_ptr_t pfnDstcBt14Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ0) + func_ptr_t pfnDstcBt15Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ1) + func_ptr_t pfnDstcBt15Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + func_ptr_t pfnDstcExint0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + func_ptr_t pfnDstcExint1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + func_ptr_t pfnDstcExint2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + func_ptr_t pfnDstcExint3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + func_ptr_t pfnDstcExint4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + func_ptr_t pfnDstcExint5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + func_ptr_t pfnDstcExint6Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + func_ptr_t pfnDstcExint7Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + func_ptr_t pfnDstcExint8Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + func_ptr_t pfnDstcExint9Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + func_ptr_t pfnDstcExint10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + func_ptr_t pfnDstcExint11Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + func_ptr_t pfnDstcExint12Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + func_ptr_t pfnDstcExint13Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + func_ptr_t pfnDstcExint14Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + func_ptr_t pfnDstcExint15Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT16) + func_ptr_t pfnDstcExint16Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT17) + func_ptr_t pfnDstcExint17Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT18) + func_ptr_t pfnDstcExint18Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT19) + func_ptr_t pfnDstcExint19Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT20) + func_ptr_t pfnDstcExint20Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT21) + func_ptr_t pfnDstcExint21Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT22) + func_ptr_t pfnDstcExint22Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT23) + func_ptr_t pfnDstcExint23Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT24) + func_ptr_t pfnDstcExint24Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT25) + func_ptr_t pfnDstcExint25Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT26) + func_ptr_t pfnDstcExint26Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT27) + func_ptr_t pfnDstcExint27Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT28) + func_ptr_t pfnDstcExint28Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT29) + func_ptr_t pfnDstcExint29Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT30) + func_ptr_t pfnDstcExint30Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT31) + func_ptr_t pfnDstcExint31Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) + func_ptr_t pfnDstcHsspi0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_RX) + func_ptr_t pfnDstcHsspi0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_RX) + func_ptr_t pfnDstcI2cs0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_TX) + func_ptr_t pfnDstcI2cs0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S0_RX) + func_ptr_t pfnDstcI2s0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX) + func_ptr_t pfnDstcI2s0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) + func_ptr_t pfnDstcI2s1RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S1_TX) + func_ptr_t pfnDstcI2s1TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + func_ptr_t pfnDstcMfs0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + func_ptr_t pfnDstcMfs0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + func_ptr_t pfnDstcMfs1RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + func_ptr_t pfnDstcMfs1TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + func_ptr_t pfnDstcMfs2RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + func_ptr_t pfnDstcMfs2TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + func_ptr_t pfnDstcMfs3RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + func_ptr_t pfnDstcMfs3TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + func_ptr_t pfnDstcMfs4RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + func_ptr_t pfnDstcMfs4TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + func_ptr_t pfnDstcMfs5RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + func_ptr_t pfnDstcMfs5TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + func_ptr_t pfnDstcMfs6RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + func_ptr_t pfnDstcMfs6TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + func_ptr_t pfnDstcMfs7RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + func_ptr_t pfnDstcMfs7TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) + func_ptr_t pfnDstcMfs8RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) + func_ptr_t pfnDstcMfs8TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) + func_ptr_t pfnDstcMfs9RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) + func_ptr_t pfnDstcMfs9TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) + func_ptr_t pfnDstcMfs10RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) + func_ptr_t pfnDstcMfs10TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) + func_ptr_t pfnDstcMfs11RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) + func_ptr_t pfnDstcMfs11TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) + func_ptr_t pfnDstcMfs12RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) + func_ptr_t pfnDstcMfs12TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) + func_ptr_t pfnDstcMfs13RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) + func_ptr_t pfnDstcMfs13TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) + func_ptr_t pfnDstcMfs14RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) + func_ptr_t pfnDstcMfs14TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) + func_ptr_t pfnDstcMfs15RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) + func_ptr_t pfnDstcMfs15TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + func_ptr_t pfnDstcMft0Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + func_ptr_t pfnDstcMft0Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + func_ptr_t pfnDstcMft0Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + func_ptr_t pfnDstcMft0Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + func_ptr_t pfnDstcMft0Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + func_ptr_t pfnDstcMft0Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + func_ptr_t pfnDstcMft0Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + func_ptr_t pfnDstcMft0Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + func_ptr_t pfnDstcMft0Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + func_ptr_t pfnDstcMft0Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + func_ptr_t pfnDstcMft0Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + func_ptr_t pfnDstcMft0Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + func_ptr_t pfnDstcMft0Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + func_ptr_t pfnDstcMft0Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + func_ptr_t pfnDstcMft0Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + func_ptr_t pfnDstcMft0Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + func_ptr_t pfnDstcMft0Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + func_ptr_t pfnDstcMft0Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + func_ptr_t pfnDstcMft0Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) + func_ptr_t pfnDstcMft1Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) + func_ptr_t pfnDstcMft1Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) + func_ptr_t pfnDstcMft1Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) + func_ptr_t pfnDstcMft1Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + func_ptr_t pfnDstcMft1Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + func_ptr_t pfnDstcMft1Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) + func_ptr_t pfnDstcMft1Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) + func_ptr_t pfnDstcMft1Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) + func_ptr_t pfnDstcMft1Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) + func_ptr_t pfnDstcMft1Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) + func_ptr_t pfnDstcMft1Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) + func_ptr_t pfnDstcMft1Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) + func_ptr_t pfnDstcMft1Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) + func_ptr_t pfnDstcMft1Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) + func_ptr_t pfnDstcMft1Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) + func_ptr_t pfnDstcMft1Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) + func_ptr_t pfnDstcMft1Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) + func_ptr_t pfnDstcMft1Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) + func_ptr_t pfnDstcMft1Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) + func_ptr_t pfnDstcMft2Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) + func_ptr_t pfnDstcMft2Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) + func_ptr_t pfnDstcMft2Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) + func_ptr_t pfnDstcMft2Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + func_ptr_t pfnDstcMft2Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + func_ptr_t pfnDstcMft2Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) + func_ptr_t pfnDstcMft2Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) + func_ptr_t pfnDstcMft2Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) + func_ptr_t pfnDstcMft2Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) + func_ptr_t pfnDstcMft2Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) + func_ptr_t pfnDstcMft2Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) + func_ptr_t pfnDstcMft2Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) + func_ptr_t pfnDstcMft2Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) + func_ptr_t pfnDstcMft2Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) + func_ptr_t pfnDstcMft2Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) + func_ptr_t pfnDstcMft2Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) + func_ptr_t pfnDstcMft2Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) + func_ptr_t pfnDstcMft2Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) + func_ptr_t pfnDstcMft2Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + func_ptr_t pfnDstcPpg0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + func_ptr_t pfnDstcPpg2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + func_ptr_t pfnDstcPpg4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG8) + func_ptr_t pfnDstcPpg8Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG10) + func_ptr_t pfnDstcPpg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG12) + func_ptr_t pfnDstcPpg12Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG16) + func_ptr_t pfnDstcPpg16Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG18) + func_ptr_t pfnDstcPpg18Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG20) + func_ptr_t pfnDstcPpg20Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + func_ptr_t pfnDstcQprc0CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc0OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + func_ptr_t pfnDstcQprc0PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc0PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + func_ptr_t pfnDstcQprc0PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + func_ptr_t pfnDstcQprc0UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION) + func_ptr_t pfnDstcQprc1CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc1OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH) + func_ptr_t pfnDstcQprc1PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc1PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH) + func_ptr_t pfnDstcQprc1PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z) + func_ptr_t pfnDstcQprc1UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION) + func_ptr_t pfnDstcQprc2CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc2OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH) + func_ptr_t pfnDstcQprc2PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc2PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH) + func_ptr_t pfnDstcQprc2PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z) + func_ptr_t pfnDstcQprc2UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_COUNT_INVERSION) + func_ptr_t pfnDstcQprc3CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc3OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_MATCH) + func_ptr_t pfnDstcQprc3PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc3PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_RC_MATCH) + func_ptr_t pfnDstcQprc3PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_UFL_OFL_Z) + func_ptr_t pfnDstcQprc3UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP1) + func_ptr_t pfnDstcUsb0Ep1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP2) + func_ptr_t pfnDstcUsb0Ep2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP3) + func_ptr_t pfnDstcUsb0Ep3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP4) + func_ptr_t pfnDstcUsb0Ep4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP5) + func_ptr_t pfnDstcUsb0Ep5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP1) + func_ptr_t pfnDstcUsb1Ep1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP2) + func_ptr_t pfnDstcUsb1Ep2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP3) + func_ptr_t pfnDstcUsb1Ep3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP4) + func_ptr_t pfnDstcUsb1Ep4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP5) + func_ptr_t pfnDstcUsb1Ep5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_WC) + func_ptr_t pfnDstcWcCallback; +#endif +} stc_dstc_config_t; + +/// DSTC Intern Data +typedef struct stc_dstc_intern_data +{ + func_ptr_t pfnNotifySwCallback; ///< Notification SW Callback Function Pointer + func_ptr_dstc_args_t pfnErrorCallback; ///< Error Status Callback + +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + func_ptr_t pfnDstcAdc0PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) + func_ptr_t pfnDstcAdc0ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + func_ptr_t pfnDstcAdc1PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) + func_ptr_t pfnDstcAdc1ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + func_ptr_t pfnDstcAdc2PrioCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) + func_ptr_t pfnDstcAdc2ScanCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + func_ptr_t pfnDstcBt0Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) + func_ptr_t pfnDstcBt0Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + func_ptr_t pfnDstcBt1Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) + func_ptr_t pfnDstcBt1Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + func_ptr_t pfnDstcBt2Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) + func_ptr_t pfnDstcBt2Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + func_ptr_t pfnDstcBt3Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) + func_ptr_t pfnDstcBt3Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + func_ptr_t pfnDstcBt4Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) + func_ptr_t pfnDstcBt4Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + func_ptr_t pfnDstcBt5Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) + func_ptr_t pfnDstcBt5Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + func_ptr_t pfnDstcBt6Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) + func_ptr_t pfnDstcBt6Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + func_ptr_t pfnDstcBt7Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) + func_ptr_t pfnDstcBt7Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) + func_ptr_t pfnDstcBt8Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) + func_ptr_t pfnDstcBt8Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) + func_ptr_t pfnDstcBt9Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) + func_ptr_t pfnDstcBt9Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) + func_ptr_t pfnDstcBt10Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) + func_ptr_t pfnDstcBt10Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) + func_ptr_t pfnDstcBt11Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) + func_ptr_t pfnDstcBt11Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) + func_ptr_t pfnDstcBt12Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) + func_ptr_t pfnDstcBt12Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) + func_ptr_t pfnDstcBt13Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) + func_ptr_t pfnDstcBt13Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) + func_ptr_t pfnDstcBt14Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) + func_ptr_t pfnDstcBt14Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ0) + func_ptr_t pfnDstcBt15Irq0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ1) + func_ptr_t pfnDstcBt15Irq1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_CANFD) + func_ptr_t pfnDstcCanfdIrqCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + func_ptr_t pfnDstcExint0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + func_ptr_t pfnDstcExint1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + func_ptr_t pfnDstcExint2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + func_ptr_t pfnDstcExint3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + func_ptr_t pfnDstcExint4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + func_ptr_t pfnDstcExint5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + func_ptr_t pfnDstcExint6Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + func_ptr_t pfnDstcExint7Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + func_ptr_t pfnDstcExint8Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + func_ptr_t pfnDstcExint9Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + func_ptr_t pfnDstcExint10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + func_ptr_t pfnDstcExint11Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + func_ptr_t pfnDstcExint12Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + func_ptr_t pfnDstcExint13Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + func_ptr_t pfnDstcExint14Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + func_ptr_t pfnDstcExint15Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT16) + func_ptr_t pfnDstcExint16Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT17) + func_ptr_t pfnDstcExint17Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT18) + func_ptr_t pfnDstcExint18Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT19) + func_ptr_t pfnDstcExint19Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT20) + func_ptr_t pfnDstcExint20Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT21) + func_ptr_t pfnDstcExint21Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT22) + func_ptr_t pfnDstcExint22Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT23) + func_ptr_t pfnDstcExint23Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT24) + func_ptr_t pfnDstcExint24Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT25) + func_ptr_t pfnDstcExint25Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT26) + func_ptr_t pfnDstcExint26Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT27) + func_ptr_t pfnDstcExint27Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT28) + func_ptr_t pfnDstcExint28Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT29) + func_ptr_t pfnDstcExint29Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT30) + func_ptr_t pfnDstcExint30Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT31) + func_ptr_t pfnDstcExint31Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) + func_ptr_t pfnDstcHsspi0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_RX) + func_ptr_t pfnDstcHsspi0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_RX) + func_ptr_t pfnDstcI2cs0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_TX) + func_ptr_t pfnDstcI2cs0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S0_RX) + func_ptr_t pfnDstcI2s0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX) + func_ptr_t pfnDstcI2s0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) + func_ptr_t pfnDstcI2s1RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_I2S1_TX) + func_ptr_t pfnDstcI2s1TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + func_ptr_t pfnDstcMfs0RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + func_ptr_t pfnDstcMfs0TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + func_ptr_t pfnDstcMfs1RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + func_ptr_t pfnDstcMfs1TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + func_ptr_t pfnDstcMfs2RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + func_ptr_t pfnDstcMfs2TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + func_ptr_t pfnDstcMfs3RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + func_ptr_t pfnDstcMfs3TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + func_ptr_t pfnDstcMfs4RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + func_ptr_t pfnDstcMfs4TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + func_ptr_t pfnDstcMfs5RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + func_ptr_t pfnDstcMfs5TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + func_ptr_t pfnDstcMfs6RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + func_ptr_t pfnDstcMfs6TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + func_ptr_t pfnDstcMfs7RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + func_ptr_t pfnDstcMfs7TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) + func_ptr_t pfnDstcMfs8RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) + func_ptr_t pfnDstcMfs8TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) + func_ptr_t pfnDstcMfs9RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) + func_ptr_t pfnDstcMfs9TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) + func_ptr_t pfnDstcMfs10RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) + func_ptr_t pfnDstcMfs10TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) + func_ptr_t pfnDstcMfs11RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) + func_ptr_t pfnDstcMfs11TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) + func_ptr_t pfnDstcMfs12RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) + func_ptr_t pfnDstcMfs12TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) + func_ptr_t pfnDstcMfs13RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) + func_ptr_t pfnDstcMfs13TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) + func_ptr_t pfnDstcMfs14RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) + func_ptr_t pfnDstcMfs14TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) + func_ptr_t pfnDstcMfs15RxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) + func_ptr_t pfnDstcMfs15TxCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + func_ptr_t pfnDstcMft0Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + func_ptr_t pfnDstcMft0Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + func_ptr_t pfnDstcMft0Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + func_ptr_t pfnDstcMft0Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + func_ptr_t pfnDstcMft0Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + func_ptr_t pfnDstcMft0Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + func_ptr_t pfnDstcMft0Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + func_ptr_t pfnDstcMft0Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + func_ptr_t pfnDstcMft0Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + func_ptr_t pfnDstcMft0Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + func_ptr_t pfnDstcMft0Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + func_ptr_t pfnDstcMft0Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + func_ptr_t pfnDstcMft0Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + func_ptr_t pfnDstcMft0Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + func_ptr_t pfnDstcMft0Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + func_ptr_t pfnDstcMft0Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + func_ptr_t pfnDstcMft0Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + func_ptr_t pfnDstcMft0Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + func_ptr_t pfnDstcMft0Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) + func_ptr_t pfnDstcMft1Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) + func_ptr_t pfnDstcMft1Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) + func_ptr_t pfnDstcMft1Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) + func_ptr_t pfnDstcMft1Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + func_ptr_t pfnDstcMft1Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + func_ptr_t pfnDstcMft1Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) + func_ptr_t pfnDstcMft1Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) + func_ptr_t pfnDstcMft1Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) + func_ptr_t pfnDstcMft1Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) + func_ptr_t pfnDstcMft1Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) + func_ptr_t pfnDstcMft1Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) + func_ptr_t pfnDstcMft1Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) + func_ptr_t pfnDstcMft1Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) + func_ptr_t pfnDstcMft1Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) + func_ptr_t pfnDstcMft1Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) + func_ptr_t pfnDstcMft1Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) + func_ptr_t pfnDstcMft1Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) + func_ptr_t pfnDstcMft1Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) + func_ptr_t pfnDstcMft1Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) + func_ptr_t pfnDstcMft2Frt0PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) + func_ptr_t pfnDstcMft2Frt0ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) + func_ptr_t pfnDstcMft2Frt1PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) + func_ptr_t pfnDstcMft2Frt1ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + func_ptr_t pfnDstcMft2Frt2PeakCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + func_ptr_t pfnDstcMft2Frt2ZeroCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) + func_ptr_t pfnDstcMft2Icu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) + func_ptr_t pfnDstcMft2Icu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) + func_ptr_t pfnDstcMft2Icu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) + func_ptr_t pfnDstcMft2Icu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) + func_ptr_t pfnDstcMft2Ocu0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) + func_ptr_t pfnDstcMft2Ocu1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) + func_ptr_t pfnDstcMft2Ocu2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) + func_ptr_t pfnDstcMft2Ocu3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) + func_ptr_t pfnDstcMft2Ocu4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) + func_ptr_t pfnDstcMft2Ocu5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) + func_ptr_t pfnDstcMft2Wfg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) + func_ptr_t pfnDstcMft2Wfg32Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) + func_ptr_t pfnDstcMft2Wfg54Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PCRC) + func_ptr_t pfnDstcPcrcCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + func_ptr_t pfnDstcPpg0Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + func_ptr_t pfnDstcPpg2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + func_ptr_t pfnDstcPpg4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG8) + func_ptr_t pfnDstcPpg8Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG10) + func_ptr_t pfnDstcPpg10Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG12) + func_ptr_t pfnDstcPpg12Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG16) + func_ptr_t pfnDstcPpg16Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG18) + func_ptr_t pfnDstcPpg18Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_PPG20) + func_ptr_t pfnDstcPpg20Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + func_ptr_t pfnDstcQprc0CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc0OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + func_ptr_t pfnDstcQprc0PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc0PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + func_ptr_t pfnDstcQprc0PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + func_ptr_t pfnDstcQprc0UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION) + func_ptr_t pfnDstcQprc1CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc1OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH) + func_ptr_t pfnDstcQprc1PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc1PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH) + func_ptr_t pfnDstcQprc1PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z) + func_ptr_t pfnDstcQprc1UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION) + func_ptr_t pfnDstcQprc2CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc2OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH) + func_ptr_t pfnDstcQprc2PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc2PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH) + func_ptr_t pfnDstcQprc2PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z) + func_ptr_t pfnDstcQprc2UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_COUNT_INVERSION) + func_ptr_t pfnDstcQprc3CountInversionCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_OUT_OF_RANGE) + func_ptr_t pfnDstcQprc3OutOfRangeCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_MATCH) + func_ptr_t pfnDstcQprc3PcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_MATCH_RC_MATCH) + func_ptr_t pfnDstcQprc3PcMatchRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_PC_RC_MATCH) + func_ptr_t pfnDstcQprc3PcRcMatchCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC3_UFL_OFL_Z) + func_ptr_t pfnDstcQprc3UflOflZCallback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP1) + func_ptr_t pfnDstcUsb0Ep1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP2) + func_ptr_t pfnDstcUsb0Ep2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP3) + func_ptr_t pfnDstcUsb0Ep3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP4) + func_ptr_t pfnDstcUsb0Ep4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP5) + func_ptr_t pfnDstcUsb0Ep5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP1) + func_ptr_t pfnDstcUsb1Ep1Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP2) + func_ptr_t pfnDstcUsb1Ep2Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP3) + func_ptr_t pfnDstcUsb1Ep3Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP4) + func_ptr_t pfnDstcUsb1Ep4Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP5) + func_ptr_t pfnDstcUsb1Ep5Callback; +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_WC) + func_ptr_t pfnDstcWcCallback; +#endif +} stc_dstc_intern_data_t; +/** \} GroupDSTC_DataStructures */ +/** +* \addtogroup GroupDSTC_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +// extern en_result_t Dsctc_InitDescriptors( uint32_t u32Des0, ... ); +void Dstc_IrqHandler( void ); +en_result_t Dstc_ReleaseStandBy(void); +en_result_t Dstc_Init( const stc_dstc_config_t* pstcConfig ); +en_result_t Dstc_DeInit(boolean_t bTouchNvic); +en_result_t Dstc_SetHwdesp( uint8_t u8Channel, + uint16_t u16HwDesp ); +uint16_t Dstc_ReadHwdesp( uint8_t u8Channel ); +en_result_t Dstc_SetCommand( en_dstc_cmd_t enCommand ); +en_result_t Dstc_SwTrigger( uint16_t u16SwDesPointer ); +en_result_t Dstc_SwTrqansferStartStatus( void ); +en_result_t Dstc_SetDreqenb( stc_dstc_dreqenb_t* pstcDreqenb ); +en_result_t Dstc_ReadDreqenb( stc_dstc_dreqenb_t* pstcDreqenb ); +en_result_t Dstc_SetDreqenbBit( uint8_t u8BitPos ); +en_result_t Dstc_ClearDreqenbBit( uint8_t u8BitPos ); +en_result_t Dstc_ReadHwint( stc_dstc_hwint_t* pstcHwint ); +en_result_t Dstc_SetHwintclr( stc_dstc_hwintclr_t* pstcHwintclr ); +boolean_t Dstc_ReadHwintBit( uint8_t u8BitPos ); +en_result_t Dstc_SetHwintclrBit( uint8_t u8BitPos ); +en_result_t Dstc_ReadDqmsk( stc_dstc_dqmsk_t* pstcDqmsk ); +en_result_t Dstc_SetDqmskclr( stc_dstc_dqmskclr_t* pstcDqmskclr ); +en_result_t Dstc_SetDqmskclrBit( uint8_t u8BitPos ); + +#if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) || (PDL_ON == PDL_DSTC_ENABLE_ADC0_SCAN) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) || (PDL_ON == PDL_DSTC_ENABLE_ADC1_SCAN) || \ + (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) || (PDL_ON == PDL_DSTC_ENABLE_ADC2_SCAN) +void Dstc_AdcIrqHandler(uint8_t u8IrqChannel0, uint8_t u8IrqChannel1); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ1) || \ + (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) || (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ1) +void Dstc_BtIrqHandler(uint8_t u8IrqChannel0, uint8_t u8IrqChannel1); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_CANFD) +void Dstc_CanfdIrqHandler(uint8_t u8IrqChannel0); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) || (PDL_ON == PDL_DSTC_ENABLE_EXINT1) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT2) || (PDL_ON == PDL_DSTC_ENABLE_EXINT3) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT4) || (PDL_ON == PDL_DSTC_ENABLE_EXINT5) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT6) || (PDL_ON == PDL_DSTC_ENABLE_EXINT7) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT8) || (PDL_ON == PDL_DSTC_ENABLE_EXINT9) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT10) || (PDL_ON == PDL_DSTC_ENABLE_EXINT11) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT12) || (PDL_ON == PDL_DSTC_ENABLE_EXINT13) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT14) || (PDL_ON == PDL_DSTC_ENABLE_EXINT15) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT16) || (PDL_ON == PDL_DSTC_ENABLE_EXINT17) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT18) || (PDL_ON == PDL_DSTC_ENABLE_EXINT19) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT20) || (PDL_ON == PDL_DSTC_ENABLE_EXINT21) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT22) || (PDL_ON == PDL_DSTC_ENABLE_EXINT23) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT24) || (PDL_ON == PDL_DSTC_ENABLE_EXINT25) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT26) || (PDL_ON == PDL_DSTC_ENABLE_EXINT27) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT28) || (PDL_ON == PDL_DSTC_ENABLE_EXINT29) || \ + (PDL_ON == PDL_DSTC_ENABLE_EXINT30) || (PDL_ON == PDL_DSTC_ENABLE_EXINT31) +void Dstc_ExintIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) || (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_RX) +void Dstc_HsspiIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_TX) || (PDL_ON == PDL_DSTC_ENABLE_I2CS0_RX) +void Dstc_I2csIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX) || (PDL_ON == PDL_DSTC_ENABLE_I2S0_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_I2S1_TX) || (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) +void Dstc_I2sIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) || (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) +void Dstc_MfsRxIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) || (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) +void Dstc_MfsTxIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) +void Dstc_MftFrtPeakIrqHandler(uint8_t u8IrqChannel); +#endif + + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) +void Dstc_MftFrtZeroIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) +void Dstc_MftOcuIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) +void Dstc_MftWfgIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) || \ + (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) || (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) +void Dstc_MftIcuIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_PCRC) +void Dstc_PcrcIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_PPG0) || (PDL_ON == PDL_DSTC_ENABLE_PPG2) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG4) || (PDL_ON == PDL_DSTC_ENABLE_PPG8) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG4) || (PDL_ON == PDL_DSTC_ENABLE_PPG8) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG10) || (PDL_ON == PDL_DSTC_ENABLE_PPG12) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG16) || (PDL_ON == PDL_DSTC_ENABLE_PPG18) || \ + (PDL_ON == PDL_DSTC_ENABLE_PPG20) +void Dstc_PpgIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH) || \ + (PDL_ON == PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z) +void Dstc_QprcIrqHandler(uint8_t u8IrqChannel); +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP1) + #error USB0 EP1 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP2) + #error USB0 EP2 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP3) + #error US0B EP3 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP4) + #error USB0 EP4 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB0_EP5) + #error USB0 EP5 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP1) + #error USB1 EP1 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP2) + #error USB1 EP2 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP3) + #error USB1 EP3 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP4) + #error USB1 EP4 DSTC function not implemented yet! +#endif +#if (PDL_ON == PDL_DSTC_ENABLE_USB1_EP5) + #error USB1 EP5 DSTC function not implemented yet! +#endif + +#if (PDL_ON == PDL_DSTC_ENABLE_WC) +void Dstc_WcIrqHandler(void); +#endif + +/** \} GroupDSTC_Functions */ +/** \} GroupDSTC */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_DSTC_ACTIVE)) + +#endif /* __DSTC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.c new file mode 100644 index 0000000000..56299a7fea --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.c @@ -0,0 +1,986 @@ +/******************************************************************************* +* \file dt.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the DT +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "dt/dt.h" + +#if (defined(PDL_PERIPHERAL_DT_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled DT instances and their internal data +static stc_dt_instance_data_t m_astcDtInstanceDataLut[DtInstanceIndexMax] = +{ +#if (PDL_PERIPHERAL_ENABLE_DT0 == PDL_ON) + { + &DT0, /* pstcInstance */ + {{0u,0u}} /* stcInternData (not initialized yet) */ + } +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +typedef union stc_dt_timerXcontrol_field +{ + volatile uint32_t stcTIMER1CTRL; + volatile stc_dt_timer1control_field_t stcTIMER1CTRL_f; + volatile uint32_t stcTIMER2CTRL; + volatile stc_dt_timer2control_field_t stcTIMER2CTRL_f; +}stc_dt_timerXcontrol_field_t; + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_dt_intern_data_t* DtGetInternDataPtr(volatile stc_dtn_t** ppstcDt, + uint8_t u8Ch); +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) +static void DtInitNvic(void); +static void DtDeInitNvic(void); +#endif + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** \brief Check pointer to Dual Timer instance and enable channel + ** + ** \param [in,out] ppstcDt Pointer of pointer to Dual Timer instance register area + ** \param [in] u8Channel Channel number + ** + ** \retval Pointer to internal data or NULL if instance is not enabled. + ** (or channel is invalid) + ** + ******************************************************************************/ +static stc_dt_intern_data_t* DtGetInternDataPtr(volatile stc_dtn_t** ppstcDt, + uint8_t u8Channel) +{ + stc_dt_intern_data_t* pstcDtInternData = NULL; + uint32_t u32Instance; + + /* check for channel */ + if ((NULL != ppstcDt) + && (NULL != *ppstcDt) + && (DtMaxChannels > u8Channel) + ) + { + /* Get ptr to internal data struct ... */ + for (u32Instance = 0; u32Instance < (uint32_t)DtInstanceIndexMax; u32Instance++) + { + if (*ppstcDt == m_astcDtInstanceDataLut[u32Instance].pstcInstance) + { + /* Set actual address of register list of current channel */ + *ppstcDt = &((*ppstcDt)[u8Channel]); + pstcDtInternData = &m_astcDtInstanceDataLut[u32Instance].stcInternData; + break; + } + } + } + + return (pstcDtInternData); +} /* DtGetInternDataPtr */ + +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl.h + ** + ******************************************************************************/ +static void DtInitNvic(void) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(DT_IRQn); + NVIC_EnableIRQ(DT_IRQn); + NVIC_SetPriority(DT_IRQn, PDL_IRQ_LEVEL_DT0); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(DT_QPRC0_2_IRQn); + NVIC_EnableIRQ(DT_QPRC0_2_IRQn); + NVIC_SetPriority(DT_QPRC0_2_IRQn, PDL_IRQ_LEVEL_DT_QPRC); +#else +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(WC_RTC_DT_IRQn); + NVIC_EnableIRQ(WC_RTC_DT_IRQn); + NVIC_SetPriority(WC_RTC_DT_IRQn, PDL_IRQ_LEVEL_DT_RTC_WC); +#elif (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + NVIC_ClearPendingIRQ(DT_IRQn); + NVIC_EnableIRQ(DT_IRQn); + NVIC_SetPriority(DT_IRQn, PDL_IRQ_LEVEL_DT); +#else + NVIC_ClearPendingIRQ(DT_QPRC_IRQn); + NVIC_EnableIRQ(DT_QPRC_IRQn); + NVIC_SetPriority(DT_QPRC_IRQn, PDL_IRQ_LEVEL_DT_QPRC); +#endif +#endif +} /* Dt_InitIrq */ + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ******************************************************************************/ +static void DtDeInitNvic(void) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(DT_IRQn); + NVIC_DisableIRQ(DT_IRQn); + NVIC_SetPriority(DT_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(DT_QPRC0_2_IRQn); + NVIC_DisableIRQ(DT_QPRC0_2_IRQn); + NVIC_SetPriority(DT_QPRC0_2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(WC_RTC_DT_IRQn); + NVIC_DisableIRQ(WC_RTC_DT_IRQn); + NVIC_SetPriority(WC_RTC_DT_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + NVIC_ClearPendingIRQ(DT_IRQn); + NVIC_DisableIRQ(DT_IRQn); + NVIC_SetPriority(DT_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + NVIC_ClearPendingIRQ(DT_QPRC_IRQn); + NVIC_DisableIRQ(DT_QPRC_IRQn); + NVIC_SetPriority(DT_QPRC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +#endif +} /* Dt_DeInitIrq */ + +/** + ***************************************************************************** + ** \brief ISR callback for DT (channel 0 and 1) + ** + ** This callbacks are called by the global DT ISR whenever an DT triggers an + ** interrupt (on channel 0 and/or 1). It calls the callback functions that + ** has been given during Dt initialization (see Dt_Init() and + ** #stc_dt_channel_config_t) for each channel individually. If the pointer + ** to a callback function is NULL, no call is performed. + ** + ** The active interrupt request flags are cleared by the ISR + ** + ** \param [in] u8Channel Channel number + ** + *****************************************************************************/ +void DtIrqHandler1() +{ + volatile stc_dtn_t* pstcDt; + stc_dt_intern_data_t* pstcDtInternData; + + pstcDt = &DT0; + pstcDtInternData = &m_astcDtInstanceDataLut[0].stcInternData; + + if (TRUE == pstcDt->TIMER1RIS_f.TIMER1RIS) /* Timer 0 interrupt? */ + { + pstcDt->TIMER1INTCLR = 0u; /* Clear interrupt */ + + /* Check for callback function pointer */ + if (NULL != pstcDtInternData->pfnIrqCallbackIntern[0]) + { + pstcDtInternData->pfnIrqCallbackIntern[0]() ; + } + } +} /* DtIrqHandler */ + + +/** + ***************************************************************************** + ** \brief ISR callback for DT (channel 0 and 1) + ** + ** This callbacks are called by the global DT ISR whenever an DT triggers an + ** interrupt (on channel 0 and/or 1). It calls the callback functions that + ** has been given during Dt initialization (see Dt_Init() and + ** #stc_dt_channel_config_t) for each channel individually. If the pointer + ** to a callback function is NULL, no call is performed. + ** + ** The active interrupt request flags are cleared by the ISR + ** + ** \param [in] u8Channel Channel number + ** + *****************************************************************************/ +void DtIrqHandler2() +{ + volatile stc_dtn_t* pstcDt; + stc_dt_intern_data_t* pstcDtInternData; + + pstcDt = &DT0; + pstcDtInternData = &m_astcDtInstanceDataLut[0].stcInternData; + + if (TRUE == pstcDt->TIMER2RIS_f.TIMER2RIS) /* Timer 0 interrupt? */ + { + pstcDt->TIMER1INTCLR = 0u; /* Clear interrupt */ + + /* Check for callback function pointer */ + if (NULL != pstcDtInternData->pfnIrqCallbackIntern[0]) + { + pstcDtInternData->pfnIrqCallbackIntern[0]() ; + } + } +} /* DtIrqHandler */ +#endif + + +/** + ***************************************************************************** + ** \brief Initialize DT + ** + ** This function initializes the specified channel of Dual Timer. + ** + ** \param [in] pstcConfig Dual timer configuration + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcConfig == NULL + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** - one or more enumerated values in pstcDt out of enumaration + ** + *****************************************************************************/ +en_result_t Dt_Init(const stc_dt_channel_config_t* pstcConfig, + uint8_t u8Channel + ) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + + + stc_dt_timerXcontrol_field_t stcTIMERXCTRL; + PDL_ZERO_STRUCT(stcTIMERXCTRL); + + pstcDt = &DT0; + /*-------- Initialize internal data -------*/ + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if ((NULL == pstcDtInternData) + || (NULL == pstcConfig) + ) + { + enResult = ErrorInvalidParameter; + } + else + { + enResult = Ok; + /*-------- Configure the DT timer -------*/ + if(DtChannel0 == u8Channel) + { + pstcDt->TIMER1CONTROL = 0u; /* Disable DT TIMER1 */ + } + else + { + pstcDt->TIMER2CONTROL = 0u; /* Disable DT TIMER2 */ + } + + /* Set Timer Mode */ + switch (pstcConfig->u8Mode) + { + /* Free run mode */ + case DtFreeRun: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERMODE = FALSE; + stcTIMERXCTRL.stcTIMER1CTRL_f.ONESHOT = FALSE; + break; + /* Periodic mode */ + case DtPeriodic: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERMODE = TRUE; + stcTIMERXCTRL.stcTIMER1CTRL_f.ONESHOT = FALSE; + break; + /* One shot mode */ + case DtOneShot: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERMODE = FALSE; + stcTIMERXCTRL.stcTIMER1CTRL_f.ONESHOT = TRUE; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + + /* Set Prescaler */ + switch (pstcConfig->u8PrescalerDiv) + { + /* Clock/1 */ + case DtPrescalerDiv1: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERPRE = DT_PRE_TIMER_DIV_1; + break; + /* Clock/16 */ + case DtPrescalerDiv16: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERPRE = DT_PRE_TIMER_DIV_16; + break; + /* Clock/256 */ + case DtPrescalerDiv256: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERPRE = DT_PRE_TIMER_DIV_256; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + + /* Set Counter Size */ + switch (pstcConfig->u8CounterSize) + { + /* 16bit */ + case DtCounterSize16: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERSIZE = FALSE; + break; + /* 32bit */ + case DtCounterSize32: + stcTIMERXCTRL.stcTIMER1CTRL_f.TIMERSIZE = TRUE; + break; + default: + enResult = ErrorInvalidParameter; + break; + } +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) + /* Set interrupt */ + if(pstcConfig->bIrqEnable == TRUE) + { + stcTIMERXCTRL.stcTIMER1CTRL_f.INTENABLE = 1u; + } + + /* Set interrupt callback function */ + pstcDtInternData->pfnIrqCallbackIntern[u8Channel] = pstcConfig->pfnIrqCallback; + + /* Set NVIC */ + if(pstcConfig->bTouchNvic == TRUE) + { + DtInitNvic(); + } +#endif + } + + if (Ok == enResult) + { + /* Set control register */ + if(DtChannel0 == u8Channel) + { + pstcDt->TIMER1CONTROL = stcTIMERXCTRL.stcTIMER1CTRL; + } + else + { + pstcDt->TIMER2CONTROL = stcTIMERXCTRL.stcTIMER2CTRL; + } + } + + return (enResult); +} /* Dt_Init */ + +/** + ***************************************************************************** + ** \brief De-Initialize DT + ** + ** This function de-initializes the specified channel of Dual Timer. + ** Dt-DeInit() accesses the DT hardware register. They are reset. + ** + ** \param [in] u8Channel Channel number + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcDt == NULL + ** - u8Ch >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + *****************************************************************************/ +en_result_t Dt_DeInit(uint8_t u8Channel, boolean_t bTouchNvic) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + pstcDt = &DT0; + /*-------- Initialize internal data -------*/ + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL == pstcDtInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + if(DtChannel0 == u8Channel) + { + /* Clear all registers */ + pstcDt->TIMER1CONTROL = 0u; + + pstcDt->TIMER1LOAD = 0u; + pstcDt->TIMER1INTCLR = 1u; + pstcDt->TIMER1BGLOAD = 0u; + +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) + /* Clear callback */ + pstcDtInternData->pfnIrqCallbackIntern[u8Channel] = NULL; + + if(bTouchNvic == TRUE) + { + DtDeInitNvic(); + } +#endif + enResult = Ok; + } + else if(DtChannel1 == u8Channel) + { + /* Clear all registers */ + pstcDt->TIMER2CONTROL = 0u; + + pstcDt->TIMER2LOAD = 0u; + pstcDt->TIMER2INTCLR = 1u; + pstcDt->TIMER2BGLOAD = 0u; + +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) + /* Clear callback */ + pstcDtInternData->pfnIrqCallbackIntern[u8Channel] = NULL; + + if(bTouchNvic == TRUE) + { + DtDeInitNvic(); + } +#endif + enResult = Ok; + } + else + { + enResult = ErrorInvalidParameter; + } + } + + return (enResult); +} /* Dt_DeInit */ + +/** + ***************************************************************************** + ** \brief Enable Timer Counter + ** + ** This function enables the timer counter. + ** + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + *****************************************************************************/ +en_result_t Dt_EnableCount(uint8_t u8Channel) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Enable timer counter */ + if ( DtChannel0 == u8Channel ) + { + pstcDt->TIMER1CONTROL_f.TIMEREN = TRUE; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + pstcDt->TIMER2CONTROL_f.TIMEREN = TRUE; + enResult = Ok; + } + + } + + return (enResult); +} /* Dt_EnableCount */ + +/** + ***************************************************************************** + ** \brief Disable Timer Counter + ** + ** This function disables the timer counter. + ** + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + *****************************************************************************/ +en_result_t Dt_DisableCount(uint8_t u8Channel) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Disable timer counter */ + if ( DtChannel0 == u8Channel ) + { + pstcDt->TIMER1CONTROL_f.TIMEREN = FALSE; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + pstcDt->TIMER2CONTROL_f.TIMEREN = FALSE; + enResult = Ok; + } + } + + return (enResult); +} /* Dt_DisableCount */ + +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) +/** + ***************************************************************************** + ** \brief Enable Interrupt + ** + ** This function enables the interruption. + ** + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + *****************************************************************************/ +en_result_t Dt_EnableIrq(uint8_t u8Channel) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Enable interrupt */ + if ( DtChannel0 == u8Channel ) + { + pstcDt->TIMER1CONTROL_f.INTENABLE = TRUE; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + pstcDt->TIMER2CONTROL_f.INTENABLE = TRUE; + enResult = Ok; + } + } + return (enResult); +} /* Dt_EnableIrq */ + +/** + ***************************************************************************** + ** \brief Disable Interrupt + ** + ** This function disables the interruption. + ** + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + *****************************************************************************/ +en_result_t Dt_DisableIrq(uint8_t u8Channel) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Disable interrupt */ + if ( DtChannel0 == u8Channel ) + { + pstcDt->TIMER1CONTROL_f.INTENABLE = FALSE; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + pstcDt->TIMER2CONTROL_f.INTENABLE = FALSE; + enResult = Ok; + } + + } + + return (enResult); +} /* Dt_DisableIrq */ +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt status + ** The Function can return the interrupt status (TimerXRIS) + ** + ** \param [in] u8Channel Channel number + ** + ** \retval boolean_t:the interrupt status + ** + ******************************************************************************/ +boolean_t Dt_GetIrqFlag(uint8_t u8Channel) +{ + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + boolean_t bRetVal = FALSE; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Check the interrupt status */ + if ( DtChannel0 == u8Channel ) + { + if (TRUE == pstcDt->TIMER1RIS_f.TIMER1RIS) + { + bRetVal = TRUE; + } + } + else if ( DtChannel1 == u8Channel ) + { + if (TRUE == pstcDt->TIMER2RIS_f.TIMER2RIS) + { + bRetVal = TRUE; + } + } + } + + return (bRetVal); +} /* Dt_GetIrqFlag */ + +/** + ****************************************************************************** + ** \brief Get mask interrupt status + ** The Function can return the mask interrupt status (TimerXMIS) + ** + ** \param [in] u8Channel Channel number + ** + ** \retval boolean_t:the mask interrupt status + ** + ******************************************************************************/ +boolean_t Dt_GetMaskIrqFlag(uint8_t u8Channel) +{ + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + boolean_t bRetVal = FALSE; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Check the mask interrupt status */ + if ( DtChannel0 == u8Channel ) + { + if (TRUE == pstcDt->TIMER1MIS_f.TIMER1MIS) + { + bRetVal = TRUE; + } + } + else if ( DtChannel1 == u8Channel ) + { + if (TRUE == pstcDt->TIMER2MIS_f.TIMER2MIS) + { + bRetVal = TRUE; + } + } + } + + return (bRetVal); +} /* Dt_GetMaskIrqFlag */ + +/** + ****************************************************************************** + ** \brief Clear interrupt status + ** The Function clears the interrupt status + ** + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + ******************************************************************************/ +en_result_t Dt_ClrIrqFlag(uint8_t u8Channel) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Clear the interrupt status */ + if ( DtChannel0 == u8Channel ) + { + pstcDt->TIMER1INTCLR = 1; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + pstcDt->TIMER2INTCLR = 1; + enResult = Ok; + } + } + + return (enResult); +} /* Dt_ClrIrqFlag */ + +/** + ****************************************************************************** + ** \brief Write load value + ** The Function writes the load value to load register + ** + ** \param [in] u32LoadVal Load value to set to load register + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + ******************************************************************************/ +en_result_t Dt_WriteLoadVal(uint32_t u32LoadVal, + uint8_t u8Channel + ) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* 16bit mode */ + if ( DtChannel0 == u8Channel ) + { + if (FALSE == pstcDt->TIMER1CONTROL_f.TIMERSIZE) + { + u32LoadVal &= 0x0000FFFFu; + } + /* Write load value to register */ + pstcDt->TIMER1LOAD = u32LoadVal; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + if (FALSE == pstcDt->TIMER2CONTROL_f.TIMERSIZE) + { + u32LoadVal &= 0x0000FFFFu; + } + /* Write load value to register */ + pstcDt->TIMER2LOAD = u32LoadVal; + enResult = Ok; + } + } + + return (enResult); +} /* Dt_WriteLoadVal */ + +/** + ****************************************************************************** + ** \brief Write back-ground load value + ** The Function writes the load value to back-ground load register + ** + ** \param [in] u32BgLoadVal Load value to set to back-ground load register + ** \param [in] u8Channel Channel number + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Channel >= DtMaxChannels + ** - pstcDtInternData == NULL (invalid or disabled DT unit + ** (PDL_PERIPHERAL_ENABLE_DT)) + ** + ******************************************************************************/ +en_result_t Dt_WriteBgLoadVal(uint32_t u32BgLoadVal, + uint8_t u8Channel + ) +{ + en_result_t enResult; + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + enResult = ErrorInvalidParameter; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* 16bit mode */ + if ( DtChannel0 == u8Channel ) + { + if (FALSE == pstcDt->TIMER1CONTROL_f.TIMERSIZE) + { + u32BgLoadVal &= 0x0000FFFFu; + } + /* Write back-ground load value to register */ + pstcDt->TIMER1BGLOAD = u32BgLoadVal; + enResult = Ok; + } + else if ( DtChannel1 == u8Channel ) + { + if (FALSE == pstcDt->TIMER2CONTROL_f.TIMERSIZE) + { + u32BgLoadVal &= 0x0000FFFFu; + } + /* Write back-ground load value to register */ + pstcDt->TIMER2BGLOAD = u32BgLoadVal; + enResult = Ok; + } + } + + return (enResult); +} /* Dt_WriteBgLoadVal */ + +/** + ****************************************************************************** + ** \brief Read current count value + ** The Function reads the value from value register + ** + ** \param [in] u8Channel Channel number + ** + ** \retval uint32_t:current counter value + ** + ******************************************************************************/ +uint32_t Dt_ReadCurCntVal(uint8_t u8Channel) +{ + /* Pointer to Dual Timer instance register area */ + volatile stc_dtn_t* pstcDt; + uint32_t u32DtValue = 0; + /* Pointer to internal data */ + stc_dt_intern_data_t* pstcDtInternData; + + pstcDt = &DT0; + /* Get pointer to internal data structure and check channel... */ + pstcDtInternData = DtGetInternDataPtr(&pstcDt, u8Channel); + /* ... and check for NULL */ + if (NULL != pstcDtInternData) + { + /* Read current count value */ + if ( DtChannel0 == u8Channel ) + { + u32DtValue = pstcDt->TIMER1VALUE; + /* 16bit mode */ + if (FALSE == pstcDt->TIMER1CONTROL_f.TIMERSIZE) + { + u32DtValue &= 0x0000FFFFu; + } + } + else if ( DtChannel1 == u8Channel ) + { + u32DtValue = pstcDt->TIMER2VALUE; + /* 16bit mode */ + if (FALSE == pstcDt->TIMER2CONTROL_f.TIMERSIZE) + { + u32DtValue &= 0x0000FFFFu; + } + } + } + + return (u32DtValue); +} /* Dt_ReadCurCntVal */ + +#endif /* #if (defined(PDL_PERIPHERAL_DT_ACTIVE)) */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.h new file mode 100644 index 0000000000..7133da382b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/dt/dt.h @@ -0,0 +1,287 @@ +/******************************************************************************* +* \file dt.h +* +* \version 1.20 +* +* \brief Headerfile for DT functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __DT_H__ +#define __DT_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_DT_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupDT Dual Timer (DT) +* \{ +* \defgroup GroupDT_Macros Macros +* \defgroup GroupDT_Functions Functions +* \defgroup GroupDT_DataStructures Data Structures +* \defgroup GroupDT_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupDT +* \{ +* The Dual Timer implements two programmable 32-/16-bit Down Counters, called timer channels. +* You can use a counter in one of three timer modes:
+* − Free-running mode. +* The counter operates continuously and wraps around to its maximum value each +* time that it reaches zero.
+* − Periodic mode. +* The counter is reloaded and operates continuously each time +* that it reaches zero.
+* − One-shot mode. +* The counter stops when it reaches zero.
+* You can write a count value to a timer. If the timer is running, the counter +* restarts immediately using the new value. When running in periodic mode, you +* can also write a count value to a buffer (background). When the timer reaches zero, +* it uses this background value as the new count value.
+* The counters have a common timer clock (TIMCLK). The source for TIMCLK is the APB bus clock +* (PCLK). Each counter also has a prescaler +* that can divide TIMCLK by 1, 16, or 256, so you can control the count rate of each independently.
+* To calculate the timer frequency, use the formula: +* Timer_Frequency = Clock_Frequency / Count_Value
+* Where Clock_Frequency is the divided clock frequency, and Count_Value is the initial value of the +* counter. For example, if the divided clock frequency is 40 MHz, and the counter is set to 1,000,000, +* then the timer frequency will be 40 Hz.
+* +* \section SectionDT_ConfigurationConsideration Configuration Consideration +* To set up DT, you provide configuration parameters in the #stc_dt_channel_config_t +* structure. Then call Dt_Init(), where the second parameter is the number of +* channel you use. Use Dt_EnableCount() to start the counter, and Dt_DisableCount() to stop it.
+* Call Dt_WriteLoadVal() to set a new count value immediately. Use +* Dt_WriteBgLoadVal() to load the background value for the next counting period. This works only in periodic mode. It has no effect on free-running or one-shot mode.
+* Use Dt_ReadCurCntVal() to get the current counter value.
+* +* +* \note Before calling Dt_DeInit(), you should +* disable all channels via Dt_DisableCount() and Dt_DisableIrq(), to avoid a +* possible, unwanted interrupt. +* +* \section SectionDT_MoreInfo More Information +* For more information on the DT peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* +*/ + +/** +* \addtogroup GroupDT_Macros +* \{ +*/ + +/******************************************************************************* +* Global definitions +*******************************************************************************/ +#define DT0 (*((volatile stc_dtn_t *) FM_DT_BASE)) + +/* for TimerPre of TimerXControl */ +#define DT_PRE_TIMER_DIV_1 (0x00) +#define DT_PRE_TIMER_DIV_16 (0x01) +#define DT_PRE_TIMER_DIV_256 (0x02) + +/** \} GroupDT_Macros */ + +/** +* \addtogroup GroupDT_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + + /** + ****************************************************************************** + ** \brief Dt mode + ** + ** To select between Free-run, Periodic, and One-Shot mode + ******************************************************************************/ +typedef enum en_dt_mode +{ + DtFreeRun = 0u, ///< Free-running mode + DtPeriodic = 1u, ///< Periodic mode + DtOneShot = 2u ///< One-shot mode +} en_dt_mode_t; + +/** + ****************************************************************************** + ** \brief Dt Prescaler + ** + ** To select clock divider + ******************************************************************************/ +typedef enum en_dt_prescaler +{ + DtPrescalerDiv1 = 0u, ///< Prescaler divisor 1 + DtPrescalerDiv16 = 1u, ///< Prescaler divisor 16 + DtPrescalerDiv256 = 2u ///< Prescaler divisor 256 +} en_dt_prescaler_t; + +/** + ****************************************************************************** + ** \brief Dt Counter Size + ** + ** To select the size of the counter + ******************************************************************************/ +typedef enum en_dt_countersize +{ + DtCounterSize16 = 0u, ///< 16 Bit counter size + DtCounterSize32 = 1u ///< 32 Bit counter size +} en_dt_countersize_t; + +/** + ****************************************************************************** + ** \brief Dt channel number + ******************************************************************************/ +typedef enum en_dt_channel +{ + DtChannel0 = 0u, ///< channel 0 + DtChannel1 = 1u, ///< channel 1 + DtMaxChannels = 2u ///< Number of channels +} en_dt_channel_t; +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/// Enumeration to define an index for each enabled Dual timer instance +typedef enum en_dt_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_DT0 == PDL_ON) + DtInstanceIndexDt0 = 0u, +#endif + DtInstanceIndexMax +} en_dt_instance_index_t; + +/** \} GroupDT_Types */ + +/** +* \addtogroup GroupDT_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Redefinition of DT register structure + ******************************************************************************/ +typedef FM_DT_TypeDef stc_dtn_t; + +/** + ***************************************************************************** + ** \brief Dt channel configuration + ** + ** The DT configuration is done on a per channel basis + *****************************************************************************/ +typedef struct stc_dt_channel_config +{ + uint8_t u8Mode; ///< Mode, see description of #en_dt_mode_t + uint8_t u8PrescalerDiv; ///< Prescaler, see description of #en_dt_prescaler_t + uint8_t u8CounterSize; ///< Counter size, see description of #en_dt_countersize_t +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) + boolean_t bIrqEnable; ///< TRUE: enable interrupt, FALSE: disable interrupt + func_ptr_t pfnIrqCallback; ///< Pointer to interrupt callback function + boolean_t bTouchNvic; ///< TRUE: enable MVIC, FALSE: don't enable NVIC +#endif +} stc_dt_channel_config_t; + +/// Datatype for holding internal data needed for DT +typedef struct stc_dt_intern_data +{ + /// Callback for interrupts of DT channel 0 + func_ptr_t pfnIrqCallbackIntern[DtMaxChannels] ; +} stc_dt_intern_data_t ; + +/// DT instance data type +typedef struct stc_dt_instance_data +{ + volatile stc_dtn_t* pstcInstance; ///< pointer to registers of an instance + stc_dt_intern_data_t stcInternData; ///< module internal data of instance +} stc_dt_instance_data_t; + +/** \} GroupDT_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupDT_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_DT0 == PDL_ON) + /* External function */ + void DtIrqHandler1(void); + void DtIrqHandler2(void); + #define DtIrqHandler(u8Channel) (((u8Channel) == (0)) ? ( DtIrqHandler1() ) : ( DtIrqHandler2() )) + en_result_t Dt_EnableIrq (uint8_t u8Channel); + en_result_t Dt_DisableIrq(uint8_t u8Channel); +#endif + +/* Init/Deinit */ +en_result_t Dt_Init(const stc_dt_channel_config_t* pstcConfig, + uint8_t u8Channel); +en_result_t Dt_DeInit(uint8_t u8Channel, boolean_t bTouchNvic); + +/* Function Enable/Disable */ +en_result_t Dt_EnableCount(uint8_t u8Channel); +en_result_t Dt_DisableCount(uint8_t u8Channel); + +/* Get/Clr irq flag */ +boolean_t Dt_GetIrqFlag(uint8_t u8Channel); +boolean_t Dt_GetMaskIrqFlag(uint8_t u8Channel); +en_result_t Dt_ClrIrqFlag(uint8_t u8Channel); + +/* Write/Read count value */ +en_result_t Dt_WriteLoadVal(uint32_t u32LoadVal, + uint8_t u8Channel); +en_result_t Dt_WriteBgLoadVal(uint32_t u32BgLoadVal, + uint8_t u8Channel); +uint32_t Dt_ReadCurCntVal(uint8_t u8Channel); + +/** \} GroupDT_Functions */ +/** \} GroupDT */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_DT_ACTIVE)) */ + +#endif /* __DT_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.c new file mode 100644 index 0000000000..70edf4b951 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.c @@ -0,0 +1,933 @@ +/******************************************************************************* +* \file exint.c +* +* \version 1.30 +* +* \brief External Interrupts driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "exint/exint.h" + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) +stc_exint_intern_data_t stcExintInternData; + +const uint8_t cau8ExintReferenceLut[PDL_EXINT_CHANNELS + 1] = +{ +#if (PDL_INTERRUPT_ENABLE_EXINT0 == PDL_ON) + 0u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT1 == PDL_ON) + 1u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT2 == PDL_ON) + 2u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT3 == PDL_ON) + 3u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT4 == PDL_ON) + 4u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT5 == PDL_ON) + 5u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT6 == PDL_ON) + 6u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT7 == PDL_ON) + 7u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT8 == PDL_ON) + 8u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT9 == PDL_ON) + 9u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT10 == PDL_ON) + 10u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT11 == PDL_ON) + 11u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT12 == PDL_ON) + 12u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT13 == PDL_ON) + 13u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT14 == PDL_ON) + 14u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT15 == PDL_ON) + 15u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT16 == PDL_ON) + 16u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT17 == PDL_ON) + 17u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT18 == PDL_ON) + 18u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT19 == PDL_ON) + 19u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT20 == PDL_ON) + 20u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT21 == PDL_ON) + 21u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT22 == PDL_ON) + 22u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT23 == PDL_ON) + 23u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT24 == PDL_ON) + 24u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT25 == PDL_ON) + 25u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT26 == PDL_ON) + 26u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT27 == PDL_ON) + 27u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT28 == PDL_ON) + 28u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT29 == PDL_ON) + 29u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT30 == PDL_ON) + 30u, +#endif +#if (PDL_INTERRUPT_ENABLE_EXINT31 == PDL_ON) + 31u, +#endif + 255u // End of table +}; + +#endif + +#if (defined(PDL_PERIPHERAL_NMI_ACTIVE)) +stc_exint_nmi_intern_data_t stcExintNMIInternData; +#endif + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +#if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) + +/** + ****************************************************************************** + ** \brief Return the internal reference index of an Exint channel + ** + ** \param u8Channel Exint channel number + ** + ** \return uint8_t Reference index (255 if not found or u8Channel > 31) + ** + ******************************************************************************/ +static uint8_t ExintGetInternDataIdx(uint8_t u8Channel) +{ + uint8_t u8Index; + + if (u8Channel > 31u) + { + return 255u; + } + + for (u8Index = 0u; u8Index < PDL_EXINT_CHANNELS; u8Index++) + { + if (u8Channel == cau8ExintReferenceLut[u8Index]) + { + return u8Index; + } + } + + return 255u; // Should never happen ... +} + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Interrupt handlers for External interrupts 0 + ** + ** This function clears the cause bit and calls the callback function, if + ** specified. + ******************************************************************************/ +void Exint_IrqHandler(uint8_t u8Channel) +{ + uint8_t u8Reference; + + u8Reference = ExintGetInternDataIdx(u8Channel); + + FM_EXTI->EICL &= (0xFFFFFFFFu ^ (1ul << u8Channel)); + + if (0u != stcExintInternData.apfnExintCallback[u8Reference]) + { + /* [andreika]: pass channel as parameter */ + stcExintInternData.apfnExintCallback[u8Reference](u8Channel); + } +} // Exint_IrqHandler + +/** + ****************************************************************************** + ** \brief Init External Interrupts + ** + ** This function initializes the external interrupts according the given + ** configuration. + ** + ** \param [in] pstcConfig EXINT configuration parameters + ** + ** \retval Ok EXINT initialized + ** \retval ErrorInvalidParameter pstcConfig == NULL or Illegal mode + ******************************************************************************/ +en_result_t Exint_Init( const stc_exint_config_t* pstcConfig) +{ + uint8_t u8Index; + uint8_t u8Reference; + uint32_t u32Elvr; + uint32_t u32Elvr1; +#if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + uint32_t u32Elvr2; +#endif + uint32_t u32Enir; + + u32Elvr = 0u; + u32Elvr1 = 0u; +#if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + u32Elvr2 = 0u; +#endif + u32Enir = 0u; + + if ( NULL == pstcConfig ) + { + return ErrorInvalidParameter; + } + + for (u8Index = 0u; u8Index < PDL_EXINT_INSTANCE_COUNT; u8Index++) + { + u8Reference = cau8ExintReferenceLut[u8Index]; + + if(1u == pstcConfig->abEnable[u8Index]) + { + if (u8Reference < 16u) + { + switch (pstcConfig->aenLevel[u8Index]) + { + case ExIntLowLevel: + break; // bits remain 2'b00 + case ExIntHighLevel: + u32Elvr |= 1u << (2u * u8Reference); + break; + case ExIntRisingEdge: + u32Elvr |= 2u << (2u * u8Reference); + break; + case ExIntFallingEdge: + u32Elvr |= 3u << (2u * u8Reference); + break; + #if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + case ExIntBothEdge: + u32Elvr2 |= 1u << (u8Reference); + break; + #endif + default: + return ErrorInvalidParameter; + } + } + else + { + switch (pstcConfig->aenLevel[u8Index]) + { + case ExIntLowLevel: + break; // bits remain 2'b00 + case ExIntHighLevel: + u32Elvr1 |= 1u << (2u * (u8Reference - 16u)); + break; + case ExIntRisingEdge: + u32Elvr1 |= 2u << (2u * (u8Reference - 16u)); + break; + case ExIntFallingEdge: + u32Elvr1 |= 3u << (2u * (u8Reference - 16u)); + break; + #if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + case ExIntBothEdge: + u32Elvr2 |= 1u << (u8Reference); + break; + #endif + default: + return ErrorInvalidParameter; + } + } + u32Enir |= 1ul << u8Reference; + } + else + { + u32Enir &= ~(1ul << u8Reference); + } + stcExintInternData.apfnExintCallback[u8Index] = pstcConfig->apfnExintCallback[u8Index]; + } + + // update hardware + FM_EXTI->ELVR = u32Elvr; + FM_EXTI->ELVR1 = u32Elvr1; +#if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + FM_EXTI->ELVR2 = u32Elvr2; +#endif + FM_EXTI->EICL = 0u; // Clear all possible interrupts due to level change + FM_EXTI->ENIR = u32Enir; + + if(TRUE == pstcConfig->bTouchNvic) + { +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + NVIC_ClearPendingIRQ(EXINT0_1_IRQn); + NVIC_SetPriority(EXINT0_1_IRQn, PDL_IRQ_LEVEL_EXINT0_1); + NVIC_EnableIRQ(EXINT0_1_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + NVIC_ClearPendingIRQ(EXINT2_3_IRQn); + NVIC_SetPriority(EXINT2_3_IRQn, PDL_IRQ_LEVEL_EXINT2_3); + NVIC_EnableIRQ(EXINT2_3_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + NVIC_ClearPendingIRQ(EXINT4_5_IRQn); + NVIC_SetPriority(EXINT4_5_IRQn, PDL_IRQ_LEVEL_EXINT4_5); + NVIC_EnableIRQ(EXINT4_5_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_ClearPendingIRQ(EXINT6_7_IRQn); + NVIC_SetPriority(EXINT6_7_IRQn, PDL_IRQ_LEVEL_EXINT6_7); + NVIC_EnableIRQ(EXINT6_7_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + NVIC_ClearPendingIRQ(EXINT8_IRQn); + NVIC_SetPriority(EXINT8_IRQn, PDL_IRQ_LEVEL_EXINT8); + NVIC_EnableIRQ(EXINT8_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + NVIC_ClearPendingIRQ(EXINT12_13_IRQn); + NVIC_SetPriority(EXINT12_13_IRQn, PDL_IRQ_LEVEL_EXINT12_13); + NVIC_EnableIRQ(EXINT12_13_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + NVIC_ClearPendingIRQ(EXINT15_IRQn); + NVIC_SetPriority(EXINT15_IRQn, PDL_IRQ_LEVEL_EXINT15); + NVIC_EnableIRQ(EXINT15_IRQn); + #endif +#else + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_ClearPendingIRQ(EXINT0_7_IRQn); + NVIC_SetPriority(EXINT0_7_IRQn, PDL_IRQ_LEVEL_EXINT0_7); + NVIC_EnableIRQ(EXINT0_7_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + NVIC_ClearPendingIRQ(EXINT8_23_IRQn); + NVIC_SetPriority(EXINT8_23_IRQn, PDL_IRQ_LEVEL_EXINT8_23); + NVIC_EnableIRQ(EXINT8_23_IRQn); + #endif +#endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_ClearPendingIRQ(EXINT0_7_IRQn); + NVIC_SetPriority(EXINT0_7_IRQn, PDL_IRQ_LEVEL_EXINT0_7); + NVIC_EnableIRQ(EXINT0_7_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + NVIC_ClearPendingIRQ(EXINT8_31_IRQn); + NVIC_SetPriority(EXINT8_31_IRQn, PDL_IRQ_LEVEL_EXINT8_31); + NVIC_EnableIRQ(EXINT8_31_IRQn); + #endif +#else +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + NVIC_ClearPendingIRQ(EXINT0_IRQn); + NVIC_SetPriority(EXINT0_IRQn, PDL_IRQ_LEVEL_EXINT0); + NVIC_EnableIRQ(EXINT0_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + NVIC_ClearPendingIRQ(EXINT1_IRQn); + NVIC_SetPriority(EXINT1_IRQn, PDL_IRQ_LEVEL_EXINT1); + NVIC_EnableIRQ(EXINT1_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + NVIC_ClearPendingIRQ(EXINT2_IRQn); + NVIC_SetPriority(EXINT2_IRQn, PDL_IRQ_LEVEL_EXINT2); + NVIC_EnableIRQ(EXINT2_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + NVIC_ClearPendingIRQ(EXINT3_IRQn); + NVIC_SetPriority(EXINT3_IRQn, PDL_IRQ_LEVEL_EXINT3); + NVIC_EnableIRQ(EXINT3_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + NVIC_ClearPendingIRQ(EXINT4_IRQn); + NVIC_SetPriority(EXINT4_IRQn, PDL_IRQ_LEVEL_EXINT4); + NVIC_EnableIRQ(EXINT4_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + NVIC_ClearPendingIRQ(EXINT5_IRQn); + NVIC_SetPriority(EXINT5_IRQn, PDL_IRQ_LEVEL_EXINT5); + NVIC_EnableIRQ(EXINT5_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + NVIC_ClearPendingIRQ(EXINT6_IRQn); + NVIC_SetPriority(EXINT6_IRQn, PDL_IRQ_LEVEL_EXINT6); + NVIC_EnableIRQ(EXINT6_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_ClearPendingIRQ(EXINT7_IRQn); + NVIC_SetPriority(EXINT7_IRQn, PDL_IRQ_LEVEL_EXINT7); + NVIC_EnableIRQ(EXINT7_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + NVIC_ClearPendingIRQ(EXINT8_IRQn); + NVIC_SetPriority(EXINT8_IRQn, PDL_IRQ_LEVEL_EXINT8); + NVIC_EnableIRQ(EXINT8_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + NVIC_ClearPendingIRQ(EXINT9_IRQn); + NVIC_SetPriority(EXINT9_IRQn, PDL_IRQ_LEVEL_EXINT9); + NVIC_EnableIRQ(EXINT9_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + NVIC_ClearPendingIRQ(EXINT10_IRQn); + NVIC_SetPriority(EXINT10_IRQn, PDL_IRQ_LEVEL_EXINT10); + NVIC_EnableIRQ(EXINT10_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + NVIC_ClearPendingIRQ(EXINT11_IRQn); + NVIC_SetPriority(EXINT11_IRQn, PDL_IRQ_LEVEL_EXINT11); + NVIC_EnableIRQ(EXINT11_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + NVIC_ClearPendingIRQ(EXINT12_IRQn); + NVIC_SetPriority(EXINT12_IRQn, PDL_IRQ_LEVEL_EXINT12); + NVIC_EnableIRQ(EXINT12_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + NVIC_ClearPendingIRQ(EXINT13_IRQn); + NVIC_SetPriority(EXINT13_IRQn, PDL_IRQ_LEVEL_EXINT13); + NVIC_EnableIRQ(EXINT13_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + NVIC_ClearPendingIRQ(EXINT14_IRQn); + NVIC_SetPriority(EXINT14_IRQn, PDL_IRQ_LEVEL_EXINT14); + NVIC_EnableIRQ(EXINT14_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + NVIC_ClearPendingIRQ(EXINT15_IRQn); + NVIC_SetPriority(EXINT15_IRQn, PDL_IRQ_LEVEL_EXINT15); + NVIC_EnableIRQ(EXINT15_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + NVIC_ClearPendingIRQ(EXINT16_19_IRQn); + NVIC_SetPriority(EXINT16_19_IRQn, PDL_IRQ_LEVEL_EXINT16_17_18_19); + NVIC_EnableIRQ(EXINT16_19_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + NVIC_ClearPendingIRQ(EXINT20_23_IRQn); + NVIC_SetPriority(EXINT20_23_IRQn, PDL_IRQ_LEVEL_EXINT20_21_22_23); + NVIC_EnableIRQ(EXINT20_23_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + NVIC_ClearPendingIRQ(EXINT24_27_IRQn); + NVIC_SetPriority(EXINT24_27_IRQn, PDL_IRQ_LEVEL_EXINT24_25_26_27); + NVIC_EnableIRQ(EXINT24_27_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + NVIC_ClearPendingIRQ(EXINT28_31_IRQn); + NVIC_SetPriority(EXINT28_31_IRQn, PDL_IRQ_LEVEL_EXINT28_29_30_31); + NVIC_EnableIRQ(EXINT28_31_IRQn); +#endif +#endif + } + + return Ok; +} // Exint_DisableChannel + +/** + ****************************************************************************** + ** \brief Init External Interrupts + ** + ** This function de-initializes all external interrupts. + ** + ** \retval Ok EXINT sucessful disabled + ******************************************************************************/ +en_result_t Exint_DeInit(void) +{ + FM_EXTI->ENIR = 0; // Disable all channels + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + NVIC_SetPriority(EXINT0_1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT0_1_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + NVIC_SetPriority(EXINT2_3_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT2_3_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + NVIC_SetPriority(EXINT4_5_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT4_5_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_SetPriority(EXINT6_7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT6_7_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + NVIC_SetPriority(EXINT8_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT8_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + NVIC_SetPriority(EXINT12_13_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT12_13_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + NVIC_SetPriority(EXINT15_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT15_IRQn); + #endif +#else + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_SetPriority(EXINT0_7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT0_7_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + NVIC_SetPriority(EXINT8_23_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT8_23_IRQn); + #endif +#endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_SetPriority(EXINT0_7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT0_7_IRQn); + #endif + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + NVIC_SetPriority(EXINT8_31_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT8_31_IRQn); + #endif +#else + // Disable interrupts +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + NVIC_SetPriority(EXINT0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT0_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + NVIC_SetPriority(EXINT1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT1_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + NVIC_SetPriority(EXINT2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT2_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + NVIC_SetPriority(EXINT3_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT3_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + NVIC_SetPriority(EXINT4_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT4_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + NVIC_SetPriority(EXINT5_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT5_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + NVIC_SetPriority(EXINT6_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT6_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + NVIC_SetPriority(EXINT7_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT7_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + NVIC_SetPriority(EXINT8_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT8_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + NVIC_SetPriority(EXINT9_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT9_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + NVIC_SetPriority(EXINT10_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT10_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + NVIC_SetPriority(EXINT11_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT11_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + NVIC_SetPriority(EXINT12_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT12_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + NVIC_SetPriority(EXINT13_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT13_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + NVIC_SetPriority(EXINT14_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT14_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + NVIC_SetPriority(EXINT15_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + NVIC_DisableIRQ(EXINT15_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + NVIC_SetPriority(EXINT16_19_IRQn, PDL_IRQ_LEVEL_EXINT16_17_18_19); + NVIC_DisableIRQ(EXINT16_19_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + NVIC_SetPriority(EXINT20_23_IRQn, PDL_IRQ_LEVEL_EXINT20_21_22_23); + NVIC_DisableIRQ(EXINT20_23_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + NVIC_SetPriority(EXINT24_27_IRQn, PDL_IRQ_LEVEL_EXINT24_25_26_27); + NVIC_DisableIRQ(EXINT24_27_IRQn); +#endif +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + NVIC_SetPriority(EXINT28_31_IRQn, PDL_IRQ_LEVEL_EXINT28_29_30_31); + NVIC_DisableIRQ(EXINT28_31_IRQn); +#endif +#endif + + return Ok; +} // Exint_DeInit + +/** + ****************************************************************************** + ** \brief Enable a single External Interrupt + ** + ** This function enables a single External Interrupt. + ** + ** \note This function does not set + ** stc_exint_config_t#abEnable[u8Channel]! + ** + ** \param [in] u8Channel External Interrupt channel number + ** + ** \retval Ok Channel enabled + ** \retval ErrorInvalidParameter Invalid channel number + ******************************************************************************/ +en_result_t Exint_EnableChannel(uint8_t u8Channel) +{ + if (u8Channel > 32) + { + return ErrorInvalidParameter; + } + + FM_EXTI->EICL &= 0xFFFFFFFFu ^ (1u << u8Channel); + FM_EXTI->ENIR |= 1u << u8Channel; + + return Ok; + +} // Exint_EnableChannel + +/** + ****************************************************************************** + ** \brief Disable a single External Interrupt + ** + ** This function disables a single External Interrupt. + ** + ** \note This function does not clear + ** stc_exint_config_t#abEnable[u8Channel]! + ** + ** \param [in] u8Channel External Interrupt channel number + ** + ** \retval Ok Channel enabled + ** \retval ErrorInvalidParameter Invalid channel number or channel + ******************************************************************************/ +en_result_t Exint_DisableChannel(uint8_t u8Channel) +{ + if (u8Channel > 32) + { + return ErrorInvalidParameter; + } + + FM_EXTI->ENIR &= (1u << u8Channel) ^ 0xFFFFFFFFu; + + return Ok; +} // Exint_DisableChannel + +/** + ****************************************************************************** + ** \brief Set external interrupt detect mode + ** + ** \param u8Channel 0~31 + ** \param enLevel + ** \arg ExIntLowLevel Low level is active edge for interrupt detection + ** \arg ExIntHighLevel High level is active edge for interrupt detection + ** \arg ExIntRisingEdge Rising edge is active edge for interrupt detection + ** \arg ExIntFallingEdge Falling edge is active edge for interrupt detection + ** + ** \retval Ok Interreupt detection edge set normmally + ** \retval ErrorInvalidParameter u8Ch > EXINT_MAX_CH_INDEX + ** invalid setting for enLevel + ** + ******************************************************************************/ +en_result_t Exint_SetDetectMode(uint8_t u8Channel, en_exint_level_t enLevel) +{ + if((u8Channel + 1) > PDL_EXINT_CHANNELS) + { + return ErrorInvalidParameter; + } + + switch (enLevel) + { + case ExIntLowLevel: + case ExIntHighLevel: + case ExIntRisingEdge: + case ExIntFallingEdge: + #if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + FM_EXTI->ELVR2 &= ~(1ul << u8Channel); + #endif + if (u8Channel < 16) + { + FM_EXTI->ELVR &= ~(3ul << (2u * u8Channel)); + FM_EXTI->ELVR |= ((uint8_t)enLevel<<(2u * u8Channel)); + } + else + { + FM_EXTI->ELVR1 &= ~(3ul << (2u * (u8Channel - 16u))); + FM_EXTI->ELVR1 |= ((uint8_t)enLevel<<(2u * (u8Channel - 16u))); + } + break; + #if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + case ExIntBothEdge: + FM_EXTI->ELVR2 |= (1ul << u8Channel); + break; + #endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get the external interrupt detection mode + ** + ** \param u8Channel 0~31 + ** + ** \retval ExIntLowLevel Low level is active edge for interrupt detection + ** \retval ExIntHighLevel High level is active edge for interrupt detection + ** \retval ExIntRisingEdge Rising edge is active edge for interrupt detection + ** \retval ExIntFallingEdge Falling edge is active edge for interrupt detection + ** + ******************************************************************************/ +en_exint_level_t Exint_GetDetectMode(uint8_t u8Channel) +{ + uint8_t u8Level; + u8Level = (FM_EXTI->ELVR & (3ul<<(2u * u8Channel))) >> (2u * u8Channel); + return (en_exint_level_t)u8Level; +} + +#endif // #if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) + +#if (defined(PDL_PERIPHERAL_NMI_ACTIVE)) + +/** + ****************************************************************************** + ** \brief Interrupt handler for None-Maskable Interrupt (NMI) + ** + ** This function clears the cause bit and calls the NMI callback function, if + ** specified. + ******************************************************************************/ +void Exint_Nmi_IrqHandler(void) +{ + if ((FM_EXTI->NMIRR & 0x01u) == 0x01u) + { + FM_EXTI->NMICL = 0u; + + if (0u != stcExintNMIInternData.pfnNmiCallback) + { + stcExintNMIInternData.pfnNmiCallback(); + } + } +} + +/** + ****************************************************************************** + ** \brief Init Non-Maskable Interrupt (NMI) + ** + ** This function initializes the NMI according to the given + ** configuration. + ** + ** \param [in] pstcConfig NMI configuration parameters + ** + ** \retval Ok NMI initialized + ** \retval ErrorInvalidParameter pstcConfig == NULL + ** + ******************************************************************************/ +en_result_t Exint_Nmi_Init(stc_exint_nmi_config_t* pstcConfig) +{ + if ( pstcConfig == NULL ) + { + return ErrorInvalidParameter ; + } + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + FM_EXTI->NMIENR = 0x01; // Enable NMI +#endif + + // Set internal data + stcExintNMIInternData.pfnNmiCallback = pstcConfig->pfnNmiCallback; + + return Ok; +} // Exint_Nmi_Init + +/** + ****************************************************************************** + ** \brief De-Init Non-Maskable Interrupt (NMI) + ** + ** This function de-initializes the NMI according to the given + ** configuration. + ** + ** \param [in] pstcConfig NMI configuration parameters + ** + ** \retval Ok NMI initialized + ** \retval ErrorInvalidParameter pstcConfig == NULL + ** + ******************************************************************************/ +en_result_t Exint_Nmi_DeInit(stc_exint_nmi_config_t* pstcConfig) +{ + if ( pstcConfig == NULL ) + { + return ErrorInvalidParameter ; + } + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + FM_EXTI->NMIENR = 0x00; // Disable NMI +#endif + + // Set internal data + stcExintNMIInternData.pfnNmiCallback = NULL; + + return Ok; +} // Exint_Nmi_DeInit + +#endif // #if (defined(PDL_PERIPHERAL_NMI_ACTIVE)) + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.h new file mode 100644 index 0000000000..18c6b6ec8d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/exint/exint.h @@ -0,0 +1,390 @@ +/******************************************************************************* +* \file exint.h +* +* \version 1.30 +* +* \brief Headerfile for External Interrupts functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __EXINT_H__ +#define __EXINT_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) || \ + (defined(PDL_PERIPHERAL_NMI_ACTIVE)) + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupEXINT External Interrupts (EXINT) +* \{ +* \defgroup GroupEXINT_Macros Macros +* \defgroup GroupEXINT_Functions Functions +* \defgroup GroupEXINT_GlobalVariables Global Variables +* \defgroup GroupEXINT_DataStructures Data Structures +* \defgroup GroupEXINT_Types Enumerated Types +* \} +*/ +/** +* \addtogroup GroupEXINT +* \{ +* The External Interrupt (EXINT) peripheral enables you to set up a response to an external +* interrupt. There are 32 possible external interrupts, corresponding to physical pins designated +* INT00-INT031. Check the schematic for your hardware to see which interrupt pins are available.
+* For each of the 32 possible interrupts you can:
+* - Enable or disable the interrupt
+* - Set the detection condition (level) that triggers the interrupt
+* - Provide the callback routine to handle the interrupt
+* You set the level from these choices: +* - High level
+* - Low level
+* - Rising edge
+* - Falling edge
+* - Both rising edge and falling edges (Certain processors only).
+* The EXINT peripheral also manages non-maskable interrupts (NMI). An +* NMI interrupt request is sent to the CPU if the edge or level is detected +* from the signal input to the NMI input pin. The edge or level varies depending +* on the state of the system, and is not configurable:
+* - Run mode: Falling edge
+* - Sleep mode: Falling edge
+* - Timer mode: Low level
+* - RTC mode: Low level
+* - Stop mode: Low level
+* - Deep standby mode: NMI request is not available in this mode
+* +* \section SectionEXINT_ConfigurationConsideration Configuration Consideration +* External Interrupts
+* You set fields in the stc_exint_config_t structure to enable an external interrupt, +* specify the detect level, and specify the callback routine. To do so you set individual +* bits and bitfields. A sample code snippet that configures the response to pin INT00 might look like this:
+* myConfig.abEnable[ExintInstanceIndexExint0] = 1u; // enabled
+* myConfig. aenLevel[ExintInstanceIndexExint0] = ExIntFallingEdge;
+* myConfig.apfnExintCallback[ExintInstanceIndexExint0] = MyCallback;
+* You configure the response to any or all 32 interrupts in this one configuration structure.
+* Call Exint_Init() to initialize and enable all interrupts you have configured.
+* After initializing, you can control single channels independently. Use Exint_DisableChannel() +* and Exint_EnableChannel(). You can change the detect mode with Exint_SetDetectMode().
+* Call Exint_DeInit() to disable all external interrupts.
+* NMI
+* Specify the interrupt handler routine in the stc_exint_nmi_config_t structure. Then call Exint_Nmi_Init(). +* This initializes and enables the NMI. Call Exint_NMI_DeInit() to disable NMI handling.
+* +* \section SectionEXINT_MoreInfo More Information +* For more information on the EXINT peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem TRM.pdf
+* FM4 Peripheral Manual Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupEXINT_Macros +* \{ +*/ +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define PDL_EXINT_CHANNELS (32u) +#define PDL_EXINT_INSTANCE_COUNT (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT0 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT1 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT2 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT3 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT4 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT5 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT6 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT7 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT8 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT9 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT10 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT11 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT12 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT13 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT14 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT15 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT16 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT17 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT18 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT19 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT20 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT21 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT22 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT23 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT24 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT25 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT26 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT27 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT28 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT29 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT30 == PDL_ON) + \ + (uint8_t)(PDL_INTERRUPT_ENABLE_EXINT31 == PDL_ON) + +/** \} GroupEXINT_Macros */ + +/** +* \addtogroup GroupEXINT_Types +* \{ +*/ +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +typedef enum en_exint_level +{ + ExIntLowLevel = 0u, ///< "L" level detection + ExIntHighLevel = 1u, ///< "H" level detection + ExIntRisingEdge = 2u, ///< Rising edge detection + ExIntFallingEdge = 3u, ///< Falling edge detection +#if (PDL_MCU_TYPE == PDL_FM4_TYPE5) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + ExIntBothEdge = 4u, ///< Both edge detection +#endif +} en_exint_level_t; + +/// Enumeration to define an index for each enabled external interrupt instance +typedef enum en_exint_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_EXINT0 == PDL_ON) + ExintInstanceIndexExint0, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT1 == PDL_ON) + ExintInstanceIndexExint1, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT2 == PDL_ON) + ExintInstanceIndexExint2, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT3 == PDL_ON) + ExintInstanceIndexExint3, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT4 == PDL_ON) + ExintInstanceIndexExint4, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT5 == PDL_ON) + ExintInstanceIndexExint5, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT6 == PDL_ON) + ExintInstanceIndexExint6, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT7 == PDL_ON) + ExintInstanceIndexExint7, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT8 == PDL_ON) + ExintInstanceIndexExint8, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT9 == PDL_ON) + ExintInstanceIndexExint9, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT10 == PDL_ON) + ExintInstanceIndexExint10, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT11 == PDL_ON) + ExintInstanceIndexExint11, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT12 == PDL_ON) + ExintInstanceIndexExint12, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT13 == PDL_ON) + ExintInstanceIndexExint13, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT14 == PDL_ON) + ExintInstanceIndexExint14, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT15 == PDL_ON) + ExintInstanceIndexExint15, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT16 == PDL_ON) + ExintInstanceIndexExint16, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT17 == PDL_ON) + ExintInstanceIndexExint17, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT18 == PDL_ON) + ExintInstanceIndexExint18, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT19 == PDL_ON) + ExintInstanceIndexExint19, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT20 == PDL_ON) + ExintInstanceIndexExint20, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT21 == PDL_ON) + ExintInstanceIndexExint21, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT22 == PDL_ON) + ExintInstanceIndexExint22, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT23 == PDL_ON) + ExintInstanceIndexExint23, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT24 == PDL_ON) + ExintInstanceIndexExint24, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT25 == PDL_ON) + ExintInstanceIndexExint25, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT26 == PDL_ON) + ExintInstanceIndexExint26, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT27 == PDL_ON) + ExintInstanceIndexExint27, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT28 == PDL_ON) + ExintInstanceIndexExint28, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT29 == PDL_ON) + ExintInstanceIndexExint29, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT30 == PDL_ON) + ExintInstanceIndexExint30, + #endif + #if (PDL_PERIPHERAL_ENABLE_EXINT31 == PDL_ON) + ExintInstanceIndexExint31, + #endif + ExintInstanceIndexMax +} en_exint_instance_index_t; + +/** \}GroupEXINT_Types */ + +/** +* \addtogroup GroupEXINT_DataStructures +* \{ +*/ +/** + ****************************************************************************** + ** \brief EXINT configuration + ******************************************************************************/ + +#if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) +/** + ***************************************************************************** + ** \brief External Interrupt configuration + ** + ** The EXINT configuration + *****************************************************************************/ +typedef struct stc_exint_config +{ + boolean_t abEnable[PDL_EXINT_INSTANCE_COUNT]; ///< TRUE: External Interrupt enable + en_exint_level_t aenLevel[PDL_EXINT_INSTANCE_COUNT]; ///< level detection, see #en_exint_level_t for details + /* [andreika]: func_ptr_t -> func_ptr_arg1_t */ + func_ptr_arg1_t apfnExintCallback[PDL_EXINT_INSTANCE_COUNT]; ///< Callback pointers + boolean_t bTouchNvic; ///< TRUE: Enable NVIC, FALSE: don't enable NVIC, + +} stc_exint_config_t; + +/** + ****************************************************************************** + ** \brief Datatype for holding internal data needed for EXINT + ******************************************************************************/ +typedef struct stc_exint_intern_data +{ + /* [andreika]: func_ptr_t -> func_ptr_arg1_t */ + func_ptr_arg1_t apfnExintCallback[PDL_EXINT_INSTANCE_COUNT]; ///< Callback pointer array +} stc_exint_intern_data_t ; +#endif + +#if (defined(PDL_PERIPHERAL_NMI_ACTIVE)) +/** + ***************************************************************************** + ** \brief NMI configuration + ** + ** The NMI configuration + *****************************************************************************/ +typedef struct stc_exint_nmi_config +{ + func_ptr_t pfnNmiCallback; ///< NMI Callback pointers +} stc_exint_nmi_config_t; + +/** + ****************************************************************************** + ** \brief Datatype for holding internal data needed for NMI + ******************************************************************************/ +typedef struct stc_exint_nmi_intern_data +{ + func_ptr_t pfnNmiCallback; ///< Callback pointer +} stc_exint_nmi_intern_data_t ; +#endif + +/** \} GroupEXINT_DataStructures */ + +/** +* \addtogroup GroupEXINT_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +#if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) +extern stc_exint_intern_data_t stcExintInternData; +#endif +#if (defined(PDL_PERIPHERAL_NMI_ACTIVE)) +extern stc_exint_nmi_intern_data_t stcExintNMIInternData; +#endif + +/** \} GroupEXINT_GlobalVariables */ + +/** +* \addtogroup GroupEXINT_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) +void Exint_IrqHandler(uint8_t u8Channel) ; + +en_result_t Exint_Init(const stc_exint_config_t* pstcConfig) ; + +en_result_t Exint_DeInit(void) ; + +en_result_t Exint_EnableChannel(uint8_t u8Channel) ; + +en_result_t Exint_DisableChannel(uint8_t u8Channel) ; + +en_result_t Exint_SetDetectMode(uint8_t u8Channel, en_exint_level_t enLevel); + +en_exint_level_t Exint_GetDetectMode(uint8_t u8Channel); +#endif +#if (defined(PDL_PERIPHERAL_NMI_ACTIVE)) +void Exint_Nmi_IrqHandler(void) ; + +en_result_t Exint_Nmi_Init(stc_exint_nmi_config_t* pstcConfig) ; + +en_result_t Exint_Nmi_DeInit(stc_exint_nmi_config_t* pstcConfig) ; +#endif + +/** \} GroupEXINT_Functions */ +/** \} GroupEXINT */ +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_EXINT_ACTIVE)) + +#endif /* __EXINT_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.c new file mode 100644 index 0000000000..cece2b2e68 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.c @@ -0,0 +1,634 @@ +/******************************************************************************* +* \file extif.c +* +* \version 1.50 +* +* \brief External Bus Interface driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "extif/extif.h" + +#if (defined(PDL_PERIPHERAL_EXTIF_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM4_CORE) +stc_extif_intern_data_t stcExtifInternData; +#endif + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief External Bus Interface Error Interrupt Service Routine + ** + ** This function provides the user callback functions, if defined. + ** + ******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM4_CORE) +void Extif_IrqHandler( void ) +{ + if ((TRUE == stcExtifInternData.bSdramErrorInterruptEnable) && + (stcExtifInternData.pfnSdramErrorCallback != NULL)) + { + if (1u == FM_EXBUS->MEMCERR_f.SDER) + { + FM_EXBUS->MEMCERR_f.SDER = 1u; // Clear SDRAM error interrupt + stcExtifInternData.pfnSdramErrorCallback(); + } + } + + if ((TRUE == stcExtifInternData.bSramFlashErrorInterruptEnable) && + (stcExtifInternData.pfnSramFlashErrorCallback != NULL)) + { + if (1u == FM_EXBUS->MEMCERR_f.SFER) + { + FM_EXBUS->MEMCERR_f.SFER = 1u; // Clear SRAM/Flash error interrupt + stcExtifInternData.pfnSramFlashErrorCallback(); + } + } + + +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + if ((TRUE == stcExtifInternData.bGdcSdramErrorInterruptEnable) && + (stcExtifInternData.pfnGdcSdramErrorCallback != NULL)) + { + if (1u == FM_EXBUS->MEMCERR_f.SDER) + { + FM_EXBUS->MEMCERR_f.SDER = 1u; // Clear GDC SDRAM error interrupt + stcExtifInternData.pfnGdcSdramErrorCallback(); + } + } +#endif +} +#endif + +/** + ****************************************************************************** + ** \brief Setup (init) an EXT-I/F area + ** + ** \param u8Area Extbus I/F area (chip select) number + ** \param pstcConfig Pointer to area configuration + ** + ** \retval Ok Setup successful + ** \retval ErrorInvalidParameter pstcConfig == NULL, Area number wrong, + ** other invalid setting. + ** \retval ErrorInvalidMode SDMODE is set for area different from 8 + ******************************************************************************/ +en_result_t Extif_InitArea( uint8_t u8Area, + const stc_extif_area_config_t* pstcConfig + ) +{ + // Local register predefinitions + stc_exbus_mode0_field_t stcMODE; + stc_exbus_tim0_field_t stcTIM; + stc_exbus_area0_field_t stcAREA; + stc_exbus_atim0_field_t stcATIM; + stc_exbus_dclkr_field_t stcDCLKR; +#if (PDL_MCU_CORE == PDL_FM4_CORE) + stc_exbus_sdmode_field_t stcSDMODE; + stc_exbus_reftim_field_t stcREFTIM; + stc_exbus_pwrdwn_field_t stcPWRDWN; + stc_exbus_sdtim_field_t stcSDTIM; + stc_exbus_memcerr_field_t stcMEMCERR; + stc_exbus_amode_field_t stcAMODE; + uint8_t u8InitNvic = 0; +#endif + uint8_t u8Dummy; + uint8_t u8InitGdcSdram = 0, u8InitExtifSdram = 0; +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + stc_sdramc_sdmode_field_t stcGdcSDMODE; + stc_sdramc_reftim_field_t stcGdcREFTIM; + stc_sdramc_pwrdwn_field_t stcGdcPWRDWN; + stc_sdramc_sdtim_field_t stcGdcSDTIM; + stc_exbus_memcerr_field_t stcGdcMEMCERR; +#endif + PDL_ZERO_STRUCT(stcMODE); + PDL_ZERO_STRUCT(stcTIM); + PDL_ZERO_STRUCT(stcAREA); + PDL_ZERO_STRUCT(stcATIM); + PDL_ZERO_STRUCT(stcDCLKR); +#if (PDL_MCU_CORE == PDL_FM4_CORE) + PDL_ZERO_STRUCT(stcSDMODE); + PDL_ZERO_STRUCT(stcREFTIM); + PDL_ZERO_STRUCT(stcPWRDWN); + PDL_ZERO_STRUCT(stcSDTIM); + PDL_ZERO_STRUCT(stcMEMCERR); + PDL_ZERO_STRUCT(stcAMODE); +#endif +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + PDL_ZERO_STRUCT(stcGdcSDMODE); + PDL_ZERO_STRUCT(stcGdcREFTIM); + PDL_ZERO_STRUCT(stcGdcPWRDWN); + PDL_ZERO_STRUCT(stcGdcSDTIM); + PDL_ZERO_STRUCT(stcGdcMEMCERR); +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + stcExtifInternData.pfnSdramErrorCallback = NULL; + stcExtifInternData.pfnSramFlashErrorCallback = NULL; +#endif + + if ((u8Area > 8u) || (NULL == pstcConfig)) + { + return ErrorInvalidParameter; + } +#if (PDL_MCU_CORE == PDL_FM4_CORE) + u8InitExtifSdram = ((NULL != pstcConfig->pExtifSdramConfig) ? 1u : 0u); +#endif +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + u8InitGdcSdram = ((NULL != pstcConfig->pGdcSdramConfig) ? 1u : 0u); +#endif + // Initialize NOR/SRAM/Nand interface when SDRAM mode is not used. + if ((0u == u8InitExtifSdram) && (0u == u8InitGdcSdram)) + { + switch (pstcConfig->enWidth) + { + case Extif8Bit: + stcMODE.WDTH = 0u; + break; + case Extif16Bit: + stcMODE.WDTH = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // MODE Register preparation + stcMODE.RBMON = (TRUE == pstcConfig->bReadByteMask) ? 1ul : 0ul ; + stcMODE.WEOFF = (TRUE == pstcConfig->bWriteEnableOff) ? 1ul : 0ul ; + stcMODE.NAND = (TRUE == pstcConfig->bNandFlash) ? 1ul : 0ul ; + stcMODE.PAGE = (TRUE == pstcConfig->bPageAccess) ? 1ul : 0ul ; + #if (PDL_MCU_TYPE != PDL_FM3_TYPE0) + stcMODE.RDY = (TRUE == pstcConfig->bRdyOn) ? 1ul : 0ul ; + stcMODE.SHRTDOUT = (TRUE == pstcConfig->bStopDataOutAtFirstIdle) ? 1ul : 0ul ; + stcMODE.MPXMODE = (TRUE == pstcConfig->bMultiplexMode) ? 1ul : 0ul ; + stcMODE.ALEINV = (TRUE == pstcConfig->bAleInvert) ? 1ul : 0ul ; + stcMODE.MPXDOFF = (TRUE == pstcConfig->bAddrOnDataLinesOff) ? 1ul : 0ul ; + stcMODE.MPXCSOF = (TRUE == pstcConfig->bMpxcsOff) ? 1ul : 0ul ; + stcMODE.MOEXEUP = (TRUE == pstcConfig->bMoexWidthAsFradc) ? 1ul : 0ul ; + #endif + + // TIM Register preparation + #if (PDL_MCU_TYPE != PDL_FM3_TYPE0) + if ((Extif0Cycle == pstcConfig->enReadAccessCycle) || + (ExtifDisabled == pstcConfig->enReadAccessCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.RACC = (uint8_t) (pstcConfig->enReadAccessCycle - 1u); + + if ((Extif16Cycle == pstcConfig->enReadAddressSetupCycle) || + (ExtifDisabled == pstcConfig->enReadAddressSetupCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.RADC = (uint8_t) pstcConfig->enReadAddressSetupCycle; + + if ((FALSE == pstcConfig->bPageAccess) && (FALSE == pstcConfig->bMoexWidthAsFradc)) + { + if ((Extif0Cycle == pstcConfig->enFirstReadAddressCycle) || + (ExtifDisabled == pstcConfig->enFirstReadAddressCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.FRADC = (uint8_t) (pstcConfig->enFirstReadAddressCycle - 1u); + } + else if ((TRUE == pstcConfig->bPageAccess) && (FALSE == pstcConfig->bMoexWidthAsFradc)) + { + if ((Extif16Cycle == pstcConfig->enFirstReadAddressCycle) || + (ExtifDisabled == pstcConfig->enFirstReadAddressCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.FRADC = (uint8_t) pstcConfig->enFirstReadAddressCycle; + } + else + { + return ErrorInvalidParameter; // Other setting for PAGE and MOEXEUP not allowed! + } + #endif + + if ((Extif0Cycle == pstcConfig->enReadIdleCycle) || + (ExtifDisabled == pstcConfig->enReadIdleCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.RIDLC = (uint8_t) (pstcConfig->enReadIdleCycle - 1u); + + if ((Extif0Cycle == pstcConfig->enWriteAccessCycle) || + (Extif1Cycle == pstcConfig->enWriteAccessCycle) || + (Extif2Cycle == pstcConfig->enWriteAccessCycle) || + (ExtifDisabled == pstcConfig->enWriteAccessCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.WACC = (uint8_t) (pstcConfig->enWriteAccessCycle - 1u); + + if ((Extif16Cycle == pstcConfig->enWriteAddressSetupCycle) || + (Extif0Cycle == pstcConfig->enWriteAddressSetupCycle) || + (ExtifDisabled == pstcConfig->enWriteAddressSetupCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.WADC = (uint8_t) (pstcConfig->enWriteAddressSetupCycle - 1u); + + if ((Extif16Cycle == pstcConfig->enWriteEnableCycle) || + (Extif0Cycle == pstcConfig->enWriteEnableCycle) || + (ExtifDisabled == pstcConfig->enWriteEnableCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.WWEC = (uint8_t) (pstcConfig->enWriteEnableCycle - 1u); + + if ((Extif0Cycle == pstcConfig->enWriteIdleCycle) || + (ExtifDisabled == pstcConfig->enWriteIdleCycle)) + { + return ErrorInvalidParameter; + } + stcTIM.WIDLC = (uint8_t) (pstcConfig->enWriteIdleCycle - 1u); + + // Check timing contraints + // WACC >= WADC + WWEC + u8Dummy = (uint8_t)stcTIM.WADC; // u8Dummy provided because of volatile + u8Dummy += (uint8_t)stcTIM.WWEC; // qualifiers, which cannot be mixed + if ((uint8_t)stcTIM.WACC < u8Dummy) // in one expression + { + return ErrorInvalidParameter; + } + + // RADC < RACC + u8Dummy = (uint8_t)stcTIM.RACC; // see above + if ((uint8_t)stcTIM.RADC >= u8Dummy) + { + return ErrorInvalidParameter; + } + + // AREA Register preparation + stcAREA.ADDR = (uint8_t) pstcConfig->u8AreaAddress; + stcAREA.MASK = (uint8_t) pstcConfig->enAreaMask; + + // ATIM Register preparation + if ((Extif0Cycle == pstcConfig->enAddressLatchCycle) || + (ExtifDisabled == pstcConfig->enAddressLatchCycle)) + { + return ErrorInvalidParameter; + } + stcATIM.ALC = (uint8_t) (pstcConfig->enAddressLatchCycle - 1u); + + if ((Extif16Cycle == pstcConfig->enReadAddressSetupCycle) || + (ExtifDisabled == pstcConfig->enReadAddressSetupCycle)) + { + return ErrorInvalidParameter; + } + stcATIM.ALES = (uint8_t) pstcConfig->enReadAddressSetupCycle; + + if ((Extif0Cycle == pstcConfig->enAddressLatchWidthCycle) || + (ExtifDisabled == pstcConfig->enAddressLatchWidthCycle)) + { + return ErrorInvalidParameter; + } + stcATIM.ALEW = (uint8_t) (pstcConfig->enAddressLatchWidthCycle - 1u); + #if (PDL_MCU_CORE == PDL_FM4_CORE) + if (TRUE == pstcConfig->bSramFlashErrorInterruptEnable) + { + stcMEMCERR.SFION = 1u; + stcExtifInternData.bSramFlashErrorInterruptEnable = TRUE; + stcExtifInternData.pfnSramFlashErrorCallback = pstcConfig->pfnSramFlashErrorCallback; + } + #endif + } +#if (PDL_MCU_TYPE != PDL_FM3_TYPE0) + // DCLKR Register preparation + if ((pstcConfig->u8MclkDivision == 0u) || + (pstcConfig->u8MclkDivision > 16u)) + { + return ErrorInvalidParameter; + } + else + { + stcDCLKR.MDIV = (uint8_t) pstcConfig->u8MclkDivision - 1u; + } + + stcDCLKR.MCLKON = (TRUE == pstcConfig->bMclkoutEnable) ? 1ul : 0ul ; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) + // AMODE Register preparation + stcAMODE.WAEN = (TRUE == pstcConfig->bPrecedReadContinuousWrite) ? 1ul : 0ul ; + + // Configure SDRAM I/F of external bus interface + if(NULL != pstcConfig->pExtifSdramConfig) + { + // Check for SDMODE and cheip select area 8 + if ((TRUE == pstcConfig->pExtifSdramConfig->bSdramEnable) && (8u != u8Area)) + { + return ErrorInvalidMode; + } + + // SDMODE Register preparation + stcSDMODE.SDON = (TRUE == pstcConfig->pExtifSdramConfig->bSdramEnable) ? 1ul : 0ul ; + stcSDMODE.PDON = (TRUE == pstcConfig->pExtifSdramConfig->bSdramPowerDownMode) ? 1ul : 0ul ; + stcSDMODE.ROFF = (TRUE == pstcConfig->pExtifSdramConfig->bSdramRefreshOff) ? 1ul : 0ul ; + + switch (pstcConfig->pExtifSdramConfig->enCasel) + { + case ExtifCas16Bit: + stcSDMODE.CASEL = 0ul; + break; + case ExtifCas32Bit: + stcSDMODE.CASEL = 1ul; + break; + default: + return ErrorInvalidParameter; + } + + stcSDMODE.RASEL = (uint8_t) pstcConfig->pExtifSdramConfig->enRasel; + stcSDMODE.BASEL = (uint8_t) pstcConfig->pExtifSdramConfig->enBasel; + stcSDMODE.MSDCLKOFF = 0u; + + // REFTIM Register preparation + stcREFTIM.REFC = pstcConfig->pExtifSdramConfig->u16RefreshCount; + stcREFTIM.NREF = pstcConfig->pExtifSdramConfig->u8RefreshNumber; + stcREFTIM.PREF = (TRUE == pstcConfig->pExtifSdramConfig->bPreRefreshEnable) ? 1ul : 0ul ; + + // PWRDWN Register preparation + stcPWRDWN.PDC = pstcConfig->pExtifSdramConfig->u16PowerDownCount; + + // SDTIM Register preparation + stcSDTIM.CL = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramCasLatencyCycle; + stcSDTIM.TRC = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramRasCycle; + stcSDTIM.TRP = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramRasPrechargeCycle; + stcSDTIM.TRCD = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramRasCasDelayCycle; + stcSDTIM.TRAS = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramRasActiveCycle; + stcSDTIM.TREFC = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramRefreshCycle; + stcSDTIM.TDPL = (uint8_t) pstcConfig->pExtifSdramConfig->enSdramPrechargeCycle; + + // MEMCERR Register preparation and Callback Pointer intern data settings + if (TRUE == pstcConfig->pExtifSdramConfig->bSdramErrorInterruptEnable) + { + stcMEMCERR.SDION = 1u; + stcExtifInternData.bSdramErrorInterruptEnable = TRUE; + stcExtifInternData.pfnSdramErrorCallback = pstcConfig->pExtifSdramConfig->pfnSdramErrorCallback; + } + } + +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + // Configure SDRAM I/F of GDC + if(NULL != pstcConfig->pGdcSdramConfig) + { + // SDMODE Register preparation + stcGdcSDMODE.SDON = (TRUE == pstcConfig->pGdcSdramConfig->bSdramEnable) ? 1ul : 0ul ; + stcGdcSDMODE.PDON = (TRUE == pstcConfig->pGdcSdramConfig->bSdramPowerDownMode) ? 1ul : 0ul ; + stcGdcSDMODE.ROFF = (TRUE == pstcConfig->pGdcSdramConfig->bSdramRefreshOff) ? 1ul : 0ul ; + + switch (pstcConfig->pGdcSdramConfig->enCasel) + { + case ExtifCas16Bit: + stcGdcSDMODE.CASEL = 0ul; + break; + case ExtifCas32Bit: + stcGdcSDMODE.CASEL = 1ul; + break; + default: + return ErrorInvalidParameter; + } + + stcGdcSDMODE.RASEL = (uint8_t) pstcConfig->pGdcSdramConfig->enRasel; + stcGdcSDMODE.BASEL = (uint8_t) pstcConfig->pGdcSdramConfig->enBasel; + stcGdcSDMODE.MSDCLKOFF = 0u; + + // REFTIM Register preparation + stcGdcREFTIM.REFC = pstcConfig->pGdcSdramConfig->u16RefreshCount; + stcGdcREFTIM.NREF = pstcConfig->pGdcSdramConfig->u8RefreshNumber; + stcGdcREFTIM.PREF = (TRUE == pstcConfig->pGdcSdramConfig->bPreRefreshEnable) ? 1ul : 0ul ; + + // PWRDWN Register preparation + stcGdcPWRDWN.PDC = pstcConfig->pGdcSdramConfig->u16PowerDownCount; + + // SDTIM Register preparation + stcGdcSDTIM.CL = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramCasLatencyCycle; + stcGdcSDTIM.TRC = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramRasCycle; + stcGdcSDTIM.TRP = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramRasPrechargeCycle; + stcGdcSDTIM.TRCD = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramRasCasDelayCycle; + stcGdcSDTIM.TRAS = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramRasActiveCycle; + stcGdcSDTIM.TREFC = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramRefreshCycle; + stcGdcSDTIM.TDPL = (uint8_t) pstcConfig->pGdcSdramConfig->enSdramPrechargeCycle; + + // MEMCERR Register preparation and Callback Pointer intern data settings + if (TRUE == pstcConfig->pGdcSdramConfig->bSdramErrorInterruptEnable) + { + stcGdcMEMCERR.SDION = 1u; + stcExtifInternData.bGdcSdramErrorInterruptEnable = TRUE; + stcExtifInternData.pfnGdcSdramErrorCallback = pstcConfig->pGdcSdramConfig->pfnSdramErrorCallback; + } + } +#endif +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + u8InitNvic = ((TRUE == pstcConfig->bSramFlashErrorInterruptEnable) ? 1u : 0u); + u8InitNvic += ((TRUE == pstcConfig->pExtifSdramConfig->bSdramErrorInterruptEnable) ? 1u : 0u); +#endif +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + u8InitNvic += ((TRUE == pstcConfig->pGdcSdramConfig->bSdramErrorInterruptEnable) ? 1u : 0u); +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + if (u8InitNvic > 0u) + { +#if (FM4_SDRAMC_AVAILABLE == 1) + NVIC_ClearPendingIRQ(EXTBUS_ERR_GDC_SDRAM_IRQn); + NVIC_EnableIRQ(EXTBUS_ERR_GDC_SDRAM_IRQn); + NVIC_SetPriority(EXTBUS_ERR_GDC_SDRAM_IRQn, PDL_IRQ_LEVEL_EXTIF); +#else + NVIC_ClearPendingIRQ(EXTBUS_ERR_IRQn); + NVIC_EnableIRQ(EXTBUS_ERR_IRQn); + NVIC_SetPriority(EXTBUS_ERR_IRQn, PDL_IRQ_LEVEL_EXTIF); +#endif + } +#endif + // Finally setup hardware + if (u8Area < 8u) + { + EXTIF.astcMODE[u8Area] = stcMODE; + EXTIF.astcTIM[u8Area] = stcTIM; + EXTIF.astcAREA[u8Area] = stcAREA; + EXTIF.astcATIM[u8Area] = stcATIM; + } + + FM_EXBUS->DCLKR_f = stcDCLKR; +#if (PDL_MCU_CORE == PDL_FM4_CORE) + FM_EXBUS->AMODE_f = stcAMODE; + if(NULL != pstcConfig->pExtifSdramConfig) + { + // Clear mode register + FM_EXBUS->SDMODE = 0u; + + // Set the registers + FM_EXBUS->REFTIM_f = stcREFTIM; + FM_EXBUS->PWRDWN_f = stcPWRDWN; + FM_EXBUS->SDTIM_f = stcSDTIM; + FM_EXBUS->MEMCERR_f = stcMEMCERR; + FM_EXBUS->SDMODE_f = stcSDMODE; + } +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + if(NULL != pstcConfig->pGdcSdramConfig) + { + // Clear mode register + FM_SDRAMC->SDMODE = 0u; + + // Set the registers + FM_SDRAMC->REFTIM_f = stcGdcREFTIM; + FM_SDRAMC->PWRDWN_f = stcGdcPWRDWN; + FM_SDRAMC->SDTIM_f = stcGdcSDTIM; + FM_EXBUS->MEMCERR_f = stcGdcMEMCERR; + FM_SDRAMC->SDMODE_f = stcGdcSDMODE; + } +#endif +#endif + + return Ok; +} // Extif_InitArea + +#if (PDL_MCU_CORE == PDL_FM4_CORE) +/** + ****************************************************************************** + ** \brief Read Error Status Register + ** + ** \retval Ok No error response exists + ** \retval Error Error response exists + ******************************************************************************/ +en_result_t Extif_ReadErrorStatus( void ) +{ + if (TRUE == FM_EXBUS->EST_f.WERR) + { + return Error; + } + + return Ok; +} // Extif_ReadErrorStatus + +/** + ****************************************************************************** + ** \brief Read Error Address Register + ** + ** \return uint32_t Error Address + ******************************************************************************/ +uint32_t Extif_ReadErrorAddress( void ) +{ + return FM_EXBUS->WEAD; +} // Extif_ReadErrorAddress + +/** + ****************************************************************************** + ** \brief Clear Error Status Register + ** + ** \retval Ok Status Error cleared + ******************************************************************************/ +en_result_t Extif_ClearErrorStatus( void ) +{ + FM_EXBUS->ESCLR_f.WERRCLR = 0u; + + return Ok; +} // Extif_ClearErrorStatus + +/** + ****************************************************************************** + ** \brief Check SDRAM command register is ready + ** + ** \retval Ok Writing to SDCMD register is possible + ** \retval ErrorNotReady Access to SDCMD register not possible + ******************************************************************************/ +en_result_t Extif_CheckSdcmdReady( void ) +{ + if (TRUE == FM_EXBUS->SDCMD_f.PEND) + { + return ErrorNotReady; + } + + return Ok; +} // Extif_CheckSdcmdReady + +/** + ****************************************************************************** + ** \brief Set a SDRAM command + ** + ** \note This function calls Extif_CheckSdcmdReady(). + ** + ** \param u16Address SDRAM address (MAD[15:00] pin values) + ** \param bMsdwex MDSWEX pin value + ** \param bMcasx MCASX pin value + ** \param bMrasx MRASX pin value + ** \param bMcsx8 MCSX8 pin value + ** \param bMadcke MADCKE pin value + ** + ** \retval Ok Writing to SDCMD register was successful + ** \retval ErrorNotReady Access to SDCMD register was not possible + ******************************************************************************/ +en_result_t Extif_SetSdramCommand( uint16_t u16Address, + boolean_t bMsdwex, + boolean_t bMcasx, + boolean_t bMrasx, + boolean_t bMcsx8, + boolean_t bMadcke + ) +{ + stc_exbus_sdcmd_field_t stcSDCMD; + + if (ErrorNotReady == Extif_CheckSdcmdReady()) + { + return ErrorNotReady; + } + + stcSDCMD.SDAD = u16Address; + stcSDCMD.SDWE = bMsdwex; + stcSDCMD.SDCAS = bMcasx; + stcSDCMD.SDRAS = bMrasx; + stcSDCMD.SDCS = bMcsx8; + stcSDCMD.SDCKE = bMadcke; + + FM_EXBUS->SDCMD_f = stcSDCMD; + + return Ok; +} +#endif + + +#endif // #if (defined(PDL_PERIPHERAL_EXTIF_ACTIVE) +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.h new file mode 100644 index 0000000000..47a2f14363 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/extif/extif.h @@ -0,0 +1,494 @@ +/******************************************************************************* +* \file extif.h +* +* \version 1.50 +* +* \brief Headerfile for External Bus Interface functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __EXTIF_H__ +#define __EXTIF_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_EXTIF_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupEXTIF External Bus Interface (EXTIF) +* \{ +* \defgroup GroupEXTIF_Macros Macros +* \defgroup GroupEXTIF_Functions Functions +* \defgroup GroupEXTIF_DataStructures Data Structures +* \defgroup GroupEXTIF_Types Enumerated Types +* \} +*/ +/** +* \addtogroup GroupEXTIF +* \{ +* The External Bus Interface (EXTIF) enables connections with SRAM, Flash memory, and +* SDRAM outside of the device.
+* The features of the external bus interface across the products are as follows:
+* - Supports 8-bit/16-bit wide SRAM, SDRAM as well as NOR and NAND Flash memories
+* - Up to 8 chip select signals are available - one chip select signal is provided +* to SDRAM exclusively
+* - Address and access timing parameters can be separately set for each chip select signal
+* - Up to 25 bits address can be output
+* - Supports NOR Flash memory page read
+* - Byte lane is fixed to little endian
+* - Automatically convers bus size when the access width from CPU and the external +* bus width are different
+* - Separate mode and multiplex mode are supported for bus access +* ( NAND flash memory, SDRAM and the page read of NOR flash memory do not support multiplex mode)
+* - The access timing parameter of ALE signal is added to support the multiplex mode. In addition, +* more detailed parameter settings, such as CS assert timing, are possible.
+* - Clock output feature allows synchronous accesses with target devices
+* - Supports external RDY feature
+* - Supports SDRAM power down mode
+* - Operates with a division clock output of the base clock (HCLK)
+* - When MCLKOUT and MSDCLK are to be output from this LSI, it is necessary to +* configure a division ratio that satisfies the output standard described on the data sheet.
+* \section SectionEXTIF_ConfigurationConsideration Configuration Consideration +* To set up the EXTIF, relocate the GPIO pin function to the external bus pins. +* Use the SetPinFunc macros provided by the headerfile file common/gpio_.h +* for the correct pin relocation.
+* Example
+* SetPinFunc_MADATA00_0();
+* SetPinFunc_MADATA01_0();
+* SetPinFunc_MADATA02_0();
+* ...
+* SetPinFunc_MNCLE_0();
+* SetPinFunc_MNALE_0();
+* SetPinFunc_MNWEX_0();
+* To setup a memory area use the function Extif_InitArea() and pass the chip +* select number and configuration structure. The configuration structure depends on the +* memory device and is described below.
+* For error handling the functions Extif_ReadErrorStatus(), Extif_ReadErrorAddress() +* and Extif_ClearErrorStatus() are provided.
+* | Clock output | External RDY | Page mode | NAND Flash | Clock division +* -----------------|--------------|--------------|-------------|-------------|--------------- +* SRAM | Available | Available | Not Allowed | Not Allowed | Available +* NOR Flash memory | Available | Not Allowed | Available | Not Allowed | Available +* NAND Flash memory| Not Allowed | Not Allowed | Not Allowed | Available | Available +* SDRAM | Available | Not allowed | Not allowed | Not allowed | Available +* +* SRAM and NOR Flash:
+* Use stc_extif_area_config_t to configure XTIF for SRAM and NOR Flash. +* The structure includes all settings for the configuration of the interface, +* for example the data width, the address area, bus speed, refresh timings and refresh cycles.
+* For accessing the SRAM and NOR Flash memory, the same signals are used.
+* NAND Flash
+* Use stc_extif_area_config_t to configure XTIF for NAND Flash. Use these macros to access NAND Flash:
+* * Extif_Nand_ReadData – Used to read data from the NAND Flash memory
+* * Extif_Nand_WriteData - Used to write data to the NAND Flash memory
+* * Extif_Nand_SetAddress – Used to set the address
+* * Extif_Nand_SetCommand - issue a command for the NAND Flash memory (MNCLE is asserted)
+* * Extif_Nand_ClearAle – de-assert the MNALE signal between multiple write accesses.
+* SDRAM
+* Use both stc_extif_area_config_t and stc_extif_sdram_config_t to configure XTIF for SDRAM. +* These structures include all settings for the configuration of the interface, for example: +* the data width, the address area, bus speed, refresh timings and refresh cycles.
+* Use Extif_SetSdramCommand() to write SDRAM commands. That function calls Extif_CheckSdcmdReady() +* to determine whether the SDRAM command register is available, and returns an error if writing is not possible.
+* SDRAM is supported only for chip select 8.
+* Notes:
+* * There are already some drivers for specific devices available in the +* utilities folder of the PDL. These drivers explain setting up a new memory device.
+* * When an access is made to an external bus area of 256MB SRAM/Flash memory address area, +* an area which has not been mapped with the area register, or SDRAM address area with the +* setting of SDRAM mode register of SDON=0, the external bus interface outputs an error +* response (by setting HRESP[1:0] to "01"). When this error occurs during a burst transfer, +* the operation of the external bus interface is not guaranteed.
+* * When the setup value of registers such as the timing register is rewritten from +* the CPU while accessing the external bus from the DMAC, written values will not be +* reflected until the access is completed (after the idle cycle).
+* * When using the external bus interface, set EXBRST bit of peripheral reset control +* register 0 (MRST0) become 1. If using external bus interface without executing +* external bus interface reset, there is a possibility that the device become runaway, +* because the access request to external bus interface cannot be accepted. +* +* \section SectionEXTIF_MoreInfo More Information +* For more information on the EXTIF peripheral, refer to:
+* FM4 Peripheral Manual Core Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupEXTIF_Macros +* \{ +*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define EXTIF (*((stc_extif_arrays_t *) FM_EXBUS_BASE)) + +/****************************************************************************** + * NAND Flash access macros (intern) + ******************************************************************************/ +#define EXITIF_NAND_ALE_OFFSET 0x00003000ul ///< Address offset for MNALE assert until write +#define EXITIF_NAND_ADDR_OFFSET 0x00002000ul ///< Address offset for address cycle (+ MNALE) +#define EXITIF_NAND_CMD_OFFSET 0x00001000ul ///< Address offset for command cycle (+ MNCLE) +#define EXITIF_NAND_DATA_OFFSET 0x00000000ul ///< Address offset for data read/write + +/****************************************************************************** + * NAND Flash access macros (user) + ******************************************************************************/ +#define Extif_Nand_SetCommand(base, cmd) {*(volatile unsigned char*)((base) + EXITIF_NAND_CMD_OFFSET) = (unsigned char)(cmd);} ///< Sets a NAND command cycle +#define Extif_Nand_SetAddress(base, addr) {*(volatile unsigned char*)((base) + EXITIF_NAND_ADDR_OFFSET) = (unsigned char)(addr);} ///< Sets a NAND address cycle +#define Extif_Nand_ReadData(base) (*(volatile unsigned char*)((base) + EXITIF_NAND_DATA_OFFSET)) ///< Reads NAND data +#define Extif_Nand_WriteData(base, data) {*(volatile unsigned char*)((base) + EXITIF_NAND_DATA_OFFSET) = (unsigned char)(data);} ///< Writes NAND data +#define Extif_Nand_ClearAle(base) {*(volatile unsigned char*)((base) + EXITIF_NAND_ALE_OFFSET) = (unsigned char)0;} ///< De-asserts MNALE signal + +/** \} GroupEXTIF_Macros */ + +/** +* \addtogroup GroupEXTIF_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Extif data width + ** + ** To select the data bus width + ******************************************************************************/ +typedef enum en_extif_width +{ + Extif8Bit = 0u, ///< 8 Bit mode + Extif16Bit = 1u, ///< 16 Bit mode +#if (PDL_MCU_TYPE == PDL_FM4_TYPE3) + Extif32Bit = 2u, ///< 32 Bit mode +#endif +} en_extif_width_t; + +/** + ****************************************************************************** + ** \brief Extif cycle defintion + ** + ** To select the bus mode of the interface. + ** + ** \note Do not change enumeration number. The numbers are taken for + ** calculating the corresponding bitfield! + ******************************************************************************/ +typedef enum en_extif_cycle +{ + Extif0Cycle = 0u, ///< 0 cycles + Extif1Cycle = 1u, ///< 1 cycle + Extif2Cycle = 2u, ///< 2 cycles + Extif3Cycle = 3u, ///< 3 cycles + Extif4Cycle = 4u, ///< 4 cycles + Extif5Cycle = 5u, ///< 5 cycles + Extif6Cycle = 6u, ///< 6 cycles + Extif7Cycle = 7u, ///< 7 cycles + Extif8Cycle = 8u, ///< 8 cycles + Extif9Cycle = 9u, ///< 9 cycles + Extif10Cycle = 10u, ///< 10 cycles + Extif11Cycle = 11u, ///< 11 cycles + Extif12Cycle = 12u, ///< 12 cycles + Extif13Cycle = 13u, ///< 13 cycles + Extif14Cycle = 14u, ///< 14 cycles + Extif15Cycle = 15u, ///< 15 cycles + Extif16Cycle = 16u, ///< 16 cycles + ExtifDisabled = 17u ///< Setting disabled +} en_extif_cycle_t; + +/** + ****************************************************************************** + ** \brief SDRAM cycle defintion + ** + ** To select the bus mode of the interface. + ** + ** \note Do not change enumeration number. The numbers are taken for + ** calculating the corresponding bitfield! + ******************************************************************************/ +typedef enum en_sdram_cycle +{ + Sdram1Cycle = 0u, ///< 1 cycle + Sdram2Cycle = 1u, ///< 2 cycles + Sdram3Cycle = 2u, ///< 3 cycles + Sdram4Cycle = 3u, ///< 4 cycles + Sdram5Cycle = 4u, ///< 5 cycles + Sdram6Cycle = 5u, ///< 6 cycles + Sdram7Cycle = 6u, ///< 7 cycles + Sdram8Cycle = 7u, ///< 8 cycles + Sdram9Cycle = 8u, ///< 9 cycles + Sdram10Cycle = 9u, ///< 10 cycles + Sdram11Cycle = 10u, ///< 11 cycles + Sdram12Cycle = 11u, ///< 12 cycles + Sdram13Cycle = 12u, ///< 13 cycles + Sdram14Cycle = 13u, ///< 14 cycles + Sdram15Cycle = 14u, ///< 15 cycles + Sdram16Cycle = 15u, ///< 16 cycles + SdramDisabled = 16u ///< Setting disabled +} en_sdram_cycle_t; + +/** + ****************************************************************************** + ** \brief Extif mask setup (area size) + ** + ** To select the Mask Setup value for the address area per chip select. + ** + ** \note Do not change enumeration number. The numbers are taken for + ** calculating the corresponding bitfield! + ******************************************************************************/ +typedef enum en_extif_mask +{ + Extif1MB = 0u, ///< Area 1 MByte + Extif2MB = 1u, ///< Area 2 MByte + Extif4MB = 2u, ///< Area 4 MByte + Extif8MB = 3u, ///< Area 8 MByte + Extif16MB = 4u, ///< Area 16 MByte + Extif32MB = 5u, ///< Area 32 MByte + Extif64MB = 6u, ///< Area 64 MByte + Extif128MB = 7u ///< Area 128 MByte +} en_extif_mask_t; + +/** + ****************************************************************************** + ** \brief Extif CAS address select + ** + ** Select the address for the Column Address Select + ** + ** \note Do not change enumeration number. The numbers are taken for + ** calculating the corresponding bitfield! + ******************************************************************************/ +typedef enum en_extif_cas +{ + ExtifCas16Bit = 0u, ///< MAD[9:0] = Internal address [10:1], 16-Bit width + ExtifCas32Bit = 1u ///< MAD[9:0] = Internal address [11:2], 32-Bit width +} en_extif_cas_t; + +/** + ****************************************************************************** + ** \brief Extif RAS address select + ** + ** Select the address for the Row Address Select + ** + ** \note Do not change enumeration number. The numbers are taken for + ** calculating the corresponding bitfield! + ******************************************************************************/ +typedef enum en_extif_ras +{ + ExtifRas_19_6 = 0u, ///< MAD[13:0] = Internal address [19:6] + ExtifRas_20_7 = 1u, ///< MAD[13:0] = Internal address [20:7] + ExtifRas_21_8 = 2u, ///< MAD[13:0] = Internal address [21:8] + ExtifRas_22_9 = 3u, ///< MAD[13:0] = Internal address [22:9] + ExtifRas_23_10 = 4u, ///< MAD[13:0] = Internal address [23:10] + ExtifRas_24_11 = 5u, ///< MAD[13:0] = Internal address [24:11] + ExtifRas_25_12 = 6u, ///< MAD[13:0] = Internal address [25:12] +} en_extif_ras_t; + +/** + ****************************************************************************** + ** \brief Extif BAS address select + ** + ** Select the address for the Bank Address Select + ** + ** \note Do not change enumeration number. The numbers are taken for + ** calculating the corresponding bitfield! + ******************************************************************************/ +typedef enum en_extif_bas +{ + ExtifBas_20_19 = 0u, ///< MAD[13:0] = Internal address [20:19] + ExtifBas_21_20 = 1u, ///< MAD[13:0] = Internal address [21:20] + ExtifBas_22_21 = 2u, ///< MAD[13:0] = Internal address [22:21] + ExtifBas_23_22 = 3u, ///< MAD[13:0] = Internal address [23:22] + ExtifBas_24_23 = 4u, ///< MAD[13:0] = Internal address [24:23] + ExtifBas_25_24 = 5u, ///< MAD[13:0] = Internal address [25:24] + ExtifBas_26_25 = 6u, ///< MAD[13:0] = Internal address [26:25] +} en_extif_bas_t; + +/** \}GroupEXTIF_Types */ + +/** +* \addtogroup GroupEXTIF_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Definition of MODE, TIM, AREA, ATIM register arrays + ** + ** To select the data bus width + ******************************************************************************/ +typedef struct stc_extif_arrays +{ + union { + uint32_t au32MODE[8]; + stc_exbus_mode0_field_t astcMODE[8]; + }; + union { + uint32_t au32TIM[8]; + stc_exbus_tim0_field_t astcTIM[8]; + }; + union { + uint32_t au32AREA[8]; + stc_exbus_area0_field_t astcAREA[8]; + }; + union { + uint32_t au32ATIM[8]; + stc_exbus_atim0_field_t astcATIM[8]; + }; +} stc_extif_arrays_t; + + +typedef struct stc_extif_sdram_config +{ + boolean_t bSdramEnable; ///< TRUE: Enables SDRAM functionality (only possible for area 8) + boolean_t bSdramPowerDownMode; ///< TRUE: Enables SDRAM Power Down Mode (only possible for area 8) + boolean_t bSdramRefreshOff; ///< TRUE: Disables Refresh Function (only possible for area 8) + en_extif_cas_t enCasel; ///< Column Address Select, see #en_extif_cas_t for details (only possible for area 8) + en_extif_ras_t enRasel; ///< Row Address Select, see #en_extif_ras_t for details (only possible for area 8) + en_extif_bas_t enBasel; ///< Bank Address Select, see #en_extif_bas_t for details (only possible for area 8) + uint16_t u16RefreshCount; ///< Refresh Count in Cycles (only possible for area 8) + uint8_t u8RefreshNumber; ///< Number of Refreshs (only possible for area 8) + boolean_t bPreRefreshEnable; ///< TRUE: Enables Refresh (only possible for area 8) + uint16_t u16PowerDownCount; ///< Power Down Count in Cycles (only possible for area 8) + en_sdram_cycle_t enSdramCasLatencyCycle; ///< Latency of CAS in Cycles (only possible for area 8) + en_sdram_cycle_t enSdramRasCycle; ///< RAS Cycles (only possible for area 8) + en_sdram_cycle_t enSdramRasPrechargeCycle; ///< RAS Precharge Cycles (only possible for area 8) + en_sdram_cycle_t enSdramRasCasDelayCycle; ///< RAS CAS Delay Cycles (only possible for area 8) + en_sdram_cycle_t enSdramRasActiveCycle; ///< RAS Active Cycles (only possible for area 8) + en_sdram_cycle_t enSdramRefreshCycle; ///< Refresh Cycles (only possible for area 8) + en_sdram_cycle_t enSdramPrechargeCycle; ///< Data-in to Precharge Lead Time in Cycles (only possible for area 8) + boolean_t bSdramErrorInterruptEnable; ///< TRUE: Enables SDRAM error interrupt (only possible for area 8) + func_ptr_t pfnSdramErrorCallback; ///< Pointer to SDRAM Error Callback Function (only possible for area 8) + +}stc_extif_sdram_config_t; + +/** + ***************************************************************************** + ** \brief Extif area configuration + ** + ** The WDG configuration is done on a per area (Chip select) basis + *****************************************************************************/ +typedef struct stc_extif_area_config +{ + en_extif_width_t enWidth; ///< 8, 16 bit data bus width. See description of #en_extif_width_t + boolean_t bReadByteMask; ///< TRUE: Read Byte Mask enable + boolean_t bWriteEnableOff; ///< TRUE: Write enable disabled + boolean_t bNandFlash; ///< TRUE: NAND Flash bus enable, FLASE: NOR Flash/SRAM bus enable + boolean_t bPageAccess; ///< TRUE: NOR Flash memory page access mode enabled +#if (PDL_MCU_TYPE != PDL_FM3_TYPE0) + boolean_t bRdyOn; ///< TRUE: RDY mode enabled + boolean_t bStopDataOutAtFirstIdle; ///< TRUE: Stop to write data output at first idle cycle, FALSE: Extends to write data output to the last idle cycle + boolean_t bMultiplexMode; ///< TRUE: Multiplex mode + boolean_t bAleInvert; ///< TRUE: Invert ALE signal (negative polarity) + boolean_t bAddrOnDataLinesOff; ///< TRUE: Do not output address to data lines (Hi-Z during ALC cycle period) + boolean_t bMpxcsOff; ///< TRUE: Do not assert MCSX in ALC cycle period + boolean_t bMoexWidthAsFradc; ///< TRUE: MOEX width is set with FRADC, FALSE: MOEX width is set with RACC-RADC + boolean_t bMclkoutEnable; ///< TRUE: Enables MCLKOUT pin + uint8_t u8MclkDivision; ///< Division ratio for MCLK (1 ... 16 div) +#endif + en_extif_cycle_t enReadAccessCycle; ///< Read Access Cycle timing + en_extif_cycle_t enReadAddressSetupCycle; ///< Read Address Setup Cycle timing + en_extif_cycle_t enFirstReadAddressCycle; ///< First Read Address Cycle timing + en_extif_cycle_t enReadIdleCycle; ///< Read Idle Cycle timing + en_extif_cycle_t enWriteAccessCycle; ///< Write Access Cycle timing + en_extif_cycle_t enWriteAddressSetupCycle; ///< Write Address Setup Cycle timing + en_extif_cycle_t enWriteEnableCycle; ///< Write Enable Cycle timing + en_extif_cycle_t enWriteIdleCycle; ///< Write Idle Cycle timing + uint8_t u8AreaAddress; ///< Address bits [27:20] + en_extif_mask_t enAreaMask; ///< See description of #en_extif_mask_t + en_extif_cycle_t enAddressLatchCycle; ///< Address Latch Cycles + en_extif_cycle_t enAddressLatchSetupCycle; ///< Address Latch Enable Setup Cycles + en_extif_cycle_t enAddressLatchWidthCycle; ///< Address Latch Enable Width Cycles +#if (PDL_MCU_CORE == PDL_FM4_CORE) + boolean_t bPrecedReadContinuousWrite; ///< TRUE: Enables preceding read and continuous write request + stc_extif_sdram_config_t* pExtifSdramConfig; ///< Pointer to the configuration of SDRAM I/F of external bus interface +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + stc_extif_sdram_config_t* pGdcSdramConfig; ///< Pointer to the configuration of SDRAM I/F of GDC +#endif + boolean_t bSramFlashErrorInterruptEnable; ///< TRUE: Enables SRAM/Flash Error Interrupt + func_ptr_t pfnSramFlashErrorCallback; ///< Pointer to SRAM/Flash Error Callback Function + +#endif +} stc_extif_area_config_t; + +/// EXTIF Error Interrupt Callback Pointers +typedef struct stc_extif_intern_data +{ + boolean_t bSdramErrorInterruptEnable; ///< TRUE: Enables SDRAM error interrupt + boolean_t bSramFlashErrorInterruptEnable; ///< TRUE: Enables SRAM/Flash Error Interrupt +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + boolean_t bGdcSdramErrorInterruptEnable; ///< TRUE: Enables GDC SDRAM Error Interrupt +#endif + func_ptr_t pfnSdramErrorCallback; ///< Pointer to SDRAM Error Callback Function + func_ptr_t pfnSramFlashErrorCallback; ///< Pointer to SRAM/Flash Error Callback Function +#if (PDL_MCU_TYPE == PDL_FM4_TYPE4) + func_ptr_t pfnGdcSdramErrorCallback; ///< Pointer to GDC SDRAM Error Callback Function +#endif +} stc_extif_intern_data_t; + +/** \} GroupEXTIF_DataStructures */ + +/** +* \addtogroup GroupEXTIF_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ + +void Extif_IrqHandler( void ); + +en_result_t Extif_InitArea( uint8_t u8Area, + const stc_extif_area_config_t* pstcConfig ); + +en_result_t Extif_ReadErrorStatus( void ); + +uint32_t Extif_ReadErrorAddress( void ); + +en_result_t Extif_ClearErrorStatus( void ); + +en_result_t Extif_CheckSdcmdReady( void ); + +en_result_t Extif_SetSdramCommand( uint16_t u16Address, + boolean_t bMsdwex, + boolean_t bMcasx, + boolean_t bMrasx, + boolean_t bMcsx8, + boolean_t bMadcke + ); + +/** \} GroupEXTIF_Functions */ +/** \} GroupEXTIF */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_EXTIF_ACTIVE)) + +#endif /* __EXTIF_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.c new file mode 100644 index 0000000000..ddb6bc152b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.c @@ -0,0 +1,378 @@ +/******************************************************************************* +* \file dualflash.c +* +* \version 1.20 +* +* \brief dual flash driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "flash/dualflash.h" + +#if defined(PDL_PERIPHERAL_DUAL_FLASH_ACTIVE) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/*! + ****************************************************************************** + ** \brief Read a half word data from Flash + ** \param addr Pointer to read data address + ****************************************************************************** + */ +#define Flash_Read(addr) *(volatile uint8_t*)((uint32_t)(addr)) + +/*! + ****************************************************************************** + ** \brief Wirte a half word data into Flash + ** \param addr Pointer to read data address + ** \param data Write data + ****************************************************************************** + */ +#define Flash_Write(addr, data) *(volatile uint8_t*)((uint32_t)(addr)) = ( uint8_t)(data) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static uint8_t DFlash_CheckToggle(uint8_t* p_sec_addr ); +static uint8_t DFlash_ReadResetCmd(uint8_t* pResetSecAddr); + +/******************************************************************************/ +/* Notes: */ +/* The feature of Dual Flash is that High bank can erase/write low bank, */ +/* low bank can erase/write high bank. */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief Issue read/reset command + ** + ** \param pResetSecAddr address of reset sector + ** + ** \retval Dummy data + ** + ****************************************************************************** + */ +static uint8_t DFlash_ReadResetCmd(uint8_t* pResetSecAddr) +{ + uint8_t dummy; + + /* issue read/reset command */ + Flash_Write(0x0000u, 0xF0u) ; + dummy = Flash_Read(pResetSecAddr) ; + return dummy ; +} +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief Flash chip erase + ** + ** \retval Ok Chip erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t DFlash_ChipErase(void) +{ + en_result_t emRetValue = Ok; + + Flash_Write(0xAA8u, 0xAAu); + Flash_Write(0x554u, 0x55u); + Flash_Write(0xAA8u, 0x80u); + Flash_Write(0xAA8u, 0xAAu); + Flash_Write(0x554u, 0x55u); + Flash_Write(0xAA8u, 0x10u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( DFLASH_CHK_TOGG_ABNORMAL == DFlash_CheckToggle((uint8_t*)0) ) + { + /* sending the read/reset command to the reset sector */ + DFlash_ReadResetCmd((uint8_t*)0) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + + + return emRetValue; +} + +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief Flash sector erase + ** + ** \param pu16SecAddr address of flash sector + ** + ** \return Operation status + ** \retval Ok sector erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t DFlash_SectorErase(uint16_t* pu16SecAddr) +{ + en_result_t emRetValue = Ok; + Flash_Write(0xAA8u |((uint32_t)pu16SecAddr&0xffff000u), 0xAAu); + Flash_Write(0x554u |((uint32_t)pu16SecAddr&0xffff000u), 0x55u); + Flash_Write(0xAA8u |((uint32_t)pu16SecAddr&0xffff000u), 0x80u); + Flash_Write(0xAA8u |((uint32_t)pu16SecAddr&0xffff000u), 0xAAu); + Flash_Write(0x554u |((uint32_t)pu16SecAddr&0xffff000u), 0x55u); + Flash_Write(pu16SecAddr, 0x30u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( DFLASH_CHK_TOGG_ABNORMAL == DFlash_CheckToggle((uint8_t*)pu16SecAddr) ) + { + /* sending the read/reset command to the reset sector */ + DFlash_ReadResetCmd((uint8_t*)pu16SecAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + + return emRetValue; +} + +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief Flash word write + ** + ** \param pu32Addr address of flash data + ** \param pu32Data pointer to write data + ** \param u32Size data size, 1 indicates 1 32-bit data + ** + ** \return Operation status + ** \retval Ok sector erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t DFlash_WriteData32Bit( uint32_t* pu32Addr, uint32_t* pu32Data,uint32_t u32Size ) +{ + uint8_t *pAddr, *pData; + en_result_t emRetValue = Ok; + uint8_t cnt=1; + pAddr = (uint8_t*)pu32Addr; + pData = (uint8_t*)pu32Data; + + for(cnt = u32Size*sizeof(uint32_t);cnt;cnt--) + { + /* issue write command */ + Flash_Write(0xAA8u |((uint32_t)pu32Addr&0xffff000u), 0xAAu) ; + Flash_Write(0x554u |((uint32_t)pu32Addr&0xffff000u), 0x55u) ; + Flash_Write(0xAA8u |((uint32_t)pu32Addr&0xffff000u), 0xA0u) ; + Flash_Write((uint32_t)pAddr, (uint16_t)*pData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( DFLASH_CHK_TOGG_ABNORMAL == DFlash_CheckToggle(pAddr) ) || + ( Flash_Read((uint32_t)pAddr) != (uint16_t)*pData)) + { + /* issue read/reset command to reset sector */ + DFlash_ReadResetCmd(pAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pAddr++; + pData++; + } + + return emRetValue ; +} + +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief Flash half word write + ** + ** \param pu16Addr address of flash data + ** \param pu16Data pointer to write data + ** \param u32Size data size, 1 indicates 1 16-bit data + ** + ** \return Operation status + ** \retval Ok sector erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t DFlash_WriteData16Bit( uint16_t* pu16Addr, uint16_t* pu16Data, uint32_t u32Size ) +{ + uint8_t *pAddr, *pData; + en_result_t emRetValue = Ok; + uint8_t cnt=1; + pAddr = (uint8_t*)pu16Addr; + pData = (uint8_t*)pu16Data; + for(cnt = u32Size*sizeof(uint16_t);cnt;cnt--) + { + /* issue write command */ + Flash_Write(0xAA8u |((uint32_t)pu16Addr&0xffff000u), 0xAAu) ; + Flash_Write(0x554u |((uint32_t)pu16Addr&0xffff000u), 0x55u) ; + Flash_Write(0xAA8u |((uint32_t)pu16Addr&0xffff000u), 0xA0u) ; + Flash_Write((uint32_t)pAddr, (uint16_t)*pData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( DFLASH_CHK_TOGG_ABNORMAL == DFlash_CheckToggle(pAddr) ) || + ( Flash_Read((uint32_t)pAddr) != (uint16_t)*pData)) + { + /* issue read/reset command to reset sector */ + DFlash_ReadResetCmd(pAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pAddr++; + pData++; + } + + + return emRetValue ; +} + +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief Flash byte write + ** + ** \param pu8Addr address of flash data + ** \param pu8Data pointer to write data + ** \param u32Size data size, 1 indicates 1 8-bit data + ** + ** \return Operation status + ** \retval Ok sector erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t DFlash_WriteData8Bit( uint8_t* pu8Addr, uint8_t* pu8Data, uint32_t u32Size ) +{ + en_result_t emRetValue = Ok; + uint8_t cnt=1; + for(cnt = u32Size;cnt;cnt--) + { + /* issue write command */ + Flash_Write(0xAA8u |((uint32_t)pu8Addr&0xffff000u), 0xAAu) ; + Flash_Write(0x554u |((uint32_t)pu8Addr&0xffff000u), 0x55u) ; + Flash_Write(0xAA8u |((uint32_t)pu8Addr&0xffff000u), 0xA0u) ; + Flash_Write((uint32_t)pu8Addr, (uint16_t)*pu8Data); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( DFLASH_CHK_TOGG_ABNORMAL == DFlash_CheckToggle(pu8Addr) ) || + ( Flash_Read((uint32_t)pu8Addr) != (uint16_t)*pu8Data)) + { + /* issue read/reset command to reset sector */ + DFlash_ReadResetCmd(pu8Addr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pu8Addr++; + pu8Data++; + } + + + return emRetValue ; +} +#if defined ( __ICCARM__ ) +#pragma location=".flashcode" +#endif +/*! + ****************************************************************************** + ** \brief automatic algorithm of flash memory execution + ** + ** \param pAddr address of flash data + ** + ** \return Operation status + ** \retval DFLASH_RET_OK + ** \retval DFLASH_RET_ABNORMAL + ** \retval DFLASH_RET_INVALID_PARA + ** + ****************************************************************************** + */ +static uint8_t DFlash_CheckToggle( uint8_t* pAddr ) +{ + uint8_t usSequenceFlag1, usSequenceFlag2 ; /* hardware sequence flag */ + uint8_t ucRetValue = DFLASH_CHK_TOGG_NORMAL ; + + /* set hardware sequence flag */ + usSequenceFlag1 = Flash_Read(pAddr) ; + usSequenceFlag2 = Flash_Read(pAddr) ; + /* if automatic algorithm is executing */ + while(DFLASH_CHK_TOGG_MASK == (( usSequenceFlag1 ^ usSequenceFlag2) & DFLASH_CHK_TOGG_MASK)) + { + /* if exceeds the timing limit */ + if(DFLASH_CHK_TLOV_MASK == ( usSequenceFlag1 & DFLASH_CHK_TLOV_MASK)) + { + /* set hardware sequence flag */ + usSequenceFlag1 = Flash_Read(pAddr) ; + usSequenceFlag2 = Flash_Read(pAddr) ; + + /* if automatic algorithm is executing */ + if(DFLASH_CHK_TOGG_MASK == (( usSequenceFlag1 ^ usSequenceFlag2) & DFLASH_CHK_TOGG_MASK)) + { + /* abnormally complete */ + ucRetValue = DFLASH_CHK_TOGG_ABNORMAL ; + + break; + } + } + + /* set hardware sequence flag */ + usSequenceFlag1 = Flash_Read(pAddr) ; + usSequenceFlag2 = Flash_Read(pAddr) ; + } + + return ucRetValue ; +} + +#endif + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.h new file mode 100644 index 0000000000..6f267a99ce --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/dualflash.h @@ -0,0 +1,132 @@ +/****************************************************************************** +* \file dualflash.h +* +* \version 1.20 +* +* \brief Headerfile for dual flash functions +* +************************************************************************************* +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +#ifndef _DUALFLASH_H_ +#define _DUALFLASH_H_ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if defined(PDL_PERIPHERAL_DUAL_FLASH_ACTIVE) +/** +* \addtogroup GroupFLASH +* \{ +* \defgroup GroupDFLASH Dual Flash (DFlash) +* \{ +* \defgroup GroupDFLASH_Macros Macros +* \defgroup GroupDFLASH_Functions Functions +* \} +*/ +/** +* \addtogroup GroupDFLASH +* \{ +* The PDL Flash peripheral provides support for working with Dual Operation +* Flash, MainFlash, and WorkFlash. This document discusses Dual Operation Flash.
+* FM0+ parts support Dual Operation Flash. There are two memory banks, the upper +* bank and the lower bank. With Dual Operation Flash you can:
+* - Read both banks
+* - Erase both banks
+* - Read one bank while writing or erasing the other bank
+* \section SectionDFLASH_ConfigurationConsideration Configuration Consideration +* Before using the Dual Flash functions, make sure the Flash operation code is not in the Flash memory +* you are working on.
+* No configuration is required. Simply call the function to erase or write data. +* You can write data using 8-, 16-, or 32-bit alignment.
+* +* \section SectionDFLASH_MoreInfo More Information +* For more information about dual operation Flash support, refer to:
+* +* the Flash Programming Manual for a particular FM0+ microcontroller series
+* +* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupDFLASH_Macros +* \{ +*/ +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +#define FLASH_LOW_BANK1_START_ADDR (uint8_t*)(0x00000000ul) +#define FLASH_LOW_BANK1_END_ADDR (uint8_t*)(0x00003FFFul) +#define FLASH_LOW_BANK2_START_ADDR (uint8_t*)(0x00200000ul) +#define FLASH_LOW_BANK2_END_ADDR (uint8_t*)(0x00208000ul) +#define FLASH_HIGH_BANK_START_ADDR (uint8_t*)(0x00004000ul) +#define FLASH_HIGH_BANK_END_ADDR (uint8_t*)(0x00080000ul) + +#define DFLASH_RET_OK 0u +#define DFLASH_RET_INVALID_PARA 1u +#define DFLASH_RET_ABNORMAL 2u + +#define DFLASH_CHK_TOGG_NORMAL 0u +#define DFLASH_CHK_TOGG_ABNORMAL 1u + +#define DFLASH_CHK_DPOL_NORMAL 0u +#define DFLASH_CHK_DPOL_ABNORMAL 1u + +#define DFLASH_CHK_DPOL_MASK (uint8_t)0x80u +#define DFLASH_CHK_TOGG_MASK (uint8_t)0x40u +#define DFLASH_CHK_TLOV_MASK (uint8_t)0x20u + +/** \} GroupDFLASH_Macros */ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +/** +* \addtogroup GroupDFLASH_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif +en_result_t DFlash_ChipErase(void); +en_result_t DFlash_SectorErase(uint16_t* pu16SecAddr); +en_result_t DFlash_WriteData32Bit( uint32_t* pu32Addr, uint32_t* pu32Data,uint32_t u32Size ); +en_result_t DFlash_WriteData16Bit( uint16_t* pu16Addr, uint16_t* pu16Data, uint32_t u32Size ); +en_result_t DFlash_WriteData8Bit( uint8_t* pu8Addr, uint8_t* pu8Data, uint32_t u32Size ); +#ifdef __cplusplus +} +#endif +/** \} GroupDFLASH_Functions */ +/** \} GroupDFLASH */ +/** \} GroupFLASH */ + +#endif /* PERIPHERAL_AVAILABLE_DUALFLASH */ + +#endif /* _DUALFLASH_H_ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/mainflash.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/mainflash.c new file mode 100644 index 0000000000..838fc32bd9 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/mainflash.c @@ -0,0 +1,850 @@ +/******************************************************************************* +* \file mainflash.c +* +* \version 1.20 +* +* \brief main flash driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "flash/mainflash.h" + +// [andreika]: add volatile to disable optimisations for gcc + +#if defined(PDL_PERIPHERAL_MAIN_FLASH_ACTIVE) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/*! + ****************************************************************************** + ** \brief Read a half word data from Flash + ** \param addr Pointer to read data address + ****************************************************************************** + */ +#define Flash_Read(addr) *(volatile uint16_t*)((uint32_t)(addr)) + +/*! + ****************************************************************************** + ** \brief Wirte a half word data into Flash + ** \param addr Pointer to read data address + ** \param data Write data + ****************************************************************************** + */ +#define Flash_Write(addr, data) *(volatile uint16_t*)((uint32_t)(addr)) = (uint16_t)(data) +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +static en_mflash_toggle_t MFlash_CheckToggle(volatile uint16_t* pAddr ); + +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +static void MFlash_ReadResetCmd(volatile uint16_t* pResetSecAddr); +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/*! + ****************************************************************************** + ** \brief Issue read/reset command + ** + ** \param pu16ResetSecAddr address of sector + ** + ** \return None + ** + ****************************************************************************** + */ +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +static __attribute__((optimize("O0"))) void MFlash_ReadResetCmd(volatile uint16_t* pu16ResetSecAddr) +{ + uint8_t u8Dummy; + + /* issue read/reset command */ + Flash_Write(0x0000u, 0xF0u) ; + u8Dummy = Flash_Read(pu16ResetSecAddr) ; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; + return ; +} + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/*! + ****************************************************************************** + ** \brief Flash chip erase + ** + ** \param bCrRemain Protect CR data or not + ** \arg TRUE Remain CR data after chip erase + ** \arg FALSE CR data will be lost after chip erase + ** + ** \return Operation status + ** \retval Ok Chip erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +en_result_t MFlash_ChipErase(boolean_t bCrRemain) +{ + uint8_t u8Cnt; + uint32_t u32CrData, u32CrAddr; + uint16_t u16WriteData; + en_result_t emRetValue = Ok; +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + uint8_t u8Dummy; +#endif + + __disable_irq(); + +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + + /* Save CR value */ + if (bCrRemain == TRUE) + { + u32CrData = *(uint32_t*)CR_DATA_ADDR; + } + + Flash_Write(MFLASH_CODE1, 0x00AAu); + Flash_Write(MFLASH_CODE2, 0x0055u); + Flash_Write(MFLASH_CODE1, 0x0080u); + Flash_Write(MFLASH_CODE1, 0x00AAu); + Flash_Write(MFLASH_CODE2, 0x0055u); + Flash_Write(MFLASH_CODE1, 0x0010u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( MFLASH_CHK_TOGG_ABNORMAL == MFlash_CheckToggle((uint16_t*)0u)) + { + /* sending the read/reset command to the reset sector */ + MFlash_ReadResetCmd((uint16_t*)0u) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + + /* restore CR data in Flash */ + if (bCrRemain == TRUE) + { + for(u8Cnt=2,u16WriteData=(uint16_t)u32CrData, u32CrAddr = CR_DATA_ADDR;u8Cnt;u8Cnt--) + { + /* issue write command */ + Flash_Write(MFLASH_CODE1, 0x00AAu) ; + Flash_Write(MFLASH_CODE2, 0x0055u) ; + Flash_Write(MFLASH_CODE1, 0x00A0u) ; + Flash_Write((uint16_t*)u32CrAddr, u16WriteData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( MFLASH_CHK_TOGG_ABNORMAL == MFlash_CheckToggle((uint16_t*)u32CrAddr)) || + ( Flash_Read((uint16_t*)u32CrAddr) != u16WriteData)) + { + /* issue read/reset command to reset sector */ + MFlash_ReadResetCmd((uint16_t*)u32CrAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + u16WriteData = (uint16_t)(u32CrData>>16); + u32CrAddr += 2; + } + } + +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + + /* Recover IRQ */ + __enable_irq(); + + return emRetValue; +} + +/*! + ****************************************************************************** + ** \brief Flash sector erase + ** + ** \param pu16SecAddr address of flash sector + ** + ** \return Operation status + ** \retval Ok sector erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +en_result_t __attribute__((optimize("O0"))) MFlash_SectorErase(volatile uint16_t* pu16SecAddr) +{ +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + uint8_t u8Dummy; +#endif + en_result_t emRetValue = Ok; + + __disable_irq(); +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x00AAu); + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x0055u); + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x0080u); + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x00AAu); + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x0055u); + Flash_Write(pu16SecAddr, 0x0030u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( MFLASH_CHK_TOGG_ABNORMAL == MFlash_CheckToggle(pu16SecAddr)) + { + /* sending the read/reset command to the reset sector */ + MFlash_ReadResetCmd(pu16SecAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + /* Recover IRQ */ + __enable_irq(); + return emRetValue; +} + +/*! + ****************************************************************************** + ** \brief Flash word write with ECC + ** + ** \param pu32WriteAddr address of flash data + ** \param pu32WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 32-bit data + ** \param bVerifyAndEccCheck Whether to verify and check ECC + ** + ** \return Operation status + ** \retval Ok Flash written successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** - ECC abnormally + ** + ****************************************************************************** + */ +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +en_result_t MFlash_WriteData32Bit(uint32_t* pu32WriteAddr,\ + uint32_t* pu32WriteData, \ + uint32_t u32Size, \ + boolean_t bVerifyAndEccCheck) +{ + uint16_t *pAddr, *pData; +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + uint8_t u8Dummy; +#endif + en_result_t emRetValue = Ok ; + uint32_t u32Cnt; + pAddr = (uint16_t*)pu32WriteAddr; + pData = (uint16_t*)pu32WriteData; + __disable_irq(); +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + for(u32Cnt=u32Size*sizeof(uint16_t);u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write(MFLASH_CODE1 | ((uint32_t)pAddr & 0xFFFFF000), 0x00AAu) ; + Flash_Write(MFLASH_CODE2 | ((uint32_t)pAddr & 0xFFFFF000), 0x0055u) ; + Flash_Write(MFLASH_CODE1 | ((uint32_t)pAddr & 0xFFFFF000), 0x00A0u) ; + Flash_Write((uint32_t)pAddr, (uint16_t)*pData); + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( MFLASH_CHK_TOGG_ABNORMAL == MFlash_CheckToggle(pAddr)) || + ( Flash_Read((uint32_t)pAddr) != (uint16_t)*pData)) + { + /* issue read/reset command to reset sector */ + MFlash_ReadResetCmd(pAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pAddr++; + pData++; + } +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + /* Recover IRQ */ + __enable_irq(); + +#if ((PDL_MCU_CORE != PDL_FM0P_CORE) && defined(bFM_FLASH_IF_FSTR_ERR)) + if(MFLASH_ECC_ABNORMAL == bVerifyAndEccCheck && 1 == FM_FLASH_IF->FSTR_f.ERR) + { + emRetValue = ErrorInvalidParameter; + bVerifyAndEccCheck = MFLASH_ECC_NORMAL; ///< clear ECC error bit + } +#endif + return emRetValue ; +} +/*! + ****************************************************************************** + ** \brief Flash half word write with ECC + ** + ** \param pu16WriteAddr address of flash data + ** \param pu16WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 16-bit data + ** + ** \return Operation status + ** \retval MFLASH_RET_OK + ** \retval MFLASH_RET_ABNORMAL + ** \retval MFLASH_RET_INVALID_PARA + ** + ****************************************************************************** + */ +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +en_result_t MFlash_WriteData16Bit(uint16_t* pu16WriteAddr, \ + uint16_t* pu16WriteData, \ + uint32_t u32Size) +{ +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + uint8_t u8Dummy; +#endif + en_result_t emRetValue = Ok ; + uint32_t u32Cnt; + + __disable_irq(); +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + for(u32Cnt=u32Size;u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16WriteAddr & 0xFFFFF000), 0x00AAu) ; + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu16WriteAddr & 0xFFFFF000), 0x0055u) ; + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16WriteAddr & 0xFFFFF000), 0x00A0u) ; + Flash_Write(pu16WriteAddr, (uint16_t)*pu16WriteData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( MFLASH_CHK_TOGG_ABNORMAL == MFlash_CheckToggle(pu16WriteAddr)) || + ( Flash_Read(pu16WriteAddr) != *pu16WriteData)) + { + /* issue read/reset command to reset sector */ + MFlash_ReadResetCmd(pu16WriteAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pu16WriteAddr++; + pu16WriteData++; + } +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + /* Recover IRQ */ + __enable_irq(); + return emRetValue ; +} +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +/*! + ****************************************************************************** + ** \brief Flash half word write with ECC + ** + ** \param pu16WriteAddr address of flash data + ** \param pu16WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 16-bit data + ** + ** \return Operation status + ** \retval MFLASH_RET_OK + ** \retval MFLASH_RET_ABNORMAL + ** \retval MFLASH_RET_INVALID_PARA + ** + ****************************************************************************** + */ +en_result_t MFlash_WriteData16Bit_Fm0Type3CrSecureArea(uint16_t* pu16WriteAddr, \ + uint16_t* pu16WriteData, \ + uint32_t u32Size) +{ +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + uint8_t u8Dummy; +#endif + en_result_t emRetValue = Ok ; + uint32_t u32Cnt; + + __disable_irq(); +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + for(u32Cnt=u32Size;u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write(MFLASH_CODE1 , 0x00AAu) ; + Flash_Write(MFLASH_CODE2 , 0x0055u) ; + Flash_Write(MFLASH_CODE1 , 0x00A0u) ; + Flash_Write(pu16WriteAddr, (uint16_t)*pu16WriteData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( MFLASH_CHK_TOGG_ABNORMAL == MFlash_CheckToggle(pu16WriteAddr)) || + ( Flash_Read(pu16WriteAddr) != *pu16WriteData)) + { + /* issue read/reset command to reset sector */ + MFlash_ReadResetCmd(pu16WriteAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pu16WriteAddr++; + pu16WriteData++; + } +#if defined(FM_FLASH_IF_FASZR_AVAILABLE) + FM_FLASH_IF->FASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_FLASH_IF->FASZR; + // [andreika]: fix gcc + (void)(u8Dummy); +#endif + /* Recover IRQ */ + __enable_irq(); + return emRetValue ; +} +/*! + ****************************************************************************** + ** \brief automatic algorithm of flash memory execution + ** + ** \param pu16Addr address of flash data + ** + ** \return Operation status + ** \retval MFLASH_RET_OK + ** \retval MFLASH_RET_ABNORMAL + ** \retval MFLASH_RET_INVALID_PARA + ** + ****************************************************************************** + */ +// [andreika]: remove #if defined ( __ICCARM__ ) +__RAMFUNC +// [andreika]: remove #endif +static en_mflash_toggle_t MFlash_CheckToggle(volatile uint16_t* pu16Addr ) +{ + uint16_t u16SequenceFlag1, u16SequenceFlag2 ; /* hardware sequence flag */ + en_mflash_toggle_t emRetValue = MFLASH_CHK_TOGG_NORMAL ; + + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + /* if automatic algorithm is executing */ + while(MFLASH_CHK_TOGG_MASK == (( u16SequenceFlag1 ^ u16SequenceFlag2) & MFLASH_CHK_TOGG_MASK)) + { + /* if exceeds the timing limit */ + if(( u16SequenceFlag1 & MFLASH_CHK_TLOV_MASK) == MFLASH_CHK_TLOV_MASK) + { + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + + /* if automatic algorithm is executing */ + if((( u16SequenceFlag1 ^ u16SequenceFlag2) & MFLASH_CHK_TOGG_MASK) == MFLASH_CHK_TOGG_MASK) + { + /* abnormally complete */ + emRetValue = MFLASH_CHK_TOGG_ABNORMAL ; + + break; + } + } + + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + } + + return emRetValue ; +} + +#if (PDL_MCU_TYPE == PDL_FM4_TYPE3) +/*! + ****************************************************************************** + ** \brief Issue read/reset command + ** + ** \param pu16ResetSecAddr address of sector + ** + ** \return None + ** + ****************************************************************************** + */ +static void MFlash_DualReadResetCmd(uint16_t* pu16ResetSecAddr) +{ + uint8_t u8Dummy; + + /* issue read/reset command */ + Flash_Write(0x0000u, 0xF0u) ; + u8Dummy = Flash_Read(pu16ResetSecAddr) ; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; + return ; +} + +/*! + ****************************************************************************** + ** \brief automatic algorithm of flash memory execution + ** + ** \param pu16Addr address of flash data + ** + ** \return Operation status + ** \retval MFLASH_RET_OK + ** \retval MFLASH_RET_ABNORMAL + ** \retval MFLASH_RET_INVALID_PARA + ** + ****************************************************************************** + */ +static en_mflash_toggle_t MFlash_DualCheckToggle( uint16_t* pu16Addr ) +{ + uint16_t u16SequenceFlag1, u16SequenceFlag2 ; /* hardware sequence flag */ + en_mflash_toggle_t emRetValue = MFLASH_CHK_TOGG_NORMAL ; + + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + /* if automatic algorithm is executing */ + while(MFLASH_CHK_TOGG_MASK == (( u16SequenceFlag1 ^ u16SequenceFlag2) & MFLASH_CHK_TOGG_MASK)) + { + /* if exceeds the timing limit */ + if(( u16SequenceFlag1 & MFLASH_CHK_TLOV_MASK) == MFLASH_CHK_TLOV_MASK) + { + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + + /* if automatic algorithm is executing */ + if((( u16SequenceFlag1 ^ u16SequenceFlag2) & MFLASH_CHK_TOGG_MASK) == MFLASH_CHK_TOGG_MASK) + { + /* abnormally complete */ + emRetValue = MFLASH_CHK_TOGG_ABNORMAL ; + + break; + } + } + + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + } + + return emRetValue ; +} + +/*! + ****************************************************************************** + ** \brief Dual Flash sector erase + ** + ** \param pu16SecAddr address of flash sector + ** + ** \return Operation status + ** \retval Ok sector erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t MFlash_DualSectorErase(uint16_t* pu16SecAddr) +{ + + uint8_t u8Dummy; + en_result_t emRetValue = Ok; + + + FM_DUALFLASH_IF->DFASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_DUALFLASH_IF->DFASZR; + // [andreika]: fix gcc + (void)(u8Dummy); + + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x00AAu); + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x0055u); + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x0080u); + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x00AAu); + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu16SecAddr & 0xFFFFF000), 0x0055u); + Flash_Write(pu16SecAddr, 0x0030u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( MFLASH_CHK_TOGG_ABNORMAL == MFlash_DualCheckToggle(pu16SecAddr)) + { + /* sending the read/reset command to the reset sector */ + MFlash_DualReadResetCmd(pu16SecAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + + FM_DUALFLASH_IF->DFASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_DUALFLASH_IF->DFASZR; + // [andreika]: fix gcc + (void)(u8Dummy); + + /* Recover IRQ */ + return emRetValue; +} + +/*! + ****************************************************************************** + ** \brief Set Dual Flash Mode of FM4 TYPE3 product + ** + ** \param bDualMode + ** \arg TRUE Dual Flash mode + ** \arg FALSE Single mode or Main Flash mode + ** + ** \return Ok Mode is set + ** + ****************************************************************************** + */ +en_result_t MFlash_SetDualMode(boolean_t bDualMode) +{ + uint32_t u32Reg; + + u32Reg = FM_FLASH_IF->DFCTRLR; + + u32Reg &= ~1ul; // Clear DFE bit + u32Reg |= 0xEACC0000; // Set WKEY + + if(TRUE == bDualMode) + { + u32Reg |= 0x0001; // Set DFE (enable Dual Flash mode) + } + + FM_FLASH_IF->DFCTRLR = u32Reg; + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Set remap function of FM4 TYPE3 product + ** + ** \param bRemapMode + ** \arg TRUE Remap mode + ** \arg FALSE Normal mode + ** + ** \return Ok Mode is set + ** + ** \note This mode is only aviable for S6E2CCA (with 2048k+40k Flash) + ** + ****************************************************************************** + */ +en_result_t MFlash_SetRemapMode(boolean_t bRemapMode) +{ + uint32_t u32Reg; + + u32Reg = FM_FLASH_IF->DFCTRLR; + + u32Reg &= ~2ul; // Clear RME bit + u32Reg |= 0xEACC0000; // Set WKEY + + if(TRUE == bRemapMode) + { + u32Reg |= 0x0002; // Set RME (enable Dual Flash mode) + } + + FM_FLASH_IF->DFCTRLR = u32Reg; + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Dual Flash word write with ECC + ** + ** \param pu32WriteAddr address of flash data + ** \param pu32WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 32-bit data + ** \param bVerifyAndEccCheck Whether to verify and check ECC + ** + ** \return Operation status + ** \retval Ok Dual Flash written successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** - ECC abnormally + ** + ****************************************************************************** + */ +en_result_t MFlash_DualWriteData32Bit(uint32_t* pu32WriteAddr,\ + uint32_t* pu32WriteData, \ + uint32_t u32Size, \ + boolean_t bVerifyAndEccCheck) +{ + uint16_t *pAddr, *pData; + uint8_t u8Dummy; + + en_result_t emRetValue = Ok ; + uint32_t u32Cnt; + pAddr = (uint16_t*)pu32WriteAddr; + pData = (uint16_t*)pu32WriteData; + + FM_DUALFLASH_IF->DFASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_DUALFLASH_IF->DFASZR; + // [andreika]: fix gcc + (void)(u8Dummy); + + for(u32Cnt=u32Size*sizeof(uint16_t);u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu32WriteAddr & 0xFFFFF000), 0x00AAu) ; + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu32WriteAddr & 0xFFFFF000), 0x0055u) ; + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu32WriteAddr & 0xFFFFF000), 0x00A0u) ; + Flash_Write((uint32_t)pAddr, (uint16_t)*pData); + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( MFLASH_CHK_TOGG_ABNORMAL == MFlash_DualCheckToggle(pAddr)) || + ( Flash_Read((uint32_t)pAddr) != (uint16_t)*pData)) + { + /* issue read/reset command to reset sector */ + MFlash_DualReadResetCmd(pAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pAddr++; + pData++; + } + + FM_DUALFLASH_IF->DFASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_DUALFLASH_IF->DFASZR; + // [andreika]: fix gcc + (void)(u8Dummy); + + if(MFLASH_ECC_ABNORMAL == bVerifyAndEccCheck && 1 == FM_DUALFLASH_IF->DFSTR_f.DFERR) + { + emRetValue = ErrorInvalidParameter; + bVerifyAndEccCheck = MFLASH_ECC_NORMAL; ///< clear ECC error bit + } + + return emRetValue ; +} + +/*! + ****************************************************************************** + ** \brief Dual Flash half-word write + ** + ** \param pu16WriteAddr address of flash data + ** \param pu16WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 16-bit data + ** + ** \return Operation status + ** \retval Ok Dual Flash written successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** - ECC abnormally + ** + ****************************************************************************** + */ +en_result_t MFlash_DualWriteData16Bit(uint16_t* pu16WriteAddr, \ + uint16_t* pu16WriteData, \ + uint32_t u32Size) +{ + + uint8_t u8Dummy; + en_result_t emRetValue = Ok ; + uint32_t u32Cnt; + + FM_DUALFLASH_IF->DFASZR = 0x01u; ///< set 16 bit read/write (CPU programming mode) + u8Dummy = FM_DUALFLASH_IF->DFASZR; + // [andreika]: fix gcc + (void)(u8Dummy); + + for(u32Cnt=u32Size;u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16WriteAddr & 0xFFFFF000), 0x00AAu) ; + Flash_Write(MFLASH_CODE2 | ((uint32_t)pu16WriteAddr & 0xFFFFF000), 0x0055u) ; + Flash_Write(MFLASH_CODE1 | ((uint32_t)pu16WriteAddr & 0xFFFFF000), 0x00A0u) ; + Flash_Write(pu16WriteAddr, (uint16_t)*pu16WriteData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( MFLASH_CHK_TOGG_ABNORMAL == MFlash_DualCheckToggle(pu16WriteAddr)) || + ( Flash_Read(pu16WriteAddr) != *pu16WriteData)) + { + /* issue read/reset command to reset sector */ + MFlash_DualReadResetCmd(pu16WriteAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pu16WriteAddr++; + pu16WriteData++; + } + + FM_DUALFLASH_IF->DFASZR = 0x02u; ///< set 32 bit read(CPU ROM mode) + u8Dummy = FM_DUALFLASH_IF->DFASZR; + + return emRetValue ; +} + +#endif + + +#endif +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/mainflash.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/mainflash.h new file mode 100644 index 0000000000..32bdc5fc44 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/mainflash.h @@ -0,0 +1,248 @@ +/****************************************************************************** +* \file mainflash.h +* +* \version 1.20 +* +* \brief Headerfile for main flash functions +* +************************************************************************************* +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +#ifndef _MAINFLASH_H_ +#define _MAINFLASH_H_ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if defined(PDL_PERIPHERAL_MAIN_FLASH_ACTIVE) +/** +* \defgroup GroupFLASH Flash Memory (FLASH) +* \{ +* \defgroup GroupMFLASH Main Flash Memory (MFLASH) +* \{ +* \defgroup GroupMFLASH_Macros Macros +* \defgroup GroupMFLASH_Functions Functions +* \defgroup GroupMFLASH_Types Enumerated Types +* \} +* \} +*/ +/** +* \addtogroup GroupMFLASH +* \{ +* The PDL Flash peripheral provides support for working with Dual Operation Flash, +* MainFlash, and WorkFlash. This document discusses MainFlash.
+* You can erase the entire MainFlash area or erase individual sectors. +* You can write data as words (32-bit) or half-words (16 bit). Built-in Error Correction Code (ECC) +* functionality can correct up to 1 bit of errors in each word. There is no function to detect +* 2-bit errors. Errors are automatically corrected when memory is read. ECC codes +* are automatically added upon writing to flash memory. Because there are no read cycle penalties +* as a result of error correction, it is not necessary to consider the error correction penalties +* during software development.
+* +* \section SectionMFLASH_ConfigurationConsideration Configuration Consideration +* +* Before using the MainFlash functions, ensure that the code is not in the +* flash memory you are working on. For example, in the IAR environment, the key word "__ramfunc" +* puts the code in RAM.
+* +* In the Keil environment, right-click the file with your code and in the options for the file, +* choose a RAM area for the file.
+* +* No configuration is required. Simply call the function to erase or write data. You can write +* data using 16-bit or 32-bit alignment.
+* +* FM4 TYPE3 microcontrollers also support a DualFlash mode. Use MFlash_SetDualMode() +* to activate this operating mode. DualFlash creates a separate Flash area. In DualFlash mode, +* the MFlash_xxx() functions have no effect on the DualFlash area. Use MFlash_Dualxxx() +* functions to erase or write data to the DualFlash area.
+* +* \section SectionMFLASH_MoreInfo More Information +* For more information on the Flash peripheral, refer to:
+* FM0+ Flash Programming Manuals
+* FM4 Flash Programming Manuals
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +/** +* \addtogroup GroupMFLASH_Macros +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief write command + ** + ** To Select write command sequence by MCU type + ******************************************************************************/ +#if (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) ||(PDL_MCU_CORE == PDL_FM4_CORE) + #define MFLASH_CODE1 0x0AA8 + #define MFLASH_CODE2 0x0554 +#elif(PDL_MCU_TYPE == PDL_FM3_TYPE10) || (PDL_MCU_TYPE == PDL_FM3_TYPE11) + #define MFLASH_CODE1 0x0554 + #define MFLASH_CODE2 0x0AA8 +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #define MFLASH_CODE1 0x0A98 + #define MFLASH_CODE2 0x0544 +#else + #define MFLASH_CODE1 0x0AA8 + #define MFLASH_CODE2 0x0554 +#endif +#else + #define MFLASH_CODE1 0x1550 + #define MFLASH_CODE2 0x0AA8 +#endif +/** + ****************************************************************************** + ** \brief main flash check bit mask + ** + ** To Set flash check hardware sequence flag bit mask + ******************************************************************************/ +#define MFLASH_CHK_DPOL_MASK (uint16_t)0x0080 +#define MFLASH_CHK_TOGG_MASK (uint16_t)0x0040 +#define MFLASH_CHK_TLOV_MASK (uint16_t)0x0020 +/** + ****************************************************************************** + ** \brief CR address + ** + ** To Set CR address + ******************************************************************************/ +#define CR_DATA_ADDR (0x00100004) + +/** \} GroupMFLASH_Macros */ + +/** +* \addtogroup GroupMFLASH_Types +* \{ +*/ +/** + ****************************************************************************** + ** \brief state feedback + ** + ** To feedback the flash operation state + ******************************************************************************/ +typedef enum en_mflash_state +{ + MFLASH_RET_OK, ///< OK + MFLASH_RET_INVALID_PARA, ///< parameter error + MFLASH_RET_ABNORMAL, ///< operation fail + MFLASH_RET_ECCERROR ///< flash ECC verify error +}en_mflash_state_t; +/** + ****************************************************************************** + ** \brief check toggle state + ** + ** To feedback the flash toggle state + ******************************************************************************/ +typedef enum en_mflash_toggle +{ + MFLASH_CHK_TOGG_NORMAL, ///< flash toggle normal + MFLASH_CHK_TOGG_ABNORMAL ///< flash toggle abnormal +}en_mflash_toggle_t; +/** + ****************************************************************************** + ** \brief check toggle state + ** + ** To feedback the flash toggle state + ******************************************************************************/ +typedef enum en_mflash_datapoll +{ + MFLASH_CHK_DPOL_NORMAL, ///< data poll normal + MFLASH_CHK_DPOL_ABNORMAL ///< data poll abnormal +}en_mflash_datapoll_t; +/** + ****************************************************************************** + ** \brief check toggle state + ** + ** To feedback the flash toggle state + ******************************************************************************/ +typedef enum en_mflash_eccbitstat +{ + MFLASH_ECC_NORMAL, ///< data poll normal + MFLASH_ECC_ABNORMAL ///< data poll abnormal +}en_mflash_eccbitstat_t; + +/** \}GroupMFLASH_Types */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +/** +* \addtogroup GroupMFLASH_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif + +// [andreika]: todo: add gcc support? +#if defined ( __ICCARM__ ) +#define __RAMFUNC __ramfunc +#elif defined ( __GNUC__ ) +#define __RAMFUNC __attribute__( ( section(".data") ) ) +#else +#define __RAMFUNC +#endif + +// [andreika]: add __RAMFUNC and volatile +__RAMFUNC en_result_t MFlash_ChipErase(boolean_t bCrRemain); +__RAMFUNC en_result_t MFlash_SectorErase(volatile uint16_t* pu16SecAddr); +__RAMFUNC en_result_t MFlash_WriteData32Bit(uint32_t* pu32WriteAddr, + uint32_t* pu32WriteData, + uint32_t u32Size, + boolean_t bVerifyAndEccCheck); +__RAMFUNC en_result_t MFlash_WriteData16Bit(uint16_t* pu16WriteAddr, + uint16_t* pu16WriteData, + uint32_t u32Size); +__RAMFUNC en_result_t MFlash_WriteData16Bit_Fm0Type3CrSecureArea(uint16_t* pu16WriteAddr, + uint16_t* pu16WriteData, + uint32_t u32Size); +#if (PDL_MCU_TYPE == PDL_FM4_TYPE3) +en_result_t MFlash_SetDualMode(boolean_t bDualMode); +en_result_t MFlash_SetRemapMode(boolean_t bRemapMode); +en_result_t MFlash_DualSectorErase(uint16_t* pu16SecAddr); +en_result_t MFlash_DualWriteData32Bit(uint32_t* pu32WriteAddr,\ + uint32_t* pu32WriteData, \ + uint32_t u32Size, \ + boolean_t bVerifyAndEccCheck); +en_result_t MFlash_DualWriteData16Bit(uint16_t* pu16WriteAddr, \ + uint16_t* pu16WriteData, \ + uint32_t u32Size); +/** \} GroupMFLASH_Functions */ +/** \} GroupMFLASH */ +/** \} GroupFLASH */ +#endif +#ifdef __cplusplus +} +#endif + + +#endif /* PERIPHERAL_AVAILABLE_MAINFLASH */ + +#endif /* _MAINFLASH_FM_H_ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/workflash.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/workflash.c new file mode 100644 index 0000000000..853d8b9612 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/workflash.c @@ -0,0 +1,357 @@ +/******************************************************************************* +* \file workflash.c +* +* \version 1.20 +* +* \brief work flash driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "flash/workflash.h" + +#if defined(PDL_PERIPHERAL_WORK_FLASH_ACTIVE) + +/*! + ****************************************************************************** + ** \brief Read a half word data from Flash + ** \param addr Pointer to read data address + ****************************************************************************** + */ +#define Flash_Read(addr) *(volatile uint16_t*)((uint32_t)(addr)) + +/*! + ****************************************************************************** + ** \brief Wirte a half word data into Flash + ** \param addr Pointer to read data address + ** \param data Write data + ****************************************************************************** + */ +#define Flash_Write(addr, data) *(volatile uint16_t*)((uint32_t)(addr)) = ( uint16_t)(data) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +static uint8_t WFlash_CheckToggle( uint16_t* pAddr ); +static void WFlash_ReadResetCmd(uint16_t* pu16ResetSecAddr); + +/*! + ****************************************************************************** + ** \brief Issue read/reset command + ** + ** \param pu16ResetSecAddr address of reset sector + ** + ** \return None + ** + ****************************************************************************** + */ +static void WFlash_ReadResetCmd(uint16_t* pu16ResetSecAddr) +{ + uint8_t u8Dummy; + + /* issue read/reset command */ + Flash_Write(0x0000u, 0xF0u) ; + u8Dummy = Flash_Read(pu16ResetSecAddr) ; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; + return ; +} + +/*! + ****************************************************************************** + ** \brief Flash chip erase + ** + ** \return Operation status + ** \retval Ok Chip erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t WFlash_ChipErase(void) +{ + en_result_t emRetValue = Ok; +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + uint8_t u8Dummy; + FM_WORKFLASH_IF->WFASZR = 0x00u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; +#endif + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00AAu); + Flash_Write((WFLASH_CODE2 | WFLASH_BASE_ADDR), 0x0055u); + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x0080u); + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00AAu); + Flash_Write((WFLASH_CODE2| WFLASH_BASE_ADDR), 0x0055u); + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x0010u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( WFLASH_CHK_TOGG_ABNORMAL == WFlash_CheckToggle((uint16_t*)WFLASH_BASE_ADDR) ) + { + /* sending the read/reset command to the reset sector */ + WFlash_ReadResetCmd((uint16_t*)WFLASH_BASE_ADDR) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + + /* CPU ROM mode setting */ +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x01u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; +#endif + + return emRetValue; +} + +/*! + ****************************************************************************** + ** \brief Flash sector erase + ** + ** \param pu16SecAddr address of flash sector + ** + ** \return Operation status + ** \retval Ok Chip erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t WFlash_SectorErase(uint16_t* pu16SecAddr) +{ + en_result_t emRetValue = Ok; +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + uint8_t u8Dummy; +#endif +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x00u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; +#endif + + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00AAu); + Flash_Write((WFLASH_CODE2 | WFLASH_BASE_ADDR), 0x0055u); + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x0080u); + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00AAu); + Flash_Write((WFLASH_CODE2 | WFLASH_BASE_ADDR), 0x0055u); + Flash_Write(pu16SecAddr, 0x0030u); + + /* if execution result of the automatic algorithm of flash memory is abnormally completed */ + if( WFLASH_CHK_TOGG_ABNORMAL == WFlash_CheckToggle(pu16SecAddr) ) + { + /* sending the read/reset command to the reset sector */ + WFlash_ReadResetCmd(pu16SecAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + + /* CPU ROM mode setting */ +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x01u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; +#endif + return emRetValue; +} + +/*! + ****************************************************************************** + ** \brief Flash word write with ECC + ** + ** \param pu32WriteAddr address of flash data + ** \param pu32WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 16-bit data, always set it to even + ** + ** \return Operation status + ** \retval Ok Chip erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t WFlash_WriteData32Bit(uint32_t* pu32WriteAddr, + uint32_t* pu32WriteData, + uint32_t u32Size) +{ + uint16_t *pAddr, *pData; + en_result_t emRetValue = Ok; + uint32_t u32Cnt; +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + uint8_t u8Dummy; +#endif + pAddr = (uint16_t*)pu32WriteAddr; + pData = (uint16_t*)pu32WriteData; + /* CPU programming mode setting */ +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x00u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; +#endif + + for(u32Cnt=u32Size*sizeof(uint16_t);u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00AAu) ; + Flash_Write((WFLASH_CODE2 | WFLASH_BASE_ADDR), 0x0055u) ; + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00A0u) ; + Flash_Write((uint32_t)pAddr, (uint16_t)*pData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( WFLASH_CHK_TOGG_ABNORMAL == WFlash_CheckToggle(pAddr) ) || + ( Flash_Read((uint32_t)pAddr) != (uint16_t)*pData)) + { + /* issue read/reset command to reset sector */ + WFlash_ReadResetCmd(pAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pAddr++; + pData++; + } + + /* CPU ROM mode setting */ +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x01u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; +#endif + return emRetValue ; +} +/*! + ****************************************************************************** + ** \brief Flash half-word write with ECC + ** + ** \param pu16WriteAddr address of flash data + ** \param pu16WriteData pointer to write data + ** \param u32Size data size, 1 indicates 1 16-bit data, always set it to even + ** + ** \return Operation status + ** \retval Ok Chip erase successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - automatic algorithm of flash memory execution abnormally + ** + ****************************************************************************** + */ +en_result_t WFlash_WriteData16Bit(uint16_t* pu16WriteAddr, + uint16_t* pu16WriteData, + uint32_t u32Size) +{ + en_result_t emRetValue = Ok; + uint32_t u32Cnt; +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + uint8_t u8Dummy; +#endif + + /* CPU programming mode setting */ +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x00u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; + // [andreika]: fix gcc + (void)(u8Dummy) /* avoid warning */ + ; +#endif + + for(u32Cnt=u32Size;u32Cnt;u32Cnt--) + { + /* issue write command */ + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00AA) ; + Flash_Write((WFLASH_CODE2 | WFLASH_BASE_ADDR), 0x0055) ; + Flash_Write((WFLASH_CODE1 | WFLASH_BASE_ADDR), 0x00A0) ; + Flash_Write(pu16WriteAddr, (uint16_t)*pu16WriteData); + + /* execution result of the automatic algorithm of flash memory is abnormally complete or verify error */ + if(( WFLASH_CHK_TOGG_ABNORMAL == WFlash_CheckToggle(pu16WriteAddr) ) || + ( Flash_Read(pu16WriteAddr) != *pu16WriteData)) + { + /* issue read/reset command to reset sector */ + WFlash_ReadResetCmd(pu16WriteAddr) ; + + /* return flash operation abnormally */ + emRetValue = ErrorInvalidParameter ; + } + /* Prepare next h-word write */ + pu16WriteAddr++; + pu16WriteData++; + } + + /* CPU ROM mode setting */ +#if (PDL_MCU_CORE != PDL_FM0P_CORE) + FM_WORKFLASH_IF->WFASZR = 0x01u; + u8Dummy = FM_WORKFLASH_IF->WFASZR; +#endif + return emRetValue ; +} +/*! + ****************************************************************************** + ** \brief automatic algorithm of flash memory execution + ** + ** \param pu16Addr address of flash data + ** + ** \return Operation status + ** \retval MFLASH_RET_OK + ** \retval MFLASH_RET_ABNORMAL + ** \retval MFLASH_RET_INVALID_PARA + ** + ****************************************************************************** + */ +static uint8_t WFlash_CheckToggle( uint16_t* pu16Addr ) +{ + uint16_t u16SequenceFlag1, u16SequenceFlag2 ; /* hardware sequence flag */ + uint8_t u8RetValue = WFLASH_CHK_TOGG_NORMAL ; + + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + /* if automatic algorithm is executing */ + while(WFLASH_CHK_TOGG_MASK == (( u16SequenceFlag1 ^ u16SequenceFlag2) & WFLASH_CHK_TOGG_MASK)) + { + /* if exceeds the timing limit */ + if(WFLASH_CHK_TLOV_MASK == ( u16SequenceFlag1 & WFLASH_CHK_TLOV_MASK ) ) + { + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + + /* if automatic algorithm is executing */ + if(WFLASH_CHK_TOGG_MASK == (( u16SequenceFlag1 ^ u16SequenceFlag2) & WFLASH_CHK_TOGG_MASK)) + { + /* abnormally complete */ + u8RetValue = WFLASH_CHK_TOGG_ABNORMAL ; + + break; + } + } + + /* set hardware sequence flag */ + u16SequenceFlag1 = Flash_Read(pu16Addr) ; + u16SequenceFlag2 = Flash_Read(pu16Addr) ; + } + + return u8RetValue ; +} + +#endif + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/workflash.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/workflash.h new file mode 100644 index 0000000000..32258f74ee --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/flash/workflash.h @@ -0,0 +1,123 @@ +/****************************************************************************** +* \file workflash.h +* +* \version 1.20 +* +* \brief Headerfile for work flash functions +* +************************************************************************************* +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef _WORK_FLASH_H_ +#define _WORK_FLASH_H_ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if defined(PDL_PERIPHERAL_WORK_FLASH_ACTIVE) +/** +* \addtogroup GroupFLASH +* \{ +* \defgroup GroupWFLASH Work Flash (WFlash) +* \{ +* \defgroup GroupWFLASH_Macros Macros +* \defgroup GroupWFLASH_Functions Functions +* \} +*/ +/** +* \addtogroup GroupWFLASH +*\{ +* The PDL Flash peripheral provides support for working with Dual Operation Flash, +* MainFlash, and WorkFlash. This document discusses WorkFlash.
+* You can erase the entire WorkFlash memory or erase individual sectors. +* You can write data as words (32-bit) or half-words (16 bit).
+* \section SectionWFLASH_ConfigurationConsideration Configuration Consideration +* WorkFlash is an independent area, separate from MainFlash. You can run code in +* MainFlash that operates on WorkFlash.
+* No configuration is required. Simply call the function to erase or write data. +* You can write data using 16-bit or 32-bit alignment.
+* \section SectionWFLASH_MoreInfo More Information +* For more information on the Flash peripheral, refer to:
+* FM0+ Flash Programming Manuals
+* FM4 Flash Programming Manuals
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupWFLASH_Macros +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define WFLASH_CODE1 0x0AA8u +#define WFLASH_CODE2 0x0554u + +#define WFLASH_RET_OK 0u +#define WFLASH_RET_INVALID_PARA 1u +#define WFLASH_RET_ABNORMAL 2u + +#define WFLASH_CHK_TOGG_NORMAL 0u +#define WFLASH_CHK_TOGG_ABNORMAL 1u + +#define WFLASH_CHK_DPOL_NORMAL 0u +#define WFLASH_CHK_DPOL_ABNORMAL 1u + +#define WFLASH_CHK_DPOL_MASK (uint16_t)0x0080u +#define WFLASH_CHK_TOGG_MASK (uint16_t)0x0040u +#define WFLASH_CHK_TLOV_MASK (uint16_t)0x0020u + +#define WFLASH_BASE_ADDR (0x200C0000u) + +/** \} GroupWFLASH_Macros */ + +/** +* \addtogroup GroupWFLASH_Functions +* \{ +*/ +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#ifdef __cplusplus +extern "C" { +#endif +en_result_t WFlash_ChipErase(void); +en_result_t WFlash_SectorErase(uint16_t* pu16Addr); +en_result_t WFlash_WriteData32Bit(uint32_t* pu32Addr, + uint32_t* pu32Data, + uint32_t u32Size); +en_result_t WFlash_WriteData16Bit(uint16_t* pu16Addr, + uint16_t* pu16Data, + uint32_t u32Size); + +/** \} GroupWFLASH_Functions */ +/** \} GroupWFLASH */ +/** \} GroupFLASH */ +#ifdef __cplusplus +} +#endif + +#endif /* PERIPHERAL_AVAILABLE_WORKFLASH */ + +#endif /* _WORKFLASH_FM3_H_ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/fgpio.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/fgpio.h new file mode 100644 index 0000000000..cfd3d1f9ae --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/fgpio.h @@ -0,0 +1,192 @@ +/****************************************************************************** +* \file fgpio.h +* +* \version 1.20 +* +* \brief Headerfile for Fast GPIO driver +* +****************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __FGPIO_H__ +#define __FGPIO_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/** +* \addtogroup GroupGPIO +* \{ +* \defgroup GroupFGPIO Fast General-purpose I/O ports (FGPIO) +* \{ +* \defgroup GroupFGPIO_Macros Macros +* \defgroup GroupFGPIO_DataStructures Data Structures +* \defgroup GroupFGPIO_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupFGPIO +* \{ +* FM0+ supports Fast General-purpose I/O ports. By default, all I/O ports operate +* as normal GPIO. You can assign any pin to be a Fast GPIO pin. Fast GPIO can read an +* input level and set an output level from the CPU in one cycle of HCLK.
+* +* \section SectionFGPIO_ConfigurationConsideration Configuration Consideration +* To set a pin to be Fast GPIO, use the FGpio_EnableOutput() macro. You provide +* the port, and a 16-bit value as parameters. The 16-bit value specifies which +* pins within the port to enable for Fast GPIO. A bit value of 1 in any position enables +* that pin. For example, this code sets Port 3 pin E to be a Fast GPIO pin.
+* // Pin F E D C B A 9 8 7 6 5 4 3 2 1 0
+* // Val 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 or 0x4000u
+* FGpio_EnableOutput(FGpioPort3, 0x4000u);
+* Once enabled as Fast GPIO, you use other macros to set or get pin direction, level, and pullup state.
+* Note: If the bus clock of a GPIO is gated, some functions of the I/O port cannot be used.
+* \attention +* - Before using the Fast GPIO output, you must call the FGpio_EnableOutput() macro. +* \section SectionFGPIO_MoreInfo More Information +* For more information on the GPIO peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem
+* +* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* +* all FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets can be downloaded
+* +*/ + +/** +* \addtogroup GroupFGPIO_Macros +* \{ +*/ + +/******************************************************************************/ +/* Defines */ +/******************************************************************************/ + +#define FGpio_EnableOutput(port, pins) do {uint32_t addr; \ + addr = (uint32_t)&FM_GPIO->FPOER0 + (uint32_t)port*4u; \ + *(uint16_t*)(addr) = pins; \ + }while(0); +#define FGpio_DisableOutput(port) do {uint32_t addr; \ + addr = (uint32_t)&FM_GPIO->FPOER0 + (uint32_t)port*4u; \ + *(uint16_t*)(addr) = 0x0000u; \ + }while(0); + +#define FGpio1pin_InitIn(p,settings) do{ stc_fgpio1pin_init_t __v__;\ + __v__.bPullup=0u;__v__.bInitVal=0u;\ + (settings);\ + p##_INITIN(__v__); }while(0) + +#define FGpio1pin_InitOut(p,settings) do{ stc_fgpio1pin_init_t __v__;\ + __v__.bPullup=0u;__v__.bInitVal=0u;\ + (settings);\ + p##_INITOUT(__v__); }while(0) + +#define FGpio1pin_Init(p,settings) do{ stc_fgpio1pin_init_t __v__;__v__.bOutput=0u;\ + __v__.bPullup=0u;__v__.bInitVal=0u;\ + (settings);\ + p##_INIT( __v__ ); }while(0) + +#define FGpio1pin_InitDirectionInput (__v__.bOutput=0u) +#define FGpio1pin_InitDirectionOutput (__v__.bOutput=1u) +#define FGpio1pin_InitPullup(v) (__v__.bPullup=(v)) +#define FGpio1pin_InitVal(v) (__v__.bInitVal=(v)) + + + +#define FGpio1pin_Get(p) p##_GET +#define FGpio1pin_Put(p,v) p##_PUT(v) + + +/******************************************************************************/ +/* Inclusion of GPIO defines of user defined device */ +/******************************************************************************/ +/** \} GroupFGPIO_Macros */ + +/** +* \addtogroup GroupFGPIO_Types +* \{ +*/ + + +/** + ****************************************************************************** + ** \brief GPIO port list + ******************************************************************************/ +typedef enum en_fgpio_port +{ + FGpioPort0 = 0u, ///< Fast GPIO port 0 + FGpioPort1 = 1u, ///< Fast GPIO port 1 + FGpioPort2 = 2u, ///< Fast GPIO port 2 + FGpioPort3 = 3u, ///< Fast GPIO port 3 + FGpioPort4 = 4u, ///< Fast GPIO port 4 + FGpioPort5 = 5u, ///< Fast GPIO port 5 + FGpioPort6 = 6u, ///< Fast GPIO port 6 + FGpioPort7 = 7u, ///< Fast GPIO port 7 + FGpioPort8 = 8u, ///< Fast GPIO port 8 + FGpioPort9 = 9u, ///< Fast GPIO port 9 + FGpioPortA = 10u, ///< Fast GPIO port 10 + FGpioPortB = 11u, ///< Fast GPIO port 11 + FGpioPortC = 12u, ///< Fast GPIO port 12 + FGpioPortD = 13u, ///< Fast GPIO port 13 + FGpioPortE = 14u, ///< Fast GPIO port 14 + FGpioPortF = 15u, ///< Fast GPIO port 15 + +}en_fgpio_port_t; + +/** \}GroupFGPIO_Types */ + +/** +* \addtogroup GroupFGPIO_DataStructures +* \{ +*/ +/** + ****************************************************************************** + ** + ** Definitions of Fast GPIO and resource pin relocation + ** + ** \attention + ** - before using the Fast GPIO output, FGpio_EnableOutput() has + ** to be called. + ******************************************************************************/ + +/******************************************************************************/ +/* \brief Fast GPIO intialization structure */ +/******************************************************************************/ + +typedef struct stc_fgpio1pin_init +{ + boolean_t bOutput; + boolean_t bInitVal; + boolean_t bPullup; +} stc_fgpio1pin_init_t; + +/** \}GroupFGPIO_DataStructures */ +/** \} GroupFGPIO */ +/** \} GroupGPIO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FPIO_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio.h new file mode 100644 index 0000000000..439d308366 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio.h @@ -0,0 +1,142 @@ +/****************************************************************************** +* \file gpio.h +* +* \version 1.20 +* +* \brief Headerfile for Definitions of GPIO and resource pin relocation +* +******************************************************************************* +\copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupGPIO General-Purpose I/O ports (GPIO) +* \{ +* \defgroup GroupGPIO_Macros Macros +* \defgroup GroupGPIO_DataStructures Data Structures +* \} +*/ + +/** +* \addtogroup GroupGPIO +* \{ +* The PDL provides macros you can use to manage pins for General-purpose I/O ports. +* If you use the macros you need to know which pin to use, but do not need to know the pin registers. +* Macros enable you to:
+* - Set a pin as an output or input pin
+* - Set a pin to an initial level (high or low)
+* - Set a pin’s pullup
+* - Get or set a pin’s level
+* For FM0+ see also Fast General-purpose IO Ports.
+* +* \section SectionGPIO_ConfigurationConsideration Configuration Consideration +* There is no configuration structure for GPIO. Use the appropriate macro to accomplish your task. +* The macros have one or two parameters.
+* One parameter is the name of the pin. The file gpio.h defines pin names, in the form:
+* GPIO1PIN_P. So, for Port 1, Pin A, the name is GPIO1PIN_P1A.
+* The second parameter (when there are two) is simply the value you want to use.
+* For example, you might write code like this:
+* Gpio1pin_InitOut(GPIO1PIN_P1A, Gpio1pin_InitVal( 1u ) );
+* This code initializes Port 1 Pin A to be an output pin, with initial level high.
+* Note: if the bus clock of a GPIO is gated, some functions of the I/O port cannot be used.
+* \section SectionGPIO_MoreInfo More Information +* For more information on the GPIO peripheral, refer to:
+* FM0+ Peripheral Manual Core Subsystem
+* FM4 Peripheral Manual Core Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupGPIO_Macros +* \{ +*/ + +/******************************************************************************/ +/* Defines */ +/******************************************************************************/ + +#define Gpio1pin_InitIn(p,settings) do{ stc_gpio1pin_init_t __v__;\ + __v__.bPullup=0u;__v__.bInitVal=0u;\ + (settings);\ + p##_INITIN(__v__); }while(0) + +#define Gpio1pin_InitOut(p,settings) do{ stc_gpio1pin_init_t __v__;\ + __v__.bPullup=0u;__v__.bInitVal=0u;\ + (settings);\ + p##_INITOUT(__v__); }while(0) + +#define Gpio1pin_Init(p,settings) do{ stc_gpio1pin_init_t __v__;__v__.bOutput=0u;\ + __v__.bPullup=0u;__v__.bInitVal=0u;\ + (settings);\ + p##_INIT( __v__ ); }while(0) + +#define Gpio1pin_InitDirectionInput (__v__.bOutput=0u) +#define Gpio1pin_InitDirectionOutput (__v__.bOutput=1u) +#define Gpio1pin_InitPullup(v) (__v__.bPullup=(v)) +#define Gpio1pin_InitVal(v) (__v__.bInitVal=(v)) + + + +#define Gpio1pin_Get(p) p##_GET +#define Gpio1pin_Put(p,v) p##_PUT(v) + +#define PINRELOC_SET_EPFR(epfr,pos,width,value) \ + ((epfr) = ((epfr) & ~(((1u<<(width))-1u)<<(pos))) | \ + ((value) << (pos))) + +/** \} GroupGPIO_Macros */ +/** +* \addtogroup GroupGPIO_DataStructures +* \{ +*/ +/******************************************************************************/ +/* Types */ +/******************************************************************************/ + +typedef struct stc_gpio1pin_init +{ + boolean_t bOutput; + boolean_t bInitVal; + boolean_t bPullup; +} stc_gpio1pin_init_t; + +/** \}GroupGPIO_DataStructures */ +/** \} GroupGPIO */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio_s6e2c5xh.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio_s6e2c5xh.h new file mode 100644 index 0000000000..6a35fd8500 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio_s6e2c5xh.h @@ -0,0 +1,7281 @@ +/************************************************************************************* +* Copyright (C) 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* +* This software, including source code, documentation and related +* materials ( "Software" ), is owned by Cypress Semiconductor +* Corporation ( "Cypress" ) and is protected by and subject to worldwide +* patent protection (United States and foreign), United States copyright +* laws and international treaty provisions. Therefore, you may use this +* Software only as provided in the license agreement accompanying the +* software package from which you obtained this Software ( "EULA" ). +* If no EULA applies, Cypress hereby grants you a personal, nonexclusive, +* non-transferable license to copy, modify, and compile the +* Software source code solely for use in connection with Cypress's +* integrated circuit products. Any reproduction, modification, translation, +* compilation, or representation of this Software except as specified +* above is prohibited without the express written permission of Cypress. +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE. Cypress reserves the right to make +* changes to the Software without notice. Cypress does not assume any +* liability arising out of the application or use of the Software or any +* product or circuit described in the Software. Cypress does not +* authorize its products for use in any products where a malfunction or +* failure of the Cypress product may reasonably be expected to result in +* significant property damage, injury or death ( "High Risk Product" ). By +* including Cypress's product in a High Risk Product, the manufacturer +* of such system or application assumes all risk of such use and in doing +* so agrees to indemnify Cypress against all liability. +*/ +/************************************************************************************/ +/** \file gpio_s6e2c5xh.h + ** + ** Header file for S6E2C5XH GPIO functions, included in gpio.h + ** + ** History: + ** - 2015-12-04 2.0 NOSU Clean ALL FM Series pin files + ** + ** Timestamp: + ** - 2015-12-16 18:30:36 Auto created by GpioHeaderGenerator Rev 1.0.0 + ** + ******************************************************************************/ + +#ifndef __GPIO_S6E2C5XH_H__ +#define __GPIO_S6E2C5XH_H__ + +#include + +#define PINCONFIG_SET_REG(pinreg,pos,width,value) \ + ((pinreg) = ((pinreg) & ~(((1u<<(width))-1u)<<(pos)) | \ + ((value) << (pos)))) + +/****************************************************************************** + GPIO +*******************************************************************************/ + +/*---- GPIO bit P00 ----*/ +#define GPIO1PIN_P00_GET ( bFM_GPIO_PDIR0_P0 ) + +#define GPIO1PIN_P00_PUT(v) ( bFM_GPIO_PDOR0_P0=(v) ) + +#define GPIO1PIN_P00_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P00_INITIN(v) \ + : GPIO1PIN_P00_INITOUT(v) ) + +#define GPIO1PIN_P00_INITIN(v) do{ \ + bFM_GPIO_PCR0_P0=(v).bPullup; \ + bFM_GPIO_DDR0_P0=0u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +#define GPIO1PIN_P00_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P0=(v).bInitVal; \ + bFM_GPIO_DDR0_P0=1u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +/*---- GPIO bit NP00 ----*/ +#define GPIO1PIN_NP00_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P0)) ) + +#define GPIO1PIN_NP00_PUT(v) ( bFM_GPIO_PDOR0_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP00_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP00_INITIN(v) \ + : GPIO1PIN_NP00_INITOUT(v) ) + +#define GPIO1PIN_NP00_INITIN(v) do{ \ + bFM_GPIO_PCR0_P0=(v).bPullup; \ + bFM_GPIO_DDR0_P0=0u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +#define GPIO1PIN_NP00_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P0=1u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +/*---- GPIO bit P01 ----*/ +#define GPIO1PIN_P01_GET ( bFM_GPIO_PDIR0_P1 ) + +#define GPIO1PIN_P01_PUT(v) ( bFM_GPIO_PDOR0_P1=(v) ) + +#define GPIO1PIN_P01_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P01_INITIN(v) \ + : GPIO1PIN_P01_INITOUT(v) ) + +#define GPIO1PIN_P01_INITIN(v) do{ \ + bFM_GPIO_PCR0_P1=(v).bPullup; \ + bFM_GPIO_DDR0_P1=0u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +#define GPIO1PIN_P01_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P1=(v).bInitVal; \ + bFM_GPIO_DDR0_P1=1u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +/*---- GPIO bit NP01 ----*/ +#define GPIO1PIN_NP01_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P1)) ) + +#define GPIO1PIN_NP01_PUT(v) ( bFM_GPIO_PDOR0_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP01_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP01_INITIN(v) \ + : GPIO1PIN_NP01_INITOUT(v) ) + +#define GPIO1PIN_NP01_INITIN(v) do{ \ + bFM_GPIO_PCR0_P1=(v).bPullup; \ + bFM_GPIO_DDR0_P1=0u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +#define GPIO1PIN_NP01_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P1=1u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +/*---- GPIO bit P02 ----*/ +#define GPIO1PIN_P02_GET ( bFM_GPIO_PDIR0_P2 ) + +#define GPIO1PIN_P02_PUT(v) ( bFM_GPIO_PDOR0_P2=(v) ) + +#define GPIO1PIN_P02_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P02_INITIN(v) \ + : GPIO1PIN_P02_INITOUT(v) ) + +#define GPIO1PIN_P02_INITIN(v) do{ \ + bFM_GPIO_PCR0_P2=(v).bPullup; \ + bFM_GPIO_DDR0_P2=0u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +#define GPIO1PIN_P02_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P2=(v).bInitVal; \ + bFM_GPIO_DDR0_P2=1u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +/*---- GPIO bit NP02 ----*/ +#define GPIO1PIN_NP02_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P2)) ) + +#define GPIO1PIN_NP02_PUT(v) ( bFM_GPIO_PDOR0_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP02_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP02_INITIN(v) \ + : GPIO1PIN_NP02_INITOUT(v) ) + +#define GPIO1PIN_NP02_INITIN(v) do{ \ + bFM_GPIO_PCR0_P2=(v).bPullup; \ + bFM_GPIO_DDR0_P2=0u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +#define GPIO1PIN_NP02_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P2=1u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +/*---- GPIO bit P03 ----*/ +#define GPIO1PIN_P03_GET ( bFM_GPIO_PDIR0_P3 ) + +#define GPIO1PIN_P03_PUT(v) ( bFM_GPIO_PDOR0_P3=(v) ) + +#define GPIO1PIN_P03_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P03_INITIN(v) \ + : GPIO1PIN_P03_INITOUT(v) ) + +#define GPIO1PIN_P03_INITIN(v) do{ \ + bFM_GPIO_PCR0_P3=(v).bPullup; \ + bFM_GPIO_DDR0_P3=0u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +#define GPIO1PIN_P03_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P3=(v).bInitVal; \ + bFM_GPIO_DDR0_P3=1u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +/*---- GPIO bit NP03 ----*/ +#define GPIO1PIN_NP03_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P3)) ) + +#define GPIO1PIN_NP03_PUT(v) ( bFM_GPIO_PDOR0_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP03_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP03_INITIN(v) \ + : GPIO1PIN_NP03_INITOUT(v) ) + +#define GPIO1PIN_NP03_INITIN(v) do{ \ + bFM_GPIO_PCR0_P3=(v).bPullup; \ + bFM_GPIO_DDR0_P3=0u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +#define GPIO1PIN_NP03_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P3=1u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +/*---- GPIO bit P04 ----*/ +#define GPIO1PIN_P04_GET ( bFM_GPIO_PDIR0_P4 ) + +#define GPIO1PIN_P04_PUT(v) ( bFM_GPIO_PDOR0_P4=(v) ) + +#define GPIO1PIN_P04_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P04_INITIN(v) \ + : GPIO1PIN_P04_INITOUT(v) ) + +#define GPIO1PIN_P04_INITIN(v) do{ \ + bFM_GPIO_PCR0_P4=(v).bPullup; \ + bFM_GPIO_DDR0_P4=0u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +#define GPIO1PIN_P04_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P4=(v).bInitVal; \ + bFM_GPIO_DDR0_P4=1u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +/*---- GPIO bit NP04 ----*/ +#define GPIO1PIN_NP04_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P4)) ) + +#define GPIO1PIN_NP04_PUT(v) ( bFM_GPIO_PDOR0_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP04_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP04_INITIN(v) \ + : GPIO1PIN_NP04_INITOUT(v) ) + +#define GPIO1PIN_NP04_INITIN(v) do{ \ + bFM_GPIO_PCR0_P4=(v).bPullup; \ + bFM_GPIO_DDR0_P4=0u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +#define GPIO1PIN_NP04_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P4=1u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +/*---- GPIO bit P08 ----*/ +#define GPIO1PIN_P08_GET ( bFM_GPIO_PDIR0_P8 ) + +#define GPIO1PIN_P08_PUT(v) ( bFM_GPIO_PDOR0_P8=(v) ) + +#define GPIO1PIN_P08_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P08_INITIN(v) \ + : GPIO1PIN_P08_INITOUT(v) ) + +#define GPIO1PIN_P08_INITIN(v) do{ \ + bFM_GPIO_PCR0_P8=(v).bPullup; \ + bFM_GPIO_DDR0_P8=0u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +#define GPIO1PIN_P08_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P8=(v).bInitVal; \ + bFM_GPIO_DDR0_P8=1u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +/*---- GPIO bit NP08 ----*/ +#define GPIO1PIN_NP08_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P8)) ) + +#define GPIO1PIN_NP08_PUT(v) ( bFM_GPIO_PDOR0_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP08_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP08_INITIN(v) \ + : GPIO1PIN_NP08_INITOUT(v) ) + +#define GPIO1PIN_NP08_INITIN(v) do{ \ + bFM_GPIO_PCR0_P8=(v).bPullup; \ + bFM_GPIO_DDR0_P8=0u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +#define GPIO1PIN_NP08_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P8=1u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +/*---- GPIO bit P09 ----*/ +#define GPIO1PIN_P09_GET ( bFM_GPIO_PDIR0_P9 ) + +#define GPIO1PIN_P09_PUT(v) ( bFM_GPIO_PDOR0_P9=(v) ) + +#define GPIO1PIN_P09_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P09_INITIN(v) \ + : GPIO1PIN_P09_INITOUT(v) ) + +#define GPIO1PIN_P09_INITIN(v) do{ \ + bFM_GPIO_PCR0_P9=(v).bPullup; \ + bFM_GPIO_DDR0_P9=0u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +#define GPIO1PIN_P09_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P9=(v).bInitVal; \ + bFM_GPIO_DDR0_P9=1u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +/*---- GPIO bit NP09 ----*/ +#define GPIO1PIN_NP09_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P9)) ) + +#define GPIO1PIN_NP09_PUT(v) ( bFM_GPIO_PDOR0_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP09_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP09_INITIN(v) \ + : GPIO1PIN_NP09_INITOUT(v) ) + +#define GPIO1PIN_NP09_INITIN(v) do{ \ + bFM_GPIO_PCR0_P9=(v).bPullup; \ + bFM_GPIO_DDR0_P9=0u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +#define GPIO1PIN_NP09_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P9=1u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +/*---- GPIO bit P0A ----*/ +#define GPIO1PIN_P0A_GET ( bFM_GPIO_PDIR0_PA ) + +#define GPIO1PIN_P0A_PUT(v) ( bFM_GPIO_PDOR0_PA=(v) ) + +#define GPIO1PIN_P0A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P0A_INITIN(v) \ + : GPIO1PIN_P0A_INITOUT(v) ) + +#define GPIO1PIN_P0A_INITIN(v) do{ \ + bFM_GPIO_PCR0_PA=(v).bPullup; \ + bFM_GPIO_DDR0_PA=0u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +#define GPIO1PIN_P0A_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_PA=(v).bInitVal; \ + bFM_GPIO_DDR0_PA=1u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +/*---- GPIO bit NP0A ----*/ +#define GPIO1PIN_NP0A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_PA)) ) + +#define GPIO1PIN_NP0A_PUT(v) ( bFM_GPIO_PDOR0_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP0A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP0A_INITIN(v) \ + : GPIO1PIN_NP0A_INITOUT(v) ) + +#define GPIO1PIN_NP0A_INITIN(v) do{ \ + bFM_GPIO_PCR0_PA=(v).bPullup; \ + bFM_GPIO_DDR0_PA=0u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +#define GPIO1PIN_NP0A_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_PA=1u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +/*---- GPIO bit P10 ----*/ +#define GPIO1PIN_P10_GET ( bFM_GPIO_PDIR1_P0 ) + +#define GPIO1PIN_P10_PUT(v) ( bFM_GPIO_PDOR1_P0=(v) ) + +#define GPIO1PIN_P10_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P10_INITIN(v) \ + : GPIO1PIN_P10_INITOUT(v) ) + +#define GPIO1PIN_P10_INITIN(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PCR1_P0=(v).bPullup; \ + bFM_GPIO_DDR1_P0=0u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +#define GPIO1PIN_P10_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PDOR1_P0=(v).bInitVal; \ + bFM_GPIO_DDR1_P0=1u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +/*---- GPIO bit NP10 ----*/ +#define GPIO1PIN_NP10_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P0)) ) + +#define GPIO1PIN_NP10_PUT(v) ( bFM_GPIO_PDOR1_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP10_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP10_INITIN(v) \ + : GPIO1PIN_NP10_INITOUT(v) ) + +#define GPIO1PIN_NP10_INITIN(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PCR1_P0=(v).bPullup; \ + bFM_GPIO_DDR1_P0=0u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +#define GPIO1PIN_NP10_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PDOR1_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P0=1u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +/*---- GPIO bit P11 ----*/ +#define GPIO1PIN_P11_GET ( bFM_GPIO_PDIR1_P1 ) + +#define GPIO1PIN_P11_PUT(v) ( bFM_GPIO_PDOR1_P1=(v) ) + +#define GPIO1PIN_P11_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P11_INITIN(v) \ + : GPIO1PIN_P11_INITOUT(v) ) + +#define GPIO1PIN_P11_INITIN(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PCR1_P1=(v).bPullup; \ + bFM_GPIO_DDR1_P1=0u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +#define GPIO1PIN_P11_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PDOR1_P1=(v).bInitVal; \ + bFM_GPIO_DDR1_P1=1u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +/*---- GPIO bit NP11 ----*/ +#define GPIO1PIN_NP11_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P1)) ) + +#define GPIO1PIN_NP11_PUT(v) ( bFM_GPIO_PDOR1_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP11_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP11_INITIN(v) \ + : GPIO1PIN_NP11_INITOUT(v) ) + +#define GPIO1PIN_NP11_INITIN(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PCR1_P1=(v).bPullup; \ + bFM_GPIO_DDR1_P1=0u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +#define GPIO1PIN_NP11_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PDOR1_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P1=1u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +/*---- GPIO bit P12 ----*/ +#define GPIO1PIN_P12_GET ( bFM_GPIO_PDIR1_P2 ) + +#define GPIO1PIN_P12_PUT(v) ( bFM_GPIO_PDOR1_P2=(v) ) + +#define GPIO1PIN_P12_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P12_INITIN(v) \ + : GPIO1PIN_P12_INITOUT(v) ) + +#define GPIO1PIN_P12_INITIN(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PCR1_P2=(v).bPullup; \ + bFM_GPIO_DDR1_P2=0u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +#define GPIO1PIN_P12_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PDOR1_P2=(v).bInitVal; \ + bFM_GPIO_DDR1_P2=1u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +/*---- GPIO bit NP12 ----*/ +#define GPIO1PIN_NP12_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P2)) ) + +#define GPIO1PIN_NP12_PUT(v) ( bFM_GPIO_PDOR1_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP12_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP12_INITIN(v) \ + : GPIO1PIN_NP12_INITOUT(v) ) + +#define GPIO1PIN_NP12_INITIN(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PCR1_P2=(v).bPullup; \ + bFM_GPIO_DDR1_P2=0u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +#define GPIO1PIN_NP12_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PDOR1_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P2=1u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +/*---- GPIO bit P13 ----*/ +#define GPIO1PIN_P13_GET ( bFM_GPIO_PDIR1_P3 ) + +#define GPIO1PIN_P13_PUT(v) ( bFM_GPIO_PDOR1_P3=(v) ) + +#define GPIO1PIN_P13_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P13_INITIN(v) \ + : GPIO1PIN_P13_INITOUT(v) ) + +#define GPIO1PIN_P13_INITIN(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PCR1_P3=(v).bPullup; \ + bFM_GPIO_DDR1_P3=0u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +#define GPIO1PIN_P13_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PDOR1_P3=(v).bInitVal; \ + bFM_GPIO_DDR1_P3=1u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +/*---- GPIO bit NP13 ----*/ +#define GPIO1PIN_NP13_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P3)) ) + +#define GPIO1PIN_NP13_PUT(v) ( bFM_GPIO_PDOR1_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP13_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP13_INITIN(v) \ + : GPIO1PIN_NP13_INITOUT(v) ) + +#define GPIO1PIN_NP13_INITIN(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PCR1_P3=(v).bPullup; \ + bFM_GPIO_DDR1_P3=0u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +#define GPIO1PIN_NP13_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PDOR1_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P3=1u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +/*---- GPIO bit P14 ----*/ +#define GPIO1PIN_P14_GET ( bFM_GPIO_PDIR1_P4 ) + +#define GPIO1PIN_P14_PUT(v) ( bFM_GPIO_PDOR1_P4=(v) ) + +#define GPIO1PIN_P14_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P14_INITIN(v) \ + : GPIO1PIN_P14_INITOUT(v) ) + +#define GPIO1PIN_P14_INITIN(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PCR1_P4=(v).bPullup; \ + bFM_GPIO_DDR1_P4=0u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +#define GPIO1PIN_P14_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PDOR1_P4=(v).bInitVal; \ + bFM_GPIO_DDR1_P4=1u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +/*---- GPIO bit NP14 ----*/ +#define GPIO1PIN_NP14_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P4)) ) + +#define GPIO1PIN_NP14_PUT(v) ( bFM_GPIO_PDOR1_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP14_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP14_INITIN(v) \ + : GPIO1PIN_NP14_INITOUT(v) ) + +#define GPIO1PIN_NP14_INITIN(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PCR1_P4=(v).bPullup; \ + bFM_GPIO_DDR1_P4=0u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +#define GPIO1PIN_NP14_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PDOR1_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P4=1u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +/*---- GPIO bit P15 ----*/ +#define GPIO1PIN_P15_GET ( bFM_GPIO_PDIR1_P5 ) + +#define GPIO1PIN_P15_PUT(v) ( bFM_GPIO_PDOR1_P5=(v) ) + +#define GPIO1PIN_P15_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P15_INITIN(v) \ + : GPIO1PIN_P15_INITOUT(v) ) + +#define GPIO1PIN_P15_INITIN(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PCR1_P5=(v).bPullup; \ + bFM_GPIO_DDR1_P5=0u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +#define GPIO1PIN_P15_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PDOR1_P5=(v).bInitVal; \ + bFM_GPIO_DDR1_P5=1u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +/*---- GPIO bit NP15 ----*/ +#define GPIO1PIN_NP15_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P5)) ) + +#define GPIO1PIN_NP15_PUT(v) ( bFM_GPIO_PDOR1_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP15_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP15_INITIN(v) \ + : GPIO1PIN_NP15_INITOUT(v) ) + +#define GPIO1PIN_NP15_INITIN(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PCR1_P5=(v).bPullup; \ + bFM_GPIO_DDR1_P5=0u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +#define GPIO1PIN_NP15_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PDOR1_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P5=1u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +/*---- GPIO bit P16 ----*/ +#define GPIO1PIN_P16_GET ( bFM_GPIO_PDIR1_P6 ) + +#define GPIO1PIN_P16_PUT(v) ( bFM_GPIO_PDOR1_P6=(v) ) + +#define GPIO1PIN_P16_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P16_INITIN(v) \ + : GPIO1PIN_P16_INITOUT(v) ) + +#define GPIO1PIN_P16_INITIN(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PCR1_P6=(v).bPullup; \ + bFM_GPIO_DDR1_P6=0u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +#define GPIO1PIN_P16_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PDOR1_P6=(v).bInitVal; \ + bFM_GPIO_DDR1_P6=1u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +/*---- GPIO bit NP16 ----*/ +#define GPIO1PIN_NP16_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P6)) ) + +#define GPIO1PIN_NP16_PUT(v) ( bFM_GPIO_PDOR1_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP16_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP16_INITIN(v) \ + : GPIO1PIN_NP16_INITOUT(v) ) + +#define GPIO1PIN_NP16_INITIN(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PCR1_P6=(v).bPullup; \ + bFM_GPIO_DDR1_P6=0u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +#define GPIO1PIN_NP16_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PDOR1_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P6=1u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +/*---- GPIO bit P17 ----*/ +#define GPIO1PIN_P17_GET ( bFM_GPIO_PDIR1_P7 ) + +#define GPIO1PIN_P17_PUT(v) ( bFM_GPIO_PDOR1_P7=(v) ) + +#define GPIO1PIN_P17_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P17_INITIN(v) \ + : GPIO1PIN_P17_INITOUT(v) ) + +#define GPIO1PIN_P17_INITIN(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PCR1_P7=(v).bPullup; \ + bFM_GPIO_DDR1_P7=0u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +#define GPIO1PIN_P17_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PDOR1_P7=(v).bInitVal; \ + bFM_GPIO_DDR1_P7=1u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +/*---- GPIO bit NP17 ----*/ +#define GPIO1PIN_NP17_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P7)) ) + +#define GPIO1PIN_NP17_PUT(v) ( bFM_GPIO_PDOR1_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP17_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP17_INITIN(v) \ + : GPIO1PIN_NP17_INITOUT(v) ) + +#define GPIO1PIN_NP17_INITIN(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PCR1_P7=(v).bPullup; \ + bFM_GPIO_DDR1_P7=0u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +#define GPIO1PIN_NP17_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PDOR1_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P7=1u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +/*---- GPIO bit P18 ----*/ +#define GPIO1PIN_P18_GET ( bFM_GPIO_PDIR1_P8 ) + +#define GPIO1PIN_P18_PUT(v) ( bFM_GPIO_PDOR1_P8=(v) ) + +#define GPIO1PIN_P18_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P18_INITIN(v) \ + : GPIO1PIN_P18_INITOUT(v) ) + +#define GPIO1PIN_P18_INITIN(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PCR1_P8=(v).bPullup; \ + bFM_GPIO_DDR1_P8=0u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +#define GPIO1PIN_P18_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PDOR1_P8=(v).bInitVal; \ + bFM_GPIO_DDR1_P8=1u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +/*---- GPIO bit NP18 ----*/ +#define GPIO1PIN_NP18_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P8)) ) + +#define GPIO1PIN_NP18_PUT(v) ( bFM_GPIO_PDOR1_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP18_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP18_INITIN(v) \ + : GPIO1PIN_NP18_INITOUT(v) ) + +#define GPIO1PIN_NP18_INITIN(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PCR1_P8=(v).bPullup; \ + bFM_GPIO_DDR1_P8=0u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +#define GPIO1PIN_NP18_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PDOR1_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P8=1u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +/*---- GPIO bit P19 ----*/ +#define GPIO1PIN_P19_GET ( bFM_GPIO_PDIR1_P9 ) + +#define GPIO1PIN_P19_PUT(v) ( bFM_GPIO_PDOR1_P9=(v) ) + +#define GPIO1PIN_P19_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P19_INITIN(v) \ + : GPIO1PIN_P19_INITOUT(v) ) + +#define GPIO1PIN_P19_INITIN(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PCR1_P9=(v).bPullup; \ + bFM_GPIO_DDR1_P9=0u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +#define GPIO1PIN_P19_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PDOR1_P9=(v).bInitVal; \ + bFM_GPIO_DDR1_P9=1u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +/*---- GPIO bit NP19 ----*/ +#define GPIO1PIN_NP19_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P9)) ) + +#define GPIO1PIN_NP19_PUT(v) ( bFM_GPIO_PDOR1_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP19_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP19_INITIN(v) \ + : GPIO1PIN_NP19_INITOUT(v) ) + +#define GPIO1PIN_NP19_INITIN(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PCR1_P9=(v).bPullup; \ + bFM_GPIO_DDR1_P9=0u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +#define GPIO1PIN_NP19_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PDOR1_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P9=1u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +/*---- GPIO bit P1A ----*/ +#define GPIO1PIN_P1A_GET ( bFM_GPIO_PDIR1_PA ) + +#define GPIO1PIN_P1A_PUT(v) ( bFM_GPIO_PDOR1_PA=(v) ) + +#define GPIO1PIN_P1A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1A_INITIN(v) \ + : GPIO1PIN_P1A_INITOUT(v) ) + +#define GPIO1PIN_P1A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PCR1_PA=(v).bPullup; \ + bFM_GPIO_DDR1_PA=0u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +#define GPIO1PIN_P1A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PDOR1_PA=(v).bInitVal; \ + bFM_GPIO_DDR1_PA=1u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +/*---- GPIO bit NP1A ----*/ +#define GPIO1PIN_NP1A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PA)) ) + +#define GPIO1PIN_NP1A_PUT(v) ( bFM_GPIO_PDOR1_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1A_INITIN(v) \ + : GPIO1PIN_NP1A_INITOUT(v) ) + +#define GPIO1PIN_NP1A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PCR1_PA=(v).bPullup; \ + bFM_GPIO_DDR1_PA=0u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +#define GPIO1PIN_NP1A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PDOR1_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PA=1u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +/*---- GPIO bit P1B ----*/ +#define GPIO1PIN_P1B_GET ( bFM_GPIO_PDIR1_PB ) + +#define GPIO1PIN_P1B_PUT(v) ( bFM_GPIO_PDOR1_PB=(v) ) + +#define GPIO1PIN_P1B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1B_INITIN(v) \ + : GPIO1PIN_P1B_INITOUT(v) ) + +#define GPIO1PIN_P1B_INITIN(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PCR1_PB=(v).bPullup; \ + bFM_GPIO_DDR1_PB=0u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +#define GPIO1PIN_P1B_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PDOR1_PB=(v).bInitVal; \ + bFM_GPIO_DDR1_PB=1u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +/*---- GPIO bit NP1B ----*/ +#define GPIO1PIN_NP1B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PB)) ) + +#define GPIO1PIN_NP1B_PUT(v) ( bFM_GPIO_PDOR1_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1B_INITIN(v) \ + : GPIO1PIN_NP1B_INITOUT(v) ) + +#define GPIO1PIN_NP1B_INITIN(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PCR1_PB=(v).bPullup; \ + bFM_GPIO_DDR1_PB=0u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +#define GPIO1PIN_NP1B_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PDOR1_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PB=1u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +/*---- GPIO bit P1C ----*/ +#define GPIO1PIN_P1C_GET ( bFM_GPIO_PDIR1_PC ) + +#define GPIO1PIN_P1C_PUT(v) ( bFM_GPIO_PDOR1_PC=(v) ) + +#define GPIO1PIN_P1C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1C_INITIN(v) \ + : GPIO1PIN_P1C_INITOUT(v) ) + +#define GPIO1PIN_P1C_INITIN(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PCR1_PC=(v).bPullup; \ + bFM_GPIO_DDR1_PC=0u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +#define GPIO1PIN_P1C_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PDOR1_PC=(v).bInitVal; \ + bFM_GPIO_DDR1_PC=1u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +/*---- GPIO bit NP1C ----*/ +#define GPIO1PIN_NP1C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PC)) ) + +#define GPIO1PIN_NP1C_PUT(v) ( bFM_GPIO_PDOR1_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1C_INITIN(v) \ + : GPIO1PIN_NP1C_INITOUT(v) ) + +#define GPIO1PIN_NP1C_INITIN(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PCR1_PC=(v).bPullup; \ + bFM_GPIO_DDR1_PC=0u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +#define GPIO1PIN_NP1C_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PDOR1_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PC=1u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +/*---- GPIO bit P1D ----*/ +#define GPIO1PIN_P1D_GET ( bFM_GPIO_PDIR1_PD ) + +#define GPIO1PIN_P1D_PUT(v) ( bFM_GPIO_PDOR1_PD=(v) ) + +#define GPIO1PIN_P1D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1D_INITIN(v) \ + : GPIO1PIN_P1D_INITOUT(v) ) + +#define GPIO1PIN_P1D_INITIN(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PCR1_PD=(v).bPullup; \ + bFM_GPIO_DDR1_PD=0u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +#define GPIO1PIN_P1D_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PDOR1_PD=(v).bInitVal; \ + bFM_GPIO_DDR1_PD=1u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +/*---- GPIO bit NP1D ----*/ +#define GPIO1PIN_NP1D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PD)) ) + +#define GPIO1PIN_NP1D_PUT(v) ( bFM_GPIO_PDOR1_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1D_INITIN(v) \ + : GPIO1PIN_NP1D_INITOUT(v) ) + +#define GPIO1PIN_NP1D_INITIN(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PCR1_PD=(v).bPullup; \ + bFM_GPIO_DDR1_PD=0u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +#define GPIO1PIN_NP1D_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PDOR1_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PD=1u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +/*---- GPIO bit P1E ----*/ +#define GPIO1PIN_P1E_GET ( bFM_GPIO_PDIR1_PE ) + +#define GPIO1PIN_P1E_PUT(v) ( bFM_GPIO_PDOR1_PE=(v) ) + +#define GPIO1PIN_P1E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1E_INITIN(v) \ + : GPIO1PIN_P1E_INITOUT(v) ) + +#define GPIO1PIN_P1E_INITIN(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PCR1_PE=(v).bPullup; \ + bFM_GPIO_DDR1_PE=0u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +#define GPIO1PIN_P1E_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PDOR1_PE=(v).bInitVal; \ + bFM_GPIO_DDR1_PE=1u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +/*---- GPIO bit NP1E ----*/ +#define GPIO1PIN_NP1E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PE)) ) + +#define GPIO1PIN_NP1E_PUT(v) ( bFM_GPIO_PDOR1_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1E_INITIN(v) \ + : GPIO1PIN_NP1E_INITOUT(v) ) + +#define GPIO1PIN_NP1E_INITIN(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PCR1_PE=(v).bPullup; \ + bFM_GPIO_DDR1_PE=0u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +#define GPIO1PIN_NP1E_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PDOR1_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PE=1u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +/*---- GPIO bit P1F ----*/ +#define GPIO1PIN_P1F_GET ( bFM_GPIO_PDIR1_PF ) + +#define GPIO1PIN_P1F_PUT(v) ( bFM_GPIO_PDOR1_PF=(v) ) + +#define GPIO1PIN_P1F_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1F_INITIN(v) \ + : GPIO1PIN_P1F_INITOUT(v) ) + +#define GPIO1PIN_P1F_INITIN(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PCR1_PF=(v).bPullup; \ + bFM_GPIO_DDR1_PF=0u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +#define GPIO1PIN_P1F_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PDOR1_PF=(v).bInitVal; \ + bFM_GPIO_DDR1_PF=1u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +/*---- GPIO bit NP1F ----*/ +#define GPIO1PIN_NP1F_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PF)) ) + +#define GPIO1PIN_NP1F_PUT(v) ( bFM_GPIO_PDOR1_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1F_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1F_INITIN(v) \ + : GPIO1PIN_NP1F_INITOUT(v) ) + +#define GPIO1PIN_NP1F_INITIN(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PCR1_PF=(v).bPullup; \ + bFM_GPIO_DDR1_PF=0u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +#define GPIO1PIN_NP1F_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PDOR1_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PF=1u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +/*---- GPIO bit P20 ----*/ +#define GPIO1PIN_P20_GET ( bFM_GPIO_PDIR2_P0 ) + +#define GPIO1PIN_P20_PUT(v) ( bFM_GPIO_PDOR2_P0=(v) ) + +#define GPIO1PIN_P20_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P20_INITIN(v) \ + : GPIO1PIN_P20_INITOUT(v) ) + +#define GPIO1PIN_P20_INITIN(v) do{ \ + bFM_GPIO_PCR2_P0=(v).bPullup; \ + bFM_GPIO_DDR2_P0=0u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +#define GPIO1PIN_P20_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P0=(v).bInitVal; \ + bFM_GPIO_DDR2_P0=1u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +/*---- GPIO bit NP20 ----*/ +#define GPIO1PIN_NP20_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P0)) ) + +#define GPIO1PIN_NP20_PUT(v) ( bFM_GPIO_PDOR2_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP20_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP20_INITIN(v) \ + : GPIO1PIN_NP20_INITOUT(v) ) + +#define GPIO1PIN_NP20_INITIN(v) do{ \ + bFM_GPIO_PCR2_P0=(v).bPullup; \ + bFM_GPIO_DDR2_P0=0u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +#define GPIO1PIN_NP20_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P0=1u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +/*---- GPIO bit P21 ----*/ +#define GPIO1PIN_P21_GET ( bFM_GPIO_PDIR2_P1 ) + +#define GPIO1PIN_P21_PUT(v) ( bFM_GPIO_PDOR2_P1=(v) ) + +#define GPIO1PIN_P21_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P21_INITIN(v) \ + : GPIO1PIN_P21_INITOUT(v) ) + +#define GPIO1PIN_P21_INITIN(v) do{ \ + bFM_GPIO_PCR2_P1=(v).bPullup; \ + bFM_GPIO_DDR2_P1=0u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +#define GPIO1PIN_P21_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P1=(v).bInitVal; \ + bFM_GPIO_DDR2_P1=1u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +/*---- GPIO bit NP21 ----*/ +#define GPIO1PIN_NP21_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P1)) ) + +#define GPIO1PIN_NP21_PUT(v) ( bFM_GPIO_PDOR2_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP21_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP21_INITIN(v) \ + : GPIO1PIN_NP21_INITOUT(v) ) + +#define GPIO1PIN_NP21_INITIN(v) do{ \ + bFM_GPIO_PCR2_P1=(v).bPullup; \ + bFM_GPIO_DDR2_P1=0u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +#define GPIO1PIN_NP21_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P1=1u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +/*---- GPIO bit P22 ----*/ +#define GPIO1PIN_P22_GET ( bFM_GPIO_PDIR2_P2 ) + +#define GPIO1PIN_P22_PUT(v) ( bFM_GPIO_PDOR2_P2=(v) ) + +#define GPIO1PIN_P22_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P22_INITIN(v) \ + : GPIO1PIN_P22_INITOUT(v) ) + +#define GPIO1PIN_P22_INITIN(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PCR2_P2=(v).bPullup; \ + bFM_GPIO_DDR2_P2=0u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +#define GPIO1PIN_P22_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PDOR2_P2=(v).bInitVal; \ + bFM_GPIO_DDR2_P2=1u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +/*---- GPIO bit NP22 ----*/ +#define GPIO1PIN_NP22_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P2)) ) + +#define GPIO1PIN_NP22_PUT(v) ( bFM_GPIO_PDOR2_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP22_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP22_INITIN(v) \ + : GPIO1PIN_NP22_INITOUT(v) ) + +#define GPIO1PIN_NP22_INITIN(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PCR2_P2=(v).bPullup; \ + bFM_GPIO_DDR2_P2=0u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +#define GPIO1PIN_NP22_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PDOR2_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P2=1u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +/*---- GPIO bit P23 ----*/ +#define GPIO1PIN_P23_GET ( bFM_GPIO_PDIR2_P3 ) + +#define GPIO1PIN_P23_PUT(v) ( bFM_GPIO_PDOR2_P3=(v) ) + +#define GPIO1PIN_P23_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P23_INITIN(v) \ + : GPIO1PIN_P23_INITOUT(v) ) + +#define GPIO1PIN_P23_INITIN(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PCR2_P3=(v).bPullup; \ + bFM_GPIO_DDR2_P3=0u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +#define GPIO1PIN_P23_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PDOR2_P3=(v).bInitVal; \ + bFM_GPIO_DDR2_P3=1u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +/*---- GPIO bit NP23 ----*/ +#define GPIO1PIN_NP23_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P3)) ) + +#define GPIO1PIN_NP23_PUT(v) ( bFM_GPIO_PDOR2_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP23_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP23_INITIN(v) \ + : GPIO1PIN_NP23_INITOUT(v) ) + +#define GPIO1PIN_NP23_INITIN(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PCR2_P3=(v).bPullup; \ + bFM_GPIO_DDR2_P3=0u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +#define GPIO1PIN_NP23_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PDOR2_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P3=1u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +/*---- GPIO bit P24 ----*/ +#define GPIO1PIN_P24_GET ( bFM_GPIO_PDIR2_P4 ) + +#define GPIO1PIN_P24_PUT(v) ( bFM_GPIO_PDOR2_P4=(v) ) + +#define GPIO1PIN_P24_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P24_INITIN(v) \ + : GPIO1PIN_P24_INITOUT(v) ) + +#define GPIO1PIN_P24_INITIN(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PCR2_P4=(v).bPullup; \ + bFM_GPIO_DDR2_P4=0u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +#define GPIO1PIN_P24_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PDOR2_P4=(v).bInitVal; \ + bFM_GPIO_DDR2_P4=1u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +/*---- GPIO bit NP24 ----*/ +#define GPIO1PIN_NP24_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P4)) ) + +#define GPIO1PIN_NP24_PUT(v) ( bFM_GPIO_PDOR2_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP24_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP24_INITIN(v) \ + : GPIO1PIN_NP24_INITOUT(v) ) + +#define GPIO1PIN_NP24_INITIN(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PCR2_P4=(v).bPullup; \ + bFM_GPIO_DDR2_P4=0u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +#define GPIO1PIN_NP24_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PDOR2_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P4=1u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +/*---- GPIO bit P25 ----*/ +#define GPIO1PIN_P25_GET ( bFM_GPIO_PDIR2_P5 ) + +#define GPIO1PIN_P25_PUT(v) ( bFM_GPIO_PDOR2_P5=(v) ) + +#define GPIO1PIN_P25_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P25_INITIN(v) \ + : GPIO1PIN_P25_INITOUT(v) ) + +#define GPIO1PIN_P25_INITIN(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PCR2_P5=(v).bPullup; \ + bFM_GPIO_DDR2_P5=0u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +#define GPIO1PIN_P25_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PDOR2_P5=(v).bInitVal; \ + bFM_GPIO_DDR2_P5=1u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +/*---- GPIO bit NP25 ----*/ +#define GPIO1PIN_NP25_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P5)) ) + +#define GPIO1PIN_NP25_PUT(v) ( bFM_GPIO_PDOR2_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP25_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP25_INITIN(v) \ + : GPIO1PIN_NP25_INITOUT(v) ) + +#define GPIO1PIN_NP25_INITIN(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PCR2_P5=(v).bPullup; \ + bFM_GPIO_DDR2_P5=0u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +#define GPIO1PIN_NP25_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PDOR2_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P5=1u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +/*---- GPIO bit P26 ----*/ +#define GPIO1PIN_P26_GET ( bFM_GPIO_PDIR2_P6 ) + +#define GPIO1PIN_P26_PUT(v) ( bFM_GPIO_PDOR2_P6=(v) ) + +#define GPIO1PIN_P26_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P26_INITIN(v) \ + : GPIO1PIN_P26_INITOUT(v) ) + +#define GPIO1PIN_P26_INITIN(v) do{ \ + bFM_GPIO_PCR2_P6=(v).bPullup; \ + bFM_GPIO_DDR2_P6=0u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +#define GPIO1PIN_P26_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P6=(v).bInitVal; \ + bFM_GPIO_DDR2_P6=1u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +/*---- GPIO bit NP26 ----*/ +#define GPIO1PIN_NP26_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P6)) ) + +#define GPIO1PIN_NP26_PUT(v) ( bFM_GPIO_PDOR2_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP26_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP26_INITIN(v) \ + : GPIO1PIN_NP26_INITOUT(v) ) + +#define GPIO1PIN_NP26_INITIN(v) do{ \ + bFM_GPIO_PCR2_P6=(v).bPullup; \ + bFM_GPIO_DDR2_P6=0u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +#define GPIO1PIN_NP26_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P6=1u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +/*---- GPIO bit P27 ----*/ +#define GPIO1PIN_P27_GET ( bFM_GPIO_PDIR2_P7 ) + +#define GPIO1PIN_P27_PUT(v) ( bFM_GPIO_PDOR2_P7=(v) ) + +#define GPIO1PIN_P27_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P27_INITIN(v) \ + : GPIO1PIN_P27_INITOUT(v) ) + +#define GPIO1PIN_P27_INITIN(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PCR2_P7=(v).bPullup; \ + bFM_GPIO_DDR2_P7=0u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +#define GPIO1PIN_P27_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PDOR2_P7=(v).bInitVal; \ + bFM_GPIO_DDR2_P7=1u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +/*---- GPIO bit NP27 ----*/ +#define GPIO1PIN_NP27_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P7)) ) + +#define GPIO1PIN_NP27_PUT(v) ( bFM_GPIO_PDOR2_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP27_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP27_INITIN(v) \ + : GPIO1PIN_NP27_INITOUT(v) ) + +#define GPIO1PIN_NP27_INITIN(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PCR2_P7=(v).bPullup; \ + bFM_GPIO_DDR2_P7=0u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +#define GPIO1PIN_NP27_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PDOR2_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P7=1u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +/*---- GPIO bit P28 ----*/ +#define GPIO1PIN_P28_GET ( bFM_GPIO_PDIR2_P8 ) + +#define GPIO1PIN_P28_PUT(v) ( bFM_GPIO_PDOR2_P8=(v) ) + +#define GPIO1PIN_P28_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P28_INITIN(v) \ + : GPIO1PIN_P28_INITOUT(v) ) + +#define GPIO1PIN_P28_INITIN(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PCR2_P8=(v).bPullup; \ + bFM_GPIO_DDR2_P8=0u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +#define GPIO1PIN_P28_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PDOR2_P8=(v).bInitVal; \ + bFM_GPIO_DDR2_P8=1u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +/*---- GPIO bit NP28 ----*/ +#define GPIO1PIN_NP28_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P8)) ) + +#define GPIO1PIN_NP28_PUT(v) ( bFM_GPIO_PDOR2_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP28_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP28_INITIN(v) \ + : GPIO1PIN_NP28_INITOUT(v) ) + +#define GPIO1PIN_NP28_INITIN(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PCR2_P8=(v).bPullup; \ + bFM_GPIO_DDR2_P8=0u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +#define GPIO1PIN_NP28_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PDOR2_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P8=1u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +/*---- GPIO bit P29 ----*/ +#define GPIO1PIN_P29_GET ( bFM_GPIO_PDIR2_P9 ) + +#define GPIO1PIN_P29_PUT(v) ( bFM_GPIO_PDOR2_P9=(v) ) + +#define GPIO1PIN_P29_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P29_INITIN(v) \ + : GPIO1PIN_P29_INITOUT(v) ) + +#define GPIO1PIN_P29_INITIN(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PCR2_P9=(v).bPullup; \ + bFM_GPIO_DDR2_P9=0u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +#define GPIO1PIN_P29_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PDOR2_P9=(v).bInitVal; \ + bFM_GPIO_DDR2_P9=1u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +/*---- GPIO bit NP29 ----*/ +#define GPIO1PIN_NP29_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P9)) ) + +#define GPIO1PIN_NP29_PUT(v) ( bFM_GPIO_PDOR2_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP29_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP29_INITIN(v) \ + : GPIO1PIN_NP29_INITOUT(v) ) + +#define GPIO1PIN_NP29_INITIN(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PCR2_P9=(v).bPullup; \ + bFM_GPIO_DDR2_P9=0u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +#define GPIO1PIN_NP29_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PDOR2_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P9=1u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +/*---- GPIO bit P2A ----*/ +#define GPIO1PIN_P2A_GET ( bFM_GPIO_PDIR2_PA ) + +#define GPIO1PIN_P2A_PUT(v) ( bFM_GPIO_PDOR2_PA=(v) ) + +#define GPIO1PIN_P2A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P2A_INITIN(v) \ + : GPIO1PIN_P2A_INITOUT(v) ) + +#define GPIO1PIN_P2A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PCR2_PA=(v).bPullup; \ + bFM_GPIO_DDR2_PA=0u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +#define GPIO1PIN_P2A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PDOR2_PA=(v).bInitVal; \ + bFM_GPIO_DDR2_PA=1u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +/*---- GPIO bit NP2A ----*/ +#define GPIO1PIN_NP2A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_PA)) ) + +#define GPIO1PIN_NP2A_PUT(v) ( bFM_GPIO_PDOR2_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP2A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP2A_INITIN(v) \ + : GPIO1PIN_NP2A_INITOUT(v) ) + +#define GPIO1PIN_NP2A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PCR2_PA=(v).bPullup; \ + bFM_GPIO_DDR2_PA=0u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +#define GPIO1PIN_NP2A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PDOR2_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_PA=1u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +/*---- GPIO bit P32 ----*/ +#define GPIO1PIN_P32_GET ( bFM_GPIO_PDIR3_P2 ) + +#define GPIO1PIN_P32_PUT(v) ( bFM_GPIO_PDOR3_P2=(v) ) + +#define GPIO1PIN_P32_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P32_INITIN(v) \ + : GPIO1PIN_P32_INITOUT(v) ) + +#define GPIO1PIN_P32_INITIN(v) do{ \ + bFM_GPIO_PCR3_P2=(v).bPullup; \ + bFM_GPIO_DDR3_P2=0u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +#define GPIO1PIN_P32_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P2=(v).bInitVal; \ + bFM_GPIO_DDR3_P2=1u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +/*---- GPIO bit NP32 ----*/ +#define GPIO1PIN_NP32_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P2)) ) + +#define GPIO1PIN_NP32_PUT(v) ( bFM_GPIO_PDOR3_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP32_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP32_INITIN(v) \ + : GPIO1PIN_NP32_INITOUT(v) ) + +#define GPIO1PIN_NP32_INITIN(v) do{ \ + bFM_GPIO_PCR3_P2=(v).bPullup; \ + bFM_GPIO_DDR3_P2=0u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +#define GPIO1PIN_NP32_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P2=1u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +/*---- GPIO bit P33 ----*/ +#define GPIO1PIN_P33_GET ( bFM_GPIO_PDIR3_P3 ) + +#define GPIO1PIN_P33_PUT(v) ( bFM_GPIO_PDOR3_P3=(v) ) + +#define GPIO1PIN_P33_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P33_INITIN(v) \ + : GPIO1PIN_P33_INITOUT(v) ) + +#define GPIO1PIN_P33_INITIN(v) do{ \ + bFM_GPIO_PCR3_P3=(v).bPullup; \ + bFM_GPIO_DDR3_P3=0u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +#define GPIO1PIN_P33_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P3=(v).bInitVal; \ + bFM_GPIO_DDR3_P3=1u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +/*---- GPIO bit NP33 ----*/ +#define GPIO1PIN_NP33_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P3)) ) + +#define GPIO1PIN_NP33_PUT(v) ( bFM_GPIO_PDOR3_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP33_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP33_INITIN(v) \ + : GPIO1PIN_NP33_INITOUT(v) ) + +#define GPIO1PIN_NP33_INITIN(v) do{ \ + bFM_GPIO_PCR3_P3=(v).bPullup; \ + bFM_GPIO_DDR3_P3=0u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +#define GPIO1PIN_NP33_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P3=1u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +/*---- GPIO bit P34 ----*/ +#define GPIO1PIN_P34_GET ( bFM_GPIO_PDIR3_P4 ) + +#define GPIO1PIN_P34_PUT(v) ( bFM_GPIO_PDOR3_P4=(v) ) + +#define GPIO1PIN_P34_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P34_INITIN(v) \ + : GPIO1PIN_P34_INITOUT(v) ) + +#define GPIO1PIN_P34_INITIN(v) do{ \ + bFM_GPIO_PCR3_P4=(v).bPullup; \ + bFM_GPIO_DDR3_P4=0u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +#define GPIO1PIN_P34_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P4=(v).bInitVal; \ + bFM_GPIO_DDR3_P4=1u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +/*---- GPIO bit NP34 ----*/ +#define GPIO1PIN_NP34_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P4)) ) + +#define GPIO1PIN_NP34_PUT(v) ( bFM_GPIO_PDOR3_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP34_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP34_INITIN(v) \ + : GPIO1PIN_NP34_INITOUT(v) ) + +#define GPIO1PIN_NP34_INITIN(v) do{ \ + bFM_GPIO_PCR3_P4=(v).bPullup; \ + bFM_GPIO_DDR3_P4=0u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +#define GPIO1PIN_NP34_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P4=1u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +/*---- GPIO bit P35 ----*/ +#define GPIO1PIN_P35_GET ( bFM_GPIO_PDIR3_P5 ) + +#define GPIO1PIN_P35_PUT(v) ( bFM_GPIO_PDOR3_P5=(v) ) + +#define GPIO1PIN_P35_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P35_INITIN(v) \ + : GPIO1PIN_P35_INITOUT(v) ) + +#define GPIO1PIN_P35_INITIN(v) do{ \ + bFM_GPIO_PCR3_P5=(v).bPullup; \ + bFM_GPIO_DDR3_P5=0u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +#define GPIO1PIN_P35_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P5=(v).bInitVal; \ + bFM_GPIO_DDR3_P5=1u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +/*---- GPIO bit NP35 ----*/ +#define GPIO1PIN_NP35_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P5)) ) + +#define GPIO1PIN_NP35_PUT(v) ( bFM_GPIO_PDOR3_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP35_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP35_INITIN(v) \ + : GPIO1PIN_NP35_INITOUT(v) ) + +#define GPIO1PIN_NP35_INITIN(v) do{ \ + bFM_GPIO_PCR3_P5=(v).bPullup; \ + bFM_GPIO_DDR3_P5=0u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +#define GPIO1PIN_NP35_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P5=1u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +/*---- GPIO bit P36 ----*/ +#define GPIO1PIN_P36_GET ( bFM_GPIO_PDIR3_P6 ) + +#define GPIO1PIN_P36_PUT(v) ( bFM_GPIO_PDOR3_P6=(v) ) + +#define GPIO1PIN_P36_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P36_INITIN(v) \ + : GPIO1PIN_P36_INITOUT(v) ) + +#define GPIO1PIN_P36_INITIN(v) do{ \ + bFM_GPIO_PCR3_P6=(v).bPullup; \ + bFM_GPIO_DDR3_P6=0u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +#define GPIO1PIN_P36_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P6=(v).bInitVal; \ + bFM_GPIO_DDR3_P6=1u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +/*---- GPIO bit NP36 ----*/ +#define GPIO1PIN_NP36_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P6)) ) + +#define GPIO1PIN_NP36_PUT(v) ( bFM_GPIO_PDOR3_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP36_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP36_INITIN(v) \ + : GPIO1PIN_NP36_INITOUT(v) ) + +#define GPIO1PIN_NP36_INITIN(v) do{ \ + bFM_GPIO_PCR3_P6=(v).bPullup; \ + bFM_GPIO_DDR3_P6=0u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +#define GPIO1PIN_NP36_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P6=1u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +/*---- GPIO bit P37 ----*/ +#define GPIO1PIN_P37_GET ( bFM_GPIO_PDIR3_P7 ) + +#define GPIO1PIN_P37_PUT(v) ( bFM_GPIO_PDOR3_P7=(v) ) + +#define GPIO1PIN_P37_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P37_INITIN(v) \ + : GPIO1PIN_P37_INITOUT(v) ) + +#define GPIO1PIN_P37_INITIN(v) do{ \ + bFM_GPIO_PCR3_P7=(v).bPullup; \ + bFM_GPIO_DDR3_P7=0u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +#define GPIO1PIN_P37_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P7=(v).bInitVal; \ + bFM_GPIO_DDR3_P7=1u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +/*---- GPIO bit NP37 ----*/ +#define GPIO1PIN_NP37_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P7)) ) + +#define GPIO1PIN_NP37_PUT(v) ( bFM_GPIO_PDOR3_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP37_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP37_INITIN(v) \ + : GPIO1PIN_NP37_INITOUT(v) ) + +#define GPIO1PIN_NP37_INITIN(v) do{ \ + bFM_GPIO_PCR3_P7=(v).bPullup; \ + bFM_GPIO_DDR3_P7=0u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +#define GPIO1PIN_NP37_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P7=1u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +/*---- GPIO bit P38 ----*/ +#define GPIO1PIN_P38_GET ( bFM_GPIO_PDIR3_P8 ) + +#define GPIO1PIN_P38_PUT(v) ( bFM_GPIO_PDOR3_P8=(v) ) + +#define GPIO1PIN_P38_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P38_INITIN(v) \ + : GPIO1PIN_P38_INITOUT(v) ) + +#define GPIO1PIN_P38_INITIN(v) do{ \ + bFM_GPIO_PCR3_P8=(v).bPullup; \ + bFM_GPIO_DDR3_P8=0u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +#define GPIO1PIN_P38_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P8=(v).bInitVal; \ + bFM_GPIO_DDR3_P8=1u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +/*---- GPIO bit NP38 ----*/ +#define GPIO1PIN_NP38_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P8)) ) + +#define GPIO1PIN_NP38_PUT(v) ( bFM_GPIO_PDOR3_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP38_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP38_INITIN(v) \ + : GPIO1PIN_NP38_INITOUT(v) ) + +#define GPIO1PIN_NP38_INITIN(v) do{ \ + bFM_GPIO_PCR3_P8=(v).bPullup; \ + bFM_GPIO_DDR3_P8=0u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +#define GPIO1PIN_NP38_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P8=1u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +/*---- GPIO bit P39 ----*/ +#define GPIO1PIN_P39_GET ( bFM_GPIO_PDIR3_P9 ) + +#define GPIO1PIN_P39_PUT(v) ( bFM_GPIO_PDOR3_P9=(v) ) + +#define GPIO1PIN_P39_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P39_INITIN(v) \ + : GPIO1PIN_P39_INITOUT(v) ) + +#define GPIO1PIN_P39_INITIN(v) do{ \ + bFM_GPIO_PCR3_P9=(v).bPullup; \ + bFM_GPIO_DDR3_P9=0u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +#define GPIO1PIN_P39_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P9=(v).bInitVal; \ + bFM_GPIO_DDR3_P9=1u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +/*---- GPIO bit NP39 ----*/ +#define GPIO1PIN_NP39_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P9)) ) + +#define GPIO1PIN_NP39_PUT(v) ( bFM_GPIO_PDOR3_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP39_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP39_INITIN(v) \ + : GPIO1PIN_NP39_INITOUT(v) ) + +#define GPIO1PIN_NP39_INITIN(v) do{ \ + bFM_GPIO_PCR3_P9=(v).bPullup; \ + bFM_GPIO_DDR3_P9=0u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +#define GPIO1PIN_NP39_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P9=1u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +/*---- GPIO bit P3A ----*/ +#define GPIO1PIN_P3A_GET ( bFM_GPIO_PDIR3_PA ) + +#define GPIO1PIN_P3A_PUT(v) ( bFM_GPIO_PDOR3_PA=(v) ) + +#define GPIO1PIN_P3A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3A_INITIN(v) \ + : GPIO1PIN_P3A_INITOUT(v) ) + +#define GPIO1PIN_P3A_INITIN(v) do{ \ + bFM_GPIO_PCR3_PA=(v).bPullup; \ + bFM_GPIO_DDR3_PA=0u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +#define GPIO1PIN_P3A_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PA=(v).bInitVal; \ + bFM_GPIO_DDR3_PA=1u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +/*---- GPIO bit NP3A ----*/ +#define GPIO1PIN_NP3A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PA)) ) + +#define GPIO1PIN_NP3A_PUT(v) ( bFM_GPIO_PDOR3_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3A_INITIN(v) \ + : GPIO1PIN_NP3A_INITOUT(v) ) + +#define GPIO1PIN_NP3A_INITIN(v) do{ \ + bFM_GPIO_PCR3_PA=(v).bPullup; \ + bFM_GPIO_DDR3_PA=0u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +#define GPIO1PIN_NP3A_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PA=1u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +/*---- GPIO bit P3B ----*/ +#define GPIO1PIN_P3B_GET ( bFM_GPIO_PDIR3_PB ) + +#define GPIO1PIN_P3B_PUT(v) ( bFM_GPIO_PDOR3_PB=(v) ) + +#define GPIO1PIN_P3B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3B_INITIN(v) \ + : GPIO1PIN_P3B_INITOUT(v) ) + +#define GPIO1PIN_P3B_INITIN(v) do{ \ + bFM_GPIO_PCR3_PB=(v).bPullup; \ + bFM_GPIO_DDR3_PB=0u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +#define GPIO1PIN_P3B_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PB=(v).bInitVal; \ + bFM_GPIO_DDR3_PB=1u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +/*---- GPIO bit NP3B ----*/ +#define GPIO1PIN_NP3B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PB)) ) + +#define GPIO1PIN_NP3B_PUT(v) ( bFM_GPIO_PDOR3_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3B_INITIN(v) \ + : GPIO1PIN_NP3B_INITOUT(v) ) + +#define GPIO1PIN_NP3B_INITIN(v) do{ \ + bFM_GPIO_PCR3_PB=(v).bPullup; \ + bFM_GPIO_DDR3_PB=0u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +#define GPIO1PIN_NP3B_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PB=1u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +/*---- GPIO bit P3C ----*/ +#define GPIO1PIN_P3C_GET ( bFM_GPIO_PDIR3_PC ) + +#define GPIO1PIN_P3C_PUT(v) ( bFM_GPIO_PDOR3_PC=(v) ) + +#define GPIO1PIN_P3C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3C_INITIN(v) \ + : GPIO1PIN_P3C_INITOUT(v) ) + +#define GPIO1PIN_P3C_INITIN(v) do{ \ + bFM_GPIO_PCR3_PC=(v).bPullup; \ + bFM_GPIO_DDR3_PC=0u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +#define GPIO1PIN_P3C_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PC=(v).bInitVal; \ + bFM_GPIO_DDR3_PC=1u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +/*---- GPIO bit NP3C ----*/ +#define GPIO1PIN_NP3C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PC)) ) + +#define GPIO1PIN_NP3C_PUT(v) ( bFM_GPIO_PDOR3_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3C_INITIN(v) \ + : GPIO1PIN_NP3C_INITOUT(v) ) + +#define GPIO1PIN_NP3C_INITIN(v) do{ \ + bFM_GPIO_PCR3_PC=(v).bPullup; \ + bFM_GPIO_DDR3_PC=0u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +#define GPIO1PIN_NP3C_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PC=1u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +/*---- GPIO bit P3D ----*/ +#define GPIO1PIN_P3D_GET ( bFM_GPIO_PDIR3_PD ) + +#define GPIO1PIN_P3D_PUT(v) ( bFM_GPIO_PDOR3_PD=(v) ) + +#define GPIO1PIN_P3D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3D_INITIN(v) \ + : GPIO1PIN_P3D_INITOUT(v) ) + +#define GPIO1PIN_P3D_INITIN(v) do{ \ + bFM_GPIO_PCR3_PD=(v).bPullup; \ + bFM_GPIO_DDR3_PD=0u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +#define GPIO1PIN_P3D_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PD=(v).bInitVal; \ + bFM_GPIO_DDR3_PD=1u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +/*---- GPIO bit NP3D ----*/ +#define GPIO1PIN_NP3D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PD)) ) + +#define GPIO1PIN_NP3D_PUT(v) ( bFM_GPIO_PDOR3_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3D_INITIN(v) \ + : GPIO1PIN_NP3D_INITOUT(v) ) + +#define GPIO1PIN_NP3D_INITIN(v) do{ \ + bFM_GPIO_PCR3_PD=(v).bPullup; \ + bFM_GPIO_DDR3_PD=0u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +#define GPIO1PIN_NP3D_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PD=1u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +/*---- GPIO bit P3E ----*/ +#define GPIO1PIN_P3E_GET ( bFM_GPIO_PDIR3_PE ) + +#define GPIO1PIN_P3E_PUT(v) ( bFM_GPIO_PDOR3_PE=(v) ) + +#define GPIO1PIN_P3E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3E_INITIN(v) \ + : GPIO1PIN_P3E_INITOUT(v) ) + +#define GPIO1PIN_P3E_INITIN(v) do{ \ + bFM_GPIO_PCR3_PE=(v).bPullup; \ + bFM_GPIO_DDR3_PE=0u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +#define GPIO1PIN_P3E_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PE=(v).bInitVal; \ + bFM_GPIO_DDR3_PE=1u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +/*---- GPIO bit NP3E ----*/ +#define GPIO1PIN_NP3E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PE)) ) + +#define GPIO1PIN_NP3E_PUT(v) ( bFM_GPIO_PDOR3_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3E_INITIN(v) \ + : GPIO1PIN_NP3E_INITOUT(v) ) + +#define GPIO1PIN_NP3E_INITIN(v) do{ \ + bFM_GPIO_PCR3_PE=(v).bPullup; \ + bFM_GPIO_DDR3_PE=0u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +#define GPIO1PIN_NP3E_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PE=1u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +/*---- GPIO bit P40 ----*/ +#define GPIO1PIN_P40_GET ( bFM_GPIO_PDIR4_P0 ) + +#define GPIO1PIN_P40_PUT(v) ( bFM_GPIO_PDOR4_P0=(v) ) + +#define GPIO1PIN_P40_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P40_INITIN(v) \ + : GPIO1PIN_P40_INITOUT(v) ) + +#define GPIO1PIN_P40_INITIN(v) do{ \ + bFM_GPIO_PCR4_P0=(v).bPullup; \ + bFM_GPIO_DDR4_P0=0u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +#define GPIO1PIN_P40_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P0=(v).bInitVal; \ + bFM_GPIO_DDR4_P0=1u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +/*---- GPIO bit NP40 ----*/ +#define GPIO1PIN_NP40_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P0)) ) + +#define GPIO1PIN_NP40_PUT(v) ( bFM_GPIO_PDOR4_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP40_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP40_INITIN(v) \ + : GPIO1PIN_NP40_INITOUT(v) ) + +#define GPIO1PIN_NP40_INITIN(v) do{ \ + bFM_GPIO_PCR4_P0=(v).bPullup; \ + bFM_GPIO_DDR4_P0=0u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +#define GPIO1PIN_NP40_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P0=1u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +/*---- GPIO bit P41 ----*/ +#define GPIO1PIN_P41_GET ( bFM_GPIO_PDIR4_P1 ) + +#define GPIO1PIN_P41_PUT(v) ( bFM_GPIO_PDOR4_P1=(v) ) + +#define GPIO1PIN_P41_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P41_INITIN(v) \ + : GPIO1PIN_P41_INITOUT(v) ) + +#define GPIO1PIN_P41_INITIN(v) do{ \ + bFM_GPIO_PCR4_P1=(v).bPullup; \ + bFM_GPIO_DDR4_P1=0u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +#define GPIO1PIN_P41_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P1=(v).bInitVal; \ + bFM_GPIO_DDR4_P1=1u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +/*---- GPIO bit NP41 ----*/ +#define GPIO1PIN_NP41_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P1)) ) + +#define GPIO1PIN_NP41_PUT(v) ( bFM_GPIO_PDOR4_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP41_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP41_INITIN(v) \ + : GPIO1PIN_NP41_INITOUT(v) ) + +#define GPIO1PIN_NP41_INITIN(v) do{ \ + bFM_GPIO_PCR4_P1=(v).bPullup; \ + bFM_GPIO_DDR4_P1=0u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +#define GPIO1PIN_NP41_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P1=1u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +/*---- GPIO bit P42 ----*/ +#define GPIO1PIN_P42_GET ( bFM_GPIO_PDIR4_P2 ) + +#define GPIO1PIN_P42_PUT(v) ( bFM_GPIO_PDOR4_P2=(v) ) + +#define GPIO1PIN_P42_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P42_INITIN(v) \ + : GPIO1PIN_P42_INITOUT(v) ) + +#define GPIO1PIN_P42_INITIN(v) do{ \ + bFM_GPIO_PCR4_P2=(v).bPullup; \ + bFM_GPIO_DDR4_P2=0u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +#define GPIO1PIN_P42_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P2=(v).bInitVal; \ + bFM_GPIO_DDR4_P2=1u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +/*---- GPIO bit NP42 ----*/ +#define GPIO1PIN_NP42_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P2)) ) + +#define GPIO1PIN_NP42_PUT(v) ( bFM_GPIO_PDOR4_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP42_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP42_INITIN(v) \ + : GPIO1PIN_NP42_INITOUT(v) ) + +#define GPIO1PIN_NP42_INITIN(v) do{ \ + bFM_GPIO_PCR4_P2=(v).bPullup; \ + bFM_GPIO_DDR4_P2=0u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +#define GPIO1PIN_NP42_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P2=1u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +/*---- GPIO bit P43 ----*/ +#define GPIO1PIN_P43_GET ( bFM_GPIO_PDIR4_P3 ) + +#define GPIO1PIN_P43_PUT(v) ( bFM_GPIO_PDOR4_P3=(v) ) + +#define GPIO1PIN_P43_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P43_INITIN(v) \ + : GPIO1PIN_P43_INITOUT(v) ) + +#define GPIO1PIN_P43_INITIN(v) do{ \ + bFM_GPIO_PCR4_P3=(v).bPullup; \ + bFM_GPIO_DDR4_P3=0u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +#define GPIO1PIN_P43_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P3=(v).bInitVal; \ + bFM_GPIO_DDR4_P3=1u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +/*---- GPIO bit NP43 ----*/ +#define GPIO1PIN_NP43_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P3)) ) + +#define GPIO1PIN_NP43_PUT(v) ( bFM_GPIO_PDOR4_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP43_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP43_INITIN(v) \ + : GPIO1PIN_NP43_INITOUT(v) ) + +#define GPIO1PIN_NP43_INITIN(v) do{ \ + bFM_GPIO_PCR4_P3=(v).bPullup; \ + bFM_GPIO_DDR4_P3=0u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +#define GPIO1PIN_NP43_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P3=1u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +/*---- GPIO bit P44 ----*/ +#define GPIO1PIN_P44_GET ( bFM_GPIO_PDIR4_P4 ) + +#define GPIO1PIN_P44_PUT(v) ( bFM_GPIO_PDOR4_P4=(v) ) + +#define GPIO1PIN_P44_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P44_INITIN(v) \ + : GPIO1PIN_P44_INITOUT(v) ) + +#define GPIO1PIN_P44_INITIN(v) do{ \ + bFM_GPIO_PCR4_P4=(v).bPullup; \ + bFM_GPIO_DDR4_P4=0u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +#define GPIO1PIN_P44_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P4=(v).bInitVal; \ + bFM_GPIO_DDR4_P4=1u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +/*---- GPIO bit NP44 ----*/ +#define GPIO1PIN_NP44_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P4)) ) + +#define GPIO1PIN_NP44_PUT(v) ( bFM_GPIO_PDOR4_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP44_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP44_INITIN(v) \ + : GPIO1PIN_NP44_INITOUT(v) ) + +#define GPIO1PIN_NP44_INITIN(v) do{ \ + bFM_GPIO_PCR4_P4=(v).bPullup; \ + bFM_GPIO_DDR4_P4=0u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +#define GPIO1PIN_NP44_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P4=1u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +/*---- GPIO bit P45 ----*/ +#define GPIO1PIN_P45_GET ( bFM_GPIO_PDIR4_P5 ) + +#define GPIO1PIN_P45_PUT(v) ( bFM_GPIO_PDOR4_P5=(v) ) + +#define GPIO1PIN_P45_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P45_INITIN(v) \ + : GPIO1PIN_P45_INITOUT(v) ) + +#define GPIO1PIN_P45_INITIN(v) do{ \ + bFM_GPIO_PCR4_P5=(v).bPullup; \ + bFM_GPIO_DDR4_P5=0u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +#define GPIO1PIN_P45_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P5=(v).bInitVal; \ + bFM_GPIO_DDR4_P5=1u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +/*---- GPIO bit NP45 ----*/ +#define GPIO1PIN_NP45_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P5)) ) + +#define GPIO1PIN_NP45_PUT(v) ( bFM_GPIO_PDOR4_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP45_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP45_INITIN(v) \ + : GPIO1PIN_NP45_INITOUT(v) ) + +#define GPIO1PIN_NP45_INITIN(v) do{ \ + bFM_GPIO_PCR4_P5=(v).bPullup; \ + bFM_GPIO_DDR4_P5=0u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +#define GPIO1PIN_NP45_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P5=1u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +/*---- GPIO bit P46 ----*/ +#define GPIO1PIN_P46_GET ( bFM_RTC_VBDIR_VDIR3 ) + +#define GPIO1PIN_P46_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P46_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P46_INITIN(v) \ + : GPIO1PIN_P46_INITOUT(v) ) + +#define GPIO1PIN_P46_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR3=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR3=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P46_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR3=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP46 ----*/ +#define GPIO1PIN_NP46_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR3)) ) + +#define GPIO1PIN_NP46_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP46_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP46_INITIN(v) \ + : GPIO1PIN_NP46_INITOUT(v) ) + +#define GPIO1PIN_NP46_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR3=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR3=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP46_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR3=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P47 ----*/ +#define GPIO1PIN_P47_GET ( bFM_RTC_VBDIR_VDIR2 ) + +#define GPIO1PIN_P47_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P47_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P47_INITIN(v) \ + : GPIO1PIN_P47_INITOUT(v) ) + +#define GPIO1PIN_P47_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR2=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR2=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P47_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR2=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP47 ----*/ +#define GPIO1PIN_NP47_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR2)) ) + +#define GPIO1PIN_NP47_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP47_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP47_INITIN(v) \ + : GPIO1PIN_NP47_INITOUT(v) ) + +#define GPIO1PIN_NP47_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR2=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR2=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP47_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR2=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P48 ----*/ +#define GPIO1PIN_P48_GET ( bFM_RTC_VBDIR_VDIR0 ) + +#define GPIO1PIN_P48_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P48_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P48_INITIN(v) \ + : GPIO1PIN_P48_INITOUT(v) ) + +#define GPIO1PIN_P48_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR0=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR0=0u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P48_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR0=1u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP48 ----*/ +#define GPIO1PIN_NP48_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR0)) ) + +#define GPIO1PIN_NP48_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP48_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP48_INITIN(v) \ + : GPIO1PIN_NP48_INITOUT(v) ) + +#define GPIO1PIN_NP48_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR0=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR0=0u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP48_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR0=1u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P49 ----*/ +#define GPIO1PIN_P49_GET ( bFM_RTC_VBDIR_VDIR1 ) + +#define GPIO1PIN_P49_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P49_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P49_INITIN(v) \ + : GPIO1PIN_P49_INITOUT(v) ) + +#define GPIO1PIN_P49_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR1=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR1=0u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P49_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR1=1u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP49 ----*/ +#define GPIO1PIN_NP49_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR1)) ) + +#define GPIO1PIN_NP49_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP49_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP49_INITIN(v) \ + : GPIO1PIN_NP49_INITOUT(v) ) + +#define GPIO1PIN_NP49_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR1=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR1=0u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP49_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR1=1u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P60 ----*/ +#define GPIO1PIN_P60_GET ( bFM_GPIO_PDIR6_P0 ) + +#define GPIO1PIN_P60_PUT(v) ( bFM_GPIO_PDOR6_P0=(v) ) + +#define GPIO1PIN_P60_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P60_INITIN(v) \ + : GPIO1PIN_P60_INITOUT(v) ) + +#define GPIO1PIN_P60_INITIN(v) do{ \ + bFM_GPIO_PCR6_P0=(v).bPullup; \ + bFM_GPIO_DDR6_P0=0u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +#define GPIO1PIN_P60_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P0=(v).bInitVal; \ + bFM_GPIO_DDR6_P0=1u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +/*---- GPIO bit NP60 ----*/ +#define GPIO1PIN_NP60_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P0)) ) + +#define GPIO1PIN_NP60_PUT(v) ( bFM_GPIO_PDOR6_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP60_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP60_INITIN(v) \ + : GPIO1PIN_NP60_INITOUT(v) ) + +#define GPIO1PIN_NP60_INITIN(v) do{ \ + bFM_GPIO_PCR6_P0=(v).bPullup; \ + bFM_GPIO_DDR6_P0=0u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +#define GPIO1PIN_NP60_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P0=1u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +/*---- GPIO bit P61 ----*/ +#define GPIO1PIN_P61_GET ( bFM_GPIO_PDIR6_P1 ) + +#define GPIO1PIN_P61_PUT(v) ( bFM_GPIO_PDOR6_P1=(v) ) + +#define GPIO1PIN_P61_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P61_INITIN(v) \ + : GPIO1PIN_P61_INITOUT(v) ) + +#define GPIO1PIN_P61_INITIN(v) do{ \ + bFM_GPIO_PCR6_P1=(v).bPullup; \ + bFM_GPIO_DDR6_P1=0u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +#define GPIO1PIN_P61_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P1=(v).bInitVal; \ + bFM_GPIO_DDR6_P1=1u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +/*---- GPIO bit NP61 ----*/ +#define GPIO1PIN_NP61_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P1)) ) + +#define GPIO1PIN_NP61_PUT(v) ( bFM_GPIO_PDOR6_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP61_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP61_INITIN(v) \ + : GPIO1PIN_NP61_INITOUT(v) ) + +#define GPIO1PIN_NP61_INITIN(v) do{ \ + bFM_GPIO_PCR6_P1=(v).bPullup; \ + bFM_GPIO_DDR6_P1=0u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +#define GPIO1PIN_NP61_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P1=1u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +/*---- GPIO bit P62 ----*/ +#define GPIO1PIN_P62_GET ( bFM_GPIO_PDIR6_P2 ) + +#define GPIO1PIN_P62_PUT(v) ( bFM_GPIO_PDOR6_P2=(v) ) + +#define GPIO1PIN_P62_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P62_INITIN(v) \ + : GPIO1PIN_P62_INITOUT(v) ) + +#define GPIO1PIN_P62_INITIN(v) do{ \ + bFM_GPIO_PCR6_P2=(v).bPullup; \ + bFM_GPIO_DDR6_P2=0u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +#define GPIO1PIN_P62_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P2=(v).bInitVal; \ + bFM_GPIO_DDR6_P2=1u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +/*---- GPIO bit NP62 ----*/ +#define GPIO1PIN_NP62_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P2)) ) + +#define GPIO1PIN_NP62_PUT(v) ( bFM_GPIO_PDOR6_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP62_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP62_INITIN(v) \ + : GPIO1PIN_NP62_INITOUT(v) ) + +#define GPIO1PIN_NP62_INITIN(v) do{ \ + bFM_GPIO_PCR6_P2=(v).bPullup; \ + bFM_GPIO_DDR6_P2=0u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +#define GPIO1PIN_NP62_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P2=1u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +/*---- GPIO bit P63 ----*/ +#define GPIO1PIN_P63_GET ( bFM_GPIO_PDIR6_P3 ) + +#define GPIO1PIN_P63_PUT(v) ( bFM_GPIO_PDOR6_P3=(v) ) + +#define GPIO1PIN_P63_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P63_INITIN(v) \ + : GPIO1PIN_P63_INITOUT(v) ) + +#define GPIO1PIN_P63_INITIN(v) do{ \ + bFM_GPIO_PCR6_P3=(v).bPullup; \ + bFM_GPIO_DDR6_P3=0u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +#define GPIO1PIN_P63_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P3=(v).bInitVal; \ + bFM_GPIO_DDR6_P3=1u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +/*---- GPIO bit NP63 ----*/ +#define GPIO1PIN_NP63_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P3)) ) + +#define GPIO1PIN_NP63_PUT(v) ( bFM_GPIO_PDOR6_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP63_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP63_INITIN(v) \ + : GPIO1PIN_NP63_INITOUT(v) ) + +#define GPIO1PIN_NP63_INITIN(v) do{ \ + bFM_GPIO_PCR6_P3=(v).bPullup; \ + bFM_GPIO_DDR6_P3=0u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +#define GPIO1PIN_NP63_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P3=1u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +/*---- GPIO bit P6E ----*/ +#define GPIO1PIN_P6E_GET ( bFM_GPIO_PDIR6_PE ) + +#define GPIO1PIN_P6E_PUT(v) ( bFM_GPIO_PDOR6_PE=(v) ) + +#define GPIO1PIN_P6E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P6E_INITIN(v) \ + : GPIO1PIN_P6E_INITOUT(v) ) + +#define GPIO1PIN_P6E_INITIN(v) do{ \ + bFM_GPIO_PCR6_PE=(v).bPullup; \ + bFM_GPIO_DDR6_PE=0u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +#define GPIO1PIN_P6E_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PE=(v).bInitVal; \ + bFM_GPIO_DDR6_PE=1u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +/*---- GPIO bit NP6E ----*/ +#define GPIO1PIN_NP6E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_PE)) ) + +#define GPIO1PIN_NP6E_PUT(v) ( bFM_GPIO_PDOR6_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP6E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP6E_INITIN(v) \ + : GPIO1PIN_NP6E_INITOUT(v) ) + +#define GPIO1PIN_NP6E_INITIN(v) do{ \ + bFM_GPIO_PCR6_PE=(v).bPullup; \ + bFM_GPIO_DDR6_PE=0u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +#define GPIO1PIN_NP6E_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_PE=1u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +/*---- GPIO bit P70 ----*/ +#define GPIO1PIN_P70_GET ( bFM_GPIO_PDIR7_P0 ) + +#define GPIO1PIN_P70_PUT(v) ( bFM_GPIO_PDOR7_P0=(v) ) + +#define GPIO1PIN_P70_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P70_INITIN(v) \ + : GPIO1PIN_P70_INITOUT(v) ) + +#define GPIO1PIN_P70_INITIN(v) do{ \ + bFM_GPIO_PCR7_P0=(v).bPullup; \ + bFM_GPIO_DDR7_P0=0u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +#define GPIO1PIN_P70_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P0=(v).bInitVal; \ + bFM_GPIO_DDR7_P0=1u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +/*---- GPIO bit NP70 ----*/ +#define GPIO1PIN_NP70_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P0)) ) + +#define GPIO1PIN_NP70_PUT(v) ( bFM_GPIO_PDOR7_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP70_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP70_INITIN(v) \ + : GPIO1PIN_NP70_INITOUT(v) ) + +#define GPIO1PIN_NP70_INITIN(v) do{ \ + bFM_GPIO_PCR7_P0=(v).bPullup; \ + bFM_GPIO_DDR7_P0=0u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +#define GPIO1PIN_NP70_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P0=1u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +/*---- GPIO bit P71 ----*/ +#define GPIO1PIN_P71_GET ( bFM_GPIO_PDIR7_P1 ) + +#define GPIO1PIN_P71_PUT(v) ( bFM_GPIO_PDOR7_P1=(v) ) + +#define GPIO1PIN_P71_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P71_INITIN(v) \ + : GPIO1PIN_P71_INITOUT(v) ) + +#define GPIO1PIN_P71_INITIN(v) do{ \ + bFM_GPIO_PCR7_P1=(v).bPullup; \ + bFM_GPIO_DDR7_P1=0u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +#define GPIO1PIN_P71_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P1=(v).bInitVal; \ + bFM_GPIO_DDR7_P1=1u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +/*---- GPIO bit NP71 ----*/ +#define GPIO1PIN_NP71_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P1)) ) + +#define GPIO1PIN_NP71_PUT(v) ( bFM_GPIO_PDOR7_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP71_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP71_INITIN(v) \ + : GPIO1PIN_NP71_INITOUT(v) ) + +#define GPIO1PIN_NP71_INITIN(v) do{ \ + bFM_GPIO_PCR7_P1=(v).bPullup; \ + bFM_GPIO_DDR7_P1=0u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +#define GPIO1PIN_NP71_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P1=1u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +/*---- GPIO bit P72 ----*/ +#define GPIO1PIN_P72_GET ( bFM_GPIO_PDIR7_P2 ) + +#define GPIO1PIN_P72_PUT(v) ( bFM_GPIO_PDOR7_P2=(v) ) + +#define GPIO1PIN_P72_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P72_INITIN(v) \ + : GPIO1PIN_P72_INITOUT(v) ) + +#define GPIO1PIN_P72_INITIN(v) do{ \ + bFM_GPIO_PCR7_P2=(v).bPullup; \ + bFM_GPIO_DDR7_P2=0u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +#define GPIO1PIN_P72_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P2=(v).bInitVal; \ + bFM_GPIO_DDR7_P2=1u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +/*---- GPIO bit NP72 ----*/ +#define GPIO1PIN_NP72_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P2)) ) + +#define GPIO1PIN_NP72_PUT(v) ( bFM_GPIO_PDOR7_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP72_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP72_INITIN(v) \ + : GPIO1PIN_NP72_INITOUT(v) ) + +#define GPIO1PIN_NP72_INITIN(v) do{ \ + bFM_GPIO_PCR7_P2=(v).bPullup; \ + bFM_GPIO_DDR7_P2=0u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +#define GPIO1PIN_NP72_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P2=1u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +/*---- GPIO bit P73 ----*/ +#define GPIO1PIN_P73_GET ( bFM_GPIO_PDIR7_P3 ) + +#define GPIO1PIN_P73_PUT(v) ( bFM_GPIO_PDOR7_P3=(v) ) + +#define GPIO1PIN_P73_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P73_INITIN(v) \ + : GPIO1PIN_P73_INITOUT(v) ) + +#define GPIO1PIN_P73_INITIN(v) do{ \ + bFM_GPIO_PCR7_P3=(v).bPullup; \ + bFM_GPIO_DDR7_P3=0u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +#define GPIO1PIN_P73_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P3=(v).bInitVal; \ + bFM_GPIO_DDR7_P3=1u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +/*---- GPIO bit NP73 ----*/ +#define GPIO1PIN_NP73_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P3)) ) + +#define GPIO1PIN_NP73_PUT(v) ( bFM_GPIO_PDOR7_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP73_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP73_INITIN(v) \ + : GPIO1PIN_NP73_INITOUT(v) ) + +#define GPIO1PIN_NP73_INITIN(v) do{ \ + bFM_GPIO_PCR7_P3=(v).bPullup; \ + bFM_GPIO_DDR7_P3=0u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +#define GPIO1PIN_NP73_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P3=1u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +/*---- GPIO bit P74 ----*/ +#define GPIO1PIN_P74_GET ( bFM_GPIO_PDIR7_P4 ) + +#define GPIO1PIN_P74_PUT(v) ( bFM_GPIO_PDOR7_P4=(v) ) + +#define GPIO1PIN_P74_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P74_INITIN(v) \ + : GPIO1PIN_P74_INITOUT(v) ) + +#define GPIO1PIN_P74_INITIN(v) do{ \ + bFM_GPIO_PCR7_P4=(v).bPullup; \ + bFM_GPIO_DDR7_P4=0u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +#define GPIO1PIN_P74_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P4=(v).bInitVal; \ + bFM_GPIO_DDR7_P4=1u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +/*---- GPIO bit NP74 ----*/ +#define GPIO1PIN_NP74_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P4)) ) + +#define GPIO1PIN_NP74_PUT(v) ( bFM_GPIO_PDOR7_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP74_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP74_INITIN(v) \ + : GPIO1PIN_NP74_INITOUT(v) ) + +#define GPIO1PIN_NP74_INITIN(v) do{ \ + bFM_GPIO_PCR7_P4=(v).bPullup; \ + bFM_GPIO_DDR7_P4=0u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +#define GPIO1PIN_NP74_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P4=1u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +/*---- GPIO bit P75 ----*/ +#define GPIO1PIN_P75_GET ( bFM_GPIO_PDIR7_P5 ) + +#define GPIO1PIN_P75_PUT(v) ( bFM_GPIO_PDOR7_P5=(v) ) + +#define GPIO1PIN_P75_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P75_INITIN(v) \ + : GPIO1PIN_P75_INITOUT(v) ) + +#define GPIO1PIN_P75_INITIN(v) do{ \ + bFM_GPIO_PCR7_P5=(v).bPullup; \ + bFM_GPIO_DDR7_P5=0u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +#define GPIO1PIN_P75_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P5=(v).bInitVal; \ + bFM_GPIO_DDR7_P5=1u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +/*---- GPIO bit NP75 ----*/ +#define GPIO1PIN_NP75_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P5)) ) + +#define GPIO1PIN_NP75_PUT(v) ( bFM_GPIO_PDOR7_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP75_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP75_INITIN(v) \ + : GPIO1PIN_NP75_INITOUT(v) ) + +#define GPIO1PIN_NP75_INITIN(v) do{ \ + bFM_GPIO_PCR7_P5=(v).bPullup; \ + bFM_GPIO_DDR7_P5=0u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +#define GPIO1PIN_NP75_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P5=1u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +/*---- GPIO bit P76 ----*/ +#define GPIO1PIN_P76_GET ( bFM_GPIO_PDIR7_P6 ) + +#define GPIO1PIN_P76_PUT(v) ( bFM_GPIO_PDOR7_P6=(v) ) + +#define GPIO1PIN_P76_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P76_INITIN(v) \ + : GPIO1PIN_P76_INITOUT(v) ) + +#define GPIO1PIN_P76_INITIN(v) do{ \ + bFM_GPIO_PCR7_P6=(v).bPullup; \ + bFM_GPIO_DDR7_P6=0u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +#define GPIO1PIN_P76_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P6=(v).bInitVal; \ + bFM_GPIO_DDR7_P6=1u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +/*---- GPIO bit NP76 ----*/ +#define GPIO1PIN_NP76_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P6)) ) + +#define GPIO1PIN_NP76_PUT(v) ( bFM_GPIO_PDOR7_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP76_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP76_INITIN(v) \ + : GPIO1PIN_NP76_INITOUT(v) ) + +#define GPIO1PIN_NP76_INITIN(v) do{ \ + bFM_GPIO_PCR7_P6=(v).bPullup; \ + bFM_GPIO_DDR7_P6=0u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +#define GPIO1PIN_NP76_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P6=1u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +/*---- GPIO bit P77 ----*/ +#define GPIO1PIN_P77_GET ( bFM_GPIO_PDIR7_P7 ) + +#define GPIO1PIN_P77_PUT(v) ( bFM_GPIO_PDOR7_P7=(v) ) + +#define GPIO1PIN_P77_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P77_INITIN(v) \ + : GPIO1PIN_P77_INITOUT(v) ) + +#define GPIO1PIN_P77_INITIN(v) do{ \ + bFM_GPIO_PCR7_P7=(v).bPullup; \ + bFM_GPIO_DDR7_P7=0u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +#define GPIO1PIN_P77_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P7=(v).bInitVal; \ + bFM_GPIO_DDR7_P7=1u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +/*---- GPIO bit NP77 ----*/ +#define GPIO1PIN_NP77_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P7)) ) + +#define GPIO1PIN_NP77_PUT(v) ( bFM_GPIO_PDOR7_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP77_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP77_INITIN(v) \ + : GPIO1PIN_NP77_INITOUT(v) ) + +#define GPIO1PIN_NP77_INITIN(v) do{ \ + bFM_GPIO_PCR7_P7=(v).bPullup; \ + bFM_GPIO_DDR7_P7=0u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +#define GPIO1PIN_NP77_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P7=1u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +/*---- GPIO bit P78 ----*/ +#define GPIO1PIN_P78_GET ( bFM_GPIO_PDIR7_P8 ) + +#define GPIO1PIN_P78_PUT(v) ( bFM_GPIO_PDOR7_P8=(v) ) + +#define GPIO1PIN_P78_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P78_INITIN(v) \ + : GPIO1PIN_P78_INITOUT(v) ) + +#define GPIO1PIN_P78_INITIN(v) do{ \ + bFM_GPIO_PCR7_P8=(v).bPullup; \ + bFM_GPIO_DDR7_P8=0u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +#define GPIO1PIN_P78_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P8=(v).bInitVal; \ + bFM_GPIO_DDR7_P8=1u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +/*---- GPIO bit NP78 ----*/ +#define GPIO1PIN_NP78_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P8)) ) + +#define GPIO1PIN_NP78_PUT(v) ( bFM_GPIO_PDOR7_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP78_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP78_INITIN(v) \ + : GPIO1PIN_NP78_INITOUT(v) ) + +#define GPIO1PIN_NP78_INITIN(v) do{ \ + bFM_GPIO_PCR7_P8=(v).bPullup; \ + bFM_GPIO_DDR7_P8=0u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +#define GPIO1PIN_NP78_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P8=1u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +/*---- GPIO bit P79 ----*/ +#define GPIO1PIN_P79_GET ( bFM_GPIO_PDIR7_P9 ) + +#define GPIO1PIN_P79_PUT(v) ( bFM_GPIO_PDOR7_P9=(v) ) + +#define GPIO1PIN_P79_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P79_INITIN(v) \ + : GPIO1PIN_P79_INITOUT(v) ) + +#define GPIO1PIN_P79_INITIN(v) do{ \ + bFM_GPIO_PCR7_P9=(v).bPullup; \ + bFM_GPIO_DDR7_P9=0u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +#define GPIO1PIN_P79_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P9=(v).bInitVal; \ + bFM_GPIO_DDR7_P9=1u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +/*---- GPIO bit NP79 ----*/ +#define GPIO1PIN_NP79_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P9)) ) + +#define GPIO1PIN_NP79_PUT(v) ( bFM_GPIO_PDOR7_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP79_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP79_INITIN(v) \ + : GPIO1PIN_NP79_INITOUT(v) ) + +#define GPIO1PIN_NP79_INITIN(v) do{ \ + bFM_GPIO_PCR7_P9=(v).bPullup; \ + bFM_GPIO_DDR7_P9=0u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +#define GPIO1PIN_NP79_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P9=1u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +/*---- GPIO bit P7A ----*/ +#define GPIO1PIN_P7A_GET ( bFM_GPIO_PDIR7_PA ) + +#define GPIO1PIN_P7A_PUT(v) ( bFM_GPIO_PDOR7_PA=(v) ) + +#define GPIO1PIN_P7A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7A_INITIN(v) \ + : GPIO1PIN_P7A_INITOUT(v) ) + +#define GPIO1PIN_P7A_INITIN(v) do{ \ + bFM_GPIO_PCR7_PA=(v).bPullup; \ + bFM_GPIO_DDR7_PA=0u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +#define GPIO1PIN_P7A_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PA=(v).bInitVal; \ + bFM_GPIO_DDR7_PA=1u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +/*---- GPIO bit NP7A ----*/ +#define GPIO1PIN_NP7A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PA)) ) + +#define GPIO1PIN_NP7A_PUT(v) ( bFM_GPIO_PDOR7_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7A_INITIN(v) \ + : GPIO1PIN_NP7A_INITOUT(v) ) + +#define GPIO1PIN_NP7A_INITIN(v) do{ \ + bFM_GPIO_PCR7_PA=(v).bPullup; \ + bFM_GPIO_DDR7_PA=0u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +#define GPIO1PIN_NP7A_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PA=1u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +/*---- GPIO bit P7B ----*/ +#define GPIO1PIN_P7B_GET ( bFM_GPIO_PDIR7_PB ) + +#define GPIO1PIN_P7B_PUT(v) ( bFM_GPIO_PDOR7_PB=(v) ) + +#define GPIO1PIN_P7B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7B_INITIN(v) \ + : GPIO1PIN_P7B_INITOUT(v) ) + +#define GPIO1PIN_P7B_INITIN(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PB=(v).bPullup; \ + bFM_GPIO_DDR7_PB=0u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +#define GPIO1PIN_P7B_INITOUT(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PB=(v).bInitVal; \ + bFM_GPIO_DDR7_PB=1u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +/*---- GPIO bit NP7B ----*/ +#define GPIO1PIN_NP7B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PB)) ) + +#define GPIO1PIN_NP7B_PUT(v) ( bFM_GPIO_PDOR7_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7B_INITIN(v) \ + : GPIO1PIN_NP7B_INITOUT(v) ) + +#define GPIO1PIN_NP7B_INITIN(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PB=(v).bPullup; \ + bFM_GPIO_DDR7_PB=0u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +#define GPIO1PIN_NP7B_INITOUT(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PB=1u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +/*---- GPIO bit P7C ----*/ +#define GPIO1PIN_P7C_GET ( bFM_GPIO_PDIR7_PC ) + +#define GPIO1PIN_P7C_PUT(v) ( bFM_GPIO_PDOR7_PC=(v) ) + +#define GPIO1PIN_P7C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7C_INITIN(v) \ + : GPIO1PIN_P7C_INITOUT(v) ) + +#define GPIO1PIN_P7C_INITIN(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PC=(v).bPullup; \ + bFM_GPIO_DDR7_PC=0u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +#define GPIO1PIN_P7C_INITOUT(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PC=(v).bInitVal; \ + bFM_GPIO_DDR7_PC=1u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +/*---- GPIO bit NP7C ----*/ +#define GPIO1PIN_NP7C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PC)) ) + +#define GPIO1PIN_NP7C_PUT(v) ( bFM_GPIO_PDOR7_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7C_INITIN(v) \ + : GPIO1PIN_NP7C_INITOUT(v) ) + +#define GPIO1PIN_NP7C_INITIN(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PC=(v).bPullup; \ + bFM_GPIO_DDR7_PC=0u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +#define GPIO1PIN_NP7C_INITOUT(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PC=1u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +/*---- GPIO bit P7D ----*/ +#define GPIO1PIN_P7D_GET ( bFM_GPIO_PDIR7_PD ) + +#define GPIO1PIN_P7D_PUT(v) ( bFM_GPIO_PDOR7_PD=(v) ) + +#define GPIO1PIN_P7D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7D_INITIN(v) \ + : GPIO1PIN_P7D_INITOUT(v) ) + +#define GPIO1PIN_P7D_INITIN(v) do{ \ + bFM_GPIO_PCR7_PD=(v).bPullup; \ + bFM_GPIO_DDR7_PD=0u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +#define GPIO1PIN_P7D_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PD=(v).bInitVal; \ + bFM_GPIO_DDR7_PD=1u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +/*---- GPIO bit NP7D ----*/ +#define GPIO1PIN_NP7D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PD)) ) + +#define GPIO1PIN_NP7D_PUT(v) ( bFM_GPIO_PDOR7_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7D_INITIN(v) \ + : GPIO1PIN_NP7D_INITOUT(v) ) + +#define GPIO1PIN_NP7D_INITIN(v) do{ \ + bFM_GPIO_PCR7_PD=(v).bPullup; \ + bFM_GPIO_DDR7_PD=0u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +#define GPIO1PIN_NP7D_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PD=1u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +/*---- GPIO bit P7E ----*/ +#define GPIO1PIN_P7E_GET ( bFM_GPIO_PDIR7_PE ) + +#define GPIO1PIN_P7E_PUT(v) ( bFM_GPIO_PDOR7_PE=(v) ) + +#define GPIO1PIN_P7E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7E_INITIN(v) \ + : GPIO1PIN_P7E_INITOUT(v) ) + +#define GPIO1PIN_P7E_INITIN(v) do{ \ + bFM_GPIO_PCR7_PE=(v).bPullup; \ + bFM_GPIO_DDR7_PE=0u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +#define GPIO1PIN_P7E_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PE=(v).bInitVal; \ + bFM_GPIO_DDR7_PE=1u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +/*---- GPIO bit NP7E ----*/ +#define GPIO1PIN_NP7E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PE)) ) + +#define GPIO1PIN_NP7E_PUT(v) ( bFM_GPIO_PDOR7_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7E_INITIN(v) \ + : GPIO1PIN_NP7E_INITOUT(v) ) + +#define GPIO1PIN_NP7E_INITIN(v) do{ \ + bFM_GPIO_PCR7_PE=(v).bPullup; \ + bFM_GPIO_DDR7_PE=0u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +#define GPIO1PIN_NP7E_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PE=1u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +/*---- GPIO bit P80 ----*/ +#define GPIO1PIN_P80_GET ( bFM_GPIO_PDIR8_P0 ) + +#define GPIO1PIN_P80_PUT(v) ( bFM_GPIO_PDOR8_P0=(v) ) + +#define GPIO1PIN_P80_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P80_INITIN(v) \ + : GPIO1PIN_P80_INITOUT(v) ) + +#define GPIO1PIN_P80_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P0=0u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +#define GPIO1PIN_P80_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P0=(v).bInitVal; \ + bFM_GPIO_DDR8_P0=1u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +/*---- GPIO bit NP80 ----*/ +#define GPIO1PIN_NP80_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P0)) ) + +#define GPIO1PIN_NP80_PUT(v) ( bFM_GPIO_PDOR8_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP80_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP80_INITIN(v) \ + : GPIO1PIN_NP80_INITOUT(v) ) + +#define GPIO1PIN_NP80_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P0=0u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +#define GPIO1PIN_NP80_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P0=1u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +/*---- GPIO bit P81 ----*/ +#define GPIO1PIN_P81_GET ( bFM_GPIO_PDIR8_P1 ) + +#define GPIO1PIN_P81_PUT(v) ( bFM_GPIO_PDOR8_P1=(v) ) + +#define GPIO1PIN_P81_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P81_INITIN(v) \ + : GPIO1PIN_P81_INITOUT(v) ) + +#define GPIO1PIN_P81_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P1=0u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +#define GPIO1PIN_P81_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P1=(v).bInitVal; \ + bFM_GPIO_DDR8_P1=1u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +/*---- GPIO bit NP81 ----*/ +#define GPIO1PIN_NP81_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P1)) ) + +#define GPIO1PIN_NP81_PUT(v) ( bFM_GPIO_PDOR8_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP81_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP81_INITIN(v) \ + : GPIO1PIN_NP81_INITOUT(v) ) + +#define GPIO1PIN_NP81_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P1=0u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +#define GPIO1PIN_NP81_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P1=1u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +/*---- GPIO bit P82 ----*/ +#define GPIO1PIN_P82_GET ( bFM_GPIO_PDIR8_P2 ) + +#define GPIO1PIN_P82_PUT(v) ( bFM_GPIO_PDOR8_P2=(v) ) + +#define GPIO1PIN_P82_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P82_INITIN(v) \ + : GPIO1PIN_P82_INITOUT(v) ) + +#define GPIO1PIN_P82_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P2=0u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +#define GPIO1PIN_P82_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P2=(v).bInitVal; \ + bFM_GPIO_DDR8_P2=1u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +/*---- GPIO bit NP82 ----*/ +#define GPIO1PIN_NP82_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P2)) ) + +#define GPIO1PIN_NP82_PUT(v) ( bFM_GPIO_PDOR8_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP82_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP82_INITIN(v) \ + : GPIO1PIN_NP82_INITOUT(v) ) + +#define GPIO1PIN_NP82_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P2=0u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +#define GPIO1PIN_NP82_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P2=1u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +/*---- GPIO bit P83 ----*/ +#define GPIO1PIN_P83_GET ( bFM_GPIO_PDIR8_P3 ) + +#define GPIO1PIN_P83_PUT(v) ( bFM_GPIO_PDOR8_P3=(v) ) + +#define GPIO1PIN_P83_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P83_INITIN(v) \ + : GPIO1PIN_P83_INITOUT(v) ) + +#define GPIO1PIN_P83_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P3=0u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +#define GPIO1PIN_P83_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P3=(v).bInitVal; \ + bFM_GPIO_DDR8_P3=1u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +/*---- GPIO bit NP83 ----*/ +#define GPIO1PIN_NP83_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P3)) ) + +#define GPIO1PIN_NP83_PUT(v) ( bFM_GPIO_PDOR8_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP83_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP83_INITIN(v) \ + : GPIO1PIN_NP83_INITOUT(v) ) + +#define GPIO1PIN_NP83_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P3=0u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +#define GPIO1PIN_NP83_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P3=1u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +/*---- GPIO bit PA0 ----*/ +#define GPIO1PIN_PA0_GET ( bFM_GPIO_PDIRA_P0 ) + +#define GPIO1PIN_PA0_PUT(v) ( bFM_GPIO_PDORA_P0=(v) ) + +#define GPIO1PIN_PA0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA0_INITIN(v) \ + : GPIO1PIN_PA0_INITOUT(v) ) + +#define GPIO1PIN_PA0_INITIN(v) do{ \ + bFM_GPIO_PCRA_P0=(v).bPullup; \ + bFM_GPIO_DDRA_P0=0u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +#define GPIO1PIN_PA0_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P0=(v).bInitVal; \ + bFM_GPIO_DDRA_P0=1u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +/*---- GPIO bit NPA0 ----*/ +#define GPIO1PIN_NPA0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P0)) ) + +#define GPIO1PIN_NPA0_PUT(v) ( bFM_GPIO_PDORA_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA0_INITIN(v) \ + : GPIO1PIN_NPA0_INITOUT(v) ) + +#define GPIO1PIN_NPA0_INITIN(v) do{ \ + bFM_GPIO_PCRA_P0=(v).bPullup; \ + bFM_GPIO_DDRA_P0=0u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +#define GPIO1PIN_NPA0_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P0=1u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +/*---- GPIO bit PA1 ----*/ +#define GPIO1PIN_PA1_GET ( bFM_GPIO_PDIRA_P1 ) + +#define GPIO1PIN_PA1_PUT(v) ( bFM_GPIO_PDORA_P1=(v) ) + +#define GPIO1PIN_PA1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA1_INITIN(v) \ + : GPIO1PIN_PA1_INITOUT(v) ) + +#define GPIO1PIN_PA1_INITIN(v) do{ \ + bFM_GPIO_PCRA_P1=(v).bPullup; \ + bFM_GPIO_DDRA_P1=0u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +#define GPIO1PIN_PA1_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P1=(v).bInitVal; \ + bFM_GPIO_DDRA_P1=1u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +/*---- GPIO bit NPA1 ----*/ +#define GPIO1PIN_NPA1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P1)) ) + +#define GPIO1PIN_NPA1_PUT(v) ( bFM_GPIO_PDORA_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA1_INITIN(v) \ + : GPIO1PIN_NPA1_INITOUT(v) ) + +#define GPIO1PIN_NPA1_INITIN(v) do{ \ + bFM_GPIO_PCRA_P1=(v).bPullup; \ + bFM_GPIO_DDRA_P1=0u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +#define GPIO1PIN_NPA1_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P1=1u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +/*---- GPIO bit PA2 ----*/ +#define GPIO1PIN_PA2_GET ( bFM_GPIO_PDIRA_P2 ) + +#define GPIO1PIN_PA2_PUT(v) ( bFM_GPIO_PDORA_P2=(v) ) + +#define GPIO1PIN_PA2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA2_INITIN(v) \ + : GPIO1PIN_PA2_INITOUT(v) ) + +#define GPIO1PIN_PA2_INITIN(v) do{ \ + bFM_GPIO_PCRA_P2=(v).bPullup; \ + bFM_GPIO_DDRA_P2=0u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +#define GPIO1PIN_PA2_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P2=(v).bInitVal; \ + bFM_GPIO_DDRA_P2=1u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +/*---- GPIO bit NPA2 ----*/ +#define GPIO1PIN_NPA2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P2)) ) + +#define GPIO1PIN_NPA2_PUT(v) ( bFM_GPIO_PDORA_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA2_INITIN(v) \ + : GPIO1PIN_NPA2_INITOUT(v) ) + +#define GPIO1PIN_NPA2_INITIN(v) do{ \ + bFM_GPIO_PCRA_P2=(v).bPullup; \ + bFM_GPIO_DDRA_P2=0u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +#define GPIO1PIN_NPA2_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P2=1u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +/*---- GPIO bit PA3 ----*/ +#define GPIO1PIN_PA3_GET ( bFM_GPIO_PDIRA_P3 ) + +#define GPIO1PIN_PA3_PUT(v) ( bFM_GPIO_PDORA_P3=(v) ) + +#define GPIO1PIN_PA3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA3_INITIN(v) \ + : GPIO1PIN_PA3_INITOUT(v) ) + +#define GPIO1PIN_PA3_INITIN(v) do{ \ + bFM_GPIO_PCRA_P3=(v).bPullup; \ + bFM_GPIO_DDRA_P3=0u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +#define GPIO1PIN_PA3_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P3=(v).bInitVal; \ + bFM_GPIO_DDRA_P3=1u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +/*---- GPIO bit NPA3 ----*/ +#define GPIO1PIN_NPA3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P3)) ) + +#define GPIO1PIN_NPA3_PUT(v) ( bFM_GPIO_PDORA_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA3_INITIN(v) \ + : GPIO1PIN_NPA3_INITOUT(v) ) + +#define GPIO1PIN_NPA3_INITIN(v) do{ \ + bFM_GPIO_PCRA_P3=(v).bPullup; \ + bFM_GPIO_DDRA_P3=0u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +#define GPIO1PIN_NPA3_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P3=1u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +/*---- GPIO bit PA4 ----*/ +#define GPIO1PIN_PA4_GET ( bFM_GPIO_PDIRA_P4 ) + +#define GPIO1PIN_PA4_PUT(v) ( bFM_GPIO_PDORA_P4=(v) ) + +#define GPIO1PIN_PA4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA4_INITIN(v) \ + : GPIO1PIN_PA4_INITOUT(v) ) + +#define GPIO1PIN_PA4_INITIN(v) do{ \ + bFM_GPIO_PCRA_P4=(v).bPullup; \ + bFM_GPIO_DDRA_P4=0u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +#define GPIO1PIN_PA4_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P4=(v).bInitVal; \ + bFM_GPIO_DDRA_P4=1u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +/*---- GPIO bit NPA4 ----*/ +#define GPIO1PIN_NPA4_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P4)) ) + +#define GPIO1PIN_NPA4_PUT(v) ( bFM_GPIO_PDORA_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA4_INITIN(v) \ + : GPIO1PIN_NPA4_INITOUT(v) ) + +#define GPIO1PIN_NPA4_INITIN(v) do{ \ + bFM_GPIO_PCRA_P4=(v).bPullup; \ + bFM_GPIO_DDRA_P4=0u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +#define GPIO1PIN_NPA4_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P4=1u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +/*---- GPIO bit PA5 ----*/ +#define GPIO1PIN_PA5_GET ( bFM_GPIO_PDIRA_P5 ) + +#define GPIO1PIN_PA5_PUT(v) ( bFM_GPIO_PDORA_P5=(v) ) + +#define GPIO1PIN_PA5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA5_INITIN(v) \ + : GPIO1PIN_PA5_INITOUT(v) ) + +#define GPIO1PIN_PA5_INITIN(v) do{ \ + bFM_GPIO_PCRA_P5=(v).bPullup; \ + bFM_GPIO_DDRA_P5=0u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +#define GPIO1PIN_PA5_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P5=(v).bInitVal; \ + bFM_GPIO_DDRA_P5=1u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +/*---- GPIO bit NPA5 ----*/ +#define GPIO1PIN_NPA5_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P5)) ) + +#define GPIO1PIN_NPA5_PUT(v) ( bFM_GPIO_PDORA_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA5_INITIN(v) \ + : GPIO1PIN_NPA5_INITOUT(v) ) + +#define GPIO1PIN_NPA5_INITIN(v) do{ \ + bFM_GPIO_PCRA_P5=(v).bPullup; \ + bFM_GPIO_DDRA_P5=0u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +#define GPIO1PIN_NPA5_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P5=1u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +/*---- GPIO bit PA6 ----*/ +#define GPIO1PIN_PA6_GET ( bFM_GPIO_PDIRA_P6 ) + +#define GPIO1PIN_PA6_PUT(v) ( bFM_GPIO_PDORA_P6=(v) ) + +#define GPIO1PIN_PA6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA6_INITIN(v) \ + : GPIO1PIN_PA6_INITOUT(v) ) + +#define GPIO1PIN_PA6_INITIN(v) do{ \ + bFM_GPIO_PCRA_P6=(v).bPullup; \ + bFM_GPIO_DDRA_P6=0u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +#define GPIO1PIN_PA6_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P6=(v).bInitVal; \ + bFM_GPIO_DDRA_P6=1u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +/*---- GPIO bit NPA6 ----*/ +#define GPIO1PIN_NPA6_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P6)) ) + +#define GPIO1PIN_NPA6_PUT(v) ( bFM_GPIO_PDORA_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA6_INITIN(v) \ + : GPIO1PIN_NPA6_INITOUT(v) ) + +#define GPIO1PIN_NPA6_INITIN(v) do{ \ + bFM_GPIO_PCRA_P6=(v).bPullup; \ + bFM_GPIO_DDRA_P6=0u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +#define GPIO1PIN_NPA6_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P6=1u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +/*---- GPIO bit PA7 ----*/ +#define GPIO1PIN_PA7_GET ( bFM_GPIO_PDIRA_P7 ) + +#define GPIO1PIN_PA7_PUT(v) ( bFM_GPIO_PDORA_P7=(v) ) + +#define GPIO1PIN_PA7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA7_INITIN(v) \ + : GPIO1PIN_PA7_INITOUT(v) ) + +#define GPIO1PIN_PA7_INITIN(v) do{ \ + bFM_GPIO_PCRA_P7=(v).bPullup; \ + bFM_GPIO_DDRA_P7=0u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +#define GPIO1PIN_PA7_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P7=(v).bInitVal; \ + bFM_GPIO_DDRA_P7=1u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +/*---- GPIO bit NPA7 ----*/ +#define GPIO1PIN_NPA7_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P7)) ) + +#define GPIO1PIN_NPA7_PUT(v) ( bFM_GPIO_PDORA_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA7_INITIN(v) \ + : GPIO1PIN_NPA7_INITOUT(v) ) + +#define GPIO1PIN_NPA7_INITIN(v) do{ \ + bFM_GPIO_PCRA_P7=(v).bPullup; \ + bFM_GPIO_DDRA_P7=0u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +#define GPIO1PIN_NPA7_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P7=1u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +/*---- GPIO bit PA8 ----*/ +#define GPIO1PIN_PA8_GET ( bFM_GPIO_PDIRA_P8 ) + +#define GPIO1PIN_PA8_PUT(v) ( bFM_GPIO_PDORA_P8=(v) ) + +#define GPIO1PIN_PA8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA8_INITIN(v) \ + : GPIO1PIN_PA8_INITOUT(v) ) + +#define GPIO1PIN_PA8_INITIN(v) do{ \ + bFM_GPIO_PCRA_P8=(v).bPullup; \ + bFM_GPIO_DDRA_P8=0u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +#define GPIO1PIN_PA8_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P8=(v).bInitVal; \ + bFM_GPIO_DDRA_P8=1u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +/*---- GPIO bit NPA8 ----*/ +#define GPIO1PIN_NPA8_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P8)) ) + +#define GPIO1PIN_NPA8_PUT(v) ( bFM_GPIO_PDORA_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA8_INITIN(v) \ + : GPIO1PIN_NPA8_INITOUT(v) ) + +#define GPIO1PIN_NPA8_INITIN(v) do{ \ + bFM_GPIO_PCRA_P8=(v).bPullup; \ + bFM_GPIO_DDRA_P8=0u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +#define GPIO1PIN_NPA8_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P8=1u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +/*---- GPIO bit PA9 ----*/ +#define GPIO1PIN_PA9_GET ( bFM_GPIO_PDIRA_P9 ) + +#define GPIO1PIN_PA9_PUT(v) ( bFM_GPIO_PDORA_P9=(v) ) + +#define GPIO1PIN_PA9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA9_INITIN(v) \ + : GPIO1PIN_PA9_INITOUT(v) ) + +#define GPIO1PIN_PA9_INITIN(v) do{ \ + bFM_GPIO_PCRA_P9=(v).bPullup; \ + bFM_GPIO_DDRA_P9=0u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +#define GPIO1PIN_PA9_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P9=(v).bInitVal; \ + bFM_GPIO_DDRA_P9=1u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +/*---- GPIO bit NPA9 ----*/ +#define GPIO1PIN_NPA9_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P9)) ) + +#define GPIO1PIN_NPA9_PUT(v) ( bFM_GPIO_PDORA_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA9_INITIN(v) \ + : GPIO1PIN_NPA9_INITOUT(v) ) + +#define GPIO1PIN_NPA9_INITIN(v) do{ \ + bFM_GPIO_PCRA_P9=(v).bPullup; \ + bFM_GPIO_DDRA_P9=0u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +#define GPIO1PIN_NPA9_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P9=1u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +/*---- GPIO bit PAA ----*/ +#define GPIO1PIN_PAA_GET ( bFM_GPIO_PDIRA_PA ) + +#define GPIO1PIN_PAA_PUT(v) ( bFM_GPIO_PDORA_PA=(v) ) + +#define GPIO1PIN_PAA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAA_INITIN(v) \ + : GPIO1PIN_PAA_INITOUT(v) ) + +#define GPIO1PIN_PAA_INITIN(v) do{ \ + bFM_GPIO_PCRA_PA=(v).bPullup; \ + bFM_GPIO_DDRA_PA=0u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +#define GPIO1PIN_PAA_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PA=(v).bInitVal; \ + bFM_GPIO_DDRA_PA=1u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +/*---- GPIO bit NPAA ----*/ +#define GPIO1PIN_NPAA_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PA)) ) + +#define GPIO1PIN_NPAA_PUT(v) ( bFM_GPIO_PDORA_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAA_INITIN(v) \ + : GPIO1PIN_NPAA_INITOUT(v) ) + +#define GPIO1PIN_NPAA_INITIN(v) do{ \ + bFM_GPIO_PCRA_PA=(v).bPullup; \ + bFM_GPIO_DDRA_PA=0u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +#define GPIO1PIN_NPAA_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PA=1u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +/*---- GPIO bit PAB ----*/ +#define GPIO1PIN_PAB_GET ( bFM_GPIO_PDIRA_PB ) + +#define GPIO1PIN_PAB_PUT(v) ( bFM_GPIO_PDORA_PB=(v) ) + +#define GPIO1PIN_PAB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAB_INITIN(v) \ + : GPIO1PIN_PAB_INITOUT(v) ) + +#define GPIO1PIN_PAB_INITIN(v) do{ \ + bFM_GPIO_PCRA_PB=(v).bPullup; \ + bFM_GPIO_DDRA_PB=0u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +#define GPIO1PIN_PAB_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PB=(v).bInitVal; \ + bFM_GPIO_DDRA_PB=1u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +/*---- GPIO bit NPAB ----*/ +#define GPIO1PIN_NPAB_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PB)) ) + +#define GPIO1PIN_NPAB_PUT(v) ( bFM_GPIO_PDORA_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAB_INITIN(v) \ + : GPIO1PIN_NPAB_INITOUT(v) ) + +#define GPIO1PIN_NPAB_INITIN(v) do{ \ + bFM_GPIO_PCRA_PB=(v).bPullup; \ + bFM_GPIO_DDRA_PB=0u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +#define GPIO1PIN_NPAB_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PB=1u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +/*---- GPIO bit PAC ----*/ +#define GPIO1PIN_PAC_GET ( bFM_GPIO_PDIRA_PC ) + +#define GPIO1PIN_PAC_PUT(v) ( bFM_GPIO_PDORA_PC=(v) ) + +#define GPIO1PIN_PAC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAC_INITIN(v) \ + : GPIO1PIN_PAC_INITOUT(v) ) + +#define GPIO1PIN_PAC_INITIN(v) do{ \ + bFM_GPIO_PCRA_PC=(v).bPullup; \ + bFM_GPIO_DDRA_PC=0u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +#define GPIO1PIN_PAC_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PC=(v).bInitVal; \ + bFM_GPIO_DDRA_PC=1u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +/*---- GPIO bit NPAC ----*/ +#define GPIO1PIN_NPAC_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PC)) ) + +#define GPIO1PIN_NPAC_PUT(v) ( bFM_GPIO_PDORA_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAC_INITIN(v) \ + : GPIO1PIN_NPAC_INITOUT(v) ) + +#define GPIO1PIN_NPAC_INITIN(v) do{ \ + bFM_GPIO_PCRA_PC=(v).bPullup; \ + bFM_GPIO_DDRA_PC=0u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +#define GPIO1PIN_NPAC_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PC=1u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +/*---- GPIO bit PAD ----*/ +#define GPIO1PIN_PAD_GET ( bFM_GPIO_PDIRA_PD ) + +#define GPIO1PIN_PAD_PUT(v) ( bFM_GPIO_PDORA_PD=(v) ) + +#define GPIO1PIN_PAD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAD_INITIN(v) \ + : GPIO1PIN_PAD_INITOUT(v) ) + +#define GPIO1PIN_PAD_INITIN(v) do{ \ + bFM_GPIO_PCRA_PD=(v).bPullup; \ + bFM_GPIO_DDRA_PD=0u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +#define GPIO1PIN_PAD_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PD=(v).bInitVal; \ + bFM_GPIO_DDRA_PD=1u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +/*---- GPIO bit NPAD ----*/ +#define GPIO1PIN_NPAD_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PD)) ) + +#define GPIO1PIN_NPAD_PUT(v) ( bFM_GPIO_PDORA_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAD_INITIN(v) \ + : GPIO1PIN_NPAD_INITOUT(v) ) + +#define GPIO1PIN_NPAD_INITIN(v) do{ \ + bFM_GPIO_PCRA_PD=(v).bPullup; \ + bFM_GPIO_DDRA_PD=0u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +#define GPIO1PIN_NPAD_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PD=1u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +/*---- GPIO bit PAE ----*/ +#define GPIO1PIN_PAE_GET ( bFM_GPIO_PDIRA_PE ) + +#define GPIO1PIN_PAE_PUT(v) ( bFM_GPIO_PDORA_PE=(v) ) + +#define GPIO1PIN_PAE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAE_INITIN(v) \ + : GPIO1PIN_PAE_INITOUT(v) ) + +#define GPIO1PIN_PAE_INITIN(v) do{ \ + bFM_GPIO_PCRA_PE=(v).bPullup; \ + bFM_GPIO_DDRA_PE=0u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +#define GPIO1PIN_PAE_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PE=(v).bInitVal; \ + bFM_GPIO_DDRA_PE=1u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +/*---- GPIO bit NPAE ----*/ +#define GPIO1PIN_NPAE_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PE)) ) + +#define GPIO1PIN_NPAE_PUT(v) ( bFM_GPIO_PDORA_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAE_INITIN(v) \ + : GPIO1PIN_NPAE_INITOUT(v) ) + +#define GPIO1PIN_NPAE_INITIN(v) do{ \ + bFM_GPIO_PCRA_PE=(v).bPullup; \ + bFM_GPIO_DDRA_PE=0u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +#define GPIO1PIN_NPAE_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PE=1u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +/*---- GPIO bit PAF ----*/ +#define GPIO1PIN_PAF_GET ( bFM_GPIO_PDIRA_PF ) + +#define GPIO1PIN_PAF_PUT(v) ( bFM_GPIO_PDORA_PF=(v) ) + +#define GPIO1PIN_PAF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAF_INITIN(v) \ + : GPIO1PIN_PAF_INITOUT(v) ) + +#define GPIO1PIN_PAF_INITIN(v) do{ \ + bFM_GPIO_PCRA_PF=(v).bPullup; \ + bFM_GPIO_DDRA_PF=0u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +#define GPIO1PIN_PAF_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PF=(v).bInitVal; \ + bFM_GPIO_DDRA_PF=1u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +/*---- GPIO bit NPAF ----*/ +#define GPIO1PIN_NPAF_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PF)) ) + +#define GPIO1PIN_NPAF_PUT(v) ( bFM_GPIO_PDORA_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAF_INITIN(v) \ + : GPIO1PIN_NPAF_INITOUT(v) ) + +#define GPIO1PIN_NPAF_INITIN(v) do{ \ + bFM_GPIO_PCRA_PF=(v).bPullup; \ + bFM_GPIO_DDRA_PF=0u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +#define GPIO1PIN_NPAF_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PF=1u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +/*---- GPIO bit PC0 ----*/ +#define GPIO1PIN_PC0_GET ( bFM_GPIO_PDIRC_P0 ) + +#define GPIO1PIN_PC0_PUT(v) ( bFM_GPIO_PDORC_P0=(v) ) + +#define GPIO1PIN_PC0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC0_INITIN(v) \ + : GPIO1PIN_PC0_INITOUT(v) ) + +#define GPIO1PIN_PC0_INITIN(v) do{ \ + bFM_GPIO_PCRC_P0=(v).bPullup; \ + bFM_GPIO_DDRC_P0=0u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +#define GPIO1PIN_PC0_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P0=(v).bInitVal; \ + bFM_GPIO_DDRC_P0=1u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +/*---- GPIO bit NPC0 ----*/ +#define GPIO1PIN_NPC0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P0)) ) + +#define GPIO1PIN_NPC0_PUT(v) ( bFM_GPIO_PDORC_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC0_INITIN(v) \ + : GPIO1PIN_NPC0_INITOUT(v) ) + +#define GPIO1PIN_NPC0_INITIN(v) do{ \ + bFM_GPIO_PCRC_P0=(v).bPullup; \ + bFM_GPIO_DDRC_P0=0u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +#define GPIO1PIN_NPC0_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P0=1u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +/*---- GPIO bit PC1 ----*/ +#define GPIO1PIN_PC1_GET ( bFM_GPIO_PDIRC_P1 ) + +#define GPIO1PIN_PC1_PUT(v) ( bFM_GPIO_PDORC_P1=(v) ) + +#define GPIO1PIN_PC1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC1_INITIN(v) \ + : GPIO1PIN_PC1_INITOUT(v) ) + +#define GPIO1PIN_PC1_INITIN(v) do{ \ + bFM_GPIO_PCRC_P1=(v).bPullup; \ + bFM_GPIO_DDRC_P1=0u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +#define GPIO1PIN_PC1_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P1=(v).bInitVal; \ + bFM_GPIO_DDRC_P1=1u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +/*---- GPIO bit NPC1 ----*/ +#define GPIO1PIN_NPC1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P1)) ) + +#define GPIO1PIN_NPC1_PUT(v) ( bFM_GPIO_PDORC_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC1_INITIN(v) \ + : GPIO1PIN_NPC1_INITOUT(v) ) + +#define GPIO1PIN_NPC1_INITIN(v) do{ \ + bFM_GPIO_PCRC_P1=(v).bPullup; \ + bFM_GPIO_DDRC_P1=0u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +#define GPIO1PIN_NPC1_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P1=1u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +/*---- GPIO bit PC2 ----*/ +#define GPIO1PIN_PC2_GET ( bFM_GPIO_PDIRC_P2 ) + +#define GPIO1PIN_PC2_PUT(v) ( bFM_GPIO_PDORC_P2=(v) ) + +#define GPIO1PIN_PC2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC2_INITIN(v) \ + : GPIO1PIN_PC2_INITOUT(v) ) + +#define GPIO1PIN_PC2_INITIN(v) do{ \ + bFM_GPIO_PCRC_P2=(v).bPullup; \ + bFM_GPIO_DDRC_P2=0u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +#define GPIO1PIN_PC2_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P2=(v).bInitVal; \ + bFM_GPIO_DDRC_P2=1u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +/*---- GPIO bit NPC2 ----*/ +#define GPIO1PIN_NPC2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P2)) ) + +#define GPIO1PIN_NPC2_PUT(v) ( bFM_GPIO_PDORC_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC2_INITIN(v) \ + : GPIO1PIN_NPC2_INITOUT(v) ) + +#define GPIO1PIN_NPC2_INITIN(v) do{ \ + bFM_GPIO_PCRC_P2=(v).bPullup; \ + bFM_GPIO_DDRC_P2=0u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +#define GPIO1PIN_NPC2_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P2=1u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +/*---- GPIO bit PC3 ----*/ +#define GPIO1PIN_PC3_GET ( bFM_GPIO_PDIRC_P3 ) + +#define GPIO1PIN_PC3_PUT(v) ( bFM_GPIO_PDORC_P3=(v) ) + +#define GPIO1PIN_PC3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC3_INITIN(v) \ + : GPIO1PIN_PC3_INITOUT(v) ) + +#define GPIO1PIN_PC3_INITIN(v) do{ \ + bFM_GPIO_PCRC_P3=(v).bPullup; \ + bFM_GPIO_DDRC_P3=0u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +#define GPIO1PIN_PC3_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P3=(v).bInitVal; \ + bFM_GPIO_DDRC_P3=1u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +/*---- GPIO bit NPC3 ----*/ +#define GPIO1PIN_NPC3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P3)) ) + +#define GPIO1PIN_NPC3_PUT(v) ( bFM_GPIO_PDORC_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC3_INITIN(v) \ + : GPIO1PIN_NPC3_INITOUT(v) ) + +#define GPIO1PIN_NPC3_INITIN(v) do{ \ + bFM_GPIO_PCRC_P3=(v).bPullup; \ + bFM_GPIO_DDRC_P3=0u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +#define GPIO1PIN_NPC3_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P3=1u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +/*---- GPIO bit PC4 ----*/ +#define GPIO1PIN_PC4_GET ( bFM_GPIO_PDIRC_P4 ) + +#define GPIO1PIN_PC4_PUT(v) ( bFM_GPIO_PDORC_P4=(v) ) + +#define GPIO1PIN_PC4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC4_INITIN(v) \ + : GPIO1PIN_PC4_INITOUT(v) ) + +#define GPIO1PIN_PC4_INITIN(v) do{ \ + bFM_GPIO_PCRC_P4=(v).bPullup; \ + bFM_GPIO_DDRC_P4=0u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +#define GPIO1PIN_PC4_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P4=(v).bInitVal; \ + bFM_GPIO_DDRC_P4=1u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +/*---- GPIO bit NPC4 ----*/ +#define GPIO1PIN_NPC4_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P4)) ) + +#define GPIO1PIN_NPC4_PUT(v) ( bFM_GPIO_PDORC_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC4_INITIN(v) \ + : GPIO1PIN_NPC4_INITOUT(v) ) + +#define GPIO1PIN_NPC4_INITIN(v) do{ \ + bFM_GPIO_PCRC_P4=(v).bPullup; \ + bFM_GPIO_DDRC_P4=0u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +#define GPIO1PIN_NPC4_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P4=1u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +/*---- GPIO bit PC5 ----*/ +#define GPIO1PIN_PC5_GET ( bFM_GPIO_PDIRC_P5 ) + +#define GPIO1PIN_PC5_PUT(v) ( bFM_GPIO_PDORC_P5=(v) ) + +#define GPIO1PIN_PC5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC5_INITIN(v) \ + : GPIO1PIN_PC5_INITOUT(v) ) + +#define GPIO1PIN_PC5_INITIN(v) do{ \ + bFM_GPIO_PCRC_P5=(v).bPullup; \ + bFM_GPIO_DDRC_P5=0u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +#define GPIO1PIN_PC5_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P5=(v).bInitVal; \ + bFM_GPIO_DDRC_P5=1u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +/*---- GPIO bit NPC5 ----*/ +#define GPIO1PIN_NPC5_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P5)) ) + +#define GPIO1PIN_NPC5_PUT(v) ( bFM_GPIO_PDORC_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC5_INITIN(v) \ + : GPIO1PIN_NPC5_INITOUT(v) ) + +#define GPIO1PIN_NPC5_INITIN(v) do{ \ + bFM_GPIO_PCRC_P5=(v).bPullup; \ + bFM_GPIO_DDRC_P5=0u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +#define GPIO1PIN_NPC5_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P5=1u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +/*---- GPIO bit PC6 ----*/ +#define GPIO1PIN_PC6_GET ( bFM_GPIO_PDIRC_P6 ) + +#define GPIO1PIN_PC6_PUT(v) ( bFM_GPIO_PDORC_P6=(v) ) + +#define GPIO1PIN_PC6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC6_INITIN(v) \ + : GPIO1PIN_PC6_INITOUT(v) ) + +#define GPIO1PIN_PC6_INITIN(v) do{ \ + bFM_GPIO_PCRC_P6=(v).bPullup; \ + bFM_GPIO_DDRC_P6=0u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +#define GPIO1PIN_PC6_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P6=(v).bInitVal; \ + bFM_GPIO_DDRC_P6=1u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +/*---- GPIO bit NPC6 ----*/ +#define GPIO1PIN_NPC6_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P6)) ) + +#define GPIO1PIN_NPC6_PUT(v) ( bFM_GPIO_PDORC_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC6_INITIN(v) \ + : GPIO1PIN_NPC6_INITOUT(v) ) + +#define GPIO1PIN_NPC6_INITIN(v) do{ \ + bFM_GPIO_PCRC_P6=(v).bPullup; \ + bFM_GPIO_DDRC_P6=0u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +#define GPIO1PIN_NPC6_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P6=1u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +/*---- GPIO bit PC7 ----*/ +#define GPIO1PIN_PC7_GET ( bFM_GPIO_PDIRC_P7 ) + +#define GPIO1PIN_PC7_PUT(v) ( bFM_GPIO_PDORC_P7=(v) ) + +#define GPIO1PIN_PC7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC7_INITIN(v) \ + : GPIO1PIN_PC7_INITOUT(v) ) + +#define GPIO1PIN_PC7_INITIN(v) do{ \ + bFM_GPIO_PCRC_P7=(v).bPullup; \ + bFM_GPIO_DDRC_P7=0u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +#define GPIO1PIN_PC7_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P7=(v).bInitVal; \ + bFM_GPIO_DDRC_P7=1u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +/*---- GPIO bit NPC7 ----*/ +#define GPIO1PIN_NPC7_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P7)) ) + +#define GPIO1PIN_NPC7_PUT(v) ( bFM_GPIO_PDORC_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC7_INITIN(v) \ + : GPIO1PIN_NPC7_INITOUT(v) ) + +#define GPIO1PIN_NPC7_INITIN(v) do{ \ + bFM_GPIO_PCRC_P7=(v).bPullup; \ + bFM_GPIO_DDRC_P7=0u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +#define GPIO1PIN_NPC7_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P7=1u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +/*---- GPIO bit PC8 ----*/ +#define GPIO1PIN_PC8_GET ( bFM_GPIO_PDIRC_P8 ) + +#define GPIO1PIN_PC8_PUT(v) ( bFM_GPIO_PDORC_P8=(v) ) + +#define GPIO1PIN_PC8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC8_INITIN(v) \ + : GPIO1PIN_PC8_INITOUT(v) ) + +#define GPIO1PIN_PC8_INITIN(v) do{ \ + bFM_GPIO_PCRC_P8=(v).bPullup; \ + bFM_GPIO_DDRC_P8=0u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +#define GPIO1PIN_PC8_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P8=(v).bInitVal; \ + bFM_GPIO_DDRC_P8=1u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +/*---- GPIO bit NPC8 ----*/ +#define GPIO1PIN_NPC8_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P8)) ) + +#define GPIO1PIN_NPC8_PUT(v) ( bFM_GPIO_PDORC_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC8_INITIN(v) \ + : GPIO1PIN_NPC8_INITOUT(v) ) + +#define GPIO1PIN_NPC8_INITIN(v) do{ \ + bFM_GPIO_PCRC_P8=(v).bPullup; \ + bFM_GPIO_DDRC_P8=0u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +#define GPIO1PIN_NPC8_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P8=1u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +/*---- GPIO bit PC9 ----*/ +#define GPIO1PIN_PC9_GET ( bFM_GPIO_PDIRC_P9 ) + +#define GPIO1PIN_PC9_PUT(v) ( bFM_GPIO_PDORC_P9=(v) ) + +#define GPIO1PIN_PC9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC9_INITIN(v) \ + : GPIO1PIN_PC9_INITOUT(v) ) + +#define GPIO1PIN_PC9_INITIN(v) do{ \ + bFM_GPIO_PCRC_P9=(v).bPullup; \ + bFM_GPIO_DDRC_P9=0u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +#define GPIO1PIN_PC9_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P9=(v).bInitVal; \ + bFM_GPIO_DDRC_P9=1u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +/*---- GPIO bit NPC9 ----*/ +#define GPIO1PIN_NPC9_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P9)) ) + +#define GPIO1PIN_NPC9_PUT(v) ( bFM_GPIO_PDORC_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC9_INITIN(v) \ + : GPIO1PIN_NPC9_INITOUT(v) ) + +#define GPIO1PIN_NPC9_INITIN(v) do{ \ + bFM_GPIO_PCRC_P9=(v).bPullup; \ + bFM_GPIO_DDRC_P9=0u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +#define GPIO1PIN_NPC9_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P9=1u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +/*---- GPIO bit PCA ----*/ +#define GPIO1PIN_PCA_GET ( bFM_GPIO_PDIRC_PA ) + +#define GPIO1PIN_PCA_PUT(v) ( bFM_GPIO_PDORC_PA=(v) ) + +#define GPIO1PIN_PCA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCA_INITIN(v) \ + : GPIO1PIN_PCA_INITOUT(v) ) + +#define GPIO1PIN_PCA_INITIN(v) do{ \ + bFM_GPIO_PCRC_PA=(v).bPullup; \ + bFM_GPIO_DDRC_PA=0u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +#define GPIO1PIN_PCA_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PA=(v).bInitVal; \ + bFM_GPIO_DDRC_PA=1u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +/*---- GPIO bit NPCA ----*/ +#define GPIO1PIN_NPCA_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PA)) ) + +#define GPIO1PIN_NPCA_PUT(v) ( bFM_GPIO_PDORC_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCA_INITIN(v) \ + : GPIO1PIN_NPCA_INITOUT(v) ) + +#define GPIO1PIN_NPCA_INITIN(v) do{ \ + bFM_GPIO_PCRC_PA=(v).bPullup; \ + bFM_GPIO_DDRC_PA=0u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +#define GPIO1PIN_NPCA_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PA=1u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +/*---- GPIO bit PCB ----*/ +#define GPIO1PIN_PCB_GET ( bFM_GPIO_PDIRC_PB ) + +#define GPIO1PIN_PCB_PUT(v) ( bFM_GPIO_PDORC_PB=(v) ) + +#define GPIO1PIN_PCB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCB_INITIN(v) \ + : GPIO1PIN_PCB_INITOUT(v) ) + +#define GPIO1PIN_PCB_INITIN(v) do{ \ + bFM_GPIO_PCRC_PB=(v).bPullup; \ + bFM_GPIO_DDRC_PB=0u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +#define GPIO1PIN_PCB_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PB=(v).bInitVal; \ + bFM_GPIO_DDRC_PB=1u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +/*---- GPIO bit NPCB ----*/ +#define GPIO1PIN_NPCB_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PB)) ) + +#define GPIO1PIN_NPCB_PUT(v) ( bFM_GPIO_PDORC_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCB_INITIN(v) \ + : GPIO1PIN_NPCB_INITOUT(v) ) + +#define GPIO1PIN_NPCB_INITIN(v) do{ \ + bFM_GPIO_PCRC_PB=(v).bPullup; \ + bFM_GPIO_DDRC_PB=0u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +#define GPIO1PIN_NPCB_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PB=1u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +/*---- GPIO bit PCC ----*/ +#define GPIO1PIN_PCC_GET ( bFM_GPIO_PDIRC_PC ) + +#define GPIO1PIN_PCC_PUT(v) ( bFM_GPIO_PDORC_PC=(v) ) + +#define GPIO1PIN_PCC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCC_INITIN(v) \ + : GPIO1PIN_PCC_INITOUT(v) ) + +#define GPIO1PIN_PCC_INITIN(v) do{ \ + bFM_GPIO_PCRC_PC=(v).bPullup; \ + bFM_GPIO_DDRC_PC=0u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +#define GPIO1PIN_PCC_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PC=(v).bInitVal; \ + bFM_GPIO_DDRC_PC=1u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +/*---- GPIO bit NPCC ----*/ +#define GPIO1PIN_NPCC_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PC)) ) + +#define GPIO1PIN_NPCC_PUT(v) ( bFM_GPIO_PDORC_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCC_INITIN(v) \ + : GPIO1PIN_NPCC_INITOUT(v) ) + +#define GPIO1PIN_NPCC_INITIN(v) do{ \ + bFM_GPIO_PCRC_PC=(v).bPullup; \ + bFM_GPIO_DDRC_PC=0u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +#define GPIO1PIN_NPCC_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PC=1u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +/*---- GPIO bit PCD ----*/ +#define GPIO1PIN_PCD_GET ( bFM_GPIO_PDIRC_PD ) + +#define GPIO1PIN_PCD_PUT(v) ( bFM_GPIO_PDORC_PD=(v) ) + +#define GPIO1PIN_PCD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCD_INITIN(v) \ + : GPIO1PIN_PCD_INITOUT(v) ) + +#define GPIO1PIN_PCD_INITIN(v) do{ \ + bFM_GPIO_PCRC_PD=(v).bPullup; \ + bFM_GPIO_DDRC_PD=0u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +#define GPIO1PIN_PCD_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PD=(v).bInitVal; \ + bFM_GPIO_DDRC_PD=1u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +/*---- GPIO bit NPCD ----*/ +#define GPIO1PIN_NPCD_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PD)) ) + +#define GPIO1PIN_NPCD_PUT(v) ( bFM_GPIO_PDORC_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCD_INITIN(v) \ + : GPIO1PIN_NPCD_INITOUT(v) ) + +#define GPIO1PIN_NPCD_INITIN(v) do{ \ + bFM_GPIO_PCRC_PD=(v).bPullup; \ + bFM_GPIO_DDRC_PD=0u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +#define GPIO1PIN_NPCD_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PD=1u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +/*---- GPIO bit PCE ----*/ +#define GPIO1PIN_PCE_GET ( bFM_GPIO_PDIRC_PE ) + +#define GPIO1PIN_PCE_PUT(v) ( bFM_GPIO_PDORC_PE=(v) ) + +#define GPIO1PIN_PCE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCE_INITIN(v) \ + : GPIO1PIN_PCE_INITOUT(v) ) + +#define GPIO1PIN_PCE_INITIN(v) do{ \ + bFM_GPIO_PCRC_PE=(v).bPullup; \ + bFM_GPIO_DDRC_PE=0u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +#define GPIO1PIN_PCE_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PE=(v).bInitVal; \ + bFM_GPIO_DDRC_PE=1u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +/*---- GPIO bit NPCE ----*/ +#define GPIO1PIN_NPCE_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PE)) ) + +#define GPIO1PIN_NPCE_PUT(v) ( bFM_GPIO_PDORC_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCE_INITIN(v) \ + : GPIO1PIN_NPCE_INITOUT(v) ) + +#define GPIO1PIN_NPCE_INITIN(v) do{ \ + bFM_GPIO_PCRC_PE=(v).bPullup; \ + bFM_GPIO_DDRC_PE=0u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +#define GPIO1PIN_NPCE_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PE=1u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +/*---- GPIO bit PCF ----*/ +#define GPIO1PIN_PCF_GET ( bFM_GPIO_PDIRC_PF ) + +#define GPIO1PIN_PCF_PUT(v) ( bFM_GPIO_PDORC_PF=(v) ) + +#define GPIO1PIN_PCF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCF_INITIN(v) \ + : GPIO1PIN_PCF_INITOUT(v) ) + +#define GPIO1PIN_PCF_INITIN(v) do{ \ + bFM_GPIO_PCRC_PF=(v).bPullup; \ + bFM_GPIO_DDRC_PF=0u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +#define GPIO1PIN_PCF_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PF=(v).bInitVal; \ + bFM_GPIO_DDRC_PF=1u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +/*---- GPIO bit NPCF ----*/ +#define GPIO1PIN_NPCF_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PF)) ) + +#define GPIO1PIN_NPCF_PUT(v) ( bFM_GPIO_PDORC_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCF_INITIN(v) \ + : GPIO1PIN_NPCF_INITOUT(v) ) + +#define GPIO1PIN_NPCF_INITIN(v) do{ \ + bFM_GPIO_PCRC_PF=(v).bPullup; \ + bFM_GPIO_DDRC_PF=0u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +#define GPIO1PIN_NPCF_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PF=1u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +/*---- GPIO bit PD0 ----*/ +#define GPIO1PIN_PD0_GET ( bFM_GPIO_PDIRD_P0 ) + +#define GPIO1PIN_PD0_PUT(v) ( bFM_GPIO_PDORD_P0=(v) ) + +#define GPIO1PIN_PD0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PD0_INITIN(v) \ + : GPIO1PIN_PD0_INITOUT(v) ) + +#define GPIO1PIN_PD0_INITIN(v) do{ \ + bFM_GPIO_PCRD_P0=(v).bPullup; \ + bFM_GPIO_DDRD_P0=0u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +#define GPIO1PIN_PD0_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P0=(v).bInitVal; \ + bFM_GPIO_DDRD_P0=1u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +/*---- GPIO bit NPD0 ----*/ +#define GPIO1PIN_NPD0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRD_P0)) ) + +#define GPIO1PIN_NPD0_PUT(v) ( bFM_GPIO_PDORD_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPD0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPD0_INITIN(v) \ + : GPIO1PIN_NPD0_INITOUT(v) ) + +#define GPIO1PIN_NPD0_INITIN(v) do{ \ + bFM_GPIO_PCRD_P0=(v).bPullup; \ + bFM_GPIO_DDRD_P0=0u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +#define GPIO1PIN_NPD0_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRD_P0=1u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +/*---- GPIO bit PD1 ----*/ +#define GPIO1PIN_PD1_GET ( bFM_GPIO_PDIRD_P1 ) + +#define GPIO1PIN_PD1_PUT(v) ( bFM_GPIO_PDORD_P1=(v) ) + +#define GPIO1PIN_PD1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PD1_INITIN(v) \ + : GPIO1PIN_PD1_INITOUT(v) ) + +#define GPIO1PIN_PD1_INITIN(v) do{ \ + bFM_GPIO_PCRD_P1=(v).bPullup; \ + bFM_GPIO_DDRD_P1=0u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +#define GPIO1PIN_PD1_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P1=(v).bInitVal; \ + bFM_GPIO_DDRD_P1=1u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +/*---- GPIO bit NPD1 ----*/ +#define GPIO1PIN_NPD1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRD_P1)) ) + +#define GPIO1PIN_NPD1_PUT(v) ( bFM_GPIO_PDORD_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPD1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPD1_INITIN(v) \ + : GPIO1PIN_NPD1_INITOUT(v) ) + +#define GPIO1PIN_NPD1_INITIN(v) do{ \ + bFM_GPIO_PCRD_P1=(v).bPullup; \ + bFM_GPIO_DDRD_P1=0u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +#define GPIO1PIN_NPD1_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRD_P1=1u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +/*---- GPIO bit PD2 ----*/ +#define GPIO1PIN_PD2_GET ( bFM_GPIO_PDIRD_P2 ) + +#define GPIO1PIN_PD2_PUT(v) ( bFM_GPIO_PDORD_P2=(v) ) + +#define GPIO1PIN_PD2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PD2_INITIN(v) \ + : GPIO1PIN_PD2_INITOUT(v) ) + +#define GPIO1PIN_PD2_INITIN(v) do{ \ + bFM_GPIO_PCRD_P2=(v).bPullup; \ + bFM_GPIO_DDRD_P2=0u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +#define GPIO1PIN_PD2_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P2=(v).bInitVal; \ + bFM_GPIO_DDRD_P2=1u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +/*---- GPIO bit NPD2 ----*/ +#define GPIO1PIN_NPD2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRD_P2)) ) + +#define GPIO1PIN_NPD2_PUT(v) ( bFM_GPIO_PDORD_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPD2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPD2_INITIN(v) \ + : GPIO1PIN_NPD2_INITOUT(v) ) + +#define GPIO1PIN_NPD2_INITIN(v) do{ \ + bFM_GPIO_PCRD_P2=(v).bPullup; \ + bFM_GPIO_DDRD_P2=0u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +#define GPIO1PIN_NPD2_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRD_P2=1u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +/*---- GPIO bit PE0 ----*/ +#define GPIO1PIN_PE0_GET ( bFM_GPIO_PDIRE_P0 ) + +#define GPIO1PIN_PE0_PUT(v) ( bFM_GPIO_PDORE_P0=(v) ) + +#define GPIO1PIN_PE0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PE0_INITIN(v) \ + : GPIO1PIN_PE0_INITOUT(v) ) + +#define GPIO1PIN_PE0_INITIN(v) do{ \ + bFM_GPIO_PCRE_P0=(v).bPullup; \ + bFM_GPIO_DDRE_P0=0u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +#define GPIO1PIN_PE0_INITOUT(v) do{ \ + bFM_GPIO_PDORE_P0=(v).bInitVal; \ + bFM_GPIO_DDRE_P0=1u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +/*---- GPIO bit NPE0 ----*/ +#define GPIO1PIN_NPE0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRE_P0)) ) + +#define GPIO1PIN_NPE0_PUT(v) ( bFM_GPIO_PDORE_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPE0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPE0_INITIN(v) \ + : GPIO1PIN_NPE0_INITOUT(v) ) + +#define GPIO1PIN_NPE0_INITIN(v) do{ \ + bFM_GPIO_PCRE_P0=(v).bPullup; \ + bFM_GPIO_DDRE_P0=0u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +#define GPIO1PIN_NPE0_INITOUT(v) do{ \ + bFM_GPIO_PDORE_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRE_P0=1u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +/*---- GPIO bit PE2 ----*/ +#define GPIO1PIN_PE2_GET ( bFM_GPIO_PDIRE_P2 ) + +#define GPIO1PIN_PE2_PUT(v) ( bFM_GPIO_PDORE_P2=(v) ) + +#define GPIO1PIN_PE2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PE2_INITIN(v) \ + : GPIO1PIN_PE2_INITOUT(v) ) + +#define GPIO1PIN_PE2_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P2=(v).bPullup; \ + bFM_GPIO_DDRE_P2=0u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +#define GPIO1PIN_PE2_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P2=(v).bInitVal; \ + bFM_GPIO_DDRE_P2=1u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +/*---- GPIO bit NPE2 ----*/ +#define GPIO1PIN_NPE2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRE_P2)) ) + +#define GPIO1PIN_NPE2_PUT(v) ( bFM_GPIO_PDORE_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPE2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPE2_INITIN(v) \ + : GPIO1PIN_NPE2_INITOUT(v) ) + +#define GPIO1PIN_NPE2_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P2=(v).bPullup; \ + bFM_GPIO_DDRE_P2=0u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +#define GPIO1PIN_NPE2_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRE_P2=1u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +/*---- GPIO bit PE3 ----*/ +#define GPIO1PIN_PE3_GET ( bFM_GPIO_PDIRE_P3 ) + +#define GPIO1PIN_PE3_PUT(v) ( bFM_GPIO_PDORE_P3=(v) ) + +#define GPIO1PIN_PE3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PE3_INITIN(v) \ + : GPIO1PIN_PE3_INITOUT(v) ) + +#define GPIO1PIN_PE3_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P3=(v).bPullup; \ + bFM_GPIO_DDRE_P3=0u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +#define GPIO1PIN_PE3_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P3=(v).bInitVal; \ + bFM_GPIO_DDRE_P3=1u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +/*---- GPIO bit NPE3 ----*/ +#define GPIO1PIN_NPE3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRE_P3)) ) + +#define GPIO1PIN_NPE3_PUT(v) ( bFM_GPIO_PDORE_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPE3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPE3_INITIN(v) \ + : GPIO1PIN_NPE3_INITOUT(v) ) + +#define GPIO1PIN_NPE3_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P3=(v).bPullup; \ + bFM_GPIO_DDRE_P3=0u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +#define GPIO1PIN_NPE3_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRE_P3=1u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +/****************************************************************************** + PIN RELOCATION +*******************************************************************************/ + +/*--- ADTG_0_ADC0 ---*/ +#define SetPinFunc_ADTG_0_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ADTG_0_ADC1 ---*/ +#define SetPinFunc_ADTG_0_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ADTG_0_ADC2 ---*/ +#define SetPinFunc_ADTG_0_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ADTG_1_ADC0 ---*/ +#define SetPinFunc_ADTG_1_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- ADTG_1_ADC1 ---*/ +#define SetPinFunc_ADTG_1_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- ADTG_1_ADC2 ---*/ +#define SetPinFunc_ADTG_1_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- ADTG_2_ADC0 ---*/ +#define SetPinFunc_ADTG_2_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 3u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- ADTG_2_ADC1 ---*/ +#define SetPinFunc_ADTG_2_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 3u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- ADTG_2_ADC2 ---*/ +#define SetPinFunc_ADTG_2_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 3u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- ADTG_3_ADC0 ---*/ +#define SetPinFunc_ADTG_3_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 4u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- ADTG_3_ADC1 ---*/ +#define SetPinFunc_ADTG_3_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 4u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- ADTG_3_ADC2 ---*/ +#define SetPinFunc_ADTG_3_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 4u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- ADTG_4_ADC0 ---*/ +#define SetPinFunc_ADTG_4_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 5u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- ADTG_4_ADC1 ---*/ +#define SetPinFunc_ADTG_4_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 5u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- ADTG_4_ADC2 ---*/ +#define SetPinFunc_ADTG_4_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 5u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- ADTG_5_ADC0 ---*/ +#define SetPinFunc_ADTG_5_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 6u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- ADTG_5_ADC1 ---*/ +#define SetPinFunc_ADTG_5_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 6u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- ADTG_5_ADC2 ---*/ +#define SetPinFunc_ADTG_5_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 6u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- ADTG_7_ADC0 ---*/ +#define SetPinFunc_ADTG_7_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 8u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- ADTG_7_ADC1 ---*/ +#define SetPinFunc_ADTG_7_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 8u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- ADTG_7_ADC2 ---*/ +#define SetPinFunc_ADTG_7_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 8u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- ADTG_8_ADC0 ---*/ +#define SetPinFunc_ADTG_8_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 9u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- ADTG_8_ADC1 ---*/ +#define SetPinFunc_ADTG_8_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 9u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- ADTG_8_ADC2 ---*/ +#define SetPinFunc_ADTG_8_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 9u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- AIN0_0 ---*/ +#define SetPinFunc_AIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 0u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- AIN0_2 ---*/ +#define SetPinFunc_AIN0_2(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 0u, 2u, 3u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- AIN1_0 ---*/ +#define SetPinFunc_AIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 6u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- AIN1_2 ---*/ +#define SetPinFunc_AIN1_2(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 6u, 2u, 3u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- AIN2_0 ---*/ +#define SetPinFunc_AIN2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- AIN2_1 ---*/ +#define SetPinFunc_AIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 0u, 2u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- AIN3_0 ---*/ +#define SetPinFunc_AIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- AIN3_1 ---*/ +#define SetPinFunc_AIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- BIN0_0 ---*/ +#define SetPinFunc_BIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- BIN0_2 ---*/ +#define SetPinFunc_BIN0_2(dummy) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 2u, 2u, 3u ); \ + bFM_GPIO_PFR1_P1 = 1u; \ + }while (0u) + +/*--- BIN1_0 ---*/ +#define SetPinFunc_BIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 8u, 2u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- BIN1_2 ---*/ +#define SetPinFunc_BIN1_2(dummy) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 8u, 2u, 3u ); \ + bFM_GPIO_PFR1_P6 = 1u; \ + }while (0u) + +/*--- BIN2_0 ---*/ +#define SetPinFunc_BIN2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- BIN2_1 ---*/ +#define SetPinFunc_BIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_P2 = 1u; \ + }while (0u) + +/*--- BIN3_0 ---*/ +#define SetPinFunc_BIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 6u, 2u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- BIN3_1 ---*/ +#define SetPinFunc_BIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 6u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- CROUT_0 ---*/ +#define SetPinFunc_CROUT_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 1u, 2u, 1u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- CROUT_1 ---*/ +#define SetPinFunc_CROUT_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 1u, 2u, 2u ); \ + bFM_GPIO_PFRC_P7 = 1u; \ + }while (0u) + +/*--- CTS4_1 ---*/ +#define SetPinFunc_CTS4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 2u, 2u, 2u ); \ + bFM_GPIO_PFRD_P2 = 1u; \ + }while (0u) + +/*--- CTS5_0 ---*/ +#define SetPinFunc_CTS5_0(dummy) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 30u, 2u, 1u ); \ + bFM_GPIO_PFR2_PA = 1u; \ + }while (0u) + +/*--- DA0 ---*/ +#define SetPinFunc_DA0(dummy) do{ \ + /* bFM_DAC0_DACR_DAE=1u; */ \ + }while (0u) + +/*--- DA1 ---*/ +#define SetPinFunc_DA1(dummy) do{ \ + /* bFM_DAC1_DACR_DAE=1u; */ \ + }while (0u) + +/*--- DTTI0X_0 ---*/ +#define SetPinFunc_DTTI0X_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 16u, 2u, 1u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- DTTI1X_0 ---*/ +#define SetPinFunc_DTTI1X_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 16u, 2u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- DTTI2X_0 ---*/ +#define SetPinFunc_DTTI2X_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 16u, 2u, 1u ); \ + bFM_GPIO_PFRA_P6 = 1u; \ + }while (0u) + +/*--- FRCK0_0 ---*/ +#define SetPinFunc_FRCK0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 18u, 2u, 1u ); \ + bFM_GPIO_PFR3_P3 = 1u; \ + }while (0u) + +/*--- FRCK1_0 ---*/ +#define SetPinFunc_FRCK1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 18u, 2u, 1u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- FRCK2_0 ---*/ +#define SetPinFunc_FRCK2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 18u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- FRCK2_1 ---*/ +#define SetPinFunc_FRCK2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 18u, 2u, 2u ); \ + bFM_GPIO_PFRD_P2 = 1u; \ + }while (0u) + +/*--- IC00_0 ---*/ +#define SetPinFunc_IC00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 1u ); \ + bFM_GPIO_PFR3_P7 = 1u; \ + }while (0u) + +/*--- IC00_LSYN0 ---*/ +#define SetPinFunc_IC00_LSYN0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 4u ); \ + }while (0u) + +/*--- IC00_LSYN4 ---*/ +#define SetPinFunc_IC00_LSYN4(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 5u ); \ + }while (0u) + +/*--- IC01_0 ---*/ +#define SetPinFunc_IC01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 1u ); \ + bFM_GPIO_PFR3_P6 = 1u; \ + }while (0u) + +/*--- IC01_LSYN1 ---*/ +#define SetPinFunc_IC01_LSYN1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 4u ); \ + }while (0u) + +/*--- IC01_LSYN5 ---*/ +#define SetPinFunc_IC01_LSYN5(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 5u ); \ + }while (0u) + +/*--- IC02_0 ---*/ +#define SetPinFunc_IC02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 1u ); \ + bFM_GPIO_PFR3_P5 = 1u; \ + }while (0u) + +/*--- IC02_LSYN2 ---*/ +#define SetPinFunc_IC02_LSYN2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 4u ); \ + }while (0u) + +/*--- IC02_LSYN6 ---*/ +#define SetPinFunc_IC02_LSYN6(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 5u ); \ + }while (0u) + +/*--- IC03_0 ---*/ +#define SetPinFunc_IC03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 1u ); \ + bFM_GPIO_PFR3_P4 = 1u; \ + }while (0u) + +/*--- IC03_LSYN3 ---*/ +#define SetPinFunc_IC03_LSYN3(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 4u ); \ + }while (0u) + +/*--- IC03_LSYN7 ---*/ +#define SetPinFunc_IC03_LSYN7(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 5u ); \ + }while (0u) + +/*--- IC10_0 ---*/ +#define SetPinFunc_IC10_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- IC10_LSYN0 ---*/ +#define SetPinFunc_IC10_LSYN0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 4u ); \ + }while (0u) + +/*--- IC10_LSYN4 ---*/ +#define SetPinFunc_IC10_LSYN4(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 5u ); \ + }while (0u) + +/*--- IC11_0 ---*/ +#define SetPinFunc_IC11_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 1u ); \ + bFM_GPIO_PFR7_P9 = 1u; \ + }while (0u) + +/*--- IC11_LSYN1 ---*/ +#define SetPinFunc_IC11_LSYN1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 4u ); \ + }while (0u) + +/*--- IC11_LSYN5 ---*/ +#define SetPinFunc_IC11_LSYN5(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 5u ); \ + }while (0u) + +/*--- IC12_0 ---*/ +#define SetPinFunc_IC12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 1u ); \ + bFM_GPIO_PFR7_PA = 1u; \ + }while (0u) + +/*--- IC12_LSYN2 ---*/ +#define SetPinFunc_IC12_LSYN2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 4u ); \ + }while (0u) + +/*--- IC12_LSYN6 ---*/ +#define SetPinFunc_IC12_LSYN6(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 5u ); \ + }while (0u) + +/*--- IC13_0 ---*/ +#define SetPinFunc_IC13_0(dummy) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 1u ); \ + bFM_GPIO_PFR7_PB = 1u; \ + }while (0u) + +/*--- IC13_LSYN3 ---*/ +#define SetPinFunc_IC13_LSYN3(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 4u ); \ + }while (0u) + +/*--- IC13_LSYN7 ---*/ +#define SetPinFunc_IC13_LSYN7(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 5u ); \ + }while (0u) + +/*--- IC20_0 ---*/ +#define SetPinFunc_IC20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 1u ); \ + bFM_GPIO_PFRA_P7 = 1u; \ + }while (0u) + +/*--- IC20_LSYN0 ---*/ +#define SetPinFunc_IC20_LSYN0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 4u ); \ + }while (0u) + +/*--- IC20_LSYN4 ---*/ +#define SetPinFunc_IC20_LSYN4(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 5u ); \ + }while (0u) + +/*--- IC21_0 ---*/ +#define SetPinFunc_IC21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- IC21_LSYN1 ---*/ +#define SetPinFunc_IC21_LSYN1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 4u ); \ + }while (0u) + +/*--- IC21_LSYN5 ---*/ +#define SetPinFunc_IC21_LSYN5(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 5u ); \ + }while (0u) + +/*--- IC22_0 ---*/ +#define SetPinFunc_IC22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 1u ); \ + bFM_GPIO_PFRA_P9 = 1u; \ + }while (0u) + +/*--- IC22_LSYN2 ---*/ +#define SetPinFunc_IC22_LSYN2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 4u ); \ + }while (0u) + +/*--- IC22_LSYN6 ---*/ +#define SetPinFunc_IC22_LSYN6(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 5u ); \ + }while (0u) + +/*--- IC23_0 ---*/ +#define SetPinFunc_IC23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 1u ); \ + bFM_GPIO_PFRA_PA = 1u; \ + }while (0u) + +/*--- IC23_1 ---*/ +#define SetPinFunc_IC23_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 2u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- IC23_LSYN3 ---*/ +#define SetPinFunc_IC23_LSYN3(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 4u ); \ + }while (0u) + +/*--- IC23_LSYN7 ---*/ +#define SetPinFunc_IC23_LSYN7(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 5u ); \ + }while (0u) + +/*--- INT00_0 ---*/ +#define SetPinFunc_INT00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- INT00_1 ---*/ +#define SetPinFunc_INT00_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 0u, 2u, 2u ); \ + bFM_GPIO_PFR3_P4 = 1u; \ + }while (0u) + +/*--- INT01_0 ---*/ +#define SetPinFunc_INT01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- INT01_1 ---*/ +#define SetPinFunc_INT01_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_P5 = 1u; \ + }while (0u) + +/*--- INT02_0 ---*/ +#define SetPinFunc_INT02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- INT02_1 ---*/ +#define SetPinFunc_INT02_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_P6 = 1u; \ + }while (0u) + +/*--- INT03_0 ---*/ +#define SetPinFunc_INT03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 6u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- INT03_1 ---*/ +#define SetPinFunc_INT03_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 6u, 2u, 2u ); \ + bFM_GPIO_PFR3_P7 = 1u; \ + }while (0u) + +/*--- INT04_0 ---*/ +#define SetPinFunc_INT04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- INT04_1 ---*/ +#define SetPinFunc_INT04_1(dummy) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 8u, 2u, 2u ); \ + bFM_GPIO_PFR7_PC = 1u; \ + }while (0u) + +/*--- INT05_0 ---*/ +#define SetPinFunc_INT05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- INT06_0 ---*/ +#define SetPinFunc_INT06_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- INT07_0 ---*/ +#define SetPinFunc_INT07_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 14u, 2u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- INT08_0 ---*/ +#define SetPinFunc_INT08_0(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 16u, 2u, 1u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- INT09_0 ---*/ +#define SetPinFunc_INT09_0(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 18u, 2u, 1u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- INT10_0 ---*/ +#define SetPinFunc_INT10_0(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 20u, 2u, 1u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- INT11_0 ---*/ +#define SetPinFunc_INT11_0(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 22u, 2u, 1u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- INT12_0 ---*/ +#define SetPinFunc_INT12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_PF = 1u; \ + }while (0u) + +/*--- INT13_0 ---*/ +#define SetPinFunc_INT13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 26u, 2u, 1u ); \ + bFM_GPIO_PFRC_P7 = 1u; \ + }while (0u) + +/*--- INT14_0 ---*/ +#define SetPinFunc_INT14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 28u, 2u, 1u ); \ + bFM_GPIO_PFRC_PD = 1u; \ + }while (0u) + +/*--- INT15_0 ---*/ +#define SetPinFunc_INT15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 30u, 2u, 1u ); \ + bFM_GPIO_PFRC_PE = 1u; \ + }while (0u) + +/*--- INT16_0 ---*/ +#define SetPinFunc_INT16_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- INT16_1 ---*/ +#define SetPinFunc_INT16_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 0u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- INT17_0 ---*/ +#define SetPinFunc_INT17_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 2u, 2u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- INT17_1 ---*/ +#define SetPinFunc_INT17_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- INT18_0 ---*/ +#define SetPinFunc_INT18_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 4u, 2u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- INT18_1 ---*/ +#define SetPinFunc_INT18_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- INT19_0 ---*/ +#define SetPinFunc_INT19_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 6u, 2u, 1u ); \ + bFM_GPIO_PFR3_P2 = 1u; \ + }while (0u) + +/*--- INT19_1 ---*/ +#define SetPinFunc_INT19_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 6u, 2u, 2u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- INT20_0 ---*/ +#define SetPinFunc_INT20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 8u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- INT21_0 ---*/ +#define SetPinFunc_INT21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- INT22_0 ---*/ +#define SetPinFunc_INT22_0(dummy) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_PB = 1u; \ + }while (0u) + +/*--- INT23_0 ---*/ +#define SetPinFunc_INT23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 14u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- INT24_0 ---*/ +#define SetPinFunc_INT24_0(dummy) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 16u, 2u, 1u ); \ + bFM_GPIO_PFR2_P7 = 1u; \ + }while (0u) + +/*--- INT24_1 ---*/ +#define SetPinFunc_INT24_1(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 16u, 2u, 2u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- INT25_0 ---*/ +#define SetPinFunc_INT25_0(dummy) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 18u, 2u, 1u ); \ + bFM_GPIO_PFR2_P5 = 1u; \ + }while (0u) + +/*--- INT25_1 ---*/ +#define SetPinFunc_INT25_1(dummy) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 18u, 2u, 2u ); \ + bFM_GPIO_PFR1_P3 = 1u; \ + }while (0u) + +/*--- INT26_0 ---*/ +#define SetPinFunc_INT26_0(dummy) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 20u, 2u, 1u ); \ + bFM_GPIO_PFR2_P2 = 1u; \ + }while (0u) + +/*--- INT26_1 ---*/ +#define SetPinFunc_INT26_1(dummy) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 20u, 2u, 2u ); \ + bFM_GPIO_PFR1_PE = 1u; \ + }while (0u) + +/*--- INT27_0 ---*/ +#define SetPinFunc_INT27_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 22u, 2u, 1u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- INT27_1 ---*/ +#define SetPinFunc_INT27_1(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 22u, 2u, 2u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- INT28_0 ---*/ +#define SetPinFunc_INT28_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_PB = 1u; \ + }while (0u) + +/*--- INT29_0 ---*/ +#define SetPinFunc_INT29_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 26u, 2u, 1u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- INT30_0 ---*/ +#define SetPinFunc_INT30_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 28u, 2u, 1u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- INT30_1 ---*/ +#define SetPinFunc_INT30_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 28u, 2u, 2u ); \ + bFM_GPIO_PFRD_P0 = 1u; \ + }while (0u) + +/*--- INT31_0 ---*/ +#define SetPinFunc_INT31_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 30u, 2u, 1u ); \ + bFM_GPIO_PFR6_P0 = 1u; \ + }while (0u) + +/*--- INT31_1 ---*/ +#define SetPinFunc_INT31_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 30u, 2u, 2u ); \ + bFM_GPIO_PFRD_P1 = 1u; \ + }while (0u) + +/*--- MAD00_0 ---*/ +#define SetPinFunc_MAD00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 14u, 1u, 1u ); \ + bFM_GPIO_PFR7_P1 = 1u; \ + }while (0u) + +/*--- MAD01_0 ---*/ +#define SetPinFunc_MAD01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 2u, 1u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- MAD02_0 ---*/ +#define SetPinFunc_MAD02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 3u, 1u, 1u ); \ + bFM_GPIO_PFR7_P3 = 1u; \ + }while (0u) + +/*--- MAD03_0 ---*/ +#define SetPinFunc_MAD03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 4u, 1u, 1u ); \ + bFM_GPIO_PFR7_P4 = 1u; \ + }while (0u) + +/*--- MAD04_0 ---*/ +#define SetPinFunc_MAD04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 5u, 1u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- MAD05_0 ---*/ +#define SetPinFunc_MAD05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 6u, 1u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- MAD06_0 ---*/ +#define SetPinFunc_MAD06_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 7u, 1u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- MAD07_0 ---*/ +#define SetPinFunc_MAD07_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 8u, 1u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- MAD08_0 ---*/ +#define SetPinFunc_MAD08_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 15u, 1u, 1u ); \ + bFM_GPIO_PFR7_P9 = 1u; \ + }while (0u) + +/*--- MAD09_0 ---*/ +#define SetPinFunc_MAD09_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 16u, 1u, 1u ); \ + bFM_GPIO_PFR7_PA = 1u; \ + }while (0u) + +/*--- MAD10_0 ---*/ +#define SetPinFunc_MAD10_0(dummy) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 17u, 1u, 1u ); \ + bFM_GPIO_PFR1_PE = 1u; \ + }while (0u) + +/*--- MAD11_0 ---*/ +#define SetPinFunc_MAD11_0(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 18u, 1u, 1u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- MAD12_0 ---*/ +#define SetPinFunc_MAD12_0(dummy) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 19u, 1u, 1u ); \ + bFM_GPIO_PFR2_PA = 1u; \ + }while (0u) + +/*--- MAD13_0 ---*/ +#define SetPinFunc_MAD13_0(dummy) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 20u, 1u, 1u ); \ + bFM_GPIO_PFR2_P9 = 1u; \ + }while (0u) + +/*--- MAD14_0 ---*/ +#define SetPinFunc_MAD14_0(dummy) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 21u, 1u, 1u ); \ + bFM_GPIO_PFR2_P8 = 1u; \ + }while (0u) + +/*--- MAD15_0 ---*/ +#define SetPinFunc_MAD15_0(dummy) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 22u, 1u, 1u ); \ + bFM_GPIO_PFR2_P7 = 1u; \ + }while (0u) + +/*--- MAD16_0 ---*/ +#define SetPinFunc_MAD16_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 23u, 1u, 1u ); \ + bFM_GPIO_PFR2_P6 = 1u; \ + }while (0u) + +/*--- MAD17_0 ---*/ +#define SetPinFunc_MAD17_0(dummy) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 24u, 1u, 1u ); \ + bFM_GPIO_PFR2_P5 = 1u; \ + }while (0u) + +/*--- MAD18_0 ---*/ +#define SetPinFunc_MAD18_0(dummy) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 25u, 1u, 1u ); \ + bFM_GPIO_PFR2_P4 = 1u; \ + }while (0u) + +/*--- MAD19_0 ---*/ +#define SetPinFunc_MAD19_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 26u, 1u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- MAD20_0 ---*/ +#define SetPinFunc_MAD20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 27u, 1u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- MAD21_0 ---*/ +#define SetPinFunc_MAD21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 28u, 1u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- MAD22_0 ---*/ +#define SetPinFunc_MAD22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 29u, 1u, 1u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- MAD23_0 ---*/ +#define SetPinFunc_MAD23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 30u, 1u, 1u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- MAD24_0 ---*/ +#define SetPinFunc_MAD24_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 31u, 1u, 1u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- MADATA00_0 ---*/ +#define SetPinFunc_MADATA00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 9u, 1u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- MADATA01_0 ---*/ +#define SetPinFunc_MADATA01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 10u, 1u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- MADATA02_0 ---*/ +#define SetPinFunc_MADATA02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 11u, 1u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- MADATA03_0 ---*/ +#define SetPinFunc_MADATA03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 12u, 1u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- MADATA04_0 ---*/ +#define SetPinFunc_MADATA04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 13u, 1u, 1u ); \ + bFM_GPIO_PFRA_P4 = 1u; \ + }while (0u) + +/*--- MADATA05_0 ---*/ +#define SetPinFunc_MADATA05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 14u, 1u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- MADATA06_0 ---*/ +#define SetPinFunc_MADATA06_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 15u, 1u, 1u ); \ + bFM_GPIO_PFRA_P6 = 1u; \ + }while (0u) + +/*--- MADATA07_0 ---*/ +#define SetPinFunc_MADATA07_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 16u, 1u, 1u ); \ + bFM_GPIO_PFRA_P7 = 1u; \ + }while (0u) + +/*--- MADATA08_0 ---*/ +#define SetPinFunc_MADATA08_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 17u, 1u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- MADATA09_0 ---*/ +#define SetPinFunc_MADATA09_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 18u, 1u, 1u ); \ + bFM_GPIO_PFRA_P9 = 1u; \ + }while (0u) + +/*--- MADATA10_0 ---*/ +#define SetPinFunc_MADATA10_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 19u, 1u, 1u ); \ + bFM_GPIO_PFRA_PA = 1u; \ + }while (0u) + +/*--- MADATA11_0 ---*/ +#define SetPinFunc_MADATA11_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 20u, 1u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- MADATA12_0 ---*/ +#define SetPinFunc_MADATA12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 21u, 1u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- MADATA13_0 ---*/ +#define SetPinFunc_MADATA13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 22u, 1u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- MADATA14_0 ---*/ +#define SetPinFunc_MADATA14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 23u, 1u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- MADATA15_0 ---*/ +#define SetPinFunc_MADATA15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 24u, 1u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- MALE_0 ---*/ +#define SetPinFunc_MALE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 0u, 1u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- MCLKOUT_0 ---*/ +#define SetPinFunc_MCLKOUT_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 2u, 1u, 1u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- MCSX0_0 ---*/ +#define SetPinFunc_MCSX0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 1u, 1u, 1u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- MCSX1_0 ---*/ +#define SetPinFunc_MCSX1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 7u, 1u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- MCSX2_0 ---*/ +#define SetPinFunc_MCSX2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 8u, 1u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- MCSX3_0 ---*/ +#define SetPinFunc_MCSX3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 9u, 1u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- MCSX4_0 ---*/ +#define SetPinFunc_MCSX4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 10u, 1u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- MCSX5_0 ---*/ +#define SetPinFunc_MCSX5_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 11u, 1u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- MCSX6_0 ---*/ +#define SetPinFunc_MCSX6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 12u, 1u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- MCSX7_0 ---*/ +#define SetPinFunc_MCSX7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 13u, 1u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- MDQM0_0 ---*/ +#define SetPinFunc_MDQM0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 4u, 1u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- MDQM1_0 ---*/ +#define SetPinFunc_MDQM1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 4u, 1u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- MNALE_0 ---*/ +#define SetPinFunc_MNALE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- MNCLE_0 ---*/ +#define SetPinFunc_MNCLE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- MNREX_0 ---*/ +#define SetPinFunc_MNREX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- MNWEX_0 ---*/ +#define SetPinFunc_MNWEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- MOEX_0 ---*/ +#define SetPinFunc_MOEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 5u, 1u, 1u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- MRDY_0 ---*/ +#define SetPinFunc_MRDY_0(dummy) do{ \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- MWEX_0 ---*/ +#define SetPinFunc_MWEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 3u, 1u, 1u ); \ + bFM_GPIO_PFR6_P2 = 1u; \ + }while (0u) + +/*--- NMIX ---*/ +#define SetPinFunc_NMIX(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 0u, 1u, 1u ); \ + bFM_GPIO_PFR2_P0 = 1u; \ + }while (0u) + +/*--- RTCCO_0 ---*/ +#define SetPinFunc_RTCCO_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 4u, 2u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- RTO00_0 ---*/ +#define SetPinFunc_RTO00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 0u, 2u, 1u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- RTO01_0 ---*/ +#define SetPinFunc_RTO01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 2u, 2u, 1u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- RTO02_0 ---*/ +#define SetPinFunc_RTO02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 4u, 2u, 1u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- RTO03_0 ---*/ +#define SetPinFunc_RTO03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 6u, 2u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- RTO04_0 ---*/ +#define SetPinFunc_RTO04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 8u, 2u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- RTO05_0 ---*/ +#define SetPinFunc_RTO05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 10u, 2u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- RTO10_0 ---*/ +#define SetPinFunc_RTO10_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 0u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- RTO11_0 ---*/ +#define SetPinFunc_RTO11_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- RTO12_0 ---*/ +#define SetPinFunc_RTO12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 4u, 2u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- RTO13_0 ---*/ +#define SetPinFunc_RTO13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 6u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- RTO14_0 ---*/ +#define SetPinFunc_RTO14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- RTO15_0 ---*/ +#define SetPinFunc_RTO15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 10u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- RTO20_0 ---*/ +#define SetPinFunc_RTO20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- RTO21_0 ---*/ +#define SetPinFunc_RTO21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- RTO22_0 ---*/ +#define SetPinFunc_RTO22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- RTO23_0 ---*/ +#define SetPinFunc_RTO23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 6u, 2u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- RTO24_0 ---*/ +#define SetPinFunc_RTO24_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_P4 = 1u; \ + }while (0u) + +/*--- RTO25_0 ---*/ +#define SetPinFunc_RTO25_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- RTS4_0 ---*/ +#define SetPinFunc_RTS4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 0u, 2u, 1u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- RTS4_1 ---*/ +#define SetPinFunc_RTS4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 0u, 2u, 2u ); \ + bFM_GPIO_PFRC_PF = 1u; \ + }while (0u) + +/*--- RTS5_0 ---*/ +#define SetPinFunc_RTS5_0(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 28u, 2u, 1u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- RX0_0 ---*/ +#define SetPinFunc_RX0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- RX1_0 ---*/ +#define SetPinFunc_RX1_0(dummy) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 28u, 2u, 1u ); \ + bFM_GPIO_PFR2_P5 = 1u; \ + }while (0u) + +/*--- RX1_1 ---*/ +#define SetPinFunc_RX1_1(dummy) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 28u, 2u, 2u ); \ + bFM_GPIO_PFR1_P3 = 1u; \ + }while (0u) + +/*--- RX2_0 ---*/ +#define SetPinFunc_RX2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 0u, 2u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- SCK0_0 ---*/ +#define SetPinFunc_SCK0_0(dummy) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 8u, 2u, 1u ); \ + bFM_GPIO_PFR2_P3 = 1u; \ + }while (0u) + +/*--- SCK10_0 ---*/ +#define SetPinFunc_SCK10_0(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 20u, 2u, 1u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- SCK11_0 ---*/ +#define SetPinFunc_SCK11_0(dummy) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 26u, 2u, 1u ); \ + bFM_GPIO_PFR1_P7 = 1u; \ + }while (0u) + +/*--- SCK12_0 ---*/ +#define SetPinFunc_SCK12_0(dummy) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 8u, 2u, 1u ); \ + bFM_GPIO_PFR1_PD = 1u; \ + }while (0u) + +/*--- SCK13_0 ---*/ +#define SetPinFunc_SCK13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 14u, 2u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- SCK14_0 ---*/ +#define SetPinFunc_SCK14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 20u, 2u, 1u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- SCK15_0 ---*/ +#define SetPinFunc_SCK15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 26u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- SCK1_0 ---*/ +#define SetPinFunc_SCK1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 14u, 2u, 1u ); \ + bFM_GPIO_PFRA_P7 = 1u; \ + }while (0u) + +/*--- SCK1_1 ---*/ +#define SetPinFunc_SCK1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 14u, 2u, 2u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- SCK2_0 ---*/ +#define SetPinFunc_SCK2_0(dummy) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 20u, 2u, 1u ); \ + bFM_GPIO_PFR1_PA = 1u; \ + }while (0u) + +/*--- SCK2_1 ---*/ +#define SetPinFunc_SCK2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 20u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- SCK3_0 ---*/ +#define SetPinFunc_SCK3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- SCK3_1 ---*/ +#define SetPinFunc_SCK3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 26u, 2u, 2u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- SCK4_0 ---*/ +#define SetPinFunc_SCK4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 8u, 2u, 1u ); \ + bFM_GPIO_PFR6_P2 = 1u; \ + }while (0u) + +/*--- SCK4_1 ---*/ +#define SetPinFunc_SCK4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 8u, 2u, 2u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- SCK5_0 ---*/ +#define SetPinFunc_SCK5_0(dummy) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 14u, 2u, 1u ); \ + bFM_GPIO_PFR2_P9 = 1u; \ + }while (0u) + +/*--- SCK6_0 ---*/ +#define SetPinFunc_SCK6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 20u, 2u, 1u ); \ + bFM_GPIO_PFR7_PA = 1u; \ + }while (0u) + +/*--- SCK7_0 ---*/ +#define SetPinFunc_SCK7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_PA = 1u; \ + }while (0u) + +/*--- SCK8_0 ---*/ +#define SetPinFunc_SCK8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 8u, 2u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- SCK9_0 ---*/ +#define SetPinFunc_SCK9_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 14u, 2u, 1u ); \ + bFM_GPIO_PFR7_P4 = 1u; \ + }while (0u) + +/*--- SCS60_0 ---*/ +#define SetPinFunc_SCS60_0(dummy) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 0u, 2u, 1u ); \ + bFM_GPIO_PFR7_PB = 1u; \ + }while (0u) + +/*--- SCS61_0 ---*/ +#define SetPinFunc_SCS61_0(dummy) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 2u, 2u, 1u ); \ + bFM_GPIO_PFR7_PC = 1u; \ + }while (0u) + +/*--- SCS70_0 ---*/ +#define SetPinFunc_SCS70_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- SCS71_0 ---*/ +#define SetPinFunc_SCS71_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- SIN0_0 ---*/ +#define SetPinFunc_SIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 4u, 2u, 1u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- SIN10_0 ---*/ +#define SetPinFunc_SIN10_0(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 16u, 2u, 1u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- SIN11_0 ---*/ +#define SetPinFunc_SIN11_0(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 22u, 2u, 1u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- SIN12_0 ---*/ +#define SetPinFunc_SIN12_0(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 4u, 2u, 1u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- SIN13_0 ---*/ +#define SetPinFunc_SIN13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 10u, 2u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- SIN14_0 ---*/ +#define SetPinFunc_SIN14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 16u, 2u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- SIN15_0 ---*/ +#define SetPinFunc_SIN15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 22u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- SIN1_0 ---*/ +#define SetPinFunc_SIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- SIN1_1 ---*/ +#define SetPinFunc_SIN1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 10u, 2u, 2u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- SIN2_0 ---*/ +#define SetPinFunc_SIN2_0(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 16u, 2u, 1u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- SIN2_1 ---*/ +#define SetPinFunc_SIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 16u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- SIN3_0 ---*/ +#define SetPinFunc_SIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 22u, 2u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- SIN3_1 ---*/ +#define SetPinFunc_SIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 22u, 2u, 2u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- SIN4_0 ---*/ +#define SetPinFunc_SIN4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 4u, 2u, 1u ); \ + bFM_GPIO_PFR6_P0 = 1u; \ + }while (0u) + +/*--- SIN4_1 ---*/ +#define SetPinFunc_SIN4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 4u, 2u, 2u ); \ + bFM_GPIO_PFRC_PE = 1u; \ + }while (0u) + +/*--- SIN5_0 ---*/ +#define SetPinFunc_SIN5_0(dummy) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 10u, 2u, 1u ); \ + bFM_GPIO_PFR2_P7 = 1u; \ + }while (0u) + +/*--- SIN6_0 ---*/ +#define SetPinFunc_SIN6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 16u, 2u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- SIN6_1 ---*/ +#define SetPinFunc_SIN6_1(dummy) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 16u, 2u, 2u ); \ + bFM_GPIO_PFR1_P3 = 1u; \ + }while (0u) + +/*--- SIN7_0 ---*/ +#define SetPinFunc_SIN7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 22u, 2u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- SIN8_0 ---*/ +#define SetPinFunc_SIN8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 4u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- SIN9_0 ---*/ +#define SetPinFunc_SIN9_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- SOT0_0 ---*/ +#define SetPinFunc_SOT0_0(dummy) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 6u, 2u, 1u ); \ + bFM_GPIO_PFR2_P2 = 1u; \ + }while (0u) + +/*--- SOT10_0 ---*/ +#define SetPinFunc_SOT10_0(dummy) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 18u, 2u, 1u ); \ + bFM_GPIO_PFR1_P1 = 1u; \ + }while (0u) + +/*--- SOT11_0 ---*/ +#define SetPinFunc_SOT11_0(dummy) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 24u, 2u, 1u ); \ + bFM_GPIO_PFR1_P6 = 1u; \ + }while (0u) + +/*--- SOT12_0 ---*/ +#define SetPinFunc_SOT12_0(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 6u, 2u, 1u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- SOT13_0 ---*/ +#define SetPinFunc_SOT13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 12u, 2u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- SOT14_0 ---*/ +#define SetPinFunc_SOT14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 18u, 2u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- SOT15_0 ---*/ +#define SetPinFunc_SOT15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 24u, 2u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- SOT1_0 ---*/ +#define SetPinFunc_SOT1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 12u, 2u, 1u ); \ + bFM_GPIO_PFRA_P6 = 1u; \ + }while (0u) + +/*--- SOT1_1 ---*/ +#define SetPinFunc_SOT1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 12u, 2u, 2u ); \ + bFM_GPIO_PFR7_P1 = 1u; \ + }while (0u) + +/*--- SOT2_0 ---*/ +#define SetPinFunc_SOT2_0(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 18u, 2u, 1u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- SOT2_1 ---*/ +#define SetPinFunc_SOT2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 18u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- SOT3_0 ---*/ +#define SetPinFunc_SOT3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- SOT3_1 ---*/ +#define SetPinFunc_SOT3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 24u, 2u, 2u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- SOT4_0 ---*/ +#define SetPinFunc_SOT4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 6u, 2u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- SOT4_1 ---*/ +#define SetPinFunc_SOT4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 6u, 2u, 2u ); \ + bFM_GPIO_PFRC_PD = 1u; \ + }while (0u) + +/*--- SOT5_0 ---*/ +#define SetPinFunc_SOT5_0(dummy) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 12u, 2u, 1u ); \ + bFM_GPIO_PFR2_P8 = 1u; \ + }while (0u) + +/*--- SOT6_0 ---*/ +#define SetPinFunc_SOT6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 18u, 2u, 1u ); \ + bFM_GPIO_PFR7_P9 = 1u; \ + }while (0u) + +/*--- SOT6_1 ---*/ +#define SetPinFunc_SOT6_1(dummy) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 18u, 2u, 2u ); \ + bFM_GPIO_PFR1_P4 = 1u; \ + }while (0u) + +/*--- SOT7_0 ---*/ +#define SetPinFunc_SOT7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_P9 = 1u; \ + }while (0u) + +/*--- SOT8_0 ---*/ +#define SetPinFunc_SOT8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 6u, 2u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- SOT9_0 ---*/ +#define SetPinFunc_SOT9_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P3 = 1u; \ + }while (0u) + +/*--- SUBOUT_0 ---*/ +#define SetPinFunc_SUBOUT_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 6u, 2u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- SWCLK ---*/ +#define SetPinFunc_SWCLK(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P1 = 1u; \ + }while (0u) + +/*--- SWDIO ---*/ +#define SetPinFunc_SWDIO(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P3 = 1u; \ + }while (0u) + +/*--- SWO ---*/ +#define SetPinFunc_SWO(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P4 = 1u; \ + }while (0u) + +/*--- S_CD_0 ---*/ +#define SetPinFunc_S_CD_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 26u, 2u, 1u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- S_CLK_0 ---*/ +#define SetPinFunc_S_CLK_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 14u, 2u, 1u ); \ + bFM_GPIO_PFR3_P4 = 1u; \ + }while (0u) + +/*--- S_CMD_0 ---*/ +#define SetPinFunc_S_CMD_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 16u, 2u, 1u ); \ + bFM_GPIO_PFR3_P5 = 1u; \ + }while (0u) + +/*--- S_DATA0_0 ---*/ +#define SetPinFunc_S_DATA0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 18u, 2u, 1u ); \ + bFM_GPIO_PFR3_P3 = 1u; \ + }while (0u) + +/*--- S_DATA1_0 ---*/ +#define SetPinFunc_S_DATA1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 20u, 2u, 1u ); \ + bFM_GPIO_PFR3_P2 = 1u; \ + }while (0u) + +/*--- S_DATA2_0 ---*/ +#define SetPinFunc_S_DATA2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 22u, 2u, 1u ); \ + bFM_GPIO_PFR3_P7 = 1u; \ + }while (0u) + +/*--- S_DATA3_0 ---*/ +#define SetPinFunc_S_DATA3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 24u, 2u, 1u ); \ + bFM_GPIO_PFR3_P6 = 1u; \ + }while (0u) + +/*--- S_WP_0 ---*/ +#define SetPinFunc_S_WP_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 28u, 2u, 1u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- TCK ---*/ +#define SetPinFunc_TCK(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P1 = 1u; \ + }while (0u) + +/*--- TDI ---*/ +#define SetPinFunc_TDI(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 17u, 1u, 1u ); \ + bFM_GPIO_PFR0_P2 = 1u; \ + }while (0u) + +/*--- TDO ---*/ +#define SetPinFunc_TDO(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P4 = 1u; \ + }while (0u) + +/*--- TIOA0_0_OUT ---*/ +#define SetPinFunc_TIOA0_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- TIOA0_1_OUT ---*/ +#define SetPinFunc_TIOA0_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- TIOA0_2_OUT ---*/ +#define SetPinFunc_TIOA0_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 2u, 2u, 3u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- TIOA10_0_OUT ---*/ +#define SetPinFunc_TIOA10_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 18u, 2u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- TIOA11_0_IN ---*/ +#define SetPinFunc_TIOA11_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- TIOA11_0_OUT ---*/ +#define SetPinFunc_TIOA11_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- TIOA12_0_OUT ---*/ +#define SetPinFunc_TIOA12_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P4 = 1u; \ + }while (0u) + +/*--- TIOA13_0_IN ---*/ +#define SetPinFunc_TIOA13_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- TIOA13_0_OUT ---*/ +#define SetPinFunc_TIOA13_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- TIOA13_1_IN ---*/ +#define SetPinFunc_TIOA13_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 8u, 2u, 2u ); \ + bFM_GPIO_PFR2_P4 = 1u; \ + }while (0u) + +/*--- TIOA13_1_OUT ---*/ +#define SetPinFunc_TIOA13_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 10u, 2u, 2u ); \ + bFM_GPIO_PFR2_P4 = 1u; \ + }while (0u) + +/*--- TIOA14_0_OUT ---*/ +#define SetPinFunc_TIOA14_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 18u, 2u, 1u ); \ + bFM_GPIO_PFRC_P6 = 1u; \ + }while (0u) + +/*--- TIOA15_0_IN ---*/ +#define SetPinFunc_TIOA15_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_PA = 1u; \ + }while (0u) + +/*--- TIOA15_0_OUT ---*/ +#define SetPinFunc_TIOA15_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 26u, 2u, 1u ); \ + bFM_GPIO_PFRC_PA = 1u; \ + }while (0u) + +/*--- TIOA1_0_IN ---*/ +#define SetPinFunc_TIOA1_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- TIOA1_0_OUT ---*/ +#define SetPinFunc_TIOA1_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 10u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- TIOA1_1_IN ---*/ +#define SetPinFunc_TIOA1_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 8u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- TIOA1_1_OUT ---*/ +#define SetPinFunc_TIOA1_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 10u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- TIOA1_2_IN ---*/ +#define SetPinFunc_TIOA1_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 8u, 2u, 3u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- TIOA1_2_OUT ---*/ +#define SetPinFunc_TIOA1_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 10u, 2u, 3u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- TIOA2_0_OUT ---*/ +#define SetPinFunc_TIOA2_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 18u, 2u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- TIOA2_1_OUT ---*/ +#define SetPinFunc_TIOA2_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 18u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- TIOA2_2_OUT ---*/ +#define SetPinFunc_TIOA2_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 18u, 2u, 3u ); \ + bFM_GPIO_PFR1_P6 = 1u; \ + }while (0u) + +/*--- TIOA3_0_IN ---*/ +#define SetPinFunc_TIOA3_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 24u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- TIOA3_0_OUT ---*/ +#define SetPinFunc_TIOA3_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 26u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- TIOA3_1_IN ---*/ +#define SetPinFunc_TIOA3_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 24u, 2u, 2u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- TIOA3_1_OUT ---*/ +#define SetPinFunc_TIOA3_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 26u, 2u, 2u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- TIOA3_2_IN ---*/ +#define SetPinFunc_TIOA3_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 24u, 2u, 3u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- TIOA3_2_OUT ---*/ +#define SetPinFunc_TIOA3_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 26u, 2u, 3u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- TIOA4_0_OUT ---*/ +#define SetPinFunc_TIOA4_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- TIOA4_1_OUT ---*/ +#define SetPinFunc_TIOA4_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- TIOA4_2_OUT ---*/ +#define SetPinFunc_TIOA4_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 2u, 2u, 3u ); \ + bFM_GPIO_PFR1_PA = 1u; \ + }while (0u) + +/*--- TIOA5_0_IN ---*/ +#define SetPinFunc_TIOA5_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- TIOA5_0_OUT ---*/ +#define SetPinFunc_TIOA5_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 10u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- TIOA5_1_IN ---*/ +#define SetPinFunc_TIOA5_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 8u, 2u, 2u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- TIOA5_1_OUT ---*/ +#define SetPinFunc_TIOA5_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 10u, 2u, 2u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- TIOA5_2_IN ---*/ +#define SetPinFunc_TIOA5_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 8u, 2u, 3u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- TIOA5_2_OUT ---*/ +#define SetPinFunc_TIOA5_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 10u, 2u, 3u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- TIOA6_0_OUT ---*/ +#define SetPinFunc_TIOA6_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 18u, 2u, 1u ); \ + bFM_GPIO_PFRC_P2 = 1u; \ + }while (0u) + +/*--- TIOA7_0_IN ---*/ +#define SetPinFunc_TIOA7_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_P4 = 1u; \ + }while (0u) + +/*--- TIOA7_0_OUT ---*/ +#define SetPinFunc_TIOA7_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 26u, 2u, 1u ); \ + bFM_GPIO_PFRC_P4 = 1u; \ + }while (0u) + +/*--- TIOA8_0_OUT ---*/ +#define SetPinFunc_TIOA8_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- TIOA8_1_OUT ---*/ +#define SetPinFunc_TIOA8_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 2u, 2u, 2u ); \ + bFM_GPIO_PFR1_PE = 1u; \ + }while (0u) + +/*--- TIOA9_0_IN ---*/ +#define SetPinFunc_TIOA9_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- TIOA9_0_OUT ---*/ +#define SetPinFunc_TIOA9_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- TIOB0_0_IN ---*/ +#define SetPinFunc_TIOB0_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 4u, 3u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- TIOB0_2_IN ---*/ +#define SetPinFunc_TIOB0_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 4u, 3u, 3u ); \ + bFM_GPIO_PFR1_P1 = 1u; \ + }while (0u) + +/*--- TIOB10_0_IN ---*/ +#define SetPinFunc_TIOB10_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 20u, 2u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- TIOB11_0_IN ---*/ +#define SetPinFunc_TIOB11_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 28u, 2u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- TIOB12_0_IN ---*/ +#define SetPinFunc_TIOB12_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 4u, 2u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- TIOB13_0_IN ---*/ +#define SetPinFunc_TIOB13_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 12u, 2u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- TIOB13_1_IN ---*/ +#define SetPinFunc_TIOB13_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 12u, 2u, 2u ); \ + bFM_GPIO_PFR2_P3 = 1u; \ + }while (0u) + +/*--- TIOB14_0_IN ---*/ +#define SetPinFunc_TIOB14_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 20u, 2u, 1u ); \ + bFM_GPIO_PFRC_P5 = 1u; \ + }while (0u) + +/*--- TIOB15_0_IN ---*/ +#define SetPinFunc_TIOB15_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 28u, 2u, 1u ); \ + bFM_GPIO_PFRC_P9 = 1u; \ + }while (0u) + +/*--- TIOB1_0_IN ---*/ +#define SetPinFunc_TIOB1_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P3 = 1u; \ + }while (0u) + +/*--- TIOB1_2_IN ---*/ +#define SetPinFunc_TIOB1_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 12u, 2u, 3u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- TIOB2_0_IN ---*/ +#define SetPinFunc_TIOB2_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 20u, 2u, 1u ); \ + bFM_GPIO_PFR7_P4 = 1u; \ + }while (0u) + +/*--- TIOB2_2_IN ---*/ +#define SetPinFunc_TIOB2_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 20u, 2u, 3u ); \ + bFM_GPIO_PFR1_P7 = 1u; \ + }while (0u) + +/*--- TIOB3_0_IN ---*/ +#define SetPinFunc_TIOB3_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 28u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- TIOB3_2_IN ---*/ +#define SetPinFunc_TIOB3_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 28u, 2u, 3u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- TIOB4_0_IN ---*/ +#define SetPinFunc_TIOB4_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 4u, 2u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- TIOB4_2_IN ---*/ +#define SetPinFunc_TIOB4_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 4u, 2u, 3u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- TIOB5_0_IN ---*/ +#define SetPinFunc_TIOB5_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- TIOB5_2_IN ---*/ +#define SetPinFunc_TIOB5_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 12u, 2u, 3u ); \ + bFM_GPIO_PFR1_PD = 1u; \ + }while (0u) + +/*--- TIOB6_0_IN ---*/ +#define SetPinFunc_TIOB6_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 20u, 2u, 1u ); \ + bFM_GPIO_PFRC_P1 = 1u; \ + }while (0u) + +/*--- TIOB7_0_IN ---*/ +#define SetPinFunc_TIOB7_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 28u, 2u, 1u ); \ + bFM_GPIO_PFRC_P3 = 1u; \ + }while (0u) + +/*--- TIOB8_0_IN ---*/ +#define SetPinFunc_TIOB8_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- TIOB8_1_IN ---*/ +#define SetPinFunc_TIOB8_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 4u, 2u, 2u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- TIOB9_0_IN ---*/ +#define SetPinFunc_TIOB9_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 12u, 2u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- TMS ---*/ +#define SetPinFunc_TMS(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P3 = 1u; \ + }while (0u) + +/*--- TRACECLK ---*/ +#define SetPinFunc_TRACECLK(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 24u, 1u, 1u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- TRACED0 ---*/ +#define SetPinFunc_TRACED0(dummy) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 24u, 1u, 1u ); \ + bFM_GPIO_PFR1_PA = 1u; \ + }while (0u) + +/*--- TRACED1 ---*/ +#define SetPinFunc_TRACED1(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 24u, 1u, 1u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- TRACED2 ---*/ +#define SetPinFunc_TRACED2(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 25u, 1u, 1u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- TRACED3 ---*/ +#define SetPinFunc_TRACED3(dummy) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 25u, 1u, 1u ); \ + bFM_GPIO_PFR1_PD = 1u; \ + }while (0u) + +/*--- TRSTX ---*/ +#define SetPinFunc_TRSTX(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 17u, 1u, 1u ); \ + bFM_GPIO_PFR0_P0 = 1u; \ + }while (0u) + +/*--- TX0_0 ---*/ +#define SetPinFunc_TX0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- TX1_0 ---*/ +#define SetPinFunc_TX1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 30u, 2u, 1u ); \ + bFM_GPIO_PFR2_P6 = 1u; \ + }while (0u) + +/*--- TX1_1 ---*/ +#define SetPinFunc_TX1_1(dummy) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 30u, 2u, 2u ); \ + bFM_GPIO_PFR1_P4 = 1u; \ + }while (0u) + +/*--- TX2_0 ---*/ +#define SetPinFunc_TX2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 2u, 2u, 1u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- UDM0 ---*/ +#define SetPinFunc_UDM0(dummy) do{ \ + bFM_GPIO_SPSR_USB0C=1u; \ + }while (0u) + +/*--- UDM1 ---*/ +#define SetPinFunc_UDM1(dummy) do{ \ + bFM_GPIO_SPSR_USB1C=1u; \ + }while (0u) + +/*--- UDP0 ---*/ +#define SetPinFunc_UDP0(dummy) do{ \ + bFM_GPIO_SPSR_USB0C=1u; \ + }while (0u) + +/*--- UDP1 ---*/ +#define SetPinFunc_UDP1(dummy) do{ \ + bFM_GPIO_SPSR_USB1C=1u; \ + }while (0u) + +/*--- UHCONX0 ---*/ +#define SetPinFunc_UHCONX0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 9u, 1u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- UHCONX1 ---*/ +#define SetPinFunc_UHCONX1(dummy) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 13u, 1u, 1u ); \ + bFM_GPIO_PFR2_P3 = 1u; \ + }while (0u) + +/*--- VREGCTL ---*/ +#define SetPinFunc_VREGCTL(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- VWAKEUP ---*/ +#define SetPinFunc_VWAKEUP(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- WKUP0 ---*/ +#define SetPinFunc_WKUP0(dummy) do{ \ + bFM_GPIO_PFR2_P0 = 1u; \ + }while (0u) + +/*--- WKUP1 ---*/ +#define SetPinFunc_WKUP1(dummy) do{ \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- WKUP2 ---*/ +#define SetPinFunc_WKUP2(dummy) do{ \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- WKUP3 ---*/ +#define SetPinFunc_WKUP3(dummy) do{ \ + bFM_GPIO_PFR6_P0 = 1u; \ + }while (0u) + +/*--- X0 ---*/ +#define SetPinFunc_X0(dummy) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 1u); \ + }while (0u) + +/*--- X0A ---*/ +#define SetPinFunc_X0A(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- X1 ---*/ +#define SetPinFunc_X1(dummy) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 1u); \ + }while (0u) + +/*--- X1A ---*/ +#define SetPinFunc_X1A(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- ZIN0_0 ---*/ +#define SetPinFunc_ZIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 4u, 2u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- ZIN0_2 ---*/ +#define SetPinFunc_ZIN0_2(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 4u, 2u, 3u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- ZIN1_0 ---*/ +#define SetPinFunc_ZIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- ZIN1_2 ---*/ +#define SetPinFunc_ZIN1_2(dummy) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 10u, 2u, 3u ); \ + bFM_GPIO_PFR1_P7 = 1u; \ + }while (0u) + +/*--- ZIN2_0 ---*/ +#define SetPinFunc_ZIN2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- ZIN2_1 ---*/ +#define SetPinFunc_ZIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_P3 = 1u; \ + }while (0u) + +/*--- ZIN3_0 ---*/ +#define SetPinFunc_ZIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ZIN3_1 ---*/ +#define SetPinFunc_ZIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 8u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/****************************************************************************** + ANALOG PINS +*******************************************************************************/ + +/*--- AN00 ---*/ +#define SetPinFunc_AN00(dummy) do{ \ + bFM_GPIO_ADE_AN00=1u; \ + }while (0u) + +/*--- AN01 ---*/ +#define SetPinFunc_AN01(dummy) do{ \ + bFM_GPIO_ADE_AN01=1u; \ + }while (0u) + +/*--- AN02 ---*/ +#define SetPinFunc_AN02(dummy) do{ \ + bFM_GPIO_ADE_AN02=1u; \ + }while (0u) + +/*--- AN03 ---*/ +#define SetPinFunc_AN03(dummy) do{ \ + bFM_GPIO_ADE_AN03=1u; \ + }while (0u) + +/*--- AN04 ---*/ +#define SetPinFunc_AN04(dummy) do{ \ + bFM_GPIO_ADE_AN04=1u; \ + }while (0u) + +/*--- AN05 ---*/ +#define SetPinFunc_AN05(dummy) do{ \ + bFM_GPIO_ADE_AN05=1u; \ + }while (0u) + +/*--- AN06 ---*/ +#define SetPinFunc_AN06(dummy) do{ \ + bFM_GPIO_ADE_AN06=1u; \ + }while (0u) + +/*--- AN07 ---*/ +#define SetPinFunc_AN07(dummy) do{ \ + bFM_GPIO_ADE_AN07=1u; \ + }while (0u) + +/*--- AN08 ---*/ +#define SetPinFunc_AN08(dummy) do{ \ + bFM_GPIO_ADE_AN08=1u; \ + }while (0u) + +/*--- AN09 ---*/ +#define SetPinFunc_AN09(dummy) do{ \ + bFM_GPIO_ADE_AN09=1u; \ + }while (0u) + +/*--- AN10 ---*/ +#define SetPinFunc_AN10(dummy) do{ \ + bFM_GPIO_ADE_AN10=1u; \ + }while (0u) + +/*--- AN11 ---*/ +#define SetPinFunc_AN11(dummy) do{ \ + bFM_GPIO_ADE_AN11=1u; \ + }while (0u) + +/*--- AN12 ---*/ +#define SetPinFunc_AN12(dummy) do{ \ + bFM_GPIO_ADE_AN12=1u; \ + }while (0u) + +/*--- AN13 ---*/ +#define SetPinFunc_AN13(dummy) do{ \ + bFM_GPIO_ADE_AN13=1u; \ + }while (0u) + +/*--- AN14 ---*/ +#define SetPinFunc_AN14(dummy) do{ \ + bFM_GPIO_ADE_AN14=1u; \ + }while (0u) + +/*--- AN15 ---*/ +#define SetPinFunc_AN15(dummy) do{ \ + bFM_GPIO_ADE_AN15=1u; \ + }while (0u) + +/*--- AN24 ---*/ +#define SetPinFunc_AN24(dummy) do{ \ + bFM_GPIO_ADE_AN24=1u; \ + }while (0u) + +/*--- AN25 ---*/ +#define SetPinFunc_AN25(dummy) do{ \ + bFM_GPIO_ADE_AN25=1u; \ + }while (0u) + +/*--- AN26 ---*/ +#define SetPinFunc_AN26(dummy) do{ \ + bFM_GPIO_ADE_AN26=1u; \ + }while (0u) + +/*--- AN27 ---*/ +#define SetPinFunc_AN27(dummy) do{ \ + bFM_GPIO_ADE_AN27=1u; \ + }while (0u) + +/*--- AN28 ---*/ +#define SetPinFunc_AN28(dummy) do{ \ + bFM_GPIO_ADE_AN28=1u; \ + }while (0u) + +/*--- AN29 ---*/ +#define SetPinFunc_AN29(dummy) do{ \ + bFM_GPIO_ADE_AN29=1u; \ + }while (0u) + +/*--- AN30 ---*/ +#define SetPinFunc_AN30(dummy) do{ \ + bFM_GPIO_ADE_AN30=1u; \ + }while (0u) + +/*--- AN31 ---*/ +#define SetPinFunc_AN31(dummy) do{ \ + bFM_GPIO_ADE_AN31=1u; \ + }while (0u) + +#endif // #ifndef __GPIO_S6E2C5XH_H__ + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio_s6e2c5xl.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio_s6e2c5xl.h new file mode 100644 index 0000000000..0a491fdf9a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/gpio/gpio_s6e2c5xl.h @@ -0,0 +1,11362 @@ +/************************************************************************************* +* Copyright (C) 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* +* This software, including source code, documentation and related +* materials ( "Software" ), is owned by Cypress Semiconductor +* Corporation ( "Cypress" ) and is protected by and subject to worldwide +* patent protection (United States and foreign), United States copyright +* laws and international treaty provisions. Therefore, you may use this +* Software only as provided in the license agreement accompanying the +* software package from which you obtained this Software ( "EULA" ). +* If no EULA applies, Cypress hereby grants you a personal, nonexclusive, +* non-transferable license to copy, modify, and compile the +* Software source code solely for use in connection with Cypress's +* integrated circuit products. Any reproduction, modification, translation, +* compilation, or representation of this Software except as specified +* above is prohibited without the express written permission of Cypress. +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE. Cypress reserves the right to make +* changes to the Software without notice. Cypress does not assume any +* liability arising out of the application or use of the Software or any +* product or circuit described in the Software. Cypress does not +* authorize its products for use in any products where a malfunction or +* failure of the Cypress product may reasonably be expected to result in +* significant property damage, injury or death ( "High Risk Product" ). By +* including Cypress's product in a High Risk Product, the manufacturer +* of such system or application assumes all risk of such use and in doing +* so agrees to indemnify Cypress against all liability. +*/ +/************************************************************************************/ +/** \file gpio_s6e2c5xl.h + ** + ** Header file for S6E2C5XL GPIO functions, included in gpio.h + ** + ** History: + ** - 2015-12-04 2.0 NOSU Clean ALL FM Series pin files + ** + ** Timestamp: + ** - 2015-12-16 18:30:36 Auto created by GpioHeaderGenerator Rev 1.0.0 + ** + ******************************************************************************/ + +#ifndef __GPIO_S6E2C5XL_H__ +#define __GPIO_S6E2C5XL_H__ + +#include + +#define PINCONFIG_SET_REG(pinreg,pos,width,value) \ + ((pinreg) = ((pinreg) & ~(((1u<<(width))-1u)<<(pos)) | \ + ((value) << (pos)))) + +/****************************************************************************** + GPIO +*******************************************************************************/ + +/*---- GPIO bit P00 ----*/ +#define GPIO1PIN_P00_GET ( bFM_GPIO_PDIR0_P0 ) + +#define GPIO1PIN_P00_PUT(v) ( bFM_GPIO_PDOR0_P0=(v) ) + +#define GPIO1PIN_P00_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P00_INITIN(v) \ + : GPIO1PIN_P00_INITOUT(v) ) + +#define GPIO1PIN_P00_INITIN(v) do{ \ + bFM_GPIO_PCR0_P0=(v).bPullup; \ + bFM_GPIO_DDR0_P0=0u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +#define GPIO1PIN_P00_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P0=(v).bInitVal; \ + bFM_GPIO_DDR0_P0=1u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +/*---- GPIO bit NP00 ----*/ +#define GPIO1PIN_NP00_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P0)) ) + +#define GPIO1PIN_NP00_PUT(v) ( bFM_GPIO_PDOR0_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP00_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP00_INITIN(v) \ + : GPIO1PIN_NP00_INITOUT(v) ) + +#define GPIO1PIN_NP00_INITIN(v) do{ \ + bFM_GPIO_PCR0_P0=(v).bPullup; \ + bFM_GPIO_DDR0_P0=0u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +#define GPIO1PIN_NP00_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P0=1u; \ + bFM_GPIO_PFR0_P0=0u; }while(0u) + +/*---- GPIO bit P01 ----*/ +#define GPIO1PIN_P01_GET ( bFM_GPIO_PDIR0_P1 ) + +#define GPIO1PIN_P01_PUT(v) ( bFM_GPIO_PDOR0_P1=(v) ) + +#define GPIO1PIN_P01_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P01_INITIN(v) \ + : GPIO1PIN_P01_INITOUT(v) ) + +#define GPIO1PIN_P01_INITIN(v) do{ \ + bFM_GPIO_PCR0_P1=(v).bPullup; \ + bFM_GPIO_DDR0_P1=0u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +#define GPIO1PIN_P01_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P1=(v).bInitVal; \ + bFM_GPIO_DDR0_P1=1u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +/*---- GPIO bit NP01 ----*/ +#define GPIO1PIN_NP01_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P1)) ) + +#define GPIO1PIN_NP01_PUT(v) ( bFM_GPIO_PDOR0_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP01_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP01_INITIN(v) \ + : GPIO1PIN_NP01_INITOUT(v) ) + +#define GPIO1PIN_NP01_INITIN(v) do{ \ + bFM_GPIO_PCR0_P1=(v).bPullup; \ + bFM_GPIO_DDR0_P1=0u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +#define GPIO1PIN_NP01_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P1=1u; \ + bFM_GPIO_PFR0_P1=0u; }while(0u) + +/*---- GPIO bit P02 ----*/ +#define GPIO1PIN_P02_GET ( bFM_GPIO_PDIR0_P2 ) + +#define GPIO1PIN_P02_PUT(v) ( bFM_GPIO_PDOR0_P2=(v) ) + +#define GPIO1PIN_P02_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P02_INITIN(v) \ + : GPIO1PIN_P02_INITOUT(v) ) + +#define GPIO1PIN_P02_INITIN(v) do{ \ + bFM_GPIO_PCR0_P2=(v).bPullup; \ + bFM_GPIO_DDR0_P2=0u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +#define GPIO1PIN_P02_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P2=(v).bInitVal; \ + bFM_GPIO_DDR0_P2=1u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +/*---- GPIO bit NP02 ----*/ +#define GPIO1PIN_NP02_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P2)) ) + +#define GPIO1PIN_NP02_PUT(v) ( bFM_GPIO_PDOR0_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP02_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP02_INITIN(v) \ + : GPIO1PIN_NP02_INITOUT(v) ) + +#define GPIO1PIN_NP02_INITIN(v) do{ \ + bFM_GPIO_PCR0_P2=(v).bPullup; \ + bFM_GPIO_DDR0_P2=0u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +#define GPIO1PIN_NP02_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P2=1u; \ + bFM_GPIO_PFR0_P2=0u; }while(0u) + +/*---- GPIO bit P03 ----*/ +#define GPIO1PIN_P03_GET ( bFM_GPIO_PDIR0_P3 ) + +#define GPIO1PIN_P03_PUT(v) ( bFM_GPIO_PDOR0_P3=(v) ) + +#define GPIO1PIN_P03_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P03_INITIN(v) \ + : GPIO1PIN_P03_INITOUT(v) ) + +#define GPIO1PIN_P03_INITIN(v) do{ \ + bFM_GPIO_PCR0_P3=(v).bPullup; \ + bFM_GPIO_DDR0_P3=0u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +#define GPIO1PIN_P03_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P3=(v).bInitVal; \ + bFM_GPIO_DDR0_P3=1u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +/*---- GPIO bit NP03 ----*/ +#define GPIO1PIN_NP03_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P3)) ) + +#define GPIO1PIN_NP03_PUT(v) ( bFM_GPIO_PDOR0_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP03_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP03_INITIN(v) \ + : GPIO1PIN_NP03_INITOUT(v) ) + +#define GPIO1PIN_NP03_INITIN(v) do{ \ + bFM_GPIO_PCR0_P3=(v).bPullup; \ + bFM_GPIO_DDR0_P3=0u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +#define GPIO1PIN_NP03_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P3=1u; \ + bFM_GPIO_PFR0_P3=0u; }while(0u) + +/*---- GPIO bit P04 ----*/ +#define GPIO1PIN_P04_GET ( bFM_GPIO_PDIR0_P4 ) + +#define GPIO1PIN_P04_PUT(v) ( bFM_GPIO_PDOR0_P4=(v) ) + +#define GPIO1PIN_P04_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P04_INITIN(v) \ + : GPIO1PIN_P04_INITOUT(v) ) + +#define GPIO1PIN_P04_INITIN(v) do{ \ + bFM_GPIO_PCR0_P4=(v).bPullup; \ + bFM_GPIO_DDR0_P4=0u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +#define GPIO1PIN_P04_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P4=(v).bInitVal; \ + bFM_GPIO_DDR0_P4=1u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +/*---- GPIO bit NP04 ----*/ +#define GPIO1PIN_NP04_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P4)) ) + +#define GPIO1PIN_NP04_PUT(v) ( bFM_GPIO_PDOR0_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP04_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP04_INITIN(v) \ + : GPIO1PIN_NP04_INITOUT(v) ) + +#define GPIO1PIN_NP04_INITIN(v) do{ \ + bFM_GPIO_PCR0_P4=(v).bPullup; \ + bFM_GPIO_DDR0_P4=0u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +#define GPIO1PIN_NP04_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P4=1u; \ + bFM_GPIO_PFR0_P4=0u; }while(0u) + +/*---- GPIO bit P08 ----*/ +#define GPIO1PIN_P08_GET ( bFM_GPIO_PDIR0_P8 ) + +#define GPIO1PIN_P08_PUT(v) ( bFM_GPIO_PDOR0_P8=(v) ) + +#define GPIO1PIN_P08_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P08_INITIN(v) \ + : GPIO1PIN_P08_INITOUT(v) ) + +#define GPIO1PIN_P08_INITIN(v) do{ \ + bFM_GPIO_PCR0_P8=(v).bPullup; \ + bFM_GPIO_DDR0_P8=0u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +#define GPIO1PIN_P08_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P8=(v).bInitVal; \ + bFM_GPIO_DDR0_P8=1u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +/*---- GPIO bit NP08 ----*/ +#define GPIO1PIN_NP08_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P8)) ) + +#define GPIO1PIN_NP08_PUT(v) ( bFM_GPIO_PDOR0_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP08_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP08_INITIN(v) \ + : GPIO1PIN_NP08_INITOUT(v) ) + +#define GPIO1PIN_NP08_INITIN(v) do{ \ + bFM_GPIO_PCR0_P8=(v).bPullup; \ + bFM_GPIO_DDR0_P8=0u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +#define GPIO1PIN_NP08_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P8=1u; \ + bFM_GPIO_PFR0_P8=0u; }while(0u) + +/*---- GPIO bit P09 ----*/ +#define GPIO1PIN_P09_GET ( bFM_GPIO_PDIR0_P9 ) + +#define GPIO1PIN_P09_PUT(v) ( bFM_GPIO_PDOR0_P9=(v) ) + +#define GPIO1PIN_P09_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P09_INITIN(v) \ + : GPIO1PIN_P09_INITOUT(v) ) + +#define GPIO1PIN_P09_INITIN(v) do{ \ + bFM_GPIO_PCR0_P9=(v).bPullup; \ + bFM_GPIO_DDR0_P9=0u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +#define GPIO1PIN_P09_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P9=(v).bInitVal; \ + bFM_GPIO_DDR0_P9=1u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +/*---- GPIO bit NP09 ----*/ +#define GPIO1PIN_NP09_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_P9)) ) + +#define GPIO1PIN_NP09_PUT(v) ( bFM_GPIO_PDOR0_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP09_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP09_INITIN(v) \ + : GPIO1PIN_NP09_INITOUT(v) ) + +#define GPIO1PIN_NP09_INITIN(v) do{ \ + bFM_GPIO_PCR0_P9=(v).bPullup; \ + bFM_GPIO_DDR0_P9=0u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +#define GPIO1PIN_NP09_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_P9=1u; \ + bFM_GPIO_PFR0_P9=0u; }while(0u) + +/*---- GPIO bit P0A ----*/ +#define GPIO1PIN_P0A_GET ( bFM_GPIO_PDIR0_PA ) + +#define GPIO1PIN_P0A_PUT(v) ( bFM_GPIO_PDOR0_PA=(v) ) + +#define GPIO1PIN_P0A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P0A_INITIN(v) \ + : GPIO1PIN_P0A_INITOUT(v) ) + +#define GPIO1PIN_P0A_INITIN(v) do{ \ + bFM_GPIO_PCR0_PA=(v).bPullup; \ + bFM_GPIO_DDR0_PA=0u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +#define GPIO1PIN_P0A_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_PA=(v).bInitVal; \ + bFM_GPIO_DDR0_PA=1u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +/*---- GPIO bit NP0A ----*/ +#define GPIO1PIN_NP0A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR0_PA)) ) + +#define GPIO1PIN_NP0A_PUT(v) ( bFM_GPIO_PDOR0_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP0A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP0A_INITIN(v) \ + : GPIO1PIN_NP0A_INITOUT(v) ) + +#define GPIO1PIN_NP0A_INITIN(v) do{ \ + bFM_GPIO_PCR0_PA=(v).bPullup; \ + bFM_GPIO_DDR0_PA=0u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +#define GPIO1PIN_NP0A_INITOUT(v) do{ \ + bFM_GPIO_PDOR0_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR0_PA=1u; \ + bFM_GPIO_PFR0_PA=0u; }while(0u) + +/*---- GPIO bit P10 ----*/ +#define GPIO1PIN_P10_GET ( bFM_GPIO_PDIR1_P0 ) + +#define GPIO1PIN_P10_PUT(v) ( bFM_GPIO_PDOR1_P0=(v) ) + +#define GPIO1PIN_P10_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P10_INITIN(v) \ + : GPIO1PIN_P10_INITOUT(v) ) + +#define GPIO1PIN_P10_INITIN(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PCR1_P0=(v).bPullup; \ + bFM_GPIO_DDR1_P0=0u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +#define GPIO1PIN_P10_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PDOR1_P0=(v).bInitVal; \ + bFM_GPIO_DDR1_P0=1u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +/*---- GPIO bit NP10 ----*/ +#define GPIO1PIN_NP10_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P0)) ) + +#define GPIO1PIN_NP10_PUT(v) ( bFM_GPIO_PDOR1_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP10_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP10_INITIN(v) \ + : GPIO1PIN_NP10_INITOUT(v) ) + +#define GPIO1PIN_NP10_INITIN(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PCR1_P0=(v).bPullup; \ + bFM_GPIO_DDR1_P0=0u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +#define GPIO1PIN_NP10_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + bFM_GPIO_PDOR1_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P0=1u; \ + bFM_GPIO_PFR1_P0=0u; }while(0u) + +/*---- GPIO bit P11 ----*/ +#define GPIO1PIN_P11_GET ( bFM_GPIO_PDIR1_P1 ) + +#define GPIO1PIN_P11_PUT(v) ( bFM_GPIO_PDOR1_P1=(v) ) + +#define GPIO1PIN_P11_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P11_INITIN(v) \ + : GPIO1PIN_P11_INITOUT(v) ) + +#define GPIO1PIN_P11_INITIN(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PCR1_P1=(v).bPullup; \ + bFM_GPIO_DDR1_P1=0u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +#define GPIO1PIN_P11_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PDOR1_P1=(v).bInitVal; \ + bFM_GPIO_DDR1_P1=1u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +/*---- GPIO bit NP11 ----*/ +#define GPIO1PIN_NP11_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P1)) ) + +#define GPIO1PIN_NP11_PUT(v) ( bFM_GPIO_PDOR1_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP11_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP11_INITIN(v) \ + : GPIO1PIN_NP11_INITOUT(v) ) + +#define GPIO1PIN_NP11_INITIN(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PCR1_P1=(v).bPullup; \ + bFM_GPIO_DDR1_P1=0u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +#define GPIO1PIN_NP11_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + bFM_GPIO_PDOR1_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P1=1u; \ + bFM_GPIO_PFR1_P1=0u; }while(0u) + +/*---- GPIO bit P12 ----*/ +#define GPIO1PIN_P12_GET ( bFM_GPIO_PDIR1_P2 ) + +#define GPIO1PIN_P12_PUT(v) ( bFM_GPIO_PDOR1_P2=(v) ) + +#define GPIO1PIN_P12_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P12_INITIN(v) \ + : GPIO1PIN_P12_INITOUT(v) ) + +#define GPIO1PIN_P12_INITIN(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PCR1_P2=(v).bPullup; \ + bFM_GPIO_DDR1_P2=0u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +#define GPIO1PIN_P12_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PDOR1_P2=(v).bInitVal; \ + bFM_GPIO_DDR1_P2=1u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +/*---- GPIO bit NP12 ----*/ +#define GPIO1PIN_NP12_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P2)) ) + +#define GPIO1PIN_NP12_PUT(v) ( bFM_GPIO_PDOR1_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP12_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP12_INITIN(v) \ + : GPIO1PIN_NP12_INITOUT(v) ) + +#define GPIO1PIN_NP12_INITIN(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PCR1_P2=(v).bPullup; \ + bFM_GPIO_DDR1_P2=0u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +#define GPIO1PIN_NP12_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + bFM_GPIO_PDOR1_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P2=1u; \ + bFM_GPIO_PFR1_P2=0u; }while(0u) + +/*---- GPIO bit P13 ----*/ +#define GPIO1PIN_P13_GET ( bFM_GPIO_PDIR1_P3 ) + +#define GPIO1PIN_P13_PUT(v) ( bFM_GPIO_PDOR1_P3=(v) ) + +#define GPIO1PIN_P13_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P13_INITIN(v) \ + : GPIO1PIN_P13_INITOUT(v) ) + +#define GPIO1PIN_P13_INITIN(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PCR1_P3=(v).bPullup; \ + bFM_GPIO_DDR1_P3=0u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +#define GPIO1PIN_P13_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PDOR1_P3=(v).bInitVal; \ + bFM_GPIO_DDR1_P3=1u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +/*---- GPIO bit NP13 ----*/ +#define GPIO1PIN_NP13_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P3)) ) + +#define GPIO1PIN_NP13_PUT(v) ( bFM_GPIO_PDOR1_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP13_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP13_INITIN(v) \ + : GPIO1PIN_NP13_INITOUT(v) ) + +#define GPIO1PIN_NP13_INITIN(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PCR1_P3=(v).bPullup; \ + bFM_GPIO_DDR1_P3=0u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +#define GPIO1PIN_NP13_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + bFM_GPIO_PDOR1_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P3=1u; \ + bFM_GPIO_PFR1_P3=0u; }while(0u) + +/*---- GPIO bit P14 ----*/ +#define GPIO1PIN_P14_GET ( bFM_GPIO_PDIR1_P4 ) + +#define GPIO1PIN_P14_PUT(v) ( bFM_GPIO_PDOR1_P4=(v) ) + +#define GPIO1PIN_P14_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P14_INITIN(v) \ + : GPIO1PIN_P14_INITOUT(v) ) + +#define GPIO1PIN_P14_INITIN(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PCR1_P4=(v).bPullup; \ + bFM_GPIO_DDR1_P4=0u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +#define GPIO1PIN_P14_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PDOR1_P4=(v).bInitVal; \ + bFM_GPIO_DDR1_P4=1u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +/*---- GPIO bit NP14 ----*/ +#define GPIO1PIN_NP14_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P4)) ) + +#define GPIO1PIN_NP14_PUT(v) ( bFM_GPIO_PDOR1_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP14_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP14_INITIN(v) \ + : GPIO1PIN_NP14_INITOUT(v) ) + +#define GPIO1PIN_NP14_INITIN(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PCR1_P4=(v).bPullup; \ + bFM_GPIO_DDR1_P4=0u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +#define GPIO1PIN_NP14_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + bFM_GPIO_PDOR1_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P4=1u; \ + bFM_GPIO_PFR1_P4=0u; }while(0u) + +/*---- GPIO bit P15 ----*/ +#define GPIO1PIN_P15_GET ( bFM_GPIO_PDIR1_P5 ) + +#define GPIO1PIN_P15_PUT(v) ( bFM_GPIO_PDOR1_P5=(v) ) + +#define GPIO1PIN_P15_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P15_INITIN(v) \ + : GPIO1PIN_P15_INITOUT(v) ) + +#define GPIO1PIN_P15_INITIN(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PCR1_P5=(v).bPullup; \ + bFM_GPIO_DDR1_P5=0u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +#define GPIO1PIN_P15_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PDOR1_P5=(v).bInitVal; \ + bFM_GPIO_DDR1_P5=1u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +/*---- GPIO bit NP15 ----*/ +#define GPIO1PIN_NP15_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P5)) ) + +#define GPIO1PIN_NP15_PUT(v) ( bFM_GPIO_PDOR1_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP15_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP15_INITIN(v) \ + : GPIO1PIN_NP15_INITOUT(v) ) + +#define GPIO1PIN_NP15_INITIN(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PCR1_P5=(v).bPullup; \ + bFM_GPIO_DDR1_P5=0u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +#define GPIO1PIN_NP15_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + bFM_GPIO_PDOR1_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P5=1u; \ + bFM_GPIO_PFR1_P5=0u; }while(0u) + +/*---- GPIO bit P16 ----*/ +#define GPIO1PIN_P16_GET ( bFM_GPIO_PDIR1_P6 ) + +#define GPIO1PIN_P16_PUT(v) ( bFM_GPIO_PDOR1_P6=(v) ) + +#define GPIO1PIN_P16_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P16_INITIN(v) \ + : GPIO1PIN_P16_INITOUT(v) ) + +#define GPIO1PIN_P16_INITIN(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PCR1_P6=(v).bPullup; \ + bFM_GPIO_DDR1_P6=0u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +#define GPIO1PIN_P16_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PDOR1_P6=(v).bInitVal; \ + bFM_GPIO_DDR1_P6=1u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +/*---- GPIO bit NP16 ----*/ +#define GPIO1PIN_NP16_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P6)) ) + +#define GPIO1PIN_NP16_PUT(v) ( bFM_GPIO_PDOR1_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP16_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP16_INITIN(v) \ + : GPIO1PIN_NP16_INITOUT(v) ) + +#define GPIO1PIN_NP16_INITIN(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PCR1_P6=(v).bPullup; \ + bFM_GPIO_DDR1_P6=0u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +#define GPIO1PIN_NP16_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + bFM_GPIO_PDOR1_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P6=1u; \ + bFM_GPIO_PFR1_P6=0u; }while(0u) + +/*---- GPIO bit P17 ----*/ +#define GPIO1PIN_P17_GET ( bFM_GPIO_PDIR1_P7 ) + +#define GPIO1PIN_P17_PUT(v) ( bFM_GPIO_PDOR1_P7=(v) ) + +#define GPIO1PIN_P17_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P17_INITIN(v) \ + : GPIO1PIN_P17_INITOUT(v) ) + +#define GPIO1PIN_P17_INITIN(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PCR1_P7=(v).bPullup; \ + bFM_GPIO_DDR1_P7=0u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +#define GPIO1PIN_P17_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PDOR1_P7=(v).bInitVal; \ + bFM_GPIO_DDR1_P7=1u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +/*---- GPIO bit NP17 ----*/ +#define GPIO1PIN_NP17_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P7)) ) + +#define GPIO1PIN_NP17_PUT(v) ( bFM_GPIO_PDOR1_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP17_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP17_INITIN(v) \ + : GPIO1PIN_NP17_INITOUT(v) ) + +#define GPIO1PIN_NP17_INITIN(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PCR1_P7=(v).bPullup; \ + bFM_GPIO_DDR1_P7=0u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +#define GPIO1PIN_NP17_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + bFM_GPIO_PDOR1_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P7=1u; \ + bFM_GPIO_PFR1_P7=0u; }while(0u) + +/*---- GPIO bit P18 ----*/ +#define GPIO1PIN_P18_GET ( bFM_GPIO_PDIR1_P8 ) + +#define GPIO1PIN_P18_PUT(v) ( bFM_GPIO_PDOR1_P8=(v) ) + +#define GPIO1PIN_P18_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P18_INITIN(v) \ + : GPIO1PIN_P18_INITOUT(v) ) + +#define GPIO1PIN_P18_INITIN(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PCR1_P8=(v).bPullup; \ + bFM_GPIO_DDR1_P8=0u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +#define GPIO1PIN_P18_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PDOR1_P8=(v).bInitVal; \ + bFM_GPIO_DDR1_P8=1u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +/*---- GPIO bit NP18 ----*/ +#define GPIO1PIN_NP18_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P8)) ) + +#define GPIO1PIN_NP18_PUT(v) ( bFM_GPIO_PDOR1_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP18_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP18_INITIN(v) \ + : GPIO1PIN_NP18_INITOUT(v) ) + +#define GPIO1PIN_NP18_INITIN(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PCR1_P8=(v).bPullup; \ + bFM_GPIO_DDR1_P8=0u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +#define GPIO1PIN_NP18_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + bFM_GPIO_PDOR1_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P8=1u; \ + bFM_GPIO_PFR1_P8=0u; }while(0u) + +/*---- GPIO bit P19 ----*/ +#define GPIO1PIN_P19_GET ( bFM_GPIO_PDIR1_P9 ) + +#define GPIO1PIN_P19_PUT(v) ( bFM_GPIO_PDOR1_P9=(v) ) + +#define GPIO1PIN_P19_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P19_INITIN(v) \ + : GPIO1PIN_P19_INITOUT(v) ) + +#define GPIO1PIN_P19_INITIN(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PCR1_P9=(v).bPullup; \ + bFM_GPIO_DDR1_P9=0u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +#define GPIO1PIN_P19_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PDOR1_P9=(v).bInitVal; \ + bFM_GPIO_DDR1_P9=1u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +/*---- GPIO bit NP19 ----*/ +#define GPIO1PIN_NP19_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_P9)) ) + +#define GPIO1PIN_NP19_PUT(v) ( bFM_GPIO_PDOR1_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP19_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP19_INITIN(v) \ + : GPIO1PIN_NP19_INITOUT(v) ) + +#define GPIO1PIN_NP19_INITIN(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PCR1_P9=(v).bPullup; \ + bFM_GPIO_DDR1_P9=0u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +#define GPIO1PIN_NP19_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + bFM_GPIO_PDOR1_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_P9=1u; \ + bFM_GPIO_PFR1_P9=0u; }while(0u) + +/*---- GPIO bit P1A ----*/ +#define GPIO1PIN_P1A_GET ( bFM_GPIO_PDIR1_PA ) + +#define GPIO1PIN_P1A_PUT(v) ( bFM_GPIO_PDOR1_PA=(v) ) + +#define GPIO1PIN_P1A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1A_INITIN(v) \ + : GPIO1PIN_P1A_INITOUT(v) ) + +#define GPIO1PIN_P1A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PCR1_PA=(v).bPullup; \ + bFM_GPIO_DDR1_PA=0u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +#define GPIO1PIN_P1A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PDOR1_PA=(v).bInitVal; \ + bFM_GPIO_DDR1_PA=1u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +/*---- GPIO bit NP1A ----*/ +#define GPIO1PIN_NP1A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PA)) ) + +#define GPIO1PIN_NP1A_PUT(v) ( bFM_GPIO_PDOR1_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1A_INITIN(v) \ + : GPIO1PIN_NP1A_INITOUT(v) ) + +#define GPIO1PIN_NP1A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PCR1_PA=(v).bPullup; \ + bFM_GPIO_DDR1_PA=0u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +#define GPIO1PIN_NP1A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + bFM_GPIO_PDOR1_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PA=1u; \ + bFM_GPIO_PFR1_PA=0u; }while(0u) + +/*---- GPIO bit P1B ----*/ +#define GPIO1PIN_P1B_GET ( bFM_GPIO_PDIR1_PB ) + +#define GPIO1PIN_P1B_PUT(v) ( bFM_GPIO_PDOR1_PB=(v) ) + +#define GPIO1PIN_P1B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1B_INITIN(v) \ + : GPIO1PIN_P1B_INITOUT(v) ) + +#define GPIO1PIN_P1B_INITIN(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PCR1_PB=(v).bPullup; \ + bFM_GPIO_DDR1_PB=0u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +#define GPIO1PIN_P1B_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PDOR1_PB=(v).bInitVal; \ + bFM_GPIO_DDR1_PB=1u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +/*---- GPIO bit NP1B ----*/ +#define GPIO1PIN_NP1B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PB)) ) + +#define GPIO1PIN_NP1B_PUT(v) ( bFM_GPIO_PDOR1_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1B_INITIN(v) \ + : GPIO1PIN_NP1B_INITOUT(v) ) + +#define GPIO1PIN_NP1B_INITIN(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PCR1_PB=(v).bPullup; \ + bFM_GPIO_DDR1_PB=0u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +#define GPIO1PIN_NP1B_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + bFM_GPIO_PDOR1_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PB=1u; \ + bFM_GPIO_PFR1_PB=0u; }while(0u) + +/*---- GPIO bit P1C ----*/ +#define GPIO1PIN_P1C_GET ( bFM_GPIO_PDIR1_PC ) + +#define GPIO1PIN_P1C_PUT(v) ( bFM_GPIO_PDOR1_PC=(v) ) + +#define GPIO1PIN_P1C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1C_INITIN(v) \ + : GPIO1PIN_P1C_INITOUT(v) ) + +#define GPIO1PIN_P1C_INITIN(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PCR1_PC=(v).bPullup; \ + bFM_GPIO_DDR1_PC=0u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +#define GPIO1PIN_P1C_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PDOR1_PC=(v).bInitVal; \ + bFM_GPIO_DDR1_PC=1u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +/*---- GPIO bit NP1C ----*/ +#define GPIO1PIN_NP1C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PC)) ) + +#define GPIO1PIN_NP1C_PUT(v) ( bFM_GPIO_PDOR1_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1C_INITIN(v) \ + : GPIO1PIN_NP1C_INITOUT(v) ) + +#define GPIO1PIN_NP1C_INITIN(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PCR1_PC=(v).bPullup; \ + bFM_GPIO_DDR1_PC=0u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +#define GPIO1PIN_NP1C_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + bFM_GPIO_PDOR1_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PC=1u; \ + bFM_GPIO_PFR1_PC=0u; }while(0u) + +/*---- GPIO bit P1D ----*/ +#define GPIO1PIN_P1D_GET ( bFM_GPIO_PDIR1_PD ) + +#define GPIO1PIN_P1D_PUT(v) ( bFM_GPIO_PDOR1_PD=(v) ) + +#define GPIO1PIN_P1D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1D_INITIN(v) \ + : GPIO1PIN_P1D_INITOUT(v) ) + +#define GPIO1PIN_P1D_INITIN(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PCR1_PD=(v).bPullup; \ + bFM_GPIO_DDR1_PD=0u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +#define GPIO1PIN_P1D_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PDOR1_PD=(v).bInitVal; \ + bFM_GPIO_DDR1_PD=1u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +/*---- GPIO bit NP1D ----*/ +#define GPIO1PIN_NP1D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PD)) ) + +#define GPIO1PIN_NP1D_PUT(v) ( bFM_GPIO_PDOR1_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1D_INITIN(v) \ + : GPIO1PIN_NP1D_INITOUT(v) ) + +#define GPIO1PIN_NP1D_INITIN(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PCR1_PD=(v).bPullup; \ + bFM_GPIO_DDR1_PD=0u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +#define GPIO1PIN_NP1D_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + bFM_GPIO_PDOR1_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PD=1u; \ + bFM_GPIO_PFR1_PD=0u; }while(0u) + +/*---- GPIO bit P1E ----*/ +#define GPIO1PIN_P1E_GET ( bFM_GPIO_PDIR1_PE ) + +#define GPIO1PIN_P1E_PUT(v) ( bFM_GPIO_PDOR1_PE=(v) ) + +#define GPIO1PIN_P1E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1E_INITIN(v) \ + : GPIO1PIN_P1E_INITOUT(v) ) + +#define GPIO1PIN_P1E_INITIN(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PCR1_PE=(v).bPullup; \ + bFM_GPIO_DDR1_PE=0u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +#define GPIO1PIN_P1E_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PDOR1_PE=(v).bInitVal; \ + bFM_GPIO_DDR1_PE=1u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +/*---- GPIO bit NP1E ----*/ +#define GPIO1PIN_NP1E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PE)) ) + +#define GPIO1PIN_NP1E_PUT(v) ( bFM_GPIO_PDOR1_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1E_INITIN(v) \ + : GPIO1PIN_NP1E_INITOUT(v) ) + +#define GPIO1PIN_NP1E_INITIN(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PCR1_PE=(v).bPullup; \ + bFM_GPIO_DDR1_PE=0u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +#define GPIO1PIN_NP1E_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + bFM_GPIO_PDOR1_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PE=1u; \ + bFM_GPIO_PFR1_PE=0u; }while(0u) + +/*---- GPIO bit P1F ----*/ +#define GPIO1PIN_P1F_GET ( bFM_GPIO_PDIR1_PF ) + +#define GPIO1PIN_P1F_PUT(v) ( bFM_GPIO_PDOR1_PF=(v) ) + +#define GPIO1PIN_P1F_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P1F_INITIN(v) \ + : GPIO1PIN_P1F_INITOUT(v) ) + +#define GPIO1PIN_P1F_INITIN(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PCR1_PF=(v).bPullup; \ + bFM_GPIO_DDR1_PF=0u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +#define GPIO1PIN_P1F_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PDOR1_PF=(v).bInitVal; \ + bFM_GPIO_DDR1_PF=1u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +/*---- GPIO bit NP1F ----*/ +#define GPIO1PIN_NP1F_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR1_PF)) ) + +#define GPIO1PIN_NP1F_PUT(v) ( bFM_GPIO_PDOR1_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP1F_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP1F_INITIN(v) \ + : GPIO1PIN_NP1F_INITOUT(v) ) + +#define GPIO1PIN_NP1F_INITIN(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PCR1_PF=(v).bPullup; \ + bFM_GPIO_DDR1_PF=0u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +#define GPIO1PIN_NP1F_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + bFM_GPIO_PDOR1_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR1_PF=1u; \ + bFM_GPIO_PFR1_PF=0u; }while(0u) + +/*---- GPIO bit P20 ----*/ +#define GPIO1PIN_P20_GET ( bFM_GPIO_PDIR2_P0 ) + +#define GPIO1PIN_P20_PUT(v) ( bFM_GPIO_PDOR2_P0=(v) ) + +#define GPIO1PIN_P20_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P20_INITIN(v) \ + : GPIO1PIN_P20_INITOUT(v) ) + +#define GPIO1PIN_P20_INITIN(v) do{ \ + bFM_GPIO_PCR2_P0=(v).bPullup; \ + bFM_GPIO_DDR2_P0=0u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +#define GPIO1PIN_P20_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P0=(v).bInitVal; \ + bFM_GPIO_DDR2_P0=1u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +/*---- GPIO bit NP20 ----*/ +#define GPIO1PIN_NP20_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P0)) ) + +#define GPIO1PIN_NP20_PUT(v) ( bFM_GPIO_PDOR2_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP20_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP20_INITIN(v) \ + : GPIO1PIN_NP20_INITOUT(v) ) + +#define GPIO1PIN_NP20_INITIN(v) do{ \ + bFM_GPIO_PCR2_P0=(v).bPullup; \ + bFM_GPIO_DDR2_P0=0u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +#define GPIO1PIN_NP20_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P0=1u; \ + bFM_GPIO_PFR2_P0=0u; }while(0u) + +/*---- GPIO bit P21 ----*/ +#define GPIO1PIN_P21_GET ( bFM_GPIO_PDIR2_P1 ) + +#define GPIO1PIN_P21_PUT(v) ( bFM_GPIO_PDOR2_P1=(v) ) + +#define GPIO1PIN_P21_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P21_INITIN(v) \ + : GPIO1PIN_P21_INITOUT(v) ) + +#define GPIO1PIN_P21_INITIN(v) do{ \ + bFM_GPIO_PCR2_P1=(v).bPullup; \ + bFM_GPIO_DDR2_P1=0u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +#define GPIO1PIN_P21_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P1=(v).bInitVal; \ + bFM_GPIO_DDR2_P1=1u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +/*---- GPIO bit NP21 ----*/ +#define GPIO1PIN_NP21_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P1)) ) + +#define GPIO1PIN_NP21_PUT(v) ( bFM_GPIO_PDOR2_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP21_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP21_INITIN(v) \ + : GPIO1PIN_NP21_INITOUT(v) ) + +#define GPIO1PIN_NP21_INITIN(v) do{ \ + bFM_GPIO_PCR2_P1=(v).bPullup; \ + bFM_GPIO_DDR2_P1=0u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +#define GPIO1PIN_NP21_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P1=1u; \ + bFM_GPIO_PFR2_P1=0u; }while(0u) + +/*---- GPIO bit P22 ----*/ +#define GPIO1PIN_P22_GET ( bFM_GPIO_PDIR2_P2 ) + +#define GPIO1PIN_P22_PUT(v) ( bFM_GPIO_PDOR2_P2=(v) ) + +#define GPIO1PIN_P22_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P22_INITIN(v) \ + : GPIO1PIN_P22_INITOUT(v) ) + +#define GPIO1PIN_P22_INITIN(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PCR2_P2=(v).bPullup; \ + bFM_GPIO_DDR2_P2=0u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +#define GPIO1PIN_P22_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PDOR2_P2=(v).bInitVal; \ + bFM_GPIO_DDR2_P2=1u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +/*---- GPIO bit NP22 ----*/ +#define GPIO1PIN_NP22_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P2)) ) + +#define GPIO1PIN_NP22_PUT(v) ( bFM_GPIO_PDOR2_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP22_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP22_INITIN(v) \ + : GPIO1PIN_NP22_INITOUT(v) ) + +#define GPIO1PIN_NP22_INITIN(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PCR2_P2=(v).bPullup; \ + bFM_GPIO_DDR2_P2=0u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +#define GPIO1PIN_NP22_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + bFM_GPIO_PDOR2_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P2=1u; \ + bFM_GPIO_PFR2_P2=0u; }while(0u) + +/*---- GPIO bit P23 ----*/ +#define GPIO1PIN_P23_GET ( bFM_GPIO_PDIR2_P3 ) + +#define GPIO1PIN_P23_PUT(v) ( bFM_GPIO_PDOR2_P3=(v) ) + +#define GPIO1PIN_P23_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P23_INITIN(v) \ + : GPIO1PIN_P23_INITOUT(v) ) + +#define GPIO1PIN_P23_INITIN(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PCR2_P3=(v).bPullup; \ + bFM_GPIO_DDR2_P3=0u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +#define GPIO1PIN_P23_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PDOR2_P3=(v).bInitVal; \ + bFM_GPIO_DDR2_P3=1u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +/*---- GPIO bit NP23 ----*/ +#define GPIO1PIN_NP23_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P3)) ) + +#define GPIO1PIN_NP23_PUT(v) ( bFM_GPIO_PDOR2_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP23_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP23_INITIN(v) \ + : GPIO1PIN_NP23_INITOUT(v) ) + +#define GPIO1PIN_NP23_INITIN(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PCR2_P3=(v).bPullup; \ + bFM_GPIO_DDR2_P3=0u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +#define GPIO1PIN_NP23_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + bFM_GPIO_PDOR2_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P3=1u; \ + bFM_GPIO_PFR2_P3=0u; }while(0u) + +/*---- GPIO bit P24 ----*/ +#define GPIO1PIN_P24_GET ( bFM_GPIO_PDIR2_P4 ) + +#define GPIO1PIN_P24_PUT(v) ( bFM_GPIO_PDOR2_P4=(v) ) + +#define GPIO1PIN_P24_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P24_INITIN(v) \ + : GPIO1PIN_P24_INITOUT(v) ) + +#define GPIO1PIN_P24_INITIN(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PCR2_P4=(v).bPullup; \ + bFM_GPIO_DDR2_P4=0u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +#define GPIO1PIN_P24_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PDOR2_P4=(v).bInitVal; \ + bFM_GPIO_DDR2_P4=1u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +/*---- GPIO bit NP24 ----*/ +#define GPIO1PIN_NP24_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P4)) ) + +#define GPIO1PIN_NP24_PUT(v) ( bFM_GPIO_PDOR2_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP24_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP24_INITIN(v) \ + : GPIO1PIN_NP24_INITOUT(v) ) + +#define GPIO1PIN_NP24_INITIN(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PCR2_P4=(v).bPullup; \ + bFM_GPIO_DDR2_P4=0u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +#define GPIO1PIN_NP24_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + bFM_GPIO_PDOR2_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P4=1u; \ + bFM_GPIO_PFR2_P4=0u; }while(0u) + +/*---- GPIO bit P25 ----*/ +#define GPIO1PIN_P25_GET ( bFM_GPIO_PDIR2_P5 ) + +#define GPIO1PIN_P25_PUT(v) ( bFM_GPIO_PDOR2_P5=(v) ) + +#define GPIO1PIN_P25_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P25_INITIN(v) \ + : GPIO1PIN_P25_INITOUT(v) ) + +#define GPIO1PIN_P25_INITIN(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PCR2_P5=(v).bPullup; \ + bFM_GPIO_DDR2_P5=0u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +#define GPIO1PIN_P25_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PDOR2_P5=(v).bInitVal; \ + bFM_GPIO_DDR2_P5=1u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +/*---- GPIO bit NP25 ----*/ +#define GPIO1PIN_NP25_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P5)) ) + +#define GPIO1PIN_NP25_PUT(v) ( bFM_GPIO_PDOR2_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP25_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP25_INITIN(v) \ + : GPIO1PIN_NP25_INITOUT(v) ) + +#define GPIO1PIN_NP25_INITIN(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PCR2_P5=(v).bPullup; \ + bFM_GPIO_DDR2_P5=0u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +#define GPIO1PIN_NP25_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + bFM_GPIO_PDOR2_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P5=1u; \ + bFM_GPIO_PFR2_P5=0u; }while(0u) + +/*---- GPIO bit P26 ----*/ +#define GPIO1PIN_P26_GET ( bFM_GPIO_PDIR2_P6 ) + +#define GPIO1PIN_P26_PUT(v) ( bFM_GPIO_PDOR2_P6=(v) ) + +#define GPIO1PIN_P26_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P26_INITIN(v) \ + : GPIO1PIN_P26_INITOUT(v) ) + +#define GPIO1PIN_P26_INITIN(v) do{ \ + bFM_GPIO_PCR2_P6=(v).bPullup; \ + bFM_GPIO_DDR2_P6=0u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +#define GPIO1PIN_P26_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P6=(v).bInitVal; \ + bFM_GPIO_DDR2_P6=1u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +/*---- GPIO bit NP26 ----*/ +#define GPIO1PIN_NP26_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P6)) ) + +#define GPIO1PIN_NP26_PUT(v) ( bFM_GPIO_PDOR2_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP26_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP26_INITIN(v) \ + : GPIO1PIN_NP26_INITOUT(v) ) + +#define GPIO1PIN_NP26_INITIN(v) do{ \ + bFM_GPIO_PCR2_P6=(v).bPullup; \ + bFM_GPIO_DDR2_P6=0u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +#define GPIO1PIN_NP26_INITOUT(v) do{ \ + bFM_GPIO_PDOR2_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P6=1u; \ + bFM_GPIO_PFR2_P6=0u; }while(0u) + +/*---- GPIO bit P27 ----*/ +#define GPIO1PIN_P27_GET ( bFM_GPIO_PDIR2_P7 ) + +#define GPIO1PIN_P27_PUT(v) ( bFM_GPIO_PDOR2_P7=(v) ) + +#define GPIO1PIN_P27_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P27_INITIN(v) \ + : GPIO1PIN_P27_INITOUT(v) ) + +#define GPIO1PIN_P27_INITIN(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PCR2_P7=(v).bPullup; \ + bFM_GPIO_DDR2_P7=0u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +#define GPIO1PIN_P27_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PDOR2_P7=(v).bInitVal; \ + bFM_GPIO_DDR2_P7=1u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +/*---- GPIO bit NP27 ----*/ +#define GPIO1PIN_NP27_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P7)) ) + +#define GPIO1PIN_NP27_PUT(v) ( bFM_GPIO_PDOR2_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP27_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP27_INITIN(v) \ + : GPIO1PIN_NP27_INITOUT(v) ) + +#define GPIO1PIN_NP27_INITIN(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PCR2_P7=(v).bPullup; \ + bFM_GPIO_DDR2_P7=0u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +#define GPIO1PIN_NP27_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + bFM_GPIO_PDOR2_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P7=1u; \ + bFM_GPIO_PFR2_P7=0u; }while(0u) + +/*---- GPIO bit P28 ----*/ +#define GPIO1PIN_P28_GET ( bFM_GPIO_PDIR2_P8 ) + +#define GPIO1PIN_P28_PUT(v) ( bFM_GPIO_PDOR2_P8=(v) ) + +#define GPIO1PIN_P28_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P28_INITIN(v) \ + : GPIO1PIN_P28_INITOUT(v) ) + +#define GPIO1PIN_P28_INITIN(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PCR2_P8=(v).bPullup; \ + bFM_GPIO_DDR2_P8=0u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +#define GPIO1PIN_P28_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PDOR2_P8=(v).bInitVal; \ + bFM_GPIO_DDR2_P8=1u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +/*---- GPIO bit NP28 ----*/ +#define GPIO1PIN_NP28_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P8)) ) + +#define GPIO1PIN_NP28_PUT(v) ( bFM_GPIO_PDOR2_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP28_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP28_INITIN(v) \ + : GPIO1PIN_NP28_INITOUT(v) ) + +#define GPIO1PIN_NP28_INITIN(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PCR2_P8=(v).bPullup; \ + bFM_GPIO_DDR2_P8=0u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +#define GPIO1PIN_NP28_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + bFM_GPIO_PDOR2_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P8=1u; \ + bFM_GPIO_PFR2_P8=0u; }while(0u) + +/*---- GPIO bit P29 ----*/ +#define GPIO1PIN_P29_GET ( bFM_GPIO_PDIR2_P9 ) + +#define GPIO1PIN_P29_PUT(v) ( bFM_GPIO_PDOR2_P9=(v) ) + +#define GPIO1PIN_P29_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P29_INITIN(v) \ + : GPIO1PIN_P29_INITOUT(v) ) + +#define GPIO1PIN_P29_INITIN(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PCR2_P9=(v).bPullup; \ + bFM_GPIO_DDR2_P9=0u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +#define GPIO1PIN_P29_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PDOR2_P9=(v).bInitVal; \ + bFM_GPIO_DDR2_P9=1u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +/*---- GPIO bit NP29 ----*/ +#define GPIO1PIN_NP29_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_P9)) ) + +#define GPIO1PIN_NP29_PUT(v) ( bFM_GPIO_PDOR2_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP29_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP29_INITIN(v) \ + : GPIO1PIN_NP29_INITOUT(v) ) + +#define GPIO1PIN_NP29_INITIN(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PCR2_P9=(v).bPullup; \ + bFM_GPIO_DDR2_P9=0u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +#define GPIO1PIN_NP29_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + bFM_GPIO_PDOR2_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_P9=1u; \ + bFM_GPIO_PFR2_P9=0u; }while(0u) + +/*---- GPIO bit P2A ----*/ +#define GPIO1PIN_P2A_GET ( bFM_GPIO_PDIR2_PA ) + +#define GPIO1PIN_P2A_PUT(v) ( bFM_GPIO_PDOR2_PA=(v) ) + +#define GPIO1PIN_P2A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P2A_INITIN(v) \ + : GPIO1PIN_P2A_INITOUT(v) ) + +#define GPIO1PIN_P2A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PCR2_PA=(v).bPullup; \ + bFM_GPIO_DDR2_PA=0u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +#define GPIO1PIN_P2A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PDOR2_PA=(v).bInitVal; \ + bFM_GPIO_DDR2_PA=1u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +/*---- GPIO bit NP2A ----*/ +#define GPIO1PIN_NP2A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR2_PA)) ) + +#define GPIO1PIN_NP2A_PUT(v) ( bFM_GPIO_PDOR2_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP2A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP2A_INITIN(v) \ + : GPIO1PIN_NP2A_INITOUT(v) ) + +#define GPIO1PIN_NP2A_INITIN(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PCR2_PA=(v).bPullup; \ + bFM_GPIO_DDR2_PA=0u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +#define GPIO1PIN_NP2A_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + bFM_GPIO_PDOR2_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR2_PA=1u; \ + bFM_GPIO_PFR2_PA=0u; }while(0u) + +/*---- GPIO bit P30 ----*/ +#define GPIO1PIN_P30_GET ( bFM_GPIO_PDIR3_P0 ) + +#define GPIO1PIN_P30_PUT(v) ( bFM_GPIO_PDOR3_P0=(v) ) + +#define GPIO1PIN_P30_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P30_INITIN(v) \ + : GPIO1PIN_P30_INITOUT(v) ) + +#define GPIO1PIN_P30_INITIN(v) do{ \ + bFM_GPIO_PCR3_P0=(v).bPullup; \ + bFM_GPIO_DDR3_P0=0u; \ + bFM_GPIO_PFR3_P0=0u; }while(0u) + +#define GPIO1PIN_P30_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P0=(v).bInitVal; \ + bFM_GPIO_DDR3_P0=1u; \ + bFM_GPIO_PFR3_P0=0u; }while(0u) + +/*---- GPIO bit NP30 ----*/ +#define GPIO1PIN_NP30_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P0)) ) + +#define GPIO1PIN_NP30_PUT(v) ( bFM_GPIO_PDOR3_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP30_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP30_INITIN(v) \ + : GPIO1PIN_NP30_INITOUT(v) ) + +#define GPIO1PIN_NP30_INITIN(v) do{ \ + bFM_GPIO_PCR3_P0=(v).bPullup; \ + bFM_GPIO_DDR3_P0=0u; \ + bFM_GPIO_PFR3_P0=0u; }while(0u) + +#define GPIO1PIN_NP30_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P0=1u; \ + bFM_GPIO_PFR3_P0=0u; }while(0u) + +/*---- GPIO bit P31 ----*/ +#define GPIO1PIN_P31_GET ( bFM_GPIO_PDIR3_P1 ) + +#define GPIO1PIN_P31_PUT(v) ( bFM_GPIO_PDOR3_P1=(v) ) + +#define GPIO1PIN_P31_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P31_INITIN(v) \ + : GPIO1PIN_P31_INITOUT(v) ) + +#define GPIO1PIN_P31_INITIN(v) do{ \ + bFM_GPIO_PCR3_P1=(v).bPullup; \ + bFM_GPIO_DDR3_P1=0u; \ + bFM_GPIO_PFR3_P1=0u; }while(0u) + +#define GPIO1PIN_P31_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P1=(v).bInitVal; \ + bFM_GPIO_DDR3_P1=1u; \ + bFM_GPIO_PFR3_P1=0u; }while(0u) + +/*---- GPIO bit NP31 ----*/ +#define GPIO1PIN_NP31_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P1)) ) + +#define GPIO1PIN_NP31_PUT(v) ( bFM_GPIO_PDOR3_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP31_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP31_INITIN(v) \ + : GPIO1PIN_NP31_INITOUT(v) ) + +#define GPIO1PIN_NP31_INITIN(v) do{ \ + bFM_GPIO_PCR3_P1=(v).bPullup; \ + bFM_GPIO_DDR3_P1=0u; \ + bFM_GPIO_PFR3_P1=0u; }while(0u) + +#define GPIO1PIN_NP31_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P1=1u; \ + bFM_GPIO_PFR3_P1=0u; }while(0u) + +/*---- GPIO bit P32 ----*/ +#define GPIO1PIN_P32_GET ( bFM_GPIO_PDIR3_P2 ) + +#define GPIO1PIN_P32_PUT(v) ( bFM_GPIO_PDOR3_P2=(v) ) + +#define GPIO1PIN_P32_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P32_INITIN(v) \ + : GPIO1PIN_P32_INITOUT(v) ) + +#define GPIO1PIN_P32_INITIN(v) do{ \ + bFM_GPIO_PCR3_P2=(v).bPullup; \ + bFM_GPIO_DDR3_P2=0u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +#define GPIO1PIN_P32_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P2=(v).bInitVal; \ + bFM_GPIO_DDR3_P2=1u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +/*---- GPIO bit NP32 ----*/ +#define GPIO1PIN_NP32_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P2)) ) + +#define GPIO1PIN_NP32_PUT(v) ( bFM_GPIO_PDOR3_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP32_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP32_INITIN(v) \ + : GPIO1PIN_NP32_INITOUT(v) ) + +#define GPIO1PIN_NP32_INITIN(v) do{ \ + bFM_GPIO_PCR3_P2=(v).bPullup; \ + bFM_GPIO_DDR3_P2=0u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +#define GPIO1PIN_NP32_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P2=1u; \ + bFM_GPIO_PFR3_P2=0u; }while(0u) + +/*---- GPIO bit P33 ----*/ +#define GPIO1PIN_P33_GET ( bFM_GPIO_PDIR3_P3 ) + +#define GPIO1PIN_P33_PUT(v) ( bFM_GPIO_PDOR3_P3=(v) ) + +#define GPIO1PIN_P33_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P33_INITIN(v) \ + : GPIO1PIN_P33_INITOUT(v) ) + +#define GPIO1PIN_P33_INITIN(v) do{ \ + bFM_GPIO_PCR3_P3=(v).bPullup; \ + bFM_GPIO_DDR3_P3=0u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +#define GPIO1PIN_P33_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P3=(v).bInitVal; \ + bFM_GPIO_DDR3_P3=1u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +/*---- GPIO bit NP33 ----*/ +#define GPIO1PIN_NP33_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P3)) ) + +#define GPIO1PIN_NP33_PUT(v) ( bFM_GPIO_PDOR3_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP33_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP33_INITIN(v) \ + : GPIO1PIN_NP33_INITOUT(v) ) + +#define GPIO1PIN_NP33_INITIN(v) do{ \ + bFM_GPIO_PCR3_P3=(v).bPullup; \ + bFM_GPIO_DDR3_P3=0u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +#define GPIO1PIN_NP33_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P3=1u; \ + bFM_GPIO_PFR3_P3=0u; }while(0u) + +/*---- GPIO bit P34 ----*/ +#define GPIO1PIN_P34_GET ( bFM_GPIO_PDIR3_P4 ) + +#define GPIO1PIN_P34_PUT(v) ( bFM_GPIO_PDOR3_P4=(v) ) + +#define GPIO1PIN_P34_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P34_INITIN(v) \ + : GPIO1PIN_P34_INITOUT(v) ) + +#define GPIO1PIN_P34_INITIN(v) do{ \ + bFM_GPIO_PCR3_P4=(v).bPullup; \ + bFM_GPIO_DDR3_P4=0u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +#define GPIO1PIN_P34_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P4=(v).bInitVal; \ + bFM_GPIO_DDR3_P4=1u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +/*---- GPIO bit NP34 ----*/ +#define GPIO1PIN_NP34_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P4)) ) + +#define GPIO1PIN_NP34_PUT(v) ( bFM_GPIO_PDOR3_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP34_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP34_INITIN(v) \ + : GPIO1PIN_NP34_INITOUT(v) ) + +#define GPIO1PIN_NP34_INITIN(v) do{ \ + bFM_GPIO_PCR3_P4=(v).bPullup; \ + bFM_GPIO_DDR3_P4=0u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +#define GPIO1PIN_NP34_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P4=1u; \ + bFM_GPIO_PFR3_P4=0u; }while(0u) + +/*---- GPIO bit P35 ----*/ +#define GPIO1PIN_P35_GET ( bFM_GPIO_PDIR3_P5 ) + +#define GPIO1PIN_P35_PUT(v) ( bFM_GPIO_PDOR3_P5=(v) ) + +#define GPIO1PIN_P35_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P35_INITIN(v) \ + : GPIO1PIN_P35_INITOUT(v) ) + +#define GPIO1PIN_P35_INITIN(v) do{ \ + bFM_GPIO_PCR3_P5=(v).bPullup; \ + bFM_GPIO_DDR3_P5=0u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +#define GPIO1PIN_P35_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P5=(v).bInitVal; \ + bFM_GPIO_DDR3_P5=1u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +/*---- GPIO bit NP35 ----*/ +#define GPIO1PIN_NP35_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P5)) ) + +#define GPIO1PIN_NP35_PUT(v) ( bFM_GPIO_PDOR3_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP35_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP35_INITIN(v) \ + : GPIO1PIN_NP35_INITOUT(v) ) + +#define GPIO1PIN_NP35_INITIN(v) do{ \ + bFM_GPIO_PCR3_P5=(v).bPullup; \ + bFM_GPIO_DDR3_P5=0u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +#define GPIO1PIN_NP35_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P5=1u; \ + bFM_GPIO_PFR3_P5=0u; }while(0u) + +/*---- GPIO bit P36 ----*/ +#define GPIO1PIN_P36_GET ( bFM_GPIO_PDIR3_P6 ) + +#define GPIO1PIN_P36_PUT(v) ( bFM_GPIO_PDOR3_P6=(v) ) + +#define GPIO1PIN_P36_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P36_INITIN(v) \ + : GPIO1PIN_P36_INITOUT(v) ) + +#define GPIO1PIN_P36_INITIN(v) do{ \ + bFM_GPIO_PCR3_P6=(v).bPullup; \ + bFM_GPIO_DDR3_P6=0u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +#define GPIO1PIN_P36_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P6=(v).bInitVal; \ + bFM_GPIO_DDR3_P6=1u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +/*---- GPIO bit NP36 ----*/ +#define GPIO1PIN_NP36_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P6)) ) + +#define GPIO1PIN_NP36_PUT(v) ( bFM_GPIO_PDOR3_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP36_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP36_INITIN(v) \ + : GPIO1PIN_NP36_INITOUT(v) ) + +#define GPIO1PIN_NP36_INITIN(v) do{ \ + bFM_GPIO_PCR3_P6=(v).bPullup; \ + bFM_GPIO_DDR3_P6=0u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +#define GPIO1PIN_NP36_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P6=1u; \ + bFM_GPIO_PFR3_P6=0u; }while(0u) + +/*---- GPIO bit P37 ----*/ +#define GPIO1PIN_P37_GET ( bFM_GPIO_PDIR3_P7 ) + +#define GPIO1PIN_P37_PUT(v) ( bFM_GPIO_PDOR3_P7=(v) ) + +#define GPIO1PIN_P37_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P37_INITIN(v) \ + : GPIO1PIN_P37_INITOUT(v) ) + +#define GPIO1PIN_P37_INITIN(v) do{ \ + bFM_GPIO_PCR3_P7=(v).bPullup; \ + bFM_GPIO_DDR3_P7=0u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +#define GPIO1PIN_P37_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P7=(v).bInitVal; \ + bFM_GPIO_DDR3_P7=1u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +/*---- GPIO bit NP37 ----*/ +#define GPIO1PIN_NP37_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P7)) ) + +#define GPIO1PIN_NP37_PUT(v) ( bFM_GPIO_PDOR3_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP37_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP37_INITIN(v) \ + : GPIO1PIN_NP37_INITOUT(v) ) + +#define GPIO1PIN_NP37_INITIN(v) do{ \ + bFM_GPIO_PCR3_P7=(v).bPullup; \ + bFM_GPIO_DDR3_P7=0u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +#define GPIO1PIN_NP37_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P7=1u; \ + bFM_GPIO_PFR3_P7=0u; }while(0u) + +/*---- GPIO bit P38 ----*/ +#define GPIO1PIN_P38_GET ( bFM_GPIO_PDIR3_P8 ) + +#define GPIO1PIN_P38_PUT(v) ( bFM_GPIO_PDOR3_P8=(v) ) + +#define GPIO1PIN_P38_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P38_INITIN(v) \ + : GPIO1PIN_P38_INITOUT(v) ) + +#define GPIO1PIN_P38_INITIN(v) do{ \ + bFM_GPIO_PCR3_P8=(v).bPullup; \ + bFM_GPIO_DDR3_P8=0u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +#define GPIO1PIN_P38_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P8=(v).bInitVal; \ + bFM_GPIO_DDR3_P8=1u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +/*---- GPIO bit NP38 ----*/ +#define GPIO1PIN_NP38_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P8)) ) + +#define GPIO1PIN_NP38_PUT(v) ( bFM_GPIO_PDOR3_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP38_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP38_INITIN(v) \ + : GPIO1PIN_NP38_INITOUT(v) ) + +#define GPIO1PIN_NP38_INITIN(v) do{ \ + bFM_GPIO_PCR3_P8=(v).bPullup; \ + bFM_GPIO_DDR3_P8=0u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +#define GPIO1PIN_NP38_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P8=1u; \ + bFM_GPIO_PFR3_P8=0u; }while(0u) + +/*---- GPIO bit P39 ----*/ +#define GPIO1PIN_P39_GET ( bFM_GPIO_PDIR3_P9 ) + +#define GPIO1PIN_P39_PUT(v) ( bFM_GPIO_PDOR3_P9=(v) ) + +#define GPIO1PIN_P39_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P39_INITIN(v) \ + : GPIO1PIN_P39_INITOUT(v) ) + +#define GPIO1PIN_P39_INITIN(v) do{ \ + bFM_GPIO_PCR3_P9=(v).bPullup; \ + bFM_GPIO_DDR3_P9=0u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +#define GPIO1PIN_P39_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P9=(v).bInitVal; \ + bFM_GPIO_DDR3_P9=1u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +/*---- GPIO bit NP39 ----*/ +#define GPIO1PIN_NP39_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_P9)) ) + +#define GPIO1PIN_NP39_PUT(v) ( bFM_GPIO_PDOR3_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP39_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP39_INITIN(v) \ + : GPIO1PIN_NP39_INITOUT(v) ) + +#define GPIO1PIN_NP39_INITIN(v) do{ \ + bFM_GPIO_PCR3_P9=(v).bPullup; \ + bFM_GPIO_DDR3_P9=0u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +#define GPIO1PIN_NP39_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_P9=1u; \ + bFM_GPIO_PFR3_P9=0u; }while(0u) + +/*---- GPIO bit P3A ----*/ +#define GPIO1PIN_P3A_GET ( bFM_GPIO_PDIR3_PA ) + +#define GPIO1PIN_P3A_PUT(v) ( bFM_GPIO_PDOR3_PA=(v) ) + +#define GPIO1PIN_P3A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3A_INITIN(v) \ + : GPIO1PIN_P3A_INITOUT(v) ) + +#define GPIO1PIN_P3A_INITIN(v) do{ \ + bFM_GPIO_PCR3_PA=(v).bPullup; \ + bFM_GPIO_DDR3_PA=0u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +#define GPIO1PIN_P3A_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PA=(v).bInitVal; \ + bFM_GPIO_DDR3_PA=1u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +/*---- GPIO bit NP3A ----*/ +#define GPIO1PIN_NP3A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PA)) ) + +#define GPIO1PIN_NP3A_PUT(v) ( bFM_GPIO_PDOR3_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3A_INITIN(v) \ + : GPIO1PIN_NP3A_INITOUT(v) ) + +#define GPIO1PIN_NP3A_INITIN(v) do{ \ + bFM_GPIO_PCR3_PA=(v).bPullup; \ + bFM_GPIO_DDR3_PA=0u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +#define GPIO1PIN_NP3A_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PA=1u; \ + bFM_GPIO_PFR3_PA=0u; }while(0u) + +/*---- GPIO bit P3B ----*/ +#define GPIO1PIN_P3B_GET ( bFM_GPIO_PDIR3_PB ) + +#define GPIO1PIN_P3B_PUT(v) ( bFM_GPIO_PDOR3_PB=(v) ) + +#define GPIO1PIN_P3B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3B_INITIN(v) \ + : GPIO1PIN_P3B_INITOUT(v) ) + +#define GPIO1PIN_P3B_INITIN(v) do{ \ + bFM_GPIO_PCR3_PB=(v).bPullup; \ + bFM_GPIO_DDR3_PB=0u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +#define GPIO1PIN_P3B_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PB=(v).bInitVal; \ + bFM_GPIO_DDR3_PB=1u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +/*---- GPIO bit NP3B ----*/ +#define GPIO1PIN_NP3B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PB)) ) + +#define GPIO1PIN_NP3B_PUT(v) ( bFM_GPIO_PDOR3_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3B_INITIN(v) \ + : GPIO1PIN_NP3B_INITOUT(v) ) + +#define GPIO1PIN_NP3B_INITIN(v) do{ \ + bFM_GPIO_PCR3_PB=(v).bPullup; \ + bFM_GPIO_DDR3_PB=0u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +#define GPIO1PIN_NP3B_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PB=1u; \ + bFM_GPIO_PFR3_PB=0u; }while(0u) + +/*---- GPIO bit P3C ----*/ +#define GPIO1PIN_P3C_GET ( bFM_GPIO_PDIR3_PC ) + +#define GPIO1PIN_P3C_PUT(v) ( bFM_GPIO_PDOR3_PC=(v) ) + +#define GPIO1PIN_P3C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3C_INITIN(v) \ + : GPIO1PIN_P3C_INITOUT(v) ) + +#define GPIO1PIN_P3C_INITIN(v) do{ \ + bFM_GPIO_PCR3_PC=(v).bPullup; \ + bFM_GPIO_DDR3_PC=0u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +#define GPIO1PIN_P3C_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PC=(v).bInitVal; \ + bFM_GPIO_DDR3_PC=1u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +/*---- GPIO bit NP3C ----*/ +#define GPIO1PIN_NP3C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PC)) ) + +#define GPIO1PIN_NP3C_PUT(v) ( bFM_GPIO_PDOR3_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3C_INITIN(v) \ + : GPIO1PIN_NP3C_INITOUT(v) ) + +#define GPIO1PIN_NP3C_INITIN(v) do{ \ + bFM_GPIO_PCR3_PC=(v).bPullup; \ + bFM_GPIO_DDR3_PC=0u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +#define GPIO1PIN_NP3C_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PC=1u; \ + bFM_GPIO_PFR3_PC=0u; }while(0u) + +/*---- GPIO bit P3D ----*/ +#define GPIO1PIN_P3D_GET ( bFM_GPIO_PDIR3_PD ) + +#define GPIO1PIN_P3D_PUT(v) ( bFM_GPIO_PDOR3_PD=(v) ) + +#define GPIO1PIN_P3D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3D_INITIN(v) \ + : GPIO1PIN_P3D_INITOUT(v) ) + +#define GPIO1PIN_P3D_INITIN(v) do{ \ + bFM_GPIO_PCR3_PD=(v).bPullup; \ + bFM_GPIO_DDR3_PD=0u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +#define GPIO1PIN_P3D_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PD=(v).bInitVal; \ + bFM_GPIO_DDR3_PD=1u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +/*---- GPIO bit NP3D ----*/ +#define GPIO1PIN_NP3D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PD)) ) + +#define GPIO1PIN_NP3D_PUT(v) ( bFM_GPIO_PDOR3_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3D_INITIN(v) \ + : GPIO1PIN_NP3D_INITOUT(v) ) + +#define GPIO1PIN_NP3D_INITIN(v) do{ \ + bFM_GPIO_PCR3_PD=(v).bPullup; \ + bFM_GPIO_DDR3_PD=0u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +#define GPIO1PIN_NP3D_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PD=1u; \ + bFM_GPIO_PFR3_PD=0u; }while(0u) + +/*---- GPIO bit P3E ----*/ +#define GPIO1PIN_P3E_GET ( bFM_GPIO_PDIR3_PE ) + +#define GPIO1PIN_P3E_PUT(v) ( bFM_GPIO_PDOR3_PE=(v) ) + +#define GPIO1PIN_P3E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P3E_INITIN(v) \ + : GPIO1PIN_P3E_INITOUT(v) ) + +#define GPIO1PIN_P3E_INITIN(v) do{ \ + bFM_GPIO_PCR3_PE=(v).bPullup; \ + bFM_GPIO_DDR3_PE=0u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +#define GPIO1PIN_P3E_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PE=(v).bInitVal; \ + bFM_GPIO_DDR3_PE=1u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +/*---- GPIO bit NP3E ----*/ +#define GPIO1PIN_NP3E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR3_PE)) ) + +#define GPIO1PIN_NP3E_PUT(v) ( bFM_GPIO_PDOR3_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP3E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP3E_INITIN(v) \ + : GPIO1PIN_NP3E_INITOUT(v) ) + +#define GPIO1PIN_NP3E_INITIN(v) do{ \ + bFM_GPIO_PCR3_PE=(v).bPullup; \ + bFM_GPIO_DDR3_PE=0u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +#define GPIO1PIN_NP3E_INITOUT(v) do{ \ + bFM_GPIO_PDOR3_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR3_PE=1u; \ + bFM_GPIO_PFR3_PE=0u; }while(0u) + +/*---- GPIO bit P40 ----*/ +#define GPIO1PIN_P40_GET ( bFM_GPIO_PDIR4_P0 ) + +#define GPIO1PIN_P40_PUT(v) ( bFM_GPIO_PDOR4_P0=(v) ) + +#define GPIO1PIN_P40_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P40_INITIN(v) \ + : GPIO1PIN_P40_INITOUT(v) ) + +#define GPIO1PIN_P40_INITIN(v) do{ \ + bFM_GPIO_PCR4_P0=(v).bPullup; \ + bFM_GPIO_DDR4_P0=0u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +#define GPIO1PIN_P40_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P0=(v).bInitVal; \ + bFM_GPIO_DDR4_P0=1u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +/*---- GPIO bit NP40 ----*/ +#define GPIO1PIN_NP40_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P0)) ) + +#define GPIO1PIN_NP40_PUT(v) ( bFM_GPIO_PDOR4_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP40_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP40_INITIN(v) \ + : GPIO1PIN_NP40_INITOUT(v) ) + +#define GPIO1PIN_NP40_INITIN(v) do{ \ + bFM_GPIO_PCR4_P0=(v).bPullup; \ + bFM_GPIO_DDR4_P0=0u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +#define GPIO1PIN_NP40_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P0=1u; \ + bFM_GPIO_PFR4_P0=0u; }while(0u) + +/*---- GPIO bit P41 ----*/ +#define GPIO1PIN_P41_GET ( bFM_GPIO_PDIR4_P1 ) + +#define GPIO1PIN_P41_PUT(v) ( bFM_GPIO_PDOR4_P1=(v) ) + +#define GPIO1PIN_P41_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P41_INITIN(v) \ + : GPIO1PIN_P41_INITOUT(v) ) + +#define GPIO1PIN_P41_INITIN(v) do{ \ + bFM_GPIO_PCR4_P1=(v).bPullup; \ + bFM_GPIO_DDR4_P1=0u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +#define GPIO1PIN_P41_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P1=(v).bInitVal; \ + bFM_GPIO_DDR4_P1=1u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +/*---- GPIO bit NP41 ----*/ +#define GPIO1PIN_NP41_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P1)) ) + +#define GPIO1PIN_NP41_PUT(v) ( bFM_GPIO_PDOR4_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP41_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP41_INITIN(v) \ + : GPIO1PIN_NP41_INITOUT(v) ) + +#define GPIO1PIN_NP41_INITIN(v) do{ \ + bFM_GPIO_PCR4_P1=(v).bPullup; \ + bFM_GPIO_DDR4_P1=0u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +#define GPIO1PIN_NP41_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P1=1u; \ + bFM_GPIO_PFR4_P1=0u; }while(0u) + +/*---- GPIO bit P42 ----*/ +#define GPIO1PIN_P42_GET ( bFM_GPIO_PDIR4_P2 ) + +#define GPIO1PIN_P42_PUT(v) ( bFM_GPIO_PDOR4_P2=(v) ) + +#define GPIO1PIN_P42_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P42_INITIN(v) \ + : GPIO1PIN_P42_INITOUT(v) ) + +#define GPIO1PIN_P42_INITIN(v) do{ \ + bFM_GPIO_PCR4_P2=(v).bPullup; \ + bFM_GPIO_DDR4_P2=0u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +#define GPIO1PIN_P42_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P2=(v).bInitVal; \ + bFM_GPIO_DDR4_P2=1u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +/*---- GPIO bit NP42 ----*/ +#define GPIO1PIN_NP42_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P2)) ) + +#define GPIO1PIN_NP42_PUT(v) ( bFM_GPIO_PDOR4_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP42_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP42_INITIN(v) \ + : GPIO1PIN_NP42_INITOUT(v) ) + +#define GPIO1PIN_NP42_INITIN(v) do{ \ + bFM_GPIO_PCR4_P2=(v).bPullup; \ + bFM_GPIO_DDR4_P2=0u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +#define GPIO1PIN_NP42_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P2=1u; \ + bFM_GPIO_PFR4_P2=0u; }while(0u) + +/*---- GPIO bit P43 ----*/ +#define GPIO1PIN_P43_GET ( bFM_GPIO_PDIR4_P3 ) + +#define GPIO1PIN_P43_PUT(v) ( bFM_GPIO_PDOR4_P3=(v) ) + +#define GPIO1PIN_P43_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P43_INITIN(v) \ + : GPIO1PIN_P43_INITOUT(v) ) + +#define GPIO1PIN_P43_INITIN(v) do{ \ + bFM_GPIO_PCR4_P3=(v).bPullup; \ + bFM_GPIO_DDR4_P3=0u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +#define GPIO1PIN_P43_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P3=(v).bInitVal; \ + bFM_GPIO_DDR4_P3=1u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +/*---- GPIO bit NP43 ----*/ +#define GPIO1PIN_NP43_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P3)) ) + +#define GPIO1PIN_NP43_PUT(v) ( bFM_GPIO_PDOR4_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP43_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP43_INITIN(v) \ + : GPIO1PIN_NP43_INITOUT(v) ) + +#define GPIO1PIN_NP43_INITIN(v) do{ \ + bFM_GPIO_PCR4_P3=(v).bPullup; \ + bFM_GPIO_DDR4_P3=0u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +#define GPIO1PIN_NP43_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P3=1u; \ + bFM_GPIO_PFR4_P3=0u; }while(0u) + +/*---- GPIO bit P44 ----*/ +#define GPIO1PIN_P44_GET ( bFM_GPIO_PDIR4_P4 ) + +#define GPIO1PIN_P44_PUT(v) ( bFM_GPIO_PDOR4_P4=(v) ) + +#define GPIO1PIN_P44_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P44_INITIN(v) \ + : GPIO1PIN_P44_INITOUT(v) ) + +#define GPIO1PIN_P44_INITIN(v) do{ \ + bFM_GPIO_PCR4_P4=(v).bPullup; \ + bFM_GPIO_DDR4_P4=0u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +#define GPIO1PIN_P44_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P4=(v).bInitVal; \ + bFM_GPIO_DDR4_P4=1u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +/*---- GPIO bit NP44 ----*/ +#define GPIO1PIN_NP44_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P4)) ) + +#define GPIO1PIN_NP44_PUT(v) ( bFM_GPIO_PDOR4_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP44_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP44_INITIN(v) \ + : GPIO1PIN_NP44_INITOUT(v) ) + +#define GPIO1PIN_NP44_INITIN(v) do{ \ + bFM_GPIO_PCR4_P4=(v).bPullup; \ + bFM_GPIO_DDR4_P4=0u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +#define GPIO1PIN_NP44_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P4=1u; \ + bFM_GPIO_PFR4_P4=0u; }while(0u) + +/*---- GPIO bit P45 ----*/ +#define GPIO1PIN_P45_GET ( bFM_GPIO_PDIR4_P5 ) + +#define GPIO1PIN_P45_PUT(v) ( bFM_GPIO_PDOR4_P5=(v) ) + +#define GPIO1PIN_P45_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P45_INITIN(v) \ + : GPIO1PIN_P45_INITOUT(v) ) + +#define GPIO1PIN_P45_INITIN(v) do{ \ + bFM_GPIO_PCR4_P5=(v).bPullup; \ + bFM_GPIO_DDR4_P5=0u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +#define GPIO1PIN_P45_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P5=(v).bInitVal; \ + bFM_GPIO_DDR4_P5=1u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +/*---- GPIO bit NP45 ----*/ +#define GPIO1PIN_NP45_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_P5)) ) + +#define GPIO1PIN_NP45_PUT(v) ( bFM_GPIO_PDOR4_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP45_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP45_INITIN(v) \ + : GPIO1PIN_NP45_INITOUT(v) ) + +#define GPIO1PIN_NP45_INITIN(v) do{ \ + bFM_GPIO_PCR4_P5=(v).bPullup; \ + bFM_GPIO_DDR4_P5=0u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +#define GPIO1PIN_NP45_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_P5=1u; \ + bFM_GPIO_PFR4_P5=0u; }while(0u) + +/*---- GPIO bit P46 ----*/ +#define GPIO1PIN_P46_GET ( bFM_RTC_VBDIR_VDIR3 ) + +#define GPIO1PIN_P46_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P46_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P46_INITIN(v) \ + : GPIO1PIN_P46_INITOUT(v) ) + +#define GPIO1PIN_P46_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR3=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR3=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P46_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR3=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP46 ----*/ +#define GPIO1PIN_NP46_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR3)) ) + +#define GPIO1PIN_NP46_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP46_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP46_INITIN(v) \ + : GPIO1PIN_NP46_INITOUT(v) ) + +#define GPIO1PIN_NP46_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR3=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR3=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP46_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR3=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P47 ----*/ +#define GPIO1PIN_P47_GET ( bFM_RTC_VBDIR_VDIR2 ) + +#define GPIO1PIN_P47_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P47_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P47_INITIN(v) \ + : GPIO1PIN_P47_INITOUT(v) ) + +#define GPIO1PIN_P47_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR2=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR2=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P47_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR2=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP47 ----*/ +#define GPIO1PIN_NP47_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR2)) ) + +#define GPIO1PIN_NP47_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP47_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP47_INITIN(v) \ + : GPIO1PIN_NP47_INITOUT(v) ) + +#define GPIO1PIN_NP47_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR2=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR2=0u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP47_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR2=1u; \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P48 ----*/ +#define GPIO1PIN_P48_GET ( bFM_RTC_VBDIR_VDIR0 ) + +#define GPIO1PIN_P48_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P48_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P48_INITIN(v) \ + : GPIO1PIN_P48_INITOUT(v) ) + +#define GPIO1PIN_P48_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR0=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR0=0u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P48_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR0=1u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP48 ----*/ +#define GPIO1PIN_NP48_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR0)) ) + +#define GPIO1PIN_NP48_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP48_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP48_INITIN(v) \ + : GPIO1PIN_NP48_INITOUT(v) ) + +#define GPIO1PIN_NP48_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR0=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR0=0u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP48_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR0=1u; \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P49 ----*/ +#define GPIO1PIN_P49_GET ( bFM_RTC_VBDIR_VDIR1 ) + +#define GPIO1PIN_P49_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(v); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_P49_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P49_INITIN(v) \ + : GPIO1PIN_P49_INITOUT(v) ) + +#define GPIO1PIN_P49_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR1=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR1=0u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_P49_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(v).bInitVal; \ + bFM_RTC_VBDDR_VDDR1=1u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit NP49 ----*/ +#define GPIO1PIN_NP49_GET ( (uint32_t)(!(uint32_t)(bFM_RTC_VBDIR_VDIR1)) ) + +#define GPIO1PIN_NP49_PUT(v) do{ FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(uint32_t)(!(v)); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + } while(0u) + +#define GPIO1PIN_NP49_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP49_INITIN(v) \ + : GPIO1PIN_NP49_INITOUT(v) ) + +#define GPIO1PIN_NP49_INITIN(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPCR_VPCR1=(v).bPullup; \ + bFM_RTC_VBDDR_VDDR1=0u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +#define GPIO1PIN_NP49_INITOUT(v) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBDOR_VDOR1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_RTC_VBDDR_VDDR1=1u; \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while(0u) + +/*---- GPIO bit P4A ----*/ +#define GPIO1PIN_P4A_GET ( bFM_GPIO_PDIR4_PA ) + +#define GPIO1PIN_P4A_PUT(v) ( bFM_GPIO_PDOR4_PA=(v) ) + +#define GPIO1PIN_P4A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P4A_INITIN(v) \ + : GPIO1PIN_P4A_INITOUT(v) ) + +#define GPIO1PIN_P4A_INITIN(v) do{ \ + bFM_GPIO_PCR4_PA=(v).bPullup; \ + bFM_GPIO_DDR4_PA=0u; \ + bFM_GPIO_PFR4_PA=0u; }while(0u) + +#define GPIO1PIN_P4A_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PA=(v).bInitVal; \ + bFM_GPIO_DDR4_PA=1u; \ + bFM_GPIO_PFR4_PA=0u; }while(0u) + +/*---- GPIO bit NP4A ----*/ +#define GPIO1PIN_NP4A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_PA)) ) + +#define GPIO1PIN_NP4A_PUT(v) ( bFM_GPIO_PDOR4_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP4A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP4A_INITIN(v) \ + : GPIO1PIN_NP4A_INITOUT(v) ) + +#define GPIO1PIN_NP4A_INITIN(v) do{ \ + bFM_GPIO_PCR4_PA=(v).bPullup; \ + bFM_GPIO_DDR4_PA=0u; \ + bFM_GPIO_PFR4_PA=0u; }while(0u) + +#define GPIO1PIN_NP4A_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_PA=1u; \ + bFM_GPIO_PFR4_PA=0u; }while(0u) + +/*---- GPIO bit P4B ----*/ +#define GPIO1PIN_P4B_GET ( bFM_GPIO_PDIR4_PB ) + +#define GPIO1PIN_P4B_PUT(v) ( bFM_GPIO_PDOR4_PB=(v) ) + +#define GPIO1PIN_P4B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P4B_INITIN(v) \ + : GPIO1PIN_P4B_INITOUT(v) ) + +#define GPIO1PIN_P4B_INITIN(v) do{ \ + bFM_GPIO_PCR4_PB=(v).bPullup; \ + bFM_GPIO_DDR4_PB=0u; \ + bFM_GPIO_PFR4_PB=0u; }while(0u) + +#define GPIO1PIN_P4B_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PB=(v).bInitVal; \ + bFM_GPIO_DDR4_PB=1u; \ + bFM_GPIO_PFR4_PB=0u; }while(0u) + +/*---- GPIO bit NP4B ----*/ +#define GPIO1PIN_NP4B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_PB)) ) + +#define GPIO1PIN_NP4B_PUT(v) ( bFM_GPIO_PDOR4_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP4B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP4B_INITIN(v) \ + : GPIO1PIN_NP4B_INITOUT(v) ) + +#define GPIO1PIN_NP4B_INITIN(v) do{ \ + bFM_GPIO_PCR4_PB=(v).bPullup; \ + bFM_GPIO_DDR4_PB=0u; \ + bFM_GPIO_PFR4_PB=0u; }while(0u) + +#define GPIO1PIN_NP4B_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_PB=1u; \ + bFM_GPIO_PFR4_PB=0u; }while(0u) + +/*---- GPIO bit P4C ----*/ +#define GPIO1PIN_P4C_GET ( bFM_GPIO_PDIR4_PC ) + +#define GPIO1PIN_P4C_PUT(v) ( bFM_GPIO_PDOR4_PC=(v) ) + +#define GPIO1PIN_P4C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P4C_INITIN(v) \ + : GPIO1PIN_P4C_INITOUT(v) ) + +#define GPIO1PIN_P4C_INITIN(v) do{ \ + bFM_GPIO_PCR4_PC=(v).bPullup; \ + bFM_GPIO_DDR4_PC=0u; \ + bFM_GPIO_PFR4_PC=0u; }while(0u) + +#define GPIO1PIN_P4C_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PC=(v).bInitVal; \ + bFM_GPIO_DDR4_PC=1u; \ + bFM_GPIO_PFR4_PC=0u; }while(0u) + +/*---- GPIO bit NP4C ----*/ +#define GPIO1PIN_NP4C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_PC)) ) + +#define GPIO1PIN_NP4C_PUT(v) ( bFM_GPIO_PDOR4_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP4C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP4C_INITIN(v) \ + : GPIO1PIN_NP4C_INITOUT(v) ) + +#define GPIO1PIN_NP4C_INITIN(v) do{ \ + bFM_GPIO_PCR4_PC=(v).bPullup; \ + bFM_GPIO_DDR4_PC=0u; \ + bFM_GPIO_PFR4_PC=0u; }while(0u) + +#define GPIO1PIN_NP4C_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_PC=1u; \ + bFM_GPIO_PFR4_PC=0u; }while(0u) + +/*---- GPIO bit P4D ----*/ +#define GPIO1PIN_P4D_GET ( bFM_GPIO_PDIR4_PD ) + +#define GPIO1PIN_P4D_PUT(v) ( bFM_GPIO_PDOR4_PD=(v) ) + +#define GPIO1PIN_P4D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P4D_INITIN(v) \ + : GPIO1PIN_P4D_INITOUT(v) ) + +#define GPIO1PIN_P4D_INITIN(v) do{ \ + bFM_GPIO_PCR4_PD=(v).bPullup; \ + bFM_GPIO_DDR4_PD=0u; \ + bFM_GPIO_PFR4_PD=0u; }while(0u) + +#define GPIO1PIN_P4D_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PD=(v).bInitVal; \ + bFM_GPIO_DDR4_PD=1u; \ + bFM_GPIO_PFR4_PD=0u; }while(0u) + +/*---- GPIO bit NP4D ----*/ +#define GPIO1PIN_NP4D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_PD)) ) + +#define GPIO1PIN_NP4D_PUT(v) ( bFM_GPIO_PDOR4_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP4D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP4D_INITIN(v) \ + : GPIO1PIN_NP4D_INITOUT(v) ) + +#define GPIO1PIN_NP4D_INITIN(v) do{ \ + bFM_GPIO_PCR4_PD=(v).bPullup; \ + bFM_GPIO_DDR4_PD=0u; \ + bFM_GPIO_PFR4_PD=0u; }while(0u) + +#define GPIO1PIN_NP4D_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_PD=1u; \ + bFM_GPIO_PFR4_PD=0u; }while(0u) + +/*---- GPIO bit P4E ----*/ +#define GPIO1PIN_P4E_GET ( bFM_GPIO_PDIR4_PE ) + +#define GPIO1PIN_P4E_PUT(v) ( bFM_GPIO_PDOR4_PE=(v) ) + +#define GPIO1PIN_P4E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P4E_INITIN(v) \ + : GPIO1PIN_P4E_INITOUT(v) ) + +#define GPIO1PIN_P4E_INITIN(v) do{ \ + bFM_GPIO_PCR4_PE=(v).bPullup; \ + bFM_GPIO_DDR4_PE=0u; \ + bFM_GPIO_PFR4_PE=0u; }while(0u) + +#define GPIO1PIN_P4E_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PE=(v).bInitVal; \ + bFM_GPIO_DDR4_PE=1u; \ + bFM_GPIO_PFR4_PE=0u; }while(0u) + +/*---- GPIO bit NP4E ----*/ +#define GPIO1PIN_NP4E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR4_PE)) ) + +#define GPIO1PIN_NP4E_PUT(v) ( bFM_GPIO_PDOR4_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP4E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP4E_INITIN(v) \ + : GPIO1PIN_NP4E_INITOUT(v) ) + +#define GPIO1PIN_NP4E_INITIN(v) do{ \ + bFM_GPIO_PCR4_PE=(v).bPullup; \ + bFM_GPIO_DDR4_PE=0u; \ + bFM_GPIO_PFR4_PE=0u; }while(0u) + +#define GPIO1PIN_NP4E_INITOUT(v) do{ \ + bFM_GPIO_PDOR4_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR4_PE=1u; \ + bFM_GPIO_PFR4_PE=0u; }while(0u) + +/*---- GPIO bit P50 ----*/ +#define GPIO1PIN_P50_GET ( bFM_GPIO_PDIR5_P0 ) + +#define GPIO1PIN_P50_PUT(v) ( bFM_GPIO_PDOR5_P0=(v) ) + +#define GPIO1PIN_P50_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P50_INITIN(v) \ + : GPIO1PIN_P50_INITOUT(v) ) + +#define GPIO1PIN_P50_INITIN(v) do{ \ + bFM_GPIO_PCR5_P0=(v).bPullup; \ + bFM_GPIO_DDR5_P0=0u; \ + bFM_GPIO_PFR5_P0=0u; }while(0u) + +#define GPIO1PIN_P50_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P0=(v).bInitVal; \ + bFM_GPIO_DDR5_P0=1u; \ + bFM_GPIO_PFR5_P0=0u; }while(0u) + +/*---- GPIO bit NP50 ----*/ +#define GPIO1PIN_NP50_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P0)) ) + +#define GPIO1PIN_NP50_PUT(v) ( bFM_GPIO_PDOR5_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP50_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP50_INITIN(v) \ + : GPIO1PIN_NP50_INITOUT(v) ) + +#define GPIO1PIN_NP50_INITIN(v) do{ \ + bFM_GPIO_PCR5_P0=(v).bPullup; \ + bFM_GPIO_DDR5_P0=0u; \ + bFM_GPIO_PFR5_P0=0u; }while(0u) + +#define GPIO1PIN_NP50_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P0=1u; \ + bFM_GPIO_PFR5_P0=0u; }while(0u) + +/*---- GPIO bit P51 ----*/ +#define GPIO1PIN_P51_GET ( bFM_GPIO_PDIR5_P1 ) + +#define GPIO1PIN_P51_PUT(v) ( bFM_GPIO_PDOR5_P1=(v) ) + +#define GPIO1PIN_P51_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P51_INITIN(v) \ + : GPIO1PIN_P51_INITOUT(v) ) + +#define GPIO1PIN_P51_INITIN(v) do{ \ + bFM_GPIO_PCR5_P1=(v).bPullup; \ + bFM_GPIO_DDR5_P1=0u; \ + bFM_GPIO_PFR5_P1=0u; }while(0u) + +#define GPIO1PIN_P51_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P1=(v).bInitVal; \ + bFM_GPIO_DDR5_P1=1u; \ + bFM_GPIO_PFR5_P1=0u; }while(0u) + +/*---- GPIO bit NP51 ----*/ +#define GPIO1PIN_NP51_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P1)) ) + +#define GPIO1PIN_NP51_PUT(v) ( bFM_GPIO_PDOR5_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP51_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP51_INITIN(v) \ + : GPIO1PIN_NP51_INITOUT(v) ) + +#define GPIO1PIN_NP51_INITIN(v) do{ \ + bFM_GPIO_PCR5_P1=(v).bPullup; \ + bFM_GPIO_DDR5_P1=0u; \ + bFM_GPIO_PFR5_P1=0u; }while(0u) + +#define GPIO1PIN_NP51_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P1=1u; \ + bFM_GPIO_PFR5_P1=0u; }while(0u) + +/*---- GPIO bit P52 ----*/ +#define GPIO1PIN_P52_GET ( bFM_GPIO_PDIR5_P2 ) + +#define GPIO1PIN_P52_PUT(v) ( bFM_GPIO_PDOR5_P2=(v) ) + +#define GPIO1PIN_P52_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P52_INITIN(v) \ + : GPIO1PIN_P52_INITOUT(v) ) + +#define GPIO1PIN_P52_INITIN(v) do{ \ + bFM_GPIO_PCR5_P2=(v).bPullup; \ + bFM_GPIO_DDR5_P2=0u; \ + bFM_GPIO_PFR5_P2=0u; }while(0u) + +#define GPIO1PIN_P52_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P2=(v).bInitVal; \ + bFM_GPIO_DDR5_P2=1u; \ + bFM_GPIO_PFR5_P2=0u; }while(0u) + +/*---- GPIO bit NP52 ----*/ +#define GPIO1PIN_NP52_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P2)) ) + +#define GPIO1PIN_NP52_PUT(v) ( bFM_GPIO_PDOR5_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP52_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP52_INITIN(v) \ + : GPIO1PIN_NP52_INITOUT(v) ) + +#define GPIO1PIN_NP52_INITIN(v) do{ \ + bFM_GPIO_PCR5_P2=(v).bPullup; \ + bFM_GPIO_DDR5_P2=0u; \ + bFM_GPIO_PFR5_P2=0u; }while(0u) + +#define GPIO1PIN_NP52_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P2=1u; \ + bFM_GPIO_PFR5_P2=0u; }while(0u) + +/*---- GPIO bit P53 ----*/ +#define GPIO1PIN_P53_GET ( bFM_GPIO_PDIR5_P3 ) + +#define GPIO1PIN_P53_PUT(v) ( bFM_GPIO_PDOR5_P3=(v) ) + +#define GPIO1PIN_P53_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P53_INITIN(v) \ + : GPIO1PIN_P53_INITOUT(v) ) + +#define GPIO1PIN_P53_INITIN(v) do{ \ + bFM_GPIO_PCR5_P3=(v).bPullup; \ + bFM_GPIO_DDR5_P3=0u; \ + bFM_GPIO_PFR5_P3=0u; }while(0u) + +#define GPIO1PIN_P53_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P3=(v).bInitVal; \ + bFM_GPIO_DDR5_P3=1u; \ + bFM_GPIO_PFR5_P3=0u; }while(0u) + +/*---- GPIO bit NP53 ----*/ +#define GPIO1PIN_NP53_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P3)) ) + +#define GPIO1PIN_NP53_PUT(v) ( bFM_GPIO_PDOR5_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP53_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP53_INITIN(v) \ + : GPIO1PIN_NP53_INITOUT(v) ) + +#define GPIO1PIN_NP53_INITIN(v) do{ \ + bFM_GPIO_PCR5_P3=(v).bPullup; \ + bFM_GPIO_DDR5_P3=0u; \ + bFM_GPIO_PFR5_P3=0u; }while(0u) + +#define GPIO1PIN_NP53_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P3=1u; \ + bFM_GPIO_PFR5_P3=0u; }while(0u) + +/*---- GPIO bit P54 ----*/ +#define GPIO1PIN_P54_GET ( bFM_GPIO_PDIR5_P4 ) + +#define GPIO1PIN_P54_PUT(v) ( bFM_GPIO_PDOR5_P4=(v) ) + +#define GPIO1PIN_P54_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P54_INITIN(v) \ + : GPIO1PIN_P54_INITOUT(v) ) + +#define GPIO1PIN_P54_INITIN(v) do{ \ + bFM_GPIO_PCR5_P4=(v).bPullup; \ + bFM_GPIO_DDR5_P4=0u; \ + bFM_GPIO_PFR5_P4=0u; }while(0u) + +#define GPIO1PIN_P54_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P4=(v).bInitVal; \ + bFM_GPIO_DDR5_P4=1u; \ + bFM_GPIO_PFR5_P4=0u; }while(0u) + +/*---- GPIO bit NP54 ----*/ +#define GPIO1PIN_NP54_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P4)) ) + +#define GPIO1PIN_NP54_PUT(v) ( bFM_GPIO_PDOR5_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP54_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP54_INITIN(v) \ + : GPIO1PIN_NP54_INITOUT(v) ) + +#define GPIO1PIN_NP54_INITIN(v) do{ \ + bFM_GPIO_PCR5_P4=(v).bPullup; \ + bFM_GPIO_DDR5_P4=0u; \ + bFM_GPIO_PFR5_P4=0u; }while(0u) + +#define GPIO1PIN_NP54_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P4=1u; \ + bFM_GPIO_PFR5_P4=0u; }while(0u) + +/*---- GPIO bit P55 ----*/ +#define GPIO1PIN_P55_GET ( bFM_GPIO_PDIR5_P5 ) + +#define GPIO1PIN_P55_PUT(v) ( bFM_GPIO_PDOR5_P5=(v) ) + +#define GPIO1PIN_P55_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P55_INITIN(v) \ + : GPIO1PIN_P55_INITOUT(v) ) + +#define GPIO1PIN_P55_INITIN(v) do{ \ + bFM_GPIO_PCR5_P5=(v).bPullup; \ + bFM_GPIO_DDR5_P5=0u; \ + bFM_GPIO_PFR5_P5=0u; }while(0u) + +#define GPIO1PIN_P55_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P5=(v).bInitVal; \ + bFM_GPIO_DDR5_P5=1u; \ + bFM_GPIO_PFR5_P5=0u; }while(0u) + +/*---- GPIO bit NP55 ----*/ +#define GPIO1PIN_NP55_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P5)) ) + +#define GPIO1PIN_NP55_PUT(v) ( bFM_GPIO_PDOR5_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP55_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP55_INITIN(v) \ + : GPIO1PIN_NP55_INITOUT(v) ) + +#define GPIO1PIN_NP55_INITIN(v) do{ \ + bFM_GPIO_PCR5_P5=(v).bPullup; \ + bFM_GPIO_DDR5_P5=0u; \ + bFM_GPIO_PFR5_P5=0u; }while(0u) + +#define GPIO1PIN_NP55_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P5=1u; \ + bFM_GPIO_PFR5_P5=0u; }while(0u) + +/*---- GPIO bit P56 ----*/ +#define GPIO1PIN_P56_GET ( bFM_GPIO_PDIR5_P6 ) + +#define GPIO1PIN_P56_PUT(v) ( bFM_GPIO_PDOR5_P6=(v) ) + +#define GPIO1PIN_P56_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P56_INITIN(v) \ + : GPIO1PIN_P56_INITOUT(v) ) + +#define GPIO1PIN_P56_INITIN(v) do{ \ + bFM_GPIO_PCR5_P6=(v).bPullup; \ + bFM_GPIO_DDR5_P6=0u; \ + bFM_GPIO_PFR5_P6=0u; }while(0u) + +#define GPIO1PIN_P56_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P6=(v).bInitVal; \ + bFM_GPIO_DDR5_P6=1u; \ + bFM_GPIO_PFR5_P6=0u; }while(0u) + +/*---- GPIO bit NP56 ----*/ +#define GPIO1PIN_NP56_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P6)) ) + +#define GPIO1PIN_NP56_PUT(v) ( bFM_GPIO_PDOR5_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP56_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP56_INITIN(v) \ + : GPIO1PIN_NP56_INITOUT(v) ) + +#define GPIO1PIN_NP56_INITIN(v) do{ \ + bFM_GPIO_PCR5_P6=(v).bPullup; \ + bFM_GPIO_DDR5_P6=0u; \ + bFM_GPIO_PFR5_P6=0u; }while(0u) + +#define GPIO1PIN_NP56_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P6=1u; \ + bFM_GPIO_PFR5_P6=0u; }while(0u) + +/*---- GPIO bit P57 ----*/ +#define GPIO1PIN_P57_GET ( bFM_GPIO_PDIR5_P7 ) + +#define GPIO1PIN_P57_PUT(v) ( bFM_GPIO_PDOR5_P7=(v) ) + +#define GPIO1PIN_P57_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P57_INITIN(v) \ + : GPIO1PIN_P57_INITOUT(v) ) + +#define GPIO1PIN_P57_INITIN(v) do{ \ + bFM_GPIO_PCR5_P7=(v).bPullup; \ + bFM_GPIO_DDR5_P7=0u; \ + bFM_GPIO_PFR5_P7=0u; }while(0u) + +#define GPIO1PIN_P57_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P7=(v).bInitVal; \ + bFM_GPIO_DDR5_P7=1u; \ + bFM_GPIO_PFR5_P7=0u; }while(0u) + +/*---- GPIO bit NP57 ----*/ +#define GPIO1PIN_NP57_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P7)) ) + +#define GPIO1PIN_NP57_PUT(v) ( bFM_GPIO_PDOR5_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP57_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP57_INITIN(v) \ + : GPIO1PIN_NP57_INITOUT(v) ) + +#define GPIO1PIN_NP57_INITIN(v) do{ \ + bFM_GPIO_PCR5_P7=(v).bPullup; \ + bFM_GPIO_DDR5_P7=0u; \ + bFM_GPIO_PFR5_P7=0u; }while(0u) + +#define GPIO1PIN_NP57_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P7=1u; \ + bFM_GPIO_PFR5_P7=0u; }while(0u) + +/*---- GPIO bit P58 ----*/ +#define GPIO1PIN_P58_GET ( bFM_GPIO_PDIR5_P8 ) + +#define GPIO1PIN_P58_PUT(v) ( bFM_GPIO_PDOR5_P8=(v) ) + +#define GPIO1PIN_P58_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P58_INITIN(v) \ + : GPIO1PIN_P58_INITOUT(v) ) + +#define GPIO1PIN_P58_INITIN(v) do{ \ + bFM_GPIO_PCR5_P8=(v).bPullup; \ + bFM_GPIO_DDR5_P8=0u; \ + bFM_GPIO_PFR5_P8=0u; }while(0u) + +#define GPIO1PIN_P58_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P8=(v).bInitVal; \ + bFM_GPIO_DDR5_P8=1u; \ + bFM_GPIO_PFR5_P8=0u; }while(0u) + +/*---- GPIO bit NP58 ----*/ +#define GPIO1PIN_NP58_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P8)) ) + +#define GPIO1PIN_NP58_PUT(v) ( bFM_GPIO_PDOR5_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP58_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP58_INITIN(v) \ + : GPIO1PIN_NP58_INITOUT(v) ) + +#define GPIO1PIN_NP58_INITIN(v) do{ \ + bFM_GPIO_PCR5_P8=(v).bPullup; \ + bFM_GPIO_DDR5_P8=0u; \ + bFM_GPIO_PFR5_P8=0u; }while(0u) + +#define GPIO1PIN_NP58_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P8=1u; \ + bFM_GPIO_PFR5_P8=0u; }while(0u) + +/*---- GPIO bit P59 ----*/ +#define GPIO1PIN_P59_GET ( bFM_GPIO_PDIR5_P9 ) + +#define GPIO1PIN_P59_PUT(v) ( bFM_GPIO_PDOR5_P9=(v) ) + +#define GPIO1PIN_P59_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P59_INITIN(v) \ + : GPIO1PIN_P59_INITOUT(v) ) + +#define GPIO1PIN_P59_INITIN(v) do{ \ + bFM_GPIO_PCR5_P9=(v).bPullup; \ + bFM_GPIO_DDR5_P9=0u; \ + bFM_GPIO_PFR5_P9=0u; }while(0u) + +#define GPIO1PIN_P59_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P9=(v).bInitVal; \ + bFM_GPIO_DDR5_P9=1u; \ + bFM_GPIO_PFR5_P9=0u; }while(0u) + +/*---- GPIO bit NP59 ----*/ +#define GPIO1PIN_NP59_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_P9)) ) + +#define GPIO1PIN_NP59_PUT(v) ( bFM_GPIO_PDOR5_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP59_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP59_INITIN(v) \ + : GPIO1PIN_NP59_INITOUT(v) ) + +#define GPIO1PIN_NP59_INITIN(v) do{ \ + bFM_GPIO_PCR5_P9=(v).bPullup; \ + bFM_GPIO_DDR5_P9=0u; \ + bFM_GPIO_PFR5_P9=0u; }while(0u) + +#define GPIO1PIN_NP59_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_P9=1u; \ + bFM_GPIO_PFR5_P9=0u; }while(0u) + +/*---- GPIO bit P5A ----*/ +#define GPIO1PIN_P5A_GET ( bFM_GPIO_PDIR5_PA ) + +#define GPIO1PIN_P5A_PUT(v) ( bFM_GPIO_PDOR5_PA=(v) ) + +#define GPIO1PIN_P5A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P5A_INITIN(v) \ + : GPIO1PIN_P5A_INITOUT(v) ) + +#define GPIO1PIN_P5A_INITIN(v) do{ \ + bFM_GPIO_PCR5_PA=(v).bPullup; \ + bFM_GPIO_DDR5_PA=0u; \ + bFM_GPIO_PFR5_PA=0u; }while(0u) + +#define GPIO1PIN_P5A_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PA=(v).bInitVal; \ + bFM_GPIO_DDR5_PA=1u; \ + bFM_GPIO_PFR5_PA=0u; }while(0u) + +/*---- GPIO bit NP5A ----*/ +#define GPIO1PIN_NP5A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_PA)) ) + +#define GPIO1PIN_NP5A_PUT(v) ( bFM_GPIO_PDOR5_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP5A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP5A_INITIN(v) \ + : GPIO1PIN_NP5A_INITOUT(v) ) + +#define GPIO1PIN_NP5A_INITIN(v) do{ \ + bFM_GPIO_PCR5_PA=(v).bPullup; \ + bFM_GPIO_DDR5_PA=0u; \ + bFM_GPIO_PFR5_PA=0u; }while(0u) + +#define GPIO1PIN_NP5A_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_PA=1u; \ + bFM_GPIO_PFR5_PA=0u; }while(0u) + +/*---- GPIO bit P5B ----*/ +#define GPIO1PIN_P5B_GET ( bFM_GPIO_PDIR5_PB ) + +#define GPIO1PIN_P5B_PUT(v) ( bFM_GPIO_PDOR5_PB=(v) ) + +#define GPIO1PIN_P5B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P5B_INITIN(v) \ + : GPIO1PIN_P5B_INITOUT(v) ) + +#define GPIO1PIN_P5B_INITIN(v) do{ \ + bFM_GPIO_PCR5_PB=(v).bPullup; \ + bFM_GPIO_DDR5_PB=0u; \ + bFM_GPIO_PFR5_PB=0u; }while(0u) + +#define GPIO1PIN_P5B_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PB=(v).bInitVal; \ + bFM_GPIO_DDR5_PB=1u; \ + bFM_GPIO_PFR5_PB=0u; }while(0u) + +/*---- GPIO bit NP5B ----*/ +#define GPIO1PIN_NP5B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_PB)) ) + +#define GPIO1PIN_NP5B_PUT(v) ( bFM_GPIO_PDOR5_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP5B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP5B_INITIN(v) \ + : GPIO1PIN_NP5B_INITOUT(v) ) + +#define GPIO1PIN_NP5B_INITIN(v) do{ \ + bFM_GPIO_PCR5_PB=(v).bPullup; \ + bFM_GPIO_DDR5_PB=0u; \ + bFM_GPIO_PFR5_PB=0u; }while(0u) + +#define GPIO1PIN_NP5B_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_PB=1u; \ + bFM_GPIO_PFR5_PB=0u; }while(0u) + +/*---- GPIO bit P5C ----*/ +#define GPIO1PIN_P5C_GET ( bFM_GPIO_PDIR5_PC ) + +#define GPIO1PIN_P5C_PUT(v) ( bFM_GPIO_PDOR5_PC=(v) ) + +#define GPIO1PIN_P5C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P5C_INITIN(v) \ + : GPIO1PIN_P5C_INITOUT(v) ) + +#define GPIO1PIN_P5C_INITIN(v) do{ \ + bFM_GPIO_PCR5_PC=(v).bPullup; \ + bFM_GPIO_DDR5_PC=0u; \ + bFM_GPIO_PFR5_PC=0u; }while(0u) + +#define GPIO1PIN_P5C_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PC=(v).bInitVal; \ + bFM_GPIO_DDR5_PC=1u; \ + bFM_GPIO_PFR5_PC=0u; }while(0u) + +/*---- GPIO bit NP5C ----*/ +#define GPIO1PIN_NP5C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_PC)) ) + +#define GPIO1PIN_NP5C_PUT(v) ( bFM_GPIO_PDOR5_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP5C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP5C_INITIN(v) \ + : GPIO1PIN_NP5C_INITOUT(v) ) + +#define GPIO1PIN_NP5C_INITIN(v) do{ \ + bFM_GPIO_PCR5_PC=(v).bPullup; \ + bFM_GPIO_DDR5_PC=0u; \ + bFM_GPIO_PFR5_PC=0u; }while(0u) + +#define GPIO1PIN_NP5C_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_PC=1u; \ + bFM_GPIO_PFR5_PC=0u; }while(0u) + +/*---- GPIO bit P5D ----*/ +#define GPIO1PIN_P5D_GET ( bFM_GPIO_PDIR5_PD ) + +#define GPIO1PIN_P5D_PUT(v) ( bFM_GPIO_PDOR5_PD=(v) ) + +#define GPIO1PIN_P5D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P5D_INITIN(v) \ + : GPIO1PIN_P5D_INITOUT(v) ) + +#define GPIO1PIN_P5D_INITIN(v) do{ \ + bFM_GPIO_PCR5_PD=(v).bPullup; \ + bFM_GPIO_DDR5_PD=0u; \ + bFM_GPIO_PFR5_PD=0u; }while(0u) + +#define GPIO1PIN_P5D_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PD=(v).bInitVal; \ + bFM_GPIO_DDR5_PD=1u; \ + bFM_GPIO_PFR5_PD=0u; }while(0u) + +/*---- GPIO bit NP5D ----*/ +#define GPIO1PIN_NP5D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_PD)) ) + +#define GPIO1PIN_NP5D_PUT(v) ( bFM_GPIO_PDOR5_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP5D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP5D_INITIN(v) \ + : GPIO1PIN_NP5D_INITOUT(v) ) + +#define GPIO1PIN_NP5D_INITIN(v) do{ \ + bFM_GPIO_PCR5_PD=(v).bPullup; \ + bFM_GPIO_DDR5_PD=0u; \ + bFM_GPIO_PFR5_PD=0u; }while(0u) + +#define GPIO1PIN_NP5D_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_PD=1u; \ + bFM_GPIO_PFR5_PD=0u; }while(0u) + +/*---- GPIO bit P5E ----*/ +#define GPIO1PIN_P5E_GET ( bFM_GPIO_PDIR5_PE ) + +#define GPIO1PIN_P5E_PUT(v) ( bFM_GPIO_PDOR5_PE=(v) ) + +#define GPIO1PIN_P5E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P5E_INITIN(v) \ + : GPIO1PIN_P5E_INITOUT(v) ) + +#define GPIO1PIN_P5E_INITIN(v) do{ \ + bFM_GPIO_PCR5_PE=(v).bPullup; \ + bFM_GPIO_DDR5_PE=0u; \ + bFM_GPIO_PFR5_PE=0u; }while(0u) + +#define GPIO1PIN_P5E_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PE=(v).bInitVal; \ + bFM_GPIO_DDR5_PE=1u; \ + bFM_GPIO_PFR5_PE=0u; }while(0u) + +/*---- GPIO bit NP5E ----*/ +#define GPIO1PIN_NP5E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_PE)) ) + +#define GPIO1PIN_NP5E_PUT(v) ( bFM_GPIO_PDOR5_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP5E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP5E_INITIN(v) \ + : GPIO1PIN_NP5E_INITOUT(v) ) + +#define GPIO1PIN_NP5E_INITIN(v) do{ \ + bFM_GPIO_PCR5_PE=(v).bPullup; \ + bFM_GPIO_DDR5_PE=0u; \ + bFM_GPIO_PFR5_PE=0u; }while(0u) + +#define GPIO1PIN_NP5E_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_PE=1u; \ + bFM_GPIO_PFR5_PE=0u; }while(0u) + +/*---- GPIO bit P5F ----*/ +#define GPIO1PIN_P5F_GET ( bFM_GPIO_PDIR5_PF ) + +#define GPIO1PIN_P5F_PUT(v) ( bFM_GPIO_PDOR5_PF=(v) ) + +#define GPIO1PIN_P5F_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P5F_INITIN(v) \ + : GPIO1PIN_P5F_INITOUT(v) ) + +#define GPIO1PIN_P5F_INITIN(v) do{ \ + bFM_GPIO_PCR5_PF=(v).bPullup; \ + bFM_GPIO_DDR5_PF=0u; \ + bFM_GPIO_PFR5_PF=0u; }while(0u) + +#define GPIO1PIN_P5F_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PF=(v).bInitVal; \ + bFM_GPIO_DDR5_PF=1u; \ + bFM_GPIO_PFR5_PF=0u; }while(0u) + +/*---- GPIO bit NP5F ----*/ +#define GPIO1PIN_NP5F_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR5_PF)) ) + +#define GPIO1PIN_NP5F_PUT(v) ( bFM_GPIO_PDOR5_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP5F_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP5F_INITIN(v) \ + : GPIO1PIN_NP5F_INITOUT(v) ) + +#define GPIO1PIN_NP5F_INITIN(v) do{ \ + bFM_GPIO_PCR5_PF=(v).bPullup; \ + bFM_GPIO_DDR5_PF=0u; \ + bFM_GPIO_PFR5_PF=0u; }while(0u) + +#define GPIO1PIN_NP5F_INITOUT(v) do{ \ + bFM_GPIO_PDOR5_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR5_PF=1u; \ + bFM_GPIO_PFR5_PF=0u; }while(0u) + +/*---- GPIO bit P60 ----*/ +#define GPIO1PIN_P60_GET ( bFM_GPIO_PDIR6_P0 ) + +#define GPIO1PIN_P60_PUT(v) ( bFM_GPIO_PDOR6_P0=(v) ) + +#define GPIO1PIN_P60_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P60_INITIN(v) \ + : GPIO1PIN_P60_INITOUT(v) ) + +#define GPIO1PIN_P60_INITIN(v) do{ \ + bFM_GPIO_PCR6_P0=(v).bPullup; \ + bFM_GPIO_DDR6_P0=0u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +#define GPIO1PIN_P60_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P0=(v).bInitVal; \ + bFM_GPIO_DDR6_P0=1u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +/*---- GPIO bit NP60 ----*/ +#define GPIO1PIN_NP60_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P0)) ) + +#define GPIO1PIN_NP60_PUT(v) ( bFM_GPIO_PDOR6_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP60_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP60_INITIN(v) \ + : GPIO1PIN_NP60_INITOUT(v) ) + +#define GPIO1PIN_NP60_INITIN(v) do{ \ + bFM_GPIO_PCR6_P0=(v).bPullup; \ + bFM_GPIO_DDR6_P0=0u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +#define GPIO1PIN_NP60_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P0=1u; \ + bFM_GPIO_PFR6_P0=0u; }while(0u) + +/*---- GPIO bit P61 ----*/ +#define GPIO1PIN_P61_GET ( bFM_GPIO_PDIR6_P1 ) + +#define GPIO1PIN_P61_PUT(v) ( bFM_GPIO_PDOR6_P1=(v) ) + +#define GPIO1PIN_P61_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P61_INITIN(v) \ + : GPIO1PIN_P61_INITOUT(v) ) + +#define GPIO1PIN_P61_INITIN(v) do{ \ + bFM_GPIO_PCR6_P1=(v).bPullup; \ + bFM_GPIO_DDR6_P1=0u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +#define GPIO1PIN_P61_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P1=(v).bInitVal; \ + bFM_GPIO_DDR6_P1=1u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +/*---- GPIO bit NP61 ----*/ +#define GPIO1PIN_NP61_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P1)) ) + +#define GPIO1PIN_NP61_PUT(v) ( bFM_GPIO_PDOR6_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP61_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP61_INITIN(v) \ + : GPIO1PIN_NP61_INITOUT(v) ) + +#define GPIO1PIN_NP61_INITIN(v) do{ \ + bFM_GPIO_PCR6_P1=(v).bPullup; \ + bFM_GPIO_DDR6_P1=0u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +#define GPIO1PIN_NP61_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P1=1u; \ + bFM_GPIO_PFR6_P1=0u; }while(0u) + +/*---- GPIO bit P62 ----*/ +#define GPIO1PIN_P62_GET ( bFM_GPIO_PDIR6_P2 ) + +#define GPIO1PIN_P62_PUT(v) ( bFM_GPIO_PDOR6_P2=(v) ) + +#define GPIO1PIN_P62_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P62_INITIN(v) \ + : GPIO1PIN_P62_INITOUT(v) ) + +#define GPIO1PIN_P62_INITIN(v) do{ \ + bFM_GPIO_PCR6_P2=(v).bPullup; \ + bFM_GPIO_DDR6_P2=0u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +#define GPIO1PIN_P62_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P2=(v).bInitVal; \ + bFM_GPIO_DDR6_P2=1u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +/*---- GPIO bit NP62 ----*/ +#define GPIO1PIN_NP62_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P2)) ) + +#define GPIO1PIN_NP62_PUT(v) ( bFM_GPIO_PDOR6_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP62_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP62_INITIN(v) \ + : GPIO1PIN_NP62_INITOUT(v) ) + +#define GPIO1PIN_NP62_INITIN(v) do{ \ + bFM_GPIO_PCR6_P2=(v).bPullup; \ + bFM_GPIO_DDR6_P2=0u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +#define GPIO1PIN_NP62_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P2=1u; \ + bFM_GPIO_PFR6_P2=0u; }while(0u) + +/*---- GPIO bit P63 ----*/ +#define GPIO1PIN_P63_GET ( bFM_GPIO_PDIR6_P3 ) + +#define GPIO1PIN_P63_PUT(v) ( bFM_GPIO_PDOR6_P3=(v) ) + +#define GPIO1PIN_P63_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P63_INITIN(v) \ + : GPIO1PIN_P63_INITOUT(v) ) + +#define GPIO1PIN_P63_INITIN(v) do{ \ + bFM_GPIO_PCR6_P3=(v).bPullup; \ + bFM_GPIO_DDR6_P3=0u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +#define GPIO1PIN_P63_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P3=(v).bInitVal; \ + bFM_GPIO_DDR6_P3=1u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +/*---- GPIO bit NP63 ----*/ +#define GPIO1PIN_NP63_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P3)) ) + +#define GPIO1PIN_NP63_PUT(v) ( bFM_GPIO_PDOR6_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP63_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP63_INITIN(v) \ + : GPIO1PIN_NP63_INITOUT(v) ) + +#define GPIO1PIN_NP63_INITIN(v) do{ \ + bFM_GPIO_PCR6_P3=(v).bPullup; \ + bFM_GPIO_DDR6_P3=0u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +#define GPIO1PIN_NP63_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P3=1u; \ + bFM_GPIO_PFR6_P3=0u; }while(0u) + +/*---- GPIO bit P64 ----*/ +#define GPIO1PIN_P64_GET ( bFM_GPIO_PDIR6_P4 ) + +#define GPIO1PIN_P64_PUT(v) ( bFM_GPIO_PDOR6_P4=(v) ) + +#define GPIO1PIN_P64_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P64_INITIN(v) \ + : GPIO1PIN_P64_INITOUT(v) ) + +#define GPIO1PIN_P64_INITIN(v) do{ \ + bFM_GPIO_PCR6_P4=(v).bPullup; \ + bFM_GPIO_DDR6_P4=0u; \ + bFM_GPIO_PFR6_P4=0u; }while(0u) + +#define GPIO1PIN_P64_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P4=(v).bInitVal; \ + bFM_GPIO_DDR6_P4=1u; \ + bFM_GPIO_PFR6_P4=0u; }while(0u) + +/*---- GPIO bit NP64 ----*/ +#define GPIO1PIN_NP64_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P4)) ) + +#define GPIO1PIN_NP64_PUT(v) ( bFM_GPIO_PDOR6_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP64_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP64_INITIN(v) \ + : GPIO1PIN_NP64_INITOUT(v) ) + +#define GPIO1PIN_NP64_INITIN(v) do{ \ + bFM_GPIO_PCR6_P4=(v).bPullup; \ + bFM_GPIO_DDR6_P4=0u; \ + bFM_GPIO_PFR6_P4=0u; }while(0u) + +#define GPIO1PIN_NP64_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P4=1u; \ + bFM_GPIO_PFR6_P4=0u; }while(0u) + +/*---- GPIO bit P65 ----*/ +#define GPIO1PIN_P65_GET ( bFM_GPIO_PDIR6_P5 ) + +#define GPIO1PIN_P65_PUT(v) ( bFM_GPIO_PDOR6_P5=(v) ) + +#define GPIO1PIN_P65_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P65_INITIN(v) \ + : GPIO1PIN_P65_INITOUT(v) ) + +#define GPIO1PIN_P65_INITIN(v) do{ \ + bFM_GPIO_PCR6_P5=(v).bPullup; \ + bFM_GPIO_DDR6_P5=0u; \ + bFM_GPIO_PFR6_P5=0u; }while(0u) + +#define GPIO1PIN_P65_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P5=(v).bInitVal; \ + bFM_GPIO_DDR6_P5=1u; \ + bFM_GPIO_PFR6_P5=0u; }while(0u) + +/*---- GPIO bit NP65 ----*/ +#define GPIO1PIN_NP65_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P5)) ) + +#define GPIO1PIN_NP65_PUT(v) ( bFM_GPIO_PDOR6_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP65_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP65_INITIN(v) \ + : GPIO1PIN_NP65_INITOUT(v) ) + +#define GPIO1PIN_NP65_INITIN(v) do{ \ + bFM_GPIO_PCR6_P5=(v).bPullup; \ + bFM_GPIO_DDR6_P5=0u; \ + bFM_GPIO_PFR6_P5=0u; }while(0u) + +#define GPIO1PIN_NP65_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P5=1u; \ + bFM_GPIO_PFR6_P5=0u; }while(0u) + +/*---- GPIO bit P66 ----*/ +#define GPIO1PIN_P66_GET ( bFM_GPIO_PDIR6_P6 ) + +#define GPIO1PIN_P66_PUT(v) ( bFM_GPIO_PDOR6_P6=(v) ) + +#define GPIO1PIN_P66_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P66_INITIN(v) \ + : GPIO1PIN_P66_INITOUT(v) ) + +#define GPIO1PIN_P66_INITIN(v) do{ \ + bFM_GPIO_PCR6_P6=(v).bPullup; \ + bFM_GPIO_DDR6_P6=0u; \ + bFM_GPIO_PFR6_P6=0u; }while(0u) + +#define GPIO1PIN_P66_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P6=(v).bInitVal; \ + bFM_GPIO_DDR6_P6=1u; \ + bFM_GPIO_PFR6_P6=0u; }while(0u) + +/*---- GPIO bit NP66 ----*/ +#define GPIO1PIN_NP66_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P6)) ) + +#define GPIO1PIN_NP66_PUT(v) ( bFM_GPIO_PDOR6_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP66_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP66_INITIN(v) \ + : GPIO1PIN_NP66_INITOUT(v) ) + +#define GPIO1PIN_NP66_INITIN(v) do{ \ + bFM_GPIO_PCR6_P6=(v).bPullup; \ + bFM_GPIO_DDR6_P6=0u; \ + bFM_GPIO_PFR6_P6=0u; }while(0u) + +#define GPIO1PIN_NP66_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P6=1u; \ + bFM_GPIO_PFR6_P6=0u; }while(0u) + +/*---- GPIO bit P67 ----*/ +#define GPIO1PIN_P67_GET ( bFM_GPIO_PDIR6_P7 ) + +#define GPIO1PIN_P67_PUT(v) ( bFM_GPIO_PDOR6_P7=(v) ) + +#define GPIO1PIN_P67_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P67_INITIN(v) \ + : GPIO1PIN_P67_INITOUT(v) ) + +#define GPIO1PIN_P67_INITIN(v) do{ \ + bFM_GPIO_PCR6_P7=(v).bPullup; \ + bFM_GPIO_DDR6_P7=0u; \ + bFM_GPIO_PFR6_P7=0u; }while(0u) + +#define GPIO1PIN_P67_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P7=(v).bInitVal; \ + bFM_GPIO_DDR6_P7=1u; \ + bFM_GPIO_PFR6_P7=0u; }while(0u) + +/*---- GPIO bit NP67 ----*/ +#define GPIO1PIN_NP67_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P7)) ) + +#define GPIO1PIN_NP67_PUT(v) ( bFM_GPIO_PDOR6_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP67_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP67_INITIN(v) \ + : GPIO1PIN_NP67_INITOUT(v) ) + +#define GPIO1PIN_NP67_INITIN(v) do{ \ + bFM_GPIO_PCR6_P7=(v).bPullup; \ + bFM_GPIO_DDR6_P7=0u; \ + bFM_GPIO_PFR6_P7=0u; }while(0u) + +#define GPIO1PIN_NP67_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P7=1u; \ + bFM_GPIO_PFR6_P7=0u; }while(0u) + +/*---- GPIO bit P68 ----*/ +#define GPIO1PIN_P68_GET ( bFM_GPIO_PDIR6_P8 ) + +#define GPIO1PIN_P68_PUT(v) ( bFM_GPIO_PDOR6_P8=(v) ) + +#define GPIO1PIN_P68_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P68_INITIN(v) \ + : GPIO1PIN_P68_INITOUT(v) ) + +#define GPIO1PIN_P68_INITIN(v) do{ \ + bFM_GPIO_PCR6_P8=(v).bPullup; \ + bFM_GPIO_DDR6_P8=0u; \ + bFM_GPIO_PFR6_P8=0u; }while(0u) + +#define GPIO1PIN_P68_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P8=(v).bInitVal; \ + bFM_GPIO_DDR6_P8=1u; \ + bFM_GPIO_PFR6_P8=0u; }while(0u) + +/*---- GPIO bit NP68 ----*/ +#define GPIO1PIN_NP68_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P8)) ) + +#define GPIO1PIN_NP68_PUT(v) ( bFM_GPIO_PDOR6_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP68_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP68_INITIN(v) \ + : GPIO1PIN_NP68_INITOUT(v) ) + +#define GPIO1PIN_NP68_INITIN(v) do{ \ + bFM_GPIO_PCR6_P8=(v).bPullup; \ + bFM_GPIO_DDR6_P8=0u; \ + bFM_GPIO_PFR6_P8=0u; }while(0u) + +#define GPIO1PIN_NP68_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P8=1u; \ + bFM_GPIO_PFR6_P8=0u; }while(0u) + +/*---- GPIO bit P69 ----*/ +#define GPIO1PIN_P69_GET ( bFM_GPIO_PDIR6_P9 ) + +#define GPIO1PIN_P69_PUT(v) ( bFM_GPIO_PDOR6_P9=(v) ) + +#define GPIO1PIN_P69_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P69_INITIN(v) \ + : GPIO1PIN_P69_INITOUT(v) ) + +#define GPIO1PIN_P69_INITIN(v) do{ \ + bFM_GPIO_PCR6_P9=(v).bPullup; \ + bFM_GPIO_DDR6_P9=0u; \ + bFM_GPIO_PFR6_P9=0u; }while(0u) + +#define GPIO1PIN_P69_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P9=(v).bInitVal; \ + bFM_GPIO_DDR6_P9=1u; \ + bFM_GPIO_PFR6_P9=0u; }while(0u) + +/*---- GPIO bit NP69 ----*/ +#define GPIO1PIN_NP69_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_P9)) ) + +#define GPIO1PIN_NP69_PUT(v) ( bFM_GPIO_PDOR6_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP69_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP69_INITIN(v) \ + : GPIO1PIN_NP69_INITOUT(v) ) + +#define GPIO1PIN_NP69_INITIN(v) do{ \ + bFM_GPIO_PCR6_P9=(v).bPullup; \ + bFM_GPIO_DDR6_P9=0u; \ + bFM_GPIO_PFR6_P9=0u; }while(0u) + +#define GPIO1PIN_NP69_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_P9=1u; \ + bFM_GPIO_PFR6_P9=0u; }while(0u) + +/*---- GPIO bit P6A ----*/ +#define GPIO1PIN_P6A_GET ( bFM_GPIO_PDIR6_PA ) + +#define GPIO1PIN_P6A_PUT(v) ( bFM_GPIO_PDOR6_PA=(v) ) + +#define GPIO1PIN_P6A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P6A_INITIN(v) \ + : GPIO1PIN_P6A_INITOUT(v) ) + +#define GPIO1PIN_P6A_INITIN(v) do{ \ + bFM_GPIO_PCR6_PA=(v).bPullup; \ + bFM_GPIO_DDR6_PA=0u; \ + bFM_GPIO_PFR6_PA=0u; }while(0u) + +#define GPIO1PIN_P6A_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PA=(v).bInitVal; \ + bFM_GPIO_DDR6_PA=1u; \ + bFM_GPIO_PFR6_PA=0u; }while(0u) + +/*---- GPIO bit NP6A ----*/ +#define GPIO1PIN_NP6A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_PA)) ) + +#define GPIO1PIN_NP6A_PUT(v) ( bFM_GPIO_PDOR6_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP6A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP6A_INITIN(v) \ + : GPIO1PIN_NP6A_INITOUT(v) ) + +#define GPIO1PIN_NP6A_INITIN(v) do{ \ + bFM_GPIO_PCR6_PA=(v).bPullup; \ + bFM_GPIO_DDR6_PA=0u; \ + bFM_GPIO_PFR6_PA=0u; }while(0u) + +#define GPIO1PIN_NP6A_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_PA=1u; \ + bFM_GPIO_PFR6_PA=0u; }while(0u) + +/*---- GPIO bit P6B ----*/ +#define GPIO1PIN_P6B_GET ( bFM_GPIO_PDIR6_PB ) + +#define GPIO1PIN_P6B_PUT(v) ( bFM_GPIO_PDOR6_PB=(v) ) + +#define GPIO1PIN_P6B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P6B_INITIN(v) \ + : GPIO1PIN_P6B_INITOUT(v) ) + +#define GPIO1PIN_P6B_INITIN(v) do{ \ + bFM_GPIO_PCR6_PB=(v).bPullup; \ + bFM_GPIO_DDR6_PB=0u; \ + bFM_GPIO_PFR6_PB=0u; }while(0u) + +#define GPIO1PIN_P6B_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PB=(v).bInitVal; \ + bFM_GPIO_DDR6_PB=1u; \ + bFM_GPIO_PFR6_PB=0u; }while(0u) + +/*---- GPIO bit NP6B ----*/ +#define GPIO1PIN_NP6B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_PB)) ) + +#define GPIO1PIN_NP6B_PUT(v) ( bFM_GPIO_PDOR6_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP6B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP6B_INITIN(v) \ + : GPIO1PIN_NP6B_INITOUT(v) ) + +#define GPIO1PIN_NP6B_INITIN(v) do{ \ + bFM_GPIO_PCR6_PB=(v).bPullup; \ + bFM_GPIO_DDR6_PB=0u; \ + bFM_GPIO_PFR6_PB=0u; }while(0u) + +#define GPIO1PIN_NP6B_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_PB=1u; \ + bFM_GPIO_PFR6_PB=0u; }while(0u) + +/*---- GPIO bit P6C ----*/ +#define GPIO1PIN_P6C_GET ( bFM_GPIO_PDIR6_PC ) + +#define GPIO1PIN_P6C_PUT(v) ( bFM_GPIO_PDOR6_PC=(v) ) + +#define GPIO1PIN_P6C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P6C_INITIN(v) \ + : GPIO1PIN_P6C_INITOUT(v) ) + +#define GPIO1PIN_P6C_INITIN(v) do{ \ + bFM_GPIO_PCR6_PC=(v).bPullup; \ + bFM_GPIO_DDR6_PC=0u; \ + bFM_GPIO_PFR6_PC=0u; }while(0u) + +#define GPIO1PIN_P6C_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PC=(v).bInitVal; \ + bFM_GPIO_DDR6_PC=1u; \ + bFM_GPIO_PFR6_PC=0u; }while(0u) + +/*---- GPIO bit NP6C ----*/ +#define GPIO1PIN_NP6C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_PC)) ) + +#define GPIO1PIN_NP6C_PUT(v) ( bFM_GPIO_PDOR6_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP6C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP6C_INITIN(v) \ + : GPIO1PIN_NP6C_INITOUT(v) ) + +#define GPIO1PIN_NP6C_INITIN(v) do{ \ + bFM_GPIO_PCR6_PC=(v).bPullup; \ + bFM_GPIO_DDR6_PC=0u; \ + bFM_GPIO_PFR6_PC=0u; }while(0u) + +#define GPIO1PIN_NP6C_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_PC=1u; \ + bFM_GPIO_PFR6_PC=0u; }while(0u) + +/*---- GPIO bit P6D ----*/ +#define GPIO1PIN_P6D_GET ( bFM_GPIO_PDIR6_PD ) + +#define GPIO1PIN_P6D_PUT(v) ( bFM_GPIO_PDOR6_PD=(v) ) + +#define GPIO1PIN_P6D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P6D_INITIN(v) \ + : GPIO1PIN_P6D_INITOUT(v) ) + +#define GPIO1PIN_P6D_INITIN(v) do{ \ + bFM_GPIO_PCR6_PD=(v).bPullup; \ + bFM_GPIO_DDR6_PD=0u; \ + bFM_GPIO_PFR6_PD=0u; }while(0u) + +#define GPIO1PIN_P6D_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PD=(v).bInitVal; \ + bFM_GPIO_DDR6_PD=1u; \ + bFM_GPIO_PFR6_PD=0u; }while(0u) + +/*---- GPIO bit NP6D ----*/ +#define GPIO1PIN_NP6D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_PD)) ) + +#define GPIO1PIN_NP6D_PUT(v) ( bFM_GPIO_PDOR6_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP6D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP6D_INITIN(v) \ + : GPIO1PIN_NP6D_INITOUT(v) ) + +#define GPIO1PIN_NP6D_INITIN(v) do{ \ + bFM_GPIO_PCR6_PD=(v).bPullup; \ + bFM_GPIO_DDR6_PD=0u; \ + bFM_GPIO_PFR6_PD=0u; }while(0u) + +#define GPIO1PIN_NP6D_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_PD=1u; \ + bFM_GPIO_PFR6_PD=0u; }while(0u) + +/*---- GPIO bit P6E ----*/ +#define GPIO1PIN_P6E_GET ( bFM_GPIO_PDIR6_PE ) + +#define GPIO1PIN_P6E_PUT(v) ( bFM_GPIO_PDOR6_PE=(v) ) + +#define GPIO1PIN_P6E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P6E_INITIN(v) \ + : GPIO1PIN_P6E_INITOUT(v) ) + +#define GPIO1PIN_P6E_INITIN(v) do{ \ + bFM_GPIO_PCR6_PE=(v).bPullup; \ + bFM_GPIO_DDR6_PE=0u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +#define GPIO1PIN_P6E_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PE=(v).bInitVal; \ + bFM_GPIO_DDR6_PE=1u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +/*---- GPIO bit NP6E ----*/ +#define GPIO1PIN_NP6E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR6_PE)) ) + +#define GPIO1PIN_NP6E_PUT(v) ( bFM_GPIO_PDOR6_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP6E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP6E_INITIN(v) \ + : GPIO1PIN_NP6E_INITOUT(v) ) + +#define GPIO1PIN_NP6E_INITIN(v) do{ \ + bFM_GPIO_PCR6_PE=(v).bPullup; \ + bFM_GPIO_DDR6_PE=0u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +#define GPIO1PIN_NP6E_INITOUT(v) do{ \ + bFM_GPIO_PDOR6_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR6_PE=1u; \ + bFM_GPIO_PFR6_PE=0u; }while(0u) + +/*---- GPIO bit P70 ----*/ +#define GPIO1PIN_P70_GET ( bFM_GPIO_PDIR7_P0 ) + +#define GPIO1PIN_P70_PUT(v) ( bFM_GPIO_PDOR7_P0=(v) ) + +#define GPIO1PIN_P70_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P70_INITIN(v) \ + : GPIO1PIN_P70_INITOUT(v) ) + +#define GPIO1PIN_P70_INITIN(v) do{ \ + bFM_GPIO_PCR7_P0=(v).bPullup; \ + bFM_GPIO_DDR7_P0=0u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +#define GPIO1PIN_P70_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P0=(v).bInitVal; \ + bFM_GPIO_DDR7_P0=1u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +/*---- GPIO bit NP70 ----*/ +#define GPIO1PIN_NP70_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P0)) ) + +#define GPIO1PIN_NP70_PUT(v) ( bFM_GPIO_PDOR7_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP70_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP70_INITIN(v) \ + : GPIO1PIN_NP70_INITOUT(v) ) + +#define GPIO1PIN_NP70_INITIN(v) do{ \ + bFM_GPIO_PCR7_P0=(v).bPullup; \ + bFM_GPIO_DDR7_P0=0u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +#define GPIO1PIN_NP70_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P0=1u; \ + bFM_GPIO_PFR7_P0=0u; }while(0u) + +/*---- GPIO bit P71 ----*/ +#define GPIO1PIN_P71_GET ( bFM_GPIO_PDIR7_P1 ) + +#define GPIO1PIN_P71_PUT(v) ( bFM_GPIO_PDOR7_P1=(v) ) + +#define GPIO1PIN_P71_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P71_INITIN(v) \ + : GPIO1PIN_P71_INITOUT(v) ) + +#define GPIO1PIN_P71_INITIN(v) do{ \ + bFM_GPIO_PCR7_P1=(v).bPullup; \ + bFM_GPIO_DDR7_P1=0u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +#define GPIO1PIN_P71_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P1=(v).bInitVal; \ + bFM_GPIO_DDR7_P1=1u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +/*---- GPIO bit NP71 ----*/ +#define GPIO1PIN_NP71_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P1)) ) + +#define GPIO1PIN_NP71_PUT(v) ( bFM_GPIO_PDOR7_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP71_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP71_INITIN(v) \ + : GPIO1PIN_NP71_INITOUT(v) ) + +#define GPIO1PIN_NP71_INITIN(v) do{ \ + bFM_GPIO_PCR7_P1=(v).bPullup; \ + bFM_GPIO_DDR7_P1=0u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +#define GPIO1PIN_NP71_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P1=1u; \ + bFM_GPIO_PFR7_P1=0u; }while(0u) + +/*---- GPIO bit P72 ----*/ +#define GPIO1PIN_P72_GET ( bFM_GPIO_PDIR7_P2 ) + +#define GPIO1PIN_P72_PUT(v) ( bFM_GPIO_PDOR7_P2=(v) ) + +#define GPIO1PIN_P72_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P72_INITIN(v) \ + : GPIO1PIN_P72_INITOUT(v) ) + +#define GPIO1PIN_P72_INITIN(v) do{ \ + bFM_GPIO_PCR7_P2=(v).bPullup; \ + bFM_GPIO_DDR7_P2=0u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +#define GPIO1PIN_P72_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P2=(v).bInitVal; \ + bFM_GPIO_DDR7_P2=1u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +/*---- GPIO bit NP72 ----*/ +#define GPIO1PIN_NP72_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P2)) ) + +#define GPIO1PIN_NP72_PUT(v) ( bFM_GPIO_PDOR7_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP72_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP72_INITIN(v) \ + : GPIO1PIN_NP72_INITOUT(v) ) + +#define GPIO1PIN_NP72_INITIN(v) do{ \ + bFM_GPIO_PCR7_P2=(v).bPullup; \ + bFM_GPIO_DDR7_P2=0u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +#define GPIO1PIN_NP72_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P2=1u; \ + bFM_GPIO_PFR7_P2=0u; }while(0u) + +/*---- GPIO bit P73 ----*/ +#define GPIO1PIN_P73_GET ( bFM_GPIO_PDIR7_P3 ) + +#define GPIO1PIN_P73_PUT(v) ( bFM_GPIO_PDOR7_P3=(v) ) + +#define GPIO1PIN_P73_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P73_INITIN(v) \ + : GPIO1PIN_P73_INITOUT(v) ) + +#define GPIO1PIN_P73_INITIN(v) do{ \ + bFM_GPIO_PCR7_P3=(v).bPullup; \ + bFM_GPIO_DDR7_P3=0u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +#define GPIO1PIN_P73_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P3=(v).bInitVal; \ + bFM_GPIO_DDR7_P3=1u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +/*---- GPIO bit NP73 ----*/ +#define GPIO1PIN_NP73_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P3)) ) + +#define GPIO1PIN_NP73_PUT(v) ( bFM_GPIO_PDOR7_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP73_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP73_INITIN(v) \ + : GPIO1PIN_NP73_INITOUT(v) ) + +#define GPIO1PIN_NP73_INITIN(v) do{ \ + bFM_GPIO_PCR7_P3=(v).bPullup; \ + bFM_GPIO_DDR7_P3=0u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +#define GPIO1PIN_NP73_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P3=1u; \ + bFM_GPIO_PFR7_P3=0u; }while(0u) + +/*---- GPIO bit P74 ----*/ +#define GPIO1PIN_P74_GET ( bFM_GPIO_PDIR7_P4 ) + +#define GPIO1PIN_P74_PUT(v) ( bFM_GPIO_PDOR7_P4=(v) ) + +#define GPIO1PIN_P74_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P74_INITIN(v) \ + : GPIO1PIN_P74_INITOUT(v) ) + +#define GPIO1PIN_P74_INITIN(v) do{ \ + bFM_GPIO_PCR7_P4=(v).bPullup; \ + bFM_GPIO_DDR7_P4=0u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +#define GPIO1PIN_P74_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P4=(v).bInitVal; \ + bFM_GPIO_DDR7_P4=1u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +/*---- GPIO bit NP74 ----*/ +#define GPIO1PIN_NP74_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P4)) ) + +#define GPIO1PIN_NP74_PUT(v) ( bFM_GPIO_PDOR7_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP74_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP74_INITIN(v) \ + : GPIO1PIN_NP74_INITOUT(v) ) + +#define GPIO1PIN_NP74_INITIN(v) do{ \ + bFM_GPIO_PCR7_P4=(v).bPullup; \ + bFM_GPIO_DDR7_P4=0u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +#define GPIO1PIN_NP74_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P4=1u; \ + bFM_GPIO_PFR7_P4=0u; }while(0u) + +/*---- GPIO bit P75 ----*/ +#define GPIO1PIN_P75_GET ( bFM_GPIO_PDIR7_P5 ) + +#define GPIO1PIN_P75_PUT(v) ( bFM_GPIO_PDOR7_P5=(v) ) + +#define GPIO1PIN_P75_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P75_INITIN(v) \ + : GPIO1PIN_P75_INITOUT(v) ) + +#define GPIO1PIN_P75_INITIN(v) do{ \ + bFM_GPIO_PCR7_P5=(v).bPullup; \ + bFM_GPIO_DDR7_P5=0u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +#define GPIO1PIN_P75_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P5=(v).bInitVal; \ + bFM_GPIO_DDR7_P5=1u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +/*---- GPIO bit NP75 ----*/ +#define GPIO1PIN_NP75_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P5)) ) + +#define GPIO1PIN_NP75_PUT(v) ( bFM_GPIO_PDOR7_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP75_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP75_INITIN(v) \ + : GPIO1PIN_NP75_INITOUT(v) ) + +#define GPIO1PIN_NP75_INITIN(v) do{ \ + bFM_GPIO_PCR7_P5=(v).bPullup; \ + bFM_GPIO_DDR7_P5=0u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +#define GPIO1PIN_NP75_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P5=1u; \ + bFM_GPIO_PFR7_P5=0u; }while(0u) + +/*---- GPIO bit P76 ----*/ +#define GPIO1PIN_P76_GET ( bFM_GPIO_PDIR7_P6 ) + +#define GPIO1PIN_P76_PUT(v) ( bFM_GPIO_PDOR7_P6=(v) ) + +#define GPIO1PIN_P76_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P76_INITIN(v) \ + : GPIO1PIN_P76_INITOUT(v) ) + +#define GPIO1PIN_P76_INITIN(v) do{ \ + bFM_GPIO_PCR7_P6=(v).bPullup; \ + bFM_GPIO_DDR7_P6=0u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +#define GPIO1PIN_P76_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P6=(v).bInitVal; \ + bFM_GPIO_DDR7_P6=1u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +/*---- GPIO bit NP76 ----*/ +#define GPIO1PIN_NP76_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P6)) ) + +#define GPIO1PIN_NP76_PUT(v) ( bFM_GPIO_PDOR7_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP76_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP76_INITIN(v) \ + : GPIO1PIN_NP76_INITOUT(v) ) + +#define GPIO1PIN_NP76_INITIN(v) do{ \ + bFM_GPIO_PCR7_P6=(v).bPullup; \ + bFM_GPIO_DDR7_P6=0u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +#define GPIO1PIN_NP76_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P6=1u; \ + bFM_GPIO_PFR7_P6=0u; }while(0u) + +/*---- GPIO bit P77 ----*/ +#define GPIO1PIN_P77_GET ( bFM_GPIO_PDIR7_P7 ) + +#define GPIO1PIN_P77_PUT(v) ( bFM_GPIO_PDOR7_P7=(v) ) + +#define GPIO1PIN_P77_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P77_INITIN(v) \ + : GPIO1PIN_P77_INITOUT(v) ) + +#define GPIO1PIN_P77_INITIN(v) do{ \ + bFM_GPIO_PCR7_P7=(v).bPullup; \ + bFM_GPIO_DDR7_P7=0u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +#define GPIO1PIN_P77_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P7=(v).bInitVal; \ + bFM_GPIO_DDR7_P7=1u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +/*---- GPIO bit NP77 ----*/ +#define GPIO1PIN_NP77_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P7)) ) + +#define GPIO1PIN_NP77_PUT(v) ( bFM_GPIO_PDOR7_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP77_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP77_INITIN(v) \ + : GPIO1PIN_NP77_INITOUT(v) ) + +#define GPIO1PIN_NP77_INITIN(v) do{ \ + bFM_GPIO_PCR7_P7=(v).bPullup; \ + bFM_GPIO_DDR7_P7=0u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +#define GPIO1PIN_NP77_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P7=1u; \ + bFM_GPIO_PFR7_P7=0u; }while(0u) + +/*---- GPIO bit P78 ----*/ +#define GPIO1PIN_P78_GET ( bFM_GPIO_PDIR7_P8 ) + +#define GPIO1PIN_P78_PUT(v) ( bFM_GPIO_PDOR7_P8=(v) ) + +#define GPIO1PIN_P78_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P78_INITIN(v) \ + : GPIO1PIN_P78_INITOUT(v) ) + +#define GPIO1PIN_P78_INITIN(v) do{ \ + bFM_GPIO_PCR7_P8=(v).bPullup; \ + bFM_GPIO_DDR7_P8=0u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +#define GPIO1PIN_P78_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P8=(v).bInitVal; \ + bFM_GPIO_DDR7_P8=1u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +/*---- GPIO bit NP78 ----*/ +#define GPIO1PIN_NP78_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P8)) ) + +#define GPIO1PIN_NP78_PUT(v) ( bFM_GPIO_PDOR7_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP78_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP78_INITIN(v) \ + : GPIO1PIN_NP78_INITOUT(v) ) + +#define GPIO1PIN_NP78_INITIN(v) do{ \ + bFM_GPIO_PCR7_P8=(v).bPullup; \ + bFM_GPIO_DDR7_P8=0u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +#define GPIO1PIN_NP78_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P8=1u; \ + bFM_GPIO_PFR7_P8=0u; }while(0u) + +/*---- GPIO bit P79 ----*/ +#define GPIO1PIN_P79_GET ( bFM_GPIO_PDIR7_P9 ) + +#define GPIO1PIN_P79_PUT(v) ( bFM_GPIO_PDOR7_P9=(v) ) + +#define GPIO1PIN_P79_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P79_INITIN(v) \ + : GPIO1PIN_P79_INITOUT(v) ) + +#define GPIO1PIN_P79_INITIN(v) do{ \ + bFM_GPIO_PCR7_P9=(v).bPullup; \ + bFM_GPIO_DDR7_P9=0u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +#define GPIO1PIN_P79_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P9=(v).bInitVal; \ + bFM_GPIO_DDR7_P9=1u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +/*---- GPIO bit NP79 ----*/ +#define GPIO1PIN_NP79_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_P9)) ) + +#define GPIO1PIN_NP79_PUT(v) ( bFM_GPIO_PDOR7_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP79_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP79_INITIN(v) \ + : GPIO1PIN_NP79_INITOUT(v) ) + +#define GPIO1PIN_NP79_INITIN(v) do{ \ + bFM_GPIO_PCR7_P9=(v).bPullup; \ + bFM_GPIO_DDR7_P9=0u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +#define GPIO1PIN_NP79_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_P9=1u; \ + bFM_GPIO_PFR7_P9=0u; }while(0u) + +/*---- GPIO bit P7A ----*/ +#define GPIO1PIN_P7A_GET ( bFM_GPIO_PDIR7_PA ) + +#define GPIO1PIN_P7A_PUT(v) ( bFM_GPIO_PDOR7_PA=(v) ) + +#define GPIO1PIN_P7A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7A_INITIN(v) \ + : GPIO1PIN_P7A_INITOUT(v) ) + +#define GPIO1PIN_P7A_INITIN(v) do{ \ + bFM_GPIO_PCR7_PA=(v).bPullup; \ + bFM_GPIO_DDR7_PA=0u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +#define GPIO1PIN_P7A_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PA=(v).bInitVal; \ + bFM_GPIO_DDR7_PA=1u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +/*---- GPIO bit NP7A ----*/ +#define GPIO1PIN_NP7A_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PA)) ) + +#define GPIO1PIN_NP7A_PUT(v) ( bFM_GPIO_PDOR7_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7A_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7A_INITIN(v) \ + : GPIO1PIN_NP7A_INITOUT(v) ) + +#define GPIO1PIN_NP7A_INITIN(v) do{ \ + bFM_GPIO_PCR7_PA=(v).bPullup; \ + bFM_GPIO_DDR7_PA=0u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +#define GPIO1PIN_NP7A_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PA=1u; \ + bFM_GPIO_PFR7_PA=0u; }while(0u) + +/*---- GPIO bit P7B ----*/ +#define GPIO1PIN_P7B_GET ( bFM_GPIO_PDIR7_PB ) + +#define GPIO1PIN_P7B_PUT(v) ( bFM_GPIO_PDOR7_PB=(v) ) + +#define GPIO1PIN_P7B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7B_INITIN(v) \ + : GPIO1PIN_P7B_INITOUT(v) ) + +#define GPIO1PIN_P7B_INITIN(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PB=(v).bPullup; \ + bFM_GPIO_DDR7_PB=0u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +#define GPIO1PIN_P7B_INITOUT(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PB=(v).bInitVal; \ + bFM_GPIO_DDR7_PB=1u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +/*---- GPIO bit NP7B ----*/ +#define GPIO1PIN_NP7B_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PB)) ) + +#define GPIO1PIN_NP7B_PUT(v) ( bFM_GPIO_PDOR7_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7B_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7B_INITIN(v) \ + : GPIO1PIN_NP7B_INITOUT(v) ) + +#define GPIO1PIN_NP7B_INITIN(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PB=(v).bPullup; \ + bFM_GPIO_DDR7_PB=0u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +#define GPIO1PIN_NP7B_INITOUT(v) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PB=1u; \ + bFM_GPIO_PFR7_PB=0u; }while(0u) + +/*---- GPIO bit P7C ----*/ +#define GPIO1PIN_P7C_GET ( bFM_GPIO_PDIR7_PC ) + +#define GPIO1PIN_P7C_PUT(v) ( bFM_GPIO_PDOR7_PC=(v) ) + +#define GPIO1PIN_P7C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7C_INITIN(v) \ + : GPIO1PIN_P7C_INITOUT(v) ) + +#define GPIO1PIN_P7C_INITIN(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PC=(v).bPullup; \ + bFM_GPIO_DDR7_PC=0u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +#define GPIO1PIN_P7C_INITOUT(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PC=(v).bInitVal; \ + bFM_GPIO_DDR7_PC=1u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +/*---- GPIO bit NP7C ----*/ +#define GPIO1PIN_NP7C_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PC)) ) + +#define GPIO1PIN_NP7C_PUT(v) ( bFM_GPIO_PDOR7_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7C_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7C_INITIN(v) \ + : GPIO1PIN_NP7C_INITOUT(v) ) + +#define GPIO1PIN_NP7C_INITIN(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PCR7_PC=(v).bPullup; \ + bFM_GPIO_DDR7_PC=0u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +#define GPIO1PIN_NP7C_INITOUT(v) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + bFM_GPIO_PDOR7_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PC=1u; \ + bFM_GPIO_PFR7_PC=0u; }while(0u) + +/*---- GPIO bit P7D ----*/ +#define GPIO1PIN_P7D_GET ( bFM_GPIO_PDIR7_PD ) + +#define GPIO1PIN_P7D_PUT(v) ( bFM_GPIO_PDOR7_PD=(v) ) + +#define GPIO1PIN_P7D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7D_INITIN(v) \ + : GPIO1PIN_P7D_INITOUT(v) ) + +#define GPIO1PIN_P7D_INITIN(v) do{ \ + bFM_GPIO_PCR7_PD=(v).bPullup; \ + bFM_GPIO_DDR7_PD=0u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +#define GPIO1PIN_P7D_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PD=(v).bInitVal; \ + bFM_GPIO_DDR7_PD=1u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +/*---- GPIO bit NP7D ----*/ +#define GPIO1PIN_NP7D_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PD)) ) + +#define GPIO1PIN_NP7D_PUT(v) ( bFM_GPIO_PDOR7_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7D_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7D_INITIN(v) \ + : GPIO1PIN_NP7D_INITOUT(v) ) + +#define GPIO1PIN_NP7D_INITIN(v) do{ \ + bFM_GPIO_PCR7_PD=(v).bPullup; \ + bFM_GPIO_DDR7_PD=0u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +#define GPIO1PIN_NP7D_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PD=1u; \ + bFM_GPIO_PFR7_PD=0u; }while(0u) + +/*---- GPIO bit P7E ----*/ +#define GPIO1PIN_P7E_GET ( bFM_GPIO_PDIR7_PE ) + +#define GPIO1PIN_P7E_PUT(v) ( bFM_GPIO_PDOR7_PE=(v) ) + +#define GPIO1PIN_P7E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P7E_INITIN(v) \ + : GPIO1PIN_P7E_INITOUT(v) ) + +#define GPIO1PIN_P7E_INITIN(v) do{ \ + bFM_GPIO_PCR7_PE=(v).bPullup; \ + bFM_GPIO_DDR7_PE=0u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +#define GPIO1PIN_P7E_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PE=(v).bInitVal; \ + bFM_GPIO_DDR7_PE=1u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +/*---- GPIO bit NP7E ----*/ +#define GPIO1PIN_NP7E_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR7_PE)) ) + +#define GPIO1PIN_NP7E_PUT(v) ( bFM_GPIO_PDOR7_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP7E_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP7E_INITIN(v) \ + : GPIO1PIN_NP7E_INITOUT(v) ) + +#define GPIO1PIN_NP7E_INITIN(v) do{ \ + bFM_GPIO_PCR7_PE=(v).bPullup; \ + bFM_GPIO_DDR7_PE=0u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +#define GPIO1PIN_NP7E_INITOUT(v) do{ \ + bFM_GPIO_PDOR7_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR7_PE=1u; \ + bFM_GPIO_PFR7_PE=0u; }while(0u) + +/*---- GPIO bit P80 ----*/ +#define GPIO1PIN_P80_GET ( bFM_GPIO_PDIR8_P0 ) + +#define GPIO1PIN_P80_PUT(v) ( bFM_GPIO_PDOR8_P0=(v) ) + +#define GPIO1PIN_P80_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P80_INITIN(v) \ + : GPIO1PIN_P80_INITOUT(v) ) + +#define GPIO1PIN_P80_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P0=0u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +#define GPIO1PIN_P80_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P0=(v).bInitVal; \ + bFM_GPIO_DDR8_P0=1u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +/*---- GPIO bit NP80 ----*/ +#define GPIO1PIN_NP80_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P0)) ) + +#define GPIO1PIN_NP80_PUT(v) ( bFM_GPIO_PDOR8_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP80_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP80_INITIN(v) \ + : GPIO1PIN_NP80_INITOUT(v) ) + +#define GPIO1PIN_NP80_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P0=0u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +#define GPIO1PIN_NP80_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P0=1u; \ + bFM_GPIO_PFR8_P0=0u; }while(0u) + +/*---- GPIO bit P81 ----*/ +#define GPIO1PIN_P81_GET ( bFM_GPIO_PDIR8_P1 ) + +#define GPIO1PIN_P81_PUT(v) ( bFM_GPIO_PDOR8_P1=(v) ) + +#define GPIO1PIN_P81_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P81_INITIN(v) \ + : GPIO1PIN_P81_INITOUT(v) ) + +#define GPIO1PIN_P81_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P1=0u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +#define GPIO1PIN_P81_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P1=(v).bInitVal; \ + bFM_GPIO_DDR8_P1=1u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +/*---- GPIO bit NP81 ----*/ +#define GPIO1PIN_NP81_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P1)) ) + +#define GPIO1PIN_NP81_PUT(v) ( bFM_GPIO_PDOR8_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP81_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP81_INITIN(v) \ + : GPIO1PIN_NP81_INITOUT(v) ) + +#define GPIO1PIN_NP81_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_DDR8_P1=0u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +#define GPIO1PIN_NP81_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB0C=0u; \ + bFM_GPIO_PDOR8_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P1=1u; \ + bFM_GPIO_PFR8_P1=0u; }while(0u) + +/*---- GPIO bit P82 ----*/ +#define GPIO1PIN_P82_GET ( bFM_GPIO_PDIR8_P2 ) + +#define GPIO1PIN_P82_PUT(v) ( bFM_GPIO_PDOR8_P2=(v) ) + +#define GPIO1PIN_P82_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P82_INITIN(v) \ + : GPIO1PIN_P82_INITOUT(v) ) + +#define GPIO1PIN_P82_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P2=0u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +#define GPIO1PIN_P82_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P2=(v).bInitVal; \ + bFM_GPIO_DDR8_P2=1u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +/*---- GPIO bit NP82 ----*/ +#define GPIO1PIN_NP82_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P2)) ) + +#define GPIO1PIN_NP82_PUT(v) ( bFM_GPIO_PDOR8_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP82_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP82_INITIN(v) \ + : GPIO1PIN_NP82_INITOUT(v) ) + +#define GPIO1PIN_NP82_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P2=0u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +#define GPIO1PIN_NP82_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P2=1u; \ + bFM_GPIO_PFR8_P2=0u; }while(0u) + +/*---- GPIO bit P83 ----*/ +#define GPIO1PIN_P83_GET ( bFM_GPIO_PDIR8_P3 ) + +#define GPIO1PIN_P83_PUT(v) ( bFM_GPIO_PDOR8_P3=(v) ) + +#define GPIO1PIN_P83_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P83_INITIN(v) \ + : GPIO1PIN_P83_INITOUT(v) ) + +#define GPIO1PIN_P83_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P3=0u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +#define GPIO1PIN_P83_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P3=(v).bInitVal; \ + bFM_GPIO_DDR8_P3=1u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +/*---- GPIO bit NP83 ----*/ +#define GPIO1PIN_NP83_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR8_P3)) ) + +#define GPIO1PIN_NP83_PUT(v) ( bFM_GPIO_PDOR8_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP83_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP83_INITIN(v) \ + : GPIO1PIN_NP83_INITOUT(v) ) + +#define GPIO1PIN_NP83_INITIN(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_DDR8_P3=0u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +#define GPIO1PIN_NP83_INITOUT(v) do{ \ + bFM_GPIO_SPSR_USB1C=0u; \ + bFM_GPIO_PDOR8_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR8_P3=1u; \ + bFM_GPIO_PFR8_P3=0u; }while(0u) + +/*---- GPIO bit P90 ----*/ +#define GPIO1PIN_P90_GET ( bFM_GPIO_PDIR9_P0 ) + +#define GPIO1PIN_P90_PUT(v) ( bFM_GPIO_PDOR9_P0=(v) ) + +#define GPIO1PIN_P90_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P90_INITIN(v) \ + : GPIO1PIN_P90_INITOUT(v) ) + +#define GPIO1PIN_P90_INITIN(v) do{ \ + bFM_GPIO_PCR9_P0=(v).bPullup; \ + bFM_GPIO_DDR9_P0=0u; \ + bFM_GPIO_PFR9_P0=0u; }while(0u) + +#define GPIO1PIN_P90_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P0=(v).bInitVal; \ + bFM_GPIO_DDR9_P0=1u; \ + bFM_GPIO_PFR9_P0=0u; }while(0u) + +/*---- GPIO bit NP90 ----*/ +#define GPIO1PIN_NP90_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P0)) ) + +#define GPIO1PIN_NP90_PUT(v) ( bFM_GPIO_PDOR9_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP90_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP90_INITIN(v) \ + : GPIO1PIN_NP90_INITOUT(v) ) + +#define GPIO1PIN_NP90_INITIN(v) do{ \ + bFM_GPIO_PCR9_P0=(v).bPullup; \ + bFM_GPIO_DDR9_P0=0u; \ + bFM_GPIO_PFR9_P0=0u; }while(0u) + +#define GPIO1PIN_NP90_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P0=1u; \ + bFM_GPIO_PFR9_P0=0u; }while(0u) + +/*---- GPIO bit P91 ----*/ +#define GPIO1PIN_P91_GET ( bFM_GPIO_PDIR9_P1 ) + +#define GPIO1PIN_P91_PUT(v) ( bFM_GPIO_PDOR9_P1=(v) ) + +#define GPIO1PIN_P91_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P91_INITIN(v) \ + : GPIO1PIN_P91_INITOUT(v) ) + +#define GPIO1PIN_P91_INITIN(v) do{ \ + bFM_GPIO_PCR9_P1=(v).bPullup; \ + bFM_GPIO_DDR9_P1=0u; \ + bFM_GPIO_PFR9_P1=0u; }while(0u) + +#define GPIO1PIN_P91_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P1=(v).bInitVal; \ + bFM_GPIO_DDR9_P1=1u; \ + bFM_GPIO_PFR9_P1=0u; }while(0u) + +/*---- GPIO bit NP91 ----*/ +#define GPIO1PIN_NP91_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P1)) ) + +#define GPIO1PIN_NP91_PUT(v) ( bFM_GPIO_PDOR9_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP91_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP91_INITIN(v) \ + : GPIO1PIN_NP91_INITOUT(v) ) + +#define GPIO1PIN_NP91_INITIN(v) do{ \ + bFM_GPIO_PCR9_P1=(v).bPullup; \ + bFM_GPIO_DDR9_P1=0u; \ + bFM_GPIO_PFR9_P1=0u; }while(0u) + +#define GPIO1PIN_NP91_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P1=1u; \ + bFM_GPIO_PFR9_P1=0u; }while(0u) + +/*---- GPIO bit P92 ----*/ +#define GPIO1PIN_P92_GET ( bFM_GPIO_PDIR9_P2 ) + +#define GPIO1PIN_P92_PUT(v) ( bFM_GPIO_PDOR9_P2=(v) ) + +#define GPIO1PIN_P92_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P92_INITIN(v) \ + : GPIO1PIN_P92_INITOUT(v) ) + +#define GPIO1PIN_P92_INITIN(v) do{ \ + bFM_GPIO_PCR9_P2=(v).bPullup; \ + bFM_GPIO_DDR9_P2=0u; \ + bFM_GPIO_PFR9_P2=0u; }while(0u) + +#define GPIO1PIN_P92_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P2=(v).bInitVal; \ + bFM_GPIO_DDR9_P2=1u; \ + bFM_GPIO_PFR9_P2=0u; }while(0u) + +/*---- GPIO bit NP92 ----*/ +#define GPIO1PIN_NP92_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P2)) ) + +#define GPIO1PIN_NP92_PUT(v) ( bFM_GPIO_PDOR9_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP92_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP92_INITIN(v) \ + : GPIO1PIN_NP92_INITOUT(v) ) + +#define GPIO1PIN_NP92_INITIN(v) do{ \ + bFM_GPIO_PCR9_P2=(v).bPullup; \ + bFM_GPIO_DDR9_P2=0u; \ + bFM_GPIO_PFR9_P2=0u; }while(0u) + +#define GPIO1PIN_NP92_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P2=1u; \ + bFM_GPIO_PFR9_P2=0u; }while(0u) + +/*---- GPIO bit P93 ----*/ +#define GPIO1PIN_P93_GET ( bFM_GPIO_PDIR9_P3 ) + +#define GPIO1PIN_P93_PUT(v) ( bFM_GPIO_PDOR9_P3=(v) ) + +#define GPIO1PIN_P93_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P93_INITIN(v) \ + : GPIO1PIN_P93_INITOUT(v) ) + +#define GPIO1PIN_P93_INITIN(v) do{ \ + bFM_GPIO_PCR9_P3=(v).bPullup; \ + bFM_GPIO_DDR9_P3=0u; \ + bFM_GPIO_PFR9_P3=0u; }while(0u) + +#define GPIO1PIN_P93_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P3=(v).bInitVal; \ + bFM_GPIO_DDR9_P3=1u; \ + bFM_GPIO_PFR9_P3=0u; }while(0u) + +/*---- GPIO bit NP93 ----*/ +#define GPIO1PIN_NP93_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P3)) ) + +#define GPIO1PIN_NP93_PUT(v) ( bFM_GPIO_PDOR9_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP93_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP93_INITIN(v) \ + : GPIO1PIN_NP93_INITOUT(v) ) + +#define GPIO1PIN_NP93_INITIN(v) do{ \ + bFM_GPIO_PCR9_P3=(v).bPullup; \ + bFM_GPIO_DDR9_P3=0u; \ + bFM_GPIO_PFR9_P3=0u; }while(0u) + +#define GPIO1PIN_NP93_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P3=1u; \ + bFM_GPIO_PFR9_P3=0u; }while(0u) + +/*---- GPIO bit P94 ----*/ +#define GPIO1PIN_P94_GET ( bFM_GPIO_PDIR9_P4 ) + +#define GPIO1PIN_P94_PUT(v) ( bFM_GPIO_PDOR9_P4=(v) ) + +#define GPIO1PIN_P94_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P94_INITIN(v) \ + : GPIO1PIN_P94_INITOUT(v) ) + +#define GPIO1PIN_P94_INITIN(v) do{ \ + bFM_GPIO_PCR9_P4=(v).bPullup; \ + bFM_GPIO_DDR9_P4=0u; \ + bFM_GPIO_PFR9_P4=0u; }while(0u) + +#define GPIO1PIN_P94_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P4=(v).bInitVal; \ + bFM_GPIO_DDR9_P4=1u; \ + bFM_GPIO_PFR9_P4=0u; }while(0u) + +/*---- GPIO bit NP94 ----*/ +#define GPIO1PIN_NP94_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P4)) ) + +#define GPIO1PIN_NP94_PUT(v) ( bFM_GPIO_PDOR9_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP94_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP94_INITIN(v) \ + : GPIO1PIN_NP94_INITOUT(v) ) + +#define GPIO1PIN_NP94_INITIN(v) do{ \ + bFM_GPIO_PCR9_P4=(v).bPullup; \ + bFM_GPIO_DDR9_P4=0u; \ + bFM_GPIO_PFR9_P4=0u; }while(0u) + +#define GPIO1PIN_NP94_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P4=1u; \ + bFM_GPIO_PFR9_P4=0u; }while(0u) + +/*---- GPIO bit P95 ----*/ +#define GPIO1PIN_P95_GET ( bFM_GPIO_PDIR9_P5 ) + +#define GPIO1PIN_P95_PUT(v) ( bFM_GPIO_PDOR9_P5=(v) ) + +#define GPIO1PIN_P95_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P95_INITIN(v) \ + : GPIO1PIN_P95_INITOUT(v) ) + +#define GPIO1PIN_P95_INITIN(v) do{ \ + bFM_GPIO_PCR9_P5=(v).bPullup; \ + bFM_GPIO_DDR9_P5=0u; \ + bFM_GPIO_PFR9_P5=0u; }while(0u) + +#define GPIO1PIN_P95_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P5=(v).bInitVal; \ + bFM_GPIO_DDR9_P5=1u; \ + bFM_GPIO_PFR9_P5=0u; }while(0u) + +/*---- GPIO bit NP95 ----*/ +#define GPIO1PIN_NP95_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P5)) ) + +#define GPIO1PIN_NP95_PUT(v) ( bFM_GPIO_PDOR9_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP95_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP95_INITIN(v) \ + : GPIO1PIN_NP95_INITOUT(v) ) + +#define GPIO1PIN_NP95_INITIN(v) do{ \ + bFM_GPIO_PCR9_P5=(v).bPullup; \ + bFM_GPIO_DDR9_P5=0u; \ + bFM_GPIO_PFR9_P5=0u; }while(0u) + +#define GPIO1PIN_NP95_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P5=1u; \ + bFM_GPIO_PFR9_P5=0u; }while(0u) + +/*---- GPIO bit P96 ----*/ +#define GPIO1PIN_P96_GET ( bFM_GPIO_PDIR9_P6 ) + +#define GPIO1PIN_P96_PUT(v) ( bFM_GPIO_PDOR9_P6=(v) ) + +#define GPIO1PIN_P96_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P96_INITIN(v) \ + : GPIO1PIN_P96_INITOUT(v) ) + +#define GPIO1PIN_P96_INITIN(v) do{ \ + bFM_GPIO_PCR9_P6=(v).bPullup; \ + bFM_GPIO_DDR9_P6=0u; \ + bFM_GPIO_PFR9_P6=0u; }while(0u) + +#define GPIO1PIN_P96_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P6=(v).bInitVal; \ + bFM_GPIO_DDR9_P6=1u; \ + bFM_GPIO_PFR9_P6=0u; }while(0u) + +/*---- GPIO bit NP96 ----*/ +#define GPIO1PIN_NP96_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P6)) ) + +#define GPIO1PIN_NP96_PUT(v) ( bFM_GPIO_PDOR9_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP96_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP96_INITIN(v) \ + : GPIO1PIN_NP96_INITOUT(v) ) + +#define GPIO1PIN_NP96_INITIN(v) do{ \ + bFM_GPIO_PCR9_P6=(v).bPullup; \ + bFM_GPIO_DDR9_P6=0u; \ + bFM_GPIO_PFR9_P6=0u; }while(0u) + +#define GPIO1PIN_NP96_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P6=1u; \ + bFM_GPIO_PFR9_P6=0u; }while(0u) + +/*---- GPIO bit P97 ----*/ +#define GPIO1PIN_P97_GET ( bFM_GPIO_PDIR9_P7 ) + +#define GPIO1PIN_P97_PUT(v) ( bFM_GPIO_PDOR9_P7=(v) ) + +#define GPIO1PIN_P97_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_P97_INITIN(v) \ + : GPIO1PIN_P97_INITOUT(v) ) + +#define GPIO1PIN_P97_INITIN(v) do{ \ + bFM_GPIO_PCR9_P7=(v).bPullup; \ + bFM_GPIO_DDR9_P7=0u; \ + bFM_GPIO_PFR9_P7=0u; }while(0u) + +#define GPIO1PIN_P97_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P7=(v).bInitVal; \ + bFM_GPIO_DDR9_P7=1u; \ + bFM_GPIO_PFR9_P7=0u; }while(0u) + +/*---- GPIO bit NP97 ----*/ +#define GPIO1PIN_NP97_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIR9_P7)) ) + +#define GPIO1PIN_NP97_PUT(v) ( bFM_GPIO_PDOR9_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NP97_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NP97_INITIN(v) \ + : GPIO1PIN_NP97_INITOUT(v) ) + +#define GPIO1PIN_NP97_INITIN(v) do{ \ + bFM_GPIO_PCR9_P7=(v).bPullup; \ + bFM_GPIO_DDR9_P7=0u; \ + bFM_GPIO_PFR9_P7=0u; }while(0u) + +#define GPIO1PIN_NP97_INITOUT(v) do{ \ + bFM_GPIO_PDOR9_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDR9_P7=1u; \ + bFM_GPIO_PFR9_P7=0u; }while(0u) + +/*---- GPIO bit PA0 ----*/ +#define GPIO1PIN_PA0_GET ( bFM_GPIO_PDIRA_P0 ) + +#define GPIO1PIN_PA0_PUT(v) ( bFM_GPIO_PDORA_P0=(v) ) + +#define GPIO1PIN_PA0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA0_INITIN(v) \ + : GPIO1PIN_PA0_INITOUT(v) ) + +#define GPIO1PIN_PA0_INITIN(v) do{ \ + bFM_GPIO_PCRA_P0=(v).bPullup; \ + bFM_GPIO_DDRA_P0=0u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +#define GPIO1PIN_PA0_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P0=(v).bInitVal; \ + bFM_GPIO_DDRA_P0=1u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +/*---- GPIO bit NPA0 ----*/ +#define GPIO1PIN_NPA0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P0)) ) + +#define GPIO1PIN_NPA0_PUT(v) ( bFM_GPIO_PDORA_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA0_INITIN(v) \ + : GPIO1PIN_NPA0_INITOUT(v) ) + +#define GPIO1PIN_NPA0_INITIN(v) do{ \ + bFM_GPIO_PCRA_P0=(v).bPullup; \ + bFM_GPIO_DDRA_P0=0u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +#define GPIO1PIN_NPA0_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P0=1u; \ + bFM_GPIO_PFRA_P0=0u; }while(0u) + +/*---- GPIO bit PA1 ----*/ +#define GPIO1PIN_PA1_GET ( bFM_GPIO_PDIRA_P1 ) + +#define GPIO1PIN_PA1_PUT(v) ( bFM_GPIO_PDORA_P1=(v) ) + +#define GPIO1PIN_PA1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA1_INITIN(v) \ + : GPIO1PIN_PA1_INITOUT(v) ) + +#define GPIO1PIN_PA1_INITIN(v) do{ \ + bFM_GPIO_PCRA_P1=(v).bPullup; \ + bFM_GPIO_DDRA_P1=0u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +#define GPIO1PIN_PA1_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P1=(v).bInitVal; \ + bFM_GPIO_DDRA_P1=1u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +/*---- GPIO bit NPA1 ----*/ +#define GPIO1PIN_NPA1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P1)) ) + +#define GPIO1PIN_NPA1_PUT(v) ( bFM_GPIO_PDORA_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA1_INITIN(v) \ + : GPIO1PIN_NPA1_INITOUT(v) ) + +#define GPIO1PIN_NPA1_INITIN(v) do{ \ + bFM_GPIO_PCRA_P1=(v).bPullup; \ + bFM_GPIO_DDRA_P1=0u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +#define GPIO1PIN_NPA1_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P1=1u; \ + bFM_GPIO_PFRA_P1=0u; }while(0u) + +/*---- GPIO bit PA2 ----*/ +#define GPIO1PIN_PA2_GET ( bFM_GPIO_PDIRA_P2 ) + +#define GPIO1PIN_PA2_PUT(v) ( bFM_GPIO_PDORA_P2=(v) ) + +#define GPIO1PIN_PA2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA2_INITIN(v) \ + : GPIO1PIN_PA2_INITOUT(v) ) + +#define GPIO1PIN_PA2_INITIN(v) do{ \ + bFM_GPIO_PCRA_P2=(v).bPullup; \ + bFM_GPIO_DDRA_P2=0u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +#define GPIO1PIN_PA2_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P2=(v).bInitVal; \ + bFM_GPIO_DDRA_P2=1u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +/*---- GPIO bit NPA2 ----*/ +#define GPIO1PIN_NPA2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P2)) ) + +#define GPIO1PIN_NPA2_PUT(v) ( bFM_GPIO_PDORA_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA2_INITIN(v) \ + : GPIO1PIN_NPA2_INITOUT(v) ) + +#define GPIO1PIN_NPA2_INITIN(v) do{ \ + bFM_GPIO_PCRA_P2=(v).bPullup; \ + bFM_GPIO_DDRA_P2=0u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +#define GPIO1PIN_NPA2_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P2=1u; \ + bFM_GPIO_PFRA_P2=0u; }while(0u) + +/*---- GPIO bit PA3 ----*/ +#define GPIO1PIN_PA3_GET ( bFM_GPIO_PDIRA_P3 ) + +#define GPIO1PIN_PA3_PUT(v) ( bFM_GPIO_PDORA_P3=(v) ) + +#define GPIO1PIN_PA3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA3_INITIN(v) \ + : GPIO1PIN_PA3_INITOUT(v) ) + +#define GPIO1PIN_PA3_INITIN(v) do{ \ + bFM_GPIO_PCRA_P3=(v).bPullup; \ + bFM_GPIO_DDRA_P3=0u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +#define GPIO1PIN_PA3_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P3=(v).bInitVal; \ + bFM_GPIO_DDRA_P3=1u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +/*---- GPIO bit NPA3 ----*/ +#define GPIO1PIN_NPA3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P3)) ) + +#define GPIO1PIN_NPA3_PUT(v) ( bFM_GPIO_PDORA_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA3_INITIN(v) \ + : GPIO1PIN_NPA3_INITOUT(v) ) + +#define GPIO1PIN_NPA3_INITIN(v) do{ \ + bFM_GPIO_PCRA_P3=(v).bPullup; \ + bFM_GPIO_DDRA_P3=0u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +#define GPIO1PIN_NPA3_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P3=1u; \ + bFM_GPIO_PFRA_P3=0u; }while(0u) + +/*---- GPIO bit PA4 ----*/ +#define GPIO1PIN_PA4_GET ( bFM_GPIO_PDIRA_P4 ) + +#define GPIO1PIN_PA4_PUT(v) ( bFM_GPIO_PDORA_P4=(v) ) + +#define GPIO1PIN_PA4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA4_INITIN(v) \ + : GPIO1PIN_PA4_INITOUT(v) ) + +#define GPIO1PIN_PA4_INITIN(v) do{ \ + bFM_GPIO_PCRA_P4=(v).bPullup; \ + bFM_GPIO_DDRA_P4=0u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +#define GPIO1PIN_PA4_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P4=(v).bInitVal; \ + bFM_GPIO_DDRA_P4=1u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +/*---- GPIO bit NPA4 ----*/ +#define GPIO1PIN_NPA4_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P4)) ) + +#define GPIO1PIN_NPA4_PUT(v) ( bFM_GPIO_PDORA_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA4_INITIN(v) \ + : GPIO1PIN_NPA4_INITOUT(v) ) + +#define GPIO1PIN_NPA4_INITIN(v) do{ \ + bFM_GPIO_PCRA_P4=(v).bPullup; \ + bFM_GPIO_DDRA_P4=0u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +#define GPIO1PIN_NPA4_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P4=1u; \ + bFM_GPIO_PFRA_P4=0u; }while(0u) + +/*---- GPIO bit PA5 ----*/ +#define GPIO1PIN_PA5_GET ( bFM_GPIO_PDIRA_P5 ) + +#define GPIO1PIN_PA5_PUT(v) ( bFM_GPIO_PDORA_P5=(v) ) + +#define GPIO1PIN_PA5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA5_INITIN(v) \ + : GPIO1PIN_PA5_INITOUT(v) ) + +#define GPIO1PIN_PA5_INITIN(v) do{ \ + bFM_GPIO_PCRA_P5=(v).bPullup; \ + bFM_GPIO_DDRA_P5=0u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +#define GPIO1PIN_PA5_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P5=(v).bInitVal; \ + bFM_GPIO_DDRA_P5=1u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +/*---- GPIO bit NPA5 ----*/ +#define GPIO1PIN_NPA5_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P5)) ) + +#define GPIO1PIN_NPA5_PUT(v) ( bFM_GPIO_PDORA_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA5_INITIN(v) \ + : GPIO1PIN_NPA5_INITOUT(v) ) + +#define GPIO1PIN_NPA5_INITIN(v) do{ \ + bFM_GPIO_PCRA_P5=(v).bPullup; \ + bFM_GPIO_DDRA_P5=0u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +#define GPIO1PIN_NPA5_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P5=1u; \ + bFM_GPIO_PFRA_P5=0u; }while(0u) + +/*---- GPIO bit PA6 ----*/ +#define GPIO1PIN_PA6_GET ( bFM_GPIO_PDIRA_P6 ) + +#define GPIO1PIN_PA6_PUT(v) ( bFM_GPIO_PDORA_P6=(v) ) + +#define GPIO1PIN_PA6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA6_INITIN(v) \ + : GPIO1PIN_PA6_INITOUT(v) ) + +#define GPIO1PIN_PA6_INITIN(v) do{ \ + bFM_GPIO_PCRA_P6=(v).bPullup; \ + bFM_GPIO_DDRA_P6=0u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +#define GPIO1PIN_PA6_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P6=(v).bInitVal; \ + bFM_GPIO_DDRA_P6=1u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +/*---- GPIO bit NPA6 ----*/ +#define GPIO1PIN_NPA6_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P6)) ) + +#define GPIO1PIN_NPA6_PUT(v) ( bFM_GPIO_PDORA_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA6_INITIN(v) \ + : GPIO1PIN_NPA6_INITOUT(v) ) + +#define GPIO1PIN_NPA6_INITIN(v) do{ \ + bFM_GPIO_PCRA_P6=(v).bPullup; \ + bFM_GPIO_DDRA_P6=0u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +#define GPIO1PIN_NPA6_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P6=1u; \ + bFM_GPIO_PFRA_P6=0u; }while(0u) + +/*---- GPIO bit PA7 ----*/ +#define GPIO1PIN_PA7_GET ( bFM_GPIO_PDIRA_P7 ) + +#define GPIO1PIN_PA7_PUT(v) ( bFM_GPIO_PDORA_P7=(v) ) + +#define GPIO1PIN_PA7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA7_INITIN(v) \ + : GPIO1PIN_PA7_INITOUT(v) ) + +#define GPIO1PIN_PA7_INITIN(v) do{ \ + bFM_GPIO_PCRA_P7=(v).bPullup; \ + bFM_GPIO_DDRA_P7=0u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +#define GPIO1PIN_PA7_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P7=(v).bInitVal; \ + bFM_GPIO_DDRA_P7=1u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +/*---- GPIO bit NPA7 ----*/ +#define GPIO1PIN_NPA7_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P7)) ) + +#define GPIO1PIN_NPA7_PUT(v) ( bFM_GPIO_PDORA_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA7_INITIN(v) \ + : GPIO1PIN_NPA7_INITOUT(v) ) + +#define GPIO1PIN_NPA7_INITIN(v) do{ \ + bFM_GPIO_PCRA_P7=(v).bPullup; \ + bFM_GPIO_DDRA_P7=0u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +#define GPIO1PIN_NPA7_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P7=1u; \ + bFM_GPIO_PFRA_P7=0u; }while(0u) + +/*---- GPIO bit PA8 ----*/ +#define GPIO1PIN_PA8_GET ( bFM_GPIO_PDIRA_P8 ) + +#define GPIO1PIN_PA8_PUT(v) ( bFM_GPIO_PDORA_P8=(v) ) + +#define GPIO1PIN_PA8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA8_INITIN(v) \ + : GPIO1PIN_PA8_INITOUT(v) ) + +#define GPIO1PIN_PA8_INITIN(v) do{ \ + bFM_GPIO_PCRA_P8=(v).bPullup; \ + bFM_GPIO_DDRA_P8=0u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +#define GPIO1PIN_PA8_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P8=(v).bInitVal; \ + bFM_GPIO_DDRA_P8=1u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +/*---- GPIO bit NPA8 ----*/ +#define GPIO1PIN_NPA8_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P8)) ) + +#define GPIO1PIN_NPA8_PUT(v) ( bFM_GPIO_PDORA_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA8_INITIN(v) \ + : GPIO1PIN_NPA8_INITOUT(v) ) + +#define GPIO1PIN_NPA8_INITIN(v) do{ \ + bFM_GPIO_PCRA_P8=(v).bPullup; \ + bFM_GPIO_DDRA_P8=0u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +#define GPIO1PIN_NPA8_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P8=1u; \ + bFM_GPIO_PFRA_P8=0u; }while(0u) + +/*---- GPIO bit PA9 ----*/ +#define GPIO1PIN_PA9_GET ( bFM_GPIO_PDIRA_P9 ) + +#define GPIO1PIN_PA9_PUT(v) ( bFM_GPIO_PDORA_P9=(v) ) + +#define GPIO1PIN_PA9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PA9_INITIN(v) \ + : GPIO1PIN_PA9_INITOUT(v) ) + +#define GPIO1PIN_PA9_INITIN(v) do{ \ + bFM_GPIO_PCRA_P9=(v).bPullup; \ + bFM_GPIO_DDRA_P9=0u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +#define GPIO1PIN_PA9_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P9=(v).bInitVal; \ + bFM_GPIO_DDRA_P9=1u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +/*---- GPIO bit NPA9 ----*/ +#define GPIO1PIN_NPA9_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_P9)) ) + +#define GPIO1PIN_NPA9_PUT(v) ( bFM_GPIO_PDORA_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPA9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPA9_INITIN(v) \ + : GPIO1PIN_NPA9_INITOUT(v) ) + +#define GPIO1PIN_NPA9_INITIN(v) do{ \ + bFM_GPIO_PCRA_P9=(v).bPullup; \ + bFM_GPIO_DDRA_P9=0u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +#define GPIO1PIN_NPA9_INITOUT(v) do{ \ + bFM_GPIO_PDORA_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_P9=1u; \ + bFM_GPIO_PFRA_P9=0u; }while(0u) + +/*---- GPIO bit PAA ----*/ +#define GPIO1PIN_PAA_GET ( bFM_GPIO_PDIRA_PA ) + +#define GPIO1PIN_PAA_PUT(v) ( bFM_GPIO_PDORA_PA=(v) ) + +#define GPIO1PIN_PAA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAA_INITIN(v) \ + : GPIO1PIN_PAA_INITOUT(v) ) + +#define GPIO1PIN_PAA_INITIN(v) do{ \ + bFM_GPIO_PCRA_PA=(v).bPullup; \ + bFM_GPIO_DDRA_PA=0u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +#define GPIO1PIN_PAA_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PA=(v).bInitVal; \ + bFM_GPIO_DDRA_PA=1u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +/*---- GPIO bit NPAA ----*/ +#define GPIO1PIN_NPAA_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PA)) ) + +#define GPIO1PIN_NPAA_PUT(v) ( bFM_GPIO_PDORA_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAA_INITIN(v) \ + : GPIO1PIN_NPAA_INITOUT(v) ) + +#define GPIO1PIN_NPAA_INITIN(v) do{ \ + bFM_GPIO_PCRA_PA=(v).bPullup; \ + bFM_GPIO_DDRA_PA=0u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +#define GPIO1PIN_NPAA_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PA=1u; \ + bFM_GPIO_PFRA_PA=0u; }while(0u) + +/*---- GPIO bit PAB ----*/ +#define GPIO1PIN_PAB_GET ( bFM_GPIO_PDIRA_PB ) + +#define GPIO1PIN_PAB_PUT(v) ( bFM_GPIO_PDORA_PB=(v) ) + +#define GPIO1PIN_PAB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAB_INITIN(v) \ + : GPIO1PIN_PAB_INITOUT(v) ) + +#define GPIO1PIN_PAB_INITIN(v) do{ \ + bFM_GPIO_PCRA_PB=(v).bPullup; \ + bFM_GPIO_DDRA_PB=0u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +#define GPIO1PIN_PAB_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PB=(v).bInitVal; \ + bFM_GPIO_DDRA_PB=1u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +/*---- GPIO bit NPAB ----*/ +#define GPIO1PIN_NPAB_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PB)) ) + +#define GPIO1PIN_NPAB_PUT(v) ( bFM_GPIO_PDORA_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAB_INITIN(v) \ + : GPIO1PIN_NPAB_INITOUT(v) ) + +#define GPIO1PIN_NPAB_INITIN(v) do{ \ + bFM_GPIO_PCRA_PB=(v).bPullup; \ + bFM_GPIO_DDRA_PB=0u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +#define GPIO1PIN_NPAB_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PB=1u; \ + bFM_GPIO_PFRA_PB=0u; }while(0u) + +/*---- GPIO bit PAC ----*/ +#define GPIO1PIN_PAC_GET ( bFM_GPIO_PDIRA_PC ) + +#define GPIO1PIN_PAC_PUT(v) ( bFM_GPIO_PDORA_PC=(v) ) + +#define GPIO1PIN_PAC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAC_INITIN(v) \ + : GPIO1PIN_PAC_INITOUT(v) ) + +#define GPIO1PIN_PAC_INITIN(v) do{ \ + bFM_GPIO_PCRA_PC=(v).bPullup; \ + bFM_GPIO_DDRA_PC=0u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +#define GPIO1PIN_PAC_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PC=(v).bInitVal; \ + bFM_GPIO_DDRA_PC=1u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +/*---- GPIO bit NPAC ----*/ +#define GPIO1PIN_NPAC_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PC)) ) + +#define GPIO1PIN_NPAC_PUT(v) ( bFM_GPIO_PDORA_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAC_INITIN(v) \ + : GPIO1PIN_NPAC_INITOUT(v) ) + +#define GPIO1PIN_NPAC_INITIN(v) do{ \ + bFM_GPIO_PCRA_PC=(v).bPullup; \ + bFM_GPIO_DDRA_PC=0u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +#define GPIO1PIN_NPAC_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PC=1u; \ + bFM_GPIO_PFRA_PC=0u; }while(0u) + +/*---- GPIO bit PAD ----*/ +#define GPIO1PIN_PAD_GET ( bFM_GPIO_PDIRA_PD ) + +#define GPIO1PIN_PAD_PUT(v) ( bFM_GPIO_PDORA_PD=(v) ) + +#define GPIO1PIN_PAD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAD_INITIN(v) \ + : GPIO1PIN_PAD_INITOUT(v) ) + +#define GPIO1PIN_PAD_INITIN(v) do{ \ + bFM_GPIO_PCRA_PD=(v).bPullup; \ + bFM_GPIO_DDRA_PD=0u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +#define GPIO1PIN_PAD_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PD=(v).bInitVal; \ + bFM_GPIO_DDRA_PD=1u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +/*---- GPIO bit NPAD ----*/ +#define GPIO1PIN_NPAD_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PD)) ) + +#define GPIO1PIN_NPAD_PUT(v) ( bFM_GPIO_PDORA_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAD_INITIN(v) \ + : GPIO1PIN_NPAD_INITOUT(v) ) + +#define GPIO1PIN_NPAD_INITIN(v) do{ \ + bFM_GPIO_PCRA_PD=(v).bPullup; \ + bFM_GPIO_DDRA_PD=0u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +#define GPIO1PIN_NPAD_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PD=1u; \ + bFM_GPIO_PFRA_PD=0u; }while(0u) + +/*---- GPIO bit PAE ----*/ +#define GPIO1PIN_PAE_GET ( bFM_GPIO_PDIRA_PE ) + +#define GPIO1PIN_PAE_PUT(v) ( bFM_GPIO_PDORA_PE=(v) ) + +#define GPIO1PIN_PAE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAE_INITIN(v) \ + : GPIO1PIN_PAE_INITOUT(v) ) + +#define GPIO1PIN_PAE_INITIN(v) do{ \ + bFM_GPIO_PCRA_PE=(v).bPullup; \ + bFM_GPIO_DDRA_PE=0u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +#define GPIO1PIN_PAE_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PE=(v).bInitVal; \ + bFM_GPIO_DDRA_PE=1u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +/*---- GPIO bit NPAE ----*/ +#define GPIO1PIN_NPAE_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PE)) ) + +#define GPIO1PIN_NPAE_PUT(v) ( bFM_GPIO_PDORA_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAE_INITIN(v) \ + : GPIO1PIN_NPAE_INITOUT(v) ) + +#define GPIO1PIN_NPAE_INITIN(v) do{ \ + bFM_GPIO_PCRA_PE=(v).bPullup; \ + bFM_GPIO_DDRA_PE=0u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +#define GPIO1PIN_NPAE_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PE=1u; \ + bFM_GPIO_PFRA_PE=0u; }while(0u) + +/*---- GPIO bit PAF ----*/ +#define GPIO1PIN_PAF_GET ( bFM_GPIO_PDIRA_PF ) + +#define GPIO1PIN_PAF_PUT(v) ( bFM_GPIO_PDORA_PF=(v) ) + +#define GPIO1PIN_PAF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PAF_INITIN(v) \ + : GPIO1PIN_PAF_INITOUT(v) ) + +#define GPIO1PIN_PAF_INITIN(v) do{ \ + bFM_GPIO_PCRA_PF=(v).bPullup; \ + bFM_GPIO_DDRA_PF=0u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +#define GPIO1PIN_PAF_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PF=(v).bInitVal; \ + bFM_GPIO_DDRA_PF=1u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +/*---- GPIO bit NPAF ----*/ +#define GPIO1PIN_NPAF_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRA_PF)) ) + +#define GPIO1PIN_NPAF_PUT(v) ( bFM_GPIO_PDORA_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPAF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPAF_INITIN(v) \ + : GPIO1PIN_NPAF_INITOUT(v) ) + +#define GPIO1PIN_NPAF_INITIN(v) do{ \ + bFM_GPIO_PCRA_PF=(v).bPullup; \ + bFM_GPIO_DDRA_PF=0u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +#define GPIO1PIN_NPAF_INITOUT(v) do{ \ + bFM_GPIO_PDORA_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRA_PF=1u; \ + bFM_GPIO_PFRA_PF=0u; }while(0u) + +/*---- GPIO bit PB0 ----*/ +#define GPIO1PIN_PB0_GET ( bFM_GPIO_PDIRB_P0 ) + +#define GPIO1PIN_PB0_PUT(v) ( bFM_GPIO_PDORB_P0=(v) ) + +#define GPIO1PIN_PB0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB0_INITIN(v) \ + : GPIO1PIN_PB0_INITOUT(v) ) + +#define GPIO1PIN_PB0_INITIN(v) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + bFM_GPIO_PCRB_P0=(v).bPullup; \ + bFM_GPIO_DDRB_P0=0u; \ + bFM_GPIO_PFRB_P0=0u; }while(0u) + +#define GPIO1PIN_PB0_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + bFM_GPIO_PDORB_P0=(v).bInitVal; \ + bFM_GPIO_DDRB_P0=1u; \ + bFM_GPIO_PFRB_P0=0u; }while(0u) + +/*---- GPIO bit NPB0 ----*/ +#define GPIO1PIN_NPB0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P0)) ) + +#define GPIO1PIN_NPB0_PUT(v) ( bFM_GPIO_PDORB_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB0_INITIN(v) \ + : GPIO1PIN_NPB0_INITOUT(v) ) + +#define GPIO1PIN_NPB0_INITIN(v) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + bFM_GPIO_PCRB_P0=(v).bPullup; \ + bFM_GPIO_DDRB_P0=0u; \ + bFM_GPIO_PFRB_P0=0u; }while(0u) + +#define GPIO1PIN_NPB0_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + bFM_GPIO_PDORB_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P0=1u; \ + bFM_GPIO_PFRB_P0=0u; }while(0u) + +/*---- GPIO bit PB1 ----*/ +#define GPIO1PIN_PB1_GET ( bFM_GPIO_PDIRB_P1 ) + +#define GPIO1PIN_PB1_PUT(v) ( bFM_GPIO_PDORB_P1=(v) ) + +#define GPIO1PIN_PB1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB1_INITIN(v) \ + : GPIO1PIN_PB1_INITOUT(v) ) + +#define GPIO1PIN_PB1_INITIN(v) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + bFM_GPIO_PCRB_P1=(v).bPullup; \ + bFM_GPIO_DDRB_P1=0u; \ + bFM_GPIO_PFRB_P1=0u; }while(0u) + +#define GPIO1PIN_PB1_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + bFM_GPIO_PDORB_P1=(v).bInitVal; \ + bFM_GPIO_DDRB_P1=1u; \ + bFM_GPIO_PFRB_P1=0u; }while(0u) + +/*---- GPIO bit NPB1 ----*/ +#define GPIO1PIN_NPB1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P1)) ) + +#define GPIO1PIN_NPB1_PUT(v) ( bFM_GPIO_PDORB_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB1_INITIN(v) \ + : GPIO1PIN_NPB1_INITOUT(v) ) + +#define GPIO1PIN_NPB1_INITIN(v) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + bFM_GPIO_PCRB_P1=(v).bPullup; \ + bFM_GPIO_DDRB_P1=0u; \ + bFM_GPIO_PFRB_P1=0u; }while(0u) + +#define GPIO1PIN_NPB1_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + bFM_GPIO_PDORB_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P1=1u; \ + bFM_GPIO_PFRB_P1=0u; }while(0u) + +/*---- GPIO bit PB2 ----*/ +#define GPIO1PIN_PB2_GET ( bFM_GPIO_PDIRB_P2 ) + +#define GPIO1PIN_PB2_PUT(v) ( bFM_GPIO_PDORB_P2=(v) ) + +#define GPIO1PIN_PB2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB2_INITIN(v) \ + : GPIO1PIN_PB2_INITOUT(v) ) + +#define GPIO1PIN_PB2_INITIN(v) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + bFM_GPIO_PCRB_P2=(v).bPullup; \ + bFM_GPIO_DDRB_P2=0u; \ + bFM_GPIO_PFRB_P2=0u; }while(0u) + +#define GPIO1PIN_PB2_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + bFM_GPIO_PDORB_P2=(v).bInitVal; \ + bFM_GPIO_DDRB_P2=1u; \ + bFM_GPIO_PFRB_P2=0u; }while(0u) + +/*---- GPIO bit NPB2 ----*/ +#define GPIO1PIN_NPB2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P2)) ) + +#define GPIO1PIN_NPB2_PUT(v) ( bFM_GPIO_PDORB_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB2_INITIN(v) \ + : GPIO1PIN_NPB2_INITOUT(v) ) + +#define GPIO1PIN_NPB2_INITIN(v) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + bFM_GPIO_PCRB_P2=(v).bPullup; \ + bFM_GPIO_DDRB_P2=0u; \ + bFM_GPIO_PFRB_P2=0u; }while(0u) + +#define GPIO1PIN_NPB2_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + bFM_GPIO_PDORB_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P2=1u; \ + bFM_GPIO_PFRB_P2=0u; }while(0u) + +/*---- GPIO bit PB3 ----*/ +#define GPIO1PIN_PB3_GET ( bFM_GPIO_PDIRB_P3 ) + +#define GPIO1PIN_PB3_PUT(v) ( bFM_GPIO_PDORB_P3=(v) ) + +#define GPIO1PIN_PB3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB3_INITIN(v) \ + : GPIO1PIN_PB3_INITOUT(v) ) + +#define GPIO1PIN_PB3_INITIN(v) do{ \ + bFM_GPIO_ADE_AN19=0u; \ + bFM_GPIO_PCRB_P3=(v).bPullup; \ + bFM_GPIO_DDRB_P3=0u; \ + bFM_GPIO_PFRB_P3=0u; }while(0u) + +#define GPIO1PIN_PB3_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN19=0u; \ + bFM_GPIO_PDORB_P3=(v).bInitVal; \ + bFM_GPIO_DDRB_P3=1u; \ + bFM_GPIO_PFRB_P3=0u; }while(0u) + +/*---- GPIO bit NPB3 ----*/ +#define GPIO1PIN_NPB3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P3)) ) + +#define GPIO1PIN_NPB3_PUT(v) ( bFM_GPIO_PDORB_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB3_INITIN(v) \ + : GPIO1PIN_NPB3_INITOUT(v) ) + +#define GPIO1PIN_NPB3_INITIN(v) do{ \ + bFM_GPIO_ADE_AN19=0u; \ + bFM_GPIO_PCRB_P3=(v).bPullup; \ + bFM_GPIO_DDRB_P3=0u; \ + bFM_GPIO_PFRB_P3=0u; }while(0u) + +#define GPIO1PIN_NPB3_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN19=0u; \ + bFM_GPIO_PDORB_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P3=1u; \ + bFM_GPIO_PFRB_P3=0u; }while(0u) + +/*---- GPIO bit PB4 ----*/ +#define GPIO1PIN_PB4_GET ( bFM_GPIO_PDIRB_P4 ) + +#define GPIO1PIN_PB4_PUT(v) ( bFM_GPIO_PDORB_P4=(v) ) + +#define GPIO1PIN_PB4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB4_INITIN(v) \ + : GPIO1PIN_PB4_INITOUT(v) ) + +#define GPIO1PIN_PB4_INITIN(v) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + bFM_GPIO_PCRB_P4=(v).bPullup; \ + bFM_GPIO_DDRB_P4=0u; \ + bFM_GPIO_PFRB_P4=0u; }while(0u) + +#define GPIO1PIN_PB4_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + bFM_GPIO_PDORB_P4=(v).bInitVal; \ + bFM_GPIO_DDRB_P4=1u; \ + bFM_GPIO_PFRB_P4=0u; }while(0u) + +/*---- GPIO bit NPB4 ----*/ +#define GPIO1PIN_NPB4_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P4)) ) + +#define GPIO1PIN_NPB4_PUT(v) ( bFM_GPIO_PDORB_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB4_INITIN(v) \ + : GPIO1PIN_NPB4_INITOUT(v) ) + +#define GPIO1PIN_NPB4_INITIN(v) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + bFM_GPIO_PCRB_P4=(v).bPullup; \ + bFM_GPIO_DDRB_P4=0u; \ + bFM_GPIO_PFRB_P4=0u; }while(0u) + +#define GPIO1PIN_NPB4_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + bFM_GPIO_PDORB_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P4=1u; \ + bFM_GPIO_PFRB_P4=0u; }while(0u) + +/*---- GPIO bit PB5 ----*/ +#define GPIO1PIN_PB5_GET ( bFM_GPIO_PDIRB_P5 ) + +#define GPIO1PIN_PB5_PUT(v) ( bFM_GPIO_PDORB_P5=(v) ) + +#define GPIO1PIN_PB5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB5_INITIN(v) \ + : GPIO1PIN_PB5_INITOUT(v) ) + +#define GPIO1PIN_PB5_INITIN(v) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + bFM_GPIO_PCRB_P5=(v).bPullup; \ + bFM_GPIO_DDRB_P5=0u; \ + bFM_GPIO_PFRB_P5=0u; }while(0u) + +#define GPIO1PIN_PB5_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + bFM_GPIO_PDORB_P5=(v).bInitVal; \ + bFM_GPIO_DDRB_P5=1u; \ + bFM_GPIO_PFRB_P5=0u; }while(0u) + +/*---- GPIO bit NPB5 ----*/ +#define GPIO1PIN_NPB5_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P5)) ) + +#define GPIO1PIN_NPB5_PUT(v) ( bFM_GPIO_PDORB_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB5_INITIN(v) \ + : GPIO1PIN_NPB5_INITOUT(v) ) + +#define GPIO1PIN_NPB5_INITIN(v) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + bFM_GPIO_PCRB_P5=(v).bPullup; \ + bFM_GPIO_DDRB_P5=0u; \ + bFM_GPIO_PFRB_P5=0u; }while(0u) + +#define GPIO1PIN_NPB5_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + bFM_GPIO_PDORB_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P5=1u; \ + bFM_GPIO_PFRB_P5=0u; }while(0u) + +/*---- GPIO bit PB6 ----*/ +#define GPIO1PIN_PB6_GET ( bFM_GPIO_PDIRB_P6 ) + +#define GPIO1PIN_PB6_PUT(v) ( bFM_GPIO_PDORB_P6=(v) ) + +#define GPIO1PIN_PB6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB6_INITIN(v) \ + : GPIO1PIN_PB6_INITOUT(v) ) + +#define GPIO1PIN_PB6_INITIN(v) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + bFM_GPIO_PCRB_P6=(v).bPullup; \ + bFM_GPIO_DDRB_P6=0u; \ + bFM_GPIO_PFRB_P6=0u; }while(0u) + +#define GPIO1PIN_PB6_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + bFM_GPIO_PDORB_P6=(v).bInitVal; \ + bFM_GPIO_DDRB_P6=1u; \ + bFM_GPIO_PFRB_P6=0u; }while(0u) + +/*---- GPIO bit NPB6 ----*/ +#define GPIO1PIN_NPB6_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P6)) ) + +#define GPIO1PIN_NPB6_PUT(v) ( bFM_GPIO_PDORB_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB6_INITIN(v) \ + : GPIO1PIN_NPB6_INITOUT(v) ) + +#define GPIO1PIN_NPB6_INITIN(v) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + bFM_GPIO_PCRB_P6=(v).bPullup; \ + bFM_GPIO_DDRB_P6=0u; \ + bFM_GPIO_PFRB_P6=0u; }while(0u) + +#define GPIO1PIN_NPB6_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + bFM_GPIO_PDORB_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P6=1u; \ + bFM_GPIO_PFRB_P6=0u; }while(0u) + +/*---- GPIO bit PB7 ----*/ +#define GPIO1PIN_PB7_GET ( bFM_GPIO_PDIRB_P7 ) + +#define GPIO1PIN_PB7_PUT(v) ( bFM_GPIO_PDORB_P7=(v) ) + +#define GPIO1PIN_PB7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB7_INITIN(v) \ + : GPIO1PIN_PB7_INITOUT(v) ) + +#define GPIO1PIN_PB7_INITIN(v) do{ \ + bFM_GPIO_ADE_AN23=0u; \ + bFM_GPIO_PCRB_P7=(v).bPullup; \ + bFM_GPIO_DDRB_P7=0u; \ + bFM_GPIO_PFRB_P7=0u; }while(0u) + +#define GPIO1PIN_PB7_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN23=0u; \ + bFM_GPIO_PDORB_P7=(v).bInitVal; \ + bFM_GPIO_DDRB_P7=1u; \ + bFM_GPIO_PFRB_P7=0u; }while(0u) + +/*---- GPIO bit NPB7 ----*/ +#define GPIO1PIN_NPB7_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P7)) ) + +#define GPIO1PIN_NPB7_PUT(v) ( bFM_GPIO_PDORB_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB7_INITIN(v) \ + : GPIO1PIN_NPB7_INITOUT(v) ) + +#define GPIO1PIN_NPB7_INITIN(v) do{ \ + bFM_GPIO_ADE_AN23=0u; \ + bFM_GPIO_PCRB_P7=(v).bPullup; \ + bFM_GPIO_DDRB_P7=0u; \ + bFM_GPIO_PFRB_P7=0u; }while(0u) + +#define GPIO1PIN_NPB7_INITOUT(v) do{ \ + bFM_GPIO_ADE_AN23=0u; \ + bFM_GPIO_PDORB_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P7=1u; \ + bFM_GPIO_PFRB_P7=0u; }while(0u) + +/*---- GPIO bit PB8 ----*/ +#define GPIO1PIN_PB8_GET ( bFM_GPIO_PDIRB_P8 ) + +#define GPIO1PIN_PB8_PUT(v) ( bFM_GPIO_PDORB_P8=(v) ) + +#define GPIO1PIN_PB8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB8_INITIN(v) \ + : GPIO1PIN_PB8_INITOUT(v) ) + +#define GPIO1PIN_PB8_INITIN(v) do{ \ + bFM_GPIO_PCRB_P8=(v).bPullup; \ + bFM_GPIO_DDRB_P8=0u; \ + bFM_GPIO_PFRB_P8=0u; }while(0u) + +#define GPIO1PIN_PB8_INITOUT(v) do{ \ + bFM_GPIO_PDORB_P8=(v).bInitVal; \ + bFM_GPIO_DDRB_P8=1u; \ + bFM_GPIO_PFRB_P8=0u; }while(0u) + +/*---- GPIO bit NPB8 ----*/ +#define GPIO1PIN_NPB8_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P8)) ) + +#define GPIO1PIN_NPB8_PUT(v) ( bFM_GPIO_PDORB_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB8_INITIN(v) \ + : GPIO1PIN_NPB8_INITOUT(v) ) + +#define GPIO1PIN_NPB8_INITIN(v) do{ \ + bFM_GPIO_PCRB_P8=(v).bPullup; \ + bFM_GPIO_DDRB_P8=0u; \ + bFM_GPIO_PFRB_P8=0u; }while(0u) + +#define GPIO1PIN_NPB8_INITOUT(v) do{ \ + bFM_GPIO_PDORB_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P8=1u; \ + bFM_GPIO_PFRB_P8=0u; }while(0u) + +/*---- GPIO bit PB9 ----*/ +#define GPIO1PIN_PB9_GET ( bFM_GPIO_PDIRB_P9 ) + +#define GPIO1PIN_PB9_PUT(v) ( bFM_GPIO_PDORB_P9=(v) ) + +#define GPIO1PIN_PB9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PB9_INITIN(v) \ + : GPIO1PIN_PB9_INITOUT(v) ) + +#define GPIO1PIN_PB9_INITIN(v) do{ \ + bFM_GPIO_PCRB_P9=(v).bPullup; \ + bFM_GPIO_DDRB_P9=0u; \ + bFM_GPIO_PFRB_P9=0u; }while(0u) + +#define GPIO1PIN_PB9_INITOUT(v) do{ \ + bFM_GPIO_PDORB_P9=(v).bInitVal; \ + bFM_GPIO_DDRB_P9=1u; \ + bFM_GPIO_PFRB_P9=0u; }while(0u) + +/*---- GPIO bit NPB9 ----*/ +#define GPIO1PIN_NPB9_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_P9)) ) + +#define GPIO1PIN_NPB9_PUT(v) ( bFM_GPIO_PDORB_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPB9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPB9_INITIN(v) \ + : GPIO1PIN_NPB9_INITOUT(v) ) + +#define GPIO1PIN_NPB9_INITIN(v) do{ \ + bFM_GPIO_PCRB_P9=(v).bPullup; \ + bFM_GPIO_DDRB_P9=0u; \ + bFM_GPIO_PFRB_P9=0u; }while(0u) + +#define GPIO1PIN_NPB9_INITOUT(v) do{ \ + bFM_GPIO_PDORB_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_P9=1u; \ + bFM_GPIO_PFRB_P9=0u; }while(0u) + +/*---- GPIO bit PBA ----*/ +#define GPIO1PIN_PBA_GET ( bFM_GPIO_PDIRB_PA ) + +#define GPIO1PIN_PBA_PUT(v) ( bFM_GPIO_PDORB_PA=(v) ) + +#define GPIO1PIN_PBA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PBA_INITIN(v) \ + : GPIO1PIN_PBA_INITOUT(v) ) + +#define GPIO1PIN_PBA_INITIN(v) do{ \ + bFM_GPIO_PCRB_PA=(v).bPullup; \ + bFM_GPIO_DDRB_PA=0u; \ + bFM_GPIO_PFRB_PA=0u; }while(0u) + +#define GPIO1PIN_PBA_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PA=(v).bInitVal; \ + bFM_GPIO_DDRB_PA=1u; \ + bFM_GPIO_PFRB_PA=0u; }while(0u) + +/*---- GPIO bit NPBA ----*/ +#define GPIO1PIN_NPBA_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_PA)) ) + +#define GPIO1PIN_NPBA_PUT(v) ( bFM_GPIO_PDORB_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPBA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPBA_INITIN(v) \ + : GPIO1PIN_NPBA_INITOUT(v) ) + +#define GPIO1PIN_NPBA_INITIN(v) do{ \ + bFM_GPIO_PCRB_PA=(v).bPullup; \ + bFM_GPIO_DDRB_PA=0u; \ + bFM_GPIO_PFRB_PA=0u; }while(0u) + +#define GPIO1PIN_NPBA_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_PA=1u; \ + bFM_GPIO_PFRB_PA=0u; }while(0u) + +/*---- GPIO bit PBB ----*/ +#define GPIO1PIN_PBB_GET ( bFM_GPIO_PDIRB_PB ) + +#define GPIO1PIN_PBB_PUT(v) ( bFM_GPIO_PDORB_PB=(v) ) + +#define GPIO1PIN_PBB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PBB_INITIN(v) \ + : GPIO1PIN_PBB_INITOUT(v) ) + +#define GPIO1PIN_PBB_INITIN(v) do{ \ + bFM_GPIO_PCRB_PB=(v).bPullup; \ + bFM_GPIO_DDRB_PB=0u; \ + bFM_GPIO_PFRB_PB=0u; }while(0u) + +#define GPIO1PIN_PBB_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PB=(v).bInitVal; \ + bFM_GPIO_DDRB_PB=1u; \ + bFM_GPIO_PFRB_PB=0u; }while(0u) + +/*---- GPIO bit NPBB ----*/ +#define GPIO1PIN_NPBB_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_PB)) ) + +#define GPIO1PIN_NPBB_PUT(v) ( bFM_GPIO_PDORB_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPBB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPBB_INITIN(v) \ + : GPIO1PIN_NPBB_INITOUT(v) ) + +#define GPIO1PIN_NPBB_INITIN(v) do{ \ + bFM_GPIO_PCRB_PB=(v).bPullup; \ + bFM_GPIO_DDRB_PB=0u; \ + bFM_GPIO_PFRB_PB=0u; }while(0u) + +#define GPIO1PIN_NPBB_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_PB=1u; \ + bFM_GPIO_PFRB_PB=0u; }while(0u) + +/*---- GPIO bit PBC ----*/ +#define GPIO1PIN_PBC_GET ( bFM_GPIO_PDIRB_PC ) + +#define GPIO1PIN_PBC_PUT(v) ( bFM_GPIO_PDORB_PC=(v) ) + +#define GPIO1PIN_PBC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PBC_INITIN(v) \ + : GPIO1PIN_PBC_INITOUT(v) ) + +#define GPIO1PIN_PBC_INITIN(v) do{ \ + bFM_GPIO_PCRB_PC=(v).bPullup; \ + bFM_GPIO_DDRB_PC=0u; \ + bFM_GPIO_PFRB_PC=0u; }while(0u) + +#define GPIO1PIN_PBC_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PC=(v).bInitVal; \ + bFM_GPIO_DDRB_PC=1u; \ + bFM_GPIO_PFRB_PC=0u; }while(0u) + +/*---- GPIO bit NPBC ----*/ +#define GPIO1PIN_NPBC_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_PC)) ) + +#define GPIO1PIN_NPBC_PUT(v) ( bFM_GPIO_PDORB_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPBC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPBC_INITIN(v) \ + : GPIO1PIN_NPBC_INITOUT(v) ) + +#define GPIO1PIN_NPBC_INITIN(v) do{ \ + bFM_GPIO_PCRB_PC=(v).bPullup; \ + bFM_GPIO_DDRB_PC=0u; \ + bFM_GPIO_PFRB_PC=0u; }while(0u) + +#define GPIO1PIN_NPBC_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_PC=1u; \ + bFM_GPIO_PFRB_PC=0u; }while(0u) + +/*---- GPIO bit PBD ----*/ +#define GPIO1PIN_PBD_GET ( bFM_GPIO_PDIRB_PD ) + +#define GPIO1PIN_PBD_PUT(v) ( bFM_GPIO_PDORB_PD=(v) ) + +#define GPIO1PIN_PBD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PBD_INITIN(v) \ + : GPIO1PIN_PBD_INITOUT(v) ) + +#define GPIO1PIN_PBD_INITIN(v) do{ \ + bFM_GPIO_PCRB_PD=(v).bPullup; \ + bFM_GPIO_DDRB_PD=0u; \ + bFM_GPIO_PFRB_PD=0u; }while(0u) + +#define GPIO1PIN_PBD_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PD=(v).bInitVal; \ + bFM_GPIO_DDRB_PD=1u; \ + bFM_GPIO_PFRB_PD=0u; }while(0u) + +/*---- GPIO bit NPBD ----*/ +#define GPIO1PIN_NPBD_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_PD)) ) + +#define GPIO1PIN_NPBD_PUT(v) ( bFM_GPIO_PDORB_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPBD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPBD_INITIN(v) \ + : GPIO1PIN_NPBD_INITOUT(v) ) + +#define GPIO1PIN_NPBD_INITIN(v) do{ \ + bFM_GPIO_PCRB_PD=(v).bPullup; \ + bFM_GPIO_DDRB_PD=0u; \ + bFM_GPIO_PFRB_PD=0u; }while(0u) + +#define GPIO1PIN_NPBD_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_PD=1u; \ + bFM_GPIO_PFRB_PD=0u; }while(0u) + +/*---- GPIO bit PBE ----*/ +#define GPIO1PIN_PBE_GET ( bFM_GPIO_PDIRB_PE ) + +#define GPIO1PIN_PBE_PUT(v) ( bFM_GPIO_PDORB_PE=(v) ) + +#define GPIO1PIN_PBE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PBE_INITIN(v) \ + : GPIO1PIN_PBE_INITOUT(v) ) + +#define GPIO1PIN_PBE_INITIN(v) do{ \ + bFM_GPIO_PCRB_PE=(v).bPullup; \ + bFM_GPIO_DDRB_PE=0u; \ + bFM_GPIO_PFRB_PE=0u; }while(0u) + +#define GPIO1PIN_PBE_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PE=(v).bInitVal; \ + bFM_GPIO_DDRB_PE=1u; \ + bFM_GPIO_PFRB_PE=0u; }while(0u) + +/*---- GPIO bit NPBE ----*/ +#define GPIO1PIN_NPBE_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_PE)) ) + +#define GPIO1PIN_NPBE_PUT(v) ( bFM_GPIO_PDORB_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPBE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPBE_INITIN(v) \ + : GPIO1PIN_NPBE_INITOUT(v) ) + +#define GPIO1PIN_NPBE_INITIN(v) do{ \ + bFM_GPIO_PCRB_PE=(v).bPullup; \ + bFM_GPIO_DDRB_PE=0u; \ + bFM_GPIO_PFRB_PE=0u; }while(0u) + +#define GPIO1PIN_NPBE_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_PE=1u; \ + bFM_GPIO_PFRB_PE=0u; }while(0u) + +/*---- GPIO bit PBF ----*/ +#define GPIO1PIN_PBF_GET ( bFM_GPIO_PDIRB_PF ) + +#define GPIO1PIN_PBF_PUT(v) ( bFM_GPIO_PDORB_PF=(v) ) + +#define GPIO1PIN_PBF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PBF_INITIN(v) \ + : GPIO1PIN_PBF_INITOUT(v) ) + +#define GPIO1PIN_PBF_INITIN(v) do{ \ + bFM_GPIO_PCRB_PF=(v).bPullup; \ + bFM_GPIO_DDRB_PF=0u; \ + bFM_GPIO_PFRB_PF=0u; }while(0u) + +#define GPIO1PIN_PBF_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PF=(v).bInitVal; \ + bFM_GPIO_DDRB_PF=1u; \ + bFM_GPIO_PFRB_PF=0u; }while(0u) + +/*---- GPIO bit NPBF ----*/ +#define GPIO1PIN_NPBF_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRB_PF)) ) + +#define GPIO1PIN_NPBF_PUT(v) ( bFM_GPIO_PDORB_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPBF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPBF_INITIN(v) \ + : GPIO1PIN_NPBF_INITOUT(v) ) + +#define GPIO1PIN_NPBF_INITIN(v) do{ \ + bFM_GPIO_PCRB_PF=(v).bPullup; \ + bFM_GPIO_DDRB_PF=0u; \ + bFM_GPIO_PFRB_PF=0u; }while(0u) + +#define GPIO1PIN_NPBF_INITOUT(v) do{ \ + bFM_GPIO_PDORB_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRB_PF=1u; \ + bFM_GPIO_PFRB_PF=0u; }while(0u) + +/*---- GPIO bit PC0 ----*/ +#define GPIO1PIN_PC0_GET ( bFM_GPIO_PDIRC_P0 ) + +#define GPIO1PIN_PC0_PUT(v) ( bFM_GPIO_PDORC_P0=(v) ) + +#define GPIO1PIN_PC0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC0_INITIN(v) \ + : GPIO1PIN_PC0_INITOUT(v) ) + +#define GPIO1PIN_PC0_INITIN(v) do{ \ + bFM_GPIO_PCRC_P0=(v).bPullup; \ + bFM_GPIO_DDRC_P0=0u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +#define GPIO1PIN_PC0_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P0=(v).bInitVal; \ + bFM_GPIO_DDRC_P0=1u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +/*---- GPIO bit NPC0 ----*/ +#define GPIO1PIN_NPC0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P0)) ) + +#define GPIO1PIN_NPC0_PUT(v) ( bFM_GPIO_PDORC_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC0_INITIN(v) \ + : GPIO1PIN_NPC0_INITOUT(v) ) + +#define GPIO1PIN_NPC0_INITIN(v) do{ \ + bFM_GPIO_PCRC_P0=(v).bPullup; \ + bFM_GPIO_DDRC_P0=0u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +#define GPIO1PIN_NPC0_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P0=1u; \ + bFM_GPIO_PFRC_P0=0u; }while(0u) + +/*---- GPIO bit PC1 ----*/ +#define GPIO1PIN_PC1_GET ( bFM_GPIO_PDIRC_P1 ) + +#define GPIO1PIN_PC1_PUT(v) ( bFM_GPIO_PDORC_P1=(v) ) + +#define GPIO1PIN_PC1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC1_INITIN(v) \ + : GPIO1PIN_PC1_INITOUT(v) ) + +#define GPIO1PIN_PC1_INITIN(v) do{ \ + bFM_GPIO_PCRC_P1=(v).bPullup; \ + bFM_GPIO_DDRC_P1=0u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +#define GPIO1PIN_PC1_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P1=(v).bInitVal; \ + bFM_GPIO_DDRC_P1=1u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +/*---- GPIO bit NPC1 ----*/ +#define GPIO1PIN_NPC1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P1)) ) + +#define GPIO1PIN_NPC1_PUT(v) ( bFM_GPIO_PDORC_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC1_INITIN(v) \ + : GPIO1PIN_NPC1_INITOUT(v) ) + +#define GPIO1PIN_NPC1_INITIN(v) do{ \ + bFM_GPIO_PCRC_P1=(v).bPullup; \ + bFM_GPIO_DDRC_P1=0u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +#define GPIO1PIN_NPC1_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P1=1u; \ + bFM_GPIO_PFRC_P1=0u; }while(0u) + +/*---- GPIO bit PC2 ----*/ +#define GPIO1PIN_PC2_GET ( bFM_GPIO_PDIRC_P2 ) + +#define GPIO1PIN_PC2_PUT(v) ( bFM_GPIO_PDORC_P2=(v) ) + +#define GPIO1PIN_PC2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC2_INITIN(v) \ + : GPIO1PIN_PC2_INITOUT(v) ) + +#define GPIO1PIN_PC2_INITIN(v) do{ \ + bFM_GPIO_PCRC_P2=(v).bPullup; \ + bFM_GPIO_DDRC_P2=0u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +#define GPIO1PIN_PC2_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P2=(v).bInitVal; \ + bFM_GPIO_DDRC_P2=1u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +/*---- GPIO bit NPC2 ----*/ +#define GPIO1PIN_NPC2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P2)) ) + +#define GPIO1PIN_NPC2_PUT(v) ( bFM_GPIO_PDORC_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC2_INITIN(v) \ + : GPIO1PIN_NPC2_INITOUT(v) ) + +#define GPIO1PIN_NPC2_INITIN(v) do{ \ + bFM_GPIO_PCRC_P2=(v).bPullup; \ + bFM_GPIO_DDRC_P2=0u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +#define GPIO1PIN_NPC2_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P2=1u; \ + bFM_GPIO_PFRC_P2=0u; }while(0u) + +/*---- GPIO bit PC3 ----*/ +#define GPIO1PIN_PC3_GET ( bFM_GPIO_PDIRC_P3 ) + +#define GPIO1PIN_PC3_PUT(v) ( bFM_GPIO_PDORC_P3=(v) ) + +#define GPIO1PIN_PC3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC3_INITIN(v) \ + : GPIO1PIN_PC3_INITOUT(v) ) + +#define GPIO1PIN_PC3_INITIN(v) do{ \ + bFM_GPIO_PCRC_P3=(v).bPullup; \ + bFM_GPIO_DDRC_P3=0u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +#define GPIO1PIN_PC3_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P3=(v).bInitVal; \ + bFM_GPIO_DDRC_P3=1u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +/*---- GPIO bit NPC3 ----*/ +#define GPIO1PIN_NPC3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P3)) ) + +#define GPIO1PIN_NPC3_PUT(v) ( bFM_GPIO_PDORC_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC3_INITIN(v) \ + : GPIO1PIN_NPC3_INITOUT(v) ) + +#define GPIO1PIN_NPC3_INITIN(v) do{ \ + bFM_GPIO_PCRC_P3=(v).bPullup; \ + bFM_GPIO_DDRC_P3=0u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +#define GPIO1PIN_NPC3_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P3=1u; \ + bFM_GPIO_PFRC_P3=0u; }while(0u) + +/*---- GPIO bit PC4 ----*/ +#define GPIO1PIN_PC4_GET ( bFM_GPIO_PDIRC_P4 ) + +#define GPIO1PIN_PC4_PUT(v) ( bFM_GPIO_PDORC_P4=(v) ) + +#define GPIO1PIN_PC4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC4_INITIN(v) \ + : GPIO1PIN_PC4_INITOUT(v) ) + +#define GPIO1PIN_PC4_INITIN(v) do{ \ + bFM_GPIO_PCRC_P4=(v).bPullup; \ + bFM_GPIO_DDRC_P4=0u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +#define GPIO1PIN_PC4_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P4=(v).bInitVal; \ + bFM_GPIO_DDRC_P4=1u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +/*---- GPIO bit NPC4 ----*/ +#define GPIO1PIN_NPC4_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P4)) ) + +#define GPIO1PIN_NPC4_PUT(v) ( bFM_GPIO_PDORC_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC4_INITIN(v) \ + : GPIO1PIN_NPC4_INITOUT(v) ) + +#define GPIO1PIN_NPC4_INITIN(v) do{ \ + bFM_GPIO_PCRC_P4=(v).bPullup; \ + bFM_GPIO_DDRC_P4=0u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +#define GPIO1PIN_NPC4_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P4=1u; \ + bFM_GPIO_PFRC_P4=0u; }while(0u) + +/*---- GPIO bit PC5 ----*/ +#define GPIO1PIN_PC5_GET ( bFM_GPIO_PDIRC_P5 ) + +#define GPIO1PIN_PC5_PUT(v) ( bFM_GPIO_PDORC_P5=(v) ) + +#define GPIO1PIN_PC5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC5_INITIN(v) \ + : GPIO1PIN_PC5_INITOUT(v) ) + +#define GPIO1PIN_PC5_INITIN(v) do{ \ + bFM_GPIO_PCRC_P5=(v).bPullup; \ + bFM_GPIO_DDRC_P5=0u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +#define GPIO1PIN_PC5_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P5=(v).bInitVal; \ + bFM_GPIO_DDRC_P5=1u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +/*---- GPIO bit NPC5 ----*/ +#define GPIO1PIN_NPC5_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P5)) ) + +#define GPIO1PIN_NPC5_PUT(v) ( bFM_GPIO_PDORC_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC5_INITIN(v) \ + : GPIO1PIN_NPC5_INITOUT(v) ) + +#define GPIO1PIN_NPC5_INITIN(v) do{ \ + bFM_GPIO_PCRC_P5=(v).bPullup; \ + bFM_GPIO_DDRC_P5=0u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +#define GPIO1PIN_NPC5_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P5=1u; \ + bFM_GPIO_PFRC_P5=0u; }while(0u) + +/*---- GPIO bit PC6 ----*/ +#define GPIO1PIN_PC6_GET ( bFM_GPIO_PDIRC_P6 ) + +#define GPIO1PIN_PC6_PUT(v) ( bFM_GPIO_PDORC_P6=(v) ) + +#define GPIO1PIN_PC6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC6_INITIN(v) \ + : GPIO1PIN_PC6_INITOUT(v) ) + +#define GPIO1PIN_PC6_INITIN(v) do{ \ + bFM_GPIO_PCRC_P6=(v).bPullup; \ + bFM_GPIO_DDRC_P6=0u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +#define GPIO1PIN_PC6_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P6=(v).bInitVal; \ + bFM_GPIO_DDRC_P6=1u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +/*---- GPIO bit NPC6 ----*/ +#define GPIO1PIN_NPC6_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P6)) ) + +#define GPIO1PIN_NPC6_PUT(v) ( bFM_GPIO_PDORC_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC6_INITIN(v) \ + : GPIO1PIN_NPC6_INITOUT(v) ) + +#define GPIO1PIN_NPC6_INITIN(v) do{ \ + bFM_GPIO_PCRC_P6=(v).bPullup; \ + bFM_GPIO_DDRC_P6=0u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +#define GPIO1PIN_NPC6_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P6=1u; \ + bFM_GPIO_PFRC_P6=0u; }while(0u) + +/*---- GPIO bit PC7 ----*/ +#define GPIO1PIN_PC7_GET ( bFM_GPIO_PDIRC_P7 ) + +#define GPIO1PIN_PC7_PUT(v) ( bFM_GPIO_PDORC_P7=(v) ) + +#define GPIO1PIN_PC7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC7_INITIN(v) \ + : GPIO1PIN_PC7_INITOUT(v) ) + +#define GPIO1PIN_PC7_INITIN(v) do{ \ + bFM_GPIO_PCRC_P7=(v).bPullup; \ + bFM_GPIO_DDRC_P7=0u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +#define GPIO1PIN_PC7_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P7=(v).bInitVal; \ + bFM_GPIO_DDRC_P7=1u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +/*---- GPIO bit NPC7 ----*/ +#define GPIO1PIN_NPC7_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P7)) ) + +#define GPIO1PIN_NPC7_PUT(v) ( bFM_GPIO_PDORC_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC7_INITIN(v) \ + : GPIO1PIN_NPC7_INITOUT(v) ) + +#define GPIO1PIN_NPC7_INITIN(v) do{ \ + bFM_GPIO_PCRC_P7=(v).bPullup; \ + bFM_GPIO_DDRC_P7=0u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +#define GPIO1PIN_NPC7_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P7=1u; \ + bFM_GPIO_PFRC_P7=0u; }while(0u) + +/*---- GPIO bit PC8 ----*/ +#define GPIO1PIN_PC8_GET ( bFM_GPIO_PDIRC_P8 ) + +#define GPIO1PIN_PC8_PUT(v) ( bFM_GPIO_PDORC_P8=(v) ) + +#define GPIO1PIN_PC8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC8_INITIN(v) \ + : GPIO1PIN_PC8_INITOUT(v) ) + +#define GPIO1PIN_PC8_INITIN(v) do{ \ + bFM_GPIO_PCRC_P8=(v).bPullup; \ + bFM_GPIO_DDRC_P8=0u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +#define GPIO1PIN_PC8_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P8=(v).bInitVal; \ + bFM_GPIO_DDRC_P8=1u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +/*---- GPIO bit NPC8 ----*/ +#define GPIO1PIN_NPC8_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P8)) ) + +#define GPIO1PIN_NPC8_PUT(v) ( bFM_GPIO_PDORC_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC8_INITIN(v) \ + : GPIO1PIN_NPC8_INITOUT(v) ) + +#define GPIO1PIN_NPC8_INITIN(v) do{ \ + bFM_GPIO_PCRC_P8=(v).bPullup; \ + bFM_GPIO_DDRC_P8=0u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +#define GPIO1PIN_NPC8_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P8=1u; \ + bFM_GPIO_PFRC_P8=0u; }while(0u) + +/*---- GPIO bit PC9 ----*/ +#define GPIO1PIN_PC9_GET ( bFM_GPIO_PDIRC_P9 ) + +#define GPIO1PIN_PC9_PUT(v) ( bFM_GPIO_PDORC_P9=(v) ) + +#define GPIO1PIN_PC9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PC9_INITIN(v) \ + : GPIO1PIN_PC9_INITOUT(v) ) + +#define GPIO1PIN_PC9_INITIN(v) do{ \ + bFM_GPIO_PCRC_P9=(v).bPullup; \ + bFM_GPIO_DDRC_P9=0u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +#define GPIO1PIN_PC9_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P9=(v).bInitVal; \ + bFM_GPIO_DDRC_P9=1u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +/*---- GPIO bit NPC9 ----*/ +#define GPIO1PIN_NPC9_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_P9)) ) + +#define GPIO1PIN_NPC9_PUT(v) ( bFM_GPIO_PDORC_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPC9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPC9_INITIN(v) \ + : GPIO1PIN_NPC9_INITOUT(v) ) + +#define GPIO1PIN_NPC9_INITIN(v) do{ \ + bFM_GPIO_PCRC_P9=(v).bPullup; \ + bFM_GPIO_DDRC_P9=0u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +#define GPIO1PIN_NPC9_INITOUT(v) do{ \ + bFM_GPIO_PDORC_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_P9=1u; \ + bFM_GPIO_PFRC_P9=0u; }while(0u) + +/*---- GPIO bit PCA ----*/ +#define GPIO1PIN_PCA_GET ( bFM_GPIO_PDIRC_PA ) + +#define GPIO1PIN_PCA_PUT(v) ( bFM_GPIO_PDORC_PA=(v) ) + +#define GPIO1PIN_PCA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCA_INITIN(v) \ + : GPIO1PIN_PCA_INITOUT(v) ) + +#define GPIO1PIN_PCA_INITIN(v) do{ \ + bFM_GPIO_PCRC_PA=(v).bPullup; \ + bFM_GPIO_DDRC_PA=0u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +#define GPIO1PIN_PCA_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PA=(v).bInitVal; \ + bFM_GPIO_DDRC_PA=1u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +/*---- GPIO bit NPCA ----*/ +#define GPIO1PIN_NPCA_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PA)) ) + +#define GPIO1PIN_NPCA_PUT(v) ( bFM_GPIO_PDORC_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCA_INITIN(v) \ + : GPIO1PIN_NPCA_INITOUT(v) ) + +#define GPIO1PIN_NPCA_INITIN(v) do{ \ + bFM_GPIO_PCRC_PA=(v).bPullup; \ + bFM_GPIO_DDRC_PA=0u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +#define GPIO1PIN_NPCA_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PA=1u; \ + bFM_GPIO_PFRC_PA=0u; }while(0u) + +/*---- GPIO bit PCB ----*/ +#define GPIO1PIN_PCB_GET ( bFM_GPIO_PDIRC_PB ) + +#define GPIO1PIN_PCB_PUT(v) ( bFM_GPIO_PDORC_PB=(v) ) + +#define GPIO1PIN_PCB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCB_INITIN(v) \ + : GPIO1PIN_PCB_INITOUT(v) ) + +#define GPIO1PIN_PCB_INITIN(v) do{ \ + bFM_GPIO_PCRC_PB=(v).bPullup; \ + bFM_GPIO_DDRC_PB=0u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +#define GPIO1PIN_PCB_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PB=(v).bInitVal; \ + bFM_GPIO_DDRC_PB=1u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +/*---- GPIO bit NPCB ----*/ +#define GPIO1PIN_NPCB_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PB)) ) + +#define GPIO1PIN_NPCB_PUT(v) ( bFM_GPIO_PDORC_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCB_INITIN(v) \ + : GPIO1PIN_NPCB_INITOUT(v) ) + +#define GPIO1PIN_NPCB_INITIN(v) do{ \ + bFM_GPIO_PCRC_PB=(v).bPullup; \ + bFM_GPIO_DDRC_PB=0u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +#define GPIO1PIN_NPCB_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PB=1u; \ + bFM_GPIO_PFRC_PB=0u; }while(0u) + +/*---- GPIO bit PCC ----*/ +#define GPIO1PIN_PCC_GET ( bFM_GPIO_PDIRC_PC ) + +#define GPIO1PIN_PCC_PUT(v) ( bFM_GPIO_PDORC_PC=(v) ) + +#define GPIO1PIN_PCC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCC_INITIN(v) \ + : GPIO1PIN_PCC_INITOUT(v) ) + +#define GPIO1PIN_PCC_INITIN(v) do{ \ + bFM_GPIO_PCRC_PC=(v).bPullup; \ + bFM_GPIO_DDRC_PC=0u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +#define GPIO1PIN_PCC_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PC=(v).bInitVal; \ + bFM_GPIO_DDRC_PC=1u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +/*---- GPIO bit NPCC ----*/ +#define GPIO1PIN_NPCC_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PC)) ) + +#define GPIO1PIN_NPCC_PUT(v) ( bFM_GPIO_PDORC_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCC_INITIN(v) \ + : GPIO1PIN_NPCC_INITOUT(v) ) + +#define GPIO1PIN_NPCC_INITIN(v) do{ \ + bFM_GPIO_PCRC_PC=(v).bPullup; \ + bFM_GPIO_DDRC_PC=0u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +#define GPIO1PIN_NPCC_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PC=1u; \ + bFM_GPIO_PFRC_PC=0u; }while(0u) + +/*---- GPIO bit PCD ----*/ +#define GPIO1PIN_PCD_GET ( bFM_GPIO_PDIRC_PD ) + +#define GPIO1PIN_PCD_PUT(v) ( bFM_GPIO_PDORC_PD=(v) ) + +#define GPIO1PIN_PCD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCD_INITIN(v) \ + : GPIO1PIN_PCD_INITOUT(v) ) + +#define GPIO1PIN_PCD_INITIN(v) do{ \ + bFM_GPIO_PCRC_PD=(v).bPullup; \ + bFM_GPIO_DDRC_PD=0u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +#define GPIO1PIN_PCD_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PD=(v).bInitVal; \ + bFM_GPIO_DDRC_PD=1u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +/*---- GPIO bit NPCD ----*/ +#define GPIO1PIN_NPCD_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PD)) ) + +#define GPIO1PIN_NPCD_PUT(v) ( bFM_GPIO_PDORC_PD=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCD_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCD_INITIN(v) \ + : GPIO1PIN_NPCD_INITOUT(v) ) + +#define GPIO1PIN_NPCD_INITIN(v) do{ \ + bFM_GPIO_PCRC_PD=(v).bPullup; \ + bFM_GPIO_DDRC_PD=0u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +#define GPIO1PIN_NPCD_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PD=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PD=1u; \ + bFM_GPIO_PFRC_PD=0u; }while(0u) + +/*---- GPIO bit PCE ----*/ +#define GPIO1PIN_PCE_GET ( bFM_GPIO_PDIRC_PE ) + +#define GPIO1PIN_PCE_PUT(v) ( bFM_GPIO_PDORC_PE=(v) ) + +#define GPIO1PIN_PCE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCE_INITIN(v) \ + : GPIO1PIN_PCE_INITOUT(v) ) + +#define GPIO1PIN_PCE_INITIN(v) do{ \ + bFM_GPIO_PCRC_PE=(v).bPullup; \ + bFM_GPIO_DDRC_PE=0u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +#define GPIO1PIN_PCE_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PE=(v).bInitVal; \ + bFM_GPIO_DDRC_PE=1u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +/*---- GPIO bit NPCE ----*/ +#define GPIO1PIN_NPCE_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PE)) ) + +#define GPIO1PIN_NPCE_PUT(v) ( bFM_GPIO_PDORC_PE=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCE_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCE_INITIN(v) \ + : GPIO1PIN_NPCE_INITOUT(v) ) + +#define GPIO1PIN_NPCE_INITIN(v) do{ \ + bFM_GPIO_PCRC_PE=(v).bPullup; \ + bFM_GPIO_DDRC_PE=0u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +#define GPIO1PIN_NPCE_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PE=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PE=1u; \ + bFM_GPIO_PFRC_PE=0u; }while(0u) + +/*---- GPIO bit PCF ----*/ +#define GPIO1PIN_PCF_GET ( bFM_GPIO_PDIRC_PF ) + +#define GPIO1PIN_PCF_PUT(v) ( bFM_GPIO_PDORC_PF=(v) ) + +#define GPIO1PIN_PCF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PCF_INITIN(v) \ + : GPIO1PIN_PCF_INITOUT(v) ) + +#define GPIO1PIN_PCF_INITIN(v) do{ \ + bFM_GPIO_PCRC_PF=(v).bPullup; \ + bFM_GPIO_DDRC_PF=0u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +#define GPIO1PIN_PCF_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PF=(v).bInitVal; \ + bFM_GPIO_DDRC_PF=1u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +/*---- GPIO bit NPCF ----*/ +#define GPIO1PIN_NPCF_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRC_PF)) ) + +#define GPIO1PIN_NPCF_PUT(v) ( bFM_GPIO_PDORC_PF=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPCF_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPCF_INITIN(v) \ + : GPIO1PIN_NPCF_INITOUT(v) ) + +#define GPIO1PIN_NPCF_INITIN(v) do{ \ + bFM_GPIO_PCRC_PF=(v).bPullup; \ + bFM_GPIO_DDRC_PF=0u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +#define GPIO1PIN_NPCF_INITOUT(v) do{ \ + bFM_GPIO_PDORC_PF=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRC_PF=1u; \ + bFM_GPIO_PFRC_PF=0u; }while(0u) + +/*---- GPIO bit PD0 ----*/ +#define GPIO1PIN_PD0_GET ( bFM_GPIO_PDIRD_P0 ) + +#define GPIO1PIN_PD0_PUT(v) ( bFM_GPIO_PDORD_P0=(v) ) + +#define GPIO1PIN_PD0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PD0_INITIN(v) \ + : GPIO1PIN_PD0_INITOUT(v) ) + +#define GPIO1PIN_PD0_INITIN(v) do{ \ + bFM_GPIO_PCRD_P0=(v).bPullup; \ + bFM_GPIO_DDRD_P0=0u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +#define GPIO1PIN_PD0_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P0=(v).bInitVal; \ + bFM_GPIO_DDRD_P0=1u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +/*---- GPIO bit NPD0 ----*/ +#define GPIO1PIN_NPD0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRD_P0)) ) + +#define GPIO1PIN_NPD0_PUT(v) ( bFM_GPIO_PDORD_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPD0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPD0_INITIN(v) \ + : GPIO1PIN_NPD0_INITOUT(v) ) + +#define GPIO1PIN_NPD0_INITIN(v) do{ \ + bFM_GPIO_PCRD_P0=(v).bPullup; \ + bFM_GPIO_DDRD_P0=0u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +#define GPIO1PIN_NPD0_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRD_P0=1u; \ + bFM_GPIO_PFRD_P0=0u; }while(0u) + +/*---- GPIO bit PD1 ----*/ +#define GPIO1PIN_PD1_GET ( bFM_GPIO_PDIRD_P1 ) + +#define GPIO1PIN_PD1_PUT(v) ( bFM_GPIO_PDORD_P1=(v) ) + +#define GPIO1PIN_PD1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PD1_INITIN(v) \ + : GPIO1PIN_PD1_INITOUT(v) ) + +#define GPIO1PIN_PD1_INITIN(v) do{ \ + bFM_GPIO_PCRD_P1=(v).bPullup; \ + bFM_GPIO_DDRD_P1=0u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +#define GPIO1PIN_PD1_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P1=(v).bInitVal; \ + bFM_GPIO_DDRD_P1=1u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +/*---- GPIO bit NPD1 ----*/ +#define GPIO1PIN_NPD1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRD_P1)) ) + +#define GPIO1PIN_NPD1_PUT(v) ( bFM_GPIO_PDORD_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPD1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPD1_INITIN(v) \ + : GPIO1PIN_NPD1_INITOUT(v) ) + +#define GPIO1PIN_NPD1_INITIN(v) do{ \ + bFM_GPIO_PCRD_P1=(v).bPullup; \ + bFM_GPIO_DDRD_P1=0u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +#define GPIO1PIN_NPD1_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRD_P1=1u; \ + bFM_GPIO_PFRD_P1=0u; }while(0u) + +/*---- GPIO bit PD2 ----*/ +#define GPIO1PIN_PD2_GET ( bFM_GPIO_PDIRD_P2 ) + +#define GPIO1PIN_PD2_PUT(v) ( bFM_GPIO_PDORD_P2=(v) ) + +#define GPIO1PIN_PD2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PD2_INITIN(v) \ + : GPIO1PIN_PD2_INITOUT(v) ) + +#define GPIO1PIN_PD2_INITIN(v) do{ \ + bFM_GPIO_PCRD_P2=(v).bPullup; \ + bFM_GPIO_DDRD_P2=0u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +#define GPIO1PIN_PD2_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P2=(v).bInitVal; \ + bFM_GPIO_DDRD_P2=1u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +/*---- GPIO bit NPD2 ----*/ +#define GPIO1PIN_NPD2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRD_P2)) ) + +#define GPIO1PIN_NPD2_PUT(v) ( bFM_GPIO_PDORD_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPD2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPD2_INITIN(v) \ + : GPIO1PIN_NPD2_INITOUT(v) ) + +#define GPIO1PIN_NPD2_INITIN(v) do{ \ + bFM_GPIO_PCRD_P2=(v).bPullup; \ + bFM_GPIO_DDRD_P2=0u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +#define GPIO1PIN_NPD2_INITOUT(v) do{ \ + bFM_GPIO_PDORD_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRD_P2=1u; \ + bFM_GPIO_PFRD_P2=0u; }while(0u) + +/*---- GPIO bit PE0 ----*/ +#define GPIO1PIN_PE0_GET ( bFM_GPIO_PDIRE_P0 ) + +#define GPIO1PIN_PE0_PUT(v) ( bFM_GPIO_PDORE_P0=(v) ) + +#define GPIO1PIN_PE0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PE0_INITIN(v) \ + : GPIO1PIN_PE0_INITOUT(v) ) + +#define GPIO1PIN_PE0_INITIN(v) do{ \ + bFM_GPIO_PCRE_P0=(v).bPullup; \ + bFM_GPIO_DDRE_P0=0u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +#define GPIO1PIN_PE0_INITOUT(v) do{ \ + bFM_GPIO_PDORE_P0=(v).bInitVal; \ + bFM_GPIO_DDRE_P0=1u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +/*---- GPIO bit NPE0 ----*/ +#define GPIO1PIN_NPE0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRE_P0)) ) + +#define GPIO1PIN_NPE0_PUT(v) ( bFM_GPIO_PDORE_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPE0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPE0_INITIN(v) \ + : GPIO1PIN_NPE0_INITOUT(v) ) + +#define GPIO1PIN_NPE0_INITIN(v) do{ \ + bFM_GPIO_PCRE_P0=(v).bPullup; \ + bFM_GPIO_DDRE_P0=0u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +#define GPIO1PIN_NPE0_INITOUT(v) do{ \ + bFM_GPIO_PDORE_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRE_P0=1u; \ + bFM_GPIO_PFRE_P0=0u; }while(0u) + +/*---- GPIO bit PE2 ----*/ +#define GPIO1PIN_PE2_GET ( bFM_GPIO_PDIRE_P2 ) + +#define GPIO1PIN_PE2_PUT(v) ( bFM_GPIO_PDORE_P2=(v) ) + +#define GPIO1PIN_PE2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PE2_INITIN(v) \ + : GPIO1PIN_PE2_INITOUT(v) ) + +#define GPIO1PIN_PE2_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P2=(v).bPullup; \ + bFM_GPIO_DDRE_P2=0u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +#define GPIO1PIN_PE2_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P2=(v).bInitVal; \ + bFM_GPIO_DDRE_P2=1u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +/*---- GPIO bit NPE2 ----*/ +#define GPIO1PIN_NPE2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRE_P2)) ) + +#define GPIO1PIN_NPE2_PUT(v) ( bFM_GPIO_PDORE_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPE2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPE2_INITIN(v) \ + : GPIO1PIN_NPE2_INITOUT(v) ) + +#define GPIO1PIN_NPE2_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P2=(v).bPullup; \ + bFM_GPIO_DDRE_P2=0u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +#define GPIO1PIN_NPE2_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRE_P2=1u; \ + bFM_GPIO_PFRE_P2=0u; }while(0u) + +/*---- GPIO bit PE3 ----*/ +#define GPIO1PIN_PE3_GET ( bFM_GPIO_PDIRE_P3 ) + +#define GPIO1PIN_PE3_PUT(v) ( bFM_GPIO_PDORE_P3=(v) ) + +#define GPIO1PIN_PE3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PE3_INITIN(v) \ + : GPIO1PIN_PE3_INITOUT(v) ) + +#define GPIO1PIN_PE3_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P3=(v).bPullup; \ + bFM_GPIO_DDRE_P3=0u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +#define GPIO1PIN_PE3_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P3=(v).bInitVal; \ + bFM_GPIO_DDRE_P3=1u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +/*---- GPIO bit NPE3 ----*/ +#define GPIO1PIN_NPE3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRE_P3)) ) + +#define GPIO1PIN_NPE3_PUT(v) ( bFM_GPIO_PDORE_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPE3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPE3_INITIN(v) \ + : GPIO1PIN_NPE3_INITOUT(v) ) + +#define GPIO1PIN_NPE3_INITIN(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PCRE_P3=(v).bPullup; \ + bFM_GPIO_DDRE_P3=0u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +#define GPIO1PIN_NPE3_INITOUT(v) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 0u); \ + bFM_GPIO_PDORE_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRE_P3=1u; \ + bFM_GPIO_PFRE_P3=0u; }while(0u) + +/*---- GPIO bit PF0 ----*/ +#define GPIO1PIN_PF0_GET ( bFM_GPIO_PDIRF_P0 ) + +#define GPIO1PIN_PF0_PUT(v) ( bFM_GPIO_PDORF_P0=(v) ) + +#define GPIO1PIN_PF0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF0_INITIN(v) \ + : GPIO1PIN_PF0_INITOUT(v) ) + +#define GPIO1PIN_PF0_INITIN(v) do{ \ + bFM_GPIO_PCRF_P0=(v).bPullup; \ + bFM_GPIO_DDRF_P0=0u; \ + bFM_GPIO_PFRF_P0=0u; }while(0u) + +#define GPIO1PIN_PF0_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P0=(v).bInitVal; \ + bFM_GPIO_DDRF_P0=1u; \ + bFM_GPIO_PFRF_P0=0u; }while(0u) + +/*---- GPIO bit NPF0 ----*/ +#define GPIO1PIN_NPF0_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P0)) ) + +#define GPIO1PIN_NPF0_PUT(v) ( bFM_GPIO_PDORF_P0=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF0_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF0_INITIN(v) \ + : GPIO1PIN_NPF0_INITOUT(v) ) + +#define GPIO1PIN_NPF0_INITIN(v) do{ \ + bFM_GPIO_PCRF_P0=(v).bPullup; \ + bFM_GPIO_DDRF_P0=0u; \ + bFM_GPIO_PFRF_P0=0u; }while(0u) + +#define GPIO1PIN_NPF0_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P0=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P0=1u; \ + bFM_GPIO_PFRF_P0=0u; }while(0u) + +/*---- GPIO bit PF1 ----*/ +#define GPIO1PIN_PF1_GET ( bFM_GPIO_PDIRF_P1 ) + +#define GPIO1PIN_PF1_PUT(v) ( bFM_GPIO_PDORF_P1=(v) ) + +#define GPIO1PIN_PF1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF1_INITIN(v) \ + : GPIO1PIN_PF1_INITOUT(v) ) + +#define GPIO1PIN_PF1_INITIN(v) do{ \ + bFM_GPIO_PCRF_P1=(v).bPullup; \ + bFM_GPIO_DDRF_P1=0u; \ + bFM_GPIO_PFRF_P1=0u; }while(0u) + +#define GPIO1PIN_PF1_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P1=(v).bInitVal; \ + bFM_GPIO_DDRF_P1=1u; \ + bFM_GPIO_PFRF_P1=0u; }while(0u) + +/*---- GPIO bit NPF1 ----*/ +#define GPIO1PIN_NPF1_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P1)) ) + +#define GPIO1PIN_NPF1_PUT(v) ( bFM_GPIO_PDORF_P1=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF1_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF1_INITIN(v) \ + : GPIO1PIN_NPF1_INITOUT(v) ) + +#define GPIO1PIN_NPF1_INITIN(v) do{ \ + bFM_GPIO_PCRF_P1=(v).bPullup; \ + bFM_GPIO_DDRF_P1=0u; \ + bFM_GPIO_PFRF_P1=0u; }while(0u) + +#define GPIO1PIN_NPF1_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P1=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P1=1u; \ + bFM_GPIO_PFRF_P1=0u; }while(0u) + +/*---- GPIO bit PF2 ----*/ +#define GPIO1PIN_PF2_GET ( bFM_GPIO_PDIRF_P2 ) + +#define GPIO1PIN_PF2_PUT(v) ( bFM_GPIO_PDORF_P2=(v) ) + +#define GPIO1PIN_PF2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF2_INITIN(v) \ + : GPIO1PIN_PF2_INITOUT(v) ) + +#define GPIO1PIN_PF2_INITIN(v) do{ \ + bFM_GPIO_PCRF_P2=(v).bPullup; \ + bFM_GPIO_DDRF_P2=0u; \ + bFM_GPIO_PFRF_P2=0u; }while(0u) + +#define GPIO1PIN_PF2_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P2=(v).bInitVal; \ + bFM_GPIO_DDRF_P2=1u; \ + bFM_GPIO_PFRF_P2=0u; }while(0u) + +/*---- GPIO bit NPF2 ----*/ +#define GPIO1PIN_NPF2_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P2)) ) + +#define GPIO1PIN_NPF2_PUT(v) ( bFM_GPIO_PDORF_P2=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF2_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF2_INITIN(v) \ + : GPIO1PIN_NPF2_INITOUT(v) ) + +#define GPIO1PIN_NPF2_INITIN(v) do{ \ + bFM_GPIO_PCRF_P2=(v).bPullup; \ + bFM_GPIO_DDRF_P2=0u; \ + bFM_GPIO_PFRF_P2=0u; }while(0u) + +#define GPIO1PIN_NPF2_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P2=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P2=1u; \ + bFM_GPIO_PFRF_P2=0u; }while(0u) + +/*---- GPIO bit PF3 ----*/ +#define GPIO1PIN_PF3_GET ( bFM_GPIO_PDIRF_P3 ) + +#define GPIO1PIN_PF3_PUT(v) ( bFM_GPIO_PDORF_P3=(v) ) + +#define GPIO1PIN_PF3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF3_INITIN(v) \ + : GPIO1PIN_PF3_INITOUT(v) ) + +#define GPIO1PIN_PF3_INITIN(v) do{ \ + bFM_GPIO_PCRF_P3=(v).bPullup; \ + bFM_GPIO_DDRF_P3=0u; \ + bFM_GPIO_PFRF_P3=0u; }while(0u) + +#define GPIO1PIN_PF3_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P3=(v).bInitVal; \ + bFM_GPIO_DDRF_P3=1u; \ + bFM_GPIO_PFRF_P3=0u; }while(0u) + +/*---- GPIO bit NPF3 ----*/ +#define GPIO1PIN_NPF3_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P3)) ) + +#define GPIO1PIN_NPF3_PUT(v) ( bFM_GPIO_PDORF_P3=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF3_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF3_INITIN(v) \ + : GPIO1PIN_NPF3_INITOUT(v) ) + +#define GPIO1PIN_NPF3_INITIN(v) do{ \ + bFM_GPIO_PCRF_P3=(v).bPullup; \ + bFM_GPIO_DDRF_P3=0u; \ + bFM_GPIO_PFRF_P3=0u; }while(0u) + +#define GPIO1PIN_NPF3_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P3=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P3=1u; \ + bFM_GPIO_PFRF_P3=0u; }while(0u) + +/*---- GPIO bit PF4 ----*/ +#define GPIO1PIN_PF4_GET ( bFM_GPIO_PDIRF_P4 ) + +#define GPIO1PIN_PF4_PUT(v) ( bFM_GPIO_PDORF_P4=(v) ) + +#define GPIO1PIN_PF4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF4_INITIN(v) \ + : GPIO1PIN_PF4_INITOUT(v) ) + +#define GPIO1PIN_PF4_INITIN(v) do{ \ + bFM_GPIO_PCRF_P4=(v).bPullup; \ + bFM_GPIO_DDRF_P4=0u; \ + bFM_GPIO_PFRF_P4=0u; }while(0u) + +#define GPIO1PIN_PF4_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P4=(v).bInitVal; \ + bFM_GPIO_DDRF_P4=1u; \ + bFM_GPIO_PFRF_P4=0u; }while(0u) + +/*---- GPIO bit NPF4 ----*/ +#define GPIO1PIN_NPF4_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P4)) ) + +#define GPIO1PIN_NPF4_PUT(v) ( bFM_GPIO_PDORF_P4=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF4_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF4_INITIN(v) \ + : GPIO1PIN_NPF4_INITOUT(v) ) + +#define GPIO1PIN_NPF4_INITIN(v) do{ \ + bFM_GPIO_PCRF_P4=(v).bPullup; \ + bFM_GPIO_DDRF_P4=0u; \ + bFM_GPIO_PFRF_P4=0u; }while(0u) + +#define GPIO1PIN_NPF4_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P4=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P4=1u; \ + bFM_GPIO_PFRF_P4=0u; }while(0u) + +/*---- GPIO bit PF5 ----*/ +#define GPIO1PIN_PF5_GET ( bFM_GPIO_PDIRF_P5 ) + +#define GPIO1PIN_PF5_PUT(v) ( bFM_GPIO_PDORF_P5=(v) ) + +#define GPIO1PIN_PF5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF5_INITIN(v) \ + : GPIO1PIN_PF5_INITOUT(v) ) + +#define GPIO1PIN_PF5_INITIN(v) do{ \ + bFM_GPIO_PCRF_P5=(v).bPullup; \ + bFM_GPIO_DDRF_P5=0u; \ + bFM_GPIO_PFRF_P5=0u; }while(0u) + +#define GPIO1PIN_PF5_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P5=(v).bInitVal; \ + bFM_GPIO_DDRF_P5=1u; \ + bFM_GPIO_PFRF_P5=0u; }while(0u) + +/*---- GPIO bit NPF5 ----*/ +#define GPIO1PIN_NPF5_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P5)) ) + +#define GPIO1PIN_NPF5_PUT(v) ( bFM_GPIO_PDORF_P5=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF5_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF5_INITIN(v) \ + : GPIO1PIN_NPF5_INITOUT(v) ) + +#define GPIO1PIN_NPF5_INITIN(v) do{ \ + bFM_GPIO_PCRF_P5=(v).bPullup; \ + bFM_GPIO_DDRF_P5=0u; \ + bFM_GPIO_PFRF_P5=0u; }while(0u) + +#define GPIO1PIN_NPF5_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P5=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P5=1u; \ + bFM_GPIO_PFRF_P5=0u; }while(0u) + +/*---- GPIO bit PF6 ----*/ +#define GPIO1PIN_PF6_GET ( bFM_GPIO_PDIRF_P6 ) + +#define GPIO1PIN_PF6_PUT(v) ( bFM_GPIO_PDORF_P6=(v) ) + +#define GPIO1PIN_PF6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF6_INITIN(v) \ + : GPIO1PIN_PF6_INITOUT(v) ) + +#define GPIO1PIN_PF6_INITIN(v) do{ \ + bFM_GPIO_PCRF_P6=(v).bPullup; \ + bFM_GPIO_DDRF_P6=0u; \ + bFM_GPIO_PFRF_P6=0u; }while(0u) + +#define GPIO1PIN_PF6_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P6=(v).bInitVal; \ + bFM_GPIO_DDRF_P6=1u; \ + bFM_GPIO_PFRF_P6=0u; }while(0u) + +/*---- GPIO bit NPF6 ----*/ +#define GPIO1PIN_NPF6_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P6)) ) + +#define GPIO1PIN_NPF6_PUT(v) ( bFM_GPIO_PDORF_P6=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF6_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF6_INITIN(v) \ + : GPIO1PIN_NPF6_INITOUT(v) ) + +#define GPIO1PIN_NPF6_INITIN(v) do{ \ + bFM_GPIO_PCRF_P6=(v).bPullup; \ + bFM_GPIO_DDRF_P6=0u; \ + bFM_GPIO_PFRF_P6=0u; }while(0u) + +#define GPIO1PIN_NPF6_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P6=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P6=1u; \ + bFM_GPIO_PFRF_P6=0u; }while(0u) + +/*---- GPIO bit PF7 ----*/ +#define GPIO1PIN_PF7_GET ( bFM_GPIO_PDIRF_P7 ) + +#define GPIO1PIN_PF7_PUT(v) ( bFM_GPIO_PDORF_P7=(v) ) + +#define GPIO1PIN_PF7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF7_INITIN(v) \ + : GPIO1PIN_PF7_INITOUT(v) ) + +#define GPIO1PIN_PF7_INITIN(v) do{ \ + bFM_GPIO_PCRF_P7=(v).bPullup; \ + bFM_GPIO_DDRF_P7=0u; \ + bFM_GPIO_PFRF_P7=0u; }while(0u) + +#define GPIO1PIN_PF7_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P7=(v).bInitVal; \ + bFM_GPIO_DDRF_P7=1u; \ + bFM_GPIO_PFRF_P7=0u; }while(0u) + +/*---- GPIO bit NPF7 ----*/ +#define GPIO1PIN_NPF7_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P7)) ) + +#define GPIO1PIN_NPF7_PUT(v) ( bFM_GPIO_PDORF_P7=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF7_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF7_INITIN(v) \ + : GPIO1PIN_NPF7_INITOUT(v) ) + +#define GPIO1PIN_NPF7_INITIN(v) do{ \ + bFM_GPIO_PCRF_P7=(v).bPullup; \ + bFM_GPIO_DDRF_P7=0u; \ + bFM_GPIO_PFRF_P7=0u; }while(0u) + +#define GPIO1PIN_NPF7_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P7=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P7=1u; \ + bFM_GPIO_PFRF_P7=0u; }while(0u) + +/*---- GPIO bit PF8 ----*/ +#define GPIO1PIN_PF8_GET ( bFM_GPIO_PDIRF_P8 ) + +#define GPIO1PIN_PF8_PUT(v) ( bFM_GPIO_PDORF_P8=(v) ) + +#define GPIO1PIN_PF8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF8_INITIN(v) \ + : GPIO1PIN_PF8_INITOUT(v) ) + +#define GPIO1PIN_PF8_INITIN(v) do{ \ + bFM_GPIO_PCRF_P8=(v).bPullup; \ + bFM_GPIO_DDRF_P8=0u; \ + bFM_GPIO_PFRF_P8=0u; }while(0u) + +#define GPIO1PIN_PF8_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P8=(v).bInitVal; \ + bFM_GPIO_DDRF_P8=1u; \ + bFM_GPIO_PFRF_P8=0u; }while(0u) + +/*---- GPIO bit NPF8 ----*/ +#define GPIO1PIN_NPF8_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P8)) ) + +#define GPIO1PIN_NPF8_PUT(v) ( bFM_GPIO_PDORF_P8=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF8_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF8_INITIN(v) \ + : GPIO1PIN_NPF8_INITOUT(v) ) + +#define GPIO1PIN_NPF8_INITIN(v) do{ \ + bFM_GPIO_PCRF_P8=(v).bPullup; \ + bFM_GPIO_DDRF_P8=0u; \ + bFM_GPIO_PFRF_P8=0u; }while(0u) + +#define GPIO1PIN_NPF8_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P8=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P8=1u; \ + bFM_GPIO_PFRF_P8=0u; }while(0u) + +/*---- GPIO bit PF9 ----*/ +#define GPIO1PIN_PF9_GET ( bFM_GPIO_PDIRF_P9 ) + +#define GPIO1PIN_PF9_PUT(v) ( bFM_GPIO_PDORF_P9=(v) ) + +#define GPIO1PIN_PF9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PF9_INITIN(v) \ + : GPIO1PIN_PF9_INITOUT(v) ) + +#define GPIO1PIN_PF9_INITIN(v) do{ \ + bFM_GPIO_PCRF_P9=(v).bPullup; \ + bFM_GPIO_DDRF_P9=0u; \ + bFM_GPIO_PFRF_P9=0u; }while(0u) + +#define GPIO1PIN_PF9_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P9=(v).bInitVal; \ + bFM_GPIO_DDRF_P9=1u; \ + bFM_GPIO_PFRF_P9=0u; }while(0u) + +/*---- GPIO bit NPF9 ----*/ +#define GPIO1PIN_NPF9_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_P9)) ) + +#define GPIO1PIN_NPF9_PUT(v) ( bFM_GPIO_PDORF_P9=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPF9_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPF9_INITIN(v) \ + : GPIO1PIN_NPF9_INITOUT(v) ) + +#define GPIO1PIN_NPF9_INITIN(v) do{ \ + bFM_GPIO_PCRF_P9=(v).bPullup; \ + bFM_GPIO_DDRF_P9=0u; \ + bFM_GPIO_PFRF_P9=0u; }while(0u) + +#define GPIO1PIN_NPF9_INITOUT(v) do{ \ + bFM_GPIO_PDORF_P9=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_P9=1u; \ + bFM_GPIO_PFRF_P9=0u; }while(0u) + +/*---- GPIO bit PFA ----*/ +#define GPIO1PIN_PFA_GET ( bFM_GPIO_PDIRF_PA ) + +#define GPIO1PIN_PFA_PUT(v) ( bFM_GPIO_PDORF_PA=(v) ) + +#define GPIO1PIN_PFA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PFA_INITIN(v) \ + : GPIO1PIN_PFA_INITOUT(v) ) + +#define GPIO1PIN_PFA_INITIN(v) do{ \ + bFM_GPIO_PCRF_PA=(v).bPullup; \ + bFM_GPIO_DDRF_PA=0u; \ + bFM_GPIO_PFRF_PA=0u; }while(0u) + +#define GPIO1PIN_PFA_INITOUT(v) do{ \ + bFM_GPIO_PDORF_PA=(v).bInitVal; \ + bFM_GPIO_DDRF_PA=1u; \ + bFM_GPIO_PFRF_PA=0u; }while(0u) + +/*---- GPIO bit NPFA ----*/ +#define GPIO1PIN_NPFA_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_PA)) ) + +#define GPIO1PIN_NPFA_PUT(v) ( bFM_GPIO_PDORF_PA=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPFA_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPFA_INITIN(v) \ + : GPIO1PIN_NPFA_INITOUT(v) ) + +#define GPIO1PIN_NPFA_INITIN(v) do{ \ + bFM_GPIO_PCRF_PA=(v).bPullup; \ + bFM_GPIO_DDRF_PA=0u; \ + bFM_GPIO_PFRF_PA=0u; }while(0u) + +#define GPIO1PIN_NPFA_INITOUT(v) do{ \ + bFM_GPIO_PDORF_PA=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_PA=1u; \ + bFM_GPIO_PFRF_PA=0u; }while(0u) + +/*---- GPIO bit PFB ----*/ +#define GPIO1PIN_PFB_GET ( bFM_GPIO_PDIRF_PB ) + +#define GPIO1PIN_PFB_PUT(v) ( bFM_GPIO_PDORF_PB=(v) ) + +#define GPIO1PIN_PFB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PFB_INITIN(v) \ + : GPIO1PIN_PFB_INITOUT(v) ) + +#define GPIO1PIN_PFB_INITIN(v) do{ \ + bFM_GPIO_PCRF_PB=(v).bPullup; \ + bFM_GPIO_DDRF_PB=0u; \ + bFM_GPIO_PFRF_PB=0u; }while(0u) + +#define GPIO1PIN_PFB_INITOUT(v) do{ \ + bFM_GPIO_PDORF_PB=(v).bInitVal; \ + bFM_GPIO_DDRF_PB=1u; \ + bFM_GPIO_PFRF_PB=0u; }while(0u) + +/*---- GPIO bit NPFB ----*/ +#define GPIO1PIN_NPFB_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_PB)) ) + +#define GPIO1PIN_NPFB_PUT(v) ( bFM_GPIO_PDORF_PB=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPFB_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPFB_INITIN(v) \ + : GPIO1PIN_NPFB_INITOUT(v) ) + +#define GPIO1PIN_NPFB_INITIN(v) do{ \ + bFM_GPIO_PCRF_PB=(v).bPullup; \ + bFM_GPIO_DDRF_PB=0u; \ + bFM_GPIO_PFRF_PB=0u; }while(0u) + +#define GPIO1PIN_NPFB_INITOUT(v) do{ \ + bFM_GPIO_PDORF_PB=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_PB=1u; \ + bFM_GPIO_PFRF_PB=0u; }while(0u) + +/*---- GPIO bit PFC ----*/ +#define GPIO1PIN_PFC_GET ( bFM_GPIO_PDIRF_PC ) + +#define GPIO1PIN_PFC_PUT(v) ( bFM_GPIO_PDORF_PC=(v) ) + +#define GPIO1PIN_PFC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_PFC_INITIN(v) \ + : GPIO1PIN_PFC_INITOUT(v) ) + +#define GPIO1PIN_PFC_INITIN(v) do{ \ + bFM_GPIO_PCRF_PC=(v).bPullup; \ + bFM_GPIO_DDRF_PC=0u; \ + bFM_GPIO_PFRF_PC=0u; }while(0u) + +#define GPIO1PIN_PFC_INITOUT(v) do{ \ + bFM_GPIO_PDORF_PC=(v).bInitVal; \ + bFM_GPIO_DDRF_PC=1u; \ + bFM_GPIO_PFRF_PC=0u; }while(0u) + +/*---- GPIO bit NPFC ----*/ +#define GPIO1PIN_NPFC_GET ( (uint32_t)(!(uint32_t)(bFM_GPIO_PDIRF_PC)) ) + +#define GPIO1PIN_NPFC_PUT(v) ( bFM_GPIO_PDORF_PC=(uint32_t)(!(v)) ) + +#define GPIO1PIN_NPFC_INIT(v) ( (0==(v).bOutput) ? GPIO1PIN_NPFC_INITIN(v) \ + : GPIO1PIN_NPFC_INITOUT(v) ) + +#define GPIO1PIN_NPFC_INITIN(v) do{ \ + bFM_GPIO_PCRF_PC=(v).bPullup; \ + bFM_GPIO_DDRF_PC=0u; \ + bFM_GPIO_PFRF_PC=0u; }while(0u) + +#define GPIO1PIN_NPFC_INITOUT(v) do{ \ + bFM_GPIO_PDORF_PC=(uint32_t)(!((uint32_t)(v).bInitVal)); \ + bFM_GPIO_DDRF_PC=1u; \ + bFM_GPIO_PFRF_PC=0u; }while(0u) + +/****************************************************************************** + PIN RELOCATION +*******************************************************************************/ + +/*--- ADTG_0_ADC0 ---*/ +#define SetPinFunc_ADTG_0_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ADTG_0_ADC1 ---*/ +#define SetPinFunc_ADTG_0_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ADTG_0_ADC2 ---*/ +#define SetPinFunc_ADTG_0_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ADTG_1_ADC0 ---*/ +#define SetPinFunc_ADTG_1_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- ADTG_1_ADC1 ---*/ +#define SetPinFunc_ADTG_1_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- ADTG_1_ADC2 ---*/ +#define SetPinFunc_ADTG_1_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- ADTG_2_ADC0 ---*/ +#define SetPinFunc_ADTG_2_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 3u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- ADTG_2_ADC1 ---*/ +#define SetPinFunc_ADTG_2_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 3u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- ADTG_2_ADC2 ---*/ +#define SetPinFunc_ADTG_2_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 3u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- ADTG_3_ADC0 ---*/ +#define SetPinFunc_ADTG_3_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 4u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- ADTG_3_ADC1 ---*/ +#define SetPinFunc_ADTG_3_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 4u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- ADTG_3_ADC2 ---*/ +#define SetPinFunc_ADTG_3_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 4u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- ADTG_4_ADC0 ---*/ +#define SetPinFunc_ADTG_4_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 5u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- ADTG_4_ADC1 ---*/ +#define SetPinFunc_ADTG_4_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 5u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- ADTG_4_ADC2 ---*/ +#define SetPinFunc_ADTG_4_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 5u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- ADTG_5_ADC0 ---*/ +#define SetPinFunc_ADTG_5_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 6u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- ADTG_5_ADC1 ---*/ +#define SetPinFunc_ADTG_5_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 6u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- ADTG_5_ADC2 ---*/ +#define SetPinFunc_ADTG_5_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 6u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- ADTG_6_ADC0 ---*/ +#define SetPinFunc_ADTG_6_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 7u ); \ + bFM_GPIO_PFRB_P8 = 1u; \ + }while (0u) + +/*--- ADTG_6_ADC1 ---*/ +#define SetPinFunc_ADTG_6_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 7u ); \ + bFM_GPIO_PFRB_P8 = 1u; \ + }while (0u) + +/*--- ADTG_6_ADC2 ---*/ +#define SetPinFunc_ADTG_6_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 7u ); \ + bFM_GPIO_PFRB_P8 = 1u; \ + }while (0u) + +/*--- ADTG_7_ADC0 ---*/ +#define SetPinFunc_ADTG_7_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 8u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- ADTG_7_ADC1 ---*/ +#define SetPinFunc_ADTG_7_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 8u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- ADTG_7_ADC2 ---*/ +#define SetPinFunc_ADTG_7_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 8u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- ADTG_8_ADC0 ---*/ +#define SetPinFunc_ADTG_8_ADC0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 12u, 4u, 9u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- ADTG_8_ADC1 ---*/ +#define SetPinFunc_ADTG_8_ADC1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 16u, 4u, 9u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- ADTG_8_ADC2 ---*/ +#define SetPinFunc_ADTG_8_ADC2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 20u, 4u, 9u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- AIN0_0 ---*/ +#define SetPinFunc_AIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 0u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- AIN0_1 ---*/ +#define SetPinFunc_AIN0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 0u, 2u, 2u ); \ + bFM_GPIO_PFR4_PA = 1u; \ + }while (0u) + +/*--- AIN0_2 ---*/ +#define SetPinFunc_AIN0_2(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 0u, 2u, 3u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- AIN1_0 ---*/ +#define SetPinFunc_AIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 6u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- AIN1_1 ---*/ +#define SetPinFunc_AIN1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 6u, 2u, 2u ); \ + bFM_GPIO_PFRF_P8 = 1u; \ + }while (0u) + +/*--- AIN1_2 ---*/ +#define SetPinFunc_AIN1_2(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 6u, 2u, 3u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- AIN2_0 ---*/ +#define SetPinFunc_AIN2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- AIN2_1 ---*/ +#define SetPinFunc_AIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 0u, 2u, 2u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- AIN2_2 ---*/ +#define SetPinFunc_AIN2_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 0u, 2u, 3u ); \ + bFM_GPIO_PFRB_P9 = 1u; \ + }while (0u) + +/*--- AIN3_0 ---*/ +#define SetPinFunc_AIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- AIN3_1 ---*/ +#define SetPinFunc_AIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- AIN3_2 ---*/ +#define SetPinFunc_AIN3_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 4u, 2u, 3u ); \ + bFM_GPIO_PFRB_PD = 1u; \ + }while (0u) + +/*--- BIN0_0 ---*/ +#define SetPinFunc_BIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- BIN0_1 ---*/ +#define SetPinFunc_BIN0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 2u, 2u, 2u ); \ + bFM_GPIO_PFR4_PB = 1u; \ + }while (0u) + +/*--- BIN0_2 ---*/ +#define SetPinFunc_BIN0_2(dummy) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 2u, 2u, 3u ); \ + bFM_GPIO_PFR1_P1 = 1u; \ + }while (0u) + +/*--- BIN1_0 ---*/ +#define SetPinFunc_BIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 8u, 2u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- BIN1_1 ---*/ +#define SetPinFunc_BIN1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 8u, 2u, 2u ); \ + bFM_GPIO_PFRF_P9 = 1u; \ + }while (0u) + +/*--- BIN1_2 ---*/ +#define SetPinFunc_BIN1_2(dummy) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 8u, 2u, 3u ); \ + bFM_GPIO_PFR1_P6 = 1u; \ + }while (0u) + +/*--- BIN2_0 ---*/ +#define SetPinFunc_BIN2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- BIN2_1 ---*/ +#define SetPinFunc_BIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_P2 = 1u; \ + }while (0u) + +/*--- BIN2_2 ---*/ +#define SetPinFunc_BIN2_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 2u, 2u, 3u ); \ + bFM_GPIO_PFRB_PA = 1u; \ + }while (0u) + +/*--- BIN3_0 ---*/ +#define SetPinFunc_BIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 6u, 2u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- BIN3_1 ---*/ +#define SetPinFunc_BIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 6u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- BIN3_2 ---*/ +#define SetPinFunc_BIN3_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 6u, 2u, 3u ); \ + bFM_GPIO_PFRB_PE = 1u; \ + }while (0u) + +/*--- CROUT_0 ---*/ +#define SetPinFunc_CROUT_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 1u, 2u, 1u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- CROUT_1 ---*/ +#define SetPinFunc_CROUT_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 1u, 2u, 2u ); \ + bFM_GPIO_PFRC_P7 = 1u; \ + }while (0u) + +/*--- CTS4_0 ---*/ +#define SetPinFunc_CTS4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 2u, 2u, 1u ); \ + bFM_GPIO_PFR6_P4 = 1u; \ + }while (0u) + +/*--- CTS4_1 ---*/ +#define SetPinFunc_CTS4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 2u, 2u, 2u ); \ + bFM_GPIO_PFRD_P2 = 1u; \ + }while (0u) + +/*--- CTS5_0 ---*/ +#define SetPinFunc_CTS5_0(dummy) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 30u, 2u, 1u ); \ + bFM_GPIO_PFR2_PA = 1u; \ + }while (0u) + +/*--- CTS5_1 ---*/ +#define SetPinFunc_CTS5_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 30u, 2u, 2u ); \ + bFM_GPIO_PFR9_P4 = 1u; \ + }while (0u) + +/*--- DA0 ---*/ +#define SetPinFunc_DA0(dummy) do{ \ + /* bFM_DAC0_DACR_DAE=1u; */ \ + }while (0u) + +/*--- DA1 ---*/ +#define SetPinFunc_DA1(dummy) do{ \ + /* bFM_DAC1_DACR_DAE=1u; */ \ + }while (0u) + +/*--- DTTI0X_0 ---*/ +#define SetPinFunc_DTTI0X_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 16u, 2u, 1u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- DTTI0X_1 ---*/ +#define SetPinFunc_DTTI0X_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 16u, 2u, 2u ); \ + bFM_GPIO_PFR5_P6 = 1u; \ + }while (0u) + +/*--- DTTI1X_0 ---*/ +#define SetPinFunc_DTTI1X_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 16u, 2u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- DTTI1X_1 ---*/ +#define SetPinFunc_DTTI1X_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 16u, 2u, 2u ); \ + bFM_GPIO_PFRF_P8 = 1u; \ + }while (0u) + +/*--- DTTI2X_0 ---*/ +#define SetPinFunc_DTTI2X_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 16u, 2u, 1u ); \ + bFM_GPIO_PFRA_P6 = 1u; \ + }while (0u) + +/*--- DTTI2X_1 ---*/ +#define SetPinFunc_DTTI2X_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 16u, 2u, 2u ); \ + bFM_GPIO_PFR6_PA = 1u; \ + }while (0u) + +/*--- FRCK0_0 ---*/ +#define SetPinFunc_FRCK0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 18u, 2u, 1u ); \ + bFM_GPIO_PFR3_P3 = 1u; \ + }while (0u) + +/*--- FRCK0_1 ---*/ +#define SetPinFunc_FRCK0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 18u, 2u, 2u ); \ + bFM_GPIO_PFR5_PB = 1u; \ + }while (0u) + +/*--- FRCK1_0 ---*/ +#define SetPinFunc_FRCK1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 18u, 2u, 1u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- FRCK1_1 ---*/ +#define SetPinFunc_FRCK1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 18u, 2u, 2u ); \ + bFM_GPIO_PFRF_P0 = 1u; \ + }while (0u) + +/*--- FRCK2_0 ---*/ +#define SetPinFunc_FRCK2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 18u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- FRCK2_1 ---*/ +#define SetPinFunc_FRCK2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 18u, 2u, 2u ); \ + bFM_GPIO_PFRD_P2 = 1u; \ + }while (0u) + +/*--- I2SCK0_0 ---*/ +#define SetPinFunc_I2SCK0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR24, 4u, 2u, 1u ); \ + bFM_GPIO_PFR3_P1 = 1u; \ + }while (0u) + +/*--- I2SDI0_0 ---*/ +#define SetPinFunc_I2SDI0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR24, 8u, 2u, 1u ); \ + bFM_GPIO_PFR3_P0 = 1u; \ + }while (0u) + +/*--- I2SDO0_0 ---*/ +#define SetPinFunc_I2SDO0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR24, 10u, 2u, 1u ); \ + bFM_GPIO_PFR5_PE = 1u; \ + }while (0u) + +/*--- I2SMCLK0_0_OUT ---*/ +#define SetPinFunc_I2SMCLK0_0_OUT(dummy)do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR24, 2u, 2u, 1u ); \ + bFM_GPIO_PFR5_PD = 1u; \ + }while (0u) + +/*--- I2SMCLK0_0_IN ---*/ +#define SetPinFunc_I2SMCLK0_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR24, 0u, 2u, 1u ); \ + bFM_GPIO_PFR5_PD = 1u; \ + }while (0u) + +/*--- I2SWS0_0 ---*/ +#define SetPinFunc_I2SWS0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR24, 6u, 2u, 1u ); \ + bFM_GPIO_PFR5_PF = 1u; \ + }while (0u) + +/*--- IC00_0 ---*/ +#define SetPinFunc_IC00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 1u ); \ + bFM_GPIO_PFR3_P7 = 1u; \ + }while (0u) + +/*--- IC00_1 ---*/ +#define SetPinFunc_IC00_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 2u ); \ + bFM_GPIO_PFR5_P7 = 1u; \ + }while (0u) + +/*--- IC00_LSYN0 ---*/ +#define SetPinFunc_IC00_LSYN0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 4u ); \ + }while (0u) + +/*--- IC00_LSYN4 ---*/ +#define SetPinFunc_IC00_LSYN4(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 20u, 3u, 5u ); \ + }while (0u) + +/*--- IC01_0 ---*/ +#define SetPinFunc_IC01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 1u ); \ + bFM_GPIO_PFR3_P6 = 1u; \ + }while (0u) + +/*--- IC01_1 ---*/ +#define SetPinFunc_IC01_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 2u ); \ + bFM_GPIO_PFR5_P8 = 1u; \ + }while (0u) + +/*--- IC01_LSYN1 ---*/ +#define SetPinFunc_IC01_LSYN1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 4u ); \ + }while (0u) + +/*--- IC01_LSYN5 ---*/ +#define SetPinFunc_IC01_LSYN5(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 23u, 3u, 5u ); \ + }while (0u) + +/*--- IC02_0 ---*/ +#define SetPinFunc_IC02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 1u ); \ + bFM_GPIO_PFR3_P5 = 1u; \ + }while (0u) + +/*--- IC02_1 ---*/ +#define SetPinFunc_IC02_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 2u ); \ + bFM_GPIO_PFR5_P9 = 1u; \ + }while (0u) + +/*--- IC02_LSYN2 ---*/ +#define SetPinFunc_IC02_LSYN2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 4u ); \ + }while (0u) + +/*--- IC02_LSYN6 ---*/ +#define SetPinFunc_IC02_LSYN6(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 26u, 3u, 5u ); \ + }while (0u) + +/*--- IC03_0 ---*/ +#define SetPinFunc_IC03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 1u ); \ + bFM_GPIO_PFR3_P4 = 1u; \ + }while (0u) + +/*--- IC03_1 ---*/ +#define SetPinFunc_IC03_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 2u ); \ + bFM_GPIO_PFR5_PA = 1u; \ + }while (0u) + +/*--- IC03_LSYN3 ---*/ +#define SetPinFunc_IC03_LSYN3(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 4u ); \ + }while (0u) + +/*--- IC03_LSYN7 ---*/ +#define SetPinFunc_IC03_LSYN7(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 29u, 3u, 5u ); \ + }while (0u) + +/*--- IC10_0 ---*/ +#define SetPinFunc_IC10_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- IC10_1 ---*/ +#define SetPinFunc_IC10_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 2u ); \ + bFM_GPIO_PFRF_P9 = 1u; \ + }while (0u) + +/*--- IC10_LSYN0 ---*/ +#define SetPinFunc_IC10_LSYN0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 4u ); \ + }while (0u) + +/*--- IC10_LSYN4 ---*/ +#define SetPinFunc_IC10_LSYN4(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 20u, 3u, 5u ); \ + }while (0u) + +/*--- IC11_0 ---*/ +#define SetPinFunc_IC11_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 1u ); \ + bFM_GPIO_PFR7_P9 = 1u; \ + }while (0u) + +/*--- IC11_1 ---*/ +#define SetPinFunc_IC11_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 2u ); \ + bFM_GPIO_PFRF_PA = 1u; \ + }while (0u) + +/*--- IC11_LSYN1 ---*/ +#define SetPinFunc_IC11_LSYN1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 4u ); \ + }while (0u) + +/*--- IC11_LSYN5 ---*/ +#define SetPinFunc_IC11_LSYN5(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 23u, 3u, 5u ); \ + }while (0u) + +/*--- IC12_0 ---*/ +#define SetPinFunc_IC12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 1u ); \ + bFM_GPIO_PFR7_PA = 1u; \ + }while (0u) + +/*--- IC12_1 ---*/ +#define SetPinFunc_IC12_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 2u ); \ + bFM_GPIO_PFRF_PB = 1u; \ + }while (0u) + +/*--- IC12_LSYN2 ---*/ +#define SetPinFunc_IC12_LSYN2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 4u ); \ + }while (0u) + +/*--- IC12_LSYN6 ---*/ +#define SetPinFunc_IC12_LSYN6(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 26u, 3u, 5u ); \ + }while (0u) + +/*--- IC13_0 ---*/ +#define SetPinFunc_IC13_0(dummy) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 1u ); \ + bFM_GPIO_PFR7_PB = 1u; \ + }while (0u) + +/*--- IC13_1 ---*/ +#define SetPinFunc_IC13_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 2u ); \ + bFM_GPIO_PFRF_PC = 1u; \ + }while (0u) + +/*--- IC13_LSYN3 ---*/ +#define SetPinFunc_IC13_LSYN3(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 4u ); \ + }while (0u) + +/*--- IC13_LSYN7 ---*/ +#define SetPinFunc_IC13_LSYN7(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 29u, 3u, 5u ); \ + }while (0u) + +/*--- IC20_0 ---*/ +#define SetPinFunc_IC20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 1u ); \ + bFM_GPIO_PFRA_P7 = 1u; \ + }while (0u) + +/*--- IC20_1 ---*/ +#define SetPinFunc_IC20_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 2u ); \ + bFM_GPIO_PFR6_PB = 1u; \ + }while (0u) + +/*--- IC20_LSYN0 ---*/ +#define SetPinFunc_IC20_LSYN0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 4u ); \ + }while (0u) + +/*--- IC20_LSYN4 ---*/ +#define SetPinFunc_IC20_LSYN4(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 20u, 3u, 5u ); \ + }while (0u) + +/*--- IC21_0 ---*/ +#define SetPinFunc_IC21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- IC21_1 ---*/ +#define SetPinFunc_IC21_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 2u ); \ + bFM_GPIO_PFR6_PC = 1u; \ + }while (0u) + +/*--- IC21_LSYN1 ---*/ +#define SetPinFunc_IC21_LSYN1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 4u ); \ + }while (0u) + +/*--- IC21_LSYN5 ---*/ +#define SetPinFunc_IC21_LSYN5(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 23u, 3u, 5u ); \ + }while (0u) + +/*--- IC22_0 ---*/ +#define SetPinFunc_IC22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 1u ); \ + bFM_GPIO_PFRA_P9 = 1u; \ + }while (0u) + +/*--- IC22_1 ---*/ +#define SetPinFunc_IC22_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 2u ); \ + bFM_GPIO_PFR6_PD = 1u; \ + }while (0u) + +/*--- IC22_LSYN2 ---*/ +#define SetPinFunc_IC22_LSYN2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 4u ); \ + }while (0u) + +/*--- IC22_LSYN6 ---*/ +#define SetPinFunc_IC22_LSYN6(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 26u, 3u, 5u ); \ + }while (0u) + +/*--- IC23_0 ---*/ +#define SetPinFunc_IC23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 1u ); \ + bFM_GPIO_PFRA_PA = 1u; \ + }while (0u) + +/*--- IC23_1 ---*/ +#define SetPinFunc_IC23_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 2u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- IC23_LSYN3 ---*/ +#define SetPinFunc_IC23_LSYN3(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 4u ); \ + }while (0u) + +/*--- IC23_LSYN7 ---*/ +#define SetPinFunc_IC23_LSYN7(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 29u, 3u, 5u ); \ + }while (0u) + +/*--- INT00_0 ---*/ +#define SetPinFunc_INT00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- INT00_1 ---*/ +#define SetPinFunc_INT00_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 0u, 2u, 2u ); \ + bFM_GPIO_PFR3_P4 = 1u; \ + }while (0u) + +/*--- INT00_2 ---*/ +#define SetPinFunc_INT00_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 0u, 2u, 3u ); \ + bFM_GPIO_PFR5_P4 = 1u; \ + }while (0u) + +/*--- INT01_0 ---*/ +#define SetPinFunc_INT01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- INT01_1 ---*/ +#define SetPinFunc_INT01_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_P5 = 1u; \ + }while (0u) + +/*--- INT01_2 ---*/ +#define SetPinFunc_INT01_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 2u, 2u, 3u ); \ + bFM_GPIO_PFR5_PD = 1u; \ + }while (0u) + +/*--- INT02_0 ---*/ +#define SetPinFunc_INT02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- INT02_1 ---*/ +#define SetPinFunc_INT02_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_P6 = 1u; \ + }while (0u) + +/*--- INT02_2 ---*/ +#define SetPinFunc_INT02_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 4u, 2u, 3u ); \ + bFM_GPIO_PFR5_P8 = 1u; \ + }while (0u) + +/*--- INT03_0 ---*/ +#define SetPinFunc_INT03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 6u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- INT03_1 ---*/ +#define SetPinFunc_INT03_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 6u, 2u, 2u ); \ + bFM_GPIO_PFR3_P7 = 1u; \ + }while (0u) + +/*--- INT03_2 ---*/ +#define SetPinFunc_INT03_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 6u, 2u, 3u ); \ + bFM_GPIO_PFR3_P0 = 1u; \ + }while (0u) + +/*--- INT04_0 ---*/ +#define SetPinFunc_INT04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- INT04_1 ---*/ +#define SetPinFunc_INT04_1(dummy) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 8u, 2u, 2u ); \ + bFM_GPIO_PFR7_PC = 1u; \ + }while (0u) + +/*--- INT04_2 ---*/ +#define SetPinFunc_INT04_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 8u, 2u, 3u ); \ + bFM_GPIO_PFR4_PA = 1u; \ + }while (0u) + +/*--- INT05_0 ---*/ +#define SetPinFunc_INT05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- INT05_1 ---*/ +#define SetPinFunc_INT05_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 10u, 2u, 2u ); \ + bFM_GPIO_PFRF_P3 = 1u; \ + }while (0u) + +/*--- INT05_2 ---*/ +#define SetPinFunc_INT05_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 10u, 2u, 3u ); \ + bFM_GPIO_PFR4_PD = 1u; \ + }while (0u) + +/*--- INT06_0 ---*/ +#define SetPinFunc_INT06_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- INT06_1 ---*/ +#define SetPinFunc_INT06_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 12u, 2u, 2u ); \ + bFM_GPIO_PFRF_P4 = 1u; \ + }while (0u) + +/*--- INT06_2 ---*/ +#define SetPinFunc_INT06_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 12u, 2u, 3u ); \ + bFM_GPIO_PFRF_PC = 1u; \ + }while (0u) + +/*--- INT07_0 ---*/ +#define SetPinFunc_INT07_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 14u, 2u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- INT07_1 ---*/ +#define SetPinFunc_INT07_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 14u, 2u, 2u ); \ + bFM_GPIO_PFRF_P5 = 1u; \ + }while (0u) + +/*--- INT07_2 ---*/ +#define SetPinFunc_INT07_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 14u, 2u, 3u ); \ + bFM_GPIO_PFRF_PB = 1u; \ + }while (0u) + +/*--- INT08_0 ---*/ +#define SetPinFunc_INT08_0(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 16u, 2u, 1u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- INT08_1 ---*/ +#define SetPinFunc_INT08_1(dummy) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 16u, 2u, 2u ); \ + bFM_GPIO_PFRB_P1 = 1u; \ + }while (0u) + +/*--- INT08_2 ---*/ +#define SetPinFunc_INT08_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 16u, 2u, 3u ); \ + bFM_GPIO_PFRB_P8 = 1u; \ + }while (0u) + +/*--- INT09_0 ---*/ +#define SetPinFunc_INT09_0(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 18u, 2u, 1u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- INT09_1 ---*/ +#define SetPinFunc_INT09_1(dummy) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 18u, 2u, 2u ); \ + bFM_GPIO_PFRB_P2 = 1u; \ + }while (0u) + +/*--- INT09_2 ---*/ +#define SetPinFunc_INT09_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 18u, 2u, 3u ); \ + bFM_GPIO_PFRB_P9 = 1u; \ + }while (0u) + +/*--- INT10_0 ---*/ +#define SetPinFunc_INT10_0(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 20u, 2u, 1u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- INT10_1 ---*/ +#define SetPinFunc_INT10_1(dummy) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 20u, 2u, 2u ); \ + bFM_GPIO_PFRB_P4 = 1u; \ + }while (0u) + +/*--- INT10_2 ---*/ +#define SetPinFunc_INT10_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 20u, 2u, 3u ); \ + bFM_GPIO_PFRB_PD = 1u; \ + }while (0u) + +/*--- INT11_0 ---*/ +#define SetPinFunc_INT11_0(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 22u, 2u, 1u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- INT11_1 ---*/ +#define SetPinFunc_INT11_1(dummy) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 22u, 2u, 2u ); \ + bFM_GPIO_PFRB_P5 = 1u; \ + }while (0u) + +/*--- INT11_2 ---*/ +#define SetPinFunc_INT11_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 22u, 2u, 3u ); \ + bFM_GPIO_PFRB_PF = 1u; \ + }while (0u) + +/*--- INT12_0 ---*/ +#define SetPinFunc_INT12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_PF = 1u; \ + }while (0u) + +/*--- INT12_1 ---*/ +#define SetPinFunc_INT12_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 24u, 2u, 2u ); \ + bFM_GPIO_PFR9_P0 = 1u; \ + }while (0u) + +/*--- INT12_2 ---*/ +#define SetPinFunc_INT12_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 24u, 2u, 3u ); \ + bFM_GPIO_PFR9_P6 = 1u; \ + }while (0u) + +/*--- INT13_0 ---*/ +#define SetPinFunc_INT13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 26u, 2u, 1u ); \ + bFM_GPIO_PFRC_P7 = 1u; \ + }while (0u) + +/*--- INT13_1 ---*/ +#define SetPinFunc_INT13_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 26u, 2u, 2u ); \ + bFM_GPIO_PFR9_P1 = 1u; \ + }while (0u) + +/*--- INT13_2 ---*/ +#define SetPinFunc_INT13_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 26u, 2u, 3u ); \ + bFM_GPIO_PFR9_P7 = 1u; \ + }while (0u) + +/*--- INT14_0 ---*/ +#define SetPinFunc_INT14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 28u, 2u, 1u ); \ + bFM_GPIO_PFRC_PD = 1u; \ + }while (0u) + +/*--- INT14_1 ---*/ +#define SetPinFunc_INT14_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 28u, 2u, 2u ); \ + bFM_GPIO_PFR9_P2 = 1u; \ + }while (0u) + +/*--- INT14_2 ---*/ +#define SetPinFunc_INT14_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 28u, 2u, 3u ); \ + bFM_GPIO_PFR6_PB = 1u; \ + }while (0u) + +/*--- INT15_0 ---*/ +#define SetPinFunc_INT15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 30u, 2u, 1u ); \ + bFM_GPIO_PFRC_PE = 1u; \ + }while (0u) + +/*--- INT15_1 ---*/ +#define SetPinFunc_INT15_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 30u, 2u, 2u ); \ + bFM_GPIO_PFR9_P3 = 1u; \ + }while (0u) + +/*--- INT15_2 ---*/ +#define SetPinFunc_INT15_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR06, 30u, 2u, 3u ); \ + bFM_GPIO_PFR6_P6 = 1u; \ + }while (0u) + +/*--- INT16_0 ---*/ +#define SetPinFunc_INT16_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- INT16_1 ---*/ +#define SetPinFunc_INT16_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 0u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- INT17_0 ---*/ +#define SetPinFunc_INT17_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 2u, 2u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- INT17_1 ---*/ +#define SetPinFunc_INT17_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- INT18_0 ---*/ +#define SetPinFunc_INT18_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 4u, 2u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- INT18_1 ---*/ +#define SetPinFunc_INT18_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- INT19_0 ---*/ +#define SetPinFunc_INT19_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 6u, 2u, 1u ); \ + bFM_GPIO_PFR3_P2 = 1u; \ + }while (0u) + +/*--- INT19_1 ---*/ +#define SetPinFunc_INT19_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 6u, 2u, 2u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- INT20_0 ---*/ +#define SetPinFunc_INT20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 8u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- INT20_1 ---*/ +#define SetPinFunc_INT20_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 8u, 2u, 2u ); \ + bFM_GPIO_PFRF_P6 = 1u; \ + }while (0u) + +/*--- INT21_0 ---*/ +#define SetPinFunc_INT21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- INT21_1 ---*/ +#define SetPinFunc_INT21_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 10u, 2u, 2u ); \ + bFM_GPIO_PFRF_P7 = 1u; \ + }while (0u) + +/*--- INT22_0 ---*/ +#define SetPinFunc_INT22_0(dummy) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_PB = 1u; \ + }while (0u) + +/*--- INT22_1 ---*/ +#define SetPinFunc_INT22_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 12u, 2u, 2u ); \ + bFM_GPIO_PFRF_P0 = 1u; \ + }while (0u) + +/*--- INT23_0 ---*/ +#define SetPinFunc_INT23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 14u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- INT23_1 ---*/ +#define SetPinFunc_INT23_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 14u, 2u, 2u ); \ + bFM_GPIO_PFRF_P1 = 1u; \ + }while (0u) + +/*--- INT24_0 ---*/ +#define SetPinFunc_INT24_0(dummy) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 16u, 2u, 1u ); \ + bFM_GPIO_PFR2_P7 = 1u; \ + }while (0u) + +/*--- INT24_1 ---*/ +#define SetPinFunc_INT24_1(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 16u, 2u, 2u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- INT25_0 ---*/ +#define SetPinFunc_INT25_0(dummy) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 18u, 2u, 1u ); \ + bFM_GPIO_PFR2_P5 = 1u; \ + }while (0u) + +/*--- INT25_1 ---*/ +#define SetPinFunc_INT25_1(dummy) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 18u, 2u, 2u ); \ + bFM_GPIO_PFR1_P3 = 1u; \ + }while (0u) + +/*--- INT26_0 ---*/ +#define SetPinFunc_INT26_0(dummy) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 20u, 2u, 1u ); \ + bFM_GPIO_PFR2_P2 = 1u; \ + }while (0u) + +/*--- INT26_1 ---*/ +#define SetPinFunc_INT26_1(dummy) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 20u, 2u, 2u ); \ + bFM_GPIO_PFR1_PE = 1u; \ + }while (0u) + +/*--- INT27_0 ---*/ +#define SetPinFunc_INT27_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 22u, 2u, 1u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- INT27_1 ---*/ +#define SetPinFunc_INT27_1(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 22u, 2u, 2u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- INT28_0 ---*/ +#define SetPinFunc_INT28_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_PB = 1u; \ + }while (0u) + +/*--- INT28_1 ---*/ +#define SetPinFunc_INT28_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 24u, 2u, 2u ); \ + bFM_GPIO_PFR6_P5 = 1u; \ + }while (0u) + +/*--- INT29_0 ---*/ +#define SetPinFunc_INT29_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 26u, 2u, 1u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- INT29_1 ---*/ +#define SetPinFunc_INT29_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 26u, 2u, 2u ); \ + bFM_GPIO_PFR6_P4 = 1u; \ + }while (0u) + +/*--- INT30_0 ---*/ +#define SetPinFunc_INT30_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 28u, 2u, 1u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- INT30_1 ---*/ +#define SetPinFunc_INT30_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 28u, 2u, 2u ); \ + bFM_GPIO_PFRD_P0 = 1u; \ + }while (0u) + +/*--- INT31_0 ---*/ +#define SetPinFunc_INT31_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 30u, 2u, 1u ); \ + bFM_GPIO_PFR6_P0 = 1u; \ + }while (0u) + +/*--- INT31_1 ---*/ +#define SetPinFunc_INT31_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR15, 30u, 2u, 2u ); \ + bFM_GPIO_PFRD_P1 = 1u; \ + }while (0u) + +/*--- MAD00_0 ---*/ +#define SetPinFunc_MAD00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 14u, 1u, 1u ); \ + bFM_GPIO_PFR7_P1 = 1u; \ + }while (0u) + +/*--- MAD01_0 ---*/ +#define SetPinFunc_MAD01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 2u, 1u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- MAD02_0 ---*/ +#define SetPinFunc_MAD02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 3u, 1u, 1u ); \ + bFM_GPIO_PFR7_P3 = 1u; \ + }while (0u) + +/*--- MAD03_0 ---*/ +#define SetPinFunc_MAD03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 4u, 1u, 1u ); \ + bFM_GPIO_PFR7_P4 = 1u; \ + }while (0u) + +/*--- MAD04_0 ---*/ +#define SetPinFunc_MAD04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 5u, 1u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- MAD05_0 ---*/ +#define SetPinFunc_MAD05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 6u, 1u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- MAD06_0 ---*/ +#define SetPinFunc_MAD06_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 7u, 1u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- MAD07_0 ---*/ +#define SetPinFunc_MAD07_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 8u, 1u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- MAD08_0 ---*/ +#define SetPinFunc_MAD08_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 15u, 1u, 1u ); \ + bFM_GPIO_PFR7_P9 = 1u; \ + }while (0u) + +/*--- MAD09_0 ---*/ +#define SetPinFunc_MAD09_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 16u, 1u, 1u ); \ + bFM_GPIO_PFR7_PA = 1u; \ + }while (0u) + +/*--- MAD10_0 ---*/ +#define SetPinFunc_MAD10_0(dummy) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 17u, 1u, 1u ); \ + bFM_GPIO_PFR1_PE = 1u; \ + }while (0u) + +/*--- MAD11_0 ---*/ +#define SetPinFunc_MAD11_0(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 18u, 1u, 1u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- MAD12_0 ---*/ +#define SetPinFunc_MAD12_0(dummy) do{ \ + bFM_GPIO_ADE_AN24=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 19u, 1u, 1u ); \ + bFM_GPIO_PFR2_PA = 1u; \ + }while (0u) + +/*--- MAD13_0 ---*/ +#define SetPinFunc_MAD13_0(dummy) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 20u, 1u, 1u ); \ + bFM_GPIO_PFR2_P9 = 1u; \ + }while (0u) + +/*--- MAD14_0 ---*/ +#define SetPinFunc_MAD14_0(dummy) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 21u, 1u, 1u ); \ + bFM_GPIO_PFR2_P8 = 1u; \ + }while (0u) + +/*--- MAD15_0 ---*/ +#define SetPinFunc_MAD15_0(dummy) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 22u, 1u, 1u ); \ + bFM_GPIO_PFR2_P7 = 1u; \ + }while (0u) + +/*--- MAD16_0 ---*/ +#define SetPinFunc_MAD16_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 23u, 1u, 1u ); \ + bFM_GPIO_PFR2_P6 = 1u; \ + }while (0u) + +/*--- MAD17_0 ---*/ +#define SetPinFunc_MAD17_0(dummy) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 24u, 1u, 1u ); \ + bFM_GPIO_PFR2_P5 = 1u; \ + }while (0u) + +/*--- MAD18_0 ---*/ +#define SetPinFunc_MAD18_0(dummy) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 25u, 1u, 1u ); \ + bFM_GPIO_PFR2_P4 = 1u; \ + }while (0u) + +/*--- MAD19_0 ---*/ +#define SetPinFunc_MAD19_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 26u, 1u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- MAD20_0 ---*/ +#define SetPinFunc_MAD20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 27u, 1u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- MAD21_0 ---*/ +#define SetPinFunc_MAD21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 28u, 1u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- MAD22_0 ---*/ +#define SetPinFunc_MAD22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 29u, 1u, 1u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- MAD23_0 ---*/ +#define SetPinFunc_MAD23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 30u, 1u, 1u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- MAD24_0 ---*/ +#define SetPinFunc_MAD24_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 31u, 1u, 1u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- MADATA00_0 ---*/ +#define SetPinFunc_MADATA00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 9u, 1u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- MADATA01_0 ---*/ +#define SetPinFunc_MADATA01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 10u, 1u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- MADATA02_0 ---*/ +#define SetPinFunc_MADATA02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 11u, 1u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- MADATA03_0 ---*/ +#define SetPinFunc_MADATA03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 12u, 1u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- MADATA04_0 ---*/ +#define SetPinFunc_MADATA04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 13u, 1u, 1u ); \ + bFM_GPIO_PFRA_P4 = 1u; \ + }while (0u) + +/*--- MADATA05_0 ---*/ +#define SetPinFunc_MADATA05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 14u, 1u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- MADATA06_0 ---*/ +#define SetPinFunc_MADATA06_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 15u, 1u, 1u ); \ + bFM_GPIO_PFRA_P6 = 1u; \ + }while (0u) + +/*--- MADATA07_0 ---*/ +#define SetPinFunc_MADATA07_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 16u, 1u, 1u ); \ + bFM_GPIO_PFRA_P7 = 1u; \ + }while (0u) + +/*--- MADATA08_0 ---*/ +#define SetPinFunc_MADATA08_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 17u, 1u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- MADATA09_0 ---*/ +#define SetPinFunc_MADATA09_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 18u, 1u, 1u ); \ + bFM_GPIO_PFRA_P9 = 1u; \ + }while (0u) + +/*--- MADATA10_0 ---*/ +#define SetPinFunc_MADATA10_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 19u, 1u, 1u ); \ + bFM_GPIO_PFRA_PA = 1u; \ + }while (0u) + +/*--- MADATA11_0 ---*/ +#define SetPinFunc_MADATA11_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 20u, 1u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- MADATA12_0 ---*/ +#define SetPinFunc_MADATA12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 21u, 1u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- MADATA13_0 ---*/ +#define SetPinFunc_MADATA13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 22u, 1u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- MADATA14_0 ---*/ +#define SetPinFunc_MADATA14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 23u, 1u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- MADATA15_0 ---*/ +#define SetPinFunc_MADATA15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 24u, 1u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- MADATA16_0 ---*/ +#define SetPinFunc_MADATA16_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 9u, 1u, 1u ); \ + bFM_GPIO_PFR5_P0 = 1u; \ + }while (0u) + +/*--- MADATA17_0 ---*/ +#define SetPinFunc_MADATA17_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 10u, 1u, 1u ); \ + bFM_GPIO_PFR5_P1 = 1u; \ + }while (0u) + +/*--- MADATA18_0 ---*/ +#define SetPinFunc_MADATA18_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 11u, 1u, 1u ); \ + bFM_GPIO_PFR5_P2 = 1u; \ + }while (0u) + +/*--- MADATA19_0 ---*/ +#define SetPinFunc_MADATA19_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 12u, 1u, 1u ); \ + bFM_GPIO_PFR5_P3 = 1u; \ + }while (0u) + +/*--- MADATA20_0 ---*/ +#define SetPinFunc_MADATA20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 13u, 1u, 1u ); \ + bFM_GPIO_PFR5_P4 = 1u; \ + }while (0u) + +/*--- MADATA21_0 ---*/ +#define SetPinFunc_MADATA21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 14u, 1u, 1u ); \ + bFM_GPIO_PFR5_P5 = 1u; \ + }while (0u) + +/*--- MADATA22_0 ---*/ +#define SetPinFunc_MADATA22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 15u, 1u, 1u ); \ + bFM_GPIO_PFR5_P6 = 1u; \ + }while (0u) + +/*--- MADATA23_0 ---*/ +#define SetPinFunc_MADATA23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 16u, 1u, 1u ); \ + bFM_GPIO_PFR5_P7 = 1u; \ + }while (0u) + +/*--- MADATA24_0 ---*/ +#define SetPinFunc_MADATA24_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 17u, 1u, 1u ); \ + bFM_GPIO_PFR5_P8 = 1u; \ + }while (0u) + +/*--- MADATA25_0 ---*/ +#define SetPinFunc_MADATA25_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 18u, 1u, 1u ); \ + bFM_GPIO_PFR5_P9 = 1u; \ + }while (0u) + +/*--- MADATA26_0 ---*/ +#define SetPinFunc_MADATA26_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 19u, 1u, 1u ); \ + bFM_GPIO_PFR5_PA = 1u; \ + }while (0u) + +/*--- MADATA27_0 ---*/ +#define SetPinFunc_MADATA27_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 20u, 1u, 1u ); \ + bFM_GPIO_PFR5_PB = 1u; \ + }while (0u) + +/*--- MADATA28_0 ---*/ +#define SetPinFunc_MADATA28_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 21u, 1u, 1u ); \ + bFM_GPIO_PFR5_PC = 1u; \ + }while (0u) + +/*--- MADATA29_0 ---*/ +#define SetPinFunc_MADATA29_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 22u, 1u, 1u ); \ + bFM_GPIO_PFR5_PD = 1u; \ + }while (0u) + +/*--- MADATA30_0 ---*/ +#define SetPinFunc_MADATA30_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 23u, 1u, 1u ); \ + bFM_GPIO_PFR5_PE = 1u; \ + }while (0u) + +/*--- MADATA31_0 ---*/ +#define SetPinFunc_MADATA31_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 24u, 1u, 1u ); \ + bFM_GPIO_PFR5_PF = 1u; \ + }while (0u) + +/*--- MALE_0 ---*/ +#define SetPinFunc_MALE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 0u, 1u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- MCASX_0 ---*/ +#define SetPinFunc_MCASX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 3u, 1u, 1u ); \ + bFM_GPIO_PFRF_P3 = 1u; \ + }while (0u) + +/*--- MCLKOUT_0 ---*/ +#define SetPinFunc_MCLKOUT_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 2u, 1u, 1u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- MCSX0_0 ---*/ +#define SetPinFunc_MCSX0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR11, 1u, 1u, 1u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- MCSX1_0 ---*/ +#define SetPinFunc_MCSX1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 7u, 1u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- MCSX2_0 ---*/ +#define SetPinFunc_MCSX2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 8u, 1u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- MCSX3_0 ---*/ +#define SetPinFunc_MCSX3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 9u, 1u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- MCSX4_0 ---*/ +#define SetPinFunc_MCSX4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 10u, 1u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- MCSX5_0 ---*/ +#define SetPinFunc_MCSX5_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 11u, 1u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- MCSX6_0 ---*/ +#define SetPinFunc_MCSX6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 12u, 1u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- MCSX7_0 ---*/ +#define SetPinFunc_MCSX7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 13u, 1u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- MCSX8_0 ---*/ +#define SetPinFunc_MCSX8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 5u, 1u, 1u ); \ + bFM_GPIO_PFRF_P5 = 1u; \ + }while (0u) + +/*--- MDQM0_0 ---*/ +#define SetPinFunc_MDQM0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 4u, 1u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- MDQM1_0 ---*/ +#define SetPinFunc_MDQM1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 4u, 1u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- MDQM2_0 ---*/ +#define SetPinFunc_MDQM2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_P0 = 1u; \ + }while (0u) + +/*--- MDQM3_0 ---*/ +#define SetPinFunc_MDQM3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 7u, 1u, 1u ); \ + bFM_GPIO_PFR3_P1 = 1u; \ + }while (0u) + +/*--- MNALE_0 ---*/ +#define SetPinFunc_MNALE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- MNCLE_0 ---*/ +#define SetPinFunc_MNCLE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- MNREX_0 ---*/ +#define SetPinFunc_MNREX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- MNWEX_0 ---*/ +#define SetPinFunc_MNWEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 6u, 1u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- MOEX_0 ---*/ +#define SetPinFunc_MOEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 5u, 1u, 1u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- MRASX_0 ---*/ +#define SetPinFunc_MRASX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 2u, 1u, 1u ); \ + bFM_GPIO_PFRF_P2 = 1u; \ + }while (0u) + +/*--- MRDY_0 ---*/ +#define SetPinFunc_MRDY_0(dummy) do{ \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- MSDCKE_0 ---*/ +#define SetPinFunc_MSDCKE_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 1u, 1u, 1u ); \ + bFM_GPIO_PFRF_P6 = 1u; \ + }while (0u) + +/*--- MSDCLK_0 ---*/ +#define SetPinFunc_MSDCLK_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 0u, 1u, 1u ); \ + bFM_GPIO_PFRF_P7 = 1u; \ + }while (0u) + +/*--- MSDWEX_0 ---*/ +#define SetPinFunc_MSDWEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR20, 4u, 1u, 1u ); \ + bFM_GPIO_PFRF_P4 = 1u; \ + }while (0u) + +/*--- MWEX_0 ---*/ +#define SetPinFunc_MWEX_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR10, 3u, 1u, 1u ); \ + bFM_GPIO_PFR6_P2 = 1u; \ + }while (0u) + +/*--- NMIX ---*/ +#define SetPinFunc_NMIX(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 0u, 1u, 1u ); \ + bFM_GPIO_PFR2_P0 = 1u; \ + }while (0u) + +/*--- Q_CS0_0 ---*/ +#define SetPinFunc_Q_CS0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 2u, 2u, 1u ); \ + bFM_GPIO_PFR9_P5 = 1u; \ + }while (0u) + +/*--- Q_CS1_0 ---*/ +#define SetPinFunc_Q_CS1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 4u, 2u, 1u ); \ + bFM_GPIO_PFR9_P6 = 1u; \ + }while (0u) + +/*--- Q_CS2_0 ---*/ +#define SetPinFunc_Q_CS2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 6u, 2u, 1u ); \ + bFM_GPIO_PFR9_P7 = 1u; \ + }while (0u) + +/*--- Q_IO0_0 ---*/ +#define SetPinFunc_Q_IO0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 10u, 2u, 1u ); \ + bFM_GPIO_PFR9_P3 = 1u; \ + }while (0u) + +/*--- Q_IO1_0 ---*/ +#define SetPinFunc_Q_IO1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 12u, 2u, 1u ); \ + bFM_GPIO_PFR9_P2 = 1u; \ + }while (0u) + +/*--- Q_IO2_0 ---*/ +#define SetPinFunc_Q_IO2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 14u, 2u, 1u ); \ + bFM_GPIO_PFR9_P1 = 1u; \ + }while (0u) + +/*--- Q_IO3_0 ---*/ +#define SetPinFunc_Q_IO3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 16u, 2u, 1u ); \ + bFM_GPIO_PFR9_P0 = 1u; \ + }while (0u) + +/*--- Q_SCK_0 ---*/ +#define SetPinFunc_Q_SCK_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR26, 0u, 2u, 1u ); \ + bFM_GPIO_PFR9_P4 = 1u; \ + }while (0u) + +/*--- RTCCO_0 ---*/ +#define SetPinFunc_RTCCO_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 4u, 2u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- RTCCO_1 ---*/ +#define SetPinFunc_RTCCO_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 4u, 2u, 2u ); \ + bFM_GPIO_PFR5_PC = 1u; \ + }while (0u) + +/*--- RTO00_0 ---*/ +#define SetPinFunc_RTO00_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 0u, 2u, 1u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- RTO00_1 ---*/ +#define SetPinFunc_RTO00_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 0u, 2u, 2u ); \ + bFM_GPIO_PFR5_P0 = 1u; \ + }while (0u) + +/*--- RTO01_0 ---*/ +#define SetPinFunc_RTO01_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 2u, 2u, 1u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- RTO01_1 ---*/ +#define SetPinFunc_RTO01_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 2u, 2u, 2u ); \ + bFM_GPIO_PFR5_P1 = 1u; \ + }while (0u) + +/*--- RTO02_0 ---*/ +#define SetPinFunc_RTO02_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 4u, 2u, 1u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- RTO02_1 ---*/ +#define SetPinFunc_RTO02_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 4u, 2u, 2u ); \ + bFM_GPIO_PFR5_P2 = 1u; \ + }while (0u) + +/*--- RTO03_0 ---*/ +#define SetPinFunc_RTO03_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 6u, 2u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- RTO03_1 ---*/ +#define SetPinFunc_RTO03_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 6u, 2u, 2u ); \ + bFM_GPIO_PFR5_P3 = 1u; \ + }while (0u) + +/*--- RTO04_0 ---*/ +#define SetPinFunc_RTO04_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 8u, 2u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- RTO04_1 ---*/ +#define SetPinFunc_RTO04_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 8u, 2u, 2u ); \ + bFM_GPIO_PFR5_P4 = 1u; \ + }while (0u) + +/*--- RTO05_0 ---*/ +#define SetPinFunc_RTO05_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 10u, 2u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- RTO05_1 ---*/ +#define SetPinFunc_RTO05_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR01, 10u, 2u, 2u ); \ + bFM_GPIO_PFR5_P5 = 1u; \ + }while (0u) + +/*--- RTO10_0 ---*/ +#define SetPinFunc_RTO10_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 0u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- RTO10_1 ---*/ +#define SetPinFunc_RTO10_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 0u, 2u, 2u ); \ + bFM_GPIO_PFRF_P2 = 1u; \ + }while (0u) + +/*--- RTO11_0 ---*/ +#define SetPinFunc_RTO11_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- RTO11_1 ---*/ +#define SetPinFunc_RTO11_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 2u, 2u, 2u ); \ + bFM_GPIO_PFRF_P3 = 1u; \ + }while (0u) + +/*--- RTO12_0 ---*/ +#define SetPinFunc_RTO12_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 4u, 2u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- RTO12_1 ---*/ +#define SetPinFunc_RTO12_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 4u, 2u, 2u ); \ + bFM_GPIO_PFRF_P4 = 1u; \ + }while (0u) + +/*--- RTO13_0 ---*/ +#define SetPinFunc_RTO13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 6u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- RTO13_1 ---*/ +#define SetPinFunc_RTO13_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 6u, 2u, 2u ); \ + bFM_GPIO_PFRF_P5 = 1u; \ + }while (0u) + +/*--- RTO14_0 ---*/ +#define SetPinFunc_RTO14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- RTO14_1 ---*/ +#define SetPinFunc_RTO14_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 8u, 2u, 2u ); \ + bFM_GPIO_PFRF_P6 = 1u; \ + }while (0u) + +/*--- RTO15_0 ---*/ +#define SetPinFunc_RTO15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 10u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- RTO15_1 ---*/ +#define SetPinFunc_RTO15_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR02, 10u, 2u, 2u ); \ + bFM_GPIO_PFRF_P7 = 1u; \ + }while (0u) + +/*--- RTO20_0 ---*/ +#define SetPinFunc_RTO20_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 0u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- RTO20_1 ---*/ +#define SetPinFunc_RTO20_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 0u, 2u, 2u ); \ + bFM_GPIO_PFR6_P9 = 1u; \ + }while (0u) + +/*--- RTO21_0 ---*/ +#define SetPinFunc_RTO21_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- RTO21_1 ---*/ +#define SetPinFunc_RTO21_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 2u, 2u, 2u ); \ + bFM_GPIO_PFR6_P8 = 1u; \ + }while (0u) + +/*--- RTO22_0 ---*/ +#define SetPinFunc_RTO22_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- RTO22_1 ---*/ +#define SetPinFunc_RTO22_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 4u, 2u, 2u ); \ + bFM_GPIO_PFR6_P7 = 1u; \ + }while (0u) + +/*--- RTO23_0 ---*/ +#define SetPinFunc_RTO23_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 6u, 2u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- RTO23_1 ---*/ +#define SetPinFunc_RTO23_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 6u, 2u, 2u ); \ + bFM_GPIO_PFR6_P6 = 1u; \ + }while (0u) + +/*--- RTO24_0 ---*/ +#define SetPinFunc_RTO24_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_P4 = 1u; \ + }while (0u) + +/*--- RTO24_1 ---*/ +#define SetPinFunc_RTO24_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 8u, 2u, 2u ); \ + bFM_GPIO_PFR6_P5 = 1u; \ + }while (0u) + +/*--- RTO25_0 ---*/ +#define SetPinFunc_RTO25_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- RTO25_1 ---*/ +#define SetPinFunc_RTO25_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR03, 10u, 2u, 2u ); \ + bFM_GPIO_PFR6_P4 = 1u; \ + }while (0u) + +/*--- RTS4_0 ---*/ +#define SetPinFunc_RTS4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 0u, 2u, 1u ); \ + bFM_GPIO_PFR6_P3 = 1u; \ + }while (0u) + +/*--- RTS4_1 ---*/ +#define SetPinFunc_RTS4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 0u, 2u, 2u ); \ + bFM_GPIO_PFRC_PF = 1u; \ + }while (0u) + +/*--- RTS5_0 ---*/ +#define SetPinFunc_RTS5_0(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 28u, 2u, 1u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- RTS5_1 ---*/ +#define SetPinFunc_RTS5_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 28u, 2u, 2u ); \ + bFM_GPIO_PFR9_P5 = 1u; \ + }while (0u) + +/*--- RX0_0 ---*/ +#define SetPinFunc_RX0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- RX0_1 ---*/ +#define SetPinFunc_RX0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 24u, 2u, 2u ); \ + bFM_GPIO_PFR3_P0 = 1u; \ + }while (0u) + +/*--- RX0_2 ---*/ +#define SetPinFunc_RX0_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 24u, 2u, 3u ); \ + bFM_GPIO_PFR9_P6 = 1u; \ + }while (0u) + +/*--- RX1_0 ---*/ +#define SetPinFunc_RX1_0(dummy) do{ \ + bFM_GPIO_ADE_AN28=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 28u, 2u, 1u ); \ + bFM_GPIO_PFR2_P5 = 1u; \ + }while (0u) + +/*--- RX1_1 ---*/ +#define SetPinFunc_RX1_1(dummy) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 28u, 2u, 2u ); \ + bFM_GPIO_PFR1_P3 = 1u; \ + }while (0u) + +/*--- RX1_2 ---*/ +#define SetPinFunc_RX1_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 28u, 2u, 3u ); \ + bFM_GPIO_PFRB_PD = 1u; \ + }while (0u) + +/*--- RX2_0 ---*/ +#define SetPinFunc_RX2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 0u, 2u, 1u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- RX2_1 ---*/ +#define SetPinFunc_RX2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 0u, 2u, 2u ); \ + bFM_GPIO_PFRF_P0 = 1u; \ + }while (0u) + +/*--- RX2_2 ---*/ +#define SetPinFunc_RX2_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 0u, 2u, 3u ); \ + bFM_GPIO_PFR4_PD = 1u; \ + }while (0u) + +/*--- SCK0_0 ---*/ +#define SetPinFunc_SCK0_0(dummy) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 8u, 2u, 1u ); \ + bFM_GPIO_PFR2_P3 = 1u; \ + }while (0u) + +/*--- SCK0_1 ---*/ +#define SetPinFunc_SCK0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 8u, 2u, 2u ); \ + bFM_GPIO_PFRB_PD = 1u; \ + }while (0u) + +/*--- SCK10_0 ---*/ +#define SetPinFunc_SCK10_0(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 20u, 2u, 1u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- SCK10_1 ---*/ +#define SetPinFunc_SCK10_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 20u, 2u, 2u ); \ + bFM_GPIO_PFR5_PF = 1u; \ + }while (0u) + +/*--- SCK11_0 ---*/ +#define SetPinFunc_SCK11_0(dummy) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 26u, 2u, 1u ); \ + bFM_GPIO_PFR1_P7 = 1u; \ + }while (0u) + +/*--- SCK11_1 ---*/ +#define SetPinFunc_SCK11_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 26u, 2u, 2u ); \ + bFM_GPIO_PFR5_PA = 1u; \ + }while (0u) + +/*--- SCK12_0 ---*/ +#define SetPinFunc_SCK12_0(dummy) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 8u, 2u, 1u ); \ + bFM_GPIO_PFR1_PD = 1u; \ + }while (0u) + +/*--- SCK12_1 ---*/ +#define SetPinFunc_SCK12_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 8u, 2u, 2u ); \ + bFM_GPIO_PFR4_PC = 1u; \ + }while (0u) + +/*--- SCK13_0 ---*/ +#define SetPinFunc_SCK13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 14u, 2u, 1u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- SCK13_1 ---*/ +#define SetPinFunc_SCK13_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 14u, 2u, 2u ); \ + bFM_GPIO_PFR6_P8 = 1u; \ + }while (0u) + +/*--- SCK14_0 ---*/ +#define SetPinFunc_SCK14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 20u, 2u, 1u ); \ + bFM_GPIO_PFR0_PA = 1u; \ + }while (0u) + +/*--- SCK14_1 ---*/ +#define SetPinFunc_SCK14_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 20u, 2u, 2u ); \ + bFM_GPIO_PFR6_PD = 1u; \ + }while (0u) + +/*--- SCK15_0 ---*/ +#define SetPinFunc_SCK15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 26u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- SCK15_1 ---*/ +#define SetPinFunc_SCK15_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 26u, 2u, 2u ); \ + bFM_GPIO_PFR5_P6 = 1u; \ + }while (0u) + +/*--- SCK1_0 ---*/ +#define SetPinFunc_SCK1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 14u, 2u, 1u ); \ + bFM_GPIO_PFRA_P7 = 1u; \ + }while (0u) + +/*--- SCK1_1 ---*/ +#define SetPinFunc_SCK1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 14u, 2u, 2u ); \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- SCK2_0 ---*/ +#define SetPinFunc_SCK2_0(dummy) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 20u, 2u, 1u ); \ + bFM_GPIO_PFR1_PA = 1u; \ + }while (0u) + +/*--- SCK2_1 ---*/ +#define SetPinFunc_SCK2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 20u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- SCK3_0 ---*/ +#define SetPinFunc_SCK3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- SCK3_1 ---*/ +#define SetPinFunc_SCK3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 26u, 2u, 2u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- SCK4_0 ---*/ +#define SetPinFunc_SCK4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 8u, 2u, 1u ); \ + bFM_GPIO_PFR6_P2 = 1u; \ + }while (0u) + +/*--- SCK4_1 ---*/ +#define SetPinFunc_SCK4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 8u, 2u, 2u ); \ + bFM_GPIO_PFR6_PE = 1u; \ + }while (0u) + +/*--- SCK5_0 ---*/ +#define SetPinFunc_SCK5_0(dummy) do{ \ + bFM_GPIO_ADE_AN25=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 14u, 2u, 1u ); \ + bFM_GPIO_PFR2_P9 = 1u; \ + }while (0u) + +/*--- SCK5_1 ---*/ +#define SetPinFunc_SCK5_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 14u, 2u, 2u ); \ + bFM_GPIO_PFR9_P3 = 1u; \ + }while (0u) + +/*--- SCK6_0 ---*/ +#define SetPinFunc_SCK6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 20u, 2u, 1u ); \ + bFM_GPIO_PFR7_PA = 1u; \ + }while (0u) + +/*--- SCK6_1 ---*/ +#define SetPinFunc_SCK6_1(dummy) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 20u, 2u, 2u ); \ + bFM_GPIO_PFRB_P0 = 1u; \ + }while (0u) + +/*--- SCK7_0 ---*/ +#define SetPinFunc_SCK7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_PA = 1u; \ + }while (0u) + +/*--- SCK7_1 ---*/ +#define SetPinFunc_SCK7_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 26u, 2u, 2u ); \ + bFM_GPIO_PFRF_PA = 1u; \ + }while (0u) + +/*--- SCK8_0 ---*/ +#define SetPinFunc_SCK8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 8u, 2u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- SCK8_1 ---*/ +#define SetPinFunc_SCK8_1(dummy) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 8u, 2u, 2u ); \ + bFM_GPIO_PFRB_P6 = 1u; \ + }while (0u) + +/*--- SCK9_0 ---*/ +#define SetPinFunc_SCK9_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 14u, 2u, 1u ); \ + bFM_GPIO_PFR7_P4 = 1u; \ + }while (0u) + +/*--- SCK9_1 ---*/ +#define SetPinFunc_SCK9_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 14u, 2u, 2u ); \ + bFM_GPIO_PFRB_PB = 1u; \ + }while (0u) + +/*--- SCS60_0 ---*/ +#define SetPinFunc_SCS60_0(dummy) do{ \ + bFM_DAC1_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 0u, 2u, 1u ); \ + bFM_GPIO_PFR7_PB = 1u; \ + }while (0u) + +/*--- SCS60_1 ---*/ +#define SetPinFunc_SCS60_1(dummy) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 0u, 2u, 2u ); \ + bFM_GPIO_PFRB_P1 = 1u; \ + }while (0u) + +/*--- SCS61_0 ---*/ +#define SetPinFunc_SCS61_0(dummy) do{ \ + bFM_DAC0_DACR_DAE=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 2u, 2u, 1u ); \ + bFM_GPIO_PFR7_PC = 1u; \ + }while (0u) + +/*--- SCS61_1 ---*/ +#define SetPinFunc_SCS61_1(dummy) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 2u, 2u, 2u ); \ + bFM_GPIO_PFRB_P2 = 1u; \ + }while (0u) + +/*--- SCS62_0 ---*/ +#define SetPinFunc_SCS62_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 4u, 2u, 1u ); \ + bFM_GPIO_PFRF_P1 = 1u; \ + }while (0u) + +/*--- SCS62_1 ---*/ +#define SetPinFunc_SCS62_1(dummy) do{ \ + bFM_GPIO_ADE_AN19=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 4u, 2u, 2u ); \ + bFM_GPIO_PFRB_P3 = 1u; \ + }while (0u) + +/*--- SCS63_0 ---*/ +#define SetPinFunc_SCS63_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 6u, 2u, 1u ); \ + bFM_GPIO_PFRF_P0 = 1u; \ + }while (0u) + +/*--- SCS63_1 ---*/ +#define SetPinFunc_SCS63_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 6u, 2u, 2u ); \ + bFM_GPIO_PFRB_P8 = 1u; \ + }while (0u) + +/*--- SCS70_0 ---*/ +#define SetPinFunc_SCS70_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_PB = 1u; \ + }while (0u) + +/*--- SCS70_1 ---*/ +#define SetPinFunc_SCS70_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 8u, 2u, 2u ); \ + bFM_GPIO_PFRF_P8 = 1u; \ + }while (0u) + +/*--- SCS71_0 ---*/ +#define SetPinFunc_SCS71_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- SCS71_1 ---*/ +#define SetPinFunc_SCS71_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 10u, 2u, 2u ); \ + bFM_GPIO_PFRF_P9 = 1u; \ + }while (0u) + +/*--- SCS72_0 ---*/ +#define SetPinFunc_SCS72_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 12u, 2u, 1u ); \ + bFM_GPIO_PFR5_P0 = 1u; \ + }while (0u) + +/*--- SCS72_1 ---*/ +#define SetPinFunc_SCS72_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 12u, 2u, 2u ); \ + bFM_GPIO_PFR4_PD = 1u; \ + }while (0u) + +/*--- SCS73_0 ---*/ +#define SetPinFunc_SCS73_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 14u, 2u, 1u ); \ + bFM_GPIO_PFR5_P1 = 1u; \ + }while (0u) + +/*--- SCS73_1 ---*/ +#define SetPinFunc_SCS73_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR23, 14u, 2u, 2u ); \ + bFM_GPIO_PFR4_PE = 1u; \ + }while (0u) + +/*--- SIN0_0 ---*/ +#define SetPinFunc_SIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 4u, 2u, 1u ); \ + bFM_GPIO_PFR2_P1 = 1u; \ + }while (0u) + +/*--- SIN0_1 ---*/ +#define SetPinFunc_SIN0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 4u, 2u, 2u ); \ + bFM_GPIO_PFRB_PF = 1u; \ + }while (0u) + +/*--- SIN10_0 ---*/ +#define SetPinFunc_SIN10_0(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 16u, 2u, 1u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- SIN10_1 ---*/ +#define SetPinFunc_SIN10_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 16u, 2u, 2u ); \ + bFM_GPIO_PFR5_PD = 1u; \ + }while (0u) + +/*--- SIN11_0 ---*/ +#define SetPinFunc_SIN11_0(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 22u, 2u, 1u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- SIN11_1 ---*/ +#define SetPinFunc_SIN11_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 22u, 2u, 2u ); \ + bFM_GPIO_PFR5_P8 = 1u; \ + }while (0u) + +/*--- SIN12_0 ---*/ +#define SetPinFunc_SIN12_0(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 4u, 2u, 1u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- SIN12_1 ---*/ +#define SetPinFunc_SIN12_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 4u, 2u, 2u ); \ + bFM_GPIO_PFR4_PA = 1u; \ + }while (0u) + +/*--- SIN13_0 ---*/ +#define SetPinFunc_SIN13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 10u, 2u, 1u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- SIN13_1 ---*/ +#define SetPinFunc_SIN13_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 10u, 2u, 2u ); \ + bFM_GPIO_PFR6_P6 = 1u; \ + }while (0u) + +/*--- SIN14_0 ---*/ +#define SetPinFunc_SIN14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 16u, 2u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- SIN14_1 ---*/ +#define SetPinFunc_SIN14_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 16u, 2u, 2u ); \ + bFM_GPIO_PFR6_PB = 1u; \ + }while (0u) + +/*--- SIN15_0 ---*/ +#define SetPinFunc_SIN15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 22u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- SIN15_1 ---*/ +#define SetPinFunc_SIN15_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 22u, 2u, 2u ); \ + bFM_GPIO_PFR5_P4 = 1u; \ + }while (0u) + +/*--- SIN1_0 ---*/ +#define SetPinFunc_SIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- SIN1_1 ---*/ +#define SetPinFunc_SIN1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 10u, 2u, 2u ); \ + bFM_GPIO_PFR7_P0 = 1u; \ + }while (0u) + +/*--- SIN2_0 ---*/ +#define SetPinFunc_SIN2_0(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 16u, 2u, 1u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- SIN2_1 ---*/ +#define SetPinFunc_SIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 16u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- SIN3_0 ---*/ +#define SetPinFunc_SIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 22u, 2u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- SIN3_1 ---*/ +#define SetPinFunc_SIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 22u, 2u, 2u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- SIN4_0 ---*/ +#define SetPinFunc_SIN4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 4u, 2u, 1u ); \ + bFM_GPIO_PFR6_P0 = 1u; \ + }while (0u) + +/*--- SIN4_1 ---*/ +#define SetPinFunc_SIN4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 4u, 2u, 2u ); \ + bFM_GPIO_PFRC_PE = 1u; \ + }while (0u) + +/*--- SIN5_0 ---*/ +#define SetPinFunc_SIN5_0(dummy) do{ \ + bFM_GPIO_ADE_AN27=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 10u, 2u, 1u ); \ + bFM_GPIO_PFR2_P7 = 1u; \ + }while (0u) + +/*--- SIN5_1 ---*/ +#define SetPinFunc_SIN5_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 10u, 2u, 2u ); \ + bFM_GPIO_PFR9_P1 = 1u; \ + }while (0u) + +/*--- SIN6_0 ---*/ +#define SetPinFunc_SIN6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 16u, 2u, 1u ); \ + bFM_GPIO_PFR7_P8 = 1u; \ + }while (0u) + +/*--- SIN6_1 ---*/ +#define SetPinFunc_SIN6_1(dummy) do{ \ + bFM_GPIO_ADE_AN03=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 16u, 2u, 2u ); \ + bFM_GPIO_PFR1_P3 = 1u; \ + }while (0u) + +/*--- SIN7_0 ---*/ +#define SetPinFunc_SIN7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 22u, 2u, 1u ); \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- SIN7_1 ---*/ +#define SetPinFunc_SIN7_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 22u, 2u, 2u ); \ + bFM_GPIO_PFRF_PC = 1u; \ + }while (0u) + +/*--- SIN8_0 ---*/ +#define SetPinFunc_SIN8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 4u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- SIN8_1 ---*/ +#define SetPinFunc_SIN8_1(dummy) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 4u, 2u, 2u ); \ + bFM_GPIO_PFRB_P4 = 1u; \ + }while (0u) + +/*--- SIN9_0 ---*/ +#define SetPinFunc_SIN9_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- SIN9_1 ---*/ +#define SetPinFunc_SIN9_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 10u, 2u, 2u ); \ + bFM_GPIO_PFRB_P9 = 1u; \ + }while (0u) + +/*--- SOT0_0 ---*/ +#define SetPinFunc_SOT0_0(dummy) do{ \ + bFM_GPIO_ADE_AN31=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 6u, 2u, 1u ); \ + bFM_GPIO_PFR2_P2 = 1u; \ + }while (0u) + +/*--- SOT0_1 ---*/ +#define SetPinFunc_SOT0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 6u, 2u, 2u ); \ + bFM_GPIO_PFRB_PE = 1u; \ + }while (0u) + +/*--- SOT10_0 ---*/ +#define SetPinFunc_SOT10_0(dummy) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 18u, 2u, 1u ); \ + bFM_GPIO_PFR1_P1 = 1u; \ + }while (0u) + +/*--- SOT10_1 ---*/ +#define SetPinFunc_SOT10_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 18u, 2u, 2u ); \ + bFM_GPIO_PFR5_PE = 1u; \ + }while (0u) + +/*--- SOT11_0 ---*/ +#define SetPinFunc_SOT11_0(dummy) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 24u, 2u, 1u ); \ + bFM_GPIO_PFR1_P6 = 1u; \ + }while (0u) + +/*--- SOT11_1 ---*/ +#define SetPinFunc_SOT11_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 24u, 2u, 2u ); \ + bFM_GPIO_PFR5_P9 = 1u; \ + }while (0u) + +/*--- SOT12_0 ---*/ +#define SetPinFunc_SOT12_0(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 6u, 2u, 1u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- SOT12_1 ---*/ +#define SetPinFunc_SOT12_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 6u, 2u, 2u ); \ + bFM_GPIO_PFR4_PB = 1u; \ + }while (0u) + +/*--- SOT13_0 ---*/ +#define SetPinFunc_SOT13_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 12u, 2u, 1u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- SOT13_1 ---*/ +#define SetPinFunc_SOT13_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 12u, 2u, 2u ); \ + bFM_GPIO_PFR6_P7 = 1u; \ + }while (0u) + +/*--- SOT14_0 ---*/ +#define SetPinFunc_SOT14_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 18u, 2u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- SOT14_1 ---*/ +#define SetPinFunc_SOT14_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 18u, 2u, 2u ); \ + bFM_GPIO_PFR6_PC = 1u; \ + }while (0u) + +/*--- SOT15_0 ---*/ +#define SetPinFunc_SOT15_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 24u, 2u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- SOT15_1 ---*/ +#define SetPinFunc_SOT15_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR17, 24u, 2u, 2u ); \ + bFM_GPIO_PFR5_P5 = 1u; \ + }while (0u) + +/*--- SOT1_0 ---*/ +#define SetPinFunc_SOT1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 12u, 2u, 1u ); \ + bFM_GPIO_PFRA_P6 = 1u; \ + }while (0u) + +/*--- SOT1_1 ---*/ +#define SetPinFunc_SOT1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 12u, 2u, 2u ); \ + bFM_GPIO_PFR7_P1 = 1u; \ + }while (0u) + +/*--- SOT2_0 ---*/ +#define SetPinFunc_SOT2_0(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 18u, 2u, 1u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- SOT2_1 ---*/ +#define SetPinFunc_SOT2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 18u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- SOT3_0 ---*/ +#define SetPinFunc_SOT3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- SOT3_1 ---*/ +#define SetPinFunc_SOT3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR07, 24u, 2u, 2u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- SOT4_0 ---*/ +#define SetPinFunc_SOT4_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 6u, 2u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- SOT4_1 ---*/ +#define SetPinFunc_SOT4_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 6u, 2u, 2u ); \ + bFM_GPIO_PFRC_PD = 1u; \ + }while (0u) + +/*--- SOT5_0 ---*/ +#define SetPinFunc_SOT5_0(dummy) do{ \ + bFM_GPIO_ADE_AN26=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 12u, 2u, 1u ); \ + bFM_GPIO_PFR2_P8 = 1u; \ + }while (0u) + +/*--- SOT5_1 ---*/ +#define SetPinFunc_SOT5_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 12u, 2u, 2u ); \ + bFM_GPIO_PFR9_P2 = 1u; \ + }while (0u) + +/*--- SOT6_0 ---*/ +#define SetPinFunc_SOT6_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 18u, 2u, 1u ); \ + bFM_GPIO_PFR7_P9 = 1u; \ + }while (0u) + +/*--- SOT6_1 ---*/ +#define SetPinFunc_SOT6_1(dummy) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 18u, 2u, 2u ); \ + bFM_GPIO_PFR1_P4 = 1u; \ + }while (0u) + +/*--- SOT7_0 ---*/ +#define SetPinFunc_SOT7_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_P9 = 1u; \ + }while (0u) + +/*--- SOT7_1 ---*/ +#define SetPinFunc_SOT7_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR08, 24u, 2u, 2u ); \ + bFM_GPIO_PFRF_PB = 1u; \ + }while (0u) + +/*--- SOT8_0 ---*/ +#define SetPinFunc_SOT8_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 6u, 2u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- SOT8_1 ---*/ +#define SetPinFunc_SOT8_1(dummy) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 6u, 2u, 2u ); \ + bFM_GPIO_PFRB_P5 = 1u; \ + }while (0u) + +/*--- SOT9_0 ---*/ +#define SetPinFunc_SOT9_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P3 = 1u; \ + }while (0u) + +/*--- SOT9_1 ---*/ +#define SetPinFunc_SOT9_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR16, 12u, 2u, 2u ); \ + bFM_GPIO_PFRB_PA = 1u; \ + }while (0u) + +/*--- SUBOUT_0 ---*/ +#define SetPinFunc_SUBOUT_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 6u, 2u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- SUBOUT_1 ---*/ +#define SetPinFunc_SUBOUT_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 6u, 2u, 2u ); \ + bFM_GPIO_PFR5_PC = 1u; \ + }while (0u) + +/*--- SWCLK ---*/ +#define SetPinFunc_SWCLK(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P1 = 1u; \ + }while (0u) + +/*--- SWDIO ---*/ +#define SetPinFunc_SWDIO(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P3 = 1u; \ + }while (0u) + +/*--- SWO ---*/ +#define SetPinFunc_SWO(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P4 = 1u; \ + }while (0u) + +/*--- S_CD_0 ---*/ +#define SetPinFunc_S_CD_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 26u, 2u, 1u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- S_CLK_0 ---*/ +#define SetPinFunc_S_CLK_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 14u, 2u, 1u ); \ + bFM_GPIO_PFR3_P4 = 1u; \ + }while (0u) + +/*--- S_CMD_0 ---*/ +#define SetPinFunc_S_CMD_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 16u, 2u, 1u ); \ + bFM_GPIO_PFR3_P5 = 1u; \ + }while (0u) + +/*--- S_DATA0_0 ---*/ +#define SetPinFunc_S_DATA0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 18u, 2u, 1u ); \ + bFM_GPIO_PFR3_P3 = 1u; \ + }while (0u) + +/*--- S_DATA1_0 ---*/ +#define SetPinFunc_S_DATA1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 20u, 2u, 1u ); \ + bFM_GPIO_PFR3_P2 = 1u; \ + }while (0u) + +/*--- S_DATA2_0 ---*/ +#define SetPinFunc_S_DATA2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 22u, 2u, 1u ); \ + bFM_GPIO_PFR3_P7 = 1u; \ + }while (0u) + +/*--- S_DATA3_0 ---*/ +#define SetPinFunc_S_DATA3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 24u, 2u, 1u ); \ + bFM_GPIO_PFR3_P6 = 1u; \ + }while (0u) + +/*--- S_WP_0 ---*/ +#define SetPinFunc_S_WP_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 28u, 2u, 1u ); \ + bFM_GPIO_PFR3_P8 = 1u; \ + }while (0u) + +/*--- TCK ---*/ +#define SetPinFunc_TCK(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P1 = 1u; \ + }while (0u) + +/*--- TDI ---*/ +#define SetPinFunc_TDI(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 17u, 1u, 1u ); \ + bFM_GPIO_PFR0_P2 = 1u; \ + }while (0u) + +/*--- TDO ---*/ +#define SetPinFunc_TDO(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P4 = 1u; \ + }while (0u) + +/*--- TIOA0_0_OUT ---*/ +#define SetPinFunc_TIOA0_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P0 = 1u; \ + }while (0u) + +/*--- TIOA0_1_OUT ---*/ +#define SetPinFunc_TIOA0_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_P9 = 1u; \ + }while (0u) + +/*--- TIOA0_2_OUT ---*/ +#define SetPinFunc_TIOA0_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN00=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 2u, 2u, 3u ); \ + bFM_GPIO_PFR1_P0 = 1u; \ + }while (0u) + +/*--- TIOA10_0_OUT ---*/ +#define SetPinFunc_TIOA10_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 18u, 2u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- TIOA10_1_OUT ---*/ +#define SetPinFunc_TIOA10_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN18=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 18u, 2u, 2u ); \ + bFM_GPIO_PFRB_P2 = 1u; \ + }while (0u) + +/*--- TIOA10_2_OUT ---*/ +#define SetPinFunc_TIOA10_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 18u, 2u, 3u ); \ + bFM_GPIO_PFR5_P4 = 1u; \ + }while (0u) + +/*--- TIOA11_0_IN ---*/ +#define SetPinFunc_TIOA11_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 24u, 2u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- TIOA11_0_OUT ---*/ +#define SetPinFunc_TIOA11_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_P3 = 1u; \ + }while (0u) + +/*--- TIOA11_1_IN ---*/ +#define SetPinFunc_TIOA11_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 24u, 2u, 2u ); \ + bFM_GPIO_PFRB_P4 = 1u; \ + }while (0u) + +/*--- TIOA11_1_OUT ---*/ +#define SetPinFunc_TIOA11_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 26u, 2u, 2u ); \ + bFM_GPIO_PFRB_P4 = 1u; \ + }while (0u) + +/*--- TIOA11_2_IN ---*/ +#define SetPinFunc_TIOA11_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 24u, 2u, 3u ); \ + bFM_GPIO_PFR5_PC = 1u; \ + }while (0u) + +/*--- TIOA11_2_OUT ---*/ +#define SetPinFunc_TIOA11_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 26u, 2u, 3u ); \ + bFM_GPIO_PFR5_PC = 1u; \ + }while (0u) + +/*--- TIOA12_0_OUT ---*/ +#define SetPinFunc_TIOA12_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P4 = 1u; \ + }while (0u) + +/*--- TIOA12_1_OUT ---*/ +#define SetPinFunc_TIOA12_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 2u, 2u, 2u ); \ + bFM_GPIO_PFRB_P6 = 1u; \ + }while (0u) + +/*--- TIOA12_2_OUT ---*/ +#define SetPinFunc_TIOA12_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 2u, 2u, 3u ); \ + bFM_GPIO_PFR5_PE = 1u; \ + }while (0u) + +/*--- TIOA13_0_IN ---*/ +#define SetPinFunc_TIOA13_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- TIOA13_0_OUT ---*/ +#define SetPinFunc_TIOA13_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P5 = 1u; \ + }while (0u) + +/*--- TIOA13_1_IN ---*/ +#define SetPinFunc_TIOA13_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 8u, 2u, 2u ); \ + bFM_GPIO_PFR2_P4 = 1u; \ + }while (0u) + +/*--- TIOA13_1_OUT ---*/ +#define SetPinFunc_TIOA13_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN29=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 10u, 2u, 2u ); \ + bFM_GPIO_PFR2_P4 = 1u; \ + }while (0u) + +/*--- TIOA13_2_IN ---*/ +#define SetPinFunc_TIOA13_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 8u, 2u, 3u ); \ + bFM_GPIO_PFR3_P0 = 1u; \ + }while (0u) + +/*--- TIOA13_2_OUT ---*/ +#define SetPinFunc_TIOA13_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 10u, 2u, 3u ); \ + bFM_GPIO_PFR3_P0 = 1u; \ + }while (0u) + +/*--- TIOA14_0_OUT ---*/ +#define SetPinFunc_TIOA14_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 18u, 2u, 1u ); \ + bFM_GPIO_PFRC_P6 = 1u; \ + }while (0u) + +/*--- TIOA14_1_OUT ---*/ +#define SetPinFunc_TIOA14_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 18u, 2u, 2u ); \ + bFM_GPIO_PFRF_P6 = 1u; \ + }while (0u) + +/*--- TIOA14_2_OUT ---*/ +#define SetPinFunc_TIOA14_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 18u, 2u, 3u ); \ + bFM_GPIO_PFR6_P8 = 1u; \ + }while (0u) + +/*--- TIOA15_0_IN ---*/ +#define SetPinFunc_TIOA15_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_PA = 1u; \ + }while (0u) + +/*--- TIOA15_0_OUT ---*/ +#define SetPinFunc_TIOA15_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 26u, 2u, 1u ); \ + bFM_GPIO_PFRC_PA = 1u; \ + }while (0u) + +/*--- TIOA15_1_IN ---*/ +#define SetPinFunc_TIOA15_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 24u, 2u, 2u ); \ + bFM_GPIO_PFRF_P0 = 1u; \ + }while (0u) + +/*--- TIOA15_1_OUT ---*/ +#define SetPinFunc_TIOA15_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 26u, 2u, 2u ); \ + bFM_GPIO_PFRF_P0 = 1u; \ + }while (0u) + +/*--- TIOA15_2_IN ---*/ +#define SetPinFunc_TIOA15_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 24u, 2u, 3u ); \ + bFM_GPIO_PFR6_P6 = 1u; \ + }while (0u) + +/*--- TIOA15_2_OUT ---*/ +#define SetPinFunc_TIOA15_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 26u, 2u, 3u ); \ + bFM_GPIO_PFR6_P6 = 1u; \ + }while (0u) + +/*--- TIOA1_0_IN ---*/ +#define SetPinFunc_TIOA1_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- TIOA1_0_OUT ---*/ +#define SetPinFunc_TIOA1_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 10u, 2u, 1u ); \ + bFM_GPIO_PFR4_P1 = 1u; \ + }while (0u) + +/*--- TIOA1_1_IN ---*/ +#define SetPinFunc_TIOA1_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 8u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- TIOA1_1_OUT ---*/ +#define SetPinFunc_TIOA1_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 10u, 2u, 2u ); \ + bFM_GPIO_PFR3_PA = 1u; \ + }while (0u) + +/*--- TIOA1_2_IN ---*/ +#define SetPinFunc_TIOA1_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 8u, 2u, 3u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- TIOA1_2_OUT ---*/ +#define SetPinFunc_TIOA1_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 10u, 2u, 3u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- TIOA2_0_OUT ---*/ +#define SetPinFunc_TIOA2_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 18u, 2u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- TIOA2_1_OUT ---*/ +#define SetPinFunc_TIOA2_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 18u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- TIOA2_2_OUT ---*/ +#define SetPinFunc_TIOA2_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN06=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 18u, 2u, 3u ); \ + bFM_GPIO_PFR1_P6 = 1u; \ + }while (0u) + +/*--- TIOA3_0_IN ---*/ +#define SetPinFunc_TIOA3_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 24u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- TIOA3_0_OUT ---*/ +#define SetPinFunc_TIOA3_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 26u, 2u, 1u ); \ + bFM_GPIO_PFR4_P3 = 1u; \ + }while (0u) + +/*--- TIOA3_1_IN ---*/ +#define SetPinFunc_TIOA3_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 24u, 2u, 2u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- TIOA3_1_OUT ---*/ +#define SetPinFunc_TIOA3_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 26u, 2u, 2u ); \ + bFM_GPIO_PFR3_PC = 1u; \ + }while (0u) + +/*--- TIOA3_2_IN ---*/ +#define SetPinFunc_TIOA3_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 24u, 2u, 3u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- TIOA3_2_OUT ---*/ +#define SetPinFunc_TIOA3_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN08=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 26u, 2u, 3u ); \ + bFM_GPIO_PFR1_P8 = 1u; \ + }while (0u) + +/*--- TIOA4_0_OUT ---*/ +#define SetPinFunc_TIOA4_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 2u, 2u, 1u ); \ + bFM_GPIO_PFR4_P4 = 1u; \ + }while (0u) + +/*--- TIOA4_1_OUT ---*/ +#define SetPinFunc_TIOA4_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 2u, 2u, 2u ); \ + bFM_GPIO_PFR3_PD = 1u; \ + }while (0u) + +/*--- TIOA4_2_OUT ---*/ +#define SetPinFunc_TIOA4_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 2u, 2u, 3u ); \ + bFM_GPIO_PFR1_PA = 1u; \ + }while (0u) + +/*--- TIOA5_0_IN ---*/ +#define SetPinFunc_TIOA5_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 8u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- TIOA5_0_OUT ---*/ +#define SetPinFunc_TIOA5_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 10u, 2u, 1u ); \ + bFM_GPIO_PFR4_P5 = 1u; \ + }while (0u) + +/*--- TIOA5_1_IN ---*/ +#define SetPinFunc_TIOA5_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 8u, 2u, 2u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- TIOA5_1_OUT ---*/ +#define SetPinFunc_TIOA5_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 10u, 2u, 2u ); \ + bFM_GPIO_PFR3_PE = 1u; \ + }while (0u) + +/*--- TIOA5_2_IN ---*/ +#define SetPinFunc_TIOA5_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 8u, 2u, 3u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- TIOA5_2_OUT ---*/ +#define SetPinFunc_TIOA5_2_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 10u, 2u, 3u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- TIOA6_0_OUT ---*/ +#define SetPinFunc_TIOA6_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 18u, 2u, 1u ); \ + bFM_GPIO_PFRC_P2 = 1u; \ + }while (0u) + +/*--- TIOA6_1_OUT ---*/ +#define SetPinFunc_TIOA6_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 18u, 2u, 2u ); \ + bFM_GPIO_PFRF_P2 = 1u; \ + }while (0u) + +/*--- TIOA6_2_OUT ---*/ +#define SetPinFunc_TIOA6_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 18u, 2u, 3u ); \ + bFM_GPIO_PFR6_PC = 1u; \ + }while (0u) + +/*--- TIOA7_0_IN ---*/ +#define SetPinFunc_TIOA7_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 24u, 2u, 1u ); \ + bFM_GPIO_PFRC_P4 = 1u; \ + }while (0u) + +/*--- TIOA7_0_OUT ---*/ +#define SetPinFunc_TIOA7_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 26u, 2u, 1u ); \ + bFM_GPIO_PFRC_P4 = 1u; \ + }while (0u) + +/*--- TIOA7_1_IN ---*/ +#define SetPinFunc_TIOA7_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 24u, 2u, 2u ); \ + bFM_GPIO_PFRF_P4 = 1u; \ + }while (0u) + +/*--- TIOA7_1_OUT ---*/ +#define SetPinFunc_TIOA7_1_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 26u, 2u, 2u ); \ + bFM_GPIO_PFRF_P4 = 1u; \ + }while (0u) + +/*--- TIOA7_2_IN ---*/ +#define SetPinFunc_TIOA7_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 24u, 2u, 3u ); \ + bFM_GPIO_PFR6_PA = 1u; \ + }while (0u) + +/*--- TIOA7_2_OUT ---*/ +#define SetPinFunc_TIOA7_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 26u, 2u, 3u ); \ + bFM_GPIO_PFR6_PA = 1u; \ + }while (0u) + +/*--- TIOA8_0_OUT ---*/ +#define SetPinFunc_TIOA8_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 2u, 2u, 1u ); \ + bFM_GPIO_PFRA_P0 = 1u; \ + }while (0u) + +/*--- TIOA8_1_OUT ---*/ +#define SetPinFunc_TIOA8_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN14=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 2u, 2u, 2u ); \ + bFM_GPIO_PFR1_PE = 1u; \ + }while (0u) + +/*--- TIOA8_2_OUT ---*/ +#define SetPinFunc_TIOA8_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 2u, 2u, 3u ); \ + bFM_GPIO_PFR5_P0 = 1u; \ + }while (0u) + +/*--- TIOA9_0_IN ---*/ +#define SetPinFunc_TIOA9_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- TIOA9_0_OUT ---*/ +#define SetPinFunc_TIOA9_0_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 10u, 2u, 1u ); \ + bFM_GPIO_PFRA_P1 = 1u; \ + }while (0u) + +/*--- TIOA9_1_IN ---*/ +#define SetPinFunc_TIOA9_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 8u, 2u, 2u ); \ + bFM_GPIO_PFRB_P0 = 1u; \ + }while (0u) + +/*--- TIOA9_1_OUT ---*/ +#define SetPinFunc_TIOA9_1_OUT(dummy) do{ \ + bFM_GPIO_ADE_AN16=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 10u, 2u, 2u ); \ + bFM_GPIO_PFRB_P0 = 1u; \ + }while (0u) + +/*--- TIOA9_2_IN ---*/ +#define SetPinFunc_TIOA9_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 8u, 2u, 3u ); \ + bFM_GPIO_PFR5_P2 = 1u; \ + }while (0u) + +/*--- TIOA9_2_OUT ---*/ +#define SetPinFunc_TIOA9_2_OUT(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 10u, 2u, 3u ); \ + bFM_GPIO_PFR5_P2 = 1u; \ + }while (0u) + +/*--- TIOB0_0_IN ---*/ +#define SetPinFunc_TIOB0_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 4u, 3u, 1u ); \ + bFM_GPIO_PFR7_P2 = 1u; \ + }while (0u) + +/*--- TIOB0_1_IN ---*/ +#define SetPinFunc_TIOB0_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 4u, 3u, 2u ); \ + bFM_GPIO_PFR5_P6 = 1u; \ + }while (0u) + +/*--- TIOB0_2_IN ---*/ +#define SetPinFunc_TIOB0_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN01=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 4u, 3u, 3u ); \ + bFM_GPIO_PFR1_P1 = 1u; \ + }while (0u) + +/*--- TIOB10_0_IN ---*/ +#define SetPinFunc_TIOB10_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 20u, 2u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- TIOB10_1_IN ---*/ +#define SetPinFunc_TIOB10_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN19=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 20u, 2u, 2u ); \ + bFM_GPIO_PFRB_P3 = 1u; \ + }while (0u) + +/*--- TIOB10_2_IN ---*/ +#define SetPinFunc_TIOB10_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 20u, 2u, 3u ); \ + bFM_GPIO_PFR5_P5 = 1u; \ + }while (0u) + +/*--- TIOB11_0_IN ---*/ +#define SetPinFunc_TIOB11_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 28u, 2u, 1u ); \ + bFM_GPIO_PFRA_PF = 1u; \ + }while (0u) + +/*--- TIOB11_1_IN ---*/ +#define SetPinFunc_TIOB11_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 28u, 2u, 2u ); \ + bFM_GPIO_PFRB_P5 = 1u; \ + }while (0u) + +/*--- TIOB11_2_IN ---*/ +#define SetPinFunc_TIOB11_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 28u, 2u, 3u ); \ + bFM_GPIO_PFR5_PD = 1u; \ + }while (0u) + +/*--- TIOB12_0_IN ---*/ +#define SetPinFunc_TIOB12_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 4u, 2u, 1u ); \ + bFM_GPIO_PFR0_P8 = 1u; \ + }while (0u) + +/*--- TIOB12_1_IN ---*/ +#define SetPinFunc_TIOB12_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN23=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 4u, 2u, 2u ); \ + bFM_GPIO_PFRB_P7 = 1u; \ + }while (0u) + +/*--- TIOB12_2_IN ---*/ +#define SetPinFunc_TIOB12_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 4u, 2u, 3u ); \ + bFM_GPIO_PFR5_PF = 1u; \ + }while (0u) + +/*--- TIOB13_0_IN ---*/ +#define SetPinFunc_TIOB13_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 12u, 2u, 1u ); \ + bFM_GPIO_PFR0_P9 = 1u; \ + }while (0u) + +/*--- TIOB13_1_IN ---*/ +#define SetPinFunc_TIOB13_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 12u, 2u, 2u ); \ + bFM_GPIO_PFR2_P3 = 1u; \ + }while (0u) + +/*--- TIOB13_2_IN ---*/ +#define SetPinFunc_TIOB13_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 12u, 2u, 3u ); \ + bFM_GPIO_PFR3_P1 = 1u; \ + }while (0u) + +/*--- TIOB14_0_IN ---*/ +#define SetPinFunc_TIOB14_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 20u, 2u, 1u ); \ + bFM_GPIO_PFRC_P5 = 1u; \ + }while (0u) + +/*--- TIOB14_1_IN ---*/ +#define SetPinFunc_TIOB14_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 20u, 2u, 2u ); \ + bFM_GPIO_PFRF_P7 = 1u; \ + }while (0u) + +/*--- TIOB14_2_IN ---*/ +#define SetPinFunc_TIOB14_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 20u, 2u, 3u ); \ + bFM_GPIO_PFR6_P9 = 1u; \ + }while (0u) + +/*--- TIOB15_0_IN ---*/ +#define SetPinFunc_TIOB15_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 28u, 2u, 1u ); \ + bFM_GPIO_PFRC_P9 = 1u; \ + }while (0u) + +/*--- TIOB15_1_IN ---*/ +#define SetPinFunc_TIOB15_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 28u, 2u, 2u ); \ + bFM_GPIO_PFRF_P1 = 1u; \ + }while (0u) + +/*--- TIOB15_2_IN ---*/ +#define SetPinFunc_TIOB15_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR13, 28u, 2u, 3u ); \ + bFM_GPIO_PFR6_P7 = 1u; \ + }while (0u) + +/*--- TIOB1_0_IN ---*/ +#define SetPinFunc_TIOB1_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P3 = 1u; \ + }while (0u) + +/*--- TIOB1_1_IN ---*/ +#define SetPinFunc_TIOB1_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 12u, 2u, 2u ); \ + bFM_GPIO_PFR5_P7 = 1u; \ + }while (0u) + +/*--- TIOB1_2_IN ---*/ +#define SetPinFunc_TIOB1_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN05=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 12u, 2u, 3u ); \ + bFM_GPIO_PFR1_P5 = 1u; \ + }while (0u) + +/*--- TIOB2_0_IN ---*/ +#define SetPinFunc_TIOB2_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 20u, 2u, 1u ); \ + bFM_GPIO_PFR7_P4 = 1u; \ + }while (0u) + +/*--- TIOB2_1_IN ---*/ +#define SetPinFunc_TIOB2_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 20u, 2u, 2u ); \ + bFM_GPIO_PFR5_P8 = 1u; \ + }while (0u) + +/*--- TIOB2_2_IN ---*/ +#define SetPinFunc_TIOB2_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 20u, 2u, 3u ); \ + bFM_GPIO_PFR1_P7 = 1u; \ + }while (0u) + +/*--- TIOB3_0_IN ---*/ +#define SetPinFunc_TIOB3_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 28u, 2u, 1u ); \ + bFM_GPIO_PFR7_P5 = 1u; \ + }while (0u) + +/*--- TIOB3_1_IN ---*/ +#define SetPinFunc_TIOB3_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 28u, 2u, 2u ); \ + bFM_GPIO_PFR5_P9 = 1u; \ + }while (0u) + +/*--- TIOB3_2_IN ---*/ +#define SetPinFunc_TIOB3_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR04, 28u, 2u, 3u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- TIOB4_0_IN ---*/ +#define SetPinFunc_TIOB4_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 4u, 2u, 1u ); \ + bFM_GPIO_PFR7_P6 = 1u; \ + }while (0u) + +/*--- TIOB4_1_IN ---*/ +#define SetPinFunc_TIOB4_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 4u, 2u, 2u ); \ + bFM_GPIO_PFR5_PA = 1u; \ + }while (0u) + +/*--- TIOB4_2_IN ---*/ +#define SetPinFunc_TIOB4_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 4u, 2u, 3u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- TIOB5_0_IN ---*/ +#define SetPinFunc_TIOB5_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 12u, 2u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- TIOB5_1_IN ---*/ +#define SetPinFunc_TIOB5_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 12u, 2u, 2u ); \ + bFM_GPIO_PFR5_PB = 1u; \ + }while (0u) + +/*--- TIOB5_2_IN ---*/ +#define SetPinFunc_TIOB5_2_IN(dummy) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 12u, 2u, 3u ); \ + bFM_GPIO_PFR1_PD = 1u; \ + }while (0u) + +/*--- TIOB6_0_IN ---*/ +#define SetPinFunc_TIOB6_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 20u, 2u, 1u ); \ + bFM_GPIO_PFRC_P1 = 1u; \ + }while (0u) + +/*--- TIOB6_1_IN ---*/ +#define SetPinFunc_TIOB6_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 20u, 2u, 2u ); \ + bFM_GPIO_PFRF_P3 = 1u; \ + }while (0u) + +/*--- TIOB6_2_IN ---*/ +#define SetPinFunc_TIOB6_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 20u, 2u, 3u ); \ + bFM_GPIO_PFR6_PD = 1u; \ + }while (0u) + +/*--- TIOB7_0_IN ---*/ +#define SetPinFunc_TIOB7_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 28u, 2u, 1u ); \ + bFM_GPIO_PFRC_P3 = 1u; \ + }while (0u) + +/*--- TIOB7_1_IN ---*/ +#define SetPinFunc_TIOB7_1_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 28u, 2u, 2u ); \ + bFM_GPIO_PFRF_P5 = 1u; \ + }while (0u) + +/*--- TIOB7_2_IN ---*/ +#define SetPinFunc_TIOB7_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR05, 28u, 2u, 3u ); \ + bFM_GPIO_PFR6_PB = 1u; \ + }while (0u) + +/*--- TIOB8_0_IN ---*/ +#define SetPinFunc_TIOB8_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- TIOB8_1_IN ---*/ +#define SetPinFunc_TIOB8_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN15=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 4u, 2u, 2u ); \ + bFM_GPIO_PFR1_PF = 1u; \ + }while (0u) + +/*--- TIOB8_2_IN ---*/ +#define SetPinFunc_TIOB8_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 4u, 2u, 3u ); \ + bFM_GPIO_PFR5_P1 = 1u; \ + }while (0u) + +/*--- TIOB9_0_IN ---*/ +#define SetPinFunc_TIOB9_0_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 12u, 2u, 1u ); \ + bFM_GPIO_PFRA_PD = 1u; \ + }while (0u) + +/*--- TIOB9_1_IN ---*/ +#define SetPinFunc_TIOB9_1_IN(dummy) do{ \ + bFM_GPIO_ADE_AN17=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 12u, 2u, 2u ); \ + bFM_GPIO_PFRB_P1 = 1u; \ + }while (0u) + +/*--- TIOB9_2_IN ---*/ +#define SetPinFunc_TIOB9_2_IN(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR12, 12u, 2u, 3u ); \ + bFM_GPIO_PFR5_P3 = 1u; \ + }while (0u) + +/*--- TMS ---*/ +#define SetPinFunc_TMS(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 16u, 1u, 1u ); \ + bFM_GPIO_PFR0_P3 = 1u; \ + }while (0u) + +/*--- TRACECLK ---*/ +#define SetPinFunc_TRACECLK(dummy) do{ \ + bFM_GPIO_ADE_AN09=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 24u, 1u, 1u ); \ + bFM_GPIO_PFR1_P9 = 1u; \ + }while (0u) + +/*--- TRACED0 ---*/ +#define SetPinFunc_TRACED0(dummy) do{ \ + bFM_GPIO_ADE_AN10=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 24u, 1u, 1u ); \ + bFM_GPIO_PFR1_PA = 1u; \ + }while (0u) + +/*--- TRACED1 ---*/ +#define SetPinFunc_TRACED1(dummy) do{ \ + bFM_GPIO_ADE_AN11=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 24u, 1u, 1u ); \ + bFM_GPIO_PFR1_PB = 1u; \ + }while (0u) + +/*--- TRACED10 ---*/ +#define SetPinFunc_TRACED10(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_PA = 1u; \ + }while (0u) + +/*--- TRACED11 ---*/ +#define SetPinFunc_TRACED11(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_PB = 1u; \ + }while (0u) + +/*--- TRACED12 ---*/ +#define SetPinFunc_TRACED12(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_PC = 1u; \ + }while (0u) + +/*--- TRACED13 ---*/ +#define SetPinFunc_TRACED13(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_PD = 1u; \ + }while (0u) + +/*--- TRACED14 ---*/ +#define SetPinFunc_TRACED14(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_PE = 1u; \ + }while (0u) + +/*--- TRACED15 ---*/ +#define SetPinFunc_TRACED15(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_PF = 1u; \ + }while (0u) + +/*--- TRACED2 ---*/ +#define SetPinFunc_TRACED2(dummy) do{ \ + bFM_GPIO_ADE_AN12=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 25u, 1u, 1u ); \ + bFM_GPIO_PFR1_PC = 1u; \ + }while (0u) + +/*--- TRACED3 ---*/ +#define SetPinFunc_TRACED3(dummy) do{ \ + bFM_GPIO_ADE_AN13=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 25u, 1u, 1u ); \ + bFM_GPIO_PFR1_PD = 1u; \ + }while (0u) + +/*--- TRACED4 ---*/ +#define SetPinFunc_TRACED4(dummy) do{ \ + bFM_GPIO_ADE_AN20=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 26u, 1u, 1u ); \ + bFM_GPIO_PFRB_P4 = 1u; \ + }while (0u) + +/*--- TRACED5 ---*/ +#define SetPinFunc_TRACED5(dummy) do{ \ + bFM_GPIO_ADE_AN21=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 26u, 1u, 1u ); \ + bFM_GPIO_PFRB_P5 = 1u; \ + }while (0u) + +/*--- TRACED6 ---*/ +#define SetPinFunc_TRACED6(dummy) do{ \ + bFM_GPIO_ADE_AN22=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 26u, 1u, 1u ); \ + bFM_GPIO_PFRB_P6 = 1u; \ + }while (0u) + +/*--- TRACED7 ---*/ +#define SetPinFunc_TRACED7(dummy) do{ \ + bFM_GPIO_ADE_AN23=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 26u, 1u, 1u ); \ + bFM_GPIO_PFRB_P7 = 1u; \ + }while (0u) + +/*--- TRACED8 ---*/ +#define SetPinFunc_TRACED8(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_P8 = 1u; \ + }while (0u) + +/*--- TRACED9 ---*/ +#define SetPinFunc_TRACED9(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 27u, 1u, 1u ); \ + bFM_GPIO_PFRB_P9 = 1u; \ + }while (0u) + +/*--- TRSTX ---*/ +#define SetPinFunc_TRSTX(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 17u, 1u, 1u ); \ + bFM_GPIO_PFR0_P0 = 1u; \ + }while (0u) + +/*--- TX0_0 ---*/ +#define SetPinFunc_TX0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 26u, 2u, 1u ); \ + bFM_GPIO_PFRA_PC = 1u; \ + }while (0u) + +/*--- TX0_1 ---*/ +#define SetPinFunc_TX0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 26u, 2u, 2u ); \ + bFM_GPIO_PFR3_P1 = 1u; \ + }while (0u) + +/*--- TX0_2 ---*/ +#define SetPinFunc_TX0_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 26u, 2u, 3u ); \ + bFM_GPIO_PFR9_P7 = 1u; \ + }while (0u) + +/*--- TX1_0 ---*/ +#define SetPinFunc_TX1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 30u, 2u, 1u ); \ + bFM_GPIO_PFR2_P6 = 1u; \ + }while (0u) + +/*--- TX1_1 ---*/ +#define SetPinFunc_TX1_1(dummy) do{ \ + bFM_GPIO_ADE_AN04=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 30u, 2u, 2u ); \ + bFM_GPIO_PFR1_P4 = 1u; \ + }while (0u) + +/*--- TX1_2 ---*/ +#define SetPinFunc_TX1_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 30u, 2u, 3u ); \ + bFM_GPIO_PFRB_PC = 1u; \ + }while (0u) + +/*--- TX2_0 ---*/ +#define SetPinFunc_TX2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 2u, 2u, 1u ); \ + bFM_GPIO_PFR7_PE = 1u; \ + }while (0u) + +/*--- TX2_1 ---*/ +#define SetPinFunc_TX2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 2u, 2u, 2u ); \ + bFM_GPIO_PFRF_P1 = 1u; \ + }while (0u) + +/*--- TX2_2 ---*/ +#define SetPinFunc_TX2_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR25, 2u, 2u, 3u ); \ + bFM_GPIO_PFR4_PE = 1u; \ + }while (0u) + +/*--- UDM0 ---*/ +#define SetPinFunc_UDM0(dummy) do{ \ + bFM_GPIO_SPSR_USB0C=1u; \ + }while (0u) + +/*--- UDM1 ---*/ +#define SetPinFunc_UDM1(dummy) do{ \ + bFM_GPIO_SPSR_USB1C=1u; \ + }while (0u) + +/*--- UDP0 ---*/ +#define SetPinFunc_UDP0(dummy) do{ \ + bFM_GPIO_SPSR_USB0C=1u; \ + }while (0u) + +/*--- UDP1 ---*/ +#define SetPinFunc_UDP1(dummy) do{ \ + bFM_GPIO_SPSR_USB1C=1u; \ + }while (0u) + +/*--- UHCONX0 ---*/ +#define SetPinFunc_UHCONX0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 9u, 1u, 1u ); \ + bFM_GPIO_PFR6_P1 = 1u; \ + }while (0u) + +/*--- UHCONX1 ---*/ +#define SetPinFunc_UHCONX1(dummy) do{ \ + bFM_GPIO_ADE_AN30=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR00, 13u, 1u, 1u ); \ + bFM_GPIO_PFR2_P3 = 1u; \ + }while (0u) + +/*--- VREGCTL ---*/ +#define SetPinFunc_VREGCTL(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPFR_VPFR0=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- VWAKEUP ---*/ +#define SetPinFunc_VWAKEUP(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + bFM_RTC_VBPFR_VPFR1=0u; \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- WKUP0 ---*/ +#define SetPinFunc_WKUP0(dummy) do{ \ + bFM_GPIO_PFR2_P0 = 1u; \ + }while (0u) + +/*--- WKUP1 ---*/ +#define SetPinFunc_WKUP1(dummy) do{ \ + bFM_GPIO_PFRA_P8 = 1u; \ + }while (0u) + +/*--- WKUP2 ---*/ +#define SetPinFunc_WKUP2(dummy) do{ \ + bFM_GPIO_PFR7_PD = 1u; \ + }while (0u) + +/*--- WKUP3 ---*/ +#define SetPinFunc_WKUP3(dummy) do{ \ + bFM_GPIO_PFR6_P0 = 1u; \ + }while (0u) + +/*--- X0 ---*/ +#define SetPinFunc_X0(dummy) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 1u); \ + }while (0u) + +/*--- X0A ---*/ +#define SetPinFunc_X0A(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- X1 ---*/ +#define SetPinFunc_X1(dummy) do{ \ + PINCONFIG_SET_REG(FM_GPIO->SPSR, 2u, 2u, 1u); \ + }while (0u) + +/*--- X1A ---*/ +#define SetPinFunc_X1A(dummy) do{ \ + bFM_RTC_VDET_PON = 0u; \ + FM_RTC->WTCR20_f.PREAD = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + PINCONFIG_SET_REG(FM_RTC->VBPFR, 4u, 2u, 0x00u); \ + FM_RTC->WTCR20_f.PWRITE = 1u; \ + while(0u != FM_RTC->WTCR10_f.TRANS){} \ + }while (0u) + +/*--- ZIN0_0 ---*/ +#define SetPinFunc_ZIN0_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 4u, 2u, 1u ); \ + bFM_GPIO_PFR4_P2 = 1u; \ + }while (0u) + +/*--- ZIN0_1 ---*/ +#define SetPinFunc_ZIN0_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 4u, 2u, 2u ); \ + bFM_GPIO_PFR4_PC = 1u; \ + }while (0u) + +/*--- ZIN0_2 ---*/ +#define SetPinFunc_ZIN0_2(dummy) do{ \ + bFM_GPIO_ADE_AN02=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 4u, 2u, 3u ); \ + bFM_GPIO_PFR1_P2 = 1u; \ + }while (0u) + +/*--- ZIN1_0 ---*/ +#define SetPinFunc_ZIN1_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 10u, 2u, 1u ); \ + bFM_GPIO_PFR7_P7 = 1u; \ + }while (0u) + +/*--- ZIN1_1 ---*/ +#define SetPinFunc_ZIN1_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 10u, 2u, 2u ); \ + bFM_GPIO_PFRF_PA = 1u; \ + }while (0u) + +/*--- ZIN1_2 ---*/ +#define SetPinFunc_ZIN1_2(dummy) do{ \ + bFM_GPIO_ADE_AN07=0u; \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR09, 10u, 2u, 3u ); \ + bFM_GPIO_PFR1_P7 = 1u; \ + }while (0u) + +/*--- ZIN2_0 ---*/ +#define SetPinFunc_ZIN2_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 4u, 2u, 1u ); \ + bFM_GPIO_PFRA_P2 = 1u; \ + }while (0u) + +/*--- ZIN2_1 ---*/ +#define SetPinFunc_ZIN2_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 4u, 2u, 2u ); \ + bFM_GPIO_PFR3_P3 = 1u; \ + }while (0u) + +/*--- ZIN2_2 ---*/ +#define SetPinFunc_ZIN2_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR14, 4u, 2u, 3u ); \ + bFM_GPIO_PFRB_PB = 1u; \ + }while (0u) + +/*--- ZIN3_0 ---*/ +#define SetPinFunc_ZIN3_0(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 8u, 2u, 1u ); \ + bFM_GPIO_PFRA_PE = 1u; \ + }while (0u) + +/*--- ZIN3_1 ---*/ +#define SetPinFunc_ZIN3_1(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 8u, 2u, 2u ); \ + bFM_GPIO_PFR3_PB = 1u; \ + }while (0u) + +/*--- ZIN3_2 ---*/ +#define SetPinFunc_ZIN3_2(dummy) do{ \ + PINRELOC_SET_EPFR( FM_GPIO->EPFR18, 8u, 2u, 3u ); \ + bFM_GPIO_PFRB_PF = 1u; \ + }while (0u) + +/****************************************************************************** + ANALOG PINS +*******************************************************************************/ + +/*--- AN00 ---*/ +#define SetPinFunc_AN00(dummy) do{ \ + bFM_GPIO_ADE_AN00=1u; \ + }while (0u) + +/*--- AN01 ---*/ +#define SetPinFunc_AN01(dummy) do{ \ + bFM_GPIO_ADE_AN01=1u; \ + }while (0u) + +/*--- AN02 ---*/ +#define SetPinFunc_AN02(dummy) do{ \ + bFM_GPIO_ADE_AN02=1u; \ + }while (0u) + +/*--- AN03 ---*/ +#define SetPinFunc_AN03(dummy) do{ \ + bFM_GPIO_ADE_AN03=1u; \ + }while (0u) + +/*--- AN04 ---*/ +#define SetPinFunc_AN04(dummy) do{ \ + bFM_GPIO_ADE_AN04=1u; \ + }while (0u) + +/*--- AN05 ---*/ +#define SetPinFunc_AN05(dummy) do{ \ + bFM_GPIO_ADE_AN05=1u; \ + }while (0u) + +/*--- AN06 ---*/ +#define SetPinFunc_AN06(dummy) do{ \ + bFM_GPIO_ADE_AN06=1u; \ + }while (0u) + +/*--- AN07 ---*/ +#define SetPinFunc_AN07(dummy) do{ \ + bFM_GPIO_ADE_AN07=1u; \ + }while (0u) + +/*--- AN08 ---*/ +#define SetPinFunc_AN08(dummy) do{ \ + bFM_GPIO_ADE_AN08=1u; \ + }while (0u) + +/*--- AN09 ---*/ +#define SetPinFunc_AN09(dummy) do{ \ + bFM_GPIO_ADE_AN09=1u; \ + }while (0u) + +/*--- AN10 ---*/ +#define SetPinFunc_AN10(dummy) do{ \ + bFM_GPIO_ADE_AN10=1u; \ + }while (0u) + +/*--- AN11 ---*/ +#define SetPinFunc_AN11(dummy) do{ \ + bFM_GPIO_ADE_AN11=1u; \ + }while (0u) + +/*--- AN12 ---*/ +#define SetPinFunc_AN12(dummy) do{ \ + bFM_GPIO_ADE_AN12=1u; \ + }while (0u) + +/*--- AN13 ---*/ +#define SetPinFunc_AN13(dummy) do{ \ + bFM_GPIO_ADE_AN13=1u; \ + }while (0u) + +/*--- AN14 ---*/ +#define SetPinFunc_AN14(dummy) do{ \ + bFM_GPIO_ADE_AN14=1u; \ + }while (0u) + +/*--- AN15 ---*/ +#define SetPinFunc_AN15(dummy) do{ \ + bFM_GPIO_ADE_AN15=1u; \ + }while (0u) + +/*--- AN16 ---*/ +#define SetPinFunc_AN16(dummy) do{ \ + bFM_GPIO_ADE_AN16=1u; \ + }while (0u) + +/*--- AN17 ---*/ +#define SetPinFunc_AN17(dummy) do{ \ + bFM_GPIO_ADE_AN17=1u; \ + }while (0u) + +/*--- AN18 ---*/ +#define SetPinFunc_AN18(dummy) do{ \ + bFM_GPIO_ADE_AN18=1u; \ + }while (0u) + +/*--- AN19 ---*/ +#define SetPinFunc_AN19(dummy) do{ \ + bFM_GPIO_ADE_AN19=1u; \ + }while (0u) + +/*--- AN20 ---*/ +#define SetPinFunc_AN20(dummy) do{ \ + bFM_GPIO_ADE_AN20=1u; \ + }while (0u) + +/*--- AN21 ---*/ +#define SetPinFunc_AN21(dummy) do{ \ + bFM_GPIO_ADE_AN21=1u; \ + }while (0u) + +/*--- AN22 ---*/ +#define SetPinFunc_AN22(dummy) do{ \ + bFM_GPIO_ADE_AN22=1u; \ + }while (0u) + +/*--- AN23 ---*/ +#define SetPinFunc_AN23(dummy) do{ \ + bFM_GPIO_ADE_AN23=1u; \ + }while (0u) + +/*--- AN24 ---*/ +#define SetPinFunc_AN24(dummy) do{ \ + bFM_GPIO_ADE_AN24=1u; \ + }while (0u) + +/*--- AN25 ---*/ +#define SetPinFunc_AN25(dummy) do{ \ + bFM_GPIO_ADE_AN25=1u; \ + }while (0u) + +/*--- AN26 ---*/ +#define SetPinFunc_AN26(dummy) do{ \ + bFM_GPIO_ADE_AN26=1u; \ + }while (0u) + +/*--- AN27 ---*/ +#define SetPinFunc_AN27(dummy) do{ \ + bFM_GPIO_ADE_AN27=1u; \ + }while (0u) + +/*--- AN28 ---*/ +#define SetPinFunc_AN28(dummy) do{ \ + bFM_GPIO_ADE_AN28=1u; \ + }while (0u) + +/*--- AN29 ---*/ +#define SetPinFunc_AN29(dummy) do{ \ + bFM_GPIO_ADE_AN29=1u; \ + }while (0u) + +/*--- AN30 ---*/ +#define SetPinFunc_AN30(dummy) do{ \ + bFM_GPIO_ADE_AN30=1u; \ + }while (0u) + +/*--- AN31 ---*/ +#define SetPinFunc_AN31(dummy) do{ \ + bFM_GPIO_ADE_AN31=1u; \ + }while (0u) + +#endif // #ifndef __GPIO_S6E2C5XL_H__ + + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hbif/hbif.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hbif/hbif.c new file mode 100644 index 0000000000..3bb24be51d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hbif/hbif.c @@ -0,0 +1,471 @@ +/****************************************************************************** +* \file hbif.c +* +* \version 1.20 +* +* \brief Hyper Bus Interface driver +* +******************************************************************************* +\copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "hbif/hbif.h" + +#if (defined(PDL_PERIPHERAL_HBIF_ACTIVE)) + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ +func_ptr_t pfnHbifIrqCb; +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ +/** + ***************************************************************************** + ** This function initialises one specific HBIF module with the parameters + ** provided in the given configuration structure. + ** After successful initialization the HBIF module is ready to use. + ** + ** Hbif_Init() has to be called with the parameter pstcConfig of type + ** stc_hbif_config_t. + ** + ** All values in pstcConfig have to be in valid range (see hbif.h for allowed + ** ranges of dedicated parameters). + ** + ** To reset and disable the HBIF module the function Hbif_DeInit() has to + ** be used. + ** + ** \param [in] pstcConfig Pointer to HBIF configuration parameters + ** + ** \return - Ok on successful init + ** - ErrorInvalidParameter if pointers are NULL + *****************************************************************************/ +en_result_t Hbif_Init(const stc_hbif_config_t* pstcConfig) +{ + if(NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + + // Configure memory space 0 + if (NULL != pstcConfig->pstcMem0Config) + { + // Set continuous read merging Option + FM_HYPERBUS->MCR0_f.CRMO = pstcConfig->pstcMem0Config->bMergeContinuousRead; + + // Set asymmetry cache system support + FM_HYPERBUS->MCR0_f.ACS = pstcConfig->pstcMem0Config->bSupportAsymmetryCache; + + // Access to memory or register + FM_HYPERBUS->MCR0_f.CRT = pstcConfig->pstcMem0Config->bRegisterSpace; + + // Set device type + FM_HYPERBUS->MCR0_f.DEVTYPE = pstcConfig->pstcMem0Config->bHyperRamDevice; + + // Set wrap size + switch (pstcConfig->pstcMem0Config->enWrapBustsize) + { + case HbifWrap64Bytes: + case HbifWrap16Bytes: + case HbifWrap32Bytes: + FM_HYPERBUS->MCR0_f.WRAPSIZE = pstcConfig->pstcMem0Config->enWrapBustsize; + break; + default: + return ErrorInvalidParameter; + } + + // Set read chip select high cycle between operations + if (pstcConfig->pstcMem0Config->enReadCsHighCycle > HbifCshi165Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR0_f.RCSHI = pstcConfig->pstcMem0Config->enReadCsHighCycle; + + // Set write chip select high cycle between operations + if (pstcConfig->pstcMem0Config->enWriteCsHighCycle > HbifCshi165Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR0_f.WCSHI = pstcConfig->pstcMem0Config->enWriteCsHighCycle; + + // Set read Chip select setup cycle to next CK rising edge + if (pstcConfig->pstcMem0Config->enReadCsNextClkCycle > HbifCcs16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR0_f.RCSS = pstcConfig->pstcMem0Config->enReadCsNextClkCycle; + + // Set write Chip select setup cycle to next CK rising edge + if (pstcConfig->pstcMem0Config->enWriteCsNextClkCycle > HbifCcs16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR0_f.WCSS = pstcConfig->pstcMem0Config->enWriteCsNextClkCycle; + + // Set read chip select hold after CK falling Edge + if (pstcConfig->pstcMem0Config->enReadCsHoldCycle > HbifCsh16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR0_f.RCSH = pstcConfig->pstcMem0Config->enReadCsHoldCycle; + + // Set write chip select hold after CK falling Edge + if (pstcConfig->pstcMem0Config->enWriteCsHoldCycle > HbifCsh16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR0_f.WCSH = pstcConfig->pstcMem0Config->enWriteCsHoldCycle; + + // Set latency cycle for HyperRAM mode + switch (pstcConfig->pstcMem0Config->enHyperRamLatencyCycle) + { + case HbRamLatency4Clk: + FM_HYPERBUS->MTR0_f.LTCY = 15u; + break; + case HbRamLatency5Clk: + FM_HYPERBUS->MTR0_f.LTCY = 0u; + break; + case HbRamLatency6Clk: + FM_HYPERBUS->MTR0_f.LTCY = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set base address of memory space 0 + FM_HYPERBUS->MBR0 = pstcConfig->pstcMem0Config->u32MemBaseAddress ; + } + + // Configure memory space 1 + if (NULL != pstcConfig->pstcMem1Config) + { + // Set base address of memory space 1 + FM_HYPERBUS->MBR1 = pstcConfig->pstcMem1Config->u32MemBaseAddress ; + + // Set continuous read merging Option + FM_HYPERBUS->MCR1_f.CRMO = pstcConfig->pstcMem1Config->bMergeContinuousRead; + + // Set asymmetry cache system support + FM_HYPERBUS->MCR1_f.ACS = pstcConfig->pstcMem1Config->bSupportAsymmetryCache; + + // Access to memory or register + FM_HYPERBUS->MCR1_f.CRT = pstcConfig->pstcMem1Config->bRegisterSpace; + + // Set device type + FM_HYPERBUS->MCR1_f.DEVTYPE = pstcConfig->pstcMem1Config->bHyperRamDevice; + + // Set wrap size + switch (pstcConfig->pstcMem1Config->enWrapBustsize) + { + case HbifWrap64Bytes: + case HbifWrap16Bytes: + case HbifWrap32Bytes: + FM_HYPERBUS->MCR1_f.WRAPSIZE = pstcConfig->pstcMem1Config->enWrapBustsize; + break; + default: + return ErrorInvalidParameter; + } + + // Set read chip select high cycle between operations + if (pstcConfig->pstcMem1Config->enReadCsHighCycle > HbifCshi165Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR1_f.RCSHI = pstcConfig->pstcMem1Config->enReadCsHighCycle; + + // Set write chip select high cycle between operations + if (pstcConfig->pstcMem1Config->enWriteCsHighCycle > HbifCshi165Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR1_f.WCSHI = pstcConfig->pstcMem1Config->enWriteCsHighCycle; + + // Set read Chip select setup cycle to next CK rising edge + if (pstcConfig->pstcMem1Config->enReadCsNextClkCycle > HbifCcs16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR1_f.RCSS = pstcConfig->pstcMem1Config->enReadCsNextClkCycle; + + // Set write Chip select setup cycle to next CK rising edge + if (pstcConfig->pstcMem1Config->enWriteCsNextClkCycle > HbifCcs16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR1_f.WCSS = pstcConfig->pstcMem1Config->enWriteCsNextClkCycle; + + // Set read chip select hold after CK falling Edge + if (pstcConfig->pstcMem1Config->enReadCsHoldCycle > HbifCsh16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR1_f.RCSH = pstcConfig->pstcMem1Config->enReadCsHoldCycle; + + // Set write chip select hold after CK falling Edge + if (pstcConfig->pstcMem1Config->enWriteCsHoldCycle > HbifCsh16Clk) + { + return ErrorInvalidParameter; + } + + FM_HYPERBUS->MTR1_f.WCSH = pstcConfig->pstcMem1Config->enWriteCsHoldCycle; + + // Set latency cycle for HyperRAM mode + switch (pstcConfig->pstcMem1Config->enHyperRamLatencyCycle) + { + case HbRamLatency4Clk: + FM_HYPERBUS->MTR1_f.LTCY = 15u; + break; + case HbRamLatency5Clk: + FM_HYPERBUS->MTR1_f.LTCY = 0u; + break; + case HbRamLatency6Clk: + FM_HYPERBUS->MTR1_f.LTCY = 1u; + break; + default: + return ErrorInvalidParameter; + } + } + + // Disable write protection + FM_HYPERBUS->WPR_f.WP = 0u; + + // Pull GPO pin to low + FM_HYPERBUS->GPOR = 0u; + +#if (PDL_INTERRUPT_ENABLE_HBIF == PDL_ON) + pfnHbifIrqCb = pstcConfig->pfnIrqCb; + FM_HYPERBUS->IEN_f.INTP = pstcConfig->bInterruptPolarity; + FM_HYPERBUS->IEN_f.RPCINTE = pstcConfig->bEnableInterrupt; + + if (TRUE == pstcConfig->bTouchNvic) + { + NVIC_ClearPendingIRQ(GDC_HYPERBUS_IRQn); + NVIC_EnableIRQ(GDC_HYPERBUS_IRQn); + NVIC_SetPriority(GDC_HYPERBUS_IRQn, PDL_IRQ_LEVEL_HBIF); + } +#endif + + return Ok ; +} // Hbif_Init + +/** + ***************************************************************************** + ** \brief Deinitializes the HBIF module. + ** + ** Any pending transmission or reception will be aborted and all HBIF related + ** registers are reset to their default values. + ** + ** \param [in] bTouchNvic TRUE = De-Init NVIC + ** + ** \retval Ok HBIF module has been successfully deinitialized + *****************************************************************************/ +en_result_t Hbif_DeInit(boolean_t bTouchNvic) +{ + // Reset all HBIF registers + FM_HYPERBUS->IEN = 0u; + FM_HYPERBUS->MBR0 = 0u; + FM_HYPERBUS->MBR1 = 0u; + FM_HYPERBUS->MCR0 = 0u; + FM_HYPERBUS->MCR1 = 0u; + FM_HYPERBUS->MTR0 = 0u; + FM_HYPERBUS->MTR1 = 0u; + FM_HYPERBUS->GPOR = 0u; + FM_HYPERBUS->WPR = 0u; + +#if (PDL_INTERRUPT_ENABLE_HBIF == PDL_ON) + if(TRUE == bTouchNvic) + { + NVIC_ClearPendingIRQ(GDC_HYPERBUS_IRQn); + NVIC_DisableIRQ(GDC_HYPERBUS_IRQn); + NVIC_SetPriority(GDC_HYPERBUS_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif + + return Ok ; +} // Hbif_DeInit + + +/** + ****************************************************************************** + ** \brief Get status of HBIF according to status type + ** + ** \param [in] enStatus HBIF status type + ** \arg HbifRstoDuringWrite RSTO Error in Write Transaction + ** \arg HbifTransactionErrDuringWrite Transaction Error in Write Transaction + ** \arg HbifDecodeErrDuringWrite Decode Error in Write Transaction + ** \arg HbifWriteActive Write Transaction Active + ** \arg HbifRdsStallDuringRead RDS Stall Error in Read Transaction + ** \arg HbifRstoDuringRead RSTO Error in Read Transaction + ** \arg HbifTransactionErrDuringRead Transaction Error in Read Transaction + ** \arg HbifDecodeErrDuringRead Decode Error in Read Transaction + ** \arg HbifReadActive Read Transaction Active + ** + ** \retval FALSE If one of following conditions are met: + ** - RSTO Normal operation during write [enStatus = HbifRstoDuringWrite] + ** - Normal operation during write [enStatus = HbifTransactionErrDuringWrite] + ** - Decode normally [enStatus = HbifDecodeErrDuringWrite] + ** - Write transaction is idle [enStatus = HbifWriteActive] + ** - No RDS stall error [enStatus = HbifRdsStallDuringRead] + ** - RSTO Normal operation during read [enStatus = HbifRstoDuringRead] + ** - Noemal oepration during read [enStatus = HbifTransactionErrDuringRead] + ** - No decode error [enStatus = HbifDecodeErrDuringRead] + ** - Read transaction is idle [enStatus = HbifReadActive] + ** \retval TRUE If one of following conditions are met: + ** - HyperBus memory is under reset (AXI SLVERR occurs) [enStatus = HbifRstoDuringWrite] + ** - Protocol is not supported (AXI SLVERR occurs) [enStatus = HbifTransactionErrDuringWrite] + ** - Access address is not reachable (AXI DECERR occurs) [enStatus = HbifDecodeErrDuringWrite] + ** - Write transaction is active [enStatus = HbifWriteActive] + ** - Detect read data error (AXI SLVERR occurs) [enStatus = HbifRdsStallDuringRead] + ** - HyperBus memory is under reset (AXI SLVERR occurs) [enStatus = HbifRstoDuringRead] + ** - Protocol is not supported (AXI SLVERR occurs) [enStatus = HbifTransactionErrDuringRead] + ** - Access address is not reachable (AXI DECERR occurs)(AXI SLVERR occurs) [enStatus = HbifDecodeErrDuringRead] + ** - Read transaction is active [enStatus = I2sRxFifoOverflow] + ** + ******************************************************************************/ +boolean_t Hbif_GetStatus(en_hbif_status_t enStatus) +{ + boolean_t bRet = FALSE; + + switch(enStatus) + { + case HbifRstoDuringWrite: + bRet = (FM_HYPERBUS->CSR_f.WRSTOERR == 1u) ? TRUE : FALSE; + break; + case HbifTransactionErrDuringWrite: + bRet = (FM_HYPERBUS->CSR_f.WTRSERR == 1u) ? TRUE : FALSE; + break; + case HbifDecodeErrDuringWrite: + bRet = (FM_HYPERBUS->CSR_f.WDECERR == 1u) ? TRUE : FALSE; + break; + case HbifWriteActive: + bRet = (FM_HYPERBUS->CSR_f.WACT == 1u) ? TRUE : FALSE; + break; + case HbifRdsStallDuringRead: + bRet = (FM_HYPERBUS->CSR_f.RDSSTALL == 1u) ? TRUE : FALSE; + break; + case HbifRstoDuringRead: + bRet = (FM_HYPERBUS->CSR_f.RRSTOERR == 1u) ? TRUE : FALSE; + break; + case HbifTransactionErrDuringRead: + bRet = (FM_HYPERBUS->CSR_f.RTRSERR == 1u) ? TRUE : FALSE; + break; + case HbifDecodeErrDuringRead: + bRet = (FM_HYPERBUS->CSR_f.RDECERR == 1u) ? TRUE : FALSE; + break; + case HbifReadActive: + bRet = (FM_HYPERBUS->CSR_f.RACT == 1u) ? TRUE : FALSE; + break; + } + + return bRet; +} + +/** + ***************************************************************************** + ** \brief Get the interrupt flag of HyperBus interface + ** + ** \retval FALSE HBIF interrupt flag is not set + ** \retval TRUE HBIF interrupt flag is set + *****************************************************************************/ +boolean_t Hbif_GetInterruptFlag(void) +{ + boolean_t bFlag = FALSE; + + bFlag = (FM_HYPERBUS->ISR_f.RPCINTS == 1u) ? TRUE : FALSE; + + return bFlag; +} + +/** + ***************************************************************************** + ** \brief Set write protection of HBIF + ** + ** \param bEnableWp Enable write protect or not + ** + ** \retval Ok Write protection is set + ** + *****************************************************************************/ +en_result_t Hbif_SetWriteProtection(boolean_t bEnableWp) +{ + FM_HYPERBUS->WPR_f.WP = bEnableWp; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Set GPO0 output pin level of HBIF + ** + ** \param bLevel Output level + ** + ** \retval Ok GPO0 output pin level set + ** + *****************************************************************************/ +en_result_t Hbif_SetGpo0Level(boolean_t bLevel) +{ + FM_HYPERBUS->GPOR_f.GPO0 = bLevel; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Set GPO1 output pin level of HBIF + ** + ** \param bLevel Output level + ** + ** \retval Ok GPO1 output pin level set + ** + *****************************************************************************/ +en_result_t Hbif_SetGpo1Level(boolean_t bLevel) +{ + FM_HYPERBUS->GPOR_f.GPO1 = bLevel; + + return Ok; +} + +#endif + +/*****************************************************************************/ +/* EOF (not truncated) */ +/*****************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hbif/hbif.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hbif/hbif.h new file mode 100644 index 0000000000..57c80403ff --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hbif/hbif.h @@ -0,0 +1,303 @@ +/****************************************************************************** +* \file hbif.h +* +* \version 1.20 +* +* \brief Headerfile for Hyper Bus Interface functions +* +******************************************************************************* +\copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __HBIF_H__ +#define __HBIF_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_HBIF_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** +* \defgroup GroupHBIF Hyper Bus Interface (HBIF) +* \{ +* \defgroup GroupHBIF_Functions Functions +* \defgroup GroupHBIF_DataStructures Data Structures +* \defgroup GroupHBIF_Types Enumerated Types +* \} +*/ +/** +* \addtogroup GroupHBIF +* \{ +* The HyperBus interface(HBIF) enables your code to access +* the HyperBus memory devices (both Flash and RAM). The HyperBus achieves high speed +* read/write throughput by using a double data rate interface.
+* Features of the HyperBus Interface include:
+* - Supports operational frequency up to 166 MHz
+* - Achieves maximum 333 MB/s data throughput
+* - Supports the double data rate interface
+* - Supports maximum 4 GByte address space
+* - Supports two slave devices
+* - Supports XiP operation by dynamic wrapped burst request
+* - Has a low pin count
+* +* \section SectionHBIF_ConfigurationConsideration Configuration Consideration +* You specify general configuration settings in the stc_hbif_config_t structure. +* This includes the address of two memory configurations, for memory space 0 and space 1. +* You specify memory configuration in the stc_hbif_mem_config_t +* structure and provide the pointers to these in the general configuration settings.
+* After specifying settings, call:
+* - Hbif_Init() to initialize HBIF configuration.
+* +* - Hbif_GetStatus() to get the status of HyberBus during data transaction.
+* +* - Hbif_GetInterruptFlag() to get the interrupt flag of HyberBus.
+* +* - Hbif_SetWriteProtection() to set write protection to external Hyper Flash.
+* +* - Hbif_SetGpo0Level() to set the level of GPO0 pin and Hbif_SetGpo1Level() sets +* the level of GPO1 pin.
+ +* \section SectionHBIF_MoreInfo More Information +* For more information on the HBIF peripheral, refer to:
+* FM4 Peripheral Manual Communication Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/*****************************************************************************/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + + /** +* \addtogroup GroupHBIF_Types +* \{ +*/ + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ +/** + ***************************************************************************** + ** \brief HyperBus interface status types + *****************************************************************************/ +typedef enum en_hbif_status +{ + HbifRstoDuringWrite = 0u, ///< RSTO Error in Write Transaction + HbifTransactionErrDuringWrite = 1u, ///< Transaction Error in Write Transaction + HbifDecodeErrDuringWrite = 2u, ///< Decode Error in Write Transaction + HbifWriteActive = 3u, ///< Write Transaction Active + HbifRdsStallDuringRead = 4u, ///< RDS Stall Error in Read Transaction + HbifRstoDuringRead = 5u, ///< RSTO Error in Read Transaction + HbifTransactionErrDuringRead = 6u, ///< Transaction Error in Read Transaction + HbifDecodeErrDuringRead = 7u, ///< Decode Error in Read Transaction + HbifReadActive = 8u, ///< Read Transaction Active + +}en_hbif_status_t; + +/** + ***************************************************************************** + ** \brief Wrap size types + *****************************************************************************/ +typedef enum en_hbif_wrap_size +{ + HbifWrap64Bytes = 1u, ///< Wrap bust length: 64 bytes + HbifWrap16Bytes = 2u, ///< Wrap bust length: 16 bytes + HbifWrap32Bytes = 3u, ///< Wrap bust length: 32 bytes + +}en_hbif_wrap_size_t; + +/** + ***************************************************************************** + ** \brief Chip Select High Cycle Between Operations + *****************************************************************************/ +typedef enum en_hbif_cshi_cycle_t +{ + HbifCshi15Clk = 0u, ///< Insert 1.5 clock to the chip select high period + HbifCshi25Clk = 1u, ///< Insert 2.5 clock to the chip select high period + HbifCshi35Clk = 2u, ///< Insert 3.5 clock to the chip select high period + HbifCshi45Clk = 3u, ///< Insert 4.5 clock to the chip select high period + HbifCshi55Clk = 4u, ///< Insert 5.5 clock to the chip select high period + HbifCshi65Clk = 5u, ///< Insert 6.5 clock to the chip select high period + HbifCshi75Clk = 6u, ///< Insert 7.5 clock to the chip select high period + HbifCshi85Clk = 7u, ///< Insert 8.5 clock to the chip select high period + HbifCshi95Clk = 8u, ///< Insert 9.5 clock to the chip select high period + HbifCshi105Clk = 9u, ///< Insert 10.5 clock to the chip select high period + HbifCshi115Clk = 10u, ///< Insert 11.5 clock to the chip select high period + HbifCshi125Clk = 11u, ///< Insert 12.5 clock to the chip select high period + HbifCshi135Clk = 12u, ///< Insert 13.5 clock to the chip select high period + HbifCshi145Clk = 13u, ///< Insert 14.5 clock to the chip select high period + HbifCshi155Clk = 14u, ///< Insert 15.5 clock to the chip select high period + HbifCshi165Clk = 15u, ///< Insert 16.5 clock to the chip select high period + +}en_hbif_rcshi_cycle_t, en_hbif_wcshi_cycle_t; + +/** + ***************************************************************************** + ** \brief Chip Select Setup To Next CK Rising Edge + *****************************************************************************/ +typedef enum en_hbif_css_cycle_t +{ + HbifCcs1Clk = 0u, ///< inserts the 1 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs2Clk = 1u, ///< inserts the 2 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs3Clk = 2u, ///< inserts the 3 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs4Clk = 3u, ///< inserts the 4 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs5Clk = 4u, ///< inserts the 5 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs6Clk = 5u, ///< inserts the 6 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs7Clk = 6u, ///< inserts the 7 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs8Clk = 7u, ///< inserts the 8 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs9Clk = 8u, ///< inserts the 9 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs10Clk = 9u, ///< inserts the 10 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs11Clk = 10u, ///< inserts the 11 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs12Clk = 11u, ///< inserts the 12 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs13Clk = 12u, ///< inserts the 13 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs14Clk = 13u, ///< inserts the 14 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs15Clk = 14u, ///< inserts the 15 cycles, between the falling edge of chip select and the rising edge of first CK. + HbifCcs16Clk = 15u, ///< inserts the 16 cycles, between the falling edge of chip select and the rising edge of first CK. + +}en_hbif_rcss_cycle_t, en_hbif_wcss_cycle_t; + +/** + ***************************************************************************** + ** \brief Chip Select Setup To Next CK Rising Edge + *****************************************************************************/ +typedef enum en_hbif_csh_cycle_t +{ + HbifCsh1Clk = 0u, ///< inserts the 1 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh2Clk = 1u, ///< inserts the 2 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh3Clk = 2u, ///< inserts the 3 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh4Clk = 3u, ///< inserts the 4 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh5Clk = 4u, ///< inserts the 5 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh6Clk = 5u, ///< inserts the 6 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh7Clk = 6u, ///< inserts the 7 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh8Clk = 7u, ///< inserts the 8 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh9Clk = 8u, ///< inserts the 9 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh10Clk = 9u, ///< inserts the 10 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh11Clk = 10u, ///< inserts the 11 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh12Clk = 11u, ///< inserts the 12 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh13Clk = 12u, ///< inserts the 13 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh14Clk = 13u, ///< inserts the 14 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh15Clk = 14u, ///< inserts the 15 cycles, between the falling edge of last CK and the rising edge of chip select. + HbifCsh16Clk = 15u, ///< inserts the 16 cycles, between the falling edge of last CK and the rising edge of chip select. + +}en_hbif_rcsh_cycle_t, en_hbif_wcsh_cycle_t; + +/** + ***************************************************************************** + ** \brief Latency Cycle for HyperRAM mode + *****************************************************************************/ +typedef enum en_hbif_ltcy_cycle +{ + HbRamLatency4Clk = 0u, + HbRamLatency5Clk = 1u, + HbRamLatency6Clk = 2u, + +}en_hbif_ltcy_cycle_t; + +/** \}GroupHBIF_Types */ +/** +* \addtogroup GroupHBIF_DataStructures +* \{ +*/ + +/** + ***************************************************************************** + ** \brief Hyber Flash memory conguration structure + *****************************************************************************/ +typedef struct stc_hbif_mem_config +{ + uint32_t u32MemBaseAddress; ///< The base address for memory space + boolean_t bMergeContinuousRead; ///< TRUE: wrap transaction and subsequent continuous transaction can be merged + ///< FALSE: wrap transaction and subsequent continuous transaction can't be merged + boolean_t bSupportAsymmetryCache; ///< TRUE: asymmetry cache system support + ///< FALSE: no asymmetry cache system support + boolean_t bRegisterSpace; ///< TRUE: access register space, FALSE: access memory space + boolean_t bHyperRamDevice; ///< TRUE: connect with HyperRAM memory, FALSE: connect with HyperFlash memory + en_hbif_wrap_size_t enWrapBustsize; ///< Wrapped burst size type + en_hbif_rcshi_cycle_t enReadCsHighCycle; ///< Before the read access, this setting inserts the CK cycles to the chip select high period. + en_hbif_wcshi_cycle_t enWriteCsHighCycle; ///< Before the write access, this setting inserts the CK cycles to the chip select high period. + en_hbif_rcss_cycle_t enReadCsNextClkCycle; ///< In the read access, this setting inserts the CK cycles, between the falling edge of chip select and the rising edge of first CK. + en_hbif_wcss_cycle_t enWriteCsNextClkCycle; ///< In the write access, this setting inserts the CK cycles, between the falling edge of chip select and the rising edge of first CK. + en_hbif_rcsh_cycle_t enReadCsHoldCycle; ///< In the read access, this setting inserts the CK cycles, between the falling edge of last CK and the rising edge of chip select. + en_hbif_wcsh_cycle_t enWriteCsHoldCycle; ///< In the write access, this setting inserts the CK cycles, between the falling edge of last CK and the rising edge of chip select + en_hbif_ltcy_cycle_t enHyperRamLatencyCycle; ///< Latency Cycle for HyperRAM mode, ignored when the connected device is HyperFlash + boolean_t bGpoOutputLevel; ///< TRUE: output high from GPO; FALSE: output low from GPO + +}stc_hbif_mem_config_t; + +/** + ***************************************************************************** + ** \brief I2S configuration + *****************************************************************************/ +typedef struct stc_hbif_config +{ + stc_hbif_mem_config_t *pstcMem0Config; ///< Pointer to memory space 0 configuration + stc_hbif_mem_config_t *pstcMem1Config; ///< Pointer to memory space 1 configuration + +#if (PDL_INTERRUPT_ENABLE_HBIF == PDL_ON) + boolean_t bEnableInterrupt; ///< TRUE: enable hyper bus interrupt, FALSE: disable interrupt + boolean_t bInterruptPolarity; ///< TRUE: IENOn signal is active high, FALSE: IENOn signal is active low + func_ptr_t pfnIrqCb; ///< Pointer to interrupt callback structure + boolean_t bTouchNvic; ///< TRUE: Enable NVIC, FALSE: disable NVIC +#endif + +} stc_hbif_config_t; + +/** \} GroupHBIF_DataStructures */ + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ +/** +* \addtogroup GroupHBIF_Functions +* \{ +*/ +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ +en_result_t Hbif_Init(const stc_hbif_config_t* pstcConfig) ; +en_result_t Hbif_DeInit(boolean_t bTouchNvic) ; +boolean_t Hbif_GetStatus(en_hbif_status_t enStatus); +boolean_t Hbif_GetInterruptFlag(void); +en_result_t Hbif_SetWriteProtection(boolean_t bEnableWp); +en_result_t Hbif_SetGpo0Level(boolean_t bLevel); +en_result_t Hbif_SetGpo1Level(boolean_t bLevel); + + +/** \} GroupHBIF_Functions */ +/** \} GroupHBIF */ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /* __I2S_H__ */ +/*****************************************************************************/ +/* EOF (not truncated) */ +/*****************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hsspi/hsspi.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hsspi/hsspi.c new file mode 100644 index 0000000000..3f484d8cc4 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hsspi/hsspi.c @@ -0,0 +1,1615 @@ +/****************************************************************************** +* \file hsspi.c +* +* \version 1.20 +* +* \brief High Speed Quad Serial Peripheral Interface driver +* +******************************************************************************* +\copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************//*****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "hsspi/hsspi.h" + +#if (defined(PDL_PERIPHERAL_HSSPI_ACTIVE)) + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('define') */ +/*****************************************************************************/ +/** + ***************************************************************************** + ** \brief Transmit and receive maximum FIFO depth. + *****************************************************************************/ +#define HS_SPI_MAX_FIFO_DEPTH (16u) + +/** +******************************************************************************* +** \brief HS-SPI transfer mode (hardware). +** +** Selects hardware transfer mode of the HS-SPI core. +******************************************************************************/ +#define HSSPI_DIRECT_MODE_TX_RX_SINGLE_MODE (0x0u) ///< Transmit and receive in single mode. +#define HSSPI_DIRECT_MODE_RX_ONLY_SINGLE_MODE (0x4u) ///< Receive only, in single mode +#define HSSPI_DIRECT_MODE_RX_ONLY_DUAL_MODE (0x5u) ///< Receive only, in dual mode +#define HSSPI_DIRECT_MODE_RX_ONLY_QUAD_MODE (0x6u) ///< Receive only, in quad mode +#define HSSPI_DIRECT_MODE_TX_ONLY_SINGLE_MODE (0x8u) ///< Transmit only, in single mode. +#define HSSPI_DIRECT_MODE_TX_ONLY_DUAL_MODE (0x9u) ///< Transmit only, in dual mode. +#define HSSPI_DIRECT_MODE_TX_ONLY_QUAD_MODE (0xAu) ///< Transmit only, in quad mode. + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/// Look-up table for all enabled I2S instances and their internal data +stc_hsspi_instance_data_t m_astcHsSpiInstanceDataLut[HS_SPI_INSTANCE_COUNT] = +{ + #if (PDL_PERIPHERAL_ENABLE_HSSPI0 == PDL_ON) + { + &HSSPI0, // pstcInstance + 0u, + {0u, 0u, 0u, 0u, 0u, HsSpiClkLowOutFallingInRising, HsSpiProtocolModeSingle, 0u} // stcInternData (not initialized yet) + } + #endif +}; + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ +static en_result_t HsSpi_ModuleEnable (volatile stc_hsspin_t* pstcHsSpi); +static en_result_t HsSpi_ModuleDisable(volatile stc_hsspin_t* pstcHsSpi); + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain HS-SPI instance. + ** + ** \param [in] pstcHsSpi Pointer to HS-SPI instance + ** + ** \return Pointer to internal data or NULL if instance is + ** not enabled (or not known) + ******************************************************************************/ +static stc_hsspi_intern_data_t* HsSpiGetInternDataPtr(volatile stc_hsspin_t* pstcHsSpi) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < HS_SPI_INSTANCE_COUNT; u8Instance++) + { + if (pstcHsSpi == m_astcHsSpiInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcHsSpiInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} + +/** + ***************************************************************************** + ** \brief Globally enable SPI module by setting bit MEN + ** + ** \param [in] pstcHsSpi Pointer to HS-SPI instance + ** + ** \retval Ok HS-SPI module successfully Enaabled. + ** \retval Error pstcHsSpi == NULL + ** \retval ErrorTimeout Operation timed out + *****************************************************************************/ +static en_result_t HsSpi_ModuleEnable(volatile stc_hsspin_t* pstcHsSpi) +{ + uint32_t u32TimeOut; + u32TimeOut = 100000000u; + + if(NULL == pstcHsSpi) + { + return Error; + } + + // Set module enable bit in module control register. + pstcHsSpi->MCTRL_f.MEN = 1u; + + // Wait until module enable status bit is set by hardware + while ((0u == pstcHsSpi->MCTRL_f.MES) && (u32TimeOut > 0u)) + { + PDL_WAIT_LOOP_HOOK(); + u32TimeOut--; + } + + if(0ul == u32TimeOut) + { + return ErrorTimeout; + } + + return Ok; +} // HsSpiModuleEnable + +/** + ***************************************************************************** + ** \brief Globally disable HS-SPI module by clearing bit MEN + ** + ** \param [in] pstcHsSpi Pointer to HS-SPI instance + ** + ** \retval Ok HS-SPI module successfully Disabled. + ** \retval Error Operation timed out, pstcHsSpi == NULL + *****************************************************************************/ +static en_result_t HsSpi_ModuleDisable(volatile stc_hsspin_t* pstcHsSpi) +{ + uint32_t u32TimeOut; + u32TimeOut = 100000000u; + + if(NULL == pstcHsSpi) + { + return Error; + } + + // Clear module enable bit in module control register. + pstcHsSpi->MCTRL_f.MEN = 0u; + + // Wait until module enable status bit is reset by hardware... + while ((0u != pstcHsSpi->MCTRL_f.MES) && (u32TimeOut > 0u)) + { + PDL_WAIT_LOOP_HOOK(); + u32TimeOut--; + } + + if(0ul == u32TimeOut) + { + return Error; + } + + return Ok; +} // HsSpiModuleDisable + +/** + ***************************************************************************** + ** \brief Initialisation of the HS-SPI module. + ** FIFO width is limited to 8 bit and DMA is not supported in + ** direct mode. The (high speed) SPI module is initialized in direct mode after + ** call of Spi_Init(). + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register start + ** address of HS-SPI module). + ** \param [in] pstcConfig HS-SPI configuration parameters. + ** + ** \retval Ok HS-SPI module successfully initialised. + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcHsSpi == NULL + ** - pstcConfig == NULL + ** - pstcConfig->u8TxFifoThresholdLow > (HS_SPI_MAX_FIFO_DEPTH - 1) + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled HS-SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +en_result_t HsSpi_Init(volatile stc_hsspin_t* pstcHsSpi, const stc_hsspi_config_t* pstcConfig) +{ + stc_hsspi_intern_data_t* pstcHsSpiInternData; // Pointer to internal data + stc_hsspi_cscfg_field_t stcCSCFG; + en_result_t enResult; + + PDL_ZERO_STRUCT(stcCSCFG); + + // Check for NULL-Pointers + if (NULL == pstcHsSpi || + NULL == pstcConfig + ) + { + return ErrorInvalidParameter; + } + + // Check for Threshold in Range + if (pstcConfig->u8TxFifoThresholdLow > (HS_SPI_MAX_FIFO_DEPTH - 1u)) + { + return ErrorInvalidParameter; + } + + // Get ptr to internal data struct ... + pstcHsSpiInternData = HsSpiGetInternDataPtr(pstcHsSpi); + // ... and check + if (NULL == pstcHsSpiInternData) + { + return ErrorInvalidParameter; + } + + // Just to ensure, Everything is switched off + enResult = HsSpi_ModuleDisable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Release STOP bit + pstcHsSpi->DMSTOP = 0x00u; // .STOP = 0; + + // Store callback functions to intern data struct. + pstcHsSpiInternData->pfnTxStatusCallbackFunction = pstcConfig->pfnTxStatusCallback; + + // Reset direct mode DMA enable register. + pstcHsSpi->DMDMAEN = 0x00u; // Rx and Tx DMA disabled + + // Save protocol mode + pstcHsSpiInternData->enDirectModeProtocol = pstcConfig->enDirectModeProtocol; + + // Save operation mode + pstcHsSpiInternData->bMasterOperation = pstcConfig->bMasterOperation; + + // Set prescaler + switch(pstcConfig->enClockDivider) + { + case HsSpiClkDividerDiv1: + pstcHsSpi->QDCLKR_f.QHDIV = 0x00u; + break; + case HsSpiClkDividerDiv2: + pstcHsSpi->QDCLKR_f.QHDIV = 0x01u; + break; + case HsSpiClkDividerDiv3: + pstcHsSpi->QDCLKR_f.QHDIV = 0x02u; + break; + case HsSpiClkDividerDiv4: + pstcHsSpi->QDCLKR_f.QHDIV = 0x03u; + break; + case HsSpiClkDividerDiv5: + pstcHsSpi->QDCLKR_f.QHDIV = 0x04u; + break; + case HsSpiClkDividerDiv6: + pstcHsSpi->QDCLKR_f.QHDIV = 0x05u; + break; + case HsSpiClkDividerDiv7: + pstcHsSpi->QDCLKR_f.QHDIV = 0x06u; + break; + case HsSpiClkDividerDiv8: + pstcHsSpi->QDCLKR_f.QHDIV = 0x07u; + break; + case HsSpiClkDividerDiv9: + pstcHsSpi->QDCLKR_f.QHDIV = 0x08u; + break; + case HsSpiClkDividerDiv10: + pstcHsSpi->QDCLKR_f.QHDIV = 0x09u; + break; + case HsSpiClkDividerDiv11: + pstcHsSpi->QDCLKR_f.QHDIV = 0x0Au; + break; + case HsSpiClkDividerDiv12: + pstcHsSpi->QDCLKR_f.QHDIV = 0x0Bu; + break; + case HsSpiClkDividerDiv13: + pstcHsSpi->QDCLKR_f.QHDIV = 0x0Cu; + break; + case HsSpiClkDividerDiv14: + pstcHsSpi->QDCLKR_f.QHDIV = 0x0Du; + break; + case HsSpiClkDividerDiv15: + pstcHsSpi->QDCLKR_f.QHDIV = 0x0Eu; + break; + case HsSpiClkDividerDiv16: + pstcHsSpi->QDCLKR_f.QHDIV = 0x0Fu; + break; + default: + return ErrorInvalidParameter; + } + + // Just a default (will be setup by the transfer function) + pstcHsSpi->DMTRP = (uint8_t)pstcConfig->enDirectModeProtocol; + + // Set direct mode configuration register. + pstcHsSpi->DMCFG_f.SSDC = 1u; // Slave Select Deassert is controlled by DMBCC:BCC + + // Reset direct mode byte count control register. + pstcHsSpi->DMBCC = 1u; + + // Set FIFO configuration register. + pstcHsSpi->FIFOCFG_f.FWIDTH = pstcConfig->enFifoWidth; // FIFO width + pstcHsSpi->FIFOCFG_f.RXFTH = 0x7u; // RX FIFO threshold + pstcHsSpi->FIFOCFG_f.TXFTH = pstcConfig->u8TxFifoThresholdLow; // TX FIFO threshold + + // Reset command sequencer address extension register. + pstcHsSpi->CSAEXT = 0x00ul; + + // Set command sequencer idle time register. + pstcHsSpi->CSITIME = (uint32_t)pstcConfig->u16IdleTimeOut; + + // Set command sequencer configuration register. + stcCSCFG.SSEL3EN = 0u; // Disable access to slave select 3 memory + stcCSCFG.SSEL2EN = 0u; // Disable access to slave select 2 memory + stcCSCFG.SSEL1EN = 0u; // Disable access to slave select 1 memory + stcCSCFG.SSEL0EN = 0u; // Disable access to slave select 0 memory + //stcCSCFG.SSEL0EN = 1u; // Enable access to slave select 0 memory + stcCSCFG.MSEL = pstcConfig->enMemoryBankSize; // Range of the AHB address space associated with each slave select line + stcCSCFG.MBM = pstcConfig->enCommandSequencerModeProtocol; // Multi bit mode + stcCSCFG.SRAM = pstcConfig->enMemoryType; // Serial Flash or SRAM device + + pstcHsSpi->CSCFG_f = stcCSCFG; // Save to register + + // Set TX/RX DMA bridge + pstcHsSpi->DBCNT_f.TXDBEN = (TRUE == pstcConfig->bTxDmaBridgeEnable) ? 1u : 0u; + pstcHsSpi->DBCNT_f.RXDBEN = (TRUE == pstcConfig->bRxDmaBridgeEnable) ? 1u : 0u; + + enResult = HsSpi_ModuleEnable(pstcHsSpi); // Now switch module on + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + return Ok; +} // HsSpi_Init + +/** + ***************************************************************************** + ** \brief De-Initializes the HS-SPI unit. + ** All registers which are used by HS-SPI will be reset to their default value. + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register + ** start address of HS-SPI module). + ** + ** \retval Ok + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - pstcHsSpi == NULL + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled HS-SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +en_result_t HsSpi_DeInit(volatile stc_hsspin_t* pstcHsSpi) +{ + stc_hsspi_intern_data_t* pstcHsSpiInternData; // Pointer to internal data + en_result_t enResult; + + // Check for NULL-Pointer + if (NULL == pstcHsSpi) + { + return ErrorInvalidParameter; + } + + // Get ptr to internal data struct ... + pstcHsSpiInternData = HsSpiGetInternDataPtr(pstcHsSpi); + // ... and check + if (NULL == pstcHsSpiInternData) + { + return ErrorInvalidParameter; + } + + // Stop any transfer and de-assert slave. + pstcHsSpi->DMSTOP = 0x01u; // STOP = 1; + + // Just to ensure, anything is switched off + enResult = HsSpi_ModuleDisable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Reset callback functions and receive buffer. + pstcHsSpiInternData->pfnTxStatusCallbackFunction = NULL; + pstcHsSpiInternData->pu8RXBuffer = NULL; + + // Reset peripheral communication register (PCC0 .. PCC3). + pstcHsSpi->PCC0_f.SAFESYNC = 1u; + pstcHsSpi->PCC1_f.SAFESYNC = 1u; + pstcHsSpi->PCC2_f.SAFESYNC = 1u; + pstcHsSpi->PCC3_f.SAFESYNC = 1u; + + // Disable and clear transmit interrupt. + pstcHsSpi->TXE = 0u; + + pstcHsSpi->TXC_f.TSSRC = 1u; + pstcHsSpi->TXC_f.TFMTC = 1u; + pstcHsSpi->TXC_f.TFLETC = 1u; + pstcHsSpi->TXC_f.TFUC = 1u; + pstcHsSpi->TXC_f.TFOC = 1u; + pstcHsSpi->TXC_f.TFEC = 1u; + pstcHsSpi->TXC_f.TFFC = 1u; + + // Disable and clear receive interrupt. + pstcHsSpi->RXE = 0u; + pstcHsSpi->RXC_f.RSSRC = 1u; + pstcHsSpi->RXC_f.RFMTC = 1u; + pstcHsSpi->RXC_f.RFLETC = 1u; + pstcHsSpi->RXC_f.RFUC = 1u; + pstcHsSpi->RXC_f.RFOC = 1u; + pstcHsSpi->RXC_f.RFEC = 1u; + pstcHsSpi->RXC_f.RFFC = 1u; + + // Clear fault interrupts. + pstcHsSpi->FAULTC_f.DWCBSFC = 1u; + pstcHsSpi->FAULTC_f.DRCBSFC = 1u; + pstcHsSpi->FAULTC_f.PVFC = 1u; + pstcHsSpi->FAULTC_f.WAFC = 1u; + pstcHsSpi->FAULTC_f.UMAFC = 1u; + + // Reset direct mode configuration register. + pstcHsSpi->DMCFG = 0u; + + // Reset direct mode DMA enable register. + pstcHsSpi->DMDMAEN = 0u; + + // Reset direct mode peripheral select register. + pstcHsSpi->DMPSEL = 0u; + + // Reset direct mode transfer protocol register. + pstcHsSpi->DMTRP = 0u; + + // Reset direct mode byte count control register. + pstcHsSpi->DMBCC = 0u; + + // Reset receive FIFO, transmit FIFO, and flush FIFOs. + pstcHsSpi->FIFOCFG_f.TXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.FWIDTH = 0u; + pstcHsSpi->FIFOCFG_f.TXFTH = 7u; + pstcHsSpi->FIFOCFG_f.RXFTH = 7u; + + // Reset command sequencer configuration register. + pstcHsSpi->CSCFG = 0u; + + // Reset command sequencer idle time register. + pstcHsSpi->CSITIME = 0x0000FFFFul; + + // Reset command sequencer address extension register. + pstcHsSpi->CSAEXT_f.AEXT = 0x00u; + + // Reset command sequence data/control register. + pstcHsSpi->RDCSDC0 = 0u; + pstcHsSpi->RDCSDC1 = 0u; + pstcHsSpi->RDCSDC2 = 0u; + pstcHsSpi->RDCSDC3 = 0u; + pstcHsSpi->RDCSDC4 = 0u; + pstcHsSpi->RDCSDC5 = 0u; + pstcHsSpi->RDCSDC6 = 0u; + pstcHsSpi->RDCSDC7 = 0u; + + pstcHsSpi->WRCSDC0 = 0u; + pstcHsSpi->WRCSDC1 = 0u; + pstcHsSpi->WRCSDC2 = 0u; + pstcHsSpi->WRCSDC3 = 0u; + pstcHsSpi->WRCSDC4 = 0u; + pstcHsSpi->WRCSDC5 = 0u; + pstcHsSpi->WRCSDC6 = 0u; + pstcHsSpi->WRCSDC7 = 0u; + + // Reset module control register. + pstcHsSpi->MCTRL = 0u; + + return Ok; +} // HsSpi_DeInit + +/** + ***************************************************************************** + ** \brief Set mode of the HS-SPI unit. + ** + ** Selects if HS-SPI unit shall be operated in Direct or Command Sequencer mode + ** and which protocol mode (legacy, dual, quad) shall be used. + ** Any transmission has to be completed before a change of HS-SPI mode is + ** possible, otherwise any ongoing transmission will be interrupted. + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register start + ** address of HS-SPI module). + ** \param [in] enMode Direct mode or command sequencer mode. + ** \param [in] enProtocolMode HS-SPI Mode (Legacy, Dual or Quad) + ** \param [in] enProtocolDirection HS-SPI protocol direction + ** + ** \retval Ok New mode was successfully set. + ** \retval ErrorInvalidParameter If following condition is met: + ** - pstcHsSpi == NULL + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +en_result_t HsSpi_SetMode(volatile stc_hsspin_t* pstcHsSpi, + en_hsspi_mode_t enMode, + en_hsspi_protocol_mode_t enProtocolMode, + en_hsspi_protocol_direction_t enProtocolDirection) +{ + stc_hsspi_intern_data_t* pstcHsSpiInternData; // Pointer to internal data + en_result_t enResult; + + // Check for NULL-Pointer + if (NULL == pstcHsSpi) + { + return ErrorInvalidParameter; + } + + // Get ptr to internal data struct ... + pstcHsSpiInternData = HsSpiGetInternDataPtr(pstcHsSpi); + // ... and check + if (NULL == pstcHsSpiInternData) + { + return ErrorInvalidParameter; + } + + enResult = HsSpi_ModuleDisable(pstcHsSpi); // Disable before any changes + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Disable transmit complete and transmit FIFO less or equal to threshold interrupt. + pstcHsSpi->TXE_f.TFLETE = 0u; + pstcHsSpi->TXE_f.TFEE = 0u; + + // Reset byte counter. + pstcHsSpi->DMBCC = 0u; + + // Flush transmit and receive FIFOs + pstcHsSpi->FIFOCFG_f.TXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + + if (enMode == HsSpiModeDirect) + { + // Update protocol mode so that transfer functions have access to it + pstcHsSpiInternData->enDirectModeProtocol = enProtocolMode; + // Just a default (will be setup by the transfer function) + + // Set bit mode + switch(enProtocolMode) + { + case HsSpiProtocolModeSingle: + pstcHsSpi->DMTRP = 0x00u; + break; + case HsSpiProtocolModeDual: + pstcHsSpi->DMTRP = 0x01u; + break; + case HsSpiProtocolModeQuad: + pstcHsSpi->DMTRP = 0x02u; + break; + default: + return ErrorInvalidParameter; + } + + // Set direction mode + switch(enProtocolDirection) + { + case HsSpiProtocolTxRx: + pstcHsSpi->DMTRP |= 0x00u; + break; + case HsSpiProtocolTx: + pstcHsSpi->DMTRP |= 0x04u; + break; + case HsSpiProtocolRx: + pstcHsSpi->DMTRP |= 0x08u; + break; + default: + return ErrorInvalidParameter; + } + + // Setup new stuff + pstcHsSpi->FIFOCFG_f.RXFTH = 7u; + pstcHsSpi->RXC_f.RFMTC = 1u; + + // Set new mode (direct). + pstcHsSpi->MCTRL_f.CSEN = 0u; + } + else + { + // Bit mode + switch(enProtocolMode) + { + case HsSpiProtocolModeSingle: + pstcHsSpi->CSCFG_f.MBM = 0x0u; + break; + case HsSpiProtocolModeDual: + pstcHsSpi->CSCFG_f.MBM = 0x1u; + break; + case HsSpiProtocolModeQuad: + pstcHsSpi->CSCFG_f.MBM = 0x2u; + break; + default: + return ErrorInvalidParameter; + } + + // Set new mode (command sequencer). + pstcHsSpi->MCTRL_f.CSEN = 1u; + } + + pstcHsSpi->MCTRL_f.SYNCON = 0u; // AHB synchronizer circuit on + + enResult = HsSpi_ModuleEnable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + return Ok; +} // HsSpi_SetMode + +/** + ***************************************************************************** + ** \brief Configures the communication parameters of an external device. + ** + ** The external device specific parameters (e.g. HS-SPI mode, LSB/MSB first, ...) + ** can be configured + ** In case of high speed SPI the slave u8DeviceNumber is also enabled for the + ** memory map in command sequencer mode. + ** (See HW-manual for more information) + ** + ** \param [in] pstcHsSpi HS-SPI module instance + ** (register start address of HS-SPI module). + ** \param [in] u8DeviceNumber Slave which is connected to corresponding + ** signals SSEL0..3 + ** \param [in] pstcConfig HS-SPI configuration parameters. + ** + ** \retval Ok External device configuration success + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcHsSpi == NULL + ** - pstcConfig == NULL + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled HS-SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + ** - u8DeviceNumber > 3 + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +en_result_t HsSpi_SetExternalDeviceConfig(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const stc_hsspi_ext_device_config_t* pstcConfig) +{ + stc_hsspi_intern_data_t* pstcHsSpiInternData; // Pointer to internal data + stc_hsspi_pcc0_field_t* pstcHsSpiPcc; // Pointer to communication configuration register + en_result_t enResult; + + // Check for NULL-Pointers + if ((NULL == pstcHsSpi) || + (NULL == pstcConfig) + ) + { + return ErrorInvalidParameter; + } + + // Get ptr to internal data struct ... + pstcHsSpiInternData = HsSpiGetInternDataPtr(pstcHsSpi); + // ... and check + if (NULL == pstcHsSpiInternData) + { + return ErrorInvalidParameter; + } + + // Check for slave number in range + if (u8DeviceNumber > 3u) + { + return ErrorInvalidParameter; + } + + enResult = HsSpi_ModuleDisable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Update command sequencer configuration register. + switch (u8DeviceNumber) + { + case 0u: + pstcHsSpiPcc = (stc_hsspi_pcc0_field_t*)&pstcHsSpi->PCC0; + break; + case 1u: + pstcHsSpiPcc = (stc_hsspi_pcc0_field_t*)&pstcHsSpi->PCC1; + break; + case 2u: + pstcHsSpiPcc = (stc_hsspi_pcc0_field_t*)&pstcHsSpi->PCC2; + break; + case 3u: + pstcHsSpiPcc = (stc_hsspi_pcc0_field_t*)&pstcHsSpi->PCC3; + break; + default: // Should never see the daylight + return ErrorInvalidParameter; + } // switch (u8DeviceNumber) + + // Update command sequencer configuration register. + switch (u8DeviceNumber) + { + case 0u: + pstcHsSpi->CSCFG_f.SSEL0EN = 1u; + break; + case 1u: + pstcHsSpi->CSCFG_f.SSEL1EN = 1u; + break; + case 2u: + pstcHsSpi->CSCFG_f.SSEL2EN = 1u; + break; + case 3u: + pstcHsSpi->CSCFG_f.SSEL3EN = 1u; + break; + default: // Should never see the daylight + return ErrorInvalidParameter; + } // switch (u8DeviceNumber) + + // Backup for later checks + pstcHsSpiInternData->enClkMode = pstcConfig->enClockMode; + + // Set peripheral communication register (PCC0 .. PCC3). + pstcHsSpiPcc->SAFESYNC = (TRUE == pstcConfig->bSafeSync) ? 1u : 0u; + pstcHsSpiPcc->CDRS = pstcConfig->enClockDivider; + pstcHsSpiPcc->SDIR = (FALSE == pstcConfig->bShiftLsbFirst) ? 0u : 1u; + pstcHsSpiPcc->SS2CD = pstcConfig->enClockDelay; + pstcHsSpiPcc->SSPOL = (FALSE == pstcConfig->bSlaveSelectPolarityHigh) ? 0u : 1u; + pstcHsSpiPcc->RTM = (TRUE == pstcConfig->bCompensatedClock) ? 1u : 0u; + pstcHsSpiPcc->ACES = ((pstcConfig->enClockMode >> 2u) & 0x01u); + pstcHsSpiPcc->CPOL = ((pstcConfig->enClockMode >> 1u) & 0x01u); + pstcHsSpiPcc->CPHA = (pstcConfig->enClockMode & 0x0u); + + // Set endianess + switch(pstcConfig->enEndianess) + { + case HsSpiBigEndian: + pstcHsSpiPcc->SENDIAN = 0u; + break; + case HsSpiLittleEndian: + pstcHsSpiPcc->SENDIAN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set read deselect time + if ((pstcConfig->u8ReadDeselectTime < 1u) || (pstcConfig->u8ReadDeselectTime > 4u)) + { + return ErrorInvalidParameter; + } + pstcHsSpiPcc->RDDSEL = pstcConfig->u8ReadDeselectTime - 1u; + + // Set write/different command deselect time + if ((pstcConfig->u8WriteDeselectTime < 1u) || (pstcConfig->u8WriteDeselectTime > 16u)) + { + return ErrorInvalidParameter; + } + pstcHsSpiPcc->WRDSEL = pstcConfig->u8WriteDeselectTime - 1u; + + enResult = HsSpi_ModuleEnable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + return Ok; +} // HsSpi_SetExternalDeviceConfig + +/** + ***************************************************************************** + ** \brief Transfers data in direct half-duplex mode. + ** + ** Note that direct mode transfer protocol is changed during operation and + ** previous mode is restored after operation has finished. + ** + ** \note This function does not work for HS-SPI clock modes 4-7 + ** + ** \note This function is restricted to HS-SPI protocol mode 'Legacy'. + ** i.e. does not support half duplex transfer in case of 'Dual' or 'Quad' mode. + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register + ** start address of (high speed) SPI module). + ** \param [in] u8DeviceNumber Slave which is connected to corresponding + ** signal SSEL0..3. + ** \param [in] pu8TxData Pointer to transmit buffer + ** \param [in] u16TxSize Number of data bytes to transmit. + ** Must be greater than 0. + ** \param [in] pu8RxData Pointer to receive buffer, can be NULL. + ** \param [in] u16RxSize Number of data bytes to receive, can be 0 + ** \param [in] bEnableTxDmaRequest Enable or disable DMA request on TX FIFO + ** interrupts (less or equal threshold level). + ** -> currently not supported + ** + ** \retval Ok Setup or transmission of data successful. + ** \retval ErrorOperationInProgress A transmission is still ongoing. + ** \retval ErrorInvalidMode HS-SPI module is in command sequencer mode. + ** or protocol mode is not "SpiProtocolModeLegacy" + ** or clock mode >= "SpiClkLowOutFallingInFalling" + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcHsSpi == NULL + ** - pu8TxData == NULL + ** - u8DeviceNumber > 3 + ** - u16TxSize == 0 + ** - u16TxSize + u16RxSize > (2^16 - 1) + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled HS-SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + *****************************************************************************/ +en_result_t HsSpi_DirectModeTransferHalfDuplex(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const uint8_t* pu8TxData, uint16_t u16TxSize, uint8_t* pu8RxData, uint16_t u16RxSize, boolean_t bEnableTxDmaRequest) +{ + stc_hsspi_linked_data_list_t stcDataList; + + stcDataList.pu8Data = pu8TxData; + stcDataList.u16ListItemDataSize = u16TxSize; + stcDataList.pstcNext = 0ul; + + return HsSpi_DirectModeTransferHalfDuplexList(pstcHsSpi, u8DeviceNumber, &stcDataList, pu8RxData, u16RxSize, bEnableTxDmaRequest); +} + +/** + ***************************************************************************** + ** \brief Transfers linked data in direct half-duplex mode. + ** + ** Note that direct mode transfer protocol is changed during operation and + ** previous mode is restored after operation has finished. + ** + ** \note This function does not work for HS-SPI clock modes 4-7 + ** + ** \note This function is restricted to HS-SPI protocol mode 'Legacy'. + ** i.e. does not support half duplex transfer in case of 'Dual' or 'Quad' mode. + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register + ** start address of (high speed) SPI module). + ** \param [in] u8DeviceNumber Slave which is connected to corresponding + ** signal SSEL0..3. + ** \param [in] pstcTxData Pointer to first item of linked transmit data list + ** The total size of transmit data must be greater than 0 + ** \param [in] pu8RxData Pointer to receive buffer, can be NULL. + ** \param [in] u16RxSize Number of data bytes to receive, can be 0 + ** \param [in] bEnableTxDmaRequest Enable or disable DMA request on TX FIFO + ** interrupts (less or equal threshold level). + ** -> currently not supported + ** + ** \retval Ok Setup or transmission of data successful. + ** \retval ErrorOperationInProgress A transmission is still ongoing. + ** \retval ErrorInvalidMode SPI module is in command sequencer mode. + ** or protocol mode is not "HsSpiProtocolModeLegacy" + ** or clock mode >= "HsSpiClkLowOutFallingInFalling" + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcHsSpi == NULL + ** - pstcTxData == NULL + ** - pstcTxData->pu8Data == NULL + ** - u8DeviceNumber > 3 + ** - total size of transmit data == 0 + ** - total size of transmit data + u16RxSize > (2^16 - 1) + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled HS-SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +extern en_result_t HsSpi_DirectModeTransferHalfDuplexList(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const stc_hsspi_linked_data_list_t* pstcTxData, uint8_t* pu8RxData, uint16_t u16RxSize, boolean_t bEnableTxDmaRequest) +{ + stc_hsspi_intern_data_t* pstcHsSpiInternData; + const stc_hsspi_linked_data_list_t* pstcListItem; + uint8_t u8TrpBackup; + uint8_t u8Index; + uint8_t u8LoopEndIndex; + uint16_t u16TransmissionLength; + uint16_t u16TxSize = 0u; + uint16_t u16RxDataCount = 0u; + uint16_t u16TxDataCount = 0u; + uint16_t u16ListItemDataCount = 0u; + en_result_t enResult; + + // Check for NULL-Pointer + if ((NULL == pstcHsSpi) || + (NULL == pstcTxData) || + (NULL == pstcTxData->pu8Data) || + (TRUE == bEnableTxDmaRequest) // Currently not supported + ) + { + return ErrorInvalidParameter; + } + + // Get ptr to internal data struct ... + pstcHsSpiInternData = HsSpiGetInternDataPtr(pstcHsSpi); + // ... and check + if (NULL == pstcHsSpiInternData) + { + return ErrorInvalidParameter; + } + + // Check for slave number in range + if (u8DeviceNumber > 3u) + { + return ErrorInvalidParameter; + } + + // Iterate through linked list to sum up total TX size + pstcListItem = pstcTxData; + do + { + u16TxSize += pstcListItem->u16ListItemDataSize; + pstcListItem = pstcListItem->pstcNext; + } while((uint32_t)pstcListItem != 0ul); + + // Check for valid transfer size + if (0u == u16TxSize) + { + return ErrorInvalidParameter; + } + + // Check for valid total transmission size + if (((uint32_t) u16TxSize + (uint32_t) u16RxSize) > 65535u) + { + return ErrorInvalidParameter; + } + + // Check if there is a pending transmission + if (pstcHsSpi->DMSTATUS_f.TXACTIVE != 0u) + { + return ErrorOperationInProgress; + } + + // Check if we're in direct mode. + if (pstcHsSpi->MCTRL_f.CSEN != 0u) + { + return ErrorInvalidMode; + } + + // Check for SPI modes which may be used in faked half-duplex mode + if ((pstcHsSpiInternData->enClkMode) >= HsSpiClkLowOutFallingInFalling) + { + // Modes >= SPI Mode 4 are not supported in full duplex mode (see hardware manual) which is + // used for faking half duplex mode. Legacy mode must be used too, because switching from + // TX-only to RX-only inside a transmission is not recommended (see hardware manual) + return ErrorInvalidMode; + } + + // Store receive buffer pointer + pstcHsSpiInternData->pu8RXBuffer = pu8RxData; + + // Select current device for transmission. + pstcHsSpi->DMPSEL = u8DeviceNumber; + + // Backup current protocol mode + u8TrpBackup = pstcHsSpi->DMTRP; + + enResult = HsSpi_ModuleDisable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // We are faking a half duplex mode for the upper layer by ignoring and not storing the unwanted data. + // Setting to SpiDirectModeTxRxLegacyMode + pstcHsSpi->DMTRP = HSSPI_DIRECT_MODE_TX_RX_SINGLE_MODE; + + enResult = HsSpi_ModuleEnable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Flush transmit and receive FIFOs + pstcHsSpi->FIFOCFG_f.TXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + + // In half-duplex mode the number of bytes in this transaction is the sum of TX and RX + u16TransmissionLength = u16TxSize + u16RxSize; + pstcHsSpi->DMBCC = u16TransmissionLength; + + // Preset current list item with the first list item + pstcListItem = pstcTxData; + + // Trigger start of transfer. + pstcHsSpi->DMSTART_f.START = 1u; + + // Loop until whole transmission has finished + while(u16TxDataCount < u16TransmissionLength) + { + // Put max FIFO size or remaining bytes of transmission (whichever is less) in TX FIFO + u8LoopEndIndex = MIN(HS_SPI_MAX_FIFO_DEPTH, (u16TransmissionLength - u16TxDataCount)); + for (u8Index = 0u; u8Index < u8LoopEndIndex; u8Index++) + { + // Put actual transmit data in FIFO or just dummy data for second part (=receive part) of half duplex transaction + *((uint8_t*)&pstcHsSpi->TXFIFO0) = (u16TxDataCount < u16TxSize) ? (uint8_t)pstcListItem->pu8Data[u16ListItemDataCount] : 0u; + + u16TxDataCount++; + // Pointer will be 0 when RX phase has been reached + if((uint32_t)pstcListItem != 0ul) + { + u16ListItemDataCount++; + // Set next list item (or 0) as new current list item when + // all data of the current list item has been transmitted + if(u16ListItemDataCount >= pstcListItem->u16ListItemDataSize) + { + pstcListItem = pstcListItem->pstcNext; + u16ListItemDataCount = 0u; + } + } + } + + // Clear "transmit FIFO & shift register" empty flag. + pstcHsSpi->TXC_f.TFEC = 1u; + + // Wait until transfer is finished (no more data in FIFO and shift register empty) + while ((pstcHsSpi->DMSTATUS_f.TXFLEVEL > 0u) || + (pstcHsSpi->TXF_f.TFES == 0u) + ) + { + PDL_WAIT_LOOP_HOOK(); + } + + // At the end of transaction (indicated by DMBCS) waiting here is necessary to ensure + // that the last item has been pushed from the shift register to the FIFO (especially at slow SPI clock) + if(0u == pstcHsSpi->DMBCS) + { + while (1u == pstcHsSpi->DMSTATUS_f.RXACTIVE) + { + PDL_WAIT_LOOP_HOOK() ; + } + } + + // Check if receive data has been requested + if ((pu8RxData != NULL) && (u16RxSize > 0u)) + { + // Data from FIFO is stored in user buffer if RX phase has been reached + while (pstcHsSpi->DMSTATUS_f.RXFLEVEL > 0u) + { + if(u16RxDataCount >= u16TxSize) + { + pu8RxData[u16RxDataCount - u16TxSize] = *((uint8_t*)&pstcHsSpi->RXFIFO0); + } + else + { + (void)(*((uint8_t*)&pstcHsSpi->RXFIFO0)); // empty FIFO + } + u16RxDataCount++; + } + } + else + { + // Flush receive FIFO in case no receive data has been requested + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + } + } + + enResult = HsSpi_ModuleDisable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Restore protocol mode + pstcHsSpi->DMTRP = u8TrpBackup; + + enResult = HsSpi_ModuleEnable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + return Ok; +} // HsSpi_DirectModeTransferHalfDuplexList + +/** + ***************************************************************************** + ** \brief Set read command sequence for command sequencer mode. + ** + ** Every command sequence is either 8 commands long, or has to be finished + ** with command #HsSpiCmdEndOfList. To find out if a 8 commands long sequence + ** is valid or not, the 9th command (which will not be transferred) must be + ** a #HsSpiCmdEndOfList command. The new sequence will be set after internally + ** disabling the HS-SPI module. After update, the SPI module is enabled + ** again. + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register start address of high speed SPI module). + ** \param [in] pstcCmdSequence Pointer to command sequence list (maximum + ** 9 entries, last entry must be SpiCmdEndOfList). + ** + ** \retval Ok Read command sequence successfully set. + ** \retval ErrorInvalidMode HS-SPI module is in direct mode. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCmdSequence == NULL + ** - SpiCmdEndOfList command missing in pstcCmdSequence + ** - pstcHsSpi == NULL + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +en_result_t HsSpi_SetReadCommandSequence(volatile stc_hsspin_t* pstcHsSpi, const stc_hsspi_command_sequencer_control_t* pstcCmdSequence) +{ + uint8_t u8Index; + uint16_t u16Data; + boolean_t bEndOfListFound; + volatile uint16_t* pu16HsSpiRdcsdc; + en_result_t enResult; + + // Check for NULL-Pointer + if ((NULL == pstcHsSpi) || + (NULL == pstcCmdSequence) + ) + { + return ErrorInvalidParameter; + } + + // Check if direct mode is configured + if (0u == pstcHsSpi->MCTRL_f.CSEN) + { + return ErrorInvalidMode; + } + + bEndOfListFound = FALSE; // Preset to FALSE + + // Loop over all possible entries and check for a valid terminator + for (u8Index = 0u; u8Index < 9u; u8Index++) + { + if (HsSpiCmdEndOfList == (pstcCmdSequence + u8Index)->enCommand) + { + bEndOfListFound = TRUE; + break; + } + } + + // If no end-of-list terminator found + if (FALSE == bEndOfListFound) + { + return ErrorInvalidParameter; + } + + // Note that there are more limitations regarding the command + // sequence which are not checked here. Refer to the Hardware Manual! + + enResult = HsSpi_ModuleDisable(pstcHsSpi); // Disable module before changes are made + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Set configuration register. + pu16HsSpiRdcsdc = &pstcHsSpi->RDCSDC0; + + // Loop over all possible "real" commands + for(u8Index = 0u; u8Index < 8u; u8Index++) + { + switch ((pstcCmdSequence + u8Index)->enCommand) + { + case HsSpiCmdTransmitData: + u16Data = ((pstcCmdSequence + u8Index)->u8Data << 8u); + break; + + case HsSpiCmdTransmitHighZStateNibble: + u16Data = (pstcCmdSequence + u8Index)->u8Data; + u16Data &= 0xF0u; // Only higher nibble used + u16Data |= 0x05u; // Control High-Z nibble + u16Data <<= 8u; // Make it the high byte + u16Data |= 1u; // Set DECode bit + break; + + case HsSpiCmdTransmitHighZStateByte: + u16Data = 0x04u; // Control High-Z Byte + u16Data <<= 8u; // Make it the high byte + u16Data |= 1u; // Set DECode bit + break; + + default: + u16Data = ((pstcCmdSequence + u8Index)->enCommand << 8u); + u16Data |= 1u; // Set DECode bit + } + + // Transfer protocol + switch ((pstcCmdSequence + u8Index)->enTransferProtocol) + { + case HsSpiSerialIf: + u16Data &= 0xFFF9u; // TRP[1:0] = 2b00 + break; + case HsSpiDualBitMode: + u16Data &= 0xFFF9u; + u16Data |= 0x0002u; // TRP[1:0] = 2b01 + break; + case HsSpiQuadBitMode: + u16Data &= 0xFFF9u; + u16Data |= 0x0004u; // TRP[1:0] = 2b10 + break; + case HsSpiSingleBitMode: + u16Data |= 0x0006u; // TRP[1:0] = 2b11 + break; + default: + return ErrorInvalidParameter; + } + + if (TRUE == ((pstcCmdSequence + u8Index)->bCont)) + { + u16Data |= 0x0008u; + } + else + { + u16Data &= 0xFFF7u; + } + + // Write data and/or command + pu16HsSpiRdcsdc[u8Index] = u16Data; + + // Stop, if end of list is reached + if (HsSpiCmdEndOfList == (pstcCmdSequence + u8Index)->enCommand) + { + break; + } + } // for(u8Index = 0u; u8Index < 8u; u8Index++) + + enResult = HsSpi_ModuleEnable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + return Ok; +} // HsSpi_SetReadCommandSequence + +/** + ***************************************************************************** + ** \brief Set write command sequence for command sequencer mode. + ** + ** Every command sequence is either 8 commands long, or has to be finished + ** with command #HsSpiCmdEndOfList. To find out if a 8 commands long sequence + ** is valid or not, the 9th command (which will not be transferred) must be + ** a #HsSpiCmdEndOfList command. The new sequence will be set after internally + ** disabling the SPI module. After update, the SPI module is enabled + ** again. + ** + ** \param [in] pstcHsSpi HS-SPI module instance (register start address of HS-SPI module). + ** \param [in] pstcCmdSequence Pointer to command sequence list (maximum + ** 9 entries, last entry must be SpiCmdEndOfList). + ** + ** \retval Ok Write command sequence successfully set. + ** \retval ErrorInvalidMode SPI module is in direct mode. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcHsSpi == NULL + ** - pstcCmdSequence == NULL + ** - SpiCmdEndOfList command missing in pstcCmdSequence + ** \retval Error If HsSpi disable/enable failed + *****************************************************************************/ +en_result_t HsSpi_SetWriteCommandSequence(volatile stc_hsspin_t* pstcHsSpi, const stc_hsspi_command_sequencer_control_t* pstcCmdSequence) +{ + uint8_t u8Index; + uint16_t u16Data; + boolean_t bEndOfListFound; + volatile uint16_t* pu16HsSpiWrcsdc; + en_result_t enResult; + + // Check for NULL-Pointer + if ((NULL == pstcHsSpi) || + (NULL == pstcCmdSequence) + ) + { + return ErrorInvalidParameter; + } + + // Check if direct mode is configured + if (0u == pstcHsSpi->MCTRL_f.CSEN) + { + return ErrorInvalidMode; + } + + bEndOfListFound = FALSE; // Preset to FALSE + + // Loop over all possible entries and check for a valid terminator + for (u8Index = 0u; u8Index < 9u; u8Index++) + { + if (HsSpiCmdEndOfList == (pstcCmdSequence + u8Index)->enCommand) + { + bEndOfListFound = TRUE; + break; + } + } + + // If no end-of-list terminator found + if (FALSE == bEndOfListFound) + { + return ErrorInvalidParameter; + } + + // Note that there are more limitations regarding the command + // sequence which are not checked here. Refer to the Hardware Manual! + + enResult = HsSpi_ModuleDisable(pstcHsSpi); // Disable module before changes are made + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + // Set configuration register. + pu16HsSpiWrcsdc = &pstcHsSpi->WRCSDC0; + + // Loop over all possible "real" commands + for(u8Index = 0u; u8Index < 8u; u8Index++) + { + switch ((pstcCmdSequence + u8Index)->enCommand) + { + case HsSpiCmdTransmitData: + u16Data = ((pstcCmdSequence + u8Index)->u8Data << 8u); + break; + + case HsSpiCmdTransmitHighZStateNibble: + u16Data = (pstcCmdSequence + u8Index)->u8Data; + u16Data &= 0xF0u; // Only higher nibble used + u16Data |= 0x05u; // Control High_z nibble + u16Data <<= 8u; // Make it the high byte + u16Data |= 1u; // Set DECode bit + break; + + case HsSpiCmdTransmitHighZStateByte: + u16Data = 0x04u; // Control High-Z Byte + u16Data <<= 8u; // Make it the high byte + u16Data |= 1u; // Set DECode bit + break; + + default: + u16Data = ((pstcCmdSequence + u8Index)->enCommand << 8u); + u16Data |= 1u; // Set DECode bit + } + + // Transfer protocol + switch ((pstcCmdSequence + u8Index)->enTransferProtocol) + { + case HsSpiSerialIf: + u16Data &= 0xFFF9u; // TRP[1:0] = 2b00 + break; + case HsSpiDualBitMode: + u16Data &= 0xFFF9u; + u16Data |= 0x0002u; // TRP[1:0] = 2b01 + break; + case HsSpiQuadBitMode: + u16Data &= 0xFFF9u; + u16Data |= 0x0004u; // TRP[1:0] = 2b10 + break; + case HsSpiSingleBitMode: + u16Data |= 0x0006u; // TRP[1:0] = 2b11 + break; + default: + return ErrorInvalidParameter; + } + + if (TRUE == ((pstcCmdSequence + u8Index)->bCont)) + { + u16Data |= 0x0008u; + } + else + { + u16Data &= 0xFFF7u; + } + + // Write data and/or command + pu16HsSpiWrcsdc[u8Index] = u16Data; + + // Stop, if end of list is reached + if((pstcCmdSequence + u8Index)->enCommand == HsSpiCmdEndOfList) + { + break; + } + } // for(u8Index = 0u; u8Index < 8u; u8Index++) + + enResult = HsSpi_ModuleEnable(pstcHsSpi); + //.... Check if operation timed out + if(Ok != enResult) + { + return Error; + } + + return Ok; +} // HsSpi_SetWriteCommandSequence + +/** + ***************************************************************************** + ** \brief Starts transfer in legacy mode and then switches to quad mode + ** + ** Some HS-SPI devices may require an access sequence where the first part of + ** a command is transmitted in legacy mode and afterwards further parameters + ** or the response from the device are transmitted in quad mode. + ** This function allows to execute such an SPI transaction. + ** + ** Note that direct mode transfer protocol is changed during operation and + ** previous mode is restored after operation has finished. + ** + ** \param [in] pstcHsSpi HS-SPI module instance + ** (register start address of high speed SPI module). + ** \param [in] u8DeviceNumber Slave which is connected to corresponding + ** SSEL0..3 line + ** \param [in] pu8LegacyData Pointer to transmit buffer for legacy mode + ** \param [in] u8LegacyTxSize Number of data bytes to transmit in legacy mode + ** \param [in] pu8TxData Pointer to transmit buffer for quad mode, can be NULL. + ** \param [in] u8TxSize Number of data bytes to transmit in quad mode + ** Valid range from 0 to HS_SPI_MAX_FIFO_DEPTH. + ** \param [in] pu8RxData Pointer to receive buffer for quad mode, can be NULL. + ** \param [in] u8RxSize Number of data bytes to receive in quad mode. + ** Valid range from 0 to HS_SPI_MAX_FIFO_DEPTH. + ** + ** \retval Ok Setup or transmission of data successful. + ** \retval ErrorOperationInProgress u8TxSize > 0 and a transmission is still ongoing. + ** \retval ErrorInvalidMode SPI module is in command sequencer mode. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcHsSpi == NULL + ** - pu8TxData == NULL + ** - u8DeviceNumber > 3 + ** - u8TxSize == 0 + ** - u8RxSize > HS_SPI_MAX_FIFO_DEPTH + ** - u8RxSize > 0 && pu8RxData == NULL + ** - u8LegacyTxSize > 0 && pu8LegacyData == NULL + ** - pstcHsSpiInternData == NULL + ** (invalid or disabled HS-SPI unit (PDL_PERIPHERAL_ENABLE_HSSPIn)) + *****************************************************************************/ +en_result_t HsSpi_MultiModeTransfer(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const uint8_t* pu8LegacyData, uint8_t u8LegacyTxSize, const uint8_t* pu8TxData, uint8_t u8TxSize, uint8_t* pu8RxData, uint8_t u8RxSize) +{ + stc_hsspi_intern_data_t* pstcHsSpiInternData; + uint8_t u8Index; + uint8_t u8TrpBackup; + + // Check for NULL-Pointer + if ((NULL == pstcHsSpi) || + (NULL == pu8TxData) + ) + { + return ErrorInvalidParameter; + } + + // Get ptr to internal data struct ... + pstcHsSpiInternData = HsSpiGetInternDataPtr(pstcHsSpi); + // ... and check + if (NULL == pstcHsSpiInternData) + { + return ErrorInvalidParameter; + } + + // Check for slave number in range + if (u8DeviceNumber > 3u) + { + return ErrorInvalidParameter; + } + + // Check for legacy data pointer + if ((u8LegacyTxSize > 0u) && + (NULL == pu8LegacyData) + ) + { + return ErrorInvalidParameter; + } + + // Check for valid quad transfer size + if ((0u == u8TxSize) || + (u8TxSize > HS_SPI_MAX_FIFO_DEPTH) + ) + { + return ErrorInvalidParameter; + } + + // Check for valid quad receive size + if (u8RxSize > HS_SPI_MAX_FIFO_DEPTH) + { + return ErrorInvalidParameter; + } + + // Check if there are is a pending transmission + if (pstcHsSpi->DMSTATUS_f.TXACTIVE != 0u) + { + return ErrorOperationInProgress; + } + + // Backup current protocol mode + u8TrpBackup = pstcHsSpi->DMTRP; + + // Store receive buffer pointer + pstcHsSpiInternData->pu8RXBuffer = pu8RxData; + + // Flush transmit and receive FIFOs + pstcHsSpi->FIFOCFG_f.TXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + + // Select current device for transmission. + pstcHsSpi->DMPSEL_f.PSEL = u8DeviceNumber; + + // In half-duplex mode the number of bytes in this transaction is the sum of TX and RX + pstcHsSpi->DMBCC = (uint16_t)(u8LegacyTxSize + u8TxSize + u8RxSize); + + // Trigger start of transfer. + pstcHsSpi->DMSTART = 1u; + + if (u8LegacyTxSize > 0u) + { + // Set Transfer Protocol to direct mode TX only + pstcHsSpi->DMTRP = HSSPI_DIRECT_MODE_TX_ONLY_SINGLE_MODE; + + // Fill Fifo with data which must be send in legacy mode + for (u8Index = 0u; u8Index < u8LegacyTxSize; u8Index++) + { + *((uint8_t*)(&pstcHsSpi->TXFIFO0)) = (uint8_t)pu8LegacyData[u8Index]; + } + + // Clear "transmit FIFO & shift register" empty flag. + pstcHsSpi->TXC_f.TFEC = 1u; + + // Now wait until all data in legacy mode is sent (no more data in FIFO and shift register empty) + while ((pstcHsSpi->DMSTATUS_f.TXFLEVEL > 0u) || + (pstcHsSpi->TXF_f.TFES != 1u) + ) + { + PDL_WAIT_LOOP_HOOK(); + } + } + + if(u8RxSize != 0) + { + // Use this ONLY in Dual/Quad I/O modes. Comment this line for other modes. + // Set Transfer Protocol to quad mode TX for Fast Read QUAD I/O OPN + pstcHsSpi->DMTRP = HSSPI_DIRECT_MODE_TX_ONLY_QUAD_MODE; + } + + // Flush transmit and receive FIFOs + pstcHsSpi->FIFOCFG_f.TXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + + // Fill FIFO with new data + for (u8Index = 0u; u8Index < u8TxSize; u8Index++) + { + *((uint8_t*)(&pstcHsSpi->TXFIFO0)) = (uint8_t)pu8TxData[u8Index]; + } + + // Clear "transmit FIFO & shift register" empty flag. + pstcHsSpi->TXC_f.TFEC = 1u; + + // Wait until quad transfer is finished (no more data in FIFO and shift register empty) + while ((pstcHsSpi->DMSTATUS_f.TXFLEVEL > 0u) || + (pstcHsSpi->TXF_f.TFES != 1u) + ) + { + PDL_WAIT_LOOP_HOOK(); + } + + // If no receive data is requested function can return here + if ((NULL == pu8RxData) || + (0u == u8RxSize) + ) + { + // Wait unit all data went out before restoring mode + while (pstcHsSpi->DMSTATUS_f.TXACTIVE != 0u) + { + PDL_WAIT_LOOP_HOOK(); + } + + // Restore previous mode + pstcHsSpi->DMTRP = u8TrpBackup; + return Ok; + } + + // Flush transmit and receive FIFOs + pstcHsSpi->FIFOCFG_f.TXFLSH = 1u; + pstcHsSpi->FIFOCFG_f.RXFLSH = 1u; + + // Set Transfer Protocol to quad mode RX only + pstcHsSpi->DMTRP = HSSPI_DIRECT_MODE_RX_ONLY_QUAD_MODE; + + // By switching to RX only mode the SPI automatically outputs the + // required clocks for the remaining byte count (SPIn_DMBCS) + + // Initialise receive buffer index + u8Index = 0u; + // Read from the RX FIFO, the FIFO will only contain the number + // of requested data, hence u8Index does not need to be checked + while ((1u == pstcHsSpi->DMSTATUS_f.RXACTIVE) || + (pstcHsSpi->DMSTATUS_f.RXFLEVEL > 0u) + ) + { + if (pstcHsSpi->DMSTATUS_f.RXFLEVEL > 0u) + { + pu8RxData[u8Index] = *((uint8_t*)(&pstcHsSpi->RXFIFO0)); + u8Index++; + } + } + + // Restore previous mode + pstcHsSpi->DMTRP = u8TrpBackup; + + return Ok; +} // HsSpi_MultiModeTransfer + +#endif //#if (defined(PDL_PERIPHERAL_HSSPI_ACTIVE)) + +/*****************************************************************************/ +/* EOF (not truncated) */ +/*****************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hsspi/hsspi.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hsspi/hsspi.h new file mode 100644 index 0000000000..61f375bb97 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/hsspi/hsspi.h @@ -0,0 +1,805 @@ +/****************************************************************************** +* \file hsspi.h +* +* \version 1.20 +* +* \brief Headerfile for High Speed Quad Serial Peripheral Interface functions +* +******************************************************************************* +\copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************//*****************************************************************************/ + + +#ifndef __HSSPI_H__ +#define __HSSPI_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_HSSPI_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupHSSPI High Speed Quad Serial Peripheral Interface (HSSPI) +* \{ +* \defgroup GroupHSSPI_Macros Macros +* \defgroup GroupHSSPI_Functions Functions +* \defgroup GroupHSSPI_GlobalVariables Global Variables +* \defgroup GroupHSSPI_Types Enumerated Types +* \defgroup GroupHSSPI_DataStructures Data Structures +* \} +*/ +/** +* \addtogroup GroupHSSPI +* \{ +* The High-speed Quad Serial Peripheral Interface (HSSPI) peripheral implements +* Quad-SPI for increased performance with Flash memory. HSSPI is available on +* certain devices in the FM4 portfolio. See the datasheet for your device to +* determine whether it supports HSSPI.
+* HSSPI supports two operating modes: direct mode and command sequencer mode. +* It supports the direct master mode for setting up the external device and +* command sequencer mode to read/write to memory devices attached to a HSSPI +* peripheral. Note that the command sequencer mode is not compatible with all +* SPI devices. Refer to the datasheet provided with the product you are using to +* determine whether your device is compatible with this mode.
+* The HSSPI controller has these features: +* * Compatible with single bit, dual bit and quad bit +* * Compatible with up to four slave devices +* * Can set format of serial interface for each slave (direct mode only) +* * Supports four clocking modes +* * Supports DMA transfer
+* This driver covers functionality for all HSSPI modules including the command sequencer mode.
+* Direct slave mode is not supported. +* +* \section SectionHSSPI_ConfigurationConsideration Configuration Consideration +* To set up communication with an HSSPI device, you go through several steps.
+* First, specify the configuration options in the stc_hsspi_config_t structure, +* and call HsSpi_Init().
+* Then set the operating mode. Call HsSpi_SetMode() to change operating modes and +* set the mode protocol.
+* Next, specify the configuration for the external device in the +* stc_hsspi_ext_device_config_t structure and call HsSpi_SetExternalDeviceConfig(). +* You do this for each external device (up to four). +* +* \section SectionHSSPI_MoreInfo More Information +* For more information on the HSSPI peripheral, refer to:
+* FM4 Peripheral Manual Communication Subsystem
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupHSSPI_Macros +* \{ +*/ +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/*****************************************************************************/ +#define stc_hsspin_t FM_HSSPI_TypeDef +#define HSSPI0 (*((volatile stc_hsspin_t *) FM_HSSPI_BASE)) + +#define HS_SPI_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_HSSPI0 == PDL_ON) + +/// Default clock divider (will set 20MHz @ 160MHz main clock) +#define HS_SPI_DEFAULT_CLK_DIV HsSpiClkDividerDiv8 + +/// Default SPI mode +#define HS_SPI_DEFAULT_MODE HsSpiClkHighOutFallingInRising // Mode 3 + +/// Default SPI protocol mode +#define HS_SPI_DEFAULT_PROTOCOL_MODE HsSpiProtocolModeLegacy + +/** \} GroupHSSPI_Macros */ + +/** +* \addtogroup GroupHSSPI_Types +* \{ +*/ +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + +/** +****************************************************************************** +** \brief High speed SPI reception status. +** +** Status value used either in SpiRxStatus callback function or in +** HsSpi_GetDirectModeRxStatus() function (for direct mode polling operation). +******************************************************************************/ +typedef enum en_hsspi_rx_status +{ + HsSpiRxFinished = 0u, ///< Receive FIFO and shift register is empty. + HsSpiRxFifoLow = 1u, ///< Receive FIFO fill level is less or equal to threshold. + HsSpiRxNoStatusAvailable = 2u ///< SPI instance is not valid, mode is set to command sequencer or + ///< reception is ongoing and FIFO level is higher than threshold. +} en_hsspi_rx_status_t; + +/** +****************************************************************************** +** \brief High speed SPI transmission status. +** +** Status value used either in SpiTxStatus callback function or in +** HsSpi_GetDirectModeTxStatus() function (for direct mode polling operation). +******************************************************************************/ +typedef enum en_hsspi_tx_status +{ + HsSpiModeError = -1, ///< Illegal mode or parameter error + HsSpiTxFinished = 0u, ///< Transmit FIFO and shift register is empty. + HsSpiTxFifoLow = 1u, ///< Transmit FIFO fill level is less or equal to threshold. + HsSpiTxNoStatusAvailable = 2u ///< SPI instance is not valid, mode is set to command sequencer or + ///< transmission is ongoing and FIFO level is higher than threshold. +} en_hsspi_tx_status_t; + +/** +****************************************************************************** +** \brief High speed SPI FIFO width +** +** Width of FIFO. Depending on the configured width, the usable size of the +** shift register in the SPI core also changes. +******************************************************************************/ +typedef enum en_hsspi_fifo_width +{ + HsSpiFifoWidth8 = 0u, ///< 8-bit FiFo width + HsSpiFifoWidth16 = 1u, ///< 16-bit FiFo width + HsSpiFifoWidth24 = 2u, ///< 24-bit FiFo width + HsSpiFifoWidth32 = 3u ///< 32-bit FiFo width +} en_hsspi_fifo_width_t; + +/** +******************************************************************************* +** \brief High speed SPI error types. +** +** These error codes will be returned by HsSpi_HandleError() function. +******************************************************************************/ +typedef enum en_hsspi_error +{ + HsSpiErrorNo = 0u, ///< No error indicated. + HsSpiErrorUnmappedMemoryAccessFault = 1u, ///< An unmapped memory access fault has occurred. + HsSpiErrorWriteAccessFault = 2u, ///< Write access fault has occurred (is used in command sequencer mode). + HsSpiErrorProtectionViolation = 3u, ///< PPU protection violation has occurred. + HsSpiErrorDmaWrChBlockSize = 4u, ///< DMA Write Channel Block Size Fault has occurred. + HsSpiErrorDmaRdChBlockSize = 5u ///< DMA Read Channel Block Size Fault has occurred. +} en_hsspi_error_t; + +/** +******************************************************************************* +** \brief High speed SPI receive callback function. +******************************************************************************/ +///< Prototype for transmit status callback function +typedef void (*hsspi_rx_func_ptr_t)(en_hsspi_rx_status_t enRxStatus); + +/** +******************************************************************************* +** \brief High speed SPI transmit callback function. +******************************************************************************/ +///< Prototype for transmit status callback function +typedef void (*hsspi_tx_func_ptr_t)(en_hsspi_tx_status_t enTxStatus); + +/** +******************************************************************************* +** \brief High speed SPI clock selection. +** +** The internal clock divider can divide either the AHB clock (i.e. HCLK) +** or the peripheral clock (i.e. PCLKn). +******************************************************************************/ +typedef enum en_hsspi_clk_selection +{ + HsSpiClockAhb = 0u, ///< Clock divider uses AHB clock. + HsSpiClockPeripheral = 1u ///< Clock divider uses peripheral clock. +} en_hsspi_clk_selection_t; + +/** +******************************************************************************* +** \brief High speed SPI bank size. +** +** This enum indicates the range of the AHB address space associated +** with each slave select line. It also indicates the size of each memory +** banks in the selected device. +******************************************************************************/ +typedef enum en_hsspi_bank_size +{ + HsSpiBankSize8kB = 0x0u, ///< 8 kB + HsSpiBankSize16kB = 0x1u, ///< 16 kB + HsSpiBankSize32kB = 0x2u, ///< 32 kB + HsSpiBankSize64kB = 0x3u, ///< 64 kB + HsSpiBankSize128kB = 0x4u, ///< 128 kB + HsSpiBankSize256kB = 0x5u, ///< 256 kB + HsSpiBankSize512kB = 0x6u, ///< 512 kB + HsSpiBankSize1MB = 0x7u, ///< 1 MB + HsSpiBankSize2MB = 0x8u, ///< 2 MB + HsSpiBankSize4MB = 0x9u, ///< 4 MB + HsSpiBankSize8MB = 0xAu, ///< 8 MB + HsSpiBankSize16MB = 0xBu, ///< 16 MB + HsSpiBankSize32MB = 0xCu, ///< 32 MB + HsSpiBankSize64MB = 0xDu, ///< 64 MB + HsSpiBankSize128MB = 0xEu, ///< 128 MB + HsSpiBankSize256MB = 0xFu ///< 256 MB +} en_hsspi_bank_size_t; + +/** +******************************************************************************* +** \brief High speed SPI command sequencer control. +** +** This enum is used to configure the phases of the serial transaction +** generated by the command sequencer for memory read or write operations. +******************************************************************************/ +typedef enum en_hsspi_command_sequencer_control +{ + HsSpiCmdTransmitAddress07To00 = 0u, ///< Transmit address bits 7:0 of serial memory address, DEC = 1 + HsSpiCmdTransmitAddress08To15 = 1u, ///< Transmit address bits 15:8 of serial memory address, DEC = 1 + HsSpiCmdTransmitAddress16To23 = 2u, ///< Transmit address bits 23:16 of serial memory address, DEC = 1 + HsSpiCmdTransmitAddress24To31 = 3u, ///< Transmit address bits 31:24 of serial memory address, DEC = 1 + HsSpiCmdTransmitHighZStateByte = 4u, ///< High-Z byte, output signals are tri-stated for 1 byte time, DEC = 1 + HsSpiCmdTransmitHighZStateNibble = 5u, ///< High-Z nibble, output signals are tri-stated for 1 + ///< nibble time after 4 bits of the transmit data have been sent,DEC = 1 + HsSpiCmdTransmitData = 6u, ///< Data "as it is", no decoding, DEC = 0 + HsSpiCmdEndOfList = 7u ///< End of list, DEC = 1 +} en_hsspi_command_sequencer_control_t; + +/** +******************************************************************************* +** \brief High speed SPI clock mode. +** +** The API must use the enum with the attributes that match the communication +** attributes of the serial peripheral that is to be interfaced on the +** corresponding slave select line. +******************************************************************************/ +typedef enum en_hsspi_clk_mode +{ + HsSpiClkLowOutFallingInRising = 0u, ///< Serial clock low during idle, data output set with falling clock edge, data input sampling with rising clock edge. + HsSpiClkLowOutRisingInFalling = 1u, ///< Serial clock low during idle, data output set with rising clock edge, data input sampling with falling clock edge. + HsSpiClkHighOutRisingInFalling = 2u, ///< Serial clock high during idle, data output set with rising clock edge, data input sampling with falling clock edge. + HsSpiClkHighOutFallingInRising = 3u, ///< Serial clock high during idle, data output set with falling clock edge, data input sampling with rising clock edge. + HsSpiClkLowOutFallingInFalling = 4u, ///< Serial clock low during idle, data output set with falling clock edge, data input sampling with falling clock edge. + HsSpiClkLowOutRisingInRising = 5u, ///< Serial clock low during idle, data output set with rising clock edge, data input sampling with rising clock edge. + HsSpiClkHighOutRisingInRising = 6u, ///< Serial clock high during idle, data output set with rising clock edge, data input sampling with rising clock edge. + HsSpiClkHighOutFallingInFalling = 7u ///< Serial clock high during idle, data output set with falling clock edge, data input sampling with falling clock edge. +} en_hsspi_clk_mode_t; + +/** +******************************************************************************* +** \brief SPI transfer mode (used for Command Sequencer and Direct mode) +** +** Selects transfer protocol mode. The direct mode is active +** after call of HsSpi_Init, and can be changed by function HsSpi_SetMode(). +** RxTx-,RxOnly- and TxOnly modes will be selected automatically by the transfer +** functions. +******************************************************************************/ +typedef enum en_hsspi_protocol_mode +{ + HsSpiProtocolModeSingle = 0u, ///< Single mode + HsSpiProtocolModeDual = 1u, ///< Dual mode, can only be used with the half-duplex functions + HsSpiProtocolModeQuad = 2u ///< Quad mode, can only be used with the half-duplex functions +} en_hsspi_protocol_mode_t; + +/** +******************************************************************************* +** \brief SPI transfer direction +******************************************************************************/ +typedef enum en_hsspi_protocol_direction +{ + HsSpiProtocolTxRx = 0u, ///< TX and RX direction + HsSpiProtocolTx = 1u, ///< TX direction only + HsSpiProtocolRx = 2u ///< RX direction only +} en_hsspi_protocol_direction_t; + +/** +******************************************************************************* +** \brief High speed SPI memory type. +** +** Serial SRAM or Serial Flash Memory Type Select (SRAM) +** This bit should only be set if serial SRAM devices are memory mapped through +** (HS)SPI. +******************************************************************************/ +typedef enum en_hsspi_memory_type +{ + HsSpiFlash = 0u, ///< Serial Flash memory devices are connected. Writes are disabled. + HsSpiSram = 1u ///< Serial SRAM memory devices are connected. Writes are enabled. +} en_hsspi_memory_type_t; + +/** +******************************************************************************* +** \brief High Speed SPI clock divider. +** +** This field decides the clock division ratio of the internal clock divider. +******************************************************************************/ +typedef enum en_hsspi_clk_divider +{ + HsSpiClkDividerDiv1 = 0u, ///< Clock divider is 1 + HsSpiClkDividerDiv2 = 1u, ///< Clock divider is 2 + HsSpiClkDividerDiv3 = 2u, ///< Clock divider is 3 + HsSpiClkDividerDiv4 = 3u, ///< Clock divider is 4 + HsSpiClkDividerDiv5 = 4u, ///< Clock divider is 5 + HsSpiClkDividerDiv6 = 5u, ///< Clock divider is 6 + HsSpiClkDividerDiv7 = 6u, ///< Clock divider is 7 + HsSpiClkDividerDiv8 = 7u, ///< Clock divider is 8 + HsSpiClkDividerDiv9 = 8u, ///< Clock divider is 9 + HsSpiClkDividerDiv10 = 9u, ///< Clock divider is 10 + HsSpiClkDividerDiv11 = 10u, ///< Clock divider is 11 + HsSpiClkDividerDiv12 = 11u, ///< Clock divider is 12 + HsSpiClkDividerDiv13 = 12u, ///< Clock divider is 13 + HsSpiClkDividerDiv14 = 13u, ///< Clock divider is 14 + HsSpiClkDividerDiv15 = 14u, ///< Clock divider is 15 + HsSpiClkDividerDiv16 = 15u, ///< Clock divider is 16 + HsSpiClkDividerDiv17 = 16u, ///< Clock divider is 17 + HsSpiClkDividerDiv18 = 17u, ///< Clock divider is 18 + HsSpiClkDividerDiv19 = 18u, ///< Clock divider is 19 + HsSpiClkDividerDiv20 = 19u, ///< Clock divider is 20 + HsSpiClkDividerDiv21 = 20u, ///< Clock divider is 21 + HsSpiClkDividerDiv22 = 21u, ///< Clock divider is 22 + HsSpiClkDividerDiv23 = 22u, ///< Clock divider is 23 + HsSpiClkDividerDiv24 = 23u, ///< Clock divider is 24 + HsSpiClkDividerDiv25 = 24u, ///< Clock divider is 25 + HsSpiClkDividerDiv26 = 25u, ///< Clock divider is 26 + HsSpiClkDividerDiv27 = 26u, ///< Clock divider is 27 + HsSpiClkDividerDiv28 = 27u, ///< Clock divider is 28 + HsSpiClkDividerDiv29 = 28u, ///< Clock divider is 29 + HsSpiClkDividerDiv30 = 29u, ///< Clock divider is 30 + HsSpiClkDividerDiv31 = 30u, ///< Clock divider is 31 + HsSpiClkDividerDiv32 = 31u, ///< Clock divider is 32 + HsSpiClkDividerDiv33 = 32u, ///< Clock divider is 33 + HsSpiClkDividerDiv34 = 33u, ///< Clock divider is 34 + HsSpiClkDividerDiv35 = 34u, ///< Clock divider is 35 + HsSpiClkDividerDiv36 = 35u, ///< Clock divider is 36 + HsSpiClkDividerDiv37 = 36u, ///< Clock divider is 37 + HsSpiClkDividerDiv38 = 37u, ///< Clock divider is 38 + HsSpiClkDividerDiv39 = 38u, ///< Clock divider is 39 + HsSpiClkDividerDiv40 = 39u, ///< Clock divider is 40 + HsSpiClkDividerDiv41 = 40u, ///< Clock divider is 41 + HsSpiClkDividerDiv42 = 41u, ///< Clock divider is 42 + HsSpiClkDividerDiv43 = 42u, ///< Clock divider is 43 + HsSpiClkDividerDiv44 = 43u, ///< Clock divider is 44 + HsSpiClkDividerDiv45 = 44u, ///< Clock divider is 45 + HsSpiClkDividerDiv46 = 45u, ///< Clock divider is 46 + HsSpiClkDividerDiv47 = 46u, ///< Clock divider is 47 + HsSpiClkDividerDiv48 = 47u, ///< Clock divider is 48 + HsSpiClkDividerDiv49 = 48u, ///< Clock divider is 49 + HsSpiClkDividerDiv50 = 49u, ///< Clock divider is 50 + HsSpiClkDividerDiv51 = 50u, ///< Clock divider is 51 + HsSpiClkDividerDiv52 = 51u, ///< Clock divider is 52 + HsSpiClkDividerDiv53 = 52u, ///< Clock divider is 53 + HsSpiClkDividerDiv54 = 53u, ///< Clock divider is 54 + HsSpiClkDividerDiv55 = 54u, ///< Clock divider is 55 + HsSpiClkDividerDiv56 = 55u, ///< Clock divider is 56 + HsSpiClkDividerDiv57 = 56u, ///< Clock divider is 57 + HsSpiClkDividerDiv58 = 57u, ///< Clock divider is 58 + HsSpiClkDividerDiv59 = 58u, ///< Clock divider is 59 + HsSpiClkDividerDiv60 = 59u, ///< Clock divider is 60 + HsSpiClkDividerDiv61 = 60u, ///< Clock divider is 61 + HsSpiClkDividerDiv62 = 61u, ///< Clock divider is 62 + HsSpiClkDividerDiv63 = 62u, ///< Clock divider is 63 + HsSpiClkDividerDiv64 = 63u, ///< Clock divider is 64 + HsSpiClkDividerDiv65 = 64u, ///< Clock divider is 65 + HsSpiClkDividerDiv66 = 65u, ///< Clock divider is 66 + HsSpiClkDividerDiv67 = 66u, ///< Clock divider is 67 + HsSpiClkDividerDiv68 = 67u, ///< Clock divider is 68 + HsSpiClkDividerDiv69 = 68u, ///< Clock divider is 69 + HsSpiClkDividerDiv70 = 69u, ///< Clock divider is 70 + HsSpiClkDividerDiv71 = 70u, ///< Clock divider is 71 + HsSpiClkDividerDiv72 = 71u, ///< Clock divider is 72 + HsSpiClkDividerDiv73 = 72u, ///< Clock divider is 73 + HsSpiClkDividerDiv74 = 73u, ///< Clock divider is 74 + HsSpiClkDividerDiv75 = 74u, ///< Clock divider is 75 + HsSpiClkDividerDiv76 = 75u, ///< Clock divider is 76 + HsSpiClkDividerDiv77 = 76u, ///< Clock divider is 77 + HsSpiClkDividerDiv78 = 77u, ///< Clock divider is 78 + HsSpiClkDividerDiv79 = 78u, ///< Clock divider is 79 + HsSpiClkDividerDiv80 = 79u, ///< Clock divider is 80 + HsSpiClkDividerDiv81 = 80u, ///< Clock divider is 81 + HsSpiClkDividerDiv82 = 81u, ///< Clock divider is 82 + HsSpiClkDividerDiv83 = 82u, ///< Clock divider is 83 + HsSpiClkDividerDiv84 = 83u, ///< Clock divider is 84 + HsSpiClkDividerDiv85 = 84u, ///< Clock divider is 85 + HsSpiClkDividerDiv86 = 85u, ///< Clock divider is 86 + HsSpiClkDividerDiv87 = 86u, ///< Clock divider is 87 + HsSpiClkDividerDiv88 = 87u, ///< Clock divider is 88 + HsSpiClkDividerDiv89 = 88u, ///< Clock divider is 89 + HsSpiClkDividerDiv90 = 89u, ///< Clock divider is 90 + HsSpiClkDividerDiv91 = 90u, ///< Clock divider is 91 + HsSpiClkDividerDiv92 = 91u, ///< Clock divider is 92 + HsSpiClkDividerDiv93 = 92u, ///< Clock divider is 93 + HsSpiClkDividerDiv94 = 93u, ///< Clock divider is 94 + HsSpiClkDividerDiv95 = 94u, ///< Clock divider is 95 + HsSpiClkDividerDiv96 = 95u, ///< Clock divider is 96 + HsSpiClkDividerDiv97 = 96u, ///< Clock divider is 97 + HsSpiClkDividerDiv98 = 97u, ///< Clock divider is 98 + HsSpiClkDividerDiv99 = 98u, ///< Clock divider is 99 + HsSpiClkDividerDiv100 = 99u, ///< Clock divider is 100 + HsSpiClkDividerDiv101 = 100u, ///< Clock divider is 101 + HsSpiClkDividerDiv102 = 101u, ///< Clock divider is 102 + HsSpiClkDividerDiv103 = 102u, ///< Clock divider is 103 + HsSpiClkDividerDiv104 = 103u, ///< Clock divider is 104 + HsSpiClkDividerDiv105 = 104u, ///< Clock divider is 105 + HsSpiClkDividerDiv106 = 105u, ///< Clock divider is 106 + HsSpiClkDividerDiv107 = 106u, ///< Clock divider is 107 + HsSpiClkDividerDiv108 = 107u, ///< Clock divider is 108 + HsSpiClkDividerDiv109 = 108u, ///< Clock divider is 109 + HsSpiClkDividerDiv110 = 109u, ///< Clock divider is 110 + HsSpiClkDividerDiv111 = 110u, ///< Clock divider is 111 + HsSpiClkDividerDiv112 = 111u, ///< Clock divider is 112 + HsSpiClkDividerDiv113 = 112u, ///< Clock divider is 113 + HsSpiClkDividerDiv114 = 113u, ///< Clock divider is 114 + HsSpiClkDividerDiv115 = 114u, ///< Clock divider is 115 + HsSpiClkDividerDiv116 = 115u, ///< Clock divider is 116 + HsSpiClkDividerDiv117 = 116u, ///< Clock divider is 117 + HsSpiClkDividerDiv118 = 117u, ///< Clock divider is 118 + HsSpiClkDividerDiv119 = 118u, ///< Clock divider is 119 + HsSpiClkDividerDiv120 = 119u, ///< Clock divider is 120 + HsSpiClkDividerDiv121 = 120u, ///< Clock divider is 121 + HsSpiClkDividerDiv122 = 121u, ///< Clock divider is 122 + HsSpiClkDividerDiv123 = 122u, ///< Clock divider is 123 + HsSpiClkDividerDiv124 = 123u, ///< Clock divider is 124 + HsSpiClkDividerDiv125 = 124u, ///< Clock divider is 125 + HsSpiClkDividerDiv126 = 125u, ///< Clock divider is 126 + HsSpiClkDividerDiv127 = 126u, ///< Clock divider is 127 + HsSpiClkDividerDiv128 = 127u, ///< Clock divider is 128 + HsSpiClkDividerDiv129 = 128u, ///< Clock divider is 129 + HsSpiClkDividerDiv130 = 129u, ///< Clock divider is 130 + HsSpiClkDividerDiv131 = 130u, ///< Clock divider is 131 + HsSpiClkDividerDiv132 = 131u, ///< Clock divider is 132 + HsSpiClkDividerDiv133 = 132u, ///< Clock divider is 133 + HsSpiClkDividerDiv134 = 133u, ///< Clock divider is 134 + HsSpiClkDividerDiv135 = 134u, ///< Clock divider is 135 + HsSpiClkDividerDiv136 = 135u, ///< Clock divider is 136 + HsSpiClkDividerDiv137 = 136u, ///< Clock divider is 137 + HsSpiClkDividerDiv138 = 137u, ///< Clock divider is 138 + HsSpiClkDividerDiv139 = 138u, ///< Clock divider is 139 + HsSpiClkDividerDiv140 = 139u, ///< Clock divider is 140 + HsSpiClkDividerDiv141 = 140u, ///< Clock divider is 141 + HsSpiClkDividerDiv142 = 141u, ///< Clock divider is 142 + HsSpiClkDividerDiv143 = 142u, ///< Clock divider is 143 + HsSpiClkDividerDiv144 = 143u, ///< Clock divider is 144 + HsSpiClkDividerDiv145 = 144u, ///< Clock divider is 145 + HsSpiClkDividerDiv146 = 145u, ///< Clock divider is 146 + HsSpiClkDividerDiv147 = 146u, ///< Clock divider is 147 + HsSpiClkDividerDiv148 = 147u, ///< Clock divider is 148 + HsSpiClkDividerDiv149 = 148u, ///< Clock divider is 149 + HsSpiClkDividerDiv150 = 149u, ///< Clock divider is 150 + HsSpiClkDividerDiv151 = 150u, ///< Clock divider is 151 + HsSpiClkDividerDiv152 = 151u, ///< Clock divider is 152 + HsSpiClkDividerDiv153 = 152u, ///< Clock divider is 153 + HsSpiClkDividerDiv154 = 153u, ///< Clock divider is 154 + HsSpiClkDividerDiv155 = 154u, ///< Clock divider is 155 + HsSpiClkDividerDiv156 = 155u, ///< Clock divider is 156 + HsSpiClkDividerDiv157 = 156u, ///< Clock divider is 157 + HsSpiClkDividerDiv158 = 157u, ///< Clock divider is 158 + HsSpiClkDividerDiv159 = 158u, ///< Clock divider is 159 + HsSpiClkDividerDiv160 = 159u, ///< Clock divider is 160 + HsSpiClkDividerDiv161 = 160u, ///< Clock divider is 161 + HsSpiClkDividerDiv162 = 161u, ///< Clock divider is 162 + HsSpiClkDividerDiv163 = 162u, ///< Clock divider is 163 + HsSpiClkDividerDiv164 = 163u, ///< Clock divider is 164 + HsSpiClkDividerDiv165 = 164u, ///< Clock divider is 165 + HsSpiClkDividerDiv166 = 165u, ///< Clock divider is 166 + HsSpiClkDividerDiv167 = 166u, ///< Clock divider is 167 + HsSpiClkDividerDiv168 = 167u, ///< Clock divider is 168 + HsSpiClkDividerDiv169 = 168u, ///< Clock divider is 169 + HsSpiClkDividerDiv170 = 169u, ///< Clock divider is 170 + HsSpiClkDividerDiv171 = 170u, ///< Clock divider is 171 + HsSpiClkDividerDiv172 = 171u, ///< Clock divider is 172 + HsSpiClkDividerDiv173 = 172u, ///< Clock divider is 173 + HsSpiClkDividerDiv174 = 173u, ///< Clock divider is 174 + HsSpiClkDividerDiv175 = 174u, ///< Clock divider is 175 + HsSpiClkDividerDiv176 = 175u, ///< Clock divider is 176 + HsSpiClkDividerDiv177 = 176u, ///< Clock divider is 177 + HsSpiClkDividerDiv178 = 177u, ///< Clock divider is 178 + HsSpiClkDividerDiv179 = 178u, ///< Clock divider is 179 + HsSpiClkDividerDiv180 = 179u, ///< Clock divider is 180 + HsSpiClkDividerDiv181 = 180u, ///< Clock divider is 181 + HsSpiClkDividerDiv182 = 181u, ///< Clock divider is 182 + HsSpiClkDividerDiv183 = 182u, ///< Clock divider is 183 + HsSpiClkDividerDiv184 = 183u, ///< Clock divider is 184 + HsSpiClkDividerDiv185 = 184u, ///< Clock divider is 185 + HsSpiClkDividerDiv186 = 185u, ///< Clock divider is 186 + HsSpiClkDividerDiv187 = 186u, ///< Clock divider is 187 + HsSpiClkDividerDiv188 = 187u, ///< Clock divider is 188 + HsSpiClkDividerDiv189 = 188u, ///< Clock divider is 189 + HsSpiClkDividerDiv190 = 189u, ///< Clock divider is 190 + HsSpiClkDividerDiv191 = 190u, ///< Clock divider is 191 + HsSpiClkDividerDiv192 = 191u, ///< Clock divider is 192 + HsSpiClkDividerDiv193 = 192u, ///< Clock divider is 193 + HsSpiClkDividerDiv194 = 193u, ///< Clock divider is 194 + HsSpiClkDividerDiv195 = 194u, ///< Clock divider is 195 + HsSpiClkDividerDiv196 = 195u, ///< Clock divider is 196 + HsSpiClkDividerDiv197 = 196u, ///< Clock divider is 197 + HsSpiClkDividerDiv198 = 197u, ///< Clock divider is 198 + HsSpiClkDividerDiv199 = 198u, ///< Clock divider is 199 + HsSpiClkDividerDiv200 = 199u, ///< Clock divider is 200 + HsSpiClkDividerDiv201 = 200u, ///< Clock divider is 201 + HsSpiClkDividerDiv202 = 201u, ///< Clock divider is 202 + HsSpiClkDividerDiv203 = 202u, ///< Clock divider is 203 + HsSpiClkDividerDiv204 = 203u, ///< Clock divider is 204 + HsSpiClkDividerDiv205 = 204u, ///< Clock divider is 205 + HsSpiClkDividerDiv206 = 205u, ///< Clock divider is 206 + HsSpiClkDividerDiv207 = 206u, ///< Clock divider is 207 + HsSpiClkDividerDiv208 = 207u, ///< Clock divider is 208 + HsSpiClkDividerDiv209 = 208u, ///< Clock divider is 209 + HsSpiClkDividerDiv210 = 209u, ///< Clock divider is 210 + HsSpiClkDividerDiv211 = 210u, ///< Clock divider is 211 + HsSpiClkDividerDiv212 = 211u, ///< Clock divider is 212 + HsSpiClkDividerDiv213 = 212u, ///< Clock divider is 213 + HsSpiClkDividerDiv214 = 213u, ///< Clock divider is 214 + HsSpiClkDividerDiv215 = 214u, ///< Clock divider is 215 + HsSpiClkDividerDiv216 = 215u, ///< Clock divider is 216 + HsSpiClkDividerDiv217 = 216u, ///< Clock divider is 217 + HsSpiClkDividerDiv218 = 217u, ///< Clock divider is 218 + HsSpiClkDividerDiv219 = 218u, ///< Clock divider is 219 + HsSpiClkDividerDiv220 = 219u, ///< Clock divider is 220 + HsSpiClkDividerDiv221 = 220u, ///< Clock divider is 221 + HsSpiClkDividerDiv222 = 221u, ///< Clock divider is 222 + HsSpiClkDividerDiv223 = 222u, ///< Clock divider is 223 + HsSpiClkDividerDiv224 = 223u, ///< Clock divider is 224 + HsSpiClkDividerDiv225 = 224u, ///< Clock divider is 225 + HsSpiClkDividerDiv226 = 225u, ///< Clock divider is 226 + HsSpiClkDividerDiv227 = 226u, ///< Clock divider is 227 + HsSpiClkDividerDiv228 = 227u, ///< Clock divider is 228 + HsSpiClkDividerDiv229 = 228u, ///< Clock divider is 229 + HsSpiClkDividerDiv230 = 229u, ///< Clock divider is 230 + HsSpiClkDividerDiv231 = 230u, ///< Clock divider is 231 + HsSpiClkDividerDiv232 = 231u, ///< Clock divider is 232 + HsSpiClkDividerDiv233 = 232u, ///< Clock divider is 233 + HsSpiClkDividerDiv234 = 233u, ///< Clock divider is 234 + HsSpiClkDividerDiv235 = 234u, ///< Clock divider is 235 + HsSpiClkDividerDiv236 = 235u, ///< Clock divider is 236 + HsSpiClkDividerDiv237 = 236u, ///< Clock divider is 237 + HsSpiClkDividerDiv238 = 237u, ///< Clock divider is 238 + HsSpiClkDividerDiv239 = 238u, ///< Clock divider is 239 + HsSpiClkDividerDiv240 = 239u, ///< Clock divider is 240 + HsSpiClkDividerDiv241 = 240u, ///< Clock divider is 241 + HsSpiClkDividerDiv242 = 241u, ///< Clock divider is 242 + HsSpiClkDividerDiv243 = 242u, ///< Clock divider is 243 + HsSpiClkDividerDiv244 = 243u, ///< Clock divider is 244 + HsSpiClkDividerDiv245 = 244u, ///< Clock divider is 245 + HsSpiClkDividerDiv246 = 245u, ///< Clock divider is 246 + HsSpiClkDividerDiv247 = 246u, ///< Clock divider is 247 + HsSpiClkDividerDiv248 = 247u, ///< Clock divider is 248 + HsSpiClkDividerDiv249 = 248u, ///< Clock divider is 249 + HsSpiClkDividerDiv250 = 249u, ///< Clock divider is 250 + HsSpiClkDividerDiv251 = 250u, ///< Clock divider is 251 + HsSpiClkDividerDiv252 = 251u, ///< Clock divider is 252 + HsSpiClkDividerDiv253 = 252u, ///< Clock divider is 253 + HsSpiClkDividerDiv254 = 253u, ///< Clock divider is 254 + HsSpiClkDividerDiv255 = 254u, ///< Clock divider is 255 + HsSpiClkDividerDiv256 = 255u, ///< Clock divider is 256 +} en_hsspi_clk_divider_t; + + +/** +******************************************************************************* +** \brief High Speed SPI clock delay. +** +** Slave-Select to Clock Delay of Peripheral 0 (SS2CD[1:0]). +** This bit is used only when HS-SPI is configured as SPI master in +** direct mode or in command sequencer mode. +** It defines a setup time for the slave device. By delaying the toggling +** of SCLK, SPI delays the data transmission (of slave) from the chip +** select active edge by a multiple of SCLK cycles. +** +** If SPIn_PCC0~3:CPHA = '0', the delay between assertion of slave select and +** first edge on the SCLK is given by: +** (SS2CD + 0.5) number of clock periods of SCLK. +** If SPIn_PCC0~3:CPHA = '1', the delay between assertion of slave select and +** first edge on the SCLK is given by: +** (SS2CD) number of clock periods of SCLK. +** +** When the slave select becomes active, the slave has to prepare +** data transfer within the delay time de?ned by SS2CD bits. +******************************************************************************/ +typedef enum en_hsspi_clk_delay +{ + HsSpiClkStart1ClkAfterSlaveSelect = 0u, + HsSpiClkStart2ClkAfterSlaveSelect = 1u, + HsSpiClkStart3ClkAfterSlaveSelect = 2u, + HsSpiClkStart4ClkAfterSlaveSelect = 3u +} en_hsspi_clk_delay_t; + +/** +****************************************************************************** +** \brief High speed SPI mode. +** +** Used to switch between direct and command sequencer mode. +******************************************************************************/ +typedef enum en_hsspi_mode +{ + HsSpiModeDirect = 0u, ///< Direct mode is enabled, command sequencer is disabled. + HsSpiModeCmdSequencer = 1u ///< Command sequencer is enabled, direct mode is disabled. +} en_hsspi_mode_t; + +/** +****************************************************************************** +** \brief High speed SPI endianess +******************************************************************************/ +typedef enum en_hsspi_endianess +{ + HsSpiBigEndian = 0u, ///< Big Endian + HsSpiLittleEndian = 1u ///< Little Endian +} en_hsspi_endianess_t; + +/** +****************************************************************************** +** \brief High speed SPI transfer protocol. +******************************************************************************/ +typedef enum en_hsspi_transfer_protocol +{ + HsSpiSerialIf = 0u, ///< Serial interface bit width complies with HSSPIn_CSCFG:MDM[1:0] setting + HsSpiDualBitMode = 1u, ///< Dual-bit mode + HsSpiQuadBitMode = 2u, ///< Quad-bit mode + HsSpiSingleBitMode = 3u ///< Single-bit mode +} en_hsspi_transfer_protocol_t; + +/// Enumeration to define an index for each enabled HS-SPI instance +typedef enum en_hsspi_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_HSSPI0 == PDL_ON) + HsSpiInstanceIndexHsSpi0, +#endif + HsSpiInstanceIndexMax +} en_hsspi_instance_index_t; + +/** \}GroupHSSPI_Types */ + +/** +* \addtogroup GroupHSSPI_DataStructures +* \{ +*/ + +/** +****************************************************************************** +** \brief (High speed) SPI configuration. +** +** Struct used for initialisation of SSPI module in direct mode, direct and +** command sequence related parameter can be configured at once, afterwards it +** is possible to switch between modes with HsSpi_SetMode(). +******************************************************************************/ +typedef struct stc_hsspi_config +{ + en_hsspi_clk_divider_t enClockDivider; ///< See description of #en_hsspi_clk_divider_t. + en_hsspi_clk_selection_t enClockSelection; ///< See description of #en_hsspi_clk_selection_t. + uint8_t u8TxFifoThresholdLow; ///< Possible values from 0 to 15 (maximum FIFO depth is 16). + hsspi_tx_func_ptr_t pfnTxStatusCallback; ///< Callback function for transmission status. + en_hsspi_bank_size_t enMemoryBankSize; ///< See description of #en_hsspi_bank_size_t. + en_hsspi_protocol_mode_t enDirectModeProtocol; ///< See description of #en_hsspi_protocol_mode_t. + en_hsspi_protocol_mode_t enCommandSequencerModeProtocol; ///< See description of #en_hsspi_protocol_mode_t. + en_hsspi_memory_type_t enMemoryType; ///< See description of #en_hsspi_memory_type_t. + uint16_t u16IdleTimeOut; ///< The idle timeout interval is in terms of the AHB clock period. Slave select will stay asserted for this time in command sequencer mode. + en_hsspi_fifo_width_t enFifoWidth; ///< See description of #en_hsspi_fifo_width + boolean_t bMasterOperation; ///< TRUE: selects HS-SPI interface operates in Master Mode (default), FALSE: operating in Slave mode (only to be used in single bit mode) + boolean_t bTxDmaBridgeEnable; ///< TRUE: enables TX DMA bridge, FALSE: disable TX DMA bridge + boolean_t bRxDmaBridgeEnable; ///< TRUE: enables RX DMA bridge, FALSE: disable RX DMA bridge +} stc_hsspi_config_t; + +/** +****************************************************************************** +** \brief (High Speed) SPI external device configuration. +** +** This struct is used to configure 1 of 4 possible devices by calling the +** HsSpi_SetExternalDeviceConfig() function. +******************************************************************************/ +typedef struct stc_hsspi_ext_device_config +{ + en_hsspi_clk_divider_t enClockDivider; ///< See description of #en_hsspi_clk_divider_t. + boolean_t bShiftLsbFirst; ///< TRUE: Least significant bit is transmitted first, FALSE: most significant bit is transmitted first. + en_hsspi_clk_delay_t enClockDelay; ///< See description of #en_hsspi_clk_delay_t. + boolean_t bSlaveSelectPolarityHigh; ///< FALSE: Slave select is low-active and held during default state, TRUE: Slave select is high-active and held low during default state + en_hsspi_clk_mode_t enClockMode; ///< See description of #en_hsspi_clk_mode_t. + boolean_t bSafeSync; ///< SAFESYNC bit set or not. + en_hsspi_endianess_t enEndianess; ///< Endianess, see #en_hsspi_endianess_t for details. + uint8_t u8ReadDeselectTime; ///< Read Deselect Time. Allowed values: 1 ... 4 serial clock times + uint8_t u8WriteDeselectTime; ///< Write/different Command Deselect Time. Allowed values: 1 ... 16 serial clock times. + boolean_t bCompensatedClock; ///< TRUE: reception by time-compensated clock, FALSE: No time-compensation +} stc_hsspi_ext_device_config_t; + +/** +****************************************************************************** +** \brief (High Speed) SPI command sequencer control command. +** +** Used to configure the command sequence with defined parameters or with user +** defined data values (by setting enCommand to #HsSpiCmdTransmitData). +******************************************************************************/ +typedef struct stc_hsspi_command_sequencer_control +{ + en_hsspi_command_sequencer_control_t enCommand; ///< See description of #en_hsspi_command_sequencer_control_t. + uint8_t u8Data; ///< 4 bits must be evaluated in case of SpiCmdTransmitHighZStateNibble, otherwise it is evaluated if enCommand is SpiCmdTransmitData. + boolean_t bCont; ///< TRUE: Omit the sequence list, FALSE: Do not omit the list + en_hsspi_transfer_protocol_t enTransferProtocol; ///< see #en_hsspi_transfer_protocol_t for details +} stc_hsspi_command_sequencer_control_t; + +/** +****************************************************************************** +** \brief (High Speed) SPI linked data list. +** +** Used to connect various different buffer sources that shall be transmitted +** during the same transaction, e.g. Ethernet packet with different buffers for +** for the ISO/OSI layer headers (external Ethernet MAC connected via HS-SPI). +******************************************************************************/ +typedef struct stc_hsspi_linked_data_list +{ + const uint8_t* pu8Data; ///< Pointer to transfer data + uint16_t u16ListItemDataSize; ///< Size of transfer data + struct stc_hsspi_linked_data_list* pstcNext; ///< Pointer to next #stc_hsspi_linked_data_list_t item or NULL if end of list +} stc_hsspi_linked_data_list_t; + + +/// HS-SPI instance internal data, storing internal information for each enabled HS-SPI instance. +typedef struct stc_hsspi_intern_data +{ + hsspi_rx_func_ptr_t pfnRxStatusCallbackFunction; + hsspi_tx_func_ptr_t pfnTxStatusCallbackFunction; + uint8_t* pu8RXBuffer; + uint8_t u8BkRXFTH; + uint8_t u8BkRFMTC; + en_hsspi_clk_mode_t enClkMode; + en_hsspi_protocol_mode_t enDirectModeProtocol; + boolean_t bMasterOperation; +} stc_hsspi_intern_data_t; + +/// HS-SPI instance data type +typedef struct stc_hsspi_instance_data +{ + volatile stc_hsspin_t* pstcInstance; ///< pointer to registers of an instance + boolean_t bIsHsSpi; ///< Is HSSPI type peripheral + stc_hsspi_intern_data_t stcInternData; ///< module internal data of instance +} stc_hsspi_instance_data_t; + +/** \} GroupHSSPI_DataStructures */ + +/** +* \addtogroup GroupHSSPI_GlobalVariables +* \{ +*/ +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/// Look-up table for all enabled ADC instances and their internal data +extern stc_hsspi_instance_data_t m_astcHsSpiInstanceDataLut[HS_SPI_INSTANCE_COUNT]; +/** \} GroupHSSPI_GlobalVariables */ + +/** +* \addtogroup GroupHSSPI_Functions +* \{ +*/ +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ +extern en_result_t HsSpi_Init(volatile stc_hsspin_t* pstcHsSpi, const stc_hsspi_config_t* pstcConfig); +extern en_result_t HsSpi_DeInit(volatile stc_hsspin_t* pstcHsSpi); +extern en_result_t HsSpi_SetMode(volatile stc_hsspin_t* pstcHsSpi, en_hsspi_mode_t enMode, en_hsspi_protocol_mode_t enProtocolMode, en_hsspi_protocol_direction_t enProtocolDirection); +extern en_result_t HsSpi_SetExternalDeviceConfig(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const stc_hsspi_ext_device_config_t* pstcConfig); +extern en_result_t HsSpi_DirectModeTransferHalfDuplex(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const uint8_t* pu8TxData, uint16_t u16TxSize, uint8_t* pu8RxData, uint16_t u16RxSize, boolean_t bEnableTxDmaRequest); +extern en_result_t HsSpi_DirectModeTransferHalfDuplexList(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const stc_hsspi_linked_data_list_t* pstcTxData, uint8_t* pu8RxData, uint16_t u16RxSize, boolean_t bEnableTxDmaRequest); +extern en_result_t HsSpi_MultiModeTransfer(volatile stc_hsspin_t* pstcHsSpi, uint8_t u8DeviceNumber, const uint8_t* pu8LegacyData, uint8_t u8LegacyTxSize, const uint8_t* pu8TxData, uint8_t u8TxSize, uint8_t* pu8RxData, uint8_t u8RxSize); +extern en_result_t HsSpi_SetReadCommandSequence(volatile stc_hsspin_t* pstcHsSpi, const stc_hsspi_command_sequencer_control_t* pstcCmdSequence); +extern en_result_t HsSpi_SetWriteCommandSequence(volatile stc_hsspin_t* pstcHsSpi, const stc_hsspi_command_sequencer_control_t* pstcCmdSequence); + +/** \} GroupHSSPI_Functions */ +/** \} GroupHSSPI */ +#endif // #if (defined(PDL_PERIPHERAL_HSSPI_ACTIVE)) + +#ifdef __cplusplus +} +#endif + +#endif /* __HSSPI_H__ */ +/*****************************************************************************/ +/* EOF (not truncated) */ +/*****************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2cs/i2cs.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2cs/i2cs.c new file mode 100644 index 0000000000..04e54fb910 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2cs/i2cs.c @@ -0,0 +1,760 @@ +/******************************************************************************* +* \file i2cs.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the I2C +* Slave driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "i2cs/i2cs.h" + +#if (defined(PDL_PERIPHERAL_I2CS_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled I2CS instances and their internal data +stc_i2cs_instance_data_t m_astcI2csInstanceDataLut[I2CS_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_I2CS0 == PDL_ON) + { + &I2CS0, // pstcInstance + { + 0u, 0u, 0u, 0u + }, + } +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_I2CS0 == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of transmit interrupts + ** according CMSIS with level defined in pdl.h + ** + ** \param pstcI2cs Pointer to I2CS instance + ** + ******************************************************************************/ +static void I2csInitNvic(volatile stc_i2csn_t* pstcI2cs) +{ + if (pstcI2cs == (volatile stc_i2csn_t*)(&I2CS0)) + { + NVIC_ClearPendingIRQ(MFS6_RX_TX_I2CSLAVE_IRQn); + NVIC_EnableIRQ(MFS6_RX_TX_I2CSLAVE_IRQn); + NVIC_SetPriority(MFS6_RX_TX_I2CSLAVE_IRQn, PDL_IRQ_LEVEL_MFS6_I2CS0); + } + +} /* I2csInitNvic */ + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ** \param pstcI2cs Pointer to I2CS instance + ** + ******************************************************************************/ +static void I2csDeInitNvic(volatile stc_i2csn_t* pstcI2cs) +{ + if (pstcI2cs == (volatile stc_i2csn_t*)(&I2CS0)) + { + NVIC_ClearPendingIRQ(MFS6_RX_TX_I2CSLAVE_IRQn); + NVIC_DisableIRQ(MFS6_RX_TX_I2CSLAVE_IRQn); + NVIC_SetPriority(MFS6_RX_TX_I2CSLAVE_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + +} /* I2csDeInitNvic */ + +#endif +/** + ****************************************************************************** + ** \brief Return the internal data for a certain I2C instance. + ** + ** \param pstcI2cs Pointer to I2CS instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_i2cs_intern_data_t* I2csGetInternDataPtr(volatile stc_i2csn_t* pstcI2cs) +{ + stc_i2cs_intern_data_t* pstcInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcI2cs) + { + for (u32Instance = 0u; u32Instance < (uint32_t)I2csInstanceIndexMax; u32Instance++) + { + if (pstcI2cs == m_astcI2csInstanceDataLut[u32Instance].pstcInstance) + { + pstcInternDataPtr = &m_astcI2csInstanceDataLut[u32Instance].stcInternData; + break; + } + } + + } + + return (pstcInternDataPtr); +} /* MfsGetInternDataPtr */ + + +#if (PDL_INTERRUPT_ENABLE_I2CS0 == PDL_ON) +/** + ****************************************************************************** + ** \brief I2CS receive interrupt service routine. + ** + ** \param pstcI2cs Pointer to I2CS instance + ** \param pstcInternData Pointer to I2CS internal data structure + ** + ** This function is called on I2CS Receive IRQ. + ** + ******************************************************************************/ +void I2csIrqHandlerRx( volatile stc_i2csn_t* pstcI2cs, + stc_i2cs_intern_data_t* pstcInternData) +{ + if ((NULL != pstcI2cs) && (NULL != pstcInternData)) + { + if (NULL != pstcInternData->pfnRxIrqCb) + { + pstcInternData->pfnRxIrqCb(); + } + } +} /* MfsIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief I2CS transfer interrupt service routine. + ** + ** \param pstcI2cs Pointer to I2CS instance + ** \param pstcInternData Pointer to I2CS internal data structure + ** + ** This function is called on I2CS transfer IRQ. + ** + ******************************************************************************/ +void I2csIrqHandlerTx( volatile stc_i2csn_t* pstcI2cs, + stc_i2cs_intern_data_t* pstcInternData) +{ + if ((NULL != pstcI2cs) && (NULL != pstcInternData)) + { + if (NULL != pstcInternData->pfnTxIrqCb) + { + pstcInternData->pfnTxIrqCb(); + } + } + +} /* I2csIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief I2CS status interrupt service routine. + ** + ** \param pstcI2cs Pointer to I2CS instance + ** \param pstcInternData Pointer to I2CS internal data structure + ** + ** This function is called on I2CS status IRQ. + ** + ******************************************************************************/ +void I2csIrqHandlerStatus( volatile stc_i2csn_t* pstcI2cs, + stc_i2cs_intern_data_t* pstcInternData) +{ + if ((NULL != pstcI2cs) && (NULL != pstcInternData)) + { + if(1u == pstcI2cs->IBSSR_f.INT) + { + if (NULL != pstcInternData->pfnStatusIrqCb) + { + pstcInternData->pfnStatusIrqCb(); + } + + pstcI2cs->IBSSCR = 0x0400u; + } + + if(1u == pstcI2cs->IBSSR_f.RSC) + { + if (NULL != pstcInternData->pfnCondIrqCb) + { + pstcInternData->pfnCondIrqCb(I2CS_IRQ_COND_RESTART_DETECTION); + } + + pstcI2cs->IBSSCR = 0x0004u; + } + + if(1u == pstcI2cs->IBSSR_f.SPC) + { + if (NULL != pstcInternData->pfnCondIrqCb) + { + pstcInternData->pfnCondIrqCb(I2CS_IRQ_COND_STOP_DETECTION); + } + + pstcI2cs->IBSSCR = 0x0002u; + } + } +} + +/** + ****************************************************************************** + ** \brief Enable I2CS interrupts + ** + ** \param [in] pstcI2cs Pointer to I2CS instance + ** \param [in] enIrqSel enumeration of I2CS interrupt selection + ** \arg I2cTxIrq TX interrupt of I2CS + ** \arg I2cRxIrq RX interrupt of I2CS + ** \arg I2cStatusIrq status interrupt of I2C + ** \arg I2cCondIrq condition interrupt of I2C + ** + ** \retval Ok Interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t I2cs_EnableIrq(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_irq_sel_t enIrqSel) +{ + if (NULL == pstcI2cs) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case I2csTxIrq: + pstcI2cs->IBSCR_f.TIE = 1u; + break; + case I2csRxIrq: + pstcI2cs->IBSCR_f.RIE = 1u; + break; + case I2csStatusIrq: + pstcI2cs->IBSCR_f.INTE = 1u; + break; + case I2csCondIrq: + pstcI2cs->IBSCR_f.CNDE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable I2CS interrupts + ** + ** \param [in] pstcI2cs Pointer to I2C instance + ** \param [in] enIrqSel enumeration of I2C interrupt selection + ** \arg I2cTxIrq TX interrupt of I2CS + ** \arg I2cRxIrq RX interrupt of I2CS + ** \arg I2cStatusIrq status interrupt of I2C + ** \arg I2cCondIrq condition interrupt of I2C + ** + ** \retval Ok Interrupts has been disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t I2cs_DisableIrq(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_irq_sel_t enIrqSel) +{ + if (NULL == pstcI2cs) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case I2csTxIrq: + pstcI2cs->IBSCR_f.TIE = 0u; + break; + case I2csRxIrq: + pstcI2cs->IBSCR_f.RIE = 0u; + break; + case I2csStatusIrq: + pstcI2cs->IBSCR_f.INTE = 0u; + break; + case I2csCondIrq: + pstcI2cs->IBSCR_f.CNDE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialization of I2CS module. + ** + ** Set registers to active I2C Slave. + ** + ** \param [in] pstcI2cs Pointer to I2CS instance register area + ** \param [in] pstcConfig I2CS configuration + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_I2CS0)) + ** + ******************************************************************************/ +en_result_t I2cs_Init(volatile stc_i2csn_t* pstcI2cs, + const stc_i2cs_config_t* pstcConfig) +{ + stc_i2cs_intern_data_t* pstcInternData; + + /* Preset local register variables to zero */ + stc_i2cslave_ibscr_field_t stcIBSCR; + stc_i2cslave_ibsadr_field_t stcIBSADR; + stc_i2cslave_ibsmskr_field_t stcIBSMSKR; + stc_i2cslave_ibsdstupr_field_t stcIBSDSTUPR; + + PDL_ZERO_STRUCT(stcIBSCR); + PDL_ZERO_STRUCT(stcIBSADR); + PDL_ZERO_STRUCT(stcIBSMSKR); + PDL_ZERO_STRUCT(stcIBSDSTUPR); + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcInternData = I2csGetInternDataPtr(pstcI2cs); + + /* Parameter check and get ptr to internal data struct */ + if ((NULL == pstcInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* Ack enable */ + stcIBSCR.ACKE = TRUE; + + /* Set WSEL */ + stcIBSCR.WSEL = ((TRUE == pstcConfig->bWaitSelection) ? 1u : 0u) ; + + /* Set noise filter */ + stcIBSCR.NFCNT = ((TRUE == pstcConfig->bEnableNoiseFilter) ? 0u : 3u) ; + + /* Set reverved address enable */ + stcIBSCR.RSVEN = ((TRUE == pstcConfig->bEnableReservedAddr) ? 1u : 0u) ; + + /* Set slave address */ + stcIBSADR.SA = pstcConfig->u8SlaveAddr; + + /* Enable slave address detection */ + stcIBSADR.SAEN = ((TRUE == pstcConfig->bEnableSlaveAddr) ? 1u : 0u); + + /* Set slave address bit mask */ + stcIBSMSKR.SM = pstcConfig->u8SlaveMaskAddr; + + /* Set setup time */ + stcIBSDSTUPR.SETUP = pstcConfig->u8SetupTime; + + /* Enable I2C*/ + stcIBSMSKR.EN = TRUE; + + /* now setup hardware with correct mode first and then go on with */ + /* bit settings */ + + /* I2C disable before other registers are set. */ + pstcI2cs->IBSMSKR_f.EN = 0u; + + /* Set registers value */ + pstcI2cs->IBSDSTUPR_f = stcIBSDSTUPR; + pstcI2cs->IBSCR_f = stcIBSCR; + pstcI2cs->IBSADR_f = stcIBSADR; + pstcI2cs->IBSMSKR_f = stcIBSMSKR; + +#if (PDL_INTERRUPT_ENABLE_I2CS0 == PDL_ON) + /* Configure interrupt */ + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTxIrq) + { + pstcI2cs->IBSCR_f.TIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bRxIrq) + { + pstcI2cs->IBSCR_f.RIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bStatusIrq) + { + pstcI2cs->IBSCR_f.INTE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bCondIrq) + { + pstcI2cs->IBSCR_f.CNDE = 1u; + } + + + } + + /* Configure interrupt callback */ + if(NULL != pstcConfig->pstcIrqCb) + { + pstcInternData->pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcInternData->pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcInternData->pfnStatusIrqCb = pstcConfig->pstcIrqCb->pfnStatusIrqCb; + pstcInternData->pfnCondIrqCb = pstcConfig->pstcIrqCb->pfnCondIrqCb; + } + + /* Configure NVIC */ + if(TRUE == pstcConfig->bTouchNvic) + { + I2csInitNvic(pstcI2cs); + } + +#endif + + return (Ok); +} /* I2cs_Init */ + +/** + ****************************************************************************** + ** \brief Deinitialisation of I2C Slave. + ** + ** All used I2CS register are reset to their default values. + ** + ** \param [in] pstcI2cs Pointer to I2CS instance register area + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** + ******************************************************************************/ +en_result_t I2cs_DeInit( volatile stc_i2csn_t* pstcI2cs, boolean_t bTouchNvic) +{ + en_result_t enResult; + stc_i2cs_intern_data_t* pstcInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcInternData = I2csGetInternDataPtr(pstcI2cs); + /* ... and check */ + if (NULL == pstcInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + /* Disable I2CS */ + pstcI2cs->IBSMSKR = 0u; + + /* Reset all other used register to default value */ + pstcI2cs->IBSCR = 0u; + pstcI2cs->IBSADR = 0u; + pstcI2cs->IBSDSTUPR = 0u; + +#if (PDL_INTERRUPT_ENABLE_I2CS0 == PDL_ON) + if(TRUE == bTouchNvic) + { + I2csDeInitNvic(pstcI2cs); + } +#endif + enResult = Ok; + } + + return (enResult); +} /* I2cs_DeInit */ + +/** + ****************************************************************************** + ** \brief Write I2CS data buffer + ** + ** \param [in] pstcI2cs Pointer to I2CS instance + ** \param [in] u8Data Data to be sent + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** + ******************************************************************************/ +en_result_t I2cs_SendData(volatile stc_i2csn_t* pstcI2cs, uint8_t u8Data) +{ + if (NULL == pstcI2cs) + { + return ErrorInvalidParameter; + } + + pstcI2cs->IBSTDR = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read I2CS data buffer + ** + ** \param [in] pstcI2cs Pointer to I2CS instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint8_t I2cs_ReceiveData(volatile stc_i2csn_t* pstcI2cs) +{ + return pstcI2cs->IBSRDR; +} + +/** + ****************************************************************************** + ** \brief Configure ACK signal sent to master + ** + ** \param [in] pstcI2cs Pointer to I2C instance + ** \param [in] enAck ACK to be sent + ** \arg I2cAck ACK will be sent as response signal + ** \arg I2cNAck NACK will be sent as response signal + ** + ** \retval Ok ACK signal has been successfully configured + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** + ** This function is only meaningful when I2C is in slave mode + ** + ******************************************************************************/ +en_result_t I2cs_ConfigAck(volatile stc_i2csn_t* pstcI2cs, en_i2cs_ack_t enAck) +{ + if (NULL == pstcI2cs) + { + return ErrorInvalidParameter; + } + + (I2csAck == enAck) ? (pstcI2cs->IBSCR_f.ACKE = 1u) : (pstcI2cs->IBSCR_f.ACKE = 0u); + + return Ok; + +} + +/** + ****************************************************************************** + ** \brief Get the ACK signal from slave + ** + ** \param [in] pstcI2cs Pointer to I2C instance + ** + ** \retval I2cAck Receive the ACK from I2C Slave + ** \retval I2cNAck Receive the NACK from I2C Slave + ** + ** This function applies in the I2C master mode. + ** + ******************************************************************************/ +en_i2cs_ack_t I2cs_GetAck(volatile stc_i2csn_t* pstcI2cs) +{ + en_i2cs_ack_t enRet; + + enRet = (0u == pstcI2cs->IBSSR_f.RACK) ? I2csAck : I2csNAck; + + return enRet; +} + +/** + ****************************************************************************** + ** \brief Get status of I2CS according to status type + ** + ** \param [in] pstcI2cs Pointer to I2CS instance + ** \param [in] enStatus I2C status type + ** \arg I2csStatus I2CS status interrupt request flag + ** \arg I2csRxFull I2CS RX buffer full interrupt request flag + ** \arg I2csTxEmpty I2CS TX buffer empty interrupt request flag + ** \arg I2csFirstByteDetect I2CS First byte detection + ** \arg I2csReservedByteDetect I2CS reserved byte detection + ** \arg I2csActive I2CS active status + ** \arg I2csRestartDetect I2CS re-start condition detection + ** \arg I2cStopDetect I2CS stop condition detection + ** \arg I2csBusBusy I2CS bus busy status + ** + ** \retval FALSE If one of following conditions are met: + ** - I2CS status interrupt request flag is clear [enStatus = I2csStatus] + ** - I2CS receive buffer is not full [enStatus = I2cRxFull] + ** - I2CS tranfer buffer is not empty [enStatus = I2cTxEmpty] + ** - I2CS first byte is not detected [enStatus = I2cFirstByteDetect] + ** - I2CS reserved address is not detected [enStatus = I2cReservedByteDetect] + ** - I2CS not active [enStatus = I2csActive] + ** - I2CS restart is not detected [enStatus = I2csRestart] + ** - I2CS stop is not detected [enStatus = I2cStopDetect] + ** - I2CS bus is idle [enStatus = I2cBusStatus] + ** + ** \retval TRUE If one of following conditions are met: + ** - I2CS status interrupt request flag is set [enStatus = I2csStatus] + ** - I2CS receive buffer is full [enStatus = I2cRxFull] + ** - I2CS tranfer buffer is empty [enStatus = I2cTxEmpty] + ** - I2CS first byte is detected [enStatus = I2cFirstByteDetect] + ** - I2CS reserved address is detected [enStatus = I2cReservedByteDetect] + ** - I2CS is active [enStatus = I2csActive] + ** - I2CS restart is detected [enStatus = I2csRestart] + ** - I2CS stop is detected [enStatus = I2cStopDetect] + ** - I2CS bus is busy [enStatus = I2cBusStatus] + ** + ******************************************************************************/ +boolean_t I2cs_GetStatus(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_status_t enStatus) +{ + boolean_t bRet = FALSE; + + switch(enStatus) + { + case I2csStatus: + bRet = (1u == pstcI2cs->IBSSR_f.INT ) ? TRUE : FALSE; + break; + case I2csRxFull: + bRet = (1u == pstcI2cs->IBSSR_f.RDRF) ? TRUE : FALSE; + break; + case I2csTxEmpty: + bRet = (1u == pstcI2cs->IBSSR_f.TDRE) ? TRUE : FALSE; + break; + case I2csFirstByteDetect: + bRet = (1u == pstcI2cs->IBSSR_f.FBT) ? TRUE : FALSE; + break; + case I2csReservedByteDetect: + bRet = (1u == pstcI2cs->IBSSR_f.RSA ) ? TRUE : FALSE; + break; + case I2csActive: + bRet = (1u == pstcI2cs->IBSSR_f.ACT ) ? TRUE : FALSE; + break; + case I2csRestartDetect: + bRet = (1u == pstcI2cs->IBSSR_f.SPC) ? TRUE : FALSE; + break; + case I2csStopDetect: + bRet = (1u == pstcI2cs->IBSSR_f.SPC) ? TRUE : FALSE; + break; + case I2csBusBusy: + bRet = (1u == pstcI2cs->IBSSR_f.BB) ? TRUE : FALSE; + break; + default: + break; + } + + return bRet; +} + + +/** + ****************************************************************************** + ** \brief Clear status of I2CS according to status type + ** + ** \param [in] pstcI2cs Pointer to I2CS instance + ** \param [in] enStatus I2CS status type + ** \arg I2csStatus I2CS status interrupt request flag + ** \arg I2csRxFull I2CS RX buffer full interrupt request flag + ** \arg I2csTxEmpty I2CS TX buffer empty interrupt request flag + ** \arg I2csFirstByteDetect I2CS First byte detection + ** \arg I2csReservedByteDetect I2CS reserved byte detection + ** \arg I2csActive I2CS active status + ** \arg I2csRestartDetect I2CS re-start condition detection + ** \arg I2cStopDetect I2CS stop condition detection + ** \arg I2csBusBusy I2CS bus busy status + ** + ** \retval Ok Status has been cleared normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2cs == NULL + ** \note The following status can only be cleared by hardware behavior: + ** - I2cRxFull + ** - I2cTxEmpty + ** - I2cFirstByteDetect + ** - I2cReservedByteDetect + ** - I2csRestartDetect + ** - I2csStopDetect + ** - I2cBusBusy + ** + ******************************************************************************/ +en_result_t I2cs_ClrStatus(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_status_t enStatus) +{ + if (NULL == pstcI2cs) + { + return ErrorInvalidParameter; + } + + switch(enStatus) + { + case I2csStatus: + pstcI2cs->IBSSCR = 0x0400u; + break; + case I2csRxFull: + case I2csTxEmpty: + break; + case I2csFirstByteDetect: + break; + case I2csReservedByteDetect: + break; + case I2csActive: + break; + case I2csRestartDetect: + pstcI2cs->IBSSCR = 0x0004u; + break; + case I2csStopDetect: + pstcI2cs->IBSSCR = 0x0002u; + break; + case I2csBusBusy: + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get direction of I2CS data in slave mode + ** + ** \param [in] pstcI2cs Pointer to I2CS instance + ** + ** \retval i2c_master_tx_slave_rx Master will send data to slave + ** \retval i2c_slave_tx_master_rx Master will receive data from slave + ** + ** This function can be called after receiving the device address from master + ** in the slave mode. + ** + ******************************************************************************/ +en_i2cs_data_dir_t I2cs_GetDataDir(volatile stc_i2csn_t* pstcI2cs) +{ + en_i2cs_data_dir_t enDir; + + (0u == pstcI2cs->IBSSR_f.TRX) ? (enDir = I2csDataRx) : (enDir = I2csDataTx); + + return enDir; +} + +#endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2cs/i2cs.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2cs/i2cs.h new file mode 100644 index 0000000000..a5c1edf2b5 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2cs/i2cs.h @@ -0,0 +1,338 @@ +/******************************************************************************* +* \file i2cs.h +* +* \version 1.20 +* +* \brief Headerfile for I2C Slave functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __I2CS_H__ +#define __I2CS_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_I2CS_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupI2CS I2C Slave (I2CS) +* \{ +* \defgroup GroupI2CS_Macros Macros +* \defgroup GroupI2CS_Functions Functions +* \defgroup GroupI2CS_GlobalVariables Global Variables +* \defgroup GroupI2CS_DataStructures Data Structures +* \defgroup GroupI2CS_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupI2CS +* \{ +* I2C Slave (I2CS) implements the slave function of I2C. The microcontroller can wake up when the +* slave address matches.
+* I2CS supports four interrupts.
+* - Data transmit +* - Data receive +* - I2CS condition +* - I2CS status
+* If the value of the I2C Bus Slave Address matches the received slave address masked by the +* I2C Bus Slave Mask Address, I2C Slave acknowledges automatically. It is possible to disable the +* detection of the slave address.
+* I2C Slave can wake up the microcontroller when its address or one of the reserved addresses is received. +* The I2C reserved addresses are used for special purposes per I2C Specification (2000). +* Software judges whether the reserved address is supported or not. +* \note I2C Slave supports the Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus +* (Fm+).
+* I2C Slave doesn't support the High-speed mode (Hs-mode) and Ultra Fast-mode +* (UFm).
+* I2C Slave doesn't support the following protocol. CBUS, SMBus, PMBus, IPMI, ATCA, DDC. +* +* \section SectionI2CS_ConfigurationConsideration Configuration Consideration +* To set up an I2CS, you provide configuration parameters in the stc_i2cs_config_t structure. +* For example, you provide the slave address and mask, enable slave address detection and +* reserved address detection. You also specify which interrupts to enable in an stc_i2cs_irq_en_t +* structure. Provide the required callback functions in an stc_i2cs_irq_cb_t structure. +* The config structure has fields for the addresses of the enable and callback structures.
+* Then call I2cs_Init().
+* You can enable or disable interrupts after configuring. You can also send and receive a byte of data.
+* Use I2cs_ConfigAck() to send an ACK or NACK signal when receiving data. I2cs_GetAck() gets the ACK signal status +* after receiving an ACK.
+* Use I2cs_GetStatus() to poll for a variety of conditions. Use values defined in en_i2cs_status_t. For +* example, use this function to get interrupt flags, to determine if the Rx buffer is full, and so on.
+* Use I2cs_ClrStatus() to clear the I2C Slave status selected. Some status can only be cleared by hardware automatically.
+* I2cs_GetDataDir() gets the data direction of I2CS in the slave mode. +* +* +* \section SectionI2CS_MoreInfo More Information +* For more information on the I2C Slave peripheral, refer to:
+* FM0+ Peripheral Manual - Communication Subsystem TRM.pdf
+* FM4 Peripheral Manual - Communication Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupI2CS_Macros +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define stc_i2csn_t FM_I2CSLAVE_TypeDef + +#define I2CS0 (*((volatile stc_i2csn_t *) FM_I2CSLAVE_BASE)) + +#define I2CS_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_I2CS0 == PDL_ON) + +#define I2CS0_DATA_REG_ADDR (uint32_t)(&FM_I2CS0->TDR) + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +#define I2CS_IRQ_COND_RESTART_DETECTION 0u +#define I2CS_IRQ_COND_STOP_DETECTION 1u + +/** \} GroupI2CS_Macros */ + +/** +* \addtogroup GroupI2CS_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief I2CS ACK types + ******************************************************************************/ +typedef enum en_i2cs_ack +{ + I2csAck = 0u, ///< I2CS normal ACK + I2csNAck = 1u, ///< I2CS NACK + +}en_i2cs_ack_t; + +/** + ****************************************************************************** + ** \brief I2CS interrupt selection + ******************************************************************************/ +typedef enum en_i2cs_irq_sel +{ + I2csTxIrq = 0u, ///< I2CS TX interrupt + I2csRxIrq = 1u, ///< I2CS RX interrupt + I2csCondIrq = 2u, ///< I2CS condition detection interrupt + I2csStatusIrq = 3u, ///< I2CS status interrupt + +}en_i2cs_irq_sel_t; + +/** + ****************************************************************************** + ** \brief I2CS status types + ******************************************************************************/ +typedef enum en_i2cs_status +{ + I2csStatus = 0u, ///< I2CS status interrupt request flag + I2csRxFull = 1u, ///< I2CS RX buffer full interrupt request flag + I2csTxEmpty = 2u, ///< I2CS TX buffer empty interrupt request flag + I2csFirstByteDetect = 3u, ///< I2CS First byte detection + I2csReservedByteDetect = 4u, ///< I2CS reserved byte detection + I2csActive = 5u, ///< I2CS active + I2csRestartDetect = 6u, ///< I2CS re-start condition detection + I2csStopDetect = 7u, ///< I2CS stop condition detection + I2csBusBusy = 8u, ///< I2CS Bus busy status +}en_i2cs_status_t; + +/** + ****************************************************************************** + ** \brief I2CS data direction + ******************************************************************************/ +typedef enum en_i2cs_data_dir +{ + I2csDataRx = 0u, ///< Data from master to slave + I2csDataTx = 1u, ///< Data from slave to master + +}en_i2cs_data_dir_t; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +/// Enumeration to define an index for each enabled I2CS instance +typedef enum en_i2cs_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_I2CS0 == PDL_ON) + I2csInstanceIndexI2cs0, +#endif + I2csInstanceIndexMax, + I2csInstanceIndexUnknown = 0xFFu, + +} en_i2cs_instance_index_t; + +/** \} GroupI2CS_Types */ + +/** +* \addtogroup GroupI2CS_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief I2CS interrupt enable structure + ******************************************************************************/ +typedef struct stc_i2cs_irq_en +{ + boolean_t bTxIrq; ///< I2CS TX interrupt + boolean_t bRxIrq; ///< I2CS RX interrupt + boolean_t bCondIrq; ///< I2CS condition interrupt + boolean_t bStatusIrq; ///< I2CS condition interrupt + +}stc_i2cs_irq_en_t; + +/** + ****************************************************************************** + ** \brief I2CS interrupt callback function + ******************************************************************************/ +typedef struct stc_i2cs_irq_cb +{ + func_ptr_t pfnTxIrqCb; ///< I2CS TX interrupt callback function pointer + func_ptr_t pfnRxIrqCb; ///< I2CS RX interrupt callback function pointer + func_ptr_arg1_t pfnCondIrqCb; ///< I2CS Condition interrupt callback function pointer + func_ptr_t pfnStatusIrqCb; ///< I2CS status interrupt callback function pointer + +}stc_i2cs_irq_cb_t; + +/** + ****************************************************************************** + ** \brief I2CS configuration structure + ******************************************************************************/ +typedef struct stc_i2cs_config +{ + uint8_t u8SlaveAddr; ///< Slave address (This is effective on slave mode. + uint8_t u8SlaveMaskAddr; ///< Slave Mask address (This is effective on slave mode.) + boolean_t bEnableSlaveAddr; ///< FLASE: disable slave address comparison, TRUE: enable salve address comparison + boolean_t bEnableReservedAddr; ///< FALSE: disable the detection of the reserved addresses (0000xxx or 1111xxx), TRUE: enable the detection of the reserved addresses (0000xxx or 1111xxx) + boolean_t bWaitSelection; ///< FALSE: generate interrupt after ACK, TRUE: generate interrupt before ACK + boolean_t bEnableNoiseFilter; ///< FALSE: disable noise filter, TRUE: enable noise filter + uint8_t u8SetupTime; ///< Setup time between the I2C data line (SDA) and I2C clock line (SCL) + +#if (PDL_INTERRUPT_ENABLE_I2CS0 == PDL_ON) + stc_i2cs_irq_en_t* pstcIrqEn; ///< Pointer to I2CS interrupt enable structure, if set to NULL, no interrupt enabled. + stc_i2cs_irq_cb_t* pstcIrqCb; ///< Pointer to I2CS interrupt callback functions structurei, if set to NULL, no interrupt callback initialized. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +} stc_i2cs_config_t; + +/// I2CS module internal data, storing internal information for each enabled I2CS instance. +typedef struct stc_i2cs_intern_data +{ + func_ptr_t pfnTxIrqCb; ///< I2CS TX interrupt callback function pointer + func_ptr_t pfnRxIrqCb; ///< I2CS RX interrupt callback function pointer + func_ptr_arg1_t pfnCondIrqCb; ///< I2CS Condition interrupt callback function pointer + func_ptr_t pfnStatusIrqCb; ///< I2CS status interrupt callback function pointer + +} stc_i2cs_intern_data_t; + +/// I2CS instance data type +typedef struct stc_i2cs_instance_data +{ + volatile stc_i2csn_t* pstcInstance; ///< pointer to registers of an instance + stc_i2cs_intern_data_t stcInternData; ///< module internal data of instance +} stc_i2cs_instance_data_t; + +/** \} GroupI2CS_DataStructures */ + +/** +* \addtogroup GroupI2CS_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled I2CS instances and their internal data +extern stc_i2cs_instance_data_t m_astcI2csInstanceDataLut[I2CS_INSTANCE_COUNT]; + +/** \} GroupI2CS_GlobalVariables */ + +/** +* \addtogroup GroupI2CS_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* I2CS */ +#if (PDL_INTERRUPT_ENABLE_I2CS0 == PDL_ON) +// Interrupt +void I2csIrqHandlerTx(volatile stc_i2csn_t* pstcI2cs, + stc_i2cs_intern_data_t* pstcInternData); +void I2csIrqHandlerRx(volatile stc_i2csn_t* pstcI2cs, + stc_i2cs_intern_data_t* pstcInternData); +void I2csIrqHandlerStatus(volatile stc_i2csn_t* pstcI2cs, + stc_i2cs_intern_data_t* pstcInternData); +en_result_t I2cs_EnableIrq(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_irq_sel_t enIrqSel); +en_result_t I2cs_DisableIrq(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_irq_sel_t enIrqSel); +#endif +// Init/De-Init +en_result_t I2cs_Init(volatile stc_i2csn_t* pstcI2cs, + const stc_i2cs_config_t* pstcConfig); +en_result_t I2cs_DeInit(volatile stc_i2csn_t* pstcI2cs, boolean_t bTouchNvic); + +// Data read/write +en_result_t I2cs_SendData(volatile stc_i2csn_t* pstcI2cs, uint8_t u8Data); +uint8_t I2cs_ReceiveData(volatile stc_i2csn_t* pstcI2cs); + +// ACK +en_result_t I2cs_ConfigAck(volatile stc_i2csn_t* pstcI2cs, en_i2cs_ack_t enAck); +en_i2cs_ack_t I2cs_GetAck(volatile stc_i2csn_t* pstcI2cs); + +// Status read/clear +boolean_t I2cs_GetStatus(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_status_t enStatus); +en_result_t I2cs_ClrStatus(volatile stc_i2csn_t* pstcI2cs, + en_i2cs_status_t enStatus); + +// Get Data direction +en_i2cs_data_dir_t I2cs_GetDataDir(volatile stc_i2csn_t* pstcI2cs); + +/** \} GroupI2CS_Functions */ +/** \} GroupI2CS */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_I2CS_ACTIVE)) */ + +#endif /* __I2CS_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2s/i2s.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2s/i2s.c new file mode 100644 index 0000000000..c0db285471 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2s/i2s.c @@ -0,0 +1,1252 @@ +/******************************************************************************* +* \file i2s.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the I2S +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "i2s/i2s.h" + +#if (defined(PDL_PERIPHERAL_I2S_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled I2S instances and their internal data +stc_i2s_instance_data_t m_astcI2sInstanceDataLut[I2sInstanceIndexMax] = +{ +#if (PDL_PERIPHERAL_ENABLE_I2S0 == PDL_ON) + { + &I2S0, // pstcInstance + {0u,0u,0u,0u,0u,0u,0u,0u,0u,0u,0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_I2S1 == PDL_ON) + { + &I2S1, // pstcInstance + {0u,0u,0u,0u,0u,0u,0u,0u,0u,0u,0u} // stcInternData (not initialized yet) + } +#endif +}; + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain I2S instance. + ** + ** \param pstcI2s Pointer to I2S instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_i2s_intern_data_t* I2sGetInternDataPtr(volatile stc_i2sn_t* pstcI2s) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < I2S_INSTANCE_COUNT; u8Instance++) + { + if (pstcI2s == m_astcI2sInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcI2sInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} + +#if (PDL_INTERRUPT_ENABLE_I2S0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_I2S1 == PDL_ON) +/** + ****************************************************************************** + ** \brief I2S instance interrupt service routine + ** + ** I2S instance interrupt service routine, clear interrupt cause and + ** + ** \param pstcI2s Pointer to I2S instance + ** \param pstcI2sInternData Pointer to I2S intern data + ** + ******************************************************************************/ +void I2sIrqHandler( volatile stc_i2sn_t* pstcI2s, + stc_i2s_intern_data_t* pstcI2sInternData) +{ + if (1u == pstcI2s->STATUS_f.TBERR) // DMA transmit channel block size large than transmit FIFO threshold value of I2S + { + pstcI2s->STATUS_f.TBERR = 0u; + + if (pstcI2sInternData->pfnTxBlockSizeErrIrqCb != NULL) + { + pstcI2sInternData->pfnTxBlockSizeErrIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.RBERR) // DMA receive channel block size large than receive FIFO threshold value of I2S + { + pstcI2s->STATUS_f.RBERR = 0u; + + if (pstcI2sInternData->pfnRxBlockSizeErrIrqCb != NULL) + { + pstcI2sInternData->pfnRxBlockSizeErrIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.FERR) // Frame error + { + pstcI2s->STATUS_f.FERR = 0u; + + if (pstcI2sInternData->pfnFrameErrIrqCb != NULL) + { + pstcI2sInternData->pfnFrameErrIrqCb(); + } + + } + + if (1u == pstcI2s->STATUS_f.TXUDR1) // TX FIFO underflow at the frame start + { + pstcI2s->STATUS_f.TXUDR1 = 0u; + + if (pstcI2sInternData->pfnTxFifoUnderflow1IrqCb != NULL) + { + pstcI2sInternData->pfnTxFifoUnderflow1IrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.TXUDR0) // TX FIFO underflow during frame transmission + { + pstcI2s->STATUS_f.TXUDR0 = 0u; + + if (pstcI2sInternData->pfnTxFifoUnderflow0IrqCb != NULL) + { + pstcI2sInternData->pfnTxFifoUnderflow0IrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.TXOVR) // TX FIFO overflow + { + pstcI2s->STATUS_f.TXOVR = 0u; + + if (pstcI2sInternData->pfnTxFifoOverflowIrqCb != NULL) + { + pstcI2sInternData->pfnTxFifoOverflowIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.RXUDR) // RX FIFO underflow + { + pstcI2s->STATUS_f.RXUDR = 0u; + + if (pstcI2sInternData->pfnRxFifoUnderflowIrqCb != NULL) + { + pstcI2sInternData->pfnRxFifoUnderflowIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.RXOVR) // RX FIFO underflow + { + pstcI2s->STATUS_f.RXOVR = 0u; + + if (pstcI2sInternData->pfnRxFifoOverflowIrqCb != NULL) + { + pstcI2sInternData->pfnRxFifoOverflowIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.EOPI) // RX FIFO idle + { + pstcI2s->STATUS_f.EOPI = 0u; + + if (pstcI2sInternData->pfnRxFifoIdleDetectIrqCb != NULL) + { + pstcI2sInternData->pfnRxFifoIdleDetectIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.RXFI) // RX FIFO count match with RX FIFO threshold value + { + if (pstcI2sInternData->pfnRxFifoIrqCb != NULL) + { + pstcI2sInternData->pfnRxFifoIrqCb(); + } + } + + if (1u == pstcI2s->STATUS_f.TXFI) // TX FIFO empty slot match with TX FIFO threshold value + { + if (pstcI2sInternData->pfnTxFifoIrqCb != NULL) + { + pstcI2sInternData->pfnTxFifoIrqCb(); + } + } + + return; +} // I2sIrqHandler + +/** + ****************************************************************************** + ** \brief Enable I2S interrupts + ** + ** \param [in] pstcI2s Pointer to I2S instance + ** \param [in] enIrqSel I2S interrupt selection + ** \arg I2sTxFifoUnderflow0Irq TX FIFO underflow interrupt 0 + ** \arg I2sTxFifoUnderflow1Irq TX FIFO underflow interrupt 1 + ** \arg I2sTxBlockSizeErrIrq DMA TX channel block error interrupt + ** \arg I2sFrameErrIrq Frame error interrupt + ** \arg I2sTxFifoOverflowIrq TX FIFO overflow interrupt + ** \arg I2sTxFifoIrq TX FIFO interrupt + ** \arg I2sRxBlockSizeErrIrq DMA RX channel block error interrupt + ** \arg I2sRxFifoIdleDetectIrq RX FIFO idle interrupt + ** \arg I2sRxFifoUnderflowIrq RX FIFO underflow interrupt + ** \arg I2sRxFifoOverflowIrq RX FIFO overflow interrupt + ** \arg I2sRxFifoIrq RX FIFO interrupt + ** + ** \retval Ok Interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2s == NULL + ** + ******************************************************************************/ +en_result_t I2s_EnableIrq(volatile stc_i2sn_t* pstcI2s, + en_i2s_irq_sel_t enIrqSel) +{ + stc_i2s_intern_data_t* pstcI2sInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcI2sInternData = I2sGetInternDataPtr(pstcI2s); + + if (NULL == pstcI2sInternData) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case I2sTxFifoUnderflow0Irq: + pstcI2s->INTCNT_f.TXUD0M = 0u; + break; + case I2sTxFifoUnderflow1Irq: + pstcI2s->INTCNT_f.TXUD1M = 0u; + break; + case I2sTxBlockSizeErrIrq: + pstcI2s->INTCNT_f.TBERM = 0u; + break; + case I2sFrameErrIrq: + pstcI2s->INTCNT_f.FERRM = 0u; + break; + case I2sTxFifoOverflowIrq: + pstcI2s->INTCNT_f.TXOVM = 0u; + break; + case I2sTxFifoIrq: + pstcI2s->INTCNT_f.TXFIM = 0u; + break; + case I2sRxBlockSizeErrIrq: + pstcI2s->INTCNT_f.RBERM = 0u; + break; + case I2sRxFifoIdleDetectIrq: + pstcI2s->INTCNT_f.EOPM = 0u; + break; + case I2sRxFifoUnderflowIrq: + pstcI2s->INTCNT_f.RXUDM = 0u; + break; + case I2sRxFifoOverflowIrq: + pstcI2s->INTCNT_f.RXOVM = 0u; + break; + case I2sRxFifoIrq: + pstcI2s->INTCNT_f.RXFIM = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable I2S interrupts + ** + ** \param [in] pstcI2s Pointer to I2S instance + ** \param [in] enIrqSel I2S interrupt selection + ** \arg I2sTxFifoUnderflow0Irq TX FIFO underflow interrupt 0 + ** \arg I2sTxFifoUnderflow1Irq TX FIFO underflow interrupt 1 + ** \arg I2sTxBlockSizeErrIrq DMA TX channel block error interrupt + ** \arg I2sFrameErrIrq Frame error interrupt + ** \arg I2sTxFifoOverflowIrq TX FIFO overflow interrupt + ** \arg I2sTxFifoIrq TX FIFO interrupt + ** \arg I2sRxBlockSizeErrIrq DMA RX channel block error interrupt + ** \arg I2sRxFifoIdleDetectIrq RX FIFO idle interrupt + ** \arg I2sRxFifoUnderflowIrq RX FIFO underflow interrupt + ** \arg I2sRxFifoOverflowIrq RX FIFO overflow interrupt + ** \arg I2sRxFifoIrq RX FIFO interrupt + ** + ** \retval Ok Interrupts has been disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2s == NULL + ** + ******************************************************************************/ +en_result_t I2s_DisableIrq(volatile stc_i2sn_t* pstcI2s, + en_i2s_irq_sel_t enIrqSel) +{ + stc_i2s_intern_data_t* pstcI2sInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcI2sInternData = I2sGetInternDataPtr(pstcI2s); + + if (NULL == pstcI2sInternData) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case I2sTxFifoUnderflow0Irq: + pstcI2s->INTCNT_f.TXUD0M = 1u; + break; + case I2sTxFifoUnderflow1Irq: + pstcI2s->INTCNT_f.TXUD1M = 1u; + break; + case I2sTxBlockSizeErrIrq: + pstcI2s->INTCNT_f.TBERM = 1u; + break; + case I2sFrameErrIrq: + pstcI2s->INTCNT_f.FERRM = 1u; + break; + case I2sTxFifoOverflowIrq: + pstcI2s->INTCNT_f.TXOVM = 1u; + break; + case I2sTxFifoIrq: + pstcI2s->INTCNT_f.TXFIM = 1u; + break; + case I2sRxBlockSizeErrIrq: + pstcI2s->INTCNT_f.RBERM = 1u; + break; + case I2sRxFifoIdleDetectIrq: + pstcI2s->INTCNT_f.EOPM = 1u; + break; + case I2sRxFifoUnderflowIrq: + pstcI2s->INTCNT_f.RXUDM = 1u; + break; + case I2sRxFifoOverflowIrq: + pstcI2s->INTCNT_f.RXOVM = 1u; + break; + case I2sRxFifoIrq: + pstcI2s->INTCNT_f.RXFIM = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on I2S instance + ** + ** \param pstcI2s Pointer to I2S instance + ** + ******************************************************************************/ +static void I2sInitNvic(volatile stc_i2sn_t* pstcI2s) +{ + NVIC_ClearPendingIRQ(PCRC_I2S0_1_IRQn); + NVIC_EnableIRQ(PCRC_I2S0_1_IRQn); + NVIC_SetPriority(PCRC_I2S0_1_IRQn, PDL_IRQ_LEVEL_I2S_PCRC); +} // I2s_InitNvic + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on I2S instance + ** + ** \param pstcI2s Pointer to I2S instance + ** + ******************************************************************************/ +static void I2sDeInitNvic(volatile stc_i2sn_t* pstcI2s) +{ + NVIC_ClearPendingIRQ(PCRC_I2S0_1_IRQn); + NVIC_DisableIRQ(PCRC_I2S0_1_IRQn); + NVIC_SetPriority(PCRC_I2S0_1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +} // I2sDeInitNvic +#endif // #if (PDL_INTERRUPT_ENABLE_I2S0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_I2S1 == PDL_ON) + +/** + ***************************************************************************** + ** \brief This function initialises the I2S PLL clock according to the given + ** parameters. + ** + ** \attention The clock parameters are only valid for 19.2 MHz main clock + ** + ** To reset and disable the I2S clock module the function I2s_DeInitClk() + ** has to be used. + ** + ** \param [in] pstcConfig Pointer to I2S clock configuration parameters + ** + ** \return - Ok on successful clock init + ** - ErrorInvalidParameter wrong enumerator used + ** - ErrorTimeout Clock off or PLL wait too long + *****************************************************************************/ +en_result_t I2s_InitClk(stc_i2s_clk_config_t* pstcConfig) +{ + uint32_t u32TimeOut = SystemCoreClock/1000; + + // Clock off + FM_I2SPRE->ICCR_f.I2SEN = 0u; + + // Wait for clock off + while((0u != u32TimeOut) && (1u == FM_I2SPRE->ICCR_f.I2SEN)) + { + u32TimeOut--; + } + + // Too long waited? + if (0u == u32TimeOut) + { + return ErrorTimeout; + } + + // Switch off PLL + FM_I2SPRE->IPCR1_f.IPLLEN = 0u; + + // Set PLL wait time + switch (pstcConfig->enI2sPllWaitTime) + { + case I2sPllWait26us: // 26 us + FM_I2SPRE->IPCR2_f.IPOWT = 0u; + break; + case I2sPllWait53us: // 53 us + FM_I2SPRE->IPCR2_f.IPOWT = 1u; + break; + case I2sPllWait106us: // 106 us + FM_I2SPRE->IPCR2_f.IPOWT = 2u; + break; + case I2sPllWait213us: // 213 us + FM_I2SPRE->IPCR2_f.IPOWT = 3u; + break; + case I2sPllWait426us: // 426 us + FM_I2SPRE->IPCR2_f.IPOWT = 4u; + break; + case I2sPllWait853us: // 853 us + FM_I2SPRE->IPCR2_f.IPOWT = 5u; + break; + case I2sPllWait1ms70: // 1.70 ms + FM_I2SPRE->IPCR2_f.IPOWT = 6u; + break; + case I2sPllWait3ms41: // 3.41 ms + FM_I2SPRE->IPCR2_f.IPOWT = 7u; + break; + default: + return ErrorInvalidParameter; + } + + // Set clock frequency + FM_I2SPRE->IPCR3_f.IPLLK = pstcConfig->u8Pllk - 1u; + FM_I2SPRE->IPCR4_f.IPLLN = pstcConfig->u8Plln - 1u; + FM_I2SPRE->IPCR5_f.IPLLM = pstcConfig->u8Pllm - 1u; + + FM_I2SPRE->IPINT_ENR_f.IPCSE = 0u; // No interrupt used + +#if (PDL_PERIPHERAL_ENABLE_I2S0) + // Set I2S ch.0 clock input + switch (pstcConfig->enI2s0ClkIn) + { + case I2s0UsePllClk: + FM_I2SPRE->ICCR_f.ICSEL = 0u; + break; + case I2s0UseI2sMclki: + FM_I2SPRE->ICCR_f.ICSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } +#endif + + +#if (PDL_PERIPHERAL_ENABLE_I2S1) + // Set I2S ch.1 clock input + switch (pstcConfig->enI2s1ClkIn) + { + case I2s1UsePllClk: + FM_I2SPRE->ICCR1_f.ICSEL1 = 0u; + break; + case I2s1UseI2sMclki: + FM_I2SPRE->ICCR1_f.ICSEL1 = 1u; + break; + case I2s1UseI2sMclki1: + FM_I2SPRE->ICCR1_f.ICSEL1 = 3u; + break; + default: + return ErrorInvalidParameter; + } +#endif + + return Ok; +} // I2s_InitClk() + +/** + ***************************************************************************** + ** \brief This function de-initialises the I2S PLL clock and reset its + ** registers. + ** + ** \return Ok on successful clock de-init + *****************************************************************************/ +en_result_t I2s_DeInitClk(void) +{ + // Clock off + FM_I2SPRE->ICCR = 0u; +#if(defined(FM_I2SPRE_ICCR1)) + FM_I2SPRE->ICCR_1 = 0u; +#endif + + // PLL off + FM_I2SPRE->IPCR1_f.IPLLEN = 0u; + + // Switch off interrupts + FM_I2SPRE->IPINT_ENR_f.IPCSE = 0u; + + // Set PLL registers to default values + FM_I2SPRE->IPCR3_f.IPLLK = 0x01u; + FM_I2SPRE->IPCR4_f.IPLLN = 0x1Fu; + FM_I2SPRE->IPCR5_f.IPLLM = 0x18u; +#if defined(FM_I2SPRE_IPCR5_1) + FM_I2SPRE->IPCR5_1_f.IPLLM1 = 0x18u; +#endif + + // Clear PLL stabilization wait time register + FM_I2SPRE->IPCR2_f.IPOWT = 0u; + + return Ok; +} // I2s_DeInitClk() + +/** + ***************************************************************************** + ** \brief This function enables I2S PLL + ** + ** \note This function can be used for polling if the input parameter is true + ** and returns directly after enable PLL. + ** + ** \return - Ok I2S PLL is enabled + ** - ErrorTimeout I2S PLL is timeout + *****************************************************************************/ +en_result_t I2s_EnablePll(boolean_t bWaitPolling) +{ + uint32_t u32TimeOut; + + u32TimeOut = SystemCoreClock/1000u; + + // Enable PLL + FM_I2SPRE->IPCR1_f.IPLLEN = 1u; + + if (bWaitPolling == TRUE) + { + // Wait for PLL stabilization + while((0u != u32TimeOut) && (0u == FM_I2SPRE->IP_STR_f.IPRDY)) + { + u32TimeOut--; + } + + // Too long waited? + if (0u == u32TimeOut) + { + // Disable PLL + FM_I2SPRE->IPCR1_f.IPLLEN = 0u; + + return ErrorTimeout; + } + } + + return Ok; +} + +/** + ***************************************************************************** + ** \brief This function disables I2S PLL + ** + ** \return - Ok I2S PLL is disable + *****************************************************************************/ +en_result_t I2s_DisablePll(void) +{ + // Disable PLL + FM_I2SPRE->IPCR1_f.IPLLEN = 0u; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief This function checks, if the PLL has stabilized. + ** + ** \pre I2s_InitClk() has to be called before. + ** + ** \note This function can be used for polling, if the PLL has stabilized and + ** in I2s_InitClk() the waiting was disabled + ** + ** \return - Ok PLL is stabilized + ** - ErrorNotReady PLL is not stabilized + *****************************************************************************/ +en_result_t I2s_CheckPllReady(void) +{ + if (1u == FM_I2SPRE->IP_STR_f.IPRDY) + { + return Ok; + } + + return ErrorNotReady; +} // I2s_PllReady() + +/** + ***************************************************************************** + ** \brief This function starts the I2S clock. + *****************************************************************************/ +void I2s_StartClk(volatile stc_i2sn_t* pstcI2s) +{ +#if (PDL_PERIPHERAL_ENABLE_I2S0) + if(&I2S0 == pstcI2s) + { + FM_I2SPRE->ICCR_f.I2SEN = 1u; + } +#endif + +#if (PDL_PERIPHERAL_ENABLE_I2S1) + if(&I2S1 == pstcI2s) + { + FM_I2SPRE->ICCR1_f.I2SEN1 = 1u; + } +#endif +} // I2s_StartClk() + +/** + ***************************************************************************** + ** \brief This function stops the I2S clock. + *****************************************************************************/ +void I2s_StopClk(volatile stc_i2sn_t* pstcI2s) +{ +#if (PDL_PERIPHERAL_ENABLE_I2S0) + if(&I2S0 == pstcI2s) + { + FM_I2SPRE->ICCR_f.I2SEN = 0u; + } +#endif + +#if (PDL_PERIPHERAL_ENABLE_I2S1) + else if(&I2S1 == pstcI2s) + { + FM_I2SPRE->ICCR1_f.I2SEN1 = 0u; + } +#endif +} // I2s_StopClk() + +/** + ***************************************************************************** + ** This function initialises one specific I2S module with the parameters + ** provided in the given configuration structure. + ** After successful initialization the I2S module is ready to use. + ** + ** I2S_Init() has to be called with the parameter pstcConfig of type + ** stc_i2s_config_t, the basic I2S settings automatic retransmission, the I2s + ** baudrate, and the error and status callback function can be set. + ** + ** All values in pstcConfig have to be in valid range (see i2s.h for allowed + ** ranges of dedicated parameters). The error and status change callback + ** functions can be NULL. In this case no information of error or status + ** changes will be reported to the user application. + ** + ** To reset and disable the I2S module the function I2s_DeInit() has to be used. + ** + ** \param [in] pstcI2s Pointer to I2S instance + ** \param [in] pstcConfig Pointer to I2S configuration parameters + ** + ** \return - Ok on successful init + ** - ErrorInvalidParameter if bit rate is 0 or pointers are NULL + *****************************************************************************/ +en_result_t I2s_Init(volatile stc_i2sn_t* pstcI2s, const stc_i2s_config_t* pstcConfig) +{ + stc_i2s_intern_data_t* pstcI2sInterndata; + + if((NULL == pstcI2s) || (NULL == pstcConfig)) + { + return ErrorInvalidParameter; + } + + // Get the poitner of intern structure + pstcI2sInterndata = I2sGetInternDataPtr(pstcI2s); + + if(NULL == pstcI2sInterndata) + { + return ErrorInvalidParameter; + } + + // Disable I2C channel for configuration + pstcI2s->OPRREG_f.START = 0u ; + + // Clock divider configuration + pstcI2s->CNTREG_f.CKRT = pstcConfig->u8ClockDiv ; + // Number of overhead bits in corresponding sub frame channel + pstcI2s->CNTREG_f.OVHD = pstcConfig->u16OverheadBits ; + // Output data in case of Invalid/Empty Frame + pstcI2s->CNTREG_f.MSKB = pstcConfig->bMaskBit ; + // Master - Slave configuration + pstcI2s->CNTREG_f.MSMD = pstcConfig->bMasterMode ; + // Number of Subframe constructions + pstcI2s->CNTREG_f.SBFN = pstcConfig->bSubFrame01 ; + // Word construction of FIFO (one 32bit word or two 16bit half words + pstcI2s->CNTREG_f.RHLL = pstcConfig->bFifoTwoWords ; + // Clock source selector (internal clock CLK_PERI4_PD2 or external clock ECLK) + pstcI2s->CNTREG_f.ECKM = pstcConfig->bBclkDivByMclk ; + // Bit extension + pstcI2s->CNTREG_f.BEXT = pstcConfig->bBitExtensionHigh ; + // Output Mode of Frame Synchronous Signal + pstcI2s->CNTREG_f.FRUN = pstcConfig->bFreeRunMode ; + // Shifting order + pstcI2s->CNTREG_f.MLSB = pstcConfig->bLsbFirst ; + // Sampling point of data reception + pstcI2s->CNTREG_f.SMPL = pstcConfig->bSampleAtEnd ; + // Clock polarity + pstcI2s->CNTREG_f.CPOL = pstcConfig->bClockpolarity ; + // Frame Sync Phase + pstcI2s->CNTREG_f.FSPH = pstcConfig->bWordSelectSamePhase ; + // Frame Sync Pulse Width + pstcI2s->CNTREG_f.FSLN = pstcConfig->bWordSelectLength ; + // Frame Sync Polarity + pstcI2s->CNTREG_f.FSPL = pstcConfig->bWordSelectPolarity ; + + // Configuration for Sub Frame 0 + pstcI2s->MCR0REG_f.S0CHN = pstcConfig->stcSubframe0.u8Snchn ; + pstcI2s->MCR0REG_f.S0CHL = pstcConfig->stcSubframe0.u8Snchl ; + pstcI2s->MCR0REG_f.S0WDL = pstcConfig->stcSubframe0.u8Snwdl ; + + // Configuration for Sub Frame 1 + pstcI2s->MCR0REG_f.S1CHN = pstcConfig->stcSubframe1.u8Snchn ; + pstcI2s->MCR0REG_f.S1CHL = pstcConfig->stcSubframe1.u8Snchl ; + pstcI2s->MCR0REG_f.S1WDL = pstcConfig->stcSubframe1.u8Snwdl ; + + // Set active channels for Sub Frame 0 + pstcI2s->MCR1REG = pstcConfig->u32S0ch ; + // Set active channels for Sub Frame 1 + pstcI2s->MCR2REG = pstcConfig->u32S1ch ; + + // Set DMA enable + pstcI2s->INTCNT_f.TXFDM = (TRUE == pstcConfig->bTxDmaEnable) ? 0u : 1u ; + pstcI2s->INTCNT_f.RXFDM = (TRUE == pstcConfig->bRxDmaEnable) ? 0u : 1u ; + + // FIFO thresholds + pstcI2s->INTCNT_f.TFTH = 0x0F & (pstcConfig->u8TxFifoThreshold); + pstcI2s->INTCNT_f.RFTH = 0x0F & (pstcConfig->u8RxFifoThreshold); + + // Packet receive completion timer + switch (pstcConfig->enPacketReceiveCompletionTimer) + { + case NoOperation: + pstcI2s->INTCNT_f.RPTMR = 0x0; + break; + case Hclk54000Cycles: + pstcI2s->INTCNT_f.RPTMR = 0x1; + break; + case Hclk108000Cycles: + pstcI2s->INTCNT_f.RPTMR = 0x2; + break; + case Hclk216000Cycles: + pstcI2s->INTCNT_f.RPTMR = 0x3; + break; + default: + return ErrorInvalidParameter ; + } + +#if (PDL_INTERRUPT_ENABLE_I2S0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_I2S1 == PDL_ON) + // Set interrupt enable + if (pstcConfig->pstcIrqEn != NULL) + { + pstcI2s->INTCNT_f.TXUD0M = (TRUE == pstcConfig->pstcIrqEn->bTxFifoUnderflow0Irq) ? 0u : 1u ; + pstcI2s->INTCNT_f.TXUD1M = (TRUE == pstcConfig->pstcIrqEn->bTxFifoUnderflow1Irq) ? 0u : 1u ; + pstcI2s->INTCNT_f.TBERM = (TRUE == pstcConfig->pstcIrqEn->bTxBlockSizeErrIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.FERRM = (TRUE == pstcConfig->pstcIrqEn->bFrameErrIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.TXOVM = (TRUE == pstcConfig->pstcIrqEn->bTxFifoOverflowIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.TXFIM = (TRUE == pstcConfig->pstcIrqEn->bTxFifoIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.RBERM = (TRUE == pstcConfig->pstcIrqEn->bRxBlockSizeErrIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.RXUDM = (TRUE == pstcConfig->pstcIrqEn->bRxFifoUnderflowIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.RXOVM = (TRUE == pstcConfig->pstcIrqEn->bRxFifoOverflowIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.EOPM = (TRUE == pstcConfig->pstcIrqEn->bRxFifoIdleDetectIrq) ? 0u : 1u ; + pstcI2s->INTCNT_f.RXFIM = (TRUE == pstcConfig->pstcIrqEn->bRxFifoIrq) ? 0u : 1u ; + } + + // Set interrupt callback funcitons + if (pstcConfig->pstcIrqCb != NULL) + { + pstcI2sInterndata->pfnTxFifoUnderflow0IrqCb = pstcConfig->pstcIrqCb->pfnTxFifoUnderflow0IrqCb; + pstcI2sInterndata->pfnTxFifoUnderflow1IrqCb = pstcConfig->pstcIrqCb->pfnTxFifoUnderflow1IrqCb; + pstcI2sInterndata->pfnTxBlockSizeErrIrqCb = pstcConfig->pstcIrqCb->pfnTxBlockSizeErrIrqCb; + pstcI2sInterndata->pfnFrameErrIrqCb = pstcConfig->pstcIrqCb->pfnFrameErrIrqCb; + pstcI2sInterndata->pfnTxFifoOverflowIrqCb = pstcConfig->pstcIrqCb->pfnTxFifoOverflowIrqCb; + pstcI2sInterndata->pfnTxFifoIrqCb = pstcConfig->pstcIrqCb->pfnTxFifoIrqCb; + pstcI2sInterndata->pfnRxBlockSizeErrIrqCb = pstcConfig->pstcIrqCb->pfnRxBlockSizeErrIrqCb; + pstcI2sInterndata->pfnRxFifoUnderflowIrqCb = pstcConfig->pstcIrqCb->pfnRxFifoUnderflowIrqCb; + pstcI2sInterndata->pfnRxFifoOverflowIrqCb = pstcConfig->pstcIrqCb->pfnRxFifoOverflowIrqCb; + pstcI2sInterndata->pfnRxFifoIdleDetectIrqCb = pstcConfig->pstcIrqCb->pfnRxFifoIdleDetectIrqCb; + pstcI2sInterndata->pfnRxFifoIrqCb = pstcConfig->pstcIrqCb->pfnRxFifoIrqCb; + } + + if (pstcConfig->bTouchNvic == TRUE) + { + I2sInitNvic(pstcI2s); + } +#endif + + // Enable I2S Transmitter + pstcI2s->OPRREG_f.TXENB = (FALSE == pstcConfig->bTxEnable) ? 0u : 1u ; + pstcI2s->CNTREG_f.TXDIS = (FALSE == pstcConfig->bTxEnable) ? 1u : 0u ; + + // Enable I2S Receiver + pstcI2s->OPRREG_f.RXENB = (FALSE == pstcConfig->bRxEnable) ? 0u : 1u ; + pstcI2s->CNTREG_f.RXDIS = (FALSE == pstcConfig->bRxEnable) ? 1u : 0u ; + + + return Ok ; +} // I2S_Init + +/** + ***************************************************************************** + ** \brief Deinitializes the I2S module. + ** + ** Any pending transmission or reception will be aborted and all I2S related + ** registers are reset to their default values. + ** + ** \param [in] pstcI2s Pointer to I2S instance + ** \param [in] bTouchNvic TRUE = De-Init NVIC + ** + ** \retval Ok I2S module has been successfully deinitialized + ** \retval ErrorInvalidParameter If one of the following conditions are met: + ** - FM4_I2S0 == NULL + ** - FM4_I2S0InternData == NULL (invalid or disabled I2S unit + *****************************************************************************/ +en_result_t I2s_DeInit(volatile stc_i2sn_t* pstcI2s, boolean_t bTouchNvic) +{ + stc_i2s_intern_data_t* pstcI2sInterndata; + + // Get the poitner of intern structure + pstcI2sInterndata = I2sGetInternDataPtr(pstcI2s); + + if(NULL == pstcI2sInterndata) + { + return ErrorInvalidParameter ; + } + + // Disable I2S channel for configuration + pstcI2s->OPRREG_f.START = 0u ; + + // Reset CNTREG bitfields to initial values + pstcI2s->CNTREG = 0u ; + + // Reset MCR0REG bitfields to initial values + pstcI2s->MCR0REG = 0u; + + // Disable all channels for Sub Frame 0 + pstcI2s->MCR1REG = 0u ; + + // Disable all channels for Sub Frame 1 + pstcI2s->MCR2REG = 0u ; + + // Finally reset I2S hardware + pstcI2s->SRST_f.SRST = 1u ; + +#if (PDL_INTERRUPT_ENABLE_I2S0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_I2S1 == PDL_ON) + pstcI2sInterndata->pfnTxFifoUnderflow0IrqCb = NULL; + pstcI2sInterndata->pfnTxFifoUnderflow1IrqCb = NULL; + pstcI2sInterndata->pfnTxBlockSizeErrIrqCb = NULL; + pstcI2sInterndata->pfnFrameErrIrqCb = NULL; + pstcI2sInterndata->pfnTxFifoOverflowIrqCb = NULL; + pstcI2sInterndata->pfnTxFifoIrqCb = NULL; + pstcI2sInterndata->pfnRxBlockSizeErrIrqCb = NULL; + pstcI2sInterndata->pfnRxFifoUnderflowIrqCb = NULL; + pstcI2sInterndata->pfnRxFifoOverflowIrqCb = NULL; + pstcI2sInterndata->pfnRxFifoIdleDetectIrqCb = NULL; + pstcI2sInterndata->pfnRxFifoIrqCb = NULL; + + if (TRUE == bTouchNvic) + { + I2sDeInitNvic(pstcI2s); + } +#endif + + return Ok ; +} // I2S_DeInit + +/** + ***************************************************************************** + ** \brief Start I2S + ** + ** \retval Ok I2S module has been started + *****************************************************************************/ +en_result_t I2s_Start(volatile stc_i2sn_t* pstcI2s) +{ + pstcI2s->OPRREG_f.START = 1u ; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Stop I2S + ** + ** \retval Ok I2S module has been stopped + *****************************************************************************/ +en_result_t I2s_Stop(volatile stc_i2sn_t* pstcI2s) +{ + pstcI2s->OPRREG_f.START = 0u ; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Reset I2S + ** + ** \retval Ok I2S module has been stopped + *****************************************************************************/ +en_result_t I2s_Reset(volatile stc_i2sn_t* pstcI2s) +{ + pstcI2s->SRST_f.SRST = 1u ; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Enable I2S TX + ** + ** \retval Ok I2S module has been stopped + *****************************************************************************/ +en_result_t I2s_EnableTx(volatile stc_i2sn_t* pstcI2s) +{ + // Enable I2S Transmitter + pstcI2s->OPRREG_f.TXENB = 1u;; + pstcI2s->CNTREG_f.TXDIS = 0u ; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Disable I2S TX + ** + ** \retval Ok I2S module has been stopped + *****************************************************************************/ +en_result_t I2s_DisableTx(volatile stc_i2sn_t* pstcI2s) +{ + // Enable I2S Transmitter + pstcI2s->OPRREG_f.TXENB = 0u;; + pstcI2s->CNTREG_f.TXDIS = 1u ; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Enable I2S RX + ** + ** \retval Ok I2S module has been stopped + *****************************************************************************/ +en_result_t I2s_EnableRx(volatile stc_i2sn_t* pstcI2s) +{ + // Enable I2S Receiver + pstcI2s->OPRREG_f.RXENB = 1u; + pstcI2s->CNTREG_f.RXDIS = 0u; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Disable I2S RX + ** + ** \retval Ok I2S module has been stopped + *****************************************************************************/ +en_result_t I2s_DisableRx(volatile stc_i2sn_t* pstcI2s) +{ + // Enable I2S Receiver + pstcI2s->OPRREG_f.RXENB = 0u; + pstcI2s->CNTREG_f.RXDIS = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get status of I2S according to status type + ** + ** \param [in] pstcI2s Pointer to I2S instance + ** \param [in] enStatus I2S status type + ** \arg I2sDmaTxChBlockSizeErr DMA transmit channel block size error + ** \arg I2sDmaRxChBlockSizeErr DMA receive channel block size error + ** \arg I2sFrameErr Frame error + ** \arg I2sTxFifoUnderflow1 TX FIFO underflow interrupt flag 1 + ** \arg I2sTxFifoUnderflow0 TX FIFO underflow interrupt flag 0 + ** \arg I2sTxFifoOverflow TX FIFO overflow interrupt flag + ** \arg I2sRxFifoUnderflow RX FIFO underflow interrupt flag + ** \arg I2sRxFifoOverflow RX FIFO overflow interrupt flag + ** \arg I2sRxFifoFifoIdle RX FIFO idle interrupt flag + ** \arg I2sBusy I2S transmit busy status + ** \arg I2sTxFifoMatchThreshold TX FIFO interrupt flag + ** \arg I2sRxFifoMatchThreshold RX FIFO interrupt flag + ** + ** \retval FALSE If one of following conditions are met: + ** - Block size of the DMA transmit channel is set to a value smaller than the transmit FIFO threshold value [enStatus = I2sDmaTxChBlockSizeErr] + ** - Block size of the DMA receive channel is set to a value larger than the receive FIFO threshold value [enStatus = I2sDmaRxChBlockSizeErr] + ** - Frame sync signal is received at the frame rate that was set. [enStatus = I2sFrameErr] + ** - Transmit FIFO don't underflow at the frame start [enStatus = I2sTxFifoUnderflow1] + ** - Transmit FIFO don't underflow during frame transmission [enStatus = I2sTxFifoUnderflow0] + ** - Transmit FIFO don't overflow [enStatus = I2sTxFifoOverflow] + ** - Receive FIFO don't underflow [enStatus = I2sRxFifoUnderflow] + ** - Receive FIFO don't overflow [enStatus = I2sRxFifoOverflow] + ** - Receive FIFO is empty when the timer reaches the time that was set [enStatus = I2sRxFifoFifoIdle] + ** - Serial transmit control unit is not busy. [enStatus =I2sBusy] + ** - Transmit FIFO empty slot is less than the TX FIFO threshold value [enStatus = I2sTxFifoMatchThreshold] + ** - Receive FIFO data count is less than the RX FIFO threshold value [enStatus = I2sRxFifoMatchThreshold] + ** \retval TRUE If one of following conditions are met: + ** - Block size of the DMA transmit channel is set to a value larger than the transmit FIFO threshold value [enStatus = I2sDmaTxChBlockSizeErr] + ** - Block size of the DMA receive channel is set to a value larger than the receive FIFO threshold value [enStatus = I2sDmaRxChBlockSizeErr] + ** - Frame sync signal cannot be received at the frame rate that was set. [enStatus = I2sFrameErr] + ** - Transmit FIFO underflows at the frame start [enStatus = I2sTxFifoUnderflow1] + ** - Transmit FIFO underflows during frame transmission [enStatus = I2sTxFifoUnderflow0] + ** - Transmit FIFO overflows [enStatus = I2sTxFifoOverflow] + ** - Receive FIFO underflows [enStatus = I2sRxFifoUnderflow] + ** - Receive FIFO overflows [enStatus = I2sRxFifoOverflow] + ** - Receive FIFO is not empty when the timer reaches the time that was set [enStatus = I2sRxFifoFifoIdle] + ** - Serial transmit control unit is busy. [enStatus =I2sBusy] + ** - Transmit FIFO empty slot meets or exceeds the TX FIFO threshold value [enStatus = I2sTxFifoMatchThreshold] + ** - Receive FIFO data count meets or exceeds the RX FIFO threshold value [enStatus = I2sRxFifoMatchThreshold] + ** + ******************************************************************************/ +boolean_t I2s_GetStatus(volatile stc_i2sn_t* pstcI2s, + en_i2s_status_t enStatus) +{ + boolean_t bRet = FALSE; + + switch(enStatus) + { + case I2sDmaTxChBlockSizeErr: + bRet = (1u == pstcI2s->STATUS_f.TBERR) ? TRUE : FALSE; + break; + case I2sDmaRxChBlockSizeErr: + bRet = (1u == pstcI2s->STATUS_f.RBERR) ? TRUE : FALSE; + break; + case I2sFrameErr: + bRet = (1u == pstcI2s->STATUS_f.FERR) ? TRUE : FALSE; + break; + case I2sTxFifoUnderflow1: + bRet = (1u == pstcI2s->STATUS_f.TXUDR1) ? TRUE : FALSE; + break; + case I2sTxFifoUnderflow0: + bRet = (1u == pstcI2s->STATUS_f.TXUDR0) ? TRUE : FALSE; + break; + case I2sTxFifoOverflow: + bRet = (1u == pstcI2s->STATUS_f.TXOVR) ? TRUE : FALSE; + break; + case I2sRxFifoUnderflow: + bRet = (1u == pstcI2s->STATUS_f.RXUDR) ? TRUE : FALSE; + break; + case I2sRxFifoOverflow: + bRet = (1u == pstcI2s->STATUS_f.RXUDR) ? TRUE : FALSE; + break; + case I2sRxFifoFifoIdle: + bRet = (1u == pstcI2s->STATUS_f.EOPI) ? TRUE : FALSE; + break; + case I2sBusy: + bRet = (1u == pstcI2s->STATUS_f.BSY) ? TRUE : FALSE; + break; + case I2sTxFifoMatchThreshold: + bRet = (1u == pstcI2s->STATUS_f.RXUDR) ? TRUE : FALSE; + break; + case I2sRxFifoMatchThreshold: + bRet = (1u == pstcI2s->STATUS_f.RXUDR) ? TRUE : FALSE; + break; + default: + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear status of I2S according to status type + ** + ** \param [in] pstcI2s Pointer to I2S instance + ** \param [in] enStatus I2S status type + ** \arg I2sDmaTxChBlockSizeErr DMA transmit channel block size error + ** \arg I2sDmaRxChBlockSizeErr DMA receive channel block size error + ** \arg I2sFrameErr Frame error + ** \arg I2sTxFifoUnderflow1 TX FIFO underflow interrupt flag 1 + ** \arg I2sTxFifoUnderflow0 TX FIFO underflow interrupt flag 0 + ** \arg I2sTxFifoOverflow TX FIFO overflow interrupt flag + ** \arg I2sRxFifoUnderflow RX FIFO underflow interrupt flag + ** \arg I2sRxFifoOverflow RX FIFO overflow interrupt flag + ** \arg I2sRxFifoFifoIdle RX FIFO idle interrupt flag + ** \arg I2sBusy I2S transmit busy status + ** \arg I2sTxFifoMatchThreshold TX FIFO interrupt flag + ** \arg I2sRxFifoMatchThreshold RX FIFO interrupt flag + ** + ** \retval Ok The status is cleared + ** \retval ErrorInvalidParameter pstcI2s == NULL or invalid value of enStatus + ** + ** \note The following status is cleared by hardware automatically: + ** - I2sDmaTxChBlockSizeErr + ** - I2sDmaRxChBlockSizeErr + ** - I2sBusy + ** - I2sTxFifoMatchThreshold + ** - I2sRxFifoMatchThreshold + ** + ******************************************************************************/ +en_result_t I2s_ClrStatus(volatile stc_i2sn_t* pstcI2s, + en_i2s_status_t enStatus) +{ + if(pstcI2s == NULL) + { + return ErrorInvalidParameter; + } + + switch(enStatus) + { + case I2sDmaTxChBlockSizeErr: + break; + case I2sDmaRxChBlockSizeErr: + break; + case I2sFrameErr: + pstcI2s->STATUS_f.FERR = 0u; + break; + case I2sTxFifoUnderflow1: + pstcI2s->STATUS_f.TXUDR1 = 0u; + break; + case I2sTxFifoUnderflow0: + pstcI2s->STATUS_f.TXUDR1 = 0u; + break; + case I2sTxFifoOverflow: + pstcI2s->STATUS_f.TXOVR = 0u; + break; + case I2sRxFifoUnderflow: + pstcI2s->STATUS_f.RXUDR = 0u; + break; + case I2sRxFifoOverflow: + pstcI2s->STATUS_f.RXUDR = 0u; + break; + case I2sRxFifoFifoIdle: + pstcI2s->STATUS_f.EOPI = 0u; + break; + case I2sBusy: + break; + case I2sTxFifoMatchThreshold: + break; + case I2sRxFifoMatchThreshold: + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Write I2S TX FIFO + ** + ** \param pstcI2s Pointer to I2S instance + ** \param u32Data Data to be written + ** + ** \retval Ok Data has been written + ** \retval ErrorInvalidParameter pstcI2s == NULL + ** + ** \note The FIFO is always written by word + *****************************************************************************/ +en_result_t I2s_WriteTxFifo(volatile stc_i2sn_t* pstcI2s, uint32_t u32Data) +{ + if (pstcI2s == NULL) + { + return ErrorInvalidParameter; + } + + pstcI2s->TXFDAT = u32Data; + + return Ok; +} + +/** + ***************************************************************************** + ** \brief Read I2S RX FIFO + ** + ** \param pstcI2s Pointer to I2S instance + ** + ** \retval The receive data in FIFO + ** + ** \note The FIFO is always read by word + *****************************************************************************/ +uint32_t I2s_ReadRxFifo(volatile stc_i2sn_t* pstcI2s) +{ + return pstcI2s->RXFDAT; +} + +/** + ***************************************************************************** + ** \brief Read I2S TX FIFO number + ** + ** \param pstcI2s Pointer to I2S instance + ** + ** \retval The transmit data in FIFO + ** + ** \note It is number of word + *****************************************************************************/ +uint8_t I2s_GetTxFifoNumber(volatile stc_i2sn_t* pstcI2s) +{ + return pstcI2s->STATUS_f.TXNUM; +} + +/** + ***************************************************************************** + ** \brief Read I2S RX FIFO number + ** + ** \param pstcI2s Pointer to I2S instance + ** + ** \retval The receive data in FIFO + ** + ** \note It is number of word + *****************************************************************************/ +uint8_t I2s_GetRxFifoNumber(volatile stc_i2sn_t* pstcI2s) +{ + return pstcI2s->STATUS_f.RXNUM; +} + +#endif + +/*****************************************************************************/ +/* EOF (not truncated) */ +/*****************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2s/i2s.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2s/i2s.h new file mode 100644 index 0000000000..a0fb9ff2b8 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/i2s/i2s.h @@ -0,0 +1,452 @@ +/******************************************************************************* +* \file i2s.h +* +* \version 1.20 +* +* \brief I2S API functions header file +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __I2S_H__ +#define __I2S_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_I2S_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupI2S Inter-IC Sound (I2S) +* \{ +* \defgroup GroupI2S_Macros Macros +* \defgroup GroupI2S_Functions Functions +* \defgroup GroupI2S_GlobalVariables Global Variables +* \defgroup GroupI2S_DataStructures Data Structures +* \defgroup GroupI2S_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupI2S +* \{ +* The Inter-IC Sound (I2S) peripheral supports this serial interface for +* digital stereo audio. The I2S interface can also transfer other serial Pulse-code +* Modulation (PCM) data by specifying the frame format. +* \note I2S is not a protocol for controlling audio codec devices by +* writing and reading registers. Codec devices that support I2S +* typically provide a separate interface for device control. +* +* The I2S peripheral has transmit and receive FIFO buffers. The buffer size changes based on operating mode:
+* - transmit-only mode (132 word × 32 bit configuration transmit FIFO) +* - receive-only mode (132 word × 32 bit configuration receive FIFO) +* - transmit/receive mode (66 word × 32 bit configuration transmit FIFO, 66 word × +* 32 bit configuration receive FIFO). +* You can use DMA, interrupts, and polling to perform internal transfers between the +* transmit and receive FIFOs and memory. +* \note FM0+ type 2 and FM4 type 5 devices support only I2S master mode. All other devices that have +* I2S support both master and slave mode. +* \section SectionI2S_ConfigurationConsideration Configuration Consideration +* Before using I2S, call Clk_PeripheralClockEnable() to set the clock for peripheral block which you use. +* See en_clk_gate_peripheral_t for choices.
+* To set up an I2S, you must configure both the clock and the I2S. You also specify which +* interrupts to enable in an stc_i2s_irq_en_t structure. Provide the required callback functions +* in an stc_i2s_irq_cb_t structure The I2S config structure has fields for the addresses of the +* enable and callback structures.
+* To configure the clock, provide configuration parameters in the stc_i2s_clk_config_t structure. +* The documentation for that structure outlines the formula that defines the clock frequency. Call +* I2s_InitClk() to initialize the clock. This does not start the clock. To reset or disable the clock, +* call . I2s_DeInitClk().
+* To set up the I2S itself, first fill in the fields for the stc_i2s_irq_en_t and +* stc_i2s_irq_cb_t structures. Configure the I2S settings in the stc_i2s_config_t structure. +* This includes the addresses of the interrupt structures. Then call I2s_Init(). +* I2s_DeInit() de-initializes an I2S instance and resets the hardware to initial values.
+* Call I2s_StartClk(), and then call I2s_Start().
+* You can then use API function calls to: +* - enable or disable transmitting +* - enable or disable receiving +* - enable or disable the PLL +* - write or read the FIFO buffer a word at a time +* - get the number of words in either the transmit or receive buffers +* - get or clear the status
+* To get or clear status, specify the particular flag or status you want. See en_i2s_status_t for choices. +* For example, use this API function call to get or clear interrupt flags. +* +* \section SectionI2S_MoreInfo More Information +* For more information on the I2S peripheral, refer to:
+* FM0+ Peripheral Manual - Communication Subsystem TRM.pdf
+* FM4 Peripheral Manual - Communication Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupI2S_Macros +* \{ +*/ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('define') */ +/*****************************************************************************/ +#define stc_i2sn_t FM_I2S_TypeDef + +#define I2S0 (*(volatile stc_i2sn_t *) FM_I2S0_BASE) +#define I2S1 (*(volatile stc_i2sn_t *) FM_I2S1_BASE) + +#define I2S_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_I2S0 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_I2S1 == PDL_ON) + +/** \} GroupI2S_Macros */ + +/** +* \addtogroup GroupI2S_Types +* \{ +*/ + +/** + ***************************************************************************** + ** \brief I2S PLL clock stabilization wait times (for 12.2 MHz input clock) + *****************************************************************************/ +typedef enum en_i2s_pll_wait_time +{ + I2sPllWait26us = 0u, ///< 26 us + I2sPllWait53us = 1u, ///< 53 us + I2sPllWait106us = 2u, ///< 106 us + I2sPllWait213us = 3u, ///< 213 us + I2sPllWait426us = 4u, ///< 426 us + I2sPllWait853us = 5u, ///< 853 us + I2sPllWait1ms70 = 6u, ///< 1.70 ms + I2sPllWait3ms41 = 7u ///< 3.41 ms +} en_i2s_pll_wait_time_t; + +/** + ***************************************************************************** + ** \brief I2S ch.0 clock selection + *****************************************************************************/ +typedef enum en_i2s0_clk_in +{ + I2s0UsePllClk = 0u, ///< Use PLL clock for I2S clock + I2s0UseI2sMclki = 1u, ///< Use MCLKI input for I2S clock + +}en_i2s0_clk_in_t; + +/** + ***************************************************************************** + ** \brief I2S ch.1 clock selection + *****************************************************************************/ +typedef enum en_i2s1_clk_in +{ + I2s1UsePllClk = 0u, ///< Use PLL clock for I2S clock + I2s1UseI2sMclki = 1u, ///< Use MCLKI input for I2S clock + I2s1UseI2sMclki1 = 2u, ///< Use MCLKI1 input for I2S clock + +}en_i2s1_clk_in_t; + +/** + ***************************************************************************** + ** \brief I2S start condition type (read, write) + *****************************************************************************/ +typedef enum en_i2s_start_condition +{ + I2sRead = 0u, ///< I2S read + I2sWrite = 1u ///< I2S write +} en_i2s_start_condition_t ; + +/** + ***************************************************************************** + ** \brief I2S packet receive completion timer + *****************************************************************************/ +typedef enum en_i2s_packet_timer +{ + NoOperation = 0u, ///< No operation + Hclk54000Cycles = 1u, ///< Timeout cycle: 54000 + Hclk108000Cycles = 2u, ///< Timeout cycle: 108000 + Hclk216000Cycles = 3u ///< Timeout cycle: 216000 +} en_i2s_packet_timer_t ; + +/** + ***************************************************************************** + ** \brief I2S interrupt enable structure + *****************************************************************************/ +typedef enum en_i2s_irq_sel +{ + I2sTxFifoUnderflow0Irq = 0u, ///< TX-FIFO underflow 0 interrupt + I2sTxFifoUnderflow1Irq = 1u, ///< TX-FIFO underflow 1 interrupt + I2sTxBlockSizeErrIrq = 2u, ///< TX block size error interrupt + I2sFrameErrIrq = 3u, ///< Frame error interrupt + I2sTxFifoOverflowIrq = 4u, ///< TX-FIFO overflow interrupt + I2sTxFifoIrq = 5u, ///< TX FIFO interrupt + I2sRxBlockSizeErrIrq = 6u, ///< RX block size error interrupt + I2sRxFifoUnderflowIrq = 7u, ///< RX-FIFO underflow interrupt + I2sRxFifoOverflowIrq = 8u, ///< RX-FIFO overflow interrupt + I2sRxFifoIdleDetectIrq = 9u, ///< RX FIFO idle detection interrupt + I2sRxFifoIrq = 10u, ///< RX FIFO interrupt + +}en_i2s_irq_sel_t; + +/** + ***************************************************************************** + ** \brief I2S status enumeration + *****************************************************************************/ +typedef enum en_i2s_status +{ + I2sDmaTxChBlockSizeErr = 0u, ///< DMA transmit channel block size error + I2sDmaRxChBlockSizeErr = 1u, ///< DMA receive channel block size error + I2sFrameErr = 2u, ///< Frame error + I2sTxFifoUnderflow1 = 3u, ///< TX FIFO underflow interrupt flag 1 + I2sTxFifoUnderflow0 = 4u, ///< TX FIFO underflow interrupt flag 0 + I2sTxFifoOverflow = 5u, ///< TX FIFO overflow interrupt flag + I2sRxFifoUnderflow = 6u, ///< RX FIFO underflow interrupt flag + I2sRxFifoOverflow = 7u, ///< RX FIFO overflow interrupt flag + I2sRxFifoFifoIdle = 8u, ///< RX FIFO idle interrupt flag + I2sBusy = 9u, ///< I2S transmit busy status + I2sTxFifoMatchThreshold = 10u, ///< TX FIFO interrupt flag + I2sRxFifoMatchThreshold = 11u, ///< RX FIFO interrupt flag + +}en_i2s_status_t; + +/// Enumeration to define an index for each enabled I2S instance +typedef enum en_i2s_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_I2S0 == PDL_ON) + I2sInstanceIndexI2s0, + #endif + #if (PDL_PERIPHERAL_ENABLE_I2S1 == PDL_ON) + I2sInstanceIndexI2s1, + #endif + I2sInstanceIndexMax +} en_i2s_instance_index_t; + +/** \} GroupI2S_Types */ + +/** +* \addtogroup GroupI2S_DataStructures +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ +typedef void (*i2s_func_ptr_t)(void); +typedef void (*i2s_error_func_ptr)(uint32_t); + +/** + ***************************************************************************** + ** \brief I2S clock configuration + ** + ** \note I2S ch.0 PLL clock output = (Fin * N * M / K) + ** I2S ch.1 PLL clock output = (Fin * N * M1 / K) + ** I2S ch.0 PLL clock = I2S ch.0 PLL clock output / M + ** I2S ch.1 PLL clock = I2S ch.1 PLL clock output / M1 + ** I2S PLL clock output must be in a certain range, check it in the + ** product datasheet. + *****************************************************************************/ +typedef struct stc_i2s_clk_config +{ + en_i2s_pll_wait_time_t enI2sPllWaitTime; ///< I2S PLL stabilization wait time, see #en_i2s_pll_wait_time_t for details + uint8_t u8Pllk; ///< K value of I2S PLL + uint8_t u8Plln; ///< N value of I2S PLL + uint8_t u8Pllm; ///< M value of I2S PLL + uint8_t u8Pllm1; ///< M1 value of I2S PLL + en_i2s0_clk_in_t enI2s0ClkIn; ///< I2S ch.0 clock selection + en_i2s1_clk_in_t enI2s1ClkIn; ///< I2S ch.1 clock selection +} stc_i2s_clk_config_t; + +/** + ***************************************************************************** + ** \brief I2S sub frame configuration + *****************************************************************************/ +typedef struct stc_i2s_subframe_config +{ + uint8_t u8Snchn; ///< Sub Frame n Channel Numbers + uint8_t u8Snchl; ///< Sub Frame n Channel Length + uint8_t u8Snwdl; ///< Sub Frame n Word Length +} stc_i2s_subframe_config_t; + +/** + ***************************************************************************** + ** \brief I2S interrupt enable structure + *****************************************************************************/ +typedef struct stc_i2s_irq_en +{ + boolean_t bTxFifoUnderflow0Irq; ///< TRUE: Enable TX-FIFO underflow 0 interrupt + boolean_t bTxFifoUnderflow1Irq; ///< TRUE: Enable TX-FIFO underflow 1 interrupt + boolean_t bTxBlockSizeErrIrq; ///< TRUE: Enable TX block size error interrupt + boolean_t bFrameErrIrq; ///< TRUE: Enable frame error interrupt + boolean_t bTxFifoOverflowIrq; ///< TRUE: Enable TX-FIFO overflow interrupt + boolean_t bTxFifoIrq; ///< TRUE: Enable TX FIFO interrupt + boolean_t bRxBlockSizeErrIrq; ///< TRUE: Enable RX block size error interrupt + boolean_t bRxFifoUnderflowIrq; ///< TRUE: Enable RX-FIFO underflow interrupt + boolean_t bRxFifoOverflowIrq; ///< TRUE: Enable RX-FIFO overflow interrupt + boolean_t bRxFifoIdleDetectIrq; ///< TRUE: Enable RX FIFO idle detection interrupt + boolean_t bRxFifoIrq; ///< TRUE: Enable RX FIFO interrupt + +}stc_i2s_irq_en_t; + +/** + ***************************************************************************** + ** \brief I2S interrupt callback function structure + *****************************************************************************/ +typedef struct stc_i2s_irq_cb +{ + func_ptr_t pfnTxFifoUnderflow0IrqCb; ///< TRUE: Enable TX-FIFO underflow 0 interrupt + func_ptr_t pfnTxFifoUnderflow1IrqCb; ///< TRUE: Enable TX-FIFO underflow 1 interrupt + func_ptr_t pfnTxBlockSizeErrIrqCb; ///< TRUE: Enable TX block size error interrupt + func_ptr_t pfnFrameErrIrqCb; ///< TRUE: Enable frame error interrupt + func_ptr_t pfnTxFifoOverflowIrqCb; ///< TRUE: Enable TX-FIFO overflow interrupt + func_ptr_t pfnTxFifoIrqCb; ///< TRUE: Enable TX FIFO interrupt + func_ptr_t pfnRxBlockSizeErrIrqCb; ///< TRUE: Enable RX block size error interrupt + func_ptr_t pfnRxFifoUnderflowIrqCb; ///< TRUE: Enable RX-FIFO underflow interrupt + func_ptr_t pfnRxFifoOverflowIrqCb; ///< TRUE: Enable RX-FIFO overflow interrupt + func_ptr_t pfnRxFifoIdleDetectIrqCb; ///< TRUE: Enable RX FIFO idle detection interrupt + func_ptr_t pfnRxFifoIrqCb; ///< TRUE: Enable RX FIFO interrupt + +}stc_i2s_irq_cb_t, stc_i2s_intern_data_t; + +/** + ***************************************************************************** + ** \brief I2S configuration + *****************************************************************************/ +typedef struct stc_i2s_config +{ + uint8_t u8ClockDiv; ///< Clock divider settings + uint16_t u16OverheadBits; ///< Number of overhead bits + boolean_t bMaskBit; ///< TRUE: Serial Ouput Data in invalid/empty case + boolean_t bMasterMode; ///< TRUE: Master, FALSE: Slave + boolean_t bSubFrame01; ///< TRUE: Sub Frame 0 and 1, FALSE: only Sub Frame 0 + boolean_t bFifoTwoWords; ///< TRUE: FIFO divided in two 16-bit words, FALSE: FIFO 32-Bit word + boolean_t bBclkDivByMclk; ///< TRUE: Divide I2SMCLK and output as BLCK, FALSE: Divide HCLK and output as BCLK + boolean_t bBitExtensionHigh; ///< TRUE: Bit extension '1', FALSE: Bit extension '0' + boolean_t bFreeRunMode; ///< TRUE: Frame sync signal is free running, FALSE: Frame sync signal in burst mode + boolean_t bLsbFirst; ///< TRUE: Shift with LSB first, FALSE: Shift with MSB first + boolean_t bSampleAtEnd; ///< TRUE: Sample at end of bit reception, FALSE: Sample at middle of bit reception + boolean_t bClockpolarity; ///< TRUE: Data at falling edge of I2SCK, FALSE: Data ar risig edge of I2SCK + boolean_t bWordSelectSamePhase; ///< TRUE: I2SWS at same time of first bit, FALSE: I2SWS one block before first bit + boolean_t bWordSelectLength; ///< TRUE: I2SWS width one channel length, FALSE: I2SWS with one I2SCK pulse + boolean_t bWordSelectPolarity; ///< TRUE: I2SWS is '1', '0' when idle, FALSE: I2SWS is '0', '1' when idle + stc_i2s_subframe_config_t stcSubframe0; ///< Sub Frame 0 config + stc_i2s_subframe_config_t stcSubframe1; ///< Sub Frame 1 config + uint32_t u32S0ch; ///< Sub Frame 0 Channel Enable + uint32_t u32S1ch; ///< Sub Frame 1 Channel Enable + uint8_t u8TxFifoThreshold; ///< Treshold value of TX-FIFO for generating an interrupt + uint8_t u8RxFifoThreshold; ///< Treshold value of RX-FIFO for generating an interrupt + en_i2s_packet_timer_t enPacketReceiveCompletionTimer; ///< see #en_i2s_packet_timer_t for details + boolean_t bTxEnable; ///< TRUE: Transmitter enable, FALSE: Transmitter disable + boolean_t bRxEnable; ///< TRUE: Receiver enable, FALSE: Receiver disable + boolean_t bTxDmaEnable; ///< TRUE: Enable TX DMA + boolean_t bRxDmaEnable; ///< TRUE: Enable RX DMA +#if (PDL_INTERRUPT_ENABLE_I2S0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_I2S1 == PDL_ON) + stc_i2s_irq_en_t* pstcIrqEn; ///< Pointer to interrupt enable structure + stc_i2s_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt callback structure + boolean_t bTouchNvic; ///< TRUE: Enable NVIC, FALSE: disable NVIC +#endif +} stc_i2s_config_t; + +/// I2S instance data type +typedef struct stc_i2s_instance_data +{ + volatile stc_i2sn_t* pstcInstance; ///< pointer to registers of an instance + stc_i2s_intern_data_t stcInternData; ///< module internal data of instance +} stc_i2s_instance_data_t; + +/** \} GroupI2S_DataStructures */ + +/** +* \addtogroup GroupI2S_GlobalVariables +* \{ +*/ + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ +/// Look-up table for all enabled I2S instances and their internal data +extern stc_i2s_instance_data_t m_astcI2sInstanceDataLut[I2S_INSTANCE_COUNT]; + +/** \} GroupI2S_GlobalVariables */ + +/** +* \addtogroup GroupI2S_Functions +* \{ +*/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ +/* I2S interrupt */ +#if (PDL_INTERRUPT_ENABLE_I2S0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_I2S1 == PDL_ON) +void I2sIrqHandler( volatile stc_i2sn_t* pstcI2s, + stc_i2s_intern_data_t* pstcI2sInternData); +en_result_t I2s_EnableIrq(volatile stc_i2sn_t* pstcI2s, + en_i2s_irq_sel_t enIrqSel); +en_result_t I2s_DisableIrq(volatile stc_i2sn_t* pstcI2s, + en_i2s_irq_sel_t enIrqSel); +#endif +/* I2S clock */ +en_result_t I2s_InitClk(stc_i2s_clk_config_t* pstcConfig) ; +en_result_t I2s_DeInitClk(void) ; +en_result_t I2s_EnablePll(boolean_t bWaitPolling); +en_result_t I2s_CheckPllReady(void) ; +en_result_t I2s_DisablePll(void) ; +void I2s_StartClk(volatile stc_i2sn_t* pstcI2s) ; +void I2s_StopClk(volatile stc_i2sn_t* pstcI2s) ; +/* I2S */ +en_result_t I2s_Init(volatile stc_i2sn_t* pstcI2s, const stc_i2s_config_t* pstcConfig) ; +en_result_t I2s_DeInit(volatile stc_i2sn_t* pstcI2s, boolean_t bTouchNvic) ; +en_result_t I2s_Start(volatile stc_i2sn_t* pstcI2s) ; +en_result_t I2s_Stop(volatile stc_i2sn_t* pstcI2s) ; +en_result_t I2s_Reset(volatile stc_i2sn_t* pstcI2s); +en_result_t I2s_EnableTx(volatile stc_i2sn_t* pstcI2s); +en_result_t I2s_DisableTx(volatile stc_i2sn_t* pstcI2s); +en_result_t I2s_EnableRx(volatile stc_i2sn_t* pstcI2s); +en_result_t I2s_DisableRx(volatile stc_i2sn_t* pstcI2s); +boolean_t I2s_GetStatus(volatile stc_i2sn_t* pstcI2s, + en_i2s_status_t enStatus); +en_result_t I2s_ClrStatus(volatile stc_i2sn_t* pstcI2s, + en_i2s_status_t enStatus); +en_result_t I2s_WriteTxFifo(volatile stc_i2sn_t* pstcI2s, uint32_t u32Data); +uint32_t I2s_ReadRxFifo(volatile stc_i2sn_t* pstcI2s); +uint8_t I2s_GetTxFifoNumber(volatile stc_i2sn_t* pstcI2s); +uint8_t I2s_GetRxFifoNumber(volatile stc_i2sn_t* pstcI2s); + +/** \} GroupI2S_Functions */ +/** \} GroupI2S */ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif /* __I2S_H__ */ +/*****************************************************************************/ +/* EOF (not truncated) */ +/*****************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/icc/icc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/icc/icc.c new file mode 100644 index 0000000000..5047c257ac --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/icc/icc.c @@ -0,0 +1,1398 @@ +/******************************************************************************* +* \file icc.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the ICC +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "icc/icc.h" + +#if (defined(PDL_PERIPHERAL_ICC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled ICC instances and their internal data +stc_icc_instance_data_t m_astcIccInstanceDataLut[ICC_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_ICC0 == PDL_ON) + { + &ICC0, // pstcInstance + {0u,0u,0u,0u,0u,0u,0u,0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_ICC1 == PDL_ON) + { + &ICC1, // pstcInstance + {0u,0u,0u,0u,0u,0u,0u,0u} // stcInternData (not initialized yet) + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_icc_intern_data_t* IccGetInternDataPtr(volatile stc_iccn_t* pstcIcc); + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts + ** according CMSIS with level defined in pdl_user.h + ** + ** \param pstcIcc Pointer to ICC instance + ** + ******************************************************************************/ +static void IccInitIrq(volatile stc_iccn_t* pstcIcc) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #if (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + if (&ICC1 == pstcIcc) + { + /* Enable the interrupt */ + NVIC_ClearPendingIRQ(SMCIF1_FLASHIF_IRQn); + NVIC_EnableIRQ(SMCIF1_FLASHIF_IRQn); + NVIC_SetPriority(SMCIF1_FLASHIF_IRQn, PDL_IRQ_LEVEL_SMCIF1_FLASHIF); + } + #endif + #else +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) + if (&ICC0 == pstcIcc) + { + /* Enable the interrupt */ + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_EnableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_IRQ_LEVEL_PPG00_02_20_DSTC_SMCIF0_HDMICEC0); + } +#endif +#if (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + if (&ICC1 == pstcIcc) + { + /* Enable the interrupt */ + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_EnableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + } +#endif +#endif +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE == PDL_FM4_TYPE5) + /* Enable the interrupt */ + NVIC_ClearPendingIRQ(ICC0_1_IRQn); + NVIC_EnableIRQ(ICC0_1_IRQn); + NVIC_SetPriority(ICC0_1_IRQn, PDL_IRQ_LEVEL_ICC0_ICC1); + #endif +#endif +} /* Icc_InitIrq */ + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ** \param pstcIcc Pointer to ICC instance + ** + ******************************************************************************/ +static void IccDeInitIrq(volatile stc_iccn_t* pstcIcc) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + #if (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + if (&ICC1 == pstcIcc) + { + /* Disable the interrupt */ + NVIC_ClearPendingIRQ(SMCIF1_FLASHIF_IRQn); + NVIC_DisableIRQ(SMCIF1_FLASHIF_IRQn); + NVIC_SetPriority(SMCIF1_FLASHIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #else +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) + if (&ICC0 == pstcIcc) + { + /* Disable the interrupt */ + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_DisableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + if (&ICC1 == pstcIcc) + { + /* Disable the interrupt */ + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_DisableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#endif +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE == PDL_FM4_TYPE5) + /* Disable the interrupt */ + NVIC_ClearPendingIRQ(ICC0_1_IRQn); + NVIC_DisableIRQ(ICC0_1_IRQn); + NVIC_SetPriority(ICC0_1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#endif +} /* Icc_DeInitIrq */ + +#endif + +/****************************************************************************** + * ICC driver functions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain ICC instance. + ** + ** \param pstcIcc Pointer to ICC instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_icc_intern_data_t* IccGetInternDataPtr(volatile stc_iccn_t* pstcIcc) +{ + stc_icc_intern_data_t* pstcInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcIcc) + { + for (u32Instance = 0u; u32Instance < ICC_INSTANCE_COUNT; u32Instance++) + { + if (pstcIcc == m_astcIccInstanceDataLut[u32Instance].pstcInstance) + { + pstcInternDataPtr = &m_astcIccInstanceDataLut[u32Instance].stcInternData; + break; + } + } + } + + return (pstcInternDataPtr); +} /* IccGetInternDataPtr */ + + +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) +/** + ****************************************************************************** + ** \brief ICC interrupt service routine. + ** + ** \param pstcIcc Pointer to ICC instance + ** \param pstcIccInternData Pointer to ICC internal data structure + ** + ** This function is called on Interrupt set by the ICC. + ** + ******************************************************************************/ +void Icc_IrqHandler( volatile stc_iccn_t* pstcIcc, + stc_icc_intern_data_t* pstcIccInternData) +{ + stc_smcif_irq_status_field_t stcIrqStatus; + + // Read IRQ status register + stcIrqStatus = pstcIcc->IRQ_STATUS_f; + + if ((NULL != pstcIcc) && (NULL != pstcIccInternData)) + { + if (TRUE == stcIrqStatus.RXFULIRQ) // RX buffer full + { + if (NULL != pstcIccInternData->pfnRxFullIrqCb) + { + pstcIccInternData->pfnRxFullIrqCb(); + } + } + + if (TRUE == stcIrqStatus.TXEMPIRQ) // TX buffer full + { + if (NULL != pstcIccInternData->pfnTxEmptyIrqCb) + { + pstcIccInternData->pfnTxEmptyIrqCb(); + } + } + + if (TRUE == stcIrqStatus.RXSTBIIRQ) // RX start bit detection + { + if (NULL != pstcIccInternData->pfnRxStartBitIrqCb) + { + pstcIccInternData->pfnRxStartBitIrqCb(); + } + } + + if (TRUE == stcIrqStatus.CARDEVENTIRQ) // Card event + { + if (NULL != pstcIccInternData->pfnCardEventIrqCb) + { + pstcIccInternData->pfnCardEventIrqCb(); + } + } + + if (TRUE == stcIrqStatus.IDTEXPIRQ) // idle timer + { + if (NULL != pstcIccInternData->pfnIdleTimerIrqCb) + { + pstcIccInternData->pfnIdleTimerIrqCb(); + } + } + + if (TRUE == stcIrqStatus.RDFIFOIRQ) // Read FIFO count is more than Read FIFO level + 1 + { + if (NULL != pstcIccInternData->pfnReadFifoIrqCb) + { + pstcIccInternData->pfnReadFifoIrqCb(); + } + } + + if (TRUE == stcIrqStatus.WRFIFOIRQ) // Write FIFO count is less than Write FIFO level + { + if (NULL != pstcIccInternData->pfnWriteFifoIrqCb) + { + pstcIccInternData->pfnWriteFifoIrqCb(); + } + } + + if (TRUE == stcIrqStatus.RDFIFOOVRIRQ) // Read FIFO overrun + { + if (NULL != pstcIccInternData->pfnReadFifoOverrunIrqCb) + { + pstcIccInternData->pfnReadFifoOverrunIrqCb(); + } + } + } +} // IccIrqHandler + +/** + ****************************************************************************** + ** \brief Enable ICC interrupts + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] enIrqSel Interrupt selection + ** + ** \retval Ok Interrupts has been enabled and callback + ** fucntions are set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcICC == NULL + ** - pstcInt == NULL + ** - pstcIntCb == NULL + ** - Other invalid configuration + ** + ** The NVIC IRQ is also enabled in this function. + ** + ******************************************************************************/ +en_result_t Icc_EnableIrq(volatile stc_iccn_t* pstcIcc, + en_icc_irq_sel_t enIrqSel) +{ + if (NULL == pstcIcc) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case IccRxFullIrq: + pstcIcc->GLOBALCONTROL1_f.MASKRXFUL = 1u; + break; + case IccTxEmptyIrq: + pstcIcc->GLOBALCONTROL1_f.MASKTXEMP = 1u; + break; + case IccRxStartBitIrq: + pstcIcc->GLOBALCONTROL1_f.MASKSTI = 1u; + break; + case IccCardEventIrq: + pstcIcc->GLOBALCONTROL1_f.MASKCAEVENT = 1u; + break; + case IccIdleTimerIrq: + pstcIcc->GLOBALCONTROL1_f.MASKITEXP = 1u; + break; + case IccReadFifoIrq: + pstcIcc->FIFO_MODE_f.RDFIFOIRQEN = 1u; + break; + case IccWriteFifoIrq: + pstcIcc->FIFO_MODE_f.WRFIFOIRQEN = 1u; + break; + case IccReadFifoOverrunIrq: + pstcIcc->FIFO_MODE_f.RDFIFOOVRIRQEN = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable ICC interrupts + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] enIrqSel Interrupt selection + ** + ** \retval Ok Interrupts has been disabled and callback + ** fucntion pointers are set to NULL + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** - pstcInt == NULL + ** + ** The NVIC IRQ is also disabled in this function if all interrupt sources + ** are disable. + ** + ******************************************************************************/ +en_result_t Icc_DisableIrq(volatile stc_iccn_t* pstcIcc, + en_icc_irq_sel_t enIrqSel) +{ + if (NULL == pstcIcc) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case IccRxFullIrq: + pstcIcc->GLOBALCONTROL1_f.MASKRXFUL = 0u; + break; + case IccTxEmptyIrq: + pstcIcc->GLOBALCONTROL1_f.MASKTXEMP = 0u; + break; + case IccRxStartBitIrq: + pstcIcc->GLOBALCONTROL1_f.MASKSTI = 0u; + break; + case IccCardEventIrq: + pstcIcc->GLOBALCONTROL1_f.MASKCAEVENT = 0u; + break; + case IccIdleTimerIrq: + pstcIcc->GLOBALCONTROL1_f.MASKITEXP = 0u; + break; + case IccReadFifoIrq: + pstcIcc->FIFO_MODE_f.RDFIFOIRQEN = 0u; + break; + case IccWriteFifoIrq: + pstcIcc->FIFO_MODE_f.WRFIFOIRQEN = 0u; + break; + case IccReadFifoOverrunIrq: + pstcIcc->FIFO_MODE_f.RDFIFOOVRIRQEN = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read ICC IRQ Status + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t Icc_ReadIrqStatus(volatile stc_iccn_t* pstcIcc) +{ + return (pstcIcc->IRQ_STATUS); +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialization of an ICC module to activate as ICC. + ** + ** Set registers to active ICC as ICC. + ** + ** \param [in] pstcIcc Pointer to ICC instance register area + ** \param [in] pstcConfig ICC configuration + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcICC == NULL + ** - pstcConfig == NULL + ** - pstcIccInternData == NULL (invalid or disabled ICC unit + ** (PDL_PERIPHERAL_ENABLE_ICC0)) + ** + ******************************************************************************/ +en_result_t Icc_Init(volatile stc_iccn_t* pstcIcc, + const stc_icc_config_t* pstcConfig) +{ + stc_icc_intern_data_t* pstcIccInternData; + + // Preset local register variables to zero + stc_smcif_globalcontrol1_field_t stcGC1; + stc_smcif_globalcontrol2_field_t stcGC2; + stc_smcif_portcontrol_field_t stcPC; + stc_smcif_fifo_mode_field_t stcFFM; + // Clear structures + PDL_ZERO_STRUCT(stcGC1); + PDL_ZERO_STRUCT(stcGC2); + PDL_ZERO_STRUCT(stcPC); + PDL_ZERO_STRUCT(stcFFM); + + // Check for valid pointer and get pointer to internal data struct + pstcIccInternData = IccGetInternDataPtr(pstcIcc); + + // Parameter check and get ptr to internal data struct + if ((NULL == pstcIccInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + stcGC1 = pstcIcc->GLOBALCONTROL1_f; + stcGC2 = pstcIcc->GLOBALCONTROL2_f; + stcFFM = pstcIcc->FIFO_MODE_f; + + // Set the clock division + pstcIcc->CARDCLOCK = pstcConfig->u16ClkDiv; + + // Set the baudrate + pstcIcc->BAUDRATE = pstcConfig->u16BaudRate; + + // Set the trasnmit data format + switch(pstcConfig->enTxDataFormat) + { + case IccTx8Even2: + stcGC1.MODE8N1 = 0u; + stcGC1.PARITY = 0u; + break; + case IccTx8Odd2: + stcGC1.MODE8N1 = 0u; + stcGC1.PARITY = 1u; + break; + case IccTx8None2: + stcGC1.MODE8N1 = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + // Set the receive data format + switch(pstcConfig->enRxDataFormat) + { + case IccRx8Even1: + stcGC1.MODE8N1 = 0u; + stcGC1.FRM0 = 0u; + stcGC1.PARITY = 0u; + stcGC2.RX8N1 = 0u; + break; + case IccRx8Odd1: + stcGC1.MODE8N1 = 0u; + stcGC1.FRM0 = 0u; + stcGC1.PARITY = 1u; + stcGC2.RX8N1 = 0u; + break; + case IccRx8None2: + stcGC1.MODE8N1 = 1u; + stcGC1.FRM0 = 0u; + stcGC2.RX8N1 = 0u; + break; + case IccRx8None1: + stcGC1.MODE8N1 = 1u; + stcGC1.FRM0 = 0u; + stcGC2.RX8N1 = 1u; + break; + case IccRx9None1: + stcGC1.MODE8N1 = 1u; + stcGC1.FRM0 = 1u; + stcGC2.RX8N1 = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + // Set idle timer source clock + switch (pstcConfig->enIdleTimerSrcClk) + { + case IccCardClk: + stcGC1.IDTSC = 0u; + break; + case IccEtuClk: + stcGC1.IDTSC = 1u; + break; + } + + // Set idle timer count + pstcIcc->IDLETIMER = pstcConfig->u16IdleTimerCnt; + + // Set the guard timer + stcGC1.GUAEN = ((TRUE == pstcConfig->bUseGuardTimer) ? 1u : 0u); + pstcIcc->GUARDTIMER = pstcConfig->u8GuardTime; + + // Set the bit direction and inversion + if((IccDataLsbFirst == pstcConfig->enBitDirection) && (FALSE == pstcConfig->bInvertData)) + { + stcGC1.FRM1 = 0u; + stcGC2.INVDATAOUT = 0u; + } + if((IccDataLsbFirst == pstcConfig->enBitDirection) && (TRUE == pstcConfig->bInvertData)) + { + stcGC1.FRM1 = 0u; + stcGC2.INVDATAOUT = 1u; + } + if((IccDataMsbFirst == pstcConfig->enBitDirection) && (TRUE == pstcConfig->bInvertData)) + { + stcGC1.FRM1 = 1u; + stcGC2.INVDATAOUT = 0u; + } + if((IccDataMsbFirst == pstcConfig->enBitDirection) && (FALSE == pstcConfig->bInvertData)) + { + stcGC1.FRM1 = 1u; + stcGC2.INVDATAOUT = 1u; + } + + // Set the data resend + stcGC1.RESND = ((TRUE == pstcConfig->bDataResend) ? 1u : 0u); + + // Set Data pin mode + if(TRUE == pstcConfig->bDataPinMode) + { + // Conotrolled by software + stcGC1.IOMOD = 1u; + stcPC.TRIMOD = 1u; + } + else + { + // Controlled by hardware + stcGC1.IOMOD = 0u; + stcPC.TRIMOD = 0u; + } + + // Set Clock pin mode + stcGC1.CKMOD = ((TRUE == pstcConfig->bClkPinMode) ? 1u : 0u); + + // Set IO output enable + stcPC.VPENOUTEN = ((TRUE == pstcConfig->bVpenPinOutputEn) ? 1u : 0u); + stcPC.VCCOUTEN = ((TRUE == pstcConfig->bVccPinOutputEn) ? 1u : 0u); + stcPC.RSTOUTEN = ((TRUE == pstcConfig->bRstPinOutputEn) ? 1u : 0u); + stcPC.CLKOUTEN = ((TRUE == pstcConfig->bClkPinOutputEn) ? 1u : 0u); + stcPC.IO1EN = ((TRUE == pstcConfig->bDataPinOutputEn) ? 1u : 0u); + + // Set IO pin level + stcPC.VPEN = ((TRUE == pstcConfig->bVpenPinLevel) ? 1u : 0u); + stcPC.VCCEN = ((TRUE == pstcConfig->bVccPinLevel) ? 1u : 0u); + stcPC.RST = ((TRUE == pstcConfig->bRstPinLevel) ? 1u : 0u); + stcPC.CLKPT = ((TRUE == pstcConfig->bClkPinLevel) ? 1u : 0u); + stcPC.IO1 = ((TRUE == pstcConfig->bDataPinLevel) ? 1u : 0u); + + // FIFO setting + if(NULL != pstcConfig->pstcFifoConfig) + { + stcFFM.WRFIFOLEVEL = pstcConfig->pstcFifoConfig->TxFifoLevel; // Set Write FIFO level + stcFFM.RDFIFOLEVEL = pstcConfig->pstcFifoConfig->RxFifoLevel; // Set ReadFIFO level + stcFFM.FIFOEN = 1u; // Enable FIFO + } + + // Set registers value + pstcIcc->GLOBALCONTROL1_f = stcGC1; + pstcIcc->GLOBALCONTROL2_f = stcGC2; + pstcIcc->FIFO_MODE_f = stcFFM; + pstcIcc->PORTCONTROL_f = stcPC; + +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bRxFullIrq) + { + pstcIcc->GLOBALCONTROL1_f.MASKRXFUL = 1u; + } + if(TRUE == pstcConfig->pstcIrqEn->bTxEmptyIrq) + { + pstcIcc->GLOBALCONTROL1_f.MASKTXEMP = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bRxStartBitIrq) + { + pstcIcc->GLOBALCONTROL1_f.MASKSTI = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bCardEventIrq) + { + pstcIcc->GLOBALCONTROL1_f.MASKCAEVENT = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bIdleTimerIrq) + { + pstcIcc->GLOBALCONTROL1_f.MASKITEXP = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bReadFifoIrq) + { + pstcIcc->FIFO_MODE_f.RDFIFOIRQEN = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bWriteFifoIrq) + { + pstcIcc->FIFO_MODE_f.WRFIFOIRQEN = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bReadFifoOverrunIrq) + { + pstcIcc->FIFO_MODE_f.RDFIFOOVRIRQEN = 1u; + } + } + + if (NULL != pstcConfig->pstcIrqCb) + { + pstcIccInternData->pfnRxFullIrqCb = pstcConfig->pstcIrqCb->pfnRxFullIrqCb; + pstcIccInternData->pfnTxEmptyIrqCb = pstcConfig->pstcIrqCb->pfnTxEmptyIrqCb; + pstcIccInternData->pfnRxStartBitIrqCb = pstcConfig->pstcIrqCb->pfnRxStartBitIrqCb; + pstcIccInternData->pfnCardEventIrqCb = pstcConfig->pstcIrqCb->pfnCardEventIrqCb; + pstcIccInternData->pfnIdleTimerIrqCb = pstcConfig->pstcIrqCb->pfnIdleTimerIrqCb; + pstcIccInternData->pfnReadFifoIrqCb = pstcConfig->pstcIrqCb->pfnReadFifoIrqCb; + pstcIccInternData->pfnWriteFifoIrqCb = pstcConfig->pstcIrqCb->pfnWriteFifoIrqCb; + pstcIccInternData->pfnReadFifoOverrunIrqCb = pstcConfig->pstcIrqCb->pfnReadFifoOverrunIrqCb; + } + + if (TRUE == pstcConfig->bTouchNvic) + { + IccInitIrq(pstcIcc); + } + +#endif + + return (Ok); +} /* ICC_Init */ + +/** + ****************************************************************************** + ** \brief Deinitialisation of a ICC module activating as ICC. + ** + ** All used icc register are reset to their default values. + ** + ** \param [in] pstcIcc Pointer to ICC instance register area + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** - pstcIccInternData == NULL (invalid or disabled ICC unit + ** (PDL_PERIPHERAL_ENABLE_ICC0)) + ** + ******************************************************************************/ +en_result_t Icc_DeInit(volatile stc_iccn_t* pstcIcc, boolean_t bTouchNvic) +{ + en_result_t enResult; + stc_icc_intern_data_t* pstcIccInternData; + + // Check for valid pointer and get pointer to internal data struct ... + pstcIccInternData = IccGetInternDataPtr(pstcIcc); + + // ... and check + if (NULL == pstcIccInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + pstcIcc->GLOBALCONTROL1 = 0u; + pstcIcc->GLOBALCONTROL2 = 0u; + pstcIcc->PORTCONTROL = 0u; + pstcIcc->CARDCLOCK = 0u; + pstcIcc->FIFO_MODE = 0u; + + #if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + pstcIccInternData->pfnRxFullIrqCb = NULL; + pstcIccInternData->pfnTxEmptyIrqCb = NULL; + pstcIccInternData->pfnRxStartBitIrqCb = NULL; + pstcIccInternData->pfnCardEventIrqCb = NULL; + pstcIccInternData->pfnIdleTimerIrqCb = NULL; + pstcIccInternData->pfnReadFifoIrqCb = NULL; + pstcIccInternData->pfnWriteFifoIrqCb = NULL; + pstcIccInternData->pfnReadFifoOverrunIrqCb = NULL; + + if (TRUE == bTouchNvic) + { + IccDeInitIrq(pstcIcc); + } + #endif + enResult = Ok; + } + + return (enResult); +} // Icc_DeInit + +/** + ****************************************************************************** + ** \brief Enable ICC Function + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Ok ICC function is enabled successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_Enable (volatile stc_iccn_t* pstcIcc) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->GLOBALCONTROL2_f.ICCDISABLE = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable ICC Function + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Ok ICC function is enabled successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_Disable (volatile stc_iccn_t* pstcIcc) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->GLOBALCONTROL2_f.ICCDISABLE = 1u; + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Set the baudrate of ICC + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] u16BaudRate Baudrate value [bps] + ** + ** \retval Ok ICC baud rate has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** \note + ** The ICC baud rate can be initialized in the Icc_Init() and be modified + ** in the funciton. + ** + ******************************************************************************/ +en_result_t Icc_SetBaudRate(volatile stc_iccn_t* pstcIcc, + uint16_t u16BaudRate) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->BAUDRATE = u16BaudRate; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get status of ICC according to status type + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] enStatus ICC status type + ** \arg IccTxEmpty Transmit buffer empty + ** \arg IccRxFull Receive buffer full + ** \arg IccRxAction Receive is in action + ** \arg IccTxAction Transmit is in action + ** \arg IccCardDetect Card insertion is detected + ** \arg IccCardEvent Card event is detected + ** \arg IccReceiveOverflow Receive buffer overflow + ** \arg IccIdleTmrRun Idle timer running + ** \arg IccRdFifoOverrun Read FIFO overflow + ** \arg IccRdFifoFull Read FIFO full + ** \arg IccWrFifoEmpty Write FIFO empty + ** \arg IccTxResend Trasmit detect resend + ** \arg IccRxResend Receive detect resend + ** + ** \retval FALSE The event do not happen + ** \retval TRUE The event happen + ** + ******************************************************************************/ +boolean_t Icc_GetStatus(volatile stc_iccn_t* pstcIcc, + en_icc_status_t enStatus) +{ + boolean_t bResult = FALSE; + + switch(enStatus) + { + case IccTxEmpty: + bResult = (pstcIcc->STATUS_f.TXEMP == 1u) ? TRUE : FALSE; + break; + case IccRxFull: + bResult = (pstcIcc->STATUS_f.RXFUL == 1u) ? TRUE : FALSE; + break; + case IccRxAction: + bResult = (pstcIcc->STATUS_f.RXACT == 1u) ? TRUE : FALSE; + break; + case IccTxAction: + bResult = (pstcIcc->STATUS_f.TXACT == 1u) ? TRUE : FALSE; + break; + case IccCardDetect: + bResult = (pstcIcc->STATUS_f.CARDDETECT == 1u) ? TRUE : FALSE; + break; + case IccCardEvent: + bResult = (pstcIcc->STATUS_f.CARDEVENT == 1u) ? TRUE : FALSE; + break; + case IccReceiveOverflow: + bResult = (pstcIcc->STATUS_f.RECOFL == 1u) ? TRUE : FALSE; + break; + case IccIdleTimerRun: + bResult = (pstcIcc->STATUS_f.IDTRUN == 1u) ? TRUE : FALSE; + break; + case IccReadFifoOverrun: + bResult = (pstcIcc->STATUS_f.RDFIFOOVR == 1u) ? TRUE : FALSE; + break; + case IccReadFifoFull: + bResult = (pstcIcc->STATUS_f.RDFIFOFUL == 1u) ? TRUE : FALSE; + break; + case IccWriteFifoEmpty: + bResult = (pstcIcc->STATUS_f.WRFIFOEMP == 1u) ? TRUE : FALSE; + break; + case IccRxStartErr: + bResult = (pstcIcc->STATUS_f.RXSTARTERR == 1u) ? TRUE : FALSE; + break; + case IccTxResend: + bResult = (pstcIcc->STATUS_f.TXRESEND == 1u) ? TRUE : FALSE; + break; + case IccRxResend: + bResult = (pstcIcc->STATUS_f.RXRESEND == 1u) ? TRUE : FALSE; + break; + default: + break; + } + + return bResult; +} + +/** + ****************************************************************************** + ** \brief Get interrupt status of ICC according to status type + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] enIrqSel ICC interrupt type + ** \arg IccRxFullIrq RX buffer full interrupt status + ** \arg IccTxEmptyIrq TX buffer empty interrupt status + ** \arg IccRxStartBitIrq RX start bit detect interrupt status + ** \arg IccCardEventIrq Card event interrupt status + ** \arg IccIdleTimerIrq Idle timer interrupt status + ** \arg IccReadFifoIrq Read FIFO interrupt status + ** \arg IccWriteFifoIrq Write FIFO interrupt status + ** \arg IccReadFifoOverrunIrq Read FIFO overrun interrupt status + ** + ** \retval FALSE The interrupt status is not set + ** \retval TRUE The interrupt status is set + ** + ******************************************************************************/ +boolean_t Icc_GetIrqStatus(volatile stc_iccn_t* pstcIcc, en_icc_irq_sel_t enIrqSel) +{ + boolean_t bRet = FALSE; + + switch (enIrqSel) + { + case IccRxFullIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.RXFULIRQ) ? TRUE : FALSE); + break; + case IccTxEmptyIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.TXEMPIRQ) ? TRUE : FALSE); + break; + case IccRxStartBitIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.RXSTBIIRQ) ? TRUE : FALSE); + break; + case IccCardEventIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.CARDEVENTIRQ) ? TRUE : FALSE); + break; + case IccIdleTimerIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.IDTEXPIRQ) ? TRUE : FALSE); + break; + case IccReadFifoIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.RDFIFOIRQ) ? TRUE : FALSE); + break; + case IccWriteFifoIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.WRFIFOIRQ) ? TRUE : FALSE); + break; + case IccReadFifoOverrunIrq: + bRet = ((1u == pstcIcc->IRQ_STATUS_f.RXFULIRQ) ? TRUE : FALSE); + break; + } + + return bRet; +} + + +/** + ****************************************************************************** + ** \brief Write ICC data buffer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SendData(volatile stc_iccn_t* pstcIcc, uint16_t u16Data) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->DATA = u16Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write ICC FIFO data buffer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SendFifoData(volatile stc_iccn_t* pstcIcc, uint16_t u16Data) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->DATA_FIFO = u16Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read ICC data buffer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t Icc_ReceiveData(volatile stc_iccn_t* pstcIcc) +{ + return (pstcIcc->DATA); +} + +/** + ****************************************************************************** + ** \brief Read ICC FIFO data buffer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t Icc_ReceiveFifoData(volatile stc_iccn_t* pstcIcc) +{ + return (pstcIcc->DATA_FIFO); +} + +/** + ****************************************************************************** + ** \brief Clear ICC Write FIFO + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Ok FIFO has been successfully reset + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_ClearWriteFifo (volatile stc_iccn_t* pstcIcc) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->FIFO_CLEAR_MSB_WRITE = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Clear ICC Read FIFO + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Ok FIFO has been successfully reset + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_ClearReadFifo (volatile stc_iccn_t* pstcIcc) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->FIFO_CLEAR_MSB_READ = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set ICC TX FIFO level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] u8Level FIFO level + ** + ** \retval Ok FIFO level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetWriteFifoLevel(volatile stc_iccn_t* pstcIcc, + uint8_t u8Level) +{ + if ((NULL == pstcIcc) || (15u < u8Level)) + { + return ErrorInvalidParameter; + } + + pstcIcc->FIFO_MODE_f.WRFIFOLEVEL = u8Level; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set ICC TX FIFO level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] u8Level FIFO level + ** + ** \retval Ok FIFO level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetReadFifoLevel(volatile stc_iccn_t* pstcIcc, + uint8_t u8Level) + +{ + if ((NULL == pstcIcc) || (15u < u8Level)) + { + return ErrorInvalidParameter; + } + + pstcIcc->FIFO_MODE_f.RDFIFOLEVEL = u8Level; + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Get ICC Write FIFO current count + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval FIFO count + ** + ******************************************************************************/ +uint8_t Icc_GetWriteFifoCurCnt(volatile stc_iccn_t* pstcIcc) +{ + uint8_t u8i, u8Count = 0u; + uint16_t u16WriteFifo; + + u16WriteFifo = pstcIcc->FIFO_LEVEL_WRITE; + + for(u8i=0u; u8i<16u; u8i++) + { + if((u16WriteFifo & (1ul << u8i)) == (1ul << u8i)) + { + u8Count++; + } + } + + return (u8Count); +} + +/** + ****************************************************************************** + ** \brief Get ICC Read FIFO current count + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval FIFO count + ** + ******************************************************************************/ +uint8_t Icc_GetReadFifoCurCnt(volatile stc_iccn_t* pstcIcc) +{ + uint8_t u8i, u8Count = 0u; + uint16_t u16ReadFifo; + + u16ReadFifo = pstcIcc->FIFO_LEVEL_READ; + + for(u8i=0u; u8i<16u; u8i++) + { + if((u16ReadFifo & (1ul << u8i)) == (1ul << u8i)) + { + u8Count++; + } + } + + return (u8Count); +} + +/** + ****************************************************************************** + ** \brief Set ICC VPEN pin level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] bLevel Pin level + ** + ** \retval Ok Pin level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetVpenPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel) + +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->PORTCONTROL_f.VPEN = ((bLevel == TRUE) ? 1u: 0u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set ICC VCC pin level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] bLevel Pin level + ** + ** \retval Ok Pin level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetVccPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel) + +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->PORTCONTROL_f.VCCEN = ((bLevel == TRUE) ? 1u: 0u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set ICC Reset pin level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] bLevel Pin level + ** + ** \retval Ok Pin level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetRstPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel) + +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->PORTCONTROL_f.RST = ((bLevel == TRUE) ? 1u: 0u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set ICC Clock pin level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] bLevel Pin level + ** + ** \retval Ok Pin level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetClkPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel) + +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->PORTCONTROL_f.CLKPT = ((bLevel == TRUE) ? 1u: 0u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set ICC Data pin level + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] bLevel Pin level + ** + ** \retval Ok Pin level has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetDataPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel) + +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->PORTCONTROL_f.IO1 = ((bLevel == TRUE) ? 1u: 0u); + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Set count value of ICC Idle timer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** \param [in] u16Cnt Timer count + ** + ** \retval Ok Configuration has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_SetIdleTimerCnt(volatile stc_iccn_t* pstcIcc, + uint16_t u16Cnt) + +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->IDLETIMER = u16Cnt; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start Idle timer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Ok No error + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_StartIdleTimer(volatile stc_iccn_t* pstcIcc) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->GLOBALCONTROL1_f.STIDT = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Stop Idle timer + ** + ** \param [in] pstcIcc Pointer to ICC instance + ** + ** \retval Ok No error + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcIcc == NULL + ** + ******************************************************************************/ +en_result_t Icc_StopIdleTimer(volatile stc_iccn_t* pstcIcc) +{ + if (NULL == pstcIcc) + { + return ErrorInvalidParameter; + } + + pstcIcc->GLOBALCONTROL1_f.STIDT = 0u; + + return Ok; +} + +#endif /* #if (defined(PDL_PERIPHERAL_ICC_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/icc/icc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/icc/icc.h new file mode 100644 index 0000000000..17d34538b9 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/icc/icc.h @@ -0,0 +1,433 @@ +/******************************************************************************* +* \file icc.h +* +* \version 1.20 +* +* \brief Headerfile for IC Card functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __ICC_H__ +#define __ICC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_ICC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupICC Smart Card Interface (ICC) +* \{ +* \defgroup GroupICC_Macros Macros +* \defgroup GroupICC_Functions Functions +* \defgroup GroupICC_GlobalVariables Global Variables +* \defgroup GroupICC_DataStructures Data Structures +* \defgroup GroupICC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupICC +* \{ +* The Smart Card Interface (ICC) peripheral supports communication with ISO 7816 smart cards. +* Only asynchronous cards are supported. The peripheral has a parallel-to-serial and serial-to-parallel +* converter with timer support. ICC supports 16-byte transmit and receive FIFO buffers.
+* The smart card pins are shared with GPIO pins. The physical smart card pins are configured +* using the GPIO module. Please refer to the GPIO section for information on configuring the +* physical pins of the smart card.
+* ICC features include:
+* * Support for ISO 7816-3 +* * Card clock frequency adjustable up to 20 MHz +* * Programmable baud rate +* * Available protocols: +* - Transmitter: 8E2, 8O2, 8N2 +* - Receiver: 8E1, 8O1, 8N2, 8N1, 9N1 +* - Inverse mode +* * Resend option: +* - Transmitter: if receiver requests a resend, data will be sent again and interrupt is delayed +* - Receiver: if parity bit is wrong, block can request a resend +* * Inversion of output data is programmable +* * Card inserted or removed detection (used for interrupt generation) +* * Programmable guard time +* * FIFO size: +* - For receiver: 16-bytes +* - For transmitter: 16-bytes +* * Programmable idle timer (interrupt may occur when expired) +* * Interrupt controlled +* +* \section SectionICC_ConfigurationConsideration Configuration Consideration +* To set up an ICC, you need to configure interrupts and the data FIFO (if you use the FIFO). +* You specify which interrupts to enable in an stc_icc_irq_en_t structure. Provide the required +* callback functions in an stc_icc_irq_cb_t structure. Similarly, if you use a FIFO data buffer, +* set the fields in an stc_icc_fifo_config_t structure. The ICC config structure has fields for the +* addresses of these structures. Use NULL if you do not use a feature.
+* To set up the ICC itself, you provide configuration parameters in the stc_icc_config_t structure. +* For example, you set the clock divider, the baud rate, the transmit and receive data formats, and so on. +* You also enable and set the level for a series of I/O pins.
+* Then call Icc_Init() andIcc_Enable(). Use Icc_DeInit() to reset all ICC related configuration registers.
+* While running, use API function calls to:
+* * Enable or disable selected interrupts +* * Change the baud rate +* * Send or receive data a word at a time, to either the ICC buffer or the FIFO buffer +* * Clear either the write or read FIFO buffer +* * Change pin levels +* * Get status and irq status +* For status and irq status, you pass in a constant identifying precisely what status you want. +* See en_icc_status_t and en_icc_irq_sel_t for choices. See the ICC function documentation for +* full information on the API.
+* \section SectionICC_MoreInfo More Information +* For more information on the ICC peripheral, refer to:
+* FM0+ Peripheral Manual - Communication Subsystem TRM.pdf
+* FM4 Peripheral Manual - Communication Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + + + +/** +* \addtogroup GroupICC_Macros +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define stc_iccn_t FM_SMCIF_TypeDef + +#define ICC0 (*((volatile stc_iccn_t *) FM_SMCIF0_BASE)) +#define ICC1 (*((volatile stc_iccn_t *) FM_SMCIF1_BASE)) + +#define ICC_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_ICC0 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_ICC1 == PDL_ON) + +/** \} GroupICC_Macros */ + +/** +* \addtogroup GroupICC_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief ICC Idle timer source + ******************************************************************************/ +typedef enum en_icc_idletmrclk +{ + IccCardClk = 0u, ///< Idle timer is clocked by card clock(ICx_CLK) + IccEtuClk = 1u, ///< Idle timer is clocked by baud clock (ETU clock). +} en_icc_idletmrclk_t; + +/** + ****************************************************************************** + ** \brief ICC data direction + ******************************************************************************/ +typedef enum en_icc_data_dir +{ + IccDataLsbFirst = 0u, ///< LSB first + IccDataMsbFirst = 1u, ///< MSB first +}en_icc_data_dir_t; + +/** + ****************************************************************************** + ** \brief ICC transmit data format + ******************************************************************************/ +typedef enum en_icc_tx_data +{ + IccTx8Even2 = 0u, ///< 8 bit with even parity and 2 stop bit + IccTx8Odd2 = 1u, ///< 8 bit with odd parity and 2 stop bit + IccTx8None2 = 2u, ///< 8 bit with none parity and 2 stop bit +}en_icc_tx_data_t; + +/** + ****************************************************************************** + ** \brief ICC receive data format + ******************************************************************************/ +typedef enum en_icc_rx_data +{ + IccRx8Even1 = 0u, ///< 8 bit with even parity and 2 stop bit + IccRx8Odd1 = 1u, ///< 8 bit with odd parity and 2 stop bit + IccRx8None2 = 2u, ///< 8 bit with none parity and 2 stop bit + IccRx8None1 = 3u, ///< 8 bit with none parity and 1 stop bit + IccRx9None1 = 4u, ///< 9 bit with none parity and 1 stop bit +}en_icc_rx_data_t; + +/** + ****************************************************************************** + ** \brief ICC interrupt types + ******************************************************************************/ +typedef enum en_icc_irq_sel +{ + IccRxFullIrq = 0u, ///< Receive buffer full interrupt + IccTxEmptyIrq = 1u, ///< Transmit buffer empty interrupt + IccRxStartBitIrq = 2u, ///< Receive start bit detected interrupt + IccCardEventIrq = 3u, ///< Card insert/pull out interrupt + IccIdleTimerIrq = 4u, ///< Idle timer interrupt + IccReadFifoIrq = 5u, ///< Receive FIFO interrupt + IccWriteFifoIrq = 6u, ///< Transfer FIFO interrupt + IccReadFifoOverrunIrq = 7u, ///< Receive FIFO overrun interrupt + +}en_icc_irq_sel_t; + +/** + ****************************************************************************** + ** \brief ICC status types + ******************************************************************************/ +typedef enum en_icc_status +{ + IccTxEmpty = 0u, ///< Transmit buffer empty + IccRxFull = 1u, ///< Receive buffer full + IccRxAction = 2u, ///< Receive is in action + IccTxAction = 3u, ///< Transmit is in action + IccCardDetect = 4u, ///< Card insertion is detected + IccCardEvent = 5u, ///< Card event is detected + IccReceiveOverflow = 6u, ///< Receive buffer overflow + IccIdleTimerRun = 7u, ///< Idle timer running + IccReadFifoOverrun = 8u, ///< Read FIFO overflow + IccReadFifoFull = 9u, ///< Read FIFO full + IccWriteFifoEmpty = 10u, ///< Write FIFO empty + IccRxStartErr = 11u, ///< Receive start bit error + IccTxResend = 12u, ///< Trasmit detect resend + IccRxResend = 13u, ///< Receive detect resend + +}en_icc_status_t; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +/// Enumeration to define an index for each enabled Icc instance +typedef enum en_icc_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_ICC0 == PDL_ON) + IccInstanceIndexIcc0, +#endif +#if (PDL_PERIPHERAL_ENABLE_ICC1 == PDL_ON) + IccInstanceIndexIcc1, +#endif + IccInstanceIndexMax, + IccInstanceIndexUnknown = 0xFFu, +} en_icc_instance_index_t; + +/** \} GroupICC_Types */ + +/** +* \addtogroup GroupICC_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief ICC interrupt enable structure + ******************************************************************************/ +typedef struct stc_icc_irq_en +{ + boolean_t bRxFullIrq; ///< Receive buffer full interrupt + boolean_t bTxEmptyIrq; ///< Transmit buffer empty interrupt + boolean_t bRxStartBitIrq; ///< Receive start bit detected interrupt + boolean_t bCardEventIrq; ///< Card insert/pull out interrupt + boolean_t bIdleTimerIrq; ///< Idle timer interrupt + boolean_t bReadFifoIrq; ///< Receive FIFO interrupt + boolean_t bWriteFifoIrq; ///< Transfer FIFO interrupt + boolean_t bReadFifoOverrunIrq; ///< Receive FIFO overrun interrupt + +}stc_icc_irq_en_t; + +/** + ****************************************************************************** + ** \brief ICC interrupt callback function + ******************************************************************************/ +typedef struct stc_icc_irq_cb +{ + func_ptr_t pfnRxFullIrqCb; ///< Receive buffer full interrupt callback function pointer + func_ptr_t pfnTxEmptyIrqCb; ///< Transmit buffer empty interrupt callback function pointer + func_ptr_t pfnRxStartBitIrqCb; ///< Receive start bit detected interrupt callback function pointer + func_ptr_t pfnCardEventIrqCb; ///< Card insert/pull out interrupt callback function pointer + func_ptr_t pfnIdleTimerIrqCb; ///< Idle timer interrupt callback function pointer + func_ptr_t pfnReadFifoIrqCb; ///< Receive FIFO interrupt callback function pointer + func_ptr_t pfnWriteFifoIrqCb; ///< Transfer FIFO interrupt callback function pointer + func_ptr_t pfnReadFifoOverrunIrqCb; ///< Receive FIFO overrun interrupt callback function pointer + +}stc_icc_irq_cb_t, stc_icc_intern_data_t; + +/** + ****************************************************************************** + ** \brief ICC FIFO configuration. + ******************************************************************************/ +typedef struct stc_icc_fifo_config +{ + uint8_t TxFifoLevel; ///< Transfer data FIFO level + uint8_t RxFifoLevel; ///< Receive data FIFO level +} stc_icc_fifo_config_t; + +/** + ****************************************************************************** + ** \brief ICC configuration structure + ******************************************************************************/ +typedef struct stc_icc_config +{ + uint16_t u16ClkDiv; ///< Clock division of card clock. (Card clock = PCLK/u16ClkDiv) + uint16_t u16BaudRate; ///< Baud rate value, which is F/D. (1 ETU = (F/D) * (1/CardClock[Hz])) + en_icc_tx_data_t enTxDataFormat; ///< Transmit data format + en_icc_rx_data_t enRxDataFormat; ///< Receive data format + boolean_t bUseGuardTimer; ///< TRUE: enable guard timer, FALSE: disable guard timer. + uint8_t u8GuardTime; ///< Guard time + en_icc_idletmrclk_t enIdleTimerSrcClk; ///< Source clock of idle timer + uint16_t u16IdleTimerCnt; ///< Idle timer count + en_icc_data_dir_t enBitDirection; ///< ICC data direction + boolean_t bInvertData; ///< Inversion of the output data + boolean_t bDataResend; ///< TRUE: data resend enabled, FALSE: data resend disabled + boolean_t bClkPinMode; ///< TRUE: ICx_CLK pin controlled by software, FALSE: ICx_CLK pin controlled by hardware + boolean_t bDataPinMode; ///< TRUE: ICx_DATA pin controlled by software, FALSE: ICx_DATA pin controlled by hardware + boolean_t bVpenPinOutputEn; ///< TRUE: enable ICx_VPEN output, FALSE: dsiable ICx_VPEN output + boolean_t bVccPinOutputEn; ///< TRUE: enable ICx_VCC output, FALSE: dsiable ICx_VCC output + boolean_t bRstPinOutputEn; ///< TRUE: enable ICx_RST output, FALSE: dsiable ICx_RST output + boolean_t bDataPinOutputEn; ///< TRUE: enable ICx_DATA output, FALSE: dsiable ICx_DATA output + boolean_t bClkPinOutputEn; ///< TRUE: enable ICx_CLK output, FALSE: dsiable ICx_CLK output + boolean_t bVpenPinLevel; ///< ICx_VPEN Pin level (Only valid when output is enabled) + boolean_t bVccPinLevel; ///< ICx_VCC Pin level (Only valid when output is enabled) + boolean_t bRstPinLevel; ///< ICx_RST Pin level (Only valid when output is enabled) + boolean_t bDataPinLevel; ///< ICx_DATA Pin level (Only valid when output is enabled and Data pin mode is set to software control) + boolean_t bClkPinLevel; ///< ICx_CLK Pin level (Only valid when output is enabled and Clock pin mode is set to software control) + stc_icc_fifo_config_t *pstcFifoConfig; ///< Pointer to FIFO configuration structure, FIFO is not used when set to NULL + +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) + stc_icc_irq_en_t *pstcIrqEn; ///< Pointer to ICC interrupt enable structure, if set to NULL, no interrupt enabled. + stc_icc_irq_cb_t *pstcIrqCb; ///< Pointer to ICC interrupt callback functions structurei, f set to NULL, no interrupt callback initialized. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif + +} stc_icc_config_t; + +/// ICC instance data type +typedef struct stc_icc_instance_data +{ + volatile stc_iccn_t* pstcInstance; ///< pointer to registers of an instance + stc_icc_intern_data_t stcInternData; ///< module internal data of instance +} stc_icc_instance_data_t; + +/** \} GroupICC_DataStructures */ + +/** +* \addtogroup GroupICC_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ +/// Look-up table for all enabled Icc instances and their internal data +extern stc_icc_instance_data_t m_astcIccInstanceDataLut[ICC_INSTANCE_COUNT]; + +/** \} GroupICC_GlobalVariables */ + +/** +* \addtogroup GroupICC_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_ICC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_ICC1 == PDL_ON) +// Interrupt +void Icc_IrqHandler(volatile stc_iccn_t* pstcIcc, + stc_icc_intern_data_t* pstcIccInternData); +en_result_t Icc_EnableIrq(volatile stc_iccn_t* pstcIcc, + en_icc_irq_sel_t enIrqSel); +en_result_t Icc_DisableIrq(volatile stc_iccn_t* pstcIcc, + en_icc_irq_sel_t enIrqSel); +#endif + +// Init/De-Init +en_result_t Icc_Init(volatile stc_iccn_t* pstcIcc, + const stc_icc_config_t* pstcConfig); +en_result_t Icc_DeInit(volatile stc_iccn_t* pstcIcc, + boolean_t bTouchNvic); + +// Function enable/disable +en_result_t Icc_Enable(volatile stc_iccn_t* pstcIcc); +en_result_t Icc_Disable(volatile stc_iccn_t* pstcIcc); + +// Baud rate +en_result_t Icc_SetBaudRate(volatile stc_iccn_t* pstcIcc, + uint16_t u16BaudRate); + +// Status read +boolean_t Icc_GetStatus(volatile stc_iccn_t* pstcIcc, + en_icc_status_t enStatus); +boolean_t Icc_GetIrqStatus(volatile stc_iccn_t* pstcIcc, + en_icc_irq_sel_t enIrqSel); + +// Data read/write +en_result_t Icc_SendData(volatile stc_iccn_t* pstcIcc, uint16_t Data); +en_result_t Icc_SendFifoData(volatile stc_iccn_t* pstcIcc, uint16_t Data); +uint16_t Icc_ReceiveData(volatile stc_iccn_t* pstcIcc); +uint16_t Icc_ReceiveFifoData(volatile stc_iccn_t* pstcIcc); + +// FIFO +en_result_t Icc_ClearWriteFifo (volatile stc_iccn_t* pstcIcc); +en_result_t Icc_ClearReadFifo (volatile stc_iccn_t* pstcIcc); +en_result_t Icc_SetWriteFifoLevel(volatile stc_iccn_t* pstcIcc, uint8_t u8Level); +en_result_t Icc_SetReadFifoLevel(volatile stc_iccn_t* pstcIcc, uint8_t u8Level); +uint8_t Icc_GetWriteFifoCurCnt(volatile stc_iccn_t* pstcIcc); +uint8_t Icc_GetReadFifoCurCnt(volatile stc_iccn_t* pstcIcc); + +// IO +en_result_t Icc_SetVpenPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel); +en_result_t Icc_SetVccPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel); +en_result_t Icc_SetRstPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel); +en_result_t Icc_SetDataPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel); +en_result_t Icc_SetClkPinLevel (volatile stc_iccn_t* pstcIcc, + boolean_t bLevel); + +// Idle timer +en_result_t Icc_SetIdleTimerCnt(volatile stc_iccn_t* pstcIcc, uint16_t u16Cnt); +en_result_t Icc_StartIdleTimer(volatile stc_iccn_t* pstcIcc); +en_result_t Icc_StopIdleTimer(volatile stc_iccn_t* pstcIcc); + +/** \} GroupICC_Functions */ +/** \} GroupICC */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_ICC_ACTIVE)) */ + +#endif /* __ICC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p.h new file mode 100644 index 0000000000..67e2f8cb3a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p.h @@ -0,0 +1,356 @@ +/******************************************************************************* +* \file interrupts_fm0.h +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + #ifndef __INTERRUPTS_FM0P_H__ +#define __INTERRUPTS_FM0P_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "pdl_user.h" + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Check whether interrupt is enable when peripheral is inactive */ +/*****************************************************************************/ + +// Include adc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) + #if defined(PDL_PERIPHERAL_ADC_ACTIVE) + #include "adc/adc.h" + #else + #error Do not enable ADC interrupt when it is inactive. + #endif +#endif + +// Include bt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + #if defined(PDL_PERIPHERAL_BT_ACTIVE) + #include "bt/bt.h" + #else + #error Do not enable BT interrupt when it is inactive. + #endif +#endif + +// Include clk.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + #if defined(PDL_PERIPHERAL_CLK_ACTIVE) + #include "clk/clk.h" + #else + #error Do not enable CLK interrupt when it is inactive. + #endif +#endif + +// Include csv.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) + #if defined(PDL_PERIPHERAL_CSV_ACTIVE) + #include "csv/csv.h" + #else + #error Do not enable CSV interrupt when it is inactive. + #endif +#endif + +// Include dma.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) + #if defined(PDL_PERIPHERAL_DMA_ACTIVE) + #include "dma/dma.h" + #else + #error Do not enable DMA interrupt when it is inactive. + #endif +#endif + +// Include dt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + #if defined(PDL_PERIPHERAL_DT_ACTIVE) + #include "dt/dt.h" + #else + #error Do not enable DT interrupt when it is inactive. + #endif +#endif + +// Include exint.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + #if defined(PDL_PERIPHERAL_EXINT_ACTIVE) + #include "exint/exint.h" + #else + #error Do not enable EXINT interrupt when it is inactive. + #endif +#endif + +// Include NMI code in exint.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + #if defined(PDL_PERIPHERAL_NMI_ACTIVE) + #include "exint/exint.h" + #else + #error Do not enable NMI interrupt when it is inactive. + #endif +#endif + +// Include i2cs.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_I2CS0) + #if defined(PDL_PERIPHERAL_I2CS_ACTIVE) + #include "i2cs/i2cs.h" + #else + #error Do not enable I2CS interrupt when it is inactive. + #endif +#endif + +// Include icc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) + #if defined(PDL_PERIPHERAL_ICC_ACTIVE) + #include "icc/icc.h" + #else + #error Do not enable ICC interrupt when it is inactive. + #endif +#endif + +// Include lcd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) + #if defined(PDL_PERIPHERAL_LCD_ACTIVE) + #include "lcd/lcd.h" + #else + #error Do not enable LCD interrupt when it is inactive. + #endif +#endif + +// Include lvd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) + #if defined(PDL_PERIPHERAL_LVD_ACTIVE) + #include "lvd/lvd.h" + #else + #error Do not enable LVD interrupt when it is inactive. + #endif +#endif + +// Include main_flash.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + #if defined(PDL_PERIPHERAL_MAIN_FLASH_ACTIVE) + #include "flash/mainflash.h" + #else + #error Do not enable MAIN_FLASH interrupt when it is inactive. + #endif +#endif + +// Include mfs.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) + #if defined(PDL_PERIPHERAL_MFS_ACTIVE) + #include "mfs/mfs.h" + #else + #error Do not enable MFS interrupt when it is inactive. + #endif +#endif + +// Include mft_frt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) + #if defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE) + #include "mft/mft_frt.h" + #else + #error Do not enable MFT_FRT interrupt when it is inactive. + #endif +#endif + +// Include mft_icu.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) + #if defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE) + #include "mft/mft_icu.h" + #else + #error Do not enable MFT_ICU interrupt when it is inactive. + #endif +#endif + +// Include mft_ocu.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) + #if defined(PDL_PERIPHERAL_MFT_OCU_ACTIVE) + #include "mft/mft_ocu.h" + #else + #error Do not enable MFT_OCU interrupt when it is inactive. + #endif +#endif + +// Include mft_wfg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG_DTIF) + #if defined(PDL_PERIPHERAL_MFT_WFG_ACTIVE) + #include "mft/mft_wfg.h" + #else + #error Do not enable MFT_WFG interrupt when it is inactive. + #endif +#endif + +// Include ppg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) + #if defined(PDL_PERIPHERAL_PPG_ACTIVE) + #include "ppg/ppg.h" + #else + #error Do not enable PPG interrupt when it is inactive. + #endif +#endif + +// Include qprc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) + #if defined(PDL_PERIPHERAL_QPRC_ACTIVE) + #include "qprc/qprc.h" + #else + #error Do not enable QPRC interrupt when it is inactive. + #endif +#endif + +// Include rc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) + #if defined(PDL_PERIPHERAL_RC_ACTIVE) + #include "rc/rc.h" + #else + #error Do not enable RC interrupt when it is inactive. + #endif +#endif + +// Include rtc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) + #if defined(PDL_PERIPHERAL_RTC_ACTIVE) + #include "rtc/rtc.h" + #else + #error Do not enable RTC interrupt when it is inactive. + #endif +#endif + +// Include usb.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) + #if defined(PDL_PERIPHERAL_USB_ACTIVE) + #include "usb/usb.h" + #else + #error Do not enable USB interrupt when it is inactive. + #endif +#endif + +// Include wc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC) + #if defined(PDL_PERIPHERAL_WC_ACTIVE) + #include "wc/wc.h" + #else + #error Do not enable WC interrupt when it is inactive. + #endif +#endif + +// Include wdg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + #if defined(PDL_PERIPHERAL_WDG_ACTIVE) + #include "wdg/wdg.h" + #else + #error Do not enable WDG interrupt when it is inactive. + #endif +#endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) + #if defined(PDL_PERIPHERAL_DSTC_ACTIVE) + #include "dstc/dstc.h" + #else + #error Do not enable DSTC interrupt when it is inactive. + #endif + #endif +//@} // PdlInterrupts +#ifdef __cplusplus +} +#endif + +#endif // PDL_MCU_CORE == PDL_FM0P_CORE) + +#endif // #ifndef __INTERRUPTS_FM0P_H__ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_1-a.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_1-a.c new file mode 100644 index 0000000000..c3df194f09 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_1-a.c @@ -0,0 +1,952 @@ +/******************************************************************************* +* \file interrupts_fm0p_type_1-a.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm0p.h" + + #ifdef __INTERRUPTS_FM0P_TYPE_1_A_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************* FM0P: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM0P: CSV IRQ handler (IRQ#0) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM0P: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM0P: SWWDG IRQ handler (IRQ#1) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM0P: LVD IRQ handler (IRQ#2) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM0P: MFT0_WFG, MFT1_WFG, MFT2_WFG *********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_WFG, MFT1_WFG, MFT2_WFG IRQ handler (IRQ#3) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_1_2_WFG_DTIF_AVAILABLE) + void MFT0_1_2_WFG_DTIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ03MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG,&m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) + if (0ul != (u32IrqMon & 0x000000F0ul)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT1_WFG,&m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) + if (0ul != (u32IrqMon & 0x00000F00ul)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT2_WFG,&m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg2].stcInternData); + } + #endif + + } + #elif (1u == IRQ_MFT0_WFG_DTIF_AVAILABLE) + void MFT0_WFG_DTIF_IRQHandler(void) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG,&m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 ****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#4) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ04MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint2); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint3); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint4); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint5); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint6); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint7); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: DT0, QPRC0 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) +/** + ****************************************************************************** + ** \brief FM0P: DT0, QPRC0 IRQ handler (IRQ#6) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_DT_QPRC_AVAILABLE) + void DT_QPRC_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ06MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(1u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) + if (0ul != (u32IrqMon & 0x000000FCul)) + { + Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC0,&m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#7) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_AVAILABLE) + void MFS0_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ07MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#8) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFS0_TX_AVAILABLE) + void MFS0_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ08MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#9) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_AVAILABLE) + void MFS1_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ09MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#10) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFS1_TX_AVAILABLE) + void MFS1_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ10MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#13) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_AVAILABLE) + void MFS3_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#14) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFS3_TX_AVAILABLE) + void MFS3_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: DMA1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) +/** + ****************************************************************************** + ** \brief FM0P: DMA1 IRQ handler (IRQ#19) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_DMAC1_AVAILABLE) + void DMAC1_IRQHandler(void) + { + DmaIrqHandler(1u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: DMA0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) +/** + ****************************************************************************** + ** \brief FM0P: DMA0 IRQ handler (IRQ#20) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_DMAC0_AVAILABLE) + void DMAC0_IRQHandler(void) + { + DmaIrqHandler(0u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM0P: PPG IRQ handler (IRQ#23) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_04_08_10_12_16_18_20_AVAILABLE) + void PPG00_02_04_08_10_12_16_18_20_IRQHandler(void) + { + Ppg_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM0P: RTC0, WC0, CLK ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM0P: RTC0, WC0, CLK IRQ handler (IRQ#24) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0,&(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Wc_IrqHandler(&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: ADC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM0P: ADC0 IRQ handler (IRQ#25) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC0,&(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_FRT *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_FRT IRQ handler (IRQ#28) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_AVAILABLE) + void MFT0_FRT_IRQHandler(void) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT,&m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_ICU *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_ICU IRQ handler (IRQ#29) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_ICU_AVAILABLE) + void MFT0_ICU_IRQHandler(void) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU,&m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_OCU *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_OCU IRQ handler (IRQ#30) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_OCU_AVAILABLE) + void MFT0_OCU_IRQHandler(void) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU,&m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************** FM0P: BT0, BT1, BT2, BT3, FLASH ***********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM0P: BT0, BT1, BT2, BT3, FLASH IRQ handler (IRQ#31) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_BT0_3_FLASHIF_AVAILABLE) + void BT0_3_FLASHIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ31MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0,&m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1,&m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2,&m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3,&m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + if (0ul != (u32IrqMon & 0x08000000ul)) + { + PDL_DummyHandler(0ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: NMI, HWWDG ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM0P: NMI, HWWDG IRQ handler (EXC#2) Type 1-a + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM0P_TYPE_1-A_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_1-b.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_1-b.c new file mode 100644 index 0000000000..2a43f2d970 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_1-b.c @@ -0,0 +1,2134 @@ +/******************************************************************************* +* \file interrupts_fm0p_type_1-b.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm0p.h" + + #ifdef __INTERRUPTS_FM0P_TYPE_1_B_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: IRQ003SEL, 1: IRQ004SEL, 2: IRQ005SEL, 3: IRQ006SEL, 4: IRQ007SEL, + // 5: IRQ008SEL, 6: IRQ009SEL, 7: IRQ010SEL, 8: LCD, 9: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************* FM0P: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM0P: CSV IRQ handler (IRQ#0) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM0P: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM0P: SWWDG IRQ handler (IRQ#1) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM0P: LVD IRQ handler (IRQ#2) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ003SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ003SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ003SEL IRQ handler (IRQ#3) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ003SEL_AVAILABLE) + void IRQ003SEL_IRQHandler(void) + { + PDL_DummyHandler(0ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ004SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ004SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ004SEL IRQ handler (IRQ#4) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ004SEL_AVAILABLE) + void IRQ004SEL_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ005SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ005SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ005SEL IRQ handler (IRQ#5) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ005SEL_AVAILABLE) + void IRQ005SEL_IRQHandler(void) + { + PDL_DummyHandler(2ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ006SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ006SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ006SEL IRQ handler (IRQ#6) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ006SEL_AVAILABLE) + void IRQ006SEL_IRQHandler(void) + { + PDL_DummyHandler(3ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ007SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ007SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ007SEL IRQ handler (IRQ#7) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ007SEL_AVAILABLE) + void IRQ007SEL_IRQHandler(void) + { + PDL_DummyHandler(4ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ008SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ008SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ008SEL IRQ handler (IRQ#8) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ008SEL_AVAILABLE) + void IRQ008SEL_IRQHandler(void) + { + PDL_DummyHandler(5ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ009SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ009SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ009SEL IRQ handler (IRQ#9) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ009SEL_AVAILABLE) + void IRQ009SEL_IRQHandler(void) + { + PDL_DummyHandler(6ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: IRQ010SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ010SEL) +/** + ****************************************************************************** + ** \brief FM0P: IRQ010SEL IRQ handler (IRQ#10) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_IRQ010SEL_AVAILABLE) + void IRQ010SEL_IRQHandler(void) + { + PDL_DummyHandler(7ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************* FM0P: MFT0_WFG_DTIF, MFS8 **************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG_DTIF) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_WFG_DTIF, MFS8 IRQ handler (IRQ#11) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_MFS8_RX_TX_AVAILABLE) + void MFT0_WFG_DTIF_MFS8_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ11MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG_DTIF) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 ****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#12) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint2); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint3); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint4); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint5); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint6); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint7); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/* FM0P: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23, EXINT24, EXINT25, EXINT26, EXINT27, EXINT28, EXINT30, EXINT31 */ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) +/** + ****************************************************************************** + ** \brief FM0P: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23, EXINT24, EXINT25, EXINT26, EXINT27, EXINT28, EXINT30, EXINT31 IRQ handler (IRQ#13) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_EXINT8_31_AVAILABLE) + void EXINT8_31_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint8); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint9); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint10); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint11); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint12); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint13); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint14); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint15); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint16); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint17); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint18); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000800ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint19); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00001000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint20); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00002000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint21); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00004000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint22); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00008000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint23); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) + if (0ul != (u32IrqMon & 0x00010000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint24); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint25); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) + if (0ul != (u32IrqMon & 0x00040000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint26); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + if (0ul != (u32IrqMon & 0x00080000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint27); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00100000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint28); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint29); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) + if (0ul != (u32IrqMon & 0x00040000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint30); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + if (0ul != (u32IrqMon & 0x00080000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint31); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: DT0, QPRC0 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) +/** + ****************************************************************************** + ** \brief FM0P: DT0, QPRC0 IRQ handler (IRQ#14) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_DT_QPRC0_AVAILABLE) + void DT_QPRC0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(1u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) + if (0ul != (u32IrqMon & 0x000000FCul)) + { + Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC0, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#15) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_TX_AVAILABLE) + void MFS0_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#16) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_TX_AVAILABLE) + void MFS1_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: MFS2, MFS3 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS2, MFS3 IRQ handler (IRQ#17) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_TX_AVAILABLE) + void MFS2_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#18) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_TX_AVAILABLE) + void MFS3_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#19) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#20) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM0P: MFS5 IRQ handler (IRQ#21) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM0P: MFS5 IRQ handler (IRQ#22) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM0P: PPG IRQ handler (IRQ#23) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_04_08_10_12_14_16_18_20_AVAILABLE) + void PPG00_02_04_08_10_12_14_16_18_20_IRQHandler(void) + { + Ppg_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM0P: RTC0, WC0, CLK ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM0P: RTC0, WC0, CLK IRQ handler (IRQ#24) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Wc_IrqHandler(&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: ADC0, MFS9 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) +/** + ****************************************************************************** + ** \brief FM0P: ADC0, MFS9 IRQ handler (IRQ#25) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_ADC0_MFS9_RX_TX_AVAILABLE) + void ADC0_MFS9_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ25MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) + if (0ul != (u32IrqMon & 0x0000001Ful)) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: ADC1, MFS10 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) +/** + ****************************************************************************** + ** \brief FM0P: ADC1, MFS10 IRQ handler (IRQ#26) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_ADC1_MFS10_RX_TX_AVAILABLE) + void ADC1_MFS10_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ26MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) + if (0ul != (u32IrqMon & 0x0000001Ful)) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC1, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM0P: ADC2, LCD, MFS11 ***************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) +/** + ****************************************************************************** + ** \brief FM0P: ADC2, LCD, MFS11 IRQ handler (IRQ#27) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_ADC2_LCDC_MFS11_RX_TX_AVAILABLE) + void ADC2_LCDC_MFS11_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ27MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) + if (0ul != (u32IrqMon & 0x0000001Ful)) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC2, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc2].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + PDL_DummyHandler(8ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM0P: MFT0_FRT, MFT0_ICU, MFT0_OCU *********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_FRT, MFT0_ICU, MFT0_OCU IRQ handler (IRQ#28) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFT0_AVAILABLE) + void MFT0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ28MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) + if (0ul != (u32IrqMon & 0x000003C0ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) + if (0ul != (u32IrqMon & 0x0000FC00ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM0P: MFT1_FRT, MFT1_ICU, MFT1_OCU *********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) +/** + ****************************************************************************** + ** \brief FM0P: MFT1_FRT, MFT1_ICU, MFT1_OCU IRQ handler (IRQ#29) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFT1_AVAILABLE) + void MFT1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ29MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) + if (0ul != (u32IrqMon & 0x000003C0ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) + if (0ul != (u32IrqMon & 0x0000FC00ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************** FM0P: MFT2_FRT, MFT2_ICU, MFT2_OCU, DMA0, DMA1 ***************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) +/** + ****************************************************************************** + ** \brief FM0P: MFT2_FRT, MFT2_ICU, MFT2_OCU, DMA0, DMA1 IRQ handler (IRQ#30) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_MFT2_DMAC0_1_AVAILABLE) + void MFT2_DMAC0_1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ30MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) + if (0ul != (u32IrqMon & 0x000003C0ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) + if (0ul != (u32IrqMon & 0x0000FC00ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) ||(PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) + if (0ul != (u32IrqMon & 0x00010000ul)) + { + DmaIrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) ||(PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + DmaIrqHandler(1u); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************ FM0P: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH *************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM0P: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH IRQ handler (IRQ#31) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_BT0_7_FLASHIF_AVAILABLE) + void BT0_7_FLASHIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ31MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + if (0ul != (u32IrqMon & 0x08000000ul)) + { + PDL_DummyHandler(9ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: NMI, HWWDG ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM0P: NMI, HWWDG IRQ handler (EXC#2) Type 1-b + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM0P_TYPE_1-B_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_2-a.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_2-a.c new file mode 100644 index 0000000000..9e30af75bc --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_2-a.c @@ -0,0 +1,2385 @@ +/******************************************************************************* +* \file interrupts_fm0p_type_2-a.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm0p.h" + +#ifdef __INTERRUPTS_FM0P_TYPE_2_A_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: DSTC, 1: LCD, 2: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************* FM0P: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM0P: CSV IRQ handler (IRQ#0) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM0P: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM0P: SWWDG IRQ handler (IRQ#1) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM0P: LVD IRQ handler (IRQ#2) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_WFG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_WFG IRQ handler (IRQ#3) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_AVAILABLE) + void MFT0_WFG_DTIF_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG54) + + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 ****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#4) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ04MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT0)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT1)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT2)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT3)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT4)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT5)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT5); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT6)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT6); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT7)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT7); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT0) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT1) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT2) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT3) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT4) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT5) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT6) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT7) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(1u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(2u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(3u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(4u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(5u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(6u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(7u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/* FM0P: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23 */ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) +/** + ****************************************************************************** + ** \brief FM0P: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23 IRQ handler (IRQ#5) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_EXINT8_23_AVAILABLE) + void EXINT8_23_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ05MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT8)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT8); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT9)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT9); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT10)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT11)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT11); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT12)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT8) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT9) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT10) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT11) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT12) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(8u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(9u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(10u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(11u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(12u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(13u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(14u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(15u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + Exint_IrqHandler(16u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Exint_IrqHandler(17u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Exint_IrqHandler(18u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000800ul)) + { + Exint_IrqHandler(19u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00001000ul)) + { + Exint_IrqHandler(20u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00002000ul)) + { + Exint_IrqHandler(21u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00004000ul)) + { + Exint_IrqHandler(22u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00008000ul)) + { + Exint_IrqHandler(23u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: DT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) +/** + ****************************************************************************** + ** \brief FM0P: DT0 IRQ handler (IRQ#6) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_DT_AVAILABLE) + void DT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ06MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(1u); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#7) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_AVAILABLE) + void MFS0_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ07MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#8) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS0_TX_AVAILABLE) + void MFS0_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ08MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS0_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#9) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_AVAILABLE) + void MFS1_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ09MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#10) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS1_TX_AVAILABLE) + void MFS1_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ10MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS1_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM0P: MFS2 IRQ handler (IRQ#11) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_AVAILABLE) + void MFS2_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ11MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS2_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM0P: MFS2 IRQ handler (IRQ#12) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS2_TX_AVAILABLE) + void MFS2_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS2_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#13) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_AVAILABLE) + void MFS3_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#14) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS3_TX_AVAILABLE) + void MFS3_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS3_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#15) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#16) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS4_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM0P: MFS5 IRQ handler (IRQ#17) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS5_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM0P: MFS5 IRQ handler (IRQ#18) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS5_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS6 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM0P: MFS6 IRQ handler (IRQ#19) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS6_RX_AVAILABLE) + void MFS6_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS6_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS6 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM0P: MFS6 IRQ handler (IRQ#20) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS6_TX_AVAILABLE) + void MFS6_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS6_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS7 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM0P: MFS7 IRQ handler (IRQ#21) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS7_RX_AVAILABLE) + void MFS7_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS7_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS7 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM0P: MFS7 IRQ handler (IRQ#22) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFS7_TX_AVAILABLE) + void MFS7_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS7_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************* FM0P: PPG, RC0, ICC0, DSTC *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) +/** + ****************************************************************************** + ** \brief FM0P: PPG, RC0, ICC0, DSTC IRQ handler (IRQ#23) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_20_DSTC_SMCIF0_HDMICEC0_AVAILABLE) + void PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ23MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG0)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG2)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG4)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG0) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG2) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG4) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) + if (0ul != (u32IrqMon & 0x000001FFul)) + { + Ppg_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + RcIrqHandler((stc_rcn_t*) &RC0, &(m_astcRcInstanceDataLut[RcInstanceIndexRc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC0, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + PDL_DummyHandler(0ul); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************** FM0P: ICC1, RC1, RTC0, WC0, CLK ***********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM0P: ICC1, RC1, RTC0, WC0, CLK IRQ handler (IRQ#24) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_TIM_SMCIF1_HDMICEC1_AVAILABLE) + void TIM_SMCIF1_HDMICEC1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_WC0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC0)) + { + Dstc_WcIrqHandler(); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_WC0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC1, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + RcIrqHandler((stc_rcn_t*) &RC1, &(m_astcRcInstanceDataLut[RcInstanceIndexRc1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Wc_IrqHandler((stc_wcn_t*)&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Clk_IrqHandler(); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: ADC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM0P: ADC0 IRQ handler (IRQ#25) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC0_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC0_PRIO, DSTC_IRQ_NUMBER_ADC0_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC0_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: USB0_DEVICE IRQ handler (IRQ#26) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_USB0_F_AVAILABLE) + void USB0_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: LCD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) +/** + ****************************************************************************** + ** \brief FM0P: LCD IRQ handler (IRQ#27) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_LCDC_AVAILABLE) + void LCDC_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_FRT *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_FRT IRQ handler (IRQ#28) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_AVAILABLE) + void MFT0_FRT_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM0P: MFT0_ICU, USB0_DEVICE *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_ICU, USB0_DEVICE IRQ handler (IRQ#29) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_USB0_F_MFT0_ICU_AVAILABLE) + void USB0_F_MFT0_ICU_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ29MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU3) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) + if (0ul != (u32IrqMon & 0x000001F0ul)) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_OCU *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_OCU IRQ handler (IRQ#30) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_MFT0_OCU_AVAILABLE) + void MFT0_OCU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************ FM0P: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH *************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM0P: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH IRQ handler (IRQ#31) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_BT0_7_FLASHIF_AVAILABLE) + void BT0_7_FLASHIF_IRQHandler(void) + { + + #if(PDL_ON != PDL_DSTC_ENABLE_BT0_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT1_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT2_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT3_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT4_IRQ0) + + uint32_t u32IrqMon = FM_INTREQ->IRQ31MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + if (0ul != (u32IrqMon & 0x08000000ul)) + { + PDL_DummyHandler(2ul); + } + #endif + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT0_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT0_IRQ0, DSTC_IRQ_NUMBER_BT0_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT1_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT1_IRQ0, DSTC_IRQ_NUMBER_BT1_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT2_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT2_IRQ0, DSTC_IRQ_NUMBER_BT2_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT3_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT3_IRQ0, DSTC_IRQ_NUMBER_BT3_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT4_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT4_IRQ0, DSTC_IRQ_NUMBER_BT6_IRQ0); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: NMI, HWWDG ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM0P: NMI, HWWDG IRQ handler (EXC#2) Type 2-a + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM0P_TYPE_2-A_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_2-b.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_2-b.c new file mode 100644 index 0000000000..21cc77d3ea --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_2-b.c @@ -0,0 +1,2140 @@ +/******************************************************************************* +* \file interrupts_fm0p_type_2-b.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm0p.h" + +#ifdef __INTERRUPTS_FM0P_TYPE_2_B_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: RCINTSEL0, 1: RCINTSEL1, 2: RCINTSEL2, 3: RCINTSEL3, 4: RCINTSEL4, + // 5: RCINTSEL5, 6: RCINTSEL6, 7: RCINTSEL7, 8: DSTC, 9: LCD, 10: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************* FM0P: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM0P: CSV IRQ handler (IRQ#0) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM0P: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM0P: SWWDG IRQ handler (IRQ#1) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM0P: LVD IRQ handler (IRQ#2) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL0 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL0) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL0 IRQ handler (IRQ#3) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL0_AVAILABLE) + void RCINTSEL0_IRQHandler(void) + { + PDL_DummyHandler(0ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL1 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL1) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL1 IRQ handler (IRQ#4) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL1_AVAILABLE) + void RCINTSEL1_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL2 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL2) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL2 IRQ handler (IRQ#5) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL2_AVAILABLE) + void RCINTSEL2_IRQHandler(void) + { + PDL_DummyHandler(2ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL3 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL3) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL3 IRQ handler (IRQ#6) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL3_AVAILABLE) + void RCINTSEL3_IRQHandler(void) + { + PDL_DummyHandler(3ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL4 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL4) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL4 IRQ handler (IRQ#7) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL4_AVAILABLE) + void RCINTSEL4_IRQHandler(void) + { + PDL_DummyHandler(4ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL5 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL5) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL5 IRQ handler (IRQ#8) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL5_AVAILABLE) + void RCINTSEL5_IRQHandler(void) + { + PDL_DummyHandler(5ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL6 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL6) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL6 IRQ handler (IRQ#9) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL6_AVAILABLE) + void RCINTSEL6_IRQHandler(void) + { + PDL_DummyHandler(6ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: RCINTSEL7 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL7) +/** + ****************************************************************************** + ** \brief FM0P: RCINTSEL7 IRQ handler (IRQ#10) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL7_AVAILABLE) + void RCINTSEL7_IRQHandler(void) + { + PDL_DummyHandler(7ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: MFT0_WFG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_WFG IRQ handler (IRQ#11) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_AVAILABLE) + void MFT0_WFG_DTIF_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG54) + + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 ****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM0P: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#12) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT0)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT1)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT2)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT3)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT4)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT5)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT5); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT6) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT6)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT6); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT7) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT7)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT7); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT0) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT1) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT2) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT3) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT4) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT5) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT6) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT7) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(1u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(2u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(3u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(4u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(5u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(6u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(7u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/* FM0P: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23 */ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) +/** + ****************************************************************************** + ** \brief FM0P: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23 IRQ handler (IRQ#13) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_EXINT8_23_AVAILABLE) + void EXINT8_23_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT8)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT8); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT9) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT9)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT9); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT10)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT11) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT11)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT11); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT12)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT8) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT9) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT10) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT11) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT12) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(8u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(9u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(10u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(11u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(12u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(13u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(14u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(15u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + Exint_IrqHandler(16u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Exint_IrqHandler(17u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Exint_IrqHandler(18u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000800ul)) + { + Exint_IrqHandler(19u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00001000ul)) + { + Exint_IrqHandler(20u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00002000ul)) + { + Exint_IrqHandler(21u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00004000ul)) + { + Exint_IrqHandler(22u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00008000ul)) + { + Exint_IrqHandler(23u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: DT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) +/** + ****************************************************************************** + ** \brief FM0P: DT0 IRQ handler (IRQ#14) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_DT_AVAILABLE) + void DT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(1u); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#15) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_TX_AVAILABLE) + void MFS0_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS0_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#16) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_TX_AVAILABLE) + void MFS1_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS1_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM0P: MFS2 IRQ handler (IRQ#17) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_TX_AVAILABLE) + void MFS2_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS2_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS2_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS2_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#18) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_TX_AVAILABLE) + void MFS3_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS3_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#19) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#20) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM0P: MFS5 IRQ handler (IRQ#21) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS5_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM0P: MFS5 IRQ handler (IRQ#22) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS5_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************* FM0P: PPG, RC0, ICC0, DSTC *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) +/** + ****************************************************************************** + ** \brief FM0P: PPG, RC0, ICC0, DSTC IRQ handler (IRQ#23) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_04_DSTC_SMCIF0_HDMICEC0_AVAILABLE) + void PPG00_02_04_DSTC_SMCIF0_HDMICEC0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ23MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG4)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG4) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Ppg_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + RcIrqHandler((stc_rcn_t*) &RC0, &(m_astcRcInstanceDataLut[RcInstanceIndexRc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC0, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + PDL_DummyHandler(8ul); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************** FM0P: ICC1, RC1, RTC0, WC0, CLK ***********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM0P: ICC1, RC1, RTC0, WC0, CLK IRQ handler (IRQ#24) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_TIM_SMCIF1_HDMICEC1_AVAILABLE) + void TIM_SMCIF1_HDMICEC1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_WC0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC0)) + { + Dstc_WcIrqHandler(); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_WC0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC1, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + RcIrqHandler((stc_rcn_t*) &RC1, &(m_astcRcInstanceDataLut[RcInstanceIndexRc1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Wc_IrqHandler((stc_wcn_t*)&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Clk_IrqHandler(); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: ADC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM0P: ADC0 IRQ handler (IRQ#25) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC0_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC0_PRIO, DSTC_IRQ_NUMBER_ADC0_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC0_PRIO) + + AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM0P: USB0_HOST, USB0_DEVICE ************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: USB0_HOST, USB0_DEVICE IRQ handler (IRQ#26) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_USB0_H_F_AVAILABLE) + void USB0_H_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: LCD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) +/** + ****************************************************************************** + ** \brief FM0P: LCD IRQ handler (IRQ#27) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_LCDC_AVAILABLE) + void LCDC_IRQHandler(void) + { + PDL_DummyHandler(9ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM0P: MFT0_FRT, MFT0_ICU, MFT0_OCU *********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM0P: MFT0_FRT, MFT0_ICU, MFT0_OCU IRQ handler (IRQ#28) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_ICU_OCU_AVAILABLE) + void MFT0_FRT_ICU_OCU_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ28MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU5) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) + if (0ul != (u32IrqMon & 0x000003C0ul)) + { + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) + if (0ul != (u32IrqMon & 0x0000FC00ul)) + { + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: USB0_DEVICE IRQ handler (IRQ#29) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_USB0_F_AVAILABLE) + void USB0_F_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EP1_DRQ) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EP1_DRQ)) + { + Dstc_Usb0_F_IrqHandler(DSTC_IRQ_NUMBER_EP1_DRQ); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EP2_DRQ) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EP2_DRQ)) + { + Dstc_Usb0_F_IrqHandler(DSTC_IRQ_NUMBER_EP2_DRQ); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EP3_DRQ) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EP3_DRQ)) + { + Dstc_Usb0_F_IrqHandler(DSTC_IRQ_NUMBER_EP3_DRQ); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EP4_DRQ) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EP4_DRQ)) + { + Dstc_Usb0_F_IrqHandler(DSTC_IRQ_NUMBER_EP4_DRQ); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EP5_DRQ) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EP5_DRQ)) + { + Dstc_Usb0_F_IrqHandler(DSTC_IRQ_NUMBER_EP5_DRQ); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EP1_DRQ) && \ + (PDL_ON != PDL_DSTC_ENABLE_EP2_DRQ) && \ + (PDL_ON != PDL_DSTC_ENABLE_EP3_DRQ) && \ + (PDL_ON != PDL_DSTC_ENABLE_EP4_DRQ) && \ + (PDL_ON != PDL_DSTC_ENABLE_EP5_DRQ) + + Usb_IrqHandler((stc_usb_t*)&USB0); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************ FM0P: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH *************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM0P: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH IRQ handler (IRQ#31) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_BT0_7_FLASHIF_AVAILABLE) + void BT0_7_FLASHIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ31MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT0_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT0_IRQ0, DSTC_IRQ_NUMBER_BT0_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT1_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT1_IRQ0, DSTC_IRQ_NUMBER_BT1_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT2_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT2_IRQ0, DSTC_IRQ_NUMBER_BT2_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT3_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT3_IRQ0, DSTC_IRQ_NUMBER_BT3_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT4_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT4_IRQ0, DSTC_IRQ_NUMBER_BT6_IRQ0); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT0_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT1_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT2_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT3_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT4_IRQ0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + if (0ul != (u32IrqMon & 0x08000000ul)) + { + PDL_DummyHandler(12ul); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: NMI, HWWDG ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM0P: NMI, HWWDG IRQ handler (EXC#2) Type 2-b + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM0P_TYPE_2-B_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_3.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_3.c new file mode 100644 index 0000000000..820610c392 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm0p_type_3.c @@ -0,0 +1,1797 @@ +/******************************************************************************* +* \file interrupts_fm0p_type_3.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm0p.h" + +#ifdef __INTERRUPTS_FM0P_TYPE_3_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: FLASH, 1: DSTC, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/*************************** FM0P: CSV, SWWDG, LVD ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM0P: CSV, SWWDG, LVD IRQ handler (IRQ#0) Type 3 + ******************************************************************************/ + #if (1u == IRQ_CSV_SWDT_LVD_AVAILABLE) + void CSV_SWDT_LVD_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ00MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Csv_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + SwwdgIrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Lvd_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS0 IRQ handler (IRQ#1) Type 3 + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_TX_AVAILABLE) + void MFS0_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ01MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS0_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM0P: MFS1 IRQ handler (IRQ#2) Type 3 + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_TX_AVAILABLE) + void MFS1_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ02MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS1_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM0P: MFS3 IRQ handler (IRQ#4) Type 3 + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_TX_AVAILABLE) + void MFS3_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ04MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS3_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM0P: MFS4 IRQ handler (IRQ#5) Type 3 + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_TX_AVAILABLE) + void MFS4_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ05MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS4_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: MFS6, I2CS0 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2CS0) +/** + ****************************************************************************** + ** \brief FM0P: MFS6, I2CS0 IRQ handler (IRQ#7) Type 3 + ******************************************************************************/ + #if (1u == IRQ_MFS6_RX_TX_I2CSLAVE_AVAILABLE) + void MFS6_RX_TX_I2CSLAVE_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ07MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS6_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS6_TX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_I2CS0_TX)) + { + Dstc_I2csIrqHandler(DSTC_IRQ_NUMBER_I2CS0_TX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_I2CS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_I2CS0_RX)) + { + Dstc_I2csIrqHandler(DSTC_IRQ_NUMBER_I2CS0_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS6_TX) && \ + (PDL_ON != PDL_DSTC_ENABLE_I2CS0_TX) && \ + (PDL_ON != PDL_DSTC_ENABLE_I2CS0_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2CS0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + I2csIrqHandlerRx((stc_i2csn_t*) &I2CS0, &m_astcI2csInstanceDataLut[0u].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2CS0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + I2csIrqHandlerTx((stc_i2csn_t*) &I2CS0, &m_astcI2csInstanceDataLut[0u].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2CS0) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + I2csIrqHandlerStatus((stc_i2csn_t*) &I2CS0, &m_astcI2csInstanceDataLut[0u].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: MFS7 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM0P: MFS7 IRQ handler (IRQ#8) Type 3 + ******************************************************************************/ + #if (1u == IRQ_MFS7_RX_TX_AVAILABLE) + void MFS7_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ08MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS7_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_TX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS7_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFS7_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: ADC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM0P: ADC0 IRQ handler (IRQ#9) Type 3 + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC0_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC0_PRIO, DSTC_IRQ_NUMBER_ADC0_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC0_PRIO) + + AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: USB0_DEVICE IRQ handler (IRQ#10) Type 3 + ******************************************************************************/ + #if (1u == IRQ_USB0_F_ED123_AVAILABLE) + void USB0_F_ED123_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: USB0_DEVICE IRQ handler (IRQ#11) Type 3 + ******************************************************************************/ + #if (1u == IRQ_USB0_F_ED450I_AVAILABLE) + void USB0_F_ED450I_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM0P: USB0_DEVICE IRQ handler (IRQ#12) Type 3 + ******************************************************************************/ + #if (1u == IRQ_USB0_F_ED0O_ST_AVAILABLE) + void USB0_F_ED0O_ST_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: USB0_HOST *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) +/** + ****************************************************************************** + ** \brief FM0P: USB0_HOST IRQ handler (IRQ#13) Type 3 + ******************************************************************************/ + #if (1u == IRQ_USB0_H_AVAILABLE) + void USB0_H_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: CLK **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM0P: CLK IRQ handler (IRQ#14) Type 3 + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + Clk_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: WC, RTC, DT0 *****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) +/** + ****************************************************************************** + ** \brief FM0P: WC, RTC, DT0 IRQ handler (IRQ#15) Type 3 + ******************************************************************************/ + #if (1u == IRQ_WC_RTC_DT_AVAILABLE) + void WC_RTC_DT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_WC0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC0)) + { + Dstc_WcIrqHandler(); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_WC0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Wc_IrqHandler((stc_wcn_t*)&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel1); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM0P: EXINT0, EXINT1 ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) +/** + ****************************************************************************** + ** \brief FM0P: EXINT0, EXINT1 IRQ handler (IRQ#16) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT0_1_AVAILABLE) + void EXINT0_1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT0)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT1)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT0) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT1) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(0u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(1u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM0P: EXINT2, EXINT3 ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) +/** + ****************************************************************************** + ** \brief FM0P: EXINT2, EXINT3 IRQ handler (IRQ#17) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT2_3_AVAILABLE) + void EXINT2_3_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT2)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT3)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT2) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT3) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(2u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(3u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM0P: EXINT4, EXINT5 ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) +/** + ****************************************************************************** + ** \brief FM0P: EXINT4, EXINT5 IRQ handler (IRQ#18) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT4_5_AVAILABLE) + void EXINT4_5_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT4)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT5)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT4) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT5) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(4u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(5u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM0P: EXINT6, EXINT7 ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM0P: EXINT6, EXINT7 IRQ handler (IRQ#19) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT6_7_AVAILABLE) + void EXINT6_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT6) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT6)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT6); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT7) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT7)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT7); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT6) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT7) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(6u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(7u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM0P: EXINT8 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) +/** + ****************************************************************************** + ** \brief FM0P: EXINT8 IRQ handler (IRQ#20) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT8_AVAILABLE) + void EXINT8_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT8)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT8); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT8) + + Exint_IrqHandler(8u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM0P: EXINT12, EXINT13 ***************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) +/** + ****************************************************************************** + ** \brief FM0P: EXINT12, EXINT13 IRQ handler (IRQ#22) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT12_13_AVAILABLE) + void EXINT12_13_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT12)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT12); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT13) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT13)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT13); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT12) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXTINT13) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(12u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(13u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: EXINT15 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) +/** + ****************************************************************************** + ** \brief FM0P: EXINT15 IRQ handler (IRQ#23) Type 3 + ******************************************************************************/ + #if (1u == IRQ_EXINT15_AVAILABLE) + void EXINT15_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXTINT15) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXTINT15)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXTINT15); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXTINT15) + + Exint_IrqHandler(15u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: BT0, BT4 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) +/** + ****************************************************************************** + ** \brief FM0P: BT0, BT4 IRQ handler (IRQ#24) Type 3 + ******************************************************************************/ + #if (1u == IRQ_BT0_4_AVAILABLE) + void BT0_4_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT0_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT0_IRQ0, DSTC_IRQ_NUMBER_BT0_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT4_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT4_IRQ0, DSTC_IRQ_NUMBER_BT4_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT0_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT4_IRQ0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: BT1, BT5 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) +/** + ****************************************************************************** + ** \brief FM0P: BT1, BT5 IRQ handler (IRQ#25) Type 3 + ******************************************************************************/ + #if (1u == IRQ_BT1_5_AVAILABLE) + void BT1_5_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ25MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT1_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT1_IRQ0, DSTC_IRQ_NUMBER_BT1_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT5_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT5_IRQ0, DSTC_IRQ_NUMBER_BT5_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT1_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT5_IRQ0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: BT2, BT6 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) +/** + ****************************************************************************** + ** \brief FM0P: BT2, BT6 IRQ handler (IRQ#26) Type 3 + ******************************************************************************/ + #if (1u == IRQ_BT2_6_AVAILABLE) + void BT2_6_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ26MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT2_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT2_IRQ0, DSTC_IRQ_NUMBER_BT2_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT6_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT6_IRQ0, DSTC_IRQ_NUMBER_BT6_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT2_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT6_IRQ0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: BT3, BT7 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) +/** + ****************************************************************************** + ** \brief FM0P: BT3, BT7 IRQ handler (IRQ#27) Type 3 + ******************************************************************************/ + #if (1u == IRQ_BT3_7_AVAILABLE) + void BT3_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ27MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT3_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT3_IRQ0, DSTC_IRQ_NUMBER_BT3_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT7_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT7_IRQ0, DSTC_IRQ_NUMBER_BT7_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT3_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT7_IRQ0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM0P: RC0, RC1 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) +/** + ****************************************************************************** + ** \brief FM0P: RC0, RC1 IRQ handler (IRQ#28) Type 3 + ******************************************************************************/ + #if (1u == IRQ_HDMICEC0_1_AVAILABLE) + void HDMICEC0_1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ28MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RC0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + RcIrqHandler((stc_rcn_t*) &RC0, &(m_astcRcInstanceDataLut[RcInstanceIndexRc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RC1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + RcIrqHandler((stc_rcn_t*) &RC1, &(m_astcRcInstanceDataLut[RcInstanceIndexRc1].stcInternData)); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM0P: ICC1, FLASH ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM0P: ICC1, FLASH IRQ handler (IRQ#29) Type 3 + ******************************************************************************/ + #if (1u == IRQ_SMCIF1_FLASHIF_AVAILABLE) + void SMCIF1_FLASHIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ29MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC1) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC1, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + PDL_DummyHandler(0ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM0P: DSTC *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) +/** + ****************************************************************************** + ** \brief FM0P: DSTC IRQ handler (IRQ#30) Type 3 + ******************************************************************************/ + #if (1u == IRQ_DSTC_AVAILABLE) + void DSTC_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM0P: NMI, HWWDG ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM0P: NMI, HWWDG IRQ handler (EXC#2) Type 3 + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM0P_TYPE_3_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3.h new file mode 100644 index 0000000000..0e03263c28 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3.h @@ -0,0 +1,377 @@ +/******************************************************************************* +* \file interrupts_fm3.h +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + #ifndef __INTERRUPTS_FM3_H__ +#define __INTERRUPTS_FM3_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "pdl_user.h" + +#if (PDL_MCU_CORE == PDL_FM3_CORE) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Check whether interrupt is enable when peripheral is inactive */ +/*****************************************************************************/ + +// Include adc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) + #if defined(PDL_PERIPHERAL_ADC_ACTIVE) + #include "adc/adc.h" + #else + #error Do not enable ADC interrupt when it is inactive! + #endif +#endif + +// Include bt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT15) + #if defined(PDL_PERIPHERAL_BT_ACTIVE) + #include "bt/bt.h" + #else + #error Do not enable BT interrupt when it is inactive! + #endif +#endif + +// Include can.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) + #if defined(PDL_PERIPHERAL_CAN_ACTIVE) + #include "can/can.h" + #else + #error Do not enable CAN interrupt when it is inactive! + #endif +#endif + +// Include cec.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) + #if defined(PDL_PERIPHERAL_CEC_ACTIVE) + #include "cec.h" + #else + #error Do not enable CEC interrupt when it is inactive! + #endif +#endif + +// Include clk.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + #if defined(PDL_PERIPHERAL_CLK_ACTIVE) + #include "clk/clk.h" + #else + #error Do not enable CLK interrupt when it is inactive! + #endif +#endif + +// Include csv.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) + #if defined(PDL_PERIPHERAL_CSV_ACTIVE) + #include "csv/csv.h" + #else + #error Do not enable CSV interrupt when it is inactive! + #endif +#endif + +// Include dma.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA7) + #if defined(PDL_PERIPHERAL_DMA_ACTIVE) + #include "dma/dma.h" + #else + #error Do not enable DMA interrupt when it is inactive! + #endif +#endif + +// Include dt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + #if defined(PDL_PERIPHERAL_DT_ACTIVE) + #include "dt/dt.h" + #else + #error Do not enable DT interrupt when it is inactive! + #endif +#endif + +// Include ether.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER1) + #if defined(PDL_PERIPHERAL_ETHER_ACTIVE) + #include "ether.h" + #else + #error Do not enable ETHER interrupt when it is inactive! + #endif +#endif + +// Include exint.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + #if defined(PDL_PERIPHERAL_EXINT_ACTIVE) + #include "exint/exint.h" + #else + #error Do not enable EXINT interrupt when it is inactive! + #endif +#endif + +// Include NMI code in exint.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + #if defined(PDL_PERIPHERAL_NMI_ACTIVE) + #include "exint/exint.h" + #else + #error Do not enable NMI interrupt when it is inactive. + #endif +#endif + +// Include lcd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) + #if defined(PDL_PERIPHERAL_LCD_ACTIVE) + #include "lcd/lcd.h" + #else + #error Do not enable LCD interrupt when it is inactive! + #endif +#endif + +// Include lvd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) + #if defined(PDL_PERIPHERAL_LVD_ACTIVE) + #include "lvd/lvd.h" + #else + #error Do not enable LVD interrupt when it is inactive! + #endif +#endif + +// Include main_flash.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + #if defined(PDL_PERIPHERAL_MAIN_FLASH_ACTIVE) + #include "flash/mainflash.h" + #else + #error Do not enable MAIN_FLASH interrupt when it is inactive! + #endif +#endif + +// Include mfs.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15) + #if defined(PDL_PERIPHERAL_MFS_ACTIVE) + #include "mfs/mfs.h" + #else + #error Do not enable MFS interrupt when it is inactive! + #endif +#endif + +// Include mft_frt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) + #if defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE) + #include "mft/mft_frt.h" + #else + #error Do not enable MFT_FRT interrupt when it is inactive! + #endif +#endif + +// Include mft_icu.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) + #if defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE) + #include "mft/mft_icu.h" + #else + #error Do not enable MFT_ICU interrupt when it is inactive! + #endif +#endif + +// Include mft_ocu.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) + #if defined(PDL_PERIPHERAL_MFT_OCU_ACTIVE) + #include "mft/mft_ocu.h" + #else + #error Do not enable MFT_OCU interrupt when it is inactive! + #endif +#endif + +// Include mft_wfg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG_DTIF) + #if defined(PDL_PERIPHERAL_MFT_WFG_ACTIVE) + #include "mft/mft_wfg.h" + #else + #error Do not enable MFT_WFG interrupt when it is inactive! + #endif +#endif + +// Include ppg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) + #if defined(PDL_PERIPHERAL_PPG_ACTIVE) + #include "ppg/ppg.h" + #else + #error Do not enable PPG interrupt when it is inactive! + #endif +#endif + +// Include qprc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC2) + #if defined(PDL_PERIPHERAL_QPRC_ACTIVE) + #include "qprc/qprc.h" + #else + #error Do not enable QPRC interrupt when it is inactive! + #endif +#endif + +// Include rtc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) + #if defined(PDL_PERIPHERAL_RTC_ACTIVE) + #include "rtc/rtc.h" + #else + #error Do not enable RTC interrupt when it is inactive! + #endif +#endif + +// Include usb.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_HOST) + #if defined(PDL_PERIPHERAL_USB_ACTIVE) + #include "usb/usb.h" + #else + #error Do not enable USB interrupt when it is inactive! + #endif +#endif + +// Include wc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC) + #if defined(PDL_PERIPHERAL_WC_ACTIVE) + #include "wc/wc.h" + #else + #error Do not enable WC interrupt when it is inactive! + #endif +#endif + +// Include wdg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + #if defined(PDL_PERIPHERAL_WDG_ACTIVE) + #include "wdg/wdg.h" + #else + #error Do not enable WDG interrupt when it is inactive! + #endif +#endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) + #if defined(PDL_PERIPHERAL_DSTC_ACTIVE) + #include "dstc/dstc.h" + #else + #error Do not enable DSTC interrupt when it is inactive! + #endif + #endif +//@} // PdlInterrupts +#ifdef __cplusplus +} +#endif + +#endif // PDL_MCU_CORE == PDL_FM3_CORE) + +#endif // #ifndef __INTERRUPTS_FM3_H__ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_a.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_a.c new file mode 100644 index 0000000000..e2f880c09b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_a.c @@ -0,0 +1,3962 @@ +/******************************************************************************* +* \file interrupts_fm3_type_a.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm3.h" + +#ifdef __INTERRUPTS_FM3_TYPE_A_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************** FM3: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM3: CSV IRQ handler (IRQ#0) Type a + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM3: SWWDG IRQ handler (IRQ#1) Type a + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM3: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM3: LVD IRQ handler (IRQ#2) Type a + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_WFG, MFT1_WFG, MFT2_WFG **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) +/** + ****************************************************************************** + ** \brief FM3: MFT0_WFG, MFT1_WFG, MFT2_WFG IRQ handler (IRQ#3) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_2_WFG_DTIF_AVAILABLE) + void MFT0_2_WFG_DTIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ03MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) + if (0ul != (u32IrqMon & 0x000000F0ul)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT1_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) + if (0ul != (u32IrqMon & 0x00000F00ul)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT2_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM3: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 *****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM3: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#4) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ04MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint2); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint3); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint4); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint5); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint6); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint7); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/* FM3: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23, EXINT24, EXINT25, EXINT26, EXINT27, EXINT28, EXINT30, EXINT31 */ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) +/** + ****************************************************************************** + ** \brief FM3: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23, EXINT24, EXINT25, EXINT26, EXINT27, EXINT28, EXINT30, EXINT31 IRQ handler (IRQ#5) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT8_31_AVAILABLE) + void EXINT8_31_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ05MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint8); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint9); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint10); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint11); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint12); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint13); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint14); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint15); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint16); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint17); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint18); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000800ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint19); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00001000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint20); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00002000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint21); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00004000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint22); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00008000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint23); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) + if (0ul != (u32IrqMon & 0x00010000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint24); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint25); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) + if (0ul != (u32IrqMon & 0x00040000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint26); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + if (0ul != (u32IrqMon & 0x00080000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint27); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00100000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint28); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint29); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) + if (0ul != (u32IrqMon & 0x00040000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint30); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + if (0ul != (u32IrqMon & 0x00080000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint31); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*********************** FM3: DT0, QPRC0, QPRC1, QPRC2 ************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC2) +/** + ****************************************************************************** + ** \brief FM3: DT0, QPRC0, QPRC1, QPRC2 IRQ handler (IRQ#6) Type a + ******************************************************************************/ + #if (1u == IRQ_DT_QPRC0_2_AVAILABLE) + void DT_QPRC0_2_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ06MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(DtChannel0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) + if (0ul != (u32IrqMon & 0x000000FCul)) + { + Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC0, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC1) + if (0ul != (u32IrqMon & 0x00003F00ul)) + { + Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC1, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC2) + if (0ul != (u32IrqMon & 0x000FC000ul)) + { + Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC2, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS0, MFS8 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) +/** + ****************************************************************************** + ** \brief FM3: MFS0, MFS8 IRQ handler (IRQ#7) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS0_8_RX_AVAILABLE) + void MFS0_8_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ07MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS0_RX_AVAILABLE) + void MFS0_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ07MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS0, MFS8 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) +/** + ****************************************************************************** + ** \brief FM3: MFS0, MFS8 IRQ handler (IRQ#8) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS0_8_TX_AVAILABLE) + void MFS0_8_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ08MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS0_TX_AVAILABLE) + void MFS0_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ08MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS1, MFS9 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) +/** + ****************************************************************************** + ** \brief FM3: MFS1, MFS9 IRQ handler (IRQ#9) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS1_9_RX_AVAILABLE) + void MFS1_9_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ09MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS1_RX_AVAILABLE) + void MFS1_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ09MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS1, MFS9 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) +/** + ****************************************************************************** + ** \brief FM3: MFS1, MFS9 IRQ handler (IRQ#10) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS1_9_TX_AVAILABLE) + void MFS1_9_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ10MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS1_TX_AVAILABLE) + void MFS1_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ10MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS2, MFS10 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) +/** + ****************************************************************************** + ** \brief FM3: MFS2, MFS10 IRQ handler (IRQ#11) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS2_10_RX_AVAILABLE) + void MFS2_10_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ11MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS2_RX_AVAILABLE) + void MFS2_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ11MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS2, MFS10 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) +/** + ****************************************************************************** + ** \brief FM3: MFS2, MFS10 IRQ handler (IRQ#12) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS2_10_TX_AVAILABLE) + void MFS2_10_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS2_TX_AVAILABLE) + void MFS2_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS3, MFS11 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) +/** + ****************************************************************************** + ** \brief FM3: MFS3, MFS11 IRQ handler (IRQ#13) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS3_11_RX_AVAILABLE) + void MFS3_11_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS3_RX_AVAILABLE) + void MFS3_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS3, MFS11 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) +/** + ****************************************************************************** + ** \brief FM3: MFS3, MFS11 IRQ handler (IRQ#14) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS3_11_TX_AVAILABLE) + void MFS3_11_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS3_TX_AVAILABLE) + void MFS3_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS4, MFS12 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12) +/** + ****************************************************************************** + ** \brief FM3: MFS4, MFS12 IRQ handler (IRQ#15) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS4_12_RX_AVAILABLE) + void MFS4_12_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS12_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS4, MFS12 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12) +/** + ****************************************************************************** + ** \brief FM3: MFS4, MFS12 IRQ handler (IRQ#16) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS4_12_TX_AVAILABLE) + void MFS4_12_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS12_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS5, MFS13 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13) +/** + ****************************************************************************** + ** \brief FM3: MFS5, MFS13 IRQ handler (IRQ#17) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS5_13_RX_AVAILABLE) + void MFS5_13_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS13_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS5, MFS13 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13) +/** + ****************************************************************************** + ** \brief FM3: MFS5, MFS13 IRQ handler (IRQ#18) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS5_13_TX_AVAILABLE) + void MFS5_13_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS13_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS6, MFS14 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14) +/** + ****************************************************************************** + ** \brief FM3: MFS6, MFS14 IRQ handler (IRQ#19) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS6_14_RX_AVAILABLE) + void MFS6_14_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS14_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS6_RX_AVAILABLE) + void MFS6_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS6, MFS14 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14) +/** + ****************************************************************************** + ** \brief FM3: MFS6, MFS14 IRQ handler (IRQ#20) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS6_14_TX_AVAILABLE) + void MFS6_14_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS14_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS6_TX_AVAILABLE) + void MFS6_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS7, MFS15 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15) +/** + ****************************************************************************** + ** \brief FM3: MFS7, MFS15 IRQ handler (IRQ#21) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS7_15_RX_AVAILABLE) + void MFS7_15_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS15_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS7_RX_AVAILABLE) + void MFS7_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: MFS7, MFS15 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15) +/** + ****************************************************************************** + ** \brief FM3: MFS7, MFS15 IRQ handler (IRQ#22) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS7_15_TX_AVAILABLE) + void MFS7_15_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS15_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15 ) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #elif (1u == IRQ_MFS7_TX_AVAILABLE) + void MFS7_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: PPG00_02_20 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG00_02_20) +/** + ****************************************************************************** + ** \brief FM3: PPG00_02_20 IRQ handler (IRQ#23) Type a + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_20_AVAILABLE) + void PPG00_02_20_IRQHandler(void) + { + Ppg_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM3: RTC, WC, CLK ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM3: RTC, WC, CLK IRQ handler (IRQ#24) Type a + ******************************************************************************/ + #if (1u == IRQ_TIM_WC_RTC_AVAILABLE) + void TIM_WC_RTC_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Wc_IrqHandler(&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: ADC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM3: ADC0 IRQ handler (IRQ#25) Type a + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: ADC1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) +/** + ****************************************************************************** + ** \brief FM3: ADC1 IRQ handler (IRQ#26) Type a + ******************************************************************************/ + #if (1u == IRQ_ADC1_AVAILABLE) + void ADC1_IRQHandler(void) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC1, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: ADC2, LCD *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) +/** + ****************************************************************************** + ** \brief FM3: ADC2, LCD IRQ handler (IRQ#27) Type a + ******************************************************************************/ + #if (1u == IRQ_ADC2_LCD_AVAILABLE) + void ADC2_LCD_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ27MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC2, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc2].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Lcd_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_FRT, MFT1_FRT, MFT2_FRT **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) +/** + ****************************************************************************** + ** \brief FM3: MFT0_FRT, MFT1_FRT, MFT2_FRT IRQ handler (IRQ#28) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_2_FRT_AVAILABLE) + void MFT0_2_FRT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ28MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) + if (0ul != (u32IrqMon & 0x00000FC0ul)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) + if (0ul != (u32IrqMon & 0x0003F000ul)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_ICU, MFT1_ICU, MFT2_ICU **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) +/** + ****************************************************************************** + ** \brief FM3: MFT0_ICU, MFT1_ICU, MFT2_ICU IRQ handler (IRQ#29) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_2_ICU_AVAILABLE) + void MFT0_2_ICU_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ29MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) + if (0ul != (u32IrqMon & 0x000000F0ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT1_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) + if (0ul != (u32IrqMon & 0x00000F00ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT2_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_OCU, MFT1_OCU, MFT2_OCU **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) +/** + ****************************************************************************** + ** \brief FM3: MFT0_OCU, MFT1_OCU, MFT2_OCU IRQ handler (IRQ#30) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_2_OCU_AVAILABLE) + void MFT0_2_OCU_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ30MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) + if (0ul != (u32IrqMon & 0x00000FC0ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT1_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) + if (0ul != (u32IrqMon & 0x0003F000ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT2_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************** FM3: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7 *****************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) +/** + ****************************************************************************** + ** \brief FM3: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7 IRQ handler (IRQ#31) Type a + ******************************************************************************/ + #if (1u == IRQ_BT0_7_AVAILABLE) + void BT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ31MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM3: ETHER0, CAN0 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CAN0) +/** + ****************************************************************************** + ** \brief FM3: ETHER0, CAN0 IRQ handler (IRQ#32) Type a + ******************************************************************************/ + #if (1u == IRQ_ETHER0_CAN0_AVAILABLE) + void ETHER0_CAN0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ32MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER0) + if (0ul != (u32IrqMon & 0x0000000Eul)) + { + EmacIrqHandler((FM_ETHERNET_MAC_TypeDef*)&EMAC0, &(m_astcEmacInstanceDataLut[EmacInstanceIndexEmac0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Can_IrqHandler(0u); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM3: ETHER1, CAN1 ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) +/** + ****************************************************************************** + ** \brief FM3: ETHER1, CAN1 IRQ handler (IRQ#33) Type a + ******************************************************************************/ + #if (1u == IRQ_ETHER1_CAN1_AVAILABLE) + void ETHER1_CAN1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ33MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER1) + if (0ul != (u32IrqMon & 0x0000000Eul)) + { + EmacIrqHandler((FM_ETHERNET_MAC_TypeDef*)&EMAC1, &(m_astcEmacInstanceDataLut[EmacInstanceIndexEmac1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Can_IrqHandler(1u); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM3: USB0_DEVICE IRQ handler (IRQ#34) Type a + ******************************************************************************/ + #if (1u == IRQ_USB0_F_AVAILABLE) + void USB0_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM3: USB0_HOST, USB0_DEVICE *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM3: USB0_HOST, USB0_DEVICE IRQ handler (IRQ#35) Type a + ******************************************************************************/ + #if (1u == IRQ_USB0_H_F_AVAILABLE) + void USB0_H_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM3: USB1_DEVICE, CEC0 ***************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) +/** + ****************************************************************************** + ** \brief FM3: USB1_DEVICE, CEC0 IRQ handler (IRQ#36) Type a + ******************************************************************************/ + #if (1u == IRQ_USB1_F_HDMICEC0_AVAILABLE) + void USB1_F_HDMICEC0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ36MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) + if (0ul != (u32IrqMon & 0x0000001Ful)) + { + Usb_IrqHandler((stc_usb_t*)&USB1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) + if (0ul != (u32IrqMon & 0x000000020ul)) + { + RcIrqHandler((stc_rcn_t*) &RC0, &(m_astcRcInstanceDataLut[RcInstanceIndexRc0].stcInternData)); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: USB1_HOST, USB1_DEVICE, CEC1 **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) +/** + ****************************************************************************** + ** \brief FM3: USB1_HOST, USB1_DEVICE, CEC1 IRQ handler (IRQ#37) Type a + ******************************************************************************/ + #if (1u == IRQ_USB1_H_F_HDMICEC1_AVAILABLE) + void USB1_H_F_HDMICEC1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ37MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_HOST) ||(PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Usb_IrqHandler((stc_usb_t*)&USB1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) + if (0ul != (u32IrqMon & 0x000000040ul)) + { + RcIrqHandler((stc_rcn_t*) &RC1, &(m_astcRcInstanceDataLut[RcInstanceIndexRc1].stcInternData)); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) +/** + ****************************************************************************** + ** \brief FM3: DMA0 IRQ handler (IRQ#38) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC0_AVAILABLE) + void DMAC0_IRQHandler(void) + { + DmaIrqHandler(0u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) +/** + ****************************************************************************** + ** \brief FM3: DMA1 IRQ handler (IRQ#39) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC1_AVAILABLE) + void DMAC1_IRQHandler(void) + { + DmaIrqHandler(1u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA2) +/** + ****************************************************************************** + ** \brief FM3: DMA2 IRQ handler (IRQ#40) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC2_AVAILABLE) + void DMAC2_IRQHandler(void) + { + DmaIrqHandler(2u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA3) +/** + ****************************************************************************** + ** \brief FM3: DMA3 IRQ handler (IRQ#41) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC3_AVAILABLE) + void DMAC3_IRQHandler(void) + { + DmaIrqHandler(3u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA4) +/** + ****************************************************************************** + ** \brief FM3: DMA4 IRQ handler (IRQ#42) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC4_AVAILABLE) + void DMAC4_IRQHandler(void) + { + DmaIrqHandler(4u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA5) +/** + ****************************************************************************** + ** \brief FM3: DMA5 IRQ handler (IRQ#43) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC5_AVAILABLE) + void DMAC5_IRQHandler(void) + { + DmaIrqHandler(5u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA6) +/** + ****************************************************************************** + ** \brief FM3: DMA6 IRQ handler (IRQ#44) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC6_AVAILABLE) + void DMAC6_IRQHandler(void) + { + DmaIrqHandler(6u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: DMA7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA7) +/** + ****************************************************************************** + ** \brief FM3: DMA7 IRQ handler (IRQ#45) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC7_AVAILABLE) + void DMAC7_IRQHandler(void) + { + DmaIrqHandler(7u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************* FM3: BT8, BT9, BT10, BT11, BT12, BT13, BT14, BT15 **************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT15) +/** + ****************************************************************************** + ** \brief FM3: BT8, BT9, BT10, BT11, BT12, BT13, BT14, BT15 IRQ handler (IRQ#46) Type a + ******************************************************************************/ + #if (1u == IRQ_BT8_15_AVAILABLE) + void BT8_15_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ46MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT8) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT8, &m_astcBtInstanceDataLut[BtInstanceIndexBt8].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT9) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT9, &m_astcBtInstanceDataLut[BtInstanceIndexBt9].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT10) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT10, &m_astcBtInstanceDataLut[BtInstanceIndexBt10].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT11) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT11, &m_astcBtInstanceDataLut[BtInstanceIndexBt11].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT12) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT12, &m_astcBtInstanceDataLut[BtInstanceIndexBt12].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT13) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT13, &m_astcBtInstanceDataLut[BtInstanceIndexBt13].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT14) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT14, &m_astcBtInstanceDataLut[BtInstanceIndexBt14].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT15) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT15, &m_astcBtInstanceDataLut[BtInstanceIndexBt15].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: FLASH *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM3: FLASH IRQ handler (IRQ#47) Type a + ******************************************************************************/ + #if (1u == IRQ_FLASHIF_AVAILABLE) + void FLASHIF_IRQHandler(void) + { + PDL_DummyHandler(0ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: NMI, HWWDG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM3: NMI, HWWDG IRQ handler (EXC#2) Type a + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM3_TYPE_A_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_b.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_b.c new file mode 100644 index 0000000000..c5b3b74f58 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_b.c @@ -0,0 +1,1822 @@ +/******************************************************************************* +* \file interrupts_fm3_type_b.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm3.h" + +#ifdef __INTERRUPTS_FM3_TYPE_B_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: RCINTSEL0, 1: RCINTSEL1, 2: RCINTSEL2, 3: RCINTSEL3, 4: RCINTSEL4, + // 5: RCINTSEL5, 6: RCINTSEL6, 7: RCINTSEL7, 8: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************** FM3: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM3: CSV IRQ handler (IRQ#0) Type b + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM3: SWWDG IRQ handler (IRQ#1) Type b + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM3: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM3: LVD IRQ handler (IRQ#2) Type b + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL0 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL0) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL0 IRQ handler (IRQ#3) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL0_AVAILABLE) + void RCINTSEL0_IRQHandler(void) + { + PDL_DummyHandler(0ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL1 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL1) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL1 IRQ handler (IRQ#4) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL1_AVAILABLE) + void RCINTSEL1_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL2 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL2) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL2 IRQ handler (IRQ#5) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL2_AVAILABLE) + void RCINTSEL2_IRQHandler(void) + { + PDL_DummyHandler(2ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL3 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL3) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL3 IRQ handler (IRQ#6) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL3_AVAILABLE) + void RCINTSEL3_IRQHandler(void) + { + PDL_DummyHandler(3ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL4 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL4) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL4 IRQ handler (IRQ#7) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL4_AVAILABLE) + void RCINTSEL4_IRQHandler(void) + { + PDL_DummyHandler(4ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL5 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL5) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL5 IRQ handler (IRQ#8) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL5_AVAILABLE) + void RCINTSEL5_IRQHandler(void) + { + PDL_DummyHandler(5ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL6 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL6) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL6 IRQ handler (IRQ#9) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL6_AVAILABLE) + void RCINTSEL6_IRQHandler(void) + { + PDL_DummyHandler(6ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RCINTSEL7 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RCINTSEL7) +/** + ****************************************************************************** + ** \brief FM3: RCINTSEL7 IRQ handler (IRQ#10) Type b + ******************************************************************************/ + #if (1u == IRQ_RCINTSEL7_AVAILABLE) + void RCINTSEL7_IRQHandler(void) + { + PDL_DummyHandler(7ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************** FM3: MFT0_WFG_DTIF, MFS8 **************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG_DTIF) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) +/** + ****************************************************************************** + ** \brief FM3: MFT0_WFG_DTIF, MFS8 IRQ handler (IRQ#11) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_MFS8_RX_TX_AVAILABLE) + void MFT0_WFG_DTIF_MFS8_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ11MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG_DTIF) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM3: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 *****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM3: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#12) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint2); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint3); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint4); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint5); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint6); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint7); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/* FM3: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23, EXINT24, EXINT25, EXINT26, EXINT27, EXINT28, EXINT30, EXINT31 */ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) +/** + ****************************************************************************** + ** \brief FM3: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15, EXINT16, EXINT17, EXINT18, EXINT19, EXINT20, EXINT21, EXINT22, EXINT23, EXINT24, EXINT25, EXINT26, EXINT27, EXINT28, EXINT30, EXINT31 IRQ handler (IRQ#13) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT8_31_AVAILABLE) + void EXINT8_31_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint8); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint9); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint10); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint11); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint12); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint13); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint14); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint15); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000100ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint16); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000200ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint17); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000400ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint18); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000800ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint19); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00001000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint20); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00002000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint21); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00004000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint22); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00008000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint23); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) + if (0ul != (u32IrqMon & 0x00010000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint24); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint25); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) + if (0ul != (u32IrqMon & 0x00040000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint26); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + if (0ul != (u32IrqMon & 0x00080000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint27); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00100000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint28); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00020000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint29); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) + if (0ul != (u32IrqMon & 0x00040000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint30); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + if (0ul != (u32IrqMon & 0x00080000ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint31); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: DT0, QPRC0 *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) +/** + ****************************************************************************** + ** \brief FM3: DT0, QPRC0 IRQ handler (IRQ#14) Type b + ******************************************************************************/ + #if (1u == IRQ_DT_QPRC_AVAILABLE) + void DT_QPRC_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(DtChannel0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) + if (0ul != (u32IrqMon & 0x000000FCul)) + { + Qprc_IrqHandler((volatile stc_qprcn_t*)&QPRC0, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM3: MFS0 IRQ handler (IRQ#15) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_TX_AVAILABLE) + void MFS0_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM3: MFS1 IRQ handler (IRQ#16) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_TX_AVAILABLE) + void MFS1_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM3: MFS2 IRQ handler (IRQ#17) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_TX_AVAILABLE) + void MFS2_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM3: MFS3 IRQ handler (IRQ#18) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_TX_AVAILABLE) + void MFS3_RX_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM3: MFS4 IRQ handler (IRQ#19) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM3: MFS4 IRQ handler (IRQ#20) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM3: MFS5 IRQ handler (IRQ#21) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM3: MFS5 IRQ handler (IRQ#22) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ22MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM3: PPG0_20 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG0_20) +/** + ****************************************************************************** + ** \brief FM3: PPG0_20 IRQ handler (IRQ#23) Type b + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_20_AVAILABLE) + void PPG00_02_20_IRQHandler(void) + { + Ppg_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM3: RTC, WC, CLK ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_WC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM3: RTC, WC, CLK IRQ handler (IRQ#24) Type b + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ24MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_WC) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Wc_IrqHandler(&WC0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: ADC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM3: ADC0 IRQ handler (IRQ#25) Type b + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: ADC1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) +/** + ****************************************************************************** + ** \brief FM3: ADC1 IRQ handler (IRQ#26) Type b + ******************************************************************************/ + #if (1u == IRQ_ADC1_AVAILABLE) + void ADC1_IRQHandler(void) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC1, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: ADC2, LCD *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) +/** + ****************************************************************************** + ** \brief FM3: ADC2, LCD IRQ handler (IRQ#27) Type b + ******************************************************************************/ + #if (1u == IRQ_ADC2_LCDC_AVAILABLE) + void ADC2_LCDC_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ27MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) + if (0ul != (u32IrqMon & 0x0000001Ful)) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC2, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc2].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Lcd_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_FRT, MFT1_FRT, MFT2_FRT **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) +/** + ****************************************************************************** + ** \brief FM3: MFT0_FRT, MFT1_FRT, MFT2_FRT IRQ handler (IRQ#28) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_1_2_FRT_AVAILABLE) + void MFT0_1_2_FRT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ28MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) + if (0ul != (u32IrqMon & 0x00000FC0ul)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) + if (0ul != (u32IrqMon & 0x0003F000ul)) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_ICU, MFT1_ICU, MFT2_ICU **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) +/** + ****************************************************************************** + ** \brief FM3: MFT0_ICU, MFT1_ICU, MFT2_ICU IRQ handler (IRQ#29) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_1_2_ICU_AVAILABLE) + void MFT0_1_2_ICU_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ29MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) + if (0ul != (u32IrqMon & 0x0000000Ful)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) + if (0ul != (u32IrqMon & 0x000000F0ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT1_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) + if (0ul != (u32IrqMon & 0x00000F00ul)) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT2_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM3: MFT0_OCU, MFT1_OCU, MFT2_OCU **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) +/** + ****************************************************************************** + ** \brief FM3: MFT0_OCU, MFT1_OCU, MFT2_OCU IRQ handler (IRQ#30) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_1_2_OCU_AVAILABLE) + void MFT0_1_2_OCU_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ30MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) + if (0ul != (u32IrqMon & 0x00000FC0ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT1_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) + if (0ul != (u32IrqMon & 0x0003F000ul)) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT2_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu2].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************* FM3: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH *************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM3: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7, FLASH IRQ handler (IRQ#31) Type b + ******************************************************************************/ + #if (1u == IRQ_BT0_7_FLASHIF_AVAILABLE) + void BT0_7_FLASHIF_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ31MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + if (0ul != (u32IrqMon & 0x08000000ul)) + { + PDL_DummyHandler(8ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: NMI, HWWDG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM3: NMI, HWWDG IRQ handler (EXC#2) Type b + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM3_TYPE_B_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_c.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_c.c new file mode 100644 index 0000000000..1e429554fa --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm3_type_c.c @@ -0,0 +1,1655 @@ +/******************************************************************************* +* \file interrupts_fm3_type_c.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm3.h" + +#ifdef __INTERRUPTS_FM3_TYPE_C_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************** FM3: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM3: CSV IRQ handler (IRQ#0) Type c + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM3: SWWDG IRQ handler (IRQ#1) Type c + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM3: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM3: LVD IRQ handler (IRQ#2) Type c + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: MFT0_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) +/** + ****************************************************************************** + ** \brief FM3: MFT0_WFG IRQ handler (IRQ#3) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_AVAILABLE) + void MFT0_WFG_IRQHandler(void) + { + Mft_Wfg_IrqHandler((volatile stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**** FM3: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 *****/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM3: EXINT0, EXINT1, EXINT2, EXINT3, EXINT4, EXINT5, EXINT6, EXINT7 IRQ handler (IRQ#4) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT0_7_AVAILABLE) + void EXINT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ04MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint2); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint3); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint4); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint5); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint6); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint7); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/* FM3: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15 **/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) +/** + ****************************************************************************** + ** \brief FM3: EXINT8, EXINT9, EXINT10, EXINT11, EXINT12, EXINT13, EXINT14, EXINT15 IRQ handler (IRQ#5) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT8_15_AVAILABLE) + void EXINT8_15_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ05MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint8); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint9); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint10); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint11); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint12); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint13); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint14); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) + if (0ul != (u32IrqMon & 0x00000080ul)) + { + Exint_IrqHandler(ExintInstanceIndexExint15); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM3: MFS0 IRQ handler (IRQ#6) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_AVAILABLE) + void MFS0_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ06MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM3: MFS0 IRQ handler (IRQ#7) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS0_TX_AVAILABLE) + void MFS0_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ07MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM3: MFS1 IRQ handler (IRQ#8) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_AVAILABLE) + void MFS1_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ08MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM3: MFS1 IRQ handler (IRQ#9) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS1_TX_AVAILABLE) + void MFS1_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ09MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM3: MFS2 IRQ handler (IRQ#10) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_AVAILABLE) + void MFS2_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ10MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM3: MFS2 IRQ handler (IRQ#11) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS2_TX_AVAILABLE) + void MFS2_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ11MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM3: MFS3 IRQ handler (IRQ#12) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_AVAILABLE) + void MFS3_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ12MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM3: MFS3 IRQ handler (IRQ#13) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS3_TX_AVAILABLE) + void MFS3_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ13MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM3: MFS4 IRQ handler (IRQ#14) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ14MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM3: MFS4 IRQ handler (IRQ#15) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ15MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM3: MFS5 IRQ handler (IRQ#16) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ16MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM3: MFS5 IRQ handler (IRQ#17) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ17MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM3: MFS6 IRQ handler (IRQ#18) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS6_RX_AVAILABLE) + void MFS6_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ18MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM3: MFS6 IRQ handler (IRQ#19) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS6_TX_AVAILABLE) + void MFS6_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ19MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM3: MFS7 IRQ handler (IRQ#20) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS7_RX_AVAILABLE) + void MFS7_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ20MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM3: MFS7 IRQ handler (IRQ#21) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS7_TX_AVAILABLE) + void MFS7_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ21MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM3: PPG0_20 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG0_20) +/** + ****************************************************************************** + ** \brief FM3: PPG0_20 IRQ handler (IRQ#22) Type c + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_20_AVAILABLE) + void PPG00_02_20_IRQHandler(void) + { + Ppg_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: RTC, CLK ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) +/** + ****************************************************************************** + ** \brief FM3: RTC, CLK IRQ handler (IRQ#23) Type c + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ23MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: ADC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM3: ADC0 IRQ handler (IRQ#24) Type c + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + AdcIrqHandler((volatile stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM3: MFT0_FRT IRQ handler (IRQ#25) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_AVAILABLE) + void MFT0_FRT_IRQHandler(void) + { + Mft_Frt_IrqHandler((volatile stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: MFT0_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) +/** + ****************************************************************************** + ** \brief FM3: MFT0_ICU IRQ handler (IRQ#26) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_ICU_AVAILABLE) + void MFT0_ICU_IRQHandler(void) + { + Mft_Icu_IrqHandler((volatile stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM3: MFT0_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM3: MFT0_OCU IRQ handler (IRQ#27) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_OCU_AVAILABLE) + void MFT0_OCU_IRQHandler(void) + { + Mft_Ocu_IrqHandler((volatile stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************** FM3: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7 *****************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) +/** + ****************************************************************************** + ** \brief FM3: BT0, BT1, BT2, BT3, BT4, BT5, BT6, BT7 IRQ handler (IRQ#28) Type c + ******************************************************************************/ + #if (1u == IRQ_BT0_7_AVAILABLE) + void BT0_7_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ28MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) + if (0ul != (u32IrqMon & 0x00000003ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) + if (0ul != (u32IrqMon & 0x0000000Cul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) + if (0ul != (u32IrqMon & 0x00000030ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) + if (0ul != (u32IrqMon & 0x000000C0ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) + if (0ul != (u32IrqMon & 0x00000300ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) + if (0ul != (u32IrqMon & 0x00000C00ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) + if (0ul != (u32IrqMon & 0x00003000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) + if (0ul != (u32IrqMon & 0x0000C000ul)) + { + Bt_IrqHandler((volatile stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM3: LCD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LCD) +/** + ****************************************************************************** + ** \brief FM3: LCD IRQ handler (IRQ#29) Type c + ******************************************************************************/ + #if (1u == IRQ_LCDC_AVAILABLE) + void LCDC_IRQHandler(void) + { + Lcd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: CEC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) +/** + ****************************************************************************** + ** \brief FM3: CEC0 IRQ handler (IRQ#30) Type c + ******************************************************************************/ + #if (1u == IRQ_HDMICEC0_AVAILABLE) + void HDMICEC0_IRQHandler(void) + { + RcIrqHandler((stc_rcn_t*) &RC0, &(m_astcRcInstanceDataLut[RcInstanceIndexRc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM3: CEC1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) +/** + ****************************************************************************** + ** \brief FM3: CEC1 IRQ handler (IRQ#31) Type c + ******************************************************************************/ + #if (1u == IRQ_HDMICEC1_AVAILABLE) + void HDMICEC1_IRQHandler(void) + { + RcIrqHandler((stc_rcn_t*) &RC1, &(m_astcRcInstanceDataLut[RcInstanceIndexRc1].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM3: NMI, HWWDG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM3: NMI, HWWDG IRQ handler (EXC#2) Type c + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM3_TYPE_C_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4.h new file mode 100644 index 0000000000..5abc885ed3 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4.h @@ -0,0 +1,454 @@ +/******************************************************************************* +* \file interrupts_fm4.h +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + #ifndef __INTERRUPTS_FM4_H__ +#define __INTERRUPTS_FM4_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "pdl_user.h" + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Check whether interrupt is enable when peripheral is inactive */ +/*****************************************************************************/ + +// Include adc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) + #if defined(PDL_PERIPHERAL_ADC_ACTIVE) + #include "adc/adc.h" + #else + #error Do not enable ADC interrupt when it is inactive. + #endif +#endif + +// Include bt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT15) + #if defined(PDL_PERIPHERAL_BT_ACTIVE) + #include "bt/bt.h" + #else + #error Do not enable BT interrupt when it is inactive. + #endif +#endif + +// Include can.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) + #if defined(PDL_PERIPHERAL_CAN_ACTIVE) + #include "can/can.h" + #else + #error Do not enable CAN interrupt when it is inactive. + #endif +#endif + +// Include canfd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) + #if defined(PDL_PERIPHERAL_CANFD_ACTIVE) + #include "can/canfd.h" + #else + #error Do not enable CANFD interrupt when it is inactive. + #endif +#endif + +// Include cec.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) + #if defined(PDL_PERIPHERAL_CEC_ACTIVE) + #include "cec.h" + #else + #error Do not enable CEC interrupt when it is inactive. + #endif +#endif + +// Include clk.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + #if defined(PDL_PERIPHERAL_CLK_ACTIVE) + #include "clk/clk.h" + #else + #error Do not enable CLK interrupt when it is inactive. + #endif +#endif + +// Include csv.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) + #if defined(PDL_PERIPHERAL_CSV_ACTIVE) + #include "csv/csv.h" + #else + #error Do not enable CSV interrupt when it is inactive. + #endif +#endif + +// Include dma.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_DMA7) + #if defined(PDL_PERIPHERAL_DMA_ACTIVE) + #include "dma/dma.h" + #else + #error Do not enable DMA interrupt when it is inactive. + #endif +#endif + +// Include dt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + #if defined(PDL_PERIPHERAL_DT_ACTIVE) + #include "dt/dt.h" + #else + #error Do not enable DT interrupt when it is inactive. + #endif +#endif + +// Include ether.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER0) + #if defined(PDL_PERIPHERAL_ETHER_ACTIVE) + #include "ether.h" + #else + #error Do not enable ETHER interrupt when it is inactive. + #endif +#endif + +// Include exint.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + #if defined(PDL_PERIPHERAL_EXINT_ACTIVE) + #include "exint/exint.h" + #else + #error Do not enable EXINT interrupt when it is inactive. + #endif +#endif + +// Include NMI code in exint.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + #if defined(PDL_PERIPHERAL_NMI_ACTIVE) + #include "exint/exint.h" + #else + #error Do not enable NMI interrupt when it is inactive. + #endif +#endif + +// Include extif.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXTIF) + #if defined(PDL_PERIPHERAL_EXTIF_ACTIVE) + #include "extif/extif.h" + #else + #error Do not enable EXTIF interrupt when it is inactive. + #endif +#endif + +// Include hsspi.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_HSSPI) + #if defined(PDL_PERIPHERAL_HSSPI_ACTIVE) + #include "hsspi/hsspi.h" + #else + #error Do not enable HSSPI interrupt when it is inactive. + #endif +#endif + +// Include i2s.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2S1) + #if defined(PDL_PERIPHERAL_I2S_ACTIVE) + #include "i2s/i2s.h" + #else + #error Do not enable I2S interrupt when it is inactive. + #endif +#endif + +// Include i2spll.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) + #if defined(PDL_PERIPHERAL_I2SPLL_ACTIVE) + #include "i2spll.h" + #else + #error Do not enable I2SPLL interrupt when it is inactive. + #endif +#endif + +// Include icc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC01) + #if defined(PDL_PERIPHERAL_ICC_ACTIVE) + #include "icc/icc.h" + #else + #error Do not enable ICC interrupt when it is inactive. + #endif +#endif + +// Include lvd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) + #if defined(PDL_PERIPHERAL_LVD_ACTIVE) + #include "lvd/lvd.h" + #else + #error Do not enable LVD interrupt when it is inactive. + #endif +#endif + +// Include main_flash.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) + #if defined(PDL_PERIPHERAL_MAIN_FLASH_ACTIVE) + #include "flash/mainflash.h" + #else + #error Do not enable MAIN_FLASH interrupt when it is inactive. + #endif +#endif + +// Include mfs.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15) + #if defined(PDL_PERIPHERAL_MFS_ACTIVE) + #include "mfs/mfs.h" + #else + #error Do not enable MFS interrupt when it is inactive. + #endif +#endif + +// Include mft_frt.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) + #if defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE) + #include "mft/mft_frt.h" + #else + #error Do not enable MFT_FRT interrupt when it is inactive. + #endif +#endif + +// Include mft_icu.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) + #if defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE) + #include "mft/mft_icu.h" + #else + #error Do not enable MFT_ICU interrupt when it is inactive. + #endif +#endif + +// Include mft_ocu.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) + #if defined(PDL_PERIPHERAL_MFT_OCU_ACTIVE) + #include "mft/mft_ocu.h" + #else + #error Do not enable MFT_OCU interrupt when it is inactive. + #endif +#endif + +// Include mft_wfg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) + #if defined(PDL_PERIPHERAL_MFT_WFG_ACTIVE) + #include "mft/mft_wfg.h" + #else + #error Do not enable MFT_WFG interrupt when it is inactive. + #endif +#endif + +// Include pcrc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PCRC) + #if defined(PDL_PERIPHERAL_PCRC_ACTIVE) + #include "pcrc/pcrc.h" + #else + #error Do not enable PCRC interrupt when it is inactive. + #endif +#endif + +// Include ppg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) + #if defined(PDL_PERIPHERAL_PPG_ACTIVE) + #include "ppg/ppg.h" + #else + #error Do not enable PPG interrupt when it is inactive. + #endif +#endif + +// Include qprc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC2) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC3) + #if defined(PDL_PERIPHERAL_QPRC_ACTIVE) + #include "qprc/qprc.h" + #else + #error Do not enable QPRC interrupt when it is inactive. + #endif +#endif + +// Include rtc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) + #if defined(PDL_PERIPHERAL_RTC_ACTIVE) + #include "rtc/rtc.h" + #else + #error Do not enable RTC interrupt when it is inactive. + #endif +#endif + +// Include sd.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SD0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_SD1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_GDC_SDRAM) + #if defined(PDL_PERIPHERAL_SD_ACTIVE) + #include "sdif/sdif.h" + #else + #error Do not enable SD interrupt when it is inactive. + #endif +#endif + +// Include upll.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) + #if defined(PDL_PERIPHERAL_UPLL_ACTIVE) + #include "upll.h" + #else + #error Do not enable UPLL interrupt when it is inactive. + #endif +#endif + +// Include usb.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_HOST) + #if defined(PDL_PERIPHERAL_USB_ACTIVE) + #include "usb/usb.h" + #else + #error Do not enable USB interrupt when it is inactive. + #endif +#endif + +// Include wc.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) + #if defined(PDL_PERIPHERAL_WC_ACTIVE) + #include "wc/wc.h" + #else + #error Do not enable WC interrupt when it is inactive. + #endif +#endif + +// Include wdg.h if active and interrupts are enabled. +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + #if defined(PDL_PERIPHERAL_WDG_ACTIVE) + #include "wdg/wdg.h" + #else + #error Do not enable WDG interrupt when it is inactive. + #endif +#endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) + #if defined(PDL_PERIPHERAL_DSTC_ACTIVE) + #include "dstc/dstc.h" + #else + #error Do not enable DSTC interrupt when it is inactive. + #endif + #endif +//@} // PdlInterrupts +#ifdef __cplusplus +} +#endif + +#endif // PDL_MCU_CORE == PDL_FM4_CORE) + +#endif // #ifndef __INTERRUPTS_FM4_H__ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_a.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_a.c new file mode 100644 index 0000000000..0d3fbc1213 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_a.c @@ -0,0 +1,4384 @@ +/******************************************************************************* +* \file interrupts_fm4_type_a.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm4.h" + +#ifdef __INTERRUPTS_FM4_TYPE_A_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: IRQ003SEL, 1: IRQ004SEL, 2: IRQ005SEL, 3: IRQ006SEL, 4: IRQ007SEL, + // 5: IRQ008SEL, 6: IRQ009SEL, 7: IRQ010SEL, 8: EXTIF, 9: UPLL, + // 10: I2SPLL, 11: CANFD0, 12: CANFD1, 13: CANFD0|CANFD1, + // 14: CANFD0|CANFD1, 15: DSTC, 16: SD0, 17: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************** FM4: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM4: CSV IRQ handler (IRQ#0) Type a + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM4: SWWDG IRQ handler (IRQ#1) Type a + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM4: LVD IRQ handler (IRQ#2) Type a + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ003SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ003SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ003SEL IRQ handler (IRQ#3) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ003SEL_AVAILABLE) + void IRQ003SEL_IRQHandler(void) + { + PDL_DummyHandler(0ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ004SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ004SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ004SEL IRQ handler (IRQ#4) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ004SEL_AVAILABLE) + void IRQ004SEL_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ005SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ005SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ005SEL IRQ handler (IRQ#5) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ005SEL_AVAILABLE) + void IRQ005SEL_IRQHandler(void) + { + PDL_DummyHandler(2ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ006SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ006SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ006SEL IRQ handler (IRQ#6) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ006SEL_AVAILABLE) + void IRQ006SEL_IRQHandler(void) + { + PDL_DummyHandler(3ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ007SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ007SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ007SEL IRQ handler (IRQ#7) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ007SEL_AVAILABLE) + void IRQ007SEL_IRQHandler(void) + { + PDL_DummyHandler(4ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ008SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ008SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ008SEL IRQ handler (IRQ#8) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ008SEL_AVAILABLE) + void IRQ008SEL_IRQHandler(void) + { + PDL_DummyHandler(5ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ009SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ009SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ009SEL IRQ handler (IRQ#9) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ009SEL_AVAILABLE) + void IRQ009SEL_IRQHandler(void) + { + PDL_DummyHandler(6ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ010SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ010SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ010SEL IRQ handler (IRQ#10) Type a + ******************************************************************************/ + #if (1u == IRQ_IRQ010SEL_AVAILABLE) + void IRQ010SEL_IRQHandler(void) + { + PDL_DummyHandler(7ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) +/** + ****************************************************************************** + ** \brief FM4: EXINT0 IRQ handler (IRQ#11) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT0_AVAILABLE) + void EXINT0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT0)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT0); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT0) + + Exint_IrqHandler(0u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) +/** + ****************************************************************************** + ** \brief FM4: EXINT1 IRQ handler (IRQ#12) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT1_AVAILABLE) + void EXINT1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT1)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT1) + + Exint_IrqHandler(1u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) +/** + ****************************************************************************** + ** \brief FM4: EXINT2 IRQ handler (IRQ#13) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT2_AVAILABLE) + void EXINT2_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT2)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT2); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT2) + + Exint_IrqHandler(2u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) +/** + ****************************************************************************** + ** \brief FM4: EXINT3 IRQ handler (IRQ#14) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT3_AVAILABLE) + void EXINT3_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT3)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT3) + + Exint_IrqHandler(3u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) +/** + ****************************************************************************** + ** \brief FM4: EXINT4 IRQ handler (IRQ#15) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT4_AVAILABLE) + void EXINT4_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT4)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT4) + + Exint_IrqHandler(4u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) +/** + ****************************************************************************** + ** \brief FM4: EXINT5 IRQ handler (IRQ#16) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT5_AVAILABLE) + void EXINT5_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT5)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT5) + + Exint_IrqHandler(5u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT6 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) +/** + ****************************************************************************** + ** \brief FM4: EXINT6 IRQ handler (IRQ#17) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT6_AVAILABLE) + void EXINT6_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT6)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT6); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT6) + + Exint_IrqHandler(6u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT7 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM4: EXINT7 IRQ handler (IRQ#18) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT7_AVAILABLE) + void EXINT7_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT7)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT7); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT7) + + Exint_IrqHandler(7u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) +/** + ****************************************************************************** + ** \brief FM4: QPRC0 IRQ handler (IRQ#19) Type a + ******************************************************************************/ + #if (1u == IRQ_QPRC0_AVAILABLE) + void QPRC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC0, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC1) +/** + ****************************************************************************** + ** \brief FM4: QPRC1 IRQ handler (IRQ#20) Type a + ******************************************************************************/ + #if (1u == IRQ_QPRC1_AVAILABLE) + void QPRC1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC1, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT0_WFG IRQ handler (IRQ#21) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_AVAILABLE) + void MFT0_WFG_DTIF_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT1_WFG IRQ handler (IRQ#22) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT1_WFG_DTIF_AVAILABLE) + void MFT1_WFG_DTIF_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT1_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT1_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT1_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT1_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT2_WFG IRQ handler (IRQ#23) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT2_WFG_DTIF_AVAILABLE) + void MFT2_WFG_DTIF_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT2_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT2_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT2_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT2_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT0_FRT IRQ handler (IRQ#24) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_PEAK_AVAILABLE) + void MFT0_FRT_PEAK_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT0_FRT IRQ handler (IRQ#25) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_ZERO_AVAILABLE) + void MFT0_FRT_ZERO_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT0_ICU IRQ handler (IRQ#26) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_ICU_AVAILABLE) + void MFT0_ICU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT0_OCU IRQ handler (IRQ#27) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT0_OCU_AVAILABLE) + void MFT0_OCU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT1_FRT IRQ handler (IRQ#28) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT1_FRT_PEAK_AVAILABLE) + void MFT1_FRT_PEAK_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT1_FRT IRQ handler (IRQ#29) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT1_FRT_ZERO_AVAILABLE) + void MFT1_FRT_ZERO_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT0_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT1_ICU IRQ handler (IRQ#30) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT1_ICU_AVAILABLE) + void MFT1_ICU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT1_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT1_OCU IRQ handler (IRQ#31) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT1_OCU_AVAILABLE) + void MFT1_OCU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT1_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT2_FRT IRQ handler (IRQ#32) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT2_FRT_PEAK_AVAILABLE) + void MFT2_FRT_PEAK_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT2_FRT IRQ handler (IRQ#33) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT2_FRT_ZERO_AVAILABLE) + void MFT2_FRT_ZERO_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT0_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT2_ICU IRQ handler (IRQ#34) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT2_ICU_AVAILABLE) + void MFT2_ICU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT2_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT2_OCU IRQ handler (IRQ#35) Type a + ******************************************************************************/ + #if (1u == IRQ_MFT2_OCU_AVAILABLE) + void MFT2_OCU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT2_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#36) Type a + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_04_AVAILABLE) + void PPG00_02_04_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG0)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG2)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG4)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG0) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG2) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG4) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#37) Type a + ******************************************************************************/ + #if (1u == IRQ_PPG08_10_12_AVAILABLE) + void PPG08_10_12_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_PPG8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG8)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG8); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG10)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG12)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG8) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG12) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#38) Type a + ******************************************************************************/ + #if (1u == IRQ_PPG16_18_20_AVAILABLE) + void PPG16_18_20_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_PPG16) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG16)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG16); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG18) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG18)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG18); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG20) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG20)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG20); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG16) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG18) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG20) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) +/** + ****************************************************************************** + ** \brief FM4: BT0 IRQ handler (IRQ#39) Type a + ******************************************************************************/ + #if (1u == IRQ_BT0_AVAILABLE) + void BT0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT0_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT0_IRQ0, DSTC_IRQ_NUMBER_BT0_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT0_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) +/** + ****************************************************************************** + ** \brief FM4: BT1 IRQ handler (IRQ#40) Type a + ******************************************************************************/ + #if (1u == IRQ_BT1_AVAILABLE) + void BT1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT1_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT1_IRQ0, DSTC_IRQ_NUMBER_BT1_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT1_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) +/** + ****************************************************************************** + ** \brief FM4: BT2 IRQ handler (IRQ#41) Type a + ******************************************************************************/ + #if (1u == IRQ_BT2_AVAILABLE) + void BT2_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT2_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT2_IRQ0, DSTC_IRQ_NUMBER_BT2_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT2_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) +/** + ****************************************************************************** + ** \brief FM4: BT3 IRQ handler (IRQ#42) Type a + ******************************************************************************/ + #if (1u == IRQ_BT3_AVAILABLE) + void BT3_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT3_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT3_IRQ0, DSTC_IRQ_NUMBER_BT3_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT3_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) +/** + ****************************************************************************** + ** \brief FM4: BT4 IRQ handler (IRQ#43) Type a + ******************************************************************************/ + #if (1u == IRQ_BT4_AVAILABLE) + void BT4_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT4_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT4_IRQ0, DSTC_IRQ_NUMBER_BT4_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT4_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) +/** + ****************************************************************************** + ** \brief FM4: BT5 IRQ handler (IRQ#44) Type a + ******************************************************************************/ + #if (1u == IRQ_BT5_AVAILABLE) + void BT5_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT5_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT5_IRQ0, DSTC_IRQ_NUMBER_BT5_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT5_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) +/** + ****************************************************************************** + ** \brief FM4: BT6 IRQ handler (IRQ#45) Type a + ******************************************************************************/ + #if (1u == IRQ_BT6_AVAILABLE) + void BT6_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT6_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT6_IRQ0, DSTC_IRQ_NUMBER_BT6_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT6_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) +/** + ****************************************************************************** + ** \brief FM4: BT7 IRQ handler (IRQ#46) Type a + ******************************************************************************/ + #if (1u == IRQ_BT7_AVAILABLE) + void BT7_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT7_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT7_IRQ0, DSTC_IRQ_NUMBER_BT7_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT7_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: DT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) +/** + ****************************************************************************** + ** \brief FM4: DT0 IRQ handler (IRQ#47) Type a + ******************************************************************************/ + #if (1u == IRQ_DT_AVAILABLE) + void DT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ047MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(DtChannel0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel1); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: WC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) +/** + ****************************************************************************** + ** \brief FM4: WC0 IRQ handler (IRQ#48) Type a + ******************************************************************************/ + #if (1u == IRQ_WC_AVAILABLE) + void WC_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_WC) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC)) + { + Dstc_WcIrqHandler(); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_WC) + + Wc_IrqHandler((stc_wcn_t*)&WC0); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: EXTIF *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXTIF) +/** + ****************************************************************************** + ** \brief FM4: EXTIF IRQ handler (IRQ#49) Type a + ******************************************************************************/ + #if (1u == IRQ_EXTBUS_ERR_AVAILABLE) + void EXTBUS_ERR_IRQHandler(void) + { + PDL_DummyHandler(8ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: RTC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) +/** + ****************************************************************************** + ** \brief FM4: RTC0 IRQ handler (IRQ#50) Type a + ******************************************************************************/ + #if (1u == IRQ_RTC_AVAILABLE) + void RTC_IRQHandler(void) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT8 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) +/** + ****************************************************************************** + ** \brief FM4: EXINT8 IRQ handler (IRQ#51) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT8_AVAILABLE) + void EXINT8_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT8)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT8); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT8) + + Exint_IrqHandler(8u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT9 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) +/** + ****************************************************************************** + ** \brief FM4: EXINT9 IRQ handler (IRQ#52) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT9_AVAILABLE) + void EXINT9_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT9)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT9); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT9) + + Exint_IrqHandler(9u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT10 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) +/** + ****************************************************************************** + ** \brief FM4: EXINT10 IRQ handler (IRQ#53) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT10_AVAILABLE) + void EXINT10_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT10)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT10); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT10) + + Exint_IrqHandler(10u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT11 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) +/** + ****************************************************************************** + ** \brief FM4: EXINT11 IRQ handler (IRQ#54) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT11_AVAILABLE) + void EXINT11_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT11)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT11); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT11) + + Exint_IrqHandler(11u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT12 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) +/** + ****************************************************************************** + ** \brief FM4: EXINT12 IRQ handler (IRQ#55) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT12_AVAILABLE) + void EXINT12_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT12)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT12) + + Exint_IrqHandler(12u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT13 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) +/** + ****************************************************************************** + ** \brief FM4: EXINT13 IRQ handler (IRQ#56) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT13_AVAILABLE) + void EXINT13_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT13)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT13); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT13) + + Exint_IrqHandler(13u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT14 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) +/** + ****************************************************************************** + ** \brief FM4: EXINT14 IRQ handler (IRQ#57) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT14_AVAILABLE) + void EXINT14_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT14)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT14); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT14) + + Exint_IrqHandler(14u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT15 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) +/** + ****************************************************************************** + ** \brief FM4: EXINT15 IRQ handler (IRQ#58) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT15_AVAILABLE) + void EXINT15_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT15)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT15); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT15) + + Exint_IrqHandler(15u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM4: CLK, UPLL, I2SPLL ***************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) +/** + ****************************************************************************** + ** \brief FM4: CLK, UPLL, I2SPLL IRQ handler (IRQ#59) Type a + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ059MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + PDL_DummyHandler(9ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + PDL_DummyHandler(10ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM4: MFS0 IRQ handler (IRQ#60) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_AVAILABLE) + void MFS0_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ060MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM4: MFS0 IRQ handler (IRQ#61) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS0_TX_AVAILABLE) + void MFS0_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ061MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS0_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM4: MFS1 IRQ handler (IRQ#62) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_AVAILABLE) + void MFS1_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ062MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM4: MFS1 IRQ handler (IRQ#63) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS1_TX_AVAILABLE) + void MFS1_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ063MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS1_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM4: MFS2 IRQ handler (IRQ#64) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_AVAILABLE) + void MFS2_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ064MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS2_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM4: MFS2 IRQ handler (IRQ#65) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS2_TX_AVAILABLE) + void MFS2_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ065MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS2_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM4: MFS3 IRQ handler (IRQ#66) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_AVAILABLE) + void MFS3_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ066MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM4: MFS3 IRQ handler (IRQ#67) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS3_TX_AVAILABLE) + void MFS3_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ067MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS3_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM4: MFS4 IRQ handler (IRQ#68) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ068MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM4: MFS4 IRQ handler (IRQ#69) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ069MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS4_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM4: MFS5 IRQ handler (IRQ#70) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ070MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS5_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM4: MFS5 IRQ handler (IRQ#71) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ071MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS5_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM4: MFS6 IRQ handler (IRQ#72) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS6_RX_AVAILABLE) + void MFS6_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ072MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS6_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM4: MFS6 IRQ handler (IRQ#73) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS6_TX_AVAILABLE) + void MFS6_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ073MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS6_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM4: MFS7 IRQ handler (IRQ#74) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS7_RX_AVAILABLE) + void MFS7_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ074MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS7_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM4: MFS7 IRQ handler (IRQ#75) Type a + ******************************************************************************/ + #if (1u == IRQ_MFS7_TX_AVAILABLE) + void MFS7_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ075MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS7_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM4: ADC0 IRQ handler (IRQ#76) Type a + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC0_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC0_PRIO, DSTC_IRQ_NUMBER_ADC0_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC0_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) +/** + ****************************************************************************** + ** \brief FM4: ADC1 IRQ handler (IRQ#77) Type a + ******************************************************************************/ + #if (1u == IRQ_ADC1_AVAILABLE) + void ADC1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC1_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC1_PRIO, DSTC_IRQ_NUMBER_ADC1_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC1_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC1, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM4: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM4: USB0_DEVICE IRQ handler (IRQ#78) Type a + ******************************************************************************/ + #if (1u == IRQ_USB0_F_AVAILABLE) + void USB0_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM4: USB0_HOST, USB0_DEVICE *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM4: USB0_HOST, USB0_DEVICE IRQ handler (IRQ#79) Type a + ******************************************************************************/ + #if (1u == IRQ_USB0_H_F_AVAILABLE) + void USB0_H_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: CAN0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN0) +/** + ****************************************************************************** + ** \brief FM4: CAN0 IRQ handler (IRQ#80) Type a + ******************************************************************************/ + #if (1u == IRQ_CAN0_AVAILABLE) + void CAN0_IRQHandler(void) + { + CanIrqHandler((stc_cann_t*) &CAN0, &(m_astcCanInstanceDataLut[CanInstanceIndexCan0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************* FM4: CAN1, CANFD0, CANFD1 **************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) +/** + ****************************************************************************** + ** \brief FM4: CAN1, CANFD0, CANFD1 IRQ handler (IRQ#81) Type a + ******************************************************************************/ + #if (1u == IRQ_CAN1_CANFD0_AVAILABLE) + void CAN1_CANFD0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ081MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + CanIrqHandler((stc_cann_t*) &CAN1, &(m_astcCanInstanceDataLut[CanInstanceIndexCan1].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + PDL_DummyHandler(11ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + PDL_DummyHandler(12ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) ||(PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + PDL_DummyHandler(13ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) ||(PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + PDL_DummyHandler(14ul); + } + #endif + + } + #elif (1u == IRQ_CAN1_AVAILABLE) + void CAN1_IRQHandler(void) + { + CanIrqHandler((stc_cann_t*) &CAN1, &(m_astcCanInstanceDataLut[CanInstanceIndexCan1].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) +/** + ****************************************************************************** + ** \brief FM4: DMA0 IRQ handler (IRQ#83) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC0_AVAILABLE) + void DMAC0_IRQHandler(void) + { + DmaIrqHandler(0u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) +/** + ****************************************************************************** + ** \brief FM4: DMA1 IRQ handler (IRQ#84) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC1_AVAILABLE) + void DMAC1_IRQHandler(void) + { + DmaIrqHandler(1u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA2) +/** + ****************************************************************************** + ** \brief FM4: DMA2 IRQ handler (IRQ#85) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC2_AVAILABLE) + void DMAC2_IRQHandler(void) + { + DmaIrqHandler(2u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA3) +/** + ****************************************************************************** + ** \brief FM4: DMA3 IRQ handler (IRQ#86) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC3_AVAILABLE) + void DMAC3_IRQHandler(void) + { + DmaIrqHandler(3u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA4) +/** + ****************************************************************************** + ** \brief FM4: DMA4 IRQ handler (IRQ#87) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC4_AVAILABLE) + void DMAC4_IRQHandler(void) + { + DmaIrqHandler(4u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA5) +/** + ****************************************************************************** + ** \brief FM4: DMA5 IRQ handler (IRQ#88) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC5_AVAILABLE) + void DMAC5_IRQHandler(void) + { + DmaIrqHandler(5u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA6) +/** + ****************************************************************************** + ** \brief FM4: DMA6 IRQ handler (IRQ#89) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC6_AVAILABLE) + void DMAC6_IRQHandler(void) + { + DmaIrqHandler(6u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA7) +/** + ****************************************************************************** + ** \brief FM4: DMA7 IRQ handler (IRQ#90) Type a + ******************************************************************************/ + #if (1u == IRQ_DMAC7_AVAILABLE) + void DMAC7_IRQHandler(void) + { + DmaIrqHandler(7u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DSTC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) +/** + ****************************************************************************** + ** \brief FM4: DSTC IRQ handler (IRQ#91) Type a + ******************************************************************************/ + #if (1u == IRQ_DSTC_AVAILABLE) + void DSTC_IRQHandler(void) + { + PDL_DummyHandler(15ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT16, EXINT17, EXINT18, EXINT19 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) +/** + ****************************************************************************** + ** \brief FM4: EXINT16, EXINT17, EXINT18, EXINT19 IRQ handler (IRQ#92) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT16_19_AVAILABLE) + void EXINT16_19_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ092MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT16) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT16)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT16); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT17) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT17)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT17); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT18) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT18)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT18); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT19) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT19)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT19); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT16) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT17) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT18) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT19) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(16u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(17u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(18u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(19u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT20, EXINT21, EXINT22, EXINT23 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) +/** + ****************************************************************************** + ** \brief FM4: EXINT20, EXINT21, EXINT22, EXINT23 IRQ handler (IRQ#93) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT20_23_AVAILABLE) + void EXINT20_23_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ093MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT20) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT20)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT20); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT21) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT21)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT21); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT22) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT22)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT22); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT23) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT23)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT23); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT20) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT21) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT22) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT23) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(20u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(21u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(22u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(24u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT24, EXINT25, EXINT26, EXINT27 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) +/** + ****************************************************************************** + ** \brief FM4: EXINT24, EXINT25, EXINT26, EXINT27 IRQ handler (IRQ#94) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT24_27_AVAILABLE) + void EXINT24_27_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ094MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT24) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT24)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT24); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT25) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT25)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT25); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT26) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT26)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT26); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT27) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT27)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT27); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT24) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT25) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT26) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT27) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(24u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(25u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(26u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(27u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT28, EXINT29, EXINT30, EXINT31 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) +/** + ****************************************************************************** + ** \brief FM4: EXINT28, EXINT29, EXINT30, EXINT31 IRQ handler (IRQ#95) Type a + ******************************************************************************/ + #if (1u == IRQ_EXINT28_31_AVAILABLE) + void EXINT28_31_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ095MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT28) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT28)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT28); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT29) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT29)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT29); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT30) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT30)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT30); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT31) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT31)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT31); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT28) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT29) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT30) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT31) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(28u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(29u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(30u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(31u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC2) +/** + ****************************************************************************** + ** \brief FM4: QPRC2 IRQ handler (IRQ#96) Type a + ******************************************************************************/ + #if (1u == IRQ_QPRC2_AVAILABLE) + void QPRC2_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC2, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) +/** + ****************************************************************************** + ** \brief FM4: ADC2 IRQ handler (IRQ#111) Type a + ******************************************************************************/ + #if (1u == IRQ_ADC2_AVAILABLE) + void ADC2_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC2_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC2_PRIO, DSTC_IRQ_NUMBER_ADC2_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC2_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC2, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc2].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM4: DSTC_HWINT_NEW *****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC_HWINT_NEW) +/** + ****************************************************************************** + ** \brief FM4: DSTC_HWINT_NEW IRQ handler (IRQ#112) Type a + ******************************************************************************/ + #if (1u == IRQ_DSTC_HWINT_AVAILABLE) + void DSTC_HWINT_IRQHandler(void) + { + Dstc_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: SD0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SD0) +/** + ****************************************************************************** + ** \brief FM4: SD0 IRQ handler (IRQ#118) Type a + ******************************************************************************/ + #if (1u == IRQ_SD_AVAILABLE) + void SD_IRQHandler(void) + { + PDL_DummyHandler(16ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: FLASH *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM4: FLASH IRQ handler (IRQ#119) Type a + ******************************************************************************/ + #if (1u == IRQ_FLASHIF_AVAILABLE) + void FLASHIF_IRQHandler(void) + { + PDL_DummyHandler(17ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM4: NMI, HWWDG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM4: NMI, HWWDG IRQ handler (EXC#2) Type a + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM4_TYPE_A_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_b.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_b.c new file mode 100644 index 0000000000..bb8cd83f00 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_b.c @@ -0,0 +1,6389 @@ +/******************************************************************************* +* \file interrupts_fm4_type_b.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +// [andreika]: added OSAL_XXX() macros for ChibiOS compatibility + +#include "hal.h" +#include "interrupts_fm4.h" + +#ifdef __INTERRUPTS_FM4_TYPE_B_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: IRQ003SEL, 1: IRQ004SEL, 2: IRQ005SEL, 3: IRQ006SEL, 4: IRQ007SEL, + // 5: IRQ008SEL, 6: IRQ009SEL, 7: IRQ010SEL, 8: EXTIF, 9: UPLL, + // 10: I2SPLL, 11: CANFD0, 12: CANFD1, 13: CANFD, 14: CANFD, 15: DSTC, + // 16: SD0, 17: SD1, 18: SD0, 19: FLASH, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************** FM4: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM4: CSV IRQ handler (IRQ#0) Type b + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + OSAL_IRQ_HANDLER(CSV_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + Csv_IrqHandler(); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM4: SWWDG IRQ handler (IRQ#1) Type b + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + OSAL_IRQ_HANDLER(SWDT_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + SwwdgIrqHandler(); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM4: LVD IRQ handler (IRQ#2) Type b + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + OSAL_IRQ_HANDLER(LVD_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + Lvd_IrqHandler(); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ003SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ003SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ003SEL IRQ handler (IRQ#3) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ003SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ003SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(0ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ004SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ004SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ004SEL IRQ handler (IRQ#4) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ004SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ004SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(1ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ005SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ005SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ005SEL IRQ handler (IRQ#5) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ005SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ005SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(2ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ006SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ006SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ006SEL IRQ handler (IRQ#6) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ006SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ006SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(3ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ007SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ007SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ007SEL IRQ handler (IRQ#7) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ007SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ007SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(4ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ008SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ008SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ008SEL IRQ handler (IRQ#8) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ008SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ008SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(5ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ009SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ009SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ009SEL IRQ handler (IRQ#9) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ009SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ009SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(6ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ010SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ010SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ010SEL IRQ handler (IRQ#10) Type b + ******************************************************************************/ + #if (1u == IRQ_IRQ010SEL_AVAILABLE) + OSAL_IRQ_HANDLER(IRQ010SEL_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(7ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) +/** + ****************************************************************************** + ** \brief FM4: EXINT0 IRQ handler (IRQ#11) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT0_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT0)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT0); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT0) + + Exint_IrqHandler(0u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) +/** + ****************************************************************************** + ** \brief FM4: EXINT1 IRQ handler (IRQ#12) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT1_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT1)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT1) + + Exint_IrqHandler(1u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) +/** + ****************************************************************************** + ** \brief FM4: EXINT2 IRQ handler (IRQ#13) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT2_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT2_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT2)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT2); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT2) + + Exint_IrqHandler(2u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) +/** + ****************************************************************************** + ** \brief FM4: EXINT3 IRQ handler (IRQ#14) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT3_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT3_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT3)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT3) + + Exint_IrqHandler(3u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) +/** + ****************************************************************************** + ** \brief FM4: EXINT4 IRQ handler (IRQ#15) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT4_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT4_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT4)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT4) + + Exint_IrqHandler(4u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) +/** + ****************************************************************************** + ** \brief FM4: EXINT5 IRQ handler (IRQ#16) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT5_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT5_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT5)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT5) + + Exint_IrqHandler(5u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT6 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) +/** + ****************************************************************************** + ** \brief FM4: EXINT6 IRQ handler (IRQ#17) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT6_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT6_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT6)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT6); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT6) + + Exint_IrqHandler(6u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT7 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM4: EXINT7 IRQ handler (IRQ#18) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT7_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT7_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT7)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT7); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT7) + + Exint_IrqHandler(7u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) +/** + ****************************************************************************** + ** \brief FM4: QPRC0 IRQ handler (IRQ#19) Type b + ******************************************************************************/ + #if (1u == IRQ_QPRC0_AVAILABLE) + OSAL_IRQ_HANDLER(QPRC0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC0, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC1) +/** + ****************************************************************************** + ** \brief FM4: QPRC1 IRQ handler (IRQ#20) Type b + ******************************************************************************/ + #if (1u == IRQ_QPRC1_AVAILABLE) + OSAL_IRQ_HANDLER(QPRC1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC1, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT0_WFG IRQ handler (IRQ#21) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_AVAILABLE) + OSAL_IRQ_HANDLER(MFT0_WFG_DTIF_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT0_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT1_WFG IRQ handler (IRQ#22) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT1_WFG_DTIF_AVAILABLE) + OSAL_IRQ_HANDLER(MFT1_WFG_DTIF_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT1_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT1_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT1_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT1_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT2_WFG IRQ handler (IRQ#23) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT2_WFG_DTIF_AVAILABLE) + OSAL_IRQ_HANDLER(MFT2_WFG_DTIF_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT2_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT2_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT2_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT2_WFG, &m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT0_FRT IRQ handler (IRQ#24) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_PEAK_AVAILABLE) + OSAL_IRQ_HANDLER(MFT0_FRT_PEAK_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT0_FRT IRQ handler (IRQ#25) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_ZERO_AVAILABLE) + OSAL_IRQ_HANDLER(MFT0_FRT_ZERO_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT0_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT0_ICU IRQ handler (IRQ#26) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_ICU_AVAILABLE) + OSAL_IRQ_HANDLER(MFT0_ICU_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT0_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT0_OCU IRQ handler (IRQ#27) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT0_OCU_AVAILABLE) + OSAL_IRQ_HANDLER(MFT0_OCU_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT0_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT1_FRT IRQ handler (IRQ#28) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT1_FRT_PEAK_AVAILABLE) + OSAL_IRQ_HANDLER(MFT1_FRT_PEAK_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT1_FRT IRQ handler (IRQ#29) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT1_FRT_ZERO_AVAILABLE) + OSAL_IRQ_HANDLER(MFT1_FRT_ZERO_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT0_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT1_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT1_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT1_ICU IRQ handler (IRQ#30) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT1_ICU_AVAILABLE) + OSAL_IRQ_HANDLER(MFT1_ICU_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT1_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT1_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT1_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT1_OCU IRQ handler (IRQ#31) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT1_OCU_AVAILABLE) + OSAL_IRQ_HANDLER(MFT1_OCU_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT1_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT1_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT1_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT1_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT1_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT2_FRT IRQ handler (IRQ#32) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT2_FRT_PEAK_AVAILABLE) + OSAL_IRQ_HANDLER(MFT2_FRT_PEAK_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT2_FRT IRQ handler (IRQ#33) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT2_FRT_ZERO_AVAILABLE) + OSAL_IRQ_HANDLER(MFT2_FRT_ZERO_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT2_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT2_FRT, &m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT2_ICU IRQ handler (IRQ#34) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT2_ICU_AVAILABLE) + OSAL_IRQ_HANDLER(MFT2_ICU_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT2_ICU, &m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT2_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT2_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT2_OCU IRQ handler (IRQ#35) Type b + ******************************************************************************/ + #if (1u == IRQ_MFT2_OCU_AVAILABLE) + OSAL_IRQ_HANDLER(MFT2_OCU_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT2_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT2_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT2_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT2_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT2_OCU, &m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#36) Type b + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_04_AVAILABLE) + OSAL_IRQ_HANDLER(PPG00_02_04_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG0)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG2)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG4)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG0) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG2) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG4) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#37) Type b + ******************************************************************************/ + #if (1u == IRQ_PPG08_10_12_AVAILABLE) + OSAL_IRQ_HANDLER(PPG08_10_12_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_PPG8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG8)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG8); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG10)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG12)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG8) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG12) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#38) Type b + ******************************************************************************/ + #if (1u == IRQ_PPG16_18_20_AVAILABLE) + OSAL_IRQ_HANDLER(PPG16_18_20_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_PPG16) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG16)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG16); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG18) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG18)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG18); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG20) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG20)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG20); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG16) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG18) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG20) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) +/** + ****************************************************************************** + ** \brief FM4: BT0 IRQ handler (IRQ#39) Type b + ******************************************************************************/ + #if (1u == IRQ_BT0_AVAILABLE) + OSAL_IRQ_HANDLER(BT0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT0_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT0_IRQ0, DSTC_IRQ_NUMBER_BT0_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT0_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT0, &m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) +/** + ****************************************************************************** + ** \brief FM4: BT1 IRQ handler (IRQ#40) Type b + ******************************************************************************/ + #if (1u == IRQ_BT1_AVAILABLE) + OSAL_IRQ_HANDLER(BT1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT1_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT1_IRQ0, DSTC_IRQ_NUMBER_BT1_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT1_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT1, &m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) +/** + ****************************************************************************** + ** \brief FM4: BT2 IRQ handler (IRQ#41) Type b + ******************************************************************************/ + #if (1u == IRQ_BT2_AVAILABLE) + OSAL_IRQ_HANDLER(BT2_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT2_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT2_IRQ0, DSTC_IRQ_NUMBER_BT2_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT2_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT2, &m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) +/** + ****************************************************************************** + ** \brief FM4: BT3 IRQ handler (IRQ#42) Type b + ******************************************************************************/ + #if (1u == IRQ_BT3_AVAILABLE) + OSAL_IRQ_HANDLER(BT3_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT3_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT3_IRQ0, DSTC_IRQ_NUMBER_BT3_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT3_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT3, &m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) +/** + ****************************************************************************** + ** \brief FM4: BT4 IRQ handler (IRQ#43) Type b + ******************************************************************************/ + #if (1u == IRQ_BT4_AVAILABLE) + OSAL_IRQ_HANDLER(BT4_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT4_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT4_IRQ0, DSTC_IRQ_NUMBER_BT4_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT4_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT4, &m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) +/** + ****************************************************************************** + ** \brief FM4: BT5 IRQ handler (IRQ#44) Type b + ******************************************************************************/ + #if (1u == IRQ_BT5_AVAILABLE) + OSAL_IRQ_HANDLER(BT5_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT5_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT5_IRQ0, DSTC_IRQ_NUMBER_BT5_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT5_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT5, &m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) +/** + ****************************************************************************** + ** \brief FM4: BT6 IRQ handler (IRQ#45) Type b + ******************************************************************************/ + #if (1u == IRQ_BT6_AVAILABLE) + OSAL_IRQ_HANDLER(BT6_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT6_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT6_IRQ0, DSTC_IRQ_NUMBER_BT6_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT6_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT6, &m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) +/** + ****************************************************************************** + ** \brief FM4: BT7 IRQ handler (IRQ#46) Type b + ******************************************************************************/ + #if (1u == IRQ_BT7_AVAILABLE) + OSAL_IRQ_HANDLER(BT7_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT7_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT7_IRQ0, DSTC_IRQ_NUMBER_BT7_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT7_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT7, &m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: DT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) +/** + ****************************************************************************** + ** \brief FM4: DT0 IRQ handler (IRQ#47) Type b + ******************************************************************************/ + #if (1u == IRQ_DT_AVAILABLE) + OSAL_IRQ_HANDLER(DT_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ047MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(DtChannel0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel1); + } + #endif + + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: WC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) +/** + ****************************************************************************** + ** \brief FM4: WC0 IRQ handler (IRQ#48) Type b + ******************************************************************************/ + #if (1u == IRQ_WC_AVAILABLE) + OSAL_IRQ_HANDLER(WC_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_WC) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC)) + { + Dstc_WcIrqHandler(); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_WC) + + Wc_IrqHandler((stc_wcn_t*)&WC0); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: EXTIF *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXTIF) +/** + ****************************************************************************** + ** \brief FM4: EXTIF IRQ handler (IRQ#49) Type b + ******************************************************************************/ + #if (1u == IRQ_EXTBUS_ERR_AVAILABLE) + OSAL_IRQ_HANDLER(EXTBUS_ERR_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(8ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: RTC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) +/** + ****************************************************************************** + ** \brief FM4: RTC0 IRQ handler (IRQ#50) Type b + ******************************************************************************/ + #if (1u == IRQ_RTC_AVAILABLE) + OSAL_IRQ_HANDLER(RTC_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + Rtc_IrqHandler((stc_rtcn_t*)&RTC0, &(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT8 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) +/** + ****************************************************************************** + ** \brief FM4: EXINT8 IRQ handler (IRQ#51) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT8_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT8_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT8)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT8); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT8) + + Exint_IrqHandler(8u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT9 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) +/** + ****************************************************************************** + ** \brief FM4: EXINT9 IRQ handler (IRQ#52) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT9_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT9_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT9)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT9); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT9) + + Exint_IrqHandler(9u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT10 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) +/** + ****************************************************************************** + ** \brief FM4: EXINT10 IRQ handler (IRQ#53) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT10_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT10_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT10)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT10); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT10) + + Exint_IrqHandler(10u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT11 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) +/** + ****************************************************************************** + ** \brief FM4: EXINT11 IRQ handler (IRQ#54) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT11_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT11_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT11)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT11); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT11) + + Exint_IrqHandler(11u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT12 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) +/** + ****************************************************************************** + ** \brief FM4: EXINT12 IRQ handler (IRQ#55) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT12_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT12_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT12)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT12) + + Exint_IrqHandler(12u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT13 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) +/** + ****************************************************************************** + ** \brief FM4: EXINT13 IRQ handler (IRQ#56) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT13_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT13_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT13)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT13); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT13) + + Exint_IrqHandler(13u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT14 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) +/** + ****************************************************************************** + ** \brief FM4: EXINT14 IRQ handler (IRQ#57) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT14_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT14_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT14)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT14); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT14) + + Exint_IrqHandler(14u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT15 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) +/** + ****************************************************************************** + ** \brief FM4: EXINT15 IRQ handler (IRQ#58) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT15_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT15_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT15)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT15); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT15) + + Exint_IrqHandler(15u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM4: CLK, UPLL, I2SPLL ***************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) +/** + ****************************************************************************** + ** \brief FM4: CLK, UPLL, I2SPLL IRQ handler (IRQ#59) Type b + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + OSAL_IRQ_HANDLER(TIM_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ059MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + PDL_DummyHandler(9ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + PDL_DummyHandler(10ul); + } + #endif + + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM4: MFS0 IRQ handler (IRQ#60) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS0_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ060MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM4: MFS0 IRQ handler (IRQ#61) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS0_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS0_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ061MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS0_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM4: MFS1 IRQ handler (IRQ#62) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS1_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ062MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM4: MFS1 IRQ handler (IRQ#63) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS1_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS1_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ063MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS1_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM4: MFS2 IRQ handler (IRQ#64) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS2_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ064MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS2_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM4: MFS2 IRQ handler (IRQ#65) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS2_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS2_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ065MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS2_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM4: MFS3 IRQ handler (IRQ#66) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS3_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ066MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM4: MFS3 IRQ handler (IRQ#67) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS3_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS3_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ067MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS3_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM4: MFS4 IRQ handler (IRQ#68) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS4_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ068MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM4: MFS4 IRQ handler (IRQ#69) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS4_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ069MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS4_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM4: MFS5 IRQ handler (IRQ#70) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS5_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ070MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS5_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM4: MFS5 IRQ handler (IRQ#71) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS5_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ071MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS5_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM4: MFS6 IRQ handler (IRQ#72) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS6_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS6_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ072MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS6_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM4: MFS6 IRQ handler (IRQ#73) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS6_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS6_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ073MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS6_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM4: MFS7 IRQ handler (IRQ#74) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS7_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS7_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ074MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS7_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM4: MFS7 IRQ handler (IRQ#75) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS7_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS7_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ075MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS7_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM4: ADC0 IRQ handler (IRQ#76) Type b + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + OSAL_IRQ_HANDLER(ADC0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC0_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC0_PRIO, DSTC_IRQ_NUMBER_ADC0_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC0_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC0, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) +/** + ****************************************************************************** + ** \brief FM4: ADC1 IRQ handler (IRQ#77) Type b + ******************************************************************************/ + #if (1u == IRQ_ADC1_AVAILABLE) + OSAL_IRQ_HANDLER(ADC1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC1_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC1_PRIO, DSTC_IRQ_NUMBER_ADC1_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC1_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC1, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM4: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM4: USB0_DEVICE IRQ handler (IRQ#78) Type b + ******************************************************************************/ + #if (1u == IRQ_USB0_F_AVAILABLE) + OSAL_IRQ_HANDLER(USB0_F_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + // [andreika]: fix for newer MCUHEADER + Usb_IrqHandlerF((stc_usbn_t*)&USB0); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM4: USB0_HOST, USB0_DEVICE *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM4: USB0_HOST, USB0_DEVICE IRQ handler (IRQ#79) Type b + ******************************************************************************/ + #if (1u == IRQ_USB0_H_F_AVAILABLE) + OSAL_IRQ_HANDLER(USB0_H_F_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + // [andreika]: fix for newer MCUHEADER + Usb_IrqHandlerH((stc_usbn_t*)&USB0); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: CAN0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN0) +/** + ****************************************************************************** + ** \brief FM4: CAN0 IRQ handler (IRQ#80) Type b + ******************************************************************************/ + #if (1u == IRQ_CAN0_AVAILABLE) + OSAL_IRQ_HANDLER(CAN0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + CanIrqHandler((stc_cann_t*) &CAN0, &(m_astcCanInstanceDataLut[CanInstanceIndexCan0].stcInternData)); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************** FM4: CAN1, CANFD0, CANFD1, CANFD **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD) + +/** + ****************************************************************************** + ** \brief FM4: CAN1, CANFD0, CANFD1, CANFD IRQ handler (IRQ#81) Type b + ******************************************************************************/ + #if (1u == IRQ_CAN1_CANFD0_AVAILABLE) + OSAL_IRQ_HANDLER(CAN1_CANFD0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ081MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CAN1) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + CanIrqHandler((stc_cann_t*) &CAN1, &(m_astcCanInstanceDataLut[CanInstanceIndexCan1].stcInternData)); + } + #endif +// [andreika]: disable error interrupts for now; are they buggy? +#if 0 + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) + // CAN-FD double bit error interrupt + if (0ul != (u32IrqMon & 0x00000002ul)) + { + // [andreika]: fix for newer MCUHEADER + CanfdIrqHandler((stc_canfdn_t*)&CANFD0); + //PDL_DummyHandler(11ul); + } + // CAN-FD single bit error interrupt + if (0ul != (u32IrqMon & 0x00000004ul)) + { + // [andreika]: fix for newer MCUHEADER + CanfdIrqHandler((stc_canfdn_t*)&CANFD0); + //PDL_DummyHandler(12ul); + } + #endif +#endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + // [andreika]: fix for newer MCUHEADER + CanfdIrqHandler((stc_canfdn_t*)&CANFD0); + //PDL_DummyHandler(13ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD1) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + // [andreika]: fix for newer MCUHEADER + CanfdIrqHandler((stc_canfdn_t*)&CANFD1); + //PDL_DummyHandler(14ul); + } + #endif + OSAL_IRQ_EPILOGUE(); + } + #elif (1u == IRQ_CAN1_AVAILABLE) + OSAL_IRQ_HANDLER(CAN1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + CanIrqHandler((stc_cann_t*) &CAN1, &(m_astcCanInstanceDataLut[CanInstanceIndexCan1].stcInternData)); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: ETHER0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ETHER0) +/** + ****************************************************************************** + ** \brief FM4: ETHER0 IRQ handler (IRQ#82) Type b + ******************************************************************************/ + #if (1u == IRQ_ETHER0_AVAILABLE) + OSAL_IRQ_HANDLER(ETHER0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + EmacIrqHandler((FM_ETHERNET_MAC_TypeDef*)&EMAC0, &(m_astcEmacInstanceDataLut[EmacInstanceIndexEmac0].stcInternData)); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) +/** + ****************************************************************************** + ** \brief FM4: DMA0 IRQ handler (IRQ#83) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC0_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(0u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) +/** + ****************************************************************************** + ** \brief FM4: DMA1 IRQ handler (IRQ#84) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC1_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(1u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA2) +/** + ****************************************************************************** + ** \brief FM4: DMA2 IRQ handler (IRQ#85) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC2_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC2_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(2u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA3) +/** + ****************************************************************************** + ** \brief FM4: DMA3 IRQ handler (IRQ#86) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC3_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC3_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(3u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA4) +/** + ****************************************************************************** + ** \brief FM4: DMA4 IRQ handler (IRQ#87) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC4_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC4_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(4u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA5) +/** + ****************************************************************************** + ** \brief FM4: DMA5 IRQ handler (IRQ#88) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC5_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC5_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(5u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA6) +/** + ****************************************************************************** + ** \brief FM4: DMA6 IRQ handler (IRQ#89) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC6_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC6_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(6u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA7) +/** + ****************************************************************************** + ** \brief FM4: DMA7 IRQ handler (IRQ#90) Type b + ******************************************************************************/ + #if (1u == IRQ_DMAC7_AVAILABLE) + OSAL_IRQ_HANDLER(DMAC7_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + DmaIrqHandler(7u); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DSTC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) +/** + ****************************************************************************** + ** \brief FM4: DSTC IRQ handler (IRQ#91) Type b + ******************************************************************************/ + #if (1u == IRQ_DSTC_AVAILABLE) + OSAL_IRQ_HANDLER(DSTC_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(15ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT16, EXINT17, EXINT18, EXINT19 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) +/** + ****************************************************************************** + ** \brief FM4: EXINT16, EXINT17, EXINT18, EXINT19 IRQ handler (IRQ#92) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT16_19_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT16_19_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ092MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT16) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT16)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT16); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT17) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT17)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT17); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT18) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT18)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT18); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT19) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT19)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT19); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT16) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT17) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT18) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT19) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT16) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(16u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT17) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(17u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT18) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(18u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT19) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(19u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT20, EXINT21, EXINT22, EXINT23 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) +/** + ****************************************************************************** + ** \brief FM4: EXINT20, EXINT21, EXINT22, EXINT23 IRQ handler (IRQ#93) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT20_23_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT20_23_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ093MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT20) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT20)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT20); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT21) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT21)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT21); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT22) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT22)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT22); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT23) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT23)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT23); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT20) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT21) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT22) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT23) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT20) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(20u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT21) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(21u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT22) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(22u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT23) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(24u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT24, EXINT25, EXINT26, EXINT27 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) +/** + ****************************************************************************** + ** \brief FM4: EXINT24, EXINT25, EXINT26, EXINT27 IRQ handler (IRQ#94) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT24_27_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT24_27_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ094MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT24) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT24)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT24); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT25) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT25)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT25); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT26) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT26)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT26); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT27) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT27)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT27); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT24) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT25) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT26) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT27) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT24) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(24u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT25) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(25u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT26) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(26u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT27) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(27u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************** FM4: EXINT28, EXINT29, EXINT30, EXINT31 *******************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) +/** + ****************************************************************************** + ** \brief FM4: EXINT28, EXINT29, EXINT30, EXINT31 IRQ handler (IRQ#95) Type b + ******************************************************************************/ + #if (1u == IRQ_EXINT28_31_AVAILABLE) + OSAL_IRQ_HANDLER(EXINT28_31_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ095MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT28) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT28)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT28); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT29) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT29)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT29); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT30) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT30)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT30); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT31) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT31)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT31); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT28) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT29) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT30) && \ + (PDL_ON != PDL_DSTC_ENABLE_EXINT31) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT28) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_IrqHandler(28u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT29) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Exint_IrqHandler(29u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT30) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Exint_IrqHandler(30u); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT31) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Exint_IrqHandler(31u); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC2) +/** + ****************************************************************************** + ** \brief FM4: QPRC2 IRQ handler (IRQ#96) Type b + ******************************************************************************/ + #if (1u == IRQ_QPRC2_AVAILABLE) + OSAL_IRQ_HANDLER(QPRC2_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC2, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC3) +/** + ****************************************************************************** + ** \brief FM4: QPRC3 IRQ handler (IRQ#97) Type b + ******************************************************************************/ + #if (1u == IRQ_QPRC3_AVAILABLE) + OSAL_IRQ_HANDLER(QPRC3_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC3, &m_astcQprcInstanceDataLut[QprcInstanceIndexQprc3].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT8 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT8) +/** + ****************************************************************************** + ** \brief FM4: BT8 IRQ handler (IRQ#98) Type b + ******************************************************************************/ + #if (1u == IRQ_BT8_AVAILABLE) + OSAL_IRQ_HANDLER(BT8_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT8_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT8_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT8_IRQ0, DSTC_IRQ_NUMBER_BT8_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT8_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT8, &m_astcBtInstanceDataLut[BtInstanceIndexBt8].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT9 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT9) +/** + ****************************************************************************** + ** \brief FM4: BT9 IRQ handler (IRQ#99) Type b + ******************************************************************************/ + #if (1u == IRQ_BT9_AVAILABLE) + OSAL_IRQ_HANDLER(BT9_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT9_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT9_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT9_IRQ0, DSTC_IRQ_NUMBER_BT9_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT9_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT9, &m_astcBtInstanceDataLut[BtInstanceIndexBt9].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: BT10 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT10) +/** + ****************************************************************************** + ** \brief FM4: BT10 IRQ handler (IRQ#100) Type b + ******************************************************************************/ + #if (1u == IRQ_BT10_AVAILABLE) + OSAL_IRQ_HANDLER(BT10_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT10_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT10_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT10_IRQ0, DSTC_IRQ_NUMBER_BT10_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT10_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT10, &m_astcBtInstanceDataLut[BtInstanceIndexBt10].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: BT11 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT11) +/** + ****************************************************************************** + ** \brief FM4: BT11 IRQ handler (IRQ#101) Type b + ******************************************************************************/ + #if (1u == IRQ_BT11_AVAILABLE) + OSAL_IRQ_HANDLER(BT11_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_BT11_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT11_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT11_IRQ0, DSTC_IRQ_NUMBER_BT11_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT11_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT11, &m_astcBtInstanceDataLut[BtInstanceIndexBt11].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM4: BT12, BT13, BT14, BT15 *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT12) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT13) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT14) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_BT15) +/** + ****************************************************************************** + ** \brief FM4: BT12, BT13, BT14, BT15 IRQ handler (IRQ#102) Type b + ******************************************************************************/ + #if (1u == IRQ_BT12_15_AVAILABLE) + OSAL_IRQ_HANDLER(BT12_15_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ102MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_BT12_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT12_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT12_IRQ0, DSTC_IRQ_NUMBER_BT12_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT13_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT13_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT13_IRQ0, DSTC_IRQ_NUMBER_BT13_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT14_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT14_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT14_IRQ0, DSTC_IRQ_NUMBER_BT14_IRQ1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_BT15_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT15_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT15_IRQ0, DSTC_IRQ_NUMBER_BT15_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT12_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT13_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT14_IRQ0) && \ + (PDL_ON != PDL_DSTC_ENABLE_BT15_IRQ0) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT12) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Bt_IrqHandler((stc_btn_t*)&BT12, &m_astcBtInstanceDataLut[BtInstanceIndexBt12].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT13) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + Bt_IrqHandler((stc_btn_t*)&BT13, &m_astcBtInstanceDataLut[BtInstanceIndexBt13].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT14) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + Bt_IrqHandler((stc_btn_t*)&BT14, &m_astcBtInstanceDataLut[BtInstanceIndexBt14].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_BT15) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Bt_IrqHandler((stc_btn_t*)&BT15, &m_astcBtInstanceDataLut[BtInstanceIndexBt15].stcInternData); + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS8 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) +/** + ****************************************************************************** + ** \brief FM4: MFS8 IRQ handler (IRQ#103) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS8_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS8_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ103MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS8_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS8_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS8_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS8_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS8 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8) +/** + ****************************************************************************** + ** \brief FM4: MFS8 IRQ handler (IRQ#104) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS8_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS8_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ104MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS8_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS8_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS8_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS8_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS8 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN8, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs8].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS9 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) +/** + ****************************************************************************** + ** \brief FM4: MFS9 IRQ handler (IRQ#105) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS9_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS9_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ105MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS9_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS9_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS9_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS9_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS9 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9) +/** + ****************************************************************************** + ** \brief FM4: MFS9 IRQ handler (IRQ#106) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS9_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS9_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ106MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS9_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS9_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS9_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS9_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS9 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN9, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs9].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS10 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) +/** + ****************************************************************************** + ** \brief FM4: MFS10 IRQ handler (IRQ#107) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS10_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS10_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ107MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS10_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS10_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS10_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS10_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS10 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10) +/** + ****************************************************************************** + ** \brief FM4: MFS10 IRQ handler (IRQ#108) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS10_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS10_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ108MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS10_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS10_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS10_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS10_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS10 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN10, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs10].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS11 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) +/** + ****************************************************************************** + ** \brief FM4: MFS11 IRQ handler (IRQ#109) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS11_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS11_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ109MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS11_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS11_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS11_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS11_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS11 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11) +/** + ****************************************************************************** + ** \brief FM4: MFS11 IRQ handler (IRQ#110) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS11_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS11_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ110MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS11_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS11_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS11_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS11_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS11 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN11, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs11].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC2) +/** + ****************************************************************************** + ** \brief FM4: ADC2 IRQ handler (IRQ#111) Type b + ******************************************************************************/ + #if (1u == IRQ_ADC2_AVAILABLE) + OSAL_IRQ_HANDLER(ADC2_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + #if (PDL_ON == PDL_DSTC_ENABLE_ADC2_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC2_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC2_PRIO, DSTC_IRQ_NUMBER_ADC2_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC2_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC2, &(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc2].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************************** FM4: DSTC_HWINT_NEW *****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC_HWINT_NEW) +/** + ****************************************************************************** + ** \brief FM4: DSTC_HWINT_NEW IRQ handler (IRQ#112) Type b + ******************************************************************************/ + #if (1u == IRQ_DSTC_HWINT_AVAILABLE) + OSAL_IRQ_HANDLER(DSTC_HWINT_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + Dstc_IrqHandler(); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM4: USB1_DEVICE, CEC0 ***************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) +/** + ****************************************************************************** + ** \brief FM4: USB1_DEVICE, CEC0 IRQ handler (IRQ#113) Type b + ******************************************************************************/ + #if (1u == IRQ_USB1_F_HDMICEC0_AVAILABLE) + OSAL_IRQ_HANDLER(USB1_F_HDMICEC0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ113MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) + if (0ul != (u32IrqMon & 0x0000001Ful)) + { + Usb_IrqHandler((stc_usb_t*)&USB1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC0) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + RcIrqHandler(0u); + } + #endif + + } + #elif (1u == IRQ_USB1_F_AVAILABLE) + void USB1_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB1); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************* FM4: USB1_HOST, USB1_DEVICE, CEC1 **********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) +/** + ****************************************************************************** + ** \brief FM4: USB1_HOST, USB1_DEVICE, CEC1 IRQ handler (IRQ#114) Type b + ******************************************************************************/ + #if (1u == IRQ_USB1_H_F_HDMICEC1_AVAILABLE) + OSAL_IRQ_HANDLER(USB1_H_F_HDMICEC1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ114MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_USB1_HOST) ||(PDL_ON == PDL_INTERRUPT_ENABLE_USB1_DEVICE) + if (0ul != (u32IrqMon & 0x0000003Ful)) + { + Usb_IrqHandler((stc_usb_t*)&USB1); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CEC1) + if (0ul != (u32IrqMon & 0x00000040ul)) + { + Rc_IrqHandler(1u); + } + #endif + + } + #elif (1u == IRQ_USB1_H_F_AVAILABLE) + void USB1_H_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB1); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: HSSPI *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_HSSPI) +/** + ****************************************************************************** + ** \brief FM4: HSSPI IRQ handler (IRQ#115) Type b + ******************************************************************************/ + #if (1u == IRQ_HSSPI0_AVAILABLE) + OSAL_IRQ_HANDLER(HSSPI0_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + HsspiHandler(); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/**************** FM4: I2S0, PCRC, I2S1, SD0, SD1, ICC0, ICC01 ****************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_PCRC) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2S1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_SD0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_SD1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC01) +/** + ****************************************************************************** + ** \brief FM4: I2S0, PCRC, I2S1, SD0, SD1, ICC0, ICC01 IRQ handler (IRQ#117) Type b + ******************************************************************************/ + #if (1u == IRQ_PCRC_I2S0_1_AVAILABLE) + OSAL_IRQ_HANDLER(PCRC_I2S0_1_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ117MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + I2sIrqHandler(&I2S0, &m_astcI2sInstanceDataLut[I2sInstanceIndexI2s0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_PCRC) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + PcrcIrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S1) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + I2sIrqHandler(&I2S1, &m_astcI2sInstanceDataLut[I2sInstanceIndexI2s1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_SD0) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + PDL_DummyHandler(16ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_SD1) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + PDL_DummyHandler(17ul); + } + #endif + + } + #elif (1u == IRQ_ICC0_1_AVAILABLE) + void ICC0_1_IRQHandler(void) + { + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_ICC01) + uint32_t u32IrqMon = FM_INTREQ->IRQ117MON; + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC0) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC0, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc0].stcInternData)); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_ICC01) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + Icc_IrqHandler((stc_iccn_t*) &ICC1, &(m_astcIccInstanceDataLut[IccInstanceIndexIcc1].stcInternData)); + } + #endif + + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: SD0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SD0) +/** + ****************************************************************************** + ** \brief FM4: SD0 IRQ handler (IRQ#118) Type b + ******************************************************************************/ + #if (1u == IRQ_SD_AVAILABLE) + OSAL_IRQ_HANDLER(SD_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(18ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: FLASH *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM4: FLASH IRQ handler (IRQ#119) Type b + ******************************************************************************/ + #if (1u == IRQ_FLASHIF_AVAILABLE) + OSAL_IRQ_HANDLER(FLASHIF_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + PDL_DummyHandler(19ul); + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS12 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12) +/** + ****************************************************************************** + ** \brief FM4: MFS12 IRQ handler (IRQ#120) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS12_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS12_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ120MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS12_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS12_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS12_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS12_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS12_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS12 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12) +/** + ****************************************************************************** + ** \brief FM4: MFS12 IRQ handler (IRQ#121) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS12_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS12_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ121MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS12_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS12_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS12_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS12_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS12_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS12 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN12, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs12].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS13 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13) +/** + ****************************************************************************** + ** \brief FM4: MFS13 IRQ handler (IRQ#122) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS13_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS13_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ122MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS13_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS13_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS13_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS13_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS13_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS13 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13) +/** + ****************************************************************************** + ** \brief FM4: MFS13 IRQ handler (IRQ#123) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS13_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS13_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ123MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS13_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS13_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS13_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS13_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS13_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS13 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN13, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs13].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS14 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14) +/** + ****************************************************************************** + ** \brief FM4: MFS14 IRQ handler (IRQ#124) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS14_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS14_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ124MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS14_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS14_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS14_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS14_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS14_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS14 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14) +/** + ****************************************************************************** + ** \brief FM4: MFS14 IRQ handler (IRQ#125) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS14_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS14_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ125MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS14_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS14_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS14_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS14_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS14_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS14 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN14, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs14].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS15 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15) +/** + ****************************************************************************** + ** \brief FM4: MFS15 IRQ handler (IRQ#126) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS15_RX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS15_RX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ126MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS15_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS15_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS15_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS15_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS15_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS15 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15) +/** + ****************************************************************************** + ** \brief FM4: MFS15 IRQ handler (IRQ#127) Type b + ******************************************************************************/ + #if (1u == IRQ_MFS15_TX_AVAILABLE) + OSAL_IRQ_HANDLER(MFS15_TX_IRQHandler) + { + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->IRQ127MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS15_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS15_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS15_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS15_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS15_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS15 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN15, &(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs15].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + OSAL_IRQ_EPILOGUE(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM4: NMI, HWWDG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM4: NMI, HWWDG IRQ handler (EXC#2) Type b + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +OSAL_IRQ_HANDLER(NMI_Handler) +{ + OSAL_IRQ_PROLOGUE(); + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + OSAL_IRQ_EPILOGUE(); +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM4_TYPE_B_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_c.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_c.c new file mode 100644 index 0000000000..58be077830 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/interrupts_fm4_type_c.c @@ -0,0 +1,3770 @@ +/******************************************************************************* +* \file interrupts_fm4_type_c.c +* +* \version 1.0 +* +* \brief Low-level interrupt processing layer to handle the hardware +* interrupts. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "interrupts_fm4.h" + +#ifdef __INTERRUPTS_FM4_TYPE_C_C__ + +/******************************************************************************/ +/******************************* Dummy Handler ********************************/ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Dummy Handler for not implemented peripheral handlers. During + ** debugging a breakpoint may be set here. The argument #u32Caller + ** contains the caller index from the handlers above. + ******************************************************************************/ + +void PDL_DummyHandler(uint32_t u32Caller) +{ + + // 0: IRQ003SEL, 1: IRQ004SEL, 2: IRQ005SEL, 3: IRQ006SEL, 4: IRQ007SEL, + // 5: IRQ008SEL, 6: IRQ009SEL, 7: IRQ010SEL, 8: EXTIF, 9: GDC_SDRAM, + // 10: UPLL, 11: I2SPLL, 12: GDC_PLL, 13: CANFD0, 14: CANFD0, 15: CANFD0, + // 16: GDC, 17: GDC, 18: GDC, 19: GDC, 20: GDC, 21: GDC, 22: GDC, + // 23: GDC, 24: GDC, 25: GDC, 26: GDC, 27: GDC, 28: GDC, 29: GDC, + // 30: GDC, 31: GDC, 32: GDC, 33: GDC, 34: GDC, 35: SD0, 36: FLASH, + // 37: GDC, 38: GDC, 39: GDC, 40: GDC, + + u32Caller = u32Caller; + while (1u) + { } +} + +/******************************************************************************/ +/********************************** FM4: CSV **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CSV) +/** + ****************************************************************************** + ** \brief FM4: CSV IRQ handler (IRQ#0) Type c + ******************************************************************************/ + #if (1u == IRQ_CSV_AVAILABLE) + void CSV_IRQHandler(void) + { + Csv_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: SWWDG *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SWWDG) +/** + ****************************************************************************** + ** \brief FM4: SWWDG IRQ handler (IRQ#1) Type c + ******************************************************************************/ + #if (1u == IRQ_SWDT_AVAILABLE) + void SWDT_IRQHandler(void) + { + SwwdgIrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: LVD **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_LVD) +/** + ****************************************************************************** + ** \brief FM4: LVD IRQ handler (IRQ#2) Type c + ******************************************************************************/ + #if (1u == IRQ_LVD_AVAILABLE) + void LVD_IRQHandler(void) + { + Lvd_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ003SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ003SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ003SEL IRQ handler (IRQ#3) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ003SEL_AVAILABLE) + void IRQ003SEL_IRQHandler(void) + { + PDL_DummyHandler(0ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ004SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ004SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ004SEL IRQ handler (IRQ#4) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ004SEL_AVAILABLE) + void IRQ004SEL_IRQHandler(void) + { + PDL_DummyHandler(1ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ005SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ005SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ005SEL IRQ handler (IRQ#5) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ005SEL_AVAILABLE) + void IRQ005SEL_IRQHandler(void) + { + PDL_DummyHandler(2ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ006SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ006SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ006SEL IRQ handler (IRQ#6) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ006SEL_AVAILABLE) + void IRQ006SEL_IRQHandler(void) + { + PDL_DummyHandler(3ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ007SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ007SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ007SEL IRQ handler (IRQ#7) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ007SEL_AVAILABLE) + void IRQ007SEL_IRQHandler(void) + { + PDL_DummyHandler(4ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ008SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ008SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ008SEL IRQ handler (IRQ#8) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ008SEL_AVAILABLE) + void IRQ008SEL_IRQHandler(void) + { + PDL_DummyHandler(5ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ009SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ009SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ009SEL IRQ handler (IRQ#9) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ009SEL_AVAILABLE) + void IRQ009SEL_IRQHandler(void) + { + PDL_DummyHandler(6ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: IRQ010SEL *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_IRQ010SEL) +/** + ****************************************************************************** + ** \brief FM4: IRQ010SEL IRQ handler (IRQ#10) Type c + ******************************************************************************/ + #if (1u == IRQ_IRQ010SEL_AVAILABLE) + void IRQ010SEL_IRQHandler(void) + { + PDL_DummyHandler(7ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT0) +/** + ****************************************************************************** + ** \brief FM4: EXINT0 IRQ handler (IRQ#11) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT0_AVAILABLE) + void EXINT0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT0)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT0); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT0) + + Exint_IrqHandler(0u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT1 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT1) +/** + ****************************************************************************** + ** \brief FM4: EXINT1 IRQ handler (IRQ#12) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT1_AVAILABLE) + void EXINT1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT1)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT1) + + Exint_IrqHandler(1u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT2 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT2) +/** + ****************************************************************************** + ** \brief FM4: EXINT2 IRQ handler (IRQ#13) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT2_AVAILABLE) + void EXINT2_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT2)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT2); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT2) + + Exint_IrqHandler(2u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT3 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT3) +/** + ****************************************************************************** + ** \brief FM4: EXINT3 IRQ handler (IRQ#14) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT3_AVAILABLE) + void EXINT3_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT3)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT3) + + Exint_IrqHandler(3u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT4 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT4) +/** + ****************************************************************************** + ** \brief FM4: EXINT4 IRQ handler (IRQ#15) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT4_AVAILABLE) + void EXINT4_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT4)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT4) + + Exint_IrqHandler(4u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT5 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT5) +/** + ****************************************************************************** + ** \brief FM4: EXINT5 IRQ handler (IRQ#16) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT5_AVAILABLE) + void EXINT5_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT5)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT5) + + Exint_IrqHandler(5u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT6 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT6) +/** + ****************************************************************************** + ** \brief FM4: EXINT6 IRQ handler (IRQ#17) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT6_AVAILABLE) + void EXINT6_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT6) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT6)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT6); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT6) + + Exint_IrqHandler(6u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT7 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT7) +/** + ****************************************************************************** + ** \brief FM4: EXINT7 IRQ handler (IRQ#18) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT7_AVAILABLE) + void EXINT7_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT7) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT7)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT7); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT7) + + Exint_IrqHandler(7u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: QPRC0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_QPRC0) +/** + ****************************************************************************** + ** \brief FM4: QPRC0 IRQ handler (IRQ#19) Type c + ******************************************************************************/ + #if (1u == IRQ_QPRC0_AVAILABLE) + void QPRC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_COUNT_INVERSION); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_OUT_OF_RANGE); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_MATCH_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_PC_RC_MATCH); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z)) + { + Dstc_QprcIrqHandler(DSTC_IRQ_NUMBER_QPRC0_UFL_OFL_Z); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH) && \ + (PDL_ON != PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z) + + Qprc_IrqHandler((stc_qprcn_t*)&QPRC0,&m_astcQprcInstanceDataLut[QprcInstanceIndexQprc0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_WFG ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_WFG) +/** + ****************************************************************************** + ** \brief FM4: MFT0_WFG IRQ handler (IRQ#21) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_WFG_DTIF_AVAILABLE) + void MFT0_WFG_DTIF_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG10)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG10); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG32) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG32)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG32); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_WFG54) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_WFG54)) + { + Dstc_MftWfgIrqHandler(DSTC_IRQ_NUMBER_MFT0_WFG54); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG10) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG32) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_WFG54) + + Mft_Wfg_IrqHandler((stc_mftn_wfg_t*)&MFT0_WFG,&m_astcMftWfgInstanceDataLut[WfgInstanceIndexWfg0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT0_FRT IRQ handler (IRQ#24) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_PEAK_AVAILABLE) + void MFT0_FRT_PEAK_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_PEAK); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK)) + { + Dstc_MftFrtPeakIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_PEAK); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_PEAK) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_PEAK) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT0_FRT,&m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_FRT ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_FRT) +/** + ****************************************************************************** + ** \brief FM4: MFT0_FRT IRQ handler (IRQ#25) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_FRT_ZERO_AVAILABLE) + void MFT0_FRT_ZERO_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT0_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT1_ZERO); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO)) + { + Dstc_MftFrtZeroIrqHandler(DSTC_IRQ_NUMBER_MFT0_FRT2_ZERO); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT0_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT1_ZERO) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_FRT2_ZERO) + + Mft_Frt_IrqHandler((stc_mftn_frt_t*)&MFT0_FRT,&m_astcMftFrtInstanceDataLut[FrtInstanceIndexFrt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_ICU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_ICU) +/** + ****************************************************************************** + ** \brief FM4: MFT0_ICU IRQ handler (IRQ#26) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_ICU_AVAILABLE) + void MFT0_ICU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU0)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU1)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU2)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_ICU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_ICU3)) + { + Dstc_MftIcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_ICU3); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_ICU3) + + Mft_Icu_IrqHandler((stc_mftn_icu_t*)&MFT0_ICU,&m_astcMftIcuInstanceDataLut[IcuInstanceIndexIcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************* FM4: MFT0_OCU ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFT0_OCU) +/** + ****************************************************************************** + ** \brief FM4: MFT0_OCU IRQ handler (IRQ#27) Type c + ******************************************************************************/ + #if (1u == IRQ_MFT0_OCU_AVAILABLE) + void MFT0_OCU_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU0)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU1) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU1)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU1); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU2)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU3) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU3)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU3); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU4)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU4); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_MFT0_OCU5) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFT0_OCU5)) + { + Dstc_MftOcuIrqHandler(DSTC_IRQ_NUMBER_MFT0_OCU5); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU0) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU1) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU2) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU3) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU4) && \ + (PDL_ON != PDL_DSTC_ENABLE_MFT0_OCU5) + + Mft_Ocu_IrqHandler((stc_mftn_ocu_t*)&MFT0_OCU,&m_astcMftOcuInstanceDataLut[OcuInstanceIndexOcu0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: PPG **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_PPG) +/** + ****************************************************************************** + ** \brief FM4: PPG IRQ handler (IRQ#36) Type c + ******************************************************************************/ + #if (1u == IRQ_PPG00_02_04_AVAILABLE) + void PPG00_02_04_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_PPG0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG0)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG0); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG2) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG2)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG2); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PPG4) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PPG4)) + { + Dstc_PpgIrqHandler(DSTC_IRQ_NUMBER_PPG4); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_PPG0) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG2) && \ + (PDL_ON != PDL_DSTC_ENABLE_PPG4) + + Ppg_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT0) +/** + ****************************************************************************** + ** \brief FM4: BT0 IRQ handler (IRQ#39) Type c + ******************************************************************************/ + #if (1u == IRQ_BT0_AVAILABLE) + void BT0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT0_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT0_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT0_IRQ0,DSTC_IRQ_NUMBER_BT0_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT0_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT0,&m_astcBtInstanceDataLut[BtInstanceIndexBt0].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT1) +/** + ****************************************************************************** + ** \brief FM4: BT1 IRQ handler (IRQ#40) Type c + ******************************************************************************/ + #if (1u == IRQ_BT1_AVAILABLE) + void BT1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT1_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT1_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT1_IRQ0,DSTC_IRQ_NUMBER_BT1_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT1_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT1,&m_astcBtInstanceDataLut[BtInstanceIndexBt1].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT2) +/** + ****************************************************************************** + ** \brief FM4: BT2 IRQ handler (IRQ#41) Type c + ******************************************************************************/ + #if (1u == IRQ_BT2_AVAILABLE) + void BT2_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT2_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT2_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT2_IRQ0,DSTC_IRQ_NUMBER_BT2_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT2_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT2,&m_astcBtInstanceDataLut[BtInstanceIndexBt2].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT3) +/** + ****************************************************************************** + ** \brief FM4: BT3 IRQ handler (IRQ#42) Type c + ******************************************************************************/ + #if (1u == IRQ_BT3_AVAILABLE) + void BT3_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT3_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT3_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT3_IRQ0,DSTC_IRQ_NUMBER_BT3_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT3_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT3,&m_astcBtInstanceDataLut[BtInstanceIndexBt3].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT4) +/** + ****************************************************************************** + ** \brief FM4: BT4 IRQ handler (IRQ#43) Type c + ******************************************************************************/ + #if (1u == IRQ_BT4_AVAILABLE) + void BT4_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT4_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT4_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT4_IRQ0,DSTC_IRQ_NUMBER_BT4_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT4_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT4,&m_astcBtInstanceDataLut[BtInstanceIndexBt4].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT5) +/** + ****************************************************************************** + ** \brief FM4: BT5 IRQ handler (IRQ#44) Type c + ******************************************************************************/ + #if (1u == IRQ_BT5_AVAILABLE) + void BT5_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT5_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT5_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT5_IRQ0,DSTC_IRQ_NUMBER_BT5_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT5_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT5,&m_astcBtInstanceDataLut[BtInstanceIndexBt5].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT6) +/** + ****************************************************************************** + ** \brief FM4: BT6 IRQ handler (IRQ#45) Type c + ******************************************************************************/ + #if (1u == IRQ_BT6_AVAILABLE) + void BT6_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT6_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT6_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT6_IRQ0,DSTC_IRQ_NUMBER_BT6_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT6_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT6,&m_astcBtInstanceDataLut[BtInstanceIndexBt6].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: BT7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_BT7) +/** + ****************************************************************************** + ** \brief FM4: BT7 IRQ handler (IRQ#46) Type c + ******************************************************************************/ + #if (1u == IRQ_BT7_AVAILABLE) + void BT7_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_BT7_IRQ0) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_BT7_IRQ0)) + { + Dstc_BtIrqHandler(DSTC_IRQ_NUMBER_BT7_IRQ0,DSTC_IRQ_NUMBER_BT7_IRQ1); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_BT7_IRQ0) + + Bt_IrqHandler((stc_btn_t*)&BT7,&m_astcBtInstanceDataLut[BtInstanceIndexBt7].stcInternData); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: DT0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) +/** + ****************************************************************************** + ** \brief FM4: DT0 IRQ handler (IRQ#47) Type c + ******************************************************************************/ + #if (1u == IRQ_DT_AVAILABLE) + void DT_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ047MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + DtIrqHandler(DtChannel0); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_DT0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + DtIrqHandler(DtChannel1); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: WC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_WC0) +/** + ****************************************************************************** + ** \brief FM4: WC0 IRQ handler (IRQ#48) Type c + ******************************************************************************/ + #if (1u == IRQ_WC_AVAILABLE) + void WC_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_WC) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_WC)) + { + Dstc_WcIrqHandler(); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_WC) + + Wc_IrqHandler((stc_wcn_t*)&WC0); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM4: EXTIF, GDC_SDRAM ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXTIF) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_GDC_SDRAM) +/** + ****************************************************************************** + ** \brief FM4: EXTIF, GDC_SDRAM IRQ handler (IRQ#49) Type c + ******************************************************************************/ + #if (1u == IRQ_EXTBUS_ERR_GDC_SDRAM_AVAILABLE) + void EXTBUS_ERR_GDC_SDRAM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ049MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_EXTIF) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + PDL_DummyHandler(8ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC_SDRAM) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + PDL_DummyHandler(9ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: RTC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_RTC0) +/** + ****************************************************************************** + ** \brief FM4: RTC0 IRQ handler (IRQ#50) Type c + ******************************************************************************/ + #if (1u == IRQ_RTC_AVAILABLE) + void RTC_IRQHandler(void) + { + Rtc_IrqHandler((stc_rtcn_t*)&RTC0,&(m_astcRtcInstanceDataLut[RtcInstanceIndexRtc0].stcInternData)); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT8 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT8) +/** + ****************************************************************************** + ** \brief FM4: EXINT8 IRQ handler (IRQ#51) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT8_AVAILABLE) + void EXINT8_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT8) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT8)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT8); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT8) + + Exint_IrqHandler(8u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT9 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT9) +/** + ****************************************************************************** + ** \brief FM4: EXINT9 IRQ handler (IRQ#52) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT9_AVAILABLE) + void EXINT9_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT9) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT9)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT9); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT9) + + Exint_IrqHandler(9u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT10 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT10) +/** + ****************************************************************************** + ** \brief FM4: EXINT10 IRQ handler (IRQ#53) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT10_AVAILABLE) + void EXINT10_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT10) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT10)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT10); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT10) + + Exint_IrqHandler(10u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT11 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT11) +/** + ****************************************************************************** + ** \brief FM4: EXINT11 IRQ handler (IRQ#54) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT11_AVAILABLE) + void EXINT11_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT11) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT11)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT11); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT11) + + Exint_IrqHandler(11u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT12 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT12) +/** + ****************************************************************************** + ** \brief FM4: EXINT12 IRQ handler (IRQ#55) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT12_AVAILABLE) + void EXINT12_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT12) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT12)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT12); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT12) + + Exint_IrqHandler(12u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT13 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT13) +/** + ****************************************************************************** + ** \brief FM4: EXINT13 IRQ handler (IRQ#56) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT13_AVAILABLE) + void EXINT13_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT13) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT13)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT13); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT13) + + Exint_IrqHandler(13u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT14 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT14) +/** + ****************************************************************************** + ** \brief FM4: EXINT14 IRQ handler (IRQ#57) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT14_AVAILABLE) + void EXINT14_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT14) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT14)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT14); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT14) + + Exint_IrqHandler(14u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: EXINT15 ********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_EXINT15) +/** + ****************************************************************************** + ** \brief FM4: EXINT15 IRQ handler (IRQ#58) Type c + ******************************************************************************/ + #if (1u == IRQ_EXINT15_AVAILABLE) + void EXINT15_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_EXINT15) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_EXINT15)) + { + Dstc_ExintIrqHandler(DSTC_IRQ_NUMBER_EXINT15); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_EXINT15) + + Exint_IrqHandler(15u); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************** FM4: CLK, UPLL, I2SPLL, GDC_PLL ***********************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_GDC_PLL) +/** + ****************************************************************************** + ** \brief FM4: CLK, UPLL, I2SPLL, GDC_PLL IRQ handler (IRQ#59) Type c + ******************************************************************************/ + #if (1u == IRQ_TIM_AVAILABLE) + void TIM_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ059MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CLK) + if (0ul != (u32IrqMon & 0x00000007ul)) + { + Clk_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_UPLL) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + PDL_DummyHandler(10ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2SPLL) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + PDL_DummyHandler(11ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC_PLL) + if (0ul != (u32IrqMon & 0x00000020ul)) + { + PDL_DummyHandler(12ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM4: MFS0 IRQ handler (IRQ#60) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS0_RX_AVAILABLE) + void MFS0_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ060MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS0_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0) +/** + ****************************************************************************** + ** \brief FM4: MFS0 IRQ handler (IRQ#61) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS0_TX_AVAILABLE) + void MFS0_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ061MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS0_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS0_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS0_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS0 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN0,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs0].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM4: MFS1 IRQ handler (IRQ#62) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS1_RX_AVAILABLE) + void MFS1_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ062MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS1_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1) +/** + ****************************************************************************** + ** \brief FM4: MFS1 IRQ handler (IRQ#63) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS1_TX_AVAILABLE) + void MFS1_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ063MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS1_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS1_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS1_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS1_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS1 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN1,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs1].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM4: MFS2 IRQ handler (IRQ#64) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS2_RX_AVAILABLE) + void MFS2_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ064MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS2_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2) +/** + ****************************************************************************** + ** \brief FM4: MFS2 IRQ handler (IRQ#65) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS2_TX_AVAILABLE) + void MFS2_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ065MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS2_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS2_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS2_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS2_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS2 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN2,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs2].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM4: MFS3 IRQ handler (IRQ#66) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS3_RX_AVAILABLE) + void MFS3_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ066MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS3_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3) +/** + ****************************************************************************** + ** \brief FM4: MFS3 IRQ handler (IRQ#67) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS3_TX_AVAILABLE) + void MFS3_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ067MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS3_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS3_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS3_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS3_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS3 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN3,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs3].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM4: MFS4 IRQ handler (IRQ#68) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS4_RX_AVAILABLE) + void MFS4_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ068MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS4_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4) +/** + ****************************************************************************** + ** \brief FM4: MFS4 IRQ handler (IRQ#69) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS4_TX_AVAILABLE) + void MFS4_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ069MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS4_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS4_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS4_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS4_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS4 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN4,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs4].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM4: MFS5 IRQ handler (IRQ#70) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS5_RX_AVAILABLE) + void MFS5_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ070MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS5_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5) +/** + ****************************************************************************** + ** \brief FM4: MFS5 IRQ handler (IRQ#71) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS5_TX_AVAILABLE) + void MFS5_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ071MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS5_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS5_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS5_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS5_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS5 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN5,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs5].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM4: MFS6 IRQ handler (IRQ#72) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS6_RX_AVAILABLE) + void MFS6_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ072MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS6_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x000000012ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6) +/** + ****************************************************************************** + ** \brief FM4: MFS6 IRQ handler (IRQ#73) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS6_TX_AVAILABLE) + void MFS6_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ073MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS6_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS6_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS6_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS6_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS6 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN6,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs6].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM4: MFS7 IRQ handler (IRQ#74) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS7_RX_AVAILABLE) + void MFS7_RX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ074MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_RX)) + { + Dstc_MfsRxIrqHandler(DSTC_IRQ_NUMBER_MFS7_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_RX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerRx((stc_mfsn_uart_t*)&UART7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerRx((stc_mfsn_csio_t*)&CSIO7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerRx((stc_mfsn_i2c_t*)&I2C7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerRx((stc_mfsn_lin_t*)&LIN7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: MFS7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7) +/** + ****************************************************************************** + ** \brief FM4: MFS7 IRQ handler (IRQ#75) Type c + ******************************************************************************/ + #if (1u == IRQ_MFS7_TX_AVAILABLE) + void MFS7_TX_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ075MON; + + #if (PDL_ON == PDL_DSTC_ENABLE_MFS7_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_MFS7_TX)) + { + Dstc_MfsTxIrqHandler(DSTC_IRQ_NUMBER_MFS7_TX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_MFS7_TX) + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + MfsUartIrqHandlerTx((stc_mfsn_uart_t*)&UART7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerTx((stc_mfsn_csio_t*)&CSIO7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerTx((stc_mfsn_i2c_t*)&I2C7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerTx((stc_mfsn_lin_t*)&LIN7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_MFS7 ) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + switch(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData.enMode) + { + case MfsUartMode: + // should never happen + while (1u) + { } + case MfsCsioMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + MfsCsioIrqHandlerStatus((stc_mfsn_csio_t*)&CSIO7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsI2cMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + MfsI2cIrqHandlerStatus((stc_mfsn_i2c_t*)&I2C7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + case MfsLinMode: + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + MfsLinIrqHandlerStatus((stc_mfsn_lin_t*)&LIN7,&(m_astcMfsInstanceDataLut[MfsInstanceIndexMfs7].stcInternData)); + #endif + break; + default: + break; + } + } + #endif + + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC0) +/** + ****************************************************************************** + ** \brief FM4: ADC0 IRQ handler (IRQ#76) Type c + ******************************************************************************/ + #if (1u == IRQ_ADC0_AVAILABLE) + void ADC0_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC0_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC0_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC0_PRIO,DSTC_IRQ_NUMBER_ADC0_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC0_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC0,&(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc0].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: ADC1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_ADC1) +/** + ****************************************************************************** + ** \brief FM4: ADC1 IRQ handler (IRQ#77) Type c + ******************************************************************************/ + #if (1u == IRQ_ADC1_AVAILABLE) + void ADC1_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_ADC1_PRIO) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_ADC1_PRIO)) + { + Dstc_AdcIrqHandler(DSTC_IRQ_NUMBER_ADC1_PRIO,DSTC_IRQ_NUMBER_ADC1_SCAN); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_ADC1_PRIO) + + AdcIrqHandler((stc_adcn_t*)&ADC1,&(m_astcAdcInstanceDataLut[AdcInstanceIndexAdc1].stcInternData)); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM4: USB0_DEVICE ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM4: USB0_DEVICE IRQ handler (IRQ#78) Type c + ******************************************************************************/ + #if (1u == IRQ_USB0_F_AVAILABLE) + void USB0_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/************************ FM4: USB0_HOST, USB0_DEVICE *************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_HOST) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_USB0_DEVICE) +/** + ****************************************************************************** + ** \brief FM4: USB0_HOST, USB0_DEVICE IRQ handler (IRQ#79) Type c + ******************************************************************************/ + #if (1u == IRQ_USB0_H_F_AVAILABLE) + void USB0_H_F_IRQHandler(void) + { + Usb_IrqHandler((stc_usb_t*)&USB0); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/******************************** FM4: CANFD0 *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) +/** + ****************************************************************************** + ** \brief FM4: CANFD0 IRQ handler (IRQ#81) Type c + ******************************************************************************/ + #if (1u == IRQ_CANFD0_AVAILABLE) + void CANFD0_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ081MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + PDL_DummyHandler(13ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) + if (0ul != (u32IrqMon & 0x00000008ul)) + { + PDL_DummyHandler(14ul); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_CANFD0) + if (0ul != (u32IrqMon & 0x00000010ul)) + { + PDL_DummyHandler(15ul); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA0) +/** + ****************************************************************************** + ** \brief FM4: DMA0 IRQ handler (IRQ#83) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC0_AVAILABLE) + void DMAC0_IRQHandler(void) + { + DmaIrqHandler(0u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA1 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA1) +/** + ****************************************************************************** + ** \brief FM4: DMA1 IRQ handler (IRQ#84) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC1_AVAILABLE) + void DMAC1_IRQHandler(void) + { + DmaIrqHandler(1u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA2 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA2) +/** + ****************************************************************************** + ** \brief FM4: DMA2 IRQ handler (IRQ#85) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC2_AVAILABLE) + void DMAC2_IRQHandler(void) + { + DmaIrqHandler(2u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA3 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA3) +/** + ****************************************************************************** + ** \brief FM4: DMA3 IRQ handler (IRQ#86) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC3_AVAILABLE) + void DMAC3_IRQHandler(void) + { + DmaIrqHandler(3u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA4 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA4) +/** + ****************************************************************************** + ** \brief FM4: DMA4 IRQ handler (IRQ#87) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC4_AVAILABLE) + void DMAC4_IRQHandler(void) + { + DmaIrqHandler(4u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA5 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA5) +/** + ****************************************************************************** + ** \brief FM4: DMA5 IRQ handler (IRQ#88) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC5_AVAILABLE) + void DMAC5_IRQHandler(void) + { + DmaIrqHandler(5u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA6 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA6) +/** + ****************************************************************************** + ** \brief FM4: DMA6 IRQ handler (IRQ#89) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC6_AVAILABLE) + void DMAC6_IRQHandler(void) + { + DmaIrqHandler(6u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DMA7 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DMA7) +/** + ****************************************************************************** + ** \brief FM4: DMA7 IRQ handler (IRQ#90) Type c + ******************************************************************************/ + #if (1u == IRQ_DMAC7_AVAILABLE) + void DMAC7_IRQHandler(void) + { + DmaIrqHandler(7u); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: DSTC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC) +/** + ****************************************************************************** + ** \brief FM4: DSTC IRQ handler (IRQ#91) Type c + ******************************************************************************/ + #if (1u == IRQ_DSTC_AVAILABLE) + void DSTC_IRQHandler(void) + { + Dstc_IrqHandler(); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#92) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_CMD_SEQ_AVAILABLE) + void GDC_CMD_SEQ_IRQHandler(void) + { + PDL_DummyHandler(16ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#93) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_BLT_ENG_AVAILABLE) + void GDC_BLT_ENG_IRQHandler(void) + { + PDL_DummyHandler(17ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#94) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DRW_ENG_AVAILABLE) + void GDC_DRW_ENG_IRQHandler(void) + { + PDL_DummyHandler(18ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#95) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_CONT_STRM0_AVAILABLE) + void GDC_CONT_STRM0_IRQHandler(void) + { + PDL_DummyHandler(19ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#96) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_SAFE_STRM0_AVAILABLE) + void GDC_SAFE_STRM0_IRQHandler(void) + { + PDL_DummyHandler(20ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#97) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP_STRM0_AVAILABLE) + void GDC_DISP_STRM0_IRQHandler(void) + { + PDL_DummyHandler(21ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#98) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_SIGNA0_AVAILABLE) + void GDC_SIGNA0_IRQHandler(void) + { + PDL_DummyHandler(22ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#99) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP0_SYNC0_AVAILABLE) + void GDC_DISP0_SYNC0_IRQHandler(void) + { + PDL_DummyHandler(23ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#100) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP0_SYNC1_AVAILABLE) + void GDC_DISP0_SYNC1_IRQHandler(void) + { + PDL_DummyHandler(24ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#101) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_CONT_STRM1_AVAILABLE) + void GDC_CONT_STRM1_IRQHandler(void) + { + PDL_DummyHandler(25ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#102) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_SAFE_STRM1_AVAILABLE) + void GDC_SAFE_STRM1_IRQHandler(void) + { + PDL_DummyHandler(26ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#103) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP_STRM1_AVAILABLE) + void GDC_DISP_STRM1_IRQHandler(void) + { + PDL_DummyHandler(27ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#104) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_SIGNA1_AVAILABLE) + void GDC_SIGNA1_IRQHandler(void) + { + PDL_DummyHandler(28ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#105) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP1_SYNC0_AVAILABLE) + void GDC_DISP1_SYNC0_IRQHandler(void) + { + PDL_DummyHandler(29ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#106) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP1_SYNC1_AVAILABLE) + void GDC_DISP1_SYNC1_IRQHandler(void) + { + PDL_DummyHandler(30ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#107) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_CAP_PLN0_AVAILABLE) + void GDC_CAP_PLN0_IRQHandler(void) + { + PDL_DummyHandler(31ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#108) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_DISP_PLN0_AVAILABLE) + void GDC_DISP_PLN0_IRQHandler(void) + { + PDL_DummyHandler(32ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#109) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_STRG_STRM0_AVAILABLE) + void GDC_STRG_STRM0_IRQHandler(void) + { + PDL_DummyHandler(33ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#110) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_HISTGRM_AVAILABLE) + void GDC_HISTGRM_IRQHandler(void) + { + PDL_DummyHandler(34ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/***************************** FM4: DSTC_I1S0_RX ******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_DSTC_I1S0_RX) +/** + ****************************************************************************** + ** \brief FM4: DSTC_I1S0_RX IRQ handler (IRQ#112) Type c + ******************************************************************************/ + #if (1u == IRQ_DSTC_HW_AVAILABLE) + void DSTC_HW_IRQHandler(void) + { + #if (PDL_ON == PDL_DSTC_ENABLE_I2S0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_I2S0_RX)) + { + Dstc_I2sIrqHandler(DSTC_IRQ_NUMBER_I2S0_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_I2S0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_I2S0_TX)) + { + Dstc_I2sIrqHandler(DSTC_IRQ_NUMBER_I2S0_TX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_HSSPI0_RX)) + { + Dstc_HsspiIrqHandler(DSTC_IRQ_NUMBER_HSSPI0_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_HSSPI0_TX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_HSSPI0_TX)) + { + Dstc_HsspiIrqHandler(DSTC_IRQ_NUMBER_HSSPI0_TX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_PCRC) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_PCRC)) + { + Dstc_PcrcIrqHandler(DSTC_IRQ_NUMBER_PCRC); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_CANFD) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_CANFD)) + { + Dstc_CanfdIrqHandler(DSTC_IRQ_NUMBER_CANFD); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_I2S1_RX)) + { + Dstc_I2sIrqHandler(DSTC_IRQ_NUMBER_I2S1_RX); + } + #endif + + #if (PDL_ON == PDL_DSTC_ENABLE_I2S1_RX) + if (TRUE == Dstc_ReadHwintBit(DSTC_IRQ_NUMBER_I2S1_RX)) + { + Dstc_I2sIrqHandler(DSTC_IRQ_NUMBER_I2S1_RX); + } + #endif + + + #if (PDL_ON != PDL_DSTC_ENABLE_I2S0_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_I2S0_TX) && \ + (PDL_ON != PDL_DSTC_ENABLE_HSSPI0_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_HSSPI0_TX) && \ + (PDL_ON != PDL_DSTC_ENABLE_PCRC) && \ + (PDL_ON != PDL_DSTC_ENABLE_CANFD) && \ + (PDL_ON != PDL_DSTC_ENABLE_I2S1_RX) && \ + (PDL_ON != PDL_DSTC_ENABLE_I2S1_RX) + + Dstc_IrqHandler(); + + #endif // #if (PDL_ON != PDL_DSTC_ENABLE_... ) + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/*************************** FM4: I2S0, I2S1, PCRC ****************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S0) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_I2S1) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_PCRC) +/** + ****************************************************************************** + ** \brief FM4: I2S0, I2S1, PCRC IRQ handler (IRQ#117) Type c + ******************************************************************************/ + #if (1u == IRQ_PCRC_I2S0_1_AVAILABLE) + void PCRC_I2S0_1_IRQHandler(void) + { + uint32_t u32IrqMon = FM_INTREQ->IRQ117MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S0) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + I2sIrqHandler(&I2S0,&m_astcI2sInstanceDataLut[I2sInstanceIndexI2s0].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_I2S1) + if (0ul != (u32IrqMon & 0x00000004ul)) + { + I2sIrqHandler(&I2S1,&m_astcI2sInstanceDataLut[I2sInstanceIndexI2s1].stcInternData); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_PCRC) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + PcrcIrqHandler(); + } + #endif + + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: SD0 **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_SD0) +/** + ****************************************************************************** + ** \brief FM4: SD0 IRQ handler (IRQ#118) Type c + ******************************************************************************/ + #if (1u == IRQ_SD_AVAILABLE) + void SD_IRQHandler(void) + { + PDL_DummyHandler(35ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************* FM4: FLASH *********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_FLASH) +/** + ****************************************************************************** + ** \brief FM4: FLASH IRQ handler (IRQ#119) Type c + ******************************************************************************/ + #if (1u == IRQ_FLASHIF_AVAILABLE) + void FLASHIF_IRQHandler(void) + { + PDL_DummyHandler(36ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#120) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_HSSPI_RX_AVAILABLE) + void GDC_HSSPI_RX_IRQHandler(void) + { + PDL_DummyHandler(37ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#121) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_HSSPI_TX_AVAILABLE) + void GDC_HSSPI_TX_IRQHandler(void) + { + PDL_DummyHandler(38ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#122) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_HSSPI_FAULT_AVAILABLE) + void GDC_HSSPI_FAULT_IRQHandler(void) + { + PDL_DummyHandler(39ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/********************************** FM4: GDC **********************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_GDC) +/** + ****************************************************************************** + ** \brief FM4: GDC IRQ handler (IRQ#123) Type c + ******************************************************************************/ + #if (1u == IRQ_GDC_HYPERBUS_AVAILABLE) + void GDC_HYPERBUS_IRQHandler(void) + { + PDL_DummyHandler(40ul); + } + #else + #error No IRQ handler found. + #endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +/******************************************************************************/ +/****************************** FM4: NMI, HWWDG *******************************/ +/******************************************************************************/ +#if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) || \ + (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) +/** + ****************************************************************************** + ** \brief FM4: NMI, HWWDG IRQ handler (EXC#2) Type c + ******************************************************************************/ + #if (1u == IRQ_NMI_AVAILABLE) +void NMI_Handler(void) +{ + uint32_t u32IrqMon = FM_INTREQ->EXC02MON; + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_NMI) + if (0ul != (u32IrqMon & 0x00000001ul)) + { + Exint_Nmi_IrqHandler(); + } + #endif + + #if (PDL_ON == PDL_INTERRUPT_ENABLE_HWWDG) + if (0ul != (u32IrqMon & 0x00000002ul)) + { + HwwdgIrqHandler(); + } + #endif + +} +#else + #error No IRQ handler found. +#endif // #if (1u == IRQ_ ... _AVAILABLE) +#endif // #if (PDL_ON == PDL_INTERRUPT_ENABLE_ ... ) + + +#endif // #ifdef __INTERRUPTS_FM4_TYPE_C_C__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lcd/lcd.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lcd/lcd.c new file mode 100644 index 0000000000..2a6549c093 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lcd/lcd.c @@ -0,0 +1,666 @@ +/******************************************************************************* +* \file lcd.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the LCD +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lcd/lcd.h" + +#if (defined(PDL_PERIPHERAL_LCD_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define LCD_RAM_MAX_INDEX (39u) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) +static func_ptr_t m_pfnIrqCb = NULL; +#endif + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl.h + ******************************************************************************/ +static void LcdInitNvic(void) +{ + NVIC_ClearPendingIRQ(LCDC_IRQn); + NVIC_EnableIRQ(LCDC_IRQn); + NVIC_SetPriority(LCDC_IRQn, PDL_IRQ_LEVEL_LCDC); + + return; +} + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ******************************************************************************/ +static void LcdDeInitNvic(void) +{ + NVIC_ClearPendingIRQ(LCDC_IRQn); + NVIC_DisableIRQ(LCDC_IRQn); + NVIC_SetPriority(LCDC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + + return; +} + +/** + ****************************************************************************** + ** \brief Irq of the LCD module + ******************************************************************************/ +void Lcd_IrqHandler(void) +{ + if(1u == bFM_LCDC_LCDCC2_LCDIF) + { + bFM_LCDC_LCDCC2_LCDIF = 0u; + if(NULL != m_pfnIrqCb) + { + m_pfnIrqCb(); + } + } + + return; +} +#endif + +/** + ****************************************************************************** + ** \brief Initialize the LCD module + ** + ** \param pstcConfig: LCD module configuration + ** + ** \retval Ok Initializiation of LCD successfully done. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - pstcConfig == NULL + ** - pstcConfig->enDispMode > Lcd_8Com_1Div8Duty + ** - pstcConfig->enDivResVal > LcdDivRes10K + ** - pstcConfig->en8ComBias > Lcd1Div4Bias + ** - pstcConfig->enInputIoMode > LcdInputIoConnect + ** - pstcConfig->stcClkConf.u32DivVal > 0x200000u + ** - pstcConfig->stcClkConf.u32DivVal == 0x00u + ** - pstcConfig->stcClkConf.enSrcClk > LcdClkSelPclk + ** + ******************************************************************************/ +en_result_t Lcd_Init(const stc_lcd_config_t* pstcConfig) +{ + en_result_t enResult = ErrorInvalidParameter; + stc_lcdc_lcdcc1_field_t stcLCDCC1; + stc_lcdc_lcdcc2_field_t stcLCDCC2; + stc_lcdc_lcdcc3_field_t stcLCDCC3; + stc_lcdc_lcdc_blink_field_t stcLCDC_BLINK; +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + stc_lcdc_lcdc_booster_field_t stcLCDC_BOOSTER; +#endif + if (NULL != pstcConfig) + { + PDL_ZERO_STRUCT(stcLCDCC1); + PDL_ZERO_STRUCT(stcLCDCC2); + PDL_ZERO_STRUCT(stcLCDCC3); + PDL_ZERO_STRUCT(stcLCDC_BLINK); +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + PDL_ZERO_STRUCT(stcLCDC_BOOSTER); +#endif + /*LCDC Control Register 1*/ + stcLCDCC1.LCDEN = ((pstcConfig->bTimerMod == TRUE) ? 1u : 0u); + stcLCDCC1.VSEL = ((pstcConfig->enDivMode == LcdcIntRes) ? 1u : 0u); //VSEL = 1 internal divider resister + switch(pstcConfig->enDispMode) + { + case LcdStop: + stcLCDCC1.MS = 0u; + break; + case Lcd_4Com_1Div2Duty: + stcLCDCC1.MS = 1u; // 4COM 1/2 bias + break; + case Lcd_4Com_1Div3Duty: + stcLCDCC1.MS = 2u; // 4COM 1/3 bias + break; + case Lcd_4Com_1Div4Duty: + stcLCDCC1.MS = 3u; // 4COM 1/4 bias + break; + case Lcd_8Com_1Div8Duty: + stcLCDCC1.MS = 4u; // 8COM 1/8 bias + break; + default: + return ErrorInvalidParameter; + } + // Update hardware + FM_LCDC->LCDCC1_f = stcLCDCC1; + + /*LCDC Control Register 2*/ + switch(pstcConfig->enDivResVal) + { + case LcdDivRes100K: + stcLCDCC2.RSEL = 0u; + break; + case LcdDivRes10K: + stcLCDCC2.RSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + if(Lcd_8Com_1Div8Duty == pstcConfig->enDispMode) + { + switch(pstcConfig->en8ComBias) + { + case Lcd1Div3Bias: + stcLCDCC2.BLS8 = 0u; + break; + case Lcd1Div4Bias: + stcLCDCC2.BLS8 = 1u; + break; + default: + return ErrorInvalidParameter; + } + } + stcLCDCC2.INV = ((pstcConfig->bEnDispRevs == TRUE) ? 1u : 0u); + stcLCDCC2.BK = ((pstcConfig->bEnBlankDisp == TRUE) ? 1u : 0u); + stcLCDCC2.LCDIF = 0u; + // Update hardware + FM_LCDC->LCDCC2_f = stcLCDCC2; + + /*LCDC Control Register 3*/ + // Update hardware + FM_LCDC->LCDCC3 = (pstcConfig->stcVvSel.u8Vv << 1u); + switch(pstcConfig->enInputIoMode) + { + case LcdInputIoCutoff: + FM_LCDC->LCDCC3_f.PICTL = 0u; + break; + case LcdInputIoConnect: + FM_LCDC->LCDCC3_f.PICTL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + /*LCDC Clock Prescaler Register*/ + if((pstcConfig->stcClkConf.u32DivVal > 0x200000u) || + (0u == pstcConfig->stcClkConf.u32DivVal)) + { + return ErrorInvalidParameter; + } + FM_LCDC->LCDC_PSR = pstcConfig->stcClkConf.u32DivVal; + switch(pstcConfig->stcClkConf.enSrcClk) + { + case LcdClkSelSubClk: + FM_LCDC->LCDC_PSR_f.CLKSEL = 0u; + break; + case LcdClkSelPclk: + FM_LCDC->LCDC_PSR_f.CLKSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + /*LCDC COM Output Enable Register*/ + // Update hardware + FM_LCDC->LCDC_COMEN = pstcConfig->stcComSel.u8ComSel; + + /*LCDC SEG Output Enable Register 1 */ + // Update hardware + FM_LCDC->LCDC_SEGEN1 = pstcConfig->stcSegSel1.u32SegSel1; + FM_LCDC->LCDC_SEGEN2 = pstcConfig->stcSegSel2.u32SegSel2; + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + if(TRUE == pstcConfig->bEnBooster) + { + FM_LCDC->LCDC_BOOSTER_f.BTRC = pstcConfig->stcBooster.BTRC; + FM_LCDC->LCDC_BOOSTER_f.BTRF = pstcConfig->stcBooster.BTRF; + FM_LCDC->LCDC_BOOSTER_f.CENSEL = pstcConfig->stcBooster.CENSEL; + FM_LCDC->LCDC_BOOSTER_f.BSTOPT = pstcConfig->stcBooster.BSTOPT; + FM_LCDC->LCDC_BOOSTER_f.BSTPD = pstcConfig->stcBooster.BSTPD; + } +#endif + +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) + FM_LCDC->LCDCC2_f.LCDIEN = ((pstcConfig->bIrqEn == TRUE) ? 1u : 0u); + m_pfnIrqCb = pstcConfig->pfnIrqCb; + // Initialize NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + LcdInitNvic(); + } + else + { + LcdDeInitNvic(); + } +#endif + enResult = Ok; + } + + return (enResult); +} + +/** + ****************************************************************************** + ** \brief De-Initialize LCD + ******************************************************************************/ +void Lcd_DeInit( void) +{ + FM_LCDC->LCDCC1 = 0x00u; + FM_LCDC->LCDCC2 = 0x14u; + FM_LCDC->LCDCC2 = 0x3Eu; + FM_LCDC->LCDC_PSR = 0x00000000u; + FM_LCDC->LCDC_COMEN = 0x00000000u; + FM_LCDC->LCDC_SEGEN1 = 0x00000000u; + FM_LCDC->LCDC_SEGEN2 = 0x00000000u; + FM_LCDC->LCDC_SEGEN2 = 0x00000000u; + FM_LCDC->LCDC_BLINK = 0x0000u; + #if (PDL_MCU_CORE == PDL_FM0P_CORE) + FM_LCDC->LCDC_BOOSTER = 0x0E03u; + #endif + +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) + m_pfnIrqCb = NULL; + LcdDeInitNvic(); +#endif + + return; +} + +/** + ****************************************************************************** + ** \brief Configure LCD input IO mode + ** \param enInputIoMode + ** \arg LcdInputIoCutoff: Input IO of LCD is cut-off + ** \arg LcdInputIoConnect: Input IO of LCD is not cut-off + ** + ** \retval Ok LCD input IO mode is set normally. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - enInputIoMode > LcdInputIoConnect + ** + ******************************************************************************/ +en_result_t Lcd_ConfInputIoMode(en_lcd_input_io_mode_t enInputIoMode) +{ + switch(enInputIoMode) + { + case LcdInputIoCutoff: + FM_LCDC->LCDCC3_f.PICTL = 0u; + break; + case LcdInputIoConnect: + FM_LCDC->LCDCC3_f.PICTL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Config LCD display mode + ** + ** \param enDispMode + ** + ******************************************************************************/ +void Lcd_SetDispMode(en_lcd_disp_mode_t enDispMode) +{ + switch(enDispMode) + { + case LcdStop: + FM_LCDC->LCDCC1_f.MS = 0u; // stop display + break; + case Lcd_4Com_1Div2Duty: + FM_LCDC->LCDCC1_f.MS = 1u; // 4 COM 1/2 bias + break; + case Lcd_4Com_1Div3Duty: + FM_LCDC->LCDCC1_f.MS = 2u; // 4 COM 1/3 bias + break; + case Lcd_4Com_1Div4Duty: + FM_LCDC->LCDCC1_f.MS = 3u; // 4COM 1/4 bias + break; + case Lcd_8Com_1Div8Duty: + FM_LCDC->LCDCC1_f.MS = 4u; // 8COM 1/8 bias + break; + default: + break; + } + + return; +} + +/** + ****************************************************************************** + ** \brief Blank is displayed + ******************************************************************************/ +void Lcd_EnableBlankDisp(void) +{ + + FM_LCDC->LCDCC2_f.BK = 1u; // display blank + + return; +} + +/** + ****************************************************************************** + ** \brief Data stored in LCDRAM is displayed. + ******************************************************************************/ +void Lcd_DisableBlankDisp(void) +{ + + FM_LCDC->LCDCC2_f.BK = 0u; // display according with LCDRAM data + + return; +} + +/** + ****************************************************************************** + ** \brief Set bitsmap in the LCD RAM . + ** + ** \param u8RAMIndex LCD RAM index + ** \param u8Bitsmap Bit map in a RAM byte + ** \param bBit Bit value + ** + ** \retval Ok bitsmap in the LCD RAM is set normally. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - u8RAMIndex > LCD_RAM_MAX_INDEX + ** + ******************************************************************************/ +en_result_t Lcd_WriteRAMBits(uint8_t u8RAMIndex, uint8_t u8Bitsmap, + boolean_t bBit) +{ + if(u8RAMIndex > LCD_RAM_MAX_INDEX) + return ErrorInvalidParameter; + + if(0u == bBit) + { + *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + u8RAMIndex) &= ~u8Bitsmap; + } + else + { + *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + u8RAMIndex) |= u8Bitsmap; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set 1 bit in the LCD RAM . + ** + ** \param u8RAMIndex LCD RAM index + ** \param u8BitIndex Bit index in a RAM byte + ** \param bBit Bit value + ** + ** \retval Ok 1 bit in the LCD RAM is set normally. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - u8RAMIndex > LCD_RAM_MAX_INDEX + ** + ******************************************************************************/ +en_result_t Lcd_WriteRAMBit(uint8_t u8RAMIndex, uint8_t u8BitIndex, + boolean_t bBit) +{ + if(u8RAMIndex > LCD_RAM_MAX_INDEX) + return ErrorInvalidParameter; + + if(0 == bBit) + { + *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + u8RAMIndex) &= ~(1ul<LCDRAM00)) + u8RAMIndex) |= (1ul< LCD_RAM_MAX_INDEX + ** + ******************************************************************************/ +en_result_t Lcd_WriteRAMByte(uint8_t u8RAMIndex, uint8_t u8DataByte) +{ + if(u8RAMIndex > LCD_RAM_MAX_INDEX) + return ErrorInvalidParameter; + + *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + u8RAMIndex) = u8DataByte; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read byte from LCD RAM . + ** + ** \param u8RAMIndex LCD RAM index + ** \param pu8DataByte pointer of buffer + ** + ** \retval Ok Byte in the LCD RAM is read normally. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - u8RAMIndex > LCD_RAM_MAX_INDEX + ** + ******************************************************************************/ +en_result_t Lcd_ReadRAMByte(uint8_t u8RAMIndex, uint8_t *pu8DataByte) +{ + if(u8RAMIndex > LCD_RAM_MAX_INDEX) + return ErrorInvalidParameter; + + *pu8DataByte = *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + u8RAMIndex); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief LCD is display all. + ******************************************************************************/ +void Lcd_FillWholeRam(void) +{ + uint8_t i; + + for (i = 0; i <= LCD_RAM_MAX_INDEX; i++) + { + *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + i) = 0xFFu; + } + + return; +} + +/** + ****************************************************************************** + ** \brief Clear LCD all. + ******************************************************************************/ +void Lcd_ClrWholeRam(void) +{ + uint8_t i; + + for (i = 0; i <= LCD_RAM_MAX_INDEX; i++) + { + *((volatile uint8_t*)(&(FM_LCDC->LCDRAM00)) + i) = 0x00u; + } + + return; +} + +/** + ****************************************************************************** + ** \brief Select blink interval time + ** \param enBlinkInterval + ** \arg LCD_BLINK_HALF_SEC blink interval is 0.5s + ** \arg LCD_BLINK_ONE_SEC blink interval is 1s + ** + ** \retval Ok Blink interval time is set normally. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - enBlinkInterval > LcdBlinkIntOneSecond + ** + ******************************************************************************/ +en_result_t Lcd_SetBinkInterval(en_lcd_blink_interval_t enBlinkInterval) +{ + switch(enBlinkInterval) + { + case LcdBlinkIntHalfSecond: + FM_LCDC->LCDCC3_f.BLSEL = 0u; + break; + case LcdBlinkIntOneSecond: + FM_LCDC->LCDCC3_f.BLSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select blink dot + ** + ** \param enBlinkDot blink dot + ** \param enBlinkOp blink operation + ** + ** \retval Ok Blink dot is set normally. + ** \retval ErrorInvalidParameter If one of following condition matches: + ** - enBlinkDot > LCDC_Blik8COMS0C0 + ** - LcdBlinkOff != enBlinkOp && LcdBlinkOn != enBlinkOp + ** + ******************************************************************************/ +en_result_t Lcd_SetBlinkDot(en_lcd_blink_dot_t enBlinkDot, + en_lcd_blink_operation_t enBlinkOp) +{ + if((LcdBlinkOff != enBlinkOp)&&(LcdBlinkOn != enBlinkOp)) + return ErrorInvalidParameter; + + if(LCDC_BlinkDotOff == enBlinkDot) + { + FM_LCDC->LCDC_BLINK = 0x0000u; //close all blink function + return Ok; + } + + if((LCDC_Blik4COMS3C3 == enBlinkDot)||(LCDC_Blik8COMS1C7 == enBlinkDot)) //blink 4COM SEG3-SOM3 or 8COM SEG1-COM7 + FM_LCDC->LCDC_BLINK_f.BLD15 = enBlinkOp; + else if((LCDC_Blik4COMS3C2 == enBlinkDot)||(LCDC_Blik8COMS1C6 == enBlinkDot)) //blink 4COM SEG3-SOM2 or 8COM SEG1-COM6 + FM_LCDC->LCDC_BLINK_f.BLD14 = enBlinkOp; + else if((LCDC_Blik4COMS3C1 == enBlinkDot)||(LCDC_Blik8COMS1C5 == enBlinkDot)) //blink 4COM SEG3-SOM1 or 8COM SEG1-COM5 + FM_LCDC->LCDC_BLINK_f.BLD13 = enBlinkOp; + else if((LCDC_Blik4COMS3C0 == enBlinkDot)||(LCDC_Blik8COMS1C4 == enBlinkDot)) //blink 4COM SEG3-SOM0 or 8COM SEG1-COM4 + FM_LCDC->LCDC_BLINK_f.BLD12 = enBlinkOp; + else if((LCDC_Blik4COMS2C3 == enBlinkDot)||(LCDC_Blik8COMS1C3 == enBlinkDot)) //blink 4COM SEG2-SOM3 or 8COM SEG1-COM3 + FM_LCDC->LCDC_BLINK_f.BLD11 = enBlinkOp; + else if((LCDC_Blik4COMS2C2 == enBlinkDot)||(LCDC_Blik8COMS1C2 == enBlinkDot)) //blink 4COM SEG2-SOM2 or 8COM SEG1-COM2 + FM_LCDC->LCDC_BLINK_f.BLD10 = enBlinkOp; + else if((LCDC_Blik4COMS2C1 == enBlinkDot)||(LCDC_Blik8COMS1C1 == enBlinkDot)) //blink 4COM SEG2-SOM1 or 8COM SEG1-COM1 + FM_LCDC->LCDC_BLINK_f.BLD09 = enBlinkOp; + else if((LCDC_Blik4COMS2C0 == enBlinkDot)||(LCDC_Blik8COMS1C0 == enBlinkDot)) //blink 4COM SEG2-SOM0 or 8COM SEG1-COM0 + FM_LCDC->LCDC_BLINK_f.BLD08 = enBlinkOp; + else if((LCDC_Blik4COMS1C3 == enBlinkDot)||(LCDC_Blik8COMS0C7 == enBlinkDot)) //blink 4COM SEG1-SOM3 or 8COM SEG0-COM7 + FM_LCDC->LCDC_BLINK_f.BLD07 = enBlinkOp; + else if((LCDC_Blik4COMS1C2 == enBlinkDot)||(LCDC_Blik8COMS0C6 == enBlinkDot)) //blink 4COM SEG1-SOM2 or 8COM SEG0-COM6 + FM_LCDC->LCDC_BLINK_f.BLD06 = enBlinkOp; + else if((LCDC_Blik4COMS1C1 == enBlinkDot)||(LCDC_Blik8COMS0C5 == enBlinkDot)) //blink 4COM SEG1-SOM1 or 8COM SEG0-COM5 + FM_LCDC->LCDC_BLINK_f.BLD05 = enBlinkOp; + else if((LCDC_Blik4COMS1C0 == enBlinkDot)||(LCDC_Blik8COMS0C4 == enBlinkDot)) //blink 4COM SEG1-SOM0 or 8COM SEG0-COM4 + FM_LCDC->LCDC_BLINK_f.BLD04 = enBlinkOp; + else if((LCDC_Blik4COMS0C3 == enBlinkDot)||(LCDC_Blik8COMS0C3 == enBlinkDot)) //blink 4COM SEG0-SOM3 or 8COM SEG0-COM3 + FM_LCDC->LCDC_BLINK_f.BLD03 = enBlinkOp; + else if((LCDC_Blik4COMS0C2 == enBlinkDot)||(LCDC_Blik8COMS0C2 == enBlinkDot)) //blink 4COM SEG0-SOM2 or 8COM SEG0-COM2 + FM_LCDC->LCDC_BLINK_f.BLD02 = enBlinkOp; + else if((LCDC_Blik4COMS0C1 == enBlinkDot)||(LCDC_Blik8COMS0C1 == enBlinkDot)) //blink 4COM SEG0-SOM1 or 8COM SEG0-COM1 + FM_LCDC->LCDC_BLINK_f.BLD01 = enBlinkOp; + else if((LCDC_Blik4COMS0C0 == enBlinkDot)||(LCDC_Blik8COMS0C0 == enBlinkDot)) //blink 4COM SEG0-SOM0 or 8COM SEG0-COM0 + FM_LCDC->LCDC_BLINK_f.BLD00 = enBlinkOp; + else + return ErrorInvalidParameter; + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) + +/** + ****************************************************************************** + ** \brief Enable lcd interrupt + ******************************************************************************/ +void Lcd_EnableIrq(void) +{ + FM_LCDC->LCDCC2_f.LCDIEN = 1u; + + return; +} + +/** + ****************************************************************************** + ** \brief Disable lcd interrupt + ******************************************************************************/ +void Lcd_DisableIrq(void) +{ + FM_LCDC->LCDCC2_f.LCDIEN = 0u; + + return; +} +#endif + +/** + ****************************************************************************** + ** \brief Clear lcd interrupt flag + ******************************************************************************/ +void Lcd_ClrIrqFlag(void) +{ + FM_LCDC->LCDCC2_f.LCDIF = 0u; +} + +/** + ****************************************************************************** + ** \brief Get lcd interrupt flag + ** + ** \retval TRUE LCD interrupt flag is set + ** \retval FALSE LCD interrupt flag is clear + ** + ******************************************************************************/ +boolean_t Lcd_GetIrqFlag(void) +{ + return FM_LCDC->LCDCC2_f.LCDIF; +} + +#endif /* #if (defined(PDL_PERIPHERAL_LCD_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lcd/lcd.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lcd/lcd.h new file mode 100644 index 0000000000..3aa7b84e21 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lcd/lcd.h @@ -0,0 +1,492 @@ +/******************************************************************************* +* \file lcd.h +* +* \version 1.20 +* +* \brief Headerfile for LCD functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __LCD_H__ +#define __LCD_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_LCD_ACTIVE)) + +#if defined (__CC_ARM) + #pragma anon_unions +#endif + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupLCD Segment LCD Controller (LCD) +* \{ +* \defgroup GroupLCD_Macros Macros +* \defgroup GroupLCD_Functions Functions +* \defgroup GroupLCD_DataStructures Data Structures +* \defgroup GroupLCD_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupLCD +* \{ +* The Segment LCD Controller (LCD) displays the contents of Display Data Memory (LCDRAM) +* directly to the Liquid Crystal Display (LCD) panel by using segment outputs and common outputs. +* You can operate with either four or eight common outputs.
+* * 4-COM: 44 segments (SEG00-SEG43); outputs COM0-COM3; bias 1/2, 1/3, or 1/4; LCDRAM 22 bytes (44x4 bits) +* * 8-COM: 40 segments (SEG00-SEG39); outputs COM0-COM7; bias 1/3 or 1/4; LCDRAM 40 bytes (40x8 bits) +* You can choose either 10kOhm or 100kOhm divider resistors for generating LCD drive power. LCD drive +* power can be supplied from an external circuit.
+* You choose either a sub-clock or PCLK to drive the LCD controller operating clock (LCDC clock). +* The LCD supports blinking (flashing), direct drive to the LCD panel, a voltage booster, and can +* generate an interrupt request per frame. +* +* \note The LCD controller for FM0+ type 1 and type 2 differs. Refer to peripheral +* manuals for details. FM4 does not provide the LCD peripheral. +* +* \section SectionLCD_ConfigurationConsideration Configuration Consideration +* To set up an LCD, you provide configuration parameters in the stc_lcd_config_t structure. Among +* these is a clock configuration structure, stc_lcd_clk_config_t, where you specify the source clock +* and clock divider. You also specify which segments to select in the fields stcSegSel1 (SEG00-SEG31) +* and stcSegSel2 (SEG32-SEG39). A one in each bit turns on the corresponding segment. Similarly, the +* stcComSel (COM0-COM7) is a structure that represents an 8-bit value to select the common outputs. +* You also enable the LCD interrupt and provide a callback function.
+* Then call LCD_Init() to initialize the LCD instance according to the configuration structure.
+* Clearing the LCDRAM at this point is good practice. Call Lcd_ClrWholeRam().
+* At runtime you can use API function calls to:
+* * Change the input mode +* * Set the display mode +* * Enable or disable a blank display (when disabled, you display LCDRAM contents) +* * Write the contents of LCDRAM using a single bit, bits, or a byte +* * Enable and disable the LCD interrupt +* * Get or clear the interrupt flag
+* See the LCD function documentation for information on each API call. +* +* \section SectionLCD_MoreInfo More Information +* For more information on the LCD peripheral, refer to:
+* FM0+ Peripheral Manual - Analog Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupLCD_Types +* \{ +*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Select divider resitors to create LCD drive power + ******************************************************************************/ +typedef enum en_lcd_div_mode +{ + LcdcExtRes = 0u, ///< External divider resistors are used to create LCD drive power. + LcdcIntRes = 1u, ///< Internal divider resistors are used to create LCD drive power. +}en_lcd_div_mode_t; + +/** + ****************************************************************************** + ** \brief Divider resistor value selection + ******************************************************************************/ +typedef enum en_lcd_disp_mode +{ + LcdStop = 0u, ///< LCD controller stops display operations. + Lcd_4Com_1Div2Duty = 1u, ///< 4 COM mode, 1/2 duty + Lcd_4Com_1Div3Duty = 2u, ///< 4 COM mode, 1/3 duty + Lcd_4Com_1Div4Duty = 3u, ///< 4 COM mode, 1/4 duty + Lcd_8Com_1Div8Duty = 4u, ///< 8 COM mode, 1/8 duty +}en_lcd_disp_mode_t; + +/** + ****************************************************************************** + ** \brief Divider resistor value selection + ******************************************************************************/ +typedef enum en_lcd_div_res_val +{ + LcdDivRes100K = 0u, ///< 100 k�� resistors are selected. + LcdDivRes10K = 1u, ///< 100 k�� resistors are selected. +}en_lcd_div_res_val_t; + +/** + ****************************************************************************** + ** \brief 8 COM mode bias selection + ******************************************************************************/ +typedef enum en_lcd_8com_bias +{ + Lcd1Div3Bias = 0u, ///< 1/3 bias is selected in 8 COM mode. + Lcd1Div4Bias = 1u, ///< 1/4 bias is selected in 8 COM mode. +}en_lcd_8com_bias_t; + +/** + ****************************************************************************** + ** \brief Source clock selection + ******************************************************************************/ +typedef enum en_lcd_src_clk_sel +{ + LcdClkSelSubClk = 0u, ///< Sub-clock is selected for LCDC source clock. + LcdClkSelPclk = 1u, ///< PCLK is selected for LCDC source clock. +}en_lcd_src_clk_sel_t; +/** + ****************************************************************************** + ** \brief controls I/O ports shared by COM and SEG. + ******************************************************************************/ +typedef enum en_lcd_input_io_mode +{ + LcdInputIoCutoff = 0u, ///< Input from I/O port is cut off. + LcdInputIoConnect = 1u, ///< Input from I/O port is not cut off. + +}en_lcd_input_io_mode_t; + +/** + ****************************************************************************** + ** \brief Blink interval + ******************************************************************************/ +typedef enum en_lcd_blink_interval +{ + LcdBlinkIntHalfSecond = 0u, ///< If sub-clock is 32.768 [kHz], the interval becomes 0.5 [s]. + LcdBlinkIntOneSecond = 1u, ///< If sub-clock is 32.768 [kHz], the interval becomes 1.0 [s]. + +}en_lcd_blink_interval_t; + +/** + ****************************************************************************** + ** \brief Blink interval + ******************************************************************************/ +typedef enum en_lcd_ram_bit_operation +{ + LcdBitClr = 0u, ///< Clear lcd ram bit. + LcdBitSet = 1u, ///< Set lcd ram bit. + +}en_lcd_ram_bit_operation_t; + +/** + ****************************************************************************** + ** \brief LCD blink function enumeration + ******************************************************************************/ +typedef enum en_lcd_blink_operation +{ + LcdBlinkOff = 0u, ///< LCD blink on + LcdBlinkOn = 1u, ///< LCD blink off +}en_lcd_blink_operation_t; + +/** + ****************************************************************************** + ** \brief LCD blink SEG COM dot enumeration + ******************************************************************************/ +typedef enum en_lcd_blink_dot_t +{ + LCDC_BlinkDotOff = 0u, ///< LCD blink on +/***4COM*****************/ + LCDC_Blik4COMS3C3, ///< lcdc blink for SEG3-COM3 + LCDC_Blik4COMS3C2, ///< lcdc blink for SEG3-COM2 + LCDC_Blik4COMS3C1, ///< lcdc blink for SEG3-COM1 + LCDC_Blik4COMS3C0, ///< lcdc blink for SEG3-COM0 + LCDC_Blik4COMS2C3, ///< lcdc blink for SEG2-COM3 + LCDC_Blik4COMS2C2, ///< lcdc blink for SEG2-COM2 + LCDC_Blik4COMS2C1, ///< lcdc blink for SEG2-COM1 + LCDC_Blik4COMS2C0, ///< lcdc blink for SEG2-COM0 + LCDC_Blik4COMS1C3, ///< lcdc blink for SEG1-COM3 + LCDC_Blik4COMS1C2, ///< lcdc blink for SEG1-COM2 + LCDC_Blik4COMS1C1, ///< lcdc blink for SEG1-COM1 + LCDC_Blik4COMS1C0, ///< lcdc blink for SEG1-COM0 + LCDC_Blik4COMS0C3, ///< lcdc blink for SEG0-COM3 + LCDC_Blik4COMS0C2, ///< lcdc blink for SEG0-COM2 + LCDC_Blik4COMS0C1, ///< lcdc blink for SEG0-COM1 + LCDC_Blik4COMS0C0, ///< lcdc blink for SEG0-COM0 +/***8COM*****************/ + LCDC_Blik8COMS1C7, ///< lcdc blink for SEG1-COM7 + LCDC_Blik8COMS1C6, ///< lcdc blink for SEG1-COM6 + LCDC_Blik8COMS1C5, ///< lcdc blink for SEG1-COM5 + LCDC_Blik8COMS1C4, ///< lcdc blink for SEG1-COM4 + LCDC_Blik8COMS1C3, ///< lcdc blink for SEG1-COM3 + LCDC_Blik8COMS1C2, ///< lcdc blink for SEG1-COM2 + LCDC_Blik8COMS1C1, ///< lcdc blink for SEG1-COM1 + LCDC_Blik8COMS1C0, ///< lcdc blink for SEG1-COM0 + LCDC_Blik8COMS0C7, ///< lcdc blink for SEG0-COM7 + LCDC_Blik8COMS0C6, ///< lcdc blink for SEG0-COM6 + LCDC_Blik8COMS0C5, ///< lcdc blink for SEG0-COM5 + LCDC_Blik8COMS0C4, ///< lcdc blink for SEG0-COM4 + LCDC_Blik8COMS0C3, ///< lcdc blink for SEG0-COM3 + LCDC_Blik8COMS0C2, ///< lcdc blink for SEG0-COM2 + LCDC_Blik8COMS0C1, ///< lcdc blink for SEG0-COM1 + LCDC_Blik8COMS0C0, ///< lcdc blink for SEG0-COM0 +}en_lcd_blink_dot_t; + +/** \} GroupLCD_Types */ + +/** +* \addtogroup GroupLCD_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Select lcd source clock and configure clock division ratio + ******************************************************************************/ +typedef struct stc_lcd_clk_config +{ + en_lcd_src_clk_sel_t enSrcClk; ///< Set LCDC source clock. + uint32_t u32DivVal; ///< These bits set LCDC clock division ratio (1 to 2097153). +}stc_lcd_clk_config_t; + +/** + ****************************************************************************** + ** \brief VVx selection bit + ** + ** \note As VV4 pin cannot be used as GPIO when LCD controller is + ** selected (LCDCC1:VSEL="1"), be sure to write "1" to VE4 bit. + ******************************************************************************/ +typedef struct stc_lcd_vv_sel +{ + union /* unVvSel */ + { + uint8_t u8Vv; + struct /* stcVvBits */ + { + uint8_t VE0 : 1 ; + uint8_t VE1 : 1 ; + uint8_t VE2 : 1 ; + uint8_t VE3 : 1 ; + uint8_t VE4 : 1 ; + uint8_t RESERVED0 : 3; + }; + }; +} stc_lcd_vv_sel_t ; + +/** + ****************************************************************************** + ** \brief These bits control I/O port status and analog switches for SEG outputs. + ******************************************************************************/ +typedef struct stc_lcd_seg_sel1 +{ + union /* unSegSel1 */ + { + uint32_t u32SegSel1; + struct /* stcSegSel1Bits */ + { + uint32_t SEG00 : 1 ; + uint32_t SEG01 : 1 ; + uint32_t SEG02 : 1 ; + uint32_t SEG03 : 1 ; + uint32_t SEG04 : 1 ; + uint32_t SEG05 : 1 ; + uint32_t SEG06 : 1 ; + uint32_t SEG07 : 1 ; + uint32_t SEG08 : 1 ; + uint32_t SEG09 : 1 ; + uint32_t SEG10 : 1 ; + uint32_t SEG11 : 1 ; + uint32_t SEG12 : 1 ; + uint32_t SEG13 : 1 ; + uint32_t SEG14 : 1 ; + uint32_t SEG15 : 1 ; + uint32_t SEG16 : 1 ; + uint32_t SEG17 : 1 ; + uint32_t SEG18 : 1 ; + uint32_t SEG19 : 1 ; + uint32_t SEG20 : 1 ; + uint32_t SEG21 : 1 ; + uint32_t SEG22 : 1 ; + uint32_t SEG23 : 1 ; + uint32_t SEG24 : 1 ; + uint32_t SEG25 : 1 ; + uint32_t SEG26 : 1 ; + uint32_t SEG27 : 1 ; + uint32_t SEG28 : 1 ; + uint32_t SEG29 : 1 ; + uint32_t SEG30 : 1 ; + uint32_t SEG31 : 1 ; + }; + }; +} stc_lcd_seg_sel1_t ; + +/** + ****************************************************************************** + ** \brief These bits control I/O port status and analog switches for SEG outputs. + ******************************************************************************/ +typedef struct stc_lcd_seg_sel2 +{ + union /* unSegSel2 */ + { + uint32_t u32SegSel2; + struct /* stcSegSel2Bits */ + { + uint32_t SEG32 : 1 ; + uint32_t SEG33 : 1 ; + uint32_t SEG34 : 1 ; + uint32_t SEG35 : 1 ; + uint32_t SEG36 : 1 ; + uint32_t SEG37 : 1 ; + uint32_t SEG38 : 1 ; + uint32_t SEG39 : 1 ; + uint32_t RESERVED0 : 24; + }; + }; +} stc_lcd_seg_sel2_t ; + +/** + ****************************************************************************** + ** \brief These bits control I/O port status and analog switches for COM outputs. + ******************************************************************************/ +typedef struct stc_lcd_com_sel +{ + union /* unComSel */ + { + uint8_t u8ComSel; + struct /* stcComSelBits */ + { + uint32_t COM0 : 1 ; + uint32_t COM1 : 1 ; + uint32_t COM2 : 1 ; + uint32_t COM3 : 1 ; + uint32_t COM4 : 1 ; + uint32_t COM5 : 1 ; + uint32_t COM6 : 1 ; + uint32_t COM7 : 1 ; + }; + }; +} stc_lcd_com_sel_t; + +/** + ****************************************************************************** + ** \brief LCD booster function + ******************************************************************************/ +typedef struct stc_lcd_booster +{ + union /* unBooster */ + { + uint16_t u16Booster; + struct /* stcBoosterBits */ + { + uint16_t BSTOPT : 1;///< booster function could be available + uint16_t BSTPD : 1;///< Control booster power + uint16_t RESERVED0 : 1; + uint16_t CENSEL : 1;///< Control booster C1/C0 pin funciton + uint16_t RESERVED1 : 4; + uint16_t BTRF : 4;///< Booster fine setting bits for reference voltage of VV1 + uint16_t BTRC : 2;///< Booster coarse setting bits for reference voltage of VV1 + }; + }; +}stc_lcd_booster_t; + +/** + ****************************************************************************** + ** \brief Clock Supervisor configuration + ** + ** The Clock Supervisor configuration settings + ******************************************************************************/ +typedef struct stc_lcd_config +{ + boolean_t bTimerMod; ///< FALSE: sops running in timer mode. TRUE:run in timer mode. + en_lcd_div_mode_t enDivMode; ///< LCD drive power control, see #en_lcd_div_mode_t for details + en_lcd_disp_mode_t enDispMode; ///< LCD controller display mode selection, see #en_lcd_disp_mode_t for details + en_lcd_div_res_val_t enDivResVal; ///< Divider resistor value selection, see #en_lcd_div_res_val_t for details + en_lcd_8com_bias_t en8ComBias; ///< 8 COM mode bias selection, see #en_lcd_8com_bias_t for details + boolean_t bEnDispRevs; ///< Reverse display control. FALSE:Display is not reversed. TRUE:Display is reversed. + boolean_t bEnBlankDisp; ///< TRUE:Blank is displayed independent of data stored in LCDRAM + en_lcd_input_io_mode_t enInputIoMode; ///< I/O port input control, see #en_lcd_input_io_mode_t for details + stc_lcd_clk_config_t stcClkConf; ///< LCD clock control, see #stc_lcd_clk_config_t for details + stc_lcd_vv_sel_t stcVvSel; ///< VVx control, see #stc_lcd_vv_sel_t for details + stc_lcd_seg_sel1_t stcSegSel1; ///< Segment output pins (SEG00 to SEG31) control, see #stc_lcd_seg_sel1_t for details + stc_lcd_seg_sel2_t stcSegSel2; ///< Segment output pins (SEG32 to SEG39) control, see #stc_lcd_seg_sel2_t for details + stc_lcd_com_sel_t stcComSel; ///< COM output pins (COM0 to COM7) control, see #stc_lcd_com_sel_t for details +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bEnBooster; ///< Enable booster function + stc_lcd_booster_t stcBooster; ///< Configure LCD booster functionl, see #stc_lcd_booster_t for details +#endif + +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) + boolean_t bIrqEn; ///< Enable LCD interrupt + func_ptr_t pfnIrqCb; ///< Pointer to LCD interrupt callback function + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +} stc_lcd_config_t; + +/** \} GroupLCD_DataStructures */ + +/** +* \addtogroup GroupLCD_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) + void Lcd_IrqHandler(void); +#endif + en_result_t Lcd_Init(const stc_lcd_config_t* pstcConfig); + void Lcd_DeInit( void); + en_result_t Lcd_ConfInputIoMode(en_lcd_input_io_mode_t enInputIoMode); + void Lcd_SetDispMode(en_lcd_disp_mode_t enDispMode); + void Lcd_EnableBlankDisp(void); + void Lcd_DisableBlankDisp(void); + en_result_t Lcd_WriteRAMBits(uint8_t u8RAMIndex, uint8_t u8Bitsmap, + boolean_t bBit); + en_result_t Lcd_WriteRAMBit(uint8_t u8RAMIndex, uint8_t u8BitIndex, + boolean_t bBit); + en_result_t Lcd_WriteRAMByte(uint8_t u8RAMIndex, uint8_t u8DataByte); + en_result_t Lcd_ReadRAMByte(uint8_t u8RAMIndex,uint8_t *pu8DataByte); + void Lcd_FillWholeRam(void); + void Lcd_ClrWholeRam(void); + en_result_t Lcd_SetBinkInterval(en_lcd_blink_interval_t enBlinkInterval); + en_result_t Lcd_SetBlinkDot(en_lcd_blink_dot_t enBlinkDot, + en_lcd_blink_operation_t enBlinkOp); + + /* Interrupt Setting */ +#if (PDL_INTERRUPT_ENABLE_LCD == PDL_ON) + void Lcd_EnableIrq(void); + void Lcd_DisableIrq(void); +#endif + void Lcd_ClrIrqFlag(void); + boolean_t Lcd_GetIrqFlag(void); + +/** \} GroupLCD_Functions */ +/** \} GroupLCD */ + +#ifdef __cplusplus +} +#endif + + +#endif /* #if (defined(PDL_PERIPHERAL_LCD_ACTIVE)) */ + +#endif /* __LCD_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lpm/lpm.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lpm/lpm.c new file mode 100644 index 0000000000..8e5d681157 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lpm/lpm.c @@ -0,0 +1,871 @@ +/******************************************************************************* +* \file lpm.c +* +* \version 1.30 +* +* \brief This file provides the source code to the API for the LPM +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lpm/lpm.h" + +#if (defined(PDL_PERIPHERAL_LPM_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +// SCR address +#define CM_CORE_CSR *((volatile unsigned int*)(0xE000ED10UL)) + +// Backup registers base address +#define LPCM_BACKUP_REG_BASE ((volatile uint8_t*)0x40035900) + +/*---------------------------------------------------------------------------*/ +/* local datatypes */ +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* local data */ +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* global data */ +/*---------------------------------------------------------------------------*/ + +/*---------------------------------------------------------------------------*/ +/* global functions */ +/*---------------------------------------------------------------------------*/ + +/** + ****************************************************************************** + ** \brief Read Backup Registers + ** + ** \param [out] stcBackUpReg double pointer to user backup register + ** structure + ** + ** \retval Ok Successfully read + ******************************************************************************/ +static en_result_t ReadBackupRegisters(stc_backupreg_t* stcBackUpReg) +{ + uint8_t u8Counter; + +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) + // Read Command to VBAT domain + FM_RTC->WTCR20_f.BREAD = 1u; + + // Poll for read completed + while(1 == FM_RTC->WTCR20_f.BREAD) + {} +#endif + + for(u8Counter = 0u; u8Counter < PDL_BACK_UP_REGISTERS; u8Counter += 4u) + { +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) + *(uint32_t*)((uint32_t)(&stcBackUpReg->u8BREG00) + (uint32_t)u8Counter) + = *(uint32_t*)((uint32_t)(&FM_RTC->BREG00_03) + u8Counter); +#else + *(uint32_t*)((uint32_t)(&stcBackUpReg->u8BREG00) + (uint32_t)u8Counter) + = *(uint32_t*)((uint32_t)(&FM_DS->BUR01) + u8Counter); +#endif + } + + return Ok; +} // ReadBackupRegisters + +/** + ****************************************************************************** + ** \brief Write Backup Registers + ** + ** \param [out] stcBackUpReg structure of backup registers + ** + ** \retval Ok Successfully written + ******************************************************************************/ +static en_result_t WriteBackupRegisters(stc_backupreg_t* stcBackUpReg) +{ + uint8_t u8Counter; + + for(u8Counter = 0u; u8Counter < PDL_BACK_UP_REGISTERS; u8Counter += 4u) + { +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) + *(uint32_t*)((uint32_t)(&FM_RTC->BREG00_03) + u8Counter) + = *(uint32_t*)((uint32_t)(&stcBackUpReg->u8BREG00) + u8Counter); +#else + *(uint32_t*)((uint32_t)(&FM_DS->BUR01) + u8Counter) + = *(uint32_t*)((uint32_t)(&stcBackUpReg->u8BREG00) + u8Counter); +#endif + } + +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) + // Write Command to VBAT domain + FM_RTC->WTCR20_f.BWRITE = 1u; + + // Poll for read completed + while(1 == FM_RTC->WTCR20_f.BWRITE) + {} +#endif + + return Ok; +} // WriteBackupRegisters + + +/** + ****************************************************************************** + ** \brief WRFSR dummy read + ******************************************************************************/ +static uint16_t WRFSRDummyRead(void) +{ + uint16_t Dummy; + Dummy = FM_DS->WRFSR; + return Dummy; +} + +/** + ****************************************************************************** + ** \brief WRFSR dummy read + ******************************************************************************/ +static uint16_t WIFSRDummyRead(void) +{ + uint16_t Dummy; + Dummy = FM_DS->WIFSR; + return Dummy; +} + + +/** + ****************************************************************************** + ** \brief go to standby mode + ** + ** \param enMode the type of standby mode. + ** This parameter can be one of the following values: + ** \arg StbSleepMode Sleep mode + ** \arg StbTimerMode Timer mode + ** \arg StbStopMode Stop mode + ** \arg StbRtcMode RTC mode + ** \arg DeepStbRtcMode deep standby RTC mode + ** \arg DeepStbStopMode deep standby stop mode + + ** \param bIoRemain Set io status when enter standby mode. + ** This parameter can be one of the following values: + ** \arg FALSE Set IO to Hi-z + ** \arg TRUE Remain IO status + ******************************************************************************/ +void Lpm_GoToStandByMode(en_lpm_mode_t enMode, boolean_t bIoRemain) +{ + WRFSRDummyRead(); + WIFSRDummyRead(); + switch (enMode) + { + case StbSleepMode: + CM_CORE_CSR &= 0xFFFFFFFFBu; + __WFI(); + break; + case StbTimerMode: + if( bIoRemain == 1u ) + { + FM_CRG->STB_CTL = 0x1ACC0000u; // Retains status of each pin + } + else + { + FM_CRG->STB_CTL = 0x1ACC0010u; // Sets the status of each pin to high impedance + } + CM_CORE_CSR |= 0x00000004u; + __WFI(); + break; + case StbStopMode: + FM_DS->PMD_CTL &= ~0x01u; /* RTCE=0 */ + if( bIoRemain == 1u ) + { + FM_CRG->STB_CTL = 0x1ACC0002u; // Retains status of each pin + } + else + { + FM_CRG->STB_CTL = 0x1ACC0012u; // Sets the status of each pin to high impedance + } + CM_CORE_CSR |= 0x00000004u; + __WFI(); + break; + case StbRtcMode: + FM_DS->PMD_CTL |= 0x01u; /* RTCE=1 */ + if( bIoRemain == 1u ) + { + FM_CRG->STB_CTL = 0x1ACC0002u; // Retains status of each pin + } + else + { + FM_CRG->STB_CTL = 0x1ACC0012u; // Sets the status of each pin to high impedance + } + CM_CORE_CSR |= 0x00000004u; + __WFI(); + break; + case DeepStbRtcMode: + FM_DS->PMD_CTL |= 0x01u; /* RTCE=1 */ + if( bIoRemain == 1u ) + { + FM_CRG->STB_CTL = 0x1ACC0006u; // Retains status of each pin + } + else + { + FM_CRG->STB_CTL = 0x1ACC0016u; // Sets the status of each pin to high impedance + } + CM_CORE_CSR |= 0x00000004u; + __WFI(); + break; + case DeepStbStopMode: + FM_DS->PMD_CTL &= ~0x01u; /* RTCE=0 */ + if( bIoRemain == 1u ) + { + FM_CRG->STB_CTL = 0x1ACC0006u; // Retains status of each pin + } + else + { + FM_CRG->STB_CTL = 0x1ACC0016u; // Sets the status of each pin to high impedance + } + CM_CORE_CSR |= 0x00000004u; + __WFI(); + break; + default: + break; + } +} + +/** + ****************************************************************************** + ** \brief Configure return cause from deep standby mode + ** + ** \param pstcCause Pointer to structure of return cause types + ** + ** \retval Ok Deep standby mode is configured normally + ** + ** \note Wakeup from WKUP0 pin is always enabled + ** + ******************************************************************************/ +en_result_t Lpm_ConfigDeepStbRetCause(stc_dstb_ret_cause_t* pstcCause) +{ + if(NULL == pstcCause) + { + return ErrorInvalidParameter; + } + + bFM_DS_WIER_WRTCE = ((pstcCause->bRtcEn == TRUE) ? 1u : 0u); + bFM_DS_WIER_WLVDE = ((pstcCause->bLvdEn == TRUE)? 1u : 0u); + bFM_DS_WIER_WUI1E = ((pstcCause->bWakeup1En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI2E = ((pstcCause->bWakeup2En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI3E = ((pstcCause->bWakeup3En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI4E = ((pstcCause->bWakeup4En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI5E = ((pstcCause->bWakeup5En == TRUE) ? 1u : 0u); +#if (defined(FM_HDMICEC_AVAILABLE)) + bFM_DS_WIER_WCEC0E = ((pstcCause->bCec0En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WCEC1E = ((pstcCause->bCec1En == TRUE) ? 1u : 0u); +#endif +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + bFM_DS_WIER_WUI6E = ((pstcCause->bWakeup6En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI7E = ((pstcCause->bWakeup7En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI8E = ((pstcCause->bWakeup8En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI9E = ((pstcCause->bWakeup9En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI10E = ((pstcCause->bWakeup10En == TRUE) ? 1u : 0u); + bFM_DS_WIER_WUI11E = ((pstcCause->bWakeup11En == TRUE) ? 1u : 0u); +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read deep standby mode return cause flag + ** + ** \retval DeepStbNoFlag No flag set + ** \retval DeepStbInitx Wakeup from deep standby mode by INITX reset + ** \retval DeepStbLvdReset Wakeup from deep standby mode by LVD reset + ** \retval DeepStbRtcInt Wakeup from deep standby mode by RTC interrupt + ** \retval DeepStbLvdInt Wakeup from deep standby mode by LVD interrupt + ** \retval DeepStbWkupPin0 Wakeup from deep standby mode by WKUP0 + ** \retval DeepStbWkupPin1 Wakeup from deep standby mode by WKUP1 + ** \retval DeepStbWkupPin2 Wakeup from deep standby mode by WKUP2 + ** \retval DeepStbWkupPin3 Wakeup from deep standby mode by WKUP3 + ** \retval DeepStbWkupPin4 Wakeup from deep standby mode by WKUP4 + ** \retval DeepStbWkupPin5 Wakeup from deep standby mode by WKUP5 + ** \retval DeepStbCec0 Wakeup from deep standby mode by CEC0 interrupt + ** \retval DeepStbCec1 Wakeup from deep standby mode by CEC1 interrupt + ** \retval DeepStbWkupPin6 Wakeup from deep standby mode by WKUP6 + ** \retval DeepStbWkupPin7 Wakeup from deep standby mode by WKUP7 + ** \retval DeepStbWkupPin8 Wakeup from deep standby mode by WKUP8 + ** \retval DeepStbWkupPin9 Wakeup from deep standby mode by WKUP9 + ** \retval DeepStbWkupPin10 Wakeup from deep standby mode by WKUP10 + ** \retval DeepStbWkupPin11 Wakeup from deep standby mode by WKUP11 + ******************************************************************************/ +en_dstb_ret_cause_t Lpm_ReadDeepStbRetCause(void) +{ + uint16_t rWIFSR,rWRFSR; + rWRFSR = FM_DS->WRFSR; + rWIFSR = FM_DS->WIFSR; + + if(rWRFSR & WRFSR_WINITX) + { + return DeepStbInitx; + } + + if(rWRFSR & WIFSR_WLVDI) + { + return DeepStbLvdReset; + } + + if(rWIFSR & WIFSR_WRTCI) + { + return DeepStbRtcInt; + } + else if(rWIFSR & WIFSR_WLVDI) + { + return DeepStbLvdInt; + } + else if(rWIFSR & WIFSR_WUI0) + { + return DeepStbWkupPin0; + } + else if(rWIFSR & WIFSR_WUI1) + { + return DeepStbWkupPin1; + } + else if(rWIFSR & WIFSR_WUI2) + { + return DeepStbWkupPin2; + } + else if(rWIFSR & WIFSR_WUI3) + { + return DeepStbWkupPin3; + } + else if(rWIFSR & WIFSR_WUI4) + { + return DeepStbWkupPin4; + } + else if(rWIFSR & WIFSR_WUI5) + { + return DeepStbWkupPin5; + } + else if(rWIFSR & WIFSR_WCEC0I) + { + return DeepStbCec0; + } + else if(rWIFSR & WIFSR_WCEC1I) + { + return DeepStbCec1; + } +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + else if(rWIFSR & WIFSR_WUI6) + { + return DeepStbWkupPin6; + } + else if(rWIFSR & WIFSR_WUI7) + { + return DeepStbWkupPin7; + } + else if(rWIFSR & WIFSR_WUI8) + { + return DeepStbWkupPin8; + } + else if(rWIFSR & WIFSR_WUI9) + { + return DeepStbWkupPin9; + } + else if(rWIFSR & WIFSR_WUI10) + { + return DeepStbWkupPin10; + } + else if(rWIFSR & WIFSR_WUI11) + { + return DeepStbWkupPin11; + } +#endif + + return DeepStbNoFlag; +} + +/** + ****************************************************************************** + ** \brief Set the valid level of wkup pin + ** + ** \param enPinIndex Pin index + ** \arg WkupPin1 WKUP1 pin index + ** \arg WkupPin2 WKUP2 pin index + ** \arg WkupPin3 WKUP3 pin index + ** \arg WkupPin4 WKUP4 pin index + ** \arg WkupPin5 WKUP5 pin index + ** \arg WkupPin6 WKUP6 pin index + ** \arg WkupPin7 WKUP7 pin index + ** \arg WkupPin8 WKUP8 pin index + ** \arg WkupPin9 WKUP9 pin index + ** \arg WkupPin10 WKUP10 pin index + ** \arg WkupPin11 WKUP11 pin index + ** + ** \param enLevel Wakeup pin valid value + ** \arg WkupLowLevelValid Set low as active level for WKUPx + ** \arg WkupHighLevelValid Set high as active level for WKUPx + ** + ** \retval Ok The valid level of wkup pin is set normally + ** \retval ErrorInvalidParameter Invalid value of enPinIndex + ** + ******************************************************************************/ +en_result_t Lpm_SetWkupPinLevel(en_dstb_wkup_pin_t enPinIndex, en_wkup_valid_level_t enLevel) +{ + if(enPinIndex >= WkupPinMax) + { + return ErrorInvalidParameter; + } + + FM_DS->WILVR &= ~(1ul << enPinIndex); + FM_DS->WILVR |= ((uint8_t)enLevel << enPinIndex); + + return Ok; +} + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +/** + ****************************************************************************** + ** \brief Configure the internal voltage in deep standby mode + ** + ** \param enVoltage Internal voltage + ** \arg LpmInternalVoltage120 Internal voltage is 1.20v + ** \arg LpmInternalVoltage110 Internal voltage is 1.10v + ** \arg LpmInternalVoltage105 Internal voltage is 1.05v + ** + ** \retval Ok Internal volatge is set normally + ** \retval ErrorInvalidParameter Invalid value of enVoltage + ** + ** \note This setting is active during deep standby only. + ** + ******************************************************************************/ +en_result_t Lpm_ConfigInternalVoltage(en_lpm_internal_voltage_t enVoltage) +{ + switch (enVoltage) + { + case LpmInternalVoltage120: + FM_DS->REG_CTL2_f.TT_SEL = 0u; + break; + case LpmInternalVoltage105: + FM_DS->REG_CTL2_f.TT_SEL = 1u; + FM_DS->REG_CTL2_f.TT_SVD = 1u; + break; + case LpmInternalVoltage110: + FM_DS->REG_CTL2_f.TT_SEL = 1u; + FM_DS->REG_CTL2_f.TT_SVD = 2u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure main oscillator types in deep standby mode + ** + ** \param enMainOsc Main oscillator types + ** \arg LpmMainOsc4M Support 4MHz main osc + ** \arg LpmMainOsc4M8M Support 4MHz,8MHz main osc + ** \arg LpmMainOsc4M8M16M Support 4MHz,8MHz,16MHz main osc + ** \arg LpmMainOsc48M Support 48MHz main osc + ** + ** \retval Ok Main oscillator types is set normally + ** \retval ErrorInvalidParameter Invalid value of enMainOsc + ** + ** \note This setting is active during deep standby only. + ** + ******************************************************************************/ +en_result_t Lpm_SelMainOscTypes(en_lpm_main_osc_t enMainOsc) +{ + switch (enMainOsc) + { + case LpmMainOsc4M: + FM_DS->MOSC_CTL_f.IMAINSEL = 0u; + break; + case LpmMainOsc4M8M: + FM_DS->MOSC_CTL_f.IMAINSEL = 1u; + break; + case LpmMainOsc4M8M16M: + FM_DS->MOSC_CTL_f.IMAINSEL = 2u; + break; + case LpmMainOsc48M: + FM_DS->MOSC_CTL_f.IMAINSEL = 3u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure Flash power in deep standby mode + ** + ** \param bPowerOn Flash power on or not + ** \arg TRUE Flash power on + ** \arg FALSE Flash power off + ** + ** \retval Ok Main oscillator types is set normally + ** \retval ErrorInvalidParameter Invalid value of enMainOsc + ** + ** \note This setting is active during stop/RTC/Sub Timer mode + ** + ******************************************************************************/ +en_result_t Lpm_ConfigFlashPower(boolean_t bPowerOn) +{ + FM_DS->STBFLASHPDX_f.STBFLASHPDX = ((bPowerOn == TRUE) ? 1u : 0u); + + return Ok; +} +#endif + +/** + ****************************************************************************** + ** \brief Configue the sub clock supply + ** + ** \param bSupplyCec Whether to supply sub clock to CEC + ** \param bSupplyRtc Whether to supply sub clock to RTC + ** + ** \retval Ok The sub clock supply is configured normally + ** \retval ErrorInvalidMode The device does not support this function + ** + ** \note Not all FM product has this function, please check it in the + ** product manual. + ** + ******************************************************************************/ +en_result_t Lpm_ConfigSubClk(boolean_t bSupplyCec, boolean_t bSupplyRtc) +{ +#if defined(bFM_DS_RCK_CTL_CECCKE) + if(TRUE == bSupplyCec) + { + bFM_DS_RCK_CTL_CECCKE = 1u; + } + else + { + bFM_DS_RCK_CTL_CECCKE = 0u; + } + + if(TRUE == bSupplyRtc) + { + bFM_DS_RCK_CTL_RTCCKE = 1u; + } + else + { + bFM_DS_RCK_CTL_RTCCKE = 0u; + } + + return Ok; +#else + return ErrorInvalidMode; +#endif +} + +/** + ****************************************************************************** + ** \brief Configure deep standby mode RAM retention + ** + ** \param bRamRetain Whether to retain data in the RAM + ** + ** \retval Ok Deep standby mode RAM retention set + ** + ** \note Not all FM0+ product has this function, please check it in the + ** product manual. + ** + ******************************************************************************/ +en_result_t Lpm_ConfigDeepStbRAMRetention(boolean_t bRamRetain) +{ + if(FALSE == bRamRetain) + { + FM_DS->DSRAMR &= ~0x03u; + } + else + { + FM_DS->DSRAMR |= 0x03u; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write the backup register + ** + ** \param enRegIndex register index + ** \arg BackupReg1 Back up register 1 index + ** \arg BackupReg2 Back up register 2 index + ** \arg BackupReg3 Back up register 3 index + ** \arg BackupReg4 Back up register 4 index + ** \arg BackupReg5 Back up register 5 index + ** \arg BackupReg6 Back up register 6 index + ** \arg BackupReg7 Back up register 7 index + ** \arg BackupReg8 Back up register 8 index + ** \arg BackupReg9 Back up register 9 index + ** \arg BackupReg10 Back up register 10 index + ** \arg BackupReg11 Back up register 11 index + ** \arg BackupReg12 Back up register 12 index + ** \arg BackupReg13 Back up register 13 index + ** \arg BackupReg14 Back up register 14 index + ** \arg BackupReg15 Back up register 15 index + ** \arg BackupReg16 Back up register 16 index + ** \param u8Data the data written into backup register + ** + ** \retval Ok The backup register written normally + ** \retval ErrorInvalidParameter enRegIndex > BackupReg15 + ** + ******************************************************************************/ +en_result_t Lpm_WriteBackupReg(en_dstb_bakup_reg_t enRegIndex, uint8_t u8Data) +{ + if(enRegIndex > BackupReg15) + { + return ErrorInvalidParameter; + } + + *(uint8_t*)(LPCM_BACKUP_REG_BASE + (uint8_t)enRegIndex) = u8Data; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read the backup register + ** + ** \param enRegIndex Backup register index + ** \arg BackupReg1 Back up register 1 index + ** \arg BackupReg2 Back up register 2 index + ** \arg BackupReg3 Back up register 3 index + ** \arg BackupReg4 Back up register 4 index + ** \arg BackupReg5 Back up register 5 index + ** \arg BackupReg6 Back up register 6 index + ** \arg BackupReg7 Back up register 7 index + ** \arg BackupReg8 Back up register 8 index + ** \arg BackupReg9 Back up register 9 index + ** \arg BackupReg10 Back up register 10 index + ** \arg BackupReg11 Back up register 11 index + ** \arg BackupReg12 Back up register 12 index + ** \arg BackupReg13 Back up register 13 index + ** \arg BackupReg14 Back up register 14 index + ** \arg BackupReg15 Back up register 15 index + ** \arg BackupReg16 Back up register 16 index + ** + ** \return Backup register data + ** + ******************************************************************************/ +uint8_t Lpm_ReadBackupReg(en_dstb_bakup_reg_t enRegIndex) +{ + return *(uint8_t*)(LPCM_BACKUP_REG_BASE + (uint8_t)enRegIndex); +} + +/** + ****************************************************************************** + ** \brief Read Backup Register (Byte) + ** + ** \param [in] u8AddressOffset Byte address offset to Back-up register + ** \param [out] u8Data Pointer to Byte data to be read + ** + ** \retval Ok Successfully written + ** \retval ErrorInvalidParameter Address offset out of range + ******************************************************************************/ +en_result_t Lpm_Readu8DataBackupRegister(uint8_t u8AddressOffset, uint8_t* u8Data) +{ + stc_backupreg_t stcBackUpReg; + + if (u8AddressOffset >= PDL_BACK_UP_REGISTERS) + { + return ErrorInvalidParameter; + } + + ReadBackupRegisters(&stcBackUpReg); + + *u8Data = *(uint8_t*)((uint32_t)(&stcBackUpReg.u8BREG00) + (uint32_t)u8AddressOffset); + + return Ok; +} // Lpm_Readu8DataBackupRegister + +/** + ****************************************************************************** + ** \brief Write Backup Registers (Byte) + ** + ** \param [in] u8AddressOffset Byte address offset to Back-up register + ** \param [in] u8Data Byte data to be written + ** + ** \retval Ok Successfully written + ** \retval ErrorInvalidParameter Address offset out of range + ******************************************************************************/ +en_result_t Lpm_Writeu8DataBackupRegister(uint8_t u8AddressOffset, uint8_t u8Data) +{ + stc_backupreg_t stcBackUpReg; + + if (u8AddressOffset >= PDL_BACK_UP_REGISTERS) + { + return ErrorInvalidParameter; + } + + ReadBackupRegisters(&stcBackUpReg); + *(uint8_t*)((uint32_t)(&stcBackUpReg.u8BREG00) + (uint32_t)u8AddressOffset) = u8Data; + WriteBackupRegisters(&stcBackUpReg); + + return Ok; +} // Lpm_Writeu8DataBackupRegister + +/** + ****************************************************************************** + ** \brief Read Backup Register (16-Bit) + ** + ** \param [in] u8AddressOffset Byte address offset to Back-up register + ** \param [out] u16Data Pointer to 16-Bit data to be read + ** + ** \retval Ok Successfully written + ** \retval ErrorInvalidParameter Address offset out of range (highest priority) + ** \retval ErrorAddressAlignment Address not aligned to 16-bit + ******************************************************************************/ +en_result_t Lpm_Readu16DataBackupRegister (uint8_t u8AddressOffset, uint16_t* u16Data) +{ + stc_backupreg_t stcBackUpReg; + + if (u8AddressOffset >= PDL_BACK_UP_REGISTERS) + { + return ErrorInvalidParameter; + } + + if (0u != (u8AddressOffset % 2u)) + { + return ErrorAddressAlignment; + } + + ReadBackupRegisters(&stcBackUpReg); + + *u16Data = *(uint16_t*)((uint32_t)(&stcBackUpReg.u8BREG00) + (uint32_t)u8AddressOffset); + + return Ok; +} // Lpm_Readu16DataBackupRegister + +/** + ****************************************************************************** + ** \brief Write Backup Registers (16-Bit) + ** + ** \param [in] u8AddressOffset Byte address offset to Back-up register + ** \param [in] u16Data 16-Bit data to be written + ** + ** \retval Ok Successfully written + ** \retval ErrorInvalidParameter Address offset out of range (highest priority) + ** \retval ErrorAddressAlignment Address not aligned to 16-bit + ******************************************************************************/ +en_result_t Lpm_Writeu16DataBackupRegister(uint8_t u8AddressOffset, uint16_t u16Data) +{ + stc_backupreg_t stcBackUpReg; + + if (u8AddressOffset >= PDL_BACK_UP_REGISTERS) + { + return ErrorInvalidParameter; + } + + if (0u != (u8AddressOffset % 2u)) + { + return ErrorAddressAlignment; + } + + ReadBackupRegisters(&stcBackUpReg); + *(uint16_t*)((uint32_t)(&stcBackUpReg.u8BREG00) + (uint32_t)u8AddressOffset) = u16Data; + WriteBackupRegisters(&stcBackUpReg); + + return Ok; +} // Lpm_Writeu16DataBackupRegister + +/** + ****************************************************************************** + ** \brief Read Backup Register (32-Bit) + ** + ** \param [in] u8AddressOffset Byte address offset to Back-up register + ** \param [out] u32Data Pointer to 32-Bit data to be read + ** + ** \retval Ok Successfully written + ** \retval ErrorInvalidParameter Address offset out of range (highest priority) + ** \retval ErrorAddressAlignment Address not aligned to 32-bit + ******************************************************************************/ +en_result_t Lpm_Readu32DataBackupRegister (uint8_t u8AddressOffset, uint32_t* u32Data) +{ + stc_backupreg_t stcBackUpReg; + + if (u8AddressOffset >= PDL_BACK_UP_REGISTERS) + { + return ErrorInvalidParameter; + } + + if (0u != (u8AddressOffset % 4u)) + { + return ErrorAddressAlignment; + } + + ReadBackupRegisters(&stcBackUpReg); + + *u32Data = *(uint32_t*)((uint32_t)(&stcBackUpReg.u8BREG00) + (uint32_t)u8AddressOffset); + + return Ok; +} // Lpm_Readu32DataBackupRegister + +/** + ****************************************************************************** + ** \brief Write Backup Registers (32-Bit) + ** + ** \param [in] u8AddressOffset Byte address offset to Back-up register + ** \param [in] u32Data Pointer to 32-Bit data + ** + ** \retval Ok Successfully written + ** \retval ErrorInvalidParameter Address offset out of range (highest priority) + ** \retval ErrorAddressAlignment Address not aligned to 32-bit + ******************************************************************************/ +en_result_t Lpm_Writeu32DataBackupRegister(uint8_t u8AddressOffset, uint32_t u32Data) +{ + stc_backupreg_t stcBackUpReg; + + if (u8AddressOffset >= PDL_BACK_UP_REGISTERS) + { + return ErrorInvalidParameter; + } + + if (0u != (u8AddressOffset % 4)) + { + return ErrorAddressAlignment; + } + + ReadBackupRegisters(&stcBackUpReg); + *(uint32_t*)((uint32_t)(&stcBackUpReg.u8BREG00) + (uint32_t)u8AddressOffset) = u32Data; + WriteBackupRegisters(&stcBackUpReg); + + return Ok; +} // Lpm_Writeu32DataBackupRegister + +#endif // #if (defined(PDL_PERIPHERAL_LPM_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lpm/lpm.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lpm/lpm.h new file mode 100644 index 0000000000..0d9496830c --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lpm/lpm.h @@ -0,0 +1,383 @@ +/******************************************************************************* +* \file lpm.h +* +* \version 1.30 +* +* \brief Headerfile for LPM functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __LPM_H__ +#define __LPM_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_LPM_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupLPM Low Power consumption Mode (LPM) +* \{ +* \defgroup GroupLPM_Macros Macros +* \defgroup GroupLPM_Functions Functions +* \defgroup GroupLPM_DataStructures Data Structures +* \defgroup GroupLPM_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupLPM +* \{ +* The Low Power Consumption Mode (LPM) peripheral enables reduced power consumption.
+* To reduce the power consumption, the system provides several low power consumption modes. LPM supports:
+* * Standby sleep +* * Standby timer +* * Standby RTC +* * Standby stop +* * Deep standby RTC +* * Deep standby stop
+* The LPM peripheral differs among different devices. For example, +* deep standby may not be available on a particular device. You can find +* information for your device in the corresponding peripheral manual. +* +* \section SectionLPM_ConfigurationConsideration Configuration Consideration +* There is no configuration structure. To enter low power consumption mode +* call Lpm_GoToStandByMode() and specify which low power mode to use. +* See en_lpm_mode_t for the choices. The second argument specifies +* whether to save IO settings or set all IO to high impedance.
+* When you make this call, the MCU enters low power consumption mode +* immediately. This function does not return until the MCU wakes up +* for some reason. The return path will vary. From standby modes, the +* function returns normally and your program can resume operation. +* From deep standby modes, control returns from the reset vector.
+* To configure the reset vector, use Lpm_ConfigDeepStbRetCause() to +* set the return causes and Lpm_ReadDeepStbRetCause() to read the return +* cause after the MCU wakes up.
+* \note Wakeup from the WKUP0 pin is always enabled. +* Use API function calls to:
+* * Read or write the contents of the backup registers +* * Retain the contents of RAM +* * Set the wakeup pin level +* * Configure the subclock for RTC and CEC in deep standby mode +* Lpm_SetWkupPinLevel() is used to set the WKUP pin active level.
+* \note Low power feature availability varies among FM products, as does +* the size of the backup registers. The deep standby mode may not be +* available for some FM products. Consult the corresponding data sheet or +* peripheral manual for details for your part.
+* +* \section SectionLPM_MoreInfo More Information +* For more information on the LPM peripheral, refer to:
+* FM0+ Peripheral Manual - Core Subsystem TRM.pdf
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupLPM_Macros +* \{ +*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) +#define PDL_BACK_UP_REGISTERS (32u) +#else +#define PDL_BACK_UP_REGISTERS (16u) +#endif + +#define WIFSR_WRTCI (1ul<<0u) +#define WIFSR_WLVDI (1ul<<1u) +#define WIFSR_WUI0 (1ul<<2u) +#define WIFSR_WUI1 (1ul<<3u) +#define WIFSR_WUI2 (1ul<<4u) +#define WIFSR_WUI3 (1ul<<5u) +#define WIFSR_WUI4 (1ul<<6u) +#define WIFSR_WUI5 (1ul<<7u) +#define WIFSR_WCEC0I (1ul<<8u) +#define WIFSR_WCEC1I (1ul<<9u) +#define WIFSR_WUI6 (1ul<<10u) +#define WIFSR_WUI7 (1ul<<11u) +#define WIFSR_WUI8 (1ul<<12u) +#define WIFSR_WUI9 (1ul<<13u) +#define WIFSR_WUI10 (1ul<<14u) +#define WIFSR_WUI11 (1ul<<15u) + +#define WRFSR_WINITX (1ul<<0u) +#define WRFSR_WLVDH (1ul<<1u) + +/** \} GroupLPM_Macros */ + +/** +* \addtogroup GroupLPM_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief define standby mode type + ******************************************************************************/ +typedef enum en_lpm_mode +{ + StbSleepMode = 0u, //!< standby sleep mode + StbTimerMode = 1u, //!< standby timer mode + StbStopMode = 2u, //!< standby stop mode + StbRtcMode = 3u, //!< standby RTC mode + DeepStbRtcMode = 4u, //!< deep standby RTC mode + DeepStbStopMode = 5u, //!< deep standby stop mode + +} en_lpm_mode_t; + +/** + ****************************************************************************** + ** \brief define deep standby mode return cause flag + ******************************************************************************/ +typedef enum en_ret_cause_flag +{ + DeepStbNoFlag = 0u, ///< No flag set + DeepStbInitx = 1u, ///< return from INITX input reset + DeepStbLvdReset = 2u, ///< return from LVD reset + DeepStbRtcInt = 3u, ///< return from RTC interrupt + DeepStbLvdInt = 4u, ///< return from LVD interrupt + DeepStbWkupPin0 = 5u, ///< return from Wkup pin1 detection + DeepStbWkupPin1 = 6u, ///< return from Wkup pin1 detection + DeepStbWkupPin2 = 7u, ///< return from Wkup pin2 detection + DeepStbWkupPin3 = 8u, ///< return from Wkup pin3 detection + DeepStbWkupPin4 = 9u, ///< return from Wkup pin4 detection + DeepStbWkupPin5 = 10u, ///< return from Wkup pin5 detection + DeepStbCec0 = 11u, ///< return from Wkup CEC1 reception interrupt + DeepStbCec1 = 12u, ///< return from Wkup CEC2 reception interrupt +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + DeepStbWkupPin6 = 13u, ///< return from Wkup pin6 detection + DeepStbWkupPin7 = 14u, ///< return from Wkup pin7 detection + DeepStbWkupPin8 = 15u, ///< return from Wkup pin8 detection + DeepStbWkupPin9 = 16u, ///< return from Wkup pin9 detection + DeepStbWkupPin10 = 17u, ///< return from Wkup pin10 detection + DeepStbWkupPin11 = 18u, ///< return from Wkup pin11 detection +#endif +} en_dstb_ret_cause_t; + +/** +****************************************************************************** + ** \brief define wkup pin index +******************************************************************************/ +typedef enum en_dstb_wkup_pin +{ + WkupPin1 = 0u, ///< index of wkup pin 1 + WkupPin2 = 1u, ///< index of wkup pin 2 + WkupPin3 = 2u, ///< index of wkup pin 3 + WkupPin4 = 3u, ///< index of wkup pin 4 + WkupPin5 = 4u, ///< index of wkup pin 5 +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + WkupPin6 = 5u, ///< index of wkup pin 6 + WkupPin7 = 6u, ///< index of wkup pin 7 + WkupPin8 = 7u, ///< index of wkup pin 8 + WkupPin9 = 8u, ///< index of wkup pin 9 + WkupPin10 = 9u, ///< index of wkup pin 10 + WkupPin11 = 10u, ///< index of wkup pin 11 +#endif + WkupPinMax, +} en_dstb_wkup_pin_t; + +/** + ****************************************************************************** + ** \brief Valid level of wakeup pin + ******************************************************************************/ +typedef enum en_wkup_valid_level +{ + WkupLowLevelValid = 0u, ///< Set low level as valid level + WkupHighLevelValid = 1u, ///< Set high level as valid level + +}en_wkup_valid_level_t; + +/** + ****************************************************************************** + ** \brief Internal voltage selection in deep standby mode + ******************************************************************************/ +typedef enum en_lpm_internal_voltage +{ + LpmInternalVoltage120 = 0u, ///< Internal voltage is 1.20v in deepstandby mode. + LpmInternalVoltage105 = 1u, ///< Internal voltage is 1.05v in deepstandby mode. + LpmInternalVoltage110 = 2u, ///< Internal voltage is 1.10v in deepstandby mode. + +}en_lpm_internal_voltage_t; + +/** + ****************************************************************************** + ** \brief Main oscillator selection types + ******************************************************************************/ +typedef enum en_lpm_main_osc +{ + LpmMainOsc4M = 0u, ///< Support 4MHz main oscillator in deep standby mode, has the lowest power consumption + LpmMainOsc4M8M = 1u, ///< Support 4MHz and 8MHz main oscillator in deep standby mode, has the middle power consumption + LpmMainOsc4M8M16M = 2u, ///< Support 4MHz, 8MHz, and 16MHz main oscillator in deep standby mode, has higher power consumption + LpmMainOsc48M = 3u, ///< Support 48MHz main oscillator in deep standby mode, has the highest power consumption + +}en_lpm_main_osc_t; + +/** + ****************************************************************************** + ** \brief backup register index + *******************************************************************************/ +typedef enum en_dstb_bakup_reg +{ + BackupReg1 = 1u, ///< index of backup register 1 + BackupReg2 = 2u, ///< index of backup register 2 + BackupReg3 = 3u, ///< index of backup register 3 + BackupReg4 = 4u, ///< index of backup register 4 + BackupReg5 = 5u, ///< index of backup register 5 + BackupReg6 = 6u, ///< index of backup register 6 + BackupReg7 = 7u, ///< index of backup register 7 + BackupReg8 = 8u, ///< index of backup register 8 + BackupReg9 = 9u, ///< index of backup register 9 + BackupReg10 = 10u, ///< index of backup register 10 + BackupReg11 = 11u, ///< index of backup register 11 + BackupReg12 = 12u, ///< index of backup register 12 + BackupReg13 = 13u, ///< index of backup register 13 + BackupReg14 = 14u, ///< index of backup register 14 + BackupReg15 = 15u, ///< index of backup register 15 + BackupReg16 = 16u, ///< index of backup register 16 + +} en_dstb_bakup_reg_t; + +/** \}GroupLPM_Types */ + +/** +* \addtogroup GroupLPM_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Deep standby mode return cause + *******************************************************************************/ +typedef struct stc_ret_cause +{ + boolean_t bRtcEn; //!< Return from RTC interrupt enable + boolean_t bLvdEn; //!< Return from LVD interrupt enable + boolean_t bWakeup1En; //!< Return from Wakeup1 pin enable + boolean_t bWakeup2En; //!< Return from Wakeup2 pin enable + boolean_t bWakeup3En; //!< Return from Wakeup3 pin enable + boolean_t bWakeup4En; //!< Return from Wakeup4 pin enable + boolean_t bWakeup5En; //!< Return from Wakeup5 pin enable + boolean_t bCec0En; //!< Return from CEC0 interrupt enable + boolean_t bCec1En; //!< Return from CEC1 interrupt enable +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + boolean_t bWakeup6En; //!< Return from Wakeup6 pin enable + boolean_t bWakeup7En; //!< Return from Wakeup7 pin enable + boolean_t bWakeup8En; //!< Return from Wakeup8 pin enable + boolean_t bWakeup9En; //!< Return from Wakeup9 pin enable + boolean_t bWakeup10En; //!< Return from Wakeup10 pin enable + boolean_t bWakeup11En; //!< Return from Wakeup10 pin enable +#endif +}stc_dstb_ret_cause_t; + +/** + ****************************************************************************** + ** \brief backup register index + *******************************************************************************/ +typedef struct stc_backupreg +{ + uint8_t u8BREG00; + uint8_t u8BREG01; + uint8_t u8BREG02; + uint8_t u8BREG03; + uint8_t u8BREG04; + uint8_t u8BREG05; + uint8_t u8BREG06; + uint8_t u8BREG07; + uint8_t u8BREG08; + uint8_t u8BREG09; + uint8_t u8BREG0A; + uint8_t u8BREG0B; + uint8_t u8BREG0C; + uint8_t u8BREG0D; + uint8_t u8BREG0E; + uint8_t u8BREG0F; + uint8_t u8BREG10; + uint8_t u8BREG11; + uint8_t u8BREG12; + uint8_t u8BREG13; + uint8_t u8BREG14; + uint8_t u8BREG15; + uint8_t u8BREG16; + uint8_t u8BREG17; + uint8_t u8BREG18; + uint8_t u8BREG19; + uint8_t u8BREG1A; + uint8_t u8BREG1B; + uint8_t u8BREG1C; + uint8_t u8BREG1D; + uint8_t u8BREG1E; + uint8_t u8BREG1F; +} stc_backupreg_t; + +/** \} GroupLPM_DataStructures */ + +/** +* \addtogroup GroupLPM_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +void Lpm_GoToStandByMode(en_lpm_mode_t enMode, boolean_t bIoRemain); +en_result_t Lpm_ConfigDeepStbRetCause(stc_dstb_ret_cause_t* pstcCause); +en_dstb_ret_cause_t Lpm_ReadDeepStbRetCause(void); +en_result_t Lpm_SetWkupPinLevel(en_dstb_wkup_pin_t enPinIndex, en_wkup_valid_level_t enLevel); +en_result_t Lpm_ConfigSubClk(boolean_t bSupplyCec, boolean_t bSupplyRtc); +en_result_t Lpm_ConfigDeepStbRAMRetention(boolean_t bRamRetain); +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +en_result_t Lpm_ConfigInternalVoltage(en_lpm_internal_voltage_t enVoltage); +en_result_t Lpm_SelMainOscTypes(en_lpm_main_osc_t enMainOsc); +en_result_t Lpm_ConfigFlashPower(boolean_t bPowerOn); +#endif +en_result_t Lpm_Readu8DataBackupRegister(uint8_t u8AddressOffset, uint8_t* u8Data) ; +en_result_t Lpm_Writeu8DataBackupRegister(uint8_t u8AddressOffset, uint8_t u8Data) ; +en_result_t Lpm_Readu16DataBackupRegister(uint8_t u8AddressOffset, uint16_t* u16Data) ; +en_result_t Lpm_Writeu16DataBackupRegister(uint8_t u8AddressOffset, uint16_t u16Data) ; +en_result_t Lpm_Readu32DataBackupRegister(uint8_t u8AddressOffset, uint32_t* u32Data) ; +en_result_t Lpm_Writeu32DataBackupRegister(uint8_t u8AddressOffset, uint32_t u32Data) ; + +/** \} GroupLPM_Functions */ +/** \} GroupLPM */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_LPM_ACTIVE)) + +#endif /* __LPM_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lvd/lvd.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lvd/lvd.c new file mode 100644 index 0000000000..63be92ebf4 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lvd/lvd.c @@ -0,0 +1,497 @@ +/******************************************************************************* +* \file lvd.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the LVD +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "lvd/lvd.h" + +#if (defined(PDL_PERIPHERAL_LVD_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_LVD == PDL_ON) +static stc_lvd_intern_data_t stcLvdInternData = {{0u, 0u}}; +#endif +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/* Unlock code for LVD_RLR */ +#define LvdCtlUnlock (0x1ACCE553) + +#if (PDL_INTERRUPT_ENABLE_LVD == PDL_ON) +/** + ****************************************************************************** + ** \brief ISR of the LVD module + ** + ******************************************************************************/ +void Lvd_IrqHandler(void) +{ + if (1u == FM_LVD->LVD_STR_f.LVDIR) + { + if (NULL != stcLvdInternData.pfnIrqCallback) + { + stcLvdInternData.pfnIrqCallback[0](); /* Clear LVD interrupt */ + } + + FM_LVD->LVD_CLR_f.LVDCL = 0; + } +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + if (1u == FM_LVD->LVD_STR_f.LVD2IR) + { + if (NULL != stcLvdInternData.pfnIrqCallback) + { + stcLvdInternData.pfnIrqCallback[1](); /* Clear LVD interrupt */ + } + + FM_LVD->LVD_CLR_f.LVD2CL = 0; + } +#endif +} /* LvdIrqHandler */ +#endif + +/** + ****************************************************************************** + ** \brief Init the LVD module + ** + ** Generating interrupts is able to use by specifying callback function. + ** If callback function is not specified (NULL), interrupt (LVD function) + ** is enabled, but NVIC is not enabled. + ** So user has to check interrupt status by #Lvd_GetIrqStatus. + ** This function enables the interrupt and the user setting voltage for + ** the LVD module. + ** + ** \param [in] pstcConfig LVD module configuration + ** + ** \retval Ok Initializiation of LVD interupt successfully + ** done. + ** \retval ErrorInvalidParameter pstcConfig == NULL or invalid + ******************************************************************************/ +en_result_t Lvd_Init(const stc_lvd_config_t* pstcConfig) +{ + en_result_t enResult; + stc_lvd_lvd_ctl_field_t stcLVD_CTL; +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + stc_lvd_lvd_ctl2_field_t stcLVD_CTL2; + stc_lvd_lvd2_ctl_field_t stcLVD2_CTL; + stc_lvd_lvd2_ctl2_field_t stcLVD2_CTL2; +#endif + + PDL_ZERO_STRUCT(stcLVD_CTL); +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + PDL_ZERO_STRUCT(stcLVD_CTL2); + PDL_ZERO_STRUCT(stcLVD2_CTL); + PDL_ZERO_STRUCT(stcLVD2_CTL2); +#endif + + enResult = ErrorInvalidParameter; + /* Check for valid pointer */ + if (NULL != pstcConfig) + { + enResult = Ok; + + /* Prepare LVD_CTL */ + if(pstcConfig->enLvd0IrqDetectVoltage < Lvd0IrqDetectVoltageMax) + { + stcLVD_CTL.SVHI = (uint8_t) pstcConfig->enLvd0IrqDetectVoltage; + } + else + { + enResult = ErrorInvalidParameter; + } +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + /* Prepare LVD_CTL2 */ + if(pstcConfig->enLvd0IrqReleaseVoltage < Lvd0IrqReleaseVoltageMax) + { + stcLVD_CTL2.SVHRLI = (uint8_t) pstcConfig->enLvd0IrqReleaseVoltage; + } + else + { + enResult = ErrorInvalidParameter; + } + + stcLVD_CTL2.LVDRLIE = ((pstcConfig->bLvd0ReleaseVoltageEnable == TRUE) ? 1 : 0); +#endif + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) + if(pstcConfig->enLvdResetVoltage < LvdResetVoltageMax) + { + stcLVD_CTL.SVHR = (uint8_t) pstcConfig->enLvdResetVoltage; + } + else + { + enResult = ErrorInvalidParameter; + } +#endif +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + /* Prepare LVD_CTL */ + if(pstcConfig->enLvd1IrqDetectVoltage < Lvd1IrqDetectVoltageMax) + { + stcLVD2_CTL.SVH2I = (uint8_t) pstcConfig->enLvd1IrqDetectVoltage; + } + else + { + enResult = ErrorInvalidParameter; + } + + /* Prepare LVD2_CTL2 */ + if(pstcConfig->enLvd1IrqReleaseVoltage < Lvd1IrqReleaseVoltageMax) + { + stcLVD2_CTL2.SVH2RLI = (uint8_t) pstcConfig->enLvd1IrqReleaseVoltage; + } + else + { + enResult = ErrorInvalidParameter; + } + + stcLVD2_CTL2.LVD2RLIE = ((pstcConfig->bLvd1ReleaseVoltageEnable == TRUE) ? 1 : 0); +#endif + if (Ok == enResult) + { + #if (PDL_INTERRUPT_ENABLE_LVD == PDL_ON) + /* Setup callback function pointer in internal data */ + stcLvdInternData.pfnIrqCallback[0] = pstcConfig->pfnIrqCallback[0]; + stcLvdInternData.pfnIrqCallback[1] = pstcConfig->pfnIrqCallback[1]; + + /* If callback function is set, interrupt is used. */ + if ((NULL != pstcConfig->pfnIrqCallback[0]) || + (NULL != pstcConfig->pfnIrqCallback[1]) ) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + /* Init NVIC */ + NVIC_ClearPendingIRQ(CSV_SWDT_LVD_IRQn); + NVIC_EnableIRQ(CSV_SWDT_LVD_IRQn); + NVIC_SetPriority(CSV_SWDT_LVD_IRQn, PDL_IRQ_LEVEL_CSV_SWDT_LVD); + #else + /* Init NVIC */ + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_EnableIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, PDL_IRQ_LEVEL_LVD); + #endif + } + #endif + FM_LVD->LVD_CLR = 0x00u; /* Clear possible pending LVD interrupt (LVDCL (bit #7)) */ + FM_LVD->LVD_RLR = LvdCtlUnlock;/* unlock LVD_CTL */ + FM_LVD->LVD_CTL_f = stcLVD_CTL; +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + FM_LVD->LVD_CTL2_f = stcLVD_CTL2; + FM_LVD->LVD2_CTL_f = stcLVD2_CTL; + FM_LVD->LVD2_CTL2_f = stcLVD2_CTL2; +#endif + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + } + } + + return (enResult); +} /* Lvd_InitIrq */ + +/** + ****************************************************************************** + ** \brief De-Init the Interrupt of the LVD module + ** + ** \retval Ok De-Initializiation of LVD interupt + ** successfully done. + ** + ******************************************************************************/ +en_result_t Lvd_DeInit(void) +{ +#if (PDL_INTERRUPT_ENABLE_LVD == PDL_ON) + /* De-Init NVIC */ + if ((NULL != stcLvdInternData.pfnIrqCallback[0]) || + (NULL != stcLvdInternData.pfnIrqCallback[1])) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(CSV_SWDT_LVD_IRQn); + NVIC_DisableIRQ(CSV_SWDT_LVD_IRQn); + NVIC_SetPriority(CSV_SWDT_LVD_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #else + NVIC_ClearPendingIRQ(LVD_IRQn); + NVIC_DisableIRQ(LVD_IRQn); + NVIC_SetPriority(LVD_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + stcLvdInternData.pfnIrqCallback[0] = NULL; + stcLvdInternData.pfnIrqCallback[1] = NULL; + } +#endif + FM_LVD->LVD_RLR = LvdCtlUnlock;/* unlock LVD_CTL */ + FM_LVD->LVD_CTL = 0u; /* Clea all (LVDIE (bit #7)) */ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + FM_LVD->LVD_CTL2 = 0u; + FM_LVD->LVD2_CTL = 0u; + FM_LVD->LVD2_CTL2 = 0u; +#endif + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + + return (Ok); +} /* Lvd_DeInitIrq */ + +/** + ****************************************************************************** + ** \brief Enable Interrupt circuit of the LVD module + ** + ** \param u8Channel LVD channel + ** + ** \retval Ok Interrupt enabled + ** + ******************************************************************************/ +en_result_t Lvd_EnableIrqDetect(uint8_t u8Channel) +{ + if (u8Channel == 0u) + { + FM_LVD->LVD_RLR = LvdCtlUnlock; /* unlock LVD_CTL */ + FM_LVD->LVD_CTL_f.LVDIE = 1u; + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + } + else if (u8Channel == 1u) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + FM_LVD->LVD_RLR = LvdCtlUnlock; /* unlock LVD_CTL */ + FM_LVD->LVD2_CTL_f.LVD2IE = 1u; + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + #endif + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable Interrupt circuit of the LVD module + ** + ** \param u8Channel LVD channel + ** + ** \retval Ok Interrupt Disabled + ** + ******************************************************************************/ +en_result_t Lvd_DisableIrqDetect(uint8_t u8Channel) +{ + if (u8Channel == 0u) + { + FM_LVD->LVD_RLR = LvdCtlUnlock; /* unlock LVD_CTL */ + FM_LVD->LVD_CTL_f.LVDIE = 0u; + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + } + else if (u8Channel == 1u) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + FM_LVD->LVD_RLR = LvdCtlUnlock; /* unlock LVD_CTL */ + FM_LVD->LVD2_CTL_f.LVD2IE = 0u; + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + #endif + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} + + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || (PDL_MCU_TYPE == PDL_FM0P_TYPE2) ||\ + (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) +/** + ****************************************************************************** + ** \brief Enable reset circuit of the LVD module + ** + ** \retval Ok Reset Enabled + ** + ******************************************************************************/ +en_result_t Lvd_EnableReset(void) +{ + FM_LVD->LVD_RLR = LvdCtlUnlock; /* unlock LVD_CTL */ + FM_LVD->LVD_CTL_f.LVDRE = 1u; + FM_LVD->LVD_RLR = 0; /* lock LVD_CTL */ + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable reset circuit of the LVD module + ** + ** \retval Ok Reset Disabled + ** + ******************************************************************************/ +en_result_t Lvd_DisableReset(void) +{ + FM_LVD->LVD_RLR = LvdCtlUnlock; /* unlock LVD_CTL */ + FM_LVD->LVD_CTL_f.LVDRE = 0u; + FM_LVD->LVD_RLR = 0u; /* lock LVD_CTL */ + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get the LVD interrupt status + ** + ** \param u8Channel LVD channel + ** + ** \retval FALSE A low-voltage detection is not detected. + ** \retval TRUE A low-voltage detection has been detected. + ** + ******************************************************************************/ +boolean_t Lvd_GetIrqStatus(uint8_t u8Channel) +{ + boolean_t bRetVal = FALSE; + + if(0u == u8Channel) + { + /* Check the LVD interrupt status */ + if (TRUE == FM_LVD->LVD_STR_f.LVDIR) + { + bRetVal = TRUE; + } + } + else if(1u == u8Channel) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + /* Check the LVD interrupt status */ + if (TRUE == FM_LVD->LVD_STR_f.LVD2IR) + { + bRetVal = TRUE; + } + #endif + } + return (bRetVal); +} /* Lvd_GetIntOperationStatus */ + +/** + ****************************************************************************** + ** \brief Clear the LVD interrupt status + ** + ******************************************************************************/ +en_result_t Lvd_ClrIrqStatus(uint8_t u8Channel) +{ + if (0u == u8Channel) + { + FM_LVD->LVD_CLR_f.LVDCL = 0x00u; /* Clear LVD interrupt */ + } + else if (1u == u8Channel) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + FM_LVD->LVD_CLR_f.LVD2CL = 0x00u; /* Clear LVD interrupt */ + #endif + } + else + { + return ErrorInvalidParameter; + } + + return Ok; +} /* Lvd_ClearIntStatus */ + +/** + ****************************************************************************** + ** \brief Get the operation status of the LVD interrupt + ** + ** \retval FALSE Stabilization wait state or monitoring stop state + ** \retval TRUE Monitoring state + ** + ******************************************************************************/ +boolean_t Lvd_GetIrqOperationStatus(uint8_t u8Channel) +{ + boolean_t bRetVal = FALSE; + + if(0u == u8Channel) + { + /* Check the operation status of LVD interrupt */ + if (TRUE == FM_LVD->LVD_STR2_f.LVDIRDY) + { + bRetVal = TRUE; + } + } + else if (1u == u8Channel) + { + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + /* Check the operation status of LVD interrupt */ + if (TRUE == FM_LVD->LVD_STR2_f.LVD2IRDY) + { + bRetVal = TRUE; + } + #endif + } + return (bRetVal); +} /* Lvd_GetIntOperationStatus */ + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || (PDL_MCU_TYPE == PDL_FM0P_TYPE2) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) +/** + ****************************************************************************** + ** \brief Get the operation status of the LVD reset + ** + ** \retval FALSE Stabilization wait state or monitoring stop state + ** \retval TRUE Monitoring state + ** + ******************************************************************************/ +boolean_t Lvd_GetResetOperationStatus(void) +{ + boolean_t bRetVal = FALSE; + + /* Check the operation status of LVD interrupt */ + if (TRUE == FM_LVD->LVD_STR2_f.LVDRRDY) + { + bRetVal = TRUE; + } + return (bRetVal); +} /* Lvd_GetIntOperationStatus */ +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_LVD_ACTIVE)) */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lvd/lvd.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lvd/lvd.h new file mode 100644 index 0000000000..d9e27743f5 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/lvd/lvd.h @@ -0,0 +1,463 @@ +/******************************************************************************* +* \file lvd.h +* +* \version 1.20 +* +* \brief Headerfile for LVD functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __LVD_H__ +#define __LVD_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_LVD_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupLVD Low Voltage Detection (LVD) +* \{ +* \defgroup GroupLVD_Macros Macros +* \defgroup GroupLVD_Functions Functions +* \defgroup GroupLVD_DataStructures Data Structures +* \defgroup GroupLVD_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupLVD +* \{ +* The Low-voltage Detection circuit (LVD) monitors the power supply voltage +* and generates a reset when the power supply voltage falls below a specified +* voltage.
+* LVD can also generate an interrupt, rather than a reset, if the power +* supply voltage falls below the detection threshold. You can set two +* threshold levels, and generate an interrupt for each.
+* Support for LVD varies among FM products. Refer to the Peripheral Manual - +* Core Subsytem for details for your part. For example, the voltage range +* differs among device types. The threshold for generating an interrupt +* and/or reset will vary. +* \section SectionLVD_ConfigurationConsideration Configuration Consideration +* To set up the LVD, you provide configuration parameters in the +* stc_lvd_config_t structure. For example, you set the voltage threshold +* for a reset. You can set two thresholds for interrupt generation. +* Use enumerated constants for the various thresholds and set the values +* in enLvd0IrqDetectVoltage and enLvd1IrqDetectVoltage. You also +* specify the interrupt callback function for each interrupt in +* pfnIrqCallback.
+* You can also set the enLvd0IrqReleaseVoltage, and enLvd1IrqReleaseVoltage, +* but this applies only to FM0+ Type 2 parts.
+* Then call Lvd_Init() to initialize the voltage thresholds for the interrupt and +* reset circuits.
+* If you do not provide a callback function, use Lvd_GetIrqStatus() to poll for +* the interrupt, and clear the interrupt with Lvd_ClearIrqStatus().
+* At runtime you can use API function calls to:
+* * Enable, disable, or get the status of either low voltage interrupt +* * Enable, disable, or get the status of the low voltage reset +* +* \section SectionLVD_MoreInfo More Information +* For more information on the LVD peripheral, refer to:
+* FM0+ Peripheral Manual - Core Subsystem TRM.pdf
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** +* \addtogroup GroupLVD_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief LVD ch.0 Interruption voltage settings for Low Voltage Detection + ******************************************************************************/ +typedef enum en_lvd0_irq_detect_voltage +{ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) + Lvd0IrqDetectVoltage280 = 3u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqDetectVoltage300 = 4u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqDetectVoltage320 = 5u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqDetectVoltage360 = 6u, ///< Interrupt when voltage is vicinity of 3.60 volts + Lvd0IrqDetectVoltage370 = 7u, ///< Interrupt when voltage is vicinity of 3.70 volts + Lvd0IrqDetectVoltage400 = 8u, ///< Interrupt when voltage is vicinity of 4.00 volts + Lvd0IrqDetectVoltage410 = 9u, ///< Interrupt when voltage is vicinity of 4.10 volts + Lvd0IrqDetectVoltage420 = 10u, ///< Interrupt when voltage is vicinity of 4.20 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#elif (PDL_MCU_TYPE == PDL_FM4_TYPE1) || (PDL_MCU_TYPE == PDL_FM4_TYPE2) || (PDL_MCU_TYPE == PDL_FM4_TYPE6) + Lvd0IrqDetectVoltage280 = 7u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqDetectVoltage300 = 4u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqDetectVoltage320 = 12u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqDetectVoltage360 = 15u, ///< Interrupt when voltage is vicinity of 3.60 volts + Lvd0IrqDetectVoltage370 = 14u, ///< Interrupt when voltage is vicinity of 3.70 volts + Lvd0IrqDetectVoltage400 = 9u, ///< Interrupt when voltage is vicinity of 4.00 volts + Lvd0IrqDetectVoltage410 = 8u, ///< Interrupt when voltage is vicinity of 4.10 volts + Lvd0IrqDetectVoltage420 = 24u, ///< Interrupt when voltage is vicinity of 4.20 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#elif (PDL_MCU_TYPE == PDL_FM4_TYPE3) || (PDL_MCU_TYPE == PDL_FM4_TYPE4) || (PDL_MCU_TYPE == PDL_FM4_TYPE5) + Lvd0IrqDetectVoltage290 = 7u, ///< Interrupt when voltage is vicinity of 2.90 volts + Lvd0IrqDetectVoltage310 = 4u, ///< Interrupt when voltage is vicinity of 3.10 volts + Lvd0IrqDetectVoltage330 = 12u, ///< Interrupt when voltage is vicinity of 3.30 volts + Lvd0IrqDetectVoltage380 = 15u, ///< Interrupt when voltage is vicinity of 3.80 volts + Lvd0IrqDetectVoltage390 = 14u, ///< Interrupt when voltage is vicinity of 3.90 volts + Lvd0IrqDetectVoltage420 = 9u, ///< Interrupt when voltage is vicinity of 4.20 volts + Lvd0IrqDetectVoltage430 = 8u, ///< Interrupt when voltage is vicinity of 4.30 volts + Lvd0IrqDetectVoltage440 = 24u, ///< Interrupt when voltage is vicinity of 4.40 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#elif (PDL_MCU_TYPE == PDL_FM3_TYPE0) || (PDL_MCU_TYPE == PDL_FM3_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE2) || (PDL_MCU_TYPE == PDL_FM3_TYPE4) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE5) + Lvd0IrqDetectVoltage280 = 0u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqDetectVoltage300 = 1u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqDetectVoltage320 = 2u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqDetectVoltage360 = 3u, ///< Interrupt when voltage is vicinity of 3.60 volts + Lvd0IrqDetectVoltage370 = 4u, ///< Interrupt when voltage is vicinity of 3.70 volts + Lvd0IrqDetectVoltage400 = 7u, ///< Interrupt when voltage is vicinity of 4.00 volts + Lvd0IrqDetectVoltage410 = 8u, ///< Interrupt when voltage is vicinity of 4.10 volts + Lvd0IrqDetectVoltage420 = 9u, ///< Interrupt when voltage is vicinity of 4.20 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#elif (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) + Lvd0IrqDetectVoltage200 = 0u, ///< Interrupt when voltage is vicinity of 2.00 volts + Lvd0IrqDetectVoltage210 = 1u, ///< Interrupt when voltage is vicinity of 2.10 volts + Lvd0IrqDetectVoltage220 = 2u, ///< Interrupt when voltage is vicinity of 2.20 volts + Lvd0IrqDetectVoltage230 = 3u, ///< Interrupt when voltage is vicinity of 2.30 volts + Lvd0IrqDetectVoltage240 = 4u, ///< Interrupt when voltage is vicinity of 2.40 volts + Lvd0IrqDetectVoltage250 = 5u, ///< Interrupt when voltage is vicinity of 2.50 volts + Lvd0IrqDetectVoltage260 = 6u, ///< Interrupt when voltage is vicinity of 2.60 volts + Lvd0IrqDetectVoltage280 = 7u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqDetectVoltage300 = 8u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqDetectVoltage320 = 9u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqDetectVoltage360 = 10u, ///< Interrupt when voltage is vicinity of 3.60 volts + Lvd0IrqDetectVoltage370 = 11u, ///< Interrupt when voltage is vicinity of 3.70 volts + Lvd0IrqDetectVoltage400 = 12u, ///< Interrupt when voltage is vicinity of 4.00 volts + Lvd0IrqDetectVoltage410 = 13u, ///< Interrupt when voltage is vicinity of 4.10 volts + Lvd0IrqDetectVoltage420 = 14u, ///< Interrupt when voltage is vicinity of 4.20 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#elif (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) + Lvd0IrqDetectVoltage170 = 4u, ///< Interrupt when voltage is vicinity of 1.70 volts + Lvd0IrqDetectVoltage175 = 5u, ///< Interrupt when voltage is vicinity of 1.75 volts + Lvd0IrqDetectVoltage180 = 6u, ///< Interrupt when voltage is vicinity of 1.80 volts + Lvd0IrqDetectVoltage185 = 7u, ///< Interrupt when voltage is vicinity of 1.85 volts + Lvd0IrqDetectVoltage190 = 8u, ///< Interrupt when voltage is vicinity of 1.90 volts + Lvd0IrqDetectVoltage195 = 9u, ///< Interrupt when voltage is vicinity of 1.95 volts + Lvd0IrqDetectVoltage200 = 10u, ///< Interrupt when voltage is vicinity of 2.00 volts + Lvd0IrqDetectVoltage205 = 11u, ///< Interrupt when voltage is vicinity of 2.05 volts + Lvd0IrqDetectVoltage250 = 12u, ///< Interrupt when voltage is vicinity of 2.50 volts + Lvd0IrqDetectVoltage260 = 13u, ///< Interrupt when voltage is vicinity of 2.60 volts + Lvd0IrqDetectVoltage270 = 14u, ///< Interrupt when voltage is vicinity of 2.70 volts + Lvd0IrqDetectVoltage280 = 15u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqDetectVoltage290 = 16u, ///< Interrupt when voltage is vicinity of 2.90 volts + Lvd0IrqDetectVoltage300 = 17u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqDetectVoltage310 = 18u, ///< Interrupt when voltage is vicinity of 3.10 volts + Lvd0IrqDetectVoltage320 = 19u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#elif (PDL_MCU_TYPE == PDL_FM0P_TYPE2) || (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + Lvd0IrqDetectVoltage150 = 0u, ///< Interrupt when voltage is vicinity of 1.50 volts + Lvd0IrqDetectVoltage155 = 1u, ///< Interrupt when voltage is vicinity of 1.55 volts + Lvd0IrqDetectVoltage160 = 2u, ///< Interrupt when voltage is vicinity of 1.60 volts + Lvd0IrqDetectVoltage165 = 3u, ///< Interrupt when voltage is vicinity of 1.65 volts + Lvd0IrqDetectVoltage170 = 4u, ///< Interrupt when voltage is vicinity of 1.70 volts + Lvd0IrqDetectVoltage175 = 5u, ///< Interrupt when voltage is vicinity of 1.75 volts + Lvd0IrqDetectVoltage180 = 6u, ///< Interrupt when voltage is vicinity of 1.80 volts + Lvd0IrqDetectVoltage185 = 7u, ///< Interrupt when voltage is vicinity of 1.85 volts + Lvd0IrqDetectVoltage190 = 8u, ///< Interrupt when voltage is vicinity of 1.90 volts + Lvd0IrqDetectVoltage195 = 9u, ///< Interrupt when voltage is vicinity of 1.95 volts + Lvd0IrqDetectVoltage200 = 10u, ///< Interrupt when voltage is vicinity of 2.00 volts + Lvd0IrqDetectVoltage205 = 11u, ///< Interrupt when voltage is vicinity of 2.05 volts + Lvd0IrqDetectVoltage250 = 12u, ///< Interrupt when voltage is vicinity of 2.50 volts + Lvd0IrqDetectVoltage260 = 13u, ///< Interrupt when voltage is vicinity of 2.60 volts + Lvd0IrqDetectVoltage270 = 14u, ///< Interrupt when voltage is vicinity of 2.70 volts + Lvd0IrqDetectVoltage280 = 15u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqDetectVoltage290 = 16u, ///< Interrupt when voltage is vicinity of 2.90 volts + Lvd0IrqDetectVoltage300 = 17u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqDetectVoltage310 = 18u, ///< Interrupt when voltage is vicinity of 3.10 volts + Lvd0IrqDetectVoltage320 = 19u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage +#endif +} en_lvd0_irq_detect_voltage_t; + +/** + ****************************************************************************** + ** \brief LVD ch.0 Interruption release voltage settings for Low Voltage Detection + ******************************************************************************/ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +typedef enum en_lvd0_irq_release_voltage +{ + Lvd0IrqReleaseVoltage155 = 0u, ///< Interrupt when voltage is vicinity of 1.55 volts + Lvd0IrqReleaseVoltage160 = 1u, ///< Interrupt when voltage is vicinity of 1.60 volts + Lvd0IrqReleaseVoltage165 = 2u, ///< Interrupt when voltage is vicinity of 1.65 volts + Lvd0IrqReleaseVoltage170 = 3u, ///< Interrupt when voltage is vicinity of 1.70 volts + Lvd0IrqReleaseVoltage175 = 4u, ///< Interrupt when voltage is vicinity of 1.75 volts + Lvd0IrqReleaseVoltage180 = 5u, ///< Interrupt when voltage is vicinity of 1.80 volts + Lvd0IrqReleaseVoltage185 = 6u, ///< Interrupt when voltage is vicinity of 1.85 volts + Lvd0IrqReleaseVoltage190 = 7u, ///< Interrupt when voltage is vicinity of 1.90 volts + Lvd0IrqReleaseVoltage195 = 8u, ///< Interrupt when voltage is vicinity of 1.95 volts + Lvd0IrqReleaseVoltage200 = 9u, ///< Interrupt when voltage is vicinity of 2.00 volts + Lvd0IrqReleaseVoltage205 = 10u, ///< Interrupt when voltage is vicinity of 2.05 volts + Lvd0IrqReleaseVoltage250 = 11u, ///< Interrupt when voltage is vicinity of 2.50 volts + Lvd0IrqReleaseVoltage260 = 12u, ///< Interrupt when voltage is vicinity of 2.60 volts + Lvd0IrqReleaseVoltage270 = 13u, ///< Interrupt when voltage is vicinity of 2.70 volts + Lvd0IrqReleaseVoltage280 = 14u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd0IrqReleaseVoltage290 = 15u, ///< Interrupt when voltage is vicinity of 2.90 volts + Lvd0IrqReleaseVoltage300 = 16u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd0IrqReleaseVoltage310 = 17u, ///< Interrupt when voltage is vicinity of 3.10 volts + Lvd0IrqReleaseVoltage320 = 18u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqReleaseVoltage330 = 19u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd0IrqReleaseVoltageMax, ///< Max index of LVD interrupt voltage + +}en_lvd0_irq_release_voltage_t; +#endif + + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) +/** + ****************************************************************************** + ** \brief LVD ch.0 Reset voltage settings for Low Voltage Detection + ******************************************************************************/ +typedef enum en_lvd_reset_voltage +{ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) + LvdResetVoltage245 = 0u, ///< Interrupt when voltage is vicinity of 2.45 volts + LvdResetVoltage260 = 1u, ///< Interrupt when voltage is vicinity of 2.60 volts + LvdResetVoltage270 = 2u, ///< Interrupt when voltage is vicinity of 2.70 volts + LvdResetVoltage280 = 3u, ///< Interrupt when voltage is vicinity of 2.80 volts + LvdResetVoltage300 = 4u, ///< Interrupt when voltage is vicinity of 3.00 volts + LvdResetVoltage320 = 5u, ///< Interrupt when voltage is vicinity of 3.20 volts + LvdResetVoltage360 = 6u, ///< Interrupt when voltage is vicinity of 3.60 volts + LvdResetVoltage370 = 7u, ///< Interrupt when voltage is vicinity of 3.70 volts + LvdResetVoltage400 = 8u, ///< Interrupt when voltage is vicinity of 4.00 volts + LvdResetVoltage410 = 9u, ///< Interrupt when voltage is vicinity of 4.10 volts + LvdResetVoltage420 = 10u, ///< Interrupt when voltage is vicinity of 4.20 volts + LvdResetVoltageMax, ///< Max index of LVD reset voltage +#elif (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) + Lvd0ResetVoltage153 = 1u, ///< Interrupt when voltage is vicinity of 1.53 volts + Lvd0ResetVoltage193 = 4u, ///< Interrupt when voltage is vicinity of 1.93 volts + Lvd0ResetVoltageMax, ///< Max index of LVD reset voltage +#elif (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) + LvdResetVoltage150 = 0u, ///< Interrupt when voltage is vicinity of 1.50 volts + LvdResetVoltage155 = 1u, ///< Interrupt when voltage is vicinity of 1.55 volts + LvdResetVoltage160 = 2u, ///< Interrupt when voltage is vicinity of 1.60 volts + LvdResetVoltage165 = 3u, ///< Interrupt when voltage is vicinity of 1.65 volts + LvdResetVoltage170 = 4u, ///< Interrupt when voltage is vicinity of 1.70 volts + LvdResetVoltage175 = 5u, ///< Interrupt when voltage is vicinity of 1.75 volts + LvdResetVoltage180 = 6u, ///< Interrupt when voltage is vicinity of 1.80 volts + LvdResetVoltage185 = 7u, ///< Interrupt when voltage is vicinity of 1.85 volts + LvdResetVoltage190 = 8u, ///< Interrupt when voltage is vicinity of 1.90 volts + LvdResetVoltage195 = 9u, ///< Interrupt when voltage is vicinity of 1.95 volts + LvdResetVoltage200 = 10u, ///< Interrupt when voltage is vicinity of 2.00 volts + LvdResetVoltage205 = 11u, ///< Interrupt when voltage is vicinity of 2.05 volts + LvdResetVoltage250 = 12u, ///< Interrupt when voltage is vicinity of 2.50 volts + LvdResetVoltage260 = 13u, ///< Interrupt when voltage is vicinity of 2.60 volts + LvdResetVoltage270 = 14u, ///< Interrupt when voltage is vicinity of 2.70 volts + LvdResetVoltage280 = 15u, ///< Interrupt when voltage is vicinity of 2.80 volts + LvdResetVoltage290 = 16u, ///< Interrupt when voltage is vicinity of 2.90 volts + LvdResetVoltage300 = 17u, ///< Interrupt when voltage is vicinity of 3.00 volts + LvdResetVoltage310 = 18u, ///< Interrupt when voltage is vicinity of 3.10 volts + LvdResetVoltage320 = 19u, ///< Interrupt when voltage is vicinity of 3.20 volts + LvdResetVoltageMax, ///< Max index of LVD reset voltage +#endif + +}en_lvd_reset_voltage_t; +#endif + +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +/** + ****************************************************************************** + ** \brief LVD ch.1 Interruption voltage settings for Low Voltage Detection + ******************************************************************************/ +typedef enum en_lvd1_irq_detect_voltage +{ + Lvd1IrqDetectVoltage150 = 0u, ///< Interrupt when voltage is vicinity of 1.50 volts + Lvd1IrqDetectVoltage155 = 1u, ///< Interrupt when voltage is vicinity of 1.55 volts + Lvd1IrqDetectVoltage160 = 2u, ///< Interrupt when voltage is vicinity of 1.60 volts + Lvd1IrqDetectVoltage165 = 3u, ///< Interrupt when voltage is vicinity of 1.65 volts + Lvd1IrqDetectVoltage170 = 4u, ///< Interrupt when voltage is vicinity of 1.70 volts + Lvd1IrqDetectVoltage175 = 5u, ///< Interrupt when voltage is vicinity of 1.75 volts + Lvd1IrqDetectVoltage180 = 6u, ///< Interrupt when voltage is vicinity of 1.80 volts + Lvd1IrqDetectVoltage185 = 7u, ///< Interrupt when voltage is vicinity of 1.85 volts + Lvd1IrqDetectVoltage190 = 8u, ///< Interrupt when voltage is vicinity of 1.90 volts + Lvd1IrqDetectVoltage195 = 9u, ///< Interrupt when voltage is vicinity of 1.95 volts + Lvd1IrqDetectVoltage200 = 10u, ///< Interrupt when voltage is vicinity of 2.00 volts + Lvd1IrqDetectVoltage205 = 11u, ///< Interrupt when voltage is vicinity of 2.05 volts + Lvd1IrqDetectVoltage250 = 12u, ///< Interrupt when voltage is vicinity of 2.50 volts + Lvd1IrqDetectVoltage260 = 13u, ///< Interrupt when voltage is vicinity of 2.60 volts + Lvd1IrqDetectVoltage270 = 14u, ///< Interrupt when voltage is vicinity of 2.70 volts + Lvd1IrqDetectVoltage280 = 15u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd1IrqDetectVoltage290 = 16u, ///< Interrupt when voltage is vicinity of 2.90 volts + Lvd1IrqDetectVoltage300 = 17u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd1IrqDetectVoltage310 = 18u, ///< Interrupt when voltage is vicinity of 3.10 volts + Lvd1IrqDetectVoltage320 = 19u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd1IrqDetectVoltageMax, ///< Max index of LVD interrupt voltage + +} en_lvd1_irq_detect_voltage_t; +#endif + +/** + ****************************************************************************** + ** \brief LVD ch.1 Interruption release voltage settings for Low Voltage Detection + ******************************************************************************/ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +typedef enum en_lvd1_irq_release_voltage +{ + Lvd1IrqReleaseVoltage155 = 0u, ///< Interrupt when voltage is vicinity of 1.55 volts + Lvd1IrqReleaseVoltage160 = 1u, ///< Interrupt when voltage is vicinity of 1.60 volts + Lvd1IrqReleaseVoltage165 = 2u, ///< Interrupt when voltage is vicinity of 1.65 volts + Lvd1IrqReleaseVoltage170 = 3u, ///< Interrupt when voltage is vicinity of 1.70 volts + Lvd1IrqReleaseVoltage175 = 4u, ///< Interrupt when voltage is vicinity of 1.75 volts + Lvd1IrqReleaseVoltage180 = 5u, ///< Interrupt when voltage is vicinity of 1.80 volts + Lvd1IrqReleaseVoltage185 = 6u, ///< Interrupt when voltage is vicinity of 1.85 volts + Lvd1IrqReleaseVoltage190 = 7u, ///< Interrupt when voltage is vicinity of 1.90 volts + Lvd1IrqReleaseVoltage195 = 8u, ///< Interrupt when voltage is vicinity of 1.95 volts + Lvd1IrqReleaseVoltage200 = 9u, ///< Interrupt when voltage is vicinity of 2.00 volts + Lvd1IrqReleaseVoltage205 = 10u, ///< Interrupt when voltage is vicinity of 2.05 volts + Lvd1IrqReleaseVoltage250 = 11u, ///< Interrupt when voltage is vicinity of 2.50 volts + Lvd1IrqReleaseVoltage260 = 12u, ///< Interrupt when voltage is vicinity of 2.60 volts + Lvd1IrqReleaseVoltage270 = 13u, ///< Interrupt when voltage is vicinity of 2.70 volts + Lvd1IrqReleaseVoltage280 = 14u, ///< Interrupt when voltage is vicinity of 2.80 volts + Lvd1IrqReleaseVoltage290 = 15u, ///< Interrupt when voltage is vicinity of 2.90 volts + Lvd1IrqReleaseVoltage300 = 16u, ///< Interrupt when voltage is vicinity of 3.00 volts + Lvd1IrqReleaseVoltage310 = 17u, ///< Interrupt when voltage is vicinity of 3.10 volts + Lvd1IrqReleaseVoltage320 = 18u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd1IrqReleaseVoltage330 = 19u, ///< Interrupt when voltage is vicinity of 3.20 volts + Lvd1IrqReleaseVoltageMax, ///< Max index of LVD interrupt voltage + +}en_lvd1_irq_release_voltage_t; +#endif + +/** \} GroupLVD_Types */ + +/** +* \addtogroup GroupLVD_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Low Voltage Detection internal data + ******************************************************************************/ +typedef struct stc_lvd_intern_data +{ + func_ptr_t pfnIrqCallback[2]; ///< LVD interrupt callback function +} stc_lvd_intern_data_t ; + +/** + ****************************************************************************** + ** \brief Clock Supervisor configuration + ** + ** The Clock Supervisor configuration settings + ******************************************************************************/ +typedef struct stc_lvd_config +{ + en_lvd0_irq_detect_voltage_t enLvd0IrqDetectVoltage; ///< LVD ch.0 interrupt detect voltage, see #en_lvd0_irq_detect_voltage_t for details. +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + en_lvd0_irq_release_voltage_t enLvd0IrqReleaseVoltage; ///< LVD ch.0 interrupt release voltage, see #en_lvd0_irq_release_voltage_t for details. + boolean_t bLvd0ReleaseVoltageEnable; +#endif +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) + en_lvd_reset_voltage_t enLvdResetVoltage; ///< LVD reset voltage, see #en_lvd_reset_voltage_t for details. +#endif +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + en_lvd1_irq_detect_voltage_t enLvd1IrqDetectVoltage; ///< LVD ch.1 interrupt detect voltage, see #en_lvd1_irq_detect_voltage_t for details. + en_lvd1_irq_release_voltage_t enLvd1IrqReleaseVoltage; ///< LVD ch.1 interrupt release voltage, see #en_lvd1_irq_detect_voltage_t for details. + boolean_t bLvd1ReleaseVoltageEnable; +#endif + func_ptr_t pfnIrqCallback[2]; ///< LVD interrupt callback function +} stc_lvd_config_t; + +/** \} GroupLVD_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupLVD_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/* LVD Interupt IRQ */ +void Lvd_IrqHandler(void); + +/* Init/De-Init */ +en_result_t Lvd_Init(const stc_lvd_config_t* pstcConfig); +en_result_t Lvd_DeInit(void); + +/* Reset */ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) || (PDL_MCU_TYPE == PDL_FM0P_TYPE2) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE6) || (PDL_MCU_TYPE == PDL_FM3_TYPE8) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE9) || (PDL_MCU_TYPE == PDL_FM3_TYPE10) || \ + (PDL_MCU_TYPE == PDL_FM3_TYPE11) || (PDL_MCU_TYPE == PDL_FM3_TYPE12) +en_result_t Lvd_EnableReset(void); +en_result_t Lvd_DisableReset(void); +boolean_t Lvd_GetResetOperationStatus(void); +#endif + +/* Interrupt */ +en_result_t Lvd_EnableIrqDetect(uint8_t u8Channel); +en_result_t Lvd_DisableIrqDetect(uint8_t u8Channel); +boolean_t Lvd_GetIrqStatus(uint8_t u8Channel); +en_result_t Lvd_ClrIrqStatus(uint8_t u8Channel); +boolean_t Lvd_GetIrqOperationStatus(uint8_t u8Channel); + +/** \} GroupLVD_Functions */ +/** \} GroupLVD */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_LVD_ACTIVE)) */ + +#endif /* __LVD_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mfs/mfs.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mfs/mfs.c new file mode 100644 index 0000000000..0e4bf4e82e --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mfs/mfs.c @@ -0,0 +1,5097 @@ +/******************************************************************************* +* \file mfs.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the MFS +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mfs/mfs.h" + +#if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define UartInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&UART0)/0x100u +#define CsioInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&CSIO0)/0x100u +#define I2cInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&I2C0)/0x100u +#define LinInstanceToIndex(Instance) ((uint32_t)Instance - (uint32_t)&LIN0)/0x100u + + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled MFS instances and their internal data +stc_mfs_instance_data_t m_astcMfsInstanceDataLut[MFS_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS0_UART_BASE) + &UART0, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS0_CSIO_BASE) + &CSIO0, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS0_I2C_BASE) + &I2C0, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS0_LIN_BASE) + &LIN0 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS1_UART_BASE) + &UART1, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS1_CSIO_BASE) + &CSIO1, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS1_I2C_BASE) + &I2C1, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS1_LIN_BASE) + &LIN1 + #endif + }, /* pstcInstance */ + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS2_UART_BASE) + &UART2, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS2_CSIO_BASE) + &CSIO2, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS2_I2C_BASE) + &I2C2, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS2_LIN_BASE) + &LIN2 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS3_UART_BASE) + &UART3, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS3_CSIO_BASE) + &CSIO3, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS3_I2C_BASE) + &I2C3, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS3_LIN_BASE) + &LIN3 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS4_UART_BASE) + &UART4, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS4_CSIO_BASE) + &CSIO4, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS4_I2C_BASE) + &I2C4, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS4_LIN_BASE) + &LIN4 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS5_UART_BASE) + &UART5, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS5_CSIO_BASE) + &CSIO5, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS5_I2C_BASE) + &I2C5, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS5_LIN_BASE) + &LIN5 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS6_UART_BASE) + &UART6, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS6_CSIO_BASE) + &CSIO6, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS6_I2C_BASE) + &I2C6, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS6_LIN_BASE) + &LIN6 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS7_UART_BASE) + &UART7, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS7_CSIO_BASE) + &CSIO7, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS7_I2C_BASE) + &I2C7, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS7_LIN_BASE) + &LIN7 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS8_UART_BASE) + &UART8, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS8_CSIO_BASE) + &CSIO8, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS8_I2C_BASE) + &I2C8, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS8_LIN_BASE) + &LIN8 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS9_UART_BASE) + &UART9, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS9_CSIO_BASE) + &CSIO9, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS9_I2C_BASE) + &I2C9, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS9_LIN_BASE) + &LIN9 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS10_UART_BASE) + &UART10, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS10_CSIO_BASE) + &CSIO10, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS10_I2C_BASE) + &I2C10, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS10_LIN_BASE) + &LIN10 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS11_UART_BASE) + &UART11, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS11_CSIO_BASE) + &CSIO11, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS11_I2C_BASE) + &I2C11, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS11_LIN_BASE) + &LIN11 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS12_UART_BASE) + &UART12, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS12_CSIO_BASE) + &CSIO12, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS12_I2C_BASE) + &I2C12, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS12_LIN_BASE) + &LIN12 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS13_UART_BASE) + &UART13, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS13_CSIO_BASE) + &CSIO13, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS13_I2C_BASE) + &I2C13, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS13_LIN_BASE) + &LIN13 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS14_UART_BASE) + &UART14, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS14_CSIO_BASE) + &CSIO14, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS14_I2C_BASE) + &I2C14, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS14_LIN_BASE) + &LIN14 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) + { + { + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) && defined(FM_MFS15_UART_BASE) + &UART15, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) && defined(FM_MFS15_CSIO_BASE) + &CSIO15, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) && defined(FM_MFS15_I2C_BASE) + &I2C15, + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) && defined(FM_MFS15_LIN_BASE) + &LIN15 + #endif + }, // pstcInstance + { + MfsInitMode, // MFS initial mode + {{0u}}, // stcInternData (not initialized yet) + } + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +#if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) +static stc_mfs_intern_data_t* MfsUartGetInternDataPtr(volatile stc_mfsn_uart_t* pstcMfs); +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) +static stc_mfs_intern_data_t* MfsCsioGetInternDataPtr(volatile stc_mfsn_csio_t* pstcMfs); +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) +static stc_mfs_intern_data_t* MfsI2cGetInternDataPtr(volatile stc_mfsn_i2c_t* pstcMfs); +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) +static stc_mfs_intern_data_t* MfsLinGetInternDataPtr(volatile stc_mfsn_lin_t* pstcMfs); +#endif +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of transmit interrupts + ** according CMSIS with level defined in pdl.h + ** + ** \param u8Ch MFS channel + ** \param bRxTx FALSE: RX IRQ, TRUE: TX IRQ + ** + ******************************************************************************/ +static void MfsInitNvic(uint8_t u8Ch, boolean_t bRxTx) +{ + IRQn_Type enIrqIndex; + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + uint8_t au8PrioLevel[8] = + { + PDL_IRQ_LEVEL_MFS0, + PDL_IRQ_LEVEL_MFS1, + 0u, + PDL_IRQ_LEVEL_MFS3, + PDL_IRQ_LEVEL_MFS4, + 0u, + PDL_IRQ_LEVEL_MFS6_I2CS0, + PDL_IRQ_LEVEL_MFS7, + }; + + enIrqIndex = (IRQn_Type)(MFS0_RX_TX_IRQn + u8Ch); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch]); + NVIC_EnableIRQ(enIrqIndex); + +#else + uint8_t au8PrioLevel[16] = + { + PDL_IRQ_LEVEL_MFS0_RX, PDL_IRQ_LEVEL_MFS0_TX, + PDL_IRQ_LEVEL_MFS1_RX, PDL_IRQ_LEVEL_MFS1_TX, + PDL_IRQ_LEVEL_MFS2_RX, PDL_IRQ_LEVEL_MFS2_TX, + PDL_IRQ_LEVEL_MFS3_RX, PDL_IRQ_LEVEL_MFS3_TX, + PDL_IRQ_LEVEL_MFS4_RX, PDL_IRQ_LEVEL_MFS4_TX, + PDL_IRQ_LEVEL_MFS5_RX, PDL_IRQ_LEVEL_MFS5_TX, + PDL_IRQ_LEVEL_MFS6_RX_DMA0, PDL_IRQ_LEVEL_MFS6_TX_DMA1, + PDL_IRQ_LEVEL_MFS7_RX_DMA2, PDL_IRQ_LEVEL_MFS7_TX_DMA3 + }; + + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_RX_IRQn + u8Ch*2u); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch*2u]); + NVIC_EnableIRQ(enIrqIndex); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_TX_IRQn + u8Ch*2u ); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch*2u+1]); + NVIC_EnableIRQ(enIrqIndex); + } +#endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + uint8_t au8PrioLevel[16] = + { + PDL_IRQ_LEVEL_MFS0_8_RX, PDL_IRQ_LEVEL_MFS0_8_TX, + PDL_IRQ_LEVEL_MFS1_9_RX, PDL_IRQ_LEVEL_MFS1_9_TX, + PDL_IRQ_LEVEL_MFS2_10_RX, PDL_IRQ_LEVEL_MFS2_10_TX, + PDL_IRQ_LEVEL_MFS3_11_RX, PDL_IRQ_LEVEL_MFS3_11_TX, + PDL_IRQ_LEVEL_MFS4_12_RX, PDL_IRQ_LEVEL_MFS4_12_TX, + PDL_IRQ_LEVEL_MFS5_13_RX, PDL_IRQ_LEVEL_MFS5_13_TX, + PDL_IRQ_LEVEL_MFS6_14_RX, PDL_IRQ_LEVEL_MFS6_14_TX, + PDL_IRQ_LEVEL_MFS7_15_RX, PDL_IRQ_LEVEL_MFS7_15_TX, + }; + + if(8 <= u8Ch) + { + u8Ch = u8Ch - 8; + } + + #if defined(IRQ_MFS0_RX_AVAILABLE) + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_RX_IRQn + u8Ch*2u ); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch*2u]); + NVIC_EnableIRQ(enIrqIndex); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_TX_IRQn + u8Ch*2u ); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch*2u+1]); + NVIC_EnableIRQ(enIrqIndex); + } + #else + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_8_RX_IRQn + u8Ch*2u ); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch*2u]); + NVIC_EnableIRQ(enIrqIndex); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_8_TX_IRQn + u8Ch*2u ); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, au8PrioLevel[u8Ch*2u+1]); + NVIC_EnableIRQ(enIrqIndex); + } + #endif +#elif (PDL_MCU_CORE == PDL_FM4_CORE) + uint8_t au8PrioLevel0[16] = + { + PDL_IRQ_LEVEL_MFS0_RX, PDL_IRQ_LEVEL_MFS0_TX, + PDL_IRQ_LEVEL_MFS1_RX, PDL_IRQ_LEVEL_MFS1_TX, + PDL_IRQ_LEVEL_MFS2_RX, PDL_IRQ_LEVEL_MFS2_TX, + PDL_IRQ_LEVEL_MFS3_RX, PDL_IRQ_LEVEL_MFS3_TX, + PDL_IRQ_LEVEL_MFS4_RX, PDL_IRQ_LEVEL_MFS4_TX, + PDL_IRQ_LEVEL_MFS5_RX, PDL_IRQ_LEVEL_MFS5_TX, + PDL_IRQ_LEVEL_MFS6_RX, PDL_IRQ_LEVEL_MFS6_TX, + PDL_IRQ_LEVEL_MFS7_RX, PDL_IRQ_LEVEL_MFS7_TX, + + }; +#if (PDL_MCU_TYPE == PDL_FM4_TYPE3) + uint8_t au8PrioLevel1[8] = + { + PDL_IRQ_LEVEL_MFS8_RX, PDL_IRQ_LEVEL_MFS8_TX, + PDL_IRQ_LEVEL_MFS9_RX, PDL_IRQ_LEVEL_MFS9_TX, + PDL_IRQ_LEVEL_MFS10_RX, PDL_IRQ_LEVEL_MFS10_TX, + PDL_IRQ_LEVEL_MFS11_RX, PDL_IRQ_LEVEL_MFS11_TX, + }; + + uint8_t au8PrioLevel2[8] = + { + PDL_IRQ_LEVEL_MFS12_RX, PDL_IRQ_LEVEL_MFS12_TX, + PDL_IRQ_LEVEL_MFS13_RX, PDL_IRQ_LEVEL_MFS13_TX, + PDL_IRQ_LEVEL_MFS14_RX, PDL_IRQ_LEVEL_MFS14_TX, + PDL_IRQ_LEVEL_MFS15_RX, PDL_IRQ_LEVEL_MFS15_TX, + }; +#elif (PDL_MCU_TYPE == PDL_FM4_TYPE5) + uint8_t au8PrioLevel1[4] = + { + PDL_IRQ_LEVEL_MFS8_RX, PDL_IRQ_LEVEL_MFS8_TX, + PDL_IRQ_LEVEL_MFS9_RX, PDL_IRQ_LEVEL_MFS9_TX, + }; +#endif + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_RX_IRQn + (2u * u8Ch)); + if(u8Ch < 8u) + { + NVIC_SetPriority(enIrqIndex, au8PrioLevel0[u8Ch*2u]); + } + #if ((PDL_MCU_TYPE == PDL_FM4_TYPE3) || (PDL_MCU_TYPE == PDL_FM4_TYPE5)) + else if((u8Ch >= 8u) && (u8Ch < 12u)) + { + enIrqIndex = (IRQn_Type)(MFS8_RX_IRQn + 2u * (u8Ch - 8u)); + NVIC_SetPriority(enIrqIndex, au8PrioLevel1[2u * (u8Ch - 8u)]); + } + #endif + #if (PDL_MCU_TYPE == PDL_FM4_TYPE3) + else if((u8Ch >= 12u) && (u8Ch < 16u)) + { + enIrqIndex = (IRQn_Type)(MFS12_RX_IRQn + 2u * (u8Ch - 12u)); + NVIC_SetPriority(enIrqIndex, au8PrioLevel2[2u * (u8Ch - 12u)]); + } + + #endif + else + { + return; + } + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_EnableIRQ(enIrqIndex); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_TX_IRQn + 2u * u8Ch); + if(u8Ch < 8u) + { + NVIC_SetPriority(enIrqIndex, au8PrioLevel0[(2u * u8Ch) + 1u]); + } + #if (PDL_MCU_TYPE == PDL_FM4_TYPE3) || (PDL_MCU_TYPE == PDL_FM4_TYPE5) + else if((u8Ch >= 8u) && (u8Ch < 12u)) + { + enIrqIndex = (IRQn_Type)(MFS8_TX_IRQn + 2u * (u8Ch - 8u)); + NVIC_SetPriority(enIrqIndex, au8PrioLevel1[2u * (u8Ch - 8u) + 1u]); + } + #endif + #if (PDL_MCU_TYPE == PDL_FM4_TYPE3) + else if((u8Ch >= 12u) && (u8Ch < 16u)) + { + enIrqIndex = (IRQn_Type)(MFS12_TX_IRQn + 2u * (u8Ch - 12u)); + NVIC_SetPriority(enIrqIndex, au8PrioLevel2[2u * (u8Ch - 12u) + 1u]); + } + #endif + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_EnableIRQ(enIrqIndex); + } +#endif + +} /* Mfs_InitTxIrq */ + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ** \param u8Ch MFS channel + ** \param bRxTx FALSE: RX IRQ, TRUE: TX IRQ + ** + ******************************************************************************/ +static void MfsDeInitNvic(uint8_t u8Ch, boolean_t bRxTx) +{ + IRQn_Type enIrqIndex; + +#if (PDL_MCU_CORE == PDL_FM3_CORE) + + if(8 <= u8Ch) + { + u8Ch = u8Ch - 8; + } + + #if defined(IRQ_MFS0_RX_AVAILABLE) + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_RX_IRQn + 2 * u8Ch); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_TX_IRQn + 2 * u8Ch); + + } + #else + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_8_RX_IRQn + 2 * u8Ch); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_8_TX_IRQn + 2 * u8Ch); + + } + #endif + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_DisableIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + enIrqIndex = (IRQn_Type)(MFS0_RX_TX_IRQn + u8Ch); + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_DisableIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + if(FALSE == bRxTx) + { + enIrqIndex = (IRQn_Type)(MFS0_RX_IRQn + 2 * u8Ch); + } + else + { + enIrqIndex = (IRQn_Type)(MFS0_TX_IRQn + 2 * u8Ch); + + } + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_DisableIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +#elif (PDL_MCU_CORE == PDL_FM4_CORE) + if(FALSE == bRxTx) + { + if(u8Ch < 8u) + { + enIrqIndex = (IRQn_Type)(MFS0_RX_IRQn + 2u * u8Ch); + } + #if ((PDL_MCU_TYPE == PDL_FM4_TYPE3) || (PDL_MCU_TYPE == PDL_FM4_TYPE5)) + else if((u8Ch >= 8u) && (u8Ch < 12u)) + { + enIrqIndex = (IRQn_Type)(MFS8_RX_IRQn + 2u * (u8Ch - 8u)); + } + #endif + #if (PDL_MCU_TYPE == PDL_FM4_TYPE3) + else if((u8Ch >= 12u) && (u8Ch < 16u)) + { + enIrqIndex = (IRQn_Type)(MFS12_RX_IRQn + 2u * (u8Ch - 12u)); + } + #endif + else + { + return; + } + } + else + { + if(u8Ch < 8u) + { + enIrqIndex = (IRQn_Type)(MFS0_TX_IRQn + 2 * u8Ch); + } + #if (PDL_MCU_TYPE == PDL_FM4_TYPE3) || (PDL_MCU_TYPE == PDL_FM4_TYPE5) + else if((u8Ch >= 8u) && (u8Ch < 12u)) + { + enIrqIndex = (IRQn_Type)(MFS8_TX_IRQn + 2u * (u8Ch - 8u)); + } + #endif + #if (PDL_MCU_TYPE == PDL_FM4_TYPE3) + else if((u8Ch >= 12u) && (u8Ch < 16u)) + { + enIrqIndex = (IRQn_Type)(MFS12_TX_IRQn + 2u * (u8Ch - 12u)); + } + #endif + else + { + return; + } + } + + NVIC_ClearPendingIRQ(enIrqIndex); + NVIC_DisableIRQ(enIrqIndex); + NVIC_SetPriority(enIrqIndex, PDL_DEFAULT_INTERRUPT_LEVEL); + +#endif + +} /* Mfs_DeInitIrq */ + +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) +/****************************************************************************** + * UART driver functions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief Return the internal data for a certain UART instance. + ** + ** \param pstcUart Pointer to UART instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_mfs_intern_data_t* MfsUartGetInternDataPtr(volatile stc_mfsn_uart_t* pstcUart) +{ + stc_mfs_intern_data_t* pstcInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcUart) + { + for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) + { + if (pstcUart == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcUartInstance) + { + pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; + break; + } + } + + } + + return (pstcInternDataPtr); +} /* MfsGetInternDataPtr */ + + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +/** + ****************************************************************************** + ** \brief UART receive interrupt service routine. + ** + ** \param pstcUart Pointer to UART instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Receive Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsUartIrqHandlerRx( volatile stc_mfsn_uart_t* pstcUart, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcUart) && (NULL != pstcMfsInternData)) + { + if (NULL != pstcMfsInternData->stcUartInternIrqCb.pfnRxIrqCb) + { + pstcMfsInternData->stcUartInternIrqCb.pfnRxIrqCb(); + } + } +} /* MfsIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief MFS transmit interrupt service routine. + ** + ** \param pstcUart Pointer to UART instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Transmit Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsUartIrqHandlerTx( volatile stc_mfsn_uart_t* pstcUart, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcUart) && (NULL != pstcMfsInternData)) + { + if(1u == pstcUart->SSR_f.TDRE) + { + if (NULL != pstcMfsInternData->stcUartInternIrqCb.pfnTxIrqCb) + { + pstcMfsInternData->stcUartInternIrqCb.pfnTxIrqCb(); + } + } + + if(1u == pstcUart->SSR_f.TBI) + { + if (NULL != pstcMfsInternData->stcUartInternIrqCb.pfnTxIdleCb) + { + pstcMfsInternData->stcUartInternIrqCb.pfnTxIdleCb(); + } + } + + if(1u == pstcUart->FCR_f.FDRQ) + { + if (NULL != pstcMfsInternData->stcUartInternIrqCb.pfnTxFifoIrqCb) + { + pstcMfsInternData->stcUartInternIrqCb.pfnTxFifoIrqCb(); + } + + pstcUart->FCR_f.FDRQ = 0u; + } + } +} /* MfsIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief Enable one interrupt source of UART + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enIrqSel Pointer to the selection structure of UART interrupt + ** \arg UartTxIrq UART TX interrupt + ** \arg UartRxIrq UART RX interrupt + ** \arg UartTxIdleIrq UART TX idle interrupt + ** \arg UartTxFifoIrq UART TX FIFO interrupt + ** + ** \retval Ok Interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mfs_Uart_EnableIrq(volatile stc_mfsn_uart_t* pstcUart, + en_uart_irq_sel_t enIrqSel) +{ + if (NULL == pstcUart) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case UartTxIrq: + pstcUart->SCR_f.TIE = 1u; + break; + case UartRxIrq: + pstcUart->SCR_f.RIE = 1u; + break; + case UartTxIdleIrq: + pstcUart->SCR_f.TBIE = 1u; + break; + case UartTxFifoIrq: + pstcUart->FCR_f.FTIE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable one interrupt source of UART + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enIrqSel Pointer to the selection structure of UART interrupt + ** \arg UartTxIrq UART TX interrupt + ** \arg UartRxIrq UART RX interrupt + ** \arg UartTxIdleIrq UART TX idle interrupt + ** \arg UartTxFifoIrq UART TX FIFO interrupt + ** + ** \retval Ok Interrupts has been disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mfs_Uart_DisableIrq(volatile stc_mfsn_uart_t* pstcUart, + en_uart_irq_sel_t enIrqSel) +{ + if (NULL == pstcUart) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case UartTxIrq: + pstcUart->SCR_f.TIE = 0u; + break; + case UartRxIrq: + pstcUart->SCR_f.RIE = 0u; + break; + case UartTxIdleIrq: + pstcUart->SCR_f.TBIE = 0u; + break; + case UartTxFifoIrq: + pstcUart->FCR_f.FTIE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialization of a MFS module to activate as UART. + ** + ** Set registers to active MFS as UART. + ** + ** \param [in] pstcUart Pointer to UART instance register area + ** \param [in] pstcConfig MFS UART configuration + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Uart_Init(volatile stc_mfsn_uart_t* pstcUart, + const stc_mfs_uart_config_t* pstcConfig) +{ + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Preset local register variables to zero */ + stc_mfs_uart_smr_field_t stcSMR; + stc_mfs_uart_scr_field_t stcSCR; + stc_mfs_uart_escr_field_t stcESCR; + + PDL_ZERO_STRUCT(stcSMR); + PDL_ZERO_STRUCT(stcSCR); + PDL_ZERO_STRUCT(stcESCR); + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsUartGetInternDataPtr(pstcUart); + + /* Parameter check and get ptr to internal data struct */ + if ((NULL == pstcMfsInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* Calculate the channel number */ + u8Ch = UartInstanceToIndex(pstcUart); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Set the MFS mode in the internal structure */ + pstcMfsInternData->enMode = MfsUartMode; + + /* Set UART mode */ + switch (pstcConfig->enMode) + { + case UartNormal: + stcSMR.MD = 0u; /* Normal mode */ + break; + case UartMulti: + stcSMR.MD = 1u; /* Multi-processor mode */ + break; + default: + return (ErrorInvalidParameter); + } + + /* Enable SOE */ + stcSMR.SOE = TRUE; + /* Set Parity */ + switch(pstcConfig->enParity) + { + case UartParityNone: + stcESCR.P = FALSE; /* Parity type selection (0-even/1-odd) */ + stcESCR.PEN = FALSE; /* Parity disable */ + break; + case UartParityEven: + stcESCR.P = FALSE; /* Parity type selection (0-even/1-odd) */ + stcESCR.PEN = TRUE; /* Parity Enable */ + break; + case UartParityOdd: + stcESCR.P = TRUE; /* Parity type selection (0-even/1-odd) */ + stcESCR.PEN = TRUE; /* Parity Enable */ + break; + default: + return (ErrorInvalidParameter); + } + /* Set Stop bit length */ + switch (pstcConfig->enStopBit) + { + case UartOneStopBit: + stcSMR.SBL = FALSE; + stcESCR.ESBL = FALSE; + break; + case UartTwoStopBits: + stcSMR.SBL = TRUE; + stcESCR.ESBL = FALSE; + break; + case UartThreeStopBits: + stcSMR.SBL = FALSE; + stcESCR.ESBL = TRUE; + break; + case UartFourStopBits: + stcSMR.SBL = TRUE; + stcESCR.ESBL = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + /* Set Data bit length (5 - 9bits) */ + switch(pstcConfig->enDataLength) + { + case UartFiveBits: + stcESCR.L = UartFiveBits; + break; + case UartSixBits: + stcESCR.L = UartSixBits; + break; + case UartSevenBits: + stcESCR.L = UartSevenBits; + break; + case UartEightBits: + stcESCR.L = UartEightBits; + break; + case UartNineBits: + stcESCR.L = UartNineBits; + break; + default: + return (ErrorInvalidParameter); + } + /* Set Bit direction (LSB/MSB) */ + switch(pstcConfig->enBitDirection) + { + case UartDataLsbFirst: + stcSMR.BDS = 0; + break; + case UartDataMsbFirst: + stcSMR.BDS = 1; + break; + default: + return ErrorInvalidParameter; + } + + /* HW Flow */ + if (TRUE == pstcConfig->bHwFlow) + { + stcESCR.FLWEN = TRUE; + } + else + { + stcESCR.FLWEN = FALSE; + } + + /* Set Signal system (NRZ/Int-NRZ) */ + if (TRUE == pstcConfig->bInvertData) + { + stcESCR.INV = TRUE; + } + else + { + stcESCR.INV = FALSE; + } + + + /* Clear MFS by setting the Software Reset bit */ + pstcUart->SCR_f.UPCL = TRUE; + + /* Set Baudrate */ + (void)Mfs_Uart_SetBaudRate(pstcUart, pstcConfig->u32BaudRate); + /* Set registers value */ + pstcUart->SMR_f = stcSMR; + pstcUart->SCR_f = stcSCR; + pstcUart->ESCR_f = stcESCR; + + /* Set external clock */ + pstcUart->BGR_f.EXT = ((pstcConfig->bUseExtClk == TRUE) ? 1u : 0u); + + /* Configue FIFO */ + if(pstcConfig->pstcFifoConfig != NULL) + { + /* Reset FIFO */ + pstcUart->FCR_f.FCL1 = 1; + pstcUart->FCR_f.FCL2 = 1; + /* Enable FIFO receive Idle detection */ + pstcUart->FCR_f.FRIIE = 1u; + /* Selection TX and RX FIFO */ + switch(pstcConfig->pstcFifoConfig->enFifoSel) + { + case MfsTxFifo1RxFifo2: + pstcUart->FCR_f.FSEL = 0u; + break; + case MfsTxFifo2RxFifo1: + pstcUart->FCR_f.FSEL = 1u; + break; + default: + return (ErrorInvalidParameter); + } + /* Set FIFO count */ + pstcUart->FBYTE1 = pstcConfig->pstcFifoConfig->u8ByteCount1; + pstcUart->FBYTE2 = pstcConfig->pstcFifoConfig->u8ByteCount2; + /* Enable FIFO */ + pstcUart->FCR_f.FE1 = 1u; + pstcUart->FCR_f.FE2 = 1u; + } + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + /* Configue interrupts */ + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bRxIrq) + { + + pstcUart->SCR_f.RIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxIrq) + { + + pstcUart->SCR_f.TIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxIdleIrq) + { + + pstcUart->SCR_f.TBIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxFifoIrq) + { + + pstcUart->FCR_f.FTIE = 1u; + } + } + + /* Configure callback functions */ + if(NULL != pstcConfig->pstcIrqCb) + { + pstcMfsInternData->stcUartInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcMfsInternData->stcUartInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcMfsInternData->stcUartInternIrqCb.pfnTxIdleCb = pstcConfig->pstcIrqCb->pfnTxIdleCb; + pstcMfsInternData->stcUartInternIrqCb.pfnTxFifoIrqCb = pstcConfig->pstcIrqCb->pfnTxFifoIrqCb; + } + + /* Configure NVIC */ + if(TRUE == pstcConfig->bTouchNvic) + { + MfsInitNvic(u8Ch, FALSE); + MfsInitNvic(u8Ch, TRUE); + } +#endif + + return (Ok); +} /* MFS_Uart_Init */ + +/** + ****************************************************************************** + ** \brief Deinitialisation of a MFS module activating as UART. + ** + ** All used uart register are reset to their default values. + ** + ** \param [in] pstcUart Pointer to UART instance register area + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Uart_DeInit(volatile stc_mfsn_uart_t* pstcUart, boolean_t bTouchNvic) +{ + en_result_t enResult; + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Calculate the channel number */ + u8Ch = UartInstanceToIndex(pstcUart); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsUartGetInternDataPtr(pstcUart); + /* ... and check */ + if (NULL == pstcMfsInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + pstcUart->SCR_f.TXE = FALSE; + pstcUart->SCR_f.RXE = FALSE; + + /* Baud Rate Generation Reload Reset */ + pstcUart->BGR = 0u; + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcUart->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcUart->SCR = 0u; + + /* Clear reception Errors */ + pstcUart->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcUart->SSR = 0u; + pstcUart->ESCR = 0u; + pstcUart->FCR = 0u; + + + /* Clear MFS by setting the Software Reset bit */ + pstcUart->SCR_f.UPCL = TRUE; + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + /* Disable NVIC */ + if(TRUE == bTouchNvic) + { + MfsDeInitNvic(u8Ch, FALSE); + MfsDeInitNvic(u8Ch, TRUE); + } +#endif + enResult = Ok; + } + + return (enResult); +} /* Mfs_Uart_DeInit */ + +/** + ****************************************************************************** + ** \brief Set the baudrate of UART + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] u32BaudRate Baudrate value [bps] + ** + ** \retval Ok UART baud rate has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - u32BaudRate < 4 + ** \note + ** The UART baud rate can be initialized in the Mfs_Uart_Init() and be modified + ** in the funciton. + ** + ******************************************************************************/ +en_result_t Mfs_Uart_SetBaudRate(volatile stc_mfsn_uart_t* pstcUart, + uint32_t u32BaudRate) +{ + uint32_t u32Pclk1; + + SystemCoreClockUpdate(); + if ((NULL == pstcUart) || (u32BaudRate < 4u)) + { + return ErrorInvalidParameter; + } + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + u32Pclk1 = SystemCoreClock / (1ul << (FM_CRG->APBC1_PSR & 0x03u)); /* MFS is attached on APB1 bus in FM0+ device */ +#else + u32Pclk1 = SystemCoreClock / (1ul << (FM_CRG->APBC2_PSR & 0x03u)); /* MFS is attached on APB2 bus in FM3, FM4 device */ +#endif + pstcUart->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable UART functions + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enFunc UART function types + ** \arg UartTx UART transfer function + ** \arg UartRx UART receive function + ** + ** \retval Ok Function has been enabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mfs_Uart_EnableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc) +{ + if (NULL == pstcUart) + { + return ErrorInvalidParameter; + } + + switch(enFunc) + { + case UartTx: + pstcUart->SCR_f.TXE = 1u; + break; + case UartRx: + pstcUart->SCR_f.RXE = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable UART functions + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enFunc UART function types + ** \arg UartTx UART transfer function + ** \arg UartRx UART receive function + ** + ** \retval Ok Function has been disabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mfs_Uart_DisableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc) +{ + if (NULL == pstcUart) + { + return ErrorInvalidParameter; + } + + switch(enFunc) + { + case UartTx: + pstcUart->SCR_f.TXE = 0u; + break; + case UartRx: + pstcUart->SCR_f.RXE = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get status of UART according to status type + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enStatus UART status type + ** \arg UartParityError UART parity error + ** \arg UartFrameError UART frame error + ** \arg UartRxFull UART receive buffer full + ** \arg UartTxEmpty UART tranfer buffer empty + ** \arg UartTxIdle UART tranfer idle status + ** \arg UartTxFifoRequest UART transfer FIFO request + ** + ** \retval FALSE If one of following conditions are met: + ** - No UART parity error [enStatus = UartParityError] + ** - No UART frame error [enStatus = UartFrameError] + ** - UART receive buffer is not full [enStatus = UartRxFull] + ** - UART tranfer buffer is not empty [enStatus = UartTxEmpty] + ** - UART tranfer is on-going [enStatus = UartTxIdle] + ** - No UART transfer FIFO request [enStatus = UartTxFifoRequest] + ** \retval TRUE If one of following conditions are met: + ** - UART parity error occurs [enStatus = UartParityError] + ** - UART frame error occurs [enStatus = UartFrameError] + ** - UART receive buffer is full [enStatus = UartRxFull] + ** - UART tranfer buffer is empty [enStatus = UartTxEmpty] + ** - UART tranfer is idle [enStatus = UartTxIdle] + ** - UART transfer FIFO request issues [enStatus = UartTxFifoRequest] + ** + ******************************************************************************/ +boolean_t Mfs_Uart_GetStatus(volatile stc_mfsn_uart_t* pstcUart, + en_uart_status_t enStatus) +{ + boolean_t bResult = FALSE; + + switch(enStatus) + { + case UartParityError: + bResult = (pstcUart->SSR_f.PE == 1u) ? TRUE : FALSE; + break; + case UartFrameError: + bResult = (pstcUart->SSR_f.FRE == 1u) ? TRUE : FALSE; + break; + case UartOverrunError: + bResult = (pstcUart->SSR_f.ORE == 1u) ? TRUE : FALSE; + break; + case UartRxFull: + bResult = (pstcUart->SSR_f.RDRF == 1u) ? TRUE : FALSE; + break; + case UartTxEmpty: + bResult = (pstcUart->SSR_f.TDRE == 1u) ? TRUE : FALSE; + break; + case UartTxIdle: + bResult = (pstcUart->SSR_f.TBI == 1u) ? TRUE : FALSE; + break; + case UartTxFifoRequest: + bResult = (pstcUart->FCR_f.FDRQ == 1u) ? TRUE : FALSE; + break; + default: + break; + } + + return bResult; +} + +/** + ****************************************************************************** + ** \brief Clear status of UART according to status type + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enStatus UART status type + ** \arg UartParityError UART parity error + ** \arg UartFrameError UART frame error + ** \arg UartRxFull UART receive buffer full + ** \arg UartTxEmpty UART tranfer buffer empty + ** \arg UartTxIdle UART tranfer idle status + ** \arg UartTxFifoRequest UART transfer FIFO request + ** + ** \retval Ok Status has been cleared normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** \note The following status can only be cleared by hardware behavior: + ** - UartRxFull + ** - UartTxEmpty + ** - UartTxIdle + ** + ******************************************************************************/ +en_result_t Mfs_Uart_ClrStatus(volatile stc_mfsn_uart_t* pstcUart, + en_uart_status_t enStatus) +{ + if (NULL == pstcUart) + { + return ErrorInvalidParameter; + } + + switch(enStatus) + { + case UartParityError: + case UartFrameError: + case UartOverrunError: + pstcUart->SSR_f.REC = 1u; + break; + case UartRxFull: + case UartTxEmpty: + case UartTxIdle: + break; + case UartTxFifoRequest: + pstcUart->FCR_f.FDRQ = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write UART data buffer + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] u16Data Send data + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Uart_SendData(volatile stc_mfsn_uart_t* pstcUart, uint16_t u16Data) +{ + if (NULL == pstcUart) + { + return ErrorInvalidParameter; + } + + pstcUart->TDR = u16Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read UART data buffer + ** + ** \param [in] pstcUart Pointer to UART instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t Mfs_Uart_ReceiveData(volatile stc_mfsn_uart_t* pstcUart) +{ + return (pstcUart->RDR); +} + +/** + ****************************************************************************** + ** \brief Reset UART FIFO + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval Ok FIFO has been successfully reset + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Uart_ResetFifo (volatile stc_mfsn_uart_t* pstcUart, + en_mfs_fifo_t enFifo) +{ + if (NULL == pstcUart) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcUart->FCR_f.FCL1 = 1u; + break; + case MfsFifo2: + pstcUart->FCR_f.FCL2 = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set UART FIFO count + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** \param [in] u8Count FIFO count + ** + ** \retval Ok FIFO count has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Uart_SetFifoCount(volatile stc_mfsn_uart_t* pstcUart, + en_mfs_fifo_t enFifo, + uint8_t u8Count) +{ + if (NULL == pstcUart) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcUart->FBYTE1 = u8Count; + break; + case MfsFifo2: + pstcUart->FBYTE2 = u8Count; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get UART FIFO count + ** + ** \param [in] pstcUart Pointer to UART instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval FIFO count + ** + ** This function gets the current data count in selected FIFO. + ** + ** \note 0xFF will be return value if FIFO index is error. + ** + ******************************************************************************/ +uint8_t Mfs_Uart_GetFifoCount(volatile stc_mfsn_uart_t* pstcUart, + en_mfs_fifo_t enFifo) +{ + uint8_t u8FifoCnt = 0xFFu; + + switch(enFifo) + { + case MfsFifo1: + u8FifoCnt = pstcUart->FBYTE1; + break; + case MfsFifo2: + u8FifoCnt = pstcUart->FBYTE2; + break; + default: + break; + } + + return u8FifoCnt; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) +/****************************************************************************** + * CSIO driver functions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain CSIO instance. + ** + ** \param pstcCsio Pointer to CSIO instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_mfs_intern_data_t* MfsCsioGetInternDataPtr(volatile stc_mfsn_csio_t* pstcCsio) +{ + stc_mfs_intern_data_t* pstcInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcCsio) + { + for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) + { + if (pstcCsio == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcCsioInstance) + { + pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; + break; + } + } + + } + + return (pstcInternDataPtr); +} /* MfsGetInternDataPtr */ + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +/** + ****************************************************************************** + ** \brief CSIO receive interrupt service routine. + ** + ** \param pstcCsio Pointer to CSIO instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Receive Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsCsioIrqHandlerRx( volatile stc_mfsn_csio_t* pstcCsio, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcCsio) && (NULL != pstcMfsInternData)) + { + if (NULL != pstcMfsInternData->stcCsioInternIrqCb.pfnRxIrqCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnRxIrqCb(); + } + } +} /* MfsCsioIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief CSIO transfer interrupt service routine. + ** + ** \param pstcCsio Pointer to CSIO instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on transfer Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsCsioIrqHandlerTx( volatile stc_mfsn_csio_t* pstcCsio, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcCsio) && (NULL != pstcMfsInternData)) + { + if(1u == pstcCsio->SSR_f.TDRE) + { + if (NULL != pstcMfsInternData->stcCsioInternIrqCb.pfnTxIrqCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnTxIrqCb(); + } + } + + if(1u == pstcCsio->SSR_f.TBI) + { + if (NULL != pstcMfsInternData->stcCsioInternIrqCb.pfnTxIdleCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnTxIdleCb(); + } + } + + if(1u == pstcCsio->FCR_f.FDRQ) + { + if (NULL != pstcMfsInternData->stcCsioInternIrqCb.pfnTxFifoIrqCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnTxFifoIrqCb(); + } + + pstcCsio->FCR_f.FDRQ = 0u; + } + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if(1u == pstcCsio->SACSR_f.CSE) + { + if (NULL != pstcMfsInternData->stcCsioInternIrqCb.pfnCsErrIrqCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnCsErrIrqCb(); + } + + pstcCsio->SACSR_f.CSE = 0u; + } + #endif + + } +} /* MfsIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief CSIO status interrupt service routine. + ** + ** \param pstcCsio Pointer to CSIO instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on transfer Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsCsioIrqHandlerStatus( volatile stc_mfsn_csio_t* pstcCsio, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcCsio) && (NULL != pstcMfsInternData)) + { + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + if(1u == pstcCsio->SACSR_f.TINT) + { + if (NULL != pstcMfsInternData->stcCsioInternIrqCb.pfnSerialTimerIrqCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnSerialTimerIrqCb(); + } + + pstcCsio->SACSR_f.TINT = 0u; + } + #endif + } +} + +/** + ****************************************************************************** + ** \brief Enable CSIO interrupts + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enIrqSel CSIO interrupt selection + ** \arg CsioTxIrq TX interrupt of CSIO + ** \arg CsioRxIrq RX interrupt of CSIO + ** \arg CsioTxIdleIrq TX idle interrupt of CSIO + ** \arg CsioTxFifoIrq TX FIFO interrupt of CSIO + ** \arg CsioCsErrIrq Chip selection error interrupt of CSIO + ** \arg CsioSerialTimerIrq Seriel timer interrupt of CSIO + ** + ** \retval Ok Interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - enIrqSel == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_EnableIrq(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_irq_sel_t enIrqSel) +{ + stc_mfs_intern_data_t* pstcMfsInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); + + if (NULL == pstcMfsInternData) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case CsioTxIrq: + pstcCsio->SCR_f.TIE = 1u; + break; + case CsioRxIrq: + pstcCsio->SCR_f.RIE = 1u; + break; + case CsioTxIdleIrq: + pstcCsio->SCR_f.TBIE = 1u; + break; + case CsioTxFifoIrq: + pstcCsio->FCR_f.FTIE = 1u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case CsioCsErrIrq: + pstcCsio->SACSR_f.CSEIE = 1u; + break; + case CsioSerialTimerIrq: + pstcCsio->SACSR_f.TINTE = 1u; + break; + #endif + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable CSIO interrupts + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enIrqSel CSIO interrupt type + ** \arg CsioTxIrq TX interrupt of CSIO + ** \arg CsioRxIrq RX interrupt of CSIO + ** \arg CsioTxIdleIrq TX idle interrupt of CSIO + ** \arg CsioTxFifoIrq TX FIFO interrupt of CSIO + ** \arg CsioCsErrIrq Chip selection error interrupt of CSIO + ** \arg CsioSerialTimerIrq Seriel timer interrupt of CSIO + ** + ** \retval Ok Interrupts has been disabled and callback + ** fucntion pointers are set to NULL + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - pstcInt == NULL + ** + ** The NVIC IRQ is also disabled in this function. + ** + ******************************************************************************/ +en_result_t Mfs_Csio_DisableIrq(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_irq_sel_t enIrqSel) +{ + if (NULL == pstcCsio) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case CsioTxIrq: + pstcCsio->SCR_f.TIE = 0u; + break; + case CsioRxIrq: + pstcCsio->SCR_f.RIE = 0u; + break; + case CsioTxIdleIrq: + pstcCsio->SCR_f.TBIE = 0u; + break; + case CsioTxFifoIrq: + pstcCsio->FCR_f.FTIE = 0u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case CsioCsErrIrq: + pstcCsio->SACSR_f.CSEIE = 0u; + break; + case CsioSerialTimerIrq: + pstcCsio->SACSR_f.TINTE = 0u; + break; + #endif + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialization of a MFS module to activate as CSIO. + ** + ** Set registers to active MFS as CSIO. + ** + ** \param [in] pstcCsio Pointer to CSIO instance register area + ** \param [in] pstcConfig MFS CSIO configuration + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Csio_Init(volatile stc_mfsn_csio_t* pstcCsio, + const stc_mfs_csio_config_t* pstcConfig) +{ + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Preset local register variables to zero */ + stc_mfs_csio_smr_field_t stcSMR; + stc_mfs_csio_scr_field_t stcSCR; + stc_mfs_csio_ssr_field_t stcSSR; + stc_mfs_csio_escr_field_t stcESCR; + + PDL_ZERO_STRUCT(stcSMR); + PDL_ZERO_STRUCT(stcSCR); + PDL_ZERO_STRUCT(stcSSR); + PDL_ZERO_STRUCT(stcESCR); + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); + + /* Parameter check and get ptr to internal data struct */ + if ((NULL == pstcMfsInternData) + || (NULL == pstcConfig)) + { + return (ErrorInvalidParameter); + } + + /* Calculate the channel number */ + u8Ch = CsioInstanceToIndex(pstcCsio); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Set MFS mode in the internal structure */ + pstcMfsInternData->enMode = MfsCsioMode; + + /* Set CSIO mode */ + stcSMR.MD = 2u; + + /* Set master/slave mode */ + switch(pstcConfig->enMsMode) + { + case CsioMaster: + stcSCR.MS = FALSE; /* Master mode */ + /* Enable SOE */ + stcSMR.SOE = TRUE; + /* Enable SCKE */ + stcSMR.SCKE = TRUE; + break; + case CsioSlave: + stcSCR.MS = TRUE; /* Slave mode */ + /* Enable SOE */ + stcSMR.SOE = TRUE; + /* Enable SCKE */ + stcSMR.SCKE = FALSE; /* Disable clock output in slave mode */ + break; + default: + return ErrorInvalidParameter; + } + + + + /* Set normal/SPI mode */ + switch (pstcConfig->enActMode) + { + case CsioActNormalMode: + stcSCR.SPI = FALSE; /* Normal mode */ + break; + case CsioActSpiMode: + stcSCR.SPI = TRUE; /* SPI mode */ + break; + default: + return (ErrorInvalidParameter); + } + + /* Wait time insertion */ + switch(pstcConfig->enSyncWaitTime) + { + case CsioSyncWaitZero: + stcESCR.WT = 0u; /* 0bit */ + break; + case CsioSyncWaitOne: + stcESCR.WT = 1u; /* 1bit */ + break; + case CsioSyncWaitTwo: + stcESCR.WT = 2u; /* 2bits */ + break; + case CsioSyncWaitThree: + stcESCR.WT = 3u; /* 3bits */ + break; + default: + return (ErrorInvalidParameter); + } +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + stcESCR.L3 = 0u; /* Default:less than 13 bits */ +#endif + + /* Set Data bit length (5-16,20,24,32 bits) */ + switch (pstcConfig->enDataLength) + { + case CsioFiveBits: + stcESCR.L = 1u; + break; + case CsioSixBits: + stcESCR.L = 2u; + break; + case CsioSevenBits: + stcESCR.L = 3u; + break; + case CsioEightBits: + stcESCR.L = 0u; + break; + case CsioNineBits: + stcESCR.L = 4u; + break; + #if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case CsioTenBits: + stcESCR.L = 5u; + break; + case CsioElevenBits: + stcESCR.L = 6u; + break; + case CsioTwelveBits: + stcESCR.L = 7u; + break; + case CsioThirteenBits: + stcESCR.L = 0u; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case CsioFourteenBits: + stcESCR.L = 1u; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case CsioFifteenBits: + stcESCR.L = 2u; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case CsioSixteenBits: + stcESCR.L = 3u; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + #endif + default: + return (ErrorInvalidParameter); + } + /* Set Bit direction (LSB/MSB) */ + switch(pstcConfig->enBitDirection) + { + case CsioDataLsbFirst: + stcSMR.BDS = FALSE; + break; + case CsioDataMsbFirst: + stcSMR.BDS = TRUE; + break; + default: + return ErrorInvalidParameter; + } + + /* Set Signal system (SCK Mark Level) */ + if (TRUE == pstcConfig->bInvertClk) + { + stcSMR.SCINV = TRUE; /* SCK Make Level : Low */ + } + else + { + stcSMR.SCINV = FALSE; /* SCK Make Level : High */ + } + + stcSSR.REC = TRUE; /* Clear received error flag */ + + /* Set Baudrate */ + (void)Mfs_Csio_SetBaudRate(pstcCsio, pstcConfig->u32BaudRate); + /* Set registers value */ + pstcCsio->SMR_f = stcSMR; + pstcCsio->SCR_f = stcSCR; + pstcCsio->ESCR_f = stcESCR; + pstcCsio->SSR_f = stcSSR; + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + if(NULL != pstcConfig->pstcSerialTimer) /* Use serial timer? */ + { + /* Set serial timer clock */ + switch(pstcConfig->pstcSerialTimer->enClkDiv) + { + case CsioTimerNoDiv: + pstcCsio->SACSR_f.TDIV = 0u; + break; + case CsioTimerDiv2: + pstcCsio->SACSR_f.TDIV = 1u; + break; + case CsioTimerDiv4: + pstcCsio->SACSR_f.TDIV = 2u; + break; + case CsioTimerDiv8: + pstcCsio->SACSR_f.TDIV = 3u; + break; + case CsioTimerDiv16: + pstcCsio->SACSR_f.TDIV = 4u; + break; + case CsioTimerDiv32: + pstcCsio->SACSR_f.TDIV = 5u; + break; + case CsioTimerDiv64: + pstcCsio->SACSR_f.TDIV = 6u; + break; + case CsioTimerDiv128: + pstcCsio->SACSR_f.TDIV = 7u; + break; + case CsioTimerDiv256: + pstcCsio->SACSR_f.TDIV = 8u; + break; + default: + return ErrorInvalidParameter; + } + + /* Transfer count */ + pstcCsio->TBYTE0 = pstcConfig->pstcSerialTimer->u8TransferByteCnt; + + /* Timer compare value */ + pstcCsio->STMCR = pstcConfig->pstcSerialTimer->u16CompareVal; + + /* Enable sync transfer */ + pstcCsio->SACSR_f.TSYNE = 1u; + } + + if(NULL != pstcConfig->pstcCsConfig) /* Use chip selection function? */ + { + if(CsioMaster == pstcConfig->enMsMode) + { + + #if (defined(FM4_MFS_TYPE_A)) + #else + /* Select CS start pin */ + switch(pstcConfig->pstcCsConfig->enCsStartPin) + { + case CsPinScs0: + pstcCsio->SCSCR_f.SST = 0u; + break; + case CsPinScs1: + pstcCsio->SCSCR_f.SST = 1u; + break; + case CsPinScs2: + pstcCsio->SCSCR_f.SST = 2u; + break; + case CsPinScs3: + pstcCsio->SCSCR_f.SST = 3u; + break; + default: + return ErrorInvalidParameter; + } + + /* Select CS end pin */ + switch(pstcConfig->pstcCsConfig->enCsEndPin) + { + case CsPinScs0: + pstcCsio->SCSCR_f.SED = 0u; + break; + case CsPinScs1: + pstcCsio->SCSCR_f.SED = 1u; + break; + case CsPinScs2: + pstcCsio->SCSCR_f.SED = 2u; + break; + case CsPinScs3: + pstcCsio->SCSCR_f.SED = 3u; + break; + default: + return ErrorInvalidParameter; + } + + /* Set transfer count of each SCS pin */ + pstcCsio->TBYTE0 = pstcConfig->pstcCsConfig->u8Scs0TransferByteCnt; + pstcCsio->TBYTE1 = pstcConfig->pstcCsConfig->u8Scs1TransferByteCnt; + pstcCsio->TBYTE2 = pstcConfig->pstcCsConfig->u8Scs2TransferByteCnt; + pstcCsio->TBYTE3 = pstcConfig->pstcCsConfig->u8Scs3TransferByteCnt; + #endif + /* Select CS active level (only for SCS0) */ + switch(pstcConfig->pstcCsConfig->enLevel) + { + case CsHighActive: + pstcCsio->SCSCR_f.CSLVL = 0u; + break; + case CsLowActive: + pstcCsio->SCSCR_f.CSLVL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + /* Active hold or not */ + pstcCsio->SCSCR_f.SCAM = pstcConfig->pstcCsConfig->bActiveHold; + + /* Set chip selection clock */ + switch(pstcConfig->pstcCsConfig->enClkDiv) + { + case CsClkNoDiv: + pstcCsio->SCSCR_f.CDIV = 0u; + break; + case CsClkDiv2: + pstcCsio->SCSCR_f.CDIV = 1u; + break; + case CsClkDiv4: + pstcCsio->SCSCR_f.CDIV = 2u; + break; + case CsClkDiv8: + pstcCsio->SCSCR_f.CDIV = 3u; + break; + case CsClkDiv16: + pstcCsio->SCSCR_f.CDIV = 4u; + break; + case CsClkDiv32: + pstcCsio->SCSCR_f.CDIV = 5u; + break; + case CsClkDiv64: + pstcCsio->SCSCR_f.CDIV = 6u; + break; + default: + return ErrorInvalidParameter; + } + /* Set chip selection timing */ + pstcCsio->SCSTR1 = pstcConfig->pstcCsConfig->u8CsSetupDelayTime; + pstcCsio->SCSTR0 = pstcConfig->pstcCsConfig->u8CsHoldDelayTime; + pstcCsio->SCSTR32 = pstcConfig->pstcCsConfig->u16CsDeselectTime; + } + + /* Enable SCS pin */ + pstcCsio->SCSCR_f.CSEN0 = ((pstcConfig->pstcCsConfig->bScs0En == TRUE) ? 1u : 0u); + #if (defined(FM4_MFS_TYPE_A)) + #else + pstcCsio->SCSCR_f.CSEN1 = ((pstcConfig->pstcCsConfig->bScs1En == TRUE) ? 1u : 0u); + pstcCsio->SCSCR_f.CSEN2 = ((pstcConfig->pstcCsConfig->bScs2En == TRUE) ? 1u : 0u); + pstcCsio->SCSCR_f.CSEN3 = ((pstcConfig->pstcCsConfig->bScs3En == TRUE) ? 1u : 0u); + #endif + + if(CsioMaster == pstcConfig->enMsMode) + { + /* Enable CS pins output */ + pstcCsio->SCSCR_f.CSOE = 1u; + } + else + { + /* Disable CS pins output */ + pstcCsio->SCSCR_f.CSOE = 0u; + } + } +#endif + + if(NULL != pstcConfig->pstcFifoConfig) /* Use FIFO function? */ + { + /* Reset FIFO */ + pstcCsio->FCR_f.FCL1 = 0u; + pstcCsio->FCR_f.FCL2 = 0u; + /* Enable FIFO receive Idle detection */ + pstcCsio->FCR_f.FRIIE = 1; + /* Selection TX and RX FIFO */ + switch(pstcConfig->pstcFifoConfig->enFifoSel) + { + case MfsTxFifo1RxFifo2: + pstcCsio->FCR_f.FSEL = 0u; + break; + case MfsTxFifo2RxFifo1: + pstcCsio->FCR_f.FSEL = 1u; + break; + default: + return (ErrorInvalidParameter); + } + /* Set FIFO count */ + pstcCsio->FBYTE1 = pstcConfig->pstcFifoConfig->u8ByteCount1; + pstcCsio->FBYTE2 = pstcConfig->pstcFifoConfig->u8ByteCount2; + /* Enable FIFO */ + pstcCsio->FCR_f.FE1 = 1u; + pstcCsio->FCR_f.FE2 = 1u; + } + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + /* Configure interrupts */ + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bRxIrq) + { + pstcCsio->SCR_f.RIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxIrq) + { + pstcCsio->SCR_f.TIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxIdleIrq) + { + pstcCsio->SCR_f.TBIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxFifoIrq) + { + pstcCsio->FCR_f.FTIE = 1u; + } + #if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + if(TRUE == pstcConfig->pstcIrqEn->bCsErrIrq) + { + pstcCsio->SACSR_f.CSEIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bSerialTimerIrq) + { + pstcCsio->SACSR_f.TINTE = 1u; + } + #endif + } + + /* Configure interrupt callback functions */ + if(NULL != pstcConfig->pstcIrqCb) + { + pstcMfsInternData->stcCsioInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcMfsInternData->stcCsioInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcMfsInternData->stcCsioInternIrqCb.pfnTxIdleCb = pstcConfig->pstcIrqCb->pfnTxIdleCb; + pstcMfsInternData->stcCsioInternIrqCb.pfnTxFifoIrqCb = pstcConfig->pstcIrqCb->pfnTxFifoIrqCb; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMfsInternData->stcCsioInternIrqCb.pfnCsErrIrqCb = pstcConfig->pstcIrqCb->pfnCsErrIrqCb; + pstcMfsInternData->stcCsioInternIrqCb.pfnSerialTimerIrqCb = pstcConfig->pstcIrqCb->pfnSerialTimerIrqCb; + #endif + } + + /* Configure NVIC */ + if(TRUE == pstcConfig->bTouchNvic) + { + MfsInitNvic(u8Ch, FALSE); + MfsInitNvic(u8Ch, TRUE); + } + +#endif + return (Ok); +} /* Mfs_Csio_Init */ + +/** + ****************************************************************************** + ** \brief Deinitialisation of a MFS module activating as CSIO. + ** + ** All used CSIO register are reset to their default values. + ** + ** \param [in] pstcCsio Pointer to CSIO instance register area + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Csio_DeInit(volatile stc_mfsn_csio_t* pstcCsio, boolean_t bTouchNvic) +{ + en_result_t enResult; + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Calculate the channel number */ + u8Ch = CsioInstanceToIndex(pstcCsio); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsCsioGetInternDataPtr(pstcCsio); + /* ... and check */ + if (NULL == pstcMfsInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + /* First of all disable receiver, transmitter and deinit interrupts */ + pstcCsio->SCR_f.TXE = FALSE; + pstcCsio->SCR_f.RXE = FALSE; + + /* Baud Rate Generation Reload Reset */ + pstcCsio->BGR = 0u; + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcCsio->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcCsio->SCR = 0u; + + /* Clear reception Errors */ + pstcCsio->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcCsio->SSR = 0u; + pstcCsio->ESCR = 0u; + pstcCsio->FCR = 0u; + + #if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + pstcCsio->SACSR = 0u; + pstcCsio->STMCR = 0u; + pstcCsio->SCSCR = 0u; + pstcCsio->SCSTR0 = 0; + pstcCsio->SCSTR1 = 0; + pstcCsio->SCSTR32 = 0; + pstcCsio->TBYTE0 = 0u; + #if (defined(FM4_MFS_TYPE_A)) + #else + pstcCsio->TBYTE1 = 0u; + pstcCsio->TBYTE2 = 0u; + pstcCsio->TBYTE3 = 0u; + #endif + #endif + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + /* Disable NVIC */ + if(TRUE == bTouchNvic) + { + MfsDeInitNvic(u8Ch, FALSE); + MfsDeInitNvic(u8Ch, TRUE); + } +#endif + enResult = Ok; + } + + return (enResult); +} /* Mfs_Csio_DeInit */ + +/** + ****************************************************************************** + ** \brief Set the baudrate of CSIO + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] u32BaudRate Baudrate value [bps] + ** + ** \retval Ok CSIO baud rate has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - u32BaudRate < 3 + ** \note + ** The CSIO baud rate can be initialized in the Mfs_Csio_Init() and be modified + ** in the funciton. + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SetBaudRate(volatile stc_mfsn_csio_t* pstcCsio, + uint32_t u32BaudRate) +{ + uint32_t u32Pclk1; + + SystemCoreClockUpdate(); + if ((NULL == pstcCsio) || (u32BaudRate < 3u)) + { + return ErrorInvalidParameter; + } +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + u32Pclk1 = SystemCoreClock /(1ul << (FM_CRG->APBC1_PSR & 0x03u)); /* MFS is attached on APB1 bus for FM0+ */ +#else + u32Pclk1 = SystemCoreClock /(1ul << (FM_CRG->APBC2_PSR & 0x03u)); /* MFS is attached on APB2 bus for FM3 and FM4 */ +#endif + pstcCsio->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1u; + + return Ok; +} + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +/** + ****************************************************************************** + ** \brief Set the compare value of CSIO serial timer + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] u16CompareValue Compare value + ** + ** \retval Ok Compare value has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ** \note + ** The compare value of CSIO serial timer can be initialized in + ** the Mfs_Csio_Init() and be modified in this function. + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SetTimerCompareValue(volatile stc_mfsn_csio_t* pstcCsio, + uint16_t u16CompareValue) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + pstcCsio->STMCR = u16CompareValue; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the transfer byte count of a selected chip selection pin + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enCsPin CS pin index + ** \param [in] u8ByteCnt Transfer byte count of a CS pin + ** + ** \retval Ok Transfer byte count has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ** \note + ** The transfer byte count of chip selection pin can be initialized in + ** the Mfs_Csio_Init() and be modified in this funciton. + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SetCsTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, + en_cs_pin_sel_t enCsPin, + uint8_t u8ByteCnt) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + switch(enCsPin) + { + case CsPinScs0: + pstcCsio->TBYTE0 = u8ByteCnt; + break; + #if (defined(FM4_MFS_TYPE_A)) + #else + case CsPinScs1: + pstcCsio->TBYTE1 = u8ByteCnt; + break; + case CsPinScs2: + pstcCsio->TBYTE2 = u8ByteCnt; + break; + case CsPinScs3: + pstcCsio->TBYTE3 = u8ByteCnt; + break; + #endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the hold status of chip selection pin + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] bHold + ** \arg FALSE Make the CS pin inactive if specified count bytes are + ** transferred + ** \arg TRUE Hold the CS pin status even if specified count bytes are + ** transferred + ** + ** \retval Ok Hold status of chip selection pin is set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SetCsHoldStatus(volatile stc_mfsn_csio_t* pstcCsio, + boolean_t bHold) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + pstcCsio->SCSCR_f.SCAM = (bHold == TRUE) ? 1u : 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the transfer byte count of CSIO serial timer + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] u8ByteCnt Transfer byte count + ** + ** \retval Ok Transfer byte count has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ** \note + ** The transfer byte count of CSIO serial timer can be initialized in + ** the Mfs_Csio_Init() and be modified in this function. + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SetTimerTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, + uint8_t u8ByteCnt) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + pstcCsio->TBYTE0 = u8ByteCnt; + + return Ok; +} +#endif + +/** + ****************************************************************************** + ** \brief Enable CSIO functions + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enFunc CSIO function types + ** \arg CsioTx CSIO transfer function + ** \arg CsioRx CSIO receive function + ** \arg CsioSerialTimer CSIO serial timer function + ** \arg CsioCsErrOccur CSIO chip selection error detection function + ** + ** \retval Ok Function has been enabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_EnableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + switch(enFunc) + { + case CsioTx: + pstcCsio->SCR_f.TXE = 1u; + break; + case CsioRx: + pstcCsio->SCR_f.RXE = 1u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case CsioSerialTimer: + pstcCsio->SACSR_f.TMRE = 1u; + break; + case CsioCsErrOccur: + pstcCsio->SACSR_f.TBEEN = 1u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable CSIO functions + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enFunc CSIO function types + ** \arg CsioTx CSIO transfer function + ** \arg CsioRx CSIO receive function + ** \arg CsioSerialTimer CSIO transfer function + ** \arg CsioCsErrOccur CSIO receive function + ** + ** \retval Ok Function has been disabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_DisableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + switch(enFunc) + { + case CsioTx: + pstcCsio->SCR_f.TXE = 0u; + break; + case CsioRx: + pstcCsio->SCR_f.RXE = 0u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case CsioSerialTimer: + pstcCsio->SACSR_f.TMRE = 0u; + break; + case CsioCsErrOccur: + pstcCsio->SACSR_f.TBEEN = 0u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get status of CSIO according to status type + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enStatus CSIO status type + ** \arg CsioOverrunError CSIO parity error + ** \arg CsioRxFull CSIO receive buffer full + ** \arg CsioTxEmpty CSIO tranfer buffer empty + ** \arg CsioTxIdle CSIO tranfer idle status + ** \arg CsioTxFifoRequest CSIO transfer FIFO request + ** \arg CsioCsErrIntFlag CSIO chip selection error occurrance + ** \arg CsioTimerIntFlag CSIO serial timer interrupt flag + ** + ** \retval FALSE If one of following conditions are met: + ** - No CSIO overrun error [enStatus = CsioOverrunError] + ** - CSIO receive buffer is not full [enStatus = CsioRxFull] + ** - CSIO tranfer buffer is not empty [enStatus = CsioTxEmpty] + ** - CSIO tranfer is on-going [enStatus = CsioTxIdle] + ** - No CSIO transfer FIFO request [enStatus = CsioTxFifoRequest] + ** - CSIO chip selection error doesn't occur [enStatus = CsioCsErrIntFlag] + ** - CSIO serial timer interrupt doesn't occur [enStatus = CsioTimerIntFlag] + ** \retval TRUE If one of following conditions are met: + ** - CSIO overrun error occurs [enStatus = CsioOverrunError] + ** - CSIO receive buffer is full [enStatus = CsioRxFull] + ** - CSIO tranfer buffer is empty [enStatus = CsioTxEmpty] + ** - CSIO tranfer is idle [enStatus = CsioTxIdle] + ** - CSIO transfer FIFO request issues [enStatus = CsioTxFifoRequest] + ** - CSIO chip selection error occurs [enStatus = CsioCsErrIntFlag] + ** - CSIO serial timer interrupt occurs [enStatus = CsioTimerIntFlag] + ** + ******************************************************************************/ +boolean_t Mfs_Csio_GetStatus(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_status_t enStatus) +{ + boolean_t bRet = FALSE; + + switch(enStatus) + { + case CsioOverrunError: + bRet = (1u == pstcCsio->SSR_f.ORE) ? TRUE : FALSE; + break; + case CsioRxFull: + bRet = (1u == pstcCsio->SSR_f.RDRF) ? TRUE : FALSE; + break; + case CsioTxEmpty: + bRet = (1u == pstcCsio->SSR_f.TDRE) ? TRUE : FALSE; + break; + case CsioTxIdle: + bRet = (1u == pstcCsio->SSR_f.TBI) ? TRUE : FALSE; + break; + case CsioTxFifoRequest: + bRet = (1u == pstcCsio->FCR_f.FDRQ) ? TRUE : FALSE; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case CsioCsErrIntFlag: + bRet = (1u == pstcCsio->SACSR_f.CSE) ? TRUE : FALSE; + break; + case CsioTimerIntFlag: + bRet = (1u == pstcCsio->SACSR_f.TINT) ? TRUE : FALSE; + break; + #endif + default: + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear status of CSIO according to status type + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enStatus UART status type + ** \arg CsioOverrunError CSIO overrun error + ** \arg CsioRxFull CSIO receive buffer full + ** \arg CsioTxEmpty CSIO tranfer buffer empty + ** \arg CsioTxIdle CSIO tranfer idle status + ** \arg CsioTxFifoRequest CSIO transfer FIFO request + ** \arg CsioCsErrIntFlag CSIO chip selection error occurrance + ** + ** \retval Ok Status has been cleared normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** \note The following status can only be cleared by hardware behavior: + ** - CsioRxFull + ** - CsioTxEmpty + ** - CsioTxIdle + ** + ******************************************************************************/ +en_result_t Mfs_Csio_ClrStatus(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_status_t enStatus) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + switch(enStatus) + { + case CsioOverrunError: + pstcCsio->SSR_f.REC = 1u; + break; + case CsioRxFull: + case CsioTxEmpty: + case CsioTxIdle: + break; + case CsioTxFifoRequest: + pstcCsio->FCR_f.FDRQ = 0u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case CsioCsErrIntFlag: + pstcCsio->SACSR_f.CSE = 0u; + break; + case CsioTimerIntFlag: + pstcCsio->SACSR_f.TINT = 0u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write CSIO data buffer + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] u16Data Send data + ** \param [in] bSotEn SOT output enable + ** \arg FALSE Mask SOT output + ** \arg TRUE Enable SOT output + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SendData(volatile stc_mfsn_csio_t* pstcCsio, + uint16_t u16Data, + boolean_t bSotEn) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + (TRUE == bSotEn) ? (pstcCsio->SMR_f.SOE = 1u) : (pstcCsio->SMR_f.SOE = 0u); + + pstcCsio->TDR = u16Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read CSIO data buffer + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint16_t Mfs_Csio_ReceiveData(volatile stc_mfsn_csio_t* pstcCsio) +{ + return pstcCsio->RDR; +} + +/** + ****************************************************************************** + ** \brief Reset CSIO FIFO + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval Ok FIFO has been successfully reset + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_ResetFifo (volatile stc_mfsn_csio_t* pstcCsio, + en_mfs_fifo_t enFifo) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcCsio->FCR_f.FCL1 = 1u; + break; + case MfsFifo2: + pstcCsio->FCR_f.FCL2 = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set CSIO FIFO count + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** \param [in] u8Count FIFO count + ** + ** \retval Ok FIFO count has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Csio_SetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, + en_mfs_fifo_t enFifo, + uint8_t u8Count) +{ + if (NULL == pstcCsio) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcCsio->FBYTE1 = u8Count; + break; + case MfsFifo2: + pstcCsio->FBYTE2 = u8Count; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get CSIO FIFO count + ** + ** \param [in] pstcCsio Pointer to CSIO instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval FIFO count + ** + ** This function gets the current data count in selected FIFO. + ** + ** \note 0xFF will be return value if FIFO index is error. + ** + ******************************************************************************/ +uint8_t Mfs_Csio_GetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, + en_mfs_fifo_t enFifo) +{ + uint8_t u8FifoCnt = 0xFFu; + + switch(enFifo) + { + case MfsFifo1: + u8FifoCnt = pstcCsio->FBYTE1; + break; + case MfsFifo2: + u8FifoCnt = pstcCsio->FBYTE2; + break; + default: + break; + } + + return u8FifoCnt; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) +/****************************************************************************** + * I2C driver functions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain I2C instance. + ** + ** \param pstcI2c Pointer to I2C instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_mfs_intern_data_t* MfsI2cGetInternDataPtr(volatile stc_mfsn_i2c_t* pstcI2c) +{ + stc_mfs_intern_data_t* pstcInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcI2c) + { + for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) + { + if (pstcI2c == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcI2cInstance) + { + pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; + break; + } + } + + } + + return (pstcInternDataPtr); +} /* MfsGetInternDataPtr */ + + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +/** + ****************************************************************************** + ** \brief I2C receive interrupt service routine. + ** + ** \param pstcI2c Pointer to I2C instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Receive Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsI2cIrqHandlerRx( volatile stc_mfsn_i2c_t* pstcI2c, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcI2c) && (NULL != pstcMfsInternData)) + { + if (NULL != pstcMfsInternData->stcI2cInternIrqCb.pfnRxIrqCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnRxIrqCb(); + } + } +} /* MfsIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief I2C transfer interrupt service routine. + ** + ** \param pstcI2c Pointer to I2C instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on transfer Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsI2cIrqHandlerTx( volatile stc_mfsn_i2c_t* pstcI2c, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if(1u == pstcI2c->SSR_f.TDRE) + { + if (NULL != pstcMfsInternData->stcI2cInternIrqCb.pfnTxIrqCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnTxIrqCb(); + } + } + + if(1u == pstcI2c->SSR_f.TBI) + { + if (NULL != pstcMfsInternData->stcI2cInternIrqCb.pfnTxIdleCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnTxIdleCb(); + } + } + + if(1u == pstcI2c->FCR_f.FDRQ) + { + if (NULL != pstcMfsInternData->stcI2cInternIrqCb.pfnTxFifoIrqCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnTxFifoIrqCb(); + } + + pstcI2c->FCR_f.FDRQ = 0u; + } +} /* MfsIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief I2C status interrupt service routine. + ** + ** \param pstcI2c Pointer to I2C instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on transfer Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsI2cIrqHandlerStatus( volatile stc_mfsn_i2c_t* pstcI2c, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcI2c) && (NULL != pstcMfsInternData)) + { + if(1u == pstcI2c->IBCR_f.INT) + { + if (NULL != pstcMfsInternData->stcI2cInternIrqCb.pfnTxRxIrqCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnTxRxIrqCb(); + } + + // pstcI2c->IBCR_f.INT = 0; /* It will be cleared in callback function */ + } + + if(1u == pstcI2c->IBSR_f.SPC) + { + if (NULL != pstcMfsInternData->stcI2cInternIrqCb.pfnStopDetectIrqCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnStopDetectIrqCb(); + } + + pstcI2c->IBSR_f.SPC = 0u; + } + } +} + +/** + ****************************************************************************** + ** \brief Enable I2C interrupts + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enIrqSel enumeration of I2C interrupt selection + ** \arg I2cTxIrq TX interrupt of I2C + ** \arg I2cRxIrq RX interrupt of I2C + ** \arg I2cTxIdleIrq TX idle interrupt of I2C + ** \arg I2cTxFifoIrq TX FIFO interrupt of I2C + ** \arg I2cTxRxIrq TX and RX interrupt of I2C + ** \arg I2cStopDetectIrq Stop detection interrupt of I2C + ** + ** \retval Ok Interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mfs_I2c_EnableIrq(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_irq_sel_t enIrqSel) +{ + if (NULL == pstcI2c) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case I2cTxIrq: + pstcI2c->SMR_f.TIE = 1u; + break; + case I2cRxIrq: + pstcI2c->SMR_f.RIE = 1u; + break; + case I2cTxIdleIrq: + pstcI2c->FCR_f.FTIE = 1u; + break; + case I2cTxFifoIrq: + pstcI2c->SSR_f.TBIE = 1u; + break; + case I2cTxRxIrq: + pstcI2c->IBCR_f.INTE = 1u; + break; + case I2cStopDetectIrq: + pstcI2c->IBCR_f.CNDE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable I2C interrupts + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enIrqSel enumeration of I2C interrupt selection + ** \arg I2cTxIrq TX interrupt of I2C + ** \arg I2cRxIrq RX interrupt of I2C + ** \arg I2cTxIdleIrq TX idle interrupt of I2C + ** \arg I2cTxFifoIrq TX FIFO interrupt of I2C + ** \arg I2cTxRxIrq TX and RX interrupt of I2C + ** \arg I2cStopDetectIrq Stop detection interrupt of I2C + ** + ** \retval Ok Interrupts has been disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mfs_I2c_DisableIrq(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_irq_sel_t enIrqSel) +{ + if (NULL == pstcI2c) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case I2cTxIrq: + pstcI2c->SMR_f.TIE = 0u; + break; + case I2cRxIrq: + pstcI2c->SMR_f.RIE = 0u; + break; + case I2cTxIdleIrq: + pstcI2c->FCR_f.FTIE = 0u; + break; + case I2cTxFifoIrq: + pstcI2c->SSR_f.TBIE = 0u; + break; + case I2cTxRxIrq: + pstcI2c->IBCR_f.INTE = 0u; + break; + case I2cStopDetectIrq: + pstcI2c->IBCR_f.CNDE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialization of a MFS module to activate as I2C. + ** + ** Set registers to active MFS as I2C. + ** + ** \param [in] pstcI2c Pointer to I2C instance register area + ** \param [in] pstcConfig MFS I2C configuration + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_I2c_Init(volatile stc_mfsn_i2c_t* pstcI2c, + const stc_mfs_i2c_config_t* pstcConfig) +{ + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Preset local register variables to zero */ + stc_mfs_i2c_smr_field_t stcSMR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_isba_field_t stcISBA; + stc_mfs_i2c_ismk_field_t stcISMK; + + PDL_ZERO_STRUCT(stcSMR); + PDL_ZERO_STRUCT(stcIBCR); + PDL_ZERO_STRUCT(stcISBA); + PDL_ZERO_STRUCT(stcISMK); + + /* Calculate the channel number */ + u8Ch = I2cInstanceToIndex(pstcI2c); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsI2cGetInternDataPtr(pstcI2c); + + /* Parameter check and get ptr to internal data struct */ + if ((NULL == pstcMfsInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* Set the MFS mode in the internal structure */ + pstcMfsInternData->enMode = MfsI2cMode; + + /* Set I2C mode */ + switch (pstcConfig->enMsMode) + { + case I2cMaster: + case I2cSlave: + stcSMR.MD = 4u; + break; + default: + return (ErrorInvalidParameter); + } + + /* Ack enable */ + stcIBCR.ACKE = TRUE; + + /* Slave mode */ + if (I2cSlave == pstcConfig->enMsMode) + { + /* Set slave address */ + stcISBA.SA = pstcConfig->u8SlaveAddr; + /* Enable slave address detection */ + stcISBA.SAEN = TRUE; + /* Set slave address bit mask */ + stcISMK.SM = pstcConfig->u8SlaveMaskAddr; + } + + /* Enable I2C*/ + stcISMK.EN = TRUE; + + /* now setup hardware with correct mode first and then go on with */ + /* bit settings */ + pstcI2c->SMR_f = stcSMR; + + /* I2C disable before other registers are set. */ + pstcI2c->ISMK = 0u; + + /* Use DMA or not */ + if(TRUE == pstcConfig->bDmaEnable) + { + pstcI2c->SSR_f.DMA = 1u; + } + else + { + pstcI2c->SSR_f.DMA = 0u; + } + + /* Set baud rate generation */ + (void)Mfs_I2c_SetBaudRate(pstcI2c, pstcConfig->u32BaudRate); + + /* Set registers value */ + pstcI2c->IBCR_f = stcIBCR; + pstcI2c->ISBA_f = stcISBA; + pstcI2c->ISMK_f = stcISMK; + + if(NULL != pstcConfig->pstcFifoConfig) /* Use FIFO function? */ + { + /* Reset FIFO */ + pstcI2c->FCR_f.FCL1 = 1u; + pstcI2c->FCR_f.FCL2 = 1u; + /* Enable FIFO receive Idle detection */ + pstcI2c->FCR_f.FRIIE = 1; + /* Selection TX and RX FIFO */ + switch(pstcConfig->pstcFifoConfig->enFifoSel) + { + case MfsTxFifo1RxFifo2: + pstcI2c->FCR_f.FSEL = 0u; + break; + case MfsTxFifo2RxFifo1: + pstcI2c->FCR_f.FSEL = 1u; + break; + default: + return (ErrorInvalidParameter); + } + /* Set FIFO count */ + pstcI2c->FBYTE1 = pstcConfig->pstcFifoConfig->u8ByteCount1; + pstcI2c->FBYTE2 = pstcConfig->pstcFifoConfig->u8ByteCount2; + /* Enable FIFO */ + pstcI2c->FCR_f.FE1 = 1; + pstcI2c->FCR_f.FE2 = 1; + } + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + /* Configure interrupt */ + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTxIrq) + { + pstcI2c->SMR_f.TIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bRxIrq) + { + pstcI2c->SMR_f.RIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxFifoIrq) + { + pstcI2c->FCR_f.FTIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxIdleIrq) + { + pstcI2c->SSR_f.TBIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxRxIrq) + { + pstcI2c->IBCR_f.INTE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bStopDetectIrq) + { + pstcI2c->IBCR_f.CNDE = 1u; + } + } + + /* Configure interrupt callback */ + if(NULL != pstcConfig->pstcIrqCb) + { + pstcMfsInternData->stcI2cInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcMfsInternData->stcI2cInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcMfsInternData->stcI2cInternIrqCb.pfnTxFifoIrqCb = pstcConfig->pstcIrqCb->pfnTxFifoIrqCb; + pstcMfsInternData->stcI2cInternIrqCb.pfnTxIdleCb = pstcConfig->pstcIrqCb->pfnTxIdleCb; + pstcMfsInternData->stcI2cInternIrqCb.pfnTxRxIrqCb = pstcConfig->pstcIrqCb->pfnTxRxIrqCb; + pstcMfsInternData->stcI2cInternIrqCb.pfnStopDetectIrqCb = pstcConfig->pstcIrqCb->pfnStopDetectIrqCb; + } + + /* Configure NVIC */ + if(TRUE == pstcConfig->bTouchNvic) + { + MfsInitNvic(u8Ch, FALSE); + MfsInitNvic(u8Ch, TRUE); + } + +#endif + + return (Ok); +} /* Mfs_I2c_Init */ + +/** + ****************************************************************************** + ** \brief Deinitialisation of a MFS module activating as I2C. + ** + ** All used I2C register are reset to their default values. + ** + ** \param [in] pstcI2c Pointer to I2C instance register area + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_I2c_DeInit( volatile stc_mfsn_i2c_t* pstcI2c, boolean_t bTouchNvic) +{ + en_result_t enResult; + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Calculate the channel number */ + u8Ch = I2cInstanceToIndex(pstcI2c); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsI2cGetInternDataPtr(pstcI2c); + /* ... and check */ + if (NULL == pstcMfsInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + /* Disable I2C */ + pstcI2c->ISMK_f.EN = FALSE; + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcI2c->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcI2c->IBCR = 0u; + + /* Clear reception Errors */ + pstcI2c->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcI2c->SSR = 0u; + pstcI2c->IBSR = 0u; + pstcI2c->FCR = 0u; + + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + if(TRUE == bTouchNvic) + { + MfsDeInitNvic(u8Ch, FALSE); + MfsDeInitNvic(u8Ch, TRUE); + } +#endif + enResult = Ok; + } + + return (enResult); +} /* Mfs_I2c_DeInit */ + +/** + ****************************************************************************** + ** \brief Set the baudrate of I2C + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] u32BaudRate Baudrate value [bps] + ** + ** \retval Ok I2C baud rate has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - u32BaudRate < 3 + ** + ** The I2C baud rate can be initialized in the Mfs_I2c_Init() and be modified + ** with this function. + ** + ******************************************************************************/ +en_result_t Mfs_I2c_SetBaudRate(volatile stc_mfsn_i2c_t* pstcI2c, + uint32_t u32BaudRate) +{ + uint32_t u32Pclk1; + boolean_t bTempBit = FALSE; + + SystemCoreClockUpdate(); + if ((NULL == pstcI2c) || (u32BaudRate > 400000u)) + { + return ErrorInvalidParameter; + } + + bTempBit = pstcI2c->ISMK_f.EN; + pstcI2c->ISMK_f.EN = 1u; +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + u32Pclk1 = SystemCoreClock /(1ul << (FM_CRG->APBC1_PSR & 0x03u)); // MFS is attached on APB1 bus for FM0+ +#else + u32Pclk1 = SystemCoreClock /(1ul << (FM_CRG->APBC2_PSR & 0x03u)); // MFS is attached on APB2 bus for FM3 and FM4 +#endif + pstcI2c->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1u; + pstcI2c->ISMK_f.EN = bTempBit; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Generate start signal of I2C + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** + ** \retval Ok Generate start signal successfully + ** \retval ErrorInvalidParameter pstcI2c == NULL + ** \retval ErrorTimeout Timeout when generating a start signal + ** + ******************************************************************************/ +en_result_t Mfs_I2c_GenerateStart(volatile stc_mfsn_i2c_t* pstcI2c) +{ + uint32_t u32TimeOut = SystemCoreClock; + + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + pstcI2c->IBCR_f.MSS = 1u; + while(u32TimeOut--) + { + if((1u == pstcI2c->IBCR_f.MSS) && (1u == pstcI2c->IBCR_f.ACT_SCC)) + { + return Ok; + } + } + + return ErrorTimeout; +} + +/** + ****************************************************************************** + ** \brief Generate restart signal of I2C + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** + ** \retval Ok Generate restart signal successfully + ** \retval ErrorInvalidParameter pstcI2c == NULL + ** \retval ErrorTimeout Timeout when generating a restart signal + ** + ******************************************************************************/ +en_result_t Mfs_I2c_GenerateRestart(volatile stc_mfsn_i2c_t* pstcI2c) +{ + uint32_t u32TimeOut = SystemCoreClock; + + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + pstcI2c->IBCR_f.ACT_SCC = 1u; + + while(u32TimeOut--) + { + if(1u == pstcI2c->IBSR_f.RSC) + { + return Ok; + } + } + + return ErrorTimeout; +} + +/** + ****************************************************************************** + ** \brief Generate stop signal of I2C + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** + ** \retval Ok Generate stop signal successfully + ** \retval ErrorInvalidParameter pstcI2c == NULL + ** \retval ErrorTimeout Timeout when generating a stop signal + ** + ******************************************************************************/ +en_result_t Mfs_I2c_GenerateStop(volatile stc_mfsn_i2c_t* pstcI2c) +{ + uint32_t u32TimeOut = SystemCoreClock; + + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + while(u32TimeOut--) + { + pstcI2c->IBCR &= ~0xc1u; + if((0u == pstcI2c->IBCR_f.MSS) && (0u == pstcI2c->IBCR_f.ACT_SCC)) + { + return Ok; + } + } + + return ErrorTimeout; +} + +/** + ****************************************************************************** + ** \brief Write I2C data buffer + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] u8Data Data to be sent + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** + ******************************************************************************/ +en_result_t Mfs_I2c_SendData(volatile stc_mfsn_i2c_t* pstcI2c, uint8_t u8Data) +{ + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + pstcI2c->TDR = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read I2C data buffer + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint8_t Mfs_I2c_ReceiveData(volatile stc_mfsn_i2c_t* pstcI2c) +{ + return pstcI2c->RDR; +} + +/** + ****************************************************************************** + ** \brief Configure ACK signal sent to master + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enAck ACK to be sent + ** \arg I2cAck ACK will be sent as response signal + ** \arg I2cNAck NACK will be sent as response signal + ** + ** \retval Ok ACK signal has been successfully configured + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** + ** This function is only meaningful when I2C is in slave mode + ** + ******************************************************************************/ +en_result_t Mfs_I2c_ConfigAck(volatile stc_mfsn_i2c_t* pstcI2c, en_i2c_ack_t enAck) +{ + stc_mfs_i2c_ibcr_field_t stcIbcr = pstcI2c->IBCR_f; + + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + (I2cAck == enAck) ? (stcIbcr.ACKE = 1u) : (stcIbcr.ACKE = 0u); + + stcIbcr.ACT_SCC = 0u; // Set SCC = 0 to avoid generating a restart + + pstcI2c->IBCR_f = stcIbcr; + + return Ok; + +} + +/** + ****************************************************************************** + ** \brief Get the ACK signal from slave + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** + ** \retval I2cAck Receive the ACK from I2C Slave + ** \retval I2cNAck Receive the NACK from I2C Slave + ** + ** This function applies in the I2C master mode. + ** + ******************************************************************************/ +en_i2c_ack_t Mfs_I2c_GetAck(volatile stc_mfsn_i2c_t* pstcI2c) +{ + en_i2c_ack_t enRet; + + enRet = (0u == pstcI2c->IBSR_f.RACK) ? I2cAck : I2cNAck; + + return enRet; +} + +/** + ****************************************************************************** + ** \brief Get status of I2C according to status type + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enStatus I2C status type + ** \arg I2cOverrunError I2C overrun error + ** \arg I2cRxFull I2C receive buffer full + ** \arg I2cTxEmpty I2C tranfer buffer empty + ** \arg I2cTxFifoRequest I2C transfer FIFO request + ** \arg I2cTxIdle I2C tranfer idle status + ** \arg I2cFirstByteDetect I2C first byte detection + ** \arg I2cReservedByteDetect I2C reserved address detection + ** \arg I2cStopDetect I2C stop condition detection + ** \arg I2cBusStatus I2C bus status + ** \arg I2cBusErr I2C bus error + ** \arg I2cRxTxIrq I2C transfer and receive interrupt flag + ** + ** \retval FALSE If one of following conditions are met: + ** - No I2C overrun error [enStatus = I2cOverrunError] + ** - I2C receive buffer is not full [enStatus = I2cRxFull] + ** - I2C tranfer buffer is not empty [enStatus = I2cTxEmpty] + ** - I2C tranfer FIFO request doesn't issue [enStatus = I2cTxFifoRequest] + ** - I2C tranfer is on-going [enStatus = I2cTxIdle] + ** - I2C first byte is not detected [enStatus = I2cFirstByteDetect] + ** - I2C reserved address is not detected [enStatus = I2cReservedByteDetect] + ** - I2C stop condition is not detected [enStatus = I2cStopDetect] + ** - I2C bus is idle [enStatus = I2cBusStatus] + ** - I2C bus error doesn't occur [enStatus = I2cBusErr] + ** - I2C transfer or receive is not completed. [enStatus = I2cRxTxIrq] + ** + ** \retval TRUE If one of following conditions are met: + ** - I2C overrun error occurs [enStatus = I2cOverrunError] + ** - I2C receive buffer is full [enStatus = I2cRxFull] + ** - I2C tranfer buffer is empty [enStatus = I2cTxEmpty] + ** - I2C tranfer FIFO request issues [enStatus = I2cTxFifoRequest] + ** - I2C tranfer is idle [enStatus = I2cTxIdle] + ** - I2C first byte is detected [enStatus = I2cFirstByteDetect] + ** - I2C reserved address is detected [enStatus = I2cReservedByteDetect] + ** - I2C stop condition is detected [enStatus = I2cStopDetect] + ** - I2C bus is busy [enStatus = I2cBusStatus] + ** - I2C bus error occurs [enStatus = I2cBusErr] + ** - I2C transfer or receive is completed. [enStatus = I2cRxTxIrq] + ** + ******************************************************************************/ +boolean_t Mfs_I2c_GetStatus(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_status_t enStatus) +{ + boolean_t bRet = FALSE; + + switch(enStatus) + { + case I2cOverrunError: + bRet = (1u == pstcI2c->SSR_f.ORE ) ? TRUE : FALSE; + break; + case I2cRxFull: + bRet = (1u == pstcI2c->SSR_f.RDRF) ? TRUE : FALSE; + break; + case I2cTxEmpty: + bRet = (1u == pstcI2c->SSR_f.TDRE) ? TRUE : FALSE; + break; + case I2cTxIdle: + bRet = (1u == pstcI2c->SSR_f.TBI) ? TRUE : FALSE; + break; + case I2cTxFifoRequest: + bRet = (1u == pstcI2c->FCR_f.FDRQ) ? TRUE : FALSE; + break; + case I2cFirstByteDetect: + bRet = (1u == pstcI2c->IBSR_f.FBT) ? TRUE : FALSE; + break; + case I2cReservedByteDetect: + bRet = (1u == pstcI2c->IBSR_f.RSA ) ? TRUE : FALSE; + break; + case I2cStopDetect: + bRet = (1u == pstcI2c->IBSR_f.SPC) ? TRUE : FALSE; + break; + case I2cBusStatus: + bRet = (1u == pstcI2c->IBSR_f.BB) ? TRUE : FALSE; + break; + case I2cBusErr: + bRet = (1u == pstcI2c->IBCR_f.BER) ? TRUE : FALSE; + break; + case I2cRxTxIrq: + bRet = (1u == pstcI2c->IBCR_f.INT) ? TRUE : FALSE; + break; + case I2cDevAddrMatch: + if((0u == pstcI2c->IBCR_f.MSS) && (1u == pstcI2c->IBCR_f.ACT_SCC)) + { + bRet = TRUE; + } + else + { + bRet = FALSE; + } + break; + default: + break; + } + + return bRet; +} + + +/** + ****************************************************************************** + ** \brief Clear status of I2C according to status type + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enStatus I2C status type + ** \arg I2cOverrunError I2C overrun error + ** \arg I2cRxFull I2C receive buffer full + ** \arg I2cTxEmpty I2C tranfer buffer empty + ** \arg I2cTxFifoRequest I2C transfer FIFO request + ** \arg I2cTxIdle I2C tranfer idle status + ** \arg I2cFirstByteDetect I2C first byte detection + ** \arg I2cReservedByteDetect I2C reserved address detection + ** \arg I2cStopDetect I2C stop condition detection + ** \arg I2cBusStatus I2C bus status + ** \arg I2cBusErr I2C bus error + ** \arg I2cRxTxIrq I2C transfer and receive interrupt flag + ** + ** \retval Ok Status has been cleared normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** \note The following status can only be cleared by hardware behavior: + ** - I2cRxFull + ** - I2cTxEmpty + ** - I2cTxIdle + ** - I2cFirstByteDetect + ** - I2cReservedByteDetect + ** - I2cBusStatus + ** - I2cBusErr + ** + ******************************************************************************/ +en_result_t Mfs_I2c_ClrStatus(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_status_t enStatus) +{ + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + switch(enStatus) + { + case I2cOverrunError: + pstcI2c->SSR_f.REC = 1u; + break; + case I2cRxFull: + case I2cTxEmpty: + case I2cTxIdle: + case I2cDevAddrMatch: + break; + case I2cTxFifoRequest: + pstcI2c->FCR_f.FDRQ = 0u; + break; + case I2cFirstByteDetect: + break; + case I2cReservedByteDetect: + break; + case I2cStopDetect: + pstcI2c->IBSR_f.SPC = 0u; + break; + case I2cBusStatus: + break; + case I2cBusErr: + break; + case I2cRxTxIrq: + pstcI2c->IBCR &= ~0x41u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get direction of I2C data in slave mode + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** + ** \retval i2c_master_tx_slave_rx Master will send data to slave + ** \retval i2c_slave_tx_master_rx Master will receive data from slave + ** + ** This function can be called after receiving the device address from master + ** in the slave mode. + ** + ******************************************************************************/ +en_i2c_data_dir_t Mfs_I2c_GetDataDir(volatile stc_mfsn_i2c_t* pstcI2c) +{ + en_i2c_data_dir_t enDir; + + (0u == pstcI2c->IBSR_f.TRX) ? (enDir = i2c_master_tx_slave_rx) : (enDir = i2c_slave_tx_master_rx); + + return enDir; +} + +/** + ****************************************************************************** + ** \brief Reset I2C FIFO + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval Ok FIFO has been successfully reset + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** + ******************************************************************************/ +en_result_t Mfs_I2c_ResetFifo (volatile stc_mfsn_i2c_t* pstcI2c, + en_mfs_fifo_t enFifo) +{ + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcI2c->FCR_f.FCL1 = 1u; + break; + case MfsFifo2: + pstcI2c->FCR_f.FCL2 = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set I2C FIFO count + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** \param [in] u8Count FIFO count + ** + ** \retval Ok FIFO count has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** + ******************************************************************************/ +en_result_t Mfs_I2c_SetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, + en_mfs_fifo_t enFifo, + uint8_t u8Count) +{ + if (NULL == pstcI2c) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcI2c->FBYTE1 = u8Count; + break; + case MfsFifo2: + pstcI2c->FBYTE2 = u8Count; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get I2C FIFO count + ** + ** \param [in] pstcI2c Pointer to I2C instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval FIFO count + ** + ** This function gets the current data count in selected FIFO. + ** + ** \note 0xFF will be return value if FIFO index is error. + ** + ******************************************************************************/ +uint8_t Mfs_I2c_GetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, + en_mfs_fifo_t enFifo) +{ + uint8_t u8FifoCnt = 0xFFu; + + switch(enFifo) + { + case MfsFifo1: + u8FifoCnt = pstcI2c->FBYTE1; + break; + case MfsFifo2: + u8FifoCnt = pstcI2c->FBYTE2; + break; + default: + break; + } + + return u8FifoCnt; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) +/****************************************************************************** + * LIN driver functions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain MFS instance. + ** + ** \param pstcLin Pointer to LIN instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_mfs_intern_data_t* MfsLinGetInternDataPtr(volatile stc_mfsn_lin_t* pstcLin) +{ + stc_mfs_intern_data_t* pstcInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcLin) + { + for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) + { + if (pstcLin == m_astcMfsInstanceDataLut[u32Instance].stcInstance.pstcLinInstance) + { + pstcInternDataPtr = &m_astcMfsInstanceDataLut[u32Instance].stcInternData; + break; + } + } + + } + + return (pstcInternDataPtr); +} /* MfsGetInternDataPtr */ + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +/** + ****************************************************************************** + ** \brief LIN receive interrupt service routine. + ** + ** \param pstcLin Pointer to LIN instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Transmit Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsLinIrqHandlerRx( volatile stc_mfsn_lin_t* pstcLin, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcLin) && (NULL != pstcMfsInternData)) + { + if (NULL != pstcMfsInternData->stcLinInternIrqCb.pfnRxIrqCb) + { + pstcMfsInternData->stcLinInternIrqCb.pfnRxIrqCb(); + } + } +} /* MfsIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief LIN transmit interrupt service routine. + ** + ** \param pstcLin Pointer to LIN instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Transmit Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsLinIrqHandlerTx( volatile stc_mfsn_lin_t* pstcLin, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if ((NULL != pstcLin) && (NULL != pstcMfsInternData)) + { + if(1u == pstcLin->SSR_f.TDRE) + { + if (NULL != pstcMfsInternData->stcLinInternIrqCb.pfnTxIrqCb) + { + pstcMfsInternData->stcLinInternIrqCb.pfnTxIrqCb(); + } + } + + if(1u == pstcLin->SSR_f.TBI) + { + if (NULL != pstcMfsInternData->stcLinInternIrqCb.pfnTxIdleIrqCb) + { + pstcMfsInternData->stcLinInternIrqCb.pfnTxIdleIrqCb(); + } + } + + if(1u == pstcLin->FCR_f.FDRQ) + { + if (NULL != pstcMfsInternData->stcLinInternIrqCb.pfnTxFifoIrqCb) + { + pstcMfsInternData->stcLinInternIrqCb.pfnTxFifoIrqCb(); + } + + pstcLin->FCR_f.FDRQ = 0u; + } + + + } +} /* MfsIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief LIN status interrupt service routine. + ** + ** \param pstcLin Pointer to LIN instance + ** \param pstcMfsInternData Pointer to MFS internal data structure + ** + ** This function is called on Transmit Interrupt set by the MFS. + ** + ******************************************************************************/ +void MfsLinIrqHandlerStatus( volatile stc_mfsn_lin_t* pstcLin, + stc_mfs_intern_data_t* pstcMfsInternData) +{ + if(1u == pstcLin->SSR_f.LBD) + { + pstcLin->SSR_f.LBD = 0u; + if (NULL != pstcMfsInternData->stcLinInternIrqCb.pfnLinBreakIrqCb) + { + pstcMfsInternData->stcLinInternIrqCb.pfnLinBreakIrqCb(); + } + } +} + +/** + ****************************************************************************** + ** \brief Enable LIN interrupts + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enIrqSel Enumeration of LIN interrupts + ** \arg LinTxIrq TX interrupt of LIN + ** \arg LinRxIrq RX interrupt of LIN + ** \arg LinBreakIrq LIN break interrupt + ** \arg LinTxIdleIrq TX idle interrupt of LIN + ** \arg LinTxFifoIrq TX FIFO interrupt of LIN + ** + ** \retval Ok Interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_EnableIrq(volatile stc_mfsn_lin_t* pstcLin, + en_lin_irq_sel_t enIrqSel) +{ + if (NULL == pstcLin) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case LinTxIrq: + pstcLin->SCR_f.TIE = 1u; + break; + case LinRxIrq: + pstcLin->SCR_f.RIE = 1u; + break; + case LinBreakIrq: + pstcLin->ESCR_f.LBIE = 1u; + break; + case LinTxIdleIrq: + pstcLin->SCR_f.TBIE = 1u; + break; + case LinTxFifoIrq: + pstcLin->FCR_f.FTIE = 1u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable LIN interrupts + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enIrqSel Enumeration of LIN interrupts + ** \arg LinTxIrq TX interrupt of LIN + ** \arg LinRxIrq RX interrupt of LIN + ** \arg LinBreakIrq LIN break interrupt + ** \arg LinTxIdleIrq TX idle interrupt of LIN + ** \arg LinTxFifoIrq TX FIFO interrupt of LIN + ** + ** \retval Ok Interrupts has been disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_DisableIrq(volatile stc_mfsn_lin_t* pstcLin, + en_lin_irq_sel_t enIrqSel) +{ + if (NULL == pstcLin) + { + return (ErrorInvalidParameter); + } + + switch (enIrqSel) + { + case LinTxIrq: + pstcLin->SCR_f.TIE = 0u; + break; + case LinRxIrq: + pstcLin->SCR_f.RIE = 0u; + break; + case LinBreakIrq: + pstcLin->ESCR_f.LBIE = 0u; + break; + case LinTxIdleIrq: + pstcLin->SCR_f.TBIE = 0u; + break; + case LinTxFifoIrq: + pstcLin->FCR_f.FTIE = 0u; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialization of a MFS module to activate as LIN. + ** + ** Set registers to active MFS as LIN. + ** + ** \param [in] pstcLin Pointer to LIN instance register area + ** \param [in] pstcConfig MFS LIN configuration + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Lin_Init( volatile stc_mfsn_lin_t* pstcLin, + const stc_mfs_lin_config_t* pstcConfig) +{ + stc_mfs_intern_data_t* pstcMfsInternData; + uint32_t u32DummyCnt = 100u; + uint8_t u8Ch; + + /* Preset local register variables to zero */ + stc_mfs_lin_smr_field_t stcSMR; + stc_mfs_lin_scr_field_t stcSCR; + stc_mfs_lin_escr_field_t stcESCR; + + PDL_ZERO_STRUCT(stcSMR); + PDL_ZERO_STRUCT(stcSCR); + PDL_ZERO_STRUCT(stcESCR); + + /* Calculate the channel number */ + u8Ch = LinInstanceToIndex(pstcLin); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsLinGetInternDataPtr(pstcLin); + + /* Parameter check and get ptr to internal data struct */ + if ((NULL == pstcMfsInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* Set MFS mode in the internal structure */ + pstcMfsInternData->enMode = MfsLinMode; + + /* First of all set MFS to Asynchronous mode 0 */ + pstcLin->SMR = 0u; + + /* Then we disable TX and RX for safe operation */ + pstcLin->SCR = 0u; + + /* Clear MFS by setting the Software Reset bit */ + pstcLin->SCR_f.UPCL = TRUE; + + /* Set LIN mode to HW and preset variable */ + stcSMR.MD = 3u; + + /* Enable serial output */ + stcSMR.SOE = TRUE; + + /* Operation Mode Selection */ + switch (pstcConfig->enMsMode) + { + /* Master */ + case LinMasterMode: + stcSCR.MS = FALSE; + break; + /* Slave */ + case LinSlaveMode: + stcSCR.MS = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + + /* Set LIN master configuration */ + if (LinMasterMode == pstcConfig->enMsMode) + { + /* Stop bits configuration */ + switch (pstcConfig->enStopBits) + { + case LinOneStopBit: + stcSMR.SBL = FALSE; + stcESCR.ESBL = FALSE; + break; + case LinTwoStopBits: + stcSMR.SBL = TRUE; + stcESCR.ESBL = FALSE; + break; + case LinThreeStopBits: + stcSMR.SBL = FALSE; + stcESCR.ESBL = TRUE; + break; + case LinFourStopBits: + stcSMR.SBL = TRUE; + stcESCR.ESBL = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + /* Break length configuration */ + switch (pstcConfig->enBreakLength) + { + case LinBreakLength13: + stcESCR.LBL = 0u; + break; + case LinBreakLength14: + stcESCR.LBL = 1u; + break; + case LinBreakLength15: + stcESCR.LBL = 2u; + break; + case LinBreakLength16: + stcESCR.LBL = 3u; + break; + default: + return (ErrorInvalidParameter); + } + /* Delimiter length configuration */ + switch (pstcConfig->enDelimiterLength) + { + case LinDelimiterLength1: + stcESCR.DEL = 0u; + break; + case LinDelimiterLength2: + stcESCR.DEL = 1u; + break; + case LinDelimiterLength3: + stcESCR.DEL = 2u; + break; + case LinDelimiterLength4: + stcESCR.DEL = 3u; + break; + default: + return (ErrorInvalidParameter); + } + } + + /* Set Baudrate */ + (void)Mfs_Lin_SetBaudRate(pstcLin, pstcConfig->u32BaudRate); + + /* Set registers value */ + pstcLin->SMR_f = stcSMR; + pstcLin->SCR_f = stcSCR; + pstcLin->ESCR_f = stcESCR; + + /* Set external clock */ + pstcLin->BGR_f.EXT = ((pstcConfig->bUseExtClk == TRUE) ? 1u : 0u); + + while(u32DummyCnt--) + { + pstcLin->SSR_f.LBD = 0u; + } + + if(pstcConfig->pstcFifoConfig != NULL) + { + /* Reset FIFO */ + pstcLin->FCR_f.FCL1 = 1u; + pstcLin->FCR_f.FCL2 = 1u; + /* Enable FIFO receive Idle detection */ + pstcLin->FCR_f.FRIIE = 1u; + /* Selection TX and RX FIFO */ + switch(pstcConfig->pstcFifoConfig->enFifoSel) + { + case MfsTxFifo1RxFifo2: + pstcLin->FCR_f.FSEL = 0u; + break; + case MfsTxFifo2RxFifo1: + pstcLin->FCR_f.FSEL = 1u; + break; + default: + return (ErrorInvalidParameter); + } + /* Set FIFO count */ + pstcLin->FBYTE1 = pstcConfig->pstcFifoConfig->u8ByteCount1; + pstcLin->FBYTE2 = pstcConfig->pstcFifoConfig->u8ByteCount2; + /* Enable FIFO */ + pstcLin->FCR_f.FE1 = 1u; + pstcLin->FCR_f.FE2 = 1u; + } + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + /* Configure interrupt */ + if(NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTxIrq) + { + pstcLin->SCR_f.TIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bRxIrq) + { + pstcLin->SCR_f.RIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxIdleIrq) + { + pstcLin->SCR_f.TBIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTxFifoIrq) + { + pstcLin->FCR_f.FTIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bLinBreakIrq) + { + pstcLin->ESCR_f.LBIE = 1u; + } + } + + /* Configure interrupt callback */ + if(NULL != pstcConfig->pstcIrqCb) + { + pstcMfsInternData->stcLinInternIrqCb.pfnRxIrqCb = pstcConfig->pstcIrqCb->pfnRxIrqCb; + pstcMfsInternData->stcLinInternIrqCb.pfnTxIrqCb = pstcConfig->pstcIrqCb->pfnTxIrqCb; + pstcMfsInternData->stcLinInternIrqCb.pfnTxIdleIrqCb = pstcConfig->pstcIrqCb->pfnTxIdleIrqCb; + pstcMfsInternData->stcLinInternIrqCb.pfnTxFifoIrqCb = pstcConfig->pstcIrqCb->pfnTxFifoIrqCb; + pstcMfsInternData->stcLinInternIrqCb.pfnLinBreakIrqCb = pstcConfig->pstcIrqCb->pfnLinBreakIrqCb; + } + + /* Configure NVIC */ + if(TRUE == pstcConfig->bTouchNvic) + { + MfsInitNvic(u8Ch, FALSE); + MfsInitNvic(u8Ch, TRUE); + } +#endif + + return (Ok); +} /* Mfs_Lin_Init */ + +/** + ****************************************************************************** + ** \brief Deinitialisation of a MFS module activating as LIN. + ** + ** All used LIN register are reset to their default values. + ** + ** \param [in] pstcLin Pointer to LIN instance register area + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Process successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Lin_DeInit(volatile stc_mfsn_lin_t* pstcLin, boolean_t bTouchNvic) +{ + en_result_t enResult; + stc_mfs_intern_data_t* pstcMfsInternData; + uint8_t u8Ch; + + /* Calculate the channel number */ + u8Ch = LinInstanceToIndex(pstcLin); + + if(u8Ch > 15u) + { + return (ErrorInvalidParameter); + } + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsInternData = MfsLinGetInternDataPtr(pstcLin); + /* ... and check */ + if (NULL == pstcMfsInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + pstcLin->SCR_f.TXE = FALSE; + pstcLin->SCR_f.RXE = FALSE; + + /* Baud Rate Generation Reload Reset */ + pstcLin->BGR = 0u; + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcLin->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcLin->SCR = 0u; + + /* Clear reception Errors */ + pstcLin->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcLin->SSR = 0u; + pstcLin->ESCR = 0u; + pstcLin->FCR = 0u; + + + /* Clear MFS by setting the Software Reset bit */ + pstcLin->SCR_f.UPCL = TRUE; + +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + if(TRUE == bTouchNvic) + { + MfsDeInitNvic(u8Ch, FALSE); + MfsDeInitNvic(u8Ch, TRUE); + } +#endif + enResult = Ok; + } + + return (enResult); +} /* Mfs_Lin_DeInit */ + + +/** + ****************************************************************************** + ** \brief Set the baudrate of LIN + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] u32BaudRate Baudrate value [bps] + ** + ** \retval Ok LIN baud rate has been successfully modified + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - u32BaudRate < 3 + ** \note + ** The LIN baud rate can be initialized in the Mfs_Lin_Init() and be modified + ** with the function. + ** + ******************************************************************************/ +en_result_t Mfs_Lin_SetBaudRate(volatile stc_mfsn_lin_t* pstcLin, + uint32_t u32BaudRate) +{ + uint32_t u32Pclk1; + + SystemCoreClockUpdate(); + if ((NULL == pstcLin) || (u32BaudRate < 3u)) + { + return ErrorInvalidParameter; + } +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + u32Pclk1 = SystemCoreClock /(1ul << (FM_CRG->APBC1_PSR & 0x03u)); /* MFS is attached on APB1 bus for FM0+ */ +#else + u32Pclk1 = SystemCoreClock /(1ul << (FM_CRG->APBC2_PSR & 0x03u)); /* MFS is attached on APB2 bus for FM3 and FM4 */ +#endif + pstcLin->BGR_f.BGR = (u32Pclk1/u32BaudRate) - 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Generate LIN break filed + ** + ** \param [in] pstcLin Pointer to LIN instance + ** + ** \retval Ok Break filed has been successfully generated + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_GenerateBreakField(volatile stc_mfsn_lin_t* pstcLin) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + pstcLin->SCR_f.LBR = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable LIN functions + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enFunc LIN function types + ** \arg LinTx LIN transfer function + ** \arg LinRx LIN receive function + ** + ** \retval Ok Function has been enabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_EnableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + switch(enFunc) + { + case LinTx: + pstcLin->SCR_f.TXE = 1u; + break; + case LinRx: + pstcLin->SCR_f.RXE = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable LIN functions + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enFunc LIN function types + ** \arg LinTx LIN transfer function + ** \arg LinRx LIN receive function + ** + ** \retval Ok Function has been disabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_DisableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + switch(enFunc) + { + case LinTx: + pstcLin->SCR_f.TXE = 0u; + break; + case LinRx: + pstcLin->SCR_f.RXE = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get status of LIN according to status type + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enStatus LIN status type + ** \arg LinParityError LIN parity error + ** \arg LinFrameError LIN frame error + ** \arg LinRxFull LIN receive buffer full + ** \arg LinTxEmpty LIN tranfer buffer empty + ** \arg LinTxIdle LIN tranfer idle status + ** \arg LinBreakFlag LIN break field detection flag + ** \arg LinTxFifoRequest LIN transfer FIFO request + ** + ** \retval FALSE If one of following conditions are met: + ** - No LIN parity error [enStatus = LinParityError] + ** - No LIN frame error [enStatus = LinFrameError] + ** - LIN receive buffer is not full [enStatus = LinRxFull] + ** - LIN tranfer buffer is not empty [enStatus = LinTxEmpty] + ** - LIN tranfer is on-going [enStatus = LinTxIdle] + ** - LIN break field is not detected [enStatus = LinBreakFlag] + ** - No LIN transfer FIFO request [enStatus = LinTxFifoRequest] + ** \retval TRUE If one of following conditions are met: + ** - LIN parity error occurs [enStatus = LinParityError] + ** - LIN frame error occurs [enStatus = LinFrameError] + ** - LIN receive buffer is full [enStatus = LinRxFull] + ** - LIN tranfer buffer is empty [enStatus = LinTxEmpty] + ** - LIN tranfer is idle [enStatus = LinTxIdle] + ** - LIN break field is detected [enStatus = LinBreakFlag] + ** - LIN transfer FIFO request issues [enStatus = LinTxFifoRequest] + ** + ******************************************************************************/ +boolean_t Mfs_Lin_GetStatus(volatile stc_mfsn_lin_t* pstcLin, + en_lin_status_t enStatus) +{ + boolean_t bResult = FALSE; + + switch(enStatus) + { + case LinFrameError: + bResult = (1u == pstcLin->SSR_f.FRE) ? TRUE : FALSE; + break; + case LinOverrunError: + bResult = (1u == pstcLin->SSR_f.ORE) ? TRUE : FALSE; + break; + case LinRxFull: + bResult = (1u == pstcLin->SSR_f.RDRF) ? TRUE : FALSE; + break; + case LinTxEmpty: + bResult = (1u == pstcLin->SSR_f.TDRE) ? TRUE : FALSE; + break; + case LinTxIdle: + bResult = (1u == pstcLin->SSR_f.TBI) ? TRUE : FALSE; + break; + case LinBreakFlag: + bResult = (1u == pstcLin->SSR_f.LBD) ? TRUE : FALSE; + break; + case LinTxFifoRequest: + bResult = (1u == pstcLin->FCR_f.FDRQ) ? TRUE : FALSE; + break; + default: + break; + } + + return bResult; +} + +/** + ****************************************************************************** + ** \brief Clear status of LIN according to status type + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enStatus LIN status type + ** \arg LinParityError LIN parity error + ** \arg LinFrameError LIN frame error + ** \arg LinRxFull LIN receive buffer full + ** \arg LinTxEmpty LIN tranfer buffer empty + ** \arg LinTxIdle LIN tranfer idle status + ** \arg LinBreakFlag LIN break field detection flag + ** \arg LinTxFifoRequest LIN transfer FIFO request + ** + ** \retval Ok Status has been cleared normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** \note The following status can only be cleared by hardware behavior: + ** - LinRxFull + ** - LinTxEmpty + ** - LinTxIdle + ** + ******************************************************************************/ +en_result_t Mfs_Lin_ClrStatus(volatile stc_mfsn_lin_t* pstcLin, + en_lin_status_t enStatus) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + switch(enStatus) + { + case LinFrameError: + case LinOverrunError: + pstcLin->SSR_f.REC = 1u; + break; + case LinRxFull: + case LinTxEmpty: + case LinTxIdle: + break; + case LinBreakFlag: + pstcLin->SSR_f.LBD = 0u; + break; + case LinTxFifoRequest: + pstcLin->FCR_f.FDRQ = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write LIN data buffer + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] Data Data to be sent + ** + ** \retval Ok Data has been successfully sent + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_SendData(volatile stc_mfsn_lin_t* pstcLin, uint8_t Data) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + pstcLin->TDR = Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read LIN data buffer + ** + ** \param [in] pstcLin Pointer to LIN instance + ** + ** \retval Receive data + ** + ******************************************************************************/ +uint8_t Mfs_Lin_ReceiveData(volatile stc_mfsn_lin_t* pstcLin) +{ + return (pstcLin->RDR); +} + +/** + ****************************************************************************** + ** \brief Reset LIN FIFO + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval Ok FIFO has been successfully reset + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_ResetFifo (volatile stc_mfsn_lin_t* pstcLin, + en_mfs_fifo_t enFifo) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcLin->FCR_f.FCL1 = 1u; + break; + case MfsFifo2: + pstcLin->FCR_f.FCL2 = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set LIN FIFO count + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** \param [in] u8Count FIFO count + ** + ** \retval Ok FIFO count has been successfully set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** + ******************************************************************************/ +en_result_t Mfs_Lin_SetFifoCount(volatile stc_mfsn_lin_t* pstcLin, + en_mfs_fifo_t enFifo, + uint8_t u8Count) +{ + if (NULL == pstcLin) + { + return ErrorInvalidParameter; + } + + switch(enFifo) + { + case MfsFifo1: + pstcLin->FBYTE1 = u8Count; + break; + case MfsFifo2: + pstcLin->FBYTE2 = u8Count; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get LIN FIFO count + ** + ** \param [in] pstcLin Pointer to LIN instance + ** \param [in] enFifo FIFO1 or FIFO2 + ** + ** \retval FIFO count + ** + ** This function gets the current data count in selected FIFO. + ** + ** \note 0xFF will be return value if FIFO index is error. + ** + ******************************************************************************/ +uint8_t Mfs_Lin_GetFifoCount(volatile stc_mfsn_lin_t* pstcLin, + en_mfs_fifo_t enFifo) +{ + uint8_t u8FifoCnt = 0xFFu; + + switch(enFifo) + { + case MfsFifo1: + u8FifoCnt = pstcLin->FBYTE1; + break; + case MfsFifo2: + u8FifoCnt = pstcLin->FBYTE2; + break; + default: + break; + } + + return u8FifoCnt; +} + +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mfs/mfs.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mfs/mfs.h new file mode 100644 index 0000000000..856572b968 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mfs/mfs.h @@ -0,0 +1,1417 @@ +/******************************************************************************* +* \file mfs.h +* +* \version 1.20 +* +* \brief Headerfile for MFS functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MFS_H__ +#define __MFS_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) + +#if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_OFF) && \ + (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_OFF) && \ + (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_OFF) && \ + (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_OFF) + #error "please enable at least one MFS Mode in pdl_user.h" +#endif + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupMFS Multi-Functional Serial interface (MFS) +* \{ +* \defgroup GroupMFS_Macros Macros +* \defgroup GroupMFS_Functions Functions +* \defgroup GroupMFS_GlobalVariables Global Variables +* \defgroup GroupMFS_DataStructures Data Structures +* \defgroup GroupMFS_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupMFS +* \{ +* The Multi-function Serial (MFS) peripheral allows you to implement several +* communication protocols. You can configure the MFS to implement the following +* serial communication interfaces: +* * UART +* * CSIO (supports SPI and I2S) +* * I2C +* * LIN +* The FM family microcontrollers and the PDL support up to 16 MFS channels. +* The number of available channels varies among processor series. You configure the +* individual channels independently. This means that you can implement an arbitrary mix +* of communication protocols in your firmware.
+* +* UART
+* The Universal Asynchronous Receiver/Transmitter (UART) has the following features:
+* * Full duplex double buffer +* * Transmit/receive FIFO (up to 128 bytes each) +* * Parity can be enabled or disabled. +* * Built-in dedicated baud rate generator +* * External clock available as a serial clock +* * Supports bidirectional communications (normal mode) +* * Supports master/slave communications (multi-processor mode) +* * Various error detection functions (parity errors, framing errors, and +* overrun errors) +* +* CSIO
+* The Clock Synchronous Serial Interface (CSIO) supports both SPI and I2S +* communication. It has the following features: +* * Full duplex double buffer +* * Transmit/receive FIFO (up to 128 bytes each) +* * Dedicated baud rate generator +* * Overrun error detection function +* * Serial chip select function (ch1 and ch3 only) +* * Data length: 5 to 16 bits +* +* I2C
+* The Inter-Integrated Circuit (I2C) interface mode enables communication via the I2C protocol. It +* operates as a master/slave device on the I2C bus. I2C mode has these features: +* * Full duplex double buffer +* * Transmit/receive FIFO (up to 128 bytes each) +* * Dedicated baud rate generator +* * Supports Standard-mode (max 100 kbps) and Fast-mode (max 400 kbps) +* * Synchronous communication +* * Data length: 8 bits +* +* LIN
+* The Local Interconnect Network (LIN) interface mode enables communication via the LIN protocol.
+* LIN mode has the following features: +* * Supports LIN protocol version.2.1 +* * Full duplex double buffer +* * Transmit/receive FIFO (up to 128 bytes each) +* * Supports Master/Slave mode +* * LIN break field generation function (The length is variable between 13 bits +* and 16 bits) +* * LIN break delimiter generation function (The length is variable between 1 +* bit and 4 bits) +* * Various error detection functions available (parity errors, framing errors, +* and overrun errors) +* +* \section SectionMFS_ConfigurationConsideration Configuration Consideration +* To set up an MFS instance you provide configuration parameters in the configuration +* structure of the type stc_mfs_xxx_config_t. Then call Mfs_Xxx_Init(). Where xxx is one of +* uart, i2c, csio, or lin. In the Mfs_xxx_Init() call you provide the base hardware address +* for the MFS channel (0-15) you are using (e.g. &UART7, or &CSIO9). These constants are defined +* in the mfs.h file.
+* After initializing, you must call Mfs_Xxx_EnableFunc() to enable transmit or receive. Use the +* correct enumerated constant for your mode of operation and function. For example: +* * Mfs_Uart_EnableFunc(&UART7, UartTx); +* * Mfs_Csio_EnableFunc(&CSIO9, CsioRx); +* +* \section SectionMFS_MoreInfo More Information +* For more information on the MFS peripheral, refer to:
+* FM0+ Peripheral Manual - Communication Subsystem TRM.pdf
+* FM4 Peripheral Manual - Communication Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupMFS_Macros +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) + #define stc_mfsn_uart_t FM_MFS_UART_TypeDef + + #define UART0 (*((volatile stc_mfsn_uart_t *) FM_MFS0_UART_BASE)) + #define UART1 (*((volatile stc_mfsn_uart_t *) FM_MFS1_UART_BASE)) + #define UART2 (*((volatile stc_mfsn_uart_t *) FM_MFS2_UART_BASE)) + #define UART3 (*((volatile stc_mfsn_uart_t *) FM_MFS3_UART_BASE)) + #define UART4 (*((volatile stc_mfsn_uart_t *) FM_MFS4_UART_BASE)) + #define UART5 (*((volatile stc_mfsn_uart_t *) FM_MFS5_UART_BASE)) + #define UART6 (*((volatile stc_mfsn_uart_t *) FM_MFS6_UART_BASE)) + #define UART7 (*((volatile stc_mfsn_uart_t *) FM_MFS7_UART_BASE)) + #define UART8 (*((volatile stc_mfsn_uart_t *) FM_MFS8_UART_BASE)) + #define UART9 (*((volatile stc_mfsn_uart_t *) FM_MFS9_UART_BASE)) + #define UART10 (*((volatile stc_mfsn_uart_t *) FM_MFS10_UART_BASE)) + #define UART11 (*((volatile stc_mfsn_uart_t *) FM_MFS11_UART_BASE)) + #define UART12 (*((volatile stc_mfsn_uart_t *) FM_MFS12_UART_BASE)) + #define UART13 (*((volatile stc_mfsn_uart_t *) FM_MFS13_UART_BASE)) + #define UART14 (*((volatile stc_mfsn_uart_t *) FM_MFS14_UART_BASE)) + #define UART15 (*((volatile stc_mfsn_uart_t *) FM_MFS15_UART_BASE)) +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) + #define stc_mfsn_csio_t FM_MFS_CSIO_TypeDef + + #define CSIO0 (*((volatile stc_mfsn_csio_t *) FM_MFS0_CSIO_BASE)) + #define CSIO1 (*((volatile stc_mfsn_csio_t *) FM_MFS1_CSIO_BASE)) + #define CSIO2 (*((volatile stc_mfsn_csio_t *) FM_MFS2_CSIO_BASE)) + #define CSIO3 (*((volatile stc_mfsn_csio_t *) FM_MFS3_CSIO_BASE)) + #define CSIO4 (*((volatile stc_mfsn_csio_t *) FM_MFS4_CSIO_BASE)) + #define CSIO5 (*((volatile stc_mfsn_csio_t *) FM_MFS5_CSIO_BASE)) + #define CSIO6 (*((volatile stc_mfsn_csio_t *) FM_MFS6_CSIO_BASE)) + #define CSIO7 (*((volatile stc_mfsn_csio_t *) FM_MFS7_CSIO_BASE)) + #define CSIO8 (*((volatile stc_mfsn_csio_t *) FM_MFS8_CSIO_BASE)) + #define CSIO9 (*((volatile stc_mfsn_csio_t *) FM_MFS9_CSIO_BASE)) + #define CSIO10 (*((volatile stc_mfsn_csio_t *) FM_MFS10_CSIO_BASE)) + #define CSIO11 (*((volatile stc_mfsn_csio_t *) FM_MFS11_CSIO_BASE)) + #define CSIO12 (*((volatile stc_mfsn_csio_t *) FM_MFS12_CSIO_BASE)) + #define CSIO13 (*((volatile stc_mfsn_csio_t *) FM_MFS13_CSIO_BASE)) + #define CSIO14 (*((volatile stc_mfsn_csio_t *) FM_MFS14_CSIO_BASE)) + #define CSIO15 (*((volatile stc_mfsn_csio_t *) FM_MFS15_CSIO_BASE)) +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) + #define stc_mfsn_i2c_t FM_MFS_I2C_TypeDef + + #define I2C0 (*((volatile stc_mfsn_i2c_t *) FM_MFS0_I2C_BASE)) + #define I2C1 (*((volatile stc_mfsn_i2c_t *) FM_MFS1_I2C_BASE)) + #define I2C2 (*((volatile stc_mfsn_i2c_t *) FM_MFS2_I2C_BASE)) + #define I2C3 (*((volatile stc_mfsn_i2c_t *) FM_MFS3_I2C_BASE)) + #define I2C4 (*((volatile stc_mfsn_i2c_t *) FM_MFS4_I2C_BASE)) + #define I2C5 (*((volatile stc_mfsn_i2c_t *) FM_MFS5_I2C_BASE)) + #define I2C6 (*((volatile stc_mfsn_i2c_t *) FM_MFS6_I2C_BASE)) + #define I2C7 (*((volatile stc_mfsn_i2c_t *) FM_MFS7_I2C_BASE)) + #define I2C8 (*((volatile stc_mfsn_i2c_t *) FM_MFS8_I2C_BASE)) + #define I2C9 (*((volatile stc_mfsn_i2c_t *) FM_MFS9_I2C_BASE)) + #define I2C10 (*((volatile stc_mfsn_i2c_t *) FM_MFS10_I2C_BASE)) + #define I2C11 (*((volatile stc_mfsn_i2c_t *) FM_MFS11_I2C_BASE)) + #define I2C12 (*((volatile stc_mfsn_i2c_t *) FM_MFS12_I2C_BASE)) + #define I2C13 (*((volatile stc_mfsn_i2c_t *) FM_MFS13_I2C_BASE)) + #define I2C14 (*((volatile stc_mfsn_i2c_t *) FM_MFS14_I2C_BASE)) + #define I2C15 (*((volatile stc_mfsn_i2c_t *) FM_MFS15_I2C_BASE)) +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) + #define stc_mfsn_lin_t FM_MFS_LIN_TypeDef + + #define LIN0 (*((volatile stc_mfsn_lin_t *) FM_MFS0_LIN_BASE)) + #define LIN1 (*((volatile stc_mfsn_lin_t *) FM_MFS1_LIN_BASE)) + #define LIN2 (*((volatile stc_mfsn_lin_t *) FM_MFS2_LIN_BASE)) + #define LIN3 (*((volatile stc_mfsn_lin_t *) FM_MFS3_LIN_BASE)) + #define LIN4 (*((volatile stc_mfsn_lin_t *) FM_MFS4_LIN_BASE)) + #define LIN5 (*((volatile stc_mfsn_lin_t *) FM_MFS5_LIN_BASE)) + #define LIN6 (*((volatile stc_mfsn_lin_t *) FM_MFS6_LIN_BASE)) + #define LIN7 (*((volatile stc_mfsn_lin_t *) FM_MFS7_LIN_BASE)) + #define LIN8 (*((volatile stc_mfsn_lin_t *) FM_MFS8_LIN_BASE)) + #define LIN9 (*((volatile stc_mfsn_lin_t *) FM_MFS9_LIN_BASE)) + #define LIN10 (*((volatile stc_mfsn_lin_t *) FM_MFS10_LIN_BASE)) + #define LIN11 (*((volatile stc_mfsn_lin_t *) FM_MFS11_LIN_BASE)) + #define LIN12 (*((volatile stc_mfsn_lin_t *) FM_MFS12_LIN_BASE)) + #define LIN13 (*((volatile stc_mfsn_lin_t *) FM_MFS13_LIN_BASE)) + #define LIN14 (*((volatile stc_mfsn_lin_t *) FM_MFS14_LIN_BASE)) + #define LIN15 (*((volatile stc_mfsn_lin_t *) FM_MFS15_LIN_BASE)) +#endif + + +#define MFS_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) + +#define MFS0_DATA_REG_ADDR (uint32_t)(&FM_MFS0_UART->TDR) +#define MFS1_DATA_REG_ADDR (uint32_t)(&FM_MFS1_UART->TDR) +#define MFS2_DATA_REG_ADDR (uint32_t)(&FM_MFS2_UART->TDR) +#define MFS3_DATA_REG_ADDR (uint32_t)(&FM_MFS3_UART->TDR) +#define MFS4_DATA_REG_ADDR (uint32_t)(&FM_MFS4_UART->TDR) +#define MFS5_DATA_REG_ADDR (uint32_t)(&FM_MFS5_UART->TDR) +#define MFS6_DATA_REG_ADDR (uint32_t)(&FM_MFS6_UART->TDR) +#define MFS7_DATA_REG_ADDR (uint32_t)(&FM_MFS7_UART->TDR) +#define MFS8_DATA_REG_ADDR (uint32_t)(&FM_MFS8_UART->TDR) +#define MFS9_DATA_REG_ADDR (uint32_t)(&FM_MFS9_UART->TDR) +#define MFS10_DATA_REG_ADDR (uint32_t)(&FM_MFS10_UART->TDR) +#define MFS11_DATA_REG_ADDR (uint32_t)(&FM_MFS11_UART->TDR) +#define MFS12_DATA_REG_ADDR (uint32_t)(&FM_MFS12_UART->TDR) +#define MFS13_DATA_REG_ADDR (uint32_t)(&FM_MFS13_UART->TDR) +#define MFS14_DATA_REG_ADDR (uint32_t)(&FM_MFS14_UART->TDR) +#define MFS15_DATA_REG_ADDR (uint32_t)(&FM_MFS15_UART->TDR) + +/** \} GroupMFS_Macros */ + +/** +* \addtogroup GroupMFS_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/****************************************************************************** + * MFS FIFO type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Mfs FIFO Selection + ******************************************************************************/ +typedef enum en_mfs_fifo_sel +{ + MfsTxFifo1RxFifo2 = 0u, ///< Transmit FIFO:FIFO1, Received FIFO:FIFO2 + MfsTxFifo2RxFifo1 = 1u, ///< Transmit FIFO:FIFO2, Received FIFO:FIFO1 +} en_mfs_fifo_sel_t; + +/** + ****************************************************************************** + ** \brief Mfs FIFO Number + ******************************************************************************/ +typedef enum en_mfs_fifo +{ + MfsFifo1 = 0u, ///< FIFO No.1 + MfsFifo2 = 1u, ///< FIFO No.2 +} en_mfs_fifo_t; + +/****************************************************************************** + * UART type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief MFS UART mode + ******************************************************************************/ +typedef enum en_mfs_uart_mode +{ + UartNormal = 0u, ///< Normal mode + UartMulti = 1u, ///< Multi-Processor Mode +} en_uart_mode_t; + +/** + ****************************************************************************** + ** \brief UART data length + ******************************************************************************/ +typedef enum en_uart_data_len +{ + UartEightBits = 0u, ///< 8 Bit character length + UartFiveBits = 1u, ///< 5 Bit character length + UartSixBits = 2u, ///< 6 Bit character length + UartSevenBits = 3u, ///< 7 Bit character length + UartNineBits = 4u, ///< 9 Bit character length +} en_uart_data_len_t; + +/** + ****************************************************************************** + ** \brief UART parity format + ******************************************************************************/ +typedef enum en_uart_parity +{ + UartParityNone = 0u, ///< No parity bit is used. + UartParityEven = 2u, ///< Even parity bit is used. + UartParityOdd = 3u, ///< Odd parity bit is used. +} en_uart_parity_t; + +/** + ****************************************************************************** + ** \brief UART stop bits length + ******************************************************************************/ +typedef enum en_uart_stop_bit +{ + UartOneStopBit = 0u, ///< 1 Stop Bit + UartTwoStopBits = 1u, ///< 2 Stop Bits + UartThreeStopBits = 2u, ///< 3 Stop Bits + UartFourStopBits = 3u, ///< 4 Stop Bits +} en_uart_stop_bit_t; + +/** + ****************************************************************************** + ** \brief UART data direction + ******************************************************************************/ +typedef enum en_uart_data_dir +{ + UartDataLsbFirst = 0u, ///< LSB first + UartDataMsbFirst = 1u, ///< MSB first +}en_uart_data_dir_t; + +/** + ****************************************************************************** + ** \brief UART functions + ******************************************************************************/ +typedef enum en_uart_func +{ + UartTx = 0u, ///< UART TX + UartRx = 1u, ///< UART RX + +}en_uart_func_t; + +/** + ****************************************************************************** + ** \brief UART interrupt selection + ******************************************************************************/ +typedef enum en_uart_irq_sel +{ + UartTxIrq = 0u, ///< UART TX interrupt + UartRxIrq = 1u, ///< UART RX interrupt + UartTxIdleIrq = 2u, ///< UART TX idle interrupt + UartTxFifoIrq = 3u, ///< UART TX FIFO interrupt + +}en_uart_irq_sel_t; + +/** + ****************************************************************************** + ** \brief UART status types + ******************************************************************************/ +typedef enum en_uart_status +{ + UartParityError = 0u, ///< Parity error + UartFrameError = 1u, ///< Frame error + UartOverrunError = 2u, ///< Overrun error + UartRxFull = 3u, ///< RX completion + UartTxEmpty = 4u, ///< TX buffer empty + UartTxIdle = 5u, ///< TX idle + UartTxFifoRequest = 6u, ///< TX FIFO request + +}en_uart_status_t; + +/****************************************************************************** + * CSIO type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief CSIO mode (Master/Slave) + ******************************************************************************/ +typedef enum en_csio_ms_mode +{ + CsioMaster = 0, ///< Master mode (generating serial clock) + CsioSlave = 1 ///< Slave mode (external serial clock) +} en_csio_ms_mode_t; + +/** + ****************************************************************************** + ** \brief CSIO active mode (Normal/SPI) + ******************************************************************************/ +typedef enum en_csio_act_mode +{ + CsioActNormalMode = 0u, ///< Normal mode + CsioActSpiMode = 1u, ///< SPI mode +} en_csio_act_mode_t; + +/** + ****************************************************************************** + ** \brief CSIO data length + ******************************************************************************/ +typedef enum en_csio_data_len +{ + CsioFiveBits = 0u, ///< 5 Bit character length + CsioSixBits = 1u, ///< 6 Bit character length + CsioSevenBits = 2u, ///< 7 Bit character length + CsioEightBits = 3u, ///< 8 Bit character length + CsioNineBits = 4u, ///< 9 Bit character length +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + CsioTenBits = 5u, ///< 10 Bit character length + CsioElevenBits = 6u, ///< 11 Bit character length + CsioTwelveBits = 7u, ///< 12 Bit character length + CsioThirteenBits = 8u, ///< 13 Bit character length + CsioFourteenBits = 9u, ///< 14 Bit character length + CsioFifteenBits = 10u, ///< 15 Bit character length + CsioSixteenBits = 11u, ///< 16 Bit character length +#endif +} en_csio_data_len_t; + +/** + ****************************************************************************** + ** \brief CSIO synchronous wait time + ******************************************************************************/ +typedef enum en_csio_sync_wait_time +{ + CsioSyncWaitZero = 0u, ///< 0 wait time insertion + CsioSyncWaitOne = 1u, ///< 1 wait time insertion + CsioSyncWaitTwo = 2u, ///< 2 wait time insertion + CsioSyncWaitThree = 3u, ///< 3 wait time insertion +} en_csio_sync_wait_time_t; + +/** + ****************************************************************************** + ** \brief CSIO bit direction + ******************************************************************************/ +typedef enum en_csio_data_dir +{ + CsioDataLsbFirst = 0u, ///< LSB first + CsioDataMsbFirst = 1u, ///< MSB first +}en_csio_data_dir_t; + +/** + ****************************************************************************** + ** \brief CSIO serial timer clock division + ******************************************************************************/ +typedef enum en_csio_timer_clk +{ + CsioTimerNoDiv = 0u, ///< Serial Timer clock = PCLK + CsioTimerDiv2 = 1u, ///< Serial Timer clock = PCLK/2 + CsioTimerDiv4 = 2u, ///< Serial Timer clock = PCLK/4 + CsioTimerDiv8 = 3u, ///< Serial Timer clock = PCLK/8 + CsioTimerDiv16 = 4u, ///< Serial Timer clock = PCLK/16 + CsioTimerDiv32 = 5u, ///< Serial Timer clock = PCLK/32 + CsioTimerDiv64 = 6u, ///< Serial Timer clock = PCLK/64 + CsioTimerDiv128 = 7u, ///< Serial Timer clock = PCLK/128 + CsioTimerDiv256 = 8u, ///< Serial Timer clock = PCLK/256 + +}en_csio_timer_clk_t; + +/** + ****************************************************************************** + ** \brief CSIO chip selection pin + ******************************************************************************/ +typedef enum en_cs_pin_sel +{ + CsPinScs0 = 0u, ///< Use SCS0 as chip selection pin + CsPinScs1 = 1u, ///< Use SCS1 as chip selection pin + CsPinScs2 = 2u, ///< Use SCS2 as chip selection pin + CsPinScs3 = 3u, ///< Use SCS3 as chip selection pin + +}en_cs_pin_sel_t; + +/** + ****************************************************************************** + ** \brief CSIO chip selection pin level + ** \note It is only available for SCS0 pin + ******************************************************************************/ +typedef enum en_cs_pin_level +{ + CsLowActive = 0u, ///< Set high as active level for SCS0 pin + CsHighActive = 1u, ///< Set low as active level for SCS0 pin + +}en_cs_pin_level_t; + +/** + ****************************************************************************** + ** \brief CSIO chip selection clock division + ******************************************************************************/ +typedef enum en_cs_timing_clk +{ + CsClkNoDiv = 0u, ///< Chip selection clock = PCLK + CsClkDiv2 = 1u, ///< Chip selection clock = PCLK/2 + CsClkDiv4 = 2u, ///< Chip selection clock = PCLK/4 + CsClkDiv8 = 3u, ///< Chip selection clock = PCLK/8 + CsClkDiv16 = 4u, ///< Chip selection clock = PCLK/16 + CsClkDiv32 = 5u, ///< Chip selection clock = PCLK/32 + CsClkDiv64 = 6u, ///< Chip selection clock = PCLK/64 + +}en_cs_timing_clk_t; + +/** + ****************************************************************************** + ** \brief CSIO function + ******************************************************************************/ +typedef enum en_csio_func +{ + CsioTx = 0u, ///< CSIO TX + CsioRx = 1u, ///< CSIO RX +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + CsioSerialTimer = 2u, ///< CSIO Serial TImer + CsioCsErrOccur = 3u, ///< CSIO chip selection error occurrance +#endif +}en_csio_func_t; + +/** + ****************************************************************************** + ** \brief CSIO interrupt selection + ******************************************************************************/ +typedef enum stc_csio_irq_sel +{ + CsioTxIrq = 0u, ///< CSIO TX interrupt + CsioRxIrq = 1u, ///< CSIO RX interrupt + CsioTxIdleIrq = 2u, ///< CSIO TX idle interrupt + CsioTxFifoIrq = 3u, ///< CSIO TX FIFO interrupt +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + CsioCsErrIrq = 4u, ///< CSIO chip selection interrupt + CsioSerialTimerIrq = 5u, ///< CSIO serial timer interrupt +#endif +}en_csio_irq_sel_t; + +/** + ****************************************************************************** + ** \brief CSIO status types + ******************************************************************************/ +typedef enum en_csio_status +{ + CsioOverrunError = 0u, ///< CSIO overrun error + CsioRxFull = 1u, ///< CSIO RX completion + CsioTxEmpty = 2u, ///< CSIO TX buffer empty + CsioTxIdle = 3u, ///< CSIO TX idle + CsioTxFifoRequest = 4u, ///< CSIO TX FIFO request +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + CsioCsErrIntFlag = 5u, ///< CSIO chip selection error occurrance + CsioTimerIntFlag = 6u, ///< CSIO serial timer interrupt +#endif +}en_csio_status_t; + +/****************************************************************************** + * I2C type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief I2C mode + ******************************************************************************/ +typedef enum en_i2c_mode +{ + I2cMaster = 0u, ///< I2C Master mode + I2cSlave = 1u, ///< I2C Slave mode + +}en_i2c_mode_t; + +/** + ****************************************************************************** + ** \brief I2C ACK types + ******************************************************************************/ +typedef enum en_i2c_ack +{ + I2cAck = 0u, ///< I2C normal ACK + I2cNAck = 1u, ///< I2C NACK + +}en_i2c_ack_t; + +/** + ****************************************************************************** + ** \brief I2C interrupt selection + ******************************************************************************/ +typedef enum en_i2c_irq_sel +{ + I2cTxIrq = 0u, ///< I2C TX interrupt + I2cRxIrq = 1u, ///< I2C RX interrupt + I2cTxIdleIrq = 2u, ///< I2C TX idle interrupt + I2cTxFifoIrq = 3u, ///< I2C TX FIFO interrupt + I2cTxRxIrq = 4u, ///< I2C TX and RX interrupt + I2cStopDetectIrq = 5u, ///< I2C stop condition interrupt + +}en_i2c_irq_sel_t; + +/** + ****************************************************************************** + ** \brief I2C status types + ******************************************************************************/ +typedef enum en_i2c_status +{ + I2cOverrunError = 0u, ///< I2C overrun error + I2cRxFull = 1u, ///< I2C RX buffer full + I2cTxEmpty = 2u, ///< I2C TX buffer empty + I2cTxIdle = 3u, ///< I2C TX idle + I2cTxFifoRequest = 4u, ///< I2C TX FIFO request + I2cFirstByteDetect = 5u, ///< I2C First byte detection + I2cReservedByteDetect = 6u, ///< I2C reserved byte detection + I2cStopDetect = 7u, ///< I2C stop condition detection + I2cBusStatus = 8u, ///< I2C Bus status + I2cBusErr = 9u, ///< I2C Bus error + I2cRxTxIrq = 10u, ///< I2C transimission or reception interrupt flag + I2cDevAddrMatch = 11u, ///< I2C received slave address matchs with pre-set address +}en_i2c_status_t; + +/** + ****************************************************************************** + ** \brief I2C data direction(used in slave mode) + ******************************************************************************/ +typedef enum en_i2c_data_dir +{ + i2c_master_tx_slave_rx = 0u, ///< Data from master to slave + i2c_slave_tx_master_rx = 1u, ///< Data from slave to master + +}en_i2c_data_dir_t; + +/****************************************************************************** + * LIN type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief MFS LIN mode (Master/Slave) + ******************************************************************************/ +typedef enum en_lin_ms_mode +{ + LinMasterMode = 0u, ///< LIN Master Mode + LinSlaveMode = 1u, ///< LIN Slave Mode +} en_lin_ms_mode_t; + +/** + ****************************************************************************** + ** \brief LIN stop bit length + ******************************************************************************/ +typedef enum en_lin_stop_bit +{ + LinOneStopBit = 0u, ///< 1 Stop Bit + LinTwoStopBits = 1u, ///< 2 Stop Bits + LinThreeStopBits = 2u, ///< 3 Stop Bits + LinFourStopBits = 3u, ///< 4 Stop Bits +} en_lin_stop_bit_t; + +/** + ****************************************************************************** + ** \brief Mfs Lin Break Generation Length (only applicable in LIN master mode) + ******************************************************************************/ +typedef enum en_lin_break_length +{ + LinBreakLength13 = 0u, ///< Lin Break Length 13 Bit Times + LinBreakLength14 = 1u, ///< Lin Break Length 14 Bit Times + LinBreakLength15 = 2u, ///< Lin Break Length 15 Bit Times + LinBreakLength16 = 3u, ///< Lin Break Length 16 Bit Times +} en_lin_break_len_t; + +/** + ****************************************************************************** + ** \brief Mfs Lin Break Delimiter Length (only applicable in LIN master mode) + ******************************************************************************/ +typedef enum en_lin_delimiter_length +{ + LinDelimiterLength1 = 0u, ///< Lin Break Delimiter Length 1 Bit Time + LinDelimiterLength2 = 1u, ///< Lin Break Delimiter Length 2 Bit Times + LinDelimiterLength3 = 2u, ///< Lin Break Delimiter Length 3 Bit Times + LinDelimiterLength4 = 3u, ///< Lin Break Delimiter Length 4 Bit Times +} en_lin_delimiter_len_t; + +/** + ****************************************************************************** + ** \brief LIN function + ******************************************************************************/ +typedef enum en_lin_func +{ + LinTx = 0u, ///< Lin TX + LinRx = 1u, ///< Lin RX + +}en_lin_func_t; + +/** + ****************************************************************************** + ** \brief LIN interrupt enumeration + ******************************************************************************/ +typedef enum en_lin_irq_sel +{ + LinTxIrq = 0u, ///< LIN TX interrupt + LinRxIrq = 1u, ///< LIN RX interrupt + LinBreakIrq = 2u, ///< LIN break field interrupt + LinTxIdleIrq = 3u, ///< LIN TX idle interrupt + LinTxFifoIrq = 4u, ///< LIN TX FIFO interrupt + +}en_lin_irq_sel_t; + +/** + ****************************************************************************** + ** \brief LIN status types + ******************************************************************************/ +typedef enum en_lin_status +{ + LinFrameError = 0u, ///< LIN Frame error + LinOverrunError = 1u, ///< LIN overrun error + LinRxFull = 2u, ///< LIN RX buffer full + LinTxEmpty = 3u, ///< LIN TX buffer empty + LinTxIdle = 4u, ///< LIN TX idle + LinBreakFlag = 5u, ///< LIN break field detection flag + LinTxFifoRequest = 6u, ///< LIN FIFO request + +}en_lin_status_t; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +/// Enumeration to define an index for each enabled MFS instance +typedef enum en_mfs_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) + MfsInstanceIndexMfs0, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) + MfsInstanceIndexMfs1, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) + MfsInstanceIndexMfs2, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) + MfsInstanceIndexMfs3, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) + MfsInstanceIndexMfs4, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) + MfsInstanceIndexMfs5, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) + MfsInstanceIndexMfs6, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) + MfsInstanceIndexMfs7, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) + MfsInstanceIndexMfs8, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) + MfsInstanceIndexMfs9, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) + MfsInstanceIndexMfs10, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) + MfsInstanceIndexMfs11, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) + MfsInstanceIndexMfs12, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) + MfsInstanceIndexMfs13, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) + MfsInstanceIndexMfs14, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) + MfsInstanceIndexMfs15, +#endif + MfsInstanceIndexMax, + MfsInstanceIndexUnknown = 0xFFu, + +} en_mfs_instance_index_t; + +/// MFS mode +typedef enum en_mfs_mode +{ + MfsInitMode = 0u, ///< MFS initial mode + MfsUartMode = 1u, ///< MFS UART mode + MfsCsioMode = 2u, ///< MFS CSIO mode + MfsI2cMode = 3u, ///< MFS I2C mode + MfsLinMode = 4u, ///< MFS LIN mode + +}en_mfs_mode_t; + +/** \} GroupMFS_Types */ + +/** +* \addtogroup GroupMFS_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Mfs FIFO configuration. + ******************************************************************************/ +typedef struct stc_mfs_fifo_config +{ + en_mfs_fifo_sel_t enFifoSel; ///< FIFO selection, see #en_mfs_fifo_sel_t for details + uint8_t u8ByteCount1; ///< Transfer data count for FIFO1 + uint8_t u8ByteCount2; ///< Transfer data count for FIFO2 +} stc_mfs_fifo_config_t; + +/******************************************************************************* +* UART Data Structures +*******************************************************************************/ + +/** + ****************************************************************************** + ** \brief UART interrupt enable structure + ******************************************************************************/ +typedef struct stc_uart_irq_en +{ + boolean_t bTxIrq; ///< UART TX interrupt + boolean_t bRxIrq; ///< UART RX interrupt + boolean_t bTxIdleIrq; ///< UART TX idle interrupt + boolean_t bTxFifoIrq; ///< UART TX FIFO interrupt + +}stc_uart_irq_en_t; + +/** + ****************************************************************************** + ** \brief UART interrupt callback function + ******************************************************************************/ +typedef struct stc_uart_irq_cb +{ + func_ptr_t pfnTxIrqCb; ///< UART TX interrupt callback function pointer + func_ptr_t pfnRxIrqCb; ///< UART RX interrupt callback function pointer + func_ptr_t pfnTxIdleCb; ///< UART TX idle interrupt callback function pointer + func_ptr_t pfnTxFifoIrqCb; ///< UART TX FIFO interrupt callback function pointer + +}stc_uart_irq_cb_t; + +/** + ****************************************************************************** + ** \brief UART configuration structure + ******************************************************************************/ +typedef struct stc_mfs_uart_config +{ + en_uart_mode_t enMode; ///< UART mode + uint32_t u32BaudRate; ///< Baud rate (bps) + en_uart_parity_t enParity; ///< Parity format + en_uart_stop_bit_t enStopBit; ///< Stop bit + en_uart_data_len_t enDataLength; ///< 5..9 Bit Character Length + en_uart_data_dir_t enBitDirection; ///< UART data direction + boolean_t bInvertData; ///< FALSE: NRZ, TRUE : Inverted NRZ + boolean_t bHwFlow; ///< FALSE: Not use Hardware Flow, TRUE : Use Hardware Flow + boolean_t bUseExtClk; ///< FALSE: use internal clock, TRUE: use external clock which input via SCK pin + + stc_mfs_fifo_config_t* pstcFifoConfig; ///< Pointer to FIFO configuration structure, if set to NULL, FIFO function will not be enabled. +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + stc_uart_irq_en_t *pstcIrqEn; ///< Pointer to UART interrupt enable structure, if set to NULL, no interrupt enabled. + stc_uart_irq_cb_t *pstcIrqCb; ///< Pointer to UART interrupt callback functions structurei, f set to NULL, no interrupt callback initialized. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +} stc_mfs_uart_config_t; + +/******************************************************************************* +* CSIO Data Structures +*******************************************************************************/ + +/** + ****************************************************************************** + ** \brief CSIO serial timer configuration + ******************************************************************************/ +typedef struct stc_csio_serial_timer +{ + en_csio_timer_clk_t enClkDiv; ///< Clock division + uint8_t u8TransferByteCnt; ///< Transfer byte count + uint16_t u16CompareVal; ///< The compare value depending on which the transfer starts + +}stc_csio_serial_timer_t; + +/** + ****************************************************************************** + ** \brief CSIO chip selection configuration + ******************************************************************************/ +typedef struct stc_csio_cs +{ + en_cs_pin_sel_t enCsStartPin; ///< Chip selecetion pin selection + en_cs_pin_sel_t enCsEndPin; ///< Chip selecetion pin selection + en_cs_pin_level_t enLevel; ///< Active level selection, only available for SCS0 + boolean_t bActiveHold; ///< FALSE: don't hold active status, TRUE: hold active status until all bytes are transfered. + en_cs_timing_clk_t enClkDiv; ///< Chip selecetion clock division + uint8_t u8CsSetupDelayTime; ///< Chip selecetion delay time + uint8_t u8CsHoldDelayTime; ///< Chip selecetion hold time + uint16_t u16CsDeselectTime; ///< Chip selecetion deselection time (gap between two bytes's transfer) + uint8_t u8Scs0TransferByteCnt; ///< SCS0 Transfer byte count + uint8_t u8Scs1TransferByteCnt; ///< SCS1 Transfer byte count + uint8_t u8Scs2TransferByteCnt; ///< SCS2 Transfer byte count + uint8_t u8Scs3TransferByteCnt; ///< SCS3 Transfer byte count + boolean_t bScs0En; ///< TRUE: SCS0 Enable + boolean_t bScs1En; ///< TRUE: SCS1 Enable + boolean_t bScs2En; ///< TRUE: SCS2 Enable + boolean_t bScs3En; ///< TRUE: SCS3 Enable + +}stc_csio_cs_t; + +/** + ****************************************************************************** + ** \brief CSIO interrupt enable structure + ******************************************************************************/ +typedef struct stc_csio_irq_en +{ + boolean_t bTxIrq; ///< CSIO TX interrupt + boolean_t bRxIrq; ///< CSIO RX interrupt + boolean_t bTxIdleIrq; ///< CSIO TX idle interrupt + boolean_t bTxFifoIrq; ///< CSIO TX FIFO interrupt +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bCsErrIrq; ///< CSIO chip selection interrupt + boolean_t bSerialTimerIrq; ///< CSIO serial timer interrupt +#endif +}stc_csio_irq_en_t; + +/** + ****************************************************************************** + ** \brief CSIO interrupt callback function + ******************************************************************************/ +typedef struct stc_csio_irq_cb +{ + func_ptr_t pfnTxIrqCb; ///< CSIO TX interrupt callback function + func_ptr_t pfnRxIrqCb; ///< CSIO RX interrupt callback function + func_ptr_t pfnTxIdleCb; ///< CSIO TX idle interrupt callback function + func_ptr_t pfnTxFifoIrqCb; ///< CSIO TX FIFO interrupt callback function +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + func_ptr_t pfnCsErrIrqCb; ///< CSIO chip selection interrupt callback function + func_ptr_t pfnSerialTimerIrqCb; ///< CSIO serial timer interrupt callback function +#endif + +}stc_csio_irq_cb_t; + +/** + ****************************************************************************** + ** \brief CSIO configuration structure + ******************************************************************************/ +typedef struct stc_mfs_csio_config +{ + en_csio_ms_mode_t enMsMode; ///< Master or slave mode + uint32_t u32BaudRate; ///< Baud rate (bps) + en_csio_act_mode_t enActMode; ///< CSIO or SPI mode + en_csio_sync_wait_time_t enSyncWaitTime; ///< Sync wait time + en_csio_data_len_t enDataLength; ///< 5..16 Bit Character Length, see description of #en_csio_data_len_t + en_csio_data_dir_t enBitDirection; ///< Bit direction + boolean_t bInvertClk ; ///< FALSE: SCK Mark Level High, TRUE: SCK Mark Level Low +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + stc_csio_serial_timer_t* pstcSerialTimer; ///< Pointer to serial timer configuration structure, if set to NULL, nothing will be done. + stc_csio_cs_t* pstcCsConfig; ///< Pointer to chip selection configuration structure, if set to NULL, nothing will be done. +#endif + stc_mfs_fifo_config_t* pstcFifoConfig; ///< Pointer to FIFO configuration structure, if set to NULL, nothing will be done. +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + stc_csio_irq_en_t *pstcIrqEn; ///< Pointer to CSIO interrupt enable structure, if set to NULL, no interrupt enabled. + stc_csio_irq_cb_t *pstcIrqCb; ///< Pointer to CSIO interrupt callback functions structurei, f set to NULL, no interrupt callback initialized. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +} stc_mfs_csio_config_t; + +/******************************************************************************* +* I2C Data Structures +*******************************************************************************/ + +/** + ****************************************************************************** + ** \brief I2C interrupt enable structure + ******************************************************************************/ +typedef struct stc_i2c_irq_en +{ + boolean_t bTxIrq; ///< I2C TX interrupt + boolean_t bRxIrq; ///< I2C RX interrupt + boolean_t bTxIdleIrq; ///< I2C TX idle interrupt + boolean_t bTxFifoIrq; ///< I2C TX FIFO interrupt + boolean_t bTxRxIrq; ///< I2C TX and RX interrupt + boolean_t bStopDetectIrq; ///< I2C stop condition interrupt + +}stc_i2c_irq_en_t; + +/** + ****************************************************************************** + ** \brief I2C interrupt callback function + ******************************************************************************/ +typedef struct stc_i2c_irq_cb +{ + func_ptr_t pfnTxIrqCb; ///< I2C TX interrupt callback function pointer + func_ptr_t pfnRxIrqCb; ///< I2C RX interrupt callback function pointer + func_ptr_t pfnTxIdleCb; ///< I2C TX idle interrupt callback function pointer + func_ptr_t pfnTxFifoIrqCb; ///< I2C TX FIFO interrupt callback function pointer + func_ptr_t pfnTxRxIrqCb; ///< I2C TX and RX completion interrupt callback function + func_ptr_t pfnStopDetectIrqCb; ///< I2C stop condition interrupt + +}stc_i2c_irq_cb_t; + +/** + ****************************************************************************** + ** \brief I2C configuration structure + ******************************************************************************/ +typedef struct stc_mfs_i2c_config +{ + en_i2c_mode_t enMsMode; ///< I2C master mode or slave mode + uint32_t u32BaudRate; ///< Baud rate (bps) + uint8_t u8SlaveAddr; ///< Slave address (This is effective on slave mode.) + uint8_t u8SlaveMaskAddr; ///< Slave Mask address (This is effective on slave mode.) + boolean_t bWaitSelection; ///< FALSE: generate interrupt after ACK, TRUE: generate interrupt before ACK + boolean_t bDmaEnable; ///< FALSE: don't use DMA function, TRUE: use DMA function + + stc_mfs_fifo_config_t* pstcFifoConfig; ///< Pointer to FIFO configuration structure, if set to NULL, FIFO function will not be enabled. +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + stc_i2c_irq_en_t* pstcIrqEn; ///< Pointer to I2C interrupt enable structure, if set to NULL, no interrupt enabled. + stc_i2c_irq_cb_t* pstcIrqCb; ///< Pointer to I2C interrupt callback functions structurei, if set to NULL, no interrupt callback initialized. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +} stc_mfs_i2c_config_t; + +/******************************************************************************* +* LIN Data Structures +*******************************************************************************/ + +/** + ****************************************************************************** + ** \brief LIN interrupt selection + ******************************************************************************/ +typedef struct stc_lin_irq_en +{ + boolean_t bTxIrq; ///< LIN TX interrupt + boolean_t bRxIrq; ///< LIN RX interrupt + boolean_t bLinBreakIrq; ///< LIN break field interrupt + boolean_t bTxIdleIrq; ///< LIN TX idle interrupt + boolean_t bTxFifoIrq; ///< LIN TX FIFO interrupt + +}stc_lin_irq_en_t; + +/** + ****************************************************************************** + ** \brief LIN interrupt callback function + ******************************************************************************/ +typedef struct stc_lin_irq_cb +{ + func_ptr_t pfnTxIrqCb; ///< LIN TX interrupt callback function + func_ptr_t pfnRxIrqCb; ///< LIN RX interrupt callback function + func_ptr_t pfnLinBreakIrqCb; ///< LIN break field interrupt callback function + func_ptr_t pfnTxIdleIrqCb; ///< LIN TX idle interrupt callback function + func_ptr_t pfnTxFifoIrqCb; ///< LIN TX FIFO interrupt callback function + +}stc_lin_irq_cb_t; + +/** + ****************************************************************************** + ** \brief LIN configuration structure + ******************************************************************************/ +typedef struct stc_mfs_lin_config +{ + en_lin_ms_mode_t enMsMode; ///< LIN master or slave mode + uint32_t u32BaudRate; ///< Baud rate (bps) + en_lin_stop_bit_t enStopBits; ///< Stop bits length + en_lin_break_len_t enBreakLength; ///< Break length + en_lin_delimiter_len_t enDelimiterLength; ///< Delimiter length + boolean_t bUseExtClk; ///< FALSE: use internal clock, TRUE: use external clock which input via SCK pin + + stc_mfs_fifo_config_t* pstcFifoConfig; ///< Pointer to FIFO configuration structure, if set to NULL, FIFO function will not be enabled. +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) + stc_lin_irq_en_t* pstcIrqEn; ///< Pointer to LIN interrupt enable structure, if set to NULL, no interrupt enabled. + stc_lin_irq_cb_t* pstcIrqCb; ///< Pointer to LIN interrupt callback functions structurei, if set to NULL, no interrupt callback initialized. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +} stc_mfs_lin_config_t; + +/// MFS common instance structure +typedef struct stc_mfsn +{ + #if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) + volatile stc_mfsn_uart_t* pstcUartInstance; ///< Pointer to UART instance + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) + volatile stc_mfsn_csio_t* pstcCsioInstance; ///< Pointer to CSIO instance + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) + volatile stc_mfsn_i2c_t* pstcI2cInstance; ///< Pointer to I2C instance + #endif + #if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) + volatile stc_mfsn_lin_t* pstcLinInstance; ///< Pointer to LIN instance + #endif +}stc_mfsn_t; + +/// MFS module internal data, storing internal information for each enabled MFS instance. +typedef struct stc_mfs_intern_data +{ + en_mfs_mode_t enMode; ///< MFS mode + union + { + func_ptr_t fnMfsInternIntCb[6]; + stc_uart_irq_cb_t stcUartInternIrqCb; ///< Uart internal interrupt callback function + stc_csio_irq_cb_t stcCsioInternIrqCb; ///< CSIO internal interrupt callback function + stc_i2c_irq_cb_t stcI2cInternIrqCb; ///< I2C internal interrupt callback function + stc_lin_irq_cb_t stcLinInternIrqCb; ///< LIN internal interrupt callback function + }; + +} stc_mfs_intern_data_t; + +/// MFS instance data type +typedef struct stc_mfs_instance_data +{ + stc_mfsn_t stcInstance; ///< pointer to registers of an instance + stc_mfs_intern_data_t stcInternData; ///< module internal data of instance +} stc_mfs_instance_data_t; + +/** \} GroupMFS_DataStructures */ + +/** +* \addtogroup GroupMFS_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled MFS instances and their internal data +extern stc_mfs_instance_data_t m_astcMfsInstanceDataLut[MFS_INSTANCE_COUNT]; + +/** \} GroupMFS_GlobalVariables */ + +/** +* \addtogroup GroupMFS_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (PDL_PERIPHERAL_ENABLE_MFS_UART_MODE == PDL_ON) +/* UART */ +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +// Interrupt +void MfsUartIrqHandlerTx(volatile stc_mfsn_uart_t* pstcUart, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsUartIrqHandlerRx(volatile stc_mfsn_uart_t* pstcUart, + stc_mfs_intern_data_t* pstcMfsInternData); +en_result_t Mfs_Uart_EnableIrq(volatile stc_mfsn_uart_t* pstcUart, + en_uart_irq_sel_t enIrqSel); +en_result_t Mfs_Uart_DisableIrq(volatile stc_mfsn_uart_t* pstcUart, + en_uart_irq_sel_t enIntSel); +#endif +// Init/De-Init +en_result_t Mfs_Uart_Init(volatile stc_mfsn_uart_t* pstcUart, + const stc_mfs_uart_config_t* pstcConfig); +en_result_t Mfs_Uart_DeInit(volatile stc_mfsn_uart_t* pstcUart, boolean_t bTouchNvic); +// Baud rate +en_result_t Mfs_Uart_SetBaudRate(volatile stc_mfsn_uart_t* pstcUart, + uint32_t u32BaudRate); +// Function enable/disable +en_result_t Mfs_Uart_EnableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc); +en_result_t Mfs_Uart_DisableFunc(volatile stc_mfsn_uart_t* pstcUart, en_uart_func_t enFunc); +// Status read/clear +boolean_t Mfs_Uart_GetStatus(volatile stc_mfsn_uart_t* pstcUart, + en_uart_status_t enStatus); +en_result_t Mfs_Uart_ClrStatus(volatile stc_mfsn_uart_t* pstcUart, + en_uart_status_t enStatus); +// Data read/write +en_result_t Mfs_Uart_SendData(volatile stc_mfsn_uart_t* pstcUart, uint16_t Data); +uint16_t Mfs_Uart_ReceiveData(volatile stc_mfsn_uart_t* pstcUart); +// FIFO +en_result_t Mfs_Uart_ResetFifo (volatile stc_mfsn_uart_t* pstcUart, + en_mfs_fifo_t enFifo); +en_result_t Mfs_Uart_SetFifoCount(volatile stc_mfsn_uart_t* pstcUart, + en_mfs_fifo_t enFifo, + uint8_t u8Count); +uint8_t Mfs_Uart_GetFifoCount(volatile stc_mfsn_uart_t* pstcUart, + en_mfs_fifo_t enFifo); +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE == PDL_ON) +/* CSIO */ +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +// Interrupt +void MfsCsioIrqHandlerTx(volatile stc_mfsn_csio_t* pstcCsio, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsCsioIrqHandlerRx(volatile stc_mfsn_csio_t* pstcCsio, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsCsioIrqHandlerStatus(volatile stc_mfsn_csio_t* pstcCsio, + stc_mfs_intern_data_t* pstcMfsInternData); +en_result_t Mfs_Csio_EnableIrq(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_irq_sel_t enIrqSel); +en_result_t Mfs_Csio_DisableIrq(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_irq_sel_t enIrqSel); +#endif +// Init/De-Init +en_result_t Mfs_Csio_Init(volatile stc_mfsn_csio_t* pstcCsio, + const stc_mfs_csio_config_t* pstcConfig); +en_result_t Mfs_Csio_DeInit(volatile stc_mfsn_csio_t* pstcCsio, boolean_t bTouchNvic); +// Re-configuration +en_result_t Mfs_Csio_SetBaudRate(volatile stc_mfsn_csio_t* pstcCsio, + uint32_t u32BaudRate); +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +en_result_t Mfs_Csio_SetTimerCompareValue(volatile stc_mfsn_csio_t* pstcCsio, + uint16_t u16CompareValue); +en_result_t Mfs_Csio_SetCsTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, + en_cs_pin_sel_t enCsPin, + uint8_t u8ByteCnt); +en_result_t Mfs_Csio_SetCsHoldStatus(volatile stc_mfsn_csio_t* pstcCsio, + boolean_t bHold); +en_result_t Mfs_Csio_SetTimerTransferByteCount(volatile stc_mfsn_csio_t* pstcCsio, + uint8_t u8ByteCnt); +#endif +// Function enable/disable +en_result_t Mfs_Csio_EnableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc); +en_result_t Mfs_Csio_DisableFunc(volatile stc_mfsn_csio_t* pstcCsio, en_csio_func_t enFunc); + +// Status read/clear +boolean_t Mfs_Csio_GetStatus(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_status_t enStatus); +en_result_t Mfs_Csio_ClrStatus(volatile stc_mfsn_csio_t* pstcCsio, + en_csio_status_t enStatus); +// Data read/write +en_result_t Mfs_Csio_SendData(volatile stc_mfsn_csio_t* pstcCsio, + uint16_t u16Data, + boolean_t bSotEn); +uint16_t Mfs_Csio_ReceiveData(volatile stc_mfsn_csio_t* pstcCsio); +// FIFO +en_result_t Mfs_Csio_ResetFifo (volatile stc_mfsn_csio_t* pstcCsio, + en_mfs_fifo_t enFifo); +en_result_t Mfs_Csio_SetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, + en_mfs_fifo_t enFifo, + uint8_t u8Count); +uint8_t Mfs_Csio_GetFifoCount(volatile stc_mfsn_csio_t* pstcCsio, + en_mfs_fifo_t enFifo); +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE == PDL_ON) +/* I2C */ +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +// Interrupt +void MfsI2cIrqHandlerTx(volatile stc_mfsn_i2c_t* pstcI2c, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsI2cIrqHandlerRx(volatile stc_mfsn_i2c_t* pstcI2c, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsI2cIrqHandlerStatus(volatile stc_mfsn_i2c_t* pstcI2c, + stc_mfs_intern_data_t* pstcMfsInternData); +en_result_t Mfs_I2c_EnableIrq(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_irq_sel_t enIrqSel); +en_result_t Mfs_I2c_DisableIrq(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_irq_sel_t enIrqSel); +#endif +// Init/De-Init +en_result_t Mfs_I2c_Init(volatile stc_mfsn_i2c_t* pstcI2c, + const stc_mfs_i2c_config_t* pstcConfig); +en_result_t Mfs_I2c_DeInit(volatile stc_mfsn_i2c_t* pstcI2c, boolean_t bTouchNvic); + +// Start/Stop +en_result_t Mfs_I2c_GenerateStart(volatile stc_mfsn_i2c_t* pstcI2c); +en_result_t Mfs_I2c_GenerateRestart(volatile stc_mfsn_i2c_t* pstcI2c); +en_result_t Mfs_I2c_GenerateStop(volatile stc_mfsn_i2c_t* pstcI2c); + +// Re-configure baud rate +en_result_t Mfs_I2c_SetBaudRate(volatile stc_mfsn_i2c_t* pstcI2c, + uint32_t u32BaudRate); +// Data read/write +en_result_t Mfs_I2c_SendData(volatile stc_mfsn_i2c_t* pstcI2c, uint8_t u8Data); +uint8_t Mfs_I2c_ReceiveData(volatile stc_mfsn_i2c_t* pstcI2c); + +// ACK +en_result_t Mfs_I2c_ConfigAck(volatile stc_mfsn_i2c_t* pstcI2c, en_i2c_ack_t enAck); +en_i2c_ack_t Mfs_I2c_GetAck(volatile stc_mfsn_i2c_t* pstcI2c); + +// Status read/clear +boolean_t Mfs_I2c_GetStatus(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_status_t enStatus); +en_result_t Mfs_I2c_ClrStatus(volatile stc_mfsn_i2c_t* pstcI2c, + en_i2c_status_t enStatus); + +// Get Data direction in slave mode +en_i2c_data_dir_t Mfs_I2c_GetDataDir(volatile stc_mfsn_i2c_t* pstcI2c); + +// FIFO +en_result_t Mfs_I2c_ResetFifo (volatile stc_mfsn_i2c_t* pstcI2c, + en_mfs_fifo_t enFifo); +en_result_t Mfs_I2c_SetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, + en_mfs_fifo_t enFifo, + uint8_t u8Count); +uint8_t Mfs_I2c_GetFifoCount(volatile stc_mfsn_i2c_t* pstcI2c, + en_mfs_fifo_t enFifo); +#endif + +#if (PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE == PDL_ON) +/* LIN */ +#if (PDL_INTERRUPT_ENABLE_MFS0 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS8 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS1 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS9 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS2 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS10 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS3 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS11 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS4 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS12 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS5 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS13 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS6 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS14 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFS7 == PDL_ON) || (PDL_INTERRUPT_ENABLE_MFS15 == PDL_ON) +// Interrupt +void MfsLinIrqHandlerTx(volatile stc_mfsn_lin_t* pstcLin, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsLinIrqHandlerRx(volatile stc_mfsn_lin_t* pstcLin, + stc_mfs_intern_data_t* pstcMfsInternData); +void MfsLinIrqHandlerStatus(volatile stc_mfsn_lin_t* pstcLin, + stc_mfs_intern_data_t* pstcMfsInternData); +en_result_t Mfs_Lin_EnableIrq(volatile stc_mfsn_lin_t* pstcLin, + en_lin_irq_sel_t enIrqSel); +en_result_t Mfs_Lin_DisableIrq(volatile stc_mfsn_lin_t* pstcLin, + en_lin_irq_sel_t enIrqSel); +#endif +// Init/De-Init +en_result_t Mfs_Lin_Init(volatile stc_mfsn_lin_t* pstcLin, + const stc_mfs_lin_config_t* pstcConfig); +en_result_t Mfs_Lin_DeInit(volatile stc_mfsn_lin_t* pstcLin, boolean_t bTouchNvic); +// Baud rate +en_result_t Mfs_Lin_SetBaudRate(volatile stc_mfsn_lin_t* pstcLin, + uint32_t u32BaudRate); +// Generate break field +en_result_t Mfs_Lin_GenerateBreakField(volatile stc_mfsn_lin_t* pstcLin); + +// Function enable/disable +en_result_t Mfs_Lin_EnableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc); +en_result_t Mfs_Lin_DisableFunc(volatile stc_mfsn_lin_t* pstcLin, en_lin_func_t enFunc); +// Status read/clear +boolean_t Mfs_Lin_GetStatus(volatile stc_mfsn_lin_t* pstcLin, + en_lin_status_t enStatus); +en_result_t Mfs_Lin_ClrStatus(volatile stc_mfsn_lin_t* pstcLin, + en_lin_status_t enStatus); +// Data read/write +en_result_t Mfs_Lin_SendData(volatile stc_mfsn_lin_t* pstcLin, uint8_t Data); +uint8_t Mfs_Lin_ReceiveData(volatile stc_mfsn_lin_t* pstcLin); +// FIFO +en_result_t Mfs_Lin_ResetFifo (volatile stc_mfsn_lin_t* pstcLin, + en_mfs_fifo_t enFifo); +en_result_t Mfs_Lin_SetFifoCount(volatile stc_mfsn_lin_t* pstcLin, + en_mfs_fifo_t enFifo, + uint8_t u8Count); +uint8_t Mfs_Lin_GetFifoCount(volatile stc_mfsn_lin_t* pstcLin, + en_mfs_fifo_t enFifo); +#endif + +/** \} GroupMFS_Functions */ +/** \} GroupMFS */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ + +#endif /* __MFS_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_adcmp.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_adcmp.c new file mode 100644 index 0000000000..224b19b2ec --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_adcmp.c @@ -0,0 +1,1061 @@ +/******************************************************************************* +* \file mft_adcmp.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the +* MFT_ADCMP driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mft/mft_adcmp.h" + +#if (defined(PDL_PERIPHERAL_MFT_ADCMP_ACTIVE)) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Device dependent initialization of Mft adcmp module + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8Ch Mft adcmp channel + ** \arg MFT_ADCMP_CH0 ADCMP channel 0 + ** \arg MFT_ADCMP_CH1 ADCMP channel 1 + ** \arg MFT_ADCMP_CH2 ADCMP channel 2 + ** \arg MFT_ADCMP_CH3 ADCMP channel 3 + ** \arg MFT_ADCMP_CH4 ADCMP channel 4 + ** \arg MFT_ADCMP_CH5 ADCMP channel 5 + ** \param [in] pstcConfig Pointer to Mft adcmp config + ** \arg structure of Mft Adcmp configuration + ** + ** \retval Ok Adcmp initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - pstcConfig == NULL + ** - u8Ch > MFT_ADCMP_CH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_Init(volatile stc_mftn_adcmp_t* pstcMftAdcmp, + uint8_t u8Ch, + const stc_mft_adcmp_config_t* pstcConfig) +{ + volatile stc_mft_adcmp_acfs10_field_t* pstcACFS10 ; + volatile stc_mft_adcmp_acfs32_field_t* pstcACFS32 ; + volatile stc_mft_adcmp_acfs54_field_t* pstcACFS54 ; + + volatile stc_mft_adcmp_acsc0_field_t* pstcACSCx ; + volatile stc_mft_adcmp_acsd0_field_t* pstcACSDx ; +#if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + volatile stc_mft_adcmp_acmc0_field_t* pstcACMCx ; +#endif + if ((NULL == pstcMftAdcmp)||(NULL == pstcConfig)||(u8Ch > MFT_ADCMP_CH_MAX)) + { + return ErrorInvalidParameter ; + } + + // Get actual address of register list of current channel + pstcACFS10 = (volatile stc_mft_adcmp_acfs10_field_t*)(&pstcMftAdcmp->ACFS10); + pstcACFS32 = (volatile stc_mft_adcmp_acfs32_field_t*)(&pstcMftAdcmp->ACFS32); + pstcACFS54 = (volatile stc_mft_adcmp_acfs54_field_t*)(&pstcMftAdcmp->ACFS54); + + pstcACSCx = (volatile stc_mft_adcmp_acsc0_field_t*)(&pstcMftAdcmp->ACSC0 + 0x4*u8Ch); + pstcACSDx = (volatile stc_mft_adcmp_acsd0_field_t*)(&pstcMftAdcmp->ACSD0 + 0x4*u8Ch); +#if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + pstcACMCx = (volatile stc_mft_adcmp_acmc0_field_t*)(&pstcMftAdcmp->ACMC0 + 0x4*u8Ch); +#endif + // Configure parameter + pstcACSDx->DE = 0u; + pstcACSDx->PE = 0u; + pstcACSDx->UE = 0u; + pstcACSDx->ZE = 0u; + + pstcMftAdcmp->ACSA &= 0x0000u; + + // Select FRT channel : FRTx -> ADCMPx + switch(u8Ch) + { + case 0: + pstcACFS10->FSA0 = (uint8_t)pstcConfig->enFrt; + break; + case 1: + pstcACFS10->FSA1 = (uint8_t)pstcConfig->enFrt; + break; + case 2: + pstcACFS32->FSA2 = (uint8_t)pstcConfig->enFrt; + break; + case 3: + pstcACFS32->FSA3 = (uint8_t)pstcConfig->enFrt; + break; + case 4: + pstcACFS54->FSA4 = (uint8_t)pstcConfig->enFrt; + break; + case 5: + pstcACFS54->FSA5 = (uint8_t)pstcConfig->enFrt; + break; + default: + return ErrorInvalidParameter; + } + + switch (pstcConfig->enBuf) + { + case AdcmpBufDisable: + pstcACSCx->BUFE = 0u; + break; + case AdcmpBufFrtZero: + pstcACSCx->BUFE = 1u; + break; + case AdcmpBufFrtPeak: + pstcACSCx->BUFE = 2u; + break; + case AdcmpBufFrtZeroPeak: + pstcACSCx->BUFE = 3u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + case AdcmpBufFrtZeroMszcZero: + pstcACSCx->APBM = 1u; + pstcACSCx->BUFE = 1u; + break; + case AdcmpBufFrtPeakMspcZero: + pstcACSCx->APBM = 1u; + pstcACSCx->BUFE = 2u; + break; + case AdcmpBufFrtZeroMszcZeroOrFrtPeakMspcZero: + pstcACSCx->APBM = 1u; + pstcACSCx->BUFE = 3u; + break; + #endif + #endif + default: + return ErrorInvalidParameter; + } + + // configure start trigger output channel number + switch (pstcConfig->enTrigSel) + { + case AdcmpTrigAdc0Scan: + pstcACSCx->ADSEL = 0u; + break; + case AdcmpTrigAdc0Prio: + pstcACSCx->ADSEL = 1u; + break; + case AdcmpTrigAdc1Scan: + pstcACSCx->ADSEL = 2u; + break; + case AdcmpTrigAdc1Prio: + pstcACSCx->ADSEL = 3u; + break; + case AdcmpTrigAdc2Scan: + pstcACSCx->ADSEL = 4u; + break; + case AdcmpTrigAdc2Prio: + pstcACSCx->ADSEL = 5u; + break; + default: + return ErrorInvalidParameter; + } + + // Select ADCMP running mode + switch (pstcConfig->enMode) + { + case AdcmpNormalMode: + pstcACSDx->AMOD = 0u; + break; + case AdcmpOffsetMode: + pstcACSDx->AMOD = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // select OCU OCCP register: OCCP(x) + switch (pstcConfig->enOccpSel) + { + case AdcmpSelOccp0: + pstcACSDx->OCUS = 0u; + break; + case AdcmpSelOccp1: + pstcACSDx->OCUS = 1u; + break; + default: + return ErrorInvalidParameter; + } + +#if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + // Set the comparison with FRT interrupt mask counter + pstcACMCx->MZCE = ((pstcConfig->bCompareFrtZeroMaskCntVal == TRUE) ? 1u : 0u); + pstcACMCx->MPCE = ((pstcConfig->bCompareFrtPeakMaskCntVal == TRUE) ? 1u : 0u); + + if(pstcConfig->u8CompareVal > 15u) + { + return ErrorInvalidParameter; + } + + pstcACMCx->AMC = pstcConfig->u8CompareVal; +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Device dependent De-initialization of Mft adcmp module + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8Ch Mft adcmp channel + ** \arg MFT_ADCMP_CH0 ADCMP channel 0 + ** \arg MFT_ADCMP_CH1 ADCMP channel 1 + ** \arg MFT_ADCMP_CH2 ADCMP channel 2 + ** \arg MFT_ADCMP_CH3 ADCMP channel 3 + ** \arg MFT_ADCMP_CH4 ADCMP channel 4 + ** \arg MFT_ADCMP_CH5 ADCMP channel 5 + ** + ** \retval Ok Adcmp De-initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - u8Ch > MFT_ADCMP_CH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_DeInit(volatile stc_mftn_adcmp_t* pstcMftAdcmp, + uint8_t u8Ch) +{ + volatile stc_mft_adcmp_acfs10_field_t* pstcACFS10 ; + volatile stc_mft_adcmp_acfs32_field_t* pstcACFS32 ; + volatile stc_mft_adcmp_acfs54_field_t* pstcACFS54 ; + + volatile uint8_t* pu8ACSCx ; + volatile uint8_t* pu8ACSDx ; + + if ((NULL == pstcMftAdcmp) || (u8Ch > MFT_ADCMP_CH_MAX)) + { + return ErrorInvalidParameter ; + } + + // Get actual address of register list of current channel + pstcACFS10 = (volatile stc_mft_adcmp_acfs10_field_t*)(&pstcMftAdcmp->ACFS10); + pstcACFS32 = (volatile stc_mft_adcmp_acfs32_field_t*)(&pstcMftAdcmp->ACFS32); + pstcACFS54 = (volatile stc_mft_adcmp_acfs54_field_t*)(&pstcMftAdcmp->ACFS54); + + pu8ACSCx = (volatile uint8_t*)(&pstcMftAdcmp->ACSC0 + 0x4*u8Ch); + pu8ACSDx = (volatile uint8_t*)(&pstcMftAdcmp->ACSD0 + 0x4*u8Ch); + + // Select FRT channel : FRTx -> ADCMPx + switch(u8Ch) + { + case 0u: + pstcACFS10->FSA0 = 0u; + break; + case 1u: + pstcACFS10->FSA1 = 0u; + break; + case 2u: + pstcACFS32->FSA2 = 0u; + break; + case 3u: + pstcACFS32->FSA3 = 0u; + break; + case 4u: + pstcACFS54->FSA4 = 0u; + break; + case 5u: + pstcACFS54->FSA5 = 0u; + break; + default: + return ErrorInvalidParameter; + } + + *pu8ACSCx = 0u; + *pu8ACSDx = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable Mft Adcmp operations + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH0 ADCMP channel 0 + ** \arg MFT_ADCMP_CH1 ADCMP channel 1 + ** \arg MFT_ADCMP_CH2 ADCMP channel 2 + ** \arg MFT_ADCMP_CH3 ADCMP channel 3 + ** \arg MFT_ADCMP_CH4 ADCMP channel 4 + ** \arg MFT_ADCMP_CH5 ADCMP channel 5 + ** \param [in] pstcFunc Pointer to Mft Adcmp function structure + ** + ** \retval Ok Functions enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - pstcFunc == NULL + ** - u8Ch > MFT_ADCMP_CH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_EnableOperation(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8Ch, + stc_mft_adcmp_func_t* pstcFunc) +{ + volatile stc_mft_adcmp_acsd0_field_t* pstcACSDx ; + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(NULL == pstcFunc)||(u8Ch > MFT_ADCMP_CH_MAX)) + { + return ErrorInvalidParameter ; + } + // Get actual address of register list of current channel + pstcACSDx = (volatile stc_mft_adcmp_acsd0_field_t*)(&pstcMftAdcmp->ACSD0 + 0x4u*u8Ch); + + pstcACSDx->PE = pstcFunc->bPeakEn; + pstcACSDx->ZE = pstcFunc->bZeroEn; + pstcACSDx->UE = pstcFunc->bUpEn; + pstcACSDx->DE = pstcFunc->bDownEn; + + return Ok; +} +/** + ****************************************************************************** + ** \brief Disable Mft Adcmp operations + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH0 ADCMP channel 0 + ** \arg MFT_ADCMP_CH1 ADCMP channel 1 + ** \arg MFT_ADCMP_CH2 ADCMP channel 2 + ** \arg MFT_ADCMP_CH3 ADCMP channel 3 + ** \arg MFT_ADCMP_CH4 ADCMP channel 4 + ** \arg MFT_ADCMP_CH5 ADCMP channel 5 + ** \param [in] pstcFunc Pointer to Mft Adcmp function structure + ** \retval Ok Mft Adcmp operations disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - pstcFunc == NULL + ** - u8Ch > MFT_ADCMP_CH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_DisableOperation(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8Ch, + stc_mft_adcmp_func_t* pstcFunc) +{ + volatile stc_mft_adcmp_acsd0_field_t* pstcACSDx; + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(NULL == pstcFunc)||(u8Ch > MFT_ADCMP_CH_MAX)) + { + return ErrorInvalidParameter ; + } + // Get actual address of register list of current channel + pstcACSDx = (volatile stc_mft_adcmp_acsd0_field_t*)(&pstcMftAdcmp->ACSD0 + 0x4u*u8Ch); + + pstcACSDx->PE = pstcFunc->bPeakEn; + pstcACSDx->ZE = pstcFunc->bZeroEn; + pstcACSDx->UE = pstcFunc->bUpEn; + pstcACSDx->DE = pstcFunc->bDownEn; + + return Ok; +} +/** + ****************************************************************************** + ** \brief Write compare or offset value to ADCMP + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH0 ADCMP channel 0 + ** \arg MFT_ADCMP_CH1 ADCMP channel 1 + ** \arg MFT_ADCMP_CH2 ADCMP channel 2 + ** \arg MFT_ADCMP_CH3 ADCMP channel 3 + ** \arg MFT_ADCMP_CH4 ADCMP channel 4 + ** \arg MFT_ADCMP_CH5 ADCMP channel 5 + ** \param [in] u16AdcmpVal ADCMP compare value + ** + ** \retval Ok Compare or offset value to ADCMP is set + ** \retval ErrorInvalidParameter If one of following condiitons are met: + ** - pstcMftAdcmp == NULL + ** - u8Ch > MFT_ADCMP_CH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_WriteAcmp(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8Ch, + uint16_t u16AdcmpVal) +{ + volatile uint16_t* pu16AdcmpAcpmReg; + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8Ch > MFT_ADCMP_CH_MAX)) + { + return ErrorInvalidParameter ; + } + pu16AdcmpAcpmReg = (volatile uint16_t*)(&pstcMftAdcmp->ACMP0 + 0x2u*u8Ch); + *pu16AdcmpAcpmReg = u16AdcmpVal; + + return Ok; +} +/** + ****************************************************************************** + ** \brief Read compare and offset value of ACMP + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH0 ADCMP channel 0 + ** \arg MFT_ADCMP_CH1 ADCMP channel 1 + ** \arg MFT_ADCMP_CH2 ADCMP channel 2 + ** \arg MFT_ADCMP_CH3 ADCMP channel 3 + ** \arg MFT_ADCMP_CH4 ADCMP channel 4 + ** \arg MFT_ADCMP_CH5 ADCMP channel 5 + ** + ** \return Value of register ACMP + ** + ******************************************************************************/ +uint16_t Mft_Adcmp_ReadAcmp(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8Ch) +{ + volatile uint16_t* pu16AdcmpAcpmReg ; + uint16_t u16Data; + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8Ch > MFT_ADCMP_CH_MAX)) + { + return ErrorInvalidParameter ; + } + pu16AdcmpAcpmReg = (volatile uint16_t*)(&pstcMftAdcmp->ACMP0 + 0x2u*u8Ch); + u16Data = *pu16AdcmpAcpmReg; + + // return data value of ACMP register + return u16Data; +} +#endif +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible initialization + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8FM3Ch Mft Adcmp couple channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** \param [in] pstcConfig Mft Adcmp configuration parameter + ** + ** \retval Ok Mft Adcmp fm3 compatible mode initialized + ** \retval ErrorInvalidParameter Invalid setting of pstcConfig elements + ******************************************************************************/ +en_result_t Mft_Adcmp_Init_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch, + const stc_mft_adcmp_config_fm3_t *pstcConfig) +{ + volatile stc_mft_adcmp_acsa_field_t* pstcACSA ; +#if (PDL_MCU_CORE == PDL_FM3_CORE) + volatile uint8_t* pu8ACSB ; + volatile stc_mft_adcmp_atsa_field_t* pstcATSA ; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_mft_adcmp_acsc0_field_t* pstcACSC0 ; + volatile stc_mft_adcmp_acsc0_field_t* pstcACSC1 ; + volatile stc_mft_adcmp_acfs10_field_t* pstcACFS10 ; + volatile stc_mft_adcmp_acfs32_field_t* pstcACFS32 ; + volatile stc_mft_adcmp_acfs54_field_t* pstcACFS54 ; + +#endif + // Get actual address of register list of current channel + pstcACSA = (volatile stc_mft_adcmp_acsa_field_t*)(&pstcMftAdcmp->ACSA); +#if (PDL_MCU_CORE == PDL_FM3_CORE) + pu8ACSB = (volatile uint8_t*)(&pstcMftAdcmp->ACSB); + pstcATSA = (volatile stc_mft_adcmp_atsa_field_t*)(&pstcMftAdcmp->ATSA); +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSC0 = (volatile stc_mft_adcmp_acsc0_field_t*)(&pstcMftAdcmp->ACSC0 + 0x8u*u8FM3Ch); + pstcACSC1 = (volatile stc_mft_adcmp_acsc0_field_t*)(&pstcMftAdcmp->ACSC0 + 0x8u*u8FM3Ch + 0x04u); + pstcACFS10 = (volatile stc_mft_adcmp_acfs10_field_t*)(&pstcMftAdcmp->ACFS10); + pstcACFS32 = (volatile stc_mft_adcmp_acfs32_field_t*)(&pstcMftAdcmp->ACFS32); + pstcACFS54 = (volatile stc_mft_adcmp_acfs54_field_t*)(&pstcMftAdcmp->ACFS54); +#endif + + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACFS10->FSA0 = (uint8_t)pstcConfig->enFrt; + pstcACFS10->FSA1 = (uint8_t)pstcConfig->enFrt; + #else + pstcACSA->CE0 = (uint8_t)pstcConfig->enFrt + 1u; + #endif + break; + case MFT_ADCMP_CH32: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACFS32->FSA2 = (uint8_t)pstcConfig->enFrt; + pstcACFS32->FSA3 = (uint8_t)pstcConfig->enFrt; + #else + pstcACSA->CE1 = (uint8_t)pstcConfig->enFrt + 1u; + #endif + break; + case MFT_ADCMP_CH54: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACFS54->FSA4 = (uint8_t)pstcConfig->enFrt; + pstcACFS54->FSA5 = (uint8_t)pstcConfig->enFrt; + #else + pstcACSA->CE2 = (uint8_t)pstcConfig->enFrt + 1u; + #endif + break; + default: + return ErrorInvalidParameter; + } + + // configure buffer transfer type + switch (pstcConfig->enBuf) + { + case AdcmpBufDisable: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSC0->BUFE = 0u; + pstcACSC1->BUFE = 0u; + #else + *pu8ACSB |= (1u << u8FM3Ch); + #endif + break; + case AdcmpBufFrtZero: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSC0->BUFE = 1u; + pstcACSC1->BUFE = 1u; + #else + *pu8ACSB &= ~(1u << (4u + u8FM3Ch)); + *pu8ACSB &= ~(1u << u8FM3Ch); + #endif + break; + case AdcmpBufFrtPeak: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSC0->BUFE = 2u; + pstcACSC1->BUFE = 2u; + #else + *pu8ACSB |= (1u << (4u + u8FM3Ch)); + *pu8ACSB &= ~(1u << u8FM3Ch); + #endif + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case AdcmpBufFrtZeroPeak: + pstcACSC0->BUFE = 3u; + pstcACSC1->BUFE = 3u; + break; + #endif + default: + return ErrorInvalidParameter; + } + // configure start trigger output channel number +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + switch (pstcConfig->enTrigSel) + { + case AdcmpTrigAdc0Scan: + pstcACSC0->ADSEL = 0u; + pstcACSC1->ADSEL = 0u; + break; + case AdcmpTrigAdc0Prio: + pstcACSC0->ADSEL = 1u; + pstcACSC1->ADSEL = 1u; + break; + case AdcmpTrigAdc1Scan: + pstcACSC0->ADSEL = 2u; + pstcACSC1->ADSEL = 2u; + break; + case AdcmpTrigAdc1Prio: + pstcACSC0->ADSEL = 3u; + pstcACSC1->ADSEL = 3u; + break; + case AdcmpTrigAdc2Scan: + pstcACSC0->ADSEL = 4u; + pstcACSC1->ADSEL = 4u; + break; + case AdcmpTrigAdc2Prio: + pstcACSC0->ADSEL = 5u; + pstcACSC1->ADSEL = 5u; + break; + default: + return ErrorInvalidParameter; + } + + // configure Adcmp Fm3 mode + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + pstcACSA->SEL10 = (uint8_t)pstcConfig->enMode; + break; + case MFT_ADCMP_CH32: + pstcACSA->SEL32 = (uint8_t)pstcConfig->enMode; + break; + case MFT_ADCMP_CH54: + pstcACSA->SEL54 = (uint8_t)pstcConfig->enMode; + break; + default: + return ErrorInvalidParameter; + } +#else + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + pstcATSA->AD0S = ((pstcConfig->bAdcScanTriggerSel == TRUE) ? 1u : 0u); + pstcATSA->AD0P = ((pstcConfig->bAdcPrioTriggerSel == TRUE) ? 1u : 0u); + break; + case MFT_ADCMP_CH32: + pstcATSA->AD1S = ((pstcConfig->bAdcScanTriggerSel == TRUE) ? 1u : 0u); + pstcATSA->AD1P = ((pstcConfig->bAdcPrioTriggerSel == TRUE) ? 1u : 0u); + break; + case MFT_ADCMP_CH54: + pstcATSA->AD2S = ((pstcConfig->bAdcScanTriggerSel == TRUE) ? 1u : 0u); + pstcATSA->AD2P = ((pstcConfig->bAdcPrioTriggerSel == TRUE) ? 1u : 0u); + break; + default: + return ErrorInvalidParameter; + } + + // configure Adcmp Fm3 mode + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + pstcACSA->SEL0 = (uint8_t)pstcConfig->enMode; + break; + case MFT_ADCMP_CH32: + pstcACSA->SEL1 = (uint8_t)pstcConfig->enMode; + break; + case MFT_ADCMP_CH54: + pstcACSA->SEL2 = (uint8_t)pstcConfig->enMode; + break; + default: + return ErrorInvalidParameter; + } +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible de-initialization + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8FM3Ch Mft Adcmp couple channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** + ** \retval Ok Mft Adcmp fm3 compatible mode de-initialized + ** \retval ErrorInvalidParameter Invalid setting of u8FM3Ch + ******************************************************************************/ +en_result_t Mft_Adcmp_DeInit_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch) +{ + volatile stc_mft_adcmp_acsa_field_t* pstcACSA ; +#if (PDL_MCU_CORE == PDL_FM3_CORE) + volatile stc_mft_adcmp_acsb_field_t* pstcACSB ; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile uint8_t* pu8ACSC0 ; + volatile uint8_t* pu8ACSC1 ; + volatile uint8_t* pu8ACFS10 ; + volatile uint8_t* pu8ACFS32 ; + volatile uint8_t* pu8ACFS54 ; +#endif + + // Get actual address of register list of current channel + pstcACSA = (volatile stc_mft_adcmp_acsa_field_t*)(&pstcMftAdcmp->ACSA); +#if (PDL_MCU_CORE == PDL_FM3_CORE) + pstcACSB = (volatile stc_mft_adcmp_acsb_field_t*)(&pstcMftAdcmp->ACSB); +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pu8ACSC0 = (volatile uint8_t*)(&pstcMftAdcmp->ACSC0 + 0x8u*u8FM3Ch); + pu8ACSC1 = (volatile uint8_t*)(&pstcMftAdcmp->ACSC0 + 0x8u*u8FM3Ch + 4u); + pu8ACFS10 = (volatile uint8_t*)(&pstcMftAdcmp->ACFS10); + pu8ACFS32 = (volatile uint8_t*)(&pstcMftAdcmp->ACFS32); + pu8ACFS54 = (volatile uint8_t*)(&pstcMftAdcmp->ACFS54); +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + *pu8ACSC0 = 0u; + *pu8ACSC1 = 0u; +#endif + + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSA->CE10 = 0u; + pstcACSA->SEL10 = 0u; + *pu8ACFS10 = 0u; + #else + pstcACSA->CE0 = 0u; + pstcACSA->SEL0 = 0u; + pstcACSB->BDIS0 = 0u; + pstcACSB->BTS0 = 0u; + #endif + break; + case MFT_ADCMP_CH32: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSA->CE32 = 0u; + pstcACSA->SEL32 = 0u; + *pu8ACFS32 = 0u; + #else + pstcACSA->CE1 = 0u; + pstcACSA->SEL1 = 0u; + pstcACSB->BDIS1 = 0u; + pstcACSB->BTS1 = 0u; + #endif + break; + case MFT_ADCMP_CH54: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcACSA->CE54 = 0u; + pstcACSA->SEL54 = 0u; + *pu8ACFS54 = 0u; + #else + pstcACSA->CE2 = 0u; + pstcACSA->SEL2 = 0u; + pstcACSB->BDIS2 = 0u; + pstcACSB->BTS2 = 0u; + #endif + break; + default: + return ErrorInvalidParameter; + } + + return Ok; + +} + +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible mode configuration and enable operation + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8FM3Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** \retval Ok ADCMP FM3 mode funcitons enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - u8CoupleCh > MFT_ADCMP_CPCH_MAX + ******************************************************************************/ +en_result_t +Mft_Adcmp_EnableOperation_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_mft_adcmp_acsa_field_t* pstcACSA ; + // Get actual address of register list of current channel + pstcACSA = (volatile stc_mft_adcmp_acsa_field_t*)(&pstcMftAdcmp->ACSA); +#endif + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8FM3Ch > MFT_ADCMP_CPCH_MAX)) + { + return ErrorInvalidParameter ; + } + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + pstcACSA->CE10 = 1u; + break; + case MFT_ADCMP_CH32: + pstcACSA->CE32 = 1u; + break; + case MFT_ADCMP_CH54: + pstcACSA->CE54 = 1u; + break; + default: + return ErrorInvalidParameter; + } +#endif + return Ok; +} +/** + ****************************************************************************** + ** \brief De-configurate Mft Adcmp fm3 compatible function and disable operation + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8FM3Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** + ** \retval Ok ADCMP FM3 operation disabled + ** \retval ErrorInvalidParameter If one of followings conditions are met: + ** - pstcMftAdcmp == NULL + ** - u8CoupleCh > MFT_ADCMP_CPCH_MAX + ** + ******************************************************************************/ +en_result_t +Mft_Adcmp_DisableOperation_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_mft_adcmp_acsa_field_t* pstcACSA; + // Get actual address of register list of current channel + pstcACSA = (volatile stc_mft_adcmp_acsa_field_t*)(&pstcMftAdcmp->ACSA); +#endif + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8FM3Ch > MFT_ADCMP_CPCH_MAX)) + { + return ErrorInvalidParameter ; + } + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + switch(u8FM3Ch) + { + case MFT_ADCMP_CH10: + pstcACSA->CE10 = 0u; + break; + case MFT_ADCMP_CH32: + pstcACSA->CE32 = 0u; + break; + case MFT_ADCMP_CH54: + pstcACSA->CE54 = 0u; + break; + default: + return ErrorInvalidParameter; + } +#endif + + return Ok; +} +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible mode, write Accp register + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \param [in] u8FM3Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** \param [in] u16AccpVal Mft Adcmp configuration parameter + ** + ** \retval Ok Accp is written + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - u8CoupleCh > MFT_ADCMP_CPCH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_WriteAccp_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch, uint16_t u16AccpVal) +{ + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp) || (u8FM3Ch > MFT_ADCMP_CPCH_MAX)) + { + return ErrorInvalidParameter ; + } + + switch (u8FM3Ch) + { + case MFT_ADCMP_CH10: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMftAdcmp->ACMP0 = u16AccpVal; + #else + pstcMftAdcmp->ACCP0 = u16AccpVal; + #endif + break; + case MFT_ADCMP_CH32: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMftAdcmp->ACMP2 = u16AccpVal; + #else + pstcMftAdcmp->ACCP1 = u16AccpVal; + #endif + break; + case MFT_ADCMP_CH54: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMftAdcmp->ACMP4 = u16AccpVal; + #else + pstcMftAdcmp->ACCP2 = u16AccpVal; + #endif + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible mode, read Accp register stored value + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \arg structure of Mft_Adcmp + ** \param [in] u8FM3Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** \return Data stored in Accp register + ** + ******************************************************************************/ +uint16_t Mft_Adcmp_ReadAccp_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch) +{ + uint16_t u16Data; + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8FM3Ch > MFT_ADCMP_CPCH_MAX)) + { + return ErrorInvalidParameter ; + } + + switch (u8FM3Ch) + { + case MFT_ADCMP_CH10: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + u16Data = pstcMftAdcmp->ACMP0; + #else + u16Data = pstcMftAdcmp->ACCP0; + #endif + break; + case MFT_ADCMP_CH32: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + u16Data = pstcMftAdcmp->ACMP2; + #else + u16Data = pstcMftAdcmp->ACCP1; + #endif + break; + case MFT_ADCMP_CH54: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + u16Data = pstcMftAdcmp->ACMP4; + #else + u16Data = pstcMftAdcmp->ACCP2; + #endif + break; + default: + return ErrorInvalidParameter ; + } + + // return data value of ACMP register + return u16Data; +} +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible mode, write Accpdn register + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \arg structure of Mft_Adcmp + ** \param [in] u8FM3Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** \param [in] u16AccpdnVal data value of Accpdn + ** + ** \retval Ok Accpdn is written + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMftAdcmp == NULL + ** - u8CoupleCh > MFT_ADCMP_CPCH_MAX + ******************************************************************************/ +en_result_t Mft_Adcmp_WriteAccpdn_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch, + uint16_t u16AccpdnVal) +{ + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8FM3Ch > MFT_ADCMP_CPCH_MAX)) + { + return ErrorInvalidParameter ; + } + + switch (u8FM3Ch) + { + case MFT_ADCMP_CH10: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMftAdcmp->ACMP1 = u16AccpdnVal; + #else + pstcMftAdcmp->ACCPDN0 = u16AccpdnVal; + #endif + break; + case MFT_ADCMP_CH32: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMftAdcmp->ACMP3 = u16AccpdnVal; + #else + pstcMftAdcmp->ACCPDN1 = u16AccpdnVal; + #endif + break; + case MFT_ADCMP_CH54: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcMftAdcmp->ACMP5 = u16AccpdnVal; + #else + pstcMftAdcmp->ACCPDN2 = u16AccpdnVal; + #endif + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief Mft Adcmp fm3 compatible mode, read Accpdn register stored value + ** + ** \param [in] pstcMftAdcmp Pointer to Mft instance + ** \arg structure of Mft_Adcmp + ** \param [in] u8FM3Ch Mft Adcmp channel + ** \arg MFT_ADCMP_CH10 The couple channel of ch.0 and ch.1 + ** \arg MFT_ADCMP_CH32 The couple channel of ch.2 and ch.3 + ** \arg MFT_ADCMP_CH54 The couple channel of ch.4 and ch.5 + ** \return Data stored in Accpdn register + ** + ******************************************************************************/ +uint16_t Mft_Adcmp_ReadAccpdn_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch) +{ + uint16_t u16Data; + + // Check for NULL pointer and channel parameter + if ((NULL == pstcMftAdcmp)||(u8FM3Ch > MFT_ADCMP_CPCH_MAX)) + { + return ErrorInvalidParameter ; + } + + switch (u8FM3Ch) + { + case MFT_ADCMP_CH10: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + u16Data = pstcMftAdcmp->ACMP1; + #else + u16Data = pstcMftAdcmp->ACCPDN0; + #endif + break; + case MFT_ADCMP_CH32: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + u16Data = pstcMftAdcmp->ACMP3; + #else + u16Data = pstcMftAdcmp->ACCPDN1; + #endif + break; + case MFT_ADCMP_CH54: + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + u16Data = pstcMftAdcmp->ACMP5; + #else + u16Data = pstcMftAdcmp->ACCPDN2; + #endif + break; + default: + return ErrorInvalidParameter ; + } + + // return data value of ACMP register + return u16Data; +} + +#endif + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_adcmp.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_adcmp.h new file mode 100644 index 0000000000..bce4ee4a47 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_adcmp.h @@ -0,0 +1,375 @@ +/******************************************************************************* +* \file mft_adcmp.h +* +* \version 1.20 +* +* \brief Headerfile for MFT_ADCMP functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MFT_ADCMP_H__ +#define __MFT_ADCMP_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_MFT_ADCMP_ACTIVE)) + +/** +* \defgroup GroupMFT_ADCMP ADC Start Compare Unit (MFT ADCMP) +* \{ +* \defgroup GroupMFT_ADCMP_Macros Macros +* \defgroup GroupMFT_ADCMP_Functions Functions +* \defgroup GroupMFT_ADCMP_DataStructures Data Structures +* \defgroup GroupMFT_ADCMP_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupMFT_ADCMP +* \{ +* The ADC Start Compare Unit (ADCMP) is part of the Multi-function Timer (MFT). +* The MFT is a collection of peripherals used primarily for motor control. There may be +* up to three MFTs supported on a particular FM microcontroller. One MFT can control a +* 3-phase motor. A microcontroller that supports multiple MFTs can control multiple 3-phase motors.
+* The peripherals in the MFT are:
+* - Free-run Timer (FRT) +* - Output Compare Unit (OCU) +* - Waveform Generator (WFG) +* - Input Capture Unit (ICU) +* - ADC Start Compare (ADCMP)
+* There are six channels (0-5) available in the ADCMP. You configure each channel independently. +* The ADCMP triggers the ADC when the counter value of the selected FRT matches the compare value +* for the ADCMP channel. Using the ADCMP you can synchronize analog signal conversions to the motor +* control timer. This enables precise control over sensor-based input to the motor.
+* You can change the compare value at runtime. The ADCMP supports a buffered compare value. +* If you use the buffer, the compare value updates at a defined moment (for example, at a zero count +* or peak count). Otherwise it updates immediately.
+* The compare value can be used as an offset counter from a match in the OCU. In this mode a match +* occurs in the selected OCU channel based. The ADCMP compare value is used as an offset from that +* moment. When the offset count is reached, the ADCMP sends the trigger signal to the selected ADC.
+* Each channel can trigger any one of three ADCs, starting either a normal or a priority scan. Multiple +* ADCMP channels can trigger the same ADC, enabling multiple start times for the same ADC in a single +* FRT cycle. +* +* \section SectionMFT_ADCMP_ConfigurationConsideration Configuration Consideration +* Each channel can trigger any one of three ADCs, starting either a normal or a priority scan. Multiple ADCMP channels can +* trigger the same ADC, enabling multiple start times for the same ADC in a single FRT cycle.
+* To set up the ADCMP, you provide configuration parameters in the stc_mft_adcmp_config_t structure. +* For example, you specify the FRT to use, the compare buffer mode, which ADC to trigger +* (use constants defined in en_adcmp_trig_sel_t), normal or offset mode, the compare value, and so on. +* If you choose to use offset mode, also specify which OCU channel to use for the initial match that +* starts the offset counter. The constant AdcmpSelOccp0 selects OCU channel 0, 2, or 4 depending on +* which OCU you specify. The constant AdcmpSelOccp1 selects OCU channel 1, 3, or 5.
+* After setting up the configuration structure, call Mft_Adcmp_Init().
+* Then call Mft_Adcmp_EnableOperation() to start the ADCMP.
+* To change the compare value of any of the six ADCMP channels call Mft_Adcmp_WriteAcmp() with the new value. +* If you are using buffering, the value updates at the defined moment. +* \section SectionMFT_ADCMP_MoreInfo More Information +* For more information on the MFT ADCMP peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupMFT_ADCMP_Macros +* \{ +*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define MFT_ADCMP_CH0 0u +#define MFT_ADCMP_CH1 1u +#define MFT_ADCMP_CH2 2u +#define MFT_ADCMP_CH3 3u +#define MFT_ADCMP_CH4 4u +#define MFT_ADCMP_CH5 5u + +#define MFT_ADCMP_CH10 0u +#define MFT_ADCMP_CH32 1u +#define MFT_ADCMP_CH54 2u + +#define MFT_ADCMP_CH0_FM3 MFT_ADCMP_CH10 +#define MFT_ADCMP_CH1_FM3 MFT_ADCMP_CH32 +#define MFT_ADCMP_CH2_FM3 MFT_ADCMP_CH54 + +#define MFT_ADCMP_CH_MAX 5u +#define MFT_ADCMP_CPCH_MAX 2u +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define stc_mftn_adcmp_t FM_MFT_ADCMP_TypeDef + +#define MFT0_ADCMP (*(volatile stc_mftn_adcmp_t *) FM_MFT0_ADCMP_BASE) +#define MFT1_ADCMP (*(volatile stc_mftn_adcmp_t *) FM_MFT1_ADCMP_BASE) +#define MFT2_ADCMP (*(volatile stc_mftn_adcmp_t *) FM_MFT2_ADCMP_BASE) + +/** \} GroupMFT_ADCMP_Macros */ + +/** +* \addtogroup GroupMFT_ADCMP_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Define Frt channel connect to Adcmp + ******************************************************************************/ +typedef enum en_adcmp_frt +{ + Frt0ToAdcmp = 0u, ///< connect Frt channel 0 to Adcmp + Frt1ToAdcmp = 1u, ///< connect Frt channel 1 to Adcmp + Frt2ToAdcmp = 2u, ///< connect Frt channel 2 to Adcmp + +}en_adcmp_frt_t; + +/** + ****************************************************************************** + ** \brief Define Frt channel with FM3 mode connect to Adcmp + ******************************************************************************/ +typedef enum en_adcmp_fm3_frt +{ +#if (PDL_MCU_CORE == PDL_FM3_CORE) + Frt0ToAdcmpFm3 = 0u, ///< connect Frt channel 0 to Adcmp +#endif + Frt1ToAdcmpFm3 = 1u, ///< connect Frt channel 1 to Adcmp + Frt2ToAdcmpFm3 = 2u, ///< connect Frt channel 2 to Adcmp + +}en_adcmp_frt_fm3_t; + +/** + ****************************************************************************** + ** \brief Define Adcmp buffer type + ******************************************************************************/ +typedef enum en_adcmp_buf +{ + AdcmpBufDisable = 0u, ///< disable Adcmp buffer function + AdcmpBufFrtZero = 1u, ///< transfer buffer of ACMP and ACMC when counter value of Frt connected= 0x0000 + AdcmpBufFrtPeak = 2u, ///< transfer buffer of ACMP and ACMC when counter value of Frt connected= TCCP + AdcmpBufFrtZeroPeak = 3u, ///< transfer buffer of ACMP and ACMC both when counter value of Frt connected= 0x0000 and TCCP +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + AdcmpBufFrtZeroMszcZero = 4u, ///< transfer buffer of ACMP and ACMC when counter value of Frt connected= 0x0000 and zero value detection mask counter value is 0 + AdcmpBufFrtPeakMspcZero = 5u, ///< transfer buffer of ACMP and ACMC when counter value of Frt connected= peak and peak value detection mask counter value is 0 + AdcmpBufFrtZeroMszcZeroOrFrtPeakMspcZero = 6u, ///< transfer buffer of ACMP and ACMC when counter value of Frt connected= 0x0000 and zero value detection mask counter value is 0 + ///< or counter value of Frt connected= peak and peak value detection mask counter value is 0 + #endif +#endif +}en_adcmp_buf_t; + +/** + ****************************************************************************** + ** \brief Define Mft Adcmp output start trig channel + ******************************************************************************/ +typedef enum en_adcmp_trig_channel +{ + AdcmpStartTrig0 = 0u, ///< Outputs ADC start trigger 0 + AdcmpStartTrig1 = 1u, ///< Outputs ADC start trigger 1 + AdcmpStartTrig2 = 2u, ///< Outputs ADC start trigger 2 + AdcmpStartTrig3 = 3u, ///< Outputs ADC start trigger 3 + AdcmpStartTrig4 = 4u, ///< Outputs ADC start trigger 4 + AdcmpStartTrig5 = 5u, ///< Outputs ADC start trigger 5 + AdcmpStartTrig6 = 6u, ///< Outputs ADC start trigger 6 + AdcmpStartTrig7 = 7u, ///< Outputs ADC start trigger 7 + +}en_adcmp_start_trig_t; + +/** + ****************************************************************************** + ** \brief Define Mft Adcmp trig mode + ******************************************************************************/ +typedef enum en_adcmp_trig_sel +{ + AdcmpTrigAdc0Scan = 0u, ///< AdcmpStartTrig0 + AdcmpTrigAdc0Prio = 1u, ///< AdcmpStartTrig1 + AdcmpTrigAdc1Scan = 2u, ///< AdcmpStartTrig2 + AdcmpTrigAdc1Prio = 3u, ///< AdcmpStartTrig3 + AdcmpTrigAdc2Scan = 4u, ///< AdcmpStartTrig4 + AdcmpTrigAdc2Prio = 5u, ///< AdcmpStartTrig5 + +}en_adcmp_trig_sel_t; + +/** + ****************************************************************************** + ** \brief Define Adcmp running mode + ******************************************************************************/ +typedef enum en_adcmp_mode +{ + AdcmpNormalMode = 0u, ///< select Adcmp Normal mode + AdcmpOffsetMode = 1u, ///< select Adcmp Offset mode + +}en_adcmp_mode_t; + +/** + ****************************************************************************** + ** \brief Define Occp channel + ******************************************************************************/ +typedef enum en_adcmp_occp_sel +{ + AdcmpSelOccp0 = 0u, ///< select Occp0 channel + AdcmpSelOccp1 = 1u, ///< select Occp1 channel + +}en_adcmp_occp_sel_t; + +/** + ****************************************************************************** + ** \brief Define Mft_adcmp compatible fm3 mode + ******************************************************************************/ +typedef enum en_adcmp_mode_fm3 +{ + AdcmpAccpUpAccpDownFm3 = 0u, ///< Fm3 compatible mode: Accp Up and Down + AdcmpAccpUpFm3 = 1u, ///< Fm3 compatible mode: Accp Up + AdcmpAccpDownFm3 = 2u, ///< Fm3 compatible mode: Accp Down + AdcmpAccpUpAccpdnDownFm3 = 3u, ///< Fm3 compatible mode: Accp up adn Accpdn Down + +}en_adcmp_mode_fm3_t; + +/** \} GroupMFT_ADCMP_Types */ + +/** +* \addtogroup GroupMFT_ADCMP_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Define Mft_adcmp configure parameters + ******************************************************************************/ +typedef struct stc_mft_adcmp_config +{ + en_adcmp_frt_t enFrt; ///< configure Adcmp Frt channel + en_adcmp_buf_t enBuf; ///< configure Adcmp Buffer transfer type + en_adcmp_trig_sel_t enTrigSel; ///< configure Adcmp Trigger type + en_adcmp_mode_t enMode; ///< configure Adcmp Running mode + en_adcmp_occp_sel_t enOccpSel; ///< select Adcmp Occp channel +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + boolean_t bCompareFrtZeroMaskCntVal; ///< TRUE: Comparison is performed with the FRT zero interrupt mask counter. + ///< FALSE: Comparison is not performed with the FRT zero interrupt mask counter. + boolean_t bCompareFrtPeakMaskCntVal; ///< TRUE: Comparison is performed with the FRT peak interrupt mask counter. + ///< FALSE: Comparison is not performed with the FRT peak interrupt mask counter. + uint8_t u8CompareVal; ///< Specifies the AD conversion start time by the value to be compared with the FRT interrupt mask counter. + #endif +#endif +}stc_mft_adcmp_config_t; + +/** + ****************************************************************************** + ** \brief Define Mft_adcmp functions + ******************************************************************************/ +typedef struct stc_mft_adcmp_func +{ + boolean_t bDownEn; ///< Enable Adcmp Down function + boolean_t bPeakEn; ///< Enable Adcmp Peak function + boolean_t bUpEn; ///< Enable Adcmp Up function + boolean_t bZeroEn; ///< Enable Adcmp Zero function + +}stc_mft_adcmp_func_t; + +/** + ****************************************************************************** + ** \brief Define Mft_adcmp compatible fm3 configure parameters + ******************************************************************************/ +typedef struct stc_mft_adcmp_config_fm3 +{ + en_adcmp_frt_fm3_t enFrt; ///< configure Adcmp Frt channel + en_adcmp_mode_fm3_t enMode; ///< configure compatible Fm3 mode + en_adcmp_buf_t enBuf; ///< configure Adcmp Buffer transfer type +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + en_adcmp_trig_sel_t enTrigSel; ///< Select trig mode +#else + boolean_t bAdcScanTriggerSel; ///< FALSE: selects the start signal of ADCMP ch.x as ADC unitx scan conversion start signal. + ///< TRUE: Selects the logic OR signal of FRT ch.0 to ch.2 start signal as ADC unitx scan conversion start signal. + boolean_t bAdcPrioTriggerSel; ///< FALSE: selects the start signal of ADCMP ch.x as ADC unitx priority conversion start signal. + ///< TRUE: Selects the logic OR signal of FRT ch.0 to ch.2 start signal as ADC unitx priority conversion start signal. +#endif + +}stc_mft_adcmp_config_fm3_t; + +/** \} GroupMFT_ADCMP_DataStructures */ + +/** +* \addtogroup GroupMFT_ADCMP_Functions +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Global function prototypes (definition in C source) + ******************************************************************************/ +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/* 1. FM4/FM0+ */ +/* Init */ +en_result_t Mft_Adcmp_Init (volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8Ch, + const stc_mft_adcmp_config_t *pstcConfig); +en_result_t Mft_Adcmp_DeInit(volatile stc_mftn_adcmp_t* pstcMftAdcmp, + uint8_t u8Ch); +/* Func enable/disable */ +en_result_t Mft_Adcmp_EnableOperation(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8Ch, + stc_mft_adcmp_func_t* pstcFunc); +en_result_t Mft_Adcmp_DisableOperation(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8Ch, + stc_mft_adcmp_func_t* pstcFunc); +/* Count write/read */ +en_result_t Mft_Adcmp_WriteAcmp(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8Ch, + uint16_t u16AcmpVal); +uint16_t Mft_Adcmp_ReadAcmp(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8Ch); +#endif +/* 2. FM3/FM0+/FM4 */ +/* Init/De-Init */ +en_result_t Mft_Adcmp_Init_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch, + const stc_mft_adcmp_config_fm3_t *pstcConfig); +en_result_t Mft_Adcmp_DeInit_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, + uint8_t u8FM3Ch); +/* Mode configuration */ +en_result_t Mft_Adcmp_EnableOperation_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8FM3Ch); +en_result_t Mft_Adcmp_DisableOperation_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8FM3Ch); +/* Count write/read */ +en_result_t Mft_Adcmp_WriteAccp_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8FM3Ch, uint16_t u16AccpVal); +uint16_t Mft_Adcmp_ReadAccp_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8FM3Ch); +en_result_t Mft_Adcmp_WriteAccpdn_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8FM3Ch, uint16_t u16AccpdnVal); +uint16_t Mft_Adcmp_ReadAccpdn_Fm3(volatile stc_mftn_adcmp_t *pstcMftAdcmp, uint8_t u8FM3Ch); + +/** \} GroupMFT_ADCMP_Functions */ +/** \} GroupMFT_ADCMP */ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_frt.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_frt.c new file mode 100644 index 0000000000..fcc8a0b924 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_frt.c @@ -0,0 +1,1139 @@ +/******************************************************************************* +* \file mft_frt.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the +* MFT_FRT driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mft/mft_frt.h" + +#if (defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM3_CORE) +#define MFT_FRT_REG_OFFSET (0x10u) +#elif (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +#define MFT_FRT_REG_OFFSET (0x0Cu) +#endif + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled FRT of MFT instances and their internal data +stc_mft_frt_instance_data_t m_astcMftFrtInstanceDataLut[] = +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_FRT == PDL_ON) + { + &MFT0_FRT, // pstcInstance + {0u, 0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_FRT == PDL_ON) + { + &MFT1_FRT, // pstcInstance + {0u, 0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_FRT == PDL_ON) + { + &MFT2_FRT, // pstcInstance + {0u, 0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +/** + ***************************************************************************** + ** \brief Return the internal data for a certain FRT instance. + ** + ** \param pstcFrt Pointer to FRT instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled + ** (or not known) + ** + *****************************************************************************/ +static stc_mft_frt_intern_data_t* MftGetInternDataPtr(volatile stc_mftn_frt_t* pstcFrt) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < FRT_INSTANCE_COUNT; u32Instance++) + { + if (pstcFrt == m_astcMftFrtInstanceDataLut[u32Instance].pstcInstance) + { + return &m_astcMftFrtInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) +/*! + ****************************************************************************** + ** \brief FRT interrupt handler sub function + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] pstcMftFrtInternData structure of frt callback function + ** + ** \retval void + ** + ***************************************************************************** +*/ +void Mft_Frt_IrqHandler( volatile stc_mftn_frt_t*pstcMft, + stc_mft_frt_intern_data_t* pstcMftFrtInternData) +{ + func_ptr_t pfnCallBack; + uint32_t* pu32Temp; + uint8_t u8Ch; + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + + /* Peak match Interrupt */ + for(u8Ch = 0u; u8Ch < 3u; u8Ch++) + { + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 +u8Ch*MFT_FRT_REG_OFFSET); + + if((PdlSet == Mft_Frt_GetIrqFlag(pstcMft, u8Ch, enFrtPeakMatchIrq)) && (1u == pstcTCSA->ICRE)) + { + /* Clear Interrupt */ + Mft_Frt_ClrIrqFlag(pstcMft, u8Ch, enFrtPeakMatchIrq); + + //get peak match callback address of each channel + pu32Temp = (uint32_t*)&(pstcMftFrtInternData->pfnFrt0PeakIrqCb); + pfnCallBack = (func_ptr_t)(*(pu32Temp + 2u*u8Ch)); + + if(pfnCallBack != NULL) + { + pfnCallBack(); + } + } + + if((PdlSet == Mft_Frt_GetIrqFlag(pstcMft, u8Ch, enFrtZeroMatchIrq)) && (1u == pstcTCSA->IRQZE)) + { + /* Clear Interrupt */ + Mft_Frt_ClrIrqFlag(pstcMft, u8Ch, enFrtZeroMatchIrq); + + //get Zero match callback address of each channel + pu32Temp = (uint32_t*)&(pstcMftFrtInternData->pfnFrt0ZeroIrqCb); + pfnCallBack = (func_ptr_t)(*(pu32Temp + 2u*u8Ch)); + + if(pfnCallBack != NULL) + { + pfnCallBack(); + } + } + } + +} + +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in l3.h + ** + ** \param pstcMft Pointer to FRT instance + ** + ** \return Ok Successful initialization + ** + ******************************************************************************/ +static void MftFrtInitIrq( volatile stc_mftn_frt_t* pstcMft) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(MFT0_FRT_IRQn); + NVIC_EnableIRQ(MFT0_FRT_IRQn); + NVIC_SetPriority(MFT0_FRT_IRQn, PDL_IRQ_LEVEL_MFT_FRT); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(MFT0_2_FRT_IRQn); + NVIC_EnableIRQ(MFT0_2_FRT_IRQn); + NVIC_SetPriority(MFT0_2_FRT_IRQn, PDL_IRQ_LEVEL_MFT_FRT); +#else +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) + if(&MFT0_FRT == pstcMft) + { + NVIC_ClearPendingIRQ(MFT0_FRT_PEAK_IRQn); + NVIC_EnableIRQ(MFT0_FRT_PEAK_IRQn); + NVIC_SetPriority(MFT0_FRT_PEAK_IRQn, PDL_IRQ_LEVEL_MFT0_FRT); + + NVIC_ClearPendingIRQ(MFT0_FRT_ZERO_IRQn); + NVIC_EnableIRQ(MFT0_FRT_ZERO_IRQn); + NVIC_SetPriority(MFT0_FRT_ZERO_IRQn, PDL_IRQ_LEVEL_MFT0_FRT); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) + if(&MFT1_FRT == pstcMft) + { + NVIC_ClearPendingIRQ(MFT1_FRT_PEAK_IRQn); + NVIC_EnableIRQ(MFT1_FRT_PEAK_IRQn); + NVIC_SetPriority(MFT1_FRT_PEAK_IRQn, PDL_IRQ_LEVEL_MFT1_FRT); + + NVIC_ClearPendingIRQ(MFT1_FRT_ZERO_IRQn); + NVIC_EnableIRQ(MFT1_FRT_ZERO_IRQn); + NVIC_SetPriority(MFT1_FRT_ZERO_IRQn, PDL_IRQ_LEVEL_MFT1_FRT); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) + if(&MFT2_FRT == pstcMft) + { + NVIC_ClearPendingIRQ(MFT2_FRT_PEAK_IRQn); + NVIC_EnableIRQ(MFT2_FRT_PEAK_IRQn); + NVIC_SetPriority(MFT2_FRT_PEAK_IRQn, PDL_IRQ_LEVEL_MFT2_FRT); + + NVIC_ClearPendingIRQ(MFT2_FRT_ZERO_IRQn); + NVIC_EnableIRQ(MFT2_FRT_ZERO_IRQn); + NVIC_SetPriority(MFT2_FRT_ZERO_IRQn, PDL_IRQ_LEVEL_MFT2_FRT); + } +#endif +#endif + + return; +} + + +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in l3.h + ** + ** \param pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \return Ok Successful initialization + ** + ******************************************************************************/ +static void MftFrtDeInitIrq( volatile stc_mftn_frt_t* pstcMft) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(MFT0_FRT_IRQn); + NVIC_DisableIRQ(MFT0_FRT_IRQn); + NVIC_SetPriority(MFT0_FRT_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(MFT0_2_FRT_IRQn); + NVIC_DisableIRQ(MFT0_2_FRT_IRQn); + NVIC_SetPriority(MFT0_2_FRT_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) + if(&MFT0_FRT == pstcMft) + { + NVIC_ClearPendingIRQ(MFT0_FRT_PEAK_IRQn); + NVIC_DisableIRQ(MFT0_FRT_PEAK_IRQn); + NVIC_SetPriority(MFT0_FRT_PEAK_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + + NVIC_ClearPendingIRQ(MFT0_FRT_ZERO_IRQn); + NVIC_DisableIRQ(MFT0_FRT_ZERO_IRQn); + NVIC_SetPriority(MFT0_FRT_ZERO_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) + if(&MFT1_FRT == pstcMft) + { + NVIC_ClearPendingIRQ(MFT1_FRT_PEAK_IRQn); + NVIC_DisableIRQ(MFT1_FRT_PEAK_IRQn); + NVIC_SetPriority(MFT1_FRT_PEAK_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + + NVIC_ClearPendingIRQ(MFT1_FRT_ZERO_IRQn); + NVIC_DisableIRQ(MFT1_FRT_ZERO_IRQn); + NVIC_SetPriority(MFT1_FRT_ZERO_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) + if(&MFT2_FRT == pstcMft) + { + NVIC_ClearPendingIRQ(MFT2_FRT_PEAK_IRQn); + NVIC_DisableIRQ(MFT2_FRT_PEAK_IRQn); + NVIC_SetPriority(MFT2_FRT_PEAK_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + + NVIC_ClearPendingIRQ(MFT2_FRT_ZERO_IRQn); + NVIC_DisableIRQ(MFT2_FRT_ZERO_IRQn); + NVIC_SetPriority(MFT2_FRT_ZERO_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#endif + + return; +} + +#endif + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Init FRT Channel + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** \param [in] pstcFrtConfig configure of FRT + ** \arg structure of FRT cofnigure + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - pstcFrtConfig == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Frt_Init(volatile stc_mftn_frt_t *pstcMft, + uint8_t u8Ch, + const stc_mft_frt_config_t* pstcFrtConfig) +{ + // Pointer to internal data + stc_mft_frt_intern_data_t* pstcFrtInternData ; + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; +#if (PDL_MCU_CORE == PDL_FM3_CORE) + volatile stc_mft_frt_tcsb0_field_t* pstcTCSB; +#endif + uint8_t u8ClkDiv; + + // Check for NULL pointer and configuration parameter + if ((NULL == pstcMft) || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcFrtInternData = MftGetInternDataPtr( pstcMft ) ; + // ... and check for NULL + if ( NULL == pstcFrtInternData ) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); +#if (PDL_MCU_CORE == PDL_FM3_CORE) + pstcTCSB = (volatile stc_mft_frt_tcsb0_field_t*)((volatile uint8_t*)&pstcMft->TCSB0 + u8Ch*MFT_FRT_REG_OFFSET); +#endif + + //set count clock cycle of FRT counter + u8ClkDiv = (uint8_t)pstcFrtConfig->enFrtClockDiv; + switch (pstcFrtConfig->enFrtClockDiv) + { + case FrtPclkDiv1: + case FrtPclkDiv2: + case FrtPclkDiv4: + case FrtPclkDiv8: + case FrtPclkDiv16: + case FrtPclkDiv32: + case FrtPclkDiv64: + case FrtPclkDiv128: + case FrtPclkDiv256: + #if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case FrtPclkDiv512: + case FrtPclkDiv1024: + #endif + pstcTCSA->CLK = (u8ClkDiv & 0x0Fu); + break; + default: + return ErrorInvalidParameter ; + } + + //set frt mode + switch (pstcFrtConfig->enFrtMode) + { + case FrtUpCount: + pstcTCSA->MODE = 0u; + break; + case FrtUpDownCount: + pstcTCSA->MODE = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + //set buffer enable bit + pstcTCSA->BFE = (pstcFrtConfig->bEnBuffer == TRUE) ? 1u : 0u; + + //set external clock enable bit + pstcTCSA->ECKE = (pstcFrtConfig->bEnExtClock == TRUE) ? 1u : 0u; + +#if (PDL_MCU_CORE == PDL_FM3_CORE) + // Set ADC trigger + pstcTCSB->AD0E = ((pstcFrtConfig->bTriggerAdc0 == TRUE) ? 1u: 0u); + pstcTCSB->AD1E = ((pstcFrtConfig->bTriggerAdc1 == TRUE) ? 1u: 0u); + pstcTCSB->AD2E = ((pstcFrtConfig->bTriggerAdc2 == TRUE) ? 1u: 0u); +#endif + +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) + // Set interrupt enable + if (NULL != pstcFrtConfig->pstcIrqEn) + { + if(pstcFrtConfig->pstcIrqEn->bFrtZeroMatchIrq == TRUE) + { + pstcTCSA->IRQZE = 1u; + } + + if(pstcFrtConfig->pstcIrqEn->bFrtPeakMatchIrq == TRUE) + { + pstcTCSA->ICRE = 1u; + } + } + + // Set interrupt callback function + if (NULL != pstcFrtConfig->pstcIrqCb) + { + switch (u8Ch) + { + case 0u: + pstcFrtInternData->pfnFrt0PeakIrqCb = pstcFrtConfig->pstcIrqCb->pfnFrtPeakIrqCb; + pstcFrtInternData->pfnFrt0ZeroIrqCb = pstcFrtConfig->pstcIrqCb->pfnFrtZeroIrqCb; + break; + case 1u: + pstcFrtInternData->pfnFrt1PeakIrqCb = pstcFrtConfig->pstcIrqCb->pfnFrtPeakIrqCb; + pstcFrtInternData->pfnFrt1ZeroIrqCb = pstcFrtConfig->pstcIrqCb->pfnFrtZeroIrqCb; + break; + case 2u: + pstcFrtInternData->pfnFrt2PeakIrqCb = pstcFrtConfig->pstcIrqCb->pfnFrtPeakIrqCb; + pstcFrtInternData->pfnFrt2ZeroIrqCb = pstcFrtConfig->pstcIrqCb->pfnFrtZeroIrqCb; + break; + default: + break; + } + } + + if(pstcFrtConfig->bTouchNvic == TRUE) + { + MftFrtInitIrq(pstcMft); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Init FRT Channel + ** + ** Clear a FRT channel. + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch channel of Free run timer + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Register been cleared + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Frt_DeInit(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + boolean_t bTouchNvic) +{ + volatile uint16_t* pu16TCSA; +#if (PDL_MCU_CORE == PDL_FM3_CORE) + volatile uint16_t* pu16TCSB; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile uint16_t* pu16TCSC; +#endif + + volatile uint16_t* pu16TCCP; + + // Check for NULL pointer and configuration parameter + if ((NULL == pstcMft) || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pu16TCSA = (volatile uint16_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); + *pu16TCSA = 0x0040u; +#if (PDL_MCU_CORE == PDL_FM3_CORE) + pu16TCSB = (volatile uint16_t*)((volatile uint8_t*)&pstcMft->TCSB0 + u8Ch*MFT_FRT_REG_OFFSET); + *pu16TCSB = 0x0000u; +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pu16TCSC = (volatile uint16_t*)((volatile uint8_t*)&pstcMft->TCSC0 + u8Ch*MFT_FRT_REG_OFFSET); + *pu16TCSC = 0x0000u; +#endif + + pu16TCCP = (volatile uint16_t*)((volatile uint8_t*)&pstcMft->TCCP0 + u8Ch*MFT_FRT_REG_OFFSET); + *pu16TCCP = 0x0000u; + +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) + if(TRUE == bTouchNvic) + { + MftFrtDeInitIrq(pstcMft); + } +#endif + + return Ok; +} + + +/*! + ****************************************************************************** + ** \brief Start FRT + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_Start(volatile stc_mftn_frt_t*pstcMft, uint8_t u8Ch) +{ + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); + pstcTCSA->STOP = 0u; + pstcTCSA->SCLR = 0u; + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief set frt stop + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_Stop(volatile stc_mftn_frt_t*pstcMft, uint8_t u8Ch) +{ + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); + + pstcTCSA->STOP = 1u; + pstcTCSA->SCLR = 1u; + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) +/*! + ****************************************************************************** + ** \brief enable frt interrupt + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \param [in] pstcIrqSel Pointer to FRT interrupt selection structure + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_EnableIrq(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + stc_frt_irq_sel_t* pstcIrqSel) +{ + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH) ) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 +u8Ch*MFT_FRT_REG_OFFSET); + + if(1u == pstcIrqSel->bFrtZeroMatchIrq) //zero detect interrupt + { + pstcTCSA->IRQZE = 1u; + } + if(1u == pstcIrqSel->bFrtPeakMatchIrq) //peak detect interrupt + { + pstcTCSA->ICRE = 1u; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief disable frt interrupt + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \param [in] pstcIrqSel Pointer to FRT interrupt selection structure + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_DisableIrq(volatile stc_mftn_frt_t*pstcMft,uint8_t u8Ch, + stc_frt_irq_sel_t* pstcIrqSel) +{ + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); + + if(1u == pstcIrqSel->bFrtZeroMatchIrq) //zero detect interrupt + { + pstcTCSA->IRQZE = 0u; + } + if(1u == pstcIrqSel->bFrtPeakMatchIrq) //peak detect interrupt + { + pstcTCSA->ICRE = 0u; + } + + + return Ok; +} + +#endif + +/*! + ****************************************************************************** + ** \brief get frt interrupt flag + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + + ** \param [in] enIrqType Interrupt type + ** \arg enFrtZeroMatchIrq Zero match interrupt of FRT + ** \arg enFrtPeakMatchIrq Peak match interrupt of FRT + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_irq_flag_t Mft_Frt_GetIrqFlag(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + en_mft_frt_irq_t enIrqType) +{ + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + en_irq_flag_t retval; + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); + + if(enFrtZeroMatchIrq == enIrqType) //zero detect interrupt + { + (pstcTCSA->IRQZF == 1u) ? (retval = PdlSet) : (retval = PdlClr); + } + else //peak detect interrupt + { + (pstcTCSA->ICLR == 1u) ? (retval = PdlSet) : (retval = PdlClr); + } + + return retval; +} + +/*! + ****************************************************************************** + ** \brief clear frt interrupt falg + ** + ** \param [in] pstcMft MFT register definition + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \param [in] enIrqType the type of interrupt + ** \arg enFrtZeroMatchIrq Zero match interrupt of FRT + ** \arg enFrtPeakMatchIrq Peak match interrupt of FRT + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_ClrIrqFlag(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + en_mft_frt_irq_t enIrqType) +{ + volatile stc_mft_frt_tcsa0_field_t* pstcTCSA; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSA = (volatile stc_mft_frt_tcsa0_field_t*)((volatile uint8_t*)&pstcMft->TCSA0 + u8Ch*MFT_FRT_REG_OFFSET); + + if(enFrtZeroMatchIrq == enIrqType) //zero detect interrupt + { + pstcTCSA->IRQZF = 0u; + } + else //peak detect interrupt + { + pstcTCSA->ICLR = 0u; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief set frt cycle value + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \param [in] u16Cycle the cycle value + ** \arg number of 16bit + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_SetCountCycle(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + uint16_t u16Cycle) +{ + volatile uint16_t* pu16TCCP; + + // Check for NULL pointer + if ( (pstcMft == NULL) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pu16TCCP = (volatile uint16_t*)( (volatile uint8_t*)&pstcMft->TCCP0 + u8Ch*MFT_FRT_REG_OFFSET); + + *pu16TCCP = u16Cycle; + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief set frt count value + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \param [in] u16Count the count value + ** \arg number of 16bit + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Frt_SetCountVal(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + uint16_t u16Count) +{ + volatile uint16_t* pu16TCDT; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pu16TCDT = (volatile uint16_t*)( (volatile uint8_t*)&pstcMft->TCDT0 + u8Ch*MFT_FRT_REG_OFFSET); + + *pu16TCDT = u16Count; + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief get frt current count + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \retval current count of frt + ** + ***************************************************************************** +*/ +uint16_t Mft_Frt_GetCurCount(volatile stc_mftn_frt_t*pstcMft, uint8_t u8Ch) +{ + uint16_t retTCDT; + volatile uint16_t* pstcTCDT; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCDT = (volatile uint16_t*)( (volatile uint8_t*)&pstcMft->TCDT0 + u8Ch*MFT_FRT_REG_OFFSET); + + retTCDT = *pstcTCDT; + + return retTCDT; +} + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +/** + ****************************************************************************** + ** \brief set mask zero times + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** \param [in] u8Times mask times + ** \arg value of 0~15 + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Frt_SetMaskZeroTimes(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + uint8_t u8Times) +{ + volatile stc_mft_frt_tcsc0_field_t* pstcTCSC; + + // Check for NULL pointer + if ( (NULL == pstcMft) || + (u8Ch >= MFT_FRT_MAX_CH) || + (u8Times > 15u) ) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSC=(volatile stc_mft_frt_tcsc0_field_t*)((volatile uint8_t*)&pstcMft->TCSC0 + u8Ch*MFT_FRT_REG_OFFSET); + + pstcTCSC->MSZI = u8Times; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get current mask zero times + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +uint8_t Mft_Frt_GetCurMaskZeroTimes(volatile stc_mftn_frt_t*pstcMft, uint8_t u8Ch) +{ + volatile stc_mft_frt_tcsc0_field_t* pu16TCSC; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return 0xFFu ; + } + + //Get pointer of current channel frt register address + pu16TCSC = (volatile stc_mft_frt_tcsc0_field_t*)((volatile uint8_t*)&pstcMft->TCSC0 + u8Ch*MFT_FRT_REG_OFFSET); + + return pu16TCSC->MSZC; +} +/** + ****************************************************************************** + ** \brief set mask peak times + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** \param [in] u8Times mask times + ** \arg value of 0~15 + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Frt_SetMaskPeakTimes(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, uint8_t u8Times) +{ + volatile stc_mft_frt_tcsc0_field_t* pstcTCSC; + + // Check for NULL pointer + if ( (NULL == pstcMft) || + (u8Ch >= MFT_FRT_MAX_CH) || + (u8Times > 15u) ) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSC = (volatile stc_mft_frt_tcsc0_field_t*)((volatile uint8_t*)&pstcMft->TCSC0 + u8Ch*MFT_FRT_REG_OFFSET); + + pstcTCSC->MSPI = u8Times;; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief get mask peak times + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** + ** \param [in] u8Ch channel of Free run timer + ** \arg MFT_FRT_CH0 ~ MFT_FRT_CH2 + ** + ** \retval Current mask peak times + ** + ******************************************************************************/ +uint8_t Mft_Frt_GetCurMaskPeakTimes(volatile stc_mftn_frt_t*pstcMft, uint8_t u8Ch) +{ + volatile stc_mft_frt_tcsc0_field_t* pstcTCSC; + + // Check for NULL pointer + if ( (NULL == pstcMft) + || (u8Ch >= MFT_FRT_MAX_CH)) + { + return 0xFFu ; + } + + //Get pointer of current channel frt register address + pstcTCSC = (volatile stc_mft_frt_tcsc0_field_t*)((volatile uint8_t*)&pstcMft->TCSC0 + u8Ch*MFT_FRT_REG_OFFSET); + + return pstcTCSC->MSPC; +} + +#endif + +/** + ****************************************************************************** + ** \brief Configure FRT channel to offest mode or normall mode + ** + ** The FRT channel 1 or 2, set to offset mode, will be working with FRT channel + ** 0 with offset mode. The channel with offset mode will follow the behavior + ** FRT channel 0, thus it is no need to call Mft_Frt_Init() to initialize this + ** channel. See peripheral manual about offset mode for the details. + ** + ** \param [in] pstcMft Pointer to FRT instance + ** \arg the pointer of FRT register structure + ** \param [in] u8Ch Channel of Free run timer + ** \arg FrtOffsetCh1 FRT channel 1 which can be set to offset mode + ** \arg FrtOffsetCh2 FRT channel 2 which can be set to offset mode + ** \param [in] bOffsetMode + ** \arg TRUE Set the FRT channel to Offset mode + ** \arg FALSE Set the FRT channel to normal mode + ** + ** \retval Ok Mode has been set normally + ** \retval ErrorInvalidParameter If oen of following cases match: + ** - pstcMft == NULL + ** - enCh out of range + ** + ** \note Only TYPE3 of FM4 or later products has this function. + ** + ******************************************************************************/ +#if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) +en_result_t Mft_Frt_SetOffsetMode(volatile stc_mftn_frt_t*pstcMft, + uint8_t u8Ch, + boolean_t bOffsetMode) +{ + volatile stc_mft_frt_tcsd_field_t* pstcTCSD; + + if(NULL == pstcMft) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel frt register address + pstcTCSD = (volatile stc_mft_frt_tcsd_field_t*)((volatile uint8_t*)&pstcMft->TCSD); + + switch (u8Ch) + { + case 1u: + pstcTCSD->OFMD1 = (bOffsetMode == TRUE) ? 1u : 0u; + break; + case 2u: + pstcTCSD->OFMD2 = (bOffsetMode == TRUE) ? 1u : 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Set the Simultaneous Start register of MFT + ** + ** \param [in] u16Stop Bit0 ----- MFT unit.0 Ch.0 + ** Bit1 ----- MFT unit.0 Ch.1 + ** Bit2 ----- MFT unit.0 Ch.2 + ** Bit3 ----- MFT unit.1 Ch.0 + ** Bit4 ----- MFT unit.1 Ch.1 + ** Bit5 ----- MFT unit.1 Ch.2 + ** Bit6 ----- MFT unit.2 Ch.0 + ** Bit7 ----- MFT unit.2 Ch.1 + ** Bit8 ----- MFT unit.2 Ch.2 + ** \arg 0 Start FRT + ** \arg 1 Stop FRT + ** + ** \param [in] u16Clr Bit0 ----- MFT unit.0 Ch.0 + ** Bit1 ----- MFT unit.0 Ch.1 + ** Bit2 ----- MFT unit.0 Ch.2 + ** Bit3 ----- MFT unit.1 Ch.0 + ** Bit4 ----- MFT unit.1 Ch.1 + ** Bit5 ----- MFT unit.1 Ch.2 + ** Bit6 ----- MFT unit.2 Ch.0 + ** Bit7 ----- MFT unit.2 Ch.1 + ** Bit8 ----- MFT unit.2 Ch.2 + ** \arg 0 Do nothing + ** \arg 1 Issues FRT operation state initialization request. + ** + ** \retval Ok Simultaneous start register is set + ******************************************************************************/ +en_result_t Mft_Frt_SetSimultaneousStart(uint16_t u16Stop, uint16_t u16Clr) +{ + volatile stc_mftn_frt_t* pstcFrt = &MFT0_FRT; + + pstcFrt->TCAL = (u16Stop | (u16Clr << 16u)); + + return Ok; +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_$$X_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_frt.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_frt.h new file mode 100644 index 0000000000..47db4f7450 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_frt.h @@ -0,0 +1,379 @@ +/******************************************************************************* +* \file mft_frt.h +* +* \version 1.20 +* +* \brief Headerfile for MFT_FRT functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MFT_FRT_H__ +#define __MFT_FRT_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE)) + +/** +* \defgroup GroupMFT_FRT Free-run Timer (MFT FRT) +* \{ +* \defgroup GroupMFT_FRT_Macros Macros +* \defgroup GroupMFT_FRT_Functions Functions +* \defgroup GroupMFT_FRT_GlobalVariables Global Variables +* \defgroup GroupMFT_FRT_DataStructures Data Structures +* \defgroup GroupMFT_FRT_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupMFT_FRT +* \{ +* The Multi-function Timer (MFT) is a collection of peripherals used primarily for +* motor control. There may be up to three MFTs supported on a particular FM microcontroller. +* One MFT can control a 3-phase motor. A microcontroller that supports multiple MFTs can +* control multiple 3-phase motors.
+* The peripherals in the MFT are:
+* - Free-run Timer (FRT)
+* - Output Compare Unit (OCU)
+* - Waveform Generator (WFG)
+* - Input Capture Unit (ICU)
+* - ADC Start Compare (ADCMP)
+* The FRT is a timer function block that outputs the reference counter value for the +* operation of each function block in the MFT.
+* All operations of the MFT are synchronized with this unit. There are three separate +* FRT instances within the MFT. For example, any OCU instance (up to 6) can be connected +* to any FRT instance (up to 3). This enables significant flexibility in timing and behavior.
+* The clock for the FRT is generated from the Peripheral bus clock (PCLK) or an external clock. +* This clock drives the FRT’s 16-bit counter based on the clock frequency and a clock divider. +* The counter counts from zero to a programmable maximum value (the count cycle value) up to 16-bits.
+* The counter operates in one of two modes: up-count, or up/down-count. In up-count mode the +* counter runs from zero to the count cycle value, then returns to zero and counts up again. +* In up/down-count mode, the counter counts up to its maximum value, and then counts down to zero, +* completing the cycle.
+* The FRT can generate interrupts when it reaches the top or bottom value. You can set a mask +* value (0-15) that determines how often to generate either interrupt. For example, +* generate an interrupt on every 4th bottom, and every 8th top. You can also configure the +* FRT to trigger an ADC conversion when the counter reaches zero.
+* + +* \section SectionMFT_FRT_ConfigurationConsideration Configuration Consideration +* To set up the FRT, you provide configuration parameters in the stc_mft_frt_config_t structure, +* such as the operation mode, the clock divider, and whether to use an external clock. +* You also provide the structures to define interrupt handlers. Then call Mft_Frt_Init().
+* You must also call Mft_Frt_SetCountCycle() to set the maximum value for the counter. +* This is not part of the configuration structure, because you may modify this at runtime.
+* When done, call Mft_Frt_Start() to start the counter running.
+* When the counter is running, you can get and set the current count value.
+* You can enable or disable interrupts at runtime. In polling mode, use Mft_Frt_GetIrqFlag() +* to check whether the interrupt occurs, and clear the interrupt flag by Mft_Frt_ClrIrqFlag(). +* You can also get or set the mask value for either the zero or peak value interrupts.
+* As noted, there are three FRT instances. You can use Mft_Frt_SetSimultaneousStart() to +* start multiple FRTs at the same time. +* +* \section SectionMFT_FRT_MoreInfo More Information +* For more information on the MFT FRT peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupMFT_FRT_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_mftn_frt_t FM_MFT_FRT_TypeDef +#define MFT0_FRT (*((volatile stc_mftn_frt_t *) FM_MFT0_FRT_BASE)) +#define MFT1_FRT (*((volatile stc_mftn_frt_t *) FM_MFT1_FRT_BASE)) +#define MFT2_FRT (*((volatile stc_mftn_frt_t *) FM_MFT2_FRT_BASE)) + +#define FRT_INSTANCE_COUNT (PDL_PERIPHERAL_ENABLE_MFT0_FRT == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_MFT1_FRT == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_MFT2_FRT == PDL_ON ? 1u : 0u) + +/** + ****************************************************************************** + ** \brief MFT Frt channel definition + ******************************************************************************/ +#define MFT_FRT_CH0 0u +#define MFT_FRT_CH1 1u +#define MFT_FRT_CH2 2u + +#define MFT_FRT_MAX_CH 3u + +/** \} GroupMFT_FRT_Macros */ + +/** +* \addtogroup GroupMFT_FRT_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each FRT instance + ******************************************************************************/ +typedef enum en_frt_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_FRT == PDL_ON) + FrtInstanceIndexFrt0, ///< Instance index of FRT0 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_FRT == PDL_ON) + FrtInstanceIndexFrt1, ///< Instance index of FRT1 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_FRT == PDL_ON) + FrtInstanceIndexFrt2, ///< Instance index of FRT2 +#endif +} en_frt_instance_index_t; + +/** + ****************************************************************************** + ** \brief Mft Clock Setting + ******************************************************************************/ +typedef enum en_mft_frt_clock +{ + FrtPclkDiv1 = 0u, ///< FRT clock: PCLK + FrtPclkDiv2 = 1u, ///< FRT clock: PCLK/2 + FrtPclkDiv4 = 2u, ///< FRT clock: PCLK/4 + FrtPclkDiv8 = 3u, ///< FRT clock: PCLK/8 + FrtPclkDiv16 = 4u, ///< FRT clock: PCLK/16 + FrtPclkDiv32 = 5u, ///< FRT clock: PCLK/32 + FrtPclkDiv64 = 6u, ///< FRT clock: PCLK/64 + FrtPclkDiv128 = 7u, ///< FRT clock: PCLK/128 + FrtPclkDiv256 = 8u, ///< FRT clock: PCLK/256 +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + FrtPclkDiv512 = 9u, ///< FRT clock: PCLK/512 + FrtPclkDiv1024 = 10u, ///< FRT clock: PCLK/1024 +#endif +} en_mft_frt_clock_t; + +/** + ****************************************************************************** + ** \brief FRT count mode + ******************************************************************************/ +typedef enum en_mft_frt_mode +{ + FrtUpCount = 0u, ///< FRT up-count mode + FrtUpDownCount = 1u ///< FRT up-/down-count mode +} en_mft_frt_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration of FRT interrupt index + ******************************************************************************/ +typedef enum en_mft_frt_int +{ + enFrtZeroMatchIrq = 0u, ///< zero match interrupt index + enFrtPeakMatchIrq = 1u, ///< peak match interrupt index + +}en_mft_frt_irq_t; + +/** + ****************************************************************************** + ** \brief Enumeration of FRT channels with offset mode + ******************************************************************************/ +typedef enum en_frt_offset_ch +{ + FrtOffsetCh1 = 0u, ///< FRT ch.1 with offset mode + FrtOffsetCh2 = 1u, ///< FRT ch.2 with offset mode + +}en_frt_offset_ch_t; + +/** \} GroupMFT_FRT_Types */ + +/** +* \addtogroup GroupMFT_FRT_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration of FRT interrupt selection + ******************************************************************************/ +typedef struct stc_frt_int_sel +{ + boolean_t bFrtZeroMatchIrq; ///< zero match interrupt selection + boolean_t bFrtPeakMatchIrq; ///< peak match interrupt selection + +}stc_frt_irq_sel_t, stc_frt_irq_en_t; + +/** + ****************************************************************************** + ** \brief FRT interrupt callback function + ******************************************************************************/ +typedef struct stc_frt_int_cb +{ + func_ptr_t pfnFrtZeroIrqCb; ///< match zero interrupt callback function + func_ptr_t pfnFrtPeakIrqCb; ///< match peak interrupt callback function + +}stc_frt_irq_cb_t; + +/** + ****************************************************************************** + ** \brief FRT configure + ******************************************************************************/ +typedef struct stc_mft_frt_config +{ + en_mft_frt_clock_t enFrtClockDiv; ///< FRT clock divide + en_mft_frt_mode_t enFrtMode; ///< FRT count mode + boolean_t bEnBuffer; ///< enable buffer + boolean_t bEnExtClock; ///< enable external clock +#if (PDL_MCU_CORE == PDL_FM3_CORE) + boolean_t bTriggerAdc0; ///< TRUE: Output AD conversion start signal to ADC uint 0 upon FRT zreo match event + ///< FALSE: Don't output AD conversion start signal to ADC uint 0 upon FRT zreo match event + boolean_t bTriggerAdc1; ///< TRUE: Output AD conversion start signal to ADC uint 1 upon FRT zreo match event + ///< FALSE: Don't output AD conversion start signal to ADC uint 1 upon FRT zreo match event + boolean_t bTriggerAdc2; ///< TRUE: Output AD conversion start signal to ADC uint 2 upon FRT zreo match event + ///< FALSE: Don't output AD conversion start signal to ADC uint 2 upon FRT zreo match event +#endif + stc_frt_irq_en_t* pstcIrqEn; ///< Pointer to FRT interrupt enable structure + stc_frt_irq_cb_t* pstcIrqCb; ///< Pointer to FRT interrupt callback functions structure + boolean_t bTouchNvic; ///< TRUE: Enable NVIC, FALSE: don't enable NVIC + +}stc_mft_frt_config_t; + +/** + ****************************************************************************** + ** \brief FRT instance internal data, storing internal + ** information for each enabled FRT instance. + ******************************************************************************/ +typedef struct stc_mft_frt_intern_data +{ + func_ptr_t pfnFrt0PeakIrqCb; ///< Callback function pointer of FRT0 peak detection interrupt + func_ptr_t pfnFrt0ZeroIrqCb; ///< Callback function pointer of FRT0 zero detection interrupt + func_ptr_t pfnFrt1PeakIrqCb; ///< Callback function pointer of FRT1 peak detection interrupt + func_ptr_t pfnFrt1ZeroIrqCb; ///< Callback function pointer of FRT1 zero detection interrupt + func_ptr_t pfnFrt2PeakIrqCb; ///< Callback function pointer of FRT2 peak detection interrupt + func_ptr_t pfnFrt2ZeroIrqCb; ///< Callback function pointer of FRT2 zero detection interrupt + +}stc_mft_frt_intern_data_t; + +/** + ****************************************************************************** + ** \brief FRT instance data type + ******************************************************************************/ +typedef struct stc_mft_frt_instance_data +{ + volatile stc_mftn_frt_t* pstcInstance; ///< pointer to registers of an instance + stc_mft_frt_intern_data_t stcInternData; ///< module internal data of instance +} stc_mft_frt_instance_data_t; + +/** \} GroupMFT_FRT_DataStructures */ + +/** +* \addtogroup GroupMFT_FRT_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/// Look-up table for all enabled FRT of MFT instances and their internal data +extern stc_mft_frt_instance_data_t m_astcMftFrtInstanceDataLut[FRT_INSTANCE_COUNT]; + +/** \} GroupMFT_FRT_GlobalVariables */ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \addtogroup GroupMFT_FRT_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +/* Init */ +en_result_t Mft_Frt_Init(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, const stc_mft_frt_config_t* pstcFrtConfig); +en_result_t Mft_Frt_DeInit(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch, + boolean_t bTouchNvic); +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +/* Mask zero/peak write/read */ +en_result_t Mft_Frt_SetMaskZeroTimes(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + uint8_t u8Times); +uint8_t Mft_Frt_GetCurMaskZeroTimes(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch); +en_result_t Mft_Frt_SetMaskPeakTimes(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + uint8_t u8Times); +uint8_t Mft_Frt_GetCurMaskPeakTimes(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch); +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) +#if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) +en_result_t Mft_Frt_SetOffsetMode(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + boolean_t bOffsetMode); +#endif +#endif +/* Func/Int enable/disable */ +en_result_t Mft_Frt_Start(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch); +en_result_t Mft_Frt_Stop(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch); +#if (PDL_INTERRUPT_ENABLE_MFT0_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_FRT == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_FRT == PDL_ON) +en_result_t Mft_Frt_EnableIrq(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + stc_frt_irq_sel_t* pstcIrqSel); +en_result_t Mft_Frt_DisableIrq(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + stc_frt_irq_sel_t* pstcIrqSel); +#endif + +/* Status get/clear */ +en_irq_flag_t Mft_Frt_GetIrqFlag(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + en_mft_frt_irq_t enIrqType); +en_result_t Mft_Frt_ClrIrqFlag(volatile stc_mftn_frt_t* pstcMft, + uint8_t u8Ch, + en_mft_frt_irq_t enIrqType); + +/* Count write/read */ +en_result_t Mft_Frt_SetCountCycle(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch, uint16_t u16Cycle); +en_result_t Mft_Frt_SetCountVal(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch,uint16_t u16Count); +uint16_t Mft_Frt_GetCurCount(volatile stc_mftn_frt_t* pstcMft, uint8_t u8Ch); + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/* Simultaneous Start */ +en_result_t Mft_Frt_SetSimultaneousStart(uint16_t u16Stop, uint16_t u16Clr); +#endif + +/* IRQ handler */ +void Mft_Frt_IrqHandler(volatile stc_mftn_frt_t* pstcMft, stc_mft_frt_intern_data_t* pstcMftFrtInternData) ; + +/** \} GroupMFT_FRT_Functions */ +/** \} GroupMFT_FRT */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE)) + +#endif /* __MFT_H__ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_icu.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_icu.c new file mode 100644 index 0000000000..e55021a6af --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_icu.c @@ -0,0 +1,706 @@ +/******************************************************************************* +* \file mft_icu.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the +* MFT_ICU driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mft/mft_icu.h" + +#if (defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +stc_mft_icu_instance_data_t m_astcMftIcuInstanceDataLut[MFT_ICU_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_ICU == PDL_ON) + { + &MFT0_ICU, // pstcInstance + {0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_ICU == PDL_ON) + { + &MFT1_ICU, // pstcInstance + {0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_ICU == PDL_ON) + { + &MFT2_ICU, // pstcInstance + {0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_MFT0_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_ICU == PDL_ON) +static stc_mft_icu_intern_data_t* MftIcuGetInternDataPtr(volatile stc_mftn_icu_t *pstcMftIcu); +static void Mft_Icu_InitIrq( volatile stc_mftn_icu_t* pstcMftIcu ); +static void Mft_Icu_DeInitIrq( volatile stc_mftn_icu_t* pstcMftIcu ); +#endif +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +#if (PDL_INTERRUPT_ENABLE_MFT0_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_ICU == PDL_ON) +/** + ***************************************************************************** + ** \brief Return the internal data for a certain MFT_ICU instance. + ** + ** \param pstcMftIcu Pointer to MftIcu instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + *****************************************************************************/ +static stc_mft_icu_intern_data_t* MftIcuGetInternDataPtr(volatile stc_mftn_icu_t *pstcMftIcu) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < MFT_ICU_INSTANCE_COUNT; u8Instance++) + { + if (pstcMftIcu == m_astcMftIcuInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcMftIcuInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} + +/** + ****************************************************************************** + ** \brief Device Interrupt handler + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] pstcMftIcuInternData Pointer to intern data + ** + ** \return none + ******************************************************************************/ +void Mft_Icu_IrqHandler( volatile stc_mftn_icu_t* pstcMftIcu, + stc_mft_icu_intern_data_t* pstcMftIcuInternData) +{ + // ICU interrupt 0 + if(TRUE == pstcMftIcu->ICSA10_f.ICP0) + { + pstcMftIcu->ICSA10_f.ICP0 = 0u; + if (pstcMftIcuInternData->pfnIcu0IrqCb != NULL) + { + pstcMftIcuInternData->pfnIcu0IrqCb(); + } + } + // ICU interrupt 1 + if(TRUE == pstcMftIcu->ICSA10_f.ICP1) + { + pstcMftIcu->ICSA10_f.ICP1 = 0u; + if (pstcMftIcuInternData->pfnIcu1IrqCb != NULL) + { + pstcMftIcuInternData->pfnIcu1IrqCb(); + } + } + // ICU interrupt 2 + if(TRUE == pstcMftIcu->ICSA32_f.ICP2) + { + pstcMftIcu->ICSA32_f.ICP2 = 0u; + if (pstcMftIcuInternData->pfnIcu2IrqCb != NULL) + { + pstcMftIcuInternData->pfnIcu2IrqCb(); + } + } + // ICU interrupt 3 + if(TRUE == pstcMftIcu->ICSA32_f.ICP3) + { + pstcMftIcu->ICSA32_f.ICP3 = 0u; + if (pstcMftIcuInternData->pfnIcu3IrqCb != NULL) + { + pstcMftIcuInternData->pfnIcu3IrqCb(); + } + } +} + +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl.h + ** + ** \param pstcMftIcu Pointer to ICU instance + ******************************************************************************/ +static void Mft_Icu_InitIrq( volatile stc_mftn_icu_t* pstcMftIcu ) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_1_A) + NVIC_ClearPendingIRQ(MFT0_ICU_IRQn); + NVIC_EnableIRQ(MFT0_ICU_IRQn); + NVIC_SetPriority(MFT0_ICU_IRQn, PDL_IRQ_LEVEL_MFT_ICU); + #elif (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_2_A) + NVIC_ClearPendingIRQ(USB0_F_MFT0_ICU_IRQn); + NVIC_EnableIRQ(USB0_F_MFT0_ICU_IRQn); + NVIC_SetPriority(USB0_F_MFT0_ICU_IRQn, PDL_IRQ_LEVEL_MFT_ICU); + #endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(MFT0_2_ICU_IRQn); + NVIC_EnableIRQ(MFT0_2_ICU_IRQn); + NVIC_SetPriority(MFT0_2_ICU_IRQn, PDL_IRQ_LEVEL_MFT_ICU); +#else + if((volatile stc_mftn_icu_t*)(&MFT0_ICU) == pstcMftIcu) + { + NVIC_ClearPendingIRQ(MFT0_ICU_IRQn); + NVIC_EnableIRQ(MFT0_ICU_IRQn); + NVIC_SetPriority(MFT0_ICU_IRQn, PDL_IRQ_LEVEL_MFT0_ICU); + } + #if(defined(FM_MFT1)) + if((volatile stc_mftn_icu_t*)(&MFT1_ICU) == pstcMftIcu) + { + NVIC_ClearPendingIRQ(MFT1_ICU_IRQn); + NVIC_EnableIRQ(MFT1_ICU_IRQn); + NVIC_SetPriority(MFT1_ICU_IRQn, PDL_IRQ_LEVEL_MFT1_ICU); + } + #endif + #if(defined(FM_MFT2)) + if((volatile stc_mftn_icu_t*)(&MFT2_ICU) == pstcMftIcu) + { + NVIC_ClearPendingIRQ(MFT2_ICU_IRQn); + NVIC_EnableIRQ(MFT2_ICU_IRQn); + NVIC_SetPriority(MFT2_ICU_IRQn, PDL_IRQ_LEVEL_MFT2_ICU); + } + #endif +#endif + + return; +} + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ******************************************************************************/ +static void Mft_Icu_DeInitIrq( volatile stc_mftn_icu_t* pstcMftIcu ) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_1_A) + NVIC_ClearPendingIRQ(MFT0_ICU_IRQn); + NVIC_DisableIRQ(MFT0_ICU_IRQn); + NVIC_SetPriority(MFT0_ICU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #elif (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_2_A) + NVIC_ClearPendingIRQ(USB0_F_MFT0_ICU_IRQn); + NVIC_DisableIRQ(USB0_F_MFT0_ICU_IRQn); + NVIC_SetPriority(USB0_F_MFT0_ICU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(MFT0_2_ICU_IRQn); + NVIC_DisableIRQ(MFT0_2_ICU_IRQn); + NVIC_SetPriority(MFT0_2_ICU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + if((volatile stc_mftn_icu_t*)(&MFT0_ICU) == pstcMftIcu) + { + NVIC_ClearPendingIRQ(MFT0_ICU_IRQn); + NVIC_DisableIRQ(MFT0_ICU_IRQn); + NVIC_SetPriority(MFT0_ICU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #if(defined(FM_MFT1)) + if((volatile stc_mftn_icu_t*)(&MFT1_ICU) == pstcMftIcu) + { + NVIC_ClearPendingIRQ(MFT1_ICU_IRQn); + NVIC_DisableIRQ(MFT1_ICU_IRQn); + NVIC_SetPriority(MFT1_ICU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if(defined(FM_MFT2)) + if((volatile stc_mftn_icu_t*)(&MFT2_ICU) == pstcMftIcu) + { + NVIC_ClearPendingIRQ(MFT2_ICU_IRQn); + NVIC_DisableIRQ(MFT2_ICU_IRQn); + NVIC_SetPriority(MFT2_ICU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#endif + + return; +} + +#endif + +/** + ****************************************************************************** + ** \brief Select FRTx channel to connect to ICUx + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** \param [in] enFrt Frt channel number + ** \arg Frt0ToIcu, + ** Frt1ToIcu, + ** Frt2ToIcu, + ** IcuFrtToExt0, + ** IcuFrtToExt1 + ** \retval Ok FRT channel selected + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - NULL == pstcMftIcu + ** - u8Ch > MFT_ICU_CHx_MAX + ** - enFrt > IcuFrtToExt1 + ******************************************************************************/ +en_result_t Mft_Icu_SelFrt( volatile stc_mftn_icu_t* pstcMftIcu, uint8_t u8Ch, + en_mft_icu_frt_t enFrt) +{ + volatile stc_mft_icu_icfs10_field_t* stcICFS10; + volatile stc_mft_icu_icfs32_field_t* stcICFS32; + + // Check for NULL pointer and channel parameter + boolean_t bAvoidSideEffects = ((NULL == pstcMftIcu) ? 1u : 0u); + bAvoidSideEffects |= ((u8Ch > MFT_ICU_CHx_MAX) ? 1u : 0u); + if (TRUE == bAvoidSideEffects) + { + return ErrorInvalidParameter ; + } + + // Get actual address of register list of current channel + stcICFS10 = (volatile stc_mft_icu_icfs10_field_t*)(&(pstcMftIcu->ICFS10)); + stcICFS32 = (volatile stc_mft_icu_icfs32_field_t*)(&(pstcMftIcu->ICFS32)); + + // FRT channel select: FRTx -> ICUx + if(enFrt > IcuFrtToExt1) + { + return ErrorInvalidParameter; + } + // configure the Frt channel to connect to Icu + switch(u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + stcICFS10->FSI0 = (uint8_t)enFrt; + break; + // ICU channel 1 + case MFT_ICU_CH1: + stcICFS10->FSI1 = (uint8_t)enFrt; + break; + // ICU channel 2 + case MFT_ICU_CH2: + stcICFS32->FSI2 = (uint8_t)enFrt; + break; + // ICU channel 3 + case MFT_ICU_CH3: + stcICFS32->FSI3 = (uint8_t)enFrt; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure ICU module detection mode(different edge) + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** \param [in] enMode Icu detect mode + ** \arg IcuDisable, + ** IcuRisingDetect, + ** IcuFallingDetect, + ** IcuBothDetect + ** \retval Ok ICU detection mode selected + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - NULL == pstcMftIcu + ** - u8Ch > MFT_ICU_CHx_MAX + ** - enMode > IcuBothDetect + ******************************************************************************/ +en_result_t Mft_Icu_ConfigDetectMode( volatile stc_mftn_icu_t* pstcMftIcu, uint8_t u8Ch, + en_mft_icu_mode_t enMode) +{ + // Check for NULL pointer and channel parameter + boolean_t bAvoidSideEffects = ((NULL == pstcMftIcu) ? 1u : 0u); + bAvoidSideEffects |= ((u8Ch > MFT_ICU_CHx_MAX) ? 1u : 0u); + if (bAvoidSideEffects) + { + return ErrorInvalidParameter ; + } + + // Check configuration of Mft Icu mode + if(enMode > IcuBothDetect) + { + return ErrorInvalidParameter; + } + // Configure Icu detection mode + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + pstcMftIcu->ICSA10_f.EG0 = (uint8_t)enMode; + break; + // ICU channel 1 + case MFT_ICU_CH1: + pstcMftIcu->ICSA10_f.EG1 = (uint8_t)enMode; + break; + // ICU channel 2 + case MFT_ICU_CH2: + pstcMftIcu->ICSA32_f.EG2 = (uint8_t)enMode; + break; + // ICU channel 3 + case MFT_ICU_CH3: + pstcMftIcu->ICSA32_f.EG3 = (uint8_t)enMode; + break; + // ICU channel number error + default: + return ErrorInvalidParameter; + } + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_MFT0_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_ICU == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable Mft Icu interrupt + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** \param [in] pfnIrqCb register callback function + ** \arg user interrupt application function + ** \param [in] bTouchNvic Touch NVIC or not + ** \retval Ok ICU interrupt are enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - NULL == pstcMftIcu + ** - u8Ch > MFT_ICU_CHx_MAX + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Mft_Icu_EnableIrq( volatile stc_mftn_icu_t*pstcMftIcu, uint8_t u8Ch, + func_ptr_t pfnIrqCb, boolean_t bTouchNvic) +{ + // Pointer to internal data + stc_mft_icu_intern_data_t* pstcMftIcuInternData ; + volatile stc_mftn_icu_t* pstcOrgMftIcu = pstcMftIcu; + + // Check for NULL pointer and channel parameter + boolean_t bAvoidSideEffects = ((NULL == pstcMftIcu) ? 1u : 0u); + bAvoidSideEffects |= ((u8Ch > MFT_ICU_CHx_MAX) ? 1u : 0u); + bAvoidSideEffects |= ((NULL == pfnIrqCb) ? 1u : 0u); + if (bAvoidSideEffects) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure + pstcMftIcuInternData = MftIcuGetInternDataPtr( pstcOrgMftIcu ); + + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + pstcMftIcuInternData->pfnIcu0IrqCb = pfnIrqCb; + pstcMftIcu->ICSA10_f.ICE0 = 1u; + break; + // ICU channel 1 + case MFT_ICU_CH1: + pstcMftIcuInternData->pfnIcu1IrqCb = pfnIrqCb; + pstcMftIcu->ICSA10_f.ICE1 = 1u; + break; + // ICU channel 2 + case MFT_ICU_CH2: + pstcMftIcuInternData->pfnIcu2IrqCb = pfnIrqCb; + pstcMftIcu->ICSA32_f.ICE2 = 1u; + break; + // ICU channel 3 + case MFT_ICU_CH3: + pstcMftIcuInternData->pfnIcu3IrqCb = pfnIrqCb; + pstcMftIcu->ICSA32_f.ICE3 = 1u; + break; + // ICU channel number error + default: + return ErrorInvalidParameter; + } + + if(TRUE == bTouchNvic) + { + // initialize interrupt + Mft_Icu_InitIrq(pstcOrgMftIcu); + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable Mft Icu interrupt and release callback function + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok ICU interrupt are disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - NULL == pstcMftIcu + ** - u8Ch > MFT_ICU_CHx_MAX + ** - Other invalid configuration + ******************************************************************************/ + +en_result_t Mft_Icu_DisableIrq( volatile stc_mftn_icu_t*pstcMftIcu, + uint8_t u8Ch, + boolean_t bTouchNvic) +{ + // Pointer to internal data + stc_mft_icu_intern_data_t* pstcMftIcuInternData ; + volatile stc_mftn_icu_t* pstcOrgMftIcu = pstcMftIcu; + + // Check for NULL pointer and channel parameter + boolean_t bAvoidSideEffects = ((NULL == pstcMftIcu) ? 1u : 0u); + bAvoidSideEffects |= ((u8Ch > MFT_ICU_CHx_MAX) ? 1u : 0u); + if (bAvoidSideEffects) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure + pstcMftIcuInternData = MftIcuGetInternDataPtr( pstcOrgMftIcu ); + // Dis-register callback function and disable interrupt operation + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + pstcMftIcuInternData->pfnIcu0IrqCb = NULL; + pstcMftIcu->ICSA10_f.ICE0 = 0u; + break; + // ICU channel 1 + case MFT_ICU_CH1: + pstcMftIcuInternData->pfnIcu1IrqCb = NULL; + pstcMftIcu->ICSA10_f.ICE1 = 0u; + break; + // ICU channel 2 + case MFT_ICU_CH2: + pstcMftIcuInternData->pfnIcu2IrqCb = NULL; + pstcMftIcu->ICSA32_f.ICE2 = 0u; + break; + // ICU channel 3 + case MFT_ICU_CH3: + pstcMftIcuInternData->pfnIcu3IrqCb = NULL; + pstcMftIcu->ICSA32_f.ICE3 = 0u; + break; + // ICU channel number error + default: + return ErrorInvalidParameter; + } + + if(TRUE == bTouchNvic) + { + Mft_Icu_DeInitIrq(pstcOrgMftIcu); + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** + ** \retval FALSE ICU active edge is not detected + ** \retval TRUE ICU active edge is detected + ******************************************************************************/ + +en_irq_flag_t Mft_Icu_GetIrqFlag(volatile stc_mftn_icu_t *pstcMftIcu, uint8_t u8Ch) +{ + en_irq_flag_t enIrqFlagBuf = PdlClr; + + // Read interrupt flag + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + (pstcMftIcu->ICSA10_f.ICP0 == 1u) ? (enIrqFlagBuf = PdlSet) : (enIrqFlagBuf = PdlClr); + break; + // ICU channel 1 + case MFT_ICU_CH1: + (pstcMftIcu->ICSA10_f.ICP1 == 1u) ? (enIrqFlagBuf = PdlSet) : (enIrqFlagBuf = PdlClr); + break; + // ICU channel 2 + case MFT_ICU_CH2: + (pstcMftIcu->ICSA32_f.ICP2 == 1u) ? (enIrqFlagBuf = PdlSet) : (enIrqFlagBuf = PdlClr); + break; + // ICU channel 3 + case MFT_ICU_CH3: + (pstcMftIcu->ICSA32_f.ICP3 == 1u) ? (enIrqFlagBuf = PdlSet) : (enIrqFlagBuf = PdlClr); + break; + // ICU channel number error + default: + break; + } + // return interrupt flag + return enIrqFlagBuf; +} +/** + ****************************************************************************** + ** \brief Clear interrupt flag + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** + ** \retval Ok Interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - NULL == pstcMftIcu + ** - u8Ch > MFT_ICU_CHx_MAX + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Mft_Icu_ClrIrqFlag( volatile stc_mftn_icu_t *pstcMftIcu, uint8_t u8Ch) +{ + // Check for NULL pointer and channel parameter + boolean_t bAvoidSideEffects = ((NULL == pstcMftIcu) ? 1u : 0u); + bAvoidSideEffects |= ((u8Ch > MFT_ICU_CHx_MAX) ? 1u : 0u); + if (bAvoidSideEffects) + { + return ErrorInvalidParameter ; + } + + // Clear interrupt flag + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + pstcMftIcu->ICSA10_f.ICP0 = 0u; + break; + // ICU channel 1 + case MFT_ICU_CH1: + pstcMftIcu->ICSA10_f.ICP1 = 0u; + break; + // ICU channel 2 + case MFT_ICU_CH2: + pstcMftIcu->ICSA32_f.ICP2 = 0u; + break; + // ICU channel 3 + case MFT_ICU_CH3: + pstcMftIcu->ICSA32_f.ICP3 = 0u; + break; + // ICU channel number error + default: + return ErrorInvalidParameter; + } + + return Ok; +} +/** + ****************************************************************************** + ** \brief Get the latest captured edge type + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** + ** \return Detected edge type + ******************************************************************************/ +en_mft_icu_edge_t Mft_Icu_GetLastEdge( volatile stc_mftn_icu_t *pstcMftIcu, uint8_t u8Ch) +{ + en_mft_icu_edge_t enEdgeTypeBuf = IcuFallingEdge; + + // Read last Edge type + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + (1u == pstcMftIcu->ICSB10_f.IEI0 ) ? (enEdgeTypeBuf = IcuRisingEdge) : (enEdgeTypeBuf = IcuFallingEdge); + break; + // ICU channel 1 + case MFT_ICU_CH1: + (1u == pstcMftIcu->ICSB10_f.IEI1) ? (enEdgeTypeBuf = IcuRisingEdge) : (enEdgeTypeBuf = IcuFallingEdge); + break; + // ICU channel 2 + case MFT_ICU_CH2: + (1u == pstcMftIcu->ICSB32_f.IEI2) ? (enEdgeTypeBuf = IcuRisingEdge) : (enEdgeTypeBuf = IcuFallingEdge); + break; + // ICU channel 3 + case MFT_ICU_CH3: + (1u == pstcMftIcu->ICSB32_f.IEI3) ? (enEdgeTypeBuf = IcuRisingEdge) : (enEdgeTypeBuf = IcuFallingEdge); + break; + // ICU channel number error + default: + break; + } + // return last edge type + return enEdgeTypeBuf; +} +/** + ****************************************************************************** + ** \brief Readout captured data value + ** + ** \param [in] pstcMftIcu Pointer to ICU instance + ** \param [in] u8Ch Mft Icu channel + ** \arg MFT_ICU_CH0 ~ MFT_ICU_CH3 + ** + ** \return captured data value + ******************************************************************************/ +uint16_t Mft_Icu_GetCaptureData(volatile stc_mftn_icu_t *pstcMftIcu, uint8_t u8Ch) +{ + uint16_t u16CaptureVal = 0u; + + // Read captured value + switch (u8Ch) + { + // ICU channel 0 + case MFT_ICU_CH0: + u16CaptureVal = (uint16_t)(pstcMftIcu->ICCP0); + break; + // ICU channel 1 + case MFT_ICU_CH1: + u16CaptureVal = (uint16_t)(pstcMftIcu->ICCP1); + break; + // ICU channel 2 + case MFT_ICU_CH2: + u16CaptureVal = (uint16_t)(pstcMftIcu->ICCP2); + break; + // ICU channel 3 + case MFT_ICU_CH3: + u16CaptureVal = (uint16_t)(pstcMftIcu->ICCP3); + break; + // ICU channel number error + default: + break; + } + + return (uint16_t)u16CaptureVal; +} + +#endif // #if (defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE)) diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_icu.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_icu.h new file mode 100644 index 0000000000..b6af7886b1 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_icu.h @@ -0,0 +1,272 @@ +/******************************************************************************* +* \file mft_icu.h +* +* \version 1.20 +* +* \brief Headerfile for ICU functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MFT_ICU_H__ +#define __MFT_ICU_H__ + +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE)) + +/** +* \defgroup GroupMFT_ICU Input Capture Unit (MFT ICU) +* \{ +* \defgroup GroupMFT_ICU_Macros Macros +* \defgroup GroupMFT_ICU_Functions Functions +* \defgroup GroupMFT_ICU_GlobalVariables Global Variables +* \defgroup GroupMFT_ICU_DataStructures Data Structures +* \defgroup GroupMFT_ICU_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupMFT_ICU +* \{ +* The Input Capture Unit (ICU) is part of the Multi-function Timer (MFT). +* The MFT is a collection of peripherals used primarily for motor control. +* There may be up to three MFTs supported on a particular FM microcontroller. +* One MFT can control a 3-phase motor. A microcontroller that supports multiple +* MFTs can control multiple 3-phase motors.
+* The peripherals in the MFT are:
+* - Free-run Timer (FRT) +* - Output Compare Unit (OCU) +* - Waveform Generator (WFG) +* - Input Capture Unit (ICU) +* - ADC Start Compare (ADCMP)
+* Each MFT has an ICU. An ICU is a function block that captures an FRT count value +* and generates an interrupt when a valid edge is detected at an external input pin signal. +* This enables external control of the MFT.
+* An ICU has four input channels (0-3), which correspond to signal pins. For each channel you can:
+* - Select which FRT to use as a timer +* - Enable or disable any channel (and provide the interrupt handler for that channel) +* - Specify what edge is valid (rising, falling, or both) +* - Capture the value of the counter at the time of the interrupt
+* There are five possible sources for the FRT used. Three inputs are from the three FRT instances of the corresponding +* MFT module. The other two FRT inputs are routed from the other possible MFT instances.
+* \section SectionMFT_ICU_ConfigurationConsideration Configuration Consideration +* To set up an ICU, first you should configure an FRT. See the description in the MFT FRT.
+* The ICU does not have a configuration structure. You make API function calls to specify the ICU behavior. +* Make the calls in this order for each of the four channels you use.
+* * - Mft_Icu_SelFrt() to connect an FRT to the ICU. +* - Mft_Icu_EnableIrq() to enable the interrupt. This function also sets the callback function for the channel. +* - Mft_Icu_ConfigDetectMode() to specify the valid edge and start ICU operation at the same time. +* The interrupt occurs when a valid edge is detected. The interrupt flag will be cleared and control passes +* to the interrupt callback function. In the callback function, you can get the FRT counter value with +* Mft_Icu_GetCaptureData().
+* If you handle interrupts by polling, you can get and clear the interrupt flag for each channel.
+* If both rising and falling edges are valid, you can call Mft_Icu_GetLastEdge() to get the edge information.
+* When stopping the ICU, use Mft_Icu_ConfigDetectMode() to disable the ICU and Mft_Icu_DisableIrq() to disable ICU interrupt. +* +* \section SectionMFT_ICU_MoreInfo More Information +* For more information on the MFT FRT peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupMFT_ICU_Macros +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define stc_mftn_icu_t FM_MFT_ICU_TypeDef +#define MFT0_ICU (*((volatile stc_mftn_icu_t *) FM_MFT0_ICU_BASE)) +#define MFT1_ICU (*((volatile stc_mftn_icu_t *) FM_MFT1_ICU_BASE)) +#define MFT2_ICU (*((volatile stc_mftn_icu_t *) FM_MFT2_ICU_BASE)) + +#define MFT_ICU_CH0 0u +#define MFT_ICU_CH1 1u +#define MFT_ICU_CH2 2u +#define MFT_ICU_CH3 3u + +#define MFT_ICU_CHx_MAX 3u + +#define MFT_ICU_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFT0_ICU == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFT1_ICU == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_MFT2_ICU == PDL_ON) + +/** \} GroupMFT_ICU_Macros */ + +/** +* \addtogroup GroupMFT_ICU_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each ICU instance + ******************************************************************************/ +typedef enum en_icu_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_ICU == PDL_ON) + IcuInstanceIndexIcu0, ///< Instance index of ICU0 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_ICU == PDL_ON) + IcuInstanceIndexIcu1, ///< Instance index of ICU1 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_ICU == PDL_ON) + IcuInstanceIndexIcu2, ///< Instance index of ICU2 +#endif +} en_icu_instance_index_t; + +/** + ****************************************************************************** + ** \brief Frt channel + ** + ** To select FRT channel to connect to ICU + ******************************************************************************/ +typedef enum en_mft_icu_frt +{ + Frt0ToIcu = 0u, ///< connect Frt channel 0 to Icu + Frt1ToIcu = 1u, ///< connect Frt channel 1 to Icu + Frt2ToIcu = 2u, ///< connect Frt channel 2 to Icu + IcuFrtToExt0 = 3u, ///< connect extern Frt channel 0 to Icu + IcuFrtToExt1 = 4u, ///< connect extern Frt channel 1 to Icu + +}en_mft_icu_frt_t; + +/** + ****************************************************************************** + ** \brief Icu mode + ** + ** To select Icu edge detection mode + ******************************************************************************/ +typedef enum en_mft_icu_mode +{ + IcuDisable = 0u, ///< disable Icu edge detection + IcuRisingDetect = 1u, ///< detect Icu rising edge + IcuFallingDetect = 2u, ///< detect Icu falling edge + IcuBothDetect = 3u, ///< detect Icu rising/falling edge + +}en_mft_icu_mode_t; + +/** + ****************************************************************************** + ** \brief Icu edge + ** + ** To select Icu edge + ******************************************************************************/ +typedef enum en_icu_edge +{ + IcuFallingEdge = 0u, ///< select Icu falling edge + IcuRisingEdge = 1u, ///< select Icu rising edge + +}en_mft_icu_edge_t; + +/** \} GroupMFT_ICU_Types */ + +/** +* \addtogroup GroupMFT_ICU_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Icu instance internal data, + ** storing internal information for each enabled Icu instance + ******************************************************************************/ +typedef struct stc_mft_icu_intern_data +{ + func_ptr_t pfnIcu0IrqCb; ///< Callback function pointer of ICU0 interrupt + func_ptr_t pfnIcu1IrqCb; ///< Callback function pointer of ICU1 interrupt + func_ptr_t pfnIcu2IrqCb; ///< Callback function pointer of ICU2 interrupt + func_ptr_t pfnIcu3IrqCb; ///< Callback function pointer of ICU3 interrupt + +}stc_mft_icu_intern_data_t; +/** + ****************************************************************************** + ** \brief Mft_icu instance data type + ******************************************************************************/ +typedef struct stc_mft_icu_instance_data +{ + volatile stc_mftn_icu_t* pstcInstance; ///< pointer to registers of an instance + stc_mft_icu_intern_data_t stcInternData;///< module internal data of instance + +}stc_mft_icu_instance_data_t; +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** \} GroupMFT_ICU_DataStructures */ + +/** +* \addtogroup GroupMFT_ICU_GlobalVariables +* \{ +*/ + +/** Look-up table for all enabled MFT_ICU instances and their internal data */ +extern stc_mft_icu_instance_data_t m_astcMftIcuInstanceDataLut[MFT_ICU_INSTANCE_COUNT]; + +/** \} GroupMFT_ICU_GlobalVariables */ + +/** +* \addtogroup GroupMFT_ICU_Functions +* \{ +*/ + +/** C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/** Clock */ +en_result_t Mft_Icu_SelFrt(volatile stc_mftn_icu_t*pstcMft, uint8_t u8Ch, en_mft_icu_frt_t enFrt); +/** mode set */ +en_result_t Mft_Icu_ConfigDetectMode(volatile stc_mftn_icu_t*pstcMft, uint8_t u8Ch, en_mft_icu_mode_t enMode); +/** Interrupt */ +#if (PDL_INTERRUPT_ENABLE_MFT0_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_ICU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_ICU == PDL_ON) +en_result_t Mft_Icu_EnableIrq(volatile stc_mftn_icu_t*pstcMft, + uint8_t u8Ch, + func_ptr_t pfnIrqCb, + boolean_t bTouchNvic); +en_result_t Mft_Icu_DisableIrq(volatile stc_mftn_icu_t*pstcMft, + uint8_t u8Ch, + boolean_t bTouchNvic); +#endif +en_irq_flag_t Mft_Icu_GetIrqFlag(volatile stc_mftn_icu_t*pstcMft, uint8_t u8Ch); +en_result_t Mft_Icu_ClrIrqFlag(volatile stc_mftn_icu_t*pstcMft, uint8_t u8Ch); +/** Status read/write */ +en_mft_icu_edge_t Mft_Icu_GetLastEdge(volatile stc_mftn_icu_t*pstcMft, uint8_t u8Ch); +/** Count read */ +uint16_t Mft_Icu_GetCaptureData(volatile stc_mftn_icu_t*pstcMft, uint8_t u8Ch); +/** IRQ handler */ +void Mft_Icu_IrqHandler(volatile stc_mftn_icu_t*pstcMft, stc_mft_icu_intern_data_t* pstcMftIcuInternData) ; + +#ifdef __cplusplus +} +#endif + +/** \} GroupMFT_ICU_Functions */ +/** \} GroupMFT_ICU */ + +#endif + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_ocu.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_ocu.c new file mode 100644 index 0000000000..3f1c03dfac --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_ocu.c @@ -0,0 +1,1255 @@ +/******************************************************************************* +* \file mft_ocu.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the +* MFT_OCU driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mft/mft_ocu.h" + +#if (defined(PDL_PERIPHERAL_MFT_OCU_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM3_CORE) +#define MFT_FRT_REG_OFFSET (0x10u) +#elif (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +#define MFT_FRT_REG_OFFSET (0x0Cu) +#endif +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled FRT of MFT instances and their internal data +stc_mft_ocu_instance_data_t m_astcMftOcuInstanceDataLut[OCU_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_OCU == PDL_ON) + { + &MFT0_OCU, // pstcInstance + {0u, 0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_OCU == PDL_ON) + { + &MFT1_OCU, // pstcInstance + {0u, 0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_OCU == PDL_ON) + { + &MFT2_OCU, // pstcInstance + {0u, 0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +/** + ***************************************************************************** + ** \brief Return the internal data for a certain OCU instance. + ** + ** \param pstcOcu Pointer to OCU instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled + ** (or not known) + ** + *****************************************************************************/ +static stc_mft_ocu_intern_data_t* MftGetInternDataPtr(volatile stc_mftn_ocu_t* pstcOcu) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < OCU_INSTANCE_COUNT; u32Instance++) + { + if (pstcOcu == m_astcMftOcuInstanceDataLut[u32Instance].pstcInstance) + { + return &m_astcMftOcuInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) +/*! + ****************************************************************************** + ** \brief OCU module interrupt handler + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] pstcMftOcuInternData callback function of OCU + ***************************************************************************** +*/ +void Mft_Ocu_IrqHandler( volatile stc_mftn_ocu_t* pstcOcu, + stc_mft_ocu_intern_data_t* pstcMftOcuInternData) +{ + func_ptr_t funCallBack; + uint32_t* ptemp; + uint8_t Ch; + + //lookup the handler + for(Ch=0u; ChpfnOcu0IrqCallback); + funCallBack = (func_ptr_t)(*(ptemp + Ch)); + + if(NULL != funCallBack) + { + funCallBack(); + } + } + } +} + +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl.h + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** + ** \retval Ok Successful initialization + ** + ******************************************************************************/ +static void MftOcuInitNvic( volatile stc_mftn_ocu_t* pstcOcu ) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(MFT0_OCU_IRQn); + NVIC_EnableIRQ(MFT0_OCU_IRQn); + NVIC_SetPriority(MFT0_OCU_IRQn, PDL_IRQ_LEVEL_MFT_OCU); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(MFT0_2_OCU_IRQn); + NVIC_EnableIRQ(MFT0_2_OCU_IRQn); + NVIC_SetPriority(MFT0_2_OCU_IRQn, PDL_IRQ_LEVEL_MFT_OCU); +#else +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) + if((volatile stc_mftn_ocu_t*)(&MFT0_OCU) == pstcOcu) + { + NVIC_ClearPendingIRQ(MFT0_OCU_IRQn); + NVIC_EnableIRQ(MFT0_OCU_IRQn); + NVIC_SetPriority(MFT0_OCU_IRQn, PDL_IRQ_LEVEL_MFT0_OCU); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) + if((volatile stc_mftn_ocu_t*)(&MFT1_OCU) == pstcOcu) + { + NVIC_ClearPendingIRQ(MFT1_OCU_IRQn); + NVIC_EnableIRQ(MFT1_OCU_IRQn); + NVIC_SetPriority(MFT1_OCU_IRQn, PDL_IRQ_LEVEL_MFT1_OCU); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + if((volatile stc_mftn_ocu_t*)(&MFT2_OCU) == pstcOcu) + { + NVIC_ClearPendingIRQ(MFT2_OCU_IRQn); + NVIC_EnableIRQ(MFT2_OCU_IRQn); + NVIC_SetPriority(MFT2_OCU_IRQn, PDL_IRQ_LEVEL_MFT2_OCU); + } +#endif + +#endif + + return ; +} + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** + ** \retval Ok Successful initialization + ** + ******************************************************************************/ +static void MftOcuDeInitNvic( volatile stc_mftn_ocu_t* pstcOcu ) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(MFT0_OCU_IRQn); + NVIC_DisableIRQ(MFT0_OCU_IRQn); + NVIC_SetPriority(MFT0_OCU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(MFT0_2_OCU_IRQn); + NVIC_DisableIRQ(MFT0_2_OCU_IRQn); + NVIC_SetPriority(MFT0_2_OCU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) + if((volatile stc_mftn_ocu_t*)(&MFT0_OCU) == pstcOcu) + { + NVIC_ClearPendingIRQ(MFT0_OCU_IRQn); + NVIC_DisableIRQ(MFT0_OCU_IRQn); + NVIC_SetPriority(MFT0_OCU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) + if((volatile stc_mftn_ocu_t*)(&MFT1_OCU) == pstcOcu) + { + NVIC_ClearPendingIRQ(MFT1_OCU_IRQn); + NVIC_DisableIRQ(MFT1_OCU_IRQn); + NVIC_SetPriority(MFT1_OCU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif +#if (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + if((volatile stc_mftn_ocu_t*)(&MFT2_OCU) == pstcOcu) + { + NVIC_ClearPendingIRQ(MFT2_OCU_IRQn); + NVIC_DisableIRQ(MFT2_OCU_IRQn); + NVIC_SetPriority(MFT2_OCU_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#endif + +#endif + + return; +} + +#endif + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Init OCU module + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** \param [in] pstcOcuConfig configure of OCU + ** \arg structure of OCU cofnigure + ** + ** \retval Ok OCU module initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - pstcOcuConfig == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Ocu_Init( volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, const stc_mft_ocu_config_t* pstcOcuConfig) +{ + stc_mft_ocu_intern_data_t* pstcOcuInternData; + volatile stc_mft_ocu_ocfs10_field_t* pstcOCFS; +#if (PDL_MCU_CORE == PDL_FM3_CORE) || \ + (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; +#endif + volatile stc_mft_ocu_ocsb10_field_t* pstcOCSB; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_mft_ocu_ocsd10_field_t* pstcOCSD; +#endif + // Check for NULL pointer and configuration parameter + if ( (NULL == pstcOcu) || + (u8Ch >= MFT_OCU_MAXCH) ) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcOcuInternData = MftGetInternDataPtr( pstcOcu ) ; + // ... and check for NULL + if ( NULL == pstcOcuInternData ) + { + return ErrorInvalidParameter; + } + + //Get pointer of current channel OCU register address +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + pstcOCFS = (volatile stc_mft_ocu_ocfs10_field_t*)((volatile uint8_t*)&pstcOcu->OCFS10 + u8Ch/2u); +#else + if(u8Ch < 4) + { + pstcOCFS = (volatile stc_mft_ocu_ocfs10_field_t*)((volatile uint8_t*)&pstcOcu->OCFS10 + u8Ch/2u); + } + else + { + pstcOCFS = (volatile stc_mft_ocu_ocfs10_field_t*)((volatile uint8_t*)&pstcOcu->OCFS10 + 4u); + } +#endif +#if (PDL_MCU_CORE == PDL_FM3_CORE) || \ + (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + (u8Ch/2u)*4u); +#endif + pstcOCSB = (volatile stc_mft_ocu_ocsb10_field_t*)((volatile uint8_t*)&pstcOcu->OCSB10 + (u8Ch/2u)*4u); +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD = (volatile stc_mft_ocu_ocsd10_field_t*)((volatile uint8_t*)&pstcOcu->OCSD10 + (u8Ch/2u)*4u); +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + //set OCSB register, config ocu's operation + pstcOCSB->FM4 = ((TRUE == pstcOcuConfig->bFm4) ? 1u : 0u); +#endif + + // Set OCSE and OCCP buffer mode + if(0u == (u8Ch % 2u)) //channel 0, 2, 4 + { + // OCSE buffer + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + switch (pstcOcuConfig->enOcseBufMode) + { + case OcseBufDisable: + pstcOCSD->OCSE0BUFE = 0u; + break; + case OcseBufTrsfByFrtZero: + pstcOCSD->OCSE0BUFE = 1u; + break; + case OcseBufTrsfByFrtPeak: + pstcOCSD->OCSE0BUFE = 2u; + break; + case OcseBufTrsfByFrtZeroPeak: + pstcOCSD->OCSE0BUFE = 3u; + break; + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + case OcseBufTrsfByFrtZeroMszcZero: + pstcOCSD->OPBM0 = 1u; + pstcOCSD->OCSE0BUFE = 1u; + break; + case OcseBufTrsfByFrtPeakMspcZero: + pstcOCSD->OPBM0 = 1u; + pstcOCSD->OCSE0BUFE = 2u; + break; + case OcseBufTrsfByFrtZeroMszcZeroOrFrtPeakMspcZero: + pstcOCSD->OPBM0 = 1u; + pstcOCSD->OCSE0BUFE = 3u; + break; + #endif + default: + return ErrorInvalidParameter ; + } + #endif + + // OCCP buffer + switch (pstcOcuConfig->enOccpBufMode) + { + case OccpBufDisable: + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD->OCCP0BUFE = 0u; + #else + pstcOCSA->BDIS0 = 1u; + #endif + break; + case OccpBufTrsfByFrtZero: + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD->OCCP0BUFE = 1u; + #else + pstcOCSB->BTS0 = 0u; + pstcOCSA->BDIS0 = 0u; + #endif + break; + case OccpBufTrsfByFrtPeak: + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD->OCCP0BUFE = 2u; + #else + pstcOCSB->BTS0 = 1u; + pstcOCSA->BDIS0 = 0u; + #endif + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case OccpBufTrsfByFrtZeroPeak: + pstcOCSD->OCCP0BUFE = 3u; + break; + #endif + #if(PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + case OccpBufTrsfByFrtZeroMszcZero: + pstcOCSD->OEBM0 = 1u; + pstcOCSD->OCCP0BUFE = 1u; + break; + case OccpBufTrsfByFrtPeakMspcZero: + pstcOCSD->OEBM0 = 1u; + pstcOCSD->OCCP0BUFE = 2u; + break; + case OccpBufTrsfByFrtZeroMszcZeroOrFrtPeakMspcZero: + pstcOCSD->OEBM0 = 1u; + pstcOCSD->OCCP0BUFE = 3u; + break; + #endif + #endif + default: + return ErrorInvalidParameter ; + } + + // set FRT to be connected + switch (pstcOcuConfig->enFrtConnect) + { + case Frt0ToOcu: + pstcOCFS->FSO0 = 0u; + break; + case Frt1ToOcu: + pstcOCFS->FSO0 = 1u; + break; + case Frt2ToOcu: + pstcOCFS->FSO0 = 2u; + break; + default: + return ErrorInvalidParameter ; + } + + // Set initial RT level + pstcOCSB->OTD0 = ((pstcOcuConfig->enPinState == RtHighLevel) ? 1u : 0u); + } + else//channel 1, 3, 5 + { + // OCSE buffer + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + switch (pstcOcuConfig->enOcseBufMode) + { + case OcseBufDisable: + pstcOCSD->OCSE1BUFE = 0u; + break; + case OcseBufTrsfByFrtZero: + pstcOCSD->OCSE1BUFE = 1u; + break; + case OcseBufTrsfByFrtPeak: + pstcOCSD->OCSE1BUFE = 2u; + break; + case OcseBufTrsfByFrtZeroPeak: + pstcOCSD->OCSE1BUFE = 3u; + break; + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + case OcseBufTrsfByFrtZeroMszcZero: + pstcOCSD->OPBM1 = 1u; + pstcOCSD->OCSE1BUFE = 1u; + break; + case OcseBufTrsfByFrtPeakMspcZero: + pstcOCSD->OPBM1 = 1u; + pstcOCSD->OCSE1BUFE = 2u; + break; + case OcseBufTrsfByFrtZeroMszcZeroOrFrtPeakMspcZero: + pstcOCSD->OPBM1 = 1u; + pstcOCSD->OCSE1BUFE = 3u; + break; + #endif + default: + return ErrorInvalidParameter ; + } + #endif + + // OCCP buffer + switch (pstcOcuConfig->enOccpBufMode) + { + case OccpBufDisable: + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD->OCCP1BUFE = 0u; + #else + pstcOCSA->BDIS1 = 1u; + #endif + break; + case OccpBufTrsfByFrtZero: + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD->OCCP1BUFE = 1u; + #else + pstcOCSB->BTS1 = 0u; + pstcOCSA->BDIS1 = 0u; + #endif + break; + case OccpBufTrsfByFrtPeak: + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcOCSD->OCCP1BUFE = 2u; + #else + pstcOCSB->BTS1 = 1u; + pstcOCSA->BDIS1 = 0u; + #endif + break; + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case OccpBufTrsfByFrtZeroPeak: + pstcOCSD->OCCP1BUFE = 3u; + break; + #endif + #if(PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + case OccpBufTrsfByFrtZeroMszcZero: + pstcOCSD->OEBM1 = 1u; + pstcOCSD->OCCP1BUFE = 1u; + break; + case OccpBufTrsfByFrtPeakMspcZero: + pstcOCSD->OEBM1 = 1u; + pstcOCSD->OCCP1BUFE = 2u; + break; + case OccpBufTrsfByFrtZeroMszcZeroOrFrtPeakMspcZero: + pstcOCSD->OEBM1 = 1u; + pstcOCSD->OCCP1BUFE = 3u; + break; + #endif + #endif + default: + return ErrorInvalidParameter ; + } + + // set FRT to be connected + switch (pstcOcuConfig->enFrtConnect) + { + case Frt0ToOcu: + pstcOCFS->FSO1 = 0u; + break; + case Frt1ToOcu: + pstcOCFS->FSO1 = 1u; + break; + case Frt2ToOcu: + pstcOCFS->FSO1 = 2u; + break; + default: + return ErrorInvalidParameter ; + } + + // Set initial RT level + pstcOCSB->OTD1 = ((pstcOcuConfig->enPinState == RtHighLevel) ? 1u : 0u); + } + +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + // set interrupt enable + if(TRUE == pstcOcuConfig->bIrqEnable) + { + if(0u == (u8Ch%2u)) //channel 0,2,4 + { + pstcOCSA->IOE0 = 1u; + } + else //channel 1,3,5 + { + pstcOCSA->IOE1 = 1u; + } + } + + // set interrupt callback funciton + switch (u8Ch) + { + case 0u: + pstcOcuInternData->pfnOcu0IrqCallback = pstcOcuConfig->pfnIrqCallback; + break; + case 1u: + pstcOcuInternData->pfnOcu1IrqCallback = pstcOcuConfig->pfnIrqCallback; + break; + case 2u: + pstcOcuInternData->pfnOcu2IrqCallback = pstcOcuConfig->pfnIrqCallback; + break; + case 3u: + pstcOcuInternData->pfnOcu3IrqCallback = pstcOcuConfig->pfnIrqCallback; + break; + case 4u: + pstcOcuInternData->pfnOcu4IrqCallback = pstcOcuConfig->pfnIrqCallback; + break; + case 5u: + pstcOcuInternData->pfnOcu5IrqCallback = pstcOcuConfig->pfnIrqCallback; + break; + default: + break; + } + + // set NVIC + if(TRUE == pstcOcuConfig->bTouchNvic) + { + MftOcuInitNvic(pstcOcu); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize OCU module + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** \param [in] bTouchNvic + ** \arg FALSE Don't disable NVIC + ** \arg TRUE Disable NVIC + ** + ** \retval Ok OCU module initialized + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Ocu_DeInit( volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, + boolean_t bTouchNvic) +{ + volatile uint8_t* pu8OCSA; + volatile uint8_t* pu8OCSB; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile uint16_t* pu16OCSD; +#endif + volatile uint8_t* pu8OCFS; + + pu8OCSA = (volatile uint8_t*)((uint8_t*)&pstcOcu->OCSA10 + (u8Ch/2u)*4u); + pu8OCSB = (volatile uint8_t*)((uint8_t*)&pstcOcu->OCSB10 + (u8Ch/2u)*4u); +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pu16OCSD = (volatile uint16_t*)((uint8_t*)&pstcOcu->OCSD10 + (u8Ch/2u)*4u); +#endif + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + pu8OCFS = (volatile uint8_t*)((volatile uint8_t*)&pstcOcu->OCFS10 + u8Ch/2u); +#else + if (u8Ch < 4) + { + pu8OCFS = (volatile uint8_t*)((volatile uint8_t*)&pstcOcu->OCFS10 + u8Ch/2u); + } + else + { + pu8OCFS = (volatile uint8_t*)((volatile uint8_t*)&pstcOcu->OCFS10 + 4u); + } +#endif + + *pu8OCSA = 0u; + *pu8OCSB = 0u; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + *pu16OCSD = 0u; +#endif + *pu8OCFS = 0u; + +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + if(TRUE == bTouchNvic) + { + MftOcuDeInitNvic(pstcOcu); + } +#endif + + return Ok; +} + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Compare congifuration of even OCU channel + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] EvenCh even channel of OCU + ** \arg MFT_OCU_CH0, MFT_OCU_CH2, MFT_OCU_CH4 + ** \param [in] pstcConfig pointer to structure of compare mode + ** + ** \retval Ok Even OCU channel compare mode is set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - EvenCh out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Ocu_SetEvenChCompareMode(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t EvenCh, + stc_ocu_even_compare_config_t* pstcConfig) +{ + volatile uint16_t* p16OCSE0; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (0u != EvenCh%2) + || (NULL == pstcConfig) + || (pstcConfig->enFrtZeroEvenMatchEvenChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtZeroEvenNotMatchEvenChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtUpCntEvenMatchEvenChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtPeakEvenMatchEvenChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtPeakEvenNotMatchEvenChStatus > RtOutputReverse) + || (pstcConfig->enFrtDownCntEvenMatchEvenChRtStatus > RtOutputReverse) + || (pstcConfig->enIopFlagWhenFrtZeroEvenMatch > IopFlagSet) + || (pstcConfig->enIopFlagWhenFrtUpCntEvenMatch > IopFlagSet) + || (pstcConfig->enIopFlagWhenFrtPeakEvenMatch > IopFlagSet) + || (pstcConfig->enIopFlagWhenFrtDownCntEvenMatch > IopFlagSet) ) + { + return ErrorInvalidParameter ; + } + + p16OCSE0 = (volatile uint16_t*)((volatile uint8_t*)&pstcOcu->OCSE0 + EvenCh*4u); + *p16OCSE0 = 0u; + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enFrtZeroEvenMatchEvenChRtStatus << 10u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enFrtZeroEvenNotMatchEvenChRtStatus << 14u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enFrtUpCntEvenMatchEvenChRtStatus << 8u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enFrtPeakEvenMatchEvenChRtStatus << 6u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enFrtPeakEvenNotMatchEvenChStatus << 12u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enFrtDownCntEvenMatchEvenChRtStatus << 4u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enIopFlagWhenFrtZeroEvenMatch << 3u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enIopFlagWhenFrtUpCntEvenMatch << 2u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enIopFlagWhenFrtPeakEvenMatch << 1u); + *p16OCSE0 |= (uint16_t)((uint16_t)pstcConfig->enIopFlagWhenFrtDownCntEvenMatch << 0u); +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + (TRUE == pstcConfig->bFrtZeroPeakExtendMatchCondition) ? (*p16OCSE0 |= (1ul<<12u)) : (*p16OCSE0 &= ~(1ul<<12u)); + #endif +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Compare congifuration of odd OCU channel + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] OddCh odd channel of OCU + ** \arg MFT_OCU_CH1, MFT_OCU_CH3, MFT_OCU_CH5 + ** \param [in] pstcConfig pointer to structure of compare mode + ** + ** \retval Ok Odd OCU channel compare mode is set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - OddCh out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Ocu_SetOddChCompareMode (volatile stc_mftn_ocu_t*pstcOcu, + uint8_t OddCh, + stc_ocu_odd_compare_config_t* pstcConfig) +{ + volatile uint32_t* pu32OCSE1; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (0u == OddCh%2u) + || (pstcConfig->enFrtZeroOddMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtZeroOddMatchEvenNotMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtZeroOddNotMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtZeroOddNotMatchEvenNotMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtUpCntOddMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtUpCntOddMatchEvenNotMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtUpCntOddNotMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtPeakOddMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtPeakOddMatchEvenNotMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtPeakOddNotMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtPeakOddNotMatchEvenNotMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtDownOddMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtDownOddMatchEvenNotMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enFrtDownOddNotMatchEvenMatchOddChRtStatus > RtOutputReverse) + || (pstcConfig->enIopFlagWhenFrtZeroOddMatch > IopFlagSet) + || (pstcConfig->enIopFlagWhenFrtUpCntOddMatch > IopFlagSet) + || (pstcConfig->enIopFlagWhenFrtPeakOddMatch > IopFlagSet) + || (pstcConfig->enIopFlagWhenFrtDownCntOddMatch > IopFlagSet) ) + { + return ErrorInvalidParameter ; + } + + pu32OCSE1 = (volatile uint32_t*)((volatile uint8_t*)&pstcOcu->OCSE0 + OddCh*4u); + *pu32OCSE1 = 0u; + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtZeroOddMatchEvenMatchOddChRtStatus << 26u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtZeroOddMatchEvenNotMatchOddChRtStatus << 10u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtZeroOddNotMatchEvenMatchOddChRtStatus << 30u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtZeroOddNotMatchEvenNotMatchOddChRtStatus << 14u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtUpCntOddMatchEvenMatchOddChRtStatus << 24u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtUpCntOddMatchEvenNotMatchOddChRtStatus << 8u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtUpCntOddNotMatchEvenMatchOddChRtStatus << 18u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtPeakOddMatchEvenMatchOddChRtStatus << 22u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtPeakOddMatchEvenNotMatchOddChRtStatus << 6u) ; + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtPeakOddNotMatchEvenMatchOddChRtStatus << 28u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtPeakOddNotMatchEvenNotMatchOddChRtStatus << 12u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtDownOddMatchEvenMatchOddChRtStatus << 20u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtDownOddMatchEvenNotMatchOddChRtStatus << 4u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enFrtDownOddNotMatchEvenMatchOddChRtStatus << 16u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enIopFlagWhenFrtZeroOddMatch << 3u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enIopFlagWhenFrtUpCntOddMatch << 2u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enIopFlagWhenFrtPeakOddMatch << 1u); + *pu32OCSE1 |= (uint32_t)((uint32_t)pstcConfig->enIopFlagWhenFrtDownCntOddMatch << 0u); +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + (TRUE == pstcConfig->bFrtZeroPeakExtendMatchCondition) ? (*pu32OCSE1 |= (1ul<<13u)) : (*pu32OCSE1 &= ~(1ul<<13u)); + #endif +#endif + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Set compare mode for FM3 compatible mode + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8CoupleCh Couple channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** \param [in] enCompareMode compare mode of OCU + ** \arg See the structure type of en_ocu_compare_mode_t + ** + ** \retval Ok OCU mode been set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - pstcOcuConfig == NULL + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Ocu_SetCompareMode_Fm3 (volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8CoupleCh, + en_ocu_compare_mode_t enCompareMode) +{ + uint8_t u8Mod; + + if (NULL == pstcOcu) + { + return ErrorInvalidParameter ; + } + + switch (enCompareMode) + { + case OcuOdd1ChangeEven1Change: + case OcuOdd1ChangeEvenActiveHigh: + case OcuOddActiveHighEven1Change: + case OcuOddActiveHighEvenActiveHigh: + switch (u8CoupleCh) + { + case MFT_OCU_CH10: + pstcOcu->OCSB10_f.CMOD = 0u; + break; + case MFT_OCU_CH32: + pstcOcu->OCSB32_f.CMOD = 0u; + break; + case MFT_OCU_CH54: + pstcOcu->OCSB54_f.CMOD = 0u; + break; + default: + return ErrorInvalidParameter ; + } + break; + case OcuOdd2ChangeEven1Change: + case OcuOddActiveLowEven1Change: + case OcuOddActiveLowEvenActiveLow: + switch (u8CoupleCh) + { + case MFT_OCU_CH10: + pstcOcu->OCSB10_f.CMOD = 1u; + break; + case MFT_OCU_CH32: + pstcOcu->OCSB32_f.CMOD = 1u; + break; + case MFT_OCU_CH54: + pstcOcu->OCSB54_f.CMOD = 1u; + break; + default: + return ErrorInvalidParameter ; + } + break; + default: + return ErrorInvalidParameter ; + + } + + switch (enCompareMode) + { + case OcuOdd1ChangeEven1Change: + case OcuOdd2ChangeEven1Change: + u8Mod = 0u; + break; + case OcuOdd1ChangeEvenActiveHigh: + u8Mod = 1u; + break; + case OcuOddActiveHighEven1Change: + case OcuOddActiveLowEven1Change: + u8Mod = 2u; + break; + case OcuOddActiveHighEvenActiveHigh: + case OcuOddActiveLowEvenActiveLow: + u8Mod = 3u; + break; + default: + return ErrorInvalidParameter ; + + } + + pstcOcu->OCSC &= ~(3u << (u8CoupleCh * 2u)); + pstcOcu->OCSC |= ((uint8_t)u8Mod << (u8CoupleCh * 2u)); + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief enable ocu operation + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval Ok OCU operation enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Ocu_EnableOperation(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch) +{ + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel OCU register address + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + (u8Ch/2u)*4u); + + //set register + if(0u == (u8Ch%2)) //channel 0,2,4 + { + pstcOCSA->CST0 = 1u; + } + else //channel 1,3,5 + { + pstcOCSA->CST1 = 1u; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Disable ocu operation + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval Ok OCU operation disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Ocu_DisableOperation(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch) +{ + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel OCU register address + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + ((u8Ch/2u) * 4u)); + + //set register + if(0 == (u8Ch%2)) //channel 0,2,4 + { + pstcOCSA->CST0 = 0u; + } + else //channel 1,3,5 + { + pstcOCSA->CST1 = 0u; + } + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) +/*! + ****************************************************************************** + ** \brief enable ocu interrupt + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** \param [in] pfnCallback callback function + ** + ** \retval Ok OCU interrupt enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Ocu_EnableIrq(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, func_ptr_t pfnCallback) +{ + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel OCU register address + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + ((u8Ch/2u) * 4u)); + + //set register + if(0u == (u8Ch%2)) //channel 0,2,4 + { + pstcOCSA->IOE0 = 1u; + } + else //channel 1,3,5 + { + pstcOCSA->IOE1 = 1u; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Disable ocu interrupt + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval Ok OCU interrupt disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Ocu_DisableIrq(volatile stc_mftn_ocu_t* pstcOcu,uint8_t u8Ch) +{ + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel OCU register address + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + (u8Ch/2u)*4u); + + //set register + if(0u == (u8Ch%2u)) //channel 0,2,4 + { + pstcOCSA->IOE0 = 0u; + } + else //channel 1,3,5 + { + pstcOCSA->IOE1 = 0u; + } + + return Ok; +} + +#endif + +/*! + ****************************************************************************** + ** \brief get ocu interrupt flag + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval PdlClr OCU interrupt flag is clear + ** \retval PdlSet OCU interrupt flag is set + ** + ***************************************************************************** +*/ +en_irq_flag_t Mft_Ocu_GetIrqFlag(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch) +{ + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; + en_irq_flag_t enFlag = PdlClr; + + //Get pointer of current channel OCU register address + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + (u8Ch/2u)*4u); + + //set return value + if(0u == (u8Ch%2)) //channel 0,2,4 + { + (pstcOCSA->IOP0 == 1u) ? (enFlag = PdlSet) : (enFlag = PdlClr); + } + else //channel 1,3,5 + { + (pstcOCSA->IOP1 == 1u) ? (enFlag = PdlSet) : (enFlag = PdlClr); + } + + return enFlag; +} + +/*! + ****************************************************************************** + ** \brief clear ocu interrupt flag + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval Ok OCU interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Ocu_ClrIrqFlag(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch) +{ + volatile stc_mft_ocu_ocsa10_field_t* pstcOCSA; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return ErrorInvalidParameter ; + } + + //Get pointer of current channel OCU register address + pstcOCSA = (volatile stc_mft_ocu_ocsa10_field_t*)((volatile uint8_t*)&pstcOcu->OCSA10 + (u8Ch/2u)*4u); + + //clear register + if(0u == (u8Ch%2u)) //channel 0,2,4 + { + pstcOCSA->IOP0 = 0u; + } + else //channel 1,3,5 + { + pstcOCSA->IOP1 = 0u; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Get RT pin level of OCU + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval RtLowlevel RT pin is low level + ** \retval RtHighlevel RT pin is high level + ** + ***************************************************************************** +*/ +en_ocu_rt_out_state_t Mft_Ocu_GetRtPinLevel(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch) +{ + volatile stc_mft_ocu_ocsb10_field_t* pstcOCSB; + en_ocu_rt_out_state_t enLevel = RtLowLevel; + + // Get the OCSB address + pstcOCSB = (volatile stc_mft_ocu_ocsb10_field_t*)((volatile uint8_t*)&pstcOcu->OCSB10 + (u8Ch/2u)*4u); + + if(0u == (u8Ch%2)) + { + (pstcOCSB->OTD0 == 1u) ? (enLevel = RtHighLevel) : (enLevel = RtLowLevel); + } + else + { + (pstcOCSB->OTD1 == 1u) ? (enLevel = RtHighLevel) : (enLevel = RtLowLevel); + } + + return enLevel; +} + +/*! + ****************************************************************************** + ** \brief writ occp register + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** \param [in] u16Occp the value of occp + ** \arg 16bit value + ** + ** \retval Ok OCCP written + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8Ch out of range + ** - Other invalid configuration + ** + ***************************************************************************** +*/ +en_result_t Mft_Ocu_WriteOccp(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, uint16_t u16Occp) +{ + volatile uint16_t* p16OCCP; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return ErrorInvalidParameter ; + } + //Get pointer of current channel OCU register address + p16OCCP = (volatile uint16_t*)((volatile uint8_t*)&pstcOcu->OCCP0 + u8Ch*4u); + + //set register + *p16OCCP = u16Occp; + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief get occp register value + ** + ** \param [in] pstcOcu Pointer to OCU instance + ** \param [in] u8Ch channel of OCU + ** \arg MFT_OCU_CH0 ~ MFT_OCU_CH5 + ** + ** \retval 16bit occp value + ** + ***************************************************************************** +*/ +uint16_t Mft_Ocu_ReadOccp(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch) +{ + volatile uint16_t* p16OCCP; + + // Check for NULL pointer + if ( (NULL == pstcOcu) + || (u8Ch >= MFT_OCU_MAXCH)) + { + return 0u ; + } + //Get pointer of current channel OCU register address + p16OCCP = (volatile uint16_t*)((volatile uint8_t*)&pstcOcu->OCCP0 + u8Ch*4u); + + return (uint16_t)((*p16OCCP) & 0xFFFFu); +} + +#endif // #if (defined(PDL_PERIPHERAL_$$X_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_ocu.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_ocu.h new file mode 100644 index 0000000000..0df4a4129b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_ocu.h @@ -0,0 +1,478 @@ +/******************************************************************************* +* \file mft_ocu.h +* +* \version 1.20 +* +* \brief Headerfile for MFT_OCU functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MFT_OCU_H__ +#define __MFT_OCU_H__ +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_MFT_OCU_ACTIVE)) + +/** +* \defgroup GroupMFT_OCU Output Compare Unit (MFT OCU) +* \{ +* \defgroup GroupMFT_OCU_Macros Macros +* \defgroup GroupMFT_OCU_Functions Functions +* \defgroup GroupMFT_OCU_GlobalVariables Global Variables +* \defgroup GroupMFT_OCU_DataStructures Data Structures +* \defgroup GroupMFT_OCU_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupMFT_OCU +* \{ +* The Multi-function Timer (MFT) is a collection of peripherals used primarily +* for motor control. There may be up to three MFTs supported on a particular FM microcontroller. +* One MFT can control a 3-phase motor. A microcontroller that supports multiple MFTs can +* control multiple 3-phase motors.
+* The peripherals in the MFT are:
+* - Free-run Timer (FRT) +* - Output Compare Unit (OCU) +* - Waveform Generator (WFG) +* - Input Capture Unit (ICU) +* - ADC Start Compare (ADCMP) +* Each MFT has three independent OCU instances with two channels per unit.
+* Each OCU generates and outputs PWM signals based on the counter value of the +* FRT and a compare value in the OCU. When the count value matches the compare value, +* the output signal is inverted. Changing the ratio of the compare value of the OCU to the count +* cycle of the FRT changes the duty cycle of the PWM. You can also change the match conditions +* for even and odd OCU channels (0-5).
+* You can change the OCU compare value at runtime. The OCU supports a buffered compare value. +* If you use the buffer, the compare value updates at a defined moment (for example, at +* a zero count or peak count). Otherwise it updates immediately.
+* Each OCU uses one of five possible FRT inputs. Three inputs are from the three FRT instances +* of the corresponding MFT module. The other two FRT inputs are routed from the other +* possible MFT instances. This enables each OCU to be synchronized using a single FRT, +* or multiple FRTs.
+* You can configure the OCU to generate an interrupt when the compare value matches the counter.
+* The output of each OCU is directly routed to a Waveform Generator. +* \section SectionMFT_OCU_ConfigurationConsideration Configuration Consideration +* To set up an OCU, first you should configure an FRT. See the description in the MFT FRT.
+* For the OCU itself, provide configuration parameters in the stc_mft_ocu_config_t structure, +* such as the FRT to use, whether to enable the buffer for the compare value, and so on. +* You also enable or disable the interrupt when there is a match between the compare value and +* counter value. Then call Mft_Ocu_Init().
+* You must also call Mft_Ocu_WriteOccp() to set the compare value. This is not part of the +* configuration structure, because you may modify this at runtime. If you are using buffering, +* the value updates at the defined moment.
+* Finally, call Mft_Ocu_EnableOperation() to start the OCU.
+* You can enable or disable interrupts at runtime. In polling mode, use Mft_Ocu_GetIrqFlag() +* to check if the interrupt occurs, and clear the interrupt flag by Mft_Ocu_ClrIrqFlag(). +* \section SectionMFT_OCU_MoreInfo More Information +* For more information on the MFT OCU peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupMFT_OCU_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_mftn_ocu_t FM_MFT_OCU_TypeDef + +#define MFT0_OCU (*((volatile stc_mftn_ocu_t *) FM_MFT0_OCU_BASE)) +#define MFT1_OCU (*((volatile stc_mftn_ocu_t *) FM_MFT1_OCU_BASE)) +#define MFT2_OCU (*((volatile stc_mftn_ocu_t *) FM_MFT2_OCU_BASE)) + +#define MFT_OCU_CH0 0u +#define MFT_OCU_CH1 1u +#define MFT_OCU_CH2 2u +#define MFT_OCU_CH3 3u +#define MFT_OCU_CH4 4u +#define MFT_OCU_CH5 5u +#define MFT_OCU_MAXCH 6u + +#define MFT_OCU_CH10 0u +#define MFT_OCU_CH32 1u +#define MFT_OCU_CH54 2u + +#define OCU_INSTANCE_COUNT (PDL_PERIPHERAL_ENABLE_MFT0_OCU == PDL_ON ? 1u :0u) + \ + (PDL_PERIPHERAL_ENABLE_MFT1_OCU == PDL_ON ? 1u :0u) + \ + (PDL_PERIPHERAL_ENABLE_MFT2_OCU == PDL_ON ? 1u :0u) + +/** \} GroupMFT_OCU_Macros */ + +/** +* \addtogroup GroupMFT_OCU_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each OCU instance + ******************************************************************************/ +typedef enum en_ocu_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_OCU == PDL_ON) + OcuInstanceIndexOcu0 = 0u, ///< Instance index of OCU0 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_OCU == PDL_ON) + OcuInstanceIndexOcu1, ///< Instance index of OCU1 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_OCU == PDL_ON) + OcuInstanceIndexOcu2, ///< Instance index of OCU2 +#endif + +} en_ocu_instance_index_t; + +/** + ****************************************************************************** + ** \brief select the FRT to be connected to OCU + ******************************************************************************/ +typedef enum en_mft_ocu_frt +{ + Frt0ToOcu = 0u, ///< connect FRT0 to OCU + Frt1ToOcu = 1u, ///< connect FRT1 to OCU + Frt2ToOcu = 2u, ///< connect FRT2 to OCU + +}en_mft_ocu_frt_t; + +/** + ****************************************************************************** + ** \brief output level of the RT pin state + ******************************************************************************/ +typedef enum en_ocu_rt_out_state +{ + RtLowLevel = 0u, ///< output low level to RT pin + RtHighLevel = 1u, ///< output high level to RT pin +}en_ocu_rt_out_state_t; + +/** + ****************************************************************************** + ** \brief buffer register function of OCCP + ******************************************************************************/ +typedef enum en_ocu_occp_buf +{ + OccpBufDisable = 0u, ///< disable the buffer function + OccpBufTrsfByFrtZero = 1u, ///< buffer transfer when counter value is 0x0000 + OccpBufTrsfByFrtPeak = 2u, ///< buffer transfer when counter value is TCCP +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + OccpBufTrsfByFrtZeroPeak = 3u, ///< buffer transfer when the value is both 0 and TCCP +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + OccpBufTrsfByFrtZeroMszcZero = 4u, ///< buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 + OccpBufTrsfByFrtPeakMspcZero = 5u, ///< buffer transfer when counter value is TCCP and peak value detection mask counter value is 0 + OccpBufTrsfByFrtZeroMszcZeroOrFrtPeakMspcZero = 6u, ///< buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or + ///< when counter value is TCCP and peak value detection mask counter value is 0 + #endif +#endif +}en_ocu_occp_buf_t; + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief buffer register function of OCSE + ******************************************************************************/ +typedef enum en_ocu_ocse_buf +{ + OcseBufDisable = 0u, ///< disable the buffer function + OcseBufTrsfByFrtZero = 1u, ///< buffer transfer when counter value is 0x0000 + OcseBufTrsfByFrtPeak = 2u, ///< buffer transfer when counter value is TCCP + OcseBufTrsfByFrtZeroPeak = 3u, ///< buffer transfer when the value is both 0 and TCCP +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + OcseBufTrsfByFrtZeroMszcZero = 4u, ///< buffer transfer when FRT counter value is 0x0000 and zero value detection mask counter value is 0 + OcseBufTrsfByFrtPeakMspcZero = 5u, ///< buffer transfer when FRT counter value is TCCP and peak value detection mask counter value is 0 + OcseBufTrsfByFrtZeroMszcZeroOrFrtPeakMspcZero = 6u, ///< buffer transfer when FRT counter value is 0x0000 and zero value detection mask counter value is 0 or + ///< when FRT counter value is TCCP and peak value detection mask counter value is 0 + #endif +#endif +}en_ocu_ocse_buf_t; +#endif + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief RT output status + ******************************************************************************/ +typedef enum en_rt_status +{ + RtOutputHold = 0u, ///< RT output hold + RtOutputHigh = 1u, ///< RT output high + RtOutputLow = 2u, ///< RT output low + RtOutputReverse = 3u, ///< RT output reverse + +}en_rt_even_status_t, en_rt_odd_status_t; + +/** + ****************************************************************************** + ** \brief The condition for IOP flag set + ******************************************************************************/ +typedef enum en_iop_flag_set_condition +{ + IopFlagHold = 0u, ///< IOP flag hold + IopFlagSet = 1u, ///< IOP flag set + +}en_iop_flag_even_t, en_iop_flag_odd_t; + +#endif + +/** + ****************************************************************************** + ** \brief The compare mode of OCU couple channels (FM3 mode) + ** + ** \note The OCU channel with 1 change mode or 2 change mode must connect + ** with FRT with up count mode. + ** The OCU channel with active high mode or active low mode must + ** connect with FRT with up/down count mode. + ******************************************************************************/ +typedef enum en_ocu_compare_mode +{ + OcuOdd1ChangeEven1Change = 0u, ///< Odd OCU channel is set to 1 change mode, even OCU channel is set to 1 change mode. + OcuOdd2ChangeEven1Change = 1u, ///< Odd OCU channel is set to 2 change mode, even OCU channel is set to 1 change mode. + OcuOdd1ChangeEvenActiveHigh = 2u, ///< Odd OCU channel is set to 1 change mode, even OCU channel is set to active high mode. + OcuOddActiveHighEven1Change = 3u, ///< Odd OCU channel is set to active high mode, even OCU channel is set to 1 change mode. + OcuOddActiveLowEven1Change = 4u, ///< Odd OCU channel is set to active low mode, even OCU channel is set to 1 change mode. + OcuOddActiveHighEvenActiveHigh = 5u, ///< Odd OCU channel is set to active high mode, even OCU channel is set to active high mode. + OcuOddActiveLowEvenActiveLow = 6u, ///< Odd OCU channel is set to active low mode, even OCU channel is set to active low mode. + +}en_ocu_compare_mode_t; + +/** \} GroupMFT_OCU_Types */ + +/** +* \addtogroup GroupMFT_OCU_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief OCU configure + ******************************************************************************/ +typedef struct stc_mft_ocu_config +{ + en_mft_ocu_frt_t enFrtConnect; ///< select the FRT to be connected to OCU + en_ocu_occp_buf_t enOccpBufMode; ///< buffer register function of OCCP +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + en_ocu_ocse_buf_t enOcseBufMode; ///< buffer register function of OCSE + boolean_t bFm4; ///< TRUE: set the compare mode of used channels with Mft_Ocu_SetEvenChCompareMode() and Mft_Ocu_SetOddChCompareMode() + ///< FALSE: set the compare mode of used channels with Mft_Ocu_SetCompareMode_Fm3() +#endif + en_ocu_rt_out_state_t enPinState; ///< RT output level state + +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) + boolean_t bIrqEnable; ///< TRUE: enable OCU interrupt, FALSE: disable OCU interrupt + func_ptr_t pfnIrqCallback; ///< Pointer to OCU interrupt callback function. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: disable NVIC +#endif + +}stc_mft_ocu_config_t; + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + +/** + ****************************************************************************** + ** \brief The compare configuration of even OCU channel + ******************************************************************************/ +typedef struct stc_ocu_even_compare_config +{ + en_rt_even_status_t enFrtZeroEvenMatchEvenChRtStatus; ///< Even channel's RT output status when even channel match occurs at the condition of FRT count=0x0000 + en_rt_even_status_t enFrtZeroEvenNotMatchEvenChRtStatus; ///< Even channel's RT output status when even channel match doesn't occur at the condition of FRT count=0x0000 + + en_rt_even_status_t enFrtUpCntEvenMatchEvenChRtStatus; ///< Even channel's RT output status when even channel match occurs at the condition of FRT is counting up + + en_rt_even_status_t enFrtPeakEvenMatchEvenChRtStatus; ///< Even channel's RT output status when even channel match occurs at the condition of FRT count=Peak + en_rt_even_status_t enFrtPeakEvenNotMatchEvenChStatus; ///< Even channel's RT output status when even channel match doesn't occur at the condition of FRT count=Peak + + en_rt_even_status_t enFrtDownCntEvenMatchEvenChRtStatus; ///< Even channel's RT output status when even channel match occurs at the condition of FRT is counting down + + en_iop_flag_even_t enIopFlagWhenFrtZeroEvenMatch; ///< Even channel OCU's IOP flag status when even channel match occurs at the condition of FRT count=0x0000 + en_iop_flag_even_t enIopFlagWhenFrtUpCntEvenMatch; ///< Even channel OCU's IOP flag status when even channel match occurs at the condition of FRT is counting up + en_iop_flag_even_t enIopFlagWhenFrtPeakEvenMatch; ///< Even channel OCU's IOP flag status when even channel match occurs at the condition of FRT count=Peak + en_iop_flag_even_t enIopFlagWhenFrtDownCntEvenMatch; ///< Even channel OCU's IOP flag status when even channel match occurs at the condition of FRT is counting down + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + boolean_t bFrtZeroPeakExtendMatchCondition; ///< TRUE: The condition of that OCCP <= FRT counter value will be treated as comparison match + ///< FALSE: The condition of that OCCP > FRT counter value will be treated as comparison not match + + #endif +#endif + +}stc_ocu_even_compare_config_t; + +/** + ****************************************************************************** + ** \brief The compare configuration of odd OCU channel + ******************************************************************************/ +typedef struct stc_ocu_odd_compare_config +{ + en_rt_odd_status_t enFrtZeroOddMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel and odd channel match occurs at the condition of FRT count=0x0000 + en_rt_odd_status_t enFrtZeroOddMatchEvenNotMatchOddChRtStatus; ///< Odd channel's RT output status when even channel not match and odd channel match occurs at the condition of FRT count=0x0000 + en_rt_odd_status_t enFrtZeroOddNotMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel match and odd channel not match occurs at the condition of FRT count=0x0000 + en_rt_odd_status_t enFrtZeroOddNotMatchEvenNotMatchOddChRtStatus; ///< Odd channel's RT output status when even channel not match and odd channel not match occurs at the condition of FRT count=0x0000 + + en_rt_odd_status_t enFrtUpCntOddMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel and odd channel match occurs at the condition of FRT is counting up + en_rt_odd_status_t enFrtUpCntOddMatchEvenNotMatchOddChRtStatus; ///< Odd channel's RT output status when even channel not match and odd channel match occurs at the condition of FRT is counting up + en_rt_odd_status_t enFrtUpCntOddNotMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel match and odd channel not match occurs at the condition of FRT is counting up + + en_rt_odd_status_t enFrtPeakOddMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel and odd channel match occurs at the condition of FRT count=Peak + en_rt_odd_status_t enFrtPeakOddMatchEvenNotMatchOddChRtStatus; ///< Odd channel's RT output status when even channel not match and odd channel match occurs at the condition of FRT count=Peak + en_rt_odd_status_t enFrtPeakOddNotMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel match and odd channel not match occurs at the condition of FRT count=Peak + en_rt_odd_status_t enFrtPeakOddNotMatchEvenNotMatchOddChRtStatus;///< Odd channel's RT output status when even channel not match and odd channel not match occurs at the condition of FRT count=Peak + + en_rt_odd_status_t enFrtDownOddMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel and odd channel match occurs at the condition of FRT is counting down + en_rt_odd_status_t enFrtDownOddMatchEvenNotMatchOddChRtStatus; ///< Odd channel's RT output status when even channel not match and odd channel match occurs at the condition of FRT is counting down + en_rt_odd_status_t enFrtDownOddNotMatchEvenMatchOddChRtStatus; ///< Odd channel's RT output status when even channel match and odd channel not match occurs at the condition of FRT is coutning down + + en_iop_flag_odd_t enIopFlagWhenFrtZeroOddMatch; ///< Odd channel OCU's IOP flag status when Odd channel match occurs at the condition of FRT count=0x0000 + en_iop_flag_odd_t enIopFlagWhenFrtUpCntOddMatch; ///< Odd channel OCU's IOP flag status when Odd channel match occurs at the condition of FRT is counting up + en_iop_flag_odd_t enIopFlagWhenFrtPeakOddMatch; ///< Odd channel OCU's IOP flag status when Odd channel match occurs at the condition of FRT count=Peak + en_iop_flag_odd_t enIopFlagWhenFrtDownCntOddMatch; ///< Odd channel OCU's IOP flag status when Odd channel match occurs at the condition of FRT is counting down + +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + boolean_t bFrtZeroPeakExtendMatchCondition; ///< TRUE: The condition of that OCCP <= FRT counter value will be treated as comparison match + ///< FALSE: The condition of that OCCP > FRT counter value will be treated as comparison not match + + #endif +#endif + +}stc_ocu_odd_compare_config_t; + +#endif + +/** + ****************************************************************************** + ** \brief Structure of OCU internal data + ******************************************************************************/ +typedef struct stc_mft_ocu_intern_data +{ + func_ptr_t pfnOcu0IrqCallback; ///< Callback function pointer of OCU0 interrupt + func_ptr_t pfnOcu1IrqCallback; ///< Callback function pointer of OCU1 interrupt + func_ptr_t pfnOcu2IrqCallback; ///< Callback function pointer of OCU2 interrupt + func_ptr_t pfnOcu3IrqCallback; ///< Callback function pointer of OCU3 interrupt + func_ptr_t pfnOcu4IrqCallback; ///< Callback function pointer of OCU4 interrupt + func_ptr_t pfnOcu5IrqCallback; ///< Callback function pointer of OCU5 interrupt +}stc_mft_ocu_intern_data_t; + +/** + ****************************************************************************** + ** \brief OCU instance data type + ******************************************************************************/ +typedef struct stc_mft_ocu_instance_data +{ + volatile stc_mftn_ocu_t* pstcInstance; ///< pointer to registers of an instance + stc_mft_ocu_intern_data_t stcInternData; ///< module internal data of instance +} stc_mft_ocu_instance_data_t; + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** \} GroupMFT_OCU_DataStructures */ + +/** +* \addtogroup GroupMFT_OCU_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/// Look-up table for all enabled OCU instances and their internal data +extern stc_mft_ocu_instance_data_t m_astcMftOcuInstanceDataLut[OCU_INSTANCE_COUNT]; + +/** \} GroupMFT_OCU_GlobalVariables */ + +/** +* \addtogroup GroupMFT_OCU_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +/* Init */ +en_result_t Mft_Ocu_Init( volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, + const stc_mft_ocu_config_t* pstcOcuConfig); +en_result_t Mft_Ocu_DeInit( volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, + boolean_t bTouchNvic); +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/* Compare configuration */ +en_result_t Mft_Ocu_SetEvenChCompareMode(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t EvenCh, + stc_ocu_even_compare_config_t* pstcConfig); +en_result_t Mft_Ocu_SetOddChCompareMode (volatile stc_mftn_ocu_t* pstcOcu, + uint8_t OddCh, + stc_ocu_odd_compare_config_t* pstcConfig); +#endif +en_result_t Mft_Ocu_SetCompareMode_Fm3(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8CoupleCh, + en_ocu_compare_mode_t enCompareMode); + +/* Func/Int enable/disable */ +en_result_t Mft_Ocu_EnableOperation(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch); +en_result_t Mft_Ocu_DisableOperation(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch); +#if (PDL_INTERRUPT_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_OCU == PDL_ON) +en_result_t Mft_Ocu_EnableIrq(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch,func_ptr_t pfnCallback); +en_result_t Mft_Ocu_DisableIrq(volatile stc_mftn_ocu_t* pstcOcu,uint8_t u8Ch); +#endif + +/* Count write/read */ +en_result_t Mft_Ocu_WriteOccp(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch, uint16_t u16Occp); +uint16_t Mft_Ocu_ReadOccp(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch); + +/* Status read/clear */ +en_irq_flag_t Mft_Ocu_GetIrqFlag(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch); +en_result_t Mft_Ocu_ClrIrqFlag(volatile stc_mftn_ocu_t* pstcOcu, uint8_t u8Ch); + +/* Get RT pin level */ +en_ocu_rt_out_state_t Mft_Ocu_GetRtPinLevel(volatile stc_mftn_ocu_t* pstcOcu, + uint8_t u8Ch); + +/* IRQ handler */ +void Mft_Ocu_IrqHandler( volatile stc_mftn_ocu_t* pstcOcu, + stc_mft_ocu_intern_data_t* pstcMftOcuInternData) ; + +/** \} GroupMFT_OCU_Functions */ +/** \} GroupMFT_OCU */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_ADC_ACTIVE)) + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_wfg.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_wfg.c new file mode 100644 index 0000000000..62b9ae32c4 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_wfg.c @@ -0,0 +1,1099 @@ +/******************************************************************************* +* \file mft_wfg.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the +* MFT_WFG driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mft/mft_wfg.h" + + +#if (defined(PDL_PERIPHERAL_MFT_WFG_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled WFG instances and their internal data +stc_mft_wfg_instance_data_t m_astcMftWfgInstanceDataLut[WFG_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_WFG == PDL_ON) + { + &MFT0_WFG, // pstcInstance + {0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_WFG == PDL_ON) + { + &MFT1_WFG, // pstcInstance + {0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_WFG == PDL_ON) + { + &MFT2_WFG, // pstcInstance + {0u, 0u, 0u, 0u, 0u} // stcInternData (not initialized yet) + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +/** + ***************************************************************************** + ** \brief Return the internal data for a certain WFG instance. + ** + ** \param pstcWfg Pointer to WFG instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled + ** (or not known) + ** + *****************************************************************************/ +static stc_mft_wfg_intern_data_t* MftGetInternDataPtr(volatile stc_mftn_wfg_t* pstcWfg) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < WFG_INSTANCE_COUNT; u32Instance++) + { + if (pstcWfg == m_astcMftWfgInstanceDataLut[u32Instance].pstcInstance) + { + return &m_astcMftWfgInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) +/*! + ****************************************************************************** + ** \brief WFG interrupt handler sub function + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \param [in] pstcMftWfgInternData structure of WFG callback function + ** \arg structure of stc_mft_intern_data + ***************************************************************************** +*/ +void Mft_Wfg_IrqHandler( volatile stc_mftn_wfg_t* pstcWfg, + stc_mft_wfg_intern_data_t* pstcMftWfgInternData) +{ + func_ptr_t funCallBack; + uint32_t* ptemp; + uint8_t ch; + + /* timer interrupt*/ + for(ch=0u; ch<3u; ch++) + { + if(PdlSet == Mft_Wfg_GetTimerIrqFlag(pstcWfg,ch)) + { + /* Clear Interrupt */ + Mft_Wfg_ClrTimerIrqFlag(pstcWfg,ch); + + //get peak timer interrupt callback address of each channel + ptemp = (uint32_t*)&(pstcMftWfgInternData->pfnWfg10TimerIrqCallback); + funCallBack = (func_ptr_t)(*(ptemp + ch)); + + if(NULL != funCallBack) + { + funCallBack(); + } + } + } + + /* DTIF Interrupt */ + //Digital filter interrupt + if(PdlSet == Mft_Wfg_Nzcl_GetDigitalFilterIrqFlag(pstcWfg)) + { + // Mft_Wfg_Nzcl_ClrDigitalFilterIntFlag(pstcMft); + funCallBack = pstcMftWfgInternData->pfnDtifDigtalFilterIrqCallback; + if(NULL != funCallBack) + { + funCallBack(); + } + } + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + //analog filter interrupt + if(PdlSet == Mft_Wfg_Nzcl_GetAnalogFilterIrqFlag(pstcWfg)) + { + // Mft_Wfg_Nzcl_ClrAnalogFilterIntFlag(pstcMft); + funCallBack = pstcMftWfgInternData->pfnDtifAnalogFilterIrqCallback; + if(NULL != funCallBack) + { + funCallBack(); + } + } +#endif +} + +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl.h + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval Ok Successful initialization + ** + ******************************************************************************/ +static void MftWfgInitNvic( volatile stc_mftn_wfg_t* pstcWfg ) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_EnableIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT0_WFG_DTIF_IRQn, PDL_IRQ_LEVEL_MFT_WFG); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(WFG_DTIF_IRQn); + NVIC_EnableIRQ(WFG_DTIF_IRQn); + NVIC_SetPriority(WFG_DTIF_IRQn, PDL_IRQ_LEVEL_MFT_WFG); +#else + #if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) + if(pstcWfg == (volatile stc_mftn_wfg_t*)(&MFT0_WFG)) + { + NVIC_ClearPendingIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_EnableIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT0_WFG_DTIF_IRQn, PDL_IRQ_LEVEL_MFT0_WFG); + } + #endif + #if (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) + if(pstcWfg == (volatile stc_mftn_wfg_t*)(&MFT1_WFG)) + { + NVIC_ClearPendingIRQ(MFT1_WFG_DTIF_IRQn); + NVIC_EnableIRQ(MFT1_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT1_WFG_DTIF_IRQn, PDL_IRQ_LEVEL_MFT1_WFG); + } + #endif + #if (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) + if(pstcWfg == (volatile stc_mftn_wfg_t*)(&MFT2_WFG)) + { + NVIC_ClearPendingIRQ(MFT2_WFG_DTIF_IRQn); + NVIC_EnableIRQ(MFT2_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT2_WFG_DTIF_IRQn, PDL_IRQ_LEVEL_MFT2_WFG); + } + #endif + +#endif + return; +} + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval Ok Successful initialization + ** + ******************************************************************************/ +static void MftWfgDeInitNvic( volatile stc_mftn_wfg_t* pstcWfg ) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_DisableIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT0_WFG_DTIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + NVIC_ClearPendingIRQ(WFG_DTIF_IRQn); + NVIC_DisableIRQ(WFG_DTIF_IRQn); + NVIC_SetPriority(WFG_DTIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + #if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) + if((volatile stc_mftn_wfg_t*)(&MFT0_WFG) == pstcWfg) + { + NVIC_ClearPendingIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_DisableIRQ(MFT0_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT0_WFG_DTIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) + if((volatile stc_mftn_wfg_t*)(&MFT1_WFG) == pstcWfg) + { + NVIC_ClearPendingIRQ(MFT1_WFG_DTIF_IRQn); + NVIC_DisableIRQ(MFT1_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT1_WFG_DTIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + #if (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) + if((volatile stc_mftn_wfg_t*)(&MFT2_WFG) == pstcWfg) + { + NVIC_ClearPendingIRQ(MFT2_WFG_DTIF_IRQn); + NVIC_DisableIRQ(MFT2_WFG_DTIF_IRQn); + NVIC_SetPriority(MFT2_WFG_DTIF_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + #endif + +#endif + + return; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialize a couple WFG channels + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** \param [in] pstcConfig Pointer to WFG configuration + ** \arg see the struct stc_wfg_config_t + ** + ** \retval Ok WFG mode is configured + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Wfg_Init(volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, + const stc_wfg_config_t* pstcConfig) +{ + volatile stc_mft_wfg_wfsa10_field_t* pstcWFSA; + stc_mft_wfg_intern_data_t* pstcWfgInternData; + + // Check for NULL pointer + if ( (NULL == pstcWfg) + || (u8CoupleCh >= MFT_WFG_MAXCH)) + { + return ErrorInvalidParameter ; + } + // Get pointer to internal data structure ... + pstcWfgInternData = MftGetInternDataPtr( pstcWfg ) ; + + // ... and check for NULL + if ( NULL == pstcWfgInternData ) + { + return ErrorInvalidParameter; + } + + // Get pointer of current channel WFG register address + pstcWFSA = (volatile stc_mft_wfg_wfsa10_field_t*)((volatile uint8_t*)&pstcWfg->WFSA10 + u8CoupleCh*4u); + + // Configure WFG mode + switch(pstcConfig->enMode) + { + case WfgThroughMode: + pstcWFSA->TMD = 0u; + break; + case WfgRtPpgMode: + pstcWFSA->TMD = 1u; + break; + case WfgTimerPpgMode: + pstcWFSA->TMD = 2u; + break; + case WfgRtDeadTimerMode: + pstcWFSA->TMD = 4u; + break; + case WfgRtDeadTimerFilterMode: + pstcWFSA->TMD = 5u; + break; + case WfgPpgDeadTimerFilterMode: + pstcWFSA->TMD = 6u; + break; + case WfgPpgDeadTimerMode: + pstcWFSA->TMD = 7u; + break; + default: + return ErrorInvalidParameter; + } + + // Set control bits + switch (pstcConfig->enDmodBits) + { + case DmodBits00B: + pstcWFSA->DMOD = 0u; + break; + case DmodBits01B: + pstcWFSA->DMOD = 1u; + break; + #if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case DmodBits10B: + pstcWFSA->DMOD = 2u; + break; + case DmodBits11B: + pstcWFSA->DMOD = 3u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + switch (pstcConfig->enPgenBits) + { + case PgenBits00B: + pstcWFSA->PGEN = 0u; + break; + case PgenBits01B: + pstcWFSA->PGEN = 1u; + break; + case PgenBits10B: + pstcWFSA->PGEN = 2u; + break; + case PgenBits11B: + pstcWFSA->PGEN = 3u; + break; + default: + return ErrorInvalidParameter; + } + + switch (pstcConfig->enPselBits) + { + case PselBits00B: + pstcWFSA->PSEL = 0u; + break; + case PselBits01B: + pstcWFSA->PSEL = 1u; + break; + case PselBits10B: + pstcWFSA->PSEL = 2u; + break; + case PselBits11B: + pstcWFSA->PSEL = 3u; + break; + default: + return ErrorInvalidParameter; + } + + switch (pstcConfig->enGtenBits) + { + case GtenBits00B: + pstcWFSA->GTEN = 0u; + break; + case GtenBits01B: + pstcWFSA->GTEN = 1u; + break; + case GtenBits10B: + pstcWFSA->GTEN = 2u; + break; + case GtenBits11B: + pstcWFSA->GTEN = 3u; + break; + default: + return ErrorInvalidParameter; + } + + // Set timer clock division + switch (pstcConfig->enClk) + { + case WfgPlckDiv1: + pstcWFSA->DCK = 0u; + break; + case WfgPlckDiv2: + pstcWFSA->DCK = 1u; + break; + case WfgPlckDiv4: + pstcWFSA->DCK = 2u; + break; + case WfgPlckDiv8: + pstcWFSA->DCK = 3u; + break; + case WfgPlckDiv16: + pstcWFSA->DCK = 4u; + break; + case WfgPlckDiv32: + pstcWFSA->DCK = 5u; + break; + case WfgPlckDiv64: + pstcWFSA->DCK = 6u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case WfgPlckDiv128: + pstcWFSA->DCK = 7u; + break; + #endif + default: + return ErrorInvalidParameter; + } + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + // Set interrupt mask + if(pstcConfig->bWfgimerIrqMask == TRUE) + { + switch (u8CoupleCh) + { + case MFT_WFG_CH10: + pstcWfg->NZCL_f.WIM10 = 1u; + break; + case MFT_WFG_CH32: + pstcWfg->NZCL_f.WIM32 = 1u; + break; + case MFT_WFG_CH54: + pstcWfg->NZCL_f.WIM54 = 1u; + break; + default: + break; + } + } +#endif + // Set interrupt callback functions + switch (u8CoupleCh) + { + case MFT_WFG_CH10: + pstcWfgInternData->pfnWfg10TimerIrqCallback = pstcConfig->pfnWfgTimerIrqCallback; + break; + case MFT_WFG_CH32: + pstcWfgInternData->pfnWfg32TimerIrqCallback = pstcConfig->pfnWfgTimerIrqCallback; + break; + case MFT_WFG_CH54: + pstcWfgInternData->pfnWfg54TimerIrqCallback = pstcConfig->pfnWfgTimerIrqCallback; + break; + default: + break; + } + + if(TRUE == pstcConfig->bTouchNvic) + { + MftWfgInitNvic(pstcWfg); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize a couple WFG channels + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh Couple channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok WFG mode is configured + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcWfg == NULL + ** - u8CoupleCh out of range + ** - Other invalid configuration + ** + ******************************************************************************/ +en_result_t Mft_Wfg_DeInit(volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, + boolean_t bTouchNvic) +{ + volatile uint16_t* pstcWFSA; + stc_mft_wfg_intern_data_t* pstcWfgInternData; + + if(NULL == pstcWfg) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure ... + pstcWfgInternData = MftGetInternDataPtr( pstcWfg ) ; + + // ... and check for NULL + if ( NULL == pstcWfgInternData ) + { + return ErrorInvalidParameter; + } + + // Get pointer of current channel WFG register address + pstcWFSA = (volatile uint16_t*)((volatile uint8_t*)&pstcWfg->WFSA10 + u8CoupleCh*4u); + *pstcWFSA = 0; + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + switch (u8CoupleCh) + { + case MFT_WFG_CH10: + pstcWfgInternData->pfnWfg10TimerIrqCallback = NULL; + pstcWfg->NZCL_f.WIM10 = 0u; + break; + case MFT_WFG_CH32: + pstcWfgInternData->pfnWfg32TimerIrqCallback = NULL; + pstcWfg->NZCL_f.WIM32 = 0u; + break; + case MFT_WFG_CH54: + pstcWfgInternData->pfnWfg54TimerIrqCallback = NULL; + pstcWfg->NZCL_f.WIM54 = 0u; + break; + default: + return ErrorInvalidParameter; + } +#endif + if(TRUE == bTouchNvic) + { + MftWfgDeInitNvic(pstcWfg); + } + +#endif + + return Ok; + +} + +/*! + ****************************************************************************** + ** \brief Start WFG timer + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** + ** \retval Ok Start timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_StartTimer(volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh) +{ + if ( (NULL == pstcWfg) + || (u8CoupleCh >= MFT_WFG_MAXCH)) + { + return ErrorInvalidParameter ; + } + + switch(u8CoupleCh) + { + case MFT_WFG_CH10: + pstcWfg->WFIR_f.TMIE10 = 1u; + break; + case MFT_WFG_CH32: + pstcWfg->WFIR_f.TMIE32 = 1u; + break; + case MFT_WFG_CH54: + pstcWfg->WFIR_f.TMIE54 = 1u; + break; + default: + break; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief Stop WFG timer + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** + ** \retval Ok Stop timer successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_StopTimer(volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh) +{ + if ( (NULL == pstcWfg) + || (u8CoupleCh >= MFT_WFG_MAXCH)) + { + return ErrorInvalidParameter ; + } + + switch(u8CoupleCh) + { + case MFT_WFG_CH10: + pstcWfg->WFIR_f.TMIS10 = 1u; + break; + case MFT_WFG_CH32: + pstcWfg->WFIR_f.TMIS32 = 1u; + break; + case MFT_WFG_CH54: + pstcWfg->WFIR_f.TMIS54 = 1u; + break; + default: + break; + } + + return Ok; +} + + +/*! + ****************************************************************************** + ** \brief get WFG timer interrupt flag + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** + ** \retval PdlSet WFG Interrupt flag is set + ** \retval PdlClr WFG Interrupt flag is clear + ** + ***************************************************************************** +*/ +en_irq_flag_t Mft_Wfg_GetTimerIrqFlag( volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh) +{ + en_irq_flag_t retval = PdlClr; + + switch(u8CoupleCh) + { + case MFT_WFG_CH10: + (pstcWfg->WFIR_f.TMIF10 == 1u) ? (retval = PdlSet) : (retval = PdlClr); + break; + case MFT_WFG_CH32: + (pstcWfg->WFIR_f.TMIF32 == 1u) ? (retval = PdlSet) : (retval = PdlClr); + break; + case MFT_WFG_CH54: + (pstcWfg->WFIR_f.TMIF54 == 1u) ? (retval = PdlSet) : (retval = PdlClr); + break; + default: + break; + } + + return retval; +} + +/*! + ****************************************************************************** + ** \brief clear WFG timer interrupt flag + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** + ** \retval Ok WFG timer interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_ClrTimerIrqFlag( volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh) +{ + // Check for NULL pointer + if ( (NULL == pstcWfg) + || (u8CoupleCh >= MFT_WFG_MAXCH)) + { + return ErrorInvalidParameter ; + } + + //set register value + switch(u8CoupleCh) + { + case MFT_WFG_CH10: + pstcWfg->WFIR_f.TMIC10 = 1u; + break; + case MFT_WFG_CH32: + pstcWfg->WFIR_f.TMIC32 = 1u; + break; + case MFT_WFG_CH54: + pstcWfg->WFIR_f.TMIC54 = 1u; + break; + default: + break; + } + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief write timer count cycle + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** \param [in] u16CycleA WFTA value + ** \arg 0~65535 + ** \param [in] u16CycleB WFTB value + ** \arg 0~65535 + ** + ** \retval Ok Timer count cycle is written + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** - u16CycleA != u16CycleB (FM3 products) + ** + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_WriteTimerCountCycle( volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, + uint16_t u16CycleA, + uint16_t u16CycleB) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile uint16_t* pu16WFTA; + volatile uint16_t* pu16WFTB; +#else + volatile uint16_t* pu16WFTM; +#endif + + // Check for NULL pointer + if ( (NULL == pstcWfg) + || (u8CoupleCh >= MFT_WFG_MAXCH)) + { + return ErrorInvalidParameter ; + } + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + //Get pointer of current channel WFG register address + pu16WFTA = (volatile uint16_t*)((volatile uint8_t*)&pstcWfg->WFTA10 + u8CoupleCh*8); + pu16WFTB = (volatile uint16_t*)((volatile uint8_t*)&pstcWfg->WFTB10 + u8CoupleCh*8); + + //set the register + *pu16WFTA = u16CycleA; + *pu16WFTB = u16CycleB; +#else + if(u16CycleA != u16CycleB) + { + return ErrorInvalidParameter; + } + + pu16WFTM = (volatile uint16_t*)((volatile uint8_t*)&pstcWfg->WFTM10 + u8CoupleCh*4u); + *pu16WFTM = u16CycleA; + +#endif + + return Ok; + +} + +#if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief set cycle of WFG timer + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] u8CoupleCh channel of WFG couple + ** \arg MFT_WFG_CH10 ~ MFT_WFG_CH54 + ** \param [in] u16Count wfg pulse counter value + ** \arg 0~65535 + ** + ** \retval Ok cycle of WFG timer is set + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ******************************************************************************/ +en_result_t Mft_Wfg_SetFilterCountValue( volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, uint16_t u16Count) +{ + volatile uint16_t* pWFTF; + + //Get pointer of current channel WFG register address + pWFTF = (volatile uint16_t*)((volatile uint8_t*)&pstcWfg->WFTF10 + u8CoupleCh*8u); + + *pWFTF =u16Count; + return Ok; +} +#endif + +/** + ****************************************************************************** + ** \brief Initialize NZCL of waveform generator + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] pstcNzclConfig Configure of NZCL + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok NZCL is configured + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** + ******************************************************************************/ +en_result_t Mft_Wfg_Nzcl_Init ( volatile stc_mftn_wfg_t* pstcWfg, + stc_wfg_nzcl_config_t* pstcNzclConfig, + boolean_t bTouchNvic ) +{ + stc_mft_wfg_intern_data_t* pstcWfgInternData; + + // Check for NULL pointer + if ( NULL == pstcWfg ) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcWfgInternData = MftGetInternDataPtr( pstcWfg ) ; + + if(NULL == pstcWfgInternData) + { + return ErrorInvalidParameter ; + } + + // Set digital path for DTTIX pin + pstcWfg->NZCL_f.DTIEA = ((pstcNzclConfig->bEnDigitalFilter == TRUE) ? 1u : 0u); +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + // Set analog path for DTTIX pin + pstcWfg->NZCL_f.DTIEB = ((pstcNzclConfig->bEnAnalogFilter == TRUE) ? 1u : 0u); + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + // Hold RTO pin when DTIF interrupt occurs or not + pstcWfg->NZCL_f.DHOLD = ((pstcNzclConfig->bHoldRto == TRUE) ? 1u : 0u); + #endif +#endif + + // Set filter width of digital path + switch (pstcNzclConfig->enDigitalFilterWidth) + { + case NzlcNoFilter: + pstcWfg->NZCL_f.NWS = 0u; + break; + case NzlcWidth4Cycle: + pstcWfg->NZCL_f.NWS = 1u; + break; + case NzlcWidth8Cycle: + pstcWfg->NZCL_f.NWS = 2u; + break; + case NzlcWidth16Cycle: + pstcWfg->NZCL_f.NWS = 3u; + break; + case NzlcWidth32Cycle: + pstcWfg->NZCL_f.NWS = 4u; + break; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + case NzlcWidth64Cycle: + pstcWfg->NZCL_f.NWS = 5u; + break; + case NzlcWidth128Cycle: + pstcWfg->NZCL_f.NWS = 6u; + break; + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + case NzlcWidth256Cycle: + pstcWfg->NZCL_f.NWS = 7u; + break; + #endif + #endif + default: + return ErrorInvalidParameter ; + } + + if(&MFT0_WFG == pstcWfg) + { + bFM_GPIO_EPFR01_DTTI0C = pstcNzclConfig->bSwitchToGpio; + } + #if(defined(FM_MFT1)) + else if (&MFT1_WFG == pstcWfg) + { + bFM_GPIO_EPFR02_DTTI1C = pstcNzclConfig->bSwitchToGpio; + } + #endif + #if(defined(FM_MFT2)) + else if(&MFT2_WFG == pstcWfg) + { + bFM_GPIO_EPFR03_DTTI2C = pstcNzclConfig->bSwitchToGpio; + } + #endif + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcWfg->NZCL_f.DIMA = ((pstcNzclConfig->bDtifDigitalFilterIrqMask == TRUE) ? 1u : 0u); + pstcWfg->NZCL_f.DIMB = ((pstcNzclConfig->bDtifAnalogFilterIrqMask == TRUE) ? 1u : 0u); + #endif + + pstcWfgInternData->pfnDtifDigtalFilterIrqCallback = pstcNzclConfig->pfnDtifDigtalFilterIrqCallback; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcWfgInternData->pfnDtifAnalogFilterIrqCallback = pstcNzclConfig->pfnDtifAnalogFilterIrqCallback; + #endif + + if(TRUE == bTouchNvic) + { + MftWfgInitNvic(pstcWfg); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize NZCL of waveform generator + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** \param [in] bTouchNvic Disable NVIC or not + ** \arg TRUE Disable NVIC + ** \arg FALSE Don't disable NVIC + ** + ** \retval Ok NZCL is cleared + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** + ******************************************************************************/ +en_result_t Mft_Wfg_Nzcl_DeInit(volatile stc_mftn_wfg_t* pstcWfg, boolean_t bTouchNvic) +{ + if(NULL == pstcWfg) + { + return ErrorInvalidParameter; + } + + pstcWfg->NZCL = 0u; + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) + if(TRUE == bTouchNvic) + { + MftWfgDeInitNvic(pstcWfg); + } +#endif + + return Ok; +} + +/*! + ****************************************************************************** + ** \brief set software trigger DTIF + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval Ok DTIF is triggered by software + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_Nzcl_SwTriggerDtif( volatile stc_mftn_wfg_t* pstcWfg) +{ + // Check for NULL pointer + if (NULL == pstcWfg) + { + return ErrorInvalidParameter ; + } + + pstcWfg->NZCL_f.SDTI = 1u; + return Ok; +} + +/*! + ****************************************************************************** + ** \brief get Digital filter interrupt flag + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval PdlClr Digital Filter interrupt flag is clear + ** \retval PdlSet Digital Filter interrupt flag is set + ** + ***************************************************************************** +*/ +en_irq_flag_t Mft_Wfg_Nzcl_GetDigitalFilterIrqFlag( volatile stc_mftn_wfg_t* pstcWfg) +{ + en_irq_flag_t enFlag = PdlClr; + + //get interrupt flag via digital noise-canceler + (pstcWfg->WFIR_f.DTIFA == 1u) ? (enFlag = PdlSet) : (enFlag = PdlClr); + + return enFlag; +} + +/*! + ****************************************************************************** + ** \brief clear Digital filter interrupt flag + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval Ok Digital filter interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_Nzcl_ClrDigitalFilterIrqFlag( volatile stc_mftn_wfg_t* pstcWfg) +{ + // Check for NULL pointer + if ( NULL == pstcWfg ) + { + return ErrorInvalidParameter ; + } + + pstcWfg->WFIR_f.DTICA = 1u; + + return Ok; +} + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/*! + ****************************************************************************** + ** \brief get Analog Filter interrupt flag + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval PdlClr Analog Filter interrupt flag is clear + ** \retval PdlSet Analog Filter interrupt flag is set + ** + ***************************************************************************** +*/ +en_irq_flag_t Mft_Wfg_Nzcl_GetAnalogFilterIrqFlag( volatile stc_mftn_wfg_t* pstcWfg) +{ + en_irq_flag_t enFlag; + + //get interrupt flag via analog noise filter + (pstcWfg->WFIR_f.DTIFB == 1u) ? (enFlag = PdlSet) : (enFlag = PdlClr); + + return enFlag; +} +/*! + ****************************************************************************** + ** \brief clear Analog Filter interrupt flag + ** + ** \param [in] pstcWfg Pointer to WFG instance + ** + ** \retval Ok Analog Filter interrupt flag is clear + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMft == NULL + ** - u8CoupleCh out of range + ** + ***************************************************************************** +*/ +en_result_t Mft_Wfg_Nzcl_ClrAnalogFilterIrqFlag( volatile stc_mftn_wfg_t* pstcWfg) +{ + // Check for NULL pointer + if ( NULL == pstcWfg ) + { + return ErrorInvalidParameter ; + } + + pstcWfg->WFIR_f.DTICB = 1u; + + return Ok; +} + +#endif + +#endif // #if (defined(PDL_PERIPHERAL_$$X_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_wfg.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_wfg.h new file mode 100644 index 0000000000..6e7ccd391a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/mft/mft_wfg.h @@ -0,0 +1,419 @@ +/******************************************************************************* +* \file mft_wfg.h +* +* \version 1.20 +* +* \brief Headerfile for MFT_WFG functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __MFT_WFG_H__ +#define __MFT_WFG_H__ + +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_MFT_WFG_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupMFT_WFG Waveform Generator (MFT WFG) +* \{ +* \defgroup GroupMFT_WFG_Macros Macros +* \defgroup GroupMFT_WFG_Functions Functions +* \defgroup GroupMFT_WFG_GlobalVariables Global Variables +* \defgroup GroupMFT_WFG_DataStructures Data Structures +* \defgroup GroupMFT_WFG_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupMFT_WFG +* \{ +* The Waveform Generator (WFG) is part of the Multi-function Timer (MFT). The MFT is a collection +* of peripherals used primarily for motor control. There may be up to three MFTs supported on a +* particular FM microcontroller. One MFT can control a 3-phase motor. A microcontroller that +* supports multiple MFTs can control multiple 3-phase motors.
+* The peripherals in the MFT are:
+* - Free-run Timer (FRT) +* - Output Compare Unit (OCU) +* - Waveform Generator (WFG) +* - Input Capture Unit (ICU) +* - ADC Start Compare (ADCMP)
+* The WFG generates signals on the RTO output pins. There are three WFGs in each MFT instance, +* corresponding to the three OCUs. Each OCU (2 channels each) is connected directly to a WFG. +* Each channel of the OCU generates an RTO signal (RTO0-RTO5) through the WFG.
+* Depending on the WFG mode, the WFG can
+* - Generate the waveform signals based on input from the OCU (Through mode) +* - Superimpose a signal from the Programmable Pulse Generator (PPG) onto the +* signals from the OCU (RT-PPG mode) +* - Bypass the OCU and generate signals using only the PPG (Timer-PPG mode)
+* Superimposing a PPG signal requires a gate-signal.
+* The WFG can automatically insert dead time when switching the RTO signals. Dead time is +* the amount of time inserted between turning off one output, and turning on the next, +* to prevent shoot-through (where the power signal has a direct path to ground). +* In dead time operating modes, you specify the amount of time to insert.
+* The WFG also supports a function block called the noise canceller (NZCL). +* You can use the NZCL to implement emergency stop for a motor.
+* See the Peripheral Manual – Timer Subsystem for more information. +* \section SectionMFT_WFG_ConfigurationConsideration Configuration Consideration +* You must set up other peripherals first. Which peripherals depends upon the WFG’s mode of operation. +* For information about how to set up and initialize another peripheral, see the documentation +* for that peripheral.
+* For Through mode, initialize the FRT and OCU first. For how to configure FRT, see the description in the \link GroupMFT_FRT MFT FRT \endlink. +* For how to configure OCU, see the description in the \link GroupMFT_OCU MFT OCU \endlink.
+* For operating modes that require a PPG, (e.g. RT-PPG, timer-PPG), initialize the PPG peripheral. +* For how to configure PPG, see the description in the \link GroupPPG PPG\endlink.
+* In all modes, you then set the fields in an stc_wfg_config_t structure, such as the mode of +* operation and the behavior of the RTO signals (inverted or not). Then call Mft_Wfg_Init() +* with the configured structure.
+* If you are using an operating mode that inserts dead time, call Mft_Wfg_WriteTimerCountCycle() to +* specify the amount of dead time to insert.
+* Finally start/enable all the peripherals required for your operating mode.
+* To set up the WFG NZCL (used for motor emergency shutdown) you provide configuration +* parameters in the stc_wfg_nzcl_config_t structure. For example, you can use an analog +* noise filter and/or a digital noise filter to filter the signal input from the DTTIX pin. +* You also provide interrupt handling routines. Then call Mft_Wfg_Nzcl_Init(). +* Use Mft_Wfg_Nzcl_SwTriggerDtif() to trigger the DTIF interrupt by software, regardless +* of DTTIX pin input status. With polling mode, there are API function calls to get and clear +* either the analog or digital interrupt flags. +* +* \section SectionMFT_WFG_MoreInfo More Information +* For more information on the MFT WFG peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupMFT_WFG_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_mftn_wfg_t FM_MFT_WFG_TypeDef + +#define MFT0_WFG (*((volatile stc_mftn_wfg_t *) FM_MFT0_WFG_BASE)) +#define MFT1_WFG (*((volatile stc_mftn_wfg_t *) FM_MFT1_WFG_BASE)) +#define MFT2_WFG (*((volatile stc_mftn_wfg_t *) FM_MFT2_WFG_BASE)) + +#define MFT_WFG_CH0 0u +#define MFT_WFG_CH1 1u +#define MFT_WFG_CH2 2u +#define MFT_WFG_CH3 3u +#define MFT_WFG_CH4 4u +#define MFT_WFG_CH5 5u + +#define MFT_WFG_CH10 0u +#define MFT_WFG_CH32 1u +#define MFT_WFG_CH54 2u +#define MFT_WFG_MAXCH 3u + +#define WFG_INSTANCE_COUNT (PDL_PERIPHERAL_ENABLE_MFT0_WFG == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_MFT1_WFG == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_MFT2_WFG == PDL_ON ? 1u : 0u) + +/** \} GroupMFT_WFG_Macros */ + +/** +* \addtogroup GroupMFT_WFG_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each WFG instance + ******************************************************************************/ +typedef enum en_wfg_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_MFT0_WFG == PDL_ON) + WfgInstanceIndexWfg0 = 0u, ///< Instance index of WFG0 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT1_WFG == PDL_ON) + WfgInstanceIndexWfg1, ///< Instance index of WFG1 +#endif +#if (PDL_PERIPHERAL_ENABLE_MFT2_WFG == PDL_ON) + WfgInstanceIndexWfg2, ///< Instance index of WFG2 +#endif + +} en_wfg_instance_index_t; + +/****************************************************************************** + * \brief WFG operation mode + ******************************************************************************/ +typedef enum en_mft_wfg_mode +{ + WfgThroughMode = 0u, ///< through mode + WfgRtPpgMode = 1u, ///< RT-PPG mode + WfgTimerPpgMode = 2u, ///< Timer-PPG mode + WfgRtDeadTimerMode = 4u, ///< RT-dead timer mode + WfgRtDeadTimerFilterMode = 5u, ///< RT-dead timer filter mode + WfgPpgDeadTimerFilterMode = 6u, ///< PPG-dead timer filter mode + WfgPpgDeadTimerMode = 7u, ///< PPG-dead timer mode + +}en_mft_wfg_mode_t; + +/****************************************************************************** + * \brief Enumeration of GTEN bits setting + ******************************************************************************/ +typedef enum en_gten_bits +{ + GtenBits00B = 0u, ///< GTEN == b'00 No CH_GATE signal output + GtenBits01B = 1u, ///< GTEN == b'01 Outputs channel 0 + GtenBits10B = 2u, ///< GTEN == b'10 Outputs channel 1 + GtenBits11B = 3u, ///< GTEN == b'11 Outputs the logic OR of signals + +}en_gten_bits_t; + +/****************************************************************************** + * \brief Enumeration of PSEL bits setting + ******************************************************************************/ +typedef enum en_psel_bits +{ + PselBits00B = 0u, ///< PSEL == b'00 Ch.0 of PPG is connected to for WFG + PselBits01B = 1u, ///< PSEL == b'01 Ch.2 of PPG is connected to for WFG + PselBits10B = 2u, ///< PSEL == b'10 Ch.4 of PPG is connected to for WFG + PselBits11B = 3u, ///< PSEL == b'11 Prohobited value + +}en_psel_bits_t; + +/****************************************************************************** + * \brief Enumeration of PGEN bits setting + ******************************************************************************/ +typedef enum en_pgen_bits +{ + PgenBits00B = 0u, ///< PGEN == b'00 No CH_PPG signal input; RTO0=RT0, RTO1=RT1 + PgenBits01B = 1u, ///< PGEN == b'01 PPG: RTO0=RT0&PPG0, RTO1=RT1 + PgenBits10B = 2u, ///< PGEN == b'10 PPG: RTO0=RT0, RTO1=RT1&PPG0 + PgenBits11B = 3u, ///< PGEN == b'11 PPG: RTO0=RT0&PPG0, RTO1=RT1&PPG0 + +}en_pgen_bits_t; + +/****************************************************************************** + * \brief Enumeration of DMOD bit setting + ******************************************************************************/ +typedef enum en_dmod_bits +{ + DmodBits00B = 0u, ///< output RTO1 and RTO0 signals without changing the level + DmodBits01B = 1u, ///< output both RTO1 and RTO0 signals reversed +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + DmodBits10B = 2u, ///< Outputs the RTO(0) signal reversed, outputs the RTO(1) signal without changing the level. + DmodBits11B = 3u, ///< Outputs the RTO(0) signal without changing the level, Outputs the RTO(1 ) signal reversed. +#endif +}en_dmod_bits_t; + +/****************************************************************************** + * \brief Enumeration to set count clock prescaler + ******************************************************************************/ +typedef enum en_wfg_timer_clock +{ + WfgPlckDiv1 = 0u, ///< WFG timer clock prescaler: None + WfgPlckDiv2 = 1u, ///< WFG timer clock prescaler: 1/2 + WfgPlckDiv4 = 2u, ///< WFG timer clock prescaler: 1/4 + WfgPlckDiv8 = 3u, ///< WFG timer clock prescaler: 1/8 + WfgPlckDiv16 = 4u, ///< WFG timer clock prescaler: 1/16 + WfgPlckDiv32 = 5u, ///< WFG timer clock prescaler: 1/32 + WfgPlckDiv64 = 6u, ///< WFG timer clock prescaler: 1/64 +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + WfgPlckDiv128 = 7u, ///< WFG timer clock prescaler: 1/128 +#endif +}en_wfg_timer_clock_t; + +/****************************************************************************** + * brief noise canceling width for a digital noise-canceler + ******************************************************************************/ +typedef enum en_nzcl_filter_width +{ + NzlcNoFilter, ///< no noise-canceling + NzlcWidth4Cycle, ///< 4 PCLK cycles + NzlcWidth8Cycle, ///< 8 PCLK cycles + NzlcWidth16Cycle, ///< 16 PCLK cycles + NzlcWidth32Cycle, ///< 32 PCLK cycles +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + NzlcWidth64Cycle, ///< 64 PCLK cycles + NzlcWidth128Cycle, ///< 128 PCLK cycles + #if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + NzlcWidth256Cycle, ///< 256 PCLK cycles + #endif +#endif + +}en_nzcl_filter_width_t; + +/** \} GroupMFT_WFG_Types */ + +/** +* \addtogroup GroupMFT_WFG_DataStructures +* \{ +*/ + +/****************************************************************************** + * \brief Configuration structure of waveform generator + ******************************************************************************/ +typedef struct stc_wfg_config +{ + en_mft_wfg_mode_t enMode; ///< select the output condition + en_gten_bits_t enGtenBits; ///< select the output condition + en_psel_bits_t enPselBits; ///< select the PPG timer unit + en_pgen_bits_t enPgenBits; ///< how to reflect the CH_PPG signal + en_dmod_bits_t enDmodBits; ///< polarity for RTO0 and RTO1 signal output + + en_wfg_timer_clock_t enClk; ///< clock division of WFG timer + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bWfgimerIrqMask; ///< TRUE: mask timer interrupt, FALSE: don't mask timer interrupt + #endif + func_ptr_t pfnWfgTimerIrqCallback; ///< Poitner to WFG timer callback function + boolean_t bTouchNvic; ///< TRUE: enable WFG NVIC, FALSE, don't enable WFG NVIC +#endif + +}stc_wfg_config_t; + +/****************************************************************************** + * \brief WFG internal data + ******************************************************************************/ +typedef struct stc_mft_wfg_intern_data +{ + func_ptr_t pfnWfg10TimerIrqCallback; ///< Callback function pointer of WFG10 timer interrupt callback + func_ptr_t pfnWfg32TimerIrqCallback; ///< Callback function pointer of WFG32 timer interrupt callback + func_ptr_t pfnWfg54TimerIrqCallback; ///< Callback function pointer of WFG54 timer interrupt callback + func_ptr_t pfnDtifAnalogFilterIrqCallback; ///< Callback function pointer of analog filter interrupt callback + func_ptr_t pfnDtifDigtalFilterIrqCallback; ///< Callback function pointer of digital filter interrupt callback +}stc_mft_wfg_intern_data_t; + +/****************************************************************************** + * brief NZCL configure + ******************************************************************************/ +typedef struct stc_wfg_nzcl_config +{ + boolean_t bEnDigitalFilter; ///< enable digital filter + en_nzcl_filter_width_t enDigitalFilterWidth; ///< digital filter width +#if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bEnAnalogFilter; ///< enable analog filter + #if(PDL_MCU_TYPE >= PDL_FM4_TYPE3) + boolean_t bHoldRto; ///< TRUE: hold RTO when DTIF interrupt occurs, FALSE: don't hold RTO when DTIF interrupt occurs + #endif +#endif + boolean_t bSwitchToGpio; ///< switch to GPIO + +#if (PDL_INTERRUPT_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_MFT2_WFG == PDL_ON) + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bDtifDigitalFilterIrqMask; ///< Digital filter interrupt selection + boolean_t bDtifAnalogFilterIrqMask; ///< Analog filter interrupt selection + #endif + + func_ptr_t pfnDtifDigtalFilterIrqCallback; ///< Pointer to digital filter interrupt callback function + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + func_ptr_t pfnDtifAnalogFilterIrqCallback; ///< Pointer to analog filter interrupt callback function + #endif + + boolean_t bTouchNvic; ///< TRUE: +#endif + +}stc_wfg_nzcl_config_t; + +/****************************************************************************** + * brief structure of WFG instance data + ******************************************************************************/ +typedef struct stc_mft_wfg_instance_data +{ + volatile stc_mftn_wfg_t* pstcInstance; ///< pointer to registers of an instance + stc_mft_wfg_intern_data_t stcInternData; ///< module internal data of instance +} stc_mft_wfg_instance_data_t; + +/** \} GroupMFT_WFG_DataStructures */ + +/** +* \addtogroup GroupMFT_WFG_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/// Look-up table for all enabled WFG instances and their internal data +extern stc_mft_wfg_instance_data_t m_astcMftWfgInstanceDataLut[WFG_INSTANCE_COUNT]; + +/** \} GroupMFT_WFG_GlobalVariables */ + +/** +* \addtogroup GroupMFT_WFG_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +/* 1. WFG function configuration */ +en_result_t Mft_Wfg_Init(volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, + const stc_wfg_config_t* pstcConfig); +en_result_t Mft_Wfg_DeInit(volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, + boolean_t bTouchNvic); + +en_result_t Mft_Wfg_StartTimer(volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh); +en_result_t Mft_Wfg_StopTimer(volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh); +en_irq_flag_t Mft_Wfg_GetTimerIrqFlag(volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh); +en_result_t Mft_Wfg_ClrTimerIrqFlag(volatile stc_mftn_wfg_t* pstcWfg, uint8_t u8CoupleCh); +en_result_t Mft_Wfg_WriteTimerCountCycle(volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, + uint16_t u16CycleA, + uint16_t u16CycleB); +#if(PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +en_result_t Mft_Wfg_SetFilterCountValue( volatile stc_mftn_wfg_t* pstcWfg, + uint8_t u8CoupleCh, uint16_t u16Count); +#endif +/* 2. WFG NZCL configuration */ +en_result_t Mft_Wfg_Nzcl_Init(volatile stc_mftn_wfg_t* pstcWfg, + stc_wfg_nzcl_config_t* pstcNzclConfig, + boolean_t bTouchNvic); +en_result_t Mft_Wfg_Nzcl_DeInit(volatile stc_mftn_wfg_t* pstcWfg, + boolean_t bTouchNvic); +en_result_t Mft_Wfg_Nzcl_SwTriggerDtif(volatile stc_mftn_wfg_t* pstcWfg); +en_irq_flag_t Mft_Wfg_Nzcl_GetDigitalFilterIrqFlag(volatile stc_mftn_wfg_t* pstcWfg); +en_result_t Mft_Wfg_Nzcl_ClrDigitalFilterIrqFlag(volatile stc_mftn_wfg_t* pstcWfg); +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +en_irq_flag_t Mft_Wfg_Nzcl_GetAnalogFilterIrqFlag(volatile stc_mftn_wfg_t* pstcWfg); +en_result_t Mft_Wfg_Nzcl_ClrAnalogFilterIrqFlag(volatile stc_mftn_wfg_t* pstcWfg); +#endif + +/* 3. IRQ handler */ +void Mft_Wfg_IrqHandler(volatile stc_mftn_wfg_t* pstcWfg, + stc_mft_wfg_intern_data_t* pstcMftWfgInternData) ; + +/** \} GroupMFT_WFG_Functions */ +/** \} GroupMFT_WFG */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_ADC_ACTIVE)) +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pcrc/pcrc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pcrc/pcrc.c new file mode 100644 index 0000000000..bdd3d2e723 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pcrc/pcrc.c @@ -0,0 +1,394 @@ +/******************************************************************************* +* \file pcrc.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the +* Programmable CRC driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pcrc/pcrc.h" + +#if (defined(PDL_PERIPHERAL_PCRC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_PCRC == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl_user.h + ** + ******************************************************************************/ +static void PcrcInitNvic(void); + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ******************************************************************************/ +static void PcrcDeInitNvic(void); +#endif + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_PCRC == PDL_ON) +static func_ptr_t m_pfnPcrcIrqCb = NULL; +#endif + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +#if (PDL_INTERRUPT_ENABLE_PCRC == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl.h + ** + ******************************************************************************/ +static void PcrcInitNvic(void) +{ + NVIC_ClearPendingIRQ(PCRC_I2S0_1_IRQn); + NVIC_EnableIRQ(PCRC_I2S0_1_IRQn); + NVIC_SetPriority(PCRC_I2S0_1_IRQn, PDL_IRQ_LEVEL_I2S_PCRC); + + return; +} + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS + ** + ******************************************************************************/ +static void PcrcDeInitNvic(void) +{ + NVIC_ClearPendingIRQ(PCRC_I2S0_1_IRQn); + NVIC_DisableIRQ(PCRC_I2S0_1_IRQn); + NVIC_SetPriority(PCRC_I2S0_1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + + return; +} + +/** + ****************************************************************************** + ** \brief ISR of the PCRC module + ** + ******************************************************************************/ +void PcrcIrqHandler(void) +{ + if(FM_PCRC->PCRC_CFG_f.CIRQ) + { + FM_PCRC->PCRC_CFG_f.CIRQCLR = 1u; + if(NULL != m_pfnPcrcIrqCb) + { + m_pfnPcrcIrqCb(); + } + } + + return; +} +#endif + +/** + ****************************************************************************** + ** \brief Initialisation of a Programmable CRC module. + ** + ** \param pstcConfig CRC module configuration + ** + ** \retval Ok Initializiation of Programmable CRC module successfully + ** done. + ** \retval ErrorInvalidParameter If one of following cases match: + ** - pstcConfig == NULL, + ** - parameter out of range + ******************************************************************************/ +en_result_t Pcrc_Init(const stc_pcrc_config_t* pstcConfig) +{ + en_result_t enResult; + stc_pcrc_pcrc_cfg_field_t PCRC_CFG_f; + + PDL_ZERO_STRUCT(PCRC_CFG_f); + + /* Check for valid pointers and configrue parameters */ + if ((NULL == pstcConfig) || + (pstcConfig->enInputFormat > LsbFirstLittleEndian) || + (pstcConfig->enOutputFormat > LsbFirstLittleEndian) || + (pstcConfig->enInputDataSize > InputData32Bit)) + { + enResult = ErrorInvalidParameter; + } + else + { + PCRC_CFG_f.FI = pstcConfig->enInputFormat; + PCRC_CFG_f.FO = pstcConfig->enOutputFormat; + PCRC_CFG_f.SZ = pstcConfig->enInputDataSize; + PCRC_CFG_f.TEST = 0x20u; //Always writes "100000" to perform write access to this register. + + /* Update hardware */ + FM_PCRC->PCRC_POLY = pstcConfig->u32GeneratorPolynomial; + FM_PCRC->PCRC_SEED = pstcConfig->u32CrcInitValue; + FM_PCRC->PCRC_FXOR = pstcConfig->u32FinalXorValue; + FM_PCRC->PCRC_CFG_f = PCRC_CFG_f; + FM_PCRC->PCRC_CFG_f.CDEN = ((pstcConfig->bUseDstc == TRUE) ? 1u : 0u); + +#if (PDL_INTERRUPT_ENABLE_PCRC== PDL_ON) + m_pfnPcrcIrqCb = pstcConfig->pfnIrqCb; + FM_PCRC->PCRC_CFG_f.CIRQCLR = 1u; + FM_PCRC->PCRC_CFG_f.CIEN = ((pstcConfig->bIrqEn == TRUE) ? 1u : 0u); + // Initialize NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + PcrcInitNvic(); + } +#endif + enResult = Ok; + } + + return (enResult); +} + +/** + ****************************************************************************** + ** \brief Re-Initialisation of a Programmable CRC module. + ******************************************************************************/ +void Pcrc_DeInit(void) +{ +#if (PDL_INTERRUPT_ENABLE_PCRC == PDL_ON) + PcrcDeInitNvic(); +#endif + /* clear hardware */ + FM_PCRC->PCRC_WR = 0u; + FM_PCRC->PCRC_POLY = 0u; + FM_PCRC->PCRC_SEED = 0u; + FM_PCRC->PCRC_FXOR = 0u; + FM_PCRC->PCRC_CFG = 0u; + + return; +} + +/** + ****************************************************************************** + ** \brief Set CRC computing initial value. + ** + ** \param u32InitialValue: CRC initial value + ** + ******************************************************************************/ +void Pcrc_SetInitialValue(uint32_t u32InitialValue) +{ + FM_PCRC->PCRC_SEED = u32InitialValue; + + return; +} + +/** + ****************************************************************************** + ** \brief Set CRC computing result XOR value. + ** + ** \param u32FinalXorValue: result XOR value + ** + ******************************************************************************/ +void Pcrc_SetFinalXorValue(uint32_t u32FinalXorValue) +{ + FM_PCRC->PCRC_FXOR = u32FinalXorValue; + + return; +} + +/** + ****************************************************************************** + ** \brief Set CRC output data Format. + ** + ** \param enOutputDataFormat: CRC output data Format + ** + ******************************************************************************/ +void Pcrc_SetOutputDataFormat(en_crc_data_format_t enOutputDataFormat) +{ + FM_PCRC->PCRC_CFG_f.FO = enOutputDataFormat; + + return; +} + +/** + ****************************************************************************** + ** \brief Set CRC input data Format. + ** + ** \param enInputDataFormat: CRC input data Format + ** + ******************************************************************************/ +void Pcrc_SetInputDataFormat(en_crc_data_format_t enInputDataFormat) +{ + FM_PCRC->PCRC_CFG_f.FI = enInputDataFormat; + + return; +} + +/** + ****************************************************************************** + ** \brief Set CRC input data size. + ** + ** \param enInputDataSize: CRC input data size + ** + ******************************************************************************/ +void Pcrc_SetInputDataSize(en_crc_input_data_size_t enInputDataSize) +{ + FM_PCRC->PCRC_CFG_f.SZ = enInputDataSize; + + return; +} + +/** + ****************************************************************************** + ** \brief Set TEST field of CRC Computing Configuration Register + ** + ** \param u8CfgTest: TEST field value. + ** The correct operation is not achieved if perform writing values other + ** than "100000" to the TEST[5:0] register + ** + ******************************************************************************/ +void Pcrc_SetCfgTest(uint8_t u8CfgTest) +{ + FM_PCRC->PCRC_CFG_f.TEST = u8CfgTest; + + return; +} + +/** + ****************************************************************************** + ** \brief Get CRC interrupt request flag. + ** + ** \retval PRGCRC Interrupt request flag + ** + ******************************************************************************/ +uint8_t Pcrc_GetIntRequestFlag(void) +{ + return (FM_PCRC->PCRC_CFG_f.CIRQ); +} + +/** + ****************************************************************************** + ** \brief Enable CRC interrupt request. + ******************************************************************************/ +void Pcrc_EnableIntRequest(void) +{ + FM_PCRC->PCRC_CFG_f.CIEN = 1u; + + return; +} + +/** + ****************************************************************************** + ** \brief Disable CRC interrupt request. + ******************************************************************************/ +void Pcrc_DisableIntRequest(void) +{ + FM_PCRC->PCRC_CFG_f.CIEN = 0u; + + return; +} + +/** + ****************************************************************************** + ** \brief Allows the transfer request of input data for DMA. + ******************************************************************************/ +void Pcrc_EnableDmaTx(void) +{ + FM_PCRC->PCRC_CFG_f.CDEN = 1u; + + return; +} + +/** + ****************************************************************************** + ** \brief Disable the transfer request of input data for DMA. + ******************************************************************************/ +void Pcrc_DisableDmaTx(void) +{ + FM_PCRC->PCRC_CFG_f.CDEN = 0u; + + return; +} + +/** + ****************************************************************************** + ** \brief Get CRC computing unit state. + ** + ** \retval 1 : Indicates the CRC computing unit is in busy state + ** \retval 0 : Indicates the CRC computing unit is in idle state. + ** + ******************************************************************************/ +uint8_t Pcrc_GetLockStatus(void) +{ + return ((FM_PCRC->PCRC_CFG_f.LOCK == 1u) ? 1u : 0u); +} + +/** + ****************************************************************************** + ** \brief Clear RGCRC Interrupt request. + ******************************************************************************/ +void Pcrc_ClrIntRequest(void) +{ + /* Caluculate CRC (Push 8bit data) */ + FM_PCRC->PCRC_CFG_f.CIRQCLR = 1u; + + return; +} + +/** + ****************************************************************************** + ** \brief Write computing input data. + ** + ** \param u32WriteData: input data value + ** + ******************************************************************************/ +void Pcrc_WriteData(uint32_t u32WriteData) +{ + FM_PCRC->PCRC_WR = u32WriteData; + + return; +} + +/** + ****************************************************************************** + ** \brief Get computing output data. + ** + ** \retval output data value + ** + ******************************************************************************/ +uint32_t Pcrc_ReadResult(void) +{ + return (FM_PCRC->PCRC_RD); +} + +#endif /* #if (defined(PDL_PERIPHERAL_PCRC_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pcrc/pcrc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pcrc/pcrc.h new file mode 100644 index 0000000000..94137d949d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pcrc/pcrc.h @@ -0,0 +1,208 @@ +/******************************************************************************* +* \file pcrc.h +* +* \version 1.20 +* +* \brief Headerfile for Programmable CRC functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __PCRC_H__ +#define __PCRC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_PCRC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupPCRC Programmable Cyclic Redundancy Check (PCRC) +* \{ +* \defgroup GroupPCRC_Functions Functions +* \defgroup GroupPCRC_DataStructures Data Structures +* \defgroup GroupPCRC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupPCRC +* \{ +* Use the Programmable CRC (PCRC) peripheral to compute CRC values using an +* arbitrary generator polynomial on the input data. By contrast, the CRC +* peripheral supports defined standards with fixed generator polynomials.
+* PCRC is available in FM4 devices types 3 and 4. Other FM devices do not +* support programmable CRC. Check the datasheet for your device to determine whether +* PCRC is supported.
+* PCRC supports these features: +* * Arbitrary CRC generator polynomial (CRC values length up to 32-bit) +* * Arbitrary seed value for CRC computing +* * Choice of input data width can be 8-, 16-, 24-, or 32-bit +* * Choice of input data format (byte/bit order) +* * Choice of output data format (byte/bit order) +* * Arbitrary value for bitwise XOR +* * Interrupt notification when CRC calculation is complete +* * Data input using hardware DMA via DSTC
+* For byte/bit ordering, you have four choices. The bits in a byte can be in least +* significant bit or most significant bit order. The bytes can be ordered as big-endian +* or little-endian. +* \section SectionPCRC_ConfigurationConsideration Configuration Consideration +* To set up the PCRC you provide configuration parameters in the stc_pcrc_config_t +* structure. For example you specify the generator polynomial, the data formats, +* the data size, and so on. Then call Pcrc_Init().
+* At runtime use API function calls to: +* * Set the initial seed value +* * Set the input or output data format +* * Set the input data size +* * Enable or disable interrupts +* * Write data to calculate the CRC +* * Read the result
+* To calculate a CRC, call Pcrc_WriteData() repeatedly until you have pushed all the of +* input data into the calculation. You should check whether CRC is busy before every call +* to Pcrc_WriteData(). Use Pcrc_GetLockStatus().
+* When done, use Pcrc_ReadResult() to get the result. +* +* \section SectionPCRC_MoreInfo More Information +* For more information on the PCRC peripheral, refer to:
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** +* \addtogroup GroupPCRC_Types +* \{ +*/ + +/** + ***************************************************************************** + ** \brief Programmable Crc data format + *****************************************************************************/ +typedef enum en_crc_data_format +{ + MsbFirstBigEndian = 0u, ///< MSB-first / Big endian is selected for output format conversion. + MsbFirstLittleEndian = 1u, ///< MSB-first / Little endian is selected for output format conversion. + LsbFirstBigEndian = 2u, ///< LSB-first / Big endian is selected for output format conversion. + LsbFirstLittleEndian = 3u, ///< LSB-first / Little endian is selected for output format conversion. +} en_crc_data_format_t; + +/** + ***************************************************************************** + ** \brief Programmable Crc input data size + *****************************************************************************/ +typedef enum en_crc_input_data_size +{ + InputData8Bit = 0u, ///< 8-bit input data size is selected. + InputData16Bit = 1u, ///< 16-bit input data size is selected. + InputData24Bit = 2u, ///< 24-bit input data size is selected. + InputData32Bit = 3u, ///< 32-bit input data size is selected. +} en_crc_input_data_size_t; + +/** \} GroupPCRC_Types */ + +/** +* \addtogroup GroupPCRC_DataStructures +* \{ +*/ + +/** + ***************************************************************************** + ** \brief Programmable Crc configuration + *****************************************************************************/ +typedef struct stc_pcrc_config +{ + uint32_t u32GeneratorPolynomial; ///< CRC Computing Generator Polynomial + en_crc_data_format_t enInputFormat; ///< Input data format + en_crc_data_format_t enOutputFormat; ///< Output data format + en_crc_input_data_size_t enInputDataSize; ///< Input data size + uint32_t u32CrcInitValue; ///< Initial value + uint32_t u32FinalXorValue; ///< Specifies the value of XOR (exclusive OR) for final results of CRC computing. + + boolean_t bUseDstc; ///< TRUE: the transfer request of input data for DMA. +#if (PDL_INTERRUPT_ENABLE_PCRC== PDL_ON) + boolean_t bIrqEn; ///< TRUE: Interrupt request enable. + func_ptr_t pfnIrqCb; ///< Interrupt request callback funciton + boolean_t bTouchNvic; +#endif +} stc_pcrc_config_t; + +/** \} GroupPCRC_DataStructures */ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupPCRC_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +#if (PDL_INTERRUPT_ENABLE_PCRC == PDL_ON) +void PcrcIrqHandler(void); +#endif +en_result_t Pcrc_Init(const stc_pcrc_config_t* pstcConfig); +void Pcrc_DeInit(void); +void Pcrc_SetInitialValue(uint32_t u32InitialValue); +void Pcrc_SetFinalXorValue(uint32_t u32FinalXorValue); +void Pcrc_SetOutputDataFormat(en_crc_data_format_t enOutputDataFormat); +void Pcrc_SetInputDataFormat(en_crc_data_format_t enInputDataFormat); +void Pcrc_SetInputDataSize(en_crc_input_data_size_t enInputDataSize); +void Pcrc_SetCfgTest(uint8_t u8CfgTest); +uint8_t Pcrc_GetIntRequestFlag(void); +void Pcrc_EnableIntRequest(void); +void Pcrc_DisableIntRequest(void); +void Pcrc_EnableDmaTx(void); +void Pcrc_DisableDmaTx(void); +uint8_t Pcrc_GetLockStatus(void); +void Pcrc_ClrIntRequest(void); +void Pcrc_WriteData(uint32_t u32WriteData); +uint32_t Pcrc_ReadResult(void); + +/** \} GroupPCRC_Functions */ +/** \} GroupPCRC */ +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_PCRC_ACTIVE)) */ + +#endif /* __PCRC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl.c new file mode 100644 index 0000000000..5e7c63c9e8 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl.c @@ -0,0 +1,81 @@ +/******************************************************************************* +* \file pdl.c +* +* \version 1.0 +* +* \brief Misc helper functions for Peripheral Driver Library. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "pdl.h" + +/** + ****************************************************************************** + ** addtogroup PDL Common Functions + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ***************************************************************************** + ** \brief Memory clear function for PDL_ZERO_STRUCT() + *****************************************************************************/ +void pdl_memclr(uint8_t* pu8Address, uint32_t u32Count) +{ + while(u32Count--) + { + *pu8Address++ = 0; + } +} + +/** + ***************************************************************************** + ** \brief Hook function, which is called in polling loops + *****************************************************************************/ +void PDL_WAIT_LOOP_HOOK(void) +{ + // Place code for triggering Watchdog counters here, if needed +} + +//@} // PDL Functions + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl.h new file mode 100644 index 0000000000..3dc5632b04 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl.h @@ -0,0 +1,285 @@ +/******************************************************************************* +* \file pdl.h +* +* \version 1.0 +* +* \brief Common headerfile for Peripheral Driver Library. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __PDL_H__ +#define __PDL_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/* Macro for initializing local structures to zero */ +/******************************************************************************/ +#define PDL_ZERO_STRUCT(x) pdl_memclr((uint8_t*)&(x), (uint32_t)(sizeof(x))) + +/** + ****************************************************************************** + ** All definitions needed for pdl_user.h are stated here + ******************************************************************************/ +#define PDL_ON 1u ///< Switches a feature on +#define PDL_OFF 0u ///< Switches a feature off + +/** + ****************************************************************************** + ** Global Device type definitions + ** Note that an existing definition does not implicitly means full device + ** type support of this library! + ******************************************************************************/ +// FM0+ device type +#define PDL_FM0P_TYPE0 0100u ///< FM0+ device type0 +#define PDL_FM0P_TYPE1 0101u ///< FM0+ device type1 +#define PDL_FM0P_TYPE2 0102u ///< FM0+ device type2 +#define PDL_FM0P_TYPE3 0103u ///< FM0+ device type3 +#define PDL_FM0P_TYPE4 0104u ///< FM0+ device type4 +#define PDL_FM0P_TYPE5 0105u ///< FM0+ device type5 +#define PDL_FM0P_TYPE6 0106u ///< FM0+ device type6 +#define PDL_FM0P_TYPE7 0107u ///< FM0+ device type7 +#define PDL_FM0P_TYPE8 0108u ///< FM0+ device type8 +#define PDL_FM0P_TYPE9 0109u ///< FM0+ device type9 +// FM3 device type +#define PDL_FM3_TYPE0 3000u ///< FM3 device type0 +#define PDL_FM3_TYPE1 3001u ///< FM3 device type1 +#define PDL_FM3_TYPE2 3002u ///< FM3 device type2 +#define PDL_FM3_TYPE3 3003u ///< FM3 device type3 +#define PDL_FM3_TYPE4 3004u ///< FM3 device type4 +#define PDL_FM3_TYPE5 3005u ///< FM3 device type5 +#define PDL_FM3_TYPE6 3006u ///< FM3 device type6 +#define PDL_FM3_TYPE7 3007u ///< FM3 device type7 +#define PDL_FM3_TYPE8 3008u ///< FM3 device type8 +#define PDL_FM3_TYPE9 3009u ///< FM3 device type9 +#define PDL_FM3_TYPE10 3010u ///< FM3 device type10 +#define PDL_FM3_TYPE11 3011u ///< FM3 device type11 +#define PDL_FM3_TYPE12 3012u ///< FM3 device type12 +// FM4 device type +#define PDL_FM4_TYPE0 4000u ///< FM4 device type0 +#define PDL_FM4_TYPE1 4001u ///< FM4 device type1 +#define PDL_FM4_TYPE2 4002u ///< FM4 device type2 +#define PDL_FM4_TYPE3 4003u ///< FM4 device type3 +#define PDL_FM4_TYPE4 4004u ///< FM4 device type4 +#define PDL_FM4_TYPE5 4005u ///< FM4 device type5 +#define PDL_FM4_TYPE6 4006u ///< FM4 device type6 +#define PDL_FM4_TYPE7 4007u ///< FM4 device type7 +#define PDL_FM4_TYPE8 4008u ///< FM4 device type8 +#define PDL_FM4_TYPE9 4009u ///< FM4 device type9 + +#define PDL_MCU_TYPE FM_DEVICE_TYPE // Definition from peripheral header + +/** + ****************************************************************************** + ** Global Device Core list + ******************************************************************************/ +#define PDL_FM0P_CORE 10u +#define PDL_FM3_CORE 20u +#define PDL_FM4_CORE 30u + +#ifdef FM_CORE_TYPE_FM0P // Definition from peripheral header +#define PDL_MCU_CORE PDL_FM0P_CORE +#endif + +#ifdef FM_CORE_TYPE_FM3 // Definition from peripheral header +#define PDL_MCU_CORE PDL_FM3_CORE +#endif + +#ifdef FM_CORE_TYPE_FM4 // Definition from peripheral header +#define PDL_MCU_CORE PDL_FM4_CORE +#endif + +/** + ****************************************************************************** + ** Global Device interrupt list + ******************************************************************************/ + +#if FM_GENERAL_MCUHEADER_VERSION == 0200 + // FM0+ interrupt type + #define PDL_FM0P_INT_TYPE_1_A 0100u + #define PDL_FM0P_INT_TYPE_1_B 0101u + #define PDL_FM0P_INT_TYPE_2_A 0102u + #define PDL_FM0P_INT_TYPE_2_B 0103u + #define PDL_FM0P_INT_TYPE_3 0104u + + // FM3 interrupt type + #define PDL_FM3_INT_TYPE_A 3000u + #define PDL_FM3_INT_TYPE_B 3001u + #define PDL_FM3_INT_TYPE_C 3002u + + // FM4 interrupt type + #define PDL_FM4_INT_TYPE_A 4000u + #define PDL_FM4_INT_TYPE_B 4001u + #define PDL_FM4_INT_TYPE_C 4002u +#elif FM_GENERAL_MCUHEADER_VERSION >= 0201 + // FM0+ interrupt type + #define PDL_FM0P_INT_TYPE_1_A 0x011Au + #define PDL_FM0P_INT_TYPE_1_B 0x011Bu + #define PDL_FM0P_INT_TYPE_2_A 0x012Au + #define PDL_FM0P_INT_TYPE_2_B 0x012Bu + #define PDL_FM0P_INT_TYPE_3 0x0130u + + // FM3 interrupt type + #define PDL_FM3_INT_TYPE_A 0x300Au + #define PDL_FM3_INT_TYPE_B 0x300Bu + #define PDL_FM3_INT_TYPE_C 0x300Cu + + // FM4 interrupt type + #define PDL_FM4_INT_TYPE_A 0x400Au + #define PDL_FM4_INT_TYPE_B 0x400Bu + #define PDL_FM4_INT_TYPE_C 0x400Cu +#else + #error unknown FM_GENERAL_MCUHEADER_VERSION configuration +#endif + +#define PDL_MCU_INT_TYPE FM_INTERRUPT_TYPE // Definition from peripheral header + +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + + #if (PDL_MCU_INT_TYPE == PDL_FM0P_INT_TYPE_1_A) + #define __INTERRUPTS_FM0P_TYPE_1_A_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM0P_INT_TYPE_1_B) + #define __INTERRUPTS_FM0P_TYPE_1_B_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM0P_INT_TYPE_2_A) + #define __INTERRUPTS_FM0P_TYPE_2_A_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM0P_INT_TYPE_2_B) + #define __INTERRUPTS_FM0P_TYPE_2_B_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM0P_INT_TYPE_3) + #define __INTERRUPTS_FM0P_TYPE_3_C__ + + #else + #error Interrupt Type for FM0P not defined! + #endif + +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + + #if (PDL_MCU_INT_TYPE == PDL_FM3_INT_TYPE_A) + #define __INTERRUPTS_FM3_TYPE_A_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM3_INT_TYPE_B) + #define __INTERRUPTS_FM3_TYPE_B_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM3_INT_TYPE_C) + #define __INTERRUPTS_FM3_TYPE_C_C__ + + #else + #error Interrupt Type for FM3 not defined! + #endif + +#elif (PDL_MCU_CORE == PDL_FM4_CORE) + + #if (PDL_MCU_INT_TYPE == PDL_FM4_INT_TYPE_A) + #define __INTERRUPTS_FM4_TYPE_A_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM4_INT_TYPE_B) + #define __INTERRUPTS_FM4_TYPE_B_C__ + + #elif (PDL_MCU_INT_TYPE == PDL_FM4_INT_TYPE_C) + #define __INTERRUPTS_FM4_TYPE_C_C__ + + #else + #error Interrupt Type for FM4 not defined! + #endif + +#else + #error FM core not defined! +#endif + +/******************************************************************************/ +/* User Device Setting Include file */ +/******************************************************************************/ +//#include "pdl_device.h" // MUST be included here! + +/** + ****************************************************************************** + ** Default Interrupt Level (lowest priority, used for De-Init functions) + ******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM3_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) +#define PDL_DEFAULT_INTERRUPT_LEVEL 0x0Fu +#else +#define PDL_DEFAULT_INTERRUPT_LEVEL 0x03u +#endif + +/******************************************************************************/ +/* Global type definitions ('typedef') */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Level + ** + ** Specifies levels. + ** + ******************************************************************************/ +typedef enum en_level +{ + PdlLow = 0u, ///< Low level '0' + PdlHigh = 1u ///< High level '1' +} en_level_t; + +/** + ****************************************************************************** + ** \brief Generic Flag Code + ** + ** Specifies flags. + ** + ******************************************************************************/ +typedef enum en_flag +{ + PdlClr = 0u, ///< Flag clr '0' + PdlSet = 1u ///< Flag set '1' +} en_stat_flag_t, en_irq_flag_t; + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +/****************************************************************************** + * Global function prototypes + ******************************************************************************/ +extern void pdl_memclr(uint8_t* pu32Address, uint32_t u32Count); + +/** + ****************************************************************************** + ** This hook is part of wait loops. + ******************************************************************************/ +extern void PDL_WAIT_LOOP_HOOK(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PDL_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl_header.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl_header.h new file mode 100644 index 0000000000..f1f0cc9e22 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/pdl_header.h @@ -0,0 +1,319 @@ +/******************************************************************************* +* \file pdl_header.h +* +* \version 1.0 +* +* \brief Includes driver header files enabled by PDL_ON / PDL_OFF +* defines in pdl_user.h. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __PDL_HEADER_H__ +#define __PDL_HEADER_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/****************************************************************************** + * Peripheral driver header files inclusion + ******************************************************************************/ +// Include adc.h if ADC is active +#if defined(PDL_PERIPHERAL_ADC_ACTIVE) + #include "adc/adc.h" +#endif + +// Include adc.h if AES is active +#if defined(PDL_PERIPHERAL_AES_ACTIVE) + #include "aes/aes.h" +#endif + +// Include bt.h if BT is active +#if defined(PDL_PERIPHERAL_BT_ACTIVE) + #include "bt/bt.h" +#endif + +// Include can.h if CAN is active +#if defined(PDL_PERIPHERAL_CAN_ACTIVE) + #include "can/can.h" +#endif + +// Include canfd.h if CANFD is active +#if defined(PDL_PERIPHERAL_CANFD_ACTIVE) + #include "can/can_pre.h" + #include "can/canfd.h" +#endif + +// Include clk.h if clock is active +#if defined(PDL_PERIPHERAL_CLK_ACTIVE) + #include "clk/clk.h" +#endif + +// Include cr.h if CR is active +#if defined(PDL_PERIPHERAL_CR_ACTIVE) + #include "cr/cr.h" +#endif + +// Include crc.h if CRC is active +#if defined(PDL_PERIPHERAL_CRC_ACTIVE) + #include "crc/crc.h" +#endif + +// Include csv.h if CSV is active +#if defined(PDL_PERIPHERAL_CSV_ACTIVE) + #include "csv/csv.h" +#endif + +// Activate code in dac.c if one or more are set to PDL_ON +#if defined(PDL_PERIPHERAL_DAC_ACTIVE) + #include "dac/dac.h" +#endif + +// Include dma.h if DMA is active +#if defined(PDL_PERIPHERAL_DMA_ACTIVE) + #include "dma/dma.h" +#endif + +// Include dstc.c if DSTC is active +#if defined(PDL_PERIPHERAL_DSTC_ACTIVE) + #include "dstc/dstc.h" +#endif + +// Include dt.h if DT is active +#if defined(PDL_PERIPHERAL_DT_ACTIVE) + #include "dt/dt.h" +#endif + +// Include exint.h if external interrupt is active +#if defined(PDL_PERIPHERAL_EXINT_ACTIVE) || defined(PDL_PERIPHERAL_NMI_ACTIVE) + #include "exint/exint.h" +#endif + +// Include pcrc.h if programmable crc is active +#if defined(PDL_PERIPHERAL_PCRC_ACTIVE) + #include "pcrc/pcrc.h" +#endif + +// Activate code in extif.c if set to PDL_ON +#if defined(PDL_PERIPHERAL_EXTIF_ACTIVE) + #include "extif/extif.h" +#endif + +// Include dualflash.h if Dual Flash is active +#if defined(PDL_PERIPHERAL_DUAL_FLASH_ACTIVE) + #include "flash/dualflash.h" +#endif + +// Include mainflash.h if Main Flash is active +#if defined(PDL_PERIPHERAL_MAIN_FLASH_ACTIVE) + #include "flash/mainflash.h" +#endif + +// Include mainflash.h if Work Flash is active +#if defined(PDL_PERIPHERAL_WORK_FLASH_ACTIVE) + #include "flash/workflash.h" +#endif + +// Include gpio.h and fgpio.h if GPIO is active +#if defined(PDL_PERIPHERAL_GPIO_ACTIVE) + #include "gpio/gpio.h" +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #include "gpio/fgpio.h" +#endif +#endif + +// Include hsspi.h if HSSPI is active +#if defined(PDL_PERIPHERAL_HSSPI_ACTIVE) + #include "hsspi/hsspi.h" +#endif + +// Include i2cs.h if I2CS is active +#if defined(PDL_PERIPHERAL_I2CS_ACTIVE) + #include "i2cs/i2cs.h" +#endif + +// Include i2s.h if I2S is active +#if defined(PDL_PERIPHERAL_I2S_ACTIVE) + #include "i2s/i2s.h" +#endif + +// Include i2sl.h if I2S is active +#if defined(PDL_PERIPHERAL_I2SL_ACTIVE) + #include "i2sl/i2sl.h" +#endif + +// Include icc.h if ICC is active +#if defined(PDL_PERIPHERAL_ICC_ACTIVE) + #include "icc/icc.h" +#endif + +// Include lpm.h if LPM is active +#if defined(PDL_PERIPHERAL_LPM_ACTIVE) + #include "lpm/lpm.h" +#endif + +// Include lvd.h if LVD is active +#if defined(PDL_PERIPHERAL_LVD_ACTIVE) + #include "lvd/lvd.h" +#endif + +// Include mfs.h if MFS is active +#if defined(PDL_PERIPHERAL_MFS_ACTIVE) + #include "mfs/mfs.h" +#endif + +// Include mft_frt.h if MFT'FRT is active +#if defined(PDL_PERIPHERAL_MFT_FRT_ACTIVE) + #include "mft/mft_frt.h" +#endif + +// Include mft_ocu.h if MFT'OCU is active +#if defined(PDL_PERIPHERAL_MFT_OCU_ACTIVE) + #include "mft/mft_ocu.h" +#endif + +// Include mft_wfg.h if MFT'WFG is active +#if defined(PDL_PERIPHERAL_MFT_WFG_ACTIVE) + #include "mft/mft_wfg.h" +#endif + +// Include mft_icu.h if MFT'ICU is active +#if defined(PDL_PERIPHERAL_MFT_ICU_ACTIVE) + #include "mft/mft_icu.h" +#endif + +// Include mft_adcmp.h if MFT'ADCMP is active +#if defined(PDL_PERIPHERAL_MFT_ADCMP_ACTIVE) + #include "mft/mft_adcmp.h" +#endif + +// Include pcrc.h if PCRC is active +#if defined(PDL_PERIPHERAL_PCRC_ACTIVE) + #include "pcrc/pcrc.h" +#endif + +// Include ppg.h if MFT'PPG is active +#if defined(PDL_PERIPHERAL_PPG_ACTIVE) + #include "ppg/ppg.h" +#endif + +// Include qprc.h if QPRC is active +#if defined(PDL_PERIPHERAL_QPRC_ACTIVE) + #include "qprc/qprc.h" +#endif + +// Include reset.h if reset is active +#if defined(PDL_PERIPHERAL_RESET_ACTIVE) + #include "reset/reset.h" +#endif + +// Include rc.h if RC is active +#if defined(PDL_PERIPHERAL_RC_ACTIVE) + #include "rc/rc.h" +#endif + +// Include rtc.h if RTC is active +#if defined(PDL_PERIPHERAL_RTC_ACTIVE) + #include "rtc/rtc.h" +#endif + +#if defined (PDL_PERIPHERAL_LCD_ACTIVE) + #include "lcd/lcd.h" +#endif + +// Activate code in sd.c is set to PDL_ON +#if defined (PDL_PERIPHERAL_SD_ACTIVE) + #include "sdif/sdif.h" + #include "sd_card/sd_card.h" + #include "sd_card/sd_cmd.h" +#endif + +// Include uid.h if UID is active +#if defined(PDL_PERIPHERAL_UID_ACTIVE) + #include "uid/uid.h" +#endif + + // Include vbat.h if WC is active +#if defined(PDL_PERIPHERAL_VBAT_ACTIVE) + #include "vbat/vbat.h" +#endif + +// Include wc.h if WC is active +#if defined(PDL_PERIPHERAL_WC_ACTIVE) + #include "wc/wc.h" +#endif + +// Include wdg.h if WDG is active +#if defined(PDL_PERIPHERAL_WDG_ACTIVE) + #include "wdg/wdg.h" +#endif + +#if (PDL_UTILITY_ENABLE_I2C_POLLING_AT24CXX == PDL_ON) || \ + (PDL_UTILITY_ENABLE_I2C_IRQ_AT24CXX == PDL_ON) + #include "eeprom/i2c_at24cxx.h" +#endif + +#if (PDL_UTILITY_ENABLE_I2S_CODEC_AT24CXX == PDL_ON) + #include "eeprom/i2c_at24cxx.h" +#endif + +#if (PDL_UTILITY_ENABLE_I2S_CODEC_WM8731 == PDL_ON) + #include "i2s_codec/wm8731.h" +#endif + +#if (PDL_UTILITY_ENABLE_HBIF_S26KL512S == PDL_ON) + #include "hyper_flash/s26kl512s.h" +#endif + +#if (PDL_UTILITY_ENABLE_EXTIF_S34ML01G == PDL_ON) + #include "nand_flash/s34ml01g.h" +#endif + +#if (PDL_UTILITY_ENABLE_EXTIF_IS42S16800 == PDL_ON) + #include "sdram/is42s16800.h" +#endif + +#if (PDL_UTILITY_ENABLE_UART_PRINTF == PDL_ON) + #include "printf_scanf/uart_io.h" +#endif + +#if (PDL_UTILITY_ENABLE_SEG_LCD_TSDH1188 == PDL_ON) + #include "seg_lcd/tsdh1188/tsdh1188.h" +#endif + +#if (PDL_UTILITY_ENABLE_SEG_LCD_CL0107031 == PDL_ON) + #include "seg_lcd/cl010/cl010.h" +#endif + +#if (PDL_UTILITY_ENABLE_QSPI_POLLING_S25FL164K == PDL_ON) || \ + (PDL_UTILITY_ENABLE_QSPI_IRQ_S25FL164K == PDL_ON) + #include "qspi_flash/flashS25FL164K.h" +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __PDL_HEADER_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/ppg/ppg.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/ppg/ppg.c new file mode 100644 index 0000000000..611c1b3ee1 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/ppg/ppg.c @@ -0,0 +1,1055 @@ +/******************************************************************************* +* \file ppg.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the PPG +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "ppg/ppg.h" + +#if (defined(PDL_PERIPHERAL_PPG_ACTIVE)) + + +#if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) +/******************************************************************************/ +/* Static variable definitions */ +/******************************************************************************/ +static func_ptr_t afnPpgCallback[PPG_INT_MAX_CH]; ///< Callback function pointer of PPG interrupt + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on PPG channel + ** + ** \param u8CoupleCh PPG couple channel + ** + ******************************************************************************/ +static void PpgInitNvic(uint8_t u8CoupleCh) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + if((PPG_COUPLE_CH01 == u8CoupleCh) || (PPG_COUPLE_CH23 == u8CoupleCh) || (PPG_COUPLE_CH45 == u8CoupleCh)) + { + NVIC_ClearPendingIRQ(PPG00_02_04_IRQn); + NVIC_EnableIRQ(PPG00_02_04_IRQn); + NVIC_SetPriority(PPG00_02_04_IRQn, PDL_IRQ_LEVEL_PPG00_02_04); + } + else if ((PPG_COUPLE_CH89 == u8CoupleCh) || (PPG_COUPLE_CH1011 == u8CoupleCh) || (PPG_COUPLE_CH1213 == u8CoupleCh)) + { + NVIC_ClearPendingIRQ(PPG08_10_12_IRQn); + NVIC_EnableIRQ(PPG08_10_12_IRQn); + NVIC_SetPriority(PPG08_10_12_IRQn, PDL_IRQ_LEVEL_PPG08_10_12); + } + else if ((PPG_COUPLE_CH1617 == u8CoupleCh) || (PPG_COUPLE_CH1819 == u8CoupleCh) || (PPG_COUPLE_CH2021 == u8CoupleCh)) + { + NVIC_ClearPendingIRQ(PPG16_18_20_IRQn); + NVIC_EnableIRQ(PPG16_18_20_IRQn); + NVIC_SetPriority(PPG16_18_20_IRQn, PDL_IRQ_LEVEL_PPG16_18_20); + } +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_1_A) + NVIC_ClearPendingIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_EnableIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_SetPriority(PPG00_02_04_08_10_12_16_18_20_IRQn, PDL_IRQ_LEVEL_PPG00_02_04_08_10_12_16_18_20); + #elif (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_2_A) + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_EnableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_IRQ_LEVEL_PPG00_02_20_DSTC_SMCIF0_HDMICEC0); + #endif +#else + NVIC_ClearPendingIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_EnableIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_SetPriority(PPG00_02_04_08_10_12_16_18_20_IRQn, PDL_IRQ_LEVEL_PPG); +#endif +} + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on PPG channel + ** + ** \param u8CoupleCh PPG couple channel + ** + ******************************************************************************/ +static void PpgDeInitNvic(uint8_t u8CoupleCh) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + if((PPG_COUPLE_CH01 == u8CoupleCh) || (PPG_COUPLE_CH23 == u8CoupleCh) || (PPG_COUPLE_CH45 == u8CoupleCh)) + { + NVIC_ClearPendingIRQ(PPG00_02_04_IRQn); + NVIC_DisableIRQ(PPG00_02_04_IRQn); + NVIC_SetPriority(PPG00_02_04_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + else if ((PPG_COUPLE_CH89 == u8CoupleCh) || (PPG_COUPLE_CH1011 == u8CoupleCh) || (PPG_COUPLE_CH1213 == u8CoupleCh)) + { + NVIC_ClearPendingIRQ(PPG08_10_12_IRQn); + NVIC_DisableIRQ(PPG08_10_12_IRQn); + NVIC_SetPriority(PPG08_10_12_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } + else if ((PPG_COUPLE_CH1617 == u8CoupleCh) || (PPG_COUPLE_CH1819 == u8CoupleCh) || (PPG_COUPLE_CH2021 == u8CoupleCh)) + { + NVIC_ClearPendingIRQ(PPG16_18_20_IRQn); + NVIC_DisableIRQ(PPG16_18_20_IRQn); + NVIC_SetPriority(PPG16_18_20_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + } +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_1_A) + NVIC_ClearPendingIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_DisableIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_SetPriority(PPG00_02_04_08_10_12_16_18_20_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #elif (FM_INTERRUPT_TYPE == PDL_FM0P_INT_TYPE_2_A) + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_DisableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#else + NVIC_ClearPendingIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_DisableIRQ(PPG00_02_04_08_10_12_16_18_20_IRQn); + NVIC_SetPriority(PPG00_02_04_08_10_12_16_18_20_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +} + +/** + ****************************************************************************** + ** \brief PPG interrupt service routine + ******************************************************************************/ +void Ppg_IrqHandler(void) +{ + if(1u == bFM_MFT_PPG_PPGC0_PUF) // IRQ triggered by ch.0? + { + bFM_MFT_PPG_PPGC0_PUF = 0u; + bFM_MFT_PPG_PPGC1_PUF = 0u; + afnPpgCallback[0u](); + } + + if(1u == bFM_MFT_PPG_PPGC2_PUF) // IRQ triggered by ch.2? + { + bFM_MFT_PPG_PPGC2_PUF = 0u; + bFM_MFT_PPG_PPGC3_PUF = 0u; + afnPpgCallback[1u](); + } + + if(1u == bFM_MFT_PPG_PPGC4_PUF) // IRQ triggered by ch.4? + { + bFM_MFT_PPG_PPGC4_PUF = 0u; + bFM_MFT_PPG_PPGC5_PUF = 0u; + afnPpgCallback[2u](); + } + + if(1u == bFM_MFT_PPG_PPGC8_PUF) // IRQ triggered by ch.8? + { + bFM_MFT_PPG_PPGC8_PUF = 0u; + bFM_MFT_PPG_PPGC9_PUF = 0u; + afnPpgCallback[3u](); + } + + if(1u == bFM_MFT_PPG_PPGC10_PUF) // IRQ triggered by ch.10? + { + bFM_MFT_PPG_PPGC10_PUF = 0u; + bFM_MFT_PPG_PPGC11_PUF = 0u; + afnPpgCallback[4u](); + } + + if(1u == bFM_MFT_PPG_PPGC12_PUF) // IRQ triggered by ch.12? + { + bFM_MFT_PPG_PPGC12_PUF = 0u; + bFM_MFT_PPG_PPGC13_PUF = 0u; + afnPpgCallback[5u](); + } + + if(1u == bFM_MFT_PPG_PPGC16_PUF) // IRQ triggered by ch.16? + { + bFM_MFT_PPG_PPGC16_PUF = 0u; + bFM_MFT_PPG_PPGC17_PUF = 0u; + afnPpgCallback[6u](); + } + + if(1u == bFM_MFT_PPG_PPGC18_PUF) // IRQ triggered by ch.18? + { + bFM_MFT_PPG_PPGC18_PUF = 0u; + bFM_MFT_PPG_PPGC19_PUF = 0u; + afnPpgCallback[7u](); + } + + if(1u == bFM_MFT_PPG_PPGC20_PUF) // IRQ triggered by ch.20? + { + bFM_MFT_PPG_PPGC20_PUF = 0u; + bFM_MFT_PPG_PPGC21_PUF = 0u; + afnPpgCallback[8u](); + } +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialize PPG + ** + ** \param [in] u8CoupleCh a couple PPG channel + ** \arg PPG_COUPLE_CH01 ~ PPG_COUPLE_CH2223 + ** \param [in] pstcConfig pointer to PPG configuration structure + ** + ** \retval Ok Configure the PPG successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8CoupleCh%2 !=0 + ** - u8CoupleCh > PPG_COUPLE_CH2223 + ** - Parameter error of PPG configuration structure + ** + ******************************************************************************/ +en_result_t Ppg_Init( uint8_t u8CoupleCh, + const stc_ppg_config_t *pstcConfig) +{ + volatile stc_mft_ppg_ppgc0_field_t *pstcPpgc0; + volatile stc_mft_ppg_ppgc1_field_t *pstcPpgc1; + volatile uint16_t *pu16Revc0, *pu16Revc1; + volatile uint8_t *pu8Gatec; + uint8_t u8Offset, u8Gap; + if( (0u != (u8CoupleCh%2)) || + (u8CoupleCh > PPG_COUPLE_CH2223) ) + { + return ErrorInvalidParameter ; + } + u8Offset = u8CoupleCh%4u; + u8Gap = u8CoupleCh/4u; + pstcPpgc1 = (stc_mft_ppg_ppgc1_field_t*)((uint8_t*)&FM_MFT_PPG->PPGC1 + u8Gap*0x40u + u8Offset*2u); + pstcPpgc0 = (stc_mft_ppg_ppgc0_field_t*)((uint8_t*)&FM_MFT_PPG->PPGC0 + u8Gap*0x40u + u8Offset*2u); + pu16Revc0 = (uint16_t*)((uint8_t*)&FM_MFT_PPG->REVC0); + pu16Revc1 = (uint16_t*)((uint8_t*)&FM_MFT_PPG->REVC1); + pu8Gatec = (uint8_t*)((uint8_t*)&FM_MFT_PPG->GATEC0 + u8Gap*0x40u); + + // set mode + switch (pstcConfig->enMode) + { + case Ppg8Bit8Bit: + pstcPpgc0->MD = 0u; + break; + case Ppg8Bit8Pres: + pstcPpgc0->MD = 1u; + break; + case Ppg16Bit: + pstcPpgc0->MD = 2u; + break; + case Ppg16Bit16Pres: + pstcPpgc0->MD = 3u; + break; + default: + return ErrorInvalidParameter ; + } + + // set even channel clock, level + switch (pstcConfig->enEvenClock) + { + case PpgPclkDiv1: + pstcPpgc0->PCS = 0u; + break; + case PpgPclkDiv4: + pstcPpgc0->PCS = 1u; + break; + case PpgPclkDiv16: + pstcPpgc0->PCS = 2u; + break; + case PpgPclkDiv64: + pstcPpgc0->PCS = 3u; + break; + default: + return ErrorInvalidParameter ; + } + + if(u8CoupleCh < PPG_CH16) + { + switch (pstcConfig->enEvenLevel) + { + case PpgNormalLevel: + *pu16Revc0 &= ~(1ul<enEvenLevel) + { + case PpgNormalLevel: + *pu16Revc1 &= ~(1ul<<(u8CoupleCh-PPG_CH16)); + break; + case PpgReverseLevel: + *pu16Revc1 |= (1ul<<(u8CoupleCh-PPG_CH16)); + break; + default: + return ErrorInvalidParameter ; + } + } + + // set odd channel clock, level + switch (pstcConfig->enOddClock) + { + case PpgPclkDiv1: + pstcPpgc1->PCS = 0u; + break; + case PpgPclkDiv4: + pstcPpgc1->PCS = 1u; + break; + case PpgPclkDiv16: + pstcPpgc1->PCS = 2u; + break; + case PpgPclkDiv64: + pstcPpgc1->PCS = 3u; + break; + default: + return ErrorInvalidParameter ; + } + + if(u8CoupleCh < PPG_CH16) + { + switch (pstcConfig->enOddLevel) + { + case PpgNormalLevel: + *pu16Revc0 &= ~(1ul<<(u8CoupleCh+1)); + break; + case PpgReverseLevel: + *pu16Revc0 |= (1ul<<(u8CoupleCh+1)); + break; + default: + return ErrorInvalidParameter ; + } + } + else + { + switch (pstcConfig->enOddLevel) + { + case PpgNormalLevel: + *pu16Revc1 &= ~(1ul<<(u8CoupleCh+1-PPG_CH16)); + break; + case PpgReverseLevel: + *pu16Revc1 |= (1ul<<(u8CoupleCh+1-PPG_CH16)); + break; + default: + return ErrorInvalidParameter ; + } + } + + // set PPG mode + switch (pstcConfig->enTrig) + { + case PpgSoftwareTrig: + pstcPpgc0->TTRG = 0u; + if((u8CoupleCh%4) == 0u) + { + *pu8Gatec &= ~(1ul<<1); + } + else + { + *pu8Gatec &= ~(1ul<<5); + } + break; + case PpgMftGateTrig: + pstcPpgc0->TTRG = 0u; + if((u8CoupleCh%4) == 0) + { + *pu8Gatec |= (1ul<<1); + } + else + { + *pu8Gatec |= (1ul<<5); + } + break; + case PpgTimingGenTrig: + pstcPpgc0->TTRG = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + // Set interrupt mode + switch (pstcConfig->enIrqMode) + { + case PpgIrqHighOrLowUnderflow: + pstcPpgc0->INTM = 0u; + break; + case PpgIrqHighUnderflow: + pstcPpgc0->INTM = 1u; + break; + default: + return ErrorInvalidParameter ; + } + +#if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) + // Set interrupt enable + if(pstcConfig->bIrqEnable == TRUE) + { + pstcPpgc0->PIE = 1u; + } + + // Set interrupt callback function + if((PPG_COUPLE_CH01 == u8CoupleCh) || (PPG_COUPLE_CH23 == u8CoupleCh) || (PPG_COUPLE_CH45 == u8CoupleCh)) + { + afnPpgCallback[u8CoupleCh/2u] = pstcConfig->pfnIrqCallback; + } + else if((PPG_COUPLE_CH89 == u8CoupleCh) || (PPG_COUPLE_CH1011 == u8CoupleCh) || (PPG_COUPLE_CH1213 == u8CoupleCh)) + { + afnPpgCallback[(u8CoupleCh-2u)/2u] = pstcConfig->pfnIrqCallback; + } + else if((PPG_COUPLE_CH1617 == u8CoupleCh) || (PPG_COUPLE_CH1819 == u8CoupleCh) || (PPG_COUPLE_CH2021 == u8CoupleCh)) + { + afnPpgCallback[(u8CoupleCh-4u)/2u] = pstcConfig->pfnIrqCallback; + } + + // Set NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + PpgInitNvic(u8CoupleCh); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize PPG + ** + ** \param [in] u8CoupleCh a couple PPG channel + ** \arg PPG_COUPLE_CH01 ~ PPG_COUPLE_CH2223 + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Configure the PPG successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8CoupleCh%2 !=0 + ** - u8CoupleCh > PPG_COUPLE_CH2223 + ** + ******************************************************************************/ +en_result_t Ppg_DeInit(uint8_t u8CoupleCh, boolean_t bTouchNvic) +{ + volatile uint8_t *pu8Ppgc0; + volatile uint8_t *pu8Ppgc1; + uint8_t u8Offset, u8Gap; + if( (0u != (u8CoupleCh%2u)) || + (u8CoupleCh > PPG_COUPLE_CH2223) ) + { + return ErrorInvalidParameter ; + } + u8Offset = u8CoupleCh%4u; + u8Gap = u8CoupleCh/4u; + pu8Ppgc1 = (uint8_t*)((uint8_t*)&FM_MFT_PPG->PPGC1 + u8Gap*0x40u + u8Offset*2u); + pu8Ppgc0 = (uint8_t*)((uint8_t*)&FM_MFT_PPG->PPGC0 + u8Gap*0x40u + u8Offset*2u + 1u); + + *pu8Ppgc0 = 0u; + *pu8Ppgc1 = 0u; +#if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) + if(TRUE == bTouchNvic) + { + PpgDeInitNvic(u8CoupleCh); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start PPG by software trigger + ** + ** \param [in] u8Ch PPG channel + ** \arg PPG_CH0~PPG_CH23 + ** + ** \retval Ok Configure the PPG successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch > PPG_CH23 + ** + ******************************************************************************/ +en_result_t Ppg_StartSoftwareTrig(uint8_t u8Ch) +{ + if((u8Ch > PPG_CH23)) + { + return ErrorInvalidParameter ; + } + + if(u8Ch < PPG_CH16) + { + FM_MFT_PPG->TRG0 |= (uint16_t)(1ul<TRG1 |= (uint16_t)(1ul<<(u8Ch-PPG_CH16)); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Stop PPG software trigger + ** + ** \param [in] u8Ch PPG channel + ** \arg PPG_CH0~PPG_CH23 + ** + ** \retval Ok Configure the PPG successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch > PPG_CH23 + ** + ******************************************************************************/ +en_result_t Ppg_StopSoftwareTrig(uint8_t u8Ch) +{ + if((u8Ch > PPG_CH23)) + { + return ErrorInvalidParameter ; + } + + if(u8Ch < PPG_CH16) + { + FM_MFT_PPG->TRG0 &= (uint16_t)(~(1ul<TRG1 &= (uint16_t)(~(1ul<<(u8Ch-PPG_CH16))); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the valid level of GATE signal + ** + ** \param [in] u8EvenCh an even channel of PPG + ** \arg PPG_CH0~PPG_CH22 + ** \param [in] enLevel Valid level + ** + ** \retval Ok Set the valid level of GATE signal successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch > PPG_CH22 + ** - u8EvenCh%2 != 0 + ** - enLevel > PpgGateLowActive + ** + ******************************************************************************/ +en_result_t Ppg_SelGateLevel(uint8_t u8EvenCh, en_ppg_gate_level_t enLevel) +{ + volatile uint8_t *pu8Gatec; + if( (0u != (u8EvenCh%2u)) || + (u8EvenCh > PPG_CH22) || + (enLevel > PpgGateLowActive) ) + { + return ErrorInvalidParameter ; + } + + pu8Gatec = (uint8_t*)FM_MFT_PPG_BASE + 0x218u + 0x40u*(u8EvenCh/4); + + if(0u == (u8EvenCh%4u)) + { + *pu8Gatec &= ~(1ul); + *pu8Gatec |= enLevel; + } + else + { + *pu8Gatec &= ~(1ul<<4u); + *pu8Gatec |= (uint8_t)((uint8_t)enLevel<<4u); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure the up counter of Timing Generator 0 + ** + ** \param [in] pstcConfig Pointer to up counter 0 configuration structure + ** + ** \retval Ok Configure the up counter successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcConfig != NULL + ** - pstcConfig->enClk > PpgUpCntPclkDiv64 + ** + ******************************************************************************/ +en_result_t Ppg_ConfigUpCnt0(stc_ppg_upcnt0_config_t* pstcConfig) +{ + if((NULL != pstcConfig) || + (pstcConfig->enClk > PpgUpCntPclkDiv64 )) + { + return ErrorInvalidParameter ; + } + + FM_MFT_PPG->TTCR0 &= ~(3ul<<2u); + FM_MFT_PPG->TTCR0 |= (uint16_t)((uint16_t)pstcConfig->enClk<<2u); + FM_MFT_PPG->COMP0 = pstcConfig->u8CmpValue0; + FM_MFT_PPG->COMP2 = pstcConfig->u8CmpValue2; + FM_MFT_PPG->COMP4 = pstcConfig->u8CmpValue4; + FM_MFT_PPG->COMP6 = pstcConfig->u8CmpValue6; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start the up counter of Timing Generator 0 + ******************************************************************************/ +void Ppg_StartUpCnt0(void) +{ + bFM_MFT_PPG_TTCR0_STR0 = 1u; +} + +/** + ****************************************************************************** + ** \brief Get the work status of up counter of Timing Generator 0 + ** + ** \retval PdlSet Up counter is counting + ** \retval PdlClr Up counter stops + ** + ******************************************************************************/ +en_stat_flag_t Ppg_GetUpCnt0Status(void) +{ + en_stat_flag_t enRet; + + (1u == bFM_MFT_PPG_TTCR0_MONI0) ? (enRet = PdlSet) : (enRet = PdlClr); + + return enRet; +} + +/** + ****************************************************************************** + ** \brief Disable start trigger of Timing Generator 0 + ** + ** \param pstcTimer0GenCh Pointer to the structure of selected channels + ** (ch.0,2,4,6) + ** + ** \retval Ok Disable start trigger + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcTimer0GenCh->bPpgChx isn't bool type + ** + ******************************************************************************/ +en_result_t Ppg_DisableTimerGen0StartTrig(stc_timer0_gen_ch_t* pstcTimer0GenCh) +{ + if((pstcTimer0GenCh->bPpgCh0 > 1u) || + (pstcTimer0GenCh->bPpgCh2 > 1u) || + (pstcTimer0GenCh->bPpgCh4 > 1u) || + (pstcTimer0GenCh->bPpgCh6 > 1u) ) + { + return ErrorInvalidParameter; + } + + bFM_MFT_PPG_TTCR0_TRG0O = ((pstcTimer0GenCh->bPpgCh0 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR0_TRG2O = ((pstcTimer0GenCh->bPpgCh2 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR0_TRG4O = ((pstcTimer0GenCh->bPpgCh4 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR0_TRG6O = ((pstcTimer0GenCh->bPpgCh6 == 1u) ? 1u : 0u); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure the up counter of Timing Generator 1 + ** + ** \param [in] pstcConfig Pointer to up counter 1 configuration structure + ** + ** \retval Ok Configure the up counter successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcConfig != NULL + ** - pstcConfig->enClk > PpgUpCntPclkDiv64 + ** + ******************************************************************************/ +en_result_t Ppg_ConfigUpCnt1(stc_ppg_upcnt1_config_t* pstcConfig) +{ + if(pstcConfig->enClk > PpgUpCntPclkDiv64 ) + { + return ErrorInvalidParameter ; + } + + FM_MFT_PPG->TTCR1 &= ~(3ul<<2u); + FM_MFT_PPG->TTCR1 |= (uint16_t)((uint16_t)pstcConfig->enClk<<2u); + FM_MFT_PPG->COMP1 = pstcConfig->u8CmpValue8; + FM_MFT_PPG->COMP3 = pstcConfig->u8CmpValue10; + FM_MFT_PPG->COMP5 = pstcConfig->u8CmpValue12; + FM_MFT_PPG->COMP7 = pstcConfig->u8CmpValue14; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start the up counter of Timing Generator 1 + ******************************************************************************/ +void Ppg_StartUpCnt1(void) +{ + bFM_MFT_PPG_TTCR1_STR1 = 1u; +} + +/** + ****************************************************************************** + ** \brief Get the work status of up counter of Timing Generator 1 + ** + ** \retval PdlSet Up counter is counting + ** \retval PdlClr Up counter stops + ** + ******************************************************************************/ +en_stat_flag_t Ppg_GetUpCnt1Status(void) +{ + en_stat_flag_t enRet; + + (bFM_MFT_PPG_TTCR1_MONI1 == 1u) ? (enRet = PdlSet) : (enRet = PdlClr); + + return enRet; +} + +/** + ****************************************************************************** + ** \brief Disable start trigger of Timing Generator 1 + ** + ** \param pstcTimer1GenCh Pointer to the structure of selected channels + ** (ch.8,10,12,14) + ** + ** \retval Ok Disable start trigger + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcTimer0GenCh->bPpgChx isn't bool type + ** + ******************************************************************************/ +en_result_t Ppg_DisableTimerGen1StartTrig(stc_timer1_gen_ch_t* pstcTimer1GenCh) +{ + if((pstcTimer1GenCh->bPpgCh8 > 1u) || + (pstcTimer1GenCh->bPpgCh10 > 1u) || + (pstcTimer1GenCh->bPpgCh12 > 1u) || + (pstcTimer1GenCh->bPpgCh14 > 1u) ) + { + return ErrorInvalidParameter; + } + + bFM_MFT_PPG_TTCR1_TRG1O = ((pstcTimer1GenCh->bPpgCh8 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR1_TRG3O = ((pstcTimer1GenCh->bPpgCh10 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR1_TRG5O = ((pstcTimer1GenCh->bPpgCh12 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR1_TRG7O = ((pstcTimer1GenCh->bPpgCh14 == 1u) ? 1u : 0u); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure the up counter of Timing Generator 2 + ** + ** \param [in] pstcConfig Pointer to up counter 2 configuration structure + ** + ** \retval Ok Configure the up counter successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcConfig != NULL + ** - pstcConfig->enClk > PpgUpCntPclkDiv64 + ** + ******************************************************************************/ +en_result_t Ppg_ConfigUpCnt2(stc_ppg_upcnt2_config_t* pstcConfig) +{ + if(pstcConfig->enClk > PpgUpCntPclkDiv64 ) + { + return ErrorInvalidParameter ; + } + + FM_MFT_PPG->TTCR1 &= ~(3ul<<2u); + FM_MFT_PPG->TTCR1 |= (uint16_t)((uint16_t)pstcConfig->enClk<<2u); + FM_MFT_PPG->COMP8 = pstcConfig->u8CmpValue16; + FM_MFT_PPG->COMP10 = pstcConfig->u8CmpValue18; + FM_MFT_PPG->COMP12 = pstcConfig->u8CmpValue20; + FM_MFT_PPG->COMP14 = pstcConfig->u8CmpValue22; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Start the up counter of Timing Generator 2 + ******************************************************************************/ +void Ppg_StartUpCnt2(void) +{ + bFM_MFT_PPG_TTCR2_STR2 = 1u; +} + +/** + ****************************************************************************** + ** \brief Get the work status of up counter of Timing Generator 2 + ** + ** \retval PdlSet Up counter is counting + ** \retval PdlClr Up counter stops + ** + ******************************************************************************/ +en_stat_flag_t Ppg_GetUpCnt2Status(void) +{ + en_stat_flag_t enRet; + (bFM_MFT_PPG_TTCR2_MONI2 == 1u) ? (enRet = PdlSet) : (enRet = PdlClr); + return enRet; +} + +/** + ****************************************************************************** + ** \brief Disable start trigger of Timing Generator 2 + ** + ** \param pstcTimer2GenCh Pointer to the structure of selected channels + ** (ch.16,18,20,22) + ** + ** \retval Ok Disable start trigger + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcTimer0GenCh->bPpgChx isn't bool type + ** + ******************************************************************************/ +en_result_t Ppg_DisableTimerGen2StartTrig(stc_timer2_gen_ch_t* pstcTimer2GenCh) +{ + if((pstcTimer2GenCh->bPpgCh16 > 1u) || + (pstcTimer2GenCh->bPpgCh18 > 1u) || + (pstcTimer2GenCh->bPpgCh20 > 1u) || + (pstcTimer2GenCh->bPpgCh22 > 1u) ) + { + return ErrorInvalidParameter; + } + + bFM_MFT_PPG_TTCR2_TRG16O = ((pstcTimer2GenCh->bPpgCh16 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR2_TRG18O = ((pstcTimer2GenCh->bPpgCh18 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR2_TRG20O = ((pstcTimer2GenCh->bPpgCh20 == 1u) ? 1u : 0u); + bFM_MFT_PPG_TTCR2_TRG22O = ((pstcTimer2GenCh->bPpgCh22 == 1u) ? 1u : 0u); + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable PPG interrupt + ** + ** \param [in] u8CoupleCh PPG couple channel + ** \arg PPG_CHx, x=0,2,4,8,10,12,16,18,20 + ** + ** \retval Ok Enable PPG interrupt successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch != ch.0,2,4,8,10,12,16,18,20 + ** + ******************************************************************************/ +en_result_t Ppg_EnableIrq(uint8_t u8CoupleCh) +{ + volatile stc_mft_ppg_ppgc0_field_t *pstcPpgc0; + uint8_t u8Offset, u8Gap; + if( (0u != (u8CoupleCh%2u)) || + (u8CoupleCh > PPG_COUPLE_CH2223) ) + { + return ErrorInvalidParameter ; + } + + u8Offset = u8CoupleCh%4u; + u8Gap = u8CoupleCh/4u; + pstcPpgc0 = (stc_mft_ppg_ppgc0_field_t*)((uint8_t*)&FM_MFT_PPG->PPGC0 + u8Gap*0x40u + u8Offset*2u); + + pstcPpgc0->PIE = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable PPG interrupt + ** + ** \param [in] u8CoupleCh PPG couple channel + ** \arg PPG_CHx, x=0,2,4,8,10,12,16,18,20 + ** + ** \retval Ok Disable PPG interrupt successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch != ch.0,2,4,8,10,12,16,18,20 + ** + ******************************************************************************/ +en_result_t Ppg_DisableIrq(uint8_t u8CoupleCh) +{ + volatile stc_mft_ppg_ppgc0_field_t *pstcPpgc0; + uint8_t u8Offset, u8Gap; + if( (0u != (u8CoupleCh%2u)) || + (u8CoupleCh > PPG_COUPLE_CH2223) ) + { + return ErrorInvalidParameter ; + } + + u8Offset = u8CoupleCh%4u; + u8Gap = u8CoupleCh/4u; + pstcPpgc0 = (stc_mft_ppg_ppgc0_field_t*)((uint8_t*)&FM_MFT_PPG->PPGC0 + u8Gap*0x40u + u8Offset*2u); + + pstcPpgc0->PIE = 0u; + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get the interrupt flag of PPG + ** + ** \param [in] u8CoupleCh PPG couple channel + ** \arg PPG_CHx, x=0,2,4,8,10,12,16,18,20 + ** + ** \retval PdlSet Interrupt flag set + ** \retval PdlClr Interrupt flag clear + ** + ******************************************************************************/ +en_irq_flag_t Ppg_GetIrqFlag(uint8_t u8CoupleCh) +{ + volatile uint8_t *pu8Ppgc0Addr; + uint8_t u8Offset, u8Gap; + en_irq_flag_t enFlag; + // Only Ch.0,2,4,8,10,12,16,18,20 can produce interrupt request + if( (0u != (u8CoupleCh%2u)) || + (u8CoupleCh > PPG_COUPLE_CH2223) ) + { + return PdlClr ; + } + + u8Offset = u8CoupleCh%4u; + u8Gap = u8CoupleCh/4u; + pu8Ppgc0Addr = (uint8_t*)FM_MFT_PPG_BASE + 0x200u + u8Gap*0x40u + u8Offset*2 + 1u; + + if(0x40u == (*pu8Ppgc0Addr & 0x40u)) + { + enFlag = PdlSet; + } + else + { + enFlag = PdlClr; + } + + return enFlag; +} + +/** + ****************************************************************************** + ** \brief Clear PPG interrupt flag + ** + ** \param [in] u8CoupleCh PPG couple channel + ** \arg PPG_CHx, x=0,2,4,8,10,12,16,18,20 + ** + ** \retval Ok Clear PPG interrupt flag successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch != ch.0,2,4,8,10,12,16,18,20 + ** + ******************************************************************************/ +en_result_t Ppg_ClrIrqFlag(uint8_t u8CoupleCh) +{ + volatile uint8_t *pu8Ppgc0Addr, *pu8Ppgc1Addr; + uint8_t u8Offset, u8Gap; + // Only Ch.0,2,4,8,10,12,16,18,20 can produce interrupt request + if( (0u != (u8CoupleCh%2u)) || + (u8CoupleCh > PPG_COUPLE_CH2223) ) + { + return ErrorInvalidParameter ; + } + + u8Offset = u8CoupleCh%4u; + u8Gap = u8CoupleCh/4u; + pu8Ppgc0Addr = (uint8_t*)FM_MFT_PPG_BASE + 0x200u + u8Gap*0x40u + u8Offset*2u + 1u; + pu8Ppgc1Addr = (uint8_t*)FM_MFT_PPG_BASE + 0x200u + u8Gap*0x40u + u8Offset*2u ; + + // Clear interrupt flag of both even and odd channel + *pu8Ppgc0Addr &= ~(1ul<<6u); + *pu8Ppgc1Addr &= ~(1ul<<6u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the pulse width of PPG + ** + ** \param [in] u8Ch PPG channel + ** \arg PPG_CH0~PPG_CH23 + ** \param [in] u8LowWidth Low level width of PPG + ** \param [in] u8HighWidth High level width of PPG + ** + ** \retval Ok Set the pulse width of PPG successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u8Ch > PPG_CH23 + ** + ******************************************************************************/ +en_result_t Ppg_SetLevelWidth(uint8_t u8Ch, uint8_t u8LowWidth, uint8_t u8HighWidth) +{ + volatile uint8_t *pu8Prll0Addr, *pu8Prlh0Addr; + uint8_t u8Offset, u8Gap; + + if(u8Ch > PPG_CH23) + { + return ErrorInvalidParameter; + } + + u8Offset = u8Ch%4u; + u8Gap = u8Ch/4u; + pu8Prll0Addr = (uint8_t*)FM_MFT_PPG_BASE + 0x208u + u8Gap*0x40u + u8Offset*4u; + pu8Prlh0Addr = (uint8_t*)FM_MFT_PPG_BASE + 0x208u + u8Gap*0x40u + u8Offset*4u + 1u; + *pu8Prll0Addr = u8LowWidth; + *pu8Prlh0Addr = u8HighWidth; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Initialize IGBT mode + ** + ** \param [in] pstcPpgIgbt pointer to IBGT configuration structure + + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcPpgIgbt == NULL + ** - Other error configuration + ** + ******************************************************************************/ +#if (defined(FM_MFT_PPG_IGBTC)) +en_result_t Ppg_InitIgbt(stc_ppg_igbt_config_t* pstcPpgIgbt) +{ + + if((NULL == pstcPpgIgbt) || + (pstcPpgIgbt->enMode > IgbtStopProhibitionMode) || + (pstcPpgIgbt->enWidth > IgbtFilter32Pclk) || + (pstcPpgIgbt->enTrigInputLevel > IgbtLevelInvert) || + (pstcPpgIgbt->enIgbt0OutputLevel > IgbtLevelInvert) || + (pstcPpgIgbt->enIgbt1OutputLevel > IgbtLevelInvert) ) + { + return ErrorInvalidParameter; + } + // Prohibition mode setting + FM_MFT_PPG->IGBTC &= ~(1ul<<7u); + FM_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enMode<<7); + // Filter width setting + FM_MFT_PPG->IGBTC &= ~(7ul<<4u); + FM_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enWidth<<4); + // Trigger input level setting + FM_MFT_PPG->IGBTC &= ~(1ul<<1u); + FM_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enTrigInputLevel<<1); + // IGBT output level setting + FM_MFT_PPG->IGBTC &= ~(1ul<<2u); + FM_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enIgbt0OutputLevel<<2); + FM_MFT_PPG->IGBTC &= ~(1ul<<3u); + FM_MFT_PPG->IGBTC |= (uint8_t)((uint8_t)pstcPpgIgbt->enIgbt0OutputLevel<<3); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable IGBT mode + ** \note Only PPG0 and PP4 supports IGBT mode. + ** + ******************************************************************************/ +void Ppg_EnableIgbtMode(void) +{ + FM_MFT_PPG->IGBTC |= 1ul; +} + +/** + ****************************************************************************** + ** \brief Disable IGBT mode + ******************************************************************************/ +void Ppg_DisableIgbtMode(void) +{ + FM_MFT_PPG->IGBTC &= ~1ul; +} +#endif + +#endif +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/ppg/ppg.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/ppg/ppg.h new file mode 100644 index 0000000000..4fb8252b54 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/ppg/ppg.h @@ -0,0 +1,503 @@ +/******************************************************************************* +* \file ppg.h +* +* \version 1.20 +* +* \brief Headerfile for PPG functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __PPG_H__ +#define __PPG_H__ + +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_PPG_ACTIVE)) + +/** +* \defgroup GroupPPG Programmable Pulse Generator (PPG) +* \{ +* \defgroup GroupPPG_Macros Macros +* \defgroup GroupPPG_Functions Functions +* \defgroup GroupPPG_DataStructures Data Structures +* \defgroup GroupPPG_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupPPG +* \{ +* Use the Programmable Pulse Generator (PPG) peripheral in conjunction +* with a Waveform Generator (WFG) to create an arbitrary pulse output +* (both count and duty cycle). The WFG is one of the elements of the +* Multi-function Timer (MFT). The Waveform Generator (WFG) gets a +* signal from the Output Compare Unit (OCU) and/or a PPG.
+* +* There are up to 24 available PPG channels. However, only 9 channels +* can generate an output signal. The output is wired downstream to a +* WFG. There may be as many as three WFGs, each with three inputs. +* The number of available channels (PPG and WFG) varies among microcontroller +* series.
+* These PPG channels generate output:
+* * PPG channels 0, 2, 4 generate output to MFT0 +* * PPG channels 8, 10, 12 generate output to MFT1 +* * PPG channels 16,18,20 generate output to MFT2
+* Each PPG channel has an 8-bit counter. You connect two or more PPG +* channels to generate output pulses with longer count lengths. There are four +* operating modes:
+* * 8-bit – one channel, the output pulse width specified by an 8-bit value +* * 8+8-bit – two channels used, one is a counter, the other a prescalar +* * 16-bit – two channels are connected, the output pulse width specified by a 16-bit value +* * 16+16-bit mode – two connected channels are a 16-bit counter, and two connected +* channels are a 16-bit prescalar
+* There are three timing generators. Each consists of an 8-bit up counter and four +* compare values. Each timing generator controls four PPG channels.
+* * Timing generator 0 – channels 0,2,4,6 +* * Timing generator 1 – channels 8,10,12,14 +* * Timing generator 2 – channels 16,18,20, 22
+* Finally you can configure the PPG trigger to be:
+* * Software +* * The timing generator +* * A GATE signal from the MFT +* +* \section SectionPPG_ConfigurationConsideration Configuration Consideration +* To set up a PPG, you must also configure a WFG. See the description in MFT WFG.
+* For configuration purposes, the PDL treats PPG channels as pairs, one even, one odd. +* To set up the PPG, fill in the fields of the stc_ppg_config_t structure for +* each channel you wish to configure. For example, you provide the operating mode, +* the clock prescalar for the even and odd numbered channel, the trigger mode, and so on. +* Call Ppg_Init() with the channel pair, and the address of the configuration structure. +* You can configure each channel pair independently.
+* If you use the timing generator to trigger a PPG, you must configure the required +* timer for the PPG channel. Use the corresponding configuration structure such as +* stc_ppg_upcnt0_config_t. Then call the corresponding configuration function such as +* Ppg_ConfigUpCnt0().
+* How you start a PPG depends on how you trigger it:
+* * Software trigger – call Ppg_StartSoftwareTrig() +* * Timing generator – start the timer with a call such as Ppg_StartUpCnt0(). +* * GATE signal – set the GATE signal to an valid level in the MFT module
+* If you use the GATE level as a trigger, use Ppg_SelGateLevel() to select the valid level.
+* How you stop a PPG depends upon the way you trigger it:
+* * Software trigger – call Ppg_StopSoftwareTrig() +* * Timing generator – call the correct disable routine, such as Ppg_DisableTimerGen0StartTrig() +* * GATE signal - set the GATE signal to an invalid level in the MFT module
+* When an enabled interrupt occurs, the interrupt flag is cleared and control passes +* to the callback function. You can also use polling to manage interrupts. With polling mode, +* use Ppg_GetIrqFlag() to poll for an interrupt. Clear the interrupt flag with Ppg_ClrIrqFlag().
+* +* +* \section SectionPPG_MoreInfo More Information +* For more information on the PPG peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* +*/ + +/** +* \addtogroup GroupPPG_Macros +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#define PPG_CH0 0u +#define PPG_CH1 1u +#define PPG_CH2 2u +#define PPG_CH3 3u +#define PPG_CH4 4u +#define PPG_CH5 5u +#define PPG_CH6 6u +#define PPG_CH7 7u +#define PPG_CH8 8u +#define PPG_CH9 9u +#define PPG_CH10 10u +#define PPG_CH11 11u +#define PPG_CH12 12u +#define PPG_CH13 13u +#define PPG_CH14 14u +#define PPG_CH15 15u +#define PPG_CH16 16u +#define PPG_CH17 17u +#define PPG_CH18 18u +#define PPG_CH19 19u +#define PPG_CH20 20u +#define PPG_CH21 21u +#define PPG_CH22 22u +#define PPG_CH23 23u + +#define PPG_COUPLE_CH01 0u +#define PPG_COUPLE_CH23 2u +#define PPG_COUPLE_CH45 4u +#define PPG_COUPLE_CH67 6u +#define PPG_COUPLE_CH89 8u +#define PPG_COUPLE_CH1011 10u +#define PPG_COUPLE_CH1213 12u +#define PPG_COUPLE_CH1415 14u +#define PPG_COUPLE_CH1617 16u +#define PPG_COUPLE_CH1819 18u +#define PPG_COUPLE_CH2021 20u +#define PPG_COUPLE_CH2223 22u + +#define PPG_INT_MAX_CH 9u // Including channel.0,2,4,8,10,12,16,18,20 + +#define PPG_UP_COUNTER_CH0 0u +#define PPG_UP_COUNTER_CH1 1u +#define PPG_UP_COUNTER_CH2 2u + +/** \} GroupPPG_Macros */ + +/** +* \addtogroup GroupPPG_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define PPG operation mode + ** \note only following combination of 4 channel is valid: + ** Ch0_Ch1 Ch2_Ch3 + ** Ppg8Bit8Bit Ppg8Bit8Bit + ** Ppg8Bit8Bit Ppg8Bit8Pres + ** Ppg8Bit8Bit Ppg16Bit + ** Ppg8Bit8Pres Ppg8Bit8Bit + ** Ppg8Bit8Pres Ppg8Bit8Pres + ** Ppg8Bit8Pres Ppg16Bit + ** Ppg16Bit Ppg8Bit8Bit + ** Ppg16Bit Ppg8Bit8Pres + ** Ppg16Bit Ppg16Bit + ** Ppg16Bit16Pres Ppg16Bit16Pres [Act as Prescaler] + ** + ******************************************************************************/ +typedef enum en_ppg_opt_mode +{ + Ppg8Bit8Bit = 0u, ///< Even channel: 8bit PPG, odd channel: 8bit PPG + Ppg8Bit8Pres = 1u, ///< Even channel: 8bit PPG, odd channel: 8bit prescaler + Ppg16Bit = 2u, ///< 16bit PPG + Ppg16Bit16Pres = 3u, ///< 16bit PPG + 16 prescaler (provided by next couple channel) + +}en_ppg_opt_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PPG count clock prescaler + ******************************************************************************/ +typedef enum en_ppg_clock +{ + PpgPclkDiv1 = 0u, ///< PPG count clock prescaler: 1 + PpgPclkDiv4 = 1u, ///< PPG count clock prescaler: 1/4 + PpgPclkDiv16 = 2u, ///< PPG count clock prescaler: 1/16 + PpgPclkDiv64 = 3u, ///< PPG count clock prescaler: 1/64 + +}en_ppg_clock_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PPG trigger + ******************************************************************************/ +typedef enum en_ppg_trig +{ + PpgSoftwareTrig = 0u, ///< Use software to trigger PPG + PpgMftGateTrig = 1u, ///< Use GATE signal from MFT to trigger PPG + PpgTimingGenTrig = 2u, ///< Use Timing Generator to trigger PPG + +}en_ppg_trig_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define PPG output initial level + ******************************************************************************/ +typedef enum en_ppg_level +{ + PpgNormalLevel = 0u, ///< Initial level: Low + PpgReverseLevel = 1u, ///< Initial level: High + +}en_ppg_level_t; + +/** + ****************************************************************************** + ** \brief PPG interrupt mode + ******************************************************************************/ +typedef enum en_ppg_irq_mode +{ + PpgIrqHighOrLowUnderflow = 0u, ///< Generate interrupt when high or low width count underflows + PpgIrqHighUnderflow = 1u, ///< Generate interrupt when high width count underflows + +}en_ppg_irq_mode_t; +/** + ****************************************************************************** + ** \brief Enumeration to define valid level of GATE signal from MFT + ******************************************************************************/ +typedef enum en_ppg_gate_level +{ + PpgGateHighActive = 0u, ///< GATE valid level: High + PpgGateLowActive = 1u, ///< GATE valid level: Low + +}en_ppg_gate_level_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define clock prescaler of up counter + ** in timing generator + ******************************************************************************/ +typedef enum en_ppg_upcnt_clk +{ + PpgUpCntPclkDiv2 = 0u, ///< Up counter clock prescaler: 1/2 + PpgUpCntPclkDiv8 = 1u, ///< Up counter clock prescaler: 1/8 + PpgUpCntPclkDiv32 = 2u, ///< Up counter clock prescaler: 1/32 + PpgUpCntPclkDiv64 = 3u, ///< Up counter clock prescaler: 1/64 + +}en_ppg_upcnt_clk_t; +/** + ****************************************************************************** + ** \brief Enumeration to define IBGT prohibition mode + ******************************************************************************/ +typedef enum en_igbt_prohibition_mode +{ + IgbtNormalMode = 0u, ///< Normal mode + IgbtStopProhibitionMode = 1u, ///< Stop prohibition mode in output active + +}en_igbt_prohibition_mode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define IBGT noise filter width + ******************************************************************************/ +typedef enum en_igbt_filter_width +{ + IgbtNoFilter = 0u, ///< No noise filter + IgbtFilter4Pclk = 1u, ///< noise filter width: 4PCLK + IgbtFilter8Pclk = 2u, ///< noise filter width: 8PCLK + IgbtFilter16Pclk = 3u, ///< noise filter width: 16PCLK + IgbtFilter32Pclk = 4u, ///< noise filter width: 32PCLK + +}en_igbt_filter_width_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define IBGT input/out level + ******************************************************************************/ +typedef enum en_igbt_level +{ + IgbtLevelNormal = 0u, ///< Normal + IgbtLevelInvert = 1u, ///< Invert + +}en_igbt_level_t; + +/** + ****************************************************************************** + ** \brief PPG IRQ channel + ******************************************************************************/ +typedef enum en_ppg_irq_ch +{ + PpgCh024 = 0u, ///< IRQ 36 for PPG ch.0,2,4 + PpgCh81012 = 1u, ///< IRQ 37 for PPG ch.8,10,12 + PpgCh161820 = 2u, ///< IRQ 38 for PPG ch.16,18,20 + +}en_ppg_irq_ch_t; + +/** \} GroupPPG_Types */ + +/** +* \addtogroup GroupPPG_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Structure to config PPG + ******************************************************************************/ +typedef struct stc_ppg_config +{ + en_ppg_opt_mode_t enMode; ///< PPG mode configuration + en_ppg_clock_t enEvenClock; ///< Clock prescaler of even channel + en_ppg_clock_t enOddClock; ///< Clock prescaler of odd channel + en_ppg_level_t enEvenLevel; ///< Output level of even channel + en_ppg_level_t enOddLevel; ///< Output level of odd channel + en_ppg_trig_t enTrig; ///< PPG trigger mode configuration + en_ppg_irq_mode_t enIrqMode; ///< PPG interrupt mode + + boolean_t bIrqEnable; ///< TRUE: enable IRQ, FALSE: don't enable IRQ + func_ptr_t pfnIrqCallback; ///< Pointer to PPG interrupt callback function + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC + +}stc_ppg_config_t; + +/** + ****************************************************************************** + ** \brief Up counter0 configuration + ******************************************************************************/ +typedef struct stc_ppg_upcnt0_config +{ + en_ppg_upcnt_clk_t enClk; ///< Up counter clock prescaler + uint8_t u8CmpValue0; ///< Up counter compare value for Ch0 + uint8_t u8CmpValue2; ///< Up counter compare value for Ch2 + uint8_t u8CmpValue4; ///< Up counter compare value for Ch4 + uint8_t u8CmpValue6; ///< Up counter compare value for Ch6 + +}stc_ppg_upcnt0_config_t; + +/** + ****************************************************************************** + ** \brief Up counter0 stop channels selection + ******************************************************************************/ +typedef struct stc_timer0_gen_ch +{ + boolean_t bPpgCh0; ///< 1: select Ch.0, 0: not selected + boolean_t bPpgCh2; ///< 1: select Ch.2, 0: not selected + boolean_t bPpgCh4; ///< 1: select Ch.4, 0: not selected + boolean_t bPpgCh6; ///< 1: select Ch.6, 0: not selected + +}stc_timer0_gen_ch_t; + +/** + ****************************************************************************** + ** \brief Up counter1 configuration + ******************************************************************************/ +typedef struct stc_ppg_upcnt1_config +{ + en_ppg_upcnt_clk_t enClk; ///< Up counter clock prescaler + uint8_t u8CmpValue8; ///< Up counter compare value for Ch8 + uint8_t u8CmpValue10; ///< Up counter compare value for Ch10 + uint8_t u8CmpValue12; ///< Up counter compare value for Ch12 + uint8_t u8CmpValue14; ///< Up counter compare value for Ch14 + +}stc_ppg_upcnt1_config_t; + +/** + ****************************************************************************** + ** \brief Up counter1 stop channels selection + ******************************************************************************/ +typedef struct stc_timer1_gen_ch +{ + boolean_t bPpgCh8; ///< 1: select Ch.8, 0: not selected + boolean_t bPpgCh10; ///< 1: select Ch.10, 0: not selected + boolean_t bPpgCh12; ///< 1: select Ch.12, 0: not selected + boolean_t bPpgCh14; ///< 1: select Ch.14, 0: not selected + +}stc_timer1_gen_ch_t; + +/** + ****************************************************************************** + ** \brief Up counter2 configuration + ******************************************************************************/ +typedef struct stc_ppg_upcnt2_config +{ + en_ppg_upcnt_clk_t enClk; ///< Up counter clock prescaler + uint8_t u8CmpValue16; ///< Up counter compare value for Ch16 + uint8_t u8CmpValue18; ///< Up counter compare value for Ch18 + uint8_t u8CmpValue20; ///< Up counter compare value for Ch20 + uint8_t u8CmpValue22; ///< Up counter compare value for Ch22 + +}stc_ppg_upcnt2_config_t; + +/** + ****************************************************************************** + ** \brief Up counter2 stop channels selection + ******************************************************************************/ +typedef struct stc_timer2_gen_ch +{ + boolean_t bPpgCh16; ///< 1: select Ch.16, 0: not selected + boolean_t bPpgCh18; ///< 1: select Ch.18, 0: not selected + boolean_t bPpgCh20; ///< 1: select Ch.20, 0: not selected + boolean_t bPpgCh22; ///< 1: select Ch.22, 0: not selected + +}stc_timer2_gen_ch_t; + +/** + ****************************************************************************** + ** \brief structure of PPG IGBT configuration + ******************************************************************************/ +typedef struct stc_ppg_igbt_config +{ + en_igbt_prohibition_mode_t enMode; ///< prohibition mode + en_igbt_filter_width_t enWidth; ///< noise filter width + en_igbt_level_t enTrigInputLevel; ///< Trigger input level + en_igbt_level_t enIgbt0OutputLevel; ///< IGBT0 output level (PPG0) + en_igbt_level_t enIgbt1OutputLevel; ///< IGBT1 output level (PPG4) + +}stc_ppg_igbt_config_t; + +/** \} GroupPPG_DataStructures */ + +/** +* \addtogroup GroupPPG_Functions +* \{ +*/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/* 1. Init/De-Init */ +en_result_t Ppg_Init( uint8_t u8CoupleCh, const stc_ppg_config_t *pstcConfig); +en_result_t Ppg_DeInit(uint8_t u8CoupleCh, boolean_t bTouchNvic); +/* 2. Trigger configuration */ +/* software */ +en_result_t Ppg_StartSoftwareTrig(uint8_t u8Ch); +en_result_t Ppg_StopSoftwareTrig(uint8_t u8Ch); +/* MFT gate signal */ +en_result_t Ppg_SelGateLevel(uint8_t u8EvenCh, en_ppg_gate_level_t enLevel); +/* Timing generator configuration */ +en_result_t Ppg_ConfigUpCnt0(stc_ppg_upcnt0_config_t* pstcConfig); +void Ppg_StartUpCnt0(void); +en_stat_flag_t Ppg_GetUpCnt0Status(void); +en_result_t Ppg_DisableTimerGen0StartTrig(stc_timer0_gen_ch_t* pstcTimer0GenCh); + +en_result_t Ppg_ConfigUpCnt1(stc_ppg_upcnt1_config_t* pstcConfig); +void Ppg_StartUpCnt1(void); +en_stat_flag_t Ppg_GetUpCnt1Status(void); +en_result_t Ppg_DisableTimerGen1StartTrig(stc_timer1_gen_ch_t* pstcTimer1GenCh); + +en_result_t Ppg_ConfigUpCnt2(stc_ppg_upcnt2_config_t* pstcConfig); +void Ppg_StartUpCnt2(void); +en_stat_flag_t Ppg_GetUpCnt2Status(void); +en_result_t Ppg_DisableTimerGen2StartTrig(stc_timer2_gen_ch_t* pstcTimer2GenCh); +/* 3. Int */ +#if (PDL_INTERRUPT_ENABLE_PPG == PDL_ON) +en_result_t Ppg_EnableIrq(uint8_t u8CoupleCh); +en_result_t Ppg_DisableIrq(uint8_t u8CoupleCh); +#endif +en_irq_flag_t Ppg_GetIrqFlag(uint8_t u8CoupleCh); +en_result_t Ppg_ClrIrqFlag(uint8_t u8CoupleCh); +/* 4. H/L width set */ +en_result_t Ppg_SetLevelWidth(uint8_t u8Ch, uint8_t u8LowWidth, uint8_t u8HighWidth); + +/* 5. IGBT mode */ +#if (defined(FM_MFT_PPG_IGBTC)) + en_result_t Ppg_InitIgbt(stc_ppg_igbt_config_t* pstcPpgIgbt); + void Ppg_EnableIgbtMode(void); + void Ppg_DisableIgbtMode(void); +#endif + +/* 6. IRQ handler */ +void Ppg_IrqHandler(void); + +/** \} GroupPPG_Functions */ +/** \} GroupPPG */ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/qprc/qprc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/qprc/qprc.c new file mode 100644 index 0000000000..123005f4ee --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/qprc/qprc.c @@ -0,0 +1,1363 @@ +/******************************************************************************* +* \file qprc.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the QPRC +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "qprc/qprc.h" + +#if (defined(PDL_PERIPHERAL_QPRC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +static volatile stc_qprc_nfn_t* QprcGetNoisFilterPtr( volatile stc_qprcn_t *pstcQprc ); +#endif + +#if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) +static stc_qprc_intern_data_t *QprcGetInternDataPtr( volatile stc_qprcn_t *pstcQprc ); +#endif +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +/// Look-up table for all enabled ADC instances and their internal data +stc_qprc_instance_data_t m_astcQprcInstanceDataLut[QPRC_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_QPRC0 == PDL_ON) + { + &QPRC0, // pstcInstance QPRC + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + &QPRCNF0, // pstcInstanceNf QPRC-NF + #endif + { + // stcInternData (not initialized yet) + 0u, 0u, 0u, 0u, 0u, 0u + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_QPRC1 == PDL_ON) + { + &QPRC1, // pstcInstance QPRC + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + &QPRCNF1, // pstcInstanceNf QPRC-NF + #endif + { + // stcInternData (not initialized yet) + 0u, 0u, 0u, 0u, 0u, 0u + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_QPRC2 == PDL_ON) + { + &QPRC2, // pstcInstance QPRC + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + &QPRCNF2, // pstcInstanceNf QPRC-NF + #endif + { + // stcInternData (not initialized yet) + 0u, 0u, 0u, 0u, 0u, 0u + } + }, +#endif + +}; + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +/** + ****************************************************************************** + ** \brief Get the noise filter for a certain QPRC instance + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \return Pointer to the noise filter + ** + ******************************************************************************/ +static volatile stc_qprc_nfn_t *QprcGetNoisFilterPtr( volatile stc_qprcn_t *pstcQprc ) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < QPRC_INSTANCE_COUNT; u32Instance++) + { + if (pstcQprc == m_astcQprcInstanceDataLut[u32Instance].pstcInstance) + { + return m_astcQprcInstanceDataLut[u32Instance].pstcInstanceNf; + } + } + + return (volatile stc_qprc_nfn_t *)NULL; +} +#endif + +/** + ****************************************************************************** + ** \brief Get the internal data for a certain QPRC instance + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \return Pointer to internal data + ** + ******************************************************************************/ +static stc_qprc_intern_data_t *QprcGetInternDataPtr( volatile stc_qprcn_t *pstcQprc ) +{ + uint32_t u32Instance; + + for (u32Instance = 0u; u32Instance < QPRC_INSTANCE_COUNT; u32Instance++) + { + if (pstcQprc == m_astcQprcInstanceDataLut[u32Instance].pstcInstance) + { + return &m_astcQprcInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +#if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on QPRC instance + ** + ** \param pstcQprc Pointer to QPRC instance + ** + ******************************************************************************/ +static void QprcInitNvic(volatile stc_qprcn_t* pstcQprc) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC0_IRQn); + NVIC_EnableIRQ(QPRC0_IRQn); + NVIC_SetPriority(QPRC0_IRQn, PDL_IRQ_LEVEL_QPRC0); + #endif + #if (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC1_IRQn); + NVIC_EnableIRQ(QPRC1_IRQn); + NVIC_SetPriority(QPRC1_IRQn, PDL_IRQ_LEVEL_QPRC1); + #endif + #if (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC2_IRQn); + NVIC_EnableIRQ(QPRC2_IRQn); + NVIC_SetPriority(QPRC2_IRQn, PDL_IRQ_LEVEL_QPRC2); + #endif + #if (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC3_IRQn); + NVIC_EnableIRQ(QPRC3_IRQn); + NVIC_SetPriority(QPRC3_IRQn, PDL_IRQ_LEVEL_QPRC3); + #endif +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(DT_QPRC_IRQn); + NVIC_EnableIRQ(DT_QPRC_IRQn); + NVIC_SetPriority(DT_QPRC_IRQn, PDL_IRQ_LEVEL_DT_QPRC); +#else + NVIC_ClearPendingIRQ(DT_QPRC0_2_IRQn); + NVIC_EnableIRQ(DT_QPRC0_2_IRQn); + NVIC_SetPriority(DT_QPRC0_2_IRQn, PDL_IRQ_LEVEL_DT_QPRC); +#endif + +} + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on QPRC instance + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ******************************************************************************/ +static void QprcDeInitNvic(volatile stc_qprcn_t* pstcQprc) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + #if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC0_IRQn); + NVIC_DisableIRQ(QPRC0_IRQn); + NVIC_SetPriority(QPRC0_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #if (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC1_IRQn); + NVIC_DisableIRQ(QPRC1_IRQn); + NVIC_SetPriority(QPRC1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #if (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC2_IRQn); + NVIC_DisableIRQ(QPRC2_IRQn); + NVIC_SetPriority(QPRC2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif + #if (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) + NVIC_ClearPendingIRQ(QPRC3_IRQn); + NVIC_DisableIRQ(QPRC3_IRQn); + NVIC_SetPriority(QPRC3_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + NVIC_ClearPendingIRQ(DT_QPRC_IRQn); + NVIC_DisableIRQ(DT_QPRC_IRQn); + NVIC_SetPriority(DT_QPRC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + NVIC_ClearPendingIRQ(DT_QPRC0_2_IRQn); + NVIC_DisableIRQ(DT_QPRC0_2_IRQn); + NVIC_SetPriority(DT_QPRC0_2_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif + return; +} + +/** + ****************************************************************************** + ** \brief QPRC instance interrupt service routine + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] pstcQprcInternData Pointer to internal data + ******************************************************************************/ +void Qprc_IrqHandler ( volatile stc_qprcn_t *pstcQprc, + stc_qprc_intern_data_t *pstcQprcInternData ) +{ + if ((NULL == pstcQprc) || + (NULL == pstcQprcInternData)) + { + return; + } + + if (PdlSet == pstcQprc->QICRL_f.QPCMF) // QPCCR match ? + { + pstcQprc->QICRL_f.QPCMF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcMatchIrqCb) + { + pstcQprcInternData->pfnPcMatchIrqCb(); + } + } + + if (PdlSet == pstcQprc->QICRL_f.QPRCMF) // QPRCR match ? + { + pstcQprc->QICRL_f.QPRCMF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcRcMatchIrqCb) + { + pstcQprcInternData->pfnPcRcMatchIrqCb(); + } + } + + if (PdlSet == pstcQprc->QICRL_f.OFDF) //Overflow interrupt ? + { + pstcQprc->QICRL_f.OFDF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcOfUfZeroIrqCb) + { + pstcQprcInternData->pfnPcOfUfZeroIrqCb(QPRC_PC_OVERFLOW_INT); + } + } + + if (PdlSet == pstcQprc->QICRL_f.UFDF) //Underflow interrupt ? + { + pstcQprc->QICRL_f.UFDF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcOfUfZeroIrqCb) + { + pstcQprcInternData->pfnPcOfUfZeroIrqCb(QPRC_PC_UNDERFLOW_INT); + } + } + + if (PdlSet == pstcQprc->QICRL_f.ZIIF) //Zero interrupt ? + { + pstcQprc->QICRL_f.ZIIF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcOfUfZeroIrqCb) + { + pstcQprcInternData->pfnPcOfUfZeroIrqCb(QPRC_PC_ZERO_INDEX_INT); + } + } + + if (PdlSet == pstcQprc->QICRH_f.CDCF) //PC invert match ? + { + pstcQprc->QICRH_f.CDCF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcCountInvertIrqCb) + { + pstcQprcInternData->pfnPcCountInvertIrqCb(); + } + } + + if (PdlSet == pstcQprc->QECR_f.ORNGF) //RC outrange ? + { + pstcQprc->QECR_f.ORNGF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnRcOutrangeIrqCb) + { + pstcQprcInternData->pfnRcOutrangeIrqCb(); + } + } + + if (PdlSet == pstcQprc->QICRH_f.QPCNRCMF) //PcMatch and RcMatch ? + { + pstcQprc->QICRH_f.QPCNRCMF = PdlClr; // Clear interrupt + if (NULL != pstcQprcInternData->pfnPcMatchRcMatchIrqCb) + { + pstcQprcInternData->pfnPcMatchRcMatchIrqCb(); + } + } + + return; +} + +#endif + +/** + ****************************************************************************** + ** \brief Initialize QPRC + ** + ** This function initializes an QPRC module and sets up the internal + ** data structures + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] pstcConfig Pointer to QPRC module configuration + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcQprc == NULL + ** - pstcConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Qprc_Init( volatile stc_qprcn_t* pstcQprc, + const stc_qprc_config_t* pstcConfig ) +{ + stc_qprc_intern_data_t* pstcQprcInternData; + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_qprc_nfn_t *pstcQprcNoiseFilter; + pstcQprcNoiseFilter = QprcGetNoisFilterPtr(pstcQprc); + if(NULL == pstcQprcNoiseFilter) + { + return ErrorInvalidParameter; + } +#endif + if ( (NULL == pstcQprc) || + (NULL == pstcConfig) + ) + { + return ErrorInvalidParameter; + } + + pstcQprcInternData = QprcGetInternDataPtr(pstcQprc); + + if (NULL == pstcQprcInternData) + { + return ErrorInvalidParameter; + } + + // Set AIN and BIN swap function + pstcQprc->QCR_f.SWAP = ((TRUE == pstcConfig->bSwapAinBin) ? 1u : 0u); + + // Set the compare mode of Position counter + switch (pstcConfig->enCompareMode) + { + case QprcCompareWithPosition: + pstcQprc->QCR_f.RSEL = 0u; + break; + case QprcCompareWithRevolution: + pstcQprc->QCR_f.RSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set ZIN active edge + switch (pstcConfig->enZinEdge) + { + case QprcZinDisable: // Disables edge and level detection + pstcQprc->QCR_f.CGE = 0u; + break; + case QprcZinFallingEdge: // ZIN active at falling edge + pstcQprc->QCR_f.CGSC = 0u; + pstcQprc->QCR_f.CGE = 1u; + break; + case QprcZinRisingEdge: // ZIN active at rising edge + pstcQprc->QCR_f.CGSC = 0u; + pstcQprc->QCR_f.CGE = 2u; + break; + case QprcZinBothEdges: // ZIN active at falling or rising edge + pstcQprc->QCR_f.CGSC = 0u; + pstcQprc->QCR_f.CGE = 3u; + break; + case QprcZinLowLevel: // ZIN active at low level detected + pstcQprc->QCR_f.CGSC = 1u; + pstcQprc->QCR_f.CGE = 1u; + break; + case QprcZinHighLevel: // ZIN active at high level detected + pstcQprc->QCR_f.CGSC = 1; + pstcQprc->QCR_f.CGE = 2u; + break; + default: + return ErrorInvalidParameter; + } + + // Set BIN active edge + switch (pstcConfig->enBinEdge) + { + case QprcBinDisable: // Disables edge detection + pstcQprc->QCR_f.BES = 0u; + break; + case QprcBinFallingEdge: // BIN active at falling edge + pstcQprc->QCR_f.BES = 1u; + break; + case QprcBinRisingEdge: // BIN active at rising edge + pstcQprc->QCR_f.BES = 2u; + break; + case QprcBinBothEdges: // BIN active at falling or rising edge + pstcQprc->QCR_f.BES = 3u; + break; + default: + return ErrorInvalidParameter; + } + + // Set AIN active edge + switch (pstcConfig->enAinEdge) + { + case QprcBinDisable: // Disables edge detection + pstcQprc->QCR_f.AES = 0u; + break; + case QprcBinFallingEdge: // BIN active at falling edge + pstcQprc->QCR_f.AES = 1u; + break; + case QprcBinRisingEdge: // BIN active at rising edge + pstcQprc->QCR_f.AES = 2u; + break; + case QprcBinBothEdges: // BIN active at falling or rising edge + pstcQprc->QCR_f.AES = 3u; + break; + default: + return ErrorInvalidParameter; + } + + // Set PC reset mask count + switch (pstcConfig->enPcResetMask) + { + case QprcResetMaskDisable: // No reset mask + pstcQprc->QCR_f.PCRM = 0u; + break; + case QprcResetMask2Times: + pstcQprc->QCR_f.PCRM = 1u; + break; + case QprcResetMask4Times: + pstcQprc->QCR_f.PCRM = 2u; + break; + case QprcResetMask8Times: + pstcQprc->QCR_f.PCRM = 3u; + break; + default: + return ErrorInvalidParameter; + } + + // Set PC compare range + pstcQprc->QECR_f.ORNGMD = (TRUE == pstcConfig->b8KValue) ? 1u : 0u ; // TRUE: Outrange mode from 0 to 0x7FFF, FALSE: Outrange mode from 0 to 0xFFFF: + +#if ((PDL_MCU_TYPE >= PDL_FM4_TYPE3) && (PDL_MCU_TYPE != PDL_FM4_TYPE6)) + // Set phase edge change + pstcQprc->QECR_f.PEC = ((TRUE == pstcConfig->bPhaseEdge) ? 1u : 0u); +#endif + + /* Set QPRC Noise Filter */ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcQprcNoiseFilter = QprcGetNoisFilterPtr(pstcQprc); + pstcQprcNoiseFilter->NFCTLA_f.AINMD = (TRUE == pstcConfig->stcAinFilter.bInputMask) ? 1u : 0u ; + pstcQprcNoiseFilter->NFCTLA_f.AINLV = (TRUE == pstcConfig->stcAinFilter.bInputInvert) ? 1u : 0u ; + switch (pstcConfig->stcAinFilter.enWidth) + { + case QprcNoFilter: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 0u; + break; + case QprcFilterWidth4Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 1u; + break; + case QprcFilterWidth8Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 2u; + break; + case QprcFilterWidth16Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 3u; + break; + case QprcFilterWidth32Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 4u; + break; + case QprcFilterWidth64Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 5u; + break; + case QprcFilterWidth128Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 6u; + break; + case QprcFilterWidth256Pclk: + pstcQprcNoiseFilter->NFCTLA_f.AINNWS = 7u; + break; + default: + return ErrorInvalidParameter; + } + + pstcQprcNoiseFilter->NFCTLB_f.BINMD = (TRUE == pstcConfig->stcBinFilter.bInputMask) ? 1u : 0u ; + pstcQprcNoiseFilter->NFCTLB_f.BINLV = (TRUE == pstcConfig->stcBinFilter.bInputInvert) ? 1u : 0u ; + switch (pstcConfig->stcBinFilter.enWidth) + { + case QprcNoFilter: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 0u; + break; + case QprcFilterWidth4Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 1u; + break; + case QprcFilterWidth8Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 2u; + break; + case QprcFilterWidth16Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 3u; + break; + case QprcFilterWidth32Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 4u; + break; + case QprcFilterWidth64Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 5u; + break; + case QprcFilterWidth128Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 6u; + break; + case QprcFilterWidth256Pclk: + pstcQprcNoiseFilter->NFCTLB_f.BINNWS = 7u; + break; + default: + return ErrorInvalidParameter; + } + + pstcQprcNoiseFilter->NFCTLZ_f.ZINMD = (TRUE == pstcConfig->stcCinFilter.bInputMask) ? 1u : 0u ; + pstcQprcNoiseFilter->NFCTLZ_f.ZINLV = (TRUE == pstcConfig->stcCinFilter.bInputInvert) ? 1u : 0u ; + switch (pstcConfig->stcCinFilter.enWidth) + { + case QprcNoFilter: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 0u; + break; + case QprcFilterWidth4Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 1u; + break; + case QprcFilterWidth8Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 2u; + break; + case QprcFilterWidth16Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 3u; + break; + case QprcFilterWidth32Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 4u; + break; + case QprcFilterWidth64Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 5u; + break; + case QprcFilterWidth128Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 6u; + break; + case QprcFilterWidth256Pclk: + pstcQprcNoiseFilter->NFCTLZ_f.ZINNWS = 7u; + break; + default: + return ErrorInvalidParameter; + } +#endif + +#if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) + // Set interrupt enable + if(pstcConfig->pstcIrqEn != NULL) + { + if (TRUE == pstcConfig->pstcIrqEn->bQprcPcMatchIrq) + { + pstcQprc->QICRL_f.QPCMIE = 1u; + } + + if (TRUE == pstcConfig->pstcIrqEn->bQprcPcRcMatchIrq) + { + pstcQprc->QICRL_f.QPRCMIE = 1u; + } + + if (TRUE == pstcConfig->pstcIrqEn->bQprcPcMatchRcMatchIrq) + { + pstcQprc->QICRH_f.QPCNRCMIE = 1u; + } + + if (TRUE == pstcConfig->pstcIrqEn->bQprcPcOfUfZeroIrq) + { + pstcQprc->QICRL_f.OUZIE = 1u; + } + + if (TRUE == pstcConfig->pstcIrqEn->bQprcPcCountInvertIrq) + { + pstcQprc->QICRH_f.CDCIE = 1u; + } + + if (TRUE == pstcConfig->pstcIrqEn->bQprcRcOutrangeIrq) + { + pstcQprc->QECR_f.ORNGIE = 1u; + } + + } + + // Set interrupt callback functions + if(NULL != pstcConfig->pstcIrqCb) + { + pstcQprcInternData->pfnPcMatchIrqCb = pstcConfig->pstcIrqCb->pfnPcMatchIrqCb; + pstcQprcInternData->pfnPcRcMatchIrqCb = pstcConfig->pstcIrqCb->pfnPcRcMatchIrqCb; + pstcQprcInternData->pfnPcMatchRcMatchIrqCb = pstcConfig->pstcIrqCb->pfnPcMatchRcMatchIrqCb; + pstcQprcInternData->pfnPcOfUfZeroIrqCb = pstcConfig->pstcIrqCb->pfnPcOfUfZeroIrqCb; + pstcQprcInternData->pfnPcCountInvertIrqCb = pstcConfig->pstcIrqCb->pfnPcCountInvertIrqCb; + pstcQprcInternData->pfnRcOutrangeIrqCb = pstcConfig->pstcIrqCb->pfnRcOutrangeIrqCb; + } + + // Set NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + QprcInitNvic(pstcQprc); + } + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize QPRC + ** + ** This function clears an QPRC instance. + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok QPRC instance cleared + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcQprc == NULL + ******************************************************************************/ +en_result_t Qprc_DeInit( volatile stc_qprcn_t* pstcQprc, boolean_t bTouchNvic ) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_qprc_nfn_t *pstcQprcNoiseFilter; + pstcQprcNoiseFilter = QprcGetNoisFilterPtr(pstcQprc); + if(NULL == pstcQprcNoiseFilter) + { + return ErrorInvalidParameter; + } +#endif + + if(NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + pstcQprc->QCRL = 0u; + pstcQprc->QCRH = 0u; + pstcQprc->QPCR = 0u; + pstcQprc->QRCR = 0u; + pstcQprc->QPCCR = 0u; + pstcQprc->QPRCR = 0u; + pstcQprc->QICRL = 0u; + pstcQprc->QICRH = 0u; + pstcQprc->QMPR = 0xFFFFu; +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + pstcQprcNoiseFilter->NFCTLA = 0u; + pstcQprcNoiseFilter->NFCTLB = 0u; + pstcQprcNoiseFilter->NFCTLZ = 0u; +#endif + +#if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) + if(TRUE == bTouchNvic) + { + QprcDeInitNvic(pstcQprc); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Stop Position Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval Ok Stop Position Counter counting successfully + ** \retval ErrorInvalidParameter pstcQprc == NULL + ******************************************************************************/ +en_result_t Qprc_StopPcCount(volatile stc_qprcn_t *pstcQprc) +{ + // Check for NULL pointer + if (NULL == pstcQprc) + { + return ErrorInvalidParameter ; + } + + pstcQprc->QCR_f.PSTP = 1u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Restart Position Counter from stop status + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval Ok Restart Position Counter successfully + ** \retval ErrorInvalidParameter pstcQprc == NULL + ******************************************************************************/ +en_result_t Qprc_RestartPcCount(volatile stc_qprcn_t *pstcQprc) +{ + // Check for NULL pointer + if (NULL == pstcQprc) + { + return ErrorInvalidParameter ; + } + + pstcQprc->QCR_f.PSTP = 0u; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set count value of Position counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] u16PcValue Count value + ** + ** \retval Ok Count value has been setup + ** \retval ErrorInvalidParameter pstcQprc == NULL + ******************************************************************************/ +en_result_t Qprc_SetPcCount ( volatile stc_qprcn_t *pstcQprc, + uint16_t u16PcValue ) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + pstcQprc->QPCR = u16PcValue; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get count value of Position counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval Count value + ** + ** \note If pstcQprc = NULL, the return value will be 0xFFFF. + ******************************************************************************/ +uint16_t Qprc_GetPcCount ( volatile stc_qprcn_t *pstcQprc ) +{ + if (NULL == pstcQprc) + { + return 0xFFFFu; + } + + return (uint16_t)pstcQprc->QPCR; +} + +/** + ****************************************************************************** + ** \brief Set count value of Revolution Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] u16RcValue Count value + ** + ** \retval Ok Count value has been setup + ** \retval ErrorInvalidParameter pstcQprc == NULL + ******************************************************************************/ +en_result_t Qprc_SetRcCount ( volatile stc_qprcn_t *pstcQprc, + uint16_t u16RcValue ) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + pstcQprc->QRCR = u16RcValue; + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Get count value of Revolution Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval Count value + ** + ** \note If pstcQprc = NULL, the return value will be 0xFFFF. + ******************************************************************************/ +uint16_t Qprc_GetRcCount ( volatile stc_qprcn_t *pstcQprc ) +{ + if (NULL == pstcQprc) + { + return 0xFFFFu; + } + + return (uint16_t)pstcQprc->QPCR; +} + +/** + ****************************************************************************** + ** \brief Set maximum count value of Position Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] u16PcMaxValue Maximum count value + ** + ** \retval Ok Maximum count value has been setup + ** \retval ErrorInvalidParameter pstcQprc == NULL + ******************************************************************************/ +en_result_t Qprc_SetPcMaxValue( volatile stc_qprcn_t *pstcQprc, + uint16_t u16PcMaxValue ) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + pstcQprc->QMPR = u16PcMaxValue; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get maximum count value of Position Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval PcMaxValue + ** + ** \note If pstcQprc = NULL, the return value will be 0xFFFF. + ******************************************************************************/ +uint16_t Qprc_GetPcMaxValue(volatile stc_qprcn_t *pstcQprc) +{ + if (NULL == pstcQprc) + { + return 0xFFFFu; + } + + return (uint16_t)pstcQprc->QMPR; +} + +/** + ****************************************************************************** + ** \brief Set compare value of Position counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] u16PcValue Compare value + ** + ** \retval Ok Compare value has been setup + ** \retval ErrorInvalidParameter pstcQprc == NULL + ******************************************************************************/ + +en_result_t Qprc_SetPcCompareValue( volatile stc_qprcn_t *pstcQprc, + uint16_t u16PcValue ) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + pstcQprc->QPCCR = u16PcValue; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get compare value of Position counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval Count value + ******************************************************************************/ + +uint16_t Qprc_GetPcCompareValue( volatile stc_qprcn_t *pstcQprc) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + return (uint16_t)pstcQprc->QPCCR; +} + + +/** + ****************************************************************************** + ** \brief Set compare value of Position and Revolution Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] u16PcRcValue Compare value + ** + ** \retval Ok Compare value has been setup + ** \retval ErrorInvalidParameter pstcQprc == NULL + ** + ** \note the object with which this value is compared depends on the compare + ** mode setting in the Qprc_Init(), plesae refer to the structure type + ** #en_qprc_compmode_t. + ******************************************************************************/ +en_result_t Qprc_SetPcRcCompareValue( volatile stc_qprcn_t *pstcQprc, + uint16_t u16PcRcValue ) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + pstcQprc->QPRCR = u16PcRcValue; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get compare value of Position and Revolution Counter + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval Count value + ** + ** If pstcQprc = NULL, the return will be 0xFFFF. + ******************************************************************************/ +uint16_t Qprc_GetPcRcCompareValue(volatile stc_qprcn_t *pstcQprc) +{ + if (NULL == pstcQprc) + { + return 0xFFFFu; + } + + return (uint16_t)pstcQprc->QPRCR; +} + +/** + ****************************************************************************** + ** \brief Set Position Counter mode + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] enMode Position Counter mode + ** + ** \retval Ok Position Counter mode has been setup + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcQprc == NULL + ** - enMode > QprcPcMode3 + ** - Other invalid configuration + ******************************************************************************/ + +en_result_t Qprc_ConfigPcMode( volatile stc_qprcn_t *pstcQprc, + en_qprc_pcmode_t enMode ) +{ + if ((NULL == pstcQprc) || + (enMode > QprcPcMode3)) + { + return ErrorInvalidParameter; + } + + switch(enMode) + { + case QprcPcMode0: //Disable position counter + { + pstcQprc->QCR_f.PCM = 0u; + } + break; + + case QprcPcMode1: //Increments with AIN active edge and decrements with BIN active edge + { + pstcQprc->QCR_f.PCM = 1u; + } + break; + + case QprcPcMode2: //Phase difference count mode: Counts up if AIN is leading BIN, down if BIN leading. + { + pstcQprc->QCR_f.PCM = 2u; + } + break; + + case QprcPcMode3: // Directional count mode: Counts up/down with BIN active edge and AIN level + { + pstcQprc->QCR_f.PCM = 3u; + } + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set Revolution Counter mode + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] enMode Revolution Counter mode + ** + ** \retval Ok Revolution Counter mode has been setup + ** \retval ErrorInvalidParameter If one of following confitions are met: + ** - pstcQprc == NULL + ** - enMode > QprcRcMode3 + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Qprc_ConfigRcMode( volatile stc_qprcn_t *pstcQprc, + en_qprc_rcmode_t enMode ) +{ + if ((NULL == pstcQprc) || + (enMode > QprcRcMode3)) + { + return ErrorInvalidParameter; + } + + switch(enMode) + { + case QprcRcMode0: // RC_Mode0: Disable revolution counter + { + pstcQprc->QCR_f.RCM = 0u; + } + break; + + case QprcRcMode1: // Up/down count of RC with ZIN active edge + { + pstcQprc->QCR_f.RCM = 1u; + } + break; + + case QprcRcMode2: // Up/down count of RC on over or underflow in position count match + { + pstcQprc->QCR_f.RCM = 2u; + } + break; + + case QprcRcMode3: // Up/down count of RC on over or underflow in position count match and ZIN active edge + { + pstcQprc->QCR_f.RCM = 3u; + } + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable QPRC interrupt + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] enIrqSel Interrupt type + ** + ** \retval Ok QPRC interrupts has been enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcQprc invalid + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Qprc_EnableIrq( volatile stc_qprcn_t* pstcQprc, en_qprc_irq_sel_t enIrqSel) +{ + if ( NULL == pstcQprc ) + { + return ErrorInvalidParameter; + } + + switch(enIrqSel) + { + case QprcPcOfUfZeroIrq: + pstcQprc->QICRL_f.OUZIE = 1u; + break; + + case QprcPcMatchIrq: + pstcQprc->QICRL_f.QPCMIE = 1u; + break; + + case QprcPcRcMatchIrq: + pstcQprc->QICRL_f.QPRCMIE = 1u; + break; + + case QprcPcMatchRcMatchIrq: + pstcQprc->QICRH_f.QPCNRCMIE = 1u; + break; + + case QprcPcCountInvertIrq: + pstcQprc->QICRH_f.CDCIE = 1u; + break; + + case QprcRcOutrangeIrq: + pstcQprc->QECR_f.ORNGIE = 1u; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable QPRC interrupt + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] enIrqSel Interrupt type + ** + ** \retval Ok PC match interrupt enable bit has been setup + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcQprc invalid + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Qprc_DisableIrq( volatile stc_qprcn_t* pstcQprc, en_qprc_irq_sel_t enIrqSel) +{ + if ( NULL == pstcQprc ) + { + return ErrorInvalidParameter; + } + + switch(enIrqSel) + { + case QprcPcOfUfZeroIrq: + pstcQprc->QICRL_f.OUZIE = 0u; + break; + + case QprcPcMatchIrq: + pstcQprc->QICRL_f.QPCMIE = 0u; + break; + + case QprcPcRcMatchIrq: + pstcQprc->QICRL_f.QPRCMIE = 0u; + break; + + case QprcPcMatchRcMatchIrq: + pstcQprc->QICRH_f.QPCNRCMIE = 0u; + break; + + case QprcPcCountInvertIrq: + pstcQprc->QICRH_f.CDCIE = 0u; + break; + + case QprcRcOutrangeIrq: + pstcQprc->QECR_f.ORNGIE = 0u; + break; + + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of QPRC + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] enIrqSel Interrupt type + ** + ** \retval PdlClr Interrupt doesn't occur selected by enIntType + ** \retval PdlSet Interrupt occurs selected by enIntType + ******************************************************************************/ +en_irq_flag_t Qprc_GetIrqFlag( volatile stc_qprcn_t *pstcQprc, + en_qprc_irq_sel_t enIrqSel) +{ + en_irq_flag_t enIrqFlag = PdlClr; + + if (NULL == pstcQprc) + { + return PdlClr; + } + + switch(enIrqSel) + { + case QprcPcOfUfZeroIrq: + if(PdlSet == pstcQprc->QICRL_f.ZIIF) + { + enIrqFlag = PdlSet; + break; + } + + if(PdlSet == pstcQprc->QICRL_f.OFDF) + { + enIrqFlag = PdlSet; + break; + } + + if(PdlSet == pstcQprc->QICRL_f.UFDF) + { + enIrqFlag = PdlSet; + break; + } + break; + + case QprcPcMatchIrq: + enIrqFlag = (1u == pstcQprc->QICRL_f.QPCMF) ? PdlSet : PdlClr ; + break; + + case QprcPcRcMatchIrq: + enIrqFlag = (1u == pstcQprc->QICRL_f.QPRCMF) ? PdlSet : PdlClr ; + break; + + case QprcPcMatchRcMatchIrq: + enIrqFlag = (1u == pstcQprc->QICRH_f.QPCNRCMF) ? PdlSet : PdlClr ; + break; + + case QprcPcCountInvertIrq: + enIrqFlag = (1u == pstcQprc->QICRH_f.CDCF) ? PdlSet : PdlClr ; + break; + + case QprcRcOutrangeIrq: + enIrqFlag = (1u == pstcQprc->QECR_f.ORNGF) ? PdlSet : PdlClr ; + break; + + default: + break; + } + + return enIrqFlag; +} + + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of QPRC + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** \param [in] enIrqSel Interrupt type + ** + ** \retval Ok Clear interrupt flag successfully + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcQprc invalid + ** - enIntType > QprcRcOutrangeInt + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Qprc_ClrIrqFlag( volatile stc_qprcn_t *pstcQprc, + en_qprc_irq_sel_t enIrqSel) +{ + if (NULL == pstcQprc) + { + return ErrorInvalidParameter; + } + + switch(enIrqSel) + { + case QprcPcOfUfZeroIrq: + pstcQprc->QICRL_f.ZIIF = PdlClr; + pstcQprc->QICRL_f.OFDF = PdlClr; + pstcQprc->QICRL_f.UFDF = PdlClr; + break; + + case QprcPcMatchIrq: + pstcQprc->QICRL_f.QPCMF = PdlClr; + break; + + case QprcPcRcMatchIrq: + pstcQprc->QICRL_f.QPRCMF = PdlClr; + break; + + case QprcPcMatchRcMatchIrq: + pstcQprc->QICRH_f.QPCNRCMF = PdlClr; + break; + + case QprcPcCountInvertIrq: + pstcQprc->QICRH_f.CDCF = PdlClr; + break; + + case QprcRcOutrangeIrq: + pstcQprc->QECR_f.ORNGF = PdlClr; + break; + + default: + break; + } + + return Ok; + +} + +/** + ****************************************************************************** + ** \brief Get last position counter flow direction + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval PdlClr The position counter was incremented. + ** \retval PdlSet The position counter was decremented. + ******************************************************************************/ +en_stat_flag_t Qprc_GetPcOfUfDir( volatile stc_qprcn_t *pstcQprc ) +{ + en_stat_flag_t enStatFlag = PdlClr; + + if (NULL == pstcQprc) + { + return PdlClr; + } + + enStatFlag = (1 == pstcQprc->QICRH_f.DIROU) ? PdlSet : PdlClr ; + return enStatFlag; +} + +/** + ****************************************************************************** + ** \brief Get last position counter direction + ** + ** \param [in] pstcQprc Pointer to QPRC instance + ** + ** \retval PdlClr The position counter was incremented. + ** \retval PdlSet The position counter was decremented. + ******************************************************************************/ +en_stat_flag_t Qprc_GetPcDir( volatile stc_qprcn_t *pstcQprc ) +{ + en_stat_flag_t enStatFlag = PdlClr; + + if (NULL == pstcQprc) + { + return PdlClr; + } + + enStatFlag = (1u == pstcQprc->QICRH_f.DIRPC) ? PdlSet : PdlClr ; + + return enStatFlag; +} + +#endif // #if (defined(PDL_PERIPHERAL_QPRC_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/qprc/qprc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/qprc/qprc.h new file mode 100644 index 0000000000..f66b7c4bc7 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/qprc/qprc.h @@ -0,0 +1,443 @@ +/******************************************************************************* +* \file qprc.h +* +* \version 1.20 +* +* \brief Headerfile for QPRC functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __QPRC_H__ +#define __QPRC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_QPRC_ACTIVE)) + +/** +* \defgroup GroupQPRC Quadrature Position/Revolution Counter (QPRC) +* \{ +* \defgroup GroupQPRC_Macros Macros +* \defgroup GroupQPRC_Functions Functions +* \defgroup GroupQPRC_DataStructures Data Structures +* \defgroup GroupQPRC_Types Enumerated Types +* \defgroup GroupQPRC_GlobalVariables Global Variables +* \} +*/ + +/** +* \addtogroup GroupQPRC +* \{ +* The Quadrature Position/Revolution Counter (QPRC) peripheral is typically +* used in motor control applications to track the position, speed, or rotation of a motor.
+* The position counter (PC) receives an input signal from two pins denoted AIN and BIN. +* The counter increments or decrements based on the signal edge on the pins (configurable). +* The revolution counter (RC) receives an input from the ZIN pin and/or the output of the +* position counter (underflow or overflow). The counter increments or decrements based on +* your configuration choices.
+* There are two compare values: the Position compare value, and the Position and +* Revolution compare value (PCRC).
+* All compare values and counters are 16-bit values.
+* There is a configurable noise filter for the signal on each of the three input pins.
+* Based on configuration choices, you can generate (and handle) interrupts when:
+* * The PC underflows or overflows +* * The PC matches the PC compare value +* * The PC and RC match +* * The PC matches the PC compare value and the RC matches the PCRC compare value +* * The PC is inverted (changes direction) +* * The RC is out of range +* \section SectionQPRC_ConfigurationConsideration Configuration Consideration +* To set up a QPRC, you provide configuration parameters in the stc_qprc_config_t structure. +* For example, you set the operating mode for the position counter: up/down count, +* phase difference count, or directional count. You set the operating mode for the RC: ZIN +* trigger mode, PC underflow/overflow mode, or both ZIN and PC underflow/overflow. You +* specify the valid signal edege for each pin: rising, falling, or both.
+* After setting all the fields, call Qprc_Init() with the configuration structure and a +* hardware pointer to the QPRC channel.
+* At runtime you use API function calls to:
+* * Enable or disable an interrupt +* * Stop, start, get, set or set the max value of the PC counter +* * Get the most recent direction of the PC counter (it was incremented or decremented) +* * Get or set the RC counter +* * Get or set the PC compare value +* * Get or set the PCRC compare value +* * Set the operating mode for either the PC or RC
+* When an enabled interrupt occurs, the interrupt flag is cleared and control passes to +* the callback function. You can also use polling to manage interrupts. With polling mode, +* use Qprc_GetIrqFlag() to poll for an interrupt. Clear the interrupt flag with +* Qprc_ClrIrqFlag().
+* To stop the QPRC, use Qprc_ConfigPcMode() and Qprc_ConfigRcMode() to set each to Mode 0 +*(disabled). Use QPRC_DisableIrq() to disable each QPRC interrupt. +* \section SectionQPRC_MoreInfo More Information +* For more information on the QPRC peripheral, refer to
+* FM0+ Family 32-Bit Microcontroller Peripheral Manual Timer Part
+* FM4 Family 32-Bit Microcontroller Peripheral Manual Timer Part
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* +*/ + +/** +* \addtogroup GroupQPRC_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_qprcn_t FM_QPRC_TypeDef + +#define QPRC0 (*((volatile stc_qprcn_t *) FM_QPRC0_BASE)) +#define QPRC1 (*((volatile stc_qprcn_t *) FM_QPRC1_BASE)) +#define QPRC2 (*((volatile stc_qprcn_t *) FM_QPRC2_BASE)) +#define QPRC3 (*((volatile stc_qprcn_t *) FM_QPRC3_BASE)) + +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) +#define stc_qprc_nfn_t FM_QPRC_NF_TypeDef + +#define QPRCNF0 (*((volatile stc_qprc_nfn_t *) FM_QPRC0_NF_BASE)) +#define QPRCNF1 (*((volatile stc_qprc_nfn_t *) FM_QPRC1_NF_BASE)) +#define QPRCNF2 (*((volatile stc_qprc_nfn_t *) FM_QPRC2_NF_BASE)) +#define QPRCNF3 (*((volatile stc_qprc_nfn_t *) FM_QPRC3_NF_BASE)) +#endif + +#define QPRC_INSTANCE_COUNT (PDL_PERIPHERAL_ENABLE_QPRC0 == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_QPRC1 == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_QPRC2 == PDL_ON ? 1u : 0u) + \ + (PDL_PERIPHERAL_ENABLE_QPRC3 == PDL_ON ? 1u : 0u) + +#define QPRC_PC_OVERFLOW_INT 0u +#define QPRC_PC_UNDERFLOW_INT 1u +#define QPRC_PC_ZERO_INDEX_INT 2u + +/** \} GroupQPRC_Macros */ + +/** +* \addtogroup GroupQPRC_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define an index for each QPRC instance + ******************************************************************************/ +typedef enum en_qprc_instance_index +{ +#if (PDL_PERIPHERAL_ENABLE_QPRC0 == PDL_ON) + QprcInstanceIndexQprc0 = 0u, ///< Instance index of QPRC0 +#endif +#if (PDL_PERIPHERAL_ENABLE_QPRC1 == PDL_ON) + QprcInstanceIndexQprc1, ///< Instance index of QPRC1 +#endif +#if (PDL_PERIPHERAL_ENABLE_QPRC2 == PDL_ON) + QprcInstanceIndexQprc2, ///< Instance index of QPRC2 +#endif +#if (PDL_PERIPHERAL_ENABLE_QPRC3 == PDL_ON) + QprcInstanceIndexQprc3, ///< Instance index of QPRC2 +#endif +} en_qprc_instance_index_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define position counter mode + ******************************************************************************/ +typedef enum en_qprc_pcmode +{ + QprcPcMode0 = 0u, ///< PC_Mode0: Disable position counter + QprcPcMode1 = 1u, ///< PC_Mode1: Increments with AIN active edge and decrements with BIN active edge + QprcPcMode2 = 2u, ///< PC_Mode2: Phase difference count mode: Counts up if AIN is leading BIN, down if BIN leading. + QprcPcMode3 = 3u, ///< PC_Mode3: Directional count mode: Counts up/down with BIN active edge and AIN level +} en_qprc_pcmode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define revolution counter mode + ******************************************************************************/ +typedef enum en_qprc_rcmode +{ + QprcRcMode0 = 0u, ///< RC_Mode0: Disable revolution counter + QprcRcMode1 = 1u, ///< RC_Mode1: Up/down count of revolution counter with ZIN active edge + QprcRcMode2 = 2u, ///< RC_Mode2: Up/down count of revolution counter on overflow or underflow in position count match + QprcRcMode3 = 3u, ///< RC_Mode3: Up/down count of revolution counter on overflow or underflow in position count match and ZIN active edge +} en_qprc_rcmode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define ZIN valid edge + ******************************************************************************/ +typedef enum en_qprc_zinedge +{ + QprcZinDisable = 0u, ///< Disables edge and level detection + QprcZinFallingEdge = 1u, ///< ZIN active at falling edge + QprcZinRisingEdge = 2u, ///< ZIN active at rising edge + QprcZinBothEdges = 3u, ///< ZIN active at falling or rising edge + QprcZinLowLevel = 4u, ///< ZIN active at low level detected + QprcZinHighLevel = 5u, ///< ZIN active at high level detected +} en_qprc_zinedge_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define BIN valid edge + ******************************************************************************/ +typedef enum en_qprc_binedge +{ + QprcBinDisable = 0u, ///< Disables edge detection + QprcBinFallingEdge = 1u, ///< BIN active at falling edge + QprcBinRisingEdge = 2u, ///< BIN active at rising edge + QprcBinBothEdges = 3u, ///< BIN active at falling or rising edge +} en_qprc_binedge_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define AIN valid edge + ******************************************************************************/ +typedef enum en_qprc_ainedge +{ + QprcAinDisable = 0u, ///< Disables edge detection + QprcAinFallingEdge = 1u, ///< AIN active at falling edge + QprcAinRisingEdge = 2u, ///< AIN active at rising edge + QprcAinBothEdges = 3u, ///< AIN active at falling or rising edge +} en_qprc_ainedge_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define reset mask times of position counter + ******************************************************************************/ +typedef enum en_qprc_pcresetmask +{ + QprcResetMaskDisable = 0u, ///< No reset mask + QprcResetMask2Times = 1u, ///< The position counter reset or a revolution counter count-up or -down events are ignored until the position counter changes twice + QprcResetMask4Times = 2u, ///< The position counter reset or a revolution counter count-up or -down events are ignored until the position counter changes four times + QprcResetMask8Times = 3u, ///< The position counter reset or a revolution counter count-up or -down events are ignored until the position counter changes eight times +} en_qprc_pcresetmask_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define compare object of QPRCR register + ******************************************************************************/ +typedef enum en_qprc_compmode +{ + QprcCompareWithPosition = 0u, ///< Compares the value of the QPRC Position and Revolution Counter Compare Register (QPRCR) with that of the position counter. + QprcCompareWithRevolution = 1u, ///< Compares the value of the QPRC Position and Revolution Counter Compare Register (QPRCR) with that of the revolution counter. +} en_qprc_compmode_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define QPRC interrupt type + ******************************************************************************/ +typedef enum en_qprc_irq_sel +{ + QprcPcOfUfZeroIrq = 0u, ///< Overflow, underflow, zero match interrupt of position counter + QprcPcMatchIrq = 1u, ///< PC match interrupt of position counter + QprcPcRcMatchIrq = 2u, ///< PC and RC match interrupt + QprcPcMatchRcMatchIrq = 3u, ///< PC match and RC match interrupt + QprcPcCountInvertIrq = 4u, ///< PC invert interrupt + QprcRcOutrangeIrq = 5u, ///< RC outrange interrupt + +}en_qprc_irq_sel_t; +/** + ****************************************************************************** + ** \brief Enumeration to define QPRC filter width + ******************************************************************************/ +typedef enum en_qprc_filter_width +{ + QprcNoFilter = 0u, ///< No filter + QprcFilterWidth4Pclk = 1u, ///< QPRC filter width: 4 PCLK + QprcFilterWidth8Pclk = 2u, ///< QPRC filter width: 8 PCLK + QprcFilterWidth16Pclk = 3u, ///< QPRC filter width: 16 PCLK + QprcFilterWidth32Pclk = 4u, ///< QPRC filter width: 32 PCLK + QprcFilterWidth64Pclk = 5u, ///< QPRC filter width: 64 PCLK + QprcFilterWidth128Pclk = 6u, ///< QPRC filter width: 128 PCLK + QprcFilterWidth256Pclk = 7u, ///< QPRC filter width: 256 PCLK + +}en_qprc_filter_width_t; + +/** \} GroupQPRC_Types */ + +/** +* \addtogroup GroupQPRC_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define QPRC interrupt selection + ******************************************************************************/ +typedef struct stc_qprc_irq_en +{ + boolean_t bQprcPcOfUfZeroIrq; ///< Overflow, underflow, zero match interrupt of position counter, 1: selected, 0: not selected + boolean_t bQprcPcMatchIrq; ///< PC match interrupt of position counter, 1: selected, 0: not selected + boolean_t bQprcPcRcMatchIrq; ///< PC and RC match interrupt, 1: selected, 0: not selected + boolean_t bQprcPcMatchRcMatchIrq; ///< PC match and RC match interrupt, 1: selected, 0: not selected + boolean_t bQprcPcCountInvertIrq; ///< PC invert interrupt, 1: selected, 0: not selected + boolean_t bQprcRcOutrangeIrq; ///< RC outrange interrupt, 1: selected, 0: not selected + +}stc_qprc_irq_en_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define QPRC interrupt callback function + ******************************************************************************/ +typedef struct stc_qprc_irq_cb +{ + func_ptr_arg1_t pfnPcOfUfZeroIrqCb; ///< Overflow, underflow, zero match interrupt callback function of position counter + func_ptr_t pfnPcMatchIrqCb; ///< PC match interrupt callback function of position counter + func_ptr_t pfnPcRcMatchIrqCb; ///< PC and RC match interrupt callback function + func_ptr_t pfnPcMatchRcMatchIrqCb; ///< PC match and RC match interrupt callback function + func_ptr_t pfnPcCountInvertIrqCb; ///< PC invert interrupt callback function + func_ptr_t pfnRcOutrangeIrqCb; ///< RC outrange interrupt callback function + +}stc_qprc_intern_data_t, stc_qprc_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Structure to configuration QPRC filter + ******************************************************************************/ +typedef struct stc_qprc_filter +{ + boolean_t bInputMask; ///< Input mask setting + boolean_t bInputInvert; ///< Input invert setting + en_qprc_filter_width_t enWidth; ///< QPRC filter width setting + +}stc_qprc_filter_t; + +/** + ****************************************************************************** + ** \brief Structure to configuration QPRC + ******************************************************************************/ +typedef struct stc_qprc_config +{ + boolean_t bSwapAinBin; ///< TRUE: Swap AIN and BIN inputs + en_qprc_compmode_t enCompareMode; ///< Description see #en_qprc_compmode_t + en_qprc_zinedge_t enZinEdge; ///< Detection mode of the ZIN pin + en_qprc_binedge_t enBinEdge; ///< Detection mode of the BIN pin + en_qprc_ainedge_t enAinEdge; ///< Detection mode of the AIN pin + en_qprc_pcresetmask_t enPcResetMask; ///< Position counter reset mask + boolean_t b8KValue; ///< TRUE: Outrange mode from 0 to 0x7FFF, FALSE: Outrange mode from 0 to 0xFFFF: +#if (PDL_MCU_TYPE >= PDL_FM4_TYPE3) + boolean_t bPhaseEdge; ///< Only meaningful for 1 -time frequency multiplication of PC_Mode2. TRUE: The QPCR is counted up or down by both edge (rising edge and falling edge).FALSE: The QPCR is counted up or down by the same edge (rising edge or falling edge). +#endif +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + stc_qprc_filter_t stcAinFilter; ///< AIN noise filter configuration + stc_qprc_filter_t stcBinFilter; ///< BIN noise filter configuration + stc_qprc_filter_t stcCinFilter; ///< CIN noise filter configuration +#endif + stc_qprc_irq_en_t* pstcIrqEn; ///< Pointer to interrupt enable structure + stc_qprc_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt callback function structure + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC + +} stc_qprc_config_t; + +/** + ****************************************************************************** + ** \brief Structure of QPRC instance data + ******************************************************************************/ +typedef struct stc_qprc_instance_data +{ + volatile stc_qprcn_t* pstcInstance; ///< pointer to registers of an instance +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + volatile stc_qprc_nfn_t* pstcInstanceNf; ///< pointer to registers of a QPRC-NF instance +#endif + stc_qprc_intern_data_t stcInternData; ///< module internal data of instance +} stc_qprc_instance_data_t; + +/** \} GroupQPRC_DataStructures */ + +/** +* \addtogroup GroupQPRC_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled MFS instances and their internal data +extern stc_qprc_instance_data_t m_astcQprcInstanceDataLut[QPRC_INSTANCE_COUNT]; + +/** \} GroupQPRC_GlobalVariables */ + +/** +* \addtogroup GroupQPRC_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* QPRC init */ +en_result_t Qprc_Init( volatile stc_qprcn_t* pstcQprc, const stc_qprc_config_t* pstcConfig ); +en_result_t Qprc_DeInit( volatile stc_qprcn_t* pstcQprc, boolean_t bTouchNvic ); +/* Stop/Restart Pc Count */ +en_result_t Qprc_StopPcCount(volatile stc_qprcn_t *pstcQprc); +en_result_t Qprc_RestartPcCount(volatile stc_qprcn_t *pstcQprc); +/* Count write/read */ +en_result_t Qprc_SetPcCount ( volatile stc_qprcn_t* pstcQprc, uint16_t u16PcValue ) ; +uint16_t Qprc_GetPcCount ( volatile stc_qprcn_t* pstcQprc ); +en_result_t Qprc_SetRcCount ( volatile stc_qprcn_t* pstcQprc, uint16_t u16RcValue ); +uint16_t Qprc_GetRcCount ( volatile stc_qprcn_t* pstcQprc ); +en_result_t Qprc_SetPcMaxValue( volatile stc_qprcn_t* pstcQprc, uint16_t u16PcMaxValue ) ; +uint16_t Qprc_GetPcMaxValue(volatile stc_qprcn_t *pstcQprc); +en_result_t Qprc_SetPcCompareValue( volatile stc_qprcn_t* pstcQprc, uint16_t u16PcValue ) ; +uint16_t Qprc_GetPcCompareValue( volatile stc_qprcn_t *pstcQprc); +en_result_t Qprc_SetPcRcCompareValue( volatile stc_qprcn_t* pstcQprc, uint16_t u16PcRcValue ) ; +uint16_t Qprc_GetPcRcCompareValue(volatile stc_qprcn_t *pstcQprc); +/* Mode configuration */ +en_result_t Qprc_ConfigPcMode( volatile stc_qprcn_t* pstcQprc, en_qprc_pcmode_t enMode ); +en_result_t Qprc_ConfigRcMode( volatile stc_qprcn_t* pstcQprc, en_qprc_rcmode_t enMode ); +/* Interrupt configuration */ +#if (PDL_INTERRUPT_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC2 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_QPRC3 == PDL_ON) +en_result_t Qprc_EnableIrq( volatile stc_qprcn_t* pstcQprc, en_qprc_irq_sel_t enIrqSel); +en_result_t Qprc_DisableIrq( volatile stc_qprcn_t* pstcQprc, en_qprc_irq_sel_t enIrqSel ); +#endif +en_irq_flag_t Qprc_GetIrqFlag( volatile stc_qprcn_t* pstcQprc, en_qprc_irq_sel_t enIrqSel ); +en_result_t Qprc_ClrIrqFlag( volatile stc_qprcn_t *pstcQprc, en_qprc_irq_sel_t enIrqSel ); +/* status */ +en_stat_flag_t Qprc_GetPcOfUfDir( volatile stc_qprcn_t* pstcQprc ); +en_stat_flag_t Qprc_GetPcDir( volatile stc_qprcn_t* pstcQprc ); +/* IRQ handler */ +void Qprc_IrqHandler ( volatile stc_qprcn_t* pstcQprc, + stc_qprc_intern_data_t* pstcQprcInternData ); + +/** \} GroupQPRC_Functions */ +/** \} GroupQPRC */ + +#ifdef __cplusplus +} +#endif + + + +#endif // #if (defined(PDL_PERIPHERAL_QPRC_ACTIVE)) + +#endif /* __QPRC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rc/rc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rc/rc.c new file mode 100644 index 0000000000..1dd091c9b7 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rc/rc.c @@ -0,0 +1,2223 @@ +/******************************************************************************* +* \file rc.c +* +* \version 1.20 +* +* \brief Remote Control driver +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "rc/rc.h" + +#if (defined(PDL_PERIPHERAL_RC_ACTIVE)) + + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled RC instances and their internal data +stc_rc_instance_data_t m_astcRcInstanceDataLut[RC_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_RC0 == PDL_ON) + { + &RC0, // pstcInstance + { + 0u, 0u, 0u, 0u, 0u, 0u, 0u, 0u, 0u + } + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_RC1 == PDL_ON) + { + &RC1, // pstcInstance + { + 0u, 0u, 0u, 0u, 0u, 0u, 0u, 0u, 0u + } + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static void RcInitNvic(void); +static void RcDeInitNvic(void); + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Initialize NVIC of Remote Control + ******************************************************************************/ +static void RcInitNvic(void) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(HDMICEC0_1_IRQn); + NVIC_EnableIRQ(HDMICEC0_1_IRQn); + NVIC_SetPriority(HDMICEC0_1_IRQn, PDL_IRQ_LEVEL_HDMICEC0_1); + #else + #if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_EnableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_IRQ_LEVEL_PPG00_02_20_DSTC_SMCIF0_HDMICEC0); + #endif + #if (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_EnableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #endif + #endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + #if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) + NVIC_ClearPendingIRQ(USB1F_HDMICEC0_IRQn); + NVIC_EnableIRQ(USB1F_HDMICEC0_IRQn); + NVIC_SetPriority(USB1F_HDMICEC0_IRQn, PDL_IRQ_LEVEL_USB1F_HDMICEC0_IRQn); + #endif + #if (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + NVIC_ClearPendingIRQ(USB1F_USB1H_HDMICEC1_IRQn); + NVIC_EnableIRQ(USB1F_USB1H_HDMICEC1_IRQn); + NVIC_SetPriority(USB1F_USB1H_HDMICEC1_IRQn, \ + PDL_IRQ_LEVEL_USB1F_USB1H_HDMICEC1_IRQn); + #endif +#elif (PDL_MCU_CORE == PDL_FM4_CORE) +#endif +} /* RcInitNvic */ + +/** + ****************************************************************************** + ** \brief De-Initialize NVIC of Remote Control + ******************************************************************************/ +static void RcDeInitNvic(void) +{ +#if (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(HDMICEC0_1_IRQn); + NVIC_DisableIRQ(HDMICEC0_1_IRQn); + NVIC_SetPriority(HDMICEC0_1_IRQn, PDL_IRQ_LEVEL_HDMICEC0_1); + #else + #if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) + NVIC_ClearPendingIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_DisableIRQ(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn); + NVIC_SetPriority(PPG00_02_20_DSTC_SMCIF0_HDMICEC0_IRQn, PDL_IRQ_LEVEL_PPG00_02_20_DSTC_SMCIF0_HDMICEC0); + #endif + #if (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_DisableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #endif + #endif +#elif (PDL_MCU_CORE == PDL_FM3_CORE) + #if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) + NVIC_ClearPendingIRQ(USB1F_HDMICEC0_IRQn); + NVIC_DisableIRQ(USB1F_HDMICEC0_IRQn); + NVIC_SetPriority(USB1F_HDMICEC0_IRQn, PDL_IRQ_LEVEL_USB1F_HDMICEC0_IRQn); + #endif + #if (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + NVIC_ClearPendingIRQ(USB1F_USB1H_HDMICEC1_IRQn); + NVIC_DisableIRQ(USB1F_USB1H_HDMICEC1_IRQn); + NVIC_SetPriority(USB1F_USB1H_HDMICEC1_IRQn, PDL_IRQ_LEVEL_USB1F_USB1H_HDMICEC1_IRQn); + #endif +#elif (PDL_MCU_CORE == PDL_FM4_CORE) +#endif +} /* RcDeInitNvic */ + +/** + ****************************************************************************** + ** \brief RC instance interrupt service routine + ** + ** RC instance interrupt service routine, clear interrupt cause and + ** implement interrupt callback function. + ** + ** \param pstcRc Pointer to RC instance + ** \param pstcRcInternData Pointer to RC intern data + ** + ******************************************************************************/ +void RcIrqHandler(volatile stc_rcn_t *pstcRc, + stc_rc_intern_data_t* pstcRcInternData) +{ + if (TRUE == pstcRc->RCST_f.ST) // Start bit detection interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxStartIrqCb) + { + pstcRcInternData->pfnRcRxStartIrqCb(); + } + pstcRc->RCST_f.ST = 0u; + } + + if (TRUE == pstcRc->RCST_f.ACK) // ACK interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxAckIrqCb) + { + pstcRcInternData->pfnRcRxAckIrqCb(); + } + pstcRc->RCST_f.ACK = 0u; + } + + if (TRUE == pstcRc->RCST_f.EOM) // EOM interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxEomCb) + { + pstcRcInternData->pfnRcRxEomCb(); + } + pstcRc->RCST_f.EOM = 0u; + } + + if (TRUE == pstcRc->RCST_f.OVF) // Counter over detection interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxCntOvfIrqCb) + { + pstcRcInternData->pfnRcRxCntOvfIrqCb(); + } + pstcRc->RCST_f.OVF = 0u; + } + + if (TRUE == pstcRc->RCRC_f.RC) // Peapeat code interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxRepeatCodeIrqCb) + { + pstcRcInternData->pfnRcRxRepeatCodeIrqCb(); + } + pstcRc->RCRC_f.RC = 0u; + } + + if (TRUE == pstcRc->RCLE_f.LEL) // Maximun data bit width violation detection interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxMaxDataIrqCb) + { + pstcRcInternData->pfnRcRxMaxDataIrqCb(); + } + pstcRc->RCLE_f.LEL = 0u; + } + + if (TRUE == pstcRc->RCLE_f.LES) // Minimun data bit width violation detection interrupt? + { + if (NULL != pstcRcInternData->pfnRcRxMinDataIrqCb) + { + pstcRcInternData->pfnRcRxMinDataIrqCb(); + } + pstcRc->RCLE_f.LES = 0u; + } + + if (TRUE == pstcRc->TXSTS_f.IBR) // Bus error detection violation detection interrupt? + { + if (NULL != pstcRcInternData->pfnRcTxIrqBusErrorCb) + { + pstcRcInternData->pfnRcTxIrqBusErrorCb(); + } + pstcRc->TXSTS_f.IBR = 0u; + } + + if (TRUE == pstcRc->TXSTS_f.ITST) // Transmission status violation detection interrupt? + { + if (NULL != pstcRcInternData->pfnRcTxIrqStatusCb) + { + pstcRcInternData->pfnRcTxIrqStatusCb(); + } + pstcRc->TXSTS_f.ITST = 0u; + } +} /* RcIrqHandler */ + +#endif + +#if (PDL_PERIPHERAL_ENABLE_RCRX_SIRCS_MODE == PDL_ON || \ + PDL_PERIPHERAL_ENABLE_RCRX_NEC_MODE == PDL_ON || \ + PDL_PERIPHERAL_ENABLE_RCRX_CEC_MODE== PDL_ON) +/** + ****************************************************************************** + ** \brief Return the internal data for a certain RC instance. + ** + ** \param pstcRc Pointer to RC instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_rc_intern_data_t* RcGetInternDataPtr(volatile stc_rcn_t* pstcRc) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < RC_INSTANCE_COUNT; u8Instance++) + { + if (pstcRc == m_astcRcInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcRcInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} +#endif + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +#if (PDL_PERIPHERAL_ENABLE_RCRX_SIRCS_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize SIRCS mode of Remote Control Reception + ** + ** This function initializes SIRCS mode of an Remote Control Reception + ** + ** \param [in] pstcRc RC instance + ** \param [in] pstcRcSircsConfig Pointer to SIRCS mode configuration + ** + ** \retval Ok SIRCS mode initialized normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ** pstcRcSircsConfig == NULL + ** Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_rx_sircs_config_t *pstcRcSircsConfig) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Check for NULL pointers + if ( (NULL == pstcRcSircsConfig) || + (NULL == pstcRc) ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(pstcRcInternData == NULL) + { + return ErrorInvalidParameter ; + } + + // Set mode + pstcRc->RCCR_f.MOD = RcSircsMode; + + // Set clock division value + pstcRc->RCCKD = pstcRcSircsConfig->u16DivVal; + + // Select source clock + switch (pstcRcSircsConfig->enSrcClk) + { + case RcPeripheralClk: + pstcRc->RCCKD_f.CKSEL = RcPeripheralClk; + break; + case RcSubClk: + pstcRc->RCCKD_f.CKSEL = RcSubClk; + break; + default: + return ErrorInvalidParameter; + } + + // Select threshold type + switch (pstcRcSircsConfig->enThresholdType) + { + case RcThresholdType0: + pstcRc->RCCR_f.THSEL = 0u; + break; + case RcThresholdType1: + pstcRc->RCCR_f.THSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Select overflow cycle + switch (pstcRcSircsConfig->enOverflowCycle) + { + case RcOverflow128Cycle: + pstcRc->RCST_f.OVFSEL = 0u; + break; + case RcOverflow256Cycle: + pstcRc->RCST_f.OVFSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set address compare enable + pstcRc->RCCR_f.ADRCE = ((TRUE == pstcRcSircsConfig->bAddrCmpEn) ? 1u : 0u); + + // Set start bit, minimum pluse, threshold width + pstcRc->RCSHW = pstcRcSircsConfig->u8StartBitWidth; + pstcRc->RCDAHW = pstcRcSircsConfig->u8MinPulseWidth; + pstcRc->RCDBHW = pstcRcSircsConfig->u8ThresholdWidth; + + // Set compare address which is used to compare with the received device address + pstcRc->RCADR1 = pstcRcSircsConfig->stcAddr.u8Addr1; + pstcRc->RCADR2 = pstcRcSircsConfig->stcAddr.u8Addr2; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Set interrupt enable + if(NULL != pstcRcSircsConfig->pstcIrqEn) + { + if(TRUE == pstcRcSircsConfig->pstcIrqEn->bRcRxSircsStartIrq) + { + pstcRc->RCST_f.STIE = 1u; + } + if(TRUE == pstcRcSircsConfig->pstcIrqEn->bRcRxSircsAckIrq) + { + pstcRc->RCST_f.ACKIE = 1u; + } + if(TRUE == pstcRcSircsConfig->pstcIrqEn->bRcRxSircsCntOvfIrq) + { + pstcRc->RCST_f.OVFIE = 1u; + } + } + + // Set interrupt callback functions + if(NULL != pstcRcSircsConfig->pstcIrqCb) + { + pstcRcInternData->pfnRcRxStartIrqCb = pstcRcSircsConfig->pstcIrqCb->pfnRcRxSircsStartIrqCb; + pstcRcInternData->pfnRcRxAckIrqCb = pstcRcSircsConfig->pstcIrqCb->pfnRcRxSircsAckIrqCb; + pstcRcInternData->pfnRcRxCntOvfIrqCb = pstcRcSircsConfig->pstcIrqCb->pfnRcRxSircsCntOvfIrqCb; + } + + // Set NVIC + if(TRUE == pstcRcSircsConfig->bTouchNvic) + { + RcInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize SIRCS mode of Remote Control Reception + ** + ** This function deinitializes an SRemote Control Reception with IRCS mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok RC instance fully disabled and reset + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(NULL == pstcRcInternData) + { + return ErrorInvalidParameter ; + } + + // Clear all registers + pstcRc->RCCR = 0u; + pstcRc->RCST = 0u; + pstcRc->RCSHW = 0u; + pstcRc->RCDAHW = 0u; + pstcRc->RCDBHW = 0u; + pstcRc->RCADR1 = 0u; + pstcRc->RCADR2 = 0u; + pstcRc->RCDTHH = 0u; + pstcRc->RCDTHL = 0u; + pstcRc->RCDTLH = 0u; + pstcRc->RCDTLL = 0u; + pstcRc->RCCKD = 0u; + pstcRc->RCRC = 0u; + pstcRc->RCRHW = 0u; + pstcRc->RCLE = 0u; + pstcRc->RCLESW = 0u; + pstcRc->RCLELW = 0u; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Clear callback functions + pstcRcInternData->pfnRcRxAckIrqCb = NULL; + pstcRcInternData->pfnRcRxCntOvfIrqCb = NULL; + pstcRcInternData->pfnRcRxStartIrqCb = NULL; + + // Disable NVIC + if(TRUE == bTouchNvic) + { + RcDeInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable SIRCS mode reception of Remote Control Reception + ** + ** This function enables reception funciton of SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok SIRCS mode reception enabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_EnableRx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcRc->RCCR_f.EN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable SIRCS mode reception of Remote Control Reception + ** + ** This function disables reception funciton of SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok SIRCS mode reception disabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_DisableRx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcRc->RCCR_f.EN = 0u; + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable interrupt of Remote Control Reception with SIRCS mode + ** + ** This function enable the interrupt selected of Remote Control Reception + ** SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception SIRCS mode interrupt types + ** + ** \retval Ok Interrupt enabled normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxSircsStartIrq: + pstcRc->RCST_f.STIE = 1u; + break; + case RcRxSircsAckIrq: + pstcRc->RCST_f.ACKIE = 1u; + break; + case RcRxSircsCntOvfIrq: + pstcRc->RCST_f.OVFIE = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable interrupt of Remote Control Reception with SIRCS mode + ** + ** This function disable the interrupt selected of Remote Control Reception + ** SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception SIRCS mode interrupt types + ** + ** \retval Ok Interrupt disabled normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxSircsStartIrq: + pstcRc->RCST_f.STIE = 0u; + break; + case RcRxSircsAckIrq: + pstcRc->RCST_f.ACKIE = 0u; + break; + case RcRxSircsCntOvfIrq: + pstcRc->RCST_f.OVFIE = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of Remote Control Reception with SIRCS mode + ** + ** This function gets the interrupt flag status of SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception SIRCS mode interrupt types + ** + ** \retval TRUE The interrupt flag selected is set + ** \retval ErrorInvalidParameter The interrupt flag selected is clear + ******************************************************************************/ +boolean_t Rc_Rx_Sircs_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel) +{ + boolean_t bRet = FALSE; + + switch (enIrqSel) + { + case RcRxSircsStartIrq: + bRet = ((1u == pstcRc->RCST_f.ST) ? TRUE : FALSE); + break; + case RcRxSircsAckIrq: + bRet = ((1u == pstcRc->RCST_f.ACK) ? TRUE : FALSE); + break; + case RcRxSircsCntOvfIrq: + bRet = ((1u == pstcRc->RCST_f.OVF) ? TRUE : FALSE); + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of Remote Control Reception with SIRCS mode + ** + ** This function clears the interrupt flag status of SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception SIRCS mode interrupt types + ** + ** \retval Ok The interrupt flag selected is clear normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - NULL == pstcRc + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxSircsStartIrq: + pstcRc->RCST_f.ST = 0u; + break; + case RcRxSircsAckIrq: + pstcRc->RCST_f.ACK = 0u; + break; + case RcRxSircsCntOvfIrq: + pstcRc->RCST_f.OVF = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get data of Remote Control Reception with SIRCS mode + ** + ** This function reads the data from data buffer in SIRCS mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] pstcData Poitner to SIRCS mode data structure + ** + ** \retval Ok Data is read normally + ** \retval ErrorInvalidParameter NULL == pstcRc + ******************************************************************************/ +en_result_t Rc_Rx_Sircs_ReadData(volatile stc_rcn_t *pstcRc, + rc_rx_sircs_data_t* pstcData) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcData->u8Command = pstcRc->RCDTHH; + pstcData->u8DeviceAddress = pstcRc->RCDTHL; + pstcData->u8Data0 = pstcRc->RCDTLH; + pstcData->u8Data1 = pstcRc->RCDTLL; + + return Ok; +} +#endif //#if (PDL_PERIPHERAL_ENABLE_RCRX_SIRCS_MODE == PDL_ON) + +#if (PDL_PERIPHERAL_ENABLE_RCRX_NEC_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize NEC mode of Remote Control Reception + ** + ** This function initializes NEC mode of an Remote Control Reception + ** + ** \param [in] pstcRc RC instance + ** \param [in] pstcRcNecConfig Pointer to NEC mode configuration + ** + ** \retval Ok NEC mode initialized normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - pstcRcNecConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Nec_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_rx_nec_config_t *pstcRcNecConfig) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Check for NULL pointers + if ( (NULL == pstcRcNecConfig) || + (NULL == pstcRc) ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(NULL == pstcRcInternData) + { + return ErrorInvalidParameter ; + } + + // Set mode + pstcRc->RCCR_f.MOD = RcNecMode; + + // Set clock division + pstcRc->RCCKD = pstcRcNecConfig->u16DivVal; + + // Set source clock + switch (pstcRcNecConfig->enSrcClk) + { + case RcPeripheralClk: + pstcRc->RCCKD_f.CKSEL = RcPeripheralClk; + break; + case RcSubClk: + pstcRc->RCCKD_f.CKSEL = RcSubClk; + break; + default: + return ErrorInvalidParameter; + } + + // Set threshold type + switch (pstcRcNecConfig->enThresholdType) + { + case RcThresholdType0: + pstcRc->RCCR_f.THSEL = 0u; + break; + case RcThresholdType1: + pstcRc->RCCR_f.THSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set overflow type + switch (pstcRcNecConfig->enOverflowCycle) + { + case RcOverflow128Cycle: + pstcRc->RCST_f.OVFSEL = 0u; + break; + case RcOverflow256Cycle: + pstcRc->RCST_f.OVFSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set address compare enable + pstcRc->RCCR_f.ADRCE = ((TRUE == pstcRcNecConfig->bAddrCmpEn) ? 1u : 0u); + + // Set start bit, minimum pulse, threshold width + pstcRc->RCSHW = pstcRcNecConfig->u8StartBitWidth; + pstcRc->RCDAHW = pstcRcNecConfig->u8MinPulseWidth; + pstcRc->RCDBHW = pstcRcNecConfig->u8ThresholdWidth; + + // Set compare address + pstcRc->RCADR1 = pstcRcNecConfig->stcAddr.u8Addr1; + pstcRc->RCADR2 = pstcRcNecConfig->stcAddr.u8Addr2; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Set interrupt enable + if(NULL != pstcRcNecConfig->pstcIrqEn) + { + if(TRUE == pstcRcNecConfig->pstcIrqEn->bRcRxNecStartIrq) + { + pstcRc->RCST_f.STIE = 1u; + } + if(TRUE == pstcRcNecConfig->pstcIrqEn->bRcRxNecAckIrq) + { + pstcRc->RCST_f.ACKIE = 1u; + } + if(TRUE == pstcRcNecConfig->pstcIrqEn->bRcRxNecCntOvfIrq) + { + pstcRc->RCST_f.OVFIE = 1u; + } + if(TRUE == pstcRcNecConfig->pstcIrqEn->bRcRxNecRepeatCodeIrq) + { + pstcRc->RCRC_f.RCIE = 1u; + } + } + + // Set interrupt callback functions + if(NULL != pstcRcNecConfig->pstcIrqEn) + { + pstcRcInternData->pfnRcRxStartIrqCb = pstcRcNecConfig->pstcIrqCb->pfnRcRxNecStartIrqCb; + pstcRcInternData->pfnRcRxAckIrqCb = pstcRcNecConfig->pstcIrqCb->pfnRcRxNecAckIrqCb; + pstcRcInternData->pfnRcRxCntOvfIrqCb = pstcRcNecConfig->pstcIrqCb->pfnRcRxNecCntOvfIrqCb; + pstcRcInternData->pfnRcRxRepeatCodeIrqCb = pstcRcNecConfig->pstcIrqCb->pfnRcRxNecRepeatCodeIrqCb; + } + + // Set NVIC enable + if(TRUE == pstcRcNecConfig->bTouchNvic) + { + RcInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize NEC mode of Remote Control Reception + ** + ** This function deinitializes an Remote Control Reception with NEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok RC instance with NEC mode de-initialized + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Nec_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(NULL == pstcRcInternData) + { + return ErrorInvalidParameter ; + } + + // Clear all registers + pstcRc->RCCR = 0u; + pstcRc->RCST = 0u; + pstcRc->RCSHW = 0u; + pstcRc->RCDAHW = 0u; + pstcRc->RCDBHW = 0u; + pstcRc->RCADR1 = 0u; + pstcRc->RCADR2 = 0u; + pstcRc->RCDTHH = 0u; + pstcRc->RCDTHL = 0u; + pstcRc->RCDTLH = 0u; + pstcRc->RCDTLL = 0u; + pstcRc->RCCKD = 0u; + pstcRc->RCRC = 0u; + pstcRc->RCRHW = 0u; + pstcRc->RCLE = 0u; + pstcRc->RCLESW = 0u; + pstcRc->RCLELW = 0u; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Clear callback functions + pstcRcInternData->pfnRcRxAckIrqCb = NULL; + pstcRcInternData->pfnRcRxCntOvfIrqCb = NULL; + pstcRcInternData->pfnRcRxStartIrqCb = NULL; + pstcRcInternData->pfnRcRxRepeatCodeIrqCb = NULL; + + // Set NVIC disable + if(TRUE == bTouchNvic) + { + RcDeInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable NEC mode reception of Remote Control Reception + ** + ** This function enables reception funciton of NEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok NEC mode reception enabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Nec_EnableRx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcRc->RCCR_f.EN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable NEC mode reception of Remote Control Reception + ** + ** This function disables reception funciton of NEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok NEC mode reception disabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Nec_DisableRx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcRc->RCCR_f.EN = 0u; + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable interrupt of Remote Control Reception with NEC mode + ** + ** This function enable the interrupt selected of Remote Control Reception + ** NEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception NEC mode interrupt types + ** + ** \retval Ok Interrupt enabled normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Nec_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxNecStartIrq: + pstcRc->RCST_f.STIE = 1u; + break; + case RcRxNecAckIrq: + pstcRc->RCST_f.ACKIE = 1u; + break; + case RcRxNecCntOvfIrq: + pstcRc->RCST_f.OVFIE = 1u; + break; + case RcRxNecRepeatCodeIrq: + pstcRc->RCRC_f.RCIE = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable interrupt of Remote Control Reception with NEC mode + ** + ** This function disable the interrupt selected of Remote Control Reception + ** NEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception NEC mode interrupt types + ** + ** \retval Ok Interrupt disabled normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Nec_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxNecStartIrq: + pstcRc->RCST_f.STIE = 0u; + break; + case RcRxNecAckIrq: + pstcRc->RCST_f.ACKIE = 0u; + break; + case RcRxNecCntOvfIrq: + pstcRc->RCST_f.OVFIE = 0u; + break; + case RcRxNecRepeatCodeIrq: + pstcRc->RCRC_f.RCIE = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of Remote Control Reception with NEC mode + ** + ** This function gets the interrupt flag status of NEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception NEC mode interrupt types + ** + ** \retval TRUE The interrupt flag selected is set + ** \retval ErrorInvalidParameter The interrupt flag selected is clear + ******************************************************************************/ +boolean_t Rc_Rx_Nec_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel) +{ + boolean_t bRet = FALSE; + + switch (enIrqSel) + { + case RcRxNecStartIrq: + bRet = ((1u == pstcRc->RCST_f.ST) ? TRUE : FALSE); + break; + case RcRxNecAckIrq: + bRet = ((1u == pstcRc->RCST_f.ACK) ? TRUE : FALSE); + break; + case RcRxNecCntOvfIrq: + bRet = ((1u == pstcRc->RCST_f.OVF) ? TRUE : FALSE); + break; + case RcRxNecRepeatCodeIrq: + bRet = ((1u == pstcRc->RCRC_f.RC) ? TRUE : FALSE); + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of Remote Control Reception with NEC mode + ** + ** This function clears the interrupt flag status of NEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception SIRCS mode interrupt types + ** + ** \retval Ok The interrupt flag selected is clear normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - NULL == pstcRc + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Nec_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxNecStartIrq: + pstcRc->RCST_f.ST = 0u; + break; + case RcRxNecAckIrq: + pstcRc->RCST_f.ACK = 0u; + break; + case RcRxNecCntOvfIrq: + pstcRc->RCST_f.OVF = 0u; + break; + case RcRxNecRepeatCodeIrq: + pstcRc->RCRC_f.RC = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get data of Remote Control Reception with NEC mode + ** + ** This function reads the data from data buffer in NEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] pstcData Poitner to NEC mode data structure + ** + ** \retval Ok Data is read normally + ** \retval ErrorInvalidParameter NULL == pstcRc + ******************************************************************************/ +en_result_t Rc_Rx_Nec_ReadData(volatile stc_rcn_t *pstcRc, + rc_rx_nec_data_t* pstcData) +{ + + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcData->u16CustomCode = pstcRc->RCDTHH ; + pstcData->u16CustomCode |= (pstcRc->RCDTHL << 8u); + pstcData->u8Data0 = pstcRc->RCDTLH; + pstcData->u8Data1 = pstcRc->RCDTLL; + + return Ok; +} +#endif //#if (PDL_PERIPHERAL_ENABLE_RCRX_NEC_MODE == PDL_ON) + +#if (PDL_PERIPHERAL_ENABLE_RCRX_CEC_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize CEC mode of Remote Control Reception + ** + ** This function initializes CEC mode of an Remote Control Reception + ** + ** \param [in] pstcRc RC instance + ** \param [in] pstcRcCecConfig Pointer to CEC mode configuration + ** + ** \retval Ok CEC mode initialized normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - pstcRcCecConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Cec_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_rx_cec_config_t *pstcRcCecConfig) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Check for NULL pointers + if ( (NULL == pstcRcCecConfig) || + (NULL == pstcRc) ) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(NULL == pstcRcInternData) + { + return ErrorInvalidParameter ; + } + + // Set mode + pstcRc->RCCR_f.MOD = RcCecMode; + + // Set clock division + pstcRc->RCCKD = pstcRcCecConfig->u16DivVal; + + // Set source clock + switch (pstcRcCecConfig->enSrcClk) + { + case RcPeripheralClk: + pstcRc->RCCKD_f.CKSEL = RcPeripheralClk; + break; + case RcSubClk: + pstcRc->RCCKD_f.CKSEL = RcSubClk; + break; + default: + return ErrorInvalidParameter; + } + + // Set threshold type + switch (pstcRcCecConfig->enThresholdType) + { + case RcThresholdType0: + pstcRc->RCCR_f.THSEL = 0u; + break; + case RcThresholdType1: + pstcRc->RCCR_f.THSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Set overflow type + switch (pstcRcCecConfig->enOverflowCycle) + { + case RcOverflow128Cycle: + pstcRc->RCST_f.OVFSEL = 0u; + break; + case RcOverflow256Cycle: + pstcRc->RCST_f.OVFSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + + // Set address compare enable + pstcRc->RCCR_f.ADRCE = ((TRUE == pstcRcCecConfig->bAddrCmpEn) ? 1u : 0u); + + // Set maximum bit violation detection + pstcRc->RCLE_f.LELE = ((TRUE == pstcRcCecConfig->u8MaxDataWidth) ? 1u : 0u); + + // Set minimum bit violation detection + pstcRc->RCLE_f.LESE = ((TRUE == pstcRcCecConfig->u8MinDataWidth) ? 1u : 0u); + + // Set error pulse output violation detection + pstcRc->RCLE_f.EPE = ((pstcRcCecConfig->bBusErrorPulseOutput) ? 1u : 0u); + + // Set address + pstcRc->RCADR1 = pstcRcCecConfig->stcAddr.u8Addr1; + pstcRc->RCADR2 = pstcRcCecConfig->stcAddr.u8Addr2; + + // Set start bit, minimum pulse, threshold width + pstcRc->RCSHW = pstcRcCecConfig->u8StartBitWidth; + pstcRc->RCDAHW = pstcRcCecConfig->u8MinPulseWidth; + pstcRc->RCDBHW = pstcRcCecConfig->u8ThresholdWidth; + pstcRc->RCLELW = pstcRcCecConfig->u8MaxDataWidth; + pstcRc->RCLESW = pstcRcCecConfig->u8MinDataWidth; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Set interrupt enable + if (NULL != pstcRcCecConfig->pstcIrqEn) + { + if(TRUE == pstcRcCecConfig->pstcIrqEn->bRcRxCecStartIrq) + { + pstcRc->RCST_f.STIE = 1u; + } + + if(TRUE == pstcRcCecConfig->pstcIrqEn->bRcRxCecAckIrq) + { + pstcRc->RCST_f.ACKIE = 1u; + } + + if(TRUE == pstcRcCecConfig->pstcIrqEn->bRcRxCecCntOvfIrq) + { + pstcRc->RCST_f.OVFIE = 1u; + } + + if(TRUE == pstcRcCecConfig->pstcIrqEn->bRcRxCecMaxDataIrq) + { + pstcRc->RCLE_f.LELIE = 1u; + } + + if(TRUE == pstcRcCecConfig->pstcIrqEn->bRcRxCecMinDataIrq) + { + pstcRc->RCLE_f.LESIE = 1u; + } + } + + // Set interrupt callback function + if (NULL != pstcRcCecConfig->pstcIrqCb) + { + pstcRcInternData->pfnRcRxStartIrqCb = pstcRcCecConfig->pstcIrqCb->pfnRcRxCecStartIrqCb; + pstcRcInternData->pfnRcRxAckIrqCb = pstcRcCecConfig->pstcIrqCb->pfnRcRxCecAckIrqCb; + pstcRcInternData->pfnRcRxCntOvfIrqCb = pstcRcCecConfig->pstcIrqCb->pfnRcRxCecCntOvfIrqCb; + pstcRcInternData->pfnRcRxMaxDataIrqCb = pstcRcCecConfig->pstcIrqCb->pfnRcRxCecMaxDataIrqCb; + pstcRcInternData->pfnRcRxMinDataIrqCb = pstcRcCecConfig->pstcIrqCb->pfnRcRxCecMinDataIrqCb; + } + + // Set NVIC enable + if(TRUE == pstcRcCecConfig->bTouchNvic) + { + RcInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize CEC mode of Remote Control Reception + ** + ** This function deinitializes an Remote Control Reception with CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok RC instance with CEC mode de-initialized + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Cec_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(pstcRcInternData == NULL) + { + return ErrorInvalidParameter ; + } + + /* Clear all registers */ + pstcRc->RCCR = 0u; + pstcRc->RCST = 0u; + pstcRc->RCSHW = 0u; + pstcRc->RCDAHW = 0u; + pstcRc->RCDBHW = 0u; + pstcRc->RCADR1 = 0u; + pstcRc->RCADR2 = 0u; + pstcRc->RCDTHH = 0u; + pstcRc->RCDTHL = 0u; + pstcRc->RCDTLH = 0u; + pstcRc->RCDTLL = 0u; + pstcRc->RCCKD = 0u; + pstcRc->RCRC = 0u; + pstcRc->RCRHW = 0u; + pstcRc->RCLE = 0u; + pstcRc->RCLESW = 0u; + pstcRc->RCLELW = 0u; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Clear callback + pstcRcInternData->pfnRcRxStartIrqCb = NULL; + pstcRcInternData->pfnRcRxAckIrqCb = NULL; + pstcRcInternData->pfnRcRxCntOvfIrqCb = NULL; + pstcRcInternData->pfnRcRxMaxDataIrqCb = NULL; + pstcRcInternData->pfnRcRxMinDataIrqCb = NULL; + + // Set NVIC disable + if(TRUE == bTouchNvic) + { + RcDeInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable CEC mode reception of Remote Control Reception + ** + ** This function enables reception funciton of CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok CEC mode reception enabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Cec_EnableRx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcRc->RCCR_f.EN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable CEC mode reception of Remote Control Reception + ** + ** This function disables reception funciton of CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok CEC mode reception disabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Rx_Cec_DisableRx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + pstcRc->RCCR_f.EN = 0u; + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable interrupt of Remote Control Reception with CEC mode + ** + ** This function enable the interrupt selected of Remote Control Reception + ** CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception CEC mode interrupt types + ** + ** \retval Ok Interrupt enabled normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Cec_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxCecStartIrq: + pstcRc->RCST_f.STIE = 1u; + break; + case RcRxCecAckIrq: + pstcRc->RCST_f.ACKIE = 1u; + break; + case RcRxCecCntOvfIrq: + pstcRc->RCST_f.OVFIE = 1u; + break; + case RcRxCecMaxDataIrq: + pstcRc->RCLE_f.LELIE = 1u; + break; + case RcRxCecMinDataIrq: + pstcRc->RCLE_f.LESIE = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable interrupt of Remote Control Reception with CEC mode + ** + ** This function disable the interrupt selected of Remote Control Reception + ** CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception CEC mode interrupt types + ** + ** \retval Ok Interrupt disabled normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Cec_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxCecStartIrq: + pstcRc->RCST_f.STIE = 0u; + break; + case RcRxCecAckIrq: + pstcRc->RCST_f.ACKIE = 0u; + break; + case RcRxCecCntOvfIrq: + pstcRc->RCST_f.OVFIE = 0u; + break; + case RcRxCecMaxDataIrq: + pstcRc->RCLE_f.LELIE = 0u; + break; + case RcRxCecMinDataIrq: + pstcRc->RCLE_f.LESIE = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of Remote Control Reception with CEC mode + ** + ** This function gets the interrupt flag status of CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception CEC mode interrupt types + ** + ** \retval TRUE The interrupt flag selected is set + ** \retval ErrorInvalidParameter The interrupt flag selected is clear + ******************************************************************************/ +boolean_t Rc_Rx_Cec_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel) +{ + boolean_t bRet = FALSE; + + switch (enIrqSel) + { + case RcRxCecStartIrq: + bRet = ((1u == pstcRc->RCST_f.ST) ? TRUE : FALSE); + break; + case RcRxCecAckIrq: + bRet = ((1u == pstcRc->RCST_f.ACK) ? TRUE : FALSE); + break; + case RcRxCecCntOvfIrq: + bRet = ((1u == pstcRc->RCST_f.OVF) ? TRUE : FALSE); + break; + case RcRxCecMaxDataIrq: + bRet = ((1u == pstcRc->RCLE_f.LEL) ? TRUE : FALSE); + break; + case RcRxCecMinDataIrq: + bRet = ((1u == pstcRc->RCLE_f.LES) ? TRUE : FALSE); + break; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of Remote Control Reception with CEC mode + ** + ** This function clears the interrupt flag status of CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception CEC mode interrupt types + ** + ** \retval Ok The interrupt flag selected is clear normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - NULL == pstcRc + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Rx_Cec_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcRxCecStartIrq: + pstcRc->RCST_f.ST = 0u; + break; + case RcRxCecAckIrq: + pstcRc->RCST_f.ACK = 0u; + break; + case RcRxCecCntOvfIrq: + pstcRc->RCST_f.OVF = 0u; + break; + case RcRxCecMaxDataIrq: + pstcRc->RCLE_f.LEL = 0u; + break; + case RcRxCecMinDataIrq: + pstcRc->RCLE_f.LES = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get data of Remote Control Reception with CEC mode + ** + ** This function reads the data from data buffer in CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval CEC data CEC data + ******************************************************************************/ +uint8_t Rc_Rx_Cec_ReadData(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + + return pstcRc->RCDTHH; +} + +/** + ****************************************************************************** + ** \brief Get EOM state of Remote Control Reception with CEC mode + ** + ** This function reads the data from data buffer in CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval True that's end of data + ** \retval Flase that isn't end of data + ******************************************************************************/ +boolean_t Rc_Rx_Cec_GetEomState(volatile stc_rcn_t *pstcRc) +{ + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + return pstcRc->RCST_f.EOM; + +} + +/** + ****************************************************************************** + ** \brief clear EOM state of Remote Control Reception with CEC mode + ** + ** This function reads the data from data buffer in CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval True that's end of data + ** \retval Flase that isn't end of data + ******************************************************************************/ +en_result_t Rc_Rx_Cec_ClrEomState(volatile stc_rcn_t *pstcRc) +{ + if (NULL == pstcRc) + { + return ErrorInvalidParameter; + } + pstcRc->RCST_f.EOM = 0u; + return Ok; +} +#endif + +#if (PDL_PERIPHERAL_ENABLE_RCTX_CEC_MODE == PDL_ON) +/** + ****************************************************************************** + ** \brief Initialize CEC mode of Remote Control transmission + ** + ** This function initializes CEC mode of an Remote Control transmission + ** + ** \param [in] pstcRc RC instance + ** \param [in] pstcRcTxConfig Pointer to TX CEC mode configuration + ** + ** \retval Ok CEC mode initialized normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcRc == NULL + ** - pstcRcTxConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Tx_Cec_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_tx_cec_config_t *pstcRcTxConfig) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(NULL == pstcRcInternData) + { + return ErrorInvalidParameter ; + } + + // Check for NULL pointers + if ( (NULL == pstcRcTxConfig) || + (NULL == pstcRc) ) + { + return ErrorInvalidParameter; + } + + // Set clock division + pstcRc->RCCKD = pstcRcTxConfig->u16DivVal; + + // Set source clock + switch (pstcRcTxConfig->enSrcClk) + { + case RcPeripheralClk: + pstcRc->RCCKD_f.CKSEL = RcPeripheralClk; + break; + case RcSubClk: + pstcRc->RCCKD_f.CKSEL = RcSubClk; + break; + default: + return ErrorInvalidParameter; + } + + + if (pstcRcTxConfig->u8FreeCycle > 15u) + { + return ErrorInvalidParameter ; + } + + pstcRc->SFREE = pstcRcTxConfig->u8FreeCycle; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Set interrupt enable + if (NULL != pstcRcTxConfig->pstcIrqEn) + { + if(TRUE == pstcRcTxConfig->pstcIrqEn->bRcTxCecBusErrorIrq) + { + pstcRc->TXCTRL_f.IBREN = 1u; + } + if(TRUE == pstcRcTxConfig->pstcIrqEn->bRcTxCecStatusIrq) + { + pstcRc->TXCTRL_f.ITSTEN = 1u; + } + } + + // Set interrupt callback function + if (NULL != pstcRcTxConfig->pstcIrqCb) + { + pstcRcInternData->pfnRcTxIrqBusErrorCb = pstcRcTxConfig->pstcIrqCb->pfnRcTxIrqBusErrorCb; + pstcRcInternData->pfnRcTxIrqStatusCb = pstcRcTxConfig->pstcIrqCb->pfnRcTxIrqTxStatusCb; + } + + // Set NVIC enable + if(TRUE == pstcRcTxConfig->bTouchNvic) + { + RcInitNvic(); + } + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize CEC mode of Remote Control transmission + ** + ** This function deinitializes an Remote Control transmission with CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok RC instance with CEC mode de-initialized + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Tx_Cec_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic) +{ + // Pointer to internal data + stc_rc_intern_data_t* pstcRcInternData ; + + // Get pointer to internal data structure ... + pstcRcInternData = RcGetInternDataPtr( pstcRc ) ; + + // Check for instance available or not + if(NULL == pstcRcInternData) + { + return ErrorInvalidParameter ; + } + + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + /* Clear all registers */ + pstcRc->TXCTRL = 0u; + pstcRc->TXDATA = 0u; + pstcRc->TXSTS = 0u; + pstcRc->SFREE = 0u; + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + // Clear callback + pstcRcInternData->pfnRcTxIrqBusErrorCb = NULL; + pstcRcInternData->pfnRcTxIrqStatusCb = NULL; + + // Set NVIC disable + if(TRUE == bTouchNvic) + { + RcDeInitNvic(); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable CEC mode transfer of Remote Control transmision + ** + ** This function enables transfer funciton of CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok CEC mode transmision enabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Tx_Cec_EnableTx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + pstcRc->TXCTRL_f.TXEN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable CEC mode transfer of Remote Control transmision + ** + ** This function disables transfer funciton of CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval Ok CEC mode transmision disabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Tx_Cec_DisableTx(volatile stc_rcn_t *pstcRc) +{ + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + pstcRc->TXCTRL_f.TXEN = 0u; + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) ||\ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable CEC mode interrupt of Remote Control transmision + ** + ** This function enables transfer interrupt of CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel Interrupt type + ** + ** \retval Ok CEC mode transmision interrupt enabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Tx_Cec_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcTxCecBusErrorIrq: + pstcRc->TXCTRL_f.IBREN = 1u; + break; + case RcTxCecTransStausIrq: + pstcRc->TXCTRL_f.ITSTEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable CEC mode interrupt of Remote Control transmision + ** + ** This function disables transfer interrupt of CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel Interrupt type + ** + ** \retval Ok CEC mode transmision interrupt disabled normally + ** \retval ErrorInvalidParameter pstcRc == NULL + ******************************************************************************/ +en_result_t Rc_Tx_Cec_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcTxCecBusErrorIrq: + pstcRc->TXCTRL_f.IBREN = 0u; + break; + case RcTxCecTransStausIrq: + pstcRc->TXCTRL_f.ITSTEN = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} +#endif + +/** + ****************************************************************************** + ** \brief Get interrupt flag of Remote Control transmission with CEC mode + ** + ** This function gets the interrupt flag status of CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception CEC mode interrupt types + ** + ** \retval TRUE The interrupt flag selected is set + ** \retval ErrorInvalidParameter The interrupt flag selected is clear + ******************************************************************************/ +boolean_t Rc_Tx_Cec_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel) +{ + boolean_t bRet; + + switch (enIrqSel) + { + case RcTxCecBusErrorIrq: + bRet = ((TRUE == pstcRc->TXSTS_f.IBR) ? 1u : 0u); + break; + case RcTxCecTransStausIrq: + bRet = ((TRUE == pstcRc->TXSTS_f.ITST) ? 1u : 0u); + break; + default: + return ErrorInvalidParameter; + } + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear interrupt flag of Remote Control Transmission with CEC mode + ** + ** This function clears the interrupt flag status of CEC mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] enIrqSel RC Reception CEC mode interrupt types + ** + ** \retval Ok The interrupt flag selected is clear normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - NULL == pstcRc + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Rc_Tx_Cec_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel) +{ + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + switch (enIrqSel) + { + case RcTxCecBusErrorIrq: + pstcRc->TXSTS_f.IBR = 0u; + break; + case RcTxCecTransStausIrq: + pstcRc->TXSTS_f.ITST = 0u; + break; + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get ACK cycle value of Remote Control transmission with CEC mode + ** + ** This function gets the ACK cycle value of CEC mode + ** + ** \param [in] pstcRc RC instance + ** + ** \retval TRUE ACK cycle value is set + ** \retval ErrorInvalidParameter ACK cycle value is clear + ******************************************************************************/ +boolean_t Rc_Tx_GetAckCycleValue(volatile stc_rcn_t *pstcRc) +{ + return pstcRc->TXSTS_f.ACKSV; +} + +/** + ****************************************************************************** + ** \brief Write data into data specified with data type for CEC TX mode + ** + ** This function writes the data buffer with data specified + ** + ** \param [in] pstcRc RC instance + ** \param [in] u8Data Data to be written + ** \param [in] enType Remote Control TX data type + ** + ** \retval Ok Data is written + ** \retval ErrorInvalidParameter pstcRc == NULL or other invalid configuration + ******************************************************************************/ +en_result_t Rc_Tx_Cec_WriteData(volatile stc_rcn_t *pstcRc, + uint8_t u8Data, + en_rc_txdata_type_t enType) +{ + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + switch (enType) + { + case RcTxCecHeader: + pstcRc->TXCTRL_f.START = 1u; + pstcRc->TXCTRL_f.EOM = 0u; + break; + case RcTxCecData: + pstcRc->TXCTRL_f.START = 0u; + pstcRc->TXCTRL_f.EOM = 0u; + break; + case RcTxCecPolling: + pstcRc->TXCTRL_f.START = 1u; + pstcRc->TXCTRL_f.EOM = 1u; + break; + case RcTxCecFinal: + pstcRc->TXCTRL_f.START = 0u; + pstcRc->TXCTRL_f.EOM = 1u; + break; + default: + return ErrorInvalidParameter; + } + + pstcRc->TXDATA = u8Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Write CEC data package with polling mode for CEC TX mode + ** + ** This function writes a CEC data frame with polling mode + ** + ** \param [in] pstcRc RC instance + ** \param [in] u8Header Data header + ** \param [in] pu8Data Pointer to data to be written + ** \param [in] u32Size Data size + ** + ** \retval Ok Data is written + ** \retval ErrorInvalidParameter pstcRc == NULL or other invalid configuration + ******************************************************************************/ +en_result_t Rc_Tx_Cec_SendDataPolling( volatile stc_rcn_t *pstcRc, + uint8_t u8Header, + uint8_t* pu8Data, + uint32_t u32Size) +{ + uint32_t u32Timeout, u32i; + + // Check for NULL pointers + if ( NULL == pstcRc ) + { + return ErrorInvalidParameter; + } + + // Send header + pstcRc->TXCTRL_f.START = 1u; + pstcRc->TXCTRL_f.EOM = 0u; + pstcRc->TXDATA = u8Header; + + u32Timeout = 0x100000u; + while(1) + { + u32Timeout--; + if(TRUE == pstcRc->TXSTS_f.ITST) + { + pstcRc->TXSTS_f.ITST = 0u; + break; // Data sent + } + + if(u32Timeout == 0u) + { + return ErrorTimeout; + } + } + + if (pstcRc->TXSTS_f.ACKSV == 1u) + { + return Error; // ACK error + } + + // Send data + pstcRc->TXCTRL_f.START = 0u; + pstcRc->TXCTRL_f.EOM = 0u; + + for(u32i=0; u32i<(u32Size-1u); u32i++) + { + pstcRc->TXDATA = *pu8Data++; + + u32Timeout = 0x100000u; + while(1) + { + u32Timeout--; + if(TRUE == pstcRc->TXSTS_f.ITST) + { + pstcRc->TXSTS_f.ITST = 0u; + break; // Data sent + } + + if(u32Timeout == 0u) + { + return ErrorTimeout; + } + } + + if (pstcRc->TXSTS_f.ACKSV == 1u) + { + return Error; // ACK error + } + } + + // Send final data + pstcRc->TXCTRL_f.START = 0u; + pstcRc->TXCTRL_f.EOM = 1u; + + pstcRc->TXDATA = *pu8Data; + + u32Timeout = 0x100000u; + while(1) + { + u32Timeout--; + if(TRUE == pstcRc->TXSTS_f.ITST) + { + pstcRc->TXSTS_f.ITST = 0u; + break; // Data sent + } + + if(0u == u32Timeout) + { + return ErrorTimeout; + } + } + + if (1u == pstcRc->TXSTS_f.ACKSV) + { + return Error; // ACK error + } + + return Ok; +} + +#endif + +#endif // #if (defined(PDL_PERIPHERAL_RC_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rc/rc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rc/rc.h new file mode 100644 index 0000000000..3667c9d953 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rc/rc.h @@ -0,0 +1,625 @@ +/******************************************************************************* +* \file rc.h +* +* \version 1.20 +* +* \brief Headerfile for Remote Control functions +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +#ifndef __RC_H__ +#define __RC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_RC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupRC HDMI-CEC/Remote Control Reception/Transmission (RC) +* \{ +* \defgroup GroupRC_Macros Macros +* \defgroup GroupRC_Functions Functions +* \defgroup GroupRC_GlobalVariables Global Variables +* \defgroup GroupRC_DataStructures Data Structures +* \defgroup GroupRC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupRC +* \{ +* Use the Remote Control (RC) peripheral to manage and receive +* HDMI-CEC signals and infrared remote control signals.
+* RC supports these standards:
+* * SIRCS +* * NEC/Association for Electric Home Appliances +* * HDMI-CEC
+* RC has these features: +* * Start bit detection (generates an interrupt) +* * ACK detection (generates an interrupt) +* * Minimum pulse width violation detection (returns to waiting for a signal) +* * Counter overflow detection (generates an interrupt) +* * Noise filtering
+* For CEC only, the RC peripheral supports transmitting a signal. When transmitting, +* setting one byte data automatically generates START, EOM and ACK to output the +* CEC transmission. After one block (1 byte data, EOM and ACK) is transmitted, a +* transmission status interrupt is generated. +* \section SectionRC_ConfigurationConsideration Configuration Considerations +* The RC peripheral has a configuration structure for each operating mode:
+* * SIRCS receive +* * NEC receive +* * CEC receive +* * CEC transmit
+* Set the fields in the correct structure. This includes identifying which interrupts to enable, and corresponding interrupt +* handlers. You can use polling rather than enabling interrupts.
+* After setting fields in the configuration structure, call the corresponding Init() +* routine. Then use the corresponding EnableRx() or EnableTx() (CEC only) call +* to start operation.
+* For each mode, use API function calls to:
+* * Enable or disable operation +* * Enable or disable particular interrupts +* * Read data +* * Write data (CEC only) +* +* \section SectionRC_MoreInfo More Information +* For more information of HDMI-CEC/Remote Control peripheral, refer to:
+* FM0+ Peripheral Manual - Communication Subsystem TRM.pdf
+* FM4 Peripheral Manual - Communication Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* +*/ + +/** +* \addtogroup GroupRC_Macros +* \{ +*/ +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define stc_rcn_t FM_HDMICEC_TypeDef +#define RC0 (*((volatile stc_rcn_t *) FM_HDMICEC0_BASE)) +#define RC1 (*((volatile stc_rcn_t *) FM_HDMICEC1_BASE)) + +#define RC_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_RC0 == PDL_ON) + \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_RC1 == PDL_ON) +/** \} GroupRC_Macros */ + +/** +* \addtogroup GroupRC_Types +* \{ +*/ +/******************************************************************************/ +/* Global type definitions */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief RC mode setting + ******************************************************************************/ +typedef enum en_rc_mode +{ + RcSircsMode = 0u, ///< SIRCS mode + RcSettingProh = 1u, ///< Setting Prohibited + RcNecMode = 2u, ///< NEC/Association for electric home appliance mode + RcCecMode = 3u, ///< HDIM-CEC mode +} en_rc_mode_t; + +/** + ****************************************************************************** + ** \brief RC CLK + ******************************************************************************/ +typedef enum en_rc_src_clk +{ + RcPeripheralClk = 0u, ///< Use peripheral clock as Remoter Control clock + RcSubClk = 1u, ///< Use sub clock as Remoter Control clock +} en_rc_src_clk_t; + +/** + ****************************************************************************** + ** \brief RC threshold type + ******************************************************************************/ +typedef enum en_rc_threshold_type +{ + RcThresholdType0 = 0u, ///< RC threshold type 0 + RcThresholdType1 = 1u, ///< RC threshold type 1 +} en_rc_threshold_type_t; + +/** + ****************************************************************************** + ** \brief RC overflow type + ******************************************************************************/ +typedef enum en_rc_overflow +{ + RcOverflow128Cycle = 0u, ///< An overflow will occur after the counter counted 128 clocks. + RcOverflow256Cycle = 1u, ///< An overflow will occur after the counter counted 256 clocks. +} en_rc_overflow_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver SIRCS mode interrupt selection enumeration + ******************************************************************************/ +typedef enum en_rc_rx_sircs_irq_sel +{ + RcRxSircsStartIrq = 0u, ///< SIRCS mode start bit detection interrupt + RcRxSircsAckIrq = 1u, ///< SIRCS mode ACK detection interrupt + RcRxSircsCntOvfIrq = 2u, ///< SIRCS mode RX counter overflow interrupt + +}en_rc_rx_sircs_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver NEC mode interrupt selection enumeration + ******************************************************************************/ +typedef enum en_rc_rx_nec_irq_sel +{ + RcRxNecStartIrq = 0u, ///< NEC mode start bit detection interrupt + RcRxNecAckIrq = 1u, ///< NEC mode ACK detection interrupt + RcRxNecCntOvfIrq = 2u, ///< NEC mode counter overflow interrupt + RcRxNecRepeatCodeIrq = 3u, ///< NEC mode repeat code interrupt + +} en_rc_rx_nec_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver CEC mode interrupt selection enumeration + ******************************************************************************/ +typedef enum en_rc_rx_cec_irq_sel +{ + RcRxCecStartIrq = 0u, ///< CEC mode start bit detection interrupt + RcRxCecAckIrq = 1u, ///< CEC mode ACK detection interrupt + RcRxCecCntOvfIrq = 2u, ///< CEC mode counter overflow interrupt + RcRxCecMinDataIrq = 3u, ///< CEC mode Minimum data bit width violation detection + RcRxCecMaxDataIrq = 4u, ///< CEC mode Maximum data bit width violation detection + +}en_rc_rx_cec_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Transmission data type + ******************************************************************************/ +typedef enum en_rc_txdata_type +{ + RcTxCecHeader = 0u, ///< Header block transmission + RcTxCecData = 1u, ///< Data block + RcTxCecPolling = 2u, ///< Header block transmission + RcTxCecFinal = 3u, ///< Final data block +} en_rc_txdata_type_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Transmission interrupt selection + ******************************************************************************/ +typedef enum en_rc_tx_cec_irq_sel +{ + RcTxCecBusErrorIrq = 0u, ///< Remoter Control CEC TX bus error interrupt + RcTxCecTransStausIrq = 1u, ///< Remoter Control CEC TX transfer status interrupt +} en_rc_tx_cec_irq_sel_t; + +/// Enumeration to define an index for each enabled RC instance +typedef enum en_rc_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_RC0 == PDL_ON) + RcInstanceIndexRc0, + #endif + #if (PDL_PERIPHERAL_ENABLE_RC1 == PDL_ON) + RcInstanceIndexRc1, + #endif + RcInstanceIndexMax +} en_rc_instance_index_t; + +/** \}GroupRC_Types */ + +/** +* \addtogroup GroupRC_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver address structure + ******************************************************************************/ +typedef struct stc_rc_rx_addr +{ + uint8_t u8Addr1; ///< RC receiver address 1 + uint8_t u8Addr2; ///< RC receiver address 2 +}stc_rc_rx_addr_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver SIRCS mode interrupt enable structure + ******************************************************************************/ +typedef struct stc_rc_rx_sircs_irq_en +{ + boolean_t bRcRxSircsStartIrq; ///< SIRCS mode start bit detection interrupt + boolean_t bRcRxSircsAckIrq; ///< SIRCS mode ACK detection interrupt + boolean_t bRcRxSircsCntOvfIrq; ///< SIRCS mode RX counter overflow interrupt + +}stc_rc_rx_sircs_irq_en_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver SIRCS mode interrupt callback function + ******************************************************************************/ +typedef struct stc_rc_rx_sircs_irq_cb +{ + func_ptr_t pfnRcRxSircsStartIrqCb; ///< Callback function pointer of SIRCS start interrupt + func_ptr_t pfnRcRxSircsAckIrqCb; ///< Callback function pointer of SIRCS ACK interrupt + func_ptr_t pfnRcRxSircsCntOvfIrqCb; ///< Callback function pointer of SIRCS counter overflow interrupt +}stc_rc_rx_sircs_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver NEC mode interrupt enable structure + ******************************************************************************/ +typedef struct stc_rc_rx_nec_irq_en +{ + boolean_t bRcRxNecStartIrq; ///< NEC mode start bit detection interrupt + boolean_t bRcRxNecAckIrq; ///< NEC mode ACK detection interrupt + boolean_t bRcRxNecCntOvfIrq; ///< NEC mode counter overflow interrupt + boolean_t bRcRxNecRepeatCodeIrq; ///< NEC mode repeat code interrupt + +} stc_rc_rx_nec_irq_en_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver NEC mode interrupt callback functions + ******************************************************************************/ +typedef struct stc_rc_rx_nec_irq_cb +{ + func_ptr_t pfnRcRxNecStartIrqCb; ///< Callback function pointer of Nec start interrupt + func_ptr_t pfnRcRxNecAckIrqCb; ///< Callback function pointer of Nec ACK interrupt + func_ptr_t pfnRcRxNecCntOvfIrqCb; ///< Callback function pointer of Nec counter overflow interrupt + func_ptr_t pfnRcRxNecRepeatCodeIrqCb; ///< Callback function pointer of Nec repeat code interrupt + +}stc_rc_rx_nec_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver CEC mode interrupt enable structure + ******************************************************************************/ +typedef struct stc_rc_rx_cec_irq_en +{ + boolean_t bRcRxCecStartIrq; ///< CEC mode start bit detection interrupt + boolean_t bRcRxCecAckIrq; ///< CEC mode ACK detection interrupt + boolean_t bRcRxCecCntOvfIrq; ///< CEC mode counter overflow interrupt + boolean_t bRcRxCecMinDataIrq; ///< CEC mode Minimum data bit width violation detection + boolean_t bRcRxCecMaxDataIrq; ///< CEC mode Maximum data bit width violation detection + +}stc_rc_rx_cec_irq_en_t; + + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver CEC mode interrupt callback functions + ******************************************************************************/ +typedef struct stc_rc_rx_cec_irq_cb +{ + func_ptr_t pfnRcRxCecStartIrqCb; ///< Callback function pointer of CEC start interrupt + func_ptr_t pfnRcRxCecAckIrqCb; ///< Callback function pointer of CEC ACK interrupt + func_ptr_t pfnRcRxCecCntOvfIrqCb; ///< Callback function pointer of CEC count over interrupt + func_ptr_t pfnRcRxCecMinDataIrqCb; ///< Callback function pointer of CEC Minimum data interrupt + func_ptr_t pfnRcRxCecMaxDataIrqCb; ///< Callback function pointer of CEC Maximum data interrupt + +}stc_rc_rx_cec_irq_cb_t; + + +/** + ****************************************************************************** + ** \brief Remoter Control Transmission interrupt enable structure + ******************************************************************************/ +typedef struct stc_rc_tx_cec_irq_en +{ + boolean_t bRcTxCecBusErrorIrq; ///< Remoter Control CEC TX bus error interrupt + boolean_t bRcTxCecStatusIrq; ///< Remoter Control CEC TX status interrupt + +} stc_rc_tx_cec_irq_en_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Transmission interrupt callback function + ******************************************************************************/ +typedef struct stc_rc_tx_irq_cb +{ + func_ptr_t pfnRcTxIrqBusErrorCb; ///< Callback function pointer of Bus error dection + func_ptr_t pfnRcTxIrqTxStatusCb; ///< Callback function pointer of Transmisstion status +}stc_rc_tx_cec_irq_cb_t; +/** + ****************************************************************************** + ** \brief Intern data structure + ******************************************************************************/ +typedef struct stc_rc_intern_data +{ + func_ptr_t pfnRcRxStartIrqCb; ///< Callback function pointer of RC Start interrupt + func_ptr_t pfnRcRxCntOvfIrqCb; ///< Callback function pointer of RC counter over interrupt + func_ptr_t pfnRcRxEomCb; ///< Callback function pointer of End of transmit interrupt + func_ptr_t pfnRcRxAckIrqCb; ///< Callback function pointer of ICU1 interrupt + func_ptr_t pfnRcRxRepeatCodeIrqCb; ///< Callback function pointer of repect code interrupt + func_ptr_t pfnRcRxMinDataIrqCb; ///< Callback function pointer of minimum data interrupt + func_ptr_t pfnRcRxMaxDataIrqCb; ///< Callback function pointer of maximum data interrupt + func_ptr_t pfnRcTxIrqBusErrorCb; ///< Callback function pointer of bus error interrupt + func_ptr_t pfnRcTxIrqStatusCb; ///< Callback function pointer of status interrupt +}stc_rc_intern_data_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver SIRCS mode configuration + ******************************************************************************/ +typedef struct stc_rc_rx_sircs_config +{ + en_rc_src_clk_t enSrcClk; ///< Source clock + uint16_t u16DivVal; ///< Clock division value + en_rc_threshold_type_t enThresholdType; ///< Theshold type selection + boolean_t bAddrCmpEn; ///< TRUE: compare with address set in the address register, FALSE: don't compare with address set in the address register + en_rc_overflow_t enOverflowCycle; ///< Overflow cycle count selection + uint8_t u8StartBitWidth; ///< Start bit width + uint8_t u8MinPulseWidth; ///< Minimum pulse width setting + uint8_t u8ThresholdWidth; ///< Theshold width setting + stc_rc_rx_addr_t stcAddr; ///< Address setting which is used to compare with device address +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + stc_rc_rx_sircs_irq_en_t* pstcIrqEn; ///< Pointer to interrupt request enable setting structure of RC with SIRCS mode + stc_rc_rx_sircs_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt request callback functions structure of RC with SIRCS mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_rc_rx_sircs_config_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver NEC mode configuration + ******************************************************************************/ +typedef struct stc_rc_rx_nec_config +{ + en_rc_src_clk_t enSrcClk; ///< Source clock + uint16_t u16DivVal; ///< Clock division value + en_rc_threshold_type_t enThresholdType; ///< Theshold type selection + boolean_t bAddrCmpEn; ///< TRUE: compare with address set in the address register, FALSE: don't compare with address set in the address register + en_rc_overflow_t enOverflowCycle; ///< Overflow cycle count selection + uint8_t u8StartBitWidth; ///< Start bit width + uint8_t u8MinPulseWidth; ///< Minimum pulse width setting + uint8_t u8ThresholdWidth; ///< Theshold width setting + uint8_t u8RepeatWidth; ///< Repeat code width setting + stc_rc_rx_addr_t stcAddr; ///< Address setting which is used to compare with device address +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + stc_rc_rx_nec_irq_en_t* pstcIrqEn; ///< Pointer to interrupt request enable setting structure of RC with NEC mode + stc_rc_rx_nec_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt request callback functions structure of RC with NEC mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_rc_rx_nec_config_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver CEC mode configuration + ******************************************************************************/ +typedef struct stc_rc_rx_cec_config +{ + en_rc_src_clk_t enSrcClk; ///< Source clock + uint16_t u16DivVal; ///< Clock division value + en_rc_threshold_type_t enThresholdType; ///< Theshold type selection + en_rc_overflow_t enOverflowCycle; ///< Overflow cycle count selection + boolean_t bAddrCmpEn; ///< TRUE: compare with address set in the address register, FALSE: don't compare with address set in the address register + boolean_t bMinDataBitDetect; ///< TRUE : Enable minimum data bit detection, FALSE: Disable minimum data bit detection + boolean_t bMaxDataBitDetect; ///< TRUE : Enable maximum data bit detection, FALSE: Disable maximum data bit detection + boolean_t bBusErrorPulseOutput; ///< TRUE : Enable Bus error pulse detection, FALSE: Disable Bus error detection + uint8_t u8StartBitWidth; ///< Start bit width + uint8_t u8MinPulseWidth; ///< Minimum pulse width setting + uint8_t u8ThresholdWidth; ///< Theshold width setting + uint8_t u8MinDataWidth; ///< Minimum data width setting + uint8_t u8MaxDataWidth; ///< Maximum data width setting + stc_rc_rx_addr_t stcAddr; ///< Address setting which is used to compare with device address +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + stc_rc_rx_cec_irq_en_t* pstcIrqEn; ///< Pointer to interrupt request enable setting structure of RC with CEC mode + stc_rc_rx_cec_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt request callback functions structure of RC with CEC mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_rc_rx_cec_config_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver SIRCS data format + ******************************************************************************/ +typedef struct rc_rx_sircs_data +{ + uint8_t u8Command; ///< SIRCS command + uint8_t u8DeviceAddress; ///< SIRCS Device address (5-bit) + uint8_t u8Data0; ///< SIRCS data 0 (3-bit) + uint8_t u8Data1; ///< SIRCS data 1 (5-bit) + +}rc_rx_sircs_data_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver NEC data format + ******************************************************************************/ +typedef struct rc_rx_nec_data +{ + uint16_t u16CustomCode; ///< NEC custom code + uint8_t u8Data0; ///< NEC data code 0 + uint8_t u8Data1; ///< NEC data code 1 + +}rc_rx_nec_data_t; + +/** + ****************************************************************************** + ** \brief Remoter Control Receiver CEC mode configuration + ******************************************************************************/ +typedef struct stc_rc_tx_cec_config +{ + en_rc_src_clk_t enSrcClk; ///< Source clock + uint16_t u16DivVal; ///< Clock division value + uint8_t u8FreeCycle; ///< Signal free time setting bits (0~15) +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) || \ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) + stc_rc_tx_cec_irq_en_t* pstcIrqEn; ///< Pointer to interrupt request enable setting structure of RC with Tx mode + stc_rc_tx_cec_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt request callback functions structure of RC with Tx mode + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_rc_tx_cec_config_t; + + +/// RC instance data type +typedef struct stc_rc_instance_data +{ + volatile stc_rcn_t* pstcInstance; ///< pointer to registers of an instance + stc_rc_intern_data_t stcInternData; ///< module internal data of instance +} stc_rc_instance_data_t; + +/** \} GroupRC_DataStructures */ + +/** +* \addtogroup GroupRC_GlobalVariables +* \{ +*/ +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + extern stc_rc_instance_data_t m_astcRcInstanceDataLut[RC_INSTANCE_COUNT]; + + /** \} GroupRC_GlobalVariables */ + +/** +* \addtogroup GroupRC_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +/* Remote Control Reception SIRCS mode */ +en_result_t Rc_Rx_Sircs_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_rx_sircs_config_t *pstcRcSircsConfig); +en_result_t Rc_Rx_Sircs_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic); +en_result_t Rc_Rx_Sircs_EnableRx(volatile stc_rcn_t *pstcRc); +en_result_t Rc_Rx_Sircs_DisableRx(volatile stc_rcn_t *pstcRc); + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) ||\ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +en_result_t Rc_Rx_Sircs_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Sircs_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel); +#endif +boolean_t Rc_Rx_Sircs_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Sircs_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_sircs_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Sircs_ReadData(volatile stc_rcn_t *pstcRc, + rc_rx_sircs_data_t* pstcData); + +/* Remote Control Reception NEC mode */ +en_result_t Rc_Rx_Nec_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_rx_nec_config_t *pstcRcNecConfig); +en_result_t Rc_Rx_Nec_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic); +en_result_t Rc_Rx_Nec_EnableRx(volatile stc_rcn_t *pstcRc); +en_result_t Rc_Rx_Nec_DisableRx(volatile stc_rcn_t *pstcRc); +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) ||\ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +en_result_t Rc_Rx_Nec_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Nec_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel); +#endif +boolean_t Rc_Rx_Nec_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Nec_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_nec_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Nec_ReadData(volatile stc_rcn_t *pstcRc, + rc_rx_nec_data_t* pstcData); + +/* Remote Control Reception CEC mode */ +en_result_t Rc_Rx_Cec_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_rx_cec_config_t *pstcRcCecConfig); +en_result_t Rc_Rx_Cec_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic); +en_result_t Rc_Rx_Cec_EnableRx(volatile stc_rcn_t *pstcRc); +en_result_t Rc_Rx_Cec_DisableRx(volatile stc_rcn_t *pstcRc); + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) ||\ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +en_result_t Rc_Rx_Cec_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Cec_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel); +#endif +boolean_t Rc_Rx_Cec_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel); +en_result_t Rc_Rx_Cec_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_rx_cec_irq_sel_t enIrqSel); +uint8_t Rc_Rx_Cec_ReadData(volatile stc_rcn_t *pstcRc); +boolean_t Rc_Rx_Cec_GetEomState(volatile stc_rcn_t *pstcRc); +en_result_t Rc_Rx_Cec_ClrEomState(volatile stc_rcn_t *pstcRc); + + +/* Remote Control Transmission CEC mode */ +en_result_t Rc_Tx_Cec_Init(volatile stc_rcn_t *pstcRc, + const stc_rc_tx_cec_config_t *pstcRcCecConfig); +en_result_t Rc_Tx_Cec_DeInit(volatile stc_rcn_t *pstcRc, boolean_t bTouchNvic); +en_result_t Rc_Tx_Cec_EnableTx(volatile stc_rcn_t *pstcRc); +en_result_t Rc_Tx_Cec_DisableTx(volatile stc_rcn_t *pstcRc); + +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) ||\ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +en_result_t Rc_Tx_Cec_EnableIrq(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel); +en_result_t Rc_Tx_Cec_DisableIrq(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel); +#endif +boolean_t Rc_Tx_Cec_GetIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel); +en_result_t Rc_Tx_Cec_ClrIrqFlag(volatile stc_rcn_t *pstcRc, + en_rc_tx_cec_irq_sel_t enIrqSel); +boolean_t Rc_Tx_GetAckCycleValue(volatile stc_rcn_t *pstcRc); +en_result_t Rc_Tx_Cec_WriteData(volatile stc_rcn_t *pstcRc, + uint8_t u8Data, + en_rc_txdata_type_t enType); +en_result_t Rc_Tx_Cec_SendDataPolling( volatile stc_rcn_t *pstcRc, + uint8_t u8Header, + uint8_t* pu8Data, + uint32_t u32Size); +#if (PDL_INTERRUPT_ENABLE_RC0 == PDL_ON) ||\ + (PDL_INTERRUPT_ENABLE_RC1 == PDL_ON) +/* RC IRQ */ +void RcIrqHandler(volatile stc_rcn_t *pstcRc, + stc_rc_intern_data_t* pstcRcInternData); +#endif + + +/** \} GroupRC_Functions */ +/** \} GroupRC */ +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_RC_ACTIVE)) + +#endif /* __RC_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.c new file mode 100644 index 0000000000..3906117968 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.c @@ -0,0 +1,193 @@ +/******************************************************************************* +* \file reset.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the RESET +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "reset/reset.h" +#include + +#if (defined(PDL_PERIPHERAL_RESET_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +stc_reset_result_t stcStoredResetCause; ///< Global reset cause register + + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Get current Reset Cause Register contents + ** + ** This function reads the Reset Cause Register and stores the cause bits + ** in the result structure pointer. + ** + ** \attention Calling this function clears all bits in the Reset Cause Register + ** RST_STR! Reset_GetCause() should only be called after Start-up + ** code! + ** + ** \param [out] pstcResult Reset Cause result structure + ** + ** \retval Ok Function done sucessfully + ** + ******************************************************************************/ +en_result_t Reset_GetCause(stc_reset_result_t* pstcResult) +{ + stc_crg_rst_str_field_t stcReadResetCause; + uint16_t u16ResetCause; + + u16ResetCause = FM_CRG->RST_STR; + stcReadResetCause = *(stc_crg_rst_str_field_t*)&u16ResetCause; + + // Check Power-on bit + if (1u == stcReadResetCause.PONR) + { + pstcResult->bPowerOn = TRUE; + } + else + { + pstcResult->bPowerOn = FALSE; + } + + // Check INITX/External Reset bit + if (1u == stcReadResetCause.INITX) + { + pstcResult->bInitx = TRUE; + } + else + { + pstcResult->bInitx = FALSE; + } + +#if (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) + // Check Low Voltage Detection bit + if (1u == stcReadResetCause.LVDH) + { + pstcResult->bLowVoltageDetection = TRUE; + } + else + { + pstcResult->bLowVoltageDetection = FALSE; + } +#endif + + // Check Software Watchdog bit + if (1u == stcReadResetCause.SWDT) + { + pstcResult->bSoftwareWatchdog = TRUE; + } + else + { + pstcResult->bSoftwareWatchdog = FALSE; + } + + // Check Hardware Watchdog bit + if (1u == stcReadResetCause.HWDT) + { + pstcResult->bHardwareWatchdog = TRUE; + } + else + { + pstcResult->bHardwareWatchdog = FALSE; + } + + // Check Clock Supervisor bit + if (1u == stcReadResetCause.CSVR) + { + pstcResult->bClockSupervisor = TRUE; + } + else + { + pstcResult->bClockSupervisor = FALSE; + } + + // Check Anomalous Frequency bit + if (1u == stcReadResetCause.FCSR) + { + pstcResult->bAnomalousFrequency = TRUE; + } + else + { + pstcResult->bAnomalousFrequency = FALSE; + } + + // Check Software Reset bit + if (1u == stcReadResetCause.SRST) + { + pstcResult->bSoftware = TRUE; + } + else + { + pstcResult->bSoftware = FALSE; + } + + // Copy reset cause structure argument contents to global reset cause structure + memcpy(&stcStoredResetCause, pstcResult, sizeof(stcStoredResetCause)); + + return Ok; +} // Reset_GetCause + +/** + ****************************************************************************** + ** \brief Get stored Reset Cause + ** + ** This function reads the gloabal Reset Cause Variable + ** + ** \pre Reset_GetCause() must be called before. + ** + ** \param [out] pstcResult Reset Cause result structure + ** + ** \retval Ok Function done sucessfully + ** + ******************************************************************************/ +en_result_t Reset_GetStoredCause( stc_reset_result_t* pstcResult ) +{ + // Copy global reset cause structure contents to reset cause structure argument + memcpy(pstcResult, &stcStoredResetCause, sizeof(stcStoredResetCause)); + + return Ok; +} + +#endif // #if (defined(PDL_PERIPHERAL_RESET_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.h new file mode 100644 index 0000000000..3156a620cf --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/reset/reset.h @@ -0,0 +1,149 @@ +/******************************************************************************* +* \file reset.h +* +* \version 1.20 +* +* \brief Headerfile for RESET functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __RESET_H__ +#define __RESET_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl_user.h" +#include "mcu.h" + +#if (defined(PDL_PERIPHERAL_RESET_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupRESET Reset (RESET) +* \{ +* \defgroup GroupRESET_Functions Functions +* \defgroup GroupRESET_DataStructures Data Structures +* \} +*/ + +/** +* \addtogroup GroupRESET +* \{ +* The Reset peripheral lets you to determine the cause of a device reset: +* - Power-on +* - INITX pin input +* - External power supply/low-voltage detection +* - Software watchdog +* - Hardware watchdog +* - Clock failure detection +* - Anomalous frequency detection +* - Software +* - Deep standby transition +* +* \note There are differences in the reset factor registers among the FM3 device +* types. FM3 types 3 and 7 provide an additional LVDH bit, which indicates a +* low-voltage detection reset. FM3 device types 3 and 7 provide an additional +* deep-standby transition reset factor indication besides power-on reset and +* low-voltage reset. FM0+ and FM4 devices do not provide low-voltage and +* deep-standby transition reset factors. +* +* \section SectionRESET_ConfigurationConsideration Configuration Consideration +* This peripheral does not require configuration. To use the functions in this peripheral, +* declare an stc_reset_result_t structure to receive the results.
+* Call Reset_GetCause() to get the reset cause. This fills in the stc_reset_result_t structure, +* and stores the same information for later reference. This function clears the hardware register, +* so the source of the reset is no longer obtainable directly.
+* After getting the reset cause, you can use Reset_GetStoredCause() to get the stored value, +* without touching the reset cause register.
+* \note Do not call Reset_GetCause() before startup code has executed. +* +* \section SectionRESET_MoreInfo More Information +* For more information on the RESET peripheral, refer to:
+* FM0+ Peripheral Manual - Core Subsystem TRM.pdf
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/** +* \addtogroup GroupRESET_DataStructures +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Datatype for Reset Cause return structure + ******************************************************************************/ +typedef struct stc_reset_result +{ + boolean_t bPowerOn; ///< TRUE: Power on reset occurred + boolean_t bInitx; ///< TRUE: INITX (external) reset occurred +#if (PDL_MCU_TYPE == PDL_FM3_TYPE3) || (PDL_MCU_TYPE == PDL_FM3_TYPE7) + boolean_t bLowVoltageDetection; ///< TRUE: Low Voltage Detection reset ocucrred (only applicable for FM3 Type3 and 7, always FALSE otherwise) +#endif + boolean_t bSoftwareWatchdog; ///< TRUE: Software Watchdog reset occurred + boolean_t bHardwareWatchdog; ///< TRUE: Hardware Watchdog reset occurred + boolean_t bClockSupervisor; ///< TRUE: Clock Supervisor reset occurred + boolean_t bAnomalousFrequency; ///< TRUE: Anomalous Frequency reset occurred + boolean_t bSoftware; ///< TRUE: Software reset occurred +} stc_reset_result_t ; + +/** \} GroupRESET_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupRESET_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +extern en_result_t Reset_GetCause( stc_reset_result_t* pstcResult ) ; +extern en_result_t Reset_GetStoredCause( stc_reset_result_t* pstcResult ); + +/** \} GroupRESET_Functions */ +/** \} GroupRESET */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_RESET_ACTIVE)) + +#endif /* __RESET_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.c new file mode 100644 index 0000000000..4abf015406 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.c @@ -0,0 +1,2836 @@ +/******************************************************************************* +* \file rtc.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the RTC +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "rtc/rtc.h" + +#if (defined(PDL_PERIPHERAL_RTC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/* Timeout count */ +#define RTC_TIMEOUT (SystemCoreClock/10u) +/* Error code for mktime */ +#define RTC_ERR (-1) +/* convert DEC to BCD */ +#define DecToBcd(x) ((((x)/10)<<4) + ((x)%10)) +/* convert BCD to DEC */ +#define BcdToDec(x) ((((x)>>4)*10) + ((x)&0x0F)) + +/* WTCR20 bit mapping */ +#define RTC_WTCR20_PWRITE (0x20u) +#define RTC_WTCR20_PREAD (0x10u) +#define RTC_WTCR20_BWRITE (0x08u) +#define RTC_WTCR20_BREAD (0x04u) +#define RTC_WTCR20_CWRITE (0x02u) +#define RTC_WTCR20_CREAD (0x01u) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/// Look-up table for all enabled RTC instances and their internal data +stc_rtc_instance_data_t m_astcRtcInstanceDataLut[RTC_INSTANCE_COUNT] = +{ +#if (PDL_PERIPHERAL_ENABLE_RTC0 == PDL_ON) + { + &RTC0, // pstcInstance + { + 0u,0u,0u,0u,0u,0u,0u + } + }, +#endif +}; + + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static void RtcToTm( stc_rtc_time_t* pstcRtcTime, + struct tm* pstcTime); +static void RtcDisableNvic(void); +static void RtcRestoreNvic(void); + +#if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) +static void RtcInitNvic(volatile stc_rtcn_t* pstcRtc); +static void RtcDeInitNvic(volatile stc_rtcn_t* pstcRtc); +#endif + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static uint32_t u32NvicData; + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain RTC instance. + ** + ** \param pstcRtc Pointer to RTC instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_rtc_intern_data_t* RtcGetInternDataPtr(volatile stc_rtcn_t* pstcRtc) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < RTC_INSTANCE_COUNT; u8Instance++) + { + if (pstcRtc == m_astcRtcInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcRtcInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) +/** + ****************************************************************************** + ** \brief Wait to complete writing transmission + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** + ** \retval Ok Success to complete transmission + ** \retval ErrorTimeout Timeout to complete transmission + ** + ******************************************************************************/ +static en_result_t RtcWaitTransComplete(volatile stc_rtcn_t* pstcRtc) +{ + en_result_t enResult = Ok; + uint32_t u32WaitCompleteTimeout; + + u32WaitCompleteTimeout = RTC_TIMEOUT; + while ((TRUE == pstcRtc->WTCR10_f.TRANS) /* Wait until transmission is completed */ + && (0u != u32WaitCompleteTimeout) /* If transmission is not completed even if it passes for a long time... */ + ) + { + PDL_WAIT_LOOP_HOOK(); + u32WaitCompleteTimeout--; + } + + if (0u == u32WaitCompleteTimeout) + { + enResult = ErrorTimeout; + } + + return (enResult); +} /* RtcWaitTransComplete */ + +/** + ****************************************************************************** + ** \brief Transfer to/from VBAT domain and wait to complete transmission + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] u8Control Control to transmission + ** + ** \retval Ok Success to complete transmission + ** \retval ErrorTimeout Timeout to complete transmission + ** + ******************************************************************************/ +static en_result_t RtcTransWithVbat(volatile stc_rtcn_t* pstcRtc, + uint8_t u8Control) +{ + en_result_t enResult; + + /* Transmit to or from VBAT domain */ + FM_RTC->WTCR20 = u8Control; + /* Wait to complete transmission */ + enResult = RtcWaitTransComplete(pstcRtc); + + return (enResult); +} /* RtcTransToVbat */ +#endif + +/** + ****************************************************************************** + ** \brief Disable RTC NVIC and save original value + ******************************************************************************/ +static void RtcDisableNvic(void) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + u32NvicData = NVIC->ISER[(uint32_t)((int32_t)RTC_IRQn) >> 5u]; + NVIC->ICER[((uint32_t)(RTC_IRQn) >> 5u)] = (1ul << ((uint32_t)(RTC_IRQn) & 0x1Fu)); +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + u32NvicData = NVIC->ISER[(uint32_t)((int32_t)TIM_SMCIF1_HDMICEC1_IRQn) >> 5u]; + NVIC->ICER[((uint32_t)(TIM_SMCIF1_HDMICEC1_IRQn) >> 5u)] = (1ul << ((uint32_t)(TIM_SMCIF1_HDMICEC1_IRQn) & 0x1Fu)); + #else + u32NvicData = NVIC->ISER[(uint32_t)((int32_t)TIM_IRQn) >> 5u]; + NVIC->ICER[((uint32_t)(TIM_IRQn) >> 5u)] = (1ul << ((uint32_t)(TIM_IRQn) & 0x1Fu)); + #endif +#else + u32NvicData = NVIC->ISER[(uint32_t)((int32_t)TIM_WC_RTC_IRQn) >> 5u]; + NVIC->ICER[((uint32_t)(TIM_WC_RTC_IRQn) >> 5u)] = (1ul << ((uint32_t)(TIM_WC_RTC_IRQn) & 0x1Fu)); +#endif +} + +/** + ****************************************************************************** + ** \brief Restore RTC NVIC + ******************************************************************************/ +static void RtcRestoreNvic(void) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC->ISER[(uint32_t)((int32_t)RTC_IRQn) >> 5u] = u32NvicData; +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + NVIC->ISER[(uint32_t)((int32_t)TIM_SMCIF1_HDMICEC1_IRQn) >> 5u] = u32NvicData; + #else + NVIC->ISER[(uint32_t)((int32_t)TIM_IRQn) >> 5u] = u32NvicData; + #endif +#else + NVIC->ISER[(uint32_t)((int32_t)TIM_WC_RTC_IRQn) >> 5u] = u32NvicData; +#endif +} + + +/** + ****************************************************************************** + ** \brief Convert RTC time structure to time.h tm structure + ** + ** \param [in] pstcRtcTime RTC Time structure + ** \param [out] pstcTime tm Time structure + ** + ******************************************************************************/ +static void RtcToTm( stc_rtc_time_t* pstcRtcTime, + struct tm* pstcTime) +{ + pstcTime->tm_year = (int)(pstcRtcTime->u16Year - 1900u); + pstcTime->tm_mon = (int)(pstcRtcTime->u8Month - 1u); + pstcTime->tm_mday = (int)(pstcRtcTime->u8Day); + pstcTime->tm_sec = (int)(pstcRtcTime->u8Second); + pstcTime->tm_min = (int)(pstcRtcTime->u8Minute); + pstcTime->tm_hour = (int)(pstcRtcTime->u8Hour); + pstcTime->tm_isdst = 0; +} /* RtcToTm */ + +#if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in pdl_user.h + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** + ******************************************************************************/ +static void RtcInitNvic(volatile stc_rtcn_t* pstcRtc) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_EnableIRQ(RTC_IRQn); + NVIC_SetPriority(RTC_IRQn, PDL_IRQ_LEVEL_RTC0); +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_EnableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #else + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_EnableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_IRQ_LEVEL_TIM); + #endif +#else + NVIC_ClearPendingIRQ(TIM_WC_RTC_IRQn); + NVIC_EnableIRQ(TIM_WC_RTC_IRQn); + NVIC_SetPriority(TIM_WC_RTC_IRQn, PDL_IRQ_LEVEL_CLK_WC_RTC); +#endif + +} /* RtcInitIrq */ + +/** + ****************************************************************************** + ** \brief Device dependent de-initialization of interrupts according CMSIS with + ** level defined in pdl.h + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** + ******************************************************************************/ +static void RtcDeInitNvic(volatile stc_rtcn_t* pstcRtc) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(RTC_IRQn); + NVIC_DisableIRQ(RTC_IRQn); + NVIC_SetPriority(RTC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_DisableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #else + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_DisableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#else + NVIC_ClearPendingIRQ(TIM_WC_RTC_IRQn); + NVIC_DisableIRQ(TIM_WC_RTC_IRQn); + NVIC_SetPriority(TIM_WC_RTC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +} /* RtcDeInitIrq */ + +/** + ****************************************************************************** + ** \brief RTC interrupt service routine. + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] pstcRtcInternData Pointer to RTC intern data + ******************************************************************************/ +void Rtc_IrqHandler(volatile stc_rtcn_t* pstcRtc, stc_rtc_intern_data_t* pstcRtcInternData) +{ +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + + stc_rtc_wtcr12_field_t stcWtcr12; + stc_rtc_wtcr11_field_t stcWtcr11; + stc_rtc_time_t stcTime; + boolean_t bAlarmMatch = TRUE; + + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return; + } + + /* Read interrupt flags */ + stcWtcr12 = pstcRtc->WTCR12_f; + /* Read alarm enable bits */ + stcWtcr11 = pstcRtc->WTCR11_f; + + /* Timer writing error Interrupt? */ + if (TRUE == stcWtcr12.INTERI) + { + /* Clear INTERI Flag */ + stcWtcr12.INTERI = FALSE; + + if (NULL != pstcRtcInternData->pfnTimeWrtErrIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnTimeWrtErrIrqCb(); + } + } + + /* Alarm Completion? */ + if (TRUE == stcWtcr12.INTALI) + { + /* Clear INTALI Flag */ + stcWtcr12.INTALI = FALSE; + + Rtc_ReadDateTime(pstcRtc, &stcTime); + + if(stcWtcr11.MIEN) + { + if(pstcRtc->ALMIR != DecToBcd(stcTime.u8Minute)) bAlarmMatch = FALSE; + } + if(stcWtcr11.HEN) + { + if(pstcRtc->ALHR != DecToBcd(stcTime.u8Hour)) bAlarmMatch = FALSE; + } + if(stcWtcr11.DEN) + { + if(pstcRtc->ALDR != DecToBcd(stcTime.u8Day)) bAlarmMatch = FALSE; + } + if(stcWtcr11.MOEN) + { + if(pstcRtc->ALMOR != DecToBcd(stcTime.u8Month)) bAlarmMatch = FALSE; + } + if(stcWtcr11.YEN) + { + if(pstcRtc->ALYR != DecToBcd(stcTime.u16Year - 2000u)) bAlarmMatch = FALSE; + } + + if(bAlarmMatch == TRUE) + { + if (NULL != pstcRtcInternData->pfnAlarmIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnAlarmIrqCb(); + } + } + } + + /* Timer Interrupt? */ + if (TRUE == stcWtcr12.INTTMI) + { + /* Clear INTTMI Flag */ + stcWtcr12.INTTMI = FALSE; + + if (NULL != pstcRtcInternData->pfnTimerIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnTimerIrqCb(); + } + } + + /* 0.5-Second Interrupt? */ + if (TRUE == stcWtcr12.INTSSI) + { + /* Clear INTSSI Flag */ + stcWtcr12.INTSSI = FALSE; + + if (NULL != pstcRtcInternData->pfnHalfSecondIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnHalfSecondIrqCb(); + } + } + + /* One Second Interrupt? */ + if (TRUE == stcWtcr12.INTSI) + { + /* Clear INTSI Flag */ + stcWtcr12.INTSI = FALSE; + + if (NULL != pstcRtcInternData->pfnOneSecondIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnOneSecondIrqCb(); + } + } + + /* One Minute Interrupt? */ + if (TRUE == stcWtcr12.INTMI) + { + /* Clear INTMI Flag */ + stcWtcr12.INTMI = FALSE; + + if (NULL != pstcRtcInternData->pfnOneMinuteIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnOneMinuteIrqCb(); + } + } + + /* One Hour Interrupt? */ + if (TRUE == stcWtcr12.INTHI) + { + /* Clear INTHI Flag */ + stcWtcr12.INTHI = FALSE; + + if (NULL != pstcRtcInternData->pfnOneHourIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnOneHourIrqCb(); + } + } + + pstcRtc->WTCR12_f = stcWtcr12; + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return; + } +#else + + stc_rtc_wtcr1_field_t stcWtcr1; + stc_rtc_time_t stcTime; + boolean_t bAlarmMatch = TRUE; + + /* Read interrupt flags */ + /* Read alarm enable bits */ + stcWtcr1 = pstcRtc->WTCR1_f; + + + /* Timer writing error Interrupt? */ + if (TRUE == stcWtcr1.INTERI) + { + /* Clear INTERI Flag */ + stcWtcr1.INTERI = FALSE; + + if (NULL != pstcRtcInternData->pfnTimeWrtErrIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnTimeWrtErrIrqCb(); + } + } + + /* Alarm Completion? */ + if (TRUE == stcWtcr1.INTALI) + { + /* Clear INTALI Flag */ + stcWtcr1.INTALI = FALSE; + + Rtc_ReadDateTime(pstcRtc, &stcTime); + + if(stcWtcr1.MIEN) + { + if(pstcRtc->ALMIR != DecToBcd(stcTime.u8Minute)) bAlarmMatch = FALSE; + } + if(stcWtcr1.HEN) + { + if(pstcRtc->ALHR != DecToBcd(stcTime.u8Hour)) bAlarmMatch = FALSE; + } + if(stcWtcr1.DEN) + { + if(pstcRtc->ALDR != DecToBcd(stcTime.u8Day)) bAlarmMatch = FALSE; + } + if(stcWtcr1.MOEN) + { + if(pstcRtc->ALMOR != DecToBcd(stcTime.u8Month)) bAlarmMatch = FALSE; + } + if(stcWtcr1.YEN) + { + if(pstcRtc->ALYR != DecToBcd(stcTime.u16Year - 2000u)) bAlarmMatch = FALSE; + } + + if(bAlarmMatch == TRUE) + { + if (NULL != pstcRtcInternData->pfnAlarmIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnAlarmIrqCb(); + } + } + } + + /* Timer Interrupt? */ + if (TRUE == stcWtcr1.INTTMI) + { + /* Clear INTTMI Flag */ + stcWtcr1.INTTMI = FALSE; + + if (NULL != pstcRtcInternData->pfnTimerIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnTimerIrqCb(); + } + } + + /* 0.5-Second Interrupt? */ + if (TRUE == stcWtcr1.INTSSI) + { + /* Clear INTSSI Flag */ + stcWtcr1.INTSSI = FALSE; + + if (NULL != pstcRtcInternData->pfnHalfSecondIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnHalfSecondIrqCb(); + } + } + + /* One Second Interrupt? */ + if (TRUE == stcWtcr1.INTSI) + { + /* Clear INTSI Flag */ + stcWtcr1.INTSI = FALSE; + + if (NULL != pstcRtcInternData->pfnOneSecondIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnOneSecondIrqCb(); + } + } + + /* One Minute Interrupt? */ + if (TRUE == stcWtcr1.INTMI) + { + /* Clear INTMI Flag */ + stcWtcr1.INTMI = FALSE; + + if (NULL != pstcRtcInternData->pfnOneMinuteIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnOneMinuteIrqCb(); + } + } + + /* One Hour Interrupt? */ + if (TRUE == stcWtcr1.INTHI) + { + /* Clear INTHI Flag */ + stcWtcr1.INTHI = FALSE; + + if (NULL != pstcRtcInternData->pfnOneHourIrqCb) + { + /* Callback */ + pstcRtcInternData->pfnOneHourIrqCb(); + } + } + + pstcRtc->WTCR1_f = stcWtcr1; + + +#endif +} /* RtcIrqHandler */ + +/** + ****************************************************************************** + ** \brief Enable RTC (and Timer) Interrupt + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] enIrqSel RTC interrupt type + ** + ** \retval Ok Interrupt selected is enabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcRtc == NULL + ** - enIrqSel out of range + ** + ******************************************************************************/ +en_result_t Rtc_EnableIrq(volatile stc_rtcn_t* pstcRtc, + en_rtc_irq_sel_t enIrqSel) +{ + /* Check for valid pointer */ + if ((NULL == pstcRtc)) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + pstcRtc->WTCR13_f.INTSSIE = 1u; + break; + case RtcOneSecondIrq: + pstcRtc->WTCR13_f.INTSIE = 1u; + break; + case RtcOneMinuteIrq: + pstcRtc->WTCR13_f.INTMIE = 1u; + break; + case RtcOneHourIrq: + pstcRtc->WTCR13_f.INTHIE = 1u; + break; + case RtcTimerIrq: + pstcRtc->WTCR13_f.INTTMIE = 1u; + break; + case RtcAlarmIrq: + pstcRtc->WTCR13_f.INTALIE = 1u; + break; + case RtcTimeRewriteErrorIrq: + pstcRtc->WTCR13_f.INTERIE = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + +#else + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + pstcRtc->WTCR1_f.INTSSIE = 1u; + break; + case RtcOneSecondIrq: + pstcRtc->WTCR1_f.INTSIE = 1u; + break; + case RtcOneMinuteIrq: + pstcRtc->WTCR1_f.INTMIE = 1u; + break; + case RtcOneHourIrq: + pstcRtc->WTCR1_f.INTHIE = 1u; + break; + case RtcTimerIrq: + pstcRtc->WTCR1_f.INTTMIE = 1u; + break; + case RtcAlarmIrq: + pstcRtc->WTCR1_f.INTALIE = 1u; + break; + case RtcTimeRewriteErrorIrq: + pstcRtc->WTCR1_f.INTERIE = 1u; + break; + default: + return ErrorInvalidParameter; + } + +#endif + + return (Ok); +} /* Rtc_EnableDisableInterrupts */ + +/** + ****************************************************************************** + ** \brief Disable RTC (and Timer) Interrupt + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] enIrqSel RTC interrupt type + ** + ** \retval Ok Interrupt selected is disabled + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcRtc == NULL + ** - enIrqSel out of range + ** + ******************************************************************************/ +en_result_t Rtc_DisableIrq(volatile stc_rtcn_t* pstcRtc, + en_rtc_irq_sel_t enIrqSel) +{ + /* Check for valid pointer */ + if ((NULL == pstcRtc)) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + pstcRtc->WTCR13_f.INTSSIE = 0u; + break; + case RtcOneSecondIrq: + pstcRtc->WTCR13_f.INTSIE = 0u; + break; + case RtcOneMinuteIrq: + pstcRtc->WTCR13_f.INTMIE = 0u; + break; + case RtcOneHourIrq: + pstcRtc->WTCR13_f.INTHIE = 0u; + break; + case RtcTimerIrq: + pstcRtc->WTCR13_f.INTTMIE = 0u; + break; + case RtcAlarmIrq: + pstcRtc->WTCR13_f.INTALIE = 0u; + break; + case RtcTimeRewriteErrorIrq: + pstcRtc->WTCR13_f.INTERIE = 0u; + break; + default: + return ErrorInvalidParameter; + } + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + +#else + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + pstcRtc->WTCR1_f.INTSSIE = 0u; + break; + case RtcOneSecondIrq: + pstcRtc->WTCR1_f.INTSIE = 0u; + break; + case RtcOneMinuteIrq: + pstcRtc->WTCR1_f.INTMIE = 0u; + break; + case RtcOneHourIrq: + pstcRtc->WTCR1_f.INTHIE = 0u; + break; + case RtcTimerIrq: + pstcRtc->WTCR1_f.INTTMIE = 0u; + break; + case RtcAlarmIrq: + pstcRtc->WTCR1_f.INTALIE = 0u; + break; + case RtcTimeRewriteErrorIrq: + pstcRtc->WTCR1_f.INTERIE = 0u; + break; + default: + return ErrorInvalidParameter; + } + +#endif + + return (Ok); +} /* Rtc_EnableDisableInterrupts */ + +#endif + +/** + ****************************************************************************** + ** \brief Initialize RTC + ** + ** This function initializes the RTC module + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] pstcConfig Pointer to RTC configuration structure + ** + ** \retval Ok RTC initialization completed normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcConfig == NULL + ** - Invalid value of a pstcConfig's element + ** + ******************************************************************************/ +en_result_t Rtc_Init(volatile stc_rtcn_t* pstcRtc , + const stc_rtc_config_t* pstcConfig) +{ + // Pointer to internal data + stc_rtc_intern_data_t* pstcRtcInternData ; + uint32_t u32Timeout = RTC_TIMEOUT; + uint32_t u32Count; + + if((NULL == pstcConfig) || (NULL == pstcRtc)) + { + return ErrorInvalidParameter; + } + + /* Get pointer to internal data structure ... */ + pstcRtcInternData = RtcGetInternDataPtr( pstcRtc ) ; + + /* Check for instance available or not */ + if(NULL == pstcRtcInternData) + { + return ErrorInvalidParameter ; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + /* Recall the data from VBAT to RTC clock registers of VBAT */ + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PREAD)) + { + return ErrorTimeout; + } + + /* Recall the data from VBAT to RTC registers of VBAT */ + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + if((TRUE == pstcConfig->bRunNotInit) && (1u == FM_RTC->WTCR10_f.RUN)) /* RTC is running ? */ + { + /* + * If bRunNotInit is TRUE, don't do initialization RTC is aready running. + * However the interrupt callback and NVIC still need updating. + */ + /* Clear all flags */ + pstcRtc->WTCR12 = 0x00u; + + /* if WTCR21 is cleared, re-configure RTC timer */ + if (0u == pstcRtc->WTCR21) + { + if(NULL != pstcConfig->pstcTimer) + { + switch (pstcConfig->pstcTimer->enMode) + { + case RtcTimerOneshot: + pstcRtc->WTCR21_f.TMEN = 0u; + break; + case RtcTimerPeriod: + pstcRtc->WTCR21_f.TMEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + if(pstcConfig->pstcTimer->u32TimerCycle > RTC_MAX_TIMER_SET_VALUE) + { + return ErrorInvalidParameter; + } + + u32Count = (pstcConfig->pstcTimer->u32TimerCycle*2u) - 1u; + + pstcRtc->WTTR0 = (uint8_t)u32Count; + pstcRtc->WTTR1 = (uint8_t)(u32Count >> 8u); + pstcRtc->WTTR2 = (uint8_t)(u32Count >> 16u); + } + } + + #if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) + /* if WTCR3 is cleared , re-configure interrupt */ + if(0u == pstcRtc->WTCR13) + { + if (NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTimeRewriteErrorIrq) + { + pstcRtc->WTCR13_f.INTERIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bAlarmIrq) + { + pstcRtc->WTCR13_f.INTALIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTimerIrq) + { + pstcRtc->WTCR13_f.INTTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneHourIrq) + { + pstcRtc->WTCR13_f.INTHIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneMinuteIrq) + { + pstcRtc->WTCR13_f.INTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneSecondIrq) + { + pstcRtc->WTCR13_f.INTSIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bHalfSecondIrq) + { + pstcRtc->WTCR13_f.INTSSIE = 1u; + } + } + } + /* Configure interrupt callback functions */ + if (NULL != pstcConfig->pstcIrqCb) + { + pstcRtcInternData->pfnTimeWrtErrIrqCb = pstcConfig->pstcIrqCb->pfnTimeWrtErrIrqCb; + pstcRtcInternData->pfnAlarmIrqCb = pstcConfig->pstcIrqCb->pfnAlarmIrqCb; + pstcRtcInternData->pfnTimerIrqCb = pstcConfig->pstcIrqCb->pfnTimerIrqCb; + pstcRtcInternData->pfnOneHourIrqCb = pstcConfig->pstcIrqCb->pfnOneHourIrqCb; + pstcRtcInternData->pfnOneMinuteIrqCb = pstcConfig->pstcIrqCb->pfnOneMinuteIrqCb; + pstcRtcInternData->pfnOneSecondIrqCb = pstcConfig->pstcIrqCb->pfnOneSecondIrqCb; + pstcRtcInternData->pfnHalfSecondIrqCb = pstcConfig->pstcIrqCb->pfnHalfSecondIrqCb; + } + + /* Configure NVIC */ + if (TRUE == pstcConfig->bTouchNvic) + { + RtcInitNvic(pstcRtc); + } + #endif + return Ok; + } + + /* For initialization: Force all bits of WTCR1 and WTCR2 (inclusive ST bit) */ + /* to '0' */ + pstcRtc->WTCR10 = 0u; + pstcRtc->WTCR11 = 0u; + pstcRtc->WTCR12 = 0u; + pstcRtc->WTCR13 = 0u; + pstcRtc->WTCR20 = 0u; + pstcRtc->WTCR21 = 0u; + + // Save RTC register data from buffer to VBAT domain (load WTCR1, WTCR2 to clear RTC) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + + if(pstcConfig->bEnSuboutDivider == TRUE) + { + /* Disable divider */ + pstcRtc->WTDIVEN_f.WTDIVEN = 0u; + + /* Set Divider ratio */ + switch (pstcConfig->enDividerRatio) + { + case RtcDivRatio1: + case RtcDivRatio2: + case RtcDivRatio4: + case RtcDivRatio8: + case RtcDivRatio16: + case RtcDivRatio32: + case RtcDivRatio64: + case RtcDivRatio128: + case RtcDivRatio256: + case RtcDivRatio512: + case RtcDivRatio1024: + case RtcDivRatio2048: + case RtcDivRatio4096: + case RtcDivRatio8192: + case RtcDivRatio16384: + case RtcDivRatio32768: + pstcRtc->WTDIV = pstcConfig->enDividerRatio; + break; + default: + return ErrorInvalidParameter; + } + + /* Enable divider */ + u32Timeout = RTC_TIMEOUT; + pstcRtc->WTDIVEN_f.WTDIVEN = 1u; + + // Save RTC clock register data from buffer to VBAT domain (load WTDIVEN) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PWRITE)) + { + return ErrorTimeout; + } + + while(TRUE != pstcRtc->WTDIVEN_f.WTDIVRDY) + { + /* Recall the data from VBAT to RTC clock registers of VBAT */ + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PREAD)) + { + return ErrorTimeout; + } + + u32Timeout--; + if(0u == u32Timeout) + { + return ErrorInvalidParameter; + } + } + } + + /* Initial frequency correction module */ + if(NULL != pstcConfig->pstcFreqCorrConfig) + { + if(pstcConfig->pstcFreqCorrConfig->u16FreqCorrValue > RTC_MAX_FREQ_CORR_VALUE) + { + return ErrorInvalidParameter; + } + pstcRtc->WTCAL0 = (uint8_t)pstcConfig->pstcFreqCorrConfig->u16FreqCorrValue ; + + pstcRtc->WTCAL1 = (uint8_t)(pstcConfig->pstcFreqCorrConfig->u16FreqCorrValue >> 8u) ; + if(pstcConfig->pstcFreqCorrConfig->u16FreqCorrCycle > RTC_MAX_FREQ_CORR_CYCLE_SET_VALUE) + { + return ErrorInvalidParameter; + } + pstcRtc->WTCALPRD = pstcConfig->pstcFreqCorrConfig->u16FreqCorrCycle - 1; + } + + /* Configure RTCCO output */ + switch (pstcConfig->enRtccoSel) + { + case RtccoOutput2Hz: + pstcRtc->WTCOSEL_f.WTCOSEL = 0u; + break; + case RtccoOutput1Hz: + pstcRtc->WTCOSEL_f.WTCOSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + + /* Initialize time and date */ + if(NULL != pstcConfig->pstcTimeDate) + { + pstcRtc->WTSR = DecToBcd(pstcConfig->pstcTimeDate->u8Second); + pstcRtc->WTMIR = DecToBcd(pstcConfig->pstcTimeDate->u8Minute); + pstcRtc->WTHR = DecToBcd(pstcConfig->pstcTimeDate->u8Hour); + pstcRtc->WTDR = DecToBcd(pstcConfig->pstcTimeDate->u8Day); + pstcRtc->WTMOR = DecToBcd(pstcConfig->pstcTimeDate->u8Month); + pstcRtc->WTYR = DecToBcd(pstcConfig->pstcTimeDate->u16Year - 2000u); + pstcRtc->WTDW = DecToBcd(pstcConfig->pstcTimeDate->u8DayOfWeek); + } + + /* Initialize Alarm */ + if(NULL != pstcConfig->pstcAlarm) + { + pstcRtc->ALMIR = DecToBcd(pstcConfig->pstcAlarm->u8Minute); + pstcRtc->ALHR = DecToBcd(pstcConfig->pstcAlarm->u8Hour); + pstcRtc->ALDR = DecToBcd(pstcConfig->pstcAlarm->u8Day); + pstcRtc->ALMOR = DecToBcd(pstcConfig->pstcAlarm->u8Month); + pstcRtc->ALYR = DecToBcd(pstcConfig->pstcAlarm->u16Year - 2000u); + } + + if(NULL != pstcConfig->pstcTimer) + { + switch (pstcConfig->pstcTimer->enMode) + { + case RtcTimerOneshot: + pstcRtc->WTCR21_f.TMEN = 0u; + break; + case RtcTimerPeriod: + pstcRtc->WTCR21_f.TMEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + if(pstcConfig->pstcTimer->u32TimerCycle > RTC_MAX_TIMER_SET_VALUE) + { + return ErrorInvalidParameter; + } + + u32Count = (pstcConfig->pstcTimer->u32TimerCycle*2u) - 1u; + + pstcRtc->WTTR0 = (uint8_t)u32Count; + pstcRtc->WTTR1 = (uint8_t)(u32Count >> 8u); + pstcRtc->WTTR2 = (uint8_t)(u32Count >> 16u); + } + + #if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) + /* Configure interrupt */ + if (NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTimeRewriteErrorIrq) + { + pstcRtc->WTCR13_f.INTERIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bAlarmIrq) + { + pstcRtc->WTCR13_f.INTALIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTimerIrq) + { + pstcRtc->WTCR13_f.INTTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneHourIrq) + { + pstcRtc->WTCR13_f.INTHIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneMinuteIrq) + { + pstcRtc->WTCR13_f.INTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneSecondIrq) + { + pstcRtc->WTCR13_f.INTSIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bHalfSecondIrq) + { + pstcRtc->WTCR13_f.INTSSIE = 1u; + } + } + + /* Configure interrupt callback functions */ + if (NULL != pstcConfig->pstcIrqCb) + { + pstcRtcInternData->pfnTimeWrtErrIrqCb = pstcConfig->pstcIrqCb->pfnTimeWrtErrIrqCb; + pstcRtcInternData->pfnAlarmIrqCb = pstcConfig->pstcIrqCb->pfnAlarmIrqCb; + pstcRtcInternData->pfnTimerIrqCb = pstcConfig->pstcIrqCb->pfnTimerIrqCb; + pstcRtcInternData->pfnOneHourIrqCb = pstcConfig->pstcIrqCb->pfnOneHourIrqCb; + pstcRtcInternData->pfnOneMinuteIrqCb = pstcConfig->pstcIrqCb->pfnOneMinuteIrqCb; + pstcRtcInternData->pfnOneSecondIrqCb = pstcConfig->pstcIrqCb->pfnOneSecondIrqCb; + pstcRtcInternData->pfnHalfSecondIrqCb = pstcConfig->pstcIrqCb->pfnHalfSecondIrqCb; + } + + /* Configure NVIC */ + if (TRUE == pstcConfig->bTouchNvic) + { + RtcInitNvic(pstcRtc); + } + #endif + + // Save RTC clock register data from buffer to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PWRITE)) + { + return ErrorTimeout; + } + // Save RTC register data from buffer to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + +#else + if((TRUE == pstcConfig->bRunNotInit) && (1u == FM_RTC->WTCR1_f.ST)) /* RTC is running ? */ + { + /* + * If bRunNotInit is TRUE, don't do initialization RTC is aready running. + * However the interrupt callback and NVIC still need updating. + */ + /* Clear all flags */ + pstcRtc->WTCR1 = 0x00u; + + /* if WTCR21 is cleared, re-configure RTC timer */ + if (0u == pstcRtc->WTCR2) + { + if(NULL != pstcConfig->pstcTimer) + { + switch (pstcConfig->pstcTimer->enMode) + { + case RtcTimerOneshot: + pstcRtc->WTCR2_f.TMEN = 0u; + break; + case RtcTimerPeriod: + pstcRtc->WTCR2_f.TMEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + if(pstcConfig->pstcTimer->u32TimerCycle > RTC_MAX_TIMER_SET_VALUE) + { + return ErrorInvalidParameter; + } + + u32Count = (pstcConfig->pstcTimer->u32TimerCycle*2u) - 1u; + + pstcRtc->WTTR = (uint8_t)u32Count; + } + } + + #if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) + /* if WTCR3 is cleared , re-configure interrupt */ + if(0u == pstcRtc->WTCR1) + { + if (NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTimeRewriteErrorIrq) + { + pstcRtc->WTCR1_f.INTERIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bAlarmIrq) + { + pstcRtc->WTCR1_f.INTALIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTimerIrq) + { + pstcRtc->WTCR1_f.INTTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneHourIrq) + { + pstcRtc->WTCR1_f.INTHIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneMinuteIrq) + { + pstcRtc->WTCR1_f.INTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneSecondIrq) + { + pstcRtc->WTCR1_f.INTSIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bHalfSecondIrq) + { + pstcRtc->WTCR1_f.INTSSIE = 1u; + } + } + } + /* Configure interrupt callback functions */ + if (NULL != pstcConfig->pstcIrqCb) + { + pstcRtcInternData->pfnTimeWrtErrIrqCb = pstcConfig->pstcIrqCb->pfnTimeWrtErrIrqCb; + pstcRtcInternData->pfnAlarmIrqCb = pstcConfig->pstcIrqCb->pfnAlarmIrqCb; + pstcRtcInternData->pfnTimerIrqCb = pstcConfig->pstcIrqCb->pfnTimerIrqCb; + pstcRtcInternData->pfnOneHourIrqCb = pstcConfig->pstcIrqCb->pfnOneHourIrqCb; + pstcRtcInternData->pfnOneMinuteIrqCb = pstcConfig->pstcIrqCb->pfnOneMinuteIrqCb; + pstcRtcInternData->pfnOneSecondIrqCb = pstcConfig->pstcIrqCb->pfnOneSecondIrqCb; + pstcRtcInternData->pfnHalfSecondIrqCb = pstcConfig->pstcIrqCb->pfnHalfSecondIrqCb; + } + + /* Configure NVIC */ + if (TRUE == pstcConfig->bTouchNvic) + { + RtcInitNvic(pstcRtc); + } + #endif + return Ok; + } + + /* For initialization: Force all bits of WTCR1 and WTCR2 (inclusive ST bit) */ + /* to '0' */ + pstcRtc->WTCR1 = 0u; + pstcRtc->WTCR2 = 0u; + + /* Select source clock for RTC */ + switch (pstcConfig->enClkSel) + { + case RtcUseSubClk: + /* Select sub clock as source clock */ + pstcRtc->WTCLKS_f.WTCLKS = 0u; + /* Wait until sub clock stable */ + while(1) + { + if(0x02u == pstcRtc->WTCLKM_f.WTCLKM) + { + break; + } + else + { + u32Timeout--; + if(0u == u32Timeout) + { + return ErrorTimeout; + } + } + } + + pstcRtc->WTBR = (pstcConfig->u32ClkPrescaler/4u) - 1u; /* set 0.5s as sub-second interval */ + break; + case RtcuseMainClk: + /* Select main clock as source clock */ + pstcRtc->WTCLKS_f.WTCLKS = 1u; + /* Wait until main clock stable */ + while(1) + { + if(0x03u == pstcRtc->WTCLKM_f.WTCLKM) + { + break; + } + else + { + u32Timeout--; + if(0u == u32Timeout) + { + return ErrorTimeout; + } + } + } + pstcRtc->WTBR = (pstcConfig->u32ClkPrescaler/4u) - 1u; /* set 0.5s as sub-second interval */ + break; + default: + return ErrorInvalidParameter; + } + + if(pstcConfig->bEnSuboutDivider == TRUE) + { + /* Disable divider */ + pstcRtc->WTDIVEN_f.WTDIVEN = 0u; + + /* Set Divider ratio */ + switch (pstcConfig->enDividerRatio) + { + case RtcDivRatio1: + case RtcDivRatio2: + case RtcDivRatio4: + case RtcDivRatio8: + case RtcDivRatio16: + case RtcDivRatio32: + case RtcDivRatio64: + case RtcDivRatio128: + case RtcDivRatio256: + case RtcDivRatio512: + case RtcDivRatio1024: + case RtcDivRatio2048: + case RtcDivRatio4096: + case RtcDivRatio8192: + case RtcDivRatio16384: + case RtcDivRatio32768: + pstcRtc->WTDIV = pstcConfig->enDividerRatio; + break; + default: + return ErrorInvalidParameter; + } + + /* Enable divider */ + u32Timeout = RTC_TIMEOUT; + pstcRtc->WTDIVEN_f.WTDIVEN = 1u; + + while(TRUE != pstcRtc->WTDIVEN_f.WTDIVRDY) + { + u32Timeout--; + if(0u == u32Timeout) + { + return ErrorInvalidParameter; + } + } + } + + /* Initial frequency correction module */ + if(NULL != pstcConfig->pstcFreqCorrConfig) + { + if(pstcConfig->pstcFreqCorrConfig->u16FreqCorrValue > RTC_MAX_FREQ_CORR_VALUE) + { + return ErrorInvalidParameter; + } + pstcRtc->WTCAL = (uint8_t)pstcConfig->pstcFreqCorrConfig->u16FreqCorrValue ; + } + + #if defined(FM_RTC_WTCOSEL_AVAILABLE) + /* Configure RTCCO output */ + switch (pstcConfig->enRtccoSel) + { + case RtccoOutput2Hz: + pstcRtc->WTCOSEL_f.WTCOSEL = 0u; + break; + case RtccoOutput1Hz: + pstcRtc->WTCOSEL_f.WTCOSEL = 1u; + break; + default: + return ErrorInvalidParameter; + } + #endif + + /* Initialize time and date */ + if(NULL != pstcConfig->pstcTimeDate) + { + pstcRtc->WTSR = DecToBcd(pstcConfig->pstcTimeDate->u8Second); + pstcRtc->WTMIR = DecToBcd(pstcConfig->pstcTimeDate->u8Minute); + pstcRtc->WTHR = DecToBcd(pstcConfig->pstcTimeDate->u8Hour); + pstcRtc->WTDR = DecToBcd(pstcConfig->pstcTimeDate->u8Day); + pstcRtc->WTMOR = DecToBcd(pstcConfig->pstcTimeDate->u8Month); + pstcRtc->WTYR = DecToBcd(pstcConfig->pstcTimeDate->u16Year - 2000u); + pstcRtc->WTDW = DecToBcd(pstcConfig->pstcTimeDate->u8DayOfWeek); + } + + /* Initialize Alarm */ + if(NULL != pstcConfig->pstcAlarm) + { + pstcRtc->ALMIR = DecToBcd(pstcConfig->pstcAlarm->u8Minute); + pstcRtc->ALHR = DecToBcd(pstcConfig->pstcAlarm->u8Hour); + pstcRtc->ALDR = DecToBcd(pstcConfig->pstcAlarm->u8Day); + pstcRtc->ALMOR = DecToBcd(pstcConfig->pstcAlarm->u8Month); + pstcRtc->ALYR = DecToBcd(pstcConfig->pstcAlarm->u16Year - 2000u); + } + + if(NULL != pstcConfig->pstcTimer) + { + switch (pstcConfig->pstcTimer->enMode) + { + case RtcTimerOneshot: + pstcRtc->WTCR2_f.TMEN = 0u; + break; + case RtcTimerPeriod: + pstcRtc->WTCR2_f.TMEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + if(pstcConfig->pstcTimer->u32TimerCycle > RTC_MAX_TIMER_SET_VALUE) + { + return ErrorInvalidParameter; + } + + u32Count = (pstcConfig->pstcTimer->u32TimerCycle*2u) - 1u; + + pstcRtc->WTTR = (uint8_t)u32Count; + } + + #if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) + /* Configure interrupt */ + if (NULL != pstcConfig->pstcIrqEn) + { + if(TRUE == pstcConfig->pstcIrqEn->bTimeRewriteErrorIrq) + { + pstcRtc->WTCR1_f.INTERIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bAlarmIrq) + { + pstcRtc->WTCR1_f.INTALIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bTimerIrq) + { + pstcRtc->WTCR1_f.INTTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneHourIrq) + { + pstcRtc->WTCR1_f.INTHIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneMinuteIrq) + { + pstcRtc->WTCR1_f.INTMIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bOneSecondIrq) + { + pstcRtc->WTCR1_f.INTSIE = 1u; + } + + if(TRUE == pstcConfig->pstcIrqEn->bHalfSecondIrq) + { + pstcRtc->WTCR1_f.INTSSIE = 1u; + } + } + + /* Configure interrupt callback functions */ + if (NULL != pstcConfig->pstcIrqCb) + { + pstcRtcInternData->pfnTimeWrtErrIrqCb = pstcConfig->pstcIrqCb->pfnTimeWrtErrIrqCb; + pstcRtcInternData->pfnAlarmIrqCb = pstcConfig->pstcIrqCb->pfnAlarmIrqCb; + pstcRtcInternData->pfnTimerIrqCb = pstcConfig->pstcIrqCb->pfnTimerIrqCb; + pstcRtcInternData->pfnOneHourIrqCb = pstcConfig->pstcIrqCb->pfnOneHourIrqCb; + pstcRtcInternData->pfnOneMinuteIrqCb = pstcConfig->pstcIrqCb->pfnOneMinuteIrqCb; + pstcRtcInternData->pfnOneSecondIrqCb = pstcConfig->pstcIrqCb->pfnOneSecondIrqCb; + pstcRtcInternData->pfnHalfSecondIrqCb = pstcConfig->pstcIrqCb->pfnHalfSecondIrqCb; + } + + /* Configure NVIC */ + if (TRUE == pstcConfig->bTouchNvic) + { + RtcInitNvic(pstcRtc); + } + #endif + + +#endif + + return (Ok); +} /* Rtc_Init */ + +/** + ****************************************************************************** + ** \brief De-Initialize RTC + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** This function stops and resets the RTC module and its interrupts. + ** + ** \retval Ok RTC de-initialization normally + ** + ******************************************************************************/ +en_result_t Rtc_DeInit(volatile stc_rtcn_t* pstcRtc, boolean_t bTouchNvic) +{ +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + /* Set all registers of RTC instance to '0' */ + pstcRtc->WTCR10 = 0u; + pstcRtc->WTCR11 = 0u; + pstcRtc->WTCR12 = 0u; + pstcRtc->WTCR13 = 0u; + pstcRtc->WTCR20 = 0u; + pstcRtc->WTCR21 = 0u; + pstcRtc->WTCAL0 = 0u; + pstcRtc->WTCAL1 = 0u; +#else + pstcRtc->WTCR1 = 0u; + pstcRtc->WTCR2 = 0u; + pstcRtc->WTCAL = 0u; +#endif + pstcRtc->WTCALEN = 0u; + pstcRtc->WTDIV = 0u; + pstcRtc->WTDIVEN = 0u; +#if defined(FM_RTC_WTCOSEL_AVAILABLE) + pstcRtc->WTCALPRD = 0u; + pstcRtc->WTCOSEL = 0u; +#endif + pstcRtc->WTSR = 0u; + pstcRtc->WTMIR = 0u; + pstcRtc->WTHR = 0u; + pstcRtc->WTDR = 0u; + pstcRtc->WTDW = 0u; + pstcRtc->WTMOR = 0u; + pstcRtc->WTYR = 0u; + pstcRtc->ALMIR = 0u; + pstcRtc->ALHR = 0u; + pstcRtc->ALDR = 0u; + pstcRtc->ALMOR = 0u; + pstcRtc->ALYR = 0u; + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Save RTC clock register data from buffer to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PWRITE)) + { + return ErrorTimeout; + } + // Save RTC register data from buffer to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } +#endif + +#if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) + if(TRUE == bTouchNvic) + { + RtcDeInitNvic(pstcRtc); + } +#endif + + return (Ok); +} /* Rtc_DeInit */ + + +/** + ****************************************************************************** + ** \brief Enable functions of RTC + ** + ** These functions includes RTC counting, Timer, Alarm compariron and frequency + ** correction module. + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param enFunc Function types + ** \arg RtcCount RTC counting + ** \arg RtcTimer RTC timer + ** \arg RtcFreqCorr RTC frequency correction module + ** \arg RtcAlarmYearEn Year comparison enable of RTC alarm + ** \arg RtcAlarmMonthEn Month comparison enable of RTC alarm + ** \arg RtcAlarmDayEn Day comparison enable of RTC alarm + ** \arg RtcAlarmHourEn Hour comparison enable of RTC alarm + ** \arg RtcAlarmMinEn Minute comparison enable of RTC alarm + ** + ** \retval Ok RTC functions enabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - Invalid value of enFunc + ** + ******************************************************************************/ +en_result_t Rtc_EnableFunc(volatile stc_rtcn_t* pstcRtc, en_rtc_func_t enFunc) +{ + // Check parameter + if(NULL == pstcRtc) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + // Recall data from VBAT domain to RTC clock registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PREAD)) + { + return ErrorTimeout; + } + + switch (enFunc) + { + case RtcCount: + pstcRtc->WTCR10_f.ST = 1u; + break; + case RtcTimer: + pstcRtc->WTCR21_f.TMST = 1u; + break; + case RtcFreqCorr: + pstcRtc->WTCALEN_f.WTCALEN = 1u; + break; + case RtcAlarmYearEn: + pstcRtc->WTCR11_f.YEN = 1u; + break; + case RtcAlarmMonthEn: + pstcRtc->WTCR11_f.MOEN = 1u; + break; + case RtcAlarmDayEn: + pstcRtc->WTCR11_f.DEN = 1u; + break; + case RtcAlarmHourEn: + pstcRtc->WTCR11_f.HEN = 1u; + break; + case RtcAlarmMinEn: + pstcRtc->WTCR11_f.MIEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + + // Save RTC clock registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PWRITE)) + { + return ErrorTimeout; + } + +#else + + switch (enFunc) + { + case RtcCount: + pstcRtc->WTCR1_f.ST = 1u; + break; + case RtcTimer: + pstcRtc->WTCR2_f.TMST = 1u; + break; + case RtcFreqCorr: + pstcRtc->WTCALEN_f.WTCALEN = 1u; + break; + case RtcAlarmYearEn: + pstcRtc->WTCR1_f.YEN = 1u; + break; + case RtcAlarmMonthEn: + pstcRtc->WTCR1_f.MOEN = 1u; + break; + case RtcAlarmDayEn: + pstcRtc->WTCR1_f.DEN = 1u; + break; + case RtcAlarmHourEn: + pstcRtc->WTCR1_f.HEN = 1u; + break; + case RtcAlarmMinEn: + pstcRtc->WTCR1_f.MIEN = 1u; + break; + default: + return ErrorInvalidParameter; + } + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable functions of RTC + ** + ** These functions includes RTC counting, Timer, Alarm compariron and frequency + ** correction module. + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param enFunc Function types + ** \arg RtcCount RTC counting + ** \arg RtcTimer RTC timer + ** \arg RtcFreqCorr RTC frequency correction module + ** \arg RtcAlarmYearEn Year comparison enable of RTC alarm + ** \arg RtcAlarmMonthEn Month comparison enable of RTC alarm + ** \arg RtcAlarmDayEn Day comparison enable of RTC alarm + ** \arg RtcAlarmHourEn Hour comparison enable of RTC alarm + ** \arg RtcAlarmMinEn Minute comparison enable of RTC alarm + ** + ** \retval Ok RTC functions disabled normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - Invalid value of enFunc + ** + ******************************************************************************/ +en_result_t Rtc_DisableFunc(volatile stc_rtcn_t* pstcRtc, en_rtc_func_t enFunc) +{ + // Check parameter + if(NULL == pstcRtc) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + switch (enFunc) + { + case RtcCount: + pstcRtc->WTCR10_f.ST = 0u; + break; + case RtcTimer: + pstcRtc->WTCR21_f.TMST = 0u; + break; + case RtcFreqCorr: + pstcRtc->WTCALEN_f.WTCALEN = 0u; + break; + case RtcAlarmYearEn: + pstcRtc->WTCR11_f.YEN = 0u; + break; + case RtcAlarmMonthEn: + pstcRtc->WTCR11_f.MOEN = 0u; + break; + case RtcAlarmDayEn: + pstcRtc->WTCR11_f.DEN = 0u; + break; + case RtcAlarmHourEn: + pstcRtc->WTCR11_f.HEN = 0u; + break; + case RtcAlarmMinEn: + pstcRtc->WTCR11_f.MIEN = 0u; + break; + default: + return ErrorInvalidParameter; + } + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } +#else + switch (enFunc) + { + case RtcCount: + pstcRtc->WTCR1_f.ST = 0u; + break; + case RtcTimer: + pstcRtc->WTCR2_f.TMST = 0u; + break; + case RtcFreqCorr: + pstcRtc->WTCALEN_f.WTCALEN = 0u; + break; + case RtcAlarmYearEn: + pstcRtc->WTCR1_f.YEN = 0u; + break; + case RtcAlarmMonthEn: + pstcRtc->WTCR1_f.MOEN = 0u; + break; + case RtcAlarmDayEn: + pstcRtc->WTCR1_f.DEN = 0u; + break; + case RtcAlarmHourEn: + pstcRtc->WTCR1_f.HEN = 0u; + break; + case RtcAlarmMinEn: + pstcRtc->WTCR1_f.MIEN = 0u; + break; + default: + return ErrorInvalidParameter; + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get RTC interrupt flag according to interrupt type + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] enIrqSel RTC interrupt type + ** \arg RtcRewriteError RTC rewrite error interrupt flag + ** \arg RtcAlarmIrq RTC alarm interrupt flag + ** \arg RtcTimerUnderFlow RTC Timer underflow interrupt flag + ** \arg RtcOneHourFlag 1-hour count-up interrupt flag + ** \arg RtcOneMiniteFlag 1-Minute count-up interrupt flag + ** \arg RtcOneSecondFlag 1-second count-up interrupt flag + ** \arg RtcHalfSecondFlag 0.5-second count-up interrupt flag + ** + ** \retval FALSE If one of following conditions are met: + ** - No RTC rewrite error [enStatus = RtcRewriteError] + ** - No element of alarm matchs [enStatus = RtcAlarmElementMatch] + ** - RTC timer underflow doesn't occurs [enStatus = RtcTimerUnderFlow] + ** - 1-hour count-up flag is not set [enStatus = RtcOneHourFlag] + ** - 1-minute count-up flag is not set [enStatus = RtcOneMiniteFlag] + ** - 1-second count-up flag is not set [enStatus = RtcOneSecondFlag] + ** - 0.5-second count-up flag is not set [enStatus = RtcHalfSecondFlag] + ** - RTC is running [enStatus = RtcRunStatus] + ** - RTC timer is running [enStatus = RtcTimerStatus] + ** \retval TRUE If one of following conditions are met: + ** - RTC rewrite error occurs [enStatus = RtcRewriteError] + ** - One of an element of alarm matchs [enStatus = RtcAlarmElementMatch] + ** - RTC timer underflow doesn't occurs [enStatus = RtcTimerUnderFlow] + ** - 1-hour count-up flag is set [enStatus = RtcOneHourFlag] + ** - 1-minute count-up flag is set [enStatus = RtcOneMiniteFlag] + ** - 1-second count-up flag is set [enStatus = RtcOneSecondFlag] + ** - 0.5-second count-up flag is set [enStatus = RtcHalfSecondFlag] + ** + ******************************************************************************/ +boolean_t Rtc_GetIrqFlag(volatile stc_rtcn_t* pstcRtc, en_rtc_irq_sel_t enIrqSel) +{ + boolean_t bRet = FALSE; + + /* Check parameter */ + if (NULL == pstcRtc) + { + return FALSE; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return FALSE; + } + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + (pstcRtc->WTCR12_f.INTSSI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcOneSecondIrq: + (pstcRtc->WTCR12_f.INTSI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcOneMinuteIrq: + (pstcRtc->WTCR12_f.INTMI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcOneHourIrq: + (pstcRtc->WTCR12_f.INTHI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcTimerIrq: + (pstcRtc->WTCR12_f.INTTMI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcAlarmIrq: + (pstcRtc->WTCR12_f.INTALI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcTimeRewriteErrorIrq: + (pstcRtc->WTCR12_f.INTERI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + default: + break; + } +#else + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + (pstcRtc->WTCR1_f.INTSSI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcOneSecondIrq: + (pstcRtc->WTCR1_f.INTSI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcOneMinuteIrq: + (pstcRtc->WTCR1_f.INTMI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcOneHourIrq: + (pstcRtc->WTCR1_f.INTHI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcTimerIrq: + (pstcRtc->WTCR1_f.INTTMI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcAlarmIrq: + (pstcRtc->WTCR1_f.INTALI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcTimeRewriteErrorIrq: + (pstcRtc->WTCR1_f.INTERI == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + default: + break; + } + +#endif + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear RTC interrupt flag according to interrupt type + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] enIrqSel RTC interrupt type + ** \arg RtcRewriteError RTC rewrite error interrupt flag + ** \arg RtcAlarmIrq RTC alarm interrupt flag + ** \arg RtcTimerUnderFlow RTC Timer underflow interrupt flag + ** \arg RtcOneHourFlag 1-hour count-up interrupt flag + ** \arg RtcOneMiniteFlag 1-Minute count-up interrupt flag + ** \arg RtcOneSecondFlag 1-second count-up interrupt flag + ** \arg RtcHalfSecondFlag 0.5-second count-up interrupt flag + ** + ** \retval Ok RTC interrupt flag is cleared normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - Invalid value of enStatus + ** + ******************************************************************************/ +en_result_t Rtc_ClrIrqFlag(volatile stc_rtcn_t* pstcRtc, en_rtc_irq_sel_t enIrqSel) +{ + if (NULL == pstcRtc) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + pstcRtc->WTCR12_f.INTSSI = 0u; + break; + case RtcOneSecondIrq: + pstcRtc->WTCR12_f.INTSI = 0u; + break; + case RtcOneMinuteIrq: + pstcRtc->WTCR12_f.INTMI = 0u; + break; + case RtcOneHourIrq: + pstcRtc->WTCR12_f.INTHI = 0u; + break; + case RtcTimerIrq: + pstcRtc->WTCR12_f.INTTMI = 0u; + break; + case RtcAlarmIrq: + pstcRtc->WTCR12_f.INTALI = 0u; + break; + case RtcTimeRewriteErrorIrq: + pstcRtc->WTCR12_f.INTERI = 0u; + break; + default: + return ErrorInvalidParameter; + } + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + +#else + + switch (enIrqSel) + { + case RtcHalfSecondIrq: + pstcRtc->WTCR1_f.INTSSI = 0u; + break; + case RtcOneSecondIrq: + pstcRtc->WTCR1_f.INTSI = 0u; + break; + case RtcOneMinuteIrq: + pstcRtc->WTCR1_f.INTMI = 0u; + break; + case RtcOneHourIrq: + pstcRtc->WTCR1_f.INTHI = 0u; + break; + case RtcTimerIrq: + pstcRtc->WTCR1_f.INTTMI = 0u; + break; + case RtcAlarmIrq: + pstcRtc->WTCR1_f.INTALI = 0u; + break; + case RtcTimeRewriteErrorIrq: + pstcRtc->WTCR1_f.INTERI = 0u; + break; + default: + return ErrorInvalidParameter; + } + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get status of RTC according to status type + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] enStatus RTC status + ** \arg RtcRunStatus RTC counter run status + ** \arg RtcTimerStatus RTC timer status + ** + ** \retval FALSE If one of following conditions are met: + ** - RTC is running [enStatus = RtcRunStatus] + ** - RTC timer is running [enStatus = RtcTimerStatus] + ** \retval TRUE If one of following conditions are met: + ** - RTC counter stops [enStatus = RtcRunStatus] + ** - RTC timer stops [enStatus = RtcTimerStatus] + ** + ******************************************************************************/ +boolean_t Rtc_GetStatus(volatile stc_rtcn_t* pstcRtc, en_rtc_status_t enStatus) +{ + boolean_t bRet = FALSE; + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + switch(enStatus) + { + case RtcRunStatus: + (pstcRtc->WTCR10_f.RUN == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcTimerStatus: + (pstcRtc->WTCR21_f.TMRUN == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + default: + break; + } +#else + switch(enStatus) + { + case RtcRunStatus: + (pstcRtc->WTCR1_f.RUN == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + case RtcTimerStatus: + (pstcRtc->WTCR2_f.TMRUN == 1u) ? (bRet = TRUE) : (bRet = FALSE); + break; + default: + break; + } +#endif + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Reset RTC + ** + ** \param [in] pstcRtc Pointer to RTC instance + ******************************************************************************/ +en_result_t Rtc_Reset(volatile stc_rtcn_t* pstcRtc) +{ +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + pstcRtc->WTCR10_f.SRST = 1; + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } +#else + + pstcRtc->WTCR1_f.SRST = 1; + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set time and date after RTC is running + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] pstcTimeDate Time and date structure + ** \param [in] bContinue RTC counting continues or not + ** \arg FALSE RTC 1-second counting reset during setting procedure + ** \arg TRUE RTC 1-second continues during setting procedure + ** \param [in] bUpdateTime Update time or not + ** \arg FALSE Don't update time + ** \arg TRUE Update time + ** \param [in] bUpdateDate Update date or not + ** \arg FALSE Don't update date + ** \arg TRUE Update date + ** + ** \retval Ok RTC time and date is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcTimeDate == NULL + ** \retval ErrorInvalidMode RTC is running + ** \retval ErrorTimeout RTC rewrite timeout + ** + ******************************************************************************/ +en_result_t Rtc_SetDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_time_t* pstcTimeDate, + boolean_t bContinue, + boolean_t bUpdateTime, + boolean_t bUpdateDate) +{ +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + uint32_t u32TimeOut; + stc_rtc_wtcr13_field_t stcWtcr13; + + if((NULL == pstcTimeDate) || (NULL == pstcRtc)) + { + return ErrorInvalidParameter; + } + + + // Recall data from VBAT domain to RTC count registers (load WTCR10) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + + /* Don't set time and date with this function before RTC starts */ + if(0u == pstcRtc->WTCR10_f.RUN) + { + return ErrorInvalidMode; + } + + if(1u == pstcRtc->WTCR10_f.BUSY) + { + /* Wait until rewrite idle */ + u32TimeOut = RTC_TIMEOUT; + while(1) + { + if(TRUE == bContinue) + { + if((0u == pstcRtc->WTCR10_f.BUSY) && (0u == pstcRtc->WTCR10_f.SCST)) + { + break; + } + } + else + { + if((0u == pstcRtc->WTCR10_f.BUSY) && (0u == pstcRtc->WTCR10_f.SCRST)) + { + break; + } + } + u32TimeOut--; + if(0u == u32TimeOut) + { + return ErrorTimeout; + } + + + // Recall data from VBAT domain to RTC count registers (load WTCR10) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + } + } + + /* Backup Interrupt Settings */ + stcWtcr13 = pstcRtc->WTCR13_f; + + /* Disable RTC NVIC */ + RtcDisableNvic(); + + /* Disable interrupt */ + pstcRtc->WTCR13 = 0u; + + /* Clear every second interrupt */ + pstcRtc->WTCR12_f.INTSI = 0u; + + /* Enable every second interrupt */ + pstcRtc->WTCR13_f.INTSIE = 1u; + + + // Save RTC count registers to VBAT domain (Write WTCR10, WTCR13) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + + + /* Wait to occur interrupt */ + while (1u != pstcRtc->WTCR12_f.INTSI) + { + // Recall data from VBAT domain to RTC count registers (load WTCR12) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + } + + /* Clear every second interrupt */ + pstcRtc->WTCR12_f.INTSI = 0u; + + if(TRUE == bContinue) + { + /* Stop 1 second output */ + pstcRtc->WTCR10_f.SCST = 1u; + } + else + { + /* Reset 1 second counter */ + pstcRtc->WTCR10_f.SCRST = 1u; + } + + /* Set time and date */ + if (TRUE == bUpdateTime) + { + pstcRtc->WTSR = DecToBcd(pstcTimeDate->u8Second); + pstcRtc->WTMIR = DecToBcd(pstcTimeDate->u8Minute); + pstcRtc->WTHR = DecToBcd(pstcTimeDate->u8Hour); + } + + if (TRUE == bUpdateDate) + { + pstcRtc->WTDR = DecToBcd(pstcTimeDate->u8Day); + pstcRtc->WTMOR = DecToBcd(pstcTimeDate->u8Month); + pstcRtc->WTYR = DecToBcd(pstcTimeDate->u16Year - 2000u); + pstcRtc->WTDW = DecToBcd(pstcTimeDate->u8DayOfWeek); + } + + // Save RTC count registers to VBAT domain (Write time registes, WTCR10, WTCR12) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + + if(TRUE == bContinue) + { + /* Refresh the time and date */ + pstcRtc->WTCR10_f.SCST = 0u; + } + else + { + /* Refresh the time and date */ + pstcRtc->WTCR10_f.SCRST = 0u; + } + + /* Retrieve Interrupt Settings */ + pstcRtc->WTCR13_f = stcWtcr13; + + // Save RTC count registers to VBAT domain (Write WTCR10, WTCR13) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } + + /* Retrieve NVIC */ + RtcRestoreNvic(); + + /* Wait until the transfer from time and date registers to counters end */ + u32TimeOut = RTC_TIMEOUT; + while(1) + { + if(TRUE == bContinue) + { + if((0u == pstcRtc->WTCR10_f.BUSY) && (0u == pstcRtc->WTCR10_f.SCST)) + { + break; + } + } + else + { + if((0u == pstcRtc->WTCR10_f.BUSY) && (0u == pstcRtc->WTCR10_f.SCRST)) + { + break; + } + } + u32TimeOut--; + if(0u == u32TimeOut) + { + return ErrorTimeout; + } + + + // Recall data from VBAT domain to RTC count registers (Load WTCR10) + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + } + +#else + + uint32_t u32TimeOut; + uint8_t u8Wtcr1HH; + + if((NULL == pstcTimeDate) || (NULL == pstcRtc)) + { + return ErrorInvalidParameter; + } + + /* Don't set time and date with this function before RTC starts */ + if(0u == pstcRtc->WTCR1_f.RUN) + { + return ErrorInvalidMode; + } + + if(1u == pstcRtc->WTCR1_f.BUSY) + { + /* Wait until rewrite idle */ + u32TimeOut = RTC_TIMEOUT; + while(1) + { + if(TRUE == bContinue) + { + if((0u == pstcRtc->WTCR1_f.BUSY) && (0u == pstcRtc->WTCR1_f.SCST)) + { + break; + } + } + else + { + if((0u == pstcRtc->WTCR1_f.BUSY) && (0u == pstcRtc->WTCR1_f.SCRST)) + { + break; + } + } + u32TimeOut--; + if(0u == u32TimeOut) + { + return ErrorTimeout; + } + } + } + + /* Backup Interrupt Settings */ + u8Wtcr1HH = pstcRtc->WTCR1HH; + + /* Disable RTC NVIC */ + RtcDisableNvic(); + + /* Disable interrupt */ + pstcRtc->WTCR1HH = 0u; + + /* Clear every second interrupt */ + pstcRtc->WTCR1_f.INTSI = 0u; + + /* Enable every second interrupt */ + pstcRtc->WTCR1_f.INTSIE = 1u; + + + /* Wait to occur interrupt */ + while (1u != pstcRtc->WTCR1_f.INTSI) + { + } + + /* Clear every second interrupt */ + pstcRtc->WTCR1_f.INTSI = 0u; + + if(TRUE == bContinue) + { + /* Stop 1 second output */ + pstcRtc->WTCR1_f.SCST = 1u; + } + else + { + /* Reset 1 second counter */ + pstcRtc->WTCR1_f.SCRST = 1u; + } + + /* Set time and date */ + if (TRUE == bUpdateTime) + { + pstcRtc->WTSR = DecToBcd(pstcTimeDate->u8Second); + pstcRtc->WTMIR = DecToBcd(pstcTimeDate->u8Minute); + pstcRtc->WTHR = DecToBcd(pstcTimeDate->u8Hour); + } + + if (TRUE == bUpdateDate) + { + pstcRtc->WTDR = DecToBcd(pstcTimeDate->u8Day); + pstcRtc->WTMOR = DecToBcd(pstcTimeDate->u8Month); + pstcRtc->WTYR = DecToBcd(pstcTimeDate->u16Year - 2000u); + pstcRtc->WTDW = DecToBcd(pstcTimeDate->u8DayOfWeek); + } + + if(TRUE == bContinue) + { + /* Refresh the time and date */ + pstcRtc->WTCR1_f.SCST = 0u; + } + else + { + /* Refresh the time and date */ + pstcRtc->WTCR1_f.SCRST = 0u; + } + + /* Retrieve Interrupt Settings */ + pstcRtc->WTCR1HH = u8Wtcr1HH; + + /* Retrieve NVIC */ + RtcRestoreNvic(); + + /* Wait until the transfer from time and date registers to counters end */ + u32TimeOut = RTC_TIMEOUT; + while(1) + { + if(TRUE == bContinue) + { + if((0u == pstcRtc->WTCR1_f.BUSY) && (0u == pstcRtc->WTCR1_f.SCST)) + { + break; + } + } + else + { + if((0u == pstcRtc->WTCR1_f.BUSY) && (0u == pstcRtc->WTCR1_f.SCRST)) + { + break; + } + } + u32TimeOut--; + if(0u == u32TimeOut) + { + return ErrorTimeout; + } + } + +#endif + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read RTC time and date + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] pstcTimeDate Time and date structure + ** + ** \retval Ok RTC time and date is read normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcTimeDate == NULL + ** \retval ErrorTimeout Time and date read timeout + ** + ******************************************************************************/ +en_result_t Rtc_ReadDateTime(volatile stc_rtcn_t* pstcRtc, stc_rtc_time_t* pstcTimeDate) +{ +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + uint8_t u8DayOfWeek, u8BcdSec, u8BcdMin, u8BcdHour, u8Day, u8Month, u16Year = 0u; + + if(pstcTimeDate == NULL) + { + return ErrorInvalidParameter; + } + + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } +#else + + uint32_t u32TimeOut; + uint8_t u8DayOfWeek, u8BcdSec, u8BcdMin, u8BcdHour, u8Day, u8Month, u16Year = 0u; + + if(pstcTimeDate == NULL) + { + return ErrorInvalidParameter; + } + /* Start read */ + pstcRtc->WTCR2_f.CREAD = 1u; + + /* Wait until read finish */ + u32TimeOut = RTC_TIMEOUT; + while(1) + { + if(0u == FM_RTC->WTCR2_f.CREAD) + { + break; + } + u32TimeOut --; + if(0u == u32TimeOut) + { + RtcRestoreNvic(); + return ErrorTimeout; + } + + } + +#endif + + /* Read time and date */ + u8BcdSec = pstcRtc->WTSR; + u8BcdMin = pstcRtc->WTMIR; + u8BcdHour = pstcRtc->WTHR; + u8Day = pstcRtc->WTDR; + u8Month = pstcRtc->WTMOR; + u16Year = pstcRtc->WTYR; + u8DayOfWeek = pstcRtc->WTDW; + + pstcTimeDate->u8Second = BcdToDec(u8BcdSec); + pstcTimeDate->u8Minute = BcdToDec(u8BcdMin); + pstcTimeDate->u8Hour = BcdToDec(u8BcdHour); + pstcTimeDate->u8Day = BcdToDec(u8Day); + pstcTimeDate->u8Month = BcdToDec(u8Month); + pstcTimeDate->u16Year = BcdToDec(u16Year) + 2000u; + pstcTimeDate->u8DayOfWeek = BcdToDec(u8DayOfWeek); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set time and date information of Alarm + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] pstcAlarm Time and date structure + ** \param [in] bUpdateAlarmTime Update alarm time or not + ** \param [in] bUpdateAlarmDate Update alarm date or not + + ** \retval Ok RTC Alarm time and date is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcAlarm == NULL + ** + ******************************************************************************/ +en_result_t Rtc_SetAlarmDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_alarm_t* pstcAlarm, + boolean_t bUpdateAlarmTime, + boolean_t bUpdateAlarmDate) +{ + if(NULL == pstcAlarm) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } +#endif + + pstcRtc->ALMIR = DecToBcd(pstcAlarm->u8Minute); + pstcRtc->ALHR = DecToBcd(pstcAlarm->u8Hour); + pstcRtc->ALDR = DecToBcd(pstcAlarm->u8Day); + pstcRtc->ALMOR = DecToBcd(pstcAlarm->u8Month); + pstcRtc->ALYR = DecToBcd(pstcAlarm->u16Year - 2000u); + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get time and date information of Alarm + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] pstcAlarm Time and date structure + ** \retval Ok RTC Alarm time and date is read normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcAlarm == NULL + ** + ******************************************************************************/ +en_result_t Rtc_GetAlarmDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_alarm_t* pstcAlarm) +{ + uint8_t u8BcdMin, u8BcdHour, u8Day, u8Month, u8Year; + if(NULL == pstcAlarm) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } +#endif + + u8BcdMin = pstcRtc->ALMIR; + u8BcdHour = pstcRtc->ALHR; + u8Day = pstcRtc->ALDR; + u8Month = pstcRtc->ALMOR; + u8Year = pstcRtc->ALYR; + + pstcAlarm->u8Minute = BcdToDec(u8BcdMin); + pstcAlarm->u8Hour = BcdToDec(u8BcdHour); + pstcAlarm->u8Day = BcdToDec(u8Day); + pstcAlarm->u8Month = BcdToDec(u8Month); + pstcAlarm->u16Year = BcdToDec(u8Year) + 2000u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set Day of the Week + ** + ** This function calculates the day of the week from YY-MM-DD in the Time + ** structure. It uses mktime of time.h library. + ** + ** \param [in,out] pstcRtcTime RTC Time structure + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter pstcRtcTime == NULL or mktime failed + ** + ******************************************************************************/ +en_result_t Rtc_SetDayOfWeek(stc_rtc_time_t* pstcRtcTime) +{ + en_result_t enResult; + struct tm stcTime; + + enResult = ErrorInvalidParameter; + + /* Check for NULL pointer */ + if (NULL != pstcRtcTime) + { + enResult = Ok; + /* Convert RTC time structure to time.h tm structure */ + RtcToTm(pstcRtcTime, &stcTime); + + /* Calculated raw time (UNIX time) is error */ + if ((time_t)RTC_ERR == mktime(&stcTime)) + { + enResult = ErrorInvalidParameter; + } + + if (Ok == enResult) + { + /* Set calculated the day of week */ + pstcRtcTime->u8DayOfWeek = (uint8_t)(stcTime.tm_wday); + } + } + + return (enResult); +} /* Rtc_SetDayOfWeek */ + +/** + ****************************************************************************** + ** \brief Set cycle of RTC timer + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] u32TimerCycle Timer cycle + ** \retval Ok RTC timer cycle is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u32TimerCycle > RTC_MAX_TIMER_SET_VALUE + ** + ** \note The unit of parameter u32TimerCycle is second. + ** + ******************************************************************************/ +en_result_t Rtc_SetTimerCycle(volatile stc_rtcn_t* pstcRtc, uint32_t u32TimerCycle) +{ + uint32_t u32Count; + + if(u32TimerCycle > RTC_MAX_TIMER_SET_VALUE) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CREAD)) + { + return ErrorTimeout; + } + + u32Count = (u32TimerCycle*2) - 1u; + + pstcRtc->WTTR0 = (uint8_t)u32Count; + pstcRtc->WTTR1 = (uint8_t)(u32Count >> 8u); + pstcRtc->WTTR2 = (uint8_t)(u32Count >> 16u); + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_CWRITE)) + { + return ErrorTimeout; + } +#else + + u32Count = (u32TimerCycle*2) - 1u; + + pstcRtc->WTTR = (uint8_t)u32Count; + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set calibration value of RTC frequency correction module + ** + ** \param [in] pstcRtc Pointer to RTC instance + ** \param [in] u16Value Calibration value + ** \retval Ok RTC timer cycle is set normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - u32TimerCycle > RTC_MAX_FREQ_CORR_VALUE + ** + ******************************************************************************/ +en_result_t Rtc_SetFreqCorrValue(volatile stc_rtcn_t* pstcRtc, uint16_t u16Value) +{ + if(u16Value > RTC_MAX_FREQ_CORR_VALUE) + { + return ErrorInvalidParameter; + } + +#if (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_VBAT_TYPEB) + // Recall data from VBAT domain to RTC count registers + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PREAD)) + { + return ErrorTimeout; + } + + pstcRtc->WTCAL0 = (uint8_t)u16Value; + pstcRtc->WTCAL1 = (uint8_t)(u16Value >> 8u); + + // Save RTC count registers to VBAT domain + if(Ok != RtcTransWithVbat(pstcRtc, RTC_WTCR20_PWRITE)) + { + return ErrorTimeout; + } + +#else + + #if (PDL_RTC_TYPE != PDL_RTC_WITHOUT_VBAT_TYPEA) + pstcRtc->WTCAL = (uint8_t)u16Value; + #else + pstcRtc->WTCAL = u16Value; + #endif + +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get raw time + ** + ** This function calculates the "raw" time ('UNIX time'). + ** + ** \param [in] pstcRtcTime Pointer to RTC Time structure + ** + ** \return Calculated time or '-1' on error + ** + ******************************************************************************/ +time_t Rtc_GetRawTime(stc_rtc_time_t* pstcRtcTime) +{ + time_t uiTime; + struct tm stcTime; + + /* Check for NULL pointer */ + if (NULL == pstcRtcTime) + { + uiTime = (time_t)RTC_ERR; + } + else + { + /* Convert RTC time structure to time.h tm structure */ + RtcToTm(pstcRtcTime, &stcTime); + uiTime = mktime(&stcTime); + } + + /* Return raw time (UNIX time) */ + return (uiTime); +} /* Rtc_GetRawTime */ + +/** + ****************************************************************************** + ** \brief Sets the RTC time structure from raw time + ** + ** This function calculates from the RTC time structure "raw" time + ** ('UNIX time'). + ** + ** \param [out] pstcRtcTime RTC Time structure + ** \param [in] tRawTime "Raw" time + ** + ** \retval Ok Internal data has been setup + ** \retval ErrorInvalidParameter pstcRtcTime == NULL or localtime failed + ** + ******************************************************************************/ +en_result_t Rtc_SetLocalTime(stc_rtc_time_t* pstcRtcTime, + time_t tRawTime) +{ + en_result_t enResult; + struct tm* pstcTime; + + enResult = ErrorInvalidParameter; + + /* Check for NULL pointer */ + if (NULL != pstcRtcTime) + { + /* Get the pointer which converted to RTC time structure from raw time */ + pstcTime = localtime((const time_t*) &tRawTime); + + /* Un-success */ + if (NULL == pstcTime) + { + enResult = ErrorInvalidParameter; + } + else + { + pstcRtcTime->u16Year = (uint16_t)(pstcTime->tm_year + 1900u); + pstcRtcTime->u8Month = (uint8_t)(pstcTime->tm_mon + 1u); + pstcRtcTime->u8Day = (uint8_t)(pstcTime->tm_mday); + pstcRtcTime->u8Second = (uint8_t)(pstcTime->tm_sec); + pstcRtcTime->u8Minute = (uint8_t)(pstcTime->tm_min); + pstcRtcTime->u8Hour = (uint8_t)(pstcTime->tm_hour); + pstcRtcTime->u8DayOfWeek = (uint8_t)(pstcTime->tm_wday); + enResult = Ok; + } + } + + return (enResult); +} /* Rtc_SetTime */ + +#endif /* #if (defined(PDL_PERIPHERAL_RTC_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.h new file mode 100644 index 0000000000..1a84f25860 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/rtc/rtc.h @@ -0,0 +1,580 @@ +/******************************************************************************* +* \file rtc.h +* +* \version 1.20 +* +* \brief Headerfile for RTC functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __RTC_H__ +#define __RTC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" +#include "time.h" + +#if (defined(PDL_PERIPHERAL_RTC_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupRTC Real Time Clock (RTC) +* \{ +* \defgroup GroupRTC_Macros Macros +* \defgroup GroupRTC_Functions Functions +* \defgroup GroupRTC_GlobalVariables Global Variables +* \defgroup GroupRTC_DataStructures Data Structures +* \defgroup GroupRTC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupRTC +* \{ +* The Real-time Clock (RTC) peripheral generates interrupts based on calendar time +* or an elapsed number of seconds. The RTC counts years, months, days, hours, minutes, +* seconds, and days of the week from 00 to 99 years, starting at the year 2000. The RTC +* can generate an interrupt for every half second, second, minute, or hour that passes.
+* You can set an alarm for a specific year, month, day, hour, and minute. The RTC generates +* an interrupt when the specified date or time is reached.
+* You can set a timer with an interval as long as 0x2000 seconds (slightly more than +* 36 hours 24 minutes). The timer can be one-shot or repeating (periodical). The RTC +* generates an interrupt when the time expires. You can use a periodic timer to generate a +* repeating interrupt at the time interval you set.
+* The RTC handles leap years automatically. +* \section SectionRTC_ConfigurationConsideration Configuration Consideration +* You use these structures to configure the RTC:
+* - stc_rtc_config_t +* - stc_rtc_time_t +* - stc_rtc_irq_en_t +* - stc_rtc_irq_cb_t +* - stc_rtc_alarm_t +* - stc_rtc_timer_t +* +* The config structure requires pointers to the other structures. For the alarm and timer, +* a NULL value is acceptable and simply means there is no alarm or timer. You can set and +* enable alarms and timers independently, after the RTC is initialized.
+* To set the time structure, you specify the second, minute, hour, day, month, +* and year. With that data in place you can call Rtc_SetDayOfWeek() to set the weekday.
+* You enable selected interrupts in the irq_en structure. For those you enable, provide the +* address for each callback function in the irq_cb structure.
+* To set up the RTC, you provide configuration parameters in the stc_rtc_config_t structure +* and the other structures. Then call Rtc_Init() to initializes an RTC instance according to the +* configuration structure. Rtc_DeInit() de-initializes an RTC instance.
+* To start the RTC, call Rtc_EnableFunc() with the RtcCount flag. Use this function, or Rtc_DisableFunc() +* to enable or disable the timer, or particular alarms (for minute, hour, day, nonth, or year).
+* After you initialize the RTC you can enable or disable individual interrupts. You must have a +* handler for any enabled interrupt. If you need to add a handler, use Rtc_DeInit(), +* update the configuration structures, and call Rtc_Init() with the new configuration. +* You can get and clear interrupt flags as well.
+* You can change the alarm date and time with Rtc_SetAlarmDateTime(). You can change the timer interval +* with Rtc_SetTimerCycle().The time interval is measured in units of one second. The maximum value for +* the timer is 0x2000 (which is 36 hours, 24 minutes, 32 seconds). +* \section SectionRTC_MoreInfo More Information +* For more information on the RTC peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupRTC_Macros +* \{ +*/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_rtcn_t FM_RTC_TypeDef +#define RTC0 (*((volatile stc_rtcn_t *) FM_RTC_BASE)) + +#define RTC_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_RTC0 == PDL_ON) + +/******************************************************************************/ +/* Define RTC types */ +/******************************************************************************/ +#define PDL_RTC_WITHOUT_VBAT_TYPEA 0u ///< The type A of RTC without VBAT domain +#define PDL_RTC_WITHOUT_VBAT_TYPEB 1u ///< The type B of RTC without VBAT domain +#define PDL_RTC_VBAT_TYPEA 2u ///< The type A of RTC association with VBAT +#define PDL_RTC_VBAT_TYPEB 3u ///< The type B of RTC association with VBAT + +/** + ****************************************************************************** + ** \brief Extract RTC type according to a certain device + ******************************************************************************/ +#if !defined(FM_RTC_AVAILABLE) + #error "RTC is not supported by this device" +#else + // FM3 + #if (PDL_MCU_CORE == PDL_FM3_CORE) + #if defined FM3_RTC_TYPE_A + #define PDL_RTC_TYPE PDL_RTC_WITHOUT_VBAT_TYPEA + #elif defined FM3_RTC_TYPE_B + #define PDL_RTC_TYPE PDL_RTC_WITHOUT_VBAT_TYPEB + #else + #error "RTC Type not supported! Please update PDL" + #endif + + // FM0+ + #elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if defined FM0P_RTC_TYPE_A + #define PDL_RTC_TYPE PDL_RTC_WITHOUT_VBAT_TYPEB + #elif defined FM0P_RTC_TYPE_B + #define PDL_RTC_TYPE PDL_RTC_VBAT_TYPEB + #else + #error "RTC Type not supported! Please update PDL" + #endif + + // FM4 + #elif (PDL_MCU_CORE == PDL_FM4_CORE) // FM4 + #if defined FM4_RTC_TYPE_A + #define PDL_RTC_TYPE PDL_RTC_VBAT_TYPEA + #elif defined FM4_RTC_TYPE_B + #define PDL_RTC_TYPE PDL_RTC_VBAT_TYPEB + #elif defined FM4_RTC_TYPE_C + #define PDL_RTC_TYPE PDL_RTC_WITHOUT_VBAT_TYPEB + #else + #error "RTC Type not supported! Please update PDL" + #endif + #else + #error "Device core not found!" + #endif +#endif + +/** + ****************************************************************************** + ** \brief Maximum Frequency Correction Value + ******************************************************************************/ +#if (PDL_RTC_TYPE == PDL_RTC_WITHOUT_VBAT_TYPEA) +#define RTC_MAX_FREQ_CORR_VALUE (0x7Fu) +#else +#define RTC_MAX_FREQ_CORR_VALUE (0x3FFu) +#endif +/** + ****************************************************************************** + ** \brief Maximum Frequency Correction Cycle Setting Value + ******************************************************************************/ +#define RTC_MAX_FREQ_CORR_CYCLE_SET_VALUE (0x3Fu) + +/** + ****************************************************************************** + ** \brief Maxmimum Timer Setting Value [unit: second] + ******************************************************************************/ +#define RTC_MAX_TIMER_SET_VALUE (0x20000u) + +/** \} GroupRTC_Macros */ + +/** +* \addtogroup GroupRTC_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +#if (PDL_RTC_TYPE == PDL_RTC_WITHOUT_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_WITHOUT_VBAT_TYPEB) +/** + ****************************************************************************** + ** \brief Real Time Clock clock selection + ******************************************************************************/ +typedef enum en_rtc_clk_sel +{ + RtcUseSubClk = 0u, ///< Use sub clock as RTC source clock + RtcuseMainClk = 1u, ///< Use main clock as RTC source clock + +}en_rtc_clk_sel_t; +#endif + +/** + ****************************************************************************** + ** \brief RTCCO output selection + ** + ** If user needs to output RTCCO, RTCCO pin function should also be enabled in + ** in GPIO macro. + ******************************************************************************/ +typedef enum en_rtc_rtcco_sel +{ + RtccoOutput2Hz = 0u, ///< Output 2Hz signal at RTCCO pin + RtccoOutput1Hz = 1u, ///< Output 1Hz signal at RTCCO pin + +}en_rtc_rtcco_sel_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock functions + ******************************************************************************/ +typedef enum en_rtc_func +{ + RtcCount = 0u, ///< RTC counting + RtcTimer = 1u, ///< RTC timer + RtcFreqCorr = 2u, ///< RTC frequency correction module + RtcAlarmYearEn = 3u, ///< Year comparison enable of RTC alarm + RtcAlarmMonthEn = 4u, ///< Month comparison enable of RTC alarm + RtcAlarmDayEn = 5u, ///< D comparison enable of RTC alarm + RtcAlarmHourEn = 6u, ///< Hour comparison enable of RTC alarm + RtcAlarmMinEn = 7u, ///< Minute comparison enable of RTC alarm + +}en_rtc_func_t; + +/** + ****************************************************************************** + ** \brief Day of week name definitions + ******************************************************************************/ +typedef enum en_rtc_day_of_week +{ + RtcSunday = 0u, ///< Sunday + RtcMonday = 1u, ///< Monday + RtcTuesday = 2u, ///< Tuesday + RtcWednesday = 3u, ///< Wednesday + RtcThursday = 4u, ///< Thursday + RtcFriday = 5u, ///< Friday + RtcSaturday = 6u, ///< Saturday +} en_rtc_day_of_week_t; + +/** + ****************************************************************************** + ** \brief Month name definitions (not used in driver - to be used by + ** user appliciation) + ******************************************************************************/ +typedef enum en_rtc_month +{ + RtcJanuary = 1u, ///< January + RtcFebruary = 2u, ///< February + RtcMarch = 3u, ///< March + RtcApril = 4u, ///< April + RtcMay = 5u, ///< May + RtcJune = 6u, ///< June + RtcJuly = 7u, ///< July + RtcAugust = 8u, ///< August + RtcSeptember = 9u, ///< September + RtcOctober = 10u, ///< October + RtcNovember = 11u, ///< November + RtcDecember = 12u, ///< December +} en_rtc_month_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock timer mode selection + ******************************************************************************/ +typedef enum en_rtc_time_mode +{ + RtcTimerOneshot = 0u, ///< One-shot mode + RtcTimerPeriod = 1u, ///< Periodical mode + +}en_rtc_time_mode_t; + +/** + ****************************************************************************** + ** \brief Rtc Divider Ratio Setting + ** + ** Divider Ration Settings for WTC. The enumarted values do not correspond to + ** the bit patterns of WTDIV! + ******************************************************************************/ +typedef enum en_rtc_div_ratio +{ + RtcDivRatio1 = 0x00u, ///< RIN clock is not divided + RtcDivRatio2 = 0x01u, ///< RIN clock is divided by 2 + RtcDivRatio4 = 0x02u, ///< RIN clock is divided by 4 + RtcDivRatio8 = 0x03u, ///< RIN clock is divided by 8 + RtcDivRatio16 = 0x04u, ///< RIN clock is divided by 16 + RtcDivRatio32 = 0x05u, ///< RIN clock is divided by 32 + RtcDivRatio64 = 0x06u, ///< RIN clock is divided by 64 + RtcDivRatio128 = 0x07u, ///< RIN clock is divided by 128 + RtcDivRatio256 = 0x08u, ///< RIN clock is divided by 256 + RtcDivRatio512 = 0x09u, ///< RIN clock is divided by 512 + RtcDivRatio1024 = 0x0Au, ///< RIN clock is divided by 1024 + RtcDivRatio2048 = 0x0Bu, ///< RIN clock is divided by 2048 + RtcDivRatio4096 = 0x0Cu, ///< RIN clock is divided by 4096 + RtcDivRatio8192 = 0x0Du, ///< RIN clock is divided by 8192 + RtcDivRatio16384 = 0x0Eu, ///< RIN clock is divided by 16384 + RtcDivRatio32768 = 0x0Fu, ///< RIN clock is divided by 32768 +} en_rtc_div_ratio_t ; + +/** + ****************************************************************************** + ** \brief Interrupt selection enumeration + ******************************************************************************/ +typedef enum en_rtc_irq_sel +{ + RtcHalfSecondIrq = 0u, ///< 0.5-second count-up interrupt request + RtcOneSecondIrq = 1u, ///< 1-second count-up interrupt request + RtcOneMinuteIrq = 2u, ///< 1-Minute count-up interrupt request + RtcOneHourIrq = 3u, ///< 1-hour count-up interrupt request + RtcTimerIrq = 4u, ///< Timer underflow interrupt request + RtcAlarmIrq = 5u, ///< Alarm interrupt request + RtcTimeRewriteErrorIrq = 6u, ///< Rewrite error interrupt request + +} en_rtc_irq_sel_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock status types + ******************************************************************************/ +typedef enum en_rtc_status +{ + RtcRunStatus = 0u, ///< RTC counter run status + RtcTimerStatus = 1u, ///< RTC timer status + +}en_rtc_status_t; + +/// Enumeration to define an index for each enabled RTC instance +typedef enum en_rtc_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_RTC0 == PDL_ON) + RtcInstanceIndexRtc0, + #endif + RtcInstanceIndexMax +} en_rtc_instance_index_t; + +/** \} GroupRTC_Types */ + +/** +* \addtogroup GroupRTC_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief frequency correction configuration + ******************************************************************************/ +typedef struct stc_rtc_freq_corr +{ + uint16_t u16FreqCorrValue; ///< Frequency correction value +#if (PDL_RTC_TYPE != PDL_RTC_WITHOUT_VBAT_TYPEA) + uint16_t u16FreqCorrCycle; ///< Frequency correction cycle +#endif +}stc_rtc_freq_corr_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock timer configuration structure + ******************************************************************************/ +typedef struct stc_rtc_timer +{ + en_rtc_time_mode_t enMode; ///< Timer mode + uint32_t u32TimerCycle; ///< The cycle [uint: second] of timer, after these seconds elapse, timer interrpt will occur + +}stc_rtc_timer_t; + +/** + ****************************************************************************** + ** \brief Interrupt configuration structure + ******************************************************************************/ +typedef struct stc_rtc_irq_en +{ + boolean_t bHalfSecondIrq; ///< TRUE: 0.5-Second interrupt enabled + ///< FALSE: 0.5-Second interrupt disabled + boolean_t bOneSecondIrq; ///< TRUE: 1-Second interrupt enabled + ///< FALSE: 1-Second interrupt disabled + boolean_t bOneMinuteIrq; ///< TRUE: 1-Minute interrupt enabled + ///< FALSE: 1-Minute interrupt disabled + boolean_t bOneHourIrq; ///< TRUE: 1-Hour interrupt enabled + ///< FALSE: 1-Hour interrupt disabled + boolean_t bTimerIrq; ///< TRUE: Timer interrupt enabled + ///< FALSE: Timer interrupt disabled + boolean_t bAlarmIrq; ///< TRUE: Alarm interrupt enabled + ///< FALSE: Alarm interrupt disabled + boolean_t bTimeRewriteErrorIrq; ///< TRUE: Time Rewrite Error interrupt enabled + ///< FALSE: Time Rewrite Error interrupt disabled +} stc_rtc_irq_en_t; + +/** + ****************************************************************************** + ** \brief RTC callback functions structure + ******************************************************************************/ +typedef struct stc_rtc_irq_cb +{ + func_ptr_t pfnTimeWrtErrIrqCb; ///< Callback function pointer for Timer writing error Interrupt + func_ptr_t pfnAlarmIrqCb; ///< Callback function pointer for Alarm Interrupt + func_ptr_t pfnTimerIrqCb; ///< Callback function pointer for Timer Interrupt + func_ptr_t pfnHalfSecondIrqCb; ///< Callback function pointer for 0.5-Second Interrupt + func_ptr_t pfnOneSecondIrqCb; ///< Callback function pointer for One Second Interrupt + func_ptr_t pfnOneMinuteIrqCb; ///< Callback function pointer for One Minute Interrupt + func_ptr_t pfnOneHourIrqCb; ///< Callback function pointer for One Hour Interrupt + +}stc_rtc_intern_data_t, stc_rtc_irq_cb_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock Date and Time structure + ******************************************************************************/ +typedef struct stc_rtc_time +{ + uint8_t u8Second; ///< Second (Format 0...59) + uint8_t u8Minute; ///< Minutes (Format 0...59) + uint8_t u8Hour; ///< Hour (Format 0...23) + uint8_t u8Day; ///< Day (Format 1...31) + uint8_t u8DayOfWeek; ///< Day of the week (Format 0...6) + uint8_t u8Month; ///< Month (Format 1...12) + uint16_t u16Year; ///< Year (Format 1...99) + 2000 +} stc_rtc_time_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock Alarm structure + ******************************************************************************/ +typedef struct stc_rtc_alarm +{ + uint8_t u8Minute; ///< Alarm minutes (Format 1...59) + uint8_t u8Hour; ///< Alarm hour (Format 0...23) + uint8_t u8Day; ///< Alarm day (Format 1...31) + uint8_t u8Month; ///< Alarm month (Foramt 1...12) + uint16_t u16Year; ///< Alarm year (Format 1...99) + 2000 +} stc_rtc_alarm_t; + +/** + ****************************************************************************** + ** \brief Real Time Clock configuration + ** + ** The RTC configuration settings + ******************************************************************************/ +typedef struct stc_rtc_config +{ +#if (PDL_RTC_TYPE == PDL_RTC_WITHOUT_VBAT_TYPEA) || (PDL_RTC_TYPE == PDL_RTC_WITHOUT_VBAT_TYPEB) + en_rtc_clk_sel_t enClkSel; ///< TRUE: RTC clock selection + uint32_t u32ClkPrescaler; ///< RTC source clock prescaler +#endif + boolean_t bEnSuboutDivider; ///< TRUE: Enable Divider for Divider Ratio + ///< FALSE: Disable Divider for Divider Ratio + en_rtc_div_ratio_t enDividerRatio; ///< Divider ratio for SUBOUT + en_rtc_rtcco_sel_t enRtccoSel; ///< Divider of CO signal, see #en_rtc_rtcco_sel_t for details + + stc_rtc_freq_corr_t* pstcFreqCorrConfig; ///< Pointer to frequency correction configuration, if it is set to NULL, frequency correction function will not be initialized. + stc_rtc_time_t* pstcTimeDate; ///< Pointer to time configuration structure, if it is set to NULL, time and date will not be initialized. + stc_rtc_alarm_t* pstcAlarm; ///< Pointer to alarm configuration structure, if it is set to NULL, alarm will not be initialized. + stc_rtc_timer_t* pstcTimer; ///< Pointer to timer configuration structure, if it is set to NULL, timer will not be initialized. +#if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) + stc_rtc_irq_en_t* pstcIrqEn; ///< Pointer to interrupt enable structure, if it is set to NULL, no interrupts will not be enabled. + stc_rtc_irq_cb_t* pstcIrqCb; ///< Pointer to interrupt callback function structure, if it is set to NULL, no interrupt callback functions will not be set. + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif + boolean_t bRunNotInit; ///< TRUE: don't initialize RTC when RTC is running, FALSE: Initialize RTC any time + +} stc_rtc_config_t; + +/// RTC instance data type +typedef struct stc_rtc_instance_data +{ + volatile stc_rtcn_t* pstcInstance; ///< pointer to registers of an instance + stc_rtc_intern_data_t stcInternData; ///< module internal data of instance +} stc_rtc_instance_data_t; + +/** \} GroupRTC_DataStructures */ + +/** +* \addtogroup GroupRTC_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/// Look-up table for all enabled RTC instances and their internal data +extern stc_rtc_instance_data_t m_astcRtcInstanceDataLut[RTC_INSTANCE_COUNT]; + +/** \} GroupRTC_GlobalVariables */ + +/** +* \addtogroup GroupRTC_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_RTC0 == PDL_ON) +void Rtc_IrqHandler(volatile stc_rtcn_t* pstcRtc, stc_rtc_intern_data_t* pstcRtcInternData); +en_result_t Rtc_EnableIrq(volatile stc_rtcn_t* pstcRtc, + en_rtc_irq_sel_t enIrqSel); +en_result_t Rtc_DisableIrq(volatile stc_rtcn_t* pstcRtc, + en_rtc_irq_sel_t enIrqSel); +#endif + +/* Init/De-Init */ +en_result_t Rtc_Init(volatile stc_rtcn_t* pstcRtc, + const stc_rtc_config_t* pstcConfig); +en_result_t Rtc_DeInit(volatile stc_rtcn_t* pstcRtc, + boolean_t bTouchNvic); + +/* Function enable/disable */ +en_result_t Rtc_EnableFunc(volatile stc_rtcn_t* pstcRtc, en_rtc_func_t enFunc); +en_result_t Rtc_DisableFunc(volatile stc_rtcn_t* pstcRtc, en_rtc_func_t enFunc); + +/* Rtc Reset */ +en_result_t Rtc_Reset(volatile stc_rtcn_t* pstcRtc); + +/* Get/Clr RTC status */ +boolean_t Rtc_GetIrqFlag(volatile stc_rtcn_t* pstcRtc, en_rtc_irq_sel_t enIrqSel); +en_result_t Rtc_ClrIrqFlag(volatile stc_rtcn_t* pstcRtc, en_rtc_irq_sel_t enIrqSel); +boolean_t Rtc_GetStatus(volatile stc_rtcn_t* pstcRtc, en_rtc_status_t enStatus); + +/* Calendar/Alarm set/get */ +en_result_t Rtc_SetDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_time_t* pstcTimeDate, + boolean_t bContinue, + boolean_t bUpdateTime, + boolean_t bUpdateDate); +en_result_t Rtc_ReadDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_time_t* pstcTimeDate); +en_result_t Rtc_SetAlarmDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_alarm_t* pstcAlarm, + boolean_t bUpdateAlarmTime, + boolean_t bUpdateAlarmDate); +en_result_t Rtc_GetAlarmDateTime(volatile stc_rtcn_t* pstcRtc, + stc_rtc_alarm_t* pstcAlarm); + +/* Set timer cycle */ +en_result_t Rtc_SetTimerCycle(volatile stc_rtcn_t* pstcRtc, + uint32_t u32TimerCycle); + +/* Set frequency correction value */ +en_result_t Rtc_SetFreqCorrValue(volatile stc_rtcn_t* pstcRtc, + uint16_t u16Value); + +/* Set day of week */ +en_result_t Rtc_SetDayOfWeek(stc_rtc_time_t* pstcRtcTime); + +/* Get raw time from RTC time */ +time_t Rtc_GetRawTime(stc_rtc_time_t* pstcRtcTime); + +/* Set RTC time from raw time */ +en_result_t Rtc_SetLocalTime(stc_rtc_time_t* pstcRtcTime, + time_t tRawTime); + +/** \} GroupRTC_Functions */ +/** \} GroupRTC */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_RTC_ACTIVE)) */ + +#endif /* __RTC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/debug.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/debug.h new file mode 100644 index 0000000000..d7959f7ddd --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/debug.h @@ -0,0 +1,70 @@ +/*! + ****************************************************************************** + ** + ** \file debug.h + ** + ** \brief Debug definition + ** + ** \author FSLA AE Team + ** + ** \version V0.10 + ** + ** \date 2012-01-19 + ** + ** \attention THIS SAMPLE CODE IS PROVIDED AS IS. SPANSION LLC + ** ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR + ** OMMISSIONS. + ** + ** Copyright (C) 2013 Spansion LLC. All Rights Reserved. + ** + ****************************************************************************** + ** + ** \note Other information. + ** + ****************************************************************************** + */ + +#ifndef _DEBUG_H_ +#define _DEBUG_H_ + +/*---------------------------------------------------------------------------*/ +/* include files */ +/*---------------------------------------------------------------------------*/ +#include +/*---------------------------------------------------------------------------*/ +/* constants and macros */ +/*---------------------------------------------------------------------------*/ +/* Uncomment the line below to expanse the "ASSERT" macro in the + Standard Peripheral Library drivers code */ +#define DEBUG_MODE +#define DEBUGGING +#ifdef DEBUG_MODE + #define ASSERT(expr) \ + {do \ + { \ + if (!(expr)) \ + { \ + printf("FILE: %s\n", __FILE__); \ + printf("FUNC: %s\n", __FUNCTION__); \ + printf("LINE: %u\n\n", __LINE__); \ + } \ + }while(0);} +#else + #define ASSERT(expr) +#endif + + +/*---------------------------------------------------------------------------*/ +/* function prototypes */ +/*---------------------------------------------------------------------------*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _DEBUG_H_ */ +/*****************************************************************************/ +/* END OF FILE */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.c new file mode 100644 index 0000000000..e325f18d5f --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.c @@ -0,0 +1,973 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file sd.c + ** + ** + ** + ** History: + ** - 2013-04-16 1.0 QXu First version. + ** - 2013-07-24 1.1 RQian Modification. + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "sd.h" + +#if (defined(PDL_PERIPHERAL_SD_ACTIVE)) + +/** + ****************************************************************************** + ** \addtogroup SdifGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define SD_PCG 0x4003C120 +#define PCG_ENABLE (1UL<<8) +#define DELAYUNIT 5000 +#define WAITTIME 50000 +#define RETRYTIMES 100 + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +volatile stc_sd_config_t Sd_stcCfg; +stc_sd_comdconfig_t Sd_stcCmdCfg; +volatile stc_sd_t *Sd_stcCtrl = (volatile stc_sd_t *)FM4_SDIF_BASE; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Delay according to specified number + ** + ** \param [in] u32Delay Delay number + ** + ******************************************************************************/ +static void dly_1unit (uint32_t u32Delay) +{ + volatile uint32_t u32i; + + for(;u32Delay;--u32Delay) + { + for(u32i = DELAYUNIT;u32i;--u32i); + } +} + +/** + ****************************************************************************** + ** \brief Init the IO configuration for SDIF. + ** + ** SCLK :P0E + ** CMD :P0D + ** DATA1 :P0C + ** DATA0 :P0B + ** DATA3 :P0A + ** DATA2 :P09 (AN19) + ** CD :P63 + ** WP :P62 + ** + ******************************************************************************/ +static void SdInitPins(void) +{ + FM4_GPIO->ADE &= ~(uint32_t)(1<<19); ///< AN19 = 0 select none analog function + FM4_GPIO->PFR0 |= 0x7E00; ///< P09~P0E =1 + FM4_GPIO->PFR6 |= 0x000C; ///< P62~P63 =1 + +#if (BUSWIDTH == BIT4) + FM4_GPIO->PCR0 |= 0x1E00; ///< PCR of P09~P0C =1 ,pull up the 4 data lines + FM4_GPIO->PCR0 &= ~0x0400; // DATA3 pull down +#else + FM4_GPIO->PCR0 |= 0x0800; ///< PCR of P0B =1 ,pull up the DAT0 lines +#endif + + FM4_GPIO->EPFR18 |= 0x01554000; ///< enable peripheral function +} + +/** + ****************************************************************************** + ** \brief Enable SD I/F peripheral clock + ** + ******************************************************************************/ +static boolean_t SdEnablePCG(void) +{ + uint32_t u32psg = 0; + volatile uint32_t * p32Sdpcg = (uint32_t *)SD_PCG; + + *p32Sdpcg |= PCG_ENABLE; + u32psg = *p32Sdpcg; + if(PCG_ENABLE == (u32psg & PCG_ENABLE)) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ****************************************************************************** + ** \brief Disable SD I/F peripheral clock + ** + ******************************************************************************/ +static void SdDisablePCG(void) +{ + *((uint32_t *)SD_PCG) &= ~(1<<8); +} + +/** + ****************************************************************************** + ** \brief Initial the SDIF internal data + ** + ** \param [in] pstcSdCfg Pointer of SDIF configuration data + ** \param [in] pstcCmdCfg Pointer of SDIF command configuration data + ** + ******************************************************************************/ +static void SdInitHostInternalData(volatile stc_sd_config_t *pstcSdCfg,stc_sd_comdconfig_t *pstcCmdCfg) +{ +#if (BUSWIDTH == BIT4 ) + pstcSdCfg->enBusWidth = BIT_4; +#else + pstcSdCfg->enBusWidth = BIT_1; +#endif + pstcSdCfg->enExist = REMOVAL; + pstcSdCfg->bCmdComplete = FALSE; + pstcSdCfg->bSendComplete = FALSE; + pstcSdCfg->bDMAComplete = FALSE; + pstcSdCfg->pfnErrorCallback = NULL; + pstcSdCfg->pfnRxCallback = NULL; + pstcSdCfg->pfnTxCallback = NULL; + pstcSdCfg->pfnWakeupCallback = NULL; + + pstcCmdCfg->enResponse = NO_RSP; + //pstcCmdCfg->enReadWrite = SD_READ; + pstcCmdCfg->enCmdType = NORMAL; + pstcCmdCfg->bDataPresent = FALSE; + pstcCmdCfg->u8Index = 0; + pstcCmdCfg->enAutoCmd = AUTO_DISABLE; + pstcCmdCfg->u16BlockCount = 0; + pstcCmdCfg->u16BlockSize = 0; + pstcCmdCfg->u32Argument1 = 0; +#ifdef SD_DMA + pstcCmdCfg->u32SysAddr_Arg2 = 0xFFFFFFFF; + pstcCmdCfg->enbound = BOUND_4K; +#endif + pstcCmdCfg->pu32Buffer = NULL; + pstcCmdCfg->pfnErrorResponseCallback = NULL; +} + +/** + ****************************************************************************** + ** \brief Check whether the command complete + ** + ** \return TRUE Completed + ** \return FALSE Imcompleted + ** + ******************************************************************************/ +static boolean_t SdGetCmdComplete(void) +{ + if(TRUE == Sd_stcCtrl->SNINTST_f.CMDCMPLT) //command complete? + { + Sd_stcCfg.bCmdComplete = TRUE; + } + else + { + Sd_stcCfg.bCmdComplete = FALSE; + } + + return (Sd_stcCfg.bCmdComplete); +} + +/** + ****************************************************************************** + ** \brief Clear command complete flag + ** + ******************************************************************************/ +static void SdClearCmdComplete(void) +{ + Sd_stcCfg.bCmdComplete = FALSE; +} + +/** + ****************************************************************************** + ** \brief Check whether the transfer complete + ** + ** \return TRUE Completed + ** \return FALSE Imcompleted + ** + ******************************************************************************/ +static boolean_t SdGetTrsComplete(void) +{ + if(1 == Sd_stcCtrl->SNINTST_f.TRSFCMPLT) //Transfer complete + { + Sd_stcCfg.bSendComplete = TRUE; + } + else + { + Sd_stcCfg.bSendComplete = FALSE; + } + + return (Sd_stcCfg.bSendComplete); +} + +/** + ****************************************************************************** + ** \brief Wait for card status stable and set the card status flag + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCfg Pointer of SDIF configuration data + ** + ******************************************************************************/ +static void SdGetCardStatus(volatile stc_sd_t* pstcSd,volatile stc_sd_config_t* pstcCfg) +{ + uint16_t waittime = WAITTIME; + + while((pstcSd->SPRSTAT_f.CARDSTB == 0) && (waittime > 0)) + { + waittime--; + dly_1unit(1); + } + + if(1 == pstcSd->SPRSTAT_f.CARDINS) + { + pstcCfg->enExist= INSERTED; + } + else + { + pstcCfg->enExist= REMOVAL; + } +} + +/** + ****************************************************************************** + ** \brief SD interrupt handler + ** + ******************************************************************************/ +static void SdIrqHandler(void) +{ + /* To do ... */ +} + +/** + ****************************************************************************** + ** \brief get response + ** + ** This function will get the response data. + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] enSdresponse SD response type + ** \param [out] pu32Buf Buffer of received response data. + ** + ******************************************************************************/ +static void SdGetResponse(volatile stc_sd_t* pstcSd,en_sd_response_t enSdresponse,uint32_t* pu32Buf) +{ + switch(enSdresponse) + { + case R1NORMAL_R5_R6_R7: + case R1B_NORMAL: + case R3_R4: + case R5B: + pu32Buf[0] = pstcSd->SRESP0; + pu32Buf[0] |=((uint32_t)pstcSd->SRESP1<<16); + break; + case R1AUTO: + case R1B_AUTO: + pu32Buf[0] = pstcSd->SRESP6; + pu32Buf[0] |=((uint32_t)pstcSd->SRESP7<<16); + break; + case R2: //120 bits + pu32Buf[0] = pstcSd->SRESP0; + pu32Buf[0] |=(uint32_t)pstcSd->SRESP1<<16; + pu32Buf[1] = pstcSd->SRESP2; + pu32Buf[1] |=(uint32_t)pstcSd->SRESP3<<16; + pu32Buf[2] = pstcSd->SRESP4; + pu32Buf[2] |=(uint32_t)pstcSd->SRESP5<<16; + pu32Buf[3] = pstcSd->SRESP6; + pu32Buf[3] |=((uint32_t)pstcSd->SRESP7&0x00FF)<<16; + break; + default : + break; + } +} + +/** + ****************************************************************************** + ** \brief Send command without data transfer using DAT line + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg Pointer of SD command configuration + ** + ** \retval TURE Command is sent + ** \retval FALSE Command sent error + ** + ******************************************************************************/ +static boolean_t SdSendCmdOnly(volatile stc_sd_t* pstcSd, stc_sd_comdconfig_t * pstcCmdCfg) +{ + boolean_t result = FALSE; + uint8_t u8Index = pstcCmdCfg->u8Index & 0x3F; + uint16_t waittime = RETRYTIMES; + + /* Wait for data line free */ + while((TRUE == pstcSd->SPRSTAT_f.CMDDATINH) && (waittime > 0)) + { + waittime--; + dly_1unit(1); + } + + /* Wait for command line free */ + waittime = RETRYTIMES; + + while((TRUE == pstcSd->SPRSTAT_f.CMDINH) && (waittime > 0)) + { + waittime--; + dly_1unit(1); + } + + pstcSd->SSA1 = pstcCmdCfg->u32Argument1; + pstcSd->SBSIZE_f.TRSFBLCKSZ = pstcCmdCfg->u16BlockSize; + pstcSd->STRSFMD_f.DTTRSFDIR = pstcCmdCfg->enReadWrite; + + /* set the response type,index check enable and CRC check enable of command register*/ + switch(pstcCmdCfg->enResponse) + { + case R1NORMAL_R5_R6_R7: + case R1AUTO: + pstcSd->SCMMD = 0x0002|(u8Index<<8)|0x0018|(pstcCmdCfg->bDataPresent<<5); + break; + case R1B_NORMAL: + case R1B_AUTO: + case R5B: + pstcSd->SCMMD = 0x0003|(u8Index<<8)|0x0018; + break; + case R2:; + pstcSd->SCMMD = 0x0001|(u8Index<<8)|0x0008; + break; + case R3_R4: + pstcSd->SCMMD = 0x0002|(u8Index<<8); + break; + default : + pstcSd->SCMMD &= 0x0000; + break; + } + + waittime = RETRYTIMES; + + /* Wait for command line free */ + while((TRUE == pstcSd->SPRSTAT_f.CMDINH) && (waittime > 0)) + { + waittime--; + dly_1unit(1); + } + + waittime = RETRYTIMES; + + /* Wait for data line free */ + while((TRUE == pstcSd->SPRSTAT_f.CMDDATINH) && (waittime > 0)) + { + waittime--; + dly_1unit(1); + } + + if(TRUE == SdGetCmdComplete()) + { + SdClearCmdComplete(); + result = TRUE; + } + else + { + result = FALSE; + } + + return result; +} + +/** + ****************************************************************************** + ** \brief Send command with data transfer using DAT line + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg Pointer of SD command configuration + ** + ** \retval TURE Command is sent + ** \retval FALSE Command sent error + ** + ******************************************************************************/ +static boolean_t SdSendCmdDatLine(volatile stc_sd_t* pstcSd, stc_sd_comdconfig_t * pstcCmdCfg) +{ + uint8_t result = FALSE; + uint16_t blockcount= pstcCmdCfg->u16BlockCount; + + pstcSd->SBSIZE_f.TRSFBLCKSZ =pstcCmdCfg->u16BlockSize & 0x0FFF; + + if(blockcount == 1) //single block + { + pstcSd->SBLCNT = 1; + pstcSd->STRSFMD_f.BLCKCNTSEL = 0; + } + else //multiple block + { + pstcSd->STRSFMD_f.BLCKCNTSEL = 1; + pstcSd->STRSFMD_f.BLCKCNTEN = 1; + pstcSd->STRSFMD_f.AUTOCMDEN = pstcCmdCfg->enAutoCmd; + pstcSd->SBLCNT = blockcount; + } + + result = SdSendCmdOnly(pstcSd,pstcCmdCfg) ; + + return result; +} + +/** + ****************************************************************************** + ** \brief Send data segment using DAT line + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg SD command configuration + ** \param [in] pu32Buf Data to be send + ** + ** \retval TURE Data is sent + ** \retval FALSE Error occurs during transmission + ** + ******************************************************************************/ +static boolean_t SdTxData(volatile stc_sd_t* pstcSd, stc_sd_comdconfig_t * pstcCmdCfg,uint32_t* pu32Buf) +{ + uint16_t i ; + uint16_t u16blocksize= pstcCmdCfg->u16BlockSize; //unit of Bytes + uint32_t* pbuf = pu32Buf; + uint8_t result = FALSE; + + while(TRUE != pstcSd->SNINTST_f.BUFWRRDY);// endless loop + + pstcSd->SNINTST_f.BUFWRRDY = 0; + + for(i=u16blocksize>>2;i!=0;i--) + { + if((pstcSd->SEINTST_f.DTTOERR == 1) + ||(pstcSd->SEINTST_f.DTEBERR == 1) + ||(pstcSd->SEINTST_f.DTCRCERR == 1)) + { + //clear the int status + pstcSd->SEINTST_f.DTTOERR = 1; + pstcSd->SEINTST_f.DTEBERR = 1; + pstcSd->SEINTST_f.DTCRCERR = 1; + return result; + } + + while(pstcSd->SPRSTAT_f.BUFWREN == 0) ;//endless loop + pstcSd->SBUFDP = *pbuf; + pbuf++; + } + + while(TRUE != SdGetTrsComplete()); + + result = TRUE; + + return result; +} + +/** + ****************************************************************************** + ** \brief Get response data after command + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg SD Command configuration + ** \param [out] pu32Buf Buffer of received response data. + ** + ** \retval TURE The correct response is received + ** \retval FALSE Error response is received + ** + ******************************************************************************/ +static boolean_t SdRxRsp(volatile stc_sd_t* pstcSd,stc_sd_comdconfig_t * pstcCmdCfg,uint32_t* pu32Buf) +{ + boolean_t result = FALSE; + + //clear the buffer + pu32Buf[0] = 0; + pu32Buf[1] = 0; + pu32Buf[2] = 0; + pu32Buf[3] = 0; + + //get response data + SdGetResponse(pstcSd,pstcCmdCfg->enResponse,pu32Buf); + + //check the error in response data + if(NULL != pstcCmdCfg->pfnErrorResponseCallback) + { + pstcCmdCfg->pfnErrorResponseCallback(pstcSd); + } + else + { + result = TRUE; + } + + return result; +} + +/** + ****************************************************************************** + ** \brief Receive data segment using DAT line + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg SD command configuration + ** \param [in] pu32Buf Pointer to reception buffer + ** + ** \retval TURE Command is sent + ** \retval FALSE Command send error + ** + ******************************************************************************/ +static boolean_t SdRxData(volatile stc_sd_t* pstcSd, stc_sd_comdconfig_t * pstcCmdCfg, uint32_t* pu32Buf) +{ + uint16_t i ; + uint16_t u16blocksize= pstcCmdCfg->u16BlockSize; //unit of Bytes + uint32_t* pbuf = pu32Buf; + uint8_t result = FALSE; + + while(TRUE != pstcSd->SNINTST_f.BUFRDRDY);//endless loop + + for(i=u16blocksize>>2;i!=0;i--) + { + if((pstcSd->SEINTST_f.DTTOERR == 1) //DataTimeout Error + ||(pstcSd->SEINTST_f.DTEBERR==1) //Data End Bit Error + ||(pstcSd->SEINTST_f.DTCRCERR==1)) //Data CRC Error + { + //clear the int status + pstcSd->SEINTST_f.DTTOERR = 1; + pstcSd->SEINTST_f.DTEBERR=1; + pstcSd->SEINTST_f.DTCRCERR=1; + return result; + } + + while(pstcSd->SPRSTAT_f .BUFRDEN == 0) ;//endless loop + *pbuf = pstcSd->SBUFDP; + pbuf++ ; + } + + result = TRUE; + + return result; +} + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Enable the interrupt flag of SD + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Sd_EnableInt(volatile stc_sd_t* pstcSd ) +{ + if(NULL == pstcSd) + { + return ErrorInvalidParameter; + } + + //buffer read&write ready int + pstcSd->SNINTSTE_f.BUFRDRDYS = 1; + pstcSd->SNINTSTE_f.BUFWRRDYS = 1; + + //Transfer & command complete + pstcSd->SNINTSTE_f.TRSFCMPLTS = 1; + pstcSd->SNINTSTE_f.CMDCMPLTS = 1; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable the interrupt flag of SD + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Sd_DisableInt(volatile stc_sd_t* pstcSd ) +{ + if(NULL == pstcSd) + { + return ErrorInvalidParameter; + } + + //buffer read&write ready int + pstcSd->SNINTSTE_f.BUFRDRDYS = 0; + pstcSd->SNINTSTE_f.BUFWRRDYS = 0; + + //Transfer & command complete + pstcSd->SNINTSTE_f.TRSFCMPLTS = 0; + pstcSd->SNINTSTE_f.CMDCMPLTS = 0; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Detect the SD card insertion status + ** + ** \param [in] pstcCmdCfg Command parameters + ** + ** \retval DEBOUNCING SD card is debouncing + ** \retval INSERTED SD card is inserted + ** \retval REMOVAL SD card is removed + ** + ******************************************************************************/ +en_sd_existing_t Sd_CardDetect(volatile stc_sd_config_t* pstcCmdCfg) +{ + if(NULL == pstcCmdCfg) + return DEBOUNCING; + else + return (pstcCmdCfg->enExist); +} + +/** + ****************************************************************************** + ** \brief Supply clock to an SD card + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] enClk SD Clock frequency + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Sd_ClockSupply(volatile stc_sd_t* pstcSd,en_sd_clk_t enClk) +{ + uint8_t u8baseclock; + uint16_t u16divider; + u8baseclock = pstcSd->CAPBLTY0_f.SDBASECLK;//read hardware init value of the capability reigister + + if(NULL == pstcSd) + { + return ErrorInvalidParameter; + } + + //set the 10 bit divider of Clock control register, N=baseclock/(2*enClk) + if(u8baseclock) + { + if(u8baseclock== enClk) + { + u16divider = 0x0000;/// base clock + } + else + { + u16divider = (u8baseclock>>1)/enClk; + } + + pstcSd->SCLKCTL_f.SDCLKSEL = (uint8_t)(u16divider &0x00FF);//lower 8bits + pstcSd->SCLKCTL_f.UPSDCLKSEL = (u16divider &0x0300)>>8; //higher 2bits + } + else //if the base clock frequenct register value is 0,using the default value 160 Mhz + { + pstcSd->SHCTL2_f.PREVALEN = 1;// automatic selection by preset value (4) + } + + pstcSd->SCLKCTL_f.INTLCLCKEN = 1; + + while (!pstcSd->SCLKCTL_f.INTLCLCKST); + + pstcSd->SCLKCTL_f.SDCLCKEN = 1; + return Ok; +} + +/** + ****************************************************************************** + ** \brief stop clock + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** + ** \retval Ok + ******************************************************************************/ +en_result_t Sd_ClockStop(volatile stc_sd_t* pstcSd) +{ + if(pstcSd == NULL) + { + return ErrorInvalidParameter; + } + + pstcSd->SCLKCTL_f.SDCLCKEN = 0; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Provide power for SD card + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] enVoltage SD card voltage setting + ** + ** \retval Ok + ******************************************************************************/ +en_result_t Sd_BusPowerControl(volatile stc_sd_t* pstcSd,en_sd_busvoltage_t enVoltage) +{ + if((NULL == pstcSd) || (enVoltage > V3_3) || (enVoltage < V1_8)) + { + return ErrorInvalidParameter; + } + + pstcSd->SPWRCTL_f.SDBUSVLSEL = enVoltage; + pstcSd->SPWRCTL_f.SDBUSPWR = 1; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Transmit commands and check the corresponding response + ** + ** \param [in] enTran Transmission type depends on the CMD and expected response + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg Command parameters + ** \param [in] pu32Buf Buffer pointer storing the recieved data + ** + ** \retval TRUE Data is transmitted + ** \retval FAlSE Error occurs during transmission + ** + ******************************************************************************/ +boolean_t Sd_SendCmd(en_sd_transaction_t enTran,volatile stc_sd_t* pstcSd,stc_sd_comdconfig_t * pstcCmdCfg,uint32_t* pu32Buf) +{ + boolean_t result = FALSE; + + switch(enTran) + { + case NO_RESPONSE: + result = SdSendCmdOnly(pstcSd,pstcCmdCfg); + break; + case NO_DATA: + if(TRUE == SdSendCmdOnly(pstcSd,pstcCmdCfg)) + { + result = SdRxRsp(pstcSd,pstcCmdCfg,pu32Buf); + } + break; + case SINGLE_BLOCK: + if(TRUE == SdSendCmdDatLine(pstcSd,pstcCmdCfg)) + { + result = SdRxRsp(pstcSd,pstcCmdCfg,pu32Buf); + } + break; + case MULTI_BLOCK: + //To Do + break; + default: + break; + } + return result; +} + +/** + ****************************************************************************** + ** \brief Transmit data segment for write commands only. + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg Command parameters + ** \param [in] pu32Buf Buffer pointer storing tje recieved data + ** + ** \retval TRUE Data is transmitted + ** \retval FAlSE Error occurs during transmission + ** + ******************************************************************************/ +boolean_t Sd_TxData(volatile stc_sd_t* pstcSd,stc_sd_comdconfig_t * pstcCmdCfg,uint32_t* pu32Buf) +{ + boolean_t result = FALSE; + + result = SdTxData(pstcSd,pstcCmdCfg,pu32Buf); + + return result; +} + +/** + ****************************************************************************** + ** \brief Receive the data of read command + ** + ** \param [in] enTran Transmission type depends on the CMD and expected response + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] pstcCmdCfg Command parameters + ** \param [out] pu32Buf Buffer pointer storing tje recieved data + ** + ** \retval TRUE Data is received + ** \retval FAlSE Error occurs during reception + ** + ******************************************************************************/ +boolean_t Sd_RxData(en_sd_transaction_t enTran,volatile stc_sd_t* pstcSd,stc_sd_comdconfig_t * pstcCmdCfg,uint32_t* pu32Buf) +{ + boolean_t result = FALSE; + uint8_t waittime = RETRYTIMES; + + //wait for read buffer is ready + while((0 == pstcSd->SPRSTAT_f.BUFRDEN) && (waittime > 0)) + { + waittime--; + dly_1unit(1); + } + + switch(enTran) + { + case SINGLE_BLOCK: + result = SdRxData(pstcSd,pstcCmdCfg,pu32Buf); + break; + case MULTI_BLOCK: + //To Do + break; + default: + break; + } + return result; +} + +/** + ****************************************************************************** + ** \brief software reset for command and data line + ** + ** \param [in] pstcSd Pointer of SDIF instance + ** \param [in] u8reset Options of reset setting,such as command ,data line and all + ** + ** \retval Ok + ** + ******************************************************************************/ +en_result_t Sd_SoftwareReset( volatile stc_sd_t* pstcSd,uint8_t u8reset) +{ + if(NULL == pstcSd) + { + return ErrorInvalidParameter; + } + + pstcSd->SSRST |= u8reset; + + while(pstcSd->SSRST & (~u8reset)); //endless loop + + pstcSd->SSRST &= ~u8reset; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief SD interrupt entry + ** + ******************************************************************************/ +void Sd_Handler(void) +{ + SdIrqHandler(); +} + +/** + ****************************************************************************** + ** \brief Initialize SD host + ** + ** \retval Ok Initialization successful + ** \retval Error Initialization failed + ** + ******************************************************************************/ +en_result_t Sd_HostInit( void) +{ + SdInitPins(); + + if (TRUE == SdEnablePCG()) + { + SdInitHostInternalData(&Sd_stcCfg, &Sd_stcCmdCfg); + SdGetCardStatus(Sd_stcCtrl,&Sd_stcCfg); + + if(INSERTED == Sd_CardDetect(&Sd_stcCfg)) + { + Sd_EnableInt(Sd_stcCtrl); + Sd_BusPowerControl(Sd_stcCtrl,V3_3); + Sd_ClockSupply(Sd_stcCtrl,CLK_25M); + return Ok; + } + else + { + return Error; + } + } + else + { + return Error; + } +} + +/** + ****************************************************************************** + ** \brief Deinitializes SD + ** + ** \retval Ok Internal data has been setup + ** + ******************************************************************************/ +en_result_t Sd_HostDeInit(void ) +{ + Sd_SoftwareReset(Sd_stcCtrl, RESET_ALL); + Sd_DisableInt(Sd_stcCtrl); + SdDisablePCG(); + return Ok; +} + +//@} //SdifGroup + +#endif // #if (defined(PDL_PERIPHERAL_SD_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.h new file mode 100644 index 0000000000..d88d853942 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sd/sd.h @@ -0,0 +1,310 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file sd.h + ** + ** Headerfile for SD functions + ** + ** History: + ** - 2013-04-16 1.0 QXu First version. + ** - 2013-07-24 1.1 RQian Modification. + ** + ******************************************************************************/ + +#ifndef __SD_H__ +#define __SD_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "pdl.h" +#include "sd_cfg.h" + +#if (defined(PDL_PERIPHERAL_SD_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \addtogroup SdifGroup + ******************************************************************************/ +//@{ + +/****************************************************************************** + * SDIF registers definitions + ******************************************************************************/ + +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_sd_t FM4_SDIF_TypeDef + +/* The Physical Layer Specification Version 3.0x defines that SDXC card may indicate 500ms busy. + Then host driver may need to change timeout value for SDXC.It is set more than 500ms +timeout regardless of card capacities.*/ +#define SD_TIMEOUT_DATLINE 1000 //ms + +/* software reset options*/ +#define RESET_DAT (1<<2) +#define RESET_CMD (1<<1) +#define RESET_ALL 1 +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +typedef void (*func_ptr_sd_arg32_t)( volatile stc_sd_t *); + +/** + ****************************************************************************** + ** \brief SD clock SDCLK frequency + ******************************************************************************/ + +typedef enum en_sd_clk +{ + CLK_25M = 25, ///<25 Mhz + CLK_50M = 50 ///<50 Mhz +}en_sd_clk_t; +/** + ****************************************************************************** + ** \brief SD transaction cases (with or without data line) + ******************************************************************************/ + +typedef enum en_sd_transaction +{ + NO_RESPONSE = 0, ///SNINTST_f.CMDCMPLT) // Command complete + { + pstcSdif->SNINTST = 0x0001u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.TRSFCMPLT) // Transfer complete + { + pstcSdif->SNINTST = 0x0002u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.BLCKGEVNT) // block gap event + { + pstcSdif->SNINTST = 0x0004u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnBlockGapIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnBlockGapIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.DMAINT) // DMA interrupt + { + pstcSdif->SNINTST = 0x0008u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnDmaIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnDmaIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.BUFWRRDY) // Buffer write ready + { + pstcSdif->SNINTST = 0x0010u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.BUFRDRDY) // Buffer read ready + { + pstcSdif->SNINTST = 0x0020u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.CARDINS) // Card insetion + { + pstcSdif->SNINTST = 0x0040u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnCardInsertIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnCardInsertIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.CARDRMV) // Card removal + { + pstcSdif->SNINTST = 0x0080u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnCardRemovalIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnCardRemovalIrqCb(); + } + } + + if (1u == pstcSdif->SNINTST_f.CARDINT) // Card interrupt + { + pstcSdif->SNINTST = 0x0100u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcNormalIrqCb.pfnCardIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnCardIrqCb(); + } + } + + /* Error interrupt handler */ + if (1u == pstcSdif->SEINTST_f.CMDTOERR) // Command timeout error + { + pstcSdif->SEINTST = 0x0001u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnCmdTimeoutErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnCmdTimeoutErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.CMDCRCERR) // Command CRC error + { + pstcSdif->SEINTST = 0x0002u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnCmdCrcErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnCmdCrcErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.CMDEBERR) // Command end bit error + { + pstcSdif->SEINTST = 0x0004u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnCmdEndBitErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnCmdEndBitErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.CMDIDXERR) // Command index error + { + pstcSdif->SEINTST = 0x0008u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnCmdIndexErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnCmdIndexErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.DTTOERR) // Data timeout error + { + pstcSdif->SEINTST = 0x0010u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnDataTimeoutErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnDataTimeoutErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.DTEBERR) // Data end bit error + { + pstcSdif->SEINTST = 0x0020u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnDataEndBitErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnDataEndBitErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.DTCRCERR) // Data CRC error + { + pstcSdif->SEINTST = 0x0040u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnDataCrcErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnDataCrcErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.CRTLMTERR) // Current limitation error + { + pstcSdif->SEINTST = 0x0080u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnCurrentLimitErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnCurrentLimitErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.ACMD12ERR) // Auto CMD12 error + { + pstcSdif->SEINTST = 0x0100u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnAutoCmdErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnAutoCmdErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.ADMAERR) // ADMA error + { + pstcSdif->SEINTST = 0x0200u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnAdmaErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnAdmaErrIrqCb(); + } + } + + if (1u == pstcSdif->SEINTST_f.TUNINGERR) // Tuning error + { + pstcSdif->SEINTST = 0x0400u; // Clear interrupt flag + if (NULL != pstcSdifInternData->stcErrIrqCb.pfnTuningErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnTuningErrIrqCb(); + } + } + + return; +} // SdifIrqHandler + +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on SDIF instance + ** + ** \param pstcSdif Pointer to SDIF instance + ** + ******************************************************************************/ +static void SdifInitNvic(volatile stc_sdifn_t* pstcSdif) +{ + NVIC_ClearPendingIRQ(SD_IRQn); + NVIC_EnableIRQ(SD_IRQn); + NVIC_SetPriority(SD_IRQn, PDL_IRQ_LEVEL_SD); +} // SdifInitNvic + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on SDIF instance + ** + ** \param pstcSdif Pointer to SDIF instance + ** + ******************************************************************************/ +static void SdifDeInitNvic(volatile stc_sdifn_t* pstcSdif) +{ + NVIC_ClearPendingIRQ(SD_IRQn); + NVIC_DisableIRQ(SD_IRQn); + NVIC_SetPriority(SD_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + +} // SdifDeInitNvic +#endif // #if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain SDIF instance. + ** + ** \param pstcSdif Pointer to SDIF instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_sdif_intern_data_t* SdifGetInternDataPtr(volatile stc_sdifn_t* pstcSdif) +{ + uint8_t u8Instance; + + for (u8Instance = 0u; u8Instance < SDIF_INSTANCE_COUNT; u8Instance++) + { + if (pstcSdif == m_astcSdifInstanceDataLut[u8Instance].pstcInstance) + { + return &m_astcSdifInstanceDataLut[u8Instance].stcInternData; + } + } + + return NULL; +} + + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Initialize SD interface + ** + ** This function initializes an SDIF module + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] pstcConfig SDIF module configuration + ** + ** \retval Ok SDIF initialized normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - pstcConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Sdif_Init( volatile stc_sdifn_t* pstcSdif, + const stc_sdif_config_t* pstcConfig ) +{ + // Pointer to internal data + stc_sdif_intern_data_t* pstcSdifInternData ; + + // Check for NULL pointer + if ((NULL == pstcSdif) || + (NULL == pstcConfig)) + { + return ErrorInvalidParameter ; + } + + // Get pointer to internal data structure ... + pstcSdifInternData = SdifGetInternDataPtr( pstcSdif ) ; + + // Check for instance available or not + if(NULL == pstcSdifInternData) + { + return ErrorInvalidParameter ; + } + + // Select ADMA or not + pstcSdif->SHCTL1_f.DMASEL = ((TRUE == pstcConfig->bSelAdma) ? 2u : 0u); + + // Set speed mode + pstcSdif->SHCTL1_f.HIGHSPDEN = ((TRUE == pstcConfig->bEnableHighSpeed) ? 1u : 0u); + + // Set bit width + pstcSdif->SHCTL1_f.DATAWIDTH = ((TRUE == pstcConfig->bEnable4BitMode) ? 1u : 0u); + + // Enable all status + pstcSdif->SNINTSTE = 0x1FFFu; + pstcSdif->SEINTSTE = 0x07FFu; + +#if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) + // Enable normal interrupt signal + if(NULL != pstcConfig->pstcNormalIrqEn) + { + pstcSdif->SNINTSGE = pstcConfig->pstcNormalIrqEn->u16NormalStatus; + } + + // Set normal interrupt callback functions + if(NULL != pstcConfig->pstcNormalIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = pstcConfig->pstcNormalIrqCb->pfnCommandCompleteIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = pstcConfig->pstcNormalIrqCb->pfnTransferCompleteIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnBlockGapIrqCb = pstcConfig->pstcNormalIrqCb->pfnBlockGapIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnDmaIrqCb = pstcConfig->pstcNormalIrqCb->pfnDmaIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = pstcConfig->pstcNormalIrqCb->pfnBufferWriteReadyIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = pstcConfig->pstcNormalIrqCb->pfnBufferReadReadyIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnCardInsertIrqCb = pstcConfig->pstcNormalIrqCb->pfnCardInsertIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = pstcConfig->pstcNormalIrqCb->pfnCardRemovalIrqCb; + pstcSdifInternData->stcNormalIrqCb.pfnCardIrqCb = pstcConfig->pstcNormalIrqCb->pfnCardIrqCb; + } + + // Enable error interrupt signal + if(NULL != pstcConfig->pstcErrIrqEn) + { + pstcSdif->SEINTSGE = pstcConfig->pstcErrIrqEn->u16ErrStatus; + } + + // Set error interrupt callback functions + if(NULL != pstcConfig->pstcErrIrqCb) + { + pstcSdifInternData->stcErrIrqCb.pfnCmdTimeoutErrIrqCb = pstcConfig->pstcErrIrqCb->pfnCmdTimeoutErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnCmdCrcErrIrqCb = pstcConfig->pstcErrIrqCb->pfnCmdCrcErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnCmdEndBitErrIrqCb = pstcConfig->pstcErrIrqCb->pfnCmdEndBitErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnCmdIndexErrIrqCb = pstcConfig->pstcErrIrqCb->pfnCmdIndexErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnDataTimeoutErrIrqCb = pstcConfig->pstcErrIrqCb->pfnDataTimeoutErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnDataEndBitErrIrqCb = pstcConfig->pstcErrIrqCb->pfnDataEndBitErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnDataCrcErrIrqCb = pstcConfig->pstcErrIrqCb->pfnDataCrcErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnCurrentLimitErrIrqCb = pstcConfig->pstcErrIrqCb->pfnCurrentLimitErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnAutoCmdErrIrqCb = pstcConfig->pstcErrIrqCb->pfnAutoCmdErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnAdmaErrIrqCb = pstcConfig->pstcErrIrqCb->pfnAdmaErrIrqCb; + pstcSdifInternData->stcErrIrqCb.pfnTuningErrIrqCb = pstcConfig->pstcErrIrqCb->pfnTuningErrIrqCb; + } + + // Set NVIC + if(TRUE == pstcConfig->bTouchNvic) + { + SdifInitNvic(pstcSdif); + } + +#endif + + return Ok; +} // Sdif_Init + +/** + ****************************************************************************** + ** \brief De-Initialize SD interface + ** + ** This function de-initializes an SDIF module + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] bTouchIrq Disable IRQ or not + ** \param [in] bTouchIrqCb Reset callback functions in internal data or not + ** \param [in] bTouchNvic Disable NVIC or not + ** + ** \retval Ok SDIF de-initialized normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_DeInit( volatile stc_sdifn_t* pstcSdif, + boolean_t bTouchIrq, + boolean_t bTouchIrqCb, + boolean_t bTouchNvic) +{ +#if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) + // Pointer to internal data + stc_sdif_intern_data_t* pstcSdifInternData ; + + // Get pointer to internal data structure ... + pstcSdifInternData = SdifGetInternDataPtr( pstcSdif ) ; + + if(NULL == pstcSdifInternData) + { + return ErrorInvalidParameter ; + } +#endif + + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + // Clear clock control and power control registers + pstcSdif->SCLKCTL = 0x0000u; + pstcSdif->SPWRCTL = 0x00u; + +#if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) + if(TRUE == bTouchIrq) + { + pstcSdif->SNINTSGE = 0x0000u; + pstcSdif->SEINTSGE = 0x0000u; + } + + if(TRUE == bTouchIrqCb) + { + pstcSdifInternData->stcNormalIrqCb.pfnCommandCompleteIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnTransferCompleteIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnBlockGapIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnDmaIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnBufferWriteReadyIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnBufferReadReadyIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnCardInsertIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnCardRemovalIrqCb = NULL; + pstcSdifInternData->stcNormalIrqCb.pfnCardIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnCmdTimeoutErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnCmdCrcErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnCmdEndBitErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnCmdIndexErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnDataTimeoutErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnDataEndBitErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnDataCrcErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnCurrentLimitErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnAutoCmdErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnAdmaErrIrqCb = NULL; + pstcSdifInternData->stcErrIrqCb.pfnTuningErrIrqCb = NULL; + } + + if(TRUE == bTouchNvic) + { + SdifDeInitNvic(pstcSdif); + } +#endif + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable SDIF normal interrupt + ** + ** This function enable the SDIF interrupt which is selected. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] enNormalIrqSel SDIF normal interrupt selection + ** + ** \retval Ok Enable normal interrupt normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - enNormalIrqSel out of range + ******************************************************************************/ +en_result_t Sdif_EnableNormalIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_normal_irq_sel_t enNormalIrqSel) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + switch (enNormalIrqSel) + { + case SdifCommandCompleteIrq: + pstcSdif->SNINTSGE_f.CMDCMPLTG = 1u; + break; + case SdifTransferCompleteIrq: + pstcSdif->SNINTSGE_f.TRSFCMPLTG = 1u; + break; + case SdifBlockGapEventIrq: + pstcSdif->SNINTSGE_f.BLCKGEVNTG = 1u; + break; + case SdifDmaIrq: + pstcSdif->SNINTSGE_f.DMAINTG = 1u; + break; + case SdifBufferWriteReadyIrq: + pstcSdif->SNINTSGE_f.BUFWRRDYG = 1u; + break; + case SdifBufferReadReadyIrq: + pstcSdif->SNINTSGE_f.BUFRDRDYG = 1u; + break; + case SdifCardInsertionIrq: + pstcSdif->SNINTSGE_f.CARDINSG = 1u; + break; + case SdifCardRemovalIrq: + pstcSdif->SNINTSGE_f.CARDRMVG = 1u; + break; + case SdifCardIrq: + pstcSdif->SNINTSGE_f.CARDINTG = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable SDIF normal interrupt + ** + ** This function disable the SDIF interrupt which is selected. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] enNormalIrqSel SDIF normal interrupt selection + ** + ** \retval Ok Disable normal interrupt normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - enNormalIrqSel out of range + ******************************************************************************/ +en_result_t Sdif_DisableNormalIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_normal_irq_sel_t enNormalIrqSel) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + switch (enNormalIrqSel) + { + case SdifCommandCompleteIrq: + pstcSdif->SNINTSGE_f.CMDCMPLTG = 0u; + break; + case SdifTransferCompleteIrq: + pstcSdif->SNINTSGE_f.TRSFCMPLTG = 0u; + break; + case SdifBlockGapEventIrq: + pstcSdif->SNINTSGE_f.BLCKGEVNTG = 0u; + break; + case SdifDmaIrq: + pstcSdif->SNINTSGE_f.DMAINTG = 0u; + break; + case SdifBufferWriteReadyIrq: + pstcSdif->SNINTSGE_f.BUFWRRDYG = 0u; + break; + case SdifBufferReadReadyIrq: + pstcSdif->SNINTSGE_f.BUFRDRDYG = 0u; + break; + case SdifCardInsertionIrq: + pstcSdif->SNINTSGE_f.CARDINSG = 0u; + break; + case SdifCardRemovalIrq: + pstcSdif->SNINTSGE_f.CARDRMVG = 0u; + break; + case SdifCardIrq: + pstcSdif->SNINTSGE_f.CARDINTG = 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable SDIF error interrupt + ** + ** This function enable the SDIF error interrupt which is selected. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] enErrIrqSel SDIF error interrupt selection + ** + ** \retval Ok Enable error interrupt normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - enErrIrqSel out of range + ******************************************************************************/ +en_result_t Sdif_EnableErrIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_err_irq_sel_t enErrIrqSel) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + switch (enErrIrqSel) + { + case SdifCmdTimeoutErrIrq: + pstcSdif->SEINTSGE_f.CMDTOERRG = 1u; + break; + case SdifCmdCrcErrIrq: + pstcSdif->SEINTSGE_f.CMDCRCERRG = 1u; + break; + case SdifCmdEndBitErrIrq: + pstcSdif->SEINTSGE_f.CMDEBERRG = 1u; + break; + case SdifCmdIndexErrIrq: + pstcSdif->SEINTSGE_f.CMDIDXERRG = 1u; + break; + case SdifDataTimeoutErrIrq: + pstcSdif->SEINTSGE_f.DTTOERRG = 1u; + break; + case SdifDataCrcErrIrq: + pstcSdif->SEINTSGE_f.DTCRCERRG = 1u; + break; + case SdifDataEndBitErrIrq: + pstcSdif->SEINTSGE_f.DTEBERRG = 1u; + break; + case SdifCurrentLimitErrIrq: + pstcSdif->SEINTSGE_f.CRTLMTERRG = 1u; + break; + case SdifAutoCmdErrIrq: + pstcSdif->SEINTSGE_f.ACMD12ERRG = 1u; + break; + case SdifAdmaErrIrq: + pstcSdif->SEINTSGE_f.ADMAERRG = 1u; + break; + case SdifTuningErrIrq: + pstcSdif->SEINTSGE_f.TUNINGERRG = 1u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable SDIF error interrupt + ** + ** This function disable the SDIF error interrupt which is selected. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] enErrIrqSel SDIF error interrupt selection + ** + ** \retval Ok Disable error interrupt normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - enErrIrqSel out of range + ******************************************************************************/ +en_result_t Sdif_DisableErrIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_err_irq_sel_t enErrIrqSel) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + switch (enErrIrqSel) + { + case SdifCmdTimeoutErrIrq: + pstcSdif->SEINTSGE_f.CMDTOERRG = 0u; + break; + case SdifCmdCrcErrIrq: + pstcSdif->SEINTSGE_f.CMDCRCERRG = 0u; + break; + case SdifCmdEndBitErrIrq: + pstcSdif->SEINTSGE_f.CMDEBERRG = 0u; + break; + case SdifCmdIndexErrIrq: + pstcSdif->SEINTSGE_f.CMDIDXERRG = 0u; + break; + case SdifDataTimeoutErrIrq: + pstcSdif->SEINTSGE_f.DTTOERRG = 0u; + break; + case SdifDataCrcErrIrq: + pstcSdif->SEINTSGE_f.DTCRCERRG = 0u; + break; + case SdifDataEndBitErrIrq: + pstcSdif->SEINTSGE_f.DTEBERRG = 0u; + break; + case SdifCurrentLimitErrIrq: + pstcSdif->SEINTSGE_f.CRTLMTERRG = 0u; + break; + case SdifAutoCmdErrIrq: + pstcSdif->SEINTSGE_f.ACMD12ERRG = 0u; + break; + case SdifAdmaErrIrq: + pstcSdif->SEINTSGE_f.ADMAERRG = 0u; + break; + case SdifTuningErrIrq: + pstcSdif->SEINTSGE_f.TUNINGERRG = 0u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +#endif + +/** + ****************************************************************************** + ** \brief Get error status of SDIF + ** + ** This function gets the SDIF error status. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [out] pstcStatus Pointer to error status selection structure + ** + ** \retval Ok Get error status of SDIF normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - pstcStatus == NULL + ******************************************************************************/ +en_result_t Sdif_GetErrStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_err_irq_status_t* pstcStatus) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcStatus->u16ErrStatus = pstcSdif->SEINTST; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Clear error status of SDIF + ** + ** This function clears the SDIF error status which is selected. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] pstcStatus Pointer to error status selection structure + ** + ** \retval Ok Clear error status of SDIF normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - pstcStatus == NULL + ******************************************************************************/ +en_result_t Sdif_ClrErrStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_err_irq_status_t* pstcStatus) +{ + // Check for NULL pointer + if ((NULL == pstcSdif) || (NULL == pstcStatus)) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SEINTST = pstcStatus->u16ErrStatus; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get normal status of SDIF + ** + ** This function gets the SDIF normal status. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [out] pstcStatus Pointer to normal status selection structure + ** + ** \retval Ok Get normal status of SDIF normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_GetNormalStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_normal_irq_status_t* pstcStatus) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcStatus->u16NormalStatus = pstcSdif->SNINTST; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Clear normal status of SDIF + ** + ** This function clears the SDIF normal status which is selected. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] pstcStatus Pointer to normal status selection structure + ** + ** \retval Ok Clear normal status of SDIF normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - pstcStatus == NULL + ******************************************************************************/ +en_result_t Sdif_ClrNormalStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_normal_irq_status_t* pstcStatus) +{ + // Check for NULL pointer + if ((NULL == pstcSdif) || (NULL == pstcStatus)) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SNINTST = pstcStatus->u16NormalStatus; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get error status of SDIF auto command + ** + ** This function gets the SDIF error status of auto command + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] pstcStatus Pointer to normal status selection structure + ** + ** \retval Ok Auto command error status of SDIF gotten normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcSdif == NULL + ** - pstcStatus == NULL + ******************************************************************************/ +en_result_t Sdif_GetAutoCommandErrStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_auto_cmd_err_t* pstcStatus) +{ + // Check for NULL pointer + if ((NULL == pstcSdif) || (NULL == pstcStatus)) + { + return ErrorInvalidParameter ; + } + + pstcStatus->u16AutoCmdErr = pstcSdif->SACMDEST; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable internal clock of SDIF + ** + ** This function makes SD host controller start working. + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok Internal clock of SDIF enabled normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_EnableInternalClock( volatile stc_sdifn_t* pstcSdif ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SCLKCTL_f.INTLCLCKEN = 1u; + + while(1u != pstcSdif->SCLKCTL_f.INTLCLCKST); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable internal clock of SDIF + ** + ** This function makes SD host controller stop working. + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok Internal clock of SDIF enabled normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_DisableInternalClock( volatile stc_sdifn_t* pstcSdif ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SCLKCTL_f.INTLCLCKEN = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable SDCLK output + ** + ** SD host drives SDCLK line. + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok SDCLK output of SDIF enabled normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_EnableSdclk( volatile stc_sdifn_t* pstcSdif ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SCLKCTL_f.SDCLCKEN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable SDCLK output + ** + ** SD host don't drive SDCLK line. + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok SDCLK output of SDIF disabled normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_DisableSdclk( volatile stc_sdifn_t* pstcSdif ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SCLKCTL_f.SDCLCKEN = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the clock division of SD clock + ** + ** This function changes the SD clock division. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] u16Div Division value + ** + ** \retval Ok Clock division is changed normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_SetClkDiv( volatile stc_sdifn_t* pstcSdif, uint16_t u16Div) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + // Set clock division (10-bit) + pstcSdif->SCLKCTL_f.SDCLKSEL = (u16Div & 0xFFu); + pstcSdif->SCLKCTL_f.UPSDCLKSEL = ((u16Div >> 8u) & 0x03u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the bus width of SD Bus + ** + ** This function changes the SD bus width. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] bEnable4BitMode Enable 4-bit mode or not + ** + ** \retval Ok Bus width is set normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_SetBusWidth( volatile stc_sdifn_t* pstcSdif, + boolean_t bEnable4BitMode ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + // Set bit width + pstcSdif->SHCTL1_f.DATAWIDTH = ((TRUE == bEnable4BitMode) ? 1u : 0u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the bus speed mode of SD Bus + ** + ** This function changes the SD bus width. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] bEnableHighSpeedMode Enable high speed mode or not + ** + ** \retval Ok Bus width is set normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_SetBusSpeedMode( volatile stc_sdifn_t* pstcSdif, + boolean_t bEnableHighSpeedMode ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + // Set bit width + pstcSdif->SHCTL1_f.HIGHSPDEN = ((TRUE == bEnableHighSpeedMode) ? 1u : 0u); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Select bus voltage of SD bus + ** + ** This function selects the SD bus voltage + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] enVoltage Voltage selection + ** + ** \retval Ok Voltage selected normally + ** \retval ErrorInvalidParameter pstcSdif == NULL or enVoltage out of range + ******************************************************************************/ +en_result_t Sdif_SelBusVoltage( volatile stc_sdifn_t* pstcSdif, + en_sdif_voltage_sel_t enVoltage) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + switch (enVoltage) + { + case SdifVoltage18v: + pstcSdif->SPWRCTL_f.SDBUSVLSEL = 5u; + break; + case SdifVoltage30v: + pstcSdif->SPWRCTL_f.SDBUSVLSEL = 6u; + break; + case SdifVoltage33v: + pstcSdif->SPWRCTL_f.SDBUSVLSEL = 7u; + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Power on SD bus power + ** + ** This function starts power supply on SD bus + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok Power on normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_BusPowerOn( volatile stc_sdifn_t* pstcSdif) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SPWRCTL_f.SDBUSPWR = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Power off SD bus power + ** + ** This function stops power supply on SD bus + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok Power off normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_BusPowerOff( volatile stc_sdifn_t* pstcSdif) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SPWRCTL_f.SDBUSPWR = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Send SD command + ** + ** This function sends command on CMD line + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] pstcConfig Pointer to command structure + ** + ** \retval Ok Command sent normally + ** \retval ErrorInvalidParameter pstcSdif == NULL or pstcConfig == NULL + ******************************************************************************/ +en_result_t Sdif_SendCommand( volatile stc_sdifn_t* pstcSdif, + stc_sdif_cmd_config_t* pstcConfig ) +{ + stc_sdif_scmmd_field_t stcCmd; + + // Clear structure + PDL_ZERO_STRUCT(stcCmd); + + // Check for NULL pointer + if ((NULL == pstcSdif) || (NULL == pstcConfig)) + { + return ErrorInvalidParameter ; + } + + // Set command type + switch (pstcConfig->enCmdType) + { + case SdifCmdNormal: + stcCmd.CMDTYPE = 0u; + break; + case SdifCmdSuspend: + stcCmd.CMDTYPE = 1u; + break; + case SdifCmdResume: + stcCmd.CMDTYPE = 2u; + break; + case SdifCmdAbort: + stcCmd.CMDTYPE = 3u; + break; + default: + return ErrorInvalidParameter ; + } + + // Set data present during the command + stcCmd.DATPRESSEL = ((TRUE == pstcConfig->bDataPresent) ? 1u : 0u); + + // Set command index check + stcCmd.CMDIDXCHKE = ((TRUE == pstcConfig->bCmdIndexCheck) ? 1u : 0u); + + // Set command CRC check + stcCmd.CMDCRCCHKE = ((TRUE == pstcConfig->bCmdCrcCheck) ? 1u : 0u); + + // Set command response type + switch (pstcConfig->enResponseType) + { + case SdifResponseNone: + stcCmd.RESPTYPE = 0u; + break; + case SdifResponse136Bit: + stcCmd.RESPTYPE = 1u; + break; + case SdifResponse48Bit: + stcCmd.RESPTYPE = 2u; + break; + case SdifResponse48BitCheckBusy: + stcCmd.RESPTYPE = 3u; + break; + default: + return ErrorInvalidParameter ; + } + + // Set command index + stcCmd.CMDINDEX = pstcConfig->u8CmdIndex; + + // Auto command setting + switch (pstcConfig->enAutoCmdType) + { + case SdifAutoCmdDisable: + pstcSdif->STRSFMD_f.AUTOCMDEN = 0u; + break; + case SdifAutoCmd12Enable: + pstcSdif->STRSFMD_f.AUTOCMDEN = 1u; + break; + case SdifAutoCmd23Enable: + pstcSdif->STRSFMD_f.AUTOCMDEN = 2u; + break; + default: + return ErrorInvalidParameter ; + } + + // Set augument derectly to hardware register + pstcSdif->SSA1 = pstcConfig->u32Argument; + + // Update command hardware register (Command is sent) + //according to the spec, this register should be only write once. + pstcSdif->SCMMD = *((uint16_t *)&stcCmd); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get SD response + ** + ** This function receives response on CMD line + ** + ** \param [in] pstcSdif SDIF instance + ** \param [out] pu16ResponseData pointer to response data + ** \param [in] u8ResponseRegCount Response register count + ** + ** \retval Ok Response received normally + ** \retval ErrorInvalidParameter pstcSdif == NULL or u8ResponseRegCount > 8u + ******************************************************************************/ +en_result_t Sdif_GetResponse( volatile stc_sdifn_t* pstcSdif, + uint16_t* pu16ResponseData, + uint8_t u8ResponseRegCount) +{ + uint16_t* pu16ResponseBaseAddr; + uint8_t u8i; + + // Check for NULL pointer + if ((NULL == pstcSdif) || (NULL == pu16ResponseData) || (u8ResponseRegCount > 8u)) + { + return ErrorInvalidParameter ; + } + + pu16ResponseBaseAddr = (uint16_t*)&pstcSdif->SRESP0; + + for(u8i=0; u8iSTRSFMD_f.BLCKCNTSEL = ((TRUE == pstcDataConfig->bMultipleBlock) ? 1u : 0u); + + // Set data transfer direction + pstcSdif->STRSFMD_f.DTTRSFDIR = ((TRUE == pstcDataConfig->bRead) ? 1u : 0u); + + // Set block size + pstcSdif->SBSIZE_f.TRSFBLCKSZ = pstcDataConfig->u16BlockSize; + + // Set block count + pstcSdif->SBLCNT = pstcDataConfig->u16BlockCount; + + // Set block count enable + pstcSdif->STRSFMD_f.BLCKCNTEN = ((TRUE == pstcDataConfig->bBlockCountEnable) ? 1u : 0u); + + // Enable DMA or not + pstcSdif->STRSFMD_f.DMAEN = ((TRUE == pstcDataConfig->bEnableDma) ? 1u : 0u); + + // Set descriptor table of ADMA + pstcSdif->SADSA0 = (uint16_t)pstcDataConfig->u32AdmaDespTableAddress; + pstcSdif->SADSA1 = (uint16_t)(pstcDataConfig->u32AdmaDespTableAddress >> 16u); + + // Set data timeout time + if(pstcDataConfig->u8DataTimeout > SdifTimeout_BaseClk_2_27) + { + return ErrorInvalidParameter ; + } + + pstcSdif->STOCTL_f.DTTMOUTVAL = pstcDataConfig->u8DataTimeout; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read data from SD data buffer port + ** + ** This function reads 32-bit data from data buffer + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Data that is read + ******************************************************************************/ +uint32_t Sdif_ReadData( volatile stc_sdifn_t* pstcSdif ) +{ + return pstcSdif->SBUFDP; +} + +/** + ****************************************************************************** + ** \brief Write data to SD data buffer port + ** + ** This function writes 32-bit data to data buffer + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] u32Data Data to be written + ** + ** \retval Ok Data is written normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_WriteData( volatile stc_sdifn_t* pstcSdif, + uint32_t u32Data) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SBUFDP = u32Data; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Stop data transfer during block gap + ** + ** This function is used to stop data trasnfer of multi-block transfer + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok Data stops tranfer normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_StopAtBlockGap( volatile stc_sdifn_t* pstcSdif ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SBLKGPCTL_f.BLCKGSTPREQ = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Restart data transfer + ** + ** This function is used to restart data transfer when transfer is pending + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval Ok Data restarts tranfer normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_RestartTransfer( volatile stc_sdifn_t* pstcSdif ) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SBLKGPCTL_f.CONTREQ = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Poll card insertion status + ** + ** This function checks card is inserted or not + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval TRUE Card is inserted + ** \retval FALSE Card is removed + ******************************************************************************/ +boolean_t Sdif_PollCardInsert( volatile stc_sdifn_t* pstcSdif ) +{ + // Wait until card is stable + while(pstcSdif->SPRSTAT_f.CARDSTB != 1u); + + return (boolean_t)pstcSdif->SPRSTAT_f.CARDINS; +} + +/** + ****************************************************************************** + ** \brief Issue software reset to SD card + ** + ** This function issues software reset all command to SD card + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] enReset Reset type + ** + ** \retval Ok Software reset is done normally + ** \retval ErrorInvalidParameter pstcSdif == NULL + ******************************************************************************/ +en_result_t Sdif_SoftwareReset( volatile stc_sdifn_t* pstcSdif, + en_sdif_reset_t enReset) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + switch (enReset) + { + case SdifResetDataLine: + pstcSdif->SSRST_f.SWRSTDATLN = 1u; + while(0u != pstcSdif->SSRST_f.SWRSTDATLN); // Wait until reset finish + break; + case SdifResetCmdLine: + pstcSdif->SSRST_f.SWRSTCMDLN = 1u; + while(0u != pstcSdif->SSRST_f.SWRSTCMDLN); // Wait until reset finish + break; + case SdifResetAll: + pstcSdif->SSRST_f.SWRSTALL = 1u; + while(0u != pstcSdif->SSRST_f.SWRSTALL); // Wait until reset finish + break; + default: + return ErrorInvalidParameter ; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Check the status of CMD line + ** + ** This function checks whether a commmand wiout data can be sent + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval TRUE Command is ready to send + ** \retval FALSE Command is inhitted to send + ******************************************************************************/ +boolean_t Sdif_CheckCommandInhit( volatile stc_sdifn_t* pstcSdif ) +{ + return (boolean_t)pstcSdif->SPRSTAT_f.CMDINH; +} + +/** + ****************************************************************************** + ** \brief Check the status of DAT line + ** + ** This function checks whether a commmand with data can be sent + ** + ** \param [in] pstcSdif SDIF instance + ** + ** \retval TRUE Command is ready to send + ** \retval FALSE Command is inhitted to send + ******************************************************************************/ +boolean_t Sdif_CheckCommandWithDataInhit( volatile stc_sdifn_t* pstcSdif ) +{ + return (boolean_t)pstcSdif->SPRSTAT_f.CMDDATINH; +} + +/** + ****************************************************************************** + ** \brief Set the wakeup factor + ** + ** This function sets SD host wakeup factors. + ** + ** \param [in] pstcSdif SDIF instance + ** \param [in] bCardRemovalWakeup Whether card removal triggers SD host wakeup + ** \param [in] bCardInsertWakeup Whether card insertion triggers SD host wakeup + ** \param [in] bCardIrqWakeup Whether card interrupt triggers SD host wakeup + ** + ** \retval Ok SD host wakeup factor set normally + ** \retval FALSE Command is inhitted to send + ******************************************************************************/ +en_result_t Sdif_SetWakeupFactor( volatile stc_sdifn_t* pstcSdif, + boolean_t bCardRemovalWakeup, + boolean_t bCardInsertWakeup, + boolean_t bCardIrqWakeup) +{ + // Check for NULL pointer + if (NULL == pstcSdif) + { + return ErrorInvalidParameter ; + } + + pstcSdif->SWKUPCTL_f.WKUPEVNTEN2 = ((TRUE == bCardRemovalWakeup) ? 1u : 0u); + pstcSdif->SWKUPCTL_f.WKUPEVNTEN1 = ((TRUE == bCardInsertWakeup) ? 1u : 0u); + pstcSdif->SWKUPCTL_f.WKUPEVNTEN0 = ((TRUE == bCardIrqWakeup) ? 1u : 0u); + + return Ok; +} + +#endif // #if (defined(PDL_PERIPHERAL_SD_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sdif/sdif.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sdif/sdif.h new file mode 100644 index 0000000000..1db2711789 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/sdif/sdif.h @@ -0,0 +1,560 @@ +/******************************************************************************* +* \file sdif.h +* +* \version 1.20 +* +* \brief Headerfile for SD Card Interface functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + + +#ifndef __SDIF_H__ +#define __SDIF_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_SD_ACTIVE)) + +#if defined (__CC_ARM) + #pragma anon_unions +#endif + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupSDIF SD Card Interface (SDIF) +* \{ +* \defgroup GroupSDIF_Macros Macros +* \defgroup GroupSDIF_Functions Functions +* \defgroup GroupSDIF_GlobalVariables Global Variables +* \defgroup GroupSDIF_DataStructures Data Structures +* \defgroup GroupSDIF_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupSDIF +* \{ +* Use the SDIF peripheral to manage an SD card. SDIF supports SD cards +* compliant with the following specifications:
+* * Part 1 Physical Layer Specification Version 3.01 +* * Part E1 SDIO Specification Version 3.00 +* * Part A2 SD Host Controller Simplified Specification Version 3.00
+* Check the datasheet for your device to determine if SDIF is supported. +* Features supported include: +* * SD bus (SPI bus not supported) +* * 1 or 4-bit data bus +* * Double buffer for transfer (buffer size: 2 KB) +* * Data write protect detection function +* * Card detection function +* * Multiple read/write transfer +* * Transfer data length: 1 byte to 2048 bytes +* * Read Wait Option function +* * Suspend/Resume function +* * Wakeup function +* * Shared bus function +* * Default Speed mode and High Speed mode (other Bus Speed modes not supported) +* * Auto CMD23 supported +* * SDMA +* * ADMA1 +* * MMC 4.41 (sequential commands not supported) +* * MMC boot operation +* \section SectionSDIF_ConfigurationConsideration Configuration Consideration +* The PDL utilities folder has files for SD Cards. To configure an SD Card, +* use the stc_sdcard_config_t structure. Look in sd_cmd.h for the definition +* of this structure. Set the bus width, the clock, whether you are using high +* speed mode, and whether you are using ADMA. The file sd_card.c also has an +* example of configuring the SD host interface. Look at the function SdCardInitHost().
+* To set up the SDIF, that function provides configuration parameters in an +* stc_sdif_config_t structure, such as the speed, 1-bit or 4-bit operation, +* and interrupt handlers. Then call Sdif_Init() to initialize the SD host interface instance.
+* To start the SDIF, call Sdif_EnableInternalClock(). This enables the SD host internal +* clock, which starts the SD host. Sdif_DisableInternalClock() stops the SD host.
+* At runtime use API function calls to: +* * Enable or disable the internal clock and the SD clock +* * Set the clock divider +* * Set the bus width, speed mode, voltage, and power (on or off) +* * Read and write data +* * Get and clear error status +* * Enable and disable interrupts +* +* \section SectionSDIF_MoreInfo More Information +* For more information on the SDIF peripheral, refer to:
+* FM4 Family 32-Bit Microcontroller Peripheral Manual Core Subsystem TRM
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* +*/ + + +/** +* \addtogroup GroupSDIF_Macros +* \{ +*/ +/****************************************************************************** + * Global definitions + ******************************************************************************/ +#define stc_sdifn_t FM_SDIF_TypeDef +#define SDIF0 (*((volatile stc_sdifn_t *) FM_SDIF_BASE)) + +#define SDIF_INSTANCE_COUNT \ + (uint8_t)(PDL_PERIPHERAL_ENABLE_SD0 == PDL_ON) + +/** \} GroupSDIF_Macros */ + +/** +* \addtogroup GroupSDIF_Types +* \{ +*/ +/****************************************************************************** + * Global type definitions + ******************************************************************************/ +/** + ****************************************************************************** + ** \brief SD command types + ******************************************************************************/ +typedef enum en_sdif_cmd_type +{ + SdifCmdAbort = 0u, ///< CMD12, CMD52 for writing "I/O Abort" in CCCR + SdifCmdResume = 1u, ///< CMD52 for writing "Function Select" in CCCR + SdifCmdSuspend = 2u, ///< CMD52 for writing "Bus Suspend" in CCCR + SdifCmdNormal = 3u, ///< Other commands + +}en_sdif_cmd_type_t; + +/** + ****************************************************************************** + ** \brief SDIF response types + ******************************************************************************/ +typedef enum en_sdif_response_type +{ + SdifResponseNone = 0u, ///< No Response + SdifResponse136Bit = 1u, ///< Response Length 136 + SdifResponse48Bit = 2u, ///< Response Length 48 + SdifResponse48BitCheckBusy = 3u, ///< Response Length 48 check Busy after response + +}en_sdif_response_type_t; + +/** + ****************************************************************************** + ** \brief SD data timeout time + ******************************************************************************/ +typedef enum en_sd_data_timeout +{ + SdifTimeout_BaseClk_2_13 = 0u, ///< Timeout time: Base clock*2^13 + SdifTimeout_BaseClk_2_14 = 1u, ///< Timeout time: Base clock*2^14 + SdifTimeout_BaseClk_2_15 = 2u, ///< Timeout time: Base clock*2^15 + SdifTimeout_BaseClk_2_16 = 3u, ///< Timeout time: Base clock*2^16 + SdifTimeout_BaseClk_2_17 = 4u, ///< Timeout time: Base clock*2^17 + SdifTimeout_BaseClk_2_18 = 5u, ///< Timeout time: Base clock*2^18 + SdifTimeout_BaseClk_2_19 = 6u, ///< Timeout time: Base clock*2^19 + SdifTimeout_BaseClk_2_20 = 7u, ///< Timeout time: Base clock*2^20 + SdifTimeout_BaseClk_2_21 = 8u, ///< Timeout time: Base clock*2^21 + SdifTimeout_BaseClk_2_22 = 9u, ///< Timeout time: Base clock*2^22 + SdifTimeout_BaseClk_2_23 = 10u, ///< Timeout time: Base clock*2^23 + SdifTimeout_BaseClk_2_24 = 11u, ///< Timeout time: Base clock*2^24 + SdifTimeout_BaseClk_2_25 = 12u, ///< Timeout time: Base clock*2^25 + SdifTimeout_BaseClk_2_26 = 13u, ///< Timeout time: Base clock*2^26 + SdifTimeout_BaseClk_2_27 = 14u, ///< Timeout time: Base clock*2^27 + +}en_sdif_data_timeout_t; + +/** + ****************************************************************************** + ** \brief SDIF auto command enable selection + ******************************************************************************/ +typedef enum en_sdif_auto_cmd +{ + SdifAutoCmdDisable = 0u, ///< Auto command disable + SdifAutoCmd12Enable = 1u, ///< Auto command 12 enable + SdifAutoCmd23Enable = 2u, ///< Auto command 23 enable + +}en_sdif_auto_cmd_t; + +/** + ****************************************************************************** + ** \brief SDIF voltage selection + ******************************************************************************/ +typedef enum en_sdif_voltage_sel +{ + SdifVoltage18v = 0u, ///< SD bus voltge: 1.8V + SdifVoltage30v = 1u, ///< SD bus voltge: 3.0V + SdifVoltage33v = 2u, ///< SD bus voltge: 3.3V + +}en_sdif_voltage_sel_t; + +/** + ****************************************************************************** + ** \brief SDIF software reset types + ******************************************************************************/ +typedef enum en_sdif_reset +{ + SdifResetDataLine = 0u, ///< Only reset data circuit + SdifResetCmdLine = 1u, ///< Only reset command circuit + SdifResetAll = 2u, ///< Reset all SDIF host controller + +}en_sdif_reset_t; + +/// Enumeration to define an index for each enabled SDIF instance +typedef enum en_sdif_instance_index +{ + #if (PDL_PERIPHERAL_ENABLE_SD0 == PDL_ON) + SdifInstanceIndexSdif0, + #endif + SdifInstanceIndexMax +} en_sdif_instance_index_t; + +/** + ****************************************************************************** + ** \brief SDIF error interrupt types + ******************************************************************************/ +typedef enum en_sdif_err_irq_sel +{ + SdifCmdTimeoutErrIrq = 0u, ///< Command timeout error + SdifCmdCrcErrIrq = 1u, ///< Command CRC error + SdifCmdEndBitErrIrq = 2u, ///< Command end bit error + SdifCmdIndexErrIrq = 3u, ///< Command index error + SdifDataTimeoutErrIrq = 4u, ///< Data timeout error + SdifDataCrcErrIrq = 5u, ///< Data CRC error + SdifDataEndBitErrIrq = 6u, ///< Data end bit error + SdifCurrentLimitErrIrq = 7u, ///< Current limit error + SdifAutoCmdErrIrq = 8u, ///< Auto command error + SdifAdmaErrIrq = 9u, ///< ADMA error + SdifTuningErrIrq = 10u, ///< Tuning error + +}en_sdif_err_irq_sel_t; + +/** + ****************************************************************************** + ** \brief SDIF normal interrupt types + ******************************************************************************/ +typedef enum en_sdif_normal_irq_sel +{ + SdifCommandCompleteIrq = 0u, ///< Command complete + SdifTransferCompleteIrq = 1u, ///< Transfer complete + SdifBlockGapEventIrq = 2u, ///< Block gap event + SdifDmaIrq = 3u, ///< DMA interrupt + SdifBufferWriteReadyIrq = 4u, ///< Buffer write ready + SdifBufferReadReadyIrq = 5u, ///< Buffer read ready + SdifCardInsertionIrq = 6u, ///< Card insertion + SdifCardRemovalIrq = 7u, ///< Card removal + SdifCardIrq = 8u, ///< Card interrupt + +}en_sdif_normal_irq_sel_t; + +/** \}GroupSDIF_Types */ + +/** +* \addtogroup GroupSDIF_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief SDIF error status types + ******************************************************************************/ +typedef struct stc_sdif_err_irq +{ + union + { + uint16_t u16ErrStatus; ///< 16-bit error status + struct /* stcErrIrqStatus */ + { + uint16_t CmdTimeoutErr : 1; ///< Command timeout error + uint16_t CmdCrcErr : 1; ///< Command CRC error + uint16_t CmdEndBitErr : 1; ///< Command end bit error + uint16_t CmdIndexErr : 1; ///< Command index error + uint16_t DataTimeoutErr : 1; ///< Data timeout error + uint16_t DataCrcErr : 1; ///< Data CRC error + uint16_t DataEndBitErr : 1; ///< Data end bit error + uint16_t CurrentLimitErr : 1; ///< Current limit error + uint16_t AutoCmdErr : 1; ///< Auto command error + uint16_t AdmaErr : 1; ///< ADMA error + uint16_t TuningErr : 1; ///< Tuning error + uint16_t Reserved : 5; ///< Reseverd + }; + }; + +} stc_sdif_err_irq_status_t, stc_sdif_err_irq_en_t; + + +/** + ****************************************************************************** + ** \brief SDIF error status callback functions + ******************************************************************************/ +typedef struct stc_sdif_err_irq_cb +{ + func_ptr_t pfnCmdTimeoutErrIrqCb; ///< Pointer to command timeout error interrupt callback function + func_ptr_t pfnCmdCrcErrIrqCb; ///< Pointer to command CRC error interrupt callback function + func_ptr_t pfnCmdEndBitErrIrqCb; ///< Pointer to command end bit error interrupt callback function + func_ptr_t pfnCmdIndexErrIrqCb; ///< Pointer to command index error interrupt callback function + func_ptr_t pfnDataTimeoutErrIrqCb; ///< Pointer to data timeout error interrupt callback function + func_ptr_t pfnDataEndBitErrIrqCb; ///< Pointer to data end bit error interrupt callback function + func_ptr_t pfnDataCrcErrIrqCb; ///< Pointer to data CRC error interrupt callback function + func_ptr_t pfnCurrentLimitErrIrqCb; ///< Pointer to current limit error interrupt callback function + func_ptr_t pfnAutoCmdErrIrqCb; ///< Pointer to command error interrupt callback function + func_ptr_t pfnAdmaErrIrqCb; ///< Pointer to ADMA error interrupt callback function + func_ptr_t pfnTuningErrIrqCb; ///< Pointer to tuning error interrupt callback function + +}stc_sdif_err_irq_cb_t; + +/** + ****************************************************************************** + ** \brief SDIF normal status types + ******************************************************************************/ +typedef struct stc_sdif_normal_irq +{ + union + { + uint16_t u16NormalStatus; ///< 16-bit normal status + struct /*stcNormalIrqStatus */ + { + uint16_t CommandComplete : 1; ///< Command complete + uint16_t TransferComplete : 1; ///< Transfer complete + uint16_t BlockGapEvent : 1; ///< Block gap event + uint16_t DmaIrq : 1; ///< DMA interrupt + uint16_t BufferWriteReady : 1; ///< Buffer write ready + uint16_t BufferReadReady : 1; ///< Buffer read ready + uint16_t CardInsertion : 1; ///< Card insertion + uint16_t CardRemoval : 1; ///< Card removal + uint16_t CardIrq : 1; ///< Card interrupt + uint16_t Reserved0 : 7; ///< Reserved bits + }; + }; + +}stc_sdif_normal_irq_status_t, stc_sdif_normal_irq_en_t; + +/** + ****************************************************************************** + ** \brief SDIF error status callback functions + ******************************************************************************/ +typedef struct stc_sdif_normal_irq_cb +{ + func_ptr_t pfnCommandCompleteIrqCb; ///< Pointer to command complete callback function + func_ptr_t pfnTransferCompleteIrqCb; ///< Pointer to transfer complete callback function + func_ptr_t pfnBlockGapIrqCb; ///< Pointer to Block gap callback function + func_ptr_t pfnDmaIrqCb; ///< Pointer to DMA interrupt callback function + func_ptr_t pfnBufferWriteReadyIrqCb; ///< Pointer to buffer write ready callback function + func_ptr_t pfnBufferReadReadyIrqCb; ///< Pointer to buffer read ready callback function + func_ptr_t pfnCardInsertIrqCb; ///< Pointer to card insertion callback function + func_ptr_t pfnCardRemovalIrqCb; ///< Pointer to card removal callback function + func_ptr_t pfnCardIrqCb; ///< Pointer to card interrupt callback function + +}stc_sdif_normal_irq_cb_t; + +/** + ****************************************************************************** + ** \brief SDIF Auto Command error status + ******************************************************************************/ +typedef struct stc_sdif_auto_cmd_err +{ + union + { + uint16_t u16AutoCmdErr; + struct /* stcAutoCmdErr */ + { + uint16_t SdifAutoCmd12NotExecuted : 1; ///< Host Controller cannot issue Auto CMD12 to stop memory multiple block data transfer due to some error + uint16_t SdifAutoCmdTimeoutErr : 1; ///< No response is returned within 64 SDCLK cycles from the end bit of command. + uint16_t SdifAutoCmdCrcErr : 1; ///< This bit is set when detecting a CRC error in the command response. + uint16_t SdifAutoCmdEndBitErr : 1; ///< Detecting that the end bit of command response is 0. + uint16_t SdifAutoCmdIndexErr : 1; ///< Command Index error occurs in response to a command. + uint16_t Reserved0 : 2; ///< Reserved + uint16_t SdifCmdNotIssuedByAutoCmd12 : 1; ///< CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. + uint16_t Reserved1 : 8; ///< Reserved + }; + }; + +}stc_sdif_auto_cmd_err_t; + +/** + ****************************************************************************** + ** \brief SDIF configuration. + ******************************************************************************/ +typedef struct stc_sdif_config +{ + boolean_t bSelAdma; ///< TRUE: Select ADMA, FALSE: don't select ADMA + boolean_t bEnableHighSpeed; ///< TRUE: Enable high speed mode, FALSE: Disable high speed mode + boolean_t bEnable4BitMode; ///< TRUE: Use 4-bit mode, FALSE: Use 1-bit mode +#if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) + stc_sdif_normal_irq_en_t* pstcNormalIrqEn; ///< Pointer to normal interrupt enable structure + stc_sdif_normal_irq_cb_t* pstcNormalIrqCb; ///< Pointer to normal interrupt callback function structure + stc_sdif_err_irq_en_t* pstcErrIrqEn; ///< Pointer to error interrupt enable structure + stc_sdif_err_irq_cb_t* pstcErrIrqCb; ///< Pointer to error interrupt callback structure + boolean_t bTouchNvic; ///< TRUE: Enable NVIC, FALSE: Disable NVIC +#endif +}stc_sdif_config_t; + +/** + ****************************************************************************** + ** \brief SDIF command configuration. + ******************************************************************************/ +typedef struct stc_sdif_cmd_config +{ + uint8_t u8CmdIndex; ///< Command index + uint32_t u32Argument; ///< The argment of command + en_sdif_cmd_type_t enCmdType; ///< Command type + boolean_t bDataPresent; ///< TRUE: Data is present and shall be transferred using the DAT line, FALSE: Commands using only CMD line + boolean_t bCmdIndexCheck; ///< TRUE: Host Controller shall check the Index field in the response to see if it has the same value as the command index. If it is not, it is reported as a Command Index Error, FALSE: the Index field is not checked. + boolean_t bCmdCrcCheck; ///< TRUE: Host Controller shall check the CRC field in the response. If an error is detected, it is reported as a Command CRC Error. FALSE: the CRC field is not checked. The position of CRC field is determined according to the length of the response. + en_sdif_response_type_t enResponseType; ///< Response type, see #en_adc_timer_select_t for details + en_sdif_auto_cmd_t enAutoCmdType; ///< Auto command enable selection, see #en_sdif_auto_cmd_t for details + +}stc_sdif_cmd_config_t; + +/** + ****************************************************************************** + ** \brief SDIF data transfer configuration. + ******************************************************************************/ +typedef struct stc_sdif_data_config +{ + boolean_t bMultipleBlock; ///< TRUE: use multiple block transfer, FALSE: use single block transfer + boolean_t bRead; ///< TRUE: Read, FALSE: write + uint16_t u16BlockSize; ///< Block size + uint16_t u16BlockCount; ///< Block count + boolean_t bBlockCountEnable; ///< Block count enable setting + boolean_t bEnableDma; ///< TRUE: use ADMA, FALSE: don't use ADMA + uint32_t u32AdmaDespTableAddress; ///< The address of ADMA descriptor table + uint8_t u8DataTimeout; ///< see #en_sdif_data_timeout_t for details + +}stc_sdif_data_config_t; + +typedef struct stc_sdif_intern_data +{ + stc_sdif_normal_irq_cb_t stcNormalIrqCb; + stc_sdif_err_irq_cb_t stcErrIrqCb; + +}stc_sdif_intern_data_t; + +/// SDIF instance data type +typedef struct stc_sdif_instance_data +{ + volatile stc_sdifn_t* pstcInstance; ///< pointer to registers of an instance + stc_sdif_intern_data_t stcInternData; ///< module internal data of instance +} stc_sdif_instance_data_t; + +/** \} GroupSDIF_DataStructures */ + +/** +* \addtogroup GroupSDIF_GlobalVariables +* \{ +*/ + +/******************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/******************************************************************************/ +/// Look-up table for all enabled SD instances and their internal data +extern stc_sdif_instance_data_t m_astcSdifInstanceDataLut[SDIF_INSTANCE_COUNT]; + +/** \} GroupSDIF_GlobalVariables */ + +/** +* \addtogroup GroupSDIF_Functions +* \{ +*/ +/******************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_SD0 == PDL_ON) +/* Int Enable/Disable */ +en_result_t Sdif_EnableErrIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_err_irq_sel_t enIrqSel); +en_result_t Sdif_DisableErrIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_err_irq_sel_t enIrqSel); +en_result_t Sdif_EnableNormalIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_normal_irq_sel_t enIrqSel); +en_result_t Sdif_DisableNormalIrq( volatile stc_sdifn_t* pstcSdif, + en_sdif_normal_irq_sel_t enIrqSel); +/* SD IRQ */ +void SdifIrqHandler( volatile stc_sdifn_t* pstcSdif, + stc_sdif_intern_data_t* pstcSdifInternData ); +#endif + +en_result_t Sdif_Init( volatile stc_sdifn_t* pstcSdif, + const stc_sdif_config_t* pstcConfig ); +en_result_t Sdif_DeInit( volatile stc_sdifn_t* pstcSdif, + boolean_t bTouchIrq, + boolean_t bTouchIrqCb, + boolean_t bTouchNvic); +en_result_t Sdif_EnableInternalClock( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_DisableInternalClock( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_EnableSdclk( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_DisableSdclk( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_SetClkDiv( volatile stc_sdifn_t* pstcSdif, uint16_t u16Div); +en_result_t Sdif_SetBusWidth( volatile stc_sdifn_t* pstcSdif, + boolean_t bEnable4BitMode); +en_result_t Sdif_SetBusSpeedMode( volatile stc_sdifn_t* pstcSdif, + boolean_t bEnableHighSpeedMode); +en_result_t Sdif_SelBusVoltage( volatile stc_sdifn_t* pstcSdif, + en_sdif_voltage_sel_t enVoltage); +en_result_t Sdif_BusPowerOn( volatile stc_sdifn_t* pstcSdif); +en_result_t Sdif_BusPowerOff( volatile stc_sdifn_t* pstcSdif); + +en_result_t Sdif_SendCommand( volatile stc_sdifn_t* pstcSdif, + stc_sdif_cmd_config_t* pstcConfig ); + +en_result_t Sdif_GetResponse( volatile stc_sdifn_t* pstcSdif, + uint16_t* pu16ResponseData, + uint8_t u8ResponseRegCount); + +en_result_t Sdif_InitDataTransfer( volatile stc_sdifn_t* pstcSdif, + stc_sdif_data_config_t* pstcDataConfig); + +uint32_t Sdif_ReadData( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_WriteData( volatile stc_sdifn_t* pstcSdif, + uint32_t u32Data); +en_result_t Sdif_StopAtBlockGap( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_RestartTransfer( volatile stc_sdifn_t* pstcSdif ); + +en_result_t Sdif_GetErrStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_err_irq_status_t* pstcStatus); +en_result_t Sdif_ClrErrStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_err_irq_status_t* pstcStatus); +en_result_t Sdif_GetNormalStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_normal_irq_status_t* pstcStatus); +en_result_t Sdif_ClrNormalStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_normal_irq_status_t* pstcStatus); +en_result_t Sdif_GetAutoCommandErrStatus( volatile stc_sdifn_t* pstcSdif, + stc_sdif_auto_cmd_err_t* pstcStatus); +boolean_t Sdif_CheckCommandInhit( volatile stc_sdifn_t* pstcSdif ); +boolean_t Sdif_CheckCommandWithDataInhit( volatile stc_sdifn_t* pstcSdif ); +boolean_t Sdif_PollCardInsert( volatile stc_sdifn_t* pstcSdif ); +en_result_t Sdif_SoftwareReset( volatile stc_sdifn_t* pstcSdif, + en_sdif_reset_t enReset); +en_result_t Sdif_SetWakeupFactor( volatile stc_sdifn_t* pstcSdif, + boolean_t bCardRemovalWakeup, + boolean_t bCardInsertWakeup, + boolean_t bCardIrqWakeup); + +/** \} GroupSDIF_Functions */ +/** \} GroupSDIF */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_SDIF_ACTIVE)) + +#endif /* __SDIF_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.c new file mode 100644 index 0000000000..b1284d46c6 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.c @@ -0,0 +1,129 @@ +/******************************************************************************* +* \file uid.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the UID +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "uid/uid.h" + +#if (defined(PDL_PERIPHERAL_UID_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Read Unique ID registers as is + ** + ** This function reads out UIDR0 and UIDR1 as is without any shift to + ** a pointered structure of the type stc_unique_id_t. + ** Reserved bits are masked to '0'. + ** + ** \param [out] pstcUniqueId Pointer to the Unique ID structure + ** + ** \retval Ok Unique ID successfully written + ** \retval ErrorInvalidParameter pstcUniqueId == NULL + ******************************************************************************/ +en_result_t Uid_ReadUniqueId(stc_unique_id_t *pstcUniqueId) +{ + if (NULL == pstcUniqueId) + { + return ErrorInvalidParameter; + } + + pstcUniqueId->u32Uidr0 = (0xFFFFFFF0ul & (FM_UNIQUE_ID->UIDR0)); + pstcUniqueId->u32Uidr1 = (0x00001FFFul & (FM_UNIQUE_ID->UIDR1)); + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read Unique ID registers 0 and shifts it by 4 (LSB aligned) + ** + ** This function reads out UIDR0 and aligns the value to the LSB by shifting + ** by 4. + ** + ** \return uint32_t Unique ID 0 >> 4 + ******************************************************************************/ +uint32_t Uid_ReadUniqueId0(void) +{ + return ((FM_UNIQUE_ID->UIDR0) >> 4u); +} + +/** + ****************************************************************************** + ** \brief Read Unique ID registers 1 and masks the upper 19 bits to '0' + ** + ** This function reads out UIDR1 and masks the upper 19 bits to '0' + ** + ** \return uint32_t Unique ID 1 & 0x00001FFF + ******************************************************************************/ +uint32_t Uid_ReadUniqueId1(void) +{ + return ((FM_UNIQUE_ID->UIDR1) & 0x00001FFFul); +} + +/** + ****************************************************************************** + ** \brief Read Unique ID registers 0 and 1 and merge it LSB aligned to a 64 bit + ** value + ** + ** \return uint64_t Complete unique ID LSB aligned + ******************************************************************************/ +uint64_t Uid_ReadUniqueId64(void) +{ + uint64_t u64UniqueIdMsw; + + // Left shift by 60 bit in two steps + u64UniqueIdMsw = (((FM_UNIQUE_ID->UIDR1) & 0x00001FFFul) << 16ul); + u64UniqueIdMsw <<= 12ul; + + u64UniqueIdMsw |= ((FM_UNIQUE_ID->UIDR0) >> 4ul); + return u64UniqueIdMsw; +} + +#endif // #if (defined(PDL_PERIPHERAL_UID_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.h new file mode 100644 index 0000000000..41884916f2 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/uid/uid.h @@ -0,0 +1,139 @@ +/******************************************************************************* +* \file uid.h +* +* \version 1.20 +* +* \brief Headerfile for UID functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __UID_H__ +#define __UID_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_UID_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupUID Unique ID Register (UID) +* \{ +* \defgroup GroupUID_Functions Functions +* \defgroup GroupUID_DataStructures Data Structures +* \} +*/ + +/** +* \addtogroup GroupUID +* \{ +* FM family microcontrollers have two 32-bit registers that store an ID number +* unique to each individual chip. You can read this value; you cannot set it. +* You can use this value as a unique ID for any purpose. For example, you might +* read the number the first time you install your software, and save it as a serial number. +* You can then check to ensure that the software is running on the same processor on which it was +* installed.
+* Unique ID 0 register uses the upper 28 bits. Unique ID 1 uses the lower 13 bits. All other bits are reserved.
+* These values will not change due to reset or power on/off. +* \section SectionUID_ConfigurationConsideration Configuration Consideration +* There is no configuration required. You can read the value of one, the other, or both registers. +* Uid_ReadUniqueId() reads out the Unique ID to a pointered structure of the +* type #stc_unique_id_t. Reserved bits are masked to zero, but the results are not aligned to least significant bit (LSB).
+* Uid_ReadUniqueId0() reads out the Unique ID 0 +* register and aligns the result to the LSB.
+* Uid_ReadUniqueId1() reads out the +* Unique ID 1 register and masks reserved bits to '0'.
+* Uid_ReadUniqueId64() reads both registers as a 64-bit value, aligns them +* to LSB, and masks out reserved bits to '0'. +* +* \section SectionUID_MoreInfo More Information +* For more information on the UID peripheral, refer to:
+* FM0+ Peripheral Manual - Core Subsystem TRM.pdf
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/** +* \addtogroup GroupUID_DataStructures +* \{ +*/ + +/******************************************************************************/ +/* Global type definitions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief PDL structure of Unique ID register set + ******************************************************************************/ + typedef struct stc_unique_id + { + uint32_t u32Uidr0; + uint32_t u32Uidr1; + } stc_unique_id_t; + +/** \} GroupUID_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + + +/** +* \addtogroup GroupUID_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ + +en_result_t Uid_ReadUniqueId(stc_unique_id_t *pstcUniqueId); + +uint32_t Uid_ReadUniqueId0(void); + +uint32_t Uid_ReadUniqueId1(void); + +uint64_t Uid_ReadUniqueId64(void); + +/** \} GroupUID_Functions */ +/** \} GroupUID */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(PDL_PERIPHERAL_UID_ACTIVE)) + +#endif /* __UID_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.c new file mode 100644 index 0000000000..2b8dd6d450 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.c @@ -0,0 +1,2969 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usb.c + ** + ** A detailed description is available at + ** @link UsbGroup USB Module description @endlink + ** + ** History: + ** - 2012-08-28 2.0 MSc First version (starting at version 2.0) + ** - 2012-10-02 2.1 MSc use of external interrupts without L3 implemented + ** - 2012-11-13 2.2 MSc Some problems while switching from Host to Device fixed + ** - 2013-01-31 2.3 MSc DMA added + ** - 2013-05-07 2.4 MSc Minor optimizations + ** - 2013-06-04 2.5 MSc FM4 support added + ** - 2013-09-23 2.6 MSc FM4 PDL support added + ** - 2013-11-29 2.7 MSc PDL adjustments done + ** - 2014-02-28 2.8 MSc Fixes for FM4 (IRQ naming, mcu headerfile typedef) + ** Fixes in SwitchUsb Routine + ** - 2014-05-27 2.9 MSc IRQ double definition with use of PDL > V1.0 solved + ** - 2014-09-04 3.0 MSc Device Mass Storage, USB Host Printer & NDIS added + ** FM4 type 3 added + ** - 2014-10-31 3.1 MSc Usb_OsTickHandle corrected to run USB without IRQs + ** - 2015-05-05 3.2 MSc Corrected wrong initialization behaviour for device / host enable + ** in Usb_Configure + ** - 2015-05-14 3.3 MSCH Moved unnecessary "old" stuff to USB legacy + ** Better timeout handling added + ** - 2015-05-29 3.4 MSCH Added new bit manipulation macros to improve EPnS access + ** - USBREG_BITBAND_ADDRESS + ** - USBREG_BIT_SET + ** - USBREG_BIT_CLEAR + ** - USBREG_BIT_ISSET + ** added better data overflow handling + ** added support for FM0P with USB + ** - 2015-06-29 3.5 MSCH Added more IRQ handles + ** - 2015-08-18 3.6 MSCH Added more IRQ handles + ** + ******************************************************************************/ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#define __USB_C__ 1 +#include "usb.h" +#include "usbethernetclock.h" + +#if ((FM_PERIPHERAL_ENABLE_USB0 == ON) || (FM_PERIPHERAL_ENABLE_USB1 == ON)) + +/** + ****************************************************************************** + ** \ingroup UsbGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +#if (FM_PERIPHERAL_ENABLE_USB0 == ON) + #if !defined(USB0) + #error USB0 is not existing in the MCUs header file, maybe this MCU does not support USB, please change L3_PERIPHERAL_ENABLE_USB0 + #endif +#endif + +#if (FM_PERIPHERAL_ENABLE_USB1 == ON) + #if !defined(USB1) + #error USB1 is not existing in the MCUs header file, maybe this MCU does not support more than one USB, please change L3_PERIPHERAL_ENABLE_USB1 + #endif +#endif + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +static boolean_t UsbInitDone = FALSE; +static volatile boolean_t bUsbNeedsOsTick = FALSE; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +static stc_usb_intern_data_t* UsbGetInternDataPtr(stc_usbn_t* pstcUsb); +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + static en_result_t Usb_InitDeviceMode(stc_usbn_t* pstcUsb); + static en_result_t Usb_DeinitDeviceMode(stc_usbn_t* pstcUsb); +#endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) */ +#if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + static en_result_t Usb_InitHostMode(stc_usbn_t* pstcUsb); + static en_result_t Usb_DeinitHostMode(stc_usbn_t* pstcUsb); +#endif /* (FM_PERIPHERAL_USB_HOST_ENABLED == ON) */ +static void Usb_TimeoutHandler(stc_usbn_t* pstcUsb); +extern void UsbHost_DisconnectionCallback(stc_usbn_t* pstcUsb); + +/// Macro to return the number of enabled USB instances +//#define USB_INSTANCE_COUNT (uint32_t)(sizeof(m_astcUsbInstanceDataLut) / sizeof(m_astcUsbInstanceDataLut[0])) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled USB instances and their internal data +stc_usbn_instance_data_t m_astcUsbInstanceDataLut[] = +{ + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + { &USB0, // pstcInstance + // [andreika]: gcc fix + {0} // stcInternData (not initialized yet) + }, + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + { &USB1, // pstcInstance + // [andreika]: gcc fix + {0} // stcInternData (not initialized yet) + }, + #endif +}; + +#if USB_USES_DMA == ON +#define USB_DMA_INSTANCE_COUNT (uint32_t)(sizeof(astcUsbDma) / sizeof(astcUsbDma[0])) +/// DMA table for all enabled DMA instances and their internal data +stc_usb_dma_t astcUsbDma[] = +{ +#if USB_USES_DMA_0 == ON + { FALSE, // This USB DMA currently not active + DMAC0_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA0), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB0), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA0), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA0) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_1 == ON + { FALSE, // This USB DMA currently not active + DMAC1_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA1), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB1), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA1), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA1) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_2 == ON + { FALSE, // This USB DMA currently not active + DMAC0_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA2), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB2), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA2), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA2) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_3 == ON + { FALSE, // This USB DMA currently not active + DMAC3_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA3), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB3), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA3), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA3) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_4 == ON + { FALSE, // This USB DMA currently not active + DMAC4_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA4), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB4), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA4), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA4) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_5 == ON + { FALSE, // This USB DMA currently not active + DMAC5_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA5), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB5), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA5), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA5) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_6 == ON + { FALSE, // This USB DMA currently not active + DMAC6_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA6), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB6), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA6), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA6) // DMACDA register of this DMA channel + }, +#endif +#if USB_USES_DMA_7 == ON + { FALSE, // This USB DMA currently not active + DMAC7_IRQn, // IRQ of this DMA channel currently not active + NULL, // Currently used with no enpoint handle + &(FM3_DMAC->DMACA7), // DMACA register of this DMA channel + &(FM3_DMAC->DMACB7), // DMACB register of this DMA channel + &(FM3_DMAC->DMACSA7), // DMACSA register of this DMA channel + &(FM3_DMAC->DMACDA7) // DMACDA register of this DMA channel + }, +#endif +}; +#endif +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain USB instance. + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_usb_intern_data_t* UsbGetInternDataPtr(stc_usbn_t* pstcUsb) +{ + volatile uint32_t u32Instance; + + for (u32Instance = 0; u32Instance < USB_INSTANCE_COUNT; u32Instance++) + { + if ((uint32_t)pstcUsb == (uint32_t)(m_astcUsbInstanceDataLut[u32Instance].pstcInstance)) + { + return &m_astcUsbInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + + + +/** + ****************************************************************************** + ** \brief Device dependent initialization of interrupts according CMSIS with + ** level defined in l3.h + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return Ok Successful initialization + ** + ******************************************************************************/ +en_result_t Usb_InitIrq(stc_usbn_t* pstcUsb) +{ + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0)) && ((USB0_DEVICE_IRQ_ENABLED == ON) || (USB0_HOST_IRQ_ENABLED == ON))) + if (pstcUsb == &USB0) + { + // USB0 interrupt settings + USBDBG("INIT ISR\n"); + #if defined(IRQ_USB0_F_ED123_AVAILABLE) && \ + defined(IRQ_USB0_F_ED450I_AVAILABLE) &&\ + defined(IRQ_USB0_F_ED0O_ST_AVAILABLE) + + NVIC_ClearPendingIRQ(USB0_F_ED123_IRQn); + NVIC_EnableIRQ(USB0_F_ED123_IRQn); + NVIC_SetPriority(USB0_F_ED123_IRQn,IRQ_LEVEL_USB0); + + NVIC_ClearPendingIRQ(USB0_F_ED450I_IRQn); + NVIC_EnableIRQ(USB0_F_ED450I_IRQn); + NVIC_SetPriority(USB0_F_ED450I_IRQn,IRQ_LEVEL_USB0); + + NVIC_ClearPendingIRQ(USB0_F_ED0O_ST_IRQn); + NVIC_EnableIRQ(USB0_F_ED0O_ST_IRQn); + NVIC_SetPriority(USB0_F_ED0O_ST_IRQn,IRQ_LEVEL_USB0); + + NVIC_ClearPendingIRQ(USBLIB_USB0_DEVHOST_IRQn); + NVIC_EnableIRQ(USBLIB_USB0_DEVHOST_IRQn); + NVIC_SetPriority(USBLIB_USB0_DEVHOST_IRQn,IRQ_LEVEL_USB0); + + #else + NVIC_ClearPendingIRQ(USBLIB_USB0_IRQn); + NVIC_EnableIRQ(USBLIB_USB0_IRQn); + NVIC_SetPriority(USBLIB_USB0_IRQn,IRQ_LEVEL_USB0); + #endif + NVIC_ClearPendingIRQ(USBLIB_USB0_DEVHOST_IRQn); + NVIC_EnableIRQ(USBLIB_USB0_DEVHOST_IRQn); + NVIC_SetPriority(USBLIB_USB0_DEVHOST_IRQn,IRQ_LEVEL_USB0); + } + #endif + + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1)) && ((USB1_DEVICE_IRQ_ENABLED == ON) || (USB1_HOST_IRQ_ENABLED == ON))) + if (pstcUsb == &USB1) + { + // USB1 interrupt settings + NVIC_ClearPendingIRQ(USBLIB_USB1_IRQn); + NVIC_EnableIRQ(USBLIB_USB1_IRQn); + NVIC_SetPriority(USBLIB_USB1_IRQn,IRQ_LEVEL_USB1); + + NVIC_ClearPendingIRQ(USBLIB_USB1_DEVHOST_IRQn); + NVIC_EnableIRQ(USBLIB_USB1_DEVHOST_IRQn); + NVIC_SetPriority(USBLIB_USB1_DEVHOST_IRQn,IRQ_LEVEL_USB1); + } + #endif + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Device dependent deinitialization of interrupts according CMSIS with + ** level defined in l3.h + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return Ok Successful deinitialization + ** + ******************************************************************************/ +en_result_t Usb_DeinitIrq(stc_usbn_t* pstcUsb) +{ + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + if (pstcUsb == &USB0) + { + // USB0 interrupt settings + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + #if defined(IRQ_USB0_F_ED123_AVAILABLE) && \ + defined(IRQ_USB0_F_ED450I_AVAILABLE) &&\ + defined(IRQ_USB0_F_ED0O_ST_AVAILABLE) + + NVIC_ClearPendingIRQ(USB0_F_ED123_IRQn); + NVIC_DisableIRQ(USB0_F_ED123_IRQn); + NVIC_SetPriority(USB0_F_ED123_IRQn,15); + + NVIC_ClearPendingIRQ(USB0_F_ED450I_IRQn); + NVIC_DisableIRQ(USB0_F_ED450I_IRQn); + NVIC_SetPriority(USB0_F_ED450I_IRQn,15); + + NVIC_ClearPendingIRQ(USB0_F_ED0O_ST_IRQn); + NVIC_DisableIRQ(USB0_F_ED0O_ST_IRQn); + NVIC_SetPriority(USB0_F_ED0O_ST_IRQn,15); + #else + NVIC_ClearPendingIRQ(USBLIB_USB0_IRQn); + NVIC_DisableIRQ(USBLIB_USB0_IRQn); + NVIC_SetPriority(USBLIB_USB0_IRQn,15); + #endif + #endif + + NVIC_ClearPendingIRQ(USBLIB_USB0_DEVHOST_IRQn); + NVIC_DisableIRQ(USBLIB_USB0_DEVHOST_IRQn); + NVIC_SetPriority(USBLIB_USB0_DEVHOST_IRQn,15); + } + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + if (pstcUsb == &USB1) + { + // USB1 interrupt settings + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + NVIC_ClearPendingIRQ(USBLIB_USB1_IRQn); + NVIC_DisableIRQ(USBLIB_USB1_IRQn); + NVIC_SetPriority(USBLIB_USB1_IRQn,15); + #endif + + NVIC_ClearPendingIRQ(USBLIB_USB1_DEVHOST_IRQn); + NVIC_DisableIRQ(USBLIB_USB1_DEVHOST_IRQn); + NVIC_SetPriority(USBLIB_USB1_DEVHOST_IRQn,15); + } + #endif + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Initialize USB in general + ** + ** \param pstcUsb USB handle + ** + ** \param pstcConfig USB configuration + ** + ** \return #en_result_t + ** + ******************************************************************************/ +en_result_t Usb_Configure(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcConfig) +{ + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + if (pstcUsbIntern->bUsbInstanceSet == FALSE) + { + memset(pstcUsbIntern,0,sizeof(stc_usb_intern_data_t)); + Usb_InitInstance(pstcUsb); + } + if (UsbInitDone == FALSE) + { + Usb_Init(); + } + if (pstcConfig->bUseInterrupts == TRUE) + { + Usb_InitIrq(pstcUsb); + } + else + { + Usb_DeinitIrq(pstcUsb); + } + + if (pstcConfig->enMode == UsbDeviceEnabled) + { + pstcUsbIntern->bDeviceEnabled = TRUE; + } + if (pstcConfig->enMode == UsbHostEnabled) + { + pstcUsbIntern->bHostEnabled = TRUE; + } + if (pstcConfig->enMode == UsbHostDeviceEnabled) + { + pstcUsbIntern->bDeviceEnabled = TRUE; + pstcUsbIntern->bHostEnabled = TRUE; + } + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + pstcUsbIntern->pu8DeviceDescriptor = pstcConfig->pu8DeviceDescriptor; + pstcUsbIntern->pu8ConfigDescriptor = pstcConfig->pu8ConfigDescriptor; + #endif + + pstcUsbIntern->pfnSetpCallback = pstcConfig->pfnSetpCallback; + pstcUsbIntern->pfnConfCallback = pstcConfig->pfnConfCallback; + pstcUsbIntern->pfnSofCallback = pstcConfig->pfnSofCallback; + pstcUsbIntern->pfnDeviceVbus = pstcConfig->pfnDeviceVbus; + pstcUsbIntern->pfnHostVbus = pstcConfig->pfnHostVbus; + pstcUsbIntern->pfnHostPullDownHostEnable = pstcConfig->pfnHostPullDownHostEnable; + pstcUsbIntern->pfnHostOvercurrent = pstcConfig->pfnHostOvercurrent; + pstcUsbIntern->pfnDeviceInit = pstcConfig->pfnDeviceInit; + pstcUsbIntern->pfnHostInit = pstcConfig->pfnHostInit; + + if (pstcUsbIntern->pfnHostVbus != NULL) + { + pstcUsbIntern->pfnHostVbus(UsbGpioInit); + pstcUsbIntern->pfnHostVbus(UsbGpioClear); + } + if (pstcUsbIntern->pfnHostPullDownHostEnable != NULL) + { + pstcUsbIntern->pfnHostPullDownHostEnable(UsbGpioInit); + pstcUsbIntern->pfnHostPullDownHostEnable(UsbGpioClear); + } + if (pstcUsbIntern->pfnHostOvercurrent != NULL) + { + pstcUsbIntern->pfnHostOvercurrent(UsbExtIntInit); + } + if (pstcUsbIntern->pfnDeviceVbus != NULL) + { + pstcUsbIntern->pfnDeviceVbus(UsbExtIntInit); + if (pstcUsbIntern->pfnDeviceVbus(UsbExtIntGetLevel)) + { + pstcUsbIntern->pfnDeviceVbus(UsbExtIntSetLowDetect); + } + else + { + pstcUsbIntern->pfnDeviceVbus(UsbExtIntSetHighDetect); + } + pstcUsbIntern->pfnDeviceVbus(UsbExtIntEnableIsr); + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Initialize USB in general + ** + ** \return #en_result_t + ** + ******************************************************************************/ +en_result_t Usb_Init( void ) +{ + volatile uint32_t u32Instance; + + for (u32Instance = 0; u32Instance < USB_INSTANCE_COUNT; u32Instance++) + { + memset(&m_astcUsbInstanceDataLut[u32Instance].stcInternData,0,sizeof(m_astcUsbInstanceDataLut[u32Instance].stcInternData)); + } + + + + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + Usb_InitInstance((stc_usbn_t*)&USB0); + #endif + + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + Usb_InitInstance((stc_usbn_t*)&USB1); + #endif + + #if (USB_USE_STANDALONE == 1) || (USB_USE_PDL == 1) + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + #if defined(FM_CLK_GATING_CKEN2) + FM_CLK_GATING_CKEN2 |= 0x1; + #elif defined(FM4_PERIPH_BASE) || (FM4_USB_AVAILABLE == 1u) + /*Peripheral Function Control Register 2 - USB Enable */ + *((volatile uint32_t*) 0x4003C120) |= 0x1; + #endif + + #if defined(bFM_GPIO_SPSR_USB0C) + bFM_GPIO_SPSR_USB0C = 1; + #elif defined(bFM0P_GPIO_SPSR_USB0C) + bFM0P_GPIO_SPSR_USB0C = 1; + #elif defined(bFM3_GPIO_SPSR_USB0C) + bFM3_GPIO_SPSR_USB0C = 1; + #elif defined(bFM4_GPIO_SPSR_USB0C) + bFM4_GPIO_SPSR_USB0C = 1; + #else + #error No definition for SPSR bit USB0C + #endif + + #if defined(bFM_GPIO_EPFR00_USBP0E) + bFM_GPIO_EPFR00_USBP0E = 1; + #elif defined(bFM_GPIO_EPFR00_USB0PE) + bFM_GPIO_EPFR00_USB0PE = 1; + #elif defined(bFM4_GPIO_EPFR00_USBP0E) + bFM4_GPIO_EPFR00_USBP0E = 1; + #elif defined(bFM4_GPIO_EPFR00_USB0PE) + bFM4_GPIO_EPFR00_USB0PE = 1; + #elif defined(bFM3_GPIO_EPFR00_USBP0E) + bFM3_GPIO_EPFR00_USBP0E = 1; + #elif defined(bFM3_GPIO_EPFR00_USB0PE) + bFM3_GPIO_EPFR00_USB0PE = 1; + #elif defined(bFM0P_GPIO_EPFR00_USBP0E) + bFM0P_GPIO_EPFR00_USBP0E = 1; + #elif defined(bFM3_GPIO_EPFR00_USB0PE) + bFM0P_GPIO_EPFR00_USB0PE = 1; + #else + #error No definition for EPFR bit USB0PE + #endif + + + #if defined(bFM4_GPIO_PFR6_P61) + /* USB Pull-up : P61 as UHCONX */ + bFM4_GPIO_PFR6_P61 = 1; + #elif defined(bFM4_GPIO_PFR6_P1) + /* USB Pull-up : P61 as UHCONX */ + bFM4_GPIO_PFR6_P1 = 1; + #elif defined(bFM3_GPIO_PFR6_P1) + /* USB Pull-up : P61 as UHCONX */ + bFM3_GPIO_PFR6_P1 = 1; + #elif (defined(bFM0P_GPIO_PFR0_PA) && (FM0P_DEVICE_TYPE == 2)) + /* USB Pull-up : P0A as UHCONX */ + bFM0P_GPIO_PFR0_PA = 1; + #elif defined(bFM0P_GPIO_PFR6_P1) + /* USB Pull-up : P61 as UHCONX */ + bFM0P_GPIO_PFR6_P1 = 1; + #else + #error no definition for UHCONX0 + #endif + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + + #if defined(FM_CLK_GATING_CKEN2) + FM_CLK_GATING_CKEN2 |= 0x2; + #elif defined(FM4_PERIPH_BASE) || (FM4_USB_AVAILABLE == 1u) + /*Peripheral Function Control Register 2 - USB Enable */ + *((volatile uint32_t*) 0x4003C120) |= 0x2; + #endif + + #if defined(bFM_GPIO_SPSR_USB1C) + bFM_GPIO_SPSR_USB1C = 1; + #elif defined(bFM0P_GPIO_SPSR_USB1C) + bFM0P_GPIO_SPSR_USB1C = 1; + #elif defined(bFM3_GPIO_SPSR_USB1C) + bFM3_GPIO_SPSR_USB1C = 1; + #elif defined(bFM4_GPIO_SPSR_USB1C) + bFM4_GPIO_SPSR_USB1C = 1; + #else + #error No definition for SPSR bit USB1C + #endif + + #if defined(bFM_GPIO_EPFR00_USBP1E) + bFM_GPIO_EPFR00_USBP1E = 1; + #elif defined(bFM_GPIO_EPFR00_USB1PE) + bFM_GPIO_EPFR00_USB1PE = 1; + #elif defined(bFM4_GPIO_EPFR00_USBP1E) + bFM4_GPIO_EPFR00_USBP1E = 1; + #elif defined(bFM4_GPIO_EPFR00_USB1PE) + bFM4_GPIO_EPFR00_USB1PE = 1; + #elif defined(bFM3_GPIO_EPFR00_USBP1E) + bFM3_GPIO_EPFR00_USBP1E = 1; + #elif defined(bFM3_GPIO_EPFR00_USB1PE) + bFM3_GPIO_EPFR00_USB1PE = 1; + #elif defined(bFM0P_GPIO_EPFR00_USBP1E) + bFM0P_GPIO_EPFR00_USBP1E = 1; + #elif defined(bFM3_GPIO_EPFR00_USB1PE) + bFM0P_GPIO_EPFR00_USB1PE = 1; + #else + #error No definition for EPFR bit USB1PE + #endif + + #ifdef bFM4_GPIO_PFR6_P61 + /* USB Pull-up : P61 as UHCONX */ + bFM4_GPIO_PFR6_P61 = 1; + #elif defined(bFM4_GPIO_PFR6_P1) + /* USB Pull-up : P61 as UHCONX */ + bFM4_GPIO_PFR6_P1 = 1; + #elif defined(bFM3_GPIO_PFR6_P1) + /* USB Pull-up : P61 as UHCONX */ + bFM3_GPIO_PFR2_P0 = 1; + #elif defined(bFM0P_GPIO_PFR6_P1) + /* USB Pull-up : P61 as UHCONX */ + bFM3_GPIO_PFR2_P0 = 1; + #else + #error no definition for UHCONX1 + #endif + #endif + #else + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + bL3_FM3_GPIO_SPSR_USB0C = 1; + bL3_FM3_GPIO_EPFR00_USB0PE = 1; + bL3_FM3_GPIO_PFR6_P1 = 1; + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + bL3_FM3_GPIO_SPSR_USB1C = 1; + bL3_FM3_GPIO_EPFR00_USB1PE = 1; + bL3_FM3_GPIO_PFR2_P0 = 1; + #endif + #endif + UsbEthernetClock_Init(); + UsbInitDone = TRUE; + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Setup USB HAL endpoint + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param u8EndpointAddress Endpoint address + ** + ** \param u16FifoSize Endpoint FIFO size + ** + ** \param enType Type of endpoint, see also #en_usb_ep_type_t + ** + ** \param bInterruptsEnabled Use interrupts + ** + ** \return #en_result_t + ** + ******************************************************************************/ +en_result_t Usb_SetupHalEndpoint(stc_usbn_t* pstcUsb,uint8_t u8EndpointAddress , uint16_t u16FifoSize, en_usb_ep_type_t enType, boolean_t bInterruptsEnabled) +{ + stc_usbn_endpoint_data_t* pstcEndpoint; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + pstcEndpoint = &(pstcUsbIntern->astcEndpoints[(u8EndpointAddress & 0x1F) + 1]); + + *(pstcEndpoint->pstcEpControlRegister) = u16FifoSize & 0x1FF; + pstcEndpoint->u8EndpointAddress = u8EndpointAddress; + pstcEndpoint->u16EndpointSize = (u16FifoSize & 0x1FF); + *(pstcEndpoint->pstcEpControlRegister) |= (((u8EndpointAddress & 0x80) > 0) << 12); + *(pstcEndpoint->pstcEpControlRegister) |= enType << 13; + if ((bInterruptsEnabled == TRUE) && ((u8EndpointAddress & 0x80) == 0)) + { + USB_EPNS_DRQIE_SET(pstcEndpoint); + //BITMASK_SET(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + } + else + { + USB_EPNS_DRQIE_CLEAR(pstcEndpoint); + //BITMASK_CLEAR(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + } + BITMASK_SET(*(pstcEndpoint->pstcEpControlRegister),_EPNC_EPEN); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Switch "Task" between host / device mode + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param enType Type of switching, see also #en_usb_switch_t + ** + ** \param u32SwitchDelay optional delay + ** + ** \return #en_result_t + ** + ******************************************************************************/ +en_result_t Usb_SwitchUsb(stc_usbn_t* pstcUsb, en_usb_switch_t enType, uint32_t u32SwitchDelay) +{ + static volatile uint32_t u32InternalSwitchDelay; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + if (u32InternalSwitchDelay != 0) + { + u32InternalSwitchDelay--; + return ErrorNotReady; + } + switch(enType) + { + case UsbSwitchDependingDeviceVbus: + if (pstcUsbIntern->pfnDeviceVbus != NULL) + { + if (pstcUsbIntern->pfnDeviceVbus(UsbExtIntGetLevel) == TRUE) + { + #if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + if ((pstcUsbIntern->bHostActive == TRUE) && (pstcUsbIntern->bHostEnabled == TRUE)) + { + pstcUsbIntern->bHostActive = !(Usb_DeinitHostMode(pstcUsb) == Ok); + u32InternalSwitchDelay = u32SwitchDelay; + return ErrorNotReady; + } + #endif + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + if ((pstcUsbIntern->bDeviceActive == FALSE) && (pstcUsbIntern->bDeviceEnabled == TRUE)) + { + pstcUsbIntern->bDeviceActive = (Usb_InitDeviceMode(pstcUsb) == Ok); + if (pstcUsbIntern->bDeviceActive == TRUE) + { + return Ok; + } + return ErrorNotReady; + } + #endif + + } else + { + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + if ((pstcUsbIntern->bDeviceActive == TRUE) && (pstcUsbIntern->bDeviceEnabled == TRUE)) + { + pstcUsbIntern->bDeviceActive = !(Usb_DeinitDeviceMode(pstcUsb) == Ok); + u32InternalSwitchDelay = u32SwitchDelay; + return ErrorNotReady; + } + #endif + #if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + if ((pstcUsbIntern->bHostActive == FALSE) && (pstcUsbIntern->bHostEnabled == TRUE)) + { + pstcUsbIntern->bHostActive = (Usb_InitHostMode(pstcUsb) == Ok); + if (pstcUsbIntern->bHostActive == TRUE) + { + return Ok; + } + return ErrorNotReady; + } + #endif + } + } + break; + case UsbSwitchToDevice: + #if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + if ((pstcUsbIntern->bHostActive == TRUE) && (pstcUsbIntern->bHostEnabled == TRUE)) + { + pstcUsbIntern->bHostActive = !(Usb_DeinitHostMode(pstcUsb) == Ok); + u32InternalSwitchDelay = u32SwitchDelay; + return ErrorNotReady; + } + #endif + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + if ((pstcUsbIntern->bDeviceActive == FALSE) && (pstcUsbIntern->bDeviceEnabled == TRUE)) + { + pstcUsbIntern->bDeviceActive = (Usb_InitDeviceMode(pstcUsb) == Ok); + if (pstcUsbIntern->bDeviceActive == TRUE) + { + return Ok; + } + return ErrorNotReady; + } + #endif + break; + case UsbSwitchToHost: + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + if ((pstcUsbIntern->bDeviceActive == TRUE) && (pstcUsbIntern->bDeviceEnabled == TRUE)) + { + pstcUsbIntern->bDeviceActive = !(Usb_DeinitDeviceMode(pstcUsb) == Ok); + u32InternalSwitchDelay = u32SwitchDelay; + return ErrorNotReady; + } + #endif + #if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + if ((pstcUsbIntern->bHostActive == FALSE) && (pstcUsbIntern->bHostEnabled == TRUE)) + { + pstcUsbIntern->bHostActive = (Usb_InitHostMode(pstcUsb) == Ok); + if (pstcUsbIntern->bHostActive == TRUE) + { + return Ok; + } + return ErrorNotReady; + } + #endif + break; + case UsbSwitchAllOff: + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + if ((pstcUsbIntern->bDeviceActive == TRUE) && (pstcUsbIntern->bDeviceEnabled == TRUE)) + { + pstcUsbIntern->bDeviceActive = !(Usb_DeinitDeviceMode(pstcUsb) == Ok); + u32InternalSwitchDelay = u32SwitchDelay; + } + #endif + #if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + if ((pstcUsbIntern->bHostActive == TRUE) && (pstcUsbIntern->bHostEnabled == TRUE)) + { + pstcUsbIntern->bHostActive = !(Usb_DeinitHostMode(pstcUsb) == Ok); + u32InternalSwitchDelay = u32SwitchDelay; + } + #endif + if ((pstcUsbIntern->bDeviceActive == FALSE) && (pstcUsbIntern->bHostActive == FALSE)) + { + return Ok; + } + return ErrorNotReady; + } + return Ok; +} + +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) +/** + ****************************************************************************** + ** \brief Init USB device + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +static en_result_t Usb_InitDeviceMode(stc_usbn_t* pstcUsb) +{ + volatile uint32_t i; + stc_usb_config_t stcConfig; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + if ((pstcUsbIntern->pu8DeviceDescriptor == NULL) || (pstcUsbIntern->pfnDeviceInit == NULL)) + { + return ErrorUninitialized; + } + if (pstcUsbIntern->pfnHostPullDownHostEnable != NULL) + { + pstcUsbIntern->pfnHostPullDownHostEnable(UsbGpioClear); + } + if (pstcUsbIntern->pfnHostVbus != NULL) + { + pstcUsbIntern->pfnHostVbus(UsbGpioClear); + } + Usb_InitInstance(pstcUsb); + Usb_DeinitDeviceMode(pstcUsb); + + pstcUsb->UDCC_f.RST = 1; // Reset USB HAL + pstcUsb->UDCC = 0x00A0; // load initial values + #if defined(FM_USB0_HCNT0) + pstcUsb->HCNT0 = 0; // Switch off host + pstcUsb->HCNT1 = 0; // Switch off host + pstcUsb->HCNT0_f.URST = 1; // Switch off host + #else + pstcUsb->HCNT = 0; // Switch off host + pstcUsb->HCNT_f.URST = 1; // Switch off host + #endif + pstcUsb->UDCC_f.USTP = 0; + pstcUsb->UDCC_f.RESUM = 0; + pstcUsb->UDCC_f.RFBK = 0; + pstcUsb->UDCC_f.STALCLREN = 1; + + if (pstcUsbIntern->pu8ConfigDescriptor[7] == USBATTR_SELFPOWER) + { + pstcUsb->UDCC_f.PWC = 1; + } + else + { + pstcUsb->UDCC_f.PWC = 0; + } + + pstcUsb->EP0C = pstcUsbIntern->pu8DeviceDescriptor[7]; + + pstcUsb->UDCC_f.RST = 0; + + pstcUsbIntern->pfnDeviceInit(pstcUsb,&stcConfig); + + + + pstcUsbIntern->pfnSetpCallback = stcConfig.pfnSetpCallback; + pstcUsbIntern->pfnConfCallback = stcConfig.pfnConfCallback; + + for (i = pstcUsbIntern->u8NumberOfEndpoints; i > 0;i--) + { + BITMASK_CLEAR(*((uint16_t*)pstcUsbIntern->astcEndpoints[i - 1].pstcEpStatusRegister),_EPNS_BFINI); + } + + pstcUsb->UDCIE_f.SUSPIE = 1; + pstcUsb->UDCIE_f.SOFIE = 0; + pstcUsb->UDCIE_f.BRSTIE = 1; + pstcUsb->UDCIE_f.WKUPIE = 1; + pstcUsb->UDCIE_f.CONFIE = 1; + pstcUsb->UDCIE_f.CONFN = 0; + + pstcUsb->EP0IS_f.DRQIIE = 0; + pstcUsb->EP0OS_f.DRQOIE = 1; + + pstcUsb->UDCC_f.HCONX = 0; + + return Ok; +} +#endif + +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) +/** + ****************************************************************************** + ** \brief Deinit USB device + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +static en_result_t Usb_DeinitDeviceMode(stc_usbn_t* pstcUsb) +{ + uint8_t i; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + for (i = 0;i < pstcUsbIntern->u8NumberOfEndpoints;i++) + { + BITMASK_CLEAR(*((uint16_t*)pstcUsbIntern->astcEndpoints[i - 1].pstcEpStatusRegister),_EPNC_EPEN); + BITMASK_CLEAR(*((uint16_t*)pstcUsbIntern->astcEndpoints[i - 1].pstcEpStatusRegister),_EPNS_DRQIE); + } + + pstcUsb->UDCIE_f.CONFN = 0; + pstcUsb->UDCC_f.HCONX = 1; + pstcUsb->UDCC_f.RST = 1; // Reset USB HAL + + pstcUsb->UDCIE = 0; + + pstcUsb->EP0IS_f.DRQIIE = 0; + pstcUsb->EP0OS_f.DRQOIE = 0; + + + if (pstcUsbIntern->pfnConfCallback != NULL) + { + pstcUsbIntern->pfnConfCallback(pstcUsb); + } + + Usb_DeinitInstance(pstcUsb); + + return Ok; +} +#endif + +#if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) +/** + ****************************************************************************** + ** \brief Init USB host + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +static en_result_t Usb_InitHostMode(stc_usbn_t* pstcUsb) +{ + uint8_t i; + stc_usb_config_t stcConfig; + stc_usb_intern_data_t* pstcUsbIntern; + USB_ZERO_STRUCT(stcConfig); + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + pstcUsbIntern->bSofTimeoutEnabled = FALSE; + for(i = 0;i<5;i++) + { + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler = NULL; + pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut = 0; + } + + pstcUsb->HCNT_f.HOST = 0; + pstcUsb->UDCC_f.HCONX = 1; // disable HCONX + pstcUsb->UDCC_f.RST = 1; // Reset USB HAL + + Usb_InitInstance(pstcUsb); + + pstcUsb->EP1C_f.EPEN = 0; + pstcUsb->EP2C_f.EPEN = 0; + + pstcUsb->EP0IS_f.DRQIIE = 0; + pstcUsb->EP0OS_f.DRQOIE = 0; + pstcUsb->EP1C = 0x4000 | 256; + pstcUsb->EP2C = 0x4000 | 64; + pstcUsb->EP3C = 0x4000; + pstcUsb->EP4C = 0x4000; + pstcUsb->EP5C = 0x4000; + + + //Usb_SetupHalEndpoint(pstcUsb,0x81, 256, EpTypeHost, FALSE); // EP 1 for IN transfers + //Usb_SetupHalEndpoint(pstcUsb,0x02, 64, EpTypeHost, FALSE); // EP 2 for OUT transfers + + pstcUsb->EP1C_f.DIR = 0; // EP1 is a HOST IN endpoint + pstcUsb->EP2C_f.DIR = 1; // EP2 is a HOST OUT endpoint + + pstcUsb->EP1C_f.EPEN = 1; // enable endpoint 1 + pstcUsb->EP2C_f.EPEN = 1; // enable endpoint 2 + + pstcUsb->HFCOMP = 0; + //pstcUsb->HRTIMER0 = 0; + //pstcUsb->HRTIMER1 = 0; + //pstcUsb->HRTIMER2 = 0; + pstcUsb->HSTATE_f.CSTAT = 0; + + pstcUsbIntern->pfnHostInit(pstcUsb,&stcConfig); + pstcUsbIntern->pfnSofCallback = stcConfig.pfnSofCallback; + pstcUsbIntern->pfnDirqCallback = stcConfig.pfnDirqCallback; + pstcUsbIntern->pfnCnnirqCallback = stcConfig.pfnCnnirqCallback; + pstcUsbIntern->pfnCmpirqCallback = stcConfig.pfnCmpirqCallback; + pstcUsbIntern->pfnUrirqCallback = stcConfig.pfnUrirqCallback; + pstcUsbIntern->pfnRwkirqCallback = stcConfig.pfnRwkirqCallback; + pstcUsbIntern->pfnTcanCallback = stcConfig.pfnTcanCallback; + + pstcUsb->HADR = 0; // Device Address = 0 + pstcUsb->HCNT_f.HOST = 1; // Enable Host + pstcUsb->HCNT_f.HOST = 1; // Enable Host + + pstcUsb->HIRQ = 0; /* IRQ clear */ + + //pstcUsb->HRTIMER0 = 0; + //pstcUsb->HRTIMER1 = 0; + //pstcUsb->HRTIMER2 = 0; + + pstcUsb->HCNT_f.RETRY = 0; + + pstcUsb->HEOF = 0x2c9; // Set the time where token are allowed in a frame + + pstcUsb->EP1S_f.BFINI = 1; + pstcUsb->EP1S_f.BFINI = 0; + + pstcUsb->EP2S_f.BFINI = 1; + pstcUsb->EP2S_f.BFINI = 0; + + pstcUsb->HFCOMP = 0x00; /* SOF interrupt frame No. for INTERRUPT-IN transfer */ + + pstcUsb->HCNT_f.HOST = 1; // Enable Host + pstcUsb->HCNT_f.CNNIRE = 1; // connection interrupt + pstcUsb->HCNT_f.DIRE = 1; // disconnect interrupt + pstcUsb->HCNT_f.CMPIRE = 1; // token completion interrupt + pstcUsb->HCNT_f.SOFIRE = 1; // SOF interrupt + pstcUsb->HCNT_f.HOST = 1; // Enable Host + + if (pstcUsbIntern->pfnHostPullDownHostEnable != NULL) + { + pstcUsbIntern->pfnHostPullDownHostEnable(UsbGpioSet); + } + if (pstcUsbIntern->pfnHostVbus != NULL) + { + pstcUsbIntern->pfnHostVbus(UsbGpioSet); + } + + return Ok; +} +#endif + +#if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) +/** + ****************************************************************************** + ** \brief Deinit USB host + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +static en_result_t Usb_DeinitHostMode(stc_usbn_t* pstcUsb) +{ + uint8_t i; + stc_usb_intern_data_t* pstcUsbIntern; + stc_usb_config_t stcConfig; + USB_ZERO_STRUCT(stcConfig); + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + pstcUsb->HIRQ = 0; + pstcUsbIntern->bSofTimeoutEnabled = FALSE; + for(i = 0;i<5;i++) + { + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler = NULL; + pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut = 0; + } + + pstcUsbIntern->pfnHostInit(pstcUsb,&stcConfig); + pstcUsbIntern->pfnSofCallback = NULL; + pstcUsbIntern->pfnDirqCallback = NULL; + pstcUsbIntern->pfnCnnirqCallback = NULL; + pstcUsbIntern->pfnCmpirqCallback = NULL; + pstcUsbIntern->pfnUrirqCallback = NULL; + pstcUsbIntern->pfnRwkirqCallback = NULL; + pstcUsbIntern->pfnTcanCallback = NULL; + + UsbHost_DisconnectionCallback(pstcUsb); + + pstcUsb->UDCC_f.HCONX = 1; // disable HCONX + pstcUsb->UDCC_f.RST = 1; // Reset USB HAL + pstcUsb->EP1C = 0x4000; + pstcUsb->EP2C = 0x4000; + pstcUsb->EP3C = 0x4000; + pstcUsb->EP4C = 0x4000; + pstcUsb->EP5C = 0x4000; + + + pstcUsb->HADR = 0; + + + if (pstcUsbIntern->pfnHostPullDownHostEnable != NULL) + { + pstcUsbIntern->pfnHostPullDownHostEnable(UsbGpioClear); + } + if (pstcUsbIntern->pfnHostVbus != NULL) + { + pstcUsbIntern->pfnHostVbus(UsbGpioClear); + } + pstcUsb->HCNT = 0; + + Usb_DeinitInstance(pstcUsb); + + return Ok; +} +#endif + + +/** + ****************************************************************************** + ** \brief Init USB instance + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +en_result_t Usb_InitInstance(stc_usbn_t* pstcUsb) +{ + uint8_t i; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + pstcUsbIntern->bUsbInstanceSet = TRUE; + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + pstcUsbIntern->u8NumberOfEndpoints = 7; + #else + pstcUsbIntern->u8NumberOfEndpoints = 2; + #endif + + pstcUsbIntern->bSofTimeoutEnabled = FALSE; + for(i = 0;i<5;i++) + { + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler = NULL; + pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut = 0; + } + + pstcUsb->UDCC = 0xA0; // load initial values + pstcUsb->EP0C = 0; // load initial values + pstcUsb->EP1C = 0; // load initial values + pstcUsb->EP2C = 0; // load initial values + pstcUsb->EP3C = 0; // load initial values + pstcUsb->EP4C = 0; // load initial values + pstcUsb->EP5C = 0; // load initial values + pstcUsb->UDCS = 0; // load initial values + pstcUsb->UDCIE = 0; // load initial values + pstcUsb->EP0IS = 0; // load initial values + pstcUsb->EP0OS = 0; // load initial values + pstcUsb->EP1S = 0; // load initial values + pstcUsb->EP2S = 0; // load initial values + pstcUsb->EP3S = 0; // load initial values + pstcUsb->EP4S = 0; // load initial values + pstcUsb->EP5S = 0; // load initial values + #if defined(FM_USB0_HCNT0) + pstcUsb->HCNT0 = 0; // load initial values + pstcUsb->HCNT1 = 0; // load initial values + #else + pstcUsb->HCNT = 0; // load initial values + + #endif + pstcUsb->HIRQ = 0; // load initial values + pstcUsb->HERR = 0; // load initial values + pstcUsb->HSTATE = 0x10; // load initial values + pstcUsb->HADR = 0x10; // load initial values + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + pstcUsbIntern->astcEndpoints[0].u8EndpointAddress = 0x80; + pstcUsbIntern->astcEndpoints[0].u16EndpointSize = 64; + pstcUsbIntern->astcEndpoints[0].pstcEpStatusRegister = &(pstcUsb->EP0IS); + pstcUsbIntern->astcEndpoints[0].pstcEpControlRegister = &(pstcUsb->EP0C); + pstcUsbIntern->astcEndpoints[0].pstcEpDataRegister = &(pstcUsb->EP0DT); + pstcUsbIntern->astcEndpoints[0].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[0].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[0].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[1].u8EndpointAddress = 0x00; + pstcUsbIntern->astcEndpoints[1].u16EndpointSize = 64; + pstcUsbIntern->astcEndpoints[1].pstcEpStatusRegister = &(pstcUsb->EP0OS); + pstcUsbIntern->astcEndpoints[1].pstcEpControlRegister = &(pstcUsb->EP0C); + pstcUsbIntern->astcEndpoints[1].pstcEpDataRegister = &(pstcUsb->EP0DT); + pstcUsbIntern->astcEndpoints[1].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[1].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[1].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[2].u8EndpointAddress = 0x01; + pstcUsbIntern->astcEndpoints[2].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[2].pstcEpStatusRegister = &(pstcUsb->EP1S); + pstcUsbIntern->astcEndpoints[2].pstcEpControlRegister = &(pstcUsb->EP1C); + pstcUsbIntern->astcEndpoints[2].pstcEpDataRegister = &(pstcUsb->EP1DT); + pstcUsbIntern->astcEndpoints[2].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[2].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[2].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[3].u8EndpointAddress = 0x02; + pstcUsbIntern->astcEndpoints[3].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[3].pstcEpStatusRegister = &(pstcUsb->EP2S); + pstcUsbIntern->astcEndpoints[3].pstcEpControlRegister = &(pstcUsb->EP2C); + pstcUsbIntern->astcEndpoints[3].pstcEpDataRegister = &(pstcUsb->EP2DT); + pstcUsbIntern->astcEndpoints[3].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[3].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[3].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[4].u8EndpointAddress = 0x03; + pstcUsbIntern->astcEndpoints[4].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[4].pstcEpStatusRegister = &(pstcUsb->EP3S); + pstcUsbIntern->astcEndpoints[4].pstcEpControlRegister = &(pstcUsb->EP3C); + pstcUsbIntern->astcEndpoints[4].pstcEpDataRegister = &(pstcUsb->EP3DT); + pstcUsbIntern->astcEndpoints[4].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[4].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[4].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[5].u8EndpointAddress = 0x04; + pstcUsbIntern->astcEndpoints[5].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[5].pstcEpStatusRegister = &(pstcUsb->EP4S); + pstcUsbIntern->astcEndpoints[5].pstcEpControlRegister = &(pstcUsb->EP4C); + pstcUsbIntern->astcEndpoints[5].pstcEpDataRegister = &(pstcUsb->EP4DT); + pstcUsbIntern->astcEndpoints[5].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[5].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[5].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[6].u8EndpointAddress = 0x05; + pstcUsbIntern->astcEndpoints[6].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[6].pstcEpStatusRegister = &(pstcUsb->EP5S); + pstcUsbIntern->astcEndpoints[6].pstcEpControlRegister = &(pstcUsb->EP5C); + pstcUsbIntern->astcEndpoints[6].pstcEpDataRegister = &(pstcUsb->EP5DT); + pstcUsbIntern->astcEndpoints[6].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[6].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[6].pstcUsbInstance = pstcUsb; + +#else + pstcUsbIntern->astcEndpoints[0].u8EndpointAddress = 0x01; + pstcUsbIntern->astcEndpoints[0].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[0].pstcEpStatusRegister = &(pstcUsb->EP1S); + pstcUsbIntern->astcEndpoints[0].pstcEpControlRegister = &(pstcUsb->EP1C); + pstcUsbIntern->astcEndpoints[0].pstcEpDataRegister = &(pstcUsb->EP1DT); + pstcUsbIntern->astcEndpoints[0].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[0].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[0].pstcUsbInstance = pstcUsb; + + pstcUsbIntern->astcEndpoints[1].u8EndpointAddress = 0x02; + pstcUsbIntern->astcEndpoints[1].u16EndpointSize = 0x00; + pstcUsbIntern->astcEndpoints[1].pstcEpStatusRegister = &(pstcUsb->EP2S); + pstcUsbIntern->astcEndpoints[1].pstcEpControlRegister = &(pstcUsb->EP2C); + pstcUsbIntern->astcEndpoints[1].pstcEpDataRegister = &(pstcUsb->EP2DT); + pstcUsbIntern->astcEndpoints[1].pfnRxTxCallback = NULL; + pstcUsbIntern->astcEndpoints[1].bAutomaticNullTermination = FALSE; + pstcUsbIntern->astcEndpoints[1].pstcUsbInstance = pstcUsb; +#endif + + return Ok; +} + + +/** + ****************************************************************************** + ** \brief Deinit USB instance + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +en_result_t Usb_DeinitInstance(stc_usbn_t* pstcUsb) +{ + pstcUsb->UDCC = 0xA0; // load initial values + pstcUsb->EP0C = 0; // load initial values + pstcUsb->EP1C = 0; // load initial values + pstcUsb->EP2C = 0; // load initial values + pstcUsb->EP3C = 0; // load initial values + pstcUsb->EP4C = 0; // load initial values + pstcUsb->EP5C = 0; // load initial values + pstcUsb->UDCS = 0; // load initial values + pstcUsb->UDCIE = 0; // load initial values + pstcUsb->EP0IS = 0; // load initial values + pstcUsb->EP0OS = 0; // load initial values + pstcUsb->EP1S = 0; // load initial values + pstcUsb->EP2S = 0; // load initial values + pstcUsb->EP3S = 0; // load initial values + pstcUsb->EP4S = 0; // load initial values + pstcUsb->EP5S = 0; // load initial values + #if defined(FM_USB0_HCNT0) + pstcUsb->HCNT0 = 0; // load initial values + pstcUsb->HCNT1 = 0; // load initial values + #else + pstcUsb->HCNT = 0; // load initial values + + #endif + pstcUsb->HIRQ = 0; // load initial values + pstcUsb->HERR = 0; // load initial values + pstcUsb->HSTATE = 0x10; // load initial values + pstcUsb->HADR = 0x10; // load initial values + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set RxTx Callback of an endpoint + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \param pfnRxTxCallback Callback routine + ** + ** \return none + ** + ******************************************************************************/ +void Usb_SetEndpointRxTxCallback(stc_usbn_endpoint_data_t* pstcEndpoint, usb_endpoint_datatransferred_func_ptr_t pfnRxTxCallback) +{ + //BITMASK_CLEAR(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + USB_EPNS_DRQIE_CLEAR(pstcEndpoint); + pstcEndpoint->pfnRxTxCallback = pfnRxTxCallback; + if ((pfnRxTxCallback != NULL) && ((pstcEndpoint->u8EndpointAddress & 0x80) == 0)) + { + //BITMASK_SET(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + USB_EPNS_DRQIE_SET(pstcEndpoint); + } +} + +/** + ****************************************************************************** + ** \brief Get endpoint pointer from endpointaddress + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param u8EndpointAddress u8EndpointAddress + ** + ** \return Pointer to endpoint, NULL if no enpoint was found + ** + ******************************************************************************/ +stc_usbn_endpoint_data_t* Usb_GetEndpointPtr(stc_usbn_t* pstcUsb, uint8_t u8EndpointAddress) +{ + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return NULL; + } + if ((u8EndpointAddress & 0x1F) == 0) + { + if ((u8EndpointAddress & 0x80) > 0) + { + return &(pstcUsbIntern->astcEndpoints[0]); + } + else + { + return &(pstcUsbIntern->astcEndpoints[1]); + } + } + else + { + if ((u8EndpointAddress & 0x1F) <= (pstcUsbIntern->u8NumberOfEndpoints - 2)) + { + if ((pstcUsbIntern->astcEndpoints[(u8EndpointAddress & 0x1F) + 1].u8EndpointAddress) == u8EndpointAddress) + { + return &(pstcUsbIntern->astcEndpoints[(u8EndpointAddress & 0x1F) + 1]); + } + } + } + return NULL; +} + +/** + ****************************************************************************** + ** \brief Stall endpoint. + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \return Ok on success + ** + ******************************************************************************/ +en_result_t Usb_HalStallEndpoint(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + volatile uint32_t u32Timeout; + u32Timeout = 1000000; + while((BITMASK_ISSET(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_BUSY)) && (u32Timeout > 0)) + { + u32Timeout--; + } + if (u32Timeout == 0) + { + return ErrorTimeout; + } + BITMASK_SET(*(pstcEpHandle->pstcEpControlRegister), _EPNC_STAL); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Unstall endpoint. + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \return Ok on success + ** + ******************************************************************************/ +en_result_t Usb_HalUnstallEndpoint(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + volatile uint32_t u32Timeout; + u32Timeout = 1000000; + while((BITMASK_ISSET(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_BUSY)) && (u32Timeout > 0)) + { + u32Timeout--; + } + if (u32Timeout == 0) + { + return ErrorTimeout; + } + BITMASK_CLEAR(*(pstcEpHandle->pstcEpControlRegister), _EPNC_STAL); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Unstall endpoint. + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \return Ok on success + ** + ******************************************************************************/ +boolean_t Usb_HalEndpointIsBusy(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + if (BITMASK_ISSET(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_BUSY)) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ****************************************************************************** + ** \brief Send data via endpoint. + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \param pu8Data Data to write + ** + ** \param u16Size Data size + ** + ** \param pu16ByteCount Pointer to data written + ** + ** \return Ok on success + ** + ******************************************************************************/ +en_result_t Usb_HalSend(stc_usbn_endpoint_data_t* pstcEpHandle, uint8_t* pu8Data, uint16_t u16Size, uint16_t* pu16ByteCount) +{ + boolean_t bEvenData = 0; + USBDBGVAL8("HAL Snd ",pstcEpHandle->u8EndpointAddress); + USBDBGVAL8("Sze ",u16Size); + if ( pu16ByteCount != NULL ) + { + *pu16ByteCount = 0; + } + + if ( (pstcEpHandle == NULL) || (((pu8Data == NULL) || (pu16ByteCount == NULL)) && (u16Size != 0)) ) + { + return ErrorInvalidParameter ; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpStatusRegister),_EPNS_DRQ)) + { + return ErrorNotReady; + } + + if (u16Size > pstcEpHandle->u16EndpointSize) + { + u16Size = pstcEpHandle->u16EndpointSize; + } + USBDBGVAL8("New Sze ",u16Size); + bEvenData = ((u16Size % 2) == 0); + + if (u16Size == 0) + { + bEvenData = TRUE; + } + else + { + for(*pu16ByteCount = 0;*pu16ByteCount < (u16Size - 1);*pu16ByteCount = *pu16ByteCount + 2) + { + *(pstcEpHandle->pstcEpDataRegister) = *((uint16_t*)pu8Data); + pu8Data += 2; + } + } + + if (!bEvenData) + { + *pu16ByteCount = *pu16ByteCount + 1; + *((__IO uint8_t*)(pstcEpHandle->pstcEpDataRegister)) = *pu8Data; + } + + USB_EPNS_DRQ_CLEAR(pstcEpHandle); + //BITMASK_CLEAR(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_DRQ); + return Ok; +} + + +#if USB_USES_DMA == ON +uint8_t u8EndpointBit; +/** + ****************************************************************************** + ** \brief Send data via endpoint. (via DMA) + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \param pu8Data Data to write + ** + ** \param u16Size Data size + ** + ** \param pu16ByteCount Pointer to data written + ** + ** \return Ok on success + ** + ******************************************************************************/ + +en_result_t Usb_HalSendDma(stc_usbn_endpoint_data_t* pstcEpHandle, uint8_t* pu8Data, uint16_t u16Size, uint16_t* pu16ByteCount) +{ + boolean_t bEvenData = FALSE; + volatile uint32_t temp = 0; + u8EndpointBit = (1 << (((pstcEpHandle->u8EndpointAddress) & 0x0F) - 1)); + uint8_t i; + USBDBGVAL8("HAL Snd DMA ",pstcEpHandle->u8EndpointAddress); + USBDBGVAL8("Sze ",u16Size); + if ( pu16ByteCount != NULL ) + { + *pu16ByteCount = 0; + } + + if ( (pstcEpHandle == NULL) || (((pu8Data == NULL) || (pu16ByteCount == NULL)) && (u16Size != 0)) ) + { + return ErrorInvalidParameter ; + } + if ((u16Size % 2) == 0) + { + bEvenData = TRUE; + } + else + { + bEvenData = FALSE; + } + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpStatusRegister),_EPNS_DRQ)) + { + return ErrorNotReady; + } + + FM3_DMAC->DMACR |= 0x80000000; + for(i = 0; i < USB_DMA_INSTANCE_COUNT;i++) + { + if(!(astcUsbDma[i].bIsActive)) + { + NVIC_ClearPendingIRQ(astcUsbDma[i].u8IRQ); // Setup DMA interrupt + NVIC_DisableIRQ(astcUsbDma[i].u8IRQ); // Disable DMA interrupt + NVIC_SetPriority(astcUsbDma[i].u8IRQ,IRQ_LEVEL_USB0); // Setup DMA interrupt + + astcUsbDma[i].pstcEpHandle = pstcEpHandle; // store used endpoint for this DMA channel + pstcEpHandle->bIsActive = TRUE; // mark enpoint as in use + astcUsbDma[i].bIsActive = TRUE; // mark DMA channel as in use + *(astcUsbDma[i].pstcDMACA) &= ~(1 << 31); // clear enable flag for this channel + + BITMASK_SET(*(pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); // Setup endpoint for DMA usage + BITMASK_SET(*(pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); // Setup endpoint for DMA usage + + *(astcUsbDma[i].pstcDMACB)= (2 << 28) | (1 << 26) | (1 << 24); // Demand transfer mode, half-word, fixed source + + temp = (((pstcEpHandle->u8EndpointAddress) & 0x0F) - 1) | 0x20; // IDREQ input select settings + temp = temp << 23; // IDREQ input select settings + #if (FM3_DEVICE_TYPE == 0u) && defined(FM3_DEVICE_TYPE) + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + if (pstcEpHandle->pstcUsbInstance == &USB0) + { + if (bEvenData) + { + //FM3_INTREQ->ODDPKS &= ~(u8EndpointBit << 24); + temp += (u16Size / 2) - 1; + FM3_INTREQ->ODDPKS = 0x0; + } + else + { + //FM3_INTREQ->ODDPKS |= (uint32_t)(u8EndpointBit << 24); + FM3_INTREQ->ODDPKS = 0xFF; + temp += (u16Size / 2); + } + } + #endif + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + if (pstcEpHandle->pstcUsbInstance == &USB1) + { + if (bEvenData) + { + FM3_INTREQ->ODDPKS1 &= ~(u8EndpointBit << 24); + temp += (u16Size / 2) - 1; + } + else + { + FM3_INTREQ->ODDPKS1 |= (u8EndpointBit << 24); + temp += (u16Size / 2); + } + } + #endif + *pu16ByteCount = u16Size; + #else + temp += (u16Size / 2) - 1; + *pu16ByteCount = (u16Size / 2) * 2; // update data transferred information + #endif + // IDREQ input select settings + *(astcUsbDma[i].pstcDMACA) = temp; + + *(astcUsbDma[i].pstcDMACSA) = (uint32_t)pu8Data; // data source + *(astcUsbDma[i].pstcDMACDA) = (uint32_t)(pstcEpHandle->pstcEpDataRegister); // endpoint data register as data destination + FM3_INTREQ->DRQSEL |= (uint32_t)(1 << ((uint32_t)(pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); // select DMA usage instead of IRQ for endpoint + BITMASK_SET(*(pstcEpHandle->pstcEpControlRegister),_EPNS_DRQIE); // enable interrupt handling for this endpoint + *(astcUsbDma[i].pstcDMACB) |= (uint32_t)(1 << 19); // DMA completion interrupt enabled + + NVIC_ClearPendingIRQ(astcUsbDma[i].u8IRQ); // Setup DMA interrupt + NVIC_EnableIRQ(astcUsbDma[i].u8IRQ); // Setup DMA interrupt + NVIC_SetPriority(astcUsbDma[i].u8IRQ,IRQ_LEVEL_USB0); // Setup DMA interrupt + *(astcUsbDma[i].pstcDMACA) |= (uint32_t)(1 << 31); // DMA enable channel + + return Ok; + } + } + return ErrorNotReady; +} +#endif + +/** + ****************************************************************************** + ** \brief Wait while endpoint is busy + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \param pu8Data Databuffer to write in + ** + ** \param pu16ByteCount Pointer to data read + ** + ** \param bClearDrq Set FIFO ready for next data + ** + ** \return Ok on success + ** + ******************************************************************************/ +en_result_t Usb_EpBusyWait(stc_usbn_endpoint_data_t* pstcEndpoint) +{ + volatile uint32_t u32Timeout; + volatile uint32_t u32NotBusyCount = 0; + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock * 10; + while(u32Timeout > 0) + { + if (!BITMASK_ISSET(*(pstcEndpoint->pstcEpStatusRegister), _EPNS_BUSY)) + { + u32NotBusyCount++; + } + else + { + u32NotBusyCount = 0; + } + if (u32NotBusyCount > 10) + { + return Ok; + } + u32Timeout--; + } + return ErrorTimeout; +} + +/** + ****************************************************************************** + ** \brief Read data via endpoint. + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \param pu8Data Databuffer to write in + ** + ** \param pu16ByteCount Pointer to data read + ** To specify maximum data which can be stored, + ** set bit 15 to 1 and bit 14 to 0. bit 0 to 13 are used + ** to specify the maximum of data which can be received. + ** If more data is received in a package, this data will be lost. + ** + ** \param bClearDrq Set FIFO ready for next data + ** + ** \return Ok on success + ** + ******************************************************************************/ +en_result_t Usb_HalReceive(stc_usbn_endpoint_data_t* pstcEpHandle, uint8_t* pu8Data, uint16_t* pu16ByteCount, boolean_t bClearDrq) +{ + boolean_t bEvenData = 0; + uint16_t u16CountTemp = 0; + volatile uint16_t u16Dummy; + uint16_t u16i; + uint16_t u16Max = 0xFFFF; + + if ( pu16ByteCount != NULL ) + { + *pu16ByteCount = 0; + } + else + { + pu16ByteCount = &u16CountTemp; + } + + if ((*pu16ByteCount & 0xC000) == 0x8000) + { + u16Max = (*pu16ByteCount & 0x03FF); + } + + if (pstcEpHandle == NULL) + { + return ErrorInvalidParameter ; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpStatusRegister),_EPNS_DRQ)) + { + return ErrorNotReady; + } + + *pu16ByteCount = (*(pstcEpHandle->pstcEpStatusRegister)) & 0x7F; + + bEvenData = (((*pu16ByteCount) % 2) == 0); + + if (*pu16ByteCount == 0) + { + bEvenData = TRUE; + u16i = 0; + } + else + { + for(u16i = 0;u16i < (*pu16ByteCount - 1);u16i += 2) + { + if (u16i < u16Max) + { + *((uint16_t*)pu8Data) = *(pstcEpHandle->pstcEpDataRegister); + pu8Data += 2; + } + else + { + u16Dummy = *(pstcEpHandle->pstcEpDataRegister); + } + } + } + + if (!bEvenData) + { + if (u16i < u16Max) + { + *pu8Data = *((__IO uint8_t*)(pstcEpHandle->pstcEpDataRegister)); + } + else + { + u16Dummy = *((__IO uint8_t*)(pstcEpHandle->pstcEpDataRegister)); + } + } + if (bClearDrq) + { + USB_EPNS_DRQ_CLEAR(pstcEpHandle); + } + // [andreika]: gcc fix + (void)(u16Dummy); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Clear Drq flag of FIFO: FIFO ready for next data + ** + ** \param pstcEpHandle Pointer to endpoint instance + ** + ** \return Ok on success + ** + ******************************************************************************/ +en_result_t Usb_HalClearDrq(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + if (pstcEpHandle == NULL) + { + return ErrorInvalidParameter ; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpStatusRegister),_EPNS_DRQ)) + { + return ErrorNotReady; + } + USB_EPNS_DRQ_CLEAR(pstcEpHandle); + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get information about the specified endpoint status + ** + ** \param pstcEpHandle Endpoint handle + ** + ** \return Status + ** + ******************************************************************************/ +en_usb_endpoint_status_t Usb_HalEndpointStatus(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + if (pstcEpHandle == NULL) + { + return UsbEndpointStatusNotReady; + } + + if (BITMASK_ISSET(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_BUSY)) + { + return UsbEndpointBusy; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpControlRegister),_EPNC_EPEN)) + { + return UsbEndpointStatusNotReady; + } + + if (BITMASK_ISSET(*(pstcEpHandle->pstcEpControlRegister), _EPNC_STAL)) + { + return UsbEndpointStatusStall; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_DRQ)) + { + return UsbEndpointStatusTransfer; + } + else + { + return UsbEndpointStatusIdle; + } + + + //return UsbEndpointStatusIdle; +} + +/** + ****************************************************************************** + ** \brief Get information if the specified endpoint is ready + ** + ** \param pstcEpHandle Endpoint handle + ** + ** \return TRUE if ready + ** + ******************************************************************************/ +boolean_t Usb_HalEpReady(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + if (pstcEpHandle == NULL) + { + return FALSE; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpControlRegister),_EPNC_EPEN)) + { + return FALSE; + } + + if (BITMASK_ISCLEARED(*(pstcEpHandle->pstcEpStatusRegister), _EPNS_DRQ)) + { + return FALSE; + } + else + { + return TRUE; + } + +} + +/** + ****************************************************************************** + ** Usb Device get current configuration + ** + ** \param pstcUsb USB handle + ** + *****************************************************************************/ +uint8_t Usb_GetConfiguration(stc_usbn_t* pstcUsb) +{ + if (pstcUsb->UDCC_f.HCONX == 1) + { + return 0; + } + return pstcUsb->UDCIE_f.CONFN; +} + + +/** + ****************************************************************************** + ** SOF callback - Realize Timeouts + ** + ** \param pstcUsb USB handle + ** + *****************************************************************************/ +static void Usb_TimeoutHandler(stc_usbn_t* pstcUsb) +{ + volatile uint8_t i; + boolean_t bNothingToBeDone = TRUE; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return; + } + for(i = 0;i<5;i++) + { + if (pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler != 0) + { + bNothingToBeDone = FALSE; + if (pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut == 0) + { + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler(pstcUsb); + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler = 0; + return; + } + else + { + pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut--; + } + } + } + if (bNothingToBeDone == TRUE) + { + pstcUsbIntern->bSofTimeoutEnabled = FALSE; + } +} + +/** + ****************************************************************************** + ** Add a timeout handler + ** + ** \param pstcUsb USB handle + ** + ** \param Handler handler executed after timeout + ** + ** \param u16TimeOut timeout in ms + ** + ** \return TRUE if command was successful + ** + *****************************************************************************/ +boolean_t Usb_AddTimeOut(stc_usbn_t* pstcUsb, void (* Handler)(stc_usbn_t* pstcUsb), uint16_t u16TimeOut) +{ + volatile uint8_t i; + boolean_t bAdded = FALSE; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return ErrorUninitialized; + } + for(i = 0;i<5;i++) + { + if (pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler == 0) + { + pstcUsbIntern->bSofTimeoutEnabled = FALSE; + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler = Handler; + pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut = u16TimeOut; + pstcUsbIntern->bSofTimeoutEnabled = TRUE; + bAdded = TRUE; + break; + } + } + pstcUsbIntern->bSofTimeoutEnabled = TRUE; + return bAdded; +} + +/** + ****************************************************************************** + ** Remove a timeout handler + ** + ** \param pstcUsb USB handle + ** + ** \param Handler handler executed after timeout + ** + ** \return none + ** + *****************************************************************************/ +void Usb_RemoveTimeOut(stc_usbn_t* pstcUsb, void (* Handler)(stc_usbn_t* pstcUsb)) +{ + volatile uint8_t i; + stc_usb_intern_data_t* pstcUsbIntern; + pstcUsbIntern = UsbGetInternDataPtr(pstcUsb); + if (pstcUsbIntern == NULL) + { + return; + } + for(i = 0;i<5;i++) + { + if (pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler == Handler) + { + pstcUsbIntern->pstcUsbTimeOutHandler[i].Handler = 0; + pstcUsbIntern->pstcUsbTimeOutHandler[i].u16TimeOut = 0; + break; + } + } +} + +/******************************************************************************/ +/* Interrupt Handling */ +/******************************************************************************/ + +void Usb_Tick(void) +{ + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + #endif + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + #endif + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + #endif + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + #endif +} + +// [andreika]: IRQs are already handled in interrupts_fm4_type_b.c +// This is a fix for PDL versions mismatch +void Usb_IrqHandlerF(stc_usbn_t* pstcUsb) +{ + UsbIrqHandler(pstcUsb, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + UsbIrqHandlerF(pstcUsb, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); +} +void Usb_IrqHandlerH(stc_usbn_t* pstcUsb) +{ + UsbIrqHandler(pstcUsb, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); +} +// [andreika]: disable all these IRQ handlers +#if 0 + +#if !defined(FM_GENERAL_MCUHEADER_VERSION) || (FM_GENERAL_MCUHEADER_VERSION < 0200) + #if (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON) + /** + ****************************************************************************** + ** USB 0 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + void USBF_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USBF_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB_F_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB_F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0F_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_F_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_F_ED123_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_F_ED450I_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_F_ED0O_ST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USB_USE_PDL == 0) + void IRQ078_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #endif + #endif + + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + /** + ****************************************************************************** + ** USB 0 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + void USB_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0F_USB0H_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0F_USB0H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_H_F_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_H_F_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_H_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_HOST_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_HOST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USB_USE_PDL == 0) + void IRQ079_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #endif + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON) + /** + ****************************************************************************** + ** USB 1 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + void USB1F_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_F_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_F_ED123_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_F_ED450I_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_F_ED0O_ST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_HDMICEC0_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + /** + ****************************************************************************** + ** USB 1 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + + void USB1_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1F_USB1H_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1F_USB1H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_H_F_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_H_F_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_H_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_HOST_Handler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_HOST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_HOST_HDMICEC1_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + #endif +#elif defined(FM_GENERAL_MCUHEADER_VERSION) || (FM_GENERAL_MCUHEADER_VERSION >= 0200) + #if (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON) + /** + ****************************************************************************** + ** USB 0 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + #if defined(IRQ_USBF_AVAILABLE) + void USBF_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB_F_AVAILABLE) + void USB_F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0F_AVAILABLE) + void USB0F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_F_AVAILABLE) + void USB0_F_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_F_ED123_AVAILABLE) &&\ + defined(IRQ_USB0_F_ED450I_AVAILABLE) + void USB0_F_ED123_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_F_ED450I_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_IRQ078_AVAILABLE) && (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USB_USE_PDL == 0) + void IRQ078_Handler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #else + #error No IRQ handler definition for the USB 0 device endpoint data + #endif + #endif + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + /** + ****************************************************************************** + ** USB 0 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + #if defined(IRQ_USB_AVAILABLE) + void USB_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + #elif defined(IRQ_USB0_AVAILABLE) + void USB0_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0F_USB0H_AVAILABLE) + void USB0F_USB0H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_H_F_AVAILABLE) + void USB0_H_F_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_F_ED0O_ST_AVAILABLE) && defined(IRQ_USB0_H_AVAILABLE) + void USB0_F_ED0O_ST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + + void USB0_H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_H_AVAILABLE) + void USB0_H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_HOST_AVAILABLE) + void USB0_HOST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #elif defined(IRQ_USB0_F_MFT0_ICU_AVAILABLE) + void USB0_F_MFT0_ICU_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + UsbIrqHandlerF((stc_usbn_t*)&USB0, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + } + #else + #error No IRQ handler definition for the USB 0 + #endif + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON) + /** + ****************************************************************************** + ** USB 1 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + #if defined(IRQ_USB1F_AVAILABLE) + void USB1F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_F_AVAILABLE) + void USB1_F_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_F_ED123_AVAILABLE) && defined(IRQ_USB1_F_ED450I_AVAILABLE) + void USB1_F_ED123_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + + void USB1_F_ED450I_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_HDMICEC0_AVAILABLE) + void USB1_HDMICEC0_IRQHandler(void) + { + UsbIrqHandlerF((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #else + #error No IRQ handler definition for the USB 1 device endpoint data + #endif + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + /** + ****************************************************************************** + ** USB 1 function interrupt handler (only used in standalone mode) + ** + *****************************************************************************/ + #if defined(IRQ_USB1_AVAILABLE) + void USB1_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1F_USB1H_AVAILABLE) + void USB1F_USB1H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_H_F_AVAILABLE) + void USB1_H_F_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_F_ED0O_ST_AVAILABLE) && defined(IRQ_USB1_H_AVAILABLE) + void USB1_F_ED0O_ST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + void USB1_H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_H_AVAILABLE) + void USB1_H_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_HOST_AVAILABLE) + void USB1_HOST_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #elif defined(IRQ_USB1_HOST_HDMICEC1_AVAILABLE) + void USB1_HOST_HDMICEC1_IRQHandler(void) + { + UsbIrqHandler((stc_usbn_t*)&USB1, &(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + } + #else + #error No IRQ handler definition for the USB 1 + #endif + #endif +#else + #error Could not initiate IRQ handlers +#endif + +#if (USB_USE_STANDALONE == ON) || (USB_USE_PDL == 1) + #if USB_USES_DMA == ON + #if USB_USES_DMA_0 == ON + void DMAC0_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex0].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex0].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex0].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex0].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex0].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex0].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex0].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex0].stcInternData)); + } + #endif + #if USB_USES_DMA_1 == ON + void DMAC1_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex1].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex1].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex1].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex1].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex1].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex1].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex1].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex1].stcInternData)); + } + #endif + #if USB_USES_DMA_2 == ON + void DMAC2_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex2].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex2].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex2].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex2].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex2].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex2].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex2].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex2].stcInternData)); + } + #endif + #if USB_USES_DMA_3 == ON + void DMAC3_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex3].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex3].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex3].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex3].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex3].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex3].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex3].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex3].stcInternData)); + } + #endif + #if USB_USES_DMA_4 == ON + void DMAC4_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex4].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex4].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex4].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex4].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex4].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex4].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex4].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex4].stcInternData)); + } + #endif + #if USB_USES_DMA_5 == ON + void DMAC5_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex5].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex5].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex5].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex5].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex5].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex5].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex5].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex5].stcInternData)); + } + #endif + #if USB_USES_DMA_6 == ON + void DMAC6_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex6].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex6].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex6].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex6].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex6].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex6].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex6].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex6].stcInternData)); + } + #endif + #if USB_USES_DMA_7 == ON + void DMAC7_Handler(void) + { + FM3_INTREQ->DRQSEL &= (uint32_t)~(1 << ((uint32_t)(astcUsbDma[UsbDmaInstanceIndex7].pstcEpHandle->u8EndpointAddress) & 0x0F) - 1); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex7].pstcEpHandle->pstcEpControlRegister),_EPNC_DMAE); + BITMASK_CLEAR(*(astcUsbDma[UsbDmaInstanceIndex7].pstcEpHandle->pstcEpControlRegister),_EP1C_NULE); + *(astcUsbDma[UsbDmaInstanceIndex7].pstcDMACA) &= (uint32_t)(1 << 31); // disable channel + *(astcUsbDma[UsbDmaInstanceIndex7].pstcDMACB) &= (uint32_t)(1 << 19); // disable interrupt + astcUsbDma[UsbDmaInstanceIndex7].bIsActive = FALSE; + UsbIrqHandlerF((stc_usbn_t*)astcUsbDma[UsbDmaInstanceIndex7].pstcEpHandle->pstcUsbInstance, &(m_astcUsbInstanceDataLut[UsbDmaInstanceIndex7].stcInternData)); + } + #endif + #endif +#endif + +// [andreika]: +#endif + +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) +/** + ****************************************************************************** + ** USB function interrupt handler (used for HAL endpoint interrupts) + ** + ** \param pstcUsb USB handle + ** + ** \param pstcUsbInternData Internal data USB handle + ** + *****************************************************************************/ +void UsbIrqHandlerF(stc_usbn_t* pstcUsb, stc_usb_intern_data_t* pstcUsbInternData) +{ + volatile uint32_t i; + uint32_t temp; + + // handle USB Endpoint 0 + if ((pstcUsb->UDCS_f.SETP == 1) && (pstcUsb->EP0OS_f.DRQOIE == 0)) + { + pstcUsb->EP0OS_f.DRQOIE = 1; + } + + if ((pstcUsb->EP0OS_f.DRQO == 1) && (pstcUsb->EP0OS_f.DRQOIE == 1)) + { + if (pstcUsb->UDCS_f.SETP == 1) + { + pstcUsb->UDCS_f.SETP = 0; + if (pstcUsbInternData->pfnSetpCallback != NULL) + { + USBDBG(">> SETP\n"); + pstcUsbInternData->pfnSetpCallback(pstcUsb); + } + } + else + { + if ((pstcUsb->EP0OS & 0x1F) == 0) + { + USBDBG(" zerro package "); + // Zerro Package Received + } + if (pstcUsbInternData->astcEndpoints[1].pfnRxTxCallback != NULL) + { + pstcUsbInternData->astcEndpoints[1].pfnRxTxCallback(pstcUsb,&(pstcUsbInternData->astcEndpoints[1])); + } + else + { + USBDBG("EP0"); + if ((pstcUsb->EP0OS & 0x1F) == 0) + { + USBDBG(" zerro package "); + // Zerro Package Received + } + pstcUsb->EP0OS_f.DRQO = 0; + USBDBG("received (not handled)\n"); + } + } + } + + if ((pstcUsb->EP0IS_f.DRQI == 1) && (pstcUsb->EP0IS_f.DRQIIE == 1)) + { + if (pstcUsbInternData->astcEndpoints[0].pfnRxTxCallback != NULL) + { + pstcUsbInternData->astcEndpoints[0].pfnRxTxCallback(pstcUsb,&(pstcUsbInternData->astcEndpoints[0])); + } + } + + // handle all other Endpoints + for(i = 2;i < pstcUsbInternData->u8NumberOfEndpoints;i++) + { + if ((BITMASK_ISSET(*(pstcUsbInternData->astcEndpoints[i].pstcEpStatusRegister),_EPNS_DRQ)) && (BITMASK_ISSET(*(pstcUsbInternData->astcEndpoints[i].pstcEpStatusRegister),_EPNS_DRQIE))) + { + while(pstcUsbInternData->astcEndpoints[i].bIsActive == TRUE) + { + pstcUsbInternData->astcEndpoints[i].bIsActive = FALSE; + } + if (pstcUsbInternData->astcEndpoints[i].pfnRxTxCallback != NULL) + { + temp = i; //needed to avoid warning, because of unknown volatile access + pstcUsbInternData->astcEndpoints[(uint8_t)temp].pfnRxTxCallback(pstcUsb,&(pstcUsbInternData->astcEndpoints[(uint8_t)temp])); + } + } + } +} +#endif + +/** + ****************************************************************************** + ** \brief Wait Hook Functions, called every time a USB operation have to wait + ** Do not call from interrupt! + *****************************************************************************/ +void Usb_WaitHook(void) +{ + if (TRUE == bUsbNeedsOsTick) + { + Usb_OsTickHandle(); + } + #if USB_USES_PDL == 1 + PDL_WAIT_LOOP_HOOK; + #endif +} + +/** + ****************************************************************************** + ** \brief Operation System Tick Handle + *****************************************************************************/ +void Usb_OsTickHandle(void) +{ + if (bUsbNeedsOsTick == FALSE) + { + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + Usb_DeinitIrq((stc_usbn_t*)&USB0); + #endif + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + Usb_DeinitIrq((stc_usbn_t*)&USB1); + #endif + bUsbNeedsOsTick = TRUE; + } + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + UsbIrqHandlerF((stc_usbn_t*)&USB0,&(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + UsbIrqHandlerF((stc_usbn_t*)&USB1,&(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + #endif + #endif + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + UsbIrqHandler((stc_usbn_t*)&USB0,&(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb0].stcInternData)); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + UsbIrqHandler((stc_usbn_t*)&USB1,&(m_astcUsbInstanceDataLut[UsbInstanceIndexUsb1].stcInternData)); + #endif +} + +/** + ****************************************************************************** + ** USB interrupt handler + ** + ** \param pstcUsb USB handle + ** + ** \param pstcUsbInternData Internal data USB handle + ** + *****************************************************************************/ +void UsbIrqHandler(stc_usbn_t* pstcUsb, stc_usb_intern_data_t* pstcUsbInternData) +{ + volatile uint32_t i; + + if (pstcUsbInternData->bDeviceActive) + { + if (pstcUsb->UDCS_f.CONF == 1) + { + pstcUsb->UDCS_f.CONF = 0; + if (pstcUsbInternData->pfnConfCallback != NULL) + { + pstcUsbInternData->pfnConfCallback(pstcUsb); + } + } + + + if (pstcUsb->EP0C_f.STAL == 1) + { + pstcUsb->EP0C_f.STAL = 0; + } + + if ((pstcUsb->UDCS_f.SETP == 1) && (pstcUsb->EP0OS_f.DRQOIE == 0)) + { + pstcUsb->EP0OS_f.DRQOIE = 1; + } + + if ((pstcUsb->EP0OS_f.DRQO == 1) && (pstcUsb->EP0OS_f.DRQOIE == 1)) + { + if (pstcUsb->UDCS_f.SETP == 1) + { + pstcUsb->UDCS_f.SETP = 0; + if (pstcUsbInternData->pfnSetpCallback != NULL) + { + USBDBG(">> SETP\n"); + pstcUsbInternData->pfnSetpCallback(pstcUsb); + } + } + else + { + if ((pstcUsb->EP0OS & 0x1F) == 0) + { + USBDBG(" zerro package "); + // Zerro Package Received + } + if (pstcUsbInternData->astcEndpoints[1].pfnRxTxCallback != NULL) + { + pstcUsbInternData->astcEndpoints[1].pfnRxTxCallback(pstcUsb,&(pstcUsbInternData->astcEndpoints[1])); + } + else + { + USBDBG("EP0"); + if ((pstcUsb->EP0OS & 0x1F) == 0) + { + USBDBG(" zerro package "); + // Zerro Package Received + } + pstcUsb->EP0OS_f.DRQO = 0; + USBDBG("received (not handled)\n"); + } + } + } + + if ((pstcUsb->EP0IS_f.DRQI == 1) && (pstcUsb->EP0IS_f.DRQIIE == 1)) + { + if (pstcUsbInternData->astcEndpoints[0].pfnRxTxCallback != NULL) + { + pstcUsbInternData->astcEndpoints[0].pfnRxTxCallback(pstcUsb,&(pstcUsbInternData->astcEndpoints[0])); + } + } + + if (pstcUsb->UDCS_f.WKUP == 1) + { + pstcUsb->UDCS_f.WKUP = 0; + if (pstcUsbInternData->pfnWkupCallback != NULL) + { + pstcUsbInternData->pfnWkupCallback(pstcUsb); + } + } + if (pstcUsb->UDCS_f.BRST == 1) + { + pstcUsb->UDCS_f.BRST = 0; + for (i = pstcUsbInternData->u8NumberOfEndpoints; i > 0;i--) + { + BITMASK_SET(*((uint16_t*)pstcUsbInternData->astcEndpoints[i - 1].pstcEpStatusRegister),_EPNS_BFINI); + BITMASK_CLEAR(*((uint16_t*)pstcUsbInternData->astcEndpoints[i - 1].pstcEpStatusRegister),_EPNS_BFINI); + } + pstcUsb->EP0IS_f.DRQIIE = 0; + pstcUsb->EP0OS_f.DRQOIE = 1; + if (pstcUsbInternData->pfnBrstCallback != NULL) + { + pstcUsbInternData->pfnBrstCallback(pstcUsb); + } + } + if (pstcUsb->UDCS_f.SOF == 1) + { + pstcUsb->UDCS_f.SOF = 0; + if (pstcUsbInternData->bSofTimeoutEnabled == TRUE) + { + Usb_TimeoutHandler(pstcUsb); + } + + if (pstcUsbInternData->pfnSofCallback != NULL) + { + pstcUsbInternData->pfnSofCallback(pstcUsb); + } + } + if (pstcUsb->UDCS_f.SUSP == 1) + { + pstcUsb->UDCS_f.SUSP = 0; + if (pstcUsbInternData->pfnSuspCallback != NULL) + { + pstcUsbInternData->pfnSuspCallback(pstcUsb); + } + } + } + if (pstcUsbInternData->bHostActive) + { + if (pstcUsb->HIRQ_f.CMPIRQ == 1) + { + pstcUsb->HIRQ_f.CMPIRQ = 0; + if (pstcUsbInternData->pfnCmpirqCallback != NULL) + { + pstcUsbInternData->pfnCmpirqCallback(pstcUsb); + } + } + if (pstcUsb->HIRQ_f.SOFIRQ == 1) + { + pstcUsb->HIRQ_f.SOFIRQ = 0; + + if (pstcUsbInternData->bSofTimeoutEnabled == TRUE) + { + Usb_TimeoutHandler(pstcUsb); + } + + if (pstcUsbInternData->pfnSofCallback != NULL) + { + pstcUsbInternData->pfnSofCallback(pstcUsb); + } + } + if (pstcUsb->HIRQ_f.DIRQ == 1) + { + pstcUsb->HIRQ_f.DIRQ = 0; + if (pstcUsbInternData->pfnDirqCallback != NULL) + { + pstcUsbInternData->pfnDirqCallback(pstcUsb); + } + } + if (pstcUsb->HIRQ_f.CNNIRQ == 1) + { + if (pstcUsbInternData->pfnCnnirqCallback != NULL) + { + pstcUsbInternData->pfnCnnirqCallback(pstcUsb); + } + else + { + pstcUsb->HIRQ_f.CNNIRQ = 0; + } + } + if (pstcUsb->HIRQ_f.URIRQ == 1) + { + if (pstcUsbInternData->pfnUrirqCallback != NULL) + { + pstcUsbInternData->pfnUrirqCallback(pstcUsb); + } + else + { + pstcUsb->HIRQ_f.URIRQ = 0; + } + } + if (pstcUsb->HIRQ_f.RWKIRQ == 1) + { + pstcUsb->HIRQ_f.RWKIRQ = 0; + if (pstcUsbInternData->pfnRwkirqCallback != NULL) + { + pstcUsbInternData->pfnRwkirqCallback(pstcUsb); + } + } + if (pstcUsb->HIRQ_f.TCAN == 1) + { + pstcUsb->HIRQ_f.TCAN = 0; + if (pstcUsbInternData->pfnTcanCallback != NULL) + { + pstcUsbInternData->pfnTcanCallback(pstcUsb); + } + } + } + //UsbIrqHandlerF(pstcUsb, pstcUsbInternData); +} + +//@} // UsbGroup + + + +#endif // #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) || (FM_PERIPHERAL_ENABLE_USB0 == ON)) +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.h new file mode 100644 index 0000000000..1e8bc17c0d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usb.h @@ -0,0 +1,1863 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usb.h + ** + ** Headerfile for USB functions + ** + ** A detailed description is available at + ** @link UsbGroup USB Module description @endlink + ** + ** History: + ** - 2012-08-28 2.0 MSc First version (starting at version 2.0) + ** - 2012-10-02 2.1 MSc use of external interrupts without L3 implemented + ** - 2012-11-13 2.2 MSc Some problems while switching from Host to Device fixed + ** - 2013-01-31 2.3 MSc DMA added + ** - 2013-05-07 2.4 MSc Minor optimizations + ** - 2013-06-04 2.5 MSc FM4 support added + ** - 2013-09-23 2.6 MSc FM4 PDL support added + ** - 2013-11-29 2.7 MSc PDL adjustments done + ** - 2014-02-28 2.8 MSc Fixes for FM4 (IRQ naming, mcu headerfile typedef) + ** Fixes in SwitchUsb Routine + ** - 2014-05-27 2.9 MSc IRQ double definition with use of PDL > V1.0 solved + ** - 2014-09-04 3.0 MSc Device Mass Storage, USB Host Printer & NDIS added + ** FM4 type 3 added + ** - 2014-10-31 3.1 MSc Usb_OsTickHandle corrected to run USB without IRQs + ** - 2015-05-05 3.2 MSc Corrected wrong initialization behaviour for device / host enable + ** in Usb_Configure + ** - 2015-05-14 3.3 MSCH Moved unnecessary "old" stuff to USB legacy + ** Better timeout handling added + ** - 2015-05-29 3.4 MSCH Added new bit manipulation macros to improve EPnS access + ** - USBREG_BITBAND_ADDRESS + ** - USBREG_BIT_SET + ** - USBREG_BIT_CLEAR + ** - USBREG_BIT_ISSET + ** added better data overflow handling + ** added support for FM0P with USB + ** - 2015-06-29 3.5 MSCH Added more IRQ handles + ** - 2015-08-18 3.6 MSCH Added more IRQ handles + ** + ******************************************************************************/ + +#ifndef __USB_H__ +#define __USB_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" + +#include "usbconfig.h" +#include "string.h" +#include "base_types.h" +#if (USB_USE_L3 == 1) + #include "l3.h" +#endif + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** + ****************************************************************************** + ** \defgroup UsbGroup USB General HAL Functionalities + ** + ** Provided functions of USB module: + ** + ** - Usb_Configure() + ** - Usb_Init() + ** - Usb_SetupHalEndpoint() + ** - Usb_SwitchUsb() + ** - Usb_InitInstance() + ** - Usb_GetEndpointPtr() + ** - Usb_HalSend() + ** - Usb_HalReceive() + ** - Usb_HalEpReady() + ** - Usb_HalEndpointIsBusy() + ** - Usb_GetConfiguration() + ** - Usb_AddTimeOut() + ** - Usb_RemoveTimeOut() + ** + ** Used to initialize the HAL and using low level functionality. Usb_Configure() is used to setup + ** the low level driver. Usb_SetupHalEndpoint() is used to setup an endpoint in hardware (for device mode). + ** Usb_SwitchUsb() can be called, to switch USB on or off or between host and device functionality. + ** Usb_SwitchUsb() is called cyclic or via external interrupt when VBUS state changes. Usb_InitInstance() + ** initializes all neccesary registers. Usb_GetEndpointPtr() returns pointer of endpoint struct. + ** Usb_HalSend() and Usb_HalReceive() can be used to transfer data to or from the endpoint FIFO. + ** Usb_HalEpReady() gives an information wether the endpoint is ready to use while Usb_HalEndpointIsBusy() + ** gives the information if the endpoint is transferring data. While endpoints having double buffers, the endpoint + ** can be ready for next data, but is still busy. Usb_GetConfiguration() returns if the HAL in device mode is + ** configured or not. Usb_AddTimeOut() adds timeout functionality via SOF interrupt. Usb_RemoveTimeOut() removes timeouts. + ** + ** \note For USB Host functionality, see also @link UsbHostGroup USB Host Module description @endlink + ** For USB Device functionality see also @link UsbDeviceGroup USB Device Module description @endlink + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#if !defined(OFF) + #define OFF 0U +#endif +#if !defined(ON) + #define ON 1U +#endif + +#if !defined(USB_USE_PDL) +#define USB_USE_PDL 0 +#endif + +#if !defined(USB_USE_LEGACYSUPPORT) + #if (!defined(FM_USB_AVAILABLE)) && (!defined(FM_USB0)) && (!defined(FM_USB1)) + #define USB_USE_LEGACYSUPPORT 1U + #if defined(__USB_C__) + #warning USB legacy support turned on automatically, but it is better to update to the latest MCU template! + #endif + #else + #define USB_USE_LEGACYSUPPORT 0U + #endif +#endif + +#if !defined(USB_USE_L3) +#define USB_USE_L3 0 +#endif + +#if !defined(USB_USES_DMA) + #define USB_USES_DMA OFF +#endif + +#if !defined(USB_USE_STANDALONE) + #if (USB_USE_PDL == OFF) && (USB_USE_L3 == OFF) + #define USB_USE_STANDALONE ON + #else + #define USB_USE_STANDALONE OFF + #endif +#endif + + +#if (USB_USE_STANDALONE == ON) + #if defined(FM_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM_USB0_BASE)) + #elif defined(FM0P_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM3_USB0_BASE)) + #elif defined(FM3_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM3_USB0_BASE)) + #elif defined(FM3_USB_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM3_USB_BASE)) + #elif defined(FM4_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM4_USB0_BASE)) + #elif defined(FM0P_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM4_USB0P_BASE)) + #endif + + #if defined(FM_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM_USB1_BASE)) + #elif defined(FM0P_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM3_USB1_BASE)) + #elif defined(FM3_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM3_USB1_BASE)) + #elif defined(FM4_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM4_USB1_BASE)) + #elif defined(FM0P_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM0P_USB1_BASE)) + #endif + + #ifndef USB0_DEVICE_IRQ_ENABLED + #define USB0_DEVICE_IRQ_ENABLED 1 + #endif + #ifndef USB0_HOST_IRQ_ENABLED + #define USB0_HOST_IRQ_ENABLED 1 + #endif + #ifndef USB1_DEVICE_IRQ_ENABLED + #define USB1_DEVICE_IRQ_ENABLED 1 + #endif + #ifndef USB1_HOST_IRQ_ENABLED + #define USB1_HOST_IRQ_ENABLED 1U + #endif + + #define FM_PERIPHERAL_ENABLE_USB0_HOST USB0_HOST_ENABLED + #define FM_PERIPHERAL_ENABLE_USB1_HOST USB1_HOST_ENABLED + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE USB0_DEVICE_ENABLED + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE USB1_DEVICE_ENABLED +#elif (USB_USE_L3 == ON) + #if defined(FM4_USB0) + #error L3 library is not available for FM4! + #endif + + #if defined(USB_USE_LEGACYSUPPORT) + #undef USB_USE_LEGACYSUPPORT + #define USB_USE_LEGACYSUPPORT 1U + #endif + + #define USB0 (*((volatile stc_usbn_t *) L3_USB0_BASE)) + #define USB1 (*((volatile stc_usbn_t *) L3_USB1_BASE)) + + #if USB_USES_DMA != OFF + #undef USB_USES_DMA + #define USB_USES_DMA OFF + #endif + + #if defined(L3_IRQ_LEVEL_USB0) + #undef IRQ_LEVEL_USB0 + #define IRQ_LEVEL_USB0 L3_IRQ_LEVEL_USB0 + #endif + #if defined(L3_IRQ_LEVEL_USB1) + #undef IRQ_LEVEL_USB1 + #define IRQ_LEVEL_USB1 L3_IRQ_LEVEL_USB1 + #endif + + #ifndef USB0_DEVICE_IRQ_ENABLED + #define USB0_DEVICE_IRQ_ENABLED 1 + #endif + + #ifndef USB0_HOST_IRQ_ENABLED + #define USB0_HOST_IRQ_ENABLED 1 + #endif + + #ifndef USB1_DEVICE_IRQ_ENABLED + #define USB1_DEVICE_IRQ_ENABLED 1 + #endif + + #ifndef USB1_HOST_IRQ_ENABLED + #define USB1_HOST_IRQ_ENABLED 1 + #endif + + #define FM_PERIPHERAL_ENABLE_USB0_HOST L3_PERIPHERAL_ENABLE_USB0_HOST + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE L3_PERIPHERAL_ENABLE_USB0_DEVICE + #define FM_PERIPHERAL_ENABLE_USB1_HOST L3_PERIPHERAL_ENABLE_USB1_HOST + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE L3_PERIPHERAL_ENABLE_USB1_DEVICE + +#elif (USB_USE_PDL == ON) + + #if defined(FM_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM_USB0_BASE)) + #elif defined(FM0P_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM3_USB0_BASE)) + #elif defined(FM3_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM3_USB0_BASE)) + #elif defined(FM3_USB_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM3_USB_BASE)) + #elif defined(FM4_USB0_BASE) + #define USB0 (*((volatile stc_usbn_t *) FM4_USB0_BASE)) + #endif + + #if defined(FM_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM_USB1_BASE)) + #elif defined(FM0P_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM3_USB1_BASE)) + #elif defined(FM3_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM3_USB1_BASE)) + #elif defined(FM4_USB1_BASE) + #define USB1 (*((volatile stc_usbn_t *) FM4_USB1_BASE)) + #endif + + #if USB_USES_DMA != OFF + #undef USB_USES_DMA + #define USB_USES_DMA OFF + #endif + + #if defined(PDL_IRQ_LEVEL_USB0) + #undef IRQ_LEVEL_USB0 + #define IRQ_LEVEL_USB0 PDL_IRQ_LEVEL_USB0 + #endif + + #if defined(PDL_IRQ_LEVEL_USB1) + #undef IRQ_LEVEL_USB1 + #define IRQ_LEVEL_USB1 PDL_IRQ_LEVEL_USB1 + #endif + + #if defined(USB0_DEVICE_IRQ_ENABLED) + #undef USB0_DEVICE_IRQ_ENABLED + #endif + + #if defined(USB0_HOST_IRQ_ENABLED) + #undef USB0_HOST_IRQ_ENABLED + #endif + + #if defined(USB1_DEVICE_IRQ_ENABLED) + #undef USB1_DEVICE_IRQ_ENABLED + #endif + + #if defined(USB1_HOST_IRQ_ENABLED) + #undef USB1_HOST_IRQ_ENABLED + #endif + + #define USB0_DEVICE_IRQ_ENABLED PDL_INTERRUPT_ENABLE_USB0_DEVICE + #define USB0_HOST_IRQ_ENABLED PDL_INTERRUPT_ENABLE_USB0_HOST + #define USB1_DEVICE_IRQ_ENABLED PDL_INTERRUPT_ENABLE_USB1_DEVICE + #define USB1_HOST_IRQ_ENABLED PDL_INTERRUPT_ENABLE_USB1_HOST + + #define FM_PERIPHERAL_ENABLE_USB0_HOST PDL_PERIPHERAL_ENABLE_USB0_HOST + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE PDL_PERIPHERAL_ENABLE_USB0_DEVICE + #define FM_PERIPHERAL_ENABLE_USB1_HOST PDL_PERIPHERAL_ENABLE_USB1_HOST + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE PDL_PERIPHERAL_ENABLE_USB1_DEVICE + + #ifdef USBDEVICECDCCOM_ENABLED + #undef USBDEVICECDCCOM_ENABLED + #endif + #ifdef USBDEVICEHIDJOYSTICK_ENABLED + #undef USBDEVICEHIDJOYSTICK_ENABLED + #endif + #ifdef USBDEVICEHIDKEYBOARD_ENABLED + #undef USBDEVICEHIDKEYBOARD_ENABLED + #endif + #ifdef USBDEVICEHIDMOUSE_ENABLED + #undef USBDEVICEHIDMOUSE_ENABLED + #endif + #ifdef USBDEVICELIBUSB_ENABLED + #undef USBDEVICELIBUSB_ENABLED + #endif + #ifdef USBDEVICEPRINTER_ENABLED + #undef USBDEVICEPRINTER_ENABLED + #endif + + + #ifdef USBHOSTHIDCOM_ENABLED + #undef USBHOSTHIDCOM_ENABLED + #endif + #ifdef USBHOSTHIDKEYBOARD_ENABLED + #undef USBHOSTHIDKEYBOARD_ENABLED + #endif + #ifdef USBHOSTHIDMOUSE_ENABLED + #undef USBHOSTHIDMOUSE_ENABLED + #endif + #ifdef USBHOSTMASSSTORAGE_ENABLED + #undef USBHOSTMASSSTORAGE_ENABLED + #endif + + #define USBDEVICECDCCOM_ENABLED PDL_USBDEVICECDCCOM_ENABLED + #define USBDEVICEHIDCOM_ENABLED PDL_USBDEVICEHIDCOM_ENABLED + #define USBDEVICEHIDJOYSTICK_ENABLED PDL_USBDEVICEHIDJOYSTICK_ENABLED + #define USBDEVICEHIDKEYBOARD_ENABLED PDL_USBDEVICEHIDKEYBOARD_ENABLED + #define USBDEVICEHIDMOUSE_ENABLED PDL_USBDEVICEHIDMOUSE_ENABLED + #define USBDEVICELIBUSB_ENABLED PDL_USBDEVICELIBUSB_ENABLED + #define USBDEVICEPRINTER_ENABLED PDL_USBDEVICEPRINTER_ENABLED + #define USBDEVICEMASSSTORAGE_ENABLED PDL_USBDEVICEMASSSTORAGE_ENABLED + + #define USBHOSTHIDCOM_ENABLED PDL_USBHOSTHIDCOM_ENABLED + #define USBHOSTHIDKEYBOARD_ENABLED PDL_USBHOSTHIDKEYBOARD_ENABLED + #define USBHOSTHIDMOUSE_ENABLED PDL_USBHOSTHIDMOUSE_ENABLED + #define USBHOSTMASSSTORAGE_ENABLED PDL_USBHOSTMASSSTORAGE_ENABLED + #define USBHOSTNDIS_ENABLED PDL_USBHOSTNDIS_ENABLED + #define USBHOSTPRINTER_ENABLED PDL_USBHOSTPRINTER_ENABLED + +#else + #error USB low level driver must be used standalone, with L3 or with PDL +#endif + +#if !defined(FM_PERIPHERAL_ENABLE_USB0_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE OFF +#endif + +#if !defined(FM_PERIPHERAL_ENABLE_USB1_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE OFF +#endif + +#if !defined(FM_PERIPHERAL_ENABLE_USB0_HOST) + #define FM_PERIPHERAL_ENABLE_USB0_HOST OFF +#endif + +#if !defined(FM_PERIPHERAL_ENABLE_USB1_HOST) + #define FM_PERIPHERAL_ENABLE_USB1_HOST OFF +#endif + +#if (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON) || (FM_PERIPHERAL_ENABLE_USB0_HOST == ON) + #define FM_PERIPHERAL_ENABLE_USB0 ON +#else + #define FM_PERIPHERAL_ENABLE_USB0 OFF +#endif + +#if (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON) || (FM_PERIPHERAL_ENABLE_USB1_HOST == ON) + #define FM_PERIPHERAL_ENABLE_USB1 ON +#else + #define FM_PERIPHERAL_ENABLE_USB1 OFF +#endif + +#if (FM_PERIPHERAL_ENABLE_USB0_HOST == ON) || (FM_PERIPHERAL_ENABLE_USB1_HOST == ON) + #define FM_PERIPHERAL_USB_HOST_ENABLED ON +#else + #define FM_PERIPHERAL_USB_HOST_ENABLED OFF + #define USB_DISBALE_HOST_FUNCTIONALITY OFF +#endif + +#if (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON) || (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON) + #define FM_PERIPHERAL_USB_DEVICE_ENABLED ON +#else + #define FM_PERIPHERAL_USB_DEVICE_ENABLED OFF + #define USB_DISBALE_DEVICE_FUNCTIONALITY OFF +#endif + +#define USB_ENABLED ((FM_PERIPHERAL_ENABLE_USB0 == ON) || (FM_PERIPHERAL_ENABLE_USB1 == ON)) +#define USB_INTERFACES_COUNT ((FM_PERIPHERAL_ENABLE_USB0) + (FM_PERIPHERAL_ENABLE_USB1)) +#define USB_INSTANCE_COUNT ((FM_PERIPHERAL_ENABLE_USB0) + (FM_PERIPHERAL_ENABLE_USB1)) +#define USB_DEVICE_INTERFACES_COUNT ((FM_PERIPHERAL_ENABLE_USB0_DEVICE) + (FM_PERIPHERAL_ENABLE_USB1_DEVICE)) +#define USB_HOST_INTERFACES_COUNT ((FM_PERIPHERAL_ENABLE_USB0_HOST) + (FM_PERIPHERAL_ENABLE_USB1_HOST)) + + +#if (USEUSBDBG == 1) +#include "uart.h" +#define USBDBG(x) DBGSPACES(u8DebugDepth); puts(x) +#define USBDBGVAL8(x,y) DBGSPACES(u8DebugDepth); puts(x); puthex((uint32_t)y,2); puts("\n") +#define USBDBGVAL16(x,y) DBGSPACES(u8DebugDepth); puts(x); puthex((uint32_t)y,4); puts("\n") +#define USBDBGVAL32(x,y) DBGSPACES(u8DebugDepth); puts(x); puthex((uint32_t)y,8); puts("\n") +#define DBGPROCENTER(x) DBGSPACES(u8DebugDepth); u8DebugDepth++; puts(">"); puts(x);puts("\n"); +#define DBGPROCRETURN(x) if (u8DebugDepth > 0) u8DebugDepth--;DBGSPACES(u8DebugDepth);puts("<"); puts(x);puts("\n"); +#define DBGSPACES(x) for(u8Dbgi = 0;u8Dbgi < x*2;u8Dbgi++) putch(' ') +volatile extern uint8_t u8DebugDepth; +volatile extern uint8_t u8Dbgi; +#else +#define USBDBG(x) +#define USBDBGVAL8(x,y) +#define USBDBGVAL16(x,y) +#define USBDBGVAL32(x,y) +#define DBGPROCENTER(x) +#define DBGPROCRETURN(x) +#define DBGSPACES(x) +#endif + +#define SETACTIVEFLAG(x) while((x) == FALSE) (x) = TRUE; +#define CLEARACTIVEFLAG(x) while((x) == TRUE) (x) = FALSE; + +#define USB_ZERO_STRUCT(x) memset(&x,0,sizeof(x)) +#define ZERO_STRUCT(x) memset(&x,0,sizeof(x)) + +#if defined(__USB_C__) + #if (USEUSBDBG == 1) + volatile uint8_t u8DebugDepth = 0; + volatile uint8_t u8Dbgi = 0; + #warning USB DEBUG ENABLED + #endif + #if (USBWARNLEVEL == 2) + +#warning *************** Library Usage ************************** + #if (USB_USE_STANDALONE == ON) + #warning Info: USB_USE_STANDALONE == ON + #else + #warning Info: USB_USE_STANDALONE == OFF + #endif + + #if (USB_USE_L3 == ON) + #warning Info: USB_USE_L3 == ON + #else + #warning Info: USB_USE_L3 == OFF + #endif + + #if (USB_USE_PDL == ON) + #warning Info: USB_USE_PDL == ON + #else + #warning Info: USB_USE_PDL == OFF + #endif + +#warning *************** USB Enabled Interfaces ***************** + #if USB_INTERFACES_COUNT == 0 + #warning Info: USB_INTERFACES_COUNT == 0 + #elif USB_INTERFACES_COUNT == 2 + #warning Info: USB_INTERFACES_COUNT == 2 + #elif USB_INTERFACES_COUNT == 3 + #warning Info: USB_INTERFACES_COUNT == 3 + #elif USB_INTERFACES_COUNT == 4 + #warning Info: USB_INTERFACES_COUNT == 4 + #elif USB_INTERFACES_COUNT == 5 + #warning Info: USB_INTERFACES_COUNT == 5 + #elif USB_INTERFACES_COUNT == 6 + #warning Info: USB_INTERFACES_COUNT == 6 + #endif + + #if (FM_PERIPHERAL_USB_HOST_ENABLED == OFF) + #warning Info: HOST EXCLUDED + #endif + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == OFF) + #warning Info: DEVICE EXCLUDED + #endif + + #if (FM_PERIPHERAL_ENABLE_USB0_HOST == ON) + #warning Info: FM_PERIPHERAL_ENABLE_USB0_HOST == ON + #else + #warning Info: FM_PERIPHERAL_ENABLE_USB0_HOST == OFF + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1_HOST == ON) + #warning Info: FM_PERIPHERAL_ENABLE_USB1_HOST == ON + #else + #warning Info: FM_PERIPHERAL_ENABLE_USB1_HOST == OFF + #endif + + #if (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON) + #warning Info: FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON + #else + #warning Info: FM_PERIPHERAL_ENABLE_USB0_DEVICE == OFF + #endif + + #if (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON) + #warning Info: FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON + #else + #warning Info: FM_PERIPHERAL_ENABLE_USB1_DEVICE == OFF + #endif + +#warning *************** USB Middleware Device ************************* + #if USBDEVICECDCCOM_ENABLED == ON + #warning Info: USBDEVICECDCCOM_ENABLED == ON + #else + #warning Info: USBDEVICECDCCOM_ENABLED == OFF + #endif + + #if USBDEVICEHIDJOYSTICK == ON + #warning Info: USBDEVICEHIDJOYSTICK == ON + #else + #warning Info: USBDEVICEHIDJOYSTICK == OFF + #endif + + #if USBDEVICEHIDKEYBOARD_ENABLED == ON + #warning Info: USBDEVICEHIDKEYBOARD_ENABLED == ON + #else + #warning Info: USBDEVICEHIDKEYBOARD_ENABLED == OFF + #endif + + #if USBDEVICEMOUSE_ENABLED == ON + #warning Info: USBDEVICEMOUSE_ENABLED == ON + #else + #warning Info: USBDEVICEMOUSE_ENABLED == OFF + #endif + + #if USBDEVICELIBUSB_ENABLED == ON + #warning Info: USBDEVICELIBUSB_ENABLED == ON + #else + #warning Info: USBDEVICELIBUSB_ENABLED == OFF + #endif + + #if USBDEVICEPRINTER_ENABLED == ON + #warning Info: USBDEVICEPRINTER_ENABLED == ON + #else + #warning Info: USBDEVICEPRINTER_ENABLED == OFF + #endif + + #if USBDEVICEMASSSTORAGE_ENABLED == ON + #warning Info: USBDEVICEMASSSTORAGE_ENABLED == ON + #else + #warning Info: USBDEVICEMASSSTORAGE_ENABLED == OFF + #endif + + +#warning *************** USB Middleware Host ************************* + #if USBHOSTHIDCOM_ENABLED == ON + #warning Info: USBHOSTHIDCOM_ENABLED == ON + #else + #warning Info: USBHOSTHIDCOM_ENABLED == OFF + #endif + + #if USBHOSTHIDKEYBOARD_ENABLED == ON + #warning Info: USBHOSTHIDKEYBOARD_ENABLED == ON + #else + #warning Info: USBHOSTHIDKEYBOARD_ENABLED == OFF + #endif + + #if USBHOSTHIDMOUSE_ENABLED == ON + #warning Info: USBHOSTHIDMOUSE_ENABLED == ON + #else + #warning Info: USBHOSTHIDMOUSE_ENABLED == OFF + #endif + + #if USBHOSTMASSSTORAGE_ENABLED == ON + #warning Info: USBHOSTMASSSTORAGE_ENABLED == ON + #else + #warning Info: USBHOSTMASSSTORAGE_ENABLED == OFF + #endif + + #if USBHOSTPRINTER_ENABLED == ON + #warning Info: USBHOSTPRINTER_ENABLED == ON + #else + #warning Info: USBHOSTPRINTER_ENABLED == OFF + #endif + + #if USBHOSTNDIS_ENABLED == ON + #warning Info: USBHOSTNDIS_ENABLED == ON + #else + #warning Info: USBHOSTNDIS_ENABLED == OFF + #endif + + +#warning *************** USB IRQ Settings *********************** + #if USB0_DEVICE_IRQ_ENABLED == ON + #warning Info: USB0_DEVICE_IRQ_ENABLED == ON + #else + #warning Info: USB0_DEVICE_IRQ_ENABLED == OFF + #endif + #if USB0_HOST_IRQ_ENABLED == ON + #warning Info: USB0_HOST_IRQ_ENABLED == ON + #else + #warning Info: USB0_HOST_IRQ_ENABLED == OFF + #endif + #if USB1_DEVICE_IRQ_ENABLED == ON + #warning Info: USB1_DEVICE_IRQ_ENABLED == ON + #else + #warning Info: USB1_DEVICE_IRQ_ENABLED == OFF + #endif + #if USB1_HOST_IRQ_ENABLED == ON + #warning Info: USB1_HOST_IRQ_ENABLED == ON + #else + #warning Info: USB1_HOST_IRQ_ENABLED == OFF + #endif + #if IRQ_LEVEL_USB0 == 0 + #warning Info: IRQ_LEVEL_USB0 == 0 + #elif IRQ_LEVEL_USB0 == 1 + #warning Info: IRQ_LEVEL_USB0 == 1 + #elif IRQ_LEVEL_USB0 == 2 + #warning Info: IRQ_LEVEL_USB0 == 2 + #elif IRQ_LEVEL_USB0 == 3 + #warning Info: IRQ_LEVEL_USB0 == 3 + #elif IRQ_LEVEL_USB0 == 4 + #warning Info: IRQ_LEVEL_USB0 == 4 + #elif IRQ_LEVEL_USB0 == 5 + #warning Info: IRQ_LEVEL_USB0 == 5 + #elif IRQ_LEVEL_USB0 == 6 + #warning Info: IRQ_LEVEL_USB0 == 6 + #elif IRQ_LEVEL_USB0 == 7 + #warning Info: IRQ_LEVEL_USB0 == 7 + #elif IRQ_LEVEL_USB0 == 8 + #warning Info: IRQ_LEVEL_USB0 == 8 + #elif IRQ_LEVEL_USB0 == 9 + #warning Info: IRQ_LEVEL_USB0 == 9 + #elif IRQ_LEVEL_USB0 == 10 + #warning Info: IRQ_LEVEL_USB0 == 10 + #elif IRQ_LEVEL_USB0 == 11 + #warning Info: IRQ_LEVEL_USB0 == 11 + #elif IRQ_LEVEL_USB0 == 12 + #warning Info: IRQ_LEVEL_USB0 == 12 + #elif IRQ_LEVEL_USB0 == 13 + #warning Info: IRQ_LEVEL_USB0 == 13 + #elif IRQ_LEVEL_USB0 == 14 + #warning Info: IRQ_LEVEL_USB0 == 14 + #elif IRQ_LEVEL_USB0 == 15 + #warning Info: IRQ_LEVEL_USB0 == 15 + #endif + + #if IRQ_LEVEL_USB1 == 0 + #warning Info: IRQ_LEVEL_USB1 == 0 + #elif IRQ_LEVEL_USB1 == 1 + #warning Info: IRQ_LEVEL_USB1 == 1 + #elif IRQ_LEVEL_USB1 == 2 + #warning Info: IRQ_LEVEL_USB1 == 2 + #elif IRQ_LEVEL_USB1 == 3 + #warning Info: IRQ_LEVEL_USB1 == 3 + #elif IRQ_LEVEL_USB1 == 4 + #warning Info: IRQ_LEVEL_USB1 == 4 + #elif IRQ_LEVEL_USB1 == 5 + #warning Info: IRQ_LEVEL_USB1 == 5 + #elif IRQ_LEVEL_USB1 == 6 + #warning Info: IRQ_LEVEL_USB1 == 6 + #elif IRQ_LEVEL_USB1 == 7 + #warning Info: IRQ_LEVEL_USB1 == 7 + #elif IRQ_LEVEL_USB1 == 8 + #warning Info: IRQ_LEVEL_USB1 == 8 + #elif IRQ_LEVEL_USB1 == 9 + #warning Info: IRQ_LEVEL_USB1 == 9 + #elif IRQ_LEVEL_USB1 == 10 + #warning Info: IRQ_LEVEL_USB1 == 10 + #elif IRQ_LEVEL_USB1 == 11 + #warning Info: IRQ_LEVEL_USB1 == 11 + #elif IRQ_LEVEL_USB1 == 12 + #warning Info: IRQ_LEVEL_USB1 == 12 + #elif IRQ_LEVEL_USB1 == 13 + #warning Info: IRQ_LEVEL_USB1 == 13 + #elif IRQ_LEVEL_USB1 == 14 + #warning Info: IRQ_LEVEL_USB1 == 14 + #elif IRQ_LEVEL_USB1 == 15 + #warning Info: IRQ_LEVEL_USB1 == 15 + #endif + #endif + + #if IRQ_LEVEL_USB0 > 15 + #error IRQ_LEVEL_USB0 must be <= 15 + #endif + + #if IRQ_LEVEL_USB1 > 15 + #error IRQ_LEVEL_USB1 must be <= 15 + #endif +#endif + + + +#define USBDESCR_DEVICE 1U +#define USBDESCR_CONFIG 2U +#define USBDESCR_STRING 3U +#define USBDESCR_INTERFACE 4U +#define USBDESCR_ENDPOINT 5U + +#define USB_DEVREQ_STDTYPE 0x00 +#define USB_DEVREQ_CLSTYPE 0x20 +#define USB_DEVREQ_VNDTYPE 0x40 + +#define USB_DEVREQ_GET_DESC 0x06 +#define USB_DEVREQ_SET_DESC 0x07 +#define USB_DEVREQ_SET_IDLE 0x0A + +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C + +#define USBATTR_BUSPOWER 0x80 +#define USBATTR_SELFPOWER 0xC0 +#define USBATTR_REMOTEWAKE 0x20 + +#define USB_FUNC_INTR_IN 0xF000 +#define USB_FUNC_INTR_OUT 0xE000 +#define USB_FUNC_BULK_IN 0xD000 +#define USB_FUNC_BULK_OUT 0xC000 + +#define USB_MASK_EPC_PKS 0x007F +#define USB_MASK_EPC_PKS1 0x01FF +#define USB_MASK_EPC_STAL 0x0200 +#define USB_MASK_EPC_NULE 0x0400 +#define USB_MASK_EPC_DMAE 0x0800 +#define USB_MASK_EPC_DIR 0x1000 +#define USB_MASK_EPC_TYPE 0x6000 +#define USB_MASK_EPC_EPEN 0x8000 + +#define USB_MASK_EPS_DRQIIE 0x4000 +#define USB_MASK_EPS_BFINI 0x8000 +#define USB_MASK_EPS_SIZE1 0x01FF +#define USB_MASK_EPS_SIZE 0x007F +#define USB_MASK_EPS_SPK 0x0200 +#define USB_MASK_EPS_DRQI 0x0400 +#define USB_MASK_EPS_DRQO 0x0400 +#define USB_MASK_EPS_DRQ 0x0400 +#define USB_MASK_EPS_BUSY 0x0800 +#define USB_MASK_EPS_SPKIE 0x2000 +#define USB_MASK_EPS_DRQIE 0x4000 +#define USB_MASK_EPS_DRQOIE 0x4000 +#define USB_MASK_EPS_BFINI 0x8000 + +#ifndef BITMASK_ISSET +#define BITMASK_ISSET(x,y) ((x & y) != 0) +#endif + +#ifndef BITMASK_ISCLEARED +#define BITMASK_ISCLEARED(x,y) ((x & y) == 0) +#endif + +#ifndef BITMASK_SET +#define BITMASK_SET(x,y) x |= y +#endif + +#ifndef BITMASK_CLEAR +#define BITMASK_CLEAR(x,y) x &= ~y +#endif + +#ifndef USBREG_BITBAND_ADDRESS +#define USBREG_BITBAND_ADDRESS(registeraddress,bit) ((volatile uint32_t*)(0x42000000 + ((uint32_t)registeraddress - (uint32_t)0x40000000UL) * 32 + 4 * bit)) +#endif + +#ifndef USBREG_BIT_SET +#define USBREG_BIT_SET(registeraddress,bit) *((volatile uint32_t*)(0x42000000 + ((uint32_t)registeraddress - (uint32_t)0x40000000UL) * 32 + 4 * bit)) = 1 +#endif + +#ifndef USBREG_BIT_CLEAR +#define USBREG_BIT_CLEAR(registeraddress,bit) *((volatile uint32_t*)(0x42000000 + ((uint32_t)registeraddress - (uint32_t)0x40000000UL) * 32 + 4 * bit)) = 0 +#endif + +#ifndef USBREG_BIT_ISSET +#define USBREG_BIT_ISSET(registeraddress,bit) (*((volatile uint32_t*)(0x42000000 + ((uint32_t)registeraddress - (uint32_t)0x40000000UL) * 32 + 4 * bit)) == 1) +#endif + +#ifndef __USBBITDEFINITIONS_H__ + #define __USBBITDEFINITIONS_H__ + #define _UDCC_RST (1 << 7) ///< Function reset bit + #define UDCC_RST_BIT 7u ///< Function reset bit + #define bUSB_UDCC_RST(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCC,UDCC_RST_BIT)) + #define USB_UDCC_RST_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCC,UDCC_RST_BIT) + #define USB_UDCC_RST_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCC,UDCC_RST_BIT) + #define USB_UDCC_RST_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCC,UDCC_RST_BIT) + #define _UDCC_RESUM (1 << 6) ///< Resume setting bit + #define UDCC_RESUM_BIT 6u ///< Resume setting bit + #define bUSB_UDCC_RESUM(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCC,UDCC_RESUM_BIT)) + #define USB_UDCC_RESUM_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCC,UDCC_RESUM_BIT) + #define USB_UDCC_RESUM_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCC,UDCC_RESUM_BIT) + #define USB_UDCC_RESUM_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCC,UDCC_RESUM_BIT) + #define _UDCC_HCONX (1 << 5) ///< Host connection bit + #define UDCC_HCONX_BIT 5u ///< Host connection bit + #define bUSB_UDCC_HCONX(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCC,UDCC_HCONX_BIT)) + #define USB_UDCC_HCONX_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCC,UDCC_HCONX_BIT) + #define USB_UDCC_HCONX_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCC,UDCC_HCONX_BIT) + #define USB_UDCC_HCONX_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCC,UDCC_HCONX_BIT) + #define _UDCC_USTP (1 << 4) ///< USB operation clock stop bit + #define UDCC_USTP_BIT 4u ///< USB operation clock stop bit + #define bUSB_UDCC_USTP(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCC,UDCC_USTP_BIT)) + #define USB_UDCC_USTP_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCC,UDCC_USTP_BIT) + #define USB_UDCC_USTP_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCC,UDCC_USTP_BIT) + #define USB_UDCC_USTP_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCC,UDCC_USTP_BIT) + #define _UDCC_RFBK (1 << 1) ///< Data toggle mode bit (Rate feedback mode) + #define UDCC_RFBK_BIT 1u ///< Data toggle mode bit (Rate feedback mode) + #define bUSB_UDCC_RFBK(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCC,UDCC_RFBK_BIT)) + #define USB_UDCC_RFBK_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCC,UDCC_RFBK_BIT) + #define USB_UDCC_RFBK_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCC,UDCC_RFBK_BIT) + #define USB_UDCC_RFBK_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCC,UDCC_RFBK_BIT) + #define _UDCC_PWC (1 << 0) ///< Power supply control bit + #define UDCC_PWC_BIT 0u ///< Power supply control bit + #define bUSB_UDCC_PWC(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCC,UDCC_PWC_BIT)) + #define USB_UDCC_PWC_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCC,UDCC_PWC_BIT) + #define USB_UDCC_PWC_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCC,UDCC_PWC_BIT) + #define USB_UDCC_PWC_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCC,UDCC_PWC_BIT) + + #define _EP0C_PKS0 0x7F ///< EP0 packet size setting bits + #define _EP0C_STAL (1 << 9) ///< STALL set bit + #define EP0C_STAL_BIT 9u ///< STALL set bit + #define bUSB_EP0C_STAL(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->EP0C,EP0C_STAL_BIT)) + #define USB_EP0C_STAL_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->EP0C,EP0C_STAL_BIT) + #define USB_EP0C_STAL_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->EP0C,EP0C_STAL_BIT) + #define USB_EP0C_STAL_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->EP0C,EP0C_STAL_BIT) + + #define _EPNC_STAL (1 << 9) ///< STALL set bit + #define EPNC_STAL_BIT 9u ///< STALL set bit + #define bUSB_EPNC_STAL(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNC_STAL_BIT)) + #define USB_EPNC_STAL_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNC_STAL_BIT) + #define USB_EPNC_STAL_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNC_STAL_BIT) + #define USB_EPNC_STAL_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNC_STAL_BIT) + #define _EPNC_NULE (1 << 10) ///< NULL automatic transfer enable bit + #define EPNC_NULE_BIT 10u ///< NULL automatic transfer enable bit + #define bUSB_EPNC_NULE(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNC_NULE_BIT)) + #define USB_EPNC_NULE_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNC_NULE_BIT) + #define USB_EPNC_NULE_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNC_NULE_BIT) + #define USB_EPNC_NULE_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNC_NULE_BIT) + #define _EPNC_DMAE (1 << 11) ///< DMA automatic transfer enable bit + #define EPNC_DMAE_BIT 11u ///< DMA automatic transfer enable bit + #define bUSB_EPNC_DMAE(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNC_DMAE_BIT)) + #define USB_EPNC_DMAE_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNC_DMAE_BIT) + #define USB_EPNC_DMAE_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNC_DMAE_BIT) + #define USB_EPNC_DMAE_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNC_DMAE_BIT) + #define _EPNC_DIR (1 << 12) ///< Endpoint direction selection bit + #define EPNC_DIR_BIT 12u ///< Endpoint direction selection bit + #define bUSB_EPNC_DIR(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNC_DIR_BIT)) + #define USB_EPNC_DIR_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNC_DIR_BIT) + #define USB_EPNC_DIR_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNC_DIR_BIT) + #define USB_EPNC_DIR_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNC_DIR_BIT) + #define _EPNC_TYPE 0x6000 ///< Endpoint transfer type bit + #define _EPNC_EPEN (1 << 15) ///< Endpoint Enable bit + #define EPNC_EPEN_BIT 15u ///< Endpoint Enable bit + #define bUSB_EPNC_EPEN(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNC_EPEN_BIT)) + #define USB_EPNC_EPEN_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNC_EPEN_BIT) + #define USB_EPNC_EPEN_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNC_EPEN_BIT) + #define USB_EPNC_EPEN_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNC_EPEN_BIT) + + /* romoved while using EPNC + #define _EP1C_PKS1 0x1FF ///< EP1 packet size setting bits + #define _EP1C_STAL (1 << 9) ///< STALL set bit + #define _EP1C_NULE (1 << 10) ///< NULL automatic transfer enable bit + #define _EP1C_DMAE (1 << 11) ///< DMA automatic transfer enable bit + #define _EP1C_DIR (1 << 12) ///< Endpoint direction selection bit + #define _EP1C_TYPE 0x6000 ///< Endpoint transfer type bit + #define _EP1C_EPEN (1 << 15) ///< Endpoint Enable bit + + #define _EP2C_PKS2 0xFF ///< EP2 packet size setting bits + #define _EP2C_STAL (1 << 9) ///< STALL set bit + #define _EP2C_NULE (1 << 10) ///< NULL automatic transfer enable bit + #define _EP2C_DMAE (1 << 11) ///< DMA automatic transfer enable bit + #define _EP2C_DIR (1 << 12) ///< Endpoint direction selection bit + #define _EP2C_TYPE 0x6000 ///< Endpoint transfer type bit + #define _EP2C_EPEN (1 << 15) ///< Endpoint Enable bit + + #define _EP3C_PKS3 0xFF ///< EP3 packet size setting bits + #define _EP3C_STAL (1 << 9) ///< STALL set bit + #define _EP3C_NULE (1 << 10) ///< NULL automatic transfer enable bit + #define _EP3C_DMAE (1 << 11) ///< DMA automatic transfer enable bit + #define _EP3C_DIR (1 << 12) ///< Endpoint direction selection bit + #define _EP3C_TYPE 0x6000 ///< Endpoint transfer type bit + #define _EP3C_EPEN (1 << 15) ///< Endpoint Enable bit + + #define _EP4C_PKS4 0xFF ///< EP4 packet size setting bits + #define _EP4C_STAL (1 << 9) ///< STALL set bit + #define _EP4C_NULE (1 << 10) ///< NULL automatic transfer enable bit + #define _EP4C_DMAE (1 << 11) ///< DMA automatic transfer enable bit + #define _EP4C_DIR (1 << 12) ///< Endpoint direction selection bit + #define _EP4C_TYPE 0x6000 ///< Endpoint transfer type bit + #define _EP4C_EPEN (1 << 15) ///< Endpoint Enable bit + + #define _EP5C_PKS5 0xFF ///< EP packet size setting bits + #define _EP5C_STAL (1 << 9) ///< STALL set bit + #define _EP5C_NULE (1 << 10) ///< NULL automatic transfer enable bit + #define _EP5C_DMAE (1 << 11) ///< DMA automatic transfer enable bit + #define _EP5C_DIR (1 << 12) ///< Endpoint direction selection bit + #define _EP5C_TYPE 0x6000 ///< Endpoint transfer type bit + #define _EP5C_EPEN (1 << 15) ///< Endpoint Enable bit*/ + + #define _EPC_TYPE_BULK 0x4000 + #define _EPC_TYPE_INTERRUPT 0x6000 + + #define _UDCS_CONF (1 << 0) ///< Configuration detection bit + #define UDCS_CONF_BIT 0u ///< Configuration detection bit + #define bUSB_UDCS_CONF(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCS,UDCS_CONF_BIT)) + #define USB_UDCS_CONF_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCS,UDCS_CONF_BIT) + #define USB_UDCS_CONF_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCS,UDCS_CONF_BIT) + #define USB_UDCS_CONF_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCS,UDCS_CONF_BIT) + #define _UDCS_SETP (1 << 1) ///< Setup stage detection bit + #define UDCS_SETP_BIT 1u ///< Setup stage detection bit + #define bUSB_UDCS_SETP(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCS,UDCS_SETP_BIT)) + #define USB_UDCS_SETP_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCS,UDCS_SETP_BIT) + #define USB_UDCS_SETP_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCS,UDCS_SETP_BIT) + #define USB_UDCS_SETP_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCS,UDCS_SETP_BIT) + #define _UDCS_WKUP (1 << 2) ///< Wake-up detection bit + #define UDCS_WKUP_BIT 2u ///< Wake-up detection bit + #define bUSB_UDCS_WKUP(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCS,UDCS_WKUP_BIT)) + #define USB_UDCS_WKUP_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCS,UDCS_WKUP_BIT) + #define USB_UDCS_WKUP_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCS,UDCS_WKUP_BIT) + #define USB_UDCS_WKUP_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCS,UDCS_WKUP_BIT) + #define _UDCS_BRST (1 << 3) ///< Bus reset detection bit + #define UDCS_BRST_BIT 3u ///< Bus reset detection bit + #define bUSB_UDCS_BRST(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCS,UDCS_BRST_BIT)) + #define USB_UDCS_BRST_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCS,UDCS_BRST_BIT) + #define USB_UDCS_BRST_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCS,UDCS_BRST_BIT) + #define USB_UDCS_BRST_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCS,UDCS_BRST_BIT) + #define _UDCS_SOF (1 << 4) ///< SOF reception detection bit + #define UDCS_SOF_BIT 4u ///< SOF reception detection bit + #define bUSB_UDCS_SOF(pstcUsb) *(USBREG_BITBAND_ADDRESS(pstcUsb->UDCS,UDCS_SOF_BIT)) + #define USB_UDCS_SOF_SET(pstcUsb) USBREG_BIT_SET(pstcUsb->UDCS,UDCS_SOF_BIT) + #define USB_UDCS_SOF_CLEAR(pstcUsb) USBREG_BIT_CLEAR(pstcUsb->UDCS,UDCS_SOF_BIT) + #define USB_UDCS_SOF_ISSET(pstcUsb) USBREG_BIT_ISSET(pstcUsb->UDCS,UDCS_SOF_BIT) + #define _UDCS_SUSP (1 << 5) ///< Suspend detection bit + + #define _UDCIE_CONFIE (1 << 0) ///< Configuration interrupt enable bit + #define _UDCIE_CONFN (1 << 1) ///< Configuration number bit + #define _UDCIE_WKUPIE (1 << 2) ///< Wake-up interrupt enable bit + #define _UDCIE_BRSTIE (1 << 3) ///< Bus reset interrupt enable bit + #define _UDCIE_SOFIE (1 << 4) ///< SOF receive interrupt enable bit + #define _UDCIE_SUSPIE (1 << 5) ///< Suspend interrupt enable bit + + #define _EPNS_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define EPNS_SPK_BIT 9u ///< Short Packet interrupt flag bit + #define bUSB_EPNS_SPK(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNS_SPK_BIT)) + #define USB_EPNS_SPK_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNS_SPK_BIT) + #define USB_EPNS_SPK_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNS_SPK_BIT) + #define USB_EPNS_SPK_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNS_SPK_BIT) + #define _EPNS_DRQ (1 << 10) ///< Packet transfer interrupt flag bit + #define EPNS_DRQ_BIT 10u ///< Packet transfer interrupt flag bit + #define bUSB_EPNS_DRQ(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNS_DRQ_BIT)) + #define USB_EPNS_DRQ_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNS_DRQ_BIT) + #define USB_EPNS_DRQ_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNS_DRQ_BIT) + #define USB_EPNS_DRQ_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNS_DRQ_BIT) + #define _EPNS_BUSY (1 << 11) ///< Busy flag bit + #define EPNS_BUSY_BIT 11u ///< Busy flag bit + #define bUSB_EPNS_BUSY(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNS_BUSY_BIT)) + #define USB_EPNS_BUSY_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNS_BUSY_BIT) + #define USB_EPNS_BUSY_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNS_BUSY_BIT) + #define USB_EPNS_BUSY_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNS_BUSY_BIT) + #define _EPNS_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define EPNS_SPKIE_BIT 13u ///< Short packet interrupt enable bit + #define bUSB_EPNS_SPKIE(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNS_SPKIE_BIT)) + #define USB_EPNS_SPKIE_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNS_SPKIE_BIT) + #define USB_EPNS_SPKIE_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNS_SPKIE_BIT) + #define USB_EPNS_SPKIE_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNS_SPKIE_BIT) + #define _EPNS_DRQIE (1 << 14) ///< DRQ Interrupt enable bit + #define EPNS_DRQIE_BIT 14u ///< DRQ Interrupt enable bit + #define bUSB_EPNS_DRQIE(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNS_DRQIE_BIT)) + #define USB_EPNS_DRQIE_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNS_DRQIE_BIT) + #define USB_EPNS_DRQIE_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNS_DRQIE_BIT) + #define USB_EPNS_DRQIE_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNS_DRQIE_BIT) + #define _EPNS_BFINI (1 << 15) ///< Transmission/Reception buffer initialization bit + #define EPNS_BFINI_BIT 15u ///< Transmission/Reception buffer initialization bit + #define bUSB_EPNS_BFINI(pstcEp) *(USBREG_BITBAND_ADDRESS(pstcEp->pstcEpStatusRegister,EPNS_BFINI_BIT)) + #define USB_EPNS_BFINI_SET(pstcEp) USBREG_BIT_SET(pstcEp->pstcEpStatusRegister,EPNS_BFINI_BIT) + #define USB_EPNS_BFINI_CLEAR(pstcEp) USBREG_BIT_CLEAR(pstcEp->pstcEpStatusRegister,EPNS_BFINI_BIT) + #define USB_EPNS_BFINI_ISSET(pstcEp) USBREG_BIT_ISSET(pstcEp->pstcEpStatusRegister,EPNS_BFINI_BIT) + + #define _EP0IS_DRQI (1 << 10) ///< Transmit Data interrupt request bit + #define _EP0IS_DRQIIE (1 << 14) ///< Transmit Data Interrupt enable bit + #define _EP0IS_BFINI (1 << 15) ///< Transmission buffer initialization bit + + #define _EP0OS_SIZE 0x7F ///< Packet size bits + #define _EP0OS_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define _EP0OS_DRQO (1 << 10) ///< Received data interrupt flag bit + #define _EP0OS_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define _EP0OS_DRQOIE (1 << 14) ///< Receive Data Interrupt enable bit + #define _EP0OS_BFINI (1 << 15) ///< Receive buffer initialization bit + + /* romoved while using EPNS + #define _EP1S_SIZE 0x1FF ///< Packet size bits + #define _EP1S_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define _EP1S_DRQ (1 << 10) ///< Packet transfer interrupt flag bit + #define _EP1S_BUSY (1 << 11) ///< Busy flag bit + #define _EP1S_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define _EP1S_DRQIE (1 << 14) ///< DRQ Interrupt enable bit + #define _EP1S_BFINI (1 << 15) ///< Transmission/Reception buffer initialization bit + + #define _EP2S_SIZE 0xFF ///< Packet size bits + #define _EP2S_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define _EP2S_DRQ (1 << 10) ///< Packet transfer interrupt flag bit + #define _EP2S_BUSY (1 << 11) ///< Busy flag bit + #define _EP2S_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define _EP2S_DRQIE (1 << 14) ///< DRQ Interrupt enable bit + #define _EP2S_BFINI (1 << 15) ///< Transmission/Reception buffer initialization bit + + #define _EP3S_SIZE 0xFF ///< Packet size bits + #define _EP3S_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define _EP3S_DRQ (1 << 10) ///< Packet transfer interrupt flag bit + #define _EP3S_BUSY (1 << 11) ///< Busy flag bit + #define _EP3S_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define _EP3S_DRQIE (1 << 14) ///< DRQ Interrupt enable bit + #define _EP3S_BFINI (1 << 15) ///< Transmission/Reception buffer initialization bit + + #define _EP4S_SIZE 0xFF ///< Packet size bits + #define _EP4S_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define _EP4S_DRQ (1 << 10) ///< Packet transfer interrupt flag bit + #define _EP4S_BUSY (1 << 11) ///< Busy flag bit + #define _EP4S_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define _EP4S_DRQIE (1 << 14) ///< DRQ Interrupt enable bit + #define _EP4S_BFINI (1 << 15) ///< Transmission/Reception buffer initialization bit + + #define _EP5S_SIZE 0xFF ///< Packet size bits + #define _EP5S_SPK (1 << 9) ///< Short Packet interrupt flag bit + #define _EP5S_DRQ (1 << 10) ///< Packet transfer interrupt flag bit + #define _EP5S_BUSY (1 << 11) ///< Busy flag bit + #define _EP5S_SPKIE (1 << 13) ///< Short packet interrupt enable bit + #define _EP5S_DRQIE (1 << 14) ///< DRQ Interrupt enable bit + #define _EP5S_BFINI (1 << 15) ///< Transmission/Reception buffer initialization bit + */ + + #define _HCNT_HOST (1 << 0) ///< HOST Mode bit + #define _HCNT_URST (1 << 1) ///< USB Bus Reset bit + #define _HCNT_SOFIRE (1 << 2) ///< SOF interrupt Enable bit + #define _HCNT_DIRE (1 << 3) ///< Disconnection interrupt Enable bit + #define _HCNT_CNNIRE (1 << 4) ///< Connection interrupt Enable bit + #define _HCNT_CMPIRE (1 << 5) ///< Completion interrupt Enable bit + #define _HCNT_URIRE (1 << 6) ///< USB bus Reset interrupt Enable bit + #define _HCNT_RWKIRE (1 << 7) ///< Remote Wake-up interrupt Enable bit + #define _HCNT_RETRY (1 << 8) ///< Retry enable bit + #define _HCNT_CANCEL (1 << 9) ///< Token cancel enable bit + #define _HCNT_SOFSTEP (1 << 10) ///< SOF interrupt trigger bit + + #define _HIRQ_SOFIRQ (1 << 0) ///< HOST Mode bit + #define _HIRQ_DIRQ (1 << 1) ///< USB Bus Reset bit + #define _HIRQ_CNNIRQ (1 << 2) ///< SOF interrupt Enable bit + #define _HIRQ_CMPIRQ (1 << 3) ///< Disconnection interrupt Enable bit + #define _HIRQ_URIRQ (1 << 4) ///< Connection interrupt Enable bit + #define _HIRQ_RWKIRQ (1 << 5) ///< Completion interrupt Enable bit + #define _HIRQ_TCAN (1 << 7) ///< Remote Wake-up interrupt Enable bit + + #define _HERR_HS 0x03 ///< Handshake Status + #define _HERR_STUFF (1 << 2) ///< Stuffing Error bit + #define _HERR_TGERR (1 << 3) ///< Toggle Error bit + #define _HERR_CRC (1 << 4) ///< CRC Error bit + #define _HERR_TOUT (1 << 5) ///< Time Out bit + #define _HERR_RERR (1 << 6) ///< Receive Error bit + #define _HERR_LSTSOF (1 << 7) ///< Lost SOF bit + + #define _HSTATE_CSTAT (1 << 0) ///< Connection status bit + #define _HSTATE_TMODE (1 << 1) ///< Transfer Mode bit + #define _HSTATE_SUSP (1 << 2) ///< Suspend bit + #define _HSTATE_SOFBUSY (1 << 3) ///< SOF timer operation bit + #define _HSTATE_CLKSEL (1 << 4) ///< Clock Selection bit (Full / Low Speed) + #define _HSTATE_ALIVE (1 << 5) ///< keep alive bit (for low speed) +#endif // __USBBITDEFINITIONS_H__ + +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +#ifndef __USBSPEC_H__ + #define __USBSPEC_H__ + + + #define GET_DESCRIPTOR 0x06 + #define USB_DEVICE_DESCRIPTOR_TYPE 0x01 ///< Usb Device Descriptor Type + #define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02 ///< Usb Configuration Descriptor Type + #define USB_STRING_DESCRIPTOR_TYPE 0x03 ///< Usb String Descriptor Type + #define USB_INTERFACE_DESCRIPTOR_TYPE 0x04 ///< Usb Interface Descriptor Type + #define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05 ///< Usb Endpoint Descriptor Type + #define USB_DEVICE_QUALIFIER_DESCRIPTOR_TYPE 0x06 ///< Usb Device Qualifier Descriptor Type + #define USB_OTHER_SPEED_CONFIGURATION_DESCRIPTOR_TYPE 0x07 ///< Usb Other Speed Configuratuion Descriptor Type + #define USB_HID_DESCRIPTOR_TYPE 0x21 ///< Usb HID Descriptor Type + + #define USB_IN_DIRECTION 0x80 ///< Usb IN direction + #define USB_OUT_DIRECTION 0x00 ///< Usb OUT direction + + #define USB_EP_TYPE_CONTROL 0x00 ///< Control Endpoint Type + #define USB_EP_TYPE_ISO 0x01 ///< ISO Endpoint Type + #define USB_EP_TYPE_BULK 0x02 ///< Bulk Endpoint Type + #define USB_EP_TYPE_INT 0x03 ///< Interrupt Endpoint Type + + // Bit-Band alias redefinition for L3 usage + #define bL3_FM3_GPIO_EPFR00_USB0PE *((volatile unsigned int*)(0x4266C024UL)) + #define bL3_FM3_GPIO_PFR6_P1 *((volatile unsigned int*)(0x42660304UL)) + #define bL3_FM3_GPIO_SPSR_USB0C *((volatile unsigned int*)(0x4266B010UL)) + #define bL3_FM3_GPIO_EPFR00_USB1PE *((volatile unsigned int*)(0x4266C034UL)) + #define bL3_FM3_GPIO_PFR2_P0 *((volatile unsigned int*)(0x42660100UL)) + #define bL3_FM3_GPIO_SPSR_USB1C *((volatile unsigned int*)(0x4266B014UL)) + + /****************************************************************************** + ** \brief Bitmask USB request type + ** + ******************************************************************************/ + typedef struct stc_bmRequestType + { + uint8_t Recipient :5; ///< Recipient + uint8_t Type :2; ///< Type + uint8_t DataPhaseTransferDirection :1; ///< Transfer direction + + } stc_bmRequestType_t; + + + /****************************************************************************** + ** \brief USB setup request type + ** + ******************************************************************************/ + typedef struct stc_usb_request + { + union { + uint8_t bmRequestType; ///< Usb request type as byte + stc_bmRequestType_t bmRequestType_f; ///< Usb request type as bit field + }; + uint8_t bRequest; ///< request + uint16_t wValue; ///< value + uint16_t wIndex; ///< index + uint16_t wLength; ///< length + } stc_usb_request_t; + + + /****************************************************************************** + ** \brief Setup package + ** + ******************************************************************************/ + typedef struct stc_usb_setup_package + { + stc_usb_request_t* pstcRequest; ///< USB setup request + uint8_t* pu8Buffer; ///< Buffer with data + } stc_usb_setup_package_t; +#endif // __USBSPEC_H__ + +#if USB_USE_LEGACYSUPPORT == 1u + #include "usblegacy.h" +#else + #if (!defined(FM_USB_AVAILABLE)) && (!defined(FM_USB0)) && (!defined(FM_USB1)) + #error For this configuration set USB_USE_LEGACYSUPPORT in usbconfig.h to 1 + #endif + #define stc_usbn_t FM_USB_TypeDef + + #if defined(FM_USB0_BASE) + #if IRQ_USBF_AVAILABLE == 1u + #define USBLIB_USB0_IRQn USBF_IRQn + #elif IRQ_USB0_AVAILABLE == 1u + #define USBLIB_USB0_IRQn USB0_IRQn + #elif IRQ_USB0_F_AVAILABLE + #define USBLIB_USB0_IRQn USB0_F_IRQn + #elif IRQ_USB0F_AVAILABLE + #define USBLIB_USB0_IRQn USB0F_IRQn + #elif IRQ_USB0_F_ED123_AVAILABLE + #define USBLIB_USB0_IRQn USB0_F_ED123_IRQn + #else + #error Unknown IRQn definition for USB0 IRQ + #endif + + #if IRQ_USB0_HOST_AVAILABLE == 1u + #define USBLIB_USB0_DEVHOST_IRQn USB0_HOST_IRQn + #elif IRQ_USBF_USBH_AVAILABLE == 1u + #define USBLIB_USB0_DEVHOST_IRQn USBF_USBH_IRQn + #elif IRQ_USB0_F_MFT0_ICU_AVAILABLE + #define USBLIB_USB0_DEVHOST_IRQn USB0_F_MFT0_ICU_IRQn + #elif IRQ_USB0F_USB0H_AVAILABLE + #define USBLIB_USB0_DEVHOST_IRQn USB0F_USB0H_IRQn + #elif IRQ_USB0_H_F_AVAILABLE + #define USBLIB_USB0_DEVHOST_IRQn USB0_H_F_IRQn + #elif IRQ_USB0_H_AVAILABLE + #define USBLIB_USB0_DEVHOST_IRQn USB0_H_IRQn + #else + #error Unknown IRQn definition for USB0 HOST IRQ + #endif + #endif + + #if defined(FM_USB1_BASE) + #if IRQ_USB1_AVAILABLE == 1u + #define USBLIB_USB1_IRQn USB1_IRQn + #elif IRQ_USB1F_AVAILABLE == 1u + #define USBLIB_USB1_IRQn USB1F_IRQn + #elif IRQ_USB1_HDMICEC0_AVAILABLE == 1u + #define USBLIB_USB1_IRQn USB1_HDMICEC0_IRQn + #elif IRQ_USB1_F_AVAILABLE == 1u + #define USBLIB_USB1_IRQn USB1_F_IRQn + #else + #error Unknown IRQn definition for USB1 IRQ + #endif + + #if IRQ_USB1_HOST_AVAILABLE == 1u + #define USBLIB_USB1_DEVHOST_IRQn USB1_HOST_IRQn + #elif IRQ_USB1F_USB1H_AVAILABLE == 1u + #define USBLIB_USB1_DEVHOST_IRQn USB1F_USB1H_IRQn + #elif IRQ_USB1_HOST_HDMICEC1_AVAILABLE == 1u + #define USBLIB_USB1_DEVHOST_IRQn USB1_HOST_HDMICEC1_IRQn + #elif IRQ_USB1_H_F_AVAILABLE + #define USBLIB_USB1_DEVHOST_IRQn USB1_H_F_IRQn + #else + #error Unknown IRQn definition for USB1 HOST IRQ + #endif + #endif + + +#endif + +/** + ****************************************************************************** + ** \cond USB_MODULE USB Module + ******************************************************************************/ + +/** + ****************************************************************************** + ** \endcond USB_MODULE End USB Module + ******************************************************************************/ + + +/****************************************************************************** + ** \brief String Descriptor + ** + ******************************************************************************/ +typedef struct stc_usbdevice_stringdescriptor +{ + uint8_t* pu8String; ///< String as ASCII + uint8_t* pu8UniCodeString; ///< String as Unicode +} stc_usbdevice_stringdescriptor_t; + +/****************************************************************************** + ** \brief Report Descriptor + ** + ******************************************************************************/ +typedef struct stc_usbdevice_reportdescriptor +{ + uint8_t* pu8Descriptor; ///< Descriptor Data + uint16_t u16Size; ///< Size +} stc_usbdevice_reportdescriptor_t; + +/****************************************************************************** + ** \brief Timeout handler + ** + ** Used to create timeout callbacks via SOF interrupt + ** + ******************************************************************************/ +typedef struct stc_usb_sof_timeout_handler +{ + uint16_t u16TimeOut; ///< Timeout in ms + void (* Handler)(stc_usbn_t* pstcUsb); ///< Callback after timeout +} stc_usb_sof_timeout_handler_t; + + +/****************************************************************************** + ** \brief GPIO / external interrupt settings enumeration + ** + ******************************************************************************/ +typedef enum en_usb_extint_param +{ + UsbExtIntDeinit = 0, ///< Deinitialize GPIO / external interrupt + UsbExtIntInit = 1, ///< Initialize GPIO / external interrupt + UsbExtIntDisableIsr = 2, ///< Disable external interrupt + UsbExtIntEnableIsr = 3, ///< Enable external interrupt + UsbExtIntClearIsrFlag = 4, ///< Clear external interrupt flag + UsbExtIntIsSetIsrFlag = 5, ///< Check external interrupt flag is set + UsbExtIntSetLowDetect = 6, ///< Set low level external interrupt + UsbExtIntSetHighDetect = 7, ///< Set high level external interrupt + UsbExtIntGetLevel = 8 ///< Get level of external interrupt +} en_usb_extint_param_t; + + +/****************************************************************************** + ** \brief GPIO settings enumeration + ** + ******************************************************************************/ +typedef enum en_usb_gpio_param +{ + UsbGpioDeinit = 0, ///< Deinitialize GPIO + UsbGpioInit = 1, ///< Initialize GPIO + UsbGpioSet = 2, ///< Set GPIO + UsbGpioClear = 3, ///< Clear GPIO + UsbGpioGet = 4 ///< Get state of GPIO +} en_usb_gpio_param_t; + + +/****************************************************************************** + ** \brief Device alternative HCONX callback + ** + ** \param en_usb_gpio_param_t type of callback + ** + ** \return depending of type of callback TRUE or FALSE + ** + ******************************************************************************/ +typedef boolean_t (*usb_device_alternative_hconx_t)(en_usb_gpio_param_t enType); + +/****************************************************************************** + ** \brief Device VBUS callback + ** + ** \param en_usb_gpio_param_t type of callback + ** + ** \return depending of type of callback TRUE or FALSE + ** + ******************************************************************************/ +typedef boolean_t (*usb_device_vbus_t)(en_usb_extint_param_t enType); + +/****************************************************************************** + ** \brief Host VBUS callback + ** + ** \param en_usb_gpio_param_t type of callback + ** + ** \return depending of type of callback TRUE or FALSE + ** + ******************************************************************************/ +typedef boolean_t (*usb_host_vbus_t)(en_usb_gpio_param_t enType); + +/****************************************************************************** + ** \brief Host pull-down callback + ** + ** \param en_usb_gpio_param_t type of callback + ** + ** \return depending of type of callback TRUE or FALSE + ** + ******************************************************************************/ +typedef boolean_t (*usb_host_pulldown_t)(en_usb_gpio_param_t enType); + +/****************************************************************************** + ** \brief Host overcurrent callback + ** + ** \param en_usb_gpio_param_t type of callback + ** + ** \return depending of type of callback TRUE or FALSE + ** + ******************************************************************************/ +typedef boolean_t (*usb_host_overcurrent_t)(en_usb_extint_param_t enType); + + +/****************************************************************************** + ** \brief USB endpoint type + ** + ******************************************************************************/ +typedef enum en_usb_ep_type +{ + EpTypeHost = 0, ///< used as host endpoint + EpTypeIso = 1, ///< ISO + EpTypeBulk = 2, ///< Bulk + EpTypeInterrupt = 3 ///< Interrupt +} en_usb_ep_type_t; + + +/****************************************************************************** + ** \brief USB endpoint buffer + ** + ******************************************************************************/ +typedef struct stc_usbn_endpoint_buffer +{ + uint8_t* pu8Buffer; ///< Buffer + uint8_t* pu8BufferPos; ///< Current position + uint32_t u32BufferSize; ///< Buffer size + uint32_t u32DataSize; ///< Data size +} stc_usbn_endpoint_buffer_t; + +struct stc_usbn_endpoint_data; +struct stc_usb_config; + +/****************************************************************************** + ** \brief USB device init callback + ** + ** \param pstcUsb USB handle + ** + ** \param pstcConfig pointer to configurtion #stc_usb_config_t + ** + ******************************************************************************/ +typedef void (*usb_device_init_t)(stc_usbn_t* pstcUsb, struct stc_usb_config* pstcConfig); + +/****************************************************************************** + ** \brief USB host init callback + ** + ** \param pstcUsb USB handle + ** + ** \param pstcConfig pointer to configurtion #stc_usb_config_t + ** + ******************************************************************************/ +typedef void (*usb_host_init_t)(stc_usbn_t* pstcUsb,struct stc_usb_config* pstcConfig); + +/****************************************************************************** + ** \brief USB endpoint data transferred callback + ** + ** \param pstcUsb USB handle + ** + ** \param pstcEndpoint endoint handle + ** + ******************************************************************************/ +typedef void (*usb_endpoint_datatransferred_func_ptr_t)(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); + +/****************************************************************************** + ** \brief USB connect callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_connect_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB disconnect callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_disconnect_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB device configuration changed callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_conf_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB device setup received callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_setp_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB suspend callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_susp_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB wakeup callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_wkup_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB bus reset callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_brst_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB start of frame callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_sof_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB host token canceled callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_tcan_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB host remote wakeup callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_rwkirq_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB host bus reset callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_urirq_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB host token complete callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_cmpirq_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB host connect callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_cnnirq_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/****************************************************************************** + ** \brief USB host disconnect callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usb_dirq_isr_func_ptr_t)(stc_usbn_t* pstcUsb); + +/** + ****************************************************************************** + ** \brief USB control stage + ** + ******************************************************************************/ +typedef enum en_usb_endpoint_status +{ + UsbEndpointStatusNotReady = 0, ///< USB endpoint not ready + UsbEndpointStatusIdle = 1, ///< USB endpoint status idle + UsbEndpointStatusTransfer = 2, ///< USB endpoint status transferring data + UsbEndpointStatusStall = 3, ///< USB endpoint status stall + UsbEndpointBusy = 4, ///< USB endpoint busy +} en_usb_endpoint_status_t; + + +/****************************************************************************** + ** \brief USB HAL endpoint informations + ** + ** + ******************************************************************************/ +typedef struct stc_usbn_endpoint_data +{ + volatile uint8_t u8EndpointAddress; ///< endpoint address + volatile uint16_t u16EndpointSize; ///< FIFO size + __IO uint16_t* pstcEpStatusRegister; ///< status register + __IO uint16_t* pstcEpControlRegister; ///< control register + __IO uint16_t* pstcEpDataRegister; ///< data register + stc_usbn_endpoint_buffer_t* pstcEndpointBuffer; ///< endpoint buffer + volatile usb_endpoint_datatransferred_func_ptr_t pfnRxTxCallback; ///< data transferred callback + volatile usb_endpoint_datatransferred_func_ptr_t pfnRxTxBlockCallback; ///< data block transferred callback + boolean_t bAutomaticNullTermination; ///< automatic null termination + volatile boolean_t bIsActive; ///< Endpoint is sending / receiving? + stc_usbn_t* pstcUsbInstance; ///< Ref. USB instance + +} stc_usbn_endpoint_data_t; + +/// Enumeration to define an index for each enabled USB instance +typedef enum en_usb_instance_index +{ + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + UsbInstanceIndexUsb0, + #endif + // Case if no DT instance is selected + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + UsbInstanceIndexUsb1, + #endif + UsbInstanceIndexMax +} en_usb_instance_index_t; + +/// Enumeration to define an index for each enabled USB DMA instance +typedef enum en_usb_dma_instance_index +{ +#if USB_USES_DMA_0 == ON + UsbDmaInstanceIndex0, +#endif +#if USB_USES_DMA_1 == ON + UsbDmaInstanceIndex1, +#endif +#if USB_USES_DMA_2 == ON + UsbDmaInstanceIndex2, +#endif +#if USB_USES_DMA_3 == ON + UsbDmaInstanceIndex3, +#endif +#if USB_USES_DMA_4 == ON + UsbDmaInstanceIndex4, +#endif +#if USB_USES_DMA_5 == ON + UsbDmaInstanceIndex5, +#endif +#if USB_USES_DMA_6 == ON + UsbDmaInstanceIndex6, +#endif +#if USB_USES_DMA_7 == ON + UsbDmaInstanceIndex7, +#endif + UsbDmaInstanceIndexMax +} en_usb_dma_instance_index_t; + +/****************************************************************************** + ** \brief USB internal data + ** + ** + ******************************************************************************/ +typedef struct stc_usb_intern_data +{ + boolean_t bHostActive; ///< Host active? + boolean_t bDeviceActive; ///< Device active? + boolean_t bHostEnabled; ///< Host enabled? + boolean_t bDeviceEnabled; ///< Device enabled? + boolean_t bUsbInstanceSet; ///< USB was initialized? + volatile boolean_t bSofTimeoutEnabled; ///< Timeout handling via SOF? + usb_conf_isr_func_ptr_t pfnConfCallback; ///< Configuration changed callback + usb_setp_isr_func_ptr_t pfnSetpCallback; ///< Setup received callback + usb_susp_isr_func_ptr_t pfnSuspCallback; ///< Suspend callback + usb_wkup_isr_func_ptr_t pfnWkupCallback; ///< Wakeup callback + usb_brst_isr_func_ptr_t pfnBrstCallback; ///< Bus reset callback + usb_sof_isr_func_ptr_t pfnSofCallback; ///< Start of frame callback + usb_dirq_isr_func_ptr_t pfnDirqCallback; ///< USB host disconnecion callback + usb_cnnirq_isr_func_ptr_t pfnCnnirqCallback; ///< USB host connecion callback + usb_cmpirq_isr_func_ptr_t pfnCmpirqCallback; ///< USB host token complete callback + usb_urirq_isr_func_ptr_t pfnUrirqCallback; ///< USB host bus reset callback + usb_rwkirq_isr_func_ptr_t pfnRwkirqCallback; ///< USB host remote wakeup callback + usb_tcan_isr_func_ptr_t pfnTcanCallback; ///< USB host token cancelled callback + usb_device_init_t pfnDeviceInit; ///< USB device init callback + usb_host_init_t pfnHostInit; ///< USB host init callback + usb_device_vbus_t pfnDeviceVbus; ///< USB device vbus callback + usb_host_vbus_t pfnHostVbus; ///< USB host vbus callback + usb_host_pulldown_t pfnHostPullDownHostEnable; ///< USB host pull-down callback + usb_host_overcurrent_t pfnHostOvercurrent; ///< USB host overcurrent callback + uint8_t u8NumberOfEndpoints; ///< USB number of HAL endpoints + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + stc_usbn_endpoint_data_t astcEndpoints[7]; ///< Endpoint handles + uint8_t* pu8DeviceDescriptor; ///< Device descriptor buffer + uint8_t* pu8ConfigDescriptor; ///< Configuration descriptor buffer + #else + stc_usbn_endpoint_data_t astcEndpoints[2]; ///< Endpoint handles + #endif + stc_usb_sof_timeout_handler_t pstcUsbTimeOutHandler[5]; ///< Timeout handles +} stc_usb_intern_data_t; + +/// USB module internal data, storing internal information for each enabled USB instance. +typedef struct stc_usbn_instance_data +{ + volatile stc_usbn_t* pstcInstance; ///< pointer to registers of an instance + stc_usb_intern_data_t stcInternData; ///< module internal data of instance +} stc_usbn_instance_data_t; + + +/** + ****************************************************************************** + ** \brief USB control stage + ** + ******************************************************************************/ +typedef enum en_usb_control_stage +{ + ControlStageUnknown = 0, ///< USB control stage unknown + SetupStage = 1, ///< USB control stage setup + DataStageIN = 2, ///< USB control stage data IN + DataStageOUT = 3, ///< USB control stage data OUT + StatusStage = 4 ///< USB control stage status +} en_usb_control_stage_t; + + +/** + ****************************************************************************** + ** \brief Usb Status + ** + ******************************************************************************/ +typedef enum en_usb_status +{ + UsbDisconnected = 0, ///< USB is disconnected + UsbConnected = 1, ///< USB is connected + UsbAddressed = 2, ///< USB is addressed + UsbConfigured = 3 ///< USB is configured +} en_usb_status_t; + +/** + ****************************************************************************** + ** \brief Usb mode + ** + ** To select between device and host + ** + ******************************************************************************/ +typedef enum en_usb_mode +{ + UsbDisabled = 0, ///< USB disabled + UsbDeviceEnabled = 1, ///< USB device enabled, USB host disabled + UsbHostEnabled = 2, ///< USB device disabled, USB host enabled + UsbHostDeviceEnabled = 3 ///< USB device enabled, USB host enabled +} en_usb_mode_t; + +/** + ****************************************************************************** + ** \brief Usb force switch to + ** + ******************************************************************************/ +typedef enum en_usb_switch +{ + UsbSwitchDependingDeviceVbus = 0, ///< Do not force switch + UsbSwitchToDevice = 1, ///< USB device enabled, USB host disabled + UsbSwitchToHost = 2, ///< USB device disabled, USB host enabled + UsbSwitchAllOff = 3 ///< USB device disabled, USB host disabled +} en_usb_switch_t; + + +/** + ****************************************************************************** + ** \brief Usb configuration. + ** + ** Contains all parameter for configuratin an USB channel. + ******************************************************************************/ +typedef struct stc_usb_config +{ + en_usb_mode_t enMode; ///< See description of #en_usb_mode_t. + boolean_t bUseInterrupts; ///< Use interrupts? + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + uint8_t* pu8DeviceDescriptor; ///< Usb Device Descriptor buffer + uint8_t* pu8ConfigDescriptor; ///< Usb Configuration Descriptor buffer + #endif + usb_conf_isr_func_ptr_t pfnConfCallback; ///< Configuration changed callback + usb_setp_isr_func_ptr_t pfnSetpCallback; ///< Setup received callback + usb_susp_isr_func_ptr_t pfnSuspCallback; ///< Device suspend callback + usb_wkup_isr_func_ptr_t pfnWkupCallback; ///< Device wakeup callback + usb_brst_isr_func_ptr_t pfnBrstCallback; ///< Device busreset callback + usb_sof_isr_func_ptr_t pfnSofCallback; ///< Start of frame callback + usb_dirq_isr_func_ptr_t pfnDirqCallback; ///< Host disconnection callback + usb_cnnirq_isr_func_ptr_t pfnCnnirqCallback; ///< Host connection callback + usb_cmpirq_isr_func_ptr_t pfnCmpirqCallback; ///< Host token completion callback + usb_urirq_isr_func_ptr_t pfnUrirqCallback; ///< Host bus reset callback + usb_rwkirq_isr_func_ptr_t pfnRwkirqCallback; ///< Host remote wakeup callback + usb_tcan_isr_func_ptr_t pfnTcanCallback; ///< Host token canceled callback + usb_device_init_t pfnDeviceInit; ///< Device init callback + usb_host_init_t pfnHostInit; ///< Host init callback + usb_device_vbus_t pfnDeviceVbus; ///< Device VBUS callback + usb_host_vbus_t pfnHostVbus; ///< Host VBUS callback + usb_host_pulldown_t pfnHostPullDownHostEnable; ///< Host pull-down callback + usb_host_overcurrent_t pfnHostOvercurrent; ///< Host overcurrent callback +} stc_usb_config_t; + +#if USB_USES_DMA == ON +/** + ****************************************************************************** + ** \brief Usb DMA handle + ** + ** Contains all parameter for configuratin an USB channel. + ******************************************************************************/ +typedef struct stc_usb_dma +{ + boolean_t bIsActive; + IRQn_Type u8IRQ; + stc_usbn_endpoint_data_t* pstcEpHandle; + __IO uint32_t* pstcDMACA; + __IO uint32_t* pstcDMACB; + __IO uint32_t* pstcDMACSA; + __IO uint32_t* pstcDMACDA; + +} stc_usb_dma_t; +#endif + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled USB instances and their internal data +extern stc_usbn_instance_data_t m_astcUsbInstanceDataLut[]; + +#if (USB_ENABLED == ON) + +en_result_t Usb_Configure(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcConfig); + +en_result_t Usb_Init( void ); + +en_result_t Usb_SetupHalEndpoint(stc_usbn_t* pstcUsb,uint8_t u8EndpointAddress , uint16_t u16FifoSize, en_usb_ep_type_t enType, boolean_t bInterruptsEnabled); + +en_result_t Usb_SwitchUsb(stc_usbn_t* pstcUsb, en_usb_switch_t enType, uint32_t u32SwitchDelay); + +en_result_t Usb_InitInstance(stc_usbn_t* pstcUsb); + +en_result_t Usb_DeinitInstance(stc_usbn_t* pstcUsb); + +en_result_t Usb_InitIrq(stc_usbn_t* pstcUsb); + +en_result_t Usb_DeinitIrq(stc_usbn_t* pstcUsb); + +stc_usbn_endpoint_data_t* Usb_GetEndpointPtr(stc_usbn_t* pstcUsb, uint8_t u8EndpointAddress); + +en_result_t Usb_HalSend(stc_usbn_endpoint_data_t* pstcEpHandle, uint8_t* pu8Data, uint16_t u16Size, uint16_t* pu16ByteCount); + +en_result_t Usb_HalReceive(stc_usbn_endpoint_data_t* pstcEpHandle, uint8_t* pu8Data, uint16_t* pu16ByteCount, boolean_t bClearDrq); + +en_result_t Usb_HalClearDrq(stc_usbn_endpoint_data_t* pstcEpHandle); + +en_result_t Usb_HalStallEndpoint(stc_usbn_endpoint_data_t* pstcEpHandle); + +en_result_t Usb_HalUnstallEndpoint(stc_usbn_endpoint_data_t* pstcEpHandle); + +boolean_t Usb_HalEpReady(stc_usbn_endpoint_data_t* pstcEpHandle); + +boolean_t Usb_HalEndpointIsBusy(stc_usbn_endpoint_data_t* pstcEpHandle); + +uint8_t Usb_GetConfiguration(stc_usbn_t* pstcUsb); + +boolean_t Usb_AddTimeOut(stc_usbn_t* pstcUsb, void (* Handler)(stc_usbn_t* pstcUsb), uint16_t u16TimeOut); + +void Usb_RemoveTimeOut(stc_usbn_t* pstcUsb, void (* Handler)(stc_usbn_t* pstcUsb)); + +void Usb_SetEndpointRxTxCallback(stc_usbn_endpoint_data_t* pstcEndpoint, usb_endpoint_datatransferred_func_ptr_t pfnRxTxCallback); + +en_result_t Usb_EpBusyWait(stc_usbn_endpoint_data_t* pstcEndpoint); + +#define Usb_EpCheckWaitBusy(pstcEndpoint) Usb_EpBusyWait(pstcEndpoint); + +#if USB_USES_DMA == ON +en_result_t Usb_HalSendDma(stc_usbn_endpoint_data_t* pstcEpHandle, uint8_t* pu8Data, uint16_t u16Size, uint16_t* pu16ByteCount); +#endif + +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) +extern void UsbIrqHandlerF(stc_usbn_t* pstcUsb, stc_usb_intern_data_t* pstcUsbInternData); +#endif + +void Usb_WaitHook(void); + +void Usb_OsTickHandle(void); + +extern void UsbIrqHandler(stc_usbn_t* pstcUsb, stc_usb_intern_data_t* pstcUsbInternData); + +void UsbConfig_UsbInit(void); + +void UsbConfig_SwitchMode(void); + +#endif /* USB_ENABLED == ON */ + +// [andreika]: used by interrupts_fm4_type_*.c +void Usb_IrqHandlerF(stc_usbn_t* pstcUsb); +void Usb_IrqHandlerH(stc_usbn_t* pstcUsb); + +#ifdef __cplusplus +} +#endif + +//@} // UsbGroup +#endif /* __USB_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.c new file mode 100644 index 0000000000..9912a6d69f --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.c @@ -0,0 +1,999 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbdevice.c + ** + ** + ** A detailed description is available at + ** @link UsbDeviceGroup USB Device Module description @endlink + ** + ** History: + ** - 2012-08-28 2.0 MSc First version (starting at version 2.0). + ** - 2012-10-02 2.1 MSc use of external interrupts without L3 implemented + ** - 2012-11-13 2.2 MSc Some problems while switching from Host to Device fixed + ** - 2013-01-31 2.3 MSc DMA added + ** - 2013-05-07 2.4 MSc Bug with sending wrong package sizes solved + ** - 2013-05-21 2.5 MSc Some Windows versions request only 4 bytes of string descriptor + ** ->fixed: more than only 4 bytes will be sent + ** - 2013-06-04 2.6 MSc FM4 support added + ** - 2013-10-17 2.7 MSc Device Configuration change: support for more than one report descriptor + ** - 2014-02-28 2.8 MSc Busy wait added to send and receive initiate procedure + ** - 2015-05-13 2.9 MSCH Better timeout handling added + ** - 2015-05-29 3.0 MSCH bit access for EPnS register changed for more stable access + ** added better data overflow handling + ** - 2015-07-21 3.1 MSCH check DRQ bit before continue data transfers for safety reasons + ** + ******************************************************************************/ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + + +#include "usbdevice.h" + +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + + + +/** + ****************************************************************************** + ** \ingroup UsbDeviceGroup + ******************************************************************************/ +//@{ + +#if (USE_USBDEVICEHW_H == 1) +#include "usbdevicehw.h" +#endif + + +static stc_usbdevice_intern_data_t* UsbDeviceGetInternDataPtr(const stc_usbn_t* pstcUsb) ; +static void EndpointContinueTxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint); +static void EndpointContinueRxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint); +static void ControlRxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint); +static void ControlTxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint); +static void ConfigChangeCallback(stc_usbn_t* pstcUsb); +static void SetupRxCallback(stc_usbn_t* pstcUsb); + + + +/// Macro to return the number of enabled MFS instances +#define USBDEVICE_INSTANCE_COUNT (uint32_t)(sizeof(m_astcUsbDeviceInstanceDataLut) / sizeof(m_astcUsbDeviceInstanceDataLut[0])) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled MFS instances and their internal data +stc_usbdevicen_instance_data_t m_astcUsbDeviceInstanceDataLut[] = +{ + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0)) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON)) + { &USB0, // pstcInstance + // [andreika]: gcc fix + {0} // stcInternData (not initialized yet) + }, + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1)) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON)) + { &USB1, // pstcInstance + // [andreika]: gcc fix + {0} // stcInternData (not initialized yet) + } + #endif +}; + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain USB instance. + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_usbdevice_intern_data_t* UsbDeviceGetInternDataPtr(const stc_usbn_t* pstcUsb) +{ + volatile uint32_t u32Instance; + + for (u32Instance = 0; u32Instance < USBDEVICE_INSTANCE_COUNT; u32Instance++) + { + if ((uint32_t)pstcUsb == (uint32_t)(m_astcUsbDeviceInstanceDataLut[u32Instance].pstcInstance)) + { + return &m_astcUsbDeviceInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + +/** + ****************************************************************************** + ** \brief Callback function, called after sending via endpoints (IN direction) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \return none + ** + ******************************************************************************/ +static void EndpointContinueTxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint) +{ + uint16_t u16DataSend = 0; + uint32_t u32TransferredData; + volatile uint32_t u32Timeout; + USBDBG(">TxClbk\n"); + + u32TransferredData = (((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8BufferPos) - ((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8Buffer)); + USBDBGVAL16("Trsfrd: ",u32TransferredData); + USBDBGVAL16("Sze: ",pstcEndpoint->pstcEndpointBuffer->u32DataSize); + while(pstcEndpoint->bIsActive == TRUE) + { + pstcEndpoint->bIsActive = FALSE; + } + if (u32TransferredData >= ((uint32_t)pstcEndpoint->pstcEndpointBuffer->u32DataSize)) + { + USBDBG("EOT\n"); + + USB_EPNS_DRQIE_CLEAR(pstcEndpoint); + + /*if ((pstcEndpoint->u8EndpointAddress == 0x80) && (pstcEndpoint->pstcEndpointBuffer->u32DataSize % 64 == 0) && (pstcEndpoint->pstcEndpointBuffer->u32DataSize != 0)) + { + USBDBG("NULL"); + Usb_HalSend(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8Buffer,0,&u16DataSend); + }*/ + if (pstcEndpoint->bAutomaticNullTermination) + { + if (((pstcEndpoint->pstcEndpointBuffer->u32DataSize % pstcEndpoint->u16EndpointSize) == 0) && (pstcEndpoint->pstcEndpointBuffer->u32DataSize != 0)) + { + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalSend(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8Buffer,0,&u16DataSend); + } + } + if (pstcEndpoint->pfnRxTxBlockCallback != NULL) + { + pstcEndpoint->pfnRxTxBlockCallback(pstcUsb, pstcEndpoint); + } + return; + //Data Transfer End + } + + + USB_EPNS_DRQIE_CLEAR(pstcEndpoint); + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalSend(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8BufferPos,pstcEndpoint->pstcEndpointBuffer->u32DataSize - u32TransferredData,&u16DataSend); + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos += u16DataSend; + + USB_EPNS_DRQIE_SET(pstcEndpoint); + +} + +/** + ****************************************************************************** + ** \brief Callback function, called after receiving via endpoints (OUT direction) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \return none + ** + ******************************************************************************/ +static void EndpointContinueRxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint) +{ + uint16_t u16DataReceived = 0; + uint32_t u32DataLeft = 0; + volatile uint32_t u32Timeout; + USB_EPNS_DRQIE_CLEAR(pstcEndpoint); + + u32DataLeft = pstcEndpoint->pstcEndpointBuffer->u32BufferSize - (((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8BufferPos) - ((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8Buffer)); + if (u32DataLeft < pstcEndpoint->u16EndpointSize) + { + //signalizing the low level it is less data available than EP size + u16DataReceived = 0x8000; + u16DataReceived |= (uint16_t)(u32DataLeft & 0x03FF); + } + + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalReceive(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8BufferPos,&u16DataReceived,FALSE); + + USB_EPNS_DRQ_CLEAR(pstcEndpoint); + + pstcEndpoint->pstcEndpointBuffer->u32DataSize += u16DataReceived; + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos += u16DataReceived; + if (((((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8BufferPos) - ((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8Buffer)) >= ((uint32_t)pstcEndpoint->pstcEndpointBuffer->u32BufferSize)) || (u16DataReceived < pstcEndpoint->u16EndpointSize)) + { + pstcEndpoint->pfnRxTxCallback = NULL; + if (pstcEndpoint->pfnRxTxBlockCallback != NULL) + { + pstcEndpoint->pfnRxTxBlockCallback(pstcUsb, pstcEndpoint); + } + return; + //Data Transfer End + } + + USB_EPNS_DRQIE_SET(pstcEndpoint); +} + + +/** + ****************************************************************************** + ** \brief Initiate receiving data (OUT direction) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \param pu8Buffer Pointer to data buffer + ** + ** \param u32DataSize Size of data to be received + ** + ** \param enMode Mode how to send data (polled, irq driven or dma driven) + ** + ** \return none + ** + ******************************************************************************/ +en_result_t UsbDevice_ReceiveData(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + uint16_t u16DataReceived = 0; + uint32_t u32DataLeft = 0; + volatile uint32_t u32Timeout; + if (pstcEndpoint->pstcEndpointBuffer == NULL) + { + return ErrorInvalidParameter; + } + pstcEndpoint->pstcEndpointBuffer->pu8Buffer = pu8Buffer; + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos = pu8Buffer; + pstcEndpoint->pstcEndpointBuffer->u32BufferSize = u32DataSize; + pstcEndpoint->pstcEndpointBuffer->u32DataSize = 0; + + //Usb_EpCheckWaitBusy(pstcEndpoint); + + switch(enMode) + { + case UsbPOLL: + while((((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8BufferPos) - ((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8Buffer)) < ((uint32_t)pstcEndpoint->pstcEndpointBuffer->u32BufferSize)) + { + //Usb_EpCheckWaitBusy(pstcEndpoint); + + u32DataLeft = pstcEndpoint->pstcEndpointBuffer->u32BufferSize - (((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8BufferPos) - ((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8Buffer)); + if (u32DataLeft < pstcEndpoint->u16EndpointSize) + { + //signalizing the low level it is less data available than EP size + u16DataReceived = 0x8000; + u16DataReceived |= (uint16_t)(u32DataLeft & 0x03FF); + } + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalReceive(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8BufferPos,&u16DataReceived,TRUE); + pstcEndpoint->pstcEndpointBuffer->u32DataSize += u16DataReceived; + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos += u16DataReceived; + if (u16DataReceived < pstcEndpoint->u16EndpointSize) + { + return Ok; + } + } + break; + case UsbIRQ: + pstcEndpoint->pfnRxTxCallback = EndpointContinueRxCallback; + + //Usb_EpCheckWaitBusy(pstcEndpoint); + //BITMASK_SET(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + USB_EPNS_DRQIE_SET(pstcEndpoint); + + break; + case UsbDMA: + #if USB_USES_DMA == ON + return Error; + #else + return Error; + #endif + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Initiate sending data (IN direction) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \param pu8Buffer Pointer to data buffer + ** + ** \param u32DataSize Size of data to be send + ** + ** \param enMode Mode how to send data (polled, irq driven or dma driven) + ** + ** \return none + ** + ******************************************************************************/ +en_result_t UsbDevice_SendData(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + uint16_t u16DataSend = 0; + volatile uint32_t u32Timeout; + USBDBGVAL8("New ",(uint32_t)pstcEndpoint->u8EndpointAddress); + USBDBGVAL8("Sze ",(uint32_t)u32DataSize); + if (pstcEndpoint->pstcEndpointBuffer == NULL) + { + USBDBG("\nERROR: Buffer == NULL!"); + return ErrorInvalidParameter; + } + if (pstcEndpoint->bIsActive == TRUE) + { + return ErrorNotReady; + } + + pstcEndpoint->pstcEndpointBuffer->pu8Buffer = pu8Buffer; + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos = pu8Buffer; + pstcEndpoint->pstcEndpointBuffer->u32BufferSize = u32DataSize; + pstcEndpoint->pstcEndpointBuffer->u32DataSize = u32DataSize; + + //Usb_EpCheckWaitBusy(pstcEndpoint); + + switch(enMode) + { + case UsbPOLL: + pstcEndpoint->bIsActive = TRUE; + while((((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8BufferPos) - ((uint32_t)pstcEndpoint->pstcEndpointBuffer->pu8Buffer)) < ((uint32_t)pstcEndpoint->pstcEndpointBuffer->u32DataSize)) + { + //Usb_EpCheckWaitBusy(pstcEndpoint); + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalSend(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8BufferPos,pstcEndpoint->pstcEndpointBuffer->u32DataSize - (uint32_t)(pstcEndpoint->pstcEndpointBuffer->pu8BufferPos - pstcEndpoint->pstcEndpointBuffer->pu8Buffer),&u16DataSend); + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos += u16DataSend; + } + if (pstcEndpoint->bAutomaticNullTermination) + { + if (((pstcEndpoint->pstcEndpointBuffer->u32DataSize % pstcEndpoint->u16EndpointSize) == 0) && (pstcEndpoint->pstcEndpointBuffer->u32DataSize != 0)) + { + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalSend(pstcEndpoint,pstcEndpoint->pstcEndpointBuffer->pu8Buffer,0,&u16DataSend); + } + } + while(pstcEndpoint->bIsActive == TRUE) + { + pstcEndpoint->bIsActive = FALSE; + } + break; + case UsbIRQ: + pstcEndpoint->bIsActive = TRUE; + pstcEndpoint->pfnRxTxCallback = EndpointContinueTxCallback; + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalSend(pstcEndpoint,pu8Buffer,u32DataSize,&u16DataSend); + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos += u16DataSend; + + //Usb_EpCheckWaitBusy(pstcEndpoint); + //BITMASK_SET(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + USB_EPNS_DRQIE_SET(pstcEndpoint); + break; + case UsbDMA: + #if USB_USES_DMA == ON + pstcEndpoint->bIsActive = TRUE; + pstcEndpoint->pfnRxTxCallback = EndpointContinueTxCallback; + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalSendDma(pstcEndpoint,pu8Buffer,u32DataSize,&u16DataSend); + pstcEndpoint->pstcEndpointBuffer->pu8BufferPos += u16DataSend; + + //Usb_EpCheckWaitBusy(pstcEndpoint); + //BITMASK_SET(*(pstcEndpoint->pstcEpStatusRegister),_EPNS_DRQIE); + USB_EPNS_DRQIE_SET(pstcEndpoint); + + break; + #else + while(pstcEndpoint->bIsActive == TRUE) + { + pstcEndpoint->bIsActive = FALSE; + } + pstcEndpoint->bIsActive = FALSE; + return Error; + #endif + default: + return Error; + + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Callback function, called after receiving via control endpoint 0 (OUT direction) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \return none + ** + ******************************************************************************/ +static void ControlRxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint) +{ + static uint8_t pu8Buffer[64]; + uint16_t u16BytesCount; + volatile uint32_t u32Timeout; + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + pstcUsbDeviceIntern->pu8LastControlTransfer = NULL; + + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcEndpoint)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalReceive(pstcEndpoint,pu8Buffer,&u16BytesCount,FALSE); + + while(pstcEndpoint->bIsActive == TRUE) + { + pstcEndpoint->bIsActive = FALSE; + } + pstcEndpoint->pstcEndpointBuffer->pu8Buffer = pu8Buffer; + pstcEndpoint->pstcEndpointBuffer->u32DataSize = u16BytesCount; + while(Usb_HalClearDrq(pstcUsbDeviceIntern->pstcEp0OUT) != Ok); + if (u16BytesCount == 0) + { + if (pstcUsbDeviceIntern->enControlStage == StatusStage) + { + pstcUsbDeviceIntern->enControlStage = ControlStageUnknown; + //BITMASK_SET(*((uint16_t*)pstcEndpoint->pstcEpStatusRegister),_EPNS_BFINI); + //BITMASK_CLEAR(*((uint16_t*)pstcEndpoint->pstcEpStatusRegister),_EPNS_BFINI); + } + //UsbDevice_SendData(pstcUsb, pstcUsbDeviceIntern->pstcEp0IN, pu8Buffer, 0, UsbIRQ); + } + else + { + if (pstcUsbDeviceIntern->pfnControlTransferred != NULL) + { + pstcUsbDeviceIntern->pfnControlTransferred(pstcUsb, pstcEndpoint); + pstcUsbDeviceIntern->pfnControlTransferred = NULL; + } else + { + pstcUsbDeviceIntern->pu8LastControlTransfer = pu8Buffer; + } + } + pstcEndpoint->pstcEndpointBuffer->pu8Buffer = NULL; + pstcEndpoint->pstcEndpointBuffer->u32DataSize = 0; +} + +/** + ****************************************************************************** + ** \brief Callback function, called after sending via control endpoint 0 (IN direction) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \return none + ** + ******************************************************************************/ +static void ControlTxCallback(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint) +{ + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + pstcUsbDeviceIntern->enControlStage = StatusStage; + while(pstcEndpoint->bIsActive == TRUE) + { + pstcEndpoint->bIsActive = FALSE; + } +} + +/** + ****************************************************************************** + ** \brief Callback function, called after device was configured + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void ConfigChangeCallback(stc_usbn_t* pstcUsb) +{ + uint8_t u8i; + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); // get internal i + + if (Usb_GetConfiguration(pstcUsb) == 0) // Check configuration + { + pstcUsbDeviceIntern->enStatus = UsbConnected; // If it is 0, set status connected + } + else + { + pstcUsbDeviceIntern->enStatus = UsbConfigured; // If it is not 0, set status configured + } + for(u8i = 0;u8i < USBDEVICE_MAXCLASSES;u8i++) + { + if (pstcUsbDeviceIntern->stcUsbClasses[u8i].pfnConfCallback != NULL) + { + pstcUsbDeviceIntern->stcUsbClasses[u8i].pfnConfCallback(pstcUsb); + } + } +} + +/** + ****************************************************************************** + ** \brief Callback function, called after setup was received + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void SetupRxCallback(stc_usbn_t* pstcUsb) +{ + volatile uint32_t u32Timeout; + static uint8_t u8DataToSend[255]; + uint16_t u16BytesCount; + uint16_t u16Length; + static uint8_t pu8Buffer[8]; + uint8_t u8Size; + static stc_usb_request_t stcSetup; + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + + USB_ZERO_STRUCT(stcSetup); + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + + + pstcUsb->EP0OS_f.DRQOIE = 0; + + SystemCoreClockUpdate(); + u32Timeout = SystemCoreClock / 100; + while((!USB_EPNS_DRQ_ISSET(pstcUsbDeviceIntern->pstcEp0OUT)) && (u32Timeout > 0)) u32Timeout--; + Usb_HalReceive(pstcUsbDeviceIntern->pstcEp0OUT,pu8Buffer,&u16BytesCount,TRUE); + + + pstcUsbDeviceIntern->enControlStage = SetupStage; + pstcUsbDeviceIntern->pu8LastControlTransfer = NULL; + + /* Decode Setup Package */ + stcSetup.bmRequestType = pu8Buffer[0]; + stcSetup.bRequest = pu8Buffer[1]; + stcSetup.wValue = pu8Buffer[3] << 8; + stcSetup.wValue += pu8Buffer[2]; + stcSetup.wIndex = pu8Buffer[5] << 8; + stcSetup.wIndex += pu8Buffer[4]; + stcSetup.wLength = pu8Buffer[7] << 8; + stcSetup.wLength += pu8Buffer[6]; + + if (stcSetup.bmRequestType_f.DataPhaseTransferDirection == 1) + { + pstcUsbDeviceIntern->enControlStage = DataStageIN; + } + else + { + pstcUsbDeviceIntern->enControlStage = DataStageOUT; + } + + //Usb_HalClearDrq(pstcUsbDeviceIntern->pstcEp0OUT); + if ((pu8Buffer[0] & 0x60) == USB_DEVREQ_CLSTYPE) + { + if(pu8Buffer[1] == USB_DEVREQ_SET_IDLE) + { + //recive SET_IDLE + BITMASK_CLEAR(pstcUsb->EP0IS,_EP0IS_DRQI); // DRQi <- 0 + + pstcUsbDeviceIntern->enControlStage = StatusStage; + while(pstcUsbDeviceIntern->pstcEp0IN->bIsActive == TRUE) + { + pstcUsbDeviceIntern->pstcEp0IN->bIsActive = FALSE; + } + + pstcUsb->EP0OS_f.DRQOIE = 1; + return; + } + } + + switch (stcSetup.bmRequestType_f.Type) + { + case 0: // Device + switch(stcSetup.bRequest) + { + case GET_DESCRIPTOR: + switch((stcSetup.wValue) >> 8) + { + case 1: // Device Descriptor + u16Length = stcSetup.wLength; + USBDBG("Req Dev Desc\n"); + USBDBGVAL16("Len ",u16Length); + if (u16Length > pstcUsbDeviceIntern->pu8DeviceDescriptor[0]) u16Length = pstcUsbDeviceIntern->pu8DeviceDescriptor[0]; + USBDBGVAL16("Len New ",u16Length); + pstcUsbDeviceIntern->pstcEp0IN->pfnRxTxBlockCallback = ControlTxCallback; + UsbDevice_SendData(pstcUsb, pstcUsbDeviceIntern->pstcEp0IN, pstcUsbDeviceIntern->pu8DeviceDescriptor, u16Length, UsbPOLL); + break; + case 2: // Config Descriptor + u16Length = stcSetup.wLength; + USBDBG("Req Conf Desc\n"); + USBDBGVAL16("Len ",u16Length); + if (u16Length > (pstcUsbDeviceIntern->pu8ConfigDescriptor[2] + pstcUsbDeviceIntern->pu8ConfigDescriptor[3]*256)) u16Length = (pstcUsbDeviceIntern->pu8ConfigDescriptor[2] + pstcUsbDeviceIntern->pu8ConfigDescriptor[3]*256); + USBDBGVAL16("Len New ",u16Length); + pstcUsbDeviceIntern->pstcEp0IN->pfnRxTxBlockCallback = ControlTxCallback; + UsbDevice_SendData(pstcUsb, pstcUsbDeviceIntern->pstcEp0IN, pstcUsbDeviceIntern->pu8ConfigDescriptor, u16Length, UsbPOLL); + break; + case 3: // String Descriptor + u16Length = stcSetup.wLength; + u8DataToSend[0] = 0; + switch ((stcSetup.wValue) & 0xFF) + { + case 0: + u8DataToSend[0] = 0x04; + u8DataToSend[1] = 0x03; + u8DataToSend[2] = 0x09; + u8DataToSend[3] = 0x04; + break; + default: + if (((stcSetup.wValue) & 0xFF) <= pstcUsbDeviceIntern->u8StringDescriptorCount) + { + if (pstcUsbDeviceIntern->pstcStringDescriptors[(stcSetup.wValue) & 0xFF].pu8String != NULL) + { + u8DataToSend[0] = 2; + u8DataToSend[1] = 0x03; + for(u8Size=0;(( pstcUsbDeviceIntern->pstcStringDescriptors[((stcSetup.wValue) & 0xFF)-1].pu8String[u8Size] != 0) && (u8Size < sizeof(u8DataToSend) / 2 - 2));u8Size++) + { + u8DataToSend[2 + u8Size * 2] = pstcUsbDeviceIntern->pstcStringDescriptors[((stcSetup.wValue) & 0xFF)-1].pu8String[u8Size]; + u8DataToSend[3 + u8Size * 2] = 0; + } + u8DataToSend[0] = u8DataToSend[0] + 2 * u8Size; + break; + } else + { + /* tbd UNICODE */ + } + } + break; + + } + if (u8DataToSend[0] > stcSetup.wLength) + { + u8DataToSend[0] = stcSetup.wLength; + } + UsbDevice_SendData(pstcUsb, pstcUsbDeviceIntern->pstcEp0IN, u8DataToSend, u8DataToSend[0], UsbPOLL); + break; + case 0x22: // Report Descriptor + + u16Length = stcSetup.wLength; + USBDBG("Req Rep Desc\n"); + USBDBGVAL16("Len ",u16Length); + if (u16Length > pstcUsbDeviceIntern->astcReportDescriptors[(stcSetup.wIndex & 0x03)].u16Size) u16Length = pstcUsbDeviceIntern->astcReportDescriptors[(stcSetup.wIndex & 0x03)].u16Size; + USBDBGVAL16("Len New ",u16Length); + pstcUsbDeviceIntern->pstcEp0IN->pfnRxTxBlockCallback = ControlTxCallback; + UsbDevice_SendData(pstcUsb, pstcUsbDeviceIntern->pstcEp0IN, pstcUsbDeviceIntern->astcReportDescriptors[(stcSetup.wIndex & 0x03)].pu8Descriptor, u16Length, UsbPOLL); + break; + default: + USBDBGVAL8("USB Request Unknown Descriptor: \n",(stcSetup.wValue) >> 8); + //while(1); + break; + } + break; + default: + //while(1); + USBDBGVAL8("USB Request Unknown: ",stcSetup.bRequest); + } + break; + case 1: // Class + if (stcSetup.wIndex < USBDEVICE_MAXCLASSES) + { + if (pstcUsbDeviceIntern->stcUsbClasses[stcSetup.wIndex].pfnSetupRequestCallback != NULL) + { + pstcUsbDeviceIntern->stcUsbClasses[stcSetup.wIndex].pfnSetupRequestCallback(pstcUsb, &stcSetup); + } + else + { + //while(1); + } + } + break; + case 2: // Vendor + break; + } + pstcUsbDeviceIntern->enControlStage = StatusStage; + while(pstcUsbDeviceIntern->pstcEp0IN->bIsActive == TRUE) + { + pstcUsbDeviceIntern->pstcEp0IN->bIsActive = FALSE; + } + //pstcUsbDeviceIntern->enControlStage = ControlStageUnknown; + /*if ((pu8Buffer[0] & 0x60) == USB_DEVREQ_CLSTYPE) + { + if(pu8Buffer[1] == USB_DEVREQ_SET_IDLE) + { + //recive SET_IDLE + BITMASK_CLEAR(pstcUsb->EP0IS,_EP0IS_DRQI); // DRQi <- 0 + pstcUsb->EP0OS_f.DRQOIE = 1; + return; + } + }*/ + pstcUsb->EP0OS_f.DRQOIE = 1; + u16BytesCount = u16BytesCount; +} + +/** + ****************************************************************************** + ** \brief Send control data + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pu8Buffer Buffer + ** + ** \param u32DataLength Data length + ** + ** \return none + ** + ******************************************************************************/ +void UsbDevice_SendDataControl(stc_usbn_t * pstcUsb,uint8_t* pu8Buffer, uint32_t u32DataLength) +{ + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + pstcUsbDeviceIntern->pstcEp0IN->pfnRxTxBlockCallback = ControlTxCallback; + pstcUsbDeviceIntern->pstcEp0IN->bIsActive = FALSE; + UsbDevice_SendData(pstcUsb, pstcUsbDeviceIntern->pstcEp0IN, pu8Buffer, u32DataLength, UsbIRQ); + +} + +/** + ****************************************************************************** + ** \brief Receive control data + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pfnCompletionCallback Data received callback + ** + ** \return none + ** + ******************************************************************************/ +void UsbDevice_ReceiveDataControl(stc_usbn_t * pstcUsb, usbdevice_controltranfered_func_ptr_t pfnCompletionCallback) +{ + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + if (pstcUsbDeviceIntern->pu8LastControlTransfer != NULL) + { + pfnCompletionCallback(pstcUsb, pstcUsbDeviceIntern->pstcEp0OUT); + pstcUsbDeviceIntern->pu8LastControlTransfer = NULL; + } else + { + pstcUsbDeviceIntern->pfnControlTransferred = pfnCompletionCallback; + /*if (pstcUsb->EP0OS_f.DRQO == 1) + { + ControlRxCallback(pstcUsb,pstcUsbDeviceIntern->pstcEp0OUT); + } + pstcUsb->EP0OS_f.DRQOIE = 1;*/ + //Usb_SetEndpointRxTxCallback(pstcUsbDeviceIntern->pstcEp0OUT,ControlRxCallback); + } + +} + +/** + ****************************************************************************** + ** \brief Register USB class + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcUsbClassConfig configuration of USB class + ** + ** \param ppu8Buffer Pointer to buffer where to return configuration buffer pointer + ** + ** \param pu8InterfaceLength Pointer to where to return length of configuration buffer + ** + ** \return Ok if registered, Error if error occured + ** + ******************************************************************************/ +en_result_t UsbDevice_RegisterVendorClass(stc_usbn_t* pstcUsb, stc_usbdevice_class_config_t* pstcUsbClassConfig, uint8_t** ppu8Buffer, uint8_t* pu8InterfaceLength) +{ + uint16_t u16i; + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + + for(u16i = 0;u16i < (pstcUsbDeviceIntern->pu8ConfigDescriptor[2] + pstcUsbDeviceIntern->pu8ConfigDescriptor[3]*256);u16i++) + { + if (pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+1] == USBDESCR_INTERFACE) + { + if (((pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+5] == pstcUsbClassConfig->u8InterfaceClass) && + (pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+6] == pstcUsbClassConfig->u8InterfaceSubClass) && + (pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+7] == pstcUsbClassConfig->u8InterfaceProtocoll)) && + ((pstcUsbClassConfig->u8InterfaceNumber == 0xFF) || (pstcUsbClassConfig->u8InterfaceNumber == pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]))) + { + *ppu8Buffer = (pstcUsbDeviceIntern->pu8ConfigDescriptor + u16i); + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].u8InterfaceClass = pstcUsbClassConfig->u8InterfaceClass; + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].u8InterfaceSubClass = pstcUsbClassConfig->u8InterfaceSubClass; + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].u8InterfaceProtocoll = pstcUsbClassConfig->u8InterfaceProtocoll; + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].pfnSetupRequestCallback = pstcUsbClassConfig->pfnSetupRequestCallback; + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].pfnConnectionCallback = pstcUsbClassConfig->pfnConnectionCallback; + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].pfnDisconnectionCallback = pstcUsbClassConfig->pfnDisconnectionCallback; + pstcUsbDeviceIntern->stcUsbClasses[pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+2]].pfnConfCallback = pstcUsbClassConfig->pfnConfCallback; + while(u16i < (pstcUsbDeviceIntern->pu8ConfigDescriptor[2] + pstcUsbDeviceIntern->pu8ConfigDescriptor[3]*256)) + { + u16i += pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i]; // go to next descriptor + if (pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i+1] == USBDESCR_INTERFACE) + { + break; + } + } + *pu8InterfaceLength = (uint8_t)((uint32_t)u16i - (uint32_t)(((uint32_t)*ppu8Buffer - (uint32_t)pstcUsbDeviceIntern->pu8ConfigDescriptor))); + return Ok; + } + } + u16i += pstcUsbDeviceIntern->pu8ConfigDescriptor[u16i] - 1; // go to next descriptor + } + return Error; +} + +/** + ****************************************************************************** + ** \brief Get Usb Device status + ** + ** \param pstcUsb Pointer to USB instance + ** + ** + ** \return status as en_usb_status_t + ** + ******************************************************************************/ +en_usb_status_t UsbDevice_GetStatus(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + return pstcUsbDeviceIntern->enStatus; +} + +/** + ****************************************************************************** + ** \brief Get information about the specified endpoint status + ** + ** \param pstcEpHandle Endpoint handle + ** + ** \return Status + ** + ******************************************************************************/ +/*en_usb_endpoint_status_t UsbDevice_HalEndpointStatus(stc_usbn_endpoint_data_t* pstcEpHandle) +{ + return Usb_HalEndpointStatus(pstcEpHandle); +}*/ + +/** + ****************************************************************************** + ** \brief Initialization handled from Usb Lowlevel Driver (usb.c) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcUsbConfig Usb Configuration + ** + ******************************************************************************/ +void UsbDevice_InitCallback(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcUsbConfig) +{ + uint16_t i; + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + for(i = 0;i<(pstcUsbDeviceIntern->pu8ConfigDescriptor[2] + pstcUsbDeviceIntern->pu8ConfigDescriptor[3]*256);i++) + { + if (pstcUsbDeviceIntern->pu8ConfigDescriptor[i+1] == USBDESCR_ENDPOINT) + { + Usb_SetupHalEndpoint(pstcUsb,pstcUsbDeviceIntern->pu8ConfigDescriptor[i+2], pstcUsbDeviceIntern->pu8ConfigDescriptor[i+4] | (pstcUsbDeviceIntern->pu8ConfigDescriptor[i+5] << 8),(en_usb_ep_type_t)(pstcUsbDeviceIntern->pu8ConfigDescriptor[i+3] & 0x03),FALSE); + } + i += pstcUsbDeviceIntern->pu8ConfigDescriptor[i] - 1; // go to next descriptor + } + pstcUsbConfig->pfnSetpCallback = &SetupRxCallback; + pstcUsbConfig->pfnConfCallback = &ConfigChangeCallback; + + pstcUsbDeviceIntern->pstcEp0IN = Usb_GetEndpointPtr(pstcUsb,0x80); + pstcUsbDeviceIntern->pstcEp0OUT = Usb_GetEndpointPtr(pstcUsb,0x00); + + pstcUsbDeviceIntern->pstcEp0IN->pstcEndpointBuffer = &(pstcUsbDeviceIntern->stcEndpointBuffer); + pstcUsbDeviceIntern->pstcEp0OUT->pstcEndpointBuffer = &(pstcUsbDeviceIntern->stcEndpointBuffer); + + pstcUsbDeviceIntern->pstcEp0IN->pfnRxTxCallback = &ControlTxCallback; + pstcUsbDeviceIntern->pstcEp0IN->bAutomaticNullTermination = TRUE; + + pstcUsbDeviceIntern->pstcEp0OUT->pfnRxTxCallback = &ControlRxCallback; + pstcUsbDeviceIntern->pu8LastControlTransfer = NULL; + + if (pstcUsbDeviceIntern->pfnInitClassesCallback != NULL) + { + pstcUsbDeviceIntern->pfnInitClassesCallback(pstcUsb); + } +} + +/** + ****************************************************************************** + ** \brief Initialization handled from Usb Lowlevel Driver (usb.c) + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcUsbConfig Usb Configuration To Export Data + ** + ** \param pstcConfig Usb Device Config + ** + ******************************************************************************/ +void UsbDevice_Init(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcUsbConfig, stc_usbdevice_config_t* pstcConfig) +{ + stc_usbdevice_intern_data_t* pstcUsbDeviceIntern; + pstcUsbDeviceIntern = UsbDeviceGetInternDataPtr(pstcUsb); + + pstcUsbConfig->enMode |= UsbDeviceEnabled; + pstcUsbConfig->pu8DeviceDescriptor = pstcConfig->pu8DeviceDescriptor; + pstcUsbConfig->pu8ConfigDescriptor = pstcConfig->pu8ConfigDescriptor; + pstcUsbConfig->pfnDeviceInit = UsbDevice_InitCallback; + //pstcUsbConfig->pstcStringDescriptors = pstcConfig->pstcStringDescriptors; + //pstcUsbConfig->u8StringDescriptorCount = pstcConfig->u8StringDescriptorCount; + + pstcUsbDeviceIntern->pu8DeviceDescriptor = pstcConfig->pu8DeviceDescriptor; + pstcUsbDeviceIntern->pu8ConfigDescriptor = pstcConfig->pu8ConfigDescriptor; + pstcUsbDeviceIntern->astcReportDescriptors = pstcConfig->astcReportDescriptors; + pstcUsbDeviceIntern->pstcStringDescriptors = pstcConfig->pstcStringDescriptors; + pstcUsbDeviceIntern->u8StringDescriptorCount = pstcConfig->u8StringDescriptorCount; + + pstcUsbDeviceIntern->pfnInitClassesCallback = pstcConfig->pfnInitClassesCallback; + + + pstcUsbDeviceIntern->pstcEp0IN = Usb_GetEndpointPtr(pstcUsb,0x80); + pstcUsbDeviceIntern->pstcEp0OUT = Usb_GetEndpointPtr(pstcUsb,0x00); + + pstcUsbDeviceIntern->pstcEp0IN->pstcEndpointBuffer = &(pstcUsbDeviceIntern->stcEndpointBuffer); + pstcUsbDeviceIntern->pstcEp0OUT->pstcEndpointBuffer = &(pstcUsbDeviceIntern->stcEndpointBuffer); + + pstcUsbDeviceIntern->pstcEp0IN->pfnRxTxCallback = &ControlTxCallback; + pstcUsbDeviceIntern->pstcEp0OUT->pfnRxTxCallback = &ControlRxCallback; +} + + +/** + ****************************************************************************** + ** \brief Setup Endpoint + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcConfig Pointer of endpoint configuration + ** + ** \return pointer of endpoint handle #stc_usbn_endpoint_data_t + ** + ******************************************************************************/ +stc_usbn_endpoint_data_t* UsbDevice_SetupEndpoint(stc_usbn_t* pstcUsb, stc_usbdevice_endpoint_config_t* pstcConfig) +{ + stc_usbn_endpoint_data_t* pstcEndpointHandle; + pstcEndpointHandle = Usb_GetEndpointPtr(pstcUsb, pstcConfig->u8EndpointAddress); + pstcEndpointHandle->pfnRxTxBlockCallback = pstcConfig->pfnRxTxCallback; + pstcEndpointHandle->pstcEndpointBuffer = pstcConfig->pstcEndpointBuffer; + return pstcEndpointHandle; +} + +//@} // UsbDeviceGroup +#endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.h new file mode 100644 index 0000000000..cb85ea1d1a --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbdevice.h @@ -0,0 +1,408 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDevice.h + ** + ** A detailed description is available at + ** @link UsbDeviceGroup USB Device Module description @endlink + ** + ** History: + ** - 2012-08-28 2.0 MSc First version (starting at version 2.0). + ** - 2012-10-02 2.1 MSc use of external interrupts without L3 implemented + ** - 2012-11-13 2.2 MSc Some problems while switching from Host to Device fixed + ** - 2013-01-31 2.3 MSc DMA added + ** - 2013-05-07 2.4 MSc Bug with sending wrong package sizes solved + ** - 2013-05-21 2.5 MSc Some Windows versions request only 4 bytes of string descriptor + ** ->fixed: more than only 4 bytes will be sent + ** - 2013-06-04 2.6 MSc FM4 support added + ** - 2013-10-17 2.7 MSc Device Configuration change: support for more than one report descriptor + ** - 2014-02-28 2.8 MSc Busy wait added to send and receive initiate procedure + ** - 2015-05-13 2.9 MSCH Better timeout handling added + ** - 2015-05-29 3.0 MSCH bit access for EPnS register changed for more stable access + ** added better data overflow handling + ** - 2015-07-21 3.1 MSCH check DRQ bit before continue data transfers for safety reasons + ** + ******************************************************************************/ + +#ifndef __USBDEVICE_H__ +#define __USBDEVICE_H__ + +#include "usb.h" + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceGroup USB Device Mode Functionality + ** + ** Provided functions of USB module: + ** + ** - UsbDevice_ReceiveData() + ** - UsbDevice_SendData() + ** - UsbDevice_SendDataControl() + ** - UsbDevice_ReceiveDataControl() + ** - UsbDevice_RegisterVendorClass() + ** - UsbDevice_GetStatus() + ** - UsbDevice_InitCallback() + ** - UsbDevice_Init() + ** - UsbDevice_SetupEndpoint() + ** + ** Used to transfer data with EP0..EP5, to do enumeration process and support different USB class drivers. + ** + ******************************************************************************/ +//@{ + +/** + ****************************************************************************** + ** \page example_usbdevice_classinit Example initializing a vendor class by use of USB descriptors + ** + ** For initializing a USB class by USB descriptor, the u8InterfaceNumber in the stc_usbdevice_class_config_t + ** must be set to 0xFF. This does only work if the interface can be found by interface class, subclass and protocol. + ** + ** @code + ** stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + ** stcUsbClassConfig.u8InterfaceClass = 0x02; // CDC Class + ** stcUsbClassConfig.u8InterfaceSubClass = 0x02; // Custom Sub Class + ** stcUsbClassConfig.u8InterfaceProtocol = 0x01; // Custom Protocol + ** @endcode + ** + ** Additional callbacks can be initialized + ** @code + ** stcUsbClassConfig.pfnSetupRequestCallback = DecodeSetupRequest; // setup requests handled + ** stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + ** stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + ** stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + ** @endcode + ** + ** UsbDevice_RegisterVendorClass registers the class configuration and searches automatically for the correct interface + ** and returns this interface in &pu8Interface with the length of it in &u8InterfaceLength. + ** + ** @code + ** UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + ** @endcode + ** + ** This example gives an idea how to setup the endpoints with the returned interface data by use of + ** UsbDevice_SetupEndpoint. + ** @code + ** u8NumEndpoints = 0; + ** u8ControlInterface = pu8Interface[2]; + ** for(u8i = 0;u8i < u8InterfaceLength;) + ** { + ** u8i += pu8Interface[u8i]; + ** if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + ** { + ** stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + ** stcEndpointConfig.pfnRxTxCallback = NULL; + ** if (((stcEndpointConfig.u8EndpointAddress) & 0x80) != 0) + ** { + ** stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferControlIN; + ** pstcEndpointControlIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + ** pstcEndpointControlIN->bAutomaticNullTermination = TRUE; + ** } + ** u8NumEndpoints++; + ** } + ** } + ** @endcode + ** + ** To initialize the whole class, the whole initialization must be called within the pfnInitClassesCallback + ** of the stc_usbdevice_config_t config in usbconfig.c. Normally all active classes are initialized in usbconfig.c + ** within the default callback for pfnInitClassesCallback called UsbConfig_UsbDeviceClassesInitCallback. + ** @code + ** stcUsbDeviceConfig.pfnInitClassesCallback = UsbConfig_UsbDeviceClassesInitCallback0; //for USB0 + ** @endcode + ** + ** If the initialization of the example class is called UsbDeviceCdcCom_Init, the code in UsbConfig_UsbDeviceClassesInitCallback0 + ** can look like this: + ** @code + ** #if FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON + ** static void UsbConfig_UsbDeviceClassesInitCallback0(stc_usbn_t* pstcUSB) + ** { + ** #if (USBDEVICECDCCOM_ENABLED == ON) + ** UsbDeviceCdcCom_Init((stc_usbn_t*)&USB0); + ** #endif + ** } + ** #endif + ** #if FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON + ** static void UsbConfig_UsbDeviceClassesInitCallback1(stc_usbn_t* pstcUSB) + ** { + ** #if (USBDEVICECDCCOM_ENABLED == ON) + ** UsbDeviceCdcCom_Init((stc_usbn_t*)&USB1); + ** #endif + ** } + ** #endif + ** @endcode + ** + ** + ** The whole UsbDeviceCdcCom_Init example: + ** @code + ** + ** static stc_usbn_endpoint_data_t* pstcEndpointControlIN; + ** static stc_usbn_endpoint_buffer_t stcEndpointBufferControlIN; + ** + ** static void DecodeSetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup); + ** static void ConfCallback(stc_usbn_t* pstcUsb); + ** + ** void UsbDeviceCdcCom_Init(stc_usbn_t* pstcUsb) + ** { + ** stc_usbdevice_class_config_t stcUsbClassConfig; + ** stc_usbdevice_endpoint_config_t stcEndpointConfig; + ** uint8_t* pu8Interface = NULL; + ** uint8_t u8InterfaceLength = 0; + ** uint8_t u8i = 0; + ** uint8_t u8NumEndpoints = 0; + ** pstcUsbHandle = pstcUsb; + ** + ** stcUsbClassConfig.u8InterfaceNumber = 0xFF; // 0xFF == do not use fix interface number, choose by class, subclass, protocol + ** stcUsbClassConfig.u8InterfaceClass = 0x02; // CDC Class + ** stcUsbClassConfig.u8InterfaceSubClass = 0x02; // Custom Sub Class + ** stcUsbClassConfig.u8InterfaceProtocoll = 0x01; // Custom Protocol + ** stcUsbClassConfig.pfnSetupRequestCallback = DecodeSetupRequest; // setup requests handled + ** stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + ** stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + ** stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + ** UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + ** + ** u8NumEndpoints = 0; + ** u8ControlInterface = pu8Interface[2]; + ** for(u8i = 0;u8i < u8InterfaceLength;) + ** { + ** u8i += pu8Interface[u8i]; + ** if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + ** { + ** stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + ** stcEndpointConfig.pfnRxTxCallback = NULL; + ** if (((stcEndpointConfig.u8EndpointAddress) & 0x80) != 0) + ** { + ** stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferControlIN; + ** pstcEndpointControlIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + ** pstcEndpointControlIN->bAutomaticNullTermination = TRUE; + ** } + ** u8NumEndpoints++; + ** } + ** } + ** + ** @endcode + ** + ******************************************************************************/ + +#define USBDEVICE_MAXCLASSES 5 + +/** + ****************************************************************************** + ** \brief setup request callback handle + ** + ** \param pstcUsb USB handle + ** + ** \param pstcSetup Pointer to setup request + ** + ******************************************************************************/ +typedef void (*usbdevice_setuprequest_func_ptr_t)(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup); + +/** + ****************************************************************************** + ** \brief control data transferred + ** + ** \param pstcUsb USB handle + ** + ** \param pstcEndpoint Endpoint handle + ** + ******************************************************************************/ +typedef void (*usbdevice_controltranfered_func_ptr_t)(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint); + +/** + ****************************************************************************** + ** \brief init class callback + ** + ** \param pstcUsb USB handle + ** + ******************************************************************************/ +typedef void (*usbdevice_initclasses_func_ptr_t)(stc_usbn_t* pstcUsb); + + + +/** + ****************************************************************************** + ** \brief USB device class configuration + ** + ** used to setup USB classes + ** + ******************************************************************************/ +typedef struct stc_usbdevice_class_config +{ + uint8_t u8InterfaceNumber; ///< Interface Number, set to 0xFF, if automatically search for + uint8_t u8InterfaceClass; ///< Interface Class + uint8_t u8InterfaceSubClass; ///< Interface Sub Class + union + { + uint8_t u8InterfaceProtocoll; ///< Interface Protocoll + uint8_t u8InterfaceProtocol; ///< Interface Protocol + }; + usbdevice_setuprequest_func_ptr_t pfnSetupRequestCallback; ///< Callback for setup requests + usb_connect_func_ptr_t pfnConnectionCallback; ///< Callback on device connect + usb_disconnect_func_ptr_t pfnDisconnectionCallback; ///< Callback on device disconnect + usb_conf_isr_func_ptr_t pfnConfCallback; ///< Callback on device configuration changed +} stc_usbdevice_class_config_t; + +/** + ****************************************************************************** + ** \brief USB device class configuration + ** + ** used to setup USB classes + ** + ******************************************************************************/ +typedef struct stc_usbdevice_intern_data +{ + uint8_t u8Dummy; + en_usb_status_t enStatus; ///< USB HAL status + uint8_t* pu8DeviceDescriptor; ///< Pointer to USB device descriptor + uint8_t* pu8ConfigDescriptor; ///< Pointer to USB configuration descriptor + stc_usbdevice_reportdescriptor_t* astcReportDescriptors; ///< Pointer to USB report descriptor struct array + stc_usbdevice_stringdescriptor_t* pstcStringDescriptors; ///< Pointer to USB string descriptors + uint8_t u8StringDescriptorCount; ///< Number of USB string descriptors + stc_usbn_endpoint_data_t* pstcEp0OUT; ///< Pointer of Endpoint 0 OUT handle + stc_usbn_endpoint_data_t* pstcEp0IN; ///< Pointer of Endpoint 0 IN handle + en_usb_control_stage_t enControlStage; ///< Control endpoint stage + uint8_t pu8ControlReceiveBuffer[64]; ///< Buffer for control endpoint + stc_usbn_endpoint_buffer_t stcEndpointBuffer; ///< Buffer struct of endpoint buffer + stc_usbdevice_class_config_t stcUsbClasses[USBDEVICE_MAXCLASSES]; ///< USB class configurations + usbdevice_initclasses_func_ptr_t pfnInitClassesCallback; ///< Callback to initialize classes + usbdevice_controltranfered_func_ptr_t pfnControlTransferred; ///< Callback control data transferred + volatile uint8_t* pu8LastControlTransfer; +} stc_usbdevice_intern_data_t; + +/** + ****************************************************************************** + ** \brief USB device configuration + ** + ******************************************************************************/ +typedef struct stc_usbdevice_config +{ + uint8_t* pu8DeviceDescriptor; ///< Pointer to USB device descriptor + uint8_t* pu8ConfigDescriptor; ///< Pointer to USB configuration descriptor + stc_usbdevice_reportdescriptor_t* astcReportDescriptors; ///< Pointer to USB report descriptor struct array + stc_usbdevice_stringdescriptor_t* pstcStringDescriptors; ///< Pointer to USB string descriptor + uint8_t u8StringDescriptorCount; ///< Number of string descriptors + usbdevice_initclasses_func_ptr_t pfnInitClassesCallback; ///< Class initialization callback +} stc_usbdevice_config_t; + + +/** + ****************************************************************************** + ** \brief USB device endpoint configuration + ** + ******************************************************************************/ +typedef struct stc_usbdevice_endpoint_config +{ + uint8_t u8EndpointAddress; ///< Endpointaddress + volatile usb_endpoint_datatransferred_func_ptr_t pfnRxTxCallback; ///< Data transferred callback + stc_usbn_endpoint_buffer_t* pstcEndpointBuffer; ///< Pointer to endpoint buffer struct +} stc_usbdevice_endpoint_config_t; + + + +/** + ****************************************************************************** + ** \brief USB device instance + ** + ******************************************************************************/ +typedef struct stc_usbdevicen_instance_data +{ + volatile stc_usbn_t* pstcInstance; ///< pointer to registers of an instance + stc_usbdevice_intern_data_t stcInternData; ///< module internal data of instance +} stc_usbdevicen_instance_data_t; + +/** + ****************************************************************************** + ** \brief USB device sending mode + ** + ******************************************************************************/ +typedef enum en_usbsend_mode +{ + UsbPOLL = 0, ///< send polled + UsbIRQ = 1, ///< send IRQ + UsbDMA = 2, ///< send DMA +} en_usbsend_mode_t; + + + + +en_result_t UsbDevice_ReceiveData(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); + +en_result_t UsbDevice_SendData(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); + +void UsbDevice_SendDataControl(stc_usbn_t * pstcUsb,uint8_t* pu8Buffer, uint32_t u32DataLength); + +void UsbDevice_ReceiveDataControl(stc_usbn_t * pstcUsb, usbdevice_controltranfered_func_ptr_t pfnCompletionCallback); + +en_result_t UsbDevice_RegisterVendorClass(stc_usbn_t* pstcUsb, stc_usbdevice_class_config_t* pstcUsbClassConfig, uint8_t** ppu8Buffer, uint8_t* pu8InterfaceLength); + +en_usb_status_t UsbDevice_GetStatus(stc_usbn_t* pstcUsb); + +en_usb_endpoint_status_t UsbDevice_HalEndpointStatus(stc_usbn_endpoint_data_t* pstcEpHandle); + +void UsbDevice_InitCallback(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcUsbConfig); + +void UsbDevice_Init(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcUsbConfig, stc_usbdevice_config_t* pstcConfig); + +stc_usbn_endpoint_data_t* UsbDevice_SetupEndpoint(stc_usbn_t* pstcUsb, stc_usbdevice_endpoint_config_t* pstcConfig); + + +#define UsbDevice_HalEndpointStatus(x) Usb_HalEndpointStatus(x) + +#define UsbDevice_HalEndpointIsBusy(x) Usb_HalEndpointIsBusy(x) + +#define UsbDevice_HalStallEndpoint(x) Usb_HalStallEndpoint(x) + +#define UsbDevice_HalUnstallEndpoint(x) Usb_HalUnstallEndpoint(x) + +#if (L3_PERIPHERAL_ENABLE_USB0 == L3_ON) + void UsbDevice_Usb0ExintCallback(void); +#endif +#if (L3_PERIPHERAL_ENABLE_USB1 == L3_ON) + void UsbDevice_Usb1ExintCallback(void); +#endif +#ifdef __cplusplus +} +#endif +//@} // UsbDeviceGroup +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.c new file mode 100644 index 0000000000..27e79bf25d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.c @@ -0,0 +1,368 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbethernetclock.h + ** + ** Headerfile for USB / Ethernet functions + ** @link UsbEthernetGroup USB/Ethernet Clock Module description @endlink + ** + ** History: + ** - 2012-08-10 1.0 MSc First version. + ** - 2012-08-23 1.1 MSc GNU compiler compatible + ** - 2012-08-30 1.2 MSc Correction in USB 0/1 clock enable + ** - 2012-09-19 1.3 MSc PLL settings for type 6 devices corrected + ** - 2012-11-02 1.4 MSc PLL settings for ethernet corrected + ** - 2012-11-02 1.5 CNo Integration Ethernet driver + ** - 2012-11-22 1.6 MSc typedefinitions for ethernetclock added + ** (for use without header file) + ** - 2013-01-14 1.7 MSc type 6 12MHz setting added + ** - 2013-01-16 1.8 MSc type 9 setting added + ** - 2013-06-04 1.9 MSc FM4 support added + ** - 2014-02-28 1.9 MSc Updates in FM4 defines + ** - 2014-09-04 2.0 MSc FM4 type 3 added + ** - 2015-02-04 2.1 MSc GCC compatibility added + ** - 2015-05-12 2.2 MSCH Updated to be compatible with new MCU templates + ** added more frequencies for PLL input crystals + ** - 2015-05-29 2.3 MSCH Updated for USBCLK with 2 USB interfaces + ** - 2015-06-29 2.4 MSCH Updated to be compatible with all FM3 series again + ** - 2015-09-01 2.5 MSCH Change of FM_USBETHERNETCLK -> FM_USBETHERCLK + ** Added devices with no USB PLL + ** + ******************************************************************************/ + +#include "usbethernetclock.h" + +/** + ****************************************************************************** + ** \ingroup UsbEthernetGroup + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Static variable declarations ('static', definition in C source) */ +/*****************************************************************************/ + +static boolean_t bUsbEthernetClockEnabled = FALSE; + +/*****************************************************************************/ +/* Global function ('extern', definition in C source) */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** \brief Initalize PLL for USB / Ethernet Clock. + ** + ******************************************************************************/ +void UsbEthernetClock_Init(void) +{ + if (bUsbEthernetClockEnabled) + { + return; + } + + /************************************************************************/ + /* Initialize default settings */ + /************************************************************************/ + #if defined(FM_USBCLK) + /* Clear USB/Ethernet Clock Setting Register */ + FM_USBCLK->UCCR = 0; + + /* Disable USB Clock */ + #if defined(bFM_USBCLK_USBEN_USBEN) + bFM_USBCLK_USBEN_USBEN = 0; + #elif defined(bFM_USBCLK_USBEN0_USBEN0) + bFM_USBCLK_USBEN0_USBEN0 = 0; + #else + #error no definition for USBEN + #endif + #if defined(bFM_USBCLK_USBEN1_USBEN1) + bFM_USBCLK_USBEN1_USBEN1 = 0; + #endif + #if USBETHERNETCLOCK_USBPLL_AVAILABLE == 1 + /* PLL Disable */ + FM_USBCLK->UPCR1 = 0x00; + #endif + + #elif defined(FM_USBETHERCLK) + /* Clear USB/Ethernet Clock Setting Register */ + FM_USBETHERCLK->UCCR = 0; + + /* Disable Ethernet PLL */ + bFM_USBETHERCLK_UPCR7_EPLLEN = 0; + + /* Disable USB PLL */ + bFM_USBETHERCLK_UPCR1_UPLLEN = 0; + + /* Disable USB Clock 0 */ + #if defined(bFM_USBCLK_USBEN0_USBEN) + bFM_USBCLK_USBEN0_USBEN = 0; + #elif defined(bFM_USBETHERCLK_UCCR_UCEN0) + bFM_USBETHERCLK_UCCR_UCEN0 = 0; + #else + #error No bit definition for UCCR -> UCEN0 + #endif + + /* Disable USB Clock 1 */ + #if defined(bFM_USBCLK_USBEN1_USBEN) + bFM_USBCLK_USBEN1_USBEN = 0; + #elif defined(bFM_USBETHERCLK_UCCR_UCEN1) + bFM_USBETHERCLK_UCCR_UCEN0 = 0; + #else + #error No bit definition for UCCR -> UCEN1 + #endif + + + /* PLL Disable */ + FM_USBETHERCLK->UPCR1 = 0x00; + #else + #error Incorrect USB/Ethernet clock module + #endif + /* End of Initialize default settings */ + + + /************************************************************************/ + /* Setup PLL */ + /************************************************************************/ + #if defined(FM_USBETHERCLK) + /* PLL Disable */ + FM_USBETHERCLK->UPCR1 = 0x00; + + /* wait 1ms */ + FM_USBETHERCLK->UPCR2 = 0x03; + + #ifdef USBETHERNETCLOCK_PLL_K + FM_USBETHERCLK->UPCR3 = USBETHERNETCLOCK_PLL_K - 1; + #endif + #ifdef USBETHERNETCLOCK_PLL_N + FM_USBETHERCLK->UPCR4 = USBETHERNETCLOCK_PLL_N - 1; + #endif + #ifdef USBETHERNETCLOCK_PLL_M + FM_USBETHERCLK->UPCR5 = USBETHERNETCLOCK_PLL_M - 1; + #endif + #elif defined(FM_USBCLK) + #if USBETHERNETCLOCK_USBPLL_AVAILABLE == 1 + /* PLL Disable */ + FM_USBCLK->UPCR1 = 0x00; + /* wait 1ms */ + FM_USBCLK->UPCR2 = 0x03; + #ifdef USBETHERNETCLOCK_PLL_K + FM_USBCLK->UPCR3 = USBETHERNETCLOCK_PLL_K - 1; + #endif + #ifdef USBETHERNETCLOCK_PLL_K + FM_USBCLK->UPCR4 = USBETHERNETCLOCK_PLL_N - 1; + #endif + #ifdef USBETHERNETCLOCK_PLL_M + FM_USBCLK->UPCR5 = USBETHERNETCLOCK_PLL_M - 1; + #endif + #endif + #else + #error Incorrect USB/Ethernet clock module + #endif + /* End Setup PLL */ + + + /************************************************************************/ + /* Enable PLL and wait PLL gets ready */ + /************************************************************************/ + #if defined(FM_USBCLK) + #if USBETHERNETCLOCK_USBPLL_AVAILABLE == 1 + /* Enable USB Part of PLL */ + bFM_USBCLK_UPCR1_UPLLEN = 1; + + /* Wait PLL gets ready */ + while(bFM_USBCLK_UP_STR_UPRDY == 0); + + + /* Select USB clock source */ + FM_USBCLK->UCCR = 0x01 | (USBETHERNETCLOCK_UCSEL << 1); + #else //!defined(FM_USBCLK) + #if __CLKMO == 48000000 + FM_USBCLK->UPCR6 = 0; + FM_USBCLK->UCCR = (0x0 << 1) | 0x01; + #else + FM_USBCLK->UPCR6 = (0x0F & ((__CLKMO * __PLLN * __PLLM) / __PLLK / 48000000ul) - 1); + FM_USBCLK->UCCR = (0x2 << 1) | 0x01; + #endif + #endif + + /* Enable USB */ + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) + #if defined(bFM_USBCLK_USBEN_USBEN) + bFM_USBCLK_USBEN_USBEN = 1; + #elif defined(bFM_USBCLK_USBEN0_USBEN0) + bFM_USBCLK_USBEN0_USBEN0 = 1; + #else + #error no definition for USBEN + #endif + #endif + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) + #if defined(bFM_USBCLK_USBEN1_USBEN1) + bFM_USBCLK_USBEN1_USBEN1 = 1; + #else + #error no definition for USBEN1 + #endif + #endif + + #elif defined(FM_USBETHERCLK) + #if defined(USBETHERNETCLOCK_UBSR) + FM_USBETHERCLK->UPCR6 = (USBETHERNETCLOCK_UBSR & 0x0F); + #endif + + + /* Enable USB Part of PLL */ + bFM_USBETHERCLK_UPCR1_UPLLEN = 1; + + /* Enable Ethernet Part of PLL */ + bFM_USBETHERCLK_UPCR7_EPLLEN = 1; + + + /* Wait PLL gets ready */ + while(bFM_USBETHERCLK_UP_STR_UPRDY == 0); + + #if ((L3_PERIPHERAL_ENABLE_EMAC0 == L3_ON) || (L3_PERIPHERAL_ENABLE_EMAC1 == L3_ON)) + FM_USBETHERCLK->UCCR |= (USBETHERNETCLOCK_UCSEL << 1) | (USBETHERNETCLOCK_ECSEL << 5); + + + bFM_USBETHERCLK_UCCR_ECEN = 1; + #endif + + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0))) + FM_USBETHERCLK->UCCR |= (USBETHERNETCLOCK_UCSEL << 1) | (USBETHERNETCLOCK_ECSEL << 5); + + #ifdef bFM_USBETHERCLK_UCCR_UCEN0 + bFM_USBETHERCLK_UCCR_UCEN0 = 1; + #endif + + + #ifdef bFM_USBCLK_USBEN0_USBEN + bFM_USBCLK_USBEN0_USBEN = 1; + #endif + #ifdef bFM_USBETHERCLK_USBEN0_USBEN0 + bFM_USBETHERCLK_USBEN0_USBEN0 = 1; + #endif + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1))) + FM_USBETHERCLK->UCCR |= (USBETHERNETCLOCK_UCSEL << 1) | (USBETHERNETCLOCK_ECSEL << 5); + + #ifdef bFM_USBETHERCLK_UCCR_UCEN1 + bFM_USBETHERCLK_UCCR_UCEN1 = 1; + #endif + + + #ifdef bFM_USBCLK_USBEN1_USBEN + bFM_USBCLK_USBEN1_USBEN = 1; + #endif + #ifdef bFM_USBETHERCLK_USBEN1_USBEN1 + bFM_USBETHERCLK_USBEN1_USBEN1 = 1; + #endif + #endif + #else + #error Incorrect USB/Ethernet clock module + #endif + /* End Enable PLL and wait PLL gets ready */ + + + + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + bUsbEthernetClockEnabled = TRUE; +} + +/** + ****************************************************************************** + ** \brief Deinitalize PLL for USB / Ethernet Clock. + ** + ******************************************************************************/ +void UsbEthernetClock_Deinit(void) +{ + #if defined(FM_USBCLK) + FM_USBCLK->UCCR = 0; + #if defined(bFM_USBCLK_USBEN_USBEN) + bFM_USBCLK_USBEN_USBEN = 0; + #elif defined(bFM_USBCLK_USBEN0_USBEN0) + bFM_USBCLK_USBEN0_USBEN0 = 0; + #else + #error no definition for USBEN + #endif + #if defined(bFM_USBCLK_USBEN1_USBEN1) + bFM_USBCLK_USBEN1_USBEN1 = 0; + #endif + #if USBETHERNETCLOCK_USBPLL_AVAILABLE == 1 + FM_USBCLK->UPCR1 = 0x00; /* PLL Disable */ + #endif + #elif defined(FM_USBETHERCLK) + + /* Disable Ethernet PLL */ + bFM_USBETHERCLK_UPCR7_EPLLEN = 0; + + /* Disable USB PLL */ + bFM_USBETHERCLK_UPCR1_UPLLEN = 0; + + FM_USBETHERCLK->UCCR = 0; + #ifdef bFM_USBCLK_USBEN0_USBEN + bFM_USBCLK_USBEN0_USBEN = 0; + #endif + #ifdef bFM_USBETHERCLK_UCCR_UCEN0 + bFM_USBETHERCLK_UCCR_UCEN0 = 0; + #endif + + #ifdef bFM_USBCLK_USBEN1_USBEN + bFM_USBCLK_USBEN1_USBEN = 0; + #endif + #ifdef bFM_USBETHERCLK_UCCR_UCEN1 + bFM_USBETHERCLK_UCCR_UCEN1 = 0; + #endif + FM_USBETHERCLK->UPCR1 = 0x00; /* PLL Disable */ + #else + #error Incorrect USB/Ethernet clock module + #endif + #if USBETHERNETCLOCK_USBPLL_AVAILABLE == 1 + #if defined(FM_USBETHERCLK) + FM_USBETHERCLK->UPCR1 = 0x00; /* PLL Disable */ + #elif defined(FM_USBCLK) + FM_USBCLK->UPCR1 = 0x00; /* PLL Disable */ + #else + #error Incorrect USB/Ethernet clock module + #endif + #endif + bUsbEthernetClockEnabled = FALSE; +} +//@} // UsbEthernetClockGroup + + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.h new file mode 100644 index 0000000000..eba4608921 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclock.h @@ -0,0 +1,1279 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbethernetclock.h + ** + ** Headerfile for USB / Ethernet functions + ** @link UsbEthernetGroup USB/Ethernet Clock Module description @endlink + ** + ** History: + ** - 2012-08-10 1.0 MSc First version. + ** - 2012-08-23 1.1 MSc GNU compiler compatible + ** - 2012-08-30 1.2 MSc Correction in USB 0/1 clock enable + ** - 2012-09-19 1.3 MSc PLL settings for type 6 devices corrected + ** - 2012-11-02 1.4 MSc PLL settings for ethernet corrected + ** - 2012-11-02 1.5 CNo Ethernet MAC driver integration + ** - 2012-11-22 1.6 MSc typedefinitions for ethernetclock added + ** (for use without header file) + ** - 2013-01-14 1.7 MSc type 6 12MHz setting added + ** - 2013-01-16 1.8 MSc type 9 setting added + ** - 2013-06-04 1.9 MSc FM4 support added + ** - 2014-02-28 1.9 MSc Updates in FM4 defines + ** - 2014-09-04 2.0 MSc FM4 type 3 added + ** - 2015-02-04 2.1 MSc GCC compatibility added + ** - 2015-05-12 2.2 MSCH Updated to be compatible with new MCU templates + ** added more frequencies for PLL input crystals + ** - 2015-05-29 2.3 MSCH Updated for USBCLK with 2 USB interfaces + ** - 2015-06-29 2.4 MSCH Updated to be compatible with all FM3 series again + ** - 2015-09-01 2.5 MSCH Change of FM_USBETHERNETCLK -> FM_USBETHERCLK + ** Added devices with no USB PLL + ** + ******************************************************************************/ + +#ifndef __USBETHERNETCLOCK_H__ +#define __USBETHERNETCLOCK_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "mcu.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbEthernetGroup USB/Ethernet Clock Module description + ** + ** Provided functions of USB Ethernet Clock module: + ** + ** - UsbEthernetClock_Init() + ** - UsbEthernetClock_Deinit() + ** + ** Used to initialize the USB Ethernet Clock PLL, devider and source selector + ** + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +#define USBETHERNETCLOCK_USE_USB 1 +#define USBETHERNETCLOCK_USE_ETHERNET 0 +#define USBETHERNETCLOCK_USE_L3 0 +#define USBETHERNETCLOCK_USE_PDL 0 + + +#if (USBETHERNETCLOCK_USE_L3 == 0) && (USBETHERNETCLOCK_USE_PDL == 0) + #define USBETHERNETCLOCK_USE_STANDALONE 1 +#else + #define USBETHERNETCLOCK_USE_STANDALONE 0 +#endif + +#if !defined(USBETHERNETCLOCK_USE_LEGACYSUPPORT) + #if (!defined(FM_USB_AVAILABLE)) && (!defined(FM_USB0)) && (!defined(FM_USB1)) + #define USBETHERNETCLOCK_USE_LEGACYSUPPORT 1U + #if defined(__USB_C__) + #warning USB legacy support turned on automatically, but it is better to update to the latest MCU template! + #endif + #else + #define USBETHERNETCLOCK_USE_LEGACYSUPPORT 0U + #endif +#endif + +#if USBETHERNETCLOCK_USE_LEGACYSUPPORT == 1u + #include "usbethernetclocklegacy.h" +#else + #if (!defined(FM_USB_AVAILABLE)) && (!defined(FM_USB0)) && (!defined(FM_USB1)) + #error For this configuration set USBETHERNETCLOCK_USE_LEGACYSUPPORT to 1 + #endif + #define stc_usbclkn_t FM_USBCLK_TypeDef + #define stc_usb_ethernetclkn_t FM_USBETHERCLK_TypeDef + +#endif + + +#if USBETHERNETCLOCK_USE_USB == 1 + #include "usb.h" /* if error happens, set USBETHERNETCLOCK_USE_USB to 0 */ +#endif + +#if USBETHERNETCLOCK_USE_ETHERNET == 1 + #include "emac_user.h" /* if error happens, set USBETHERNETCLOCK_USE_ETHERNET to 0 */ + + #if EMAC_PHYINTERFACE_RMII == L3_ON + #define ETHERNETCLOCK_OUTFREQ FREQ_50MHZ //< Set required source clock frequency for RMII mode (50MHZ) + #else + #define ETHERNETCLOCK_OUTFREQ FREQ_25MHZ //< Set required source clock frequency for MII mode (25MHZ) + #endif + #if EMAC_ECOUT == L3_OFF + #undef USBETHERNETCLOCK_USE_ETHERNET + #define USBETHERNETCLOCK_USE_ETHERNET 0 + #endif +#endif + +#if (FM0P_DEVICE_TYPE == 3) + #define USBETHERNETCLOCK_USBPLL_AVAILABLE 0 +#else + #define USBETHERNETCLOCK_USBPLL_AVAILABLE 1 +#endif + +#if (USBETHERNETCLOCK_USE_USB == 1) && (USBETHERNETCLOCK_USE_STANDALONE == 1) + #if defined(FM4_USB0) + #include "base_types.h" + #endif + #if defined(FM3_USB0) + #include "base_types.h" + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB0_HOST) + #define FM_PERIPHERAL_ENABLE_USB0_HOST USB0_HOST_ENABLED + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB1_HOST) + #define FM_PERIPHERAL_ENABLE_USB1_HOST USB1_HOST_ENABLED + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB0_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE USB0_DEVICE_ENABLED + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB1_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE USB1_DEVICE_ENABLED + #endif +#elif (USBETHERNETCLOCK_USE_L3 == 1) + #include "l3.h" /* if error happens, set USBETHERNETCLOCK_USE_L3 to 0 */ + #include "base_types.h" + #if !defined(FM_PERIPHERAL_ENABLE_USB0_HOST) + #define FM_PERIPHERAL_ENABLE_USB0_HOST L3_PERIPHERAL_ENABLE_USB0_HOST + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB0_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE L3_PERIPHERAL_ENABLE_USB0_DEVICE + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB1_HOST) + #define FM_PERIPHERAL_ENABLE_USB1_HOST L3_PERIPHERAL_ENABLE_USB1_HOST + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB1_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE L3_PERIPHERAL_ENABLE_USB1_DEVICE + #endif +#elif (USBETHERNETCLOCK_USE_PDL == 1) + #include "pdl.h" /* if error happens, set USBETHERNETCLOCK_USE_PDL to 0 */ + #include "base_types.h" + #if !defined(FM_PERIPHERAL_ENABLE_USB0_HOST) + #define FM_PERIPHERAL_ENABLE_USB0_HOST PDL_PERIPHERAL_ENABLE_USB0_HOST + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB0_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB0_DEVICE PDL_PERIPHERAL_ENABLE_USB0_DEVICE + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB1_HOST) + #define FM_PERIPHERAL_ENABLE_USB1_HOST PDL_PERIPHERAL_ENABLE_USB0_HOST + #endif + #if !defined(FM_PERIPHERAL_ENABLE_USB1_DEVICE) + #define FM_PERIPHERAL_ENABLE_USB1_DEVICE PDL_PERIPHERAL_ENABLE_USB0_DEVICE + #endif +#else + #error Not supported configuration +#endif + +#ifndef OFF + #define OFF 0 +#endif + +#ifndef ON + #define ON 1 +#endif + +#ifndef L3_OFF + #define L3_OFF 0 +#endif + +#ifndef L3_ON + #define L3_ON 1 +#endif + +#ifndef ETHERNETCLOCK_OUTFREQ + #define ETHERNETCLOCK_OUTFREQ FREQ_25MHZ +#endif + +#ifndef FREQ_4MHZ + #define FREQ_4MHZ ( 4000000UL) +#endif + +#ifndef FREQ_8MHZ + #define FREQ_8MHZ ( 8000000UL) +#endif +#ifndef FREQ_16MHZ + #define FREQ_16MHZ (16000000UL) +#endif +#ifndef FREQ_24MHZ + #define FREQ_24MHZ (24000000UL) +#endif + +#ifndef FREQ_48MHZ + #define FREQ_48MHZ (48000000UL) +#endif + +#ifndef FREQ_25MHZ + #define FREQ_25MHZ (25000000UL) +#endif + +#ifndef FREQ_50MHZ + #define FREQ_50MHZ (50000000UL) +#endif + +#ifndef FREQ_96MHZ + #define FREQ_96MHZ (96000000UL) +#endif + +#ifndef FREQ_144MHZ + #define FREQ_144MHZ (144000000UL) +#endif + +//#define MAINCRYSTALFREQ 4MHZ // <<< External 4MHz Crystal + +#if ((!defined(__CLKMO)) && (!defined(MAINCRYSTALFREQ))) + #error __CLKMO does not exist, please specify crystal freqency in MAINCRYSTALFREQ +#endif + +#if !defined(MAINCRYSTALFREQ) + #define MAINCRYSTALFREQ __CLKMO +#endif + + + +/* USBCLK (FM3 type 0) */ +#if (((defined(FM3_DEVICE_TYPE) && (FM3_DEVICE_TYPE == 0))) && (defined(FM3_USBCLK_BASE) || defined(FM_USBCLK_BASE))) + #if !defined(__CLKMO) + #error Please define __CLKMO in your system header file + #elif __CLKMO == (4000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4800000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 12 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9600000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 10 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 8 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (48000000UL) + #define USBETHERNETCLOCK_UCSEL 0x00 // no PLL needed for 48MHz crystal, using directly CLKMO + #else + #error The external crystal defined in __CLKMO is not supported for USB PLL + #endif /* __CLKMO == ... */ +#endif /* USBCLK (FM3 type 0) */ + +/* if Ethernet is not using the USBETHERNETCLOCK */ +#if (USBETHERNETCLOCK_USE_ETHERNET == 0) + + + /* USB only: USBCLK/USBETHERNELCLK (all except FM3 type 0) */ + /* USBCLK/USBETHERNELCLK (FM3 type 1,4,5) */ + #if (!((defined(FM3_DEVICE_TYPE) && (FM3_DEVICE_TYPE == 0))) && \ + ((FM3_DEVICE_TYPE == 1) || (FM3_DEVICE_TYPE == 4) || (FM3_DEVICE_TYPE == 4)) && \ + (defined(FM3_USBCLK_BASE) || defined(FM4_USBCLK_BASE) \ + || defined(FM0P_USBCLK_BASE) || defined(FM_USBCLK_BASE) \ + || defined(FM3_USBETHERCLK_BASE) || defined(FM4_USBETHERCLK_BASE) \ + || defined(FM0P_USBETHERCLK_BASE) || defined(FM_USBETHERCLK_BASE))) + #if !defined(__CLKMO) + #error Please define __CLKMO in your system header file + #elif __CLKMO == (4000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 60 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 64 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4800000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 48 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5106383UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 47 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5760000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 45 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7200000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8888889UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 27 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9600000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10909091UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 22 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11520000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12631579UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 19 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (14400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (16000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (18000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (19200000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #else + #error The external crystal defined in __CLKMO is not supported for USB PLL + #endif /* __CLKMO == ... */ + /* USBCLK/USBETHERNELCLK (FM3 type 6,9,12) */ + #elif (!((defined(FM3_DEVICE_TYPE) && (FM3_DEVICE_TYPE == 0))) && \ + ((FM3_DEVICE_TYPE == 6) || (FM3_DEVICE_TYPE == 9) || (FM3_DEVICE_TYPE == 12)) && \ + (defined(FM3_USBCLK_BASE) || defined(FM4_USBCLK_BASE) \ + || defined(FM0P_USBCLK_BASE) || defined(FM_USBCLK_BASE) \ + || defined(FM3_USBETHERCLK_BASE) || defined(FM4_USBETHERCLK_BASE) \ + || defined(FM0P_USBETHERCLK_BASE) || defined(FM_USBETHERCLK_BASE))) + #if !defined(__CLKMO) + #error Please define __CLKMO in your system header file + #elif __CLKMO == (4000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4800000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5760000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7200000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 12 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9600000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 10 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 8 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (14400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 10 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (16000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 6 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (18000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 8 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (19200000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 5 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (24000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 6 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (28800000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 5 + #define USBETHERNETCLOCK_PLL_M 3 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #else + #error The external crystal defined in __CLKMO is not supported for USB PLL + #endif /* __CLKMO == ... */ + /* USB only: USBCLK/USBETHERNELCLK (all except FM3 type 0,1,4,6,5,9,12) */ + #elif (!((defined(FM3_DEVICE_TYPE) && (FM3_DEVICE_TYPE == 0))) && \ + (defined(FM3_USBCLK_BASE) || defined(FM4_USBCLK_BASE) \ + || defined(FM0P_USBCLK_BASE) || defined(FM_USBCLK_BASE) \ + || defined(FM3_USBETHERCLK_BASE) || defined(FM4_USBETHERCLK_BASE) \ + || defined(FM0P_USBETHERCLK_BASE) || defined(FM_USBETHERCLK_BASE))) + #if !defined(__CLKMO) + #error Please define __CLKMO in your system header file + #elif ((__CLKMO == (4000000UL)) && (FM0P_DEVICE_TYPE == 2)) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 60 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 64 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4800000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4881356UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 59 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 48 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5106383UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 47 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5760000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 45 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7200000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8888889UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 27 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9600000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10909091UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 22 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11520000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12631579UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 19 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (14400000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15157895UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 19 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (16000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (18000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (19200000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (48000000UL) + #define USBETHERNETCLOCK_UCSEL 0x00 // no PLL needed for 48MHz crystal, using directly CLKMO + #else + #error The external crystal defined in __CLKMO is not supported for USB PLL + #endif /* __CLKMO == ... */ + #endif /* USB only: USBCLK/USBETHERNELCLK (all except FM3 type 0) */ + +/* if Ethernet is using the USBETHERNETCLOCK */ +#elif (USBETHERNETCLOCK_USE_ETHERNET == 1) + + + /* Ethernet 25MHz: USBCLK/USBETHERNELCLK (all except FM3 type 0) */ + #if (ETHERNETCLOCK_OUTFREQ == FREQ_25MHZ) && (!((defined(FM3_DEVICE_TYPE) && (FM3_DEVICE_TYPE == 0))) && \ + (defined(FM3_USBCLK_BASE) || defined(FM4_USBCLK_BASE) \ + || defined(FM0P_USBCLK_BASE) || defined(FM_USBCLK_BASE) \ + || defined(FM3_USBETHERCLK_BASE) || defined(FM4_USBETHERCLK_BASE) \ + || defined(FM0P_USBETHERCLK_BASE) || defined(FM_USBETHERCLK_BASE))) + #if !defined(__CLKMO) + #error Please define __CLKMO in your system header file + #elif __CLKMO == (4000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4296875UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 64 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4385965UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 57 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4435484UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 62 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4661017UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 59 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4687500UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 48 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5102041UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 49 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5263158UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 38 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5319149UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 47 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5357143UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 42 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5392157UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 51 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5487805UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 41 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5612245UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 49 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5625000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5851064UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 47 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5882353UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 34 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5952381UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 42 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5978261UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 46 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 12 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6097561UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 41 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6250000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6395349UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 43 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6451613UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 31 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6756757UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 37 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6818182UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 33 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6875000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7031250UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7638889UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 36 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7812500UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7857143UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 35 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8593750UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8870968UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 31 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9166667UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9375000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9782609UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 23 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10227273UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 22 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10416667UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10526316UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 19 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10714286UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 21 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11250000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11764706UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 17 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11904762UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 21 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11956522UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 23 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 12 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (13157895UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 19 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (13750000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (13888889UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 18 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (14062500UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15277778UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 18 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15625000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (16071429UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 14 + #define USBETHERNETCLOCK_PLL_M 9 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (16176471UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 17 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (16666667UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (17187500UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (17857143UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 14 + #define USBETHERNETCLOCK_PLL_M 10 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (18333334UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 11 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (18750000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 12 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (20000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 12 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #else + #error The external crystal defined in __CLKMO is not supported for Ethernet PLL + #endif /* __CLKMO == ... */ + /* Ethernet 50MHz: USBCLK/USBETHERNELCLK (all except FM3 type 0) */ + #elif (ETHERNETCLOCK_OUTFREQ == FREQ_50MHZ) && (!((defined(FM3_DEVICE_TYPE) && (FM3_DEVICE_TYPE == 0))) && \ + (defined(FM3_USBCLK_BASE) || defined(FM4_USBCLK_BASE) \ + || defined(FM0P_USBCLK_BASE) || defined(FM_USBCLK_BASE) \ + || defined(FM3_USBETHERCLK_BASE) || defined(FM4_USBETHERCLK_BASE) \ + || defined(FM0P_USBETHERCLK_BASE) || defined(FM_USBETHERCLK_BASE))) + #if !defined(__CLKMO) + #error Please define __CLKMO in your system header file + #elif __CLKMO == (4000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (4687500UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 64 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5319149UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 47 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5882353UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 34 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (5952381UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 42 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6097561UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 41 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6250000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (6451613UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 31 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (7812500UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (8000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (9375000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 32 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (10000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11764706UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 17 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (11904762UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 21 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (12500000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (13888889UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 18 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (15625000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (17857143UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 14 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (18750000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 16 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #elif __CLKMO == (20000000UL) + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 6 + #define USBETHERNETCLOCK_ECSEL 0x01 // use USB/Ethernet-PLL oscillation clock + #else + #error The external crystal defined in __CLKMO is not supported for Ethernet PLL + #endif /* __CLKMO == ... */ + #else + #error ETHERNETCLOCK must be 25MHz or 50MHz + #endif /* Ethernet 25/50MHz: USBCLK/USBETHERNELCLK (all except FM3 type 0) */ + + + #if (USBETHERNETCLOCK_USE_USB == 1) + #if __CLKMO == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #elif __PLLCLK == FREQ_144MHZ + #define USBETHERNETCLOCK_UCSEL 0x02 // CLKPLL division clock + #define USBETHERNETCLOCK_UBSR (3 - 1) // Clock divided by 3 + #elif __PLLCLK == FREQ_96MHz + #define USBETHERNETCLOCK_UCSEL 0x02 // CLKPLL division clock + #define USBETHERNETCLOCK_UBSR (2 - 1) // Clock divided by 3 + #else + #if (USBETHERNETCLOCK_USE_USB == 1) + #error USB Clock Setting not supported + #endif + #endif + #endif + + +#endif + + +/* Check Clock Settings */ +#if USBETHERNETCLOCK_PLL_K > 63 + #error USB ETHERNET CLOCK: (K - 1) must be < 64 +#endif + +#if ((FM3MCUTYPE == FM3MCUTYPE_TYPE6) || (FM3MCUTYPE == FM3MCUTYPE_TYPE0)) + #if USBETHERNETCLOCK_PLL_N == 0 + #error USB ETHERNET CLOCK: (N - 1) cant be 0 + #endif + #if USBETHERNETCLOCK_PLL_N > 63 + #error USB ETHERNET CLOCK: (N - 1) cant be > 63 + #endif +#endif +#if ((FM3MCUTYPE == FM3MCUTYPE_TYPE1) || (FM3MCUTYPE == FM3MCUTYPE_TYPE4) || (FM3MCUTYPE == FM3MCUTYPE_TYPE5)) + #if USBETHERNETCLOCK_PLL_N < 13 + #error USB ETHERNET CLOCK: (N - 1) must be > 12 + #endif + #if USBETHERNETCLOCK_PLL_N > 99 + #error USB ETHERNET CLOCK: (N - 1) cant be > 99 + #endif +#endif + +#if ((FM3MCUTYPE == FM3MCUTYPE_TYPE1) || (FM3MCUTYPE == FM3MCUTYPE_TYPE4) || (FM3MCUTYPE == FM3MCUTYPE_TYPE5)) + #if USBETHERNETCLOCK_PLL_M > 15 + #error USB ETHERNET CLOCK: (M - 1) cant be > 15 + #endif +#endif + +#if ((FM3MCUTYPE == FM3MCUTYPE_TYPE6)) + #if USBETHERNETCLOCK_PLL_M > 15 + #error USB ETHERNET CLOCK: (M - 1) cant be > 15 + #endif +#endif +/* End Check Clock Settings */ + +#ifndef USBETHERNETCLOCK_UCSEL + #define USBETHERNETCLOCK_UCSEL 0x00 +#endif + +#ifndef USBETHERNETCLOCK_ECSEL + #define USBETHERNETCLOCK_ECSEL 0x00 +#endif + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +void UsbEthernetClock_Init(void); +void UsbEthernetClock_Deinit(void); +#ifdef __cplusplus +} +#endif + +//@} // UsbEthernetClockGroup + +#endif /* __USBETHERNETCLOCK_H__ */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + + + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclocklegacy.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclocklegacy.h new file mode 100644 index 0000000000..685db789a7 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbethernetclocklegacy.h @@ -0,0 +1,1712 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbethernetclocklegacy.h + ** + ** A detailed description is available at + ** @link UsbEthernetClockLegacyGroup USB Ethernet Clock legcy support for older libraries of L3, PDL or MCU template description @endlink + ** + ** History: + ** - 2015-11-05 V1.0 MSc First Version + *****************************************************************************/ + +#ifndef __USBETHERNETCLOCKLEGACY_H__ +#define __USBETHERNETCLOCKLEGACY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbEthernetClockLegacyGroup USB Ethernet Clock legcy support for older libraries of L3, PDL or MCU template + ** + ******************************************************************************/ +//@{ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "mcu.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + +#ifndef FM3MCUTYPE_TYPE0 + #define FM3MCUTYPE_TYPE0 0 +#endif +#ifndef FM3MCUTYPE_TYPE1 + #define FM3MCUTYPE_TYPE1 1 +#endif +#ifndef FM3MCUTYPE_TYPE2 + #define FM3MCUTYPE_TYPE2 2 +#endif +#ifndef FM3MCUTYPE_TYPE3 + #define FM3MCUTYPE_TYPE3 3 +#endif +#ifndef FM3MCUTYPE_TYPE4 + #define FM3MCUTYPE_TYPE4 4 +#endif +#ifndef FM3MCUTYPE_TYPE5 + #define FM3MCUTYPE_TYPE5 5 +#endif +#ifndef FM3MCUTYPE_TYPE6 + #define FM3MCUTYPE_TYPE6 6 +#endif +#ifndef FM3MCUTYPE_TYPE7 + #define FM3MCUTYPE_TYPE7 7 +#endif +#ifndef FM3MCUTYPE_TYPE8 + #define FM3MCUTYPE_TYPE8 8 +#endif +#ifndef FM3MCUTYPE_TYPE9 + #define FM3MCUTYPE_TYPE9 9 +#endif + +#ifndef FM4MCUTYPE_TYPE0 + #define FM4MCUTYPE_TYPE0 0 +#endif +#ifndef FM4MCUTYPE_TYPE1 + #define FM4MCUTYPE_TYPE1 1 +#endif +#ifndef FM4MCUTYPE_TYPE2 + #define FM4MCUTYPE_TYPE2 2 +#endif +#ifndef FM4MCUTYPE_TYPE3 + #define FM4MCUTYPE_TYPE3 3 +#endif +#ifndef FM4MCUTYPE_TYPE4 + #define FM4MCUTYPE_TYPE4 4 +#endif +#ifndef FM4MCUTYPE_TYPE5 + #define FM4MCUTYPE_TYPE5 5 +#endif +#ifndef FM4MCUTYPE_TYPE6 + #define FM4MCUTYPE_TYPE6 6 +#endif + +#ifdef FM3_DEVICE_TYPE + #ifndef FM3MCUTYPE + #define FM3MCUTYPE FM3_DEVICE_TYPE + #endif +#endif + +#ifdef FM4_DEVICE_TYPE + #ifndef FM4MCUTYPE + #define FM4MCUTYPE FM4_DEVICE_TYPE + #endif +#endif + +#if (0 == USBETHERNETCLOCK_USE_L3) + #ifndef FM4MCUTYPE + #ifdef _MB9ABXXX_H_ + #define FM4MCUTYPE FM4MCUTYPE_TYPE0 + #endif + #ifdef _MB9B560R_H_ + #define FM4MCUTYPE FM4MCUTYPE_TYPE0 + #endif + #ifdef _S6E2CC_H_ + #define FM4MCUTYPE FM4MCUTYPE_TYPE3 + #endif + #endif + #ifndef FM3MCUTYPE + #ifdef _MB9B120K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B320K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B420K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B520K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B120L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B320L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B420L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B520L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B120M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B320M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B420M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B520M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #ifdef _MB9B500N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B400N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B300N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B100N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B500R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B400R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B300R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9B100R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9BD10S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B610S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B510S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B410S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B310S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B210S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B110S_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9BD10T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B610T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B210T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B510T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B410T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B310T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B110T_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #endif + #ifdef _MB9B510N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B410N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B310N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B110N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B510R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B410R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B310R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9B110R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #endif + #ifdef _MB9A310K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE5 + #endif + #ifdef _MB9A110K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE5 + #endif + #ifdef _MB9A310L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #endif + #ifdef _MB9A110L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #endif + #ifdef _MB9A310M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #endif + #ifdef _MB9A110M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #endif + #ifdef _MB9A310N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #endif + #ifdef _MB9A100N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9A110N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #endif + #ifdef _MB9A100R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #endif + #ifdef _MB9AB40L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9AA40L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A340L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A140L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9AB40M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9AA40M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A340M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A140M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9AB40N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9AA40N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A340N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A140N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #endif + #ifdef _MB9A150M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE8 + #endif + #ifdef _MB9A150N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE8 + #endif + #ifdef _MB9A150R_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE8 + #endif + #ifdef _MB9A130K_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE3 + #endif + #ifdef _MB9A130L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE3 + #endif + #ifdef _MB9AA30L_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE7 + #endif + #ifdef _MB9AA30M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE7 + #endif + #ifdef _MB9A130M_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE7 + #endif + #ifdef _MB9AA30N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE7 + #endif + #ifdef _MB9A130N_H_ + #define FM3MCUTYPE FM3MCUTYPE_TYPE7 + #endif + #endif +#else // (0 == USBETHERNETCLOCK_USE_L3) + #ifndef FM3MCUTYPE + #if (L3_DEVICE_TYPE == L3_TYPE0) + #define FM3MCUTYPE FM3MCUTYPE_TYPE0 + #elif (L3_DEVICE_TYPE == L3_TYPE1) + #define FM3MCUTYPE FM3MCUTYPE_TYPE1 + #elif (L3_DEVICE_TYPE == L3_TYPE2) + #define FM3MCUTYPE FM3MCUTYPE_TYPE2 + #elif (L3_DEVICE_TYPE == L3_TYPE3) + #define FM3MCUTYPE FM3MCUTYPE_TYPE3 + #elif (L3_DEVICE_TYPE == L3_TYPE4) + #define FM3MCUTYPE FM3MCUTYPE_TYPE4 + #elif (L3_DEVICE_TYPE == L3_TYPE5) + #define FM3MCUTYPE FM3MCUTYPE_TYPE5 + #elif (L3_DEVICE_TYPE == L3_TYPE6) + #define FM3MCUTYPE FM3MCUTYPE_TYPE6 + #elif (L3_DEVICE_TYPE == L3_TYPE7) + #define FM3MCUTYPE FM3MCUTYPE_TYPE7 + #elif (L3_DEVICE_TYPE == L3_TYPE9) + #define FM3MCUTYPE FM3MCUTYPE_TYPE9 + #endif + #endif +#endif // (0 == USBETHERNETCLOCK_USE_L3) + + /* +#if defined(FM3MCUTYPE) && (FM3MCUTYPE == FM3MCUTYPE_TYPE0) + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 12 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 6 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 8 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif +#elif ((FM3MCUTYPE == FM3MCUTYPE_TYPE1) || ((FM3MCUTYPE == FM3MCUTYPE_TYPE4) || (FM3MCUTYPE == FM3MCUTYPE_TYPE5))) + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 60 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif +#elif ((FM3MCUTYPE == FM3MCUTYPE_TYPE6) || (FM3MCUTYPE == FM3MCUTYPE_TYPE9)) + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 24 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 12 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_12MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 6 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 8 + #define USBETHERNETCLOCK_PLL_M 2 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif +#elif (FM3MCUTYPE == FM3MCUTYPE_TYPE2) + #if ((USBETHERNETCLOCK_USE_USB == 1) && (USBETHERNETCLOCK_USE_ETHERNET == 0)) + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 60 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_25MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 48 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #elif MAINCRYSTALFREQ == FREQ_50MHZ + #define USBETHERNETCLOCK_PLL_K 10 + #define USBETHERNETCLOCK_PLL_N 48 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif + #else + #if ETHERNETCLOCK_OUTFREQ == FREQ_25MHZ + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 6 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_50MHZ + #define USBETHERNETCLOCK_ECSEL 0x00 // CLKMO + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_PLL_K 6 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_50MHZ + #define USBETHERNETCLOCK_PLL_K 5 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 8 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif + #elif ETHERNETCLOCK_OUTFREQ == FREQ_50MHZ + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 3 + #define USBETHERNETCLOCK_PLL_N 50 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_25MHZ + #define USBETHERNETCLOCK_PLL_K 5 + #define USBETHERNETCLOCK_PLL_N 40 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_PLL_K 6 + #define USBETHERNETCLOCK_PLL_N 25 + #define USBETHERNETCLOCK_PLL_M 4 + #define USBETHERNETCLOCK_ECSEL 0x01 // USB/Ethernet-PLL oscillation clock + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif + #else + #error ETHERNETCLOCK must be 25MHz or 50MHz + #endif + + #if MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #elif __PLLCLK == FREQ_144MHZ + #define USBETHERNETCLOCK_UCSEL 0x02 // CLKPLL division clock + #define USBETHERNETCLOCK_UBSR (3 - 1) // Clock divided by 3 + #elif __PLLCLK == FREQ_96MHz + #define USBETHERNETCLOCK_UCSEL 0x02 // CLKPLL division clock + #define USBETHERNETCLOCK_UBSR (2 - 1) // Clock divided by 3 + #else + #if (USBETHERNETCLOCK_USE_USB == 1) + #error USB Clock Setting not supported + #endif + #endif + #endif +#elif defined(FM4MCUTYPE) && ((FM4MCUTYPE == FM4MCUTYPE_TYPE0) || (FM4MCUTYPE == FM4MCUTYPE_TYPE3)) + #if MAINCRYSTALFREQ == FREQ_4MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 60 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_8MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 30 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_16MHZ + #define USBETHERNETCLOCK_PLL_K 1 + #define USBETHERNETCLOCK_PLL_N 15 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_24MHZ + #define USBETHERNETCLOCK_PLL_K 2 + #define USBETHERNETCLOCK_PLL_N 20 + #define USBETHERNETCLOCK_PLL_M 5 + #define USBETHERNETCLOCK_UCSEL 0x01 // USB/Ethernet-PLL oscillation clock + #elif MAINCRYSTALFREQ == FREQ_48MHZ + #define USBETHERNETCLOCK_UCSEL 0x00 // CLKMO + #else + #error NOT SUPPORTED CRYSTAL / PLL SETTING FOR USB / ETHERNET CLOCK + #endif +#else + #error FM MCU TYPE UNKNOWN +#endif +*/ +#ifndef L3_PERIPHERAL_ENABLE_USB0 + #define L3_PERIPHERAL_ENABLE_USB0 L3_OFF +#endif + +#ifndef L3_PERIPHERAL_ENABLE_USB1 + #define L3_PERIPHERAL_ENABLE_USB1 L3_OFF +#endif + +#ifndef __IO + #define __IO volatile /*!< Defines 'read / write' permissions */ +#endif + +#ifndef FM3_PERIPH_BASE + #define FM3_PERIPH_BASE (0x40000000UL) /* Peripheral Base */ +#endif + + + +#if (FM3MCUTYPE == FM3MCUTYPE_TYPE2) +/************************************************************************************************************/ +/* FM3 Type 2 Ethernet USB Clock */ +/************************************************************************************************************/ + #ifdef FM3_USBCLK + #undef FM3_USBCLK + #warning You are using a mcu header file that is not valid for your choosen mcu type! (Operation of this module may work) + #endif + #ifdef FM3_USBCLK_BASE + #undef FM3_USBCLK_BASE + #endif + #ifdef bFM3_USBCLK_UPCR1_UPLLEN + #undef bFM3_USBCLK_UPCR1_UPLLEN + #endif + + #ifndef FM3_USBETHERNETCLK_BASE + #define FM3_USBETHERNETCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ + #endif + #ifdef FM3_USBETHERNETCLK + #undef FM3_USBETHERNETCLK + #define FM3_USBETHERNETCLK ((stc_usb_ethernetclkn_t *)FM3_USBETHERNETCLK_BASE) + #endif + #ifndef FM3_USBETHERNETCLK + #define FM3_USBETHERNETCLK ((stc_usb_ethernetclkn_t *)FM3_USBETHERNETCLK_BASE) + #endif + + #ifdef FM3_USBETHERNETCLK + #define FM_USBETHERCLK ((stc_usb_ethernetclkn_t *)FM3_USBETHERNETCLK) + #endif + /****************************************************************************** + * USB Ethernet CLK + ******************************************************************************/ + /* USB ETHERNET CLK register bit fields */ + typedef struct stc_usbethernetclkn_uccr_field + { + __IO uint8_t UCEN0 : 1; + __IO uint8_t UCSEL0 : 1; + __IO uint8_t UCSEL1 : 1; + __IO uint8_t UCEN1 : 1; + __IO uint8_t ECEN : 1; + __IO uint8_t ECSEL0 : 1; + __IO uint8_t ECSEL1 : 1; + } stc_usbethernetclkn_uccr_field_t; + + typedef struct stc_usbethernetclkn_upcr1_field + { + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; + } stc_usbethernetclkn_upcr1_field_t; + + typedef struct stc_usbethernetclkn_upcr2_field + { + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; + } stc_usbethernetclkn_upcr2_field_t; + + typedef struct stc_usbethernetclkn_upcr3_field + { + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; + } stc_usbethernetclkn_upcr3_field_t; + + typedef struct stc_usbethernetclkn_upcr4_field + { + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; + } stc_usbethernetclkn_upcr4_field_t; + + typedef struct stc_usbethernetclkn_up_str_field + { + __IO uint8_t UPRDY : 1; + } stc_usbethernetclkn_up_str_field_t; + + typedef struct stc_usbethernetclkn_upint_enr_field + { + __IO uint8_t UPCSE : 1; + } stc_usbethernetclkn_upint_enr_field_t; + + typedef struct stc_usbethernetclkn_upint_clr_field + { + __IO uint8_t UPCSC : 1; + } stc_usbethernetclkn_upint_clr_field_t; + + typedef struct stc_usbethernetclkn_upint_str_field + { + __IO uint8_t UPCSI : 1; + } stc_usbethernetclkn_upint_str_field_t; + + typedef struct stc_usbethernetclkn_upcr5_field + { + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; + } stc_usbethernetclkn_upcr5_field_t; + + typedef struct stc_usbethernetclkn_upcr6_field + { + __IO uint8_t UBSR0 : 1; + __IO uint8_t UBSR1 : 1; + __IO uint8_t UBSR2 : 1; + __IO uint8_t UBSR3 : 1; + } stc_usbethernetclkn_upcr6_field_t; + + typedef struct stc_usbethernetclkn_upcr7_field + { + __IO uint8_t EPLLEN : 1; + } stc_usbethernetclkn_upcr7_field_t; + + typedef struct stc_usbethernetclkn_usben0_field + { + __IO uint8_t USBEN0 : 1; + } stc_usbethernetclkn_usben0_field_t; + + typedef struct stc_usbethernetclkn_usben1_field + { + __IO uint8_t USBEN1 : 1; + } stc_usbethernetclkn_usben1_field_t; + + + /****************************************************************************** + * USBETHERNETCLK + ******************************************************************************/ + /* USB Ethernet clock registers */ + typedef struct stc_usb_ethernetclkn + { + union { + __IO uint8_t UCCR; + stc_usbethernetclkn_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbethernetclkn_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbethernetclkn_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbethernetclkn_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbethernetclkn_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbethernetclkn_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbethernetclkn_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbethernetclkn_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbethernetclkn_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbethernetclkn_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t UPCR6; + stc_usbethernetclkn_upcr6_field_t UPCR6_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t UPCR7; + stc_usbethernetclkn_upcr7_field_t UPCR7_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t USBEN0; + stc_usbethernetclkn_usben0_field_t USBEN0_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint8_t USBEN1; + stc_usbethernetclkn_usben1_field_t USBEN1_f; + }; + } stc_usb_ethernetclkn_t; + + /* USB clock registers */ + + + #define bFM_USBETHERCLK_UCCR_UCEN0 *((volatile unsigned int*)(0x426C0000UL)) + #define bFM_USBETHERCLK_UCCR_UCSEL0 *((volatile unsigned int*)(0x426C0004UL)) + #define bFM_USBETHERCLK_UCCR_UCSEL1 *((volatile unsigned int*)(0x426C0008UL)) + #define bFM_USBETHERCLK_UCCR_UCEN1 *((volatile unsigned int*)(0x426C000CUL)) + #define bFM_USBETHERCLK_UCCR_ECEN *((volatile unsigned int*)(0x426C0010UL)) + #define bFM_USBETHERCLK_UCCR_ECSEL0 *((volatile unsigned int*)(0x426C0014UL)) + #define bFM_USBETHERCLK_UCCR_ECSEL1 *((volatile unsigned int*)(0x426C0018UL)) + #define bFM_USBETHERCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) + #define bFM_USBETHERCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) + #define bFM_USBETHERCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) + #define bFM_USBETHERCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) + #define bFM_USBETHERCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) + #define bFM_USBETHERCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) + #define bFM_USBETHERCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) + #define bFM_USBETHERCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) + #define bFM_USBETHERCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) + #define bFM_USBETHERCLK_UPCR6_UBSR0 *((volatile unsigned int*)(0x426C0500UL)) + #define bFM_USBETHERCLK_UPCR6_UBSR1 *((volatile unsigned int*)(0x426C0504UL)) + #define bFM_USBETHERCLK_UPCR6_UBSR2 *((volatile unsigned int*)(0x426C0508UL)) + #define bFM_USBETHERCLK_UPCR6_UBSR3 *((volatile unsigned int*)(0x426C050CUL)) + #define bFM_USBETHERCLK_UPCR7_EPLLEN *((volatile unsigned int*)(0x426C0580UL)) + #define bFM_USBETHERCLK_USBEN0_USBEN0 *((volatile unsigned int*)(0x426C0600UL)) + #define bFM_USBETHERCLK_USBEN1_USBEN1 *((volatile unsigned int*)(0x426C0680UL)) + +#elif defined(FM3MCUTYPE) && (FM3MCUTYPE == FM3MCUTYPE_TYPE0) +/************************************************************************************************************/ +/* FM3 Type 0 USB Clock */ +/************************************************************************************************************/ + #ifdef FM3_USBETHERNETCLK + #undef FM3_USBETHERNETCLK + #warning You are using a mcu header file that is not valid for your choosen mcu type! (Operation of this module may work) + #endif + #ifdef FM3_USBETHERNETCLK_BASE + #undef FM3_USBETHERNETCLK_BASE + #endif + + #ifndef FM3_USBCLK_BASE + #define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ + #endif + #ifdef FM3_USBCLK + #define FM_USBCLK ((stc_usbclkn_t *)FM3_USBCLK_BASE) + #endif + /****************************************************************************** + * USBCLK + ******************************************************************************/ + /* USBCLK register bit fields */ + typedef struct stc_usbclkn_uccr_field + { + __IO uint8_t UCEN : 1; + __IO uint8_t UCSEL : 1; + } stc_usbclkn_uccr_field_t; + + typedef struct stc_usbclkn_upcr1_field + { + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; + } stc_usbclkn_upcr1_field_t; + + typedef struct stc_usbclkn_upcr2_field + { + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; + } stc_usbclkn_upcr2_field_t; + + typedef struct stc_usbclkn_upcr3_field + { + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; + } stc_usbclkn_upcr3_field_t; + + typedef struct stc_usbclkn_upcr4_field + { + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + } stc_usbclkn_upcr4_field_t; + + typedef struct stc_usbclkn_up_str_field + { + __IO uint8_t UPRDY : 1; + } stc_usbclkn_up_str_field_t; + + typedef struct stc_usbclkn_upint_enr_field + { + __IO uint8_t UPCSE : 1; + } stc_usbclkn_upint_enr_field_t; + + typedef struct stc_usbclkn_upint_clr_field + { + __IO uint8_t UPCSC : 1; + } stc_usbclkn_upint_clr_field_t; + + typedef struct stc_usbclkn_upint_str_field + { + __IO uint8_t UPCSI : 1; + } stc_usbclkn_upint_str_field_t; + + typedef struct stc_usbclkn_usben_field + { + __IO uint8_t USBEN : 1; + } stc_usbclkn_usben_field_t; + + + /****************************************************************************** + * USBCLK + ******************************************************************************/ + /* USB clock registers */ + typedef struct + { + union { + __IO uint8_t UCCR; + stc_usbclkn_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclkn_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclkn_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclkn_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclkn_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclkn_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclkn_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclkn_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclkn_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[15]; + union { + __IO uint8_t USBEN; + stc_usbclkn_usben_field_t USBEN_f; + }; + } stc_usbclkn_t; + + #define bFM_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) + #define bFM_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) + #define bFM_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) + #define bFM_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) + #define bFM_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) + #define bFM_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) + #define bFM_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) + #define bFM_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) + #define bFM_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) + #define bFM_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) + #define bFM_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) + #define bFM_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) + #define bFM_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) + #define bFM_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) + #define bFM_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) + #define bFM_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) + #define bFM_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) + #define bFM_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) + #define bFM_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) + #define bFM_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) + #define bFM_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) + #define bFM_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +#elif defined(FM4MCUTYPE) && (FM4MCUTYPE == FM4MCUTYPE_TYPE3) +/************************************************************************************************************/ +/* FM3 Type 2 Ethernet USB Clock */ +/************************************************************************************************************/ + #ifdef FM4_USBCLK + #undef FM4_USBCLK + #warning You are using a mcu header file that is not valid for your choosen mcu type! (Operation of this module may work) + #endif + #ifdef FM4_USBCLK_BASE + #undef FM4_USBCLK_BASE + #endif + #ifdef bFM4_USBCLK_UPCR1_UPLLEN + #undef bFM4_USBCLK_UPCR1_UPLLEN + #endif + #ifndef FM4_USBETHERNETCLK_BASE + #define FM4_USBETHERNETCLK_BASE (FM4_PERIPH_BASE + 0x36000UL) /* USB clock registers */ + #endif + #ifdef FM4_USBETHERNETCLK + #undef FM4_USBETHERNETCLK + #define FM4_USBETHERNETCLK ((stc_usb_ethernetclkn_t *)FM4_USBETHERNETCLK_BASE) + #endif + #ifndef FM4_USBETHERNETCLK + #define FM4_USBETHERNETCLK ((stc_usb_ethernetclkn_t *)FM4_USBETHERNETCLK_BASE) + #endif + + #ifdef FM4_USBETHERNETCLK + #define FM_USBETHERCLK ((stc_usb_ethernetclkn_t *)FM4_USBETHERNETCLK) + #endif + /****************************************************************************** + * USB Ethernet CLK + ******************************************************************************/ + /* USB ETHERNET CLK register bit fields */ + typedef struct stc_usbethernetclkn_uccr_field + { + __IO uint8_t UCEN0 : 1; + __IO uint8_t UCSEL0 : 1; + __IO uint8_t UCSEL1 : 1; + __IO uint8_t UCEN1 : 1; + __IO uint8_t ECEN : 1; + __IO uint8_t ECSEL0 : 1; + __IO uint8_t ECSEL1 : 1; + } stc_usbethernetclkn_uccr_field_t; + + typedef struct stc_usbethernetclkn_upcr1_field + { + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; + } stc_usbethernetclkn_upcr1_field_t; + + typedef struct stc_usbethernetclkn_upcr2_field + { + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; + } stc_usbethernetclkn_upcr2_field_t; + + typedef struct stc_usbethernetclkn_upcr3_field + { + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; + } stc_usbethernetclkn_upcr3_field_t; + + typedef struct stc_usbethernetclkn_upcr4_field + { + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; + } stc_usbethernetclkn_upcr4_field_t; + + typedef struct stc_usbethernetclkn_up_str_field + { + __IO uint8_t UPRDY : 1; + } stc_usbethernetclkn_up_str_field_t; + + typedef struct stc_usbethernetclkn_upint_enr_field + { + __IO uint8_t UPCSE : 1; + } stc_usbethernetclkn_upint_enr_field_t; + + typedef struct stc_usbethernetclkn_upint_clr_field + { + __IO uint8_t UPCSC : 1; + } stc_usbethernetclkn_upint_clr_field_t; + + typedef struct stc_usbethernetclkn_upint_str_field + { + __IO uint8_t UPCSI : 1; + } stc_usbethernetclkn_upint_str_field_t; + + typedef struct stc_usbethernetclkn_upcr5_field + { + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; + } stc_usbethernetclkn_upcr5_field_t; + + typedef struct stc_usbethernetclkn_upcr6_field + { + __IO uint8_t UBSR0 : 1; + __IO uint8_t UBSR1 : 1; + __IO uint8_t UBSR2 : 1; + __IO uint8_t UBSR3 : 1; + } stc_usbethernetclkn_upcr6_field_t; + + typedef struct stc_usbethernetclkn_upcr7_field + { + __IO uint8_t EPLLEN : 1; + } stc_usbethernetclkn_upcr7_field_t; + + typedef struct stc_usbethernetclkn_usben0_field + { + __IO uint8_t USBEN0 : 1; + } stc_usbethernetclkn_usben0_field_t; + + typedef struct stc_usbethernetclkn_usben1_field + { + __IO uint8_t USBEN1 : 1; + } stc_usbethernetclkn_usben1_field_t; + + + /****************************************************************************** + * USBETHERNETCLK + ******************************************************************************/ + /* USB Ethernet clock registers */ + typedef struct stc_usb_ethernetclkn + { + union { + __IO uint8_t UCCR; + stc_usbethernetclkn_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbethernetclkn_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbethernetclkn_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbethernetclkn_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbethernetclkn_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbethernetclkn_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbethernetclkn_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbethernetclkn_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbethernetclkn_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbethernetclkn_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[3]; + union { + __IO uint8_t UPCR6; + stc_usbethernetclkn_upcr6_field_t UPCR6_f; + }; + uint8_t RESERVED10[3]; + union { + __IO uint8_t UPCR7; + stc_usbethernetclkn_upcr7_field_t UPCR7_f; + }; + uint8_t RESERVED11[3]; + union { + __IO uint8_t USBEN0; + stc_usbethernetclkn_usben0_field_t USBEN0_f; + }; + uint8_t RESERVED12[3]; + union { + __IO uint8_t USBEN1; + stc_usbethernetclkn_usben1_field_t USBEN1_f; + }; + } stc_usb_ethernetclkn_t; + + /* USB clock registers */ + + + #define bFM_USBETHERCLK_UCCR_UCEN0 *((volatile unsigned int*)(0x426C0000UL)) + #define bFM_USBETHERCLK_UCCR_UCSEL0 *((volatile unsigned int*)(0x426C0004UL)) + #define bFM_USBETHERCLK_UCCR_UCSEL1 *((volatile unsigned int*)(0x426C0008UL)) + #define bFM_USBETHERCLK_UCCR_UCEN1 *((volatile unsigned int*)(0x426C000CUL)) + #define bFM_USBETHERCLK_UCCR_ECEN *((volatile unsigned int*)(0x426C0010UL)) + #define bFM_USBETHERCLK_UCCR_ECSEL0 *((volatile unsigned int*)(0x426C0014UL)) + #define bFM_USBETHERCLK_UCCR_ECSEL1 *((volatile unsigned int*)(0x426C0018UL)) + #define bFM_USBETHERCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) + #define bFM_USBETHERCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) + #define bFM_USBETHERCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) + #define bFM_USBETHERCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) + #define bFM_USBETHERCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) + #define bFM_USBETHERCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) + #define bFM_USBETHERCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) + #define bFM_USBETHERCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) + #define bFM_USBETHERCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) + #define bFM_USBETHERCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) + #define bFM_USBETHERCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) + #define bFM_USBETHERCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) + #define bFM_USBETHERCLK_UPCR6_UBSR0 *((volatile unsigned int*)(0x426C0500UL)) + #define bFM_USBETHERCLK_UPCR6_UBSR1 *((volatile unsigned int*)(0x426C0504UL)) + #define bFM_USBETHERCLK_UPCR6_UBSR2 *((volatile unsigned int*)(0x426C0508UL)) + #define bFM_USBETHERCLK_UPCR6_UBSR3 *((volatile unsigned int*)(0x426C050CUL)) + #define bFM_USBETHERCLK_UPCR7_EPLLEN *((volatile unsigned int*)(0x426C0580UL)) + #define bFM_USBETHERCLK_USBEN0_USBEN0 *((volatile unsigned int*)(0x426C0600UL)) + #define bFM_USBETHERCLK_USBEN1_USBEN1 *((volatile unsigned int*)(0x426C0680UL)) + + +#elif defined(FM4MCUTYPE) +/************************************************************************************************************/ +/* FM4 General USB Clock */ +/************************************************************************************************************/ + #ifdef FM4_USBETHERNETCLK + #undef FM4_USBETHERNETCLK + #warning You are using a mcu header file that is not valid for your choosen mcu type! (Operation of this module may work) + #endif + #ifdef FM4_USBETHERNETCLK_BASE + #undef FM4_USBETHERNETCLK_BASE + #endif + + #ifndef FM4_USBCLK_BASE + #define FM4_USBCLK_BASE (FM4_PERIPH_BASE + 0x36000UL) /* USB clock registers */ + #endif + #ifdef FM4_USBCLK + #define FM_USBCLK ((stc_usbclkn_t *)FM4_USBCLK_BASE) + #endif + + /****************************************************************************** + * USBCLK + ******************************************************************************/ + /* USBCLK register bit fields */ + typedef struct stc_usbclkn_uccr_field + { + __IO uint8_t UCEN : 1; + __IO uint8_t UCSEL : 1; + } stc_usbclkn_uccr_field_t; + + typedef struct stc_usbclkn_upcr1_field + { + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; + } stc_usbclkn_upcr1_field_t; + + typedef struct stc_usbclkn_upcr2_field + { + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; + } stc_usbclkn_upcr2_field_t; + + typedef struct stc_usbclkn_upcr3_field + { + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; + } stc_usbclkn_upcr3_field_t; + + typedef struct stc_usbclkn_upcr4_field + { + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; + } stc_usbclkn_upcr4_field_t; + + typedef struct stc_usbclkn_up_str_field + { + __IO uint8_t UPRDY : 1; + } stc_usbclkn_up_str_field_t; + + typedef struct stc_usbclkn_upint_enr_field + { + __IO uint8_t UPCSE : 1; + } stc_usbclkn_upint_enr_field_t; + + typedef struct stc_usbclkn_upint_clr_field + { + __IO uint8_t UPCSC : 1; + } stc_usbclkn_upint_clr_field_t; + + typedef struct stc_usbclkn_upint_str_field + { + __IO uint8_t UPCSI : 1; + } stc_usbclkn_upint_str_field_t; + + typedef struct stc_usbclkn_upcr5_field + { + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; + } stc_usbclkn_upcr5_field_t; + + typedef struct stc_usbclkn_usben_field + { + __IO uint8_t USBEN : 1; + } stc_usbclkn_usben_field_t; + /****************************************************************************** + * USBCLK + ******************************************************************************/ + /* USB clock registers */ + typedef struct + { + union { + __IO uint8_t UCCR; + stc_usbclkn_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclkn_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclkn_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclkn_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclkn_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclkn_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclkn_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclkn_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclkn_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbclkn_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[11]; + union { + __IO uint8_t USBEN; + stc_usbclkn_usben_field_t USBEN_f; + }; + }stc_usbclkn_t; + /* USB clock registers */ + + #define bFM_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) + #define bFM_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) + #define bFM_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) + #define bFM_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) + #define bFM_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) + #define bFM_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) + #define bFM_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) + #define bFM_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) + #define bFM_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) + #define bFM_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) + #define bFM_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) + #define bFM_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) + #define bFM_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) + #define bFM_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) + #define bFM_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) + #define bFM_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) + #define bFM_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) + #define bFM_USBCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) + #define bFM_USBCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) + #define bFM_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) + #define bFM_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) + #define bFM_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) + #define bFM_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) + #define bFM_USBCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) + #define bFM_USBCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) + #define bFM_USBCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) + #define bFM_USBCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) + #define bFM_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) + +#elif defined(FM3MCUTYPE) +/************************************************************************************************************/ +/* FM3 General USB Clock */ +/************************************************************************************************************/ + #ifdef FM3_USBETHERNETCLK + #undef FM3_USBETHERNETCLK + #warning You are using a mcu header file that is not valid for your choosen mcu type! (Operation of this module may work) + #endif + #ifdef FM3_USBETHERNETCLK_BASE + #undef FM3_USBETHERNETCLK_BASE + #endif + + #ifndef FM3_USBCLK_BASE + #define FM3_USBCLK_BASE (FM3_PERIPH_BASE + 0x36000UL) /* USB clock registers */ + #endif + #ifdef FM3_USBCLK + #define FM_USBCLK ((stc_usbclkn_t *)FM3_USBCLK_BASE) + #endif + + /****************************************************************************** + * USBCLK + ******************************************************************************/ + /* USBCLK register bit fields */ + typedef struct stc_usbclkn_uccr_field + { + __IO uint8_t UCEN : 1; + __IO uint8_t UCSEL : 1; + } stc_usbclkn_uccr_field_t; + + typedef struct stc_usbclkn_upcr1_field + { + __IO uint8_t UPLLEN : 1; + __IO uint8_t UPINC : 1; + } stc_usbclkn_upcr1_field_t; + + typedef struct stc_usbclkn_upcr2_field + { + __IO uint8_t UPOWT0 : 1; + __IO uint8_t UPOWT1 : 1; + __IO uint8_t UPOWT2 : 1; + } stc_usbclkn_upcr2_field_t; + + typedef struct stc_usbclkn_upcr3_field + { + __IO uint8_t UPLLK0 : 1; + __IO uint8_t UPLLK1 : 1; + __IO uint8_t UPLLK2 : 1; + __IO uint8_t UPLLK3 : 1; + __IO uint8_t UPLLK4 : 1; + } stc_usbclkn_upcr3_field_t; + + typedef struct stc_usbclkn_upcr4_field + { + __IO uint8_t UPLLN0 : 1; + __IO uint8_t UPLLN1 : 1; + __IO uint8_t UPLLN2 : 1; + __IO uint8_t UPLLN3 : 1; + __IO uint8_t UPLLN4 : 1; + __IO uint8_t UPLLN5 : 1; + __IO uint8_t UPLLN6 : 1; + } stc_usbclkn_upcr4_field_t; + + typedef struct stc_usbclkn_up_str_field + { + __IO uint8_t UPRDY : 1; + } stc_usbclkn_up_str_field_t; + + typedef struct stc_usbclkn_upint_enr_field + { + __IO uint8_t UPCSE : 1; + } stc_usbclkn_upint_enr_field_t; + + typedef struct stc_usbclkn_upint_clr_field + { + __IO uint8_t UPCSC : 1; + } stc_usbclkn_upint_clr_field_t; + + typedef struct stc_usbclkn_upint_str_field + { + __IO uint8_t UPCSI : 1; + } stc_usbclkn_upint_str_field_t; + + typedef struct stc_usbclkn_upcr5_field + { + __IO uint8_t UPLLM0 : 1; + __IO uint8_t UPLLM1 : 1; + __IO uint8_t UPLLM2 : 1; + __IO uint8_t UPLLM3 : 1; + } stc_usbclkn_upcr5_field_t; + + typedef struct stc_usbclkn_usben_field + { + __IO uint8_t USBEN : 1; + } stc_usbclkn_usben_field_t; + /****************************************************************************** + * USBCLK + ******************************************************************************/ + /* USB clock registers */ + typedef struct + { + union { + __IO uint8_t UCCR; + stc_usbclkn_uccr_field_t UCCR_f; + }; + uint8_t RESERVED0[3]; + union { + __IO uint8_t UPCR1; + stc_usbclkn_upcr1_field_t UPCR1_f; + }; + uint8_t RESERVED1[3]; + union { + __IO uint8_t UPCR2; + stc_usbclkn_upcr2_field_t UPCR2_f; + }; + uint8_t RESERVED2[3]; + union { + __IO uint8_t UPCR3; + stc_usbclkn_upcr3_field_t UPCR3_f; + }; + uint8_t RESERVED3[3]; + union { + __IO uint8_t UPCR4; + stc_usbclkn_upcr4_field_t UPCR4_f; + }; + uint8_t RESERVED4[3]; + union { + __IO uint8_t UP_STR; + stc_usbclkn_up_str_field_t UP_STR_f; + }; + uint8_t RESERVED5[3]; + union { + __IO uint8_t UPINT_ENR; + stc_usbclkn_upint_enr_field_t UPINT_ENR_f; + }; + uint8_t RESERVED6[3]; + union { + __IO uint8_t UPINT_CLR; + stc_usbclkn_upint_clr_field_t UPINT_CLR_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint8_t UPINT_STR; + stc_usbclkn_upint_str_field_t UPINT_STR_f; + }; + uint8_t RESERVED8[3]; + union { + __IO uint8_t UPCR5; + stc_usbclkn_upcr5_field_t UPCR5_f; + }; + uint8_t RESERVED9[11]; + union { + __IO uint8_t USBEN; + stc_usbclkn_usben_field_t USBEN_f; + }; + }stc_usbclkn_t; + /* USB clock registers */ + + #define bFM_USBCLK_UCCR_UCEN *((volatile unsigned int*)(0x426C0000UL)) + #define bFM_USBCLK_UCCR_UCSEL *((volatile unsigned int*)(0x426C0004UL)) + #define bFM_USBCLK_UPCR1_UPLLEN *((volatile unsigned int*)(0x426C0080UL)) + #define bFM_USBCLK_UPCR1_UPINC *((volatile unsigned int*)(0x426C0084UL)) + #define bFM_USBCLK_UPCR2_UPOWT0 *((volatile unsigned int*)(0x426C0100UL)) + #define bFM_USBCLK_UPCR2_UPOWT1 *((volatile unsigned int*)(0x426C0104UL)) + #define bFM_USBCLK_UPCR2_UPOWT2 *((volatile unsigned int*)(0x426C0108UL)) + #define bFM_USBCLK_UPCR3_UPLLK0 *((volatile unsigned int*)(0x426C0180UL)) + #define bFM_USBCLK_UPCR3_UPLLK1 *((volatile unsigned int*)(0x426C0184UL)) + #define bFM_USBCLK_UPCR3_UPLLK2 *((volatile unsigned int*)(0x426C0188UL)) + #define bFM_USBCLK_UPCR3_UPLLK3 *((volatile unsigned int*)(0x426C018CUL)) + #define bFM_USBCLK_UPCR3_UPLLK4 *((volatile unsigned int*)(0x426C0190UL)) + #define bFM_USBCLK_UPCR4_UPLLN0 *((volatile unsigned int*)(0x426C0200UL)) + #define bFM_USBCLK_UPCR4_UPLLN1 *((volatile unsigned int*)(0x426C0204UL)) + #define bFM_USBCLK_UPCR4_UPLLN2 *((volatile unsigned int*)(0x426C0208UL)) + #define bFM_USBCLK_UPCR4_UPLLN3 *((volatile unsigned int*)(0x426C020CUL)) + #define bFM_USBCLK_UPCR4_UPLLN4 *((volatile unsigned int*)(0x426C0210UL)) + #define bFM_USBCLK_UPCR4_UPLLN5 *((volatile unsigned int*)(0x426C0214UL)) + #define bFM_USBCLK_UPCR4_UPLLN6 *((volatile unsigned int*)(0x426C0218UL)) + #define bFM_USBCLK_UP_STR_UPRDY *((volatile unsigned int*)(0x426C0280UL)) + #define bFM_USBCLK_UPINT_ENR_UPCSE *((volatile unsigned int*)(0x426C0300UL)) + #define bFM_USBCLK_UPINT_CLR_UPCSC *((volatile unsigned int*)(0x426C0380UL)) + #define bFM_USBCLK_UPINT_STR_UPCSI *((volatile unsigned int*)(0x426C0400UL)) + #define bFM_USBCLK_UPCR5_UPLLM0 *((volatile unsigned int*)(0x426C0480UL)) + #define bFM_USBCLK_UPCR5_UPLLM1 *((volatile unsigned int*)(0x426C0484UL)) + #define bFM_USBCLK_UPCR5_UPLLM2 *((volatile unsigned int*)(0x426C0488UL)) + #define bFM_USBCLK_UPCR5_UPLLM3 *((volatile unsigned int*)(0x426C048CUL)) + #define bFM_USBCLK_USBEN_USBEN *((volatile unsigned int*)(0x426C0600UL)) +#else + #error MCU type could not be detected +#endif +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +#ifdef __cplusplus +} +#endif + +//@} // UsbEthernetClockLegacyGroup + +#endif /* __USBETHERNETCLOCKLEGACY_H__*/ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.c new file mode 100644 index 0000000000..49aa0da669 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.c @@ -0,0 +1,1698 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbhost.c + ** + ** A detailed description is available at + ** @link UsbHostGroup USB Host Module description @endlink + ** + ** History: + ** - 2012-08-28 2.0 MSc First version (starting at version 2.0). + ** - 2012-11-13 2.1 MSc Some problems while switching from Host to Device fixed + ** - 2013-01-28 2.2 MSc Better Device Detection + ** - 2013-06-04 2.3 MSc FM4 support added + ** - 2014-02-28 2.4 MSc Speedup in package handling, fixes in fifo initialization + ** ISO transfers added + ** - 2014-05-06 2.5 MSc Fixing some variable initializations in disconnect routine + ** Added USBHOST_CONNECTION_DELAY to specify a delay in interations + ** for bus-reset / connection delay + ** - 2014-07-25 2.6 MSc Updated memory usage EP0 + ** - 2014-09-03 2.7 MSc Doxygen examples added + ** - 2015-09-03 2.8 MSCH Fixed disconnection deinitializations + ** + ******************************************************************************/ + + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + + +#include "usbhost.h" + +#if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + +#include "usbhostclasssupervisor.h" + +#if (USE_USBHOSTHW_H == 1) +#include "usbhosthw.h" +#endif + +/** + ****************************************************************************** + ** \addtogroup UsbHostGroup + ******************************************************************************/ +//@{ + + + + +const stc_usb_request_t stcDeviceDescriptorRequest = {0x80,0x06,0x0100,0x00,18}; +const stc_usb_request_t stcShortDeviceDescriptorRequest = {0x80,0x06,0x0100,0x00,8}; +const stc_usb_request_t stcClearStallEp0 = {0x02,0x01,0x0000,0x00,0x00}; + + +static stc_usbhost_intern_data_t* UsbHostGetInternDataPtr(stc_usbn_t* pstcUsb) ; +static void EnumerationStateMachine(stc_usbn_t* pstcUsb); +static void ConvertRequestToByteArray(uint8_t* pu8Buffer, stc_usb_request_t* pstcSetup); +static void StallCompletionEp0(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32Size); +static void UsbHost_SetupComplete(stc_usbn_t* pstcUsb); + + + +/// Macro to return the number of enabled MFS instances +#define USBHOST_INSTANCE_COUNT (uint32_t)(sizeof(m_astcUsbHostInstanceDataLut) / sizeof(m_astcUsbHostInstanceDataLut[0])) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled MFS instances and their internal data +stc_usbhostn_instance_data_t m_astcUsbHostInstanceDataLut[] = +{ + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (defined(USB0)) && (FM_PERIPHERAL_ENABLE_USB0_HOST == ON)) + { &USB0, // pstcInstance + NULL // stcInternData (not initialized yet) + }, + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (defined(USB1)) && (FM_PERIPHERAL_ENABLE_USB1_HOST == ON)) + { &USB1, // pstcInstance + NULL // stcInternData (not initialized yet) + } + #endif +}; + + + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain USB instance. + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_usbhost_intern_data_t* UsbHostGetInternDataPtr(stc_usbn_t* pstcUsb) +{ + volatile uint32_t u32Instance; + + for (u32Instance = 0; u32Instance < USBHOST_INSTANCE_COUNT; u32Instance++) + { + if ((uint32_t)pstcUsb == (uint32_t)(m_astcUsbHostInstanceDataLut[u32Instance].pstcInstance)) + { + return &m_astcUsbHostInstanceDataLut[u32Instance].stcInternData; + } + } + + return NULL; +} + + +/** + ****************************************************************************** + ** \brief Add new endpoint + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcHandler returns pointer to stc_host_endpoint_t (pointer of pointer) + ** + ** \param u8EndpointAddress Endpointaddress + ** + ** \param u16FifoSize Fifosize + ** + ** \param u8Interval Interval (for interrupt transfers) + ** + ** \param CompletionHandler Transfer completion callback routine + ** + ** \return USBHOST_SUCCESS at success + ** + ******************************************************************************/ +uint8_t UsbHost_AddHostEndpoint(stc_usbn_t* pstcUsb, stc_host_endpoint_t** pstcHandler, uint8_t u8EndpointAddress, uint16_t u16FifoSize, uint8_t u8Interval, void(* CompletionHandler)(stc_usbn_t* pstcUsb)) +{ + uint8_t i; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + volatile boolean_t bOldSchedulerLockState; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + bOldSchedulerLockState = pstcUsbHostIntern->bSchedulerLock; + pstcUsbHostIntern->bSchedulerLock = TRUE; + pstcUsbHostIntern->bSchedulerLock = TRUE; + pstcUsbHostIntern->bSchedulerLock = TRUE; + for(i=0;iastcHostEndpoints[i].u16FifoSize == 0) || ((&pstcUsbHostIntern->astcHostEndpoints[i] == *pstcHandler) && (*pstcHandler != 0))) + { + if ((&pstcUsbHostIntern->astcHostEndpoints[i] == *pstcHandler) && (*pstcHandler != 0)) + { + USBDBG(" |->Endpoint exists in list...\n"); + } + USBDBGVAL8(" |->New EP, Address: ",u8EndpointAddress); + pstcUsbHostIntern->astcHostEndpoints[i].u8Stage = 0; + pstcUsbHostIntern->astcHostEndpoints[i].u8Status = 0; + pstcUsbHostIntern->astcHostEndpoints[i].u16FifoSize = u16FifoSize; + pstcUsbHostIntern->astcHostEndpoints[i].u8Address = u8EndpointAddress; + pstcUsbHostIntern->astcHostEndpoints[i].u8Interval = u8Interval; + pstcUsbHostIntern->astcHostEndpoints[i].u8IntervalCount = u8Interval; + pstcUsbHostIntern->astcHostEndpoints[i].CompletionHandler = CompletionHandler; + *pstcHandler = &pstcUsbHostIntern->astcHostEndpoints[i]; + USBDBGVAL8(" |->New EP, Index: ",i); + USBDBGVAL32(" |->New EP, Handler: ",*pstcHandler); + pstcUsbHostIntern->u8EndpointListEnd = i; + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + return USBHOST_SUCCESS; + } + } + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + return USBHOST_ERROR; +} + +/** + ****************************************************************************** + ** \brief Get pointzer to host endpoint via endpoint address + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param u8EndpointNumber Endpointaddress + ** + ** \return Pointer to stc_host_endpoint_t + ** + ******************************************************************************/ +stc_host_endpoint_t* UsbHost_EndpointFromNumber(stc_usbn_t* pstcUsb, uint8_t u8EndpointNumber) +{ + uint8_t i; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + + for(i=0;i<=pstcUsbHostIntern->u8EndpointListEnd;i++) + { + if ((pstcUsbHostIntern->astcHostEndpoints[i].u8Address & 0x0F) == u8EndpointNumber) + { + return &pstcUsbHostIntern->astcHostEndpoints[i]; + } + } + return NULL; +} + +/** + ****************************************************************************** + ** \brief Force abort current transfer + ** + ** \param pstcEndpoint Endpoint handle + ** + ******************************************************************************/ +void UsbHost_AbortTransfer(stc_host_endpoint_t* pstcEndpoint) +{ + if (pstcEndpoint == NULL) + { + return; + } + pstcEndpoint->bAbortTransfer = TRUE; +} + + +/** + ****************************************************************************** + ** \brief Force reset data toggle + ** + ** \param pstcEndpoint Endpoint handle + ** + ******************************************************************************/ +void UsbHost_ResetToggle(stc_host_endpoint_t* pstcEndpoint) +{ + if (pstcEndpoint == NULL) + { + return; + } + pstcEndpoint->bToggle = FALSE; +} + +/** + ****************************************************************************** + ** \brief Completion callback for ClearEndpoint setup request + ** + ** \param pstcUsb USB handle + ** + ** \param pu8Buffer data buffer (not used) + ** + ** \param u32DataSize data size (not used) + ** + ******************************************************************************/ +void UsbHost_ClearEndpointCompletion(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + if (pstcUsbHostIntern->pstcClearEndpoint == NULL) + { + return; + } + UsbHost_ResetToggle(pstcUsbHostIntern->pstcClearEndpoint); + pstcUsbHostIntern->pstcClearEndpoint->bAbortTransfer = FALSE; + pstcUsbHostIntern->pstcClearEndpoint = NULL; +} + +/** + ****************************************************************************** + ** \brief Clear endpoint setup request + ** + ** \param pstcUsb USB handle + ** + ** \param pstcEndpoint Endpoint handle + ** + ******************************************************************************/ +void UsbHost_ClearEndpoint(stc_usbn_t* pstcUsb, stc_host_endpoint_t* pstcEndpoint) +{ + stc_usb_request_t setup; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + ZERO_STRUCT(setup); + setup.bmRequestType=0x02; + setup.bRequest=0x01; + setup.wValue=0x00; + setup.wIndex=pstcEndpoint->u8Address; + setup.wLength=0x00; + UsbHost_AbortTransfer(pstcEndpoint); + pstcUsbHostIntern->pstcClearEndpoint = pstcEndpoint; + UsbHost_SetupRequest(pstcUsb,&setup,UsbHost_ClearEndpointCompletion); + return; +} +/** + ****************************************************************************** + ** \brief Clear endpoint setup request (polled) + ** + ** \param pstcUsb USB handle + ** + ** \param pstcEndpoint Endpoint handle + ** + ******************************************************************************/ +void UsbHost_ClearEndpointPoll(stc_usbn_t* pstcUsb, stc_host_endpoint_t* pstcEndpoint) +{ + volatile uint32_t u32Timeout = 1000000; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + UsbHost_ClearEndpoint(pstcUsb, pstcEndpoint); + while((pstcUsbHostIntern->pstcClearEndpoint != NULL) && (u32Timeout > 0)) u32Timeout--; +} + +/** + ****************************************************************************** + ** \brief Enumeration Statemachine + ** + ** \param pstcUsb Pointer to USB instance + ** + ** + ******************************************************************************/ +static void EnumerationStateMachine(stc_usbn_t* pstcUsb) +{ + uint8_t* pu8SetupBuffer; + uint32_t u32Size = UsbHost_ReceiveSetupData(pstcUsb, &pu8SetupBuffer); + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + pstcUsbHostIntern->Ep0IN->CompletionHandler = 0; + + USBDBG("ENUM STATEMACH\n"); + if (pu8SetupBuffer != 0) + { + if (u32Size > 0) + { + if (pu8SetupBuffer[1] == 0x02) + { + USBDBG("Received Configuration\n"); + } + if (pu8SetupBuffer[1] == 0x01) + { + USBDBG("Enumeration Process:\n"); + USBDBG(" ->Received Device Descriptor\n"); + USBDBGVAL16(" ->New EP0 buffersize: ",(uint16_t)((uint8_t)pu8SetupBuffer[7])); + pstcUsbHostIntern->Ep0IN->u16FifoSize = (uint16_t)((uint8_t)pu8SetupBuffer[7]); + pstcUsbHostIntern->Ep0OUT->u16FifoSize = (uint16_t)((uint8_t)pu8SetupBuffer[7]); + } + } + else + { + if (pstcUsbHostIntern->u8DeviceStatus == USBHOST_DEVICE_ADDRESSING) + { + pstcUsbHostIntern->u8EnumerationCounter = 0; + pstcUsb->HADR = pstcUsbHostIntern->u8DeviceAddress; + USBDBG("Enumeration Process:\n"); + USBDBGVAL8(" ->Addressed: ",pstcUsbHostIntern->u8DeviceAddress); + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_ADDRESSED; + //UsbClassSupervisor_Init(pstcUsb); + } + } + } + else + { + if (pstcUsbHostIntern->Ep0IN->u16FifoSize == 20) + { + USBDBG("Enumeration Process:\n"); + USBDBG(" -> Endpoint 0 has no Fifo size specified.\n"); + USBDBG(" Requesting Device Descriptor.\n"); + UsbHost_SetupRequest(pstcUsb,(stc_usb_request_t *)&stcShortDeviceDescriptorRequest,0); + } + else + { + if (pstcUsbHostIntern->u8DeviceStatus == USBHOST_DEVICE_IDLE) + { + USBDBG("Enumeration Process:\n"); + pstcUsbHostIntern->Ep0IN->CompletionHandler = EnumerationStateMachine; + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_ADDRESSING; + UsbHost_AddressDevice(pstcUsb, 2); + pstcUsbHostIntern->u8EnumerationCounter = 0; + } + } + } + if (pstcUsbHostIntern->u8DeviceStatus != USBHOST_DEVICE_ADDRESSED) + { + pstcUsbHostIntern->u8EnumerationCounter++; + if (pstcUsbHostIntern->u8EnumerationCounter == 40) + { + pstcUsbHostIntern->u32ConnectionDelay -= 1000; + if (pstcUsbHostIntern->u32ConnectionDelay <= 1000) + { + pstcUsbHostIntern->u32ConnectionDelay = USBHOST_CONNECTION_DELAY; + } + pstcUsbHostIntern->u8EnumerationCounter = 0; + //UsbHost_DeInit(); + //UsbHost_Init(); + } + + if (pstcUsbHostIntern->u8EnumerationCounter > 50) + { + /*stc_usb_request_t stcSetup; + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_IDLE; + USBDBG("Enumeration timed out...\n"); + pstcUsbHostIntern->u8EnumerationCounter = 0; + USBDBG("ENUMERATION FAILED - SYSTEM HALT\n"); + stcSetup.bmRequestType=0x82; + stcSetup.bRequest=0x00; + stcSetup.wValue=0x00; + stcSetup.wIndex=0x00; + stcSetup.wLength=0x02; + UsbHost_SetupRequest(pstcUsb, (stc_usb_request_t *)&stcShortDeviceDescriptorRequest,EndpointInStatusUpdate);*/ + } + else + { + Usb_AddTimeOut(pstcUsb, EnumerationStateMachine,100); + } + } + else + { + UsbClassSupervisor_Init(pstcUsb); + } +} + +/** + ****************************************************************************** + ** \brief Convert stc_usb_request_t to byte array + ** + ** \param pu8Buffer pointer to byte array + ** + ** \param pstcSetup Setup request + ** + ******************************************************************************/ +static void ConvertRequestToByteArray(uint8_t* pu8Buffer, stc_usb_request_t* pstcSetup) +{ + pu8Buffer[0] = pstcSetup->bmRequestType; + pu8Buffer[1] = pstcSetup->bRequest; + pu8Buffer[2] = (uint8_t)(pstcSetup->wValue & 0xFF); + pu8Buffer[3] = (uint8_t)((pstcSetup->wValue >> 8) & 0xFF); + pu8Buffer[4] = (uint8_t)(pstcSetup->wIndex & 0xFF); + pu8Buffer[5] = (uint8_t)((pstcSetup->wIndex >> 8) & 0xFF); + pu8Buffer[6] = (uint8_t)(pstcSetup->wLength & 0xFF); + pu8Buffer[7] = (uint8_t)((pstcSetup->wLength >> 8) & 0xFF); +} + +/** + ****************************************************************************** + ** \brief Address device + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param u8NewAddress New address + ** + ******************************************************************************/ +void UsbHost_AddressDevice(stc_usbn_t* pstcUsb, uint8_t u8NewAddress) +{ + stc_usb_request_t stcSetup = {0x00,0x05,0x02,0x00,0x00}; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + + USBDBGVAL8("Start Addressing: ",u8NewAddress); + stcSetup.wValue = u8NewAddress; + pstcUsbHostIntern->u8DeviceAddress = u8NewAddress; // Device Address = NewAddress + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_ADDRESSING; + UsbHost_SetupRequest(pstcUsb, &stcSetup,NULL); +} + +/** + ****************************************************************************** + ** \brief Receive data of setup request + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pu8Buffer pointer returned + ** + ** \return length + ** + ******************************************************************************/ +uint32_t UsbHost_ReceiveSetupData(stc_usbn_t* pstcUsb, uint8_t** pu8Buffer) +{ + uint32_t u32Size; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + + if (pstcUsbHostIntern->Ep0IN->u8Status & USBHOST_ENDPOINTSTATUS_DATA) + { + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_DATA; + *pu8Buffer = pstcUsbHostIntern->Ep0IN->pu8Buffer; + u32Size = (pstcUsbHostIntern->Ep0IN->u32DataSize); + return u32Size; + } + *pu8Buffer = 0; + return 0; +} + +/** + ****************************************************************************** + ** \brief Add data package to setup package + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcSetup setup request + ** + ** \param pu8Data data to send + ** + ** \param SetupCompletion completion callback routine + ** + ******************************************************************************/ +void UsbHost_SetupRequestWithData(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup, uint8_t* pu8Data, void(*SetupCompletion)(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize)) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + pstcUsbHostIntern->pu8SetupData = pu8Data; + UsbHost_SetupRequest(pstcUsb, pstcSetup,SetupCompletion); +} + +/** + ****************************************************************************** + ** \brief Send setup package + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcSetup setup request + ** + ** \param SetupCompletion completion callback routine + ** + ******************************************************************************/ +void UsbHost_SetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup, void(*SetupCompletion)(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize)) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + volatile boolean_t bOldSchedulerLockState; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + bOldSchedulerLockState = pstcUsbHostIntern->bSchedulerLock; + if ((pstcUsbHostIntern->Ep0IN->u8Status & USBHOST_ENDPOINTSTATUS_INUSE) || (pstcUsbHostIntern->Ep0OUT->u8Status & USBHOST_ENDPOINTSTATUS_INUSE)) + { + return; + } + pstcUsbHostIntern->bSchedulerLock = TRUE; + pstcUsbHostIntern->SetupCompletionHandler = SetupCompletion; + if ((((pstcUsbHostIntern->Ep0IN->u8Status) & USBHOST_ENDPOINTSTATUS_STALL) == 0) && (((pstcUsbHostIntern->Ep0OUT->u8Status) & USBHOST_ENDPOINTSTATUS_STALL) == 0)) + { + memcpy((uint8_t*)&pstcUsbHostIntern->stcLastSetup,(uint8_t*)pstcSetup,sizeof(pstcUsbHostIntern->stcLastSetup)); + } + ConvertRequestToByteArray(pstcUsbHostIntern->pu8Setup,pstcSetup); + USBDBGVAL8("Setup [0]",pstcUsbHostIntern->pu8Setup[0]); + USBDBGVAL8("[1]",pstcUsbHostIntern->pu8Setup[1]); + USBDBGVAL8("[2]",pstcUsbHostIntern->pu8Setup[2]); + USBDBGVAL8("[3]",pstcUsbHostIntern->pu8Setup[3]); + USBDBGVAL8("[4]",pstcUsbHostIntern->pu8Setup[4]); + USBDBGVAL8("[5]",pstcUsbHostIntern->pu8Setup[5]); + USBDBGVAL8("[6]",pstcUsbHostIntern->pu8Setup[6]); + USBDBGVAL8("[7]",pstcUsbHostIntern->pu8Setup[7]); + + //UsbHost_TransferDataToFifo(pstcUsb, pstcUsbHostIntern->pu8Setup,8,pstcUsbHostIntern->Ep0OUT->u16FifoSize); + + pstcUsbHostIntern->Ep0OUT->u8Stage = USBHOST_STAGE_SETUP; + pstcUsbHostIntern->Ep0IN->u8Stage = USBHOST_STAGE_SETUP; + + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + + pstcUsbHostIntern->Ep0IN->pu8BufferPos = pstcUsbHostIntern->Ep0IN->pu8Buffer; + pstcUsbHostIntern->Ep0IN->pu8BufferPosNextPackage = pstcUsbHostIntern->Ep0IN->pu8Buffer; + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_DATA; + pstcUsbHostIntern->Ep0OUT->bToggle = FALSE; + pstcUsbHostIntern->Ep0OUT->u32DataSize = 8; + pstcUsbHostIntern->Ep0OUT->pu8Buffer = pstcUsbHostIntern->pu8Setup; + pstcUsbHostIntern->Ep0OUT->pu8BufferPos = pstcUsbHostIntern->pu8Setup; + pstcUsbHostIntern->Ep0OUT->u32BufferSize = 8; + pstcUsbHostIntern->Ep0IN->CompletionHandler = UsbHost_SetupComplete; + pstcUsbHostIntern->Ep0OUT->CompletionHandler = UsbHost_SetupComplete; + + + //pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + //pstcUsbHostIntern->Ep0OUT->u8Status |= USBHOST_ENDPOINTSTATUS_INUSE; + //pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + pstcUsbHostIntern->Ep0OUT->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + //pstcUsbHostIntern->u8SetupDelay = 3; + //pstcUsbHostIntern->ActiveEndpoint=pstcUsbHostIntern->Ep0OUT; + //UsbHost_TransferData(Ep0OUT,u8Setup,8,SetupComplete); + + // synchronous token (sent after next SOF) + + //pstcUsbHostIntern->Ep0OUT->u8LastToken = CREATE_TOKEN(pstcUsbHostIntern->Ep0OUT->bToggle,HTOKEN_SETUP,pstcUsbHostIntern->Ep0OUT->u8Address & 0x0F); + //pstcUsbHostIntern->ActiveEndpoint = pstcUsbHostIntern->Ep0OUT; + //pstcUsbHostIntern->u8LastToken = pstcUsbHostIntern->Ep0OUT->u8LastToken; + //pstcUsbHostIntern->u8SyncToken = pstcUsbHostIntern->Ep0OUT->u8LastToken; + + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; +} + +/** + ****************************************************************************** + ** \brief Stall completion routine + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pu8Buffer data returned + ** + ** \param u32Size size of data + ** + ******************************************************************************/ +static void StallCompletionEp0(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32Size) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + USBDBG("Resending last Setup\n"); + UsbHost_SetupRequest(pstcUsb, &pstcUsbHostIntern->stcLastSetupBeforeStall, pstcUsbHostIntern->SetupCompletionHandler); + +} + +/** + ****************************************************************************** + ** \brief Stall completion routine + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +static void UsbHost_SetupComplete(stc_usbn_t* pstcUsb) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + if (pstcUsbHostIntern->SetupCompletionHandler != 0) + { + pstcUsbHostIntern->SetupCompletionHandler(pstcUsb,(pstcUsbHostIntern->Ep0IN->pu8Buffer),(pstcUsbHostIntern->Ep0IN->u32DataSize)); + } +} + +/** + ****************************************************************************** + ** \brief Connection Callback Routine + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +void ConnectionCallback(stc_usbn_t* pstcUsb) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + if (pstcUsbHostIntern->u32ConTimeout == 0) + { + if ((pstcUsb->HIRQ_f.URIRQ == 0) || (pstcUsbHostIntern->bBusResetSend == FALSE)) + { + pstcUsb->UDCC_f.RST = 1; + if (pstcUsb->HSTATE_f.TMODE == 1) /* TMODE : Full-Speed */ + { + USBDBG("Full-Speed Device\n"); + pstcUsb->HSTATE_f.ALIVE = 0; + pstcUsb->HSTATE_f.CLKSEL = 1; + pstcUsbHostIntern->bFullSpeed = TRUE; + } + else /* Low-Speed */ + { + USBDBG("Low-Speed Device\n"); + pstcUsbHostIntern->bFullSpeed = FALSE; + pstcUsb->HSTATE_f.ALIVE = 1; + pstcUsb->HSTATE_f.CLKSEL = 0; + } + pstcUsb->UDCC_f.RST = 0; + } + USBDBG("\n### Device Connection - wait...\n"); + if (pstcUsb->HSTATE_f.TMODE == 1) /* TMODE : Full-Speed */ + { + pstcUsbHostIntern->u32ConTimeout = pstcUsbHostIntern->u32ConnectionDelay; + } + else + { + pstcUsbHostIntern->u32ConTimeout = pstcUsbHostIntern->u32ConnectionDelay; + } + return; + } + if (pstcUsbHostIntern->u32ConTimeout > 1) + { + pstcUsbHostIntern->u32ConTimeout = pstcUsbHostIntern->u32ConTimeout - 1; + return; + } + USBDBG("\n### Device Connection...\n"); + pstcUsb->HIRQ_f.CNNIRQ = 0; + if ((pstcUsb->HIRQ_f.URIRQ == 0) || (pstcUsbHostIntern->bBusResetSend == FALSE)) + { + pstcUsbHostIntern->bBusResetSend = TRUE; + if (pstcUsb->HSTATE_f.CSTAT == 1) + { + USBDBG(">> Exec Bus Reset...\n"); + + pstcUsb->HADR = 0; // Device Address = 0 + + pstcUsb->EP1S_f.BFINI = 1; + pstcUsb->EP1S_f.BFINI = 0; + pstcUsb->EP2S_f.BFINI = 1; + pstcUsb->EP2S_f.BFINI = 0; + + pstcUsb->HCNT_f.URST = 1; // initiate bus reset + } + } + else + { + USBDBG(" |->Bus Resetted\n"); + pstcUsb->HIRQ_f.URIRQ = 0; + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + UsbHost_AddHostEndpoint(pstcUsb,&pstcUsbHostIntern->Ep0IN ,USBHOST_EPADDR0_IN,20,0,0); + UsbHost_AddHostEndpoint(pstcUsb,&pstcUsbHostIntern->Ep0OUT,USBHOST_EPADDR0_OUT,20,0,0); + pstcUsbHostIntern->Ep0IN->u32BufferSize = 255; + pstcUsbHostIntern->Ep0OUT->u32BufferSize = 255; + + pstcUsbHostIntern->Ep0IN->pu8Buffer = pstcUsbHostIntern->pu8GlobalBuffer; + pstcUsbHostIntern->Ep0OUT->pu8Buffer = pstcUsbHostIntern->pu8GlobalBuffer; + + USBDBG(">> Starting SOF\n"); + pstcUsb->HFRAME = 0; + pstcUsb->HEOF = 0x2c9; // Set the time where token are allowed in a frame + + pstcUsb->HCNT_f.SOFSTEP = 1; + + pstcUsbHostIntern->Ep0OUT->bToggle = FALSE; + + + pstcUsb->HTOKEN = CREATE_TOKEN(0,HTOKEN_SOF,0); + /*SET_TOKEN_NOW(,HTOKEN_SOF);*/ + + pstcUsbHostIntern->u8EnumerationCounter = 0; + Usb_AddTimeOut(pstcUsb, EnumerationStateMachine,500); + } +} + +/** + ****************************************************************************** + ** \brief Clear all endpoints + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +void UsbHost_ClearAllEndpoints(stc_usbn_t* pstcUsb) +{ + uint8_t i; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + pstcUsbHostIntern->u8EndpointListEnd = 0; + pstcUsbHostIntern->u8CurrentEndpointPosition = 2; + for(i=2;iastcHostEndpoints[i],0,sizeof(pstcUsbHostIntern->astcHostEndpoints[i])); + } + pstcUsbHostIntern->astcHostEndpoints[0].bToggle = 0; + pstcUsbHostIntern->astcHostEndpoints[1].bToggle = 0; +} + +/** + ****************************************************************************** + ** \brief Disconnection Callback Routine + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +void UsbHost_DisconnectionCallback(stc_usbn_t* pstcUsb) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + USBDBG("\n### Device Disconnection...\n"); + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_IDLE; + pstcUsbHostIntern->u32BusResetTimeout = 0; + pstcUsbHostIntern->u32ConnectionDelay = USBHOST_CONNECTION_DELAY; + pstcUsbHostIntern->u32ConTimeout = 0; + pstcUsbHostIntern->bBusResetSend = FALSE; + UsbClassSupervisor_Deinit(pstcUsb); + UsbHost_ClearAllEndpoints(pstcUsb); + pstcUsbHostIntern->bSofToken = FALSE; + pstcUsbHostIntern->bSchedulerLock = FALSE; + pstcUsbHostIntern->bBusResetSend = FALSE; + pstcUsbHostIntern->u8DeviceAddress = 0; + pstcUsbHostIntern->u8EnumerationCounter = 0; + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + pstcUsbHostIntern->u8LastToken = 0; + pstcUsbHostIntern->ActiveEndpoint = NULL; + memset(&pstcUsbHostIntern->stcLastSetup,0,sizeof(pstcUsbHostIntern->stcLastSetup)); + memset(&pstcUsbHostIntern->stcLastSetupBeforeStall,0,sizeof(pstcUsbHostIntern->stcLastSetupBeforeStall)); + memset(pstcUsbHostIntern->pu8SetupData,0,8); + pstcUsb->HIRQ_f.DIRQ = 0; // be sure disconnection IRQ is released (should be already done in usb.c) + pstcUsb->HIRQ_f.CNNIRQ = 0; // wanted here to be sure connection IRQ is not fired +} + + +/** + ****************************************************************************** + ** \brief Bus Reset Callback Routine + ** + ** \param pstcUsb Pointer to USB instance + ** + ******************************************************************************/ +void UsbHost_BusresetCallback(stc_usbn_t* pstcUsb) +{ + +} + +/** + ****************************************************************************** + ** \brief Host Init Callback Routine + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcConfig USB Config + ** + ******************************************************************************/ +void UsbHost_InitCallback(stc_usbn_t* pstcUsb,struct stc_usb_config* pstcConfig) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + pstcUsbHostIntern->bSofToken = FALSE; + pstcUsbHostIntern->u32ConTimeout = 0; + pstcUsbHostIntern->u32BusResetTimeout = 0; + pstcUsbHostIntern->u8CurrentEndpointPosition = 2; + pstcUsbHostIntern->u8EndpointListEnd = 0; + pstcUsbHostIntern->bSchedulerLock = FALSE; + pstcUsbHostIntern->bBusResetSend = FALSE; + //pstcUsbHostIntern->SetupCompletionHandler = 0; + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_IDLE; + pstcUsbHostIntern->u8DeviceAddress = 0; + pstcUsbHostIntern->u8EnumerationCounter = 0; + pstcConfig->pfnCnnirqCallback = ConnectionCallback; + pstcConfig->pfnDirqCallback = UsbHost_DisconnectionCallback; + pstcConfig->pfnCmpirqCallback = UsbHost_CompletionCallback; + pstcConfig->pfnSofCallback = UsbHost_SofCallback; + pstcUsbHostIntern->u32ConnectionDelay = USBHOST_CONNECTION_DELAY; + pstcUsbHostIntern->pstcUsbHalEndpointIN = Usb_GetEndpointPtr(pstcUsb,0x81); + pstcUsbHostIntern->pstcUsbHalEndpointOUT = Usb_GetEndpointPtr(pstcUsb,0x02); + +} + +/** + ****************************************************************************** + ** \brief Transfer OUT token data + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pu8Buffer Source buffer + ** + ** \param u16Size data size + ** + ** \param u16FifoSize FIFO data size + ** + ******************************************************************************/ +void UsbHost_TransferDataToFifo(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint16_t u16Size, uint16_t u16FifoSize) +{ + volatile uint32_t u32Timeout; + boolean_t Odd = u16Size & 1; + //stc_usbhost_intern_data_t* pstcUsbHostIntern; + //pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + USBDBGVAL8("TX: ",u16Size); + USBDBGVAL32("#",pu8Buffer); + u32Timeout = 10000; + while((pstcUsb->EP2S_f.BUSY == 1) && (u32Timeout > 0)) + { + u32Timeout--; + } + pstcUsb->EP2S_f.BFINI=1; + pstcUsb->EP2S_f.BFINI=0; + pstcUsb->EP2S = (pstcUsb->EP2S & (~0x1F)) | u16FifoSize; + + u16Size = u16Size / 2; // transfer 16 Bit words; + while(u16Size--) + { + //EP2DT = *(uint16_t*)pu8Buffer; + pstcUsb->EP2DTL = *pu8Buffer++; + pstcUsb->EP2DTH = *pu8Buffer++; + //pu8Buffer += 2; + } + if(Odd == TRUE) { + pstcUsb->EP2DTL= *(uint8_t*)pu8Buffer; // transfer the first or last byte + } + pstcUsb->EP2S_f.DRQ = 0; // now the OUT FIFO is valid for the next transfer +} + +/** + ****************************************************************************** + ** \brief Transfer IN token data + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pu8Buffer Destination buffer + ** + ** \param u32MaxBufferSize Maximal data to receive, all other data will be cleared + ** + ** \return received size + ** + ******************************************************************************/ +uint16_t UsbHost_TransferFifoToBuffer(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32MaxBufferSize) +{ + uint16_t u16Size = 0; + uint16_t u16ReceivedSize; + volatile uint32_t u32Timeout; + volatile uint8_t u8Dummy = 0; + u32Timeout = 10000; + while((pstcUsb->EP1S_f.BUSY == 1) && (u32Timeout > 0)) + { + u32Timeout--; + } + //stc_usbhost_intern_data_t* pstcUsbHostIntern; + //pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + u16Size = (uint16_t)(pstcUsb->EP1S & 0x00FF); + u16ReceivedSize = u16Size; + USBDBGVAL16("RX: ",u16Size); + if (u16ReceivedSize > u32MaxBufferSize) + { + USBDBGVAL16("WOW... more data than expected, new data size: ",u32MaxBufferSize); + u16Size = u32MaxBufferSize; + u16ReceivedSize = u16Size; + } + USBDBGVAL32("#",pu8Buffer); + u16Size = u16Size / 2; // transfer 16 Bit words; + while(u16Size--) + { + //*(uint16_t*)pu8Buffer = EP1DT; + if (pu8Buffer == 0) + { + u8Dummy = pstcUsb->EP1DTL; + u8Dummy = pstcUsb->EP1DTH; + } + else + { + *pu8Buffer++ = pstcUsb->EP1DTL; + *pu8Buffer++ = pstcUsb->EP1DTH; + } + //pu8Buffer += 2; + } + if(u16ReceivedSize & 1 == TRUE) { + if (pu8Buffer == 0) + { + u8Dummy = pstcUsb->EP1DTL; // transfer the first or last byte + } + else + { + *(uint8_t*)pu8Buffer = pstcUsb->EP1DTL; // transfer the first or last byte + } + } + pstcUsb->EP1S_f.DRQ = 0; // now the IN FIFO is valid for the next transfer + pstcUsb->EP1S_f.BFINI=1; + pstcUsb->EP1S_f.BFINI=0; + return u16ReceivedSize; +} + +/** + ****************************************************************************** + ** \brief Transfer data via endpoint + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param Handler Endpoint handle + ** + ** \param pu8Buffer buffer + ** + ** \param u32BufferSize size of data to be transferred + ** + ** \param CompletionHandler callback handle + ** + ******************************************************************************/ +void UsbHost_TransferData(stc_usbn_t* pstcUsb, stc_host_endpoint_t* Handler,uint8_t* pu8Buffer, uint32_t u32BufferSize, void (* CompletionHandler)(stc_usbn_t* pstcUsb)) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + volatile boolean_t bOldSchedulerLockState; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + bOldSchedulerLockState = pstcUsbHostIntern->bSchedulerLock; + pstcUsbHostIntern->bSchedulerLock = TRUE; + DBGPROCENTER("UsbHost_TransferData"); + + (Handler->u8Status) &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + if ((Handler->u8Interval) == 0) + { + (Handler->u8Status) |= USBHOST_ENDPOINTSTATUS_INUSE; + } + Handler->bAbortTransfer = FALSE; + USBHOST_RESETENDPOINTBUFFER(Handler,pu8Buffer,u32BufferSize); + + (Handler->CompletionHandler) = CompletionHandler; + (Handler->u8Status) &= ~USBHOST_ENDPOINTSTATUS_INUSE; + + USBDBGVAL32("DATASIZE: ",Handler->u32DataSize); + + if ((Handler->u8Interval) == 0) + { + (Handler->u8Status) |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + + DBGPROCRETURN("UsbHost_TransferData"); + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + + //UsbHost_Tick(); + //Handler->u8Status |= USBHOST_ENDPOINTSTATUS_DATA; +} + +/** + ****************************************************************************** + ** \brief Write host relevant initializations into pstcUsbConfig + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcUsbConfig Write host relevant initializations into pstcUsbConfig + ** + ******************************************************************************/ +void UsbHost_Init(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcUsbConfig) +{ + //stc_usbhost_intern_data_t* pstcUsbHostIntern; + //pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + + pstcUsbConfig->enMode |= UsbHostEnabled; + pstcUsbConfig->pfnHostInit = UsbHost_InitCallback; + + +} + +/** + ****************************************************************************** + ** \brief Get status of current enumerated device + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return USB device status + ** #USBHOST_DEVICE_IDLE = 1, + ** #USBHOST_DEVICE_ADDRESSING = 2, + ** #USBHOST_DEVICE_ADDRESSED = 3, + ** #USBHOST_DEVICE_ENUMERATED = 4, + ** #USBHOST_DEVICE_CONFIGURATING = 5, + ** #USBHOST_DEVICE_CONFIGURED = 6 + ** + ******************************************************************************/ +uint8_t UsbHost_GetDeviceStatus(stc_usbn_t* pstcUsb) +{ + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + return pstcUsbHostIntern->u8DeviceStatus; +} + + +/** + ****************************************************************************** + ** \brief Set configuration + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param u8Configuration number of configuration + ** + ******************************************************************************/ +void UsbHost_SetConfigurationDescriptor(stc_usbn_t* pstcUsb, uint8_t u8Configuration) +{ + stc_usb_request_t stcSetup = {0x00,0x09,0x00,0x00,0x00}; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + stcSetup.wValue |= u8Configuration; + USBDBGVAL8("Setting Configuration: ",u8Configuration); + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_CONFIGURATING; + UsbHost_SetupRequest(pstcUsb,&stcSetup,0); +} + +/** + ****************************************************************************** + ** \brief Get endpoint descriptor from buffer of configuration + ** + ** \param pu8Buffer Buffer + ** + ** \param u16Size Size of buffer + ** + ** \param u8InterfaceNumber Interface number + ** + ** \param u8EndpointNumber Number of endpoint + ** + ** \return NULL, if endpoint was not found in the configuration, else pointer to endpoint descriptor (as buffer) + ** + ******************************************************************************/ +uint8_t* UsbHost_GetUsbEndpointDescriptor(uint8_t* pu8Buffer, uint16_t u16Size, uint8_t u8InterfaceNumber, uint8_t u8EndpointNumber) +{ + uint16_t u16Position = 0; + uint8_t u8DescriptorLength = 0; + uint8_t u8DescriptorType = 0; + uint8_t u8CurrentInterface = 0xFF; + uint8_t u8CurrentEndpoint = 0; + uint16_t u16wTotalLength; + + + if (pu8Buffer[1] != USB_CONFIGURATION_DESCRIPTOR_TYPE) + { + return 0; + } + + u16wTotalLength = (uint16_t)pu8Buffer[2] + (uint16_t)(pu8Buffer[3] << 8); + if (u16Size < u16wTotalLength) + { + u16wTotalLength = u16Size; + } + + while(u16Position < u16wTotalLength) + { + u8DescriptorLength = pu8Buffer[u16Position]; + u8DescriptorType = pu8Buffer[u16Position + 1]; + if (u8DescriptorType == USB_INTERFACE_DESCRIPTOR_TYPE) + { + u8CurrentEndpoint = 0; + u8CurrentInterface = pu8Buffer[u16Position + 2]; + } + if (u8DescriptorType == USB_ENDPOINT_DESCRIPTOR_TYPE) + { + u8CurrentEndpoint = u8CurrentEndpoint + 1; + } + if (((u8CurrentEndpoint == u8EndpointNumber) || (u8EndpointNumber == 0)) && (u8InterfaceNumber == u8CurrentInterface)) + { + return (uint8_t*)(pu8Buffer + u16Position); + } + u16Position += u8DescriptorLength; + } + return 0; +} + + +typedef enum en_usbhost_scheduler_event +{ + UsbHostSchedulerEventUnknown = 0, + UsbHostSchedulerEventSof = 1, + UsbHostSchedulerEventCompletion = 2, + UsbHostSchedulerEventTick = 3, +} en_usbhost_scheduler_event_t; + +void UsbHost_SchedulerInitiateEndpoint(stc_usbn_t* pstcUsb, stc_usbhost_intern_data_t* pstcUsbHostIntern, stc_host_endpoint_t* pstcEndpoint) +{ + uint32_t u32DataSize = 0; + uint8_t u8NextToken = 0; + volatile uint32_t u32Timeout; + DBGPROCENTER("UsbHost_SchedulerInitiateEndpoint"); + USBDBGVAL8("Init TKN, EP: ", pstcEndpoint->u8Address); + pstcEndpoint->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + pstcEndpoint->u8Status |= USBHOST_ENDPOINTSTATUS_INUSE; + pstcEndpoint->u8IntervalCount = (pstcEndpoint->u8Interval); + pstcUsbHostIntern->u32WaitForCompletionTimeout = 10; + if (((pstcEndpoint->u8Address) & 0x0F) == 0) + { + pstcUsbHostIntern->u32WaitForCompletionTimeout = 10; + } + if ((pstcEndpoint->u8Address) & 0x80) + { + USBDBG("Type IN\n"); + if (pstcEndpoint->bIsochronous == TRUE) + { + u8NextToken = CREATE_TOKEN(FALSE,HTOKEN_ISO_IN,((pstcEndpoint->u8Address) & 0x0F)); + } + else + { + u8NextToken = CREATE_TOKEN(pstcEndpoint->bToggle,HTOKEN_IN,((pstcEndpoint->u8Address) & 0x0F)); + } + + } + else + { + //u32DataSize = (pstcEndpoint->u32DataSize); + u32DataSize = (pstcEndpoint->u32DataSize); + USBDBG("Type OUT\n"); + USBDBGVAL32("Data Size:", u32DataSize); + u32DataSize -= (uint32_t)((pstcEndpoint->pu8BufferPos) - (pstcEndpoint->pu8Buffer)); + USBDBGVAL32("Data Size Left:", u32DataSize); + if (u32DataSize > (pstcEndpoint->u16FifoSize)) + { + u32DataSize = pstcEndpoint->u16FifoSize; + USBDBGVAL32("Resizing new:", u32DataSize); + } + if (u32DataSize > 0) + { + pstcEndpoint->pu8BufferPosNextPackage += u32DataSize; + UsbHost_TransferDataToFifo(pstcUsb,pstcEndpoint->pu8BufferPos, (uint16_t)u32DataSize, pstcEndpoint->u16FifoSize); + u8NextToken = CREATE_TOKEN(pstcEndpoint->bToggle,HTOKEN_OUT,((pstcEndpoint->u8Address) & 0x0F)); + + } + else + { + USBDBG("Sending 0 byte\n"); + UsbHost_TransferDataToFifo(pstcUsb,pstcEndpoint->pu8BufferPos, (uint16_t)u32DataSize, pstcEndpoint->u16FifoSize); + u8NextToken = CREATE_TOKEN(pstcEndpoint->bToggle,HTOKEN_OUT,((pstcEndpoint->u8Address) & 0x0F)); + } + } + + if (pstcEndpoint->u8Stage == USBHOST_STAGE_SETUP) + { + u8NextToken = 0x10; + } + + USBDBGVAL8("",u8NextToken); + USBDBGVAL8("DATA",(u8NextToken & 0x80) > 0); + pstcUsbHostIntern->bSofToken = FALSE; + pstcUsbHostIntern->u8LastToken = u8NextToken; + pstcUsbHostIntern->ActiveEndpoint = pstcEndpoint; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpoint) || (pstcUsbHostIntern->Ep0IN == pstcEndpoint)) + { + pstcUsbHostIntern->Ep0OUT->u8LastToken = u8NextToken; + pstcUsbHostIntern->Ep0IN->u8LastToken = u8NextToken; + } + pstcEndpoint->u8LastToken = u8NextToken; + pstcUsbHostIntern->u8SchedulerState = USBHOST_SCHEDULER_BUSY; + pstcEndpoint->u8Status |= USBHOST_ENDPOINTSTATUS_INUSE; + u32Timeout = 10000; + while(((pstcUsb->EP1S_f.BUSY == 1) || (pstcUsb->EP2S_f.BUSY == 1)) && (u32Timeout > 0)) + { + u32Timeout--; + } + pstcUsb->HTOKEN = u8NextToken; + DBGPROCRETURN("UsbHost_SchedulerInitiateEndpoint"); +} + +void UsbHost_Scheduler(stc_usbn_t* pstcUsb, en_usbhost_scheduler_event_t enEvent) +{ + uint8_t i; + static volatile boolean_t bSchedulerIsRunning = FALSE; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + if (bSchedulerIsRunning == TRUE) return; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + + if (enEvent == UsbHostSchedulerEventCompletion) + { + } + + if (enEvent == UsbHostSchedulerEventSof) + { + if (pstcUsbHostIntern->u32WaitForCompletionTimeout > 0) + { + pstcUsbHostIntern->u32WaitForCompletionTimeout--; + } + + for(i = 0;i <= pstcUsbHostIntern->u8EndpointListEnd;i++) + { + if ((pstcUsbHostIntern->astcHostEndpoints[i].u8Interval > 0) && (pstcUsbHostIntern->astcHostEndpoints[i].u8IntervalCount > 0)) + { + pstcUsbHostIntern->astcHostEndpoints[i].u8IntervalCount--; + } + } + } + + if (pstcUsbHostIntern->bSchedulerLock == TRUE) + { + bSchedulerIsRunning = FALSE; + return; + } + + if (pstcUsbHostIntern->u32WaitForCompletionTimeout > 0) + { + bSchedulerIsRunning = FALSE; + return; + } + + if ((pstcUsbHostIntern->Ep0IN->bAbortTransfer == TRUE) || (pstcUsbHostIntern->Ep0OUT->bAbortTransfer == TRUE)) + { + USBDBG("-> EP0 CANCELED\n"); + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0IN->bAbortTransfer = FALSE; + pstcUsbHostIntern->Ep0OUT->bAbortTransfer = FALSE; + pstcUsbHostIntern->Ep0IN->u8Stage = 0; + pstcUsbHostIntern->Ep0OUT->u8Stage = 0; + pstcUsbHostIntern->u32ConTimeout = 0; + + } + + // Process control transfers + if (((pstcUsbHostIntern->Ep0IN->u8Status) & USBHOST_ENDPOINTSTATUS_INITIATE) > 0) + { + UsbHost_SchedulerInitiateEndpoint(pstcUsb,pstcUsbHostIntern,pstcUsbHostIntern->Ep0IN); + bSchedulerIsRunning = FALSE; + return; + } + + if (((pstcUsbHostIntern->Ep0OUT->u8Status) & USBHOST_ENDPOINTSTATUS_INITIATE) > 0) + { + UsbHost_SchedulerInitiateEndpoint(pstcUsb,pstcUsbHostIntern,pstcUsbHostIntern->Ep0OUT); + bSchedulerIsRunning = FALSE; + return; + } + + if (pstcUsbHostIntern->u8DeviceStatus != USBHOST_DEVICE_CONFIGURED) + { + bSchedulerIsRunning = FALSE; + return; + } + + // Process interrupt transfers + for(i = 0;i <= pstcUsbHostIntern->u8EndpointListEnd;i++) + { + pstcUsbHostIntern->u8CurrentEndpointPosition++; + if (pstcUsbHostIntern->u8CurrentEndpointPosition > pstcUsbHostIntern->u8EndpointListEnd) + { + pstcUsbHostIntern->u8CurrentEndpointPosition = 0; + } + if ((pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].u8Interval > 0) && (pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].u8IntervalCount == 0)) + { + // Init Interrupt Transfer + pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].pu8BufferPos = (pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].pu8Buffer); + pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].pu8BufferPosNextPackage = (pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].pu8Buffer); + UsbHost_SchedulerInitiateEndpoint(pstcUsb,pstcUsbHostIntern,&(pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition])); + bSchedulerIsRunning = FALSE; + return; + } + } + + // Process other transfers than interrupt + for(i = 0;i <= pstcUsbHostIntern->u8EndpointListEnd;i++) + { + pstcUsbHostIntern->u8CurrentEndpointPosition++; + if (pstcUsbHostIntern->u8CurrentEndpointPosition > pstcUsbHostIntern->u8EndpointListEnd) + { + pstcUsbHostIntern->u8CurrentEndpointPosition = 0; + } + if (((pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition].u8Status) & USBHOST_ENDPOINTSTATUS_INITIATE) > 0) + { + // Init Transfer + UsbHost_SchedulerInitiateEndpoint(pstcUsb,pstcUsbHostIntern,&(pstcUsbHostIntern->astcHostEndpoints[pstcUsbHostIntern->u8CurrentEndpointPosition])); + bSchedulerIsRunning = FALSE; + return; + } + } +} + +void UsbHost_CompletionCallback(stc_usbn_t* pstcUsb) +{ + uint32_t tmp; + uint32_t u32DataSize = 0; + volatile boolean_t bOldSchedulerLockState; + stc_host_endpoint_t* pstcEndpointHandle = 0; + stc_usbhost_intern_data_t* pstcUsbHostIntern; + pstcUsbHostIntern = UsbHostGetInternDataPtr(pstcUsb); + pstcEndpointHandle = pstcUsbHostIntern->ActiveEndpoint; + DBGPROCENTER("UsbHost_CompletionCallback"); + bOldSchedulerLockState = pstcUsbHostIntern->bSchedulerLock; + pstcUsbHostIntern->bSchedulerLock = TRUE; + + + USBDBGVAL8("EP: ",pstcEndpointHandle->u8Address); + + USBDBGVAL8("EP: ",pstcEndpointHandle->u8Address); + + if (pstcEndpointHandle == 0) + { + USBDBG("WARNING: pstcEndpointHandle == 0\n"); + USBDBG("\n< UsbHost_CompletionCallback\n"); + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + return; + } + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + + if (pstcEndpointHandle->bAbortTransfer == TRUE) + { + USBDBG("-> CANCELED\n"); + pstcEndpointHandle->u32DataSize = 0; + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpointHandle) || (pstcUsbHostIntern->Ep0IN == pstcEndpointHandle)) + { + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + } + pstcEndpointHandle->bAbortTransfer = FALSE; + pstcUsbHostIntern->ActiveEndpoint = 0; + DBGPROCRETURN("UsbHost_CompletionCallback"); + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + return; + } + USBDBGVAL8("HERR: ",pstcUsb->HERR); + USBDBGVAL8("TKN: ",(pstcEndpointHandle->u8LastToken)); + if ((pstcUsb->HERR & 0x03) == HERR_ACK) + { + USBDBG("ACK\n"); + + if (pstcEndpointHandle->bToggle == TRUE) + { + USBDBG("TGL 1 -> 0\n"); + pstcEndpointHandle->bToggle = FALSE; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpointHandle) || (pstcUsbHostIntern->Ep0IN == pstcEndpointHandle)) + { + pstcUsbHostIntern->Ep0OUT->bToggle = FALSE; + pstcUsbHostIntern->Ep0IN->bToggle = FALSE; + } + } + else + { + USBDBG("TGL 0 -> 1\n"); + pstcEndpointHandle->bToggle = TRUE; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpointHandle) || (pstcUsbHostIntern->Ep0IN == pstcEndpointHandle)) + { + pstcUsbHostIntern->Ep0OUT->bToggle = TRUE; + pstcUsbHostIntern->Ep0IN->bToggle = TRUE; + } + } + + + if (((pstcEndpointHandle->u8Address) & 0x0F) == 0) // handler == endpoint 0? + { + if (((pstcEndpointHandle->u8LastToken) & 0x70) == HTOKEN_SETUP) // type == SETUP token? + { + USBDBG("SETUP\n"); + if (((pstcUsbHostIntern->stcLastSetup.bmRequestType) & 0x80) || (pstcUsbHostIntern->stcLastSetup.wLength == 0)) + { + USBDBG("TYPE IN\n"); + pstcEndpointHandle = pstcUsbHostIntern->Ep0IN; + } + else + { + USBDBG("TYPE OUT\n"); + pstcEndpointHandle = pstcUsbHostIntern->Ep0OUT; + } + pstcUsbHostIntern->Ep0IN->bToggle = TRUE; + pstcUsbHostIntern->Ep0OUT->bToggle = TRUE; + pstcEndpointHandle->pu8BufferPos = (pstcEndpointHandle->pu8Buffer); + pstcEndpointHandle->u32DataSize = 0; + if ((pstcUsbHostIntern->stcLastSetup.wLength == 0)) // || ((stcLastSetup.wLength <= (Ep0IN->u16FifoSize)) && (Handler == Ep0IN))) + { + USBDBG("NO DATA -> ENTERING STATUS STAGE\n"); + pstcUsbHostIntern->Ep0OUT->u8Stage = USBHOST_STAGE_STATUS; + pstcUsbHostIntern->Ep0IN->u8Stage = USBHOST_STAGE_STATUS; + } + else + { + USBDBG("DATA -> ENTERING DATA STAGE\n"); + pstcUsbHostIntern->Ep0OUT->u8Stage = USBHOST_STAGE_DATA; + pstcUsbHostIntern->Ep0IN->u8Stage = USBHOST_STAGE_DATA; + } + pstcEndpointHandle->u32DataSize = pstcUsbHostIntern->stcLastSetup.wLength; + if (((pstcUsbHostIntern->stcLastSetup.bmRequestType) & 0x80) || (pstcUsbHostIntern->stcLastSetup.wLength == 0)) + { + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + else + { + pstcEndpointHandle->pu8BufferPosNextPackage = pstcUsbHostIntern->pu8SetupData; + pstcEndpointHandle->pu8BufferPos = pstcUsbHostIntern->pu8SetupData; + pstcEndpointHandle->pu8Buffer = pstcUsbHostIntern->pu8SetupData; + pstcEndpointHandle->u32BufferSize = pstcUsbHostIntern->stcLastSetup.wLength; + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + DBGPROCRETURN("UsbHost_CompletionCallback"); + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + return; + } // endif (((pstcEndpointHandle->u8LastToken) & 0x70) == HTOKEN_SETUP) --> type == SETUP token? + else + { + if (pstcUsbHostIntern->u8DeviceStatus == USBHOST_DEVICE_ADDRESSING) + { + pstcUsbHostIntern->u8EnumerationCounter = 0; + pstcUsb->HADR = pstcUsbHostIntern->u8DeviceAddress; + USBDBG("Enumeration Process:\n"); + USBDBGVAL8(" ->Addressed: ",pstcUsbHostIntern->u8DeviceAddress); + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_ADDRESSED; + //UsbClassSupervisor_Init(pstcUsb); + } + if (pstcUsbHostIntern->u8DeviceStatus == USBHOST_DEVICE_CONFIGURATING) + { + USBDBG("-->Configured\n"); + pstcUsbHostIntern->u8DeviceStatus = USBHOST_DEVICE_CONFIGURED; + } + } + } // endif (((pstcEndpointHandle->u8Address) & 0x0F) == 0) --> handler == endpoint 0? + + if ((((pstcEndpointHandle->u8LastToken) & 0x70) != HTOKEN_SETUP)) + { + USBDBG("NO SETUP\n"); + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + if ((((pstcEndpointHandle->u8LastToken) & 0x70) == HTOKEN_IN) || (((pstcEndpointHandle->u8LastToken) & 0x70) == HTOKEN_ISO_IN)) + { + USBDBG("IN TKN\n"); + tmp = (pstcEndpointHandle->u32DataSize) - ((uint32_t)((uint32_t)(pstcEndpointHandle->pu8BufferPos) - (uint32_t)(pstcEndpointHandle->pu8Buffer))); + USBDBGVAL32("Max free in buffer: ",(pstcEndpointHandle->u32DataSize)); + u32DataSize = (uint32_t)((uint16_t)UsbHost_TransferFifoToBuffer(pstcUsb,pstcEndpointHandle->pu8BufferPos,tmp)); + (pstcEndpointHandle->pu8BufferPos) = (pstcEndpointHandle->pu8BufferPos) + u32DataSize; + tmp = ((uint32_t)((uint32_t)(pstcEndpointHandle->pu8BufferPos) - (uint32_t)(pstcEndpointHandle->pu8Buffer))); + USBDBGVAL8("EP#",(uint32_t)(pstcEndpointHandle->u8Address)); + USBDBGVAL32("#",(uint32_t)(pstcEndpointHandle->pu8Buffer)); + USBDBGVAL32("Received: ", u32DataSize); + USBDBGVAL32("New Size: ", tmp); + USBDBGVAL32("Max Size: ",(pstcEndpointHandle->u32DataSize)); + if (((u32DataSize == (pstcEndpointHandle->u16FifoSize)) && ((pstcEndpointHandle->u32DataSize) == 0)) || ((u32DataSize == (pstcEndpointHandle->u16FifoSize) && (pstcEndpointHandle->u32DataSize) > 0) && ((pstcEndpointHandle->u32DataSize) > tmp))) + { + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + else + { + pstcEndpointHandle->u32DataSize = (uint32_t)((uint32_t)(pstcEndpointHandle->pu8BufferPos) - (uint32_t)(pstcEndpointHandle->pu8Buffer)); + USBDBGVAL32("RX-Size: ", (pstcEndpointHandle->u32DataSize)); + pstcEndpointHandle->pu8BufferPos = (pstcEndpointHandle->pu8Buffer); + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_DATA; + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpointHandle) || (pstcUsbHostIntern->Ep0IN == pstcEndpointHandle)) + { + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + } + if ((((pstcEndpointHandle->u8Address) & 0x0F) == 0) && ((pstcEndpointHandle->u8Stage) == USBHOST_STAGE_DATA)) + { + pstcUsbHostIntern->Ep0IN->u8Stage = USBHOST_STAGE_STATUS; + pstcUsbHostIntern->Ep0OUT->u8Stage = USBHOST_STAGE_STATUS; + pstcUsbHostIntern->Ep0OUT->bToggle = TRUE; + pstcUsbHostIntern->Ep0IN->bToggle = TRUE; + pstcUsbHostIntern->Ep0OUT->u32DataSize = 0; + pstcUsbHostIntern->Ep0OUT->pu8BufferPos = (pstcUsbHostIntern->Ep0OUT->pu8Buffer); + pstcUsbHostIntern->Ep0OUT->pu8BufferPosNextPackage = (pstcUsbHostIntern->Ep0OUT->pu8BufferPos); + pstcUsbHostIntern->Ep0OUT->CompletionHandler = pstcUsbHostIntern->Ep0IN->CompletionHandler; + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + pstcUsbHostIntern->Ep0OUT->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + else + { + USBDBG("TRANS COMPLETE\n"); + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + if ((pstcEndpointHandle->CompletionHandler) != 0) + { + USBDBG("Exec(IN)\n"); + pstcEndpointHandle->CompletionHandler(pstcUsb); + } + pstcUsbHostIntern->ActiveEndpoint = 0; + } + } + + } + if ((((pstcEndpointHandle->u8LastToken) & 0x70) == HTOKEN_OUT) || (((pstcEndpointHandle->u8LastToken) & 0x70) == HTOKEN_ISO_OUT)) + { + pstcEndpointHandle->pu8BufferPos = (pstcEndpointHandle->pu8BufferPosNextPackage); + + USBDBG("OUT TKN\n"); + USBDBGVAL8("EP#",(uint32_t)(pstcEndpointHandle->u8Address)); + USBDBGVAL32("#",(uint32_t)(pstcEndpointHandle->pu8Buffer)); + USBDBGVAL32("Transferred: ",(uint32_t)((pstcEndpointHandle->pu8BufferPos) - (pstcEndpointHandle->pu8Buffer))); + u32DataSize = (pstcEndpointHandle->u32DataSize); + + USBDBGVAL32("Datalen old: ",u32DataSize); + + u32DataSize -= (uint32_t)((pstcEndpointHandle->pu8BufferPos) - (pstcEndpointHandle->pu8Buffer)); + + USBDBGVAL32("Datalen new: ",u32DataSize); + + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + if (u32DataSize > 0) + { + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + else + { + USBDBG("SIZE == 0\n"); + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpointHandle) || (pstcUsbHostIntern->Ep0IN == pstcEndpointHandle)) + { + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + } + if ((((pstcEndpointHandle->u8Address) & 0x0F) == 0) && ((pstcEndpointHandle->u8Stage) == USBHOST_STAGE_DATA)) + { + USBDBG("DATA STAGE -> STATUS STAGE\n"); + pstcUsbHostIntern->Ep0IN->u8Stage = USBHOST_STAGE_STATUS; + pstcUsbHostIntern->Ep0OUT->u8Stage = USBHOST_STAGE_STATUS; + pstcUsbHostIntern->Ep0IN->CompletionHandler = pstcUsbHostIntern->Ep0OUT->CompletionHandler; + pstcUsbHostIntern->Ep0IN->bToggle = TRUE; + pstcUsbHostIntern->Ep0OUT->bToggle = TRUE; + pstcUsbHostIntern->Ep0IN->u32DataSize = 0; + pstcUsbHostIntern->Ep0IN->pu8BufferPos = (pstcUsbHostIntern->Ep0IN->pu8Buffer); + pstcUsbHostIntern->Ep0IN->pu8BufferPosNextPackage = (pstcUsbHostIntern->Ep0IN->pu8BufferPos); + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + pstcUsbHostIntern->Ep0IN->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + else + { + USBDBG("TRANS COMPLETE\n"); + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + if (pstcEndpointHandle->u8Interval != 0) + { + pstcEndpointHandle->u32DataSize = 0; + } + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INITIATE; + if ((pstcEndpointHandle->CompletionHandler) != 0) + { + pstcEndpointHandle->CompletionHandler(pstcUsb); + } + + } + pstcUsbHostIntern->ActiveEndpoint = 0; + } + } + + } // endif ((((pstcEndpointHandle->u8LastToken) & 0x70) != HTOKEN_SETUP)) + + } // endif ((pstcUsb->HERR & 0x03) == HERR_ACK) + + if ((pstcUsb->HERR & 0x08) > 0) + { + USBDBG("Toggle Error\n"); + pstcUsb->HERR_f.TGERR = 0; + //pstcEndpointHandle->bToggle = ~pstcEndpointHandle->bToggle; + } // endif ((pstcUsb->HERR & 0x08) > 0) + + if ((pstcUsb->HERR & 0x08) > 0) + { + USBDBG("Toggle Error\n"); + pstcUsb->HERR_f.TGERR = 0; + //pstcEndpointHandle->bToggle = ~pstcEndpointHandle->bToggle; + } // endif ((pstcUsb->HERR & 0x08) > 0) + + if ((pstcUsb->HERR & 0x20) > 0) + { + USBDBG("NULL\n"); + USBDBGVAL8("HERR: ",pstcUsb->HERR); + pstcUsb->HERR_f.TOUT = 0; + } // endif ((pstcUsb->HERR & 0x20) > 0) + + if (((pstcUsb->HERR & 0x03) == HERR_NAK) || ((pstcUsb->HERR & 0x03) == HERR_NULL)) + { + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + USBDBG("NAK\n"); + if (((pstcEndpointHandle->u8Interval) > 0) && ((pstcEndpointHandle->pu8Buffer) == (pstcEndpointHandle->pu8BufferPos))) + { + USBDBG("Cancel\n"); + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + } + else + { + USBDBG("RTY\n"); + //UsbHost_TransferFifoToBuffer(pstcUsb,(uint8_t*)0); + pstcEndpointHandle->pu8BufferPosNextPackage = pstcEndpointHandle->pu8BufferPos; + if (pstcEndpointHandle->bAbortTransfer == TRUE) + { + USBDBG("-> CANCELED\n"); + pstcEndpointHandle->u32DataSize = 0; + pstcEndpointHandle->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + if ((pstcUsbHostIntern->Ep0OUT == pstcEndpointHandle) || (pstcUsbHostIntern->Ep0IN == pstcEndpointHandle)) + { + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + } + pstcEndpointHandle->bAbortTransfer = FALSE; + pstcUsbHostIntern->ActiveEndpoint = 0; + } + else + { + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_INITIATE; + } + } + } // endif ((pstcUsb->HERR & 0x03) == HERR_NAK) + + + + if ((pstcUsb->HERR & 0x03) == HERR_STALL) + { + USBDBG("STALL\n"); + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + pstcEndpointHandle = pstcUsbHostIntern->ActiveEndpoint; + pstcEndpointHandle->u8Status |= USBHOST_ENDPOINTSTATUS_STALL; + if (((pstcEndpointHandle->u8Address) & 0x0F) == 0) + { + USBDBG("Clearing STALL EP0\n"); + pstcUsbHostIntern->StallCompletionHandler = pstcEndpointHandle->CompletionHandler; + memcpy((uint8_t*)&pstcUsbHostIntern->stcLastSetupBeforeStall,(uint8_t*)&pstcUsbHostIntern->stcLastSetup,sizeof(pstcUsbHostIntern->stcLastSetup)); + pstcUsbHostIntern->Ep0IN->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + pstcUsbHostIntern->Ep0OUT->u8Status &= ~USBHOST_ENDPOINTSTATUS_INUSE; + UsbHost_SetupRequest(pstcUsb,(stc_usb_request_t*)&stcClearStallEp0,StallCompletionEp0); + } + else + { + if ((pstcEndpointHandle->CompletionHandler) != 0) + { + pstcEndpointHandle->CompletionHandler(pstcUsb); + } + } + } // endif ((pstcUsb->HERR & 0x03) == HERR_STALL) + DBGPROCRETURN("UsbHost_CompletionCallback"); + pstcUsbHostIntern->bSchedulerLock = bOldSchedulerLockState; + pstcUsbHostIntern->u32WaitForCompletionTimeout = 0; + UsbHost_Scheduler(pstcUsb, UsbHostSchedulerEventCompletion); +} + +void UsbHost_SofCallback(stc_usbn_t* pstcUsb) +{ + UsbHost_Scheduler(pstcUsb, UsbHostSchedulerEventSof); +} + +void UsbHost_Tick(void) +{ + #if (FM_PERIPHERAL_ENABLE_USB0 == ON) && defined(USB0) + UsbHost_Scheduler((stc_usbn_t*)&USB0,UsbHostSchedulerEventTick); + #endif + #if (FM_PERIPHERAL_ENABLE_USB1 == ON) && defined(USB1) + UsbHost_Scheduler((stc_usbn_t*)&USB1, UsbHostSchedulerEventTick); + #endif +} + +//@} // UsbHostGroup + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.h new file mode 100644 index 0000000000..470deca1a9 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usbhost.h @@ -0,0 +1,554 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbhost.h + ** + ** A detailed description is available at + ** @link UsbHostGroup USB Host Module description @endlink + ** + ** History: + ** - 2012-08-28 2.0 MSc First version (starting at version 2.0). + ** - 2012-11-13 2.1 MSc Some problems while switching from Host to Device fixed + ** - 2013-01-28 2.2 MSc Better Device Detection + ** - 2013-06-04 2.3 MSc FM4 support added + ** - 2014-02-28 2.4 MSc Speedup in package handling, fixes in fifo initialization + ** ISO transfers added + ** - 2014-05-06 2.5 MSc Fixing some variable initializations in disconnect routine + ** Added USBHOST_CONNECTION_DELAY to specify a delay in interations + ** for bus-reset / connection delay + ** - 2014-07-25 2.6 MSc Updated memory usage EP0 + ** - 2014-09-03 2.7 MSc Doxygen examples added + ** - 2015-09-03 2.8 MSCH Fixed disconnection deinitializations + ** + ******************************************************************************/ + +#ifndef __USBHOST_H__ +#define __USBHOST_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "usb.h" + + +/** + ****************************************************************************** + ** \defgroup UsbHostGroup USB Host Mode Functionality + ** + ** Provided functions of USB module: + ** + ** - UsbHost_AddHostEndpoint() + ** - UsbHost_EndpointFromNumber() + ** - UsbHost_AddressDevice() + ** - UsbHost_ReceiveSetupData() + ** - UsbHost_SetupRequestWithData() + ** - UsbHost_SetupRequest() + ** - UsbHost_ConnectionCallback() + ** - UsbHost_ClearAllEndpoints() + ** - UsbHost_DisconnectionCallback() + ** - UsbHost_CompletionCallback() + ** - UsbHost_SofCallback() + ** - UsbHost_BusresetCallback() + ** - UsbHost_InitCallback() + ** - UsbHost_TransferDataToFifo() + ** - UsbHost_TransferFifoToBuffer() + ** - UsbHost_TransferData() + ** - UsbHost_Init() + ** - UsbHost_GetDeviceStatus() + ** - UsbHost_SetConfigurationDescriptor() + ** - UsbHost_GetUsbEndpointDescriptor() + ** + ** Used to transfer data with EP0..EP15, to do enumeration process and support different + ** USB class drivers via UsbClassSupervisor. + ** + ******************************************************************************/ +//@{ + +/** + ****************************************************************************** + ** \page example_usbhostclass Example creating USB class named UsbHostClass + ** + ** usbhostclass.h + ** @code + ** #ifndef __USBHOSTCLASS_H__ + ** #define __USBHOSTCLASS_H__ + ** #include "usb.h" + ** #include "usbhost.h" + ** + ** void UsbHostNdis_RegisterDriver(void); + ** + ** #endif + ** @endcode + ** + ** usbhostclass.c + ** @code + ** #include "usbhostclass.h" + ** + ** static stc_usbn_t* pstcUsbHandle = NULL; + ** + ** static stc_host_endpoint_t *pstcEndpointOUT; + ** static stc_host_endpoint_t *pstcEndpointIN; + ** static uint8_t u8EndpointIN, u8EndpointOUT; + ** static uint16_t u16MaxPackageSizeIN, u16MaxPackageSizeOUT; + ** + ** static boolean_t Init(stc_usbn_t* pstcUsb, uint8_t* pu8Configuration, uint32_t u32Length); + ** static boolean_t Deinit(stc_usbn_t* pstcUsb); + ** static void Configured(stc_usbn_t* pstcUsb); + ** static void MsTask(stc_usbn_t* pstcUsb); + ** static void IsActive(stc_usbn_t* pstcUsb); + ** + ** static const stc_usbhostclasssupervisor_usbclassdriver_t stcDriverSetup = { + ** Init, //pfnInitClassDriver deinitialization callback of class driver + ** Deinit, //pfnDeinitClassDriver initialization callback of class driver + ** 0x0BDA, //u16IdVendor match vendor ID + ** 0x8196, //u16IdProduct match product ID + ** 0, //u8MatchDeviceClass match device class + ** 0, //u8MatchDeviceSubClass match device subclass + ** 0, //u8MatchDeviceProtocol match device protocol + ** 0, //u8MatchInterfaceClass match interface class + ** 0, //u8MatchInterfaceSubClass match interface subclass + ** 0, //u8MatchInterfaceProtocol match interface protocoll + ** 0, //u8Reserved reserved for back compatible reasons since UsbClassSupervisor V2.2 + ** Configured, //pfnDeviceConfigured device configured callback of class driver + ** MsTask, //pfnPeriodicTaskMs periodic ms callback for class driver + ** IsActive, //pfnIsActive driver is active callback for class driver + ** }; + ** + ** static stc_linked_list_item_t stcDriverSetupItem; + ** + ** void UsbHostNdis_RegisterDriver(void) + ** { + ** UsbHostClassSupervisor_RegisterClassDriver((stc_usbhostclasssupervisor_usbclassdriver_t*)&stcDriverSetup,&stcDriverSetupItem); + ** } + ** + ** static boolean_t Init(stc_usbn_t* pstcUsb, uint8_t* pu8Configuration, uint32_t u32Length) + ** { + ** uint8_t* pu8Buffer; + ** uint8_t u8NumberOfInterfaces; + ** uint8_t u8NumberOfEndpoints; + ** uint8_t u8EndpointNumber; + ** uint8_t u8InterfaceNumber; + ** if (pstcUsbHandle != NULL) // driver already loaded, do not load twice + ** { + ** return FALSE; + ** } + ** pstcUsbHandle = pstcUsb; + ** + ** u8NumberOfInterfaces=pu8Configuration[4]; // get number of interfaces in this configuration + ** + ** //for every interface... + ** for(u8InterfaceNumber=0;u8InterfaceNumber < u8NumberOfInterfaces;u8InterfaceNumber++) + ** { + ** //get pointer to interface descriptor + ** pu8Buffer = UsbHost_GetUsbInterfaceDescriptor(pu8Configuration,u32Length,u8InterfaceNumber); + ** + ** //if pointer to interface == 0, data is corrupt + ** if (pu8Buffer == 0) + ** { + ** return FALSE; + ** } + ** + ** //get number of endpoints + ** u8NumberOfEndpoints = pu8Buffer[4]; + ** + ** //in this case, search for mass storage interface class + ** if ((pu8Buffer[6] == 0x06) && (pu8Buffer[7] == 0x50)) //SubClass & Protocol + ** { + ** + ** //for every endpoint in this interface + ** for(u8EndpointNumber=1;u8EndpointNumber<=u8NumberOfEndpoints;u8EndpointNumber++) + ** { + ** + ** //get pointer to endpoint descriptor + ** pu8Buffer = UsbHost_GetUsbEndpointDescriptor(pu8Configuration,u32Length,u8InterfaceNumber,u8EndpointNumber); + ** + ** //is endpoint is IN direction? + ** if (pu8Buffer[2] & USB_IN_DIRECTION) + ** { + ** //get endpoint address + ** u8EndpointIN = pu8Buffer[2]; + ** + ** //get endpoint size + ** u16MaxPackageSizeIN = (uint16_t)(pu8Buffer[4] + (pu8Buffer[5] << 8)); + ** } + ** else //else endpoint is OUT direction + ** { + ** //get endpoint address + ** u8EndpointOUT = pu8Buffer[2]; + ** + ** //get endpoint size + ** u16MaxPackageSizeOUT = (uint16_t)(pu8Buffer[4] + (pu8Buffer[5] << 8)); + ** } + ** if ((u8EndpointIN != 0) && (u8EndpointOUT != 0)) //all endpoints found? + ** { + ** break; + ** } + ** } + ** + ** if ((u8EndpointIN == 0) && (u8EndpointOUT == 0)) //endpoint addresses are not valid? + ** { + ** return FALSE; + ** } + ** + ** //registering found endpoints + ** UsbHost_AddHostEndpoint(pstcUsbHandle,&pstcEndpointOUT,u8EndpointOUT,u16MaxPackageSizeOUT,0,0); + ** UsbHost_AddHostEndpoint(pstcUsbHandle,&pstcEndpointIN,u8EndpointIN,u16MaxPackageSizeIN,0,0); + ** + ** return TRUE; //endpoints are ready to use, configuration can be used + ** } + ** } + ** + ** return FALSE; //This configuration is not workable for this driver + ** } + ** + ** static boolean_t Deinit(stc_usbn_t* pstcUsb) + ** { + ** if (pstcUsbHandle == pstcUsb) + ** { + ** pstcUsbHandle = NULL; + ** return TRUE; + ** } + ** return FALSE; + ** } + ** + ** static void Configured(stc_usbn_t* pstcUsb) + ** { + ** } + ** + ** static void MsTask(stc_usbn_t* pstcUsb) + ** { + ** } + ** + ** static void IsActive(stc_usbn_t* pstcUsb) + ** { + ** if (pstcUsbHandle == pstcUsb) + ** { + ** return TRUE; + ** } + ** return FALSE; + ** } + ** @endcode + ** + ** Example in main.c + ** @code + ** #include "usb.h" + ** #include "usbhostclass.h" + ** + ** int main() + ** { + ** UsbHostClass_RegisterDriver(); + ** UsbConfig_UsbInit(); + ** for(;;) + ** { + ** UsbConfig_SwitchMode(); + ** //your code to access UsbHostClass + ** } + ** } + ** @endcode + ** + ******************************************************************************/ + + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + +#if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + +#define USBHOST_CONNECTION_DELAY 200000 +#define USBHOST_GLOBALBUFFER_SIZE 2000 +#define MAX_HOST_ENDPOINTS 6 +// Token mask in the HTOKEN register +#define HTOKEN_SETUP 0x10 +#define HTOKEN_IN 0x20 +#define HTOKEN_OUT 0x30 +#define HTOKEN_SOF 0x40 +#define HTOKEN_ISO_IN 0x50 +#define HTOKEN_ISO_OUT 0x60 + +#define CREATE_TOKEN(toggle, type, endpoint) ((toggle) << 7) | type | endpoint + +#define HERR_SOF_MASK 0x80 +#define HERR_RCV_MASK 0x40 +#define HERR_TOUT_MASK 0x20 +#define HERR_CRC_MASK 0x10 +#define HERR_TOGGLE_MASK 0x8 +#define HERR_BITSTUFF_MASK 0x4 + +#define USBHOST_SCHEDULER_COMPLETION 0x01 +#define USBHOST_SCHEDULER_SOF 0x02 +#define USBHOST_SCHEDULER_IDLE 0x03 +#define USBHOST_SCHEDULER_BUSY 0x04 + +#define USBHOST_SUCCESS 0 +#define USBHOST_ERROR 1 + +#define USBHOST_ENDPOINTSTATUS_INITIATE 0x01 +#define USBHOST_ENDPOINTSTATUS_ACTIVE 0x02 +#define USBHOST_ENDPOINTSTATUS_INUSE 0x04 +#define USBHOST_ENDPOINTSTATUS_DATA 0x08 +#define USBHOST_ENDPOINTSTATUS_STALL 0x10 + +#define USBHOST_EPADDR0_OUT 0x00 +#define USBHOST_EPADDR0_IN 0x80 + + +#define HERR_ACK 0 +#define HERR_NAK 0x01 +#define HERR_STALL 0x02 +#define HERR_NULL 0x03 + +#define BM_REQUESTTYPE_DIROUT 0x00 +#define BM_REQUESTTYPE_DIRIN 0x80 + +#define BM_REQUESTTYPE_DIR 0x80 +#define BM_REQUESTTYPE_TYPE 0x60 +#define BM_REQUESTTYPE_RECEIVER 0x1F + + +#define USBHOST_STAGE_IDLE 1 +#define USBHOST_STAGE_SETUP 2 +#define USBHOST_STAGE_DATA 3 +#define USBHOST_STAGE_STATUS 4 +#define USBHOST_STAGE_HANDSHAKE 5 + +#define USBHOST_DEVICE_IDLE 1 +#define USBHOST_DEVICE_ADDRESSING 2 +#define USBHOST_DEVICE_ADDRESSED 4 +#define USBHOST_DEVICE_ENUMERATED 8 +#define USBHOST_DEVICE_CONFIGURATING 16 +#define USBHOST_DEVICE_CONFIGURED 32 + +#ifndef IS_SET + #define IS_SET(x,y) ((x & y) > 0) +#endif + +#ifndef IS_CLEARED + #define IS_CLEARED(x,y) ((x & y) == 0) +#endif + +#ifndef SET_MASK + #define SET_MASK(x,y) x |= y +#endif + +#ifndef CLEAR_MASK + #define CLEAR_MASK(x,y) x &= ~y +#endif + +#ifndef TOGGLE_MASK + #define TOGGLE_MASK(x,y) SET_MASK(x,y); CLEAR_MASK(x,y) +#endif +#define ISOUT(x) (!ISIN(x)) +#define ISIN(x) ((Handler->u8Address) & 0x80) + +#define USBHOST_RESETENDPOINTBUFFER(endpoint,buffer,datasize) (endpoint->u32DataSize) = datasize;\ + (endpoint->pu8Buffer) = buffer;\ + (endpoint->pu8BufferPosNextPackage) = buffer;\ + (endpoint->pu8BufferPos) = buffer;\ + if (endpoint->u32BufferSize < datasize) (endpoint->u32BufferSize) = datasize + +#define USB_DESCRIPTOR_LENGTH 0x00 +#define USB_DESCRIPTOR_DESCRIPTORTYPE 0x01 +#define USB_INTERFACE_DESCRIPTOR_INTERFACENUMBER 0x03 + +#define USBH_STATUS_SUCCESS 0x0000 +#define USBH_STATUS_ERROR 0x0001 +#define USBH_STATUS_STALL 0x0008 +#define USBH_STATUS_LENGTH 0x000D + +#define UsbHost_GetUsbInterfaceDescriptor(x,y,z) UsbHost_GetUsbEndpointDescriptor(x,y,z, 0) + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + +typedef void(*usbhost_setupcomplete_t)(stc_usbn_t* pstcUsb, uint8_t* pu8Data, uint32_t u32Size); + +/** + ****************************************************************************** + ** \brief Host endpoint + ** + ** Used to setup virtual endpoints + ** + ******************************************************************************/ +typedef struct stc_host_endpoint +{ + uint8_t* pu8Buffer; ///< Buffer for sending / receiving data + uint8_t* pu8BufferPos; ///< Current woring position + uint8_t* pu8BufferPosNextPackage; ///< Next working position + uint32_t u32DataSize; ///< Size of data in buffer + uint32_t u32BufferSize; ///< Size of buffer + uint16_t u16FifoSize; ///< FIFO size of virtual endpoint + void (* CompletionHandler)(stc_usbn_t* pstcUsb); ///< Data transferred callback handle + boolean_t bToggle; ///< Data toggle + uint8_t u8LastToken; ///< Last token via this endpoint + volatile uint8_t u8Status; ///< endpoint status + volatile uint8_t u8Stage; ///< endpoint stage + uint8_t u8Address; ///< Endpoint address + uint8_t u8Interval; ///< Endpoint interrupt value (for interrupt transfers) + uint8_t u8IntervalCount; ///< Counter used for priority calulations + uint8_t u8Retries; ///< Number of retries before abort the transfer + boolean_t bAbortTransfer; ///< Force abort transfer + boolean_t bIsochronous; ///< TRUE, if type is isochronous +} stc_host_endpoint_t; + +/** + ****************************************************************************** + ** \brief Host internal data + ** + ** used to store different values + ** + ******************************************************************************/ +typedef struct stc_usbhost_intern_data +{ + stc_usbn_endpoint_data_t* pstcUsbHalEndpointOUT; ///< Endpoint used for data OUT transfers + stc_usbn_endpoint_data_t* pstcUsbHalEndpointIN; ///< Endpoint used for data IN transfers + stc_host_endpoint_t* Ep0IN; ///< Control endpoint IN + stc_host_endpoint_t* Ep0OUT; ///< Control endpoint OUT + stc_host_endpoint_t* ActiveEndpoint; ///< Current active endpoint + uint8_t u8DeviceStatus; ///< Status of connected device + uint8_t u8DeviceAddress; ///< Address of connected device + uint8_t u8EnumerationCounter; ///< Statemachine counter for initial enumeration process + stc_usb_request_t stcLastSetup; ///< Last sent setup request + stc_usb_request_t stcLastSetupBeforeStall; ///< Last sent setup request before stall + uint8_t* pu8SetupData; ///< Additional data of setup request + volatile uint32_t u32Timeout; ///< Timout variable + volatile uint32_t u32ConTimeout; ///< Connection timout variable + volatile uint32_t u32BusResetTimeout; ///< Busreset timout variable + volatile uint32_t u32ConnectionDelay; ///< Connection delay variable + uint8_t u8CurrentEndpointPosition; ///< Current position in endpoint list + uint8_t u8EndpointListEnd; ///< Last element in endpoint list + volatile boolean_t bSchedulerLock; ///< Lock Scheduler + volatile boolean_t bBusResetSend; ///< Bus reset was executed (used to determine second connect after bus reset) + stc_host_endpoint_t astcHostEndpoints[MAX_HOST_ENDPOINTS]; ///< Endpoint list + uint8_t pu8Setup[8]; ///< Setup buffer + uint8_t u8SyncToken; ///< Sync Token + uint8_t u8SetupDelay; ///< Send delayed setup + uint8_t u8LastToken; ///< Last token which was sent + uint8_t u8SchedulerState; ///< Status of scheduler + stc_host_endpoint_t* pstcClearEndpoint; ///< Endpoint handle which was cleared + volatile boolean_t bFullSpeed; ///< Fullspeed mode? + volatile uint32_t u32WaitForCompletionTimeout; ///< Wait for completion timeout + volatile boolean_t bSofToken; ///< Send token with SOF + uint8_t pu8GlobalBuffer[USBHOST_GLOBALBUFFER_SIZE]; ///< Global buffer + void (* StallCompletionHandler)(stc_usbn_t* pstcUsb); ///< Stall callback handler + void (* SetupCompletionHandler)(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize); ///< Setup package finished callback handler +} stc_usbhost_intern_data_t; + +/** + ****************************************************************************** + ** \brief Host internal instance data + ** + ** used to sync USB HAL with internal variables + ** + ******************************************************************************/ +typedef struct stc_usbhostn_instance_data +{ + volatile stc_usbn_t* pstcInstance; ///< pointer to registers of an instance + stc_usbhost_intern_data_t stcInternData; ///< module internal data of instance +} stc_usbhostn_instance_data_t; + + + + + + + + +uint8_t UsbHost_AddHostEndpoint(stc_usbn_t* pstcUsb, stc_host_endpoint_t** pstcHandler, uint8_t u8EndpointAddress, uint16_t u16FifoSize, uint8_t u8Interval, void(* CompletionHandler)(stc_usbn_t* pstcUsb)); + +stc_host_endpoint_t* UsbHost_EndpointFromNumber(stc_usbn_t* pstcUsb, uint8_t u8EndpointNumber); + +void UsbHost_AddressDevice(stc_usbn_t* pstcUsb, uint8_t u8NewAddress); + +uint32_t UsbHost_ReceiveSetupData(stc_usbn_t* pstcUsb, uint8_t** pu8Buffer); + +void UsbHost_SetupRequestWithData(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup, uint8_t* pu8Data, void(*SetupCompletion)(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize)); + +void UsbHost_SetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup, void(*SetupCompletion)(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize)); + +void UsbHost_ConnectionCallback(stc_usbn_t* pstcUsb); + +void UsbHost_ClearAllEndpoints(stc_usbn_t* pstcUsb); + +void UsbHost_DisconnectionCallback(stc_usbn_t* pstcUsb); + +void UsbHost_CompletionCallback(stc_usbn_t* pstcUsb); + +void UsbHost_SofCallback(stc_usbn_t* pstcUsb); + +void UsbHost_BusresetCallback(stc_usbn_t* pstcUsb); + +void UsbHost_InitCallback(stc_usbn_t* pstcUsb,struct stc_usb_config* pstcConfig); + +void UsbHost_TransferDataToFifo(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint16_t u16Size, uint16_t u16FifoSize); + +uint16_t UsbHost_TransferFifoToBuffer(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32MaxBufferSize); + +void UsbHost_TransferData(stc_usbn_t* pstcUsb, stc_host_endpoint_t* Handler,uint8_t* pu8Buffer, uint32_t u32BufferSize, void (* CompletionHandler)(stc_usbn_t* pstcUsb)); + +void UsbHost_Init(stc_usbn_t* pstcUsb, stc_usb_config_t* pstcUsbConfig); + +uint8_t UsbHost_GetDeviceStatus(stc_usbn_t* pstcUsb); + +void UsbHost_ClearEndpoint(stc_usbn_t* pstcUsb, stc_host_endpoint_t* pstcEndpoint); + +void UsbHost_AbortTransfer(stc_host_endpoint_t* pstcEndpoint); + +void UsbHost_ResetToggle(stc_host_endpoint_t* pstcEndpoint); + +void UsbHost_ClearEndpointCompletion(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize); + +void UsbHost_ClearEndpointPoll(stc_usbn_t* pstcUsb, stc_host_endpoint_t* pstcEndpoint); + +void UsbHost_SetConfigurationDescriptor(stc_usbn_t* pstcUsb, uint8_t u8Configuration); + +uint8_t* UsbHost_GetUsbEndpointDescriptor(uint8_t* pu8Buffer, uint16_t u16Size, uint8_t u8InterfaceNumber, uint8_t u8EndpointNumber); + +void UsbHost_SchedulerInitiateEndpoint(stc_usbn_t* pstcUsb, stc_usbhost_intern_data_t* pstcUsbHostIntern, stc_host_endpoint_t* pstcEndpoint); + +void UsbHost_Tick(void); + +#ifdef __cplusplus +} +#endif +//@} // UsbHostGroup + +#endif /* (FM_PERIPHERAL_USB_HOST_ENABLED == ON) */ +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usblegacy.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usblegacy.h new file mode 100644 index 0000000000..4d9be20ff6 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/usb/usblegacy.h @@ -0,0 +1,906 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usblegacy.h + ** + ** A detailed description is available at + ** @link UsbLegacyGroup USB backward support for older software stacks of PDL, L3 or older templates description @endlink + ** + ** History: + ** - 2015-11-05 V1.0 MSc First Version + *****************************************************************************/ + +#ifndef __USBLEGACY_H__ +#define __USBLEGACY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbLegacyGroup USB backward support for older software stacks of PDL, L3 or older templates + ** + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "base_types.h" +#include "mcu.h" + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB_MODULE register bit fields */ +typedef struct stc_usbn_hcnt_field +{ + __IO uint16_t HOST : 1; + __IO uint16_t URST : 1; + __IO uint16_t SOFIRE : 1; + __IO uint16_t DIRE : 1; + __IO uint16_t CNNIRE : 1; + __IO uint16_t CMPIRE : 1; + __IO uint16_t URIRE : 1; + __IO uint16_t RWKIRE : 1; + __IO uint16_t RETRY : 1; + __IO uint16_t CANCEL : 1; + __IO uint16_t SOFSTEP : 1; +} stc_usbn_hcnt_field_t; + +typedef struct stc_usbn_hcnt0_field +{ + __IO uint8_t HOST : 1; + __IO uint8_t URST : 1; + __IO uint8_t SOFIRE : 1; + __IO uint8_t DIRE : 1; + __IO uint8_t CNNIRE : 1; + __IO uint8_t CMPIRE : 1; + __IO uint8_t URIRE : 1; + __IO uint8_t RWKIRE : 1; +} stc_usbn_hcnt0_field_t; + +typedef struct stc_usbn_hcnt1_field +{ + __IO uint8_t RETRY : 1; + __IO uint8_t CANCEL : 1; + __IO uint8_t SOFSTEP : 1; +} stc_usbn_hcnt1_field_t; + +typedef struct stc_usbn_hirq_field +{ + __IO uint8_t SOFIRQ : 1; + __IO uint8_t DIRQ : 1; + __IO uint8_t CNNIRQ : 1; + __IO uint8_t CMPIRQ : 1; + __IO uint8_t URIRQ : 1; + __IO uint8_t RWKIRQ : 1; + uint8_t RESERVED1 : 1; + __IO uint8_t TCAN : 1; +} stc_usbn_hirq_field_t; + +typedef struct stc_usbn_herr_field +{ + __IO uint8_t HS0 : 1; + __IO uint8_t HS1 : 1; + __IO uint8_t STUFF : 1; + __IO uint8_t TGERR : 1; + __IO uint8_t CRC : 1; + __IO uint8_t TOUT : 1; + __IO uint8_t RERR : 1; + __IO uint8_t LSTOF : 1; +} stc_usbn_herr_field_t; + +typedef struct stc_usbn_hstate_field +{ + __IO uint8_t CSTAT : 1; + __IO uint8_t TMODE : 1; + __IO uint8_t SUSP : 1; + __IO uint8_t SOFBUSY : 1; + __IO uint8_t CLKSEL : 1; + __IO uint8_t ALIVE : 1; +} stc_usbn_hstate_field_t; + +typedef struct stc_usbn_hfcomp_field +{ + __IO uint8_t FRAMECOMP0 : 1; + __IO uint8_t FRAMECOMP1 : 1; + __IO uint8_t FRAMECOMP2 : 1; + __IO uint8_t FRAMECOMP3 : 1; + __IO uint8_t FRAMECOMP4 : 1; + __IO uint8_t FRAMECOMP5 : 1; + __IO uint8_t FRAMECOMP6 : 1; + __IO uint8_t FRAMECOMP7 : 1; +} stc_usbn_hfcomp_field_t; + +typedef struct stc_usbn_hrtimer_field +{ + __IO uint16_t RTIMER0 : 1; + __IO uint16_t RTIMER1 : 1; + __IO uint16_t RTIMER2 : 1; + __IO uint16_t RTIMER3 : 1; + __IO uint16_t RTIMER4 : 1; + __IO uint16_t RTIMER5 : 1; + __IO uint16_t RTIMER6 : 1; + __IO uint16_t RTIMER7 : 1; + __IO uint16_t RTIMER8 : 1; + __IO uint16_t RTIMER9 : 1; + __IO uint16_t RTIMER10 : 1; + __IO uint16_t RTIMER11 : 1; + __IO uint16_t RTIMER12 : 1; + __IO uint16_t RTIMER13 : 1; + __IO uint16_t RTIMER14 : 1; + __IO uint16_t RTIMER15 : 1; +} stc_usbn_hrtimer_field_t; + +typedef struct stc_usbn_hrtimer0_field +{ + __IO uint8_t RTIMER00 : 1; + __IO uint8_t RTIMER01 : 1; + __IO uint8_t RTIMER02 : 1; + __IO uint8_t RTIMER03 : 1; + __IO uint8_t RTIMER04 : 1; + __IO uint8_t RTIMER05 : 1; + __IO uint8_t RTIMER06 : 1; + __IO uint8_t RTIMER07 : 1; +} stc_usbn_hrtimer0_field_t; + +typedef struct stc_usbn_hrtimer1_field +{ + __IO uint8_t RTIMER10 : 1; + __IO uint8_t RTIMER11 : 1; + __IO uint8_t RTIMER12 : 1; + __IO uint8_t RTIMER13 : 1; + __IO uint8_t RTIMER14 : 1; + __IO uint8_t RTIMER15 : 1; + __IO uint8_t RTIMER16 : 1; + __IO uint8_t RTIMER17 : 1; +} stc_usbn_hrtimer1_field_t; + +typedef struct stc_usbn_hrtimer2_field +{ + __IO uint8_t RTIMER20 : 1; + __IO uint8_t RTIMER21 : 1; + __IO uint8_t RTIMER22 : 1; +} stc_usbn_hrtimer2_field_t; + +typedef struct stc_usbn_hadr_field +{ + __IO uint8_t ADDRESS0 : 1; + __IO uint8_t ADDRESS1 : 1; + __IO uint8_t ADDRESS2 : 1; + __IO uint8_t ADDRESS3 : 1; + __IO uint8_t ADDRESS4 : 1; + __IO uint8_t ADDRESS5 : 1; + __IO uint8_t ADDRESS6 : 1; +} stc_usbn_hadr_field_t; + +typedef struct stc_usbn_heof_field +{ + __IO uint16_t EOF0 : 1; + __IO uint16_t EOF1 : 1; + __IO uint16_t EOF2 : 1; + __IO uint16_t EOF3 : 1; + __IO uint16_t EOF4 : 1; + __IO uint16_t EOF5 : 1; + __IO uint16_t EOF6 : 1; + __IO uint16_t EOF7 : 1; + __IO uint16_t EOF8 : 1; + __IO uint16_t EOF9 : 1; + __IO uint16_t EOF10 : 1; + __IO uint16_t EOF11 : 1; + __IO uint16_t EOF12 : 1; + __IO uint16_t EOF13 : 1; + __IO uint16_t EOF14 : 1; + __IO uint16_t EOF15 : 1; +} stc_usbn_heof_field_t; + +typedef struct stc_usbn_heof0_field +{ + __IO uint8_t EOF00 : 1; + __IO uint8_t EOF01 : 1; + __IO uint8_t EOF02 : 1; + __IO uint8_t EOF03 : 1; + __IO uint8_t EOF04 : 1; + __IO uint8_t EOF05 : 1; + __IO uint8_t EOF06 : 1; + __IO uint8_t EOF07 : 1; +} stc_usbn_heof0_field_t; + +typedef struct stc_usbn_heof1_field +{ + __IO uint8_t EOF10 : 1; + __IO uint8_t EOF11 : 1; + __IO uint8_t EOF12 : 1; + __IO uint8_t EOF13 : 1; + __IO uint8_t EOF14 : 1; + __IO uint8_t EOF15 : 1; +} stc_usbn_heof1_field_t; + +typedef struct stc_usbn_hframe_field +{ + __IO uint16_t FRAME0 : 1; + __IO uint16_t FRAME1 : 1; + __IO uint16_t FRAME2 : 1; + __IO uint16_t FRAME3 : 1; + __IO uint16_t FRAME4 : 1; + __IO uint16_t FRAME5 : 1; + __IO uint16_t FRAME6 : 1; + __IO uint16_t FRAME7 : 1; + __IO uint16_t FRAME8 : 1; + __IO uint16_t FRAME9 : 1; + __IO uint16_t FRAME10 : 1; +} stc_usbn_hframe_field_t; + +typedef struct stc_usbn_hframe0_field +{ + __IO uint8_t FRAME00 : 1; + __IO uint8_t FRAME01 : 1; + __IO uint8_t FRAME02 : 1; + __IO uint8_t FRAME03 : 1; + __IO uint8_t FRAME04 : 1; + __IO uint8_t FRAME05 : 1; + __IO uint8_t FRAME06 : 1; + __IO uint8_t FRAME07 : 1; +} stc_usbn_hframe0_field_t; + +typedef struct stc_usbn_hframe1_field +{ + __IO uint8_t FRAME10 : 1; + __IO uint8_t FRAME11 : 1; + __IO uint8_t FRAME12 : 1; + __IO uint8_t FRAME13 : 1; +} stc_usbn_hframe1_field_t; + +typedef struct stc_usbn_htoken_field +{ + __IO uint8_t ENDPT0 : 1; + __IO uint8_t ENDPT1 : 1; + __IO uint8_t ENDPT2 : 1; + __IO uint8_t ENDPT3 : 1; + __IO uint8_t TKNEN0 : 1; + __IO uint8_t TKNEN1 : 1; + __IO uint8_t TKNEN2 : 1; + __IO uint8_t TGGL : 1; +} stc_usbn_htoken_field_t; + +typedef struct stc_usbn_udcc_field +{ + __IO uint16_t PWC : 1; + __IO uint16_t RFBK : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t STALCLREN : 1; + __IO uint16_t USTP : 1; + __IO uint16_t HCONX : 1; + __IO uint16_t RESUM : 1; + __IO uint16_t RST : 1; +} stc_usbn_udcc_field_t; + +typedef struct stc_usbn_ep0c_field +{ + __IO uint16_t PKS00 : 1; + __IO uint16_t PKS01 : 1; + __IO uint16_t PKS02 : 1; + __IO uint16_t PKS03 : 1; + __IO uint16_t PKS04 : 1; + __IO uint16_t PKS05 : 1; + __IO uint16_t PKS06 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; +} stc_usbn_ep0c_field_t; + +typedef struct stc_usbn_ep1c_field +{ + __IO uint16_t PKS10 : 1; + __IO uint16_t PKS11 : 1; + __IO uint16_t PKS12 : 1; + __IO uint16_t PKS13 : 1; + __IO uint16_t PKS14 : 1; + __IO uint16_t PKS15 : 1; + __IO uint16_t PKS16 : 1; + __IO uint16_t PKS17 : 1; + __IO uint16_t PKS18 : 1; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usbn_ep1c_field_t; + +typedef struct stc_usbn_ep2c_field +{ + __IO uint16_t PKS20 : 1; + __IO uint16_t PKS21 : 1; + __IO uint16_t PKS22 : 1; + __IO uint16_t PKS23 : 1; + __IO uint16_t PKS24 : 1; + __IO uint16_t PKS25 : 1; + __IO uint16_t PKS26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usbn_ep2c_field_t; + +typedef struct stc_usbn_ep3c_field +{ + __IO uint16_t PKS30 : 1; + __IO uint16_t PKS31 : 1; + __IO uint16_t PKS32 : 1; + __IO uint16_t PKS33 : 1; + __IO uint16_t PKS34 : 1; + __IO uint16_t PKS35 : 1; + __IO uint16_t PKS36 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usbn_ep3c_field_t; + +typedef struct stc_usbn_ep4c_field +{ + __IO uint16_t PKS40 : 1; + __IO uint16_t PKS41 : 1; + __IO uint16_t PKS42 : 1; + __IO uint16_t PKS43 : 1; + __IO uint16_t PKS44 : 1; + __IO uint16_t PKS45 : 1; + __IO uint16_t PKS46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usbn_ep4c_field_t; + +typedef struct stc_usbn_ep5c_field +{ + __IO uint16_t PKS50 : 1; + __IO uint16_t PKS51 : 1; + __IO uint16_t PKS52 : 1; + __IO uint16_t PKS53 : 1; + __IO uint16_t PKS54 : 1; + __IO uint16_t PKS55 : 1; + __IO uint16_t PKS56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usbn_ep5c_field_t; + +typedef struct stc_usbn_tmsp_field +{ + __IO uint16_t TMSP0 : 1; + __IO uint16_t TMSP1 : 1; + __IO uint16_t TMSP2 : 1; + __IO uint16_t TMSP3 : 1; + __IO uint16_t TMSP4 : 1; + __IO uint16_t TMSP5 : 1; + __IO uint16_t TMSP6 : 1; + __IO uint16_t TMSP7 : 1; + __IO uint16_t TMSP8 : 1; + __IO uint16_t TMSP9 : 1; + __IO uint16_t TMSP10 : 1; +} stc_usbn_tmsp_field_t; + +typedef struct stc_usbn_udcs_field +{ + __IO uint8_t CONF : 1; + __IO uint8_t SETP : 1; + __IO uint8_t WKUP : 1; + __IO uint8_t BRST : 1; + __IO uint8_t SOF : 1; + __IO uint8_t SUSP : 1; +} stc_usbn_udcs_field_t; + +typedef struct stc_usbn_udcie_field +{ + __IO uint8_t CONFIE : 1; + __IO uint8_t CONFN : 1; + __IO uint8_t WKUPIE : 1; + __IO uint8_t BRSTIE : 1; + __IO uint8_t SOFIE : 1; + __IO uint8_t SUSPIE : 1; +} stc_usbn_udcie_field_t; + +typedef struct stc_usbn_ep0is_field +{ + uint16_t RESERVED1 : 10; + __IO uint16_t DRQI : 1; + uint16_t RESERVED2 : 3; + __IO uint16_t DRQIIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_ep0is_field_t; + +typedef struct stc_usbn_ep0os_field +{ + __IO uint16_t SIZE0 : 1; + __IO uint16_t SIZE1 : 1; + __IO uint16_t SIZE2 : 1; + __IO uint16_t SIZE3 : 1; + __IO uint16_t SIZE4 : 1; + __IO uint16_t SIZE5 : 1; + __IO uint16_t SIZE6 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQO : 1; + uint16_t RESERVED2 : 2; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQOIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_ep0os_field_t; + +typedef struct stc_usbn_ep1s_field +{ + __IO uint16_t SIZE10 : 1; + __IO uint16_t SIZE11 : 1; + __IO uint16_t SIZE12 : 1; + __IO uint16_t SIZE13 : 1; + __IO uint16_t SIZE14 : 1; + __IO uint16_t SIZE15 : 1; + __IO uint16_t SIZE16 : 1; + __IO uint16_t SIZE17 : 1; + __IO uint16_t SIZE18 : 1; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_ep1s_field_t; + +typedef struct stc_usbn_ep2s_field +{ + __IO uint16_t SIZE20 : 1; + __IO uint16_t SIZE21 : 1; + __IO uint16_t SIZE22 : 1; + __IO uint16_t SIZE23 : 1; + __IO uint16_t SIZE24 : 1; + __IO uint16_t SIZE25 : 1; + __IO uint16_t SIZE26 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_ep2s_field_t; + +typedef struct stc_usbn_ep4s_field +{ + __IO uint16_t SIZE40 : 1; + __IO uint16_t SIZE41 : 1; + __IO uint16_t SIZE42 : 1; + __IO uint16_t SIZE43 : 1; + __IO uint16_t SIZE44 : 1; + __IO uint16_t SIZE45 : 1; + __IO uint16_t SIZE46 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_ep4s_field_t; + +typedef struct stc_usbn_ep5s_field +{ + __IO uint16_t SIZE50 : 1; + __IO uint16_t SIZE51 : 1; + __IO uint16_t SIZE52 : 1; + __IO uint16_t SIZE53 : 1; + __IO uint16_t SIZE54 : 1; + __IO uint16_t SIZE55 : 1; + __IO uint16_t SIZE56 : 1; + uint16_t RESERVED1 : 2; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED2 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_ep5s_field_t; + + +typedef struct stc_usbn_epns_field +{ + __IO uint16_t SIZE : 8; + __IO uint16_t SPK : 1; + __IO uint16_t DRQ : 1; + __IO uint16_t BUSY : 1; + uint16_t RESERVED1 : 1; + __IO uint16_t SPKIE : 1; + __IO uint16_t DRQIE : 1; + __IO uint16_t BFINI : 1; +} stc_usbn_epns_field_t; + +typedef struct stc_usbn_epns +{ + union { + __IO uint16_t EPNS; + stc_usbn_epns_field_t EPNS_f; + }; + uint8_t RESERVED[2]; +} stc_usbn_epns_t; + +typedef struct stc_usbn_epnc_field +{ + __IO uint16_t PKS : 9; + __IO uint16_t STAL : 1; + __IO uint16_t NULE : 1; + __IO uint16_t DMAE : 1; + __IO uint16_t DIR : 1; + __IO uint16_t TYPE0 : 1; + __IO uint16_t TYPE1 : 1; + __IO uint16_t EPEN : 1; +} stc_usbn_epnc_field_t; + +typedef struct stc_usbn_epnc +{ + union { + __IO uint16_t EPNC; + stc_usbn_epnc_field_t EPNC_f; + }; + uint8_t RESERVED[2]; + +} stc_usbn_epnc_t; + +typedef struct stc_usbn_epdt +{ + union { + __IO uint16_t EPNDT; + struct { + __IO uint8_t EPNDTL; + __IO uint8_t EPNDTH; + }; + }; + uint8_t RESERVED[2]; +} stc_usbn_epdt_t; + +/****************************************************************************** + * USB_MODULE + ******************************************************************************/ +/* USB channel 0 registers */ +typedef struct stc_usbn +{ + union { + union { + __IO uint16_t HCNT; + stc_usbn_hcnt_field_t HCNT_f; + }; + struct { + union { + __IO uint8_t HCNT0; + stc_usbn_hcnt0_field_t HCNT0_f; + }; + union { + __IO uint8_t HCNT1; + stc_usbn_hcnt1_field_t HCNT1_f; + }; + }; + }; + uint8_t RESERVED0[2]; + union { + __IO uint8_t HIRQ; + stc_usbn_hirq_field_t HIRQ_f; + }; + union { + __IO uint8_t HERR; + stc_usbn_herr_field_t HERR_f; + }; + uint8_t RESERVED1[2]; + union { + __IO uint8_t HSTATE; + stc_usbn_hstate_field_t HSTATE_f; + }; + union { + __IO uint8_t HFCOMP; + stc_usbn_hfcomp_field_t HFCOMP_f; + }; + uint8_t RESERVED2[2]; + union { + union { + __IO uint16_t HRTIMER; + stc_usbn_hrtimer_field_t HRTIMER_f; + }; + struct { + union { + __IO uint8_t HRTIMER0; + stc_usbn_hrtimer0_field_t HRTIMER0_f; + }; + union { + __IO uint8_t HRTIMER1; + stc_usbn_hrtimer1_field_t HRTIMER1_f; + }; + }; + }; + uint8_t RESERVED3[2]; + union { + __IO uint8_t HRTIMER2; + stc_usbn_hrtimer2_field_t HRTIMER2_f; + }; + union { + __IO uint8_t HADR; + stc_usbn_hadr_field_t HADR_f; + }; + uint8_t RESERVED4[2]; + union { + union { + __IO uint16_t HEOF; + stc_usbn_heof_field_t HEOF_f; + }; + struct { + union { + __IO uint8_t HEOF0; + stc_usbn_heof0_field_t HEOF0_f; + }; + union { + __IO uint8_t HEOF1; + stc_usbn_heof1_field_t HEOF1_f; + }; + }; + }; + uint8_t RESERVED5[2]; + union { + union { + __IO uint16_t HFRAME; + stc_usbn_hframe_field_t HFRAME_f; + }; + struct { + union { + __IO uint8_t HFRAME0; + stc_usbn_hframe0_field_t HFRAME0_f; + }; + union { + __IO uint8_t HFRAME1; + stc_usbn_hframe1_field_t HFRAME1_f; + }; + }; + }; + uint8_t RESERVED6[2]; + union { + __IO uint8_t HTOKEN; + stc_usbn_htoken_field_t HTOKEN_f; + }; + uint8_t RESERVED7[3]; + union { + __IO uint16_t UDCC; + stc_usbn_udcc_field_t UDCC_f; + }; + uint8_t RESERVED8[2]; + union { + __IO uint16_t EP0C; + stc_usbn_ep0c_field_t EP0C_f; + }; + uint8_t RESERVED9[2]; + union { + __IO uint16_t EP1C; + stc_usbn_ep1c_field_t EP1C_f; + }; + uint8_t RESERVED10[2]; + union { + __IO uint16_t EP2C; + stc_usbn_ep2c_field_t EP2C_f; + }; + uint8_t RESERVED11[2]; + union { + __IO uint16_t EP3C; + stc_usbn_ep3c_field_t EP3C_f; + }; + uint8_t RESERVED12[2]; + union { + __IO uint16_t EP4C; + stc_usbn_ep4c_field_t EP4C_f; + }; + uint8_t RESERVED13[2]; + union { + __IO uint16_t EP5C; + stc_usbn_ep5c_field_t EP5C_f; + }; + uint8_t RESERVED14[2]; + union { + __IO uint16_t TMSP; + stc_usbn_tmsp_field_t TMSP_f; + }; + uint8_t RESERVED15[2]; + union { + __IO uint8_t UDCS; + stc_usbn_udcs_field_t UDCS_f; + }; + union { + __IO uint8_t UDCIE; + stc_usbn_udcie_field_t UDCIE_f; + }; + uint8_t RESERVED16[2]; + union { + __IO uint16_t EP0IS; + stc_usbn_ep0is_field_t EP0IS_f; + }; + uint8_t RESERVED17[2]; + union { + __IO uint16_t EP0OS; + stc_usbn_ep0os_field_t EP0OS_f; + }; + uint8_t RESERVED18[2]; + union { + __IO uint16_t EP1S; + stc_usbn_ep1s_field_t EP1S_f; + }; + uint8_t RESERVED19[2]; + union { + __IO uint16_t EP2S; + stc_usbn_ep2s_field_t EP2S_f; + }; + uint8_t RESERVED20[2]; + __IO uint16_t EP3S; + uint8_t RESERVED21[2]; + union { + __IO uint16_t EP4S; + stc_usbn_ep4s_field_t EP4S_f; + }; + uint8_t RESERVED22[2]; + union { + __IO uint16_t EP5S; + stc_usbn_ep5s_field_t EP5S_f; + }; + uint8_t RESERVED23[2]; + union { + __IO uint16_t EP0DT; + struct { + __IO uint8_t EP0DTL; + __IO uint8_t EP0DTH; + }; + }; + uint8_t RESERVED24[2]; + union { + __IO uint16_t EP1DT; + struct { + __IO uint8_t EP1DTL; + __IO uint8_t EP1DTH; + }; + }; + uint8_t RESERVED25[2]; + union { + __IO uint16_t EP2DT; + struct { + __IO uint8_t EP2DTL; + __IO uint8_t EP2DTH; + }; + }; + uint8_t RESERVED26[2]; + union { + __IO uint16_t EP3DT; + struct { + __IO uint8_t EP3DTL; + __IO uint8_t EP3DTH; + }; + }; + uint8_t RESERVED27[2]; + union { + __IO uint16_t EP4DT; + struct { + __IO uint8_t EP4DTL; + __IO uint8_t EP4DTH; + }; + }; + uint8_t RESERVED28[2]; + union { + __IO uint16_t EP5DT; + struct { + __IO uint8_t EP5DTL; + __IO uint8_t EP5DTH; + }; + }; +} stc_usbn_t; + +#if (defined(_MB9A110K_H_) || defined(_MB9A110L_H_) || defined(_MB9A110M_H_) || defined(_MB9A110N_H_) || \ + defined(_MB9A130K_H_) || defined(_MB9A130L_H_) || defined(_MB9A130M_H_) || defined(_MB9A130N_H_) || \ + defined(_MB9A310L_H_) || defined(_MB9A310M_H_) || defined(_MB9A310N_H_) || \ + defined(_MB9B500N_H_) || defined(_MB9B500R_H_)) + #define USBLIB_USB0_IRQn USBF_IRQn + #define USBLIB_USB0_DEVHOST_IRQn USBF_USBH_IRQn +#elif defined(FM4_USB0_BASE) || defined(FM4_USB1_BASE) + #define USBLIB_USB0_IRQn USB0_IRQn + #define USBLIB_USB0_DEVHOST_IRQn USB0_HOST_IRQn + #if FM4_DEVICE_TYPE == 3 + #define USBLIB_USB1_IRQn USB1_HDMICEC0_IRQn + #define USBLIB_USB1_DEVHOST_IRQn USB1_HOST_HDMICEC1_IRQn + #else + #define USBLIB_USB1_IRQn USB1_IRQn + #define USBLIB_USB1_DEVHOST_IRQn USB1_HOST_IRQn + #endif +#else + #define USBLIB_USB0_IRQn USB0F_IRQn + #define USBLIB_USB0_DEVHOST_IRQn USB0F_USB0H_IRQn + #define USBLIB_USB1_IRQn USB1F_IRQn + #define USBLIB_USB1_DEVHOST_IRQn USB1F_USB1H_IRQn +#endif + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + + +#ifdef __cplusplus +} +#endif + +//@} // UsbLegacyGroup + +#endif /* __USBLEGACY_H__*/ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.c new file mode 100644 index 0000000000..169ff2daed --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.c @@ -0,0 +1,689 @@ +/******************************************************************************* +* \file vbat.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the VBAT +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "vbat/vbat.h" + +#if (defined(PDL_PERIPHERAL_VBAT_ACTIVE)) + +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/* This is a workaround for Cypress ID 245800. The CCB register definition is +* not present in the device header file for FM0P_TYPE2 MCU. +*/ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) +#define FM_RTC_CCB *((volatile uint8_t*)(0x4003B180UL)) +#endif /* PDL_MCU_TYPE == PDL_FM0P_TYPE2 */ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Initialize VBAT + ** + ** This function initializes an VBAT module + ** + ** \param [in] pstcConfig VBAT module configuration + ** + ** \retval Ok VBAT initialized normally + ** \retval ErrorInvalidParameter If one of following cases matchs: + ** - pstcConfig == NULL + ** - Other invalid configuration + ******************************************************************************/ +en_result_t Vbat_Init(const stc_vbat_config_t* pstcConfig) +{ + // Check parameter + if (NULL == pstcConfig) + { + return ErrorInvalidParameter; + } + + // Clear VBAT power on flag + FM_RTC->VDET = 0u; + + // Configure transfer clock + if ((0u == pstcConfig->u8ClkDiv) || (0xFFu == pstcConfig->u8ClkDiv)) + { + return ErrorInvalidParameter; + } + FM_RTC->VB_CLKDIV = pstcConfig->u8ClkDiv; + + // Configure sustain/boost current +#ifdef PDL_PERIPHERAL_VBAT_TYPE_A + switch (pstcConfig->enSustainCurrent) + { + case Clk0nA: + FM_RTC->CCS = 0x00u; + break; + case Clk385nA: + FM_RTC->CCS = 0x04u; + break; + case Clk445nA: + FM_RTC->CCS = 0x08u; + break; + case Clk510nA: + FM_RTC->CCS = 0x10u; + break; + default: + return ErrorInvalidParameter; + } + + switch (pstcConfig->enBoostCurrent) + { + case Clk0nA: + FM_RTC->CCB = 0x00u; + break; + case Clk385nA: + FM_RTC->CCB = 0x04u; + break; + case Clk445nA: + FM_RTC->CCB = 0x08u; + break; + case Clk510nA: + FM_RTC->CCB = 0x10u; + break; + default: + return ErrorInvalidParameter; + } +#else + switch (pstcConfig->enSustainCurrent) + { + case ClkLowPower: + FM_RTC->CCS = 0x04u; + break; + case ClkStandard: + FM_RTC->CCS = 0xCEu; + break; + default: + return ErrorInvalidParameter; + } + +/* Workaround for Cypress ID 245800 */ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE2) + switch (pstcConfig->enBoostCurrent) + { + case ClkLowPower: + FM_RTC_CCB = 0x04u; + break; + case ClkStandard: + FM_RTC_CCB = 0xCEu; + break; + default: + return ErrorInvalidParameter; + } +#else + switch (pstcConfig->enBoostCurrent) + { + case ClkLowPower: + FM_RTC->CCB = 0x04u; + break; + case ClkStandard: + FM_RTC->CCB = 0xCEu; + break; + default: + return ErrorInvalidParameter; + } +#endif /* (PDL_MCU_TYPE == PDL_FM0P_TYPE2) */ +#endif /* PDL_PERIPHERAL_VBAT_TYPE_A */ + + // Set boost time + switch (pstcConfig->enClkBoostTime) + { + case ClkBoost50ms: + FM_RTC->BOOST = 0u; + break; + case ClkBoost63ms: + FM_RTC->BOOST = 1u; + break; + case ClkBoost125ms: + FM_RTC->BOOST = 2u; + break; + case ClkBoost250ms: + FM_RTC->BOOST = 3u; + break; + default: + return ErrorInvalidParameter; + } + + // Configure whether to link clock to clock control module + FM_RTC->WTOSCCNT_f.SOSCNTL = ((pstcConfig->bLinkSubClk == TRUE) ? 1u : 0u); + + // Configure whether to enable sub clock in the VBAT domain + FM_RTC->WTOSCCNT_f.SOSCEX = ((pstcConfig->bVbatClkEn == TRUE) ? 0u : 1u); + + // Transmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Configure pin funciton of P48/VREGCTL to VREGCTL + ******************************************************************************/ +void Vbat_SetPinFunc_VREGCTL(void) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set function register + FM_RTC->VBPFR_f.VPFR0 = 1u; + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Configure pin funciton of P49/VWAKEUP to VWAKEUP + ******************************************************************************/ +void Vbat_SetPinFunc_VWAKEUP(void) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set function register + FM_RTC->VBPFR_f.VPFR1 = 1u; + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Configure pin funciton of P46/X0A, P47/X1A to X0A, X1A + ******************************************************************************/ +void Vbat_SetPinFunc_X0A_X1A(void) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set function register + FM_RTC->VBPFR_f.SPSR0 = 1u; + FM_RTC->VBPFR_f.SPSR1 = 0u; + FM_RTC->VBPFR_f.VPFR2 = 1u; + FM_RTC->VBPFR_f.VPFR3 = 1u; + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Initialize VBAT GPIO output + ** + ** This function initializes an VBAT GPIO output + ** + ** \param [in] enGpio VBAT GPIO list + ** \param [in] bInitLevel GPIO output initial level + ** \param [in] bOpenDrain GPIO open drain or not + ** + ** \retval Ok VBAT initialized normally + ** \retval ErrorInvalidParameter enGpio out of range + ** + ** \note Open drain funciton is only available for P48 and P49. + ** + ******************************************************************************/ +en_result_t Vbat_InitGpioOutput(en_vbat_gpio_t enGpio, + boolean_t bInitLevel, + boolean_t bOpenDrain) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set GPIO registers + switch (enGpio) + { + case VbatGpioP46: + FM_RTC->VBPFR_f.SPSR0 = 0u; + FM_RTC->VBPFR_f.SPSR1 = 0u; + FM_RTC->VBPFR_f.VPFR3 = 0u; + FM_RTC->VBDDR_f.VDDR3 = 1u; + FM_RTC->VBDOR_f.VDOR3 = ((1u == bInitLevel) ? 1u : 0u); + break; + case VbatGpioP47: + FM_RTC->VBPFR_f.SPSR0 = 0u; + FM_RTC->VBPFR_f.SPSR1 = 0u; + FM_RTC->VBPFR_f.VPFR2 = 0u; + FM_RTC->VBDDR_f.VDDR2 = 1u; + FM_RTC->VBDOR_f.VDOR2 = ((1u == bInitLevel) ? 1u : 0u); + break; + case VbatGpioP48: + FM_RTC->VBPFR_f.VPFR0 = 0u; + FM_RTC->VBDDR_f.VDDR0 = 1u; + FM_RTC->VBDOR_f.VDOR0 = ((1u == bInitLevel) ? 1u : 0u); + FM_RTC->VBPZR_f.VPZR0 = ((1u == bOpenDrain) ? 1u : 0u); + break; + case VbatGpioP49: + FM_RTC->VBPFR_f.VPFR1 = 0u; + FM_RTC->VBDDR_f.VDDR1 = 1u; + FM_RTC->VBDOR_f.VDOR1 = ((1u == bInitLevel) ? 1u : 0u); + FM_RTC->VBPZR_f.VPZR1 = ((1u == bOpenDrain) ? 1u : 0u); + break; + default: + return ErrorInvalidParameter; + } + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Initialize VBAT GPIO input + ** + ** This function initializes an VBAT GPIO input + ** + ** \param [in] enGpio VBAT GPIO list + ** \param [in] bPullup GPIO pullup register connected or not + ** + ** \retval Ok VBAT initialized normally + ** \retval ErrorInvalidParameter enGpio out of range + ** + ******************************************************************************/ +en_result_t Vbat_InitGpioInput(en_vbat_gpio_t enGpio, boolean_t bPullup) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set GPIO registers + switch (enGpio) + { + case VbatGpioP46: + FM_RTC->VBPFR_f.SPSR0 = 0u; + FM_RTC->VBPFR_f.SPSR1 = 0u; + FM_RTC->VBPFR_f.VPFR3 = 0u; + FM_RTC->VBDDR_f.VDDR3 = 0u; + FM_RTC->VBPCR_f.VPCR3 = ((1u == bPullup) ? 1u : 0u); + break; + case VbatGpioP47: + FM_RTC->VBPFR_f.SPSR0 = 0u; + FM_RTC->VBPFR_f.SPSR1 = 0u; + FM_RTC->VBPFR_f.VPFR2 = 0u; + FM_RTC->VBDDR_f.VDDR2 = 0u; + FM_RTC->VBPCR_f.VPCR2 = ((1u == bPullup) ? 1u : 0u); + break; + case VbatGpioP48: + FM_RTC->VBPFR_f.VPFR0 = 0u; + FM_RTC->VBDDR_f.VDDR0 = 0u; + FM_RTC->VBPCR_f.VPCR0 = ((1u == bPullup) ? 1u : 0u); + break; + case VbatGpioP49: + FM_RTC->VBPFR_f.VPFR1 = 0u; + FM_RTC->VBDDR_f.VDDR1 = 0u; + FM_RTC->VBPCR_f.VPCR1 = ((1u == bPullup) ? 1u : 0u); + break; + default: + return ErrorInvalidParameter; + } + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Set the output level of P46 + ** + ** \param [in] bLevel Output level + ** + ******************************************************************************/ +void Vbat_PutPinP46(boolean_t bLevel) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set output register + FM_RTC->VBDOR_f.VDOR3 = ((1u == bLevel) ? 1u : 0u); + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Set the output level of P47 + ** + ** \param [in] bLevel Output level + ** + ******************************************************************************/ +void Vbat_PutPinP47(boolean_t bLevel) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set output register + FM_RTC->VBDOR_f.VDOR2 = ((1u == bLevel) ? 1u : 0u); + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Set the output level of P48 + ** + ** \param [in] bLevel Output level + ** + ******************************************************************************/ +void Vbat_PutPinP48(boolean_t bLevel) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set output register + FM_RTC->VBDOR_f.VDOR0 = ((1u == bLevel) ? 1u : 0u); + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Set the output level of P49 + ** + ** \param [in] bLevel Output level + ** + ******************************************************************************/ +void Vbat_PutPinP49(boolean_t bLevel) +{ + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + // Set output register + FM_RTC->VBDOR_f.VDOR1 = ((1u == bLevel) ? 1u : 0u); + + // Trasnmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + return; +} + +/** + ****************************************************************************** + ** \brief Get the input level of P46 + ** + ** \retval TRUE High level + ** \retval FALSE Low level + ** + ******************************************************************************/ +boolean_t Vbat_GetPinP46(void) +{ + boolean_t bRet; + + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + bRet = ((1u == FM_RTC->VBDIR_f.VDIR3) ? 1u : 0u) ; + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Get the input level of P47 + ** + ** \retval TRUE High level + ** \retval FALSE Low level + ** + ******************************************************************************/ +boolean_t Vbat_GetPinP47(void) +{ + boolean_t bRet; + + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + bRet = ((1u == FM_RTC->VBDIR_f.VDIR2) ? 1u : 0u) ; + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Get the input level of P48 + ** + ** \retval TRUE High level + ** \retval FALSE Low level + ** + ******************************************************************************/ +boolean_t Vbat_GetPinP48(void) +{ + boolean_t bRet; + + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + bRet = ((1u == FM_RTC->VBDIR_f.VDIR0) ? 1u : 0u) ; + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Get the input level of P49 + ** + ** \retval TRUE High level + ** \retval FALSE Low level + ** + ******************************************************************************/ +boolean_t Vbat_GetPinP49(void) +{ + boolean_t bRet; + + // Recall from VBAT domain + FM_RTC->WTCR20_f.PREAD = 1u; + + // Wait to complete transmission + while(0u != FM_RTC->WTCR10_f.TRANS) + {} + + bRet = ((1u == FM_RTC->VBDIR_f.VDIR1) ? 1u : 0u) ; + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Start hibernation function of VBAT + ******************************************************************************/ +void Vbat_StartHibernation(void) +{ + FM_RTC->HIBRST = 1u; + + return; +} + +/** + ****************************************************************************** + ** \brief Get power on flag of VBAT + ** + ** \retval TRUE Power on flag set + ** \retval FALSE Power on flag clear + ******************************************************************************/ +boolean_t Vbat_GetPowerOnFlag(void) +{ + boolean_t bRet; + + bRet = (1u == FM_RTC->VDET_f.PON) ? 1u : 0u; + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Get wakeup flag of VBAT + ** + ** \retval TRUE wakeup flag set + ** \retval FALSE wakeup flag clear + ******************************************************************************/ +boolean_t Vbat_GetWakeupFlag(void) +{ + boolean_t bRet; + + bRet = (1u == FM_RTC->EWKUP_f.WUP0) ? 1u : 0u; + + return bRet; +} + +/** + ****************************************************************************** + ** \brief Clear wakeup flag of VBAT + ******************************************************************************/ +void Vbat_ClrWakeupFlag(void) +{ + FM_RTC->EWKUP_f.WUP0 = 0u; +} + +#endif + +#endif // #if (defined(PDL_PERIPHERAL_VBAT_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.h new file mode 100644 index 0000000000..79e7fa4dae --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/vbat/vbat.h @@ -0,0 +1,243 @@ +/******************************************************************************* +* \file vbat.h +* +* \version 1.20 +* +* \brief Headerfile for VBAT functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __VBAT_H__ +#define __VBAT_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if defined (FM4_RTC_TYPE_A) + #define PDL_PERIPHERAL_VBAT_TYPE_A 1 +#elif defined (FM4_RTC_TYPE_B) || defined (FM0P_RTC_TYPE_B) + #define PDL_PERIPHERAL_VBAT_TYPE_B 1 +#endif + +#if defined (PDL_PERIPHERAL_VBAT_TYPE_A) || defined (PDL_PERIPHERAL_VBAT_TYPE_B) + #define PDL_PERIPHERAL_VBAT_AVAILABLE PDL_ON +#else + #define PDL_PERIPHERAL_VBAT_AVAILABLE PDL_OFF +#endif + +#if (defined(PDL_PERIPHERAL_VBAT_ACTIVE)) + +#if (PDL_PERIPHERAL_VBAT_AVAILABLE == PDL_ON) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupVBAT VBAT Domain (VBAT) +* \{ +* \defgroup GroupVBAT_Functions Functions +* \defgroup GroupVBAT_DataStructures Data Structures +* \defgroup GroupVBAT_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupVBAT +* \{ +* Use this peripheral block to manage battery power. Cypress FM microcontrollers have three power domains:
+* - CPU domain +* - Always-on domain +* - VBAT domain +* If the system power supply to the VCC pin is cut off, power to the CPU Domain and Always-on Domain is stopped. +* The VBAT domain gets power from a battery. The VBAT domain includes these circuits:
+* * Real time clock (RTC) +* * 32 kHz oscillation circuit +* * Power-on circuit +* * Back up registers: 32 bytes +* * Port circuit +* The VBAT power supply provides power to four I/O port pins, P46, P47, P48, and P49. This peripheral enables control of those pins.
+* +* \note The VBAT domain is available only in FM4 devices (except type 5) +* and FM0+ type 2 devices. +* +* \section SectionVBAT_ConfigurationConsideration Configuration Consideration +* To set up a VBAT, you provide configuration parameters in the stc_vbat_config_t +* structure. Then call Vbat_Init(). This call clears the VBAT power-on flag and sets the transfer +* clock division, sub oscillator configuration, and boost time current.
+* To set pin function, call Vbat_SetPinFunc_X() where X = VREGCTL, VWAKEUP, +* or X0A_X1A.
+* To initialize a VBAT GPIO pin for output, call Vbat_InitGpioOutput() with the pin, level, and drain. +* To initialize a pin for input, use Vbat_InitGpioOutput with the pin and pullup.
+* You can set or get the level of any of the four pins with Vbat_PutPinX() or Vbat_GetPinX(), where X = P46, P47, P48, or P49.
+* Use other function calls start hibernation, read the power flag (which is set when VBAT is power on), and get or clear the wakeup flag.
+* +* \section SectionVBAT_MoreInfo More Information +* For more information on the VBAT peripheral, refer to:
+* FM0+ Peripheral Manual - Core Subsystem TRM.pdf
+* FM4 Peripheral Manual - Core Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +#ifdef PDL_PERIPHERAL_VBAT_TYPE_A + +/** +* \addtogroup GroupVBAT_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Sustain and Boost Current + ******************************************************************************/ +typedef enum en_clk_current +{ + Clk0nA = 0u, ///< 0 nA sustain/boost, not allowed, if subclock is enabled + Clk385nA = 1u, ///< 385 nA + Clk445nA = 2u, ///< 445 nA, initial value for current sustain + Clk510nA = 3u, ///< 510 nA, initial value for current boost + ClkErrorCurrent = 4u, ///< Errornous setting (for read-out function) +} en_clk_current_t; +#else +typedef enum en_clk_current +{ + ClkLowPower = 0u, ///< Low power mode. Allows for a smaller type of crystal oscillator + ClkStandard = 1u ///< Standard power mode (initial value) +} en_clk_current_t; +#endif + +/** + ****************************************************************************** + ** \brief Sustain and Boost Time + ******************************************************************************/ +typedef enum en_clk_boost_time +{ + ClkBoost50ms = 0u, ///< Boost time 50 ms (initial value) + ClkBoost63ms = 1u, ///< Boost time 62.5 ms + ClkBoost125ms = 2u, ///< Boost time 125 ms + ClkBoost250ms = 3u ///< Boost time 250 ms +} en_clk_boost_time_t; + +/** + ****************************************************************************** + ** \brief VBAT GPIO selection + *******************************************************************************/ +typedef enum en_vbat_gpio +{ + VbatGpioP46 = 0u, ///< P46 pin + VbatGpioP47 = 1u, ///< P47 pin + VbatGpioP48 = 2u, ///< P48 pin + VbatGpioP49 = 3u, ///< P49 pin + +}en_vbat_gpio_t; + +/** \} GroupVBAT_Types */ + +/** +* \addtogroup GroupVBAT_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief VBAT configuration + *******************************************************************************/ +typedef struct stc_vbat_config +{ + uint8_t u8ClkDiv; ///< Transfer clock division of PREAD, PWRITE, BREAD, BWRITE + boolean_t bLinkSubClk; ///< FALSE: The 32 kHz oscillation circuit operates independently as VBAT Domain + ///< TRUE: The 32 kHz oscillation circuit is linked with the clock control circuit. + boolean_t bVbatClkEn; ///< FALSE: Stops the oscillation of VBAT + ///< TRUE: Starts the oscillation of VBAT + en_clk_current_t enSustainCurrent; ///< Sustain current of sub clock + en_clk_current_t enBoostCurrent; ///< Boost current of sub clock + en_clk_boost_time_t enClkBoostTime; ///< Boost time of sub clock + +}stc_vbat_config_t; + + +/** \} GroupVBAT_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupVBAT_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/* VBAT init */ +en_result_t Vbat_Init(const stc_vbat_config_t* pstcConfig); +/* Function pin setting */ +void Vbat_SetPinFunc_VREGCTL(void); +void Vbat_SetPinFunc_VWAKEUP(void); +void Vbat_SetPinFunc_X0A_X1A(void); +/* GPIO setting */ +en_result_t Vbat_InitGpioOutput(en_vbat_gpio_t enGpio, + boolean_t bInitLevel, + boolean_t bOpenDrain); +en_result_t Vbat_InitGpioInput(en_vbat_gpio_t enGpio, boolean_t bPullup); +void Vbat_PutPinP46(boolean_t bLevel); +void Vbat_PutPinP47(boolean_t bLevel); +void Vbat_PutPinP48(boolean_t bLevel); +void Vbat_PutPinP49(boolean_t bLevel); +boolean_t Vbat_GetPinP46(void); +boolean_t Vbat_GetPinP47(void); +boolean_t Vbat_GetPinP48(void); +boolean_t Vbat_GetPinP49(void); +/* Start hibernation function */ +void Vbat_StartHibernation(void); +/* Get VBAT power on flag */ +boolean_t Vbat_GetPowerOnFlag(void); +/* Get/clear hibernation wakeup flag */ +boolean_t Vbat_GetWakeupFlag(void); +void Vbat_ClrWakeupFlag(void); + +/** \} GroupVBAT_Functions */ +/** \} GroupVBAT */ + +#ifdef __cplusplus +} +#endif + +#endif + +#endif // #if (defined(PDL_PERIPHERAL_VBAT_ACTIVE)) + +#endif /* __LPM_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.c new file mode 100644 index 0000000000..f814d4cc49 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.c @@ -0,0 +1,601 @@ +/******************************************************************************* +* \file wc.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the WC +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "wc/wc.h" + +#if (defined(PDL_PERIPHERAL_WC_ACTIVE)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) +static func_ptr_t pWcfnIrqCallback = NULL; +#endif + +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Set NVIC Interrupt depending on WC instance + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ******************************************************************************/ +static void WcInitNvic(stc_wcn_t* pstcWc) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(WC_IRQn); + NVIC_EnableIRQ(WC_IRQn); + NVIC_SetPriority(WC_IRQn, PDL_IRQ_LEVEL_WC0); +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_EnableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #elif (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_EnableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_IRQ_LEVEL_DT_RTC_WC); + #else + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_EnableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_IRQ_LEVEL_TIM_SMCIF1_HDMICEC1); + #endif +#else + NVIC_ClearPendingIRQ(TIM_WC_RTC_IRQn); + NVIC_EnableIRQ(TIM_WC_RTC_IRQn); + NVIC_SetPriority(TIM_WC_RTC_IRQn, PDL_IRQ_LEVEL_CLK_WC_RTC); +#endif +} + +/** + ****************************************************************************** + ** \brief Clear NVIC Interrupt depending on WC instance + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ******************************************************************************/ +static void WcDeInitNvic(stc_wcn_t* pstcWc) +{ +#if (PDL_MCU_CORE == PDL_FM4_CORE) + NVIC_ClearPendingIRQ(WC_IRQn); + NVIC_DisableIRQ(WC_IRQn); + NVIC_SetPriority(WC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#elif (PDL_MCU_CORE == PDL_FM0P_CORE) + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE1) + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_DisableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #elif (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + NVIC_ClearPendingIRQ(TIM_IRQn); + NVIC_DisableIRQ(TIM_IRQn); + NVIC_SetPriority(TIM_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #else + NVIC_ClearPendingIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_DisableIRQ(TIM_SMCIF1_HDMICEC1_IRQn); + NVIC_SetPriority(TIM_SMCIF1_HDMICEC1_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); + #endif +#else + NVIC_ClearPendingIRQ(TIM_WC_RTC_IRQn); + NVIC_DisableIRQ(TIM_WC_RTC_IRQn); + NVIC_SetPriority(TIM_WC_RTC_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif +} +/*! + ****************************************************************************** + ** \brief Watch counter interrupt function + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ******************************************************************************/ +void Wc_IrqHandler(stc_wcn_t* pstcWc) +{ + if (PdlSet == Wc_GetIrqFlag(pstcWc)) + { + Wc_ClearIrqFlag(pstcWc); + if (NULL != pWcfnIrqCallback) + { + pWcfnIrqCallback(); + } + } +} +#endif + +/** + ****************************************************************************** + ** \brief Select the input clock an and set the division clock to be output. + ** + ** The Function can set SEL_OUT, SEL_IN of Watch counter prescaler (hereafter WCP) + ** + ** \param [in] pstcWc Pointer to WC instance + ** \param [in] pstcWcPresClk WC prescaler clock configuration + ** + ** \retval Ok Write data successfully done or started. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - invalid value of pstcWcPresClk->enInputClk + ** - invalid value of pstcWcPresClk->enOutputClk + ** + ******************************************************************************/ +en_result_t Wc_Pres_SelClk(stc_wcn_t* pstcWc, stc_wc_pres_clk_t* pstcWcPresClk) +{ + /* check for non-null pointers */ + if ( (NULL == pstcWc) || (NULL == pstcWcPresClk) ) + { + return ErrorInvalidParameter; + } + + switch (pstcWcPresClk->enInputClk) + { + case WcPresInClkSubOsc: + pstcWc->CLK_SEL_f.SEL_IN = 0u; + break; + case WcPresInClkMainOsc: + pstcWc->CLK_SEL_f.SEL_IN = 1u; + break; + #if (PDL_MCU_TYPE == PDL_FM3_TYPE12) || (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case WcPresInClkHighCr: + pstcWc->CLK_SEL_f.SEL_IN = 2u; + break; + case WcPresInClkLowCr: + pstcWc->CLK_SEL_f.SEL_IN = 3u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + switch(pstcWcPresClk->enOutputClk) + { + case WcPresOutClkArray0: + pstcWc->CLK_SEL_f.SEL_OUT = 0u; + break; + case WcPresOutClkArray1: + pstcWc->CLK_SEL_f.SEL_OUT = 1u; + break; + #if (PDL_MCU_TYPE == PDL_FM3_TYPE12) || (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + case WcPresOutClkArray2: + pstcWc->CLK_SEL_f.SEL_OUT = 2u; + break; + case WcPresOutClkArray3: + pstcWc->CLK_SEL_f.SEL_OUT = 3u; + break; + case WcPresOutClkArray4: + pstcWc->CLK_SEL_f.SEL_OUT = 4u; + break; + case WcPresOutClkArray5: + pstcWc->CLK_SEL_f.SEL_OUT = 5u; + break; + case WcPresOutClkArray6: + pstcWc->CLK_SEL_f.SEL_OUT = 6u; + break; + #endif + default: + return ErrorInvalidParameter; + } + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable oscillation of the division clock. + ** + ** The Function can set CLK_EN:CLK_EN to 1 of WCP + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Ok Enable oscillation of the division clock normally + ** + ******************************************************************************/ +en_result_t Wc_Pres_EnableDiv(stc_wcn_t* pstcWc) +{ + /* check for non-null pointers */ + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->CLK_EN_f.CLK_EN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable oscillation of the division clock. + ** + ** The Function can clear CLK_EN:CLK_EN to 0 of WCP + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Ok Disable oscillation of the division clock normally + ** + ******************************************************************************/ +en_result_t Wc_Pres_DisableDiv(stc_wcn_t* pstcWc) +{ + /* check for non-null pointers */ + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->CLK_EN_f.CLK_EN = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get the operation status of the division counter. + ** + ** The Function can get CLK_EN:CLK_EN_R to 0 of WCP + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval PdlClr CLK_EN_R is 0, oscillation of the division clock is not performed + ** \retval PdlSet CLK_EN R is 1, oscillation of the division clock is performed + ** + ******************************************************************************/ +en_stat_flag_t Wc_Pres_GetDivStat(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return PdlClr; + } + + return ((en_stat_flag_t)(pstcWc->CLK_EN_f.CLK_EN_R)); +} + +/** + ****************************************************************************** + ** \brief Select the input clock and set the division clock to be output. + ** + ** The Function can set SEL_OUT, SEL_IN of Watch counter prescaler (hereafter WCP) + ** + ** \param [in] pstcWc Pointer to WC instance + ** \param [in] pstcWcConfig Pointer to WC configuration + ** + ** \retval Ok The data is written to registers normally. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - invalid value of pstcWcConfig->enCntClk + ** + ******************************************************************************/ +en_result_t Wc_Init(stc_wcn_t* pstcWc, const stc_wc_config_t* pstcWcConfig) +{ + // Check for NULL pointers + if ( (NULL == pstcWcConfig) || + (NULL == pstcWc) ) + { + return ErrorInvalidParameter; + } + + switch (pstcWcConfig->enCntClk) + { + case WcCntClkWcck0: + pstcWc->WCCR_f.CS = 0u; + break; + case WcCntClkWcck1: + pstcWc->WCCR_f.CS = 1u; + break; + case WcCntClkWcck2: + pstcWc->WCCR_f.CS = 2u; + break; + case WcCntClkWcck3: + pstcWc->WCCR_f.CS = 3u; + break; + default: + return ErrorInvalidParameter; + } + + pstcWc->WCRL = pstcWcConfig->u8ReloadValue; + +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) + if(TRUE == pstcWcConfig->bIrqEnable) + { + pstcWc->WCCR_f.WCIE = 1u; + } + + pWcfnIrqCallback = pstcWcConfig->pfnIrqCallback; + + if(TRUE == pstcWcConfig->bTouchNvic) + { + WcInitNvic(pstcWc); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief De-Initialize WC + ** + ** Clear all registers of WC + ** + ** \param [in] pstcWc WC configuration + ** \param [in] bTouchNvic Touch NVIC or not + ** + ** \retval Ok Write data successfully done or started. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcWc == NULL + ** + ******************************************************************************/ +en_result_t Wc_DeInit(stc_wcn_t* pstcWc, boolean_t bTouchNvic) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCCR = 0u; + pstcWc->WCRL = 0u; + +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) + if(TRUE == bTouchNvic) + { + WcDeInitNvic(pstcWc); + } +#endif + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Enable WC operation. + ** + ** The Function can set WCCR:WCEN to 1 of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Ok Enable WC operation normally + ** + ******************************************************************************/ +en_result_t Wc_EnableCount(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCCR_f.WCEN = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable WC operation. + ** + ** The Function can clear WCCR:WCEN to 0 of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Ok Disable WC operation normally + ** + ******************************************************************************/ +en_result_t Wc_DisableCount(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCCR_f.WCEN = 0u; + + return Ok; +} + +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) +/** + ****************************************************************************** + ** \brief Enable WC underflow interrupt. + ** + ** The Function can set WCIE of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Ok WC enabled successfully. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcWc == NULL + ** + ******************************************************************************/ +en_result_t Wc_EnableIrq(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCCR_f.WCIE = 1u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Disable WC underflow interrupt. + ** + ** The Function can clear WCIE of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** + ** \retval Ok Disable WC underflow interrupt normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcWc == NULL + ** + ******************************************************************************/ +en_result_t Wc_DisableIrq(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCCR_f.WCIE = 0u; + + return Ok; +} +#endif +/** + ****************************************************************************** + ** \brief Set the counter value of WC + ** + ** The Function can set value to WCRL of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** \param [in] u8Val Set the reload count value + ** + ** + ** \retval Ok Set the counter value of WC normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcWc == NULL + ** + ******************************************************************************/ +en_result_t Wc_WriteReloadVal(stc_wcn_t* pstcWc, uint8_t u8Val) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCRL = u8Val; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Read the value in the 6-bit down counter + ** + ** The Function can read value of WCRD of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Current count value of WC + ** + ******************************************************************************/ +uint8_t Wc_ReadCurCnt(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return 0xFFu; + } + + return (pstcWc->WCRD); +} + +/** + ****************************************************************************** + ** \brief Clear WC underflow flag + ** + ** The Function clear WCIF to 0 of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval Ok Clear WC underflow flag normally + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcWc == NULL + ** + ******************************************************************************/ +en_result_t Wc_ClearIrqFlag(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return ErrorInvalidParameter; + } + + pstcWc->WCCR_f.WCIF = 0u; + + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get WC underflow flag status + ** + ** The Function get value WCIF of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval PdlClr WCIF is 0, WC underflow does not occur + ** \retval PdlSet WCIF is 1, WC underflow occurs + ** + ******************************************************************************/ +en_irq_flag_t Wc_GetIrqFlag(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return PdlClr; + } + + return ((en_irq_flag_t)(pstcWc->WCCR_f.WCIF)); +} + +/** + ****************************************************************************** + ** \brief Get WC operation state + ** + ** The Function get value WCOP of WC + ** + ** \param [in] pstcWc Pointer to WC instance + ** + ** \retval PdlClr WCOP is 0, The WC is stopped + ** \retval PdlSet WCOP is 1, The WC is active + ** + ******************************************************************************/ +en_stat_flag_t Wc_GetOperationFlag(stc_wcn_t* pstcWc) +{ + // check for non-null pointers + if (NULL == pstcWc) + { + return PdlClr; + } + + return ((en_stat_flag_t)(pstcWc->WCCR_f.WCOP)); +} + + +#endif // #if (defined(PDL_PERIPHERAL_WC_ACTIVE)) + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.h new file mode 100644 index 0000000000..2caf2ea339 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wc/wc.h @@ -0,0 +1,245 @@ +/******************************************************************************* +* \file wc.h +* +* \version 1.20 +* +* \brief Headerfile for WC functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __WC_H__ +#define __WC_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_WC_ACTIVE)) + +/** +* \defgroup GroupWC Watch Counter (WC) +* \{ +* \defgroup GroupWC_Macros Macros +* \defgroup GroupWC_Functions Functions +* \defgroup GroupWC_DataStructures Data Structures +* \defgroup GroupWC_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupWC +* \{ +* The watch counter is a 6-bit down counter. It counts down from a specified value, +* and generates an interrupt request at the time that it enters an underflow condition. +* The timer’s period is based on an input clock, an output clock, and a prescalar. +* The output clock is one of WCCK0 to WCCK3. The input clock can be the main clock, +* the sub clock, the built-in high-speed CR clock or the built-in low-speed CR clock. +* The prescaler outputs the division clocks (WCCK0 to WCCK3) based on your prescalar choice. +* The prescalar choice ranges from 2 to 2^23.
+* The output clock and the watch counter’s value (0-63) determines the timer’s period. For example, +* if based on your configuration the timer’s period is one second, and you set the watch counter +* to a value of 60, it will generate an interrupt request once per minute.
+* You can handle the watch counter in one of two modes. In interrupt mode, the peripheral sets the +* interrupt flag and calls the interrupt handler when the interrupt occurs. In polling mode, the +* peripheral just sets the interrupt flag. You must poll to check the flag status, and handle the +* interrupt when the flag is set.
+* +* The Watch Counter wakes up the microcontroller from low-power mode. +* +* \section SectionWC_ConfigurationConsideration Configuration Consideration +* You configure the clock choices and the counter. You then start the clock, and the counter itself.
+* +* For easy setting needed underflow frequency in the WC use the following formula:
+* Set values in the stc_wc_pres_clk_t structure to specify the input clock and the prescalar choice. +* See the documentation for en_output_clk_t to see prescalar choices and how they affect WCCK0 +* through WCCK3. Then call Wc_Pres_SelClk() to initialize these choices.
+* +* Set values in the stc_wc_config_t structure to configure the counter. For example, set enCntClk +* to specify which clock drives the counter (WCCK0-WCCK3). If bIrqEnable is FALSE, you must poll to +* check for interrupts. If bIrqEnable is TRUE, the interrupt handler is called directly.
+* +* After setting the fields, call Wc_Init() to initialize the counter.
+* Call Wc_Pres_EnableDiv() to start the clock supply.
+* Call Wc_EnableCount() to start the counter.
+* If you are polling for interrupts, use WcGetIrqFlag() to check the interrupt status. If the +* flag is set, call Wc_IrqHandler() to clear the flag and invoke the handler. +* +* \section SectionWC_MoreInfo More Information +* For more information on the WC peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupWC_Macros +* \{ +*/ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +#define stc_wcn_t FM_WC_TypeDef +#define WC0 (*((stc_wcn_t *) FM_WC_BASE)) + +/** \} GroupWC_Macros */ + +/** +* \addtogroup GroupWC_Types +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Enumeration to define source clock of watch counter precaler + ******************************************************************************/ +typedef enum en_input_clk +{ + WcPresInClkSubOsc = 0u, ///< Watch counter prescaler source clock: sub oscillator + WcPresInClkMainOsc = 1u, ///< Watch counter prescaler source clock: main oscillator +#if (PDL_MCU_TYPE == PDL_FM3_TYPE12) || (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + WcPresInClkHighCr = 2u, ///< Watch counter prescaler source clock: high-speed CR + WcPresInClkLowCr = 3u, ///< Watch counter prescaler source clock: low-speed CR +#endif +}en_input_clk_t; + +/** + ****************************************************************************** + ** \brief Enumeration to define output clock of watch counter precaler + ******************************************************************************/ +typedef enum en_output_clk +{ /// WCCk3 WCCk2 WCCk1 WCCk0 + WcPresOutClkArray0 = 0u, ///< Watch counter prescaler output array0: 2^15/src clock, 2^14/src clock, 2^13/src clock, 2^12/src clock + WcPresOutClkArray1 = 1u, ///< Watch counter prescaler output array0: 2^25/src clock, 2^24/src clock, 2^23/src clock, 2^22/src clock +#if (PDL_MCU_TYPE == PDL_FM3_TYPE12) || (PDL_MCU_CORE == PDL_FM0P_CORE) || (PDL_MCU_CORE == PDL_FM4_CORE) + WcPresOutClkArray2 = 2u, ///< Watch counter prescaler output array0: 2^4/src clock, 2^3/src clock, 2^2/src clock, 2/src clock + WcPresOutClkArray3 = 3u, ///< Watch counter prescaler output array0: 2^8/src clock, 2^7/src clock, 2^6/src clock, 2^5/src clock + WcPresOutClkArray4 = 4u, ///< Watch counter prescaler output array0: 2^12/src clock, 2^11/src clock, 2^10/src clock, 2^9/src clock + WcPresOutClkArray5 = 5u, ///< Watch counter prescaler output array0: 2^19/src clock, 2^18/src clock, 2^17/src clock, 2^16/src clock + WcPresOutClkArray6 = 6u, ///< Watch counter prescaler output array0: 2^23/src clock, 2^22/src clock, 2^21/src clock, 2^20/src clock +#endif +}en_output_clk_t; + +/** + ****************************************************************************** + ** \brief Enumeration to set the clock of watch counter + ******************************************************************************/ +typedef enum en_wc_cnt_clk +{ + WcCntClkWcck0 = 0u, ///< Watch counter source clock: WCCK0 + WcCntClkWcck1 = 1u, ///< Watch counter source clock: WCCK1 + WcCntClkWcck2 = 2u, ///< Watch counter source clock: WCCK2 + WcCntClkWcck3 = 3u, ///< Watch counter source clock: WCCK3 + +}en_wc_cnt_clk_t; + +/** \} GroupWC_Types */ + +/** +* \addtogroup GroupWC_DataStructures +* \{ +*/ + +/** + ****************************************************************************** + ** \brief Structure to configure watch counter prescaler + ******************************************************************************/ +typedef struct stc_wc_pres_clk +{ + en_input_clk_t enInputClk; ///< Watch counter prescaler input clock setting + en_output_clk_t enOutputClk; ///< Watch counter prescaler output clock setting + +}stc_wc_pres_clk_t; + +/** + ****************************************************************************** + ** \brief Structure to configure the watch counter + ******************************************************************************/ +typedef struct stc_wc_config +{ + en_wc_cnt_clk_t enCntClk; ///< Watch counter source clock setting + uint8_t u8ReloadValue; ///< Reload value +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) + boolean_t bIrqEnable; ///< TRUE: enable IRQ, FALSE: don't enable IRQ + func_ptr_t pfnIrqCallback; ///< Pointer to interrupt callback function + boolean_t bTouchNvic; ///< TRUE: enable NVIC, FALSE: don't enable NVIC +#endif +}stc_wc_config_t; + +/** \} GroupWC_DataStructures */ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupWC_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/* 1. WC prescaler setting */ +en_result_t Wc_Pres_SelClk(stc_wcn_t* pstcWc, stc_wc_pres_clk_t* pstcWcPresClk); +en_result_t Wc_Pres_EnableDiv(stc_wcn_t* pstcWc); +en_result_t Wc_Pres_DisableDiv(stc_wcn_t* pstcWc); +en_stat_flag_t Wc_Pres_GetDivStat(stc_wcn_t* pstcWc); +/* 2. WC setting */ +/* Init/De-Init */ +en_result_t Wc_Init(stc_wcn_t* pstcWc, const stc_wc_config_t* pstcWcConfig); +en_result_t Wc_DeInit(stc_wcn_t* pstcWc, boolean_t bTouchNvic); +/* Func/Int enable/disable */ +en_result_t Wc_EnableCount(stc_wcn_t* pstcWc); +en_result_t Wc_DisableCount(stc_wcn_t* pstcWc); +#if (PDL_INTERRUPT_ENABLE_WC0 == PDL_ON) +en_result_t Wc_EnableIrq(stc_wcn_t* pstcWc); +en_result_t Wc_DisableIrq(stc_wcn_t* pstcWc); +#endif +/* Count write/read */ +en_result_t Wc_WriteReloadVal(stc_wcn_t* pstcWc, uint8_t u8Val); +uint8_t Wc_ReadCurCnt(stc_wcn_t* pstcWc); +/* Status clear */ +en_result_t Wc_ClearIrqFlag(stc_wcn_t* pstcWc); +/* Status read */ +en_irq_flag_t Wc_GetIrqFlag(stc_wcn_t* pstcWc); +en_stat_flag_t Wc_GetOperationFlag(stc_wcn_t* pstcWc); +/* 3. IRQ handler */ +void Wc_IrqHandler(stc_wcn_t* pstcWc); + +/** \} GroupWC_Functions */ +/** \} GroupWC */ + +#ifdef __cplusplus +} +#endif + +#endif // #if (defined(L3_PERIPHERAL_WC_ACTIVE)) + +#endif /* __WC_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.c new file mode 100644 index 0000000000..876b887d6b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.c @@ -0,0 +1,301 @@ +/******************************************************************************* +* \file hwwdg.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the HWWDG +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "wdg/hwwdg.h" + +#if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) + +#if (PDL_PERIPHERAL_ENABLE_HWWDG == PDL_ON) +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/* for WDG_CTL */ +#define HWWDG_CTL_INTEN (0x01u) +#define HWWDG_CTL_RESEN (0x02u) + +/* for checking magic word (Hwwdg_DeInit) */ +#define HWWDG_MAGIC_WORD_CHK1 (0x38D1AE5Cu) +#define HWWDG_MAGIC_WORD_CHK2 (0x7624D1BCu) +#define HWWDG_MAGIC_WORD_CHK_RESULT (0xFFFFFFFFu) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +static func_ptr_t pfnHwwdgCallback; ///< callback function pointer for HW-Wdg Irq + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Hardware Watchdog Interrupt Handler + ******************************************************************************/ +void HwwdgIrqHandler(void) +{ + /* Check hardware interrupt status */ + if (TRUE == FM_HWWDT->WDG_RIS_f.RIS) + { + if (NULL != pfnHwwdgCallback) + { + pfnHwwdgCallback(); + } + } +} /* HwwdgIrqHandler */ + +/** + ****************************************************************************** + ** \brief Initialize Hardware Watchdog + ** + ** \param [in] pstcConfig Pointer to Hardware Watchdog configuration + ** + ** \retval Ok Setup successful + ** \retval ErrorInvalidParameter pstcConfig == NULL + ** + ** \note This function only set the Hardware Watchdog configuration. + ** If Hwwdg_Start() is called, MCU start the Hardware Watchdog. + ******************************************************************************/ +en_result_t Hwwdg_Init(const stc_hwwdg_config_t* pstcConfig) +{ + en_result_t enResult; + uint8_t u8WdogControl = 0u; /* Preset register */ + + enResult = ErrorInvalidParameter; + /* Check for NULL Pointer */ + if (NULL != pstcConfig) + { + /* Release Lock */ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; + FM_HWWDT->WDG_LDR = pstcConfig->u32LoadValue; + + if (TRUE == pstcConfig->bResetEnable) + { + /* RESEN bit */ + u8WdogControl |= HWWDG_CTL_RESEN; + } + + /* HW Watchdog Control Register unlock sequence */ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_2; + + /* Setup HW-Watchdog and start */ + FM_HWWDT->WDG_CTL = u8WdogControl; + + /* Initialize callback to NULL */ + pfnHwwdgCallback = pstcConfig->pfnHwwdgIrqCb; + + enResult = Ok; + } + + return (enResult); +} /* Hwwdg_Init */ + +/** + ****************************************************************************** + ** \brief Un-Initialize Hardware Watchdog + ** + ** This function disables and un-initializes the Hardware Watchdog, when the + ** first argument is 0xC72E51A3 and the second agrument 0x89DB2E43. + ** The magic words are together 64-bit wide and have a balanced entropy. + ** (32 zero and 32 one bits) + ** + ** \param [in] u32MagicWord1 1st Magic word for disabling (0xC72E51A3) + ** \param [in] u32MagicWord2 2nd Magic word for disabling (0x89DB2E43) + ** + ** \retval Ok disable sucessful + ** \retval ErrorInvalidParameter not disabled => magic word is wrong + ** + ******************************************************************************/ +en_result_t Hwwdg_DeInit(uint32_t u32MagicWord1, + uint32_t u32MagicWord2 + ) +{ + en_result_t enResult; + + enResult = ErrorInvalidParameter; + + /* Inverted magic word check is done to avoid "plain text magic word" in ROM. */ + if ((HWWDG_MAGIC_WORD_CHK_RESULT == (u32MagicWord1 ^ HWWDG_MAGIC_WORD_CHK1)) && + (HWWDG_MAGIC_WORD_CHK_RESULT == (u32MagicWord2 ^ HWWDG_MAGIC_WORD_CHK2)) + ) + { + /* HW Watchdog Control Register unlock sequence */ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_2; + + /* HW Watchdog stop */ + FM_HWWDT->WDG_CTL = 0; + + /* Initialize callback to NULL */ + pfnHwwdgCallback = NULL; + + enResult = Ok; + } + + return (enResult); +} /* Hwwdg_DeInit */ + +/** + ****************************************************************************** + ** \brief Start the Hardware Watchdog + ** + ** \retval Ok Setup successful + ** \retval ErrorOperationInProgress Hardware Watchdog is active now + ** + ******************************************************************************/ +en_result_t Hwwdg_Start(void) +{ + en_result_t enResult; + + /* If hardware watchdog is active, error is returned. */ + if (TRUE == FM_HWWDT->WDG_CTL_f.INTEN) + { + enResult = ErrorOperationInProgress; + } + else + { + /* HW Watchdog Control Register unlock sequence */ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_2; + + /* Enable interrupt and count */ + FM_HWWDT->WDG_CTL_f.INTEN = TRUE; + + enResult = Ok; + } + + return (enResult); +} /* Hwwdg_Start */ + +/** + ****************************************************************************** + ** \brief Stop the Hardware Watchdog + ** + ******************************************************************************/ +void Hwwdg_Stop(void) +{ + if (TRUE == FM_HWWDT->WDG_CTL_f.INTEN) + { + /* HW Watchdog Control Register unlock sequence */ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_2; + + /* Disable interrupt and count */ + FM_HWWDT->WDG_CTL_f.INTEN = FALSE; + } +} /* Hwwdg_Stop */ + +/** + ****************************************************************************** + ** \brief Write the load value for Hardware Watchdog + ** + ** \param [in] u32LoadValue Load value + ** + ******************************************************************************/ +void Hwwdg_WriteWdgLoad(uint32_t u32LoadValue) +{ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; /* Release Lock */ + FM_HWWDT->WDG_LDR = u32LoadValue; /* Write load value */ +} /* Hwwdg_WriteWdgLoad */ + +/** + ****************************************************************************** + ** \brief Read the count value for Hardware Watchdog + ** + ** \retval uint32_t:Value of value register + ** + ******************************************************************************/ +uint32_t Hwwdg_ReadWdgValue(void) +{ + return (FM_HWWDT->WDG_VLR); +} /* Hwwdg_ReadWdgValue */ + +/** + ****************************************************************************** + ** \brief Feed Hardware Watchdog (Call function) + ** + ** This function feeds the Hardware Watchdog with the unlock, feed, and lock + ** sequence. Take care of the arbitrary values, because there are not checked + ** for plausibility! + ** + ** \param [in] u8ClearPattern1 Pattern of arbitrary value + ** \param [in] u8ClearPattern2 Inverted arbitrary value + ** + ******************************************************************************/ +void Hwwdg_Feed(uint8_t u8ClearPattern1, + uint8_t u8ClearPattern2 + ) +{ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1; /* Release Lock */ + FM_HWWDT->WDG_ICL = u8ClearPattern1; /* Clear possible interrupt and reload value, step 1 */ + FM_HWWDT->WDG_ICL = u8ClearPattern2; /* Clear possible interrupt and reload value, step 2 */ +} /* Hwwdg_Feed */ + +/** + ****************************************************************************** + ** \brief Enable Debug Break Watchdog Timer Control + ** + ******************************************************************************/ +void Hwwdg_EnableDbgBrkWdgCtl(void) +{ + stc_crg_dbwdt_ctl_field_t stcDBWDT_CTL; + + stcDBWDT_CTL = FM_CRG->DBWDT_CTL_f; + stcDBWDT_CTL.DPHWBE = TRUE; + FM_CRG->DBWDT_CTL_f = stcDBWDT_CTL; +} /* Hwwdt_EnableDbgBrkWdtCtl */ + +/** + ****************************************************************************** + ** \brief Disable Debug Break Watchdog Timer Control + ** + ******************************************************************************/ +void Hwwdg_DisableDbgBrkWdgCtl(void) +{ + stc_crg_dbwdt_ctl_field_t stcDBWDT_CTL; + + stcDBWDT_CTL = FM_CRG->DBWDT_CTL_f; + stcDBWDT_CTL.DPHWBE = FALSE; + FM_CRG->DBWDT_CTL_f = stcDBWDT_CTL; +} /* Hwwdt_DisableDbgBrkWdtCtl */ + +#endif /* #if (PDL_PERIPHERAL_ENABLE_HWWDG == PDL_ON) */ + +#endif /* #if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.h new file mode 100644 index 0000000000..8901d72c47 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/hwwdg.h @@ -0,0 +1,205 @@ +/******************************************************************************* +* \file hwwdg.h +* +* \version 1.20 +* +* \brief Headerfile for HWWDG functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __HWWDG_H__ +#define __HWWDG_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupHWWDG Hardware Watchdog Timer (HWWDG) +* \{ +* \defgroup GroupHWWDG_Macros Macros +* \defgroup GroupHWWDG_Functions Functions +* \defgroup GroupHWWDG_DataStructures Data Structures +* \defgroup GroupHWWDG_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupHWWDG +* \{ +* This document describes the hardware watchdog timer (HWWDG). The FM families +* also support a software watchdog timer.
+* A watchdog timer generates an interrupt or a system reset if the main program +* neglects to periodically “feed” the watchdog.
+* The hardware watchdog timer is a 32-bit down counter. If a program does not reload +* the watchdog timer within the specified interval time, it judges that a user program +* is out of control. When the timer underflows, it outputs an interrupt request to the CPU. +* If the interrupt request is not cleared, when the next underflow occurs the timer outputs a +* reset request.
+* The HWWDG timer is clocked by the built-in low-speed CR oscillator (CLKLC). If the clock is +* stopped, the timer stops. It retains its value and resumes the countdown when the clock restarts +* after returning from standby mode.
+* Unlike the software watchdog, the HWWDG does not support a windowed watchdog. +* \section SectionHWWDG_ConfigurationConsideration Configuration Consideration +* To set up the HWWDG, you provide configuration parameters in the stc_hwwdg_config_t structure, such as the timer value, whether +* to issue a reset, and the pointer to the interrupt callback function. Then call Hwwdg_Init().
+* To start the watchdog timer call Hwwdg_Start(). Use Hwwdg_Stop() if you want to stop the counter.
+* When the counter is running, you must call Hwwdg_Feed() or Hwwdg_QuickFeed().For example, you can +* feed the watchdog in your interrupt callback routine. These two functions perform the same task. +* However, Hwwdg_QuickFeed() is expanded inline for time-critical polling loops. Each function requires +* two parameters – an arbitrary number, and its inverse. The hardware circuit requires this pattern to +* clear the interrupt and reload the timer.
+* Hwwdg_DeInit() stops and disables the Hardware Watchdog. You must provide two “magic words” +* for this function to be successful. Check the documentation for this function call for those values. +* \note +* - The Hardware Watchdog shares its interrupt vector with the NMI. +* - The Hardware Watchdog is also switched off in System_Init() in +* system_fmx.c. Set the definition for HWWD_DISABLE to 0 in +* system_fmx.h to enable the Hardware Watchdog during +* start-up. +* +* \section SectionHWWDG_MoreInfo More Information +* For more information on the HWWDG peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupHWWDG_Macros +* \{ +*/ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +/* for WDG_LCK */ +#define HWWDG_REG_UNLOCK_1 (0x1ACCE551u) +#define HWWDG_REG_UNLOCK_2 (0xE5331AAEu) + +/** \} GroupHWWDG_Macros */ + +/** +* \addtogroup GroupHWWDG_DataStructures +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ***************************************************************************** + ** \brief Hardware Watchdog configuration + *****************************************************************************/ +typedef struct stc_hwwdg_config +{ + uint32_t u32LoadValue; ///< Timer interval + boolean_t bResetEnable; ///< TRUE: Enables Hardware watchdog reset + func_ptr_t pfnHwwdgIrqCb; ///< Pointer to hardware watchdog interrupt callback function + +} stc_hwwdg_config_t; + +/** \} GroupHWWDG_DataStructures */ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/** +* \addtogroup GroupHWWDG_Functions +* \{ +*/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* Interrupt */ +void HwwdgIrqHandler(void); + +/* Setup(Initialize)/Disable(Un-initialize) */ +en_result_t Hwwdg_Init(const stc_hwwdg_config_t* pstcConfig); +en_result_t Hwwdg_DeInit(uint32_t u32MagicWord1, + uint32_t u32MagicWord2 ); + +/* Start/Stop */ +en_result_t Hwwdg_Start(void); +void Hwwdg_Stop(void); + +/* Write/Read for counter */ +void Hwwdg_WriteWdgLoad(uint32_t u32LoadValue); +uint32_t Hwwdg_ReadWdgValue(void); + +/* Feed watchdog */ +void Hwwdg_Feed(uint8_t u8ClearPattern1, uint8_t u8ClearPattern2); + +void Hwwdg_EnableDbgBrkWdgCtl(void); +void Hwwdg_DisableDbgBrkWdgCtl(void); + +static void Hwwdg_QuickFeed(uint8_t u8ClearPattern1, uint8_t u8ClearPattern2); + +/******************************************************************************/ +/* Static inline functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Quickly feed Hardware Watchdog (inline function) + ** + ** This function feeds the Hardware Watchdog with the unlock, feed, and lock + ** sequence as an inline function for quick execution in polling loops. + ** Take care of the arbitrary values, because there are not checked for + ** plausibility! + ** + ** \param [in] u8ClearPattern1 Pattern of arbitrary value + ** \param [in] u8ClearPattern2 Inverted arbitrary value + ******************************************************************************/ +static __INLINE void Hwwdg_QuickFeed(uint8_t u8ClearPattern1, uint8_t u8ClearPattern2) +{ + FM_HWWDT->WDG_LCK = HWWDG_REG_UNLOCK_1;/* Release Lock */ + FM_HWWDT->WDG_ICL = u8ClearPattern1; /* Clear possible interrupt and reload value, step 1 */ + FM_HWWDT->WDG_ICL = u8ClearPattern2; /* Clear possible interrupt and reload value, step 2 */ +} /* Hwwdg_QuickFeed */ + +/** \} GroupHWWDG_Functions */ +/** \} GroupHWWDG */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) */ + +#endif /* __HWWDG_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.c new file mode 100644 index 0000000000..98f48ac056 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.c @@ -0,0 +1,332 @@ +/******************************************************************************* +* \file swwdg.c +* +* \version 1.20 +* +* \brief This file provides the source code to the API for the SWWDG +* driver. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "wdg/swwdg.h" + +#if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) + +#if (PDL_PERIPHERAL_ENABLE_SWWDG == PDL_ON) +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/* for WDOGLOAD */ +#define SWWDG_DEFAULT_VAL (0xFFFFFFFFu) + +/* for WDOGCONTROL */ +#define SWWDG_CTL_INTEN (0x01u) +#define SWWDG_CTL_RESEN (0x02u) +#define SWWDG_CTL_TWD100 (0x00u) +#define SWWDG_CTL_TWD75 (0x04u) +#define SWWDG_CTL_TWD50 (0x08u) +#define SWWDG_CTL_TWD25 (0x0Cu) +#define SWWDG_CTL_SPM (0x10u) + +/* for WDOGSPMC */ +#define SWWDG_SPMC_TGR (0x01u) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ +static func_ptr_t pfnSwwdgCallback; ///< callback function pointer for SW-Wdg Irq + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Software Watchdog Interrupt Handler + ******************************************************************************/ +void SwwdgIrqHandler(void) +{ + /* Check software interrupt status */ + if (TRUE == FM_SWWDT->WDOGRIS_f.RIS) + { + if (NULL != pfnSwwdgCallback) + { + pfnSwwdgCallback(); + } + } +} /* SwwdgIrqHandler */ + +/** + ****************************************************************************** + ** \brief Initialize Software Watchdog + ** + ** \param [in] pstcConfig Pointer to Software Watchdog configuration + ** + ** \retval Ok Setup successful + ** \retval ErrorInvalidParameter pstcConfig == NULL + ** + ** \note This function only initializes the Software Watchdog configuration. + ** If Swwdg_Start() is called, MCU start the Software Watchdog. + ** + ******************************************************************************/ +en_result_t Swwdg_Init(const stc_swwdg_config_t* pstcConfig) +{ + en_result_t enResult; + uint8_t u8WdogControl = 0u; /* Preset Watchdog Control Register */ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + uint8_t u8WdogSpmc = 0u; /* Preset Window Watchdog Control Register */ +#endif + enResult = ErrorInvalidParameter; + + /* Check for NULL Pointer */ + if (NULL != pstcConfig) + { + enResult = Ok; + /* Un Lock */ + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + /* Window watchdog mode */ + if (TRUE == pstcConfig->bWinWdgEnable) + { + /* Set SPM bit */ + u8WdogControl |= SWWDG_CTL_SPM; + /* Set reset enable when reload without timing window was occured */ + if (TRUE == pstcConfig->bWinWdgResetEnable) + { + u8WdogSpmc = SWWDG_SPMC_TGR; + } + /* Set timing window for window watchdog mode */ + switch (pstcConfig->u8TimingWindow) + { + case en_swwdg_timing_window_100: + u8WdogControl |= SWWDG_CTL_TWD100; + break; + case en_swwdg_timing_window_75: + u8WdogControl |= SWWDG_CTL_TWD75; + break; + case en_swwdg_timing_window_50: + u8WdogControl |= SWWDG_CTL_TWD50; + break; + case en_swwdg_timing_window_25: + u8WdogControl |= SWWDG_CTL_TWD25; + break; + default: + enResult = ErrorInvalidParameter; + break; + } + } + #endif + if (Ok == enResult) + { + /* Set reset enable */ + if (TRUE == pstcConfig->bResetEnable) + { + /* Set RESEN bit */ + u8WdogControl |= SWWDG_CTL_RESEN; + } + + // Set interval + FM_SWWDT->WDOGLOAD = pstcConfig->u32LoadValue; + #if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + FM_SWWDT->WDOGSPMC = u8WdogSpmc; /* Setup Window watchdog and */ + #endif + FM_SWWDT->WDOGCONTROL = u8WdogControl; /* Setup SW-Watchdog */ + FM_SWWDT->WDOGLOCK = 0u; /* Lock it! */ + + /* Initialize callback to NULL */ + pfnSwwdgCallback = pstcConfig->pfnSwwdgIrqCb; + + #if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + /* Enable NVIC */ + NVIC_ClearPendingIRQ(CSV_SWDT_LVD_IRQn); + NVIC_EnableIRQ(CSV_SWDT_LVD_IRQn); + NVIC_SetPriority(CSV_SWDT_LVD_IRQn, PDL_IRQ_LEVEL_CSV_SWDT_LVD); + #else + /* Enable NVIC */ + NVIC_ClearPendingIRQ(SWDT_IRQn); + NVIC_EnableIRQ(SWDT_IRQn); + NVIC_SetPriority(SWDT_IRQn, PDL_IRQ_LEVEL_SWWDG); + #endif + } + } + + return (enResult); +} /* Swwdg_Init */ + +/** + ****************************************************************************** + ** \brief Un-Initialize Software Watchdog + ** + ******************************************************************************/ +void Swwdg_DeInit(void) +{ +#if (PDL_MCU_TYPE == PDL_FM0P_TYPE3) + /* Disable NVIC */ + NVIC_ClearPendingIRQ(CSV_SWDT_LVD_IRQn); + NVIC_DisableIRQ(CSV_SWDT_LVD_IRQn); + NVIC_SetPriority(CSV_SWDT_LVD_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#else + /* Disable NVIC */ + NVIC_ClearPendingIRQ(SWDT_IRQn); + NVIC_DisableIRQ(SWDT_IRQn); + NVIC_SetPriority(SWDT_IRQn, PDL_DEFAULT_INTERRUPT_LEVEL); +#endif + + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; /* Un Lock */ + FM_SWWDT->WDOGCONTROL = 0u; /* Reset SW-Watchdog */ +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + FM_SWWDT->WDOGSPMC = 0u; /* Reset Window watchdog */ +#endif + FM_SWWDT->WDOGLOAD = SWWDG_DEFAULT_VAL; /* Set default value to load value */ + + pfnSwwdgCallback = NULL; /* Initialize callback to NULL */ +} /* Swwdg_DeInit */ + +/** + ****************************************************************************** + ** \brief Start the Software Watchdog + ** + ** \retval Ok Setup successful + ** \retval ErrorOperationInProgress Software Watchdog is active now + ** + ** \note Please initialize by calling Swwdt_Init() before executing this function. + ** + ******************************************************************************/ +en_result_t Swwdg_Start(void) +{ + en_result_t enResult; + + /* If software watchdog is active, error is returned. */ + if (TRUE == FM_SWWDT->WDOGCONTROL_f.INTEN) + { + enResult = ErrorOperationInProgress; + } + else + { + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; /* Un Lock */ + FM_SWWDT->WDOGCONTROL_f.INTEN = TRUE; /* Enable interrupt and count */ + FM_SWWDT->WDOGLOCK = 0u; /* Lock */ + + enResult = Ok; + } + + return (enResult); +} /* Swwdg_Start */ + +/** + ****************************************************************************** + ** \brief Stop the Software Watchdog + ** + ******************************************************************************/ +void Swwdg_Stop(void) +{ + if (TRUE == FM_SWWDT->WDOGCONTROL_f.INTEN) + { + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; /* Un Lock */ + FM_SWWDT->WDOGCONTROL_f.INTEN = FALSE; /* Disable interrupt and count */ + FM_SWWDT->WDOGLOCK = 0u; /* Lock */ + } +} /* Swwdg_Stop */ + +/** + ****************************************************************************** + ** \brief Write the load value for Software Watchdog + ** + ** \param [in] u32LoadValue Load value + ** + ******************************************************************************/ +void Swwdg_WriteWdgLoad(uint32_t u32LoadValue) +{ + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; /* Un Lock */ + FM_SWWDT->WDOGLOAD = u32LoadValue; /* Write the load value */ + FM_SWWDT->WDOGLOCK = 0u; /* Lock */ +} /* Swwdg_WriteWdgLoad */ + +/** + ****************************************************************************** + ** \brief Read the count value for Software Watchdog + ** + ** \retval uint32_t:Value of value register + ** + ******************************************************************************/ +uint32_t Swwdg_ReadWdgValue(void) +{ + return (FM_SWWDT->WDOGVALUE); +} /* Swwdg_ReadWdgValue */ + +/** + ****************************************************************************** + ** \brief Feed Software Watchdog (Call function) + ** + ** This function feeds the Software Watchdog with the unlock, feed, and lock + ** sequence. + ** + ******************************************************************************/ +void Swwdg_Feed(void) +{ + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; /* Release Lock */ + FM_SWWDT->WDOGINTCLR = 1u; /* Clear possible interrupt and reload value */ + FM_SWWDT->WDOGLOCK = 0u; /* Lock again it! */ +} /* Swwdg_Feed */ + +/** + ****************************************************************************** + ** \brief Enable Debug Break Watchdog Timer Control + ** + ******************************************************************************/ +void Swwdg_EnableDbgBrkWdgCtl(void) +{ + stc_crg_dbwdt_ctl_field_t stcDBWDT_CTL; + + stcDBWDT_CTL = FM_CRG->DBWDT_CTL_f; + stcDBWDT_CTL.DPSWBE = TRUE; + FM_CRG->DBWDT_CTL_f = stcDBWDT_CTL; +} /* Swwdt_EnableDbgBrkWdtCtl */ + +/** + ****************************************************************************** + ** \brief Disable Debug Break Watchdog Timer Control + ** + ******************************************************************************/ +void Swwdg_DisableDbgBrkWdgCtl(void) +{ + stc_crg_dbwdt_ctl_field_t stcDBWDT_CTL; + + stcDBWDT_CTL = FM_CRG->DBWDT_CTL_f; + stcDBWDT_CTL.DPSWBE = FALSE; + FM_CRG->DBWDT_CTL_f = stcDBWDT_CTL; +} /* Swwdt_DisableDbgBrkWdtCtl */ + +#endif /* #if (PDL_PERIPHERAL_ENABLE_SWWDG == PDL_ON) */ + +#endif /* #if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) */ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.h new file mode 100644 index 0000000000..46225c87b6 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/swwdg.h @@ -0,0 +1,224 @@ +/******************************************************************************* +* \file swwdg.h +* +* \version 1.20 +* +* \brief Headerfile for SWWDG functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __SWWDG_H__ +#define __SWWDG_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mcu.h" +#include "pdl_user.h" + +#if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** +* \defgroup GroupSWWDG Sofrware Watchdog Timer (SWWDG) +* \{ +* \defgroup GroupSWWDG_Macros Macros +* \defgroup GroupSWWDG_Functions Functions +* \defgroup GroupSWWDG_DataStructures Data Structures +* \defgroup GroupSWWDG_Types Enumerated Types +* \} +*/ + +/** +* \addtogroup GroupSWWDG +* \{ +* This document describes the software watchdog timer. +* The FM families also support a hardware watchdog timer. +* A watchdog timer generates an interrupt or a system reset if the main program neglects to periodically “feed” the watchdog. +* The software watchdog timer (SWWDG) is a 32-bit down counter. If a program does not reload the +* watchdog timer within the specified interval time, it judges +* that a user program is out of control. When the timer underflows, it outputs +* an interrupt request to CPU. If the interrupt request is not cleared, when the next underflow occurs the timer outputs a reset request.
+* The timer uses a divided APB bus clock. If the clock is stopped, the timer stops. +* It retains its value and resumes +* the countdown when the clock restarts after returning from +* standby mode.
+* The software watchdog timer also supports a windowed watchdog. This implements a +* further restriction upon feeding the watchdog, such that the feed must happen within a +* certain time window. If the reload happens outside the time window, an interrupt or reset +* request occurs.
+* +* \section SectionSWWDG_ConfigurationConsideration Configuration Consideration +* +* To set up the SWWDG, you provide configuration parameters in the stc_swwdg_config_t +* structure. Note that you can disable the reset request if you wish. You also provide a +* function pointer to the routine called by the watchdog interrupt.Then call Swwdg_Init().
+* To start the watchdog timer, call Swwdg_Start(). Use Swwdg_Stop() if you want to stop the counter.
+* When the counter is running, you must call Swwdg_Feed() or Swwdg_QuickFeed() regularly to reload the watchdog +* timer. These perform the same task. However, Swwdg_QuickFeed() +* is expanded inline for time-critical polling loops. For example, you might implement a separate dedicated +* interrupt callback function that feeds the watchdog at regular intervals.
+* +* To implement Window Watchdog Mode set the bWinWdgEnable parameter to TRUE. +* Specify the timing in u8TimingWindow. In Window Watchdog mode if the counter is +* reloaded outside the timing window the Software Watchdog timer issues an interrupt or +* reset. It also issues the interrupt or reset for an underflow.
+ +* \section SectionSWWDG_MoreInfo More Information +* For more information on the SWWDG peripheral, refer to:
+* FM0+ Peripheral Manual - Timer Subsystem TRM.pdf
+* FM4 Peripheral Manual - Timer Subsystem TRM.pdf
+* The Peripheral Manual is divided into several subsystems. Click the link to see:
+* all +* FM0+ Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+* all +* FM4 Family 32-Bit Microcontrollers Peripheral Manuals, and Errata Sheets
+*/ + +/** +* \addtogroup GroupSWWDG_Macros +* \{ +*/ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ +/* for WDOGLOCK */ +#define SWWDG_REG_UNLOCK (0x1ACCE551u) + +/** \} GroupSWWDG_Macros */ + +/** +* \addtogroup GroupSWWDG_Types +* \{ +*/ + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Software watchdog timing window settings + ******************************************************************************/ +typedef enum en_swwdg_timing_window +{ + en_swwdg_timing_window_100 = 0x00, ///< Reload can be executed at less than or equal to WDOGLOAD. + en_swwdg_timing_window_75 = 0x01, ///< Reload can be executed at less than or equal to 75% of WDOGLOAD. + en_swwdg_timing_window_50 = 0x02, ///< Reload can be executed at less than or equal to 50% of WDOGLOAD + en_swwdg_timing_window_25 = 0x03 ///< Reload can be executed at less than or equal to 25% of WDOGLOAD +} en_swwdg_timing_window_t; + +/** \} GroupSWWDG_Types */ + +/** +* \addtogroup GroupSWWDG_DataStructures +* \{ +*/ + +/** + ***************************************************************************** + ** \brief Software and Hardware Watchdog configuration + *****************************************************************************/ +typedef struct stc_swwdg_config +{ + uint32_t u32LoadValue; ///< Timer interval + boolean_t bResetEnable; ///< TRUE: Enables SW watchdog reset +#if (PDL_MCU_CORE == PDL_FM4_CORE) || (PDL_MCU_CORE == PDL_FM0P_CORE) + boolean_t bWinWdgEnable; ///< TRUE: Enables Window watchdog mode + boolean_t bWinWdgResetEnable; ///< TRUE: Enables reset when reload without timing window was occured. + ///< FALSE: Enables interrupt when reload without timing window was occured. + uint8_t u8TimingWindow; ///< Timing window setting, see description of #en_swwdg_timing_window_t +#endif + func_ptr_t pfnSwwdgIrqCb; ///< Pointer to interrupt callback funciton + +} stc_swwdg_config_t; + +/** \} GroupSWWDG_DataStructures */ + +/** +* \addtogroup GroupSWWDG_Functions +* \{ +*/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* Interrupt */ +void SwwdgIrqHandler(void); + +/* Setup(Initialize)/Disable(Un-initialize) */ +en_result_t Swwdg_Init(const stc_swwdg_config_t* pstcConfig); +void Swwdg_DeInit(void); + +/* Start/Stop */ +en_result_t Swwdg_Start(void); +void Swwdg_Stop(void); + +/* Write/Read for counter */ +void Swwdg_WriteWdgLoad(uint32_t u32LoadValue); +uint32_t Swwdg_ReadWdgValue(void); + +/* Feed watchdog */ +void Swwdg_Feed(void) ; +static void Swwdg_QuickFeed(void); + +/* Setting Debug Break Watchdog Timer Control */ +void Swwdg_EnableDbgBrkWdgCtl(void); +void Swwdg_DisableDbgBrkWdgCtl(void); + +/******************************************************************************/ +/* Static inline functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Quickly feed Software Watchdog (inline function) + ** + ** This function feeds the Software Watchdog with the unlock, feed, and lock + ** sequence as an inline function for quick execution in polling loops. + ******************************************************************************/ +static __INLINE void Swwdg_QuickFeed(void) +{ + FM_SWWDT->WDOGLOCK = SWWDG_REG_UNLOCK; /* Release Lock */ + FM_SWWDT->WDOGINTCLR = 1u; /* Clear possible interrupt and reload value */ + FM_SWWDT->WDOGLOCK = 0u; /* Lock again it! */ +} /* Swwdg_QuickFeed */ + +/** \} GroupSWWDG_Functions */ +/** \} GroupSWWDG */ + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_WDG_ACTIVE)) */ + +#endif /* __SWWDG_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/wdg.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/wdg.h new file mode 100644 index 0000000000..055003c265 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/driver/wdg/wdg.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* \file wdg.h +* +* \version 1.20 +* +* \brief Headerfile for WDG functions. +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ + +#ifndef __WDG_H__ +#define __WDG_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "hwwdg.h" +#include "swwdg.h" + +#endif /* __WDG_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.c new file mode 100644 index 0000000000..9baaf36bc7 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.c @@ -0,0 +1,4687 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file mfs_hl.c + ** + ** MFS High Level functions + ** + ** History: + ** - 2013-03-26 1.0 NT First version. + ** - 2014-05-26 1.1 EZ Return Error when receiving errors occurs in + ** Mfs_Hl_Read(). + ** Add a function to get the pointer of TX or RX + ** buffer. + ** - 2014-11-07 1.2 EZ Update the data transmission sequence in + ** Mfs_Hl_Csio_SynchronousTrans() + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mfs_hl.h" + +#if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) + +#if (PDL_MFS_USE_HL == PDL_ON) +/** + ****************************************************************************** + ** \addtogroup MfshlGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +/* for BGR */ +#define MFS_HL_RELOADVAL_MIN4UART (4u) +#define MFS_HL_RELOADVAL_MIN4CSIO (3u) +#define MFS_HL_RELOADVAL_MIN4LIN (3u) +#define MFS_HL_BGR_MASK (0x7FFFu) + +/* Number definition */ +#define MFS_HL_NUM_1 (1u) +#define MFS_HL_NUM_2 (2u) +#define MFS_HL_NUM_3 (3u) +#define MFS_HL_NUM_4 (4u) +#define MFS_HL_NUM_5 (5u) +#define MFS_HL_NUM_6 (6u) +#define MFS_HL_NUM_7 (7u) +#define MFS_HL_NUM_8 (8u) +#define MFS_HL_NUM_9 (9u) +#define MFS_HL_NUM_10 (10u) + +/* Mask data */ +#define MFS_HL_MASK_0 (0x01u) +#define MFS_HL_MASK_1 (0x02u) +#define MFS_HL_MASK_2 (0x04u) +#define MFS_HL_MASK_3 (0x08u) +#define MFS_HL_MASK_4 (0x10u) +#define MFS_HL_MASK_5 (0x20u) +#define MFS_HL_MASK_6 (0x40u) +#define MFS_HL_MASK_7 (0x80u) +#define MFS_HL_MASK_0_2 (0x07u) +#define MFS_HL_MASK_0_3 (0x0Fu) +#define MFS_HL_MASK_0_6 (0x7Fu) +#define MFS_HL_MASK_4_7 (0xF0u) + +#define MFS_HL_MASK_0_7 (0x000000FFu) +#define MFS_HL_MASK_8_15 (0x0000FF00u) +#define MFS_HL_MASK_16_23 (0x00FF0000u) +#define MFS_HL_MASK_24_31 (0xFF000000u) +#define MFS_HL_MASK_0_15 (0x0000FFFFu) +#define MFS_HL_MASK_16_31 (0xFFFF0000u) + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/// Look-up table for all enabled MFS_HL instances and their internal data +static stc_mfs_hl_instance_data_t m_astcMfsHlInstanceDataLut[MfsInstanceIndexMax] = +{ +#if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) + { + &MFS0, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) + { + &MFS1, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) + { + &MFS2, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) + { + &MFS3, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) + { + &MFS4, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) + { + &MFS5, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) + { + &MFS6, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) + { + &MFS7, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) + { + &MFS8, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) + { + &MFS9, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) + { + &MFS10, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) + { + &MFS11, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) + { + &MFS12, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) + { + &MFS13, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) + { + &MFS14, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +#if (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) + { + &MFS15, /* pstcInstance */ + {NULL} /* stcInternData (not initialized yet) */ + }, +#endif +}; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ +static stc_mfs_hl_intern_data_t* MfsHlGetInternDataPtr(volatile stc_mfsn_t* pstcMfs); + +static uint16_t MfsHlGetMin(uint16_t u16Num1, + uint16_t u16Num2 + ); + +static void MfsHlWriteBuf(volatile stc_mfsn_t* pstcMfs, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlIrqHandlerTx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ); + +static void MfsHlReadBuf(volatile stc_mfsn_t* pstcMfs, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlIrqHandlerRx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ); + +static void MfsHlIrqHandlerSts(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ); + +static void MfsHlFifoUseInit(volatile stc_mfsn_t* pstcMfs, + uint16_t u16BufFillLvl + ); + +static void MfsHlI2cDataTxMaster(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlI2cDataRxMaster(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlI2cPreStartSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlI2cDataRxSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlI2cDataTxSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static void MfsHlI2cIrqHandlerTx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ); + +static void MfsHlI2cIrqHandlerRx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ); + +static void MfsHlI2cIrqHandlerSts(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ); + +static en_result_t MfsHlI2cStartSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ); + +static en_result_t MfsHlI2cWaitIntState(volatile stc_mfs_hl_intern_data_t* pstcMfsHlInternData); + +static en_result_t MfsHlI2cChkTxRxComplete(stc_mfs_hl_intern_data_t* pstcMfsHlInternData, + uint32_t u32MaxCnt); + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Return the internal data for a certain MFS_HL instance. + ** + ** \param pstcMfs Pointer to MFS_HL instance + ** + ** \return Pointer to internal data or NULL if instance is not enabled (or not known) + ** + ******************************************************************************/ +static stc_mfs_hl_intern_data_t* MfsHlGetInternDataPtr(volatile stc_mfsn_t* pstcMfs) +{ + stc_mfs_hl_intern_data_t* pstcMfsInternDataPtr = NULL; + uint32_t u32Instance; + + if (NULL != pstcMfs) + { + for (u32Instance = 0u; u32Instance < (uint32_t)MfsInstanceIndexMax; u32Instance++) + { + if (pstcMfs == m_astcMfsHlInstanceDataLut[u32Instance].pstcInstance) + { + pstcMfsInternDataPtr = &m_astcMfsHlInstanceDataLut[u32Instance].stcInternData; + break; + } + } + } + + return (pstcMfsInternDataPtr); +} /* MfsHlGetInternDataPtr */ + +/** + ****************************************************************************** + ** \brief Get minimum number. + ** + ** \param [in] u16Num1 The number to compare to u16Num2 + ** \param [in] u16Num2 The number to compare to u16Num1 + ** + ** \return The smaller number as the result of comparing u16Num1 with u16Num2 + ** + ******************************************************************************/ +static uint16_t MfsHlGetMin(uint16_t u16Num1, + uint16_t u16Num2 + ) +{ + uint16_t u16Min; + + /* Return the smaller number as the result of comparing u16Num1 with u16Num2 */ + u16Min = u16Num2; + if (u16Num1 < u16Num2) + { + u16Min = u16Num1; + } + + return (u16Min); +} /* MfsHlGetMin */ + +/** + ****************************************************************************** + ** \brief Write the contents of the buffer to Transmit Data Register. + ** + ** The data from the internal Ring Buffer is put into the Fifo until there's + ** no more space left or all data has been transferred to the Fifo. + ** If the referenced MFS does not have a FIFO single data is put. + ** + ** \param [in] pstcMfs Pointer to MFS instance register area + ** \param [in,out] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlWriteBuf(volatile stc_mfsn_t* pstcMfs, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_hl_buffer_t* pstcBuffer; + uint32_t u32Data; + uint_fast16_t fu16Loop; + uint_fast16_t fu16Cnt; + + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Get # of Data to put into HW FIFO, whichever space is less */ + /* Temporary var only used to define the order of volatile accesses to */ + /* Get rid of the compiler warning */ + fu16Loop = (uint_fast16_t)MfsHlGetMin( pstcBuffer->u16FillCount, + (uint16_t)(MFS_FIFO_MAX_VAL - (pstcMfs->FBYTE1)) + ); + } + else + { + fu16Loop = MFS_HL_NUM_1; + } + + while (0u != fu16Loop) + { + u32Data = 0u; + if (MfsEightBits >= pstcMfsHlInternData->u8DataWidth) + { + fu16Cnt = MFS_HL_NUM_1; + } + else if (MfsSixteenBits >= pstcMfsHlInternData->u8DataWidth) + { + fu16Cnt = MFS_HL_NUM_2; + } + else if (MfsTwentyFourBits >= pstcMfsHlInternData->u8DataWidth) + { + fu16Cnt = MFS_HL_NUM_3; + } + else + { + fu16Cnt = MFS_HL_NUM_4; + } + while ((0u != fu16Cnt) && (0u != fu16Loop)) + { + u32Data <<= MFS_HL_NUM_8; + u32Data |= (uint32_t)(pstcBuffer->pu8Buffer[pstcBuffer->u16OutIndex]) & MFS_HL_MASK_0_7; + /* update tail */ + pstcBuffer->u16OutIndex = ((pstcBuffer->u16OutIndex + (uint16_t)MFS_HL_NUM_1) % (pstcBuffer->u16BufferSize)); + pstcBuffer->u16FillCount-- ; + pstcBuffer->u16TxCount-- ; + pstcBuffer->u16TxCounter++ ; + fu16Loop-- ; + fu16Cnt--; + } + if (MfsSixteenBits >= pstcMfsHlInternData->u8DataWidth) + { + /* Put data from Buffer into Transmit Data Register */ + pstcMfs->TDR = (uint16_t)u32Data; + } + else + { + /* Put data from Buffer into Transmit Data Register (upper 16 bits width) */ + pstcMfs->TDR32 = u32Data; + } + } /* while ( fu16Loop != 0 ) */ +} /* MfsHlWriteBuf */ + +/** + ****************************************************************************** + ** \brief MFS_HL transmit interrupt service routine. + ** + ** This Function is called on each Transmit Interrupt set by the MFS. + ** This highly depends on the Configuration of the INT Sources. + ** Interrupts might occur on TX Fifo empty, last bit has been shifted out, ... + ** The data from the internal Ring Buffer is put into the Fifo until there's + ** no more space left or all data has been transferred to the Fifo. + ** If the referenced MFS does not have a FIFO single data is put. + ** + ** In LIN mode this handler also checks for LIN Break detection. If it is + ** detected, possible reception errors are cleared, the reception register + ** (RDR) is flushed and (if not NULL) a dedicated callback function is called. + ** Afterwards the Function is left by return w/o any further transmission action. + ** + ******************************************************************************/ +static void MfsHlIrqHandlerTx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + uint8_t u8End = FALSE; + volatile uint16_t u16DummyData; + + pstcMfsHlInternData = (stc_mfs_hl_intern_data_t *)pvHandle; + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + + /* Wait TX bus idle (for CSIO timer mode) */ + if (MfsHlExecWaitTxBusIdle == pstcMfsHlInternData->u8Exec) + { + /* Disable TX Idle Interrupt */ + pstcMfs->SCR_f.TBIE = FALSE; + /* Disable serial timer */ + pstcMfs->SCR_f.TXE = FALSE; + pstcMfs->SACSR_f.TMRE = FALSE; + pstcMfs->SCR_f.TXE = TRUE; + if (NULL != pstcMfsHlInternData->pfnTransmitCbFunction) + { + /* Call transmit callback function. */ + pstcMfsHlInternData->pfnTransmitCbFunction(pstcBuffer->u16TxCounter); + } + /* Transmit is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + else + { + /* Write the contents of the buffer to Transmit Data Register */ + MfsHlWriteBuf(pstcMfs, pstcMfsHlInternData); + if (0u == pstcBuffer->u16FillCount) + { + u8End = TRUE; + } + + if (TRUE == u8End) + { + /* If no more bytes to sent: Disable transmission interrupt(s) */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Disable TX Fifo Interrupt */ + pstcMfs->FCR1_f.FTIE = FALSE; + } + else + { + /* Disable TX Interrupt */ + pstcMfs->SCR_f.TIE = FALSE; + } + + if (0u == pstcBuffer->u16TxCount) + { + /* CSIO timer mode */ + if (MfsHlModeCsioNormalMasterTimer == pstcMfsHlInternData->u8MfsMode) + { + /* Wait TX bus idle */ + pstcMfsHlInternData->u8Exec = MfsHlExecWaitTxBusIdle; + /* Enable TX Idle Interrupt */ + pstcMfs->SCR_f.TBIE = TRUE; + } + else + { + if (NULL != pstcMfsHlInternData->pfnTransmitCbFunction) + { + /* Call transmit callback function. */ + pstcMfsHlInternData->pfnTransmitCbFunction(pstcBuffer->u16TxCounter); + } + /* Transmit is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + } + } + } + +} /* MfsHlIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief Store received data into buffer. + ** + ** It stores the data from the FIFO into the internal Ring Buffer + ** If the referenced MFS does not have a FIFO single data is read. + ** + ** \param [in] pstcMfs Pointer to MFS instance register area + ** \param [in,out] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlReadBuf(volatile stc_mfsn_t* pstcMfs, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_hl_buffer_t* pstcRxBuffer; + volatile uint32_t u32Data; + uint8_t u8Cnt; + uint8_t u8Shift; + + /* Pointer to the receive buffer */ + pstcRxBuffer = &pstcMfsHlInternData->stcRxBuffer; + + if (MfsEightBits >= pstcMfsHlInternData->u8DataWidth) + { + u8Cnt = MFS_HL_NUM_1; + } + else if (MfsSixteenBits >= pstcMfsHlInternData->u8DataWidth) + { + u8Cnt = MFS_HL_NUM_2; + } + else if (MfsTwentyFourBits >= pstcMfsHlInternData->u8DataWidth) + { + u8Cnt = MFS_HL_NUM_3; + } + else + { + u8Cnt = MFS_HL_NUM_4; + } + u8Shift = 0u; + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Now read all available bytes from hardware FIFO (if available) to buffer */ + while (0u != pstcMfs->FBYTE2) + { + if (MfsSixteenBits >= pstcMfsHlInternData->u8DataWidth) + { + u32Data = (uint32_t)pstcMfs->RDR; + } + else + { + u32Data = pstcMfs->RDR32; + } + /* If there is empty space in RX buffer */ + if (pstcRxBuffer->u16FillCount < pstcRxBuffer->u16BufferSize) + { + while ((pstcRxBuffer->u16FillCount < pstcRxBuffer->u16BufferSize) && (0u != u8Cnt)) + { + u8Cnt--; + u32Data = u32Data >> (u8Shift * MFS_HL_NUM_8); + u8Shift++; + /* Read data from RX FIFO, store in RX buffer */ + pstcRxBuffer->pu8Buffer[pstcRxBuffer->u16InIndex] = (uint8_t)u32Data; + /* Increment in index */ + pstcRxBuffer->u16InIndex++; + if (pstcRxBuffer->u16InIndex == pstcRxBuffer->u16BufferSize) + { + pstcRxBuffer->u16InIndex = 0u; + } + /* Count bytes in RX-FIFO */ + pstcRxBuffer->u16FillCount++; + } + } + else + { + /* We still need to do a dummy read to clear pending interrupts */ + pstcRxBuffer->bOverflow = TRUE; + } + } + } + else + { + if (MfsSixteenBits >= pstcMfsHlInternData->u8DataWidth) + { + u32Data = (uint32_t)pstcMfs->RDR; + } + else + { + u32Data = pstcMfs->RDR32; + } + /* If there is empty space in RX buffer */ + if (pstcRxBuffer->u16FillCount < pstcRxBuffer->u16BufferSize) + { + while ((pstcRxBuffer->u16FillCount < pstcRxBuffer->u16BufferSize) && (0u != u8Cnt)) + { + u8Cnt--; + u32Data = u32Data >> (u8Shift * MFS_HL_NUM_8); + u8Shift++; + /* Read data from RX FIFO, store in RX buffer */ + pstcRxBuffer->pu8Buffer[pstcRxBuffer->u16InIndex] = (uint8_t)u32Data; + /* Increment in index */ + pstcRxBuffer->u16InIndex++; + if (pstcRxBuffer->u16InIndex == pstcRxBuffer->u16BufferSize) + { + pstcRxBuffer->u16InIndex = 0u; + } + /* Count bytes in RX-FIFO */ + pstcRxBuffer->u16FillCount++; + } + } + else + { + /* We still need to do a dummy read to clear pending interrupts */ + pstcRxBuffer->bOverflow = TRUE; + } + } +} /* MfsHlReadBuf */ + +/** + ****************************************************************************** + ** \brief MFS_HL receive interrupt service routine. + ** + ** This Function is called on each Receive Interrupt set by the MFS. It stores + ** the data from the FIFO into the internal Ring Buffer an triggers a callback + ** function if the specific Fill Level of the internal Ring Buffer is reached. + ** If the referenced MFS does not have a FIFO single data is read. + ** + ** In LIN mode this ISR also handles the LIN Break detection. + ** + ******************************************************************************/ +static void MfsHlIrqHandlerRx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcRxBuffer; + volatile uint8_t u8Ssr; + + pstcMfsHlInternData = (stc_mfs_hl_intern_data_t *)pvHandle; + + u8Ssr = pstcMfs->SSR; + /* Error is different each mode */ + switch (pstcMfsHlInternData->u8MfsMode & MFS_HL_MODE_GROUP_CHK) + { + /* UART */ + case MFS_HL_MODE_GROUP_UART: + /* Check Overrun/Framing/Parity error */ + u8Ssr &= MFS_UART_SSR_ERR; + break; + /* CSIO */ + case MFS_HL_MODE_GROUP_CSIO: + /* Check Overrun error */ + u8Ssr &= MFS_CSIO_SSR_ERR; + break; + /* LIN */ + case MFS_HL_MODE_GROUP_LIN: + /* Check Overrun/Framing error */ + u8Ssr &= MFS_LIN_SSR_ERR; + break; + default: + u8Ssr = 0u; + break; + } + /* Error */ + if(0u != u8Ssr) + { + /* Clear possible reception errors */ + pstcMfs->SSR_f.REC = TRUE; + } + + /* Store Received Data Register into buffer */ + MfsHlReadBuf(pstcMfs, pstcMfsHlInternData); + /* Check if receive callback function is valid. */ + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Pointer to the receive buffer */ + pstcRxBuffer = &pstcMfsHlInternData->stcRxBuffer; + if (pstcRxBuffer->u16FillCount >= pstcMfsHlInternData->u16RxCallbackBufFillLevel) + { + /* Call receive callback function. */ + pstcMfsHlInternData->pfnReceiveCbFunction(pstcRxBuffer->u16FillCount); + } + } +} /* MfsHlIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief MFS_HL status interrupt service routine. + ** + ** + ******************************************************************************/ +static void MfsHlIrqHandlerSts(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + volatile uint16_t u16DummyData; + + pstcMfsHlInternData = (stc_mfs_hl_intern_data_t *)pvHandle; + + /* LIN mode */ + if ((pstcMfs->SMR & MFS_SMR_MODEBITS_MASK) == MFS_SMR_LIN_MODE) + { + /* LIN break detected? */ + if (pstcMfs->SSR_f.LBD == 1) + { + u16DummyData = pstcMfs->RDR; + pstcMfs->SSR_f.LBD = FALSE; /* Clear LIN break detection */ + pstcMfs->SSR_f.REC = TRUE; /* Clear possible reception errors */ + + /* Break Callback if specified */ + if (NULL != pstcMfsHlInternData->pfnLinBreakCbFunction) + { + pstcMfsHlInternData->pfnLinBreakCbFunction(); + } + } + } + +} /* MfsHlIrqHandlerSts */ + +/** + ****************************************************************************** + ** \brief MFS_HL Initialize FIFO to use + ** + ** \param [in] pstcMfs Pointer to MFS instance register area + ** \param [in] u16BufFillLvl Filled count to interrupt + ** + ******************************************************************************/ +static void MfsHlFifoUseInit(volatile stc_mfsn_t* pstcMfs, + uint16_t u16BufFillLvl + ) +{ + stc_mfs_fcr0_field_t stcFCR0 = { 0 }; /* Preset to zero */ + stc_mfs_fcr1_field_t stcFCR1 = { 0 }; + + /* + * Local Fifo Control Register 0 variable + */ + + stcFCR0.FLD = FALSE; /* No reload (for transmission) */ + stcFCR0.FSET = FALSE; /* FIFO2 read pointer not saved */ + stcFCR0.FCL2 = TRUE; /* Reset FIFO2 */ + stcFCR0.FCL1 = TRUE; /* Reset FIFO1 */ + stcFCR0.FE2 = TRUE; /* Enable FIFO2 */ + stcFCR0.FE1 = TRUE; /* Enable FIFO1 */ + + /* + * Local Fifo Control Register 1 variable + */ + + /* No FIFO test (also not used for I2C) */ + stcFCR1.FTST0 = FALSE; + stcFCR1.FTST1 = FALSE; + + stcFCR1.FLSTE = FALSE; /* disable data lost detection */ + stcFCR1.FRIIE = FALSE; /* disable FIFO idle detection */ + stcFCR1.FDRQ = FALSE; /* no request for transmission FIFO data */ + stcFCR1.FTIE = FALSE; /* disable transmission FIFO interrupt */ + stcFCR1.FSEL = FALSE; /* FIFO1: transmission FIFO, FIFO2: reception FIFO */ + + /* Setup hardware */ + pstcMfs->FCR0_f = stcFCR0; + pstcMfs->FCR1_f = stcFCR1; + pstcMfs->FBYTE2 = (uint8_t)MfsHlGetMin(u16BufFillLvl, MFS_FIFO_MAX_VAL); +} /* MfsHlFifoUseInit */ + +/** + ****************************************************************************** + ** \brief MFS_HL Operation to send data for I2C master + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cDataTxMaster(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_hl_buffer_t* pstcBuffer; + uint16_t u16Num; + uint16_t u16Cnt; + stc_mfs_smr_field_t stcSMR; + stc_mfs_fcr1_field_t stcFCR1 = { 0 }; + stc_mfs_ssr_field_t stcSSR; + stc_mfs_i2c_ibsr_field_t stcIBSR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_ismk_field_t stcISMK; + + stcIBSR = pstcI2c->IBSR_f; + stcIBCR = pstcI2c->IBCR_f; + + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + + /* stop condition */ + if (TRUE == stcIBSR.SPC) + { + /* Clear stop condition interrupt */ + stcIBSR.SPC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + + /* stop condition interrupt disable */ + stcIBCR.CNDE = FALSE; + stcIBCR.ACT_SCC = FALSE; + pstcI2c->IBCR_f = stcIBCR; + + /* Clear IBSR:RACK */ + stcISMK = pstcI2c->ISMK_f; + stcISMK.EN = FALSE; + pstcI2c->ISMK_f = stcISMK; + + /* Restart */ + stcISMK.EN = TRUE; + pstcI2c->ISMK_f = stcISMK; + + if (NULL != pstcMfsHlInternData->pfnTransmitCbFunction) + { + /* Call transmit callback function. */ + pstcMfsHlInternData->pfnTransmitCbFunction(pstcBuffer->u16OutIndex); + } + /* Transmit is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + else if (((pstcBuffer->u16BufferSize == pstcBuffer->u16OutIndex) + && (TRUE == stcIBCR.INT)) + || (TRUE == stcIBSR.RACK)) + { + /* Disable master mode */ + stcIBCR.MSS = FALSE; + stcIBCR.ACT_SCC = FALSE; + /* Disable interrupt */ + stcIBCR.INTE = FALSE; + /* Clear interrupt */ + stcIBCR.INT = FALSE; + /* Enable stop condition interrupt */ + stcIBCR.CNDE = TRUE; + pstcI2c->IBCR_f = stcIBCR; + } + else + { + stcSSR = pstcI2c->SSR_f; + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + stcFCR1 = pstcI2c->FCR1_f; + } + if ((TRUE == stcSSR.TDRE) || (TRUE == stcFCR1.FDRQ)) + { + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + u16Num = MfsHlGetMin(((pstcBuffer->u16BufferSize) - (pstcBuffer->u16OutIndex)), + (uint16_t)(MFS_FIFO_MAX_VAL - (pstcI2c->FBYTE1)) + ); + for (u16Cnt = 0u; u16Cnt < u16Num; u16Cnt++) + { + pstcI2c->TDR = pstcBuffer->pu8Buffer[pstcBuffer->u16OutIndex]; + pstcBuffer->u16OutIndex += MFS_HL_NUM_1; + } + /* clear FIFO tx interrupt */ + stcFCR1 = pstcI2c->FCR1_f; + stcFCR1.FDRQ = FALSE; + if (pstcBuffer->u16BufferSize == pstcBuffer->u16OutIndex) + { + /* tx FIFO interrupt disable */ + stcFCR1.FTIE = FALSE; + } + pstcI2c->FCR1_f = stcFCR1; + } + else + { + /* tx data to register */ + pstcI2c->TDR = pstcBuffer->pu8Buffer[pstcBuffer->u16OutIndex]; + pstcBuffer->u16OutIndex += MFS_HL_NUM_1; + if (pstcBuffer->u16BufferSize == pstcBuffer->u16OutIndex) + { + /* tx interrupt disable */ + stcSMR = pstcI2c->SMR_f; + stcSMR.TIE = FALSE; + pstcI2c->SMR_f = stcSMR; + } + } + } + + /* clear interrupt */ + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; + } +} /* MfsHlI2cDataTxMaster */ + +/** + ****************************************************************************** + ** \brief MFS_HL Operation to receive data for I2C master + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cDataRxMaster(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_hl_buffer_t* pstcBuffer; + stc_mfs_ssr_field_t stcSSR; + stc_mfs_i2c_ibsr_field_t stcIBSR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_ismk_field_t stcISMK; + + stcIBSR = pstcI2c->IBSR_f; + stcIBCR = pstcI2c->IBCR_f; + stcSSR = pstcI2c->SSR_f; + + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcRxBuffer; + + /* stop condition */ + if (TRUE == stcIBSR.SPC) + { + /* Clear stop condition interrupt */ + stcIBSR.SPC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + + /* Disable stop condition interrupt */ + stcIBCR.CNDE = FALSE; + /* Disable interrupt */ + stcIBCR.INTE = FALSE; + + /* Clear IBSR:RACK */ + stcISMK = pstcI2c->ISMK_f; + stcISMK.EN = FALSE; + pstcI2c->ISMK_f = stcISMK; + + /* Restart */ + stcISMK.EN = TRUE; + pstcI2c->ISMK_f = stcISMK; + + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Call receive callback function. */ + pstcMfsHlInternData->pfnReceiveCbFunction(pstcBuffer->u16InIndex); + } + /* Receiving is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + /* Received data after second byte */ + else if ((TRUE == stcSSR.RDRF) && (FALSE == stcIBSR.FBT)) + { + /* Continue until specified data length is received */ + while (pstcBuffer->u16InIndex < pstcBuffer->u16BufferSize) + { + stcSSR = pstcI2c->SSR_f; + if (TRUE == stcSSR.RDRF) + { + pstcBuffer->pu8Buffer[pstcBuffer->u16InIndex] = (uint8_t)pstcI2c->RDR; + pstcBuffer->u16InIndex += MFS_HL_NUM_1; + } + else + { + /* No data */ + break; + } + } + /* Complete to receive */ + if (pstcBuffer->u16InIndex == pstcBuffer->u16BufferSize) + { + /* Stop condition */ + stcIBCR.MSS = FALSE; + /* NACK */ + stcIBCR.ACKE = FALSE; + /* stop condition interrupt enable */ + stcIBCR.CNDE = TRUE; + + /* If restart condition was detected */ + if (TRUE == stcIBSR.RSC) + { + /* Clear restart condition */ + stcIBSR.RSC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + } + } + } + /* Overrun error */ + else if (TRUE == stcSSR.ORE) + { + /* Clear RX error */ + stcSSR.REC = TRUE; + pstcI2c->SSR_f = stcSSR; + } + else + { + /* There is no process that should be executed. */ + } + + /* Clear interrupt */ + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; +} /* MfsHlI2cDataRxMaster */ + +/** + ****************************************************************************** + ** \brief MFS_HL Start operation for I2C slave + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cPreStartSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_smr_field_t stcSMR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_ibsr_field_t stcIBSR; + stc_mfs_i2c_ismk_field_t stcISMK; + uint8_t u8Data; + + stcIBCR = pstcI2c->IBCR_f; + stcIBSR = pstcI2c->IBSR_f; + /* Chk Slave Address Received */ + if ((FALSE == stcIBCR.MSS) && (TRUE == stcIBCR.ACT_SCC) && (TRUE == stcIBSR.FBT)) + { + stcSMR = pstcI2c->SMR_f; + /* Check direction */ + /* TX */ + if (TRUE == stcIBSR.TRX) + { + /* Callback for the I2C slave starting(TX) and get 1st data to send */ + if (NULL != pstcMfsHlInternData->pfnI2cSlvStCbFunction) + { + u8Data = pstcMfsHlInternData->pfnI2cSlvStCbFunction(MfsI2cWrite); + } + else + { + u8Data = 0x00u; + } + /* Send 1st data */ + pstcI2c->TDR = (uint16_t)u8Data; + /* Disable TX interrupt */ + stcSMR.TIE = FALSE; + stcIBCR.WSEL = FALSE; + } + /* RX */ + else + { + stcIBCR.ACKE = TRUE; + /* Disable RX interrupt */ + stcSMR.RIE = FALSE; + stcIBCR.WSEL = TRUE; + /* Callback for the I2C slave starting(RX) */ + if (NULL != pstcMfsHlInternData->pfnI2cSlvStCbFunction) + { + pstcMfsHlInternData->pfnI2cSlvStCbFunction(MfsI2cRead); + } + } + pstcI2c->SMR_f = stcSMR; + } + + /* Clear interrupt */ + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; +} /* MfsHlI2cPreStartSlave */ + +/** + ****************************************************************************** + ** \brief MFS_HL Operation to receive data for I2C slave + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cDataRxSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_hl_buffer_t* pstcBuffer; + stc_mfs_ssr_field_t stcSSR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_ibsr_field_t stcIBSR; + stc_mfs_i2c_ismk_field_t stcISMK; + + stcIBSR = pstcI2c->IBSR_f; + stcSSR = pstcI2c->SSR_f; + + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcRxBuffer; + + /* Stop condition */ + if (TRUE == stcIBSR.SPC) + { + /* Clear stop condition interrupt */ + stcIBSR.SPC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + + /* Clear IBSR:RACK */ + stcISMK = pstcI2c->ISMK_f; + stcISMK.EN = FALSE; + pstcI2c->ISMK_f = stcISMK; + + /* Restart */ + stcISMK.EN = TRUE; + pstcI2c->ISMK_f = stcISMK; + + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Call receive callback function. */ + pstcMfsHlInternData->pfnReceiveCbFunction(pstcBuffer->u16InIndex); + } + /* Receiving is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + /* Received NACK */ + else if (TRUE == stcIBSR.RACK) + { + /* Clear interrupt */ + stcIBCR = pstcI2c->IBCR_f; + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; + } + /* Received data */ + else + { + stcIBCR = pstcI2c->IBCR_f; + + if ((TRUE == stcSSR.RDRF) && (FALSE == stcIBSR.FBT)) + { + /* Continue until specified data length is received */ + while (pstcBuffer->u16InIndex < pstcBuffer->u16BufferSize) + { + stcSSR = pstcI2c->SSR_f; + if (TRUE == stcSSR.RDRF) + { + pstcBuffer->pu8Buffer[pstcBuffer->u16InIndex] = (uint8_t)pstcI2c->RDR; + pstcBuffer->u16InIndex += MFS_HL_NUM_1; + } + else + { + /* No data */ + break; + } + } + /* Complete to receive */ + if (pstcBuffer->u16InIndex == pstcBuffer->u16BufferSize) + { + /* Send NACK */ + stcIBCR.ACKE = FALSE; + } + else + { + /* Send ACK */ + stcIBCR.ACKE = TRUE; + } + } + /* Clear interrupt */ + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; + } + /* Overrun error */ + if (TRUE == stcSSR.ORE) + { + /* Clear RX error */ + stcSSR.REC = TRUE; + pstcI2c->SSR_f = stcSSR; + } +} /* MfsHlI2cDataRxSlave */ + +/** + ****************************************************************************** + ** \brief MFS_HL Operation to send data for I2C slave + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cDataTxSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + stc_mfs_hl_buffer_t* pstcBuffer; + stc_mfs_smr_field_t stcSMR; + stc_mfs_fcr1_field_t stcFCR1 = { 0 }; + stc_mfs_ssr_field_t stcSSR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_ibsr_field_t stcIBSR; + stc_mfs_i2c_ismk_field_t stcISMK; + uint16_t u16Num; + uint16_t u16Cnt; + + stcIBSR = pstcI2c->IBSR_f; + + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + + /* end of data or */ + if ((pstcBuffer->u16BufferSize == pstcBuffer->u16OutIndex) + /* Stop condition */ + || (TRUE == stcIBSR.SPC)) + { + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Disable TX FIFO interrupt */ + stcFCR1 = pstcI2c->FCR1_f; + stcFCR1.FTIE = FALSE; + pstcI2c->FCR1_f = stcFCR1; + } + /* FIFO is not used */ + else + { + /* Disable TX interrupt */ + stcSMR = pstcI2c->SMR_f; + stcSMR.TIE = FALSE; + pstcI2c->SMR_f = stcSMR; + } + /* Stop condition */ + if (TRUE == stcIBSR.SPC) + { + /* Clear IBSR:RACK */ + stcISMK = pstcI2c->ISMK_f; + stcISMK.EN = FALSE; + pstcI2c->ISMK_f = stcISMK; + + /* Restart */ + stcISMK.EN = TRUE; + pstcI2c->ISMK_f = stcISMK; + + /* Clear stop condition interrupt */ + stcIBSR.SPC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + + if (NULL != pstcMfsHlInternData->pfnTransmitCbFunction) + { + /* Call transmit callback function. */ + pstcMfsHlInternData->pfnTransmitCbFunction(pstcBuffer->u16OutIndex); + } + /* Transmit is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + + /* Clear interrupt */ + stcIBCR = pstcI2c->IBCR_f; + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; + + /* Clear RSC interrupt */ + stcIBSR.RSC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + } + else + { + stcSSR = pstcI2c->SSR_f; + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + stcFCR1 = pstcI2c->FCR1_f; + } + if ((TRUE == stcSSR.TDRE) || (TRUE == stcFCR1.FDRQ)) + { + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + u16Num = MfsHlGetMin(((pstcBuffer->u16BufferSize) - (pstcBuffer->u16OutIndex)), + (uint16_t)(MFS_FIFO_MAX_VAL - (pstcI2c->FBYTE1)) + ); + for (u16Cnt = 0u; u16Cnt < u16Num; u16Cnt++) + { + /* Set data to TX FIFO */ + pstcI2c->TDR = pstcBuffer->pu8Buffer[pstcBuffer->u16OutIndex]; + pstcBuffer->u16OutIndex++; + } + /* clear FIFO tx interrupt */ + stcFCR1 = pstcI2c->FCR1_f; + stcFCR1.FDRQ = FALSE; + pstcI2c->FCR1_f = stcFCR1; + } + /* FIFO is not used */ + else + { + /* Set data to TX FIFO */ + pstcI2c->TDR = pstcBuffer->pu8Buffer[pstcBuffer->u16OutIndex]; + pstcBuffer->u16OutIndex++; + } + } + /* Clear interrupt */ + stcIBCR = pstcI2c->IBCR_f; + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + pstcI2c->IBCR_f = stcIBCR; + /* Received NACK */ + if (TRUE == stcIBSR.RACK) + { + /* Clear RSC interrupt */ + stcIBSR.RSC = FALSE; + pstcI2c->IBSR_f = stcIBSR; + } + } +} /* MfsHlI2cDataTxSlave */ + +/** + ****************************************************************************** + ** \brief MFS_HL transmit interrupt service routine for I2C. + ** + ** This Function is called on Transmit Interrupt set by the I2C. + ** + ** \param [in] pstcMfs Pointer to I2C (MFS) instance register area + ** \param [in] pvHandle Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cIrqHandlerTx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + pstcMfsHlInternData = (stc_mfs_hl_intern_data_t *)pvHandle; + + /* I2C Master mode */ + if (MfsHlModeI2cMaster == pstcMfsHlInternData->u8MfsMode) + { + MfsHlI2cDataTxMaster(pstcMfs, pstcMfsHlInternData); + } + /* I2C Slave mode */ + else + { + MfsHlI2cDataTxSlave(pstcMfs, pstcMfsHlInternData); + } +} /* MfsHlI2cIrqHandlerTx */ + +/** + ****************************************************************************** + ** \brief MFS_HL receive interrupt service routine for I2C. + ** + ** This Function is called on Reception Interrupt set by the I2C. + ** + ** \param [in] pstcMfs Pointer to I2C (MFS) instance register area + ** \param [in] pvHandle Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cIrqHandlerRx(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + pstcMfsHlInternData = (stc_mfs_hl_intern_data_t *)pvHandle; + + /* I2C Master mode */ + if (MfsHlModeI2cMaster == pstcMfsHlInternData->u8MfsMode) + { + MfsHlI2cDataRxMaster(pstcMfs, pstcMfsHlInternData); + } + /* I2C Slave mode */ + else + { + /* If status is standby... */ + if (MfsHlExecStby == pstcMfsHlInternData->u8Exec) + { + MfsHlI2cPreStartSlave(pstcMfs, pstcMfsHlInternData); + } + else + { + MfsHlI2cDataRxSlave(pstcMfs, pstcMfsHlInternData); + } + } +} /* MfsHlI2cIrqHandlerRx */ + +/** + ****************************************************************************** + ** \brief MFS_HL status interrupt service routine for I2C. + ** + ** This Function is called on Status Interrupt set by the I2C. + ** + ** \param [in] pstcMfs Pointer to I2C (MFS) instance register area + ** \param [in] pvHandle Pointer to internal data + ** + ******************************************************************************/ +static void MfsHlI2cIrqHandlerSts(volatile stc_mfsn_t* pstcMfs, + void* pvHandle + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + pstcMfsHlInternData = (stc_mfs_hl_intern_data_t *)pvHandle; + + /* I2C Master mode */ + if (MfsHlModeI2cMaster == pstcMfsHlInternData->u8MfsMode) + { + /* Tramsmission */ + if (MfsHlExecTransmitting == pstcMfsHlInternData->u8Exec) + { + MfsHlI2cDataTxMaster(pstcMfs, pstcMfsHlInternData); + } + /* Reception */ + else + { + MfsHlI2cDataRxMaster(pstcMfs, pstcMfsHlInternData); + } + } + /* I2C Slave mode */ + else + { + switch (pstcMfsHlInternData->u8Exec) + { + /* Standby */ + case MfsHlExecStby: + MfsHlI2cPreStartSlave(pstcMfs, pstcMfsHlInternData); + break; + /* Receiving (after slave address was received) */ + case MfsHlExecReceiving: + MfsHlI2cDataRxSlave(pstcMfs, pstcMfsHlInternData); + break; + default: + MfsHlI2cDataTxSlave(pstcMfs, pstcMfsHlInternData); + break; + } + } +} /* MfsHlI2cIrqHandlerSts */ + +/** + ****************************************************************************** + ** \brief Initialize an MFS_HL module as UART mode. + ** This Function initialises the MFS according the UART setup in the passed + ** configuration structure. + ** Several checking are done before that and an error is returned if invalid + ** Modes are requested. + ** + ** \param [in] pstcUart Pointer to UART (MFS) instance register area + ** \param [in] pstcConfig MFS UART configuration + ** + ** \retval Ok Initializiation of MFS_HL module successfully + ** done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** - one or more values in pstcConfig out of range + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Uart_Init(volatile stc_mfsn_t* pstcUart, + stc_mfs_hl_uart_config_t* pstcConfig + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + uint32_t u32ReloadValue; + + /* Preset local register variables to zero */ + stc_mfs_smr_field_t stcSMR = { 0 }; + stc_mfs_scr_field_t stcSCR = { 0 }; + stc_mfs_escr_field_t stcESCR = { 0 }; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcUart); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* RX Callback Level must be set more than zero */ + if (1u > pstcConfig->u16RxCbBufFillLvl) + { + return (ErrorInvalidParameter); + } + + /* Get reload value */ + u32ReloadValue = Mfs_GetReloadValue(pstcConfig->u32DataRate); + /* For asynchronous communication, the reload value must be greater than */ + /* or equal to 4 because five times over-sampling is performed internally */ + if (MFS_HL_NUM_4 > u32ReloadValue) + { + return (ErrorInvalidParameter); + } + + /* Check buffer for UART */ + if (((NULL == pstcConfig->pu8TxBuf) + || (0u == pstcConfig->u16TxBufSize)) + || ((NULL == pstcConfig->pu8RxBuf) + || (0u == pstcConfig->u16RxBufSize)) + ) + { + return (ErrorInvalidParameter); + } + + /* First of all set MFS to Asynchronous mode 0 */ + pstcUart->SMR = 0u; + + /* Then we disable TX and RX for safe operation */ + pstcUart->SCR = 0u; + + /* Clear MFS by setting the Software Reset bit */ + pstcUart->SCR_f.UPCL = TRUE; + + /* Check the configration of FIFO usage */ + switch (pstcConfig->u8FifoUsage) + { + case MfsHlUseNoFifo: + case MfsHlUseFifo: + /* Set FIFO usage */ + pstcMfsHlInternData->u8FifoUsage = pstcConfig->u8FifoUsage; + break; + default: + return (ErrorInvalidParameter); + } + + /* ************ Register Settings ************ */ + /* + * Local Serial Mode Register variable + */ + + /* Operation Mode Selection */ + switch (pstcConfig->u8UartMode) + { + /* Normal mode */ + case MfsUartNormal: + stcSMR.MD = MFS_MD_UART_NORNAL; + break; + /* Multi-Processor mode */ + case MfsUartMulti: + stcSMR.MD = MFS_MD_UART_MULTI; + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + + /* Bit direction */ + if (TRUE == pstcConfig->bBitDirection) + { + stcSMR.BDS = TRUE; + } + else + { + stcSMR.BDS = FALSE; + } + + /* now setup hardware with correct mode first and then go on with */ + /* bit settings */ + pstcUart->SMR_f = stcSMR; + + /* Stop bit length 1 */ + switch (pstcConfig->u8StopBit) + { + case MfsOneStopBit: + case MfsThreeStopBits: + stcSMR.SBL = FALSE; + break; + case MfsTwoStopBits: + case MfsFourStopBits: + stcSMR.SBL = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + + /* Enable serial output */ + stcSMR.SOE = TRUE; + + /* now setup hardware (asynchronous) */ + pstcUart->SMR_f = stcSMR; + + /* + * Local Serial/I2C Control Register variable + */ + /* now setup hardware */ + pstcUart->SCR_f = stcSCR; + + /* + * Local Extended Serial Control Register variable + */ + /* Setup Parity 1 (Only in Normal mode available) */ + if (MfsUartNormal == pstcConfig->u8UartMode) + { + switch (pstcConfig->u8Parity) + { + case MfsParityNone: + stcESCR.P = FALSE; /* Parity type selection (0-even/1-odd) */ + stcESCR.PEN = FALSE; /* Parity disable */ + break; + case MfsParityEven: + stcESCR.P = FALSE; /* Parity type selection (0-even/1-odd) */ + stcESCR.PEN = TRUE; /* Parity Enable */ + break; + case MfsParityOdd: + stcESCR.P = TRUE; /* Parity type selection (0-even/1-odd) */ + stcESCR.PEN = TRUE; /* Parity Enable */ + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + } /* if (pstcConfig->enUartMode == MfsAsynchronous0) */ + + /* Stop bits */ + switch (pstcConfig->u8StopBit) + { + case MfsOneStopBit: + case MfsTwoStopBits: + stcESCR.ESBL = FALSE; + break; + case MfsThreeStopBits: + case MfsFourStopBits: + stcESCR.ESBL = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + + /* HW Flow */ + if (TRUE == pstcConfig->bHwFlow) + { + stcESCR.FLWEN = TRUE; + } + else + { + stcESCR.FLWEN = FALSE; + } + + /* NRZ / inverted NRZI */ + if (TRUE == pstcConfig->bSignalSystem) + { + stcESCR.INV = TRUE; + } + else + { + stcESCR.INV = FALSE; + } + + /* Caracter Length */ + switch (pstcConfig->u8CharLength) + { + case MfsFiveBits: + stcESCR.L = MFS_DATA_LEN_5; + break; + case MfsSixBits: + stcESCR.L = MFS_DATA_LEN_6; + break; + case MfsSevenBits: + stcESCR.L = MFS_DATA_LEN_7; + break; + case MfsEightBits: + stcESCR.L = MFS_DATA_LEN_8; + break; + case MfsNineBits: + stcESCR.L = MFS_DATA_LEN_9; + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + + /* now setup hardware */ + pstcUart->ESCR_f = stcESCR; + + /* + * Local Serial Status Register variable (USART) + */ + /* Clear possible reception errors */ + pstcUart->SSR_f.REC = TRUE; + + /* + * Local Fifo Control Register 0 variable + */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Initialize FIFO to use */ + MfsHlFifoUseInit(pstcUart, pstcConfig->u16RxCbBufFillLvl); + } + + /* Save RX Callback Buffer Fill Level (needed during servicing RX INT) */ + pstcMfsHlInternData->u16RxCallbackBufFillLevel = pstcConfig->u16RxCbBufFillLvl; + + /* Save character length */ + pstcMfsHlInternData->u8DataWidth = pstcConfig->u8CharLength; + + /* Set baud rate generation reload register */ + pstcUart->BGR = (uint16_t)(u32ReloadValue & MFS_HL_BGR_MASK); + + /* Set callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = pstcConfig->pfnTxCb; + pstcMfsHlInternData->pfnReceiveCbFunction = pstcConfig->pfnRxCb; + + /* Initialise TX ring buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = pstcConfig->pu8TxBuf; + pstcMfsHlInternData->stcTxBuffer.u16BufferSize = pstcConfig->u16TxBufSize; + pstcMfsHlInternData->stcTxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCounter = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* Initialise RX ring buffer */ + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = pstcConfig->pu8RxBuf; + pstcMfsHlInternData->stcRxBuffer.u16BufferSize = pstcConfig->u16RxBufSize; + pstcMfsHlInternData->stcRxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcRxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* MFS is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + + /* Operation Mode Selection */ + if (MfsUartNormal == pstcConfig->u8UartMode) + { + /* Normal mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeUartNormal; + } + else + { + /* Multi-Processor mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeUartMulti; + } + + /* Register interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcUart, MfsHlIrqHandlerTx); + (void)Mfs_SetRxIntCallBack(pstcUart, MfsHlIrqHandlerRx); + (void)Mfs_SetUpperLayerHandle(pstcUart, pstcMfsHlInternData); + + /* Enable receiver, transmitter */ + pstcUart->SCR_f.TXE = TRUE; + pstcUart->SCR_f.RXE = TRUE; + + /* Use interruption */ + if (NULL != pstcConfig->pfnRxCb) + { + /* Enable reception interrupt */ + pstcUart->SCR_f.RIE = TRUE; + } + + /* Init transmission interrupt */ + (void)Mfs_InitTxIrq(pstcUart); + /* Init reception interrupt */ + (void)Mfs_InitRxIrq(pstcUart); + + return (Ok); +} /* Mfs_Hl_Uart_Init */ + +/** + ****************************************************************************** + ** \brief UART deinitialisation of a MFS_HL module. + ** + ** This function de-initializes the MFS_HL module activating as UART. + ** This function uses for mode change or other changed settings. + ** + ** \param [in] pstcUart Pointer to UART (MFS) instance register area + ** + ** \retval Ok Deinitialisation of MFS_HL module successfully + ** done + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcUart == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Uart_DeInit(volatile stc_mfsn_t* pstcUart) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcUart); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + /* First of all disable receiver, transmitter and deinit interrupts */ + pstcUart->SCR_f.TXE = FALSE; + pstcUart->SCR_f.RXE = FALSE; + + (void)Mfs_DeInitIrq(pstcUart); /* returns always en_result_t Ok */ + + /* Baud Rate Generation Reload Reset */ + pstcUart->BGR = 0u; + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcUart->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcUart->SCR = 0u; + + /* Clear reception Errors */ + pstcUart->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcUart->SSR = 0u; + pstcUart->ESCR = 0u; + pstcUart->FCR0 = 0u; + pstcUart->FCR1 = 0u; + + /* Clear MFS by setting the Software Reset bit */ + pstcUart->SCR_f.UPCL = TRUE; + + /* Unregist interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcUart, NULL); + (void)Mfs_SetRxIntCallBack(pstcUart, NULL); + (void)Mfs_SetStsIntCallBack(pstcUart, NULL); + (void)Mfs_SetUpperLayerHandle(pstcUart, NULL); + + /* Reset Fifo buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = NULL; + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = NULL; + + /* Reset callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = NULL; + pstcMfsHlInternData->pfnReceiveCbFunction = NULL; + + /* Reset LIN Break Callback used for Mfs_Lin_DeInit() */ + pstcMfsHlInternData->pfnLinBreakCbFunction = NULL; + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + pstcMfsHlInternData->u8MfsMode = MfsHlModeStby; + + enResult = Ok; + } + + return (enResult); +} /* Mfs_Hl_Uart_DeInit */ + +/** + ****************************************************************************** + ** \brief Initialize an MFS_HL module as CSIO mode. + ** + ** This Function initialises the MFS according the CSIO setup in the passed + ** configuration structure. + ** Several checking are done before that and an error is returned if invalid + ** Modes are requested. + ** + ** \param [in] pstcCsio Pointer to CSIO (MFS) instance register area + ** \param [in] pstcConfig MFS CSIO configuration + ** + ** \retval Ok Initializiation of MFS_HL module successfully + ** done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** - one or more enumerated values in pstcUart out of enumaration + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Csio_Init(volatile stc_mfsn_t* pstcCsio, + stc_mfs_hl_csio_config_t* pstcConfig + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + uint32_t u32ReloadValue; + + /* Preset local register variables to zero */ + stc_mfs_smr_field_t stcSMR = { 0 }; + stc_mfs_scr_field_t stcSCR = { 0 }; + stc_mfs_escr_field_t stcESCR = { 0 }; + stc_mfs_ssr_field_t stcSSR = { 0 }; + stc_mfs_csio_sacsr_field_t stcSACSR = { 0 }; + stc_mfs_csio_scscr_field_t stcSCSCR = { 0 }; + uint16_t u16STMCR = 0u; + uint16_t u16SCSTR32 = 0u; + uint8_t u8SCSTR0 = 0u; + uint8_t u8SCSTR1 = 0u; + uint8_t u8TBYTE0 = 0u; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcCsio); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* RX Callback Level must be set somewhat ge zero (except I2C mode) */ + if (1 > pstcConfig->u16RxCbBufFillLvl) + { + return (ErrorInvalidParameter); + } + + /* Check buffer for CSIO */ + if (((NULL == pstcConfig->pu8TxBuf) + || (0u == pstcConfig->u16TxBufSize)) + || ((NULL == pstcConfig->pu8RxBuf) + || (0u == pstcConfig->u16RxBufSize)) + ) + { + return (ErrorInvalidParameter); + } + + /* Get reload value */ + u32ReloadValue = Mfs_GetReloadValue(pstcConfig->u32DataRate); + /* For synchronous communication, the reload value must be greater than */ + /* or equal to 3 because four times over-sampling is performed internally */ + if (MFS_HL_RELOADVAL_MIN4CSIO > u32ReloadValue) + { + return (ErrorInvalidParameter); + } + + /* First of all set MFS to Asynchronous mode 0 */ + pstcCsio->SMR = 0u; + + /* Then we disable TX and RX for safe operation */ + pstcCsio->SCR = 0u; + + /* Clear MFS by setting the Software Reset bit */ + pstcCsio->SCR_f.UPCL = TRUE; + + /* Check the configration of FIFO usage */ + switch (pstcConfig->u8FifoUsage) + { + case MfsHlUseNoFifo: + case MfsHlUseFifo: + /* Set FIFO usage */ + pstcMfsHlInternData->u8FifoUsage = pstcConfig->u8FifoUsage; + break; + default: + return (ErrorInvalidParameter); + } + + /* ************ Register Settings ************ */ + /* Local Serial Mode Register variable */ + + /* Operation Mode Selection */ + switch (pstcConfig->u8CsioMode) + { + /* Master mode */ + case MfsCsioMaster: + stcSCR.MS = FALSE; + break; + /* Slave mode */ + case MfsCsioSlave: + stcSCR.MS = TRUE; + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + + /* Set mode (CSIO) */ + stcSMR.MD = MFS_MD_CSIO; + + /* Active Mode Selection */ + switch (pstcConfig->u8CsioActMode) + { + /* Normal mode */ + case MfsCsioActNormalMode: + stcSCR.SPI = FALSE; + break; + /* SPI mode */ + case MfsCsioActSpiMode: + stcSCR.SPI = TRUE; + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + + /* Bit direction */ + if (TRUE == pstcConfig->bBitDirection) + { + stcSMR.BDS = TRUE; + } + else + { + stcSMR.BDS = FALSE; + } + + /* now setup hardware with correct mode first and then go on with */ + /* bit settings */ + pstcCsio->SMR_f = stcSMR; + + /* Set synchronous clock input/output according master/slave mode */ + if (MfsCsioMaster == pstcConfig->u8CsioMode) + { + /* Master:Clock output */ + stcSMR.SCKE = TRUE; + } + else + { + /* Slave:Clock input */ + stcSMR.SCKE = FALSE; + } + + /* Serial clock invert */ + if (TRUE == pstcConfig->bSignalSystem) + { + /* Mark level "LOW" */ + stcSMR.SCINV = TRUE; + } + else + { + /* Mark level "HIGH" */ + stcSMR.SCINV = FALSE; + } + + /* Enable serial output */ + stcSMR.SOE = TRUE; + + /* Wait time insertion */ + switch (pstcConfig->u8SyncWaitTime) + { + case MfsSyncWaitZero: + stcESCR.WT = MFS_WAIT_TIME_0BIT; + break; + case MfsSyncWaitOne: + stcESCR.WT = MFS_WAIT_TIME_1BIT; + break; + case MfsSyncWaitTwo: + stcESCR.WT = MFS_WAIT_TIME_2BITS; + break; + case MfsSyncWaitThree: + stcESCR.WT = MFS_WAIT_TIME_3BITS; + break; + default: + return (ErrorInvalidParameter); + } + + stcESCR.SOP = FALSE; + + stcESCR.L3 = FALSE; /* less than 13 bits */ + stcSSR.AWC = FALSE; /* 16bit access for RDR/TDR (less than or equal to 16 bits) */ + /* Caracter Length */ + switch (pstcConfig->u8CharLength) + { + case MfsFiveBits: + stcESCR.L = MFS_DATA_LEN_5; + break; + case MfsSixBits: + stcESCR.L = MFS_DATA_LEN_6; + break; + case MfsSevenBits: + stcESCR.L = MFS_DATA_LEN_7; + break; + case MfsEightBits: + stcESCR.L = MFS_DATA_LEN_8; + break; + case MfsNineBits: + stcESCR.L = MFS_DATA_LEN_9; + break; + case MfsTenBits: + stcESCR.L = MFS_DATA_LEN_10; + break; + case MfsElevenBits: + stcESCR.L = MFS_DATA_LEN_11; + break; + case MfsTwelveBits: + stcESCR.L = MFS_DATA_LEN_12; + break; + case MfsThirteenBits: + stcESCR.L = MFS_DATA_LEN_13; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case MfsFourteenBits: + stcESCR.L = MFS_DATA_LEN_14; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case MfsFifteenBits: + stcESCR.L = MFS_DATA_LEN_15; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case MfsSixteenBits: + stcESCR.L = MFS_DATA_LEN_16; + stcESCR.L3 = TRUE; /* More than 12 bits */ + break; + case MfsTwentyBits: + stcESCR.L = MFS_DATA_LEN_20; + stcESCR.L3 = TRUE; /* More than 12 bits */ + stcSSR.AWC = TRUE; /* 32bit access for RDR/TDR (more than 16 bits) */ + break; + case MfsTwentyFourBits: + stcESCR.L = MFS_DATA_LEN_24; + stcESCR.L3 = TRUE; /* More than 12 bits */ + stcSSR.AWC = TRUE; /* 32bit access for RDR/TDR (more than 16 bits) */ + break; + case MfsThirtyTwoBits: + stcESCR.L = MFS_DATA_LEN_32; + stcESCR.L3 = TRUE; /* More than 12 bits */ + stcSSR.AWC = TRUE; /* 32bit access for RDR/TDR (more than 16 bits) */ + break; + default: + return (ErrorInvalidParameter); + } + + /* now setup hardware (synchronous) */ + pstcCsio->SMR_f = stcSMR; + + /* now setup hardware */ + pstcCsio->SCR_f = stcSCR; + + /* now setup hardware */ + pstcCsio->ESCR_f = stcESCR; + pstcCsio->SSR_f = stcSSR; + + /* Local Serial Status Register variable (USART) */ + /* Clear possible reception errors */ + pstcCsio->SSR_f.REC = TRUE; + + /* Master mode */ + if (MfsCsioMaster == pstcConfig->u8CsioMode) + { + /* Normal mode */ + if (MfsCsioActNormalMode == pstcConfig->u8CsioActMode) + { + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioNormalMaster; + } + /* SPI mode */ + else + { + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioSpiMaster; + } + } + /* Slave mode */ + else + { + /* Normal mode */ + if (MfsCsioActNormalMode == pstcConfig->u8CsioActMode) + { + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioNormalSlave; + } + /* SPI mode */ + else + { + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioSpiSlave; + } + } + + /* SPI Chip select configration */ + if (NULL != pstcConfig->pstcMfsSpiCsConfig) + { + /* Chip select function sets when mode is master and SPI */ + if ((MfsCsioActSpiMode == pstcConfig->u8CsioActMode) + /* Chip select is available only ch.6 or 7. */ + && ((pstcCsio == &MFS6) || (pstcCsio == &MFS7)) + ) + { + /* Enable chip select */ + stcSCSCR.CSEN0 = TRUE; + if (MfsCsioMaster == pstcConfig->u8CsioMode) + { + /* Enable chip select output */ + stcSCSCR.CSOE = TRUE; + /* Set clock dividor for chip select activation */ + stcSCSCR.CDIV = pstcConfig->pstcMfsSpiCsConfig->u8CsDivision & MFS_HL_MASK_0_2; + /* Set chip de-select bit */ + u16SCSTR32 = pstcConfig->pstcMfsSpiCsConfig->u16CsDeSelect; + /* Set chip select setting delay */ + u8SCSTR0 = pstcConfig->pstcMfsSpiCsConfig->u8CsSetDelay; + /* Set chip select holding delay */ + u8SCSTR1 = pstcConfig->pstcMfsSpiCsConfig->u8CsHoldDelay; + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioSpiMasterWithCs; + } + else + { + /* Set chip select activation level */ + if (FALSE == pstcConfig->pstcMfsSpiCsConfig->bCsLevel) + { + /* In-active High (Active level low) */ + stcSCSCR.CSLVL = TRUE; + } + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioSpiSlaveWithCs; + } + /* now setup hardware */ + pstcCsio->SCSCR_f = stcSCSCR; + pstcCsio->SCSTR32 = u16SCSTR32; + pstcCsio->SCSTR0 = u8SCSTR0; + pstcCsio->SCSTR1 = u8SCSTR1; + } + } + /* Timer mode configration */ + else if (NULL != pstcConfig->pstcMfsTimerConfig) + { + /* Serial timer settings (master only) */ + if ((0u != pstcConfig->pstcMfsTimerConfig->u16SerialTimer) + && (MfsCsioMaster == pstcConfig->u8CsioMode)) + { + /* Set serial timer */ + u16STMCR = pstcConfig->pstcMfsTimerConfig->u16SerialTimer; + /* Set serial timer dividor */ + stcSACSR.TDIV = pstcConfig->pstcMfsTimerConfig->u8TimerDivision & MFS_HL_MASK_0_3; + /* Synchronous transfer with serial timer */ + if (TRUE == pstcConfig->pstcMfsTimerConfig->bTimerSyncEnable) + { + /* Enable synchronous transfer */ + stcSACSR.TSYNE = TRUE; + u8TBYTE0 = pstcConfig->pstcMfsTimerConfig->u8TxByte; + } + /* now setup hardware */ + pstcCsio->SACSR_f = stcSACSR; + pstcCsio->STMCR = u16STMCR; + pstcCsio->TBYTE0 = u8TBYTE0; + /* CSIO timer mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeCsioNormalMasterTimer; + } + } + else + { + /* There is no process that should be executed. */ + } + + /* Local Fifo Control Register 0 variable */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Initialize FIFO to use */ + MfsHlFifoUseInit(pstcCsio, pstcConfig->u16RxCbBufFillLvl); + } + + /* Save RX Callback Buffer Fill Level (needed during servicing RX INT) */ + pstcMfsHlInternData->u16RxCallbackBufFillLevel = pstcConfig->u16RxCbBufFillLvl; + + /* Save character length */ + pstcMfsHlInternData->u8DataWidth = pstcConfig->u8CharLength; + + /* Set baud rate generation reload register */ + pstcCsio->BGR = (uint16_t)(u32ReloadValue & MFS_HL_BGR_MASK); + + /* Set callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = pstcConfig->pfnTxCb; + pstcMfsHlInternData->pfnReceiveCbFunction = pstcConfig->pfnRxCb; + + /* Initialise TX ring buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = pstcConfig->pu8TxBuf; + pstcMfsHlInternData->stcTxBuffer.u16BufferSize = pstcConfig->u16TxBufSize; + pstcMfsHlInternData->stcTxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCounter = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* Initialise RX ring buffer */ + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = pstcConfig->pu8RxBuf; + pstcMfsHlInternData->stcRxBuffer.u16BufferSize = pstcConfig->u16RxBufSize; + pstcMfsHlInternData->stcRxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcRxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* MFS is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + + /* Register interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcCsio, MfsHlIrqHandlerTx); + (void)Mfs_SetRxIntCallBack(pstcCsio, MfsHlIrqHandlerRx); + (void)Mfs_SetStsIntCallBack(pstcCsio, MfsHlIrqHandlerSts); + (void)Mfs_SetUpperLayerHandle(pstcCsio, pstcMfsHlInternData); + + /* Enable receiver, transmitter */ + pstcCsio->SCR_f.TXE = TRUE; + pstcCsio->SCR_f.RXE = TRUE; + + /* Use interruption */ + if (NULL != pstcConfig->pfnRxCb) + { + /* Enable reception interrupt */ + pstcCsio->SCR_f.RIE = TRUE; + } + + /* Init transmission interrupt */ + (void)Mfs_InitTxIrq(pstcCsio); + /* Init reception interrupt */ + (void)Mfs_InitRxIrq(pstcCsio); + + return (Ok); +} /* Mfs_Hl_Csio_Init */ + +/** + ****************************************************************************** + ** \brief CSIO deinitialisation of a MFS_HL module. + ** + ** This function de-initializes the MFS_HL module activating as CSIO. + ** This function uses for mode change or other changed settings. + ** + ** \param [in] pstcCsio Pointer to CSIO (MFS) instance register area + ** + ** \retval Ok Deinitialisation of MFS_HL module successfully + ** done + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Csio_DeInit(volatile stc_mfsn_t* pstcCsio) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcCsio); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + /* First of all disable receiver, transmitter and deinit interrupts */ + pstcCsio->SCR_f.TXE = FALSE; + pstcCsio->SCR_f.RXE = FALSE; + + (void)Mfs_DeInitIrq(pstcCsio); /* returns always en_result_t Ok */ + + /* Baud Rate Generation Reload Reset */ + pstcCsio->BGR = 0u; + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcCsio->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcCsio->SCR = 0u; + + /* Clear reception Errors */ + pstcCsio->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcCsio->SSR = 0u; + pstcCsio->ESCR = 0u; + pstcCsio->FCR0 = 0u; + pstcCsio->FCR1 = 0u; + pstcCsio->SACSR = 0u; + pstcCsio->SCSCR = 0u; + pstcCsio->STMCR = 0u; + pstcCsio->SCSTR10 = 0u; + pstcCsio->SCSTR32 = 0u; + pstcCsio->TBYTE0 = 0u; + + /* Clear MFS by setting the Software Reset bit */ + pstcCsio->SCR_f.UPCL = TRUE; + + /* Unregist interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcCsio, NULL); + (void)Mfs_SetRxIntCallBack(pstcCsio, NULL); + (void)Mfs_SetStsIntCallBack(pstcCsio, NULL); + (void)Mfs_SetUpperLayerHandle(pstcCsio, NULL); + + /* Reset Fifo buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = NULL; + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = NULL; + + /* Reset callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = NULL; + pstcMfsHlInternData->pfnReceiveCbFunction = NULL; + + /* Reset LIN Break Callback used for Mfs_Lin_DeInit() */ + pstcMfsHlInternData->pfnLinBreakCbFunction = NULL; + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + pstcMfsHlInternData->u8MfsMode = MfsHlModeStby; + + enResult = Ok; + } + + return (enResult); +} /* Mfs_Hl_Csio_DeInit */ + +/** + ****************************************************************************** + ** \brief Simultaneously transmit and receive data as CSIO master + ** + ** This function will transmit and receive the same amount of data, based on + ** the serial (shift) clock signal (MFS SCK pin) in synchronous master or + ** slave mode. The operation mode of the MFS instance must be setup for + ** synchronous master or slave mode. + ** + ** While the data in Mfs_Hl_Csio_SynchronousTrans#pu8TxData is transmitted the + ** input data is received and stored in Mfs_Hl_Csio_SynchronousTrans#pu8RxData. + ** The function operates in CSIO (blocking) mode + ** only i.e. it will wait until the amount of data defined by + ** Mfs_Hl_Csio_SynchronousTrans#u16TransferSize + ** is transmitted/received. No MFS internal buffers or transfer counters + ** are used. + ** The TX/RX callback functions will not be called. + ** Note, that in synchronous slave mode, the transfer is controlled by + ** the external master device, providing the serial shift clock. This may + ** cause this function to block very long time. + ** + ** Because this function uses blocking method, no interrupts are needed and + ** therfore are not used. Also no FIFO operation is performed. + ** + ** \note Synchronous (non-blocking) TX/RX operations are provided by using + ** the functions Mfs_Hl_Write() and Mfs_Hl_Read() for MFS CSIO master + ** and slave modes, too. Note, that these functions do not support + ** full-duplex operation! + ** This function can use only if character length was set to less or + ** equal to eight bits. + ** Mfs_Hl_Csio_SynchronousTrans#pu8TxData and + ** Mfs_Hl_Csio_SynchronousTrans#pu8RxData can be set NULL, but either + ** should be set except NULL. + ** If only Mfs_Hl_Csio_SynchronousTrans#pu8TxData is set NULL, + ** dummy data is sent and the received data is stored in the buffer + ** shown by Mfs_Hl_Csio_SynchronousTrans#pu8RxData. + ** If only Mfs_Hl_Csio_SynchronousTrans#pu8RxData is set NULL, the data + ** of the buffer shown by Mfs_Hl_Csio_SynchronousTrans#pu8TxData is + ** transmitted and the received data is thrown away. + ** + ** \param [in] pstcCsio Pointer to CSIO (MFS) instance register area + ** \param [in] pu8TxData Pointer to transmit data buffer, can be NULL. + ** \param [in,out] pu8RxData Pointer to receive data buffer, can be NULL. + ** \param [in] u16TransferSize Transmit size (Must be at least 1) + ** \param [in] bCsHolding Specify to hold chip select + ** + ** \retval Ok Transfer done successfully. + ** \retval ErrorInvalidParameter If any of following conditions are met: + ** - pstcCsio == NULL + ** - pu8TxData == NULL or pu8RxData == NULL + ** - u16TransferSize == 0 + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorOperationInProgress A transmission is still pending or + ** the RX buffer is not empty. + ** \retval ErrorInvalidMode MFS_HL module was not initalised in MFS + ** CSIO mode. + ** \retval Error Character length is over 8 bits. + ** +******************************************************************************/ +en_result_t Mfs_Hl_Csio_SynchronousTrans(volatile stc_mfsn_t* pstcCsio, + const uint8_t* pu8TxData, + uint8_t* pu8RxData, + uint16_t u16TransferSize, + boolean_t bCsHolding + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData ; + uint16_t u16DataToSendCounter; + uint16_t u16DataReceivedCounter; + uint8_t u8Data; + volatile uint8_t u8Reg; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcCsio); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || ((NULL == pu8TxData) && (NULL == pu8RxData)) + /* Check for 0 < transmission length */ + || (0u == u16TransferSize) + ) + { + return (ErrorInvalidParameter); + } + + /* check for valid mode (only sync mode allowed) */ + if (MFS_MD_CSIO != pstcCsio->SMR_f.MD) + { + return (ErrorInvalidMode); + } + + /* This function can use when character length is set less or equel to 8 bits. */ + if (MfsEightBits < pstcMfsHlInternData->u8DataWidth) + { + return (Error); + } + + switch (pstcMfsHlInternData->u8MfsMode) + { + /* Set tx bytes when chip select is used on master mode */ + case MfsHlModeCsioSpiMasterWithCs: + if (MFS_CSIO_TBYTE_MAX < u16TransferSize) + { + return (ErrorInvalidParameter); + } + pstcCsio->SCR_f.TXE = FALSE; + /* Set size to active chip select */ + pstcCsio->TBYTE0 = (uint8_t)u16TransferSize; + if (TRUE == bCsHolding) + { + /* Hold chip select */ + pstcCsio->SCSCR_f.SCAM = TRUE; + } + else + { + /* In-active chip select when transmit is end */ + pstcCsio->SCSCR_f.SCAM = FALSE; + } + pstcCsio->SCR_f.TXE = TRUE; + break; + + /* CSIO timer mode */ + case MfsHlModeCsioNormalMasterTimer: + /* Enable serial timer */ + pstcCsio->SCR_f.TXE = FALSE; + pstcCsio->SACSR_f.TMRE = TRUE; + pstcCsio->SCR_f.TXE = TRUE; + break; + + default: + break; + } + + /* Use interruption */ + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Disable reception interrupt during sending and receiving data */ + pstcCsio->SCR_f.RIE = FALSE; + } + + u16DataToSendCounter = 0u; + u16DataReceivedCounter = 0u; + + while (u16DataReceivedCounter != u16TransferSize) + { + /* Wait for TDR empty */ + while(FALSE == pstcCsio->SSR_f.TDRE) + { + PDL_WAIT_LOOP_HOOK(); + } + /* If pu8TxData is NULL, dummy data is sent. */ + u8Data = 0u; + if (NULL != pu8TxData) + { + u8Data = pu8TxData[u16DataToSendCounter]; + } + /* Send data */ + pstcCsio->TDR = (uint16_t)u8Data; + u16DataToSendCounter++; + + do + { + /* Check reception */ + u8Reg = pstcCsio->SSR; + /* wait for reception finsihed */ + } while (0u == (u8Reg & MFS_SSR_RDRF)); + /* Check Overrun error */ + if (0u != (u8Reg & MFS_CSIO_SSR_ERR)) + { + pstcCsio->SSR_f.REC = TRUE; /* Clear possible reception errors */ + } + /* If pu8RxData is NULL, dummy data is received. */ + u8Data = (uint8_t)pstcCsio->RDR; + if (NULL != pu8RxData) + { + pu8RxData[u16DataReceivedCounter] = u8Data; + } + u16DataReceivedCounter++; + } + + /* CSIO timer mode */ + if (MfsHlModeCsioNormalMasterTimer == pstcMfsHlInternData->u8MfsMode) + { + /* Wait for TX bus idle */ + while (FALSE == pstcCsio->SSR_f.TBI) + { + /* Disable serial timer */ + pstcCsio->SCR_f.TXE = FALSE; + pstcCsio->SACSR_f.TMRE = FALSE; + pstcCsio->SCR_f.TXE = TRUE; + } + } + + /* Use interruption */ + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Enable reception interrupt */ + pstcCsio->SCR_f.RIE = TRUE; + } + + return (Ok); +} /* Mfs_Hl_Csio_SynchronousTrans */ + +/** + ****************************************************************************** + ** \brief Initialize an MFS_HL module as LIN mode. + ** + ** This Function initialises the MFS according the LIN setup in the passed + ** configuration structure. + ** Several checking are done before that and an error is returned if invalid + ** Modes are requested. + ** + ** \param [in] pstcLin Pointer to LIN (MFS) instance register area + ** \param [in] pstcConfig MFS LIN configuration + ** + ** \retval Ok Initializiation of MFS_HL module successfully + ** done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcCsio == NULL + ** - pstcConfig == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** - one or more enumerated values in pstcUart out of enumaration + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Lin_Init(volatile stc_mfsn_t* pstcLin, + stc_mfs_hl_lin_config_t* pstcConfig + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + uint32_t u32ReloadValue; + + /* Preset local register variables to zero */ + stc_mfs_smr_field_t stcSMR = { 0 }; + stc_mfs_scr_field_t stcSCR = { 0 }; + stc_mfs_escr_field_t stcESCR = { 0 }; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcLin); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* Get reload value */ + u32ReloadValue = Mfs_GetReloadValue(pstcConfig->u32DataRate); + /* For asynchronous communication, the reload value must be greater than */ + /* or equal to 3 because five times over-sampling is performed internally */ + if (MFS_HL_RELOADVAL_MIN4LIN > u32ReloadValue) + { + return (ErrorInvalidParameter); + } + + /* Check buffer for LIN */ + if (((NULL == pstcConfig->pu8TxBuf) + || (0u == pstcConfig->u16TxBufSize)) + || ((NULL == pstcConfig->pu8RxBuf) + || (0u == pstcConfig->u16RxBufSize))) + { + return (ErrorInvalidParameter); + } + + /* Check the configration of FIFO usage */ + switch (pstcConfig->u8FifoUsage) + { + case MfsHlUseNoFifo: + case MfsHlUseFifo: + /* Set FIFO usage */ + pstcMfsHlInternData->u8FifoUsage = pstcConfig->u8FifoUsage; + break; + default: + return (ErrorInvalidParameter); + } + + /* First of all set MFS to Asynchronous mode 0 */ + pstcLin->SMR = 0u; + + /* Then we disable TX and RX for safe operation */ + pstcLin->SCR = 0u; + + /* Clear MFS by setting the Software Reset bit */ + pstcLin->SCR_f.UPCL = TRUE; + + /* Set LIN mode to HW and preset variable */ + stcSMR.MD = MFS_MD_LIN; + + /* Serial output */ + stcSMR.SOE = TRUE; + + /* Operation Mode Selection */ + switch (pstcConfig->u8LinMode) + { + /* Master */ + case MfsLinMaster: + stcSCR.MS = FALSE; + break; + /* Slave */ + case MfsLinSlave: + stcSCR.MS = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + + /* Set LIN master configuration */ + if (MfsLinMaster == pstcConfig->u8LinMode) + { + /* Stop bits configration */ + switch (pstcConfig->u8StopBits) + { + case MfsLinOneStopBit: + stcSMR.SBL = FALSE; + stcESCR.ESBL = FALSE; + break; + case MfsLinTwoStopBits: + stcSMR.SBL = TRUE; + stcESCR.ESBL = FALSE; + break; + case MfsLinThreeStopBits: + stcSMR.SBL = FALSE; + stcESCR.ESBL = TRUE; + break; + case MfsLinFourStopBits: + stcSMR.SBL = TRUE; + stcESCR.ESBL = TRUE; + break; + default: + return (ErrorInvalidParameter); + } + /* Break length configration */ + switch (pstcConfig->u8BreakLength) + { + case MfsLinBreakLength13: + stcESCR.LBL = MFS_LIN_BREAK_13BITS; + break; + case MfsLinBreakLength14: + stcESCR.LBL = MFS_LIN_BREAK_14BITS; + break; + case MfsLinBreakLength15: + stcESCR.LBL = MFS_LIN_BREAK_15BITS; + break; + case MfsLinBreakLength16: + stcESCR.LBL = MFS_LIN_BREAK_16BITS; + break; + default: + return (ErrorInvalidParameter); + } + /* Delimiter length configration */ + switch (pstcConfig->u8DelimiterLength) + { + case MfsLinDelimiterLength1: + stcESCR.DEL = MFS_LIN_DELIMITER_1BIT; + break; + case MfsLinDelimiterLength2: + stcESCR.DEL = MFS_LIN_DELIMITER_2BITS; + break; + case MfsLinDelimiterLength3: + stcESCR.DEL = MFS_LIN_DELIMITER_3BITS; + break; + case MfsLinDelimiterLength4: + stcESCR.DEL = MFS_LIN_DELIMITER_4BITS; + break; + default: + return (ErrorInvalidParameter); + } + } + + /* Lin break interrupt */ + if (TRUE == pstcConfig->bLinBreakIrqEnable) + { + stcESCR.LBIE = TRUE; + } + else + { + stcESCR.LBIE = FALSE; + } + + /* Local Fifo Control Register 0 variable */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Initialize FIFO to use */ + MfsHlFifoUseInit(pstcLin, MFS_RX_FIFO_MIN_VAL); + } + + /* Save RX Callback Buffer Fill Level (needed during servicing RX INT) */ + pstcMfsHlInternData->u16RxCallbackBufFillLevel = MFS_RX_FIFO_MIN_VAL; + + /* Save character length (Only 8bits) */ + pstcMfsHlInternData->u8DataWidth = MfsEightBits; + + /* Set baud rate generation reload register */ + pstcLin->BGR = (uint16_t)(u32ReloadValue & MFS_HL_BGR_MASK); + + /* Set callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = pstcConfig->pfnTxCb; + pstcMfsHlInternData->pfnReceiveCbFunction = pstcConfig->pfnRxCb; + pstcMfsHlInternData->pfnLinBreakCbFunction = pstcConfig->pfnLinBrkCb; + + /* Initialise TX ring buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = pstcConfig->pu8TxBuf; + pstcMfsHlInternData->stcTxBuffer.u16BufferSize = pstcConfig->u16TxBufSize; + pstcMfsHlInternData->stcTxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCounter = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* Initialise RX ring buffer */ + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = pstcConfig->pu8RxBuf; + pstcMfsHlInternData->stcRxBuffer.u16BufferSize = pstcConfig->u16RxBufSize; + pstcMfsHlInternData->stcRxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcRxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* MFS is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + + /* Operation Mode Selection */ + if (MfsLinMaster == pstcConfig->u8LinMode) + { + /* Master mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeLinMaster; + } + else + { + /* Slave mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeLinSlave; + } + + + /* Register interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcLin, MfsHlIrqHandlerTx); + (void)Mfs_SetRxIntCallBack(pstcLin, MfsHlIrqHandlerRx); + (void)Mfs_SetStsIntCallBack(pstcLin, MfsHlIrqHandlerSts); + (void)Mfs_SetUpperLayerHandle(pstcLin, pstcMfsHlInternData); + + /* Setup hardware */ + pstcLin->SMR_f = stcSMR; + pstcLin->SCR_f = stcSCR; + pstcLin->ESCR_f = stcESCR; + + /* Enable receiver, transmitter */ + pstcLin->SCR_f.TXE = TRUE; + pstcLin->SCR_f.RXE = TRUE; + + /* Use interruption */ + if (NULL != pstcConfig->pfnRxCb) + { + /* Enable reception interrupt */ + pstcLin->SCR_f.RIE = TRUE; + } + + /* Init transmission interrupt */ + (void)Mfs_InitTxIrq(pstcLin); + /* Init reception interrupt */ + (void)Mfs_InitRxIrq(pstcLin); + + return (Ok); +} /* Mfs_Hl_Lin_Init */ + +/** + ****************************************************************************** + ** \brief LIN deinitialisation of a MFS_HL module. + ** + ** This function de-initializes the MFS_HL module activating as LIN. + ** This function uses for mode change or other changed settings. + ** + ** \param [in] pstcLin Pointer to LIN (MFS) instance register area + ** + ** \retval Ok LIN Deinitialisation of MFS_HL module + ** successfully done + ** \retval ErrorInvalidMode MFS not in LIN mode + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMfs == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Lin_DeInit(volatile stc_mfsn_t* pstcLin) +{ + en_result_t enResult; + + /* Check correct LIN master mode */ + if (MFS_SMR_LIN_MODE != (pstcLin->SMR & MFS_SMR_MODEBITS_MASK)) + { + enResult = ErrorInvalidMode; + } + else + { + enResult = Mfs_Hl_Uart_DeInit(pstcLin); + } + + return (enResult); +} /* Mfs_Hl_Lin_DeInit */ + +/** + ****************************************************************************** + ** \brief Set LIN Break with an MFS_HL module in LIN Master Mode + ** + ** \note MFS_HL module must be initialized to LIN Master mode + ** + ** This Function sets a LIN break and break delimiter length with the + ** configuration by the previous initialization. + ** + ** \param [in] pstcLin Pointer to LIN (MFS) instance register area + ** + ** \retval Ok LIN Break is (being) generated + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorInvalidMode MFS not in LIN master mode + ** \retval ErrorOperationInProgress MFS not ready for generating break + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Lin_SetBreak(volatile stc_mfsn_t* pstcLin) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcLin); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + + /* Check correct LIN master mode */ + else if ((MFS_SMR_LIN_MODE != (pstcLin->SMR & MFS_SMR_MODEBITS_MASK)) + || (TRUE == pstcLin->SCR_f.MS) ) + { + enResult = ErrorInvalidMode; + } + + /* Check if transmission bus is free (no transmission ongoing) */ + else if (FALSE == pstcLin->SSR_f.TBI) + { + enResult = ErrorOperationInProgress; + } + + else + { + /* Finally generate LIN break with configured length and delimiter */ + pstcLin->SCR_f.LBR = TRUE; + enResult = Ok; + } + + return (enResult); +} /* Mfs_Hl_Lin_SetBreak */ + +/** + ****************************************************************************** + ** \brief Set new baud divisor (NOT Baud Rate!) in LIN Slave Mode + ** + ** \pre MFS_HL module must be initialized to LIN Slave mode + ** + ** This Function sets a new (calculated) baud divisor, if the MFS is in LIN + ** Slave mode. + ** + ** \note This function should only be called: + ** - After a complete LIN frame was received and before next LIN Break + ** - Shortly after the second ICU interrupt within the LIN Synch Field + ** and before the next start bit of the LIN Header byte! + ** + ** \param [in] pstcLin Pointer to LIN (MFS) instance register area + ** \param [in] u16BaudDivisor New (calculated) Baud Divisor + ** + ** \retval Ok Baud rate was set correctly + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorInvalidMode MFS not in LIN slave mode + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Lin_SetNewBaudDivisor(volatile stc_mfsn_t* pstcLin, + uint16_t u16BaudDivisor + ) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcLin); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + + /* Check correct LIN slave mode */ + else if ((MFS_SMR_LIN_MODE != (pstcLin->SMR & MFS_SMR_MODEBITS_MASK)) + || (FALSE == pstcLin->SCR_f.MS) ) + { + enResult = ErrorInvalidMode; + } + + else + { + /* Update Baud Rate register */ + pstcLin->BGR = u16BaudDivisor; + enResult = Ok; + } + + return (enResult); +} /* Mfs_Hl_Lin_SetNewBaudDivisor */ + +/** + ****************************************************************************** + ** \brief Transfers n bytes of recent receive buffer to user buffer + ** + ** \param [in] pstcLin Pointer to MFS instance register area + ** \param [in,out] pu8Data Pointer to data buffer + ** \param [in] u16ReadCount Number of bytes to be transfered + ** + ** \retval Ok Process is success + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - pu8Data == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Lin_TransferRxBuffer(volatile stc_mfsn_t* pstcLin, + uint8_t* pu8Data, + uint16_t u16ReadCount) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + uint16_t u16Count; + int32_t i32BufferCount; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcLin); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pu8Data) + ) + { + enResult = ErrorInvalidParameter; + } + + else + { + enResult = Ok; + /* Check if nothing to do */ + if (0u != u16ReadCount) + { + /* Calculate internal buffer index */ + i32BufferCount = (int32_t)(pstcMfsHlInternData->stcRxBuffer.u16InIndex) - (int32_t)(u16ReadCount); + + /* Adjust ring buffer index? */ + if (0 > i32BufferCount) + { + i32BufferCount += (int32_t)pstcMfsHlInternData->stcRxBuffer.u16BufferSize; + } + + for (u16Count = 0u; u16Count < u16ReadCount; u16Count++) + { + pu8Data[u16Count] = pstcMfsHlInternData->stcRxBuffer.pu8Buffer[i32BufferCount]; + i32BufferCount++; + + if (i32BufferCount > (int32_t)pstcMfsHlInternData->stcRxBuffer.u16BufferSize) + { + i32BufferCount = 0; + } + } + } + } + + return (enResult); +} /* Mfs_Hl_Lin_TransferRxBuffer */ + +/** + ****************************************************************************** + ** \brief Disable reception interrupt for LIN mode + ** + ** \retval Ok Baud rate was set correctly + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcLin == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Lin_DisableRxInterrupt(volatile stc_mfsn_t* pstcLin) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcLin); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + + else + { + pstcLin->SCR_f.RIE = FALSE; + enResult = Ok; + } + + return (enResult); +} /* Mfs_Hl_Lin_DisableRxInterrupt */ + +/** + ****************************************************************************** + ** \brief Initialize an MFS_HL module as I2C mode. + ** This Function initialises the MFS according the I2C setup in the + ** passed Config Struct. Several Checkings are done before that and an error + ** is returned if invalid Modes are requested. + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcConfig MFS I2C configuration + ** + ** \retval Ok Initializiation of MFS_HL module successfully + ** done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pstcConfig == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** - one or more enumerated values in pstcUart out of enumaration + ** \retval ErrorUninitialized If bus clock is over specification, NFCR can't + ** set properly. So this function returned this + ** error code. + ** + ******************************************************************************/ +en_result_t Mfs_Hl_I2c_Init(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_i2c_config_t* pstcConfig + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + uint32_t u32ReloadValue; + uint32_t u32BusClock; + + /* Preset local register variables to zero */ + stc_mfs_smr_field_t stcSMR = { 0 }; + stc_mfs_i2c_ibcr_field_t stcIBCR = { 0 }; + stc_mfs_i2c_isba_field_t stcISBA = { 0 }; + stc_mfs_i2c_ismk_field_t stcISMK = { 0 }; + uint8_t u8NFCR = 0; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcI2c); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pstcConfig) + ) + { + return (ErrorInvalidParameter); + } + + /* Get reload value */ + u32ReloadValue = Mfs_I2c_GetReloadValue(pstcConfig->u32DataRate); + /* For asynchronous communication, the reload value must be greater than 0 */ + /* because reload counter is stop */ + if (0u == u32ReloadValue) + { + return (ErrorInvalidParameter); + } + + /* Check the configration of FIFO usage */ + switch (pstcConfig->u8FifoUsage) + { + case MfsHlUseNoFifo: + case MfsHlUseFifo: + /* Set FIFO usage */ + pstcMfsHlInternData->u8FifoUsage = pstcConfig->u8FifoUsage; + break; + default: + return (ErrorInvalidParameter); + } + + /* ************ Register Settings ************ */ + /* Local Serial Mode Register variable */ + + /* Operation Mode Selection */ + switch (pstcConfig->u8I2cMode) + { + /* I2C master mode */ + case MfsI2cMaster: + /* I2C slave mode */ + case MfsI2cSlave: + stcSMR.MD = MFS_MD_I2C; + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + + /* Noize filter settings according to the APB2 bus clock */ + u32BusClock = Mfs_GetBusClock(); + if (MFS_CLOCK_40M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess40M; + } + else if (MFS_CLOCK_60M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess60M; + } + else if (MFS_CLOCK_80M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess80M; + } + else if (MFS_CLOCK_100M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess100M; + } + else if (MFS_CLOCK_120M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess120M; + } + else if (MFS_CLOCK_140M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess140M; + } + else if (MFS_CLOCK_160M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess160M; + } + else if (MFS_CLOCK_180M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess180M; + } + else if (MFS_CLOCK_200M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess200M; + } + else if (MFS_CLOCK_220M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess220M; + } + else if (MFS_CLOCK_240M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess240M; + } + else if (MFS_CLOCK_260M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess260M; + } + else if (MFS_CLOCK_280M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess280M; + } + else if (MFS_CLOCK_300M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess300M; + } + else if (MFS_CLOCK_320M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess320M; + } + else if (MFS_CLOCK_340M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess340M; + } + else if (MFS_CLOCK_360M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess360M; + } + else if (MFS_CLOCK_380M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess380M; + } + else if (MFS_CLOCK_400M > u32BusClock) + { + u8NFCR = MfsI2cNoizeFilterLess400M; + } + else + { + return (ErrorUninitialized); + } + + /* Fast mode selection */ + if ((pstcI2c == MFS_I2C_FAST_MODE_PLUS_CH_A) + || (pstcI2c == MFS_I2C_FAST_MODE_PLUS_CH_B) + ) + { + switch (pstcConfig->u8FastMode) + { + /* Standard-mode */ + case MfsI2cDisableFastModePlus: + if (pstcI2c == MFS_I2C_FAST_MODE_PLUS_CH_A) + { + FM4_GPIO->EPFR16_f.SFMPAC = FALSE; + } + else + { + FM4_GPIO->EPFR16_f.SFMPBC = FALSE; + } + break; + /* Fast-mode Plus */ + case MfsI2cEnableFastModePlus: + if (pstcI2c == MFS_I2C_FAST_MODE_PLUS_CH_A) + { + FM4_GPIO->EPFR16_f.SFMPAC = TRUE; + } + else + { + FM4_GPIO->EPFR16_f.SFMPBC = TRUE; + } + break; + default: + return (ErrorInvalidParameter); /* should never see the daylight */ + } + } + + /* Ack enable */ + stcIBCR.ACKE = TRUE; + + /* Slave mode */ + if (MfsI2cSlave == pstcConfig->u8I2cMode) + { + /* Enable stop condition interrupt */ + stcIBCR.CNDE = TRUE; + /* Enable interrupt */ + stcIBCR.INTE = TRUE; + /* Set slave address */ + stcISBA.SA = pstcConfig->u8SlvAddr; + /* Enable slave address detection */ + stcISBA.SAEN = TRUE; + } + + /* Enable I2C, Enable bit comparing */ + stcISMK.SM = MFS_HL_MASK_0_6; + stcISMK.EN = TRUE; + + /* now setup hardware with correct mode first and then go on with */ + /* bit settings */ + pstcI2c->SMR_f = stcSMR; + + /* I2C disable before other registers are set. */ + pstcI2c->ISMK = 0u; + + /* Local Fifo Control Register 0 variable */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Initialize FIFO to use */ + MfsHlFifoUseInit(pstcI2c, MFS_FIFO_MAX_VAL); + } + + /* Save RX Callback Buffer Fill Level (needed during servicing RX INT) */ + pstcMfsHlInternData->u16RxCallbackBufFillLevel = 0u; + + /* Save character length */ + pstcMfsHlInternData->u8DataWidth = MfsEightBits; + + /* Clear callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = pstcConfig->pfnTxCb; + pstcMfsHlInternData->pfnReceiveCbFunction = pstcConfig->pfnRxCb; + + /* Initialise TX ring buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = NULL; + pstcMfsHlInternData->stcTxBuffer.u16BufferSize = 0u; + pstcMfsHlInternData->stcTxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcTxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCounter = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.u16TxCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcTxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* Initialise RX ring buffer */ + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = NULL; + pstcMfsHlInternData->stcRxBuffer.u16BufferSize = 0u; + pstcMfsHlInternData->stcRxBuffer.u16InIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16OutIndex = 0u; /* Reset Index */ + pstcMfsHlInternData->stcRxBuffer.u16FillCount = 0u; /* Reset Counter */ + pstcMfsHlInternData->stcRxBuffer.bOverflow = 0u; /* Reset Flag */ + + /* MFS is standby */ + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + + /* Operation Mode Selection */ + if (MfsI2cMaster == pstcConfig->u8I2cMode) + { + /* Master mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeI2cMaster; + /* Clear the starting slave callback function. */ + pstcMfsHlInternData->pfnI2cSlvStCbFunction = NULL; + } + else + { + /* Slave mode */ + pstcMfsHlInternData->u8MfsMode = MfsHlModeI2cSlave; + /* Set the starting slave callback function. */ + pstcMfsHlInternData->pfnI2cSlvStCbFunction = pstcConfig->pfnI2cSlvStCb; + } + + /* Register interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcI2c, MfsHlI2cIrqHandlerTx); + (void)Mfs_SetRxIntCallBack(pstcI2c, MfsHlI2cIrqHandlerRx); + (void)Mfs_SetStsIntCallBack(pstcI2c, MfsHlI2cIrqHandlerSts); + (void)Mfs_SetUpperLayerHandle(pstcI2c, pstcMfsHlInternData); + + /* Set baud rate generation reload register */ + pstcI2c->BGR = (uint16_t)(u32ReloadValue & MFS_HL_BGR_MASK); + + pstcI2c->NFCR = u8NFCR; + + pstcI2c->IBCR_f = stcIBCR; + pstcI2c->ISBA_f = stcISBA; + pstcI2c->ISMK_f = stcISMK; + + /* Init transmission interrupt */ + (void)Mfs_InitTxIrq(pstcI2c); + /* Init reception interrupt */ + (void)Mfs_InitRxIrq(pstcI2c); + + return (Ok); +} /* Mfs_Hl_I2c_Init */ + +/** + ****************************************************************************** + ** \brief I2C deinitialisation of a MFS_HL module. + ** + ** All used mfs register are reset to their default values. + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** + ** \retval Ok Deinitialisation of MFS_HL module successfully + ** done + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pstcMfsInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_I2c_DeInit(volatile stc_mfsn_t* pstcI2c) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointer and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcI2c); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + else + { + /* Disable I2C */ + pstcI2c->ISMK_f.EN = FALSE; + + (void)Mfs_DeInitIrq(pstcI2c); /* returns always en_result_t Ok */ + + /* Serial Mode Register clear all bits (valid in any mode) */ + pstcI2c->SMR = 0u; + + /* Reset Mfs receive and transmit bit to default */ + /* and clear all error flags */ + pstcI2c->IBCR = 0u; + + /* Clear reception Errors */ + pstcI2c->SSR_f.REC = TRUE; + + /* Reset all other used register to default value */ + pstcI2c->SSR = 0u; + pstcI2c->IBSR = 0u; + pstcI2c->FCR0 = 0u; + pstcI2c->FCR1 = 0u; + pstcI2c->NFCR = 0u; + + /* Unregist interrupt handler and internal handle */ + (void)Mfs_SetTxIntCallBack(pstcI2c, NULL); + (void)Mfs_SetRxIntCallBack(pstcI2c, NULL); + (void)Mfs_SetStsIntCallBack(pstcI2c, NULL); + (void)Mfs_SetUpperLayerHandle(pstcI2c, NULL); + + /* Reset Fifo buffer */ + pstcMfsHlInternData->stcTxBuffer.pu8Buffer = NULL; + pstcMfsHlInternData->stcRxBuffer.pu8Buffer = NULL; + + /* Reset callback functions. */ + pstcMfsHlInternData->pfnTransmitCbFunction = NULL; + pstcMfsHlInternData->pfnReceiveCbFunction = NULL; + pstcMfsHlInternData->pfnI2cSlvStCbFunction = NULL; + + /* Reset LIN Break Callback used for Mfs_Lin_DeInit() */ + pstcMfsHlInternData->pfnLinBreakCbFunction = NULL; + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + pstcMfsHlInternData->u8MfsMode = MfsHlModeStby; + + enResult = Ok; + } + + return (enResult); +} /* Mfs_Hl_I2c_DeInit */ + +/** + ****************************************************************************** + ** \brief Start operation as I2C slave + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ** \retval Ok Start slave process successfully done + ** \retval ErrorInvalidMode Slave isn't active + ** + ******************************************************************************/ +static en_result_t MfsHlI2cStartSlave(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_intern_data_t* pstcMfsHlInternData + ) +{ + en_result_t enResult; + stc_mfs_smr_field_t stcSMR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_i2c_ibsr_field_t stcIBSR; + stc_mfs_fcr1_field_t stcFCR1; + + stcIBCR = pstcI2c->IBCR_f; + /* Slave is active */ + if ((TRUE == stcIBCR.ACT_SCC) && (FALSE == stcIBCR.MSS)) + { + /* Set ACK */ + stcIBCR.ACKE = TRUE; + stcIBCR.ACT_SCC = FALSE; + pstcI2c->IBCR_f = stcIBCR; + + stcIBSR = pstcI2c->IBSR_f; + + /* Direction is TX */ + if (TRUE == stcIBSR.TRX) + { + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* tx FIFO interrupt enable */ + stcFCR1 = pstcI2c->FCR1_f; + stcFCR1.FTIE = TRUE; + pstcI2c->FCR1_f = stcFCR1; + } + /* FIFO is not used */ + else + { + /* tx interrupt enable */ + stcSMR = pstcI2c->SMR_f; + stcSMR.TIE = TRUE; + pstcI2c->SMR_f = stcSMR; + } + } + /* Direction is RX */ + else + { + /* rx interrupt enable */ + stcSMR = pstcI2c->SMR_f; + stcSMR.RIE = TRUE; + pstcI2c->SMR_f = stcSMR; + } + enResult = Ok; + } + else + { + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + enResult = ErrorInvalidMode; + } + + return (enResult); +} /* MfsHlI2cStartSlave */ + +/** + ****************************************************************************** + ** \brief Wait to change I2C interruption state + ** + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** + ** \retval Ok Interruption state changed within the specified + ** period of time. + ** \retval ErrorTimeout Interruption state didn't change within the + ** specified period of time. + ** + ******************************************************************************/ +static en_result_t MfsHlI2cWaitIntState(volatile stc_mfs_hl_intern_data_t* pstcMfsHlInternData) +{ + en_result_t enResult = ErrorTimeout; + volatile uint32_t u32Count; + uint32_t u32MaxCnt; + + u32MaxCnt = Mfs_GetBusClock() / MFS_HL_NUM_10; + u32Count = 0u; + while (u32Count < u32MaxCnt) + { + /* Wait until tx or rx is completed */ + if (MfsHlExecStby == pstcMfsHlInternData->u8Exec) + { + enResult = Ok; + break; + } + u32Count++; + } + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + + return (enResult); +} /* MfsHlI2cWaitIntState */ + +/** + ****************************************************************************** + ** \brief Check changing I2C interruption state + ** + ** \param [in] pstcMfsHlInternData Pointer to internal data + ** \param [in] u32MaxCnt Maximum counter to check state changing + ** + ** \retval Ok Interruption state changed within the + ** specified period of count. + ** \retval ErrorOperationInProgress Interruption state doesn't change and + ** counter isn't overflow yet. + ** \retval ErrorTimeout Interruption state didn't change within + ** the specified period of count. + ** + ******************************************************************************/ +static en_result_t MfsHlI2cChkTxRxComplete(stc_mfs_hl_intern_data_t* pstcMfsHlInternData, + uint32_t u32MaxCnt) +{ + en_result_t enResult; + + /* If tx or rx is completed, return OK */ + if (MfsHlExecStby == pstcMfsHlInternData->u8Exec) + { + enResult = Ok; + } + else + { + enResult = ErrorOperationInProgress; + /* If tx or rx is proceeding, polling counter counts */ + pstcMfsHlInternData->u32I2cProcCnt++; + if (u32MaxCnt <= pstcMfsHlInternData->u32I2cProcCnt) + { + enResult = ErrorTimeout; + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + } + + return (enResult); +} + +/** + ****************************************************************************** + ** \brief Write data to MFS_HL module for I2C + ** + ** The data provided by Mfs_Hl_I2c_Write#pu8Data is used directly and + ** the transmission (via TX interrupt) is started, if not ongoing already. + ** + ** If Mfs_Hl_I2c_Write#bBlocking is specified FALSE, the function will return + ** immediately after datas are transfered to the remote device. + ** + ** If Mfs_Hl_I2c_Write#bBlocking is specified TRUE, the function wait until + ** all data is transferred to the MFS hardware FIFO. If the referenced MFS + ** does not have a FIFO single data is written. + ** + ** Note: Don't access to the buffer which specified by pu8Data until transmission + ** processing completes. + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area + ** \param [in] u8SlaveAddr Slave address for master mode + ** \param [in] pu8Data Pointer to data buffer for transmission + ** \param [in,out] pu16WriteCnt Pointrer to variable for number of bytes to + ** send(must be at least 1). + ** And pointrer to variable for number of bytes + ** been sent. + ** \param [in] bBlocking If TRUE, synchronously wait until all data is + ** transferred into the hardware (Fifo) buffer. + ** If FALSE, return immediately. + ** + ** \retval Ok Write data successfully done or started. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pu8Data == NULL + ** - pu16WriteCnt == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorOperationInProgress If the following condition is met: + ** - A transmission or reception is still ongoing while another + ** I2C operation should be started. + ** \retval ErrorTimeout Interruption state didn't change within + ** the specified period of time. + ** + ******************************************************************************/ +en_result_t Mfs_Hl_I2c_Write(volatile stc_mfsn_t* pstcI2c, + uint8_t u8SlaveAddr, + uint8_t* pu8Data, + uint16_t* pu16WriteCnt, + boolean_t bBlocking + ) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + stc_mfs_smr_field_t stcSMR; + stc_mfs_i2c_ibcr_field_t stcIBCR; + stc_mfs_fcr1_field_t stcFCR1; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcI2c); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pu8Data) + || (NULL == pu16WriteCnt) + ) + { + enResult = ErrorInvalidParameter; + } + + /* Check the execution */ + else if (MfsHlExecStby != pstcMfsHlInternData->u8Exec) + { + enResult = ErrorOperationInProgress; + } + + else + { + enResult = Ok; + /* Check if nothing to do */ + if (0u != *pu16WriteCnt) + { + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + + /* Preset buffer */ + pstcBuffer->pu8Buffer = pu8Data; + pstcBuffer->u16BufferSize = *pu16WriteCnt; + pstcBuffer->u16OutIndex = 0u; + + /* Change state */ + pstcMfsHlInternData->u8Exec = MfsHlExecTransmitting; + + /* Master mode */ + if (MfsHlModeI2cMaster == pstcMfsHlInternData->u8MfsMode) + { + /* tx */ + /* write slave address, bit0 = 0 (tx) */ + u8SlaveAddr <<= MFS_HL_NUM_1; + u8SlaveAddr |= (uint8_t)(MfsI2cWrite); + pstcI2c->TDR = (uint16_t)(u8SlaveAddr); + + stcIBCR = pstcI2c->IBCR_f; + /* Set master mode */ + stcIBCR.MSS = TRUE; + /* Enable ACK */ + stcIBCR.ACKE = TRUE; + /* Enable interrupt */ + stcIBCR.INTE = TRUE; + stcIBCR.ACT_SCC = FALSE; + /* wait select */ + stcIBCR.WSEL = FALSE; + pstcI2c->IBCR_f = stcIBCR; + + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* tx FIFO interrupt enable : interruption occur */ + stcFCR1 = pstcI2c->FCR1_f; + stcFCR1.FTIE = TRUE; + pstcI2c->FCR1_f = stcFCR1; + } + /* FIFO is not used */ + else + { + /* tx interrupt enable : interruption occur */ + stcSMR = pstcI2c->SMR_f; + stcSMR.TIE = TRUE; + pstcI2c->SMR_f = stcSMR; + } + enResult = Ok; + } + /* Slave mode */ + else + { + enResult = MfsHlI2cStartSlave(pstcI2c, pstcMfsHlInternData); + } + + if (Ok == enResult) + { + /* Specified non-blocking call */ + if (FALSE == bBlocking) + { + /* Polling counter for check status is clear */ + pstcMfsHlInternData->u32I2cProcCnt = 0; + } + /* Specified blocking call */ + else + { + /* Wait until TX is completed or error occur */ + enResult = MfsHlI2cWaitIntState(pstcMfsHlInternData); + + if (0u == pstcBuffer->u16OutIndex) + { + enResult = ErrorTimeout; + } + *pu16WriteCnt = pstcBuffer->u16OutIndex; + } + } + } + } + + return (enResult); +} /* Mfs_Hl_I2c_Write */ + +/** + ****************************************************************************** + ** \brief Read received data from I2C + ** + ** The received data is copied from Receive Data Register into the provided + ** data buffer Mfs_Hl_I2c_Read#pu8Data. + ** The slave address (Mfs_Hl_I2c_Read#u8SlaveAddr) is used on master mode. + ** The size is defined by Mfs_Hl_I2c_Read#pu16ReadCnt. + ** If non-blocking is specified (Mfs_Hl_I2c_Read#bBlocking is FALSE), this + ** function will return immediately after available datas from remote device + ** are received into the provided buffer. (Mfs_Hl_I2c_Read#pu8Data) + ** + ** Anyway, Receive interrupt is used in any case. + ** + ** Note: Don't access to the buffer which specified by pu8Data until reception + ** processing completes. + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area. + ** \param [in] u8SlaveAddr Slave Address. + ** \param [in,out] pu8Data Buffer to store received characters. + ** \param [in,out] pu16ReadCnt Pointrer to variable for number of bytes + ** been read. + ** \param [in] bBlocking If TRUE, synchronously wait until pu16ReadCnt + ** bytes have been received. + ** If FALSE, return immediately. + ** + ** \retval Ok Read data successfully done or started. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pu8Data == NULL + ** - pu16ReadCnt == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorOperationInProgress If the following condition is met: + ** - A transmission or reception is still ongoing while another + ** I2C operation should be started. + ** \retval ErrorTimeout Interruption state didn't change within + ** the specified period of time. + ** + ******************************************************************************/ +en_result_t Mfs_Hl_I2c_Read(volatile stc_mfsn_t* pstcI2c, + uint8_t u8SlaveAddr, + uint8_t* pu8Data, + uint16_t* pu16ReadCnt, + boolean_t bBlocking + ) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + stc_mfs_i2c_ibcr_field_t stcIBCR; + uint16_t u16Count; + uint16_t u16Cnt; + + /* Check for valid pointers, and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcI2c); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pu8Data) + || (NULL == pu16ReadCnt) + ) + { + enResult = ErrorInvalidParameter; + } + + /* Check the execution */ + else if (MfsHlExecStby != pstcMfsHlInternData->u8Exec) + { + enResult = ErrorOperationInProgress; + } + + else + { + /* Get ptr to internal reception Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcRxBuffer; + + pstcBuffer->pu8Buffer = pu8Data; + pstcBuffer->u16BufferSize = *pu16ReadCnt; + pstcBuffer->u16InIndex = 0u; + + /* Change state */ + pstcMfsHlInternData->u8Exec = MfsHlExecReceiving; + + /* Master mode */ + if (MfsHlModeI2cMaster == pstcMfsHlInternData->u8MfsMode) + { + /* FIFO is used */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* -1 is for SlaveAddr */ + u16Count = MfsHlGetMin((pstcBuffer->u16BufferSize), + (MFS_FIFO_MAX_VAL - MFS_HL_NUM_1) + ); + /* Set threshold value for RX FIFO */ + pstcI2c->FBYTE2 = (uint8_t)u16Count; + } + /* FIFO is not used */ + else + { + u16Count = 0u; + } + /* rx */ + /* write slave address, bit0 = 1 (rx) */ + u8SlaveAddr <<= MFS_HL_NUM_1; + u8SlaveAddr |= (uint8_t)(MfsI2cRead); + pstcI2c->TDR = (uint16_t)(u8SlaveAddr); + + /* Write dummy data (0x00) for FIFO */ + for (u16Cnt = 0u; u16Cnt < u16Count; u16Cnt++) + { + pstcI2c->TDR = 0x00u; + } + + stcIBCR = pstcI2c->IBCR_f; + /* Enable ACK */ + stcIBCR.ACKE = TRUE; + /* wait select */ + stcIBCR.WSEL = TRUE; + /* interrup enable */ + stcIBCR.INTE = TRUE; + /* clear interrupt */ + stcIBCR.ACT_SCC = FALSE; + stcIBCR.INT = FALSE; + /* Set master mode */ + stcIBCR.MSS = TRUE; + pstcI2c->IBCR_f = stcIBCR; + + enResult = Ok; + } + /* Slave mode */ + else + { + enResult = MfsHlI2cStartSlave(pstcI2c, pstcMfsHlInternData); + } + + if (Ok == enResult) + { + /* Specified non-blocking call */ + if (FALSE == bBlocking) + { + /* Polling counter for check status is clear */ + pstcMfsHlInternData->u32I2cProcCnt = 0; + } + /* Specified blocking call */ + else + { + /* Wait until TX is completed or error occur */ + enResult = MfsHlI2cWaitIntState(pstcMfsHlInternData); + + if ((Ok != enResult) + || (0u == pstcBuffer->u16InIndex)) + { + *pu16ReadCnt = 0u; + enResult = ErrorTimeout; + } + else + { + *pu16ReadCnt = pstcBuffer->u16InIndex; + } + } + } + } + + return (enResult); +} /* Mfs_Hl_I2c_Read */ + +/** + ****************************************************************************** + ** \brief Check to complete I2C transmission + ** + ** If Mfs_Hl_I2c_Write() is used by non-blocking, please call this function + ** at the application periodically because execution status doesn't change to + ** standby if stop condition isn't detected. + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area. + ** \param [in] u32MaxCnt Maximum period to check state changing + ** + ** \retval Ok Write data successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorInvalidMode A reception is still ongoing. + ** \retval ErrorOperationInProgress A transmission is still ongoing. + ** \retval ErrorTimeout A transmission didn't complete within + ** the specified period. + ** + ******************************************************************************/ +en_result_t Mfs_Hl_I2c_WaitTxComplete(volatile stc_mfsn_t* pstcI2c, + uint32_t u32MaxCnt + ) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + + /* Check for valid pointers, and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcI2c); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + + /* Check the execution */ + else if ((MfsHlExecTransmitting != pstcMfsHlInternData->u8Exec) + && (MfsHlExecStby != pstcMfsHlInternData->u8Exec)) + { + enResult = ErrorInvalidMode; + } + + else + { + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + + enResult = Ok; + if (MfsHlExecTransmitting == pstcMfsHlInternData->u8Exec) + { + /* Check tx or rx is completed or error occur */ + enResult = MfsHlI2cChkTxRxComplete(pstcMfsHlInternData, u32MaxCnt); + if (ErrorOperationInProgress != enResult) + { + if (0u == pstcBuffer->u16OutIndex) + { + enResult = ErrorTimeout; + } + } + } + } + + return (enResult); +} /* Mfs_Hl_I2c_WaitTxComplete */ + +/** + ****************************************************************************** + ** \brief Check to complete I2C reception + ** + ** If Mfs_Hl_I2c_Read() is used by non-blocking, please call this function + ** at the application periodically because execution status doesn't change to + ** standby if stop condition isn't detected. + ** + ** \param [in] pstcI2c Pointer to I2C (MFS) instance register area. + ** \param [in] u32MaxCnt Maximum period to check state changing + ** + ** \retval Ok Write data successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcI2c == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorInvalidMode A transmission is still ongoing. + ** \retval ErrorOperationInProgress A reception is still ongoing. + ** \retval ErrorTimeout A reception didn't complete within + ** the specified period. + ** + ******************************************************************************/ +en_result_t Mfs_Hl_I2c_WaitRxComplete(volatile stc_mfsn_t* pstcI2c, + uint32_t u32MaxCnt + ) +{ + en_result_t enResult; + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + + /* Check for valid pointers, and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcI2c); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + enResult = ErrorInvalidParameter; + } + + /* Check the execution */ + else if ((MfsHlExecReceiving != pstcMfsHlInternData->u8Exec) + && (MfsHlExecStby != pstcMfsHlInternData->u8Exec)) + { + enResult = ErrorInvalidMode; + } + + else + { + enResult = Ok; + if (MfsHlExecReceiving == pstcMfsHlInternData->u8Exec) + { + /* Check tx or rx is completed or error occur */ + enResult = MfsHlI2cChkTxRxComplete(pstcMfsHlInternData, u32MaxCnt); + if (ErrorOperationInProgress != enResult) + { + /* Get ptr to internal reception Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcRxBuffer; + + if ((Ok != enResult) + || (0u == pstcBuffer->u16InIndex)) + { + enResult = ErrorTimeout; + } + } + } + } + + return (enResult); +} /* Mfs_Hl_I2c_WaitRxComplete */ + +/** + ****************************************************************************** + ** \brief Write data to MFS_HL module synchronously or asynchronously + ** + ** This function can use for UART, CSIO or LIN. + ** + ** The data provided by Mfs_Hl_Write#pu8Data is copied into the internal + ** TX buffer and the transmission (via TX interrupt) is started, if transmission + ** is not ongoing already. + ** Depending on the Mfs_Hl_Write#bBlocking parameter, the function return behavior + ** is different. + ** + ** For an asynchronous (non-blocking) call (Mfs_Hl_Write#bBlocking = FALSE), + ** the free size of the internal buffer must be sufficient to take all data + ** (Mfs_Hl_Write#pu8Data) of length Mfs_Hl_Write#u16WriteCnt, otherwise + ** the function will return ErrorBufferFull. + ** After all data is copied into the internal buffer, the function will return + ** immediately. The transmission may be pending when the function returns. + ** + ** For a synchronous (blocking) call (Mfs_Hl_Write#bBlocking = TRUE), + ** the function will wait until all data is transferred to the MFS hardware FIFO. + ** The transmission may be pending when the function returns. + ** If the referenced MFS does not have a FIFO single data is written. + ** + ** However, when call-back for transmission is not set, this function executes + ** only by blocking. + ** + ** \param [in] pstcMfs Pointer to MFS instance register area + ** \param [in] pu8Data Transmit data buffer holding data to transmit + ** \param [in] u16WriteCnt Number of characters to write, must be at least 1 + ** \param [in] bBlocking If TRUE, synchronously wait until all data is + ** transferred into the hardware Fifo buffer + ** If FALSE, put data into internal TX buffer and return + ** immediately + ** But this parameter isn't effective when the + ** call-back for transmission isn't set. + ** \param [in] bCsHolding Specify to hold chip select + ** This parameter is only effective when mode is + ** CSIO/SPI master and chip select function is used. + ** + ** \retval Ok Transmit data successfully done or started. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMfs == NULL + ** - pu8Data == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorOperationInProgress A transmission or reception is still + ** ongoing + ** \retval ErrorBufferFull Insufficient free size of TX buffer to + ** take all data (in case of + ** Mfs_Hl_Write#bBlocking = FALSE only) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Write(volatile stc_mfsn_t* pstcMfs, + uint8_t* pu8Data, + uint16_t u16WriteCnt, + boolean_t bBlocking, + boolean_t bCsHolding + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + uint_fast16_t fu16DataSent; + uint_fast16_t fu16Idx; + boolean_t bTxInProgress; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcMfs); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pu8Data) + ) + { + return (ErrorInvalidParameter); + } + + /* Check if nothing to do */ + if (0u == u16WriteCnt) + { + return (Ok); + } + + /* Check the execution */ + if (MfsHlExecStby != pstcMfsHlInternData->u8Exec) + { + return (ErrorOperationInProgress); + } + + /* Get ptr to internal transmit Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + + /* Check if ring buffer can take all bytes (blocking only) */ + if ((FALSE == bBlocking) && + (u16WriteCnt > (pstcBuffer->u16BufferSize - pstcBuffer->u16FillCount)) + ) + { + /* not enough space left if non-blocking mode is requested */ + return (ErrorBufferFull); + } + + /* Change state */ + pstcMfsHlInternData->u8Exec = MfsHlExecTransmitting; + + /* Set total tx bytes (for CSIO timer mode) */ + pstcBuffer->u16TxCount = u16WriteCnt; + /* Clear total tx bytes */ + pstcBuffer->u16TxCounter = 0u; + + /* CSIO timer mode */ + if (MfsHlModeCsioNormalMasterTimer == pstcMfsHlInternData->u8MfsMode) + { + /* Enable serial timer */ + pstcMfs->SCR_f.TXE = FALSE; + pstcMfs->SACSR_f.TMRE = TRUE; + pstcMfs->SCR_f.TXE = TRUE; + } + /* Loop until all data has been sent (blocking only) */ + /* If non-blocking mode is requested, it is guaranteed here that the */ + /* provided data will fit into the tx buffer */ + while (0u < u16WriteCnt) + { + /* Use interruption */ + if (NULL != pstcMfsHlInternData->pfnTransmitCbFunction) + { + /* Check for transmission ongoing */ + bTxInProgress = pstcMfs->SSR_f.TDRE; + + /* In case, a transmission is already pending */ + if (TRUE == bTxInProgress) + { + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Disable transmission Fifo interrupt during copy */ + pstcMfs->FCR1_f.FTIE = FALSE; + } + else /* if (pstcMfsInternData->enFifoAvailable == MfsHasFifo) */ + { + /* Disable transmission interrupt during copy */ + pstcMfs->SCR_f.TIE = FALSE; + } + } + } + + /* Copy data to provided destinaton buffer and save # bytes been read */ + /* determine free size in TX buffer */ + fu16DataSent = (uint_fast16_t)MfsHlGetMin(((pstcBuffer->u16BufferSize) - (pstcBuffer->u16FillCount)), + u16WriteCnt + ); + + if (MfsHlModeCsioSpiMasterWithCs == pstcMfsHlInternData->u8MfsMode) + { + if (MFS_CSIO_TBYTE_MAX < fu16DataSent) + { + fu16DataSent = MFS_CSIO_TBYTE_MAX; + } + } + + /* store bytes in TX buffer */ + for (fu16Idx = 0u; fu16Idx < fu16DataSent; fu16Idx++) + { + pstcBuffer->pu8Buffer[pstcBuffer->u16InIndex] = pu8Data[fu16Idx]; + + /* Update in index */ + pstcBuffer->u16InIndex++; + if (pstcBuffer->u16InIndex == pstcBuffer->u16BufferSize) + { + pstcBuffer->u16InIndex = 0u; /* wrapped around */ + } + } + + pstcBuffer->u16FillCount += (uint16_t)fu16DataSent; + u16WriteCnt -= (uint16_t)fu16DataSent; + + /* Set tx bytes when chip select is used on master mode */ + if (MfsHlModeCsioSpiMasterWithCs == pstcMfsHlInternData->u8MfsMode) + { + pstcMfs->SCR_f.TXE = FALSE; + /* Set size to active chip select */ + pstcMfs->TBYTE0 = (uint8_t)fu16DataSent; + if ((0u != u16WriteCnt) || (TRUE == bCsHolding)) + { + /* Hold chip select */ + pstcMfs->SCSCR_f.SCAM = TRUE; + } + else + { + /* In-active chip select when transmit is end */ + pstcMfs->SCSCR_f.SCAM = FALSE; + } + pstcMfs->SCR_f.TXE = TRUE; + } + /* Use interruption */ + if (NULL != pstcMfsHlInternData->pfnTransmitCbFunction) + { + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + /* Now enable transmission Fifo interrupt to trigger send operation */ + pstcMfs->FCR1_f.FTIE = TRUE; + } + else /* if (MfsHlUseNoFifo == pstcMfsHlInternData->u8FifoUsage) */ + { + /* Now enable transmission interrupt to trigger send operation */ + pstcMfs->SCR_f.TIE = TRUE; + } + } + /* No use interruption */ + else + { + /* Wait until all data has been tranferred to the MFS HW FIFO */ + while (0u != pstcBuffer->u16FillCount) + { + /* If Transmit Data Register (TDR) is empty */ + if (TRUE == pstcMfs->SSR_f.TDRE) + { + /* Write the contents of the buffer to Transmit Data Register */ + MfsHlWriteBuf(pstcMfs, pstcMfsHlInternData); + } + } + if (0u == u16WriteCnt) + { + /* CSIO timer mode */ + if (MfsHlModeCsioNormalMasterTimer == pstcMfsHlInternData->u8MfsMode) + { + /* Wait for TX bus idle */ + while (FALSE == pstcMfs->SSR_f.TBI) + { + /* There is no process that should be executed. */ + ; + } + /* Disable serial timer */ + pstcMfs->SCR_f.TXE = FALSE; + pstcMfs->SACSR_f.TMRE = FALSE; + pstcMfs->SCR_f.TXE = TRUE; + } + pstcMfsHlInternData->u8Exec = MfsHlExecStby; + } + } + } /* while (u16WriteCnt) */ + + /* Wait until all data has been tranferred to the MFS HW FIFO (when blocking) */ + if (TRUE == bBlocking) + { + while (MfsHlExecStby != pstcMfsHlInternData->u8Exec) + { + PDL_WAIT_LOOP_HOOK(); + } + } + + return (Ok); +} /* Mfs_Hl_Write */ + +/** + ****************************************************************************** + ** \brief Read received data from MFS_HL module synchronously or asynchronously + ** + ** This function can use for UART, CSIO or LIN. + ** + ** The received data is copied from internal RX buffer (filled by RX interrupt) + ** into the provided data buffer Mfs_Hl_Read#pu8Data. The size is defined + ** by Mfs_Hl_Read#pu16DataCnt. Depending on the Mfs_Hl_Read#bBlocking + ** parameter, the function behavior is different. + ** + ** For an asynchronous (non-blocking) call (Mfs_Hl_Read#bBlocking = FALSE), + ** the function will return immediately after all currently available characters + ** (in SW ring buffer and HW FIFO) are copied into the provided buffer + ** (Mfs_Hl_Read#pu8Data) or the maximum count (Mfs_Hl_Read#u16ReadCnt) + ** is reached. The value returned by Mfs_Hl_Read#pu16DataCnt gives the + ** count of characters that was read actually. + ** If the referenced MFS does not have a FIFO single data is read. + ** + ** For a synchronous (blocking) call (Mfs_Hl_Read#bBlocking == TRUE), + ** the function will return after the requested count of characters + ** (Mfs_Hl_Read#pu16DataCnt) is received completely. + ** This should be used with caution as the full application can get stuck + ** if no further data is received. + ** + ** \param [in] pstcMfs Pointer to MFS instance register area + ** \param [in,out] pu8Data Buffer to store received data + ** \param [in,out] pu16DataCnt Pointer to variable for number of bytes + ** been read + ** \param [in] u16ReadCnt Maximum number of characters to read + ** (ensure sufficient size of pu16DataCnt#pu8Data!) + ** \param [in] bBlocking If TRUE, synchronously wait until + ** pu16DataCnt#u16ReadCnt bytes have been + ** received. + ** If FALSE, read all available and + ** return immediately. + ** + ** \retval Ok Read data successfully done or started. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMfs == NULL + ** - pu8Data == NULL + ** - pu16DataCnt == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** \retval ErrorOperationInProgress If the following condition is met: + ** - An asynchronous transmission is still ongoing while another + ** asynchronous operation should be started. + ** + ******************************************************************************/ +en_result_t Mfs_Hl_Read(volatile stc_mfsn_t* pstcMfs, + uint8_t* pu8Data, + uint16_t* pu16DataCnt, + uint16_t u16ReadCnt, + boolean_t bBlocking + ) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + stc_mfs_hl_buffer_t* pstcBuffer; + uint_fast16_t fu16Idx; + uint_fast16_t fu16Length; + uint16_t u16BytesToReadLeft; + volatile uint8_t u8Ssr; + volatile uint8_t u8SsrErr; + + if (NULL != pu16DataCnt) + { + *pu16DataCnt = 0u; /* Preset to default */ + } + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcMfs); + /* ... and check */ + if ((NULL == pstcMfsHlInternData) + || (NULL == pu8Data) + || (NULL == pu16DataCnt) + ) + { + return (ErrorInvalidParameter); + } + + /* Check the execution */ + if (MfsHlExecStby != pstcMfsHlInternData->u8Exec) + { + return (ErrorOperationInProgress); + } + + /* Save Read Count for later use */ + u16BytesToReadLeft = u16ReadCnt; + + /* Check for nothing to do */ + if (0u == u16ReadCnt) + { + return (Ok); + } + + /* Get ptr to internal receive Buffer */ + pstcBuffer = &pstcMfsHlInternData->stcRxBuffer; + + /* Adjust FIFO, if u16ReadCnt less than FIFO depth */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + if (MFS_FIFO_MAX_VAL > u16ReadCnt) + { + pstcMfs->FBYTE2 = (uint8_t)u16ReadCnt; + } + else + { + pstcMfs->FBYTE2 = MFS_FIFO_MAX_VAL; + } + } + + /* Use interruption */ + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + if (FALSE == pstcMfs->SCR_f.RIE) + { + /* Enable reception interrupt */ + pstcMfs->SCR_f.RIE = TRUE; + } + } + + /* Read all available bytes from ring buffer, blocking. */ + while (0u < u16BytesToReadLeft) + { + /* Blocking read */ + if (TRUE == bBlocking) + { + while (0u == pstcBuffer->u16FillCount) + { + /* No use interruption */ + if (NULL == pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Read status */ + u8Ssr = u8SsrErr = pstcMfs->SSR; + /* Error is different each mode */ + switch (pstcMfsHlInternData->u8MfsMode & MFS_HL_MODE_GROUP_CHK) + { + /* UART */ + case MFS_HL_MODE_GROUP_UART: + /* Check Overrun/Framing/Parity error */ + u8SsrErr &= MFS_UART_SSR_ERR; + break; + /* CSIO */ + case MFS_HL_MODE_GROUP_CSIO: + /* Check Overrun error */ + u8SsrErr &= MFS_CSIO_SSR_ERR; + break; + /* LIN */ + case MFS_HL_MODE_GROUP_LIN: + /* Check Overrun/Framing error */ + u8SsrErr &= MFS_LIN_SSR_ERR; + break; + default: + u8SsrErr = 0u; + break; + } + /* Error */ + if(0u != u8SsrErr) + { + /* Clear possible reception errors */ + pstcMfs->SSR_f.REC = TRUE; + + /* If error occurs when receiving data, return error. */ + return Error; + } + /* If received data is full... */ + if (0u != (u8Ssr & MFS_SSR_RDRF)) + { + /* Store Received Data Register into buffer */ + MfsHlReadBuf(pstcMfs, pstcMfsHlInternData); + } + } + else + { + /* Wait until at least one byte is available */ + PDL_WAIT_LOOP_HOOK(); + } + } + } + else + { + /* No use interruption */ + if (NULL == pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Read status */ + u8Ssr = u8SsrErr = pstcMfs->SSR; + /* Error is different each mode */ + switch (pstcMfsHlInternData->u8MfsMode & MFS_HL_MODE_GROUP_CHK) + { + /* UART */ + case MFS_HL_MODE_GROUP_UART: + /* Check Overrun/Framing/Parity error */ + u8SsrErr &= MFS_UART_SSR_ERR; + break; + /* CSIO */ + case MFS_HL_MODE_GROUP_CSIO: + /* Check Overrun error */ + u8SsrErr &= MFS_CSIO_SSR_ERR; + break; + /* LIN */ + case MFS_HL_MODE_GROUP_LIN: + /* Check Overrun/Framing error */ + u8SsrErr &= MFS_LIN_SSR_ERR; + break; + default: + u8SsrErr = 0u; + break; + } + /* Error */ + if(0u != u8SsrErr) + { + /* Clear possible reception errors */ + pstcMfs->SSR_f.REC = TRUE; + /* If error occurs when receiving data, return error. */ + return Error; + } + /* If received data is full... */ + if (0u != (u8Ssr & MFS_SSR_RDRF)) + { + /* Store Received Data Register into buffer */ + MfsHlReadBuf(pstcMfs, pstcMfsHlInternData); + } + } + if (0u == pstcBuffer->u16FillCount) + { + return (Ok); + } + } + + /* Disable reception interrupt */ + pstcMfs->SCR_f.RIE = FALSE; + + /* Copy data to destinaton buffer and save no. of bytes been read */ + /* get number of bytes to read */ + fu16Length = (uint_fast16_t)MfsHlGetMin(pstcBuffer->u16FillCount, u16BytesToReadLeft); + + /* if there are any bytes left to read */ + if (0u != fu16Length) + { + /* read bytes out of RX buffer */ + for (fu16Idx = *pu16DataCnt; fu16Idx < (fu16Length + *pu16DataCnt); fu16Idx++) + { + pu8Data[fu16Idx] = pstcBuffer->pu8Buffer[pstcBuffer->u16OutIndex]; + /* Update out index */ + pstcBuffer->u16OutIndex++; + if (pstcBuffer->u16OutIndex == pstcBuffer->u16BufferSize) + { + pstcBuffer->u16OutIndex = 0u; + } + } + pstcBuffer->u16FillCount -= (uint16_t)fu16Length; /* Update fill counter */ + } + + *pu16DataCnt += (uint16_t)fu16Length; /* Provide no. of read to the caller */ + u16BytesToReadLeft -= (uint16_t)fu16Length; /* Some data processed */ + + /* Adjust FIFO, if bytes to read left less than FIFO depth */ + if (MfsHlUseFifo == pstcMfsHlInternData->u8FifoUsage) + { + if (MFS_FIFO_MAX_VAL > u16BytesToReadLeft) + { + if (0u == u16BytesToReadLeft) + { + pstcMfs->FBYTE2 = MFS_RX_FIFO_MIN_VAL; + } + else + { + pstcMfs->FBYTE2 = (uint8_t)u16BytesToReadLeft; + } + } + } + /* Use interruption */ + if (NULL != pstcMfsHlInternData->pfnReceiveCbFunction) + { + /* Reenable reception interrupt */ + pstcMfs->SCR_f.RIE = TRUE; + } + } + + return (Ok); +} /* Mfs_Hl_Read */ + + +/** + ****************************************************************************** + ** \brief Get the internal TX or RX buffer pointer + ** + ** The buffer information can be gotten with this pointer. + ** + ** \param [in] pstcMfs Pointer to MFS instance register area. + ** \param [in] enBufIndex Buffer index + ** \param [out] ppstcBuffer Pointer to the pointer of RX or TX buffer + ** + ** \retval Ok Write data successfully done. + ** \retval ErrorInvalidParameter If one of following conditions are met: + ** - pstcMfs == NULL + ** - pstcMfsHlInternData == NULL (invalid or disabled MFS unit + ** (PDL_PERIPHERAL_ENABLE_MFS)) + ** - (enBuf != MfsHlRxBuffer) && (enBuf != MfsHlTxBuffer) + ** + ******************************************************************************/ +en_result_t Mfs_Hl_GetBufferPointer(volatile stc_mfsn_t* pstcMfs, + en_mfs_hl_buffer_t enBufIndex, + stc_mfs_hl_buffer_t** ppstcBuffer) +{ + stc_mfs_hl_intern_data_t* pstcMfsHlInternData; + + /* Check for valid pointers and get pointer to internal data struct ... */ + pstcMfsHlInternData = MfsHlGetInternDataPtr(pstcMfs); + /* ... and check */ + if (NULL == pstcMfsHlInternData) + { + return (ErrorInvalidParameter); + } + + switch(enBufIndex) + { + case MfsHlRxBuffer: + *ppstcBuffer = &pstcMfsHlInternData->stcRxBuffer; + break; + case MfsHlTxBuffer: + *ppstcBuffer = &pstcMfsHlInternData->stcTxBuffer; + break; + default: + return (ErrorInvalidParameter); + } + + return Ok; +} + +//@} // MfshlGroup + +#endif /* #if (PDL_MFS_USE_HL == PDL_ON) */ + +#endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.h new file mode 100644 index 0000000000..d02342c3bb --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/mfs/mfs_hl.h @@ -0,0 +1,563 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file mfs_hl.h + ** + ** Headerfile for MFS High Level functions + ** + ** History: + ** - 2013-03-26 1.0 NT First version. + ** - 2014-05-26 1.1 EZ Add a function to get the pointer of TX or RX + ** buffer. + ** - 2014-05-28 1.2 MWi Doxygen comments corrected. + ** + ******************************************************************************/ + +#ifndef __MFS_HL_H__ +#define __MFS_HL_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "mfs/mfs.h" + +#if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup MfshlGroup MFS High Level Functions (MFS_HL) + ** + ** Provided functions of MFS_HL module: + ** + ** - Mfs_Hl_Uart_Init() + ** - Mfs_Hl_Uart_DeInit() + ** - Mfs_Hl_Csio_Init() + ** - Mfs_Hl_Csio_DeInit() + ** - Mfs_Hl_Csio_SynchronousTrans() + ** - Mfs_Hl_Lin_Init() + ** - Mfs_Hl_Lin_DeInit() + ** - Mfs_Hl_Lin_SetBreak() + ** - Mfs_Hl_Lin_SetNewBaudDivisor() + ** - Mfs_Hl_Lin_TransferRxBuffer() + ** - Mfs_Hl_Lin_DisableRxInterrupt() + ** - Mfs_Hl_I2c_Init() + ** - Mfs_Hl_I2c_DeInit() + ** - Mfs_Hl_I2c_Write() + ** - Mfs_Hl_I2c_Read() + ** - Mfs_Hl_I2c_WaitTxComplete() + ** - Mfs_Hl_I2c_WaitRxComplete() + ** - Mfs_Hl_Read() + ** - Mfs_Hl_Write() + ** - Mfs_Hl_GetBufferPointer() + ** + ** \brief How to use MFS High Level module + ** + ** Mfs_Hl_Uart_Init() is used to initialize an MFS instance to UART mode with + ** parameter pstcConfig of type #stc_mfs_hl_uart_config_t. + ** Mfs_Hl_Uart_DeInit() is used to reset all MFS UART related register. + ** So this function is used after initialization by Mfs_Hl_Uart_Init(). + ** + ** Mfs_Hl_Csio_Init() is used to initialize an MFS instance to CSIO mode with + ** parameter pstcConfig of type #stc_mfs_hl_csio_config_t. + ** This function can be able to set timer mode or SPI mode using chip select + ** (CS) with parameter pstcConfig->pstcMfsSpiConfig of type + ** #stc_mfs_hl_spi_config_t. + ** Mfs_Hl_Csio_DeInit() is used to reset all MFS CSIO related register. + ** So this function is used after initialization by Mfs_Hl_Csio_Init(). + ** Mfs_Hl_Csio_SynchronousTrans() is used to transfer and receive data + ** simultaneously. This function is only used by blocking. So interrupt is + ** not used for this function. + ** + ** Mfs_Hl_Lin_Init() is used to initialize an MFS instance to LIN mode with + ** its dedicated LIN configuration (#stc_mfs_hl_lin_config_t). + ** Mfs_Hl_Lin_DeInit() is used to reset all MFS LIN related register. + ** So this function is used after initialization by Mfs_Hl_Lin_Init(). + ** Mfs_Hl_Lin_SetBreak() set the LIN Break in LIN Master mode. The baud rate + ** divisor (not the rate itself!) can be adjusted by Mfs_Hl_Lin_SetNewBaudDivisor() + ** after measurement with a dedicated ICU in LIN Slave mode. + ** Note that the LIN functionality only works properly when the MFS is + ** connected to a LIN transceiver, which means, that the SOT line as always + ** read-back by SIN input! + ** Mfs_Hl_Lin_DisableRxInterrupt() is used to disable the Rx interrupt, if a + ** LIN frame was completely read and a new frame beginning with the LIN break + ** is awaited to avoid unnecessary reception of a '0'-Byte with a framing + ** error. + ** Mfs_Hl_Lin_TransferRxBuffer() transfers the reception data from the internal + ** ring buffer to a user buffer. This function can be used for LIN Master and + ** Slave mode, because of the external LIN transceiver, every data + ** (transmission and/or reception) is always read completely to the reception + ** buffer. + ** + ** Mfs_Hl_I2c_Init() is used to initialize an MFS instance to I2C mode with + ** parameter pstcConfig of type #stc_mfs_hl_i2c_config_t. + ** Mfs_Hl_I2c_DeInit() is used to reset all MFS I2C related register. + ** So this function is used after initialization by Mfs_Hl_I2c_Init(). + ** Mfs_Hl_I2c_Write() is used to transmit data, and Mfs_Hl_I2c_Read() is used to + ** receive data on I2C mode. These function can use synchronously (blocking-call) + ** or asynchronously(non-blocking-call). If user wants to use it synchronously, + ** the parameter bBlocking of Mfs_Hl_I2c_Write() or/and Mfs_Hl_I2c_Read() + ** should specified TRUE. Otherwise, if user wants to use it asynchronously, + ** the parameter bBlocking of Mfs_Hl_I2c_Write() or/and Mfs_Hl_I2c_Read() + ** should specified FALSE. + ** These functions are used for I2C mode. But Mfs_Hl_Read() and Mfs_Hl_Write() + ** can't use for I2C. + ** Mfs_Hl_I2c_WaitTxComplete() and Mfs_Hl_I2c_WaitRxComplete() are used to check + ** complete transmission or receiption. + ** If Mfs_Hl_I2c_Write() is used by non-blocking, please call Mfs_Hl_I2c_WaitTxComplete() + ** at the application periodically because execution status doesn't change to + ** standby if stop condition isn't detected. + ** If Mfs_Hl_I2c_Read() is used by non-blocking, please call Mfs_Hl_I2c_WaitRxComplete() + ** at the application periodically because execution status doesn't change to + ** standby if stop condition isn't detected. + ** + ** For UART, CSIO or LIN, Mfs_Hl_Read() and Mfs_Hl_Write() can use for communication. + ** See the description of these functions for detail. + ** + ******************************************************************************/ +//@{ + +/** + ****************************************************************************** + ** \brief MFS_HL callback function prototypes. + ******************************************************************************/ +typedef void (*mfs_hl_tx_cb_func_ptr_t)(uint16_t); +typedef void (*mfs_hl_rx_cb_func_ptr_t)(uint16_t); +typedef uint8_t (*mfs_hl_i2c_slv_cb_func_prt_t)(uint8_t); +typedef void (*mfs_hl_lin_brk_func_ptr_t)(void); + +/*****************************************************************************/ +/* Gloval pre-processor symbols/macros ('#define") */ +/*****************************************************************************/ +/** + ****************************************************************************** + ** \brief MFS_HL mode group + ******************************************************************************/ +#define MFS_HL_MODE_GROUP_CHK (0xF0u) +#define MFS_HL_MODE_GROUP_UART (0x10u) +#define MFS_HL_MODE_GROUP_CSIO (0x20u) +#define MFS_HL_MODE_GROUP_I2C (0x30u) +#define MFS_HL_MODE_GROUP_LIN (0x40u) + +/****************************************************************************** + * Global type definitions + ******************************************************************************/ + +/** + ****************************************************************************** + ** \brief MFS_HL FIFO usage + ******************************************************************************/ +typedef enum en_mfs_hl_fifo_usage +{ + MfsHlUseNoFifo = 0, ///< Don't use MFS FIFO function. + MfsHlUseFifo = 1 ///< Use MFS FIFO function. +} en_mfs_hl_fifo_usage_t; + +/** + ****************************************************************************** + ** \brief MFS_HL Execution status + ******************************************************************************/ +typedef enum en_mfs_hl_exec +{ + MfsHlExecStby = 0, ///< MFS doesn't active. + MfsHlExecReceiving = 1, ///< MFS is performing reception. + MfsHlExecTransmitting = 2, ///< MFS is performing transmission. + MfsHlExecWaitTxBusIdle = 3 ///< MFS is waiting TX bus idle. +} en_mfs_hl_exec_t; + +/** + ****************************************************************************** + ** \brief MFS_HL MFS mode + ******************************************************************************/ +typedef enum en_mfs_hl_mfs_mode +{ + MfsHlModeStby = 0x00, ///< MFS is no active + MfsHlModeUartNormal = 0x10, ///< UART normal mode + MfsHlModeUartMulti = 0x11, ///< UART multi-processor mode + MfsHlModeCsioNormalMaster = 0x20, ///< CSIO normal mode/master + MfsHlModeCsioNormalMasterTimer = 0x21, ///< CSIO normal mode/master/use serial timer + MfsHlModeCsioNormalSlave = 0x22, ///< CSIO normal mode/slave + MfsHlModeCsioNormalSlaveTimer = 0x23, ///< CSIO normal mode/slave/use serial timer + MfsHlModeCsioSpiMaster = 0x28, ///< CSIO SPI mode/master + MfsHlModeCsioSpiMasterWithCs = 0x29, ///< CSIO SPI mode/master/use chip select + MfsHlModeCsioSpiSlave = 0x2A, ///< CSIO SPI mode/slave + MfsHlModeCsioSpiSlaveWithCs = 0x2B, ///< CSIO SPI mode/slave/use chip select + MfsHlModeI2cMaster = 0x30, ///< I2C mode/master + MfsHlModeI2cSlave = 0x31, ///< I2C mode/slave + MfsHlModeI2cMasterFast = 0x32, ///< I2C mode/master/Fast mode + MfsHlModeI2cSlaveFast = 0x33, ///< I2C mode/master/Fast mode + MfsHlModeLinMaster = 0x40, ///< LIN mode/master + MfsHlModeLinSlave = 0x41 ///< LIN mode/slave +} en_mfs_hl_mfs_mode_t; + +/** + ****************************************************************************** + ** \brief MFS_HL I2C wait selection + ******************************************************************************/ +typedef enum en_mfs_hl_i2c_wait_select +{ + MfsHlI2cWaitAfterAck = 0, ///< Waits (9bits) after acknowledgement. + MfsHlI2cWaitAfterDataTxRx = 1 ///< Waits (8bits) after data transmission or reception. +} en_mfs_hl_i2c_wait_select_t; + +/** + ****************************************************************************** + ** \brief MFS_HL I2C interrupt status + ******************************************************************************/ +typedef enum en_mfs_hl_i2c_int_state +{ + MfsHlI2cIntStateStby = 0, ///< Non interruption + MfsHlI2cIntStateEndData = 1, ///< End to transmit data + MfsHlI2cIntStateNack = 2, ///< Receive NACK + MfsHlI2cIntStateStopCond = 3, ///< Stop condition + MfsHlI2cIntStateErr = 0xEE ///< Error +} en_mfs_hl_i2c_int_state_t; + +/** + ****************************************************************************** + ** \brief MFS_HL ring buffer. + ** + ** Contains all parameter for ring buffer handling. + ******************************************************************************/ +typedef struct stc_mfs_hl_buffer +{ + uint8_t* pu8Buffer; ///< Pointer to communication buffer. + uint16_t u16BufferSize; ///< Size of buffer. + uint16_t u16InIndex; ///< Index of next element to store on buffer. + uint16_t u16OutIndex; ///< Index of next element to read from buffer. + uint16_t u16FillCount; ///< Indicates if elements are available in buffer. + uint16_t u16TxCounter; ///< Transmitted size + uint16_t u16TxCount; ///< Transfer size for timer mode. + boolean_t bOverflow; ///< TRUE: Indicates Overrun Condition +} stc_mfs_hl_buffer_t; + +/** + ****************************************************************************** + ** \brief MFS_HL UART configuration. + ** + ** Contains all parameter for configuratin a MFS channel, if set to UART mode. + ******************************************************************************/ +typedef struct stc_mfs_hl_uart_config +{ + uint32_t u32DataRate; ///< Bits per second + boolean_t bBitDirection; ///< TRUE: MSB first, FALSE: LSB first + boolean_t bSignalSystem; ///< TRUE: Inverted NRZ, FALSE: NRZ + boolean_t bHwFlow; ///< TRUE: Use Hardware Flow + uint8_t* pu8TxBuf; ///< Pointer to tranasmit FIFO buffer. + uint8_t* pu8RxBuf; ///< Pointer to receive FIFO buffer. + uint16_t u16TxBufSize; ///< Size of transmit FIFO buffer. + uint16_t u16RxBufSize; ///< Size of receive FIFO buffer. + uint16_t u16RxCbBufFillLvl; ///< Unread counts of data buffer to call RX Callback function + uint8_t u8UartMode; ///< Uart mode, see description of #en_mfs_uart_mode_t on mfs.h + uint8_t u8Parity; ///< Parity, see description of #en_mfs_parity_t on mfs.h + uint8_t u8StopBit; ///< Stop bit, see description of #en_mfs_stopbit_t on mfs.h + uint8_t u8CharLength; ///< 5..9 Bit Character Length, see description of #en_mfs_characterlength_t on mfs.h + uint8_t u8FifoUsage; ///< Usage of MFS FIFO, see description of #en_mfs_hl_fifo_usage_t + mfs_hl_rx_cb_func_ptr_t pfnRxCb; ///< Callback function, if RX Buffer is filled more than u16RxCbBufFillLvl + mfs_hl_tx_cb_func_ptr_t pfnTxCb; ///< Callback function, if TX Buffer is empty +} stc_mfs_hl_uart_config_t; + +/** + ****************************************************************************** + ** \brief MFS_HL SPI configuration. + ** + ** Contains all parameter for configuratin a MFS channel, if set to CSIO mode. + ******************************************************************************/ +typedef struct stc_mfs_hl_spi_config +{ + boolean_t bCsLevel; /**< Chip select active level + - TRUE: Chip select active HIGH(in-active LOW) + - FALSE: Chip select active LOW (in-active HIGH) */ + uint16_t u16CsDeSelect; ///< Chip de-select bit + uint8_t u8CsSetDelay; ///< Chip select setup delay + uint8_t u8CsHoldDelay; ///< Chip select hold delay + uint8_t u8CsDivision; ///< Setting for Chip select timing divider +} stc_mfs_hl_spi_config_t; + +/** + ****************************************************************************** + ** \brief MFS_HL Timer mode configuration. + ** + ** Contains all parameter for configuratin a MFS channel, if set to CSIO mode. + ******************************************************************************/ +typedef struct stc_mfs_hl_timer_config +{ + boolean_t bTimerSyncEnable; ///< TRUE: Enable synchronous tansfer, FALSE: Disable synchronous transfer + uint16_t u16SerialTimer; ///< Serial timer value. If chip select disables and this value is not zero serial timer is activate. + uint8_t u8TimerDivision; ///< Setting for serial timer divider + uint8_t u8TxByte; ///< Transfer length when timer mode. This is used if bTimerSyncEnable is TRUE. +} stc_mfs_hl_timer_config_t; + +/** + ****************************************************************************** + ** \brief MFS_HL CSIO configuration. + ** + ** Contains all parameter for configuratin a MFS channel, if set to CSIO mode. + ******************************************************************************/ +typedef struct stc_mfs_hl_csio_config +{ + uint32_t u32DataRate; ///< Baud rate (bps) + boolean_t bBitDirection; ///< TRUE: MSB first, FALSE: LSB first + boolean_t bSignalSystem; ///< TRUE: SCK Mark Level Low, FALSE: SCK Mark Level High + stc_mfs_hl_spi_config_t* pstcMfsSpiCsConfig; ///< See description of #stc_mfs_hl_spi_config_t. Only applicable when u8CsioActMode is MfsCsioActSpiMode + stc_mfs_hl_timer_config_t* pstcMfsTimerConfig; ///< See description of #stc_mfs_hl_timer_config_t. Only applicable when u8CsioMode is MfsCsioMaster. + uint8_t* pu8TxBuf; ///< Data store for transmit buffer. + uint8_t* pu8RxBuf; ///< Char store for receive buffer. + uint16_t u16TxBufSize; ///< Size of transmit fifo buffer. + uint16_t u16RxBufSize; ///< Size of receive fifo buffer. + uint16_t u16RxCbBufFillLvl; ///< Unread counts of data buffer to call RX Callback function + uint8_t u8CsioMode; ///< CSIO mode, see description of #en_mfs_csio_mode_t on mfs.h + uint8_t u8CsioActMode; ///< CSIO active mode, see description of #en_mfs_csio_act_mode_t on mfs.h + uint8_t u8SyncWaitTime; ///< Sync wait time insersion, see description of #en_mfs_csio_sync_wait_time_t on mfs.h + uint8_t u8CharLength; ///< 5..32 Bit Character Length, see description of #en_mfs_characterlength_t + uint8_t u8FifoUsage; ///< Usage of MFS FIFO, see description of #en_mfs_hl_fifo_usage_t + mfs_hl_rx_cb_func_ptr_t pfnRxCb; ///< Callback function, if RX Buffer is filled specified bytes of u16RxCbBufFillLvl + mfs_hl_tx_cb_func_ptr_t pfnTxCb; ///< Callback function, if TX Buffer is empty +} stc_mfs_hl_csio_config_t; + +/** + ****************************************************************************** + ** \brief MFS_HL I2C configuration. + ** + ** Contains all parameter for configuratin a MFS channel, if set to I2C mode. + ******************************************************************************/ +typedef struct stc_mfs_hl_i2c_config +{ + uint32_t u32DataRate; ///< Baud rate (bps) + uint8_t u8I2cMode; ///< I2C mode, see description of #en_mfs_i2c_mode_t on mfs.h + uint8_t u8SlvAddr; ///< Slave address (This is effective on slave mode.) + uint8_t u8FastMode; ///< Fast mode, see description of #en_mfs_i2c_fast_mode_t. on mfs.h + uint8_t u8FifoUsage; ///< Usage of MFS FIFO, see description of #en_mfs_hl_fifo_usage_t + mfs_hl_rx_cb_func_ptr_t pfnRxCb; ///< Callback function, if RX process is completed + mfs_hl_tx_cb_func_ptr_t pfnTxCb; ///< Callback function, if TX process is completed + mfs_hl_i2c_slv_cb_func_prt_t pfnI2cSlvStCb; ///< Callback function, if slave address is detected. This is used for Slave mode. +} stc_mfs_hl_i2c_config_t; + +/** + ****************************************************************************** + ** \brief MFS_HL LIN configuration. + ** + ** Contains all parameter for configuratin a MFS channel, if set to LIN mode. + ** This configuration was rolled-out from #stc_mfs_hl_lin_config_t to save RAM + ** memory since LIN is a special mode. Only use functions with prefix + ** 'Mfs_Hl_Lin_'! + ******************************************************************************/ +typedef struct stc_mfs_hl_lin_config +{ + uint32_t u32DataRate; ///< Baud rate (bps) + boolean_t bExtWakeUp; ///< TRUE: Sets external wake-up function + boolean_t bLinBreakIrqEnable; ///< TRUE: Enable LIN break receptioninterrupt + uint8_t* pu8TxBuf; ///< Data store for transmit buffer. + uint8_t* pu8RxBuf; ///< Char store for receive buffer. + uint16_t u16TxBufSize; ///< Size of transmit fifo buffer. + uint16_t u16RxBufSize; ///< Size of receive fifo buffer. + uint8_t u8LinMode; ///< LIN mode, see #en_mfs_lin_mode_t (mfs.h) for details + uint8_t u8StopBits; ///< Stop bits length, see description of #en_mfs_stopbit_t on mfs.h + uint8_t u8BreakLength; ///< Break length, see description of #en_mfs_lin_break_length_t on mfs.h. Only applicable in LIN master mode + uint8_t u8DelimiterLength; ///< Delimiter length, see description of #en_mfs_lin_delimiter_length_t on mfs.h + uint8_t u8FifoUsage; ///< Usage of MFS FIFO, see description of #en_mfs_hl_fifo_usage_t + mfs_hl_rx_cb_func_ptr_t pfnRxCb; ///< Callback function, if RX Buffer is full + mfs_hl_tx_cb_func_ptr_t pfnTxCb; ///< Callback function, if TX Buffer is empty + mfs_hl_lin_brk_func_ptr_t pfnLinBrkCb; ///< Callback function, if LIN break was detected +} stc_mfs_hl_lin_config_t; + +/** + ****************************************************************************** + ** \brief Get the poitner to internal RX or TX buffer. + ** + ** The buffer information can be gotten with this pointer. + ******************************************************************************/ +typedef enum en_mfs_hl_buffer +{ + MfsHlRxBuffer = 0u, ///< MFS high level RX buffer + MfsHlTxBuffer = 1u, ///< MFS high level TX buffer + +}en_mfs_hl_buffer_t; + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ +/// MFS_HL module internal data, storing internal information for each enabled MFS instance. +typedef struct stc_mfs_hl_intern_data +{ + mfs_hl_tx_cb_func_ptr_t pfnTransmitCbFunction; ///< Transmission complete callback function + mfs_hl_rx_cb_func_ptr_t pfnReceiveCbFunction; ///< Receive callback function + mfs_hl_i2c_slv_cb_func_prt_t pfnI2cSlvStCbFunction; ///< Starting I2C slave callback function. + mfs_hl_lin_brk_func_ptr_t pfnLinBreakCbFunction; ///< LIN break detection callback function + stc_mfs_hl_buffer_t stcRxBuffer; ///< Store location for receive Fifo buffer + stc_mfs_hl_buffer_t stcTxBuffer; ///< Store location for transmission Fifo buffer + uint32_t u32I2cProcCnt; ///< TX or RX processing count for polling (for I2C) + uint16_t u16RxCallbackBufFillLevel; ///< Unread counts of data buffer to call RX Callback function + uint8_t u8FifoUsage; ///< Usage of MFS FIFO, see description of #en_mfs_hl_fifo_usage_t + uint8_t u8MfsMode; ///< Usage of MFS, see description of #en_mfs_hl_mfs_mode_t + uint8_t u8Exec; ///< Execution status, see description of #en_mfs_hl_exec_t + uint8_t u8DataWidth; ///< Data width +} stc_mfs_hl_intern_data_t; + +/// MFS_HL instance data type +typedef struct stc_mfs_hl_instance_data +{ + volatile stc_mfsn_t* pstcInstance; ///< pointer to registers of an instance + stc_mfs_hl_intern_data_t stcInternData; ///< module internal data of instance +} stc_mfs_hl_instance_data_t; + +/******************************************************************************/ +/* Global variable definitions ('extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes (definition in C source) */ +/******************************************************************************/ +/* for UART */ +/* Init/Deinit */ +extern en_result_t Mfs_Hl_Uart_Init(volatile stc_mfsn_t* pstcUart, + stc_mfs_hl_uart_config_t* pstcConfig + ); + +extern en_result_t Mfs_Hl_Uart_DeInit(volatile stc_mfsn_t* pstcUart); + +/* for CSIO */ +/* Init/Deinit */ +extern en_result_t Mfs_Hl_Csio_Init(volatile stc_mfsn_t* pstcCsio, + stc_mfs_hl_csio_config_t* pstcConfig + ); + +extern en_result_t Mfs_Hl_Csio_DeInit(volatile stc_mfsn_t* pstcCsio); + +/* Data Transfer */ +extern en_result_t Mfs_Hl_Csio_SynchronousTrans(volatile stc_mfsn_t* pstcCsio, + const uint8_t* pu8TxData, + uint8_t* pu8RxData, + uint16_t u16TransferSize, + boolean_t bCsHolding + ); + +/* for LIN */ +/* Init/Deinit */ +extern en_result_t Mfs_Hl_Lin_Init(volatile stc_mfsn_t* pstcLin, + stc_mfs_hl_lin_config_t* pstcConfig + ); + +extern en_result_t Mfs_Hl_Lin_DeInit(volatile stc_mfsn_t* pstcLin); + +/* Set configuration */ +extern en_result_t Mfs_Hl_Lin_SetBreak(volatile stc_mfsn_t* pstcLin); + +extern en_result_t Mfs_Hl_Lin_SetNewBaudDivisor(volatile stc_mfsn_t* pstcLin, + uint16_t u16BaudDivisor + ); + +extern en_result_t Mfs_Hl_Lin_DisableRxInterrupt(volatile stc_mfsn_t* pstcLin); + +/* Data Transfer */ +extern en_result_t Mfs_Hl_Lin_TransferRxBuffer(volatile stc_mfsn_t* pstcLin, + uint8_t* pu8Data, + uint16_t u16ReadCount + ); + +/* for I2C */ +/* Init/Deinit */ +extern en_result_t Mfs_Hl_I2c_Init(volatile stc_mfsn_t* pstcI2c, + stc_mfs_hl_i2c_config_t* pstcConfig + ); + +extern en_result_t Mfs_Hl_I2c_DeInit(volatile stc_mfsn_t* pstcI2c); + +/* Data Transfer */ +extern en_result_t Mfs_Hl_I2c_Write(volatile stc_mfsn_t* pstcI2c, + uint8_t u8SlaveAddr, + uint8_t* pu8Data, + uint16_t* pu16WriteCnt, + boolean_t bBlocking + ); + +extern en_result_t Mfs_Hl_I2c_Read(volatile stc_mfsn_t* pstcI2c, + uint8_t u8SlaveAddr, + uint8_t* pu8Data, + uint16_t* pu16ReadCnt, + boolean_t bBlocking + ); + +extern en_result_t Mfs_Hl_I2c_WaitTxComplete(volatile stc_mfsn_t* pstcI2c, + uint32_t u32MaxCnt + ); + +extern en_result_t Mfs_Hl_I2c_WaitRxComplete(volatile stc_mfsn_t* pstcI2c, + uint32_t u32MaxCnt + ); + +/* for Common(UART/CSIO/LIN) */ +/* Data Transfer */ +extern en_result_t Mfs_Hl_Read(volatile stc_mfsn_t* pstcMfs, + uint8_t* pu8Data, + uint16_t* pu16DataCnt, + uint16_t u16ReadCnt, + boolean_t bBlocking + ); + +extern en_result_t Mfs_Hl_Write(volatile stc_mfsn_t* pstcMfs, + uint8_t* pu8Data, + uint16_t u16WriteCnt, + boolean_t bBlocking, + boolean_t bCsHolding + ); +/* Get the RX/TX buffer pointer */ +extern en_result_t Mfs_Hl_GetBufferPointer(volatile stc_mfsn_t* pstcMfs, + en_mfs_hl_buffer_t enBufIndex, + stc_mfs_hl_buffer_t** ppstcBuffer); + +//@} // MfshlGroup + +#ifdef __cplusplus +} +#endif + +#endif /* #if (defined(PDL_PERIPHERAL_MFS_ACTIVE)) */ + +#endif /* __MFS_H__ */ +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcard.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcard.c new file mode 100644 index 0000000000..aab070e0ed --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/highlevel/sd/sdcard.c @@ -0,0 +1,424 @@ +/******************************************************************************* +* Copyright (C) 2013 Spansion LLC. All Rights Reserved. +* +* This software is owned and published by: +* Spansion LLC, 915 DeGuigne Dr. Sunnyvale, CA 94088-3453 ("Spansion"). +* +* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +* +* This software contains source code for use with Spansion +* components. This software is licensed by Spansion to be adapted only +* for use in systems utilizing Spansion components. Spansion shall not be +* responsible for misuse or illegal use of this software for devices not +* supported herein. Spansion is providing this software "AS IS" and will +* not be responsible for issues arising from incorrect user implementation +* of the software. +* +* SPANSION MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +* REGARDING THE SOFTWARE (INCLUDING ANY ACOOMPANYING WRITTEN MATERIALS), +* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +* WARRANTY OF NONINFRINGEMENT. +* SPANSION SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +* SAVINGS OR PROFITS, +* EVEN IF SPANSION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +* FROM, THE SOFTWARE. +* +* This software may be replicated in part or whole for the licensed use, +* with the restriction that this Disclaimer and Copyright notice must be +* included with each copy of this software, whether used in part or whole, +* at all times. +*/ +/******************************************************************************/ +/** \file sdcard.c + ** + ** History: + ** - 2013-05-16 1.0 QXu First version. + ** - 2013-07-24 1.1 RQian Modification. + ** - 2014-01-28 1.2 MWi Some comment and code beautifying + ** + ******************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ +#include "sdcard.h" +#include + +#if (defined(PDL_PERIPHERAL_SD_ACTIVE)) + +/** + ****************************************************************************** + ** \addtogroup SdifGroup + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ +#define SD_DLY_1UNIT 8000 + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions ('static') */ +/******************************************************************************/ +static uint32_t m_u32NumSector; + +/******************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local Functions */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief Sd card delay function + ** + ** \param [in] u32Delay Delay interval + ** + ******************************************************************************/ +static void SdDly_1unit (uint32_t u32Delay) +{ + volatile uint32_t u32i; + for(;u32Delay;--u32Delay) + { + for(u32i = SD_DLY_1UNIT;u32i;--u32i); + } +} + +/******************************************************************************/ +/* Global Functions */ +/******************************************************************************/ +/** + ****************************************************************************** + ** \brief detect SD + ** + ** \retval TRUE The SD card is inserted + ** \retval FALSE The SD card is non-existent + ** + ******************************************************************************/ +boolean_t Sdcard_Detect(void) +{ + if (INSERTED == Sd_CardDetect(&Sd_stcCfg)) + { + return TRUE; + } + + return FALSE; +} + +/** + ****************************************************************************** + ** \brief SD card initialization + ** + ** \param [in] pstcSdcardReg SD card information + ** + ** \retval E_SD_NO_CARD SD card is removed + ** \retval E_SD_INIT SD card initialization is failed + ** \retval E_SD_OK SD card is initialized and ready SRESP1 + ** + ******************************************************************************/ +int32_t Sdcard_Init(stc_sdcard_info_t *pstcSdcardReg) +{ + stc_csdver1_t *pstcCsdSd; + stc_csdver2_t *pstcCsdSdHc; + uint32_t u32ArgAcd41 = 0; + uint32_t u32Buf[4]={0}; + boolean_t result = FALSE; + uint8_t u8Flag = 1;//1: Support High capacity; 0: not support + volatile uint8_t u8Retry = 0; + uint32_t i; + uint32_t u32Csize; + uint32_t u32CsizeMulti; + + if(NULL == pstcSdcardReg) + { + return E_SD_PARAMETER; + } + + pstcCsdSd = (stc_csdver1_t*)pstcSdcardReg->CSD; + pstcCsdSdHc = (stc_csdver2_t*)pstcSdcardReg->CSD; + + if(Sdcard_Detect() == FALSE) return E_SD_NO_CARD; + + result = Sdcmd_SendCmd(SD_CMD0, 0, u32Buf); + if(FALSE == result) + { + Sd_HostDeInit(); + return E_SD_INIT; + } + + result = Sdcmd_SendCmd(SD_CMD8,ARG_CMD8,u32Buf); + if (FALSE == result) { + Sd_HostDeInit(); + return E_SD_INIT; + } + for (i = 0; i < CMD8_WAIT; i++) + {} + + //<3.Get OCR + u8Retry = 0; + memset(u32Buf,0,sizeof(u32Buf)); + + do + { + u8Retry++; + SdDly_1unit(100); + result =Sdcmd_SendCmd(SD_CMD55,0,u32Buf); + + if(result == TRUE) + { + u32ArgAcd41 =( (u8Flag == 1)? ARG_ACMD41_HCS_ON : ARG_ACMD41_HCS_OFF ); + Sdcmd_SendCmd(SD_ACMD41, u32ArgAcd41, u32Buf); + } + }while((0 == (u32Buf[0]&ARG_ACMD41_BUSY))&&(u8Retry < 10)); + + if(u8Retry >= 10) + { + return E_SD_INIT; + } + pstcSdcardReg->OCR = u32Buf[0]; + + if(0 != (u32Buf[0] & OCR_CAPACITY_MASK )) //need to verify + { + pstcSdcardReg->stcCardType.u8Capacity = SD_CAPACITY_HIGH ; + } + else + { + pstcSdcardReg->stcCardType.u8Capacity = SD_CAPACITY_STANDARD; + } + if(FALSE == result) + { + return E_SD_INIT; + } + + SdDly_1unit(5); + + //<4.Get CID + memset(u32Buf,0,sizeof(u32Buf)); + if(Sdcmd_SendCmd(SD_CMD2,0,u32Buf) == TRUE) + { + for(i=0;i<15;i++) + { + /* Response data 127:8 is stored in Response reg: 119:0 */ + /* Make clear of LSB/MSB */ + pstcSdcardReg->CID[i] = *((uint8_t *)(u32Buf) + (14 - i)); + } + } + else + { + return E_SD_INIT; + } + + //<5.Get RCA + memset(u32Buf,0,sizeof(u32Buf)); + if(Sdcmd_SendCmd(SD_CMD3,0,u32Buf) == TRUE) + { + pstcSdcardReg->RCA = u32Buf[0] >> 16; + } + else + { + return E_SD_INIT; + } + + //<6.Get CSD + memset(u32Buf,0,sizeof(u32Buf)); + if(TRUE == Sdcmd_SendCmd(SD_CMD9,pstcSdcardReg->RCA<<16,u32Buf)) + { + for(i=0;i<15;i++) + { + /* Response data 127:8 is stored in Response reg: 119:0 */ + /* Make clear of LSB/MSB */ + pstcSdcardReg->CSD[i] = *((uint8_t *)(u32Buf) + (14 - i)); + } + } + else + { + return E_SD_INIT; + } + + /* *** High Capacity *** */ + if(SD_CAPACITY_HIGH == pstcSdcardReg->stcCardType.u8Capacity) + { + /* number of sectors */ + u32Csize = ((unsigned int)pstcCsdSdHc->u8C_size1 << 16) + ((unsigned int)pstcCsdSdHc->u8C_size2 << 8) + pstcCsdSdHc->u8C_size3; + m_u32NumSector = (u32Csize + 1) * 1024; + } + /* *** Standard Capacity ***/ + else{ + /* number of sectors */ + u32Csize = ((unsigned int)pstcCsdSd->u8C_size1 << 10) + ((unsigned int)pstcCsdSd->u8C_size2 << 2) + pstcCsdSd->u8C_size3; + u32CsizeMulti = (pstcCsdSd->u8C_size_multi1 << 1) + pstcCsdSd->u8C_size_multi2; + m_u32NumSector = (u32Csize + 1) << (u32CsizeMulti + 2); + + if(pstcCsdSd->u8Read_bl_len == 0x0A ){ + m_u32NumSector *= 2; + } + else if(pstcCsdSd->u8Read_bl_len == 0x0B ){ + m_u32NumSector *= 4; + } + } + pstcSdcardReg->u32MaxSectorNum = m_u32NumSector; + + //<7.Select Card + if(Sdcmd_SendCmd(SD_CMD7, pstcSdcardReg->RCA<<16, u32Buf) == TRUE) + { + return E_SD_OK; + } + else + { + return E_SD_INIT; + } +} + +/** + ****************************************************************************** + ** \brief read one or multiple sectors of data + ** + ** This function read the data and store into buffer + ** + ** + ** \param [in] pstcSdcardInfo SD card information + ** \param [in] u32Start Data address to read + ** \param [in] u16Count Sector number to read + ** \param [in] pu8Buf Data buffer + ** + ** \retval E_SD_NO_CARD SD card is removed + ** \retval E_SD_PARAMETER Parameters are not valid + ** \retval E_SD_READ Read error + ** \retval E_SD_OK SD card accessing is OK + ** + ******************************************************************************/ +int32_t Sdcard_ReadSector(stc_sdcard_info_t *pstcSdcardInfo, uint32_t u32Start, uint16_t u16Count, uint8_t *pu8Buf) +{ + uint32_t u32addr; + uint32_t u32i; + boolean_t result = FALSE; + uint32_t u32start_addr = u32Start; + uint32_t u32maxsectornum = pstcSdcardInfo->u32MaxSectorNum; + uint32_t u32buf[4] = {0}; + uint32_t *pu32 = (uint32_t*)pu8Buf; + + if(Sdcard_Detect() == FALSE) return E_SD_NO_CARD; + + if((pstcSdcardInfo ==NULL)||(u16Count == 0)||(u32Start+u16Count>u32maxsectornum)||(u32Start>u32maxsectornum)) + { + return E_SD_PARAMETER; + } + + if(SD_CAPACITY_STANDARD == pstcSdcardInfo->stcCardType.u8Capacity) + { + u32addr = u32start_addr<<9; ///u32MaxSectorNum; + uint32_t u32buf[4] = {0}; + uint32_t *pu32 = (uint32_t*)pu8Buf; + + if(Sdcard_Detect() == FALSE) return E_SD_NO_CARD; + + if((pstcSdcardInfo ==NULL)||(u16Count == 0)||(u32Start+u16Count>u32maxsectornum)||(u32Start>u32maxsectornum)) + { + return E_SD_PARAMETER; + } + + if(SD_CAPACITY_STANDARD == pstcSdcardInfo->stcCardType.u8Capacity) + { + u32addr = u32start_addr << 9; ///= FM3 + ** - 2012-11-26 1.4 MSc Data received routine added + ** - 2013-01-30 1.5 MSc DMA routines added + ** - 2013-04-24 1.6 MSc Data sent handle added + ** - 2013-10-14 1.7 MSc PDL support added + ** - 2014-08-25 1.8 MSc Polled data changed to IRQ transfer + ** USE_DTR_FOR_CONNECT to enable/disable DTR + ** USBDEVICECDCCOM_USE_PRINTF to enable printf + ** - 2015-09-04 1.9 MSCH Usb_WaitHook() added + *****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "UsbDeviceCdcCom.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICECDCCOM_ENABLED == ON)) + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +static const char_t pcASCII[] = "0123456789ABCDEF"; + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +static volatile uint8_t DataReceivedFlags = 0; //Status for received data +static volatile uint8_t DataSentFlags = 0xFF; //Status for sent data +static uint8_t pu8VcommBuffer[USBDEVICECDCCOM_MAX_RECEIVE_BUFFER]; +static stc_cdc_linecoding_t stcLineCoding = {9600,USBCLASSCDC_CHARFORMAT_1STOPBIT,USBCLASSCDC_PARITYTYPE_NONE,8}; +static uint8_t pu8LineCoding[8]; +static boolean_t bEchoMode = FALSE; +static boolean_t bEchoAtSeperatorOnly = FALSE; +static volatile boolean_t bVcommActive = FALSE; +static boolean_t bSeperatorFlag = FALSE; +static char_t cSeperator = '\0'; +static volatile uint32_t u32ReceivedData = 0; +static uint8_t pu8IngoingBuffer[USBDEVICECDCCOM_EPOUT_BUFFERSIZE]; +static boolean_t bReady = FALSE; +static stc_usbn_t* pstcUsbHandle = NULL; +static uint8_t u8ControlInterface = 0; +static stc_cdc_uart_state_t stcSerialState; +static stc_usbn_endpoint_data_t* pstcEndpointControlIN; +static stc_usbn_endpoint_buffer_t stcEndpointBufferControlIN; +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static stc_usbn_endpoint_data_t* pstcEndpointOUT; +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; +static stc_usbn_endpoint_buffer_t stcEndpointBufferOUT; +static usbdevicecdccom_linecodingchange_func_ptr_t pfnLineCodingChange; +static cdc_dtr_changed_t pstnDtrChanged = NULL; +static cdc_rts_changed_t pstnRtsChanged = NULL; +#if (USBDEVICECDCCOM_USE_PRINTF == 1) + char_t tbuf; + + static long brk_siz = 0; + #if HEAP_SIZE + typedef int _heap_t; + #define ROUNDUP(s) (((s)+sizeof(_heap_t)-1)&~(sizeof(_heap_t)-1)) + static _heap_t _heap[ROUNDUP(HEAP_SIZE)/sizeof(_heap_t)]; + #define _heap_size ROUNDUP(HEAP_SIZE) + #else + extern char *_heap; + extern long _heap_size; + #endif +#endif + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb); +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); +static void DecodeSetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup); +static void SetLineCoding(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint); +static void SendLineCoding(void); +static uint32_t ASCIItobin(uint8_t k); +static cdc_data_received_t pstnReceivedData; +static cdc_data_sent_t pstnSentData; + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** \brief Configuration change callback, used to see if configuration is set + ** or cleared + ** + ** \param pstcUsb Pointer to USB instance + ** + ** + ******************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + bReady = TRUE; + } else + { + bReady = FALSE; + } + #if USE_DTR_FOR_CONNECT == 0 + bVcommActive = bReady; + #endif +} + +/** + ****************************************************************************** + ** \brief Receive or transmitted data callback + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** + ******************************************************************************/ +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + volatile uint32_t u32i; + uint8_t* pu8Buffer = pstcEndpoint->pstcEndpointBuffer->pu8Buffer; + uint32_t u32DataSize = pstcEndpoint->pstcEndpointBuffer->u32DataSize; + + if ((pstcEndpoint->u8EndpointAddress) & 0x80) + { + DataSentFlags |= (1<<1); + if (pstnSentData != NULL) + { + pstnSentData(); + } + } + else + { + DataReceivedFlags |= (1<<3); // setting data received flag + if (pstnReceivedData != NULL) + { + pstnReceivedData(pu8Buffer,u32DataSize); + UsbDevice_ReceiveData(pstcUsb, pstcEndpoint, pstcEndpoint->pstcEndpointBuffer->pu8Buffer, pstcEndpoint->pstcEndpointBuffer->u32BufferSize, UsbIRQ); + return; + } + + if ((bEchoMode) && (bVcommActive) && (bEchoAtSeperatorOnly == FALSE)) + { + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, u32DataSize, UsbPOLL); + } + for(u32i=0;u32ipstcEndpointBuffer->pu8Buffer, pstcEndpoint->pstcEndpointBuffer->u32BufferSize, UsbIRQ); + } +} + + +/** + ****************************************************************************** + ** \brief Initialisation callback + ** + ** \param pstcUsb Pointer to USB instance + ** + ** + ******************************************************************************/ +void UsbDeviceCdcCom_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x02; // CDC Class + stcUsbClassConfig.u8InterfaceSubClass = 0x02; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x01; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = DecodeSetupRequest; // setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + u8NumEndpoints = 0; + u8ControlInterface = pu8Interface[2]; + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + stcEndpointConfig.pfnRxTxCallback = NULL; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) != 0) + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferControlIN; + pstcEndpointControlIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + pstcEndpointControlIN->bAutomaticNullTermination = TRUE; + } + u8NumEndpoints++; + } + } + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x0A; // CDC Class + stcUsbClassConfig.u8InterfaceSubClass = 0x00; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x00; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = DecodeSetupRequest; // setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + u8NumEndpoints = 0; + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + stcEndpointConfig.pfnRxTxCallback = RxTxCallback; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferOUT; + pstcEndpointOUT = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8IngoingBuffer, USBDEVICECDCCOM_EPOUT_BUFFERSIZE, UsbIRQ); + } + else + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + u8NumEndpoints++; + } + } +} + +/** + ****************************************************************************** + ** Set DTR changed callback + ** + ** \param pstnCallback callback handle + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SetDtrChangedCallback(cdc_dtr_changed_t pstnCallback) +{ + pstnDtrChanged = pstnCallback; +} + +/** + ****************************************************************************** + ** Set RTS changed callback + ** + ** \param pstnCallback callback handle + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SetRtsChangedCallback(cdc_rts_changed_t pstnCallback) +{ + pstnRtsChanged = pstnCallback; +} + +/** + ****************************************************************************** + ** Set received callback + ** + ** \param pstnCallback callback handle + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SetReceivedCallback(cdc_data_received_t pstnCallback) +{ + pstnReceivedData = pstnCallback; +} + +/** + ****************************************************************************** + ** Set sent callback + ** + ** \param pstnCallback callback handle + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SetSentCallback(cdc_data_sent_t pstnCallback) +{ + pstnSentData = pstnCallback; +} + +/** + ****************************************************************************** + ** Is called from main application to send data via endpoint 1 + ** + ** \param pu8Buffer Buffer to send + ** \param u32DataSize Buffersize + ** \param enMode Sending mode: UsbPOLL, UsbIRQ or UsbDMA; + ** + ** \return TRUE: if succesful, FALSE: if usb was not ready + *****************************************************************************/ +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + volatile uint32_t u32Timeout = 100000000; + if (UsbDevice_GetStatus(pstcUsbHandle) == UsbConfigured) + { + while(!(DataSentFlags & (1<<1)) && u32Timeout > 0) + { + Usb_WaitHook(); + u32Timeout--; + } + DataSentFlags &= ~(1<<1); + + while(UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, u32DataSize, enMode) != Ok) + { + Usb_WaitHook(); + } + if (enMode == UsbPOLL) + { + DataSentFlags |= (1<<1); + } + return TRUE; + } + return FALSE; +} + +/** + ****************************************************************************** + ** Check if data was sent + ** + ** \return TRUE if data was sent + *****************************************************************************/ +boolean_t UsbDeviceCdcCom_DataSent(void) +{ + if ((DataSentFlags & (1<<1)) > 0) + { + return TRUE; + } + else + { + return FALSE; + } +} + +/** + ****************************************************************************** + ** Set callback function for LineCoding changed event + ** + ** \param pfnLineCodingChangeCallback Callback handler + *****************************************************************************/ +void UsbDeviceCdcCom_SetCallbackLineCodingChange(usbdevicecdccom_linecodingchange_func_ptr_t pfnLineCodingChangeCallback) +{ + pfnLineCodingChange = pfnLineCodingChangeCallback; +} + +/** + ****************************************************************************** + ** Decode setup request (class specific) handler + ** + ** \param pstcUsb USB handle + ** + ** \param pstcSetup pointer of setup request + *****************************************************************************/ +static void DecodeSetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup) +{ + switch (pstcSetup->bRequest) + { + case SET_LINE_CODING: + UsbDevice_ReceiveDataControl(pstcUsb,SetLineCoding); + UsbDevice_SendDataControl(pstcUsbHandle,(uint8_t *)NULL, 0); + return; + case GET_LINE_CODING: + SendLineCoding(); + return; + case SET_CONTROL_LINE_STATE: + if (pstnRtsChanged != NULL) + { + pstnRtsChanged((pstcSetup->wValue & 0x02) != 0); + } + + if (pstnDtrChanged != NULL) + { + pstnDtrChanged((pstcSetup->wValue & 0x01) != 0); + } + + #if USE_DTR_FOR_CONNECT == 1 + if (pstcSetup->wValue & 0x01) + { + bVcommActive = TRUE; + } + else + { + bVcommActive = FALSE; + } + #endif + if (pstcSetup->wValue & 0x02) + { + + } + else + { + + } + UsbDevice_SendDataControl(pstcUsbHandle,(uint8_t *)NULL, 0); + return; + default: + UsbDevice_SendDataControl(pstcUsbHandle,(uint8_t *)NULL, 0); + return; + } +} + +/** + ****************************************************************************** + ** Update serial state + ** + ** \param pstcState Set specified bits + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SerialStateSet(stc_cdc_uart_state_t* pstcState) +{ + uint8_t au8Data[10]; + stcSerialState.u16UartState |= pstcState->u16UartState; + au8Data[0] = 0xA1; + au8Data[1] = SERIAL_STATE; + au8Data[2] = 0; + au8Data[3] = 0; + au8Data[4] = u8ControlInterface; + au8Data[5] = 0; + au8Data[6] = 2; + au8Data[7] = 0; + au8Data[8] = (uint8_t)(stcSerialState.u16UartState & 0xFF); + au8Data[9] = (uint8_t)(stcSerialState.u16UartState >> 8); + while(UsbDevice_SendData(pstcUsbHandle, pstcEndpointControlIN, &au8Data[0], 10, UsbPOLL) != Ok) + { + Usb_WaitHook(); + } +} + +/** + ****************************************************************************** + ** Update serial state + ** + ** \param pstcState Clear specified bits + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SerialStateClear(stc_cdc_uart_state_t* pstcState) +{ + uint8_t au8Data[10]; + stcSerialState.u16UartState &= ~(pstcState->u16UartState); + au8Data[0] = 0xA1; + au8Data[1] = SERIAL_STATE; + au8Data[2] = 0; + au8Data[3] = 0; + au8Data[4] = u8ControlInterface; + au8Data[5] = 0; + au8Data[6] = 2; + au8Data[7] = 0; + au8Data[8] = (uint8_t)(stcSerialState.u16UartState & 0xFF); + au8Data[9] = (uint8_t)(stcSerialState.u16UartState >> 8); + while(UsbDevice_SendData(pstcUsbHandle, pstcEndpointControlIN, &au8Data[0], 10, UsbPOLL) != Ok) + { + Usb_WaitHook(); + } +} + +/** + ****************************************************************************** + ** Update serial state + ** + ** \param pstcState Set this state + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SerialStateUpdate(stc_cdc_uart_state_t* pstcState) +{ + uint8_t au8Data[10]; + stcSerialState.u16UartState = pstcState->u16UartState; + au8Data[0] = 0xA1; + au8Data[1] = SERIAL_STATE; + au8Data[2] = 0; + au8Data[3] = 0; + au8Data[4] = u8ControlInterface; + au8Data[5] = 0; + au8Data[6] = 2; + au8Data[7] = 0; + au8Data[8] = (uint8_t)(stcSerialState.u16UartState & 0xFF); + au8Data[9] = (uint8_t)(stcSerialState.u16UartState >> 8); + while(UsbDevice_SendData(pstcUsbHandle, pstcEndpointControlIN, &au8Data[0], 10, UsbPOLL) != Ok) + { + Usb_WaitHook(); + } +} + +/** + ****************************************************************************** + ** Get serial state + ** + ** \param pstcState returned state + ** + *****************************************************************************/ +void UsbDeviceCdcCom_SerialStateGet(stc_cdc_uart_state_t* pstcState) +{ + pstcState->u16UartState = stcSerialState.u16UartState; +} +/** + ****************************************************************************** + ** callback for data package of setup request "SET_LINE_CODING" + ** + ** \param pstcUsb USB handle + ** + ** \param pstcEndpoint endpoint handle of received data + ** + *****************************************************************************/ +static void SetLineCoding(stc_usbn_t* pstcUsb, stc_usbn_endpoint_data_t* pstcEndpoint) +{ + static uint8_t pu8Buffer[8]; + static volatile uint32_t u32Rate = 0; + memcpy(pu8Buffer,pstcEndpoint->pstcEndpointBuffer->pu8Buffer,8); + u32Rate = 0; + u32Rate += ((uint32_t)pu8Buffer[3]) << 24; + u32Rate += ((uint32_t)pu8Buffer[2]) << 16; + u32Rate += ((uint32_t)pu8Buffer[1]) << 8; + u32Rate += ((uint32_t)pu8Buffer[0]) << 0; + /*switch(u32Rate) + { + case 110: + break; + case 300: + break; + case 1200: + break; + case 2400: + break; + case 4800: + break; + case 9600: + break; + case 19200: + break; + case 38400: + break; + case 57600: + break; + case 115200: + break; + case 230400: + break; + case 460800: + break; + case 921600: + break; + default: + u32Rate = u32Rate; + return; + }*/ + stcLineCoding.dwDTERate = u32Rate; + stcLineCoding.bCharFormat = pu8Buffer[4]; + stcLineCoding.bParityType = pu8Buffer[5]; + stcLineCoding.bDataBits = pu8Buffer[6]; + if (pfnLineCodingChange != NULL) + { + pfnLineCodingChange(&stcLineCoding); + } + +} +/** + ****************************************************************************** + ** answer for request "GET_LINE_CODING" + ** + *****************************************************************************/ +static void SendLineCoding(void) +{ + pu8LineCoding[3] = (uint8_t)((stcLineCoding.dwDTERate >> 24) & 0xFF); + pu8LineCoding[2] = (uint8_t)((stcLineCoding.dwDTERate >> 16) & 0xFF); + pu8LineCoding[1] = (uint8_t)((stcLineCoding.dwDTERate >> 8) & 0xFF); + pu8LineCoding[0] = (uint8_t)((stcLineCoding.dwDTERate >> 0) & 0xFF); + pu8LineCoding[4] = stcLineCoding.bCharFormat; + pu8LineCoding[5] = stcLineCoding.bParityType; + pu8LineCoding[6] = stcLineCoding.bDataBits; + UsbDevice_SendDataControl(pstcUsbHandle,(uint8_t *)pu8LineCoding, 8); + +} + + + +/** + ****************************************************************************** + ** getting vcomm connection status + ** + ** \return TRUE: active / FALSE: inactive + *****************************************************************************/ +boolean_t UsbDeviceCdcCom_IsConnected(void) +{ + return (bVcommActive && bReady); +} + + +/** + ****************************************************************************** + ** sending byte / char_t + ** + ** \param c byte / char_t to send + ** + ** \return 1: error vcomm inactive / 0: successful sent + *****************************************************************************/ + +uint8_t UsbDeviceCdcCom_SendByte(char_t c) +{ + if (bVcommActive) + { + SendData((uint8_t*)&c,1,UsbIRQ); + return 0; + } + return 1; +} + + +/** + ****************************************************************************** + ** sending a null terminated string + ** + ** \param pcBuffer string to send + ** + ** \return 1: error vcomm inactive / 0: successful sent + *****************************************************************************/ + +uint8_t UsbDeviceCdcCom_SendString(char_t *pcBuffer) +{ + volatile uint32_t u32Size; + if (bVcommActive) + { + for(u32Size=0;(pcBuffer[u32Size] != '\0');u32Size++); //calculating size + + SendData((uint8_t *)pcBuffer,u32Size,UsbIRQ); + return 0; + } + return 1; +} + + +/** + ****************************************************************************** + ** sending a buffer + ** + ** \param pu8Buffer buffer to send + ** \param u32Size buffersize + ** + ** \return 1: error vcomm inactive / 0: successful sent + *****************************************************************************/ + +uint8_t UsbDeviceCdcCom_SendBuffer(uint8_t *pu8Buffer, uint32_t u32Size) +{ + if (bVcommActive) + { + #if USB_USES_DMA == ON + SendData((uint8_t *)pu8Buffer,u32Size,UsbDMA); + #else + SendData((uint8_t *)pu8Buffer,u32Size,UsbIRQ); + #endif + return 0; + } + return 1; +} + + +/** + ****************************************************************************** + ** splits the buffer at a defined character + ** + ** \param cNewSeperator split buffer every newSeparator + ** if zerro, ignore splitting (default) + ** + ** \return 1: error vcomm inactive / 0: successful sent + *****************************************************************************/ + +void UsbDeviceCdcCom_SetSeparator(const char_t cNewSeperator) +{ + cSeperator = cNewSeperator; +} + + +/** + ****************************************************************************** + ** echoes every received char + ** + ** \param bEchoOnOff switch echo on/off + ** + *****************************************************************************/ + +void UsbDeviceCdcCom_SetEchomode(boolean_t bEchoOnOff) +{ + bEchoMode = bEchoOnOff; +} + +/** + ****************************************************************************** + ** echoes every received char after receiving defined seperator + ** + ** \param bEchoAtSeperatorOnlyOnOff switch echo on/off + ** + *****************************************************************************/ + +void UsbDeviceCdcCom_SetEchoAtSeperatorOnly(boolean_t bEchoAtSeperatorOnlyOnOff) +{ + bEchoAtSeperatorOnly = bEchoAtSeperatorOnlyOnOff; +} + +/** + ****************************************************************************** + ** returns number of received bytes in buffer + ** + ** + ** \return number of received bytes in buffer + *****************************************************************************/ + +uint32_t UsbDeviceCdcCom_ReceivedLength(void) +{ + if ((cSeperator == '\0') || (bSeperatorFlag == TRUE)) + { + return u32ReceivedData; + } + return 0; +} + + + +/** + ****************************************************************************** + ** transfer receive buffer and clear it + ** + ** \param pu8Buffer buffer to write in + ** + ** \return buffer size + *****************************************************************************/ + +uint32_t UsbDeviceCdcCom_ReceiveBuffer(uint8_t *pu8Buffer, uint32_t numBytes) /* [andreika]: add numBytes */ +{ + uint32_t u32ReturnValue; + if (u32ReceivedData < numBytes) + numBytes = u32ReceivedData; + for(u32ReturnValue=0;u32ReturnValue 0) + { + return (char_t)pu8VcommBuffer[u32ReceivedData - 1]; + } + return 0; +} + + +/** + ****************************************************************************** + ** sends a x-digit Hex-number (as ASCII charcaters) + ** + ** \param n value + ** \param digits number of hex-digits + ** + ** \return 1: error vcomm inactive / 0: successful sent + *****************************************************************************/ + +uint8_t UsbDeviceCdcCom_SendHex(uint32_t n, uint8_t digits) +{ + uint8_t i,ch,div=0; + + if (UsbDeviceCdcCom_SendString("0x")) return 1; /* hex string */ + div=(digits-1) << 2; /* init shift divisor */ + + for (i=0; i> div) & 0xF;/* get hex-digit value */ + if (UsbDeviceCdcCom_SendByte(pcASCII[ch])) return 1; /* prompt to terminal as ASCII */ + div-=4; /* next digit shift */ + } + return 0; +} + + +/** + ****************************************************************************** + ** sends a decimal-digit + ** + ** \param x value + ** + ** \return 1: error vcomm inactive / 0: successful sent + *****************************************************************************/ + +uint8_t UsbDeviceCdcCom_SendDec(uint32_t x) +{ + int16_t i; + char_t buf[9]; + if (x == 0) + { + if (UsbDeviceCdcCom_SendString(" 0")) return 1; + return 0; + } + buf[8]='\0'; /* end sign of string */ + + for (i=8; i>0; i--) + { + buf[i-1] = pcASCII[x % 10]; + x = x/10; + + } + + for (i=0; buf[i]=='0'; i++) // no print16_t of zero + { + buf[i] = ' '; + } + if (UsbDeviceCdcCom_SendString(buf)) return 1; /* send string */ + return 0; +} + + +/** + ****************************************************************************** + ** 4-bit bin to ascii function + ** + ** \param a value + ** \param base type: HEX / DEC + ** \param fill fill char + ** + *****************************************************************************/ + +void UsbDeviceCdcCom_SendBinAsci4(uint16_t a, uint8_t base, char_t fill) +{ + uint8_t val; + a &= 0x0F; + + switch(base) + { + case HEX: if (a <= 9) UsbDeviceCdcCom_SendByte(a + '0'); + else UsbDeviceCdcCom_SendByte(a + 'A' - 10); + break; + + case DEC: val = a / 10; + if( val ) UsbDeviceCdcCom_SendByte( a / 10 + '0'); + else UsbDeviceCdcCom_SendByte( fill ); + UsbDeviceCdcCom_SendByte( a % 10 + '0'); + break; + + default: UsbDeviceCdcCom_SendString(" "); + } +} + + +/** + ****************************************************************************** + ** 8-bit bin to ascii function + ** + ** \param a value + ** \param base type: HEX / DEC + ** \param fill fill char + ** + *****************************************************************************/ + +void UsbDeviceCdcCom_SendBinAsci8(uint16_t a, uint8_t base, char_t fill) +{ + uint16_t rem,val,d; + uint8_t filling=1; + + switch(base) + { + case HEX: UsbDeviceCdcCom_SendBinAsci4(a >> 4, HEX, fill); + UsbDeviceCdcCom_SendBinAsci4(a, HEX, fill); + break; + + case DEC: rem = a; + for( d=100; d >= 10; d = d / 10) + { + val = rem / d; rem = rem % d; + if( val ) filling=0; + if( filling ) UsbDeviceCdcCom_SendByte( fill ); + else UsbDeviceCdcCom_SendByte( val + '0' ); + } + UsbDeviceCdcCom_SendByte( rem + '0'); + break; + + default: UsbDeviceCdcCom_SendString(" "); + } + +} + + +/** + ****************************************************************************** + ** bin to ascii function + ** + ** \param a value + ** + *****************************************************************************/ + +void UsbDeviceCdcCom_SendBin2DotDec99(uint8_t a) +{ + + uint8_t rem, val; + UsbDeviceCdcCom_SendByte('.'); + + rem = a; + + val = rem / 10; rem = rem % 10; + UsbDeviceCdcCom_SendByte( val + '0' ); + + UsbDeviceCdcCom_SendByte( rem + '0'); + + +} + + +/** + ****************************************************************************** + ** receive hex value + ** + ** \param digits number of digits + ** + ** \return value + *****************************************************************************/ + +uint32_t UsbDeviceCdcCom_ReceiveHex(uint8_t digits) +{ + uint32_t number=0; + signed digit=0; + uint8_t abort=0,mlt=0,i,key; + UsbDeviceCdcCom_SetSeparator('\0'); + UsbDeviceCdcCom_SetEchomode(TRUE); + mlt=(4*(digits-1)); /* 20 for 6 hex-digit numers, 4 for 2 hex-digits */ + for (i=0;i 47) & (k < 58)) d = k - 48; /* 0..9 */ + if ((k > 64) & (k < 71)) d = k - 55; /* A..F */ + if ((k > 96) & (k < 103)) d = k - 87; /* a..f */ + return d; +} + +#if (USBDEVICECDCCOM_USE_PRINTF == 1) + +/** + ****************************************************************************** + ** Low-Level function for printf() + ** + ** \param fileno Filenumber + ** + ** \param buf Buffer + ** + ** \param size Size + ** + *****************************************************************************/ +int __write(int fileno, char *buf, unsigned int size) +{ + unsigned int cnt = size; + switch(fileno) + { + case 0 : + //return(0); /* stdin */ + case 1 : + UsbDeviceCdcCom_SendBuffer((uint8_t*)buf,size); + return(cnt); /* successful output */ + case 2 : + return(-1); /* stderr */ + default: + return(-1); /* should never happend */ + } +} + +/** + ****************************************************************************** + ** \brief low level read function, read characters via UART1 + * carrige return (ASCII:13) is translated into line feed + * and carrige return (ASCII: 10 and 13) + ** \param fileno Filenumber + ** + ** \param buf Buffer + ** + ** \param size Size + ** + ** \return successfull: number of read characters + ** error: -1 + ** + *****************************************************************************/ +int __read( int fileno, char *buf, unsigned int size) { + + unsigned int cnt; + unsigned char helpchar; + switch(fileno) + { + case 0 : + for(cnt = 0;size > cnt;cnt++) /* stdin */ + { + + helpchar = UsbDeviceCdcCom_ReceiveByte(); + if (helpchar == 13) + { + *buf=10; + return(cnt+1); /* successful input */ + } + *buf=helpchar; + buf++; + } + return(cnt); /* successful output */ + case 1 : + return(0); /* stdout */ + case 2 : + return(-1); /* stderr */ + default: + return(-1); /* should never happend */ + } +} + +/** + ****************************************************************************** + ** \brief low-Level function to close specific file + ** + ** \param fileno Filenumber + ** + ** \return successful or error (-1) + ** + *****************************************************************************/ +int __close(int fileno) +{ + if((fileno >= 0) && (fileno <= 2)) + { + return(0); + } + else + { + return(-1); + } +} + +extern char *sbrk(int size) +{ + if (brk_siz + size > _heap_size || brk_siz + size < 0) + return((char*)-1); + brk_siz += size; + return( (char *)_heap + brk_siz - size); +} + + +#endif /* (USBDEVICECDCCOM_USE_PRINTF == 1) */ + +#endif + + + + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCdcCom.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCdcCom.h new file mode 100644 index 0000000000..0f4490ed94 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCdcCom.h @@ -0,0 +1,416 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/*****************************************************************************/ +/** \file UsbDeviceCdcCom.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceCdcComGroup USB Device Cdc Com Module description @endlink + ** + ** History: + ** - 2009-08-31 1.0 MSc First version (works with 16FX) + ** - 2010-04-16 1.1 MSc new USB library added - API had changed + ** - 2011-08-30 1.2 MSc bug fixes while echo data + ** added UsbDeviceCdcCom_SetEchoAtSeperatorOnly for + ** echo data only after seperator received + ** - 2012-07-24 1.3 MSc Version for USB Library >= FM3 + ** - 2012-11-26 1.4 MSc Data received routine added + ** - 2013-01-30 1.5 MSc DMA routines added + ** - 2013-04-24 1.6 MSc Data sent handle added + ** - 2013-10-14 1.7 MSc PDL support added + ** - 2014-08-25 1.8 MSc Polled data changed to IRQ transfer + ** USE_DTR_FOR_CONNECT to enable/disable DTR + ** USBDEVICECDCCOM_USE_PRINTF to enable printf + ** - 2015-09-04 1.9 MSCH Usb_WaitHook() added + *****************************************************************************/ + +#ifndef __USBDEVICECDCCOM_H__ +#define __USBDEVICECDCCOM_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "usb.h" + +#ifndef USBDEVICECDCCOM_ENABLED + #define USBDEVICECDCCOM_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICECDCCOM_ENABLED == ON)) + +#include "UsbDevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceCdcComGroup USB Device Middleware: CDC Com - Virtual Com Port + ** + ** Provided functions of USB module: + ** + ** - UsbDeviceCdcCom_Init() + ** - UsbDeviceCdcCom_DataSent() + ** - UsbDeviceCdcCom_IsConnected() + ** - UsbDeviceCdcCom_SendByte() + ** - UsbDeviceCdcCom_SendString() + ** - UsbDeviceCdcCom_SendBuffer() + ** - UsbDeviceCdcCom_SetSeparator() + ** - UsbDeviceCdcCom_SetEchomode() + ** - UsbDeviceCdcCom_SetEchoAtSeperatorOnly() + ** - UsbDeviceCdcCom_ReceivedLength() + ** - UsbDeviceCdcCom_ReceiveBuffer() + ** - UsbDeviceCdcCom_ReceiveByte() + ** - UsbDeviceCdcCom_ReceiveLastByte() + ** - UsbDeviceCdcCom_SendHex() + ** - UsbDeviceCdcCom_SendDec() + ** - UsbDeviceCdcCom_SendBinAsci4() + ** - UsbDeviceCdcCom_SendBinAsci8() + ** - UsbDeviceCdcCom_SendBin2DotDec99() + ** - UsbDeviceCdcCom_ReceiveHex() + ** - UsbDeviceCdcCom_SetReceivedCallback() + ** - UsbDeviceCdcCom_SetSentCallback() + ** - UsbDeviceCdcCom_SetCallbackLineCodingChange() + ** + ** Emulates UART routines for USB virtual com port + ** + ******************************************************************************/ +//@{ + +/** + ****************************************************************************** + ** \page usbdevicecdccom_module_includes Required includes in main application + ** \brief Following includes are required + ** @code + ** #include "usb.h" + ** #if (USBDEVICECDCCOM_ENABLED == ON) + ** #include "UsbDeviceCdcCom.h" + ** #endif + ** @endcode + ** + ******************************************************************************/ + +/** + ****************************************************************************** + ** \page usbdevicecdccom_module_init Example: Initialization + ** \brief Following initialization is required + ** + ** @code + ** UsbConfig_UsbInit(); + ** @endcode + ** + ******************************************************************************/ + +/** + ****************************************************************************** + ** \page usbdevicecdccom_example_transfer_polled Example: Sending / receiving data polled + ** @code + ** #include "usb.h" + ** #if (USBDEVICECDCCOM_ENABLED == ON) + ** #include "UsbDeviceCdcCom.h" + ** #endif + ** + ** char_t pu8DeviceCdcReceiveBuffer[512]; + ** uint32_t u32DeviceCdcReceiveSize; + ** boolean_t bDeviceCdcComConnected; + ** + ** int main() + ** { + ** UsbConfig_UsbInit(); + ** + ** UsbDeviceCdcCom_SetSeparator('\r'); // there is the possibility to set end of buffer by a seperator + ** UsbDeviceCdcCom_SetEchomode(TRUE); // all input shall be echoed + ** + ** for(;;) + ** { + ** UsbConfig_SwitchMode(); + ** // waiting for a connection + ** if (bDeviceCdcComConnected != UsbDeviceCdcCom_IsConnected()) + ** { + ** bDeviceCdcComConnected = UsbDeviceCdcCom_IsConnected(); + ** if (bDeviceCdcComConnected == TRUE) + ** { + ** // sending welcome message after connection + ** UsbDeviceCdcCom_SendString("\r\n"); + ** UsbDeviceCdcCom_SendString("Welcome to Spansion Virtual Comm Port Example!\r\n"); + ** UsbDeviceCdcCom_SendString("waiting for your message:\r\n"); + ** } + ** } + ** + ** if (UsbDeviceCdcCom_IsConnected()) + ** { + ** if (UsbDeviceCdcCom_ReceivedLength() > 0) + ** { + ** // receive data from buffer + ** u32DeviceCdcReceiveSize = UsbDeviceCdcCom_ReceiveBuffer((uint8_t *)pu8DeviceCdcReceiveBuffer); //this clears also the receive buffer + ** pu8DeviceCdcReceiveBuffer[u32DeviceCdcReceiveSize] = '\0'; //adding zero termination to string + ** + ** //print out pu8DeviceCdcReceiveBuffer through Virtual Comm Port + ** UsbDeviceCdcCom_SendByte('\n'); + ** UsbDeviceCdcCom_SendString("Received String: "); + ** UsbDeviceCdcCom_SendString(pu8DeviceCdcReceiveBuffer); + ** UsbDeviceCdcCom_SendString("\r\n"); + ** } + ** } + ** } + ** } + ** @endcode + ** + ******************************************************************************/ + + /** + ****************************************************************************** + ** \page usbdevicecdccom_example_transfer_irq Example: Sending / receiving data with IRQ + ** @code + ** #include "usb.h" + ** #if (USBDEVICECDCCOM_ENABLED == ON) + ** #include "UsbDeviceCdcCom.h" + ** #endif + ** + ** void DataReceived(uint8_t* pu8Data, uint32_t u32ReceviedSize) + ** { + ** //process the received data pu8Data with size of u32ReceviedSize here + ** } + ** + ** void DataSent(void) + ** { + ** //data was sent + ** } + ** + ** int main() + ** { + ** UsbConfig_UsbInit(); + ** + ** UsbDeviceCdcCom_SetReceivedCallback(DataReceived); + ** UsbDeviceCdcCom_SetSentCallback(DataSent); + ** + ** for(;;) + ** { + ** UsbConfig_SwitchMode(); + ** //... + ** } + ** } + ** @endcode + ** + ******************************************************************************/ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +#define USBDEVICECDCCOM_EPOUT_BUFFERSIZE 128 //buffer Size by default 512 bytes +// [andreika]: +#define USBDEVICECDCCOM_MAX_RECEIVE_BUFFER 1/*512*/ + +#define USBDEVICECDCCOM_USE_UARTCOMMANDS 0 +#define USBDEVICECDCCOM_USE_PRINTF 0 + +#define USE_DTR_FOR_CONNECT 0 + +#if (USBDEVICECDCCOM_USE_PRINTF == 1) + #include +#endif + +/* CDC Management Element Requests */ +#define SEND_ENCAPSULATED_COMMAND 0x00 +#define GET_ENCAPSULATED_RESPONSE 0x01 +#define SET_COMM_FEATURE 0x02 +#define GET_COMM_FEATURE 0x03 +#define CLEAR_COMM_FEATURE 0x04 +#define SET_AUX_LINE_STATE 0x10 +#define SET_HOOK_STATE 0x11 +#define PULSE_SETUP 0x12 +#define SEND_PULSE 0x13 +#define SET_PULSE_TIME 0x14 +#define RING_AUX_JACK 0x15 +#define SET_LINE_CODING 0x20 +#define GET_LINE_CODING 0x21 +#define SET_CONTROL_LINE_STATE 0x22 +#define SEND_BREAK 0x23 +#define SET_RINGER_PARMS 0x30 +#define GET_RINGER_PARMS 0x31 +#define SET_OPERATION_PARMS 0x32 +#define GET_OPERATION_PARMS 0x33 +#define SET_LINE_PARMS 0x34 +#define GET_LINE_PARMS 0x35 +#define DIAL_DIGITS 0x36 +#define SET_UNIT_PARAMETER 0x37 +#define GET_UNIT_PARAMETER 0x38 +#define CLEAR_UNIT_PARAMETER 0x39 +#define GET_PROFILE 0x3A +#define SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x41 +#define GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER 0x42 +#define SET_ETHERNET_PACKET_FILTER 0x43 +#define GET_ETHERNET_STATISTIC 0x44 +#define SET_ATM_DATA_FORMAT 0x50 +#define GET_ATM_DEVICE_STATISTICS 0x51 +#define SET_ATM_DEFAULT_VC 0x52 +#define GET_ATM_VC_STATISTICS 0x53 + + +#define DEC 0 +#define HEX 1 + + +#if (USBDEVICECDCCOM_USE_UARTCOMMANDS == 1) + #define puts(x) UsbDeviceCdcCom_SendString(x) + #define putch(x) UsbDeviceCdcCom_SendByte((uint8_t)x) + #define puthex(x,y) UsbDeviceCdcCom_SendHex(x,y) + #define putdec(x) UsbDeviceCdcCom_SendDec(x) + #define getch() ((char_t)UsbDeviceCdcCom_ReceiveByte()) + #define Inputhex(x) UsbDeviceCdcCom_ReceiveHex(x) + #define binasci8(x,y,z) UsbDeviceCdcCom_SendBinAsci8(x,y,z); + #define binasci4(x,y,z) UsbDeviceCdcCom_SendBinAsci4(x,y,z); + #define bin2_dot_dec99(x) UsbDeviceCdcCom_Send_Bin2DotDec99(x); +#endif + +#define USBCLASSCDC_CHARFORMAT_1STOPBIT 0 +#define USBCLASSCDC_CHARFORMAT_1_5STOPBIT 1 +#define USBCLASSCDC_CHARFORMAT_2STOPBIT 2 + +#define USBCLASSCDC_PARITYTYPE_NONE 0 +#define USBCLASSCDC_PARITYTYPE_ODD 1 +#define USBCLASSCDC_PARITYTYPE_EVEN 2 +#define USBCLASSCDC_PARITYTYPE_MARK 3 +#define USBCLASSCDC_PARITYTYPE_SPACE 4 + +#ifndef SERIAL_STATE +#define SERIAL_STATE 0x20 +#endif +typedef void (*cdc_data_received_t)(uint8_t* pu8Data, uint32_t u32ReceviedSize); +typedef void (*cdc_data_sent_t)(void); +typedef void (*cdc_dtr_changed_t)(boolean_t bNewState); +typedef void (*cdc_rts_changed_t)(boolean_t bNewState); + +typedef struct stc_cdc_linecoding +{ + volatile uint32_t dwDTERate; + volatile uint8_t bCharFormat; + volatile uint8_t bParityType; + volatile uint8_t bDataBits; +} stc_cdc_linecoding_t ; + +typedef struct stc_cdc_control_signal_bitmap +{ + uint16_t DTR:1; + uint16_t RTS:1; + uint16_t RESERVED:14; +} stc_cdc_control_signal_bitmap_t; + +typedef struct stc_cdc_uart_state_bitmap +{ + uint16_t DCD:1; + uint16_t DSR:1; + uint16_t bBreak:1; + uint16_t RI:1; + uint16_t bFraming:1; + uint16_t bParity:1; + uint16_t bOverRun:1; + uint16_t RESERVED:7; +} stc_cdc_uart_state_bitmap_t; + +typedef struct stc_cdc_uart_state +{ + union + { + uint16_t u16UartState; + stc_cdc_uart_state_bitmap_t u16UartState_f; + }; +} stc_cdc_uart_state_t; +typedef void (*usbdevicecdccom_linecodingchange_func_ptr_t)(stc_cdc_linecoding_t* pstcLineCoding); + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + + +void UsbDeviceCdcCom_SerialStateSet(stc_cdc_uart_state_t* pstcState); +void UsbDeviceCdcCom_SerialStateClear(stc_cdc_uart_state_t* pstcState); +void UsbDeviceCdcCom_SerialStateUpdate(stc_cdc_uart_state_t* pstcState); +void UsbDeviceCdcCom_SerialStateGet(stc_cdc_uart_state_t* pstcState); + +void UsbDeviceCdcCom_Init(stc_usbn_t* pstcUsb); +boolean_t UsbDeviceCdcCom_DataSent(void); +boolean_t UsbDeviceCdcCom_IsConnected(void); +uint8_t UsbDeviceCdcCom_SendByte(char_t c); +uint8_t UsbDeviceCdcCom_SendString(char_t *pcBuffer); +uint8_t UsbDeviceCdcCom_SendBuffer(uint8_t *pu8Buffer, uint32_t u32Size); +void UsbDeviceCdcCom_SetSeparator(const char_t cNewSeperator); +void UsbDeviceCdcCom_SetEchomode(boolean_t bEchoOnOff); +void UsbDeviceCdcCom_SetEchoAtSeperatorOnly(boolean_t bEchoAtSeperatorOnlyOnOff); +uint32_t UsbDeviceCdcCom_ReceivedLength(void); +uint32_t UsbDeviceCdcCom_ReceiveBuffer(uint8_t *pu8Buffer, uint32_t numBytes); /* [andreika]: add numBytes */ +uint8_t UsbDeviceCdcCom_ReceiveByte(void); +uint8_t UsbDeviceCdcCom_ReceiveLastByte(void); +uint8_t UsbDeviceCdcCom_SendHex(uint32_t n, uint8_t digits); +uint8_t UsbDeviceCdcCom_SendDec(uint32_t x); +void UsbDeviceCdcCom_SendBinAsci4(uint16_t a, uint8_t base, char_t fill); +void UsbDeviceCdcCom_SendBinAsci8(uint16_t a, uint8_t base, char_t fill); +void UsbDeviceCdcCom_SendBin2DotDec99(uint8_t a); +uint32_t UsbDeviceCdcCom_ReceiveHex(uint8_t digits); +void UsbDeviceCdcCom_SetDtrChangedCallback(cdc_dtr_changed_t pstnCallback); +void UsbDeviceCdcCom_SetRtsChangedCallback(cdc_rts_changed_t pstnCallback); +void UsbDeviceCdcCom_SetReceivedCallback(cdc_data_received_t pstnCallback); +void UsbDeviceCdcCom_SetSentCallback(cdc_data_sent_t pstnCallback); +void UsbDeviceCdcCom_SetCallbackLineCodingChange(usbdevicecdccom_linecodingchange_func_ptr_t pfnLineCodingChangeCallback); +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceCdcComGroup +#else + #define UsbDeviceCdcCom_Init(x) ; +#endif + + +#endif /* __USBCLASS_H__*/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.c new file mode 100644 index 0000000000..8607e55d5e --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.c @@ -0,0 +1,393 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceCmsisDap.c + ** + ** CMSIS-DAP HID Communication Backend + ** for protocol layer visit http://www.arm.com + ** + ** History: + ** - 2014-02-28 1.0 MSc First public version + *****************************************************************************/ +#define __USBDEVICECMSISDAP_C__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "UsbDeviceCmsisDap.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICECMSISDAP_ENABLED == ON)) + +#include "DAP_config.h" +#include "DAP.h" + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); +static void ConfCallback(stc_usbn_t* pstcUsb); +extern uint32_t DAP_ProcessVendorCommand(uint8_t *request, uint8_t *response); + +/******************************************************************************/ +/* Local variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +#if (64 != DAP_PACKET_SIZE) +#error "USB HID Output Report Size must match DAP Packet Size" +#endif +#if (64 != DAP_PACKET_SIZE) +#error "USB HID Input Report Size must match DAP Packet Size" +#endif + +static volatile uint8_t USB_RequestFlag; // Request Buffer Usage Flag +static volatile uint32_t USB_RequestIn; // Request Buffer In Index +static volatile uint32_t USB_RequestOut; // Request Buffer Out Index + +static volatile uint8_t USB_ResponseIdle; // Response Buffer Idle Flag +static volatile uint8_t USB_ResponseFlag; // Response Buffer Usage Flag +static volatile uint32_t USB_ResponseIn; // Response Buffer In Index +static volatile uint32_t USB_ResponseOut; // Response Buffer Out Index + + +//static const uint8_t u8MaxSupportedEndpoints = 2; +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; +static stc_usbn_endpoint_buffer_t stcEndpointBufferOUT; + +static uint8_t USB_Request [DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Request Buffer +static uint8_t USB_Response[DAP_PACKET_COUNT][DAP_PACKET_SIZE]; // Response Buffer +uint8_t pu8BufferOUT[64]; +uint8_t pu8BufferIN[64]; + +static stc_usbn_endpoint_data_t* pstcEndpointIN = NULL; +static stc_usbn_endpoint_data_t* pstcEndpointOUT = NULL; + +static boolean_t bDataReceived = FALSE; +static boolean_t bDataSent = TRUE; +static boolean_t bReady = FALSE; +static stc_usbn_t* pstcUsbHandle = NULL; + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Procedures / Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Configuration change callback, used to see if configuration is set + ** or cleared + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + DAP_Setup(); // DAP Setup + bDataReceived = FALSE; + bDataSent = TRUE; + USB_RequestFlag = 0; + USB_RequestIn = 0; + USB_RequestOut = 0; + USB_ResponseIdle = 1; + USB_ResponseFlag = 0; + USB_ResponseIn = 0; + USB_ResponseOut = 0; + bReady = TRUE; + LED_CONNECTED_OUT(1); // Turn on Debugger Connected LED + Delayms(50); // Wait for 500ms + LED_RUNNING_OUT(1); // Turn on Target Running LED + Delayms(50); // Wait for 500ms + LED_CONNECTED_OUT(0); // Turn off Debugger Connected LED + Delayms(50); // Wait for 500ms + LED_RUNNING_OUT(0); // Turn off Target Running LED + } else + { + bReady = FALSE; + } +} + +/** + ****************************************************************************** + ** \brief Receive or transmitted data callback + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \return none + ** + ******************************************************************************/ +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + volatile uint8_t i; + volatile uint8_t u8EndpointIndex = 0xFF; + + if ((pstcEndpoint->u8EndpointAddress) & 0x80) + { + bDataSent = TRUE; + } + else + { + + if (pu8BufferOUT[0] == ID_DAP_TransferAbort) { + DAP_TransferAbort = 1; + return; + } + if (USB_RequestFlag && (USB_RequestIn == USB_RequestOut)) { + return; // Discard packet when buffer is full + } + // Store data into request packet buffer + memcpy(USB_Request[USB_RequestIn], pstcEndpoint->pstcEndpointBuffer->pu8Buffer, 64); + UsbDevice_ReceiveData(pstcUsb, pstcEndpoint, pstcEndpoint->pstcEndpointBuffer->pu8Buffer, 64, UsbIRQ); + USB_RequestIn++; + if (USB_RequestIn == DAP_PACKET_COUNT) { + USB_RequestIn = 0; + } + if (USB_RequestIn == USB_RequestOut) + { + USB_RequestFlag = 1; + } + bDataReceived = TRUE; + } +} + +/** + ****************************************************************************** + ** \brief Initialisation callback + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +void UsbDeviceCmsisDap_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + //uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + pstcEndpointIN = NULL; + pstcEndpointOUT = NULL; + + USB_RequestFlag = 0; + USB_RequestIn = 0; + USB_RequestOut = 0; + USB_ResponseIdle = 1; + USB_ResponseFlag = 0; + USB_ResponseIn = 0; + USB_ResponseOut = 0; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x03; // HID Class + stcUsbClassConfig.u8InterfaceSubClass = 0x00; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x00; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = NULL; // No setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + stcEndpointConfig.pfnRxTxCallback = RxTxCallback; + + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferOUT; + pstcEndpointOUT = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8BufferOUT, 64, UsbIRQ); + } + else + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + if ((pstcEndpointIN != NULL) && (pstcEndpointOUT != NULL)) + { + return; + } + } + } + +} + +/** + ****************************************************************************** + ** \brief Send data + ** + ** \param pu8Buffer Pointer to data buffer + ** + ** \param enMode Transfer mode (UsbPOLL, UsbDMA, UsbIRQ) + ** + ** \return TRUE on success + ** + ******************************************************************************/ +boolean_t UsbDeviceCmsisDap_Send(uint8_t* pu8Buffer, en_usbsend_mode_t enMode) +{ + if ((bReady == FALSE) || (bDataSent == FALSE)) + { + return FALSE; + } + bDataSent = FALSE; + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, 64, enMode); + if ((USB_ResponseOut != USB_ResponseIn) || USB_ResponseFlag) { + + USB_ResponseOut++; + if (USB_ResponseOut == DAP_PACKET_COUNT) { + USB_ResponseOut = 0; + } + if (USB_ResponseOut == USB_ResponseIn) { + USB_ResponseFlag = 0; + } + return TRUE; + } else { + USB_ResponseIdle = 1; + } + + if (enMode == UsbPOLL) + { + bDataSent = TRUE; + } + return TRUE; +} + +void UsbDeviceCmsisDap_Tick(void) +{ + uint32_t n; + + // Process pending requests + if ((USB_RequestOut != USB_RequestIn) || USB_RequestFlag) { + + // Process DAP Command and prepare response + DAP_ProcessCommand(USB_Request[USB_RequestOut], USB_Response[USB_ResponseIn]); + DAP_ProcessVendorCommand(USB_Request[USB_RequestOut], USB_Response[USB_ResponseIn]); + // Update request index and flag + n = USB_RequestOut + 1; + if (n == DAP_PACKET_COUNT) { + n = 0; + } + USB_RequestOut = n; + if (USB_RequestOut == USB_RequestIn) { + USB_RequestFlag = 0; + } + + if (USB_ResponseIdle) { + // Request that data is send back to host + USB_ResponseIdle = 0; + #if USB_USES_DMA == ON + UsbDeviceCmsisDap_Send(USB_Response[USB_ResponseOut],UsbDMA); + #else + UsbDeviceCmsisDap_Send(USB_Response[USB_ResponseOut],UsbIRQ); + #endif + } else { + // Update response index and flag + n = USB_ResponseIn + 1; + if (n == DAP_PACKET_COUNT) { + n = 0; + } + USB_ResponseIn = n; + if (USB_ResponseIn == USB_ResponseOut) { + USB_ResponseFlag = 1; + } + } + } +} + +/** + ****************************************************************************** + ** \brief Check if data transfer is still in process + ** + ** \return TRUE on sending + ** + ******************************************************************************/ +boolean_t UsbDeviceCmsisDap_IsSending() +{ + return !bDataSent; +} + +/** + ****************************************************************************** + ** \brief Check if data transfer was transmitted + ** + ** \return TRUE if data was sent + ** + ******************************************************************************/ +boolean_t UsbDeviceCmsisDap_DataSent() +{ + return bDataSent; +} + +/** + ****************************************************************************** + ** \brief Send data + ** + ** \param pu8OutBuffer Pointer to data buffer where to write in data + ** + ** \return number of bytes read + ** + ******************************************************************************/ +uint32_t UsbDeviceCmsisDap_GetReceivedData(uint8_t* pu8OutBuffer) +{ + if (bDataReceived == TRUE) + { + bDataReceived = FALSE; + memcpy(pu8OutBuffer,pstcEndpointOUT->pstcEndpointBuffer->pu8Buffer,64); + UsbDevice_ReceiveData(pstcUsbHandle, pstcEndpointOUT, pstcEndpointOUT->pstcEndpointBuffer->pu8Buffer, pstcEndpointOUT->pstcEndpointBuffer->u32BufferSize, UsbIRQ); + return 64; + } + return 0; +} + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.h new file mode 100644 index 0000000000..7017c844c8 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceCmsisDap.h @@ -0,0 +1,85 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceCmsisDap.h + ** + ** CMSIS-DAP HID Communication Backend + ** for protocol layer visit http://www.arm.com + ** + ** History: + ** - 2014-02-28 1.0 MSc First public version + *****************************************************************************/ + +#ifndef __USBDEVICECMSISDAP_H__ +#define __USBDEVICECMSISDAP_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "usb.h" +#include "usbdevice.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICECMSISDAP_ENABLED == ON)) + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('static') */ +/******************************************************************************/ + +void UsbDeviceCmsisDap_Init(stc_usbn_t* pstcUsb); +uint32_t UsbDeviceCmsisDap_GetReceivedData(uint8_t* pu8OutBuffer); +boolean_t UsbDeviceCmsisDap_Send(uint8_t* pu8Buffer, en_usbsend_mode_t enMode); +boolean_t UsbDeviceCmsisDap_IsSending(void); +boolean_t UsbDeviceCmsisDap_DataSent(void); +void UsbDeviceCmsisDap_Tick(void); + +#endif +#endif /*__USBDEVICECMSISDAP_H__ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.c new file mode 100644 index 0000000000..1f9db9e8c6 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.c @@ -0,0 +1,268 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/*****************************************************************************/ +/** \file UsbDeviceHidCom.c + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidComGroup USB Device HID Com Module description @endlink + ** + ** - See README.TXT for project description + ** - USB Human Interface Device Communication + ** + ** History: + ** - 2012-07-20 1.0 MSc First version for FM3 USB library + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ +#define __USBDEVICEHIDCOM_C__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "UsbDeviceHidCom.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDCOM_ENABLED == ON)) +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); +static void ConfCallback(stc_usbn_t* pstcUsb); + +/******************************************************************************/ +/* Local variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +static const uint8_t u8MaxSupportedEndpoints = 2; +static stc_usbn_endpoint_data_t* ppstcUsedEndpoints[2]; +static stc_usbn_endpoint_buffer_t pstcEndpointBuffers[2]; +static uint8_t ppu8Buffers[2][64]; +static const uint32_t pu32BufferSizes[2] = {64,64}; +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static stc_usbn_endpoint_data_t* pstcEndpointOUT; +static boolean_t bDataReceived = FALSE; +static boolean_t bDataSent = TRUE; +static boolean_t bReady = FALSE; +static stc_usbn_t* pstcUsbHandle = NULL; + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Procedures / Functions */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** \brief Configuration change callback, used to see if configuration is set + ** or cleared + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + bReady = TRUE; + } else + { + bReady = FALSE; + } +} + +/** + ****************************************************************************** + ** \brief Receive or transmitted data callback + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \param pstcEndpoint Pointer to endpoint instance + ** + ** \return none + ** + ******************************************************************************/ +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + volatile uint8_t i; + volatile uint8_t u8EndpointIndex = 0xFF; + + if ((pstcEndpoint->u8EndpointAddress) & 0x80) + { + bDataSent = TRUE; + } + else + { + bDataReceived = TRUE; + } +} + +/** + ****************************************************************************** + ** \brief Initialisation callback + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +void UsbDeviceHidCom_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x03; // HID Class + stcUsbClassConfig.u8InterfaceSubClass = 0x00; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x00; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = NULL; // No setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + stcEndpointConfig.pfnRxTxCallback = RxTxCallback; + stcEndpointConfig.pstcEndpointBuffer = &(pstcEndpointBuffers[u8NumEndpoints]); + ppstcUsedEndpoints[u8NumEndpoints] = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + pstcEndpointOUT = ppstcUsedEndpoints[u8NumEndpoints]; + UsbDevice_ReceiveData(pstcUsb, ppstcUsedEndpoints[u8NumEndpoints], ppu8Buffers[u8NumEndpoints], pu32BufferSizes[u8NumEndpoints], UsbIRQ); + } + else + { + pstcEndpointIN = ppstcUsedEndpoints[u8NumEndpoints]; + } + u8NumEndpoints++; + if (u8NumEndpoints > u8MaxSupportedEndpoints) + { + return; + } + } + } + +} + +/** + ****************************************************************************** + ** \brief Send data + ** + ** \param pu8Buffer Pointer to data buffer + ** + ** \param enMode Transfer mode (UsbPOLL, UsbDMA, UsbIRQ) + ** + ** \return TRUE on success + ** + ******************************************************************************/ +boolean_t UsbDeviceHidCom_Send(uint8_t* pu8Buffer, en_usbsend_mode_t enMode) +{ + if ((bReady == FALSE) || (bDataSent == FALSE)) + { + return FALSE; + } + bDataSent = FALSE; + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, 64, enMode); + if (enMode == UsbPOLL) + { + bDataSent = TRUE; + } + return TRUE; +} + +/** + ****************************************************************************** + ** \brief Check if data transfer is still in process + ** + ** \return TRUE on sending + ** + ******************************************************************************/ +boolean_t UsbDeviceHidCom_IsSending() +{ + return !bDataSent; +} + +/** + ****************************************************************************** + ** \brief Check if data transfer was transmitted + ** + ** \return TRUE if data was sent + ** + ******************************************************************************/ +boolean_t UsbDeviceHidCom_DataSent() +{ + return bDataSent; +} + +/** + ****************************************************************************** + ** \brief Send data + ** + ** \param pu8OutBuffer Pointer to data buffer where to write in data + ** + ** \return number of bytes read + ** + ******************************************************************************/ +uint32_t UsbDeviceHidCom_GetReceivedData(uint8_t* pu8OutBuffer) +{ + if (bDataReceived == TRUE) + { + bDataReceived = FALSE; + memcpy(pu8OutBuffer,pstcEndpointOUT->pstcEndpointBuffer->pu8Buffer,64); + UsbDevice_ReceiveData(pstcUsbHandle, pstcEndpointOUT, pstcEndpointOUT->pstcEndpointBuffer->pu8Buffer, pstcEndpointOUT->pstcEndpointBuffer->u32BufferSize, UsbIRQ); + return 64; + } + return 0; +} +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.h new file mode 100644 index 0000000000..6d05ccd05e --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidCom.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/*****************************************************************************/ +/** \file UsbDeviceHidCom.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** + ** A detailed description is available at + ** @link UsbDeviceHidComGroup USB Device HID Com Module description @endlink + ** + ** - See README.TXT for project description + ** - USB Human Interface Device Communication + ** + ** History: + ** - 2012-07-20 1.0 MSc First version for FM3 USB library + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +#ifndef __USBDEVICEHIDCOM_H__ +#define __USBDEVICEHIDCOM_H__ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "usb.h" + +#ifndef USBDEVICEHIDCOM_ENABLED + #define USBDEVICEHIDCOM_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDCOM_ENABLED == ON)) + +#include "usbdevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceHidComGroup USB Device Middleware: HID Com - Data Communicaton + ** + ** Provided functions of USB Device HID Communication module: + ** + ** - UsbDeviceHidCom_Init() + ** - UsbDeviceHidCom_GetReceivedData() + ** - UsbDeviceHidCom_Send() + ** - UsbDeviceHidCom_IsSending() + ** - UsbDeviceHidCom_DataSent() + ** + ** Used to send or receive 64 byte block data + ** + ******************************************************************************/ +//@{ + +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local type definitions ('typedef') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global function prototypes ('static') */ +/******************************************************************************/ + +void UsbDeviceHidCom_Init(stc_usbn_t* pstcUsb); +uint32_t UsbDeviceHidCom_GetReceivedData(uint8_t* pu8OutBuffer); +boolean_t UsbDeviceHidCom_Send(uint8_t* pu8Buffer, en_usbsend_mode_t enMode); +boolean_t UsbDeviceHidCom_IsSending(void); +boolean_t UsbDeviceHidCom_DataSent(void); +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceHidComGroup +#else + #define UsbDeviceHidCom_Init(x) ; +#endif + +#endif /*__USBDEVICEHIDCOM_H__ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.c new file mode 100644 index 0000000000..75913aa945 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.c @@ -0,0 +1,389 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceHidJoystick.c + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidJoystickGroup USB Device Joystick Module description @endlink + ** + ** History: + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "UsbDeviceHidJoystick.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDJOYSTICK_ENABLED == ON)) + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +static uint8_t DataSentFlags = 0; //Status for sent data +static uint8_t pu8JoystickData[4] = {0,0,0,0}; +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; +static stc_usbn_t* pstcUsbHandle = NULL; +static boolean_t bReady = FALSE; +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Configuration change callback, used to see if configuration is set + ** or cleared + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + bReady = TRUE; + } else + { + bReady = FALSE; + } +} + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +void UsbDeviceHidJoystick_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x03; // HID Class + stcUsbClassConfig.u8InterfaceSubClass = 0x00; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x00; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = NULL; // setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + /* NOT USED */ + } + else + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + u8NumEndpoints++; + } + } + +} + +/** + ****************************************************************************** + ** Is called from main application to send data via endpoint + ** + ** \param pu8Buffer Buffer to send + ** \param u32DataSize Buffersize + ** \param enMode polled sending, interrupt sending or DMA + ** + ** \return 1: if succesful, 0: if usb was not ready + *****************************************************************************/ +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + if (UsbDevice_GetStatus(pstcUsbHandle) == UsbConfigured) + { + DataSentFlags &= ~(1<<1); + + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, u32DataSize, enMode); + if (enMode == UsbPOLL) + { + DataSentFlags |= (1<<1); + } + return TRUE; + } + return FALSE; +} + + +/** + ****************************************************************************** + ** Used to change the throttle value + ** + ** \param iThrottle signed byte value + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeThrottle(int8_t iThrottle) +{ + pu8JoystickData[0] = (uint8_t)iThrottle; + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the X value + ** + ** \param iX signed byte value + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeX(int8_t iX) +{ + pu8JoystickData[1] = (uint8_t)iX; + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the Y value + ** + ** \param iY signed byte value + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeY(int8_t iY) +{ + pu8JoystickData[2] = (uint8_t)iY; + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the X and Y value + ** + ** \param iX signed byte value + ** + ** \param iY signed byte value + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeXY(int8_t iX, int8_t iY) +{ + pu8JoystickData[1] = (uint8_t)iX; + pu8JoystickData[2] = (uint8_t)iY; + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the button 1 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton1(boolean_t bButtonValue) +{ + if (bButtonValue) + { + pu8JoystickData[3] |= (1 << 4); + } + else + { + pu8JoystickData[3] &= ~(1 << 4); + } + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the button 2 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton2(boolean_t bButtonValue) +{ + if (bButtonValue) + { + pu8JoystickData[3] |= (1 << 5); + } + else + { + pu8JoystickData[3] &= ~(1 << 5); + } + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the button 3 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton3(boolean_t bButtonValue) +{ + if (bButtonValue) + { + pu8JoystickData[3] |= (1 << 6); + } + else + { + pu8JoystickData[3] &= ~(1 << 6); + } + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the button 4 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton4(boolean_t bButtonValue) +{ + if (bButtonValue) + { + pu8JoystickData[3] |= (1 << 6); + } + else + { + pu8JoystickData[3] &= ~(1 << 6); + } + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the hat direction UP + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatUp(void) +{ + pu8JoystickData[3] = (pu8JoystickData[3] & 0xF0) | 0; + + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the hat direction RIGHT + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatRight(void) +{ + pu8JoystickData[3] = (pu8JoystickData[3] & 0xF0) | 1; + + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the hat direction DOWN + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatDown(void) +{ + pu8JoystickData[3] = (pu8JoystickData[3] & 0xF0) | 2; + + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the hat direction LEFT + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatLeft(void) +{ + pu8JoystickData[3] = (pu8JoystickData[3] & 0xF0) | 3; + + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Used to change the hat direction no direction + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatNoDirection(void) +{ + pu8JoystickData[3] = (pu8JoystickData[3] & 0xF0) | 7; + + SendData((uint8_t*)pu8JoystickData,4,UsbPOLL); +} + +/** + ****************************************************************************** + ** Return connected state + ** + ** \return TRUE if ready + ** + *****************************************************************************/ +boolean_t UsbDeviceHidJoystick_IsConnected(void) +{ + return bReady; +} +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.h new file mode 100644 index 0000000000..51c77b5ef0 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidJoystick.h @@ -0,0 +1,258 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceHidJoystick.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidJoystickGroup USB Device Joystick Module description @endlink + ** + ** History: + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +#ifndef __USBDEVICEHIDJOYSTICK_H__ +#define __USBDEVICEHIDJOYSTICK_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "usb.h" + +#ifndef USBDEVICEHIDJOYSTICK_ENABLED + #define USBDEVICEHIDJOYSTICK_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDJOYSTICK_ENABLED == ON)) + +#include "usbdevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceHidJoystickGroup USB Device Middleware: HID Joystick + ** + ** Provided functions of USB Device Joystick module: + ** + ** - UsbDeviceHidJoystick_Init() + ** - UsbDeviceHidJoystick_ChangeThrottle() + ** - UsbDeviceHidJoystick_ChangeX() + ** - UsbDeviceHidJoystick_ChangeY() + ** - UsbDeviceHidJoystick_ChangeXY() + ** - UsbDeviceHidJoystick_ChangeButton1() + ** - UsbDeviceHidJoystick_ChangeButton2() + ** - UsbDeviceHidJoystick_ChangeButton3() + ** - UsbDeviceHidJoystick_ChangeButton4() + ** - UsbDeviceHidJoystick_ChangeHatUp() + ** - UsbDeviceHidJoystick_ChangeHatRight() + ** - UsbDeviceHidJoystick_ChangeHatDown() + ** - UsbDeviceHidJoystick_ChangeHatLeft() + ** - UsbDeviceHidJoystick_ChangeHatNoDirection() + ** - UsbDeviceHidJoystick_IsConnected() + ** + ** Used to enumerate a joystick device + ** + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + + + + + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +void UsbDeviceHidJoystick_Init(stc_usbn_t* pstcUsb); + + + +/** + ****************************************************************************** + ** Used to change the throttle value + ** + ** \param iThrottle signed byte value + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeThrottle(int8_t iThrottle); + + +/** + ****************************************************************************** + ** Used to change the X value + ** + ** \param iX signed byte value + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeX(int8_t iX); + + +/** + ****************************************************************************** + ** Used to change the Y value + ** + ** \param iY signed byte value + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeY(int8_t iY); + + +/** + ****************************************************************************** + ** Used to change the X and Y value + ** + ** \param iX signed byte value + ** + ** \param iY signed byte value + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeXY(int8_t iX, int8_t iY); + + +/** + ****************************************************************************** + ** Used to change the button 1 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton1(boolean_t bButtonValue); + + +/** + ****************************************************************************** + ** Used to change the button 2 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton2(boolean_t bButtonValue); + + +/** + ****************************************************************************** + ** Used to change the button 3 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton3(boolean_t bButtonValue); + + +/** + ****************************************************************************** + ** Used to change the button 4 value + ** + ** \param bButtonValue TRUE = pressed, FALSE = released + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeButton4(boolean_t bButtonValue); + + +/** + ****************************************************************************** + ** Used to change the hat direction UP + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatUp(void); + + +/** + ****************************************************************************** + ** Used to change the hat direction RIGHT + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatRight(void); + + +/** + ****************************************************************************** + ** Used to change the hat direction DOWN + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatDown(void); + + +/** + ****************************************************************************** + ** Used to change the hat direction LEFT + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatLeft(void); + + +/** + ****************************************************************************** + ** Used to change the hat direction no direction + ** + *****************************************************************************/ +void UsbDeviceHidJoystick_ChangeHatNoDirection(void); + +/** + ****************************************************************************** + ** Return connected state + ** + ** \return TRUE if ready + ** + *****************************************************************************/ +boolean_t UsbDeviceHidJoystick_IsConnected(void); + +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceHidJoystickGroup +#else + #define UsbDeviceHidJoystick_Init(x) ; +#endif +#endif /* __UsbDeviceHidJoystickCLASS_H__*/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.c new file mode 100644 index 0000000000..88d2e61a3c --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.c @@ -0,0 +1,537 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceHidKeyboard.c + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidKeyboardGroup USB Device Keyboard Module description @endlink + ** + ** History: + ** - 2013-05-08 1.0 MSc First Version + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "UsbDeviceHidKeyboard.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDKEYBOARD_ENABLED == ON)) +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ +const uint8_t u8AsciiToKeyCode[] = { +0, // 0 = +0, // 1 = +0, // 2 = +0, // 3 = +0, // 4 = +0, // 5 = +0, // 6 = +0, // 7 = +0, // 8 = +0, // 9 = +0x28, // 10 = \r +0, // 11 = +0, // 12 = +0x58, // 13 = \n +0, // 14 = +0, // 15 = +0, // 16 = +0, // 17 = +0, // 18 = +0, // 19 = +0, // 20 = +0, // 21 = +0, // 22 = +0, // 23 = +0, // 24 = +0, // 25 = +0, // 26 = +29, // 27 = ESC +0, // 28 = +0, // 29 = +0, // 30 = +0, // 31 = +44, // 32 = SPACE +0, // 33 = ! +0, // 34 = " +0, // 35 = # +0, // 36 = $ +0, // 37 = % +0, // 38 = & +0, // 39 = ' +0, // 40 = ( +0, // 41 = ) +0, // 42 = * +0, // 43 = + +0, // 44 = , +0, // 45 = - +0x37, // 46 = . +0, // 47 = / +39, // 48 = 0 +30, // 49 = 1 +31, // 50 = 2 +32, // 51 = 3 +33, // 52 = 4 +34, // 53 = 5 +35, // 54 = 6 +36, // 55 = 7 +37, // 56 = 8 +38, // 57 = 9 +0, // 58 = : +0, // 59 = ; +0, // 60 = < +0, // 61 = = +0, // 62 = > +0, // 63 = ? +0, // 64 = @ +0, // 65 = A +0, // 66 = B +0, // 67 = C +0, // 68 = D +0, // 69 = E +0, // 70 = F +0, // 71 = G +0, // 72 = H +0, // 73 = I +0, // 74 = J +0, // 75 = K +0, // 76 = L +0, // 77 = M +0, // 78 = N +0, // 79 = O +0, // 80 = P +0, // 81 = Q +0, // 82 = R +0, // 83 = S +0, // 84 = T +0, // 85 = U +0, // 86 = V +0, // 87 = W +0, // 88 = X +0, // 89 = Y +0, // 90 = Z +0, // 91 = [ +0, // 92 = +0, // 93 = ] +0, // 94 = ^ +0, // 95 = _ +0, // 96 = ` +4, // 97 = a +5, // 98 = b +6, // 99 = c +7, // 100 = d +8, // 101 = e +9, // 102 = f +10, // 103 = g +11, // 104 = h +12, // 105 = i +13, // 106 = j +14, // 107 = k +15, // 108 = l +16, // 109 = m +17, // 110 = n +18, // 111 = o +19, // 112 = p +20, // 113 = q +21, // 114 = r +22, // 115 = s +23, // 116 = t +24, // 117 = u +25, // 118 = v +26, // 119 = w +27, // 120 = x +28, // 121 = y +29, // 122 = z +0, // 123 = { +0, // 124 = | +0, // 125 = } +0, // 126 = ~ +0, // 127 =  +0, // 128 = ? +0, // 129 = ? +0, // 130 = ? +0, // 131 = ? +0, // 132 = ? +0, // 133 = ? +0, // 134 = ? +0, // 135 = ? +0, // 136 = ? +0, // 137 = ? +0, // 138 = ? +0, // 139 = ? +0, // 140 = ? +0, // 141 = ? +0, // 142 = ? +0, // 143 = ? +0, // 144 = ? +0, // 145 = ? +0, // 146 = ? +0, // 147 = ? +0, // 148 = ? +0, // 149 = ? +0, // 150 = ? +0, // 151 = ? +0, // 152 = ? +0, // 153 = ? +0, // 154 = ? +0, // 155 = ? +0, // 156 = ? +0, // 157 = ? +0, // 158 = ? +0, // 159 = ? +0, // 160 = ? +0, // 161 = ? +0, // 162 = ? +0, // 163 = ? +0, // 164 = ? +0, // 165 = ? +0, // 166 = ? +0, // 167 = ? +0, // 168 = ? +0, // 169 = ? +0, // 170 = ? +0, // 171 = ? +0, // 172 = ? +0, // 173 = ? +0, // 174 = ? +0, // 175 = ? +0, // 176 = ? +0, // 177 = ? +0, // 178 = ? +0, // 179 = ? +0, // 180 = ? +0, // 181 = ? +0, // 182 = ? +0, // 183 = ? +0, // 184 = ? +0, // 185 = ? +0, // 186 = ? +0, // 187 = ? +0, // 188 = ? +0, // 189 = ? +0, // 190 = ? +0, // 191 = ? +0, // 192 = ? +0, // 193 = ? +0, // 194 = ? +0, // 195 = ? +0, // 196 = ? +0, // 197 = ? +0, // 198 = ? +0, // 199 = ? +0, // 200 = ? +0, // 201 = ? +0, // 202 = ? +0, // 203 = ? +0, // 204 = ? +0, // 205 = ? +0, // 206 = ? +0, // 207 = ? +0, // 208 = ? +0, // 209 = ? +0, // 210 = ? +0, // 211 = ? +0, // 212 = ? +0, // 213 = ? +0, // 214 = ? +0, // 215 = ? +0, // 216 = ? +0, // 217 = ? +0, // 218 = ? +0, // 219 = ? +0, // 220 = ? +0, // 221 = ? +0, // 222 = ? +0, // 223 = ? +0, // 224 = ? +0, // 225 = ? +0, // 226 = ? +0, // 227 = ? +0, // 228 = ? +0, // 229 = ? +0, // 230 = ? +0, // 231 = ? +0, // 232 = ? +0, // 233 = ? +0, // 234 = ? +0, // 235 = ? +0, // 236 = ? +0, // 237 = ? +0, // 238 = ? +0, // 239 = ? +0, // 240 = ? +0, // 241 = ? +0, // 242 = ? +0, // 243 = ? +0, // 244 = ? +0, // 245 = ? +0, // 246 = ? +0, // 247 = ? +0, // 248 = ? +0, // 249 = ? +0, // 250 = ? +0, // 251 = ? +0, // 252 = ? +0, // 253 = ? +0, // 254 = ? +0, // 255 = ? +}; +static uint8_t DataSentFlags = 0; //Status for sent data +static uint8_t pu8KeyboardData[8] = {0,0,0,0,0,0,0,0}; +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; +static stc_usbn_t* pstcUsbHandle = NULL; +static boolean_t bReady = FALSE; +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Configuration change callback, used to see if configuration is set + ** or cleared + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + bReady = TRUE; + } else + { + bReady = FALSE; + } +} + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +void UsbDeviceHidKeyboard_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x03; // HID Class + stcUsbClassConfig.u8InterfaceSubClass = 0x01; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x01; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = NULL; // setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + /* NOT USED */ + } + else + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + u8NumEndpoints++; + } + } + +} + +/** + ****************************************************************************** + ** Is called from main application to send data via endpoint + ** + ** \param pu8Buffer Buffer to send + ** \param u32DataSize Buffersize + ** \param enMode polled sending, interrupt sending or DMA + ** + ** \return 1: if succesful, 0: if usb was not ready + *****************************************************************************/ +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + if (UsbDevice_GetStatus(pstcUsbHandle) == UsbConfigured) + { + DataSentFlags &= ~(1<<1); + + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, u32DataSize, enMode); + if (enMode == UsbPOLL) + { + DataSentFlags |= (1<<1); + } + return TRUE; + } + return FALSE; +} + + +/** + ****************************************************************************** + ** Set modifier keys + ** + ** \param u8ModifierKey Bitmask of modifier keys: + ** MODIFIERKEY_LEFT_CTRL + ** MODIFIERKEY_LEFT_SHIFT + ** MODIFIERKEY_LEFT_ALT + ** MODIFIERKEY_LEFT_GUI + ** MODIFIERKEY_RIGHT_CTRL + ** MODIFIERKEY_RIGHT_SHIFT + ** MODIFIERKEY_RIGHT_ALT + ** MODIFIERKEY_RIGHT_GUI + ** + ** \return none + *****************************************************************************/ +void UsbDeviceHidKeyboard_SetModifierKey(uint8_t u8ModifierKey) +{ + pu8KeyboardData[0] |= u8ModifierKey; + SendData((uint8_t*)pu8KeyboardData,8,UsbPOLL); +} +/** + ****************************************************************************** + ** Clear modifier keys + ** + ** \param u8ModifierKey Bitmask of modifier keys: + ** MODIFIERKEY_LEFT_CTRL + ** MODIFIERKEY_LEFT_SHIFT + ** MODIFIERKEY_LEFT_ALT + ** MODIFIERKEY_LEFT_GUI + ** MODIFIERKEY_RIGHT_CTRL + ** MODIFIERKEY_RIGHT_SHIFT + ** MODIFIERKEY_RIGHT_ALT + ** MODIFIERKEY_RIGHT_GUI + ** + ** \return none + *****************************************************************************/ +void UsbDeviceHidKeyboard_ClearModifierKey(uint8_t u8ModifierKey) +{ + pu8KeyboardData[0] &= ~u8ModifierKey; + SendData((uint8_t*)pu8KeyboardData,8,UsbPOLL); +} + +/** + ****************************************************************************** + ** Press key (Down - Up) + ** + ** \param u8Index 0..5 (parallel pressed keys) + ** \param u8KeyCode Keycode + ** + ** \return none + *****************************************************************************/ +void UsbDeviceHidKeyboard_KeyPress(uint8_t u8Index, uint8_t u8KeyCode) +{ + pu8KeyboardData[u8Index + 2] = u8KeyCode; + SendData((uint8_t*)pu8KeyboardData,8,UsbPOLL); + pu8KeyboardData[u8Index + 2] = 0; + SendData((uint8_t*)pu8KeyboardData,8,UsbPOLL); +} + +/** + ****************************************************************************** + ** Press key (Down) + ** + ** \param u8Index 0..5 (parallel pressed keys) + ** \param u8KeyCode Keycode + ** + ** \return none + *****************************************************************************/ +void UsbDeviceHidKeyboard_KeyDown(uint8_t u8Index, uint8_t u8KeyCode) +{ + pu8KeyboardData[u8Index + 2] = u8KeyCode; + SendData((uint8_t*)pu8KeyboardData,8,UsbPOLL); +} + +/** + ****************************************************************************** + ** Press key (Up) + ** + ** \param u8Index 0..5 (parallel pressed keys) + ** \param u8KeyCode Keycode + ** + ** \return none + *****************************************************************************/ +void UsbDeviceHidKeyboard_KeyUp(uint8_t u8Index, uint8_t u8KeyCode) +{ + pu8KeyboardData[u8Index + 2] = u8KeyCode; + SendData((uint8_t*)pu8KeyboardData,8,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Return connected state + ** + ** \return TRUE if ready + ** + *****************************************************************************/ +boolean_t UsbDeviceHidKeyboard_IsConnected(void) +{ + return bReady; +} +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.h new file mode 100644 index 0000000000..57c852bf57 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidKeyboard.h @@ -0,0 +1,168 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceHidKeyboard.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidKeyboardGroup USB Device Keyboard Module description @endlink + ** + ** History: + ** - 2013-05-08 1.0 MSc First Version + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +#ifndef __USBDEVICEHIDKEYBOARD_H__ +#define __USBDEVICEHIDKEYBOARD_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "usb.h" + +#ifndef USBDEVICEHIDKEYBOARD_ENABLED + #define USBDEVICEHIDKEYBOARD_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDKEYBOARD_ENABLED == ON)) + +#include "usbdevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceHidKeyboardGroup USB Device Middleware: HID Keyboard + ** + ** Provided functions of USB Device Keyboard module: + ** + ** - UsbDeviceHidKeyboard_Init() + ** - UsbDeviceHidKeyboard_SetModifierKey() + ** - UsbDeviceHidKeyboard_ClearModifierKey() + ** - UsbDeviceHidKeyboard_KeyPress() + ** - UsbDeviceHidKeyboard_KeyDown() + ** - UsbDeviceHidKeyboard_KeyUp() + ** - UsbDeviceHidKeyboard_IsConnected() + ** + ** Used to enumerate a keyboard device + ** + ******************************************************************************/ +//@{ + +extern const uint8_t u8AsciiToKeyCode[]; + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +#ifndef MODIFIERKEY_LEFT_CTRL +#define MODIFIERKEY_LEFT_CTRL (1 << 0) +#endif +#ifndef MODIFIERKEY_LEFT_SHIFT +#define MODIFIERKEY_LEFT_SHIFT (1 << 1) +#endif +#ifndef MODIFIERKEY_LEFT_ALT +#define MODIFIERKEY_LEFT_ALT (1 << 2) +#endif +#ifndef MODIFIERKEY_LEFT_GUI +#define MODIFIERKEY_LEFT_GUI (1 << 3) +#endif + +#ifndef MODIFIERKEY_RIGHT_CTRL +#define MODIFIERKEY_RIGHT_CTRL (1 << 4) +#endif +#ifndef MODIFIERKEY_RIGHT_SHIFT +#define MODIFIERKEY_RIGHT_SHIFT (1 << 5) +#endif +#ifndef MODIFIERKEY_RIGHT_ALT +#define MODIFIERKEY_RIGHT_ALT (1 << 6) +#endif +#ifndef MODIFIERKEY_RIGHT_GUI +#define MODIFIERKEY_RIGHT_GUI (1 << 7) +#endif + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + +typedef struct stc_usbdevice_keyboard +{ + uint8_t u8ModifierKeys; + uint8_t u8Reserved; + uint8_t u8KeyCode1; + uint8_t u8KeyCode2; + uint8_t u8KeyCode3; + uint8_t u8KeyCode4; + uint8_t u8KeyCode5; + uint8_t u8KeyCode6; +} stc_usbdevice_keyboard_t; + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +void UsbDeviceHidKeyboard_Init(stc_usbn_t* pstcUsb); +void UsbDeviceHidKeyboard_SetModifierKey(uint8_t u8ModifierKey); +void UsbDeviceHidKeyboard_ClearModifierKey(uint8_t u8ModifierKey); +void UsbDeviceHidKeyboard_KeyPress(uint8_t u8Index, uint8_t u8KeyCode); +void UsbDeviceHidKeyboard_KeyDown(uint8_t u8Index, uint8_t u8KeyCode); +void UsbDeviceHidKeyboard_KeyUp(uint8_t u8Index, uint8_t u8KeyCode); + +boolean_t UsbDeviceHidKeyboard_IsConnected(void); +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceHidKeyboardGroup +#else + #define UsbDeviceHidKeyboard_Init(x) ; +#endif + +#endif /* __UsbDeviceHidKeyboard__*/ + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.c new file mode 100644 index 0000000000..aa07c45897 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.c @@ -0,0 +1,342 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceHidMouse.c + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidMouseGroup USB Device Mouse Module description @endlink + ** + ** History: + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "UsbDeviceHidMouse.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDMOUSE_ENABLED == ON)) + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +static uint8_t DataSentFlags = 0; //Status for sent data +static uint8_t pu8MouseData[4]; +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; +static stc_usbn_t* pstcUsbHandle = NULL; +static boolean_t bReady = FALSE; + + + + + + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + +static void ConfCallback(stc_usbn_t* pstcUsb); + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + + +/** + ****************************************************************************** + ** \brief Configuration change callback, used to see if configuration is set + ** or cleared + ** + ** \param pstcUsb Pointer to USB instance + ** + ** \return none + ** + ******************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + bReady = TRUE; + } else + { + bReady = FALSE; + } +} + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +void UsbDeviceHidMouse_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x03; // HID Class + stcUsbClassConfig.u8InterfaceSubClass = 0x01; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x02; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = NULL; // setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + /* NOT USED */ + } + else + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + u8NumEndpoints++; + } + } + +} + +/** + ****************************************************************************** + ** Is called from main application to send data via endpoint + ** + ** \param pu8Buffer Buffer to send + ** \param u32DataSize Buffersize + ** \param enMode polled sending, interrupt sending or DMA + ** + ** \return 1: if succesful, 0: if usb was not ready + *****************************************************************************/ +static boolean_t SendData(uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + if (UsbDevice_GetStatus(pstcUsbHandle) == UsbConfigured) + { + DataSentFlags &= ~(1<<1); + + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, u32DataSize, enMode); + if (enMode == UsbPOLL) + { + DataSentFlags |= (1<<1); + } + return TRUE; + } + return FALSE; +} + + +/** + ****************************************************************************** + ** Move Mouse + ** + ** \param i8X Move in X direction + ** + ** \param i8Y Move in Y direction + *****************************************************************************/ +void UsbDeviceHidMouse_Move(int8_t i8X, int8_t i8Y) +{ + pu8MouseData[1] = (int8_t)i8X; + pu8MouseData[2] = (int8_t)i8Y; + SendData((uint8_t*)pu8MouseData,4,UsbPOLL); +} + + +/** + ****************************************************************************** + ** Mouse Left Click (Up-Down-Up) + ** + *****************************************************************************/ +void UsbDeviceHidMouse_LeftClick(void) +{ + UsbDeviceHidMouse_LeftUp(); + UsbDeviceHidMouse_LeftDown(); + UsbDeviceHidMouse_LeftUp(); +} + + +/** + ****************************************************************************** + ** Mouse Left Click (Up-Down-Up-Down-Up) + ** + *****************************************************************************/ +void UsbDeviceHidMouse_LeftDoubleClick(void) +{ + UsbDeviceHidMouse_LeftUp(); + UsbDeviceHidMouse_LeftDown(); + UsbDeviceHidMouse_LeftUp(); + UsbDeviceHidMouse_LeftDown(); + UsbDeviceHidMouse_LeftUp(); +} + +/** + ****************************************************************************** + ** Mouse Left Down + ** + *****************************************************************************/ +void UsbDeviceHidMouse_LeftDown(void) +{ + pu8MouseData[0] |= 0x01; + pu8MouseData[1] = 0; + pu8MouseData[2] = 0; + pu8MouseData[3] = 0; + SendData((uint8_t*)pu8MouseData,4,UsbPOLL); +} + +/** + ****************************************************************************** + ** Mouse Left Up + ** + *****************************************************************************/ +void UsbDeviceHidMouse_LeftUp(void) +{ + pu8MouseData[0] &= ~0x01; + pu8MouseData[1] = 0; + pu8MouseData[2] = 0; + pu8MouseData[3] = 0; + SendData((uint8_t*)pu8MouseData,4,UsbPOLL); +} + +/** + ****************************************************************************** + ** Mouse Right Click (Up-Down-Up) + ** + *****************************************************************************/ +void UsbDeviceHidMouse_RightClick(void) +{ + UsbDeviceHidMouse_RightUp(); + UsbDeviceHidMouse_RightDown(); + UsbDeviceHidMouse_RightUp(); +} + +/** + ****************************************************************************** + ** Mouse Right Click (Up-Down-Up-Down-Up) + ** + *****************************************************************************/ +void UsbDeviceHidMouse_RightDoubleClick(void) +{ + UsbDeviceHidMouse_RightUp(); + UsbDeviceHidMouse_RightDown(); + UsbDeviceHidMouse_RightUp(); + UsbDeviceHidMouse_RightDown(); + UsbDeviceHidMouse_RightUp(); +} + +/** + ****************************************************************************** + ** Mouse Right Down + ** + *****************************************************************************/ +void UsbDeviceHidMouse_RightDown(void) +{ + pu8MouseData[0] |= 0x02; + pu8MouseData[1] = 0; + pu8MouseData[2] = 0; + pu8MouseData[3] = 0; + SendData((uint8_t*)pu8MouseData,4,UsbPOLL); +} + +/** + ****************************************************************************** + ** Mouse Right Up + ** + *****************************************************************************/ +void UsbDeviceHidMouse_RightUp(void) +{ + pu8MouseData[0] &= ~0x02; + pu8MouseData[1] = 0; + pu8MouseData[2] = 0; + pu8MouseData[3] = 0; + SendData((uint8_t*)pu8MouseData,4,UsbPOLL); +} + +/** + ****************************************************************************** + ** Scroll Wheel Movement + ** + ** \param i8Scroll Move + ** + *****************************************************************************/ +void UsbDeviceHidMouse_Scroll(int8_t i8Scroll) +{ + pu8MouseData[1] = 0; + pu8MouseData[2] = 0; + pu8MouseData[3] = (int8_t)i8Scroll; + SendData((uint8_t*)pu8MouseData,4,UsbPOLL); +} + +/** + ****************************************************************************** + ** Return connected state + ** + ** \return TRUE if ready + ** + *****************************************************************************/ +boolean_t UsbDeviceHidMouse_IsConnected(void) +{ + return bReady; +} +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.h new file mode 100644 index 0000000000..c93c5fa912 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceHidMouse.h @@ -0,0 +1,141 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceHidMouse.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceHidMouseGroup USB Device Mouse Module description @endlink + ** + ** History: + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +#ifndef __USBCLASS_H__ +#define __USBCLASS_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "usb.h" + +#ifndef USBDEVICEHIDMOUSE_ENABLED + #define USBDEVICEHIDMOUSE_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEHIDMOUSE_ENABLED == ON)) + +#include "usbdevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceHidMouseGroup USB Device Middleware: HID Mouse + ** + ** Provided functions of USB Device Mouse module: + ** + ** - UsbDeviceHidMouse_Init() + ** - UsbDeviceHidMouse_Scroll() + ** - UsbDeviceHidMouse_RightClick() + ** - UsbDeviceHidMouse_RightDoubleClick() + ** - UsbDeviceHidMouse_RightDown() + ** - UsbDeviceHidMouse_RightUp() + ** - UsbDeviceHidMouse_LeftClick() + ** - UsbDeviceHidMouse_LeftDoubleClick() + ** - UsbDeviceHidMouse_LeftDown() + ** - UsbDeviceHidMouse_LeftUp() + ** - UsbDeviceHidMouse_Move() + ** - UsbDeviceHidMouse_IsConnected() + ** + ** Used to enumerate a mouse device + ** + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + + + + + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +void UsbDeviceHidMouse_Init(stc_usbn_t* pstcUsb); + + +void UsbDeviceHidMouse_Scroll(int8_t i8Scroll); +void UsbDeviceHidMouse_RightClick(void); +void UsbDeviceHidMouse_RightDoubleClick(void); +void UsbDeviceHidMouse_RightDown(void); +void UsbDeviceHidMouse_RightUp(void); +void UsbDeviceHidMouse_LeftClick(void); +void UsbDeviceHidMouse_LeftDoubleClick(void); +void UsbDeviceHidMouse_LeftDown(void); +void UsbDeviceHidMouse_LeftUp(void); +void UsbDeviceHidMouse_Move(int8_t i8X, int8_t i8Y); +boolean_t UsbDeviceHidMouse_IsConnected(void); +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceHidMouseGroup +#else + #define UsbDeviceHidMouse_Init(x) ; +#endif +#endif /* __USBCLASS_H__*/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.c new file mode 100644 index 0000000000..69de383dd1 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.c @@ -0,0 +1,244 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceLibUsb.c + ** + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceLibUsbGroup USB Device LibUSB Module description @endlink + ** + ** History: + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "UsbDeviceLibUsb.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICELIBUSB_ENABLED == ON)) + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +static uint8_t DataReceivedFlags = 0; //Status for received data +static uint8_t DataSentFlags = 0; //Status for sent data + + +static uint32_t u32LastReceivedSize1; // last received size EP1 +static stc_usbn_endpoint_buffer_t stcEpBuffer1; //struct for custom buffer EP1 +static uint8_t pu8BufferEp1[BUFFER_SIZE_ENDPOINT1]; // custom buffer EP1 +static stc_usbn_endpoint_data_t* pstcEpOUT1; + +static stc_usbn_endpoint_data_t* pstcEpIN2; +stc_usbn_endpoint_buffer_t stcEpBuffer2; //struct for custom buffer EP2v + + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + + + +static void UsbDeviceLibUsb_RxCallbackEp1(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); + +static void UsbDeviceLibUsb_TxCallbackEp2(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); + + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** Is called to initialize this class (usally in UsbConfig.c) + ** + ** \param pstcUsb USB Handle + + *****************************************************************************/ +void UsbDeviceLibUsb_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + + stcUsbClassConfig.u8InterfaceNumber = 0; + stcUsbClassConfig.u8InterfaceClass = 0xFF; + stcUsbClassConfig.u8InterfaceSubClass = 0x00; + stcUsbClassConfig.u8InterfaceProtocoll = 0x00; + stcUsbClassConfig.pfnSetupRequestCallback = ClassSetupRequest0; + stcUsbClassConfig.pfnConnectionCallback = NULL; + stcUsbClassConfig.pfnDisconnectionCallback = NULL; + stcUsbClassConfig.pfnConfCallback = NULL; + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + stcEndpointConfig.u8EndpointAddress = 1; + stcEndpointConfig.pfnRxTxCallback = UsbDeviceLibUsb_RxCallbackEp1; + stcEndpointConfig.pstcEndpointBuffer = &stcEpBuffer1; + pstcEpOUT1 = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + UsbDevice_ReceiveData(pstcUsb, pstcEpOUT1, pu8BufferEp1, BUFFER_SIZE_ENDPOINT1, UsbIRQ); + + stcEndpointConfig.u8EndpointAddress = 0x80 | 2; + stcEndpointConfig.pfnRxTxCallback = UsbDeviceLibUsb_TxCallbackEp2; + stcEndpointConfig.pstcEndpointBuffer = &stcEpBuffer2; + pstcEpIN2 = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + +} + +/** + ****************************************************************************** + ** Class Setup Request handling + ** + ** \param pstcUsb USB handle + ** + ** \param pstcSetup Received Setup + ** + *****************************************************************************/ +static void ClassSetupRequest0(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup) +{ + +} + +/** + ****************************************************************************** + ** Is called from UsbDevice.c when a endpoint buffer was received + ** + ** \param pstcUsb USB Handle + ** \param pstcEndpoint Endpoint + + *****************************************************************************/ +static void UsbDeviceLibUsb_RxCallbackEp1(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + u32LastReceivedSize1 = pstcEndpoint->pstcEndpointBuffer->u32DataSize;; + DataReceivedFlags |= (1<<1); // setting data received flag + + //Add your code here to process the received buffer + UsbDevice_ReceiveData(pstcUsb, pstcEpOUT1, pu8BufferEp1, BUFFER_SIZE_ENDPOINT1, UsbIRQ); +} + + +/** + ****************************************************************************** + ** Is used to use received data from endpoint + ** + ** \param ppu8Buffer pointer to buffer + *****************************************************************************/ +uint32_t UsbDeviceLibUsb_GetReceivedDataEndpoint1(uint8_t** ppu8Buffer) +{ + if ((DataReceivedFlags & (1<<1)) == 0) + { + return 0; // nothing to receive + } + DataReceivedFlags -= (1<<1); + *ppu8Buffer = pstcEpOUT1->pstcEndpointBuffer->pu8Buffer; + return u32LastReceivedSize1; +} + + +/** + ****************************************************************************** + ** Is called from main application to send data via endpoint + ** + ** \param pstcUsb USB Handle + ** \param pu8Buffer Buffer to send + ** \param u32DataSize Buffersize + ** \param enMode polled sending, interrupt sending or DMA + ** + ** \return 1: if succesful, 0: if usb was not ready + *****************************************************************************/ +boolean_t UsbDeviceLibUsb_SendDataVia2(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + DataSentFlags &= ~(1<<2); + + UsbDevice_SendData(pstcUsb, pstcEpIN2, pu8Buffer, u32DataSize, enMode); + if (enMode == UsbPOLL) + { + DataSentFlags |= (1<<2); + } + return 1; + } + return 0; +} + +/** + ****************************************************************************** + ** Is called from UsbDevice.c when a endpoint buffer was sent + ** + ** \param pstcUsb USB Handle + ** \param pstcEndpoint Endpoint + *****************************************************************************/ +static void UsbDeviceLibUsb_TxCallbackEp2(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + DataSentFlags |= (1<<2); +} +/** + ****************************************************************************** + ** Is used to use get the sent status of endpoint 2 + ** + *****************************************************************************/ +uint8_t UsbDeviceLibUsb_DataSent2(void) +{ + if ((DataSentFlags & (1<<2)) > 0) + { + return 1; + } + else + { + return 0; + } +} +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.h new file mode 100644 index 0000000000..26c6d0f310 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceLibUsb.h @@ -0,0 +1,126 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceLibUsb.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceLibUsbGroup USB Device LibUSB Module description @endlink + ** + ** History: + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +#ifndef __USBDEVICELIBUSB_H__ +#define __USBDEVICELIBUSB_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "usb.h" + +#ifndef USBDEVICELIBUSB_ENABLED + #define USBDEVICELIBUSB_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICELIBUSB_ENABLED == ON)) + +#include "usbdevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDeviceLibUsbGroup USB Device Middleware: LibUSB + ** + ** Provided functions of USB Device LibUSB module: + ** + ** - UsbDeviceLibUsb_GetReceivedDataEndpoint1() + ** - UsbDeviceLibUsb_SendDataVia2() + ** - UsbDeviceLibUsb_DataSent2() + ** + ** Used to communicate with LibUSB backend + ** + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +#define BUFFER_SIZE_ENDPOINT1 512 + + + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +void UsbDeviceLibUsb_Init(stc_usbn_t* pstcUsb); + +static void ClassSetupRequest0(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup); + +uint32_t UsbDeviceLibUsb_GetReceivedDataEndpoint1(uint8_t** ppu8Buffer); + +boolean_t UsbDeviceLibUsb_SendDataVia2(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); +uint8_t UsbDeviceLibUsb_DataSent2(void); +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceLibUsbGroup +#else + #define UsbDeviceLibUsb_Init(x) ; +#endif +#endif /* __USBCLASS_H__*/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.c new file mode 100644 index 0000000000..29e9237f11 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.c @@ -0,0 +1,941 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceMassStorage.c + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceMassStorageGroup USB Device Mass Storage Module description @endlink + ** + ** History: + ** - 2014-08-19 1.0 MSc First Version + ** - 2014-10-31 1.1 MSc Fix for __STC_LINKED_LIST_ITEM_T__ while use with + ** USB host + ** - 2015-04-16 1.2 MSCH depending on compiler optimization, + ** #pragma pack(1) added also for GCC + ** so structs don't getting destroyed + ** - 2016-07-07 1.3 MSCH fixing wrong max lun inforation (decreased by one) + *****************************************************************************/ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "UsbDeviceMassStorage.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEMASSSTORAGE_ENABLED == ON)) + +#include "base_types.h" +#include "usbdevice.h" +#include "usb.h" + + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); +static boolean_t UsbDeviceMassStorage_SendData(uint8_t* pu8Buffer, uint32_t u32DataSize); +static void ProcessNextTransfer(stc_usbn_t* pstcUsb, stc_msd_lun_command_status_t* pstcCommandStatus); +static void ProcessCbwDeviceSide(stc_msd_lun_t* pstcLun, stc_msd_cbw_t* pstcCbw, uint8_t** ppu8Data, uint32_t* pu32BlockSize, uint32_t* pu32Length,en_usb_device_massstorage_direction_t* penDir); +static void ProcessCbwHostSide(stc_msd_cbw_t* pstcCbw, uint32_t* pu32Length,en_usb_device_massstorage_direction_t* penDir); +static en_result_t CallbackRead10(stc_msd_lun_t* pstcLun); +static en_result_t CallbackWrite10(stc_msd_lun_t* pstcLun); +static en_result_t LunRead(stc_msd_lun_t* pstcLun, uint32_t u32BlockAddress, uint8_t* pu8Data, uint32_t u32Length); +static en_result_t LunWrite(stc_msd_lun_t* pstcLun, uint32_t u32BlockAddress, uint8_t* pu8Data, uint32_t u32Length); + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +static stc_usbn_endpoint_buffer_t stcEndpointBufferOUT; //struct for custom buffer EPOUT +static uint8_t pu8EndpointBufferOUT[BUFFER_SIZE_ENDPOINTOUT]; // custom buffer EPOUT +static stc_usbn_endpoint_data_t* pstcEndpointOUT; +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static volatile boolean_t bDataSent = TRUE; +static stc_usbn_t* pstcUsbHandle = NULL; +static boolean_t bReady = FALSE; +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; //struct for custom buffer EPIN +static pfn_msd_lun_read_t LunReadCallback = LunRead; +static pfn_msd_lun_write_t LunWriteCallback = LunWrite; + +static stc_msd_lun_command_status_t stcCommandStatus; +static stc_msd_lun_list_t stcLunList = {NULL,0}; + +static stc_scsi_mode_parameter_header6_t stcModeParameterHeader6 = +{ + sizeof(stc_scsi_mode_parameter_header6_t) - 1, //!< Length of mode page data is 0x03 + SCSI_MSD_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE, //!< Direct-access block device + 0, //!< Reserved bits + 0, //!< DPO/FUA not supported + 0, //!< Reserved bits + 0, //!< Medium is not write-protected + 0 //!< No block descriptor +}; + +static stc_scsi_inquiry_data_t stcInquiryData = +{ + SCSI_MSD_DIRECT_ACCESS_BLOCK_DEVICE, // Direct-access block device + SCSI_MSD_PERIPHERAL_DEVICE_CONNECTED, // Peripheral device is connected + 0x00, // Reserved bits + 0x01, // Media is removable + SCSI_MSD_SPC_VERSION_4, // SPC-4 supported + 0x2, // Response data format, must be 0x2 + 0, // Hierarchical addressing not supported + 0, // ACA not supported + 0x0, // Obsolete bits + sizeof(stc_scsi_inquiry_data_t) - 5, // Additional Length + 0, // No embedded SCC + 0, // No access control coordinator + SCSI_MSD_TPGS_NONE, // No target port support group + 0, // Third-party copy not supported + 0x0, // Reserved bits + 0, // Protection information not supported + 0, + 0x0, // Obsolete bit + 0, // No embedded enclosure service component + 0x0, // ??? + 0, // Device is not multi-port + 0x0, // Obsolete bits + 0x0, // Unused feature + 0x0, // Unused features + 0, // Task management model not supported + 0x0, // ??? + 0, + 0, + 0, + 0, + {'S','P','A','N','S','I','O','N'}, + {'U','S','B',' ','S','t','o','r','a','g','e',' ',' ',' ',' ',' '}, + {'0','.','0','1'}, + {'S','P','A','N','S','I','O','N','-','U','S','B','-','D','R','I','V','E',' ',' '}, + 0x00, // Unused features + 0x00, // Reserved bits + {SCSI_MSD_VERSION_DESCRIPTOR_SBC_3}, // SBC-3 compliant device + {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} // Reserved +}; + + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** \brief Set callbacks for LUN read / write, if not used, default read / write + ** functionality will be used. + ** + ** \param pfnRead Read callback, if this is NULL, default callback LunRead will be used + ** + ** \param pfnWrite Write callback, if this is NULL, default callback LunWrite will be used + ** + ** \result Ok on success + ** + *****************************************************************************/ +en_result_t UsbDeviceMassStorage_SetLunReadWrite(pfn_msd_lun_read_t pfnRead, pfn_msd_lun_write_t pfnWrite) +{ + if (pfnRead != NULL) + { + LunReadCallback = pfnRead; + } + else + { + LunReadCallback = LunRead; + } + if (pfnWrite != NULL) + { + LunWriteCallback = pfnWrite; + } + else + { + LunWriteCallback = LunWrite; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Get the pointer to a LUN via ID / index of a LUN + ** + ** \param u8ID ID / index of the LUN + ** + ** \result NULL, if no LUN was found for the ID, else the pointer to the LUN + ** + *****************************************************************************/ +stc_msd_lun_t* UsbDeviceMassStorage_GetLun(uint8_t u8Id) +{ + stc_msd_lun_list_item_t* pstcCurrent = stcLunList.pstcRoot; + + while((pstcCurrent != NULL) && (pstcCurrent->u8Id != u8Id)) + { + pstcCurrent = pstcCurrent->pstcNext; + } + if (pstcCurrent == NULL) + { + return NULL; + } + else + { + return pstcCurrent->pstcLun; + } +} + +/** + ****************************************************************************** + ** \brief Add LUN to a list of LUNs + ** + ** \param pstcLunItem List Item, containing pointer of LUN handle + ** + ** \param pstcDisk Pointer of disk / media handle + ** + ** \param pstcCache Pointer to disk cache + ** + ** \param u32BaseAddress LUN Base Address + ** + ** \param u32Size Size of the media / LUN + ** + ** \param u32BlockSize Blocksize of the media / LUN + ** + ** \result Ok on success + ** + *****************************************************************************/ +en_result_t UsbDeviceMassStorage_AddLun(stc_msd_lun_list_item_t* pstcLunItem, stc_msd_lun_disk_t* pstcDisk, stc_msd_lun_cache_t* pstcCache, uint32_t u32BaseAddress, uint32_t u32Size, uint32_t u32BlockSize) +{ + uint32_t u32LogicalBlockAddress = (u32Size / u32BlockSize) - 1; + stc_msd_lun_t* pstcLun = pstcLunItem->pstcLun; + stc_msd_lun_list_item_t* pstcCurrent = stcLunList.pstcRoot; + + if (stcLunList.pstcRoot == NULL) //Check for first item in the list + { + stcLunList.pstcRoot = pstcLunItem; //Add first item in the list + } + else + { + while(pstcCurrent->pstcNext == NULL) //Search for last item in the list + { + pstcCurrent = pstcCurrent->pstcNext; + } + pstcCurrent->pstcNext = pstcLunItem; //Add last item to the list + pstcLunItem->pstcNext = NULL; + pstcLunItem->pstcPrev = pstcCurrent; + } + pstcLunItem->u8Id = stcLunList.u8Count; //Set index of this element + stcLunList.u8Count++; //Increment max data in list + + pstcLun->pstcDisk = pstcDisk; //Initialize disk (media) pointer + pstcLun->u32BaseAddress = u32BaseAddress; //Setup base address + pstcLun->u32Size = u32Size; //Setup size + pstcLun->u32BlockSize = u32BlockSize; //Setup block size + pstcLun->pstcCache = pstcCache; //Setup cache + + //Initialize Request Sense Data + ZERO_STRUCT(pstcLun->stcRequestSenseData); + pstcLun->stcRequestSenseData.u7ResponseCode = SCSI_MSD_SENSE_DATA_FIXED_CURRENT; + pstcLun->stcRequestSenseData.bValid = TRUE; + pstcLun->stcRequestSenseData.u4SenseKey = SCSI_MSD_SENSE_KEY_NO_SENSE; + pstcLun->stcRequestSenseData.u8AdditionalSenseLength = sizeof(stc_scsi_request_sense_data_t) - 8; + + //Initialize Read Capacity Data + U32TOAU8(u32LogicalBlockAddress,pstcLun->stcReadCapacityData.au8LogicalBlockAddress); + U32TOAU8(u32BlockSize,pstcLun->stcReadCapacityData.au8LogicalBlockLength); + + pstcLun->pstcInquiryData = &stcInquiryData; + return Ok; +} + +/** + ****************************************************************************** + ** \brief Decode setup request (class specific) handler + ** + ** \param pstcUsb USB handle + ** + ** \param pstcSetup pointer of setup request + *****************************************************************************/ +static void DecodeSetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup) +{ + uint8_t au8Buffer[1]; + au8Buffer[0] = stcLunList.u8Count - 1; + switch (pstcSetup->bRequest) + { + case MSD_GET_MAX_LUN: + if ((pstcSetup->wValue == 0) && (pstcSetup->wIndex == 0) && (pstcSetup->wLength == 1)) + { + UsbDevice_SendDataControl(pstcUsb, au8Buffer, 1); + } + else + { + pstcUsbHandle->EP0C_f.STAL = 1; + } + break; + case MSD_BULK_ONLY_RESET: + if ((pstcSetup->wValue == 0) && (pstcSetup->wIndex == 0) && (pstcSetup->wLength == 0)) + { + UsbDevice_SendDataControl(pstcUsb, NULL, 0); + } + else + { + pstcUsbHandle->EP0C_f.STAL = 1; + } + break; + default: + pstcUsbHandle->EP0C_f.STAL = 1; + break; + } +} + +/** + ****************************************************************************** + ** \brief Configuration changed callback + ** + ** \param pstcUsb USB handle + ** + *****************************************************************************/ +static void ConfCallback(stc_usbn_t* pstcUsb) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + bReady = TRUE; + } else + { + bReady = FALSE; + } +} + +/** + ****************************************************************************** + ** \brief Init Mass Storage Class during class initialization callback + ** + ** \param pstcUsb USB handle + ** + *****************************************************************************/ +void UsbDeviceMassStorage_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; // do not use fix interface number, choose by class, subclass, protocol + stcUsbClassConfig.u8InterfaceClass = 0x08; // CDC Class + stcUsbClassConfig.u8InterfaceSubClass = 0x06; // Custom Sub Class + stcUsbClassConfig.u8InterfaceProtocoll = 0x50; // Custom Protocol + stcUsbClassConfig.pfnSetupRequestCallback = DecodeSetupRequest; // setup requests handled + stcUsbClassConfig.pfnConnectionCallback = NULL; // No connection callback handled + stcUsbClassConfig.pfnDisconnectionCallback = NULL; // No disconnection callback handled + stcUsbClassConfig.pfnConfCallback = ConfCallback; // Callback for configuration set + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + stcEndpointConfig.pfnRxTxCallback = RxTxCallback; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferOUT; + pstcEndpointOUT = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8EndpointBufferOUT, BUFFER_SIZE_ENDPOINTOUT, UsbIRQ); + } + else + { + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + u8NumEndpoints++; + } + } +} + +/** + ****************************************************************************** + ** \brief Send data via USB (IN Transfer) + ** + ** \param pu8Buffer Buffer + ** \param u32DataSize Datasize + ** + ** \return TRUE at success + ** + *****************************************************************************/ +static boolean_t UsbDeviceMassStorage_SendData(uint8_t* pu8Buffer, uint32_t u32DataSize) +{ + if (pstcUsbHandle == NULL) + { + return FALSE; + } + if (bDataSent == FALSE) + { + return FALSE; + } + if (UsbDevice_GetStatus(pstcUsbHandle) == UsbConfigured) + { + bDataSent = FALSE; + + UsbDevice_SendData(pstcUsbHandle, pstcEndpointIN, pu8Buffer, u32DataSize, UsbIRQ); + + return TRUE; + } + return FALSE; +} + +/** + ****************************************************************************** + ** \brief RX / TX data callback + ** + ** \param pstcUsb USB handle + ** \param pstcEndpoint Endpoint handle + ** + *****************************************************************************/ +static void RxTxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + volatile uint32_t u32i; + en_usb_device_massstorage_direction_t enHostDir; + en_usb_device_massstorage_direction_t enDeviceDir; + uint32_t u32HostLength = 0; + uint32_t u32DeviceLength = 0; + uint32_t u32BlockDeviceLength = 0; + uint8_t* pu8Data = NULL; + stc_msd_cbw_t* pstcCbw = ((stc_msd_cbw_t*)pstcEndpoint->pstcEndpointBuffer->pu8Buffer); + stc_msd_csw_t* pstcCsw = &stcCommandStatus.stcCsw; + boolean_t bCbwReceived = FALSE; + uint32_t u32DataSize = pstcEndpoint->pstcEndpointBuffer->u32DataSize; + if ((pstcEndpoint->u8EndpointAddress) & 0x80) + { + SPANSION_TRACE(1,">IN\r\n"); + bDataSent = TRUE; + } + else + { + SPANSION_TRACE(1,">OUT\r\n"); + if ((u32DataSize == sizeof(stc_msd_cbw_t)) && (pstcCbw->dCBWSignature == MSD_CBW_SIGNATURE)) + { + bCbwReceived = TRUE; + SPANSION_TRACE(1,"\r\n------------ TRANSFER START --------------\r\n"); + SPANSION_TRACE(1,"CBW received \r\n"); + SPANSION_TRACE(1," -bCBWLUN: (0x%08X) \r\n",pstcCbw->bCBWLUN); + SPANSION_TRACE(1," -dCBWDataTransferLength:(0x%08X) \r\n",pstcCbw->dCBWDataTransferLength); + u32HostLength = stcCommandStatus.enStatus = enScsiCommandStateUninitialized; + if (pstcCbw->bCBWLUN < stcLunList.u8Count) + { + ProcessCbwHostSide(pstcCbw,&u32HostLength, &enHostDir); + + ProcessCbwDeviceSide(UsbDeviceMassStorage_GetLun(pstcCbw->bCBWLUN),pstcCbw,&pu8Data,&u32BlockDeviceLength, &u32DeviceLength, &enDeviceDir); + + SPANSION_TRACE(1," -Device Datalength:(0x%08X) \r\n",u32DeviceLength); + if (enDeviceDir == enUsbDeviceMassStorageDeviceToHost) + { + SPANSION_TRACE(1," -Device : Device -> Host\r\n"); + stcCommandStatus.enStatus = enScsiCommandStateWaitWrite; + } else if (enDeviceDir == enUsbDeviceMassStorageHostToDevice) + { + SPANSION_TRACE(1," -Device : Host -> Device\r\n"); + stcCommandStatus.enStatus = enScsiCommandStateWaitRead; + } else + { + SPANSION_TRACE(1," -Device : No transfer\r\n"); + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + } + + if ((enHostDir == enDeviceDir) && (u32HostLength == u32DeviceLength)) //state 1, 6 and 12 + { + pstcCsw->dCSWDataResidue = 0; + if (enDeviceDir == enUsbDeviceMassStorageDeviceToHost) + { + SPANSION_TRACE(1," - OK: Device -> Host\r\n"); + stcCommandStatus.enStatus = enScsiCommandStateWaitWrite; + } else if (enDeviceDir == enUsbDeviceMassStorageHostToDevice) + { + SPANSION_TRACE(1," - OK: Host -> Device\r\n"); + stcCommandStatus.enStatus = enScsiCommandStateWaitRead; + } else + { + SPANSION_TRACE(1," - OK: No transfer\r\n"); + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + } + } else if ((u32HostLength == 0) && (u32DeviceLength != 0)) // state 2 and 3 + { + SPANSION_TRACE(1," - Error state 2 / 3\r\n"); + pstcCsw->bCSWStatus = MSD_CSW_PHASE_ERROR; + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + UsbDevice_HalStallEndpoint(pstcEndpointIN); + } else if ((enHostDir == enUsbDeviceMassStorageDeviceToHost) && (u32HostLength > u32DeviceLength) && ((enDeviceDir == enUsbDeviceMassStorageNoTransfer) || (enDeviceDir == enUsbDeviceMassStorageDeviceToHost))) // case 4 and 5 + { + SPANSION_TRACE(1," - Error state 4 / 5\r\n") + pstcCsw->dCSWDataResidue = u32HostLength - u32DeviceLength; + stcCommandStatus.enStatus = enScsiCommandStateWaitWrite; + //UsbDevice_HalStallEndpoint(pstcEndpointIN); + } else if ((enHostDir == enUsbDeviceMassStorageDeviceToHost) && (u32DeviceLength != u32HostLength)) // case 7 and 8 + { + SPANSION_TRACE(1," - Error state 7 / 8\r\n") + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + UsbDevice_HalStallEndpoint(pstcEndpointIN); + } else if ((enHostDir == enUsbDeviceMassStorageHostToDevice) && (u32DeviceLength > u32HostLength)) + { + SPANSION_TRACE(1," - Error state ) / 11 / 12\r\n") + stcCommandStatus.enStatus = enScsiCommandStateWaitRead; + pstcCsw->dCSWDataResidue = u32HostLength - u32DeviceLength; + } else if ((enHostDir == enUsbDeviceMassStorageHostToDevice) && (u32DeviceLength != u32HostLength)) + { + SPANSION_TRACE(1," - Error state 10 / 13\r\n") + pstcCsw->bCSWStatus = MSD_CSW_PHASE_ERROR; + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + UsbDevice_HalStallEndpoint(pstcEndpointOUT); + } else + { + SPANSION_TRACE(1," - NOT CATCHED CASE\r\n") + } + if (u32BlockDeviceLength == 0) + { + u32BlockDeviceLength = u32DeviceLength; + } + stcCommandStatus.u32Size = u32BlockDeviceLength; + stcCommandStatus.u32Remaining = u32DeviceLength; + stcCommandStatus.pu8Data = pu8Data; + } + else + { + SPANSION_TRACE(1,"Requesting unknown LUN\r\n"); + UsbDevice_HalStallEndpoint(pstcEndpointOUT); + } + + } + } + + if ((bCbwReceived == FALSE) && (stcCommandStatus.stcCurrentTransfer.pfnCallback != NULL)) + { + stcCommandStatus.stcCurrentTransfer.pfnCallback(UsbDeviceMassStorage_GetLun(stcCommandStatus.stcCbw.bCBWLUN)); + } + + ProcessNextTransfer(pstcUsb, &stcCommandStatus); + + SPANSION_TRACE(1,"dCBWDataTransferLength; + if (pstcCbw->dCBWDataTransferLength == 0) + { + *penDir = enUsbDeviceMassStorageNoTransfer; + SPANSION_TRACE(1," - Host: no transfer\r\n"); + } else if (pstcCbw->bmCBWFlags & MSD_CBW_DEVICE_TO_HOST) + { + *penDir = enUsbDeviceMassStorageDeviceToHost; + SPANSION_TRACE(1," - Host: device -> host\r\n"); + } else + { + *penDir = enUsbDeviceMassStorageHostToDevice; + SPANSION_TRACE(1," - Host: host -> device\r\n"); + } +} + +/** + ****************************************************************************** + ** \brief Process next data transfer defined by pstcCommandStatus + ** + ** \param pstcUsb USB handle + ** + ** \param pstcCommandStatus Command Transport Package + ** + *****************************************************************************/ +static void ProcessNextTransfer(stc_usbn_t* pstcUsb, stc_msd_lun_command_status_t* pstcCommandStatus) +{ + switch(pstcCommandStatus->enStatus) + { + case enScsiCommandStateWaitWrite: + SPANSION_TRACE(1,"/>START WRITE Size: (0x%04X)\r\n",pstcCommandStatus->u32Size); + UsbDeviceMassStorage_SendData (pstcCommandStatus->pu8Data, pstcCommandStatus->u32Size); + pstcCommandStatus->enStatus = enScsiCommandStateNextBlock; + break; + case enScsiCommandStateWaitRead: + SPANSION_TRACE(1,"/>START READ Size: (0x%04X)\r\n",pstcCommandStatus->u32Size); + stcEndpointBufferOUT.u32BufferSize = stcCommandStatus.u32Size; + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pstcCommandStatus->pu8Data, pstcCommandStatus->u32Size, UsbIRQ); + pstcCommandStatus->enStatus = enScsiCommandStateNextBlock; + break; + case enScsiCommandStateNextBlock: + pstcCommandStatus->stcCurrentTransfer.pfnCallback = NULL; + SPANSION_TRACE(1,"/>END, sending CSW\r\n"); + UsbDeviceMassStorage_SendData ((uint8_t*)&pstcCommandStatus->stcCsw, sizeof(stc_msd_csw_t)); + pstcCommandStatus->enStatus = enScsiCommandStateUninitialized; + SPANSION_TRACE(1,"\r\n------------ TRANSFER STOP --------------\r\n"); + break; + case enScsiCommandStateUninitialized: + pstcCommandStatus->stcCurrentTransfer.pfnCallback = NULL; + SPANSION_TRACE(1,"/>Wait for data...\r\n"); + stcEndpointBufferOUT.u32BufferSize = sizeof(pu8EndpointBufferOUT); + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8EndpointBufferOUT, pstcEndpointOUT->u16EndpointSize, UsbIRQ); + break; + default: + pstcCommandStatus->stcCurrentTransfer.pfnCallback = NULL; + SPANSION_TRACE(1,"/>WARNING: unknown state, waiting for data...\r\n"); + stcEndpointBufferOUT.u32BufferSize = sizeof(pu8EndpointBufferOUT); + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8EndpointBufferOUT, pstcEndpointOUT->u16EndpointSize, UsbIRQ); + pstcCommandStatus->enStatus = enScsiCommandStateUninitialized; + break; + } +} + + +/** + ****************************************************************************** + ** \brief Process and decode CBW from device side + ** + ** \param pstcLun LUN pointer + ** + ** \param pstcCbw pointer of CBW + ** + ** \param ppu8Data data pointer returned + ** + ** \param pu32BlockSize block to transfer + ** + ** \param pu32Length Return data pointer of expected length from device + ** + ** \param penDir Return direction pointer of expected transfer direction from device + ** + *****************************************************************************/ +static void ProcessCbwDeviceSide(stc_msd_lun_t* pstcLun, stc_msd_cbw_t* pstcCbw, uint8_t** ppu8Data, uint32_t* pu32BlockSize, uint32_t* pu32Length,en_usb_device_massstorage_direction_t* penDir) +{ + stc_scsi_command_t* pstcCommand = (stc_scsi_command_t*)pstcCbw->au16Command; + stc_msd_csw_t* pstcCsw = &stcCommandStatus.stcCsw; + uint32_t u32LogicalBlockAddres; + + pstcCsw->dCSWSignature = 0x53425355; + pstcCsw->dCSWTag = pstcCbw->dCBWTag; + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + COPY_STRUCT(stcCommandStatus.stcCbw,*pstcCbw); + stcCommandStatus.enStatus = enScsiCommandStateUninitialized; + stcCommandStatus.pu8Data = NULL; + *pu32Length = 0; + *pu32BlockSize = 0; + *penDir = enUsbDeviceMassStorageNoTransfer; + stcCommandStatus.u32Remaining = 0; + switch (pstcCommand->u8OperationCode) + { + case SCSI_MSD_INQUIRY: + *pu32Length = sizeof(stc_scsi_inquiry_data_t); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + *ppu8Data = (uint8_t*)pstcLun->pstcInquiryData; + *penDir = enUsbDeviceMassStorageDeviceToHost; + if (pstcCbw->dCBWDataTransferLength < *pu32Length) + { + *pu32Length = pstcCbw->dCBWDataTransferLength; + } + SPANSION_TRACE(1," ->SCSI_MSD_INQUIRY\r\n"); + break; + case SCSI_MSD_MODE_SENSE_6: + if (pstcCommand->stcModeSense6.u6PageCode == SCSI_MSD_PAGE_RETURN_ALL) + { + *pu32Length = sizeof(stcModeParameterHeader6); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + *ppu8Data = (uint8_t*)&stcModeParameterHeader6; + if (pstcLun->pstcDisk->pfnWrite == NULL) + { + stcModeParameterHeader6.bWP = TRUE; + } + else + { + stcModeParameterHeader6.bWP = FALSE; + } + *penDir = enUsbDeviceMassStorageDeviceToHost; + if (pstcCommand->stcModeSense6.u8AllocationLength < sizeof(stcModeParameterHeader6)) + { + *pu32Length = pstcCommand->stcModeSense6.u8AllocationLength; + } + } + SPANSION_TRACE(1," ->SCSI_MSD_MODE_SENSE_6\r\n"); + break; + case SCSI_MSD_PREVENT_ALLOW_MEDIUM_REMOVAL: + SPANSION_TRACE(1," ->SCSI_MSD_PREVENT_ALLOW_MEDIUM_REMOVAL\r\n"); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + break; + case SCSI_MSD_REQUEST_SENSE: + SPANSION_TRACE(1," ->SCSI_MSD_REQUEST_SENSE\r\n"); + *pu32Length = pstcCommand->stcRequestSense.u8AllocationLength; + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + *ppu8Data = (uint8_t*)&pstcLun->stcRequestSenseData; + *penDir = enUsbDeviceMassStorageDeviceToHost; + break; + case SCSI_MSD_TEST_UNIT_READY: + switch(pstcLun->pstcDisk->enState) + { + case enMsdLunDiskStateReady: + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + break; + case enMsdLunDiskStateBusy: + pstcLun->stcRequestSenseData.u4SenseKey = SCSI_MSD_SENSE_KEY_NOT_READY; + pstcLun->stcRequestSenseData.u8AdditionalSenseCode = 0; + pstcLun->stcRequestSenseData.u8AdditionalSenseCodeQualifier = 0; + break; + default: + pstcLun->stcRequestSenseData.u4SenseKey = SCSI_MSD_SENSE_KEY_NOT_READY; + pstcLun->stcRequestSenseData.u8AdditionalSenseCode = SCSI_MSD_ASC_MEDIUM_NOT_PRESENT; + pstcLun->stcRequestSenseData.u8AdditionalSenseCodeQualifier = 0; + break; + } + SPANSION_TRACE(1," ->SCSI_MSD_TEST_UNIT_READY\r\n"); + break; + case SCSI_MSD_READ_CAPACITY_10: + SPANSION_TRACE(1," ->SCSI_MSD_READ_CAPACITY_10\r\n"); + *pu32Length = sizeof(pstcLun->stcReadCapacityData); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + *ppu8Data = (uint8_t*)&pstcLun->stcReadCapacityData; + *penDir = enUsbDeviceMassStorageDeviceToHost; + break; + case SCSI_MSD_READ_10: + u32LogicalBlockAddres = AU8TOU32(pstcCommand->stcRead10.au8LogicalBlockAddress); + if (pstcLun->pstcDisk->pfnRead == NULL) + { + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + SPANSION_TRACE(1," ->FAILED, no read callback\r\n"); + } + else + { + SPANSION_TRACE(1," ->SCSI_MSD_READ_10\r\n"); + *pu32Length = (AU8TOU16(pstcCommand->stcRead10.au8TransferLength))* (pstcLun->u32BlockSize); + SPANSION_TRACE(1," ->prebuffering one block\r\n"); + if (LunReadCallback(pstcLun,AU8TOU32(pstcCommand->stcRead10.au8LogicalBlockAddress),pstcLun->pstcCache->pu8Buffer,1) == Ok) + { + *ppu8Data = pstcLun->pstcCache->pu8Buffer; + *pu32BlockSize = pstcLun->pstcCache->u32CacheSize; + *penDir = enUsbDeviceMassStorageDeviceToHost; + stcCommandStatus.stcCurrentTransfer.pfnCallback = CallbackRead10; + SPANSION_TRACE(1," ->LOGICAL BLOCK (0x%08X)\r\n",AU8TOU32(pstcCommand->stcRead10.au8LogicalBlockAddress)); + SPANSION_TRACE(1," ->read 1 block\r\n"); + u32LogicalBlockAddres++; + U32TOAU8(u32LogicalBlockAddres,((stc_scsi_command_t*)stcCommandStatus.stcCbw.au16Command)->stcRead10.au8LogicalBlockAddress); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + } + else + { + SPANSION_TRACE(1," ->FAILED\r\n"); + } + } + break; + case SCSI_MSD_WRITE_10: + if (pstcLun->pstcDisk->pfnWrite == NULL) + { + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_FAILED; + SPANSION_TRACE(1," ->FAILED, no write callback\r\n"); + } + else + { + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + *pu32Length = AU8TOU16(pstcCommand->stcWrite10.au8TransferLength) * pstcLun->u32BlockSize; + *pu32BlockSize = pstcLun->pstcCache->u32CacheSize; + *ppu8Data = pstcLun->pstcCache->pu8Buffer; + *penDir = enUsbDeviceMassStorageHostToDevice; + stcCommandStatus.stcCurrentTransfer.pfnCallback = CallbackWrite10; + SPANSION_TRACE(1," ->SCSI_MSD_WRITE_10\r\n"); + } + break; + case SCSI_MSD_VERIFY_10: + SPANSION_TRACE(1," ->SCSI_MSD_VERIFY_10\r\n"); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + break; + default: + SPANSION_TRACE(2," ->CMD UNKNOWN (0x%02X)\r\n",pstcCommand->u8OperationCode); + *pu32Length = 0; + *ppu8Data = NULL; + break; + } + +} + +/** + ****************************************************************************** + ** \brief Callback to process next data package for READ10 command + ** + ** \param pstcLun LUN pointer + ** + ** \return Ok, if successful + ** + *****************************************************************************/ +static en_result_t CallbackRead10(stc_msd_lun_t* pstcLun) +{ + stc_msd_csw_t* pstcCsw = &stcCommandStatus.stcCsw; + stc_scsi_command_t* pstcCommand = (stc_scsi_command_t*)(stcCommandStatus.stcCbw.au16Command); + uint32_t u32LogicalBlockAddres = AU8TOU32(pstcCommand->stcRead10.au8LogicalBlockAddress); + stcCommandStatus.u32Remaining -= pstcLun->u32BlockSize; + if (stcCommandStatus.u32Remaining != 0) + { + if (LunReadCallback(pstcLun,AU8TOU32(pstcCommand->stcRead10.au8LogicalBlockAddress),pstcLun->pstcCache->pu8Buffer,1) == Ok) + { + SPANSION_TRACE(1," ->LOGICAL BLOCK (0x%08X)\r\n",AU8TOU32(pstcCommand->stcRead10.au8LogicalBlockAddress)); + SPANSION_TRACE(1," ->read 1 block\r\n"); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + stcCommandStatus.u32Size = pstcLun->u32BlockSize; + stcCommandStatus.pu8Data = pstcLun->pstcCache->pu8Buffer; + stcCommandStatus.enStatus = enScsiCommandStateWaitWrite; + u32LogicalBlockAddres++; + U32TOAU8(u32LogicalBlockAddres,((stc_scsi_command_t*)stcCommandStatus.stcCbw.au16Command)->stcRead10.au8LogicalBlockAddress); + } + } + else + { + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Callback to process next data package for WRITE10 command + ** + ** \param pstcLun LUN pointer + ** + ** \return Ok, if successful + ** + *****************************************************************************/ +static en_result_t CallbackWrite10(stc_msd_lun_t* pstcLun) +{ + stc_msd_csw_t* pstcCsw = &stcCommandStatus.stcCsw; + stc_scsi_command_t* pstcCommand = (stc_scsi_command_t*)(stcCommandStatus.stcCbw.au16Command); + uint32_t u32LogicalBlockAddres = AU8TOU32(pstcCommand->stcWrite10.au8LogicalBlockAddress); + SPANSION_TRACE(1," ->EP Received Size (0x%08X)\r\n",pstcEndpointOUT->pstcEndpointBuffer->u32DataSize); + if (LunWriteCallback(pstcLun,AU8TOU32(pstcCommand->stcWrite10.au8LogicalBlockAddress),pstcLun->pstcCache->pu8Buffer,1) == Ok) + { + SPANSION_TRACE(1," ->LOGICAL BLOCK (0x%08X)\r\n",AU8TOU32(pstcCommand->stcWrite10.au8LogicalBlockAddress)); + SPANSION_TRACE(1," ->write 1 block\r\n"); + pstcCsw->bCSWStatus = MSD_CSW_COMMAND_PASSED; + stcCommandStatus.u32Size = pstcLun->u32BlockSize; + stcCommandStatus.pu8Data = pstcLun->pstcCache->pu8Buffer; + stcCommandStatus.enStatus = enScsiCommandStateWaitRead; + u32LogicalBlockAddres++; + U32TOAU8(u32LogicalBlockAddres,((stc_scsi_command_t*)stcCommandStatus.stcCbw.au16Command)->stcWrite10.au8LogicalBlockAddress); + } + stcCommandStatus.u32Remaining -= pstcLun->u32BlockSize; + if (stcCommandStatus.u32Remaining == 0) + { + stcCommandStatus.enStatus = enScsiCommandStateNextBlock; + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Default callback for LUN read + ** + ** \param pstcLun LUN pointer + ** + ** \param u32BlockAddress Block Address + ** + ** \param pu8Data Data + ** + ** \param u32Length Data Size + ** + ** \return Ok, if successful + ** + *****************************************************************************/ +static en_result_t LunRead(stc_msd_lun_t* pstcLun, uint32_t u32BlockAddress, uint8_t* pu8Data, uint32_t u32Length) +{ + uint32_t u32Address = (uint32_t)pstcLun->pstcDisk->u32BaseAddress + pstcLun->u32BaseAddress + ((uint32_t)u32BlockAddress * pstcLun->u32BlockSize); + if ((u32Length * pstcLun->u32BlockSize) > (pstcLun->u32Size - pstcLun->u32BlockSize * u32BlockAddress)) + { + return Error; + } + else + { + pstcLun->pstcDisk->pfnRead(pstcLun->pstcDisk,u32Address,pu8Data,u32Length * pstcLun->u32BlockSize,NULL,NULL); + } + return Ok; +} + +/** + ****************************************************************************** + ** \brief Default callback for LUN write + ** + ** \param pstcLun LUN pointer + ** + ** \param u32BlockAddress Block Address + ** + ** \param pu8Data Data + ** + ** \param u32Length Data Size + ** + ** \return Ok, if successful + ** + *****************************************************************************/ +static en_result_t LunWrite(stc_msd_lun_t* pstcLun, uint32_t u32BlockAddress, uint8_t* pu8Data, uint32_t u32Length) +{ + uint32_t u32Address = (uint32_t)pstcLun->pstcDisk->u32BaseAddress + pstcLun->u32BaseAddress + ((uint32_t)u32BlockAddress * pstcLun->u32BlockSize); + if ((u32Length * pstcLun->u32BlockSize) > (pstcLun->u32Size - pstcLun->u32BlockSize * u32BlockAddress)) + { + return Error; + } + else + { + pstcLun->pstcDisk->pfnWrite(pstcLun->pstcDisk,u32Address,pu8Data,u32Length * pstcLun->u32BlockSize,NULL,NULL); + } + return Ok; +} + + +#endif /* ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEMASSSTORAGE_ENABLED == ON)) */ + + + + + diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.h new file mode 100644 index 0000000000..a766997682 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDeviceMassStorage.h @@ -0,0 +1,859 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDeviceMassStorage.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDeviceMassStorageGroup USB Device Mass Storage Module description @endlink + ** + ** History: + ** - 2014-08-19 1.0 MSc First Version + ** - 2014-10-31 1.1 MSc Fix for __STC_LINKED_LIST_ITEM_T__ while use with + ** USB host + ** - 2015-04-16 1.2 MSCH depending on compiler optimization, + ** #pragma pack(1) added also for GCC + ** so structs don't getting destroyed + ** - 2016-07-07 1.3 MSCH fixing wrong max lun inforation (decreased by one) + *****************************************************************************/ + +#ifndef __USBDEVICEMASSSTORAGE_H__ +#define __USBDEVICEMASSSTORAGE_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "usb.h" + +#ifndef USBDEVICEMASSSTORAGE_ENABLED + #define USBDEVICEMASSSTORAGE_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEMASSSTORAGE_ENABLED == ON)) + +#include "UsbDevice.h" +#include "base_types.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + + /** + ****************************************************************************** + ** \defgroup UsbDeviceMassStorageGroup USB Device Middleware: Mass Storage + ** + ** Provided functions of USB module: + ** + ** - UsbDeviceMassStorage_SetLunReadWrite() + ** - UsbDeviceMassStorage_GetLun() + ** - UsbDeviceMassStorage_AddLun() + ** - UsbDeviceMassStorage_Init() + ** + ** UsbDeviceMassStorage_AddLun is called before initializing USB. + ** UsbDeviceMassStorage_SetLunReadWrite adds the possibility to add own LUN read/write routines. + ** UsbDeviceMassStorage_Init called in usb class initialization phase. + ** + ******************************************************************************/ +//@{ + +#define NO_TRACE + +#define USBDEVICEMASSSTORAGE_VERSION 0100 + +#if defined(__ICCARM__) // IAR Workbench + #pragma pack(1) + #define __attribute__(...) +#elif defined(__CC_ARM) // ARM MDK / Keil �Vision + #pragma pack(1) + #define __attribute__(...) +#elif defined(__GNUC__) // GNU Compiler + #pragma pack(1) + /* nothing else needed */ +#endif + + +#ifndef __MSD__ +#define __MSD__ +/* Mass Storage structures and defines */ +/* - 2014-08-11 V10 MSc First Version */ + +#define MSD_VERSION 0100 + +/* Class-specific requests */ +#define MSD_BULK_ONLY_RESET 0xFF +#define MSD_GET_MAX_LUN 0xFE + +/* Subclass codes */ +#define MSD_SUBCLASS_RBC 0x01 //<-- Reduced Block Commands (RBC) T10 +#define MSD_SUBCLASS_SFF_MCC 0x02 //<-- C/DVD devices +#define MSD_SUBCLASS_QIC 0x03 //<-- Tape device +#define MSD_SUBCLASS_UFI 0x04 //<-- Floppy disk drive (FDD) device +#define MSD_SUBCLASS_SFF 0x05 //<-- Floppy disk drive (FDD) device +#define MSD_SUBCLASS_SCSI 0x06 //<-- SCSI transparent command set + +/* Table 3.1 - Mass Storage Transport Protocol (see usb_msc_overview_1.2.pdf) */ +#define MSD_PROTOCOL_CBI_COMPLETION 0x00 +#define MSD_PROTOCOL_CBI 0x01 +#define MSD_PROTOCOL_BULK_ONLY 0x50 + +/* Test unit control: */ +#define MSD_CTRL_NOT_READY 0x00 +#define MSD_CTRL_GOOD 0x01 +#define MSD_CTRL_BUSY 0x02 + +/* Command block wrapper */ +#define MSD_CBW_SIZE 31 //<-- Command Block Wrapper Size +#define MSD_CBW_SIGNATURE 0x43425355 //<-- 'USBC' 0x43425355 + +/* Command status wrapper */ +#define MSD_CSW_SIZE 13 +#define MSD_CSW_SIGNATURE 0x53425355 + +/* Table 5.3 - Command Block Status Values (usbmassbulk_10.pdf) */ +#define MSD_CSW_COMMAND_PASSED 0 +#define MSD_CSW_COMMAND_FAILED 1 +#define MSD_CSW_PHASE_ERROR 2 + +/* CBW bmCBWFlags field */ +#define MSD_CBW_DEVICE_TO_HOST (1 << 7) + +/************************************************************************** + ** \brief Command Block Wrapper + ** + ** Table 5.1 - Command Block Wrapper (see usbmassbulk_10.pdf) + ** The CBW shall start on a packet boundary and shall end as a + ** short packet with exactly 31 (1Fh) bytes transferred. + **************************************************************************/ +typedef struct stc_msd_cbw +{ + uint32_t dCBWSignature; //<-- 'USBC' 0x43425355 (little endian) + uint32_t dCBWTag; //<-- Must be the same as dCSWTag + uint32_t dCBWDataTransferLength; //<-- Number of bytes transfer + uint8_t bmCBWFlags; //<-- Indicates the directin of the + // transfer: 0x80=IN=device-to-host, + // 0x00=OUT=host-to-device + uint8_t bCBWLUN :4; //<-- bits 0->3: bCBWLUN + uint8_t bReserved1 :4; //<-- reserved + uint8_t bCBWCBLength :5; //<-- bits 0->4: bCBWCBLength + uint8_t bReserved2 :3; //<-- reserved + uint8_t au16Command[16]; //<-- Command block +} stc_msd_cbw_t; + +/**************************************************************************//** + ** \brief Command Status Wrapper + ** + ** Table 5.2 - Command Status Wrapper (CSW) (usbmassbulk_10.pdf) + *****************************************************************************/ +typedef struct stc_msd_csw +{ + uint32_t dCSWSignature; //<-- 'USBS' 0x53425355 (little endian) + uint32_t dCSWTag; //<-- Must be the same as dCBWTag + uint32_t dCSWDataResidue; //<-- For Data-Out the device shall report in the dCSWDataResidue the difference between the amount of + // data expected as stated in the dCBWDataTransferLength, and the actual amount of data processed by + // the device. For Data-In the device shall report in the dCSWDataResidue the difference between the + // amount of data expected as stated in the dCBWDataTransferLength and the actual amount of relevant + // data sent by the device. The dCSWDataResidue shall not exceed the value sent in the dCBWDataTransferLength. + uint8_t bCSWStatus; //<-- Indicates the success or failure of the command. +} stc_msd_csw_t; + +#endif /* __MSD__ */ + + +#ifndef __SCSI_MSD__ +#define __SCSI_MSD__ +/* see also Segate SCSI Commands Reference Manual Rev. A */ +/* - 2014-08-11 V10 MSc First Version */ + +#define SCSI_MSD_VERSION 0100 + + +/* Operation codes of commands described in the SBC-3 standard */ +#define SCSI_MSD_INQUIRY 0x12 +#define SCSI_MSD_READ_10 0x28 +#define SCSI_MSD_READ_CAPACITY_10 0x25 +#define SCSI_MSD_REQUEST_SENSE 0x03 +#define SCSI_MSD_TEST_UNIT_READY 0x00 +#define SCSI_MSD_WRITE_10 0x2A + +/* Optional according to the standard, required by Windows */ +#define SCSI_MSD_PREVENT_ALLOW_MEDIUM_REMOVAL 0x1E +#define SCSI_MSD_MODE_SENSE_6 0x1A +#define SCSI_MSD_VERIFY_10 0x2F + +/* Peripheral qualifier values specified in the INQUIRY data */ +#define SCSI_MSD_PERIPHERAL_DEVICE_CONNECTED 0x00 +#define SCSI_MSD_PERIPHERAL_DEVICE_NOT_CONNECTED 0x01 +#define SCSI_MSD_PERIPHERAL_DEVICE_NOT_SUPPORTED 0x03 + +/* Peripheral device types specified in the INQUIRY data */ +#define SCSI_MSD_DIRECT_ACCESS_BLOCK_DEVICE 0x00 +#define SCSI_MSD_SEQUENTIAL_ACCESS_DEVICE 0x01 +#define SCSI_MSD_PRINTER_DEVICE 0x02 +#define SCSI_MSD_PROCESSOR_DEVICE 0x03 +#define SCSI_MSD_WRITE_ONCE_DEVICE 0x04 +#define SCSI_MSD_CD_DVD_DEVICE 0x05 +#define SCSI_MSD_SCANNER_DEVICE 0x06 +#define SCSI_MSD_OPTICAL_MEMORY_DEVICE 0x07 +#define SCSI_MSD_MEDIA_CHANGER_DEVICE 0x08 +#define SCSI_MSD_COMMUNICATION_DEVICE 0x09 +#define SCSI_MSD_STORAGE_ARRAY_CONTROLLER_DEVICE 0x0C +#define SCSI_MSD_ENCLOSURE_SERVICES_DEVICE 0x0D +#define SCSI_MSD_SIMPLIFIED_DIRECT_ACCESS_DEVICE 0x0E +#define SCSI_MSD_OPTICAL_CARD_READER_WRITER_DEVICE 0x0F +#define SCSI_MSD_BRIDGE_CONTROLLER_COMMANDS 0x10 +#define SCSI_MSD_OBJECT_BASED_STORAGE_DEVICE 0x11 + +/* Version value for the SBC-3 specification */ +#define SCSI_MSD_SPC_VERSION_4 0x06 + +/* Values for the TPGS field returned in INQUIRY data */ +#define SCSI_MSD_TPGS_NONE 0x0 +#define SCSI_MSD_TPGS_ASYMMETRIC 0x1 +#define SCSI_MSD_TPGS_SYMMETRIC 0x2 +#define SCSI_MSD_TPGS_BOTH 0x3 + +/* Version descriptor value for the SBC-3 specification */ +#define SCSI_MSD_VERSION_DESCRIPTOR_SBC_3 0x04C0 + +/* Sense data response codes returned in REQUEST SENSE data */ +#define SCSI_MSD_SENSE_DATA_FIXED_CURRENT 0x70 +#define SCSI_MSD_SENSE_DATA_FIXED_DEFERRED 0x71 +#define SCSI_MSD_SENSE_DATA_DESCRIPTOR_CURRENT 0x72 +#define SCSI_MSD_SENSE_DATA_DESCRIPTOR_DEFERRED 0x73 + +/* Sense key values returned in the REQUEST SENSE data */ +#define SCSI_MSD_SENSE_KEY_NO_SENSE 0x00 +#define SCSI_MSD_SENSE_KEY_RECOVERED_ERROR 0x01 +#define SCSI_MSD_SENSE_KEY_NOT_READY 0x02 +#define SCSI_MSD_SENSE_KEY_MEDIUM_ERROR 0x03 +#define SCSI_MSD_SENSE_KEY_HARDWARE_ERROR 0x04 +#define SCSI_MSD_SENSE_KEY_ILLEGAL_REQUEST 0x05 +#define SCSI_MSD_SENSE_KEY_UNIT_ATTENTION 0x06 +#define SCSI_MSD_SENSE_KEY_DATA_PROTECT 0x07 +#define SCSI_MSD_SENSE_KEY_BLANK_CHECK 0x08 +#define SCSI_MSD_SENSE_KEY_VENDOR_SPECIFIC 0x09 +#define SCSI_MSD_SENSE_KEY_COPY_ABORTED 0x0A +#define SCSI_MSD_SENSE_KEY_ABORTED_COMMAND 0x0B +#define SCSI_MSD_SENSE_KEY_VOLUME_OVERFLOW 0x0D +#define SCSI_MSD_SENSE_KEY_MISCOMPARE 0x0E + +/* Additional sense code values returned in REQUEST SENSE data */ +#define SCSI_MSD_ASC_LOGICAL_UNIT_NOT_READY 0x04 +#define SCSI_MSD_ASC_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE 0x21 +#define SCSI_MSD_ASC_INVALID_FIELD_IN_CDB 0x24 +#define SCSI_MSD_ASC_WRITE_PROTECTED 0x27 +#define SCSI_MSD_ASC_FORMAT_CORRUPTED 0x31 +#define SCSI_MSD_ASC_INVALID_COMMAND_OPERATION_CODE 0x20 +#define SCSI_MSD_ASC_TOO_MUCH_WRITE_DATA 0x26 +#define SCSI_MSD_ASC_NOT_READY_TO_READY_CHANGE 0x28 +#define SCSI_MSD_ASC_MEDIUM_NOT_PRESENT 0x3A + +/* MEDIUM TYPE field value for direct-access block devices */ +#define SCSI_MSD_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE 0x00 + +/* MRIE field values */ +#define SCSI_MSD_MRIE_NO_REPORTING 0x00 +#define SCSI_MSD_MRIE_ASYNCHRONOUS 0x01 +#define SCSI_MSD_MRIE_GENERATE_UNIT_ATTENTION 0x02 +#define SCSI_MSD_MRIE_COND_GENERATE_RECOVERED_ERROR 0x03 +#define SCSI_MSD_MRIE_UNCOND_GENERATE_RECOVERED_ERROR 0x04 +#define SCSI_MSD_MRIE_GENERATE_NO_SENSE 0x05 +#define SCSI_MSD_MRIE_ON_REQUEST 0x06 + +/* Supported mode pages */ +#define SCSI_MSD_PAGE_READ_WRITE_ERROR_RECOVERY 0x01 +#define SCSI_MSD_PAGE_INFORMATIONAL_EXCEPTIONS_CONTROL 0x1C +#define SCSI_MSD_PAGE_RETURN_ALL 0x3F +#define SCSI_MSD_PAGE_VENDOR_SPECIFIC 0x00 + +/************************************************************************** + ** \brief Command States + ** + **************************************************************************/ +typedef enum en_scsi_command_state +{ + enScsiCommandStateUninitialized = 0, + enScsiCommandStateRead = 1, + enScsiCommandStateWaitRead = 2, + enScsiCommandStateWrite = 3, + enScsiCommandStateWaitWrite = 4, + enScsiCommandStateNextBlock = 5 +} en_scsi_command_state_t; + +/************************************************************************** + ** \brief Inquiry Command + ** + **************************************************************************/ +typedef struct stc_scsi_inquiry +{ + uint8_t u8OperationCode; //<-- must be 0x12 + uint8_t bEVPD:1; //<-- EVPD (Enable Vital Product Data) bit + uint8_t u8Reserved1:7; + uint8_t u8PageCode; + uint16_t u16AllocationLength; + uint8_t u8Control; +} __attribute__ ((packed)) stc_scsi_inquiry_t; + +/************************************************************************** + ** \brief Command Inquiry Command Response Data + ** + **************************************************************************/ +typedef struct stc_scsi_inquiry_data +{ + uint8_t u8PeripheralDeviceType:5; //<-- Peripheral Device Type + uint8_t u8PeripheralQualifier :3; //<-- Peripheral Qualifier + + uint8_t u7Reserved1 :7; //<-- Reserved + uint8_t bRMB :1; //<-- RMB (Removable Media) bit + + uint8_t u8Version; //<-- Version + + uint8_t u8ResponseDataFormat :4; //<-- Must be 0x2 + uint8_t bHiSup :1; //<-- HISUP (Hierarchical Support) bit + uint8_t bNormACA :1; //<-- NORMACA (Normal ACA Supported) + uint8_t u2Obsolete1 :2; //<-- Obsolete + + uint8_t u8AdditionalLength; //<-- (N - 4): Length of remaining INQUIRY data + + uint8_t bProtect :1; //<-- PROTECT bit + uint8_t u2Reserved2 :2; //<-- Reserved + uint8_t b3PC :1; //<-- 3PC (Third-Party Copy) bit + uint8_t u2TPGS :2; //<-- TPGS (Target Port Group Support) field + uint8_t bACC :1; //<-- ACC (Access Controls Coordinator) bit + uint8_t bSCCS :1; //<-- SCCS (SCC Supported) bit + + uint8_t bAddr16 :1; //<-- + uint8_t u2Obsolete2 :2; //<-- Obsolete + uint8_t bMCHNGR :1; //<-- MCHNGR (Medium Changer) bit + uint8_t bMultiP :1; //<-- MULTIP (Multi Port) bit + uint8_t bVS1 :1; //<-- + uint8_t bEncServ :1; //<-- ENCSERV (Enclosure Services) bit + uint8_t bBQue :1; //<-- BQUE (Basic Queuing) bit + + uint8_t bVS2 :1; //<-- + uint8_t bCmdQue :1; //<-- CMDQUE (Command Queuing) bit + uint8_t bObsolete3 :1; //<-- Obsolete + uint8_t bLinked :1; //<-- LINKED (Linked Command) bit + uint8_t bSync :1; //<-- + uint8_t bWBUS16 :1; //<-- + uint8_t u2Obsolet4 :2; //<-- Obsolete + + uint8_t auVendorID[8]; //<-- T10 vendor identification + uint8_t auProductID[16]; //<-- Vendor-defined product ID + uint8_t auProductRevisionLevel[4]; //<-- Vendor-defined product revision + uint8_t auVendorSpecific[20]; //<-- Vendor-specific data + uint8_t u8Unused3; //<-- Unused features + uint8_t u8Reserved3; //<-- Reserved bits + uint16_t au16VersionDescriptors[8]; //<-- Standards the device complies to + uint8_t pu8Reserved4[22]; //<-- Reserved bytes +} __attribute__ ((packed)) stc_scsi_inquiry_data_t; + +/************************************************************************** + ** \brief Command Read10 + ** + **************************************************************************/ +typedef struct stc_scsi_read10 +{ + uint8_t u8OperationCode; //<-- must be 0x28 + uint8_t bObsolete1 :1; //<-- Obsolete + uint8_t bFUA_NV :1; //<-- Cache control bit + uint8_t bReserved1 :1; //<-- Reserved + uint8_t bFUA :1; //<-- Cache control bit + uint8_t bDPO :1; //<-- Cache control bit + uint8_t u3RdProtect :3; //<-- RDPROTECT field + union + { + uint8_t au8LogicalBlockAddress[4]; //<-- Index of first block to read + uint32_t u32LogicalBlockAddress; //<-- Index of first block to read + } __attribute__ ((packed)); + uint8_t u5GroupNumber :5; //<-- Information grouping + uint8_t u3Reserved2 :3; //<-- Reserved bits + union + { + uint8_t au8TransferLength[2]; //<-- Number of blocks to transmit + uint16_t u16TransferLength; //<-- Number of blocks to transmit + } __attribute__ ((packed)); + uint8_t u8Control; //<-- 0x00 + +} __attribute__ ((packed)) stc_scsi_read10_t; + +/************************************************************************** + ** \brief Command Read12 + ** + **************************************************************************/ +typedef struct stc_scsi_read12 +{ + uint8_t u8OperationCode; //<-- must be 0xa8 + uint8_t bObsolete1 :1; //<-- Obsolete + uint8_t bFUA_NV :1; //<-- Cache control bit + uint8_t bReserved1 :1; //<-- Reserved + uint8_t bFUA :1; //<-- Cache control bit + uint8_t bDPO :1; //<-- Cache control bit + uint8_t u3RdProtect :3; //<-- RDPROTECT field + union + { + uint8_t au8LogicalBlockAddress[4]; //<-- Index of first block to read + uint32_t u32LogicalBlockAddress; //<-- Index of first block to read + } __attribute__ ((packed)); + union + { + uint8_t au8TransferLength[4]; //<-- Number of blocks to transmit + uint32_t u32TransferLength; //<-- Number of blocks to transmit + } __attribute__ ((packed)); + uint8_t u5GroupNumber :5; //<-- Information grouping + uint8_t u2Reserved2 :2; //<-- Reserved bits + uint8_t bMMC4 :1; //<-- MMC4 + uint8_t u8Control; //<-- 0x00 +} __attribute__ ((packed)) stc_scsi_read12_t; + +/************************************************************************** + ** \brief Command Read Capaxity10 + ** + **************************************************************************/ +typedef struct stc_scsi_read_capacity10 +{ + uint8_t u8OperationCode; //<-- must be 0x25 + uint8_t bObsolete1 :1; //<-- Obsolete + uint8_t u7Reserved1 :7; //<-- Reserved + union + { + uint8_t au8LogicalBlockAddress[4]; //<-- Block to evaluate if PMI is set + uint32_t u32LogicalBlockAddress; //<-- Block to evaluate if PMI is set + } __attribute__ ((packed)); + uint8_t au8Reserved2[2]; //<-- Reserved bytes + uint8_t bPMI :1; //<-- Partial medium indicator bit + uint8_t u7Reserved3 :7; //<-- Reserved bits + uint8_t u8Control; //<-- 0x00 +} __attribute__ ((packed)) stc_scsi_read_capacity10_t; + +/************************************************************************** + ** \brief Command Read Capacity10 Response Data + ** + **************************************************************************/ +typedef struct stc_scsi_read_capacity10_data +{ + union + { + uint8_t au8LogicalBlockAddress[4];//<-- Address of last logical block + uint32_t u32LogicalBlockAddress; //<-- Address of last logical block + } __attribute__ ((packed)); + union + { + uint8_t au8LogicalBlockLength[4]; //<-- Length of last logical block + uint32_t u32LogicalBlockLength; //<-- Length of last logical block + } __attribute__ ((packed)); +} __attribute__ ((packed)) stc_scsi_read_capacity10_data_t; + +/************************************************************************** + ** \brief Command Request Sense + ** + **************************************************************************/ +typedef struct stc_scsi_request_sense +{ + uint8_t u8OperationCode; //<-- must be 0x03 + uint8_t bDesc :1; //<-- Type of information expected + uint8_t u7Reserved1 :7; //<-- Reserved bits + uint8_t au8Reserved2[2]; //<-- Reserved bytes + uint8_t u8AllocationLength; //<-- Size of host buffer + uint8_t u8Control; //<-- x00 +} __attribute__ ((packed)) stc_scsi_request_sense_t; + +/************************************************************************** + ** \brief Command Request Sense Response Data + ** + **************************************************************************/ +typedef struct stc_scsi_request_sense_data +{ + uint8_t u7ResponseCode :7; //<-- Sense data format + uint8_t bValid :1; //<-- Information field is standard + uint8_t u8Obsolete1; //<-- Obsolete + uint8_t u4SenseKey :4; //<-- Generic error information + uint8_t bReserved1 :1; //<-- Reserved bit + uint8_t bILI :1; //<-- SSC + uint8_t bEOM :1; //<-- SSC + uint8_t bFilemark :1; //<-- SSC + union + { + uint8_t au8Information[4]; //<-- Command-specific + uint32_t u32Information; //<-- Command-specific + } __attribute__ ((packed)); + uint8_t u8AdditionalSenseLength; //<-- sizeof(stc_scsi_request_sense_data_t)-8 + union + { + uint8_t au8CommandSpecificInformation[4]; //<-- Command-specific + uint32_t u32CommandSpecificInformation; //<-- Command-specific + } __attribute__ ((packed)); + uint8_t u8AdditionalSenseCode; //<-- Additional error information + uint8_t u8AdditionalSenseCodeQualifier; //<-- Further error information + uint8_t u8FieldReplaceableUnitCode; //<-- Specific component code + uint8_t u7SenseKeySpecific :7; //<-- Additional exception info + uint8_t bSKSV :1; //<-- Is sense key specific valid? + uint8_t au8SenseKeySpecific[2]; //<-- Additional exception info +} __attribute__ ((packed)) stc_scsi_request_sense_data_t; + +/************************************************************************** + ** \brief CommandTest Unit Ready + ** + **************************************************************************/ +typedef struct stc_scsi_test_unit_ready +{ + uint8_t bOperationCode; //<-- must be 0x00 + uint8_t au8Reserved1[4]; //<-- Reserved + uint8_t u8Control; //<-- 0x00 +} __attribute__ ((packed)) stc_scsi_test_unit_ready_t; + +/************************************************************************** + ** \brief Command Write10 + ** + **************************************************************************/ +typedef struct stc_scsi_write10 +{ + uint8_t u8OperationCode; //<-- must be 0x2A + uint8_t bObsolete1 :1; //<-- Obsolete bit + uint8_t bFUA_NV :1; //<-- Cache control bit + uint8_t bReserved1 :1; //<-- Reserved bit + uint8_t bFUA :1; //<-- Cache control bit + uint8_t bDPO :1; //<-- Cache control bit + uint8_t u3WrProtect :3; //<-- Protection information to send + union + { + uint8_t au8LogicalBlockAddress[4]; //<-- First block to write + uint32_t u32LogicalBlockAddress; //<-- First block to write + }; + uint8_t u5GroupNumber :5; //<-- Information grouping + uint8_t u3Reserved2 :3; //<-- Reserved bits + union + { + uint8_t au8TransferLength[2]; //<-- Number of blocks to write + uint16_t u16TransferLength; + }; + uint8_t u8Control; //<-- 0x00 +} stc_scsi_write10_t; + +/************************************************************************** + ** \brief Command Medium Removal + ** + **************************************************************************/ +typedef struct stc_scsi_medium_removal +{ + uint8_t u32OperationCode; //<-- must be 0x1E + uint8_t au8Reserved1[3]; //<-- must be Reserved bytes + uint8_t u2Prevent :2; //<-- must be Accept/prohibit removal + uint8_t u6Reserved2 :6; //<-- must be Reserved bits + uint8_t u8Control; //<-- must be 0x00 +} __attribute__ ((packed)) stc_scsi_medium_removal_t; + +/************************************************************************** + ** \brief Command Mode Sense6 + ** + **************************************************************************/ +typedef struct stc_scsi_mode_sense6 +{ + uint8_t bOperationCode; //<-- must be 0x1A + uint8_t bReserved1 :3; //<-- Reserved + uint8_t bDBD :1; //<-- Disable block descriptors bit + uint8_t u4Reserved2 :4; //<-- Reserved + uint8_t u6PageCode :6; //<-- Mode page to return + uint8_t u2PC :2; //<-- Type of parameter values to return + uint8_t u8SubpageCode; //<-- Mode subpage to return + uint8_t u8AllocationLength; //<-- Host buffer allocated size + uint8_t u8Control; //<-- 0x00 +} __attribute__ ((packed)) stc_scsi_mode_sense6_t; + +/************************************************************************** + ** \brief Command Mode Sense6 Response Data Header + ** + **************************************************************************/ +typedef struct stc_scsi_mode_parameter_header6 +{ + uint8_t u8ModeDataLength; //<-- Length of mode data to follow + uint8_t u8MediumType; //<-- Type of medium (SCSI_MSD_MEDIUM_TYPE_DIRECT_ACCESS_BLOCK_DEVICE) + uint8_t u4Reserved1 :4; //<-- Reserved bits + uint8_t bDPOFUA :1; //<-- DPO/FUA bits supported ? + uint8_t u2Reserved2 :2; //<-- Reserved + uint8_t bWP :1; //<-- Is medium write-protected ? + uint8_t u8BlockDescriptorLength; //<-- Length of all block descriptors +} __attribute__ ((packed)) stc_scsi_mode_parameter_header6_t; + +/************************************************************************** + ** \brief Command Response Data + ** + **************************************************************************/ +typedef union +{ + uint8_t u8OperationCode; + stc_scsi_inquiry_t stcInquiry; + stc_scsi_read10_t stcRead10; + stc_scsi_read_capacity10_t stcReadCapacity10; + stc_scsi_request_sense_t stcRequestSense; + stc_scsi_test_unit_ready_t stcTestUnitReady; + stc_scsi_write10_t stcWrite10; + stc_scsi_medium_removal_t stcMediumRemoval; + stc_scsi_mode_sense6_t stcModeSense6; +} stc_scsi_command_t; + +#endif /* __SCSI_MSD__ */ + +#ifndef __MSD_LUN__ +#define __MSD_LUN__ +/* - 2014-08-11 V10 MSc First Version */ +#define MSD_LUN_VERSION 0100 + + +#define MSD_LUN_DISK_STATUS_SUCCESS 0x00 +#define MSD_LUN_DISK_STATUS_ERROR 0x01 +#define MSD_LUN_DISK_STATUS_BUSY 0x02 + +#define MSD_LUN_DISK_STATE_READY 0x00 +#define MSD_LUN_DISK_STATE_BUSY 0x01 + +/************************************************************************** + ** \brief LUN Disk Status + ** + **************************************************************************/ +typedef enum en_msd_lun_disk_status +{ + enMsdLunDiskStatusSuccess = MSD_LUN_DISK_STATUS_SUCCESS, + enMsdLunDiskStatusError = MSD_LUN_DISK_STATUS_ERROR, + enMsdLunDiskStatusBusy = MSD_LUN_DISK_STATUS_BUSY, +} en_msd_lun_disk_status_t; + +/************************************************************************** + ** \brief LUN Disk State + ** + **************************************************************************/ +typedef enum en_msd_lun_disk_state +{ + enMsdLunDiskStateReady = MSD_LUN_DISK_STATE_READY, + enMsdLunDiskStateBusy = MSD_LUN_DISK_STATE_BUSY, +} en_msd_lun_disk_state_t; + +typedef struct stc_msd_lun_disk stc_msd_lun_disk_t; +typedef struct stc_msd_lun_command_status stc_msd_lun_command_status_t; +typedef struct stc_msd_lun stc_msd_lun_t; + +typedef en_result_t (*pfn_msd_lun_disk_callback_t)(stc_msd_lun_t* pstcLun); +typedef uint8_t (*pfn_msd_lun_disk_write_t)(stc_msd_lun_disk_t* pstcDisk, uint32_t u32Address, void* pData, uint32_t u32Length, pfn_msd_lun_disk_callback_t pfnCallback, void* pArgument); +typedef uint8_t (*pfn_msd_lun_disk_read_t)(stc_msd_lun_disk_t* pstcDisk, uint32_t u32Address, void* pData, uint32_t u32Length, pfn_msd_lun_disk_callback_t pfnCallback, void* pArgument); +typedef en_result_t (*pfn_msd_lun_read_t)(stc_msd_lun_t* pstcLun, uint32_t u32BlockAddress, uint8_t* pu8Data, uint32_t u32Length); +typedef en_result_t (*pfn_msd_lun_write_t)(stc_msd_lun_t* pstcLun, uint32_t u32BlockAddress, uint8_t* pu8Data, uint32_t u32Length); + +typedef struct stc_msd_lun_transfer +{ + void* pData; + uint32_t u32Address; + uint32_t u32Length; + pfn_msd_lun_disk_callback_t pfnCallback; + void* pArgument; +} stc_msd_lun_transfer_t; + +struct stc_msd_lun_command_status +{ + stc_msd_lun_transfer_t stcCurrentTransfer; + stc_msd_csw_t stcCsw; + stc_msd_cbw_t stcCbw; + uint8_t* pu8Data; + uint32_t u32Remaining; + uint32_t u32Size; + en_scsi_command_state_t enStatus; +}; + +struct stc_msd_lun_disk +{ + pfn_msd_lun_disk_read_t pfnRead; + pfn_msd_lun_disk_write_t pfnWrite; + uint32_t u32BaseAddress; + uint32_t u32Size; + stc_msd_lun_transfer_t* pstcCurrentTransfer; + void* pInterface; + en_msd_lun_disk_state_t enState; +}; // stc_msd_lun_disk_t; + +typedef struct stc_msd_lun_cache +{ + uint8_t* pu8Buffer; + uint32_t u32CacheSize; +} stc_msd_lun_cache_t; + +struct stc_msd_lun +{ + stc_scsi_inquiry_data_t* pstcInquiryData; + stc_scsi_request_sense_data_t stcRequestSenseData; + stc_scsi_read_capacity10_data_t stcReadCapacityData; + stc_msd_lun_cache_t* pstcCache; + uint32_t u32BaseAddress; + uint32_t u32Size; + uint32_t u32BlockSize; + stc_msd_lun_disk_t* pstcDisk; +}; + +typedef struct stc_msd_lun_list_item stc_msd_lun_list_item_t; + +struct stc_msd_lun_list_item +{ + stc_msd_lun_t* pstcLun; + uint8_t u8Id; + stc_msd_lun_list_item_t* pstcPrev; + stc_msd_lun_list_item_t* pstcNext; +}; + +typedef struct stc_msd_lun_list +{ + stc_msd_lun_list_item_t* pstcRoot; + uint8_t u8Count; +} stc_msd_lun_list_t; + +#endif /* __MSD_LUN__ */ + + +#if defined(__ICCARM__) // IAR +#pragma pack() +#elif defined(__CC_ARM) // ARM MDK / Keil �Vision + //#pragma pack(0) +#elif defined(__GNUC__) // GNU Compiler + /* nothing needed */ +#endif + +#ifndef __STC_LINKED_LIST_ITEM_T__ +#define __STC_LINKED_LIST_ITEM_T__ +struct stc_linked_list_item; + +typedef struct stc_linked_list_item +{ + uint32_t u32Id; + struct stc_linked_list_item* pstcPrev; + struct stc_linked_list_item* pstcNext; + void* pHandle; +} stc_linked_list_item_t; + +#endif + +#ifndef COPY_STRUCT +#define COPY_STRUCT(dest,src) memcpy(&(dest),&(src),sizeof(src)) +#endif + +#ifndef AU8TOU16 +#define AU8TOU16(bytes) ((uint16_t) ((bytes[0] << 8) | bytes[1])) +#endif + +#ifndef AU8TOU32 +#define AU8TOU32(bytes) ((uint32_t) ((bytes[0] << 24) | (bytes[1] << 16) | (bytes[2] << 8) | bytes[3])) +#endif + +#ifndef U32TOAU8 +#define U32TOAU8(ui,bytes) \ + bytes[0] = (uint8_t) (((ui) >> 24) & 0xFF); \ + bytes[1] = (uint8_t) (((ui) >> 16) & 0xFF); \ + bytes[2] = (uint8_t) (((ui) >> 8) & 0xFF); \ + bytes[3] = (uint8_t) ((ui) & 0xFF); +#endif + +#ifndef U16TOAU8 +#define U16TOAU8(ui,bytes) \ + bytes[0] = (uint8_t) (((ui) >> 8) & 0xFF); \ + bytes[1] = (uint8_t) ((ui) & 0xFF); +#endif + + +#ifndef SPANSION_TRACE + #if defined(NO_TRACE) + #define SPANSION_TRACE(level,...) + #else + #include "uart.h" + #ifndef SPANSION_TRACE_LEVEL + #define SPANSION_TRACE_LEVEL 0 + #endif + #define SPANSION_TRACE(level,...) \ + { \ + if (level >= SPANSION_TRACE_LEVEL) \ + { \ + char_t tracebuffer[100+1]; \ + tracebuffer[100] = '\0'; \ + snprintf(tracebuffer, 100, __VA_ARGS__); \ + puts(tracebuffer); \ + } \ + } + #endif +#endif + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +#define BUFFER_SIZE_ENDPOINTOUT 64 + + + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ +typedef enum en_usb_device_massstorage_direction +{ + enUsbDeviceMassStorageNoTransfer = 0, + enUsbDeviceMassStorageDeviceToHost = 1, + enUsbDeviceMassStorageHostToDevice = 2, +} en_usb_device_massstorage_direction_t; + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +en_result_t UsbDeviceMassStorage_SetLunReadWrite(pfn_msd_lun_read_t pfnRead, pfn_msd_lun_write_t pfnWrite); +stc_msd_lun_t* UsbDeviceMassStorage_GetLun(uint8_t u8Id); +en_result_t UsbDeviceMassStorage_AddLun(stc_msd_lun_list_item_t* pstcLunItem, stc_msd_lun_disk_t* pstcDisk, stc_msd_lun_cache_t* pstcCache, uint32_t u32BaseAddress, uint32_t u32Size, uint32_t u32BlockSize); +void UsbDeviceMassStorage_Init(stc_usbn_t* pstcUsb); +#ifdef __cplusplus +} +#endif + +//@} // UsbDeviceMassStorageGroup + +#else +#define UsbDeviceMassStorage_Init(x) ; +#endif /* ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEMASSSTORAGE_ENABLED == ON)) */ +#endif /* __USBDEVICEMASSSTORAGE_H__ */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.c new file mode 100644 index 0000000000..dc5fe00c16 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.c @@ -0,0 +1,300 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDevicePrinter.c + ** + ** CONST USB_ASSISTANT_OFF + ** + ** A detailed description is available at + ** @link UsbDevicePrinterGroup USB Device Printer Module description @endlink + ** + ** History: + ** - 2013-08-12 1.0 MSc First version + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + +#include "UsbDevicePrinter.h" + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEPRINTER_ENABLED == ON)) + + +/*****************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/*****************************************************************************/ + +/*****************************************************************************/ +/* Local type definitions ('typedef') */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Local variable definitions ('static') */ +/*****************************************************************************/ + +static uint8_t DataReceivedFlags = 0; //Status for received data +static uint8_t DataSentFlags = 0; //Status for sent data + + +static uint32_t u32LastReceivedSize; // last received size +static stc_usbn_endpoint_buffer_t stcEndpointBufferOUT; //struct for custom buffer +static uint8_t pu8IngoingBuffer[BUFFER_SIZE_ENDPOINTOUT]; // custom buffer +static stc_usbn_endpoint_data_t* pstcEndpointOUT; + +static stc_usbn_endpoint_buffer_t stcEndpointBufferIN; +stc_usbn_endpoint_buffer_t stcEpBufferIN; //struct for custom buffer +static stc_usbn_endpoint_data_t* pstcEndpointIN; +static stc_usbn_t* pstcUsbHandle = NULL; + +static usbdeviceprinter_datareceived_func_ptr_t pstnReceivedData; +static usbdeviceprinter_datasent_func_ptr_t pstnSentData; + + +/*****************************************************************************/ +/* Local function prototypes ('static') */ +/*****************************************************************************/ + +static void ClassSetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup); + +static void UsbDevicePrinter_RxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); + +static void UsbDevicePrinter_TxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint); + + +/*****************************************************************************/ +/* Function implementation - global ('extern') and local ('static') */ +/*****************************************************************************/ + +/** + ****************************************************************************** + ** Is called to initialize this class (usally in UsbConfig.c) + ** + ** \param pstcUsb USB Handle + + *****************************************************************************/ +void UsbDevicePrinter_Init(stc_usbn_t* pstcUsb) +{ + stc_usbdevice_class_config_t stcUsbClassConfig; + stc_usbdevice_endpoint_config_t stcEndpointConfig; + uint8_t* pu8Interface = NULL; + uint8_t u8InterfaceLength = 0; + uint8_t u8i = 0; + uint8_t u8NumEndpoints = 0; + pstcUsbHandle = pstcUsb; + + stcUsbClassConfig.u8InterfaceNumber = 0xFF; + stcUsbClassConfig.u8InterfaceClass = 0x07; + stcUsbClassConfig.u8InterfaceSubClass = 0x01; + stcUsbClassConfig.u8InterfaceProtocoll = 0x02; + stcUsbClassConfig.pfnSetupRequestCallback = ClassSetupRequest; + stcUsbClassConfig.pfnConnectionCallback = NULL; + stcUsbClassConfig.pfnDisconnectionCallback = NULL; + stcUsbClassConfig.pfnConfCallback = NULL; + UsbDevice_RegisterVendorClass(pstcUsb,&stcUsbClassConfig,&pu8Interface,&u8InterfaceLength); + + for(u8i = 0;u8i < u8InterfaceLength;) + { + u8i += pu8Interface[u8i]; + if (USBDESCR_ENDPOINT == pu8Interface[u8i + 1]) + { + stcEndpointConfig.u8EndpointAddress = pu8Interface[u8i + 2]; + if (((stcEndpointConfig.u8EndpointAddress) & 0x80) == 0) + { + stcEndpointConfig.pfnRxTxCallback = UsbDevicePrinter_RxCallback; + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferOUT; + pstcEndpointOUT = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8IngoingBuffer, BUFFER_SIZE_ENDPOINTOUT, UsbIRQ); + } + else + { + stcEndpointConfig.pfnRxTxCallback = UsbDevicePrinter_TxCallback; + stcEndpointConfig.pstcEndpointBuffer = &stcEndpointBufferIN; + pstcEndpointIN = UsbDevice_SetupEndpoint(pstcUsb, &stcEndpointConfig); + } + u8NumEndpoints++; + } + } +} + +/** + ****************************************************************************** + ** Set received callback + ** + ** \param pstnCallback callback handle + ** + *****************************************************************************/ +void UsbDevicePrinter_SetReceivedCallback(usbdeviceprinter_datareceived_func_ptr_t pstnCallback) +{ + pstnReceivedData = pstnCallback; +} + +/** + ****************************************************************************** + ** Set sent callback + ** + ** \param pstnCallback callback handle + ** + *****************************************************************************/ +void UsbDevicePrinter_SetSentCallback(usbdeviceprinter_datasent_func_ptr_t pstnCallback) +{ + pstnSentData = pstnCallback; +} + +/** + ****************************************************************************** + ** Class Setup Request handling + ** + ** \param pstcUsb USB handle + ** + ** \param pstcSetup Received Setup + ** + *****************************************************************************/ +static void ClassSetupRequest(stc_usbn_t* pstcUsb, stc_usb_request_t* pstcSetup) +{ + +} + +/** + ****************************************************************************** + ** Is called from UsbDevice.c when a endpoint buffer was received + ** + ** \param pstcUsb USB Handle + ** \param pstcEndpoint Endpoint + + *****************************************************************************/ +static void UsbDevicePrinter_RxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + uint8_t* pu8Buffer = pstcEndpoint->pstcEndpointBuffer->pu8Buffer; + uint32_t u32DataSize = pstcEndpoint->pstcEndpointBuffer->u32DataSize; + u32LastReceivedSize = u32DataSize; + DataReceivedFlags |= (1<<2); // setting data received flag + if (pstnReceivedData != NULL) + { + pstnReceivedData(pu8Buffer,u32DataSize); + } + //Add your code here to process the received buffer + UsbDevice_ReceiveData(pstcUsb, pstcEndpointOUT, pu8IngoingBuffer, BUFFER_SIZE_ENDPOINTOUT, UsbIRQ); +} + + +/** + ****************************************************************************** + ** Is used to use received data from endpoint + ** + ** \param ppu8Buffer pointer to buffer + *****************************************************************************/ +uint32_t UsbDevicePrinter_GetReceivedData(uint8_t** ppu8Buffer) +{ + if ((DataReceivedFlags & (1<<2)) == 0) + { + return 0; // nothing to receive + } + DataReceivedFlags -= (1<<2); + *ppu8Buffer = pstcEndpointOUT->pstcEndpointBuffer->pu8Buffer; + return u32LastReceivedSize; +} + +/** + ****************************************************************************** + ** Is called from main application to send data via endpoint + ** + ** \param pstcUsb USB Handle + ** \param pu8Buffer Buffer to send + ** \param u32DataSize Buffersize + ** \param enMode polled sending, interrupt sending or DMA + ** + ** \return 1: if succesful, 0: if usb was not ready + *****************************************************************************/ +boolean_t UsbDevicePrinter_SendData(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode) +{ + if (UsbDevice_GetStatus(pstcUsb) == UsbConfigured) + { + DataSentFlags &= ~(1<<1); + + UsbDevice_SendData(pstcUsb, pstcEndpointIN, pu8Buffer, u32DataSize, enMode); + if (enMode == UsbPOLL) + { + DataSentFlags |= (1<<1); + } + return TRUE; + } + return FALSE; +} + +/** + ****************************************************************************** + ** Is called from UsbDevice.c when a endpoint buffer was sent + ** + ** \param pstcUsb USB Handle + ** \param pstcEndpoint Endpoint + *****************************************************************************/ +static void UsbDevicePrinter_TxCallback(stc_usbn_t* pstcUsb, struct stc_usbn_endpoint_data* pstcEndpoint) +{ + DataSentFlags |= (1<<1); + if (pstnSentData != NULL) + { + pstnSentData(); + } +} +/** + ****************************************************************************** + ** Is used to use get the sent status of endpoint + ** + *****************************************************************************/ +uint8_t UsbDevicePrinter_DataSent(void) +{ + if ((DataSentFlags & (1<<1)) > 0) + { + return 1; + } + else + { + return 0; + } +} + +#endif diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.h new file mode 100644 index 0000000000..551afc22dd --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/PDL/midware/usb/device/UsbDevicePrinter.h @@ -0,0 +1,138 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDevicePrinter.h + ** + ** CONST USB_ASSISTANT_OFF + ** + ** + ** A detailed description is available at + ** @link UsbDevicePrinterGroup USB Device Printer Module description @endlink + ** + ** History: + ** - 2013-08-12 1.0 MSc First version + ** - 2013-10-14 1.1 MSc PDL support added + *****************************************************************************/ + +#ifndef __USBDEVICEPRINTER_H__ +#define __USBDEVICEPRINTER_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ +#include "usb.h" + +#ifndef USBDEVICEPRINTER_ENABLED + #define USBDEVICEPRINTER_ENABLED OFF +#endif + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) && (USBDEVICEPRINTER_ENABLED == ON)) + +#include "usbdevice.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + ****************************************************************************** + ** \defgroup UsbDevicePrinterGroup USB Device Middleware: Printer Class + ** + ** Provided functions of USB Device Printer module: + ** + ** - void UsbDevicePrinter_Init() + ** - UsbDevicePrinter_GetReceivedData() + ** - UsbDevicePrinter_SendData() + ** - UsbDevicePrinter_DataSent(void) + ** - UsbDevicePrinter_SetReceivedCallback() + ** - UsbDevicePrinter_SetSentCallback() + ** + ** Used to enumerate printe class + ** + ******************************************************************************/ +//@{ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + + + +#define BUFFER_SIZE_ENDPOINTOUT 512 + + + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + + +typedef void (*usbdeviceprinter_datareceived_func_ptr_t)(uint8_t* pu8DataBuffer, uint32_t u32DataLength); +typedef void (*usbdeviceprinter_datasent_func_ptr_t)(void); + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + +void UsbDevicePrinter_Init(stc_usbn_t* pstcUsb); + + + +uint32_t UsbDevicePrinter_GetReceivedData(uint8_t** ppu8Buffer); + +boolean_t UsbDevicePrinter_SendData(stc_usbn_t* pstcUsb, uint8_t* pu8Buffer, uint32_t u32DataSize, en_usbsend_mode_t enMode); +uint8_t UsbDevicePrinter_DataSent(void); +void UsbDevicePrinter_SetReceivedCallback(usbdeviceprinter_datareceived_func_ptr_t pstnCallback); +void UsbDevicePrinter_SetSentCallback(usbdeviceprinter_datasent_func_ptr_t pstnCallback); +#ifdef __cplusplus +} +#endif + +//@} // UsbDevicePrinterGroup + +#else + #define UsbDevicePrinter_Init(x) ; +#endif + +#endif /* __USBCLASS_H__*/ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/cypress_stm32.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/cypress_stm32.h new file mode 100644 index 0000000000..ddd9c0521c --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/cypress_stm32.h @@ -0,0 +1,104 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file cypress_stm32.h + * @brief This is needed for better compatibility with STM32 or other CPUs of Cypress family. + * @author andreika + * + */ + +#ifndef CYPRESS_STM32_H_ +#define CYPRESS_STM32_H_ + +// Cypress family compatibility macros +/*#define GPIO_TypeDef GPIO_Type +#define PORT_TypeDef PORT_Type +#define UART_TypeDef LPUART_Type +#define FTM_TypeDef FTM_Type +#define COMP_TypeDef CMP_Type +*/ +#define ADC_TypeDef FM_ADC_TypeDef + +// More Cypress family compatibility macros + +#define PAL_STM32_PUPDR_PULLUP (1U << 5U) +#define PAL_STM32_PUPDR_PULLDOWN (2U << 5U) +#define PAL_STM32_OSPEED_HIGHEST 0 +#define PAL_STM32_MODE_INPUT (0U << 0U) + +#if 0 +#define PORTx_PCRn_MUX PORT_PCR_MUX +#define PORTx_PCRn_PE PORT_PCR_PE(1) +#define PORTx_PCRn_PS PORT_PCR_PS(1) + +#define FTM_SC_TOFx FTM_SC_TOF(1) +#define FTM_SC_TOIEx FTM_SC_TOIE(1) +#define FTM_CnSC_CHFx FTM_CnSC_CHF(1) +#define FTM_CnSC_CHIEx FTM_CnSC_CHIE(1) +#define FTM_CnSC_MSBx FTM_CnSC_MSB(1) +#define FTM_CnSC_ELSAx FTM_CnSC_ELSA(1) +#define FTM_CnSC_ELSBx FTM_CnSC_ELSB(1) + +#define PIT LPIT0 +#define PITChannel0_IRQn LPIT0_Ch0_IRQn +#define PITChannel1_IRQn LPIT0_Ch1_IRQn +#define PITChannel2_IRQn LPIT0_Ch2_IRQn +#define PITChannel3_IRQn LPIT0_Ch3_IRQn +#endif + +// SPI STM32 compatibility layer +#define SPI_CR1_DFF (0x1U << 11U) /*!< 0x00000800 */ +#define SPI_CR1_CPOL (0x1U << 1U) /*!< 0x00000002 */ +#define SPI_CR1_CPHA (0x1U << 0U) /*!< 0x00000001 */ +#define SPI_CR1_MSTR (0x1U << 2U) /*!< 0x00000004 */ +#define SPI_CR1_BR_Pos (3U) +#define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */ +#define SPI_CR1_BR SPI_CR1_BR_Msk /*! + * + * @addtogroup HAL + * @{ + */ + +#include +#include "hal.h" + +#include "flash/mainflash.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * @todo Use a macro to define the system clock frequency. + * + * @notapi + */ +void hal_lld_init(void) { + // Enable DMA + //dmaInit(); + MFlash_SetDualMode(FALSE/*TRUE*/); +} + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/hal_lld.h b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/hal_lld.h new file mode 100644 index 0000000000..6090c4f64d --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/hal_lld.h @@ -0,0 +1,104 @@ +/* + ChibiOS - Copyright (C) 2014-2015 Fabio Utzig + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file S6E2Cx/hal_lld.h + * @brief Cypress S6E2Cx HAL subsystem low level driver header. + * @author andreika + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H_ +#define HAL_LLD_H_ + +#include "cypress_stm32.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Defines the support for realtime counters in the HAL. + */ +#define HAL_IMPLEMENTS_COUNTERS FALSE + +/** + * @name Platform identification + * @{ + */ +#define PLATFORM_NAME "Hellen/Cypress" +/** @} */ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing a system clock frequency. + */ +typedef uint32_t halclock_t; + +/** + * @brief Type of the realtime free counter value. + */ +typedef uint32_t halrtcnt_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Returns the current value of the system free running counter. + * @note This service is implemented by returning the content of the + * DWT_CYCCNT register. + * + * @return The value of the system free running counter of + * type halrtcnt_t. + * + * @notapi + */ +#define hal_lld_get_counter_value() 0 + +/** + * @brief Realtime counter frequency. + * @note The DWT_CYCCNT register is incremented directly by the system + * clock so this function returns STM32_HCLK. + * + * @return The realtime counter frequency of type halclock_t. + * + * @notapi + */ +#define hal_lld_get_counter_frequency() 0 + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#include "nvic.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/platform.mk b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/platform.mk new file mode 100644 index 0000000000..de96d1ddc8 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/platform.mk @@ -0,0 +1,45 @@ +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +ifeq ($(PDL_DIR),) +PDL_DIR = $(CYPRESS_CONTRIB)/os/hal/ports/Cypress/PDL +endif + +USBSRC = $(PDL_DIR)/midware/usb/device/UsbDeviceCdcCom.c \ + $(PDL_DIR)/driver/usb/usb.c \ + $(PDL_DIR)/driver/usb/usbdevice.c \ + $(PDL_DIR)/driver/usb/usbethernetclock.c + +PDLSRC := $(PDL_DIR)/driver/pdl.c \ + $(PDL_DIR)/driver/interrupts_fm4_type_b.c \ + $(PDL_DIR)/driver/adc/adc.c \ + $(PDL_DIR)/driver/bt/bt.c \ + $(PDL_DIR)/driver/can/canfd.c \ + $(PDL_DIR)/driver/can/can_pre.c \ + $(PDL_DIR)/driver/exint/exint.c \ + $(PDL_DIR)/driver/flash/dualflash.c \ + $(PDL_DIR)/driver/flash/mainflash.c \ + $(PDL_DIR)/driver/mfs/mfs.c \ + $(USBSRC) + +PLATFORMSRC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ + ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/S6E2CxAH/hal_lld.c \ + ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/S6E2CxAH/system_s6e2c5.c \ + ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/PITv2/hal_st_lld.c \ + $(PDLSRC) + +PLATFORMINC_CONTRIB := ${CHIBIOS}/os/hal/ports/common/ARMCMx \ + ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD \ + ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/S6E2CxAH \ + $(PDL_DIR) + +include ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/GPIOv2/driver.mk +include ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/SPIv2/driver.mk +include ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/ADCv2/driver.mk +include ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/PITv2/driver.mk +include ${CYPRESS_CONTRIB}/os/hal/ports/Cypress/LLD/CANv2/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC_CONTRIB) +ALLINC += $(PLATFORMINC_CONTRIB) diff --git a/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/system_s6e2c5.c b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/system_s6e2c5.c new file mode 100644 index 0000000000..ff605adf9b --- /dev/null +++ b/firmware/config/boards/hellen/cypress/OS/os/hal/ports/Cypress/S6E2CxAH/system_s6e2c5.c @@ -0,0 +1,259 @@ +/******************************************************************************* +* Copyright (C) 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +* +* This software, including source code, documentation and related +* materials ( "Software" ), is owned by Cypress Semiconductor +* Corporation ( "Cypress" ) and is protected by and subject to worldwide +* patent protection (United States and foreign), United States copyright +* laws and international treaty provisions. Therefore, you may use this +* Software only as provided in the license agreement accompanying the +* software package from which you obtained this Software ( "EULA" ). +* If no EULA applies, Cypress hereby grants you a personal, nonexclusive, +* non-transferable license to copy, modify, and compile the +* Software source code solely for use in connection with Cypress's +* integrated circuit products. Any reproduction, modification, translation, +* compilation, or representation of this Software except as specified +* above is prohibited without the express written permission of Cypress. +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +* PARTICULAR PURPOSE. Cypress reserves the right to make +* changes to the Software without notice. Cypress does not assume any +* liability arising out of the application or use of the Software or any +* product or circuit described in the Software. Cypress does not +* authorize its products for use in any products where a malfunction or +* failure of the Cypress product may reasonably be expected to result in +* significant property damage, injury or death ( "High Risk Product" ). By +* including Cypress's product in a High Risk Product, the manufacturer +* of such system or application assumes all risk of such use and in doing +* so agrees to indemnify Cypress against all liability. +*/ +/** ****************************************************************************** +/ ** \file system_s6e2c5.c + ** + ** FM series system initialization functions + ** All adjustments can be done in belonging header file. + ** + ** History: + ** 16.12.2015 18:31:27 2.0 MISH Auto created by make sys_xxx.c script + ******************************************************************************/ + +#include "mcu.h" + +/** + ****************************************************************************** + ** System Clock Frequency (Core Clock) Variable according CMSIS + ******************************************************************************/ +uint32_t SystemCoreClock = __HCLK; + +/** + ****************************************************************************** + ** \brief Update the System Core Clock with current core Clock retrieved from + ** cpu registers. + ** \param none + ** \return none + ******************************************************************************/ +void SystemCoreClockUpdate (void) { + uint32_t masterClk; + uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance + + switch ((FM_CRG->SCM_CTL >> 5u) & 0x07U) { + case 0u: /* internal High-speed Cr osc. */ + masterClk = __CLKHC; + break; + + case 1u: /* external main osc. */ + masterClk = __CLKMO; + break; + + case 2u: /* PLL clock */ + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violation: + // "Unordered accesses to a volatile location" + u32RegisterRead = (__CLKMO * (((uint32_t)(FM_CRG->PLL_CTL2) & 0x3F) + 1u)); + masterClk = (u32RegisterRead / ((((uint32_t)(FM_CRG->PLL_CTL1) >> 4ul) & 0x0Fu) + 1u)); + break; + + case 4u: /* internal Low-speed CR osc. */ + masterClk = __CLKLC; + break; + + case 5u: /* external Sub osc. */ + masterClk = __CLKSO; + break; + + default: + masterClk = 0ul; + break; + } + + switch (FM_CRG->BSC_PSR & 0x07u) { + case 0u: + SystemCoreClock = masterClk; + break; + + case 1u: + SystemCoreClock = masterClk / 2u; + break; + + case 2u: + SystemCoreClock = masterClk / 3u; + break; + + case 3u: + SystemCoreClock = masterClk / 4u; + break; + + case 4u: + SystemCoreClock = masterClk / 6u; + break; + + case 5u: + SystemCoreClock = masterClk /8u; + break; + + case 6u: + SystemCoreClock = masterClk /16u; + break; + + default: + SystemCoreClock = 0ul; + break; + } + +} + +/** + ****************************************************************************** + ** \brief Setup the microcontroller system. Initialize the System and update + ** the SystemCoreClock variable. + ** + ** \param none + ** \return none + ******************************************************************************/ +void SystemInit (void) { + +#if (CLOCK_SETUP == CLOCK_SETTING_CMSIS) + static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance +#endif + +#if (HWWD_DISABLE) /* HW Watchdog Disable */ + FM_HWWDT->WDG_LCK = 0x1ACCE551u; /* HW Watchdog Unlock */ + FM_HWWDT->WDG_LCK = 0xE5331AAEu; + FM_HWWDT->WDG_CTL = 0u; /* HW Watchdog stop */ +#endif + +// FPU settings +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + +#if (TRACE_BUFFER_ENABLE == 1) + FM_FLASH_IF->FBFCR = 0x01u; /* Trace Buffer enable */ + while(0x02u != (FM_FLASH_IF->FBFCR & 0x02u)) /* Wait for trace Buffer enable */ + {} +#endif + +#if (CLOCK_SETUP == CLOCK_SETTING_CMSIS) /* Clock Setup */ + FM_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */ + FM_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */ + FM_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */ + FM_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */ + FM_CRG->SWC_PSR = SWC_PSR_Val | (1ul << 7u); /* set SW Watchdog presacaler */ + FM_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */ + FM_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */ + + if (SCM_CTL_Val & (1ul << 1u)) { /* Main clock oscillator enabled ? */ + FM_CRG->SCM_CTL |= (1ul << 1u); /* enable main oscillator */ + while (!(FM_CRG->SCM_STR & (1ul << 1u))); /* wait for Main clock oscillation stable */ + } + + if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */ + // Initialize VBAT + FM_RTC->VDET = 0x00; /* Clear the power-on signal */ + FM_RTC->VBPFR = 0x1C; /* set P46/X0A and P47/X1A pin to 32kHz oscillation pins. */ + FM_RTC->CCB = 0xCE; /* set Oscillation boost current */ + FM_RTC->CCS = 0x08; /* set Oscillation sustain current */ + + // VB_CLK is less or equal to 1MHz + FM_RTC->VB_CLKDIV = 0; /* set transfer clock division */ + FM_RTC->BOOST = 0x03; /* set Oscillation boost time */ + + // Enable SUB CLK oscilation + FM_RTC->WTOSCCNT_f.SOSCNTL = 1; /* set 32kHz oscillation clock control connection enabled */ + FM_RTC->WTOSCCNT_f.SOSCEX = 0; /* set 32kHz oscillation enabled */ + + // Transmit to VBAT domain + FM_RTC->WTCR20_f.PWRITE = 1; + + // Wait to complete transmission + while(0 != FM_RTC->WTCR10_f.TRANS) + + FM_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */ + while (!(FM_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */ + } + + FM_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */ + FM_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */ + FM_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */ + + if (SCM_CTL_Val & (1ul << 4u)) { /* PLL enabled ? */ + if(((PSW_TMR_Val & (1ul << 4u)) == 0) && ((SCM_CTL_Val & (1ul << 1u)) == 0u)){ + //Main clock is sellected as PLL input, but the oscillator is disabled. + FM_CRG->PSW_TMR_f.PINC = 1u; /* use high-speed CR as PLL source clock instead of main clock oscillator. */ + } + FM_CRG->SCM_CTL |= (1ul << 4u); /* enable PLL */ + while (!(FM_CRG->SCM_STR & (1ul << 4u))); /* wait for PLL stable */ + } + + if ((SCM_CTL_Val & 0xE0u)==0x80ul) { /* Low-speed CR oscillation selected ? */ + u32IoRegisterRead = (FM_LSCRP->LCR_PRSLD & 0x3Fu); /* Read LCR_PRSLD value */ + if(u32IoRegisterRead > 0ul) { + uint32_t i; + uint32_t u32WaitValue; + u32WaitValue = (__CLKHC/__CLKLC)*u32IoRegisterRead; /* caluculate wait value */ + FM_LSCRP->LCR_PRSLD = 0x00u; /* Set "0" to LCR_PRSLD register */ + for(i=0; iLCR_PRSLD = LCR_PRSLD_Val; /* set the division ratio of low-speed CR */ + } + + FM_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */ + + // Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2) + // violations: + // "Unordered reads and writes to or from same location" and + // "Unordered accesses to a volatile location" + do + { + u32IoRegisterRead = (FM_CRG->SCM_CTL & 0xE0u); + }while ((FM_CRG->SCM_STR & 0xE0u) != u32IoRegisterRead); + + +#elif (CLOCK_SETUP == CLOCK_SETTING_NONE) + + // user defined clock setting + +#else + #error Clock setup type unknown! +#endif + +#if (CR_TRIM_SETUP) + /* CR Trimming Data */ + if( 0x001F03FF != (FM_FLASH_IF->CRTRMM & 0x001F03FF) ) + { + /* UnLock (MCR_FTRM) */ + FM_CRTRIM->MCR_RLR = 0x1ACCE554u; + /* Set MCR_TTRM */ + FM_CRTRIM->MCR_TTRM = (FM_FLASH_IF->CRTRMM >> 16); + /* Set MCR_FTRM */ + FM_CRTRIM->MCR_FTRM = FM_FLASH_IF->CRTRMM; + /* Lock (MCR_FTRM) */ + FM_CRTRIM->MCR_RLR = 0x00000000u; + } +#endif // (CR_TRIM_SETUP) +} + + + diff --git a/firmware/config/boards/hellen/cypress/board.c b/firmware/config/boards/hellen/cypress/board.c new file mode 100644 index 0000000000..35ca3a391f --- /dev/null +++ b/firmware/config/boards/hellen/cypress/board.c @@ -0,0 +1,47 @@ +/** + * @file board.c + * @brief Board initialization file. + * @author andreika + */ + +/* This is a template for board specific configuration created by MCUXpresso IDE Project Wizard.*/ + +#include +#include "pdl_header.h" +//#include "board.h" +//#include "hal.h" + +/** + * @brief Set up and initialize all required blocks and functions related to the board hardware. + */ +void BOARD_InitDebugConsole(void) { + /* The user initialization should be placed here */ +} + +void delay(void) +{ + volatile uint32_t i = 0; + for (i = 0; i < 800000; ++i) + { + __asm("NOP"); /* delay */ + } +} + +/* Test LED blinker (Uses PD7). Should work in any conditions! */ +void __blink(int n) { +#if 1 +#endif +} + +void __early_init(void) { + SystemInit(); +} + +void __late_init(void) { + // we need static variables to be already initialized + // to configure the clock properly and save its state + //ke1xf_clock_init(KINETIS_DEFAULT_CLK); +} + +void boardInit(void) { +} diff --git a/firmware/config/boards/hellen/cypress/board.h b/firmware/config/boards/hellen/cypress/board.h new file mode 100644 index 0000000000..a1da6bda0f --- /dev/null +++ b/firmware/config/boards/hellen/cypress/board.h @@ -0,0 +1,47 @@ +/** + * @file board.h + * @brief Board initialization header file. + * @author andreika + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/** + * @brief The board name + */ +#define BOARD_NAME "Hellen/Cypress" + +/* + * Board voltages. + * Required for performance limits calculation. + */ +//#define STM32_VDD 300U + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); + void setBoardConfigurationOverrides(void); + void setPinConfigurationOverrides(void); + void setSerialConfigurationOverrides(void); + void setSdCardConfigurationOverrides(void); + void setAdcChannelOverrides(void); + +/** + * @brief Initialize board specific settings. + */ + void BOARD_InitDebugConsole(void); + + void __blink(int n); + +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ + + diff --git a/firmware/config/boards/hellen/cypress/board.mk b/firmware/config/boards/hellen/cypress/board.mk new file mode 100644 index 0000000000..20318a24a2 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/board.mk @@ -0,0 +1,27 @@ +# List of all the board related files. + +BOARD_DIR = $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD) + +# we have: +# PDL_DEVICE_TYPE=PDL_TYPE3 +# PDL_MCU_INT_TYPE=PDL_FM4_INT_TYPE_B +PDL_DIR = $(CYPRESS_CONTRIB)/os/hal/ports/Cypress/PDL + +BOARDSRC = $(BOARD_DIR)/board.c + +BOARDSRC_CPP = $(BOARD_DIR)/board_configuration.cpp + +# Required include directories +BOARDINC = $(BOARD_DIR) +BOARDINC += $(BOARD_DIR)/config/controllers/algo + +BOARDINC += $(PDL_DIR)/driver $(PDL_DIR)/driver/gpio $(PDL_DIR)/driver/usb $(PDL_DIR)/driver/mfs $(PDL_DIR)/midware/usb/device + +BOARDSRC_CPP += $(CONTROLLERS_ALGO_AUTO_GENERATED_ENUMS) + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/cypress_S6E2CxAH.ld + +PLATFORMSRC += $(PLATFORMSRC_CONTRIB) +PLATFORMINC += $(PLATFORMINC_CONTRIB) + diff --git a/firmware/config/boards/hellen/cypress/board_configuration.cpp b/firmware/config/boards/hellen/cypress/board_configuration.cpp new file mode 100644 index 0000000000..611c97c67c --- /dev/null +++ b/firmware/config/boards/hellen/cypress/board_configuration.cpp @@ -0,0 +1,161 @@ +/** + * @file boards/hellen/cypress/board_configuration.h + * + * @brief In this file we can override engine_configuration.cpp. + * + * @date Jan 27, 2020 + * @author andreika + */ + +#include "global.h" +#include "engine.h" +#include "engine_configuration.h" +#include "adc_inputs.h" +#include "engine_math.h" +#include "tps.h" +#include "trigger_input.h" + +EXTERN_ENGINE; + +void setBoardConfigurationOverrides(void) { + setOperationMode(engineConfiguration, FOUR_STROKE_CRANK_SENSOR); + + engineConfiguration->trigger.type = TT_TOOTHED_WHEEL_60_2; + engineConfiguration->useOnlyRisingEdgeForTrigger = true; + engineConfiguration->invertPrimaryTriggerSignal = true; + engineConfiguration->isFasterEngineSpinUpEnabled = true; + engineConfiguration->useNoiselessTriggerDecoder = true; + + engineConfiguration->isEngineChartEnabled = false; + + engineConfiguration->consoleLoopPeriodMs = 200; + + setAlgorithm(LM_SPEED_DENSITY PASS_CONFIG_PARAMETER_SUFFIX); + + engineConfiguration->specs.cylindersCount = 4; + engineConfiguration->specs.firingOrder = FO_1_3_4_2; + + engineConfiguration->ignitionMode = IM_WASTED_SPARK; + engineConfiguration->crankingInjectionMode = IM_SIMULTANEOUS; + engineConfiguration->injectionMode = IM_SIMULTANEOUS; + + engineConfiguration->globalTriggerAngleOffset = 114; // the end of 19th tooth? + + engineConfiguration->specs.displacement = 1.645; + engineConfiguration->injector.flow = 200; + + engineConfiguration->cranking.baseFuel = 5; // ??? + engineConfiguration->crankingChargeAngle = 70; + engineConfiguration->cranking.rpm = 600; + + engineConfiguration->rpmHardLimit = 3000; // yes, 3k. let's play it safe for now + + engineConfiguration->map.sensor.type = MT_MPX4250A; + + engineConfiguration->idleStepperReactionTime = 10; + engineConfiguration->stepperDirectionPinMode = OM_INVERTED; + engineConfiguration->idle.stepperDirectionPin = GPIO_UNASSIGNED; + engineConfiguration->idle.stepperStepPin = GPIO_UNASSIGNED; + engineConfiguration->stepperEnablePin = GPIO_UNASSIGNED; + + engineConfiguration->useLinearCltSensor = true; + // todo: + engineConfiguration->clt.config.resistance_1 = 0; + engineConfiguration->clt.config.tempC_1 = -40.0f; + engineConfiguration->clt.config.resistance_2 = 5.0f; + engineConfiguration->clt.config.tempC_2 = 120.0f, + engineConfiguration->clt.config.bias_resistor = 3300; + + //engineConfiguration->canNbcType = CAN_BUS_NBC_BMW; + engineConfiguration->canNbcType = CAN_BUS_MAZDA_RX8; + engineConfiguration->canReadEnabled = true; + engineConfiguration->canWriteEnabled = false; + + engineConfiguration->tpsMin = convertVoltageTo10bitADC(0.250); + engineConfiguration->tpsMax = convertVoltageTo10bitADC(4.538); + engineConfiguration->tpsErrorDetectionTooLow = -10; // -10% open + engineConfiguration->tpsErrorDetectionTooHigh = 110; // 110% open + + engineConfiguration->mapMinBufferLength = 4; + + engineConfiguration->communicationLedPin = GPIO_UNASSIGNED;//GPIOJ_0; + engineConfiguration->runningLedPin = GPIO_UNASSIGNED; + engineConfiguration->warningLedPin = GPIO_UNASSIGNED; + engineConfiguration->triggerErrorPin = GPIO_UNASSIGNED; + + //engineConfiguration->checkEngineLedPin = GPIO_UNASSIGNED; + //engineConfiguration->errorLedPin = GPIOJ_15; + //engineConfiguration->fatalErrorPin = GPIOJ_15; + + //!!!!!!!!! + engineConfiguration->map.sensor.hwChannel = EFI_ADC_13; + engineConfiguration->clt.adcChannel = EFI_ADC_26; + engineConfiguration->iat.adcChannel = EFI_ADC_27; + engineConfiguration->tps1_1AdcChannel = EFI_ADC_3; + engineConfiguration->afr.hwChannel = EFI_ADC_4; + engineConfiguration->vbattAdcChannel = EFI_ADC_2; + +#if 0 + engineConfiguration->tps1_1AdcChannel = EFI_ADC_NONE; + engineConfiguration->vbattAdcChannel = EFI_ADC_NONE; + engineConfiguration->clt.adcChannel = EFI_ADC_NONE; + engineConfiguration->iat.adcChannel = EFI_ADC_NONE; + engineConfiguration->afr.hwChannel = EFI_ADC_NONE; +#endif + + engineConfiguration->auxFastSensor1_adcChannel = EFI_ADC_NONE; + engineConfiguration->tps1_2AdcChannel = EFI_ADC_NONE; + engineConfiguration->tps2_2AdcChannel = EFI_ADC_NONE; + engineConfiguration->throttlePedalPositionSecondAdcChannel = EFI_ADC_NONE; + + engineConfiguration->mafAdcChannel = EFI_ADC_NONE; + engineConfiguration->hipOutputChannel = EFI_ADC_NONE; + engineConfiguration->fuelLevelSensor = EFI_ADC_NONE; + engineConfiguration->oilPressure.hwChannel = EFI_ADC_NONE; + engineConfiguration->acSwitchAdc = EFI_ADC_NONE; + + engineConfiguration->triggerInputPins[0] = GPIOB_0; + engineConfiguration->triggerInputPins[1] = GPIO_UNASSIGNED; + engineConfiguration->triggerInputPins[2] = GPIO_UNASSIGNED; + +#if 0 + + // todo: + int i; + for (i = 0; i < INJECTION_PIN_COUNT; i++) + engineConfiguration->injectionPins[i] = GPIO_UNASSIGNED; + for (i = 0; i < IGNITION_PIN_COUNT; i++) + engineConfiguration->ignitionPins[i] = GPIO_UNASSIGNED; + + engineConfiguration->adcVcc = 5.0f; + engineConfiguration->analogInputDividerCoefficient = 1; + + // we call it here because setDefaultBoardConfiguration() is not called for DEFAULT_ENGINE_TYPE=MINIMAL_PINS + setSerialConfigurationOverrides(); +#endif + + //!!!!!!!!!!!!!!!!!!! + //engineConfiguration->isFastAdcEnabled = false; +} + +void setPinConfigurationOverrides(void) { +} + +void setSerialConfigurationOverrides(void) { +#if 0 + engineConfiguration->useSerialPort = true; + engineConfiguration->binarySerialTxPin = GPIOC_7; + engineConfiguration->binarySerialRxPin = GPIOC_6; + engineConfiguration->consoleSerialTxPin = GPIOA_10; + engineConfiguration->consoleSerialRxPin = GPIOA_11; + engineConfiguration->tunerStudioSerialSpeed = SERIAL_SPEED; + engineConfiguration->uartConsoleSerialSpeed = SERIAL_SPEED; +#endif +} + +void setSdCardConfigurationOverrides(void) { +} + +void setAdcChannelOverrides(void) { + addAdcChannelForTrigger(); +} diff --git a/firmware/config/boards/hellen/cypress/chconf.h b/firmware/config/boards/hellen/cypress/chconf.h new file mode 100644 index 0000000000..309547bc28 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/chconf.h @@ -0,0 +1,830 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +// todo: access some existing configuration field +#define STM32_SYSCLK 192000000 // 192 MHz + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_5_1_ + +/* + * __process_stack_size__ and __process_stack_size__ defaults are each hard-coded as 0x400 in ChibiOS rules.mk files + * rusEfi do not override these defaults. + * + * http://www.chibios.com/forum/viewtopic.php?t=309 + * "__main_stack_size__ is the size of INTERRUPTS stack" + * "__process_stack_size__ is the stack of the C-runtime, in ChibiOS the "main" thread uses the C-runtime stack." + * + */ + +#define PORT_IDLE_THREAD_STACK_SIZE 32 + +// See global_shared.h notes about stack requirements +// see also http://www.chibios.org/dokuwiki/doku.php?id=chibios:kb:stacks +#define PORT_INT_REQUIRED_STACK 128 + +#define CHPRINTF_USE_FLOAT TRUE + +#if !defined(EFI_CLOCK_LOCKS) || defined(__DOXYGEN__) +// looks like this value could not be defined in efifeatures.h - please define either externally or just change the value here + #define EFI_CLOCK_LOCKS FALSE +#endif /* EFI_CLOCK_LOCKS */ + + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + #ifndef __ASSEMBLER__ + #if EFI_CLOCK_LOCKS + void irqEnterHook(void); + void irqExitHook(void); + #else /* EFI_CLOCK_LOCKS */ + #define irqEnterHook() {} + #define irqExitHook() {} + #endif /*EFI_CLOCK_LOCKS */ + #endif /* __ASSEMBLER__ */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#if EFI_CLOCK_LOCKS +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ +#ifndef __ASSEMBLER__ + void onLockHook(void); + void onUnlockHook(void); +#endif /* __ASSEMBLER__ */ +#ifdef __cplusplus +} +#endif /* __cplusplus */ + #define ON_LOCK_HOOK onLockHook() + #define ON_UNLOCK_HOOK onUnlockHook() +#else /* EFI_CLOCK_LOCKS */ + #define ON_LOCK_HOOK + #define ON_UNLOCK_HOOK +#endif /* EFI_CLOCK_LOCKS */ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 1000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +// rusEfi currently uses tick mode, see CH_CFG_ST_FREQUENCY +// ST requires TIM2 or another 32 bit timer and we currently use it for ICU +// but! there is no reason to use it for ICU as we've recently realized +// so todo: migrate trigger to EXTI and try tick-less mode +// see also CH_CFG_TIME_QUANTUM +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 0 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0/*2048*/ +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_QUEUES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC FALSE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY FALSE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY FALSE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS FALSE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES FALSE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES FALSE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK TRUE +#endif + +/** + * micro-optimization: use same (lower-level) api for lock/unlock regardless on context + * this saves us one branching + */ +#define USE_PORT_LOCK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS TRUE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS TRUE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#ifndef CH_DBG_ENABLE_TRACE +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK TRUE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +// see also CH_DBG_STACK_FILL_VALUE +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS TRUE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + void *activeStack; \ + int remainingStack; \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ + irqEnterHook(); \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ + irqExitHook(); \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ + chDbgPanic3(reason, __FILE__, __LINE__); \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#ifndef __ASSEMBLER__ + +#ifdef __cplusplus +extern "C" +#endif +void chDbgPanic3(const char *msg, const char * file, int line); +#endif + +/** + * declared as a macro so that this code does not use stack + * so that it would not crash the error handler in case of stack issues + */ +#if CH_DBG_SYSTEM_STATE_CHECK +#define hasFatalError() (ch.dbg.panic_msg != NULL) +#else +#define hasFatalError() (FALSE) +#endif + + +#define chDbgAssert(c, remark) do { \ + if (CH_DBG_ENABLE_ASSERTS != FALSE) { \ + if (!(c)) { \ + /*lint -restore*/ \ + chSysHalt(remark); \ + } \ + } \ +} while (false) + +#define ENABLE_PERF_TRACE FALSE +#define TRACE_BUFFER_LENGTH 1 + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/config.mk b/firmware/config/boards/hellen/cypress/config.mk new file mode 100644 index 0000000000..28aeb22cc5 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config.mk @@ -0,0 +1,17 @@ + +USE_PROCESS_STACKSIZE = 1536 +USE_EXCEPTIONS_STACKSIZE = 4096 + +CYPRESS_CONTRIB = $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD)/OS + +CPU_STARTUP_DIR = $(CYPRESS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_S6E2CxAH.mk +CPU_PLATFORM_DIR = $(CYPRESS_CONTRIB)/os/hal/ports/Cypress/S6E2CxAH/platform.mk +CPU_HWLAYER = ports/cypress + +GENERATED_ENUMS_DIR = $(BOARD_DIR)/config/controllers/algo + +EXTRA_PARAMS += -DFIRMWARE_ID=\"cypress\" +# -nodefaultlibs -lc -lgcc -ltinyc + +# used by USE_SMART_BUILD +CONFDIR = $(PROJECT_DIR)/config/boards/$(PROJECT_BOARD) diff --git a/firmware/config/boards/hellen/cypress/config/!gen_config.bat b/firmware/config/boards/hellen/cypress/config/!gen_config.bat new file mode 100644 index 0000000000..d608a21c7f --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config/!gen_config.bat @@ -0,0 +1,36 @@ +@echo off + +rem This batch files reads rusefi_config.txt and produses firmware persistent configuration headers +rem the storage section of rusefi.ini is updated as well + +cd ../../../../.. + +pwd + +java ^ + -DSystemOut.name=gen_config ^ + -cp ../java_tools/ConfigDefinition.jar;../java_tools/configuration_definition/lib/snakeyaml.jar ^ + com.rusefi.board_generator.BoardReader ^ + -board hellen/cypress ^ + -firmware_path . ^ + -out config/boards/hellen/cypress/config/tunerstudio ^ + -enumInputFile controllers/algo/rusefi_enums.h ^ + -enumInputFile config/boards/hellen/cypress/rusefi_hw_enums.h + +mkdir build_cypress + +java ^ + -DSystemOut.name=gen_config ^ + -Drusefi.generator.lazyfile.enabled=true ^ + -jar ../java_tools/ConfigDefinition.jar ^ + -definition integration/rusefi_config.txt ^ + -ts_destination tunerstudio ^ + -with_c_defines false ^ + -initialize_to_zero false ^ + -ts_output_name rusefi_cypress.ini ^ + -c_defines config/boards/hellen/cypress/config/controllers/algo/rusefi_generated.h ^ + -c_destination config/boards/hellen/cypress/config/controllers/algo/engine_configuration_generated_structures.h ^ + -prepend config/boards/hellen/cypress/config/rusefi_config_cypress.txt ^ + -prepend config/boards/hellen/cypress/config/tunerstudio/cypress_prefix.txt ^ + -skip build_cypress/config.gen + diff --git a/firmware/config/boards/hellen/cypress/config/!gen_enum_to_string.bat b/firmware/config/boards/hellen/cypress/config/!gen_enum_to_string.bat new file mode 100644 index 0000000000..6975e27026 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config/!gen_enum_to_string.bat @@ -0,0 +1,12 @@ +@echo off + +rem This batch files reads rusefi_enums.h and produses auto_generated_enums.* files + +cd ../../../../.. + +java -jar ../java_tools/enum2string.jar ^ + -inputPath . ^ + -outputPath config/boards/hellen/cypress/config/controllers/algo ^ + -enumInputFile controllers/algo/rusefi_enums.h ^ + -enumInputFile config/boards/hellen/cypress/rusefi_hw_enums.h ^ + diff --git a/firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.cpp b/firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.cpp new file mode 100644 index 0000000000..621caa4da1 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.cpp @@ -0,0 +1,1296 @@ +#include "global.h" +#include "rusefi_enums.h" +#include "rusefi_hw_enums.h" +// was generated automatically by rusEfi tool from rusefi_hw_enums.h +// was generated automatically by rusEfi tool from rusefi_enums.h +// by enum2string.jar tool +// on Sun May 10 15:34:04 EEST 2020 +// see also gen_config_and_enums.bat + + + +const char *getPidAutoTune_AutoTunerState(PidAutoTune_AutoTunerState value){ +switch(value) { +case AUTOTUNER_OFF: + return "AUTOTUNER_OFF"; +case CONVERGED: + return "CONVERGED"; +case FAILED: + return "FAILED"; +case RELAY_STEP_DOWN: + return "RELAY_STEP_DOWN"; +case RELAY_STEP_UP: + return "RELAY_STEP_UP"; +case STEADY_STATE_AFTER_STEP_UP: + return "STEADY_STATE_AFTER_STEP_UP"; +case STEADY_STATE_AT_BASELINE: + return "STEADY_STATE_AT_BASELINE"; + } + return NULL; +} +const char *getPidAutoTune_Peak(PidAutoTune_Peak value){ +switch(value) { +case MAXIMUM: + return "MAXIMUM"; +case MINIMUM: + return "MINIMUM"; +case NOT_A_PEAK: + return "NOT_A_PEAK"; + } + return NULL; +} +const char *getAdc_channel_e(adc_channel_e value){ +switch(value) { +case EFI_ADC_0: + return "EFI_ADC_0"; +case EFI_ADC_1: + return "EFI_ADC_1"; +case EFI_ADC_10: + return "EFI_ADC_10"; +case EFI_ADC_11: + return "EFI_ADC_11"; +case EFI_ADC_12: + return "EFI_ADC_12"; +case EFI_ADC_13: + return "EFI_ADC_13"; +case EFI_ADC_14: + return "EFI_ADC_14"; +case EFI_ADC_15: + return "EFI_ADC_15"; +case EFI_ADC_16: + return "EFI_ADC_16"; +case EFI_ADC_17: + return "EFI_ADC_17"; +case EFI_ADC_18: + return "EFI_ADC_18"; +case EFI_ADC_19: + return "EFI_ADC_19"; +case EFI_ADC_2: + return "EFI_ADC_2"; +case EFI_ADC_20: + return "EFI_ADC_20"; +case EFI_ADC_21: + return "EFI_ADC_21"; +case EFI_ADC_22: + return "EFI_ADC_22"; +case EFI_ADC_23: + return "EFI_ADC_23"; +case EFI_ADC_24: + return "EFI_ADC_24"; +case EFI_ADC_25: + return "EFI_ADC_25"; +case EFI_ADC_26: + return "EFI_ADC_26"; +case EFI_ADC_27: + return "EFI_ADC_27"; +case EFI_ADC_28: + return "EFI_ADC_28"; +case EFI_ADC_29: + return "EFI_ADC_29"; +case EFI_ADC_3: + return "EFI_ADC_3"; +case EFI_ADC_30: + return "EFI_ADC_30"; +case EFI_ADC_31: + return "EFI_ADC_31"; +case EFI_ADC_4: + return "EFI_ADC_4"; +case EFI_ADC_5: + return "EFI_ADC_5"; +case EFI_ADC_6: + return "EFI_ADC_6"; +case EFI_ADC_7: + return "EFI_ADC_7"; +case EFI_ADC_8: + return "EFI_ADC_8"; +case EFI_ADC_9: + return "EFI_ADC_9"; +case EFI_ADC_ERROR: + return "EFI_ADC_ERROR"; +case EFI_ADC_NONE: + return "EFI_ADC_NONE"; + } + return NULL; +} +const char *getAdc_channel_mode_e(adc_channel_mode_e value){ +switch(value) { +case ADC_FAST: + return "ADC_FAST"; +case ADC_OFF: + return "ADC_OFF"; +case ADC_SLOW: + return "ADC_SLOW"; +case Force_4_bytes_size_adc_channel_mode: + return "Force_4_bytes_size_adc_channel_mode"; + } + return NULL; +} +const char *getAir_pressure_sensor_type_e(air_pressure_sensor_type_e value){ +switch(value) { +case Force_4_bytes_size_cranking_map_type: + return "Force_4_bytes_size_cranking_map_type"; +case MT_CUSTOM: + return "MT_CUSTOM"; +case MT_DENSO183: + return "MT_DENSO183"; +case MT_DODGE_NEON_2003: + return "MT_DODGE_NEON_2003"; +case MT_GM_3_BAR: + return "MT_GM_3_BAR"; +case MT_HONDA3BAR: + return "MT_HONDA3BAR"; +case MT_MPX4100: + return "MT_MPX4100"; +case MT_MPX4250: + return "MT_MPX4250"; +case MT_MPX4250A: + return "MT_MPX4250A"; +case MT_SUBY_DENSO: + return "MT_SUBY_DENSO"; +case MT_TOYOTA_89420_02010: + return "MT_TOYOTA_89420_02010"; + } + return NULL; +} +const char *getBrain_pin_e(brain_pin_e value){ +switch(value) { +case DRV8860_PIN_1: + return "DRV8860_PIN_1"; +case DRV8860_PIN_10: + return "DRV8860_PIN_10"; +case DRV8860_PIN_11: + return "DRV8860_PIN_11"; +case DRV8860_PIN_12: + return "DRV8860_PIN_12"; +case DRV8860_PIN_13: + return "DRV8860_PIN_13"; +case DRV8860_PIN_14: + return "DRV8860_PIN_14"; +case DRV8860_PIN_15: + return "DRV8860_PIN_15"; +case DRV8860_PIN_16: + return "DRV8860_PIN_16"; +case DRV8860_PIN_2: + return "DRV8860_PIN_2"; +case DRV8860_PIN_3: + return "DRV8860_PIN_3"; +case DRV8860_PIN_4: + return "DRV8860_PIN_4"; +case DRV8860_PIN_5: + return "DRV8860_PIN_5"; +case DRV8860_PIN_6: + return "DRV8860_PIN_6"; +case DRV8860_PIN_7: + return "DRV8860_PIN_7"; +case DRV8860_PIN_8: + return "DRV8860_PIN_8"; +case DRV8860_PIN_9: + return "DRV8860_PIN_9"; +case GPIOA_0: + return "GPIOA_0"; +case GPIOA_1: + return "GPIOA_1"; +case GPIOA_10: + return "GPIOA_10"; +case GPIOA_11: + return "GPIOA_11"; +case GPIOA_12: + return "GPIOA_12"; +case GPIOA_13: + return "GPIOA_13"; +case GPIOA_14: + return "GPIOA_14"; +case GPIOA_15: + return "GPIOA_15"; +case GPIOA_2: + return "GPIOA_2"; +case GPIOA_3: + return "GPIOA_3"; +case GPIOA_4: + return "GPIOA_4"; +case GPIOA_5: + return "GPIOA_5"; +case GPIOA_6: + return "GPIOA_6"; +case GPIOA_7: + return "GPIOA_7"; +case GPIOA_8: + return "GPIOA_8"; +case GPIOA_9: + return "GPIOA_9"; +case GPIOB_0: + return "GPIOB_0"; +case GPIOB_1: + return "GPIOB_1"; +case GPIOB_10: + return "GPIOB_10"; +case GPIOB_11: + return "GPIOB_11"; +case GPIOB_12: + return "GPIOB_12"; +case GPIOB_13: + return "GPIOB_13"; +case GPIOB_14: + return "GPIOB_14"; +case GPIOB_15: + return "GPIOB_15"; +case GPIOB_2: + return "GPIOB_2"; +case GPIOB_3: + return "GPIOB_3"; +case GPIOB_4: + return "GPIOB_4"; +case GPIOB_5: + return "GPIOB_5"; +case GPIOB_6: + return "GPIOB_6"; +case GPIOB_7: + return "GPIOB_7"; +case GPIOB_8: + return "GPIOB_8"; +case GPIOB_9: + return "GPIOB_9"; +case GPIOC_0: + return "GPIOC_0"; +case GPIOC_1: + return "GPIOC_1"; +case GPIOC_10: + return "GPIOC_10"; +case GPIOC_11: + return "GPIOC_11"; +case GPIOC_12: + return "GPIOC_12"; +case GPIOC_13: + return "GPIOC_13"; +case GPIOC_14: + return "GPIOC_14"; +case GPIOC_15: + return "GPIOC_15"; +case GPIOC_2: + return "GPIOC_2"; +case GPIOC_3: + return "GPIOC_3"; +case GPIOC_4: + return "GPIOC_4"; +case GPIOC_5: + return "GPIOC_5"; +case GPIOC_6: + return "GPIOC_6"; +case GPIOC_7: + return "GPIOC_7"; +case GPIOC_8: + return "GPIOC_8"; +case GPIOC_9: + return "GPIOC_9"; +case GPIOD_0: + return "GPIOD_0"; +case GPIOD_1: + return "GPIOD_1"; +case GPIOD_10: + return "GPIOD_10"; +case GPIOD_11: + return "GPIOD_11"; +case GPIOD_12: + return "GPIOD_12"; +case GPIOD_13: + return "GPIOD_13"; +case GPIOD_14: + return "GPIOD_14"; +case GPIOD_15: + return "GPIOD_15"; +case GPIOD_2: + return "GPIOD_2"; +case GPIOD_3: + return "GPIOD_3"; +case GPIOD_4: + return "GPIOD_4"; +case GPIOD_5: + return "GPIOD_5"; +case GPIOD_6: + return "GPIOD_6"; +case GPIOD_7: + return "GPIOD_7"; +case GPIOD_8: + return "GPIOD_8"; +case GPIOD_9: + return "GPIOD_9"; +case GPIOE_0: + return "GPIOE_0"; +case GPIOE_1: + return "GPIOE_1"; +case GPIOE_10: + return "GPIOE_10"; +case GPIOE_11: + return "GPIOE_11"; +case GPIOE_12: + return "GPIOE_12"; +case GPIOE_13: + return "GPIOE_13"; +case GPIOE_14: + return "GPIOE_14"; +case GPIOE_15: + return "GPIOE_15"; +case GPIOE_2: + return "GPIOE_2"; +case GPIOE_3: + return "GPIOE_3"; +case GPIOE_4: + return "GPIOE_4"; +case GPIOE_5: + return "GPIOE_5"; +case GPIOE_6: + return "GPIOE_6"; +case GPIOE_7: + return "GPIOE_7"; +case GPIOE_8: + return "GPIOE_8"; +case GPIOE_9: + return "GPIOE_9"; +case GPIOF_0: + return "GPIOF_0"; +case GPIOF_1: + return "GPIOF_1"; +case GPIOF_10: + return "GPIOF_10"; +case GPIOF_11: + return "GPIOF_11"; +case GPIOF_12: + return "GPIOF_12"; +case GPIOF_13: + return "GPIOF_13"; +case GPIOF_14: + return "GPIOF_14"; +case GPIOF_15: + return "GPIOF_15"; +case GPIOF_2: + return "GPIOF_2"; +case GPIOF_3: + return "GPIOF_3"; +case GPIOF_4: + return "GPIOF_4"; +case GPIOF_5: + return "GPIOF_5"; +case GPIOF_6: + return "GPIOF_6"; +case GPIOF_7: + return "GPIOF_7"; +case GPIOF_8: + return "GPIOF_8"; +case GPIOF_9: + return "GPIOF_9"; +case GPIOG_0: + return "GPIOG_0"; +case GPIOG_1: + return "GPIOG_1"; +case GPIOG_10: + return "GPIOG_10"; +case GPIOG_11: + return "GPIOG_11"; +case GPIOG_12: + return "GPIOG_12"; +case GPIOG_13: + return "GPIOG_13"; +case GPIOG_14: + return "GPIOG_14"; +case GPIOG_15: + return "GPIOG_15"; +case GPIOG_2: + return "GPIOG_2"; +case GPIOG_3: + return "GPIOG_3"; +case GPIOG_4: + return "GPIOG_4"; +case GPIOG_5: + return "GPIOG_5"; +case GPIOG_6: + return "GPIOG_6"; +case GPIOG_7: + return "GPIOG_7"; +case GPIOG_8: + return "GPIOG_8"; +case GPIOG_9: + return "GPIOG_9"; +case GPIOH_0: + return "GPIOH_0"; +case GPIOH_1: + return "GPIOH_1"; +case GPIOH_10: + return "GPIOH_10"; +case GPIOH_11: + return "GPIOH_11"; +case GPIOH_12: + return "GPIOH_12"; +case GPIOH_13: + return "GPIOH_13"; +case GPIOH_14: + return "GPIOH_14"; +case GPIOH_15: + return "GPIOH_15"; +case GPIOH_2: + return "GPIOH_2"; +case GPIOH_3: + return "GPIOH_3"; +case GPIOH_4: + return "GPIOH_4"; +case GPIOH_5: + return "GPIOH_5"; +case GPIOH_6: + return "GPIOH_6"; +case GPIOH_7: + return "GPIOH_7"; +case GPIOH_8: + return "GPIOH_8"; +case GPIOH_9: + return "GPIOH_9"; +case GPIOI_0: + return "GPIOI_0"; +case GPIOI_1: + return "GPIOI_1"; +case GPIOI_10: + return "GPIOI_10"; +case GPIOI_11: + return "GPIOI_11"; +case GPIOI_12: + return "GPIOI_12"; +case GPIOI_13: + return "GPIOI_13"; +case GPIOI_14: + return "GPIOI_14"; +case GPIOI_15: + return "GPIOI_15"; +case GPIOI_2: + return "GPIOI_2"; +case GPIOI_3: + return "GPIOI_3"; +case GPIOI_4: + return "GPIOI_4"; +case GPIOI_5: + return "GPIOI_5"; +case GPIOI_6: + return "GPIOI_6"; +case GPIOI_7: + return "GPIOI_7"; +case GPIOI_8: + return "GPIOI_8"; +case GPIOI_9: + return "GPIOI_9"; +case GPIOJ_0: + return "GPIOJ_0"; +case GPIOJ_1: + return "GPIOJ_1"; +case GPIOJ_10: + return "GPIOJ_10"; +case GPIOJ_11: + return "GPIOJ_11"; +case GPIOJ_12: + return "GPIOJ_12"; +case GPIOJ_13: + return "GPIOJ_13"; +case GPIOJ_14: + return "GPIOJ_14"; +case GPIOJ_15: + return "GPIOJ_15"; +case GPIOJ_2: + return "GPIOJ_2"; +case GPIOJ_3: + return "GPIOJ_3"; +case GPIOJ_4: + return "GPIOJ_4"; +case GPIOJ_5: + return "GPIOJ_5"; +case GPIOJ_6: + return "GPIOJ_6"; +case GPIOJ_7: + return "GPIOJ_7"; +case GPIOJ_8: + return "GPIOJ_8"; +case GPIOJ_9: + return "GPIOJ_9"; +case GPIOK_0: + return "GPIOK_0"; +case GPIOK_1: + return "GPIOK_1"; +case GPIOK_10: + return "GPIOK_10"; +case GPIOK_11: + return "GPIOK_11"; +case GPIOK_12: + return "GPIOK_12"; +case GPIOK_13: + return "GPIOK_13"; +case GPIOK_14: + return "GPIOK_14"; +case GPIOK_15: + return "GPIOK_15"; +case GPIOK_2: + return "GPIOK_2"; +case GPIOK_3: + return "GPIOK_3"; +case GPIOK_4: + return "GPIOK_4"; +case GPIOK_5: + return "GPIOK_5"; +case GPIOK_6: + return "GPIOK_6"; +case GPIOK_7: + return "GPIOK_7"; +case GPIOK_8: + return "GPIOK_8"; +case GPIOK_9: + return "GPIOK_9"; +case GPIO_INVALID: + return "GPIO_INVALID"; +case GPIO_UNASSIGNED: + return "GPIO_UNASSIGNED"; + } + return NULL; +} +const char *getCan_device_mode_e(can_device_mode_e value){ +switch(value) { +case CD_OFF: + return "CD_OFF"; +case CD_USE_CAN1: + return "CD_USE_CAN1"; +case CD_USE_CAN2: + return "CD_USE_CAN2"; +case Internal_ForceMyEnumIntSize_can_device_mode: + return "Internal_ForceMyEnumIntSize_can_device_mode"; + } + return NULL; +} +const char *getCan_nbc_e(can_nbc_e value){ +switch(value) { +case CAN_BUS_MAZDA_RX8: + return "CAN_BUS_MAZDA_RX8"; +case CAN_BUS_NBC_BMW: + return "CAN_BUS_NBC_BMW"; +case CAN_BUS_NBC_FIAT: + return "CAN_BUS_NBC_FIAT"; +case CAN_BUS_NBC_VAG: + return "CAN_BUS_NBC_VAG"; +case Internal_ForceMyEnumIntSize_can_nbc: + return "Internal_ForceMyEnumIntSize_can_nbc"; + } + return NULL; +} +const char *getChamber_style_e(chamber_style_e value){ +switch(value) { +case CS_CLOSED: + return "CS_CLOSED"; +case CS_OPEN: + return "CS_OPEN"; +case CS_SWIRL_TUMBLE: + return "CS_SWIRL_TUMBLE"; +case Internal_ForceMyEnumIntSize_chamber_stype: + return "Internal_ForceMyEnumIntSize_chamber_stype"; + } + return NULL; +} +const char *getCranking_ignition_mode_e(cranking_ignition_mode_e value){ +switch(value) { +case CIM_DEFAULT: + return "CIM_DEFAULT"; +case CIM_FIXED_ANGLE: + return "CIM_FIXED_ANGLE"; +case Force_4_bytes_size_cranking_ignition_mode: + return "Force_4_bytes_size_cranking_ignition_mode"; + } + return NULL; +} +const char *getDebug_mode_e(debug_mode_e value){ +switch(value) { +case DBG_2: + return "DBG_2"; +case DBG_36: + return "DBG_36"; +case DBG_37: + return "DBG_37"; +case DBG_ALTERNATOR_PID: + return "DBG_ALTERNATOR_PID"; +case DBG_ANALOG_INPUTS: + return "DBG_ANALOG_INPUTS"; +case DBG_ANALOG_INPUTS2: + return "DBG_ANALOG_INPUTS2"; +case DBG_AUX_PID_1: + return "DBG_AUX_PID_1"; +case DBG_AUX_TEMPERATURE: + return "DBG_AUX_TEMPERATURE"; +case DBG_AUX_VALVES: + return "DBG_AUX_VALVES"; +case DBG_BENCH_TEST: + return "DBG_BENCH_TEST"; +case DBG_CAN: + return "DBG_CAN"; +case DBG_CJ125: + return "DBG_CJ125"; +case DBG_CRANKING_DETAILS: + return "DBG_CRANKING_DETAILS"; +case DBG_DWELL_METRIC: + return "DBG_DWELL_METRIC"; +case DBG_ELECTRONIC_THROTTLE_EXTRA: + return "DBG_ELECTRONIC_THROTTLE_EXTRA"; +case DBG_ELECTRONIC_THROTTLE_PID: + return "DBG_ELECTRONIC_THROTTLE_PID"; +case DBG_EL_ACCEL: + return "DBG_EL_ACCEL"; +case DBG_ETB_LOGIC: + return "DBG_ETB_LOGIC"; +case DBG_EXECUTOR: + return "DBG_EXECUTOR"; +case DBG_FSIO_ADC: + return "DBG_FSIO_ADC"; +case DBG_FSIO_EXPRESSION: + return "DBG_FSIO_EXPRESSION"; +case DBG_FUEL_PID_CORRECTION: + return "DBG_FUEL_PID_CORRECTION"; +case DBG_IDLE_CONTROL: + return "DBG_IDLE_CONTROL"; +case DBG_IGNITION_TIMING: + return "DBG_IGNITION_TIMING"; +case DBG_INSTANT_RPM: + return "DBG_INSTANT_RPM"; +case DBG_ION: + return "DBG_ION"; +case DBG_KNOCK: + return "DBG_KNOCK"; +case DBG_MAP: + return "DBG_MAP"; +case DBG_METRICS: + return "DBG_METRICS"; +case DBG_SD_CARD: + return "DBG_SD_CARD"; +case DBG_SR5_PROTOCOL: + return "DBG_SR5_PROTOCOL"; +case DBG_STATUS: + return "DBG_STATUS"; +case DBG_TLE8888: + return "DBG_TLE8888"; +case DBG_TPS_ACCEL: + return "DBG_TPS_ACCEL"; +case DBG_TRIGGER_COUNTERS: + return "DBG_TRIGGER_COUNTERS"; +case DBG_TRIGGER_SYNC: + return "DBG_TRIGGER_SYNC"; +case DBG_VEHICLE_SPEED_SENSOR: + return "DBG_VEHICLE_SPEED_SENSOR"; +case DBG_VVT: + return "DBG_VVT"; +case Force_4_bytes_size_debug_mode_e: + return "Force_4_bytes_size_debug_mode_e"; + } + return NULL; +} +const char *getDisplay_mode_e(display_mode_e value){ +switch(value) { +case DM_HD44780: + return "DM_HD44780"; +case DM_HD44780_OVER_PCF8574: + return "DM_HD44780_OVER_PCF8574"; +case DM_NONE: + return "DM_NONE"; +case Force_4_bytes_size_display_mode: + return "Force_4_bytes_size_display_mode"; + } + return NULL; +} +const char *getEgo_sensor_e(ego_sensor_e value){ +switch(value) { +case ES_14Point7_Free: + return "ES_14Point7_Free"; +case ES_AEM: + return "ES_AEM"; +case ES_BPSX_D1: + return "ES_BPSX_D1"; +case ES_Custom: + return "ES_Custom"; +case ES_Innovate_MTX_L: + return "ES_Innovate_MTX_L"; +case ES_NarrowBand: + return "ES_NarrowBand"; +case ES_PLX: + return "ES_PLX"; +case Force_4_bytes_size_ego_sensor: + return "Force_4_bytes_size_ego_sensor"; + } + return NULL; +} +const char *getEngine_load_mode_e(engine_load_mode_e value){ +switch(value) { +case Force_4_bytes_size_engine_load_mode: + return "Force_4_bytes_size_engine_load_mode"; +case LM_ALPHA_N: + return "LM_ALPHA_N"; +case LM_MAP: + return "LM_MAP"; +case LM_PLAIN_MAF: + return "LM_PLAIN_MAF"; +case LM_REAL_MAF: + return "LM_REAL_MAF"; +case LM_SPEED_DENSITY: + return "LM_SPEED_DENSITY"; + } + return NULL; +} +const char *getEngine_type_e(engine_type_e value){ +switch(value) { +case AUDI_AAN: + return "AUDI_AAN"; +case BMW_E34: + return "BMW_E34"; +case BMW_M73_F: + return "BMW_M73_F"; +case BMW_M73_M: + return "BMW_M73_M"; +case CAMARO_4: + return "CAMARO_4"; +case CHEVY_C20_1973: + return "CHEVY_C20_1973"; +case CITROEN_TU3JP: + return "CITROEN_TU3JP"; +case DAIHATSU: + return "DAIHATSU"; +case DEFAULT_FRANKENSO: + return "DEFAULT_FRANKENSO"; +case DODGE_NEON_1995: + return "DODGE_NEON_1995"; +case DODGE_NEON_2003_CAM: + return "DODGE_NEON_2003_CAM"; +case DODGE_NEON_2003_CRANK: + return "DODGE_NEON_2003_CRANK"; +case DODGE_RAM: + return "DODGE_RAM"; +case DODGE_STRATUS: + return "DODGE_STRATUS"; +case ETB_BENCH_ENGINE: + return "ETB_BENCH_ENGINE"; +case FORD_ASPIRE_1996: + return "FORD_ASPIRE_1996"; +case FORD_ESCORT_GT: + return "FORD_ESCORT_GT"; +case FORD_FIESTA: + return "FORD_FIESTA"; +case FORD_INLINE_6_1995: + return "FORD_INLINE_6_1995"; +case FRANKENSO_QA_ENGINE: + return "FRANKENSO_QA_ENGINE"; +case Force_4_bytes_size_engine_type: + return "Force_4_bytes_size_engine_type"; +case GY6_139QMB: + return "GY6_139QMB"; +case HONDA_600: + return "HONDA_600"; +case HONDA_ACCORD_1_24_SHIFTED: + return "HONDA_ACCORD_1_24_SHIFTED"; +case HONDA_ACCORD_CD: + return "HONDA_ACCORD_CD"; +case HONDA_ACCORD_CD_DIP: + return "HONDA_ACCORD_CD_DIP"; +case HONDA_ACCORD_CD_TWO_WIRES: + return "HONDA_ACCORD_CD_TWO_WIRES"; +case ISSUE_898: + return "ISSUE_898"; +case LADA_KALINA: + return "LADA_KALINA"; +case MAZDA_626: + return "MAZDA_626"; +case MAZDA_MIATA_2003: + return "MAZDA_MIATA_2003"; +case MAZDA_MIATA_2003_BOARD_TEST: + return "MAZDA_MIATA_2003_BOARD_TEST"; +case MAZDA_MIATA_2003_NA_RAIL: + return "MAZDA_MIATA_2003_NA_RAIL"; +case MAZDA_MIATA_NA8: + return "MAZDA_MIATA_NA8"; +case MAZDA_MIATA_NB1: + return "MAZDA_MIATA_NB1"; +case MIATA_1990: + return "MIATA_1990"; +case MIATA_1994_DEVIATOR: + return "MIATA_1994_DEVIATOR"; +case MIATA_1996: + return "MIATA_1996"; +case MIATA_NA6_MAP: + return "MIATA_NA6_MAP"; +case MIATA_NA6_VAF: + return "MIATA_NA6_VAF"; +case MICRO_RUS_EFI: + return "MICRO_RUS_EFI"; +case MINIMAL_PINS: + return "MINIMAL_PINS"; +case MITSU_4G93: + return "MITSU_4G93"; +case MRE_BOARD_TEST: + return "MRE_BOARD_TEST"; +case MRE_MIATA_NA6: + return "MRE_MIATA_NA6"; +case MRE_MIATA_NB2: + return "MRE_MIATA_NB2"; +case MRE_MIATA_NB2_MTB: + return "MRE_MIATA_NB2_MTB"; +case NISSAN_PRIMERA: + return "NISSAN_PRIMERA"; +case PROMETHEUS_DEFAULTS: + return "PROMETHEUS_DEFAULTS"; +case PROTEUS: + return "PROTEUS"; +case ROVER_V8: + return "ROVER_V8"; +case SACHS: + return "SACHS"; +case SUBARUEJ20G_DEFAULTS: + return "SUBARUEJ20G_DEFAULTS"; +case SUBARU_2003_WRX: + return "SUBARU_2003_WRX"; +case SUZUKI_VITARA: + return "SUZUKI_VITARA"; +case TEST_CIVIC_4_0_BOTH: + return "TEST_CIVIC_4_0_BOTH"; +case TEST_CIVIC_4_0_RISE: + return "TEST_CIVIC_4_0_RISE"; +case TEST_ENGINE: + return "TEST_ENGINE"; +case TEST_ENGINE_VVT: + return "TEST_ENGINE_VVT"; +case TEST_ISSUE_366_BOTH: + return "TEST_ISSUE_366_BOTH"; +case TEST_ISSUE_366_RISE: + return "TEST_ISSUE_366_RISE"; +case TLE8888_BENCH_ENGINE: + return "TLE8888_BENCH_ENGINE"; +case TOYOTA_2JZ_GTE_VVTi: + return "TOYOTA_2JZ_GTE_VVTi"; +case TOYOTA_JZS147: + return "TOYOTA_JZS147"; +case VAG_18_TURBO: + return "VAG_18_TURBO"; +case VW_ABA: + return "VW_ABA"; +case VW_B6: + return "VW_B6"; +case ZIL_130: + return "ZIL_130"; + } + return NULL; +} +const char *getGear_e(gear_e value){ +switch(value) { +case GEAR_1: + return "GEAR_1"; +case GEAR_2: + return "GEAR_2"; +case GEAR_3: + return "GEAR_3"; +case GEAR_4: + return "GEAR_4"; +case NEUTRAL: + return "NEUTRAL"; + } + return NULL; +} +const char *getHip_state_e(hip_state_e value){ +switch(value) { +case IS_INTEGRATING: + return "IS_INTEGRATING"; +case IS_SENDING_SPI_COMMAND: + return "IS_SENDING_SPI_COMMAND"; +case NOT_READY: + return "NOT_READY"; +case READY_TO_INTEGRATE: + return "READY_TO_INTEGRATE"; +case WAITING_FOR_ADC_TO_SKIP: + return "WAITING_FOR_ADC_TO_SKIP"; +case WAITING_FOR_RESULT_ADC: + return "WAITING_FOR_RESULT_ADC"; + } + return NULL; +} +const char *getIdle_mode_e(idle_mode_e value){ +switch(value) { +case Force_4_bytes_size_idle_mode: + return "Force_4_bytes_size_idle_mode"; +case IM_AUTO: + return "IM_AUTO"; +case IM_MANUAL: + return "IM_MANUAL"; + } + return NULL; +} +const char *getIdle_state_e(idle_state_e value){ +switch(value) { +case ADJUSTING: + return "ADJUSTING"; +case BLIP: + return "BLIP"; +case Force_4bytes_size_idle_state_e: + return "Force_4bytes_size_idle_state_e"; +case INIT: + return "INIT"; +case PID_UPPER: + return "PID_UPPER"; +case PID_VALUE: + return "PID_VALUE"; +case PWM_PRETTY_CLOSE: + return "PWM_PRETTY_CLOSE"; +case RPM_DEAD_ZONE: + return "RPM_DEAD_ZONE"; +case TPS_THRESHOLD: + return "TPS_THRESHOLD"; + } + return NULL; +} +const char *getIgnition_mode_e(ignition_mode_e value){ +switch(value) { +case Force_4_bytes_size_ignition_mode: + return "Force_4_bytes_size_ignition_mode"; +case IM_INDIVIDUAL_COILS: + return "IM_INDIVIDUAL_COILS"; +case IM_ONE_COIL: + return "IM_ONE_COIL"; +case IM_TWO_COILS: + return "IM_TWO_COILS"; +case IM_WASTED_SPARK: + return "IM_WASTED_SPARK"; + } + return NULL; +} +const char *getInjection_mode_e(injection_mode_e value){ +switch(value) { +case Force_4_bytes_size_injection_mode: + return "Force_4_bytes_size_injection_mode"; +case IM_BATCH: + return "IM_BATCH"; +case IM_SEQUENTIAL: + return "IM_SEQUENTIAL"; +case IM_SIMULTANEOUS: + return "IM_SIMULTANEOUS"; +case IM_SINGLE_POINT: + return "IM_SINGLE_POINT"; + } + return NULL; +} +const char *getLog_format_e(log_format_e value){ +switch(value) { +case Force_4_bytes_size_log_format: + return "Force_4_bytes_size_log_format"; +case LF_NATIVE: + return "LF_NATIVE"; +case LM_MLV: + return "LM_MLV"; + } + return NULL; +} +const char *getMaf_sensor_type_e(maf_sensor_type_e value){ +switch(value) { +case Bosch0280218004: + return "Bosch0280218004"; +case Bosch0280218037: + return "Bosch0280218037"; +case CUSTOM: + return "CUSTOM"; +case DensoTODO: + return "DensoTODO"; +case Internal_ForceMyEnumIntSize_maf_sensor: + return "Internal_ForceMyEnumIntSize_maf_sensor"; + } + return NULL; +} +const char *getMass_storage_e(mass_storage_e value){ +switch(value) { +case Force_4_bytes_size_mass_storage: + return "Force_4_bytes_size_mass_storage"; +case MS_ALWAYS: + return "MS_ALWAYS"; +case MS_AUTO: + return "MS_AUTO"; +case MS_NEVER: + return "MS_NEVER"; + } + return NULL; +} +const char *getOperation_mode_e(operation_mode_e value){ +switch(value) { +case FOUR_STROKE_CAM_SENSOR: + return "FOUR_STROKE_CAM_SENSOR"; +case FOUR_STROKE_CRANK_SENSOR: + return "FOUR_STROKE_CRANK_SENSOR"; +case FOUR_STROKE_SYMMETRICAL_CRANK_SENSOR: + return "FOUR_STROKE_SYMMETRICAL_CRANK_SENSOR"; +case Force_4_bytes_size_operation_mode_e: + return "Force_4_bytes_size_operation_mode_e"; +case OM_NONE: + return "OM_NONE"; +case TWO_STROKE: + return "TWO_STROKE"; + } + return NULL; +} +const char *getPin_input_mode_e(pin_input_mode_e value){ +switch(value) { +case PI_DEFAULT: + return "PI_DEFAULT"; +case PI_PULLDOWN: + return "PI_PULLDOWN"; +case PI_PULLUP: + return "PI_PULLUP"; + } + return NULL; +} +const char *getPin_mode_e(pin_mode_e value){ +switch(value) { +case PO_DEFAULT: + return "PO_DEFAULT"; +case PO_OPENDRAIN: + return "PO_OPENDRAIN"; +case PO_PULLDOWN: + return "PO_PULLDOWN"; +case PO_PULLUP: + return "PO_PULLUP"; + } + return NULL; +} +const char *getPin_output_mode_e(pin_output_mode_e value){ +switch(value) { +case OM_DEFAULT: + return "OM_DEFAULT"; +case OM_INVERTED: + return "OM_INVERTED"; +case OM_OPENDRAIN: + return "OM_OPENDRAIN"; +case OM_OPENDRAIN_INVERTED: + return "OM_OPENDRAIN_INVERTED"; + } + return NULL; +} +const char *getSensor_chart_e(sensor_chart_e value){ +switch(value) { +case Internal_ForceMyEnumIntSize_sensor_chart: + return "Internal_ForceMyEnumIntSize_sensor_chart"; +case SC_AUX_FAST1: + return "SC_AUX_FAST1"; +case SC_DETAILED_RPM: + return "SC_DETAILED_RPM"; +case SC_MAP: + return "SC_MAP"; +case SC_OFF: + return "SC_OFF"; +case SC_RPM_ACCEL: + return "SC_RPM_ACCEL"; +case SC_TRIGGER: + return "SC_TRIGGER"; + } + return NULL; +} +const char *getSpi_device_e(spi_device_e value){ +switch(value) { +case SPI_DEVICE_1: + return "SPI_DEVICE_1"; +case SPI_DEVICE_2: + return "SPI_DEVICE_2"; +case SPI_DEVICE_3: + return "SPI_DEVICE_3"; +case SPI_DEVICE_4: + return "SPI_DEVICE_4"; +case SPI_NONE: + return "SPI_NONE"; + } + return NULL; +} +const char *getSpi_speed_e(spi_speed_e value){ +switch(value) { +case _150KHz: + return "_150KHz"; +case _1_25MHz: + return "_1_25MHz"; +case _2_5MHz: + return "_2_5MHz"; +case _5MHz: + return "_5MHz"; + } + return NULL; +} +const char *getTChargeMode_e(tChargeMode_e value){ +switch(value) { +case Force_4bytes_size_tChargeMode_e: + return "Force_4bytes_size_tChargeMode_e"; +case TCHARGE_MODE_AIR_INTERP: + return "TCHARGE_MODE_AIR_INTERP"; +case TCHARGE_MODE_RPM_TPS: + return "TCHARGE_MODE_RPM_TPS"; + } + return NULL; +} +const char *getTiming_mode_e(timing_mode_e value){ +switch(value) { +case Internal_ForceMyEnumIntSize_timing_mode: + return "Internal_ForceMyEnumIntSize_timing_mode"; +case TM_DYNAMIC: + return "TM_DYNAMIC"; +case TM_FIXED: + return "TM_FIXED"; + } + return NULL; +} +const char *getTrigger_event_e(trigger_event_e value){ +switch(value) { +case SHAFT_3RD_FALLING: + return "SHAFT_3RD_FALLING"; +case SHAFT_3RD_RISING: + return "SHAFT_3RD_RISING"; +case SHAFT_PRIMARY_FALLING: + return "SHAFT_PRIMARY_FALLING"; +case SHAFT_PRIMARY_RISING: + return "SHAFT_PRIMARY_RISING"; +case SHAFT_SECONDARY_FALLING: + return "SHAFT_SECONDARY_FALLING"; +case SHAFT_SECONDARY_RISING: + return "SHAFT_SECONDARY_RISING"; + } + return NULL; +} +const char *getTrigger_type_e(trigger_type_e value){ +switch(value) { +case Force_4_bytes_size_trigger_type: + return "Force_4_bytes_size_trigger_type"; +case TT_2JZ_1_12: + return "TT_2JZ_1_12"; +case TT_2JZ_3_34: + return "TT_2JZ_3_34"; +case TT_36_2_2_2: + return "TT_36_2_2_2"; +case TT_3_1_CAM: + return "TT_3_1_CAM"; +case TT_60_2_VW: + return "TT_60_2_VW"; +case TT_DODGE_NEON_1995: + return "TT_DODGE_NEON_1995"; +case TT_DODGE_NEON_1995_ONLY_CRANK: + return "TT_DODGE_NEON_1995_ONLY_CRANK"; +case TT_DODGE_NEON_2003_CAM: + return "TT_DODGE_NEON_2003_CAM"; +case TT_DODGE_NEON_2003_CRANK: + return "TT_DODGE_NEON_2003_CRANK"; +case TT_DODGE_RAM: + return "TT_DODGE_RAM"; +case TT_DODGE_STRATUS: + return "TT_DODGE_STRATUS"; +case TT_FIAT_IAW_P8: + return "TT_FIAT_IAW_P8"; +case TT_FORD_ASPIRE: + return "TT_FORD_ASPIRE"; +case TT_GM_7X: + return "TT_GM_7X"; +case TT_GM_LS_24: + return "TT_GM_LS_24"; +case TT_HONDA_1_24: + return "TT_HONDA_1_24"; +case TT_HONDA_1_4_24: + return "TT_HONDA_1_4_24"; +case TT_HONDA_4_24: + return "TT_HONDA_4_24"; +case TT_HONDA_4_24_1: + return "TT_HONDA_4_24_1"; +case TT_HONDA_ACCORD_1_24_SHIFTED: + return "TT_HONDA_ACCORD_1_24_SHIFTED"; +case TT_HONDA_CBR_600: + return "TT_HONDA_CBR_600"; +case TT_HONDA_CBR_600_CUSTOM: + return "TT_HONDA_CBR_600_CUSTOM"; +case TT_JEEP_18_2_2_2: + return "TT_JEEP_18_2_2_2"; +case TT_JEEP_4_CYL: + return "TT_JEEP_4_CYL"; +case TT_MAZDA_DOHC_1_4: + return "TT_MAZDA_DOHC_1_4"; +case TT_MAZDA_MIATA_NA: + return "TT_MAZDA_MIATA_NA"; +case TT_MAZDA_MIATA_NB1: + return "TT_MAZDA_MIATA_NB1"; +case TT_MAZDA_MIATA_VVT_TEST: + return "TT_MAZDA_MIATA_VVT_TEST"; +case TT_MAZDA_SOHC_4: + return "TT_MAZDA_SOHC_4"; +case TT_MAZDA_Z5: + return "TT_MAZDA_Z5"; +case TT_MIATA_VVT: + return "TT_MIATA_VVT"; +case TT_MINI_COOPER_R50: + return "TT_MINI_COOPER_R50"; +case TT_MITSUBISHI: + return "TT_MITSUBISHI"; +case TT_NISSAN_SR20VE: + return "TT_NISSAN_SR20VE"; +case TT_NISSAN_SR20VE_360: + return "TT_NISSAN_SR20VE_360"; +case TT_ONE: + return "TT_ONE"; +case TT_ONE_PLUS_ONE: + return "TT_ONE_PLUS_ONE"; +case TT_ONE_PLUS_TOOTHED_WHEEL_60_2: + return "TT_ONE_PLUS_TOOTHED_WHEEL_60_2"; +case TT_ROVER_K: + return "TT_ROVER_K"; +case TT_SUBARU_7_6: + return "TT_SUBARU_7_6"; +case TT_TOOTHED_WHEEL: + return "TT_TOOTHED_WHEEL"; +case TT_TOOTHED_WHEEL_36_1: + return "TT_TOOTHED_WHEEL_36_1"; +case TT_TOOTHED_WHEEL_60_2: + return "TT_TOOTHED_WHEEL_60_2"; +case TT_UNUSED: + return "TT_UNUSED"; + } + return NULL; +} +const char *getTrigger_value_e(trigger_value_e value){ +switch(value) { +case TV_FALL: + return "TV_FALL"; +case TV_RISE: + return "TV_RISE"; + } + return NULL; +} +const char *getTrigger_wheel_e(trigger_wheel_e value){ +switch(value) { +case T_CHANNEL_3: + return "T_CHANNEL_3"; +case T_NONE: + return "T_NONE"; +case T_PRIMARY: + return "T_PRIMARY"; +case T_SECONDARY: + return "T_SECONDARY"; + } + return NULL; +} +const char *getUart_device_e(uart_device_e value){ +switch(value) { +case UART_DEVICE_1: + return "UART_DEVICE_1"; +case UART_DEVICE_2: + return "UART_DEVICE_2"; +case UART_DEVICE_3: + return "UART_DEVICE_3"; +case UART_DEVICE_4: + return "UART_DEVICE_4"; +case UART_NONE: + return "UART_NONE"; + } + return NULL; +} +const char *getVvt_mode_e(vvt_mode_e value){ +switch(value) { +case Force_4_bytes_size_vvt_mode: + return "Force_4_bytes_size_vvt_mode"; +case MIATA_NB2: + return "MIATA_NB2"; +case VVT_2GZ: + return "VVT_2GZ"; +case VVT_FIRST_HALF: + return "VVT_FIRST_HALF"; +case VVT_SECOND_HALF: + return "VVT_SECOND_HALF"; + } + return NULL; +} diff --git a/firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.h b/firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.h new file mode 100644 index 0000000000..feba74d6c8 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config/controllers/algo/auto_generated_enums.h @@ -0,0 +1,53 @@ +// was generated automatically by rusEfi tool from rusefi_hw_enums.h +// was generated automatically by rusEfi tool from rusefi_enums.h +// by enum2string.jar tool +// on Sun May 10 15:34:04 EEST 2020 +// see also gen_config_and_enums.bat + + + +#include "rusefi_enums.h" +#include "rusefi_hw_enums.h" +#ifndef _A_H_HEADER_ +#define _A_H_HEADER_ +const char *getPidAutoTune_AutoTunerState(PidAutoTune_AutoTunerState value); +const char *getPidAutoTune_Peak(PidAutoTune_Peak value); +const char *getAdc_channel_e(adc_channel_e value); +const char *getAdc_channel_mode_e(adc_channel_mode_e value); +const char *getAir_pressure_sensor_type_e(air_pressure_sensor_type_e value); +const char *getBrain_pin_diag_e(brain_pin_diag_e value); +const char *getBrain_pin_e(brain_pin_e value); +const char *getCan_device_mode_e(can_device_mode_e value); +const char *getCan_nbc_e(can_nbc_e value); +const char *getChamber_style_e(chamber_style_e value); +const char *getCranking_ignition_mode_e(cranking_ignition_mode_e value); +const char *getDebug_mode_e(debug_mode_e value); +const char *getDisplay_mode_e(display_mode_e value); +const char *getEgo_sensor_e(ego_sensor_e value); +const char *getEngine_load_mode_e(engine_load_mode_e value); +const char *getEngine_type_e(engine_type_e value); +const char *getGear_e(gear_e value); +const char *getHip_state_e(hip_state_e value); +const char *getIdle_mode_e(idle_mode_e value); +const char *getIdle_state_e(idle_state_e value); +const char *getIgnition_mode_e(ignition_mode_e value); +const char *getInjection_mode_e(injection_mode_e value); +const char *getLog_format_e(log_format_e value); +const char *getMaf_sensor_type_e(maf_sensor_type_e value); +const char *getMass_storage_e(mass_storage_e value); +const char *getOperation_mode_e(operation_mode_e value); +const char *getPin_input_mode_e(pin_input_mode_e value); +const char *getPin_mode_e(pin_mode_e value); +const char *getPin_output_mode_e(pin_output_mode_e value); +const char *getSensor_chart_e(sensor_chart_e value); +const char *getSpi_device_e(spi_device_e value); +const char *getSpi_speed_e(spi_speed_e value); +const char *getTChargeMode_e(tChargeMode_e value); +const char *getTiming_mode_e(timing_mode_e value); +const char *getTrigger_event_e(trigger_event_e value); +const char *getTrigger_type_e(trigger_type_e value); +const char *getTrigger_value_e(trigger_value_e value); +const char *getTrigger_wheel_e(trigger_wheel_e value); +const char *getUart_device_e(uart_device_e value); +const char *getVvt_mode_e(vvt_mode_e value); +#endif /*_A_H_HEADER_ */ diff --git a/firmware/config/boards/hellen/cypress/config/controllers/algo/engine_configuration_generated_structures.h b/firmware/config/boards/hellen/cypress/config/controllers/algo/engine_configuration_generated_structures.h new file mode 100644 index 0000000000..9b7cf84a75 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config/controllers/algo/engine_configuration_generated_structures.h @@ -0,0 +1,3136 @@ +// this section was generated automatically by rusEfi tool ConfigDefinition.jar based on integration/rusefi_config.txt Sun May 10 18:01:52 EEST 2020 +// by class com.rusefi.output.CHeaderConsumer +// begin +#ifndef CONFIG_BOARDS_HELLEN_CYPRESS_CONFIG_CONTROLLERS_ALGO_ENGINE_CONFIGURATION_GENERATED_STRUCTURES_H +#define CONFIG_BOARDS_HELLEN_CYPRESS_CONFIG_CONTROLLERS_ALGO_ENGINE_CONFIGURATION_GENERATED_STRUCTURES_H +#include "rusefi_types.h" +// start of pid_s +struct pid_s { + /** + * offset 0 + */ + float pFactor; + /** + * offset 4 + */ + float iFactor; + /** + * offset 8 + */ + float dFactor; + /** + * Linear addition to PID logic + * offset 12 + */ + int16_t offset; + /** + * PID dTime + * offset 14 + */ + int16_t periodMs; + /** + * Output min value + * offset 16 + */ + int16_t minValue; + /** + * Output max value + * offset 18 + */ + int16_t maxValue; + /** total size 20*/ +}; + +typedef struct pid_s pid_s; + +// start of cranking_parameters_s +struct cranking_parameters_s { + /** + * Base duration of the fuel injection during cranking, this is modified by the multipliers for CLT, IAT, TPS ect, to give the final cranking pulse width. + * offset 0 + */ + float baseFuel; + /** + * This sets the RPM limit below which the ECU will use cranking fuel and ignition logic, typically this is around 350-450rpm. + * set cranking_rpm X + * offset 4 + */ + int16_t rpm; + /** + * need 4 byte alignment + * offset 6 + */ + uint8_t alignmentFill[2]; + /** total size 8*/ +}; + +typedef struct cranking_parameters_s cranking_parameters_s; + +// start of spi_pins +struct spi_pins { + /** + * offset 0 + */ + brain_pin_e mosiPin; + /** + * offset 1 + */ + brain_pin_e misoPin; + /** + * offset 2 + */ + brain_pin_e sckPin; + /** + * need 4 byte alignment + * offset 3 + */ + uint8_t alignmentFill; + /** total size 4*/ +}; + +typedef struct spi_pins spi_pins; + +// start of air_pressure_sensor_config_s +struct air_pressure_sensor_config_s { + /** + * kPa value at low volts + * offset 0 + */ + float lowValue; + /** + * kPa value at high volts + * offset 4 + */ + float highValue; + /** + * offset 8 + */ + air_pressure_sensor_type_e type; + /** + * offset 12 + */ + adc_channel_e hwChannel; + /** + * offset 13 + */ + uint8_t align[3]; + /** total size 16*/ +}; + +typedef struct air_pressure_sensor_config_s air_pressure_sensor_config_s; + +/** + * @brief MAP averaging configuration + +*/ +// start of MAP_sensor_config_s +struct MAP_sensor_config_s { + /** + * offset 0 + */ + float samplingAngleBins[MAP_ANGLE_SIZE]; + /** + * @brief MAP averaging sampling start angle, by RPM + * offset 32 + */ + float samplingAngle[MAP_ANGLE_SIZE]; + /** + * offset 64 + */ + float samplingWindowBins[MAP_WINDOW_SIZE]; + /** + * @brief MAP averaging angle duration, by RPM + * offset 96 + */ + float samplingWindow[MAP_WINDOW_SIZE]; + /** + * offset 128 + */ + air_pressure_sensor_config_s sensor; + /** total size 144*/ +}; + +typedef struct MAP_sensor_config_s MAP_sensor_config_s; + +/** + * @brief Thermistor known values + +*/ +// start of thermistor_conf_s +struct thermistor_conf_s { + /** + * these values are in Celcius + * offset 0 + */ + float tempC_1; + /** + * offset 4 + */ + float tempC_2; + /** + * offset 8 + */ + float tempC_3; + /** + * offset 12 + */ + float resistance_1; + /** + * offset 16 + */ + float resistance_2; + /** + * offset 20 + */ + float resistance_3; + /** + * Pull-up resistor value on your board + * offset 24 + */ + float bias_resistor; + /** total size 28*/ +}; + +typedef struct thermistor_conf_s thermistor_conf_s; + +/** + * @brief Oil pressure sensor interpolation + +*/ +// start of oil_pressure_config_s +struct oil_pressure_config_s { + /** + * offset 0 + */ + adc_channel_e hwChannel; + /** + * offset 1 + */ + uint8_t align[3]; + /** + * offset 4 + */ + float v1; + /** + * offset 8 + */ + float value1; + /** + * offset 12 + */ + float v2; + /** + * offset 16 + */ + float value2; + /** total size 20*/ +}; + +typedef struct oil_pressure_config_s oil_pressure_config_s; + +/** + * @brief Thermistor curve parameters + +*/ +// start of ThermistorConf +struct ThermistorConf { + /** + * offset 0 + */ + thermistor_conf_s config; + /** + * offset 28 + */ + adc_channel_e adcChannel; + /** + * need 4 byte alignment + * offset 29 + */ + uint8_t alignmentFill[3]; + /** total size 32*/ +}; + +typedef struct ThermistorConf ThermistorConf; + +// start of injector_s +struct injector_s { + /** + * This is your injector flow at the fuel pressure used in the vehicle. cc/min, cubic centimetre per minute + * By the way, g/s = 0.125997881 * (lb/hr) + * g/s = 0.125997881 * (cc/min)/10.5 + * g/s = 0.0119997981 * cc/min + * offset 0 + */ + float flow; + /** + * set_flat_injector_lag LAG + * set_injector_lag VOLTAGE LAG + * offset 4 + */ + float battLagCorrBins[VBAT_INJECTOR_CURVE_SIZE]; + /** + * ms delay between injector open and close dead times + * offset 36 + */ + float battLagCorr[VBAT_INJECTOR_CURVE_SIZE]; + /** total size 68*/ +}; + +typedef struct injector_s injector_s; + +// start of bi_quard_s +struct bi_quard_s { + /** + * offset 0 + */ + float a0; + /** + * offset 4 + */ + float a1; + /** + * offset 8 + */ + float a2; + /** + * offset 12 + */ + float b1; + /** + * offset 16 + */ + float b2; + /** total size 20*/ +}; + +typedef struct bi_quard_s bi_quard_s; + +// start of specs_s +struct specs_s { + /** + * Engine displacement, in litres + * see also cylindersCount + * offset 0 + */ + float displacement; + /** + * offset 4 + */ + cylinders_count_t cylindersCount; + /** + * offset 8 + */ + firing_order_e firingOrder; + /** total size 12*/ +}; + +typedef struct specs_s specs_s; + +/** + * @brief Trigger wheel(s) configuration + +*/ +// start of trigger_config_s +struct trigger_config_s { + /** + * set trigger_type X + * offset 0 + */ + trigger_type_e type; + /** + offset 4 bit 0 */ + bool unusedTriggerBit0 : 1; + /** + offset 4 bit 1 */ + bool unusedTriggerBit1 : 1; + /** + * This option could be used if your second trigger channel is broken + offset 4 bit 2 */ + bool useOnlyFirstChannel : 1; + /** + offset 4 bit 3 */ + bool unusedBit_4_3 : 1; + /** + offset 4 bit 4 */ + bool unusedBit_4_4 : 1; + /** + offset 4 bit 5 */ + bool unusedBit_4_5 : 1; + /** + offset 4 bit 6 */ + bool unusedBit_4_6 : 1; + /** + offset 4 bit 7 */ + bool unusedBit_4_7 : 1; + /** + offset 4 bit 8 */ + bool unusedBit_4_8 : 1; + /** + offset 4 bit 9 */ + bool unusedBit_4_9 : 1; + /** + offset 4 bit 10 */ + bool unusedBit_4_10 : 1; + /** + offset 4 bit 11 */ + bool unusedBit_4_11 : 1; + /** + offset 4 bit 12 */ + bool unusedBit_4_12 : 1; + /** + offset 4 bit 13 */ + bool unusedBit_4_13 : 1; + /** + offset 4 bit 14 */ + bool unusedBit_4_14 : 1; + /** + offset 4 bit 15 */ + bool unusedBit_4_15 : 1; + /** + offset 4 bit 16 */ + bool unusedBit_4_16 : 1; + /** + offset 4 bit 17 */ + bool unusedBit_4_17 : 1; + /** + offset 4 bit 18 */ + bool unusedBit_4_18 : 1; + /** + offset 4 bit 19 */ + bool unusedBit_4_19 : 1; + /** + offset 4 bit 20 */ + bool unusedBit_4_20 : 1; + /** + offset 4 bit 21 */ + bool unusedBit_4_21 : 1; + /** + offset 4 bit 22 */ + bool unusedBit_4_22 : 1; + /** + offset 4 bit 23 */ + bool unusedBit_4_23 : 1; + /** + offset 4 bit 24 */ + bool unusedBit_4_24 : 1; + /** + offset 4 bit 25 */ + bool unusedBit_4_25 : 1; + /** + offset 4 bit 26 */ + bool unusedBit_4_26 : 1; + /** + offset 4 bit 27 */ + bool unusedBit_4_27 : 1; + /** + offset 4 bit 28 */ + bool unusedBit_4_28 : 1; + /** + offset 4 bit 29 */ + bool unusedBit_4_29 : 1; + /** + offset 4 bit 30 */ + bool unusedBit_4_30 : 1; + /** + offset 4 bit 31 */ + bool unusedBit_4_31 : 1; + /** + * offset 8 + */ + int customTotalToothCount; + /** + * offset 12 + */ + int customSkippedToothCount; + /** total size 16*/ +}; + +typedef struct trigger_config_s trigger_config_s; + +// start of afr_sensor_s +struct afr_sensor_s { + /** + * offset 0 + */ + adc_channel_e hwChannel; + /** + * offset 1 + */ + uint8_t alignAf[3]; + /** + * offset 4 + */ + float v1; + /** + * offset 8 + */ + float value1; + /** + * offset 12 + */ + float v2; + /** + * offset 16 + */ + float value2; + /** total size 20*/ +}; + +typedef struct afr_sensor_s afr_sensor_s; + +// start of idle_hardware_s +struct idle_hardware_s { + /** + * offset 0 + */ + int solenoidFrequency; + /** + * offset 4 + */ + brain_pin_e solenoidPin; + /** + * offset 5 + */ + brain_pin_e stepperDirectionPin; + /** + * offset 6 + */ + brain_pin_e stepperStepPin; + /** + * offset 7 + */ + pin_output_mode_e solenoidPinMode; + /** total size 8*/ +}; + +typedef struct idle_hardware_s idle_hardware_s; + +// start of etb_io +struct etb_io { + /** + * offset 0 + */ + brain_pin_e directionPin1; + /** + * offset 1 + */ + brain_pin_e directionPin2; + /** + * offset 2 + */ + brain_pin_e controlPin1; + /** + * offset 3 + */ + pin_output_mode_e controlPinMode; + /** total size 4*/ +}; + +typedef struct etb_io etb_io; + +// start of engine_configuration_s +struct engine_configuration_s { + /** + * http://rusefi.com/wiki/index.php?title=Manual:Engine_Type + * set engine_type X + * offset 0 + */ + engine_type_e engineType; + /** + * Engine sniffer would be disabled above this rpm + * set engineSnifferRpmThreshold X + * offset 4 + */ + int engineSnifferRpmThreshold; + /** + * offset 8 + */ + injector_s injector; + /** + * Should trigger emulator push data right into trigger handling logic, eliminating the need for physical jumper wires? + * See also triggerSimulatorPins + * PS: Funny name, right? :) + offset 76 bit 0 */ + bool directSelfStimulation : 1; + /** + offset 76 bit 1 */ + bool activateAuxPid1 : 1; + /** + offset 76 bit 2 */ + bool isVerboseAuxPid1 : 1; + /** + offset 76 bit 3 */ + bool activateAuxPid2 : 1; + /** + offset 76 bit 4 */ + bool isVerboseAuxPid2 : 1; + /** + offset 76 bit 5 */ + bool activateAuxPid3 : 1; + /** + offset 76 bit 6 */ + bool isVerboseAuxPid3 : 1; + /** + offset 76 bit 7 */ + bool activateAuxPid4 : 1; + /** + offset 76 bit 8 */ + bool isVerboseAuxPid4 : 1; + /** + offset 76 bit 9 */ + bool useBiQuadAnalogFiltering : 1; + /** + offset 76 bit 10 */ + bool cj125isUaDivided : 1; + /** + offset 76 bit 11 */ + bool cj125isLsu49 : 1; + /** + offset 76 bit 12 */ + bool etb_use_two_wires : 1; + /** + offset 76 bit 13 */ + bool unusedHereo_wires : 1; + /** + offset 76 bit 14 */ + bool showSdCardWarning : 1; + /** + * looks like 3v range should be enough, divider not needed + offset 76 bit 15 */ + bool cj125isUrDivided : 1; + /** + offset 76 bit 16 */ + bool useTLE8888_hall_mode : 1; + /** + offset 76 bit 17 */ + bool useTLE8888_cranking_hack : 1; + /** + offset 76 bit 18 */ + bool useInstantRpmForIdle : 1; + /** + * If your fuel regulator does not have vacuum line + offset 76 bit 19 */ + bool absoluteFuelPressure : 1; + /** + offset 76 bit 20 */ + bool issue_294_21 : 1; + /** + offset 76 bit 21 */ + bool issue_294_22 : 1; + /** + offset 76 bit 22 */ + bool issue_294_23 : 1; + /** + offset 76 bit 23 */ + bool issue_294_24 : 1; + /** + offset 76 bit 24 */ + bool issue_294_25 : 1; + /** + offset 76 bit 25 */ + bool issue_294_26 : 1; + /** + offset 76 bit 26 */ + bool issue_294_27 : 1; + /** + offset 76 bit 27 */ + bool issue_294_28 : 1; + /** + offset 76 bit 28 */ + bool issue_294_29 : 1; + /** + offset 76 bit 29 */ + bool issue_294_30 : 1; + /** + offset 76 bit 30 */ + bool issue_294_31 : 1; + /** + offset 76 bit 31 */ + bool unusedBit_34_31 : 1; + /** + * Closed throttle. todo: extract these two fields into a structure + * See also tps1_1AdcChannel + * set tps_min X + * offset 80 + */ + int16_t tpsMin; + /** + * Full throttle. tpsMax value as 10 bit ADC value. Not Voltage! + * See also tps1_1AdcChannel + * set tps_max X + * offset 82 + */ + int16_t tpsMax; + /** + * TPS error detection, what TPS % value is unrealistically low + * offset 84 + */ + int16_t tpsErrorDetectionTooLow; + /** + * TPS error detection, what TPS % value is unrealistically high + * offset 86 + */ + int16_t tpsErrorDetectionTooHigh; + /** + * offset 88 + */ + cranking_parameters_s cranking; + /** + * offset 96 + */ + float primingSquirtDurationMs; + /** + * Used if useConstantDwellDuringCranking is TRUE + * offset 100 + */ + float ignitionDwellForCrankingMs; + /** + * While cranking (which causes battery voltage to drop) we can calculate dwell time in shaft + * degrees, not in absolute time as in running mode. + * set cranking_charge_angle X + * offset 104 + */ + float crankingChargeAngle; + /** + * @see hasMapSensor + * @see isMapAveragingEnabled + * offset 108 + */ + MAP_sensor_config_s map; + /** + * todo: merge with channel settings, use full-scale Thermistor here! + * offset 252 + */ + ThermistorConf clt; + /** + * offset 284 + */ + ThermistorConf iat; + /** + * A secondary Rev limit engaged by the driver to help launch the vehicle faster + * offset 316 + */ + int step1rpm; + /** + * offset 320 + */ + int step1timing; + /** + * value '6' for 8MHz hw osc + * read hip9011 datasheet for details + * todo split into two bit fields + * offset 324 + */ + int hip9011PrescalerAndSDO; + /** + * We calculate knock band based of cylinderBore + * Use this to override - kHz knock band override + * offset 328 + */ + float knockBandCustom; + /** + * On single-coil or wasted spark setups you have to lower dwell at high RPM + * offset 332 + */ + float sparkDwellRpmBins[DWELL_CURVE_SIZE]; + /** + * offset 364 + */ + float sparkDwellValues[DWELL_CURVE_SIZE]; + /** + * offset 396 + */ + specs_s specs; + /** + * Cylinder diameter, in mm. + * offset 408 + */ + float cylinderBore; + /** + * Disable sensor sniffer above this rpm + * offset 412 + */ + int sensorSnifferRpmThreshold; + /** + * set rpm_hard_limit X + * offset 416 + */ + int rpmHardLimit; + /** + * This setting controls which fuel quantity control algorithm is used. + * See also useTPSAdvanceTable + * set algorithm X + * offset 420 + */ + engine_load_mode_e fuelAlgorithm; + /** + * This is the injection strategy during engine start. See Fuel/Injection settings for more detail. It is suggested to use "Simultaneous". + * offset 424 + */ + injection_mode_e crankingInjectionMode; + /** + * This is where the fuel injection type is defined: "Simultaneous" means all injectors will fire together at once. "Sequential" fires the injectors on a per cylinder basis, which requires individually wired injectors. "Batched" will fire the injectors in groups. If your injectors are individually wired you will also need to enable "Two wire batch emulation". + * set injection_mode X + * See also twoWireBatchInjection + * offset 428 + */ + injection_mode_e injectionMode; + /** + * this is about deciding when the injector starts it's squirt + * See also injectionPhase map + * todo: do we need even need this since we have the map anyway? + * offset 432 + */ + angle_t extraInjectionOffset; + /** + * Ignition advance angle used during engine cranking, 5-10 degrees will work as a base setting for most engines. + * set cranking_timing_angle X + * offset 436 + */ + angle_t crankingTimingAngle; + /** + * "One Coil" is for use on distributed ignition system. "Individual Coils" is to be used when you have one coil per cylinder (COP or similar). "Wasted" means one coil is driving two spark plugs in two cylinders, with one of the sparks not doing anything since it's happening on the exhaust cycle + * set ignition_mode X + * offset 440 + */ + ignition_mode_e ignitionMode; + /** + * this value could be used to offset the whole ignition timing table by a constant + * offset 444 + */ + angle_t ignitionOffset; + /** + * Dynamic uses the timing map to decide the ignition timing, Static timing fixes the timing to the value set below (only use for checking static timing). + * offset 448 + */ + timing_mode_e timingMode; + /** + * This value is the ignition timing used when in 'fixed timing' mode, i.e. constant timing + * This mode is useful when adjusting distributor location. + * offset 452 + */ + angle_t fixedModeTiming; + /** + * Angle between Top Dead Center (TDC) and the first trigger event. + * Knowing this angle allows us to control timing and other angles in reference to TDC. + * set global_trigger_offset_angle X + * offset 456 + */ + angle_t globalTriggerAngleOffset; + /** + * Coefficient of input voltage dividers on your PCB + * offset 460 + */ + float analogInputDividerCoefficient; + /** + * This is the ratio of the resistors for the battery voltage, measure the voltage at the battery and then adjust this number until the gauge matches the reading. + * offset 464 + */ + float vbattDividerCoeff; + /** + * Cooling fan turn-on temperature threshold, in Celsius + * offset 468 + */ + float fanOnTemperature; + /** + * Cooling fan turn-off temperature threshold, in Celsius + * offset 472 + */ + float fanOffTemperature; + /** + * This coefficient translates vehicle speed input frequency (in Hz) into vehicle speed, km/h + * offset 476 + */ + float vehicleSpeedCoef; + /** + * set can_mode X + * offset 480 + */ + can_nbc_e canNbcType; + /** + * CANbus thread period, ms + * offset 484 + */ + int canSleepPeriodMs; + /** + * 'Some triggers could be mounted differently. Most well-known triggers imply specific sensor setup. 4 stroke with symmetrical crank' is a pretty special case for example on Miata NB2 + * See engineCycle + * set operation_mode X + * offset 488 + */ + operation_mode_e ambiguousOperationMode; + /** + * offset 492 + */ + display_mode_e displayMode; + /** + * offset 496 + */ + log_format_e logFormat; + /** + * offset 500 + */ + int byFirmwareVersion; + /** + * offset 504 + */ + int HD44780width; + /** + * offset 508 + */ + int HD44780height; + /** + * First throttle body, first sensor. See also pedalPositionAdcChannel + * offset 512 + */ + adc_channel_e tps1_1AdcChannel; + /** + * This is the processor input pin that the battery voltage circuit is connected to, if you are unsure of what pin to use, check the schematic that corresponds to your PCB. + * offset 513 + */ + adc_channel_e vbattAdcChannel; + /** + * This is the processor pin that your fuel level sensor in connected to. This is a non standard input so will need to be user defined. + * offset 514 + */ + adc_channel_e fuelLevelSensor; + /** + * Second throttle body position sensor, single channel so far + * offset 515 + */ + adc_channel_e tps2_1AdcChannel; + /** + * offset 516 + */ + int overrideCrankingIgnition; + /** + * offset 520 + */ + int sensorChartFrequency; + /** + * offset 524 + */ + trigger_config_s trigger; + /** + * offset 540 + */ + spi_device_e hip9011SpiDevice; + /** + * offset 541 + */ + adc_channel_e high_fuel_pressure_sensor_1; + /** + * offset 542 + */ + adc_channel_e high_fuel_pressure_sensor_2; + /** + * See hasMafSensor + * offset 543 + */ + adc_channel_e mafAdcChannel; + /** + * set global_fuel_correction X + * offset 544 + */ + float globalFuelCorrection; + /** + * offset 548 + */ + float adcVcc; + /** + * maximum total number of degrees to subtract from ignition advance + * when knocking + * offset 552 + */ + float maxKnockSubDeg; + /** + * Camshaft input could be used either just for engine phase detection if your trigger shape does not include cam sensor as 'primary' channel, or it could be used for Variable Valve timing on one of the camshafts. + * TODO #660 + * offset 556 + */ + brain_input_pin_e camInputs[CAM_INPUTS_COUNT]; + /** + * offset 560 + */ + afr_sensor_s afr; + /** + * Electronic throttle pedal position input + * First channel + * See also tps1_1AdcChannel + * offset 580 + */ + adc_channel_e throttlePedalPositionAdcChannel; + /** + * offset 581 + */ + brain_pin_e tle6240_cs; + /** + * offset 582 + */ + pin_output_mode_e tle6240_csPinMode; + /** + * Throttle Pedal not pressed switch - used on some older vehicles like early Mazda Miata + * offset 583 + */ + switch_input_pin_e throttlePedalUpPin; + /** + * @see hasBaroSensor + * offset 584 + */ + air_pressure_sensor_config_s baroSensor; + /** + * offset 600 + */ + idle_hardware_s idle; + /** + * value between 0 and 100 used in Manual mode + * offset 608 + */ + float manIdlePosition; + /** + * offset 612 + */ + float mapFrequency0Kpa; + /** + * offset 616 + */ + float mapFrequency100Kpa; + /** + * Same RPM is used for two ways of producing simulated RPM. See also triggerSimulatorPins (with wires) + * See also directSelfStimulation (no wires, bypassing input hardware) + * rpm X + * offset 620 + */ + int triggerSimulatorFrequency; + /** + * offset 624 + */ + output_pin_e injectionPins[INJECTION_PIN_COUNT]; + /** + * offset 636 + */ + output_pin_e ignitionPins[IGNITION_PIN_COUNT]; + /** + * offset 648 + */ + pin_output_mode_e injectionPinMode; + /** + * offset 649 + */ + pin_output_mode_e ignitionPinMode; + /** + * offset 650 + */ + brain_pin_e HD44780_rs; + /** + * offset 651 + */ + brain_pin_e HD44780_e; + /** + * offset 652 + */ + brain_pin_e HD44780_db4; + /** + * offset 653 + */ + brain_pin_e HD44780_db5; + /** + * offset 654 + */ + brain_pin_e HD44780_db6; + /** + * offset 655 + */ + brain_pin_e HD44780_db7; + /** + * offset 656 + */ + brain_pin_e gps_rx_pin; + /** + * offset 657 + */ + brain_pin_e gps_tx_pin; + /** + * offset 658 + */ + output_pin_e fuelPumpPin; + /** + * offset 659 + */ + pin_output_mode_e fuelPumpPinMode; + /** + * Check engine light, also malfunction indicator light. Always blinks once on boot. + * offset 660 + */ + output_pin_e malfunctionIndicatorPin; + /** + * offset 661 + */ + pin_output_mode_e malfunctionIndicatorPinMode; + /** + * offset 662 + */ + pin_output_mode_e fanPinMode; + /** + * offset 663 + */ + output_pin_e fanPin; + /** + * some cars have a switch to indicate that clutch pedal is all the way down + * offset 664 + */ + switch_input_pin_e clutchDownPin; + /** + * offset 665 + */ + output_pin_e alternatorControlPin; + /** + * offset 666 + */ + pin_output_mode_e alternatorControlPinMode; + /** + * offset 667 + */ + pin_input_mode_e clutchDownPinMode; + /** + * offset 668 + */ + brain_pin_e digitalPotentiometerChipSelect[DIGIPOT_COUNT]; + /** + * offset 672 + */ + pin_output_mode_e electronicThrottlePin1Mode; + /** + * offset 673 + */ + brain_pin_e wboHeaterPin; + /** + * offset 674 + */ + brain_pin_e cj125CsPin; + /** + * offset 675 + */ + spi_device_e max31855spiDevice; + /** + * offset 676 + */ + brain_pin_e debugTriggerSync; + /** + * Digital Potentiometer is used by stock ECU stimulation code + * offset 677 + */ + spi_device_e digitalPotentiometerSpiDevice; + /** + * offset 678 + */ + brain_pin_e mc33972_cs; + /** + * offset 679 + */ + pin_output_mode_e mc33972_csPinMode; + /** + * Useful in Research&Development phase + * offset 680 + */ + adc_channel_e auxFastSensor1_adcChannel; + /** + * First throttle body, second sensor. + * offset 681 + */ + adc_channel_e tps1_2AdcChannel; + /** + * Second throttle body, second sensor. + * offset 682 + */ + adc_channel_e tps2_2AdcChannel; + /** + * Electronic throttle pedal position input + * Second channel + * See also tps1_1AdcChannel + * offset 683 + */ + adc_channel_e throttlePedalPositionSecondAdcChannel; + /** + * offset 684 + */ + float fuelLevelEmptyTankVoltage; + /** + * offset 688 + */ + float fuelLevelFullTankVoltage; + /** + * AFR, WBO, EGO - whatever you like to call it + * offset 692 + */ + ego_sensor_e afr_type; + /** + * offset 696 + */ + float fuelClosedLoopAfrLowThreshold; + /** + * offset 700 + */ + brain_input_pin_e triggerInputPins[TRIGGER_INPUT_PIN_COUNT]; + /** + * offset 703 + */ + pin_output_mode_e hip9011CsPinMode; + /** + * This implementation produces one pulse per engine cycle. See also dizzySparkOutputPin. + * offset 704 + */ + output_pin_e tachOutputPin; + /** + * offset 705 + */ + pin_output_mode_e tachOutputPinMode; + /** + * offset 706 + */ + output_pin_e mainRelayPin; + /** + * offset 707 + */ + brain_pin_e sdCardCsPin; + /** + * offset 708 + */ + brain_pin_e canTxPin; + /** + * offset 709 + */ + brain_pin_e canRxPin; + /** + * offset 710 + */ + pin_input_mode_e throttlePedalUpPinMode; + /** + * offset 711 + */ + brain_pin_e debugTimerCallback; + /** + * offset 712 + */ + int idleThreadPeriodMs; + /** + * offset 716 + */ + int consoleLoopPeriodMs; + /** + * offset 720 + */ + int lcdThreadPeriodMs; + /** + * offset 724 + */ + int generalPeriodicThreadPeriodMs; + /** + * offset 728 + */ + uint32_t tunerStudioSerialSpeed; + /** + * offset 732 + */ + can_device_mode_e canDeviceMode; + /** + * Each rusEfi piece can provide synthetic trigger signal for external ECU. Sometimes these wires are routed back into trigger inputs of the same rusEfi board. + * See also directSelfStimulation which is different. + * offset 736 + */ + brain_pin_e triggerSimulatorPins[TRIGGER_SIMULATOR_PIN_COUNT]; + /** + * offset 739 + */ + pin_output_mode_e triggerSimulatorPinModes[TRIGGER_SIMULATOR_PIN_COUNT]; + /** + * Narrow band o2 heater, not used for CJ125. See wboHeaterPin + * offset 742 + */ + output_pin_e o2heaterPin; + /** + * offset 743 + */ + pin_output_mode_e o2heaterPinModeTodO; + /** + offset 744 bit 0 */ + bool is_enabled_spi_1 : 1; + /** + offset 744 bit 1 */ + bool is_enabled_spi_2 : 1; + /** + offset 744 bit 2 */ + bool is_enabled_spi_3 : 1; + /** + offset 744 bit 3 */ + bool isSdCardEnabled : 1; + /** + offset 744 bit 4 */ + bool isFastAdcEnabled : 1; + /** + offset 744 bit 5 */ + bool isEngineControlEnabled : 1; + /** + offset 744 bit 6 */ + bool isHip9011Enabled : 1; + /** + offset 744 bit 7 */ + bool isVerboseAlternator : 1; + /** + offset 744 bit 8 */ + bool useSerialPort : 1; + /** + * This setting should only be used if you have a stepper motor idle valve and a stepper motor driver installed. + offset 744 bit 9 */ + bool useStepperIdle : 1; + /** + offset 744 bit 10 */ + bool enabledStep1Limiter : 1; + /** + offset 744 bit 11 */ + bool useTpicAdvancedMode : 1; + /** + offset 744 bit 12 */ + bool useLcdScreen : 1; + /** + offset 744 bit 13 */ + bool unusedAnotherOne : 1; + /** + offset 744 bit 14 */ + bool unusedOldWarmupAfr : 1; + /** + * +This will cause the alternator to be operated in a basic on or off mode, this is the simplest alternator control. + offset 744 bit 15 */ + bool onOffAlternatorLogic : 1; + /** + offset 744 bit 16 */ + bool isCJ125Enabled : 1; + /** + * Use rise or fall signal front + offset 744 bit 17 */ + bool vvtCamSensorUseRise : 1; + /** + * Useful for individual intakes + offset 744 bit 18 */ + bool measureMapOnlyInOneCylinder : 1; + /** + offset 744 bit 19 */ + bool stepperForceParkingEveryRestart : 1; + /** + * Smarter cranking logic. + * See also startOfCrankingPrimingPulse + offset 744 bit 20 */ + bool isFasterEngineSpinUpEnabled : 1; + /** + * This setting disables fuel injection while the engine is in overrun, this is useful as a fuel saving measure and to prevent back firing. + offset 744 bit 21 */ + bool coastingFuelCutEnabled : 1; + /** + * This setting allows the ECU to open the IAC during overrun conditions to help reduce engine breaking, this can be helpful for large engines in light weight cars. + offset 744 bit 22 */ + bool useIacTableForCoasting : 1; + /** + offset 744 bit 23 */ + bool useNoiselessTriggerDecoder : 1; + /** + offset 744 bit 24 */ + bool useIdleTimingPidControl : 1; + /** + offset 744 bit 25 */ + bool useTPSBasedVeTable : 1; + /** + offset 744 bit 26 */ + bool is_enabled_spi_4 : 1; + /** + offset 744 bit 27 */ + bool pauseEtbControl : 1; + /** + offset 744 bit 28 */ + bool alignEngineSnifferAtTDC : 1; + /** + * This setting allows the ETB to act as the idle air control valve and move to regulate the airflow at idle. + offset 744 bit 29 */ + bool useETBforIdleControl : 1; + /** + offset 744 bit 30 */ + bool idleIncrementalPidCic : 1; + /** + offset 744 bit 31 */ + bool enableAemXSeries : 1; + /** + * offset 748 + */ + brain_input_pin_e logicAnalyzerPins[LOGIC_ANALYZER_CHANNEL_COUNT]; + /** + * offset 752 + */ + pin_output_mode_e mainRelayPinMode; + /** + * offset 753 + */ + brain_pin_e hip9011CsPin; + /** + * offset 754 + */ + brain_pin_e hip9011IntHoldPin; + /** + * offset 755 + */ + pin_output_mode_e hip9011IntHoldPinMode; + /** + * default or inverted input + * offset 756 + */ + uint8_t logicAnalyzerMode[LOGIC_ANALYZER_CHANNEL_COUNT]; + /** + * offset 760 + */ + int unrealisticRpmThreashold; + /** + * offset 764 + */ + pin_output_mode_e gpioPinModes[FSIO_COMMAND_COUNT]; + /** + * todo: more comments + * offset 780 + */ + output_pin_e fsioOutputPins[FSIO_COMMAND_COUNT]; + /** + * offset 796 + */ + brain_pin_e max31855_cs[EGT_CHANNEL_COUNT]; + /** + * SD card logging period, in milliseconds + * offset 804 + */ + int16_t sdCardPeriodMs; + /** + * offset 806 + */ + brain_pin_e debugSetTimer; + /** + * offset 807 + */ + brain_pin_e debugMapAveraging; + /** + * offset 808 + */ + brain_pin_e starterRelayPin; + /** + * offset 809 + */ + pin_output_mode_e starterRelayPinMode; + /** + * offset 810 + */ + uint8_t unuseduartPadding1[2]; + /** + * offset 812 + */ + int mapMinBufferLength; + /** + * offset 816 + */ + int16_t idlePidDeactivationTpsThreshold; + /** + * offset 818 + */ + int16_t stepperParkingExtraSteps; + /** + * This magic property is specific to Mazda Miata NB2 + * offset 820 + */ + float miataNb2VVTRatioFrom; + /** + * This magic property is specific to Mazda Miata NB2 + * offset 824 + */ + float miataNb2VVTRatioTo; + /** + * This pin is used for debugging - snap a logic analyzer on it and see if it's ever high + * offset 828 + */ + brain_pin_e triggerErrorPin; + /** + * offset 829 + */ + pin_output_mode_e triggerErrorPinMode; + /** + * offset 830 + */ + output_pin_e acRelayPin; + /** + * offset 831 + */ + pin_output_mode_e acRelayPinMode; + /** + * offset 832 + */ + fsio_pwm_freq_t fsioFrequency[FSIO_COMMAND_COUNT]; + /** + * offset 864 + */ + fsio_setting_t fsio_setting[FSIO_COMMAND_COUNT]; + /** + * offset 928 + */ + brain_pin_e spi1mosiPin; + /** + * offset 929 + */ + brain_pin_e spi1misoPin; + /** + * offset 930 + */ + brain_pin_e spi1sckPin; + /** + * offset 931 + */ + brain_pin_e spi2mosiPin; + /** + * offset 932 + */ + brain_pin_e spi2misoPin; + /** + * offset 933 + */ + brain_pin_e spi2sckPin; + /** + * offset 934 + */ + brain_pin_e spi3mosiPin; + /** + * offset 935 + */ + brain_pin_e spi3misoPin; + /** + * offset 936 + */ + brain_pin_e spi3sckPin; + /** + * Saab Combustion Detection Module knock signal input pin + * also known as Saab Ion Sensing Module + * offset 937 + */ + brain_pin_e cdmInputPin; + /** + * offset 938 + */ + brain_pin_e joystickCenterPin; + /** + * offset 939 + */ + brain_pin_e joystickAPin; + /** + * offset 940 + */ + brain_pin_e joystickBPin; + /** + * offset 941 + */ + brain_pin_e joystickCPin; + /** + * offset 942 + */ + brain_pin_e joystickDPin; + /** + * offset 943 + */ + uart_device_e consoleUartDevice; + /** + * rusEfi console Sensor Sniffer mode + * offset 944 + */ + sensor_chart_e sensorChartMode; + /** + * offset 948 + */ + maf_sensor_type_e mafSensorType; + /** + * todo:not finished + * These input pins allow us to pull toggle buttons state + * offset 952 + */ + brain_pin_e fsioDigitalInputs[FSIO_COMMAND_COUNT]; + /** + * offset 968 + */ + brain_input_pin_e vehicleSpeedSensorInputPin; + /** + * Some vehicles have a switch to indicate that clutch pedal is all the way up + * offset 969 + */ + switch_input_pin_e clutchUpPin; + /** + * offset 970 + */ + brain_input_pin_e frequencyReportingMapInputPin; + /** + * offset 971 + */ + pin_input_mode_e clutchUpPinMode; + /** + * offset 972 + */ + float unused; + /** + offset 976 bit 0 */ + bool todoClutchUpPinInverted : 1; + /** + offset 976 bit 1 */ + bool todoClutchDownPinInverted : 1; + /** + offset 976 bit 2 */ + bool unusedBit_249_2 : 1; + /** + offset 976 bit 3 */ + bool unusedBit_249_3 : 1; + /** + offset 976 bit 4 */ + bool unusedBit_249_4 : 1; + /** + offset 976 bit 5 */ + bool unusedBit_249_5 : 1; + /** + offset 976 bit 6 */ + bool unusedBit_249_6 : 1; + /** + offset 976 bit 7 */ + bool unusedBit_249_7 : 1; + /** + offset 976 bit 8 */ + bool unusedBit_249_8 : 1; + /** + offset 976 bit 9 */ + bool unusedBit_249_9 : 1; + /** + offset 976 bit 10 */ + bool unusedBit_249_10 : 1; + /** + offset 976 bit 11 */ + bool unusedBit_249_11 : 1; + /** + offset 976 bit 12 */ + bool unusedBit_249_12 : 1; + /** + offset 976 bit 13 */ + bool unusedBit_249_13 : 1; + /** + offset 976 bit 14 */ + bool unusedBit_249_14 : 1; + /** + offset 976 bit 15 */ + bool unusedBit_249_15 : 1; + /** + offset 976 bit 16 */ + bool unusedBit_249_16 : 1; + /** + offset 976 bit 17 */ + bool unusedBit_249_17 : 1; + /** + offset 976 bit 18 */ + bool unusedBit_249_18 : 1; + /** + offset 976 bit 19 */ + bool unusedBit_249_19 : 1; + /** + offset 976 bit 20 */ + bool unusedBit_249_20 : 1; + /** + offset 976 bit 21 */ + bool unusedBit_249_21 : 1; + /** + offset 976 bit 22 */ + bool unusedBit_249_22 : 1; + /** + offset 976 bit 23 */ + bool unusedBit_249_23 : 1; + /** + offset 976 bit 24 */ + bool unusedBit_249_24 : 1; + /** + offset 976 bit 25 */ + bool unusedBit_249_25 : 1; + /** + offset 976 bit 26 */ + bool unusedBit_249_26 : 1; + /** + offset 976 bit 27 */ + bool unusedBit_249_27 : 1; + /** + offset 976 bit 28 */ + bool unusedBit_249_28 : 1; + /** + offset 976 bit 29 */ + bool unusedBit_249_29 : 1; + /** + offset 976 bit 30 */ + bool unusedBit_249_30 : 1; + /** + offset 976 bit 31 */ + bool unusedBit_249_31 : 1; + /** + * offset 980 + */ + etb_io etbIo[ETB_COUNT]; + /** + * offset 988 + */ + int unusedAtOldBoardConfigurationEnd[119]; + /** + offset 1464 bit 0 */ + bool vvtDisplayInverted : 1; + /** + * Enables lambda sensor closed loop feedback for fuelling. + offset 1464 bit 1 */ + bool fuelClosedLoopCorrectionEnabled : 1; + /** + * Print details into rusEfi console + offset 1464 bit 2 */ + bool isVerboseIAC : 1; + /** + * Prints ETB details to rusEFI console + offset 1464 bit 3 */ + bool isVerboseETB : 1; + /** + * If set to true, will use the specified duration for cranking dwell. If set to false, will use the specified dwell angle. Unless you have a really good reason to, leave this set to true to use duration mode. + offset 1464 bit 4 */ + bool useConstantDwellDuringCranking : 1; + /** + * This options enables data for 'engine sniffer' tab in console, which comes at some CPU price + offset 1464 bit 5 */ + bool isEngineChartEnabled : 1; + /** + * Sometimes we have a performance issue while printing error + offset 1464 bit 6 */ + bool silentTriggerError : 1; + /** + offset 1464 bit 7 */ + bool useLinearCltSensor : 1; + /** + offset 1464 bit 8 */ + bool canReadEnabled : 1; + /** + offset 1464 bit 9 */ + bool canWriteEnabled : 1; + /** + offset 1464 bit 10 */ + bool useLinearIatSensor : 1; + /** + * See fsioTimingAdjustment + offset 1464 bit 11 */ + bool useFSIO16ForTimingAdjustment : 1; + /** + offset 1464 bit 12 */ + bool tachPulseDurationAsDutyCycle : 1; + /** + * This enables smart alternator control and activates the extra alternator settings. + offset 1464 bit 13 */ + bool isAlternatorControlEnabled : 1; + /** + * This setting flips the signal from the primary engine speed sensor. + offset 1464 bit 14 */ + bool invertPrimaryTriggerSignal : 1; + /** + * This setting flips the signal from the secondary engine speed sensor. + offset 1464 bit 15 */ + bool invertSecondaryTriggerSignal : 1; + /** + offset 1464 bit 16 */ + bool cutFuelOnHardLimit : 1; + /** + offset 1464 bit 17 */ + bool cutSparkOnHardLimit : 1; + /** + offset 1464 bit 18 */ + bool step1fuelCutEnable : 1; + /** + offset 1464 bit 19 */ + bool step1SparkCutEnable : 1; + /** + offset 1464 bit 20 */ + bool hasFrequencyReportingMapSensor : 1; + /** + offset 1464 bit 21 */ + bool useFSIO8ForServo1 : 1; + /** + offset 1464 bit 22 */ + bool useFSIO9ForServo2 : 1; + /** + offset 1464 bit 23 */ + bool useFSIO10ForServo3 : 1; + /** + offset 1464 bit 24 */ + bool useFSIO11ForServo4 : 1; + /** + offset 1464 bit 25 */ + bool useFSIO12ForServo5 : 1; + /** + offset 1464 bit 26 */ + bool useFSIO15ForIdleRpmAdjustment : 1; + /** + * Sometimes we just have to shut the engine down. Use carefully! + offset 1464 bit 27 */ + bool useFSIO5ForCriticalIssueEngineStop : 1; + /** + * Sometimes we have to miss injection on purpose to attract driver's attention + offset 1464 bit 28 */ + bool useFSIO4ForSeriousEngineWarning : 1; + /** + offset 1464 bit 29 */ + bool useFSIO12ForIdleOffset : 1; + /** + offset 1464 bit 30 */ + bool useFSIO13ForIdleMinValue : 1; + /** + offset 1464 bit 31 */ + bool useFSIO6ForRevLimiter : 1; + /** + * offset 1468 + */ + adc_channel_e hipOutputChannel; + /** + * A/C button input handled as analogue input + * offset 1469 + */ + adc_channel_e acSwitchAdc; + /** + * offset 1470 + */ + adc_channel_e vRefAdcChannel; + /** + * Expected neutral position + * offset 1471 + */ + uint8_t etbNeutralPosition; + /** + * See also idleRpmPid + * offset 1472 + */ + idle_mode_e idleMode; + /** + * Enable fuel injection - This is default off for new projects as a safety feature, set to "true" to enable fuel injection and further injector settings. + offset 1476 bit 0 */ + bool isInjectionEnabled : 1; + /** + * Enable ignition - This is default off for new projects as a safety feature, set to "true" to enable ignition and further ignition settings. + offset 1476 bit 1 */ + bool isIgnitionEnabled : 1; + /** + * When enabled if TPS is held above 95% no fuel is injected while cranking to clear excess fuel from the cylinders. + offset 1476 bit 2 */ + bool isCylinderCleanupEnabled : 1; + /** + offset 1476 bit 3 */ + bool secondTriggerChannelEnabled : 1; + /** + offset 1476 bit 4 */ + bool unusedBit4_1476 : 1; + /** + offset 1476 bit 5 */ + bool isMapAveragingEnabled : 1; + /** + * This setting overrides the normal multiplication values that have been set for the idle air control valve during cranking. If this setting is enabled the "IAC multiplier" table in the Cranking settings tab needs to be adjusted appropriately or potentially no IAC opening will occur. + offset 1476 bit 6 */ + bool overrideCrankingIacSetting : 1; + /** + * This activates a separate ignition timing table for idle conditions, this can help idle stability by using ignition retard and advance either side of the desired idle speed. Extra retard at low idle speeds will prevent stalling and extra advance at high idle speeds can help reduce engine power and slow the idle speed. + offset 1476 bit 7 */ + bool useSeparateAdvanceForIdle : 1; + /** + offset 1476 bit 8 */ + bool isTunerStudioEnabled : 1; + /** + offset 1476 bit 9 */ + bool isWaveAnalyzerEnabled : 1; + /** + * This activates a separate fuel table for Idle, this allows fine tuning of the idle fuelling. + offset 1476 bit 10 */ + bool useSeparateVeForIdle : 1; + /** + * enable trigger_details + offset 1476 bit 11 */ + bool verboseTriggerSynchDetails : 1; + /** + * Usually if we have no trigger events that means engine is stopped + * Unless we are troubleshooting and spinning the engine by hand - this case a longer + * delay is needed + offset 1476 bit 12 */ + bool isManualSpinningMode : 1; + /** + * This is needed if your coils are individually wired and you wish to use batch injection. + * enable two_wire_batch_injection + offset 1476 bit 13 */ + bool twoWireBatchInjection : 1; + /** + * VR sensors are only precise on rising front + * enable trigger_only_front + offset 1476 bit 14 */ + bool useOnlyRisingEdgeForTrigger : 1; + /** + * This is needed if your coils are individually wired (COP) and you wish to use batch ignition (wasted spark). + offset 1476 bit 15 */ + bool twoWireBatchIgnition : 1; + /** + offset 1476 bit 16 */ + bool useFixedBaroCorrFromMap : 1; + /** + * This activates a separate advance table for cranking conditions, this allows cranking advance to be RPM dependant. + offset 1476 bit 17 */ + bool useSeparateAdvanceForCranking : 1; + /** + * This enables the various ignition corrections during cranking (IAT, CLT, FSIO and PID idle). + offset 1476 bit 18 */ + bool useAdvanceCorrectionsForCranking : 1; + /** + * This flag allows to use TPS for ignition lookup while in Speed Density Fuel Mode + offset 1476 bit 19 */ + bool useTPSAdvanceTable : 1; + /** + offset 1476 bit 20 */ + bool etbCalibrationOnStart : 1; + /** + * This flag allows to use a special 'PID Multiplier' table (0.0-1.0) to compensate for nonlinear nature of IAC-RPM controller + offset 1476 bit 21 */ + bool useIacPidMultTable : 1; + /** + offset 1476 bit 22 */ + bool unused_1484_bit_22 : 1; + /** + offset 1476 bit 23 */ + bool unused_1484_bit_23 : 1; + /** + offset 1476 bit 24 */ + bool unused_1484_bit_24 : 1; + /** + offset 1476 bit 25 */ + bool unused_1484_bit_25 : 1; + /** + offset 1476 bit 26 */ + bool unused_1484_bit_26 : 1; + /** + offset 1476 bit 27 */ + bool unused_1484_bit_27 : 1; + /** + offset 1476 bit 28 */ + bool unused_1484_bit_28 : 1; + /** + offset 1476 bit 29 */ + bool unused_1484_bit_29 : 1; + /** + offset 1476 bit 30 */ + bool unused_1484_bit_30 : 1; + /** + offset 1476 bit 31 */ + bool unused_1484_bit_31 : 1; + /** + * offset 1480 + */ + uint32_t engineChartSize; + /** + * Relative to the target idle RPM + * offset 1484 + */ + int16_t idlePidRpmUpperLimit; + /** + * This sets the temperature above which no priming pulse is used, The value at -40 is reduced until there is no more priming injection at this temperature. + * offset 1486 + */ + int16_t primeInjFalloffTemperature; + /** + * At what trigger index should some ignition-related math be executed? This is a performance trick to reduce load on synchronization trigger callback. + * offset 1488 + */ + int ignMathCalculateAtIndex; + /** + * offset 1492 + */ + int16_t acCutoffLowRpm; + /** + * offset 1494 + */ + int16_t acCutoffHighRpm; + /** + * offset 1496 + */ + int16_t acIdleRpmBump; + /** + * set warningPeriod X + * offset 1498 + */ + int16_t warningPeriod; + /** + * offset 1500 + */ + float knockDetectionWindowStart; + /** + * offset 1504 + */ + float knockDetectionWindowEnd; + /** + * offset 1508 + */ + float idleStepperReactionTime; + /** + * offset 1512 + */ + float knockVThreshold; + /** + * offset 1516 + */ + pin_input_mode_e fsioInputModes[FSIO_COMMAND_COUNT]; + /** + * offset 1532 + */ + int idleStepperTotalSteps; + /** + * TODO: finish this #413 + * offset 1536 + */ + float noAccelAfterHardLimitPeriodSecs; + /** + * At what trigger index should some MAP-related math be executed? This is a performance trick to reduce load on synchronization trigger callback. + * offset 1540 + */ + int mapAveragingSchedulingAtIndex; + /** + * offset 1544 + */ + float baroCorrPressureBins[BARO_CORR_SIZE]; + /** + * offset 1560 + */ + float baroCorrRpmBins[BARO_CORR_SIZE]; + /** + * offset 1576 + */ + baro_corr_table_t baroCorrTable; + /** + * Cranking fuel correction coefficient based on TPS + * offset 1640 + */ + float crankingTpsCoef[CRANKING_CURVE_SIZE]; + /** + * offset 1672 + */ + float crankingTpsBins[CRANKING_CURVE_SIZE]; + /** + * offset 1704 + */ + float tachPulseDuractionMs; + /** + * Trigger cycle index at which we start tach pulse (performance consideration) + * offset 1708 + */ + int tachPulseTriggerIndex; + /** + * Length of time the deposited wall fuel takes to dissipate after the start of acceleration. + * offset 1712 + */ + float wwaeTau; + /** + * offset 1716 + */ + pid_s alternatorControl; + /** + * offset 1736 + */ + pid_s etb; + /** + * offset 1756 + */ + float fuelRailPressure; + /** + * offset 1760 + */ + float alternator_derivativeFilterLoss; + /** + * offset 1764 + */ + float alternator_antiwindupFreq; + /** + * Closed throttle#2. todo: extract these two fields into a structure + * See also tps2_1AdcChannel + * set tps2_min X + * offset 1768 + */ + int16_t tps2Min; + /** + * Full throttle#2. tpsMax value as 10 bit ADC value. Not Voltage! + * See also tps1_1AdcChannel + * set tps2_max X + * offset 1770 + */ + int16_t tps2Max; + /** + * offset 1772 + */ + uint8_t unusedFormerWarmupAfrPid[3]; + /** + * offset 1775 + */ + uint8_t tachPulsePerRev; + /** + * kPa value which is too low to be true + * offset 1776 + */ + float mapErrorDetectionTooLow; + /** + * kPa value which is too high to be true + * offset 1780 + */ + float mapErrorDetectionTooHigh; + /** + * RPMs prior to step1rpm point where ignition advance is retarded + * offset 1784 + */ + int step1RpmWindow; + /** + * See cltIdleRpmBins + * offset 1788 + */ + pid_s idleRpmPid; + /** + * 0 = No fuel settling on port walls 1 = All the fuel settling on port walls setting this to 0 disables the wall wetting enrichment. + * offset 1808 + */ + float wwaeBeta; + /** + * blue LED on discovery by default + * offset 1812 + */ + brain_pin_e communicationLedPin; + /** + * green LED on discovery by default + * offset 1813 + */ + brain_pin_e runningLedPin; + /** + * offset 1814 + */ + brain_pin_e binarySerialTxPin; + /** + * offset 1815 + */ + brain_pin_e binarySerialRxPin; + /** + * offset 1816 + */ + brain_pin_e auxValves[AUX_DIGITAL_VALVE_COUNT]; + /** + * todo: finish pin migration from hard-coded to configurable? + * offset 1818 + */ + brain_pin_e consoleSerialTxPin; + /** + * todo: finish pin migration from hard-coded to configurable? + * offset 1819 + */ + brain_pin_e consoleSerialRxPin; + /** + * Knock sensor output knock detection threshold depending on current RPM + * offset 1820 + */ + float knockNoise[ENGINE_NOISE_CURVE_SIZE]; + /** + * offset 1852 + */ + float knockNoiseRpmBins[ENGINE_NOISE_CURVE_SIZE]; + /** + * offset 1884 + */ + float throttlePedalUpVoltage; + /** + * Pedal in the floor + * offset 1888 + */ + float throttlePedalWOTVoltage; + /** + * on ECU start turn fuel pump on to build fuel pressure + * offset 1892 + */ + int16_t startUpFuelPumpDuration; + /** + * If RPM is close enough let's leave IAC alone, and maybe engage timing PID correction + * offset 1894 + */ + int16_t idlePidRpmDeadZone; + /** + * CLT-based target RPM for automatic idle controller + * offset 1896 + */ + float cltIdleRpmBins[CLT_CURVE_SIZE]; + /** + * See idleRpmPid + * offset 1960 + */ + float cltIdleRpm[CLT_CURVE_SIZE]; + /** + * This is the target battery voltage the alternator PID control will attempt to maintain + * offset 2024 + */ + float targetVBatt; + /** + * Turns off alternator output above specified TPS, enabling this reduced parasitic drag on the engine at full load. + * offset 2028 + */ + float alternatorOffAboveTps; + /** + * Prime pulse for cold engine, duration in ms + * Linear interpolation between -40F/-40C and fallout temperature + * + * See also isFasterEngineSpinUpEnabled + * set cranking_priming_pulse X + * offset 2032 + */ + float startOfCrankingPrimingPulse; + /** + * This is the duration in cycles that the IAC will take to reach its normal idle position, it can be used to hold the idle higher for a few seconds after cranking to improve startup. + * offset 2036 + */ + int16_t afterCrankingIACtaperDuration; + /** + * Extra IAC, in percent between 0 and 100, tapered between zero and idle deactivation TPS value + * offset 2038 + */ + int16_t iacByTpsTaper; + /** + * offset 2040 + */ + brain_pin_e unusedErrorPin; + /** + * offset 2041 + */ + brain_pin_e warningLedPin; + /** + * offset 2042 + */ + brain_pin_e unused1234234; + /** + * offset 2043 + */ + brain_pin_e LIS302DLCsPin; + /** + * This is the number of engine cycles that the TPS position change can occur over, a longer duration will make the enrichment more active but too long may affect steady state driving, a good default is 30-60 cycles. + * offset 2044 + */ + int tpsAccelLength; + /** + * Maximum change delta of TPS percentage over the 'length'. Actual TPS change has to be above this value in order for TPS/TPS acceleration to kick in. + * offset 2048 + */ + float tpsAccelEnrichmentThreshold; + /** + * Angle between cam sensor and VVT zero position + * set vvt_offset X + * offset 2052 + */ + float vvtOffset; + /** + * offset 2056 + */ + int engineLoadAccelLength; + /** + * offset 2060 + */ + float engineLoadDecelEnleanmentThreshold; + /** + * offset 2064 + */ + float engineLoadDecelEnleanmentMultiplier; + /** + * offset 2068 + */ + float engineLoadAccelEnrichmentThreshold; + /** + * offset 2072 + */ + float engineLoadAccelEnrichmentMultiplier; + /** + * offset 2076 + */ + uint32_t uartConsoleSerialSpeed; + /** + * offset 2080 + */ + float tpsDecelEnleanmentThreshold; + /** + * offset 2084 + */ + float tpsDecelEnleanmentMultiplier; + /** + * ExpAverage alpha coefficient + * offset 2088 + */ + float slowAdcAlpha; + /** + * See http://rusefi.com/s/debugmode + * + * set debug_mode X + * offset 2092 + */ + debug_mode_e debugMode; + /** + * offset 2096 + */ + uint32_t unused_former_warmup_target_afr[9]; + /** + * kPa value at which we need to cut fuel and spark, 0 if not enabled + * offset 2132 + */ + float boostCutPressure; + /** + * offset 2136 + */ + float mapAccelTaperBins[MAP_ACCEL_TAPER]; + /** + * offset 2168 + */ + float mapAccelTaperMult[MAP_ACCEL_TAPER]; + /** + * todo: rename to fsioAnalogInputs + * offset 2200 + */ + adc_channel_e fsioAdc[FSIO_ANALOG_INPUT_COUNT]; + /** + * Fixed timing, useful for TDC testing + * offset 2204 + */ + float fixedTiming; + /** + * MAP voltage for low point + * offset 2208 + */ + float mapLowValueVoltage; + /** + * MAP voltage for low point + * offset 2212 + */ + float mapHighValueVoltage; + /** + * EGO value correction + * offset 2216 + */ + float egoValueShift; + /** + * offset 2220 + */ + output_pin_e auxPidPins[AUX_PID_COUNT]; + /** + * offset 2224 + */ + spi_device_e cj125SpiDevice; + /** + * offset 2225 + */ + pin_output_mode_e cj125CsPinMode; + /** + * This implementation makes a pulse every time one of the coils is charged, using coil dwell for pulse width. See also tachOutputPin + * offset 2226 + */ + brain_pin_e dizzySparkOutputPin; + /** + * offset 2227 + */ + pin_output_mode_e dizzySparkOutputPinMode; + /** + * This is the IAC position during cranking, some engines start better if given more air during cranking to improve cylinder filling. + * offset 2228 + */ + int crankingIACposition; + /** + * offset 2232 + */ + float tChargeMinRpmMinTps; + /** + * offset 2236 + */ + float tChargeMinRpmMaxTps; + /** + * offset 2240 + */ + float tChargeMaxRpmMinTps; + /** + * offset 2244 + */ + float tChargeMaxRpmMaxTps; + /** + * offset 2248 + */ + fsio_pwm_freq_t auxPidFrequency[AUX_PID_COUNT]; + /** + * offset 2256 + */ + int alternatorPwmFrequency; + /** + * offset 2260 + */ + mass_storage_e storageMode; + /** + * Narrow Band WBO Approximation + * offset 2264 + */ + float narrowToWideOxygenBins[NARROW_BAND_WIDE_BAND_CONVERSION_SIZE]; + /** + * offset 2296 + */ + float narrowToWideOxygen[NARROW_BAND_WIDE_BAND_CONVERSION_SIZE]; + /** + * set vvt_mode X + * offset 2328 + */ + vvt_mode_e vvtMode; + /** + * offset 2332 + */ + bi_quard_s biQuad; + /** + * CLT-based timing correction + * offset 2352 + */ + float cltTimingBins[CLT_TIMING_CURVE_SIZE]; + /** + * offset 2384 + */ + float cltTimingExtra[CLT_TIMING_CURVE_SIZE]; + /** + * offset 2416 + */ + int nbVvtIndex; + /** + * offset 2420 + */ + float autoTuneCltThreshold; + /** + * offset 2424 + */ + float autoTuneTpsRocThreshold; + /** + * offset 2428 + */ + float autoTuneTpsQuietPeriod; + /** + * offset 2432 + */ + float postCrankingTargetClt; + /** + * Fuel multiplier taper, see also postCrankingDurationSec + * offset 2436 + */ + float postCrankingFactor; + /** + * See also postCrankingFactor + * offset 2440 + */ + float postCrankingDurationSec; + /** + * todo: finish implementation #332 + * offset 2444 + */ + ThermistorConf auxTempSensor1; + /** + * todo: finish implementation #332 + * offset 2476 + */ + ThermistorConf auxTempSensor2; + /** + * offset 2508 + */ + int16_t fuelClosedLoopCltThreshold; + /** + * offset 2510 + */ + int16_t fuelClosedLoopTpsThreshold; + /** + * offset 2512 + */ + int16_t fuelClosedLoopRpmThreshold; + /** + * offset 2514 + */ + int16_t etbFreq; + /** + * offset 2516 + */ + pid_s fuelClosedLoopPid; + /** + * offset 2536 + */ + float fuelClosedLoopAfrHighThreshold; + /** + * per-cylinder timing correction + * offset 2540 + */ + cfg_float_t_1f timing_offset_cylinder[IGNITION_PIN_COUNT]; + /** + * offset 2588 + */ + float idlePidActivationTime; + /** + * offset 2592 + */ + spi_device_e sdCardSpiDevice; + /** + * offset 2593 + */ + uint8_t unusedSpiPadding4[3]; + /** + * offset 2596 + */ + pin_mode_e spi1SckMode; + /** + * offset 2597 + */ + pin_mode_e spi1MosiMode; + /** + * offset 2598 + */ + pin_mode_e spi1MisoMode; + /** + * offset 2599 + */ + pin_mode_e spi2SckMode; + /** + * offset 2600 + */ + pin_mode_e spi2MosiMode; + /** + * offset 2601 + */ + pin_mode_e spi2MisoMode; + /** + * offset 2602 + */ + pin_mode_e spi3SckMode; + /** + * offset 2603 + */ + pin_mode_e spi3MosiMode; + /** + * offset 2604 + */ + pin_mode_e spi3MisoMode; + /** + * offset 2605 + */ + pin_output_mode_e stepperEnablePinMode; + /** + * ResetB + * offset 2606 + */ + brain_pin_e mc33816_rstb; + /** + * offset 2607 + */ + brain_pin_e mc33816_driven; + /** + * Brake pedal switch + * offset 2608 + */ + switch_input_pin_e brakePedalPin; + /** + * lambda input + * offset 2609 + */ + adc_channel_e cj125ua; + /** + * heater input + * offset 2610 + */ + adc_channel_e cj125ur; + /** + * offset 2611 + */ + pin_input_mode_e brakePedalPinMode; + /** + * offset 2612 + */ + pid_s auxPid[AUX_PID_COUNT]; + /** + * offset 2692 + */ + oil_pressure_config_s oilPressure; + /** + * offset 2712 + */ + spi_device_e accelerometerSpiDevice; + /** + * offset 2713 + */ + uint8_t unusedSpiPadding5[3]; + /** + * offset 2716 + */ + float fsioCurve1Bins[FSIO_CURVE_16]; + /** + * offset 2780 + */ + float fsioCurve1[FSIO_CURVE_16]; + /** + * offset 2844 + */ + float fsioCurve2Bins[FSIO_CURVE_16]; + /** + * offset 2908 + */ + float fsioCurve2[FSIO_CURVE_16]; + /** + * offset 2972 + */ + float fsioCurve3Bins[FSIO_CURVE_8]; + /** + * offset 3004 + */ + float fsioCurve3[FSIO_CURVE_8]; + /** + * offset 3036 + */ + float fsioCurve4Bins[FSIO_CURVE_8]; + /** + * offset 3068 + */ + float fsioCurve4[FSIO_CURVE_8]; + /** + * offset 3100 + */ + uint8_t unusedFlexFuelSensor; + /** + * offset 3101 + */ + brain_pin_e test557pin; + /** + * offset 3102 + */ + pin_output_mode_e stepperDirectionPinMode; + /** + * offset 3103 + */ + adc_channel_e externalKnockSenseAdc; + /** + * offset 3104 + */ + brain_pin_e stepperEnablePin; + /** + * offset 3105 + */ + brain_pin_e tle8888_cs; + /** + * offset 3106 + */ + pin_output_mode_e tle8888_csPinMode; + /** + * offset 3107 + */ + brain_pin_e mc33816_cs; + /** + * Optional timing advance table for Cranking (see useSeparateAdvanceForCranking) + * offset 3108 + */ + float crankingAdvanceBins[CRANKING_ADVANCE_CURVE_SIZE]; + /** + * Optional timing advance table for Cranking (see useSeparateAdvanceForCranking) + * offset 3124 + */ + float crankingAdvance[CRANKING_ADVANCE_CURVE_SIZE]; + /** + * todo: more comments + * offset 3140 + */ + brain_pin_e servoOutputPins[SERVO_COUNT]; + /** + * This sets the RPM limit above which the fuel cut is deactivated, activating this maintains fuel flow at high RPM to help cool pistons + * offset 3148 + */ + int16_t coastingFuelCutRpmHigh; + /** + * This sets the RPM limit below which the fuel cut is deactivated, this prevents jerking or issues transitioning to idle + * offset 3150 + */ + int16_t coastingFuelCutRpmLow; + /** + * percent between 0 and 100 below which the fuel cut is deactivated, this helps low speed drivability. + * offset 3152 + */ + int16_t coastingFuelCutTps; + /** + * Fuel cutoff is deactivated below this coolant threshold. + * offset 3154 + */ + int16_t coastingFuelCutClt; + /** + * Increases PID reaction for RPM + + + + + + RUSEFI + 0 + OPEN_SR5_0.1 + RUSEFI + rusEfi + rusEfi + 19988 + + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
+ + +
+ + + + +
+ +
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+ +
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+ +
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+ +
+ + + + + +
+ +
+ + + + +
+ +
+ + + + diff --git a/firmware/config/boards/hellen/cypress/config/rusefi_config_cypress.txt b/firmware/config/boards/hellen/cypress/config/rusefi_config_cypress.txt new file mode 100644 index 0000000000..5432227d39 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/config/rusefi_config_cypress.txt @@ -0,0 +1,16 @@ + +! see "integration/rusefi_config.txt" for more details + +! all these #defines are in priority over the "default" values in rusefi_config.txt + +! see firmware/config/boards/hellen/cypress/rusefi_hw_enums.h +#define brain_pin_e_enum "NONE", "INVALID", "P00 (A_0)", "P01 (A_1)", "P02 (A_2)", "P03 (A_3)", "P04 (A_4)", "P05 (A_5)", "P06 (A_6)", "P07 (A_7)", "P08 (A_8)", "P09 (A_9)", "P0A (A_10)", "P0B (A_11)", "P0C (A_12)", "P0D (A_13)", "P0E (A_14)", "P0F (A_15)", "P10 (B_0)", "P11 (B_1)", "P12 (B_2)", "P13 (B_3)", "P14 (B_4)", "P15 (B_5)", "P16 (B_6)", "P17 (B_7)", "P18 (B_8)", "P19 (B_9)", "P1A (B_10)", "P1B (B_11)", "P1C (B_12)", "P1D (B_13)", "P1E (B_14)", "P1F (B_15)", "P20 (C_0)", "P21 (C_1)", "P22 (C_2)", "P23 (C_3)", "P24 (C_4)", "P25 (C_5)", "P26 (C_6)", "P27 (C_7)", "P28 (C_8)", "P29 (C_9)", "P2A (C_10)", "P2B (C_11)", "P2C (C_12)", "P2D (C_13)", "P2E (C_14)", "P2F (C_15)", "P30 (D_0)", "P31 (D_1)", "P32 (D_2)", "P33 (D_3)", "P34 (D_4)", "P35 (D_5)", "P36 (D_6)", "P37 (D_7)", "P38 (D_8)", "P39 (D_9)", "P3A (D_10)", "P3B (D_11)", "P3C (D_12)", "P3D (D_13)", "P3E (D_14)", "P3F (D_15)", "P40 (E_0)", "P41 (E_1)", "P42 (E_2)", "P43 (E_3)", "P44 (E_4)", "P45 (E_5)", "P46 (E_6)", "P47 (E_7)", "P48 (E_8)", "P49 (E_9)", "P4A (E_10)", "P4B (E_11)", "P4C (E_12)", "P4D (E_13)", "P4E (E_14)", "P4F (E_15)", "P50 (F_0)", "P51 (F_1)", "P52 (F_2)", "P53 (F_3)", "P54 (F_4)", "P55 (F_5)", "P56 (F_6)", "P57 (F_7)", "P58 (F_8)", "P59 (F_9)", "P5A (F_10)", "P5B (F_11)", "P5C (F_12)", "P5D (F_13)", "P5E (F_14)", "P5F (F_15)", "P70 (G_0)", "P71 (G_1)", "P72 (G_2)", "P73 (G_3)", "P74 (G_4)", "P75 (G_5)", "P76 (G_6)", "P77 (G_7)", "P78 (G_8)", "P79 (G_9)", "P7A (G_10)", "P7B (G_11)", "P7C (G_12)", "P7D (G_13)", "P7E (G_14)", "P7F (G_15)", "PA0 (H_0)", "PA1 (H_1)", "PA2 (H_2)", "PA3 (H_3)", "PA4 (H_4)", "PA5 (H_5)", "PA6 (H_6)", "PA7 (H_7)", "PA8 (H_8)", "PA9 (H_9)", "PAA (H_10)", "PAB (H_11)", "PAC (H_12)", "PAD (H_13)", "PAE (H_14)", "PAF (H_15)", "PB0 (I_0)", "PB1 (I_1)", "PB2 (I_2)", "PB3 (I_3)", "PB4 (I_4)", "PB5 (I_5)", "PB6 (I_6)", "PB7 (I_7)", "PB8 (I_8)", "PB9 (I_9)", "PBA (I_10)", "PBB (I_11)", "PBC (I_12)", "PBD (I_13)", "PBE (I_14)", "PBF (I_15)", "PC0 (J_0)", "PC1 (J_1)", "PC2 (J_2)", "PC3 (J_3)", "PC4 (J_4)", "PC5 (J_5)", "PC6 (J_6)", "PC7 (J_7)", "PC8 (J_8)", "PC9 (J_9)", "PCA (J_10)", "PCB (J_11)", "PCC (J_12)", "PCD (J_13)", "PCE (J_14)", "PCF (J_15)", "PF0 (K_0)", "PF1 (K_1)", "PF2 (K_2)", "PF3 (K_3)", "PF4 (K_4)", "PF5 (K_5)", "PF6 (K_6)", "PF7 (K_7)", "PF8 (K_8)", "PF9 (K_9)", "PFA (K_10)", "PFB (K_11)", "PFC (K_12)", "PFD (K_13)", "PFE (K_14)", "PFF (K_15)", "DRV8860_1", "DRV8860_2", "DRV8860_3", "DRV8860_4", "DRV8860_5", "DRV8860_6", "DRV8860_7", "DRV8860_8", "DRV8860_9", "DRV8860_10", "DRV8860_11", "DRV8860_12", "DRV8860_13", "DRV8860_14", "DRV8860_15", "DRV8860_16", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID" + +! Based on Cypress S6E2Cx pinout (144-pin package) +#define brain_input_pin_e_enum "NONE", "INVALID", "P00 (A_0)", "P01 (A_1)", "P02 (A_2)", "P03 (A_3)", "P04 (A_4)", "P05 (A_5)", "P06 (A_6)", "P07 (A_7)", "P08 (A_8)", "P09 (A_9)", "P0A (A_10)", "P0B (A_11)", "P0C (A_12)", "P0D (A_13)", "P0E (A_14)", "P0F (A_15)", "P10 (B_0)", "P11 (B_1)", "P12 (B_2)", "P13 (B_3)", "P14 (B_4)", "P15 (B_5)", "P16 (B_6)", "P17 (B_7)", "P18 (B_8)", "P19 (B_9)", "P1A (B_10)", "P1B (B_11)", "P1C (B_12)", "P1D (B_13)", "P1E (B_14)", "P1F (B_15)", "P20 (C_0)", "P21 (C_1)", "P22 (C_2)", "P23 (C_3)", "P24 (C_4)", "P25 (C_5)", "P26 (C_6)", "P27 (C_7)", "P28 (C_8)", "P29 (C_9)", "P2A (C_10)", "P2B (C_11)", "P2C (C_12)", "P2D (C_13)", "P2E (C_14)", "P2F (C_15)", "P30 (D_0)", "P31 (D_1)", "P32 (D_2)", "P33 (D_3)", "P34 (D_4)", "P35 (D_5)", "P36 (D_6)", "P37 (D_7)", "P38 (D_8)", "P39 (D_9)", "P3A (D_10)", "P3B (D_11)", "P3C (D_12)", "P3D (D_13)", "P3E (D_14)", "P3F (D_15)", "P40 (E_0)", "P41 (E_1)", "P42 (E_2)", "P43 (E_3)", "P44 (E_4)", "P45 (E_5)", "P46 (E_6)", "P47 (E_7)", "P48 (E_8)", "P49 (E_9)", "P4A (E_10)", "P4B (E_11)", "P4C (E_12)", "P4D (E_13)", "P4E (E_14)", "P4F (E_15)", "P50 (F_0)", "P51 (F_1)", "P52 (F_2)", "P53 (F_3)", "P54 (F_4)", "P55 (F_5)", "P56 (F_6)", "P57 (F_7)", "P58 (F_8)", "P59 (F_9)", "P5A (F_10)", "P5B (F_11)", "P5C (F_12)", "P5D (F_13)", "P5E (F_14)", "P5F (F_15)", "P70 (G_0)", "P71 (G_1)", "P72 (G_2)", "P73 (G_3)", "P74 (G_4)", "P75 (G_5)", "P76 (G_6)", "P77 (G_7)", "P78 (G_8)", "P79 (G_9)", "P7A (G_10)", "P7B (G_11)", "P7C (G_12)", "P7D (G_13)", "P7E (G_14)", "P7F (G_15)", "PA0 (H_0)", "PA1 (H_1)", "PA2 (H_2)", "PA3 (H_3)", "PA4 (H_4)", "PA5 (H_5)", "PA6 (H_6)", "PA7 (H_7)", "PA8 (H_8)", "PA9 (H_9)", "PAA (H_10)", "PAB (H_11)", "PAC (H_12)", "PAD (H_13)", "PAE (H_14)", "PAF (H_15)", "PB0 (I_0)", "PB1 (I_1)", "PB2 (I_2)", "PB3 (I_3)", "PB4 (I_4)", "PB5 (I_5)", "PB6 (I_6)", "PB7 (I_7)", "PB8 (I_8)", "PB9 (I_9)", "PBA (I_10)", "PBB (I_11)", "PBC (I_12)", "PBD (I_13)", "PBE (I_14)", "PBF (I_15)", "PC0 (J_0)", "PC1 (J_1)", "PC2 (J_2)", "PC3 (J_3)", "PC4 (J_4)", "PC5 (J_5)", "PC6 (J_6)", "PC7 (J_7)", "PC8 (J_8)", "PC9 (J_9)", "PCA (J_10)", "PCB (J_11)", "PCC (J_12)", "PCD (J_13)", "PCE (J_14)", "PCF (J_15)", "PF0 (K_0)", "PF1 (K_1)", "PF2 (K_2)", "PF3 (K_3)", "PF4 (K_4)", "PF5 (K_5)", "PF6 (K_6)", "PF7 (K_7)", "PF8 (K_8)", "PF9 (K_9)", "PFA (K_10)", "PFB (K_11)", "PFC (K_12)", "PFD (K_13)", "PFE (K_14)", "PFF (K_15)", "DRV8860_1", "DRV8860_2", "DRV8860_3", "DRV8860_4", "DRV8860_5", "DRV8860_6", "DRV8860_7", "DRV8860_8", "DRV8860_9", "DRV8860_10", "DRV8860_11", "DRV8860_12", "DRV8860_13", "DRV8860_14", "DRV8860_15", "DRV8860_16", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID" +#define switch_input_pin_e_enum "NONE", "INVALID", "P00 (A_0)", "P01 (A_1)", "P02 (A_2)", "P03 (A_3)", "P04 (A_4)", "P05 (A_5)", "P06 (A_6)", "P07 (A_7)", "P08 (A_8)", "P09 (A_9)", "P0A (A_10)", "P0B (A_11)", "P0C (A_12)", "P0D (A_13)", "P0E (A_14)", "P0F (A_15)", "P10 (B_0)", "P11 (B_1)", "P12 (B_2)", "P13 (B_3)", "P14 (B_4)", "P15 (B_5)", "P16 (B_6)", "P17 (B_7)", "P18 (B_8)", "P19 (B_9)", "P1A (B_10)", "P1B (B_11)", "P1C (B_12)", "P1D (B_13)", "P1E (B_14)", "P1F (B_15)", "P20 (C_0)", "P21 (C_1)", "P22 (C_2)", "P23 (C_3)", "P24 (C_4)", "P25 (C_5)", "P26 (C_6)", "P27 (C_7)", "P28 (C_8)", "P29 (C_9)", "P2A (C_10)", "P2B (C_11)", "P2C (C_12)", "P2D (C_13)", "P2E (C_14)", "P2F (C_15)", "P30 (D_0)", "P31 (D_1)", "P32 (D_2)", "P33 (D_3)", "P34 (D_4)", "P35 (D_5)", "P36 (D_6)", "P37 (D_7)", "P38 (D_8)", "P39 (D_9)", "P3A (D_10)", "P3B (D_11)", "P3C (D_12)", "P3D (D_13)", "P3E (D_14)", "P3F (D_15)", "P40 (E_0)", "P41 (E_1)", "P42 (E_2)", "P43 (E_3)", "P44 (E_4)", "P45 (E_5)", "P46 (E_6)", "P47 (E_7)", "P48 (E_8)", "P49 (E_9)", "P4A (E_10)", "P4B (E_11)", "P4C (E_12)", "P4D (E_13)", "P4E (E_14)", "P4F (E_15)", "P50 (F_0)", "P51 (F_1)", "P52 (F_2)", "P53 (F_3)", "P54 (F_4)", "P55 (F_5)", "P56 (F_6)", "P57 (F_7)", "P58 (F_8)", "P59 (F_9)", "P5A (F_10)", "P5B (F_11)", "P5C (F_12)", "P5D (F_13)", "P5E (F_14)", "P5F (F_15)", "P70 (G_0)", "P71 (G_1)", "P72 (G_2)", "P73 (G_3)", "P74 (G_4)", "P75 (G_5)", "P76 (G_6)", "P77 (G_7)", "P78 (G_8)", "P79 (G_9)", "P7A (G_10)", "P7B (G_11)", "P7C (G_12)", "P7D (G_13)", "P7E (G_14)", "P7F (G_15)", "PA0 (H_0)", "PA1 (H_1)", "PA2 (H_2)", "PA3 (H_3)", "PA4 (H_4)", "PA5 (H_5)", "PA6 (H_6)", "PA7 (H_7)", "PA8 (H_8)", "PA9 (H_9)", "PAA (H_10)", "PAB (H_11)", "PAC (H_12)", "PAD (H_13)", "PAE (H_14)", "PAF (H_15)", "PB0 (I_0)", "PB1 (I_1)", "PB2 (I_2)", "PB3 (I_3)", "PB4 (I_4)", "PB5 (I_5)", "PB6 (I_6)", "PB7 (I_7)", "PB8 (I_8)", "PB9 (I_9)", "PBA (I_10)", "PBB (I_11)", "PBC (I_12)", "PBD (I_13)", "PBE (I_14)", "PBF (I_15)", "PC0 (J_0)", "PC1 (J_1)", "PC2 (J_2)", "PC3 (J_3)", "PC4 (J_4)", "PC5 (J_5)", "PC6 (J_6)", "PC7 (J_7)", "PC8 (J_8)", "PC9 (J_9)", "PCA (J_10)", "PCB (J_11)", "PCC (J_12)", "PCD (J_13)", "PCE (J_14)", "PCF (J_15)", "PF0 (K_0)", "PF1 (K_1)", "PF2 (K_2)", "PF3 (K_3)", "PF4 (K_4)", "PF5 (K_5)", "PF6 (K_6)", "PF7 (K_7)", "PF8 (K_8)", "PF9 (K_9)", "PFA (K_10)", "PFB (K_11)", "PFC (K_12)", "PFD (K_13)", "PFE (K_14)", "PFF (K_15)", "DRV8860_1", "DRV8860_2", "DRV8860_3", "DRV8860_4", "DRV8860_5", "DRV8860_6", "DRV8860_7", "DRV8860_8", "DRV8860_9", "DRV8860_10", "DRV8860_11", "DRV8860_12", "DRV8860_13", "DRV8860_14", "DRV8860_15", "DRV8860_16", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID" +#define output_pin_e_enum "NONE", "INVALID", "P00 (A_0)", "P01 (A_1)", "P02 (A_2)", "P03 (A_3)", "P04 (A_4)", "P05 (A_5)", "P06 (A_6)", "P07 (A_7)", "P08 (A_8)", "P09 (A_9)", "P0A (A_10)", "P0B (A_11)", "P0C (A_12)", "P0D (A_13)", "P0E (A_14)", "P0F (A_15)", "P10 (B_0)", "P11 (B_1)", "P12 (B_2)", "P13 (B_3)", "P14 (B_4)", "P15 (B_5)", "P16 (B_6)", "P17 (B_7)", "P18 (B_8)", "P19 (B_9)", "P1A (B_10)", "P1B (B_11)", "P1C (B_12)", "P1D (B_13)", "P1E (B_14)", "P1F (B_15)", "P20 (C_0)", "P21 (C_1)", "P22 (C_2)", "P23 (C_3)", "P24 (C_4)", "P25 (C_5)", "P26 (C_6)", "P27 (C_7)", "P28 (C_8)", "P29 (C_9)", "P2A (C_10)", "P2B (C_11)", "P2C (C_12)", "P2D (C_13)", "P2E (C_14)", "P2F (C_15)", "P30 (D_0)", "P31 (D_1)", "P32 (D_2)", "P33 (D_3)", "P34 (D_4)", "P35 (D_5)", "P36 (D_6)", "P37 (D_7)", "P38 (D_8)", "P39 (D_9)", "P3A (D_10)", "P3B (D_11)", "P3C (D_12)", "P3D (D_13)", "P3E (D_14)", "P3F (D_15)", "P40 (E_0)", "P41 (E_1)", "P42 (E_2)", "P43 (E_3)", "P44 (E_4)", "P45 (E_5)", "P46 (E_6)", "P47 (E_7)", "P48 (E_8)", "P49 (E_9)", "P4A (E_10)", "P4B (E_11)", "P4C (E_12)", "P4D (E_13)", "P4E (E_14)", "P4F (E_15)", "P50 (F_0)", "P51 (F_1)", "P52 (F_2)", "P53 (F_3)", "P54 (F_4)", "P55 (F_5)", "P56 (F_6)", "P57 (F_7)", "P58 (F_8)", "P59 (F_9)", "P5A (F_10)", "P5B (F_11)", "P5C (F_12)", "P5D (F_13)", "P5E (F_14)", "P5F (F_15)", "P70 (G_0)", "P71 (G_1)", "P72 (G_2)", "P73 (G_3)", "P74 (G_4)", "P75 (G_5)", "P76 (G_6)", "P77 (G_7)", "P78 (G_8)", "P79 (G_9)", "P7A (G_10)", "P7B (G_11)", "P7C (G_12)", "P7D (G_13)", "P7E (G_14)", "P7F (G_15)", "PA0 (H_0)", "PA1 (H_1)", "PA2 (H_2)", "PA3 (H_3)", "PA4 (H_4)", "PA5 (H_5)", "PA6 (H_6)", "PA7 (H_7)", "PA8 (H_8)", "PA9 (H_9)", "PAA (H_10)", "PAB (H_11)", "PAC (H_12)", "PAD (H_13)", "PAE (H_14)", "PAF (H_15)", "PB0 (I_0)", "PB1 (I_1)", "PB2 (I_2)", "PB3 (I_3)", "PB4 (I_4)", "PB5 (I_5)", "PB6 (I_6)", "PB7 (I_7)", "PB8 (I_8)", "PB9 (I_9)", "PBA (I_10)", "PBB (I_11)", "PBC (I_12)", "PBD (I_13)", "PBE (I_14)", "PBF (I_15)", "PC0 (J_0)", "PC1 (J_1)", "PC2 (J_2)", "PC3 (J_3)", "PC4 (J_4)", "PC5 (J_5)", "PC6 (J_6)", "PC7 (J_7)", "PC8 (J_8)", "PC9 (J_9)", "PCA (J_10)", "PCB (J_11)", "PCC (J_12)", "PCD (J_13)", "PCE (J_14)", "PCF (J_15)", "PF0 (K_0)", "PF1 (K_1)", "PF2 (K_2)", "PF3 (K_3)", "PF4 (K_4)", "PF5 (K_5)", "PF6 (K_6)", "PF7 (K_7)", "PF8 (K_8)", "PF9 (K_9)", "PFA (K_10)", "PFB (K_11)", "PFC (K_12)", "PFD (K_13)", "PFE (K_14)", "PFF (K_15)", "DRV8860_1", "DRV8860_2", "DRV8860_3", "DRV8860_4", "DRV8860_5", "DRV8860_6", "DRV8860_7", "DRV8860_8", "DRV8860_9", "DRV8860_10", "DRV8860_11", "DRV8860_12", "DRV8860_13", "DRV8860_14", "DRV8860_15", "DRV8860_16", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID" +#define adc_channel_e_enum "P10 (B_0)", "P11 (B_1)", "P12 (B_2)", "P13 (B_3)", "P14 (B_4)", "P15 (B_5)", "P16 (B_6)", "P17 (B_7)", "P18 (B_8)", "P19 (B_9)", "P1A (B_10)", "P1B (B_11)", "P1C (B_12)", "P1D (B_13)", "P1E (B_14)", "P1F (B_15)", "INVALID", "INVALID", "INVALID", "INVALID", "INVALID", "INVALID", "INVALID", "INVALID", "P2A (C_10)", "P29 (C_9)", "P28 (C_8)", "P27 (C_7)", "P25 (C_5)", "P24 (C_4)", "P23 (C_3)", "P22 (C_2)", "Disabled", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID", "INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID","INVALID" + +! = (ADC_MAX_CHANNELS_COUNT + 1) +#define HW_MAX_ADC_INDEX 33 diff --git a/firmware/config/boards/hellen/cypress/config/tunerstudio/cypress_prefix.txt b/firmware/config/boards/hellen/cypress/config/tunerstudio/cypress_prefix.txt new file mode 100644 index 0000000000..e69de29bb2 diff --git a/firmware/config/boards/hellen/cypress/efifeatures.h b/firmware/config/boards/hellen/cypress/efifeatures.h new file mode 100644 index 0000000000..f700c1276e --- /dev/null +++ b/firmware/config/boards/hellen/cypress/efifeatures.h @@ -0,0 +1,436 @@ +/** + * @file efifeatures.h + * + * @brief In this header we can configure which firmware modules are used. + * + * @date Jan 27, 2020 + * @author Andrey Belomutskiy, (c) 2012-2020 + * @author andreika + */ + +#ifndef EFIFEATURES_H_ +#define EFIFEATURES_H_ + +#define EFI_GPIO_HARDWARE TRUE + +#define EFI_FSIO TRUE + +#define EFI_CDM_INTEGRATION FALSE + +#define EFI_TOOTH_LOGGER FALSE + +#define EFI_PWM_TESTER FALSE + +#define HAL_USE_USB_MSD FALSE + +#define EFI_ENABLE_CRITICAL_ENGINE_STOP FALSE +#define EFI_ENABLE_ENGINE_WARNING TRUE + +#define EFI_USE_CCM FALSE + +/** + * if you have a 60-2 trigger, or if you just want better performance, you + * probably want EFI_ENABLE_ASSERTS to be FALSE. Also you would probably want to FALSE + * CH_DBG_ENABLE_CHECKS + * CH_DBG_ENABLE_ASSERTS + * in chconf.h + * + */ +#if !defined(EFI_ENABLE_ASSERTS) || defined(__DOXYGEN__) + #define EFI_ENABLE_ASSERTS FALSE +#endif /* EFI_ENABLE_ASSERTS */ + +#if !defined(EFI_ENABLE_MOCK_ADC) || defined(__DOXYGEN__) + #define EFI_ENABLE_MOCK_ADC FALSE +#endif /* EFI_ENABLE_MOCK_ADC */ + + +#define EFI_TEXT_LOGGING TRUE + +//#define EFI_UART_ECHO_TEST_MODE FALSE + +//#define EFI_USE_UART_FOR_CONSOLE FALSE + +#define EFI_CONSOLE_NO_THREAD + +/** + * Build-in logic analyzer support. Logic analyzer viewer is one of the java console panes. + */ +#ifndef EFI_LOGIC_ANALYZER +#define EFI_LOGIC_ANALYZER FALSE +#endif + +#ifndef EFI_ICU_INPUTS +#define EFI_ICU_INPUTS FALSE +#endif + +/** + * TunerStudio support. + */ +#define EFI_TUNER_STUDIO TRUE + +#undef EFI_NO_CONFIG_WORKING_COPY + +/** + * Bluetooth UART setup support. + */ +#define EFI_BLUETOOTH_SETUP FALSE + +/** + * TunerStudio debug output + */ +#define EFI_TUNER_STUDIO_VERBOSE FALSE + +#define EFI_DEFAILED_LOGGING FALSE + +/** + * Dev console support. + */ +#define EFI_CLI_SUPPORT FALSE + +#define EFI_RTC FALSE + +#define EFI_ALTERNATOR_CONTROL FALSE + +#define EFI_AUX_PID FALSE + +#define EFI_SIGNAL_EXECUTOR_SLEEP FALSE +#define EFI_SIGNAL_EXECUTOR_ONE_TIMER TRUE +#define EFI_SIGNAL_EXECUTOR_HW_TIMER FALSE + +#define FUEL_MATH_EXTREME_LOGGING FALSE + +#define SPARK_EXTREME_LOGGING FALSE + +#define TRIGGER_EXTREME_LOGGING FALSE + +#define EFI_INTERNAL_FLASH TRUE + +/** + * Flex Non Volatile Memory is faster than flash + * It also has smaller pages so it takes less time to erase + * + * There is no remote access to FlexNVM meaning that we cannot erase settings externally + */ + +// Dual-Flash version: +//#define FLASH_ADDR 0x200F8000 +// todo: find other location for 1Mb Flash chip versions? +//#define FLASH_ADDR_SECOND_COPY 0x20100000 + +// Main-Flash version: +#define FLASH_ADDR 0x000E0000 +#define FLASH_ADDR_SECOND_COPY 0x000C0000 + +#define BACKUP_FLASH_ADDR 0x00406000 +#define BACKUP_FLASH_SIZE 0x2000 // 8k + +/** + * Usually you need shaft position input, but maybe you do not need it? + */ +#ifndef EFI_SHAFT_POSITION_INPUT +#define EFI_SHAFT_POSITION_INPUT TRUE +#endif + +/** + * Maybe we are just sniffing what's going on? + */ +#define EFI_ENGINE_CONTROL TRUE + +#define EFI_SPEED_DENSITY TRUE + +/** + * MCP42010 digital potentiometer support. This could be useful if you are stimulating some + * stock ECU + */ +//#define EFI_POTENTIOMETER FALSE +#define EFI_POTENTIOMETER FALSE + +#define EFI_ANALOG_SENSORS TRUE + +#ifndef EFI_MAX_31855 +#define EFI_MAX_31855 FALSE +#endif + +#define EFI_MCP_3208 FALSE + +#ifndef EFI_HIP_9011 +#define EFI_HIP_9011 FALSE +#endif + +#ifndef EFI_CJ125 +#define EFI_CJ125 FALSE +#endif + +#if !defined(EFI_MEMS) || defined(__DOXYGEN__) + #define EFI_MEMS FALSE +#endif + +#define EFI_INTERNAL_ADC TRUE + +#define EFI_NARROW_EGO_AVERAGING FALSE + +#define EFI_DENSO_ADC FALSE + +#ifndef EFI_CAN_SUPPORT +#define EFI_CAN_SUPPORT FALSE +#endif + +#define EFI_HD44780_LCD FALSE +#define EFI_LCD FALSE + +#define EFI_IDLE_CONTROL TRUE + +#define EFI_IDLE_PID_CIC FALSE + +/** + * Control the main power relay based on measured ignition voltage (Vbatt) + */ +#define EFI_MAIN_RELAY_CONTROL TRUE + +#ifndef EFI_PWM +#define EFI_PWM FALSE +#endif + +#define EFI_VEHICLE_SPEED FALSE + +#define EFI_FUEL_PUMP TRUE + +#define EFI_ENGINE_EMULATOR TRUE + +#define EFI_EMULATE_POSITION_SENSORS TRUE + +/** + * This macros is used to hide pieces of the code from unit tests, so it only makes sense in folders exposed to the tests project. + * This macros is NOT about taking out logging in general. + */ +#define EFI_PROD_CODE TRUE + +/** + * Do we need file logging (like SD card) logic? + */ +#ifndef EFI_FILE_LOGGING +#define EFI_FILE_LOGGING FALSE +#endif + + +/** + * While we embed multiple PnP configurations into the same firmware binary, these marcoses give us control + * over which configurations go into the binary + */ +#define EFI_SUPPORT_DODGE_NEON FALSE +#define EFI_SUPPORT_FORD_ASPIRE FALSE +#define EFI_SUPPORT_FORD_FIESTA FALSE +#define EFI_SUPPORT_NISSAN_PRIMERA FALSE +#define EFI_SUPPORT_1995_FORD_INLINE_6 FALSE + +#define EFI_ENGINE_SNIFFER TRUE + +#define EFI_HISTOGRAMS FALSE +#define EFI_SENSOR_CHART FALSE + +#define EFI_PERF_METRICS FALSE + +/** + * Do we need GPS logic? + */ +#define EFI_UART_GPS FALSE + +#define EFI_SERVO FALSE + +#define EFI_ELECTRONIC_THROTTLE_BODY FALSE +//#define EFI_ELECTRONIC_THROTTLE_BODY FALSE + +#define EFI_HAS_RESET FALSE + +/** + * Do we need Malfunction Indicator blinking logic? + */ +#define EFI_MALFUNCTION_INDICATOR FALSE +//#define EFI_MALFUNCTION_INDICATOR FALSE + +#define CONSOLE_MAX_ACTIONS 180 +//#define EFI_DISABLE_CONSOLE_ACTIONS TRUE + +#define EFI_MAP_AVERAGING TRUE + +#define EFI_INTERNAL_FAST_ADC_GPT &GPTD2 +#define ADC_MAX_CHANNELS_COUNT 32 + +#define EFI_FASTER_UNIFORM_ADC TRUE +#define ADC_BUF_NUM_AVG 4 +#define ADC_BUF_DEPTH_FAST 1 + +//ADC freq = ~40kHz +#define GPT_FREQ_FAST 400000 /* PWM clock frequency. */ +#define GPT_PERIOD_FAST 10 /* PWM period (in PWM ticks). */ + +#define EFI_SPI1_AF PAL_MODE_ALTERNATIVE_SPI + +#define EFI_SPI2_AF PAL_MODE_ALTERNATIVE_SPI + +/** + * This section is for right-side center SPI + */ + +#define EFI_SPI3_AF PAL_MODE_ALTERNATIVE_SPI + +#define EFI_I2C_SCL_BRAIN_PIN GPIOB_6 + +#define EFI_I2C_SDA_BRAIN_PIN GPIOB_7 +#define EFI_I2C_AF 4 + +/** + * Patched version of ChibiOS/RT support extra details in the system error messages + */ +#define EFI_CUSTOM_PANIC_METHOD FALSE + +#define ADC_CHANNEL_VREF ADC_CHANNEL_IN14 + +/** + * Use 'HAL_USE_UART' DMA-mode driver instead of 'HAL_USE_SERIAL' + * + * See also + * STM32_SERIAL_USE_USARTx + * STM32_UART_USE_USARTx + * in mcuconf.h + */ +#define TS_UART_DMA_MODE FALSE +#define TS_UART_MODE FALSE +#define PRIMARY_UART_DMA_MODE FALSE + +#undef TS_UART_DEVICE +#undef TS_SERIAL_DEVICE +//#define TS_USB_DEVICE SDU1 +#undef TS_USB_DEVICE + +#define TS_CAN_DEVICE CAND1 +#define TS_CAN_AF PAL_MODE_ALTERNATIVE_CAN +#define TS_CAN_DEVICE_SHORT_PACKETS_IN_ONE_FRAME + +#undef EFI_CONSOLE_SERIAL_DEVICE +#undef EFI_CONSOLE_UART_DEVICE + +#define EFI_USB_SERIAL TRUE +#define EFI_CONSOLE_USB_DEVICE SDU1 + +#define SERIAL_USB_DRIVER BaseChannel + +#define EFI_CONSOLE_TX_PORT GPIOA +#define EFI_CONSOLE_TX_PIN 10 +#define EFI_CONSOLE_RX_PORT GPIOA +#define EFI_CONSOLE_RX_PIN 11 +#define EFI_CONSOLE_AF 3 + +#define TS_SERIAL_AF 2 + +#undef SERIAL_SPEED +#define SERIAL_SPEED 115200 + +//#define SR5_WRITE_TIMEOUT TIME_MS2I(3000) +//#define SR5_READ_TIMEOUT TIME_MS2I(3000) + +#define HAL_TRIGGER_USE_PAL FALSE +#define HAL_TRIGGER_USE_ADC TRUE + +//#define EFI_COMP_PRIMARY_DEVICE (&COMPD3) +//#define EFI_COMP_TRIGGER_CHANNEL 6 // =E7 +//#define EFI_TRIGGER_DEBUG_BLINK TRUE +//#define EFI_TRIGGER_COMP_ADAPTIVE_HYSTERESIS TRUE + +// LED1 = GPIOJ_15 +// LED2 = GPIOJ_0 +// LED3 = GPIOJ_12 +// LED4 = GPIOA_0 + +#define LED_WARNING_BRAIN_PIN GPIOA_0 + +#define LED_ERROR_BRAIN_PIN GPIOJ_15 +#define LED_ERROR_BRAIN_PIN_MODE INVERTED_OUTPUT + +#define EFI_WARNING_LED FALSE + +#define EFI_UNIT_TEST FALSE + +#undef CONSOLE_MODE_SWITCH_PORT +#undef CONFIG_RESET_SWITCH_PORT + +/** + * This is the size of the MemoryStream used by chvprintf + */ +#define INTERMEDIATE_LOGGING_BUFFER_SIZE 2000 +#define STATUS_LOGGING_BUFFER_SIZE 1800 +#define SETTINGS_LOGGING_BUFFER_SIZE 1000 +#define DL_OUTPUT_BUFFER 6500 + +//#define UTILITY_THREAD_STACK_SIZE 270 /*400*/ + +//#define CONSOLE_THREAD_STACK_SIZE UTILITY_THREAD_STACK_SIZE + +#define BOARD_EXT_GPIOCHIPS 1 + +#define BOARD_TLE6240_COUNT 0 +#define BOARD_MC33972_COUNT 0 +#define BOARD_TLE8888_COUNT 0 +#define BOARD_DRV8860_COUNT 1 + +// todo: move this outside of efifeatures.h +#define BOARD_EXT_PINREPOPINS 24 + +#define DRV8860_SS_PORT GPIOH +#define DRV8860_SS_PAD 11U +#define DRV8860_RESET_PORT NULL +#define DRV8860_RESET_PAD 0 +#define DRV8860_DIRECT_IO \ + /* IN1..4 grounded */ \ + [0] = {.port = NULL, .pad = 0}, \ + [1] = {.port = NULL, .pad = 0}, \ + [2] = {.port = NULL, .pad = 0}, \ + [3] = {.port = NULL, .pad = 0}, \ + /* IN9..12 */ \ + [4] = {.port = NULL, .pad = 0}, \ + [5] = {.port = NULL, .pad = 0}, \ + [6] = {.port = NULL, .pad = 0}, \ + [7] = {.port = NULL, .pad = 0}, + +#define EFI_BOSCH_YAW FALSE +#define ADC_SNIFFER FALSE + +#define GPTDEVICE GPTD1 + +#define EFI_BOARD_TEST FALSE +#define EFI_JOYSTICK FALSE +#define EFI_ENGINE_AUDI_AAN FALSE +#define EFI_ENGINE_SNOW_BLOWER FALSE +#define DEBUG_FUEL FALSE +#define EFI_UART_ECHO_TEST_MODE FALSE +#define EXTREME_TERM_LOGGING FALSE +#define EFI_PRINTF_FUEL_DETAILS FALSE + +#define EFI_SIMULATOR FALSE + +#define RAM_UNUSED_SIZE 1 +#define CCM_UNUSED_SIZE 1 + +#define EFI_PRINT_ERRORS_AS_WARNINGS TRUE +//#define EFI_PRINT_MESSAGES_TO_TERMINAL TRUE + +//#define EFI_ACTIVE_CONFIGURATION_IN_FLASH (FLASH_ADDR + offsetof(persistent_config_container_s, persistentConfiguration.engineConfiguration)) + +//#define PWM_PHASE_MAX_COUNT 122 + +//!!!!!!!!!!!!!!!!!!!!!! +#define debugLog(fmt,...) { \ + extern int __debugEnabled; \ + if (__debugEnabled) { \ + extern SERIAL_USB_DRIVER EFI_CONSOLE_USB_DEVICE; \ + extern char __debugBuffer[200]; \ + chsnprintf(__debugBuffer, sizeof(__debugBuffer), fmt, ##__VA_ARGS__); \ + chnWriteTimeout(&EFI_CONSOLE_USB_DEVICE, (const uint8_t *)__debugBuffer, strlen(__debugBuffer), TIME_MS2I(1000)); \ + chThdSleepMilliseconds(20); \ + } \ +} + + + +#endif /* EFIFEATURES_H_ */ diff --git a/firmware/config/boards/hellen/cypress/halconf.h b/firmware/config/boards/hellen/cypress/halconf.h new file mode 100644 index 0000000000..8f1e7bf936 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/halconf.h @@ -0,0 +1,416 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +// Warning! This is used for Hellen-cypress board! +#define HAL_USE_PAL_POWER_PINS TRUE + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC TRUE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN TRUE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT TRUE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE/*TRUE*/ +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE/*TRUE*/ +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the Comparator subsystem. + */ +#if !defined(HAL_USE_COMP) || defined(__DOXYGEN__) +#define HAL_USE_COMP FALSE +#endif + + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS TRUE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT TRUE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE FALSE /* TRUE */ +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_LLD +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/firmware/config/boards/hellen/cypress/halconf_community.h b/firmware/config/boards/hellen/cypress/halconf_community.h new file mode 100644 index 0000000000..e69de29bb2 diff --git a/firmware/config/boards/hellen/cypress/mapping.yaml b/firmware/config/boards/hellen/cypress/mapping.yaml new file mode 100644 index 0000000000..d6f6d941e3 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/mapping.yaml @@ -0,0 +1,7 @@ +# TODO if anyone would be interested + +#outputs: +# GPIOB_7: "Injector 3Z" + +#analog_inputs: +# EFI_ADC_0: "Analog 3O" \ No newline at end of file diff --git a/firmware/config/boards/hellen/cypress/mcuconf.h b/firmware/config/boards/hellen/cypress/mcuconf.h new file mode 100644 index 0000000000..028f62fb64 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/mcuconf.h @@ -0,0 +1,86 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * HAL driver system settings. + */ + +/* Select the MCU clocking mode below by enabling the appropriate block. */ +#define CYPRESS_PLL_FREQ 192000000UL // 192MHz +#define CYPRESS_CLK 8000000U // 8MHz + +#define CYPRESS_SYSCLK_FREQUENCY CYPRESS_PLL_FREQ +#define CYPRESS_PCLK1_FREQENCY (CYPRESS_PLL_FREQ / (1 << (APBC1_PSR_Val & 3))) // 48 MHz + +/* + * GPIO driver system settings. + */ +// Use this with PAL_MODE_ALTERNATE(x) +#define PAL_MODE_ALTERNATIVE_GPIO 0x0 +#define PAL_MODE_ALTERNATIVE_ANALOG 0x1 +#define PAL_MODE_ALTERNATIVE_SPI 0x2 +#define PAL_MODE_ALTERNATIVE_I2C 0x3 +#define PAL_MODE_ALTERNATIVE_UART 0x4 +#define PAL_MODE_ALTERNATIVE_CAN 0x5 +#define PAL_MODE_ALTERNATIVE_EXTINT 0x6 + +/* + * UART driver system settings. + */ +#define CYPRESS_UART_USE_UART1 FALSE/*TRUE*/ +#define CYPRESS_UART_USE_UART2 FALSE/*TRUE*/ + +/* + * GPT/PIT driver system settings. + */ +#define CYPRESS_GPT_USE_BT0_BT1 TRUE +#define CYPRESS_GPT_USE_BT2_BT3 TRUE +#define CYPRESS_GPT_USE_BT4_BT5 FALSE +#define CYPRESS_GPT_USE_BT6_BT7 FALSE + +/* + * PWM/FTM driver system settings. + */ +#define CYPRESS_PWM_USE_FTM0 FALSE +#define CYPRESS_PWM_USE_FTM1 FALSE +#define CYPRESS_PWM_USE_FTM2 FALSE +#define CYPRESS_PWM_USE_FTM3 FALSE + +/* + * SPI driver system settings. + */ +#define CYPRESS_SPI_USE_SPI0 TRUE +#define CYPRESS_SPI_SPI0_CHANNEL CSIO6 +#define CYPRESS_SPI_USE_SPI1 TRUE +#define CYPRESS_SPI_SPI1_CHANNEL CSIO7 + +/* + * ADC driver system settings. + */ +#define CYPRESS_ADC_USE_ADC0 TRUE +#define CYPRESS_ADC_USE_ADC1 TRUE +#define CYPRESS_ADC_USE_ADC2 TRUE + +/* + * CAN driver system settings. + */ +#define CYPRESS_CAN_USE_CAN0 TRUE +#define CYPRESS_CAN_USE_CAN1 FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/firmware/config/boards/hellen/cypress/pdl_user.h b/firmware/config/boards/hellen/cypress/pdl_user.h new file mode 100644 index 0000000000..16e9bcaaf6 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/pdl_user.h @@ -0,0 +1,1436 @@ +/******************************************************************************* +* \file pdl_user.h +* +* \version 1.10 +* +* \brief User settings headerfile for Peripheral Driver Library +* +******************************************************************************** +* \copyright +* Copyright 2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +* CYPRESS PROVIDES THIS SOFTWARE "AS IS" AND MAKES NO WARRANTY +* OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS SOFTWARE, +* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF +* MERCHANTABILITY, NON-INFRINGEMENT AND FITNESS FOR A PARTICULAR +* PURPOSE. +*******************************************************************************/ +#ifndef __PDL_USER_H__ +#define __PDL_USER_H__ + +#include "pdl.h" + +/******************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/** + ****************************************************************************** + ** User Defines for PDL resource activation + ** + ** Possible definitions are PDL_ON and PDL_OFF. + ** + ******************************************************************************/ +// ADC +#define PDL_PERIPHERAL_ENABLE_ADC0 PDL_ON +#define PDL_PERIPHERAL_ENABLE_ADC1 PDL_ON +#define PDL_PERIPHERAL_ENABLE_ADC2 PDL_ON + +// AES +#define PDL_PERIPHERAL_ENABLE_AES PDL_OFF + +// Base Timers +#define PDL_PERIPHERAL_ENABLE_BT0 PDL_ON +#define PDL_PERIPHERAL_ENABLE_BT1 PDL_ON +#define PDL_PERIPHERAL_ENABLE_BT2 PDL_ON +#define PDL_PERIPHERAL_ENABLE_BT3 PDL_ON +#define PDL_PERIPHERAL_ENABLE_BT4 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT5 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT6 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT7 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT8 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT9 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT10 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT11 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT12 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT13 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT14 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT15 PDL_OFF + +// Modes of Base Timers +#define PDL_PERIPHERAL_ENABLE_BT_PWM_MODE PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT_PPG_MODE PDL_OFF +#define PDL_PERIPHERAL_ENABLE_BT_RT_MODE PDL_ON +#define PDL_PERIPHERAL_ENABLE_BT_PWC_MODE PDL_OFF + +// CAN +#define PDL_PERIPHERAL_ENABLE_CAN0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_CAN1 PDL_OFF + +// CAN-FD +#define PDL_PERIPHERAL_ENABLE_CANFD0 PDL_ON +#define PDL_PERIPHERAL_ENABLE_CANFD1 PDL_OFF + +// Clock +#define PDL_PERIPHERAL_ENABLE_CLK PDL_ON + +// CR Trimming +#define PDL_PERIPHERAL_ENABLE_CR PDL_OFF + +// CRC +#define PDL_PERIPHERAL_ENABLE_CRC0 PDL_OFF + +// Clock Supervisor +#define PDL_PERIPHERAL_ENABLE_CSV PDL_OFF + +// DAC +#define PDL_PERIPHERAL_ENABLE_DAC0 PDL_OFF + +// DMA +#define PDL_PERIPHERAL_ENABLE_DMA0 PDL_ON +#define PDL_PERIPHERAL_ENABLE_DMA1 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_DMA2 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_DMA3 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_DMA4 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_DMA5 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_DMA6 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_DMA7 PDL_OFF + +// DSTC +#define PDL_PERIPHERAL_ENABLE_DSTC PDL_OFF + +// Dual Timer(s) +#define PDL_PERIPHERAL_ENABLE_DT0 PDL_OFF + +// Ethernet +// Please activate/deactivate in emac_user.h + +// External Interrupts +#define PDL_PERIPHERAL_ENABLE_EXINT0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT1 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT2 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT3 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT4 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT5 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT6 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT7 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT8 PDL_ON // P10 crank +#define PDL_PERIPHERAL_ENABLE_EXINT9 PDL_ON // P29 res_in +#define PDL_PERIPHERAL_ENABLE_EXINT10 PDL_ON // P18 cam +#define PDL_PERIPHERAL_ENABLE_EXINT11 PDL_ON // P1B aux1 +#define PDL_PERIPHERAL_ENABLE_EXINT12 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT13 PDL_ON // PC7 res2 +#define PDL_PERIPHERAL_ENABLE_EXINT14 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT15 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT16 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT17 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT18 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT19 PDL_ON // P32 drv_miso +#define PDL_PERIPHERAL_ENABLE_EXINT20 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT21 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT22 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT23 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT24 PDL_ON // P19 vss +#define PDL_PERIPHERAL_ENABLE_EXINT25 PDL_ON // P25 aux4 +#define PDL_PERIPHERAL_ENABLE_EXINT26 PDL_ON // P1E aux2 +#define PDL_PERIPHERAL_ENABLE_EXINT27 PDL_ON // P1F aux3 +#define PDL_PERIPHERAL_ENABLE_EXINT28 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT29 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT30 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_EXINT31 PDL_ON // P60 vbus_det + +// External Bus Interface +#define PDL_PERIPHERAL_ENABLE_EXTIF PDL_OFF + +// Flash routines +#define PDL_PERIPHERAL_ENABLE_MAIN_FLASH PDL_ON +#define PDL_PERIPHERAL_ENABLE_DUAL_FLASH PDL_ON +#define PDL_PERIPHERAL_ENABLE_WORK_FLASH PDL_OFF + +// GPIO header inclusion +#define PDL_PERIPHERAL_ENABLE_GPIO PDL_ON + +// Hyber Bus Interface +#define PDL_PERIPHERAL_ENABLE_HBIF PDL_OFF + +// High-Speed Quad SPI +#define PDL_PERIPHERAL_ENABLE_HSSPI0 PDL_OFF + +// I2C Slave +#define PDL_PERIPHERAL_ENABLE_I2CS0 PDL_OFF + +// ICC +#define PDL_PERIPHERAL_ENABLE_ICC0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_ICC1 PDL_OFF + +// I2S +#define PDL_PERIPHERAL_ENABLE_I2S0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_I2S1 PDL_OFF + +// I2S-Lite +#define PDL_PERIPHERAL_ENABLE_I2SL0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_I2SL1 PDL_OFF + +// LCD controller +#define PDL_PERIPHERAL_ENABLE_LCD PDL_OFF + +// LPM +#define PDL_PERIPHERAL_ENABLE_LPM PDL_OFF + +// Low Voltage Detection +#define PDL_PERIPHERAL_ENABLE_LVD PDL_OFF + +// Multi Function Serial Interfaces +#define PDL_PERIPHERAL_ENABLE_MFS0 PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS1 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS2 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS3 PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS4 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS5 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS6 PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS7 PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS8 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS9 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS10 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS11 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS12 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS13 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS14 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFS15 PDL_OFF + +// Modes of Multi Function Serial Interfaces +#define PDL_PERIPHERAL_ENABLE_MFS_UART_MODE PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS_CSIO_MODE PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS_I2C_MODE PDL_ON +#define PDL_PERIPHERAL_ENABLE_MFS_LIN_MODE PDL_ON + +// Multi Function Timer Interfaces +#define PDL_PERIPHERAL_ENABLE_MFT0_FRT PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT0_OCU PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT0_WFG PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT0_ICU PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT0_ADCMP PDL_OFF + +#define PDL_PERIPHERAL_ENABLE_MFT1_FRT PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT1_OCU PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT1_WFG PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT1_ICU PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT1_ADCMP PDL_OFF + +#define PDL_PERIPHERAL_ENABLE_MFT2_FRT PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT2_OCU PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT2_WFG PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT2_ICU PDL_OFF +#define PDL_PERIPHERAL_ENABLE_MFT2_ADCMP PDL_OFF + +// PPG +#define PDL_PERIPHERAL_ENABLE_PPG PDL_OFF + +// Programmable-CRC +#define PDL_PERIPHERAL_ENABLE_PCRC PDL_OFF + +// NMI +#define PDL_PERIPHERAL_ENABLE_NMI PDL_OFF + +// Quad Decoder +#define PDL_PERIPHERAL_ENABLE_QPRC0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_QPRC1 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_QPRC2 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_QPRC3 PDL_OFF + +// Remote Control routines +#define PDL_PERIPHERAL_ENABLE_RC0 PDL_OFF +#define PDL_PERIPHERAL_ENABLE_RC1 PDL_OFF + +// RX modes of Remote Control routines +#define PDL_PERIPHERAL_ENABLE_RCRX_SIRCS_MODE PDL_OFF +#define PDL_PERIPHERAL_ENABLE_RCRX_NEC_MODE PDL_OFF +#define PDL_PERIPHERAL_ENABLE_RCRX_CEC_MODE PDL_OFF + +// TX modes of Remote Control routines +#define PDL_PERIPHERAL_ENABLE_RCTX_CEC_MODE PDL_OFF + +// Reset Cause +#define PDL_PERIPHERAL_ENABLE_RESET PDL_OFF + +// Real Time Clock +#define PDL_PERIPHERAL_ENABLE_RTC0 PDL_OFF + +// SD +#define PDL_PERIPHERAL_ENABLE_SD0 PDL_OFF + +// Unique ID +#define PDL_PERIPHERAL_ENABLE_UID PDL_OFF + +// USB +#define PDL_PERIPHERAL_USB_ACTIVE PDL_ON +#define PDL_PERIPHERAL_ENABLE_USB0_DEVICE PDL_ON +#define PDL_PERIPHERAL_ENABLE_USB0_HOST PDL_OFF +#define PDL_PERIPHERAL_ENABLE_USB1_DEVICE PDL_OFF +#define PDL_PERIPHERAL_ENABLE_USB1_HOST PDL_OFF + +// USB Device Middle Ware +#define PDL_USBDEVICECDCCOM_ENABLED PDL_ON +#define PDL_USBDEVICEHIDCOM_ENABLED PDL_OFF +#define PDL_USBDEVICEHIDJOYSTICK_ENABLED PDL_OFF +#define PDL_USBDEVICEHIDKEYBOARD_ENABLED PDL_OFF +#define PDL_USBDEVICEHIDMOUSE_ENABLED PDL_OFF +#define PDL_USBDEVICELIBUSB_ENABLED PDL_OFF +#define PDL_USBDEVICEPRINTER_ENABLED PDL_OFF + +// USB Host Middle Ware +#define PDL_USBHOSTHIDCOM_ENABLED PDL_OFF +#define PDL_USBHOSTHIDKEYBOARD_ENABLED PDL_OFF +#define PDL_USBHOSTHIDMOUSE_ENABLED PDL_OFF +#define PDL_USBHOSTMASSSTORAGE_ENABLED PDL_OFF + +// VBAT domain +#define PDL_PERIPHERAL_ENABLE_VBAT PDL_OFF + +// Watch Counter +#define PDL_PERIPHERAL_ENABLE_WC0 PDL_OFF + +// Watchdog Timers +#define PDL_PERIPHERAL_ENABLE_HWWDG PDL_OFF +#define PDL_PERIPHERAL_ENABLE_SWWDG PDL_OFF + +/** + ****************************************************************************** + ** User Interrupt activation settings + ** + ** Possible values are PDL_INT_ACTIVE (Interrupts active) and PDL_INT_INACTIVE + ** (Interrupts deactivated) + ******************************************************************************/ +// ADC +#define PDL_INTERRUPT_ENABLE_ADC0 PDL_ON +#define PDL_INTERRUPT_ENABLE_ADC1 PDL_ON +#define PDL_INTERRUPT_ENABLE_ADC2 PDL_ON + +// Base Timers +#define PDL_INTERRUPT_ENABLE_BT0 PDL_ON +#define PDL_INTERRUPT_ENABLE_BT1 PDL_ON +#define PDL_INTERRUPT_ENABLE_BT2 PDL_ON +#define PDL_INTERRUPT_ENABLE_BT3 PDL_ON +#define PDL_INTERRUPT_ENABLE_BT4 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT5 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT6 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT7 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT8 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT9 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT10 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT11 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT12 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT13 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT14 PDL_OFF +#define PDL_INTERRUPT_ENABLE_BT15 PDL_OFF + +// CAN +#define PDL_INTERRUPT_ENABLE_CAN0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_CAN1 PDL_OFF + +// CAN-FD +#define PDL_INTERRUPT_ENABLE_CANFD0 PDL_ON +#define PDL_INTERRUPT_ENABLE_CANFD1 PDL_OFF + +// Clock +#define PDL_INTERRUPT_ENABLE_CLK PDL_OFF + +// Clock Supervisor +#define PDL_INTERRUPT_ENABLE_CSV PDL_OFF + +// DMA +#define PDL_INTERRUPT_ENABLE_DMA0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA1 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA2 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA3 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA4 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA5 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA6 PDL_OFF +#define PDL_INTERRUPT_ENABLE_DMA7 PDL_OFF + +// Dual Timer(s) +#define PDL_INTERRUPT_ENABLE_DT0 PDL_OFF + +// DSTC +#define PDL_INTERRUPT_ENABLE_DSTC PDL_OFF + +// External Interrupts (automatically set by peripheral enable) +#if (PDL_PERIPHERAL_ENABLE_EXINT0 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT0 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT0 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT1 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT1 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT1 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT2 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT2 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT2 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT3 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT3 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT3 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT4 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT4 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT4 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT5 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT5 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT5 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT6 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT6 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT6 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT7 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT7 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT7 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT8 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT8 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT8 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT9 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT9 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT9 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT10 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT10 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT10 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT11 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT11 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT11 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT12 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT12 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT12 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT13 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT13 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT13 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT14 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT14 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT14 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT15 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT15 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT15 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT16== PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT16 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT16 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT17 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT17 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT17 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT18 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT18 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT18 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT19 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT19 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT19 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT20 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT20 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT20 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT21 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT21 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT21 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT22 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT22 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT22 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT23 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT23 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT23 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT24 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT24 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT24 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT25 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT25 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT25 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT26 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT26 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT26 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT27 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT27 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT27 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT28 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT28 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT28 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT29 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT29 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT29 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT30 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT30 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT30 PDL_OFF +#endif +#if (PDL_PERIPHERAL_ENABLE_EXINT31 == PDL_ON) +#define PDL_INTERRUPT_ENABLE_EXINT31 PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_EXINT31 PDL_OFF +#endif + +// External Bus Interface +#define PDL_INTERRUPT_ENABLE_EXTIF PDL_OFF + +// Flash +#define PDL_INTERRUPT_ENABLE_FLASH PDL_ON + +// Hyper Bus Interface +#define PDL_INTERRUPT_ENABLE_HBIF PDL_OFF + +// High-Speed Quad SPI +#define PDL_INTERRUPT_ENABLE_HSSPI0 PDL_OFF + +// I2C Slave +#define PDL_INTERRUPT_ENABLE_I2CS0 PDL_OFF + +// ICC +#define PDL_INTERRUPT_ENABLE_ICC0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_ICC1 PDL_OFF + +// LCD +#define PDL_INTERRUPT_ENABLE_LCD PDL_OFF + +// Low Voltage Detection +#define PDL_INTERRUPT_ENABLE_LVD PDL_OFF + +// I2S +#define PDL_INTERRUPT_ENABLE_I2S0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_I2S1 PDL_OFF + +// I2S-Lite +#define PDL_INTERRUPT_ENABLE_I2SL0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_I2SL1 PDL_OFF + +// Multi Function Serial Interfaces +#define PDL_INTERRUPT_ENABLE_MFS0 PDL_ON +#define PDL_INTERRUPT_ENABLE_MFS1 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS2 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS3 PDL_ON +#define PDL_INTERRUPT_ENABLE_MFS4 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS5 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS6 PDL_ON +#define PDL_INTERRUPT_ENABLE_MFS7 PDL_ON +#define PDL_INTERRUPT_ENABLE_MFS8 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS9 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS10 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS11 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS12 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS13 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS14 PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFS15 PDL_OFF + +// Multi Function Timer Interfaces +#define PDL_INTERRUPT_ENABLE_MFT0_FRT PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT0_OCU PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT0_WFG PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT0_ICU PDL_OFF + +#define PDL_INTERRUPT_ENABLE_MFT1_FRT PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT1_OCU PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT1_WFG PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT1_ICU PDL_OFF + +#define PDL_INTERRUPT_ENABLE_MFT2_FRT PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT2_OCU PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT2_WFG PDL_OFF +#define PDL_INTERRUPT_ENABLE_MFT2_ICU PDL_OFF + +// NMI +#if (PDL_PERIPHERAL_ENABLE_NMI== PDL_ON) +#define PDL_INTERRUPT_ENABLE_NMI PDL_ON +#else +#define PDL_INTERRUPT_ENABLE_NMI PDL_OFF +#endif + +// Programmable-CRC +#define PDL_INTERRUPT_ENABLE_PCRC PDL_OFF + +// PPG +#define PDL_INTERRUPT_ENABLE_PPG PDL_OFF + +// Quad Decoder +#define PDL_INTERRUPT_ENABLE_QPRC0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_QPRC1 PDL_OFF +#define PDL_INTERRUPT_ENABLE_QPRC2 PDL_OFF +#define PDL_INTERRUPT_ENABLE_QPRC3 PDL_OFF + +// Real Time Clock +#define PDL_INTERRUPT_ENABLE_RTC0 PDL_OFF + +// Remote Control routines +#define PDL_INTERRUPT_ENABLE_RC0 PDL_OFF +#define PDL_INTERRUPT_ENABLE_RC1 PDL_OFF + +// SD Host +#define PDL_INTERRUPT_ENABLE_SD0 PDL_OFF + +// USB +#define PDL_INTERRUPT_ENABLE_USB0_DEVICE PDL_ON +#define PDL_INTERRUPT_ENABLE_USB0_HOST PDL_OFF +#define PDL_INTERRUPT_ENABLE_USB1_DEVICE PDL_OFF +#define PDL_INTERRUPT_ENABLE_USB1_HOST PDL_OFF + +// Watch Counter +#define PDL_INTERRUPT_ENABLE_WC0 PDL_OFF + +// Watchdog Timers +#define PDL_INTERRUPT_ENABLE_HWWDG PDL_OFF +#define PDL_INTERRUPT_ENABLE_SWWDG PDL_OFF + +/** + ****************************************************************************** + ** User DSTC enable settings + ** + ** Possible values are PDL_ON or PDL_OFF + ******************************************************************************/ +// ADC +#define PDL_DSTC_ENABLE_ADC0_PRIO PDL_OFF +#define PDL_DSTC_ENABLE_ADC0_SCAN PDL_OFF +#define PDL_DSTC_ENABLE_ADC1_PRIO PDL_OFF +#define PDL_DSTC_ENABLE_ADC1_SCAN PDL_OFF +#define PDL_DSTC_ENABLE_ADC2_PRIO PDL_OFF +#define PDL_DSTC_ENABLE_ADC2_SCAN PDL_OFF + +// BT +#define PDL_DSTC_ENABLE_BT0_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT0_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT1_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT1_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT2_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT2_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT3_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT3_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT4_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT4_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT5_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT5_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT6_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT6_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT7_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT7_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT8_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT8_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT9_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT9_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT10_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT10_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT11_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT11_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT12_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT12_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT13_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT13_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT14_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT14_IRQ1 PDL_OFF +#define PDL_DSTC_ENABLE_BT15_IRQ0 PDL_OFF +#define PDL_DSTC_ENABLE_BT15_IRQ1 PDL_OFF + +// CAN-FD +#define PDL_DSTC_ENABLE_CANFD0 PDL_OFF + +// EXINT +#define PDL_DSTC_ENABLE_EXTINT0 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT1 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT2 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT3 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT4 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT5 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT6 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT7 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT8 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT9 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT10 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT11 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT12 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT13 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT14 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT15 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT16 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT17 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT18 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT19 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT20 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT21 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT22 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT23 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT24 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT25 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT26 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT27 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT28 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT29 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT30 PDL_OFF +#define PDL_DSTC_ENABLE_EXTINT31 PDL_OFF + +// HSSPI +#define PDL_DSTC_ENABLE_HSSPI0_TX PDL_OFF +#define PDL_DSTC_ENABLE_HSSPI0_RX PDL_OFF + +// I2C Slave +#define PDL_DSTC_ENABLE_I2CS0_RX PDL_OFF +#define PDL_DSTC_ENABLE_I2CS0_TX PDL_OFF + +// I2S +#define PDL_DSTC_ENABLE_I2S0_TX PDL_OFF +#define PDL_DSTC_ENABLE_I2S0_RX PDL_OFF +#define PDL_DSTC_ENABLE_I2S1_TX PDL_OFF +#define PDL_DSTC_ENABLE_I2S1_RX PDL_OFF + +// MFS +#define PDL_DSTC_ENABLE_MFS0_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS0_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS1_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS1_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS2_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS2_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS3_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS3_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS4_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS4_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS5_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS5_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS6_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS6_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS7_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS7_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS8_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS8_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS9_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS9_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS10_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS10_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS11_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS11_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS12_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS12_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS13_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS13_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS14_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS14_TX PDL_OFF +#define PDL_DSTC_ENABLE_MFS15_RX PDL_OFF +#define PDL_DSTC_ENABLE_MFS15_TX PDL_OFF + +// MFT +#define PDL_DSTC_ENABLE_MFT0_FRT0_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_FRT0_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_FRT1_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_FRT1_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_FRT2_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_FRT2_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_ICU0 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_ICU1 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_ICU2 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_ICU3 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_OCU0 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_OCU1 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_OCU2 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_OCU3 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_OCU4 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_OCU5 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_WFG10 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_WFG32 PDL_OFF +#define PDL_DSTC_ENABLE_MFT0_WFG54 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_FRT0_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_FRT0_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_FRT1_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_FRT1_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_FRT2_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_FRT2_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_ICU0 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_ICU1 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_ICU2 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_ICU3 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_OCU0 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_OCU1 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_OCU2 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_OCU3 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_OCU4 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_OCU5 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_WFG10 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_WFG32 PDL_OFF +#define PDL_DSTC_ENABLE_MFT1_WFG54 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_FRT0_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_FRT0_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_FRT1_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_FRT1_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_FRT2_PEAK PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_FRT2_ZERO PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_ICU0 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_ICU1 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_ICU2 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_ICU3 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_OCU0 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_OCU1 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_OCU2 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_OCU3 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_OCU4 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_OCU5 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_WFG10 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_WFG32 PDL_OFF +#define PDL_DSTC_ENABLE_MFT2_WFG54 PDL_OFF + +// Programmable CRC +#define PDL_DSTC_ENABLE_PCRC PDL_OFF + +// PPG +#define PDL_DSTC_ENABLE_PPG0 PDL_OFF +#define PDL_DSTC_ENABLE_PPG2 PDL_OFF +#define PDL_DSTC_ENABLE_PPG4 PDL_OFF +#define PDL_DSTC_ENABLE_PPG8 PDL_OFF +#define PDL_DSTC_ENABLE_PPG10 PDL_OFF +#define PDL_DSTC_ENABLE_PPG12 PDL_OFF +#define PDL_DSTC_ENABLE_PPG16 PDL_OFF +#define PDL_DSTC_ENABLE_PPG18 PDL_OFF +#define PDL_DSTC_ENABLE_PPG20 PDL_OFF + +// QPRC +#define PDL_DSTC_ENABLE_QPRC0_COUNT_INVERSION PDL_OFF +#define PDL_DSTC_ENABLE_QPRC0_OUT_OF_RANGE PDL_OFF +#define PDL_DSTC_ENABLE_QPRC0_PC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC0_PC_MATCH_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC0_PC_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC0_UFL_OFL_Z PDL_OFF +#define PDL_DSTC_ENABLE_QPRC1_COUNT_INVERSION PDL_OFF +#define PDL_DSTC_ENABLE_QPRC1_OUT_OF_RANGE PDL_OFF +#define PDL_DSTC_ENABLE_QPRC1_PC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC1_PC_MATCH_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC1_PC_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC1_UFL_OFL_Z PDL_OFF +#define PDL_DSTC_ENABLE_QPRC2_COUNT_INVERSION PDL_OFF +#define PDL_DSTC_ENABLE_QPRC2_OUT_OF_RANGE PDL_OFF +#define PDL_DSTC_ENABLE_QPRC2_PC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC2_PC_MATCH_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC2_PC_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC2_UFL_OFL_Z PDL_OFF +#define PDL_DSTC_ENABLE_QPRC3_COUNT_INVERSION PDL_OFF +#define PDL_DSTC_ENABLE_QPRC3_OUT_OF_RANGE PDL_OFF +#define PDL_DSTC_ENABLE_QPRC3_PC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC3_PC_MATCH_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC3_PC_RC_MATCH PDL_OFF +#define PDL_DSTC_ENABLE_QPRC3_UFL_OFL_Z PDL_OFF + +// USB +#define PDL_DSTC_ENABLE_USB0_EP1 PDL_OFF +#define PDL_DSTC_ENABLE_USB0_EP2 PDL_OFF +#define PDL_DSTC_ENABLE_USB0_EP3 PDL_OFF +#define PDL_DSTC_ENABLE_USB0_EP4 PDL_OFF +#define PDL_DSTC_ENABLE_USB0_EP5 PDL_OFF +#define PDL_DSTC_ENABLE_USB1_EP1 PDL_OFF +#define PDL_DSTC_ENABLE_USB1_EP2 PDL_OFF +#define PDL_DSTC_ENABLE_USB1_EP3 PDL_OFF +#define PDL_DSTC_ENABLE_USB1_EP4 PDL_OFF +#define PDL_DSTC_ENABLE_USB1_EP5 PDL_OFF + +// WC +#define PDL_DSTC_ENABLE_WC PDL_OFF + +/** + ****************************************************************************** + ** User Interrupt level settings + ** + ** Possible values are 0 (high priority) to 15 (low priority) + ******************************************************************************/ +#if (PDL_MCU_CORE == PDL_FM4_CORE) // FM4 +// Analog Digital Converters +#define PDL_IRQ_LEVEL_ADC0 15u // slow +#define PDL_IRQ_LEVEL_ADC1 2u // fast adc must be higher than BT* +#define PDL_IRQ_LEVEL_ADC2 15u + +// Base Timers +#define PDL_IRQ_LEVEL_BT0 4u +#define PDL_IRQ_LEVEL_BT1 4u +#define PDL_IRQ_LEVEL_BT2 3u // adcfast timer has more priority +#define PDL_IRQ_LEVEL_BT3 3u +#define PDL_IRQ_LEVEL_BT4 15u +#define PDL_IRQ_LEVEL_BT5 15u +#define PDL_IRQ_LEVEL_BT6 15u +#define PDL_IRQ_LEVEL_BT7 15u +#define PDL_IRQ_LEVEL_BT8 15u +#define PDL_IRQ_LEVEL_BT9 15u +#define PDL_IRQ_LEVEL_BT10 15u +#define PDL_IRQ_LEVEL_BT11 15u +#define PDL_IRQ_LEVEL_BT12_13_14_15 15u + +// CAN +#define PDL_IRQ_LEVEL_CAN0 15u +#define PDL_IRQ_LEVEL_CAN1_CANFD0 15u // 6u + +// Clock Stabilization Irq +#define PDL_IRQ_LEVEL_CLK 15u + +// Clock Supervisor +#define PDL_IRQ_LEVEL_CSV 15u + +// DMA +#define PDL_IRQ_LEVEL_DMA0 15u +#define PDL_IRQ_LEVEL_DMA1 15u +#define PDL_IRQ_LEVEL_DMA2 15u +#define PDL_IRQ_LEVEL_DMA3 15u +#define PDL_IRQ_LEVEL_DMA4 15u +#define PDL_IRQ_LEVEL_DMA5 15u +#define PDL_IRQ_LEVEL_DMA6 15u +#define PDL_IRQ_LEVEL_DMA7 15u + +// DSTC +#define PDL_IRQ_LEVEL_DSTC 15u + +// Dual Timer(s) +#define PDL_IRQ_LEVEL_DT0 15u + +// Ethernet +// Please set IRQ level in emac_user.h + +// External Bus Interface +#define PDL_IRQ_LEVEL_EXTIF 15u + +// External Interrupts + NMI +#define PDL_IRQ_LEVEL_EXINT0 2u // the same as fast ADC +#define PDL_IRQ_LEVEL_EXINT1 2u +#define PDL_IRQ_LEVEL_EXINT2 2u +#define PDL_IRQ_LEVEL_EXINT3 2u +#define PDL_IRQ_LEVEL_EXINT4 2u +#define PDL_IRQ_LEVEL_EXINT5 2u +#define PDL_IRQ_LEVEL_EXINT6 2u +#define PDL_IRQ_LEVEL_EXINT7 2u +#define PDL_IRQ_LEVEL_EXINT8 2u +#define PDL_IRQ_LEVEL_EXINT9 2u +#define PDL_IRQ_LEVEL_EXINT10 2u +#define PDL_IRQ_LEVEL_EXINT11 2u +#define PDL_IRQ_LEVEL_EXINT12 2u +#define PDL_IRQ_LEVEL_EXINT13 2u +#define PDL_IRQ_LEVEL_EXINT14 2u +#define PDL_IRQ_LEVEL_EXINT15 2u +#define PDL_IRQ_LEVEL_EXINT16_17_18_19 2u +#define PDL_IRQ_LEVEL_EXINT20_21_22_23 2u +#define PDL_IRQ_LEVEL_EXINT24_25_26_27 2u +#define PDL_IRQ_LEVEL_EXINT28_29_30_31 2u + +// Hyper Bus Interface +#define PDL_IRQ_LEVEL_HBIF 15u + +// High Speed Quad SPI +#define PDL_IRQ_LEVEL_HSSPI0 15u + +// I2S and Programmable CRC +#define PDL_IRQ_LEVEL_I2S_PCRC 15u + +// IC Card +#define PDL_IRQ_LEVEL_ICC0_1 15u + +// Low Voltage Detection Interrupt +#define PDL_IRQ_LEVEL_LVD 15u + +// Multi Function Serial Interfaces +#define PDL_IRQ_LEVEL_MFS0_TX 15u +#define PDL_IRQ_LEVEL_MFS0_RX 15u +#define PDL_IRQ_LEVEL_MFS1_TX 15u +#define PDL_IRQ_LEVEL_MFS1_RX 15u +#define PDL_IRQ_LEVEL_MFS2_TX 15u +#define PDL_IRQ_LEVEL_MFS2_RX 15u +#define PDL_IRQ_LEVEL_MFS3_TX 15u +#define PDL_IRQ_LEVEL_MFS3_RX 15u +#define PDL_IRQ_LEVEL_MFS4_TX 15u +#define PDL_IRQ_LEVEL_MFS4_RX 15u +#define PDL_IRQ_LEVEL_MFS5_TX 15u +#define PDL_IRQ_LEVEL_MFS5_RX 15u +#define PDL_IRQ_LEVEL_MFS6_TX 15u +#define PDL_IRQ_LEVEL_MFS6_RX 15u +#define PDL_IRQ_LEVEL_MFS7_TX 15u +#define PDL_IRQ_LEVEL_MFS7_RX 15u +#define PDL_IRQ_LEVEL_MFS8_TX 15u +#define PDL_IRQ_LEVEL_MFS8_RX 15u +#define PDL_IRQ_LEVEL_MFS9_TX 15u +#define PDL_IRQ_LEVEL_MFS9_RX 15u +#define PDL_IRQ_LEVEL_MFS10_TX 15u +#define PDL_IRQ_LEVEL_MFS10_RX 15u +#define PDL_IRQ_LEVEL_MFS11_TX 15u +#define PDL_IRQ_LEVEL_MFS11_RX 15u +#define PDL_IRQ_LEVEL_MFS12_TX 15u +#define PDL_IRQ_LEVEL_MFS12_RX 15u +#define PDL_IRQ_LEVEL_MFS13_TX 15u +#define PDL_IRQ_LEVEL_MFS13_RX 15u +#define PDL_IRQ_LEVEL_MFS14_TX 15u +#define PDL_IRQ_LEVEL_MFS14_RX 15u +#define PDL_IRQ_LEVEL_MFS15_TX 15u +#define PDL_IRQ_LEVEL_MFS15_RX 15u + +// Multi Function Timer Interrupts +#define PDL_IRQ_LEVEL_MFT0_FRT 15u +#define PDL_IRQ_LEVEL_MFT0_OCU 15u +#define PDL_IRQ_LEVEL_MFT0_WFG 15u +#define PDL_IRQ_LEVEL_MFT0_ICU 15u + +#define PDL_IRQ_LEVEL_MFT1_FRT 15u +#define PDL_IRQ_LEVEL_MFT1_OCU 15u +#define PDL_IRQ_LEVEL_MFT1_WFG 15u +#define PDL_IRQ_LEVEL_MFT1_ICU 15u + +#define PDL_IRQ_LEVEL_MFT2_FRT 15u +#define PDL_IRQ_LEVEL_MFT2_OCU 15u +#define PDL_IRQ_LEVEL_MFT2_WFG 15u +#define PDL_IRQ_LEVEL_MFT2_ICU 15u + +// NMI +#define PDL_IRQ_LEVEL_NMI 15u + +// PPG Interrupts +#define PDL_IRQ_LEVEL_PPG00_02_04 15u +#define PDL_IRQ_LEVEL_PPG08_10_12 15u +#define PDL_IRQ_LEVEL_PPG16_18_20 15u + +// Quad Decoder and Revolution Counter +#define PDL_IRQ_LEVEL_QPRC0 15u +#define PDL_IRQ_LEVEL_QPRC1 15u +#define PDL_IRQ_LEVEL_QPRC2 15u +#define PDL_IRQ_LEVEL_QPRC3 15u + +// Real Time Clock +#define PDL_IRQ_LEVEL_RTC0 15u + +// SD Host +#define PDL_IRQ_LEVEL_SD 15u + +// USB +#define PDL_IRQ_LEVEL_USB0 6u +#define PDL_IRQ_LEVEL_USB1 6u + +// Watch Counter +#define PDL_IRQ_LEVEL_WC0 15u + +// Watchdog Timers +#define PDL_IRQ_LEVEL_HWWDG 15u +#define PDL_IRQ_LEVEL_SWWDG 15u + +#else +#error MCU core not found! +#endif +/** + ****************************************************************************** + ** PDL resource activiation check + ** + ** \note It does not check, if a device has actually all instances available! + ** + ******************************************************************************/ +// Activate code in adc.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_ADC0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_ADC1 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_ADC2 == PDL_ON) + #define PDL_PERIPHERAL_ADC_ACTIVE +#endif + +// Activate code in aes.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_AES == PDL_ON) + #define PDL_PERIPHERAL_AES_ACTIVE +#endif + +// Activate code in bt.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_BT0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT1 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT2 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT3 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT4 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT5 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT6 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT7 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT8 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT9 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT10 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT11 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT12 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT13 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT14 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_BT15 == PDL_ON) + #define PDL_PERIPHERAL_BT_ACTIVE +#endif + +// Activate code in can.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_CAN0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_CAN1 == PDL_ON) + #define PDL_PERIPHERAL_CAN_ACTIVE +#endif + +// Activate code in canfd.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_CANFD0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_CANFD1 == PDL_ON) + #define PDL_PERIPHERAL_CANFD_ACTIVE +#endif + +// Activate code in crc.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_CRC0 == PDL_ON) + #define PDL_PERIPHERAL_CRC_ACTIVE +#endif + +// Activate code in clk.c if set to PDL_ON or WC enabled +#if (PDL_PERIPHERAL_ENABLE_CLK == PDL_ON) + #define PDL_PERIPHERAL_CLK_ACTIVE +#endif + +// Activate code in crtrim.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_CR == PDL_ON) + #define PDL_PERIPHERAL_CR_ACTIVE +#endif + +// Activate code in csv.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_CSV == PDL_ON) + #define PDL_PERIPHERAL_CSV_ACTIVE +#endif + +// Activate code in dac.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_DAC0 == PDL_ON) + #define PDL_PERIPHERAL_DAC_ACTIVE +#endif + +// Activate code for dma.c +#if (PDL_PERIPHERAL_ENABLE_DMA0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA1 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA2 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA3 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA4 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA5 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA6 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_DMA7 == PDL_ON) + #define PDL_PERIPHERAL_DMA_ACTIVE +#endif + +// Activate code in dstc.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_DSTC == PDL_ON) + #define PDL_PERIPHERAL_DSTC_ACTIVE +#endif + +// Activate code in dt.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_DT0 == PDL_ON) + #define PDL_PERIPHERAL_DT_ACTIVE +#endif + +// Activate code in exint.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_EXINT0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT1 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT2 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT3 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT4 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT5 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT6 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT7 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT8 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT9 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT10 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT11 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT12 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT13 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT14 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT15 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT16 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT17 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT18 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT19 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT20 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT21 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT22 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT23 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT24 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT25 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT26 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT27 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT28 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT29 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT30 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_EXINT31 == PDL_ON) + #define PDL_PERIPHERAL_EXINT_ACTIVE +#endif + +// Activate code in extif.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_EXTIF == PDL_ON) + #define PDL_PERIPHERAL_EXTIF_ACTIVE +#endif + +// Activate code in dualflash.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_DUAL_FLASH == PDL_ON) + #define PDL_PERIPHERAL_DUAL_FLASH_ACTIVE +#endif + +// Activate code in mainflash.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MAIN_FLASH == PDL_ON) + #define PDL_PERIPHERAL_MAIN_FLASH_ACTIVE +#endif + +// Activate code in workflash.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_WORK_FLASH == PDL_ON) + #define PDL_PERIPHERAL_WORK_FLASH_ACTIVE +#endif + +// Activate code in gpio.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_GPIO == PDL_ON) + #define PDL_PERIPHERAL_GPIO_ACTIVE +#endif + +// Activate code in hbif.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_HBIF == PDL_ON) + #define PDL_PERIPHERAL_HBIF_ACTIVE +#endif + +// Activate code in hsspi.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_HSSPI0 == PDL_ON) + #define PDL_PERIPHERAL_HSSPI_ACTIVE +#endif + +// Activate code in i2cs.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_I2CS0 == PDL_ON) + #define PDL_PERIPHERAL_I2CS_ACTIVE +#endif + +// Activate code in icc.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_ICC0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_ICC1 == PDL_ON) + #define PDL_PERIPHERAL_ICC_ACTIVE +#endif + +// Activate code in i2s.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_I2S0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_I2S1 == PDL_ON) + #define PDL_PERIPHERAL_I2S_ACTIVE +#endif + +// Activate code in i2sl.h if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_I2SL0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_I2SL1 == PDL_ON) + #define PDL_PERIPHERAL_I2SL_ACTIVE +#endif + +// Activate code in lcd.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_LCD == PDL_ON) + #define PDL_PERIPHERAL_LCD_ACTIVE +#endif + +// Activate code in lpm.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_LPM == PDL_ON) + #define PDL_PERIPHERAL_LPM_ACTIVE +#endif + +// Activate code in lvd.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_LVD == PDL_ON) + #define PDL_PERIPHERAL_LVD_ACTIVE +#endif + +// Activate code in mfs.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MFS0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS1 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS2 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS3 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS4 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS5 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS6 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS7 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS8 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS9 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS10 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS11 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS12 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS13 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS14 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFS15 == PDL_ON) + #define PDL_PERIPHERAL_MFS_ACTIVE +#endif + +// Activate code in mft_frt.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MFT0_FRT == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT1_FRT == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT2_FRT == PDL_ON) + #define PDL_PERIPHERAL_MFT_FRT_ACTIVE +#endif + +// Activate code in mft_ocu.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MFT0_OCU == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT1_OCU == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT2_OCU == PDL_ON) + #define PDL_PERIPHERAL_MFT_OCU_ACTIVE +#endif + +// Activate code in mft_wfg.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MFT0_WFG == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT1_WFG == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT2_WFG == PDL_ON) + #define PDL_PERIPHERAL_MFT_WFG_ACTIVE +#endif + +// Activate code in mft_icu.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MFT0_ICU == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT1_ICU == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT2_ICU == PDL_ON) + #define PDL_PERIPHERAL_MFT_ICU_ACTIVE +#endif + +// Activate code in mft_adcmp.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_MFT0_ADCMP == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT1_ADCMP == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_MFT2_ADCMP == PDL_ON) + #define PDL_PERIPHERAL_MFT_ADCMP_ACTIVE +#endif + +// Activate NMI code in exint.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_NMI == PDL_ON) + #define PDL_PERIPHERAL_NMI_ACTIVE +#endif + +// Activate code in pcrc.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_PCRC == PDL_ON) + #define PDL_PERIPHERAL_PCRC_ACTIVE +#endif + +// Activate code in ppg.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_PPG == PDL_ON) + #define PDL_PERIPHERAL_PPG_ACTIVE +#endif + +// Activate code in qprc.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_QPRC0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_QPRC1 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_QPRC2 == PDL_ON) + #define PDL_PERIPHERAL_QPRC_ACTIVE +#endif + +// Activate code in rc.c if set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_RC0 == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_RC1 == PDL_ON) + #define PDL_PERIPHERAL_RC_ACTIVE +#endif + +// Reset Cause +#if (PDL_PERIPHERAL_ENABLE_RESET == PDL_ON) + #define PDL_PERIPHERAL_RESET_ACTIVE +#endif + +// Real Time Clock +#if (PDL_PERIPHERAL_ENABLE_RTC0 == PDL_ON) + #define PDL_PERIPHERAL_RTC_ACTIVE +#endif + +// SD +#if (PDL_PERIPHERAL_ENABLE_SD0 == PDL_ON) + #define PDL_PERIPHERAL_SD_ACTIVE +#endif + +// Unique ID +#if (PDL_PERIPHERAL_ENABLE_UID == PDL_ON) + #define PDL_PERIPHERAL_UID_ACTIVE +#endif + +// Activate code in vbat.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_VBAT == PDL_ON) + #define PDL_PERIPHERAL_VBAT_ACTIVE +#endif + +// Activate code in wc.c if one or more are set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_WC0 == PDL_ON) + #define PDL_PERIPHERAL_WC_ACTIVE +#endif + +// Activate code in wdg.c is set to PDL_ON +#if (PDL_PERIPHERAL_ENABLE_HWWDG == PDL_ON) || \ + (PDL_PERIPHERAL_ENABLE_SWWDG == PDL_ON) + #define PDL_PERIPHERAL_WDG_ACTIVE +#endif + +/** + ****************************************************************************** + ** \brief PDL utility enable setting + ******************************************************************************/ +// Printf/Scanf via UART function +#define PDL_UTILITY_ENABLE_UART_PRINTF PDL_OFF +#define PDL_UTILITY_ENABLE_UART_SCANF PDL_OFF + +// AT24CXX(EEPROM) driver +#define PDL_UTILITY_ENABLE_I2C_POLLING_AT24CXX PDL_OFF +#define PDL_UTILITY_ENABLE_I2C_IRQ_AT24CXX PDL_OFF + +// S25FL164K(SPI Flash) QSPI access driver with or without using interrupt +#define PDL_UTILITY_ENABLE_QSPI_POLLING_S25FL164K PDL_OFF +#define PDL_UTILITY_ENABLE_QSPI_IRQ_S25FL164K PDL_OFF + +// S26KL512S (Hyper Bus Flash) driver +#define PDL_UTILITY_ENABLE_HBIF_S26KL512S PDL_OFF + +// WM8731(I2S Codec) driver +#define PDL_UTILITY_ENABLE_I2S_CODEC_WM8731 PDL_OFF + +// SV6P1615(External Bus SRAM) driver +#define PDL_UTILITY_ENABLE_EXTIF_SV6P1615 PDL_OFF + +// IS42S16800(SDRAM) driver +#define PDL_UTILITY_ENABLE_EXTIF_IS42S16800 PDL_OFF + +// HY57V281620(SDRAM) driver +#define PDL_UTILITY_ENABLE_EXTIF_HY57V281620 PDL_OFF + +// K9F5608U0D (Nand Flash) driver +#define PDL_UTILITY_ENABLE_EXTIF_K9F5608U0D PDL_OFF + +// S34ML01G (Nand Flash) driver +#define PDL_UTILITY_ENABLE_EXTIF_S34ML01G PDL_OFF + +// TSDH1188 (Segment LCD) driver +#define PDL_UTILITY_ENABLE_SEG_LCD_TSDH1188 PDL_OFF + +// CL010-7031-04(Segment LCD) driver +#define PDL_UTILITY_ENABLE_SEG_LCD_CL0107031 PDL_OFF + +/** + ****************************************************************************** + ** \brief Enable/disable print on the terminal window + ******************************************************************************/ +#define DEBUG_PRINT + +#endif // __PDL_USER_H__ + +/******************************************************************************/ +/* EOF (not truncated) */ +/******************************************************************************/ diff --git a/firmware/config/boards/hellen/cypress/readme.md b/firmware/config/boards/hellen/cypress/readme.md new file mode 100644 index 0000000000..5b16803b44 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/readme.md @@ -0,0 +1,7 @@ +rusEfi runs on Cypress FM4 S6E2xx (alpha version as of Jan 2020) + +# How to program + +Cypress has "FLASH USB Direct Programmer" utility: + +https://www.cypress.com/documentation/software-and-drivers/flash-usb-direct-programmer-1 diff --git a/firmware/config/boards/hellen/cypress/rusefi_hw_enums.h b/firmware/config/boards/hellen/cypress/rusefi_hw_enums.h new file mode 100644 index 0000000000..8d82328101 --- /dev/null +++ b/firmware/config/boards/hellen/cypress/rusefi_hw_enums.h @@ -0,0 +1,304 @@ +/* + * @file config/boards/kinetis/rusefi_hw_enums.h + * + * @date Jun 2, 2019 + * @author Andrey Belomutskiy, (c) 2012-2020 + * @author andreika + */ + +#ifndef RUSEFI_HW_ENUMS_H_ +#define RUSEFI_HW_ENUMS_H_ + +// todo: migrate/unify with pin_output_mode_e? rename? something is messy here +// this enum is currently only used for SPI pins +typedef enum __attribute__ ((__packed__)) { +// todo: here we have a rare example of stm32-specific enum, todo: make this not stm32 specific? + PO_DEFAULT = 0, + PO_OPENDRAIN = 4, // PAL_STM32_OTYPE_OPENDRAIN + PO_PULLUP = 32, // PAL_STM32_PUDR_PULLUP + PO_PULLDOWN = 64 // PAL_STM32_PUPDR_PULLDOWN +} pin_mode_e; + +/** + * Hardware pin. This enum is platform-specific. + */ +typedef enum __attribute__ ((__packed__)) { + GPIO_UNASSIGNED = 0, + GPIO_INVALID = 1, + + GPIOA_0 = 2, + GPIOA_1 = 3, + GPIOA_2 = 4, + GPIOA_3 = 5, + GPIOA_4 = 6, + GPIOA_5 = 7, + GPIOA_6 = 8, + GPIOA_7 = 9, + GPIOA_8 = 10, + GPIOA_9 = 11, + GPIOA_10 = 12, + GPIOA_11 = 13, + GPIOA_12 = 14, + GPIOA_13 = 15, + GPIOA_14 = 16, + GPIOA_15 = 17, + + GPIOB_0 = 18, + GPIOB_1 = 19, + GPIOB_2 = 20, + GPIOB_3 = 21, + GPIOB_4 = 22, + GPIOB_5 = 23, + GPIOB_6 = 24, + GPIOB_7 = 25, + GPIOB_8 = 26, + GPIOB_9 = 27, + GPIOB_10 = 28, + GPIOB_11 = 29, + GPIOB_12 = 30, + GPIOB_13 = 31, + GPIOB_14 = 32, + GPIOB_15 = 33, + + GPIOC_0 = 34, + GPIOC_1 = 35, + GPIOC_2 = 36, + GPIOC_3 = 37, + GPIOC_4 = 38, + GPIOC_5 = 39, + GPIOC_6 = 40, + GPIOC_7 = 41, + GPIOC_8 = 42, + GPIOC_9 = 43, + GPIOC_10 = 44, + GPIOC_11 = 45, + GPIOC_12 = 46, + GPIOC_13 = 47, + GPIOC_14 = 48, + GPIOC_15 = 49, + + GPIOD_0 = 50, + GPIOD_1 = 51, + GPIOD_2 = 52, + GPIOD_3 = 53, + GPIOD_4 = 54, + GPIOD_5 = 55, + GPIOD_6 = 56, + GPIOD_7 = 57, + GPIOD_8 = 58, + GPIOD_9 = 59, + GPIOD_10 = 60, + GPIOD_11 = 61, + GPIOD_12 = 62, + GPIOD_13 = 63, + GPIOD_14 = 64, + GPIOD_15 = 65, + + GPIOE_0 = 66, + GPIOE_1 = 67, + GPIOE_2 = 68, + GPIOE_3 = 69, + GPIOE_4 = 70, + GPIOE_5 = 71, + GPIOE_6 = 72, + GPIOE_7 = 73, + GPIOE_8 = 74, + GPIOE_9 = 75, + GPIOE_10 = 76, + GPIOE_11 = 77, + GPIOE_12 = 78, + GPIOE_13 = 79, + GPIOE_14 = 80, + GPIOE_15 = 81, + + GPIOF_0 = 82, + GPIOF_1 = 83, + GPIOF_2 = 84, + GPIOF_3 = 85, + GPIOF_4 = 86, + GPIOF_5 = 87, + GPIOF_6 = 88, + GPIOF_7 = 89, + GPIOF_8 = 90, + GPIOF_9 = 91, + GPIOF_10 = 92, + GPIOF_11 = 93, + GPIOF_12 = 94, + GPIOF_13 = 95, + GPIOF_14 = 96, + GPIOF_15 = 97, + + GPIOG_0 = 98, + GPIOG_1 = 99, + GPIOG_2 = 100, + GPIOG_3 = 101, + GPIOG_4 = 102, + GPIOG_5 = 103, + GPIOG_6 = 104, + GPIOG_7 = 105, + GPIOG_8 = 106, + GPIOG_9 = 107, + GPIOG_10 = 108, + GPIOG_11 = 109, + GPIOG_12 = 110, + GPIOG_13 = 111, + GPIOG_14 = 112, + GPIOG_15 = 113, + + GPIOH_0 = 114, + GPIOH_1 = 115, + GPIOH_2 = 116, + GPIOH_3 = 117, + GPIOH_4 = 118, + GPIOH_5 = 119, + GPIOH_6 = 120, + GPIOH_7 = 121, + GPIOH_8 = 122, + GPIOH_9 = 123, + GPIOH_10 = 124, + GPIOH_11 = 125, + GPIOH_12 = 126, + GPIOH_13 = 127, + GPIOH_14 = 128, + GPIOH_15 = 129, + + GPIOI_0 = 130, + GPIOI_1 = 131, + GPIOI_2 = 132, + GPIOI_3 = 133, + GPIOI_4 = 134, + GPIOI_5 = 135, + GPIOI_6 = 136, + GPIOI_7 = 137, + GPIOI_8 = 138, + GPIOI_9 = 139, + GPIOI_10 = 140, + GPIOI_11 = 141, + GPIOI_12 = 142, + GPIOI_13 = 143, + GPIOI_14 = 144, + GPIOI_15 = 145, + + GPIOJ_0 = 146, + GPIOJ_1 = 147, + GPIOJ_2 = 148, + GPIOJ_3 = 149, + GPIOJ_4 = 150, + GPIOJ_5 = 151, + GPIOJ_6 = 152, + GPIOJ_7 = 153, + GPIOJ_8 = 154, + GPIOJ_9 = 155, + GPIOJ_10 = 156, + GPIOJ_11 = 157, + GPIOJ_12 = 158, + GPIOJ_13 = 159, + GPIOJ_14 = 160, + GPIOJ_15 = 161, + + GPIOK_0 = 162, + GPIOK_1 = 163, + GPIOK_2 = 164, + GPIOK_3 = 165, + GPIOK_4 = 166, + GPIOK_5 = 167, + GPIOK_6 = 168, + GPIOK_7 = 169, + GPIOK_8 = 170, + GPIOK_9 = 171, + GPIOK_10 = 172, + GPIOK_11 = 173, + GPIOK_12 = 174, + GPIOK_13 = 175, + GPIOK_14 = 176, + GPIOK_15 = 177, + + // DRV8860 pins go right after on chips + //#define DRV8860_PIN(n) ((brain_pin_e)((int)BRAIN_PIN_LAST_ONCHIP + 1 + (n))) + DRV8860_PIN_1 = 178, + DRV8860_PIN_2 = 179, + DRV8860_PIN_3 = 180, + DRV8860_PIN_4 = 181, + DRV8860_PIN_5 = 182, + DRV8860_PIN_6 = 183, + DRV8860_PIN_7 = 184, + DRV8860_PIN_8 = 185, + DRV8860_PIN_9 = 186, + DRV8860_PIN_10 = 187, + DRV8860_PIN_11 = 188, + DRV8860_PIN_12 = 189, + DRV8860_PIN_13 = 190, + DRV8860_PIN_14 = 191, + DRV8860_PIN_15 = 192, + DRV8860_PIN_16 = 193, + +} brain_pin_e; + +/* Plase keep updating this define */ +#define BRAIN_PIN_LAST_ONCHIP GPIOK_15 + +/* diagnostic for brain pins + * can be combination of few bits + * defined as bit mask */ +typedef enum __attribute__ ((__packed__)) +{ + PIN_OK = 0, + PIN_OPEN = 0x01, + PIN_SHORT_TO_GND = 0x02, + PIN_SHORT_TO_BAT = 0x04, + PIN_OVERLOAD = 0x08, + PIN_DRIVER_OVERTEMP = 0x10, + PIN_INVALID = 0x80 +} brain_pin_diag_e; + +typedef enum __attribute__ ((__packed__)) { + EFI_ADC_0 = 0, + EFI_ADC_1 = 1, + EFI_ADC_2 = 2, + EFI_ADC_3 = 3, + EFI_ADC_4 = 4, + EFI_ADC_5 = 5, + EFI_ADC_6 = 6, + EFI_ADC_7 = 7, + EFI_ADC_8 = 8, + EFI_ADC_9 = 9, + EFI_ADC_10 = 10, + EFI_ADC_11 = 11, + EFI_ADC_12 = 12, + EFI_ADC_13 = 13, + EFI_ADC_14 = 14, + EFI_ADC_15 = 15, + EFI_ADC_16 = 16, + EFI_ADC_17 = 17, + EFI_ADC_18 = 18, + EFI_ADC_19 = 19, + EFI_ADC_20 = 20, + EFI_ADC_21 = 21, + EFI_ADC_22 = 22, + EFI_ADC_23 = 23, + EFI_ADC_24 = 24, + EFI_ADC_25 = 25, + EFI_ADC_26 = 26, + EFI_ADC_27 = 27, + EFI_ADC_28 = 28, + EFI_ADC_29 = 29, + EFI_ADC_30 = 30, + EFI_ADC_31 = 31, + + // todo: bad choice of value since now we have ADC_CHANNEL_SENSOR and could end up with 17 and 18 also + EFI_ADC_NONE = 32, + EFI_ADC_ERROR = 33, +#if EFI_UNIT_TEST + /** + * these values are unfortunately visible to BoardReader + * and TunerStudio would need these ordinals to fit into field size + */ + TEST_MAF_CHANNEL = 34, + TEST_CLT_CHANNEL = 35, + TEST_IAT_CHANNEL = 36, +#endif /* EFI_UNIT_TEST */ +} adc_channel_e; + +#define INCOMPATIBLE_CONFIG_CHANGE EFI_ADC_0 + +#endif /* RUSEFI_HW_ENUMS_H_ */ From 40150c5fc677a3cacfe0a461085499bc22a4d4a1 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 11:31:29 -0400 Subject: [PATCH 03/12] Hellen says cyclic buffer --- firmware/tunerstudio/rusefi.input | 4 ++ firmware/util/containers/cyclic_buffer.h | 2 +- firmware/util/containers/fifo_buffer.h | 75 ++++++++++++++++++++++++ 3 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 firmware/util/containers/fifo_buffer.h diff --git a/firmware/tunerstudio/rusefi.input b/firmware/tunerstudio/rusefi.input index 328279a1e6..029173dc64 100644 --- a/firmware/tunerstudio/rusefi.input +++ b/firmware/tunerstudio/rusefi.input @@ -1813,6 +1813,10 @@ cmd_set_engine_type_default = "w\x00\x31\x00\x00" field = "TLE8888 Chip Select", tle8888_cs field = "TLE8888 CS Mode", tle8888_csPinMode field = "TLE 8888 spi", tle8888spiDevice + field = "DRV8860 CS", drv8860_cs + field = "DRV8860 CS Mode", drv8860_csPinMode + field = "DRV8860 MISO pin", drv8860_miso + field = "DRV8860 SPI", drv8860spiDevice field = "servo#1", servoOutputPins1 field = "servo#2", servoOutputPins2 field = "servo#3", servoOutputPins3 diff --git a/firmware/util/containers/cyclic_buffer.h b/firmware/util/containers/cyclic_buffer.h index 5c76adb9ed..399783e0a0 100644 --- a/firmware/util/containers/cyclic_buffer.h +++ b/firmware/util/containers/cyclic_buffer.h @@ -41,7 +41,7 @@ class cyclic_buffer volatile T elements[maxSize]; volatile int currentIndex; - private: + protected: void baseC(int size); /** * number of elements added into this buffer, would be eventually bigger then size diff --git a/firmware/util/containers/fifo_buffer.h b/firmware/util/containers/fifo_buffer.h new file mode 100644 index 0000000000..b51ac7ed77 --- /dev/null +++ b/firmware/util/containers/fifo_buffer.h @@ -0,0 +1,75 @@ +/** + * @file fifo_buffer.h + * @brief A FIFO buffer (base on cyclic_buffer) + * + * https://en.wikipedia.org/wiki/FIFO_(computing_and_electronics) + * + * @date Aug 6, 2020 + * @author andreika + * @author Andrey Belomutskiy + * +*/ + +#ifndef FIFO_BUFFER_H +#define FIFO_BUFFER_H + +#include "cyclic_buffer.h" + +// todo: this is not a thread-safe version! +template +class fifo_buffer : public cyclic_buffer { +public: + fifo_buffer() : currentIndexRead(0) { + } + + void put(T item); + T get(); + void clear() /*override*/; + + void put(const T *items, int numItems); + + bool isEmpty() const { + return getCount() == 0; + } + + bool isFull() const { + return getCount() >= getSize(); + } + +public: + volatile int currentIndexRead; // FIFO "tail" +}; + +template +void fifo_buffer::put(T item) { + // check if full + if (!isFull()) { + cyclic_buffer::add(item); + } +} + +template +void fifo_buffer::put(const T *items, int numItems) { + for (int i = 0; i < numItems; i++) { + put(items[i]); + } +} + +template +T fifo_buffer::get() { + auto ret = elements[currentIndexRead]; + if (!isEmpty()) { + currentIndexRead = (currentIndexRead + 1) % size; + count--; + } + return ret; +} + +template +void fifo_buffer::clear() { + cyclic_buffer::clear(); + currentIndexRead = 0; +} + + +#endif /* FIFO_BUFFER_H */ \ No newline at end of file From 0aa76da9f29bb17685b160114a20f7f55afcf673 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 11:57:20 -0400 Subject: [PATCH 04/12] Hellen says ports (cherry picked from commit 4acea75cc800149bd950dc58f6417b85cb79f79c) --- .../hw_layer/ports/cypress/backup_ram.cpp | 79 ++ .../hw_layer/ports/cypress/cypress_common.cpp | 170 ++++ .../hw_layer/ports/cypress/cypress_pins.cpp | 180 ++++ firmware/hw_layer/ports/cypress/flash.c | 135 +++ firmware/hw_layer/ports/cypress/hw_ports.mk | 16 + firmware/hw_layer/ports/cypress/mpu_util.cpp | 253 +++++ firmware/hw_layer/ports/cypress/mpu_util.h | 92 ++ .../ports/cypress/serial_over_usb/usbconfig.c | 895 ++++++++++++++++++ .../ports/cypress/serial_over_usb/usbconfig.h | 266 ++++++ .../cypress/serial_over_usb/usbconsole.c | 170 ++++ .../cypress/serial_over_usb/usbconsole.h | 23 + .../cypress/serial_over_usb/usbdescriptors.h | 190 ++++ .../cypress/serial_over_usb/usbdevicehw.h | 83 ++ .../ports/cypress/serial_over_usb/usbhosthw.h | 100 ++ 14 files changed, 2652 insertions(+) create mode 100644 firmware/hw_layer/ports/cypress/backup_ram.cpp create mode 100644 firmware/hw_layer/ports/cypress/cypress_common.cpp create mode 100644 firmware/hw_layer/ports/cypress/cypress_pins.cpp create mode 100644 firmware/hw_layer/ports/cypress/flash.c create mode 100644 firmware/hw_layer/ports/cypress/hw_ports.mk create mode 100644 firmware/hw_layer/ports/cypress/mpu_util.cpp create mode 100644 firmware/hw_layer/ports/cypress/mpu_util.h create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.c create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.h create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.c create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.h create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbdescriptors.h create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbdevicehw.h create mode 100644 firmware/hw_layer/ports/cypress/serial_over_usb/usbhosthw.h diff --git a/firmware/hw_layer/ports/cypress/backup_ram.cpp b/firmware/hw_layer/ports/cypress/backup_ram.cpp new file mode 100644 index 0000000000..b07f1862ea --- /dev/null +++ b/firmware/hw_layer/ports/cypress/backup_ram.cpp @@ -0,0 +1,79 @@ +/** + * @file backup_ram.cpp + * + * @date May 22, 2020 + */ + +#include "global.h" +#include "backup_ram.h" +#include "flash.h" + +#define BACKUP_NOT_INITIALIZED 0xFFFF +#define BACKUP_SAVED 0x5555 +#define BACKUP_PENDING 0x0000 + +// we store the flash state at 0 index + all backup variables +static volatile uint32_t backupRam[BACKUP_RAM_NUM + 1]; +static bool wasLoaded = false; +// these offsets are indices in the 'BACKUP_FLASH_ADDR' (32-bit array) +static const int backupStateOffset = 0, backupDataOffset = 1; +const size_t backupSize = (BACKUP_RAM_NUM + 1) * sizeof(uint32_t); + +static void backupInit(void) { + static_assert(backupSize <= BACKUP_FLASH_SIZE, "Backup flash overflow"); + + // first, load the whole buffer into the memory + flashRead((flashaddr_t)BACKUP_FLASH_ADDR, (char *)backupRam, backupSize); + // check if we have a reliable properly saved data + if (backupRam[backupStateOffset] != BACKUP_SAVED) { + // zero is the default value + memset((void *)backupRam, 0, backupSize); + } + + // we cannot trust the saved data anymore, until it's saved in backupRamFlush() + // so we mark is as 'pending' + backupRam[backupStateOffset] = BACKUP_PENDING; + flashWrite(BACKUP_FLASH_ADDR + backupStateOffset, (char *)backupRam, sizeof(backupRam[backupStateOffset])); + + wasLoaded = true; +} + +uint32_t backupRamLoad(backup_ram_e idx) { + // this is executed only once during the firmware init + if (!wasLoaded) { + backupInit(); + } + + return backupRam[idx + backupDataOffset]; +} + +void backupRamSave(backup_ram_e idx, uint32_t value) { + // this is executed only once during the firmware init + if (!wasLoaded) { + backupInit(); + } + + backupRam[idx + backupDataOffset] = value; +} + +void backupRamFlush(void) { + + // todo: implement an incremental "append-to-the-end" algorithm to minimize sector erasings? + + // Enter the critical zone + syssts_t sts = chSysGetStatusAndLockX(); + + // rewrite the whole sector + flashErase((flashaddr_t)BACKUP_FLASH_ADDR, BACKUP_FLASH_SIZE); + // mark the data as valid & saved + backupRam[backupStateOffset] = BACKUP_SAVED; + // save the data to the flash + flashWrite((flashaddr_t)BACKUP_FLASH_ADDR, (char *)backupRam, backupSize); + + // Leaving the critical zone + chSysRestoreStatusX(sts); + + // there should not be any backup-RAM activity after this call + // but if there is, at least try to reinitialize... + wasLoaded = false; +} diff --git a/firmware/hw_layer/ports/cypress/cypress_common.cpp b/firmware/hw_layer/ports/cypress/cypress_common.cpp new file mode 100644 index 0000000000..466e294ef4 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/cypress_common.cpp @@ -0,0 +1,170 @@ +/** + * @file cypress_common.cpp + * @brief Low level common Cypress code + * + * @date Jan 28, 2020 + * @author andreika + */ + +#include "global.h" +#include "engine.h" +#include "pin_repository.h" + +#if HAL_USE_ADC || defined(__DOXYGEN__) + +// ADC_CHANNEL_IN0 // PA2 (def=VIGN) +// ADC_CHANNEL_IN1 // PA3 (def=MAP4) +// ADC_CHANNEL_IN2 // x +// ADC_CHANNEL_IN3 // PD3 (def=MAP3) +// ADC_CHANNEL_IN4 // x +// ADC_CHANNEL_IN5 // x +// ADC_CHANNEL_IN6 // x +// ADC_CHANNEL_IN7 // PB12 (def=MAP2) +// ADC_CHANNEL_IN8 // PB13 (def=MAP1) +// ADC_CHANNEL_IN9 // x +// ADC_CHANNEL_IN10 // PE2 (def=O2S2) +// ADC_CHANNEL_IN11 // x +// ADC_CHANNEL_IN12 // PC14 (def=O2S) +// ADC_CHANNEL_IN13 // PC15 (def=TPS) +// ADC_CHANNEL_IN14 // PC16 (def=CLT) +// ADC_CHANNEL_IN15 // PC17 (def=IAT) + +brain_pin_e getAdcChannelBrainPin(const char *msg, adc_channel_e hwChannel) { + // todo: replace this with an array :) + switch (hwChannel) { + case EFI_ADC_0: + return GPIOB_0; + case EFI_ADC_1: + return GPIOB_1; + case EFI_ADC_2: + return GPIOB_2; + case EFI_ADC_3: + return GPIOB_3; + case EFI_ADC_4: + return GPIOB_4; + case EFI_ADC_5: + return GPIOB_5; + case EFI_ADC_6: + return GPIO_INVALID; + case EFI_ADC_7: + return GPIO_INVALID; + case EFI_ADC_8: + return GPIOB_8; + case EFI_ADC_9: + return GPIOB_9; + case EFI_ADC_10: + return GPIO_INVALID; + case EFI_ADC_11: + return GPIO_INVALID; + case EFI_ADC_12: + return GPIOB_12; + case EFI_ADC_13: + return GPIOB_13; + case EFI_ADC_14: + return GPIOB_14; + case EFI_ADC_15: + return GPIOB_15; + case EFI_ADC_16: + return GPIO_INVALID; + case EFI_ADC_17: + return GPIO_INVALID; + case EFI_ADC_18: + return GPIO_INVALID; + case EFI_ADC_19: + return GPIO_INVALID; + case EFI_ADC_20: + return GPIO_INVALID; + case EFI_ADC_21: + return GPIO_INVALID; + case EFI_ADC_22: + return GPIO_INVALID; + case EFI_ADC_23: + return GPIO_INVALID; + case EFI_ADC_24: + return GPIOC_10; + case EFI_ADC_25: + return GPIOC_9; + case EFI_ADC_26: + return GPIOC_8; + case EFI_ADC_27: + return GPIOC_7; + case EFI_ADC_28: + return GPIOC_5; + case EFI_ADC_29: + return GPIOC_4; + case EFI_ADC_30: + return GPIOC_3; + case EFI_ADC_31: + return GPIOC_2; + default: + firmwareError(CUSTOM_ERR_ADC_UNKNOWN_CHANNEL, "Unknown hw channel %d [%s]", hwChannel, msg); + return GPIO_INVALID; + } +} + +adc_channel_e getAdcChannel(brain_pin_e pin) { + switch (pin) { + case GPIOB_0: + return EFI_ADC_0; + case GPIOB_1: + return EFI_ADC_1; + case GPIOB_2: + return EFI_ADC_2; + case GPIOB_3: + return EFI_ADC_3; + case GPIOB_4: + return EFI_ADC_4; + case GPIOB_5: + return EFI_ADC_5; + case GPIOB_8: + return EFI_ADC_8; + case GPIOB_9: + return EFI_ADC_9; + case GPIOB_12: + return EFI_ADC_12; + case GPIOB_13: + return EFI_ADC_13; + case GPIOB_14: + return EFI_ADC_14; + case GPIOB_15: + return EFI_ADC_15; + case GPIOC_10: + return EFI_ADC_24; + case GPIOC_9: + return EFI_ADC_25; + case GPIOC_8: + return EFI_ADC_26; + case GPIOC_7: + return EFI_ADC_27; + case GPIOC_5: + return EFI_ADC_28; + case GPIOC_4: + return EFI_ADC_29; + case GPIOC_3: + return EFI_ADC_30; + case GPIOC_2: + return EFI_ADC_31; + default: + return EFI_ADC_ERROR; + } +} + +// deprecated - migrate to 'getAdcChannelBrainPin' +ioportid_t getAdcChannelPort(const char *msg, adc_channel_e hwChannel) { + return getHwPort(msg, getAdcChannelBrainPin(msg, hwChannel)); +} + +// deprecated - migrate to 'getAdcChannelBrainPin' +int getAdcChannelPin(adc_channel_e hwChannel) { + return getHwPin("get_pin", getAdcChannelBrainPin("get_pin", hwChannel)); +} + +#endif /* HAL_USE_ADC */ + +#if EFI_PROD_CODE +void jump_to_bootloader() { + // todo: + // Will not return from here + NVIC_SystemReset(); +} +#endif /* EFI_PROD_CODE */ diff --git a/firmware/hw_layer/ports/cypress/cypress_pins.cpp b/firmware/hw_layer/ports/cypress/cypress_pins.cpp new file mode 100644 index 0000000000..9458df3acf --- /dev/null +++ b/firmware/hw_layer/ports/cypress/cypress_pins.cpp @@ -0,0 +1,180 @@ +/** + * @file cypress_pins.cpp + * @brief Cypress-compatible GPIO code + * + * @date Jun 02, 2019 + * @author Andrey Belomutskiy, (c) 2012-2020 + * @author andreika + */ + +#include "global.h" +#include "engine.h" +#include "efi_gpio.h" + +#if EFI_GPIO_HARDWARE + +#define PORT_SIZE 16 + +static ioportid_t ports[] = { + GPIOA, + GPIOB, + GPIOC, + GPIOD, + GPIOE, + GPIOF, + GPIOG, + GPIOH, + GPIOI, + GPIOJ, + GPIOK, +}; + +static brain_pin_e portMap[16] = { + GPIOA_0, GPIOB_0, GPIOC_0, GPIOD_0, GPIOE_0, GPIOF_0, GPIO_INVALID, GPIOG_0, GPIO_INVALID, GPIO_INVALID, GPIOH_0, GPIOI_0, GPIOJ_0, GPIO_INVALID, GPIO_INVALID, GPIOK_0 +}; + +#define PIN_REPO_SIZE (sizeof(ports) / sizeof(ports[0])) * PORT_SIZE +// todo: move this into PinRepository class +static const char *PIN_USED[PIN_REPO_SIZE + BOARD_EXT_PINREPOPINS]; + +#include "pin_repository.h" +#include "io_pins.h" + +/** + * @deprecated - use hwPortname() instead + */ +const char *portname(ioportid_t GPIOx) { + if (GPIOx == GPIOA) + return "P0"; + if (GPIOx == GPIOB) + return "P1"; + if (GPIOx == GPIOC) + return "P2"; + if (GPIOx == GPIOD) + return "P3"; + if (GPIOx == GPIOE) + return "P4"; + if (GPIOx == GPIOF) + return "P5"; + if (GPIOx == GPIOG) + return "P7"; + if (GPIOx == GPIOH) + return "PA"; + if (GPIOx == GPIOI) + return "PB"; + if (GPIOx == GPIOJ) + return "PC"; + if (GPIOx == GPIOK) + return "PF"; + return "unknown"; +} + +static int getPortIndex(ioportid_t port) { + efiAssert(CUSTOM_ERR_ASSERT, port != NULL, "null port", -1); + if (port == GPIOA) + return 0; + if (port == GPIOB) + return 1; + if (port == GPIOC) + return 2; + if (port == GPIOD) + return 3; + if (port == GPIOE) + return 4; + if (port == GPIOF) + return 5; + if (port == GPIOG) + return 6; + if (port == GPIOH) + return 7; + if (port == GPIOI) + return 8; + if (port == GPIOJ) + return 9; + if (port == GPIOK) + return 10; + firmwareError(CUSTOM_ERR_UNKNOWN_PORT, "unknown port"); + return -1; +} + +ioportid_t getBrainPort(brain_pin_e brainPin) { + return ports[(brainPin - GPIOA_0) / PORT_SIZE]; +} + +int getBrainPinIndex(brain_pin_e brainPin) { + return (brainPin - GPIOA_0) % PORT_SIZE; +} + +int getBrainIndex(ioportid_t port, ioportmask_t pin) { + int portIndex = getPortIndex(port); + return portIndex * PORT_SIZE + pin; +} + +ioportid_t getHwPort(const char *msg, brain_pin_e brainPin) { + if (brainPin == GPIO_UNASSIGNED || brainPin == GPIO_INVALID) + return GPIO_NULL; + if (brainPin < GPIOA_0 || brainPin > BRAIN_PIN_LAST_ONCHIP) { + firmwareError(CUSTOM_ERR_INVALID_PIN, "%s: Invalid brain_pin_e: %d", msg, brainPin); + return GPIO_NULL; + } + return ports[(brainPin - GPIOA_0) / PORT_SIZE]; +} + +/** + * this method returns the numeric part of pin name. For instance, for PC13 this would return '13' + */ +ioportmask_t getHwPin(const char *msg, brain_pin_e brainPin) +{ + if (brainPin == GPIO_UNASSIGNED || brainPin == GPIO_INVALID) + return EFI_ERROR_CODE; + + if (brain_pin_is_onchip(brainPin)) + return getBrainPinIndex(brainPin); + + firmwareError(CUSTOM_ERR_INVALID_PIN, "%s: Invalid on-chip brain_pin_e: %d", msg, brainPin); + return EFI_ERROR_CODE; +} + +/** + * Parse string representation of physical pin into brain_pin_e ordinal. + * + * @return GPIO_UNASSIGNED for "none", GPIO_INVALID for invalid entry + */ +brain_pin_e parseBrainPin(const char *str) { + if (strEqual(str, "none")) + return GPIO_UNASSIGNED; + // todo: create method toLowerCase? + if (str[0] != 'p' && str[0] != 'P') { + return GPIO_INVALID; + } + char port = str[1]; + if (port >= 'a' && port <= 'z') { + port = 10 + (port - 'a'); + } else if (port >= 'A' && port <= 'Z') { + port = 10 + (port - 'A'); + } else if (port >= '0' && port <= '9') { + port = 0 + (port - '0'); + } else { + return GPIO_INVALID; + } + brain_pin_e basePin = portMap[(int)port]; + if (basePin == GPIO_INVALID) + return GPIO_INVALID; + const char *pinStr = str + 2; + int pin = atoi(pinStr); + return (brain_pin_e)(basePin + pin); +} + +unsigned int getNumBrainPins(void) { + return PIN_REPO_SIZE; +} + +void initBrainUsedPins(void) { + memset(PIN_USED, 0, sizeof(PIN_USED)); +} + +const char* & getBrainUsedPin(unsigned int idx) { + return PIN_USED[idx]; +} + +#endif /* EFI_GPIO_HARDWARE */ diff --git a/firmware/hw_layer/ports/cypress/flash.c b/firmware/hw_layer/ports/cypress/flash.c new file mode 100644 index 0000000000..dbed2a8cae --- /dev/null +++ b/firmware/hw_layer/ports/cypress/flash.c @@ -0,0 +1,135 @@ +/** + * + * @file flash.c + * @brief Lower-level code for Cypress related to internal flash memory + * @author andreika + */ + +#include "global.h" + +#if EFI_INTERNAL_FLASH + +#include "flash.h" +#include + + +// todo: add DualFlash support + +//#define CYPRESS_FLASH_DEBUG + +typedef uint32_t flashdata_t; + +static volatile uint32_t mainFlashMap[] = { + 0x00000000, 0x00002000, 0x00004000, 0x00006000, 0x00008000, + 0x00010000, 0x00020000, 0x00030000, 0x00040000, 0x00050000, + 0x00060000, 0x00070000, 0x00080000, 0x00090000, 0x000A0000, + 0x000B0000, 0x000C0000, 0x000D0000, 0x000E0000, 0x000F0000, + 0x00100000, 0x00102000, 0x00104000, 0x00106000, 0x00108000, + 0x00110000, 0x00120000, 0x00130000, 0x00140000, 0x00150000, + 0x00160000, 0x00170000, 0x00180000, + // todo: add upper 40k flash area +}; + +bool flashUnlock(void) { + return true; +} + +bool flashLock(void) { + return true; +} + +#define CYPRESS_FLASH_WORD_ALIGNMENT 2 + +static int alignToWord(int v) { + return (v + CYPRESS_FLASH_WORD_ALIGNMENT - 1) & ~(CYPRESS_FLASH_WORD_ALIGNMENT - 1); +} + +static __attribute__((optimize("O0"))) int flashSectorEraseAtAddress(volatile uint32_t sectorStart) { + return MFlash_SectorErase((uint16_t*)sectorStart) != Ok ? FLASH_RETURN_BAD_FLASH : FLASH_RETURN_SUCCESS; +} + +int __attribute__((optimize("O0"))) flashErase(flashaddr_t address, size_t size) { + // todo: this is a temporary hack + // todo: why the code below doesn't work with -O2?! + if (flashSectorEraseAtAddress(address) != FLASH_RETURN_SUCCESS) { + return FLASH_RETURN_BAD_FLASH; + } +#if 0 + volatile int i; + size = alignToWord(size); + + volatile int numSectors = (sizeof(mainFlashMap) / sizeof(mainFlashMap[0])) - 1; + // list through all sectors and erase those inside the given memory area + for (i = 0; i < numSectors; i++) { + volatile uint32_t sectorStart = mainFlashMap[i]; + volatile uint32_t sectorEnd = mainFlashMap[i + 1] - 1; + // if the sector overlaps the address range + if (sectorStart < (address + size) && sectorEnd >= address) { + if (flashSectorEraseAtAddress(sectorStart) != FLASH_RETURN_SUCCESS) { + return FLASH_RETURN_BAD_FLASH; + } + // check if erased + size_t sectorSize = sectorEnd - sectorStart + 1; + if (flashIsErased(sectorStart, sectorSize) == FALSE) + return FLASH_RETURN_BAD_FLASH; /* Sector is not empty despite the erase cycle! */ + + } + } +#endif + /* Successfully deleted sector */ + return FLASH_RETURN_SUCCESS; +} + +int flashWrite(flashaddr_t address, const char* buffer, size_t size) { + uint32_t sizeInWords = alignToWord(size) >> 1; + return MFlash_WriteData16Bit((uint16_t*)address, (uint16_t*)buffer, sizeInWords) == Ok ? FLASH_RETURN_SUCCESS : FLASH_RETURN_BAD_FLASH; + //return MFlash_WriteData16Bit_Fm0Type3CrSecureArea((uint16_t*)address, (uint16_t*)buffer, sizeInWords) == Ok ? 0 : -1; +} + +bool flashIsErased(flashaddr_t address, size_t size) { + /* Check for default set bits in the flash memory + * For efficiency, compare flashdata_t values as much as possible, + * then, fallback to byte per byte comparison. */ + while (size >= sizeof(flashdata_t)) { + if (*(volatile flashdata_t*) address != (flashdata_t) (-1)) // flashdata_t being unsigned, -1 is 0xFF..FF + return false; + address += sizeof(flashdata_t); + size -= sizeof(flashdata_t); + } + while (size > 0) { + if (*(char*) address != 0xFF) + return false; + ++address; + --size; + } + + return TRUE; +} + +bool flashCompare(flashaddr_t address, const char* buffer, size_t size) { + /* For efficiency, compare flashdata_t values as much as possible, + * then, fallback to byte per byte comparison. */ + while (size >= sizeof(flashdata_t)) { + if (*(volatile flashdata_t*) address != *(flashdata_t*) buffer) + return FALSE; + address += sizeof(flashdata_t); + buffer += sizeof(flashdata_t); + size -= sizeof(flashdata_t); + } + while (size > 0) { + if (*(volatile char*) address != *buffer) + return FALSE; + ++address; + ++buffer; + --size; + } + + return TRUE; +} + +int flashRead(flashaddr_t address, char* buffer, size_t size) { + memcpy(buffer, (char*) address, size); + return FLASH_RETURN_SUCCESS; +} + +#endif /* EFI_INTERNAL_FLASH */ diff --git a/firmware/hw_layer/ports/cypress/hw_ports.mk b/firmware/hw_layer/ports/cypress/hw_ports.mk new file mode 100644 index 0000000000..1b766c27c1 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/hw_ports.mk @@ -0,0 +1,16 @@ +ifeq ($(CYPRESS_CONTRIB),) + CYPRESS_CONTRIB = $(CHIBIOS_CONTRIB) +endif + +HW_LAYER_EGT = $(PROJECT_DIR)/hw_layer/ports/cypress/serial_over_usb/usbconfig.c \ + $(PROJECT_DIR)/hw_layer/ports/cypress/serial_over_usb/usbconsole.c + +HW_LAYER_EMS += $(PROJECT_DIR)/hw_layer/ports/cypress/flash.c + +HW_LAYER_EMS_CPP += $(PROJECT_DIR)/hw_layer/ports/cypress/mpu_util.cpp \ + $(PROJECT_DIR)/hw_layer/ports/cypress/cypress_pins.cpp \ + $(PROJECT_DIR)/hw_layer/ports/cypress/cypress_common.cpp \ + $(PROJECT_DIR)/hw_layer/ports/cypress/backup_ram.cpp \ + $(PROJECT_DIR)/hw_layer/trigger_input_adc.cpp + +HW_INC += $(PROJECT_DIR)/hw_layer/ports/cypress/serial_over_usb diff --git a/firmware/hw_layer/ports/cypress/mpu_util.cpp b/firmware/hw_layer/ports/cypress/mpu_util.cpp new file mode 100644 index 0000000000..b029516471 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/mpu_util.cpp @@ -0,0 +1,253 @@ +/** + * @file mpu_util.cpp + * + * @date Jul 27, 2014 + * @author Andrey Belomutskiy, (c) 2012-2020 + * @author andreika + */ + +#include "global.h" + +#if EFI_PROD_CODE + +#include "mpu_util.h" +#include "flash.h" +#include "engine.h" +#include "pin_repository.h" +#include "os_util.h" + +EXTERN_ENGINE; + +extern "C" { + void _unhandled_exception(void); + void DebugMonitorVector(void); + void UsageFaultVector(void); + void BusFaultVector(void); + void HardFaultVector(void); +} + +void baseMCUInit(void) { +} + +void _unhandled_exception(void) { +/*lint -restore*/ + + chDbgPanic3("_unhandled_exception", __FILE__, __LINE__); + while (true) { + } +} + +void DebugMonitorVector(void) { + chDbgPanic3("DebugMonitorVector", __FILE__, __LINE__); + while (TRUE) + ; +} + +void UsageFaultVector(void) { + chDbgPanic3("UsageFaultVector", __FILE__, __LINE__); + while (TRUE) + ; +} + +void BusFaultVector(void) { + chDbgPanic3("BusFaultVector", __FILE__, __LINE__); + while (TRUE) { + } +} + +void HardFaultVector(void) { + while (TRUE) { + } +} + +#if HAL_USE_SPI || defined(__DOXYGEN__) +bool isSpiInitialized[5] = { false, false, false, false, false }; + +static int getSpiAf(SPIDriver *driver) { +#if STM32_SPI_USE_SPI1 + if (driver == &SPID1) { + return EFI_SPI1_AF; + } +#endif +#if STM32_SPI_USE_SPI2 + if (driver == &SPID2) { + return EFI_SPI2_AF; + } +#endif +#if STM32_SPI_USE_SPI3 + if (driver == &SPID3) { + return EFI_SPI3_AF; + } +#endif + return -1; +} + +brain_pin_e getMisoPin(spi_device_e device) { + switch(device) { + case SPI_DEVICE_1: + return CONFIG(spi1misoPin); + case SPI_DEVICE_2: + return CONFIG(spi2misoPin); + case SPI_DEVICE_3: + return CONFIG(spi3misoPin); + default: + break; + } + return GPIO_UNASSIGNED; +} + +brain_pin_e getMosiPin(spi_device_e device) { + switch(device) { + case SPI_DEVICE_1: + return CONFIG(spi1mosiPin); + case SPI_DEVICE_2: + return CONFIG(spi2mosiPin); + case SPI_DEVICE_3: + return CONFIG(spi3mosiPin); + default: + break; + } + return GPIO_UNASSIGNED; +} + +brain_pin_e getSckPin(spi_device_e device) { + switch(device) { + case SPI_DEVICE_1: + return CONFIG(spi1sckPin); + case SPI_DEVICE_2: + return CONFIG(spi2sckPin); + case SPI_DEVICE_3: + return CONFIG(spi3sckPin); + default: + break; + } + return GPIO_UNASSIGNED; +} + +void turnOnSpi(spi_device_e device) { + if (isSpiInitialized[device]) + return; // already initialized + isSpiInitialized[device] = true; + if (device == SPI_DEVICE_1) { +// todo: introduce a nice structure with all fields for same SPI +#if STM32_SPI_USE_SPI1 +// scheduleMsg(&logging, "Turning on SPI1 pins"); + initSpiModule(&SPID1, getSckPin(device), + getMisoPin(device), + getMosiPin(device), + engineConfiguration->spi1SckMode, + engineConfiguration->spi1MosiMode, + engineConfiguration->spi1MisoMode); +#endif /* STM32_SPI_USE_SPI1 */ + } + if (device == SPI_DEVICE_2) { +#if STM32_SPI_USE_SPI2 +// scheduleMsg(&logging, "Turning on SPI2 pins"); + initSpiModule(&SPID2, getSckPin(device), + getMisoPin(device), + getMosiPin(device), + engineConfiguration->spi2SckMode, + engineConfiguration->spi2MosiMode, + engineConfiguration->spi2MisoMode); +#endif /* STM32_SPI_USE_SPI2 */ + } + if (device == SPI_DEVICE_3) { +#if STM32_SPI_USE_SPI3 +// scheduleMsg(&logging, "Turning on SPI3 pins"); + initSpiModule(&SPID3, getSckPin(device), + getMisoPin(device), + getMosiPin(device), + engineConfiguration->spi3SckMode, + engineConfiguration->spi3MosiMode, + engineConfiguration->spi3MisoMode); +#endif /* STM32_SPI_USE_SPI3 */ + } +} + +void initSpiModule(SPIDriver *driver, brain_pin_e sck, brain_pin_e miso, + brain_pin_e mosi, + int sckMode, + int mosiMode, + int misoMode) { + + /** + * See https://github.com/rusefi/rusefi/pull/664/ + * + * Info on the silicon defect can be found in this document, section 2.5.2: + * https://www.st.com/content/ccc/resource/technical/document/errata_sheet/0a/98/58/84/86/b6/47/a2/DM00037591.pdf/files/DM00037591.pdf/jcr:content/translations/en.DM00037591.pdf + */ + efiSetPadMode("SPI clock", sck, PAL_MODE_ALTERNATE(getSpiAf(driver)) /*| sckMode | PAL_STM32_OSPEED_HIGHEST*/); + + efiSetPadMode("SPI master out", mosi, PAL_MODE_ALTERNATE(getSpiAf(driver)) /*| mosiMode | PAL_STM32_OSPEED_HIGHEST*/); + efiSetPadMode("SPI master in ", miso, PAL_MODE_ALTERNATE(getSpiAf(driver)) /*| misoMode | PAL_STM32_OSPEED_HIGHEST*/); +} + +void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin) { + spiConfig->end_cb = NULL; + ioportid_t port = getHwPort("spi", csPin); + ioportmask_t pin = getHwPin("spi", csPin); + spiConfig->ssport = port; + spiConfig->sspad = pin; + // CS is controlled inside 'hal_spi_lld' driver using both software and hardware methods. + //efiSetPadMode("chip select", csPin, PAL_MODE_OUTPUT_OPENDRAIN); +} + +#endif /* HAL_USE_SPI */ + +BOR_Level_t BOR_Get(void) { + return BOR_Level_None; +} + +BOR_Result_t BOR_Set(BOR_Level_t BORValue) { + return BOR_Result_Ok; +} + +#if EFI_CAN_SUPPORT || defined(__DOXYGEN__) + +static bool isValidCan1RxPin(brain_pin_e pin) { + return pin == GPIOA_11 || pin == GPIOB_8 || pin == GPIOD_0; +} + +static bool isValidCan1TxPin(brain_pin_e pin) { + return pin == GPIOA_12 || pin == GPIOB_9 || pin == GPIOD_1; +} + +static bool isValidCan2RxPin(brain_pin_e pin) { + return pin == GPIOB_5 || pin == GPIOB_12; +} + +static bool isValidCan2TxPin(brain_pin_e pin) { + return pin == GPIOB_6 || pin == GPIOB_13; +} + +bool isValidCanTxPin(brain_pin_e pin) { + return isValidCan1TxPin(pin) || isValidCan2TxPin(pin); +} + +bool isValidCanRxPin(brain_pin_e pin) { + return isValidCan1RxPin(pin) || isValidCan2RxPin(pin); +} + +CANDriver * detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx) { + if (isValidCan1RxPin(pinRx) && isValidCan1TxPin(pinTx)) + return &CAND1; + if (isValidCan2RxPin(pinRx) && isValidCan2TxPin(pinTx)) + return &CAND2; + return NULL; +} + +#endif /* EFI_CAN_SUPPORT */ + +size_t flashSectorSize(flashsector_t sector) { + // sectors 0..11 are the 1st memory bank (1Mb), and 12..23 are the 2nd (the same structure). + if (sector <= 3 || (sector >= 12 && sector <= 15)) + return 16 * 1024; + else if (sector == 4 || sector == 16) + return 64 * 1024; + else if ((sector >= 5 && sector <= 11) || (sector >= 17 && sector <= 23)) + return 128 * 1024; + return 0; +} + +#endif /* EFI_PROD_CODE */ + diff --git a/firmware/hw_layer/ports/cypress/mpu_util.h b/firmware/hw_layer/ports/cypress/mpu_util.h new file mode 100644 index 0000000000..6bca3aacf5 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/mpu_util.h @@ -0,0 +1,92 @@ +/** + * @file mpu_util.h + * + * @date Jul 27, 2014 + * @author Andrey Belomutskiy, (c) 2012-2020 + * @author andreika + */ + +#ifndef MPU_UTIL_H_ +#define MPU_UTIL_H_ + +// we are lucky - all CAN pins use the same AF +#define EFI_CAN_RX_AF 9 +#define EFI_CAN_TX_AF 9 + +// burnout or 'Burn Out' +typedef enum { + BOR_Level_None = 0, + BOR_Level_1 = 1, + BOR_Level_2 = 2, + BOR_Level_3 = 3 +} BOR_Level_t; + +typedef enum { + BOR_Result_Ok = 0x00, + BOR_Result_Error +} BOR_Result_t; + +BOR_Level_t BOR_Get(void); +BOR_Result_t BOR_Set(BOR_Level_t BORValue); + +#ifndef ADC_TwoSamplingDelay_5Cycles +#define ADC_TwoSamplingDelay_5Cycles ((uint32_t)0x00000000) +#endif + +#ifndef ADC_TwoSamplingDelay_20Cycles +#define ADC_TwoSamplingDelay_20Cycles ((uint32_t)0x00000F00) +#endif + +#ifndef ADC_CR2_SWSTART +#define ADC_CR2_SWSTART ((uint32_t)0x40000000) +#endif + +#define SPI_CR1_8BIT_MODE 0 +#define SPI_CR2_8BIT_MODE 0 + +#define SPI_CR1_16BIT_MODE SPI_CR1_DFF +#define SPI_CR2_16BIT_MODE 0 + +// TODO +#define SPI_CR1_24BIT_MODE 0 +#define SPI_CR2_24BIT_MODE 0 + +void baseMCUInit(void); +void turnOnSpi(spi_device_e device); +void jump_to_bootloader(); + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +// these need to be declared C style for the linker magic to work + +void DebugMonitorVector(void); +void UsageFaultVector(void); +void BusFaultVector(void); +void HardFaultVector(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#if HAL_USE_SPI +void initSpiModule(SPIDriver *driver, brain_pin_e sck, brain_pin_e miso, + brain_pin_e mosi, + int sckMode, + int mosiMode, + int misoMode); +/** + * @see getSpiDevice + */ +void initSpiCs(SPIConfig *spiConfig, brain_pin_e csPin); +#endif /* HAL_USE_SPI */ + +bool isValidCanTxPin(brain_pin_e pin); +bool isValidCanRxPin(brain_pin_e pin); +#if HAL_USE_CAN +CANDriver * detectCanDevice(brain_pin_e pinRx, brain_pin_e pinTx); +#endif /* HAL_USE_CAN */ + +#endif /* MPU_UTIL_H_ */ diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.c b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.c new file mode 100644 index 0000000000..950c2005fd --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.c @@ -0,0 +1,895 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/************************************************************************/ +/** \file usbconfig.c + ** + ** Part of USB Driver Module + ** + ** A detailed description is available at + ** @link UsbConfigGroup USB Device Cdc Com Module description @endlink + ** + ** History: + ** - 2012-08-24 2.0 MSc New Version for use with M3 L3 USB driver + ** - 2012-10-02 2.1 MSc use of external interrupts without L3 implemented + ** - 2012-11-22 2.2 MSc minor bug fixes + ** - 2015-05-05 2.3 MSCH updated to latest version, changed + ** !USB_DISBALE_..._FUNCTIONALITY to FM_PERIPHERAL_USB_..._ENABLED + *****************************************************************************/ + +/******************************************************************************/ +/* Include files */ +/******************************************************************************/ + +#include "pdl_header.h" +#include "usb.h" + +/** + ****************************************************************************** + ** \defgroup UsbConfigGroup USB Config + ** + ** Provided functions of USB module: + ** + ** - UsbConfig_UsbInit() + ** - UsbConfig_SwitchMode() + ** - UsbConfig_Device0Vbus() + ** - UsbConfig_Device1Vbus() + ** - UsbConfig_Host0Overcurrent() + ** - UsbConfig_Host1Overcurrent() + ** - UsbConfig_Host0Vbus() + ** - UsbConfig_Host1Vbus() + ** - UsbConfig_Host0PulldownHostEnable() + ** - UsbConfig_Host1PulldownHostEnable() + ** - UsbDevice_Usb0ExintCallback() + ** - UsbDevice_Usb1ExintCallback() + ** + ** Used to initialize and configure the USB HAL. It gives an example how to initialize + ** all USB parts. UsbConfig_UsbInit() is used to setup USB host and device mode for USB0 and USB1. + ** UsbConfig_SwitchMode() is used to detect the Device VBUS and to do the Host / Device switching. + ** UsbConfig_DeviceVbus() is used to do GPIO read or write for the Device VBUS detection pin. + ** UsbConfig_DeviceVbus() is defined as callback for the USB stack. + ** UsbConfig_HostOvercurrent() is used to do GPIO read or write for the Host overcurrent detection. + ** UsbConfig_HostOvercurrent() is defined as callback for the USB stack. + ** UsbConfig_HostVbus() is used to do GPIO read or write for the Host VBUS enable. + ** UsbConfig_HostVbus() is defined as callback for the USB stack. + ** UsbConfig_HostPulldownHostEnable() is used to do GPIO read or write to enable the Host 15K pulldowns (externally). + ** UsbConfig_HostPulldownHostEnable() is defined as callback for the USB stack. + ** UsbDevice_UsbExintCallback() is used if the Device VBUS detection is done by IRQ. + ** UsbDevice_UsbExintCallback() is called from an external IRQ pin. + ** + ******************************************************************************/ +//@{ + +/** + ****************************************************************************** + ** \page usbconfig_module_includes Required includes in main application + ** \brief Following includes are required + ** @code + ** #include "usb.h" + ** @endcode + ** + ******************************************************************************/ + +/** + ****************************************************************************** + ** \page usbconfig_module_init Example: Initialization + ** \brief Following initialization is required + ** + ** @code + ** UsbConfig_UsbInit(); + ** @endcode + ** + ******************************************************************************/ + +/** + ****************************************************************************** + ** \page usbconfig_example_main Example: Whole example + ** @code + ** #include "usb.h" + ** + ** + ** int main() + ** { + ** + ** // other initializations + ** + ** UsbConfig_UsbInit(); + ** + ** // other initializations + ** + ** for(;;) + ** { + ** UsbConfig_SwitchMode(); //must be called periodically to do VBUS detection + ** //or Host / Device switching + ** + ** // application code + ** } + ** } + ** @endcode + ** + ******************************************************************************/ + +#if ((FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) || (FM_PERIPHERAL_USB_HOST_ENABLED == ON)) + +#if (FM_PERIPHERAL_USB_DEVICE_ENABLED == ON) + #include "usbdevice.h" + #if ((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1)) + #include "usbdevicehw.h" + #endif + #if ((USE_USBDESCRIPTORS_H == 1) || (USB_USE_PDL == 1)) + #include "usbdescriptors.h" + #endif +#endif +#if (FM_PERIPHERAL_USB_HOST_ENABLED == ON) + #include "usbhost.h" + #if ((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1)) + #include "usbhosthw.h" + #endif +#endif + +#if (USBDEVICECDCCOM_ENABLED == ON) + #include "UsbDeviceCdcCom.h" +#endif +#if (USBDEVICEHIDCOM_ENABLED == ON) + #include "UsbDeviceHidCom.h" +#endif +#if (USBDEVICEHIDJOYSTICK_ENABLED == ON) + #include "UsbDeviceHidJoystick.h" +#endif +#if (USBDEVICEHIDKEYBOARD_ENABLED == ON) + #include "UsbDeviceHidKeyboard.h" +#endif +#if (USBDEVICEHIDMOUSE_ENABLED == ON) + #include "UsbDeviceHidMouse.h" +#endif +#if (USBDEVICELIBUSB_ENABLED == ON) + #include "UsbDeviceLibUsb.h" +#endif +#if (USBDEVICEPRINTER_ENABLED == ON) + #include "UsbDevicePrinter.h" +#endif +#if USBHOSTHIDMOUSE_ENABLED == ON + #include "UsbHostHidMouse.h" +#endif +#if USBHOSTHIDKEYBOARD_ENABLED == ON + #include "UsbHostHidKeyboard.h" +#endif +#if (USBDEVICEMASSSTORAGE_ENABLED == ON) + #include "UsbDeviceMassStorage.h" +#endif +/******************************************************************************/ +/* Local pre-processor symbols/macros ('#define') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + +/******************************************************************************/ +/* Local function prototypes ('static') */ +/******************************************************************************/ + +#if FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON +static void UsbConfig_UsbDeviceClassesInitCallback0(stc_usbn_t* pstcUSB); +#endif + +#if FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON +static void UsbConfig_UsbDeviceClassesInitCallback1(stc_usbn_t* pstcUSB); +#endif + +#ifdef __USBDEVICEHW_H__ + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1)))) + static boolean_t UsbConfig_Device0Vbus(en_usb_extint_param_t enType); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1)))) + static boolean_t UsbConfig_Device1Vbus(en_usb_extint_param_t enType); + #endif +#endif +#ifdef __USBHOSTHW_H__ + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1)))) + boolean_t UsbConfig_Host0Overcurrent(en_usb_extint_param_t enType); + boolean_t UsbConfig_Host0Vbus(en_usb_gpio_param_t enType); + boolean_t UsbConfig_Host0PulldownHostEnable(en_usb_gpio_param_t enType); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1)))) + boolean_t UsbConfig_Host1Overcurrent(en_usb_extint_param_t enType); + boolean_t UsbConfig_Host1Vbus(en_usb_gpio_param_t enType); + boolean_t UsbConfig_Host1PulldownHostEnable(en_usb_gpio_param_t enType); + #endif +#endif + +#if FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON +static void UsbConfig_UsbDeviceClassesInitCallback0(stc_usbn_t* pstcUSB) +{ + #if (USBDEVICECDCCOM_ENABLED == ON) + UsbDeviceCdcCom_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICEHIDCOM_ENABLED == ON) + UsbDeviceHidCom_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICEHIDJOYSTICK_ENABLED == ON) + UsbDeviceHidJoystick_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICEHIDKEYBOARD_ENABLED == ON) + UsbDeviceHidKeyboard_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICEHIDMOUSE_ENABLED == ON) + UsbDeviceHidMouse_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICELIBUSB_ENABLED == ON) + UsbDeviceLibUsb_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICEPRINTER_ENABLED == ON) + UsbDevicePrinter_Init((stc_usbn_t*)&USB0); + #endif + #if (USBDEVICEMASSSTORAGE_ENABLED == ON) + UsbDeviceMassStorage_Init((stc_usbn_t*)&USB0); + #endif + /* USB0 WIZARD DEVICECLASSINIT */ +} +#endif + +#if FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON +static void UsbConfig_UsbDeviceClassesInitCallback1(stc_usbn_t* pstcUSB) +{ + #if (USBDEVICECDCCOM_ENABLED == ON) + UsbDeviceCdcCom_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICEHIDCOM_ENABLED == ON) + UsbDeviceHidCom_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICEHIDJOYSTICK_ENABLED == ON) + UsbDeviceHidJoystick_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICEHIDKEYBOARD_ENABLED == ON) + UsbDeviceHidKeyboard_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICEHIDMOUSE_ENABLED == ON) + UsbDeviceHidMouse_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICELIBUSB_ENABLED == ON) + UsbDeviceLibUsb_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICEPRINTER_ENABLED == ON) + UsbDevicePrinter_Init((stc_usbn_t*)&USB1); + #endif + #if (USBDEVICEMASSSTORAGE_ENABLED == ON) + UsbDeviceMassStorage_Init((stc_usbn_t*)&USB1); + #endif + /* USB1 WIZARD DEVICECLASSINIT */ +} +#endif + +/******************************************************************************/ +/* Global variable definitions (declared in header file with 'extern') */ +/******************************************************************************/ + + + + + + + + +/** + ****************************************************************************** + ** \brief Initialize USB + ** + ******************************************************************************/ +void UsbConfig_UsbInit(void) +{ + stc_usb_config_t stcUsbConfig; + #if (!defined(USB_DISBALE_DEVICE_FUNCTIONALITY)) + stc_usbdevice_config_t stcUsbDeviceConfig; + #endif + + Usb_Init(); + + + /* Setup USB 0 */ + USB_ZERO_STRUCT(stcUsbConfig); + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED) + USB_ZERO_STRUCT(stcUsbDeviceConfig); + #endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED) */ + + #if ((FM_PERIPHERAL_ENABLE_USB0_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON)) + stcUsbConfig.enMode = UsbHostDeviceEnabled; + #elif ((FM_PERIPHERAL_ENABLE_USB0_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == OFF)) + stcUsbConfig.enMode = UsbHostEnabled; + #elif ((FM_PERIPHERAL_ENABLE_USB0_HOST == OFF) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON)) + stcUsbConfig.enMode = UsbDeviceEnabled; + #endif + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED) + #if ((USE_USBDESCRIPTORS_H == 1) || (USB_USE_PDL == 1)) + stcUsbDeviceConfig.pu8DeviceDescriptor = (uint8_t*)au8DeviceDescriptor; + stcUsbDeviceConfig.pu8ConfigDescriptor = (uint8_t*)au8ConfigDescriptor; + stcUsbDeviceConfig.astcReportDescriptors = (stc_usbdevice_reportdescriptor_t*)astcReportDescriptors; + stcUsbDeviceConfig.pstcStringDescriptors = (stc_usbdevice_stringdescriptor_t*)pstcStringDescriptors; + stcUsbDeviceConfig.u8StringDescriptorCount = USBDESCRIPTORS_STRINGDESCRIPTOR_COUNT; + #endif /* ((USE_USBDESCRIPTORS_H == 1) || (USB_USE_PDL == 1)) */ + #endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED) */ + + stcUsbConfig.bUseInterrupts = TRUE; + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED) + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && ((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1))) + stcUsbConfig.pfnDeviceVbus = UsbConfig_Device0Vbus; + #endif + #endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED) */ + + #if ((FM_PERIPHERAL_USB_HOST_ENABLED)) + #if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && ((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1))) + stcUsbConfig.pfnHostVbus = UsbConfig_Host0Vbus; + stcUsbConfig.pfnHostPullDownHostEnable = UsbConfig_Host0PulldownHostEnable; + stcUsbConfig.pfnHostOvercurrent = UsbConfig_Host0Overcurrent; + #endif + #endif /* ((FM_PERIPHERAL_USB_HOST_ENABLED)) */ + + #if FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON + stcUsbDeviceConfig.pfnInitClassesCallback = UsbConfig_UsbDeviceClassesInitCallback0; + #endif + + #if FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON + UsbDevice_Init((stc_usbn_t*)&USB0,&stcUsbConfig,&stcUsbDeviceConfig); + #endif + + #if FM_PERIPHERAL_ENABLE_USB0 == ON + #if FM_PERIPHERAL_ENABLE_USB0_HOST == ON + UsbHost_Init((stc_usbn_t*)&USB0,&stcUsbConfig); + #endif + Usb_Configure((stc_usbn_t*)&USB0,&stcUsbConfig); + #endif + + + + + /* Setup USB 1 */ + USB_ZERO_STRUCT(stcUsbConfig); + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED) + USB_ZERO_STRUCT(stcUsbDeviceConfig); + #endif + + #if ((FM_PERIPHERAL_ENABLE_USB1_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON)) + stcUsbConfig.enMode = UsbHostDeviceEnabled; + #elif ((FM_PERIPHERAL_ENABLE_USB1_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == OFF)) + stcUsbConfig.enMode = UsbHostEnabled; + #elif ((FM_PERIPHERAL_ENABLE_USB1_HOST == OFF) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON)) + stcUsbConfig.enMode = UsbDeviceEnabled; + #endif + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED) + #if ((USE_USBDESCRIPTORS_H == 1) || (USB_USE_PDL == 1)) + stcUsbDeviceConfig.pu8DeviceDescriptor = (uint8_t*)au8DeviceDescriptor; + stcUsbDeviceConfig.pu8ConfigDescriptor = (uint8_t*)au8ConfigDescriptor; + stcUsbDeviceConfig.astcReportDescriptors = (stc_usbdevice_reportdescriptor_t*)astcReportDescriptors; + stcUsbDeviceConfig.pstcStringDescriptors = (stc_usbdevice_stringdescriptor_t*)pstcStringDescriptors; + stcUsbDeviceConfig.u8StringDescriptorCount = USBDESCRIPTORS_STRINGDESCRIPTOR_COUNT; + #endif + #endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED) */ + + stcUsbConfig.bUseInterrupts = TRUE; + + #if (FM_PERIPHERAL_USB_DEVICE_ENABLED) + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && ((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1))) + stcUsbConfig.pfnDeviceVbus = UsbConfig_Device1Vbus; + #endif + #endif /* (FM_PERIPHERAL_USB_DEVICE_ENABLED) */ + + #if (FM_PERIPHERAL_USB_HOST_ENABLED) + #if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && ((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1))) + stcUsbConfig.pfnHostVbus = UsbConfig_Host1Vbus; + stcUsbConfig.pfnHostPullDownHostEnable = UsbConfig_Host1PulldownHostEnable; + stcUsbConfig.pfnHostOvercurrent = UsbConfig_Host1Overcurrent; + #endif + #endif /* (FM_PERIPHERAL_USB_HOST_ENABLED) */ + + #if FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON + stcUsbDeviceConfig.pfnInitClassesCallback = UsbConfig_UsbDeviceClassesInitCallback1; + #endif + + #if FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON + UsbDevice_Init((stc_usbn_t*)&USB1,&stcUsbConfig,&stcUsbDeviceConfig); + #endif + + #if FM_PERIPHERAL_ENABLE_USB1 == ON + #if FM_PERIPHERAL_ENABLE_USB1_HOST == ON + UsbHost_Init((stc_usbn_t*)&USB1,&stcUsbConfig); + #endif + Usb_Configure((stc_usbn_t*)&USB1,&stcUsbConfig); + #endif +} + +#ifdef __USBDEVICEHW_H__ + +#if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1)))) +/** + ****************************************************************************** + ** \brief Device 0 VBUS GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +static boolean_t UsbConfig_Device0Vbus(en_usb_extint_param_t enType) +{ + switch(enType) + { + case UsbExtIntDeinit: + DEVICE0VBUS_DEINIT; + break; + case UsbExtIntInit: + DEVICE0VBUS_INIT; + break; + case UsbExtIntDisableIsr: + DEVICE0VBUS_DISABLEISR; + break; + case UsbExtIntEnableIsr: + DEVICE0VBUS_ENABLEISR; + break; + case UsbExtIntClearIsrFlag: + DEVICE0VBUS_CLEARISRFLAG; + break; + case UsbExtIntIsSetIsrFlag: + return DEVICE0VBUS_ISRISSET; + case UsbExtIntSetLowDetect: + DEVICE0VBUS_SETLOWDETECT; + break; + case UsbExtIntSetHighDetect: + DEVICE0VBUS_SETHIGHDETECT; + break; + case UsbExtIntGetLevel: + return DEVICE0VBUS_HIGHDETECT; + } + return FALSE; +} +#endif + +#if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && ((USE_USBDEVICEHW_H == 1) || (USB_USE_PDL == 1))) +/** + ****************************************************************************** + ** \brief Device 1 VBUS GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +static boolean_t UsbConfig_Device1Vbus(en_usb_extint_param_t enType) +{ + switch(enType) + { + case UsbExtIntDeinit: + DEVICE1VBUS_DEINIT; + break; + case UsbExtIntInit: + DEVICE1VBUS_INIT; + break; + case UsbExtIntDisableIsr: + DEVICE1VBUS_DISABLEISR; + break; + case UsbExtIntEnableIsr: + DEVICE1VBUS_ENABLEISR; + break; + case UsbExtIntClearIsrFlag: + DEVICE1VBUS_CLEARISRFLAG; + break; + case UsbExtIntIsSetIsrFlag: + return DEVICE1VBUS_ISRISSET; + break; + case UsbExtIntSetLowDetect: + DEVICE1VBUS_SETLOWDETECT; + break; + case UsbExtIntSetHighDetect: + DEVICE1VBUS_SETHIGHDETECT; + break; + case UsbExtIntGetLevel: + return DEVICE1VBUS_HIGHDETECT; + break; + } + return FALSE; +} +#endif + +#endif + +#ifdef __USBHOSTHW_H__ + +#if ((FM_PERIPHERAL_ENABLE_USB0 == ON) && (((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1)))) +/** + ****************************************************************************** + ** \brief Host 0 Overcurrent GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +boolean_t UsbConfig_Host0Overcurrent(en_usb_extint_param_t enType) +{ + switch(enType) + { + case UsbExtIntDeinit: + HOST0OVERCURRENT_DEINIT; + break; + case UsbExtIntInit: + HOST0OVERCURRENT_INIT; + break; + case UsbExtIntDisableIsr: + HOST0OVERCURRENT_DISABLEISR; + break; + case UsbExtIntEnableIsr: + HOST0OVERCURRENT_ENABLEISR; + break; + case UsbExtIntClearIsrFlag: + HOST0OVERCURRENT_CLEARISRFLAG; + break; + case UsbExtIntIsSetIsrFlag: + return HOST0OVERCURRENT_ISRISSET; + case UsbExtIntSetLowDetect: + HOST0OVERCURRENT_SETLOWDETECT; + break; + case UsbExtIntSetHighDetect: + HOST0OVERCURRENT_SETHIGHDETECT; + break; + case UsbExtIntGetLevel: + return HOST0OVERCURRENT_HIGHDETECT; + default: + return FALSE; + } + return TRUE; +} + +/** + ****************************************************************************** + ** \brief Host 0 VBUS GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +boolean_t UsbConfig_Host0Vbus(en_usb_gpio_param_t enType) +{ + switch(enType) + { + case UsbGpioDeinit: + HOST0VBUS_DEINIT; + break; + case UsbGpioInit: + HOST0VBUS_INIT; + break; + case UsbGpioSet: + HOST0VBUS_SET; + break; + case UsbGpioClear: + HOST0VBUS_CLEAR; + break; + default: + return FALSE; + } + return TRUE; +} + +/** + ****************************************************************************** + ** \brief Host 0 pull-down GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +boolean_t UsbConfig_Host0PulldownHostEnable(en_usb_gpio_param_t enType) +{ + switch(enType) + { + case UsbGpioDeinit: + HOST0OTGPULLDOWN_DEINIT; + break; + case UsbGpioInit: + HOST0OTGPULLDOWN_INIT; + break; + case UsbGpioSet: + HOST0OTGPULLDOWN_SET; + break; + case UsbGpioClear: + HOST0OTGPULLDOWN_CLEAR; + break; + default: + return FALSE; + } + return TRUE; +} +#endif + +#if ((FM_PERIPHERAL_ENABLE_USB1 == ON) && (((USE_USBHOSTHW_H == 1) || (USB_USE_PDL == 1)))) +/** + ****************************************************************************** + ** \brief Host 1 Overcurrent GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +boolean_t UsbConfig_Host1Overcurrent(en_usb_extint_param_t enType) +{ + switch(enType) + { + case UsbExtIntDeinit: + HOST1OVERCURRENT_DEINIT; + break; + case UsbExtIntInit: + HOST1OVERCURRENT_INIT; + break; + case UsbExtIntDisableIsr: + HOST1OVERCURRENT_DISABLEISR; + break; + case UsbExtIntEnableIsr: + HOST1OVERCURRENT_ENABLEISR; + break; + case UsbExtIntClearIsrFlag: + HOST1OVERCURRENT_CLEARISRFLAG; + break; + case UsbExtIntIsSetIsrFlag: + return HOST1OVERCURRENT_ISRISSET; + case UsbExtIntSetLowDetect: + HOST1OVERCURRENT_SETLOWDETECT; + break; + case UsbExtIntSetHighDetect: + HOST1OVERCURRENT_SETHIGHDETECT; + break; + case UsbExtIntGetLevel: + return HOST1OVERCURRENT_HIGHDETECT; + default: + return FALSE; + } + return TRUE; +} + +/** + ****************************************************************************** + ** \brief Host 1 VBUS GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +boolean_t UsbConfig_Host1Vbus(en_usb_gpio_param_t enType) +{ + switch(enType) + { + case UsbGpioDeinit: + HOST1VBUS_DEINIT; + break; + case UsbGpioInit: + HOST1VBUS_INIT; + break; + case UsbGpioSet: + HOST1VBUS_SET; + break; + case UsbGpioClear: + HOST1VBUS_CLEAR; + break; + default: + return FALSE; + } + return TRUE; +} + +/** + ****************************************************************************** + ** \brief Host 1 pull-down GPIO / external interrupt callback + ** + ** \param enType + ** + ** \return Depending on enType + ** + ******************************************************************************/ +boolean_t UsbConfig_Host1PulldownHostEnable(en_usb_gpio_param_t enType) +{ + switch(enType) + { + case UsbGpioDeinit: + HOST1OTGPULLDOWN_DEINIT; + break; + case UsbGpioInit: + HOST1OTGPULLDOWN_INIT; + break; + case UsbGpioSet: + HOST1OTGPULLDOWN_SET; + break; + case UsbGpioClear: + HOST1OTGPULLDOWN_CLEAR; + break; + default: + return FALSE; + } + return TRUE; +} +#endif + +#endif + +void UsbConfig_SwitchMode(void) +{ + #if FM_PERIPHERAL_ENABLE_USB0 == ON + #if ((FM_PERIPHERAL_ENABLE_USB0_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == OFF)) + Usb_SwitchUsb((stc_usbn_t*)&USB0,UsbSwitchToHost,0); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB0_HOST == OFF) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON)) + Usb_SwitchUsb((stc_usbn_t*)&USB0,UsbSwitchDependingDeviceVbus,0); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB0_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON)) + Usb_SwitchUsb((stc_usbn_t*)&USB0,UsbSwitchDependingDeviceVbus,0); + #endif + #endif + + #if FM_PERIPHERAL_ENABLE_USB1 == ON + #if ((FM_PERIPHERAL_ENABLE_USB1_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == OFF)) + + Usb_SwitchUsb((stc_usbn_t*)&USB1,UsbSwitchToHost,0); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1_HOST == OFF) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON)) + Usb_SwitchUsb((stc_usbn_t*)&USB1,UsbSwitchDependingDeviceVbus,0); + #endif + #if ((FM_PERIPHERAL_ENABLE_USB1_HOST == ON) && (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON)) + Usb_SwitchUsb((stc_usbn_t*)&USB1,UsbSwitchDependingDeviceVbus,0); + #endif + #endif +} + + +#if (FM_PERIPHERAL_ENABLE_USB0_DEVICE == ON) +void UsbDevice_Usb0ExintCallback(void) +{ + if (Usb_SwitchUsb((stc_usbn_t*)&USB0,UsbSwitchDependingDeviceVbus,0) == Ok) + { + if (DEVICE0VBUS_HIGHDETECT) + { + DEVICE0VBUS_SETLOWDETECT; + } + else + { + DEVICE0VBUS_SETHIGHDETECT; + } + } + +} +#endif + +#if (FM_PERIPHERAL_ENABLE_USB1_DEVICE == ON) +void UsbDevice_Usb1ExintCallback(void) +{ + if (Usb_SwitchUsb((stc_usbn_t*)&USB1,UsbSwitchDependingDeviceVbus,0) == Ok) + { + if (DEVICE1VBUS_HIGHDETECT) + { + DEVICE1VBUS_SETLOWDETECT; + } + else + { + DEVICE1VBUS_SETHIGHDETECT; + } + } +} +#endif + + + +#if (USB_USE_L3 == 0) +#if ((USB_USE_L3 == 0) && (USB_USE_EXT_INT == 1)) +#if (!defined(USB_DISBALE_DEVICE_FUNCTIONALITY)) +void INT8_31_Handler (void) +{ + #if FM_PERIPHERAL_ENABLE_USB0 == ON + if (DEVICE0VBUS_ISRISSET) + { + DEVICE0VBUS_CLEARISRFLAG; + UsbDevice_Usb0ExintCallback(); + } + #endif + #if FM_PERIPHERAL_ENABLE_USB1 == ON + if (DEVICE1VBUS_ISRISSET) + { + DEVICE1VBUS_CLEARISRFLAG; + UsbDevice_Usb1ExintCallback(); + } + #endif +} + +void INT8_15_Handler (void) +{ + #if FM_PERIPHERAL_ENABLE_USB0 == ON + if (DEVICE0VBUS_ISRISSET) + { + DEVICE0VBUS_CLEARISRFLAG; + UsbDevice_Usb0ExintCallback(); + } + #endif + #if FM_PERIPHERAL_ENABLE_USB1 == ON + if (DEVICE1VBUS_ISRISSET) + { + DEVICE1VBUS_CLEARISRFLAG; + UsbDevice_Usb1ExintCallback(); + } + #endif +} + +void INT0_7_Handler (void) +{ + #if FM_PERIPHERAL_ENABLE_USB0 == ON + if (DEVICE0VBUS_ISRISSET) + { + DEVICE0VBUS_CLEARISRFLAG; + UsbDevice_Usb0ExintCallback(); + } + #endif + #if FM_PERIPHERAL_ENABLE_USB1 == ON + if (DEVICE1VBUS_ISRISSET) + { + DEVICE1VBUS_CLEARISRFLAG; + UsbDevice_Usb1ExintCallback(); + } + #endif +} +#endif +#endif +#endif +#else + +/** + ****************************************************************************** + ** \brief Initialize USB (dummy if USB is disabled) + ** + ******************************************************************************/ +void UsbConfig_UsbInit(void) +{ +} + +/** + ****************************************************************************** + ** \brief Switch USB mode (dummy if USB is disabled) + ** + ******************************************************************************/ +void UsbConfig_SwitchMode(void) +{ +} +#endif /* ((!defined(USB_DISBALE_DEVICE_FUNCTIONALITY)) || (!defined(USB_DISBALE_HOST_FUNCTIONALITY))) */ +//@} // UsbConfigGroup \ No newline at end of file diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.h b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.h new file mode 100644 index 0000000000..01e18ed580 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconfig.h @@ -0,0 +1,266 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file usbconfig.h + ** + ** Part of FSEU USB Driver Module + ** + ** History: + ** - 2012-07-17 2.0 MSc New Version for use with M3 L3 USB driver + ** - 2012-10-02 2.1 MSc use of external interrupts without L3 implemented + ** - 2012-01-31 2.2 MSc DMA settings added + ** - 2013-06-04 2.3 MSc FM4 support added + ** - 2013-09-23 2.4 MSc Version for PDL + *****************************************************************************/ + +#ifndef __USBCONFIG_H__ +#define __USBCONFIG_H__ + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +//-------- <<< Use Configuration Wizard in Context Menu>>> ----------------- +// USB Debug +// ======================= +// +// Use USB debug functionality via UART +// <0=> OFF +// <1=> ON +#ifndef USEUSBDBG + #define USEUSBDBG 0 +#endif + +// Precompiler Warning Level +// <0=> no warnings +// <1=> hard warnings +// <2=> all warnings +#ifndef USBWARNLEVEL + #define USBWARNLEVEL 0 //0: no warnings, 1: hard warnings, 2: all warnings +#endif +// + +// Use of Headerfiles +// ======================= +// +// Use usbdescriptors.h +// <0=> OFF +// <1=> ON +#ifndef USE_USBDESCRIPTORS_H + #define USE_USBDESCRIPTORS_H 1 //<- 1 use usbdescriptors.h file for USB descriptors settings, 0 for disabling +#endif + +// Use usbdevicehw.h +// <0=> OFF +// <1=> ON +#ifndef USE_USBDEVICEHW_H + #define USE_USBDEVICEHW_H 1 //<- 1 use usbdevicehw.h file for gpio settings, 0 for disabling +#endif + +// Use usbhosthw.h +// <0=> OFF +// <1=> ON +#ifndef USE_USBHOSTHW_H + #define USE_USBHOSTHW_H 1 //<- 1 use usbhosthw.h file for gpio settings, 0 for disabling +#endif + +// Use sbhostclassdrivertable.h +// <0=> OFF +// <1=> ON +#ifndef USE_USBHOSTCLASSDRIVERTABLE_H + #define USE_USBHOSTCLASSDRIVERTABLE_H 0 //<- 1 use usbhostclassdrivertable.h file +#endif +// + +// Use USB within a low level library +// ======================= +// +// Use with L3 (old library for FM3 MCUs) +// <0=> OFF +// <1=> ON +#ifndef USB_USE_L3 +#define USB_USE_L3 0 //<- 1 use as part of L3 library, 0 for using without L3 library +#endif + +// Use with PDL +// <0=> OFF +// <1=> ON +#define USB_USE_PDL 0 //<- 1 use as part of PDL library, 0 for using without PDL library +// + + +#if (USB_USE_PDL == 0) && (USB_USE_L3 == 0) +/* START Middleware Modules */ + +/* DEVICE */ +// USB Device middleware modules +// ======================= +// +// USB Device CDC +// <0=> OFF +// <1=> ON +#ifndef USBDEVICECDCCOM_ENABLED +#define USBDEVICECDCCOM_ENABLED ON //Middleware USB CDC Communication Class +#endif + +// USB Device HID (data communication) +// <0=> OFF +// <1=> ON +#ifndef USBDEVICEHIDCOM_ENABLED + #define USBDEVICEHIDCOM_ENABLED OFF +#endif + +// USB Device HID Joystick +// <0=> OFF +// <1=> ON +#ifndef USBDEVICEHIDJOYSTICK_ENABLED + #define USBDEVICEHIDJOYSTICK_ENABLED OFF +#endif + +// USB Device HID Keyboard +// <0=> OFF +// <1=> ON +#ifndef USBDEVICEHIDKEYBOARD_ENABLED + #define USBDEVICEHIDKEYBOARD_ENABLED OFF +#endif + +// USB Device HID Mouse +// <0=> OFF +// <1=> ON +#ifndef USBDEVICEHIDMOUSE_ENABLED + #define USBDEVICEHIDMOUSE_ENABLED OFF +#endif + +// USB Device LibUSB +// <0=> OFF +// <1=> ON +#ifndef USBDEVICELIBUSB_ENABLED + #define USBDEVICELIBUSB_ENABLED OFF +#endif + +// USB Device Printer +// <0=> OFF +// <1=> ON +#ifndef USBDEVICEPRINTER_ENABLED + #define USBDEVICEPRINTER_ENABLED OFF +#endif + +// USB Device Mass Storage +// <0=> OFF +// <1=> ON +#ifndef USBDEVICEMASSSTORAGE_ENABLED + #define USBDEVICEMASSSTORAGE_ENABLED OFF +#endif +// + + + +/* HOST */ +// USB Host middleware modules +// ======================= +// +// USB Host HID (Data communication) +// <0=> OFF +// <1=> ON +#ifndef USBHOSTHIDCOM_ENABLED +#define USBHOSTHIDCOM_ENABLED OFF +#endif + +// USB Host HID Keyboard +// <0=> OFF +// <1=> ON +#ifndef USBHOSTHIDKEYBOARD_ENABLED +#define USBHOSTHIDKEYBOARD_ENABLED OFF /* [andreika] */ +#endif + +// USB Host HID Mouse +// <0=> OFF +// <1=> ON +#ifndef USBHOSTHIDMOUSE_ENABLED +#define USBHOSTHIDMOUSE_ENABLED OFF /* [andreika] */ +#endif + +// USB Host Mass Storage +// <0=> OFF +// <1=> ON +#ifndef USBHOSTMASSSTORAGE_ENABLED +#define USBHOSTMASSSTORAGE_ENABLED OFF /* [andreika] */ +#endif + +// USB Host NDIS +// <0=> OFF +// <1=> ON +#ifndef USBHOSTNDIS_ENABLED +#define USBHOSTNDIS_ENABLED OFF /* [andreika] */ +#endif + +// USB Host Printer +// <0=> OFF +// <1=> ON +#ifndef USBHOSTPRINTER_ENABLED +#define USBHOSTPRINTER_ENABLED OFF /* [andreika] */ +#endif +// + +/* END Middleware Modules */ + +/* only used if USB is used without L3 or PDL*/ +#define USB0_HOST_ENABLED 0 +#define USB0_DEVICE_ENABLED 1 +#define USB1_HOST_ENABLED 0 +#define USB1_DEVICE_ENABLED 0 +#define USB0_DEVICE_IRQ_ENABLED 1 +#define USB0_HOST_IRQ_ENABLED 1 +#define USB1_DEVICE_IRQ_ENABLED 1 +#define USB1_HOST_IRQ_ENABLED 1 +#define USB_USE_EXT_INT 0 +#define IRQ_LEVEL_USB0 3 +#define IRQ_LEVEL_USB1 3 +#define USB_USES_DMA 0 +#define USB_USES_DMA_0 1 +#define USB_USES_DMA_1 1 +#define USB_USES_DMA_2 0 +#define USB_USES_DMA_3 0 +#define USB_USES_DMA_4 0 +#define USB_USES_DMA_5 0 +#define USB_USES_DMA_6 0 +#define USB_USES_DMA_7 0 + +#endif //(USB_USE_PDL == 0) && (USB_USE_L3 == 0) + +void UsbConfig_UsbInit(void); +void UsbConfig_SwitchMode(void); + +#endif diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.c b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.c new file mode 100644 index 0000000000..24489995d3 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.c @@ -0,0 +1,170 @@ +#include "global.h" +#include "os_access.h" + +#if EFI_USB_SERIAL + +#include "pdl_header.h" +#include "usb.h" +#include "UsbDeviceCdcCom.h" + +// 10 seconds +#define USB_WRITE_TIMEOUT 10000 + +// See uart_dma_s +#define USB_FIFO_BUFFER_SIZE (BLOCKING_FACTOR + 30) + +// struct needed for async transfer mode +typedef struct { + // secondary FIFO buffer for async. transfer + uint8_t buffer[USB_FIFO_BUFFER_SIZE]; + // input FIFO Rx queue + input_queue_t fifoRxQueue; +} usb_buf_s; + +static usb_buf_s usbBuf; + + +static bool isUsbSerialInitialized = false; + +static bool isUsbSerialInitStarted = false; + +static thread_reference_t threadrx = NULL; + +// called from the USB IRQ handler +static void onUsbDataReceived(uint8_t* pu8Data, uint32_t u32ReceviedSize) { + osalSysLockFromISR(); + + // copy the data to the FIFO buffer + for (int i = 0; i < u32ReceviedSize; i++) { + if (iqPutI(&usbBuf.fifoRxQueue, *pu8Data++) != Q_OK) { + break; // todo: ignore overflow? + } + } + + // tell the reader thread to wake up +#if 0 + if (threadrx != NULL) { + osalThreadResumeI(&threadrx, MSG_OK); + } +#endif + + osalSysUnlockFromISR(); +} + +// To use UART driver instead of Serial, we need to imitate "BaseChannel" streaming functionality +static msg_t _putt(void *ip, uint8_t b, sysinterval_t timeout) { + (void)ip; + (void)timeout; + UsbDeviceCdcCom_SendByte(b); + return MSG_OK; +} +static size_t _writet(void *ip, const uint8_t *bp, size_t n, sysinterval_t timeout) { + (void)ip; + (void)timeout; + UsbDeviceCdcCom_SendBuffer((uint8_t *)bp, n); + return n; +} +static msg_t _put(void *ip, uint8_t b) { + (void)ip; + UsbDeviceCdcCom_SendByte(b); +/* + // uartSendTimeout() needs interrupts to wait for the end of transfer, so we have to unlock them temporary + bool wasLocked = isLocked(); + if (wasLocked) + unlockAnyContext(); + _putt(ip, b, CONSOLE_WRITE_TIMEOUT); + if (wasLocked) + lockAnyContext(); +*/ + return MSG_OK; +} +static size_t _write(void *ip, const uint8_t *bp, size_t n) { + return _writet(ip, bp, n, USB_WRITE_TIMEOUT); +} +static size_t _readt(void *ip, uint8_t *bp, size_t n, sysinterval_t timeout) { + size_t numBytesRead; + //numBytesRead = UsbDeviceCdcCom_ReceiveBuffer(bp, n); + + return (size_t)iqReadTimeout(&usbBuf.fifoRxQueue, bp, n, timeout); +/* + // if we don't have all bytes immediately + if (numBytesRead < n) { + osalSysLock(); + threadrx = chThdGetSelfX(); + osalThreadSuspendTimeoutS(&threadrx, timeout); + osalSysUnlock(); + numBytesRead += UsbDeviceCdcCom_ReceiveBuffer(bp + numBytesRead, n - numBytesRead); + } + return numBytesRead; +*/ +} +static msg_t _gett(void *ip, sysinterval_t timeout) { + (void)ip; + (void)timeout; + //msg_t msg = UsbDeviceCdcCom_ReceiveByte(); + uint8_t b; + if (_readt(ip, &b, 1, timeout) == 1) + return (msg_t)b; + return MSG_TIMEOUT; +} +static msg_t _get(void *ip) { + return _gett(ip, USB_WRITE_TIMEOUT); +} +static size_t _read(void *ip, uint8_t *bp, size_t n) { + (void)ip; + return _readt(ip, bp, n, USB_WRITE_TIMEOUT); +} +static msg_t _ctl(void *ip, unsigned int operation, void *arg) { + return MSG_OK; +} + +// This is a "fake" channel for getConsoleChannel() filled with our handlers +static const struct BaseChannelVMT usbChannelVmt = { + .instance_offset = (size_t)0, .write = _write, .read = _read, .put = _put, .get = _get, + .putt = _putt, .gett = _gett, .writet = _writet, .readt = _readt, .ctl = _ctl +}; + +BaseChannel SDU1 = { .vmt = &usbChannelVmt }; + + +static void usb_VBus_handler(uint8_t channel) { + // call it only if the USB driver is already initialized + if (isUsbSerialInitialized) + UsbConfig_SwitchMode(); +} + +/** + ****************************************************************************** + ** \brief Main function of PDL + ** + ** \return uint32_t return value, if needed + ******************************************************************************/ +void usb_serial_start(void) { + if (isUsbSerialInitStarted) + return; + + isUsbSerialInitStarted = true; + + UsbConfig_UsbInit(); + + // init FIFO queue + iqObjectInit(&usbBuf.fifoRxQueue, usbBuf.buffer, sizeof(usbBuf.buffer), NULL, NULL); + + UsbDeviceCdcCom_SetReceivedCallback(onUsbDataReceived); + + UsbConfig_SwitchMode(); + + // init VBus detector for P60 (INT31_0) + SetPinFunc_INT31_0(0u); + _pal_lld_setpadeventhandler(31, ExIntRisingEdge, usb_VBus_handler); + + + isUsbSerialInitialized = true; + +} + +bool is_usb_serial_ready(void) { + return isUsbSerialInitialized /*&& SDU1.config->usbp->state == USB_ACTIVE*/; +} + +#endif /* EFI_USB_SERIAL */ diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.h b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.h new file mode 100644 index 0000000000..c87a3acbb5 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbconsole.h @@ -0,0 +1,23 @@ +/** + * @file usbconsole.h + * + * @date Jan 27, 2020 + * @author andreika + */ + +#ifndef USBCONSOLE_H_ +#define USBCONSOLE_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +void usb_serial_start(void); +bool is_usb_serial_ready(void); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* USBCONSOLE_H_ */ diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbdescriptors.h b/firmware/hw_layer/ports/cypress/serial_over_usb/usbdescriptors.h new file mode 100644 index 0000000000..26a4b58068 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbdescriptors.h @@ -0,0 +1,190 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/******************************************************************************/ +/** \file UsbDescriptors.h + ** + ** USB Descriptors File + ** + ** History: + ** - 2020-1-27 1.0 MSc Automatically Created by Spansion USB Wizard + *****************************************************************************/ + +#ifndef __USBDESCRIPTORS_H__ +#define __USBDESCRIPTORS_H__ + +/*****************************************************************************/ +/* Include files */ +/*****************************************************************************/ + + + +/*****************************************************************************/ +/* Global pre-processor symbols/macros ('#define') */ +/*****************************************************************************/ + +#define USB_DEVDESC_SIZE 18 +#define USB_CNFGDESC_SIZE 53 +#define USB_FUNC_EP0_SIZE 64 +#define CLASSNAME "UsbDeviceCdcCom" + + +/*****************************************************************************/ +/* Global type definitions ('typedef') */ +/*****************************************************************************/ + +#define USBDESCRIPTORS_STRINGDESCRIPTOR_COUNT (uint32_t)(sizeof(pstcStringDescriptors) / sizeof(pstcStringDescriptors[0])) + + + + +/*****************************************************************************/ +/* Global variable declarations ('extern', definition in C source) */ +/*****************************************************************************/ +// [andreika]: use ST-compatible vendor+product IDs +const uint8_t au8DeviceDescriptor[18] = +{ + ///DEVICE DESCRIPTOR + 0x12, ///bLength: Length of this descriptor + 0x01, ///bDescriptorType: Device Descriptor Type + 0x10, ///bcdUSB: USB Version + 0x01, ///bcdUSB: USB Version + 0x02, ///bDeviceClass: Class Code: COMMUNICATIONS_AND_CDC_CONTROL + 0x00, ///bDeviceSubClass: Sub Class Code + 0x00, ///bDeviceProtocol: Protocol Code + 0x40, ///bMaxPacketSize0: Maximum size of endpoint 0 + 0x83, ///idVendor: Vendor ID + 0x04, ///idVendor: Vendor ID + 0x40, ///idProduct: Product ID + 0x57, ///idProduct: Product ID + 0x00, ///bcdDevice: Release Number + 0x02, ///bcdDevice: Release Number + 0x01, ///iManufacture: String-Index of Manufacture + 0x02, ///iProduct: String-Index of Product + 0x03, ///iSerialNumber: String-Index of Serial Number + 0x01 ///bNumConfigurations: Number of possible configurations +}; + +const uint8_t au8ConfigDescriptor[53] = +{ ///NEW CONFIG DESCRIPTOR(1) + 0x09, ///bLength: Length of this descriptor + 0x02, ///bDescriptorType: Config Descriptor Type + 0x35, ///wTotalLength: Total Length with all interface- and endpoint descriptors + 0x00, ///wTotalLength: Total Length with all interface- and endpoint descriptors + 0x02, ///bNumInterfaces: Number of interfaces + 0x01, ///iConfigurationValue: Number of this configuration + 0x00, ///iConfiguration: String index of this configuration + 0xC0, ///bmAttributes: Bus-Powered, Remote-Wakeup not supported + 0xFA, ///MaxPower: (in 2mA) + ///NEW INTERFACE DESCRIPTOR(0) + 0x09, ///bLength: Length of this descriptor + 0x04, ///bDescriptorType: Interface Descriptor Type + 0x00, ///bInterfaceNumber: Interface Number + 0x00, ///bAlternateSetting: Alternate setting for this interface + 0x01, ///bNumEndpoints: Number of endpoints in this interface excluding endpoint 0 + 0x02, ///iInterfaceClass: Class Code: COMMUNICATIONS_AND_CDC_CONTROL + 0x02, ///iInterfaceSubClass: SubClass Code + 0x01, ///bInterfaceProtocol: Protocol Code + 0x00, ///iInterface: String index + ///NEW FUNCTION DESCRIPTOR(0) + 0x05, ///bLength: Length of this descriptor + 0x24, ///bDescriptorType: Class Specific Interface Descriptor Type + 0x06, ///bDescriptorSubtype: Union Functional descriptor + 0x00, ///Master Interface (Control) + 0x01, ///Slave Interface (Data) + ///NEW ENDPOINT DESCRIPTOR(1) + 0x07, ///bLength: Length of this descriptor + 0x05, ///bDescriptorType: Endpoint Descriptor Type + 0x82, ///bEndpointAddress: Endpoint address (IN,EP2) + 0x03, ///bmAttributes: Transfer Type: INTERRUPT_TRANSFER + 0x40, ///wMaxPacketSize: Endpoint Size + 0x00, ///wMaxPacketSize: Endpoint Size + 0xFF, ///bIntervall: Polling Intervall + ///NEW INTERFACE DESCRIPTOR(1) + 0x09, ///bLength: Length of this descriptor + 0x04, ///bDescriptorType: Interface Descriptor Type + 0x01, ///bInterfaceNumber: Interface Number + 0x00, ///bAlternateSetting: Alternate setting for this interface + 0x02, ///bNumEndpoints: Number of endpoints in this interface excluding endpoint 0 + 0x0A, ///iInterfaceClass: Class Code: CDC_DATA + 0x00, ///iInterfaceSubClass: SubClass Code + 0x00, ///bInterfaceProtocol: Protocol Code + 0x00, ///iInterface: String index + ///NEW ENDPOINT DESCRIPTOR(0) + 0x07, ///bLength: Length of this descriptor + 0x05, ///bDescriptorType: Endpoint Descriptor Type + 0x03, ///bEndpointAddress: Endpoint address (OUT,EP3) + 0x02, ///bmAttributes: Transfer Type: BULK_TRANSFER + 0x40, ///wMaxPacketSize: Endpoint Size + 0x00, ///wMaxPacketSize: Endpoint Size + 0x00, ///bIntervall: Polling Intervall + ///NEW ENDPOINT DESCRIPTOR(1) + 0x07, ///bLength: Length of this descriptor + 0x05, ///bDescriptorType: Endpoint Descriptor Type + 0x81, ///bEndpointAddress: Endpoint address (IN,EP1) + 0x02, ///bmAttributes: Transfer Type: BULK_TRANSFER + 0x40, ///wMaxPacketSize: Endpoint Size + 0x00, ///wMaxPacketSize: Endpoint Size + 0x00 ///bIntervall: Polling Intervall +}; + +const uint8_t au8ReportDescriptor0[1]; // Not used +const uint8_t au8ReportDescriptor1[1]; // Not used +const uint8_t au8ReportDescriptor2[1]; // Not used + + +const stc_usbdevice_stringdescriptor_t pstcStringDescriptors[] = +{ +{"Spansion International Inc.",NULL}, //Manufacturer String +{"rusEFI ECU Comm Port",NULL}, //Product String +{"1.0",NULL}, //Serial Number String +}; + + +const stc_usbdevice_reportdescriptor_t astcReportDescriptors[3] = +{ + {(uint8_t*)au8ReportDescriptor0,sizeof(au8ReportDescriptor0)}, + {(uint8_t*)au8ReportDescriptor1,sizeof(au8ReportDescriptor1)}, + {(uint8_t*)au8ReportDescriptor2,sizeof(au8ReportDescriptor2)}, +}; + +/*****************************************************************************/ +/* Global function prototypes ('extern', definition in C source) */ +/*****************************************************************************/ + + + + + +#endif /* __USBDESCRIPTORS_H__ */ diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbdevicehw.h b/firmware/hw_layer/ports/cypress/serial_over_usb/usbdevicehw.h new file mode 100644 index 0000000000..efb1ed4c15 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbdevicehw.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/************************************************************************/ +/** \file usbdevicehw.h + ** + ** - See README.TXT for project description + ** - pre release for a simple universal usb function library + ** + ** History: + ** - 2010-03-30 1.0 MSc First version (works with 16FX,FR80) + ** - 2011-03-30 1.1 MSc New HW description style + ** - 2016-06-23 1.2 MSc Updated for use with MCU Templates >= v2.0 + *****************************************************************************/ + +#ifndef __USBDEVICEHW_H__ +#define __USBDEVICEHW_H__ + +#define DEVICE0VBUS_DISABLEISR +#define DEVICE0VBUS_ENABLEISR +#define DEVICE0VBUS_ISRISSET 0 +#define DEVICE0VBUS_CLEARISRFLAG +#define DEVICE0VBUS_SETLOWDETECT +#define DEVICE0VBUS_SETHIGHDETECT +#define DEVICE0VBUS_HIGHDETECT Gpio1pin_Get( GPIO1PIN_P60 ) +#define DEVICE0VBUS_INIT Gpio1pin_InitIn( GPIO1PIN_P60, Gpio1pin_InitPullup( 0u ) ) +#define DEVICE0VBUS_DEINIT +#define DEVICE0VBUS_ENABLED 1 + +#define DEVICE0HCONX_INIT +#define DEVICE0HCONX_SET +#define DEVICE0HCONX_CLEAR +#define DEVICE0HCONX_ENABLED 1 + +#define DEVICE1VBUS_DISABLEISR +#define DEVICE1VBUS_ENABLEISR +#define DEVICE1VBUS_ISRISSET 0 +#define DEVICE1VBUS_CLEARISRFLAG +#define DEVICE1VBUS_SETLOWDETECT +#define DEVICE1VBUS_SETHIGHDETECT +#define DEVICE1VBUS_HIGHDETECT (0) +#define DEVICE1VBUS_INIT +#define DEVICE1VBUS_DEINIT +#define DEVICE1VBUS_ENABLED 0 + +#define DEVICE1HCONX_INIT +#define DEVICE1HCONX_SET +#define DEVICE1HCONX_CLEAR +#define DEVICE1HCONX_ENABLED 0 + + +#endif diff --git a/firmware/hw_layer/ports/cypress/serial_over_usb/usbhosthw.h b/firmware/hw_layer/ports/cypress/serial_over_usb/usbhosthw.h new file mode 100644 index 0000000000..b223ea6868 --- /dev/null +++ b/firmware/hw_layer/ports/cypress/serial_over_usb/usbhosthw.h @@ -0,0 +1,100 @@ +/******************************************************************************* +* Copyright (C) 2013-2016, Cypress Semiconductor Corporation or a * +* subsidiary of Cypress Semiconductor Corporation. All rights reserved. * +* * +* This software, including source code, documentation and related * +* materials ("Software"), is owned by Cypress Semiconductor Corporation or * +* one of its subsidiaries ("Cypress") and is protected by and subject to * +* worldwide patent protection (United States and foreign), United States * +* copyright laws and international treaty provisions. Therefore, you may use * +* this Software only as provided in the license agreement accompanying the * +* software package from which you obtained this Software ("EULA"). * +* * +* If no EULA applies, Cypress hereby grants you a personal, non-exclusive, * +* non-transferable license to copy, modify, and compile the * +* Software source code solely for use in connection with Cypress's * +* integrated circuit products. Any reproduction, modification, translation, * +* compilation, or representation of this Software except as specified * +* above is prohibited without the express written permission of Cypress. * +* * +* Disclaimer: THIS SOFTWARE IS PROVIDED AS-IS, WITH NO * +* WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, * +* BUT NOT LIMITED TO, NONINFRINGEMENT, IMPLIED * +* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * +* PARTICULAR PURPOSE. Cypress reserves the right to make * +* changes to the Software without notice. Cypress does not assume any * +* liability arising out of the application or use of the Software or any * +* product or circuit described in the Software. Cypress does not * +* authorize its products for use in any products where a malfunction or * +* failure of the Cypress product may reasonably be expected to result in * +* significant property damage, injury or death ("High Risk Product"). By * +* including Cypress's product in a High Risk Product, the manufacturer * +* of such system or application assumes all risk of such use and in doing * +* so agrees to indemnify Cypress against all liability. * +*******************************************************************************/ +/************************************************************************/ +/** \file UsbHostHW.h + ** + ** USB hardware specific settings + ** + ** History: + ** - 2010-10-14 1.0 MSc First version (works with 16FX,FR80) + ** - 2011-03-30 1.1 MSc Compatible with FSEU Host drivers 2011-03-30 + *****************************************************************************/ + +#ifndef __USBHOSTHW_H__ +#define __USBHOSTHW_H__ + +#define HOST0VBUS_DEINIT +#define HOST0VBUS_INIT +#define HOST0VBUS_SET +#define HOST0VBUS_CLEAR +#define HOST0VBUS_GET +#define HOST0VBUS_ENABLED 0 + +#define HOST0OTGPULLDOWN_DEINIT +#define HOST0OTGPULLDOWN_INIT +#define HOST0OTGPULLDOWN_SET +#define HOST0OTGPULLDOWN_CLEAR +#define HOST0OTGPULLDOWN_GET 1 +#define HOST0OTGPULLDOWN_ENABLED 0 + +#define HOST0OVERCURRENT_DISABLEISR +#define HOST0OVERCURRENT_ENABLEISR +#define HOST0OVERCURRENT_CLEARISRFLAG +#define HOST0OVERCURRENT_ISRISSET 0 +#define HOST0OVERCURRENT_SETLOWDETECT +#define HOST0OVERCURRENT_SETHIGHDETECT +#define HOST0OVERCURRENT_HIGHDETECT 0 +#define HOST0OVERCURRENT_INIT +#define HOST0OVERCURRENT_DEINIT +#define HOST0OVERCURRENT_ENABLED 0 + + +#define HOST1VBUS_DEINIT +#define HOST1VBUS_INIT +#define HOST1VBUS_SET +#define HOST1VBUS_CLEAR +#define HOST1VBUS_GET 0 +#define HOST1VBUS_ENABLED 0 + +#define HOST1OTGPULLDOWN_DEINIT +#define HOST1OTGPULLDOWN_INIT +#define HOST1OTGPULLDOWN_SET +#define HOST1OTGPULLDOWN_CLEAR +#define HOST1OTGPULLDOWN_GET 1 +#define HOST1OTGPULLDOWN_ENABLED 0 + +#define HOST1OVERCURRENT_DISABLEISR +#define HOST1OVERCURRENT_ENABLEISR +#define HOST1OVERCURRENT_CLEARISRFLAG +#define HOST1OVERCURRENT_ISRISSET 0 +#define HOST1OVERCURRENT_SETLOWDETECT +#define HOST1OVERCURRENT_SETHIGHDETECT +#define HOST1OVERCURRENT_HIGHDETECT 0 +#define HOST1OVERCURRENT_INIT +#define HOST1OVERCURRENT_DEINIT +#define HOST0OVERCURRENT_ENABLED 0 + + +#endif From 38f480741f97e4898f74931ed7a7cd9ee232f129 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 12:00:16 -0400 Subject: [PATCH 05/12] Hellen says drivers (cherry picked from commit 02573713f35d0a6e0b3e0bd1c9160cefcb91a557) --- firmware/hw_layer/drivers/drivers.mk | 3 +- firmware/hw_layer/drivers/gpio/drv8860.c | 297 +++++++++++++++++++++++ firmware/hw_layer/drivers/gpio/drv8860.h | 43 ++++ 3 files changed, 342 insertions(+), 1 deletion(-) create mode 100644 firmware/hw_layer/drivers/gpio/drv8860.c create mode 100644 firmware/hw_layer/drivers/gpio/drv8860.h diff --git a/firmware/hw_layer/drivers/drivers.mk b/firmware/hw_layer/drivers/drivers.mk index 03cbb36909..0ee4870408 100644 --- a/firmware/hw_layer/drivers/drivers.mk +++ b/firmware/hw_layer/drivers/drivers.mk @@ -11,7 +11,8 @@ HW_LAYER_DRIVERS = \ $(DRIVERS_DIR)/gpio/tle6240.c \ $(DRIVERS_DIR)/gpio/tle8888.c \ $(DRIVERS_DIR)/gpio/mc33972.c \ - $(DRIVERS_DIR)/gpio/mc33810.c + $(DRIVERS_DIR)/gpio/mc33810.c \ + $(DRIVERS_DIR)/gpio/drv8860.c \ HW_LAYER_DRIVERS_CPP = diff --git a/firmware/hw_layer/drivers/gpio/drv8860.c b/firmware/hw_layer/drivers/gpio/drv8860.c new file mode 100644 index 0000000000..5900121fbf --- /dev/null +++ b/firmware/hw_layer/drivers/gpio/drv8860.c @@ -0,0 +1,297 @@ +/* + * drv8860.c + * + * DRV8860 Smart 8/16-Channel Low-Side Switch + * + * All channels are controlled via the serial interface (SPI). + * <200 kHz SPI + * + * @date Apr 6, 2020 + * + * @author andreika, (c) 2020 + * @author Andrey Belomutskiy, (c) 2012-2020 + */ + +#include "global.h" +#include "gpio/gpio_ext.h" +#include "gpio/drv8860.h" +#include "pin_repository.h" +#include "os_util.h" + +#if (BOARD_DRV8860_COUNT > 0) + +/*==========================================================================*/ +/* Driver local definitions. */ +/*==========================================================================*/ + +#define DRIVER_NAME "drv8860" + +static bool drv_task_ready = false; + +typedef enum { + DRV8860_DISABLED = 0, + DRV8860_WAIT_INIT, + DRV8860_READY, + DRV8860_FAILED +} drv8860_drv_state; + +/*==========================================================================*/ +/* Driver exported variables. */ +/*==========================================================================*/ + +/*==========================================================================*/ +/* Driver local variables and types. */ +/*==========================================================================*/ + +/* OS */ +SEMAPHORE_DECL(drv8860_wake, 10 /* or BOARD_DRV8860_COUNT ? */); +static THD_WORKING_AREA(drv8860_thread_1_wa, 256); + +/* Driver */ +struct drv8860_priv { + const struct drv8860_config *cfg; + /* cached output state - state last send to chip */ + uint16_t o_state_cached; + /* state to be sended to chip */ + uint16_t o_state; + + drv8860_drv_state drv_state; +}; + +static struct drv8860_priv chips[BOARD_DRV8860_COUNT]; + +static const char* drv8860_pin_names[DRV8860_OUTPUTS] = { + "drv8860.OUT1", "drv8860.OUT2", "drv8860.OUT3", "drv8860.OUT4", + "drv8860.OUT5", "drv8860.OUT6", "drv8860.OUT7", "drv8860.OUT8", + "drv8860.OUT9", "drv8860.OUT10", "drv8860.OUT11", "drv8860.OUT12", + "drv8860.OUT13", "drv8860.OUT14", "drv8860.OUT15", "drv8860.OUT16", +}; + +/*==========================================================================*/ +/* Driver local functions. */ +/*==========================================================================*/ + +static SPIDriver *get_bus(struct drv8860_priv *chip) { + /* return non-const SPIDriver* from const struct cfg */ + return chip->cfg->spi_bus; +} + +/** + * @brief DRV8860 send routine. + * @details Sends 8/16 bits. CS asserted before and released after transaction. + */ + +static void drv8860_spi_send(struct drv8860_priv *chip, uint16_t tx) { + SPIDriver *spi = get_bus(chip); + + /* Acquire ownership of the bus. */ + spiAcquireBus(spi); + /* Setup transfer parameters. */ + spiStart(spi, &chip->cfg->spi_config); + /* Slave Select assertion. */ + spiSelect(spi); + /* Atomic transfer operations. */ + spiPolledExchange(spi, tx); + /* Slave Select de-assertion. */ + spiUnselect(spi); + /* Ownership release. */ + spiReleaseBus(spi); +} + +/** + * @brief DRV8860 send output data. + */ + +static void drv8860_update_outputs(struct drv8860_priv *chip) { + /* TODO: lock? */ + + /* atomic */ + /* set value only for non-direct driven pins */ + drv8860_spi_send(chip, chip->o_state & 0xffff); + + /* atomic */ + chip->o_state_cached = chip->o_state; + + /* TODO: unlock? */ +} + +/** + * @brief DRV8860 chip init. + * @details Marks all used pins. + * @todo: Checks direct io signals integrity, read initial diagnostic state. + */ + +static int drv8860_chip_init(struct drv8860_priv *chip) { + /* upload pin states */ + drv8860_update_outputs(chip); + + return 0; +} + +/** + * @brief DRV8860 chip driver wakeup. + * @details Wake up driver. Will cause output register update. + */ + +static int drv8860_wake_driver(struct drv8860_priv *chip) { + (void)chip; + + /* Entering a reentrant critical zone.*/ + syssts_t sts = chSysGetStatusAndLockX(); + chSemSignalI(&drv8860_wake); + /* Leaving the critical zone.*/ + chSysRestoreStatusX(sts); + + return 0; +} + +/*==========================================================================*/ +/* Driver thread. */ +/*==========================================================================*/ + +static THD_FUNCTION(drv8860_driver_thread, p) { + int i; + msg_t msg; + + (void)p; + + chRegSetThreadName(DRIVER_NAME); + + while (1) { + msg = chSemWaitTimeout(&drv8860_wake, TIME_MS2I(DRV8860_POLL_INTERVAL_MS)); + + /* should we care about msg == MSG_TIMEOUT? */ + (void)msg; + + for (i = 0; i < BOARD_DRV8860_COUNT; i++) { + struct drv8860_priv *chip; + + chip = &chips[i]; + if ((chip->cfg == NULL) || + (chip->drv_state == DRV8860_DISABLED) || + (chip->drv_state == DRV8860_FAILED)) + continue; + + drv8860_update_outputs(chip); + } + } +} + +/*==========================================================================*/ +/* Driver interrupt handlers. */ +/*==========================================================================*/ + +/* TODO: add IRQ support */ + +/*==========================================================================*/ +/* Driver exported functions. */ +/*==========================================================================*/ + +int drv8860_writePad(void *data, unsigned int pin, int value) { + struct drv8860_priv *chip; + + if ((pin >= DRV8860_OUTPUTS) || (data == NULL)) + return -1; + + chip = (struct drv8860_priv *)data; + + /* TODO: lock */ + if (value) + chip->o_state |= (1 << pin); + else + chip->o_state &= ~(1 << pin); + /* TODO: unlock */ + drv8860_wake_driver(chip); + + return 0; +} + +brain_pin_diag_e drv8860_getDiag(void *data, unsigned int pin) { + // todo: implement diag + return PIN_OK; +} + +int drv8860_init(void * data) { + int ret; + struct drv8860_priv *chip; + + chip = (struct drv8860_priv *)data; + + ret = drv8860_chip_init(chip); + if (ret) + return ret; + + chip->drv_state = DRV8860_READY; + + if (!drv_task_ready) { + chThdCreateStatic(drv8860_thread_1_wa, sizeof(drv8860_thread_1_wa), + NORMALPRIO + 1, drv8860_driver_thread, NULL); + drv_task_ready = true; + } + + return 0; +} + +int drv8860_deinit(void *data) { + (void)data; + + /* TODO: set all pins to inactive state, stop task? */ + return 0; +} + +struct gpiochip_ops drv8860_ops = { + .writePad = drv8860_writePad, + .readPad = NULL, /* chip outputs only */ + .getDiag = drv8860_getDiag, + .init = drv8860_init, + .deinit = drv8860_deinit, +}; + +/** + * @brief DRV8860 driver add. + * @details Checks for valid config + */ + +int drv8860_add(unsigned int index, const struct drv8860_config *cfg) { + int i; + int ret; + struct drv8860_priv *chip; + + /* no config or no such chip */ + if ((!cfg) || (!cfg->spi_bus) || (index >= BOARD_DRV8860_COUNT)) + return -1; + + /* check for valid cs. + * TODO: remove this check? CS can be driven by SPI */ + //if (cfg->spi_config.ssport == NULL) + // return -1; + + chip = &chips[index]; + + /* already initted? */ + if (chip->cfg != NULL) + return -1; + + chip->cfg = cfg; + chip->o_state = 0; + chip->o_state_cached = 0; + chip->drv_state = DRV8860_WAIT_INIT; + + /* register, return gpio chip base */ + ret = gpiochip_register(DRIVER_NAME, &drv8860_ops, DRV8860_OUTPUTS, chip); + + /* set default pin names, board init code can rewrite */ + gpiochips_setPinNames(ret, drv8860_pin_names); + + return ret; +} + +#else /* BOARD_DRV8860_COUNT > 0 */ + +int drv8860_add(unsigned int index, const struct drv8860_config *cfg) { + (void)index; (void)cfg; + + return -1; +} + +#endif /* BOARD_DRV8860_COUNT */ diff --git a/firmware/hw_layer/drivers/gpio/drv8860.h b/firmware/hw_layer/drivers/gpio/drv8860.h new file mode 100644 index 0000000000..3629285aca --- /dev/null +++ b/firmware/hw_layer/drivers/gpio/drv8860.h @@ -0,0 +1,43 @@ +/* + * drv8860.h + * + * DRV8860 Smart 8/16-Channel Low-Side Switch + * + * @date Apr 6, 2020 + * + * @author andreika, (c) 2020 + * @author Andrey Belomutskiy, (c) 2012-2020 + */ + +#ifndef HW_LAYER_DRV8860_H_ +#define HW_LAYER_DRV8860_H_ + +#include "efifeatures.h" +#include + +#define DRV8860_OUTPUTS 16 + +/* TODO: add irq support */ +#define DRV8860_POLL_INTERVAL_MS 500 + +struct drv8860_config { + SPIDriver *spi_bus; + SPIConfig spi_config; + struct { + ioportid_t port; + uint_fast8_t pad; + } reset; +}; + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +int drv8860_add(unsigned int index, const struct drv8860_config *cfg); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* HW_LAYER_DRV8860_H_ */ From 63eb179ddf4498afca1666c8fe9c9f62aac38018 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 12:08:36 -0400 Subject: [PATCH 06/12] Hellen says efifeatures --- firmware/config/stm32f4ems/efifeatures.h | 15 ++++++++++++++- firmware/config/stm32f7ems/efifeatures.h | 6 +++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/firmware/config/stm32f4ems/efifeatures.h b/firmware/config/stm32f4ems/efifeatures.h index 88c18d35c9..32713327c5 100644 --- a/firmware/config/stm32f4ems/efifeatures.h +++ b/firmware/config/stm32f4ems/efifeatures.h @@ -69,6 +69,10 @@ #define HAL_TRIGGER_USE_PAL FALSE #endif /* HAL_TRIGGER_USE_PAL */ +#ifndef HAL_TRIGGER_USE_ADC +#define HAL_TRIGGER_USE_ADC FALSE +#endif /* HAL_TRIGGER_USE_ADC */ + /** * TunerStudio support. */ @@ -144,8 +148,12 @@ #define BOARD_TLE8888_COUNT 1 #endif +#ifndef BOARD_DRV8860_COUNT +#define BOARD_DRV8860_COUNT 0 +#endif + // todo: move this outside of efifeatures.h -#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT) +#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT + BOARD_DRV8860_COUNT) // todo: move this outside of efifeatures.h #define BOARD_EXT_PINREPOPINS 24 @@ -242,6 +250,8 @@ #define EFI_USB_SERIAL TRUE #endif +#define EFI_CONSOLE_USB_DEVICE (&SDU1) + /** * While we embed multiple PnP configurations into the same firmware binary, these marcoses give us control * over which configurations go into the binary @@ -381,6 +391,9 @@ #ifndef LED_ERROR_BRAIN_PIN #define LED_ERROR_BRAIN_PIN GPIOD_14 #endif +#ifndef LED_ERROR_BRAIN_PIN_MODE +#define LED_ERROR_BRAIN_PIN_MODE DEFAULT_OUTPUT +#endif // USART1 -> check defined STM32_SERIAL_USE_USART1 // For GPS we have USART1. We can start with PB7 USART1_RX and PB6 USART1_TX diff --git a/firmware/config/stm32f7ems/efifeatures.h b/firmware/config/stm32f7ems/efifeatures.h index dcfeacf284..a66f52edee 100644 --- a/firmware/config/stm32f7ems/efifeatures.h +++ b/firmware/config/stm32f7ems/efifeatures.h @@ -49,8 +49,12 @@ #define BOARD_TLE8888_COUNT 1 #endif +#ifndef BOARD_DRV8860_COUNT +#define BOARD_DRV8860_COUNT 0 +#endif + // todo: move this outside of efifeatures.h -#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT) +#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT + BOARD_DRV8860_COUNT) #undef EFI_CAN_SUPPORT From 47c98370e09c103c31d5683070d456de279926f3 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 12:09:39 -0400 Subject: [PATCH 07/12] Hellen says simulator --- simulator/Makefile | 2 ++ simulator/simulator/efifeatures.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/simulator/Makefile b/simulator/Makefile index 50a11c8764..cacb76b934 100644 --- a/simulator/Makefile +++ b/simulator/Makefile @@ -20,6 +20,8 @@ RULESFILE = $(RULESPATH)/rules.mk include ../firmware/rusefi.mk RULESFILE = ../firmware/rusefi_rules.mk +# used by USE_SMART_BUILD +CONFDIR = . # Compiler options here. diff --git a/simulator/simulator/efifeatures.h b/simulator/simulator/efifeatures.h index d1499e4d3f..7b1117b896 100644 --- a/simulator/simulator/efifeatures.h +++ b/simulator/simulator/efifeatures.h @@ -106,6 +106,10 @@ #define HAL_TRIGGER_USE_PAL FALSE #endif /* HAL_TRIGGER_USE_PAL */ +#ifndef HAL_TRIGGER_USE_ADC +#define HAL_TRIGGER_USE_ADC FALSE +#endif /* HAL_TRIGGER_USE_ADC */ + #define EFI_UART_GPS FALSE #define EFI_HAS_RESET FALSE #define EXTREME_TERM_LOGGING FALSE From 4e341dfa99914b523e8ed64d89ef37f0f367f929 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 12:10:39 -0400 Subject: [PATCH 08/12] Hellen says serial can --- firmware/console/binary/serial_can.cpp | 268 +++++++++++++++++++++++++ firmware/console/binary/serial_can.h | 67 +++++++ 2 files changed, 335 insertions(+) create mode 100644 firmware/console/binary/serial_can.cpp create mode 100644 firmware/console/binary/serial_can.h diff --git a/firmware/console/binary/serial_can.cpp b/firmware/console/binary/serial_can.cpp new file mode 100644 index 0000000000..3d637c958d --- /dev/null +++ b/firmware/console/binary/serial_can.cpp @@ -0,0 +1,268 @@ +/** + * @file serial_can.cpp + * + * This code is a bridge between a serial streaming used by TS and a packet-frame CAN-bus, using the ISO-TP protocol. + * ISO 15765-2, or ISO-TP (Transport Layer), which is an international standard for sending data packets over a CAN-Bus. + * https://en.wikipedia.org/wiki/ISO_15765-2 + * + * @date Aug 1, 2020 + * @author andreika + * @author Andrey Belomutskiy, (c) 2012-2020 + */ + +#include "global.h" +#include "os_access.h" + +#include "serial_can.h" + + +static CanStreamerState state; + +int CanStreamerState::sendFrame(CANDriver *canp, const IsoTpFrameHeader & header, const uint8_t *data, int num) { + CANTxFrame txmsg; + memset(&txmsg, 0, sizeof(txmsg)); + txmsg.IDE = CAN_IDE_STD; + txmsg.EID = CAN_TX_ID; + txmsg.RTR = CAN_RTR_DATA; + txmsg.DLC = 8; // 8 bytes + + // fill the frame data according to the CAN-TP protocol (ISO 15765-2) + txmsg.data8[0] = (uint8_t)((header.frameType & 0xf) << 4); + int offset, maxNumBytes; + switch (header.frameType) { + case ISO_TP_FRAME_SINGLE: + offset = 1; + maxNumBytes = minI(header.numBytes, txmsg.DLC - offset); + txmsg.data8[0] |= maxNumBytes; + break; + case ISO_TP_FRAME_FIRST: + txmsg.data8[0] |= (header.numBytes >> 8) & 0xf; + txmsg.data8[1] = (uint8_t)(header.numBytes & 0xff); + offset = 2; + maxNumBytes = minI(header.numBytes, txmsg.DLC - offset); + break; + case ISO_TP_FRAME_CONSECUTIVE: + txmsg.data8[0] |= header.index & 0xf; + offset = 1; + maxNumBytes = txmsg.DLC - offset; + break; + case ISO_TP_FRAME_FLOW_CONTROL: + txmsg.data8[0] |= header.fcFlag & 0xf; + txmsg.data8[1] = (uint8_t)(header.blockSize); + txmsg.data8[2] = (uint8_t)(header.separationTime); + offset = 3; + maxNumBytes = 0; // no data is sent with 'flow control' frame + break; + } + + int numBytes = minI(maxNumBytes, num); + // copy the contents + if (data != nullptr) { + for (int i = 0; i < numBytes; i++) { + txmsg.data8[i + offset] = data[i]; + } + } + + // send the frame! + if (canTransmit(&CAND1, CAN_ANY_MAILBOX, &txmsg, TIME_MS2I(100)) == MSG_OK) + return numBytes; + return 0; +} + +// returns the number of copied bytes +int CanStreamerState::receiveFrame(CANDriver *canp, CANRxFrame *rxmsg, uint8_t *buf, int num) { + if (rxmsg == nullptr || rxmsg->DLC < 1) + return 0; + int frameType = (rxmsg->data8[0] >> 4) & 0xf; + int numBytesAvailable, frameIdx; + uint8_t *srcBuf = rxmsg->data8; + switch (frameType) { + case ISO_TP_FRAME_SINGLE: + numBytesAvailable = rxmsg->data8[0] & 0xf; + srcBuf = rxmsg->data8 + 1; + this->waitingForNumBytes = -1; + break; + case ISO_TP_FRAME_FIRST: + this->waitingForNumBytes = ((rxmsg->data8[0] & 0xf) << 8) | rxmsg->data8[1]; + this->waitingForFrameIndex = 1; + numBytesAvailable = minI(this->waitingForNumBytes, 6); + srcBuf = rxmsg->data8 + 2; + break; + case ISO_TP_FRAME_CONSECUTIVE: + frameIdx = rxmsg->data8[0] & 0xf; + if (this->waitingForNumBytes < 0 || this->waitingForFrameIndex != frameIdx) { + // todo: that's an abnormal situation, and we probably should react? + return 0; + } + numBytesAvailable = minI(this->waitingForNumBytes, 7); + srcBuf = rxmsg->data8 + 1; + this->waitingForFrameIndex = (this->waitingForFrameIndex + 1) & 0xf; + break; + case ISO_TP_FRAME_FLOW_CONTROL: + // todo: currently we just ignore the FC frame + return 0; + } + +#if defined(TS_CAN_DEVICE_SHORT_PACKETS_IN_ONE_FRAME) + if (frameType == ISO_TP_FRAME_SINGLE) { + srcBuf = state.tmpRxBuf; + // restore the CRC on the whole packet + uint32_t crc = crc32((void *) (rxmsg->data + 1), numBytesAvailable); + // we need a separate buffer for crc because srcBuf may not be word-aligned for direct copy + uint8_t crcBuffer[sizeof(uint32_t)]; + *(uint32_t *) (crcBuffer) = SWAP_UINT32(crc); + + // now set the packet size (including the command byte) + *(uint16_t *) srcBuf = SWAP_UINT16(numBytesAvailable); + // copy the data + if (numBytesAvailable > 0) + memcpy(srcBuf + 2, rxmsg->data8 + 1, numBytesAvailable); + // copy the crc + memcpy(srcBuf + 2 + numBytesAvailable, crcBuffer, sizeof(crcBuffer)); + numBytesAvailable += 1 + sizeof(crcBuffer); // added command & crc bytes + } +#endif /* TS_CAN_DEVICE_SHORT_PACKETS_IN_ONE_FRAME */ + + int numBytesToCopy = minI(num, numBytesAvailable); + if (buf != nullptr) { + memcpy(buf, srcBuf, numBytesToCopy); + } + srcBuf += numBytesToCopy; + numBytesAvailable -= numBytesToCopy; + waitingForNumBytes -= numBytesToCopy; + // if there are some more bytes left, we save them for the next time + for (int i = 0; i < numBytesAvailable; i++) { + rxFifoBuf.put(srcBuf[i]); + } + + // according to the specs, we need to acknowledge the received multi-frame start frame + if (frameType == ISO_TP_FRAME_FIRST) { + IsoTpFrameHeader header; + header.frameType = ISO_TP_FRAME_FLOW_CONTROL; + header.fcFlag = 0; // = "continue to send" + header.blockSize = 0; // = the remaining "frames" to be sent without flow control or delay + header.separationTime = 0; // = wait 0 milliseconds, send immediately + sendFrame(canp, header, nullptr, 0); + } + + return numBytesToCopy; +} + +int CanStreamerState::sendDataTimeout(CANDriver *canp, const uint8_t *txbuf, int numBytes, sysinterval_t timeout) { + + int offset = 0; + msg_t ret; + // 1 frame + if (numBytes <= 7) { + IsoTpFrameHeader header; + header.frameType = ISO_TP_FRAME_SINGLE; + header.numBytes = numBytes; + return state.sendFrame(canp, header, txbuf, numBytes); + } + + // multiple frames + + // send the first header frame + IsoTpFrameHeader header; + header.frameType = ISO_TP_FRAME_FIRST; + header.numBytes = numBytes; + int numSent = state.sendFrame(canp, header, txbuf + offset, numBytes); + offset += numSent; + numBytes -= numSent; + int totalNumSent = numSent; + + // get a flow control frame + CANRxFrame rxmsg; + if (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, timeout) == MSG_OK) { + state.receiveFrame(canp, &rxmsg, nullptr, 0); + } + + // send the rest of the data + int idx = 1; + while (numBytes > 0) { + int len = minI(numBytes, 7); + // send the consecutive frames + IsoTpFrameHeader header; + header.frameType = ISO_TP_FRAME_CONSECUTIVE; + header.index = ((idx++) & 0x0f); + header.numBytes = numBytes; + int numSent = state.sendFrame(canp, header, txbuf + offset, numBytes); + if (numSent < 1) + break; + totalNumSent += numSent; + offset += numSent; + numBytes -= numSent; + } + return totalNumSent; +} + +int CanStreamerState::getDataFromFifo(uint8_t *rxbuf, size_t &numBytes) { + if (rxFifoBuf.isEmpty()) + return 0; + int numReadFromFifo = minI(numBytes, rxFifoBuf.getCount()); + // move bytes from the FIFO buffer + int i; + for (i = 0; !rxFifoBuf.isEmpty() && i < numReadFromFifo; i++) { + rxbuf[i] = rxFifoBuf.get(); + numBytes--; + } + return i; +} + +void canInit(CANDriver *canp) { + chEvtRegister(&CAND1.rxfull_event, &state.el, 0); +} + +msg_t canAddToTxStreamTimeout(CANDriver *canp, size_t *np, + const uint8_t *txbuf, sysinterval_t timeout) { + int numBytes = *np; + int offset = 0; + int minNumBytesRequiredToSend = 7 - state.txFifoBuf.getCount(); + while (numBytes >= minNumBytesRequiredToSend) { + state.txFifoBuf.put(txbuf + offset, minNumBytesRequiredToSend); + int numSent = state.sendDataTimeout(canp, (const uint8_t *)state.txFifoBuf.elements, state.txFifoBuf.getCount(), timeout); + if (numSent < 1) + break; + state.txFifoBuf.clear(); + offset += numSent; + numBytes -= numSent; + minNumBytesRequiredToSend = 7; + } + + // now we put the rest on hold + state.txFifoBuf.put(txbuf + offset, numBytes); + + return MSG_OK; +} + +msg_t canFlushTxStream(CANDriver *canp, sysinterval_t timeout) { + int numSent = state.sendDataTimeout(canp, (const uint8_t *)state.txFifoBuf.elements, state.txFifoBuf.getCount(), timeout); + state.txFifoBuf.clear(); + + return MSG_OK; +} + +msg_t canStreamReceiveTimeout(CANDriver *canp, size_t *np, + uint8_t *rxbuf, sysinterval_t timeout) { + int i = 0; + size_t numBytes = *np; + + // first, fill the data from the stored buffer (saved from the previous CAN frame) + i = state.getDataFromFifo(rxbuf, numBytes); + + // if even more data is needed, then we receive more CAN frames + while (numBytes > 0) { + if (chEvtWaitAnyTimeout(ALL_EVENTS, timeout) == 0) + return MSG_TIMEOUT; + CANRxFrame rxmsg; + if (canReceive(&CAND1, CAN_ANY_MAILBOX, &rxmsg, TIME_IMMEDIATE) == MSG_OK) { + int numReceived = state.receiveFrame(canp, &rxmsg, rxbuf + i, numBytes); + if (numReceived < 1) + break; + numBytes -= numReceived; + } + } + //*np -= numBytes; + return MSG_OK; +} + diff --git a/firmware/console/binary/serial_can.h b/firmware/console/binary/serial_can.h new file mode 100644 index 0000000000..e9ff258c9f --- /dev/null +++ b/firmware/console/binary/serial_can.h @@ -0,0 +1,67 @@ +/** + * @file serial_can.h + * + * @date Aug 1, 2020 + * @author andreika + * @author Andrey Belomutskiy, (c) 2012-2020 + */ + +#pragma once + +#include "fifo_buffer.h" + +#define CAN_TX_ID 0x102 + +enum IsoTpFrameType { + ISO_TP_FRAME_SINGLE = 0, + ISO_TP_FRAME_FIRST = 1, + ISO_TP_FRAME_CONSECUTIVE = 2, + ISO_TP_FRAME_FLOW_CONTROL = 3, +}; + +class IsoTpFrameHeader { +public: + IsoTpFrameType frameType; + + // used for 'single' or 'first' frames + int numBytes; + // used for 'consecutive' frames + int index; + // used for 'flow control' frames + int fcFlag; + int blockSize; + int separationTime; +}; + +class CanStreamerState { +public: + fifo_buffer rxFifoBuf; + fifo_buffer txFifoBuf; + +#if defined(TS_CAN_DEVICE_SHORT_PACKETS_IN_ONE_FRAME) + // used to restore the original packet with CRC + uint8_t tmpRxBuf[13]; +#endif + + // used for multi-frame ISO-TP packets + int waitingForNumBytes = 0; + int waitingForFrameIndex = 0; + + event_listener_t el; + +public: + int sendFrame(CANDriver *canp, const IsoTpFrameHeader & header, const uint8_t *data, int num); + int receiveFrame(CANDriver *canp, CANRxFrame *rxmsg, uint8_t *buf, int num); + int getDataFromFifo(uint8_t *rxbuf, size_t &numBytes); + // returns the number of bytes sent + int sendDataTimeout(CANDriver *canp, const uint8_t *txbuf, int numBytes, sysinterval_t timeout); +}; + +void canInit(CANDriver *canp); + +// we don't have canStreamSendTimeout() because we need to "bufferize" the stream and send it in fixed-length packets +msg_t canAddToTxStreamTimeout(CANDriver *canp, size_t *np, const uint8_t *txbuf, sysinterval_t timeout); +msg_t canFlushTxStream(CANDriver *canp, sysinterval_t timeout); + +msg_t canStreamReceiveTimeout(CANDriver *canp, size_t *np, uint8_t *rxbuf, sysinterval_t timeout); + From 41b5d5de0605e9e8580539ae4da485351cd0df7a Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 12:24:50 -0400 Subject: [PATCH 09/12] Revert "Hellen says efifeatures" This reverts commit 63eb179d --- firmware/config/stm32f4ems/efifeatures.h | 15 +-------------- firmware/config/stm32f7ems/efifeatures.h | 6 +----- 2 files changed, 2 insertions(+), 19 deletions(-) diff --git a/firmware/config/stm32f4ems/efifeatures.h b/firmware/config/stm32f4ems/efifeatures.h index 32713327c5..88c18d35c9 100644 --- a/firmware/config/stm32f4ems/efifeatures.h +++ b/firmware/config/stm32f4ems/efifeatures.h @@ -69,10 +69,6 @@ #define HAL_TRIGGER_USE_PAL FALSE #endif /* HAL_TRIGGER_USE_PAL */ -#ifndef HAL_TRIGGER_USE_ADC -#define HAL_TRIGGER_USE_ADC FALSE -#endif /* HAL_TRIGGER_USE_ADC */ - /** * TunerStudio support. */ @@ -148,12 +144,8 @@ #define BOARD_TLE8888_COUNT 1 #endif -#ifndef BOARD_DRV8860_COUNT -#define BOARD_DRV8860_COUNT 0 -#endif - // todo: move this outside of efifeatures.h -#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT + BOARD_DRV8860_COUNT) +#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT) // todo: move this outside of efifeatures.h #define BOARD_EXT_PINREPOPINS 24 @@ -250,8 +242,6 @@ #define EFI_USB_SERIAL TRUE #endif -#define EFI_CONSOLE_USB_DEVICE (&SDU1) - /** * While we embed multiple PnP configurations into the same firmware binary, these marcoses give us control * over which configurations go into the binary @@ -391,9 +381,6 @@ #ifndef LED_ERROR_BRAIN_PIN #define LED_ERROR_BRAIN_PIN GPIOD_14 #endif -#ifndef LED_ERROR_BRAIN_PIN_MODE -#define LED_ERROR_BRAIN_PIN_MODE DEFAULT_OUTPUT -#endif // USART1 -> check defined STM32_SERIAL_USE_USART1 // For GPS we have USART1. We can start with PB7 USART1_RX and PB6 USART1_TX diff --git a/firmware/config/stm32f7ems/efifeatures.h b/firmware/config/stm32f7ems/efifeatures.h index a66f52edee..dcfeacf284 100644 --- a/firmware/config/stm32f7ems/efifeatures.h +++ b/firmware/config/stm32f7ems/efifeatures.h @@ -49,12 +49,8 @@ #define BOARD_TLE8888_COUNT 1 #endif -#ifndef BOARD_DRV8860_COUNT -#define BOARD_DRV8860_COUNT 0 -#endif - // todo: move this outside of efifeatures.h -#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT + BOARD_DRV8860_COUNT) +#define BOARD_EXT_GPIOCHIPS (BOARD_TLE6240_COUNT + BOARD_MC33972_COUNT + BOARD_TLE8888_COUNT) #undef EFI_CAN_SUPPORT From a88e142df048e1fca55e29f822593dab9d96a559 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 14:09:00 -0400 Subject: [PATCH 10/12] Hellen says misc (cherry picked from commit 2390c3ae2bbef8f54a876af00fa6a8eeb0754813) --- firmware/hw_layer/microsecond_timer.cpp | 4 +- firmware/hw_layer/trigger_input_adc.cpp | 453 ++++++++++++++++++++++++ 2 files changed, 455 insertions(+), 2 deletions(-) create mode 100644 firmware/hw_layer/trigger_input_adc.cpp diff --git a/firmware/hw_layer/microsecond_timer.cpp b/firmware/hw_layer/microsecond_timer.cpp index 2d8db0d587..409c174096 100644 --- a/firmware/hw_layer/microsecond_timer.cpp +++ b/firmware/hw_layer/microsecond_timer.cpp @@ -179,9 +179,9 @@ static void timerValidationCallback(void *arg) { testSchedulingHappened = true; efitimems_t actualTimeSinceScheduling = (currentTimeMillis() - testSchedulingStart); - + if (absI(actualTimeSinceScheduling - TEST_CALLBACK_DELAY) > TEST_CALLBACK_DELAY * TIMER_PRECISION_THRESHOLD) { - firmwareError(CUSTOM_ERR_TIMER_TEST_CALLBACK_WRONG_TIME, "hwTimer broken precision"); + firmwareError(CUSTOM_ERR_TIMER_TEST_CALLBACK_WRONG_TIME, "hwTimer broken precision: %ld ms", actualTimeSinceScheduling); } } diff --git a/firmware/hw_layer/trigger_input_adc.cpp b/firmware/hw_layer/trigger_input_adc.cpp new file mode 100644 index 0000000000..fac3b01ad7 --- /dev/null +++ b/firmware/hw_layer/trigger_input_adc.cpp @@ -0,0 +1,453 @@ +/** + * @file trigger_input_adc.cpp + * @brief Position sensor hardware layer, Using ADC and software comparator + * + * @date Jan 27, 2020 + * @author andreika + * @author Andrey Belomutskiy, (c) 2012-2020 + */ + +#include "global.h" + +#if (EFI_SHAFT_POSITION_INPUT && HAL_TRIGGER_USE_ADC && HAL_USE_ADC) || defined(__DOXYGEN__) + +#include "trigger_input.h" +#include "digital_input_exti.h" +#include "adc_inputs.h" + +//!!!!!!!!!!!!!!! +extern "C" void toggleLed(int led, int mode); +#define BOARD_MOD1_PORT GPIOD +#define BOARD_MOD1_PIN 5 + + +extern bool hasFirmwareErrorFlag; + +EXTERN_ENGINE +; +static Logging *logger; + +#if 0 +static volatile int centeredDacValue = 127; +static volatile int toothCnt = 0; +static volatile int dacHysteresisMin = 1; // = 5V * 1/256 (8-bit DAC) = ~20mV +static volatile int dacHysteresisMax = 15; // = ~300mV +static volatile int dacHysteresisDelta = dacHysteresisMin; +static volatile int hystUpdatePeriodNumEvents = 116; // every ~1 turn of 60-2 wheel +static volatile efitick_t prevNt = 0; +// VR-sensor saturation stuff +static volatile float curVrFreqNt = 0, saturatedVrFreqNt = 0; +#endif + +static const adcsample_t adcDefaultThreshold = (ADC_MAX_VALUE / 2); +static const adcsample_t adcMinThreshold = adcDefaultThreshold - 200; +static const adcsample_t adcMaxThreshold = adcDefaultThreshold + 200; + +static float triggerAdcITermCoef = 1600.0f; +static float triggerAdcITermMin = 3.125e-8f; // corresponds to rpm=25 + +static int transitionCooldown = 5; + +#define DELTA_THRESHOLD_CNT_LOW (GPT_FREQ_FAST / GPT_PERIOD_FAST / 32) // ~1/32 second? +#define DELTA_THRESHOLD_CNT_HIGH (GPT_FREQ_FAST / GPT_PERIOD_FAST / 4) // ~1/4 second? + +/*static */triggerAdcMode_t curAdcMode = TRIGGER_NONE; +/*static*/ float adcThreshold = adcDefaultThreshold; +static float triggerAdcITerm = triggerAdcITermMin; +// these thresholds allow to switch from ADC mode (low-rpm) to EXTI mode (fast-rpm), indicating the clamping of the signal +static adcsample_t switchingThresholdLow = 0, switchingThresholdHigh = 0; +static efitick_t minDeltaTimeForStableAdcDetectionNt = 0; +static efitick_t stampCorrectionForAdc = 0; +static int switchingCnt = 0, switchingTeethCnt = 0; +static int prevValue = 0; // not set +static efitick_t prevStamp = 0; +// we need to distinguish between weak and strong signals because of different SNR and thresholds. +static bool isSignalWeak = true; +static int zeroThreshold = 0; +// the 'center' of the signal is variable, so we need to adjust the thresholds. +static int minDeltaThresholdWeakSignal = 0, minDeltaThresholdStrongSignal = 0; +// this is the number of measurements while we store the counter before we reset to 'isSignalWeak' +static int minDeltaThresholdCntPos = 0, minDeltaThresholdCntNeg = 0; +static int integralSum = 0; +static int transitionCooldownCnt = 0; + +// used for fast pin mode switching between ADC and EXTINT +static ioportid_t triggerInputPort; +static ioportmask_t triggerInputPin; + + +#if 0 +// We want to interpolate between min and max depending on the signal level (adaptive hysteresis). +// But we don't want to measure the signal amplitude directly, so we estimate it by measuring the signal frequency: +// for VR sensors, the amplitude is inversely proportional to the tooth's 'time-width'. +// We find it by dividing the total time by the teeth count, and use the reciprocal value as signal frequency! +static void setHysteresis(int sign) { + // update the hysteresis threshold, but not for every tooth +#ifdef EFI_TRIGGER_COMP_ADAPTIVE_HYSTERESIS + if (toothCnt++ > hystUpdatePeriodNumEvents) { + efitick_t nowNt = getTimeNowNt(); + curVrFreqNt = (float)toothCnt / (float)(nowNt - prevNt); + dacHysteresisDelta = (int)efiRound(interpolateClamped(0.0f, dacHysteresisMin, saturatedVrFreqNt, dacHysteresisMax, curVrFreqNt), 1.0f); + toothCnt = 0; + prevNt = nowNt; +#ifdef TRIGGER_COMP_EXTREME_LOGGING + scheduleMsg(logger, "* f=%f d=%d", curVrFreqNt * 1000.0f, dacHysteresisDelta); +#endif /* TRIGGER_COMP_EXTREME_LOGGING */ + } +#endif /* EFI_TRIGGER_COMP_ADAPTIVE_HYSTERESIS */ + + //comp_lld_set_dac_value(comp, centeredDacValue + dacHysteresisDelta * sign); +} +#endif + +static void setTriggerAdcMode(triggerAdcMode_t adcMode) { + palSetPadMode(triggerInputPort, triggerInputPin, + (adcMode == TRIGGER_ADC) ? PAL_MODE_INPUT_ANALOG : PAL_MODE_ALTERNATE(PAL_MODE_ALTERNATIVE_EXTINT)); + curAdcMode = adcMode; +} + +static void onTriggerChanged(efitick_t stamp, bool isPrimary, bool isRising) { + //!!!!!!!!! + palWritePad(BOARD_MOD1_PORT, BOARD_MOD1_PIN, isRising ? 1 : 0); + + //toggleLed(2, (curAdcMode == TRIGGER_ADC) ? 0 : -1); + //toggleLed(3, (curAdcMode == TRIGGER_EXTI) ? 0 : -1); + +#if 1 + // todo: support for 3rd trigger input channel + // todo: start using real event time from HW event, not just software timer? + if (hasFirmwareErrorFlag) + return; + + if (!isPrimary && !TRIGGER_WAVEFORM(needSecondTriggerInput)) { + return; + } + trigger_event_e signal; + if (isRising) { + signal = isPrimary ? (engineConfiguration->invertPrimaryTriggerSignal ? SHAFT_PRIMARY_FALLING : SHAFT_PRIMARY_RISING) : + (engineConfiguration->invertSecondaryTriggerSignal ? SHAFT_SECONDARY_FALLING : SHAFT_SECONDARY_RISING); + } + else { + signal = isPrimary ? (engineConfiguration->invertPrimaryTriggerSignal ? SHAFT_PRIMARY_RISING : SHAFT_PRIMARY_FALLING) : + (engineConfiguration->invertSecondaryTriggerSignal ? SHAFT_SECONDARY_RISING : SHAFT_SECONDARY_FALLING); + } + // call the main trigger handler + hwHandleShaftSignal(signal, stamp); +#endif +} + + +static void shaft_callback(void *arg) { + if (curAdcMode != TRIGGER_EXTI) { + return; + } + + // do the time sensitive things as early as possible! + efitick_t stamp = getTimeNowNt(); + ioline_t pal_line = (ioline_t)arg; + bool rise = (palReadLine(pal_line) == PAL_HIGH); + + onTriggerChanged(stamp, true, rise); + + if ((stamp - prevStamp) > minDeltaTimeForStableAdcDetectionNt) { + switchingCnt++; + } else { + switchingCnt = 0; + switchingTeethCnt = 0; + } + + if (switchingCnt > 4) { + switchingCnt = 0; + // we need at least 3 wide teeth to be certain! + // we don't want to confuse them with a sync.gap + if (switchingTeethCnt++ > 3) { + switchingTeethCnt = 0; + prevValue = rise ? 1: -1; + setTriggerAdcMode(TRIGGER_ADC); + } + } + + prevStamp = stamp; +} + +static void cam_callback(void *) { +} + +// todo: add cam support? +#if 0 +static void comp_cam_callback(COMPDriver *comp) { + efitick_t stamp = getTimeNowNt(); + + if (isRising) { + hwHandleVvtCamSignal(TV_RISE, stamp); + } else { + hwHandleVvtCamSignal(TV_FALL, stamp); + } +} +#endif + +void turnOnTriggerInputPins(Logging *sharedLogger) { + logger = sharedLogger; + + applyNewTriggerInputPins(); +} + +#if 0 +static int getDacValue(uint8_t voltage DECLARE_ENGINE_PARAMETER_SUFFIX) { + constexpr float maxDacValue = 255.0f; // 8-bit DAC + return (int)efiRound(maxDacValue * (float)voltage * VOLTAGE_1_BYTE_PACKING_DIV / CONFIG(adcVcc), 1.0f); +} +#endif + +static void resetTriggerDetector() { + // todo: move some of these to config + + // we need to make at least minNumAdcMeasurementsPerTooth for 1 tooth (i.e. between two consequent events) + const int minNumAdcMeasurementsPerTooth = 20; + minDeltaTimeForStableAdcDetectionNt = US2NT(US_PER_SECOND_LL * minNumAdcMeasurementsPerTooth * GPT_PERIOD_FAST / GPT_FREQ_FAST); + // we assume that the transition occurs somewhere in the middle of the measurement period, so we take the half of it + stampCorrectionForAdc = US2NT(US_PER_SECOND_LL * GPT_PERIOD_FAST / GPT_FREQ_FAST / 2); + // these thresholds allow to switch from ADC mode to EXTI mode, indicating the clamping of the signal + switchingThresholdLow = voltsToAdc(1.0f); + switchingThresholdHigh = voltsToAdc(4.0f); + switchingCnt = 0; + switchingTeethCnt = 0; + // used to filter out low signals + minDeltaThresholdWeakSignal = voltsToAdc(0.05f); // 50mV + // we need to shift the default threshold even for strong signals because of the possible loss of the first tooth (after the sync) + minDeltaThresholdStrongSignal = voltsToAdc(0.04f); // 5mV + // when the strong signal becomes weak, we want to ignore the increased noise + // so we create a dead-zone between the pos. and neg. thresholds + zeroThreshold = minDeltaThresholdWeakSignal / 2; + triggerAdcITerm = triggerAdcITermMin; + adcThreshold = adcDefaultThreshold; + isSignalWeak = true; + integralSum = 0; + transitionCooldownCnt = 0; + prevValue = 0; // not set + prevStamp = 0; + minDeltaThresholdCntPos = 0; + minDeltaThresholdCntNeg = 0; +} + +static int turnOnTriggerInputPin(const char *msg, int index, bool isTriggerShaft) { + brain_pin_e brainPin = isTriggerShaft ? + CONFIG(triggerInputPins)[index] : engineConfiguration->camInputs[index]; + + if (brainPin == GPIO_UNASSIGNED) + return 0; +#if 0 + centeredDacValue = getDacValue(CONFIG(triggerCompCenterVolt) PASS_ENGINE_PARAMETER_SUFFIX); // usually 2.5V resistor divider + + dacHysteresisMin = getDacValue(CONFIG(triggerCompHystMin) PASS_ENGINE_PARAMETER_SUFFIX); // usually ~20mV + dacHysteresisMax = getDacValue(CONFIG(triggerCompHystMax) PASS_ENGINE_PARAMETER_SUFFIX); // usually ~300mV + dacHysteresisDelta = dacHysteresisMin; + + // 20 rpm (60_2) = 1000*60/((2*60)*20) = 25 ms for 1 tooth event + float satRpm = CONFIG(triggerCompSensorSatRpm) * RPM_1_BYTE_PACKING_MULT; + hystUpdatePeriodNumEvents = ENGINE(triggerCentral.triggerShape).getSize(); // = 116 for "60-2" trigger wheel + float saturatedToothDurationUs = 60.0f * US_PER_SECOND_F / satRpm / hystUpdatePeriodNumEvents; + saturatedVrFreqNt = 1.0f / US2NT(saturatedToothDurationUs); + + scheduleMsg(logger, "startTIPins(): cDac=%d hystMin=%d hystMax=%d satRpm=%.0f satFreq*1k=%f period=%d", + centeredDacValue, dacHysteresisMin, dacHysteresisMax, satRpm, saturatedVrFreqNt * 1000.0f, hystUpdatePeriodNumEvents); +#endif + + resetTriggerDetector(); + + triggerInputPort = getHwPort("trg", brainPin); + triggerInputPin = getHwPin("trg", brainPin); + + ioline_t pal_line = PAL_LINE(triggerInputPort, triggerInputPin); + scheduleMsg(logger, "turnOnTriggerInputPin %s l=%d", hwPortname(brainPin), pal_line); + + efiExtiEnablePin(msg, brainPin, PAL_EVENT_MODE_BOTH_EDGES, isTriggerShaft ? shaft_callback : cam_callback, (void *)pal_line); + + // ADC mode is default, because we don't know if the wheel is already spinning + setTriggerAdcMode(TRIGGER_ADC); + + return 0; +} + +void startTriggerInputPins(void) { + for (int i = 0; i < TRIGGER_SUPPORTED_CHANNELS; i++) { + if (isConfigurationChanged(triggerInputPins[i])) { + const char * msg = (i == 0 ? "trigger#1" : (i == 1 ? "trigger#2" : "trigger#3")); + turnOnTriggerInputPin(msg, i, true); + } + } +} + + +void stopTriggerInputPins(void) { + scheduleMsg(logger, "stopTIPins();"); + +#if 0 + for (int i = 0; i < TRIGGER_SUPPORTED_CHANNELS; i++) { + if (isConfigurationChanged(bc.triggerInputPins[i])) { + turnOffTriggerInputPin(activeConfiguration.bc.triggerInputPins[i]); + } + } + if (isConfigurationChanged(camInput)) { + turnOffTriggerInputPin(activeConfiguration.camInput); + } +#endif +} + +adc_channel_e getAdcChannelForTrigger(void) { + // todo: add other trigger or cam channels? + brain_pin_e brainPin = CONFIG(triggerInputPins)[0]; + if (brainPin == GPIO_UNASSIGNED) + return EFI_ADC_NONE; + return getAdcChannel(brainPin); +} + +void addAdcChannelForTrigger(void) { + adc_channel_e ch = getAdcChannelForTrigger(); + if (ch != EFI_ADC_NONE) { + addChannel("TRIG", ch, ADC_FAST); + } +} + +void triggerAdcCallback(adcsample_t value) { + if (curAdcMode != TRIGGER_ADC) { + return; + } + + efitick_t stamp = getTimeNowNt(); + + // <1V or >4V? + if (value >= switchingThresholdHigh || value <= switchingThresholdLow) { + switchingCnt++; + } else { + switchingCnt = 0; + switchingTeethCnt = 0; + } + + int delta = value - adcThreshold; + int aDelta = absI(delta); + if (isSignalWeak) { + // todo: detect if the sensor is disconnected (where the signal is always near 'ADC_MAX_VALUE') + + // filter out low signals (noise) + if (delta >= minDeltaThresholdWeakSignal) { + minDeltaThresholdCntPos++; + } + if (delta <= -minDeltaThresholdWeakSignal) { + minDeltaThresholdCntNeg++; + } + } else { + // we just had a strong signal, let's reset the counter + if (delta >= minDeltaThresholdWeakSignal) { + minDeltaThresholdCntPos = DELTA_THRESHOLD_CNT_HIGH; + } + if (delta <= -minDeltaThresholdWeakSignal) { + minDeltaThresholdCntNeg = DELTA_THRESHOLD_CNT_HIGH; + } + minDeltaThresholdCntPos--; + minDeltaThresholdCntNeg--; + // we haven't seen the strong signal (pos or neg) for too long, maybe it's lost or too weak? + if (minDeltaThresholdCntPos <= 0 || minDeltaThresholdCntNeg <= 0) { + // reset to the weak signal mode + resetTriggerDetector(); + return; + } + } + + // the threshold should always correspond to the averaged signal. + integralSum += delta; + // we need some limits for the integral sum + // we use a simple I-regulator to move the threshold + adcThreshold += (float)integralSum * triggerAdcITerm; + // limit the threshold for safety + adcThreshold = maxF(minF(adcThreshold, adcMaxThreshold), adcMinThreshold); + + // now to the transition part... First, we need a cooldown to pre-filter the transition noise + if (transitionCooldownCnt-- < 0) + transitionCooldownCnt = 0; + + // we need at least 2 different measurements to detect a transition + if (prevValue == 0) { + // we can take the measurement only from outside the dead-zone + if (aDelta > minDeltaThresholdWeakSignal) { + prevValue = (delta > 0) ? 1 : -1; + } else { + return; + } + } + + // detect the edge + int transition = 0; + if (delta > zeroThreshold && prevValue == -1) { + // a rising transition found! + transition = 1; + } + else if (delta <= -zeroThreshold && prevValue == 1) { + // a falling transition found! + transition = -1; + } + else { + //!!!!!!!!!! + toggleLed(2, 0); + + return; // both are positive/negative/zero: not interested! + } + + //!!!!!!!!!! + toggleLed(2, -1); + //!!!!!!!!!! + toggleLed(3, 0); + + if (isSignalWeak) { + if (minDeltaThresholdCntPos >= DELTA_THRESHOLD_CNT_LOW && minDeltaThresholdCntNeg >= DELTA_THRESHOLD_CNT_LOW) { + // ok, now we have a legit strong signal, let's restore the threshold + isSignalWeak = false; + integralSum = 0; + zeroThreshold = minDeltaThresholdStrongSignal; + } else { + // we cannot trust the weak signal! + return; + } + } + + if (transitionCooldownCnt <= 0) { + onTriggerChanged(stamp - stampCorrectionForAdc, true, transition == 1); + // let's skip some nearest possible measurements: + // the transition cannot be SO fast, but the jitter can! + transitionCooldownCnt = transitionCooldown; + + // it should not accumulate too much + integralSum = 0; + + // update triggerAdcITerm + efitime_t deltaTimeUs = NT2US(stamp - prevStamp); + if (deltaTimeUs > 200) { // 200 us = ~2500 RPM (we don't need this correction for large RPM) + triggerAdcITerm = 1.0f / (triggerAdcITermCoef * deltaTimeUs); + triggerAdcITerm = maxF(triggerAdcITerm, triggerAdcITermMin); + } + } + + if (switchingCnt > 4) { + switchingCnt = 0; + // we need at least 3 high-signal teeth to be certain! + if (switchingTeethCnt++ > 3) { + switchingTeethCnt = 0; + setTriggerAdcMode(TRIGGER_EXTI); + // we don't want to loose the signal on return + minDeltaThresholdCntPos = DELTA_THRESHOLD_CNT_HIGH; + minDeltaThresholdCntNeg = DELTA_THRESHOLD_CNT_HIGH; + // we want to reset the thresholds on return + zeroThreshold = minDeltaThresholdStrongSignal; + adcThreshold = adcDefaultThreshold; + integralSum = 0; + transitionCooldownCnt = 0; + return; + } + } + + prevValue = transition; + prevStamp = stamp; + +} + +#endif /* EFI_SHAFT_POSITION_INPUT && HAL_TRIGGER_USE_ADC && HAL_USE_ADC */ From ec0d3a8eb23cfad87199464da9ed43bb82058a12 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 14:12:21 -0400 Subject: [PATCH 11/12] Hellen says isIdleMotorBusy (cherry picked from commit b24246791e03f29d334216b6b0ad04e8ec914ac9) --- firmware/controllers/actuators/idle_thread.cpp | 8 ++++++++ firmware/controllers/actuators/idle_thread.h | 1 + 2 files changed, 9 insertions(+) diff --git a/firmware/controllers/actuators/idle_thread.cpp b/firmware/controllers/actuators/idle_thread.cpp index c2c275c040..19e1c29db5 100644 --- a/firmware/controllers/actuators/idle_thread.cpp +++ b/firmware/controllers/actuators/idle_thread.cpp @@ -544,6 +544,14 @@ bool isIdleHardwareRestartNeeded() { } +bool isIdleMotorBusy(DECLARE_ENGINE_PARAMETER_SIGNATURE) { + if (!CONFIG(useStepperIdle)) { + // todo: check other motor types? + return false; + } + return iacMotor.isBusy(); +} + void stopIdleHardware(DECLARE_ENGINE_PARAMETER_SIGNATURE) { #if EFI_PROD_CODE brain_pin_markUnused(activeConfiguration.stepperEnablePin); diff --git a/firmware/controllers/actuators/idle_thread.h b/firmware/controllers/actuators/idle_thread.h index 9818f65287..fc3c44660e 100644 --- a/firmware/controllers/actuators/idle_thread.h +++ b/firmware/controllers/actuators/idle_thread.h @@ -35,5 +35,6 @@ void setIdleDT(int value); void stopIdleHardware(DECLARE_ENGINE_PARAMETER_SIGNATURE); void initIdleHardware(DECLARE_ENGINE_PARAMETER_SIGNATURE); bool isIdleHardwareRestartNeeded(); +bool isIdleMotorBusy(DECLARE_ENGINE_PARAMETER_SIGNATURE); void onConfigurationChangeIdleCallback(engine_configuration_s *previousConfiguration); From 6a3d2123706a2d8e45dd736f78696d928ee34237 Mon Sep 17 00:00:00 2001 From: rusefi Date: Mon, 7 Sep 2020 14:41:04 -0400 Subject: [PATCH 12/12] Hellen says merge #1772 Hellen says stepper (cherry picked from commit a2f26ac99b66c5cff408abce55a89cc19012e7c0) --- firmware/controllers/algo/engine.cpp | 86 ++++++++++++++++++++++------ firmware/controllers/algo/engine.h | 26 ++++++++- firmware/hw_layer/stepper.cpp | 84 +++++++++++++++++++++------ firmware/hw_layer/stepper.h | 36 ++++++++++-- 4 files changed, 188 insertions(+), 44 deletions(-) diff --git a/firmware/controllers/algo/engine.cpp b/firmware/controllers/algo/engine.cpp index 2d76d49615..54af1d64ab 100644 --- a/firmware/controllers/algo/engine.cpp +++ b/firmware/controllers/algo/engine.cpp @@ -133,7 +133,7 @@ void Engine::periodicSlowCallback(DECLARE_ENGINE_PARAMETER_SIGNATURE) { watchdog(); updateSlowSensors(PASS_ENGINE_PARAMETER_SIGNATURE); - checkShutdown(); + checkShutdown(PASS_ENGINE_PARAMETER_SIGNATURE); #if EFI_FSIO runFsio(PASS_ENGINE_PARAMETER_SIGNATURE); @@ -414,36 +414,83 @@ void Engine::watchdog() { #endif } -void Engine::checkShutdown() { +void Engine::checkShutdown(DECLARE_ENGINE_PARAMETER_SIGNATURE) { #if EFI_MAIN_RELAY_CONTROL - int rpm = rpmCalculator.getRpm(); + // if we are already in the "ignition_on" mode, then do nothing + if (ignitionOnTimeNt > 0) { + return; + } - /** - * Something is weird here: "below 5.0 volts on battery" what is it about? Is this about - * Frankenso powering everything while driver has already turned ignition off? or what is this condition about? - */ - const float vBattThreshold = 5.0f; - if (isValidRpm(rpm) && sensors.vBatt < vBattThreshold && stopEngineRequestTimeNt == 0) { - scheduleStopEngine(); - // todo: add stepper motor parking + // here we are in the shutdown (the ignition is off) or initial mode (after the firmware fresh start) + const efitick_t engineStopWaitTimeoutUs = 500000LL; // 0.5 sec + // in shutdown mode, we need a small cooldown time between the ignition off and on + if (stopEngineRequestTimeNt == 0 || (getTimeNowNt() - stopEngineRequestTimeNt) > US2NT(engineStopWaitTimeoutUs)) { + // if the ignition key is turned on again, + // we cancel the shutdown mode, but only if all shutdown procedures are complete + const float vBattThresholdOn = 8.0f; + if ((sensors.vBatt > vBattThresholdOn) && !isInShutdownMode(PASS_ENGINE_PARAMETER_SIGNATURE)) { + ignitionOnTimeNt = getTimeNowNt(); + stopEngineRequestTimeNt = 0; + scheduleMsg(&engineLogger, "Ingition voltage detected! Cancel the engine shutdown!"); + } } #endif /* EFI_MAIN_RELAY_CONTROL */ } -bool Engine::isInShutdownMode() const { +bool Engine::isInShutdownMode(DECLARE_ENGINE_PARAMETER_SIGNATURE) const { #if EFI_MAIN_RELAY_CONTROL - if (stopEngineRequestTimeNt == 0) // the shutdown procedure is not started + // if we are in "ignition_on" mode and not in shutdown mode + if (stopEngineRequestTimeNt == 0 && ignitionOnTimeNt > 0) { + const float vBattThresholdOff = 5.0f; + // start the shutdown process if the ignition voltage dropped low + if (sensors.vBatt <= vBattThresholdOff) { + scheduleStopEngine(); + } + } + + // we are not in the shutdown mode? + if (stopEngineRequestTimeNt == 0) { return false; - - const efitick_t engineStopWaitTimeoutNt = 5LL * 1000000LL; - // The engine is still spinning! Give it some time to stop (but wait no more than 5 secs) - if (isSpinning && (getTimeNowNt() - stopEngineRequestTimeNt) < US2NT(engineStopWaitTimeoutNt)) + } + + const efitick_t turnOffWaitTimeoutUs = 1LL * 1000000LL; + // We don't want any transients to step in, so we wait at least 1 second whatever happens. + // Also it's good to give the stepper motor some time to start moving to the initial position (or parking) + if ((getTimeNowNt() - stopEngineRequestTimeNt) < US2NT(turnOffWaitTimeoutUs)) + return true; + + const efitick_t engineSpinningWaitTimeoutUs = 5LL * 1000000LL; + // The engine is still spinning! Give it some time to stop (but wait no more than 5 secs) + if (isSpinning && (getTimeNowNt() - stopEngineRequestTimeNt) < US2NT(engineSpinningWaitTimeoutUs)) + return true; + + // The idle motor valve is still moving! Give it some time to park (but wait no more than 10 secs) + // Usually it can move to the initial 'cranking' position or zero 'parking' position. + const efitick_t idleMotorWaitTimeoutUs = 10LL * 1000000LL; + if (isIdleMotorBusy(PASS_ENGINE_PARAMETER_SIGNATURE) && (getTimeNowNt() - stopEngineRequestTimeNt) < US2NT(idleMotorWaitTimeoutUs)) return true; - // todo: add checks for stepper motor parking #endif /* EFI_MAIN_RELAY_CONTROL */ return false; } +bool Engine::isMainRelayEnabled(DECLARE_ENGINE_PARAMETER_SIGNATURE) const { +#if EFI_MAIN_RELAY_CONTROL + return enginePins.mainRelay.getLogicValue(); +#else + // if no main relay control, we assume it's always turned on + return true; +#endif /* EFI_MAIN_RELAY_CONTROL */ +} + + +float Engine::getTimeIgnitionSeconds(void) const { + // return negative if the ignition is turned off + if (ignitionOnTimeNt == 0) + return -1; + float numSeconds = (float)NT2US(getTimeNowNt() - ignitionOnTimeNt) / 1000000.0f; + return numSeconds; +} + injection_mode_e Engine::getCurrentInjectionMode(DECLARE_ENGINE_PARAMETER_SIGNATURE) { return rpmCalculator.isCranking(PASS_ENGINE_PARAMETER_SIGNATURE) ? CONFIG(crankingInjectionMode) : CONFIG(injectionMode); } @@ -487,9 +534,12 @@ void Engine::periodicFastCallback(DECLARE_ENGINE_PARAMETER_SIGNATURE) { } void doScheduleStopEngine(DECLARE_ENGINE_PARAMETER_SIGNATURE) { + scheduleMsg(&engineLogger, "Starting doScheduleStopEngine"); engine->stopEngineRequestTimeNt = getTimeNowNt(); + engine->ignitionOnTimeNt = 0; // let's close injectors or else if these happen to be open right now enginePins.stopPins(); + // todo: initiate stepper motor parking } void action_s::execute() { diff --git a/firmware/controllers/algo/engine.h b/firmware/controllers/algo/engine.h index b11c384c58..bf78699f3a 100644 --- a/firmware/controllers/algo/engine.h +++ b/firmware/controllers/algo/engine.h @@ -173,6 +173,11 @@ public: */ efitick_t stopEngineRequestTimeNt = 0; + /** + * this is needed by getTimeIgnitionSeconds() and checkShutdown() + */ + efitick_t ignitionOnTimeNt = 0; + /** * This counter is incremented every time user adjusts ECU parameters online (either via rusEfi console or other * tuning software) @@ -295,14 +300,29 @@ public: /** * Needed by EFI_MAIN_RELAY_CONTROL to shut down the engine correctly. + * This method cancels shutdown if the ignition voltage is detected. */ - void checkShutdown(); - + void checkShutdown(DECLARE_ENGINE_PARAMETER_SIGNATURE); + /** * Allows to finish some long-term shutdown procedures (stepper motor parking etc.) + Called when the ignition switch is turned off (vBatt is too low). Returns true if some operations are in progress on background. */ - bool isInShutdownMode() const; + bool isInShutdownMode(DECLARE_ENGINE_PARAMETER_SIGNATURE) const; + + /** + * The stepper does not work if the main relay is turned off (it requires +12V). + * Needed by the stepper motor code to detect if it works. + */ + bool isMainRelayEnabled(DECLARE_ENGINE_PARAMETER_SIGNATURE) const; + + /** + * Needed by EFI_MAIN_RELAY_CONTROL to handle fuel pump and shutdown timings correctly. + * This method returns the number of seconds since the ignition voltage is present. + * The return value is float for more FSIO flexibility. + */ + float getTimeIgnitionSeconds(void) const; monitoring_timestamps_s m; diff --git a/firmware/hw_layer/stepper.cpp b/firmware/hw_layer/stepper.cpp index d1bceab345..b955ade7ad 100644 --- a/firmware/hw_layer/stepper.cpp +++ b/firmware/hw_layer/stepper.cpp @@ -21,14 +21,15 @@ EXTERN_ENGINE; static Logging *logger; -static void saveStepperPos(int pos) { +void StepperMotor::saveStepperPos(int pos) { // use backup-power RTC registers to store the data #if EFI_PROD_CODE backupRamSave(BACKUP_STEPPER_POS, pos + 1); #endif + postCurrentPosition(); } -static int loadStepperPos() { +int StepperMotor::loadStepperPos() { #if EFI_PROD_CODE return (int)backupRamLoad(BACKUP_STEPPER_POS) - 1; #else @@ -36,12 +37,24 @@ static int loadStepperPos() { #endif } -void StepperMotor::ThreadTask() { - // Require hardware to be set - if (!m_hw) { - return; +void StepperMotor::changeCurrentPosition(bool positive) { + if (positive) { + m_currentPosition++; + } else { + m_currentPosition--; } + postCurrentPosition(); +} +void StepperMotor::postCurrentPosition(void) { + if (engineConfiguration->debugMode == DBG_IDLE_CONTROL) { +#if EFI_TUNER_STUDIO + tsOutputChannels.debugIntField5 = m_currentPosition; +#endif /* EFI_TUNER_STUDIO */ + } +} + +void StepperMotor::setInitialPosition(void) { // try to get saved stepper position (-1 for no data) m_currentPosition = loadStepperPos(); @@ -49,6 +62,7 @@ void StepperMotor::ThreadTask() { // first wait until at least 1 slowADC sampling is complete waitForSlowAdc(); #endif + #if EFI_SHAFT_POSITION_INPUT bool isRunning = engine->rpmCalculator.isRunning(PASS_ENGINE_PARAMETER_SIGNATURE); #else @@ -61,6 +75,7 @@ void StepperMotor::ThreadTask() { scheduleMsg(logger, "Stepper: savedStepperPos=%d forceStepperParking=%d (tps=%.2f)", m_currentPosition, (forceStepperParking ? 1 : 0), getTPS(PASS_ENGINE_PARAMETER_SIGNATURE)); if (m_currentPosition < 0 || forceStepperParking) { + scheduleMsg(logger, "Stepper: starting parking..."); // reset saved value saveStepperPos(-1); @@ -74,36 +89,58 @@ void StepperMotor::ThreadTask() { */ int numParkingSteps = (int)efiRound((1.0f + (float)CONFIG(stepperParkingExtraSteps) / PERCENT_MULT) * m_totalSteps, 1.0f); for (int i = 0; i < numParkingSteps; i++) { - m_hw->step(false); + if (!m_hw->step(false)) { + initialPositionSet = false; + return; + } + changeCurrentPosition(false); } // set & save zero stepper position after the parking completion m_currentPosition = 0; saveStepperPos(m_currentPosition); + scheduleMsg(logger, "Stepper: parking finished!"); } else { // The initial target position should correspond to the saved stepper position. // Idle thread starts later and sets a new target position. setTargetPosition(m_currentPosition); } + initialPositionSet = true; +} + +void StepperMotor::ThreadTask() { + // Require hardware to be set + if (!m_hw) { + return; + } + while (true) { int targetPosition = getTargetPosition(); int currentPosition = m_currentPosition; + // the stepper does not work if the main relay is turned off (it requires +12V) + if (!engine->isMainRelayEnabled()) { + m_hw->pause(); + continue; + } + + if (!initialPositionSet) { + setInitialPosition(); + continue; + } + if (targetPosition == currentPosition) { m_hw->pause(); continue; } + bool isIncrementing = targetPosition > currentPosition; - if (isIncrementing) { - m_currentPosition++; - } else { - m_currentPosition--; + if (m_hw->step(isIncrementing)) { + changeCurrentPosition(isIncrementing); } - m_hw->step(isIncrementing); - // save position to backup RTC register #if EFI_PROD_CODE saveStepperPos(m_currentPosition); @@ -118,7 +155,14 @@ int StepperMotor::getTargetPosition() const { } void StepperMotor::setTargetPosition(int targetPosition) { - m_targetPosition = targetPosition; + // we accept a new target position only if the motor is powered from the main relay + if (engine->isMainRelayEnabled()) { + m_targetPosition = targetPosition; + } +} + +bool StepperMotor::isBusy() const { + return m_currentPosition != m_targetPosition; } void StepDirectionStepper::setDirection(bool isIncrementing) { @@ -131,7 +175,11 @@ void StepDirectionStepper::setDirection(bool isIncrementing) { directionPin.setValue(isIncrementing); } -void StepDirectionStepper::pulse() { +bool StepDirectionStepper::pulse() { + // we move the motor only of it is powered from the main relay + if (!engine->isMainRelayEnabled()) + return false; + enablePin.setValue(false); // enable stepper stepPin.setValue(true); @@ -141,6 +189,8 @@ void StepDirectionStepper::pulse() { pause(); enablePin.setValue(true); // disable stepper + + return true; } void StepperHw::pause() const { @@ -151,9 +201,9 @@ void StepperHw::setReactionTime(float ms) { m_reactionTime = maxF(1, ms); } -void StepDirectionStepper::step(bool positive) { +bool StepDirectionStepper::step(bool positive) { setDirection(positive); - pulse(); + return pulse(); } void StepperMotor::initialize(StepperHw *hardware, int totalSteps, Logging *sharedLogger) { diff --git a/firmware/hw_layer/stepper.h b/firmware/hw_layer/stepper.h index de4d356367..91ebcffc36 100644 --- a/firmware/hw_layer/stepper.h +++ b/firmware/hw_layer/stepper.h @@ -4,8 +4,8 @@ * @date Dec 24, 2014 * @author Andrey Belomutskiy, (c) 2012-2020 */ -#ifndef STEPPER_H_ -#define STEPPER_H_ + +#pragma once #include "global.h" #include "efi_gpio.h" @@ -14,7 +14,7 @@ class StepperHw { public: - virtual void step(bool positive) = 0; + virtual bool step(bool positive) = 0; void pause() const; protected: @@ -28,10 +28,10 @@ class StepDirectionStepper final : public StepperHw { public: void initialize(brain_pin_e stepPin, brain_pin_e directionPin, pin_output_mode_e directionPinMode, float reactionTime, brain_pin_e enablePin, pin_output_mode_e enablePinMode); - void step(bool positive) override; + bool step(bool positive) override; private: - void pulse(); + bool pulse(); void setDirection(bool isIncrementing); bool m_currentDirection = false; @@ -40,6 +40,21 @@ private: pin_output_mode_e directionPinMode, stepPinMode, enablePinMode; }; +class DcMotor; + +class DualHBridgeStepper final : public StepperHw { +public: + void initialize(DcMotor* motorPhaseA, DcMotor* motorPhaseB, float reactionTime); + + bool step(bool positive) override; + +private: + DcMotor* m_motorPhaseA = nullptr; + DcMotor* m_motorPhaseB = nullptr; + + uint8_t m_phase = 0; +}; + class StepperMotor final : private ThreadController { public: StepperMotor(); @@ -49,16 +64,25 @@ public: void setTargetPosition(int targetPosition); int getTargetPosition() const; + bool isBusy() const; + int m_currentPosition = 0; int m_totalSteps = 0; protected: void ThreadTask() override; + void setInitialPosition(void); + + void saveStepperPos(int pos); + int loadStepperPos(); + + void changeCurrentPosition(bool positive); + void postCurrentPosition(void); private: StepperHw* m_hw = nullptr; int m_targetPosition = 0; + bool initialPositionSet = false; }; -#endif /* STEPPER_H_ */